Arrow
Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
Revision 0:01f31e923fe2, committed 2020-04-07
- Comitter:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Commit message:
- hani: DAPLink with reset workaround
Changed in this revision
diff -r 000000000000 -r 01f31e923fe2 CONTRIBUTING.md --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/CONTRIBUTING.md Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,72 @@ +Contributing +============ + +We appreciate your contributions! Because this is an open source project, we want to keep it as easy +as possible to contribute changes. However, we need contributors to follow a few guidelines. + + +## Requirements + +There are a few architectural requirements that must be followed by contributed changes. + +- Target-specific code is not allowed in common source files. Specifically, this means that you + may not introduce `#ifdefs` for the target or HIC into common code. +- If you need to implement a target-specific feature that would require changes to common code, you + must first add a hook mechanism to the common code that allows your target-specific feature to + be implemented outside the common code (in a family or board source file). +- DAPLink makes extensive use of weak function and variable definitions as hooks to allow + target-specific builds to change behaviour. This is the preferred hook mechanism. +- Another option is to use a macro defined in the board yaml to override a default. In such a + design, there must be a reasonable default if the macro is not set. + + +## Coding style + +Contributed source code must match the existing style of the DAPLink code base. + +The key requirements are: +- 4 space indents, no tabs are allowed. +- No trailing whitespace. +- All source files must end with a newline (an empty line at the end). +- Lines should generally not be longer than 120 characters, though this is not a hard rule. +- Braces generally follow the K&R style. +- Single-statement blocks for **if**, **else**, **do**, **while**, and **for** statements must be + enclosed in braces. +- Spaces are required between keywords and parentheses, and around operators. +- All functions require prototypes. +- Macros must be all uppercase. +- Functions should be all lowercase with underscores between words (sometimes called snake case). +- Types must be all lowercase, underscores between words, and have a `_t` suffix. +- Enumerations must start with `k` and use camel case, e.g. `kHardwareReset`. +- Code must be well commented and use Doxygen-style documentation comments for all declarations. + +For other style questions, please look to the existing code for answers. + + +## License + +By creating a pull request on GitHub, you are granting license your contributions under the same +Apache 2.0 license as the originalâ¯code. However, you still own the copyright to your contributions. +You may add your copyright below the Arm copyright in the license header at the top of the source +file. If a file is newly added by you, it must contain the standard license header, but it does not +require an Arm copyright. Please note that we do not list changes in each source file by copyright +owner, as this becomes a burden to maintain. + + +## Process + +Please create a pull request in GitHub with your contribution. Before creating the pull request, +please ensure that your code meets the requirements listed above and all tests pass. We also run the +tests on a wide range of boards for every pull request using our CI setup. Changes must pass on all +tested boards before the the pull request can be merged. + +The [developers' guide](docs/DEVELOPERS-GUIDE.md) describes how to create your development +environment. The [automated tests guide](docs/AUTOMATED_TESTS.md) provides information about the +available types of tests and describes how to run the tests. + + +## More + +For more information about contributing, see the Mbed OS [contributor +documentation](http://os.mbed.com/contributing). Although this documentation is written primarily +with Mbed OS in mind, much of it applies directly to DAPLink, as well.
diff -r 000000000000 -r 01f31e923fe2 LICENSE --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/LICENSE Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,167 @@ +Apache License +Version 2.0, January 2004 +http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. Definitions. + +"License" shall mean the terms and conditions for use, reproduction, and +distribution as defined by Sections 1 through 9 of this document. + +"Licensor" shall mean the copyright owner or entity authorized by the copyright +owner that is granting the License. + +"Legal Entity" shall mean the union of the acting entity and all other entities +that control, are controlled by, or are under common control with that entity. +For the purposes of this definition, "control" means (i) the power, direct or +indirect, to cause the direction or management of such entity, whether by +contract or otherwise, or (ii) ownership of fifty percent (50%) or more of the +outstanding shares, or (iii) beneficial ownership of such entity. + +"You" (or "Your") shall mean an individual or Legal Entity exercising +permissions granted by this License. + +"Source" form shall mean the preferred form for making modifications, including +but not limited to software source code, documentation source, and configuration +files. + +"Object" form shall mean any form resulting from mechanical transformation or +translation of a Source form, including but not limited to compiled object code, +generated documentation, and conversions to other media types. + +"Work" shall mean the work of authorship, whether in Source or Object form, made +available under the License, as indicated by a copyright notice that is included +in or attached to the work (an example is provided in the Appendix below). + +"Derivative Works" shall mean any work, whether in Source or Object form, that +is based on (or derived from) the Work and for which the editorial revisions, +annotations, elaborations, or other modifications represent, as a whole, an +original work of authorship. For the purposes of this License, Derivative Works +shall not include works that remain separable from, or merely link (or bind by +name) to the interfaces of, the Work and Derivative Works thereof. + +"Contribution" shall mean any work of authorship, including the original version +of the Work and any modifications or additions to that Work or Derivative Works +thereof, that is intentionally submitted to Licensor for inclusion in the Work +by the copyright owner or by an individual or Legal Entity authorized to submit +on behalf of the copyright owner. For the purposes of this definition, +"submitted" means any form of electronic, verbal, or written communication sent +to the Licensor or its representatives, including but not limited to +communication on electronic mailing lists, source code control systems, and +issue tracking systems that are managed by, or on behalf of, the Licensor for +the purpose of discussing and improving the Work, but excluding communication +that is conspicuously marked or otherwise designated in writing by the copyright +owner as "Not a Contribution." + +"Contributor" shall mean Licensor and any individual or Legal Entity on behalf +of whom a Contribution has been received by Licensor and subsequently +incorporated within the Work. + +2. Grant of Copyright License. + +Subject to the terms and conditions of this License, each Contributor hereby +grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, +irrevocable copyright license to reproduce, prepare Derivative Works of, +publicly display, publicly perform, sublicense, and distribute the Work and such +Derivative Works in Source or Object form. + +3. Grant of Patent License. + +Subject to the terms and conditions of this License, each Contributor hereby +grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, +irrevocable (except as stated in this section) patent license to make, have +made, use, offer to sell, sell, import, and otherwise transfer the Work, where +such license applies only to those patent claims licensable by such Contributor +that are necessarily infringed by their Contribution(s) alone or by combination +of their Contribution(s) with the Work to which such Contribution(s) was +submitted. If You institute patent litigation against any entity (including a +cross-claim or counterclaim in a lawsuit) alleging that the Work or a +Contribution incorporated within the Work constitutes direct or contributory +patent infringement, then any patent licenses granted to You under this License +for that Work shall terminate as of the date such litigation is filed. + +4. Redistribution. + +You may reproduce and distribute copies of the Work or Derivative Works thereof +in any medium, with or without modifications, and in Source or Object form, +provided that You meet the following conditions: + +You must give any other recipients of the Work or Derivative Works a copy of +this License; and +You must cause any modified files to carry prominent notices stating that You +changed the files; and +You must retain, in the Source form of any Derivative Works that You distribute, +all copyright, patent, trademark, and attribution notices from the Source form +of the Work, excluding those notices that do not pertain to any part of the +Derivative Works; and +If the Work includes a "NOTICE" text file as part of its distribution, then any +Derivative Works that You distribute must include a readable copy of the +attribution notices contained within such NOTICE file, excluding those notices +that do not pertain to any part of the Derivative Works, in at least one of the +following places: within a NOTICE text file distributed as part of the +Derivative Works; within the Source form or documentation, if provided along +with the Derivative Works; or, within a display generated by the Derivative +Works, if and wherever such third-party notices normally appear. The contents of +the NOTICE file are for informational purposes only and do not modify the +License. You may add Your own attribution notices within Derivative Works that +You distribute, alongside or as an addendum to the NOTICE text from the Work, +provided that such additional attribution notices cannot be construed as +modifying the License. +You may add Your own copyright statement to Your modifications and may provide +additional or different license terms and conditions for use, reproduction, or +distribution of Your modifications, or for any such Derivative Works as a whole, +provided Your use, reproduction, and distribution of the Work otherwise complies +with the conditions stated in this License. + +5. Submission of Contributions. + +Unless You explicitly state otherwise, any Contribution intentionally submitted +for inclusion in the Work by You to the Licensor shall be under the terms and +conditions of this License, without any additional terms or conditions. +Notwithstanding the above, nothing herein shall supersede or modify the terms of +any separate license agreement you may have executed with Licensor regarding +such Contributions. + +6. Trademarks. + +This License does not grant permission to use the trade names, trademarks, +service marks, or product names of the Licensor, except as required for +reasonable and customary use in describing the origin of the Work and +reproducing the content of the NOTICE file. + +7. Disclaimer of Warranty. + +Unless required by applicable law or agreed to in writing, Licensor provides the +Work (and each Contributor provides its Contributions) on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, +including, without limitation, any warranties or conditions of TITLE, +NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A PARTICULAR PURPOSE. You are +solely responsible for determining the appropriateness of using or +redistributing the Work and assume any risks associated with Your exercise of +permissions under this License. + +8. Limitation of Liability. + +In no event and under no legal theory, whether in tort (including negligence), +contract, or otherwise, unless required by applicable law (such as deliberate +and grossly negligent acts) or agreed to in writing, shall any Contributor be +liable to You for damages, including any direct, indirect, special, incidental, +or consequential damages of any character arising as a result of this License or +out of the use or inability to use the Work (including but not limited to +damages for loss of goodwill, work stoppage, computer failure or malfunction, or +any and all other commercial damages or losses), even if such Contributor has +been advised of the possibility of such damages. + +9. Accepting Warranty or Additional Liability. + +While redistributing the Work or Derivative Works thereof, You may choose to +offer, and charge a fee for, acceptance of support, warranty, indemnity, or +other liability obligations and/or rights consistent with this License. However, +in accepting such obligations, You may act only on Your own behalf and on Your +sole responsibility, not on behalf of any other Contributor, and only if You +agree to indemnify, defend, and hold each Contributor harmless for any liability +incurred by, or claims asserted against, such Contributor by reason of your +accepting any such warranty or additional liability. + +END OF TERMS AND CONDITIONS
diff -r 000000000000 -r 01f31e923fe2 README.md --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/README.md Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,41 @@ +[](https://armmbed.github.io/DAPLink/) + +Arm Mbed DAPLink is an open-source software project that enables programming and debugging application software running on Arm Cortex CPUs. Commonly referred to as interface firmware, DAPLink runs on a secondary MCU that is attached to the SWD or JTAG port of the application MCU. This configuration is found on nearly all development boards. Enumerating as a USB composite device, it creates a bridge between your development computer and the CPU debug access port. DAPLink enables developers with: +* MSC - drag-n-drop programming flash memory +* CDC - virtual com port for log, trace and terminal emulation +* HID - CMSIS-DAP compliant debug channel +* WEBUSB HID - CMSIS-DAP compliant debug channel + +More features are planned and will show up gradually over time. The project is constantly under heavy development by Arm, its partners, numerous hardware vendors and the open-source community around the world. DAPLink has superseded the mbed CMSIS-DAP interface firmware project. You are free to use and contribute. Enjoy! + +For more detailed usability information [see the users guide.](docs/USERS-GUIDE.md) + +## Compatibility +There are many ARM microcontroller-based Hardware Interface Circuits (HICs) that DAPLink interface firmware runs on. These can be found as standalone boards (debugger) or as part of a development kit. Some branded circuits that are known to be IO compatible are: +* [NXP OpenSDA based on K20, K22 and KL26](http://www.nxp.com/products/software-and-tools/run-time-software/kinetis-software-and-tools/ides-for-kinetis-mcus/opensda-serial-and-debug-adapter:OPENSDA) +* [NXP LPC-Link2 based on LPC11U35 or LPC4322](https://www.nxp.com/support/developer-resources/hardware-development-tools/lpcxpresso-boards:LPCXPRESSO-BOARDS) +* [Segger J-Link OB based on Atmel SAM3U](https://www.segger.com/products/debug-probes/j-link/models/j-link-ob/) + +## Releases +There are many board builds (board = HIC + target combination) created from this repository. Quarterly releases will contain new features and bugfixes. Standalone bugfixes are released once reported, verified and fixed. Both quarterly and bugfix releases will result in the build number being incremented. Many development kits and products ship with DAPLink interface firmware or are capable of running DAPLink firmware. **[The current release builds and instructions for updating DAPLink interface firmware is hosted on the DAPLink release site.](https://armmbed.github.io/DAPLink/)** Release notes and previous release builds can be found under GitHub releases. + +## Contribute + +We welcome contributions to DAPLink in any area. Look for an interesting feature or defect [under +issues](https://github.com/ARMmbed/DAPLink/issues), or start a new thread to engage with the +developers and maintainers. + +Please see the [contribution guidelines](CONTRIBUTING.md) for detailed requirements for +contributions. + +To report bugs, please [create an issue](https://github.com/ARMmbed/DAPLink/issues/new) in the +GitHub project. + +## Develop +Information for setting up a development environment, running the tests or creating a release build [can be found in the developers guide.](docs/DEVELOPERS-GUIDE.md) + +## License +DAPLink is licensed with the permissive Apache 2.0 license. See the [LICENSE](LICENSE) file for the +full text of the license. + +Copyright © 2006-2019 Arm Ltd
diff -r 000000000000 -r 01f31e923fe2 docs/AUTOMATED_TESTS.md --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/docs/AUTOMATED_TESTS.md Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,89 @@ +# Automated Tests + +DAPLink has an extensive automated test suite. It can be run on the current development environment (Windows and Linux) or a release package (Windows, Mac or Linux). Test results are written to the current directory and printed to the console. + +Tests are launched by running ``python test/run_test.py`` in the Python virtual environment. The test logic discovers connected DAPLink boards and targets only those boards. Likewise, it detects what firmware you have built and targets only that firmware. Specify --help to view testing options (``run_test.py --help``). + +The tests rely on information in ``test/info.py``. If you are porting DAPLink to a new board, you will need to add to info.py. See [Adding a new board](PORT_BOARD.md) for details. + +## Preparing bootloader for Tests +* Build the bootloader or interface project to be tested. +* [Enable automation mode](ENABLE_AUTOMATION.md) on the board if it has not been enabled already. + +## Test on Windows +### Prepare Host Machine +Windows drive indexing needs to be turned off prior to running the tests. + +* Disable indexing on removable drives + Run gpedit.msc (<Windows>+<R> to open run window)Â then go to: + Computer Configuration \ Administrative Templates \ Windows Components \ Search \ Do not allow locations on removable drives to be added to libraries. Enable the setting there. + +### Running Tests + * Open CMD and cd to DAPLink directory. + * Activate virtual env, launch tests by running ``python test/run_test.py`` + Specifying --firmwaredir is optional. For target images, either provide mbed.org authentication or use --targetdir to specify the location of pre-built target app binaries. + * Test results will be printed to console + +## Test on Linux +### Prepare Host Machine + Linux may have a daemon called modemmanager that sends unsolicitated traffic to DAPLink. This will cause serial port tests to fail, typically at band rate initialization. + To check if modemmanager service is running, run ``systemctl | grep Modem``. Modem Manager will be displayed if so. To disable this service, run ``systemctl disable ModemManager.service``. + Alternatively, this daemon can be removed with ``sudo apt-get purge modemmanager``. + +**Step 1.** Build Firmware Releases + The firmware images under test need to be built on Windows. Under tools directory, run ``build_release_uvision.bat``. Then copy the generated uvision_release directory to Linux. + +**Step 2.** Install Tools + Install [Python 2, 2.7.9 or above](https://www.python.org/downloads/). + Install [Git](https://git-scm.com/downloads). + +**Step 3.** Get the sources and create a virtual environment. + +``` +$ git clone https://github.com/mbedmicro/DAPLink +$ cd DAPLink +$ pip install virtualenv +$ virtualenv venv +``` +**Step 4.** Update tools + +``` +$ source venv/bin/activate +$ sudo pip install -r requirements.txt +``` + +### Running Tests +``` +$ sudo python test/run_test.py --force --firmwaredir <path_to_uvision_release> +``` + +--firmwaredir is required. For target images, either provide mbed.org authentication or use --targetdir to specify the location of pre-built target app binaries. +Test results will be printed to console. + +## Test on Mac +### Prepare Host Machine + Refer to the steps for Linux. + +### Running Tests + Refer to the steps for Linux. + +## Two Areas of Testing +Tests are grouped into two categories + +* Tests that validate how DAPLink is used for programming the target device and even the HIC itself via MSD--by copying an image file to the MSD drive (most users will drag-and-drop). These tests do not run by default but can be turned on by specifying --testdl. + + +* Tests that validate the MSD, CDC, and CMSIS-DAP endpoints. These tests run by default, but can be turned off by specifying --notestendpt + +The endpoint tests rely on a target application--a small UART program that implements a simple protocol. The target app is used by all three endpoint sub-tests. + +For mbed boards that are registered on mbed.org, the test builds the target application code on the fly in the cloud using the mbed RESTful Compile API. It then downloads the resulting image and downloads it to the target. The UART application source is in the mbed mercurial repository [daplink-validation](https://developer.mbed.org/users/c1728p9/code/daplink-validation/). For this workflow, you must specify your mbed.org user id and password via --user and --password. + +For boards that are not mbed enabled or not registered on mbed.org, the test accepts pre-built applications via the --targetdir option. You will need to build the UART application, porting it to whatever platform is suitable if the board is not mbed enabled. + +Currently, the tests only work in one fashion in any given run--using the Compile API or using pre-built binaries. That is, you cannot test (in one run) multiple boards if some have their target app built with Compile API and others have pre-built binaries. + +## CMSIS-DAP Tests +The CMSIS-DAP tests (referred to as "HID" tests in the python code) require pyOCD. Fortunately, pyOCD is listed in ``requirements.txt``, and thus it is downloaded and made available to the tests automatically when you set up your DAPLink python virtual environment. This is fine if you're doing regression testing, but won't be of much help if you're trying to test a new DAPLink port. The publicly released pyOCD is unlikely to support your new board. You will need to combine your DAPLink porting efforts with a pyOCD porting effort if you want to fully validate your DAPLink firmware with the automated tests. + +Assuming you have a pyOCD workspace on your local machine that supports your board, you'll need to tell the DAPLink tests to use that pyOCD instead of the one it downloaded from the Internet. The way to do that is to, while in the DAPLink virtual environment, cd to the root of your pyOCD workspace and run ``pip install --editable ./``, then cd back to the DAPLink workspace to run the tests.
diff -r 000000000000 -r 01f31e923fe2 docs/BOOTLOADER_UPDATES.md --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/docs/BOOTLOADER_UPDATES.md Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,27 @@ +# Bootloader updates + +DAPLink has the ability to bundle the bootloader firmware with the interface firmware and apply a bootloader update on the first boot of the interface. This allows bootloader updates to occur at the same time as interface updates and without any special instructions for the user. + +## Enabling bootloader updates + +To enable bootloader updates for a board or interface circuit, you must define the value ```DAPLINK_BOOTLOADER_UPDATE```. Once you define it, you can use the normal release process, which the [developers guide](DEVELOPERS-GUIDE.md) documents, to create firmware for all targets. + +## Safety when updating the bootloader + +The interface firmware erases and updates the vector table when updating the bootloader. Because of this, there is a small window of time during which the device will be in a nonbootable state if the device loses power. The cause of this is the lack of a valid vector table. To minimize the time without a valid vector table and to reduce risk, interface firmware replaces the bootloader's vector table with its own before performing the update. This way, while the bulk of the bootloader is being loaded, there is a valid vector table, and a loss of power event does not prevent the device from booting. The update process is below. The critical sections during which the device cannot lose power are in bold: + +1. **Erase the boot vector table, and program the intenterface's vector table to this location**. +1. Erase and program each sector of the bootloader with the new firmware. +1. **Erase the boot vector table, and program the new bootloader's vector table to this location**. + +Other checks +* The interface firmware will not downgrade the bootloader. If the current bootloader has a valid signature and a version greater than the interface's copy of the bootloader then the interface will not replace the bootloader. +* The interface firmware does a checksum over itself to check for any corruption. If it finds itself to be corrupt, it will not apply the bootloader update. In addition, an assert will appear on the on mass storage. +* Before attempting to update the bootloader the interface firmware compares its internal copy of the bootloader to the curent bootloader. If they are the same then it does not apply an update. + +## Dangers + +* The DAPLink bootloader has a fixed location for where the interface firmware is loaded (typically an offset of 0x8000 from the start of ROM). If you update to a bootloader that has a different offset then you will no longer be able to use the same interface firmware. Instead, you must use interface firmware built for the new offset. + +* This mechanism does not support downgrading or loading third party bootloaders. To do this, you must use a debugger or create a custom build of DAPLink. +* The LPC11U35 does not have a bootloader, so you cannot use bootloader updates on this interface.
diff -r 000000000000 -r 01f31e923fe2 docs/BUILD_OUTPUT.md --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/docs/BUILD_OUTPUT.md Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,72 @@ +# DAPLink Build Output + +## Variants + +Building a DAPLink target produces several variants of the build output. Files with the following names will be located in the project build directory after a successful build. + +``*_if.bin`` + +- Base file created by build, should not be used. + +``*_if_crc.bin`` + +- Preferred image for new boards. Does not work with some old bootloaders due to the vector table validation + +``*_if_crc.hex`` + +- Same as "``*_if_crc.bin``" just in hex form. + +``*_if_crc_legacy_0x5000.bin`` + +- Image required for existing boards with a bootloader built for an application starting at 0x5000. + +``*_if_crc_legacy_0x8000.bin`` + +- Image required for existing boards with a bootloader built for an application starting at 0x8000. + +The ``tools/post_compute_crc.py`` script is automatically run on the build output. It produces the variants listed above by modifying the output images in several ways. + +The image ``*_if_crc_legacy_0x5000.bin`` is a copy of ``*_if_crc_legacy_0x8000.bin`` but with 0x3000 bytes of extra padding pre-pended to the image. The first 0x40 bytes are an exact copy of the vector table and the remaining 0x2FC0 bytes are filled with 0xFF. This makes an image that can be loaded onto bootloaders with the old offset (0x5000) without requiring a complete rebuild. + +Not all targets will produce the legacy output files. + +## Image structure + +Aside from the code itself, the following are the important features of a DAPLink binary image. The ``post_compute_crc.py`` script adds the checksum and CRC into the images. + +### Vector table + +All images must begin with a valid NVIC vector table. + +The vector table is defined by the ``startup_MCUNAME.S`` file for each of the HIC HALs. The build info fields below are set directly in the vector table definition. + +### Checksum + +The first 7 vectors from the NVIC vector table (offsets 0x00-0x18) are checksummed. The two's complement of the checksum is stored in the unused, reserved vector at offset 0x1C. This checksum is required for certain NXP MCUs in order to boot. For other MCUs, the checksum is ignored. + +### Build info fields + +The vector table for DAPLink images contains several build info fields. These fields are placed in the unused, reserved vector table entries starting at offset 0x20. + +The information here is as follows (in order): + +* ``DAPLINK_BUILD_KEY`` + * Key used to indicate if the image is bootloader or interface. +* ``DAPLINK_HIC_ID`` + * Key used to determine hardware compatibility. + * This ensures that for example a bootloader update mean for a k20dx could never be loaded on a kl26z or any other chip +* ``DAPLINK_VERSION`` + * Software version. + * Meant for checking for incompatible legacy versions. + * Currently it is not used for this purpose and is just displayed in ``details.txt``. + +This change caused a problem with some old bootloaders, which require the 3 vector table entries starting at 0x20 to be set to 0. To overcome this the build scripts create the legacy images which zero out 0x20 and recompute the checksum. If you compare ``*_if_crc.bin`` and ``*_if_crc_legacy_0x8000.bin`` you should be able to see this difference. + +The corresponding struct in the code for these fields is ``daplink_info_t``, defined in ``daplink.h``. Constants with the valid values for these fields are also defined in ``daplink.h``. + +### CRC + +A CRC-32 is computed over the base output file (``*_if.bin``) and stored in the last 4 bytes of the image in little endian byte order. This produces the ``*_if_crc.bin`` file. + +At the moment the interface CRC isn't actually enforced so existing and interface images without a CRC can still be loaded. +
diff -r 000000000000 -r 01f31e923fe2 docs/DEVELOPERS-GUIDE.md --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/docs/DEVELOPERS-GUIDE.md Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,170 @@ +# DAPLink Developers Guide + +## Setup +DAPLink sources can be compiled using Keil MDK-ARM or mbed cli tool with arm compiler, which could be run both on Linux and Windows. See [here](AUTOMATED_TESTS.md) for test instructions on both OS and Mac. + +Install the necessary tools listed below. Skip any step where a compatible tool already exists. + +* Install [Python 2, 2.7.11 or above](https://www.python.org/downloads/) . Add to PATH. +* Install [Git](https://git-scm.com/downloads) . Add to PATH. +* Install [Keil MDK-ARM](https://www.keil.com/download/product/), preferably version 5. Set environment variable "UV4" to + the absolute path of the UV4 executable if you don't install to the default location. Note that "UV4" is what's used for + both MDK versions 4 and 5. This step can be skipped if you plan to use mbed cli, but you still need Arm Compiler 5, and + MDK is required to debug. +* Install virtualenv in your global Python installation eg: `pip install virtualenv`. + + +**Step 1.** Initial setup. + +Get the sources and create a virtual environment + +``` +$ git clone https://github.com/mbedmicro/DAPLink +$ cd DAPLink +$ pip install virtualenv +$ virtualenv venv +``` + +**Step 2.** One-time mbed-cli setup. + +This step is only required once if you are planning to use the mbed-cli build method. + +First run step 3 below to activate the virtual environment. Then execute these commands. +``` +$ mbed deploy +$ mbed config root . +$ mbed config ARM_PATH <FULL_PATH_TO_ARMCC_FOLDER> +``` + + +## Activate virtual environment +**Step 3.** Activate the virtual environment and update requirements. This is necessary when you open a new shell. **This should be done every time you pull new changes** + +``` +$ venv/Scripts/activate (For Linux) +$ venv/Scripts/activate.bat (For Windows) +$ pip install -r requirements.txt +``` + + +## Build +**This should be done every time you pull new changes** + +There are two ways to build DAPLink. You can generate Keil MDK project files and build within MDK. MDK is also used to debug DAPLink running on the interface chip. Or, you can use the `mbedcli_compile.py` script to build projects from the command line without requiring MDK. + + +**Step 4.1.** For MDK progen compilation. + +This command generates MDK project files under the `projectfiles/uvision` directory. +``` +$ progen generate -t uvision +``` + +To only generate one specific project, use a command like this: +``` +progen generate -f projects.yaml -p stm32f103xb_stm32f746zg_if -t uvision +``` +These options to `progen` set the parameters: +- `-f` for the input projects file +- `-p` for the project name +- `-t` to specify the IDE name + + +**Step 4.2.** For mbed-cli project compilation + +This command will build all projects: +``` +$ tools/mbedcli_compile.py +``` + +To build only a subset of projects, add the project name(s) to the end of the command line. Valid project names are listed +in the usage text shown with `--help`. The first time you build after each pull you should add `--clean` to perform a +complete re-build. + +## Contribute +We would love to have your changes! Pull requests should be made once a changeset is [rebased onto Master](https://www.atlassian.com/git/tutorials/merging-vs-rebasing/workflow-walkthrough). See the [contributing guide](../CONTRIBUTING.md) for detailed requirements and guidelines for contributions. + +## Mbed-cli compile environment + +### Features +- Support both Python 2.x and 3.x versions. +- Can compile a list of projects or the all of the projects. +- Can generate the release directory with one command. + +### Prerequisite +mbed-cli is included in `requirements.txt`, so it will be installed automatically when configuring +your development environment using the steps described above. + +### `tools/mbedcli_compile.py` script +Arguments +``` +positional arguments: + projects Selectively compile only the firmware specified + otherwise all projects + +optional arguments: + -h, --help show this help message and exit + --release Create a release with the yaml version file + --build-folder BUILD_FOLDER + Release directory to grab files from + --release-folder RELEASE_FOLDER + Directory to create and place files in + --toolchain TOOLCHAIN + Toolchain directory if present + --clean Rebuild or delete build folder before compile + -v Pass verbosity level to mbed compile -vv for more +``` +Valid projects are listed on help. + +Generate files needed by mbed-cli +* `custom_profile.json` lists toolchain profile or compile flags parsed from the yaml files +* `custom_targets.json` contains platform information for specific hics. +* `.mbedignore` filters all files not needed for the project. + +## Port +There are three defined ways in which DAPLink can be extended. These are adding target support, adding board support and adding HIC support. Details on porting each of these can be found below. + +* [Adding a new target](PORT_TARGET_FAMILY.md) +* [Adding a new board](PORT_BOARD.md) +* [Adding a new HIC](PORT_HIC.md) + + +## Test +DAPLink has an extensive set of automated tests written in Python. They are used for regression testing, but you can use them to validate your DAPLink port. Details are [here](AUTOMATED_TESTS.md) + +An option to search for the daplink firmware build in uvision and mbedcli build folders. +`python test/run_test.py --projecttool mbedcli ...` or `python test/run_test.py --projecttool uvision ...`. + +## Release + +### Release using uvision + +DAPLink contains scripts to automate most of the steps of building a release. In addition to building the release, these scripts also save relevant build information such as git SHA and python tool versions so the same build can be reproduced. The recommended steps for creating a release are below. + +* Create a tag with the correct release version and push it to github +* Clean the repo you will be building from by running 'git clean -xdf' followed by 'git reset --hard' +* Run the script ``build_release_uvision.bat`` to create all builds. +* All release deliverables will be created and stored in 'uvision_release'. Save this wherever your builds are stored. + +Note: A previous build can be reproduced by using the ``build_requirements.txt`` of that build. +To do this add the additional argument ``build_requirements.txt`` when calling ``build_release_uvision.bat`` in step 2. +This will install and build with the exact version of the python packages used to create that build. + +### Release using mbedcli + +If the project list is not specify, all interface and booloader projects will be compiled. If `--release_version` is given, a folder (`firmware` on default or specified by `--release_folder`, to be concatenated with the version number), will be generated with the bin, update.yml and zip file containing the bins for release +``` +$ venv/Scripts/activate +$ pip install -r requirements3.txt +$ tools/mbedcli_compile.py --release_version 0250 --release_folder firmware +``` + +There is an intermediate step in uvision environment in creating a release directory. This step is not needed in mbedcli environment but to make this equivalent directory invoke +`copy_release_files.py --project-tool mbedcli` +To make a release directory from the step above. +`package_release_files.py SRC_DIR DEST_DIR VERSION_NUMBER --toolchain ARM` + +## MDK +If you want to use the MDK (uVision) IDE to work with the DAPLink code, you must launch it in the right environment. The project will fail to build otherwise. To launch uVision properly, use ``tools/launch_uvision.bat`` + +This script can take arguments to override default virtual environment and python packages to be installed. For example `tools\launch_uvision.bat other_env other_requirements.txt`
diff -r 000000000000 -r 01f31e923fe2 docs/Doxyfile
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/docs/Doxyfile Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,2433 @@
+# Doxyfile 1.8.9.1
+
+# This file describes the settings to be used by the documentation system
+# doxygen (www.doxygen.org) for a project.
+#
+# All text after a double hash (##) is considered a comment and is placed in
+# front of the TAG it is preceding.
+#
+# All text after a single hash (#) is considered a comment and will be ignored.
+# The format is:
+# TAG = value [value, ...]
+# For lists, items can also be appended using:
+# TAG += value [value, ...]
+# Values that contain spaces should be placed between quotes (\" \").
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+
+# This tag specifies the encoding used for all characters in the config file
+# that follow. The default is UTF-8 which is also the encoding used for all text
+# before the first occurrence of this tag. Doxygen uses libiconv (or the iconv
+# built into libc) for the transcoding. See http://www.gnu.org/software/libiconv
+# for the list of possible encodings.
+# The default value is: UTF-8.
+
+DOXYFILE_ENCODING = UTF-8
+
+# The PROJECT_NAME tag is a single word (or a sequence of words surrounded by
+# double-quotes, unless you are using Doxywizard) that should identify the
+# project for which the documentation is generated. This name is used in the
+# title of most generated pages and in a few other places.
+# The default value is: My Project.
+
+PROJECT_NAME = DAPLink
+
+# The PROJECT_NUMBER tag can be used to enter a project or revision number. This
+# could be handy for archiving the generated documentation or if some version
+# control system is used.
+
+PROJECT_NUMBER =
+
+# Using the PROJECT_BRIEF tag one can provide an optional one line description
+# for a project that appears at the top of each page and should give viewer a
+# quick idea about the purpose of the project. Keep the description short.
+
+PROJECT_BRIEF = "mbed interface firmware"
+
+# With the PROJECT_LOGO tag one can specify a logo or an icon that is included
+# in the documentation. The maximum height of the logo should not exceed 55
+# pixels and the maximum width should not exceed 200 pixels. Doxygen will copy
+# the logo to the output directory.
+
+PROJECT_LOGO =
+
+# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path
+# into which the generated documentation will be written. If a relative path is
+# entered, it will be relative to the location where doxygen was started. If
+# left blank the current directory will be used.
+
+OUTPUT_DIRECTORY = ./doxygen/
+
+# If the CREATE_SUBDIRS tag is set to YES then doxygen will create 4096 sub-
+# directories (in 2 levels) under the output directory of each output format and
+# will distribute the generated files over these directories. Enabling this
+# option can be useful when feeding doxygen a huge amount of source files, where
+# putting all generated files in the same directory would otherwise causes
+# performance problems for the file system.
+# The default value is: NO.
+
+CREATE_SUBDIRS = YES
+
+# If the ALLOW_UNICODE_NAMES tag is set to YES, doxygen will allow non-ASCII
+# characters to appear in the names of generated files. If set to NO, non-ASCII
+# characters will be escaped, for example _xE3_x81_x84 will be used for Unicode
+# U+3044.
+# The default value is: NO.
+
+ALLOW_UNICODE_NAMES = NO
+
+# The OUTPUT_LANGUAGE tag is used to specify the language in which all
+# documentation generated by doxygen is written. Doxygen will use this
+# information to generate all constant output in the proper language.
+# Possible values are: Afrikaans, Arabic, Armenian, Brazilian, Catalan, Chinese,
+# Chinese-Traditional, Croatian, Czech, Danish, Dutch, English (United States),
+# Esperanto, Farsi (Persian), Finnish, French, German, Greek, Hungarian,
+# Indonesian, Italian, Japanese, Japanese-en (Japanese with English messages),
+# Korean, Korean-en (Korean with English messages), Latvian, Lithuanian,
+# Macedonian, Norwegian, Persian (Farsi), Polish, Portuguese, Romanian, Russian,
+# Serbian, Serbian-Cyrillic, Slovak, Slovene, Spanish, Swedish, Turkish,
+# Ukrainian and Vietnamese.
+# The default value is: English.
+
+OUTPUT_LANGUAGE = English
+
+# If the BRIEF_MEMBER_DESC tag is set to YES, doxygen will include brief member
+# descriptions after the members that are listed in the file and class
+# documentation (similar to Javadoc). Set to NO to disable this.
+# The default value is: YES.
+
+BRIEF_MEMBER_DESC = YES
+
+# If the REPEAT_BRIEF tag is set to YES, doxygen will prepend the brief
+# description of a member or function before the detailed description
+#
+# Note: If both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the
+# brief descriptions will be completely suppressed.
+# The default value is: YES.
+
+REPEAT_BRIEF = YES
+
+# This tag implements a quasi-intelligent brief description abbreviator that is
+# used to form the text in various listings. Each string in this list, if found
+# as the leading text of the brief description, will be stripped from the text
+# and the result, after processing the whole list, is used as the annotated
+# text. Otherwise, the brief description is used as-is. If left blank, the
+# following values are used ($name is automatically replaced with the name of
+# the entity):The $name class, The $name widget, The $name file, is, provides,
+# specifies, contains, represents, a, an and the.
+
+ABBREVIATE_BRIEF = "The $name class" \
+ "The $name widget" \
+ "The $name file" \
+ is \
+ provides \
+ specifies \
+ contains \
+ represents \
+ a \
+ an \
+ the
+
+# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then
+# doxygen will generate a detailed section even if there is only a brief
+# description.
+# The default value is: NO.
+
+ALWAYS_DETAILED_SEC = NO
+
+# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all
+# inherited members of a class in the documentation of that class as if those
+# members were ordinary class members. Constructors, destructors and assignment
+# operators of the base classes will not be shown.
+# The default value is: NO.
+
+INLINE_INHERITED_MEMB = NO
+
+# If the FULL_PATH_NAMES tag is set to YES, doxygen will prepend the full path
+# before files name in the file list and in the header files. If set to NO the
+# shortest path that makes the file name unique will be used
+# The default value is: YES.
+
+FULL_PATH_NAMES = YES
+
+# The STRIP_FROM_PATH tag can be used to strip a user-defined part of the path.
+# Stripping is only done if one of the specified strings matches the left-hand
+# part of the path. The tag can be used to show relative paths in the file list.
+# If left blank the directory from which doxygen is run is used as the path to
+# strip.
+#
+# Note that you can specify absolute paths here, but also relative paths, which
+# will be relative from the directory where doxygen is started.
+# This tag requires that the tag FULL_PATH_NAMES is set to YES.
+
+STRIP_FROM_PATH =
+
+# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of the
+# path mentioned in the documentation of a class, which tells the reader which
+# header file to include in order to use a class. If left blank only the name of
+# the header file containing the class definition is used. Otherwise one should
+# specify the list of include paths that are normally passed to the compiler
+# using the -I flag.
+
+STRIP_FROM_INC_PATH =
+
+# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter (but
+# less readable) file names. This can be useful is your file systems doesn't
+# support long names like on DOS, Mac, or CD-ROM.
+# The default value is: NO.
+
+SHORT_NAMES = NO
+
+# If the JAVADOC_AUTOBRIEF tag is set to YES then doxygen will interpret the
+# first line (until the first dot) of a Javadoc-style comment as the brief
+# description. If set to NO, the Javadoc-style will behave just like regular Qt-
+# style comments (thus requiring an explicit @brief command for a brief
+# description.)
+# The default value is: NO.
+
+JAVADOC_AUTOBRIEF = NO
+
+# If the QT_AUTOBRIEF tag is set to YES then doxygen will interpret the first
+# line (until the first dot) of a Qt-style comment as the brief description. If
+# set to NO, the Qt-style will behave just like regular Qt-style comments (thus
+# requiring an explicit \brief command for a brief description.)
+# The default value is: NO.
+
+QT_AUTOBRIEF = NO
+
+# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make doxygen treat a
+# multi-line C++ special comment block (i.e. a block of //! or /// comments) as
+# a brief description. This used to be the default behavior. The new default is
+# to treat a multi-line C++ comment block as a detailed description. Set this
+# tag to YES if you prefer the old behavior instead.
+#
+# Note that setting this tag to YES also means that rational rose comments are
+# not recognized any more.
+# The default value is: NO.
+
+MULTILINE_CPP_IS_BRIEF = NO
+
+# If the INHERIT_DOCS tag is set to YES then an undocumented member inherits the
+# documentation from any documented member that it re-implements.
+# The default value is: YES.
+
+INHERIT_DOCS = YES
+
+# If the SEPARATE_MEMBER_PAGES tag is set to YES then doxygen will produce a new
+# page for each member. If set to NO, the documentation of a member will be part
+# of the file/class/namespace that contains it.
+# The default value is: NO.
+
+SEPARATE_MEMBER_PAGES = NO
+
+# The TAB_SIZE tag can be used to set the number of spaces in a tab. Doxygen
+# uses this value to replace tabs by spaces in code fragments.
+# Minimum value: 1, maximum value: 16, default value: 4.
+
+TAB_SIZE = 4
+
+# This tag can be used to specify a number of aliases that act as commands in
+# the documentation. An alias has the form:
+# name=value
+# For example adding
+# "sideeffect=@par Side Effects:\n"
+# will allow you to put the command \sideeffect (or @sideeffect) in the
+# documentation, which will result in a user-defined paragraph with heading
+# "Side Effects:". You can put \n's in the value part of an alias to insert
+# newlines.
+
+ALIASES =
+
+# This tag can be used to specify a number of word-keyword mappings (TCL only).
+# A mapping has the form "name=value". For example adding "class=itcl::class"
+# will allow you to use the command class in the itcl::class meaning.
+
+TCL_SUBST =
+
+# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources
+# only. Doxygen will then generate output that is more tailored for C. For
+# instance, some of the names that are used will be different. The list of all
+# members will be omitted, etc.
+# The default value is: NO.
+
+OPTIMIZE_OUTPUT_FOR_C = YES
+
+# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java or
+# Python sources only. Doxygen will then generate output that is more tailored
+# for that language. For instance, namespaces will be presented as packages,
+# qualified scopes will look different, etc.
+# The default value is: NO.
+
+OPTIMIZE_OUTPUT_JAVA = NO
+
+# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran
+# sources. Doxygen will then generate output that is tailored for Fortran.
+# The default value is: NO.
+
+OPTIMIZE_FOR_FORTRAN = NO
+
+# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL
+# sources. Doxygen will then generate output that is tailored for VHDL.
+# The default value is: NO.
+
+OPTIMIZE_OUTPUT_VHDL = NO
+
+# Doxygen selects the parser to use depending on the extension of the files it
+# parses. With this tag you can assign which parser to use for a given
+# extension. Doxygen has a built-in mapping, but you can override or extend it
+# using this tag. The format is ext=language, where ext is a file extension, and
+# language is one of the parsers supported by doxygen: IDL, Java, Javascript,
+# C#, C, C++, D, PHP, Objective-C, Python, Fortran (fixed format Fortran:
+# FortranFixed, free formatted Fortran: FortranFree, unknown formatted Fortran:
+# Fortran. In the later case the parser tries to guess whether the code is fixed
+# or free formatted code, this is the default for Fortran type files), VHDL. For
+# instance to make doxygen treat .inc files as Fortran files (default is PHP),
+# and .f files as C (default is Fortran), use: inc=Fortran f=C.
+#
+# Note: For files without extension you can use no_extension as a placeholder.
+#
+# Note that for custom extensions you also need to set FILE_PATTERNS otherwise
+# the files are not read by doxygen.
+
+EXTENSION_MAPPING =
+
+# If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments
+# according to the Markdown format, which allows for more readable
+# documentation. See http://daringfireball.net/projects/markdown/ for details.
+# The output of markdown processing is further processed by doxygen, so you can
+# mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in
+# case of backward compatibilities issues.
+# The default value is: YES.
+
+MARKDOWN_SUPPORT = YES
+
+# When enabled doxygen tries to link words that correspond to documented
+# classes, or namespaces to their corresponding documentation. Such a link can
+# be prevented in individual cases by putting a % sign in front of the word or
+# globally by setting AUTOLINK_SUPPORT to NO.
+# The default value is: YES.
+
+AUTOLINK_SUPPORT = YES
+
+# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want
+# to include (a tag file for) the STL sources as input, then you should set this
+# tag to YES in order to let doxygen match functions declarations and
+# definitions whose arguments contain STL classes (e.g. func(std::string);
+# versus func(std::string) {}). This also make the inheritance and collaboration
+# diagrams that involve STL classes more complete and accurate.
+# The default value is: NO.
+
+BUILTIN_STL_SUPPORT = NO
+
+# If you use Microsoft's C++/CLI language, you should set this option to YES to
+# enable parsing support.
+# The default value is: NO.
+
+CPP_CLI_SUPPORT = NO
+
+# Set the SIP_SUPPORT tag to YES if your project consists of sip (see:
+# http://www.riverbankcomputing.co.uk/software/sip/intro) sources only. Doxygen
+# will parse them like normal C++ but will assume all classes use public instead
+# of private inheritance when no explicit protection keyword is present.
+# The default value is: NO.
+
+SIP_SUPPORT = NO
+
+# For Microsoft's IDL there are propget and propput attributes to indicate
+# getter and setter methods for a property. Setting this option to YES will make
+# doxygen to replace the get and set methods by a property in the documentation.
+# This will only work if the methods are indeed getting or setting a simple
+# type. If this is not the case, or you want to show the methods anyway, you
+# should set this option to NO.
+# The default value is: YES.
+
+IDL_PROPERTY_SUPPORT = YES
+
+# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC
+# tag is set to YES then doxygen will reuse the documentation of the first
+# member in the group (if any) for the other members of the group. By default
+# all members of a group must be documented explicitly.
+# The default value is: NO.
+
+DISTRIBUTE_GROUP_DOC = NO
+
+# Set the SUBGROUPING tag to YES to allow class member groups of the same type
+# (for instance a group of public functions) to be put as a subgroup of that
+# type (e.g. under the Public Functions section). Set it to NO to prevent
+# subgrouping. Alternatively, this can be done per class using the
+# \nosubgrouping command.
+# The default value is: YES.
+
+SUBGROUPING = YES
+
+# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and unions
+# are shown inside the group in which they are included (e.g. using \ingroup)
+# instead of on a separate page (for HTML and Man pages) or section (for LaTeX
+# and RTF).
+#
+# Note that this feature does not work in combination with
+# SEPARATE_MEMBER_PAGES.
+# The default value is: NO.
+
+INLINE_GROUPED_CLASSES = NO
+
+# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and unions
+# with only public data fields or simple typedef fields will be shown inline in
+# the documentation of the scope in which they are defined (i.e. file,
+# namespace, or group documentation), provided this scope is documented. If set
+# to NO, structs, classes, and unions are shown on a separate page (for HTML and
+# Man pages) or section (for LaTeX and RTF).
+# The default value is: NO.
+
+INLINE_SIMPLE_STRUCTS = NO
+
+# When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or
+# enum is documented as struct, union, or enum with the name of the typedef. So
+# typedef struct TypeS {} TypeT, will appear in the documentation as a struct
+# with name TypeT. When disabled the typedef will appear as a member of a file,
+# namespace, or class. And the struct will be named TypeS. This can typically be
+# useful for C code in case the coding convention dictates that all compound
+# types are typedef'ed and only the typedef is referenced, never the tag name.
+# The default value is: NO.
+
+TYPEDEF_HIDES_STRUCT = NO
+
+# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This
+# cache is used to resolve symbols given their name and scope. Since this can be
+# an expensive process and often the same symbol appears multiple times in the
+# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small
+# doxygen will become slower. If the cache is too large, memory is wasted. The
+# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range
+# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536
+# symbols. At the end of a run doxygen will report the cache usage and suggest
+# the optimal cache size from a speed point of view.
+# Minimum value: 0, maximum value: 9, default value: 0.
+
+LOOKUP_CACHE_SIZE = 0
+
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+
+# If the EXTRACT_ALL tag is set to YES, doxygen will assume all entities in
+# documentation are documented, even if no documentation was available. Private
+# class members and static file members will be hidden unless the
+# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES.
+# Note: This will also disable the warnings about undocumented members that are
+# normally produced when WARNINGS is set to YES.
+# The default value is: NO.
+
+EXTRACT_ALL = NO
+
+# If the EXTRACT_PRIVATE tag is set to YES, all private members of a class will
+# be included in the documentation.
+# The default value is: NO.
+
+EXTRACT_PRIVATE = NO
+
+# If the EXTRACT_PACKAGE tag is set to YES, all members with package or internal
+# scope will be included in the documentation.
+# The default value is: NO.
+
+EXTRACT_PACKAGE = NO
+
+# If the EXTRACT_STATIC tag is set to YES, all static members of a file will be
+# included in the documentation.
+# The default value is: NO.
+
+EXTRACT_STATIC = NO
+
+# If the EXTRACT_LOCAL_CLASSES tag is set to YES, classes (and structs) defined
+# locally in source files will be included in the documentation. If set to NO,
+# only classes defined in header files are included. Does not have any effect
+# for Java sources.
+# The default value is: YES.
+
+EXTRACT_LOCAL_CLASSES = YES
+
+# This flag is only useful for Objective-C code. If set to YES, local methods,
+# which are defined in the implementation section but not in the interface are
+# included in the documentation. If set to NO, only methods in the interface are
+# included.
+# The default value is: NO.
+
+EXTRACT_LOCAL_METHODS = NO
+
+# If this flag is set to YES, the members of anonymous namespaces will be
+# extracted and appear in the documentation as a namespace called
+# 'anonymous_namespace{file}', where file will be replaced with the base name of
+# the file that contains the anonymous namespace. By default anonymous namespace
+# are hidden.
+# The default value is: NO.
+
+EXTRACT_ANON_NSPACES = NO
+
+# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all
+# undocumented members inside documented classes or files. If set to NO these
+# members will be included in the various overviews, but no documentation
+# section is generated. This option has no effect if EXTRACT_ALL is enabled.
+# The default value is: NO.
+
+HIDE_UNDOC_MEMBERS = NO
+
+# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all
+# undocumented classes that are normally visible in the class hierarchy. If set
+# to NO, these classes will be included in the various overviews. This option
+# has no effect if EXTRACT_ALL is enabled.
+# The default value is: NO.
+
+HIDE_UNDOC_CLASSES = NO
+
+# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend
+# (class|struct|union) declarations. If set to NO, these declarations will be
+# included in the documentation.
+# The default value is: NO.
+
+HIDE_FRIEND_COMPOUNDS = NO
+
+# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any
+# documentation blocks found inside the body of a function. If set to NO, these
+# blocks will be appended to the function's detailed documentation block.
+# The default value is: NO.
+
+HIDE_IN_BODY_DOCS = NO
+
+# The INTERNAL_DOCS tag determines if documentation that is typed after a
+# \internal command is included. If the tag is set to NO then the documentation
+# will be excluded. Set it to YES to include the internal documentation.
+# The default value is: NO.
+
+INTERNAL_DOCS = NO
+
+# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file
+# names in lower-case letters. If set to YES, upper-case letters are also
+# allowed. This is useful if you have classes or files whose names only differ
+# in case and if your file system supports case sensitive file names. Windows
+# and Mac users are advised to set this option to NO.
+# The default value is: system dependent.
+
+CASE_SENSE_NAMES = NO
+
+# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with
+# their full class and namespace scopes in the documentation. If set to YES, the
+# scope will be hidden.
+# The default value is: NO.
+
+HIDE_SCOPE_NAMES = NO
+
+# If the HIDE_COMPOUND_REFERENCE tag is set to NO (default) then doxygen will
+# append additional text to a page's title, such as Class Reference. If set to
+# YES the compound reference will be hidden.
+# The default value is: NO.
+
+HIDE_COMPOUND_REFERENCE= NO
+
+# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of
+# the files that are included by a file in the documentation of that file.
+# The default value is: YES.
+
+SHOW_INCLUDE_FILES = YES
+
+# If the SHOW_GROUPED_MEMB_INC tag is set to YES then Doxygen will add for each
+# grouped member an include statement to the documentation, telling the reader
+# which file to include in order to use the member.
+# The default value is: NO.
+
+SHOW_GROUPED_MEMB_INC = NO
+
+# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include
+# files with double quotes in the documentation rather than with sharp brackets.
+# The default value is: NO.
+
+FORCE_LOCAL_INCLUDES = NO
+
+# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the
+# documentation for inline members.
+# The default value is: YES.
+
+INLINE_INFO = YES
+
+# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the
+# (detailed) documentation of file and class members alphabetically by member
+# name. If set to NO, the members will appear in declaration order.
+# The default value is: YES.
+
+SORT_MEMBER_DOCS = YES
+
+# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief
+# descriptions of file, namespace and class members alphabetically by member
+# name. If set to NO, the members will appear in declaration order. Note that
+# this will also influence the order of the classes in the class list.
+# The default value is: NO.
+
+SORT_BRIEF_DOCS = NO
+
+# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the
+# (brief and detailed) documentation of class members so that constructors and
+# destructors are listed first. If set to NO the constructors will appear in the
+# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS.
+# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief
+# member documentation.
+# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting
+# detailed member documentation.
+# The default value is: NO.
+
+SORT_MEMBERS_CTORS_1ST = NO
+
+# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy
+# of group names into alphabetical order. If set to NO the group names will
+# appear in their defined order.
+# The default value is: NO.
+
+SORT_GROUP_NAMES = NO
+
+# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by
+# fully-qualified names, including namespaces. If set to NO, the class list will
+# be sorted only by class name, not including the namespace part.
+# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.
+# Note: This option applies only to the class list, not to the alphabetical
+# list.
+# The default value is: NO.
+
+SORT_BY_SCOPE_NAME = NO
+
+# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper
+# type resolution of all parameters of a function it will reject a match between
+# the prototype and the implementation of a member function even if there is
+# only one candidate or it is obvious which candidate to choose by doing a
+# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still
+# accept a match between prototype and implementation in such cases.
+# The default value is: NO.
+
+STRICT_PROTO_MATCHING = NO
+
+# The GENERATE_TODOLIST tag can be used to enable (YES) or disable (NO) the todo
+# list. This list is created by putting \todo commands in the documentation.
+# The default value is: YES.
+
+GENERATE_TODOLIST = YES
+
+# The GENERATE_TESTLIST tag can be used to enable (YES) or disable (NO) the test
+# list. This list is created by putting \test commands in the documentation.
+# The default value is: YES.
+
+GENERATE_TESTLIST = YES
+
+# The GENERATE_BUGLIST tag can be used to enable (YES) or disable (NO) the bug
+# list. This list is created by putting \bug commands in the documentation.
+# The default value is: YES.
+
+GENERATE_BUGLIST = YES
+
+# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or disable (NO)
+# the deprecated list. This list is created by putting \deprecated commands in
+# the documentation.
+# The default value is: YES.
+
+GENERATE_DEPRECATEDLIST= YES
+
+# The ENABLED_SECTIONS tag can be used to enable conditional documentation
+# sections, marked by \if <section_label> ... \endif and \cond <section_label>
+# ... \endcond blocks.
+
+ENABLED_SECTIONS =
+
+# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the
+# initial value of a variable or macro / define can have for it to appear in the
+# documentation. If the initializer consists of more lines than specified here
+# it will be hidden. Use a value of 0 to hide initializers completely. The
+# appearance of the value of individual variables and macros / defines can be
+# controlled using \showinitializer or \hideinitializer command in the
+# documentation regardless of this setting.
+# Minimum value: 0, maximum value: 10000, default value: 30.
+
+MAX_INITIALIZER_LINES = 30
+
+# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at
+# the bottom of the documentation of classes and structs. If set to YES, the
+# list will mention the files that were used to generate the documentation.
+# The default value is: YES.
+
+SHOW_USED_FILES = YES
+
+# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This
+# will remove the Files entry from the Quick Index and from the Folder Tree View
+# (if specified).
+# The default value is: YES.
+
+SHOW_FILES = YES
+
+# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces
+# page. This will remove the Namespaces entry from the Quick Index and from the
+# Folder Tree View (if specified).
+# The default value is: YES.
+
+SHOW_NAMESPACES = YES
+
+# The FILE_VERSION_FILTER tag can be used to specify a program or script that
+# doxygen should invoke to get the current version for each file (typically from
+# the version control system). Doxygen will invoke the program by executing (via
+# popen()) the command command input-file, where command is the value of the
+# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided
+# by doxygen. Whatever the program writes to standard output is used as the file
+# version. For an example see the documentation.
+
+FILE_VERSION_FILTER =
+
+# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed
+# by doxygen. The layout file controls the global structure of the generated
+# output files in an output format independent way. To create the layout file
+# that represents doxygen's defaults, run doxygen with the -l option. You can
+# optionally specify a file name after the option, if omitted DoxygenLayout.xml
+# will be used as the name of the layout file.
+#
+# Note that if you run doxygen from a directory containing a file called
+# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE
+# tag is left empty.
+
+LAYOUT_FILE =
+
+# The CITE_BIB_FILES tag can be used to specify one or more bib files containing
+# the reference definitions. This must be a list of .bib files. The .bib
+# extension is automatically appended if omitted. This requires the bibtex tool
+# to be installed. See also http://en.wikipedia.org/wiki/BibTeX for more info.
+# For LaTeX the style of the bibliography can be controlled using
+# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the
+# search path. See also \cite for info how to create references.
+
+CITE_BIB_FILES =
+
+#---------------------------------------------------------------------------
+# Configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+
+# The QUIET tag can be used to turn on/off the messages that are generated to
+# standard output by doxygen. If QUIET is set to YES this implies that the
+# messages are off.
+# The default value is: NO.
+
+QUIET = NO
+
+# The WARNINGS tag can be used to turn on/off the warning messages that are
+# generated to standard error (stderr) by doxygen. If WARNINGS is set to YES
+# this implies that the warnings are on.
+#
+# Tip: Turn warnings on while writing the documentation.
+# The default value is: YES.
+
+WARNINGS = YES
+
+# If the WARN_IF_UNDOCUMENTED tag is set to YES then doxygen will generate
+# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag
+# will automatically be disabled.
+# The default value is: YES.
+
+WARN_IF_UNDOCUMENTED = YES
+
+# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for
+# potential errors in the documentation, such as not documenting some parameters
+# in a documented function, or documenting parameters that don't exist or using
+# markup commands wrongly.
+# The default value is: YES.
+
+WARN_IF_DOC_ERROR = YES
+
+# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that
+# are documented, but have no documentation for their parameters or return
+# value. If set to NO, doxygen will only warn about wrong or incomplete
+# parameter documentation, but not about the absence of documentation.
+# The default value is: NO.
+
+WARN_NO_PARAMDOC = NO
+
+# The WARN_FORMAT tag determines the format of the warning messages that doxygen
+# can produce. The string should contain the $file, $line, and $text tags, which
+# will be replaced by the file and line number from which the warning originated
+# and the warning text. Optionally the format may contain $version, which will
+# be replaced by the version of the file (if it could be obtained via
+# FILE_VERSION_FILTER)
+# The default value is: $file:$line: $text.
+
+WARN_FORMAT = "$file:$line: $text"
+
+# The WARN_LOGFILE tag can be used to specify a file to which warning and error
+# messages should be written. If left blank the output is written to standard
+# error (stderr).
+
+WARN_LOGFILE =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the input files
+#---------------------------------------------------------------------------
+
+# The INPUT tag is used to specify the files and/or directories that contain
+# documented source files. You may enter file names like myfile.cpp or
+# directories like /usr/src/myproject. Separate the files or directories with
+# spaces.
+# Note: If this tag is empty the current directory is searched.
+
+INPUT = ./source \
+ ./source/template
+
+# This tag can be used to specify the character encoding of the source files
+# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses
+# libiconv (or the iconv built into libc) for the transcoding. See the libiconv
+# documentation (see: http://www.gnu.org/software/libiconv) for the list of
+# possible encodings.
+# The default value is: UTF-8.
+
+INPUT_ENCODING = UTF-8
+
+# If the value of the INPUT tag contains directories, you can use the
+# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and
+# *.h) to filter out the source-files in the directories. If left blank the
+# following patterns are tested:*.c, *.cc, *.cxx, *.cpp, *.c++, *.java, *.ii,
+# *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h, *.hh, *.hxx, *.hpp,
+# *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc, *.m, *.markdown,
+# *.md, *.mm, *.dox, *.py, *.f90, *.f, *.for, *.tcl, *.vhd, *.vhdl, *.ucf,
+# *.qsf, *.as and *.js.
+
+FILE_PATTERNS = *.c \
+ *.cc \
+ *.cxx \
+ *.cpp \
+ *.c++ \
+ *.java \
+ *.ii \
+ *.ixx \
+ *.ipp \
+ *.i++ \
+ *.inl \
+ *.idl \
+ *.ddl \
+ *.odl \
+ *.h \
+ *.hh \
+ *.hxx \
+ *.hpp \
+ *.h++ \
+ *.cs \
+ *.d \
+ *.php \
+ *.php4 \
+ *.php5 \
+ *.phtml \
+ *.inc \
+ *.m \
+ *.markdown \
+ *.md \
+ *.mm \
+ *.dox \
+ *.py \
+ *.f90 \
+ *.f \
+ *.for \
+ *.tcl \
+ *.vhd \
+ *.vhdl \
+ *.ucf \
+ *.qsf \
+ *.as \
+ *.js
+
+# The RECURSIVE tag can be used to specify whether or not subdirectories should
+# be searched for input files as well.
+# The default value is: NO.
+
+RECURSIVE = NO
+
+# The EXCLUDE tag can be used to specify files and/or directories that should be
+# excluded from the INPUT source files. This way you can easily exclude a
+# subdirectory from a directory tree whose root is specified with the INPUT tag.
+#
+# Note that relative paths are relative to the directory from which doxygen is
+# run.
+
+EXCLUDE =
+
+# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or
+# directories that are symbolic links (a Unix file system feature) are excluded
+# from the input.
+# The default value is: NO.
+
+EXCLUDE_SYMLINKS = NO
+
+# If the value of the INPUT tag contains directories, you can use the
+# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude
+# certain files from those directories.
+#
+# Note that the wildcards are matched against the file with absolute path, so to
+# exclude all test directories for example use the pattern */test/*
+
+EXCLUDE_PATTERNS =
+
+# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names
+# (namespaces, classes, functions, etc.) that should be excluded from the
+# output. The symbol name can be a fully qualified name, a word, or if the
+# wildcard * is used, a substring. Examples: ANamespace, AClass,
+# AClass::ANamespace, ANamespace::*Test
+#
+# Note that the wildcards are matched against the file with absolute path, so to
+# exclude all test directories use the pattern */test/*
+
+EXCLUDE_SYMBOLS =
+
+# The EXAMPLE_PATH tag can be used to specify one or more files or directories
+# that contain example code fragments that are included (see the \include
+# command).
+
+EXAMPLE_PATH =
+
+# If the value of the EXAMPLE_PATH tag contains directories, you can use the
+# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and
+# *.h) to filter out the source-files in the directories. If left blank all
+# files are included.
+
+EXAMPLE_PATTERNS = *
+
+# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be
+# searched for input files to be used with the \include or \dontinclude commands
+# irrespective of the value of the RECURSIVE tag.
+# The default value is: NO.
+
+EXAMPLE_RECURSIVE = NO
+
+# The IMAGE_PATH tag can be used to specify one or more files or directories
+# that contain images that are to be included in the documentation (see the
+# \image command).
+
+IMAGE_PATH =
+
+# The INPUT_FILTER tag can be used to specify a program that doxygen should
+# invoke to filter for each input file. Doxygen will invoke the filter program
+# by executing (via popen()) the command:
+#
+# <filter> <input-file>
+#
+# where <filter> is the value of the INPUT_FILTER tag, and <input-file> is the
+# name of an input file. Doxygen will then use the output that the filter
+# program writes to standard output. If FILTER_PATTERNS is specified, this tag
+# will be ignored.
+#
+# Note that the filter must not add or remove lines; it is applied before the
+# code is scanned, but not when the output code is generated. If lines are added
+# or removed, the anchors will not be placed correctly.
+
+INPUT_FILTER =
+
+# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern
+# basis. Doxygen will compare the file name with each pattern and apply the
+# filter if there is a match. The filters are a list of the form: pattern=filter
+# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how
+# filters are used. If the FILTER_PATTERNS tag is empty or if none of the
+# patterns match the file name, INPUT_FILTER is applied.
+
+FILTER_PATTERNS =
+
+# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using
+# INPUT_FILTER) will also be used to filter the input files that are used for
+# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES).
+# The default value is: NO.
+
+FILTER_SOURCE_FILES = NO
+
+# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file
+# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and
+# it is also possible to disable source filtering for a specific pattern using
+# *.ext= (so without naming a filter).
+# This tag requires that the tag FILTER_SOURCE_FILES is set to YES.
+
+FILTER_SOURCE_PATTERNS =
+
+# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that
+# is part of the input, its contents will be placed on the main page
+# (index.html). This can be useful if you have a project on for instance GitHub
+# and want to reuse the introduction page also for the doxygen output.
+
+USE_MDFILE_AS_MAINPAGE =
+
+#---------------------------------------------------------------------------
+# Configuration options related to source browsing
+#---------------------------------------------------------------------------
+
+# If the SOURCE_BROWSER tag is set to YES then a list of source files will be
+# generated. Documented entities will be cross-referenced with these sources.
+#
+# Note: To get rid of all source code in the generated output, make sure that
+# also VERBATIM_HEADERS is set to NO.
+# The default value is: NO.
+
+SOURCE_BROWSER = NO
+
+# Setting the INLINE_SOURCES tag to YES will include the body of functions,
+# classes and enums directly into the documentation.
+# The default value is: NO.
+
+INLINE_SOURCES = NO
+
+# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any
+# special comment blocks from generated source code fragments. Normal C, C++ and
+# Fortran comments will always remain visible.
+# The default value is: YES.
+
+STRIP_CODE_COMMENTS = NO
+
+# If the REFERENCED_BY_RELATION tag is set to YES then for each documented
+# function all documented functions referencing it will be listed.
+# The default value is: NO.
+
+REFERENCED_BY_RELATION = NO
+
+# If the REFERENCES_RELATION tag is set to YES then for each documented function
+# all documented entities called/used by that function will be listed.
+# The default value is: NO.
+
+REFERENCES_RELATION = NO
+
+# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set
+# to YES then the hyperlinks from functions in REFERENCES_RELATION and
+# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will
+# link to the documentation.
+# The default value is: YES.
+
+REFERENCES_LINK_SOURCE = YES
+
+# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the
+# source code will show a tooltip with additional information such as prototype,
+# brief description and links to the definition and documentation. Since this
+# will make the HTML file larger and loading of large files a bit slower, you
+# can opt to disable this feature.
+# The default value is: YES.
+# This tag requires that the tag SOURCE_BROWSER is set to YES.
+
+SOURCE_TOOLTIPS = YES
+
+# If the USE_HTAGS tag is set to YES then the references to source code will
+# point to the HTML generated by the htags(1) tool instead of doxygen built-in
+# source browser. The htags tool is part of GNU's global source tagging system
+# (see http://www.gnu.org/software/global/global.html). You will need version
+# 4.8.6 or higher.
+#
+# To use it do the following:
+# - Install the latest version of global
+# - Enable SOURCE_BROWSER and USE_HTAGS in the config file
+# - Make sure the INPUT points to the root of the source tree
+# - Run doxygen as normal
+#
+# Doxygen will invoke htags (and that will in turn invoke gtags), so these
+# tools must be available from the command line (i.e. in the search path).
+#
+# The result: instead of the source browser generated by doxygen, the links to
+# source code will now point to the output of htags.
+# The default value is: NO.
+# This tag requires that the tag SOURCE_BROWSER is set to YES.
+
+USE_HTAGS = NO
+
+# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a
+# verbatim copy of the header file for each class for which an include is
+# specified. Set to NO to disable this.
+# See also: Section \class.
+# The default value is: YES.
+
+VERBATIM_HEADERS = YES
+
+# If the CLANG_ASSISTED_PARSING tag is set to YES then doxygen will use the
+# clang parser (see: http://clang.llvm.org/) for more accurate parsing at the
+# cost of reduced performance. This can be particularly helpful with template
+# rich C++ code for which doxygen's built-in parser lacks the necessary type
+# information.
+# Note: The availability of this option depends on whether or not doxygen was
+# compiled with the --with-libclang option.
+# The default value is: NO.
+
+CLANG_ASSISTED_PARSING = NO
+
+# If clang assisted parsing is enabled you can provide the compiler with command
+# line options that you would normally use when invoking the compiler. Note that
+# the include paths will already be set by doxygen for the files and directories
+# specified with INPUT and INCLUDE_PATH.
+# This tag requires that the tag CLANG_ASSISTED_PARSING is set to YES.
+
+CLANG_OPTIONS =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+
+# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all
+# compounds will be generated. Enable this if the project contains a lot of
+# classes, structs, unions or interfaces.
+# The default value is: YES.
+
+ALPHABETICAL_INDEX = YES
+
+# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in
+# which the alphabetical index list will be split.
+# Minimum value: 1, maximum value: 20, default value: 5.
+# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.
+
+COLS_IN_ALPHA_INDEX = 5
+
+# In case all classes in a project start with a common prefix, all classes will
+# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag
+# can be used to specify a prefix (or a list of prefixes) that should be ignored
+# while generating the index headers.
+# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.
+
+IGNORE_PREFIX =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the HTML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_HTML tag is set to YES, doxygen will generate HTML output
+# The default value is: YES.
+
+GENERATE_HTML = YES
+
+# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it.
+# The default directory is: html.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_OUTPUT = html
+
+# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each
+# generated HTML page (for example: .htm, .php, .asp).
+# The default value is: .html.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_FILE_EXTENSION = .html
+
+# The HTML_HEADER tag can be used to specify a user-defined HTML header file for
+# each generated HTML page. If the tag is left blank doxygen will generate a
+# standard header.
+#
+# To get valid HTML the header file that includes any scripts and style sheets
+# that doxygen needs, which is dependent on the configuration options used (e.g.
+# the setting GENERATE_TREEVIEW). It is highly recommended to start with a
+# default header using
+# doxygen -w html new_header.html new_footer.html new_stylesheet.css
+# YourConfigFile
+# and then modify the file new_header.html. See also section "Doxygen usage"
+# for information on how to generate the default header that doxygen normally
+# uses.
+# Note: The header is subject to change so you typically have to regenerate the
+# default header when upgrading to a newer version of doxygen. For a description
+# of the possible markers and block names see the documentation.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_HEADER =
+
+# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each
+# generated HTML page. If the tag is left blank doxygen will generate a standard
+# footer. See HTML_HEADER for more information on how to generate a default
+# footer and what special commands can be used inside the footer. See also
+# section "Doxygen usage" for information on how to generate the default footer
+# that doxygen normally uses.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_FOOTER =
+
+# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style
+# sheet that is used by each HTML page. It can be used to fine-tune the look of
+# the HTML output. If left blank doxygen will generate a default style sheet.
+# See also section "Doxygen usage" for information on how to generate the style
+# sheet that doxygen normally uses.
+# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as
+# it is more robust and this tag (HTML_STYLESHEET) will in the future become
+# obsolete.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_STYLESHEET =
+
+# The HTML_EXTRA_STYLESHEET tag can be used to specify additional user-defined
+# cascading style sheets that are included after the standard style sheets
+# created by doxygen. Using this option one can overrule certain style aspects.
+# This is preferred over using HTML_STYLESHEET since it does not replace the
+# standard style sheet and is therefore more robust against future updates.
+# Doxygen will copy the style sheet files to the output directory.
+# Note: The order of the extra style sheet files is of importance (e.g. the last
+# style sheet in the list overrules the setting of the previous ones in the
+# list). For an example see the documentation.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_EXTRA_STYLESHEET =
+
+# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or
+# other source files which should be copied to the HTML output directory. Note
+# that these files will be copied to the base HTML output directory. Use the
+# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these
+# files. In the HTML_STYLESHEET file, use the file name only. Also note that the
+# files will be copied as-is; there are no commands or markers available.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_EXTRA_FILES =
+
+# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen
+# will adjust the colors in the style sheet and background images according to
+# this color. Hue is specified as an angle on a colorwheel, see
+# http://en.wikipedia.org/wiki/Hue for more information. For instance the value
+# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300
+# purple, and 360 is red again.
+# Minimum value: 0, maximum value: 359, default value: 220.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_COLORSTYLE_HUE = 220
+
+# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors
+# in the HTML output. For a value of 0 the output will use grayscales only. A
+# value of 255 will produce the most vivid colors.
+# Minimum value: 0, maximum value: 255, default value: 100.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_COLORSTYLE_SAT = 100
+
+# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the
+# luminance component of the colors in the HTML output. Values below 100
+# gradually make the output lighter, whereas values above 100 make the output
+# darker. The value divided by 100 is the actual gamma applied, so 80 represents
+# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not
+# change the gamma.
+# Minimum value: 40, maximum value: 240, default value: 80.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_COLORSTYLE_GAMMA = 80
+
+# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML
+# page will contain the date and time when the page was generated. Setting this
+# to NO can help when comparing the output of multiple runs.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_TIMESTAMP = YES
+
+# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML
+# documentation will contain sections that can be hidden and shown after the
+# page has loaded.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_DYNAMIC_SECTIONS = NO
+
+# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries
+# shown in the various tree structured indices initially; the user can expand
+# and collapse entries dynamically later on. Doxygen will expand the tree to
+# such a level that at most the specified number of entries are visible (unless
+# a fully collapsed tree already exceeds this amount). So setting the number of
+# entries 1 will produce a full collapsed tree by default. 0 is a special value
+# representing an infinite number of entries and will result in a full expanded
+# tree by default.
+# Minimum value: 0, maximum value: 9999, default value: 100.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_INDEX_NUM_ENTRIES = 100
+
+# If the GENERATE_DOCSET tag is set to YES, additional index files will be
+# generated that can be used as input for Apple's Xcode 3 integrated development
+# environment (see: http://developer.apple.com/tools/xcode/), introduced with
+# OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a
+# Makefile in the HTML output directory. Running make will produce the docset in
+# that directory and running make install will install the docset in
+# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at
+# startup. See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html
+# for more information.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_DOCSET = NO
+
+# This tag determines the name of the docset feed. A documentation feed provides
+# an umbrella under which multiple documentation sets from a single provider
+# (such as a company or product suite) can be grouped.
+# The default value is: Doxygen generated docs.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_FEEDNAME = "Doxygen generated docs"
+
+# This tag specifies a string that should uniquely identify the documentation
+# set bundle. This should be a reverse domain-name style string, e.g.
+# com.mycompany.MyDocSet. Doxygen will append .docset to the name.
+# The default value is: org.doxygen.Project.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_BUNDLE_ID = org.doxygen.Project
+
+# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify
+# the documentation publisher. This should be a reverse domain-name style
+# string, e.g. com.mycompany.MyDocSet.documentation.
+# The default value is: org.doxygen.Publisher.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_PUBLISHER_ID = org.doxygen.Publisher
+
+# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher.
+# The default value is: Publisher.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_PUBLISHER_NAME = Publisher
+
+# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three
+# additional HTML index files: index.hhp, index.hhc, and index.hhk. The
+# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop
+# (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on
+# Windows.
+#
+# The HTML Help Workshop contains a compiler that can convert all HTML output
+# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML
+# files are now used as the Windows 98 help format, and will replace the old
+# Windows help format (.hlp) on all Windows platforms in the future. Compressed
+# HTML files also contain an index, a table of contents, and you can search for
+# words in the documentation. The HTML workshop also contains a viewer for
+# compressed HTML files.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_HTMLHELP = NO
+
+# The CHM_FILE tag can be used to specify the file name of the resulting .chm
+# file. You can add a path in front of the file if the result should not be
+# written to the html output directory.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+CHM_FILE =
+
+# The HHC_LOCATION tag can be used to specify the location (absolute path
+# including file name) of the HTML help compiler (hhc.exe). If non-empty,
+# doxygen will try to run the HTML help compiler on the generated index.hhp.
+# The file has to be specified with full path.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+HHC_LOCATION =
+
+# The GENERATE_CHI flag controls if a separate .chi index file is generated
+# (YES) or that it should be included in the master .chm file (NO).
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+GENERATE_CHI = NO
+
+# The CHM_INDEX_ENCODING is used to encode HtmlHelp index (hhk), content (hhc)
+# and project file content.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+CHM_INDEX_ENCODING =
+
+# The BINARY_TOC flag controls whether a binary table of contents is generated
+# (YES) or a normal table of contents (NO) in the .chm file. Furthermore it
+# enables the Previous and Next buttons.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+BINARY_TOC = NO
+
+# The TOC_EXPAND flag can be set to YES to add extra items for group members to
+# the table of contents of the HTML help documentation and to the tree view.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+TOC_EXPAND = NO
+
+# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and
+# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that
+# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help
+# (.qch) of the generated HTML documentation.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_QHP = NO
+
+# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify
+# the file name of the resulting .qch file. The path specified is relative to
+# the HTML output folder.
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QCH_FILE =
+
+# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help
+# Project output. For more information please see Qt Help Project / Namespace
+# (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#namespace).
+# The default value is: org.doxygen.Project.
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_NAMESPACE = org.doxygen.Project
+
+# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt
+# Help Project output. For more information please see Qt Help Project / Virtual
+# Folders (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#virtual-
+# folders).
+# The default value is: doc.
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_VIRTUAL_FOLDER = doc
+
+# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom
+# filter to add. For more information please see Qt Help Project / Custom
+# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-
+# filters).
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_CUST_FILTER_NAME =
+
+# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the
+# custom filter to add. For more information please see Qt Help Project / Custom
+# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-
+# filters).
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_CUST_FILTER_ATTRS =
+
+# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this
+# project's filter section matches. Qt Help Project / Filter Attributes (see:
+# http://qt-project.org/doc/qt-4.8/qthelpproject.html#filter-attributes).
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_SECT_FILTER_ATTRS =
+
+# The QHG_LOCATION tag can be used to specify the location of Qt's
+# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the
+# generated .qhp file.
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHG_LOCATION =
+
+# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be
+# generated, together with the HTML files, they form an Eclipse help plugin. To
+# install this plugin and make it available under the help contents menu in
+# Eclipse, the contents of the directory containing the HTML and XML files needs
+# to be copied into the plugins directory of eclipse. The name of the directory
+# within the plugins directory should be the same as the ECLIPSE_DOC_ID value.
+# After copying Eclipse needs to be restarted before the help appears.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_ECLIPSEHELP = NO
+
+# A unique identifier for the Eclipse help plugin. When installing the plugin
+# the directory name containing the HTML and XML files should also have this
+# name. Each documentation set should have its own identifier.
+# The default value is: org.doxygen.Project.
+# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES.
+
+ECLIPSE_DOC_ID = org.doxygen.Project
+
+# If you want full control over the layout of the generated HTML pages it might
+# be necessary to disable the index and replace it with your own. The
+# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top
+# of each HTML page. A value of NO enables the index and the value YES disables
+# it. Since the tabs in the index contain the same information as the navigation
+# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+DISABLE_INDEX = NO
+
+# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index
+# structure should be generated to display hierarchical information. If the tag
+# value is set to YES, a side panel will be generated containing a tree-like
+# index structure (just like the one that is generated for HTML Help). For this
+# to work a browser that supports JavaScript, DHTML, CSS and frames is required
+# (i.e. any modern browser). Windows users are probably better off using the
+# HTML help feature. Via custom style sheets (see HTML_EXTRA_STYLESHEET) one can
+# further fine-tune the look of the index. As an example, the default style
+# sheet generated by doxygen has an example that shows how to put an image at
+# the root of the tree instead of the PROJECT_NAME. Since the tree basically has
+# the same information as the tab index, you could consider setting
+# DISABLE_INDEX to YES when enabling this option.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_TREEVIEW = NO
+
+# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that
+# doxygen will group on one line in the generated HTML documentation.
+#
+# Note that a value of 0 will completely suppress the enum values from appearing
+# in the overview section.
+# Minimum value: 0, maximum value: 20, default value: 4.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+ENUM_VALUES_PER_LINE = 4
+
+# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used
+# to set the initial width (in pixels) of the frame in which the tree is shown.
+# Minimum value: 0, maximum value: 1500, default value: 250.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+TREEVIEW_WIDTH = 250
+
+# If the EXT_LINKS_IN_WINDOW option is set to YES, doxygen will open links to
+# external symbols imported via tag files in a separate window.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+EXT_LINKS_IN_WINDOW = NO
+
+# Use this tag to change the font size of LaTeX formulas included as images in
+# the HTML documentation. When you change the font size after a successful
+# doxygen run you need to manually remove any form_*.png images from the HTML
+# output directory to force them to be regenerated.
+# Minimum value: 8, maximum value: 50, default value: 10.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+FORMULA_FONTSIZE = 10
+
+# Use the FORMULA_TRANPARENT tag to determine whether or not the images
+# generated for formulas are transparent PNGs. Transparent PNGs are not
+# supported properly for IE 6.0, but are supported on all modern browsers.
+#
+# Note that when changing this option you need to delete any form_*.png files in
+# the HTML output directory before the changes have effect.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+FORMULA_TRANSPARENT = YES
+
+# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see
+# http://www.mathjax.org) which uses client side Javascript for the rendering
+# instead of using pre-rendered bitmaps. Use this if you do not have LaTeX
+# installed or if you want to formulas look prettier in the HTML output. When
+# enabled you may also need to install MathJax separately and configure the path
+# to it using the MATHJAX_RELPATH option.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+USE_MATHJAX = NO
+
+# When MathJax is enabled you can set the default output format to be used for
+# the MathJax output. See the MathJax site (see:
+# http://docs.mathjax.org/en/latest/output.html) for more details.
+# Possible values are: HTML-CSS (which is slower, but has the best
+# compatibility), NativeMML (i.e. MathML) and SVG.
+# The default value is: HTML-CSS.
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_FORMAT = HTML-CSS
+
+# When MathJax is enabled you need to specify the location relative to the HTML
+# output directory using the MATHJAX_RELPATH option. The destination directory
+# should contain the MathJax.js script. For instance, if the mathjax directory
+# is located at the same level as the HTML output directory, then
+# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax
+# Content Delivery Network so you can quickly see the result without installing
+# MathJax. However, it is strongly recommended to install a local copy of
+# MathJax from http://www.mathjax.org before deployment.
+# The default value is: http://cdn.mathjax.org/mathjax/latest.
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_RELPATH = http://cdn.mathjax.org/mathjax/latest
+
+# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax
+# extension names that should be enabled during MathJax rendering. For example
+# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_EXTENSIONS =
+
+# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces
+# of code that will be used on startup of the MathJax code. See the MathJax site
+# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an
+# example see the documentation.
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_CODEFILE =
+
+# When the SEARCHENGINE tag is enabled doxygen will generate a search box for
+# the HTML output. The underlying search engine uses javascript and DHTML and
+# should work on any modern browser. Note that when using HTML help
+# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET)
+# there is already a search function so this one should typically be disabled.
+# For large projects the javascript based search engine can be slow, then
+# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to
+# search using the keyboard; to jump to the search box use <access key> + S
+# (what the <access key> is depends on the OS and browser, but it is typically
+# <CTRL>, <ALT>/<option>, or both). Inside the search box use the <cursor down
+# key> to jump into the search results window, the results can be navigated
+# using the <cursor keys>. Press <Enter> to select an item or <escape> to cancel
+# the search. The filter options can be selected when the cursor is inside the
+# search box by pressing <Shift>+<cursor down>. Also here use the <cursor keys>
+# to select a filter and <Enter> or <escape> to activate or cancel the filter
+# option.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+SEARCHENGINE = YES
+
+# When the SERVER_BASED_SEARCH tag is enabled the search engine will be
+# implemented using a web server instead of a web client using Javascript. There
+# are two flavors of web server based searching depending on the EXTERNAL_SEARCH
+# setting. When disabled, doxygen will generate a PHP script for searching and
+# an index file used by the script. When EXTERNAL_SEARCH is enabled the indexing
+# and searching needs to be provided by external tools. See the section
+# "External Indexing and Searching" for details.
+# The default value is: NO.
+# This tag requires that the tag SEARCHENGINE is set to YES.
+
+SERVER_BASED_SEARCH = NO
+
+# When EXTERNAL_SEARCH tag is enabled doxygen will no longer generate the PHP
+# script for searching. Instead the search results are written to an XML file
+# which needs to be processed by an external indexer. Doxygen will invoke an
+# external search engine pointed to by the SEARCHENGINE_URL option to obtain the
+# search results.
+#
+# Doxygen ships with an example indexer (doxyindexer) and search engine
+# (doxysearch.cgi) which are based on the open source search engine library
+# Xapian (see: http://xapian.org/).
+#
+# See the section "External Indexing and Searching" for details.
+# The default value is: NO.
+# This tag requires that the tag SEARCHENGINE is set to YES.
+
+EXTERNAL_SEARCH = NO
+
+# The SEARCHENGINE_URL should point to a search engine hosted by a web server
+# which will return the search results when EXTERNAL_SEARCH is enabled.
+#
+# Doxygen ships with an example indexer (doxyindexer) and search engine
+# (doxysearch.cgi) which are based on the open source search engine library
+# Xapian (see: http://xapian.org/). See the section "External Indexing and
+# Searching" for details.
+# This tag requires that the tag SEARCHENGINE is set to YES.
+
+SEARCHENGINE_URL =
+
+# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the unindexed
+# search data is written to a file for indexing by an external tool. With the
+# SEARCHDATA_FILE tag the name of this file can be specified.
+# The default file is: searchdata.xml.
+# This tag requires that the tag SEARCHENGINE is set to YES.
+
+SEARCHDATA_FILE = searchdata.xml
+
+# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the
+# EXTERNAL_SEARCH_ID tag can be used as an identifier for the project. This is
+# useful in combination with EXTRA_SEARCH_MAPPINGS to search through multiple
+# projects and redirect the results back to the right project.
+# This tag requires that the tag SEARCHENGINE is set to YES.
+
+EXTERNAL_SEARCH_ID =
+
+# The EXTRA_SEARCH_MAPPINGS tag can be used to enable searching through doxygen
+# projects other than the one defined by this configuration file, but that are
+# all added to the same external search index. Each project needs to have a
+# unique id set via EXTERNAL_SEARCH_ID. The search mapping then maps the id of
+# to a relative location where the documentation can be found. The format is:
+# EXTRA_SEARCH_MAPPINGS = tagname1=loc1 tagname2=loc2 ...
+# This tag requires that the tag SEARCHENGINE is set to YES.
+
+EXTRA_SEARCH_MAPPINGS =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_LATEX tag is set to YES, doxygen will generate LaTeX output.
+# The default value is: YES.
+
+GENERATE_LATEX = NO
+
+# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it.
+# The default directory is: latex.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_OUTPUT = latex
+
+# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be
+# invoked.
+#
+# Note that when enabling USE_PDFLATEX this option is only used for generating
+# bitmaps for formulas in the HTML output, but not in the Makefile that is
+# written to the output directory.
+# The default file is: latex.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_CMD_NAME = latex
+
+# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to generate
+# index for LaTeX.
+# The default file is: makeindex.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+MAKEINDEX_CMD_NAME = makeindex
+
+# If the COMPACT_LATEX tag is set to YES, doxygen generates more compact LaTeX
+# documents. This may be useful for small projects and may help to save some
+# trees in general.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+COMPACT_LATEX = NO
+
+# The PAPER_TYPE tag can be used to set the paper type that is used by the
+# printer.
+# Possible values are: a4 (210 x 297 mm), letter (8.5 x 11 inches), legal (8.5 x
+# 14 inches) and executive (7.25 x 10.5 inches).
+# The default value is: a4.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+PAPER_TYPE = a4
+
+# The EXTRA_PACKAGES tag can be used to specify one or more LaTeX package names
+# that should be included in the LaTeX output. To get the times font for
+# instance you can specify
+# EXTRA_PACKAGES=times
+# If left blank no extra packages will be included.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+EXTRA_PACKAGES =
+
+# The LATEX_HEADER tag can be used to specify a personal LaTeX header for the
+# generated LaTeX document. The header should contain everything until the first
+# chapter. If it is left blank doxygen will generate a standard header. See
+# section "Doxygen usage" for information on how to let doxygen write the
+# default header to a separate file.
+#
+# Note: Only use a user-defined header if you know what you are doing! The
+# following commands have a special meaning inside the header: $title,
+# $datetime, $date, $doxygenversion, $projectname, $projectnumber,
+# $projectbrief, $projectlogo. Doxygen will replace $title with the empty
+# string, for the replacement values of the other commands the user is referred
+# to HTML_HEADER.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_HEADER =
+
+# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for the
+# generated LaTeX document. The footer should contain everything after the last
+# chapter. If it is left blank doxygen will generate a standard footer. See
+# LATEX_HEADER for more information on how to generate a default footer and what
+# special commands can be used inside the footer.
+#
+# Note: Only use a user-defined footer if you know what you are doing!
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_FOOTER =
+
+# The LATEX_EXTRA_STYLESHEET tag can be used to specify additional user-defined
+# LaTeX style sheets that are included after the standard style sheets created
+# by doxygen. Using this option one can overrule certain style aspects. Doxygen
+# will copy the style sheet files to the output directory.
+# Note: The order of the extra style sheet files is of importance (e.g. the last
+# style sheet in the list overrules the setting of the previous ones in the
+# list).
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_EXTRA_STYLESHEET =
+
+# The LATEX_EXTRA_FILES tag can be used to specify one or more extra images or
+# other source files which should be copied to the LATEX_OUTPUT output
+# directory. Note that the files will be copied as-is; there are no commands or
+# markers available.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_EXTRA_FILES =
+
+# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated is
+# prepared for conversion to PDF (using ps2pdf or pdflatex). The PDF file will
+# contain links (just like the HTML output) instead of page references. This
+# makes the output suitable for online browsing using a PDF viewer.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+PDF_HYPERLINKS = YES
+
+# If the USE_PDFLATEX tag is set to YES, doxygen will use pdflatex to generate
+# the PDF file directly from the LaTeX files. Set this option to YES, to get a
+# higher quality PDF documentation.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+USE_PDFLATEX = YES
+
+# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \batchmode
+# command to the generated LaTeX files. This will instruct LaTeX to keep running
+# if errors occur, instead of asking the user for help. This option is also used
+# when generating formulas in HTML.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_BATCHMODE = NO
+
+# If the LATEX_HIDE_INDICES tag is set to YES then doxygen will not include the
+# index chapters (such as File Index, Compound Index, etc.) in the output.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_HIDE_INDICES = NO
+
+# If the LATEX_SOURCE_CODE tag is set to YES then doxygen will include source
+# code with syntax highlighting in the LaTeX output.
+#
+# Note that which sources are shown also depends on other settings such as
+# SOURCE_BROWSER.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_SOURCE_CODE = NO
+
+# The LATEX_BIB_STYLE tag can be used to specify the style to use for the
+# bibliography, e.g. plainnat, or ieeetr. See
+# http://en.wikipedia.org/wiki/BibTeX and \cite for more info.
+# The default value is: plain.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_BIB_STYLE = plain
+
+#---------------------------------------------------------------------------
+# Configuration options related to the RTF output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_RTF tag is set to YES, doxygen will generate RTF output. The
+# RTF output is optimized for Word 97 and may not look too pretty with other RTF
+# readers/editors.
+# The default value is: NO.
+
+GENERATE_RTF = NO
+
+# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it.
+# The default directory is: rtf.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+RTF_OUTPUT = rtf
+
+# If the COMPACT_RTF tag is set to YES, doxygen generates more compact RTF
+# documents. This may be useful for small projects and may help to save some
+# trees in general.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+COMPACT_RTF = NO
+
+# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated will
+# contain hyperlink fields. The RTF file will contain links (just like the HTML
+# output) instead of page references. This makes the output suitable for online
+# browsing using Word or some other Word compatible readers that support those
+# fields.
+#
+# Note: WordPad (write) and others do not support links.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+RTF_HYPERLINKS = NO
+
+# Load stylesheet definitions from file. Syntax is similar to doxygen's config
+# file, i.e. a series of assignments. You only have to provide replacements,
+# missing definitions are set to their default value.
+#
+# See also section "Doxygen usage" for information on how to generate the
+# default style sheet that doxygen normally uses.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+RTF_STYLESHEET_FILE =
+
+# Set optional variables used in the generation of an RTF document. Syntax is
+# similar to doxygen's config file. A template extensions file can be generated
+# using doxygen -e rtf extensionFile.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+RTF_EXTENSIONS_FILE =
+
+# If the RTF_SOURCE_CODE tag is set to YES then doxygen will include source code
+# with syntax highlighting in the RTF output.
+#
+# Note that which sources are shown also depends on other settings such as
+# SOURCE_BROWSER.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+RTF_SOURCE_CODE = NO
+
+#---------------------------------------------------------------------------
+# Configuration options related to the man page output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_MAN tag is set to YES, doxygen will generate man pages for
+# classes and files.
+# The default value is: NO.
+
+GENERATE_MAN = NO
+
+# The MAN_OUTPUT tag is used to specify where the man pages will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it. A directory man3 will be created inside the directory specified by
+# MAN_OUTPUT.
+# The default directory is: man.
+# This tag requires that the tag GENERATE_MAN is set to YES.
+
+MAN_OUTPUT = man
+
+# The MAN_EXTENSION tag determines the extension that is added to the generated
+# man pages. In case the manual section does not start with a number, the number
+# 3 is prepended. The dot (.) at the beginning of the MAN_EXTENSION tag is
+# optional.
+# The default value is: .3.
+# This tag requires that the tag GENERATE_MAN is set to YES.
+
+MAN_EXTENSION = .3
+
+# The MAN_SUBDIR tag determines the name of the directory created within
+# MAN_OUTPUT in which the man pages are placed. If defaults to man followed by
+# MAN_EXTENSION with the initial . removed.
+# This tag requires that the tag GENERATE_MAN is set to YES.
+
+MAN_SUBDIR =
+
+# If the MAN_LINKS tag is set to YES and doxygen generates man output, then it
+# will generate one additional man file for each entity documented in the real
+# man page(s). These additional files only source the real man page, but without
+# them the man command would be unable to find the correct page.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_MAN is set to YES.
+
+MAN_LINKS = NO
+
+#---------------------------------------------------------------------------
+# Configuration options related to the XML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_XML tag is set to YES, doxygen will generate an XML file that
+# captures the structure of the code including all documentation.
+# The default value is: NO.
+
+GENERATE_XML = NO
+
+# The XML_OUTPUT tag is used to specify where the XML pages will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it.
+# The default directory is: xml.
+# This tag requires that the tag GENERATE_XML is set to YES.
+
+XML_OUTPUT = xml
+
+# If the XML_PROGRAMLISTING tag is set to YES, doxygen will dump the program
+# listings (including syntax highlighting and cross-referencing information) to
+# the XML output. Note that enabling this will significantly increase the size
+# of the XML output.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_XML is set to YES.
+
+XML_PROGRAMLISTING = YES
+
+#---------------------------------------------------------------------------
+# Configuration options related to the DOCBOOK output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_DOCBOOK tag is set to YES, doxygen will generate Docbook files
+# that can be used to generate PDF.
+# The default value is: NO.
+
+GENERATE_DOCBOOK = NO
+
+# The DOCBOOK_OUTPUT tag is used to specify where the Docbook pages will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be put in
+# front of it.
+# The default directory is: docbook.
+# This tag requires that the tag GENERATE_DOCBOOK is set to YES.
+
+DOCBOOK_OUTPUT = docbook
+
+# If the DOCBOOK_PROGRAMLISTING tag is set to YES, doxygen will include the
+# program listings (including syntax highlighting and cross-referencing
+# information) to the DOCBOOK output. Note that enabling this will significantly
+# increase the size of the DOCBOOK output.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_DOCBOOK is set to YES.
+
+DOCBOOK_PROGRAMLISTING = NO
+
+#---------------------------------------------------------------------------
+# Configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_AUTOGEN_DEF tag is set to YES, doxygen will generate an
+# AutoGen Definitions (see http://autogen.sf.net) file that captures the
+# structure of the code including all documentation. Note that this feature is
+# still experimental and incomplete at the moment.
+# The default value is: NO.
+
+GENERATE_AUTOGEN_DEF = NO
+
+#---------------------------------------------------------------------------
+# Configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_PERLMOD tag is set to YES, doxygen will generate a Perl module
+# file that captures the structure of the code including all documentation.
+#
+# Note that this feature is still experimental and incomplete at the moment.
+# The default value is: NO.
+
+GENERATE_PERLMOD = NO
+
+# If the PERLMOD_LATEX tag is set to YES, doxygen will generate the necessary
+# Makefile rules, Perl scripts and LaTeX code to be able to generate PDF and DVI
+# output from the Perl module output.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_PERLMOD is set to YES.
+
+PERLMOD_LATEX = NO
+
+# If the PERLMOD_PRETTY tag is set to YES, the Perl module output will be nicely
+# formatted so it can be parsed by a human reader. This is useful if you want to
+# understand what is going on. On the other hand, if this tag is set to NO, the
+# size of the Perl module output will be much smaller and Perl will parse it
+# just the same.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_PERLMOD is set to YES.
+
+PERLMOD_PRETTY = YES
+
+# The names of the make variables in the generated doxyrules.make file are
+# prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. This is useful
+# so different doxyrules.make files included by the same Makefile don't
+# overwrite each other's variables.
+# This tag requires that the tag GENERATE_PERLMOD is set to YES.
+
+PERLMOD_MAKEVAR_PREFIX =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+
+# If the ENABLE_PREPROCESSING tag is set to YES, doxygen will evaluate all
+# C-preprocessor directives found in the sources and include files.
+# The default value is: YES.
+
+ENABLE_PREPROCESSING = YES
+
+# If the MACRO_EXPANSION tag is set to YES, doxygen will expand all macro names
+# in the source code. If set to NO, only conditional compilation will be
+# performed. Macro expansion can be done in a controlled way by setting
+# EXPAND_ONLY_PREDEF to YES.
+# The default value is: NO.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
+
+MACRO_EXPANSION = NO
+
+# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES then
+# the macro expansion is limited to the macros specified with the PREDEFINED and
+# EXPAND_AS_DEFINED tags.
+# The default value is: NO.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
+
+EXPAND_ONLY_PREDEF = NO
+
+# If the SEARCH_INCLUDES tag is set to YES, the include files in the
+# INCLUDE_PATH will be searched if a #include is found.
+# The default value is: YES.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
+
+SEARCH_INCLUDES = YES
+
+# The INCLUDE_PATH tag can be used to specify one or more directories that
+# contain include files that are not input files but should be processed by the
+# preprocessor.
+# This tag requires that the tag SEARCH_INCLUDES is set to YES.
+
+INCLUDE_PATH =
+
+# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard
+# patterns (like *.h and *.hpp) to filter out the header-files in the
+# directories. If left blank, the patterns specified with FILE_PATTERNS will be
+# used.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
+
+INCLUDE_FILE_PATTERNS =
+
+# The PREDEFINED tag can be used to specify one or more macro names that are
+# defined before the preprocessor is started (similar to the -D option of e.g.
+# gcc). The argument of the tag is a list of macros of the form: name or
+# name=definition (no spaces). If the definition and the "=" are omitted, "=1"
+# is assumed. To prevent a macro definition from being undefined via #undef or
+# recursively expanded use the := operator instead of the = operator.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
+
+PREDEFINED =
+
+# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then this
+# tag can be used to specify a list of macro names that should be expanded. The
+# macro definition that is found in the sources will be used. Use the PREDEFINED
+# tag if you want to use a different macro definition that overrules the
+# definition found in the source code.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
+
+EXPAND_AS_DEFINED =
+
+# If the SKIP_FUNCTION_MACROS tag is set to YES then doxygen's preprocessor will
+# remove all references to function-like macros that are alone on a line, have
+# an all uppercase name, and do not end with a semicolon. Such function macros
+# are typically used for boiler-plate code, and will confuse the parser if not
+# removed.
+# The default value is: YES.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
+
+SKIP_FUNCTION_MACROS = YES
+
+#---------------------------------------------------------------------------
+# Configuration options related to external references
+#---------------------------------------------------------------------------
+
+# The TAGFILES tag can be used to specify one or more tag files. For each tag
+# file the location of the external documentation should be added. The format of
+# a tag file without this location is as follows:
+# TAGFILES = file1 file2 ...
+# Adding location for the tag files is done as follows:
+# TAGFILES = file1=loc1 "file2 = loc2" ...
+# where loc1 and loc2 can be relative or absolute paths or URLs. See the
+# section "Linking to external documentation" for more information about the use
+# of tag files.
+# Note: Each tag file must have a unique name (where the name does NOT include
+# the path). If a tag file is not located in the directory in which doxygen is
+# run, you must also specify the path to the tagfile here.
+
+TAGFILES =
+
+# When a file name is specified after GENERATE_TAGFILE, doxygen will create a
+# tag file that is based on the input files it reads. See section "Linking to
+# external documentation" for more information about the usage of tag files.
+
+GENERATE_TAGFILE =
+
+# If the ALLEXTERNALS tag is set to YES, all external class will be listed in
+# the class index. If set to NO, only the inherited external classes will be
+# listed.
+# The default value is: NO.
+
+ALLEXTERNALS = NO
+
+# If the EXTERNAL_GROUPS tag is set to YES, all external groups will be listed
+# in the modules index. If set to NO, only the current project's groups will be
+# listed.
+# The default value is: YES.
+
+EXTERNAL_GROUPS = YES
+
+# If the EXTERNAL_PAGES tag is set to YES, all external pages will be listed in
+# the related pages index. If set to NO, only the current project's pages will
+# be listed.
+# The default value is: YES.
+
+EXTERNAL_PAGES = YES
+
+# The PERL_PATH should be the absolute path and name of the perl script
+# interpreter (i.e. the result of 'which perl').
+# The default file (with absolute path) is: /usr/bin/perl.
+
+PERL_PATH = /usr/bin/perl
+
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+
+# If the CLASS_DIAGRAMS tag is set to YES, doxygen will generate a class diagram
+# (in HTML and LaTeX) for classes with base or super classes. Setting the tag to
+# NO turns the diagrams off. Note that this option also works with HAVE_DOT
+# disabled, but it is recommended to install and use dot, since it yields more
+# powerful graphs.
+# The default value is: YES.
+
+CLASS_DIAGRAMS = YES
+
+# You can define message sequence charts within doxygen comments using the \msc
+# command. Doxygen will then run the mscgen tool (see:
+# http://www.mcternan.me.uk/mscgen/)) to produce the chart and insert it in the
+# documentation. The MSCGEN_PATH tag allows you to specify the directory where
+# the mscgen tool resides. If left empty the tool is assumed to be found in the
+# default search path.
+
+MSCGEN_PATH =
+
+# You can include diagrams made with dia in doxygen documentation. Doxygen will
+# then run dia to produce the diagram and insert it in the documentation. The
+# DIA_PATH tag allows you to specify the directory where the dia binary resides.
+# If left empty dia is assumed to be found in the default search path.
+
+DIA_PATH =
+
+# If set to YES the inheritance and collaboration graphs will hide inheritance
+# and usage relations if the target is undocumented or is not a class.
+# The default value is: YES.
+
+HIDE_UNDOC_RELATIONS = YES
+
+# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is
+# available from the path. This tool is part of Graphviz (see:
+# http://www.graphviz.org/), a graph visualization toolkit from AT&T and Lucent
+# Bell Labs. The other options in this section have no effect if this option is
+# set to NO
+# The default value is: NO.
+
+HAVE_DOT = YES
+
+# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is allowed
+# to run in parallel. When set to 0 doxygen will base this on the number of
+# processors available in the system. You can set it explicitly to a value
+# larger than 0 to get control over the balance between CPU load and processing
+# speed.
+# Minimum value: 0, maximum value: 32, default value: 0.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_NUM_THREADS = 0
+
+# When you want a differently looking font in the dot files that doxygen
+# generates you can specify the font name using DOT_FONTNAME. You need to make
+# sure dot is able to find the font, which can be done by putting it in a
+# standard location or by setting the DOTFONTPATH environment variable or by
+# setting DOT_FONTPATH to the directory containing the font.
+# The default value is: Helvetica.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_FONTNAME = Helvetica
+
+# The DOT_FONTSIZE tag can be used to set the size (in points) of the font of
+# dot graphs.
+# Minimum value: 4, maximum value: 24, default value: 10.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_FONTSIZE = 10
+
+# By default doxygen will tell dot to use the default font as specified with
+# DOT_FONTNAME. If you specify a different font using DOT_FONTNAME you can set
+# the path where dot can find it using this tag.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_FONTPATH =
+
+# If the CLASS_GRAPH tag is set to YES then doxygen will generate a graph for
+# each documented class showing the direct and indirect inheritance relations.
+# Setting this tag to YES will force the CLASS_DIAGRAMS tag to NO.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+CLASS_GRAPH = YES
+
+# If the COLLABORATION_GRAPH tag is set to YES then doxygen will generate a
+# graph for each documented class showing the direct and indirect implementation
+# dependencies (inheritance, containment, and class references variables) of the
+# class with other documented classes.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+COLLABORATION_GRAPH = YES
+
+# If the GROUP_GRAPHS tag is set to YES then doxygen will generate a graph for
+# groups, showing the direct groups dependencies.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+GROUP_GRAPHS = YES
+
+# If the UML_LOOK tag is set to YES, doxygen will generate inheritance and
+# collaboration diagrams in a style similar to the OMG's Unified Modeling
+# Language.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+UML_LOOK = NO
+
+# If the UML_LOOK tag is enabled, the fields and methods are shown inside the
+# class node. If there are many fields or methods and many nodes the graph may
+# become too big to be useful. The UML_LIMIT_NUM_FIELDS threshold limits the
+# number of items for each type to make the size more manageable. Set this to 0
+# for no limit. Note that the threshold may be exceeded by 50% before the limit
+# is enforced. So when you set the threshold to 10, up to 15 fields may appear,
+# but if the number exceeds 15, the total amount of fields shown is limited to
+# 10.
+# Minimum value: 0, maximum value: 100, default value: 10.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+UML_LIMIT_NUM_FIELDS = 10
+
+# If the TEMPLATE_RELATIONS tag is set to YES then the inheritance and
+# collaboration graphs will show the relations between templates and their
+# instances.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+TEMPLATE_RELATIONS = NO
+
+# If the INCLUDE_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are set to
+# YES then doxygen will generate a graph for each documented file showing the
+# direct and indirect include dependencies of the file with other documented
+# files.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+INCLUDE_GRAPH = YES
+
+# If the INCLUDED_BY_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are
+# set to YES then doxygen will generate a graph for each documented file showing
+# the direct and indirect include dependencies of the file with other documented
+# files.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+INCLUDED_BY_GRAPH = YES
+
+# If the CALL_GRAPH tag is set to YES then doxygen will generate a call
+# dependency graph for every global function or class method.
+#
+# Note that enabling this option will significantly increase the time of a run.
+# So in most cases it will be better to enable call graphs for selected
+# functions only using the \callgraph command.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+CALL_GRAPH = YES
+
+# If the CALLER_GRAPH tag is set to YES then doxygen will generate a caller
+# dependency graph for every global function or class method.
+#
+# Note that enabling this option will significantly increase the time of a run.
+# So in most cases it will be better to enable caller graphs for selected
+# functions only using the \callergraph command.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+CALLER_GRAPH = YES
+
+# If the GRAPHICAL_HIERARCHY tag is set to YES then doxygen will graphical
+# hierarchy of all classes instead of a textual one.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+GRAPHICAL_HIERARCHY = YES
+
+# If the DIRECTORY_GRAPH tag is set to YES then doxygen will show the
+# dependencies a directory has on other directories in a graphical way. The
+# dependency relations are determined by the #include relations between the
+# files in the directories.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DIRECTORY_GRAPH = YES
+
+# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images
+# generated by dot.
+# Note: If you choose svg you need to set HTML_FILE_EXTENSION to xhtml in order
+# to make the SVG files visible in IE 9+ (other browsers do not have this
+# requirement).
+# Possible values are: png, jpg, gif and svg.
+# The default value is: png.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_IMAGE_FORMAT = png
+
+# If DOT_IMAGE_FORMAT is set to svg, then this option can be set to YES to
+# enable generation of interactive SVG images that allow zooming and panning.
+#
+# Note that this requires a modern browser other than Internet Explorer. Tested
+# and working are Firefox, Chrome, Safari, and Opera.
+# Note: For IE 9+ you need to set HTML_FILE_EXTENSION to xhtml in order to make
+# the SVG files visible. Older versions of IE do not have SVG support.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+INTERACTIVE_SVG = NO
+
+# The DOT_PATH tag can be used to specify the path where the dot tool can be
+# found. If left blank, it is assumed the dot tool can be found in the path.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_PATH =
+
+# The DOTFILE_DIRS tag can be used to specify one or more directories that
+# contain dot files that are included in the documentation (see the \dotfile
+# command).
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOTFILE_DIRS =
+
+# The MSCFILE_DIRS tag can be used to specify one or more directories that
+# contain msc files that are included in the documentation (see the \mscfile
+# command).
+
+MSCFILE_DIRS =
+
+# The DIAFILE_DIRS tag can be used to specify one or more directories that
+# contain dia files that are included in the documentation (see the \diafile
+# command).
+
+DIAFILE_DIRS =
+
+# When using plantuml, the PLANTUML_JAR_PATH tag should be used to specify the
+# path where java can find the plantuml.jar file. If left blank, it is assumed
+# PlantUML is not used or called during a preprocessing step. Doxygen will
+# generate a warning when it encounters a \startuml command in this case and
+# will not generate output for the diagram.
+
+PLANTUML_JAR_PATH =
+
+# When using plantuml, the specified paths are searched for files specified by
+# the !include statement in a plantuml block.
+
+PLANTUML_INCLUDE_PATH =
+
+# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of nodes
+# that will be shown in the graph. If the number of nodes in a graph becomes
+# larger than this value, doxygen will truncate the graph, which is visualized
+# by representing a node as a red box. Note that doxygen if the number of direct
+# children of the root node in a graph is already larger than
+# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note that
+# the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH.
+# Minimum value: 0, maximum value: 10000, default value: 50.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_GRAPH_MAX_NODES = 50
+
+# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the graphs
+# generated by dot. A depth value of 3 means that only nodes reachable from the
+# root by following a path via at most 3 edges will be shown. Nodes that lay
+# further from the root node will be omitted. Note that setting this option to 1
+# or 2 may greatly reduce the computation time needed for large code bases. Also
+# note that the size of a graph can be further restricted by
+# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction.
+# Minimum value: 0, maximum value: 1000, default value: 0.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+MAX_DOT_GRAPH_DEPTH = 0
+
+# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent
+# background. This is disabled by default, because dot on Windows does not seem
+# to support this out of the box.
+#
+# Warning: Depending on the platform used, enabling this option may lead to
+# badly anti-aliased labels on the edges of a graph (i.e. they become hard to
+# read).
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_TRANSPARENT = NO
+
+# Set the DOT_MULTI_TARGETS tag to YES to allow dot to generate multiple output
+# files in one run (i.e. multiple -o and -T options on the command line). This
+# makes dot run faster, but since only newer versions of dot (>1.8.10) support
+# this, this feature is disabled by default.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_MULTI_TARGETS = NO
+
+# If the GENERATE_LEGEND tag is set to YES doxygen will generate a legend page
+# explaining the meaning of the various boxes and arrows in the dot generated
+# graphs.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+GENERATE_LEGEND = YES
+
+# If the DOT_CLEANUP tag is set to YES, doxygen will remove the intermediate dot
+# files that are used to generate the various graphs.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_CLEANUP = YES
diff -r 000000000000 -r 01f31e923fe2 docs/ENABLE_AUTOMATION.md --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/docs/ENABLE_AUTOMATION.md Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +# Enable Automation Features +1. Update the interface software to a version at or above 0241 +1. Copy an empty text file called ``auto_on.cfg`` to the DAPLink MSD drive while the reset button is held. +1. Release the reset button when the drive unmounts. When it remounts, confirm "Automation Allowed" is set to 1 in ``details.txt`` +1. Update the bootloader software to a version at or above 0241 +1. Confirm that the ``start_bl.act`` MSD command causes the device to enter bootloader mode, and that the ``start_if.act`` command causes the device to enter interface mode. See [MSD Commands](MSD_COMMANDS.md) \ No newline at end of file
diff -r 000000000000 -r 01f31e923fe2 docs/MSD_COMMANDS.md --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/docs/MSD_COMMANDS.md Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,84 @@ +# MSD Commands + +DAPLink allows you to give it some simple commands via its MSD interface. By +copying a file with a certain name to the root of the DAPLink MSD drive, you +can get DAPLink to either perform an action or configure a flash-persisted +option. The contents of the file are ignored; you can pass it an empty file. + +MSD commands only work if you are either holding down the RESET button +when you add the file to the MSD drive, or if you've turned on DAPLink's +automation-allowed mode. Of course, the way you turn on automation-allowed +mode is via an MSD command (see below). So, you'll either hold the RESET +button each time you invoke an MSD command or you'll do so only once to turn +on automation-allowed mode. The automation-allowed mode is saved in flash and +so it persists across board reboots. + +By convention, files that end with ``.act`` trigger an action; files that end +with ``.cfg`` configure a behavior. The mechanism is case-insensitive. + +Every command completes by remounting the DAPLink MSD drive. Every command +is supported in both interface and bootloader mode. + +### Action Commands + +``start_bl.act`` This file will force DAPLink to remount in bootloader mode. +It is equivalent to unplugging the USB cable, and plugging it back in while +holding the RESET button. This command has no effect if DAPLink is already +in bootloader mode. + +``start_if.act`` This file will force DAPLink to remount in interface mode. It +is equivalent to unplugging the USB cable and plugging it back in. This command +has no effect if DAPLink is already in interface mode. + +``assert.act`` This file can be used to test DAPLink's assert utility. When you +copy this file to the DAPLink MSD drive, DAPLink generates a call to the +util_assert() method. An assert call causes the DAPLink MSD drive to remount +with an additional file, ``ASSERT.TXT``, appearing at the root of the drive. This file +details where the assertion failure occurred (source file, line number). An +assert call is a no-op if there is already an outstanding assert failure (there +can only be one). The outstanding assertion failure can be cleared by deleting +``ASSERT.TXT``. The deletion causes a remount of the DAPLink MSD drive. In actuality, +any file operation (addition, deletion, content change) could be used to trigger +a DAPLink command. Deleting ``ASSERT.TXT`` is actually a DAPLink MSD command in its +own right. + +``refresh.act`` This file forces a remount of the DAPLink MSD drive. + +``erase.act`` This file triggers an erase of the target's flash. + +``msd_off.act`` Mass storage device can be disabled by this file command regardless of presence of target flash algo for drag and drop. MSD will always be disabled without the target flash algo. + +``msd_on.act`` Mass storage device can be enabled back by this file command on bootloader mode only if there is a target flash algo. + +``page_off.act`` This file temporary enables page programming and chip erasing until the next restart occurred for drag and drop. + +``page_on.act`` This file temporary enables page programming and sector erasing until the next restart occurred for drag and drop. + +### Configuration Commands + +``auto_rst.cfg`` This file will turn on Auto Reset mode. In this mode, +a reset is performed at the end of the programming sequence. From the +user's perspective, the program starts running as soon as programming +completes. The default behavior is for Auto Reset to be off. This means that +after programming, the application is left halted and does not run. Note that +this mode does not affect what happens when you update the Hardware +Interface Circuit firmware itself (DAPLink) via the DAPLink MSD drive in +bootloader mode. + +``hard_rst.cfg`` This file turns off Auto Reset mode. Auto Reset mode is off by +default. + + +``auto_on.cfg`` This file turns on automation-allowed mode. In this mode, DAPLink +MSD commands can be triggered without needing to hold down the RESET button. Also, +bootloader updates are allowed only in automation-allowed mode. + +``auto_off.cfg`` This file turns off automation-allowed mode. This mode +is off by default + + +``ovfl_on.cfg`` This file turns on serial overflow reporting. If the host PC is not reading +data fast enough from DAPLink and an overflow occurs the text ```<DAPLink:Overflow>``` +will show up in the serial data. Serial overflow reporting is turned off by default. + +``ovfl_off.cfg`` This file turns off serial overflow reporting.
diff -r 000000000000 -r 01f31e923fe2 docs/PORT_BOARD.md
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/docs/PORT_BOARD.md Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,144 @@
+# Adding A New Board
+A board is composed of a Hardware Interface Circuit and target MCU. To create a new board build a description needs to be added to `projects.yaml`. The yaml descriptions are used to create modules that can be inherited. Create a new board build by adding the product name and the required modules. eg: if the HIC is OpenSDA based on the NXP MK20D50 MCU
+
+```yaml
+ k20dx_myboardname_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/myboardname.yaml
+```
+
+Next create a new file in the `records/board` directory called myboardname.yaml. This file defines the target family MCU and allows overrideable board parameters to be configured. The target family MCU in this example exists and is a Nordic nRF51822 (16k RAM variant). More than one target/family can be added to the project and the family can be retargeted by family ID. See `Post-build Board ID and Family ID` section.
+
+```yaml
+common:
+ sources:
+ board:
+ - source/board/myboardname.c
+ family:
+ - source/family/nordic/nrf51822/target_16.c
+ - source/family/nordic/target_reset_nrf51.c
+```
+
+This assumes there is already target support present in the codebase. If adding a new target family is needed, additional steps in [Porting target family guide](PORT_TARGET_FAMILY.md) will be needed. If the target support exists `source/board/myboardname.c` needs creation with a BOARD ID. If you're developing a custom or non-official Mbed platform, then can use any BOARD ID and the `mbedls` [mocking feature](https://github.com/ARMmbed/mbed-os-tools/blob/master/packages/mbed-ls/README.md#mocking-renaming-platforms).
+```c
+/**
+ * @file myboard.c
+ * @brief board_info api for my board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .board_id = "0x240",
+ .family_id = kStub_HWReset_FamilyID,
+ .flags = kEnablePageErase|kEnableUnderResetConnect,
+ .target_cfg = &target_device,
+};
+```
+The complete fields of board_info api with description is in `source/target/target_board.h`.
+```c
+// Flags for board_info
+enum {
+ kEnablePageErase = 1, /*!< Enable page programming and sector erase for drag and drop */
+ kEnableUnderResetConnect = 1<<1, /*!< Enable under reset connection when enabling debug mode */
+};
+
+typedef struct __attribute__((__packed__)) board_info {
+ uint16_t infoVersion; /*!< Version number of the board */
+ uint16_t family_id; /*!< Use to select target family from defined target family ids */
+ char board_id[5]; /*!< 4-char board ID plus null terminator */
+ uint8_t _padding[3];
+ uint32_t flags; /*!< Combination of kEnablePageErase and kEnableUnderResetConnect */
+ target_cfg_t *target_cfg; /*!< Specific chip configuration for the target and enables MSD when non-NULL */
+
+ // fields used by MSD
+ vfs_filename_t daplink_url_name; /*!< Customize the URL file name */
+ vfs_filename_t daplink_drive_name; /*!< Customize the MSD DAPLink drive name */
+ char daplink_target_url[64]; /*!< Customize the target url in DETAILS.TXT */
+
+ // some specific board initilization
+ void (*prerun_board_config)(void); /*!< Specific board debug/ID related initialization */
+ void (*swd_set_target_reset)(uint8_t asserted); /*!< Boards can customize how to send reset to the target precedence over target family */
+ uint8_t (*target_set_state)(TARGET_RESET_STATE state); /*!< Boards can customize target debug states in target_reset.h precedence over target family */
+ uint32_t soft_reset_type; /*!< Boards can override software reset type to VECTRESET or SYSRESETREQ */
+} board_info_t;
+```
+Now running `progen generate -t uvision` will create project files including the new board that can be developed and debugged. Complete development guide is in [Developers Guide](DEVELOPERS-GUIDE.md). For more information about the yaml format [see the project_generator documentation.](https://github.com/project-generator/project_generator/wiki/Getting_started)
+
+### Adding Board to Automated Tests
+Update `test/info.py` so the new board has at least one configuration in SUPPORTED_CONFIGURATIONS
+```python
+SUPPORTED_CONFIGURATIONS = [
+ # Board ID Family ID Firmware Bootloader Target
+ ...
+ ( 0x0240, VENDOR_TO_FAMILY('NXP', 1), 'k20dx_frdmk64f_if', 'k20dx_bl', 'FRDM-K64F' ),
+ ...
+]
+```
+Configration Fields
+* Board ID - The ID assigned to the board type.
+* Family ID - Use to select or identify target family from defined target family or custom ones. Note that common or stub families are supported which supports hw_reset, sw_vectreset or sw_sysreset. More details in [Porting target family guide](PORT_TARGET_FAMILY.md).
+* Firmware - The name of the firmware as shown in projects.yaml.
+* Bootloader - The name of the bootloader firmware as shown in projects.yaml. Only required on HICs with a DAPLink bootloader.
+* Target - Name of the target for this board.
+ * If this is an mbed official board then the target should match the name in the mbed platform page URL. For example the K64F is located at https://developer.mbed.org/platforms/FRDM-K64F/ so it would have the target name `FRDM-K64F`. Using this naming convention allows the automated tests to use the RESTful Compile API. the automated tests will build the target UART application on-the-fly in the cloud using the RESTful Compile API, download it to the PC, then download the resulting image to the target.
+ * If it is not, you will need to build the UART application yourself and supply it to `test/run_tests.py` via --targetdir. In this case, the target is the application image filename sans extension.
+
+You may need to update one or more other dictionaries. See comments in the code for guidance.
+
+See [Automated Tests](AUTOMATED_TESTS.md) for more information related to automated testing.
+
+# Post-build Board ID and Family ID
+Board ID and Family ID can be overwritten by `tools/post_build_scpript.py`. This is helpful for supporting existing families and adding board IDs to the database without the need to compile DAPLink. Board ID can uniquely identify the target board while family ID can select which target family to support.
+```
+usage: post_build_script.py [-h] [--board-id BOARD_ID] [--family-id FAMILY_ID]
+ [--bin-offset BIN_OFFSET]
+ input output
+
+post Build tool for Board ID, Family ID and CRC generation
+
+positional arguments:
+ input Hex or bin file to read from.
+ output Output base file name to write crc, board_id and
+ family_id.
+
+optional arguments:
+ -h, --help show this help message and exit
+ --board-id BOARD_ID board id to for the target in hex
+ --family-id FAMILY_ID
+ family id to for the target in hex
+ --bin-offset BIN_OFFSET
+ binary offset in hex
+```
+Note however that run time board id and family id can be present in the code and DAPLink will use this if it has non-zero value. From `source/hic_hal_target_config.h`
+```
+/**
+ @struct target_cfg_t
+ @brief The firmware configuration struct has unique about the chip its running on.
+ */
+ ...
+typedef struct target_cfg {
+ ...
+ const char *rt_board_id; /*!< If assigned, this is a flexible board ID */
+ uint16_t rt_family_id; /*!< If assigned, this is a flexible board ID */
+} target_cfg_t;
+...
+```
diff -r 000000000000 -r 01f31e923fe2 docs/PORT_HIC.md --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/docs/PORT_HIC.md Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,2 @@ +# Adding A New HIC +Coming soon.
diff -r 000000000000 -r 01f31e923fe2 docs/PORT_TARGET_FAMILY.md
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/docs/PORT_TARGET_FAMILY.md Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,330 @@
+# Adding A New Target Family
+Adding new target family support requires creating a flash algo blob and the implementation for target family api. Target support is added to the `source/family/<mfg>/<target>` directory. At minimum, 3 files are needed. The first is `source/target/<mfg>/target_reset.c`
+
+```c
+/**
+ * @file target_reset.c
+ * @brief Target reset for the new target
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_reset.h"
+#include "swd_host.h"
+#include "target_family.h"
+
+static void target_before_init_debug(void)
+{
+ // any target specific sequences needed before attaching
+ // to the DAP across JTAG or SWD
+ return;
+}
+
+static uint8_t target_unlock_sequence(void)
+{
+ // if the device can secure the flash and there is a way to
+ // erase all it should be implemented here.
+ return 1;
+}
+
+static uint8_t target_set_state(TARGET_RESET_STATE state)
+{
+ // if a custom state machine is needed to set the TARGET_RESET_STATE state
+ return 1;
+}
+
+static uint8_t security_bits_set(uint32_t addr, uint8_t *data, uint32_t size)
+{
+ // if there are security bits in the programmable flash region
+ // a check should be performed. This method is used when programming
+ // by drag-n-drop and should refuse to program an image requesting
+ // to set the device security. This can be performed with the debug channel
+ // if needed.
+ return 0;
+}
+
+const target_family_descriptor_t g_target_family = {
+ .family_id = myFamilyID,
+ .default_reset_type = kHardwareReset,
+ .target_before_init_debug = target_before_init_debug,
+ .target_unlock_sequence = target_unlock_sequence,
+ .target_set_state = target_set_state,
+ .security_bits_set = security_bits_set,
+};
+```
+
+The target family api is located in `source/target/target_family.h` and target_reset file can customize the function apis according to the family specification. Family id is a combination of vendor id and an incrementing id. There are predefined family id stubs that can be used for generic reset types; kStub_HWReset_FamilyID, kStub_SWVectReset_FamilyID and kStub_SWSysReset_FamilyID.
+
+```c
+/**
+ * @file target_family.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2018-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef TARGET_FAMILY_H
+#define TARGET_FAMILY_H
+
+#include <stdint.h>
+#include <string.h>
+#include "target_reset.h"
+
+#define VENDOR_TO_FAMILY(x, y) (x<<8 | y)
+
+typedef enum _reset_type {
+ kHardwareReset=1,
+ kSoftwareReset,
+} reset_type_t;
+
+enum _vendor_ids {
+ kStub_VendorID = 0,
+ kNXP_VendorID = 11,
+ kTI_VendorID = 16,
+ kNordic_VendorID = 54,
+ kToshiba_VendorID = 92,
+ kRenesas_VendorID = 117,
+ kWiznet_VendorID = 122,
+ kRealtek_VendorID = 124,
+};
+
+typedef enum _family_id {
+ kStub_HWReset_FamilyID = VENDOR_TO_FAMILY(kStub_VendorID, 1),
+ kStub_SWVectReset_FamilyID = VENDOR_TO_FAMILY(kStub_VendorID, 2),
+ kStub_SWSysReset_FamilyID = VENDOR_TO_FAMILY(kStub_VendorID, 3),
+ kNXP_KinetisK_FamilyID = VENDOR_TO_FAMILY(kNXP_VendorID, 1),
+ kNXP_KinetisL_FamilyID = VENDOR_TO_FAMILY(kNXP_VendorID, 2),
+ kNXP_Mimxrt_FamilyID = VENDOR_TO_FAMILY(kNXP_VendorID, 3),
+ kNXP_RapidIot_FamilyID = VENDOR_TO_FAMILY(kNXP_VendorID, 4),
+ kNXP_KinetisK32W_FamilyID = VENDOR_TO_FAMILY(kNXP_VendorID, 5),
+ kNordic_Nrf51_FamilyID = VENDOR_TO_FAMILY(kNordic_VendorID, 1),
+ kNordic_Nrf52_FamilyID = VENDOR_TO_FAMILY(kNordic_VendorID, 2),
+ kRealtek_Rtl8195am_FamilyID = VENDOR_TO_FAMILY(kRealtek_VendorID, 1),
+ kTI_Cc3220sf_FamilyID = VENDOR_TO_FAMILY(kTI_VendorID, 1),
+ kToshiba_Tz_FamilyID = VENDOR_TO_FAMILY(kToshiba_VendorID, 1),
+ kWiznet_W7500_FamilyID = VENDOR_TO_FAMILY(kWiznet_VendorID, 1),
+ kRenesas_FamilyID = VENDOR_TO_FAMILY(kRenesas_VendorID, 1),
+} family_id_t;
+
+typedef struct target_family_descriptor {
+ uint16_t family_id; /*!< Use to select or identify target family from defined target family or custom ones */
+ reset_type_t default_reset_type; /*!< Target family can select predefined reset from kHardwareReset and kSoftwareReset */
+ uint32_t soft_reset_type; /*!< Families can override software reset type to VECTRESET or SYSRESETREQ */
+ void (*target_before_init_debug)(void); /*!< Target dependant function before debug initialization */
+ void (*prerun_target_config)(void); /*!< Target specific initialization */
+ uint8_t (*target_unlock_sequence)(void); /*!< Unlock targets that can enter lock state */
+ uint8_t (*security_bits_set)(uint32_t addr, uint8_t *data, uint32_t size); /*!< Check security bits in the programmable flash region */
+ uint8_t (*target_set_state)(TARGET_RESET_STATE state); /*!< Families can customize target debug states in target_reset.h */
+ void (*swd_set_target_reset)(uint8_t asserted); /*!< Families can customize how to send reset to the target */
+ uint8_t (*validate_bin_nvic)(const uint8_t *buf); /*!< Validate a bin file to be flash by drag and drop */
+ uint8_t (*validate_hexfile)(const uint8_t *buf); /*!< Validate a hex file to be flash by drag and drop */
+} target_family_descriptor_t;
+
+extern const target_family_descriptor_t *g_target_family;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void init_family(void);
+uint8_t target_family_valid(void);
+uint8_t target_set_state(TARGET_RESET_STATE state);
+void swd_set_target_reset(uint8_t asserted);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+```
+
+A flash algorithm blob is needed to program the target MCUs internal (or external) flash memory. This blob contains position independent functions for erasing, reading and writing to the flash controller. Flash algorithm blobs are created from the [FlashAlgo project.](https://github.com/mbedmicro/FlashAlgo) An example blob is shown below and would be added to `source/family/<mfg>/<targetname>/flash_blob.c`
+
+```c
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the new target MCU
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t targetname_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x4770ba40, 0x4770bac0, 0x4c0cb510, 0xf04068a0, 0x60a00001, 0x301af246, 0xf44f6560, 0x60e07040,
+ 0x20012100, 0xf83ef000, 0x65612100, 0xf02168a1, 0x60a10101, 0xbf182800, 0xbd102001, 0x400c0000,
+ 0x4684b510, 0xf44f2300, 0xf8505180, 0x1f092b04, 0x1c52d002, 0xe001d0f9, 0xd0131c50, 0x68a04c0c,
+ 0x0001f040, 0xf8c460a0, 0x2001c010, 0x200260e0, 0x210060e0, 0xf0002001, 0x4603f815, 0xf02068a0,
+ 0x60a00001, 0xbf142b00, 0x20002001, 0x0000bd10, 0x400c0000, 0xf6414902, 0x63c83071, 0x47702000,
+ 0x400c0000, 0x4b14b410, 0xc050f8df, 0x201cf8dc, 0x0f16f012, 0xf8dcd014, 0xf0200008, 0xf8cc0005,
+ 0xf0120008, 0xbf1e0f02, 0x0001f06f, 0x4770bc10, 0x0f04f012, 0xf04fbf1e, 0xbc1030ff, 0xe0074770,
+ 0x428a4002, 0xbc10d102, 0x47702000, 0xd1dd1e5b, 0xf06fbc10, 0x47700002, 0x00989680, 0x400c0000,
+ 0x4df0e92d, 0x1cc84604, 0x0603f020, 0x46904859, 0xf0416881, 0x60810101, 0xd9732e07, 0x0f07f014,
+ 0xf8d8d011, 0x61041000, 0x60c22201, 0x21086181, 0x210060c1, 0xf7ff4610, 0x2800ffb5, 0x1d24d17e,
+ 0x0810f108, 0x484b1f36, 0xf0416881, 0x60810104, 0xbf882e07, 0x0a02f06f, 0xf504d966, 0x46015080,
+ 0x010bf36f, 0x42b11b09, 0x4635bf8e, 0x000bf36f, 0xf0151b05, 0xbf180f04, 0x46471f2d, 0x20012100,
+ 0xff90f7ff, 0xd13b2800, 0xe0e8f8df, 0x4010f8ce, 0xf8ce2001, 0xf857000c, 0xf8ce0b04, 0xf8570018,
+ 0xf8ce0b04, 0x20080018, 0x000cf8ce, 0x0208f1a5, 0xd9332a07, 0x0b08f04f, 0x46dc482f, 0x101cf8de,
+ 0x0f16f011, 0xf8ded012, 0xf0200008, 0xf8ce0005, 0xf0110008, 0xbf180f02, 0x0001f06f, 0xf011d10f,
+ 0xbf180f04, 0x30fff04f, 0xe007d109, 0x010bea01, 0xd1014561, 0xe0022000, 0xd1df1e40, 0xb1104650,
+ 0xe00bb9e0, 0xf857e01c, 0xf8ce0b04, 0xf8570018, 0xf8ce0b04, 0x3a080018, 0xd8cb2a07, 0xeb081b76,
+ 0x442c0885, 0xd8982e07, 0x20012100, 0xff3af7ff, 0x4810b920, 0xf0216881, 0xe0000104, 0x6081e00f,
+ 0x480cb186, 0x1000f8d8, 0x22016104, 0x618160c2, 0x60c12108, 0x46102100, 0xff24f7ff, 0x2001b110,
+ 0x8df0e8bd, 0x68814803, 0x0101f021, 0x20006081, 0x8df0e8bd, 0x400c0000, 0x00989680, 0x68814803,
+ 0x0105f021, 0x20006081, 0x00004770, 0x400c0000, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x00000000, 0x00001000},
+ };
+
+static const program_target_t flash = {
+ 0x200000B5, // Init
+ 0x2000029D, // UnInit
+ 0x20000029, // EraseChip
+ 0x20000061, // EraseSector
+ 0x20000121, // ProgramPage
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000000 + 0x00000001,
+ 0x20000000 + 0x00000020 + 0x00000290,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(targetname_blob), // prog_blob size
+ targetname_blob, // address of prog_blob
+ 0x00000200 // program_buffer_size, largest size that can be written in a single call to program page
+};
+
+```
+
+The last required file is the target MCU description file `source/family/<mfg>/<targetname>/target.c` This file contains information about the size of ROM, RAM and sector operations needed to be performed on the target MCU while programming an image across the drag-n-drop channel.
+
+```c
+/**
+ * @file target.c
+ * @brief Target information for the target MCU
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x00000000,
+ .flash_regions[0].end = 0x00200000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x1fff0000,
+ .ram_regions[0].end = 0x20030000,
+};
+```
+Complete target configuration api is located in `source/target/target_config.h`
+```c
+enum _region_flags {
+ kRegionIsDefault = (1 << 0), //out of bounds regions will use the same flash algo if this is set
+ kRegionIsSecure = (1 << 1)
+};
+
+
+typedef struct region_info {
+ uint32_t start;
+ uint32_t end;
+ uint32_t flags;
+ uint8_t alias_index; /*!<use with flags; will point to a different index if there is an alias region */
+ program_target_t *flash_algo; /*!< A pointer to the flash algorithm structure */
+} region_info_t;
+
+/**
+ @struct target_cfg_t
+ @brief The firmware configuration struct has unique about the chip its running on.
+ */
+typedef struct target_cfg {
+ uint32_t version; /*!< Target configuration version */
+ const sector_info_t* sectors_info; /*!< Sector start and length list */
+ int sector_info_length; /*!< Sector start and length list total */
+ region_info_t flash_regions[MAX_EXTRA_FLASH_REGION]; /*!< Flash regions */
+ region_info_t ram_regions[MAX_EXTRA_RAM_REGION]; /*!< RAM regions */
+ uint8_t erase_reset; /*!< Reset after performing an erase */
+ const char *rt_board_id; /*!< If assigned, this is a flexible board ID */
+ uint16_t rt_family_id; /*!< If assigned, this is a flexible board ID */
+} target_cfg_t;
+```
+At this point these target specific files could be added to a board build and developed.
+
+# Supported Target Families
+A HIC can target all supported families available and a post build script can modify a board's family id to point to the correct family. See [Porting board guide](PORT_BOARD.md)
diff -r 000000000000 -r 01f31e923fe2 docs/README.md --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/docs/README.md Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,27 @@ +# DAPLink Documentation + + +## Table of Contents + +### User documentation + +* [Usersâ guide](USERS-GUIDE.md) + +### Developer documentation + +* [Developersâ guide](DEVELOPERS-GUIDE.md) + * [Build output details](BUILD_OUTPUT.md) + +Automated tests and automation: + +* [Automated tests](AUTOMATED_TESTS.md) +* [How to enable automation](ENABLE_AUTOMATION.md) +* [MSD commands](MSD_COMMANDS.md) + +Porting DAPLink to new systems: + +* [Adding a new board](PORT_BOARD.md) +* [Adding a new target device](PORT_TARGET_FAMILY.md) +* [Adding a new HIC](PORT_HIC.md) + +
diff -r 000000000000 -r 01f31e923fe2 docs/USERS-GUIDE.md --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/docs/USERS-GUIDE.md Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,45 @@ +# DAPLink users guide + +DAPLink provides three interfaces. These are drag-and-drop programming, a serial port and debugging support. In addition, you can update DAPLink firmware using the drag-and-drop programming interface of the bootloader. + +## Drag-and-drop programming + +Program the target microcontroller by copying or saving a file in one of the supported formats to the DAPLink drive. Upon completion, the drive remounts. If a failure occurs, the file `FAIL.TXT` appears on the drive containing information about the failure. + +Supported file formats: + +- Raw binary file. +- Intel Hex. + +## Serial port + +The serial port is connected directly to the target MCU allowing for bidirectional communication. It also allows the target to be reset by sending a break command over the serial port. + +Supported baud rates: + +- 9600 +- 14400 +- 19200 +- 28800 +- 38400 +- 56000 +- 57600 +- 115200 + +Note: Most DAPLink implementations support other baud rates in addition to the ones listed here. + +## Debugging + +You can debug with any IDE that supports the CMSIS-DAP protocol. Some tools capable of debugging are: + +- [pyOCD](https://github.com/mbedmicro/pyOCD). +- [uVision](http://www.keil.com/). +- [IAR](https://www.iar.com/). + +## Firmware update + +To update the firmware on a device, hold the reset button while attaching USB. The device boots into bootloader mode. From there, copy the appropriate firmware onto the drive. If successful, the device leaves bootloader mode and starts running the new firmware. Otherwise, the bootloader displays `FAIL.TXT` with an explanation of what went wrong. + +## No MSD builds + +MSD or drag-and-drop support is automatically detected and enabled when the target flash algorithm is in the DAPLink build. But there are builds that does not have a particular target and can retarget any families which have DAPLink support by using a debugger or pyocd without the MSD DAPLink drive. The script `tools/post_build_script.py` can take a board id, family id, flm elf or axf file as flash algo bin and bind it to a DAPLink binary build. The ram boundaries also needed to be specified as parameters. This is useful in all-family builds which has no board target originally but can target all existing families and retarget a particular target. The DAPLink MSD drive will be automatically enabled when there is a flash algoritm embedded in the binary file. The reverse use case of disabling the MSD even with a target support can also be done, please see `docs/MSD_COMMANDS.md` for details.
diff -r 000000000000 -r 01f31e923fe2 docs/images/daplink-website-logo-link.png Binary file docs/images/daplink-website-logo-link.png has changed
diff -r 000000000000 -r 01f31e923fe2 mbed-os.lib --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-os.lib Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,1 @@ +https://github.com/ARMmbed/mbed-os/#bf6f2c3c6434a6de9eb9511feffa5948b3d1f20f
diff -r 000000000000 -r 01f31e923fe2 projects.yaml
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/projects.yaml Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,644 @@
+settings:
+ export_dir:
+ - projectfiles/{tool}/{project_name}
+ tools:
+ uvision:
+ template:
+ - records/tools/uvision.uvproj.tmpl
+
+module:
+ tools: &module_tools
+ - records/tools/make_gcc_arm.yaml
+ - records/tools/make_armcc.yaml
+ - records/tools/version.yaml
+ bl: &module_bl
+ - *module_tools
+ - records/usb/usb-core.yaml
+ - records/usb/usb-msc.yaml
+ - records/daplink/bootloader.yaml
+ - records/daplink/drag-n-drop.yaml
+ - records/daplink/settings.yaml
+ - records/daplink/settings_rom_stub.yaml
+ - records/daplink/target_board.yaml
+ - records/rtos/rtos-none.yaml
+ if: &module_if
+ - *module_tools
+ - records/usb/usb-core.yaml
+ - records/usb/usb-hid.yaml
+ - records/usb/usb-msc.yaml
+ - records/usb/usb-cdc.yaml
+ - records/usb/usb-webusb.yaml
+ - records/usb/usb-winusb.yaml
+ - records/daplink/cmsis-dap.yaml
+ - records/daplink/drag-n-drop.yaml
+ - records/daplink/usb2uart.yaml
+ - records/daplink/settings.yaml
+ - records/daplink/settings_rom.yaml
+ - records/daplink/interface.yaml
+ - records/daplink/target_family.yaml
+ - records/daplink/target_board.yaml
+ # HICs
+ hic_k20dx: &module_hic_k20dx
+ - records/rtos/rtos-cm3.yaml
+ - records/hic_hal/k20dx.yaml
+ - records/usb/usb-bulk.yaml
+ hic_k26f: &module_hic_k26f
+ - records/rtos/rtos-cm4.yaml
+ - records/hic_hal/k26f.yaml
+ - records/usb/usb-bulk.yaml
+ hic_kl26z: &module_hic_kl26z
+ - records/rtos/rtos-cm0.yaml
+ - records/hic_hal/kl26z.yaml
+ - records/usb/usb-bulk.yaml
+ hic_lpc11u35: &module_hic_lpc11u35
+ - records/rtos/rtos-cm0.yaml
+ - records/hic_hal/lpc11u35.yaml
+ hic_lpc4322: &module_hic_lpc4322
+ - records/rtos/rtos-cm3.yaml
+ - records/hic_hal/lpc4322.yaml
+ - records/usb/usb-bulk.yaml
+ hic_sam3u2c: &module_hic_sam3u2c
+ - records/rtos/rtos-cm3.yaml
+ - records/hic_hal/sam3u2c.yaml
+ hic_stm32f103xb: &module_hic_stm32f103xb
+ - records/rtos/rtos-cm3.yaml
+ - records/hic_hal/stm32f103xb.yaml
+ hic_max32620: &module_hic_max32620
+ - records/rtos/rtos-cm4.yaml
+ - records/hic_hal/max32620.yaml
+ hic_max32625: &module_hic_max32625
+ - records/rtos/rtos-cm4.yaml
+ - records/hic_hal/max32625.yaml
+ hic_m48ssidae: &module_hic_m48ssidae
+ - records/rtos/rtos-cm4.yaml
+ - records/hic_hal/m48ssidae.yaml
+
+projects:
+ kl26z_bl:
+ - *module_bl
+ - records/hic_hal/kl26z.yaml
+ - records/board/kl26z_bl.yaml
+ kl26z_if:
+ - *module_if
+ - *module_hic_kl26z
+ - records/family/all_family.yaml
+ k20dx_bl:
+ - *module_bl
+ - records/hic_hal/k20dx.yaml
+ - records/board/k20dx_bl.yaml
+ k20dx_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/family/all_family.yaml
+ k26f_bl:
+ - *module_bl
+ - records/hic_hal/k26f.yaml
+ - records/board/k26f_bl.yaml
+ k26f_if:
+ - *module_if
+ - *module_hic_k26f
+ - records/family/all_family.yaml
+ lpc11u35_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/family/all_family.yaml
+ - records/usb/usb-bulk.yaml
+ lpc4322_bl:
+ - *module_bl
+ - records/hic_hal/lpc4322.yaml
+ - records/board/lpc4322_bl.yaml
+ lpc4322_if:
+ - *module_if
+ - *module_hic_lpc4322
+ - records/family/all_family.yaml
+ max32620_bl:
+ - *module_bl
+ - records/hic_hal/max32620.yaml
+ - records/board/max32620_bl.yaml
+ max32620_if:
+ - *module_if
+ - *module_hic_max32620
+ - records/family/all_family.yaml
+ - records/usb/usb-bulk.yaml
+ max32625_bl:
+ - *module_bl
+ - records/hic_hal/max32625.yaml
+ - records/board/max32625_bl.yaml
+ max32625_if:
+ - *module_if
+ - *module_hic_max32625
+ - records/family/all_family.yaml
+ - records/usb/usb-bulk.yaml
+ sam3u2c_bl:
+ - *module_bl
+ - records/hic_hal/sam3u2c.yaml
+ - records/board/sam3u2c_bl.yaml
+ sam3u2c_if:
+ - *module_if
+ - *module_hic_sam3u2c
+ - records/family/all_family.yaml
+ stm32f103xb_bl:
+ - *module_bl
+ - records/hic_hal/stm32f103xb.yaml
+ - records/board/stm32f103xb_bl.yaml
+ stm32f103xb_if:
+ - *module_if
+ - *module_hic_stm32f103xb
+ - records/family/all_family.yaml
+ - records/usb/usb-bulk.yaml
+ sam3u2c_mkit_dk_dongle_nrf5x_if:
+ - *module_if
+ - *module_hic_sam3u2c
+ - records/board/mkit_dk_dongle_nrf5x.yaml
+ kl26z_microbit_if:
+ - *module_if
+ - *module_hic_kl26z
+ - records/board/microbit.yaml
+ kl26z_nina_b1_if:
+ - *module_if
+ - *module_hic_kl26z
+ - records/board/nina_b1.yaml
+ k20dx_frdmk20dx_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/frdmk20dx.yaml
+ k20dx_frdmk22f_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/frdmk22f.yaml
+ k20dx_frdmkw24d_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/frdmkw24d.yaml
+ k20dx_frdmkw41z_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/frdmkw41z.yaml
+ k20dx_frdmk64f_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/frdmk64f.yaml
+ k20dx_hexiwear_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/hexiwear.yaml
+ k20dx_rapid_iot_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/rapid_iot.yaml
+ k20dx_frdmk66f_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/frdmk66f.yaml
+ k20dx_frdmk82f_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/frdmk82f.yaml
+ k20dx_frdmk28f_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/frdmk28f.yaml
+ k20dx_frdmke15z_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/frdmke15z.yaml
+ k20dx_frdmkl02z_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/frdmkl02z.yaml
+ k20dx_frdmkl05z_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/frdmkl05z.yaml
+ k20dx_frdmkl25z_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/frdmkl25z.yaml
+ k20dx_frdmkl26z_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/frdmkl26z.yaml
+ k20dx_frdmkl27z_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/frdmkl27z.yaml
+ k20dx_frdmkl43z_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/frdmkl43z.yaml
+ k20dx_frdmkl46z_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/frdmkl46z.yaml
+ k20dx_frdmkl28z_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/frdmkl28z.yaml
+ k20dx_frdmkl82z_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/frdmkl82z.yaml
+ k20dx_twrkl28z72m_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/twrkl28z72m.yaml
+ k20dx_twrke18f_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/twrke18f.yaml
+ k20dx_hvpke18f_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/hvpke18f.yaml
+ k20dx_rbl_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/rbl.yaml
+ k20dx_rblnano_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/rblnano.yaml
+ k20dx_xdot_l151_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/xDot-L151.yaml
+ k20dx_mimxrt1020_evk_qspi_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/mimxrt1020_evk_qspi.yaml
+ k20dx_mimxrt1050_evk_hyper_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/mimxrt1050_evk_hyper.yaml
+ k20dx_mimxrt1050_evk_qspi_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/mimxrt1050_evk_qspi.yaml
+ k20dx_ep_agora_if:
+ - *module_if
+ - *module_hic_k20dx
+ - records/board/ep_agora.yaml
+ k26f_frdmk32w042_if:
+ - *module_if
+ - *module_hic_k26f
+ - records/board/frdmk32w042.yaml
+ lpc11u35_ff1705_l151_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/FF1705_L151.yaml
+ lpc11u35_lpc812xpresso_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/lpc812xpresso.yaml
+ lpc11u35_lpc824xpresso_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/lpc824xpresso.yaml
+ lpc4322_lpc54114xpresso_if:
+ - *module_if
+ - *module_hic_lpc4322
+ - records/board/lpc54114xpresso.yaml
+ lpc4322_lpc54608xpresso_if:
+ - *module_if
+ - *module_hic_lpc4322
+ - records/board/lpc54608xpresso.yaml
+ lpc4322_lpc55s69xpresso_if:
+ - *module_if
+ - *module_hic_lpc4322
+ - records/board/lpc55S69xpresso.yaml
+ lpc11u35_ff_lpc546xx_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/ff_lpc546xx.yaml
+ lpc11u35_lpc4088dm_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/lpc4088dm.yaml
+ lpc11u35_lpc4088qsb_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/lpc4088qsb.yaml
+ lpc11u35_archble_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/archble.yaml
+ lpc11u35_tiny_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/tiny.yaml
+ lpc11u35_archpro_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/archpro.yaml
+ lpc11u35_archmax_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/archmax.yaml
+ lpc11u35_wio3g_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/wio3g.yaml
+ lpc11u35_wiobg96_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/wiobg96.yaml
+ lpc11u35_hrm1017_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/hrm1017.yaml
+ lpc11u35_sscity_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/sscity.yaml
+ lpc11u35_ssci824_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/ssci824.yaml
+ lpc11u35_ssci1114_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/ssci1114.yaml
+ lpc11u35_ssci_chibi_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/ssci_chibi.yaml
+ lpc11u35_ro359b_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/ro359b.yaml
+ lpc11u35_c027_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/c027.yaml
+ lpc11u35_arm_watch_stm32f411_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/arm_watch_stm32f411.yaml
+ lpc11u35_arm_watch_efm32_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/arm_watch_efm32.yaml
+ lpc11u35_arm_watch_nrf51_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/arm_watch_nrf51.yaml
+ lpc11u35_archlink_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/archlink.yaml
+ lpc11u35_6lowpan_borderrouterusb_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/6LoWPAN_BorderRouterUSB.yaml
+ lpc11u35_6lowpan_borderrouterhat_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/6LoWPAN_BorderRouterHAT.yaml
+ lpc11u35_6lowpan_borderrouterethernet_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/6LoWPAN_BorderRouterETHERNET.yaml
+ lpc11u35_cocorico_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/cocorico.yaml
+ lpc11u35_gr_peach_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/gr-peach.yaml
+ lpc11u35_blueninja_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/blueninja.yaml
+ lpc11u35_nz32_sc151_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/nz32_sc151.yaml
+ lpc11u35_wizwiki_w7500_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/wizwiki_w7500.yaml
+ lpc11u35_wizwiki_w7500_eco_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/wizwiki_w7500_eco.yaml
+ lpc11u35_wizwiki_w7500p_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/wizwiki_w7500p.yaml
+ lpc11u35_mbed_cloud_connect_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/mbed_cloud_connect.yaml
+ lpc11u35_rtl8195am_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/rtl8195am.yaml
+ sam3u2c_ncs36510rf_if:
+ - *module_if
+ - *module_hic_sam3u2c
+ - records/board/ncs36510rf.yaml
+ sam3u2c_ublox_evk_nina_b1_if:
+ - *module_if
+ - *module_hic_sam3u2c
+ - records/board/ublox_evk_nina_b1.yaml
+ lpc11u35_vbluno51_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/vbluno51.yaml
+ lpc11u35_mtconnect04s_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/mtconnect04s.yaml
+ lpc11u35_96b_nitrogen_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/96b_nitrogen.yaml
+ lpc11u35_mtb_mxchip_emw3166_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/mtb_mxchip_emw3166.yaml
+ lpc11u35_mtb_nina_b112_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/mtb_nina_b112.yaml
+ lpc11u35_mtb_murata_abz_078_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/mtb_murata_abz_078.yaml
+ lpc11u35_mtb_rak811_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/mtb_rak811.yaml
+ lpc11u35_mtb_wise1510_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/mtb_wise1510.yaml
+ lpc11u35_mtb_wise1530_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/mtb_wise1530.yaml
+ lpc11u35_mtb_wise1570_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/mtb_wise1570.yaml
+ lpc11u35_mtb_laird_bl652_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/mtb_laird_bl652.yaml
+ lpc11u35_mtb_usi_wm_bn_bm_22_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/mtb_usi_wm_bn_bm_22.yaml
+ lpc11u35_gr_lychee_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/gr-lychee.yaml
+ lpc11u35_dipdap_sdt32429b_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/dipdap_sdt32429b.yaml
+ lpc11u35_dipdap_sdt32439b_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/dipdap_sdt32439b.yaml
+ lpc11u35_dipdap_sdt64b_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/dipdap_sdt64b.yaml
+ lpc11u35_dipdap_sdt51822b_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/dipdap_sdt51822b.yaml
+ lpc11u35_dipdap_sdt52832b_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/dipdap_sdt52832b.yaml
+ lpc11u35_mtb_ublox_odin_w2_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/mtb_ublox_odin_w2.yaml
+ lpc11u35_mtb_mts_dragonfly_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/mtb_mts_dragonfly.yaml
+ lpc11u35_mtb_mts_xdot_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/mtb_mts_xdot.yaml
+ lpc11u35_dipdap_cc3220sf_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/dipdap_cc3220sf.yaml
+ stm32f103xb_stm32f103rb_if:
+ - *module_if
+ - *module_hic_stm32f103xb
+ - records/board/stm32f103rb.yaml
+ stm32f103xb_stm32f072rb_if:
+ - *module_if
+ - *module_hic_stm32f103xb
+ - records/board/stm32f072rb.yaml
+ stm32f103xb_stm32f334r8_if:
+ - *module_if
+ - *module_hic_stm32f103xb
+ - records/board/stm32f334r8.yaml
+ stm32f103xb_stm32f401re_if:
+ - *module_if
+ - *module_hic_stm32f103xb
+ - records/board/stm32f401re.yaml
+ stm32f103xb_stm32f411re_if:
+ - *module_if
+ - *module_hic_stm32f103xb
+ - records/board/stm32f411re.yaml
+ stm32f103xb_stm32f429zi_if:
+ - *module_if
+ - *module_hic_stm32f103xb
+ - records/board/stm32f429zi.yaml
+ stm32f103xb_ublox_evk_odin_w2_if:
+ - *module_if
+ - *module_hic_stm32f103xb
+ - records/board/ublox_evk_odin_w2.yaml
+ stm32f103xb_stm32l476rg_if:
+ - *module_if
+ - *module_hic_stm32f103xb
+ - records/board/stm32l476rg.yaml
+ stm32f103xb_stm32f746zg_if:
+ - *module_if
+ - *module_hic_stm32f103xb
+ - records/board/stm32f746zg.yaml
+ stm32f103xb_stm32f207zg_if:
+ - *module_if
+ - *module_hic_stm32f103xb
+ - records/board/stm32f207zg.yaml
+ lpc11u35_mtb_laird_bl654_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/mtb_laird_bl654.yaml
+ lpc11u35_mtb_murata_bl241_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/mtb_murata_bl241.yaml
+ lpc11u35_mtb_stm_s2lp_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/mtb_stm_s2lp.yaml
+ lpc11u35_mini_iot_lpc54018_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/mini_iot_lpc54018.yaml
+ lpc11u35_mtb_stm32l475_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/mtb_stm32l475.yaml
+ lpc11u35_mtb_aconno_acn52832_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/mtb_aconno_acn52832.yaml
+ lpc11u35_mtb_stm32f439_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/mtb_stm32f439.yaml
+ lpc11u35_musca_a_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/musca_a.yaml
+ lpc11u35_musca_b_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/musca_b.yaml
+ lpc11u35_musca_b_eflash_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/musca_b_eflash.yaml
+ max32620_max32625mbed_if:
+ - *module_if
+ - *module_hic_max32620
+ - records/board/max32625mbed.yaml
+ max32625_max32620fthr_if:
+ - *module_if
+ - *module_hic_max32625
+ - records/board/max32620fthr.yaml
+ max32625_max32630fthr_if:
+ - *module_if
+ - *module_hic_max32625
+ - records/board/max32630fthr.yaml
+ lpc11u35_wio_emw3166_if:
+ - *module_if
+ - *module_hic_lpc11u35
+ - records/board/wio_emw3166.yaml
+ m48ssidae_bl:
+ - *module_bl
+ - records/hic_hal/m48ssidae.yaml
+ - records/board/m48ssidae_bl.yaml
+ m48ssidae_numaker_m252kg_if:
+ - *module_if
+ - *module_hic_m48ssidae
+ - records/board/numaker_m252kg.yaml
+ m48ssidae_numaker_iot_m263a_if:
+ - *module_if
+ - *module_hic_m48ssidae
+ - records/board/numaker_iot_m263a.yaml
+ lpc4322_hani_iot_if:
+ - *module_if
+ - *module_hic_lpc4322
+ - records/board/hani_iot.yaml
diff -r 000000000000 -r 01f31e923fe2 records/board/6LoWPAN_BorderRouterETHERNET.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/6LoWPAN_BorderRouterETHERNET.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,12 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_lpc11u35_6LoWPAN_BorderRouter + sources: + board: + - source/board/6LoWPAN_BorderRouterETHERNET.c + family: + - source/family/freescale/k64f/target.c + - source/family/freescale/target_reset_Kseries.c +
diff -r 000000000000 -r 01f31e923fe2 records/board/6LoWPAN_BorderRouterHAT.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/6LoWPAN_BorderRouterHAT.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,12 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_lpc11u35_6LoWPAN_BorderRouter + sources: + board: + - source/board/6LoWPAN_BorderRouterHAT.c + family: + - source/family/freescale/k64f/target.c + - source/family/freescale/target_reset_Kseries.c +
diff -r 000000000000 -r 01f31e923fe2 records/board/6LoWPAN_BorderRouterUSB.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/6LoWPAN_BorderRouterUSB.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,12 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_lpc11u35_6LoWPAN_BorderRouter + sources: + board: + - source/board/6LoWPAN_BorderRouterUSB.c + family: + - source/family/freescale/k64f/target.c + - source/family/freescale/target_reset_Kseries.c +
diff -r 000000000000 -r 01f31e923fe2 records/board/96b_nitrogen.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/96b_nitrogen.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,11 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_96b_nitrogen + sources: + board: + - source/board/96b_nitrogen.c + family: + - source/family/nordic/nrf5x/target.c + - source/family/nordic/target_reset_nrf52.c
diff -r 000000000000 -r 01f31e923fe2 records/board/FF1705_L151.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/FF1705_L151.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/FF1705_L151.c + family: + - source/family/st/xDot-L151/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/archble.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/archble.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,11 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_lpc11u35_reset + sources: + board: + - source/board/archble.c + family: + - source/family/nordic/nrf51822/target_16.c + - source/family/nordic/target_reset_nrf51.c
diff -r 000000000000 -r 01f31e923fe2 records/board/archlink.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/archlink.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,11 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_lpc11u35_reset + sources: + board: + - source/board/archlink.c + family: + - source/family/nordic/nrf51822/target_16.c + - source/family/nordic/target_reset_nrf51.c
diff -r 000000000000 -r 01f31e923fe2 records/board/archmax.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/archmax.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/archmax.c + family: + - source/family/st/stm32f407ve/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/archpro.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/archpro.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/archpro.c + family: + - source/family/nxp/lpc1768/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/arm_watch_efm32.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/arm_watch_efm32.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/arm_watch_efm32.c + family: + - source/family/siliconlabs/efm32gg/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/arm_watch_nrf51.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/arm_watch_nrf51.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/arm_watch_nrf51.c + family: + - source/family/nordic/nrf51822/target_16.c + - source/family/nordic/target_reset_nrf51.c
diff -r 000000000000 -r 01f31e923fe2 records/board/arm_watch_stm32f411.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/arm_watch_stm32f411.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/arm_watch_stm32f411.c + family: + - source/family/st/stm32f411/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/blueninja.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/blueninja.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,11 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_blueninja + sources: + board: + - source/board/blueninja.c + family: + - source/family/toshiba/tz10xx/target_remap0.c + - source/family/toshiba/target_reset_tz.c
diff -r 000000000000 -r 01f31e923fe2 records/board/c027.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/c027.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/c027.c + family: + - source/family/nxp/lpc1768/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/cocorico.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/cocorico.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/cocorico.c + family: + - source/family/nxp/lpc812/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/dipdap_cc3220sf.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/dipdap_cc3220sf.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,9 @@ +common: + sources: + macros: + - SOFT_RESET=VECTRESET + board: + - source/board/dipdap_cc3220sf.c + family: + - source/family/ti/cc3220sf/target.c + - source/family/ti/target_reset_ti.c
diff -r 000000000000 -r 01f31e923fe2 records/board/dipdap_sdt32429b.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/dipdap_sdt32429b.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/dipdap_sdt32429b.c + family: + - source/family/st/stm32f429zi/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/dipdap_sdt32439b.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/dipdap_sdt32439b.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/dipdap_sdt32439b.c + family: + - source/family/st/stm32f439zi/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/dipdap_sdt51822b.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/dipdap_sdt51822b.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/dipdap_sdt51822b.c + family: + - source/family/nordic/nrf51822/target_16.c + - source/family/nordic/target_reset_nrf51.c
diff -r 000000000000 -r 01f31e923fe2 records/board/dipdap_sdt52832b.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/dipdap_sdt52832b.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/dipdap_sdt52832b.c + family: + - source/family/nordic/nrf5x/target.c + - source/family/nordic/target_reset_nrf52.c
diff -r 000000000000 -r 01f31e923fe2 records/board/dipdap_sdt64b.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/dipdap_sdt64b.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/dipdap_sdt64b.c + family: + - source/family/freescale/k64f/target.c + - source/family/freescale/target_reset_Kseries.c
diff -r 000000000000 -r 01f31e923fe2 records/board/ep_agora.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/ep_agora.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/ep_agora.c + family: + - source/family/nordic/nrf5x/target.c + - source/family/nordic/target_reset_nrf52.c
diff -r 000000000000 -r 01f31e923fe2 records/board/ff_lpc546xx.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/ff_lpc546xx.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/ff_lpc546xx.c + family: + - source/family/nxp/lpc54608/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/frdmk20dx.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/frdmk20dx.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/frdmk20dx.c + family: + - source/family/freescale/k20dx/target.c + - source/family/freescale/target_reset_Kseries.c
diff -r 000000000000 -r 01f31e923fe2 records/board/frdmk22f.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/frdmk22f.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/frdmk22f.c + family: + - source/family/freescale/k22f/target.c + - source/family/freescale/target_reset_Kseries.c
diff -r 000000000000 -r 01f31e923fe2 records/board/frdmk28f.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/frdmk28f.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/frdmk28f.c + family: + - source/family/freescale/k28f/target.c + - source/family/freescale/target_reset_Kseries.c
diff -r 000000000000 -r 01f31e923fe2 records/board/frdmk32w042.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/frdmk32w042.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/frdmk32w042.c + family: + - source/family/freescale/k32w042/target.c + - source/family/freescale/target_reset_k32w_series.c
diff -r 000000000000 -r 01f31e923fe2 records/board/frdmk64f.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/frdmk64f.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/frdmk64f.c + family: + - source/family/freescale/k64f/target.c + - source/family/freescale/target_reset_Kseries.c
diff -r 000000000000 -r 01f31e923fe2 records/board/frdmk66f.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/frdmk66f.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/frdmk66f.c + family: + - source/family/freescale/k66f/target.c + - source/family/freescale/target_reset_Kseries.c
diff -r 000000000000 -r 01f31e923fe2 records/board/frdmk82f.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/frdmk82f.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/frdmk82f.c + family: + - source/family/freescale/k82f/target.c + - source/family/freescale/target_reset_Kseries.c
diff -r 000000000000 -r 01f31e923fe2 records/board/frdmke15z.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/frdmke15z.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/frdmke15z.c + family: + - source/family/freescale/ke15z/target.c + - source/family/freescale/target_reset_Lseries.c
diff -r 000000000000 -r 01f31e923fe2 records/board/frdmkl02z.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/frdmkl02z.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/frdmkl02z.c + family: + - source/family/freescale/kl02z/target.c + - source/family/freescale/target_reset_Lseries.c
diff -r 000000000000 -r 01f31e923fe2 records/board/frdmkl05z.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/frdmkl05z.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/frdmkl05z.c + family: + - source/family/freescale/kl05z/target.c + - source/family/freescale/target_reset_Lseries.c
diff -r 000000000000 -r 01f31e923fe2 records/board/frdmkl25z.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/frdmkl25z.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/frdmkl25z.c + family: + - source/family/freescale/kl25z/target.c + - source/family/freescale/target_reset_Lseries.c
diff -r 000000000000 -r 01f31e923fe2 records/board/frdmkl26z.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/frdmkl26z.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/frdmkl26z.c + family: + - source/family/freescale/kl26z/target.c + - source/family/freescale/target_reset_Lseries.c
diff -r 000000000000 -r 01f31e923fe2 records/board/frdmkl27z.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/frdmkl27z.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/frdmkl27z.c + family: + - source/family/freescale/kl27z/target.c + - source/family/freescale/target_reset_Lseries.c
diff -r 000000000000 -r 01f31e923fe2 records/board/frdmkl28z.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/frdmkl28z.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/frdmkl28z.c + family: + - source/family/freescale/kl28z/target.c + - source/family/freescale/target_reset_Lseries.c
diff -r 000000000000 -r 01f31e923fe2 records/board/frdmkl43z.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/frdmkl43z.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/frdmkl43z.c + family: + - source/family/freescale/kl43z/target.c + - source/family/freescale/target_reset_Lseries.c
diff -r 000000000000 -r 01f31e923fe2 records/board/frdmkl46z.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/frdmkl46z.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/frdmkl46z.c + family: + - source/family/freescale/kl46z/target.c + - source/family/freescale/target_reset_Lseries.c
diff -r 000000000000 -r 01f31e923fe2 records/board/frdmkl82z.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/frdmkl82z.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/frdmkl82z.c + family: + - source/family/freescale/kl82z/target.c + - source/family/freescale/target_reset_Lseries.c
diff -r 000000000000 -r 01f31e923fe2 records/board/frdmkw24d.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/frdmkw24d.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/frdmkw24d.c + family: + - source/family/freescale/kw24d/target.c + - source/family/freescale/target_reset_Kseries.c
diff -r 000000000000 -r 01f31e923fe2 records/board/frdmkw41z.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/frdmkw41z.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/frdmkw41z.c + family: + - source/family/freescale/kw41z/target.c + - source/family/freescale/target_reset_Lseries.c
diff -r 000000000000 -r 01f31e923fe2 records/board/gr-lychee.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/gr-lychee.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,9 @@ +common: + macros: + - TARGET_MCU_CORTEX_A + sources: + board: + - source/board/gr-lychee.c + family: + - source/family/renesas/rza1lu/gr-lychee/target.c + - source/family/renesas/target_reset_rza.c
diff -r 000000000000 -r 01f31e923fe2 records/board/gr-peach.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/gr-peach.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,9 @@ +common: + macros: + - TARGET_MCU_CORTEX_A + sources: + board: + - source/board/gr-peach.c + family: + - source/family/renesas/rza1h/gr-peach/target.c + - source/family/renesas/target_reset_rza.c
diff -r 000000000000 -r 01f31e923fe2 records/board/hani_iot.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/hani_iot.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/hani_iot.c + family: + - source/family/nxp/lpc55S6X/target.c + - source/family/nxp/lpc55S6X/target_reset.c
diff -r 000000000000 -r 01f31e923fe2 records/board/hexiwear.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/hexiwear.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/hexiwear.c + family: + - source/family/freescale/rapid_iot/target.c + - source/family/freescale/target_reset_rapid_iot.c
diff -r 000000000000 -r 01f31e923fe2 records/board/hrm1017.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/hrm1017.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/hrm1017.c + family: + - source/family/nordic/nrf51822/target_16.c + - source/family/nordic/target_reset_nrf51.c
diff -r 000000000000 -r 01f31e923fe2 records/board/hvpke18f.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/hvpke18f.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/hvpke18f.c + family: + - source/family/freescale/ke18f/target.c + - source/family/freescale/target_reset_Kseries.c
diff -r 000000000000 -r 01f31e923fe2 records/board/k20dx_bl.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/k20dx_bl.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,4 @@ +common: + sources: + board: + - source/board/k20dx_bl.c
diff -r 000000000000 -r 01f31e923fe2 records/board/k26f_bl.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/k26f_bl.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,4 @@ +common: + sources: + board: + - source/board/k26f_bl.c
diff -r 000000000000 -r 01f31e923fe2 records/board/kl26z_bl.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/kl26z_bl.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,4 @@ +common: + sources: + board: + - source/board/kl26z_bl.c
diff -r 000000000000 -r 01f31e923fe2 records/board/lpc4088dm.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/lpc4088dm.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/lpc4088dm.c + family: + - source/family/nxp/lpc4088/target_lpc4088dm.c + - source/family/nxp/target_reset_lpc4088.c
diff -r 000000000000 -r 01f31e923fe2 records/board/lpc4088qsb.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/lpc4088qsb.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/lpc4088qsb.c + family: + - source/family/nxp/lpc4088/target_lpc4088qsb.c + - source/family/nxp/target_reset_lpc4088.c
diff -r 000000000000 -r 01f31e923fe2 records/board/lpc4322_bl.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/lpc4322_bl.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,4 @@ +common: + sources: + board: + - source/board/lpc4322_bl.c
diff -r 000000000000 -r 01f31e923fe2 records/board/lpc54114xpresso.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/lpc54114xpresso.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/lpc54114xpresso.c + family: + - source/family/nxp/lpc54114/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/lpc54608xpresso.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/lpc54608xpresso.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/lpc54608xpresso.c + family: + - source/family/nxp/lpc54608/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/lpc55S69xpresso.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/lpc55S69xpresso.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/lpc55S69xpresso.c + family: + - source/family/nxp/lpc55S6X/target.c + - source/family/nxp/lpc55S6X/target_reset.c
diff -r 000000000000 -r 01f31e923fe2 records/board/lpc812xpresso.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/lpc812xpresso.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/lpc812xpresso.c + family: + - source/family/nxp/lpc812/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/lpc824xpresso.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/lpc824xpresso.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/lpc824xpresso.c + family: + - source/family/nxp/lpc824/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/m48ssidae_bl.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/m48ssidae_bl.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,4 @@ +common: + sources: + board: + - source/board/m48ssidae_bl.c
diff -r 000000000000 -r 01f31e923fe2 records/board/max32620_bl.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/max32620_bl.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,4 @@ +common: + sources: + board: + - source/board/max32620_bl.c
diff -r 000000000000 -r 01f31e923fe2 records/board/max32620fthr.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/max32620fthr.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/max32620fthr.c + family: + - source/family/maxim/max32620/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/max32625_bl.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/max32625_bl.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,4 @@ +common: + sources: + board: + - source/board/max32625_bl.c
diff -r 000000000000 -r 01f31e923fe2 records/board/max32625mbed.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/max32625mbed.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/max32625mbed.c + family: + - source/family/maxim/max32625/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/max32630fthr.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/max32630fthr.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/max32630fthr.c + family: + - source/family/maxim/max32630/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/mbed_cloud_connect.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/mbed_cloud_connect.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/mbed_cloud_connect.c + family: + - source/family/st/stm32f439zi/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/microbit.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/microbit.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,12 @@ +common: + macros: + - HID_LED_DEF=GPIO_LED_ON + - CDC_LED_DEF=GPIO_LED_ON + - MSC_LED_DEF=GPIO_LED_ON + - USB_PROD_STR="BBC micro:bit CMSIS-DAP" + sources: + board: + - source/board/microbit.c + family: + - source/family/nordic/nrf51822/target_16.c + - source/family/nordic/target_reset_nrf51.c
diff -r 000000000000 -r 01f31e923fe2 records/board/mimxrt1020_evk_qspi.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/mimxrt1020_evk_qspi.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,9 @@ +common: + macros: + - SOFT_RESET=VECTRESET + sources: + board: + - source/board/mimxrt1020_evk.c + family: + - source/family/freescale/mimxrt1020_spi_flash/target.c + - source/family/freescale/target_reset_mimxrt.c
diff -r 000000000000 -r 01f31e923fe2 records/board/mimxrt1050_evk_hyper.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/mimxrt1050_evk_hyper.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,9 @@ +common: + macros: + - SOFT_RESET=VECTRESET + sources: + board: + - source/board/mimxrt1050_evk.c + family: + - source/family/freescale/mimxrt1050_hyper_flash/target.c + - source/family/freescale/target_reset_mimxrt.c
diff -r 000000000000 -r 01f31e923fe2 records/board/mimxrt1050_evk_qspi.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/mimxrt1050_evk_qspi.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,9 @@ +common: + macros: + - SOFT_RESET=VECTRESET + sources: + board: + - source/board/mimxrt1050_evk.c + family: + - source/family/freescale/mimxrt1050_spi_flash/target.c + - source/family/freescale/target_reset_mimxrt.c
diff -r 000000000000 -r 01f31e923fe2 records/board/mini_iot_lpc54018.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/mini_iot_lpc54018.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,8 @@ +common: + macros: + - SOFT_RESET=VECTRESET + sources: + board: + - source/board/mini_iot_lpc54018.c + family: + - source/family/nxp/lpc54018/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/mkit_dk_dongle_nrf5x.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/mkit_dk_dongle_nrf5x.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,12 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_mkit_dk_dongle_nrf5x + sources: + board: + - source/board/mkit_dk_dongle_nrf5x.c + family: + - source/family/nordic/nrf5x/target.c + - source/family/nordic/target_reset_nrf51.c + - source/family/nordic/target_reset_nrf52.c
diff -r 000000000000 -r 01f31e923fe2 records/board/mtb_aconno_acn52832.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/mtb_aconno_acn52832.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,11 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_mtb + sources: + board: + - source/board/mtb_aconno_acn52832.c + family: + - source/family/nordic/nrf5x/target.c + - source/family/nordic/target_reset_nrf52.c
diff -r 000000000000 -r 01f31e923fe2 records/board/mtb_laird_bl652.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/mtb_laird_bl652.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,11 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_mtb + sources: + board: + - source/board/mtb_laird_bl652.c + family: + - source/family/nordic/nrf5x/target.c + - source/family/nordic/target_reset_nrf52.c
diff -r 000000000000 -r 01f31e923fe2 records/board/mtb_laird_bl654.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/mtb_laird_bl654.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,11 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_mtb + sources: + board: + - source/board/mtb_laird_bl654.c + family: + - source/family/nordic/nrf5x/target.c + - source/family/nordic/target_reset_nrf52.c
diff -r 000000000000 -r 01f31e923fe2 records/board/mtb_mts_dragonfly.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/mtb_mts_dragonfly.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,10 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_mtb + sources: + board: + - source/board/mtb_mts_dragonfly.c + family: + - source/family/st/stm32f411/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/mtb_mts_xdot.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/mtb_mts_xdot.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,10 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_mtb + sources: + board: + - source/board/mtb_mts_xdot.c + family: + - source/family/st/xDot-L151/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/mtb_murata_abz_078.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/mtb_murata_abz_078.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,10 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_mtb + sources: + board: + - source/board/mtb_murata_abz_078.c + family: + - source/family/st/stm32l082cz/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/mtb_murata_bl241.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/mtb_murata_bl241.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,11 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_mtb + sources: + board: + - source/board/mtb_murata_bl241.c + family: + - source/family/nordic/nrf5x/target.c + - source/family/nordic/target_reset_nrf52.c
diff -r 000000000000 -r 01f31e923fe2 records/board/mtb_mxchip_emw3166.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/mtb_mxchip_emw3166.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,10 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_mtb + sources: + board: + - source/board/mtb_mxchip_emw3166.c + family: + - source/family/st/stm32f412rg/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/mtb_nina_b112.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/mtb_nina_b112.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,11 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_mtb + sources: + board: + - source/board/mtb_nina_b112.c + family: + - source/family/nordic/nrf5x/target.c + - source/family/nordic/target_reset_nrf52.c
diff -r 000000000000 -r 01f31e923fe2 records/board/mtb_rak811.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/mtb_rak811.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,11 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_mtb + sources: + board: + - source/board/mtb_rak811.c + family: + - source/family/st/stm32l151cbxxa/target.c +
diff -r 000000000000 -r 01f31e923fe2 records/board/mtb_stm32f439.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/mtb_stm32f439.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,10 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_mtb + sources: + board: + - source/board/mtb_stm32f439.c + family: + - source/family/st/stm32f439zi/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/mtb_stm32l475.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/mtb_stm32l475.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,10 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_mtb + sources: + board: + - source/board/mtb_stm32l475.c + family: + - source/family/st/stm32l4xx_1024/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/mtb_stm_s2lp.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/mtb_stm_s2lp.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,10 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_mtb + sources: + board: + - source/board/mtb_stm_s2lp.c + family: + - source/family/st/stm32f429zi/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/mtb_ublox_odin_w2.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/mtb_ublox_odin_w2.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,10 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_mtb + sources: + board: + - source/board/mtb_ublox_odin_w2.c + family: + - source/family/st/stm32f439zi/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/mtb_usi_wm_bn_bm_22.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/mtb_usi_wm_bn_bm_22.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,10 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_mtb + sources: + board: + - source/board/mtb_usi_wm_bn_bm_22.c + family: + - source/family/st/stm32f412rg/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/mtb_wise1510.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/mtb_wise1510.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,10 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_mtb + sources: + board: + - source/board/mtb_wise1510.c + family: + - source/family/st/stm32l443rc/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/mtb_wise1530.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/mtb_wise1530.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,10 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_mtb + sources: + board: + - source/board/mtb_wise1530.c + family: + - source/family/st/stm32f412rg/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/mtb_wise1570.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/mtb_wise1570.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,10 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_mtb + sources: + board: + - source/board/mtb_wise1570.c + family: + - source/family/st/stm32l486jg/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/mtconnect04s.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/mtconnect04s.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/mtconnect04s.c + family: + - source/family/nordic/nrf51822/target_32.c + - source/family/nordic/target_reset_nrf51.c
diff -r 000000000000 -r 01f31e923fe2 records/board/musca_a.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/musca_a.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,15 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_musca_a + sources: + board: + - source/board/musca_a.c + daplink_if: + - source/family/arm/musca_a/syscon.c + - source/family/arm/musca_a/power_ctrl.c + - source/family/arm/musca_a/utils.c + family: + - source/family/arm/musca_a/target.c + - source/family/arm/musca_a/target_reset.c
diff -r 000000000000 -r 01f31e923fe2 records/board/musca_b.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/musca_b.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,18 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + - MUSCA_B_BOOT_QSPI_FLASH + includes: + - source/board/override_musca_b + - source/family/arm/musca_b + sources: + board: + - source/board/musca_b.c + daplink_if: + - source/family/arm/musca_b/syscon.c + - source/family/arm/musca_b/power_ctrl.c + - source/family/arm/musca_b/utils.c + - source/family/arm/musca_b/i2c_gpio.c + family: + - source/family/arm/musca_b/target.c + - source/family/arm/musca_b/target_reset.c
diff -r 000000000000 -r 01f31e923fe2 records/board/musca_b_eflash.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/musca_b_eflash.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,18 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + - MUSCA_B_BOOT_EFLASH0 + includes: + - source/board/override_musca_b + - source/family/arm/musca_b + sources: + board: + - source/board/musca_b.c + daplink_if: + - source/family/arm/musca_b/syscon.c + - source/family/arm/musca_b/power_ctrl.c + - source/family/arm/musca_b/utils.c + - source/family/arm/musca_b/i2c_gpio.c + family: + - source/family/arm/musca_b/target.c + - source/family/arm/musca_b/target_reset.c
diff -r 000000000000 -r 01f31e923fe2 records/board/ncs36510rf.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/ncs36510rf.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/ncs36510rf.c + family: + - source/family/onsemi/ncs36510/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/nina_b1.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/nina_b1.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,11 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_mkl26z_reset + sources: + board: + - source/board/nina_b1.c + family: + - source/family/nordic/nrf5x/target.c + - source/family/nordic/target_reset_nrf51.c
diff -r 000000000000 -r 01f31e923fe2 records/board/numaker_iot_m263a.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/numaker_iot_m263a.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/numaker_iot_m263a.c + family: + - source/family/nuvoton/m263kiaae/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/numaker_m252kg.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/numaker_m252kg.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/numaker_m252kg.c + family: + - source/family/nuvoton/m252kg6ae/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/nz32_sc151.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/nz32_sc151.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/nz32_sc151.c + family: + - source/family/st/nz32_sc151/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/rapid_iot.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/rapid_iot.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,9 @@ +common: + macros: + - BOARD_RAPID_IOT + sources: + board: + - source/board/rapid_iot.c + family: + - source/family/freescale/rapid_iot/target.c + - source/family/freescale/target_reset_rapid_iot.c
diff -r 000000000000 -r 01f31e923fe2 records/board/rbl.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/rbl.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/rbl.c + family: + - source/family/nordic/nrf51822/target_16.c + - source/family/nordic/target_reset_nrf51.c
diff -r 000000000000 -r 01f31e923fe2 records/board/rblnano.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/rblnano.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/rblnano.c + family: + - source/family/nordic/nrf51822/target_16.c + - source/family/nordic/target_reset_nrf51.c
diff -r 000000000000 -r 01f31e923fe2 records/board/ro359b.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/ro359b.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/ro359b.c + family: + - source/family/freescale/k64f/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/rtl8195am.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/rtl8195am.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,9 @@ +common: + sources: + board: + - source/board/rtl8195am.c + family: + - source/family/realtek/rtl8195am/target.c + - source/family/realtek/target_reset_realtek_rtl8195am.c + macros: + - BOARD_RTL8195AM
diff -r 000000000000 -r 01f31e923fe2 records/board/sam3u2c_bl.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/sam3u2c_bl.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,4 @@ +common: + sources: + board: + - source/board/sam3u2c_bl.c
diff -r 000000000000 -r 01f31e923fe2 records/board/ssci1114.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/ssci1114.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/ssci1114.c + family: + - source/family/nxp/lpc1114/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/ssci824.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/ssci824.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,8 @@ +common: + includes: + - source/target/nxp/lpc824 + sources: + board: + - source/board/scci824.c + family: + - source/family/nxp/lpc824/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/ssci_chibi.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/ssci_chibi.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/ssci_chibi.c + family: + - source/family/nordic/nrf51822/target_16.c + - source/family/nordic/target_reset_nrf51.c
diff -r 000000000000 -r 01f31e923fe2 records/board/sscity.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/sscity.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/sscity.c + family: + - source/family/nordic/nrf51822/target_16.c + - source/family/nordic/target_reset_nrf51.c
diff -r 000000000000 -r 01f31e923fe2 records/board/stm32f072rb.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/stm32f072rb.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/stm32f072rb.c + family: + - source/family/st/stm32f072rb/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/stm32f103rb.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/stm32f103rb.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/stm32f103rb.c + family: + - source/family/st/stm32f103rb/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/stm32f103xb_bl.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/stm32f103xb_bl.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,4 @@ +common: + sources: + board: + - source/board/stm32f103xb_bl.c
diff -r 000000000000 -r 01f31e923fe2 records/board/stm32f207zg.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/stm32f207zg.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/stm32f207zg.c + family: + - source/family/st/stm32f207zg/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/stm32f334r8.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/stm32f334r8.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/stm32f334r8.c + family: + - source/family/st/stm32f334r8/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/stm32f401re.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/stm32f401re.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/stm32f401re.c + family: + - source/family/st/stm32f401re/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/stm32f411re.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/stm32f411re.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/stm32f411re.c + family: + - source/family/st/stm32f411/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/stm32f429zi.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/stm32f429zi.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/stm32f429zi.c + family: + - source/family/st/stm32f429zi/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/stm32f746zg.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/stm32f746zg.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/stm32f746zg.c + family: + - source/family/st/stm32f746zg/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/stm32l476rg.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/stm32l476rg.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/stm32l476rg.c + family: + - source/family/st/stm32l476rg/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/tiny.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/tiny.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,11 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_tiny + sources: + board: + - source/board/tiny.c + family: + - source/family/nordic/nrf51822/target_16.c + - source/family/nordic/target_reset_nrf51.c
diff -r 000000000000 -r 01f31e923fe2 records/board/twrke18f.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/twrke18f.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/twrke18f.c + family: + - source/family/freescale/ke18f/target.c + - source/family/freescale/target_reset_Kseries.c
diff -r 000000000000 -r 01f31e923fe2 records/board/twrkl28z72m.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/twrkl28z72m.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/twrkl28z72m.c + family: + - source/family/freescale/kl28z/target.c + - source/family/freescale/target_reset_Lseries.c
diff -r 000000000000 -r 01f31e923fe2 records/board/ublox_evk_nina_b1.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/ublox_evk_nina_b1.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,11 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_ublox_evk_nina_b1 + sources: + board: + - source/board/ublox_evk_nina_b1.c + family: + - source/family/nordic/nrf5x/target.c + - source/family/nordic/target_reset_nrf52.c
diff -r 000000000000 -r 01f31e923fe2 records/board/ublox_evk_odin_w2.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/ublox_evk_odin_w2.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/ublox_evk_odin_w2.c + family: + - source/family/st/stm32f439zi/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/vbluno51.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/vbluno51.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,11 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_vbluno51 + sources: + board: + - source/board/vbluno51.c + family: + - source/family/nordic/nrf51822/target_32.c + - source/family/nordic/target_reset_nrf51.c
diff -r 000000000000 -r 01f31e923fe2 records/board/wio3g.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/wio3g.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/wio3g.c + family: + - source/family/st/stm32f439zi/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/wio_emw3166.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/wio_emw3166.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/wio_emw3166.c + family: + - source/family/st/stm32f412rg/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/wiobg96.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/wiobg96.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/wiobg96.c + family: + - source/family/st/stm32f439zi/target.c
diff -r 000000000000 -r 01f31e923fe2 records/board/wizwiki_w7500.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/wizwiki_w7500.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/wizwiki_w7500.c + family: + - source/family/wiznet/w7500/target.c + - source/family/wiznet/target_reset_wiznet.c
diff -r 000000000000 -r 01f31e923fe2 records/board/wizwiki_w7500_eco.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/wizwiki_w7500_eco.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/wizwiki_w7500_eco.c + family: + - source/family/wiznet/w7500/target.c + - source/family/wiznet/target_reset_wiznet.c
diff -r 000000000000 -r 01f31e923fe2 records/board/wizwiki_w7500p.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/wizwiki_w7500p.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/wizwiki_w7500p.c + family: + - source/family/wiznet/w7500/target.c + - source/family/wiznet/target_reset_wiznet.c
diff -r 000000000000 -r 01f31e923fe2 records/board/xDot-L151.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/board/xDot-L151.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/xDot-L151.c + family: + - source/family/st/xDot-L151/target.c
diff -r 000000000000 -r 01f31e923fe2 records/daplink/bootloader.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/daplink/bootloader.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,27 @@ +common: + macros: + - DAPLINK_BL + - DAPLINK_BUILD_KEY=0x9B939D93 # DAPLINK_BUILD_KEY_BL + includes: + - source/daplink + - source/daplink/bootloader + - source/cmsis-core + - source/hic_hal + sources: + daplink_bl: + - source/daplink + - source/daplink/bootloader + +tool_specific: + uvision: + linker_file: + - source/daplink/daplink.sct + misc: + ld_flags: + - --predefine="-DDAPLINK_BL" + make_armcc: + linker_file: + - source/daplink/daplink.sct + misc: + ld_flags: + - --predefine="-DDAPLINK_BL"
diff -r 000000000000 -r 01f31e923fe2 records/daplink/cmsis-dap.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/daplink/cmsis-dap.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + includes: + - source/daplink/cmsis-dap + sources: + cmsis-dap: + - source/daplink/cmsis-dap
diff -r 000000000000 -r 01f31e923fe2 records/daplink/drag-n-drop.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/daplink/drag-n-drop.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,8 @@ +common: + macros: + - DRAG_N_DROP_SUPPORT + includes: + - source/daplink/drag-n-drop + sources: + drag-n-drop: + - source/daplink/drag-n-drop
diff -r 000000000000 -r 01f31e923fe2 records/daplink/interface.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/daplink/interface.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,27 @@ +common: + macros: + - DAPLINK_IF + - DAPLINK_BUILD_KEY=0x9B939E8F # DAPLINK_BUILD_KEY_IF + includes: + - source/daplink + - source/daplink/interface + - source/cmsis-core + - source/hic_hal + sources: + daplink_if: + - source/daplink + - source/daplink/interface + +tool_specific: + uvision: + linker_file: + - source/daplink/daplink.sct + misc: + ld_flags: + - --predefine="-DDAPLINK_IF" + make_armcc: + linker_file: + - source/daplink/daplink.sct + misc: + ld_flags: + - --predefine="-DDAPLINK_IF"
diff -r 000000000000 -r 01f31e923fe2 records/daplink/settings.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/daplink/settings.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + includes: + - source/daplink/settings + sources: + settings: + - source/daplink/settings/settings.c
diff -r 000000000000 -r 01f31e923fe2 records/daplink/settings_rom.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/daplink/settings_rom.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,4 @@ +common: + sources: + settings: + - source/daplink/settings/settings_rom.c
diff -r 000000000000 -r 01f31e923fe2 records/daplink/settings_rom_stub.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/daplink/settings_rom_stub.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,4 @@ +common: + sources: + settings: + - source/daplink/settings/settings_rom_stub.c
diff -r 000000000000 -r 01f31e923fe2 records/daplink/target_board.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/daplink/target_board.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + includes: + - source/target/ + sources: + target: + - source/target/target_board.c
diff -r 000000000000 -r 01f31e923fe2 records/daplink/target_family.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/daplink/target_family.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + includes: + - source/target/ + sources: + target: + - source/target/target_family.c
diff -r 000000000000 -r 01f31e923fe2 records/daplink/usb2uart.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/daplink/usb2uart.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + includes: + - source/daplink/usb2uart + sources: + usb2uart: + - source/daplink/usb2uart
diff -r 000000000000 -r 01f31e923fe2 records/family/all_family.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/family/all_family.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,14 @@ +common: + sources: + family: + - source/family/freescale/target_reset_Kseries.c + - source/family/freescale/target_reset_Lseries.c + - source/family/freescale/target_reset_mimxrt.c + - source/family/freescale/target_reset_rapid_iot.c + - source/family/nordic/target_reset_nrf51.c + - source/family/nordic/target_reset_nrf52.c + - source/family/realtek/target_reset_realtek_rtl8195am.c + - source/family/ti/target_reset_ti.c + - source/family/toshiba/target_reset_tz.c + - source/family/wiznet/target_reset_wiznet.c + - source/family/renesas/target_reset_rza.c
diff -r 000000000000 -r 01f31e923fe2 records/family/nordic_nrf51.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/family/nordic_nrf51.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,4 @@ +common: + sources: + target: + - source/target/nordic/target_reset_nrf51.c
diff -r 000000000000 -r 01f31e923fe2 records/family/nordic_nrf52.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/family/nordic_nrf52.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,4 @@ +common: + sources: + target: + - source/target/nordic/target_reset_nrf52.c
diff -r 000000000000 -r 01f31e923fe2 records/family/nxp_kinetis_kseries.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/family/nxp_kinetis_kseries.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,4 @@ +common: + sources: + target: + - source/target/freescale/target_reset_Kseries.c
diff -r 000000000000 -r 01f31e923fe2 records/family/nxp_kinetis_lseries.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/family/nxp_kinetis_lseries.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,4 @@ +common: + sources: + target: + - source/target/freescale/target_reset_Lseries.c
diff -r 000000000000 -r 01f31e923fe2 records/family/nxp_lpc4088.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/family/nxp_lpc4088.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,4 @@ +common: + sources: + target: + - source/target/nxp/target_reset_lpc4088.c
diff -r 000000000000 -r 01f31e923fe2 records/family/nxp_mimxrt.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/family/nxp_mimxrt.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,4 @@ +common: + sources: + target: + - source/target/freescale/target_reset_mimxrt.c
diff -r 000000000000 -r 01f31e923fe2 records/family/nxp_rapid_iot.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/family/nxp_rapid_iot.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,4 @@ +common: + sources: + target: + - source/target/freescale/target_reset_rapid_iot.c
diff -r 000000000000 -r 01f31e923fe2 records/family/realtek_rtl8195am.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/family/realtek_rtl8195am.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,4 @@ +common: + sources: + target: + - source/target/realtek/target_reset_realtek_rtl8195am.c
diff -r 000000000000 -r 01f31e923fe2 records/family/renesas_family.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/family/renesas_family.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,4 @@ +common: + sources: + target: + - source/target/renesas/target_reset_rza.c
diff -r 000000000000 -r 01f31e923fe2 records/family/ti_family.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/family/ti_family.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,4 @@ +common: + sources: + target: + - source/target/ti/target_reset_ti.c
diff -r 000000000000 -r 01f31e923fe2 records/family/toshiba_tz_family.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/family/toshiba_tz_family.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,4 @@ +common: + sources: + target: + - source/target/toshiba/target_reset_tz.c
diff -r 000000000000 -r 01f31e923fe2 records/family/wiznet_family.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/family/wiznet_family.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,4 @@ +common: + sources: + target: + - source/target/wiznet/target_reset_wiznet.c
diff -r 000000000000 -r 01f31e923fe2 records/hic_hal/k20dx.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/hic_hal/k20dx.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,47 @@ +common: + target: + - mk20dx128xxx5 + core: + - Cortex-M4 + macros: + - INTERFACE_K20D5 + - CPU_MK20DX128VFM5 + - DAPLINK_HIC_ID=0x97969900 # DAPLINK_HIC_ID_K20DX + - FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT=0 + - FLASH_DRIVER_IS_FLASH_RESIDENT=1 + - DAPLINK_NO_ASSERT_FILENAMES + - OS_CLOCK=48000000 + includes: + - source/hic_hal/freescale/k20dx + - source/hic_hal/freescale/k20dx/MK20D5 + - projectfiles/uvision/k20dx_bl/build + sources: + hic_hal: + - source/hic_hal/freescale + - source/hic_hal/freescale/k20dx + - source/hic_hal/freescale/k20dx/MK20D5 + - source/hic_hal/freescale/k20dx/armcc + fsl_flash_driver: + - source/hic_hal/freescale/iap + +tool_specific: + uvision: + misc: + ld_flags: + - --predefine="-I..\..\..\source\hic_hal\freescale\k20dx" + c_flags: + - --no_unaligned_access + cxx_flags: + - --no_unaligned_access + asm_flags: + - --no_unaligned_access + make_armcc: + misc: + ld_flags: + - --predefine="-Isource\hic_hal\freescale\k20dx" + c_flags: + - --no_unaligned_access + cxx_flags: + - --no_unaligned_access + asm_flags: + - --no_unaligned_access
diff -r 000000000000 -r 01f31e923fe2 records/hic_hal/k26f.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/hic_hal/k26f.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,48 @@ +common: + target: + - mk64fn1m0xxx12 # Closest device. + core: + - Cortex-M4F + macros: + - INTERFACE_K26F + - CPU_MK26FN2M0VMD18 + - DAPLINK_HIC_ID=0x97969909 # DAPLINK_HIC_ID_K26F + - FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT=0 + - FLASH_DRIVER_IS_FLASH_RESIDENT=1 + - OS_CLOCK=120000000 + includes: + - source/hic_hal/freescale/k26f + - source/hic_hal/freescale/k26f/MK26F18 + - source/hic_hal/freescale/iap + - projectfiles/uvision/k26f_bl/build + sources: + hic_hal: + - source/hic_hal/freescale/k26f + - source/hic_hal/freescale/k26f/MK26F18 + - source/hic_hal/freescale/k26f/armcc + fsl_flash_driver: + - source/hic_hal/freescale/iap + +tool_specific: + uvision: + misc: + ld_flags: + - --predefine="-I..\..\..\source\hic_hal\freescale\k26f" + c_flags: + - --no_unaligned_access + - --diag_suppress=66 # disable warning about enums not fitting in signed 32-bit + cxx_flags: + - --no_unaligned_access + asm_flags: + - --no_unaligned_access + make_armcc: + misc: + ld_flags: + - --predefine="-Isource\hic_hal\freescale\k26f" + c_flags: + - --no_unaligned_access + - --diag_suppress=66 # disable warning about enums not fitting in signed 32-bit + cxx_flags: + - --no_unaligned_access + asm_flags: + - --no_unaligned_access
diff -r 000000000000 -r 01f31e923fe2 records/hic_hal/kl26z.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/hic_hal/kl26z.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,35 @@ +common: + target: + - mkl26z128xxx4 + core: + - Cortex-M0+ + macros: + - INTERFACE_KL26Z + - CPU_MKL26Z128VLH4 + - DAPLINK_HIC_ID=0x97969901 # DAPLINK_HIC_ID_KL26 + - FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT=0 + - FLASH_DRIVER_IS_FLASH_RESIDENT=1 + - DAPLINK_NO_ASSERT_FILENAMES + - OS_CLOCK=48000000 + includes: + - source/hic_hal/freescale/kl26z + - source/hic_hal/freescale/kl26z/MKL26Z4 + - projectfiles/uvision/kl26z_bl/build + sources: + hic_hal: + - source/hic_hal/freescale + - source/hic_hal/freescale/kl26z + - source/hic_hal/freescale/kl26z/MKL26Z4 + - source/hic_hal/freescale/kl26z/armcc + fsl_flash_driver: + - source/hic_hal/freescale/iap + +tool_specific: + uvision: + misc: + ld_flags: + - --predefine="-I..\..\..\source\hic_hal\freescale\kl26z" + make_armcc: + misc: + ld_flags: + - --predefine="-Isource\hic_hal\freescale\kl26z"
diff -r 000000000000 -r 01f31e923fe2 records/hic_hal/lpc11u35.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/hic_hal/lpc11u35.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,27 @@ +common: + target: + - lpc11u35_501 + core: + - Cortex-M0 + macros: + - INTERFACE_LPC11U35 + - DAPLINK_HIC_ID=0x97969902 # DAPLINK_HIC_ID_LPC11U35 + - OS_CLOCK=48000000 + includes: + - source/hic_hal/nxp/lpc11u35 + - source/hic_hal/nxp/lpc11u35 + sources: + hic_hal: + - source/hic_hal/nxp/lpc11u35 + - source/hic_hal/nxp/lpc11u35/armcc + - source/hic_hal/nxp/lpc11u35 + +tool_specific: + uvision: + misc: + ld_flags: + - --predefine="-I..\..\..\source\hic_hal\nxp\lpc11u35" + make_armcc: + misc: + ld_flags: + - --predefine="-Isource\hic_hal\nxp\lpc11u35"
diff -r 000000000000 -r 01f31e923fe2 records/hic_hal/lpc4322.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/hic_hal/lpc4322.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,29 @@ +common: + target: + - lpc4322_jet100 + core: + - Cortex-M4 + macros: + - INTERFACE_LPC4322 + - CORE_M4 + - INTERNAL_FLASH + - DAPLINK_HIC_ID=0x97969905 # DAPLINK_HIC_ID_LPC4322 + - OS_CLOCK=96000000 + includes: + - source/hic_hal/nxp/lpc4322 + - source/hic_hal/nxp/lpc4322 + sources: + hic_hal: + - source/hic_hal/nxp/lpc4322 + - source/hic_hal/nxp/lpc4322/armcc + - source/hic_hal/nxp/lpc4322 + +tool_specific: + uvision: + misc: + ld_flags: + - --predefine="-I..\..\..\source\hic_hal\nxp\lpc4322" + make_armcc: + misc: + ld_flags: + - --predefine="-Isource\hic_hal\nxp\lpc4322"
diff -r 000000000000 -r 01f31e923fe2 records/hic_hal/m48ssidae.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/hic_hal/m48ssidae.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,43 @@ +common: + target: + - m485sidae + core: + - Cortex-M4F + macros: + - INTERFACE_M48SSIDAE + - DAPLINK_HIC_ID=0x97969921 # DAPLINK_HIC_ID_M48SSIDAE + - OS_CLOCK=192000000 + - DAPLINK_IF + includes: + - source/hic_hal/nuvoton/m48ssidae + - source/hic_hal/nuvoton/m48ssidae/CMSIS/Include + - source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Include + - source/hic_hal/nuvoton/m48ssidae/StdDriver/inc + sources: + hic_hal: + - source/hic_hal/nuvoton/m48ssidae + - source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Source + - source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Source/ARM + - source/hic_hal/nuvoton/m48ssidae/StdDriver/src + +tool_specific: + uvision: + misc: + ld_flags: + - --predefine="-I..\..\..\source\hic_hal\nuvoton\m48ssidae" + c_flags: + - --no_unaligned_access + cxx_flags: + - --no_unaligned_access + asm_flags: + - --no_unaligned_access + make_armcc: + misc: + ld_flags: + - --predefine="-Isource\hic_hal\nuvoton\m48ssidae" + c_flags: + - --no_unaligned_access + cxx_flags: + - --no_unaligned_access + asm_flags: + - --no_unaligned_access
diff -r 000000000000 -r 01f31e923fe2 records/hic_hal/max32620.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/hic_hal/max32620.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,25 @@ +common: + target: + - max32620 + core: + - Cortex-M4F + macros: + - INTERFACE_MAX32620 + - DAPLINK_HIC_ID=0x97969904 # DAPLINK_HIC_ID_MAX32620 + - OS_CLOCK=96000000 + includes: + - source/hic_hal/maxim/max32620 + sources: + hic_hal: + - source/hic_hal/maxim/max32620 + - source/hic_hal/maxim/max32620/armcc + +tool_specific: + uvision: + misc: + ld_flags: + - --predefine="-I..\..\..\source\hic_hal\maxim\max32620" + make_armcc: + misc: + ld_flags: + - --predefine="-Isource\hic_hal\maxim\max32620"
diff -r 000000000000 -r 01f31e923fe2 records/hic_hal/max32625.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/hic_hal/max32625.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,25 @@ +common: + target: + - max32625 + core: + - Cortex-M4F + macros: + - INTERFACE_MAX32625 + - DAPLINK_HIC_ID=0x97969906 # DAPLINK_HIC_ID_MAX32625 + - OS_CLOCK=96000000 + includes: + - source/hic_hal/maxim/max32625 + sources: + hic_hal: + - source/hic_hal/maxim/max32625 + - source/hic_hal/maxim/max32625/armcc + +tool_specific: + uvision: + misc: + ld_flags: + - --predefine="-I..\..\..\source\hic_hal\maxim\max32625" + make_armcc: + misc: + ld_flags: + - --predefine="-Isource\hic_hal\maxim\max32625"
diff -r 000000000000 -r 01f31e923fe2 records/hic_hal/sam3u2c.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/hic_hal/sam3u2c.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,29 @@ +common: + target: + - atsam3u2c + core: + - Cortex-M3 + macros: + - INTERFACE_SAM3U2C + - __SAM3U2C__ + - DAPLINK_HIC_ID=0x97969903 # DAPLINK_HIC_ID_SAM3U2C + - OS_CLOCK=96000000 + includes: + - source/hic_hal/atmel/sam3u2c + - source/hic_hal/atmel/sam3u2c + - projectfiles/uvision/sam3u2c_bl/build + sources: + hic_hal: + - source/hic_hal/atmel/sam3u2c + - source/hic_hal/atmel/sam3u2c/armcc + - source/hic_hal/atmel/sam3u2c + +tool_specific: + uvision: + misc: + ld_flags: + - --predefine="-I..\..\..\source\hic_hal\atmel\sam3u2c" + make_armcc: + misc: + ld_flags: + - --predefine="-Isource\hic_hal\atmel\sam3u2c"
diff -r 000000000000 -r 01f31e923fe2 records/hic_hal/stm32f103xb.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/hic_hal/stm32f103xb.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,46 @@ +common: + target: + - stm32f103xb + core: + - Cortex-M3 + macros: + - INTERFACE_STM32F103XB + - USE_HAL_DRIVER + - STM32F103xB + - DAPLINK_HIC_ID=0x97969908 # DAPLINK_HIC_ID_STM32F103XB + - __packed=__packed # Prevent redefinition of __packed with ARMCC + - DAPLINK_NO_ASSERT_FILENAMES + - OS_CLOCK=72000000 + includes: + - source/hic_hal/stm32/stm32f103xb + - source/hic_hal/stm32/stm32f103xb/cmsis + - source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver + - source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc + sources: + hic_hal: + - source/hic_hal/stm32/stm32f103xb + - source/hic_hal/stm32/stm32f103xb/cmsis + - source/hic_hal/stm32/stm32f103xb/armcc + - source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src + +tool_specific: + uvision: + misc: + ld_flags: + - --predefine="-I..\..\..\source\hic_hal\stm32\stm32f103xb" + c_flags: + - --no_unaligned_access + cxx_flags: + - --no_unaligned_access + asm_flags: + - --no_unaligned_access + make_armcc: + misc: + ld_flags: + - --predefine="-Isource\hic_hal\stm32\stm32f103xb" + c_flags: + - --no_unaligned_access + cxx_flags: + - --no_unaligned_access + asm_flags: + - --no_unaligned_access
diff -r 000000000000 -r 01f31e923fe2 records/rtos/rtos-cm0.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/rtos/rtos-cm0.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,21 @@ +common: + macros: + - OS_TICK=10000 + includes: + - source/rtos + sources: + rtos: + - source/rtos/cm0 + - source/rtos/rt_Event.c + - source/rtos/rt_List.c + - source/rtos/rt_Mailbox.c + - source/rtos/rt_MemBox.c + - source/rtos/rt_Mutex.c + - source/rtos/rt_Robin.c + - source/rtos/rt_Semaphore.c + - source/rtos/rt_System.c + - source/rtos/rt_Task.c + - source/rtos/rt_Time.c + - source/rtos/rt_Timer.c + - source/rtos/RTX_Config.c + - source/rtos/cmsis_os2_port.c
diff -r 000000000000 -r 01f31e923fe2 records/rtos/rtos-cm3.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/rtos/rtos-cm3.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,21 @@ +common: + macros: + - OS_TICK=10000 + includes: + - source/rtos + sources: + rtos: + - source/rtos/cm3 + - source/rtos/rt_Event.c + - source/rtos/rt_List.c + - source/rtos/rt_Mailbox.c + - source/rtos/rt_MemBox.c + - source/rtos/rt_Mutex.c + - source/rtos/rt_Robin.c + - source/rtos/rt_Semaphore.c + - source/rtos/rt_System.c + - source/rtos/rt_Task.c + - source/rtos/rt_Time.c + - source/rtos/rt_Timer.c + - source/rtos/RTX_Config.c + - source/rtos/cmsis_os2_port.c
diff -r 000000000000 -r 01f31e923fe2 records/rtos/rtos-cm4.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/rtos/rtos-cm4.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,21 @@ +common: + macros: + - OS_TICK=10000 + includes: + - source/rtos + sources: + rtos: + - source/rtos/cm4 + - source/rtos/rt_Event.c + - source/rtos/rt_List.c + - source/rtos/rt_Mailbox.c + - source/rtos/rt_MemBox.c + - source/rtos/rt_Mutex.c + - source/rtos/rt_Robin.c + - source/rtos/rt_Semaphore.c + - source/rtos/rt_System.c + - source/rtos/rt_Task.c + - source/rtos/rt_Time.c + - source/rtos/rt_Timer.c + - source/rtos/RTX_Config.c + - source/rtos/cmsis_os2_port.c
diff -r 000000000000 -r 01f31e923fe2 records/rtos/rtos-none.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/rtos/rtos-none.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,8 @@ +common: + macros: + - OS_TICK=10000 + includes: + - source/rtos_none + sources: + rtos: + - source/rtos_none
diff -r 000000000000 -r 01f31e923fe2 records/tools/make_armcc.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/tools/make_armcc.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,24 @@ +tool_specific: + make_armcc: + mcu: + - cortex-m0 + macros: + - + linker_file: + - source/daplink/daplink.sct + misc: + common_flags: + - -c + c_flags: + - -O2 + - --gnu + - --c99 + - --split_sections + - --interleave + linker_options: + - nostartfiles + pre_build_script: + - tools/pre_build_script.sh + post_build_script: + - tools/post_build_script.sh +
diff -r 000000000000 -r 01f31e923fe2 records/tools/make_gcc_arm.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/tools/make_gcc_arm.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,22 @@ +tool_specific: + make_gcc_arm: + mcu: + - cortex-m0 + macros: + - + misc: + libraries: + - m + - gcc + - c + - nosys + optimization: + - O3 + compiler_options: + - Wall + - ffunction-sections + - fdata-sections + linker_options: + - nostartfiles + +
diff -r 000000000000 -r 01f31e923fe2 records/tools/uvision.uvproj.tmpl
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/records/tools/uvision.uvproj.tmpl Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,412 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>Target 1</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M0</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
+ <DeviceId>4803</DeviceId>
+ <RegisterFile></RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile></SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\build\</OutputDirectory>
+ <OutputName>FlashAlgo</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\build\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>..\..\..\tools\pre_build_script.bat</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>2</nStopB1X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>..\..\..\tools\post_build_script.bat $L@L $KARM</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>2</nStopA1X>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>0</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Simulator>
+ <Target>
+ <UseTarget>1</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>1</RestoreTracepoints>
+ <RestoreSysVw>1</RestoreSysVw>
+ <UsePdscDebugDescription>0</UsePdscDebugDescription>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>-1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver></Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>0</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <bUseTDR>0</bUseTDR>
+ <Flash2></Flash2>
+ <Flash3>"" ()</Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>1</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M0"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>0</hadIROM>
+ <hadIRAM>0</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>0</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>0</RoSelD>
+ <RwSelD>0</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>0</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>0</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM>
+ <IROM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>3</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>1</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <uC99>0</uC99>
+ <useXO>0</useXO>
+ <VariousControls>
+ <MiscControls>--gnu --c99</MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <useXO>0</useXO>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>0</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x00000000</DataAddressRange>
+ <pXoBase></pXoBase>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Source Group 1</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff -r 000000000000 -r 01f31e923fe2 records/tools/version.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/tools/version.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,3 @@ +common: + macros: + - DAPLINK_VERSION=254
diff -r 000000000000 -r 01f31e923fe2 records/usb/usb-bulk.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/usb/usb-bulk.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + macros: + - BULK_ENDPOINT + sources: + usb: + - source/usb/bulk
diff -r 000000000000 -r 01f31e923fe2 records/usb/usb-cdc.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/usb/usb-cdc.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + macros: + - CDC_ENDPOINT + sources: + usb: + - source/usb/cdc
diff -r 000000000000 -r 01f31e923fe2 records/usb/usb-core.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/usb/usb-core.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + includes: + - source/usb + sources: + usb: + - source/usb/usbd_core.c
diff -r 000000000000 -r 01f31e923fe2 records/usb/usb-hid.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/usb/usb-hid.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + macros: + - HID_ENDPOINT + sources: + usb: + - source/usb/hid
diff -r 000000000000 -r 01f31e923fe2 records/usb/usb-msc.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/usb/usb-msc.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + macros: + - MSC_ENDPOINT + sources: + usb: + - source/usb/msc
diff -r 000000000000 -r 01f31e923fe2 records/usb/usb-webusb.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/usb/usb-webusb.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + macros: + - WEBUSB_INTERFACE + sources: + usb: + - source/usb/webusb
diff -r 000000000000 -r 01f31e923fe2 records/usb/usb-winusb.yaml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/records/usb/usb-winusb.yaml Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,6 @@ +common: + macros: + - WINUSB_INTERFACE + sources: + usb: + - source/usb/winusb
diff -r 000000000000 -r 01f31e923fe2 requirements.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/requirements.txt Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,15 @@ +project_generator==0.9.13 +mbed-ls==1.6.2 +pyserial +pyOCD==0.16.0 +requests +intelhex +six +enum34 +pyusb +mbed-cli==1.8.2 +bs4 +numpy +pyelftools +fuzzywuzzy +jsonschema
diff -r 000000000000 -r 01f31e923fe2 source/board/6LoWPAN_BorderRouterETHERNET.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/6LoWPAN_BorderRouterETHERNET.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file 6LoWPAN_BorderRouterETHERNET.c
+ * @brief board ID for the 6LoWPAN_BorderRouterETHERNET
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "7404",
+ .family_id = kNXP_KinetisK_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/6LoWPAN_BorderRouterHAT.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/6LoWPAN_BorderRouterHAT.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file 6LoWPAN_BorderRouterHAT.c
+ * @brief board ID for the 6LoWPAN_BorderRouterHAT
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "7402",
+ .family_id = kNXP_KinetisK_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/6LoWPAN_BorderRouterUSB.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/6LoWPAN_BorderRouterUSB.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,31 @@
+/**
+ * @file 6LoWPAN_BorderRouterUSB.c
+ * @brief board ID for the 6LoWPAN_BorderRouterUSB
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "7403",
+ .family_id = kNXP_KinetisK_FamilyID,
+ .target_cfg = &target_device,
+};
+
diff -r 000000000000 -r 01f31e923fe2 source/board/96b_nitrogen.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/96b_nitrogen.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,32 @@
+/**
+ * @file 96b_nitrogen.c
+ * @brief board ID for the Seeed Studio 96Boards Nitrogen board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+extern target_cfg_t target_device_nrf52;
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "9014",
+ .family_id = kNordic_Nrf52_FamilyID,
+ .target_cfg = &target_device_nrf52,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/FF1705_L151.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/FF1705_L151.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,34 @@
+/**
+ * @file FF1705_L151.c
+ * @brief board ID for the L-TEK FF1705
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "8080",
+ .family_id = kStub_HWReset_FamilyID,
+ .daplink_url_name = "FF1705 HTM",
+ .daplink_drive_name = "FF1705 ",
+ .daplink_target_url = "https://mbed.org/device/?code=@U?version=@V?target_id=@T",
+ .target_cfg = &target_device,
+};
+
diff -r 000000000000 -r 01f31e923fe2 source/board/archble.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/archble.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file archble.c
+ * @brief board ID for the Seeed Studio ArchBLE board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "9009",
+ .family_id = kNordic_Nrf51_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/archlink.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/archlink.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file archlink.c
+ * @brief board ID for the Seeed Studio ArchLink board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "9013",
+ .family_id = kNordic_Nrf51_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/archmax.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/archmax.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file archmax.c
+ * @brief board ID for the Seeed Studio ArchMax board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "9011",
+ .family_id = kStub_HWReset_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/archpro.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/archpro.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,31 @@
+/**
+ * @file archpro.c
+ * @brief board ID for the Seeed Studio ArchPro board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "9004",
+ .family_id = kStub_HWReset_FamilyID,
+ .target_cfg = &target_device,
+};
+
diff -r 000000000000 -r 01f31e923fe2 source/board/arm_watch_efm32.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/arm_watch_efm32.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file arm_watch_efm32.c
+ * @brief board ID for the ARM Wearable Reference Design EFM32 MCU
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "5051",
+ .family_id = kStub_SWSysReset_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/arm_watch_nrf51.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/arm_watch_nrf51.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file arm_watch_nrf51.c
+ * @brief board ID for the ARM Wearable Reference Design nRF51822 MCU
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "5052",
+ .family_id = kNordic_Nrf51_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/arm_watch_stm32f411.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/arm_watch_stm32f411.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,31 @@
+/**
+ * @file arm_watch_stm32f411.c
+ * @brief board ID for the ARM Wearable Reference Design STM32F411 MCU
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "5050",
+ .family_id = kStub_HWReset_FamilyID,
+ .target_cfg = &target_device,
+};
+
diff -r 000000000000 -r 01f31e923fe2 source/board/blueninja.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/blueninja.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,43 @@
+/**
+ * @file blueninja_sb.c
+ * @brief board ID for the Cerevo BlueNinja sub board & specific functions.
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "cmsis_os2.h"
+#include "IO_Config.h"
+#include "swd_host.h"
+#include "target_family.h"
+#include "target_board.h"
+
+static uint8_t target_set_state_by_board(target_state_t state)
+{
+
+ if (RESET_PROGRAM == state) {
+ LPC_GPIO->SET[PIN_PWH_PORT] = PIN_PWH;
+ osDelay(10);
+ }
+ return 1;
+}
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "7010",
+ .family_id = kToshiba_Tz_FamilyID,
+ .target_set_state = target_set_state_by_board,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/c027.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/c027.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file c027.c
+ * @brief board ID for the Ublox C027 board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "1234",
+ .family_id = kStub_HWReset_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/cocorico.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/cocorico.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file cocorico.c
+ * @brief board ID for the Elektor CoCo-ri-Co! board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "C000",
+ .family_id = kStub_HWReset_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/dipdap_cc3220sf.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/dipdap_cc3220sf.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,31 @@
+/**
+ * @file dipdap_cc3220sf.c
+ * @brief board ID for the dipdap cc3220sf board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "3300",
+ .family_id = kTI_Cc3220sf_FamilyID,
+ .flags = kEnablePageErase,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/dipdap_sdt32429b.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/dipdap_sdt32429b.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,31 @@
+/**
+ * @file dipdap_sdt32429b.c
+ * @brief board file for DIPDAP targeting STM32F429ZI
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2018, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "3108",
+ .family_id = kStub_HWReset_FamilyID,
+ .flags = kEnablePageErase,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/dipdap_sdt32439b.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/dipdap_sdt32439b.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,31 @@
+/**
+ * @file dipdap_sdt32439b.c
+ * @brief board file for DIPDAP targeting STM32F439ZI
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2018, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "3110",
+ .family_id = kStub_HWReset_FamilyID,
+ .flags = kEnablePageErase,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/dipdap_sdt51822b.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/dipdap_sdt51822b.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,31 @@
+/**
+ * @file dipdap_sdt51822b.c
+ * @brief board ID for the dipdap sdt51822 board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "3103",
+ .family_id = kNordic_Nrf51_FamilyID,
+ .flags = kEnablePageErase,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/dipdap_sdt52832b.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/dipdap_sdt52832b.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,33 @@
+/**
+ * @file dipdap_sdt52832b.c
+ * @brief board file for DIPDAP targeting nRF52832
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2018, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+extern target_cfg_t target_device_nrf52;
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "3104",
+ .family_id = kNordic_Nrf52_FamilyID,
+ .flags = kEnablePageErase,
+ .target_cfg = &target_device_nrf52,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/dipdap_sdt64b.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/dipdap_sdt64b.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,31 @@
+/**
+ * @file dipdap_sdt64b.c
+ * @brief board ID for the dipdap sdt64b board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "3105",
+ .family_id = kNXP_KinetisK_FamilyID,
+ .flags = kEnablePageErase,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/ep_agora.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/ep_agora.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,33 @@
+/**
+ * @file ep_agora.c
+ * @brief board ID for the Embedded Planet EP_AGORA
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+extern target_cfg_t target_device_nrf52840;
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .flags = kEnablePageErase,
+ .board_id = "2600",
+ .family_id = kNordic_Nrf52_FamilyID,
+ .target_cfg = &target_device_nrf52840,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/ff_lpc546xx.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/ff_lpc546xx.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,33 @@
+/**
+ * @file ff_lpc546xx.c
+ * @brief board ID for the NXP LPC54608Xpresso board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "8081",
+ .family_id = kStub_HWReset_FamilyID,
+ .daplink_url_name = "PRODINFOHTM",
+ .daplink_drive_name = "FF-LPC546XX",
+ .daplink_target_url = "https://os.mbed.com/platforms/L-TEK-FF-LPC546XX",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/frdmk20dx.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/frdmk20dx.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file frdmk20dx.c
+ * @brief board ID for the NXP FRDM-K20DX board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0230",
+ .family_id = kNXP_KinetisK_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/frdmk22f.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/frdmk22f.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file frdmk22f.c
+ * @brief board ID for the NXP FRDM-K22F board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0231",
+ .family_id = kNXP_KinetisK_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/frdmk28f.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/frdmk28f.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,33 @@
+/**
+ * @file frdmk28f.c
+ * @brief board ID for the NXP FRDM-K28F board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0224",
+ .family_id = kNXP_KinetisK_FamilyID,
+ .daplink_url_name = "PRODINFOHTM",
+ .daplink_drive_name = "FRDM-K28FD",
+ .daplink_target_url = "http://www.nxp.com/frdm-k28f",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/frdmk32w042.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/frdmk32w042.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,34 @@
+/**
+ * @file frdmk32w042.c
+ * @brief board ID for the NXP FRDM-K32W042 board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0225",
+ .family_id = kNXP_KinetisK32W_FamilyID,
+ .flags = kEnablePageErase,
+ .daplink_url_name = "PRODINFOHTM",
+ .daplink_drive_name = "K32W042",
+ .daplink_target_url = "http://www.nxp.com/frdm-k32w042",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/frdmk64f.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/frdmk64f.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,31 @@
+/**
+ * @file frdmk64f.c
+ * @brief board ID for the NXP FRDM-K64F board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0240",
+ .family_id = kNXP_KinetisK_FamilyID,
+ .flags = kEnablePageErase,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/frdmk66f.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/frdmk66f.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,35 @@
+/**
+ * @file frdmk66f.c
+ * @brief board ID for the NXP FRDM-K64F board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0311",
+ .family_id = kNXP_KinetisK_FamilyID,
+ .flags = kEnablePageErase,
+ .daplink_url_name = "PRODINFOHTM",
+ .daplink_drive_name = "FRDM-K66FD",
+ .daplink_target_url = "http://www.nxp.com/frdm-k66f",
+ .target_cfg = &target_device,
+};
+
diff -r 000000000000 -r 01f31e923fe2 source/board/frdmk82f.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/frdmk82f.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,33 @@
+/**
+ * @file frdmk66f.c
+ * @brief board ID for the NXP FRDM-K64F board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0217",
+ .family_id = kNXP_KinetisK_FamilyID,
+ .daplink_url_name = "PRODINFOHTM",
+ .daplink_drive_name = "FRDM-K82FD",
+ .daplink_target_url = "http://www.nxp.com/frdm-k82f",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/frdmke15z.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/frdmke15z.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,33 @@
+/**
+ * @file frdmke15z.c
+ * @brief board ID for the NXP FRDM-KE15Z board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0213",
+ .family_id = kNXP_KinetisL_FamilyID,
+ .daplink_url_name = "PRODINFOHTM",
+ .daplink_drive_name = "FRDM-KE15ZD",
+ .daplink_target_url = "http://www.nxp.com/frdm-ke15z",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/frdmkl02z.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/frdmkl02z.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file frdmkl02z.c
+ * @brief board ID for the NXP FRDM-KL02Z board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0204",
+ .family_id = kNXP_KinetisL_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/frdmkl05z.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/frdmkl05z.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file frdmkl05z.c
+ * @brief board ID for the NXP FRDM-KL05Z board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0210",
+ .family_id = kNXP_KinetisL_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/frdmkl25z.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/frdmkl25z.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file frdmkl25z.c
+ * @brief board ID for the NXP FRDM-KL25Z board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0200",
+ .family_id = kNXP_KinetisL_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/frdmkl26z.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/frdmkl26z.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file frdmkl26z.c
+ * @brief board ID for the NXP FRDM-KL26Z board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0260",
+ .family_id = kNXP_KinetisL_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/frdmkl27z.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/frdmkl27z.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,33 @@
+/**
+ * @file frdmkl27z.c
+ * @brief board ID for the NXP FRDM-KL27Z board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0261",
+ .family_id = kNXP_KinetisL_FamilyID,
+ .daplink_url_name = "PRODINFOHTM",
+ .daplink_drive_name = "FRDM-KL27ZD",
+ .daplink_target_url = "http://www.nxp.com/frdm-kl27z",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/frdmkl28z.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/frdmkl28z.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,33 @@
+/**
+ * @file frdmkl28z.c
+ * @brief board ID for the NXP FRDM-KL28Z board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0205",
+ .family_id = kNXP_KinetisL_FamilyID,
+ .daplink_url_name = "PRODINFOHTM",
+ .daplink_drive_name = "FRDM-KL28ZD",
+ .daplink_target_url = "http://www.nxp.com/frdm-kl28z",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/frdmkl43z.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/frdmkl43z.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,33 @@
+/**
+ * @file frdmkl43z.c
+ * @brief board ID for the NXP FRDM-KL43Z board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0262",
+ .family_id = kNXP_KinetisL_FamilyID,
+ .daplink_url_name = "PRODINFOHTM",
+ .daplink_drive_name = "FRDM-KL43ZD",
+ .daplink_target_url = "http://www.nxp.com/frdm-kl43z",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/frdmkl46z.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/frdmkl46z.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file frdmkl46z.c
+ * @brief board ID for the NXP FRDM-KL46Z board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0220",
+ .family_id = kNXP_KinetisL_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/frdmkl82z.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/frdmkl82z.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,33 @@
+/**
+ * @file frdmkl82z.c
+ * @brief board ID for the NXP FRDM-KL82Z board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0218",
+ .family_id = kNXP_KinetisL_FamilyID,
+ .daplink_url_name = "PRODINFOHTM",
+ .daplink_drive_name = "FRDM-KL82Z",
+ .daplink_target_url = "http://www.nxp.com/frdm-kl82z",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/frdmkw24d.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/frdmkw24d.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,34 @@
+/**
+ * @file frdmkw24d.c
+ * @brief board ID for the NXP FRDM-KW24D board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0250",
+ .family_id = kNXP_KinetisK_FamilyID,
+ .daplink_url_name = "PRODINFOHTM",
+ .daplink_drive_name = "FRDM-KW24D",
+ .daplink_target_url = "http://www.nxp.com/frdm-kw24d",
+ .target_cfg = &target_device,
+};
+
diff -r 000000000000 -r 01f31e923fe2 source/board/frdmkw41z.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/frdmkw41z.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,34 @@
+/**
+ * @file frdmkw41z.c
+ * @brief board ID for the NXP FRDM-KW24F board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0201",
+ .family_id = kNXP_KinetisL_FamilyID,
+ .daplink_url_name = "PRODINFOHTM",
+ .daplink_drive_name = "FRDM-KW41Z",
+ .daplink_target_url = "http://www.nxp.com/frdm-kw41z",
+ .target_cfg = &target_device,
+};
+
diff -r 000000000000 -r 01f31e923fe2 source/board/gr-lychee.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/gr-lychee.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,32 @@
+/**
+ * @file gr-lychee.c
+ * @brief board ID for the GR-LYCHEE
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "5501",
+ .family_id = kStub_HWReset_FamilyID,
+ .flags = kEnablePageErase,
+ .daplink_drive_name = "MBED ",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/gr-peach.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/gr-peach.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,32 @@
+/**
+ * @file gr-peach.c
+ * @brief board ID for the GR-PEACH
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "5500",
+ .family_id = kStub_HWReset_FamilyID,
+ .flags = kEnablePageErase,
+ .daplink_drive_name = "MBED ",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/hani_iot.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/hani_iot.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,35 @@
+/**
+ * @file hani_iot.c
+ * @brief board ID for the Arrow HANI_IOT board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0360",
+ .family_id = VENDOR_TO_FAMILY(kNXP_VendorID, 0), //ID not maching the predefined family ids
+ .flags = kEnablePageErase,
+ .daplink_url_name = "PRODINFOHTM",
+ .daplink_drive_name = "HANI_IOT",
+ .daplink_target_url = "https://os.mbed.com/platforms/HANI-IOT/",
+ .target_cfg = &target_device,
+};
+
diff -r 000000000000 -r 01f31e923fe2 source/board/hexiwear.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/hexiwear.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,92 @@
+/**
+ * @file hexiwear.c
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2018, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "swd_host.h"
+#include "target_board.h"
+#include "target_family.h"
+
+char *board_id_kw41z = "0234";
+
+#define MDM_STATUS 0x01000000
+#define MDM_CTRL 0x01000004
+#define MDM_IDR 0x010000fc
+#define MDM_ID_K64 0x001c0000 // K64
+#define MDM_ID_KW4 0x001c0020 // KW4
+
+/* Kinetis series ID */
+#define K_SERIES 0
+#define KW_SERIES 5
+
+/* KW4 subfamily defines */
+#define KW40 0
+#define KW41 1
+
+static void prerun_board_config(void);
+
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0214",
+ .family_id = kNXP_RapidIot_FamilyID,
+ .flags = kEnablePageErase,
+ .daplink_url_name = "PRODINFOHTM",
+ .daplink_drive_name = "HEX-DAPLINK",
+ .daplink_target_url = "http://www.hexiwear.com/",
+ .target_cfg = &target_device,
+ .prerun_board_config = prerun_board_config,
+};
+
+static void prerun_board_config(void)
+{
+ // SIM peripheral 0x40047000
+ // address offset 0x 1024
+ uint32_t SDID = 0x40048024;
+ uint32_t sdid;
+
+ // get a hold of the target
+ if (target_set_state(HALT) == 0) {
+ /*
+ * When the Kinetis flash is empty the reset line toggles. This causes failures
+ * when trying to halt the target. Use the reset halt method in this case.
+ */
+ target_set_state(RESET_PROGRAM);
+ }
+
+ // Read the system identification register
+ swd_read_memory(SDID, (uint8_t *)&sdid, 4);
+
+ // Set the target flash algorithm
+ if (((sdid >> 20) & 0xF) == KW_SERIES) {
+
+ if (((sdid >> 24) & 0x3) == KW40) {
+ // Program to the KW40 flash
+ extern target_cfg_t target_device_kw40;
+ target_device = target_device_kw40;
+ } else {
+ // Program to the KW41 flash
+ extern target_cfg_t target_device_kw41;
+ target_device = target_device_kw41;
+ target_device.rt_board_id = board_id_kw41z;
+ }
+ }
+
+ // Let the target run
+ target_set_state(RUN);
+}
diff -r 000000000000 -r 01f31e923fe2 source/board/hrm1017.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/hrm1017.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file hrm1017.c
+ * @brief board ID for the Switch Science HRM1017 board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "1017",
+ .family_id = kNordic_Nrf51_FamilyID,
+ .daplink_drive_name = "MBED ",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/hvpke18f.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/hvpke18f.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,33 @@
+/**
+ * @file hvpke18f.c
+ * @brief board ID for the NXP HVP-KE18F board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0216",
+ .family_id = kNXP_KinetisK_FamilyID,
+ .daplink_url_name = "PRODINFOHTM",
+ .daplink_drive_name = "HVP-KE18FD",
+ .daplink_target_url = "http://www.nxp.com/hvp-ke18f",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/k20dx_bl.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/k20dx_bl.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,65 @@
+/**
+ * @file k20dx_bl.c
+ * @brief board ID and meta-data for the hardware interface circuit (HIC) based on the NXP K20DX
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+#include "daplink_addr.h"
+#include "compiler.h"
+#include "target_board.h"
+#include "target_family.h"
+
+// Warning - changing the interface start will break backwards compatibility
+COMPILER_ASSERT(DAPLINK_ROM_IF_START == KB(32));
+COMPILER_ASSERT(DAPLINK_ROM_IF_SIZE == KB(95));
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {DAPLINK_ROM_IF_START, 1024},
+ };
+
+// k20dx128 target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = DAPLINK_ROM_IF_START,
+ .flash_regions[0].end = DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .ram_regions[0].start = 0x1fffe000,
+ .ram_regions[0].end = 0x20002000,
+ // flash_algo not needed for bootloader
+};
+
+//bootloader has no family
+const target_family_descriptor_t *g_target_family = NULL;
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0000",
+ .daplink_url_name = "HELP_FAQHTM",
+ .daplink_drive_name = "MAINTENANCE",
+ .daplink_target_url = "https://mbed.com/daplink",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/k26f_bl.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/k26f_bl.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,64 @@
+/**
+ * @file k26f_bl.c
+ * @brief board ID and meta-data for the hardware interface circuit (HIC) based on the NXP K26F
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+#include "daplink_addr.h"
+#include "compiler.h"
+#include "target_board.h"
+#include "target_family.h"
+
+// Warning - changing the interface start will break backwards compatibility
+COMPILER_ASSERT(DAPLINK_ROM_IF_START == KB(64));
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {DAPLINK_ROM_IF_START, DAPLINK_SECTOR_SIZE},
+ };
+
+// k26f target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = DAPLINK_ROM_IF_START,
+ .flash_regions[0].end = DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .ram_regions[0].start = 0x1fff0000,
+ .ram_regions[0].end = 0x20030000,
+ /* .flash_algo not needed for bootloader */
+};
+
+//bootloader has no family
+const target_family_descriptor_t *g_target_family = NULL;
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0000",
+ .daplink_url_name = "HELP_FAQHTM",
+ .daplink_drive_name = "BOOTLOADER",
+ .daplink_target_url = "https://mbed.com/daplink",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/kl26z_bl.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/kl26z_bl.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,64 @@
+/**
+ * @file kl26z_bl.c
+ * @brief board ID and meta-data for the hardware interface circuit (HIC) based on the NXP KL26Z
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+#include "daplink_addr.h"
+#include "compiler.h"
+#include "target_board.h"
+#include "target_family.h"
+
+// Warning - changing the interface start will break backwards compatibility
+COMPILER_ASSERT(DAPLINK_ROM_IF_START == KB(32));
+COMPILER_ASSERT(DAPLINK_ROM_IF_SIZE == KB(95));
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {DAPLINK_ROM_IF_START, 1024},
+ };
+
+// kl26z128 target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = DAPLINK_ROM_IF_START,
+ .flash_regions[0].end = DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .ram_regions[0].start = 0x1FFFF000,
+ .ram_regions[0].end = 0x20003000,
+};
+
+//bootloader has no family
+const target_family_descriptor_t *g_target_family = NULL;
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0000",
+ .daplink_url_name = "HELP_FAQHTM",
+ .daplink_drive_name = "MAINTENANCE",
+ .daplink_target_url = "https://mbed.com/daplink",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/lpc4088dm.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/lpc4088dm.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file lpc4088dm.c
+ * @brief board ID for the Embedded Artists LPC4088 Display Module
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "1062",
+ .family_id = VENDOR_TO_FAMILY(kNXP_VendorID, 0), //custom
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/lpc4088qsb.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/lpc4088qsb.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file lpc4088qsb.c
+ * @brief board ID for the Embedded Artists LPC4088 QuickStart Board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "1060",
+ .family_id = VENDOR_TO_FAMILY(kNXP_VendorID, 0), //custom
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/lpc4322_bl.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/lpc4322_bl.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,65 @@
+/**
+ * @file lpc4322_bl.c
+ * @brief board ID and meta-data for the hardware interface circuit (HIC) based on the NXP LPC4322
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+#include "daplink_addr.h"
+#include "compiler.h"
+#include "target_board.h"
+#include "target_family.h"
+
+// Warning - changing the interface start will break backwards compatibility
+COMPILER_ASSERT(DAPLINK_ROM_IF_START == 0x1A010000);
+COMPILER_ASSERT(DAPLINK_ROM_IF_SIZE == (0x1A030000 - 0x1A010000));
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {DAPLINK_ROM_IF_START, 65536},
+ };
+
+// lpc4322 target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = DAPLINK_ROM_IF_START,
+ .flash_regions[0].end = DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .ram_regions[0].start = 0x10000000,
+ .ram_regions[0].end = 0x10008000,
+ /* .flash_algo not needed for bootloader */
+};
+
+//bootloader has no family
+const target_family_descriptor_t *g_target_family = NULL;
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0000",
+ .daplink_url_name = "HELP_FAQHTM",
+ .daplink_drive_name = "MAINTENANCE",
+ .daplink_target_url = "https://mbed.com/daplink",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/lpc54114xpresso.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/lpc54114xpresso.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,33 @@
+/**
+ * @file lpc54114xpresso.c
+ * @brief board ID for the NXP LPC54114Xpresso board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "1054",
+ .family_id = kStub_HWReset_FamilyID,
+ .daplink_url_name = "PRODINFOHTM",
+ .daplink_drive_name = "LPC54114",
+ .daplink_target_url = "https://os.mbed.com/platforms/LPCXpresso54114/",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/lpc54608xpresso.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/lpc54608xpresso.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,33 @@
+/**
+ * @file lpc54608xpresso.c
+ * @brief board ID for the NXP LPC54608Xpresso board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "1056",
+ .family_id = kStub_HWReset_FamilyID,
+ .daplink_url_name = "PRODINFOHTM",
+ .daplink_drive_name = "LPC546XX",
+ .daplink_target_url = "https://os.mbed.com/platforms/LPCXpresso54608/",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/lpc55S69xpresso.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/lpc55S69xpresso.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,35 @@
+/**
+ * @file lpc55S69xpresso.c
+ * @brief board ID for the NXP LPC54608Xpresso board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0236",
+ .family_id = VENDOR_TO_FAMILY(kNXP_VendorID, 0), //ID not maching the predefined family ids
+ .flags = kEnablePageErase,
+ .daplink_url_name = "PRODINFOHTM",
+ .daplink_drive_name = "LPC55S69",
+ .daplink_target_url = "https://os.mbed.com/platforms/LPCXpresso55S69/",
+ .target_cfg = &target_device,
+};
+
diff -r 000000000000 -r 01f31e923fe2 source/board/lpc812xpresso.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/lpc812xpresso.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file lpc812xpresso.c
+ * @brief board ID for the NXP LPC812Xpresso board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "1050",
+ .family_id = kStub_HWReset_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/lpc824xpresso.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/lpc824xpresso.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file lpc824xpresso.c
+ * @brief board ID for the NXP LPC824Xpresso board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0824",
+ .family_id = kStub_HWReset_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/m48ssidae_bl.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/m48ssidae_bl.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,65 @@
+/**
+ * @file m48ssidae_bl.c
+ * @brief board ID and meta-data for the hardware interface circuit (HIC) based on Nuvoton M48SSIDAE
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+#include "daplink_addr.h"
+#include "compiler.h"
+#include "target_board.h"
+#include "target_family.h"
+
+// Warning - changing the interface start will break backwards compatibility
+COMPILER_ASSERT(DAPLINK_ROM_IF_START == 0x0000C000);
+COMPILER_ASSERT(DAPLINK_ROM_IF_SIZE == KB(204));
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {DAPLINK_ROM_IF_START, 0x1000},
+};
+
+// m48ssidae target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = DAPLINK_ROM_IF_START,
+ .flash_regions[0].end = DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .ram_regions[0].start = DAPLINK_RAM_START,
+ .ram_regions[0].end = DAPLINK_RAM_START + DAPLINK_RAM_SIZE,
+ /* .flash_algo not needed for bootloader */
+};
+
+// bootloader has no family
+const target_family_descriptor_t *g_target_family = NULL;
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0000",
+ .daplink_url_name = "HELP_FAQHTM",
+ .daplink_drive_name = "MAINTENANCE",
+ .daplink_target_url = "https://mbed.com/daplink",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/max32620_bl.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/max32620_bl.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,59 @@
+/**
+ * @file max32620_bl.c
+ * @brief board ID and meta-data for the hardware interface circuit (HIC) based on MAX32620
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+#include "target_board.h"
+#include "target_family.h"
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x00000000 + 0x10000, 0x2000},
+ };
+
+/* ME02 -- MAX32620 2MiB Flash, 256KiB RAM */
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x00000000 + 0x10000,
+ .flash_regions[0].end = 0x00000000 + MB(2),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20040000,
+ /* .flash_algo not needed for bootloader */
+};
+
+//bootloader has no family
+const target_family_descriptor_t *g_target_family = NULL;
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0000",
+ .daplink_url_name = "HELP_FAQHTM",
+ .daplink_drive_name = "MAINTENANCE",
+ .daplink_target_url = "https://mbed.com/daplink",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/max32620fthr.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/max32620fthr.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file max32620fthr.c
+ * @brief board ID for the Maxim Integrated's MAX32620FTHR
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .board_id = "0418",
+ .family_id = kStub_HWReset_FamilyID,
+ .flags = kEnablePageErase,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/max32625_bl.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/max32625_bl.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,61 @@
+/**
+ * @file max32625_bl.c
+ * @brief board ID and meta-data for the hardware interface circuit (HIC) based on MAX32625
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+#include "target_board.h"
+#include "target_family.h"
+
+const char *board_id = "0000";
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x00000000 + 0x10000, 0x2000},
+ };
+
+/* ME03 -- MAX32625 512KiB Flash, 160KiB RAM */
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x00000000 + 0x10000,
+ .flash_regions[0].end = 0x00000000 + KB(512),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20028000,
+ /* .flash_algo not needed for bootloader */
+};
+
+//bootloader has no family
+const target_family_descriptor_t *g_target_family = NULL;
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0000",
+ .daplink_url_name = "HELP_FAQHTM",
+ .daplink_drive_name = "MAINTENANCE",
+ .daplink_target_url = "https://mbed.com/daplink",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/max32625mbed.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/max32625mbed.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file max32625mbed.c
+ * @brief board ID for the Maxim Integrated's MAX32625MBED
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .board_id = "0415",
+ .family_id = kStub_HWReset_FamilyID,
+ .flags = kEnablePageErase,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/max32630fthr.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/max32630fthr.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file max32630fthr.c
+ * @brief board ID for the Maxim Integrated's MAX32630FTHR
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .board_id = "0409",
+ .family_id = kStub_HWReset_FamilyID,
+ .flags = kEnablePageErase,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/mbed_cloud_connect.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/mbed_cloud_connect.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,31 @@
+/**
+ * @file mbed_cloud_connect.c
+ * @brief board ID for the mbed cloud connect board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "2410",
+ .family_id = kStub_HWReset_FamilyID,
+ .flags = kEnablePageErase,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/microbit.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/microbit.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,89 @@
+/**
+ * @file microbit.c
+ * @brief board ID for the BBC Microbit board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "fsl_device_registers.h"
+#include "IO_Config.h"
+#include "DAP.h"
+#include "target_family.h"
+#include "target_board.h"
+
+const char * const board_id_mb_1_3 = "9900";
+const char * const board_id_mb_1_5 = "9901";
+
+typedef enum {
+ BOARD_VERSION_1_3 = 0,
+ BOARD_VERSION_1_5 = 1,
+} mb_version_t;
+
+// Enables Board Type Pin, reads it and disables it
+// Depends on gpio_init() to have been executed already
+static uint8_t read_board_type_pin(void) {
+ uint8_t pin_state = 0;
+ // GPIO mode, Pull enable, pull down, input
+ PIN_BOARD_TYPE_PORT->PCR[PIN_BOARD_TYPE_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE(1) | PORT_PCR_PS(0);
+ PIN_BOARD_TYPE_GPIO->PDDR &= ~PIN_BOARD_TYPE;
+ // Wait to stabilise, based on gpio.c busy_wait(), at -O2 10000 iterations delay ~850us
+ for (volatile uint32_t i = 10000; i > 0; i--);
+ // Read pin
+ pin_state = (PIN_BOARD_TYPE_GPIO->PDIR & PIN_BOARD_TYPE);
+ // Revert and disable
+ PIN_BOARD_TYPE_PORT->PCR[PIN_BOARD_TYPE_BIT] = PORT_PCR_MUX(0) | PORT_PCR_PE(0);
+ return pin_state;
+}
+
+static void set_board_id(mb_version_t board_version) {
+ switch (board_version) {
+ case BOARD_VERSION_1_3:
+ target_device.rt_board_id = board_id_mb_1_3;
+ break;
+ case BOARD_VERSION_1_5:
+ target_device.rt_board_id = board_id_mb_1_5;
+ break;
+ default:
+ target_device.rt_board_id = board_id_mb_1_5;
+ break;
+ }
+}
+
+// Called in main_task() to init before USB and files are configured
+static void prerun_board_config(void) {
+ // With only two boards the digital pin read maps directly to the type
+ mb_version_t board_version = (mb_version_t)read_board_type_pin();
+ set_board_id(board_version);
+}
+
+// USB HID override function return 1 if the activity is trivial or response is null
+uint8_t usbd_hid_no_activity(uint8_t *buf)
+{
+ if(buf[0] == ID_DAP_Vendor3 && buf[1] == 0)
+ return 1;
+ else
+ return 0;
+}
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .family_id = kNordic_Nrf51_FamilyID,
+ .daplink_url_name = "MICROBITHTM",
+ .daplink_drive_name = "MICROBIT ",
+ .daplink_target_url = "https://microbit.org/device/?id=@B&v=@V",
+ .prerun_board_config = prerun_board_config,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/mimxrt1020_evk.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/mimxrt1020_evk.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,34 @@
+/**
+ * @file mimxrt1020_evk.c
+ * @brief board ID for the NXP MIMXRT1020-EVK board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0226",
+ .family_id = kNXP_Mimxrt_FamilyID,
+ .flags = kEnablePageErase,
+ .daplink_url_name = "PRODINFOHTM",
+ .daplink_drive_name = "RT1020-EVK",
+ .daplink_target_url = "http://www.nxp.com/imxrt1020evk",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/mimxrt1050_evk.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/mimxrt1050_evk.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,33 @@
+/**
+ * @file mimxrt1050_evk.c
+ * @brief board ID for the NXP MIMXRT1050-EVK board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0227",
+ .family_id = kNXP_Mimxrt_FamilyID,
+ .daplink_url_name = "PRODINFOHTM",
+ .daplink_drive_name = "RT1050-EVK",
+ .daplink_target_url = "http://www.nxp.com/imxrt1050evk",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/mini_iot_lpc54018.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/mini_iot_lpc54018.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,33 @@
+/**
+ * @file iotmodule_lpc54018.c
+ * @brief board ID for the NXP LPC54608Xpresso board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2018-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .board_id = "0235",
+ .family_id = kStub_SWVectReset_FamilyID,
+ .flags = kEnablePageErase,
+ .daplink_url_name = "PRODINFOHTM",
+ .daplink_drive_name = "MINI-54018",
+ .daplink_target_url = "https://os.mbed.com/platforms/LPC54018IoTModule/",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/mkit_dk_dongle_nrf5x.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/mkit_dk_dongle_nrf5x.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,140 @@
+/**
+ * @file nrf5x.c
+ * @brief board ID for the Nordic nRF5x developments boards
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "sam3u2c.h"
+#include "DAP_config.h"
+#include "target_config.h"
+#include "util.h"
+#include "flash_manager.h"
+#include "target_family.h"
+#include "target_board.h"
+
+// BOARD_ID pointer will be set during run time to point to one of these
+const char *board_id_nrf51_mkit = "1070";
+const char *board_id_nrf51_dk = "1100";
+const char *board_id_nrf51_dongle = "1120";
+const char *board_id_nrf52_dk = "1101";
+const char *board_id_nrf52840_dk = "1102";
+
+extern target_cfg_t target_device_nrf52;
+extern target_cfg_t target_device_nrf52840;
+static uint8_t device_type;
+
+static void set_target_device(uint32_t device)
+{
+ device_type = device;
+ if (device == 0) {
+ // Target device already set to nRF51
+ }
+ else if (device == 1) {
+ target_device = target_device_nrf52;
+ }
+ else if (device == 2) {
+ target_device = target_device_nrf52840;
+ }
+}
+
+
+static void nrf_prerun_board_config(void)
+{
+ // Work around for setting the correct board id based on GPIOs
+ uint8_t bit1;
+ uint8_t bit2;
+ uint8_t bit3;
+
+ PIOB->PIO_PER = (1 << 1); // Enable PIO pin PB1
+ PIOB->PIO_PER = (1 << 2); // Enable PIO pin PB2
+ PIOB->PIO_PER = (1 << 3); // Enable PIO pin PB3
+ PIOB->PIO_ODR = (1 << 1); // Disabe output
+ PIOB->PIO_ODR = (1 << 2); // Disabe output
+ PIOB->PIO_ODR = (1 << 3); // Disabe output
+ PIOB->PIO_PUER = (1 << 1); // Enable pull-up
+ PIOB->PIO_PUER = (1 << 2); // Enable pull-up
+ PIOB->PIO_PUER = (1 << 3); // Enable pull-up
+
+ bit1 = (PIOB->PIO_PDSR >> 1) & 1; // Read PB1
+ bit2 = (PIOB->PIO_PDSR >> 2) & 1; // Read PB2
+ bit3 = (PIOB->PIO_PDSR >> 3) & 1; // Read PB3
+
+ /* pins translate to board-ids as follow
+ *
+ * PB3|PB2|PB1|BOARD ID| BOARD
+ * ----------------------------------
+ * 0 | 0 | 0 | 1120 | nRF51-Dongle
+ * 0 | 0 | 1 | 1100 | nRF51-DK
+ * 0 | 1 | 0 | 1101 | nRF52-DK
+ * 0 | 1 | 1 | 1102 | nRF52840-DK
+ * 1 | 1 | 1 | 1070 | older nRF51 (mkit)
+ * 1 | 0 | 0 | undefined
+ * 1 | 0 | 1 | undefined
+ * 1 | 1 | 0 | undefined
+ */
+
+
+ if (bit3) {
+ set_target_device(0);
+ target_device.rt_family_id = kNordic_Nrf51_FamilyID;
+ target_device.rt_board_id = board_id_nrf51_mkit; // 1070
+ //Note only a setting of 111 is defined
+ util_assert(bit2 && bit1);
+ } else {
+ if (!bit2 && bit1) {
+ set_target_device(0);
+ target_device.rt_family_id = kNordic_Nrf51_FamilyID;
+ target_device.rt_board_id = board_id_nrf51_dk; // 1100
+ }
+ else if (!bit2 && !bit1) {
+ set_target_device(0);
+ target_device.rt_family_id = kNordic_Nrf51_FamilyID;
+ target_device.rt_board_id = board_id_nrf51_dongle; // 1120
+ }
+ else if (bit2 && !bit1) {
+ set_target_device(1);
+ target_device.rt_family_id = kNordic_Nrf52_FamilyID;
+ target_device.rt_board_id = board_id_nrf52_dk; // 1101
+ } else { //(bit2 && bit1)
+ set_target_device(2);
+ target_device.rt_family_id = kNordic_Nrf52_FamilyID;
+ target_device.rt_board_id = board_id_nrf52840_dk; // 1102
+ }
+ }
+
+ PIOB->PIO_PUDR = (1 << 1); // Disable pull-up
+ PIOB->PIO_PUDR = (1 << 2); // Disable pull-up
+ PIOB->PIO_PUDR = (1 << 3); // Disable pull-up
+}
+
+static void nrf_swd_set_target_reset(uint8_t asserted){
+ if (asserted && device_type == 0) {
+ PIOA->PIO_OER = PIN_SWDIO;
+ PIOA->PIO_OER = PIN_SWCLK;
+ }else if(!asserted) {
+ PIOA->PIO_MDER = PIN_SWDIO | PIN_SWCLK | PIN_nRESET;
+ }
+}
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .flags = kEnablePageErase,
+ .prerun_board_config = nrf_prerun_board_config,
+ .swd_set_target_reset = nrf_swd_set_target_reset,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/mtb_aconno_acn52832.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/mtb_aconno_acn52832.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,31 @@
+/**
+ * @file mtb_aconno_acn52832.c
+ * @brief board ID for mtb_aconno_acn52832
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+extern target_cfg_t target_device_nrf52_64;
+
+const board_info_t g_board_info = {
+ .board_id = "0472",
+ .family_id = kNordic_Nrf52_FamilyID,
+ .target_cfg = &target_device_nrf52_64,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/mtb_laird_bl652.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/mtb_laird_bl652.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,32 @@
+/**
+ * @file mtb_laird_bl652.c
+ * @brief board ID for the Laird BL652
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+extern target_cfg_t target_device_nrf52;
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0461",
+ .family_id = kNordic_Nrf52_FamilyID,
+ .target_cfg = &target_device_nrf52,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/mtb_laird_bl654.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/mtb_laird_bl654.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,33 @@
+/**
+ * @file mtb_laird_bl654.c
+ * @brief board ID for the Laird BL654
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+extern target_cfg_t target_device_nrf52840_256;
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0465",
+ .family_id = kNordic_Nrf52_FamilyID,
+ .target_cfg = &target_device_nrf52840_256,
+};
+
diff -r 000000000000 -r 01f31e923fe2 source/board/mtb_mts_dragonfly.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/mtb_mts_dragonfly.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file mtb_mts_dragonfly.c
+ * @brief board ID for the MTB Dragonfly
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0454",
+ .family_id = kStub_HWReset_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/mtb_mts_xdot.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/mtb_mts_xdot.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file mtb_mts_xdot.c
+ * @brief board ID for the MultiTech xDot
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0453",
+ .family_id = kStub_HWReset_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/mtb_murata_abz_078.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/mtb_murata_abz_078.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,31 @@
+/**
+ * @file mtb_murata_abz_078.c
+ * @brief board ID for the Murata abz
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0456",
+ .family_id = kStub_HWReset_FamilyID,
+ .flags = kEnablePageErase,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/mtb_murata_bl241.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/mtb_murata_bl241.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,32 @@
+/**
+ * @file mtb_murata_bl241.c
+ * @brief board ID for the Murata bl241
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+extern target_cfg_t target_device_nrf52_64;
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0466",
+ .family_id = kNordic_Nrf52_FamilyID,
+ .target_cfg = &target_device_nrf52_64,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/mtb_mxchip_emw3166.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/mtb_mxchip_emw3166.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file mtb_mxchip_emw3166.c
+ * @brief board ID for MXCHIP EMW3166
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0451",
+ .family_id = kStub_HWReset_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/mtb_nina_b112.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/mtb_nina_b112.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,32 @@
+/**
+ * @file mtb_ninab112.c
+ * @brief board ID for MTB nina
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+extern target_cfg_t target_device_nrf52;
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0455",
+ .family_id = kNordic_Nrf52_FamilyID,
+ .target_cfg = &target_device_nrf52,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/mtb_rak811.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/mtb_rak811.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,31 @@
+/**
+ * @file mtb_rak811.c
+ * @brief board ID for the RAK811
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0457",
+ .family_id = kStub_HWReset_FamilyID,
+ .flags = kEnablePageErase,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/mtb_stm32f439.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/mtb_stm32f439.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file mtb_stm32f439.c
+ * @brief board file for stm32f439
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2018-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .board_id = "0469",
+ .family_id = kStub_HWReset_FamilyID,
+ .flags = kEnablePageErase|kEnableUnderResetConnect,
+ .target_cfg = &target_device,
+};
\ No newline at end of file
diff -r 000000000000 -r 01f31e923fe2 source/board/mtb_stm32l475.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/mtb_stm32l475.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,32 @@
+/**
+ * @file mtb_stm32l475.c
+ * @brief board ID for the mtb_stm32l475
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+extern target_cfg_t target_device_stm32l475;
+
+const board_info_t g_board_info = {
+ .board_id = "0468",
+ .family_id = kStub_HWReset_FamilyID,
+ .flags = kEnablePageErase|kEnableUnderResetConnect,
+ .target_cfg = &target_device_stm32l475,
+};
\ No newline at end of file
diff -r 000000000000 -r 01f31e923fe2 source/board/mtb_stm_s2lp.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/mtb_stm_s2lp.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file mtb_stm_s2lp.c
+ * @brief board ID for the STM S2 LP
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0467",
+ .family_id = kStub_HWReset_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/mtb_ublox_odin_w2.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/mtb_ublox_odin_w2.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,31 @@
+/**
+ * @file mtb_ublox_odin_w2.c
+ * @brief board file for UBLOX ODIN W2
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2018-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0450",
+ .family_id = kStub_HWReset_FamilyID,
+ .flags = kEnablePageErase|kEnableUnderResetConnect,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/mtb_usi_wm_bn_bm_22.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/mtb_usi_wm_bn_bm_22.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,32 @@
+/**
+ * @file mtb_usi_wm_bn_bm_22.c
+ * @brief board ID for the mtb usi
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+extern target_cfg_t target_device;
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0462",
+ .family_id = kStub_HWReset_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/mtb_wise1510.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/mtb_wise1510.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file mtb_wise1510.c
+ * @brief board ID for the MTB Wise 1510
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0458",
+ .family_id = kStub_HWReset_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/mtb_wise1530.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/mtb_wise1530.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file mtb_wise1530.c
+ * @brief board ID for the MTB Wise 1530
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0459",
+ .family_id = kStub_HWReset_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/mtb_wise1570.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/mtb_wise1570.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,31 @@
+/**
+ * @file mtb_wise1570.c
+ * @brief board ID for the MTB Wise 1570
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0460",
+ .family_id = kStub_HWReset_FamilyID,
+ .flags = kEnablePageErase|kEnableUnderResetConnect,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/mtconnect04s.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/mtconnect04s.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,33 @@
+/**
+ * @file mtconnect04s.c
+ * @brief board ID for the MtM MtConnect04S developments board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "C005",
+ .family_id = kNordic_Nrf51_FamilyID,
+ .daplink_url_name = "HELP HTM",
+ .daplink_drive_name = "MTCONNEC04S",
+ .daplink_target_url = "https://blog.mtmtech.com.tw/mtconnect04s/",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/musca_a.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/musca_a.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,95 @@
+/**
+ * @file musca_a.c
+ * @brief board ID for the ARM MUSCA A board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "stdbool.h"
+#include "virtual_fs.h"
+#include "flash_manager.h"
+#include "IO_Config.h"
+#include "target_board.h"
+#include "target_family.h"
+
+void power_on_sequence(void);
+
+uint8_t gpio_get_pbon_btn()
+{
+ return LPC_GPIO->PIN[PIN_PBON_PORT] & PIN_PBON ? 0 : 1;
+}
+
+static void prerun_board_config(void)
+{
+ /* configure MUSCA specific gpio */
+ // configure PBON as input
+ PIN_PBON_IOCON = PIN_PBON_IOCON_INIT;
+ LPC_GPIO->DIR[PIN_PBON_PORT] &= ~PIN_PBON;
+ // configure PSUON as output
+ PIN_PSUON_IOCON = PIN_PSUON_IOCON_INIT;
+ LPC_GPIO->CLR[PIN_PSUON_PORT] = PIN_PSUON;
+ LPC_GPIO->DIR[PIN_PSUON_PORT] |= PIN_PSUON;
+ // configure SHUTDOWN as input
+ PIN_SHUTDOWN_IOCON = PIN_SHUTDOWN_IOCON_INIT;
+ LPC_GPIO->DIR[PIN_SHUTDOWN_PORT] &= ~PIN_SHUTDOWN;
+ // configure CB_nRST as output
+ PIN_CB_nRST_IOCON = PIN_CB_nRST_IOCON_INIT;
+ LPC_GPIO->CLR[PIN_CB_nRST_PORT] = PIN_CB_nRST;
+ LPC_GPIO->DIR[PIN_CB_nRST_PORT] |= PIN_CB_nRST;
+ // configure CFG_nRST as output
+ PIN_CFG_nRST_IOCON = PIN_CFG_nRST_IOCON_INIT;
+ LPC_GPIO->CLR[PIN_CFG_nRST_PORT] = PIN_CFG_nRST;
+ LPC_GPIO->DIR[PIN_CFG_nRST_PORT] |= PIN_CFG_nRST;
+ // configure SCC_LOAD as output
+ PIN_SCC_LOAD_IOCON = PIN_SCC_LOAD_IOCON_INIT;
+ LPC_GPIO->CLR[PIN_SCC_LOAD_PORT] = PIN_SCC_LOAD;
+ LPC_GPIO->DIR[PIN_SCC_LOAD_PORT] |= PIN_SCC_LOAD;
+ // configure SCC_WNR as output
+ PIN_SCC_WNR_IOCON = PIN_SCC_WNR_IOCON_INIT;
+ LPC_GPIO->CLR[PIN_SCC_WNR_PORT] = PIN_SCC_WNR;
+ LPC_GPIO->DIR[PIN_SCC_WNR_PORT] |= PIN_SCC_WNR;
+ // configure SCC_DATAIN as output
+ PIN_SCC_DATAIN_IOCON = PIN_SCC_DATAIN_IOCON_INIT;
+ LPC_GPIO->CLR[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
+ LPC_GPIO->DIR[PIN_SCC_DATAIN_PORT] |= PIN_SCC_DATAIN;
+ // configure SCC_CLK as output
+ PIN_SCC_CLK_IOCON = PIN_SCC_CLK_IOCON_INIT;
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ LPC_GPIO->DIR[PIN_SCC_CLK_PORT] |= PIN_SCC_CLK;
+ // configure SCC_DATAOUT as input
+ PIN_SCC_DATAOUT_IOCON = PIN_SCC_DATAOUT_IOCON_INIT;
+ LPC_GPIO->DIR[PIN_SCC_DATAOUT_PORT] &= ~PIN_SCC_DATAOUT;
+ // configure CS_nDET as input
+ PIN_CS_nDET_IOCON = PIN_CS_nDET_IOCON_INIT;
+ LPC_GPIO->DIR[PIN_CS_nDET_PORT] &= ~PIN_CS_nDET;
+
+ PIN_USART_IOCON = PIN_USART_IOCON_INIT;
+
+ // Switch on power supply - PSUON
+ LPC_GPIO->SET[PIN_PSUON_PORT] = PIN_PSUON;
+
+ power_on_sequence();
+
+ flash_manager_set_page_erase(true);
+}
+
+const board_info_t g_board_info = {
+ .board_id = "5006",
+ .daplink_drive_name = "MBED ",
+ .target_cfg = &target_device,
+ .prerun_board_config = prerun_board_config,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/musca_b.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/musca_b.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,103 @@
+/**
+ * @file musca_b.c
+ * @brief board ID for the ARM MUSCA B board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "stdbool.h"
+#include "virtual_fs.h"
+#include "flash_manager.h"
+#include "IO_Config.h"
+#include "target_board.h"
+#include "target_family.h"
+#include "power_ctrl.h"
+
+uint8_t gpio_get_pbon_btn()
+{
+ return LPC_GPIO->PIN[PIN_PBON_PORT] & PIN_PBON ? 0 : 1;
+}
+
+static void prerun_board_config(void)
+{
+ /* configure MUSCA specific gpio */
+ // configure PBON as input
+ PIN_PBON_IOCON = PIN_PBON_IOCON_INIT;
+ LPC_GPIO->DIR[PIN_PBON_PORT] &= ~PIN_PBON;
+ // configure PWROK as output
+ PIN_PWROK_IOCON = PIN_PWROK_IOCON_INIT;
+ LPC_GPIO->CLR[PIN_PWROK_PORT] = PIN_PWROK;
+ LPC_GPIO->DIR[PIN_PWROK_PORT] |= PIN_PWROK;
+ // configure SHUTDOWN as input
+ PIN_SHUTDOWN_IOCON = PIN_SHUTDOWN_IOCON_INIT;
+ LPC_GPIO->DIR[PIN_SHUTDOWN_PORT] &= ~PIN_SHUTDOWN;
+ // configure CB_nRST as output
+ PIN_CB_nRST_IOCON = PIN_CB_nRST_IOCON_INIT;
+ LPC_GPIO->CLR[PIN_CB_nRST_PORT] = PIN_CB_nRST;
+ LPC_GPIO->DIR[PIN_CB_nRST_PORT] |= PIN_CB_nRST;
+ // configure CFG_nRST as output
+ PIN_CFG_nRST_IOCON = PIN_CFG_nRST_IOCON_INIT;
+ LPC_GPIO->CLR[PIN_CFG_nRST_PORT] = PIN_CFG_nRST;
+ LPC_GPIO->DIR[PIN_CFG_nRST_PORT] |= PIN_CFG_nRST;
+ // configure SCC_LOAD as output
+ PIN_SCC_LOAD_IOCON = PIN_SCC_LOAD_IOCON_INIT;
+ LPC_GPIO->CLR[PIN_SCC_LOAD_PORT] = PIN_SCC_LOAD;
+ LPC_GPIO->DIR[PIN_SCC_LOAD_PORT] |= PIN_SCC_LOAD;
+ // configure SCC_WNR as output
+ PIN_SCC_WNR_IOCON = PIN_SCC_WNR_IOCON_INIT;
+ LPC_GPIO->CLR[PIN_SCC_WNR_PORT] = PIN_SCC_WNR;
+ LPC_GPIO->DIR[PIN_SCC_WNR_PORT] |= PIN_SCC_WNR;
+ // configure SCC_DATAIN as output
+ PIN_SCC_DATAIN_IOCON = PIN_SCC_DATAIN_IOCON_INIT;
+ LPC_GPIO->CLR[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
+ LPC_GPIO->DIR[PIN_SCC_DATAIN_PORT] |= PIN_SCC_DATAIN;
+ // configure SCC_CLK as output
+ PIN_SCC_CLK_IOCON = PIN_SCC_CLK_IOCON_INIT;
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ LPC_GPIO->DIR[PIN_SCC_CLK_PORT] |= PIN_SCC_CLK;
+ // configure SCC_DATAOUT as input
+ PIN_SCC_DATAOUT_IOCON = PIN_SCC_DATAOUT_IOCON_INIT;
+ LPC_GPIO->DIR[PIN_SCC_DATAOUT_PORT] &= ~PIN_SCC_DATAOUT;
+ // configure CS_nDET as input
+ PIN_CS_nDET_IOCON = PIN_CS_nDET_IOCON_INIT;
+ LPC_GPIO->DIR[PIN_CS_nDET_PORT] &= ~PIN_CS_nDET;
+ // configure PIN_I2C_SCL as OC output
+ PIN_I2C_SCL_IOCON = PIN_I2C_SCL_IOCON_INIT;
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] &= ~PIN_I2C_SCL;
+ // configure PIN_I2C_SDA as OC output
+ PIN_I2C_SDA_IOCON = PIN_I2C_SDA_IOCON_INIT;
+ LPC_GPIO->DIR[PIN_I2C_SDA_PORT] &= ~PIN_I2C_SDA;
+
+ // Setup I2CIO expander
+ i2cio_init();
+
+ PIN_USART_IOCON = PIN_USART_IOCON_INIT;
+
+ // Turn ON power
+ i2cio_power_on();
+
+ power_on_sequence();
+
+ flash_manager_set_page_erase(true);
+}
+
+const board_info_t g_board_info = {
+ .board_id = "5007",
+ .daplink_drive_name = "MBED ",
+ .target_cfg = &target_device,
+ .prerun_board_config = prerun_board_config,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/ncs36510rf.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/ncs36510rf.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,32 @@
+/* CMSIS-DAP Interface Firmware
+ * Copyright (c) 2009-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "uart.h"
+#include "target_board.h"
+#include "target_family.h"
+
+static void prerun_board_config()
+{
+ uart_enable_flow_control(false);
+}
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "1200",
+ .family_id = kStub_SWSysReset_FamilyID,
+ .prerun_board_config = prerun_board_config,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/nina_b1.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/nina_b1.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,33 @@
+/**
+ * @file nina_b1.c
+ * @brief board ID for the u-blox NINA-B1 EVA maker board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+extern target_cfg_t target_device_nrf52;
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "1238",
+ .family_id = kNordic_Nrf51_FamilyID,
+ .daplink_target_url = "https://os.mbed.com/platforms/VBLUNO51/",
+ .target_cfg = &target_device_nrf52,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/numaker_iot_m263a.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/numaker_iot_m263a.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,31 @@
+/**
+ * @file numaker_iot_m263a.c
+ * @brief board ID for the NuMaker-IoT-M263A board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "1310",
+ .family_id = kStub_SWSysReset_FamilyID,
+ .flags = kEnablePageErase,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/numaker_m252kg.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/numaker_m252kg.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,31 @@
+/**
+ * @file numaker_m252kg.c
+ * @brief board ID for the NuMaker-M252KG board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "1309",
+ .family_id = kStub_SWSysReset_FamilyID,
+ .flags = kEnablePageErase,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/nz32_sc151.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/nz32_sc151.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,34 @@
+/**
+ * @file nz32_sc151.c
+ * @brief board ID for the Modtronix NZ32-SC151
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "6660",
+ .family_id = kStub_HWReset_FamilyID,
+ .daplink_url_name = "NZ32-SC151 ",
+ .daplink_drive_name = "NZ32-SC151 ",
+ .daplink_target_url = "http://www.modtronix/nz32-sc151",
+ .target_cfg = &target_device,
+};
+
diff -r 000000000000 -r 01f31e923fe2 source/board/override_96b_nitrogen/IO_Config_Override.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/board/override_96b_nitrogen/IO_Config_Override.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,108 @@ +/** + * @file IO_Config_Override.c + * @brief Alternative IO for LPC11U35 based Hardware Interface Circuit + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ + +#include "LPC11Uxx.h" +#include "daplink.h" + +// This GPIO configuration is only valid for the LPC11U35 HIC +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC11U35); + +// Peripheral register bit masks (used for pin inits) +#define FUNC_0 0 +#define FUNC_1 1 +#define PULL_DOWN_ENABLED (1 << 3) +#define PULL_UP_ENABLED (2 << 3) +#define OPENDRAIN (1 << 10) + +// DAP LED PIO0_21 +#define PIN_DAP_LED_PORT 0 +#define PIN_DAP_LED_BIT 21 +#define PIN_DAP_LED (1 << PIN_DAP_LED_BIT) +#define PIN_DAP_LED_IOCON LPC_IOCON->PIO0_21 +#define PIN_DAP_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// MSD LED PIO0_20 +#define PIN_MSD_LED_PORT 0 +#define PIN_MSD_LED_BIT 20 +#define PIN_MSD_LED (1 << PIN_MSD_LED_BIT) +#define PIN_MSD_LED_IOCON LPC_IOCON->PIO0_20 +#define PIN_MSD_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// CDC LED PIO0_11 +#define PIN_CDC_LED_PORT 0 +#define PIN_CDC_LED_BIT 11 +#define PIN_CDC_LED (1 << PIN_CDC_LED_BIT) +#define PIN_CDC_LED_IOCON LPC_IOCON->TDI_PIO0_11 +#define PIN_CDC_LED_IOCON_INIT (FUNC_1 | PULL_UP_ENABLED) + +// Non-Forwarded Reset in PIN PIO1_19 (Nitrogen override) +#define PIN_RESET_IN_PORT 1 +#define PIN_RESET_IN_BIT 19 +#define PIN_RESET_IN (1 << PIN_RESET_IN_BIT) +#define PIN_RESET_IN_IOCON LPC_IOCON->PIO1_19 +#define PIN_RESET_IN_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// Forwarded Reset in PIN PIO0_1 +#define PIN_RESET_IN_FWRD_PORT 0 +#define PIN_RESET_IN_FWRD_BIT 1 +#define PIN_RESET_IN_FWRD (1 << PIN_RESET_IN_FWRD_BIT) +#define PIN_RESET_IN_FWRD_IOCON LPC_IOCON->PIO0_1 +#define PIN_RESET_IN_FWRD_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// nRESET OUT Pin PIO0_2 +#define PIN_nRESET_PORT 0 +#define PIN_nRESET_BIT 2 +#define PIN_nRESET (1 << PIN_nRESET_BIT) +#define PIN_nRESET_IOCON LPC_IOCON->PIO0_2 +#define PIN_nRESET_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// SWCLK/TCK Pin PIO0_9 (Nitrogen override) +#define PIN_SWCLK_PORT 0 +#define PIN_SWCLK_BIT 9 +#define PIN_SWCLK (1 << PIN_SWCLK_BIT) +#define PIN_SWCLK_TCK_IOCON LPC_IOCON->PIO0_9 +#define PIN_SWCLK_TCK_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// SWDIO/TMS In/Out Pin PIO0_8 +#define PIN_SWDIO_PORT 0 +#define PIN_SWDIO_BIT 8 +#define PIN_SWDIO (1 << PIN_SWDIO_BIT) +#define PIN_SWDIO_TMS_IOCON LPC_IOCON->PIO0_8 +#define PIN_SWDIO_TMS_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// TDI Pin PIO0_17 +#define PIN_TDI_PORT 17 +#define PIN_TDI_BIT 17 +#define PIN_TDI (1 << PIN_TDI_BIT) +#define PIN_TDI_IOCON LPC_IOCON->PIO0_17 +#define PIN_TDI_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// SWO/TDO Pin PIO0_9 +#define PIN_TDO_PORT 9 +#define PIN_TDO_BIT 9 +#define PIN_TDO (1 << PIN_TDO_BIT) +#define PIN_TDO_IOCON LPC_IOCON->PIO0_9 +#define PIN_TDO_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/board/override_blueninja/IO_Config_Override.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/board/override_blueninja/IO_Config_Override.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,129 @@ +/** + * @file IO_Config_Override.c + * @brief Alternative IO for LPC11U35 based Hardware Interface Circuit + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ + +#include "LPC11Uxx.h" +#include "daplink.h" + +#define TARGET_POWER_HOLD +#define CONTROLLED_POWER_LED +#define INTEGRATED_STATUS_LED + +// nRESET is FET drive. +#define PIN_nRESET_FET_DRIVE + +// This GPIO configuration is only valid for the LPC11U35 HIC +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC11U35); + +// Peripheral register bit masks (used for pin inits) +#define FUNC_0 0 +#define FUNC_1 1 +#define PULL_DOWN_ENABLED (1 << 3) +#define PULL_UP_ENABLED (2 << 3) +#define OPENDRAIN (1 << 10) + +// POW LED +#define PIN_POW_LED_PORT 0 +#define PIN_POW_LED_BIT 15 +#define PIN_POW_LED (1 << PIN_POW_LED_BIT) +#define PIN_POW_LED_IOCON LPC_IOCON->SWDIO_PIO0_15 +#define PIN_POW_LED_IOCON_INIT (FUNC_1 | OPENDRAIN | PULL_UP_ENABLED) + +// DAP LED PIO0_16 +#define PIN_DAP_LED_PORT 0 +#define PIN_DAP_LED_BIT 16 +#define PIN_DAP_LED (1 << PIN_DAP_LED_BIT) +#define PIN_DAP_LED_IOCON LPC_IOCON->PIO0_16 +#define PIN_DAP_LED_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// MSD LED PIO0_16 +#define PIN_MSD_LED_PORT 0 +#define PIN_MSD_LED_BIT 16 +#define PIN_MSD_LED (1 << PIN_MSD_LED_BIT) +#define PIN_MSD_LED_IOCON LPC_IOCON->PIO0_16 +#define PIN_MSD_LED_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// CDC LED PIO0_16 +#define PIN_CDC_LED_PORT 0 +#define PIN_CDC_LED_BIT 16 +#define PIN_CDC_LED (1 << PIN_CDC_LED_BIT) +#define PIN_CDC_LED_IOCON LPC_IOCON->PIO0_16 +#define PIN_CDC_LED_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// Non-Forwarded Reset in PIN PIO1_19 +#define PIN_RESET_IN_PORT 1 +#define PIN_RESET_IN_BIT 19 +#define PIN_RESET_IN (1 << PIN_RESET_IN_BIT) +#define PIN_RESET_IN_IOCON LPC_IOCON->PIO1_19 +#define PIN_RESET_IN_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// Forwarded Reset in PIN PIO0_1 +#define PIN_RESET_IN_FWRD_PORT 0 +#define PIN_RESET_IN_FWRD_BIT 1 +#define PIN_RESET_IN_FWRD (1 << PIN_RESET_IN_FWRD_BIT) +#define PIN_RESET_IN_FWRD_IOCON LPC_IOCON->PIO0_1 +#define PIN_RESET_IN_FWRD_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// nRESET OUT Pin PIO0_2 +#define PIN_nRESET_PORT 0 +#define PIN_nRESET_BIT 2 +#define PIN_nRESET (1 << PIN_nRESET_BIT) +#define PIN_nRESET_IOCON LPC_IOCON->PIO0_2 +#define PIN_nRESET_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// SWCLK/TCK Pin PIO0_7 +#define PIN_SWCLK_PORT 0 +#define PIN_SWCLK_BIT 7 +#define PIN_SWCLK (1 << PIN_SWCLK_BIT) +#define PIN_SWCLK_TCK_IOCON LPC_IOCON->PIO0_7 +#define PIN_SWCLK_TCK_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// SWDIO/TMS In/Out Pin PIO0_8 +#define PIN_SWDIO_PORT 0 +#define PIN_SWDIO_BIT 8 +#define PIN_SWDIO (1 << PIN_SWDIO_BIT) +#define PIN_SWDIO_TMS_IOCON LPC_IOCON->PIO0_8 +#define PIN_SWDIO_TMS_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// TDI Pin PIO0_22 +#define PIN_TDI_PORT 0 +#define PIN_TDI_BIT 22 +#define PIN_TDI (1 << PIN_TDI_BIT) +#define PIN_TDI_IOCON LPC_IOCON->PIO0_22 +#define PIN_TDI_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// SWO/TDO Pin PIO0_9 +#define PIN_TDO_PORT 0 +#define PIN_TDO_BIT 9 +#define PIN_TDO (1 << PIN_TDO_BIT) +#define PIN_TDO_IOCON LPC_IOCON->PIO0_9 +#define PIN_TDO_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// PowerSW HOLD Pin PIO0_13 +#define PIN_PWH_PORT 0 +#define PIN_PWH_BIT 13 +#define PIN_PWH (1 << PIN_PWH_BIT) +#define PIN_PWH_IOCON LPC_IOCON->TDO_PIO0_13 +#define PIN_PWH_IOCON_INIT (FUNC_1) + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/board/override_lpc11u35_6LoWPAN_BorderRouter/IO_Config_Override.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/board/override_lpc11u35_6LoWPAN_BorderRouter/IO_Config_Override.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,108 @@ +/** + * @file IO_Config_Override.c + * @brief Alternative IO for LPC11U35 based Hardware Interface Circuit for all 6LoWPAN_BorderRouter, Moved SWCLK + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ + +#include "LPC11Uxx.h" +#include "daplink.h" + +// This GPIO configuration is only valid for the LPC11U35 HIC +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC11U35); + +// Peripheral register bit masks (used for pin inits) +#define FUNC_0 0 +#define FUNC_1 1 +#define PULL_DOWN_ENABLED (1 << 3) +#define PULL_UP_ENABLED (2 << 3) +#define OPENDRAIN (1 << 10) + +// DAP LED PIO0_21 +#define PIN_DAP_LED_PORT 0 +#define PIN_DAP_LED_BIT 21 +#define PIN_DAP_LED (1 << PIN_DAP_LED_BIT) +#define PIN_DAP_LED_IOCON LPC_IOCON->PIO0_21 +#define PIN_DAP_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// MSD LED PIO0_20 +#define PIN_MSD_LED_PORT 0 +#define PIN_MSD_LED_BIT 20 +#define PIN_MSD_LED (1 << PIN_MSD_LED_BIT) +#define PIN_MSD_LED_IOCON LPC_IOCON->PIO0_20 +#define PIN_MSD_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// CDC LED PIO0_11 +#define PIN_CDC_LED_PORT 0 +#define PIN_CDC_LED_BIT 11 +#define PIN_CDC_LED (1 << PIN_CDC_LED_BIT) +#define PIN_CDC_LED_IOCON LPC_IOCON->TDI_PIO0_11 +#define PIN_CDC_LED_IOCON_INIT (FUNC_1 | PULL_UP_ENABLED) + +// Non-Forwarded Reset in PIN PIO1_19 +#define PIN_RESET_IN_PORT 1 +#define PIN_RESET_IN_BIT 19 +#define PIN_RESET_IN (1 << PIN_RESET_IN_BIT) +#define PIN_RESET_IN_IOCON LPC_IOCON->PIO1_19 +#define PIN_RESET_IN_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// Forwarded Reset in PIN PIO0_1 +#define PIN_RESET_IN_FWRD_PORT 0 +#define PIN_RESET_IN_FWRD_BIT 1 +#define PIN_RESET_IN_FWRD (1 << PIN_RESET_IN_FWRD_BIT) +#define PIN_RESET_IN_FWRD_IOCON LPC_IOCON->PIO0_1 +#define PIN_RESET_IN_FWRD_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// nRESET OUT Pin PIO0_2 +#define PIN_nRESET_PORT 0 +#define PIN_nRESET_BIT 2 +#define PIN_nRESET (1 << PIN_nRESET_BIT) +#define PIN_nRESET_IOCON LPC_IOCON->PIO0_2 +#define PIN_nRESET_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// SWCLK/TCK Pin PIO0_9 +#define PIN_SWCLK_PORT 0 +#define PIN_SWCLK_BIT 9 +#define PIN_SWCLK (1 << PIN_SWCLK_BIT) +#define PIN_SWCLK_TCK_IOCON LPC_IOCON->PIO0_9 +#define PIN_SWCLK_TCK_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// SWDIO/TMS In/Out Pin PIO0_8 +#define PIN_SWDIO_PORT 0 +#define PIN_SWDIO_BIT 8 +#define PIN_SWDIO (1 << PIN_SWDIO_BIT) +#define PIN_SWDIO_TMS_IOCON LPC_IOCON->PIO0_8 +#define PIN_SWDIO_TMS_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// TDI Pin PIO0_17 +#define PIN_TDI_PORT 17 +#define PIN_TDI_BIT 17 +#define PIN_TDI (1 << PIN_TDI_BIT) +#define PIN_TDI_IOCON LPC_IOCON->PIO0_17 +#define PIN_TDI_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// SWO/TDO Pin PIO0_010 +#define PIN_TDO_PORT 0 +#define PIN_TDO_BIT 10 +#define PIN_TDO (1 << PIN_TDO_BIT) +#define PIN_TDO_IOCON LPC_IOCON->PIO0_010 +#define PIN_TDO_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/board/override_lpc11u35_reset/IO_Config_Override.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/board/override_lpc11u35_reset/IO_Config_Override.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,108 @@ +/** + * @file IO_Config_Override.c + * @brief Alternative IO for LPC11U35 based Hardware Interface Circuit + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ + +#include "LPC11Uxx.h" +#include "daplink.h" + +// This GPIO configuration is only valid for the LPC11U35 HIC +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC11U35); + +// Peripheral register bit masks (used for pin inits) +#define FUNC_0 0 +#define FUNC_1 1 +#define PULL_DOWN_ENABLED (1 << 3) +#define PULL_UP_ENABLED (2 << 3) +#define OPENDRAIN (1 << 10) + +// DAP LED PIO0_21 +#define PIN_DAP_LED_PORT 0 +#define PIN_DAP_LED_BIT 21 +#define PIN_DAP_LED (1 << PIN_DAP_LED_BIT) +#define PIN_DAP_LED_IOCON LPC_IOCON->PIO0_21 +#define PIN_DAP_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// MSD LED PIO0_20 +#define PIN_MSD_LED_PORT 0 +#define PIN_MSD_LED_BIT 20 +#define PIN_MSD_LED (1 << PIN_MSD_LED_BIT) +#define PIN_MSD_LED_IOCON LPC_IOCON->PIO0_20 +#define PIN_MSD_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// CDC LED PIO0_11 +#define PIN_CDC_LED_PORT 0 +#define PIN_CDC_LED_BIT 11 +#define PIN_CDC_LED (1 << PIN_CDC_LED_BIT) +#define PIN_CDC_LED_IOCON LPC_IOCON->TDI_PIO0_11 +#define PIN_CDC_LED_IOCON_INIT (FUNC_1 | PULL_UP_ENABLED) + +// Non-Forwarded Reset in PIN PIO1_19 +#define PIN_RESET_IN_PORT 1 +#define PIN_RESET_IN_BIT 19 +#define PIN_RESET_IN (1 << PIN_RESET_IN_BIT) +#define PIN_RESET_IN_IOCON LPC_IOCON->PIO1_19 +#define PIN_RESET_IN_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// Forwarded Reset in PIN PIO0_1 +#define PIN_RESET_IN_FWRD_PORT 0 +#define PIN_RESET_IN_FWRD_BIT 1 +#define PIN_RESET_IN_FWRD (1 << PIN_RESET_IN_FWRD_BIT) +#define PIN_RESET_IN_FWRD_IOCON LPC_IOCON->PIO0_1 +#define PIN_RESET_IN_FWRD_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// nRESET OUT Pin PIO0_2 +#define PIN_nRESET_PORT 0 +#define PIN_nRESET_BIT 2 +#define PIN_nRESET (1 << PIN_nRESET_BIT) +#define PIN_nRESET_IOCON LPC_IOCON->PIO0_2 +#define PIN_nRESET_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// SWCLK/TCK Pin PIO0_7 +#define PIN_SWCLK_PORT 0 +#define PIN_SWCLK_BIT 7 +#define PIN_SWCLK (1 << PIN_SWCLK_BIT) +#define PIN_SWCLK_TCK_IOCON LPC_IOCON->PIO0_7 +#define PIN_SWCLK_TCK_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// SWDIO/TMS In/Out Pin PIO0_8 +#define PIN_SWDIO_PORT 0 +#define PIN_SWDIO_BIT 8 +#define PIN_SWDIO (1 << PIN_SWDIO_BIT) +#define PIN_SWDIO_TMS_IOCON LPC_IOCON->PIO0_8 +#define PIN_SWDIO_TMS_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// TDI Pin PIO0_17 +#define PIN_TDI_PORT 17 +#define PIN_TDI_BIT 17 +#define PIN_TDI (1 << PIN_TDI_BIT) +#define PIN_TDI_IOCON LPC_IOCON->PIO0_17 +#define PIN_TDI_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// SWO/TDO Pin PIO0_9 +#define PIN_TDO_PORT 9 +#define PIN_TDO_BIT 9 +#define PIN_TDO (1 << PIN_TDO_BIT) +#define PIN_TDO_IOCON LPC_IOCON->PIO0_9 +#define PIN_TDO_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/board/override_mkit_dk_dongle_nrf5x/IO_Config_Override.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/board/override_mkit_dk_dongle_nrf5x/IO_Config_Override.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,43 @@ +/** + * @file IO_Config_Override.c + * @brief Alternative IO for LPC11U35 based Hardware Interface Circuit + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __IO_CONFIG_OVERRIDE_H__ +#define __IO_CONFIG_OVERRIDE_H__ + +// This GPIO configuration is only valid for the SAM3U2C HIC +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_SAM3U2C); + +// DAP LED +#define PIN_DAP_LED_PORT PIOA +#define PIN_DAP_LED_BIT 29 +#define PIN_DAP_LED (1UL << PIN_DAP_LED_BIT) + +// MSD LED +#define PIN_MSD_LED_PORT PIOA +#define PIN_MSD_LED_BIT 29 +#define PIN_MSD_LED (1UL << PIN_MSD_LED_BIT) + +// CDC LED +#define PIN_CDC_LED_PORT PIOA +#define PIN_CDC_LED_BIT 29 +#define PIN_CDC_LED (1UL << PIN_CDC_LED_BIT) + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/board/override_mkl26z_reset/IO_Config_Override.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/board/override_mkl26z_reset/IO_Config_Override.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,115 @@ +/** + * @file IO_Config.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +// Override all defines if IO_CONFIG_OVERRIDE is defined + +#ifndef __IO_CONFIG_OVERRIDE_H__ +#define __IO_CONFIG_OVERRIDE_H__ + +#include "MKL26Z4.h" +#include "compiler.h" +#include "daplink.h" + +// This GPIO configuration is only valid for the KL26 HIC +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_KL26); + + +// Debug Port I/O Pins + +// SWCLK Pin PTC5(C5) +#define PIN_SWCLK_PORT PORTC +#define PIN_SWCLK_GPIO PTC +#define PIN_SWCLK_BIT (5) +#define PIN_SWCLK (1<<PIN_SWCLK_BIT) + +// SWDIO Pin PTC6(C6) +#define PIN_SWDIO_PORT PORTC +#define PIN_SWDIO_GPIO PTC +#define PIN_SWDIO_BIT (6) +#define PIN_SWDIO (1<<PIN_SWDIO_BIT) + +// nRESET Pin PTC8(C8) +#define PIN_nRESET_PORT PORTC +#define PIN_nRESET_GPIO PTC +#define PIN_nRESET_BIT (1/*8 DUE TO SMALLER PACKAGE*/) +#define PIN_nRESET (1<<PIN_nRESET_BIT) + +// PWR_REG_EN PTD2 - Not connected +#define PIN_POWER_EN_PORT PORTD +#define PIN_POWER_EN_GPIO PTD +#define PIN_POWER_EN_BIT (2) +#define PIN_POWER_EN (1<<PIN_POWER_EN_BIT) + +// VTRG_FAULT_B PTD3 - Not connected +#define PIN_VTRG_FAULT_B_PORT PORTD +#define PIN_VTRG_FAULT_B_GPIO PTD +#define PIN_VTRG_FAULT_B_BIT (7) +#define PIN_VTRG_FAULT_B_EN (1<<PIN_VTRG_FAULT_B_BIT) + +// Debug Unit LEDs + +// HID_LED PTD4 +#define PIN_HID_LED_PORT PORTD +#define PIN_HID_LED_GPIO PTD +#define PIN_HID_LED_BIT (4) +#define PIN_HID_LED (1<<PIN_HID_LED_BIT) + +// MSC_LED PTD5 +#define PIN_MSC_LED_PORT PORTD +#define PIN_MSC_LED_GPIO PTD +#define PIN_MSC_LED_BIT (4) +#define PIN_MSC_LED (1<<PIN_MSC_LED_BIT) + +// CDC_LED PTD6 +#define PIN_CDC_LED_PORT PORTD +#define PIN_CDC_LED_GPIO PTD +#define PIN_CDC_LED_BIT (4) +#define PIN_CDC_LED (1<<PIN_CDC_LED_BIT) + +// SW RESET BUTTON PTB1 +#define PIN_SW_RESET_PORT PORTB +#define PIN_SW_RESET_GPIO PTB +#define PIN_SW_RESET_BIT (1) +#define PIN_SW_RESET (1<<PIN_SW_RESET_BIT) + +// Connected LED Not available + +// Target Running LED Not available + +// UART +#define UART_PORT PORTC +#define UART_NUM (1) +// RX PTC3 +#define PIN_UART_RX_GPIO PTC +#define PIN_UART_RX_BIT (3) +#define PIN_UART_RX (1<<PIN_UART_RX_BIT) +#define PIN_UART_RX_MUX_ALT (3) +// TX PTC4 +#define PIN_UART_TX_GPIO PTC +#define PIN_UART_TX_BIT (4) +#define PIN_UART_TX (1<<PIN_UART_TX_BIT) +#define PIN_UART_TX_MUX_ALT (3) + +#define UART UART1 +#define UART_RX_TX_IRQn UART1_IRQn +#define UART_RX_TX_IRQHandler UART1_IRQHandler + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/board/override_mtb/IO_Config_Override.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/board/override_mtb/IO_Config_Override.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,108 @@ +/** + * @file IO_Config_Override.c + * @brief Alternative IO for LPC11U35 based Hardware Interface Circuit for all 6LoWPAN_BorderRouter, Moved SWCLK + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ + +#include "LPC11Uxx.h" +#include "daplink.h" + +// This GPIO configuration is only valid for the LPC11U35 HIC +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC11U35); + +// Peripheral register bit masks (used for pin inits) +#define FUNC_0 0 +#define FUNC_1 1 +#define PULL_DOWN_ENABLED (1 << 3) +#define PULL_UP_ENABLED (2 << 3) +#define OPENDRAIN (1 << 10) + +// DAP LED PIO0_21 +#define PIN_DAP_LED_PORT 0 +#define PIN_DAP_LED_BIT 21 +#define PIN_DAP_LED (1 << PIN_DAP_LED_BIT) +#define PIN_DAP_LED_IOCON LPC_IOCON->PIO0_21 +#define PIN_DAP_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// MSD LED PIO0_20 +#define PIN_MSD_LED_PORT 0 +#define PIN_MSD_LED_BIT 20 +#define PIN_MSD_LED (1 << PIN_MSD_LED_BIT) +#define PIN_MSD_LED_IOCON LPC_IOCON->PIO0_20 +#define PIN_MSD_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// CDC LED PIO0_11 +#define PIN_CDC_LED_PORT 0 +#define PIN_CDC_LED_BIT 11 +#define PIN_CDC_LED (1 << PIN_CDC_LED_BIT) +#define PIN_CDC_LED_IOCON LPC_IOCON->TDI_PIO0_11 +#define PIN_CDC_LED_IOCON_INIT (FUNC_1 | PULL_UP_ENABLED) + +// Non-Forwarded Reset in PIN PIO1_19 +#define PIN_RESET_IN_PORT 1 +#define PIN_RESET_IN_BIT 19 +#define PIN_RESET_IN (1 << PIN_RESET_IN_BIT) +#define PIN_RESET_IN_IOCON LPC_IOCON->PIO1_19 +#define PIN_RESET_IN_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// Forwarded Reset in PIN PIO0_1 +#define PIN_RESET_IN_FWRD_PORT 0 +#define PIN_RESET_IN_FWRD_BIT 1 +#define PIN_RESET_IN_FWRD (1 << PIN_RESET_IN_FWRD_BIT) +#define PIN_RESET_IN_FWRD_IOCON LPC_IOCON->PIO0_1 +#define PIN_RESET_IN_FWRD_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// nRESET OUT Pin PIO0_2 +#define PIN_nRESET_PORT 0 +#define PIN_nRESET_BIT 2 +#define PIN_nRESET (1 << PIN_nRESET_BIT) +#define PIN_nRESET_IOCON LPC_IOCON->PIO0_2 +#define PIN_nRESET_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// SWCLK/TCK Pin PIO0_9 +#define PIN_SWCLK_PORT 0 +#define PIN_SWCLK_BIT 9 +#define PIN_SWCLK (1 << PIN_SWCLK_BIT) +#define PIN_SWCLK_TCK_IOCON LPC_IOCON->PIO0_9 +#define PIN_SWCLK_TCK_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// SWDIO/TMS In/Out Pin PIO0_8 +#define PIN_SWDIO_PORT 0 +#define PIN_SWDIO_BIT 8 +#define PIN_SWDIO (1 << PIN_SWDIO_BIT) +#define PIN_SWDIO_TMS_IOCON LPC_IOCON->PIO0_8 +#define PIN_SWDIO_TMS_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// TDI Pin PIO0_17 +#define PIN_TDI_PORT 17 +#define PIN_TDI_BIT 17 +#define PIN_TDI (1 << PIN_TDI_BIT) +#define PIN_TDI_IOCON LPC_IOCON->PIO0_17 +#define PIN_TDI_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// SWO/TDO Pin PIO0_010 +#define PIN_TDO_PORT 0 +#define PIN_TDO_BIT 10 +#define PIN_TDO (1 << PIN_TDO_BIT) +#define PIN_TDO_IOCON LPC_IOCON->PIO0_010 +#define PIN_TDO_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/board/override_musca_a/IO_Config_Override.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/board/override_musca_a/IO_Config_Override.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,201 @@ +/** + * @file IO_Config_Override.h + * @brief Alternative IO for LPC11U35 based Hardware Interface Circuit + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ + +#include "LPC11Uxx.h" +#include "daplink.h" + +// This GPIO configuration is only valid for the LPC11U35 HIC +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC11U35); + +// Enable Musca A specific code +#define MUSCA_A_BOARD 1 + +// Musca A board has PBON button +#define PBON_BUTTON 1 + +// Peripheral register bit masks (used for pin inits) +#define FUNC_0 0 // Primary function +#define FUNC_1 1 // Secondary function +#define PULL_DOWN_ENABLED (1 << 3) +#define PULL_UP_ENABLED (2 << 3) +#define OPENDRAIN (1 << 10) +#define DIGITAL_IN (1 << 7) + +// DAP LED PIO0_21 +#define PIN_DAP_LED_PORT 0 +#define PIN_DAP_LED_BIT 21 +#define PIN_DAP_LED (1 << PIN_DAP_LED_BIT) +#define PIN_DAP_LED_IOCON LPC_IOCON->PIO0_21 +#define PIN_DAP_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// MSD LED PIO0_20 +#define PIN_MSD_LED_PORT 0 +#define PIN_MSD_LED_BIT 20 +#define PIN_MSD_LED (1 << PIN_MSD_LED_BIT) +#define PIN_MSD_LED_IOCON LPC_IOCON->PIO0_20 +#define PIN_MSD_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// CDC LED PIO0_11 +#define PIN_CDC_LED_PORT 0 +#define PIN_CDC_LED_BIT 11 +#define PIN_CDC_LED (1 << PIN_CDC_LED_BIT) +#define PIN_CDC_LED_IOCON LPC_IOCON->TDI_PIO0_11 +#define PIN_CDC_LED_IOCON_INIT (FUNC_1 | PULL_UP_ENABLED) + +// CM_nISP / Non-Forwarded Reset in PIN PIO0_1 +#define PIN_RESET_IN_PORT 0 +#define PIN_RESET_IN_BIT 1 +#define PIN_RESET_IN (1 << PIN_RESET_IN_BIT) +#define PIN_RESET_IN_IOCON LPC_IOCON->PIO0_1 +#define PIN_RESET_IN_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// Forwarded Reset in PIN PIO1_19 +#define PIN_RESET_IN_FWRD_PORT 0 //1 +#define PIN_RESET_IN_FWRD_BIT 1 //19 +#define PIN_RESET_IN_FWRD (1 << PIN_RESET_IN_FWRD_BIT) +#define PIN_RESET_IN_FWRD_IOCON LPC_IOCON->PIO0_1 //1_19 +#define PIN_RESET_IN_FWRD_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// CS_nSRST / nRESET OUT Pin PIO0_2 +#define PIN_nRESET_PORT 0 +#define PIN_nRESET_BIT 2 +#define PIN_nRESET (1 << PIN_nRESET_BIT) +#define PIN_nRESET_IOCON LPC_IOCON->PIO0_2 +#define PIN_nRESET_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// SWCLK PIO0_7 +#define PIN_SWCLK_PORT 0 +#define PIN_SWCLK_BIT 7 +#define PIN_SWCLK (1 << PIN_SWCLK_BIT) +#define PIN_SWCLK_TCK_IOCON LPC_IOCON->PIO0_7 +#define PIN_SWCLK_TCK_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// SWDIO In/Out Pin PIO0_8 +#define PIN_SWDIO_PORT 0 +#define PIN_SWDIO_BIT 8 +#define PIN_SWDIO (1 << PIN_SWDIO_BIT) +#define PIN_SWDIO_TMS_IOCON LPC_IOCON->PIO0_8 +#define PIN_SWDIO_TMS_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// Reset and Power control pins +// PBON PIO0_16 +#define PIN_PBON_PORT 0 +#define PIN_PBON_BIT 16 +#define PIN_PBON (1 << PIN_PBON_BIT) +#define PIN_PBON_IOCON LPC_IOCON->PIO0_16 +#define PIN_PBON_IOCON_INIT (FUNC_0 | DIGITAL_IN) + +// PSUON Pin PIO0_17 +#define PIN_PSUON_PORT 0 +#define PIN_PSUON_BIT 17 +#define PIN_PSUON (1 << PIN_PSUON_BIT) +#define PIN_PSUON_IOCON LPC_IOCON->PIO0_17 +#define PIN_PSUON_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// SHUTDOWN PIO0_15 +#define PIN_SHUTDOWN_PORT 0 +#define PIN_SHUTDOWN_BIT 15 +#define PIN_SHUTDOWN (1 << PIN_SHUTDOWN_BIT) +#define PIN_SHUTDOWN_IOCON LPC_IOCON->SWDIO_PIO0_15 +#define PIN_SHUTDOWN_IOCON_INIT (FUNC_1 | DIGITAL_IN | PULL_UP_ENABLED) + +// CB_nRST OUT Pin PIO0_4 +#define PIN_CB_nRST_PORT 0 +#define PIN_CB_nRST_BIT 4 +#define PIN_CB_nRST (1 << PIN_CB_nRST_BIT) +#define PIN_CB_nRST_IOCON LPC_IOCON->PIO0_4 +#define PIN_CB_nRST_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// CFG_nRST OUT Pin PIO0_5 +#define PIN_CFG_nRST_PORT 0 +#define PIN_CFG_nRST_BIT 5 +#define PIN_CFG_nRST (1 << PIN_CFG_nRST_BIT) +#define PIN_CFG_nRST_IOCON LPC_IOCON->PIO0_5 +#define PIN_CFG_nRST_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// CS_nDET detect for external debug to SoC +#define PIN_CS_nDET_PORT 1 +#define PIN_CS_nDET_BIT 15 +#define PIN_CS_nDET (1 << PIN_CS_nDET_BIT) +#define PIN_CS_nDET_IOCON LPC_IOCON->PIO1_15 +#define PIN_CS_nDET_IOCON_INIT (FUNC_0 | DIGITAL_IN | PULL_UP_ENABLED) + +// SCC Configuration Pins +// SCC_LOAD PIO0_9 +#define PIN_SCC_LOAD_PORT 0 +#define PIN_SCC_LOAD_BIT 9 +#define PIN_SCC_LOAD (1 << PIN_SCC_LOAD_BIT) +#define PIN_SCC_LOAD_IOCON LPC_IOCON->PIO0_9 +#define PIN_SCC_LOAD_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// SCC_WNR PIO0_10 +#define PIN_SCC_WNR_PORT 0 +#define PIN_SCC_WNR_BIT 10 +#define PIN_SCC_WNR (1 << PIN_SCC_WNR_BIT) +#define PIN_SCC_WNR_IOCON LPC_IOCON->SWCLK_PIO0_10 +#define PIN_SCC_WNR_IOCON_INIT (FUNC_1 | PULL_UP_ENABLED) + +// SCC_DATAIN PIO0_12 +#define PIN_SCC_DATAIN_PORT 0 +#define PIN_SCC_DATAIN_BIT 12 +#define PIN_SCC_DATAIN (1 << PIN_SCC_DATAIN_BIT) +#define PIN_SCC_DATAIN_IOCON LPC_IOCON->TMS_PIO0_12 +#define PIN_SCC_DATAIN_IOCON_INIT (FUNC_1 | PULL_UP_ENABLED) + +// SCC_CLK PIO0_13 +#define PIN_SCC_CLK_PORT 0 +#define PIN_SCC_CLK_BIT 13 +#define PIN_SCC_CLK (1 << PIN_SCC_CLK_BIT) +#define PIN_SCC_CLK_IOCON LPC_IOCON->TDO_PIO0_13 +#define PIN_SCC_CLK_IOCON_INIT (FUNC_1 | PULL_UP_ENABLED) + +// SCC_DATAOUT PIO0_14 +#define PIN_SCC_DATAOUT_PORT 0 +#define PIN_SCC_DATAOUT_BIT 14 +#define PIN_SCC_DATAOUT (1 << PIN_SCC_DATAOUT_BIT) +#define PIN_SCC_DATAOUT_IOCON LPC_IOCON->TRST_PIO0_14 +#define PIN_SCC_DATAOUT_IOCON_INIT (FUNC_1 | DIGITAL_IN | PULL_UP_ENABLED) + +// I2C_SCL PIO0_22 +#define PIN_I2C_SCL_PORT 0 +#define PIN_I2C_SCL_BIT 22 +#define PIN_I2C_SCL (1 << PIN_I2C_SCL_BIT) +#define PIN_I2C_SCL_IOCON LPC_IOCON->PIO0_22 +#define PIN_I2C_SCL_IOCON_INIT (FUNC_0 PULL_UP_ENABLED) + +// I2C_SDA PIO0_23 +#define PIN_I2C_SDA_PORT 0 +#define PIN_I2C_SDA_BIT 23 +#define PIN_I2C_SDA (1 << PIN_I2C_SDA_BIT) +#define PIN_I2C_SDA_IOCON LPC_IOCON->PIO0_23 +#define PIN_I2C_SDA_IOCON_INIT (FUNC_0 PULL_UP_ENABLED) + +// USART PIO0_18 +#define PIN_USART_PORT 0 +#define PIN_USART_BIT 18 +#define PIN_USART (1 << PIN_USART_BIT) +#define PIN_USART_IOCON LPC_IOCON->PIO0_18 +#define PIN_USART_IOCON_INIT (FUNC_1 | PULL_DOWN_ENABLED) + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/board/override_musca_b/IO_Config_Override.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/board/override_musca_b/IO_Config_Override.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,201 @@ +/** + * @file IO_Config_Override.h + * @brief Alternative IO for LPC11U35 based Hardware Interface Circuit + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ + +#include "LPC11Uxx.h" +#include "daplink.h" + +// This GPIO configuration is only valid for the LPC11U35 HIC +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC11U35); + +// Enable Musca B specific code +#define MUSCA_B_BOARD 1 + +// Musca B board has PBON button +#define PBON_BUTTON 1 + +// Peripheral register bit masks (used for pin inits) +#define FUNC_0 0 // Primary function +#define FUNC_1 1 // Secondary function +#define PULL_DOWN_ENABLED (1 << 3) +#define PULL_UP_ENABLED (2 << 3) +#define OPENDRAIN (1 << 10) +#define DIGITAL_IN (1 << 7) + +// DAP LED PIO0_21 +#define PIN_DAP_LED_PORT 0 +#define PIN_DAP_LED_BIT 21 +#define PIN_DAP_LED (1 << PIN_DAP_LED_BIT) +#define PIN_DAP_LED_IOCON LPC_IOCON->PIO0_21 +#define PIN_DAP_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// MSD LED PIO0_20 +#define PIN_MSD_LED_PORT 0 +#define PIN_MSD_LED_BIT 20 +#define PIN_MSD_LED (1 << PIN_MSD_LED_BIT) +#define PIN_MSD_LED_IOCON LPC_IOCON->PIO0_20 +#define PIN_MSD_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// CDC LED PIO0_11 +#define PIN_CDC_LED_PORT 0 +#define PIN_CDC_LED_BIT 11 +#define PIN_CDC_LED (1 << PIN_CDC_LED_BIT) +#define PIN_CDC_LED_IOCON LPC_IOCON->TDI_PIO0_11 +#define PIN_CDC_LED_IOCON_INIT (FUNC_1 | PULL_UP_ENABLED) + +// CM_nISP / Non-Forwarded Reset in PIN PIO0_1 +#define PIN_RESET_IN_PORT 0 +#define PIN_RESET_IN_BIT 1 +#define PIN_RESET_IN (1 << PIN_RESET_IN_BIT) +#define PIN_RESET_IN_IOCON LPC_IOCON->PIO0_1 +#define PIN_RESET_IN_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// Forwarded Reset in PIN PIO1_19 +#define PIN_RESET_IN_FWRD_PORT 0 //1 +#define PIN_RESET_IN_FWRD_BIT 1 //19 +#define PIN_RESET_IN_FWRD (1 << PIN_RESET_IN_FWRD_BIT) +#define PIN_RESET_IN_FWRD_IOCON LPC_IOCON->PIO0_1 //1_19 +#define PIN_RESET_IN_FWRD_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// CS_nSRST / nRESET OUT Pin PIO0_2 +#define PIN_nRESET_PORT 0 +#define PIN_nRESET_BIT 2 +#define PIN_nRESET (1 << PIN_nRESET_BIT) +#define PIN_nRESET_IOCON LPC_IOCON->PIO0_2 +#define PIN_nRESET_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// SWCLK PIO0_7 +#define PIN_SWCLK_PORT 0 +#define PIN_SWCLK_BIT 7 +#define PIN_SWCLK (1 << PIN_SWCLK_BIT) +#define PIN_SWCLK_TCK_IOCON LPC_IOCON->PIO0_7 +#define PIN_SWCLK_TCK_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// SWDIO In/Out Pin PIO0_8 +#define PIN_SWDIO_PORT 0 +#define PIN_SWDIO_BIT 8 +#define PIN_SWDIO (1 << PIN_SWDIO_BIT) +#define PIN_SWDIO_TMS_IOCON LPC_IOCON->PIO0_8 +#define PIN_SWDIO_TMS_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// Reset and Power control pins +// PBON PIO0_16 +#define PIN_PBON_PORT 0 +#define PIN_PBON_BIT 16 +#define PIN_PBON (1 << PIN_PBON_BIT) +#define PIN_PBON_IOCON LPC_IOCON->PIO0_16 +#define PIN_PBON_IOCON_INIT (FUNC_0 | DIGITAL_IN) + +// PWROK Pin PIO0_17 +#define PIN_PWROK_PORT 0 +#define PIN_PWROK_BIT 17 +#define PIN_PWROK (1 << PIN_PWROK_BIT) +#define PIN_PWROK_IOCON LPC_IOCON->PIO0_17 +#define PIN_PWROK_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// SHUTDOWN PIO0_15 +#define PIN_SHUTDOWN_PORT 0 +#define PIN_SHUTDOWN_BIT 15 +#define PIN_SHUTDOWN (1 << PIN_SHUTDOWN_BIT) +#define PIN_SHUTDOWN_IOCON LPC_IOCON->SWDIO_PIO0_15 +#define PIN_SHUTDOWN_IOCON_INIT (FUNC_1 | DIGITAL_IN | PULL_UP_ENABLED) + +// CB_nRST OUT Pin PIO0_4 +#define PIN_CB_nRST_PORT 0 +#define PIN_CB_nRST_BIT 4 +#define PIN_CB_nRST (1 << PIN_CB_nRST_BIT) +#define PIN_CB_nRST_IOCON LPC_IOCON->PIO0_4 +#define PIN_CB_nRST_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// CFG_nRST OUT Pin PIO0_5 +#define PIN_CFG_nRST_PORT 0 +#define PIN_CFG_nRST_BIT 5 +#define PIN_CFG_nRST (1 << PIN_CFG_nRST_BIT) +#define PIN_CFG_nRST_IOCON LPC_IOCON->PIO0_5 +#define PIN_CFG_nRST_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// CS_nDET detect for external debug to SoC +#define PIN_CS_nDET_PORT 1 +#define PIN_CS_nDET_BIT 15 +#define PIN_CS_nDET (1 << PIN_CS_nDET_BIT) +#define PIN_CS_nDET_IOCON LPC_IOCON->PIO1_15 +#define PIN_CS_nDET_IOCON_INIT (FUNC_0 | DIGITAL_IN | PULL_UP_ENABLED) + +// SCC Configuration Pins +// SCC_LOAD PIO0_9 +#define PIN_SCC_LOAD_PORT 0 +#define PIN_SCC_LOAD_BIT 9 +#define PIN_SCC_LOAD (1 << PIN_SCC_LOAD_BIT) +#define PIN_SCC_LOAD_IOCON LPC_IOCON->PIO0_9 +#define PIN_SCC_LOAD_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// SCC_WNR PIO0_10 +#define PIN_SCC_WNR_PORT 0 +#define PIN_SCC_WNR_BIT 10 +#define PIN_SCC_WNR (1 << PIN_SCC_WNR_BIT) +#define PIN_SCC_WNR_IOCON LPC_IOCON->SWCLK_PIO0_10 +#define PIN_SCC_WNR_IOCON_INIT (FUNC_1 | PULL_UP_ENABLED) + +// SCC_DATAIN PIO0_12 +#define PIN_SCC_DATAIN_PORT 0 +#define PIN_SCC_DATAIN_BIT 12 +#define PIN_SCC_DATAIN (1 << PIN_SCC_DATAIN_BIT) +#define PIN_SCC_DATAIN_IOCON LPC_IOCON->TMS_PIO0_12 +#define PIN_SCC_DATAIN_IOCON_INIT (FUNC_1 | PULL_UP_ENABLED) + +// SCC_CLK PIO0_13 +#define PIN_SCC_CLK_PORT 0 +#define PIN_SCC_CLK_BIT 13 +#define PIN_SCC_CLK (1 << PIN_SCC_CLK_BIT) +#define PIN_SCC_CLK_IOCON LPC_IOCON->TDO_PIO0_13 +#define PIN_SCC_CLK_IOCON_INIT (FUNC_1 | PULL_UP_ENABLED) + +// SCC_DATAOUT PIO0_14 +#define PIN_SCC_DATAOUT_PORT 0 +#define PIN_SCC_DATAOUT_BIT 14 +#define PIN_SCC_DATAOUT (1 << PIN_SCC_DATAOUT_BIT) +#define PIN_SCC_DATAOUT_IOCON LPC_IOCON->TRST_PIO0_14 +#define PIN_SCC_DATAOUT_IOCON_INIT (FUNC_1 | DIGITAL_IN | PULL_UP_ENABLED) + +// I2C_SCL PIO0_22 +#define PIN_I2C_SCL_PORT 0 +#define PIN_I2C_SCL_BIT 22 +#define PIN_I2C_SCL (1 << PIN_I2C_SCL_BIT) +#define PIN_I2C_SCL_IOCON LPC_IOCON->PIO0_22 +#define PIN_I2C_SCL_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// I2C_SDA PIO0_23 +#define PIN_I2C_SDA_PORT 0 +#define PIN_I2C_SDA_BIT 23 +#define PIN_I2C_SDA (1 << PIN_I2C_SDA_BIT) +#define PIN_I2C_SDA_IOCON LPC_IOCON->PIO0_23 +#define PIN_I2C_SDA_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// USART PIO0_18 +#define PIN_USART_PORT 0 +#define PIN_USART_BIT 18 +#define PIN_USART (1 << PIN_USART_BIT) +#define PIN_USART_IOCON LPC_IOCON->PIO0_18 +#define PIN_USART_IOCON_INIT (FUNC_1 | PULL_DOWN_ENABLED) + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/board/override_tiny/IO_Config_Override.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/board/override_tiny/IO_Config_Override.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,108 @@ +/** + * @file IO_Config_Override.c + * @brief Alternative IO for LPC11U35 based Hardware Interface Circuit + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ + +#include "LPC11Uxx.h" +#include "daplink.h" + +// This GPIO configuration is only valid for the LPC11U35 HIC +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC11U35); + +// Peripheral register bit masks (used for pin inits) +#define FUNC_0 0 +#define FUNC_1 1 +#define PULL_DOWN_ENABLED (1 << 3) +#define PULL_UP_ENABLED (2 << 3) +#define OPENDRAIN (1 << 10) + +// DAP LED PIO0_21 +#define PIN_DAP_LED_PORT 0 +#define PIN_DAP_LED_BIT 21 +#define PIN_DAP_LED (1 << PIN_DAP_LED_BIT) +#define PIN_DAP_LED_IOCON LPC_IOCON->PIO0_21 +#define PIN_DAP_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// MSD LED PIO0_20 +#define PIN_MSD_LED_PORT 0 +#define PIN_MSD_LED_BIT 20 +#define PIN_MSD_LED (1 << PIN_MSD_LED_BIT) +#define PIN_MSD_LED_IOCON LPC_IOCON->PIO0_20 +#define PIN_MSD_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// CDC LED PIO0_11 +#define PIN_CDC_LED_PORT 0 +#define PIN_CDC_LED_BIT 11 +#define PIN_CDC_LED (1 << PIN_CDC_LED_BIT) +#define PIN_CDC_LED_IOCON LPC_IOCON->TDI_PIO0_11 +#define PIN_CDC_LED_IOCON_INIT (FUNC_1 | PULL_UP_ENABLED) + +// Non-Forwarded Reset in PIN PIO1_19 +#define PIN_RESET_IN_PORT 1 +#define PIN_RESET_IN_BIT 19 +#define PIN_RESET_IN (1 << PIN_RESET_IN_BIT) +#define PIN_RESET_IN_IOCON LPC_IOCON->PIO1_19 +#define PIN_RESET_IN_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// Forwarded Reset in PIN PIO0_1 +#define PIN_RESET_IN_FWRD_PORT 0 +#define PIN_RESET_IN_FWRD_BIT 1 +#define PIN_RESET_IN_FWRD (1 << PIN_RESET_IN_FWRD_BIT) +#define PIN_RESET_IN_FWRD_IOCON LPC_IOCON->PIO0_1 +#define PIN_RESET_IN_FWRD_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// nRESET OUT Pin PIO0_2 +#define PIN_nRESET_PORT 0 +#define PIN_nRESET_BIT 2 +#define PIN_nRESET (1 << PIN_nRESET_BIT) +#define PIN_nRESET_IOCON LPC_IOCON->PIO0_2 +#define PIN_nRESET_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// SWCLK/TCK Pin PIO0_9 +#define PIN_SWCLK_PORT 0 +#define PIN_SWCLK_BIT 9 +#define PIN_SWCLK (1 << PIN_SWCLK_BIT) +#define PIN_SWCLK_TCK_IOCON LPC_IOCON->PIO0_9 +#define PIN_SWCLK_TCK_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// SWDIO/TMS In/Out Pin PIO0_8 +#define PIN_SWDIO_PORT 0 +#define PIN_SWDIO_BIT 8 +#define PIN_SWDIO (1 << PIN_SWDIO_BIT) +#define PIN_SWDIO_TMS_IOCON LPC_IOCON->PIO0_8 +#define PIN_SWDIO_TMS_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// TDI Pin PIO0_17 +#define PIN_TDI_PORT 17 +#define PIN_TDI_BIT 17 +#define PIN_TDI (1 << PIN_TDI_BIT) +#define PIN_TDI_IOCON LPC_IOCON->PIO0_17 +#define PIN_TDI_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// SWO/TDO Pin PIO0_9 +#define PIN_TDO_PORT 9 +#define PIN_TDO_BIT 9 +#define PIN_TDO (1 << PIN_TDO_BIT) +#define PIN_TDO_IOCON LPC_IOCON->PIO0_9 +#define PIN_TDO_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/board/override_ublox_evk_nina_b1/IO_Config_Override.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/board/override_ublox_evk_nina_b1/IO_Config_Override.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,43 @@ +/** + * @file IO_Config_Override.c + * @brief Alternative IO for LPC11U35 based Hardware Interface Circuit + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __IO_CONFIG_OVERRIDE_H__ +#define __IO_CONFIG_OVERRIDE_H__ + +// This GPIO configuration is only valid for the SAM3U2C HIC +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_SAM3U2C); + +// DAP LED +#define PIN_DAP_LED_PORT PIOA +#define PIN_DAP_LED_BIT 29 +#define PIN_DAP_LED (1UL << PIN_DAP_LED_BIT) + +// MSD LED +#define PIN_MSD_LED_PORT PIOA +#define PIN_MSD_LED_BIT 29 +#define PIN_MSD_LED (1UL << PIN_MSD_LED_BIT) + +// CDC LED +#define PIN_CDC_LED_PORT PIOA +#define PIN_CDC_LED_BIT 29 +#define PIN_CDC_LED (1UL << PIN_CDC_LED_BIT) + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/board/override_vbluno51/IO_Config_Override.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/board/override_vbluno51/IO_Config_Override.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,113 @@ +/** + * @file IO_Config_Override.c + * @brief Alternative IO for LPC11U35 based Hardware Interface Circuit + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * The VBLUno51 board use PIO0_9(18) pin for TGT_SWCLK function. + * Because it uses RTS/CTS pins for UART Hardware flow control feature. + */ + +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ + +#include "LPC11Uxx.h" +#include "daplink.h" + +// This GPIO configuration is only valid for the LPC11U35 HIC +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC11U35); + +// Peripheral register bit masks (used for pin inits) +#define FUNC_0 0 +#define FUNC_1 1 +#define PULL_DOWN_ENABLED (1 << 3) +#define PULL_UP_ENABLED (2 << 3) +#define OPENDRAIN (1 << 10) + +// DAP LED PIO0_21 +#define PIN_DAP_LED_PORT 0 +#define PIN_DAP_LED_BIT 21 +#define PIN_DAP_LED (1 << PIN_DAP_LED_BIT) +#define PIN_DAP_LED_IOCON LPC_IOCON->PIO0_21 +#define PIN_DAP_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// MSD LED PIO0_20 +#define PIN_MSD_LED_PORT 0 +#define PIN_MSD_LED_BIT 20 +#define PIN_MSD_LED (1 << PIN_MSD_LED_BIT) +#define PIN_MSD_LED_IOCON LPC_IOCON->PIO0_20 +#define PIN_MSD_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// CDC LED PIO0_11 +#define PIN_CDC_LED_PORT 0 +#define PIN_CDC_LED_BIT 11 +#define PIN_CDC_LED (1 << PIN_CDC_LED_BIT) +#define PIN_CDC_LED_IOCON LPC_IOCON->TDI_PIO0_11 +#define PIN_CDC_LED_IOCON_INIT (FUNC_1 | PULL_UP_ENABLED) + +// Non-Forwarded Reset in PIN PIO1_19 +#define PIN_RESET_IN_PORT 1 +#define PIN_RESET_IN_BIT 19 +#define PIN_RESET_IN (1 << PIN_RESET_IN_BIT) +#define PIN_RESET_IN_IOCON LPC_IOCON->PIO1_19 +#define PIN_RESET_IN_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// Forwarded Reset in PIN PIO0_1 +#define PIN_RESET_IN_FWRD_PORT 0 +#define PIN_RESET_IN_FWRD_BIT 1 +#define PIN_RESET_IN_FWRD (1 << PIN_RESET_IN_FWRD_BIT) +#define PIN_RESET_IN_FWRD_IOCON LPC_IOCON->PIO0_1 +#define PIN_RESET_IN_FWRD_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// nRESET OUT Pin PIO0_2 +#define PIN_nRESET_PORT 0 +#define PIN_nRESET_BIT 2 +#define PIN_nRESET (1 << PIN_nRESET_BIT) +#define PIN_nRESET_IOCON LPC_IOCON->PIO0_2 +#define PIN_nRESET_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// SWCLK/TCK Pin PIO0_9 +#define PIN_SWCLK_PORT 0 +#define PIN_SWCLK_BIT 9 +#define PIN_SWCLK (1 << PIN_SWCLK_BIT) +#define PIN_SWCLK_TCK_IOCON LPC_IOCON->PIO0_9 +#define PIN_SWCLK_TCK_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// SWDIO/TMS In/Out Pin PIO0_8 +#define PIN_SWDIO_PORT 0 +#define PIN_SWDIO_BIT 8 +#define PIN_SWDIO (1 << PIN_SWDIO_BIT) +#define PIN_SWDIO_TMS_IOCON LPC_IOCON->PIO0_8 +#define PIN_SWDIO_TMS_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// TDI Pin PIO0_17 +#define PIN_TDI_PORT 17 +#define PIN_TDI_BIT 17 +#define PIN_TDI (1 << PIN_TDI_BIT) +#define PIN_TDI_IOCON LPC_IOCON->PIO0_17 +#define PIN_TDI_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// SWO/TDO Pin PIO0_9 +#define PIN_TDO_PORT 9 +#define PIN_TDO_BIT 9 +#define PIN_TDO (1 << PIN_TDO_BIT) +#define PIN_TDO_IOCON LPC_IOCON->PIO0_9 +#define PIN_TDO_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/board/rapid_iot.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/rapid_iot.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,94 @@
+/**
+ * @file rapiod_iot.c
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2018, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "swd_host.h"
+#include "target_board.h"
+#include "target_family.h"
+
+char *board_id_kw41z = "0234";
+
+#define MDM_STATUS 0x01000000
+#define MDM_CTRL 0x01000004
+#define MDM_IDR 0x010000fc
+#define MDM_ID_K64 0x001c0000 // K64
+#define MDM_ID_KW4 0x001c0020 // KW4
+
+/* Kinetis series ID */
+#define K_SERIES 0
+#define KW_SERIES 5
+
+/* KW4 subfamily defines */
+#define KW40 0
+#define KW41 1
+
+
+static void prerun_board_config(void);
+
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0228",
+ .family_id = kNXP_RapidIot_FamilyID,
+ .flags = kEnablePageErase,
+ .daplink_url_name = "PRODINFOHTM",
+ .daplink_drive_name = "IOT-DAPLINK",
+ .daplink_target_url = "http://www.nxp.com/rapid-iot",
+ .target_cfg = &target_device,
+ .prerun_board_config = prerun_board_config,
+};
+
+static void prerun_board_config(void)
+{
+ // SIM peripheral 0x40047000
+ // address offset 0x 1024
+ uint32_t SDID = 0x40048024;
+ uint32_t sdid;
+
+ // get a hold of the target
+ if (target_set_state(HALT) == 0) {
+ /*
+ * When the Kinetis flash is empty the reset line toggles. This causes failures
+ * when trying to halt the target. Use the reset halt method in this case.
+ */
+ target_set_state(RESET_PROGRAM);
+ }
+
+ // Read the system identification register
+ swd_read_memory(SDID, (uint8_t *)&sdid, 4);
+
+ // Set the target flash algorithm
+ if (((sdid >> 20) & 0xF) == KW_SERIES) {
+ //mdm_id = MDM_ID_KW4;
+
+ if (((sdid >> 24) & 0x3) == KW40) {
+ // Program to the KW40 flash
+ extern target_cfg_t target_device_kw40;
+ target_device = target_device_kw40;
+ } else {
+ // Program to the KW41 flash
+ extern target_cfg_t target_device_kw41;
+ target_device = target_device_kw41;
+ target_device.rt_board_id = board_id_kw41z;
+ }
+ }
+
+ // Let the target run
+ target_set_state(RUN);
+}
diff -r 000000000000 -r 01f31e923fe2 source/board/rbl.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/rbl.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file rbl.c
+ * @brief board ID for the Red Bear Labs Arduino based nRF51822 board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "1090",
+ .family_id = kNordic_Nrf51_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/rblnano.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/rblnano.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file rblnano.c
+ * @brief board ID for the Red Bear Labs Nano board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "1095",
+ .family_id = kNordic_Nrf51_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/ro359b.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/ro359b.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,31 @@
+/**
+ * @file ro359b.c
+ * @brief board ID for the RO359B board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "1022",
+ .family_id = kStub_HWReset_FamilyID,
+ .daplink_drive_name = "MBED ",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/rtl8195am.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/rtl8195am.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,33 @@
+/**
+ * @file rtl8195am.c
+ * @brief board ID for the Realtek RTL8195AM board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2014-2019, Realtek Semiconductor Corp., All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "string.h"
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "4600",
+ .family_id = kRealtek_Rtl8195am_FamilyID,
+ .flags = kEnablePageErase,
+ .target_cfg = &target_device,
+};
+
diff -r 000000000000 -r 01f31e923fe2 source/board/sam3u2c_bl.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/sam3u2c_bl.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,65 @@
+/**
+ * @file sam3u2c_bl.c
+ * @brief board ID and meta-data for the hardware interface circuit (HIC) based on ATSAM3U
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+#include "daplink_addr.h"
+#include "compiler.h"
+#include "target_board.h"
+#include "target_family.h"
+
+// Warning - changing the interface start will break backwards compatibility
+COMPILER_ASSERT(DAPLINK_ROM_IF_START == (0x00080000 + KB(32)));
+COMPILER_ASSERT(DAPLINK_ROM_IF_SIZE == (KB(124) - KB(32)));
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {DAPLINK_ROM_IF_START, 0x1000},
+ };
+
+// atsam3u2c target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = DAPLINK_ROM_IF_START,
+ .flash_regions[0].end = DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .ram_regions[0].start = 0x2007C000,
+ .ram_regions[0].end = 0x20084000,
+ /* .flash_algo not needed for bootloader */
+};
+
+//bootloader has no family
+const target_family_descriptor_t *g_target_family = NULL;
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0000",
+ .daplink_url_name = "HELP_FAQHTM",
+ .daplink_drive_name = "MAINTENANCE",
+ .daplink_target_url = "https://mbed.com/daplink",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/scci824.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/scci824.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,33 @@
+/**
+ * @file ss824.c
+ * @brief board ID for the Switch Science LPC824 board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "1018",
+ .family_id = kStub_HWReset_FamilyID,
+ .daplink_drive_name = "MBED ",
+ .target_cfg = &target_device,
+};
+
+
diff -r 000000000000 -r 01f31e923fe2 source/board/ssci1114.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/ssci1114.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,32 @@
+/**
+ * @file ssci1114.c
+ * @brief board ID for the Switch Science LPC1114 board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "1114",
+ .family_id = kStub_HWReset_FamilyID,
+ .daplink_drive_name = "MBED ",
+ .target_cfg = &target_device,
+};
+
diff -r 000000000000 -r 01f31e923fe2 source/board/ssci_chibi.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/ssci_chibi.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,32 @@
+/**
+ * @file sscity.c
+ * @brief board ID for the Switch Science ty51822r3 board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "1021",
+ .family_id = kNordic_Nrf51_FamilyID,
+ .daplink_drive_name = "MBED ",
+ .target_cfg = &target_device,
+};
+
diff -r 000000000000 -r 01f31e923fe2 source/board/sscity.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/sscity.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,32 @@
+/**
+ * @file sscity.c
+ * @brief board ID for the Switch Science ty51822r3 board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "1019",
+ .family_id = kNordic_Nrf51_FamilyID,
+ .daplink_drive_name = "MBED ",
+ .target_cfg = &target_device,
+};
+
diff -r 000000000000 -r 01f31e923fe2 source/board/stm32f072rb.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/stm32f072rb.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file stm32f103rb.c
+ * @brief board ID for the STM32 NUCLEO-F103RB board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0720",
+ .family_id = kStub_HWReset_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/stm32f103rb.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/stm32f103rb.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file stm32f103rb.c
+ * @brief board ID for the STM32 NUCLEO-F103RB board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0700",
+ .family_id = kStub_HWReset_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/stm32f103xb_bl.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/stm32f103xb_bl.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,59 @@
+/**
+ * @file stm32f103_bl.c
+ * @brief board ID and meta-data for the hardware interface circuit (HIC) based on STM32F103XB
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+#include "target_board.h"
+#include "target_family.h"
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x08000000 + KB(48), 0x400},
+ };
+
+// stm32f103 target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x08000000 + KB(48),
+ .flash_regions[0].end = 0x08000000 + KB(128),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20005000,
+ /* .flash_algo not needed for bootloader */
+};
+
+//bootloader has no family
+const target_family_descriptor_t *g_target_family = NULL;
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0000",
+ .daplink_url_name = "HELP_FAQHTM",
+ .daplink_drive_name = "MAINTENANCE",
+ .daplink_target_url = "https://mbed.com/daplink",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/stm32f207zg.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/stm32f207zg.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file stm32f103rb.c
+ * @brief board ID for the STM32 NUCLEO-F103RB board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0835",
+ .family_id = kStub_HWReset_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/stm32f334r8.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/stm32f334r8.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file stm32f103rb.c
+ * @brief board ID for the STM32 NUCLEO-F103RB board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0735",
+ .family_id = kStub_HWReset_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/stm32f401re.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/stm32f401re.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file stm32f401re.c
+ * @brief board ID for the STM32 NUCLEO-F401RE board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0720",
+ .family_id = kStub_HWReset_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/stm32f411re.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/stm32f411re.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file stm32f103rb.c
+ * @brief board ID for the STM32 NUCLEO-F103RB board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0740",
+ .family_id = kStub_HWReset_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/stm32f429zi.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/stm32f429zi.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file stm32f429zi.c
+ * @brief board ID for the STM32 NUCLEO-F429ZI board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0796",
+ .family_id = kStub_HWReset_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/stm32f746zg.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/stm32f746zg.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file stm32f103rb.c
+ * @brief board ID for the STM32 NUCLEO-F103RB board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0816",
+ .family_id = kStub_HWReset_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/stm32l476rg.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/stm32l476rg.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file stm32f103rb.c
+ * @brief board ID for the STM32 NUCLEO-F103RB board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0765",
+ .family_id = kStub_HWReset_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/swdap-lpc11u35.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/swdap-lpc11u35.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file SWDAP-lpc11u35.c
+ * @brief board ID for the Seeed Studio ArchBLE board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "7401",
+ .family_id = kStub_HWReset_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/tiny.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/tiny.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file tiny.c
+ * @brief board ID for the Seeed Studio BLE Tiny board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "9012",
+ .family_id = kNordic_Nrf51_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/twrke18f.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/twrke18f.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,33 @@
+/**
+ * @file twrke18f.c
+ * @brief board ID for the NXP TWR-KE18F board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0206",
+ .family_id = kNXP_KinetisK_FamilyID,
+ .daplink_url_name = "PRODINFOHTM",
+ .daplink_drive_name = "TWR-KE18FD",
+ .daplink_target_url = "http://www.nxp.com/twr-ke18f",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/twrkl28z72m.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/twrkl28z72m.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,33 @@
+/**
+ * @file twrkl28z72m.c
+ * @brief board ID for the NXP TWR-KL28Z72M board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_board.h"
+#include "target_family.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0203",
+ .family_id = kNXP_KinetisL_FamilyID,
+ .daplink_url_name = "PRODINFOHTM",
+ .daplink_drive_name = "TWR-KL28ZD",
+ .daplink_target_url = "http://www.nxp.com/twr-kl28z72m",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/ublox_evk_nina_b1.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/ublox_evk_nina_b1.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,38 @@
+/**
+ * @file ublox_evk_nina_b1.c
+ * @brief board ID for the UBLOX_EVK_NINA_B1
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "DAP_config.h"
+#include "target_board.h"
+#include "target_family.h"
+
+static void nina_swd_set_target_reset(uint8_t asserted){
+ if(!asserted) {
+ PIOA->PIO_MDER = PIN_SWDIO | PIN_SWCLK | PIN_nRESET;
+ }
+}
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "1237",
+ .family_id = kNordic_Nrf52_FamilyID,
+ .swd_set_target_reset = nina_swd_set_target_reset,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/ublox_evk_odin_w2.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/ublox_evk_odin_w2.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file stm32f429zi.c
+ * @brief board ID for the STM32 NUCLEO-F429ZI board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "1236",
+ .family_id = kStub_HWReset_FamilyID,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/vbluno51.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/vbluno51.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,38 @@
+/**
+ * @file vbluno51.c
+ * @brief Board ID for the VBLUno51 board (VNG Bluetooth Low Energy UNO nRF51822 board)
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "uart.h"
+#include "target_board.h"
+#include "target_family.h"
+
+static void vbluno_prerun_board_config()
+{
+ uart_enable_flow_control(false);
+}
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "C006",
+ .family_id = kNordic_Nrf51_FamilyID,
+ .daplink_target_url = "https://os.mbed.com/platforms/VBLUNO51/",
+ .prerun_board_config = vbluno_prerun_board_config,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/wio3g.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/wio3g.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file wio3g.c
+ * @brief board ID for the mbed cloud connect board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2018-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .board_id = "9014",
+ .family_id = kStub_HWReset_FamilyID,
+ .flags = kEnablePageErase|kEnableUnderResetConnect,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/wio_emw3166.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/wio_emw3166.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,31 @@
+/**
+ * @file wio_emw3166.c
+ * @brief board ID for Seeed Wio EMW3166
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "9017",
+ .family_id = kStub_HWReset_FamilyID,
+ .flags = kEnablePageErase|kEnableUnderResetConnect,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/wiobg96.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/wiobg96.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,30 @@
+/**
+ * @file wiobg96.c
+ * @brief board ID for the mbed cloud connect board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2018-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .board_id = "9015",
+ .family_id = kStub_HWReset_FamilyID,
+ .flags = kEnablePageErase|kEnableUnderResetConnect,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/wizwiki_w7500.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/wizwiki_w7500.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,49 @@
+/**
+ * @file wizwiki_w7500.c
+ * @brief board ID for the WIZnet WIZwiki-W7500 board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "cmsis_os2.h"
+#include "target_family.h"
+#include "target_board.h"
+#include "swd_host.h"
+
+static uint8_t target_set_state_by_board(target_state_t state)
+{
+ if( state == RESET_PROGRAM )
+ {
+ do
+ {
+ swd_set_target_reset(1);
+ osDelay(2);
+
+ swd_set_target_reset(0);
+ osDelay(2);
+ } while(!swd_init_debug());
+ }
+ return 1;
+}
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "2201",
+ .family_id = kWiznet_W7500_FamilyID,
+ .target_set_state = target_set_state_by_board,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/wizwiki_w7500_eco.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/wizwiki_w7500_eco.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,49 @@
+/**
+ * @file wizwiki_w7500_eco.c
+ * @brief board ID for the WIZnet WIZwiki-W7500ECO board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "cmsis_os2.h"
+#include "target_family.h"
+#include "target_board.h"
+#include "swd_host.h"
+
+static uint8_t target_set_state_by_board(target_state_t state)
+{
+ if( state == RESET_PROGRAM )
+ {
+ do
+ {
+ swd_set_target_reset(1);
+ osDelay(2);
+
+ swd_set_target_reset(0);
+ osDelay(2);
+ } while(!swd_init_debug());
+ }
+ return 1;
+}
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "2202",
+ .family_id = kWiznet_W7500_FamilyID,
+ .target_set_state = target_set_state_by_board,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/wizwiki_w7500p.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/wizwiki_w7500p.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,49 @@
+/**
+ * @file wizwiki_w7500p.c
+ * @brief board ID for the WIZnet WIZwiki-W7500P board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "cmsis_os2.h"
+#include "target_family.h"
+#include "target_board.h"
+#include "swd_host.h"
+
+static uint8_t target_set_state_by_board(target_state_t state)
+{
+ if( state == RESET_PROGRAM )
+ {
+ do
+ {
+ swd_set_target_reset(1);
+ osDelay(2);
+
+ swd_set_target_reset(0);
+ osDelay(2);
+ } while(!swd_init_debug());
+ }
+ return 1;
+}
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "2203",
+ .family_id = kWiznet_W7500_FamilyID,
+ .target_set_state = target_set_state_by_board,
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/board/xDot-L151.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/board/xDot-L151.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,32 @@
+/**
+ * @file xDot.c
+ * @brief board ID for the MultiTech xDot
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_board.h"
+
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0350",
+ .family_id = kStub_HWReset_FamilyID,
+ .daplink_url_name = "XDOT HTM",
+ .daplink_drive_name = "XDOT ",
+ .target_cfg = &target_device,
+};
diff -r 000000000000 -r 01f31e923fe2 source/cmsis-core/cmsis_armcc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/cmsis-core/cmsis_armcc.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,882 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version V5.1.1
+ * @date 30. July 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
+ #define __ARM_ARCH_6M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
+ #define __ARM_ARCH_7M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+ #define __ARM_ARCH_7EM__ 1
+#endif
+
+ /* __ARM_ARCH_8M_BASE__ not applicable */
+ /* __ARM_ARCH_8M_MAIN__ not applicable */
+
+/* CMSIS compiler control DSP macros */
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __ARM_FEATURE_DSP 1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE static __forceinline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __declspec(noreturn)
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT __packed struct
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION __packed union
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __memory_changed()
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return result;
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff -r 000000000000 -r 01f31e923fe2 source/cmsis-core/cmsis_armclang.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/cmsis-core/cmsis_armclang.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1444 @@
+/**************************************************************************//**
+ * @file cmsis_armclang.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V5.2.1
+ * @date 30. July 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF)
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+#define __SADD8 __builtin_arm_sadd8
+#define __QADD8 __builtin_arm_qadd8
+#define __SHADD8 __builtin_arm_shadd8
+#define __UADD8 __builtin_arm_uadd8
+#define __UQADD8 __builtin_arm_uqadd8
+#define __UHADD8 __builtin_arm_uhadd8
+#define __SSUB8 __builtin_arm_ssub8
+#define __QSUB8 __builtin_arm_qsub8
+#define __SHSUB8 __builtin_arm_shsub8
+#define __USUB8 __builtin_arm_usub8
+#define __UQSUB8 __builtin_arm_uqsub8
+#define __UHSUB8 __builtin_arm_uhsub8
+#define __SADD16 __builtin_arm_sadd16
+#define __QADD16 __builtin_arm_qadd16
+#define __SHADD16 __builtin_arm_shadd16
+#define __UADD16 __builtin_arm_uadd16
+#define __UQADD16 __builtin_arm_uqadd16
+#define __UHADD16 __builtin_arm_uhadd16
+#define __SSUB16 __builtin_arm_ssub16
+#define __QSUB16 __builtin_arm_qsub16
+#define __SHSUB16 __builtin_arm_shsub16
+#define __USUB16 __builtin_arm_usub16
+#define __UQSUB16 __builtin_arm_uqsub16
+#define __UHSUB16 __builtin_arm_uhsub16
+#define __SASX __builtin_arm_sasx
+#define __QASX __builtin_arm_qasx
+#define __SHASX __builtin_arm_shasx
+#define __UASX __builtin_arm_uasx
+#define __UQASX __builtin_arm_uqasx
+#define __UHASX __builtin_arm_uhasx
+#define __SSAX __builtin_arm_ssax
+#define __QSAX __builtin_arm_qsax
+#define __SHSAX __builtin_arm_shsax
+#define __USAX __builtin_arm_usax
+#define __UQSAX __builtin_arm_uqsax
+#define __UHSAX __builtin_arm_uhsax
+#define __USAD8 __builtin_arm_usad8
+#define __USADA8 __builtin_arm_usada8
+#define __SSAT16 __builtin_arm_ssat16
+#define __USAT16 __builtin_arm_usat16
+#define __UXTB16 __builtin_arm_uxtb16
+#define __UXTAB16 __builtin_arm_uxtab16
+#define __SXTB16 __builtin_arm_sxtb16
+#define __SXTAB16 __builtin_arm_sxtab16
+#define __SMUAD __builtin_arm_smuad
+#define __SMUADX __builtin_arm_smuadx
+#define __SMLAD __builtin_arm_smlad
+#define __SMLADX __builtin_arm_smladx
+#define __SMLALD __builtin_arm_smlald
+#define __SMLALDX __builtin_arm_smlaldx
+#define __SMUSD __builtin_arm_smusd
+#define __SMUSDX __builtin_arm_smusdx
+#define __SMLSD __builtin_arm_smlsd
+#define __SMLSDX __builtin_arm_smlsdx
+#define __SMLSLD __builtin_arm_smlsld
+#define __SMLSLDX __builtin_arm_smlsldx
+#define __SEL __builtin_arm_sel
+#define __QADD __builtin_arm_qadd
+#define __QSUB __builtin_arm_qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff -r 000000000000 -r 01f31e923fe2 source/cmsis-core/cmsis_armclang_ltm.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/cmsis-core/cmsis_armclang_ltm.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1891 @@
+/**************************************************************************//**
+ * @file cmsis_armclang_ltm.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V1.2.1
+ * @date 30. July 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF)
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff -r 000000000000 -r 01f31e923fe2 source/cmsis-core/cmsis_compiler.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/cmsis-core/cmsis_compiler.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,283 @@
+/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler generic header file
+ * @version V5.1.0
+ * @date 09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+ #include "cmsis_armclang_ltm.h"
+
+ /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+ #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+ #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+ #include <cmsis_ccs.h>
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed))
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed))
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #endif
+ #ifndef __RESTRICT
+ #define __RESTRICT __restrict
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed__
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __packed__
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __packed__
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __packed__ T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __align(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+ #include <cmsis_csm.h>
+
+ #ifndef __ASM
+ #define __ASM _asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ // NO RETURN is automatically detected hence no warning here
+ #define __NO_RETURN
+ #endif
+ #ifndef __USED
+ #warning No compiler specific solution for __USED. __USED is ignored.
+ #define __USED
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __PACKED
+ #define __PACKED @packed
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT @packed struct
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION @packed union
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ @packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+#else
+ #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff -r 000000000000 -r 01f31e923fe2 source/cmsis-core/cmsis_gcc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/cmsis-core/cmsis_gcc.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,2168 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS compiler GCC header file
+ * @version V5.2.1
+ * @date 30. July 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+ #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+
+/**
+ \brief Initializes data and bss sections
+ \details This default implementations initialized all data and additional bss
+ sections relying on .copy.table and .zero.table specified properly
+ in the used linker script.
+
+ */
+__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+{
+ extern void _start(void) __NO_RETURN;
+
+ typedef struct {
+ uint32_t const* src;
+ uint32_t* dest;
+ uint32_t wlen;
+ } __copy_table_t;
+
+ typedef struct {
+ uint32_t* dest;
+ uint32_t wlen;
+ } __zero_table_t;
+
+ extern const __copy_table_t __copy_table_start__;
+ extern const __copy_table_t __copy_table_end__;
+ extern const __zero_table_t __zero_table_start__;
+ extern const __zero_table_t __zero_table_end__;
+
+ for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {
+ for(uint32_t i=0u; i<pTable->wlen; ++i) {
+ pTable->dest[i] = pTable->src[i];
+ }
+ }
+
+ for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
+ for(uint32_t i=0u; i<pTable->wlen; ++i) {
+ pTable->dest[i] = 0u;
+ }
+ }
+
+ _start();
+}
+
+#define __PROGRAM_START __cmsis_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP __StackTop
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT __StackLimit
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ return __builtin_arm_get_fpscr();
+#else
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#endif
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ __builtin_arm_set_fpscr(fpscr);
+#else
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP() __ASM volatile ("nop")
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI() __ASM volatile ("wfi":::"memory")
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE() __ASM volatile ("wfe":::"memory")
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV() __ASM volatile ("sev")
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (int16_t)__builtin_bswap16(value);
+#else
+ int16_t result;
+
+ __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return result;
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1, ARG2) \
+__extension__ \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1, ARG2) \
+ __extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+ return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1, ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1, ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff -r 000000000000 -r 01f31e923fe2 source/cmsis-core/cmsis_iccarm.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/cmsis-core/cmsis_iccarm.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,964 @@
+/**************************************************************************//**
+ * @file cmsis_iccarm.h
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version V5.1.1
+ * @date 30. July 2019
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2019 IAR Systems
+// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+ #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+ #define __ICCARM_V8 1
+#else
+ #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+ #if __ICCARM_V8
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #elif (__VER__ >= 7080000)
+ /* Needs IAR language extensions */
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #else
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+ #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+ #if __ARM_ARCH == 6
+ #define __ARM_ARCH_6M__ 1
+ #elif __ARM_ARCH == 7
+ #if __ARM_FEATURE_DSP
+ #define __ARM_ARCH_7EM__ 1
+ #else
+ #define __ARM_ARCH_7M__ 1
+ #endif
+ #endif /* __ARM_ARCH */
+ #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+ #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+ #define __ARM_ARCH_6M__ 1
+ #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+ #define __ARM_ARCH_7M__ 1
+ #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+ #define __ARM_ARCH_7EM__ 1
+ #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #else
+ #error "Unknown target."
+ #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+ #define __IAR_M0_FAMILY 1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+ #define __IAR_M0_FAMILY 1
+#else
+ #define __IAR_M0_FAMILY 0
+#endif
+
+
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+
+#ifndef __NO_RETURN
+ #if __ICCARM_V8
+ #define __NO_RETURN __attribute__((__noreturn__))
+ #else
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+ #endif
+#endif
+
+#ifndef __PACKED
+ #if __ICCARM_V8
+ #define __PACKED __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED __packed
+ #endif
+#endif
+
+#ifndef __PACKED_STRUCT
+ #if __ICCARM_V8
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_STRUCT __packed struct
+ #endif
+#endif
+
+#ifndef __PACKED_UNION
+ #if __ICCARM_V8
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_UNION __packed union
+ #endif
+#endif
+
+#ifndef __RESTRICT
+ #if __ICCARM_V8
+ #define __RESTRICT __restrict
+ #else
+ /* Needs IAR language extensions */
+ #define __RESTRICT restrict
+ #endif
+#endif
+
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE _Pragma("inline=forced")
+#endif
+
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+ return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+ *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+ return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+ *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef __USED
+ #if __ICCARM_V8
+ #define __USED __attribute__((used))
+ #else
+ #define __USED _Pragma("__root")
+ #endif
+#endif
+
+#ifndef __WEAK
+ #if __ICCARM_V8
+ #define __WEAK __attribute__((weak))
+ #else
+ #define __WEAK _Pragma("__weak")
+ #endif
+#endif
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __iar_program_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP CSTACK$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT CSTACK$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __vector_table
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
+#endif
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+ #define __ICCARM_INTRINSICS_VERSION__ 0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+ #if defined(__CLZ)
+ #undef __CLZ
+ #endif
+ #if defined(__REVSH)
+ #undef __REVSH
+ #endif
+ #if defined(__RBIT)
+ #undef __RBIT
+ #endif
+ #if defined(__SSAT)
+ #undef __SSAT
+ #endif
+ #if defined(__USAT)
+ #undef __USAT
+ #endif
+
+ #include "iccarm_builtin.h"
+
+ #define __disable_fault_irq __iar_builtin_disable_fiq
+ #define __disable_irq __iar_builtin_disable_interrupt
+ #define __enable_fault_irq __iar_builtin_enable_fiq
+ #define __enable_irq __iar_builtin_enable_interrupt
+ #define __arm_rsr __iar_builtin_rsr
+ #define __arm_wsr __iar_builtin_wsr
+
+
+ #define __get_APSR() (__arm_rsr("APSR"))
+ #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
+ #define __get_CONTROL() (__arm_rsr("CONTROL"))
+ #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
+
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
+ #else
+ #define __get_FPSCR() ( 0 )
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #define __get_IPSR() (__arm_rsr("IPSR"))
+ #define __get_MSP() (__arm_rsr("MSP"))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __get_MSPLIM() (0U)
+ #else
+ #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
+ #endif
+ #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
+ #define __get_PSP() (__arm_rsr("PSP"))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __get_PSPLIM() (0U)
+ #else
+ #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
+ #endif
+
+ #define __get_xPSR() (__arm_rsr("xPSR"))
+
+ #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
+ #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
+ #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
+ #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
+ #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __set_MSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
+ #endif
+ #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
+ #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __set_PSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
+ #endif
+
+ #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
+ #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
+ #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
+ #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
+ #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
+ #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
+ #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
+ #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
+ #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
+ #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
+ #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
+ #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
+ #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
+ #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __TZ_get_PSPLIM_NS() (0U)
+ #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+ #else
+ #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
+ #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+ #endif
+
+ #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
+ #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+ #define __NOP __iar_builtin_no_operation
+
+ #define __CLZ __iar_builtin_CLZ
+ #define __CLREX __iar_builtin_CLREX
+
+ #define __DMB __iar_builtin_DMB
+ #define __DSB __iar_builtin_DSB
+ #define __ISB __iar_builtin_ISB
+
+ #define __LDREXB __iar_builtin_LDREXB
+ #define __LDREXH __iar_builtin_LDREXH
+ #define __LDREXW __iar_builtin_LDREX
+
+ #define __RBIT __iar_builtin_RBIT
+ #define __REV __iar_builtin_REV
+ #define __REV16 __iar_builtin_REV16
+
+ __IAR_FT int16_t __REVSH(int16_t val)
+ {
+ return (int16_t) __iar_builtin_REVSH(val);
+ }
+
+ #define __ROR __iar_builtin_ROR
+ #define __RRX __iar_builtin_RRX
+
+ #define __SEV __iar_builtin_SEV
+
+ #if !__IAR_M0_FAMILY
+ #define __SSAT __iar_builtin_SSAT
+ #endif
+
+ #define __STREXB __iar_builtin_STREXB
+ #define __STREXH __iar_builtin_STREXH
+ #define __STREXW __iar_builtin_STREX
+
+ #if !__IAR_M0_FAMILY
+ #define __USAT __iar_builtin_USAT
+ #endif
+
+ #define __WFE __iar_builtin_WFE
+ #define __WFI __iar_builtin_WFI
+
+ #if __ARM_MEDIA__
+ #define __SADD8 __iar_builtin_SADD8
+ #define __QADD8 __iar_builtin_QADD8
+ #define __SHADD8 __iar_builtin_SHADD8
+ #define __UADD8 __iar_builtin_UADD8
+ #define __UQADD8 __iar_builtin_UQADD8
+ #define __UHADD8 __iar_builtin_UHADD8
+ #define __SSUB8 __iar_builtin_SSUB8
+ #define __QSUB8 __iar_builtin_QSUB8
+ #define __SHSUB8 __iar_builtin_SHSUB8
+ #define __USUB8 __iar_builtin_USUB8
+ #define __UQSUB8 __iar_builtin_UQSUB8
+ #define __UHSUB8 __iar_builtin_UHSUB8
+ #define __SADD16 __iar_builtin_SADD16
+ #define __QADD16 __iar_builtin_QADD16
+ #define __SHADD16 __iar_builtin_SHADD16
+ #define __UADD16 __iar_builtin_UADD16
+ #define __UQADD16 __iar_builtin_UQADD16
+ #define __UHADD16 __iar_builtin_UHADD16
+ #define __SSUB16 __iar_builtin_SSUB16
+ #define __QSUB16 __iar_builtin_QSUB16
+ #define __SHSUB16 __iar_builtin_SHSUB16
+ #define __USUB16 __iar_builtin_USUB16
+ #define __UQSUB16 __iar_builtin_UQSUB16
+ #define __UHSUB16 __iar_builtin_UHSUB16
+ #define __SASX __iar_builtin_SASX
+ #define __QASX __iar_builtin_QASX
+ #define __SHASX __iar_builtin_SHASX
+ #define __UASX __iar_builtin_UASX
+ #define __UQASX __iar_builtin_UQASX
+ #define __UHASX __iar_builtin_UHASX
+ #define __SSAX __iar_builtin_SSAX
+ #define __QSAX __iar_builtin_QSAX
+ #define __SHSAX __iar_builtin_SHSAX
+ #define __USAX __iar_builtin_USAX
+ #define __UQSAX __iar_builtin_UQSAX
+ #define __UHSAX __iar_builtin_UHSAX
+ #define __USAD8 __iar_builtin_USAD8
+ #define __USADA8 __iar_builtin_USADA8
+ #define __SSAT16 __iar_builtin_SSAT16
+ #define __USAT16 __iar_builtin_USAT16
+ #define __UXTB16 __iar_builtin_UXTB16
+ #define __UXTAB16 __iar_builtin_UXTAB16
+ #define __SXTB16 __iar_builtin_SXTB16
+ #define __SXTAB16 __iar_builtin_SXTAB16
+ #define __SMUAD __iar_builtin_SMUAD
+ #define __SMUADX __iar_builtin_SMUADX
+ #define __SMMLA __iar_builtin_SMMLA
+ #define __SMLAD __iar_builtin_SMLAD
+ #define __SMLADX __iar_builtin_SMLADX
+ #define __SMLALD __iar_builtin_SMLALD
+ #define __SMLALDX __iar_builtin_SMLALDX
+ #define __SMUSD __iar_builtin_SMUSD
+ #define __SMUSDX __iar_builtin_SMUSDX
+ #define __SMLSD __iar_builtin_SMLSD
+ #define __SMLSDX __iar_builtin_SMLSDX
+ #define __SMLSLD __iar_builtin_SMLSLD
+ #define __SMLSLDX __iar_builtin_SMLSLDX
+ #define __SEL __iar_builtin_SEL
+ #define __QADD __iar_builtin_QADD
+ #define __QSUB __iar_builtin_QSUB
+ #define __PKHBT __iar_builtin_PKHBT
+ #define __PKHTB __iar_builtin_PKHTB
+ #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #define __CLZ __cmsis_iar_clz_not_active
+ #define __SSAT __cmsis_iar_ssat_not_active
+ #define __USAT __cmsis_iar_usat_not_active
+ #define __RBIT __cmsis_iar_rbit_not_active
+ #define __get_APSR __cmsis_iar_get_APSR_not_active
+ #endif
+
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+ #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+ #endif
+
+ #ifdef __INTRINSICS_INCLUDED
+ #error intrinsics.h is already included previously!
+ #endif
+
+ #include <intrinsics.h>
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #undef __CLZ
+ #undef __SSAT
+ #undef __USAT
+ #undef __RBIT
+ #undef __get_APSR
+
+ __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+ {
+ if (data == 0U) { return 32U; }
+
+ uint32_t count = 0U;
+ uint32_t mask = 0x80000000U;
+
+ while ((data & mask) == 0U)
+ {
+ count += 1U;
+ mask = mask >> 1U;
+ }
+ return count;
+ }
+
+ __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+ {
+ uint8_t sc = 31U;
+ uint32_t r = v;
+ for (v >>= 1U; v; v >>= 1U)
+ {
+ r <<= 1U;
+ r |= v & 1U;
+ sc--;
+ }
+ return (r << sc);
+ }
+
+ __STATIC_INLINE uint32_t __get_APSR(void)
+ {
+ uint32_t res;
+ __asm("MRS %0,APSR" : "=r" (res));
+ return res;
+ }
+
+ #endif
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #undef __get_FPSCR
+ #undef __set_FPSCR
+ #define __get_FPSCR() (0)
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #pragma diag_suppress=Pe940
+ #pragma diag_suppress=Pe177
+
+ #define __enable_irq __enable_interrupt
+ #define __disable_irq __disable_interrupt
+ #define __NOP __no_operation
+
+ #define __get_xPSR __get_PSR
+
+ #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+ {
+ return __LDREX((unsigned long *)ptr);
+ }
+
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+ {
+ return __STREX(value, (unsigned long *)ptr);
+ }
+ #endif
+
+
+ /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+ #if (__CORTEX_M >= 0x03)
+
+ __IAR_FT uint32_t __RRX(uint32_t value)
+ {
+ uint32_t result;
+ __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value));
+ return(result);
+ }
+
+ __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
+ }
+
+
+ #define __enable_fault_irq __enable_fiq
+ #define __disable_fault_irq __disable_fiq
+
+
+ #endif /* (__CORTEX_M >= 0x03) */
+
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+ {
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+ }
+
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+ __IAR_FT uint32_t __get_MSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,MSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_MSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR MSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __get_PSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_PSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
+ {
+ __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR PSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_SP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,SP_NS" : "=r" (res));
+ return res;
+ }
+ __IAR_FT void __TZ_set_SP_NS(uint32_t value)
+ {
+ __asm volatile("MSR SP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
+ }
+
+ #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+ __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+ {
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+ }
+
+ __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+ {
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+ }
+#endif
+
+#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+ {
+ __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+ {
+ __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+ {
+ __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+ }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+
+ __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+ {
+ __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+ {
+ __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+ {
+ __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/cmsis-core/cmsis_version.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/cmsis-core/cmsis_version.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.4 + * @date 23. July 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif
diff -r 000000000000 -r 01f31e923fe2 source/cmsis-core/core_armv81mml.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/cmsis-core/core_armv81mml.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,2957 @@
+/**************************************************************************//**
+ * @file core_armv81mml.h
+ * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File
+ * @version V1.2.0
+ * @date 21. October 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV81MML_H_GENERIC
+#define __CORE_ARMV81MML_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_ARMV81MML
+ @{
+ */
+
+#include "cmsis_version.h"
+
+#define __ARM_ARCH_8M_MAIN__ 1 // patching for now
+/* CMSIS ARMV81MML definitions */
+#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \
+ __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (81U) /*!< Cortex-M Core */
+
+#if defined ( __CC_ARM )
+ #error Legacy Arm Compiler does not support Armv8.1-M target architecture.
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_MVE)
+ #if defined(__MVE_PRESENT) && (__MVE_PRESENT == 1U)
+ #define __MVE_USED 1U
+ #else
+ #error "Compiler generates MVE instructions for a devices without MVE extensions (check __MVE_PRESENT)"
+ #define __MVE_USED 0U
+ #endif
+ #else
+ #define __MVE_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_MVE)
+ #if defined(__MVE_PRESENT) && (__MVE_PRESENT == 1U)
+ #define __MVE_USED 1U
+ #else
+ #error "Compiler generates MVE instructions for a devices without MVE extensions (check __MVE_PRESENT)"
+ #define __MVE_USED 0U
+ #endif
+ #else
+ #define __MVE_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_MVE)
+ #if defined(__MVE_PRESENT) && (__MVE_PRESENT == 1U)
+ #define __MVE_USED 1U
+ #else
+ #error "Compiler generates MVE instructions for a devices without MVE extensions (check __MVE_PRESENT)"
+ #define __MVE_USED 0U
+ #endif
+ #else
+ #define __MVE_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV81MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV81MML_H_DEPENDANT
+#define __CORE_ARMV81MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __ARMv81MML_REV
+ #define __ARMv81MML_REV 0x0000U
+ #warning "__ARMv81MML_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MVE_PRESENT
+ #define __MVE_PRESENT 0U
+ #warning "__MVE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv81MML */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */
+ uint32_t RESERVED4[14U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */
+#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */
+
+#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */
+#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */
+#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */
+
+#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */
+#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */
+
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */
+#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */
+
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */
+#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */
+
+#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */
+#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */
+
+#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */
+#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */
+
+#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */
+#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */
+
+#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */
+#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */
+
+#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */
+#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */
+
+#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */
+#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */
+
+#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */
+#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */
+
+/* SCB Debug Feature Register 0 Definitions */
+#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */
+#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */
+
+#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */
+#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB RAS Fault Status Register Definitions */
+#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */
+#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */
+
+#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */
+#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */
+
+#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */
+#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[3U];
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */
+#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */
+#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */
+#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */
+
+#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */
+#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */
+#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */
+
+#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */
+#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */
+
+#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */
+#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */
+#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */
+
+#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */
+#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */
+
+#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */
+#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */
+#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */
+
+#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */
+#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */
+
+#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */
+#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */
+
+#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */
+#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */
+
+#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */
+#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */
+
+#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */
+#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
+#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< CoreDebug DHCSR: S_FPD Position */
+#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< CoreDebug DHCSR: S_FPD Mask */
+
+#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< CoreDebug DHCSR: S_SUIDE Position */
+#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< CoreDebug DHCSR: S_SUIDE Mask */
+
+#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< CoreDebug DHCSR: S_NSUIDE Position */
+#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< CoreDebug DHCSR: S_NSUIDE Mask */
+
+#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< CoreDebug DHCSR: S_SDE Position */
+#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< CoreDebug DHCSR: S_SDE Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< CoreDebug DHCSR: C_PMOV Position */
+#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< CoreDebug DHCSR: C_PMOV Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Set Clear Exception and Monitor Control Register Definitions */
+#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< CoreDebug DSCEMCR: CLR_MON_REQ, Position */
+#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< CoreDebug DSCEMCR: CLR_MON_REQ, Mask */
+
+#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< CoreDebug DSCEMCR: CLR_MON_PEND, Position */
+#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< CoreDebug DSCEMCR: CLR_MON_PEND, Mask */
+
+#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< CoreDebug DSCEMCR: SET_MON_REQ, Position */
+#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< CoreDebug DSCEMCR: SET_MON_REQ, Mask */
+
+#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< CoreDebug DSCEMCR: SET_MON_PEND, Position */
+#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< CoreDebug DSCEMCR: SET_MON_PEND, Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< CoreDebug DAUTHCTRL: UIDEN, Position */
+#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< CoreDebug DAUTHCTRL: UIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< CoreDebug DAUTHCTRL: UIDAPEN, Position */
+#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< CoreDebug DAUTHCTRL: UIDAPEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< CoreDebug DAUTHCTRL: FSDMA, Position */
+#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< CoreDebug DAUTHCTRL: FSDMA, Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV81MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r 01f31e923fe2 source/cmsis-core/core_armv8mbl.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/cmsis-core/core_armv8mbl.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1921 @@
+/**************************************************************************//**
+ * @file core_armv8mbl.h
+ * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
+ * @version V5.0.8
+ * @date 12. November 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MBL_H_GENERIC
+#define __CORE_ARMV8MBL_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_ARMv8MBL
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS definitions */
+#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+ __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M ( 2U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT
+#define __CORE_ARMV8MBL_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __ARMv8MBL_REV
+ #define __ARMv8MBL_REV 0x0000U
+ #warning "__ARMv8MBL_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ETM_PRESENT
+ #define __ETM_PRESENT 0U
+ #warning "__ETM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MTB_PRESENT
+ #define __MTB_PRESENT 0U
+ #warning "__MTB_PRESENT not defined in device header file; using default!"
+ #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ uint32_t RESERVED0[6U];
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ uint32_t RESERVED0[7U];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r 01f31e923fe2 source/cmsis-core/core_armv8mml.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/cmsis-core/core_armv8mml.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,2835 @@
+/**************************************************************************//**
+ * @file core_armv8mml.h
+ * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
+ * @version V5.1.0
+ * @date 12. September 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MML_H_GENERIC
+#define __CORE_ARMV8MML_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_ARMv8MML
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS Armv8MML definitions */
+#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+ __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (81U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MML_H_DEPENDANT
+#define __CORE_ARMV8MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __ARMv8MML_REV
+ #define __ARMv8MML_REV 0x0000U
+ #warning "__ARMv8MML_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r 01f31e923fe2 source/cmsis-core/core_cm0.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/cmsis-core/core_cm0.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,952 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V5.0.8
+ * @date 21. August 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M0
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (0U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0_REV
+ #define __CM0_REV 0x0000U
+ #warning "__CM0_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ Address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
+ *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
+ /* ARM Application Note 321 states that the M0 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
+ return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r 01f31e923fe2 source/cmsis-core/core_cm0plus.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/cmsis-core/core_cm0plus.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1087 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V5.0.9
+ * @date 21. August 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex-M0+
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (0U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000U
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0+ header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+#else
+ uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
+ *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
+#endif
+ /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+#else
+ uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
+ return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
+#endif
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r 01f31e923fe2 source/cmsis-core/core_cm1.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/cmsis-core/core_cm1.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,979 @@
+/**************************************************************************//**
+ * @file core_cm1.h
+ * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
+ * @version V1.0.1
+ * @date 12. November 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM1_H_GENERIC
+#define __CORE_CM1_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M1
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM1 definitions */
+#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
+ __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (1U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM1_H_DEPENDANT
+#define __CORE_CM1_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM1_REV
+ #define __CM1_REV 0x0100U
+ #warning "__CM1_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M1 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
+
+#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M1 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ Address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M1 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r 01f31e923fe2 source/cmsis-core/core_cm23.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/cmsis-core/core_cm23.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1996 @@
+/**************************************************************************//**
+ * @file core_cm23.h
+ * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version V5.0.8
+ * @date 12. November 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M23
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS definitions */
+#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+ __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (23U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM23_REV
+ #define __CM23_REV 0x0000U
+ #warning "__CM23_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ETM_PRESENT
+ #define __ETM_PRESENT 0U
+ #warning "__ETM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MTB_PRESENT
+ #define __MTB_PRESENT 0U
+ #warning "__MTB_PRESENT not defined in device header file; using default!"
+ #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ uint32_t RESERVED0[6U];
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ uint32_t RESERVED0[7U];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r 01f31e923fe2 source/cmsis-core/core_cm3.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/cmsis-core/core_cm3.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1938 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V5.1.1
+ * @date 19. August 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M3
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (3U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200U
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+#endif
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M3 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r 01f31e923fe2 source/cmsis-core/core_cm33.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/cmsis-core/core_cm33.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,2910 @@
+/**************************************************************************//**
+ * @file core_cm33.h
+ * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version V5.1.0
+ * @date 12. November 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M33
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+ __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (33U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined (__TARGET_FPU_VFP)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined (__ARM_FP)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined (__ARMVFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined (__TI_VFP_SUPPORT__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined (__FPU_VFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM33_REV
+ #define __CM33_REV 0x0000U
+ #warning "__CM33_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r 01f31e923fe2 source/cmsis-core/core_cm35p.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/cmsis-core/core_cm35p.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,2910 @@
+/**************************************************************************//**
+ * @file core_cm35p.h
+ * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File
+ * @version V1.0.0
+ * @date 12. November 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM35P_H_GENERIC
+#define __CORE_CM35P_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M35P
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM35P definitions */
+#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \
+ __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (35U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined (__TARGET_FPU_VFP)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined (__ARM_FP)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined (__ARMVFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined (__TI_VFP_SUPPORT__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined (__FPU_VFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM35P_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM35P_H_DEPENDANT
+#define __CORE_CM35P_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM35P_REV
+ #define __CM35P_REV 0x0000U
+ #warning "__CM35P_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M35P */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM35P_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r 01f31e923fe2 source/cmsis-core/core_cm4.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/cmsis-core/core_cm4.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,2124 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V5.1.1
+ * @date 19. August 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M4
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (4U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000U
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
+#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M4 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r 01f31e923fe2 source/cmsis-core/core_cm7.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/cmsis-core/core_cm7.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,2725 @@
+/**************************************************************************//**
+ * @file core_cm7.h
+ * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version V5.1.2
+ * @date 19. August 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M7
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+ __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (7U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM7_REV
+ #define __CM7_REV 0x0000U
+ #warning "__CM7_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ICACHE_PRESENT
+ #define __ICACHE_PRESENT 0U
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DCACHE_PRESENT
+ #define __DCACHE_PRESENT 0U
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DTCM_PRESENT
+ #define __DTCM_PRESENT 0U
+ #warning "__DTCM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[1U];
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED3[93U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */
+#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */
+
+#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */
+#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */
+
+#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */
+#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */
+
+#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */
+#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */
+
+#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */
+#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */
+
+#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */
+#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */
+
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED3[981U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
+#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = SCB->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## Cache functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions
+ \brief Functions that configure Instruction and Data cache.
+ @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
+
+#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+
+/**
+ \brief Enable I-Cache
+ \details Turns on I-Cache
+ */
+__STATIC_FORCEINLINE void SCB_EnableICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
+
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable I-Cache
+ \details Turns off I-Cache
+ */
+__STATIC_FORCEINLINE void SCB_DisableICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate I-Cache
+ \details Invalidates I-Cache
+ */
+__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL;
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief I-Cache Invalidate by address
+ \details Invalidates I-Cache for the given address.
+ I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+ I-Cache memory blocks which are part of given address + given size are invalidated.
+ \param[in] addr address
+ \param[in] isize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ if ( isize > 0 ) {
+ int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_ICACHE_LINE_SIZE;
+ op_size -= __SCB_ICACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+
+/**
+ \brief Enable D-Cache
+ \details Turns on D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_EnableDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+ __DSB();
+
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable D-Cache
+ \details Turns off D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_DisableDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate D-Cache
+ \details Invalidates D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean D-Cache
+ \details Cleans D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_CleanDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean & Invalidate D-Cache
+ \details Cleans and Invalidates D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Invalidate by address
+ \details Invalidates D-Cache for the given address.
+ D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+ D-Cache memory blocks which are part of given address + given size are invalidated.
+ \param[in] addr address
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if ( dsize > 0 ) {
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_DCACHE_LINE_SIZE;
+ op_size -= __SCB_DCACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean by address
+ \details Cleans D-Cache for the given address
+ D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
+ D-Cache memory blocks which are part of given address + given size are cleaned.
+ \param[in] addr address
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if ( dsize > 0 ) {
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_DCACHE_LINE_SIZE;
+ op_size -= __SCB_DCACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean and Invalidate by address
+ \details Cleans and invalidates D_Cache for the given address
+ D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
+ D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if ( dsize > 0 ) {
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_DCACHE_LINE_SIZE;
+ op_size -= __SCB_DCACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r 01f31e923fe2 source/cmsis-core/core_sc000.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/cmsis-core/core_sc000.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1025 @@
+/**************************************************************************//**
+ * @file core_sc000.h
+ * @brief CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version V5.0.7
+ * @date 19. August 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup SC000
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+ __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC (000U) /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC000_REV
+ #define __SC000_REV 0x0000U
+ #warning "__SC000_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ uint32_t RESERVED1[154U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the SC000 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r 01f31e923fe2 source/cmsis-core/core_sc300.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/cmsis-core/core_sc300.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1912 @@
+/**************************************************************************//**
+ * @file core_sc300.h
+ * @brief CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version V5.0.9
+ * @date 19. August 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup SC3000
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+ __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC (300U) /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC300_REV
+ #define __SC300_REV 0x0000U
+ #warning "__SC300_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED1[129U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M3 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff -r 000000000000 -r 01f31e923fe2 source/cmsis-core/mpu_armv7.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/cmsis-core/mpu_armv7.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,272 @@
+/******************************************************************************
+ * @file mpu_armv7.h
+ * @brief CMSIS MPU API for Armv7-M MPU
+ * @version V5.1.0
+ * @date 08. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
+ ((Region) & MPU_RBAR_REGION_Msk) | \
+ (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+*
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
+ ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
+ (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
+ (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
+ (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
+ ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
+ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
+ (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
+ (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
+ (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
+ (((MPU_RASR_ENABLE_Msk))))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+* - TEX: 000b
+* - Shareable
+* - Non-cacheable
+* - Non-bufferable
+*/
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+* - TEX: 000b (if shareable) or 010b (if non-shareable)
+* - Shareable or non-shareable
+* - Non-cacheable
+* - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+* - TEX: 1BBb (reflecting outer cacheability rules)
+* - Shareable or non-shareable
+* - Cacheable or non-cacheable (reflecting inner cacheability rules)
+* - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+ uint32_t RBAR; //!< The region base address register value (RBAR)
+ uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ __DSB();
+ __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+ __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ MPU->RNR = rnr;
+ MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+ MPU->RNR = rnr;
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0U; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+ while (cnt > MPU_TYPE_RALIASES) {
+ ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+ table += MPU_TYPE_RALIASES;
+ cnt -= MPU_TYPE_RALIASES;
+ }
+ ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/cmsis-core/mpu_armv8.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/cmsis-core/mpu_armv8.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,346 @@
+/******************************************************************************
+ * @file mpu_armv8.h
+ * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
+ * @version V5.1.1
+ * @date 09. August 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+ ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable */
+#define ARM_MPU_SH_NON (0U)
+
+/** \brief Normal memory outer shareable */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+ (((BASE) & MPU_RBAR_BASE_Msk) | \
+ (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+ (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+ (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+ (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+ (MPU_RLAR_EN_Msk))
+
+#if defined(MPU_RLAR_PXN_Pos)
+
+/** \brief Region Limit Address Register with PXN value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
+ (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+ (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
+ (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+ (MPU_RLAR_EN_Msk))
+
+#endif
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+ uint32_t RBAR; /*!< Region Base Address Register value */
+ uint32_t RLAR; /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ __DSB();
+ __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+ __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+ MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ __DSB();
+ __ISB();
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+ __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+ const uint8_t reg = idx / 4U;
+ const uint32_t pos = ((idx % 4U) * 8U);
+ const uint32_t mask = 0xFFU << pos;
+
+ if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+ return; // invalid index
+ }
+
+ mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+ ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+ ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+ mpu->RNR = rnr;
+ mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{
+ ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ mpu->RNR = rnr;
+ mpu->RBAR = rbar;
+ mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0U; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+ if (cnt == 1U) {
+ mpu->RNR = rnr;
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+ } else {
+ uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
+ uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+
+ mpu->RNR = rnrBase;
+ while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+ uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+ table += c;
+ cnt -= c;
+ rnrOffset = 0U;
+ rnrBase += MPU_TYPE_RALIASES;
+ mpu->RNR = rnrBase;
+ }
+
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+
diff -r 000000000000 -r 01f31e923fe2 source/cmsis-core/tz_context.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/cmsis-core/tz_context.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include <stdint.h> + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H
diff -r 000000000000 -r 01f31e923fe2 source/daplink/HardFault_Handler.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/HardFault_Handler.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,78 @@
+/**
+ * @file main.c
+ * @brief Entry point for interface program logic
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2018, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#include "settings.h"
+#include "util.h"
+#include "cortex_m.h"
+
+register unsigned int _psp __asm("psp");
+register unsigned int _msp __asm("msp");
+register unsigned int _lr __asm("lr");
+register unsigned int _control __asm("control");
+void HardFault_Handler()
+{
+//hexdump logic on hardfault
+ uint32_t stk_ptr;
+ uint32_t * stack = (uint32_t *)_msp;
+
+ if ((_lr & 0xF) == 0xD) { //process stack
+ stack = (uint32_t *)_psp;
+ }
+
+ //calculate stack ptr before fault
+ stk_ptr = (uint32_t)stack + 0x20;
+ if ((stack[7] & 0x200) != 0) { //xpsr bit 9 align
+ stk_ptr += 0x4;
+ }
+ if ((_lr & 0x10) == 0) { //fp
+ stk_ptr += 0x48;
+ }
+
+ config_ram_add_hexdump(_lr); //EXC_RETURN
+ config_ram_add_hexdump(_psp);
+ config_ram_add_hexdump(_msp);
+ config_ram_add_hexdump(_control);
+ config_ram_add_hexdump(stk_ptr); //SP
+ config_ram_add_hexdump(stack[5]); //LR
+ config_ram_add_hexdump(stack[6]); //PC
+ config_ram_add_hexdump(stack[7]); //xPSR
+
+#ifndef __CORTEX_M
+#error __CORTEX_M not defined!!
+#else
+
+#if (__CORTEX_M > 0x00)
+ config_ram_add_hexdump(SCB->HFSR);
+ config_ram_add_hexdump(SCB->CFSR);
+ config_ram_add_hexdump(SCB->DFSR);
+ config_ram_add_hexdump(SCB->AFSR);
+ config_ram_add_hexdump(SCB->MMFAR);
+ config_ram_add_hexdump(SCB->BFAR);
+#endif
+
+#endif //#ifndef __CORTEX_M
+
+ util_assert(0);
+ SystemReset();
+
+ while (1); // Wait for reset
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/bootloader.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/bootloader.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,36 @@
+/**
+ * @file bootloader.h
+ * @brief Information about different Hardware Interface Circuits the firmware runs
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef BOOTLOADER_H
+#define BOOTLOADER_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Check to see if an update should be applied and if so apply it
+void bootloader_check_and_update(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/bootloader/SVC_Table.s --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/daplink/bootloader/SVC_Table.s Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,38 @@ +;/** +; * @file SVC_Table.s +; * @brief SVC functions +; * +; * DAPLink Interface Firmware +; * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + AREA SVC_TABLE, CODE, READONLY + + EXPORT SVC_Count + +SVC_Cnt EQU (SVC_End-SVC_Table)/4 +SVC_Count DCD SVC_Cnt + +; Import user SVC functions here. + + + EXPORT SVC_Table +SVC_Table +; Insert user SVC functions here. SVC 0 used by RTL Kernel. + +SVC_End + + END
diff -r 000000000000 -r 01f31e923fe2 source/daplink/bootloader/daplink.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/bootloader/daplink.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,41 @@
+/**
+ * @file daplink.c
+ * @brief Implementation of daplink.h for the bootloader application
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "daplink.h"
+#include "virtual_fs.h"
+#include "compiler.h"
+
+COMPILER_ASSERT(DAPLINK_BUILD_KEY == DAPLINK_BUILD_KEY_BL);
+
+// daplink_mode_file_name, daplink_url_name and
+// daplink_drive_name strings must be 11 characters
+// excluding the null terminated character
+const char daplink_mode_file_name[11] = "START_IFACT";
+
+bool daplink_is_bootloader()
+{
+ return true;
+}
+
+bool daplink_is_interface()
+{
+ return false;
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/bootloader/main.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/bootloader/main.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,253 @@
+/**
+ * @file main.c
+ * @brief DAPLink Bootloader application entry point
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "main.h"
+#include "gpio.h"
+#include "validation.h"
+#include "vfs_manager.h"
+#include "cmsis_os2.h"
+#include "rl_usb.h"
+#include "settings.h"
+#include "info.h"
+#include "target_config.h"
+#include "util.h"
+#include "cortex_m.h"
+#include "sdk.h"
+#include "target_board.h"
+
+//default msc led settings
+#ifndef MSC_LED_DEF
+#define MSC_LED_DEF GPIO_LED_ON
+#endif
+
+__asm void modify_stack_pointer_and_start_app(uint32_t r0_sp, uint32_t r1_pc)
+{
+ MOV SP, R0
+ BX R1
+}
+
+// Event flags for main task
+// Timers events
+#define FLAGS_MAIN_90MS (1 << 0)
+#define FLAGS_MAIN_30MS (1 << 1)
+// USB Events
+#define FLAGS_MAIN_PROC_USB (1 << 9)
+// Used by msc when flashing a new binary
+#define FLAGS_LED_BLINK_30MS (1 << 6)
+
+// Timing constants (in 90mS ticks)
+// USB busy time
+#define USB_BUSY_TIME (33)
+// Delay before a USB device connect may occur
+#define USB_CONNECT_DELAY (11)
+// Decrement to zero
+#define DECZERO(x) (x ? --x : 0)
+#define NO_TIMEOUT (0xffff)
+
+// Global state of usb used in
+main_usb_connect_t usb_state;
+
+// Reference to our main task
+osThreadId_t main_task_id;
+
+static uint8_t msc_led_usb_activity = 0;
+static main_led_state_t msc_led_state = MAIN_LED_FLASH;
+
+static main_usb_busy_t usb_busy;
+static uint32_t usb_busy_count;
+
+// Timer task, set flags every 30mS and 90mS
+void timer_task_30mS(void * arg)
+{
+ static uint32_t i = 0;
+ osThreadFlagsSet(main_task_id, FLAGS_MAIN_30MS);
+ if (!(i++ % 3)) {
+ osThreadFlagsSet(main_task_id, FLAGS_MAIN_90MS);
+ }
+}
+
+// Flash MSC LED using 30mS tick
+void main_blink_msc_led(main_led_state_t state)
+{
+ msc_led_usb_activity = 1;
+ msc_led_state = state;
+ return;
+}
+
+void USBD_SignalHandler()
+{
+ osThreadFlagsSet(main_task_id, FLAGS_MAIN_PROC_USB);
+}
+
+void main_task(void * arg)
+{
+ // State processing
+ uint16_t flags;
+ // LED
+ gpio_led_state_t msc_led_value = MSC_LED_DEF;
+ // USB
+ uint32_t usb_state_count;
+
+ if (config_ram_get_initial_hold_in_bl()) {
+ // Delay for 1 second for VMs
+ osDelay(100);
+ }
+
+ // Get a reference to this task
+ main_task_id = osThreadGetId();
+ // Set LED defaults
+ gpio_set_hid_led(GPIO_LED_OFF);
+ gpio_set_cdc_led(GPIO_LED_OFF);
+ gpio_set_msc_led(msc_led_value);
+ // Update version information file
+ info_init();
+ // USB
+ usbd_init();
+ vfs_mngr_init(true);
+ usbd_connect(0);
+ usb_busy = MAIN_USB_IDLE;
+ usb_busy_count = 0;
+ usb_state = MAIN_USB_CONNECTING;
+ usb_state_count = USB_CONNECT_DELAY;
+ // Start timer tasks
+ osTimerId_t tmr_id = osTimerNew(timer_task_30mS, osTimerPeriodic, NULL, NULL);
+ osTimerStart(tmr_id, 3);
+
+ while (1) {
+ // need to create a new event for programming failure
+ flags = osThreadFlagsWait(FLAGS_MAIN_90MS // 90mS tick
+ | FLAGS_MAIN_30MS // 30mS tick
+ | FLAGS_MAIN_PROC_USB // process usb events
+ , osFlagsWaitAny,
+ osWaitForever);
+
+ if (flags & FLAGS_MAIN_PROC_USB) {
+ USBD_Handler();
+ }
+
+ if (flags & FLAGS_MAIN_90MS) {
+ vfs_mngr_periodic(90); // FLAGS_MAIN_90MS
+
+ // Update USB busy status
+ switch (usb_busy) {
+ case MAIN_USB_ACTIVE:
+ if (DECZERO(usb_busy_count) == 0) {
+ usb_busy = MAIN_USB_IDLE;
+ }
+
+ break;
+
+ case MAIN_USB_IDLE:
+ default:
+ break;
+ }
+
+ // Update USB connect status
+ switch (usb_state) {
+ case MAIN_USB_DISCONNECTING:
+
+ // Wait until USB is idle before disconnecting
+ if (usb_busy == MAIN_USB_IDLE && (DECZERO(usb_state_count) == 0)) {
+ usbd_connect(0);
+ usb_state = MAIN_USB_DISCONNECTED;
+ }
+
+ break;
+
+ case MAIN_USB_CONNECTING:
+
+ // Wait before connecting
+ if (DECZERO(usb_state_count) == 0) {
+ usbd_connect(1);
+ usb_state = MAIN_USB_CHECK_CONNECTED;
+ }
+
+ break;
+
+ case MAIN_USB_CHECK_CONNECTED:
+ if (usbd_configured()) {
+ usb_state = MAIN_USB_CONNECTED;
+ }
+
+ break;
+
+ case MAIN_USB_DISCONNECTED:
+ SystemReset();
+ break;
+
+ case MAIN_USB_CONNECTED:
+ default:
+ break;
+ }
+ }
+
+ // 30mS tick used for flashing LED when USB is busy
+ if (flags & FLAGS_MAIN_30MS) {
+ if (msc_led_usb_activity) {
+
+ if ((msc_led_state == MAIN_LED_FLASH) || (msc_led_state == MAIN_LED_FLASH_PERMANENT)) {
+ // Toggle LED value
+ msc_led_value = (GPIO_LED_ON == msc_led_value) ? GPIO_LED_OFF : GPIO_LED_ON;
+ // If in flash mode stop after one cycle but in bootloader LED stays on
+ if ((MSC_LED_DEF == msc_led_value) && (MAIN_LED_FLASH == msc_led_state)) {
+ msc_led_usb_activity = 0;
+ msc_led_state = MAIN_LED_DEF;
+ }
+
+ }else{
+ //LED next state is MAIN_LED_DEF
+ msc_led_value = MSC_LED_DEF;
+ msc_led_usb_activity = 0;
+ }
+
+ // Update hardware
+ gpio_set_msc_led(msc_led_value);
+ }
+ }
+ }
+}
+
+int main(void)
+{
+ // initialize vendor sdk
+ sdk_init();
+ // init leds and button
+ gpio_init();
+ // init settings
+ config_init();
+
+ // check for invalid app image or rst button press. Should be checksum or CRC but NVIC validation is better than nothing.
+ // If the interface has set the hold in bootloader setting don't jump to app
+ if (!gpio_get_reset_btn() && g_board_info.target_cfg && validate_bin_nvic((uint8_t *)g_board_info.target_cfg->flash_regions[0].start) && !config_ram_get_initial_hold_in_bl()) {
+ // change to the new vector table
+ SCB->VTOR = g_board_info.target_cfg->flash_regions[0].start; //bootloaders should only have one flash region for interface
+ // modify stack pointer and start app
+ modify_stack_pointer_and_start_app((*(uint32_t *)(g_board_info.target_cfg->flash_regions[0].start)), (*(uint32_t *)(g_board_info.target_cfg->flash_regions[0].start + 4)));
+ }
+
+ // config the usb interface descriptor and web auth token before USB connects
+ //unique_string_auth_config();
+ // either the rst pin was pressed or we have an empty app region
+ osKernelInitialize(); // Initialize CMSIS-RTOS
+ osThreadNew(main_task, NULL, NULL); // Create application main thread
+ osKernelStart(); // Start thread execution
+ for (;;) {}
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/bootloader/main.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/bootloader/main.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,94 @@
+/**
+ * @file main.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MAIN_H
+#define MAIN_H
+
+#include <stdint.h>
+
+/**
+ * @enum main_usb_busy_t
+ * @brief Defines the filtered activity of the USB connection
+ */
+typedef enum {
+ MAIN_USB_IDLE, /*!< MAIN_USB_IDLE value means no bus activity */
+ MAIN_USB_ACTIVE /*!< MAIN_USB_ACTIVE value means MSC transfers are occuring */
+} main_usb_busy_t;
+
+/**
+ * @enum main_usb_connect_t
+ * @brief State the USB connection can be in
+ */
+typedef enum {
+ MAIN_USB_DISCONNECTED, /*!< MAIN_USB_DISCONNECTED state for a USB */
+ MAIN_USB_CONNECTING, /*!< MAIN_USB_CONNECTING state for a USB */
+ MAIN_USB_CONNECTED, /*!< MAIN_USB_CONNECTED state for a USB */
+ MAIN_USB_CHECK_CONNECTED, /*!< MAIN_USB_CHECK_CONNECTED state for a USB */
+ MAIN_USB_DISCONNECTING /*!< MAIN_USB_DISCONNECTING state for a USB */
+} main_usb_connect_t;
+
+/**
+ * @enum main_led_state_t
+ * @brief Statest the USB connection can be in
+ */
+typedef enum {
+ MAIN_LED_DEF = 0,
+ MAIN_LED_FLASH,
+ MAIN_LED_FLASH_PERMANENT
+} main_led_state_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Allows other parts of the program to request the device to eject physical media
+ * @param none
+ * @return none
+ */
+void main_msc_disconnect_event(void);
+
+/**
+ * Delay the disconnect if there is one in progress
+ * @param none
+ * @return none
+ */
+void main_msc_delay_disconnect_event(void);
+
+/**
+ * Allows other parts of the program to request the device to immediately eject physical media
+ * @param none
+ * @return none
+ */
+void main_force_msc_disconnect_event(void);
+
+/**
+ * Allows other parts of the program to request a LED to toggle state
+ * @param permanent decides if the led should remain on or flash
+ * @return none
+ */
+void main_blink_msc_led(main_led_state_t permanent);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/circ_buf.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/circ_buf.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,136 @@
+/**
+ * @file circular_buffer.c
+ * @brief Implementation of a circular buffer
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2016-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "circ_buf.h"
+
+#include "cortex_m.h"
+#include "util.h"
+
+void circ_buf_init(circ_buf_t *circ_buf, uint8_t *buffer, uint32_t size)
+{
+ cortex_int_state_t state;
+ state = cortex_int_get_and_disable();
+
+ circ_buf->buf = buffer;
+ circ_buf->size = size;
+ circ_buf->head = 0;
+ circ_buf->tail = 0;
+
+ cortex_int_restore(state);
+}
+
+void circ_buf_push(circ_buf_t *circ_buf, uint8_t data)
+{
+ cortex_int_state_t state;
+ state = cortex_int_get_and_disable();
+
+ circ_buf->buf[circ_buf->tail] = data;
+ circ_buf->tail += 1;
+ if (circ_buf->tail >= circ_buf->size) {
+ util_assert(circ_buf->tail == circ_buf->size);
+ circ_buf->tail = 0;
+ }
+
+ // Assert no overflow
+ util_assert(circ_buf->head != circ_buf->tail);
+
+ cortex_int_restore(state);
+}
+
+uint8_t circ_buf_pop(circ_buf_t *circ_buf)
+{
+ uint8_t data;
+ cortex_int_state_t state;
+
+ state = cortex_int_get_and_disable();
+
+ // Assert buffer isn't empty
+ util_assert(circ_buf->head != circ_buf->tail);
+
+ data = circ_buf->buf[circ_buf->head];
+ circ_buf->head += 1;
+ if (circ_buf->head >= circ_buf->size) {
+ util_assert(circ_buf->head == circ_buf->size);
+ circ_buf->head = 0;
+ }
+
+ cortex_int_restore(state);
+
+ return data;
+}
+
+uint32_t circ_buf_count_used(circ_buf_t *circ_buf)
+{
+ uint32_t cnt;
+ cortex_int_state_t state;
+
+ state = cortex_int_get_and_disable();
+
+ if (circ_buf->tail >= circ_buf->head) {
+ cnt = circ_buf->tail - circ_buf->head;
+ } else {
+ cnt = circ_buf->tail + circ_buf->size - circ_buf->head;
+ }
+
+ cortex_int_restore(state);
+ return cnt;
+}
+
+uint32_t circ_buf_count_free(circ_buf_t *circ_buf)
+{
+ uint32_t cnt;
+ cortex_int_state_t state;
+
+ state = cortex_int_get_and_disable();
+
+ cnt = circ_buf->size - circ_buf_count_used(circ_buf) - 1;
+
+ cortex_int_restore(state);
+ return cnt;
+}
+
+uint32_t circ_buf_read(circ_buf_t *circ_buf, uint8_t *data, uint32_t size)
+{
+ uint32_t cnt;
+ uint32_t i;
+
+ cnt = circ_buf_count_used(circ_buf);
+ cnt = MIN(size, cnt);
+ for (i = 0; i < cnt; i++) {
+ data[i] = circ_buf_pop(circ_buf);
+ }
+
+ return cnt;
+}
+
+uint32_t circ_buf_write(circ_buf_t *circ_buf, const uint8_t *data, uint32_t size)
+{
+ uint32_t cnt;
+ uint32_t i;
+
+ cnt = circ_buf_count_free(circ_buf);
+ cnt = MIN(size, cnt);
+ for (i = 0; i < cnt; i++) {
+ circ_buf_push(circ_buf, data[i]);
+ }
+
+ return cnt;
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/circ_buf.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/circ_buf.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,64 @@
+/**
+ * @file circ_buf.h
+ * @brief Implementation of a circular buffer
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2016-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef CIRC_BUF_H
+#define CIRC_BUF_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ uint32_t head;
+ uint32_t tail;
+ uint32_t size;
+ uint8_t *buf;
+} circ_buf_t;
+
+// Initialize or reinitialize a circular buffer
+void circ_buf_init(circ_buf_t *circ_buf, uint8_t *buffer, uint32_t size);
+
+// Push a byte into the circular buffer
+void circ_buf_push(circ_buf_t *circ_buf, uint8_t data);
+
+// Return a byte from the circular buffer
+uint8_t circ_buf_pop(circ_buf_t *circ_buf);
+
+// Get the number of bytes in the circular buffer
+uint32_t circ_buf_count_used(circ_buf_t *circ_buf);
+
+// Get the number of free spots left in the circular buffer
+uint32_t circ_buf_count_free(circ_buf_t *circ_buf);
+
+// Attempt to read size bytes from the buffer. Return the number of bytes read
+uint32_t circ_buf_read(circ_buf_t *circ_buf, uint8_t *data, uint32_t size);
+
+// Attempt to write size bytes to the buffer. Return the number of bytes written
+uint32_t circ_buf_write(circ_buf_t *circ_buf, const uint8_t *data, uint32_t size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/cmsis-dap/DAP.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/cmsis-dap/DAP.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1795 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ * Copyright 2019, Cypress Semiconductor Corporation
+ * or a subsidiary of Cypress Semiconductor Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date: 1. December 2017
+ * $Revision: V2.0.0
+ *
+ * Project: CMSIS-DAP Source
+ * Title: DAP.c CMSIS-DAP Commands
+ *
+ *---------------------------------------------------------------------------*/
+
+#include <string.h>
+#ifdef RTE_CMSIS_RTOS
+#include "cmsis_os.h"
+#endif
+#include "DAP_config.h"
+#include "DAP.h"
+#include "info.h"
+#include "dap_strings.h"
+
+
+#if (DAP_PACKET_SIZE < 64U)
+#error "Minimum Packet Size is 64!"
+#endif
+#if (DAP_PACKET_SIZE > 32768U)
+#error "Maximum Packet Size is 32768!"
+#endif
+#if (DAP_PACKET_COUNT < 1U)
+#error "Minimum Packet Count is 1!"
+#endif
+#if (DAP_PACKET_COUNT > 255U)
+#error "Maximum Packet Count is 255!"
+#endif
+
+
+// Clock Macros
+
+#define MAX_SWJ_CLOCK(delay_cycles) \
+ ((CPU_CLOCK/2U) / (IO_PORT_WRITE_CYCLES + delay_cycles))
+
+#define CLOCK_DELAY(swj_clock) \
+ (((CPU_CLOCK/2U) / swj_clock) - IO_PORT_WRITE_CYCLES)
+
+
+ DAP_Data_t DAP_Data; // DAP Data
+volatile uint8_t DAP_TransferAbort; // Transfer Abort Flag
+
+
+// static const char DAP_FW_Ver [] = DAP_FW_VER;
+
+#if TARGET_DEVICE_FIXED
+static const char TargetDeviceVendor [] = TARGET_DEVICE_VENDOR;
+static const char TargetDeviceName [] = TARGET_DEVICE_NAME;
+#endif
+
+
+// Get DAP Information
+// id: info identifier
+// info: pointer to info data
+// return: number of bytes in info data
+static uint8_t DAP_Info(uint8_t id, uint8_t *info) {
+ uint8_t length = 0U;
+
+ switch (id) {
+ case DAP_ID_VENDOR:
+ length = DAP_GetVendorString((char *)info);
+ break;
+ case DAP_ID_PRODUCT:
+ length = DAP_GetProductString((char *)info);
+ break;
+ case DAP_ID_SER_NUM:
+ length = DAP_GetSerNumString((char *)info);
+ break;
+ case DAP_ID_FW_VER: {
+// --- begin DAPLink change ---
+ length = DAP_GetFirmwareVersionString((char *)info);
+// Original:
+// memcpy(info, DAP_FW_Ver, sizeof(DAP_FW_Ver));
+// length = (uint8_t)sizeof(DAP_FW_Ver);
+// --- end DAPLink change ---
+ break;
+ }
+ case DAP_ID_DEVICE_VENDOR:
+#if TARGET_DEVICE_FIXED
+ length = (uint8_t)sizeof(TargetDeviceVendor);
+ memcpy(info, TargetDeviceVendor, length);
+#endif
+ break;
+ case DAP_ID_DEVICE_NAME:
+#if TARGET_DEVICE_FIXED
+ length = (uint8_t)sizeof(TargetDeviceName);
+ memcpy(info, TargetDeviceName, length);
+#endif
+ break;
+ case DAP_ID_CAPABILITIES:
+ info[0] = ((DAP_SWD != 0) ? (1U << 0) : 0U) |
+ ((DAP_JTAG != 0) ? (1U << 1) : 0U) |
+ ((SWO_UART != 0) ? (1U << 2) : 0U) |
+ ((SWO_MANCHESTER != 0) ? (1U << 3) : 0U) |
+ /* Atomic Commands */ (1U << 4) |
+ ((TIMESTAMP_CLOCK != 0U) ? (1U << 5) : 0U) |
+ ((SWO_STREAM != 0U) ? (1U << 6) : 0U);
+ length = 1U;
+ break;
+ case DAP_ID_TIMESTAMP_CLOCK:
+#if (TIMESTAMP_CLOCK != 0U)
+ info[0] = (uint8_t)(TIMESTAMP_CLOCK >> 0);
+ info[1] = (uint8_t)(TIMESTAMP_CLOCK >> 8);
+ info[2] = (uint8_t)(TIMESTAMP_CLOCK >> 16);
+ info[3] = (uint8_t)(TIMESTAMP_CLOCK >> 24);
+ length = 4U;
+#endif
+ break;
+ case DAP_ID_SWO_BUFFER_SIZE:
+#if ((SWO_UART != 0) || (SWO_MANCHESTER != 0))
+ info[0] = (uint8_t)(SWO_BUFFER_SIZE >> 0);
+ info[1] = (uint8_t)(SWO_BUFFER_SIZE >> 8);
+ info[2] = (uint8_t)(SWO_BUFFER_SIZE >> 16);
+ info[3] = (uint8_t)(SWO_BUFFER_SIZE >> 24);
+ length = 4U;
+#endif
+ break;
+ case DAP_ID_PACKET_SIZE:
+ info[0] = (uint8_t)(DAP_PACKET_SIZE >> 0);
+ info[1] = (uint8_t)(DAP_PACKET_SIZE >> 8);
+ length = 2U;
+ break;
+ case DAP_ID_PACKET_COUNT:
+ info[0] = DAP_PACKET_COUNT;
+ length = 1U;
+ break;
+ default:
+ break;
+ }
+
+ return (length);
+}
+
+
+// Delay for specified time
+// delay: delay time in ms
+void Delayms(uint32_t delay) {
+ delay *= ((CPU_CLOCK/1000U) + (DELAY_SLOW_CYCLES-1U)) / DELAY_SLOW_CYCLES;
+ PIN_DELAY_SLOW(delay);
+}
+
+
+// Process Delay command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+static uint32_t DAP_Delay(const uint8_t *request, uint8_t *response) {
+ uint32_t delay;
+
+ delay = (uint32_t)(*(request+0)) |
+ (uint32_t)(*(request+1) << 8);
+ delay *= ((CPU_CLOCK/1000000U) + (DELAY_SLOW_CYCLES-1U)) / DELAY_SLOW_CYCLES;
+
+ PIN_DELAY_SLOW(delay);
+
+ *response = DAP_OK;
+ return ((2U << 16) | 1U);
+}
+
+
+// Process Host Status command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+static uint32_t DAP_HostStatus(const uint8_t *request, uint8_t *response) {
+
+ switch (*request) {
+ case DAP_DEBUGGER_CONNECTED:
+ LED_CONNECTED_OUT((*(request+1) & 1U));
+ break;
+ case DAP_TARGET_RUNNING:
+ LED_RUNNING_OUT((*(request+1) & 1U));
+ break;
+ default:
+ *response = DAP_ERROR;
+ return ((2U << 16) | 1U);
+ }
+
+ *response = DAP_OK;
+ return ((2U << 16) | 1U);
+}
+
+
+// Process Connect command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+static uint32_t DAP_Connect(const uint8_t *request, uint8_t *response) {
+ uint32_t port;
+
+ if (*request == DAP_PORT_AUTODETECT) {
+ port = DAP_DEFAULT_PORT;
+ } else {
+ port = *request;
+ }
+
+ switch (port) {
+#if (DAP_SWD != 0)
+ case DAP_PORT_SWD:
+ DAP_Data.debug_port = DAP_PORT_SWD;
+ PORT_SWD_SETUP();
+ break;
+#endif
+#if (DAP_JTAG != 0)
+ case DAP_PORT_JTAG:
+ DAP_Data.debug_port = DAP_PORT_JTAG;
+ PORT_JTAG_SETUP();
+ break;
+#endif
+ default:
+ port = DAP_PORT_DISABLED;
+ break;
+ }
+
+ *response = (uint8_t)port;
+ return ((1U << 16) | 1U);
+}
+
+
+// Process Disconnect command and prepare response
+// response: pointer to response data
+// return: number of bytes in response
+static uint32_t DAP_Disconnect(uint8_t *response) {
+
+ DAP_Data.debug_port = DAP_PORT_DISABLED;
+ PORT_OFF();
+
+ *response = DAP_OK;
+ return (1U);
+}
+
+
+// Process Reset Target command and prepare response
+// response: pointer to response data
+// return: number of bytes in response
+static uint32_t DAP_ResetTarget(uint8_t *response) {
+
+ *(response+1) = RESET_TARGET();
+ *(response+0) = DAP_OK;
+ return (2U);
+}
+
+
+// Process SWJ Pins command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+static uint32_t DAP_SWJ_Pins(const uint8_t *request, uint8_t *response) {
+#if ((DAP_SWD != 0) || (DAP_JTAG != 0))
+ uint32_t value;
+ uint32_t select;
+ uint32_t wait;
+ uint32_t timestamp;
+
+ value = (uint32_t) *(request+0);
+ select = (uint32_t) *(request+1);
+ wait = (uint32_t)(*(request+2) << 0) |
+ (uint32_t)(*(request+3) << 8) |
+ (uint32_t)(*(request+4) << 16) |
+ (uint32_t)(*(request+5) << 24);
+
+ if ((select & (1U << DAP_SWJ_SWCLK_TCK)) != 0U) {
+ if ((value & (1U << DAP_SWJ_SWCLK_TCK)) != 0U) {
+ PIN_SWCLK_TCK_SET();
+ } else {
+ PIN_SWCLK_TCK_CLR();
+ }
+ }
+ if ((select & (1U << DAP_SWJ_SWDIO_TMS)) != 0U) {
+ if ((value & (1U << DAP_SWJ_SWDIO_TMS)) != 0U) {
+ PIN_SWDIO_TMS_SET();
+ } else {
+ PIN_SWDIO_TMS_CLR();
+ }
+ }
+ if ((select & (1U << DAP_SWJ_TDI)) != 0U) {
+ PIN_TDI_OUT(value >> DAP_SWJ_TDI);
+ }
+ if ((select & (1U << DAP_SWJ_nTRST)) != 0U) {
+ PIN_nTRST_OUT(value >> DAP_SWJ_nTRST);
+ }
+ if ((select & (1U << DAP_SWJ_nRESET)) != 0U){
+ PIN_nRESET_OUT(value >> DAP_SWJ_nRESET);
+ }
+
+ if (wait != 0U) {
+#if (TIMESTAMP_CLOCK != 0U)
+ if (wait > 3000000U) {
+ wait = 3000000U;
+ }
+#if (TIMESTAMP_CLOCK >= 1000000U)
+ wait *= TIMESTAMP_CLOCK / 1000000U;
+#else
+ wait /= 1000000U / TIMESTAMP_CLOCK;
+#endif
+#else
+ wait = 1U;
+#endif
+ timestamp = TIMESTAMP_GET();
+ do {
+ if ((select & (1U << DAP_SWJ_SWCLK_TCK)) != 0U) {
+ if ((value >> DAP_SWJ_SWCLK_TCK) ^ PIN_SWCLK_TCK_IN()) {
+ continue;
+ }
+ }
+ if ((select & (1U << DAP_SWJ_SWDIO_TMS)) != 0U) {
+ if ((value >> DAP_SWJ_SWDIO_TMS) ^ PIN_SWDIO_TMS_IN()) {
+ continue;
+ }
+ }
+ if ((select & (1U << DAP_SWJ_TDI)) != 0U) {
+ if ((value >> DAP_SWJ_TDI) ^ PIN_TDI_IN()) {
+ continue;
+ }
+ }
+ if ((select & (1U << DAP_SWJ_nTRST)) != 0U) {
+ if ((value >> DAP_SWJ_nTRST) ^ PIN_nTRST_IN()) {
+ continue;
+ }
+ }
+ if ((select & (1U << DAP_SWJ_nRESET)) != 0U) {
+ if ((value >> DAP_SWJ_nRESET) ^ PIN_nRESET_IN()) {
+ continue;
+ }
+ }
+ break;
+ } while ((TIMESTAMP_GET() - timestamp) < wait);
+ }
+
+ value = (PIN_SWCLK_TCK_IN() << DAP_SWJ_SWCLK_TCK) |
+ (PIN_SWDIO_TMS_IN() << DAP_SWJ_SWDIO_TMS) |
+ (PIN_TDI_IN() << DAP_SWJ_TDI) |
+ (PIN_TDO_IN() << DAP_SWJ_TDO) |
+ (PIN_nTRST_IN() << DAP_SWJ_nTRST) |
+ (PIN_nRESET_IN() << DAP_SWJ_nRESET);
+
+ *response = (uint8_t)value;
+#else
+ *response = 0U;
+#endif
+
+ return ((6U << 16) | 1U);
+}
+
+
+// Process SWJ Clock command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+static uint32_t DAP_SWJ_Clock(const uint8_t *request, uint8_t *response) {
+#if ((DAP_SWD != 0) || (DAP_JTAG != 0))
+ uint32_t clock;
+ uint32_t delay;
+
+ clock = (uint32_t)(*(request+0) << 0) |
+ (uint32_t)(*(request+1) << 8) |
+ (uint32_t)(*(request+2) << 16) |
+ (uint32_t)(*(request+3) << 24);
+
+ if (clock == 0U) {
+ *response = DAP_ERROR;
+ return ((4U << 16) | 1U);
+ }
+
+ if (clock >= MAX_SWJ_CLOCK(DELAY_FAST_CYCLES)) {
+ DAP_Data.fast_clock = 1U;
+ DAP_Data.clock_delay = 1U;
+ } else {
+ DAP_Data.fast_clock = 0U;
+
+ delay = ((CPU_CLOCK/2U) + (clock - 1U)) / clock;
+ if (delay > IO_PORT_WRITE_CYCLES) {
+ delay -= IO_PORT_WRITE_CYCLES;
+ delay = (delay + (DELAY_SLOW_CYCLES - 1U)) / DELAY_SLOW_CYCLES;
+ } else {
+ delay = 1U;
+ }
+
+ DAP_Data.clock_delay = delay;
+ }
+
+ *response = DAP_OK;
+#else
+ *response = DAP_ERROR;
+#endif
+
+ return ((4U << 16) | 1U);
+}
+
+
+// Process SWJ Sequence command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+static uint32_t DAP_SWJ_Sequence(const uint8_t *request, uint8_t *response) {
+ uint32_t count;
+
+ count = *request++;
+ if (count == 0U) {
+ count = 256U;
+ }
+
+#if ((DAP_SWD != 0) || (DAP_JTAG != 0))
+ SWJ_Sequence(count, request);
+ *response = DAP_OK;
+#else
+ *response = DAP_ERROR;
+#endif
+
+ count = (count + 7U) >> 3;
+
+ return (((count + 1U) << 16) | 1U);
+}
+
+
+// Process SWD Configure command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+static uint32_t DAP_SWD_Configure(const uint8_t *request, uint8_t *response) {
+#if (DAP_SWD != 0)
+ uint8_t value;
+
+ value = *request;
+ DAP_Data.swd_conf.turnaround = (value & 0x03U) + 1U;
+ DAP_Data.swd_conf.data_phase = (value & 0x04U) ? 1U : 0U;
+
+ *response = DAP_OK;
+#else
+ *response = DAP_ERROR;
+#endif
+
+ return ((1U << 16) | 1U);
+}
+
+
+// Process SWD Sequence command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+static uint32_t DAP_SWD_Sequence(const uint8_t *request, uint8_t *response) {
+ uint32_t sequence_info;
+ uint32_t sequence_count;
+ uint32_t request_count;
+ uint32_t response_count;
+ uint32_t count;
+
+#if (DAP_SWD != 0)
+ *response++ = DAP_OK;
+#else
+ *response++ = DAP_ERROR;
+#endif
+ request_count = 1U;
+ response_count = 1U;
+
+ sequence_count = *request++;
+ while (sequence_count--) {
+ sequence_info = *request++;
+ count = sequence_info & SWD_SEQUENCE_CLK;
+ if (count == 0U) {
+ count = 64U;
+ }
+ count = (count + 7U) / 8U;
+#if (DAP_SWD != 0)
+ if ((sequence_info & SWD_SEQUENCE_DIN) != 0U) {
+ PIN_SWDIO_OUT_DISABLE();
+ } else {
+ PIN_SWDIO_OUT_ENABLE();
+ }
+ SWD_Sequence(sequence_info, request, response);
+ if (sequence_count == 0U) {
+ PIN_SWDIO_OUT_ENABLE();
+ }
+#endif
+ if ((sequence_info & SWD_SEQUENCE_DIN) != 0U) {
+ request_count++;
+#if (DAP_SWD != 0)
+ response += count;
+ response_count += count;
+#endif
+ } else {
+ request += count;
+ request_count += count + 1U;
+ }
+ }
+
+ return ((request_count << 16) | response_count);
+}
+
+
+// Process JTAG Sequence command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+static uint32_t DAP_JTAG_Sequence(const uint8_t *request, uint8_t *response) {
+ uint32_t sequence_info;
+ uint32_t sequence_count;
+ uint32_t request_count;
+ uint32_t response_count;
+ uint32_t count;
+
+#if (DAP_JTAG != 0)
+ *response++ = DAP_OK;
+#else
+ *response++ = DAP_ERROR;
+#endif
+ request_count = 1U;
+ response_count = 1U;
+
+ sequence_count = *request++;
+ while (sequence_count--) {
+ sequence_info = *request++;
+ count = sequence_info & JTAG_SEQUENCE_TCK;
+ if (count == 0U) {
+ count = 64U;
+ }
+ count = (count + 7U) / 8U;
+#if (DAP_JTAG != 0)
+ JTAG_Sequence(sequence_info, request, response);
+#endif
+ request += count;
+ request_count += count + 1U;
+#if (DAP_JTAG != 0)
+ if ((sequence_info & JTAG_SEQUENCE_TDO) != 0U) {
+ response += count;
+ response_count += count;
+ }
+#endif
+ }
+
+ return ((request_count << 16) | response_count);
+}
+
+
+// Process JTAG Configure command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+static uint32_t DAP_JTAG_Configure(const uint8_t *request, uint8_t *response) {
+ uint32_t count;
+#if (DAP_JTAG != 0)
+ uint32_t length;
+ uint32_t bits;
+ uint32_t n;
+
+ count = *request++;
+ DAP_Data.jtag_dev.count = (uint8_t)count;
+
+ bits = 0U;
+ for (n = 0U; n < count; n++) {
+ length = *request++;
+ DAP_Data.jtag_dev.ir_length[n] = (uint8_t)length;
+ DAP_Data.jtag_dev.ir_before[n] = (uint16_t)bits;
+ bits += length;
+ }
+ for (n = 0U; n < count; n++) {
+ bits -= DAP_Data.jtag_dev.ir_length[n];
+ DAP_Data.jtag_dev.ir_after[n] = (uint16_t)bits;
+ }
+
+ *response = DAP_OK;
+#else
+ count = *request;
+ *response = DAP_ERROR;
+#endif
+
+ return (((count + 1U) << 16) | 1U);
+}
+
+
+// Process JTAG IDCODE command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+static uint32_t DAP_JTAG_IDCode(const uint8_t *request, uint8_t *response) {
+#if (DAP_JTAG != 0)
+ uint32_t data;
+
+ if (DAP_Data.debug_port != DAP_PORT_JTAG) {
+ goto id_error;
+ }
+
+ // Device index (JTAP TAP)
+ DAP_Data.jtag_dev.index = *request;
+ if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) {
+ goto id_error;
+ }
+
+ // Select JTAG chain
+ JTAG_IR(JTAG_IDCODE);
+
+ // Read IDCODE register
+ data = JTAG_ReadIDCode();
+
+ // Store Data
+ *(response+0) = DAP_OK;
+ *(response+1) = (uint8_t)(data >> 0);
+ *(response+2) = (uint8_t)(data >> 8);
+ *(response+3) = (uint8_t)(data >> 16);
+ *(response+4) = (uint8_t)(data >> 24);
+
+ return ((1U << 16) | 5U);
+
+id_error:
+#endif
+ *response = DAP_ERROR;
+ return ((1U << 16) | 1U);
+}
+
+
+// Process Transfer Configure command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+static uint32_t DAP_TransferConfigure(const uint8_t *request, uint8_t *response) {
+
+ DAP_Data.transfer.idle_cycles = *(request+0);
+ DAP_Data.transfer.retry_count = (uint16_t) *(request+1) |
+ (uint16_t)(*(request+2) << 8);
+ DAP_Data.transfer.match_retry = (uint16_t) *(request+3) |
+ (uint16_t)(*(request+4) << 8);
+
+ *response = DAP_OK;
+ return ((5U << 16) | 1U);
+}
+
+
+// Process SWD Transfer command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+#if (DAP_SWD != 0)
+static uint32_t DAP_SWD_Transfer(const uint8_t *request, uint8_t *response) {
+ const
+ uint8_t *request_head;
+ uint32_t request_count;
+ uint32_t request_value;
+ uint8_t *response_head;
+ uint32_t response_count;
+ uint32_t response_value;
+ uint32_t post_read;
+ uint32_t check_write;
+ uint32_t match_value;
+ uint32_t match_retry;
+ uint32_t retry;
+ uint32_t data;
+#if (TIMESTAMP_CLOCK != 0U)
+ uint32_t timestamp;
+#endif
+
+ request_head = request;
+
+ response_count = 0U;
+ response_value = 0U;
+ response_head = response;
+ response += 2;
+
+ DAP_TransferAbort = 0U;
+
+ post_read = 0U;
+ check_write = 0U;
+
+ request++; // Ignore DAP index
+
+ request_count = *request++;
+
+ for (; request_count != 0U; request_count--) {
+ request_value = *request++;
+ if ((request_value & DAP_TRANSFER_RnW) != 0U) {
+ // Read register
+ if (post_read) {
+ // Read was posted before
+ retry = DAP_Data.transfer.retry_count;
+ if ((request_value & (DAP_TRANSFER_APnDP | DAP_TRANSFER_MATCH_VALUE)) == DAP_TRANSFER_APnDP) {
+ // Read previous AP data and post next AP read
+ do {
+ response_value = SWD_Transfer(request_value, &data);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ } else {
+ // Read previous AP data
+ do {
+ response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ post_read = 0U;
+ }
+ if (response_value != DAP_TRANSFER_OK) {
+ break;
+ }
+ // Store previous AP data
+ *response++ = (uint8_t) data;
+ *response++ = (uint8_t)(data >> 8);
+ *response++ = (uint8_t)(data >> 16);
+ *response++ = (uint8_t)(data >> 24);
+#if (TIMESTAMP_CLOCK != 0U)
+ if (post_read) {
+ // Store Timestamp of next AP read
+ if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) {
+ timestamp = DAP_Data.timestamp;
+ *response++ = (uint8_t) timestamp;
+ *response++ = (uint8_t)(timestamp >> 8);
+ *response++ = (uint8_t)(timestamp >> 16);
+ *response++ = (uint8_t)(timestamp >> 24);
+ }
+ }
+#endif
+ }
+ if ((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) {
+ // Read with value match
+ match_value = (uint32_t)(*(request+0) << 0) |
+ (uint32_t)(*(request+1) << 8) |
+ (uint32_t)(*(request+2) << 16) |
+ (uint32_t)(*(request+3) << 24);
+ request += 4;
+ match_retry = DAP_Data.transfer.match_retry;
+ if ((request_value & DAP_TRANSFER_APnDP) != 0U) {
+ // Post AP read
+ retry = DAP_Data.transfer.retry_count;
+ do {
+ response_value = SWD_Transfer(request_value, NULL);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ if (response_value != DAP_TRANSFER_OK) {
+ break;
+ }
+ }
+ do {
+ // Read register until its value matches or retry counter expires
+ retry = DAP_Data.transfer.retry_count;
+ do {
+ response_value = SWD_Transfer(request_value, &data);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ if (response_value != DAP_TRANSFER_OK) {
+ break;
+ }
+ } while (((data & DAP_Data.transfer.match_mask) != match_value) && match_retry-- && !DAP_TransferAbort);
+ if ((data & DAP_Data.transfer.match_mask) != match_value) {
+ response_value |= DAP_TRANSFER_MISMATCH;
+ }
+ if (response_value != DAP_TRANSFER_OK) {
+ break;
+ }
+ } else {
+ // Normal read
+ retry = DAP_Data.transfer.retry_count;
+ if ((request_value & DAP_TRANSFER_APnDP) != 0U) {
+ // Read AP register
+ if (post_read == 0U) {
+ // Post AP read
+ do {
+ response_value = SWD_Transfer(request_value, NULL);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ if (response_value != DAP_TRANSFER_OK) {
+ break;
+ }
+#if (TIMESTAMP_CLOCK != 0U)
+ // Store Timestamp
+ if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) {
+ timestamp = DAP_Data.timestamp;
+ *response++ = (uint8_t) timestamp;
+ *response++ = (uint8_t)(timestamp >> 8);
+ *response++ = (uint8_t)(timestamp >> 16);
+ *response++ = (uint8_t)(timestamp >> 24);
+ }
+#endif
+ post_read = 1U;
+ }
+ } else {
+ // Read DP register
+ do {
+ response_value = SWD_Transfer(request_value, &data);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ if (response_value != DAP_TRANSFER_OK) {
+ break;
+ }
+#if (TIMESTAMP_CLOCK != 0U)
+ // Store Timestamp
+ if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) {
+ timestamp = DAP_Data.timestamp;
+ *response++ = (uint8_t) timestamp;
+ *response++ = (uint8_t)(timestamp >> 8);
+ *response++ = (uint8_t)(timestamp >> 16);
+ *response++ = (uint8_t)(timestamp >> 24);
+ }
+#endif
+ // Store data
+ *response++ = (uint8_t) data;
+ *response++ = (uint8_t)(data >> 8);
+ *response++ = (uint8_t)(data >> 16);
+ *response++ = (uint8_t)(data >> 24);
+ }
+ }
+ check_write = 0U;
+ } else {
+ // Write register
+ if (post_read) {
+ // Read previous data
+ retry = DAP_Data.transfer.retry_count;
+ do {
+ response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ if (response_value != DAP_TRANSFER_OK) {
+ break;
+ }
+ // Store previous data
+ *response++ = (uint8_t) data;
+ *response++ = (uint8_t)(data >> 8);
+ *response++ = (uint8_t)(data >> 16);
+ *response++ = (uint8_t)(data >> 24);
+ post_read = 0U;
+ }
+ // Load data
+ data = (uint32_t)(*(request+0) << 0) |
+ (uint32_t)(*(request+1) << 8) |
+ (uint32_t)(*(request+2) << 16) |
+ (uint32_t)(*(request+3) << 24);
+ request += 4;
+ if ((request_value & DAP_TRANSFER_MATCH_MASK) != 0U) {
+ // Write match mask
+ DAP_Data.transfer.match_mask = data;
+ response_value = DAP_TRANSFER_OK;
+ } else {
+ // Write DP/AP register
+ retry = DAP_Data.transfer.retry_count;
+ do {
+ response_value = SWD_Transfer(request_value, &data);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ if (response_value != DAP_TRANSFER_OK) {
+ break;
+ }
+#if (TIMESTAMP_CLOCK != 0U)
+ // Store Timestamp
+ if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) {
+ timestamp = DAP_Data.timestamp;
+ *response++ = (uint8_t) timestamp;
+ *response++ = (uint8_t)(timestamp >> 8);
+ *response++ = (uint8_t)(timestamp >> 16);
+ *response++ = (uint8_t)(timestamp >> 24);
+ }
+#endif
+ check_write = 1U;
+ }
+ }
+ response_count++;
+ if (DAP_TransferAbort) {
+ break;
+ }
+ }
+
+ for (; request_count != 0U; request_count--) {
+ // Process canceled requests
+ request_value = *request++;
+ if ((request_value & DAP_TRANSFER_RnW) != 0U) {
+ // Read register
+ if ((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) {
+ // Read with value match
+ request += 4;
+ }
+ } else {
+ // Write register
+ request += 4;
+ }
+ }
+
+ if (response_value == DAP_TRANSFER_OK) {
+ if (post_read) {
+ // Read previous data
+ retry = DAP_Data.transfer.retry_count;
+ do {
+ response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ if (response_value != DAP_TRANSFER_OK) {
+ goto end;
+ }
+ // Store previous data
+ *response++ = (uint8_t) data;
+ *response++ = (uint8_t)(data >> 8);
+ *response++ = (uint8_t)(data >> 16);
+ *response++ = (uint8_t)(data >> 24);
+ } else if (check_write) {
+ // Check last write
+ retry = DAP_Data.transfer.retry_count;
+ do {
+ response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ }
+ }
+
+end:
+ *(response_head+0) = (uint8_t)response_count;
+ *(response_head+1) = (uint8_t)response_value;
+
+ return (((uint32_t)(request - request_head) << 16) | (uint32_t)(response - response_head));
+}
+#endif
+
+
+// Process JTAG Transfer command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+#if (DAP_JTAG != 0)
+static uint32_t DAP_JTAG_Transfer(const uint8_t *request, uint8_t *response) {
+ const
+ uint8_t *request_head;
+ uint32_t request_count;
+ uint32_t request_value;
+ uint32_t request_ir;
+ uint8_t *response_head;
+ uint32_t response_count;
+ uint32_t response_value;
+ uint32_t post_read;
+ uint32_t match_value;
+ uint32_t match_retry;
+ uint32_t retry;
+ uint32_t data;
+ uint32_t ir;
+#if (TIMESTAMP_CLOCK != 0U)
+ uint32_t timestamp;
+#endif
+
+ request_head = request;
+
+ response_count = 0U;
+ response_value = 0U;
+ response_head = response;
+ response += 2;
+
+ DAP_TransferAbort = 0U;
+
+ ir = 0U;
+ post_read = 0U;
+
+ // Device index (JTAP TAP)
+ DAP_Data.jtag_dev.index = *request++;
+ if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) {
+ goto end;
+ }
+
+ request_count = *request++;
+
+ for (; request_count != 0U; request_count--) {
+ request_value = *request++;
+ request_ir = (request_value & DAP_TRANSFER_APnDP) ? JTAG_APACC : JTAG_DPACC;
+ if ((request_value & DAP_TRANSFER_RnW) != 0U) {
+ // Read register
+ if (post_read) {
+ // Read was posted before
+ retry = DAP_Data.transfer.retry_count;
+ if ((ir == request_ir) && ((request_value & DAP_TRANSFER_MATCH_VALUE) == 0U)) {
+ // Read previous data and post next read
+ do {
+ response_value = JTAG_Transfer(request_value, &data);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ } else {
+ // Select JTAG chain
+ if (ir != JTAG_DPACC) {
+ ir = JTAG_DPACC;
+ JTAG_IR(ir);
+ }
+ // Read previous data
+ do {
+ response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ post_read = 0U;
+ }
+ if (response_value != DAP_TRANSFER_OK) {
+ break;
+ }
+ // Store previous data
+ *response++ = (uint8_t) data;
+ *response++ = (uint8_t)(data >> 8);
+ *response++ = (uint8_t)(data >> 16);
+ *response++ = (uint8_t)(data >> 24);
+#if (TIMESTAMP_CLOCK != 0U)
+ if (post_read) {
+ // Store Timestamp of next AP read
+ if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) {
+ timestamp = DAP_Data.timestamp;
+ *response++ = (uint8_t) timestamp;
+ *response++ = (uint8_t)(timestamp >> 8);
+ *response++ = (uint8_t)(timestamp >> 16);
+ *response++ = (uint8_t)(timestamp >> 24);
+ }
+ }
+#endif
+ }
+ if ((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) {
+ // Read with value match
+ match_value = (uint32_t)(*(request+0) << 0) |
+ (uint32_t)(*(request+1) << 8) |
+ (uint32_t)(*(request+2) << 16) |
+ (uint32_t)(*(request+3) << 24);
+ request += 4;
+ match_retry = DAP_Data.transfer.match_retry;
+ // Select JTAG chain
+ if (ir != request_ir) {
+ ir = request_ir;
+ JTAG_IR(ir);
+ }
+ // Post DP/AP read
+ retry = DAP_Data.transfer.retry_count;
+ do {
+ response_value = JTAG_Transfer(request_value, NULL);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ if (response_value != DAP_TRANSFER_OK) {
+ break;
+ }
+ do {
+ // Read register until its value matches or retry counter expires
+ retry = DAP_Data.transfer.retry_count;
+ do {
+ response_value = JTAG_Transfer(request_value, &data);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ if (response_value != DAP_TRANSFER_OK) {
+ break;
+ }
+ } while (((data & DAP_Data.transfer.match_mask) != match_value) && match_retry-- && !DAP_TransferAbort);
+ if ((data & DAP_Data.transfer.match_mask) != match_value) {
+ response_value |= DAP_TRANSFER_MISMATCH;
+ }
+ if (response_value != DAP_TRANSFER_OK) {
+ break;
+ }
+ } else {
+ // Normal read
+ if (post_read == 0U) {
+ // Select JTAG chain
+ if (ir != request_ir) {
+ ir = request_ir;
+ JTAG_IR(ir);
+ }
+ // Post DP/AP read
+ retry = DAP_Data.transfer.retry_count;
+ do {
+ response_value = JTAG_Transfer(request_value, NULL);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ if (response_value != DAP_TRANSFER_OK) {
+ break;
+ }
+#if (TIMESTAMP_CLOCK != 0U)
+ // Store Timestamp
+ if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) {
+ timestamp = DAP_Data.timestamp;
+ *response++ = (uint8_t) timestamp;
+ *response++ = (uint8_t)(timestamp >> 8);
+ *response++ = (uint8_t)(timestamp >> 16);
+ *response++ = (uint8_t)(timestamp >> 24);
+ }
+#endif
+ post_read = 1U;
+ }
+ }
+ } else {
+ // Write register
+ if (post_read) {
+ // Select JTAG chain
+ if (ir != JTAG_DPACC) {
+ ir = JTAG_DPACC;
+ JTAG_IR(ir);
+ }
+ // Read previous data
+ retry = DAP_Data.transfer.retry_count;
+ do {
+ response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ if (response_value != DAP_TRANSFER_OK) {
+ break;
+ }
+ // Store previous data
+ *response++ = (uint8_t) data;
+ *response++ = (uint8_t)(data >> 8);
+ *response++ = (uint8_t)(data >> 16);
+ *response++ = (uint8_t)(data >> 24);
+ post_read = 0U;
+ }
+ // Load data
+ data = (uint32_t)(*(request+0) << 0) |
+ (uint32_t)(*(request+1) << 8) |
+ (uint32_t)(*(request+2) << 16) |
+ (uint32_t)(*(request+3) << 24);
+ request += 4;
+ if ((request_value & DAP_TRANSFER_MATCH_MASK) != 0U) {
+ // Write match mask
+ DAP_Data.transfer.match_mask = data;
+ response_value = DAP_TRANSFER_OK;
+ } else {
+ // Select JTAG chain
+ if (ir != request_ir) {
+ ir = request_ir;
+ JTAG_IR(ir);
+ }
+ // Write DP/AP register
+ retry = DAP_Data.transfer.retry_count;
+ do {
+ response_value = JTAG_Transfer(request_value, &data);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ if (response_value != DAP_TRANSFER_OK) {
+ break;
+ }
+#if (TIMESTAMP_CLOCK != 0U)
+ // Store Timestamp
+ if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) {
+ timestamp = DAP_Data.timestamp;
+ *response++ = (uint8_t) timestamp;
+ *response++ = (uint8_t)(timestamp >> 8);
+ *response++ = (uint8_t)(timestamp >> 16);
+ *response++ = (uint8_t)(timestamp >> 24);
+ }
+#endif
+ }
+ }
+ response_count++;
+ if (DAP_TransferAbort) {
+ break;
+ }
+ }
+
+ for (; request_count != 0U; request_count--) {
+ // Process canceled requests
+ request_value = *request++;
+ if ((request_value & DAP_TRANSFER_RnW) != 0U) {
+ // Read register
+ if ((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) {
+ // Read with value match
+ request += 4;
+ }
+ } else {
+ // Write register
+ request += 4;
+ }
+ }
+
+ if (response_value == DAP_TRANSFER_OK) {
+ // Select JTAG chain
+ if (ir != JTAG_DPACC) {
+ ir = JTAG_DPACC;
+ JTAG_IR(ir);
+ }
+ if (post_read) {
+ // Read previous data
+ retry = DAP_Data.transfer.retry_count;
+ do {
+ response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ if (response_value != DAP_TRANSFER_OK) {
+ goto end;
+ }
+ // Store previous data
+ *response++ = (uint8_t) data;
+ *response++ = (uint8_t)(data >> 8);
+ *response++ = (uint8_t)(data >> 16);
+ *response++ = (uint8_t)(data >> 24);
+ } else {
+ // Check last write
+ retry = DAP_Data.transfer.retry_count;
+ do {
+ response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ }
+ }
+
+end:
+ *(response_head+0) = (uint8_t)response_count;
+ *(response_head+1) = (uint8_t)response_value;
+
+ return (((uint32_t)(request - request_head) << 16) | (uint32_t)(response - response_head));
+}
+#endif
+
+
+// Process Dummy Transfer command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+static uint32_t DAP_Dummy_Transfer(const uint8_t *request, uint8_t *response) {
+ const
+ uint8_t *request_head;
+ uint32_t request_count;
+ uint32_t request_value;
+
+ request_head = request;
+
+ request++; // Ignore DAP index
+
+ request_count = *request++;
+
+ for (; request_count != 0U; request_count--) {
+ // Process dummy requests
+ request_value = *request++;
+ if ((request_value & DAP_TRANSFER_RnW) != 0U) {
+ // Read register
+ if ((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) {
+ // Read with value match
+ request += 4;
+ }
+ } else {
+ // Write register
+ request += 4;
+ }
+ }
+
+ *(response+0) = 0U; // Response count
+ *(response+1) = 0U; // Response value
+
+ return (((uint32_t)(request - request_head) << 16) | 2U);
+}
+
+
+// Process Transfer command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+static uint32_t DAP_Transfer(const uint8_t *request, uint8_t *response) {
+ uint32_t num;
+
+ switch (DAP_Data.debug_port) {
+#if (DAP_SWD != 0)
+ case DAP_PORT_SWD:
+ num = DAP_SWD_Transfer(request, response);
+ break;
+#endif
+#if (DAP_JTAG != 0)
+ case DAP_PORT_JTAG:
+ num = DAP_JTAG_Transfer(request, response);
+ break;
+#endif
+ default:
+ num = DAP_Dummy_Transfer(request, response);
+ break;
+ }
+
+ return (num);
+}
+
+
+// Process SWD Transfer Block command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response
+#if (DAP_SWD != 0)
+static uint32_t DAP_SWD_TransferBlock(const uint8_t *request, uint8_t *response) {
+ uint32_t request_count;
+ uint32_t request_value;
+ uint32_t response_count;
+ uint32_t response_value;
+ uint8_t *response_head;
+ uint32_t retry;
+ uint32_t data;
+
+ response_count = 0U;
+ response_value = 0U;
+ response_head = response;
+ response += 3;
+
+ DAP_TransferAbort = 0U;
+
+ request++; // Ignore DAP index
+
+ request_count = (uint32_t)(*(request+0) << 0) |
+ (uint32_t)(*(request+1) << 8);
+ request += 2;
+ if (request_count == 0U) {
+ goto end;
+ }
+
+ request_value = *request++;
+ if ((request_value & DAP_TRANSFER_RnW) != 0U) {
+ // Read register block
+ if ((request_value & DAP_TRANSFER_APnDP) != 0U) {
+ // Post AP read
+ retry = DAP_Data.transfer.retry_count;
+ do {
+ response_value = SWD_Transfer(request_value, NULL);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ if (response_value != DAP_TRANSFER_OK) {
+ goto end;
+ }
+ }
+ while (request_count--) {
+ // Read DP/AP register
+ if ((request_count == 0U) && ((request_value & DAP_TRANSFER_APnDP) != 0U)) {
+ // Last AP read
+ request_value = DP_RDBUFF | DAP_TRANSFER_RnW;
+ }
+ retry = DAP_Data.transfer.retry_count;
+ do {
+ response_value = SWD_Transfer(request_value, &data);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ if (response_value != DAP_TRANSFER_OK) {
+ goto end;
+ }
+ // Store data
+ *response++ = (uint8_t) data;
+ *response++ = (uint8_t)(data >> 8);
+ *response++ = (uint8_t)(data >> 16);
+ *response++ = (uint8_t)(data >> 24);
+ response_count++;
+ }
+ } else {
+ // Write register block
+ while (request_count--) {
+ // Load data
+ data = (uint32_t)(*(request+0) << 0) |
+ (uint32_t)(*(request+1) << 8) |
+ (uint32_t)(*(request+2) << 16) |
+ (uint32_t)(*(request+3) << 24);
+ request += 4;
+ // Write DP/AP register
+ retry = DAP_Data.transfer.retry_count;
+ do {
+ response_value = SWD_Transfer(request_value, &data);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ if (response_value != DAP_TRANSFER_OK) {
+ goto end;
+ }
+ response_count++;
+ }
+ // Check last write
+ retry = DAP_Data.transfer.retry_count;
+ do {
+ response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ }
+
+end:
+ *(response_head+0) = (uint8_t)(response_count >> 0);
+ *(response_head+1) = (uint8_t)(response_count >> 8);
+ *(response_head+2) = (uint8_t) response_value;
+
+ return ((uint32_t)(response - response_head));
+}
+#endif
+
+
+// Process JTAG Transfer Block command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response
+#if (DAP_JTAG != 0)
+static uint32_t DAP_JTAG_TransferBlock(const uint8_t *request, uint8_t *response) {
+ uint32_t request_count;
+ uint32_t request_value;
+ uint32_t response_count;
+ uint32_t response_value;
+ uint8_t *response_head;
+ uint32_t retry;
+ uint32_t data;
+ uint32_t ir;
+
+ response_count = 0U;
+ response_value = 0U;
+ response_head = response;
+ response += 3;
+
+ DAP_TransferAbort = 0U;
+
+ // Device index (JTAP TAP)
+ DAP_Data.jtag_dev.index = *request++;
+ if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) {
+ goto end;
+ }
+
+ request_count = (uint32_t)(*(request+0) << 0) |
+ (uint32_t)(*(request+1) << 8);
+ request += 2;
+ if (request_count == 0U) {
+ goto end;
+ }
+
+ request_value = *request++;
+
+ // Select JTAG chain
+ ir = (request_value & DAP_TRANSFER_APnDP) ? JTAG_APACC : JTAG_DPACC;
+ JTAG_IR(ir);
+
+ if ((request_value & DAP_TRANSFER_RnW) != 0U) {
+ // Post read
+ retry = DAP_Data.transfer.retry_count;
+ do {
+ response_value = JTAG_Transfer(request_value, NULL);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ if (response_value != DAP_TRANSFER_OK) {
+ goto end;
+ }
+ // Read register block
+ while (request_count--) {
+ // Read DP/AP register
+ if (request_count == 0U) {
+ // Last read
+ if (ir != JTAG_DPACC) {
+ JTAG_IR(JTAG_DPACC);
+ }
+ request_value = DP_RDBUFF | DAP_TRANSFER_RnW;
+ }
+ retry = DAP_Data.transfer.retry_count;
+ do {
+ response_value = JTAG_Transfer(request_value, &data);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ if (response_value != DAP_TRANSFER_OK) {
+ goto end;
+ }
+ // Store data
+ *response++ = (uint8_t) data;
+ *response++ = (uint8_t)(data >> 8);
+ *response++ = (uint8_t)(data >> 16);
+ *response++ = (uint8_t)(data >> 24);
+ response_count++;
+ }
+ } else {
+ // Write register block
+ while (request_count--) {
+ // Load data
+ data = (uint32_t)(*(request+0) << 0) |
+ (uint32_t)(*(request+1) << 8) |
+ (uint32_t)(*(request+2) << 16) |
+ (uint32_t)(*(request+3) << 24);
+ request += 4;
+ // Write DP/AP register
+ retry = DAP_Data.transfer.retry_count;
+ do {
+ response_value = JTAG_Transfer(request_value, &data);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ if (response_value != DAP_TRANSFER_OK) {
+ goto end;
+ }
+ response_count++;
+ }
+ // Check last write
+ if (ir != JTAG_DPACC) {
+ JTAG_IR(JTAG_DPACC);
+ }
+ retry = DAP_Data.transfer.retry_count;
+ do {
+ response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL);
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
+ }
+
+end:
+ *(response_head+0) = (uint8_t)(response_count >> 0);
+ *(response_head+1) = (uint8_t)(response_count >> 8);
+ *(response_head+2) = (uint8_t) response_value;
+
+ return ((uint32_t)(response - response_head));
+}
+#endif
+
+
+// Process Transfer Block command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+static uint32_t DAP_TransferBlock(const uint8_t *request, uint8_t *response) {
+ uint32_t num;
+
+ switch (DAP_Data.debug_port) {
+#if (DAP_SWD != 0)
+ case DAP_PORT_SWD:
+ num = DAP_SWD_TransferBlock (request, response);
+ break;
+#endif
+#if (DAP_JTAG != 0)
+ case DAP_PORT_JTAG:
+ num = DAP_JTAG_TransferBlock(request, response);
+ break;
+#endif
+ default:
+ *(response+0) = 0U; // Response count [7:0]
+ *(response+1) = 0U; // Response count[15:8]
+ *(response+2) = 0U; // Response value
+ num = 3U;
+ break;
+ }
+
+ if ((*(request+3) & DAP_TRANSFER_RnW) != 0U) {
+ // Read register block
+ num |= 4U << 16;
+ } else {
+ // Write register block
+ num |= (4U + (((uint32_t)(*(request+1)) | (uint32_t)(*(request+2) << 8)) * 4)) << 16;
+ }
+
+ return (num);
+}
+
+
+// Process SWD Write ABORT command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response
+#if (DAP_SWD != 0)
+static uint32_t DAP_SWD_WriteAbort(const uint8_t *request, uint8_t *response) {
+ uint32_t data;
+
+ // Load data (Ignore DAP index)
+ data = (uint32_t)(*(request+1) << 0) |
+ (uint32_t)(*(request+2) << 8) |
+ (uint32_t)(*(request+3) << 16) |
+ (uint32_t)(*(request+4) << 24);
+
+ // Write Abort register
+ SWD_Transfer(DP_ABORT, &data);
+
+ *response = DAP_OK;
+ return (1U);
+}
+#endif
+
+
+// Process JTAG Write ABORT command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response
+#if (DAP_JTAG != 0)
+static uint32_t DAP_JTAG_WriteAbort(const uint8_t *request, uint8_t *response) {
+ uint32_t data;
+
+ // Device index (JTAP TAP)
+ DAP_Data.jtag_dev.index = *request;
+ if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) {
+ *response = DAP_ERROR;
+ return (1U);
+ }
+
+ // Select JTAG chain
+ JTAG_IR(JTAG_ABORT);
+
+ // Load data
+ data = (uint32_t)(*(request+1) << 0) |
+ (uint32_t)(*(request+2) << 8) |
+ (uint32_t)(*(request+3) << 16) |
+ (uint32_t)(*(request+4) << 24);
+
+ // Write Abort register
+ JTAG_WriteAbort(data);
+
+ *response = DAP_OK;
+ return (1U);
+}
+#endif
+
+
+// Process Write ABORT command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+static uint32_t DAP_WriteAbort(const uint8_t *request, uint8_t *response) {
+ uint32_t num;
+
+ switch (DAP_Data.debug_port) {
+#if (DAP_SWD != 0)
+ case DAP_PORT_SWD:
+ num = DAP_SWD_WriteAbort (request, response);
+ break;
+#endif
+#if (DAP_JTAG != 0)
+ case DAP_PORT_JTAG:
+ num = DAP_JTAG_WriteAbort(request, response);
+ break;
+#endif
+ default:
+ *response = DAP_ERROR;
+ num = 1U;
+ break;
+ }
+ return ((5U << 16) | num);
+}
+
+
+// Process DAP Vendor command request and prepare response
+// Default function (can be overridden)
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+__WEAK uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) {
+ (void)request;
+ *response = ID_DAP_Invalid;
+ return ((1U << 16) | 1U);
+}
+
+// Process DAP Vendor extended command request and prepare response
+// Default function (can be overridden)
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+__weak uint32_t DAP_ProcessVendorCommandEx(const uint8_t *request, uint8_t *response) {
+ *response = ID_DAP_Invalid;
+ return ((1U << 16) | 1U);
+}
+
+// Process DAP command request and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+uint32_t DAP_ProcessCommand(const uint8_t *request, uint8_t *response) {
+ uint32_t num;
+
+ if ((*request >= ID_DAP_Vendor0) && (*request <= ID_DAP_Vendor31)) {
+ return DAP_ProcessVendorCommand(request, response);
+ }
+
+ if ((*request >= ID_DAP_VendorExFirst) && (*request <= ID_DAP_VendorExLast)) {
+ return DAP_ProcessVendorCommandEx(request, response);
+ }
+
+ *response++ = *request;
+
+ switch (*request++) {
+ case ID_DAP_Info:
+ num = DAP_Info(*request, response+1);
+ *response = (uint8_t)num;
+ return ((2U << 16) + 2U + num);
+
+ case ID_DAP_HostStatus:
+ num = DAP_HostStatus(request, response);
+ break;
+
+ case ID_DAP_Connect:
+ num = DAP_Connect(request, response);
+ break;
+ case ID_DAP_Disconnect:
+ num = DAP_Disconnect(response);
+ break;
+
+ case ID_DAP_Delay:
+ num = DAP_Delay(request, response);
+ break;
+
+ case ID_DAP_ResetTarget:
+ num = DAP_ResetTarget(response);
+ break;
+
+ case ID_DAP_SWJ_Pins:
+ num = DAP_SWJ_Pins(request, response);
+ break;
+ case ID_DAP_SWJ_Clock:
+ num = DAP_SWJ_Clock(request, response);
+ break;
+ case ID_DAP_SWJ_Sequence:
+ num = DAP_SWJ_Sequence(request, response);
+ break;
+
+ case ID_DAP_SWD_Configure:
+ num = DAP_SWD_Configure(request, response);
+ break;
+ case ID_DAP_SWD_Sequence:
+ num = DAP_SWD_Sequence(request, response);
+ break;
+
+ case ID_DAP_JTAG_Sequence:
+ num = DAP_JTAG_Sequence(request, response);
+ break;
+ case ID_DAP_JTAG_Configure:
+ num = DAP_JTAG_Configure(request, response);
+ break;
+ case ID_DAP_JTAG_IDCODE:
+ num = DAP_JTAG_IDCode(request, response);
+ break;
+
+ case ID_DAP_TransferConfigure:
+ num = DAP_TransferConfigure(request, response);
+ break;
+ case ID_DAP_Transfer:
+ num = DAP_Transfer(request, response);
+ break;
+ case ID_DAP_TransferBlock:
+ num = DAP_TransferBlock(request, response);
+ break;
+
+ case ID_DAP_WriteABORT:
+ num = DAP_WriteAbort(request, response);
+ break;
+
+#if ((SWO_UART != 0) || (SWO_MANCHESTER != 0))
+ case ID_DAP_SWO_Transport:
+ num = SWO_Transport(request, response);
+ break;
+ case ID_DAP_SWO_Mode:
+ num = SWO_Mode(request, response);
+ break;
+ case ID_DAP_SWO_Baudrate:
+ num = SWO_Baudrate(request, response);
+ break;
+ case ID_DAP_SWO_Control:
+ num = SWO_Control(request, response);
+ break;
+ case ID_DAP_SWO_Status:
+ num = SWO_Status(response);
+ break;
+ case ID_DAP_SWO_ExtendedStatus:
+ num = SWO_ExtendedStatus(request, response);
+ break;
+ case ID_DAP_SWO_Data:
+ num = SWO_Data(request, response);
+ break;
+#endif
+
+ default:
+ *(response-1) = ID_DAP_Invalid;
+ return ((1U << 16) | 1U);
+ }
+
+ return ((1U << 16) + 1U + num);
+}
+
+
+// Execute DAP command (process request and prepare response)
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+uint32_t DAP_ExecuteCommand(const uint8_t *request, uint8_t *response) {
+ uint32_t cnt, num, n;
+
+ if (*request == ID_DAP_ExecuteCommands) {
+ *response++ = *request++;
+ cnt = *request++;
+ *response++ = (uint8_t)cnt;
+ num = (2U << 16) | 2U;
+ while (cnt--) {
+ n = DAP_ProcessCommand(request, response);
+ num += n;
+ request += (uint16_t)(n >> 16);
+ response += (uint16_t) n;
+ }
+ return (num);
+ }
+
+ return DAP_ProcessCommand(request, response);
+}
+
+
+// Setup DAP
+void DAP_Setup(void) {
+
+ // Default settings
+ DAP_Data.debug_port = 0U;
+ DAP_Data.fast_clock = 0U;
+ DAP_Data.clock_delay = CLOCK_DELAY(DAP_DEFAULT_SWJ_CLOCK);
+ DAP_Data.transfer.idle_cycles = 0U;
+ DAP_Data.transfer.retry_count = 100U;
+ DAP_Data.transfer.match_retry = 0U;
+ DAP_Data.transfer.match_mask = 0x00000000U;
+#if (DAP_SWD != 0)
+ DAP_Data.swd_conf.turnaround = 1U;
+ DAP_Data.swd_conf.data_phase = 0U;
+#endif
+#if (DAP_JTAG != 0)
+ DAP_Data.jtag_dev.count = 0U;
+#endif
+
+ DAP_SETUP(); // Device specific setup
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/cmsis-dap/DAP.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/cmsis-dap/DAP.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,332 @@
+/*
+ * Copyright (c) 2013-2019 ARM Limited. All rights reserved.
+ * Copyright 2019, Cypress Semiconductor Corporation
+ * or a subsidiary of Cypress Semiconductor Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date: 26. November 2019
+ * $Revision: V2.0.0
+ *
+ * Project: CMSIS-DAP Include
+ * Title: DAP.h Definitions
+ *
+ *---------------------------------------------------------------------------*/
+
+#ifndef __DAP_H__
+#define __DAP_H__
+
+
+// DAP Firmware Version
+#ifdef DAP_FW_V1
+#define DAP_FW_VER "1.2.0"
+#else
+#define DAP_FW_VER "2.0.0"
+#endif
+
+// DAP Command IDs
+#define ID_DAP_Info 0x00U
+#define ID_DAP_HostStatus 0x01U
+#define ID_DAP_Connect 0x02U
+#define ID_DAP_Disconnect 0x03U
+#define ID_DAP_TransferConfigure 0x04U
+#define ID_DAP_Transfer 0x05U
+#define ID_DAP_TransferBlock 0x06U
+#define ID_DAP_TransferAbort 0x07U
+#define ID_DAP_WriteABORT 0x08U
+#define ID_DAP_Delay 0x09U
+#define ID_DAP_ResetTarget 0x0AU
+#define ID_DAP_SWJ_Pins 0x10U
+#define ID_DAP_SWJ_Clock 0x11U
+#define ID_DAP_SWJ_Sequence 0x12U
+#define ID_DAP_SWD_Configure 0x13U
+#define ID_DAP_SWD_Sequence 0x1DU
+#define ID_DAP_JTAG_Sequence 0x14U
+#define ID_DAP_JTAG_Configure 0x15U
+#define ID_DAP_JTAG_IDCODE 0x16U
+#define ID_DAP_SWO_Transport 0x17U
+#define ID_DAP_SWO_Mode 0x18U
+#define ID_DAP_SWO_Baudrate 0x19U
+#define ID_DAP_SWO_Control 0x1AU
+#define ID_DAP_SWO_Status 0x1BU
+#define ID_DAP_SWO_ExtendedStatus 0x1EU
+#define ID_DAP_SWO_Data 0x1CU
+
+#define ID_DAP_QueueCommands 0x7EU
+#define ID_DAP_ExecuteCommands 0x7FU
+
+// DAP Vendor Command IDs
+#define ID_DAP_Vendor0 0x80U
+#define ID_DAP_Vendor1 0x81U
+#define ID_DAP_Vendor2 0x82U
+#define ID_DAP_Vendor3 0x83U
+#define ID_DAP_Vendor4 0x84U
+#define ID_DAP_Vendor5 0x85U
+#define ID_DAP_Vendor6 0x86U
+#define ID_DAP_Vendor7 0x87U
+#define ID_DAP_Vendor8 0x88U
+#define ID_DAP_Vendor9 0x89U
+#define ID_DAP_Vendor10 0x8AU
+#define ID_DAP_Vendor11 0x8BU
+#define ID_DAP_Vendor12 0x8CU
+#define ID_DAP_Vendor13 0x8DU
+#define ID_DAP_Vendor14 0x8EU
+#define ID_DAP_Vendor15 0x8FU
+#define ID_DAP_Vendor16 0x90U
+#define ID_DAP_Vendor17 0x91U
+#define ID_DAP_Vendor18 0x92U
+#define ID_DAP_Vendor19 0x93U
+#define ID_DAP_Vendor20 0x94U
+#define ID_DAP_Vendor21 0x95U
+#define ID_DAP_Vendor22 0x96U
+#define ID_DAP_Vendor23 0x97U
+#define ID_DAP_Vendor24 0x98U
+#define ID_DAP_Vendor25 0x99U
+#define ID_DAP_Vendor26 0x9AU
+#define ID_DAP_Vendor27 0x9BU
+#define ID_DAP_Vendor28 0x9CU
+#define ID_DAP_Vendor29 0x9DU
+#define ID_DAP_Vendor30 0x9EU
+#define ID_DAP_Vendor31 0x9FU
+
+// DAP Extended range of Vendor Command IDs
+
+#define ID_DAP_VendorExFirst 0xA0U
+#define ID_DAP_VendorExLast 0xFEU
+
+#define ID_DAP_Invalid 0xFFU
+
+// DAP Status Code
+#define DAP_OK 0U
+#define DAP_ERROR 0xFFU
+
+// DAP ID
+#define DAP_ID_VENDOR 1U
+#define DAP_ID_PRODUCT 2U
+#define DAP_ID_SER_NUM 3U
+#define DAP_ID_FW_VER 4U
+#define DAP_ID_DEVICE_VENDOR 5U
+#define DAP_ID_DEVICE_NAME 6U
+#define DAP_ID_CAPABILITIES 0xF0U
+#define DAP_ID_TIMESTAMP_CLOCK 0xF1U
+#define DAP_ID_SWO_BUFFER_SIZE 0xFDU
+#define DAP_ID_PACKET_COUNT 0xFEU
+#define DAP_ID_PACKET_SIZE 0xFFU
+
+// DAP Host Status
+#define DAP_DEBUGGER_CONNECTED 0U
+#define DAP_TARGET_RUNNING 1U
+
+// DAP Port
+#define DAP_PORT_AUTODETECT 0U // Autodetect Port
+#define DAP_PORT_DISABLED 0U // Port Disabled (I/O pins in High-Z)
+#define DAP_PORT_SWD 1U // SWD Port (SWCLK, SWDIO) + nRESET
+#define DAP_PORT_JTAG 2U // JTAG Port (TCK, TMS, TDI, TDO, nTRST) + nRESET
+
+// DAP SWJ Pins
+#define DAP_SWJ_SWCLK_TCK 0 // SWCLK/TCK
+#define DAP_SWJ_SWDIO_TMS 1 // SWDIO/TMS
+#define DAP_SWJ_TDI 2 // TDI
+#define DAP_SWJ_TDO 3 // TDO
+#define DAP_SWJ_nTRST 5 // nTRST
+#define DAP_SWJ_nRESET 7 // nRESET
+
+// DAP Transfer Request
+#define DAP_TRANSFER_APnDP (1U<<0)
+#define DAP_TRANSFER_RnW (1U<<1)
+#define DAP_TRANSFER_A2 (1U<<2)
+#define DAP_TRANSFER_A3 (1U<<3)
+#define DAP_TRANSFER_MATCH_VALUE (1U<<4)
+#define DAP_TRANSFER_MATCH_MASK (1U<<5)
+#define DAP_TRANSFER_TIMESTAMP (1U<<7)
+
+// DAP Transfer Response
+#define DAP_TRANSFER_OK (1U<<0)
+#define DAP_TRANSFER_WAIT (1U<<1)
+#define DAP_TRANSFER_FAULT (1U<<2)
+#define DAP_TRANSFER_ERROR (1U<<3)
+#define DAP_TRANSFER_MISMATCH (1U<<4)
+
+// DAP SWO Trace Mode
+#define DAP_SWO_OFF 0U
+#define DAP_SWO_UART 1U
+#define DAP_SWO_MANCHESTER 2U
+
+// DAP SWO Trace Status
+#define DAP_SWO_CAPTURE_ACTIVE (1U<<0)
+#define DAP_SWO_CAPTURE_PAUSED (1U<<1)
+#define DAP_SWO_STREAM_ERROR (1U<<6)
+#define DAP_SWO_BUFFER_OVERRUN (1U<<7)
+
+
+// Debug Port Register Addresses
+#define DP_IDCODE 0x00U // IDCODE Register (SW Read only)
+#define DP_ABORT 0x00U // Abort Register (SW Write only)
+#define DP_CTRL_STAT 0x04U // Control & Status
+#define DP_WCR 0x04U // Wire Control Register (SW Only)
+#define DP_SELECT 0x08U // Select Register (JTAG R/W & SW W)
+#define DP_RESEND 0x08U // Resend (SW Read Only)
+#define DP_RDBUFF 0x0CU // Read Buffer (Read Only)
+
+// JTAG IR Codes
+#define JTAG_ABORT 0x08U
+#define JTAG_DPACC 0x0AU
+#define JTAG_APACC 0x0BU
+#define JTAG_IDCODE 0x0EU
+#define JTAG_BYPASS 0x0FU
+
+// JTAG Sequence Info
+#define JTAG_SEQUENCE_TCK 0x3FU // TCK count
+#define JTAG_SEQUENCE_TMS 0x40U // TMS value
+#define JTAG_SEQUENCE_TDO 0x80U // TDO capture
+
+// SWD Sequence Info
+#define SWD_SEQUENCE_CLK 0x3FU // SWCLK count
+#define SWD_SEQUENCE_DIN 0x80U // SWDIO capture
+
+
+#include <stddef.h>
+#include <stdint.h>
+#include "cmsis_compiler.h"
+
+// DAP Data structure
+typedef struct {
+ uint8_t debug_port; // Debug Port
+ uint8_t fast_clock; // Fast Clock Flag
+ uint8_t padding[2];
+ uint32_t clock_delay; // Clock Delay
+ uint32_t timestamp; // Last captured Timestamp
+ struct { // Transfer Configuration
+ uint8_t idle_cycles; // Idle cycles after transfer
+ uint8_t padding[3];
+ uint16_t retry_count; // Number of retries after WAIT response
+ uint16_t match_retry; // Number of retries if read value does not match
+ uint32_t match_mask; // Match Mask
+ } transfer;
+#if (DAP_SWD != 0)
+ struct { // SWD Configuration
+ uint8_t turnaround; // Turnaround period
+ uint8_t data_phase; // Always generate Data Phase
+ } swd_conf;
+#endif
+#if (DAP_JTAG != 0)
+ struct { // JTAG Device Chain
+ uint8_t count; // Number of devices
+ uint8_t index; // Device index (device at TDO has index 0)
+#if (DAP_JTAG_DEV_CNT != 0)
+ uint8_t ir_length[DAP_JTAG_DEV_CNT]; // IR Length in bits
+ uint16_t ir_before[DAP_JTAG_DEV_CNT]; // Bits before IR
+ uint16_t ir_after [DAP_JTAG_DEV_CNT]; // Bits after IR
+#endif
+ } jtag_dev;
+#endif
+} DAP_Data_t;
+
+extern DAP_Data_t DAP_Data; // DAP Data
+extern volatile uint8_t DAP_TransferAbort; // Transfer Abort Flag
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+// Functions
+extern void SWJ_Sequence (uint32_t count, const uint8_t *data);
+extern void SWD_Sequence (uint32_t info, const uint8_t *swdo, uint8_t *swdi);
+extern void JTAG_Sequence (uint32_t info, const uint8_t *tdi, uint8_t *tdo);
+extern void JTAG_IR (uint32_t ir);
+extern uint32_t JTAG_ReadIDCode (void);
+extern void JTAG_WriteAbort (uint32_t data);
+extern uint8_t JTAG_Transfer (uint32_t request, uint32_t *data);
+extern uint8_t SWD_Transfer (uint32_t request, uint32_t *data);
+
+extern void Delayms (uint32_t delay);
+
+extern uint32_t SWO_Transport (const uint8_t *request, uint8_t *response);
+extern uint32_t SWO_Mode (const uint8_t *request, uint8_t *response);
+extern uint32_t SWO_Baudrate (const uint8_t *request, uint8_t *response);
+extern uint32_t SWO_Control (const uint8_t *request, uint8_t *response);
+extern uint32_t SWO_Status (uint8_t *response);
+extern uint32_t SWO_ExtendedStatus (const uint8_t *request, uint8_t *response);
+extern uint32_t SWO_Data (const uint8_t *request, uint8_t *response);
+
+extern void SWO_QueueTransfer (uint8_t *buf, uint32_t num);
+extern void SWO_AbortTransfer (void);
+extern void SWO_TransferComplete (void);
+
+extern uint32_t UART_SWO_Mode (uint32_t enable);
+extern uint32_t UART_SWO_Baudrate (uint32_t baudrate);
+extern uint32_t UART_SWO_Control (uint32_t active);
+extern void UART_SWO_Capture (uint8_t *buf, uint32_t num);
+extern uint32_t UART_SWO_GetCount (void);
+
+extern uint32_t Manchester_SWO_Mode (uint32_t enable);
+extern uint32_t Manchester_SWO_Baudrate (uint32_t baudrate);
+extern uint32_t Manchester_SWO_Control (uint32_t active);
+extern void Manchester_SWO_Capture (uint8_t *buf, uint32_t num);
+extern uint32_t Manchester_SWO_GetCount (void);
+
+extern uint32_t DAP_ProcessVendorCommand (const uint8_t *request, uint8_t *response);
+extern uint32_t DAP_ProcessCommand (const uint8_t *request, uint8_t *response);
+extern uint32_t DAP_ExecuteCommand (const uint8_t *request, uint8_t *response);
+
+extern void DAP_Setup (void);
+
+// Configurable delay for clock generation
+#ifndef DELAY_SLOW_CYCLES
+#define DELAY_SLOW_CYCLES 3U // Number of cycles for one iteration
+#endif
+#if defined(__CC_ARM)
+__STATIC_FORCEINLINE void PIN_DELAY_SLOW (uint32_t delay) {
+ uint32_t count = delay;
+ while (--count);
+}
+#else
+__STATIC_FORCEINLINE void PIN_DELAY_SLOW (uint32_t delay) {
+ __ASM volatile (
+ ".syntax unified\n"
+ "0:\n\t"
+ "subs %0,%0,#1\n\t"
+ "bne 0b\n"
+ : "+l" (delay) : : "cc"
+ );
+}
+#endif
+
+// Fixed delay for fast clock generation
+#ifndef DELAY_FAST_CYCLES
+#define DELAY_FAST_CYCLES 0U // Number of cycles: 0..3
+#endif
+__STATIC_FORCEINLINE void PIN_DELAY_FAST (void) {
+#if (DELAY_FAST_CYCLES >= 1U)
+ __NOP();
+#endif
+#if (DELAY_FAST_CYCLES >= 2U)
+ __NOP();
+#endif
+#if (DELAY_FAST_CYCLES >= 3U)
+ __NOP();
+#endif
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __DAP_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/daplink/cmsis-dap/DAP_queue.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/cmsis-dap/DAP_queue.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,75 @@
+/**
+ * @file DAP_queue.c
+ * @brief DAP processing queue
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+#include "DAP_queue.h"
+void DAP_queue_init(DAP_queue * queue)
+{
+ queue->recv_idx = 0;
+ queue->send_idx = 0;
+ queue->free_count = FREE_COUNT_INIT;
+ queue->send_count = SEND_COUNT_INIT;
+}
+
+/*
+ * Get the a buffer from the DAP_queue where the response to the request is stored
+ * Parameters: queue - DAP queue, buf = return the buffer location, len = return the len of the response
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+BOOL DAP_queue_get_send_buf(DAP_queue * queue, uint8_t ** buf, int * len)
+{
+ if (queue->send_count) {
+ queue->send_count--;
+ *buf = queue->USB_Request[queue->send_idx];
+ *len = queue->resp_size[queue->send_idx];
+ queue->send_idx = (queue->send_idx + 1) % DAP_PACKET_COUNT;
+ queue->free_count++;
+ return (__TRUE);
+ }
+ return (__FALSE);
+}
+
+/*
+ * Execute a request and store result to the DAP_queue
+ * Parameters: queue - DAP queue, reqbuf = buffer with DAP request, len = of the request buffer, retbuf = buffer to peek on the result of the DAP operation
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+
+BOOL DAP_queue_execute_buf(DAP_queue * queue, const uint8_t *reqbuf, int len, uint8_t ** retbuf)
+{
+ uint32_t rsize;
+ if (queue->free_count > 0) {
+ if (len > DAP_PACKET_SIZE) {
+ len = DAP_PACKET_SIZE;
+ }
+ queue->free_count--;
+ memcpy(queue->USB_Request[queue->recv_idx], reqbuf, len);
+ rsize = DAP_ExecuteCommand(reqbuf, queue->USB_Request[queue->recv_idx]);
+ queue->resp_size[queue->recv_idx] = rsize & 0xFFFF; //get the response size
+ *retbuf = queue->USB_Request[queue->recv_idx];
+ queue->recv_idx = (queue->recv_idx + 1) % DAP_PACKET_COUNT;
+ queue->send_count++;
+ return (__TRUE);
+ }
+ return (__FALSE);
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/cmsis-dap/DAP_queue.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/cmsis-dap/DAP_queue.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,65 @@
+/**
+ * @file DAP_queue.h
+ * @brief DAP processing queue
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef DAP_QUEUE_H
+#define DAP_QUEUE_H
+
+#include "usb_def.h"
+#include "DAP_config.h"
+#include "DAP.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define FREE_COUNT_INIT (DAP_PACKET_COUNT)
+#define SEND_COUNT_INIT 0
+
+typedef struct _DAP_queue {
+ uint8_t USB_Request [DAP_PACKET_COUNT][DAP_PACKET_SIZE]; // Request Buffer
+ uint16_t resp_size[DAP_PACKET_COUNT]; //track the return response size
+ uint32_t free_count;
+ uint32_t send_count;
+ uint32_t recv_idx;
+ uint32_t send_idx;
+} DAP_queue;
+
+void DAP_queue_init(DAP_queue * queue);
+
+/*
+ * Get the a buffer from the DAP_queue where the response to the request is stored
+ * Parameters: queue - DAP queue, buf = return the buffer location, len = return the len of the response
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+BOOL DAP_queue_get_send_buf(DAP_queue * queue, uint8_t ** buf, int * len);
+
+/*
+ * Execute a request and store result to the DAP_queue
+ * Parameters: queue - DAP queue, reqbuf = buffer with DAP request, len = of the request buffer, retbuf = buffer to peek on the result of the DAP operation
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+BOOL DAP_queue_execute_buf(DAP_queue * queue, const uint8_t *reqbuf, int len, uint8_t ** retbuf);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/cmsis-dap/DAP_vendor.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/cmsis-dap/DAP_vendor.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,207 @@
+/*
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright 2019, Cypress Semiconductor Corporation
+ * or a subsidiary of Cypress Semiconductor Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date: 20. May 2015
+ * $Revision: V1.10
+ *
+ * Project: CMSIS-DAP Source
+ * Title: DAP_vendor.c CMSIS-DAP Vendor Commands
+ *
+ *---------------------------------------------------------------------------*/
+
+#include "rl_usb.h"
+#include "DAP_config.h"
+#include "DAP.h"
+#include "info.h"
+#include "main.h"
+#include "uart.h"
+#include "settings.h"
+#include "target_family.h"
+#include "flash_manager.h"
+#include <string.h>
+
+
+#ifdef DRAG_N_DROP_SUPPORT
+#include "file_stream.h"
+#endif
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Vendor_Adapt_gr Adapt Vendor Commands
+\ingroup DAP_Vendor_gr
+@{
+
+The file DAP_vendor.c provides template source code for extension of a Debug Unit with
+Vendor Commands. Copy this file to the project folder of the Debug Unit and add the
+file to the MDK-ARM project under the file group Configuration.
+*/
+
+/** Process DAP Vendor Command and prepare Response Data
+\param request pointer to request data
+\param response pointer to response data
+\return number of bytes in response (lower 16 bits)
+ number of bytes in request (upper 16 bits)
+*/
+uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) {
+ uint32_t num = (1U << 16) | 1U;
+
+ *response++ = *request; // copy Command ID
+
+ switch (*request++) { // first byte in request is Command ID
+ case ID_DAP_Vendor0: {
+ const char *id_str = info_get_unique_id();
+ uint8_t len = strlen(id_str);
+ *response++ = len;
+ memcpy(response, id_str, len);
+ num += (len + 1); // increment response count by ID length + length byte
+ break;
+ }
+ case ID_DAP_Vendor1: {
+ // get line coding
+ int32_t read_len = sizeof(CDC_LINE_CODING);
+ CDC_LINE_CODING cdc_line_coding;
+ USBD_CDC_ACM_PortGetLineCoding(&cdc_line_coding);
+ memcpy(response, &cdc_line_coding, read_len);
+ num += (read_len + 1);
+ break;
+ }
+ case ID_DAP_Vendor2: {
+ // set uart configuration
+ CDC_LINE_CODING cdc_line_coding;
+ USBD_CDC_ACM_PortGetLineCoding(&cdc_line_coding);
+ //set BaudRate
+ uint32_t baud_rate = 0;
+ memcpy(&baud_rate, request, sizeof(uint32_t));
+ cdc_line_coding.dwDTERate = baud_rate;
+ USBD_CDC_ACM_PortSetLineCoding(&cdc_line_coding);
+ USBD_CDC_ACM_SendBreak(0);
+ *response = 1;
+ num += (sizeof(uint32_t) << 16) | 1;
+ break;
+ }
+ case ID_DAP_Vendor3: {
+ // uart read
+ int32_t read_len = 62;
+ read_len = uart_read_data(response + 1, read_len);
+ response[0] = read_len;
+ // increment request and response count
+ num += (read_len + 1);
+ break;
+ }
+ case ID_DAP_Vendor4: {
+ // uart write
+ int32_t write_len = *request;
+ request++;
+ uart_write_data((uint8_t *)request, write_len);
+ *response = 1;
+ num += ((write_len + 1) << 16) | 1;
+ break;
+ }
+ case ID_DAP_Vendor5: break;
+ case ID_DAP_Vendor6: break;
+ case ID_DAP_Vendor7: break;
+ case ID_DAP_Vendor8: {
+ *response = 1;
+ if (0 == *request) {
+ main_usb_set_test_mode(false);
+ } else if (1 == *request) {
+ main_usb_set_test_mode(true);
+ } else {
+ *response = 0;
+ }
+ num += (1U << 16) | 1U; // increment request and response count each by 1
+ break;
+ }
+ case ID_DAP_Vendor9: {
+ // reset target
+ *response = 1;
+ if (!config_get_auto_rst()) {
+ target_set_state(RESET_RUN);
+ }
+ num += 1;
+ break;
+ }
+#ifdef DRAG_N_DROP_SUPPORT
+ case ID_DAP_Vendor10: {
+ // open mass storage device stream
+ *response = stream_open((stream_type_t)(*request));
+ num += (1 << 16) | 1;
+ break;
+ }
+ case ID_DAP_Vendor11: {
+ // close mass storage device stream
+ *response = stream_close();
+ num += 1;
+ break;
+ }
+ case ID_DAP_Vendor12: {
+ // write to mass storage device
+ uint32_t write_len = *request;
+ request++;
+ *response = stream_write((uint8_t *)request, write_len);
+ num += ((write_len + 1) << 16) | 1;
+ break;
+ }
+#endif
+ case ID_DAP_Vendor13: {
+ // switching between chip erase and page erase
+ // COMMAND(OUT Packet)
+ // BYTE 0 1000 1110 0x8D
+ // BYTE 1 Desired Mode:
+ // 0x00 - Chip Erase
+ // nonzero - Page Erase
+ // RESPONSE(IN Packet)
+ // BYTE 0
+ // 0x00 - OK
+ *response = DAP_OK;
+ if (0x00U == *request) {
+ flash_manager_set_page_erase(false);
+ } else {
+ flash_manager_set_page_erase(true);
+ }
+ num += (1U << 16) | 1U; // increment request and response count each by 1
+ break;
+ }
+ case ID_DAP_Vendor14: break;
+ case ID_DAP_Vendor15: break;
+ case ID_DAP_Vendor16: break;
+ case ID_DAP_Vendor17: break;
+ case ID_DAP_Vendor18: break;
+ case ID_DAP_Vendor19: break;
+ case ID_DAP_Vendor20: break;
+ case ID_DAP_Vendor21: break;
+ case ID_DAP_Vendor22: break;
+ case ID_DAP_Vendor23: break;
+ case ID_DAP_Vendor24: break;
+ case ID_DAP_Vendor25: break;
+ case ID_DAP_Vendor26: break;
+ case ID_DAP_Vendor27: break;
+ case ID_DAP_Vendor28: break;
+ case ID_DAP_Vendor29: break;
+ case ID_DAP_Vendor30: break;
+ case ID_DAP_Vendor31: break;
+ default: break;
+ }
+
+ return (num);
+}
+
+///@}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/cmsis-dap/JTAG_DP.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/cmsis-dap/JTAG_DP.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,370 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date: 1. December 2017
+ * $Revision: V2.0.0
+ *
+ * Project: CMSIS-DAP Source
+ * Title: JTAG_DP.c CMSIS-DAP JTAG DP I/O
+ *
+ *---------------------------------------------------------------------------*/
+
+#include "DAP_config.h"
+#include "DAP.h"
+
+
+// JTAG Macros
+
+#define PIN_TCK_SET PIN_SWCLK_TCK_SET
+#define PIN_TCK_CLR PIN_SWCLK_TCK_CLR
+#define PIN_TMS_SET PIN_SWDIO_TMS_SET
+#define PIN_TMS_CLR PIN_SWDIO_TMS_CLR
+
+#define JTAG_CYCLE_TCK() \
+ PIN_TCK_CLR(); \
+ PIN_DELAY(); \
+ PIN_TCK_SET(); \
+ PIN_DELAY()
+
+#define JTAG_CYCLE_TDI(tdi) \
+ PIN_TDI_OUT(tdi); \
+ PIN_TCK_CLR(); \
+ PIN_DELAY(); \
+ PIN_TCK_SET(); \
+ PIN_DELAY()
+
+#define JTAG_CYCLE_TDO(tdo) \
+ PIN_TCK_CLR(); \
+ PIN_DELAY(); \
+ tdo = PIN_TDO_IN(); \
+ PIN_TCK_SET(); \
+ PIN_DELAY()
+
+#define JTAG_CYCLE_TDIO(tdi,tdo) \
+ PIN_TDI_OUT(tdi); \
+ PIN_TCK_CLR(); \
+ PIN_DELAY(); \
+ tdo = PIN_TDO_IN(); \
+ PIN_TCK_SET(); \
+ PIN_DELAY()
+
+#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
+
+
+#if (DAP_JTAG != 0)
+
+
+// Generate JTAG Sequence
+// info: sequence information
+// tdi: pointer to TDI generated data
+// tdo: pointer to TDO captured data
+// return: none
+void JTAG_Sequence (uint32_t info, const uint8_t *tdi, uint8_t *tdo) {
+ uint32_t i_val;
+ uint32_t o_val;
+ uint32_t bit;
+ uint32_t n, k;
+
+ n = info & JTAG_SEQUENCE_TCK;
+ if (n == 0U) {
+ n = 64U;
+ }
+
+ if (info & JTAG_SEQUENCE_TMS) {
+ PIN_TMS_SET();
+ } else {
+ PIN_TMS_CLR();
+ }
+
+ while (n) {
+ i_val = *tdi++;
+ o_val = 0U;
+ for (k = 8U; k && n; k--, n--) {
+ JTAG_CYCLE_TDIO(i_val, bit);
+ i_val >>= 1;
+ o_val >>= 1;
+ o_val |= bit << 7;
+ }
+ o_val >>= k;
+ if (info & JTAG_SEQUENCE_TDO) {
+ *tdo++ = (uint8_t)o_val;
+ }
+ }
+}
+
+
+// JTAG Set IR
+// ir: IR value
+// return: none
+#define JTAG_IR_Function(speed) /**/ \
+static void JTAG_IR_##speed (uint32_t ir) { \
+ uint32_t n; \
+ \
+ PIN_TMS_SET(); \
+ JTAG_CYCLE_TCK(); /* Select-DR-Scan */ \
+ JTAG_CYCLE_TCK(); /* Select-IR-Scan */ \
+ PIN_TMS_CLR(); \
+ JTAG_CYCLE_TCK(); /* Capture-IR */ \
+ JTAG_CYCLE_TCK(); /* Shift-IR */ \
+ \
+ PIN_TDI_OUT(1U); \
+ for (n = DAP_Data.jtag_dev.ir_before[DAP_Data.jtag_dev.index]; n; n--) { \
+ JTAG_CYCLE_TCK(); /* Bypass before data */ \
+ } \
+ for (n = DAP_Data.jtag_dev.ir_length[DAP_Data.jtag_dev.index] - 1U; n; n--) { \
+ JTAG_CYCLE_TDI(ir); /* Set IR bits (except last) */ \
+ ir >>= 1; \
+ } \
+ n = DAP_Data.jtag_dev.ir_after[DAP_Data.jtag_dev.index]; \
+ if (n) { \
+ JTAG_CYCLE_TDI(ir); /* Set last IR bit */ \
+ PIN_TDI_OUT(1U); \
+ for (--n; n; n--) { \
+ JTAG_CYCLE_TCK(); /* Bypass after data */ \
+ } \
+ PIN_TMS_SET(); \
+ JTAG_CYCLE_TCK(); /* Bypass & Exit1-IR */ \
+ } else { \
+ PIN_TMS_SET(); \
+ JTAG_CYCLE_TDI(ir); /* Set last IR bit & Exit1-IR */ \
+ } \
+ \
+ JTAG_CYCLE_TCK(); /* Update-IR */ \
+ PIN_TMS_CLR(); \
+ JTAG_CYCLE_TCK(); /* Idle */ \
+ PIN_TDI_OUT(1U); \
+}
+
+
+// JTAG Transfer I/O
+// request: A[3:2] RnW APnDP
+// data: DATA[31:0]
+// return: ACK[2:0]
+#define JTAG_TransferFunction(speed) /**/ \
+static uint8_t JTAG_Transfer##speed (uint32_t request, uint32_t *data) { \
+ uint32_t ack; \
+ uint32_t bit; \
+ uint32_t val; \
+ uint32_t n; \
+ \
+ PIN_TMS_SET(); \
+ JTAG_CYCLE_TCK(); /* Select-DR-Scan */ \
+ PIN_TMS_CLR(); \
+ JTAG_CYCLE_TCK(); /* Capture-DR */ \
+ JTAG_CYCLE_TCK(); /* Shift-DR */ \
+ \
+ for (n = DAP_Data.jtag_dev.index; n; n--) { \
+ JTAG_CYCLE_TCK(); /* Bypass before data */ \
+ } \
+ \
+ JTAG_CYCLE_TDIO(request >> 1, bit); /* Set RnW, Get ACK.0 */ \
+ ack = bit << 1; \
+ JTAG_CYCLE_TDIO(request >> 2, bit); /* Set A2, Get ACK.1 */ \
+ ack |= bit << 0; \
+ JTAG_CYCLE_TDIO(request >> 3, bit); /* Set A3, Get ACK.2 */ \
+ ack |= bit << 2; \
+ \
+ if (ack != DAP_TRANSFER_OK) { \
+ /* Exit on error */ \
+ PIN_TMS_SET(); \
+ JTAG_CYCLE_TCK(); /* Exit1-DR */ \
+ goto exit; \
+ } \
+ \
+ if (request & DAP_TRANSFER_RnW) { \
+ /* Read Transfer */ \
+ val = 0U; \
+ for (n = 31U; n; n--) { \
+ JTAG_CYCLE_TDO(bit); /* Get D0..D30 */ \
+ val |= bit << 31; \
+ val >>= 1; \
+ } \
+ n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U; \
+ if (n) { \
+ JTAG_CYCLE_TDO(bit); /* Get D31 */ \
+ for (--n; n; n--) { \
+ JTAG_CYCLE_TCK(); /* Bypass after data */ \
+ } \
+ PIN_TMS_SET(); \
+ JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ \
+ } else { \
+ PIN_TMS_SET(); \
+ JTAG_CYCLE_TDO(bit); /* Get D31 & Exit1-DR */ \
+ } \
+ val |= bit << 31; \
+ if (data) { *data = val; } \
+ } else { \
+ /* Write Transfer */ \
+ val = *data; \
+ for (n = 31U; n; n--) { \
+ JTAG_CYCLE_TDI(val); /* Set D0..D30 */ \
+ val >>= 1; \
+ } \
+ n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U; \
+ if (n) { \
+ JTAG_CYCLE_TDI(val); /* Set D31 */ \
+ for (--n; n; n--) { \
+ JTAG_CYCLE_TCK(); /* Bypass after data */ \
+ } \
+ PIN_TMS_SET(); \
+ JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ \
+ } else { \
+ PIN_TMS_SET(); \
+ JTAG_CYCLE_TDI(val); /* Set D31 & Exit1-DR */ \
+ } \
+ } \
+ \
+exit: \
+ JTAG_CYCLE_TCK(); /* Update-DR */ \
+ PIN_TMS_CLR(); \
+ JTAG_CYCLE_TCK(); /* Idle */ \
+ PIN_TDI_OUT(1U); \
+ \
+ /* Capture Timestamp */ \
+ if (request & DAP_TRANSFER_TIMESTAMP) { \
+ DAP_Data.timestamp = TIMESTAMP_GET(); \
+ } \
+ \
+ /* Idle cycles */ \
+ n = DAP_Data.transfer.idle_cycles; \
+ while (n--) { \
+ JTAG_CYCLE_TCK(); /* Idle */ \
+ } \
+ \
+ return ((uint8_t)ack); \
+}
+
+
+#undef PIN_DELAY
+#define PIN_DELAY() PIN_DELAY_FAST()
+JTAG_IR_Function(Fast)
+JTAG_TransferFunction(Fast)
+
+#undef PIN_DELAY
+#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
+JTAG_IR_Function(Slow)
+JTAG_TransferFunction(Slow)
+
+
+// JTAG Read IDCODE register
+// return: value read
+uint32_t JTAG_ReadIDCode (void) {
+ uint32_t bit;
+ uint32_t val;
+ uint32_t n;
+
+ PIN_TMS_SET();
+ JTAG_CYCLE_TCK(); /* Select-DR-Scan */
+ PIN_TMS_CLR();
+ JTAG_CYCLE_TCK(); /* Capture-DR */
+ JTAG_CYCLE_TCK(); /* Shift-DR */
+
+ for (n = DAP_Data.jtag_dev.index; n; n--) {
+ JTAG_CYCLE_TCK(); /* Bypass before data */
+ }
+
+ val = 0U;
+ for (n = 31U; n; n--) {
+ JTAG_CYCLE_TDO(bit); /* Get D0..D30 */
+ val |= bit << 31;
+ val >>= 1;
+ }
+ PIN_TMS_SET();
+ JTAG_CYCLE_TDO(bit); /* Get D31 & Exit1-DR */
+ val |= bit << 31;
+
+ JTAG_CYCLE_TCK(); /* Update-DR */
+ PIN_TMS_CLR();
+ JTAG_CYCLE_TCK(); /* Idle */
+
+ return (val);
+}
+
+
+// JTAG Write ABORT register
+// data: value to write
+// return: none
+void JTAG_WriteAbort (uint32_t data) {
+ uint32_t n;
+
+ PIN_TMS_SET();
+ JTAG_CYCLE_TCK(); /* Select-DR-Scan */
+ PIN_TMS_CLR();
+ JTAG_CYCLE_TCK(); /* Capture-DR */
+ JTAG_CYCLE_TCK(); /* Shift-DR */
+
+ for (n = DAP_Data.jtag_dev.index; n; n--) {
+ JTAG_CYCLE_TCK(); /* Bypass before data */
+ }
+
+ PIN_TDI_OUT(0U);
+ JTAG_CYCLE_TCK(); /* Set RnW=0 (Write) */
+ JTAG_CYCLE_TCK(); /* Set A2=0 */
+ JTAG_CYCLE_TCK(); /* Set A3=0 */
+
+ for (n = 31U; n; n--) {
+ JTAG_CYCLE_TDI(data); /* Set D0..D30 */
+ data >>= 1;
+ }
+ n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U;
+ if (n) {
+ JTAG_CYCLE_TDI(data); /* Set D31 */
+ for (--n; n; n--) {
+ JTAG_CYCLE_TCK(); /* Bypass after data */
+ }
+ PIN_TMS_SET();
+ JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */
+ } else {
+ PIN_TMS_SET();
+ JTAG_CYCLE_TDI(data); /* Set D31 & Exit1-DR */
+ }
+
+ JTAG_CYCLE_TCK(); /* Update-DR */
+ PIN_TMS_CLR();
+ JTAG_CYCLE_TCK(); /* Idle */
+ PIN_TDI_OUT(1U);
+}
+
+
+// JTAG Set IR
+// ir: IR value
+// return: none
+void JTAG_IR (uint32_t ir) {
+ if (DAP_Data.fast_clock) {
+ JTAG_IR_Fast(ir);
+ } else {
+ JTAG_IR_Slow(ir);
+ }
+}
+
+
+// JTAG Transfer I/O
+// request: A[3:2] RnW APnDP
+// data: DATA[31:0]
+// return: ACK[2:0]
+uint8_t JTAG_Transfer(uint32_t request, uint32_t *data) {
+ if (DAP_Data.fast_clock) {
+ return JTAG_TransferFast(request, data);
+ } else {
+ return JTAG_TransferSlow(request, data);
+ }
+}
+
+
+#endif /* (DAP_JTAG != 0) */
diff -r 000000000000 -r 01f31e923fe2 source/daplink/cmsis-dap/SWO.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/cmsis-dap/SWO.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,800 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date: 1. December 2017
+ * $Revision: V2.0.0
+ *
+ * Project: CMSIS-DAP Source
+ * Title: SWO.c CMSIS-DAP SWO I/O
+ *
+ *---------------------------------------------------------------------------*/
+
+#include "DAP_config.h"
+#include "DAP.h"
+#if (SWO_UART != 0)
+#include "Driver_USART.h"
+#endif
+#if (SWO_STREAM != 0)
+#include "cmsis_os2.h"
+#endif
+
+#if (SWO_STREAM != 0)
+#ifdef DAP_FW_V1
+#error "SWO Streaming Trace not supported in DAP V1!"
+#endif
+#endif
+
+#if (SWO_UART != 0)
+
+#ifndef SWO_USART_PORT
+#define SWO_USART_PORT 0 /* USART Port Number */
+#endif
+
+// USART Driver
+#define _USART_Driver_(n) Driver_USART##n
+#define USART_Driver_(n) _USART_Driver_(n)
+extern ARM_DRIVER_USART USART_Driver_(SWO_USART_PORT);
+#define pUSART (&USART_Driver_(SWO_USART_PORT))
+
+static uint8_t USART_Ready = 0U;
+
+#endif /* (SWO_UART != 0) */
+
+
+#if ((SWO_UART != 0) || (SWO_MANCHESTER != 0))
+
+
+#define SWO_STREAM_TIMEOUT 50U /* Stream timeout in ms */
+
+#define USB_BLOCK_SIZE 512U /* USB Block Size */
+#define TRACE_BLOCK_SIZE 64U /* Trace Block Size (2^n: 32...512) */
+
+// Trace State
+static uint8_t TraceTransport = 0U; /* Trace Transport */
+static uint8_t TraceMode = 0U; /* Trace Mode */
+static uint8_t TraceStatus = 0U; /* Trace Status without Errors */
+static uint8_t TraceError[2] = {0U, 0U}; /* Trace Error flags (banked) */
+static uint8_t TraceError_n = 0U; /* Active Trace Error bank */
+
+// Trace Buffer
+static uint8_t TraceBuf[SWO_BUFFER_SIZE]; /* Trace Buffer (must be 2^n) */
+static volatile uint32_t TraceIndexI = 0U; /* Incoming Trace Index */
+static volatile uint32_t TraceIndexO = 0U; /* Outgoing Trace Index */
+static volatile uint8_t TraceUpdate; /* Trace Update Flag */
+static uint32_t TraceBlockSize; /* Current Trace Block Size */
+
+#if (TIMESTAMP_CLOCK != 0U)
+// Trace Timestamp
+static volatile struct {
+ uint32_t index;
+ uint32_t tick;
+} TraceTimestamp;
+#endif
+
+// Trace Helper functions
+static void ClearTrace (void);
+static void ResumeTrace (void);
+static uint32_t GetTraceCount (void);
+static uint8_t GetTraceStatus (void);
+static void SetTraceError (uint8_t flag);
+
+#if (SWO_STREAM != 0)
+extern osThreadId_t SWO_ThreadId;
+static volatile uint8_t TransferBusy = 0U; /* Transfer Busy Flag */
+static uint32_t TransferSize; /* Current Transfer Size */
+#endif
+
+
+#if (SWO_UART != 0)
+
+// USART Driver Callback function
+// event: event mask
+static void USART_Callback (uint32_t event) {
+ uint32_t index_i;
+ uint32_t index_o;
+ uint32_t count;
+ uint32_t num;
+
+ if (event & ARM_USART_EVENT_RECEIVE_COMPLETE) {
+#if (TIMESTAMP_CLOCK != 0U)
+ TraceTimestamp.tick = TIMESTAMP_GET();
+#endif
+ index_o = TraceIndexO;
+ index_i = TraceIndexI;
+ index_i += TraceBlockSize;
+ TraceIndexI = index_i;
+#if (TIMESTAMP_CLOCK != 0U)
+ TraceTimestamp.index = index_i;
+#endif
+ num = TRACE_BLOCK_SIZE - (index_i & (TRACE_BLOCK_SIZE - 1U));
+ count = index_i - index_o;
+ if (count <= (SWO_BUFFER_SIZE - num)) {
+ index_i &= SWO_BUFFER_SIZE - 1U;
+ TraceBlockSize = num;
+ pUSART->Receive(&TraceBuf[index_i], num);
+ } else {
+ TraceStatus = DAP_SWO_CAPTURE_ACTIVE | DAP_SWO_CAPTURE_PAUSED;
+ }
+ TraceUpdate = 1U;
+#if (SWO_STREAM != 0)
+ if (TraceTransport == 2U) {
+ if (count >= (USB_BLOCK_SIZE - (index_o & (USB_BLOCK_SIZE - 1U)))) {
+ osThreadFlagsSet(SWO_ThreadId, 1U);
+ }
+ }
+#endif
+ }
+ if (event & ARM_USART_EVENT_RX_OVERFLOW) {
+ SetTraceError(DAP_SWO_BUFFER_OVERRUN);
+ }
+ if (event & (ARM_USART_EVENT_RX_BREAK |
+ ARM_USART_EVENT_RX_FRAMING_ERROR |
+ ARM_USART_EVENT_RX_PARITY_ERROR)) {
+ SetTraceError(DAP_SWO_STREAM_ERROR);
+ }
+}
+
+// Enable or disable UART SWO Mode
+// enable: enable flag
+// return: 1 - Success, 0 - Error
+__WEAK uint32_t UART_SWO_Mode (uint32_t enable) {
+ int32_t status;
+
+ USART_Ready = 0U;
+
+ if (enable != 0U) {
+ status = pUSART->Initialize(USART_Callback);
+ if (status != ARM_DRIVER_OK) {
+ return (0U);
+ }
+ status = pUSART->PowerControl(ARM_POWER_FULL);
+ if (status != ARM_DRIVER_OK) {
+ pUSART->Uninitialize();
+ return (0U);
+ }
+ } else {
+ pUSART->Control(ARM_USART_CONTROL_RX, 0U);
+ pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U);
+ pUSART->PowerControl(ARM_POWER_OFF);
+ pUSART->Uninitialize();
+ }
+ return (1U);
+}
+
+// Configure UART SWO Baudrate
+// baudrate: requested baudrate
+// return: actual baudrate or 0 when not configured
+__WEAK uint32_t UART_SWO_Baudrate (uint32_t baudrate) {
+ int32_t status;
+ uint32_t index;
+ uint32_t num;
+
+ if (baudrate > SWO_UART_MAX_BAUDRATE) {
+ baudrate = SWO_UART_MAX_BAUDRATE;
+ }
+
+ if (TraceStatus & DAP_SWO_CAPTURE_ACTIVE) {
+ pUSART->Control(ARM_USART_CONTROL_RX, 0U);
+ if (pUSART->GetStatus().rx_busy) {
+ TraceIndexI += pUSART->GetRxCount();
+ pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U);
+ }
+ }
+
+ status = pUSART->Control(ARM_USART_MODE_ASYNCHRONOUS |
+ ARM_USART_DATA_BITS_8 |
+ ARM_USART_PARITY_NONE |
+ ARM_USART_STOP_BITS_1,
+ baudrate);
+
+ if (status == ARM_DRIVER_OK) {
+ USART_Ready = 1U;
+ } else {
+ USART_Ready = 0U;
+ return (0U);
+ }
+
+ if (TraceStatus & DAP_SWO_CAPTURE_ACTIVE) {
+ if ((TraceStatus & DAP_SWO_CAPTURE_PAUSED) == 0U) {
+ index = TraceIndexI & (SWO_BUFFER_SIZE - 1U);
+ num = TRACE_BLOCK_SIZE - (index & (TRACE_BLOCK_SIZE - 1U));
+ TraceBlockSize = num;
+ pUSART->Receive(&TraceBuf[index], num);
+ }
+ pUSART->Control(ARM_USART_CONTROL_RX, 1U);
+ }
+
+ return (baudrate);
+}
+
+// Control UART SWO Capture
+// active: active flag
+// return: 1 - Success, 0 - Error
+__WEAK uint32_t UART_SWO_Control (uint32_t active) {
+ int32_t status;
+
+ if (active) {
+ if (!USART_Ready) {
+ return (0U);
+ }
+ TraceBlockSize = 1U;
+ status = pUSART->Receive(&TraceBuf[0], 1U);
+ if (status != ARM_DRIVER_OK) {
+ return (0U);
+ }
+ status = pUSART->Control(ARM_USART_CONTROL_RX, 1U);
+ if (status != ARM_DRIVER_OK) {
+ return (0U);
+ }
+ } else {
+ pUSART->Control(ARM_USART_CONTROL_RX, 0U);
+ if (pUSART->GetStatus().rx_busy) {
+ TraceIndexI += pUSART->GetRxCount();
+ pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U);
+ }
+ }
+ return (1U);
+}
+
+// Start UART SWO Capture
+// buf: pointer to buffer for capturing
+// num: number of bytes to capture
+__WEAK void UART_SWO_Capture (uint8_t *buf, uint32_t num) {
+ TraceBlockSize = num;
+ pUSART->Receive(buf, num);
+}
+
+// Get UART SWO Pending Trace Count
+// return: number of pending trace data bytes
+__WEAK uint32_t UART_SWO_GetCount (void) {
+ uint32_t count;
+
+ if (pUSART->GetStatus().rx_busy) {
+ count = pUSART->GetRxCount();
+ } else {
+ count = 0U;
+ }
+ return (count);
+}
+
+#endif /* (SWO_UART != 0) */
+
+
+#if (SWO_MANCHESTER != 0)
+
+// Enable or disable Manchester SWO Mode
+// enable: enable flag
+// return: 1 - Success, 0 - Error
+__WEAK uint32_t Manchester_SWO_Mode (uint32_t enable) {
+ return (0U);
+}
+
+// Configure Manchester SWO Baudrate
+// baudrate: requested baudrate
+// return: actual baudrate or 0 when not configured
+__WEAK uint32_t Manchester_SWO_Baudrate (uint32_t baudrate) {
+ return (0U);
+}
+
+// Control Manchester SWO Capture
+// active: active flag
+// return: 1 - Success, 0 - Error
+__WEAK uint32_t Manchester_SWO_Control (uint32_t active) {
+ return (0U);
+}
+
+// Start Manchester SWO Capture
+// buf: pointer to buffer for capturing
+// num: number of bytes to capture
+__WEAK void Manchester_SWO_Capture (uint8_t *buf, uint32_t num) {
+}
+
+// Get Manchester SWO Pending Trace Count
+// return: number of pending trace data bytes
+__WEAK uint32_t Manchester_SWO_GetCount (void) {
+}
+
+#endif /* (SWO_MANCHESTER != 0) */
+
+
+// Clear Trace Errors and Data
+static void ClearTrace (void) {
+
+#if (SWO_STREAM != 0)
+ if (TraceTransport == 2U) {
+ if (TransferBusy != 0U) {
+ SWO_AbortTransfer();
+ TransferBusy = 0U;
+ }
+ }
+#endif
+
+ TraceError[0] = 0U;
+ TraceError[1] = 0U;
+ TraceError_n = 0U;
+ TraceIndexI = 0U;
+ TraceIndexO = 0U;
+
+#if (TIMESTAMP_CLOCK != 0U)
+ TraceTimestamp.index = 0U;
+ TraceTimestamp.tick = 0U;
+#endif
+}
+
+// Resume Trace Capture
+static void ResumeTrace (void) {
+ uint32_t index_i;
+ uint32_t index_o;
+
+ if (TraceStatus == (DAP_SWO_CAPTURE_ACTIVE | DAP_SWO_CAPTURE_PAUSED)) {
+ index_i = TraceIndexI;
+ index_o = TraceIndexO;
+ if ((index_i - index_o) < SWO_BUFFER_SIZE) {
+ index_i &= SWO_BUFFER_SIZE - 1U;
+ switch (TraceMode) {
+#if (SWO_UART != 0)
+ case DAP_SWO_UART:
+ TraceStatus = DAP_SWO_CAPTURE_ACTIVE;
+ UART_SWO_Capture(&TraceBuf[index_i], 1U);
+ break;
+#endif
+#if (SWO_MANCHESTER != 0)
+ case DAP_SWO_MANCHESTER:
+ TraceStatus = DAP_SWO_CAPTURE_ACTIVE;
+ Manchester_SWO_Capture(&TraceBuf[index_i], 1U);
+ break;
+#endif
+ default:
+ break;
+ }
+ }
+ }
+}
+
+// Get Trace Count
+// return: number of available data bytes in trace buffer
+static uint32_t GetTraceCount (void) {
+ uint32_t count;
+
+ if (TraceStatus == DAP_SWO_CAPTURE_ACTIVE) {
+ do {
+ TraceUpdate = 0U;
+ count = TraceIndexI - TraceIndexO;
+ switch (TraceMode) {
+#if (SWO_UART != 0)
+ case DAP_SWO_UART:
+ count += UART_SWO_GetCount();
+ break;
+#endif
+#if (SWO_MANCHESTER != 0)
+ case DAP_SWO_MANCHESTER:
+ count += Manchester_SWO_GetCount();
+ break;
+#endif
+ default:
+ break;
+ }
+ } while (TraceUpdate != 0U);
+ } else {
+ count = TraceIndexI - TraceIndexO;
+ }
+
+ return (count);
+}
+
+// Get Trace Status (clear Error flags)
+// return: Trace Status (Active flag and Error flags)
+static uint8_t GetTraceStatus (void) {
+ uint8_t status;
+ uint32_t n;
+
+ n = TraceError_n;
+ TraceError_n ^= 1U;
+ status = TraceStatus | TraceError[n];
+ TraceError[n] = 0U;
+
+ return (status);
+}
+
+// Set Trace Error flag(s)
+// flag: error flag(s) to set
+static void SetTraceError (uint8_t flag) {
+ TraceError[TraceError_n] |= flag;
+}
+
+
+// Process SWO Transport command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+uint32_t SWO_Transport (const uint8_t *request, uint8_t *response) {
+ uint8_t transport;
+ uint32_t result;
+
+ if ((TraceStatus & DAP_SWO_CAPTURE_ACTIVE) == 0U) {
+ transport = *request;
+ switch (transport) {
+ case 0U:
+ case 1U:
+#if (SWO_STREAM != 0)
+ case 2U:
+#endif
+ TraceTransport = transport;
+ result = 1U;
+ break;
+ default:
+ result = 0U;
+ break;
+ }
+ } else {
+ result = 0U;
+ }
+
+ if (result != 0U) {
+ *response = DAP_OK;
+ } else {
+ *response = DAP_ERROR;
+ }
+
+ return ((1U << 16) | 1U);
+}
+
+
+// Process SWO Mode command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+uint32_t SWO_Mode (const uint8_t *request, uint8_t *response) {
+ uint8_t mode;
+ uint32_t result;
+
+ mode = *request;
+
+ switch (TraceMode) {
+#if (SWO_UART != 0)
+ case DAP_SWO_UART:
+ UART_SWO_Mode(0U);
+ break;
+#endif
+#if (SWO_MANCHESTER != 0)
+ case DAP_SWO_MANCHESTER:
+ Manchester_SWO_Mode(0U);
+ break;
+#endif
+ default:
+ break;
+ }
+
+ switch (mode) {
+ case DAP_SWO_OFF:
+ result = 1U;
+ break;
+#if (SWO_UART != 0)
+ case DAP_SWO_UART:
+ result = UART_SWO_Mode(1U);
+ break;
+#endif
+#if (SWO_MANCHESTER != 0)
+ case DAP_SWO_MANCHESTER:
+ result = Manchester_SWO_Mode(1U);
+ break;
+#endif
+ default:
+ result = 0U;
+ break;
+ }
+ if (result != 0U) {
+ TraceMode = mode;
+ } else {
+ TraceMode = DAP_SWO_OFF;
+ }
+
+ TraceStatus = 0U;
+
+ if (result != 0U) {
+ *response = DAP_OK;
+ } else {
+ *response = DAP_ERROR;
+ }
+
+ return ((1U << 16) | 1U);
+}
+
+
+// Process SWO Baudrate command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+uint32_t SWO_Baudrate (const uint8_t *request, uint8_t *response) {
+ uint32_t baudrate;
+
+ baudrate = (uint32_t)(*(request+0) << 0) |
+ (uint32_t)(*(request+1) << 8) |
+ (uint32_t)(*(request+2) << 16) |
+ (uint32_t)(*(request+3) << 24);
+
+ switch (TraceMode) {
+#if (SWO_UART != 0)
+ case DAP_SWO_UART:
+ baudrate = UART_SWO_Baudrate(baudrate);
+ break;
+#endif
+#if (SWO_MANCHESTER != 0)
+ case DAP_SWO_MANCHESTER:
+ baudrate = Manchester_SWO_Baudrate(baudrate);
+ break;
+#endif
+ default:
+ baudrate = 0U;
+ break;
+ }
+
+ if (baudrate == 0U) {
+ TraceStatus = 0U;
+ }
+
+ *response++ = (uint8_t)(baudrate >> 0);
+ *response++ = (uint8_t)(baudrate >> 8);
+ *response++ = (uint8_t)(baudrate >> 16);
+ *response = (uint8_t)(baudrate >> 24);
+
+ return ((4U << 16) | 4U);
+}
+
+
+// Process SWO Control command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+uint32_t SWO_Control (const uint8_t *request, uint8_t *response) {
+ uint8_t active;
+ uint32_t result;
+
+ active = *request & DAP_SWO_CAPTURE_ACTIVE;
+
+ if (active != (TraceStatus & DAP_SWO_CAPTURE_ACTIVE)) {
+ if (active) {
+ ClearTrace();
+ }
+ switch (TraceMode) {
+#if (SWO_UART != 0)
+ case DAP_SWO_UART:
+ result = UART_SWO_Control(active);
+ break;
+#endif
+#if (SWO_MANCHESTER != 0)
+ case DAP_SWO_MANCHESTER:
+ result = Manchester_SWO_Control(active);
+ break;
+#endif
+ default:
+ result = 0U;
+ break;
+ }
+ if (result != 0U) {
+ TraceStatus = active;
+#if (SWO_STREAM != 0)
+ if (TraceTransport == 2U) {
+ osThreadFlagsSet(SWO_ThreadId, 1U);
+ }
+#endif
+ }
+ } else {
+ result = 1U;
+ }
+
+ if (result != 0U) {
+ *response = DAP_OK;
+ } else {
+ *response = DAP_ERROR;
+ }
+
+ return ((1U << 16) | 1U);
+}
+
+
+// Process SWO Status command and prepare response
+// response: pointer to response data
+// return: number of bytes in response
+uint32_t SWO_Status (uint8_t *response) {
+ uint8_t status;
+ uint32_t count;
+
+ status = GetTraceStatus();
+ count = GetTraceCount();
+
+ *response++ = status;
+ *response++ = (uint8_t)(count >> 0);
+ *response++ = (uint8_t)(count >> 8);
+ *response++ = (uint8_t)(count >> 16);
+ *response = (uint8_t)(count >> 24);
+
+ return (5U);
+}
+
+
+// Process SWO Extended Status command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+uint32_t SWO_ExtendedStatus (const uint8_t *request, uint8_t *response) {
+ uint8_t cmd;
+ uint8_t status;
+ uint32_t count;
+#if (TIMESTAMP_CLOCK != 0U)
+ uint32_t index;
+ uint32_t tick;
+#endif
+ uint32_t num;
+
+ num = 0U;
+ cmd = *request;
+
+ if (cmd & 0x01U) {
+ status = GetTraceStatus();
+ *response++ = status;
+ num += 1U;
+ }
+
+ if (cmd & 0x02U) {
+ count = GetTraceCount();
+ *response++ = (uint8_t)(count >> 0);
+ *response++ = (uint8_t)(count >> 8);
+ *response++ = (uint8_t)(count >> 16);
+ *response++ = (uint8_t)(count >> 24);
+ num += 4U;
+ }
+
+#if (TIMESTAMP_CLOCK != 0U)
+ if (cmd & 0x04U) {
+ do {
+ TraceUpdate = 0U;
+ index = TraceTimestamp.index;
+ tick = TraceTimestamp.tick;
+ } while (TraceUpdate != 0U);
+ *response++ = (uint8_t)(index >> 0);
+ *response++ = (uint8_t)(index >> 8);
+ *response++ = (uint8_t)(index >> 16);
+ *response++ = (uint8_t)(index >> 24);
+ *response++ = (uint8_t)(tick >> 0);
+ *response++ = (uint8_t)(tick >> 8);
+ *response++ = (uint8_t)(tick >> 16);
+ *response++ = (uint8_t)(tick >> 24);
+ num += 4U;
+ }
+#endif
+
+ return ((1U << 16) | num);
+}
+
+
+// Process SWO Data command and prepare response
+// request: pointer to request data
+// response: pointer to response data
+// return: number of bytes in response (lower 16 bits)
+// number of bytes in request (upper 16 bits)
+uint32_t SWO_Data (const uint8_t *request, uint8_t *response) {
+ uint8_t status;
+ uint32_t count;
+ uint32_t index;
+ uint32_t n, i;
+
+ status = GetTraceStatus();
+ count = GetTraceCount();
+
+ if (TraceTransport == 1U) {
+ n = (uint32_t)(*(request+0) << 0) |
+ (uint32_t)(*(request+1) << 8);
+ if (n > (DAP_PACKET_SIZE - 4U)) {
+ n = DAP_PACKET_SIZE - 4U;
+ }
+ if (count > n) {
+ count = n;
+ }
+ } else {
+ count = 0U;
+ }
+
+ *response++ = status;
+ *response++ = (uint8_t)(count >> 0);
+ *response++ = (uint8_t)(count >> 8);
+
+ if (TraceTransport == 1U) {
+ index = TraceIndexO;
+ for (i = index, n = count; n; n--) {
+ i &= SWO_BUFFER_SIZE - 1U;
+ *response++ = TraceBuf[i++];
+ }
+ TraceIndexO = index + count;
+ ResumeTrace();
+ }
+
+ return ((2U << 16) | (3U + count));
+}
+
+
+#if (SWO_STREAM != 0)
+
+// SWO Data Transfer complete callback
+void SWO_TransferComplete (void) {
+ TraceIndexO += TransferSize;
+ TransferBusy = 0U;
+ ResumeTrace();
+ osThreadFlagsSet(SWO_ThreadId, 1U);
+}
+
+// SWO Thread
+__NO_RETURN void SWO_Thread (void *argument) {
+ uint32_t timeout;
+ uint32_t flags;
+ uint32_t count;
+ uint32_t index;
+ uint32_t i, n;
+ (void) argument;
+
+ timeout = osWaitForever;
+
+ for (;;) {
+ flags = osThreadFlagsWait(1U, osFlagsWaitAny, timeout);
+ if (TraceStatus & DAP_SWO_CAPTURE_ACTIVE) {
+ timeout = SWO_STREAM_TIMEOUT;
+ } else {
+ timeout = osWaitForever;
+ flags = osFlagsErrorTimeout;
+ }
+ if (TransferBusy == 0U) {
+ count = GetTraceCount();
+ if (count != 0U) {
+ index = TraceIndexO & (SWO_BUFFER_SIZE - 1U);
+ n = SWO_BUFFER_SIZE - index;
+ if (count > n) {
+ count = n;
+ }
+ if (flags != osFlagsErrorTimeout) {
+ i = index & (USB_BLOCK_SIZE - 1U);
+ if (i == 0U) {
+ count &= ~(USB_BLOCK_SIZE - 1U);
+ } else {
+ n = USB_BLOCK_SIZE - i;
+ if (count >= n) {
+ count = n;
+ } else {
+ count = 0U;
+ }
+ }
+ }
+ if (count != 0U) {
+ TransferSize = count;
+ TransferBusy = 1U;
+ SWO_QueueTransfer(&TraceBuf[index], count);
+ }
+ }
+ }
+ }
+}
+
+#endif /* (SWO_STREAM != 0) */
+
+
+#endif /* ((SWO_UART != 0) || (SWO_MANCHESTER != 0)) */
diff -r 000000000000 -r 01f31e923fe2 source/daplink/cmsis-dap/SW_DP.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/cmsis-dap/SW_DP.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,286 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date: 1. December 2017
+ * $Revision: V2.0.0
+ *
+ * Project: CMSIS-DAP Source
+ * Title: SW_DP.c CMSIS-DAP SW DP I/O
+ *
+ *---------------------------------------------------------------------------*/
+
+#include "DAP_config.h"
+#include "DAP.h"
+
+
+// SW Macros
+
+#define PIN_SWCLK_SET PIN_SWCLK_TCK_SET
+#define PIN_SWCLK_CLR PIN_SWCLK_TCK_CLR
+
+#define SW_CLOCK_CYCLE() \
+ PIN_SWCLK_CLR(); \
+ PIN_DELAY(); \
+ PIN_SWCLK_SET(); \
+ PIN_DELAY()
+
+#define SW_WRITE_BIT(bit) \
+ PIN_SWDIO_OUT(bit); \
+ PIN_SWCLK_CLR(); \
+ PIN_DELAY(); \
+ PIN_SWCLK_SET(); \
+ PIN_DELAY()
+
+#define SW_READ_BIT(bit) \
+ PIN_SWCLK_CLR(); \
+ PIN_DELAY(); \
+ bit = PIN_SWDIO_IN(); \
+ PIN_SWCLK_SET(); \
+ PIN_DELAY()
+
+#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
+
+
+// Generate SWJ Sequence
+// count: sequence bit count
+// data: pointer to sequence bit data
+// return: none
+#if ((DAP_SWD != 0) || (DAP_JTAG != 0))
+void SWJ_Sequence (uint32_t count, const uint8_t *data) {
+ uint32_t val;
+ uint32_t n;
+
+ val = 0U;
+ n = 0U;
+ while (count--) {
+ if (n == 0U) {
+ val = *data++;
+ n = 8U;
+ }
+ if (val & 1U) {
+ PIN_SWDIO_TMS_SET();
+ } else {
+ PIN_SWDIO_TMS_CLR();
+ }
+ SW_CLOCK_CYCLE();
+ val >>= 1;
+ n--;
+ }
+}
+#endif
+
+
+// Generate SWD Sequence
+// info: sequence information
+// swdo: pointer to SWDIO generated data
+// swdi: pointer to SWDIO captured data
+// return: none
+#if (DAP_SWD != 0)
+void SWD_Sequence (uint32_t info, const uint8_t *swdo, uint8_t *swdi) {
+ uint32_t val;
+ uint32_t bit;
+ uint32_t n, k;
+
+ n = info & SWD_SEQUENCE_CLK;
+ if (n == 0U) {
+ n = 64U;
+ }
+
+ if (info & SWD_SEQUENCE_DIN) {
+ while (n) {
+ val = 0U;
+ for (k = 8U; k && n; k--, n--) {
+ SW_READ_BIT(bit);
+ val >>= 1;
+ val |= bit << 7;
+ }
+ val >>= k;
+ *swdi++ = (uint8_t)val;
+ }
+ } else {
+ while (n) {
+ val = *swdo++;
+ for (k = 8U; k && n; k--, n--) {
+ SW_WRITE_BIT(val);
+ val >>= 1;
+ }
+ }
+ }
+}
+#endif
+
+
+#if (DAP_SWD != 0)
+
+
+// SWD Transfer I/O
+// request: A[3:2] RnW APnDP
+// data: DATA[31:0]
+// return: ACK[2:0]
+#define SWD_TransferFunction(speed) /**/ \
+static uint8_t SWD_Transfer##speed (uint32_t request, uint32_t *data) { \
+ uint32_t ack; \
+ uint32_t bit; \
+ uint32_t val; \
+ uint32_t parity; \
+ \
+ uint32_t n; \
+ \
+ /* Packet Request */ \
+ parity = 0U; \
+ SW_WRITE_BIT(1U); /* Start Bit */ \
+ bit = request >> 0; \
+ SW_WRITE_BIT(bit); /* APnDP Bit */ \
+ parity += bit; \
+ bit = request >> 1; \
+ SW_WRITE_BIT(bit); /* RnW Bit */ \
+ parity += bit; \
+ bit = request >> 2; \
+ SW_WRITE_BIT(bit); /* A2 Bit */ \
+ parity += bit; \
+ bit = request >> 3; \
+ SW_WRITE_BIT(bit); /* A3 Bit */ \
+ parity += bit; \
+ SW_WRITE_BIT(parity); /* Parity Bit */ \
+ SW_WRITE_BIT(0U); /* Stop Bit */ \
+ SW_WRITE_BIT(1U); /* Park Bit */ \
+ \
+ /* Turnaround */ \
+ PIN_SWDIO_OUT_DISABLE(); \
+ for (n = DAP_Data.swd_conf.turnaround; n; n--) { \
+ SW_CLOCK_CYCLE(); \
+ } \
+ \
+ /* Acknowledge response */ \
+ SW_READ_BIT(bit); \
+ ack = bit << 0; \
+ SW_READ_BIT(bit); \
+ ack |= bit << 1; \
+ SW_READ_BIT(bit); \
+ ack |= bit << 2; \
+ \
+ if (ack == DAP_TRANSFER_OK) { /* OK response */ \
+ /* Data transfer */ \
+ if (request & DAP_TRANSFER_RnW) { \
+ /* Read data */ \
+ val = 0U; \
+ parity = 0U; \
+ for (n = 32U; n; n--) { \
+ SW_READ_BIT(bit); /* Read RDATA[0:31] */ \
+ parity += bit; \
+ val >>= 1; \
+ val |= bit << 31; \
+ } \
+ SW_READ_BIT(bit); /* Read Parity */ \
+ if ((parity ^ bit) & 1U) { \
+ ack = DAP_TRANSFER_ERROR; \
+ } \
+ if (data) { *data = val; } \
+ /* Turnaround */ \
+ for (n = DAP_Data.swd_conf.turnaround; n; n--) { \
+ SW_CLOCK_CYCLE(); \
+ } \
+ PIN_SWDIO_OUT_ENABLE(); \
+ } else { \
+ /* Turnaround */ \
+ for (n = DAP_Data.swd_conf.turnaround; n; n--) { \
+ SW_CLOCK_CYCLE(); \
+ } \
+ PIN_SWDIO_OUT_ENABLE(); \
+ /* Write data */ \
+ val = *data; \
+ parity = 0U; \
+ for (n = 32U; n; n--) { \
+ SW_WRITE_BIT(val); /* Write WDATA[0:31] */ \
+ parity += val; \
+ val >>= 1; \
+ } \
+ SW_WRITE_BIT(parity); /* Write Parity Bit */ \
+ } \
+ /* Capture Timestamp */ \
+ if (request & DAP_TRANSFER_TIMESTAMP) { \
+ DAP_Data.timestamp = TIMESTAMP_GET(); \
+ } \
+ /* Idle cycles */ \
+ n = DAP_Data.transfer.idle_cycles; \
+ if (n) { \
+ PIN_SWDIO_OUT(0U); \
+ for (; n; n--) { \
+ SW_CLOCK_CYCLE(); \
+ } \
+ } \
+ PIN_SWDIO_OUT(1U); \
+ return ((uint8_t)ack); \
+ } \
+ \
+ if ((ack == DAP_TRANSFER_WAIT) || (ack == DAP_TRANSFER_FAULT)) { \
+ /* WAIT or FAULT response */ \
+ if (DAP_Data.swd_conf.data_phase && ((request & DAP_TRANSFER_RnW) != 0U)) { \
+ for (n = 32U+1U; n; n--) { \
+ SW_CLOCK_CYCLE(); /* Dummy Read RDATA[0:31] + Parity */ \
+ } \
+ } \
+ /* Turnaround */ \
+ for (n = DAP_Data.swd_conf.turnaround; n; n--) { \
+ SW_CLOCK_CYCLE(); \
+ } \
+ PIN_SWDIO_OUT_ENABLE(); \
+ if (DAP_Data.swd_conf.data_phase && ((request & DAP_TRANSFER_RnW) == 0U)) { \
+ PIN_SWDIO_OUT(0U); \
+ for (n = 32U+1U; n; n--) { \
+ SW_CLOCK_CYCLE(); /* Dummy Write WDATA[0:31] + Parity */ \
+ } \
+ } \
+ PIN_SWDIO_OUT(1U); \
+ return ((uint8_t)ack); \
+ } \
+ \
+ /* Protocol error */ \
+ for (n = DAP_Data.swd_conf.turnaround + 32U + 1U; n; n--) { \
+ SW_CLOCK_CYCLE(); /* Back off data phase */ \
+ } \
+ PIN_SWDIO_OUT_ENABLE(); \
+ PIN_SWDIO_OUT(1U); \
+ return ((uint8_t)ack); \
+}
+
+
+#undef PIN_DELAY
+#define PIN_DELAY() PIN_DELAY_FAST()
+SWD_TransferFunction(Fast)
+
+#undef PIN_DELAY
+#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
+SWD_TransferFunction(Slow)
+
+
+// SWD Transfer I/O
+// request: A[3:2] RnW APnDP
+// data: DATA[31:0]
+// return: ACK[2:0]
+uint8_t SWD_Transfer(uint32_t request, uint32_t *data) {
+ if (DAP_Data.fast_clock) {
+ return SWD_TransferFast(request, data);
+ } else {
+ return SWD_TransferSlow(request, data);
+ }
+}
+
+
+#endif /* (DAP_SWD != 0) */
diff -r 000000000000 -r 01f31e923fe2 source/daplink/cmsis-dap/dap_strings.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/cmsis-dap/dap_strings.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,62 @@
+/**
+ * @file dap_strings.h
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "cmsis_compiler.h"
+#include "info.h"
+
+/** Get Vendor ID string.
+\param str Pointer to buffer to store the string.
+\return String length.
+*/
+__STATIC_INLINE uint8_t DAP_GetVendorString (char *str) {
+ (void)str;
+ return (0U);
+}
+
+/** Get Product ID string.
+\param str Pointer to buffer to store the string.
+\return String length.
+*/
+__STATIC_INLINE uint8_t DAP_GetProductString (char *str) {
+ (void)str;
+ return (0U);
+}
+
+/** Get Serial Number string.
+\param str Pointer to buffer to store the string.
+\return String length.
+*/
+__STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) {
+ const char * data = info_get_unique_id();
+ uint8_t length = (uint8_t)strlen(data) + 1;
+ memcpy(str, data, length);
+ return length;
+}
+
+/** Get firmware version string.
+\param str Pointer to buffer to store the string.
+\return String length.
+*/
+__STATIC_INLINE uint8_t DAP_GetFirmwareVersionString (char *str) {
+ const char * data = info_get_version();
+ uint8_t length = (uint8_t)strlen(data) + 1;
+ memcpy(str, data, length);
+ return length;
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/cmsis-dap/debug_ca.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/daplink/cmsis-dap/debug_ca.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,147 @@ +/** + * @file debug_ca.h + * @brief Access to ARM DAP (Cortex-A) using CMSIS-DAP protocol + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef DEBUG_CA_H +#define DEBUG_CA_H + +#include "debug_cm.h" + +// Debug registers +#define DEBUG_REGSITER_BASE (0x80030000) + +#define DBGDIDR (DEBUG_REGSITER_BASE + (0 * 4)) // Debug ID +#define DBGWFAR (DEBUG_REGSITER_BASE + (6 * 4)) // Watchpoint Fault Address +#define DBGVCR (DEBUG_REGSITER_BASE + (7 * 4)) // Vector Catch +#define DBGECR (DEBUG_REGSITER_BASE + (9 * 4)) // Event Catch +#define DBGDTRRX (DEBUG_REGSITER_BASE + (32 * 4)) // Host to Target Data Transfer +#define DBGITR (DEBUG_REGSITER_BASE + (33 * 4)) // WO Instruction Transfer +#define DBGDSCR (DEBUG_REGSITER_BASE + (34 * 4)) // Debug Status and Control +#define DBGDTRTX (DEBUG_REGSITER_BASE + (35 * 4)) // Target to Host Data Transfer +#define DBGDRCR (DEBUG_REGSITER_BASE + (36 * 4)) // Debug Run Control +#define DBGEACR (DEBUG_REGSITER_BASE + (37 * 4)) // External Auxiliary Control +#define DBGPCSR (DEBUG_REGSITER_BASE + (40 * 4)) // Program Counter Sampling +#define DBGCIDSR (DEBUG_REGSITER_BASE + (41 * 4)) // Context ID Sampling +#define DBGVIDSR (DEBUG_REGSITER_BASE + (42 * 4)) // Virtualization ID Sampling +#define DBGBVR0 (DEBUG_REGSITER_BASE + (64 * 4)) // Breakpoint Value +#define DBGBVR1 (DEBUG_REGSITER_BASE + (65 * 4)) // Breakpoint Value +#define DBGBVR2 (DEBUG_REGSITER_BASE + (66 * 4)) // Breakpoint Value +#define DBGBVR3 (DEBUG_REGSITER_BASE + (67 * 4)) // Breakpoint Value +#define DBGBVR4 (DEBUG_REGSITER_BASE + (68 * 4)) // Breakpoint Value +#define DBGBVR5 (DEBUG_REGSITER_BASE + (69 * 4)) // Breakpoint Value +#define DBGBVR6 (DEBUG_REGSITER_BASE + (70 * 4)) // Breakpoint Value +#define DBGBVR7 (DEBUG_REGSITER_BASE + (71 * 4)) // Breakpoint Value +#define DBGBVR8 (DEBUG_REGSITER_BASE + (72 * 4)) // Breakpoint Value +#define DBGBVR9 (DEBUG_REGSITER_BASE + (73 * 4)) // Breakpoint Value +#define DBGBVR10 (DEBUG_REGSITER_BASE + (74 * 4)) // Breakpoint Value +#define DBGBVR11 (DEBUG_REGSITER_BASE + (75 * 4)) // Breakpoint Value +#define DBGBVR12 (DEBUG_REGSITER_BASE + (76 * 4)) // Breakpoint Value +#define DBGBVR13 (DEBUG_REGSITER_BASE + (77 * 4)) // Breakpoint Value +#define DBGBVR14 (DEBUG_REGSITER_BASE + (78 * 4)) // Breakpoint Value +#define DBGBVR15 (DEBUG_REGSITER_BASE + (79 * 4)) // Breakpoint Value +#define DBGBCR0 (DEBUG_REGSITER_BASE + (80 * 4)) // Breakpoint Control +#define DBGBCR1 (DEBUG_REGSITER_BASE + (81 * 4)) // Breakpoint Control +#define DBGBCR2 (DEBUG_REGSITER_BASE + (82 * 4)) // Breakpoint Control +#define DBGBCR3 (DEBUG_REGSITER_BASE + (83 * 4)) // Breakpoint Control +#define DBGBCR4 (DEBUG_REGSITER_BASE + (84 * 4)) // Breakpoint Control +#define DBGBCR5 (DEBUG_REGSITER_BASE + (85 * 4)) // Breakpoint Control +#define DBGBCR6 (DEBUG_REGSITER_BASE + (86 * 4)) // Breakpoint Control +#define DBGBCR7 (DEBUG_REGSITER_BASE + (87 * 4)) // Breakpoint Control +#define DBGBCR8 (DEBUG_REGSITER_BASE + (88 * 4)) // Breakpoint Control +#define DBGBCR9 (DEBUG_REGSITER_BASE + (89 * 4)) // Breakpoint Control +#define DBGBCR10 (DEBUG_REGSITER_BASE + (90 * 4)) // Breakpoint Control +#define DBGBCR11 (DEBUG_REGSITER_BASE + (91 * 4)) // Breakpoint Control +#define DBGBCR12 (DEBUG_REGSITER_BASE + (92 * 4)) // Breakpoint Control +#define DBGBCR13 (DEBUG_REGSITER_BASE + (93 * 4)) // Breakpoint Control +#define DBGBCR14 (DEBUG_REGSITER_BASE + (94 * 4)) // Breakpoint Control +#define DBGBCR15 (DEBUG_REGSITER_BASE + (95 * 4)) // Breakpoint Control +#define DBGWVR0 (DEBUG_REGSITER_BASE + (96 * 4)) // Watchpoint Value +#define DBGWVR1 (DEBUG_REGSITER_BASE + (97 * 4)) // Watchpoint Value +#define DBGWVR2 (DEBUG_REGSITER_BASE + (98 * 4)) // Watchpoint Value +#define DBGWVR3 (DEBUG_REGSITER_BASE + (99 * 4)) // Watchpoint Value +#define DBGWVR4 (DEBUG_REGSITER_BASE + (100 * 4)) // Watchpoint Value +#define DBGWVR5 (DEBUG_REGSITER_BASE + (101 * 4)) // Watchpoint Value +#define DBGWVR6 (DEBUG_REGSITER_BASE + (102 * 4)) // Watchpoint Value +#define DBGWVR7 (DEBUG_REGSITER_BASE + (103 * 4)) // Watchpoint Value +#define DBGWVR8 (DEBUG_REGSITER_BASE + (104 * 4)) // Watchpoint Value +#define DBGWVR9 (DEBUG_REGSITER_BASE + (105 * 4)) // Watchpoint Value +#define DBGWVR10 (DEBUG_REGSITER_BASE + (106 * 4)) // Watchpoint Value +#define DBGWVR11 (DEBUG_REGSITER_BASE + (107 * 4)) // Watchpoint Value +#define DBGWVR12 (DEBUG_REGSITER_BASE + (108 * 4)) // Watchpoint Value +#define DBGWVR13 (DEBUG_REGSITER_BASE + (109 * 4)) // Watchpoint Value +#define DBGWVR14 (DEBUG_REGSITER_BASE + (110 * 4)) // Watchpoint Value +#define DBGWVR15 (DEBUG_REGSITER_BASE + (111 * 4)) // Watchpoint Value +#define DBGWCR0 (DEBUG_REGSITER_BASE + (112 * 4)) // Watchpoint Control +#define DBGWCR1 (DEBUG_REGSITER_BASE + (113 * 4)) // Watchpoint Control +#define DBGWCR2 (DEBUG_REGSITER_BASE + (114 * 4)) // Watchpoint Control +#define DBGWCR3 (DEBUG_REGSITER_BASE + (115 * 4)) // Watchpoint Control +#define DBGWCR4 (DEBUG_REGSITER_BASE + (116 * 4)) // Watchpoint Control +#define DBGWCR5 (DEBUG_REGSITER_BASE + (117 * 4)) // Watchpoint Control +#define DBGWCR6 (DEBUG_REGSITER_BASE + (118 * 4)) // Watchpoint Control +#define DBGWCR7 (DEBUG_REGSITER_BASE + (119 * 4)) // Watchpoint Control +#define DBGWCR8 (DEBUG_REGSITER_BASE + (120 * 4)) // Watchpoint Control +#define DBGWCR9 (DEBUG_REGSITER_BASE + (121 * 4)) // Watchpoint Control +#define DBGWCR10 (DEBUG_REGSITER_BASE + (122 * 4)) // Watchpoint Control +#define DBGWCR11 (DEBUG_REGSITER_BASE + (123 * 4)) // Watchpoint Control +#define DBGWCR12 (DEBUG_REGSITER_BASE + (124 * 4)) // Watchpoint Control +#define DBGWCR13 (DEBUG_REGSITER_BASE + (125 * 4)) // Watchpoint Control +#define DBGWCR14 (DEBUG_REGSITER_BASE + (126 * 4)) // Watchpoint Control +#define DBGWCR15 (DEBUG_REGSITER_BASE + (127 * 4)) // Watchpoint Control +#define DBGBXVR0 (DEBUG_REGSITER_BASE + (144 * 4)) // Breakpoint Extended Valueb +#define DBGBXVR1 (DEBUG_REGSITER_BASE + (145 * 4)) // Breakpoint Extended Valueb +#define DBGBXVR2 (DEBUG_REGSITER_BASE + (146 * 4)) // Breakpoint Extended Valueb +#define DBGBXVR3 (DEBUG_REGSITER_BASE + (147 * 4)) // Breakpoint Extended Valueb +#define DBGBXVR4 (DEBUG_REGSITER_BASE + (148 * 4)) // Breakpoint Extended Valueb +#define DBGBXVR5 (DEBUG_REGSITER_BASE + (149 * 4)) // Breakpoint Extended Valueb +#define DBGBXVR6 (DEBUG_REGSITER_BASE + (150 * 4)) // Breakpoint Extended Valueb +#define DBGBXVR7 (DEBUG_REGSITER_BASE + (151 * 4)) // Breakpoint Extended Valueb +#define DBGBXVR8 (DEBUG_REGSITER_BASE + (152 * 4)) // Breakpoint Extended Valueb +#define DBGBXVR9 (DEBUG_REGSITER_BASE + (153 * 4)) // Breakpoint Extended Valueb +#define DBGBXVR10 (DEBUG_REGSITER_BASE + (154 * 4)) // Breakpoint Extended Valueb +#define DBGBXVR11 (DEBUG_REGSITER_BASE + (155 * 4)) // Breakpoint Extended Valueb +#define DBGBXVR12 (DEBUG_REGSITER_BASE + (156 * 4)) // Breakpoint Extended Valueb +#define DBGBXVR13 (DEBUG_REGSITER_BASE + (157 * 4)) // Breakpoint Extended Valueb +#define DBGBXVR14 (DEBUG_REGSITER_BASE + (158 * 4)) // Breakpoint Extended Valueb +#define DBGBXVR15 (DEBUG_REGSITER_BASE + (159 * 4)) // Breakpoint Extended Valueb +#define DBGOSLAR (DEBUG_REGSITER_BASE + (192 * 4)) // OS Lock Access +#define DBGOSLSR (DEBUG_REGSITER_BASE + (193 * 4)) // OS Lock Status +#define DBGPRCR (DEBUG_REGSITER_BASE + (196 * 4)) // Powerdown and Reset Control +#define DBGPRSR (DEBUG_REGSITER_BASE + (197 * 4)) // Powerdown and Reset Status +#define DBGITCTRL (DEBUG_REGSITER_BASE + (960 * 4)) // Integration Mode Control +#define DBGCLAIMSET (DEBUG_REGSITER_BASE + (1000 * 4)) // Claim Tag Set +#define DBGCLAIMCLR (DEBUG_REGSITER_BASE + (1001 * 4)) // Claim Tag Clear +#define DBGLAR (DEBUG_REGSITER_BASE + (1004 * 4)) // Lock Access +#define DBGLSR (DEBUG_REGSITER_BASE + (1005 * 4)) // Lock Status +#define DBGAUTHSTATUS (DEBUG_REGSITER_BASE + (1006 * 4)) // Authentication Status +#define DBGDEVID2 (DEBUG_REGSITER_BASE + (1008 * 4)) // Debug Device ID 2 +#define DBGDEVID1 (DEBUG_REGSITER_BASE + (1009 * 4)) // Debug Device ID 1 +#define DBGDEVID (DEBUG_REGSITER_BASE + (1010 * 4)) // Debug Device ID +#define DBGDEVTYPE (DEBUG_REGSITER_BASE + (1011 * 4)) // Device Type +#define DBGPID0 (DEBUG_REGSITER_BASE + (1012 * 4)) // Debug Peripheral ID +#define DBGPID1 (DEBUG_REGSITER_BASE + (1013 * 4)) // Debug Peripheral ID +#define DBGPID2 (DEBUG_REGSITER_BASE + (1014 * 4)) // Debug Peripheral ID +#define DBGPID3 (DEBUG_REGSITER_BASE + (1015 * 4)) // Debug Peripheral ID +#define DBGPID4 (DEBUG_REGSITER_BASE + (1016 * 4)) // Debug Peripheral ID +#define DBGCID0 (DEBUG_REGSITER_BASE + (1020 * 4)) // Debug Component ID +#define DBGCID1 (DEBUG_REGSITER_BASE + (1021 * 4)) // Debug Component ID +#define DBGCID2 (DEBUG_REGSITER_BASE + (1022 * 4)) // Debug Component ID +#define DBGCID3 (DEBUG_REGSITER_BASE + (1023 * 4)) // Debug Component ID + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/cmsis-dap/debug_cm.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/daplink/cmsis-dap/debug_cm.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,168 @@ +/** + * @file debug_cm.h + * @brief Access to ARM DAP (Cortex-M) using CMSIS-DAP protocol + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef DEBUG_CM_H +#define DEBUG_CM_H + +#include "DAP.h" + +// SWD register access +#define SWD_REG_AP (1) +#define SWD_REG_DP (0) +#define SWD_REG_R (1<<1) +#define SWD_REG_W (0<<1) +#define SWD_REG_ADR(a) (a & 0x0c) + +// Abort Register definitions +#define DAPABORT 0x00000001 // DAP Abort +#define STKCMPCLR 0x00000002 // Clear STICKYCMP Flag (SW Only) +#define STKERRCLR 0x00000004 // Clear STICKYERR Flag (SW Only) +#define WDERRCLR 0x00000008 // Clear WDATAERR Flag (SW Only) +#define ORUNERRCLR 0x00000010 // Clear STICKYORUN Flag (SW Only) + +// Debug Control and Status definitions +#define ORUNDETECT 0x00000001 // Overrun Detect +#define STICKYORUN 0x00000002 // Sticky Overrun +#define TRNMODE 0x0000000C // Transfer Mode Mask +#define TRNNORMAL 0x00000000 // Transfer Mode: Normal +#define TRNVERIFY 0x00000004 // Transfer Mode: Pushed Verify +#define TRNCOMPARE 0x00000008 // Transfer Mode: Pushed Compare +#define STICKYCMP 0x00000010 // Sticky Compare +#define STICKYERR 0x00000020 // Sticky Error +#define READOK 0x00000040 // Read OK (SW Only) +#define WDATAERR 0x00000080 // Write Data Error (SW Only) +#define MASKLANE 0x00000F00 // Mask Lane Mask +#define MASKLANE0 0x00000100 // Mask Lane 0 +#define MASKLANE1 0x00000200 // Mask Lane 1 +#define MASKLANE2 0x00000400 // Mask Lane 2 +#define MASKLANE3 0x00000800 // Mask Lane 3 +#define TRNCNT 0x001FF000 // Transaction Counter Mask +#define CDBGRSTREQ 0x04000000 // Debug Reset Request +#define CDBGRSTACK 0x08000000 // Debug Reset Acknowledge +#define CDBGPWRUPREQ 0x10000000 // Debug Power-up Request +#define CDBGPWRUPACK 0x20000000 // Debug Power-up Acknowledge +#define CSYSPWRUPREQ 0x40000000 // System Power-up Request +#define CSYSPWRUPACK 0x80000000 // System Power-up Acknowledge + +// Debug Select Register definitions +#define CTRLSEL 0x00000001 // CTRLSEL (SW Only) +#define APBANKSEL 0x000000F0 // APBANKSEL Mask +#define APSEL 0xFF000000 // APSEL Mask + +// Access Port Register Addresses +#define AP_CSW 0x00 // Control and Status Word +#define AP_TAR 0x04 // Transfer Address +#define AP_DRW 0x0C // Data Read/Write +#define AP_BD0 0x10 // Banked Data 0 +#define AP_BD1 0x14 // Banked Data 1 +#define AP_BD2 0x18 // Banked Data 2 +#define AP_BD3 0x1C // Banked Data 3 +#define AP_ROM 0xF8 // Debug ROM Address +#define AP_IDR 0xFC // Identification Register + +// AP Control and Status Word definitions +#define CSW_SIZE 0x00000007 // Access Size: Selection Mask +#define CSW_SIZE8 0x00000000 // Access Size: 8-bit +#define CSW_SIZE16 0x00000001 // Access Size: 16-bit +#define CSW_SIZE32 0x00000002 // Access Size: 32-bit +#define CSW_ADDRINC 0x00000030 // Auto Address Increment Mask +#define CSW_NADDRINC 0x00000000 // No Address Increment +#define CSW_SADDRINC 0x00000010 // Single Address Increment +#define CSW_PADDRINC 0x00000020 // Packed Address Increment +#define CSW_DBGSTAT 0x00000040 // Debug Status +#define CSW_TINPROG 0x00000080 // Transfer in progress +#define CSW_HPROT 0x02000000 // User/Privilege Control +#define CSW_MSTRTYPE 0x20000000 // Master Type Mask +#define CSW_MSTRCORE 0x00000000 // Master Type: Core +#define CSW_MSTRDBG 0x20000000 // Master Type: Debug +#define CSW_RESERVED 0x01000000 // Reserved Value + +// Core Debug Register Address Offsets +#define DBG_OFS 0x0DF0 // Debug Register Offset inside NVIC +#define DBG_HCSR_OFS 0x00 // Debug Halting Control & Status Register +#define DBG_CRSR_OFS 0x04 // Debug Core Register Selector Register +#define DBG_CRDR_OFS 0x08 // Debug Core Register Data Register +#define DBG_EMCR_OFS 0x0C // Debug Exception & Monitor Control Register + +// Core Debug Register Addresses +#define DBG_HCSR (DBG_Addr + DBG_HCSR_OFS) +#define DBG_CRSR (DBG_Addr + DBG_CRSR_OFS) +#define DBG_CRDR (DBG_Addr + DBG_CRDR_OFS) +#define DBG_EMCR (DBG_Addr + DBG_EMCR_OFS) + +// Debug Halting Control and Status Register definitions +#define C_DEBUGEN 0x00000001 // Debug Enable +#define C_HALT 0x00000002 // Halt +#define C_STEP 0x00000004 // Step +#define C_MASKINTS 0x00000008 // Mask Interrupts +#define C_SNAPSTALL 0x00000020 // Snap Stall +#define S_REGRDY 0x00010000 // Register R/W Ready Flag +#define S_HALT 0x00020000 // Halt Flag +#define S_SLEEP 0x00040000 // Sleep Flag +#define S_LOCKUP 0x00080000 // Lockup Flag +#define S_RETIRE_ST 0x01000000 // Sticky Retire Flag +#define S_RESET_ST 0x02000000 // Sticky Reset Flag +#define DBGKEY 0xA05F0000 // Debug Key + +// Debug Exception and Monitor Control Register definitions +#define VC_CORERESET 0x00000001 // Reset Vector Catch +#define VC_MMERR 0x00000010 // Debug Trap on MMU Fault +#define VC_NOCPERR 0x00000020 // Debug Trap on No Coprocessor Fault +#define VC_CHKERR 0x00000040 // Debug Trap on Checking Error Fault +#define VC_STATERR 0x00000080 // Debug Trap on State Error Fault +#define VC_BUSERR 0x00000100 // Debug Trap on Bus Error Fault +#define VC_INTERR 0x00000200 // Debug Trap on Interrupt Error Fault +#define VC_HARDERR 0x00000400 // Debug Trap on Hard Fault +#define MON_EN 0x00010000 // Monitor Enable +#define MON_PEND 0x00020000 // Monitor Pend +#define MON_STEP 0x00040000 // Monitor Step +#define MON_REQ 0x00080000 // Monitor Request +#define TRCENA 0x01000000 // Trace Enable (DWT, ITM, ETM, TPIU) + +// NVIC: Interrupt Controller Type Register +#define NVIC_ICT (NVIC_Addr + 0x0004) +#define INTLINESNUM 0x0000001F // Interrupt Line Numbers + +// NVIC: CPUID Base Register +#define NVIC_CPUID (NVIC_Addr + 0x0D00) +#define CPUID_PARTNO 0x0000FFF0 // Part Number Mask +#define CPUID_REVISION 0x0000000F // Revision Mask +#define CPUID_VARIANT 0x00F00000 // Variant Mask + +// NVIC: Application Interrupt/Reset Control Register +#define NVIC_AIRCR (NVIC_Addr + 0x0D0C) +#define VECTRESET 0x00000001 // Reset Cortex-M (except Debug) +#define VECTCLRACTIVE 0x00000002 // Clear Active Vector Bit +#define SYSRESETREQ 0x00000004 // Reset System (except Debug) +#define VECTKEY 0x05FA0000 // Write Key + +// NVIC: Debug Fault Status Register +#define NVIC_DFSR (NVIC_Addr + 0x0D30) +#define HALTED 0x00000001 // Halt Flag +#define BKPT 0x00000002 // BKPT Flag +#define DWTTRAP 0x00000004 // DWT Match +#define VCATCH 0x00000008 // Vector Catch Flag +#define EXTERNAL 0x00000010 // External Debug Request + +// Data Watchpoint and Trace unit +#define DWT_PCSR 0xe000101c // DWT PC Sampling Register + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/compiler.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/compiler.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,46 @@
+/**
+ * @file compiler.h
+ * @brief Special asserts and macros
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef COMPILER_H
+#define COMPILER_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define COMPILER_CONCAT_(a, b) a##b
+#define COMPILER_CONCAT(a, b) COMPILER_CONCAT_(a, b)
+
+// Divide by zero if the the expression is false. This
+// causes an error at compile time.
+//
+// The special value '__COUNTER__' is used to create a unique value to
+// append to 'compiler_assert_' to create a unique token. This prevents
+// conflicts resulting from the same enum being declared multiple times.
+#define COMPILER_ASSERT(e) enum { COMPILER_CONCAT(compiler_assert_, __COUNTER__) = 1/((e) ? 1 : 0) }
+
+#define __at(_addr) __attribute__ ((at(_addr)))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/cortex_m.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/cortex_m.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,28 @@
+/**
+ * @file cortex_m.c
+ * @brief ARM Cortex-Mx cpu functions
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "cortex_m.h"
+
+__attribute__((weak))
+void SystemReset(void)
+{
+ NVIC_SystemReset();
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/cortex_m.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/cortex_m.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,64 @@
+/**
+ * @file cortex_m.h
+ * @brief ARM Cortex-Mx cpu state helper functions
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef CORTEX_M_H
+#define CORTEX_M_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "IO_Config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef int cortex_int_state_t;
+
+__attribute__((always_inline))
+static cortex_int_state_t cortex_int_get_and_disable(void)
+{
+ cortex_int_state_t state;
+ state = __disable_irq();
+ return state;
+}
+
+__attribute__((always_inline))
+static void cortex_int_restore(cortex_int_state_t state)
+{
+ if (!state) {
+ __enable_irq();
+ }
+}
+
+__attribute__((always_inline))
+static bool cortex_in_isr(void)
+{
+ return (__get_xPSR() & 0x1F) != 0;
+}
+
+extern void SystemReset(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/crc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/crc.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,38 @@
+/**********************************************************************
+ *
+ * Filename: crc.h
+ *
+ * Description: A header file describing the various CRC standards.
+ *
+ * Notes:
+ *
+ *
+ * Copyright (c) 2000 by Michael Barr. This software is placed into
+ * the public domain and may be used for any purpose. However, this
+ * notice must not be changed or removed and no warranty is either
+ * expressed or implied by its publication or distribution.
+ **********************************************************************/
+
+/**
+ * @file crc.h
+ * @brief CRC functions
+ */
+
+#ifndef _crc_h
+#define _crc_h
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+uint16_t crc16(const void *data, int nBytes);
+uint32_t crc32(const void *data, int nBytes);
+uint32_t crc32_continue(uint32_t prev_crc, const void *data, int nBytes);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/crc16.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/crc16.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,144 @@
+/**********************************************************************
+ *
+ * Filename: crc.c
+ *
+ * Description: Slow and fast implementations of the CRC standards.
+ *
+ * Notes: The parameters for each supported CRC standard are
+ * defined in the header file crc.h. The implementations
+ * here should stand up to further additions to that list.
+ *
+ *
+ * Copyright (c) 2000 by Michael Barr. This software is placed into
+ * the public domain and may be used for any purpose. However, this
+ * notice must not be changed or removed and no warranty is either
+ * expressed or implied by its publication or distribution.
+ **********************************************************************/
+
+/**
+ * @file crc16.c
+ * @brief Implementation of crc.h
+ */
+
+#include "crc.h"
+
+#define FALSE 0
+#define TRUE !FALSE
+
+typedef unsigned short crc;
+
+#define CRC_NAME "CRC-16"
+#define POLYNOMIAL 0x8005
+#define INITIAL_REMAINDER 0x0000
+#define FINAL_XOR_VALUE 0x0000
+#define REFLECT_DATA TRUE
+#define REFLECT_REMAINDER TRUE
+#define CHECK_VALUE 0xBB3D
+
+/*
+ * Derive parameters from the standard-specific parameters in crc.h.
+ */
+#define WIDTH (8 * sizeof(crc))
+#define TOPBIT (1 << (WIDTH - 1))
+
+#if (REFLECT_DATA == TRUE)
+#undef REFLECT_DATA
+#define REFLECT_DATA(X) ((unsigned char) reflect((X), 8))
+#else
+#undef REFLECT_DATA
+#define REFLECT_DATA(X) (X)
+#endif
+
+#if (REFLECT_REMAINDER == TRUE)
+#undef REFLECT_REMAINDER
+#define REFLECT_REMAINDER(X) ((crc) reflect((X), WIDTH))
+#else
+#undef REFLECT_REMAINDER
+#define REFLECT_REMAINDER(X) (X)
+#endif
+
+
+/*********************************************************************
+ *
+ * Function: reflect()
+ *
+ * Description: Reorder the bits of a binary sequence, by reflecting
+ * them about the middle position.
+ *
+ * Notes: No checking is done that nBits <= 32.
+ *
+ * Returns: The reflection of the original data.
+ *
+ *********************************************************************/
+static unsigned long
+reflect(unsigned long data, unsigned char nBits)
+{
+ unsigned long reflection = 0x00000000;
+ unsigned char bit;
+
+ /*
+ * Reflect the data about the center bit.
+ */
+ for (bit = 0; bit < nBits; ++bit) {
+ /*
+ * If the LSB bit is set, set the reflection of it.
+ */
+ if (data & 0x01) {
+ reflection |= (1 << ((nBits - 1) - bit));
+ }
+
+ data = (data >> 1);
+ }
+
+ return (reflection);
+} /* reflect() */
+
+
+/*********************************************************************
+ *
+ * Function: crcSlow()
+ *
+ * Description: Compute the CRC of a given message.
+ *
+ * Notes:
+ *
+ * Returns: The CRC of the message.
+ *
+ *********************************************************************/
+uint16_t
+crc16(const void *data, int nBytes)
+{
+ crc remainder = INITIAL_REMAINDER;
+ int byte;
+ unsigned char bit;
+ unsigned char const *message = data;
+
+ /*
+ * Perform modulo-2 division, a byte at a time.
+ */
+ for (byte = 0; byte < nBytes; ++byte) {
+ /*
+ * Bring the next byte into the remainder.
+ */
+ remainder ^= (REFLECT_DATA(message[byte]) << (WIDTH - 8));
+
+ /*
+ * Perform modulo-2 division, a bit at a time.
+ */
+ for (bit = 8; bit > 0; --bit) {
+ /*
+ * Try to divide the current data bit.
+ */
+ if (remainder & TOPBIT) {
+ remainder = (remainder << 1) ^ POLYNOMIAL;
+ } else {
+ remainder = (remainder << 1);
+ }
+ }
+ }
+
+ /*
+ * The final remainder is the CRC result.
+ */
+ return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE);
+} /* crcSlow() */
diff -r 000000000000 -r 01f31e923fe2 source/daplink/crc32.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/crc32.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,193 @@
+/**********************************************************************
+ *
+ * Filename: crc.c
+ *
+ * Description: Slow and fast implementations of the CRC standards.
+ *
+ * Notes: The parameters for each supported CRC standard are
+ * defined in the header file crc.h. The implementations
+ * here should stand up to further additions to that list.
+ *
+ *
+ * Copyright (c) 2000 by Michael Barr. This software is placed into
+ * the public domain and may be used for any purpose. However, this
+ * notice must not be changed or removed and no warranty is either
+ * expressed or implied by its publication or distribution.
+ **********************************************************************/
+
+/**
+ * @file crc32.c
+ * @brief Implementation of crc.h
+ */
+
+#include "crc.h"
+
+#define FALSE 0
+#define TRUE !FALSE
+
+typedef unsigned long crc;
+
+#define CRC_NAME "CRC-32"
+#define POLYNOMIAL 0x04C11DB7
+#define INITIAL_REMAINDER 0xFFFFFFFF
+#define FINAL_XOR_VALUE 0xFFFFFFFF
+#define REFLECT_DATA TRUE
+#define REFLECT_REMAINDER TRUE
+#define CHECK_VALUE 0xCBF43926
+
+/*
+ * Derive parameters from the standard-specific parameters in crc.h.
+ */
+#define WIDTH (8 * sizeof(crc))
+#define TOPBIT (1U << (WIDTH - 1))
+
+#if (REFLECT_DATA == TRUE)
+#undef REFLECT_DATA
+#define REFLECT_DATA(X) ((unsigned char) reflect((X), 8))
+#else
+#undef REFLECT_DATA
+#define REFLECT_DATA(X) (X)
+#endif
+
+#if (REFLECT_REMAINDER == TRUE)
+#undef REFLECT_REMAINDER
+#define REFLECT_REMAINDER(X) ((crc) reflect((X), WIDTH))
+#else
+#undef REFLECT_REMAINDER
+#define REFLECT_REMAINDER(X) (X)
+#endif
+
+
+/*********************************************************************
+ *
+ * Function: reflect()
+ *
+ * Description: Reorder the bits of a binary sequence, by reflecting
+ * them about the middle position.
+ *
+ * Notes: No checking is done that nBits <= 32.
+ *
+ * Returns: The reflection of the original data.
+ *
+ *********************************************************************/
+static unsigned long
+reflect(unsigned long data, unsigned char nBits)
+{
+ unsigned long reflection = 0x00000000;
+ unsigned char bit;
+
+ /*
+ * Reflect the data about the center bit.
+ */
+ for (bit = 0; bit < nBits; ++bit) {
+ /*
+ * If the LSB bit is set, set the reflection of it.
+ */
+ if (data & 0x01) {
+ reflection |= (1 << ((nBits - 1) - bit));
+ }
+
+ data = (data >> 1);
+ }
+
+ return (reflection);
+} /* reflect() */
+
+
+/*********************************************************************
+ *
+ * Function: crc32()
+ *
+ * Description: Compute the CRC of a given message.
+ *
+ * Notes:
+ *
+ * Returns: The CRC of the message.
+ *
+ *********************************************************************/
+uint32_t
+crc32(const void *data, int nBytes)
+{
+ crc remainder = INITIAL_REMAINDER;
+ int byte;
+ unsigned char bit;
+ unsigned char const *message = data;
+
+ /*
+ * Perform modulo-2 division, a byte at a time.
+ */
+ for (byte = 0; byte < nBytes; ++byte) {
+ /*
+ * Bring the next byte into the remainder.
+ */
+ remainder ^= (REFLECT_DATA(message[byte]) << (WIDTH - 8));
+
+ /*
+ * Perform modulo-2 division, a bit at a time.
+ */
+ for (bit = 8; bit > 0; --bit) {
+ /*
+ * Try to divide the current data bit.
+ */
+ if (remainder & TOPBIT) {
+ remainder = (remainder << 1) ^ POLYNOMIAL;
+ } else {
+ remainder = (remainder << 1);
+ }
+ }
+ }
+
+ /*
+ * The final remainder is the CRC result.
+ */
+ return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE);
+} /* crc32() */
+
+/*********************************************************************
+ *
+ * Function: crc32_continue()
+ *
+ * Description: Compute the CRC of a given message.
+ *
+ * Notes:
+ *
+ * Returns: The CRC of the message.
+ *
+ *********************************************************************/
+uint32_t
+crc32_continue(uint32_t prev_crc, const void *data, int nBytes)
+{
+ crc remainder = REFLECT_REMAINDER(prev_crc ^ FINAL_XOR_VALUE);
+ int byte;
+ unsigned char bit;
+ unsigned char const *message = data;
+
+ /*
+ * Perform modulo-2 division, a byte at a time.
+ */
+ for (byte = 0; byte < nBytes; ++byte) {
+ /*
+ * Bring the next byte into the remainder.
+ */
+ remainder ^= (REFLECT_DATA(message[byte]) << (WIDTH - 8));
+
+ /*
+ * Perform modulo-2 division, a bit at a time.
+ */
+ for (bit = 8; bit > 0; --bit) {
+ /*
+ * Try to divide the current data bit.
+ */
+ if (remainder & TOPBIT) {
+ remainder = (remainder << 1) ^ POLYNOMIAL;
+ } else {
+ remainder = (remainder << 1);
+ }
+ }
+ }
+
+ /*
+ * The final remainder is the CRC result.
+ */
+ return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE);
+} /* crc32_continue() */
diff -r 000000000000 -r 01f31e923fe2 source/daplink/daplink.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/daplink.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,89 @@
+/**
+ * @file daplink.h
+ * @brief Information about different Hardware Interface Circuits the firmware runs
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef DAPLINK_H
+#define DAPLINK_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "daplink_addr.h"
+#include "compiler.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Assert that regions are sequential with no gaps
+// and that they take up all available space
+
+// ROM check
+COMPILER_ASSERT(DAPLINK_ROM_BL_START == DAPLINK_ROM_START);
+COMPILER_ASSERT(DAPLINK_ROM_BL_START + DAPLINK_ROM_BL_SIZE == DAPLINK_ROM_CONFIG_ADMIN_START);
+COMPILER_ASSERT(DAPLINK_ROM_CONFIG_ADMIN_START + DAPLINK_ROM_CONFIG_ADMIN_SIZE == DAPLINK_ROM_IF_START);
+COMPILER_ASSERT(DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE == DAPLINK_ROM_CONFIG_USER_START);
+COMPILER_ASSERT(DAPLINK_ROM_CONFIG_USER_START + DAPLINK_ROM_CONFIG_USER_SIZE == DAPLINK_ROM_START + DAPLINK_ROM_SIZE);
+
+// RAM check
+COMPILER_ASSERT(DAPLINK_RAM_APP_START == DAPLINK_RAM_START);
+COMPILER_ASSERT(DAPLINK_RAM_APP_START + DAPLINK_RAM_APP_SIZE == DAPLINK_RAM_SHARED_START);
+COMPILER_ASSERT(DAPLINK_RAM_SHARED_START + DAPLINK_RAM_SHARED_SIZE == DAPLINK_RAM_START + DAPLINK_RAM_SIZE);
+
+#define DAPLINK_BUILD_KEY_IF 0x9B939E8F
+#define DAPLINK_BUILD_KEY_BL 0x9B939D93
+
+//! @name HIC IDs
+//@{
+#define DAPLINK_HIC_ID_K20DX 0x97969900
+#define DAPLINK_HIC_ID_KL26 0x97969901
+#define DAPLINK_HIC_ID_LPC11U35 0x97969902
+#define DAPLINK_HIC_ID_SAM3U2C 0x97969903
+#define DAPLINK_HIC_ID_MAX32620 0x97969904
+#define DAPLINK_HIC_ID_LPC4322 0x97969905
+#define DAPLINK_HIC_ID_MAX32625 0x97969906
+#define DAPLINK_HIC_ID_MAX32550 0x97969907
+#define DAPLINK_HIC_ID_STM32F103XB 0x97969908
+#define DAPLINK_HIC_ID_K26F 0x97969909
+#define DAPLINK_HIC_ID_K22F 0x9796990A
+#define DAPLINK_HIC_ID_KL27Z 0x9796990B // reserving for future use
+#define DAPLINK_HIC_ID_LPC54606 0x9796990C // reserving for future use
+#define DAPLINK_HIC_ID_STM32F723IE 0x9796990D // reserving for future use
+#define DAPLINK_HIC_ID_LPC55S69 0x97969920 // reserving for future use
+#define DAPLINK_HIC_ID_M48SSIDAE 0x97969921
+#define DAPLINK_HIC_ID_PSOC5 0x2E127069
+//@}
+
+#define DAPLINK_INFO_OFFSET 0x20
+
+typedef struct {
+ uint32_t build_key;
+ uint32_t hic_id;
+ uint32_t version;
+} daplink_info_t;
+
+bool daplink_is_bootloader(void);
+bool daplink_is_interface(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/daplink.sct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/daplink.sct Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,59 @@
+#! armcc -E
+;/**
+; * @file daplink.sct
+; * @brief Memory layout for DAPLink Interface Firmware
+; *
+; * DAPLink Interface Firmware
+; * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License"); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+#include "daplink_addr.h"
+
+LR_IROM1 DAPLINK_ROM_APP_START DAPLINK_ROM_APP_SIZE {
+
+ ER_IROM1 DAPLINK_ROM_APP_START DAPLINK_ROM_APP_SIZE {
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ RW_IRAM1 DAPLINK_RAM_APP_START DAPLINK_RAM_APP_SIZE { ; RW data
+ .ANY (ram_func)
+ .ANY (+RW +ZI)
+ .ANY (RAM1)
+ }
+
+ #if defined(DAPLINK_RAM_APP2_START)
+ RW_IRAM2 DAPLINK_RAM_APP2_START DAPLINK_RAM_APP2_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ .ANY (RAM2)
+ }
+ #endif
+
+ RW_CONFIG DAPLINK_RAM_SHARED_START UNINIT DAPLINK_RAM_SHARED_SIZE {
+ .ANY (cfgram)
+ }
+
+ ER_IROM1_CRC (DAPLINK_ROM_APP_START + DAPLINK_ROM_APP_SIZE - 4) FIXED FILL 0xFFFFFFFF 4 {
+ ; reserve space for the CRC
+ }
+}
+
+LR_CONFIG DAPLINK_ROM_CONFIG_USER_START DAPLINK_ROM_CONFIG_USER_SIZE { ; reserve last sector for config data
+ ER_CONFIG DAPLINK_ROM_CONFIG_USER_START UNINIT DAPLINK_ROM_CONFIG_USER_SIZE {
+ .ANY (cfgrom)
+ }
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/daplink_debug.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/daplink_debug.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,110 @@
+/**
+ * @file daplink_debug.h
+ * @brief optional trace messages useful in development
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef DAPLINK_DEBUG_H
+#define DAPLINK_DEBUG_H
+
+#include <stdarg.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdint.h>
+#include "cmsis_os2.h"
+#include "rl_usb.h"
+#include "util.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef MSC_DEBUG
+//#define MSC_DEBUG
+#endif
+
+#if defined (MSC_DEBUG)
+
+static const char error_msg[] = "\r\n<OVERFLOW>\r\n";
+
+static inline uint32_t daplink_debug(uint8_t *buf, uint32_t size)
+{
+ uint32_t total_free;
+ uint32_t write_free;
+ uint32_t error_len = strlen(error_msg);
+ total_free = USBD_CDC_ACM_DataFree();
+
+ if (total_free < error_len) {
+ // No space
+ return 0;
+ }
+
+ // Size available for writing
+ write_free = total_free - error_len;
+ size = MIN(write_free, size);
+ USBD_CDC_ACM_DataSend(buf, size);
+
+ if (write_free == size) {
+ USBD_CDC_ACM_DataSend((uint8_t *)error_msg, error_len);
+ }
+
+ return size;
+}
+
+static char daplink_debug_buf[128] = {0};
+static inline uint32_t daplink_debug_print(const char *format, ...)
+{
+ uint32_t ret;
+ int32_t r = 0;
+ va_list arg;
+ ret = 1;
+ va_start(arg, format);
+ r = vsnprintf(daplink_debug_buf, sizeof(daplink_debug_buf), format, arg);
+
+ if (r >= sizeof(daplink_debug_buf)) {
+ r = snprintf(daplink_debug_buf, sizeof(daplink_debug_buf), "<Error - string length %i exceeds print buffer>\r\n", r);
+ ret = 0;
+ }
+
+ va_end(arg);
+ daplink_debug((uint8_t *)daplink_debug_buf, r);
+ return ret;
+}
+
+#else
+
+static inline uint32_t daplink_debug_print(const char *format, ...)
+{
+ return 1;
+}
+
+static inline uint32_t daplink_debug(uint8_t *data, uint32_t size)
+{
+ return 1;
+}
+
+#endif
+
+#define debug_msg(fmt, args...) daplink_debug_print(fmt, ## args);
+#define debug_data(buf, size) daplink_debug(buf, size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/drag-n-drop/file_stream.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/drag-n-drop/file_stream.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,366 @@
+/**
+ * @file file_stream.c
+ * @brief Implementation of file_stream.h
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+
+#include "file_stream.h"
+#include "util.h"
+#include "intelhex.h"
+#include "flash_decoder.h"
+#include "error.h"
+#include "cmsis_os2.h"
+#include "compiler.h"
+#include "validation.h"
+
+typedef enum {
+ STREAM_STATE_CLOSED,
+ STREAM_STATE_OPEN,
+ STREAM_STATE_END,
+ STREAM_STATE_ERROR
+} stream_state_t;
+
+typedef bool (*stream_detect_cb_t)(const uint8_t *data, uint32_t size);
+typedef error_t (*stream_open_cb_t)(void *state);
+typedef error_t (*stream_write_cb_t)(void *state, const uint8_t *data, uint32_t size);
+typedef error_t (*stream_close_cb_t)(void *state);
+
+typedef struct {
+ stream_detect_cb_t detect;
+ stream_open_cb_t open;
+ stream_write_cb_t write;
+ stream_close_cb_t close;
+} stream_t;
+
+typedef struct {
+ uint8_t vector_buf[FLASH_DECODER_MIN_SIZE];
+ uint8_t buf_pos;
+ uint32_t flash_addr;
+} bin_state_t;
+
+typedef struct {
+ bool parsing_complete;
+ uint8_t bin_buffer[256];
+} hex_state_t;
+
+typedef union {
+ bin_state_t bin;
+ hex_state_t hex;
+} shared_state_t;
+
+static bool detect_bin(const uint8_t *data, uint32_t size);
+static error_t open_bin(void *state);
+static error_t write_bin(void *state, const uint8_t *data, uint32_t size);
+static error_t close_bin(void *state);
+
+static bool detect_hex(const uint8_t *data, uint32_t size);
+static error_t open_hex(void *state);
+static error_t write_hex(void *state, const uint8_t *data, uint32_t size);
+static error_t close_hex(void *state);
+
+stream_t stream[] = {
+ {detect_bin, open_bin, write_bin, close_bin}, // STREAM_TYPE_BIN
+ {detect_hex, open_hex, write_hex, close_hex}, // STREAM_TYPE_HEX
+};
+COMPILER_ASSERT(ARRAY_SIZE(stream) == STREAM_TYPE_COUNT);
+// STREAM_TYPE_NONE must not be included in count
+COMPILER_ASSERT(STREAM_TYPE_NONE > STREAM_TYPE_COUNT);
+
+static shared_state_t shared_state;
+static stream_state_t state = STREAM_STATE_CLOSED;
+static stream_t *current_stream = 0;
+
+// Thread variables (STUB these if RTX is not used)
+static osThreadId_t stream_thread_tid = 0;
+static void stream_thread_set(void)
+{
+ stream_thread_tid = osThreadGetId();
+}
+static void stream_thread_assert(void)
+{
+ util_assert(osThreadGetId() == stream_thread_tid);
+}
+
+stream_type_t stream_start_identify(const uint8_t *data, uint32_t size)
+{
+ stream_type_t i;
+
+ for (i = STREAM_TYPE_START; i < STREAM_TYPE_COUNT; i++) {
+ if (stream[i].detect(data, size)) {
+ return i;
+ }
+ }
+
+ return STREAM_TYPE_NONE;
+}
+
+// Identify the file type from its extension
+stream_type_t stream_type_from_name(const vfs_filename_t filename)
+{
+ // 8.3 file names must be in upper case
+ if (0 == strncmp("BIN", &filename[8], 3)) {
+ return STREAM_TYPE_BIN;
+ } else if (0 == strncmp("HEX", &filename[8], 3)) {
+ return STREAM_TYPE_HEX;
+ } else {
+ return STREAM_TYPE_NONE;
+ }
+}
+
+error_t stream_open(stream_type_t stream_type)
+{
+ error_t status;
+
+ // Stream must not be open already
+ if (state != STREAM_STATE_CLOSED) {
+ util_assert(0);
+ return ERROR_INTERNAL;
+ }
+
+ // Stream must be of a supported type
+ if (stream_type >= STREAM_TYPE_COUNT) {
+ util_assert(0);
+ return ERROR_INTERNAL;
+ }
+
+ stream_thread_set();
+ // Initialize all variables
+ memset(&shared_state, 0, sizeof(shared_state));
+ state = STREAM_STATE_OPEN;
+ current_stream = &stream[stream_type];
+ // Initialize the specified stream
+ status = current_stream->open(&shared_state);
+
+ if (ERROR_SUCCESS != status) {
+ state = STREAM_STATE_ERROR;
+ }
+
+ return status;
+}
+
+error_t stream_write(const uint8_t *data, uint32_t size)
+{
+ error_t status;
+
+ // Stream must be open already
+ if (state != STREAM_STATE_OPEN) {
+ util_assert(0);
+ return ERROR_INTERNAL;
+ }
+
+ // Check thread after checking state since the stream thread is
+ // set only if stream_open has been called
+ stream_thread_assert();
+ // Write to stream
+ status = current_stream->write(&shared_state, data, size);
+
+ if (ERROR_SUCCESS_DONE == status) {
+ state = STREAM_STATE_END;
+ } else if ((ERROR_SUCCESS_DONE_OR_CONTINUE == status) || (ERROR_SUCCESS == status)) {
+ // Stream should remain in the open state
+ util_assert(STREAM_STATE_OPEN == state);
+ } else {
+ state = STREAM_STATE_ERROR;
+ }
+
+ return status;
+}
+
+error_t stream_close(void)
+{
+ error_t status;
+
+ // Stream must not be closed already
+ if (STREAM_STATE_CLOSED == state) {
+ util_assert(0);
+ return ERROR_INTERNAL;
+ }
+
+ // Check thread after checking state since the stream thread is
+ // set only if stream_open has been called
+ stream_thread_assert();
+ // Close stream
+ status = current_stream->close(&shared_state);
+ state = STREAM_STATE_CLOSED;
+ return status;
+}
+
+/* Binary file processing */
+
+static bool detect_bin(const uint8_t *data, uint32_t size)
+{
+ return FLASH_DECODER_TYPE_UNKNOWN != flash_decoder_detect_type(data, size, 0, false);
+}
+
+static error_t open_bin(void *state)
+{
+ error_t status;
+ status = flash_decoder_open();
+ return status;
+}
+
+static error_t write_bin(void *state, const uint8_t *data, uint32_t size)
+{
+ error_t status;
+ bin_state_t *bin_state = (bin_state_t *)state;
+
+ if (bin_state->buf_pos < FLASH_DECODER_MIN_SIZE) {
+ flash_decoder_type_t flash_type;
+ uint32_t size_left;
+ uint32_t copy_size;
+ uint32_t start_addr;
+ const flash_intf_t *flash_intf;
+ // Buffer Data
+ size_left = FLASH_DECODER_MIN_SIZE - bin_state->buf_pos;
+ copy_size = MIN(size_left, size);
+ memcpy(bin_state->vector_buf + bin_state->buf_pos, data, copy_size);
+ bin_state->buf_pos += copy_size;
+
+ if (bin_state->buf_pos < FLASH_DECODER_MIN_SIZE) {
+ // Not enough data to determine type
+ return ERROR_SUCCESS;
+ }
+
+ data += copy_size;
+ size -= copy_size;
+ // Determine type
+ flash_type = flash_decoder_detect_type(bin_state->vector_buf, bin_state->buf_pos, 0, false);
+
+ if (FLASH_DECODER_TYPE_UNKNOWN == flash_type) {
+ return ERROR_FD_UNSUPPORTED_UPDATE;
+ }
+
+ // Determine flash addresss
+ status = flash_decoder_get_flash(flash_type, 0, false, &start_addr, &flash_intf);
+
+ if (ERROR_SUCCESS != status) {
+ return status;
+ }
+
+ bin_state->flash_addr = start_addr;
+ // Pass on data to the decoder
+ status = flash_decoder_write(bin_state->flash_addr, bin_state->vector_buf, bin_state->buf_pos);
+
+ if (ERROR_SUCCESS != status) {
+ return status;
+ }
+
+ bin_state->flash_addr += bin_state->buf_pos;
+ }
+
+ // Write data
+ status = flash_decoder_write(bin_state->flash_addr, data, size);
+
+ if (ERROR_SUCCESS != status) {
+ return status;
+ }
+
+ bin_state->flash_addr += size;
+ // There is no way to determine the end of a binary
+ // file so any point could be the end
+ return ERROR_SUCCESS_DONE_OR_CONTINUE;
+}
+
+static error_t close_bin(void *state)
+{
+ error_t status;
+ status = flash_decoder_close();
+ return status;
+}
+
+/* Hex file processing */
+
+static bool detect_hex(const uint8_t *data, uint32_t size)
+{
+ return 1 == validate_hexfile(data);
+}
+
+static error_t open_hex(void *state)
+{
+ error_t status;
+ hex_state_t *hex_state = (hex_state_t *)state;
+ memset(hex_state, 0, sizeof(*hex_state));
+ reset_hex_parser();
+ hex_state->parsing_complete = false;
+ status = flash_decoder_open();
+ return status;
+}
+
+static error_t write_hex(void *state, const uint8_t *data, uint32_t size)
+{
+ error_t status = ERROR_SUCCESS;
+ hex_state_t *hex_state = (hex_state_t *)state;
+ hexfile_parse_status_t parse_status = HEX_PARSE_UNINIT;
+ uint32_t bin_start_address = 0; // Decoded from the hex file, the binary buffer data starts at this address
+ uint32_t bin_buf_written = 0; // The amount of data in the binary buffer starting at address above
+ uint32_t block_amt_parsed = 0; // amount of data parsed in the block on the last call
+
+ while (1) {
+ // try to decode a block of hex data into bin data
+ parse_status = parse_hex_blob(data, size, &block_amt_parsed, hex_state->bin_buffer, sizeof(hex_state->bin_buffer), &bin_start_address, &bin_buf_written);
+
+ // the entire block of hex was decoded. This is a simple state
+ if (HEX_PARSE_OK == parse_status) {
+ if (bin_buf_written > 0) {
+ status = flash_decoder_write(bin_start_address, hex_state->bin_buffer, bin_buf_written);
+ }
+
+ break;
+ } else if (HEX_PARSE_UNALIGNED == parse_status) {
+ if (bin_buf_written > 0) {
+ status = flash_decoder_write(bin_start_address, hex_state->bin_buffer, bin_buf_written);
+
+ if (ERROR_SUCCESS != status) {
+ break;
+ }
+ }
+
+ // incrememntal offset to finish the block
+ size -= block_amt_parsed;
+ data += block_amt_parsed;
+ } else if (HEX_PARSE_EOF == parse_status) {
+ if (bin_buf_written > 0) {
+ status = flash_decoder_write(bin_start_address, hex_state->bin_buffer, bin_buf_written);
+ }
+
+ if (ERROR_SUCCESS == status) {
+ status = ERROR_SUCCESS_DONE;
+ }
+
+ break;
+ } else if (HEX_PARSE_CKSUM_FAIL == parse_status) {
+ status = ERROR_HEX_CKSUM;
+ break;
+ } else if ((HEX_PARSE_UNINIT == parse_status) || (HEX_PARSE_FAILURE == parse_status)) {
+ util_assert(HEX_PARSE_UNINIT != parse_status);
+ status = ERROR_HEX_PARSER;
+ break;
+ }
+ }
+
+ return status;
+}
+
+static error_t close_hex(void *state)
+{
+ error_t status;
+ status = flash_decoder_close();
+ return status;
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/drag-n-drop/file_stream.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/drag-n-drop/file_stream.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,63 @@
+/**
+ * @file file_stream.h
+ * @brief Different file stream parsers that are supported
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef FILE_STREAM_H
+#define FILE_STREAM_H
+
+#include <stdint.h>
+
+#include "virtual_fs.h"
+#include "error.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ STREAM_TYPE_START = 0,
+
+ STREAM_TYPE_BIN = STREAM_TYPE_START,
+ STREAM_TYPE_HEX,
+
+ // Add new stream types here
+
+ STREAM_TYPE_COUNT,
+
+ STREAM_TYPE_NONE
+} stream_type_t;
+
+// Stateless function to identify a filestream by its contents
+stream_type_t stream_start_identify(const uint8_t *data, uint32_t size);
+
+// Stateless function to identify a filestream by its name
+stream_type_t stream_type_from_name(const vfs_filename_t filename);
+
+error_t stream_open(stream_type_t stream_type);
+
+error_t stream_write(const uint8_t *data, uint32_t size);
+
+error_t stream_close(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/drag-n-drop/flash_decoder.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/drag-n-drop/flash_decoder.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,385 @@
+/**
+ * @file flash_decoder.c
+ * @brief Implementation of flash_decoder.h
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+
+#include "flash_decoder.h"
+#include "util.h"
+#include "daplink.h"
+#include "flash_manager.h"
+#include "target_config.h" // for target_device
+#include "settings.h" // for config_get_automation_allowed
+#include "validation.h"
+#include "target_board.h"
+
+// Set to 1 to enable debugging
+#define DEBUG_FLASH_DECODER 0
+
+#if DEBUG_FLASH_DECODER
+#include "daplink_debug.h"
+#define flash_decoder_printf debug_msg
+#else
+#define flash_decoder_printf(...)
+#endif
+
+typedef enum {
+ DECODER_STATE_CLOSED,
+ DECODER_STATE_OPEN,
+ DECODER_STATE_DONE,
+ DECODER_STATE_ERROR
+} decoder_state_t;
+
+static uint8_t flash_buf[FLASH_DECODER_MIN_SIZE];
+static decoder_state_t state = DECODER_STATE_CLOSED;
+static flash_decoder_type_t flash_type;
+static uint32_t flash_buf_pos;
+static uint32_t initial_addr;
+static uint32_t current_addr;
+static bool flash_initialized;
+static bool initial_addr_set;
+static bool flash_type_target_bin;
+
+static bool flash_decoder_is_at_end(uint32_t addr, const uint8_t *data, uint32_t size);
+
+flash_decoder_type_t flash_decoder_detect_type(const uint8_t *data, uint32_t size, uint32_t addr, bool addr_valid)
+{
+ daplink_info_t info;
+ util_assert(size >= FLASH_DECODER_MIN_SIZE);
+ // Check if this is a daplink image
+ memcpy(&info, data + DAPLINK_INFO_OFFSET, sizeof(info));
+ if(!addr_valid){ //reset until we know the binary type
+ flash_type_target_bin = false;
+ }
+ if (DAPLINK_HIC_ID == info.hic_id) {
+ if (DAPLINK_BUILD_KEY_IF == info.build_key) {
+ // Interface update
+ return FLASH_DECODER_TYPE_INTERFACE;
+ } else if (DAPLINK_BUILD_KEY_BL == info.build_key) {
+ // Bootloader update
+ return FLASH_DECODER_TYPE_BOOTLOADER;
+ } else {
+ return FLASH_DECODER_TYPE_UNKNOWN;
+ }
+ }
+
+ // Check if a valid vector table for the target can be found
+ if (validate_bin_nvic(data)) {
+ if(!addr_valid){ //binary is a bin type
+ flash_type_target_bin = true;
+ }
+ return FLASH_DECODER_TYPE_TARGET;
+ }
+
+ // If an address is specified then the data can be decoded
+ if (addr_valid) {
+ // TODO - future improvement - make sure address is within target's flash
+ return FLASH_DECODER_TYPE_TARGET;
+ }
+
+ return FLASH_DECODER_TYPE_UNKNOWN;
+}
+
+error_t flash_decoder_get_flash(flash_decoder_type_t type, uint32_t addr, bool addr_valid, uint32_t *start_addr, const flash_intf_t **flash_intf)
+{
+ error_t status = ERROR_SUCCESS;
+ uint32_t flash_start_local;
+ const flash_intf_t *flash_intf_local = 0;
+
+ if ((0 == start_addr) || (0 == flash_intf)) {
+ util_assert(0);
+ return ERROR_INTERNAL;
+ }
+
+ *start_addr = 0;
+ *flash_intf = 0;
+ flash_start_local = 0;
+ flash_intf_local = 0;
+
+ if (daplink_is_bootloader()) {
+ if (FLASH_DECODER_TYPE_INTERFACE == type) {
+ if (addr_valid && (DAPLINK_ROM_IF_START != addr)) {
+ // Address is wrong so display error message
+ status = ERROR_FD_INTF_UPDT_ADDR_WRONG;
+ } else {
+ // Setup for update
+ flash_start_local = DAPLINK_ROM_IF_START;
+ flash_intf_local = flash_intf_iap_protected;
+ }
+ } else if (FLASH_DECODER_TYPE_TARGET == type) {
+ // "Target" update in this case would be a 3rd party interface application
+ flash_start_local = DAPLINK_ROM_IF_START;
+ flash_intf_local = flash_intf_iap_protected;
+ } else {
+ status = ERROR_FD_UNSUPPORTED_UPDATE;
+ }
+ } else if (daplink_is_interface()) {
+ if (FLASH_DECODER_TYPE_BOOTLOADER == type) {
+ if (addr_valid && (DAPLINK_ROM_BL_START != addr)) {
+ // Address is wrong so display error message
+ status = ERROR_FD_BL_UPDT_ADDR_WRONG;
+ } else {
+ // Setup for update
+ flash_start_local = DAPLINK_ROM_BL_START;
+ flash_intf_local = flash_intf_iap_protected;
+ }
+ } else if (FLASH_DECODER_TYPE_TARGET == type) {
+ if (g_board_info.target_cfg) {
+ region_info_t * region = g_board_info.target_cfg->flash_regions;
+ for (; region->start != 0 || region->end != 0; ++region) {
+ if (kRegionIsDefault == region->flags) {
+ flash_start_local = region->start;
+ break;
+ }
+ }
+ flash_intf_local = flash_intf_target;
+ } else {
+ status = ERROR_FD_UNSUPPORTED_UPDATE;
+ }
+ } else {
+ status = ERROR_FD_UNSUPPORTED_UPDATE;
+ }
+ } else {
+ status = ERROR_FD_UNSUPPORTED_UPDATE;
+ }
+
+ // Don't allow bootloader updates unless automation is allowed
+ if (!config_get_automation_allowed() && (FLASH_DECODER_TYPE_BOOTLOADER == type)) {
+ status = ERROR_FD_UNSUPPORTED_UPDATE;
+ }
+
+ if (ERROR_SUCCESS != status) {
+ return status;
+ }
+
+ if (0 == flash_intf_local) {
+ util_assert(0);
+ return ERROR_INTERNAL;
+ }
+
+ *start_addr = flash_start_local;
+ *flash_intf = flash_intf_local;
+ return status;
+}
+
+error_t flash_decoder_open(void)
+{
+ flash_decoder_printf("flash_decoder_open()\r\n");
+
+ // Stream must not be open already
+ if (state != DECODER_STATE_CLOSED) {
+ util_assert(0);
+ return ERROR_INTERNAL;
+ }
+
+ memset(flash_buf, 0xff, sizeof(flash_buf));
+ state = DECODER_STATE_OPEN;
+ flash_type = FLASH_DECODER_TYPE_UNKNOWN;
+ flash_buf_pos = 0;
+ initial_addr = 0;
+ current_addr = 0;
+ flash_initialized = false;
+ initial_addr_set = false;
+ return ERROR_SUCCESS;
+}
+
+error_t flash_decoder_write(uint32_t addr, const uint8_t *data, uint32_t size)
+{
+ error_t status;
+ flash_decoder_printf("flash_decoder_write(addr=0x%x, size=0x%x)\r\n", addr, size);
+
+ if (DECODER_STATE_OPEN != state) {
+ util_assert(0);
+ return ERROR_INTERNAL;
+ }
+
+ // Set the initial address the first time through
+ if (!initial_addr_set) {
+ initial_addr = addr;
+ current_addr = initial_addr;
+ flash_decoder_printf(" initial_addr=0x%x\r\n", initial_addr);
+ initial_addr_set = true;
+ }
+
+ if (!flash_initialized) {
+ uint32_t copy_size;
+ bool flash_type_known = false;
+ bool sequential;
+ // Check if the data is sequential
+ sequential = addr == current_addr;
+ current_addr += size;
+
+ // Buffer data until the flash type is known
+ if (sequential) {
+ // Copy data into buffer
+ copy_size = MIN(size, sizeof(flash_buf) - flash_buf_pos);
+ memcpy(&flash_buf[flash_buf_pos], data, copy_size);
+ flash_buf_pos += copy_size;
+ flash_decoder_printf(" buffering %i bytes\r\n", copy_size);
+ // Update vars so they no longer include the buffered data
+ data += copy_size;
+ size -= copy_size;
+ addr += copy_size;
+
+ // If enough data has been buffered then determine the type
+ if (flash_buf_pos >= sizeof(flash_buf)) {
+ util_assert(sizeof(flash_buf) == flash_buf_pos);
+ // Determine flash type and get info for it
+ flash_type = flash_decoder_detect_type(flash_buf, flash_buf_pos, initial_addr, true);
+ flash_decoder_printf(" Buffering complete, setting flash_type=%i\r\n", flash_type);
+ flash_type_known = true;
+ }
+ } else {
+ flash_type = FLASH_DECODER_TYPE_TARGET;
+ flash_decoder_printf(" Non sequential addr, setting flash_type=%i\r\n", flash_type);
+ flash_type_known = true;
+ }
+
+ // If flash type is known initialize the flash manager
+ if (flash_type_known) {
+ const flash_intf_t *flash_intf;
+ uint32_t flash_start_addr;
+ status = flash_decoder_get_flash(flash_type, initial_addr, true, &flash_start_addr, &flash_intf);
+
+ if (ERROR_SUCCESS != status) {
+ state = DECODER_STATE_ERROR;
+ return status;
+ }
+
+ flash_decoder_printf(" flash_start_addr=0x%x\r\n", flash_start_addr);
+ // Initialize flash manager
+ util_assert(!flash_initialized);
+ status = flash_manager_init(flash_intf);
+ flash_decoder_printf(" flash_manager_init ret %i\r\n", status);
+
+ if (ERROR_SUCCESS != status) {
+ state = DECODER_STATE_ERROR;
+ return status;
+ }
+
+ flash_initialized = true;
+ }
+
+ // If flash has been initalized then write out buffered data
+ if (flash_initialized) {
+ status = flash_manager_data(initial_addr, flash_buf, flash_buf_pos);
+ flash_decoder_printf(" Flushing buffer initial_addr=0x%x, flash_buf_pos=%i, flash_manager_data ret=%i\r\n",
+ initial_addr, flash_buf_pos, status);
+
+ if (ERROR_SUCCESS != status) {
+ state = DECODER_STATE_ERROR;
+ return status;
+ }
+ }
+ }
+
+ // Write data as normal if flash has been initialized
+ if (flash_initialized) {
+ status = flash_manager_data(addr, data, size);
+ flash_decoder_printf(" Writing data, addr=0x%x, size=0x%x, flash_manager_data ret %i\r\n",
+ addr, size, status);
+
+ if (ERROR_SUCCESS != status) {
+ state = DECODER_STATE_ERROR;
+ return status;
+ }
+ }
+
+ // Check if this is the end of data
+ if (flash_decoder_is_at_end(addr, data, size)) {
+ flash_decoder_printf(" End of transfer detected - addr 0x%08x, size 0x%08x\r\n",
+ addr, size);
+ state = DECODER_STATE_DONE;
+ return ERROR_SUCCESS_DONE;
+ }
+
+ return ERROR_SUCCESS;
+}
+
+error_t flash_decoder_close(void)
+{
+ error_t status = ERROR_SUCCESS;
+ decoder_state_t prev_state = state;
+ flash_decoder_printf("flash_decoder_close()\r\n");
+
+ if (DECODER_STATE_CLOSED == state) {
+ util_assert(0);
+ return ERROR_INTERNAL;
+ }
+
+ state = DECODER_STATE_CLOSED;
+
+ if (flash_initialized) {
+ status = flash_manager_uninit();
+ flash_decoder_printf(" flash_manager_uninit ret %i\r\n", status);
+ }
+
+ if ((DECODER_STATE_DONE != prev_state) &&
+ (flash_type != FLASH_DECODER_TYPE_TARGET) &&
+ (status == ERROR_SUCCESS)) {
+ status = ERROR_IAP_UPDT_INCOMPLETE;
+ }
+
+ return status;
+}
+
+static bool flash_decoder_is_at_end(uint32_t addr, const uint8_t *data, uint32_t size)
+{
+ uint32_t end_addr=0;
+
+ switch (flash_type) {
+ case FLASH_DECODER_TYPE_BOOTLOADER:
+ end_addr = DAPLINK_ROM_BL_START + DAPLINK_ROM_BL_SIZE;
+ break;
+
+ case FLASH_DECODER_TYPE_INTERFACE:
+ end_addr = DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE;
+ break;
+
+ case FLASH_DECODER_TYPE_TARGET:
+ //only if we are sure it is a bin for the target; without check unordered hex files will cause to terminate flashing
+ if (flash_type_target_bin && g_board_info.target_cfg) {
+ region_info_t * region = g_board_info.target_cfg->flash_regions;
+ for (; region->start != 0 || region->end != 0; ++region) {
+ if (addr >= region->start && addr<=region->end) {
+ end_addr = region->end;
+ break;
+ }
+ }
+ if(end_addr == 0){ //invalid end_addr
+ return false;
+ }
+
+ }
+ else {
+ return false;
+ }
+ break;
+
+ default:
+ return false;
+ }
+
+ if (addr + size >= end_addr) {
+ return true;
+ } else {
+ return false;
+ }
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/drag-n-drop/flash_decoder.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/drag-n-drop/flash_decoder.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,56 @@
+/**
+ * @file flash_decoder.h
+ * @brief Steam handling of different image types that are supported
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef FLASH_DECODER_H
+#define FLASH_DECODER_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "flash_intf.h"
+#include "error.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Enough space for 12 vectors
+#define FLASH_DECODER_MIN_SIZE 0x30
+
+typedef enum {
+ FLASH_DECODER_TYPE_UNKNOWN,
+ FLASH_DECODER_TYPE_BOOTLOADER,
+ FLASH_DECODER_TYPE_INTERFACE,
+ FLASH_DECODER_TYPE_TARGET,
+} flash_decoder_type_t;
+
+flash_decoder_type_t flash_decoder_detect_type(const uint8_t *data, uint32_t size, uint32_t addr, bool addr_valid);
+error_t flash_decoder_get_flash(flash_decoder_type_t type, uint32_t addr, bool addr_valid, uint32_t *start_addr, const flash_intf_t **flash_intf);
+
+error_t flash_decoder_open(void);
+error_t flash_decoder_write(uint32_t addr, const uint8_t *data, uint32_t size);
+error_t flash_decoder_close(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/drag-n-drop/flash_intf.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/daplink/drag-n-drop/flash_intf.c Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,30 @@ +/** + * @file flash_intf.c + * @brief Implementation of flash_intf.h + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "flash_intf.h" + + +__attribute__((weak)) +const flash_intf_t *const flash_intf_iap_protected = 0; +__attribute__((weak)) +const flash_intf_t *const flash_intf_target = 0; +__attribute__((weak)) +const flash_intf_t *const flash_intf_target_custom = 0;
diff -r 000000000000 -r 01f31e923fe2 source/daplink/drag-n-drop/flash_intf.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/drag-n-drop/flash_intf.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,71 @@
+/**
+ * @file flash_intf.h
+ * @brief Interface for implementing differet ways to write an image into memory
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef FLASH_INTF_H
+#define FLASH_INTF_H
+
+#include <stdint.h>
+
+#include "error.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ FLASH_FUNC_NOP,
+ FLASH_FUNC_ERASE,
+ FLASH_FUNC_PROGRAM,
+ FLASH_FUNC_VERIFY
+} flash_func_t;
+
+typedef error_t (*flash_intf_init_cb_t)(void);
+typedef error_t (*flash_intf_uninit_cb_t)(void);
+typedef error_t (*flash_intf_program_page_cb_t)(uint32_t addr, const uint8_t *buf, uint32_t size);
+typedef error_t (*flash_intf_erase_sector_cb_t)(uint32_t sector);
+typedef error_t (*flash_intf_erase_chip_cb_t)(void);
+typedef uint32_t (*flash_program_page_min_size_cb_t)(uint32_t addr);
+typedef uint32_t (*flash_erase_sector_size_cb_t)(uint32_t addr);
+typedef uint8_t (*flash_busy_cb_t)(void);
+typedef error_t (*flash_algo_set_cb_t)(uint32_t addr);
+
+typedef struct {
+ flash_intf_init_cb_t init;
+ flash_intf_uninit_cb_t uninit;
+ flash_intf_program_page_cb_t program_page;
+ flash_intf_erase_sector_cb_t erase_sector;
+ flash_intf_erase_chip_cb_t erase_chip;
+ flash_program_page_min_size_cb_t program_page_min_size;
+ flash_erase_sector_size_cb_t erase_sector_size;
+ flash_busy_cb_t flash_busy;
+ flash_algo_set_cb_t flash_algo_set;
+} flash_intf_t;
+
+// All flash interfaces. Unsupported interfaces are NULL.
+extern const flash_intf_t *const flash_intf_iap_protected;
+extern const flash_intf_t *const flash_intf_target;
+extern const flash_intf_t *const flash_intf_target_custom;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/drag-n-drop/flash_manager.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/drag-n-drop/flash_manager.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,350 @@
+/**
+ * @file flash_manager.c
+ * @brief Implementation of flash_manager.h
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * Copyright 2019, Cypress Semiconductor Corporation
+ * or a subsidiary of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_manager.h"
+#include "util.h"
+#include "error.h"
+#include "settings.h"
+
+// Set to 1 to enable debugging
+#define DEBUG_FLASH_MANAGER 0
+
+#if DEBUG_FLASH_MANAGER
+#include "daplink_debug.h"
+#define flash_manager_printf debug_msg
+#else
+#define flash_manager_printf(...)
+#endif
+
+typedef enum {
+ STATE_CLOSED,
+ STATE_OPEN,
+ STATE_ERROR
+} state_t;
+
+// Target programming expects buffer
+// passed in to be 4 byte aligned
+__attribute__((aligned(4)))
+static uint8_t buf[1024];
+static bool buf_empty;
+static bool current_sector_valid;
+static bool page_erase_enabled = false;
+static uint32_t current_write_block_addr;
+static uint32_t current_write_block_size;
+static uint32_t current_sector_addr;
+static uint32_t current_sector_size;
+static uint32_t last_addr;
+static const flash_intf_t *intf;
+static state_t state = STATE_CLOSED;
+
+static bool flash_intf_valid(const flash_intf_t *flash_intf);
+static error_t flush_current_block(uint32_t addr);
+static error_t setup_next_sector(uint32_t addr);
+
+error_t flash_manager_init(const flash_intf_t *flash_intf)
+{
+ error_t status;
+ // Assert that interface has been properly uninitialized
+ flash_manager_printf("flash_manager_init()\r\n");
+
+ if (state != STATE_CLOSED) {
+ util_assert(0);
+ return ERROR_INTERNAL;
+ }
+
+ // Check for a valid flash interface
+ if (!flash_intf_valid(flash_intf)) {
+ util_assert(0);
+ return ERROR_INTERNAL;
+ }
+
+ // Initialize variables
+ memset(buf, 0xFF, sizeof(buf));
+ buf_empty = true;
+ current_sector_valid = false;
+ current_write_block_addr = 0;
+ current_write_block_size = 0;
+ current_sector_addr = 0;
+ current_sector_size = 0;
+ last_addr = 0;
+ intf = flash_intf;
+ // Initialize flash
+ status = intf->init();
+ flash_manager_printf(" intf->init ret=%i\r\n", status);
+
+ if (ERROR_SUCCESS != status) {
+ return status;
+ }
+
+ if (!page_erase_enabled) {
+ // Erase flash and unint if there are errors
+ status = intf->erase_chip();
+ flash_manager_printf(" intf->erase_chip ret=%i\r\n", status);
+
+ if (ERROR_SUCCESS != status) {
+ intf->uninit();
+ return status;
+ }
+ }
+
+ state = STATE_OPEN;
+ return status;
+}
+
+error_t flash_manager_data(uint32_t addr, const uint8_t *data, uint32_t size)
+{
+ uint32_t size_left;
+ uint32_t copy_size;
+ uint32_t pos;
+ error_t status = ERROR_SUCCESS;
+ flash_manager_printf("flash_manager_data(addr=0x%x size=0x%x)\r\n", addr, size);
+
+ if (state != STATE_OPEN) {
+ util_assert(0);
+ return ERROR_INTERNAL;
+ }
+
+ // Setup the current sector if it is not setup already
+ if (!current_sector_valid) {
+ status = setup_next_sector(addr);
+
+ if (ERROR_SUCCESS != status) {
+ state = STATE_ERROR;
+ return status;
+ }
+ current_sector_valid = true;
+ last_addr = addr;
+ }
+
+ //non-increasing address support
+ if (ROUND_DOWN(addr, current_write_block_size) != ROUND_DOWN(last_addr, current_write_block_size)) {
+ status = flush_current_block(addr);
+ if (ERROR_SUCCESS != status) {
+ state = STATE_ERROR;
+ return status;
+ }
+ }
+
+ if (ROUND_DOWN(addr, current_sector_size) != ROUND_DOWN(last_addr, current_sector_size)) {
+ status = setup_next_sector(addr);
+ if (ERROR_SUCCESS != status) {
+ state = STATE_ERROR;
+ return status;
+ }
+ }
+
+ while (true) {
+ // flush if necessary
+ if (addr >= current_write_block_addr + current_write_block_size) {
+ status = flush_current_block(addr);
+ if (ERROR_SUCCESS != status) {
+ state = STATE_ERROR;
+ return status;
+ }
+ }
+
+ // Check for end
+ if (size <= 0) {
+ break;
+ }
+
+ // Change sector if necessary
+ if (addr >= current_sector_addr + current_sector_size) {
+ status = setup_next_sector(addr);
+
+ if (ERROR_SUCCESS != status) {
+ state = STATE_ERROR;
+ return status;
+ }
+ }
+
+ // write buffer
+ pos = addr - current_write_block_addr;
+ size_left = current_write_block_size - pos;
+ copy_size = MIN(size, size_left);
+ memcpy(buf + pos, data, copy_size);
+ buf_empty = copy_size == 0;
+ // Update variables
+ addr += copy_size;
+ data += copy_size;
+ size -= copy_size;
+ }
+
+ last_addr = addr;
+ return status;
+}
+
+error_t flash_manager_uninit(void)
+{
+ error_t flash_uninit_error;
+ error_t flash_write_error = ERROR_SUCCESS;
+ flash_manager_printf("flash_manager_uninit()\r\n");
+
+ if (STATE_CLOSED == state) {
+ util_assert(0);
+ return ERROR_INTERNAL;
+ }
+
+ // Flush last buffer if its not empty
+ if (STATE_OPEN == state) {
+ flash_write_error = flush_current_block(0);
+ flash_manager_printf(" last flush_current_block ret=%i\r\n",flash_write_error);
+ }
+ // Close flash interface (even if there was an error during program_page)
+ flash_uninit_error = intf->uninit();
+ flash_manager_printf(" intf->uninit() ret=%i\r\n", flash_uninit_error);
+ // Reset variables to catch accidental use
+ memset(buf, 0xFF, sizeof(buf));
+ buf_empty = true;
+ current_sector_valid = false;
+ current_write_block_addr = 0;
+ current_write_block_size = 0;
+ current_sector_addr = 0;
+ current_sector_size = 0;
+ last_addr = 0;
+ state = STATE_CLOSED;
+
+ // Make sure an error from a page write or from an
+ // uninit gets propagated
+ if (flash_uninit_error != ERROR_SUCCESS) {
+ return flash_uninit_error;
+ }
+
+ if (flash_write_error != ERROR_SUCCESS) {
+ return flash_write_error;
+ }
+
+ return ERROR_SUCCESS;
+}
+
+void flash_manager_set_page_erase(bool enabled)
+{
+ config_ram_set_page_erase(enabled);
+ page_erase_enabled = enabled;
+}
+
+static bool flash_intf_valid(const flash_intf_t *flash_intf)
+{
+ // Check for all requried members
+ if (0 == flash_intf) {
+ return false;
+ }
+
+ if (0 == flash_intf->uninit) {
+ return false;
+ }
+
+ if (0 == flash_intf->program_page) {
+ return false;
+ }
+
+ if (0 == flash_intf->erase_sector) {
+ return false;
+ }
+
+ if (0 == flash_intf->erase_chip) {
+ return false;
+ }
+
+ if (0 == flash_intf->program_page_min_size) {
+ return false;
+ }
+
+ if (0 == flash_intf->erase_sector_size) {
+ return false;
+ }
+
+ if (0 == flash_intf->flash_busy) {
+ return false;
+ }
+
+ return true;
+}
+
+static error_t flush_current_block(uint32_t addr){
+ // Write out current buffer if there is data in it
+ error_t status = ERROR_SUCCESS;
+ if (!buf_empty) {
+ status = intf->program_page(current_write_block_addr, buf, current_write_block_size);
+ flash_manager_printf(" intf->program_page(addr=0x%x, size=0x%x) ret=%i\r\n", current_write_block_addr, current_write_block_size, status);
+ buf_empty = true;
+ }
+
+ // Setup for next block
+ memset(buf, 0xFF, current_write_block_size);
+ current_write_block_addr = ROUND_DOWN(addr,current_write_block_size);
+ return status;
+}
+
+static error_t setup_next_sector(uint32_t addr)
+{
+ uint32_t min_prog_size;
+ uint32_t sector_size;
+ error_t status;
+ min_prog_size = intf->program_page_min_size(addr);
+ sector_size = intf->erase_sector_size(addr);
+
+ if ((min_prog_size <= 0) || (sector_size <= 0)) {
+ // Either of these conditions could cause divide by 0 error
+ util_assert(0);
+ return ERROR_INTERNAL;
+ }
+
+ // Assert required size and alignment
+ util_assert(sizeof(buf) >= min_prog_size);
+ util_assert(sizeof(buf) % min_prog_size == 0);
+ util_assert(sector_size >= min_prog_size);
+ util_assert(sector_size % min_prog_size == 0);
+ // Setup global variables
+ current_sector_addr = ROUND_DOWN(addr, sector_size);
+ current_sector_size = sector_size;
+ current_write_block_addr = current_sector_addr;
+ current_write_block_size = MIN(sector_size, sizeof(buf));
+
+ //check flash algo every sector change, addresses with different flash algo should be sector aligned
+ if (intf->flash_algo_set) {
+ status = intf->flash_algo_set(current_sector_addr);
+ if (ERROR_SUCCESS != status) {
+ intf->uninit();
+ return status;
+ }
+ }
+
+ if (page_erase_enabled) {
+ // Erase the current sector
+ status = intf->erase_sector(current_sector_addr);
+ flash_manager_printf(" intf->erase_sector(addr=0x%x) ret=%i\r\n", current_sector_addr);
+ if (ERROR_SUCCESS != status) {
+ intf->uninit();
+ return status;
+ }
+ }
+
+ // Clear out buffer in case block size changed
+ memset(buf, 0xFF, current_write_block_size);
+ flash_manager_printf(" setup_next_sector(addr=0x%x) sect_addr=0x%x, write_addr=0x%x,\r\n",
+ addr, current_sector_addr, current_write_block_addr);
+ flash_manager_printf(" actual_write_size=0x%x, sector_size=0x%x, min_write=0x%x\r\n",
+ current_write_block_size, current_sector_size, min_prog_size);
+ return ERROR_SUCCESS;
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/drag-n-drop/flash_manager.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/drag-n-drop/flash_manager.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,43 @@
+/**
+ * @file flash_manager.h
+ * @brief Handling of file steam decode and prep for writing
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef FLASH_MANAGER_H
+#define FLASH_MANAGER_H
+
+#include <string.h>
+#include <stdbool.h>
+#include "flash_intf.h"
+#include "error.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+error_t flash_manager_init(const flash_intf_t *flash_intf);
+error_t flash_manager_data(uint32_t addr, const uint8_t *data, uint32_t size);
+error_t flash_manager_uninit(void);
+void flash_manager_set_page_erase(bool enabled);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/drag-n-drop/iap_flash_intf.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/drag-n-drop/iap_flash_intf.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,504 @@
+/**
+ * @file iap_flash_intf.c
+ * @brief Implementation of flash_intf.h
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+
+#include "daplink.h"
+#include "flash_intf.h"
+#include "util.h"
+#include "flash_hal.h"
+#include "FlashPrg.h"
+#include "compiler.h"
+#include "crc.h"
+#include "info.h"
+
+// Application start must be aligned to page write
+COMPILER_ASSERT(DAPLINK_ROM_APP_START % DAPLINK_MIN_WRITE_SIZE == 0);
+// Application size must be a multiple of write size
+COMPILER_ASSERT(DAPLINK_ROM_APP_SIZE % DAPLINK_MIN_WRITE_SIZE == 0);
+// Sector size must be a multiple of write size
+COMPILER_ASSERT(DAPLINK_SECTOR_SIZE % DAPLINK_MIN_WRITE_SIZE == 0);
+// Application start must be aligned to a sector erase
+COMPILER_ASSERT(DAPLINK_ROM_APP_START % DAPLINK_SECTOR_SIZE == 0);
+// Update start must be aligned to sector write
+COMPILER_ASSERT(DAPLINK_ROM_UPDATE_START % DAPLINK_SECTOR_SIZE == 0);
+// Update size must be a multiple of sector size
+COMPILER_ASSERT(DAPLINK_ROM_UPDATE_SIZE % DAPLINK_SECTOR_SIZE == 0);
+
+typedef enum {
+ STATE_CLOSED,
+ STATE_OPEN,
+ STATE_ERROR
+} state_t;
+
+static error_t init(void);
+static error_t uninit(void);
+static error_t program_page(uint32_t addr, const uint8_t *buf, uint32_t size);
+static error_t erase_sector(uint32_t addr);
+static error_t erase_chip(void);
+static uint32_t program_page_min_size(uint32_t addr);
+static uint32_t erase_sector_size(uint32_t addr);
+
+static bool page_program_allowed(uint32_t addr, uint32_t size);
+static bool sector_erase_allowed(uint32_t addr);
+static error_t intercept_page_write(uint32_t addr, const uint8_t *buf, uint32_t size);
+static error_t intercept_sector_erase(uint32_t addr);
+static error_t critical_erase_and_program(uint32_t addr, const uint8_t *data, uint32_t size);
+static uint8_t target_flash_busy(void);
+
+static const flash_intf_t flash_intf = {
+ init,
+ uninit,
+ program_page,
+ erase_sector,
+ erase_chip,
+ program_page_min_size,
+ erase_sector_size,
+ target_flash_busy,
+};
+
+const flash_intf_t *const flash_intf_iap_protected = &flash_intf;
+
+static state_t state = STATE_CLOSED;
+static bool update_complete;
+static bool mass_erase_performed;
+static bool current_sector_set;
+static uint32_t current_sector;
+static uint32_t current_sector_size;
+static bool current_page_set;
+static uint32_t current_page;
+static uint32_t current_page_write_size;
+static uint32_t crc;
+static uint8_t sector_buf[DAPLINK_SECTOR_SIZE];
+
+static error_t init()
+{
+ int iap_status;
+ bool update_supported = DAPLINK_ROM_UPDATE_SIZE != 0;
+
+ if (state != STATE_CLOSED) {
+ util_assert(0);
+ return ERROR_INTERNAL;
+ }
+
+ if (!update_supported) {
+ return ERROR_IAP_UPDT_NOT_SUPPORTED;
+ }
+
+ iap_status = Init(0, 0, 0);
+
+ if (iap_status != 0) {
+ return ERROR_IAP_INIT;
+ }
+
+ update_complete = false;
+ mass_erase_performed = false;
+ current_sector_set = false;
+ current_sector = 0;
+ current_sector_size = 0;
+ current_page_set = false;
+ current_page = 0;
+ current_page_write_size = 0;
+ crc = 0;
+ memset(sector_buf, 0, sizeof(sector_buf));
+ state = STATE_OPEN;
+ return ERROR_SUCCESS;
+}
+
+static error_t uninit(void)
+{
+ int iap_status;
+
+ if (STATE_CLOSED == state) {
+ util_assert(0);
+ return ERROR_INTERNAL;
+ }
+
+ state = STATE_CLOSED;
+ iap_status = UnInit(0);
+
+ if (iap_status != 0) {
+ return ERROR_IAP_UNINIT;
+ }
+
+ if (!update_complete && !daplink_is_bootloader()) {
+ // Interface - Error if the bootloader update is not complete
+ // Bootloader - For 3rd party applications the end of the update
+ // is unknown so it is not an error if the transfer
+ // ends early.
+ return ERROR_IAP_UPDT_INCOMPLETE;
+ }
+
+ return ERROR_SUCCESS;
+}
+
+static error_t program_page(uint32_t addr, const uint8_t *buf, uint32_t size)
+{
+ uint32_t iap_status;
+ error_t status;
+ uint32_t min_prog_size;
+ uint32_t sector_size;
+ uint32_t updt_end = DAPLINK_ROM_UPDATE_START + DAPLINK_ROM_UPDATE_SIZE;
+
+ if (state != STATE_OPEN) {
+ util_assert(0);
+ return ERROR_INTERNAL;
+ }
+
+ min_prog_size = program_page_min_size(addr);
+ sector_size = erase_sector_size(addr);
+
+ // Address must be on a write size boundary
+ if (addr % min_prog_size != 0) {
+ util_assert(0);
+ state = STATE_ERROR;
+ return ERROR_INTERNAL;
+ }
+
+ // Programming size must be a non-zero multiple of the minimum write size
+ if ((size < min_prog_size) || (size % min_prog_size != 0)) {
+ util_assert(0);
+ state = STATE_ERROR;
+ return ERROR_INTERNAL;
+ }
+
+ // Write must not cross a sector boundary
+ if ((addr % sector_size) + size > sector_size) {
+ util_assert(0);
+ state = STATE_ERROR;
+ return ERROR_INTERNAL;
+ }
+
+ // Write must be in an erased sector (current_sector is always erased if it is set)
+ if (!mass_erase_performed) {
+ if (!current_sector_set) {
+ util_assert(0);
+ state = STATE_ERROR;
+ return ERROR_INTERNAL;
+ }
+
+ if ((addr < current_sector) || (addr >= current_sector + current_sector_size)) {
+ util_assert(0);
+ state = STATE_ERROR;
+ return ERROR_INTERNAL;
+ }
+ }
+
+ // Address must be sequential - no gaps
+ if (current_page_set && (addr != current_page + current_page_write_size)) {
+ util_assert(0);
+ state = STATE_ERROR;
+ return ERROR_INTERNAL;
+ }
+
+ if (!page_program_allowed(addr, size)) {
+ state = STATE_ERROR;
+ return ERROR_IAP_WRITE;
+ }
+
+ current_page_set = true;
+ current_page = addr;
+ current_page_write_size = size;
+ status = intercept_page_write(addr, buf, size);
+
+ if (status != ERROR_IAP_NO_INTERCEPT) {
+ // The operation has been intercepted so
+ // return the result
+ if (ERROR_SUCCESS != status) {
+ state = STATE_ERROR;
+ }
+
+ return status;
+ }
+
+ iap_status = flash_program_page(addr, size, (uint8_t *)buf);
+
+ if (iap_status != 0) {
+ state = STATE_ERROR;
+ return ERROR_IAP_WRITE;
+ }
+
+ if (addr + size >= updt_end) {
+ // Something has been updated so recompute the crc
+ info_crc_compute();
+ update_complete = true;
+ }
+
+ return ERROR_SUCCESS;
+}
+
+static error_t erase_sector(uint32_t addr)
+{
+ uint32_t iap_status;
+ error_t status;
+ uint32_t sector_size;
+
+ if (state != STATE_OPEN) {
+ util_assert(0);
+ return ERROR_INTERNAL;
+ }
+
+ // Address must be on a sector boundary
+ sector_size = erase_sector_size(addr);
+
+ if (addr % sector_size != 0) {
+ util_assert(0);
+ state = STATE_ERROR;
+ return ERROR_INTERNAL;
+ }
+
+ // Address must be sequential - no gaps
+ if (current_sector_set && (addr != current_sector + current_sector_size)) {
+ util_assert(0);
+ state = STATE_ERROR;
+ return ERROR_INTERNAL;
+ }
+
+ if (!sector_erase_allowed(addr)) {
+ state = STATE_ERROR;
+ return ERROR_IAP_ERASE_SECTOR;
+ }
+
+ current_sector_set = true;
+ current_sector = addr;
+ current_sector_size = sector_size;
+ status = intercept_sector_erase(addr);
+
+ if (status != ERROR_IAP_NO_INTERCEPT) {
+ // The operation has been intercepted so
+ // return the result
+ if (ERROR_SUCCESS != status) {
+ state = STATE_ERROR;
+ }
+
+ return status;
+ }
+
+ iap_status = flash_erase_sector(addr);
+
+ if (iap_status != 0) {
+ state = STATE_ERROR;
+ return ERROR_IAP_ERASE_SECTOR;
+ }
+
+ return ERROR_SUCCESS;
+}
+
+static error_t erase_chip(void)
+{
+ uint32_t updt_start = DAPLINK_ROM_UPDATE_START;
+ uint32_t updt_end = DAPLINK_ROM_UPDATE_START + DAPLINK_ROM_UPDATE_SIZE;
+
+ if (state != STATE_OPEN) {
+ util_assert(0);
+ return ERROR_INTERNAL;
+ }
+
+ if (mass_erase_performed) {
+ // Mass erase only allowed once
+ util_assert(0);
+ state = STATE_ERROR;
+ return ERROR_INTERNAL;
+ }
+
+ for (uint32_t addr = updt_start; addr < updt_end; addr += DAPLINK_SECTOR_SIZE) {
+ error_t status;
+ status = erase_sector(addr);
+
+ if (status != ERROR_SUCCESS) {
+ state = STATE_ERROR;
+ return ERROR_IAP_ERASE_ALL;
+ }
+ }
+
+ mass_erase_performed = true;
+ return ERROR_SUCCESS;
+}
+
+static uint32_t program_page_min_size(uint32_t addr)
+{
+ return DAPLINK_MIN_WRITE_SIZE;
+}
+
+static uint32_t erase_sector_size(uint32_t addr)
+{
+ return DAPLINK_SECTOR_SIZE;
+}
+
+static bool page_program_allowed(uint32_t addr, uint32_t size)
+{
+ // Check if any data would overlap with the application region
+ if ((addr < DAPLINK_ROM_APP_START + DAPLINK_ROM_APP_SIZE) && (addr + size > DAPLINK_ROM_APP_START)) {
+ return false;
+ }
+
+ return true;
+}
+
+static bool sector_erase_allowed(uint32_t addr)
+{
+ uint32_t app_start = DAPLINK_ROM_APP_START;
+ uint32_t app_end = DAPLINK_ROM_APP_START + DAPLINK_ROM_APP_SIZE;
+
+ // Check if the sector is part of the application
+ if ((addr >= app_start) && (addr < app_end)) {
+ return false;
+ }
+
+ return true;
+}
+
+static error_t intercept_page_write(uint32_t addr, const uint8_t *buf, uint32_t size)
+{
+ error_t status;
+ uint32_t crc_size;
+ uint32_t updt_start = DAPLINK_ROM_UPDATE_START;
+ uint32_t updt_end = DAPLINK_ROM_UPDATE_START + DAPLINK_ROM_UPDATE_SIZE;
+
+ if (state != STATE_OPEN) {
+ util_assert(0);
+ return ERROR_INTERNAL;
+ }
+
+ if ((addr < updt_start) || (addr >= updt_end)) {
+ return ERROR_IAP_OUT_OF_BOUNDS;
+ }
+
+ if (!daplink_is_interface()) {
+ return ERROR_IAP_NO_INTERCEPT;
+ }
+
+ /* Everything below here is interface specific */
+ crc_size = MIN(size, updt_end - addr - 4);
+ crc = crc32_continue(crc, buf, crc_size);
+
+ // Intercept the data if it is in the first sector
+ if ((addr >= updt_start) && (addr < updt_start + DAPLINK_SECTOR_SIZE)) {
+ uint32_t buf_offset = addr - updt_start;
+ memcpy(sector_buf + buf_offset, buf, size);
+ // Intercept was successful
+ return ERROR_SUCCESS;
+ }
+
+ // Finalize update if this is the last sector
+ if (updt_end == addr + size) {
+ uint32_t iap_status;
+ uint32_t size_left = updt_end - addr;
+ uint32_t crc_in_image = (buf[size_left - 4] << 0) |
+ (buf[size_left - 3] << 8) |
+ (buf[size_left - 2] << 16) |
+ (buf[size_left - 1] << 24);
+
+ if (crc != crc_in_image) {
+ return ERROR_BL_UPDT_BAD_CRC;
+ }
+
+ // Program the current buffer
+ iap_status = flash_program_page(addr, size, (uint8_t *)buf);
+
+ if (iap_status != 0) {
+ return ERROR_IAP_WRITE;
+ }
+
+ status = critical_erase_and_program(DAPLINK_ROM_UPDATE_START, sector_buf, DAPLINK_SECTOR_SIZE);
+
+ if (ERROR_SUCCESS == status) {
+ status = ERROR_SUCCESS;
+ }
+
+ // The bootloader has been updated so recompute the crc
+ info_crc_compute();
+ update_complete = true;
+ return status;
+ }
+
+ return ERROR_IAP_NO_INTERCEPT;
+}
+
+static error_t intercept_sector_erase(uint32_t addr)
+{
+ error_t status;
+ uint32_t updt_start = DAPLINK_ROM_UPDATE_START;
+ uint32_t updt_end = DAPLINK_ROM_UPDATE_START + DAPLINK_ROM_UPDATE_SIZE;
+
+ if (state != STATE_OPEN) {
+ util_assert(0);
+ return ERROR_INTERNAL;
+ }
+
+ if ((addr < updt_start) || (addr >= updt_end)) {
+ return ERROR_IAP_OUT_OF_BOUNDS;
+ }
+
+ if (!daplink_is_interface()) {
+ return ERROR_IAP_NO_INTERCEPT;
+ }
+
+ /* Everything below here is interface specific */
+
+ if (DAPLINK_ROM_UPDATE_START == addr) {
+ uint32_t addr = DAPLINK_ROM_UPDATE_START;
+ status = critical_erase_and_program(addr, (uint8_t *)DAPLINK_ROM_IF_START, DAPLINK_MIN_WRITE_SIZE);
+
+ if (ERROR_SUCCESS == status) {
+ // Intercept was successful
+ status = ERROR_SUCCESS;
+ }
+
+ return status;
+ }
+
+ return ERROR_IAP_NO_INTERCEPT;
+}
+
+static error_t critical_erase_and_program(uint32_t addr, const uint8_t *data, uint32_t size)
+{
+ uint32_t iap_status;
+
+ if (size < DAPLINK_MIN_WRITE_SIZE) {
+ util_assert(0);
+ return ERROR_INTERNAL;
+ }
+
+ // CRITICAL SECTION BELOW HERE!
+ // If something goes wrong with either
+ // the erase or write then the device
+ // will no longer be bootable.
+ // Erase the first sector
+ iap_status = flash_erase_sector(addr);
+
+ if (iap_status != 0) {
+ return ERROR_ERASE_ALL;
+ }
+
+ // Program the interface's vector table
+ iap_status = flash_program_page(addr, size, (uint8_t *)data);
+
+ if (iap_status != 0) {
+ return ERROR_IAP_WRITE;
+ }
+
+ return ERROR_SUCCESS;
+}
+
+static uint8_t target_flash_busy(void){
+ return (state == STATE_OPEN);
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/drag-n-drop/intelhex.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/drag-n-drop/intelhex.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,228 @@
+/**
+ * @file intelhex.c
+ * @brief Implementation of intelhex.h
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+
+#include "intelhex.h"
+
+typedef enum hex_record_t hex_record_t;
+enum hex_record_t {
+ DATA_RECORD = 0,
+ EOF_RECORD = 1,
+ EXT_SEG_ADDR_RECORD = 2,
+ START_SEG_ADDR_RECORD = 3,
+ EXT_LINEAR_ADDR_RECORD = 4,
+ START_LINEAR_ADDR_RECORD = 5
+};
+
+typedef union hex_line_t hex_line_t;
+union __attribute__((packed)) hex_line_t {
+ uint8_t buf[0x25];
+ struct __attribute__((packed)) {
+ uint8_t byte_count;
+ uint16_t address;
+ uint8_t record_type;
+ uint8_t data[0x25 - 0x5];
+ uint8_t checksum;
+ };
+};
+
+/** Swap 16bit value - let compiler figure out the best way
+ * @param val a variable of size uint16_t to be swapped
+ * @return the swapped value
+ */
+static uint16_t swap16(uint16_t a)
+{
+ return ((a & 0x00ff) << 8) | ((a & 0xff00) >> 8);
+}
+
+/** Converts a character representation of a hex to real value.
+ * @param c is the hex value in char format
+ * @return the value of the hex
+ */
+static uint8_t ctoh(char c)
+{
+ return (c & 0x10) ? /*0-9*/ c & 0xf : /*A-F, a-f*/ (c & 0xf) + 9;
+}
+
+/** Calculate checksum on a hex record
+ * @param data is the line of hex record
+ * @param size is the length of the data array
+ * @return 1 if the data provided is a valid hex record otherwise 0
+ */
+static uint8_t validate_checksum(hex_line_t *record)
+{
+ uint8_t result = 0, i = 0;
+
+ for (; i < (record->byte_count + 5); i++) {
+ result += record->buf[i];
+ }
+
+ return (result == 0);
+}
+
+static hex_line_t line = {0}, shadow_line = {0};
+static uint32_t next_address_to_write = 0;
+static uint8_t low_nibble = 0, idx = 0, record_processed = 0, load_unaligned_record = 0;
+
+void reset_hex_parser(void)
+{
+ memset(line.buf, 0, sizeof(hex_line_t));
+ memset(shadow_line.buf, 0, sizeof(hex_line_t));
+ next_address_to_write = 0;
+ low_nibble = 0;
+ idx = 0;
+ record_processed = 0;
+ load_unaligned_record = 0;
+}
+
+hexfile_parse_status_t parse_hex_blob(const uint8_t *hex_blob, const uint32_t hex_blob_size, uint32_t *hex_parse_cnt, uint8_t *bin_buf, const uint32_t bin_buf_size, uint32_t *bin_buf_address, uint32_t *bin_buf_cnt)
+{
+ uint8_t *end = (uint8_t *)hex_blob + hex_blob_size;
+ hexfile_parse_status_t status = HEX_PARSE_UNINIT;
+ // reset the amount of data that is being return'd
+ *bin_buf_cnt = (uint32_t)0;
+
+ // we had an exit state where the address was unaligned to the previous record and data count.
+ // Need to pop the last record into the buffer before decoding anthing else since it was
+ // already decoded.
+ if (load_unaligned_record) {
+ // need some help...
+ load_unaligned_record = 0;
+ // move from line buffer back to input buffer
+ memcpy((uint8_t *)bin_buf, (uint8_t *)line.data, line.byte_count);
+ bin_buf += line.byte_count;
+ *bin_buf_cnt = (uint32_t)(*bin_buf_cnt) + line.byte_count;
+ // Store next address to write
+ next_address_to_write = ((next_address_to_write & 0xffff0000) | line.address) + line.byte_count;
+ }
+
+ while (hex_blob != end) {
+ switch ((uint8_t)(*hex_blob)) {
+ // we've hit the end of an ascii line
+ // junk we dont care about could also just run the validate_checksum on &line
+ case '\r':
+ case '\n':
+ //ignore new lines
+ break;
+
+ // found start of a new record. reset state variables
+ case ':':
+ memset(line.buf, 0, sizeof(hex_line_t));
+ low_nibble = 0;
+ idx = 0;
+ record_processed = 0;
+ break;
+
+ // decoding lines
+ default:
+ if (low_nibble) {
+ line.buf[idx] |= ctoh((uint8_t)(*hex_blob)) & 0xf;
+ if (++idx >= (line.byte_count + 5)) { //all data in
+ if (0 == validate_checksum(&line)) {
+ status = HEX_PARSE_CKSUM_FAIL;
+ goto hex_parser_exit;
+ } else {
+ if (!record_processed) {
+ record_processed = 1;
+ // address byteswap...
+ line.address = swap16(line.address);
+
+ switch (line.record_type) {
+ case DATA_RECORD:
+ // keeping a record of the last hex record
+ memcpy(shadow_line.buf, line.buf, sizeof(hex_line_t));
+
+ // verify this is a continous block of memory or need to exit and dump
+ if (((next_address_to_write & 0xffff0000) | line.address) != next_address_to_write) {
+ load_unaligned_record = 1;
+ status = HEX_PARSE_UNALIGNED;
+ goto hex_parser_exit;
+ }
+
+ // move from line buffer back to input buffer
+ memcpy(bin_buf, line.data, line.byte_count);
+ bin_buf += line.byte_count;
+ *bin_buf_cnt = (uint32_t)(*bin_buf_cnt) + line.byte_count;
+ // Save next address to write
+ next_address_to_write = ((next_address_to_write & 0xffff0000) | line.address) + line.byte_count;
+ break;
+
+ case EOF_RECORD:
+ status = HEX_PARSE_EOF;
+ goto hex_parser_exit;
+
+ case EXT_SEG_ADDR_RECORD:
+ // Could have had data in the buffer so must exit and try to program
+ // before updating bin_buf_address with next_address_to_write
+ memset(bin_buf, 0xff, (bin_buf_size - (uint32_t)(*bin_buf_cnt)));
+ // figure the start address for the buffer before returning
+ *bin_buf_address = next_address_to_write - (uint32_t)(*bin_buf_cnt);
+ *hex_parse_cnt = (uint32_t)(hex_blob_size - (end - hex_blob));
+ // update the address msb's
+ next_address_to_write = (next_address_to_write & 0x00000000) | ((line.data[0] << 12) | (line.data[1] << 4));
+ // Need to exit and program if buffer has been filled
+ status = HEX_PARSE_UNALIGNED;
+ return status;
+
+ case EXT_LINEAR_ADDR_RECORD:
+ // Could have had data in the buffer so must exit and try to program
+ // before updating bin_buf_address with next_address_to_write
+ // Good catch Gaute!!
+ memset(bin_buf, 0xff, (bin_buf_size - (uint32_t)(*bin_buf_cnt)));
+ // figure the start address for the buffer before returning
+ *bin_buf_address = next_address_to_write - (uint32_t)(*bin_buf_cnt);
+ *hex_parse_cnt = (uint32_t)(hex_blob_size - (end - hex_blob));
+ // update the address msb's
+ next_address_to_write = (next_address_to_write & 0x00000000) | ((line.data[0] << 24) | (line.data[1] << 16));
+ // Need to exit and program if buffer has been filled
+ status = HEX_PARSE_UNALIGNED;
+ return status;
+
+ default:
+ break;
+ }
+ }
+ }
+ }
+ } else {
+ if (idx < sizeof(hex_line_t)) {
+ line.buf[idx] = ctoh((uint8_t)(*hex_blob)) << 4;
+ }
+ }
+
+ low_nibble = !low_nibble;
+ break;
+ }
+
+ hex_blob++;
+ }
+
+ // decoded an entire hex block - verify (cant do this hex_parse_cnt is figured below)
+ //status = (hex_blob_size == (uint32_t)(*hex_parse_cnt)) ? HEX_PARSE_OK : HEX_PARSE_FAILURE;
+ status = HEX_PARSE_OK;
+hex_parser_exit:
+ memset(bin_buf, 0xff, (bin_buf_size - (uint32_t)(*bin_buf_cnt)));
+ // figure the start address for the buffer before returning
+ *bin_buf_address = next_address_to_write - (uint32_t)(*bin_buf_cnt);
+ *hex_parse_cnt = (uint32_t)(hex_blob_size - (end - hex_blob));
+ return status;
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/drag-n-drop/intelhex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/drag-n-drop/intelhex.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,72 @@
+/**
+ * @file intelhex.h
+ * @brief Parser for the intel hex format
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef INTELHEX_H
+#define INTELHEX_H
+
+/** \ingroup hexfile_parser
+ * @{
+ */
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Type of states that the parser can return
+ * @enum hexfile_parse_status_t
+ */
+typedef enum {
+ HEX_PARSE_OK = 0, /*!< The input buffer was complete parsed and converted into the output buffer */
+ HEX_PARSE_EOF, /*!< EOF line found in the hex file */
+ HEX_PARSE_UNALIGNED, /*!< The address of decoded data isnt consecutive. Need to program what was returned and continue to parse the input buffer */
+ HEX_PARSE_LINE_OVERRUN, /*!< Error state when the record length is longer than the record structure */
+ HEX_PARSE_CKSUM_FAIL, /*!< Error state when the record checksum doesnt properly compute */
+ HEX_PARSE_UNINIT, /*!< Default state. Return of this type is unrecoverable logic error */
+ HEX_PARSE_FAILURE /*!< Amount of hex data to decode didnt match the parsing logics count of decoded bytes */
+} hexfile_parse_status_t;
+
+/** Prepare any state that is maintained for the start of a file
+ * @param none
+ * @return none
+ */
+void reset_hex_parser(void);
+
+/** Convert a blob of hex data into its binary equivelant
+ * @param hex_blob A block of ascii encoded hexfile data
+ * @param hex_blob_size The amount of valid data in the hex_blob
+ * @param hex_parse_cnt The amount of hex_blob data from the call that was parsed
+ * @param bin_buf Buffer the decoded hex file contents goes into
+ * @param bin_buf_size max size of the buffer
+ * @param bin_buf_address The start address for data in the bin_buf as decoded from the hex file
+ * @param bin_buf_cnt The amount of data in the bin_buf
+ * @return A member of hex_parse_status_t that describes the state of decoding
+ */
+hexfile_parse_status_t parse_hex_blob(const uint8_t *hex_blob, const uint32_t hex_blob_size, uint32_t *hex_parse_cnt, uint8_t *bin_buf, const uint32_t bin_buf_size, uint32_t *bin_buf_address, uint32_t *bin_buf_cnt);
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/drag-n-drop/vfs_manager.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/drag-n-drop/vfs_manager.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,839 @@
+/**
+ * @file vfs_manager.c
+ * @brief Implementation of vfs_manager.h
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ctype.h>
+
+#include "main.h"
+#include "cmsis_os2.h"
+#include "rl_usb.h"
+#include "virtual_fs.h"
+#include "vfs_manager.h"
+#include "daplink_debug.h"
+#include "info.h"
+#include "settings.h"
+#include "daplink.h"
+#include "util.h"
+#include "version_git.h"
+#include "IO_Config.h"
+#include "file_stream.h"
+#include "error.h"
+
+// Set to 1 to enable debugging
+#define DEBUG_VFS_MANAGER 0
+
+#if DEBUG_VFS_MANAGER
+#define vfs_mngr_printf debug_msg
+#else
+#define vfs_mngr_printf(...)
+#endif
+
+#define INVALID_TIMEOUT_MS 0xFFFFFFFF
+#define MAX_EVENT_TIME_MS 60000
+
+#define CONNECT_DELAY_MS 0
+#define RECONNECT_DELAY_MS 2500 // Must be above 1s for windows (more for linux)
+// TRANSFER_IN_PROGRESS
+#define DISCONNECT_DELAY_TRANSFER_TIMEOUT_MS 20000
+// TRANSFER_CAN_BE_FINISHED
+#define DISCONNECT_DELAY_TRANSFER_IDLE_MS 500
+// TRANSFER_NOT_STARTED || TRASNFER_FINISHED
+#define DISCONNECT_DELAY_MS 500
+
+// Make sure none of the delays exceed the max time
+COMPILER_ASSERT(CONNECT_DELAY_MS < MAX_EVENT_TIME_MS);
+COMPILER_ASSERT(RECONNECT_DELAY_MS < MAX_EVENT_TIME_MS);
+COMPILER_ASSERT(DISCONNECT_DELAY_TRANSFER_TIMEOUT_MS < MAX_EVENT_TIME_MS);
+COMPILER_ASSERT(DISCONNECT_DELAY_TRANSFER_IDLE_MS < MAX_EVENT_TIME_MS);
+COMPILER_ASSERT(DISCONNECT_DELAY_MS < MAX_EVENT_TIME_MS);
+
+typedef enum {
+ TRANSFER_NOT_STARTED,
+ TRANSFER_IN_PROGRESS,
+ TRANSFER_CAN_BE_FINISHED,
+ TRASNFER_FINISHED,
+} transfer_state_t;
+
+typedef struct {
+ vfs_file_t file_to_program; // A pointer to the directory entry of the file being programmed
+ vfs_sector_t start_sector; // Start sector of the file being programmed by stream
+ vfs_sector_t file_start_sector; // Start sector of the file being programmed by vfs
+ vfs_sector_t file_next_sector; // Expected next sector of the file
+ vfs_sector_t last_ooo_sector; // Last out of order sector within the file
+ uint32_t size_processed; // The number of bytes processed by the stream
+ uint32_t file_size; // Size of the file indicated by root dir. Only allowed to increase
+ uint32_t size_transferred; // The number of bytes transferred
+ transfer_state_t transfer_state;// Transfer state
+ bool stream_open; // State of the stream
+ bool stream_started; // Stream processing started. This only gets reset remount
+ bool stream_finished; // Stream processing is done. This only gets reset remount
+ bool stream_optional_finish; // True if the stream processing can be considered done
+ bool file_info_optional_finish; // True if the file transfer can be considered done
+ bool transfer_timeout; // Set if the transfer was finished because of a timeout. This only gets reset remount
+ stream_type_t stream; // Current stream or STREAM_TYPE_NONE is stream is closed. This only gets reset remount
+} file_transfer_state_t;
+
+typedef enum {
+ VFS_MNGR_STATE_DISCONNECTED,
+ VFS_MNGR_STATE_RECONNECTING,
+ VFS_MNGR_STATE_CONNECTED
+} vfs_mngr_state_t;
+
+static const file_transfer_state_t default_transfer_state = {
+ VFS_FILE_INVALID,
+ VFS_INVALID_SECTOR,
+ VFS_INVALID_SECTOR,
+ VFS_INVALID_SECTOR,
+ VFS_INVALID_SECTOR,
+ 0,
+ 0,
+ 0,
+ TRANSFER_NOT_STARTED,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ STREAM_TYPE_NONE,
+};
+
+//Compile option not to include MSC at all, these will be dummy variables
+#ifndef MSC_ENDPOINT
+BOOL USBD_MSC_MediaReady = __FALSE;
+BOOL USBD_MSC_ReadOnly = __FALSE;
+U32 USBD_MSC_MemorySize;
+U32 USBD_MSC_BlockSize;
+U32 USBD_MSC_BlockGroup;
+U32 USBD_MSC_BlockCount;
+U8 *USBD_MSC_BlockBuf;
+#endif
+
+static uint32_t usb_buffer[VFS_SECTOR_SIZE / sizeof(uint32_t)];
+static error_t fail_reason = ERROR_SUCCESS;
+static file_transfer_state_t file_transfer_state;
+
+// These variables can be access from multiple threads
+// so access to them must be synchronized
+static vfs_mngr_state_t vfs_state;
+static vfs_mngr_state_t vfs_state_next;
+static uint32_t time_usb_idle;
+
+static osMutexId_t sync_mutex;
+static osThreadId_t sync_thread = 0;
+
+// Synchronization functions
+static void sync_init(void);
+static void sync_assert_usb_thread(void);
+static void sync_lock(void);
+static void sync_unlock(void);
+
+static bool changing_state(void);
+static void build_filesystem(void);
+static void file_change_handler(const vfs_filename_t filename, vfs_file_change_t change, vfs_file_t file, vfs_file_t new_file_data);
+static void file_data_handler(uint32_t sector, const uint8_t *buf, uint32_t num_of_sectors);
+static bool ready_for_state_change(void);
+static void abort_remount(void);
+
+static void transfer_update_file_info(vfs_file_t file, uint32_t start_sector, uint32_t size, stream_type_t stream);
+static void transfer_reset_file_info(void);
+static void transfer_stream_open(stream_type_t stream, uint32_t start_sector);
+static void transfer_stream_data(uint32_t sector, const uint8_t *data, uint32_t size);
+static void transfer_update_state(error_t status);
+
+
+void vfs_mngr_fs_enable(bool enable)
+{
+ sync_lock();
+
+ if (enable) {
+ if (VFS_MNGR_STATE_DISCONNECTED == vfs_state_next) {
+ vfs_state_next = VFS_MNGR_STATE_CONNECTED;
+ }
+ } else {
+ vfs_state_next = VFS_MNGR_STATE_DISCONNECTED;
+ }
+
+ sync_unlock();
+}
+
+void vfs_mngr_fs_remount(void)
+{
+ sync_lock();
+
+ // Only start a remount if in the connected state and not in a transition
+ if (!changing_state() && (VFS_MNGR_STATE_CONNECTED == vfs_state)) {
+ vfs_state_next = VFS_MNGR_STATE_RECONNECTING;
+ }
+
+ sync_unlock();
+}
+
+void vfs_mngr_init(bool enable)
+{
+ sync_assert_usb_thread();
+ build_filesystem();
+
+ if (enable) {
+ vfs_state = VFS_MNGR_STATE_CONNECTED;
+ vfs_state_next = VFS_MNGR_STATE_CONNECTED;
+ USBD_MSC_MediaReady = 1;
+ } else {
+ vfs_state = VFS_MNGR_STATE_DISCONNECTED;
+ vfs_state_next = VFS_MNGR_STATE_DISCONNECTED;
+ USBD_MSC_MediaReady = 0;
+ }
+}
+
+void vfs_mngr_periodic(uint32_t elapsed_ms)
+{
+ bool change_state;
+ vfs_mngr_state_t vfs_state_local;
+ vfs_mngr_state_t vfs_state_local_prev;
+ sync_assert_usb_thread();
+ sync_lock();
+
+ // Return immediately if the desired state has been reached
+ if (!changing_state()) {
+ sync_unlock();
+ return;
+ }
+
+ change_state = ready_for_state_change();
+
+ if (time_usb_idle < MAX_EVENT_TIME_MS) {
+ time_usb_idle += elapsed_ms;
+ }
+
+ if (!change_state) {
+ sync_unlock();
+ return;
+ }
+
+ vfs_mngr_printf("vfs_mngr_periodic()\r\n");
+ vfs_mngr_printf(" time_usb_idle=%i\r\n", time_usb_idle);
+ vfs_mngr_printf(" transfer_state=%i\r\n", file_transfer_state.transfer_state);
+ // Transistion to new state
+ vfs_state_local_prev = vfs_state;
+ vfs_state = vfs_state_next;
+
+ switch (vfs_state) {
+ case VFS_MNGR_STATE_RECONNECTING:
+ // Transition back to the connected state
+ vfs_state_next = VFS_MNGR_STATE_CONNECTED;
+ break;
+
+ default:
+ // No state change logic required in other states
+ break;
+ }
+
+ vfs_state_local = vfs_state;
+ time_usb_idle = 0;
+ sync_unlock();
+ // Processing when leaving a state
+ vfs_mngr_printf(" state %i->%i\r\n", vfs_state_local_prev, vfs_state_local);
+
+ switch (vfs_state_local_prev) {
+ case VFS_MNGR_STATE_DISCONNECTED:
+ // No action needed
+ break;
+
+ case VFS_MNGR_STATE_RECONNECTING:
+ // No action needed
+ break;
+
+ case VFS_MNGR_STATE_CONNECTED:
+
+ // Close ongoing transfer if there is one
+ if (file_transfer_state.transfer_state != TRASNFER_FINISHED) {
+ vfs_mngr_printf(" transfer timeout\r\n");
+ file_transfer_state.transfer_timeout = true;
+ transfer_update_state(ERROR_SUCCESS);
+ }
+
+ util_assert(TRASNFER_FINISHED == file_transfer_state.transfer_state);
+ vfs_user_disconnecting();
+ break;
+ }
+
+ // Processing when entering a state
+ switch (vfs_state_local) {
+ case VFS_MNGR_STATE_DISCONNECTED:
+ USBD_MSC_MediaReady = 0;
+ break;
+
+ case VFS_MNGR_STATE_RECONNECTING:
+ USBD_MSC_MediaReady = 0;
+ break;
+
+ case VFS_MNGR_STATE_CONNECTED:
+ build_filesystem();
+ USBD_MSC_MediaReady = 1;
+ break;
+ }
+
+ return;
+}
+
+error_t vfs_mngr_get_transfer_status()
+{
+ sync_assert_usb_thread();
+ return fail_reason;
+}
+
+void usbd_msc_init(void)
+{
+ sync_init();
+ build_filesystem();
+ vfs_state = VFS_MNGR_STATE_DISCONNECTED;
+ vfs_state_next = VFS_MNGR_STATE_DISCONNECTED;
+ time_usb_idle = 0;
+ USBD_MSC_MediaReady = 0;
+}
+
+void usbd_msc_read_sect(uint32_t sector, uint8_t *buf, uint32_t num_of_sectors)
+{
+ sync_assert_usb_thread();
+
+ // dont proceed if we're not ready
+ if (!USBD_MSC_MediaReady) {
+ return;
+ }
+
+ // indicate msc activity
+ main_blink_msc_led(MAIN_LED_FLASH);
+ vfs_read(sector, buf, num_of_sectors);
+}
+
+void usbd_msc_write_sect(uint32_t sector, uint8_t *buf, uint32_t num_of_sectors)
+{
+ sync_assert_usb_thread();
+
+ if (!USBD_MSC_MediaReady) {
+ return;
+ }
+
+ // Restart the disconnect counter on every packet
+ // so the device does not detach in the middle of a
+ // transfer.
+ time_usb_idle = 0;
+
+ if (TRASNFER_FINISHED == file_transfer_state.transfer_state) {
+ return;
+ }
+
+ // indicate msc activity
+ main_blink_msc_led(MAIN_LED_FLASH);
+ vfs_write(sector, buf, num_of_sectors);
+ if (TRASNFER_FINISHED == file_transfer_state.transfer_state) {
+ return;
+ }
+ file_data_handler(sector, buf, num_of_sectors);
+}
+
+static void sync_init(void)
+{
+ sync_thread = osThreadGetId();
+ sync_mutex = osMutexNew(NULL);
+}
+
+static void sync_assert_usb_thread(void)
+{
+ util_assert(osThreadGetId() == sync_thread);
+}
+
+static void sync_lock(void)
+{
+ osMutexAcquire(sync_mutex, 0);
+}
+
+static void sync_unlock(void)
+{
+ osMutexRelease(sync_mutex);
+}
+
+static bool changing_state()
+{
+ return vfs_state != vfs_state_next;
+}
+
+static void build_filesystem()
+{
+ // Update anything that could have changed file system state
+ file_transfer_state = default_transfer_state;
+ vfs_user_build_filesystem();
+ vfs_set_file_change_callback(file_change_handler);
+ // Set mass storage parameters
+ USBD_MSC_MemorySize = vfs_get_total_size();
+ USBD_MSC_BlockSize = VFS_SECTOR_SIZE;
+ USBD_MSC_BlockGroup = 1;
+ USBD_MSC_BlockCount = USBD_MSC_MemorySize / USBD_MSC_BlockSize;
+ USBD_MSC_BlockBuf = (uint8_t *)usb_buffer;
+}
+
+// Callback to handle changes to the root directory. Should be used with vfs_set_file_change_callback
+static void file_change_handler(const vfs_filename_t filename, vfs_file_change_t change, vfs_file_t file, vfs_file_t new_file_data)
+{
+ vfs_mngr_printf("vfs_manager file_change_handler(name=%*s, file=%p, change=%i)\r\n", 11, filename, file, change);
+ vfs_user_file_change_handler(filename, change, file, new_file_data);
+ if (TRASNFER_FINISHED == file_transfer_state.transfer_state) {
+ // If the transfer is finished stop further processing
+ return;
+ }
+
+ if (VFS_FILE_CHANGED == change) {
+ if (file == file_transfer_state.file_to_program) {
+ stream_type_t stream;
+ uint32_t size = vfs_file_get_size(new_file_data);
+ vfs_sector_t sector = vfs_file_get_start_sector(new_file_data);
+ stream = stream_type_from_name(filename);
+ transfer_update_file_info(file, sector, size, stream);
+ }
+ }
+
+ if (VFS_FILE_CREATED == change) {
+ stream_type_t stream;
+
+ if (STREAM_TYPE_NONE != stream_type_from_name(filename)) {
+ // Check for a know file extension to detect the current file being
+ // transferred. Ignore hidden files since MAC uses hidden files with
+ // the same extension to keep track of transfer info in some cases.
+ if (!(VFS_FILE_ATTR_HIDDEN & vfs_file_get_attr(new_file_data))) {
+ stream = stream_type_from_name(filename);
+ uint32_t size = vfs_file_get_size(new_file_data);
+ vfs_sector_t sector = vfs_file_get_start_sector(new_file_data);
+ transfer_update_file_info(file, sector, size, stream);
+ }
+ }
+ }
+
+ if (VFS_FILE_DELETED == change) {
+ if (file == file_transfer_state.file_to_program) {
+ // The file that was being transferred has been deleted
+ transfer_reset_file_info();
+ }
+ }
+}
+
+// Handler for file data arriving over USB. This function is responsible
+// for detecting the start of a BIN/HEX file and performing programming
+static void file_data_handler(uint32_t sector, const uint8_t *buf, uint32_t num_of_sectors)
+{
+ stream_type_t stream;
+ uint32_t size;
+
+ // this is the key for starting a file write - we dont care what file types are sent
+ // just look for something unique (NVIC table, hex, srec, etc) until root dir is updated
+ if (!file_transfer_state.stream_started) {
+ // look for file types we can program
+ stream = stream_start_identify((uint8_t *)buf, VFS_SECTOR_SIZE * num_of_sectors);
+
+ if (STREAM_TYPE_NONE != stream) {
+ transfer_stream_open(stream, sector);
+ }
+ }
+
+ if (file_transfer_state.stream_started) {
+ // Ignore sectors coming before this file
+ if (sector < file_transfer_state.start_sector) {
+ return;
+ }
+
+ // sectors must be in order
+ if (sector != file_transfer_state.file_next_sector) {
+ vfs_mngr_printf("vfs_manager file_data_handler sector=%i\r\n", sector);
+
+ if (sector < file_transfer_state.file_next_sector) {
+ vfs_mngr_printf(" sector out of order! lowest ooo = %i\r\n",
+ file_transfer_state.last_ooo_sector);
+
+ if (VFS_INVALID_SECTOR == file_transfer_state.last_ooo_sector) {
+ file_transfer_state.last_ooo_sector = sector;
+ }
+
+ file_transfer_state.last_ooo_sector =
+ MIN(file_transfer_state.last_ooo_sector, sector);
+ } else {
+ vfs_mngr_printf(" sector not part of file transfer\r\n");
+ }
+
+ vfs_mngr_printf(" discarding data - size transferred=0x%x, data=%x,%x,%x,%x,...\r\n",
+ file_transfer_state.size_transferred, buf[0], buf[1], buf[2], buf[3]);
+ return;
+ }
+
+ // This sector could be part of the file so record it
+ size = VFS_SECTOR_SIZE * num_of_sectors;
+ file_transfer_state.size_transferred += size;
+ file_transfer_state.file_next_sector = sector + num_of_sectors;
+
+ // If stream processing is done then discard the data
+ if (file_transfer_state.stream_finished) {
+ vfs_mngr_printf("vfs_manager file_data_handler\r\n sector=%i, size=%i\r\n", sector, size);
+ vfs_mngr_printf(" discarding data - size transferred=0x%x, data=%x,%x,%x,%x,...\r\n",
+ file_transfer_state.size_transferred, buf[0], buf[1], buf[2], buf[3]);
+ transfer_update_state(ERROR_SUCCESS);
+ return;
+ }
+
+ transfer_stream_data(sector, buf, size);
+ }
+}
+
+static bool ready_for_state_change(void)
+{
+ uint32_t timeout_ms = INVALID_TIMEOUT_MS;
+ util_assert(vfs_state != vfs_state_next);
+
+ if (VFS_MNGR_STATE_CONNECTED == vfs_state) {
+ switch (file_transfer_state.transfer_state) {
+ case TRANSFER_NOT_STARTED:
+ case TRASNFER_FINISHED:
+ timeout_ms = DISCONNECT_DELAY_MS;
+ break;
+
+ case TRANSFER_IN_PROGRESS:
+ timeout_ms = DISCONNECT_DELAY_TRANSFER_TIMEOUT_MS;
+ break;
+
+ case TRANSFER_CAN_BE_FINISHED:
+ timeout_ms = DISCONNECT_DELAY_TRANSFER_IDLE_MS;
+ break;
+
+ default:
+ util_assert(0);
+ timeout_ms = DISCONNECT_DELAY_MS;
+ break;
+ }
+ } else if ((VFS_MNGR_STATE_DISCONNECTED == vfs_state) &&
+ (VFS_MNGR_STATE_CONNECTED == vfs_state_next)) {
+ timeout_ms = CONNECT_DELAY_MS;
+ } else if ((VFS_MNGR_STATE_RECONNECTING == vfs_state) &&
+ (VFS_MNGR_STATE_CONNECTED == vfs_state_next)) {
+ timeout_ms = RECONNECT_DELAY_MS;
+ } else if ((VFS_MNGR_STATE_RECONNECTING == vfs_state) &&
+ (VFS_MNGR_STATE_DISCONNECTED == vfs_state_next)) {
+ timeout_ms = 0;
+ }
+
+ if (INVALID_TIMEOUT_MS == timeout_ms) {
+ util_assert(0);
+ timeout_ms = 0;
+ }
+
+ return time_usb_idle > timeout_ms ? true : false;
+}
+
+// Abort a remount if one is pending
+void abort_remount(void)
+{
+ sync_lock();
+
+ // Only abort a remount if in the connected state and reconnecting is the next state
+ if ((VFS_MNGR_STATE_RECONNECTING == vfs_state_next) && (VFS_MNGR_STATE_CONNECTED == vfs_state)) {
+ vfs_state_next = VFS_MNGR_STATE_CONNECTED;
+ }
+
+ sync_unlock();
+}
+
+// Update the tranfer state with file information
+static void transfer_update_file_info(vfs_file_t file, uint32_t start_sector, uint32_t size, stream_type_t stream)
+{
+ vfs_mngr_printf("vfs_manager transfer_update_file_info(file=%p, start_sector=%i, size=%i)\r\n", file, start_sector, size);
+
+ if (TRASNFER_FINISHED == file_transfer_state.transfer_state) {
+ util_assert(0);
+ return;
+ }
+
+ // Initialize the directory entry if it has not been set
+ if (VFS_FILE_INVALID == file_transfer_state.file_to_program) {
+ file_transfer_state.file_to_program = file;
+
+ if (file != VFS_FILE_INVALID) {
+ vfs_mngr_printf(" file_to_program=%p\r\n", file);
+ }
+ }
+
+ // Initialize the starting sector if it has not been set
+ if (VFS_INVALID_SECTOR == file_transfer_state.file_start_sector) {
+ file_transfer_state.file_start_sector = start_sector;
+
+ if (start_sector != VFS_INVALID_SECTOR) {
+ vfs_mngr_printf(" start_sector=%i\r\n", start_sector);
+ }
+ }
+
+ // Initialize the stream if it has not been set
+ if (STREAM_TYPE_NONE == file_transfer_state.stream) {
+ file_transfer_state.stream = stream;
+
+ if (stream != STREAM_TYPE_NONE) {
+ vfs_mngr_printf(" stream=%i\r\n", stream);
+ }
+ }
+
+ // Check - File size must either grow or be smaller than the size already transferred
+ if ((size < file_transfer_state.file_size) && (size < file_transfer_state.size_transferred) && (size > 0)) {
+ vfs_mngr_printf(" error: file size changed from %i to %i\r\n", file_transfer_state.file_size, size);
+ transfer_update_state(ERROR_ERROR_DURING_TRANSFER);
+ return;
+ }
+
+ // Check - Starting sector must be the same - this is optional for file info since it may not be present initially
+ if ((VFS_INVALID_SECTOR != start_sector) && (start_sector != file_transfer_state.file_start_sector)) {
+ vfs_mngr_printf(" error: starting sector changed from %i to %i\r\n", file_transfer_state.file_start_sector, start_sector);
+ transfer_update_state(ERROR_ERROR_DURING_TRANSFER);
+ return;
+ }
+
+ // Check - stream must be the same
+ if ((stream != STREAM_TYPE_NONE) && (stream != file_transfer_state.stream)) {
+ vfs_mngr_printf(" error: changed types during transfer from %i to %i\r\n", file_transfer_state.stream, stream);
+ transfer_update_state(ERROR_ERROR_DURING_TRANSFER);
+ return;
+ }
+
+ // Update values - Size is the only value that can change
+ file_transfer_state.file_size = size;
+ vfs_mngr_printf(" updated size=%i\r\n", size);
+
+ transfer_update_state(ERROR_SUCCESS);
+}
+
+// Reset the transfer information or error if transfer is already in progress
+static void transfer_reset_file_info()
+{
+ vfs_mngr_printf("vfs_manager transfer_reset_file_info()\r\n");
+ //check if the data started streaming; size can be updated on matching start sector and stream type
+ if(file_transfer_state.stream_started){
+ //file, start sector and size has to be updated
+ file_transfer_state.file_to_program = VFS_FILE_INVALID;
+ file_transfer_state.file_start_sector = VFS_INVALID_SECTOR;
+ file_transfer_state.file_size = 0;
+ }else{
+ file_transfer_state = default_transfer_state;
+ abort_remount();
+ }
+
+}
+
+// Update the tranfer state with new information
+static void transfer_stream_open(stream_type_t stream, uint32_t start_sector)
+{
+ error_t status;
+ util_assert(!file_transfer_state.stream_open);
+ util_assert(start_sector != VFS_INVALID_SECTOR);
+ vfs_mngr_printf("vfs_manager transfer_update_stream_open(stream=%i, start_sector=%i)\r\n",
+ stream, start_sector);
+
+ // Initialize the starting sector if it has not been set
+ if (VFS_INVALID_SECTOR == file_transfer_state.start_sector) {
+ file_transfer_state.start_sector = start_sector;
+
+ if (start_sector != VFS_INVALID_SECTOR) {
+ vfs_mngr_printf(" start_sector=%i\r\n", start_sector);
+ }
+ }
+
+ // Initialize the stream if it has not been set
+ if (STREAM_TYPE_NONE == file_transfer_state.stream) {
+ file_transfer_state.stream = stream;
+
+ if (stream != STREAM_TYPE_NONE) {
+ vfs_mngr_printf(" stream=%i\r\n", stream);
+ }
+ }
+
+ // Check - Starting sector must be the same
+ if (start_sector != file_transfer_state.start_sector) {
+ vfs_mngr_printf(" error: starting sector changed from %i to %i\r\n", file_transfer_state.start_sector, start_sector);
+ transfer_update_state(ERROR_ERROR_DURING_TRANSFER);
+ return;
+ }
+
+ // Check - stream must be the same
+ if (stream != file_transfer_state.stream) {
+ vfs_mngr_printf(" error: changed types during transfer from %i to %i\r\n", file_transfer_state.stream, stream);
+ transfer_update_state(ERROR_ERROR_DURING_TRANSFER);
+ return;
+ }
+
+ // Open stream
+ status = stream_open(stream);
+ vfs_mngr_printf(" stream_open stream=%i ret %i\r\n", stream, status);
+
+ if (ERROR_SUCCESS == status) {
+ file_transfer_state.file_next_sector = start_sector;
+ file_transfer_state.stream_open = true;
+ file_transfer_state.stream_started = true;
+ }
+
+ transfer_update_state(status);
+}
+
+// Update the tranfer state with new information
+static void transfer_stream_data(uint32_t sector, const uint8_t *data, uint32_t size)
+{
+ error_t status;
+ vfs_mngr_printf("vfs_manager transfer_stream_data(sector=%i, size=%i)\r\n", sector, size);
+ vfs_mngr_printf(" size processed=0x%x, data=%x,%x,%x,%x,...\r\n",
+ file_transfer_state.size_processed, data[0], data[1], data[2], data[3]);
+
+ if (file_transfer_state.stream_finished) {
+ util_assert(0);
+ return;
+ }
+
+ util_assert(size % VFS_SECTOR_SIZE == 0);
+ util_assert(file_transfer_state.stream_open);
+ status = stream_write((uint8_t *)data, size);
+ vfs_mngr_printf(" stream_write ret=%i\r\n", status);
+
+ if (ERROR_SUCCESS_DONE == status) {
+ // Override status so ERROR_SUCCESS_DONE
+ // does not get passed into transfer_update_state
+ status = stream_close();
+ vfs_mngr_printf(" stream_close ret=%i\r\n", status);
+ file_transfer_state.stream_open = false;
+ file_transfer_state.stream_finished = true;
+ file_transfer_state.stream_optional_finish = true;
+ } else if (ERROR_SUCCESS_DONE_OR_CONTINUE == status) {
+ status = ERROR_SUCCESS;
+ file_transfer_state.stream_optional_finish = true;
+ } else {
+ file_transfer_state.stream_optional_finish = false;
+ }
+
+ file_transfer_state.size_processed += size;
+ transfer_update_state(status);
+}
+
+// Check if the current transfer is still in progress, done, or if an error has occurred
+static void transfer_update_state(error_t status)
+{
+ bool transfer_timeout;
+ bool transfer_started;
+ bool transfer_can_be_finished;
+ bool transfer_must_be_finished;
+ bool out_of_order_sector;
+ error_t local_status = status;
+ util_assert((status != ERROR_SUCCESS_DONE) &&
+ (status != ERROR_SUCCESS_DONE_OR_CONTINUE));
+
+ if (TRASNFER_FINISHED == file_transfer_state.transfer_state) {
+ util_assert(0);
+ return;
+ }
+
+ // Update file info status. The end of a file is never known for sure since
+ // what looks like a complete file could be part of a file getting flushed to disk.
+ // The criteria for an successful optional finish is
+ // 1. A file has been detected
+ // 2. The size of the file indicated in the root dir has been transferred
+ // 3. The file size is greater than zero
+ // 4. Matching start sector set by stream and vfs changes
+ file_transfer_state.file_info_optional_finish =
+ (file_transfer_state.file_to_program != VFS_FILE_INVALID) &&
+ (file_transfer_state.size_transferred >= file_transfer_state.file_size) &&
+ (file_transfer_state.file_size > 0) &&
+ (file_transfer_state.start_sector == file_transfer_state.file_start_sector);
+ transfer_timeout = file_transfer_state.transfer_timeout;
+ transfer_started = (VFS_FILE_INVALID != file_transfer_state.file_to_program) ||
+ (STREAM_TYPE_NONE != file_transfer_state.stream);
+ // The transfer can be finished if both file and stream processing
+ // can be considered complete
+ transfer_can_be_finished = file_transfer_state.file_info_optional_finish &&
+ file_transfer_state.stream_optional_finish;
+ // The transfer must be fnished if stream processing is for sure complete
+ // and file processing can be considered complete
+ transfer_must_be_finished = file_transfer_state.stream_finished &&
+ file_transfer_state.file_info_optional_finish;
+ out_of_order_sector = false;
+
+ if (file_transfer_state.last_ooo_sector != VFS_INVALID_SECTOR) {
+ util_assert(file_transfer_state.start_sector != VFS_INVALID_SECTOR);
+ uint32_t sector_offset = (file_transfer_state.last_ooo_sector -
+ file_transfer_state.start_sector) * VFS_SECTOR_SIZE;
+
+ if (sector_offset < file_transfer_state.size_processed) {
+ // The out of order sector was within the range of data already
+ // processed.
+ out_of_order_sector = true;
+ }
+ }
+
+ // Set the transfer state and set the status if necessary
+ if (local_status != ERROR_SUCCESS) {
+ file_transfer_state.transfer_state = TRASNFER_FINISHED;
+ } else if (transfer_timeout) {
+ if (out_of_order_sector) {
+ local_status = ERROR_OOO_SECTOR;
+ } else if (!transfer_started) {
+ local_status = ERROR_SUCCESS;
+ } else if (transfer_can_be_finished) {
+ local_status = ERROR_SUCCESS;
+ } else {
+ local_status = ERROR_TRANSFER_TIMEOUT;
+ }
+
+ file_transfer_state.transfer_state = TRASNFER_FINISHED;
+ } else if (transfer_must_be_finished) {
+ file_transfer_state.transfer_state = TRASNFER_FINISHED;
+ } else if (transfer_can_be_finished) {
+ file_transfer_state.transfer_state = TRANSFER_CAN_BE_FINISHED;
+ } else if (transfer_started) {
+ file_transfer_state.transfer_state = TRANSFER_IN_PROGRESS;
+ }
+
+ if (TRASNFER_FINISHED == file_transfer_state.transfer_state) {
+ vfs_mngr_printf("vfs_manager transfer_update_state(status=%i)\r\n", status);
+ vfs_mngr_printf(" file=%p, start_sect= %i %i, size=%i\r\n",
+ file_transfer_state.file_to_program, file_transfer_state.start_sector,
+ file_transfer_state.file_start_sector, file_transfer_state.file_size);
+ vfs_mngr_printf(" stream=%i, size_processed=%i, opt_finish=%i, timeout=%i\r\n",
+ file_transfer_state.stream, file_transfer_state.size_processed,
+ file_transfer_state.file_info_optional_finish, transfer_timeout);
+
+ // Close the file stream if it is open
+ if (file_transfer_state.stream_open) {
+ error_t close_status;
+ close_status = stream_close();
+ vfs_mngr_printf(" stream closed ret=%i\r\n", close_status);
+ file_transfer_state.stream_open = false;
+
+ if (ERROR_SUCCESS == local_status) {
+ local_status = close_status;
+ }
+ }
+
+ // Set the fail reason
+ fail_reason = local_status;
+ vfs_mngr_printf(" Transfer finished, status: %i=%s\r\n", fail_reason, error_get_string(fail_reason));
+ }
+
+ // If this state change is not from aborting a transfer
+ // due to a remount then trigger a remount
+ if (!transfer_timeout) {
+ vfs_mngr_fs_remount();
+ }
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/drag-n-drop/vfs_manager.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/drag-n-drop/vfs_manager.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,79 @@
+/**
+ * @file vfs_manager.h
+ * @brief Methods that build and manipulate a virtual file system
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef VFS_MANAGER_USER_H
+#define VFS_MANAGER_USER_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "virtual_fs.h"
+#include "error.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+extern const vfs_filename_t daplink_mode_file_name;
+
+/* Callable from anywhere */
+
+// Enable or disable the virtual filesystem
+void vfs_mngr_fs_enable(bool enabled);
+
+// Remount the virtual filesystem
+void vfs_mngr_fs_remount(void);
+
+
+/* Callable only from the thread running the virtual fs */
+
+// Initialize the VFS manager
+// Must be called after USB has been initialized (usbd_init())
+// Notes: Must only be called from the thread runnning USB
+void vfs_mngr_init(bool enabled);
+
+// Run the vfs manager state machine
+// Notes: Must only be called from the thread runnning USB
+void vfs_mngr_periodic(uint32_t elapsed_ms);
+
+// Return the status of the last transfer or ERROR_SUCCESS
+// if none have been performed yet
+error_t vfs_mngr_get_transfer_status(void);
+
+
+/* Use functions */
+
+// Build the filesystem by calling vfs_init and then adding files with vfs_create_file
+void vfs_user_build_filesystem(void);
+
+// Called when a file on the filesystem changes
+void vfs_user_file_change_handler(const vfs_filename_t filename, vfs_file_change_t change, vfs_file_t file, vfs_file_t new_file_data);
+
+// Called when VFS is disconnecting
+void vfs_user_disconnecting(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/drag-n-drop/vfs_user.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/drag-n-drop/vfs_user.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,656 @@
+/**
+ * @file vfs_user.c
+ * @brief Implementation of vfs_user.h
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2020, ARM Limited, All Rights Reserved
+ * Copyright 2019, Cypress Semiconductor Corporation
+ * or a subsidiary of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdbool.h>
+#include <ctype.h>
+#include <string.h>
+
+#include "vfs_user.h"
+#include "vfs_manager.h"
+#include "error.h"
+#include "util.h"
+#include "settings.h"
+#include "daplink.h"
+#include "version_git.h"
+#include "info.h"
+#include "gpio.h" // for gpio_get_sw_reset
+#include "flash_intf.h" // for flash_intf_target
+#include "cortex_m.h"
+#include "target_board.h"
+#include "flash_manager.h"
+
+//! @brief Size in bytes of the virtual disk.
+//!
+//! Must be bigger than 4x the flash size of the biggest supported
+//! device. This is to accomodate for hex file programming.
+#define VFS_DISK_SIZE (MB(64))
+
+//! @brief Constants for magic action or config files.
+//!
+//! The "magic files" are files with a special name that if created on the USB MSC volume, will
+//! cause an event. There are two classes of magic files: action files and config files. The former
+//! causes a given action to take place, while the latter changes a persistent configuration setting
+//! to a predetermined value.
+//!
+//! See #s_magic_file_info for the mapping of filenames to these enums.
+typedef enum _magic_file {
+ kDAPLinkModeActionFile, //!< Switch between interface and bootloader.
+ kTestAssertActionFile, //!< Force an assertion for testing.
+ kRefreshActionFile, //!< Force a remount.
+ kEraseActionFile, //!< Erase the target flash.
+ kAutoResetConfigFile, //!< Enable reset after flash.
+ kHardResetConfigFile, //!< Disable reset after flash.
+ kAutomationOnConfigFile, //!< Enable automation.
+ kAutomationOffConfigFile, //!< Disable automation.
+ kOverflowOnConfigFile, //!< Enable UART overflow reporting.
+ kOverflowOffConfigFile, //!< Disable UART overflow reporting.
+ kMSDOnConfigFile, //!< Enable USB MSC. Uh....
+ kMSDOffConfigFile, //!< Disable USB MSC.
+ kPageEraseActionFile, //!< Enable page programming and sector erase for drag and drop.
+ kChipEraseActionFile, //!< Enable page programming and chip erase for drag and drop.
+} magic_file_t;
+
+//! @brief Mapping from filename string to magic file enum.
+typedef struct _magic_file_info {
+ const char *name; //!< Name of the magic file, must be in 8.3 format.
+ magic_file_t which; //!< Enum for the file.
+} magic_file_info_t;
+
+static const char mbed_redirect_file[] =
+ "<!doctype html>\r\n"
+ "<!-- mbed Platform Website and Authentication Shortcut -->\r\n"
+ "<html>\r\n"
+ "<head>\r\n"
+ "<meta charset=\"utf-8\">\r\n"
+ "<title>mbed Website Shortcut</title>\r\n"
+ "</head>\r\n"
+ "<body>\r\n"
+ "<script>\r\n"
+ "window.location.replace(\"@R\");\r\n"
+ "</script>\r\n"
+ "</body>\r\n"
+ "</html>\r\n";
+
+static const char error_prefix[] = "error: ";
+static const char error_type_prefix[] = "type: ";
+
+static const vfs_filename_t assert_file = "ASSERT TXT";
+
+//! @brief Table of magic files and their names.
+static const magic_file_info_t s_magic_file_info[] = {
+ { daplink_mode_file_name, kDAPLinkModeActionFile },
+ { "ASSERT ACT", kTestAssertActionFile },
+ { "REFRESH ACT", kRefreshActionFile },
+ { "ERASE ACT", kEraseActionFile },
+ { "AUTO_RSTCFG", kAutoResetConfigFile },
+ { "HARD_RSTCFG", kHardResetConfigFile },
+ { "AUTO_ON CFG", kAutomationOnConfigFile },
+ { "AUTO_OFFCFG", kAutomationOffConfigFile },
+ { "OVFL_ON CFG", kOverflowOnConfigFile },
+ { "OVFL_OFFCFG", kOverflowOffConfigFile },
+ { "MSD_ON CFG", kMSDOnConfigFile },
+ { "MSD_OFF CFG", kMSDOffConfigFile },
+ { "PAGE_ON ACT", kPageEraseActionFile },
+ { "PAGE_OFFACT", kChipEraseActionFile },
+ };
+
+static uint8_t file_buffer[VFS_SECTOR_SIZE];
+static char assert_buf[64 + 1];
+static uint16_t assert_line;
+static assert_source_t assert_source;
+static uint32_t remount_count;
+
+static uint32_t get_file_size(vfs_read_cb_t read_func);
+
+static uint32_t read_file_mbed_htm(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors);
+static uint32_t read_file_details_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors);
+static uint32_t read_file_fail_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors);
+static uint32_t read_file_assert_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors);
+static uint32_t read_file_need_bl_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors);
+
+static uint32_t update_html_file(uint8_t *data, uint32_t datasize);
+static uint32_t update_details_txt_file(uint8_t *data, uint32_t datasize);
+static void erase_target(void);
+
+static uint32_t expand_info(uint8_t *buf, uint32_t bufsize);
+
+void vfs_user_build_filesystem()
+{
+ uint32_t file_size;
+ vfs_file_t file_handle;
+ // Setup the filesystem based on target parameters
+ vfs_init(get_daplink_drive_name(), VFS_DISK_SIZE);
+ // MBED.HTM
+ file_size = get_file_size(read_file_mbed_htm);
+ vfs_create_file(get_daplink_url_name(), read_file_mbed_htm, 0, file_size);
+ // DETAILS.TXT
+ file_size = get_file_size(read_file_details_txt);
+ vfs_create_file("DETAILS TXT", read_file_details_txt, 0, file_size);
+
+ // FAIL.TXT
+ if (vfs_mngr_get_transfer_status() != ERROR_SUCCESS) {
+ file_size = get_file_size(read_file_fail_txt);
+ vfs_create_file("FAIL TXT", read_file_fail_txt, 0, file_size);
+ }
+
+ // ASSERT.TXT
+ if (config_ram_get_assert(assert_buf, sizeof(assert_buf), &assert_line, &assert_source)) {
+ file_size = get_file_size(read_file_assert_txt);
+ file_handle = vfs_create_file(assert_file, read_file_assert_txt, 0, file_size);
+ vfs_file_set_attr(file_handle, (vfs_file_attr_bit_t)0); // Remove read only attribute
+ }
+
+ // NEED_BL.TXT
+ volatile uint32_t bl_start = DAPLINK_ROM_BL_START; // Silence warnings about null pointer
+ volatile uint32_t if_start = DAPLINK_ROM_IF_START; // Silence warnings about null pointer
+
+ if (daplink_is_interface() &&
+ (DAPLINK_ROM_BL_SIZE > 0) &&
+ (0 == memcmp((void *)bl_start, (void *)if_start, DAPLINK_MIN_WRITE_SIZE))) {
+ // If the bootloader contains a copy of the interfaces vector table
+ // then an error occurred when updating so warn that the bootloader is
+ // missing.
+ file_size = get_file_size(read_file_need_bl_txt);
+ vfs_create_file("NEED_BL TXT", read_file_need_bl_txt, 0, file_size);
+ }
+}
+
+// Default file change hook.
+__WEAK bool vfs_user_file_change_handler_hook(const vfs_filename_t filename, vfs_file_change_t change,
+ vfs_file_t file, vfs_file_t new_file_data)
+{
+ return false;
+}
+
+// Default magic file hook.
+__WEAK bool vfs_user_magic_file_hook(const vfs_filename_t filename, bool *do_remount)
+{
+ return false;
+}
+
+// Callback to handle changes to the root directory. Should be used with vfs_set_file_change_callback
+void vfs_user_file_change_handler(const vfs_filename_t filename, vfs_file_change_t change, vfs_file_t file, vfs_file_t new_file_data)
+{
+ // Call file changed hook. If it returns true, then it handled the request and we have nothing
+ // more to do.
+ if (vfs_user_file_change_handler_hook(filename, change, file, new_file_data)) {
+ return;
+ }
+
+ // Allow settings to be changed if automation mode is
+ // enabled or if the user is holding the reset button
+ bool btn_pressed = gpio_get_reset_btn();
+
+ if (!btn_pressed && !config_get_automation_allowed()) {
+ return;
+ }
+
+ if (VFS_FILE_CHANGED == change) {
+ // Unused
+ }
+
+ else if (VFS_FILE_CREATED == change) {
+ bool do_remount = true; // Almost all magic files cause a remount.
+ int32_t which_magic_file = -1;
+
+ // Let the hook examine the filename. If it returned false then look for the standard
+ // magic files.
+ if (!vfs_user_magic_file_hook(filename, &do_remount)) {
+ // Compare the new file's name to our table of magic filenames.
+ for (int32_t i = 0; i < ARRAY_SIZE(s_magic_file_info); ++i) {
+ if (!memcmp(filename, s_magic_file_info[i].name, sizeof(vfs_filename_t))) {
+ which_magic_file = i;
+ }
+ }
+
+ // Check if we matched a magic filename and handle it.
+ if (which_magic_file != -1) {
+ switch (which_magic_file) {
+ case kDAPLinkModeActionFile:
+ if (daplink_is_interface()) {
+ config_ram_set_hold_in_bl(true);
+ } else {
+ // Do nothing - bootloader will go to interface by default
+ }
+ break;
+ case kTestAssertActionFile:
+ // Test asserts
+ util_assert(0);
+ do_remount = false;
+ break;
+ case kRefreshActionFile:
+ // Remount to update the drive
+ break;
+ case kEraseActionFile:
+ erase_target();
+ break;
+ case kAutoResetConfigFile:
+ config_set_auto_rst(true);
+ break;
+ case kHardResetConfigFile:
+ config_set_auto_rst(false);
+ break;
+ case kAutomationOnConfigFile:
+ config_set_automation_allowed(true);
+ break;
+ case kAutomationOffConfigFile:
+ config_set_automation_allowed(false);
+ break;
+ case kOverflowOnConfigFile:
+ config_set_overflow_detect(true);
+ break;
+ case kOverflowOffConfigFile:
+ config_set_overflow_detect(false);
+ break;
+ case kMSDOnConfigFile:
+ config_ram_set_disable_msd(false);
+ break;
+ case kMSDOffConfigFile:
+ config_ram_set_disable_msd(true);
+ break;
+ case kPageEraseActionFile:
+ config_ram_set_page_erase(true);
+ break;
+ case kChipEraseActionFile:
+ config_ram_set_page_erase(false);
+ break;
+ default:
+ util_assert(false);
+ }
+ }
+ else {
+ do_remount = false;
+ }
+ }
+
+ // Remount if requested.
+ if (do_remount) {
+ vfs_mngr_fs_remount();
+ }
+ }
+
+ else if (VFS_FILE_DELETED == change) {
+ if (!memcmp(filename, assert_file, sizeof(vfs_filename_t))) {
+ // Clear assert and remount to update the drive
+ util_assert_clear();
+ vfs_mngr_fs_remount();
+ }
+ }
+}
+
+void vfs_user_disconnecting()
+{
+ // Reset if programming was successful //TODO - move to flash layer
+ if (daplink_is_bootloader() && (ERROR_SUCCESS == vfs_mngr_get_transfer_status())) {
+ SystemReset();
+ }
+
+ // If hold in bootloader has been set then reset after usb is disconnected
+ if (daplink_is_interface() && (config_ram_get_hold_in_bl() || config_ram_get_disable_msd()==1)) {
+ SystemReset();
+ }
+
+ remount_count++;
+}
+
+// Get the filesize from a filesize callback.
+// The file data must be null terminated for this to work correctly.
+static uint32_t get_file_size(vfs_read_cb_t read_func)
+{
+ // Determine size of the file by faking a read
+ return read_func(0, file_buffer, 1);
+}
+
+// File callback to be used with vfs_add_file to return file contents
+static uint32_t read_file_mbed_htm(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors)
+{
+ if (sector_offset != 0) {
+ return 0;
+ }
+
+ return update_html_file(data, VFS_SECTOR_SIZE);
+}
+
+// File callback to be used with vfs_add_file to return file contents
+static uint32_t read_file_details_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors)
+{
+
+ if (sector_offset != 0) {
+ return 0;
+ }
+
+ return update_details_txt_file(data, VFS_SECTOR_SIZE);
+}
+
+// Text representation of each error type, starting from the rightmost bit
+static const char* const error_type_names[] = {
+ "internal",
+ "transient",
+ "user",
+ "target",
+ "interface"
+};
+
+COMPILER_ASSERT(1 << ARRAY_SIZE(error_type_names) == ERROR_TYPE_MASK + 1);
+
+// File callback to be used with vfs_add_file to return file contents
+static uint32_t read_file_fail_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors)
+{
+ uint32_t size = 0;
+ char *buf = (char *)data;
+ error_t status = vfs_mngr_get_transfer_status();
+ const char *contents = error_get_string(status);
+ error_type_t type = error_get_type(status);
+
+ if (sector_offset != 0) {
+ return 0;
+ }
+
+ size += util_write_string(buf + size, error_prefix);
+ size += util_write_string(buf + size, contents);
+ size += util_write_string(buf + size, "\r\n");
+ size += util_write_string(buf + size, error_type_prefix);
+
+ // Write each applicable error type, separated by commas
+ int index = 0;
+ bool first = true;
+ while (type && index < ARRAY_SIZE(error_type_names)) {
+ if (!first) {
+ size += util_write_string(buf + size, ", ");
+ }
+ if (type & 1) {
+ size += util_write_string(buf + size, error_type_names[index]);
+ first = false;
+ }
+ index++;
+ type >>= 1;
+ }
+
+ size += util_write_string(buf + size, "\r\n");
+ return size;
+}
+
+// File callback to be used with vfs_add_file to return file contents
+static uint32_t read_file_assert_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors)
+{
+ uint32_t pos;
+ const char *source_str;
+ char *buf = (char *)data;
+ uint32_t * hexdumps = 0;
+ uint8_t valid_hexdumps = 0;
+ uint8_t index = 0;
+
+ if (sector_offset != 0) {
+ return 0;
+ }
+
+ pos = 0;
+
+ if (ASSERT_SOURCE_BL == assert_source) {
+ source_str = "Bootloader";
+ } else if (ASSERT_SOURCE_APP == assert_source) {
+ source_str = "Application";
+ } else {
+ source_str = 0;
+ }
+
+ pos += util_write_string(buf + pos, "Assert\r\n");
+ pos += util_write_string(buf + pos, "File: ");
+ pos += util_write_string(buf + pos, assert_buf);
+ pos += util_write_string(buf + pos, "\r\n");
+ pos += util_write_string(buf + pos, "Line: ");
+ pos += util_write_uint32(buf + pos, assert_line);
+ pos += util_write_string(buf + pos, "\r\n");
+
+ if (source_str != 0) {
+ pos += util_write_string(buf + pos, "Source: ");
+ pos += util_write_string(buf + pos, source_str);
+ pos += util_write_string(buf + pos, "\r\n");
+ }
+
+ valid_hexdumps = config_ram_get_hexdumps(&hexdumps);
+ if ((valid_hexdumps > 0) && (hexdumps != 0)) {
+ //print hexdumps
+ pos += util_write_string(buf + pos, "Hexdumps\r\n");
+ while ((index < valid_hexdumps) && ((pos + 10) < VFS_SECTOR_SIZE)) { //hexdumps + newline is always 10 characters
+ pos += util_write_hex32(buf + pos, hexdumps[index++]);
+ pos += util_write_string(buf + pos, "\r\n");
+ }
+ }
+
+ return pos;
+}
+
+// File callback to be used with vfs_add_file to return file contents
+static uint32_t read_file_need_bl_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors)
+{
+ const char *contents = "A bootloader update was started but unable to complete.\r\n"
+ "Reload the bootloader to fix this error message.\r\n";
+ uint32_t size = strlen(contents);
+
+ if (sector_offset != 0) {
+ return 0;
+ }
+
+ memcpy(data, contents, size);
+ return size;
+}
+
+
+static uint32_t update_html_file(uint8_t *data, uint32_t datasize)
+{
+ char *buf = (char *)data;
+ //Needed by expand_info strlen
+ memset(buf, 0, datasize);
+ memcpy(buf, mbed_redirect_file, strlen(mbed_redirect_file));
+ //expand
+ return expand_info(data, datasize);
+}
+
+static uint32_t update_details_txt_file(uint8_t *data, uint32_t datasize)
+{
+ uint32_t pos=0;
+ const char *mode_str;
+
+ char *buf = (char *)data;
+
+ //Needed by expand_info strlen
+ memset(buf, 0, datasize);
+
+ pos += util_write_string(buf + pos, "# DAPLink Firmware - see https://mbed.com/daplink\r\n");
+ // Unique ID
+ pos += util_write_string(buf + pos, "Unique ID: @U\r\n");
+ // HIC ID
+ pos += util_write_string(buf + pos, "HIC ID: @D\r\n");
+ // Settings
+ pos += util_write_string(buf + pos, "Auto Reset: ");
+ pos += util_write_string(buf + pos, config_get_auto_rst() ? "1" : "0");
+ pos += util_write_string(buf + pos, "\r\n");
+ pos += util_write_string(buf + pos, "Automation allowed: ");
+ pos += util_write_string(buf + pos, config_get_automation_allowed() ? "1" : "0");
+ pos += util_write_string(buf + pos, "\r\n");
+ pos += util_write_string(buf + pos, "Overflow detection: ");
+ pos += util_write_string(buf + pos, config_get_overflow_detect() ? "1" : "0");
+ pos += util_write_string(buf + pos, "\r\n");
+ pos += util_write_string(buf + pos, "Page erasing: ");
+ pos += util_write_string(buf + pos, config_ram_get_page_erase() ? "1" : "0");
+ pos += util_write_string(buf + pos, "\r\n");
+ // Current mode
+ mode_str = daplink_is_bootloader() ? "Bootloader" : "Interface";
+ pos += util_write_string(buf + pos, "Daplink Mode: ");
+ pos += util_write_string(buf + pos, mode_str);
+ pos += util_write_string(buf + pos, "\r\n");
+ // Current build's version
+ pos += util_write_string(buf + pos, mode_str);
+ pos += util_write_string(buf + pos, " Version: @V\r\n");
+
+ // Other builds version (bl or if)
+ if (!daplink_is_bootloader() && info_get_bootloader_present()) {
+ pos += util_write_string(buf + pos, "Bootloader Version: ");
+ pos += util_write_uint32_zp(buf + pos, info_get_bootloader_version(), 4);
+ pos += util_write_string(buf + pos, "\r\n");
+ }
+
+ if (!daplink_is_interface() && info_get_interface_present()) {
+ pos += util_write_string(buf + pos, "Interface Version: ");
+ pos += util_write_uint32_zp(buf + pos, info_get_interface_version(), 4);
+ pos += util_write_string(buf + pos, "\r\n");
+ }
+
+ // GIT sha
+ pos += util_write_string(buf + pos, "Git SHA: ");
+ pos += util_write_string(buf + pos, GIT_COMMIT_SHA);
+ pos += util_write_string(buf + pos, "\r\n");
+ // Local modifications when making the build
+ pos += util_write_string(buf + pos, "Local Mods: ");
+ pos += util_write_uint32(buf + pos, GIT_LOCAL_MODS);
+ pos += util_write_string(buf + pos, "\r\n");
+ // Supported USB endpoints
+ pos += util_write_string(buf + pos, "USB Interfaces: ");
+#ifdef MSC_ENDPOINT
+ pos += util_write_string(buf + pos, "MSD");
+#endif
+#ifdef CDC_ENDPOINT
+ pos += util_write_string(buf + pos, ", CDC");
+#endif
+#ifdef HID_ENDPOINT
+ pos += util_write_string(buf + pos, ", HID");
+#endif
+#if (WEBUSB_INTERFACE)
+ pos += util_write_string(buf + pos, ", WebUSB");
+#endif
+ pos += util_write_string(buf + pos, "\r\n");
+
+ // CRC of the bootloader (if there is one)
+ if (info_get_bootloader_present()) {
+ pos += util_write_string(buf + pos, "Bootloader CRC: 0x");
+ pos += util_write_hex32(buf + pos, info_get_crc_bootloader());
+ pos += util_write_string(buf + pos, "\r\n");
+ }
+
+ // CRC of the interface
+ pos += util_write_string(buf + pos, "Interface CRC: 0x");
+ pos += util_write_hex32(buf + pos, info_get_crc_interface());
+ pos += util_write_string(buf + pos, "\r\n");
+
+ // Number of remounts that have occurred
+ pos += util_write_string(buf + pos, "Remount count: ");
+ pos += util_write_uint32(buf + pos, remount_count);
+ pos += util_write_string(buf + pos, "\r\n");
+
+ //Target URL
+ pos += util_write_string(buf + pos, "URL: @R\r\n");
+
+ return expand_info(data, datasize);
+}
+
+// Fill buf with the contents of the mbed redirect file by
+// expanding the special characters in mbed_redirect_file.
+static uint32_t expand_info(uint8_t *buf, uint32_t bufsize)
+{
+ uint8_t *orig_buf = buf;
+ uint8_t *insert_string;
+
+ do {
+ // Look for key or the end of the string
+ while ((*buf != '@') && (*buf != 0)) {
+ buf++;
+ }
+
+ // If key was found then replace it
+ if ('@' == *buf) {
+ switch (*(buf + 1)) {
+ case 'm':
+ case 'M': // MAC address
+ insert_string = (uint8_t *)info_get_mac();
+ break;
+
+ case 'u':
+ case 'U': // UUID
+ insert_string = (uint8_t *)info_get_unique_id();
+ break;
+
+ case 'b':
+ case 'B': // Board ID
+ insert_string = (uint8_t *)info_get_board_id();
+ break;
+
+ case 'h':
+ case 'H': // Host ID
+ insert_string = (uint8_t *)info_get_host_id();
+ break;
+
+ case 't':
+ case 'T': // Target ID
+ insert_string = (uint8_t *)info_get_target_id();
+ break;
+
+ case 'd':
+ case 'D': // HIC
+ insert_string = (uint8_t *)info_get_hic_id();
+ break;
+
+ case 'v':
+ case 'V': // Firmware version
+ insert_string = (uint8_t *)info_get_version();
+ break;
+
+ case 'r':
+ case 'R': // URL replacement
+ insert_string = (uint8_t *)get_daplink_target_url();
+ break;
+
+ default:
+ insert_string = (uint8_t *)"ERROR";
+ break;
+ }
+
+ // Remove strip_count characters from the start of buf and then insert
+ // insert_string at the new start of buf.
+ uint32_t buf_len = strlen((const char *)buf);
+ uint32_t str_len = strlen((const char *)insert_string);
+ //buffer overflow check on insert
+ if( (buf + str_len + buf_len - 2) < (orig_buf+bufsize)){
+ // push out string
+ memmove(buf + str_len, buf + 2, buf_len - 2);
+ // insert
+ memcpy(buf, insert_string, str_len);
+ }else{
+ //stop the string expansion and leave as it is
+ buf += buf_len;
+ break;
+ }
+
+ }
+ } while (*buf != '\0');
+
+ return (buf - orig_buf);
+}
+
+// Initialize flash algo, erase flash, uninit algo
+static void erase_target(void)
+{
+ flash_intf_target->init();
+ flash_intf_target->erase_chip();
+ flash_intf_target->uninit();
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/drag-n-drop/vfs_user.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/drag-n-drop/vfs_user.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,61 @@
+/**
+ * @file vfs_user.h
+ * @brief VFS user files header.
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2020, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef VFS_USER_H
+#define VFS_USER_H
+
+#include <stdbool.h>
+#include "virtual_fs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//! @brief Hook for file changes in root directory.
+//!
+//! @param filename Name of the file that has changed.
+//! @param change Type of change.
+//! @param file
+//! @param new_file_data Data being written to the file if _change_ is #VFS_FILE_CHANGED.
+//! @retval true The hook handled the change notification, the caller should do nothing else.
+//! @retval false The hook did nothing, continue with normal behaviour.
+bool vfs_user_file_change_handler_hook(const vfs_filename_t filename,
+ vfs_file_change_t change, vfs_file_t file, vfs_file_t new_file_data);
+
+//! @brief Hook for magic files.
+//!
+//! This hook is intended to simplify checking for magic files. In addition to allowing support for
+//! new magic files, you can also change the behaviour of or disable standard magic files.
+//!
+//! @param filename Name of the file that was created.
+//! @param[out] do_remount Whether the caller should remount the MSD volume. Only applies if true
+//! is returned. The default is true, so if the hook does not modify this parameter and returns
+//! true, a remount is performed.
+//! @retval true The hook handled the specified file. A remount will be performed if requested,
+//! but otherwise no other standard behaviour is applied.
+//! @retval false The hook did not handle the file; continue with canonical behaviour.
+bool vfs_user_magic_file_hook(const vfs_filename_t filename, bool *do_remount);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // VFS_USER_H
diff -r 000000000000 -r 01f31e923fe2 source/daplink/drag-n-drop/virtual_fs.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/drag-n-drop/virtual_fs.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,744 @@
+/**
+ * @file virtual_fs.c
+ * @brief Implementation of virtual_fs.h
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+
+#include "virtual_fs.h"
+#include "info.h"
+#include "settings.h"
+#include "compiler.h"
+#include "util.h"
+
+// Virtual file system driver
+// Limitations:
+// - files must be contiguous
+// - data written cannot be read back
+// - data should only be read once
+
+// FAT16 limitations +- safety margin
+#define FAT_CLUSTERS_MAX (65525 - 100)
+#define FAT_CLUSTERS_MIN (4086 + 100)
+
+typedef struct {
+ uint8_t boot_sector[11];
+ /* DOS 2.0 BPB - Bios Parameter Block, 11 bytes */
+ uint16_t bytes_per_sector;
+ uint8_t sectors_per_cluster;
+ uint16_t reserved_logical_sectors;
+ uint8_t num_fats;
+ uint16_t max_root_dir_entries;
+ uint16_t total_logical_sectors;
+ uint8_t media_descriptor;
+ uint16_t logical_sectors_per_fat;
+ /* DOS 3.31 BPB - Bios Parameter Block, 12 bytes */
+ uint16_t physical_sectors_per_track;
+ uint16_t heads;
+ uint32_t hidden_sectors;
+ uint32_t big_sectors_on_drive;
+ /* Extended BIOS Parameter Block, 26 bytes */
+ uint8_t physical_drive_number;
+ uint8_t not_used;
+ uint8_t boot_record_signature;
+ uint32_t volume_id;
+ char volume_label[11];
+ char file_system_type[8];
+ /* bootstrap data in bytes 62-509 */
+ uint8_t bootstrap[448];
+ /* These entries in place of bootstrap code are the *nix partitions */
+ //uint8_t partition_one[16];
+ //uint8_t partition_two[16];
+ //uint8_t partition_three[16];
+ //uint8_t partition_four[16];
+ /* Mandatory value at bytes 510-511, must be 0xaa55 */
+ uint16_t signature;
+} __attribute__((packed)) mbr_t;
+
+typedef struct file_allocation_table {
+ uint8_t f[512];
+} file_allocation_table_t;
+
+typedef struct FatDirectoryEntry {
+ vfs_filename_t filename;
+ uint8_t attributes;
+ uint8_t reserved;
+ uint8_t creation_time_ms;
+ uint16_t creation_time;
+ uint16_t creation_date;
+ uint16_t accessed_date;
+ uint16_t first_cluster_high_16;
+ uint16_t modification_time;
+ uint16_t modification_date;
+ uint16_t first_cluster_low_16;
+ uint32_t filesize;
+} __attribute__((packed)) FatDirectoryEntry_t;
+COMPILER_ASSERT(sizeof(FatDirectoryEntry_t) == 32);
+
+// to save RAM all files must be in the first root dir entry (512 bytes)
+// but 2 actually exist on disc (32 entries) to accomodate hidden OS files,
+// folders and metadata
+typedef struct root_dir {
+ FatDirectoryEntry_t f[32];
+} root_dir_t;
+
+typedef struct virtual_media {
+ vfs_read_cb_t read_cb;
+ vfs_write_cb_t write_cb;
+ uint32_t length;
+} virtual_media_t;
+
+static uint32_t read_zero(uint32_t offset, uint8_t *data, uint32_t size);
+static void write_none(uint32_t offset, const uint8_t *data, uint32_t size);
+
+static uint32_t read_mbr(uint32_t offset, uint8_t *data, uint32_t size);
+static uint32_t read_fat(uint32_t offset, uint8_t *data, uint32_t size);
+static uint32_t read_dir(uint32_t offset, uint8_t *data, uint32_t size);
+static void write_dir(uint32_t offset, const uint8_t *data, uint32_t size);
+static void file_change_cb_stub(const vfs_filename_t filename, vfs_file_change_t change,
+ vfs_file_t file, vfs_file_t new_file_data);
+static uint32_t cluster_to_sector(uint32_t cluster_idx);
+static bool filename_valid(const vfs_filename_t filename);
+static bool filename_character_valid(char character);
+
+// If sector size changes update comment below
+COMPILER_ASSERT(0x0200 == VFS_SECTOR_SIZE);
+// If root directory size changes update max_root_dir_entries
+COMPILER_ASSERT(0x0020 == sizeof(root_dir_t) / sizeof(FatDirectoryEntry_t));
+static const mbr_t mbr_tmpl = {
+ /*uint8_t[11]*/.boot_sector = {
+ 0xEB, 0x3C, 0x90,
+ 'M', 'S', 'D', '0', 'S', '4', '.', '1' // OEM Name in text (8 chars max)
+ },
+ /*uint16_t*/.bytes_per_sector = 0x0200, // 512 bytes per sector
+ /*uint8_t */.sectors_per_cluster = 0x08, // 4k cluser
+ /*uint16_t*/.reserved_logical_sectors = 0x0001, // mbr is 1 sector
+ /*uint8_t */.num_fats = 0x02, // 2 FATs
+ /*uint16_t*/.max_root_dir_entries = 0x0020, // 32 dir entries (max)
+ /*uint16_t*/.total_logical_sectors = 0x1f50, // sector size * # of sectors = drive size
+ /*uint8_t */.media_descriptor = 0xf8, // fixed disc = F8, removable = F0
+ /*uint16_t*/.logical_sectors_per_fat = 0x0001, // FAT is 1k - ToDO:need to edit this
+ /*uint16_t*/.physical_sectors_per_track = 0x0001, // flat
+ /*uint16_t*/.heads = 0x0001, // flat
+ /*uint32_t*/.hidden_sectors = 0x00000000, // before mbt, 0
+ /*uint32_t*/.big_sectors_on_drive = 0x00000000, // 4k sector. not using large clusters
+ /*uint8_t */.physical_drive_number = 0x00,
+ /*uint8_t */.not_used = 0x00, // Current head. Linux tries to set this to 0x1
+ /*uint8_t */.boot_record_signature = 0x29, // signature is present
+ /*uint32_t*/.volume_id = 0x27021974, // serial number
+ // needs to match the root dir label
+ /*char[11]*/.volume_label = {'D', 'A', 'P', 'L', 'I', 'N', 'K', '-', 'D', 'N', 'D'},
+ // unused by msft - just a label (FAT, FAT12, FAT16)
+ /*char[8] */.file_system_type = {'F', 'A', 'T', '1', '6', ' ', ' ', ' '},
+
+ /* BOOTSTRAP SOURCE CODE AND PAYLOAD GENERATOR
+ * PRINTS OUT WARNING MESSAGE ON ACCIDENTAL BOOT FROM DAPLINK
+ 1 [BITS 16]
+ 2 %define BLSTART 0x3E
+ 3 %define BLLEN 448
+ 4
+ 5 00000000 FA cli
+ 6 00000001 B8C007 mov ax, 07C0h
+ 7 00000004 052001 add ax, 288
+ 8 00000007 8ED0 mov ss, ax
+ 9 00000009 BC0010 mov sp, 4096
+ 10 0000000C B8C007 mov ax, 07C0h
+ 11 0000000F 8ED8 mov ds, ax
+ 12 00000011 BE[6D00] mov si,message+BLSTART
+ 13 00000014 E80B00 call print
+ 14 00000017 EBFE jmp $
+ 15
+ 16 printc:
+ 17 00000019 B40E mov ah, 0x0E
+ 18 0000001B B700 mov bh, 0x00
+ 19 0000001D B307 mov bl, 0x07
+ 20 0000001F CD10 int 0x10
+ 21 00000021 C3 ret
+ 22
+ 23 print:
+ 24 nextc:
+ 25 00000022 8A04 mov al, [si]
+ 26 00000024 46 inc si
+ 27 00000025 08C0 or al, al
+ 28 00000027 7405 jz return
+ 29 00000029 E8EDFF call printc
+ 30 0000002C EBF4 jmp nextc
+ 31 return:
+ 32 0000002E C3 ret
+ 33
+ 34 0000002F 504C45415345205245- message db 'PLEASE REMOVE THE ARM MBED DAPLINK USB DEVICE AND REBOOT THE SYSTEM..', 0
+ 35 00000038 4D4F56452054484520-
+ 36 00000041 41524D204D42454420-
+ 37 0000004A 4441504C494E4B2055-
+ 38 00000053 534220444556494345-
+ 39 0000005C 20414E44205245424F-
+ 40 00000065 4F5420544845205359-
+ 41 0000006E 5354454D2E2E00
+ 42
+ 43 00000075 00<rept> times BLLEN-($-$$) db 0
+
+ USE BELOW SCRIPT TO COMPILE BOOTSTRAP AND GENERATE PAYLOAD:
+ #!/usr/bin/env python
+ import os
+ os.system('nasm -f bin -o print.bin -l print.lst print.asm')
+ print(open('print.lst','r').read())
+ x=1
+ for c in open('print.bin','rb').read():
+ print('0x%02X, '%c, end='' if x % 16 else '\n')
+ x += 1
+ */
+ /*uint8_t[448]*/.bootstrap = {
+ 0xFA, 0xB8, 0xC0, 0x07, 0x05, 0x20, 0x01, 0x8E, 0xD0, 0xBC, 0x00, 0x10, 0xB8, 0xC0, 0x07, 0x8E,
+ 0xD8, 0xBE, 0x6D, 0x00, 0xE8, 0x0B, 0x00, 0xEB, 0xFE, 0xB4, 0x0E, 0xB7, 0x00, 0xB3, 0x07, 0xCD,
+ 0x10, 0xC3, 0x8A, 0x04, 0x46, 0x08, 0xC0, 0x74, 0x05, 0xE8, 0xED, 0xFF, 0xEB, 0xF4, 0xC3, 0x50,
+ 0x4C, 0x45, 0x41, 0x53, 0x45, 0x20, 0x52, 0x45, 0x4D, 0x4F, 0x56, 0x45, 0x20, 0x54, 0x48, 0x45,
+ 0x20, 0x41, 0x52, 0x4D, 0x20, 0x4D, 0x42, 0x45, 0x44, 0x20, 0x44, 0x41, 0x50, 0x4C, 0x49, 0x4E,
+ 0x4B, 0x20, 0x55, 0x53, 0x42, 0x20, 0x44, 0x45, 0x56, 0x49, 0x43, 0x45, 0x20, 0x41, 0x4E, 0x44,
+ 0x20, 0x52, 0x45, 0x42, 0x4F, 0x4F, 0x54, 0x20, 0x54, 0x48, 0x45, 0x20, 0x53, 0x59, 0x53, 0x54,
+ 0x45, 0x4D, 0x2E, 0x2E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ },
+ // Signature MUST be 0xAA55 to maintain compatibility (i.e. with Android).
+ /*uint16_t*/.signature = 0xAA55,
+};
+
+enum virtual_media_idx_t {
+ MEDIA_IDX_MBR = 0,
+ MEDIA_IDX_FAT1,
+ MEDIA_IDX_FAT2,
+ MEDIA_IDX_ROOT_DIR,
+
+ MEDIA_IDX_COUNT
+};
+
+// Note - everything in virtual media must be a multiple of VFS_SECTOR_SIZE
+const virtual_media_t virtual_media_tmpl[] = {
+ /* Read CB Write CB Region Size Region Name */
+ { read_mbr, write_none, VFS_SECTOR_SIZE }, /* MBR */
+ { read_fat, write_none, 0 /* Set at runtime */ }, /* FAT1 */
+ { read_fat, write_none, 0 /* Set at runtime */ }, /* FAT2 */
+ { read_dir, write_dir, VFS_SECTOR_SIZE * 2 }, /* Root Dir */
+ /* Raw filesystem contents follow */
+};
+// Keep virtual_media_idx_t in sync with virtual_media_tmpl
+COMPILER_ASSERT(MEDIA_IDX_COUNT == ARRAY_SIZE(virtual_media_tmpl));
+
+static const FatDirectoryEntry_t root_dir_entry = {
+ /*uint8_t[11] */ .filename = {""},
+ /*uint8_t */ .attributes = VFS_FILE_ATTR_VOLUME_LABEL | VFS_FILE_ATTR_ARCHIVE,
+ /*uint8_t */ .reserved = 0x00,
+ /*uint8_t */ .creation_time_ms = 0x00,
+ /*uint16_t*/ .creation_time = 0x0000,
+ /*uint16_t*/ .creation_date = 0x0000,
+ /*uint16_t*/ .accessed_date = 0x0000,
+ /*uint16_t*/ .first_cluster_high_16 = 0x0000,
+ /*uint16_t*/ .modification_time = 0x8E41,
+ /*uint16_t*/ .modification_date = 0x32bb,
+ /*uint16_t*/ .first_cluster_low_16 = 0x0000,
+ /*uint32_t*/ .filesize = 0x00000000
+};
+
+static const FatDirectoryEntry_t dir_entry_tmpl = {
+ /*uint8_t[11] */ .filename = {""},
+ /*uint8_t */ .attributes = VFS_FILE_ATTR_READ_ONLY,
+ /*uint8_t */ .reserved = 0x00,
+ /*uint8_t */ .creation_time_ms = 0x00,
+ /*uint16_t*/ .creation_time = 0x0000,
+ /*uint16_t*/ .creation_date = 0x4876,
+ /*uint16_t*/ .accessed_date = 0x4876,
+ /*uint16_t*/ .first_cluster_high_16 = 0x0000,
+ /*uint16_t*/ .modification_time = 0x83dc,
+ /*uint16_t*/ .modification_date = 0x4876,
+ /*uint16_t*/ .first_cluster_low_16 = 0x0000,
+ /*uint32_t*/ .filesize = 0x00000000
+};
+
+mbr_t mbr;
+file_allocation_table_t fat;
+virtual_media_t virtual_media[16];
+root_dir_t dir_current;
+uint8_t file_count;
+vfs_file_change_cb_t file_change_cb;
+uint32_t virtual_media_idx;
+uint32_t fat_idx;
+uint32_t dir_idx;
+uint32_t data_start;
+
+// Virtual media must be larger than the template
+COMPILER_ASSERT(sizeof(virtual_media) > sizeof(virtual_media_tmpl));
+
+static void write_fat(file_allocation_table_t *fat, uint32_t idx, uint16_t val)
+{
+ uint32_t low_idx;
+ uint32_t high_idx;
+ low_idx = idx * 2 + 0;
+ high_idx = idx * 2 + 1;
+
+ // Assert that this is still within the fat table
+ if (high_idx >= ARRAY_SIZE(fat->f)) {
+ util_assert(0);
+ return;
+ }
+
+ fat->f[low_idx] = (val >> 0) & 0xFF;
+ fat->f[high_idx] = (val >> 8) & 0xFF;
+}
+
+void vfs_init(const vfs_filename_t drive_name, uint32_t disk_size)
+{
+ uint32_t i;
+ uint32_t num_clusters;
+ uint32_t total_sectors;
+ // Clear everything
+ memset(&mbr, 0, sizeof(mbr));
+ memset(&fat, 0, sizeof(fat));
+ fat_idx = 0;
+ memset(&virtual_media, 0, sizeof(virtual_media));
+ memset(&dir_current, 0, sizeof(dir_current));
+ dir_idx = 0;
+ file_count = 0;
+ file_change_cb = file_change_cb_stub;
+ virtual_media_idx = 0;
+ data_start = 0;
+ // Initialize MBR
+ memcpy(&mbr, &mbr_tmpl, sizeof(mbr_t));
+ total_sectors = ((disk_size + KB(64)) / mbr.bytes_per_sector);
+ // Make sure this is the right size for a FAT16 volume
+ if (total_sectors < FAT_CLUSTERS_MIN * mbr.sectors_per_cluster) {
+ util_assert(0);
+ total_sectors = FAT_CLUSTERS_MIN * mbr.sectors_per_cluster;
+ } else if (total_sectors > FAT_CLUSTERS_MAX * mbr.sectors_per_cluster) {
+ util_assert(0);
+ total_sectors = FAT_CLUSTERS_MAX * mbr.sectors_per_cluster;
+ }
+ if (total_sectors >= 0x10000) {
+ mbr.total_logical_sectors = 0;
+ mbr.big_sectors_on_drive = total_sectors;
+ } else {
+ mbr.total_logical_sectors = total_sectors;
+ mbr.big_sectors_on_drive = 0;
+ }
+ // FAT table will likely be larger than needed, but this is allowed by the
+ // fat specification
+ num_clusters = total_sectors / mbr.sectors_per_cluster;
+ mbr.logical_sectors_per_fat = (num_clusters * 2 + VFS_SECTOR_SIZE - 1) / VFS_SECTOR_SIZE;
+ // Initailize virtual media
+ memcpy(&virtual_media, &virtual_media_tmpl, sizeof(virtual_media_tmpl));
+ virtual_media[MEDIA_IDX_FAT1].length = VFS_SECTOR_SIZE * mbr.logical_sectors_per_fat;
+ virtual_media[MEDIA_IDX_FAT2].length = VFS_SECTOR_SIZE * mbr.logical_sectors_per_fat;
+ // Initialize indexes
+ virtual_media_idx = MEDIA_IDX_COUNT;
+ data_start = 0;
+
+ for (i = 0; i < ARRAY_SIZE(virtual_media_tmpl); i++) {
+ data_start += virtual_media[i].length;
+ }
+
+ // Initialize FAT
+ fat_idx = 0;
+ write_fat(&fat, fat_idx, 0xFFF8); // Media type "media_descriptor"
+ fat_idx++;
+ write_fat(&fat, fat_idx, 0xFFFF); // FAT12 - always 0xFFF (no meaning), FAT16 - dirty/clean (clean = 0xFFFF)
+ fat_idx++;
+ // Initialize root dir
+ dir_idx = 0;
+ dir_current.f[dir_idx] = root_dir_entry;
+ memcpy(dir_current.f[dir_idx].filename, drive_name, sizeof(dir_current.f[0].filename));
+ dir_idx++;
+}
+
+uint32_t vfs_get_total_size()
+{
+ uint32_t size;
+ if (mbr.total_logical_sectors > 0) {
+ size = mbr.total_logical_sectors * mbr.bytes_per_sector;
+ } else if (mbr.big_sectors_on_drive > 0) {
+ size = mbr.big_sectors_on_drive * mbr.bytes_per_sector;
+ } else {
+ size = 0;
+ util_assert(0);
+ }
+ return size;
+}
+
+vfs_file_t vfs_create_file(const vfs_filename_t filename, vfs_read_cb_t read_cb, vfs_write_cb_t write_cb, uint32_t len)
+{
+ uint32_t first_cluster;
+ FatDirectoryEntry_t *de;
+ uint32_t clusters;
+ uint32_t cluster_size;
+ uint32_t i;
+ util_assert(filename_valid(filename));
+ // Compute the number of clusters in the file
+ cluster_size = mbr.bytes_per_sector * mbr.sectors_per_cluster;
+ clusters = (len + cluster_size - 1) / cluster_size;
+ // Write the cluster chain to the fat table
+ first_cluster = 0;
+
+ if (len > 0) {
+ first_cluster = fat_idx;
+
+ for (i = 0; i < clusters - 1; i++) {
+ write_fat(&fat, fat_idx, fat_idx + 1);
+ fat_idx++;
+ }
+
+ write_fat(&fat, fat_idx, 0xFFFF);
+ fat_idx++;
+ }
+
+ // Update directory entry
+ if (dir_idx >= ARRAY_SIZE(dir_current.f)) {
+ util_assert(0);
+ return VFS_FILE_INVALID;
+ }
+
+ de = &dir_current.f[dir_idx];
+ dir_idx++;
+ memcpy(de, &dir_entry_tmpl, sizeof(dir_entry_tmpl));
+ memcpy(de->filename, filename, 11);
+ de->filesize = len;
+ de->first_cluster_high_16 = (first_cluster >> 16) & 0xFFFF;
+ de->first_cluster_low_16 = (first_cluster >> 0) & 0xFFFF;
+
+ // Update virtual media
+ if (virtual_media_idx >= ARRAY_SIZE(virtual_media)) {
+ util_assert(0);
+ return VFS_FILE_INVALID;
+ }
+
+ virtual_media[virtual_media_idx].read_cb = read_zero;
+ virtual_media[virtual_media_idx].write_cb = write_none;
+
+ if (0 != read_cb) {
+ virtual_media[virtual_media_idx].read_cb = read_cb;
+ }
+
+ if (0 != write_cb) {
+ virtual_media[virtual_media_idx].write_cb = write_cb;
+ }
+
+ virtual_media[virtual_media_idx].length = clusters * mbr.bytes_per_sector * mbr.sectors_per_cluster;
+ virtual_media_idx++;
+ file_count += 1;
+ return de;
+}
+
+void vfs_file_set_attr(vfs_file_t file, vfs_file_attr_bit_t attr)
+{
+ FatDirectoryEntry_t *de = file;
+ de->attributes = attr;
+}
+
+vfs_sector_t vfs_file_get_start_sector(vfs_file_t file)
+{
+ FatDirectoryEntry_t *de = file;
+
+ if (vfs_file_get_size(file) == 0) {
+ return VFS_INVALID_SECTOR;
+ }
+
+ return cluster_to_sector(de->first_cluster_low_16);
+}
+
+uint32_t vfs_file_get_size(vfs_file_t file)
+{
+ FatDirectoryEntry_t *de = file;
+ return de->filesize;
+}
+
+vfs_file_attr_bit_t vfs_file_get_attr(vfs_file_t file)
+{
+ FatDirectoryEntry_t *de = file;
+ return (vfs_file_attr_bit_t)de->attributes;
+}
+
+void vfs_set_file_change_callback(vfs_file_change_cb_t cb)
+{
+ file_change_cb = cb;
+}
+
+void vfs_read(uint32_t requested_sector, uint8_t *buf, uint32_t num_sectors)
+{
+ uint8_t i = 0;
+ uint32_t current_sector;
+ // Zero out the buffer
+ memset(buf, 0, num_sectors * VFS_SECTOR_SIZE);
+ current_sector = 0;
+
+ for (i = 0; i < ARRAY_SIZE(virtual_media); i++) {
+ uint32_t vm_sectors = virtual_media[i].length / VFS_SECTOR_SIZE;
+ uint32_t vm_start = current_sector;
+ uint32_t vm_end = current_sector + vm_sectors;
+
+ // Data can be used in this sector
+ if ((requested_sector >= vm_start) && (requested_sector < vm_end)) {
+ uint32_t sector_offset;
+ uint32_t sectors_to_write = vm_end - requested_sector;
+ sectors_to_write = MIN(sectors_to_write, num_sectors);
+ sector_offset = requested_sector - current_sector;
+ virtual_media[i].read_cb(sector_offset, buf, sectors_to_write);
+ // Update requested sector
+ requested_sector += sectors_to_write;
+ num_sectors -= sectors_to_write;
+ }
+
+ // If there is no more data to be read then break
+ if (num_sectors == 0) {
+ break;
+ }
+
+ // Move to the next virtual media entry
+ current_sector += vm_sectors;
+ }
+}
+
+void vfs_write(uint32_t requested_sector, const uint8_t *buf, uint32_t num_sectors)
+{
+ uint8_t i = 0;
+ uint32_t current_sector;
+ current_sector = 0;
+
+ for (i = 0; i < virtual_media_idx; i++) {
+ uint32_t vm_sectors = virtual_media[i].length / VFS_SECTOR_SIZE;
+ uint32_t vm_start = current_sector;
+ uint32_t vm_end = current_sector + vm_sectors;
+
+ // Data can be used in this sector
+ if ((requested_sector >= vm_start) && (requested_sector < vm_end)) {
+ uint32_t sector_offset;
+ uint32_t sectors_to_read = vm_end - requested_sector;
+ sectors_to_read = MIN(sectors_to_read, num_sectors);
+ sector_offset = requested_sector - current_sector;
+ virtual_media[i].write_cb(sector_offset, buf, sectors_to_read);
+ // Update requested sector
+ requested_sector += sectors_to_read;
+ num_sectors -= sectors_to_read;
+ }
+
+ // If there is no more data to be read then break
+ if (num_sectors == 0) {
+ break;
+ }
+
+ // Move to the next virtual media entry
+ current_sector += vm_sectors;
+ }
+}
+
+static uint32_t read_zero(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors)
+{
+ uint32_t read_size = VFS_SECTOR_SIZE * num_sectors;
+ memset(data, 0, read_size);
+ return read_size;
+}
+
+static void write_none(uint32_t sector_offset, const uint8_t *data, uint32_t num_sectors)
+{
+ // Do nothing
+}
+
+static uint32_t read_mbr(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors)
+{
+ uint32_t read_size = sizeof(mbr_t);
+ COMPILER_ASSERT(sizeof(mbr_t) <= VFS_SECTOR_SIZE);
+
+ if (sector_offset != 0) {
+ // Don't worry about reading other sectors
+ return 0;
+ }
+
+ memcpy(data, &mbr, read_size);
+ return read_size;
+}
+
+/* No need to handle writes to the mbr */
+
+static uint32_t read_fat(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors)
+{
+ uint32_t read_size = sizeof(file_allocation_table_t);
+ COMPILER_ASSERT(sizeof(file_allocation_table_t) <= VFS_SECTOR_SIZE);
+
+ if (sector_offset != 0) {
+ // Don't worry about reading other sectors
+ return 0;
+ }
+
+ memcpy(data, &fat, read_size);
+ return read_size;
+}
+
+/* No need to handle writes to the fat */
+
+static uint32_t read_dir(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors)
+{
+ if ((sector_offset + num_sectors) * VFS_SECTOR_SIZE > sizeof(dir_current)) {
+ // Trying to read too much of the root directory
+ util_assert(0);
+ return 0;
+ }
+
+ // Zero buffer data is VFS_SECTOR_SIZE max
+ memset(data, 0, VFS_SECTOR_SIZE);
+
+ if (sector_offset == 0) { //Handle the first 512 bytes
+ // Copy data that is actually created in the directory
+ memcpy(data, &dir_current.f[0], dir_idx*sizeof(FatDirectoryEntry_t));
+ }
+
+ return num_sectors * VFS_SECTOR_SIZE;
+}
+
+static void write_dir(uint32_t sector_offset, const uint8_t *data, uint32_t num_sectors)
+{
+ FatDirectoryEntry_t *old_entry;
+ FatDirectoryEntry_t *new_entry;
+ uint32_t start_index;
+ uint32_t num_entries;
+ uint32_t i;
+
+ if ((sector_offset + num_sectors) * VFS_SECTOR_SIZE > sizeof(dir_current)) {
+ // Trying to write too much of the root directory
+ util_assert(0);
+ return;
+ }
+
+ start_index = sector_offset * VFS_SECTOR_SIZE / sizeof(FatDirectoryEntry_t);
+ num_entries = num_sectors * VFS_SECTOR_SIZE / sizeof(FatDirectoryEntry_t);
+ old_entry = &dir_current.f[start_index];
+ new_entry = (FatDirectoryEntry_t *)data;
+ // If this is the first sector start at index 1 to get past drive name
+ i = 0 == sector_offset ? 1 : 0;
+
+ for (; i < num_entries; i++) {
+ bool same_name;
+
+ if (0 == memcmp(&old_entry[i], &new_entry[i], sizeof(FatDirectoryEntry_t))) {
+ continue;
+ }
+
+ // If were at this point then something has changed in the file
+ same_name = (0 == memcmp(old_entry[i].filename, new_entry[i].filename, sizeof(new_entry[i].filename))) ? 1 : 0;
+ // Changed
+ file_change_cb(new_entry[i].filename, VFS_FILE_CHANGED, (vfs_file_t)&old_entry[i], (vfs_file_t)&new_entry[i]);
+
+ // Deleted
+ if (0xe5 == (uint8_t)new_entry[i].filename[0]) {
+ file_change_cb(old_entry[i].filename, VFS_FILE_DELETED, (vfs_file_t)&old_entry[i], (vfs_file_t)&new_entry[i]);
+ continue;
+ }
+
+ // Created
+ if (!same_name && filename_valid(new_entry[i].filename)) {
+ file_change_cb(new_entry[i].filename, VFS_FILE_CREATED, (vfs_file_t)&old_entry[i], (vfs_file_t)&new_entry[i]);
+ continue;
+ }
+ }
+
+ memcpy(&dir_current.f[start_index], data, num_sectors * VFS_SECTOR_SIZE);
+}
+
+static void file_change_cb_stub(const vfs_filename_t filename, vfs_file_change_t change, vfs_file_t file, vfs_file_t new_file_data)
+{
+ // Do nothing
+}
+
+static uint32_t cluster_to_sector(uint32_t cluster_idx)
+{
+ uint32_t sectors_before_data = data_start / mbr.bytes_per_sector;
+ return sectors_before_data + (cluster_idx - 2) * mbr.sectors_per_cluster;
+}
+
+static bool filename_valid(const vfs_filename_t filename)
+{
+ // Information on valid 8.3 filenames can be found in
+ // the microsoft hardware whitepaper:
+ //
+ // Microsoft Extensible Firmware Initiative
+ // FAT32 File System Specification
+ // FAT: General Overview of On-Disk Format
+ const char invalid_starting_chars[] = {
+ 0xE5, // Deleted
+ 0x00, // Deleted (and all following entries are free)
+ 0x20, // Space not allowed as first character
+ };
+ uint32_t i;
+
+ // Check for invalid starting characters
+ for (i = 0; i < sizeof(invalid_starting_chars); i++) {
+ if (invalid_starting_chars[i] == filename[0]) {
+ return false;
+ }
+ }
+
+ // Make sure all the characters are valid
+ for (i = 0; i < sizeof(vfs_filename_t); i++) {
+ if (!filename_character_valid(filename[i])) {
+ return false;
+ }
+ }
+
+ // All checks have passed so filename is valid
+ return true;
+}
+
+static bool filename_character_valid(char character)
+{
+ const char invalid_chars[] = {0x22, 0x2A, 0x2B, 0x2C, 0x2E, 0x2F, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x5B, 0x5C, 0x5D, 0x7C};
+ uint32_t i;
+
+ // Lower case characters are not allowed
+ if ((character >= 'a') && (character <= 'z')) {
+ return false;
+ }
+
+ // Values less than 0x20 are not allowed except 0x5
+ if ((character < 0x20) && (character != 0x5)) {
+ return false;
+ }
+
+ // Check for special characters that are not allowed
+ for (i = 0; i < sizeof(invalid_chars); i++) {
+ if (invalid_chars[i] == character) {
+ return false;
+ }
+ }
+
+ // All of the checks have passed so this is a valid file name character
+ return true;
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/drag-n-drop/virtual_fs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/drag-n-drop/virtual_fs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,108 @@
+/**
+ * @file virtual_fs.h
+ * @brief FAT 12/16 filesystem handling
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef VIRTUAL_FS_H
+#define VIRTUAL_FS_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define VFS_CLUSTER_SIZE 0x1000
+#define VFS_SECTOR_SIZE 512
+#define VFS_INVALID_SECTOR 0xFFFFFFFF
+#define VFS_FILE_INVALID 0
+#define VFS_MAX_FILES 16
+
+typedef char vfs_filename_t[11];
+
+typedef enum {
+ VFS_FILE_ATTR_READ_ONLY = (1 << 0),
+ VFS_FILE_ATTR_HIDDEN = (1 << 1),
+ VFS_FILE_ATTR_SYSTEM = (1 << 2),
+ VFS_FILE_ATTR_VOLUME_LABEL = (1 << 3),
+ VFS_FILE_ATTR_SUB_DIR = (1 << 4),
+ VFS_FILE_ATTR_ARCHIVE = (1 << 5),
+} vfs_file_attr_bit_t;
+
+typedef enum {
+ VFS_FILE_CREATED = 0, /*!< A new file was created */
+ VFS_FILE_DELETED, /*!< An existing file was deleted */
+ VFS_FILE_CHANGED, /*!< Some attribute of the file changed.
+ Note: when a file is deleted or
+ created a file changed
+ notification will also occur*/
+} vfs_file_change_t;
+
+typedef void *vfs_file_t;
+typedef uint32_t vfs_sector_t;
+
+// Callback for when data is written to a file on the virtual filesystem
+typedef void (*vfs_write_cb_t)(uint32_t sector_offset, const uint8_t *data, uint32_t num_sectors);
+// Callback for when data is ready from the virtual filesystem
+typedef uint32_t (*vfs_read_cb_t)(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors);
+// Callback for when a file's attributes are changed on the virtual filesystem. Note that the 'file' parameter
+// can be saved and compared to other files to see if they are referencing the same object. The
+// same cannot be done with new_file_data since it points to a temporary buffer.
+typedef void (*vfs_file_change_cb_t)(const vfs_filename_t filename, vfs_file_change_t change,
+ vfs_file_t file, vfs_file_t new_file_data);
+
+// Initialize the filesystem with the given size and name
+void vfs_init(const vfs_filename_t drive_name, uint32_t disk_size);
+
+// Get the total size of the virtual filesystem
+uint32_t vfs_get_total_size(void);
+
+// Add a file to the virtual FS and return a handle to this file.
+// This must be called before vfs_read or vfs_write are called.
+// Adding a new file after vfs_read or vfs_write have been called results in undefined behavior.
+vfs_file_t vfs_create_file(const vfs_filename_t filename, vfs_read_cb_t read_cb, vfs_write_cb_t write_cb, uint32_t len);
+
+// Set the attributes of a file
+void vfs_file_set_attr(vfs_file_t file, vfs_file_attr_bit_t attr);
+
+// Get the starting sector of this file.
+// NOTE - If the file size is 0 there is no starting
+// sector so VFS_INVALID_SECTOR will be returned.
+vfs_sector_t vfs_file_get_start_sector(vfs_file_t file);
+
+// Get the size of the file.
+uint32_t vfs_file_get_size(vfs_file_t file);
+
+// Get the attributes of a file
+vfs_file_attr_bit_t vfs_file_get_attr(vfs_file_t file);
+
+// Set the callback when a file is created, deleted or has atributes changed.
+void vfs_set_file_change_callback(vfs_file_change_cb_t cb);
+
+// Read one or more sectors from the virtual filesystem
+void vfs_read(uint32_t sector, uint8_t *buf, uint32_t num_of_sectors);
+
+// Write one or more sectors to the virtual filesystem
+void vfs_write(uint32_t sector, const uint8_t *buf, uint32_t num_of_sectors);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/error.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/error.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,252 @@
+/**
+ * @file error.c
+ * @brief Implementation of error.h
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "error.h"
+#include "util.h"
+#include "compiler.h"
+
+static const char *const error_message[] = {
+
+ /* Shared errors */
+
+ // ERROR_SUCCESS
+ "Operation was successful",
+ // ERROR_FAILURE
+ "An error has occurred",
+ // ERROR_INTERNAL
+ "An internal error has occurred",
+
+ /* VFS user errors */
+
+ // ERROR_ERROR_DURING_TRANSFER
+ "An error occurred during the transfer",
+ // ERROR_TRANSFER_TIMEOUT
+ "The transfer timed out.",
+ // ERROR_FILE_BOUNDS
+ "Possible mismatch between file size and size programmed",
+ // ERROR_OOO_SECTOR
+ "File sent out of order by PC. Target might not be programmed correctly.",
+
+ /* Target flash errors */
+
+ // ERROR_RESET
+ "The interface firmware FAILED to reset/halt the target MCU",
+ // ERROR_ALGO_DL
+ "The interface firmware FAILED to download the flash programming algorithms to the target MCU",
+ //ERROR_ALGO_MISSING
+ "The flash algo missing for a region",
+ // ERROR_ALGO_DATA_SEQ
+ "The interface firmware FAILED to download the flash data contents to be programmed",
+ // ERROR_INIT
+ "The interface firmware FAILED to initialize the target MCU",
+ // ERROR_UNINIT
+ "The interface firmware FAILED to uninitialize the target MCU",
+ // ERROR_SECURITY_BITS
+ "The interface firmware ABORTED programming. Image is trying to set security bits",
+ // ERROR_UNLOCK
+ "The interface firmware FAILED to unlock the target for programming",
+ // ERROR_ERASE_SECTOR
+ "Flash algorithm erase sector command FAILURE",
+ // ERROR_ERASE_ALL
+ "Flash algorithm erase all command FAILURE",
+ // ERROR_WRITE
+ "Flash algorithm write command FAILURE",
+ // ERROR_WRITE_VERIFY
+ "Flash algorithm write verify command FAILURE",
+
+ /* File stream errors */
+
+ // ERROR_SUCCESS_DONE
+ "End of stream has been reached",
+ // ERROR_SUCCESS_DONE_OR_CONTINUE
+ "End of stream is unknown",
+ // ERROR_HEX_CKSUM
+ "The hex file cannot be decoded. Checksum calculation failure occurred.",
+ // ERROR_HEX_PARSER
+ "The hex file cannot be decoded. Parser logic failure occurred.",
+ // ERROR_HEX_PROGRAM
+ "The hex file cannot be programmed. Logic failure occurred.",
+ // ERROR_HEX_INVALID_ADDRESS
+ "The hex file you dropped isn't compatible with this mode or device. Are you in MAINTENANCE mode? See HELP FAQ.HTM",
+ // ERROR_HEX_INVALID_APP_OFFSET
+ "The hex file offset load address is not correct.",
+
+ /* Flash decoder errors */
+
+ // ERROR_FD_BL_UPDT_ADDR_WRONG
+ "The starting address for the bootloader update is wrong.",
+ // ERROR_FD_INTF_UPDT_ADDR_WRONG
+ "The starting address for the interface update is wrong.",
+ // ERROR_FD_UNSUPPORTED_UPDATE
+ "The application file format is unknown and cannot be parsed and/or processed.",
+
+ /* Flash IAP interface */
+
+ // ERROR_IAP_INIT
+ "In application programming initialization failed.",
+ // ERROR_IAP_UNINIT
+ "In application programming uninit failed.",
+ // ERROR_IAP_WRITE
+ "In application programming write failed.",
+ // ERROR_IAP_ERASE_SECTOR
+ "In application programming sector erase failed.",
+ // ERROR_IAP_ERASE_ALL
+ "In application programming mass erase failed.",
+ // ERROR_IAP_OUT_OF_BOUNDS
+ "In application programming aborted due to an out of bounds address.",
+ // ERROR_IAP_UPDT_NOT_SUPPORTED
+ "In application programming not supported on this device.",
+ // ERROR_IAP_UPDT_INCOMPLETE
+ "In application programming failed because the update sent was incomplete.",
+ // ERROR_IAP_NO_INTERCEPT
+ "",
+ // ERROR_BL_UPDT_BAD_CRC
+ "The bootloader CRC did not pass.",
+
+};
+
+static error_type_t error_type[] = {
+
+ /* These should always stay the same for each error type. */
+
+ // ERROR_SUCCESS
+ 0,
+ // ERROR_FAILURE
+ ERROR_TYPE_INTERNAL,
+ // ERROR_INTERNAL
+ ERROR_TYPE_INTERNAL,
+
+ /* VFS user errors */
+
+ // ERROR_ERROR_DURING_TRANSFER
+ ERROR_TYPE_TRANSIENT,
+ // ERROR_TRANSFER_TIMEOUT
+ ERROR_TYPE_USER | ERROR_TYPE_TRANSIENT,
+ // ERROR_FILE_BOUNDS
+ ERROR_TYPE_TRANSIENT,
+ // ERROR_OOO_SECTOR
+ ERROR_TYPE_TRANSIENT,
+
+ /* Target flash errors */
+
+ // ERROR_RESET
+ ERROR_TYPE_TARGET,
+ // ERROR_ALGO_DL
+ ERROR_TYPE_TARGET,
+ //ERROR_ALGO_MISSING
+ ERROR_TYPE_TARGET,
+ // ERROR_ALGO_DATA_SEQ
+ ERROR_TYPE_TARGET,
+ // ERROR_INIT
+ ERROR_TYPE_TARGET,
+ // ERROR_UNINIT
+ ERROR_TYPE_TARGET,
+ // ERROR_SECURITY_BITS
+ ERROR_TYPE_USER,
+ // ERROR_UNLOCK
+ ERROR_TYPE_TARGET,
+ // ERROR_ERASE_SECTOR
+ ERROR_TYPE_TARGET,
+ // ERROR_ERASE_ALL
+ ERROR_TYPE_TARGET,
+ // ERROR_WRITE
+ ERROR_TYPE_TARGET,
+ // ERROR_WRITE_VERIFY
+ ERROR_TYPE_TARGET,
+
+ /* File stream errors */
+
+ // ERROR_SUCCESS_DONE
+ ERROR_TYPE_INTERNAL,
+ // ERROR_SUCCESS_DONE_OR_CONTINUE
+ ERROR_TYPE_INTERNAL,
+ // ERROR_HEX_CKSUM
+ ERROR_TYPE_USER | ERROR_TYPE_TRANSIENT,
+ // ERROR_HEX_PARSER
+ ERROR_TYPE_USER | ERROR_TYPE_TRANSIENT,
+ // ERROR_HEX_PROGRAM
+ ERROR_TYPE_USER | ERROR_TYPE_TRANSIENT,
+ // ERROR_HEX_INVALID_ADDRESS
+ ERROR_TYPE_USER,
+ // ERROR_HEX_INVALID_APP_OFFSET
+ ERROR_TYPE_USER,
+
+ /* Flash decoder errors */
+
+ // ERROR_FD_BL_UPDT_ADDR_WRONG
+ ERROR_TYPE_USER,
+ // ERROR_FD_INTF_UPDT_ADDR_WRONG
+ ERROR_TYPE_USER,
+ // ERROR_FD_UNSUPPORTED_UPDATE
+ ERROR_TYPE_USER,
+
+ /* Flash IAP interface */
+
+ // ERROR_IAP_INIT
+ ERROR_TYPE_INTERFACE,
+ // ERROR_IAP_UNINIT
+ ERROR_TYPE_INTERFACE,
+ // ERROR_IAP_WRITE
+ ERROR_TYPE_INTERFACE,
+ // ERROR_IAP_ERASE_SECTOR
+ ERROR_TYPE_INTERFACE,
+ // ERROR_IAP_ERASE_ALL
+ ERROR_TYPE_INTERFACE,
+ // ERROR_IAP_OUT_OF_BOUNDS
+ ERROR_TYPE_INTERFACE,
+ // ERROR_IAP_UPDT_NOT_SUPPORTED
+ ERROR_TYPE_INTERFACE,
+ // ERROR_IAP_UPDT_INCOMPLETE
+ ERROR_TYPE_INTERFACE,
+ // ERROR_IAP_NO_INTERCEPT
+ ERROR_TYPE_INTERFACE,
+ // ERROR_BL_UPDT_BAD_CRC
+ ERROR_TYPE_INTERFACE,
+};
+
+COMPILER_ASSERT(ERROR_COUNT == ARRAY_SIZE(error_message));
+
+const char *error_get_string(error_t error)
+{
+ const char *msg = 0;
+
+ if (error < ERROR_COUNT) {
+ msg = error_message[error];
+ }
+
+ if (0 == msg) {
+ util_assert(0);
+ msg = "";
+ }
+
+ return msg;
+}
+
+error_type_t error_get_type(error_t error)
+{
+ error_type_t type = ERROR_TYPE_INTERNAL;
+
+ if (error < ERROR_COUNT) {
+ type = error_type[error];
+ }
+
+ return type;
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/error.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/error.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,108 @@
+/**
+ * @file error.h
+ * @brief collection of known errors and accessor for the friendly string
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ERROR_H
+#define ERROR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Keep in sync with the lists error_message and error_type
+typedef enum {
+ /* Shared errors */
+ ERROR_SUCCESS = 0,
+ ERROR_FAILURE,
+ ERROR_INTERNAL,
+
+ /* VFS user errors */
+ ERROR_ERROR_DURING_TRANSFER,
+ ERROR_TRANSFER_TIMEOUT,
+ ERROR_FILE_BOUNDS,
+ ERROR_OOO_SECTOR,
+
+ /* Target flash errors */
+ ERROR_RESET,
+ ERROR_ALGO_DL,
+ ERROR_ALGO_MISSING,
+ ERROR_ALGO_DATA_SEQ,
+ ERROR_INIT,
+ ERROR_UNINIT,
+ ERROR_SECURITY_BITS,
+ ERROR_UNLOCK,
+ ERROR_ERASE_SECTOR,
+ ERROR_ERASE_ALL,
+ ERROR_WRITE,
+ ERROR_WRITE_VERIFY,
+
+ /* File stream errors */
+ ERROR_SUCCESS_DONE,
+ ERROR_SUCCESS_DONE_OR_CONTINUE,
+ ERROR_HEX_CKSUM,
+ ERROR_HEX_PARSER,
+ ERROR_HEX_PROGRAM,
+ ERROR_HEX_INVALID_ADDRESS,
+ ERROR_HEX_INVALID_APP_OFFSET,
+
+ /* Flash decoder error */
+ ERROR_FD_BL_UPDT_ADDR_WRONG,
+ ERROR_FD_INTF_UPDT_ADDR_WRONG,
+ ERROR_FD_UNSUPPORTED_UPDATE,
+
+ /* Flash IAP interface */
+ ERROR_IAP_INIT,
+ ERROR_IAP_UNINIT,
+ ERROR_IAP_WRITE,
+ ERROR_IAP_ERASE_SECTOR,
+ ERROR_IAP_ERASE_ALL,
+ ERROR_IAP_OUT_OF_BOUNDS,
+ ERROR_IAP_UPDT_NOT_SUPPORTED,
+ ERROR_IAP_UPDT_INCOMPLETE,
+ ERROR_IAP_NO_INTERCEPT,
+ ERROR_BL_UPDT_BAD_CRC,
+
+ // Add new values here
+
+ ERROR_COUNT
+} error_t;
+
+const char *error_get_string(error_t error);
+
+typedef unsigned char error_type_t;
+
+#define ERROR_TYPE_INTERNAL 0x1
+#define ERROR_TYPE_TRANSIENT 0x2
+#define ERROR_TYPE_USER 0x4
+#define ERROR_TYPE_TARGET 0x8
+#define ERROR_TYPE_INTERFACE 0x10
+// If you add another error type:
+// 1. update error_type_names, used by read_file_fail_txt()
+// 2. update ERROR_TYPE_MASK
+// 3. make sure that error type bits still fit inside of error_type_t
+#define ERROR_TYPE_MASK 0x1F
+
+error_type_t error_get_type(error_t error);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/flash_hal.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/flash_hal.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,43 @@
+/**
+ * @file flash_hal.c
+ * @brief Implementation of flash_hal.h
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_hal.h"
+#include "cortex_m.h"
+
+uint32_t flash_erase_sector(uint32_t addr)
+{
+ cortex_int_state_t state;
+ int retval = -1;
+ state = cortex_int_get_and_disable();
+ retval = EraseSector(addr);
+ cortex_int_restore(state);
+ return retval;
+}
+
+uint32_t flash_program_page(uint32_t adr, uint32_t sz, uint8_t *buf)
+{
+ int retval = -1;
+ cortex_int_state_t state;
+ state = cortex_int_get_and_disable();
+ retval = ProgramPage(adr, sz, (uint32_t *)buf);
+ cortex_int_restore(state);
+ return retval;
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/info.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/info.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,346 @@
+/**
+ * @file info.c
+ * @brief Implementation of info.h
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+#include "main.h"
+#include "info.h"
+#include "target_config.h"
+#include "read_uid.h"
+#include "util.h"
+#include "crc.h"
+#include "daplink.h"
+#include "settings.h"
+#include "target_board.h"
+
+static char hex_to_ascii(uint8_t x)
+{
+ return ('0' + (x>9 ? x+0x27 : x));
+}
+
+// Constant variables
+static const daplink_info_t *const info_bl = (daplink_info_t *)(DAPLINK_ROM_BL_START + DAPLINK_INFO_OFFSET);
+static const daplink_info_t *const info_if = (daplink_info_t *)(DAPLINK_ROM_IF_START + DAPLINK_INFO_OFFSET);
+
+// Raw variables
+static uint32_t host_id[4];
+static uint32_t target_id[4];
+static uint32_t hic_id = DAPLINK_HIC_ID;
+
+static uint32_t crc_bootloader;
+static uint32_t crc_interface;
+static uint32_t crc_config_admin;
+static uint32_t crc_config_user;
+
+// Strings
+static char string_unique_id[48 + 1];
+static char string_mac[12 + 1];
+static char string_board_id[4 + 1];
+static char string_family_id[4 + 1];
+static char string_host_id[32 + 1];
+static char string_target_id[32 + 1];
+static char string_hic_id[8 + 1];
+static char string_version[4 + 1];
+
+static char usb_desc_unique_id[2 + sizeof(string_unique_id) * 2];
+
+
+const char *info_get_unique_id(void)
+{
+ return string_unique_id;
+}
+
+const char *info_get_board_id(void)
+{
+ return string_board_id;
+}
+
+const char *info_get_host_id(void)
+{
+ return string_host_id;
+}
+
+const char *info_get_target_id(void)
+{
+ return string_target_id;
+}
+
+const char *info_get_hic_id(void)
+{
+ return string_hic_id;
+}
+const char *info_get_version(void)
+{
+ return string_version;
+}
+const char *info_get_mac(void)
+{
+ return string_mac;
+}
+
+const char *info_get_unique_id_string_descriptor(void)
+{
+ return usb_desc_unique_id;
+}
+
+//prevent the compiler to optimize boad and family id
+#if (defined(__ICCARM__))
+#pragma optimize = none
+static void setup_basics(void)
+#elif (defined(__CC_ARM))
+#pragma push
+#pragma O0
+static void setup_basics(void)
+#elif (!defined(__GNUC__))
+/* #pragma GCC push_options */
+/* #pragma GCC optimize("O0") */
+static void __attribute__((optimize("O0"))) setup_basics(void)
+#else
+#error "Unknown compiler"
+#endif
+
+{
+ uint8_t i = 0, idx = 0;
+ uint16_t family_id = get_family_id();
+ memset(string_board_id, 0, sizeof(string_board_id));
+ memset(string_host_id, 0, sizeof(string_host_id));
+ memset(string_target_id, 0, sizeof(string_target_id));
+ memset(string_hic_id, 0, sizeof(string_hic_id));
+ memset(string_board_id, 0, sizeof(string_board_id));
+ // Host ID
+ idx = 0;
+
+ for (i = 0; i < 4; i++) {
+ idx += util_write_hex32(string_host_id + idx, host_id[i]);
+ }
+
+ string_host_id[idx++] = 0;
+ // Target ID
+ idx = 0;
+
+ for (i = 0; i < 4; i++) {
+ idx += util_write_hex32(string_target_id + idx, target_id[i]);
+ }
+
+ string_target_id[idx++] = 0;
+ // HIC ID
+ idx = 0;
+ idx += util_write_hex32(string_hic_id + idx, hic_id);
+ string_hic_id[idx++] = 0;
+ // Board ID
+ memcpy(string_board_id, get_board_id(), 4);
+ string_board_id[4] = 0;
+ idx = 0;
+ //Family ID
+ string_family_id[idx++] = hex_to_ascii(((family_id >> 12) & 0xF));
+ string_family_id[idx++] = hex_to_ascii(((family_id >> 8) & 0xF));
+#if !(defined(DAPLINK_BL)) && defined(DRAG_N_DROP_SUPPORT) //need to change the unique id when the msd is disabled
+ #if defined(MSC_ENDPOINT)
+ if (config_ram_get_disable_msd() == 1 || flash_algo_valid()==0){
+ string_family_id[idx++] = hex_to_ascii((((family_id >> 4) | 0x08) & 0xF));
+ } else {
+ string_family_id[idx++] = hex_to_ascii(((family_id >> 4) & 0xF));
+ }
+ #else //no msd support always have the most significant bit set for family id 2nd byte
+ string_family_id[idx++] = hex_to_ascii((((family_id >> 4) | 0x08) & 0xF));
+ #endif
+#else
+ string_family_id[idx++] = hex_to_ascii(((family_id >> 4) & 0xF));
+#endif
+ string_family_id[idx++] = hex_to_ascii(((family_id) & 0xF));
+ string_family_id[idx++] = 0;
+ // Version
+ idx = 0;
+ string_version[idx++] = '0' + (DAPLINK_VERSION / 1000) % 10;
+ string_version[idx++] = '0' + (DAPLINK_VERSION / 100) % 10;
+ string_version[idx++] = '0' + (DAPLINK_VERSION / 10) % 10;
+ string_version[idx++] = '0' + (DAPLINK_VERSION / 1) % 10;
+ string_version[idx++] = 0;
+}
+
+static void setup_unique_id()
+{
+ memset(string_unique_id, 0, sizeof(string_unique_id));
+ strcat(string_unique_id, string_board_id);
+ strcat(string_unique_id, string_family_id);
+ strcat(string_unique_id, string_host_id);
+ strcat(string_unique_id, string_hic_id);
+}
+
+static void setup_string_descriptor()
+{
+ uint8_t i = 0, idx = 0, len = 0;
+ len = strlen((const char *)string_unique_id);
+ // bLength
+ usb_desc_unique_id[idx++] = len * 2 + 2;
+ // bDescriptorType
+ usb_desc_unique_id[idx++] = 3;
+
+ // bString
+ for (i = 0; i < len; i++) {
+ usb_desc_unique_id[idx++] = string_unique_id[i];
+ usb_desc_unique_id[idx++] = 0;
+ }
+}
+
+void info_init(void)
+{
+ info_crc_compute();
+ read_unique_id(host_id);
+ setup_basics();
+ setup_unique_id();
+ setup_string_descriptor();
+}
+
+void info_set_uuid_target(uint32_t *uuid_data)
+{
+ uint32_t idx = 0;
+ // Save the target ID
+ memcpy(target_id, uuid_data, 16);
+ // patch for MAC use. Make sure MSB bits are set correctly
+ uuid_data[2] |= (0x2 << 8);
+ uuid_data[2] &= ~(0x1 << 8);
+ idx += util_write_hex16(string_mac + idx, uuid_data[2] & 0xFFFF);
+ idx += util_write_hex32(string_mac + idx, uuid_data[3]);
+ string_mac[idx++] = 0;
+}
+
+bool info_get_bootloader_present(void)
+{
+ bool present = true;
+
+ if (0 == DAPLINK_ROM_BL_SIZE) {
+ present = false;
+ }
+
+ if (DAPLINK_BUILD_KEY_BL != info_bl->build_key) {
+ present = false;
+ }
+
+ if (DAPLINK_HIC_ID != info_bl->hic_id) {
+ present = false;
+ }
+
+ return present;
+}
+
+bool info_get_interface_present(void)
+{
+ bool present = true;
+
+ if (0 == DAPLINK_ROM_IF_SIZE) {
+ present = false;
+ }
+
+ if (DAPLINK_BUILD_KEY_IF != info_if->build_key) {
+ present = false;
+ }
+
+ if (DAPLINK_HIC_ID != info_if->hic_id) {
+ present = false;
+ }
+
+ return present;
+}
+
+bool info_get_config_admin_present(void)
+{
+ //TODO, c1728p9 - check if admin config has been loaded
+ return false;
+}
+
+bool info_get_config_user_present(void)
+{
+ //TODO, c1728p9 - check if user config has a valid key
+ return false;
+}
+
+uint32_t info_get_crc_bootloader()
+{
+ return crc_bootloader;
+}
+
+uint32_t info_get_crc_interface()
+{
+ return crc_interface;
+}
+
+uint32_t info_get_crc_config_admin()
+{
+ return crc_config_admin;
+}
+
+uint32_t info_get_crc_config_user()
+{
+ return crc_config_user;
+}
+
+void info_crc_compute()
+{
+ crc_bootloader = 0;
+ crc_interface = 0;
+ crc_config_admin = 0;
+ crc_config_user = 0;
+
+ // Compute the CRCs of regions that exist
+ if (DAPLINK_ROM_BL_SIZE > 0) {
+ crc_bootloader = crc32((void *)DAPLINK_ROM_BL_START, DAPLINK_ROM_BL_SIZE - 4);
+ }
+
+ if (DAPLINK_ROM_IF_SIZE > 0) {
+ crc_interface = crc32((void *)DAPLINK_ROM_IF_START, DAPLINK_ROM_IF_SIZE - 4);
+ }
+
+ if (DAPLINK_ROM_CONFIG_ADMIN_SIZE > 0) {
+ crc_config_admin = crc32((void *)DAPLINK_ROM_CONFIG_ADMIN_START, DAPLINK_ROM_CONFIG_ADMIN_SIZE);
+ }
+
+ if (DAPLINK_ROM_CONFIG_USER_SIZE > 0) {
+ crc_config_user = crc32((void *)DAPLINK_ROM_CONFIG_USER_START, DAPLINK_ROM_CONFIG_USER_SIZE);
+ }
+}
+
+// Get version info as an integer
+uint32_t info_get_bootloader_version(void)
+{
+ // Don't read version if image is not present
+ if (!info_get_bootloader_present()) {
+ return 0;
+ }
+
+ return info_bl->version;
+}
+
+uint32_t info_get_interface_version(void)
+{
+ // Don't read version if image is not present
+ if (!info_get_interface_present()) {
+ return 0;
+ }
+
+ return info_if->version;
+}
+
+#if (defined(__CC_ARM))
+#pragma pop
+#endif
+#if (defined(__GNUC__))
+/* #pragma GCC pop_options */
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/info.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/info.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,92 @@
+/**
+ * @file info.h
+ * @brief methods to get information about the board
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef INFO_H
+#define INFO_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void info_init(void);
+void info_set_uuid_target(uint32_t *uuid_data);
+void info_crc_compute(void);
+
+
+// Get the 48 digit unique ID as a null terminated string.
+// This is the string used as the USB serial number.
+// This string is made up of the following:
+// <board ID><family ID><host ID><hic ID>
+const char *info_get_unique_id(void);
+
+// Get the 4 digit board ID as a null terminated string
+const char *info_get_board_id(void);
+
+// Get the 32 digit ID of the processor running daplink as a null terminated string
+const char *info_get_host_id(void);
+
+// Get the 32 digit ID of the target processor as a null terminated string
+const char *info_get_target_id(void);
+
+// Get the 8 digit hic ID as a null terminated string
+const char *info_get_hic_id(void);
+
+// Get the 4 digit version ID as a null terminated string
+const char *info_get_version(void);
+
+// Get the 12 digit mac as a null terminated string
+const char *info_get_mac(void);
+
+
+// Get the string descriptor for for the unique_id
+// This is in the format of a USB string descriptor
+// offset 0, size 1, bLength
+// offset 1, size 1, bDescriptorType always 3
+// offset 2, size n, bString - unicode encoded unique id
+const char *info_get_unique_id_string_descriptor(void);
+
+
+// Check if various regions are present
+bool info_get_bootloader_present(void);
+bool info_get_interface_present(void);
+bool info_get_config_admin_present(void);
+bool info_get_config_user_present(void);
+
+// Get the CRCs of various regions.
+// The CRC returned is only valid if
+// the given region is present.
+uint32_t info_get_crc_bootloader(void);
+uint32_t info_get_crc_interface(void);
+uint32_t info_get_crc_config_admin(void);
+uint32_t info_get_crc_config_user(void);
+
+// Get version info as an integer
+uint32_t info_get_bootloader_version(void);
+uint32_t info_get_interface_version(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/interface/SVC_Table.s --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/daplink/interface/SVC_Table.s Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,38 @@ +;/** +; * @file SVC_Table.s +; * @brief SVC config for application +; * +; * DAPLink Interface Firmware +; * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + AREA SVC_TABLE, CODE, READONLY + + EXPORT SVC_Count + +SVC_Cnt EQU (SVC_End-SVC_Table)/4 +SVC_Count DCD SVC_Cnt + +; Import user SVC functions here. + + EXPORT SVC_Table +SVC_Table +; Insert user SVC functions here. SVC 0 used by RTL Kernel. + +SVC_End + + END +
diff -r 000000000000 -r 01f31e923fe2 source/daplink/interface/bootloader_update.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/interface/bootloader_update.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,109 @@
+/**
+ * @file bootloader_update.c
+ * @brief Logic to perform a bootloader update when enabled
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2016-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifdef DRAG_N_DROP_SUPPORT
+#include <stdbool.h>
+#include <string.h>
+#include "flash_manager.h"
+#include "util.h"
+#include "bootloader.h"
+#include "info.h"
+#include "daplink.h"
+#include "crc.h"
+
+// Supress the warning 'null argument provided for parameter marked with attribute "nonnull"'
+// since the vector table is at address 0
+#pragma diag_suppress 2748
+
+#if !defined(DAPLINK_BOOTLOADER_UPDATE)
+ #define DAPLINK_BOOTLOADER_UPDATE 0
+#endif
+
+#if DAPLINK_BOOTLOADER_UPDATE
+ // The bootloader must be built first or this header will not be found
+ #include "bootloader_image.c"
+#else //DAPLINK_BOOTLOADER_UPDATE
+ static const unsigned int image_start = 0;
+ static const unsigned int image_size = 0;
+ static const char image_data[1];
+#endif //DAPLINK_BOOTLOADER_UPDATE
+
+static bool interface_image_valid()
+{
+ uint32_t stored_crc;
+ uint32_t computed_crc;
+
+ stored_crc = *(uint32_t *)(DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE - 4);
+ computed_crc = crc32((void *)DAPLINK_ROM_IF_START, DAPLINK_ROM_IF_SIZE - 4);
+ return computed_crc == stored_crc;
+}
+
+void bootloader_check_and_update(void)
+{
+ int same;
+ error_t ret;
+ bool update_present = image_size > 0;
+
+ if (!update_present) {
+ return;
+ }
+
+ if (info_get_bootloader_present() &&
+ (info_get_bootloader_version() > DAPLINK_VERSION)) {
+ // Bootloader is more recent than the one we have so
+ // don't change it
+ return;
+ }
+
+ if (!interface_image_valid()) {
+ // The interface is corrupt so don't attempt
+ // to apply the update
+ util_assert(0);
+ return;
+ }
+
+ same = memcmp((void*)image_start, image_data, image_size) == 0;
+ if (!same) {
+ ret = flash_manager_init(flash_intf_iap_protected);
+ if (ret != ERROR_SUCCESS) {
+ util_assert(0);
+ return;
+ }
+
+ ret = flash_manager_data(image_start, (const uint8_t*)image_data, image_size);
+ if (ret != ERROR_SUCCESS) {
+ flash_manager_uninit();
+ util_assert(0);
+ return;
+ }
+
+ ret = flash_manager_uninit();
+ if (ret != ERROR_SUCCESS) {
+ util_assert(0);
+ return;
+ }
+ }
+}
+#else //DRAG_N_DROP_SUPPORT
+
+void bootloader_check_and_update(void) {}
+
+#endif //DRAG_N_DROP_SUPPORT
diff -r 000000000000 -r 01f31e923fe2 source/daplink/interface/daplink.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/interface/daplink.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,43 @@
+/**
+ * @file daplink.c
+ * @brief Implementation of daplink.h
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "daplink.h"
+
+#ifdef DRAG_N_DROP_SUPPORT
+
+#include "virtual_fs.h"
+#include "compiler.h"
+
+COMPILER_ASSERT(DAPLINK_BUILD_KEY == DAPLINK_BUILD_KEY_IF);
+
+const vfs_filename_t daplink_mode_file_name = "START_BLACT";
+
+#endif //DRAG_N_DROP_SUPPORT
+
+bool daplink_is_bootloader()
+{
+ return false;
+}
+
+bool daplink_is_interface()
+{
+ return true;
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/interface/main.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/interface/main.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,475 @@
+/**
+ * @file main.c
+ * @brief Entry point for interface program logic
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+#include <stdio.h>
+
+#include "cmsis_os2.h"
+#include "rl_usb.h"
+#include "main.h"
+#include "gpio.h"
+#include "uart.h"
+#include "tasks.h"
+#include "swd_host.h"
+#include "info.h"
+#include "settings.h"
+#include "daplink.h"
+#include "util.h"
+#include "DAP.h"
+#include "bootloader.h"
+#include "cortex_m.h"
+#include "sdk.h"
+#include "target_family.h"
+#include "target_board.h"
+
+#ifdef DRAG_N_DROP_SUPPORT
+#include "vfs_manager.h"
+#include "flash_intf.h"
+#include "flash_manager.h"
+#endif
+
+// Event flags for main task
+// Timers events
+#define FLAGS_MAIN_90MS (1 << 0)
+#define FLAGS_MAIN_30MS (1 << 1)
+// Reset events
+#define FLAGS_MAIN_RESET (1 << 2)
+// Other Events
+#define FLAGS_MAIN_POWERDOWN (1 << 4)
+#define FLAGS_MAIN_DISABLEDEBUG (1 << 5)
+#define FLAGS_MAIN_PROC_USB (1 << 9)
+// Used by cdc when an event occurs
+#define FLAGS_MAIN_CDC_EVENT (1 << 11)
+// Used by msd when flashing a new binary
+#define FLAGS_LED_BLINK_30MS (1 << 6)
+
+// Timing constants (in 90mS ticks)
+// USB busy time (~3 sec)
+#define USB_BUSY_TIME (33)
+// Delay before a USB device connect may occur (~1 sec)
+#define USB_CONNECT_DELAY (11)
+// Timeout for USB being configured (~2 sec)
+#define USB_CONFIGURE_TIMEOUT (22)
+// Delay before target may be taken out of reset or reprogrammed after startup
+#define STARTUP_DELAY (1)
+
+// Decrement to zero
+#define DECZERO(x) (x ? --x : 0)
+
+//default hid led settings
+#ifndef HID_LED_DEF
+#define HID_LED_DEF GPIO_LED_OFF
+#endif
+
+//default cdc led settings
+#ifndef CDC_LED_DEF
+#define CDC_LED_DEF GPIO_LED_OFF
+#endif
+
+//default msc led settings
+#ifndef MSC_LED_DEF
+#define MSC_LED_DEF GPIO_LED_OFF
+#endif
+
+// Reference to our main task
+osThreadId_t main_task_id;
+
+// USB busy LED state; when TRUE the LED will flash once using 30mS clock tick
+static uint8_t hid_led_usb_activity = 0;
+static uint8_t cdc_led_usb_activity = 0;
+static uint8_t msc_led_usb_activity = 0;
+static main_led_state_t hid_led_state = MAIN_LED_FLASH;
+static main_led_state_t cdc_led_state = MAIN_LED_FLASH;
+static main_led_state_t msc_led_state = MAIN_LED_FLASH;
+
+// Global state of usb
+main_usb_connect_t usb_state;
+static bool usb_test_mode = false;
+
+// Timer task, set flags every 30mS and 90mS
+void timer_task_30mS(void * arg)
+{
+ static uint32_t i = 0;
+ osThreadFlagsSet(main_task_id, FLAGS_MAIN_30MS);
+ if (!(i++ % 3)) {
+ osThreadFlagsSet(main_task_id, FLAGS_MAIN_90MS);
+ }
+}
+
+// Functions called from other tasks to trigger events in the main task
+// parameter should be reset type??
+void main_reset_target(uint8_t send_unique_id)
+{
+ osThreadFlagsSet(main_task_id, FLAGS_MAIN_RESET);
+ return;
+}
+
+// Flash HID LED using 30mS tick
+void main_blink_hid_led(main_led_state_t state)
+{
+ hid_led_usb_activity = 1;
+ hid_led_state = state;
+ return;
+}
+
+// Flash CDC LED using 30mS tick
+void main_blink_cdc_led(main_led_state_t state)
+{
+ cdc_led_usb_activity = 1;
+ cdc_led_state = state;
+ return;
+}
+
+// Flash MSC LED using 30mS tick
+void main_blink_msc_led(main_led_state_t state)
+{
+ msc_led_usb_activity = 1;
+ msc_led_state = state;
+ return;
+}
+
+// Power down the interface
+void main_powerdown_event(void)
+{
+ osThreadFlagsSet(main_task_id, FLAGS_MAIN_POWERDOWN);
+ return;
+}
+
+// Disable debug on target
+void main_disable_debug_event(void)
+{
+ osThreadFlagsSet(main_task_id, FLAGS_MAIN_DISABLEDEBUG);
+ return;
+}
+
+// Start CDC processing
+void main_cdc_send_event(void)
+{
+ osThreadFlagsSet(main_task_id, FLAGS_MAIN_CDC_EVENT);
+ return;
+}
+
+void main_usb_set_test_mode(bool enabled)
+{
+ usb_test_mode = enabled;
+}
+
+void USBD_SignalHandler()
+{
+ osThreadFlagsSet(main_task_id, FLAGS_MAIN_PROC_USB);
+}
+
+extern void cdc_process_event(void);
+
+void main_task(void * arg)
+{
+ // State processing
+ uint16_t flags = 0;
+ // LED
+ gpio_led_state_t hid_led_value = HID_LED_DEF;
+ gpio_led_state_t cdc_led_value = CDC_LED_DEF;
+ gpio_led_state_t msc_led_value = MSC_LED_DEF;
+ // USB
+ uint32_t usb_state_count = USB_BUSY_TIME;
+ uint32_t usb_no_config_count = USB_CONFIGURE_TIMEOUT;
+ // button state
+ uint8_t reset_pressed = 0;
+#ifdef PBON_BUTTON
+ uint8_t power_on = 1;
+#endif
+
+ // Initialize settings - required for asserts to work
+ config_init();
+ // Update bootloader if it is out of date
+ bootloader_check_and_update();
+ // Get a reference to this task
+ main_task_id = osThreadGetId();
+ // leds
+ gpio_init();
+ // Turn to LED default settings
+ gpio_set_hid_led(hid_led_value);
+ gpio_set_cdc_led(cdc_led_value);
+ gpio_set_msc_led(msc_led_value);
+ // Initialize the DAP
+ DAP_Setup();
+
+ // make sure we have a valid board info structure.
+ util_assert(g_board_info.info_version == kBoardInfoVersion);
+
+ // do some init with the target before USB and files are configured
+ if (g_board_info.prerun_board_config) {
+ g_board_info.prerun_board_config();
+ }
+
+ //initialize the family
+ init_family();
+
+ if (g_target_family && g_target_family->prerun_target_config) {
+ g_target_family->prerun_target_config();
+ }
+
+ //setup some flags
+ if (g_board_info.flags & kEnableUnderResetConnect) {
+ swd_set_reset_connect(CONNECT_UNDER_RESET);
+ }
+ if (g_board_info.flags & kEnablePageErase) {
+#ifdef DRAG_N_DROP_SUPPORT
+ flash_manager_set_page_erase(true);
+#endif
+ }
+
+ // Update versions and IDs
+ info_init();
+ // USB
+ usbd_init();
+#ifdef DRAG_N_DROP_SUPPORT
+ vfs_mngr_fs_enable((config_ram_get_disable_msd()==0));
+#endif
+ usbd_connect(0);
+ usb_state = USB_CONNECTING;
+ usb_state_count = USB_CONNECT_DELAY;
+
+ // Start timer tasks
+ osTimerId_t tmr_id = osTimerNew(timer_task_30mS, osTimerPeriodic, NULL, NULL);
+ osTimerStart(tmr_id, 3);
+ while (1) {
+ flags = osThreadFlagsWait(FLAGS_MAIN_RESET // Put target in reset state
+ | FLAGS_MAIN_90MS // 90mS tick
+ | FLAGS_MAIN_30MS // 30mS tick
+ | FLAGS_MAIN_POWERDOWN // Power down interface
+ | FLAGS_MAIN_DISABLEDEBUG // Disable target debug
+ | FLAGS_MAIN_PROC_USB // process usb events
+ | FLAGS_MAIN_CDC_EVENT // cdc event
+ , osFlagsWaitAny
+ , osWaitForever);
+
+ if (flags & FLAGS_MAIN_PROC_USB) {
+ if (usb_test_mode) {
+ // When in USB test mode Insert a delay to
+ // simulate worst-case behavior.
+ osDelay(1);
+ }
+ USBD_Handler();
+ }
+
+ if (flags & FLAGS_MAIN_RESET) {
+ target_set_state(RESET_RUN);
+ }
+
+ if (flags & FLAGS_MAIN_POWERDOWN) {
+ // Disable debug
+ target_set_state(NO_DEBUG);
+ // Disable board power before USB is disconnected.
+ gpio_set_board_power(false);
+ // Disconnect USB
+ usbd_connect(0);
+ // Turn off LED
+ gpio_set_hid_led(GPIO_LED_OFF);
+ gpio_set_cdc_led(GPIO_LED_OFF);
+ gpio_set_msc_led(GPIO_LED_OFF);
+
+ // TODO: put the interface chip in sleep mode
+ while (1);
+ }
+
+ if (flags & FLAGS_MAIN_DISABLEDEBUG) {
+ // Disable debug
+ target_set_state(NO_DEBUG);
+ }
+
+ if (flags & FLAGS_MAIN_CDC_EVENT) {
+ cdc_process_event();
+ }
+
+ if (flags & FLAGS_MAIN_90MS) {
+ // Update USB busy status
+#ifdef DRAG_N_DROP_SUPPORT
+ vfs_mngr_periodic(90); // FLAGS_MAIN_90MS
+#endif
+ // Update USB connect status
+ switch (usb_state) {
+ case USB_DISCONNECTING:
+ usb_state = USB_DISCONNECTED;
+ // Disable board power before USB is disconnected.
+ gpio_set_board_power(false);
+ usbd_connect(0);
+ break;
+
+ case USB_CONNECTING:
+ // Wait before connecting
+ if (DECZERO(usb_state_count) == 0) {
+ usbd_connect(1);
+ usb_state = USB_CHECK_CONNECTED;
+ // Reset connect timeout
+ usb_no_config_count = USB_CONFIGURE_TIMEOUT;
+ }
+
+ break;
+
+ case USB_CHECK_CONNECTED:
+ if (usbd_configured()) {
+ // Let the HIC enable power to the target now that high power has been negotiated.
+ gpio_set_board_power(true);
+
+ usb_state = USB_CONNECTED;
+ }
+ else if (DECZERO(usb_no_config_count) == 0) {
+ // USB configuration timed out, which most likely indicates that the HIC is
+ // powered by a USB wall wart or similar power source. Go ahead and enable
+ // board power.
+ gpio_set_board_power(true);
+ }
+
+ break;
+
+ case USB_CONNECTED:
+ case USB_DISCONNECTED:
+ default:
+ break;
+ }
+ }
+
+ // 30mS tick used for flashing LED when USB is busy
+ if (flags & FLAGS_MAIN_30MS) {
+
+ // handle reset button without eventing
+ if (!reset_pressed && gpio_get_reset_btn_fwrd()) {
+#ifdef DRAG_N_DROP_SUPPORT
+ if (!flash_intf_target->flash_busy()) //added checking if flashing on target is in progress
+#endif
+ {
+ // Reset button pressed
+ target_set_state(RESET_HOLD);
+ reset_pressed = 1;
+ }
+ } else if (reset_pressed && !gpio_get_reset_btn_fwrd()) {
+ // Reset button released
+ target_set_state(RESET_RUN);
+ reset_pressed = 0;
+ }
+
+#ifdef PBON_BUTTON
+ // handle PBON pressed
+ if(gpio_get_pbon_btn())
+ {
+ if(power_on)
+ {
+ // Loop till PBON is pressed
+ while (gpio_get_pbon_btn()) {;}
+ // Power button released when target was running
+ target_set_state(SHUTDOWN);
+ power_on = 0;
+ }
+ else
+ {
+ // Loop till PBON is pressed
+ while (gpio_get_pbon_btn()) {;}
+ // Power button released when target was already powered off
+ target_set_state(POWER_ON);
+ power_on = 1;
+ }
+ }
+#endif
+
+ // DAP LED
+ if (hid_led_usb_activity) {
+
+ if ((hid_led_state == MAIN_LED_FLASH) || (hid_led_state == MAIN_LED_FLASH_PERMANENT)) {
+ // Toggle LED value
+ hid_led_value = GPIO_LED_ON == hid_led_value ? GPIO_LED_OFF : GPIO_LED_ON;
+
+ // If in flash mode stop after one cycle
+ if ((HID_LED_DEF == hid_led_value) && (MAIN_LED_FLASH == hid_led_state)) {
+ hid_led_usb_activity = 0;
+ hid_led_state = MAIN_LED_DEF;
+ }
+ } else {
+ //LED next state is MAIN_LED_DEF
+ hid_led_value = HID_LED_DEF;
+ hid_led_usb_activity = 0;
+ }
+
+ // Update hardware
+ gpio_set_hid_led(hid_led_value);
+ }
+
+ // MSD LED
+ if (msc_led_usb_activity) {
+
+ if ((msc_led_state == MAIN_LED_FLASH) || (msc_led_state == MAIN_LED_FLASH_PERMANENT)) {
+ // Toggle LED value
+ msc_led_value = GPIO_LED_ON == msc_led_value ? GPIO_LED_OFF : GPIO_LED_ON;
+
+ // If in flash mode stop after one cycle
+ if ((MSC_LED_DEF == msc_led_value) && (MAIN_LED_FLASH == msc_led_state)) {
+ msc_led_usb_activity = 0;
+ msc_led_state = MAIN_LED_DEF;
+ }
+ } else {
+ //LED next state is MAIN_LED_DEF
+ msc_led_value = MSC_LED_DEF;
+ msc_led_usb_activity = 0;
+ }
+
+ // Update hardware
+ gpio_set_msc_led(msc_led_value);
+ }
+
+ // CDC LED
+ if (cdc_led_usb_activity) {
+
+ if ((cdc_led_state == MAIN_LED_FLASH) || (cdc_led_state == MAIN_LED_FLASH_PERMANENT)){
+ // Toggle LED value
+ cdc_led_value = GPIO_LED_ON == cdc_led_value ? GPIO_LED_OFF : GPIO_LED_ON;
+
+ // If in flash mode stop after one cycle
+ if ((CDC_LED_DEF == cdc_led_value) && (MAIN_LED_FLASH == cdc_led_state)) {
+ cdc_led_usb_activity = 0;
+ cdc_led_state = MAIN_LED_DEF;
+ }
+ }else{
+ //LED next state is MAIN_LED_DEF
+ cdc_led_value = CDC_LED_DEF;
+ cdc_led_usb_activity = 0;
+ }
+
+ // Update hardware
+ gpio_set_cdc_led(cdc_led_value);
+ }
+ }
+ }
+}
+
+int main(void)
+{
+ // Explicitly set the vector table since the bootloader might not set
+ // it to what we expect.
+#if DAPLINK_ROM_BL_SIZE > 0
+ SCB->VTOR = SCB_VTOR_TBLOFF_Msk & DAPLINK_ROM_IF_START;
+#endif
+ // initialize vendor sdk
+ sdk_init();
+
+ osKernelInitialize(); // Initialize CMSIS-RTOS
+ osThreadNew(main_task, NULL, NULL); // Create application main thread
+ osKernelStart(); // Start thread execution
+ for (;;) {}
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/interface/main.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/interface/main.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,64 @@
+/**
+ * @file main.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MAIN_H
+#define MAIN_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+// LED state
+typedef enum main_led_state {
+ MAIN_LED_DEF = 0,
+ MAIN_LED_FLASH,
+ MAIN_LED_FLASH_PERMANENT
+} main_led_state_t;
+
+typedef enum main_usb_connect {
+ USB_DISCONNECTED,
+ USB_CONNECTING,
+ USB_CONNECTED,
+ USB_CHECK_CONNECTED,
+ USB_CONFIGURED,
+ USB_DISCONNECTING
+} main_usb_connect_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void main_reset_target(uint8_t send_unique_id);
+void main_usb_set_test_mode(bool enabled);
+void main_powerdown_event(void);
+void main_disable_debug_event(void);
+void main_cdc_send_event(void);
+void main_msc_disconnect_event(void);
+void main_msc_delay_disconnect_event(void);
+void main_force_msc_disconnect_event(void);
+void main_blink_hid_led(main_led_state_t state);
+void main_blink_msc_led(main_led_state_t state);
+void main_blink_cdc_led(main_led_state_t state);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/interface/swd_host.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/interface/swd_host.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1178 @@
+/**
+ * @file swd_host.c
+ * @brief Implementation of swd_host.h
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * Copyright 2019, Cypress Semiconductor Corporation
+ * or a subsidiary of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef TARGET_MCU_CORTEX_A
+#include "cmsis_os2.h"
+#include "target_config.h"
+#include "swd_host.h"
+#include "debug_cm.h"
+#include "DAP_config.h"
+#include "DAP.h"
+#include "target_family.h"
+#include "device.h"
+
+// Default NVIC and Core debug base addresses
+// TODO: Read these addresses from ROM.
+#define NVIC_Addr (0xe000e000)
+#define DBG_Addr (0xe000edf0)
+
+// AP CSW register, base value
+#define CSW_VALUE (CSW_RESERVED | CSW_MSTRDBG | CSW_HPROT | CSW_DBGSTAT | CSW_SADDRINC)
+
+#define DCRDR 0xE000EDF8
+#define DCRSR 0xE000EDF4
+#define DHCSR 0xE000EDF0
+#define REGWnR (1 << 16)
+
+#define MAX_SWD_RETRY 100//10
+#define MAX_TIMEOUT 1000000 // Timeout for syscalls on target
+
+// Use the CMSIS-Core definition if available.
+#if !defined(SCB_AIRCR_PRIGROUP_Pos)
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+#endif
+
+typedef struct {
+ uint32_t select;
+ uint32_t csw;
+} DAP_STATE;
+
+typedef struct {
+ uint32_t r[16];
+ uint32_t xpsr;
+} DEBUG_STATE;
+
+static SWD_CONNECT_TYPE reset_connect = CONNECT_NORMAL;
+
+static DAP_STATE dap_state;
+static uint32_t soft_reset = SYSRESETREQ;
+
+static uint32_t swd_get_apsel(uint32_t adr)
+{
+ uint32_t apsel = target_get_apsel();
+ if (!apsel)
+ return adr & 0xff000000;
+ else
+ return apsel;
+}
+
+void swd_set_reset_connect(SWD_CONNECT_TYPE type)
+{
+ reset_connect = type;
+}
+
+void int2array(uint8_t *res, uint32_t data, uint8_t len)
+{
+ uint8_t i = 0;
+
+ for (i = 0; i < len; i++) {
+ res[i] = (data >> 8 * i) & 0xff;
+ }
+}
+
+uint8_t swd_transfer_retry(uint32_t req, uint32_t *data)
+{
+ uint8_t i, ack;
+
+ for (i = 0; i < MAX_SWD_RETRY; i++) {
+ ack = SWD_Transfer(req, data);
+
+ // if ack != WAIT
+ if (ack != DAP_TRANSFER_WAIT) {
+ return ack;
+ }
+ }
+
+ return ack;
+}
+
+void swd_set_soft_reset(uint32_t soft_reset_type)
+{
+ soft_reset = soft_reset_type;
+}
+
+uint8_t swd_init(void)
+{
+ //TODO - DAP_Setup puts GPIO pins in a hi-z state which can
+ // cause problems on re-init. This needs to be investigated
+ // and fixed.
+ DAP_Setup();
+ PORT_SWD_SETUP();
+ return 1;
+}
+
+uint8_t swd_off(void)
+{
+ PORT_OFF();
+ return 1;
+}
+
+uint8_t swd_clear_errors(void)
+{
+ if (!swd_write_dp(DP_ABORT, STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR)) {
+ return 0;
+ }
+ return 1;
+}
+
+// Read debug port register.
+uint8_t swd_read_dp(uint8_t adr, uint32_t *val)
+{
+ uint32_t tmp_in;
+ uint8_t tmp_out[4];
+ uint8_t ack;
+ uint32_t tmp;
+ tmp_in = SWD_REG_DP | SWD_REG_R | SWD_REG_ADR(adr);
+ ack = swd_transfer_retry(tmp_in, (uint32_t *)tmp_out);
+ *val = 0;
+ tmp = tmp_out[3];
+ *val |= (tmp << 24);
+ tmp = tmp_out[2];
+ *val |= (tmp << 16);
+ tmp = tmp_out[1];
+ *val |= (tmp << 8);
+ tmp = tmp_out[0];
+ *val |= (tmp << 0);
+ return (ack == 0x01);
+}
+
+// Write debug port register
+uint8_t swd_write_dp(uint8_t adr, uint32_t val)
+{
+ uint32_t req;
+ uint8_t data[4];
+ uint8_t ack;
+
+ //check if the right bank is already selected
+ if ((adr == DP_SELECT) && (dap_state.select == val)) {
+ return 1;
+ }
+
+ req = SWD_REG_DP | SWD_REG_W | SWD_REG_ADR(adr);
+ int2array(data, val, 4);
+ ack = swd_transfer_retry(req, (uint32_t *)data);
+ if ((ack == DAP_TRANSFER_OK) && (adr == DP_SELECT)) {
+ dap_state.select = val;
+ }
+ return (ack == 0x01);
+}
+
+// Read access port register.
+uint8_t swd_read_ap(uint32_t adr, uint32_t *val)
+{
+ uint8_t tmp_in, ack;
+ uint8_t tmp_out[4];
+ uint32_t tmp;
+ uint32_t apsel = swd_get_apsel(adr);
+ uint32_t bank_sel = adr & APBANKSEL;
+
+ if (!swd_write_dp(DP_SELECT, apsel | bank_sel)) {
+ return 0;
+ }
+
+ tmp_in = SWD_REG_AP | SWD_REG_R | SWD_REG_ADR(adr);
+ // first dummy read
+ swd_transfer_retry(tmp_in, (uint32_t *)tmp_out);
+ ack = swd_transfer_retry(tmp_in, (uint32_t *)tmp_out);
+ *val = 0;
+ tmp = tmp_out[3];
+ *val |= (tmp << 24);
+ tmp = tmp_out[2];
+ *val |= (tmp << 16);
+ tmp = tmp_out[1];
+ *val |= (tmp << 8);
+ tmp = tmp_out[0];
+ *val |= (tmp << 0);
+ return (ack == 0x01);
+}
+
+// Write access port register
+uint8_t swd_write_ap(uint32_t adr, uint32_t val)
+{
+ uint8_t data[4];
+ uint8_t req, ack;
+ uint32_t apsel = swd_get_apsel(adr);
+ uint32_t bank_sel = adr & APBANKSEL;
+
+ if (!swd_write_dp(DP_SELECT, apsel | bank_sel)) {
+ return 0;
+ }
+
+ switch (adr) {
+ case AP_CSW:
+ if (dap_state.csw == val) {
+ return 1;
+ }
+
+ dap_state.csw = val;
+ break;
+
+ default:
+ break;
+ }
+
+ req = SWD_REG_AP | SWD_REG_W | SWD_REG_ADR(adr);
+ int2array(data, val, 4);
+
+ if (swd_transfer_retry(req, (uint32_t *)data) != 0x01) {
+ return 0;
+ }
+
+ req = SWD_REG_DP | SWD_REG_R | SWD_REG_ADR(DP_RDBUFF);
+ ack = swd_transfer_retry(req, NULL);
+ return (ack == 0x01);
+}
+
+
+// Write 32-bit word aligned values to target memory using address auto-increment.
+// size is in bytes.
+static uint8_t swd_write_block(uint32_t address, uint8_t *data, uint32_t size)
+{
+ uint8_t tmp_in[4], req;
+ uint32_t size_in_words;
+ uint32_t i, ack;
+
+ if (size == 0) {
+ return 0;
+ }
+
+ size_in_words = size / 4;
+
+ // CSW register
+ if (!swd_write_ap(AP_CSW, CSW_VALUE | CSW_SIZE32)) {
+ return 0;
+ }
+
+ // TAR write
+ req = SWD_REG_AP | SWD_REG_W | (1 << 2);
+ int2array(tmp_in, address, 4);
+
+ if (swd_transfer_retry(req, (uint32_t *)tmp_in) != 0x01) {
+ return 0;
+ }
+
+ // DRW write
+ req = SWD_REG_AP | SWD_REG_W | (3 << 2);
+
+ for (i = 0; i < size_in_words; i++) {
+ if (swd_transfer_retry(req, (uint32_t *)data) != 0x01) {
+ return 0;
+ }
+
+ data += 4;
+ }
+
+ // dummy read
+ req = SWD_REG_DP | SWD_REG_R | SWD_REG_ADR(DP_RDBUFF);
+ ack = swd_transfer_retry(req, NULL);
+ return (ack == 0x01);
+}
+
+// Read 32-bit word aligned values from target memory using address auto-increment.
+// size is in bytes.
+static uint8_t swd_read_block(uint32_t address, uint8_t *data, uint32_t size)
+{
+ uint8_t tmp_in[4], req, ack;
+ uint32_t size_in_words;
+ uint32_t i;
+
+ if (size == 0) {
+ return 0;
+ }
+
+ size_in_words = size / 4;
+
+ if (!swd_write_ap(AP_CSW, CSW_VALUE | CSW_SIZE32)) {
+ return 0;
+ }
+
+ // TAR write
+ req = SWD_REG_AP | SWD_REG_W | AP_TAR;
+ int2array(tmp_in, address, 4);
+
+ if (swd_transfer_retry(req, (uint32_t *)tmp_in) != DAP_TRANSFER_OK) {
+ return 0;
+ }
+
+ // read data
+ req = SWD_REG_AP | SWD_REG_R | AP_DRW;
+
+ // initiate first read, data comes back in next read
+ if (swd_transfer_retry(req, NULL) != 0x01) {
+ return 0;
+ }
+
+ for (i = 0; i < (size_in_words - 1); i++) {
+ if (swd_transfer_retry(req, (uint32_t *)data) != DAP_TRANSFER_OK) {
+ return 0;
+ }
+
+ data += 4;
+ }
+
+ // read last word
+ req = SWD_REG_DP | SWD_REG_R | SWD_REG_ADR(DP_RDBUFF);
+ ack = swd_transfer_retry(req, (uint32_t *)data);
+ return (ack == 0x01);
+}
+
+// Read target memory.
+static uint8_t swd_read_data(uint32_t addr, uint32_t *val)
+{
+ uint8_t tmp_in[4];
+ uint8_t tmp_out[4];
+ uint8_t req, ack;
+ uint32_t tmp;
+ // put addr in TAR register
+ int2array(tmp_in, addr, 4);
+ req = SWD_REG_AP | SWD_REG_W | (1 << 2);
+
+ if (swd_transfer_retry(req, (uint32_t *)tmp_in) != 0x01) {
+ return 0;
+ }
+
+ // read data
+ req = SWD_REG_AP | SWD_REG_R | (3 << 2);
+
+ if (swd_transfer_retry(req, (uint32_t *)tmp_out) != 0x01) {
+ return 0;
+ }
+
+ // dummy read
+ req = SWD_REG_DP | SWD_REG_R | SWD_REG_ADR(DP_RDBUFF);
+ ack = swd_transfer_retry(req, (uint32_t *)tmp_out);
+ *val = 0;
+ tmp = tmp_out[3];
+ *val |= (tmp << 24);
+ tmp = tmp_out[2];
+ *val |= (tmp << 16);
+ tmp = tmp_out[1];
+ *val |= (tmp << 8);
+ tmp = tmp_out[0];
+ *val |= (tmp << 0);
+ return (ack == 0x01);
+}
+
+// Write target memory.
+static uint8_t swd_write_data(uint32_t address, uint32_t data)
+{
+ uint8_t tmp_in[4];
+ uint8_t req, ack;
+ // put addr in TAR register
+ int2array(tmp_in, address, 4);
+ req = SWD_REG_AP | SWD_REG_W | (1 << 2);
+
+ if (swd_transfer_retry(req, (uint32_t *)tmp_in) != 0x01) {
+ return 0;
+ }
+
+ // write data
+ int2array(tmp_in, data, 4);
+ req = SWD_REG_AP | SWD_REG_W | (3 << 2);
+
+ if (swd_transfer_retry(req, (uint32_t *)tmp_in) != 0x01) {
+ return 0;
+ }
+
+ // dummy read
+ req = SWD_REG_DP | SWD_REG_R | SWD_REG_ADR(DP_RDBUFF);
+ ack = swd_transfer_retry(req, NULL);
+ return (ack == 0x01) ? 1 : 0;
+}
+
+// Read 32-bit word from target memory.
+uint8_t swd_read_word(uint32_t addr, uint32_t *val)
+{
+ if (!swd_write_ap(AP_CSW, CSW_VALUE | CSW_SIZE32)) {
+ return 0;
+ }
+
+ if (!swd_read_data(addr, val)) {
+ return 0;
+ }
+
+ return 1;
+}
+
+// Write 32-bit word to target memory.
+uint8_t swd_write_word(uint32_t addr, uint32_t val)
+{
+ if (!swd_write_ap(AP_CSW, CSW_VALUE | CSW_SIZE32)) {
+ return 0;
+ }
+
+ if (!swd_write_data(addr, val)) {
+ return 0;
+ }
+
+ return 1;
+}
+
+// Read 8-bit byte from target memory.
+uint8_t swd_read_byte(uint32_t addr, uint8_t *val)
+{
+ uint32_t tmp;
+
+ if (!swd_write_ap(AP_CSW, CSW_VALUE | CSW_SIZE8)) {
+ return 0;
+ }
+
+ if (!swd_read_data(addr, &tmp)) {
+ return 0;
+ }
+
+ *val = (uint8_t)(tmp >> ((addr & 0x03) << 3));
+ return 1;
+}
+
+// Write 8-bit byte to target memory.
+uint8_t swd_write_byte(uint32_t addr, uint8_t val)
+{
+ uint32_t tmp;
+
+ if (!swd_write_ap(AP_CSW, CSW_VALUE | CSW_SIZE8)) {
+ return 0;
+ }
+
+ tmp = val << ((addr & 0x03) << 3);
+
+ if (!swd_write_data(addr, tmp)) {
+ return 0;
+ }
+
+ return 1;
+}
+
+// Read unaligned data from target memory.
+// size is in bytes.
+uint8_t swd_read_memory(uint32_t address, uint8_t *data, uint32_t size)
+{
+ uint32_t n;
+
+ // Read bytes until word aligned
+ while ((size > 0) && (address & 0x3)) {
+ if (!swd_read_byte(address, data)) {
+ return 0;
+ }
+
+ address++;
+ data++;
+ size--;
+ }
+
+ // Read word aligned blocks
+ while (size > 3) {
+ // Limit to auto increment page size
+ n = TARGET_AUTO_INCREMENT_PAGE_SIZE - (address & (TARGET_AUTO_INCREMENT_PAGE_SIZE - 1));
+
+ if (size < n) {
+ n = size & 0xFFFFFFFC; // Only count complete words remaining
+ }
+
+ if (!swd_read_block(address, data, n)) {
+ return 0;
+ }
+
+ address += n;
+ data += n;
+ size -= n;
+ }
+
+ // Read remaining bytes
+ while (size > 0) {
+ if (!swd_read_byte(address, data)) {
+ return 0;
+ }
+
+ address++;
+ data++;
+ size--;
+ }
+
+ return 1;
+}
+
+// Write unaligned data to target memory.
+// size is in bytes.
+uint8_t swd_write_memory(uint32_t address, uint8_t *data, uint32_t size)
+{
+ uint32_t n = 0;
+
+ // Write bytes until word aligned
+ while ((size > 0) && (address & 0x3)) {
+ if (!swd_write_byte(address, *data)) {
+ return 0;
+ }
+
+ address++;
+ data++;
+ size--;
+ }
+
+ // Write word aligned blocks
+ while (size > 3) {
+ // Limit to auto increment page size
+ n = TARGET_AUTO_INCREMENT_PAGE_SIZE - (address & (TARGET_AUTO_INCREMENT_PAGE_SIZE - 1));
+
+ if (size < n) {
+ n = size & 0xFFFFFFFC; // Only count complete words remaining
+ }
+
+ if (!swd_write_block(address, data, n)) {
+ return 0;
+ }
+
+ address += n;
+ data += n;
+ size -= n;
+ }
+
+ // Write remaining bytes
+ while (size > 0) {
+ if (!swd_write_byte(address, *data)) {
+ return 0;
+ }
+
+ address++;
+ data++;
+ size--;
+ }
+
+ return 1;
+}
+
+// Execute system call.
+static uint8_t swd_write_debug_state(DEBUG_STATE *state)
+{
+ uint32_t i, status;
+
+ if (!swd_write_dp(DP_SELECT, 0)) {
+ return 0;
+ }
+
+ // R0, R1, R2, R3
+ for (i = 0; i < 4; i++) {
+ if (!swd_write_core_register(i, state->r[i])) {
+ return 0;
+ }
+ }
+
+ // R9
+ if (!swd_write_core_register(9, state->r[9])) {
+ return 0;
+ }
+
+ // R13, R14, R15
+ for (i = 13; i < 16; i++) {
+ if (!swd_write_core_register(i, state->r[i])) {
+ return 0;
+ }
+ }
+
+ // xPSR
+ if (!swd_write_core_register(16, state->xpsr)) {
+ return 0;
+ }
+
+ if (!swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN | C_MASKINTS | C_HALT)) {
+ return 0;
+ }
+
+ if (!swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN | C_MASKINTS)) {
+ return 0;
+ }
+
+ // check status
+ if (!swd_read_dp(DP_CTRL_STAT, &status)) {
+ return 0;
+ }
+
+ if (status & (STICKYERR | WDATAERR)) {
+ return 0;
+ }
+
+ return 1;
+}
+
+uint8_t swd_read_core_register(uint32_t n, uint32_t *val)
+{
+ int i = 0, timeout = 100;
+
+ if (!swd_write_word(DCRSR, n)) {
+ return 0;
+ }
+
+ // wait for S_REGRDY
+ for (i = 0; i < timeout; i++) {
+ if (!swd_read_word(DHCSR, val)) {
+ return 0;
+ }
+
+ if (*val & S_REGRDY) {
+ break;
+ }
+ }
+
+ if (i == timeout) {
+ return 0;
+ }
+
+ if (!swd_read_word(DCRDR, val)) {
+ return 0;
+ }
+
+ return 1;
+}
+
+uint8_t swd_write_core_register(uint32_t n, uint32_t val)
+{
+ int i = 0, timeout = 100;
+
+ if (!swd_write_word(DCRDR, val)) {
+ return 0;
+ }
+
+ if (!swd_write_word(DCRSR, n | REGWnR)) {
+ return 0;
+ }
+
+ // wait for S_REGRDY
+ for (i = 0; i < timeout; i++) {
+ if (!swd_read_word(DHCSR, &val)) {
+ return 0;
+ }
+
+ if (val & S_REGRDY) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+static uint8_t swd_wait_until_halted(void)
+{
+ // Wait for target to stop
+ uint32_t val, i, timeout = MAX_TIMEOUT;
+
+ for (i = 0; i < timeout; i++) {
+ if (!swd_read_word(DBG_HCSR, &val)) {
+ return 0;
+ }
+
+ if (val & S_HALT) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+uint8_t swd_flash_syscall_exec(const program_syscall_t *sysCallParam, uint32_t entry, uint32_t arg1, uint32_t arg2, uint32_t arg3, uint32_t arg4, flash_algo_return_t return_type)
+{
+ DEBUG_STATE state = {{0}, 0};
+ // Call flash algorithm function on target and wait for result.
+ state.r[0] = arg1; // R0: Argument 1
+ state.r[1] = arg2; // R1: Argument 2
+ state.r[2] = arg3; // R2: Argument 3
+ state.r[3] = arg4; // R3: Argument 4
+ state.r[9] = sysCallParam->static_base; // SB: Static Base
+ state.r[13] = sysCallParam->stack_pointer; // SP: Stack Pointer
+ state.r[14] = sysCallParam->breakpoint; // LR: Exit Point
+ state.r[15] = entry; // PC: Entry Point
+ state.xpsr = 0x01000000; // xPSR: T = 1, ISR = 0
+
+ if (!swd_write_debug_state(&state)) {
+ return 0;
+ }
+
+ if (!swd_wait_until_halted()) {
+ return 0;
+ }
+
+ if (!swd_read_core_register(0, &state.r[0])) {
+ return 0;
+ }
+
+ //remove the C_MASKINTS
+ if (!swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN | C_HALT)) {
+ return 0;
+ }
+
+ if ( return_type == FLASHALGO_RETURN_POINTER ) {
+ // Flash verify functions return pointer to byte following the buffer if successful.
+ if (state.r[0] != (arg1 + arg2)) {
+ return 0;
+ }
+ }
+ else {
+ // Flash functions return 0 if successful.
+ if (state.r[0] != 0) {
+ return 0;
+ }
+ }
+
+ return 1;
+}
+
+// SWD Reset
+static uint8_t swd_reset(void)
+{
+ uint8_t tmp_in[8];
+ uint8_t i = 0;
+
+ for (i = 0; i < 8; i++) {
+ tmp_in[i] = 0xff;
+ }
+
+ SWJ_Sequence(51, tmp_in);
+ return 1;
+}
+
+// SWD Switch
+static uint8_t swd_switch(uint16_t val)
+{
+ uint8_t tmp_in[2];
+ tmp_in[0] = val & 0xff;
+ tmp_in[1] = (val >> 8) & 0xff;
+ SWJ_Sequence(16, tmp_in);
+ return 1;
+}
+
+// SWD Read ID
+static uint8_t swd_read_idcode(uint32_t *id)
+{
+ uint8_t tmp_in[1];
+ uint8_t tmp_out[4];
+ tmp_in[0] = 0x00;
+ SWJ_Sequence(8, tmp_in);
+
+ if (swd_read_dp(0, (uint32_t *)tmp_out) != 0x01) {
+ return 0;
+ }
+
+ *id = (tmp_out[3] << 24) | (tmp_out[2] << 16) | (tmp_out[1] << 8) | tmp_out[0];
+ return 1;
+}
+
+
+uint8_t JTAG2SWD()
+{
+ uint32_t tmp = 0;
+
+ if (!swd_reset()) {
+ return 0;
+ }
+
+ if (!swd_switch(0xE79E)) {
+ return 0;
+ }
+
+ if (!swd_reset()) {
+ return 0;
+ }
+
+ if (!swd_read_idcode(&tmp)) {
+ return 0;
+ }
+
+ return 1;
+}
+
+uint8_t swd_init_debug(void)
+{
+ uint32_t tmp = 0;
+ int i = 0;
+ int timeout = 100;
+ // init dap state with fake values
+ dap_state.select = 0xffffffff;
+ dap_state.csw = 0xffffffff;
+
+ int8_t retries = 4;
+ int8_t do_abort = 0;
+ do {
+ if (do_abort) {
+ //do an abort on stale target, then reset the device
+ swd_write_dp(DP_ABORT, DAPABORT);
+ swd_set_target_reset(1);
+ osDelay(2);
+ swd_set_target_reset(0);
+ osDelay(2);
+ do_abort = 0;
+ }
+ swd_init();
+ // call a target dependant function
+ // this function can do several stuff before really
+ // initing the debug
+ if (g_target_family && g_target_family->target_before_init_debug) {
+ g_target_family->target_before_init_debug();
+ }
+
+ if (!JTAG2SWD()) {
+ do_abort = 1;
+ continue;
+ }
+
+ if (!swd_clear_errors()) {
+ do_abort = 1;
+ continue;
+ }
+
+ if (!swd_write_dp(DP_SELECT, 0)) {
+ do_abort = 1;
+ continue;
+
+ }
+
+ // Power up
+ if (!swd_write_dp(DP_CTRL_STAT, CSYSPWRUPREQ | CDBGPWRUPREQ)) {
+ do_abort = 1;
+ continue;
+ }
+
+ for (i = 0; i < timeout; i++) {
+ if (!swd_read_dp(DP_CTRL_STAT, &tmp)) {
+ do_abort = 1;
+ break;
+ }
+ if ((tmp & (CDBGPWRUPACK | CSYSPWRUPACK)) == (CDBGPWRUPACK | CSYSPWRUPACK)) {
+ // Break from loop if powerup is complete
+ break;
+ }
+ }
+ if ((i == timeout) || (do_abort == 1)) {
+ // Unable to powerup DP
+ do_abort = 1;
+ continue;
+ }
+
+ if (!swd_write_dp(DP_CTRL_STAT, CSYSPWRUPREQ | CDBGPWRUPREQ | TRNNORMAL | MASKLANE)) {
+ do_abort = 1;
+ continue;
+ }
+
+ // call a target dependant function:
+ // some target can enter in a lock state
+ // this function can unlock these targets
+ if (g_target_family && g_target_family->target_unlock_sequence) {
+ g_target_family->target_unlock_sequence();
+ }
+
+ if (!swd_write_dp(DP_SELECT, 0)) {
+ do_abort = 1;
+ continue;
+ }
+
+ return 1;
+
+ } while (--retries > 0);
+
+ return 0;
+}
+
+uint8_t swd_set_target_state_hw(target_state_t state)
+{
+ uint32_t val;
+ int8_t ap_retries = 2;
+ /* Calling swd_init prior to entering RUN state causes operations to fail. */
+ if (state != RUN) {
+ swd_init();
+ }
+
+ switch (state) {
+ case RESET_HOLD:
+ swd_set_target_reset(1);
+ break;
+
+ case RESET_RUN:
+ swd_set_target_reset(1);
+ osDelay(2);
+ swd_set_target_reset(0);
+ osDelay(2);
+ swd_off();
+ break;
+
+ case RESET_PROGRAM:
+ if (!swd_init_debug()) {
+ return 0;
+ }
+
+ if (reset_connect == CONNECT_UNDER_RESET) {
+ // Assert reset
+ swd_set_target_reset(1);
+ osDelay(2);
+ }
+
+ // Enable debug
+ while(swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN) == 0) {
+ if( --ap_retries <=0 )
+ return 0;
+ // Target is in invalid state?
+ swd_set_target_reset(1);
+ osDelay(2);
+ swd_set_target_reset(0);
+ osDelay(2);
+ }
+
+ // Enable halt on reset
+ if (!swd_write_word(DBG_EMCR, VC_CORERESET)) {
+ return 0;
+ }
+
+ if (reset_connect == CONNECT_NORMAL) {
+ // Assert reset
+ swd_set_target_reset(1);
+ osDelay(2);
+ }
+
+ // Deassert reset
+ swd_set_target_reset(0);
+ osDelay(2);
+
+ do {
+ if (!swd_read_word(DBG_HCSR, &val)) {
+ return 0;
+ }
+ } while ((val & S_HALT) == 0);
+
+ // Disable halt on reset
+ if (!swd_write_word(DBG_EMCR, 0)) {
+ return 0;
+ }
+
+ break;
+
+ case NO_DEBUG:
+ if (!swd_write_word(DBG_HCSR, DBGKEY)) {
+ return 0;
+ }
+
+ break;
+
+ case DEBUG:
+ if (!JTAG2SWD()) {
+ return 0;
+ }
+
+ if (!swd_clear_errors()) {
+ return 0;
+ }
+
+ // Ensure CTRL/STAT register selected in DPBANKSEL
+ if (!swd_write_dp(DP_SELECT, 0)) {
+ return 0;
+ }
+
+ // Power up
+ if (!swd_write_dp(DP_CTRL_STAT, CSYSPWRUPREQ | CDBGPWRUPREQ)) {
+ return 0;
+ }
+
+ // Enable debug
+ if (!swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN)) {
+ return 0;
+ }
+
+ break;
+
+ case HALT:
+ if (!swd_init_debug()) {
+ return 0;
+ }
+
+ // Enable debug and halt the core (DHCSR <- 0xA05F0003)
+ if (!swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN | C_HALT)) {
+ return 0;
+ }
+
+ // Wait until core is halted
+ do {
+ if (!swd_read_word(DBG_HCSR, &val)) {
+ return 0;
+ }
+ } while ((val & S_HALT) == 0);
+ break;
+
+ case RUN:
+ if (!swd_write_word(DBG_HCSR, DBGKEY)) {
+ return 0;
+ }
+ swd_off();
+ break;
+
+ case POST_FLASH_RESET:
+ // This state should be handled in target_reset.c, nothing needs to be done here.
+ break;
+
+ default:
+ return 0;
+ }
+
+ return 1;
+}
+
+uint8_t swd_set_target_state_sw(target_state_t state)
+{
+ uint32_t val;
+ int8_t ap_retries = 2;
+ /* Calling swd_init prior to enterring RUN state causes operations to fail. */
+ if (state != RUN) {
+ swd_init();
+ }
+
+ switch (state) {
+ case RESET_HOLD:
+ swd_set_target_reset(1);
+ break;
+
+ case RESET_RUN:
+ swd_set_target_reset(1);
+ osDelay(2);
+ swd_set_target_reset(0);
+ osDelay(2);
+ swd_off();
+ break;
+
+ case RESET_PROGRAM:
+ if (!swd_init_debug()) {
+ return 0;
+ }
+
+ // Enable debug and halt the core (DHCSR <- 0xA05F0003)
+ while (swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN | C_HALT) == 0) {
+ if ( --ap_retries <=0 ) {
+ return 0;
+ }
+ // Target is in invalid state?
+ swd_set_target_reset(1);
+ osDelay(2);
+ swd_set_target_reset(0);
+ osDelay(2);
+ }
+
+ // Wait until core is halted
+ do {
+ if (!swd_read_word(DBG_HCSR, &val)) {
+ return 0;
+ }
+ } while ((val & S_HALT) == 0);
+
+ // Enable halt on reset
+ if (!swd_write_word(DBG_EMCR, VC_CORERESET)) {
+ return 0;
+ }
+
+ // Perform a soft reset
+ if (!swd_read_word(NVIC_AIRCR, &val)) {
+ return 0;
+ }
+
+ if (!swd_write_word(NVIC_AIRCR, VECTKEY | (val & SCB_AIRCR_PRIGROUP_Msk) | soft_reset)) {
+ return 0;
+ }
+
+ osDelay(2);
+
+ do {
+ if (!swd_read_word(DBG_HCSR, &val)) {
+ return 0;
+ }
+ } while ((val & S_HALT) == 0);
+
+ // Disable halt on reset
+ if (!swd_write_word(DBG_EMCR, 0)) {
+ return 0;
+ }
+
+ break;
+
+ case NO_DEBUG:
+ if (!swd_write_word(DBG_HCSR, DBGKEY)) {
+ return 0;
+ }
+
+ break;
+
+ case DEBUG:
+ if (!JTAG2SWD()) {
+ return 0;
+ }
+
+ if (!swd_clear_errors()) {
+ return 0;
+ }
+
+ // Ensure CTRL/STAT register selected in DPBANKSEL
+ if (!swd_write_dp(DP_SELECT, 0)) {
+ return 0;
+ }
+
+ // Power up
+ if (!swd_write_dp(DP_CTRL_STAT, CSYSPWRUPREQ | CDBGPWRUPREQ)) {
+ return 0;
+ }
+
+ // Enable debug
+ if (!swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN)) {
+ return 0;
+ }
+
+ break;
+
+ case HALT:
+ if (!swd_init_debug()) {
+ return 0;
+ }
+
+ // Enable debug and halt the core (DHCSR <- 0xA05F0003)
+ if (!swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN | C_HALT)) {
+ return 0;
+ }
+
+ // Wait until core is halted
+ do {
+ if (!swd_read_word(DBG_HCSR, &val)) {
+ return 0;
+ }
+ } while ((val & S_HALT) == 0);
+ break;
+
+ case RUN:
+ if (!swd_write_word(DBG_HCSR, DBGKEY)) {
+ return 0;
+ }
+ swd_off();
+ break;
+
+ case POST_FLASH_RESET:
+ // This state should be handled in target_reset.c, nothing needs to be done here.
+ break;
+
+ default:
+ return 0;
+ }
+
+ return 1;
+}
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/interface/swd_host.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/interface/swd_host.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,78 @@
+/**
+ * @file swd_host.h
+ * @brief Host driver for accessing the DAP
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * Copyright 2019, Cypress Semiconductor Corporation
+ * or a subsidiary of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef SWDHOST_CM_H
+#define SWDHOST_CM_H
+
+#include "flash_blob.h"
+#include "target_family.h"
+#ifdef TARGET_MCU_CORTEX_A
+#include "debug_ca.h"
+#else
+#include "debug_cm.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ CONNECT_NORMAL,
+ CONNECT_UNDER_RESET,
+} SWD_CONNECT_TYPE;
+
+typedef enum {
+ FLASHALGO_RETURN_BOOL,
+ FLASHALGO_RETURN_POINTER
+} flash_algo_return_t;
+
+uint8_t swd_init(void);
+uint8_t swd_off(void);
+uint8_t swd_init_debug(void);
+uint8_t swd_clear_errors(void);
+uint8_t swd_read_dp(uint8_t adr, uint32_t *val);
+uint8_t swd_write_dp(uint8_t adr, uint32_t val);
+uint8_t swd_read_ap(uint32_t adr, uint32_t *val);
+uint8_t swd_write_ap(uint32_t adr, uint32_t val);
+uint8_t swd_read_word(uint32_t addr, uint32_t *val);
+uint8_t swd_write_word(uint32_t addr, uint32_t val);
+uint8_t swd_read_byte(uint32_t addr, uint8_t *val);
+uint8_t swd_write_byte(uint32_t addr, uint8_t val);
+uint8_t swd_read_memory(uint32_t address, uint8_t *data, uint32_t size);
+uint8_t swd_write_memory(uint32_t address, uint8_t *data, uint32_t size);
+uint8_t swd_read_core_register(uint32_t n, uint32_t *val);
+uint8_t swd_write_core_register(uint32_t n, uint32_t val);
+uint8_t swd_flash_syscall_exec(const program_syscall_t *sysCallParam, uint32_t entry, uint32_t arg1, uint32_t arg2, uint32_t arg3, uint32_t arg4, flash_algo_return_t return_type);
+uint8_t swd_set_target_state_hw(target_state_t state);
+uint8_t swd_set_target_state_sw(target_state_t state);
+uint8_t swd_transfer_retry(uint32_t req, uint32_t *data);
+void int2array(uint8_t *res, uint32_t data, uint8_t len);
+void swd_set_reset_connect(SWD_CONNECT_TYPE type);
+void swd_set_soft_reset(uint32_t soft_reset_type);
+uint8_t JTAG2SWD(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/interface/swd_host_ca.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/interface/swd_host_ca.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,969 @@
+/**
+ * @file swd_host.c
+ * @brief Implementation of swd_host.h
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * Copyright 2019, Cypress Semiconductor Corporation
+ * or a subsidiary of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifdef TARGET_MCU_CORTEX_A
+
+#include "cmsis_os2.h"
+#include "target_config.h"
+#include "swd_host.h"
+#include "debug_ca.h"
+#include "DAP_config.h"
+#include "DAP.h"
+#include "target_family.h"
+
+// Default NVIC and Core debug base addresses
+// TODO: Read these addresses from ROM.
+#define NVIC_Addr (0xe000e000)
+#define DBG_Addr (0xe000edf0)
+
+// AP CSW register, base value
+#define CSW_VALUE (0x80000000 | CSW_RESERVED | CSW_MSTRDBG | CSW_HPROT | CSW_DBGSTAT | CSW_PADDRINC)
+
+// SWD register access
+#define SWD_REG_AP (1)
+#define SWD_REG_DP (0)
+#define SWD_REG_R (1<<1)
+#define SWD_REG_W (0<<1)
+#define SWD_REG_ADR(a) (a & 0x0c)
+
+#define CMD_MRC (0xEE100E15) /* 1110 1110 0001 0000 RRRR 1110 0001 0101 */
+#define CMD_MCR (0xEE000E15) /* 1110 1110 0000 0000 RRRR 1110 0001 0101 */
+#define CMD_MSR (0xE12CF000) /* 1110 0001 0010 1100 1111 0000 0000 RRRR */
+#define CMD_MRS (0xE14F0000) /* 1110 0001 0100 1111 RRRR 0000 0000 0000 */
+#define CMD_MOV (0xE1A00000) /* 1110 0001 1010 0000 DDDD 0000 0000 RRRR */ /* D = distination */
+
+#define DBGDSCR_HALTED (0x00000001)
+
+#define SELECT_MEM (0x00000000) /* setting of SELECT access memmory */
+#define SELECT_DBG (0x01000000) /* setting of SELECT access Debug Register */
+
+#define MAX_SWD_RETRY 10
+#define MAX_TIMEOUT 100000 // Timeout for syscalls on target
+
+
+typedef struct {
+ uint32_t select;
+ uint32_t csw;
+} DAP_STATE;
+
+typedef struct {
+ uint32_t r[16];
+ uint32_t xpsr;
+} DEBUG_STATE;
+
+static DAP_STATE dap_state;
+static uint32_t soft_reset = SYSRESETREQ;
+static uint32_t select_state = SELECT_MEM;
+static volatile uint32_t swd_init_debug_flag = 0;
+
+/* Add static functions */
+static uint8_t swd_restart_req(void);
+static uint8_t swd_enable_debug(void);
+
+void swd_set_reset_connect(SWD_CONNECT_TYPE type)
+{
+}
+
+void int2array(uint8_t *res, uint32_t data, uint8_t len)
+{
+ uint8_t i = 0;
+
+ for (i = 0; i < len; i++) {
+ res[i] = (data >> 8 * i) & 0xff;
+ }
+}
+
+uint8_t swd_transfer_retry(uint32_t req, uint32_t *data)
+{
+ uint8_t i, ack;
+
+ for (i = 0; i < MAX_SWD_RETRY; i++) {
+ ack = SWD_Transfer(req, data);
+
+ // if ack != WAIT
+ if (ack != DAP_TRANSFER_WAIT) {
+ return ack;
+ }
+ }
+
+ return ack;
+}
+
+void swd_set_soft_reset(uint32_t soft_reset_type)
+{
+ soft_reset = soft_reset_type;
+}
+
+uint8_t swd_init(void)
+{
+ //TODO - DAP_Setup puts GPIO pins in a hi-z state which can
+ // cause problems on re-init. This needs to be investigated
+ // and fixed.
+ DAP_Setup();
+ PORT_SWD_SETUP();
+ return 1;
+}
+
+uint8_t swd_off(void)
+{
+ PORT_OFF();
+ return 1;
+}
+
+// Read debug port register.
+uint8_t swd_read_dp(uint8_t adr, uint32_t *val)
+{
+ uint32_t tmp_in;
+ uint8_t tmp_out[4];
+ uint8_t ack;
+ uint32_t tmp;
+ tmp_in = SWD_REG_DP | SWD_REG_R | SWD_REG_ADR(adr);
+ ack = swd_transfer_retry(tmp_in, (uint32_t *)tmp_out);
+ *val = 0;
+ tmp = tmp_out[3];
+ *val |= (tmp << 24);
+ tmp = tmp_out[2];
+ *val |= (tmp << 16);
+ tmp = tmp_out[1];
+ *val |= (tmp << 8);
+ tmp = tmp_out[0];
+ *val |= (tmp << 0);
+ return (ack == 0x01);
+}
+
+// Write debug port register
+uint8_t swd_write_dp(uint8_t adr, uint32_t val)
+{
+ uint32_t req;
+ uint8_t data[4];
+ uint8_t ack;
+
+ switch (adr) {
+ case DP_SELECT:
+ if (dap_state.select == val) {
+ return 1;
+ }
+
+ dap_state.select = val;
+ break;
+
+ default:
+ break;
+ }
+
+ req = SWD_REG_DP | SWD_REG_W | SWD_REG_ADR(adr);
+ int2array(data, val, 4);
+ ack = swd_transfer_retry(req, (uint32_t *)data);
+ return (ack == 0x01);
+}
+
+// Read access port register.
+uint8_t swd_read_ap(uint32_t adr, uint32_t *val)
+{
+ uint8_t tmp_in, ack;
+ uint8_t tmp_out[4];
+ uint32_t tmp;
+ uint32_t apsel = adr & 0xff000000;
+ uint32_t bank_sel = adr & APBANKSEL;
+
+ if (!swd_write_dp(DP_SELECT, apsel | bank_sel)) {
+ return 0;
+ }
+
+ tmp_in = SWD_REG_AP | SWD_REG_R | SWD_REG_ADR(adr);
+ // first dummy read
+ swd_transfer_retry(tmp_in, (uint32_t *)tmp_out);
+ ack = swd_transfer_retry(tmp_in, (uint32_t *)tmp_out);
+ *val = 0;
+ tmp = tmp_out[3];
+ *val |= (tmp << 24);
+ tmp = tmp_out[2];
+ *val |= (tmp << 16);
+ tmp = tmp_out[1];
+ *val |= (tmp << 8);
+ tmp = tmp_out[0];
+ *val |= (tmp << 0);
+ return (ack == 0x01);
+}
+
+// Write access port register
+uint8_t swd_write_ap(uint32_t adr, uint32_t val)
+{
+ uint8_t data[4];
+ uint8_t req, ack;
+ uint32_t apsel = adr & 0xff000000;
+ uint32_t bank_sel = adr & APBANKSEL;
+
+ if (!swd_write_dp(DP_SELECT, apsel | bank_sel)) {
+ return 0;
+ }
+
+ switch (adr) {
+ case AP_CSW:
+ if (dap_state.csw == val) {
+ return 1;
+ }
+
+ dap_state.csw = val;
+ break;
+
+ default:
+ break;
+ }
+
+ req = SWD_REG_AP | SWD_REG_W | SWD_REG_ADR(adr);
+ int2array(data, val, 4);
+
+ if (swd_transfer_retry(req, (uint32_t *)data) != 0x01) {
+ return 0;
+ }
+
+ req = SWD_REG_DP | SWD_REG_R | SWD_REG_ADR(DP_RDBUFF);
+ ack = swd_transfer_retry(req, NULL);
+ return (ack == 0x01);
+}
+
+uint8_t swd_ca_select_state(uint32_t addr) {
+ uint8_t tmp_in[4];
+ uint32_t work_select_state;
+
+ if ((DEBUG_REGSITER_BASE <= addr) && (addr <= DBGCID3)) {
+ work_select_state = SELECT_DBG;
+ } else {
+ work_select_state = SELECT_MEM;
+ }
+ if (select_state != work_select_state) {
+ // SELECT
+ select_state = work_select_state;
+ int2array(tmp_in, select_state, 4);
+ if (swd_transfer_retry(0x08, (uint32_t *)tmp_in) != 0x01) {
+ return 0;
+ }
+ }
+ return 1;
+}
+
+
+// Write 32-bit word aligned values to target memory using address auto-increment.
+// size is in bytes.
+static uint8_t swd_write_block(uint32_t address, uint8_t *data, uint32_t size)
+{
+ uint8_t tmp_in[4], req;
+ uint32_t size_in_words;
+ uint32_t i, ack = 0x01;
+ uint32_t *work_write_data;
+
+ if (size == 0) {
+ return 0;
+ }
+
+ size_in_words = size / 4;
+
+ // CSW register
+ if (!swd_write_ap(AP_CSW, CSW_VALUE | CSW_SIZE32)) {
+ return 0;
+ }
+
+ if (swd_ca_select_state(address) == 0) {
+ return 0;
+ }
+
+ // TAR write
+ req = SWD_REG_AP | SWD_REG_W | (1 << 2);
+ int2array(tmp_in, address, 4);
+
+ if (swd_transfer_retry(req, (uint32_t *)tmp_in) != 0x01) {
+ return 0;
+ }
+
+ // DRW write
+ req = SWD_REG_AP | SWD_REG_W | (3 << 2);
+ work_write_data = (uint32_t *)data;
+ for (i = 0; i < size_in_words; i++) {
+ int2array(tmp_in, *work_write_data, 4);
+ ack = swd_transfer_retry(req, (uint32_t *)tmp_in);
+ if (ack != 0x01) {
+ return 0;
+ }
+ work_write_data++;
+ }
+ return (ack == 0x01);
+}
+
+// Read target memory.
+static uint8_t swd_read_data(uint32_t addr, uint32_t *val)
+{
+ uint8_t tmp_in[4];
+ uint8_t tmp_out[4];
+ uint8_t req, ack;
+ uint32_t tmp;
+
+ if (swd_ca_select_state(addr) == 0) {
+ return 0;
+ }
+
+ // put addr in TAR register
+ int2array(tmp_in, addr, 4);
+ req = SWD_REG_AP | SWD_REG_W | (1 << 2);
+
+ if (swd_transfer_retry(req, (uint32_t *)tmp_in) != 0x01) {
+ return 0;
+ }
+
+ // read data
+ req = SWD_REG_AP | SWD_REG_R | (3 << 2);
+
+ if (swd_transfer_retry(req, (uint32_t *)tmp_out) != 0x01) {
+ return 0;
+ }
+
+ // dummy read
+ req = SWD_REG_DP | SWD_REG_R | SWD_REG_ADR(DP_RDBUFF);
+ ack = swd_transfer_retry(req, (uint32_t *)tmp_out);
+ *val = 0;
+ tmp = tmp_out[3];
+ *val |= (tmp << 24);
+ tmp = tmp_out[2];
+ *val |= (tmp << 16);
+ tmp = tmp_out[1];
+ *val |= (tmp << 8);
+ tmp = tmp_out[0];
+ *val |= (tmp << 0);
+ return (ack == 0x01);
+}
+
+// Write target memory.
+static uint8_t swd_write_data(uint32_t address, uint32_t data)
+{
+ uint8_t tmp_in[4];
+ uint8_t req, ack;
+
+ if (swd_ca_select_state(address) == 0) {
+ return 0;
+ }
+
+ // put addr in TAR register
+ int2array(tmp_in, address, 4);
+ req = SWD_REG_AP | SWD_REG_W | (1 << 2);
+
+ if (swd_transfer_retry(req, (uint32_t *)tmp_in) != 0x01) {
+ return 0;
+ }
+
+ // write data
+ int2array(tmp_in, data, 4);
+ req = SWD_REG_AP | SWD_REG_W | (3 << 2);
+ ack = swd_transfer_retry(req, (uint32_t *)tmp_in);
+
+ return (ack == 0x01) ? 1 : 0;
+}
+
+// Read 32-bit word from target memory.
+uint8_t swd_read_word(uint32_t addr, uint32_t *val)
+{
+ if (!swd_write_ap(AP_CSW, CSW_VALUE | CSW_SIZE32)) {
+ return 0;
+ }
+
+ if (!swd_read_data(addr, val)) {
+ return 0;
+ }
+
+ return 1;
+}
+
+// Write 32-bit word to target memory.
+uint8_t swd_write_word(uint32_t addr, uint32_t val)
+{
+ if (!swd_write_ap(AP_CSW, CSW_VALUE | CSW_SIZE32)) {
+ return 0;
+ }
+
+ if (!swd_write_data(addr, val)) {
+ return 0;
+ }
+
+ return 1;
+}
+
+// Read unaligned data from target memory.
+// size is in bytes.
+uint8_t swd_read_memory(uint32_t address, uint8_t *data, uint32_t size)
+{
+ uint32_t read_size;
+ uint32_t* read_data;
+
+ read_size = (size / 4);
+ read_data = (uint32_t*)data;
+ /* Write bytes until end */
+ while ((read_size > 0)) {
+ if (!swd_read_data(address, read_data)) {
+ return 0;
+ }
+ address+=4;
+ read_data++;
+ read_size--;
+ }
+
+ return 1;
+}
+
+// Write unaligned data to target memory.
+// size is in bytes.
+uint8_t swd_write_memory(uint32_t address, uint8_t *data, uint32_t size)
+{
+ uint32_t n;
+
+ while (size > 3) {
+ // Limit to auto increment page size
+ n = TARGET_AUTO_INCREMENT_PAGE_SIZE - (address & (TARGET_AUTO_INCREMENT_PAGE_SIZE - 1));
+ if (size < n) {
+ n = size & 0xFFFFFFFC; // Only count complete words remaining
+ }
+
+ if (!swd_write_block(address, data, n)) {
+ return 0;
+ }
+
+ address += n;
+ data += n;
+ size -= n;
+ }
+ /* Auto increment is end */
+ /* Return the CSW reg value to SIZE8 */
+ if (!swd_write_ap(AP_CSW, CSW_VALUE | CSW_SIZE8)) {
+ return 0;
+ }
+
+ return 1;
+}
+
+// Execute system call.
+static uint8_t swd_write_debug_state(DEBUG_STATE *state)
+{
+ uint32_t i, status;
+
+ if (!swd_write_dp(DP_SELECT, 0)) {
+ return 0;
+ }
+
+ // R0, R1, R2, R3
+ for (i = 0; i < 4; i++) {
+ if (!swd_write_core_register(i, state->r[i])) {
+ return 0;
+ }
+ }
+
+ // R9
+ if (!swd_write_core_register(9, state->r[9])) {
+ return 0;
+ }
+
+ // R13, R14
+ for (i = 13; i < 15; i++) {
+ if (!swd_write_core_register(i, state->r[i])) {
+ return 0;
+ }
+ }
+
+ // xPSR
+ /* xPSR write */
+ /* write PSR (write r6) */
+ if (!swd_write_core_register(6, state->xpsr)) {
+ return 0;
+ }
+ /* MSR (PSR <- r6) */
+ if (!swd_write_word(DBGITR, CMD_MSR | (6))) {
+ return 0;
+ }
+
+ /* R15(PC) */
+ /* MRC R7 */
+ if (!swd_write_core_register(7, state->r[15])) {
+ return 0;
+ }
+ /* MOV R15, R7 */
+ if (!swd_write_word(DBGITR, CMD_MOV | (15 << 12) | (7))) {
+ return 0;
+ }
+ if (!swd_restart_req()) {
+ return 0;
+ }
+
+ // check status
+ if (!swd_read_dp(DP_CTRL_STAT, &status)) {
+ return 0;
+ }
+
+ if (status & (STICKYERR | WDATAERR)) {
+ return 0;
+ }
+
+ return 1;
+}
+
+static uint8_t swd_restart_req(void) {
+ uint32_t val, i, timeout = MAX_TIMEOUT;
+ /* Clear ITRen */
+ if (!swd_read_word(DBGDSCR, &val)) {
+ return 0;
+ }
+ val = val & ~0x00002000;
+ if (!swd_write_word(DBGDSCR, val)) {
+ return 0;
+ }
+ for (i = 0; i < timeout; i++) {
+ /* read DBGDSCR */
+ if (!swd_read_word(DBGDSCR, &val)) {
+ return 0;
+ }
+ /* wait Clear UND_I, ADABORT_I, SDABORT_I[bit:8-6] and InstrCompl_I[bit24] set to 1 */
+ if ((val & 0x010001C0) == 0x01000000) {
+ break;
+ } else if (i == (timeout -1)) {
+ return 0;
+ }
+ }
+ /* DBGDRCR Restart req */
+ if (!swd_write_word(DBGDRCR, 0x00000002 )) {
+ return 0;
+ }
+ for (i = 0; i < timeout; i++) {
+ /* read DBGDSCR */
+ if (!swd_read_word(DBGDSCR, &val)) {
+ return 0;
+ }
+ if ((val & 0x00000002) == 0x00000002) {
+ /* restarted */
+ return 1;
+ }
+ }
+ return 0;
+}
+
+static uint8_t swd_enable_debug(void) {
+ uint32_t val;
+ if (!swd_read_word(DBGDSCR, &val)) {
+ return 0;
+ }
+ /* DBGDSCR ITRen = 1(ARM instruction enable) */
+ /* and ExtDCCmode = 01(stall mode) */
+ val = val | 0x00106000;
+ if (!swd_write_word(DBGDSCR, val)) {
+ return 0;
+ }
+ return 1;
+}
+
+uint8_t swd_read_core_register(uint32_t n, uint32_t *val)
+{
+ if (!swd_write_word(DBGITR, CMD_MCR | (n << 12))) {
+ return 0;
+ }
+
+ if (!swd_read_word(DBGDTRTX, val)){
+ return 0;
+ }
+
+ return 1;
+}
+
+uint8_t swd_write_core_register(uint32_t n, uint32_t val)
+{
+ if (!swd_write_word(DBGDTRRX, val)){
+ return 0;
+ }
+
+ /* Write MRC */
+ if (!swd_write_word(DBGITR, (CMD_MRC | (n << 12)))) {
+ return 0;
+ }
+
+ return 1;
+}
+
+static uint8_t swd_wait_until_halted(void)
+{
+ uint32_t val, i, timeout = MAX_TIMEOUT;
+ for (i = 0; i < timeout; i++) {
+ /* read DBGDSCR */
+ if (!swd_read_word(DBGDSCR, &val)) {
+ return 0;
+ }
+
+ if ((val & DBGDSCR_HALTED) == DBGDSCR_HALTED) {
+ return 1;
+ }
+ osDelay(1);
+ }
+
+ return 0;
+}
+
+uint8_t swd_flash_syscall_exec(const program_syscall_t *sysCallParam, uint32_t entry, uint32_t arg1, uint32_t arg2, uint32_t arg3, uint32_t arg4, flash_algo_return_t return_type)
+{
+ DEBUG_STATE state = {{0}, 0};
+ // Call flash algorithm function on target and wait for result.
+ state.r[0] = arg1; // R0: Argument 1
+ state.r[1] = arg2; // R1: Argument 2
+ state.r[2] = arg3; // R2: Argument 3
+ state.r[3] = arg4; // R3: Argument 4
+ state.r[9] = sysCallParam->static_base; // SB: Static Base
+ state.r[13] = sysCallParam->stack_pointer; // SP: Stack Pointer
+ state.r[14] = sysCallParam->breakpoint; // LR: Exit Point
+ state.r[15] = entry; // PC: Entry Point
+ state.xpsr = 0x00000000; // xPSR: T = 1, ISR = 0
+
+ if (!swd_write_debug_state(&state)) {
+ return 0;
+ }
+
+ if (!swd_wait_until_halted()) {
+ return 0;
+ }
+
+ if (!swd_enable_debug()) {
+ return 0;
+ }
+
+ if (!swd_read_core_register(0, &state.r[0])) {
+ return 0;
+ }
+
+ if ( return_type == FLASHALGO_RETURN_POINTER ) {
+ // Flash verify functions return pointer to byte following the buffer if successful.
+ if (state.r[0] != (arg1 + arg2)) {
+ return 0;
+ }
+ }
+ else {
+ // Flash functions return 0 if successful.
+ if (state.r[0] != 0) {
+ return 0;
+ }
+ }
+
+ return 1;
+}
+
+// SWD Reset
+static uint8_t swd_reset(void)
+{
+ uint8_t tmp_in[8];
+ uint8_t i = 0;
+
+ for (i = 0; i < 8; i++) {
+ tmp_in[i] = 0xff;
+ }
+
+ SWJ_Sequence(51, tmp_in);
+ return 1;
+}
+
+// SWD Switch
+static uint8_t swd_switch(uint16_t val)
+{
+ uint8_t tmp_in[2];
+ tmp_in[0] = val & 0xff;
+ tmp_in[1] = (val >> 8) & 0xff;
+ SWJ_Sequence(16, tmp_in);
+ return 1;
+}
+
+// SWD Read ID
+static uint8_t swd_read_idcode(uint32_t *id)
+{
+ uint8_t tmp_in[1];
+ uint8_t tmp_out[4];
+ tmp_in[0] = 0x00;
+ SWJ_Sequence(8, tmp_in);
+
+ if (swd_read_dp(0, (uint32_t *)tmp_out) != 0x01) {
+ return 0;
+ }
+
+ *id = (tmp_out[3] << 24) | (tmp_out[2] << 16) | (tmp_out[1] << 8) | tmp_out[0];
+ return 1;
+}
+
+
+uint8_t JTAG2SWD()
+{
+ uint32_t tmp = 0;
+
+ if (!swd_reset()) {
+ return 0;
+ }
+
+ if (!swd_switch(0xE79E)) {
+ return 0;
+ }
+
+ if (!swd_reset()) {
+ return 0;
+ }
+
+ if (!swd_read_idcode(&tmp)) {
+ return 0;
+ }
+
+ return 1;
+}
+
+uint8_t swd_init_debug(void)
+{
+ uint32_t tmp = 0;
+
+ if (swd_init_debug_flag != 0) {
+ return 1;
+ }
+ swd_init_debug_flag = 1;
+
+ // init dap state with fake values
+ dap_state.select = 0xffffffff;
+ dap_state.csw = 0xffffffff;
+ swd_init();
+ // call a target dependant function
+ // this function can do several stuff before really
+ // initing the debug
+ if (g_target_family && g_target_family->target_before_init_debug) {
+ g_target_family->target_before_init_debug();
+ }
+
+ if (!JTAG2SWD()) {
+ return 0;
+ }
+
+ if (!swd_write_dp(DP_ABORT, STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR)) {
+ return 0;
+ }
+
+ // Ensure CTRL/STAT register selected in DPBANKSEL
+ if (!swd_write_dp(DP_SELECT, 0)) {
+ return 0;
+ }
+
+ // Power up
+ if (!swd_write_dp(DP_CTRL_STAT, CSYSPWRUPREQ | CDBGPWRUPREQ)) {
+ return 0;
+ }
+
+ do {
+ if (!swd_read_dp(DP_CTRL_STAT, &tmp)) {
+ return 0;
+ }
+ } while ((tmp & (CDBGPWRUPACK | CSYSPWRUPACK)) != (CDBGPWRUPACK | CSYSPWRUPACK));
+
+ if (!swd_write_dp(DP_CTRL_STAT, CSYSPWRUPREQ | CDBGPWRUPREQ | TRNNORMAL | MASKLANE)) {
+ return 0;
+ }
+
+ // call a target dependant function:
+ // some target can enter in a lock state
+ // this function can unlock these targets
+ if (g_target_family && g_target_family->target_unlock_sequence) {
+ g_target_family->target_unlock_sequence();
+ }
+
+ if (!swd_write_dp(DP_SELECT, 0)) {
+ return 0;
+ }
+
+ return 1;
+}
+
+uint8_t swd_uninit_debug(void)
+{
+ return 1;
+}
+
+uint8_t swd_set_target_state_hw(target_state_t state)
+{
+ uint32_t val;
+ swd_init();
+
+ switch (state) {
+ case RESET_HOLD:
+ swd_set_target_reset(1);
+ break;
+
+ case RESET_RUN:
+ swd_set_target_reset(1);
+ osDelay(2);
+ swd_set_target_reset(0);
+ osDelay(2);
+ swd_off();
+ break;
+
+ case RESET_PROGRAM:
+ swd_set_target_reset(1);
+ osDelay(2);
+ swd_set_target_reset(0);
+ osDelay(2);
+
+ if (!swd_init_debug()) {
+ return 0;
+ }
+
+ if (!swd_enable_debug()) {
+ return 0;
+ }
+ /* DBGDRCR halt req*/
+ val = 0x00000001;
+ if (!swd_write_word(DBGDRCR, val )) {
+ return 0;
+ }
+ osDelay(2);
+ if (!swd_wait_until_halted()) {
+ return 0;
+ }
+
+ break;
+
+ case NO_DEBUG:
+ if (!swd_write_word(DBG_HCSR, DBGKEY)) {
+ return 0;
+ }
+
+ break;
+
+ case DEBUG:
+ if (!JTAG2SWD()) {
+ return 0;
+ }
+
+ if (!swd_write_dp(DP_ABORT, STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR)) {
+ return 0;
+ }
+
+ // Ensure CTRL/STAT register selected in DPBANKSEL
+ if (!swd_write_dp(DP_SELECT, 0)) {
+ return 0;
+ }
+
+ // Power up
+ if (!swd_write_dp(DP_CTRL_STAT, CSYSPWRUPREQ | CDBGPWRUPREQ)) {
+ return 0;
+ }
+
+ // Enable debug
+ if (!swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN)) {
+ return 0;
+ }
+
+ break;
+
+ default:
+ return 0;
+ }
+
+ return 1;
+}
+
+uint8_t swd_set_target_state_sw(target_state_t state)
+{
+ uint32_t val;
+ swd_init();
+ switch (state) {
+ case RESET_HOLD:
+ swd_set_target_reset(1);
+ break;
+
+ case RESET_RUN:
+ swd_set_target_reset(1);
+ osDelay(2);
+ swd_set_target_reset(0);
+ osDelay(2);
+ swd_off();
+ break;
+
+ case RESET_PROGRAM:
+ if (!swd_init_debug()) {
+ return 0;
+ }
+
+ // Enable debug and halt the core (DHCSR <- 0xA05F0003)
+ if (!swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN | C_HALT)) {
+ return 0;
+ }
+
+ // Wait until core is halted
+ do {
+ if (!swd_read_word(DBG_HCSR, &val)) {
+ return 0;
+ }
+ } while ((val & S_HALT) == 0);
+
+ // Enable halt on reset
+ if (!swd_write_word(DBG_EMCR, VC_CORERESET)) {
+ return 0;
+ }
+
+ // Perform a soft reset
+ if (!swd_write_word(NVIC_AIRCR, VECTKEY | soft_reset)) {
+ return 0;
+ }
+
+ break;
+
+ case NO_DEBUG:
+ if (!swd_write_word(DBG_HCSR, DBGKEY)) {
+ return 0;
+ }
+
+ break;
+
+ case DEBUG:
+ if (!JTAG2SWD()) {
+ return 0;
+ }
+
+ if (!swd_write_dp(DP_ABORT, STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR)) {
+ return 0;
+ }
+
+ // Ensure CTRL/STAT register selected in DPBANKSEL
+ if (!swd_write_dp(DP_SELECT, 0)) {
+ return 0;
+ }
+
+ // Power up
+ if (!swd_write_dp(DP_CTRL_STAT, CSYSPWRUPREQ | CDBGPWRUPREQ)) {
+ return 0;
+ }
+
+ // Enable debug
+ if (!swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN)) {
+ return 0;
+ }
+
+ break;
+
+ default:
+ return 0;
+ }
+
+ return 1;
+}
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/interface/target_flash.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/interface/target_flash.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,406 @@
+/**
+ * @file target_flash.c
+ * @brief Implementation of target_flash.h
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * Copyright 2019, Cypress Semiconductor Corporation
+ * or a subsidiary of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifdef DRAG_N_DROP_SUPPORT
+#include <string.h>
+
+#include "target_config.h"
+#include "gpio.h"
+#include "target_config.h"
+#include "intelhex.h"
+#include "swd_host.h"
+#include "flash_intf.h"
+#include "util.h"
+#include "settings.h"
+#include "target_family.h"
+#include "target_board.h"
+
+#define DEFAULT_PROGRAM_PAGE_MIN_SIZE (256u)
+
+typedef enum {
+ STATE_CLOSED,
+ STATE_OPEN,
+ STATE_ERROR
+} state_t;
+
+static error_t target_flash_init(void);
+static error_t target_flash_uninit(void);
+static error_t target_flash_program_page(uint32_t adr, const uint8_t *buf, uint32_t size);
+static error_t target_flash_erase_sector(uint32_t addr);
+static error_t target_flash_erase_chip(void);
+static uint32_t target_flash_program_page_min_size(uint32_t addr);
+static uint32_t target_flash_erase_sector_size(uint32_t addr);
+static uint8_t target_flash_busy(void);
+static error_t target_flash_set(uint32_t addr);
+
+static const flash_intf_t flash_intf = {
+ target_flash_init,
+ target_flash_uninit,
+ target_flash_program_page,
+ target_flash_erase_sector,
+ target_flash_erase_chip,
+ target_flash_program_page_min_size,
+ target_flash_erase_sector_size,
+ target_flash_busy,
+ target_flash_set,
+};
+
+static state_t state = STATE_CLOSED;
+
+const flash_intf_t *const flash_intf_target = &flash_intf;
+
+static flash_func_t last_flash_func = FLASH_FUNC_NOP;
+
+//saved flash algo
+static program_target_t * current_flash_algo = NULL;
+
+//saved default region for default flash algo
+static region_info_t * default_region = NULL;
+
+//saved flash start from flash algo
+static uint32_t flash_start = 0;
+
+static program_target_t * get_flash_algo(uint32_t addr)
+{
+ region_info_t * flash_region = g_board_info.target_cfg->flash_regions;
+
+ for (; flash_region->start != 0 || flash_region->end != 0; ++flash_region) {
+ if (addr >= flash_region->start && addr <= flash_region->end) {
+ flash_start = flash_region->start; //save the flash start
+ if (flash_region->flash_algo) {
+ return flash_region->flash_algo;
+ }else{
+ return NULL;
+ }
+ }
+ }
+
+ //could not find a flash algo for the region; use default
+ if (default_region) {
+ flash_start = default_region->start;
+ return default_region->flash_algo;
+ } else {
+ return NULL;
+ }
+}
+
+static error_t flash_func_start(flash_func_t func)
+{
+ program_target_t * flash = current_flash_algo;
+
+ if (last_flash_func != func)
+ {
+ // Finish the currently active function.
+ if (FLASH_FUNC_NOP != last_flash_func &&
+ ((flash->algo_flags & kAlgoSingleInitType) == 0 || FLASH_FUNC_NOP == func ) &&
+ 0 == swd_flash_syscall_exec(&flash->sys_call_s, flash->uninit, last_flash_func, 0, 0, 0, FLASHALGO_RETURN_BOOL)) {
+ return ERROR_UNINIT;
+ }
+
+ // Start a new function.
+ if (FLASH_FUNC_NOP != func &&
+ ((flash->algo_flags & kAlgoSingleInitType) == 0 || FLASH_FUNC_NOP == last_flash_func ) &&
+ 0 == swd_flash_syscall_exec(&flash->sys_call_s, flash->init, flash_start, 0, func, 0, FLASHALGO_RETURN_BOOL)) {
+ return ERROR_INIT;
+ }
+
+ last_flash_func = func;
+ }
+
+ return ERROR_SUCCESS;
+}
+
+static error_t target_flash_set(uint32_t addr)
+{
+ program_target_t * new_flash_algo = get_flash_algo(addr);
+ if (new_flash_algo == NULL) {
+ return ERROR_ALGO_MISSING;
+ }
+ if(current_flash_algo != new_flash_algo){
+ //run uninit to last func
+ error_t status = flash_func_start(FLASH_FUNC_NOP);
+ if (status != ERROR_SUCCESS) {
+ return status;
+ }
+ // Download flash programming algorithm to target
+ if (0 == swd_write_memory(new_flash_algo->algo_start, (uint8_t *)new_flash_algo->algo_blob, new_flash_algo->algo_size)) {
+ return ERROR_ALGO_DL;
+ }
+
+ current_flash_algo = new_flash_algo;
+
+ }
+ return ERROR_SUCCESS;
+}
+
+static error_t target_flash_init()
+{
+ if (g_board_info.target_cfg) {
+ last_flash_func = FLASH_FUNC_NOP;
+
+ current_flash_algo = NULL;
+
+ if (0 == target_set_state(RESET_PROGRAM)) {
+ return ERROR_RESET;
+ }
+
+ //get default region
+ region_info_t * flash_region = g_board_info.target_cfg->flash_regions;
+ for (; flash_region->start != 0 || flash_region->end != 0; ++flash_region) {
+ if (flash_region->flags & kRegionIsDefault) {
+ default_region = flash_region;
+ break;
+ }
+ }
+
+ state = STATE_OPEN;
+ return ERROR_SUCCESS;
+ } else {
+ return ERROR_FAILURE;
+ }
+
+}
+
+static error_t target_flash_uninit(void)
+{
+ if (g_board_info.target_cfg) {
+ error_t status = flash_func_start(FLASH_FUNC_NOP);
+ if (status != ERROR_SUCCESS) {
+ return status;
+ }
+ if (config_get_auto_rst()) {
+ // Resume the target if configured to do so
+ target_set_state(RESET_RUN);
+ } else {
+ // Leave the target halted until a reset occurs
+ target_set_state(RESET_PROGRAM);
+ }
+ // Check to see if anything needs to be done after programming.
+ // This is usually a no-op for most targets.
+ target_set_state(POST_FLASH_RESET);
+
+ state = STATE_CLOSED;
+ swd_off();
+ return ERROR_SUCCESS;
+ } else {
+ return ERROR_FAILURE;
+ }
+}
+
+static error_t target_flash_program_page(uint32_t addr, const uint8_t *buf, uint32_t size)
+{
+ if (g_board_info.target_cfg) {
+ error_t status = ERROR_SUCCESS;
+ program_target_t * flash = current_flash_algo;
+
+ if (!flash) {
+ return ERROR_INTERNAL;
+ }
+
+ // check if security bits were set
+ if (g_target_family && g_target_family->security_bits_set){
+ if (1 == g_target_family->security_bits_set(addr, (uint8_t *)buf, size)) {
+ return ERROR_SECURITY_BITS;
+ }
+ }
+
+ status = flash_func_start(FLASH_FUNC_PROGRAM);
+
+ if (status != ERROR_SUCCESS) {
+ return status;
+ }
+
+ while (size > 0) {
+ uint32_t write_size = MIN(size, flash->program_buffer_size);
+
+ // Write page to buffer
+ if (!swd_write_memory(flash->program_buffer, (uint8_t *)buf, write_size)) {
+ return ERROR_ALGO_DATA_SEQ;
+ }
+
+ // Run flash programming
+ if (!swd_flash_syscall_exec(&flash->sys_call_s,
+ flash->program_page,
+ addr,
+ write_size,
+ flash->program_buffer,
+ 0,
+ FLASHALGO_RETURN_BOOL)) {
+ return ERROR_WRITE;
+ }
+
+ if (config_get_automation_allowed()) {
+ // Verify data flashed if in automation mode
+ if (flash->verify != 0) {
+ status = flash_func_start(FLASH_FUNC_VERIFY);
+ if (status != ERROR_SUCCESS) {
+ return status;
+ }
+ flash_algo_return_t return_type;
+ if ((flash->algo_flags & kAlgoVerifyReturnsAddress) != 0) {
+ return_type = FLASHALGO_RETURN_POINTER;
+ } else {
+ return_type = FLASHALGO_RETURN_BOOL;
+ }
+ if (!swd_flash_syscall_exec(&flash->sys_call_s,
+ flash->verify,
+ addr,
+ write_size,
+ flash->program_buffer,
+ 0,
+ return_type)) {
+ return ERROR_WRITE_VERIFY;
+ }
+ } else {
+ while (write_size > 0) {
+ uint8_t rb_buf[16];
+ uint32_t verify_size = MIN(write_size, sizeof(rb_buf));
+ if (!swd_read_memory(addr, rb_buf, verify_size)) {
+ return ERROR_ALGO_DATA_SEQ;
+ }
+ if (memcmp(buf, rb_buf, verify_size) != 0) {
+ return ERROR_WRITE_VERIFY;
+ }
+ addr += verify_size;
+ buf += verify_size;
+ size -= verify_size;
+ write_size -= verify_size;
+ }
+ continue;
+ }
+ }
+ addr += write_size;
+ buf += write_size;
+ size -= write_size;
+
+ }
+
+ return ERROR_SUCCESS;
+
+ } else {
+ return ERROR_FAILURE;
+ }
+}
+
+static error_t target_flash_erase_sector(uint32_t addr)
+{
+ if (g_board_info.target_cfg) {
+ error_t status = ERROR_SUCCESS;
+ program_target_t * flash = current_flash_algo;
+
+ if (!flash) {
+ return ERROR_INTERNAL;
+ }
+
+ // Check to make sure the address is on a sector boundary
+ if ((addr % target_flash_erase_sector_size(addr)) != 0) {
+ return ERROR_ERASE_SECTOR;
+ }
+
+ status = flash_func_start(FLASH_FUNC_ERASE);
+
+ if (status != ERROR_SUCCESS) {
+ return status;
+ }
+
+ if (0 == swd_flash_syscall_exec(&flash->sys_call_s, flash->erase_sector, addr, 0, 0, 0, FLASHALGO_RETURN_BOOL)) {
+ return ERROR_ERASE_SECTOR;
+ }
+
+ return ERROR_SUCCESS;
+ } else {
+ return ERROR_FAILURE;
+ }
+}
+
+static error_t target_flash_erase_chip(void)
+{
+ if (g_board_info.target_cfg){
+ error_t status = ERROR_SUCCESS;
+ region_info_t * flash_region = g_board_info.target_cfg->flash_regions;
+
+ for (; flash_region->start != 0 || flash_region->end != 0; ++flash_region) {
+ program_target_t *new_flash_algo = get_flash_algo(flash_region->start);
+ if ((new_flash_algo != NULL) && ((new_flash_algo->algo_flags & kAlgoSkipChipErase) != 0)) {
+ // skip flash region
+ continue;
+ }
+ status = target_flash_set(flash_region->start);
+ if (status != ERROR_SUCCESS) {
+ return status;
+ }
+ status = flash_func_start(FLASH_FUNC_ERASE);
+ if (status != ERROR_SUCCESS) {
+ return status;
+ }
+ if (0 == swd_flash_syscall_exec(¤t_flash_algo->sys_call_s, current_flash_algo->erase_chip, 0, 0, 0, 0, FLASHALGO_RETURN_BOOL)) {
+ return ERROR_ERASE_ALL;
+ }
+ }
+
+ // Reset and re-initialize the target after the erase if required
+ if (g_board_info.target_cfg->erase_reset) {
+ status = target_flash_init();
+ }
+
+ return status;
+ } else {
+ return ERROR_FAILURE;
+ }
+}
+
+static uint32_t target_flash_program_page_min_size(uint32_t addr)
+{
+ if (g_board_info.target_cfg){
+ uint32_t size = DEFAULT_PROGRAM_PAGE_MIN_SIZE;
+ if (size > target_flash_erase_sector_size(addr)) {
+ size = target_flash_erase_sector_size(addr);
+ }
+ return size;
+ } else {
+ return 0;
+ }
+}
+
+static uint32_t target_flash_erase_sector_size(uint32_t addr)
+{
+ if (g_board_info.target_cfg){
+ if(g_board_info.target_cfg->sector_info_length > 0) {
+ int sector_index = g_board_info.target_cfg->sector_info_length - 1;
+ for (; sector_index >= 0; sector_index--) {
+ if (addr >= g_board_info.target_cfg->sectors_info[sector_index].start) {
+ return g_board_info.target_cfg->sectors_info[sector_index].size;
+ }
+ }
+ }
+ //sector information should be in sector_info
+ util_assert(0);
+ return 0;
+ } else {
+ return 0;
+ }
+}
+
+static uint8_t target_flash_busy(void){
+ return (state == STATE_OPEN);
+}
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/interface/tasks.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/interface/tasks.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,48 @@
+/**
+ * @file tasks.h
+ * @brief Macros for configuring the run time tasks
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef TASK_H
+#define TASK_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NO_TIMEOUT (0xffff)
+
+#define LOWEST_PRIORITY (1) /* Priority 0 is reserved for the RTX idle task */
+#define HIGHEST_PRIORITY (254) /* Priority 255 is reserved by RTX */
+
+#define MAIN_TASK_PRIORITY (10)
+#define TIMER_TASK_PRIORITY (11)
+#define TIMER_TASK_30_PRIORITY (TIMER_TASK_PRIORITY)
+
+// trouble here is that reset for different targets is implemented differently so all targets
+// have to use the largest stack or these have to be defined in multiple places... Not ideal
+// may want to move away from threads for some of these behaviours to optimize mempory usage (RAM)
+#define TIMER_TASK_30_STACK (136)
+#define MAIN_TASK_STACK (800)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/sdk_stub.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/sdk_stub.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,25 @@
+/**
+ * @file sdk_stub.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+__weak void sdk_init()
+{
+ // Do nothing
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/settings/settings.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/settings/settings.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,244 @@
+/**
+ * @file settings.c
+ * @brief Implementation of settings.h
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * Copyright 2019, Cypress Semiconductor Corporation
+ * or a subsidiary of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+
+#include "settings.h"
+#include "target_config.h"
+#include "compiler.h"
+#include "cortex_m.h"
+#include "daplink.h"
+
+// 'kvld' in hex - key valid
+#define CFG_KEY 0x6b766c64
+#define SECTOR_BUFFER_SIZE 16
+
+// For generating hexdumps on faults
+#define ALLOWED_HEXDUMP 16
+
+// WARNING - THIS STRUCTURE RESIDES IN RAM STORAGE!
+// Be careful with changes:
+// -Only add new members to end end of this structure
+// -Do not change the order of members in this structure
+// -Structure must remain packed so no padding bytes are added
+typedef struct __attribute__((__packed__)) cfg_ram {
+ uint32_t key; // Magic key to indicate a valid record
+ uint16_t size; // Offset of the last member from the start
+
+ // Configurable values
+ uint8_t hold_in_bl;
+ char assert_file_name[64 + 1];
+ uint16_t assert_line;
+ uint8_t assert_source;
+
+ // Additional debug information on faults
+ uint8_t valid_dumps;
+ uint32_t hexdump[ALLOWED_HEXDUMP]; //Alignments checked
+
+ // Disable msd support
+ uint8_t disable_msd;
+
+ //Add new entries from here
+ uint8_t page_erase_enable;
+} cfg_ram_t;
+
+// Configuration RAM
+static cfg_ram_t config_ram __attribute__((section("cfgram"), zero_init));
+// Ram copy of RAM config
+static cfg_ram_t config_ram_copy;
+
+void config_init()
+{
+ uint32_t new_size;
+ // Initialize RAM copy
+ memset(&config_ram_copy, 0, sizeof(config_ram_copy));
+ // Read settings from RAM if the key is valid
+ new_size = sizeof(config_ram);
+
+ if (CFG_KEY == config_ram.key) {
+ uint32_t size = MIN(config_ram.size, sizeof(config_ram));
+ new_size = MAX(config_ram.size, sizeof(config_ram));
+ memcpy(&config_ram_copy, (void *)&config_ram, size);
+ config_ram_copy.assert_file_name[sizeof(config_ram_copy.assert_file_name) - 1] = 0;
+ }
+
+ // Initialize RAM
+ memset((void *)&config_ram, 0, sizeof(config_ram));
+ config_ram.key = CFG_KEY;
+ config_ram.size = new_size;
+ // Copy assert info back over (must be explicitly cleared)
+ memcpy(config_ram.assert_file_name,
+ config_ram_copy.assert_file_name,
+ sizeof(config_ram_copy.assert_file_name));
+ config_ram.assert_line = config_ram_copy.assert_line;
+ config_ram.assert_source = config_ram_copy.assert_source;
+ config_ram.valid_dumps = config_ram_copy.valid_dumps;
+ memcpy(config_ram.hexdump, config_ram_copy.hexdump, sizeof(config_ram_copy.hexdump[0]) * config_ram_copy.valid_dumps);
+ config_ram.disable_msd = config_ram_copy.disable_msd;
+ config_ram.page_erase_enable = config_ram_copy.page_erase_enable;
+ config_rom_init();
+}
+
+void config_ram_set_hold_in_bl(bool hold)
+{
+ config_ram.hold_in_bl = hold;
+}
+
+void config_ram_set_assert(const char *file, uint16_t line)
+{
+ // Initialize
+ uint32_t file_name_size = strlen(file) + 1;
+ const char *start;
+ uint32_t assert_buf_size = sizeof(config_ram.assert_file_name);
+ uint32_t copy_size;
+ memset(config_ram.assert_file_name, 0, sizeof(config_ram.assert_file_name));
+
+ // Determine size to copy
+ if (file_name_size <= assert_buf_size) {
+ start = file;
+ copy_size = file_name_size;
+ } else {
+ start = &file[file_name_size - assert_buf_size];
+ copy_size = assert_buf_size;
+ }
+
+ // Write to ram
+ memcpy(config_ram.assert_file_name, start, copy_size);
+ config_ram.assert_line = line;
+
+ if (daplink_is_bootloader()) {
+ config_ram.assert_source = ASSERT_SOURCE_BL;
+ } else if (daplink_is_interface()) {
+ config_ram.assert_source = ASSERT_SOURCE_APP;
+ } else {
+ config_ram.assert_source = ASSERT_SOURCE_NONE;
+ }
+}
+
+void config_ram_clear_assert()
+{
+ memset(config_ram.assert_file_name, 0, sizeof(config_ram.assert_file_name));
+ config_ram.assert_line = 0;
+ config_ram.valid_dumps = 0;
+}
+
+bool config_ram_get_hold_in_bl()
+{
+ return config_ram.hold_in_bl;
+}
+
+bool config_ram_get_initial_hold_in_bl()
+{
+ return config_ram_copy.hold_in_bl;
+}
+
+bool config_ram_get_assert(char *buf, uint16_t buf_size, uint16_t *line, assert_source_t *source)
+{
+ // Initialize
+ const char *start;
+ uint32_t copy_size;
+ uint32_t assert_size = strlen(config_ram.assert_file_name) + 1;
+
+ if (0 != buf) {
+ memset(buf, 0, buf_size);
+ }
+
+ if (0 != line) {
+ *line = 0;
+ }
+
+ if (0 != source) {
+ *source = ASSERT_SOURCE_NONE;
+ }
+
+ // If the string is empty then there is no assert
+ if (0 == config_ram.assert_file_name[0]) {
+ return false;
+ }
+
+ // Determine size to copy
+ if (assert_size <= buf_size) {
+ start = config_ram.assert_file_name;
+ copy_size = assert_size;
+ } else {
+ start = &config_ram.assert_file_name[assert_size - buf_size];
+ copy_size = buf_size;
+ }
+
+ // Copy data over
+ if (0 != buf) {
+ *line = config_ram.assert_line;
+ }
+
+ if (0 != line) {
+ memcpy(buf, start, copy_size);
+ }
+
+ if (0 != source) {
+ *source = (assert_source_t)config_ram.assert_source;
+ }
+
+ return true;
+}
+
+uint8_t config_ram_add_hexdump(uint32_t hexdump)
+{
+ if (config_ram.valid_dumps >= ALLOWED_HEXDUMP) {
+ return 0;
+ }
+
+ //alignment is maintained here
+ config_ram.hexdump[config_ram.valid_dumps++] = hexdump;
+ return config_ram.valid_dumps;
+}
+
+uint8_t config_ram_get_hexdumps(uint32_t **hexdumps)
+{
+ if (config_ram.valid_dumps == 0) {
+ return 0;
+ }
+
+ //prevent memcopy check alignment
+ *hexdumps = config_ram.hexdump;
+ return config_ram.valid_dumps;
+}
+
+void config_ram_set_disable_msd(bool disable_msd)
+{
+ config_ram.disable_msd = disable_msd;
+}
+
+uint8_t config_ram_get_disable_msd(void)
+{
+ return config_ram.disable_msd;
+}
+
+void config_ram_set_page_erase(bool page_erase_enable)
+{
+ config_ram.page_erase_enable = page_erase_enable;
+}
+
+bool config_ram_get_page_erase(void)
+{
+ return config_ram.page_erase_enable;
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/settings/settings.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/settings/settings.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,70 @@
+/**
+ * @file settings.h
+ * @brief Access to read user configuration settings
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * Copyright 2019, Cypress Semiconductor Corporation
+ * or a subsidiary of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef SETTINGS_H
+#define SETTINGS_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ASSERT_SOURCE_NONE = 0,
+ ASSERT_SOURCE_BL = 1,
+ ASSERT_SOURCE_APP = 2
+} assert_source_t;
+
+void config_init(void);
+
+// Get/set settings residing in flash
+void config_set_auto_rst(bool on);
+void config_set_automation_allowed(bool on);
+void config_set_overflow_detect(bool on);
+bool config_get_auto_rst(void);
+bool config_get_automation_allowed(void);
+bool config_get_overflow_detect(void);
+
+// Get/set settings residing in shared ram
+void config_ram_set_hold_in_bl(bool hold);
+void config_ram_set_assert(const char *file, uint16_t line);
+void config_ram_clear_assert(void);
+bool config_ram_get_hold_in_bl(void);
+bool config_ram_get_initial_hold_in_bl(void);
+bool config_ram_get_assert(char *buf, uint16_t buf_size, uint16_t *line, assert_source_t *source);
+uint8_t config_ram_add_hexdump(uint32_t hexdump);
+uint8_t config_ram_get_hexdumps(uint32_t **hexdumps);
+void config_ram_set_disable_msd(bool disable_msd);
+uint8_t config_ram_get_disable_msd(void);
+void config_ram_set_page_erase(bool page_erase_enable);
+bool config_ram_get_page_erase(void);
+
+// Private - should only be called from settings.c
+void config_rom_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/settings/settings_rom.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/settings/settings_rom.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,179 @@
+/**
+ * @file settings_rom.c
+ * @brief Implementation of settings.h
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+
+#include "settings.h"
+#include "target_config.h"
+#include "compiler.h"
+#include "cortex_m.h"
+#include "FlashPrg.h"
+
+// 'kvld' in hex - key valid
+#define CFG_KEY 0x6b766c64
+#define SECTOR_BUFFER_SIZE 16
+
+// WARNING - THIS STRUCTURE RESIDES IN NON-VOLATILE STORAGE!
+// Be careful with changes:
+// -Only add new members to end end of this structure
+// -Do not change the order of members in this structure
+// -Structure must remain packed so no padding bytes are added
+typedef struct __attribute__((__packed__)) cfg_setting {
+ uint32_t key; // Magic key to indicate a valid record
+ uint16_t size; // Size of cfg_setting_t
+
+ // Configurable values
+ uint8_t auto_rst;
+ uint8_t automation_allowed;
+ uint8_t overflow_detect;
+
+ // Add new members here
+
+} cfg_setting_t;
+
+// Make sure FORMAT in generate_config.py is updated if size changes
+COMPILER_ASSERT(sizeof(cfg_setting_t) == 9);
+
+// Sector buffer must be as big or bigger than settings
+COMPILER_ASSERT(sizeof(cfg_setting_t) < SECTOR_BUFFER_SIZE);
+// Sector buffer must be a multiple of 4 bytes at least.
+// ProgramPage for some interfaces, like the k20dx, require that
+// the data is a multiple of 4 bytes, otherwise programming will
+// fail. Assert 8 byte alignement just to be safe.
+COMPILER_ASSERT(SECTOR_BUFFER_SIZE % 8 == 0);
+
+// Configuration ROM
+static volatile const cfg_setting_t config_rom __attribute__((section("cfgrom"), zero_init));
+// Ram copy of ROM config
+static cfg_setting_t config_rom_copy;
+
+// Configuration defaults in flash
+static const cfg_setting_t config_default = {
+ .auto_rst = 1,
+ .automation_allowed = 1,
+ .overflow_detect = 1,
+};
+
+// Buffer for data to flash
+static uint32_t write_buffer[SECTOR_BUFFER_SIZE / 4];
+
+// Check if the configuration in flash needs to be updated
+static bool config_needs_update()
+{
+ // Update if the key is invalid
+ if (CFG_KEY != config_rom.key) {
+ return true;
+ }
+
+ // Update if the config key is valid but
+ // has a smaller size.
+ if (config_rom.size < sizeof(config_rom)) {
+ return true;
+ }
+
+ // The config is valid and has the right
+ // size so it does not need to be updated
+ return false;
+}
+
+// Reprogram the new settings if flash writing is allowed
+static void program_cfg(cfg_setting_t *new_cfg)
+{
+ uint32_t status;
+ uint32_t addr;
+ cortex_int_state_t state;
+ addr = (uint32_t)&config_rom;
+ state = cortex_int_get_and_disable();
+ status = EraseSector(addr);
+ cortex_int_restore(state);
+
+ if (status != 0) {
+ return;
+ }
+
+ memset(write_buffer, 0xFF, sizeof(write_buffer));
+ memcpy(write_buffer, new_cfg, sizeof(cfg_setting_t));
+ state = cortex_int_get_and_disable();
+ status = ProgramPage(addr, sizeof(write_buffer), write_buffer);
+ cortex_int_restore(state);
+
+ if (0 != status) {
+ return;
+ }
+}
+
+void config_rom_init()
+{
+ Init(0, 0, 0);
+ // Fill in the ram copy with the defaults
+ memcpy(&config_rom_copy, &config_default, sizeof(config_rom_copy));
+
+ // Read settings from flash if the key is valid
+ if (CFG_KEY == config_rom.key) {
+ uint32_t size = MIN(config_rom.size, sizeof(config_rom));
+ memcpy(&config_rom_copy, (void *)&config_rom, size);
+ }
+
+ // Fill in special values
+ config_rom_copy.key = CFG_KEY;
+ config_rom_copy.size = sizeof(config_rom);
+
+ // Write settings back to flash if they are out of date
+ // Note - program_cfg only programs data in bootloader mode
+ if (config_needs_update()) {
+ // Program with defaults if none are set
+ program_cfg(&config_rom_copy);
+ }
+}
+
+
+void config_set_auto_rst(bool on)
+{
+ config_rom_copy.auto_rst = on;
+ program_cfg(&config_rom_copy);
+}
+
+void config_set_automation_allowed(bool on)
+{
+ config_rom_copy.automation_allowed = on;
+ program_cfg(&config_rom_copy);
+}
+
+void config_set_overflow_detect(bool on)
+{
+ config_rom_copy.overflow_detect = on;
+ program_cfg(&config_rom_copy);
+}
+
+bool config_get_auto_rst()
+{
+ return config_rom_copy.auto_rst;
+}
+
+bool config_get_automation_allowed(void)
+{
+ return config_rom_copy.automation_allowed;
+}
+
+bool config_get_overflow_detect()
+{
+ return config_rom_copy.overflow_detect;
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/settings/settings_rom_stub.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/settings/settings_rom_stub.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,57 @@
+/**
+ * @file settings_rom_stub.c
+ * @brief Implementation of settings.h
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "settings.h"
+
+void config_rom_init()
+{
+ // Do nothing
+}
+
+void config_set_auto_rst(bool on)
+{
+ // Do nothing
+}
+
+void config_set_automation_allowed(bool on)
+{
+ // Do nothing
+}
+
+void config_set_overflow_detect(bool on)
+{
+ // Do nothing
+}
+
+bool config_get_auto_rst()
+{
+ return false;
+}
+
+bool config_get_automation_allowed()
+{
+ return true;
+}
+
+bool config_get_overflow_detect()
+{
+ return false;
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/usb2uart/usbd_user_cdc_acm.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/usb2uart/usbd_user_cdc_acm.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,193 @@
+/**
+ * @file usbd_user_cdc_acm.c
+ * @brief implementation of USB CDC ACM middleware
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "cmsis_os2.h"
+#include "rl_usb.h"
+#include "main.h"
+#include "uart.h"
+#ifdef DRAG_N_DROP_SUPPORT
+#include "flash_intf.h"
+#endif
+#include "target_family.h"
+
+UART_Configuration UART_Config;
+
+/** @brief Vitual COM Port initialization
+ *
+ * The function inititalizes the hardware resources of the port used as
+ * the Virtual COM Port.
+ *
+ * @return 0 Function failed.
+ * @return 1 Function succeeded.
+ */
+int32_t USBD_CDC_ACM_PortInitialize(void)
+{
+ uart_initialize();
+ main_cdc_send_event();
+ return 1;
+}
+
+/** @brief Vitual COM Port uninitialization
+ *
+ * The function uninititalizes/releases the hardware resources of the port used
+ * as the Virtual COM Port.
+ *
+ * @return 0 Function failed.
+ * @return 1 Function succeeded.
+ */
+int32_t USBD_CDC_ACM_PortUninitialize(void)
+{
+ uart_uninitialize();
+ return 1;
+}
+
+/** @brief Vitual COM Port reset
+ *
+ * The function resets the internal states of the port used
+ * as the Virtual COM Port.
+ *
+ * @return 0 Function failed.
+ * @return 1 Function succeeded.
+ */
+int32_t USBD_CDC_ACM_PortReset(void)
+{
+ uart_reset();
+ return 1;
+}
+
+/** @brief Virtual COM Port change communication settings
+ *
+ * The function changes communication settings of the port used as the
+ * Virtual COM Port.
+ *
+ * @param [in] line_coding Pointer to the loaded CDC_LINE_CODING structure.
+ * @return 0 Function failed.
+ * @return 1 Function succeeded.
+ */
+int32_t USBD_CDC_ACM_PortSetLineCoding(CDC_LINE_CODING *line_coding)
+{
+ UART_Config.Baudrate = line_coding->dwDTERate;
+ UART_Config.DataBits = (UART_DataBits) line_coding->bDataBits;
+ UART_Config.Parity = (UART_Parity) line_coding->bParityType;
+ UART_Config.StopBits = (UART_StopBits) line_coding->bCharFormat;
+ UART_Config.FlowControl = UART_FLOW_CONTROL_NONE;
+ return uart_set_configuration(&UART_Config);
+}
+
+/** @brief Vitual COM Port retrieve communication settings
+ *
+ * The function retrieves communication settings of the port used as the
+ * Virtual COM Port.
+ *
+ * @param [in] line_coding Pointer to the CDC_LINE_CODING structure.
+ * @return 0 Function failed.
+ * @return 1 Function succeeded.
+ */
+int32_t USBD_CDC_ACM_PortGetLineCoding(CDC_LINE_CODING *line_coding)
+{
+ line_coding->dwDTERate = UART_Config.Baudrate;
+ line_coding->bDataBits = UART_Config.DataBits;
+ line_coding->bParityType = UART_Config.Parity;
+ line_coding->bCharFormat = UART_Config.StopBits;
+ return (1);
+}
+
+static U32 start_break_time = 0;
+int32_t USBD_CDC_ACM_SendBreak(uint16_t dur)
+{
+ uint32_t end_break_time;
+#ifdef DRAG_N_DROP_SUPPORT
+ if (!flash_intf_target->flash_busy())
+#endif
+ { //added checking if flashing on target is in progress
+ // reset and send the unique id over CDC
+ if (dur != 0) {
+ start_break_time = osKernelGetSysTimerCount();
+ target_set_state(RESET_HOLD);
+ } else {
+ end_break_time = osKernelGetSysTimerCount();
+
+ // long reset -> send uID over serial (300 -> break > 3s)
+ if ((end_break_time - start_break_time) >= (300)) {
+ main_reset_target(1);
+ } else {
+ main_reset_target(0);
+ }
+ }
+ }
+ return (1);
+}
+
+/** @brief Virtual COM Port set control line state
+ *
+ * The function sets control line state on the port used as the
+ * Virtual COM Port.
+ *
+ * @param [in] ctrl_bmp Control line settings
+ * bitmap (0. bit - DTR state, 1. bit - RTS state).
+ * @return 0 Function failed.
+ * @return 1 Function succeeded.
+ */
+int32_t USBD_CDC_ACM_PortSetControlLineState(uint16_t ctrl_bmp)
+{
+ return (1);
+}
+
+void cdc_process_event()
+{
+ int32_t len_data = 0;
+ uint8_t data[64];
+
+ len_data = USBD_CDC_ACM_DataFree();
+
+ if (len_data > sizeof(data)) {
+ len_data = sizeof(data);
+ }
+
+ if (len_data) {
+ len_data = uart_read_data(data, len_data);
+ }
+
+ if (len_data) {
+ if (USBD_CDC_ACM_DataSend(data , len_data)) {
+ main_blink_cdc_led(MAIN_LED_FLASH);
+ }
+ }
+
+ len_data = uart_write_free();
+
+ if (len_data > sizeof(data)) {
+ len_data = sizeof(data);
+ }
+
+ if (len_data) {
+ len_data = USBD_CDC_ACM_DataRead(data, len_data);
+ }
+
+ if (len_data) {
+ if (uart_write_data(data, len_data)) {
+ main_blink_cdc_led(MAIN_LED_FLASH);
+ }
+ }
+
+ // Always process events
+ main_cdc_send_event();
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/util.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/util.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,160 @@
+/**
+ * @file util.c
+ * @brief Implementation of util.h
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+
+#include "util.h"
+#include "settings.h"
+#include "cortex_m.h"
+
+//remove dependency from vfs_manager
+__attribute__((weak)) void vfs_mngr_fs_remount(void) {}
+
+uint32_t util_write_hex8(char *str, uint8_t value)
+{
+ static const char nybble_chars[] = "0123456789abcdef";
+ *(str + 0) = nybble_chars[(value >> 4) & 0x0F ];
+ *(str + 1) = nybble_chars[(value >> 0) & 0x0F ];
+ return 2;
+}
+
+uint32_t util_write_hex16(char *str, uint16_t value)
+{
+ uint32_t pos = 0;
+ pos += util_write_hex8(str + pos, (value >> 8) & 0xFF);
+ pos += util_write_hex8(str + pos, (value >> 0) & 0xFF);
+ return pos;
+}
+
+uint32_t util_write_hex32(char *str, uint32_t value)
+{
+ uint32_t pos = 0;
+ pos += util_write_hex8(str + pos, (value >> 0x18) & 0xFF);
+ pos += util_write_hex8(str + pos, (value >> 0x10) & 0xFF);
+ pos += util_write_hex8(str + pos, (value >> 0x08) & 0xFF);
+ pos += util_write_hex8(str + pos, (value >> 0x00) & 0xFF);
+ return pos;
+}
+
+uint32_t util_write_uint32(char *str, uint32_t value)
+{
+ uint32_t temp_val;
+ uint64_t digits;
+ uint32_t i;
+ // Count the number of digits
+ digits = 0;
+ temp_val = value;
+
+ while (temp_val > 0) {
+ temp_val /= 10;
+ digits += 1;
+ }
+
+ if (digits <= 0) {
+ digits = 1;
+ }
+
+ // Write the number
+ for (i = 0; i < digits; i++) {
+ str[digits - i - 1] = '0' + (value % 10);
+ value /= 10;
+ }
+
+ return digits;
+}
+
+uint32_t util_write_uint32_zp(char *str, uint32_t value, uint16_t total_size)
+{
+ uint32_t size;
+ // Get the size of value
+ size = util_write_uint32(str, value);
+
+ if (size >= total_size) {
+ return size;
+ }
+
+ // Zero fill
+ memset(str, '0', total_size);
+ // Write value
+ util_write_uint32(str + (total_size - size), value);
+ return total_size;
+}
+
+uint32_t util_write_string(char *str, const char *data)
+{
+ uint32_t pos = 0;
+
+ while (0 != data[pos]) {
+ str[pos] = data[pos];
+ pos++;
+ }
+
+ return pos;
+}
+
+uint32_t util_div_round_up(uint32_t dividen, uint32_t divisor)
+{
+ return (dividen + divisor - 1) / divisor;
+}
+
+uint32_t util_div_round_down(uint32_t dividen, uint32_t divisor)
+{
+ return dividen / divisor;
+}
+
+uint32_t util_div_round(uint32_t dividen, uint32_t divisor)
+{
+ return (dividen + divisor / 2) / divisor;
+}
+
+void _util_assert(bool expression, const char *filename, uint16_t line)
+{
+ bool assert_set;
+ cortex_int_state_t int_state;
+
+ if (expression) {
+ return;
+ }
+
+ int_state = cortex_int_get_and_disable();
+ // Only write the assert if there is not already one
+ assert_set = config_ram_get_assert(0, 0, 0, 0);
+
+ if (!assert_set) {
+ config_ram_set_assert(filename, line);
+ }
+
+ cortex_int_restore(int_state);
+
+ // Start a remount if this is the first assert
+ // Do not call vfs_mngr_fs_remount from an ISR!
+ if (!assert_set && !cortex_in_isr()) {
+ vfs_mngr_fs_remount();
+ }
+}
+
+void util_assert_clear()
+{
+ cortex_int_state_t int_state;
+ int_state = cortex_int_get_and_disable();
+ config_ram_clear_assert();
+ cortex_int_restore(int_state);
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/util.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/util.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,84 @@
+/**
+ * @file util.h
+ * @brief useful things
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2020, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef UTIL_H
+#define UTIL_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+// Protect commonly-defined macros with ifdefs, to prevent conflicts if redefined
+// in imported sources (mostly vendor SDKs).
+
+#if !defined(ARRAY_SIZE)
+//! @brief Get number of elements in the array.
+#define ARRAY_SIZE(array) (sizeof(array) / sizeof(array[0]))
+#endif
+
+#if !defined(MIN)
+#define MIN(a,b) ((a) < (b) ? (a) : (b))
+#endif
+
+#if !defined(MAX)
+#define MAX(a,b) ((a) > (b) ? (a) : (b))
+#endif
+
+#define MB(size) ((size) * 1024 * 1024)
+
+#define KB(size) ((size) * 1024)
+
+#define ROUND_UP(value, boundary) ((value) + ((boundary) - (value)) % (boundary))
+
+#define ROUND_DOWN(value, boundary) ((value) - ((value) % (boundary)))
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Write the value to the address specified and return the size
+uint32_t util_write_hex8(char *str, uint8_t value);
+uint32_t util_write_hex16(char *str, uint16_t value);
+uint32_t util_write_hex32(char *str, uint32_t value);
+uint32_t util_write_uint32(char *str, uint32_t value);
+uint32_t util_write_uint32(char *str, uint32_t value);
+uint32_t util_write_uint32_zp(char *str, uint32_t value, uint16_t total_size);
+uint32_t util_write_string(char *str, const char *data);
+
+uint32_t util_div_round_up(uint32_t dividen, uint32_t divisor);
+uint32_t util_div_round_down(uint32_t dividen, uint32_t divisor);
+uint32_t util_div_round(uint32_t dividen, uint32_t divisor);
+
+#if !(defined(DAPLINK_NO_ASSERT_FILENAMES) && defined(DAPLINK_BL))
+// With the filename enabled.
+#define util_assert(expression) _util_assert((expression), __FILE__, __LINE__)
+#else
+// Filename disabled to save code size.
+#define util_assert(expression) _util_assert((expression), "(file)", __LINE__)
+#endif
+void _util_assert(bool expression, const char *filename, uint16_t line);
+
+void util_assert_clear(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/validation.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/validation.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,89 @@
+/**
+ * @file validation.c
+ * @brief Implementation of validation.h
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+#include "validation.h"
+#include "target_config.h"
+#include "target_family.h"
+#include "target_board.h"
+
+static inline uint32_t test_range(const uint32_t test, const uint32_t min, const uint32_t max)
+{
+ return ((test < min) || (test > max)) ? 0 : 1;
+}
+
+uint8_t validate_bin_nvic(const uint8_t *buf)
+{
+ if (g_target_family && g_target_family->validate_bin_nvic) {
+ return g_target_family && g_target_family->validate_bin_nvic(buf);
+ } else if (g_board_info.target_cfg) {
+ uint32_t i = 4, nvic_val = 0;
+ uint8_t in_range = 0;
+ // test the initial SP value
+ memcpy(&nvic_val, buf + 0, sizeof(nvic_val));
+
+ region_info_t * region = g_board_info.target_cfg->ram_regions;
+ for (; region->start != 0 || region->end != 0; ++region) {
+ if (1 == test_range(nvic_val, region->start, region->end)) {
+ in_range = 1;
+ break;
+ }
+ }
+
+ if (in_range == 0) {
+ return 0;
+ }
+
+ // Reset_Handler
+ // NMI_Handler
+ // HardFault_Handler
+ for (; i <= 12; i += 4) {
+ in_range = 0;
+ memcpy(&nvic_val, buf + i, sizeof(nvic_val));
+ region_info_t * region = g_board_info.target_cfg->flash_regions;
+ for (; region->start != 0 || region->end != 0; ++region) {
+ if (1 == test_range(nvic_val, region->start, region->end)) {
+ in_range = 1;
+ break;
+ }
+ }
+ if (in_range == 0) {
+ return 0;
+ }
+ }
+
+ return 1;
+
+ } else {
+ return 0;
+ }
+}
+
+uint8_t validate_hexfile(const uint8_t *buf)
+{
+ if (g_target_family && g_target_family->validate_hexfile) {
+ return g_target_family->validate_hexfile(buf);
+ } else {
+ // look here for known hex records
+ // add hex identifier b[0] == ':' && b[8] == {'0', '2', '3', '4', '5'}
+ return ((buf[0] == ':') && ((buf[8] == '0') || (buf[8] == '2') || (buf[8] == '3') || (buf[8] == '4') || (buf[8] == '5'))) ? 1 : 0;
+ }
+}
diff -r 000000000000 -r 01f31e923fe2 source/daplink/validation.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/validation.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,38 @@
+/**
+ * @file validation.h
+ * @brief Helper functions to determine if a hex or binary file is valid
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef VALIDATION_H
+#define VALIDATION_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+uint8_t validate_bin_nvic(const uint8_t *buf);
+uint8_t validate_hexfile(const uint8_t *buf);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/daplink/version_git_tmpl.txt
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/daplink/version_git_tmpl.txt Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,36 @@
+/**
+ * @file version_git_tmpl.txt
+ * @brief Template for tracking repo status in a build
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef VERSION_GIT_H
+#define VERSION_GIT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define GIT_COMMIT_SHA "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"
+#define GIT_LOCAL_MODS 1
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/family/arm/musca_a/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/arm/musca_a/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,178 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the Musca A
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2016-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x4604b570, 0x4616460d, 0x4448486a, 0xb9e86800, 0x44784869, 0x44494969, 0x46086008, 0x44494968,
+ 0x46086008, 0x44494967, 0x68096008, 0xf0006808, 0x4964fc9c, 0x68084449, 0xf0002101, 0xb108f9c1,
+ 0xbd702001, 0x495b2001, 0x60084449, 0xe7f82000, 0x4604b510, 0x4857b984, 0x68004448, 0xd10b2801,
+ 0x44494958, 0xf0006808, 0xb108fa25, 0xbd102001, 0x49502000, 0x60084449, 0xe7f82000, 0x4951b510,
+ 0x22004449, 0x46116808, 0xfbaaf000, 0x2001b108, 0x2000bd10, 0xb510e7fc, 0xf0244604, 0xf5a0407f,
+ 0x49481400, 0xf44f4449, 0x68083280, 0xf0004621, 0xb108fb97, 0xbd102001, 0xe7fc2000, 0x41f0e92d,
+ 0x460d4604, 0xf0244617, 0xf5a0407f, 0x493d1400, 0x462b4449, 0x6808463a, 0xf0004621, 0x4606faf6,
+ 0x4630b116, 0x81f0e8bd, 0xe7fb2000, 0x43f8e92d, 0x46884607, 0xf0274615, 0xf5a6467f, 0x24001600,
+ 0x4930e025, 0x23044449, 0x6808466a, 0xf0004631, 0xf89dfa8e, 0x5d290000, 0xd1114288, 0x1001f89d,
+ 0x5c281c60, 0xd10b4281, 0x1002f89d, 0x5c281ca0, 0xd1054281, 0x1003f89d, 0x5c281ce0, 0xd0044281,
+ 0x1000f506, 0xe8bd4420, 0x1d3683f8, 0x45441d24, 0x2000d3d7, 0xe92de7f7, 0x460643f8, 0x4614460f,
+ 0x457ff026, 0x1500f5a5, 0x0800f04f, 0x4915e01d, 0x23044449, 0x6808466a, 0xf0004629, 0xf89dfa58,
+ 0x42a00000, 0xf89dd10b, 0x42a00001, 0xf89dd107, 0x42a00002, 0xf89dd103, 0x42a00003, 0x2001d002,
+ 0x83f8e8bd, 0xf1081d2d, 0x45b80804, 0x2000d3df, 0x0000e7f6, 0x00000004, 0x00000da6, 0x00000008,
+ 0x0000000c, 0x00000020, 0xb118b570, 0x2d2018d5, 0xb902d800, 0x2a20bd70, 0x6001d101, 0x2501e7fa,
+ 0x1e6c4095, 0xfa046805, 0x43b5f603, 0x0604ea01, 0x4335409e, 0xbf006005, 0xb510e7ec, 0x21064604,
+ 0xf0006820, 0xbd10fd7b, 0x4604b57f, 0x2000460d, 0x90009003, 0x90029001, 0xaa032301, 0x68202165,
+ 0xfd7ef000, 0xb1164606, 0xb0044630, 0xb125bd70, 0xd00d2d01, 0xd1212d02, 0xf89de015, 0xf040000c,
+ 0x90030040, 0x000cf89d, 0x0080f040, 0xe0179003, 0x000cf89d, 0x0040f020, 0xf89d9003, 0xf040000c,
+ 0x90030080, 0xf89de00c, 0xf040000c, 0x90030040, 0x000cf89d, 0x0080f020, 0xe0019003, 0xe7d42001,
+ 0x4620bf00, 0xffb9f7ff, 0x90002000, 0x90029001, 0xaa032301, 0x68202161, 0xfd5ff000, 0xb10e4606,
+ 0xe7c24630, 0x462a462b, 0x68204629, 0xfb83f000, 0xb10e4606, 0xe7b84630, 0xe7b62000, 0x4604b57f,
+ 0x2000460e, 0x90009003, 0x90029001, 0xaa032301, 0x68202185, 0xfd24f000, 0xb1154605, 0xb0044628,
+ 0x2304bd70, 0x4631461a, 0xf7ffa803, 0x4620ff6d, 0xff83f7ff, 0x90002000, 0x90029001, 0xaa032301,
+ 0x68202181, 0xfd29f000, 0xb10d4605, 0xe7e64628, 0xe7e42000, 0x4605b57f, 0x90032000, 0x2000e00e,
+ 0x90019000, 0x23019002, 0x2170aa03, 0xf0006828, 0x4604fcf7, 0x4620b114, 0xbd70b004, 0x000cf89d,
+ 0x280009c0, 0x2000d0eb, 0xe92de7f6, 0xb0844dff, 0x46924606, 0x9c10469b, 0xf5c0b2e0, 0xe9dd7580,
+ 0xe9cd1011, 0x90024100, 0x4652462b, 0x99056830, 0xfcf3f000, 0xb11f4607, 0xb0084638, 0x8df0e8bd,
+ 0x442c44aa, 0xf7ff4630, 0x4680ffc5, 0x0f00f1b8, 0x4640d001, 0x4630e7f1, 0xff2ff7ff, 0x1011e9dd,
+ 0x0305ebab, 0x4100e9cd, 0x46529002, 0x99056830, 0xfcd3f000, 0xb10f4607, 0xe7de4638, 0xe7dc2000,
+ 0x4df3e92d, 0x4604b082, 0xb1209803, 0xd00b2801, 0xd11b2802, 0x2700e011, 0x0a03f04f, 0xf04f2600,
+ 0x20000b02, 0xe0159001, 0xf04f2700, 0x26080a0b, 0x0b02f04f, 0x90012000, 0x2702e00c, 0x0a6bf04f,
+ 0xf04f2608, 0x20000b32, 0xe0039001, 0xb0042001, 0x8df0e8bd, 0x4639bf00, 0xf7ff4620, 0x4680fef5,
+ 0x0f00f1b8, 0x4640d001, 0x4631e7f1, 0xf7ff4620, 0x4680ff45, 0x0f00f1b8, 0x4640d001, 0xbf00e7e7,
+ 0xf0006820, 0x2800fa40, 0x6820d0fa, 0xfa85f000, 0x682068a1, 0xfa91f000, 0xb10d4605, 0xe7d64628,
+ 0x46514632, 0xf0006820, 0x4605faff, 0x4628b10d, 0x6820e7cd, 0x9a014659, 0xfb01f000, 0xb10d4605,
+ 0xe7c44628, 0x7180f44f, 0xf0006820, 0x4605fb03, 0x4628b10d, 0x2103e7bb, 0xf0006820, 0x4605fb14,
+ 0x4628b10d, 0x6820e7b3, 0xfa5ff000, 0x74209803, 0xe7ac2000, 0x4604b570, 0x46202100, 0xfea4f7ff,
+ 0xb10d4605, 0xbd704628, 0x46202100, 0xfef6f7ff, 0xb10d4605, 0xe7f64628, 0x6820bf00, 0xf9f3f000,
+ 0xd0fa2800, 0xf0006820, 0x6820fa38, 0xfb30f000, 0xf0006820, 0x2000fa3a, 0xbf007420, 0xe92de7e3,
+ 0x46044df0, 0x46174688, 0x6820461d, 0x68406800, 0xfbb51c46, 0xb107fbf6, 0x2001b915, 0x8df0e8bd,
+ 0x0005eb08, 0x428868e1, 0x2006d301, 0xf04fe7f6, 0xe00d0a00, 0x68204641, 0xfadef000, 0x46384632,
+ 0xf0006861, 0x1badfc29, 0x44b04437, 0x0a01f10a, 0xd3ef45da, 0x4641b145, 0xf0006820, 0x462afacd,
+ 0x68614638, 0xfc18f000, 0xf0006820, 0x2000fadc, 0xe92de7d4, 0x46044dfc, 0x4692460f, 0x6820461e,
+ 0x68406800, 0x0801f100, 0x0f00f1ba, 0xb916d000, 0xe8bd2001, 0x19b88dfc, 0x428868e1, 0x2006d301,
+ 0xf007e7f7, 0x1b7f0503, 0xfbb01970, 0x9001f0f8, 0x90002000, 0x4639e01e, 0xf0006820, 0xeba8fa9d,
+ 0x68610205, 0x46511948, 0xfbe6f000, 0x0005eba8, 0xeba81a36, 0x44820005, 0x25004447, 0xf7ff4620,
+ 0x4683fe99, 0x0f00f1bb, 0x4658d001, 0x9800e7d1, 0x90001c40, 0x0100e9dd, 0xd3dc4288, 0x4639b196,
+ 0xf0006820, 0x6861fa79, 0x46321948, 0xf0004651, 0x4620fbc3, 0xfe7ef7ff, 0xf1bb4683, 0xd0010f00,
+ 0xe7b64658, 0xf0006820, 0x2000fa7e, 0xe92de7b1, 0xb0844dff, 0x460e4605, 0x08f8461f, 0x7c289003,
+ 0x2801b160, 0x2802d005, 0xf04fd107, 0x24080a6b, 0xf04fe008, 0x24080a0b, 0xbf00e004, 0x0a03f04f,
+ 0xbf002400, 0xf04fbf00, 0xe0180b00, 0xe9cd2003, 0x94026000, 0x68282308, 0x9a064651, 0xfb50f000,
+ 0xf1b84680, 0xd0030f00, 0xb0084640, 0x8df0e8bd, 0x30089806, 0x36089006, 0xf10b3f08, 0x98030b01,
+ 0xd3e34583, 0x2003b17f, 0x6000e9cd, 0x463b9402, 0x46516828, 0xf0009a06, 0x4680fb33, 0x0f00f1b8,
+ 0x4640d001, 0x2000e7e1, 0xe92de7df, 0xb0864dff, 0x460c4680, 0x08f0461e, 0xf8989005, 0xb1480010,
+ 0xd0062801, 0xd1032802, 0x0b32f04f, 0xe0052500, 0xbf00bf00, 0x0b02f04f, 0xbf002500, 0x2000bf00,
+ 0xe0379004, 0xf7ff4640, 0x0a21fd78, 0xebb11de0, 0xd00f2f10, 0x23082003, 0x0501e9cd, 0x46599400,
+ 0x9a084640, 0xfe11f7ff, 0xb1a74607, 0xb00a4638, 0x8df0e8bd, 0xe9cd2003, 0x94000501, 0xf8d82308,
+ 0x46590000, 0xf0009a08, 0x4682fb08, 0x0f00f1ba, 0x4650d001, 0x4640e7eb, 0xfddcf7ff, 0xb10f4607,
+ 0xe7e44638, 0x30089808, 0x34089008, 0x98043e08, 0x90041c40, 0x0104e9dd, 0xd3c34288, 0x4640b376,
+ 0xfd3bf7ff, 0x19a00a21, 0xebb11e40, 0xd00d2f10, 0x46332003, 0x0501e9cd, 0x46599400, 0x9a084640,
+ 0xfdd3f7ff, 0xb1974607, 0xe7c04638, 0xe9cd2003, 0x94000501, 0xf8d84633, 0x46590000, 0xf0009a08,
+ 0x4682facc, 0x0f00f1ba, 0x4650d001, 0x4640e7af, 0xfda0f7ff, 0xb10f4607, 0xe7a84638, 0xe7a62000,
+ 0x4df0e92d, 0x4607b086, 0x4693460c, 0xf7ff4638, 0xf1bbfd04, 0xd0090f00, 0x5f80f5bb, 0xf5bbd01d,
+ 0xd0124f00, 0x3f80f5bb, 0xe007d11f, 0x2005b11c, 0xe8bdb006, 0x25c78df0, 0xe0182600, 0x260325d8,
+ 0xb108b2a0, 0xe7f32005, 0x2552e011, 0xf3c42603, 0xb108000e, 0xe7eb2005, 0x2520e009, 0xf3c42603,
+ 0xb108000b, 0xe7e32005, 0x2001e001, 0xbf00e7e0, 0x42a068f8, 0x2006d801, 0x2000e7da, 0xc151a901,
+ 0x90009004, 0x461a2300, 0x68384629, 0xf986f000, 0xf1b84680, 0xd0010f00, 0xe7c94640, 0xf7ff4638,
+ 0x4682fd49, 0x0f00f1ba, 0x4640d001, 0x2000e7c0, 0x0000e7be, 0xb118b570, 0x2d2018d5, 0xb902d800,
+ 0x2a20bd70, 0x6001d101, 0x2501e7fa, 0x1e6c4095, 0xfa046805, 0x43b5f603, 0x0604ea01, 0x4335409e,
+ 0xbf006005, 0x4601e7ec, 0x68026808, 0x0fc06810, 0xe92d4770, 0x460545f8, 0x4614468a, 0x6828461e,
+ 0xb10e6807, 0xe0011d38, 0x0008f107, 0xf8d84680, 0x90000000, 0x4628bf00, 0xffe5f7ff, 0xd0fa2800,
+ 0xd9022c1f, 0xe8bd2001, 0x230085f8, 0x46512208, 0xf7ff4668, 0x2318ffbf, 0x46212205, 0xf7ff4668,
+ 0x9800ffb9, 0x0000f8c8, 0xe7ec2000, 0xb1214601, 0xd0042901, 0xd1062902, 0x2000e003, 0x20014770,
+ 0x2002e7fc, 0xf04fe7fa, 0xe7f730ff, 0x68084601, 0x68106802, 0x0001f000, 0x46014770, 0x6810680a,
+ 0xf0226802, 0x60020201, 0x46014770, 0x6810680a, 0xf0426802, 0x60020201, 0xb5704770, 0x460c4605,
+ 0x68066828, 0x4628bf00, 0xff9df7ff, 0xd0fa2800, 0x0001f004, 0x2c02b918, 0x2c20d301, 0x2001d901,
+ 0x2001bd70, 0x0154ebc0, 0x22042313, 0xf7ff4630, 0x2000ff71, 0xe92de7f4, 0xb0824dff, 0x460f4682,
+ 0xf8da4693, 0x68040000, 0x90016860, 0x900068a0, 0x4650bf00, 0xff77f7ff, 0xd0fa2800, 0xf7ff4638,
+ 0x4605ffa5, 0xb9181c68, 0xb0062001, 0x8df0e8bd, 0x2308b13f, 0x46292202, 0xf7ff1d20, 0x2000ff4b,
+ 0x4658e7f3, 0xff92f7ff, 0x98054680, 0xff8ef7ff, 0xf1084606, 0xb1080001, 0xb9081c70, 0xe7e42001,
+ 0x22022308, 0xa8014629, 0xff34f7ff, 0x2202230c, 0xa8014641, 0xff2ef7ff, 0x22022310, 0xa8014631,
+ 0xff28f7ff, 0x2202230c, 0x46684641, 0xff22f7ff, 0x22022310, 0x46684631, 0xff1cf7ff, 0x60609801,
+ 0x60a09800, 0xe7c02000, 0x4604b570, 0x4616460d, 0x46322301, 0x46204629, 0xff2bf7ff, 0xb570bd70,
+ 0x460d4604, 0x23004616, 0x46294632, 0xf7ff4620, 0xbd70ff20, 0x4604b570, 0x6820460d, 0xbf006806,
+ 0xf7ff4620, 0x2800ff10, 0xf5b5d0fa, 0xd3015f80, 0xbd702001, 0x220c2304, 0xf1064629, 0xf7ff0014,
+ 0x2000fee9, 0xb570e7f5, 0x460c4605, 0x68066828, 0x4628bf00, 0xfef7f7ff, 0xd0fa2800, 0x2c10b10c,
+ 0x2001d901, 0x1e61bd70, 0x22042300, 0x0014f106, 0xfed0f7ff, 0xe7f52000, 0x4604b570, 0x6820460d,
+ 0x46206803, 0xff22f7ff, 0xb1164606, 0xf7ff4620, 0x625dff24, 0xf4406818, 0x60183080, 0x4620b116,
+ 0xff23f7ff, 0xb530bd70, 0x68184603, 0x46186804, 0xff0cf7ff, 0xb1154605, 0xf7ff4618, 0x6820ff0e,
+ 0x3080f420, 0xb1156020, 0xf7ff4618, 0xbd30ff0e, 0x680a4601, 0x4a8e6810, 0x22036002, 0x22026042,
+ 0x4a8c6082, 0x22006142, 0xf8c06242, 0xf8c02090, 0xf8c02094, 0xf8c020a8, 0x477020ac, 0x4dffe92d,
+ 0x4616b086, 0xf8dd461d, 0xe9dda054, 0x98068712, 0x68046800, 0x90052000, 0xb10db116, 0xe0002001,
+ 0x46832000, 0x0f00f1b8, 0xb10fd002, 0xe0002001, 0x90042000, 0x0f00f1ba, 0x2001d001, 0x2000e000,
+ 0x20009003, 0x90029001, 0xd9032d08, 0xb00a2001, 0x8df0e8bd, 0xd9012f08, 0xe7f82001, 0x0f04f1ba,
+ 0x2001d901, 0x9816e7f3, 0xd901281f, 0xe7ee2001, 0x0f00f1bb, 0x9804d003, 0x2001b108, 0x2318e7e7,
+ 0xa8052208, 0xf7ff9907, 0xf1bbfe45, 0xd0090f00, 0xf4409805, 0x90050000, 0x23141e69, 0xa8052203,
+ 0xfe38f7ff, 0xb3289804, 0xf4409805, 0x90054000, 0x230c1e79, 0xa8052203, 0xfe2cf7ff, 0x0003f008,
+ 0xf007b968, 0xb9500003, 0x0000f8d8, 0x00a8f8c4, 0xd10f2f08, 0x0004f8d8, 0x00acf8c4, 0x463ae00a,
+ 0xa8014641, 0xf898f000, 0xf8c49801, 0x980200a8, 0x00acf8c4, 0xb1689803, 0xf4409805, 0x90052000,
+ 0xf8c49814, 0xf1aa0094, 0x23100101, 0xa8052202, 0xfe00f7ff, 0x22052307, 0x9916a805, 0xfdfaf7ff,
+ 0xf8449805, 0x68200f90, 0x0001f040, 0x0990f844, 0xf8d4bf00, 0xf3c00090, 0x28000040, 0xf1bbd1f9,
+ 0xd0190f00, 0x0003f006, 0xf005b958, 0xb9400003, 0x00a0f8d4, 0x2d086030, 0xf8d4d10e, 0x607000a4,
+ 0xf8d4e00a, 0x900100a0, 0x00a4f8d4, 0x462a9002, 0x4630a901, 0xf850f000, 0xe7682000, 0xb085b530,
+ 0x460d4604, 0x90012000, 0x90039002, 0x46039004, 0x46294602, 0x46209000, 0xff30f7ff, 0xbd30b005,
+ 0x4df0e92d, 0x4606b086, 0x4614460f, 0xe9dd461d, 0xf8ddab0f, 0xb1048038, 0x2001b91d, 0xe8bdb006,
+ 0x20008df0, 0xe8a1a901, 0x462b0d01, 0x46394622, 0x46309000, 0xff12f7ff, 0xe92de7f0, 0xb0864df0,
+ 0x460f4606, 0x461d4614, 0xab0fe9dd, 0x8038f8dd, 0xb91db104, 0xb0062001, 0x8df0e8bd, 0x461a2300,
+ 0x46304639, 0x0d30e88d, 0xfef8f7ff, 0x0000e7f3, 0x80780081, 0x00101002, 0x0301ea40, 0xd003079b,
+ 0xc908e009, 0xc0081f12, 0xd2fa2a04, 0xf811e003, 0xf8003b01, 0x1e523b01, 0x4770d2f9, 0x5010a000,
+ 0x0003ffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00000004, 0x00800000,
+ 0x00000000, 0x00000000
+};
+
+// Start address of flash
+static const uint32_t flash_start = 0x00200000;
+// Size of flash
+static const uint32_t flash_size = 0x00800000;
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x00200000, 0x00010000},
+};
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000071, // UnInit
+ 0x2000009d, // EraseChip
+ 0x200000b7, // EraseSector
+ 0x200000dd, // ProgramPage
+ 0x2000010d, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x20000de4,
+ 0x20001100
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(flash_prog_blob), // prog_blob size
+ flash_prog_blob, // address of prog_blob
+ 0x00000100 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/arm/musca_a/power_ctrl.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/arm/musca_a/power_ctrl.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,184 @@
+/**
+ * @file power_ctrl.c
+ * @brief power control sequence logic for Musca A
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "string.h"
+#include "stdio.h"
+#include "stdint.h"
+#include "syscon.h"
+#include "gpio.h"
+#include "utils.h"
+#include "uart.h"
+
+// Configure SCC
+void configure_syscon(unsigned int pc)
+{
+ unsigned int din;
+
+ // Dummy read
+ syscon_readreg(0x004, &din);
+
+ // CPU0 boot from QSPI or SRAM
+ syscon_writereg(0x020, pc);
+
+ // CPU1 boot from QSPI or SRAM
+ syscon_writereg(0x028, pc);
+
+ // Set IO drive strength and slew rate
+ syscon_writereg(0x068, 0x03F00000);
+ syscon_writereg(0x06C, 0x000FFFFF);
+ syscon_writereg(0x078, 0xFFFFFFFF);
+}
+
+// Brown Out Detect
+void enable_BOD(int enable)
+{
+ if (enable)
+ {
+ // Set BOD interrupt to 2.80-2.90V
+ LPC_SYSCON->BODCTRL |= 0x1C;
+ NVIC_EnableIRQ(BOD_IRQn); /* Enable BOD interrupt */
+ }
+ else
+ {
+ LPC_SYSCON->BODCTRL = 0x00;
+ NVIC_DisableIRQ(BOD_IRQn);
+ NVIC_ClearPendingIRQ(BOD_IRQn);
+ }
+}
+
+//Power off / shutdown sequence
+void power_off_sequence()
+{
+ // Disable Brown Out Detection
+ enable_BOD(0);
+
+ // Apply CS_nSRST
+ LPC_GPIO->CLR[PIN_nRESET_PORT] = PIN_nRESET;
+
+ // Wait 10ms
+ delay(10);
+
+ // Apply CB_nRST
+ LPC_GPIO->CLR[PIN_CB_nRST_PORT] = PIN_CB_nRST;
+ // Wait 10ms
+ delay(10);
+
+ // Apply CFG_nRST
+ LPC_GPIO->CLR[PIN_CFG_nRST_PORT] = PIN_CFG_nRST;
+
+ // Wait 10ms
+ delay(10);
+}
+
+//Power on sequence
+void power_on_sequence()
+{
+ // Drive SCC signals
+ LPC_GPIO->DIR[PIN_SCC_CLK_PORT] |= PIN_SCC_CLK;
+ LPC_GPIO->DIR[PIN_SCC_DATAIN_PORT] |= PIN_SCC_DATAIN;
+ LPC_GPIO->DIR[PIN_SCC_DATAOUT_PORT] &= ~PIN_SCC_DATAOUT;
+ LPC_GPIO->DIR[PIN_SCC_WNR_PORT] |= PIN_SCC_WNR;
+ LPC_GPIO->DIR[PIN_SCC_LOAD_PORT] |= PIN_SCC_LOAD;
+
+ // Wait 10ms
+ delay(10);
+
+ // Release CFG_nRST to allow SCC config
+ LPC_GPIO->SET[PIN_CFG_nRST_PORT] = PIN_CFG_nRST;
+
+ // Wait 10ms
+ delay(10);
+
+ // Configure SCC
+ configure_syscon(0x10200000);
+
+ // Wait 10ms
+ delay(10);
+
+ // Release SCC signals
+ LPC_GPIO->DIR[PIN_SCC_CLK_PORT] &= ~PIN_SCC_CLK;
+ LPC_GPIO->DIR[PIN_SCC_DATAIN_PORT] &= ~PIN_SCC_DATAIN;
+ LPC_GPIO->DIR[PIN_SCC_DATAOUT_PORT] &= ~PIN_SCC_DATAOUT;
+ LPC_GPIO->DIR[PIN_SCC_WNR_PORT] &= ~PIN_SCC_WNR;
+ LPC_GPIO->DIR[PIN_SCC_LOAD_PORT] &= ~PIN_SCC_LOAD;
+
+ // Wait 10ms
+ delay(10);
+
+ // Release CB_nRST
+ LPC_GPIO->SET[PIN_CB_nRST_PORT] = PIN_CB_nRST;
+
+ // Wait 10ms
+ delay(10);
+
+ // Release CS_nSRST
+ LPC_GPIO->SET[PIN_nRESET_PORT] = PIN_nRESET;
+
+ // Wait 10ms
+ delay(10);
+
+ // Enable Brown Out Detection
+ enable_BOD(1);
+}
+
+// BOD Interrupt Service Routine
+void BOD_IRQHandler(void)
+{
+ NVIC_DisableIRQ(BOD_IRQn);
+ gpio_set_cdc_led(GPIO_LED_OFF); // ON GREEN
+
+ // go into controlled shutdown
+ power_off_sequence();
+
+ while(1)
+ {
+ delay(100);
+ gpio_set_hid_led(GPIO_LED_ON);
+ delay(100);
+ gpio_set_hid_led(GPIO_LED_OFF);
+ }
+}
+
+// Function to wait till PBON button is pressed and released
+void wait_for_pbon(void)
+{
+ // Standby - wait for PBON
+ while (!gpio_get_pbon_btn())
+ {
+ // Do something with leds?
+ gpio_set_cdc_led(GPIO_LED_ON);
+ delay(100);
+ gpio_set_cdc_led(GPIO_LED_OFF);
+ delay(100);
+ }
+ // Wait for PBON to go low then high
+ while (gpio_get_pbon_btn())
+ {
+ // Do something with leds?
+ gpio_set_hid_led(GPIO_LED_ON);
+ delay(100);
+ gpio_set_hid_led(GPIO_LED_OFF);
+ delay(100);
+ }
+ // Wait 10ms
+ delay(10);
+
+}
diff -r 000000000000 -r 01f31e923fe2 source/family/arm/musca_a/power_ctrl.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/family/arm/musca_a/power_ctrl.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,32 @@ +/** + * @file power_ctrl.h + * @brief power control sequence logic for Musca A + * + * DAPLink Interface Firmware + * Copyright (c) 2018-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +void BOD_IRQHandler(void); + +void wait_for_pbon(void); + +void configure_syscon(unsigned int pc); + +void enable_BOD(int enable); + +void power_off_sequence(void); + +void power_on_sequence(void);
diff -r 000000000000 -r 01f31e923fe2 source/family/arm/musca_a/syscon.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/arm/musca_a/syscon.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,215 @@
+/**
+ * @file syscon.c
+ * @brief System Controller serial interface
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2008-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ctype.h> // character functions
+#include <string.h> // string and memory functions
+
+#include "IO_Config_Override.h" // I/O pin definitions
+
+#include "syscon.h" // SCC interface
+
+// SYSCON timing
+#define TSUH 2 // Clock setup and hold
+#define TCLK 2 // Clock high time
+
+// Misc defines
+#define GPIOIMSK 0x003F // GPIOI SCC bit mask
+
+/*----------------------------------------------------------------------------
+ System Controller serial interface
+ *----------------------------------------------------------------------------*/
+static void Sleepns(uint32_t cycles)
+{
+ volatile uint32_t i = cycles; // fudge factor to give approximate 1 ns
+
+ while (i > 0) {
+ i--;
+ }
+}
+/*----------------------------------------------------------------------------
+ System Controller 32bit register read (16uS)
+ *----------------------------------------------------------------------------*/
+void syscon_readreg(unsigned int addr, unsigned int *din)
+{
+ volatile unsigned int loop, data;
+
+ // Write the 12bit address value
+ for(loop = 0; loop < 12; loop++)
+ {
+ if (addr & 0x800)
+ {
+ LPC_GPIO->SET[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
+ }
+ else
+ {
+ LPC_GPIO->CLR[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
+ }
+ Sleepns(TCLK);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ // Set next address bit
+ addr = (addr << 1) & 0xFFF;
+ }
+
+ LPC_GPIO->CLR[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
+ Sleepns(TCLK);
+
+ // Config load
+ LPC_GPIO->SET[PIN_SCC_LOAD_PORT] = PIN_SCC_LOAD;
+ Sleepns(TCLK * 2);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK * 3);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ LPC_GPIO->CLR[PIN_SCC_LOAD_PORT] = PIN_SCC_LOAD;
+ Sleepns(TCLK * 2);
+
+ // Read the 32bit data value
+ data = 0;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ data = (data >> 8) & 0x00FFFFFF;
+ Sleepns(TCLK);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK * 2);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK);
+ data |= ((LPC_GPIO->PIN[PIN_SCC_DATAOUT_PORT] & PIN_SCC_DATAOUT) << (24 - PIN_SCC_DATAOUT_BIT));
+ Sleepns(TCLK);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK * 2);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK);
+ data |= ((LPC_GPIO->PIN[PIN_SCC_DATAOUT_PORT] & PIN_SCC_DATAOUT) << (25 - PIN_SCC_DATAOUT_BIT));
+ Sleepns(TCLK);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK * 2);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK);
+ data |= ((LPC_GPIO->PIN[PIN_SCC_DATAOUT_PORT] & PIN_SCC_DATAOUT) << (26 - PIN_SCC_DATAOUT_BIT));
+ Sleepns(TCLK);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK * 2);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK);
+ data |= ((LPC_GPIO->PIN[PIN_SCC_DATAOUT_PORT] & PIN_SCC_DATAOUT) << (27 - PIN_SCC_DATAOUT_BIT));
+ Sleepns(TCLK);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK * 2);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK);
+ data |= ((LPC_GPIO->PIN[PIN_SCC_DATAOUT_PORT] & PIN_SCC_DATAOUT) << (28 - PIN_SCC_DATAOUT_BIT));
+ Sleepns(TCLK);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK * 2);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK);
+ data |= ((LPC_GPIO->PIN[PIN_SCC_DATAOUT_PORT] & PIN_SCC_DATAOUT) << (29 - PIN_SCC_DATAOUT_BIT));
+ Sleepns(TCLK);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK * 2);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK);
+ data |= ((LPC_GPIO->PIN[PIN_SCC_DATAOUT_PORT] & PIN_SCC_DATAOUT) << (30 - PIN_SCC_DATAOUT_BIT));
+ Sleepns(TCLK);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK * 2);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK);
+ data |= ((LPC_GPIO->PIN[PIN_SCC_DATAOUT_PORT] & PIN_SCC_DATAOUT) << (31 - PIN_SCC_DATAOUT_BIT));
+ Sleepns(TCLK);
+ }
+
+ // Return the 32bit data value
+ *din = data;
+}
+
+/*----------------------------------------------------------------------------
+ System Controller 32bit register write (20uS)
+ *----------------------------------------------------------------------------*/
+void syscon_writereg(unsigned int addr, unsigned int dout)
+{
+ volatile unsigned int loop, data;
+
+ // Set write enable
+ LPC_GPIO->SET[PIN_SCC_WNR_PORT] = PIN_SCC_WNR;
+
+ // Write the 12bit address value
+ for(loop = 0; loop < 12; loop++)
+ {
+ if (addr & 0x800)
+ {
+ LPC_GPIO->SET[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
+ }
+ else
+ {
+ LPC_GPIO->CLR[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
+ }
+ Sleepns(TCLK);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ // Set next address bit
+ addr = (addr << 1) & 0xFFF;
+ }
+
+ LPC_GPIO->CLR[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
+ Sleepns(TCLK);
+
+ // Write the 32bit data value
+ data = dout;
+ for (loop = 0; loop < 32; loop++)
+ {
+ if (data & 0x80000000)
+ {
+ LPC_GPIO->SET[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
+ }
+ else
+ {
+ LPC_GPIO->CLR[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
+ }
+ Sleepns(TCLK);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ // Set next address bit
+ data = (data << 1);
+ Sleepns(TCLK);
+ }
+
+ LPC_GPIO->CLR[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
+ Sleepns(TCLK);
+
+ // Config load
+ LPC_GPIO->SET[PIN_SCC_LOAD_PORT] = PIN_SCC_LOAD;
+ Sleepns(TCLK * 2);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK * 3);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ LPC_GPIO->CLR[PIN_SCC_LOAD_PORT] = PIN_SCC_LOAD;
+ Sleepns(TCLK * 2);
+
+ // Set to read
+ LPC_GPIO->CLR[PIN_SCC_WNR_PORT] = PIN_SCC_WNR;
+}
+
+// end of syscon.c
diff -r 000000000000 -r 01f31e923fe2 source/family/arm/musca_a/syscon.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/family/arm/musca_a/syscon.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,43 @@ +/** + * @file syscon.h + * @brief System Controller serial interface + * + * DAPLink Interface Firmware + * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __SYSCON_H +#define __SYSCON_H + +/* SCC registers */ +#define SCC_RESET_CTRL 0x00 // RESET Control register +#define SCC_CLK_CTRL 0x04 // CLOCK Control register +#define SCC_PWR_CTRL 0x08 // Power Control register +#define SCC_PLL_CTRL 0x0C // System Clock divider register +#define SCC_DBG_CTRL 0x10 // Debug Security override +#define SCC_SRAM_CTRL 0x14 // SRAM Bank power gate enable +#define SCC_INTR_CTRL 0x18 // Combined interrupt mask +#define SCC_CORDIO_CTRL 0x1C // REF to LLC Control and multiplex +#define SCC_CPU0_VTOR_SRAM 0x20 // CPU0 SRAM Boot vector +#define SCC_SPARE0 0x24 // CPU0 Spare +#define SCC_CPU1_VTOR_SRAM 0x28 // CPU1 SRAM Boot vector +#define SCC_SPARE1 0x2C // CPU1 Spare + +void syscon_readreg(unsigned int addr, unsigned int *din); +void syscon_writereg(unsigned int addr, unsigned int dout); + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/family/arm/musca_a/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/arm/musca_a/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,63 @@
+/**
+ * @file target.c
+ * @brief Target information for the Musca A qspi
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2016-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+#define MUSCA_A_NS_CODE_SRAM_START 0x00000000
+#define MUSCA_A_S_CODE_SRAM_START 0x10000000
+#define MUSCA_A_CODE_SRAM_SIZE MB(2)
+
+#define MUSCA_A_NS_FLASH_START 0x00200000
+#define MUSCA_A_S_FLASH_START 0x10200000
+#define MUSCA_A_FLASH_SIZE MB(8)
+
+#define MUSCA_A_FLASH_SECTOR_SIZE 0x010000
+
+#define MUSCA_A_NS_RAM_START 0x20000000
+#define MUSCA_A_S_RAM_START 0x30000000
+#define MUSCA_A_RAM_SIZE KB(128)
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = (MUSCA_A_NS_FLASH_START),
+ .flash_regions[0].end = (MUSCA_A_NS_FLASH_START + MUSCA_A_FLASH_SIZE),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+
+ .flash_regions[1].start = (MUSCA_A_S_FLASH_START),
+ .flash_regions[1].end = (MUSCA_A_S_FLASH_START + MUSCA_A_FLASH_SIZE),
+ .flash_regions[1].flash_algo = (program_target_t *) &flash,
+
+ .flash_regions[2].start = (MUSCA_A_NS_CODE_SRAM_START),
+ .flash_regions[2].end = (MUSCA_A_NS_CODE_SRAM_START + MUSCA_A_CODE_SRAM_SIZE),
+ .flash_regions[3].start = (MUSCA_A_S_CODE_SRAM_START),
+ .flash_regions[3].end = (MUSCA_A_S_CODE_SRAM_START + MUSCA_A_CODE_SRAM_SIZE),
+
+ .ram_regions[0].start = (MUSCA_A_NS_RAM_START),
+ .ram_regions[0].end = (MUSCA_A_NS_RAM_START + MUSCA_A_RAM_SIZE),
+ .ram_regions[1].start = (MUSCA_A_S_RAM_START),
+ .ram_regions[1].end = (MUSCA_A_S_RAM_START + MUSCA_A_RAM_SIZE),
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/arm/musca_a/target_reset.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/arm/musca_a/target_reset.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,162 @@
+/**
+ * @file target_reset.c
+ * @brief Target reset for Musca A target
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_config.h" // for target_device
+#include "swd_host.h"
+#include "gpio.h"
+#include "debug_cm.h"
+#include "utils.h"
+#include "power_ctrl.h"
+#include "uart.h"
+
+static void musca_a_target_before_init_debug(void)
+{
+ uint8_t buf[12];
+
+ // go into controlled shutdown
+ power_off_sequence();
+
+ // Drive SCC signals
+ LPC_GPIO->DIR[PIN_SCC_CLK_PORT] |= PIN_SCC_CLK;
+ LPC_GPIO->DIR[PIN_SCC_DATAIN_PORT] |= PIN_SCC_DATAIN;
+ LPC_GPIO->DIR[PIN_SCC_DATAOUT_PORT] &= ~PIN_SCC_DATAOUT;
+ LPC_GPIO->DIR[PIN_SCC_WNR_PORT] |= PIN_SCC_WNR;
+ LPC_GPIO->DIR[PIN_SCC_LOAD_PORT] |= PIN_SCC_LOAD;
+
+ // Wait 10ms
+ delay(10);
+
+ // Release CFG_nRST to allow SCC config
+ LPC_GPIO->SET[PIN_CFG_nRST_PORT] = PIN_CFG_nRST;
+
+ // Wait 10ms
+ delay(10);
+
+ // Configure SCC
+ configure_syscon(0x10000000);
+
+ // Wait 10ms
+ delay(10);
+
+ // Creating branch to self in SRAM
+ buf[0] = 0x00;
+ buf[1] = 0x00;
+ buf[2] = 0x08;
+ buf[3] = 0x30;
+ buf[4] = 0x09;
+ buf[5] = 0x00;
+ buf[6] = 0x00;
+ buf[7] = 0x10;
+ buf[8] = 0xFE;
+ buf[9] = 0xE7;
+ buf[10] = 0xFE;
+ buf[11] = 0xE7;
+
+ swd_write_memory(0x10000000, (uint8_t *)buf, 12);
+
+ // Wait 10ms
+ delay(10);
+
+ // Release SCC signals
+ LPC_GPIO->DIR[PIN_SCC_CLK_PORT] &= ~PIN_SCC_CLK;
+ LPC_GPIO->DIR[PIN_SCC_DATAIN_PORT] &= ~PIN_SCC_DATAIN;
+ LPC_GPIO->DIR[PIN_SCC_DATAOUT_PORT] &= ~PIN_SCC_DATAOUT;
+ LPC_GPIO->DIR[PIN_SCC_WNR_PORT] &= ~PIN_SCC_WNR;
+ LPC_GPIO->DIR[PIN_SCC_LOAD_PORT] &= ~PIN_SCC_LOAD;
+
+ // Wait 10ms
+ delay(10);
+
+ // Release CB_nRST (nPORESET)
+ LPC_GPIO->SET[PIN_CB_nRST_PORT] = PIN_CB_nRST;
+
+ // Wait 10ms
+ delay(10);
+
+ // Release CS_nSRST
+ LPC_GPIO->SET[PIN_nRESET_PORT] = PIN_nRESET;
+
+ // Wait 10ms
+ delay(10);
+
+ return;
+}
+
+static uint8_t musca_a_target_set_state(target_state_t state)
+{
+ if(state == RESET_RUN)
+ {
+ // go through controlled reset
+ power_off_sequence();
+
+ power_on_sequence();
+
+ // Wait 10ms
+ delay(10);
+
+ swd_off();
+
+ return 1;
+ }
+ if(state == SHUTDOWN)
+ {
+ // go through controlled shutdown
+ power_off_sequence();
+
+ // Remove PSUON
+ LPC_GPIO->CLR[PIN_PSUON_PORT] = PIN_PSUON;
+
+ // Wait 10ms
+ delay(10);
+
+ uart_reset();
+
+ return 1;
+ }
+ if(state == POWER_ON)
+ {
+ // Switch on power supply - PSUON
+ LPC_GPIO->SET[PIN_PSUON_PORT] = PIN_PSUON;
+
+ // Wait 10ms
+ delay(10);
+
+ // power on the target
+ power_on_sequence();
+
+ // Wait 10ms
+ delay(10);
+
+ swd_off();
+ return 1;
+ }
+
+ return swd_set_target_state_sw(state);
+}
+
+const target_family_descriptor_t g_target_family_musca_a = {
+ .target_before_init_debug = musca_a_target_before_init_debug,
+ .target_set_state = musca_a_target_set_state,
+ .apsel = 0x01000000,
+};
+
+const target_family_descriptor_t *g_target_family = &g_target_family_musca_a;
diff -r 000000000000 -r 01f31e923fe2 source/family/arm/musca_a/utils.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/arm/musca_a/utils.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,32 @@
+/**
+ * @file utils.c
+ * @brief Utilities for Musca A target
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2018-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "stdint.h"
+
+void delay(uint32_t cycles)
+{
+ volatile uint32_t i;
+ i = cycles * 4000; // fudge factor to give approximate 1 ms
+
+ while (i > 0) {
+ i--;
+ }
+}
diff -r 000000000000 -r 01f31e923fe2 source/family/arm/musca_a/utils.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/family/arm/musca_a/utils.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,22 @@ +/** + * @file utils.h + * @brief Utilities for Musca A target + * + * DAPLink Interface Firmware + * Copyright (c) 2018-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +void delay(uint32_t cycles);
diff -r 000000000000 -r 01f31e923fe2 source/family/arm/musca_b/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/arm/musca_b/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,250 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the Musca B
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2016-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t qspi_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x4604b570, 0x4616460d, 0x44484867, 0xb9e86800, 0x44784866, 0x44494966, 0x46086008, 0x44494965,
+ 0x46086008, 0x44494964, 0x68096008, 0xf0006808, 0x4961fc96, 0x68084449, 0xf0002101, 0xb108f9bb,
+ 0xbd702001, 0x49582001, 0x60084449, 0xe7f82000, 0x4604b510, 0x4854b984, 0x68004448, 0xd10b2801,
+ 0x44494955, 0xf0006808, 0xb108fa1f, 0xbd102001, 0x494d2000, 0x60084449, 0xe7f82000, 0x494eb510,
+ 0x22004449, 0x46116808, 0xfba4f000, 0x2001b108, 0x2000bd10, 0xb510e7fc, 0xf0244604, 0x4604407f,
+ 0x44494945, 0x3280f44f, 0x46216808, 0xfb92f000, 0x2001b108, 0x2000bd10, 0xe92de7fc, 0x460441f0,
+ 0x4617460d, 0x407ff024, 0x493b4604, 0x462b4449, 0x6808463a, 0xf0004621, 0x4606faf2, 0x4630b116,
+ 0x81f0e8bd, 0xe7fb2000, 0x43f8e92d, 0x46884607, 0xf0274615, 0xbf00467f, 0xe0232400, 0x4449492e,
+ 0x466a2304, 0x46316808, 0xfa8bf000, 0x0000f89d, 0x42885d29, 0xf89dd111, 0x1c601001, 0x42815c28,
+ 0xf89dd10b, 0x1ca01002, 0x42815c28, 0xf89dd105, 0x1ce01003, 0x42815c28, 0x1930d002, 0x83f8e8bd,
+ 0x1d241d36, 0xd3d94544, 0xe7f72000, 0x43f8e92d, 0x460f4606, 0xf0264614, 0xbf00457f, 0x0800f04f,
+ 0x4915e01d, 0x23044449, 0x6808466a, 0xf0004629, 0xf89dfa58, 0x42a00000, 0xf89dd10b, 0x42a00001,
+ 0xf89dd107, 0x42a00002, 0xf89dd103, 0x42a00003, 0x2001d002, 0x83f8e8bd, 0xf1081d2d, 0x45b80804,
+ 0x2000d3df, 0x0000e7f6, 0x00000004, 0x00000d9a, 0x00000008, 0x0000000c, 0x00000020, 0xb118b570,
+ 0x2d2018d5, 0xb902d800, 0x2a20bd70, 0x6001d101, 0x2501e7fa, 0x1e6c4095, 0xfa046805, 0x43b5f603,
+ 0x0604ea01, 0x4335409e, 0xbf006005, 0xb510e7ec, 0x21064604, 0xf0006820, 0xbd10fd7b, 0x4604b57f,
+ 0x2000460d, 0x90009003, 0x90029001, 0xaa032301, 0x68202165, 0xfd7ef000, 0xb1164606, 0xb0044630,
+ 0xb125bd70, 0xd00d2d01, 0xd1212d02, 0xf89de015, 0xf040000c, 0x90030040, 0x000cf89d, 0x0080f040,
+ 0xe0179003, 0x000cf89d, 0x0040f020, 0xf89d9003, 0xf040000c, 0x90030080, 0xf89de00c, 0xf040000c,
+ 0x90030040, 0x000cf89d, 0x0080f020, 0xe0019003, 0xe7d42001, 0x4620bf00, 0xffb9f7ff, 0x90002000,
+ 0x90029001, 0xaa032301, 0x68202161, 0xfd5ff000, 0xb10e4606, 0xe7c24630, 0x462a462b, 0x68204629,
+ 0xfb83f000, 0xb10e4606, 0xe7b84630, 0xe7b62000, 0x4604b57f, 0x2000460e, 0x90009003, 0x90029001,
+ 0xaa032301, 0x68202185, 0xfd24f000, 0xb1154605, 0xb0044628, 0x2304bd70, 0x4631461a, 0xf7ffa803,
+ 0x4620ff6d, 0xff83f7ff, 0x90002000, 0x90029001, 0xaa032301, 0x68202181, 0xfd29f000, 0xb10d4605,
+ 0xe7e64628, 0xe7e42000, 0x4605b57f, 0x90032000, 0x2000e00e, 0x90019000, 0x23019002, 0x2170aa03,
+ 0xf0006828, 0x4604fcf7, 0x4620b114, 0xbd70b004, 0x000cf89d, 0x280009c0, 0x2000d0eb, 0xe92de7f6,
+ 0xb0844dff, 0x46924606, 0x9c10469b, 0xf5c0b2e0, 0xe9dd7580, 0xe9cd1011, 0x90024100, 0x4652462b,
+ 0x99056830, 0xfcf3f000, 0xb11f4607, 0xb0084638, 0x8df0e8bd, 0x442c44aa, 0xf7ff4630, 0x4680ffc5,
+ 0x0f00f1b8, 0x4640d001, 0x4630e7f1, 0xff2ff7ff, 0x1011e9dd, 0x0305ebab, 0x4100e9cd, 0x46529002,
+ 0x99056830, 0xfcd3f000, 0xb10f4607, 0xe7de4638, 0xe7dc2000, 0x4df3e92d, 0x4604b082, 0xb1209803,
+ 0xd00b2801, 0xd11b2802, 0x2700e011, 0x0a03f04f, 0xf04f2600, 0x20000b02, 0xe0159001, 0xf04f2700,
+ 0x26080a0b, 0x0b02f04f, 0x90012000, 0x2702e00c, 0x0a6bf04f, 0xf04f2608, 0x20000b32, 0xe0039001,
+ 0xb0042001, 0x8df0e8bd, 0x4639bf00, 0xf7ff4620, 0x4680fef5, 0x0f00f1b8, 0x4640d001, 0x4631e7f1,
+ 0xf7ff4620, 0x4680ff45, 0x0f00f1b8, 0x4640d001, 0xbf00e7e7, 0xf0006820, 0x2800fa40, 0x6820d0fa,
+ 0xfa85f000, 0x682068a1, 0xfa91f000, 0xb10d4605, 0xe7d64628, 0x46514632, 0xf0006820, 0x4605faff,
+ 0x4628b10d, 0x6820e7cd, 0x9a014659, 0xfb01f000, 0xb10d4605, 0xe7c44628, 0x7180f44f, 0xf0006820,
+ 0x4605fb03, 0x4628b10d, 0x2103e7bb, 0xf0006820, 0x4605fb14, 0x4628b10d, 0x6820e7b3, 0xfa5ff000,
+ 0x74209803, 0xe7ac2000, 0x4604b570, 0x46202100, 0xfea4f7ff, 0xb10d4605, 0xbd704628, 0x46202100,
+ 0xfef6f7ff, 0xb10d4605, 0xe7f64628, 0x6820bf00, 0xf9f3f000, 0xd0fa2800, 0xf0006820, 0x6820fa38,
+ 0xfb30f000, 0xf0006820, 0x2000fa3a, 0xbf007420, 0xe92de7e3, 0x46044df0, 0x46174688, 0x6820461d,
+ 0x68406800, 0xfbb51c46, 0xb107fbf6, 0x2001b915, 0x8df0e8bd, 0x0005eb08, 0x428868e1, 0x2006d301,
+ 0xf04fe7f6, 0xe00d0a00, 0x68204641, 0xfadef000, 0x46384632, 0xf0006861, 0x1badfc29, 0x44b04437,
+ 0x0a01f10a, 0xd3ef45da, 0x4641b145, 0xf0006820, 0x462afacd, 0x68614638, 0xfc18f000, 0xf0006820,
+ 0x2000fadc, 0xe92de7d4, 0x46044dfc, 0x4692460f, 0x6820461e, 0x68406800, 0x0801f100, 0x0f00f1ba,
+ 0xb916d000, 0xe8bd2001, 0x19b88dfc, 0x428868e1, 0x2006d301, 0xf007e7f7, 0x1b7f0503, 0xfbb01970,
+ 0x9001f0f8, 0x90002000, 0x4639e01e, 0xf0006820, 0xeba8fa9d, 0x68610205, 0x46511948, 0xfbe6f000,
+ 0x0005eba8, 0xeba81a36, 0x44820005, 0x25004447, 0xf7ff4620, 0x4683fe99, 0x0f00f1bb, 0x4658d001,
+ 0x9800e7d1, 0x90001c40, 0x0100e9dd, 0xd3dc4288, 0x4639b196, 0xf0006820, 0x6861fa79, 0x46321948,
+ 0xf0004651, 0x4620fbc3, 0xfe7ef7ff, 0xf1bb4683, 0xd0010f00, 0xe7b64658, 0xf0006820, 0x2000fa7e,
+ 0xe92de7b1, 0xb0844dff, 0x460e4605, 0x08f8461f, 0x7c289003, 0x2801b160, 0x2802d005, 0xf04fd107,
+ 0x24080a6b, 0xf04fe008, 0x24080a0b, 0xbf00e004, 0x0a03f04f, 0xbf002400, 0xf04fbf00, 0xe0180b00,
+ 0xe9cd2003, 0x94026000, 0x68282308, 0x9a064651, 0xfb50f000, 0xf1b84680, 0xd0030f00, 0xb0084640,
+ 0x8df0e8bd, 0x30089806, 0x36089006, 0xf10b3f08, 0x98030b01, 0xd3e34583, 0x2003b17f, 0x6000e9cd,
+ 0x463b9402, 0x46516828, 0xf0009a06, 0x4680fb33, 0x0f00f1b8, 0x4640d001, 0x2000e7e1, 0xe92de7df,
+ 0xb0864dff, 0x460c4680, 0x08f0461e, 0xf8989005, 0xb1480010, 0xd0062801, 0xd1032802, 0x0b32f04f,
+ 0xe0052500, 0xbf00bf00, 0x0b02f04f, 0xbf002500, 0x2000bf00, 0xe0379004, 0xf7ff4640, 0x0a21fd78,
+ 0xebb11de0, 0xd00f2f10, 0x23082003, 0x0501e9cd, 0x46599400, 0x9a084640, 0xfe11f7ff, 0xb1a74607,
+ 0xb00a4638, 0x8df0e8bd, 0xe9cd2003, 0x94000501, 0xf8d82308, 0x46590000, 0xf0009a08, 0x4682fb08,
+ 0x0f00f1ba, 0x4650d001, 0x4640e7eb, 0xfddcf7ff, 0xb10f4607, 0xe7e44638, 0x30089808, 0x34089008,
+ 0x98043e08, 0x90041c40, 0x0104e9dd, 0xd3c34288, 0x4640b376, 0xfd3bf7ff, 0x19a00a21, 0xebb11e40,
+ 0xd00d2f10, 0x46332003, 0x0501e9cd, 0x46599400, 0x9a084640, 0xfdd3f7ff, 0xb1974607, 0xe7c04638,
+ 0xe9cd2003, 0x94000501, 0xf8d84633, 0x46590000, 0xf0009a08, 0x4682facc, 0x0f00f1ba, 0x4650d001,
+ 0x4640e7af, 0xfda0f7ff, 0xb10f4607, 0xe7a84638, 0xe7a62000, 0x4df0e92d, 0x4607b086, 0x4693460c,
+ 0xf7ff4638, 0xf1bbfd04, 0xd0090f00, 0x5f80f5bb, 0xf5bbd01d, 0xd0124f00, 0x3f80f5bb, 0xe007d11f,
+ 0x2005b11c, 0xe8bdb006, 0x25c78df0, 0xe0182600, 0x260325d8, 0xb108b2a0, 0xe7f32005, 0x2552e011,
+ 0xf3c42603, 0xb108000e, 0xe7eb2005, 0x2520e009, 0xf3c42603, 0xb108000b, 0xe7e32005, 0x2001e001,
+ 0xbf00e7e0, 0x42a068f8, 0x2006d801, 0x2000e7da, 0xc151a901, 0x90009004, 0x461a2300, 0x68384629,
+ 0xf986f000, 0xf1b84680, 0xd0010f00, 0xe7c94640, 0xf7ff4638, 0x4682fd49, 0x0f00f1ba, 0x4640d001,
+ 0x2000e7c0, 0x0000e7be, 0xb118b570, 0x2d2018d5, 0xb902d800, 0x2a20bd70, 0x6001d101, 0x2501e7fa,
+ 0x1e6c4095, 0xfa046805, 0x43b5f603, 0x0604ea01, 0x4335409e, 0xbf006005, 0x4601e7ec, 0x68026808,
+ 0x0fc06810, 0xe92d4770, 0x460545f8, 0x4614468a, 0x6828461e, 0xb10e6807, 0xe0011d38, 0x0008f107,
+ 0xf8d84680, 0x90000000, 0x4628bf00, 0xffe5f7ff, 0xd0fa2800, 0xd9022c1f, 0xe8bd2001, 0x230085f8,
+ 0x46512208, 0xf7ff4668, 0x2318ffbf, 0x46212205, 0xf7ff4668, 0x9800ffb9, 0x0000f8c8, 0xe7ec2000,
+ 0xb1214601, 0xd0042901, 0xd1062902, 0x2000e003, 0x20014770, 0x2002e7fc, 0xf04fe7fa, 0xe7f730ff,
+ 0x68084601, 0x68106802, 0x0001f000, 0x46014770, 0x6810680a, 0xf0226802, 0x60020201, 0x46014770,
+ 0x6810680a, 0xf0426802, 0x60020201, 0xb5704770, 0x460c4605, 0x68066828, 0x4628bf00, 0xff9df7ff,
+ 0xd0fa2800, 0x0001f004, 0x2c02b918, 0x2c20d301, 0x2001d901, 0x2001bd70, 0x0154ebc0, 0x22042313,
+ 0xf7ff4630, 0x2000ff71, 0xe92de7f4, 0xb0824dff, 0x460f4682, 0xf8da4693, 0x68040000, 0x90016860,
+ 0x900068a0, 0x4650bf00, 0xff77f7ff, 0xd0fa2800, 0xf7ff4638, 0x4605ffa5, 0xb9181c68, 0xb0062001,
+ 0x8df0e8bd, 0x2308b13f, 0x46292202, 0xf7ff1d20, 0x2000ff4b, 0x4658e7f3, 0xff92f7ff, 0x98054680,
+ 0xff8ef7ff, 0xf1084606, 0xb1080001, 0xb9081c70, 0xe7e42001, 0x22022308, 0xa8014629, 0xff34f7ff,
+ 0x2202230c, 0xa8014641, 0xff2ef7ff, 0x22022310, 0xa8014631, 0xff28f7ff, 0x2202230c, 0x46684641,
+ 0xff22f7ff, 0x22022310, 0x46684631, 0xff1cf7ff, 0x60609801, 0x60a09800, 0xe7c02000, 0x4604b570,
+ 0x4616460d, 0x46322301, 0x46204629, 0xff2bf7ff, 0xb570bd70, 0x460d4604, 0x23004616, 0x46294632,
+ 0xf7ff4620, 0xbd70ff20, 0x4604b570, 0x6820460d, 0xbf006806, 0xf7ff4620, 0x2800ff10, 0xf5b5d0fa,
+ 0xd3015f80, 0xbd702001, 0x220c2304, 0xf1064629, 0xf7ff0014, 0x2000fee9, 0xb570e7f5, 0x460c4605,
+ 0x68066828, 0x4628bf00, 0xfef7f7ff, 0xd0fa2800, 0x2c10b10c, 0x2001d901, 0x1e61bd70, 0x22042300,
+ 0x0014f106, 0xfed0f7ff, 0xe7f52000, 0x4604b570, 0x6820460d, 0x46206803, 0xff22f7ff, 0xb1164606,
+ 0xf7ff4620, 0x625dff24, 0xf4406818, 0x60183080, 0x4620b116, 0xff23f7ff, 0xb530bd70, 0x68184603,
+ 0x46186804, 0xff0cf7ff, 0xb1154605, 0xf7ff4618, 0x6820ff0e, 0x3080f420, 0xb1156020, 0xf7ff4618,
+ 0xbd30ff0e, 0x680a4601, 0x4a8e6810, 0x22036002, 0x22026042, 0x4a8c6082, 0x22006142, 0xf8c06242,
+ 0xf8c02090, 0xf8c02094, 0xf8c020a8, 0x477020ac, 0x4dffe92d, 0x4616b086, 0xf8dd461d, 0xe9dda054,
+ 0x98068712, 0x68046800, 0x90052000, 0xb10db116, 0xe0002001, 0x46832000, 0x0f00f1b8, 0xb10fd002,
+ 0xe0002001, 0x90042000, 0x0f00f1ba, 0x2001d001, 0x2000e000, 0x20009003, 0x90029001, 0xd9032d08,
+ 0xb00a2001, 0x8df0e8bd, 0xd9012f08, 0xe7f82001, 0x0f04f1ba, 0x2001d901, 0x9816e7f3, 0xd901281f,
+ 0xe7ee2001, 0x0f00f1bb, 0x9804d003, 0x2001b108, 0x2318e7e7, 0xa8052208, 0xf7ff9907, 0xf1bbfe45,
+ 0xd0090f00, 0xf4409805, 0x90050000, 0x23141e69, 0xa8052203, 0xfe38f7ff, 0xb3289804, 0xf4409805,
+ 0x90054000, 0x230c1e79, 0xa8052203, 0xfe2cf7ff, 0x0003f008, 0xf007b968, 0xb9500003, 0x0000f8d8,
+ 0x00a8f8c4, 0xd10f2f08, 0x0004f8d8, 0x00acf8c4, 0x463ae00a, 0xa8014641, 0xf898f000, 0xf8c49801,
+ 0x980200a8, 0x00acf8c4, 0xb1689803, 0xf4409805, 0x90052000, 0xf8c49814, 0xf1aa0094, 0x23100101,
+ 0xa8052202, 0xfe00f7ff, 0x22052307, 0x9916a805, 0xfdfaf7ff, 0xf8449805, 0x68200f90, 0x0001f040,
+ 0x0990f844, 0xf8d4bf00, 0xf3c00090, 0x28000040, 0xf1bbd1f9, 0xd0190f00, 0x0003f006, 0xf005b958,
+ 0xb9400003, 0x00a0f8d4, 0x2d086030, 0xf8d4d10e, 0x607000a4, 0xf8d4e00a, 0x900100a0, 0x00a4f8d4,
+ 0x462a9002, 0x4630a901, 0xf850f000, 0xe7682000, 0xb085b530, 0x460d4604, 0x90012000, 0x90039002,
+ 0x46039004, 0x46294602, 0x46209000, 0xff30f7ff, 0xbd30b005, 0x4df0e92d, 0x4606b086, 0x4614460f,
+ 0xe9dd461d, 0xf8ddab0f, 0xb1048038, 0x2001b91d, 0xe8bdb006, 0x20008df0, 0xe8a1a901, 0x462b0d01,
+ 0x46394622, 0x46309000, 0xff12f7ff, 0xe92de7f0, 0xb0864df0, 0x460f4606, 0x461d4614, 0xab0fe9dd,
+ 0x8038f8dd, 0xb91db104, 0xb0062001, 0x8df0e8bd, 0x461a2300, 0x46304639, 0x0d30e88d, 0xfef8f7ff,
+ 0x0000e7f3, 0x80780081, 0x00101002, 0x0301ea40, 0xd003079b, 0xc908e009, 0xc0081f12, 0xd2fa2a04,
+ 0xf811e003, 0xf8003b01, 0x1e523b01, 0x4770d2f9, 0x52800000, 0x0003ffff, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000004, 0x00800000, 0x00000000, 0x00000000
+};
+
+static const program_target_t qspi_flash = {
+ 0x20000021, // Init
+ 0x20000071, // UnInit
+ 0x2000009d, // EraseChip
+ 0x200000b7, // EraseSector
+ 0x200000db, // ProgramPage
+ 0x20000109, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x20000dd8,
+ 0x20001000
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(qspi_flash_prog_blob), // prog_blob size
+ qspi_flash_prog_blob, // address of prog_blob
+ 0x00000100 // ram_to_flash_bytes_to_be_written
+};
+
+static const uint32_t musca_b_eflash_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x4604b570, 0x4616460d, 0x44484866, 0xb9986800, 0x44484865, 0x44494965, 0x48656048, 0x60084448,
+ 0x49644608, 0x60084449, 0x49636808, 0xf8dbf000, 0x495c2001, 0x60084449, 0xbd702000, 0xb9414601,
+ 0x44484858, 0x28016800, 0x2000d103, 0x444a4a55, 0x20006010, 0xb5104770, 0x44494956, 0x68082202,
+ 0xf0002100, 0xb108fa2b, 0xbd102001, 0xe7fc2000, 0x4604b510, 0x6020f1a4, 0x4449494b, 0x1e496849,
+ 0x0401ea00, 0x4449494b, 0x68082200, 0xf0004621, 0xb108fa15, 0xbd102001, 0xe7fc2000, 0x43f8e92d,
+ 0x460d4604, 0xf1a44616, 0x493f6020, 0x68494449, 0xea001e49, 0x20040401, 0xea4f9000, 0x27000895,
+ 0x493ce00e, 0x466b4449, 0x68084632, 0xf0004621, 0xb110f94b, 0xe8bd2001, 0x1d3683f8, 0x1c7f1d24,
+ 0xd3ee4547, 0xe7f62000, 0x41fce92d, 0x460f4604, 0xf1a44690, 0x492c6020, 0x68494449, 0xea001e49,
+ 0x20040401, 0x25009001, 0x492ae01a, 0xab014449, 0x6808466a, 0xf0004621, 0x2600f8c1, 0xf81de00c,
+ 0x19a90006, 0x1001f818, 0xd0044288, 0x6020f104, 0xe8bd4428, 0x1c7681fc, 0xd3f02e04, 0x1d2d1d24,
+ 0xd3e242bd, 0xe7f42000, 0x41fce92d, 0x460e4604, 0xf1a44617, 0x49146020, 0x68494449, 0xea001e49,
+ 0x20040401, 0xf04f9001, 0xe0160800, 0x44494911, 0x466aab01, 0x46216808, 0xf890f000, 0xe0072500,
+ 0x0005f81d, 0xd00242b8, 0xe8bd2001, 0x1c6d81fc, 0xd3f52d04, 0xf1081d24, 0x45b00804, 0x2000d3e6,
+ 0x0000e7f3, 0x00000004, 0x0000000c, 0x00000014, 0x00000008, 0x0000001c, 0x02710000, 0x6804b510,
+ 0xb11a6823, 0x041ff001, 0xe002601c, 0x041ff001, 0xbd10605c, 0x4604b510, 0x68096821, 0x5080f501,
+ 0xf9eaf000, 0xb570bd10, 0x460d4604, 0x211f2200, 0xf7ff4620, 0x6821ffe3, 0xf5016809, 0x46295080,
+ 0xf9cef000, 0xf7ff4620, 0x6861ffe5, 0x20016048, 0x70086861, 0xb570bd70, 0x25004604, 0x69a0bf00,
+ 0x001cf000, 0xd0fa1e05, 0x0010f005, 0x4620b140, 0xf9b3f000, 0x69a0bf00, 0x000cf000, 0xd0fa1e05,
+ 0xbd704628, 0x4604b570, 0xbf00460d, 0xf00069a0, 0x28000001, 0x61e5d1fa, 0x61602001, 0xf7ff4620,
+ 0xbd70ffda, 0x4604b5f0, 0x462e460d, 0x0020f104, 0x2a1018c7, 0x2010d901, 0x4610e000, 0x18d04602,
+ 0xd9002810, 0x21001ad2, 0x7838e004, 0x1c7f7030, 0x1c491c76, 0xd3f84291, 0xbdf04610, 0x4dfce92d,
+ 0x460f4604, 0x461d4692, 0x68006820, 0x682e9001, 0x0b00f04f, 0x200046d8, 0x68609000, 0xb9107800,
+ 0xe8bd2001, 0x68288dfc, 0x68614438, 0x42886849, 0x2005d901, 0x9801e7f5, 0xb1086980, 0xe7f02002,
+ 0x68096821, 0x5080f501, 0xf963f000, 0xd0012880, 0xe7e62003, 0x4639e015, 0xf7ff9801, 0x4683ffa3,
+ 0x000ff007, 0x46329000, 0xe9dd4651, 0xf7ff3000, 0x4680ffa9, 0x0608eba6, 0x44c24447, 0xf0009801,
+ 0xb11ef93c, 0x0008f00b, 0xd0e42800, 0x0008f00b, 0x4446b100, 0x1b806828, 0xf00b6028, 0xb1080008,
+ 0xe7be2006, 0xe7bc2000, 0x41f0e92d, 0x460d4604, 0x61e54616, 0x20026226, 0x46206160, 0xff5bf7ff,
+ 0x46384607, 0x81f0e8bd, 0x4df0e92d, 0x460e4605, 0x461c4690, 0xf8d06828, 0xf04fb000, 0x68270a00,
+ 0x78006868, 0x2001b910, 0x8df0e8bd, 0x44306820, 0x68496869, 0xd9014288, 0xe7f52005, 0x0018f8db,
+ 0x2002b108, 0xf006e7f0, 0xb9180003, 0xf0007820, 0xb1080003, 0xe7e72007, 0x4631e00d, 0xf8d84658,
+ 0xf7ff2000, 0x4682ffc1, 0xf1081d36, 0x1f3f0804, 0xf0004658, 0xb11ff8e2, 0x0008f00a, 0xd0ec2800,
+ 0x0008f00a, 0x1d3fb100, 0x1bc06820, 0xf00a6020, 0xb1080008, 0xe7c72006, 0xe7c52000, 0x4ff8e92d,
+ 0x460e4607, 0x461c4692, 0x68056838, 0x90002000, 0x8000f8d4, 0x0b02f04f, 0x78006878, 0x2001b910,
+ 0x8ff8e8bd, 0x44306820, 0x68496879, 0xd9014288, 0xe7f52005, 0xb10869a8, 0xe7f12002, 0x0003f006,
+ 0x7820b918, 0x0003f000, 0x2007b108, 0xe023e7e8, 0xf8da61ee, 0x62280000, 0x61682003, 0x9800e00c,
+ 0x0008f000, 0x6820b140, 0x0008eba0, 0x46286020, 0xf893f000, 0xe7d32006, 0x900069a8, 0x000bea00,
+ 0xd1ec4558, 0x0b06f04f, 0xf10a1d36, 0xf1a80a04, 0x46280804, 0xf881f000, 0x0f00f1b8, 0xbf00d1d8,
+ 0xf00069a8, 0x28000004, 0x6820d0fa, 0x0008eba0, 0x46286020, 0xf871f000, 0xe7b12000, 0x41f0e92d,
+ 0x460e4605, 0x68284617, 0xf04f6804, 0x68680800, 0xb9107800, 0xe8bd2001, 0x69a081f0, 0x2002b108,
+ 0xb127e7f9, 0xd0132f01, 0xd12a2f02, 0x6868e01c, 0x42b06840, 0x2005d201, 0x61e6e7ed, 0x61602004,
+ 0xf7ff4620, 0x4680fe88, 0xf0004620, 0xe01af846, 0x61e02000, 0x61602007, 0xf7ff4620, 0x4680fe7c,
+ 0xf0004620, 0xe00ef83a, 0x1000f44f, 0x200761e0, 0x46206160, 0xfe6ff7ff, 0x46204680, 0xf82df000,
+ 0x2004e001, 0xbf00e7c7, 0x0f08f1b8, 0x2006d101, 0x2000e7c1, 0x4601e7bf, 0x68026808, 0xf3c06990,
+ 0x47701040, 0x4604b510, 0x68096821, 0x5080f501, 0xf826f000, 0xb510bd10, 0x68214604, 0xf5016809,
+ 0xf0005080, 0xbd10f821, 0x4604b510, 0x68096821, 0x5080f501, 0xf81bf000, 0x211fbd10, 0x477060c1,
+ 0x4601460a, 0x600b4b0c, 0x604b4b0c, 0x608b4b0c, 0x46014770, 0x47702080, 0xf44f4601, 0x47701000,
+ 0xf44f4601, 0x47704080, 0x20034601, 0x46014770, 0x6990460a, 0x00004770, 0x11082801, 0x64050208,
+ 0x0a0a0a08, 0x00000000, 0x00000000, 0x52400000, 0x00000000, 0x00400000, 0x00000000, 0x00000000,
+ 0x00000000
+};
+
+static const program_target_t eflash = {
+ 0x20000021, // Init
+ 0x2000005d, // UnInit
+ 0x20000077, // EraseChip
+ 0x20000091, // EraseSector
+ 0x200000bd, // ProgramPage
+ 0x20000109, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x20000604,
+ 0x20000900
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(musca_b_eflash_flash_prog_blob), // prog_blob size
+ musca_b_eflash_flash_prog_blob, // address of prog_blob
+ 0x00004000 // ram_to_flash_bytes_to_be_written
+};
+
+/**
+* List of start and size for each size of flash sector - even indexes are start, odd are size
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address flash_start + flash_size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x00000000, 0x00010000},
+ {0x0a000000, 0x00004000},
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/arm/musca_b/i2c_gpio.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/arm/musca_b/i2c_gpio.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,262 @@
+/**
+ * @file i2c_gpio.c
+ * @brief I2C GPIO control for musca PCA9537
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "string.h"
+#include "stdio.h"
+#include "stdint.h"
+
+#include "gpio.h"
+#include "utils.h"
+#include "i2c_gpio.h"
+
+// Clock registers
+#define I2CGPIO_FREQ 6 // Sets OSC Clock SCL frequency
+#define I2CGPIO_WR 0 // Write command
+#define I2CGPIO_RD 1 // Read command
+#define I2CGPIO_ADDR 0x49 // Default slave address for PCA9537
+
+/*----------------------------------------------------------------------------
+ I2C Address + Wr + A
+ *----------------------------------------------------------------------------*/
+void i2c_gpio_addr(unsigned int addr, unsigned int read)
+{
+ unsigned int loop, data;
+
+ // Repeated Start condition (if required after Command)
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] &= ~PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+ LPC_GPIO->DIR[PIN_I2C_SDA_PORT] &= ~PIN_I2C_SDA;
+ delay_us(I2CGPIO_FREQ);
+
+ // Start condition 'S' (DATA > CLK)
+ LPC_GPIO->DIR[PIN_I2C_SDA_PORT] |= PIN_I2C_SDA;
+ delay_us(I2CGPIO_FREQ);
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] |= PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+
+ // Addr is 7 bits so add Read
+ data = (addr << 1) & 0xFE;
+ if (read)
+ data |= 0x01;
+
+ // Clock out the 8 bits
+ for (loop = 0; loop < 8; loop++)
+ {
+ if (data & (0x80 >> loop))
+ {
+ LPC_GPIO->DIR[PIN_I2C_SDA_PORT] &= ~PIN_I2C_SDA;
+ delay_us(I2CGPIO_FREQ);
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] &= ~PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] |= PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+ }
+ else
+ {
+ LPC_GPIO->DIR[PIN_I2C_SDA_PORT] |= PIN_I2C_SDA;
+ delay_us(I2CGPIO_FREQ);
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] &= ~PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] |= PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+ }
+ }
+
+ // Set data low
+ delay_us(I2CGPIO_FREQ);
+ LPC_GPIO->DIR[PIN_I2C_SDA_PORT] |= PIN_I2C_SDA;
+ delay_us(I2CGPIO_FREQ);
+
+ // Transmission clock 'A'
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] &= ~PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] |= PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+}
+
+/*----------------------------------------------------------------------------
+ I2C Command + A
+ *----------------------------------------------------------------------------*/
+void i2c_gpio_cmd(unsigned int cmd)
+{
+ unsigned int loop;
+
+ // Clock out the 8 bits
+ for (loop = 0; loop < 8; loop++)
+ {
+ if (cmd & (0x80 >> loop))
+ {
+ LPC_GPIO->DIR[PIN_I2C_SDA_PORT] &= ~PIN_I2C_SDA;
+ delay_us(I2CGPIO_FREQ);
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] &= ~PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] |= PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+ }
+ else
+ {
+ LPC_GPIO->DIR[PIN_I2C_SDA_PORT] |= PIN_I2C_SDA;
+ delay_us(I2CGPIO_FREQ);
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] &= ~PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] |= PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+ }
+ }
+
+ // Set data low
+ delay_us(I2CGPIO_FREQ);
+ LPC_GPIO->DIR[PIN_I2C_SDA_PORT] |= PIN_I2C_SDA;
+ delay_us(I2CGPIO_FREQ);
+
+ // Transmission clock 'A'
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] &= ~PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] |= PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+}
+
+/*----------------------------------------------------------------------------
+ I2C Write Data + A + P
+ *----------------------------------------------------------------------------*/
+void i2c_gpio_write(unsigned int data)
+{
+ unsigned int loop;
+
+ // Clock out the 8 bits
+ for (loop = 0; loop < 8; loop++)
+ {
+ if (data & (0x80 >> loop))
+ {
+ LPC_GPIO->DIR[PIN_I2C_SDA_PORT] &= ~PIN_I2C_SDA;
+ delay_us(I2CGPIO_FREQ);
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] &= ~PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] |= PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+ }
+ else
+ {
+ LPC_GPIO->DIR[PIN_I2C_SDA_PORT] |= PIN_I2C_SDA;
+ delay_us(I2CGPIO_FREQ);
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] &= ~PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] |= PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+ }
+ }
+
+ // Set data low
+ delay_us(I2CGPIO_FREQ);
+ LPC_GPIO->DIR[PIN_I2C_SDA_PORT] |= PIN_I2C_SDA;
+ delay_us(I2CGPIO_FREQ);
+
+ // Transmission clock 'A'
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] &= ~PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] |= PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+
+ // Stop condition 'P'
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] &= ~PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+ LPC_GPIO->DIR[PIN_I2C_SDA_PORT] &= ~PIN_I2C_SDA;
+ delay_us(I2CGPIO_FREQ);
+}
+
+/*----------------------------------------------------------------------------
+ I2C Read Data + A + P
+ *----------------------------------------------------------------------------*/
+void i2c_gpio_read(unsigned int *data, unsigned int ack)
+{
+ unsigned int loop;
+
+ // Set SDA high (O/D) and allow PCA9537 to drive SDA
+ LPC_GPIO->DIR[PIN_I2C_SDA_PORT] &= ~PIN_I2C_SDA;
+ delay_us(I2CGPIO_FREQ);
+
+ // Clock in the 8 bits
+ *data = 0;
+ for (loop = 0; loop < 8; loop++)
+ {
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] &= ~PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+ if (LPC_GPIO->DIR[PIN_I2C_SDA_PORT] & PIN_I2C_SDA)
+ *data &= ~(0x80 >> loop);
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] |= PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+ }
+
+ // Set data for acknowledge
+ delay_us(I2CGPIO_FREQ);
+ if (ack)
+ LPC_GPIO->DIR[PIN_I2C_SDA_PORT] |= PIN_I2C_SDA;
+ else
+ LPC_GPIO->DIR[PIN_I2C_SDA_PORT] &= ~PIN_I2C_SDA;
+ delay_us(I2CGPIO_FREQ);
+
+ // Transmission clock 'A'
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] &= ~PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] |= PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+
+ // End of acknowledge
+ LPC_GPIO->DIR[PIN_I2C_SDA_PORT] |= PIN_I2C_SDA;
+ delay_us(I2CGPIO_FREQ);
+
+ // Stop condition 'P'
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] &= ~PIN_I2C_SCL;
+ delay_us(I2CGPIO_FREQ);
+ LPC_GPIO->DIR[PIN_I2C_SDA_PORT] &= ~PIN_I2C_SDA;
+ delay_us(I2CGPIO_FREQ);
+}
+
+/*----------------------------------------------------------------------------
+ I2C Write byte
+ *----------------------------------------------------------------------------*/
+void i2c_gpio_wbyte(unsigned int cmd, unsigned int data)
+{
+ // Set slave address write
+ i2c_gpio_addr(I2CGPIO_ADDR, I2CGPIO_WR);
+ // Set command
+ i2c_gpio_cmd(cmd);
+ // Write the data
+ i2c_gpio_write(data);
+}
+
+/*----------------------------------------------------------------------------
+ I2C Read byte
+ *----------------------------------------------------------------------------*/
+void i2c_gpio_rbyte(unsigned int cmd, unsigned int *data)
+{
+ // Set slave address write
+ i2c_gpio_addr(I2CGPIO_ADDR, I2CGPIO_WR);
+ // Set command
+ i2c_gpio_cmd(cmd);
+
+ // Set slave address write
+ i2c_gpio_addr(I2CGPIO_ADDR, I2CGPIO_RD);
+ // Read the data
+ i2c_gpio_read(data, 0);
+}
+
+// end of i2c_gpio.c
diff -r 000000000000 -r 01f31e923fe2 source/family/arm/musca_b/i2c_gpio.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/family/arm/musca_b/i2c_gpio.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,33 @@ +/** + * @file i2c_gpio.c + * @brief I2C GPIO control for musca PCA9537 + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef I2C_GPIO_H +#define I2C_GPIO_H + +#define FL_ON 0x01 // FLASH power control +#define CR_ON 0x02 // Core power control +#define IO_ON 0x04 // I/O power control +#define FLASH_PDM 0x08 // FLASH PDM power control + +void i2c_gpio_wbyte(unsigned int cmd, unsigned int data); +void i2c_gpio_rbyte(unsigned int cmd, unsigned int *data); + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/family/arm/musca_b/power_ctrl.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/arm/musca_b/power_ctrl.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,277 @@
+/**
+ * @file power_ctrl.c
+ * @brief power control sequence logic for Musca B
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "string.h"
+#include "stdio.h"
+#include "stdint.h"
+#include "syscon.h"
+#include "gpio.h"
+#include "utils.h"
+#include "uart.h"
+#include "i2c_gpio.h"
+#include "daplink_debug.h"
+#include "settings.h"
+#include "region_defs.h"
+
+// I2CIO expander init (PCA9537)
+void i2cio_init(void)
+{
+ unsigned int data;
+
+ // Default I2C state
+ LPC_GPIO->DIR[PIN_I2C_SCL_PORT] &= ~PIN_I2C_SCL;
+ // Wait 1ms
+ delay(1);
+ LPC_GPIO->DIR[PIN_I2C_SDA_PORT] &= ~PIN_I2C_SDA;
+ // Wait 1ms
+ delay(1);
+
+ // Dummy read
+ i2c_gpio_rbyte(0, &data);
+ // Wait 1ms
+ delay(1);
+
+ // Set default values
+ // Output register (all PSUs OFF)
+ i2c_gpio_wbyte(1, 0x00);
+ // Wait 1ms
+ delay(1);
+ // Inversion register
+ i2c_gpio_wbyte(2, 0x00);
+ // Wait 1ms
+ delay(1);
+ // Configuration register
+ i2c_gpio_wbyte(3, 0xF0);
+ // Wait 100ms
+ delay(100);
+}
+
+// I2CIO expander power OFF
+// Sequence: ON > FLASH_PDM + /PWR_OK > /VDD_IO > /VDD_CORE > + /VDD_FLASH + /FLASH_PDM > OFF
+void i2cio_power_off(void)
+{
+ i2c_gpio_wbyte(1, FL_ON | FLASH_PDM | CR_ON | IO_ON);
+ LPC_GPIO->CLR[PIN_PWROK_PORT] = PIN_PWROK;
+
+ i2c_gpio_wbyte(1, FL_ON | FLASH_PDM | CR_ON);
+
+ i2c_gpio_wbyte(1, FL_ON | FLASH_PDM);
+
+ i2c_gpio_wbyte(1, 0);
+}
+
+// I2CIO expander power ON
+// Sequence: OFF > VDD_FLASH + FLASH_PDM > VDD_CORE > /FLASH_PDM + PWR_OK > VDD_IO > ON
+void i2cio_power_on(void)
+{
+ i2c_gpio_wbyte(1, FL_ON | FLASH_PDM);
+ // Wait 100ms
+ delay(100);
+
+ i2c_gpio_wbyte(1, FL_ON | FLASH_PDM | CR_ON);
+ // Wait 100ms
+ delay(100);
+
+ i2c_gpio_wbyte(1, FL_ON | CR_ON);
+ LPC_GPIO->SET[PIN_PWROK_PORT] = PIN_PWROK;
+ // Wait 100ms
+ delay(100);
+
+ i2c_gpio_wbyte(1, FL_ON | CR_ON | IO_ON);
+ // Wait 100ms
+ delay(100);
+}
+
+// Configure SCC
+void configure_syscon(unsigned int pc)
+{
+ unsigned int din, dout;
+
+ // Dummy read
+ syscon_readreg(0x004, &din);
+
+ // CPU0 boot from QSPI/eFlash0/eFlash1/SRAM
+ // pc = 0x10000000/0x1A000000/0x1A200000/0x1A400000;
+ syscon_writereg(0x058, pc);
+
+ // CPU1 boot from QSPI/eFlash0/eFlash1/SRAM
+ // pc = 0x10000000/0x1A000000/0x1A200000/0x1A400000;
+ syscon_writereg(0x060, pc);
+
+ // QSPI divider for 20MHz
+ dout = 0x00000001;
+ syscon_writereg(0x010, dout);
+
+ // Set PA[37:0] IO drive strength (4/8/4mA) and slew rate (Slow)
+ syscon_writereg(0x0E8, 0xFFF00000);
+ syscon_writereg(0x0EC, 0xFFFFFFC0);
+ syscon_writereg(0x0F0, 0x000FFFFF);
+ syscon_writereg(0x0F4, 0xFFFFFFFF);
+ syscon_writereg(0x108, 0xFFFFFFFF);
+ syscon_writereg(0x10C, 0x0000003F);
+}
+
+// Brown Out Detect
+void enable_BOD(int enable)
+{
+ if (enable)
+ {
+ // Set BOD interrupt to 2.80-2.90V
+ LPC_SYSCON->BODCTRL |= 0x1C;
+ NVIC_EnableIRQ(BOD_IRQn); /* Enable BOD interrupt */
+ }
+ else
+ {
+ LPC_SYSCON->BODCTRL = 0x00;
+ NVIC_DisableIRQ(BOD_IRQn);
+ NVIC_ClearPendingIRQ(BOD_IRQn);
+ }
+}
+
+//Power off / shutdown sequence
+void power_off_sequence()
+{
+ // Disable Brown Out Detection
+ enable_BOD(0);
+
+ // Apply CS_nSRST
+ LPC_GPIO->CLR[PIN_nRESET_PORT] = PIN_nRESET;
+
+ // Wait 10ms
+ delay(10);
+
+ // Apply CB_nRST
+ LPC_GPIO->CLR[PIN_CB_nRST_PORT] = PIN_CB_nRST;
+ // Wait 10ms
+ delay(10);
+
+ // Apply CFG_nRST
+ LPC_GPIO->CLR[PIN_CFG_nRST_PORT] = PIN_CFG_nRST;
+
+ // Wait 10ms
+ delay(10);
+}
+
+//Power on sequence
+void power_on_sequence()
+{
+ // Drive SCC signals
+ LPC_GPIO->DIR[PIN_SCC_CLK_PORT] |= PIN_SCC_CLK;
+ LPC_GPIO->DIR[PIN_SCC_DATAIN_PORT] |= PIN_SCC_DATAIN;
+ LPC_GPIO->DIR[PIN_SCC_DATAOUT_PORT] &= ~PIN_SCC_DATAOUT;
+ LPC_GPIO->DIR[PIN_SCC_WNR_PORT] |= PIN_SCC_WNR;
+ LPC_GPIO->DIR[PIN_SCC_LOAD_PORT] |= PIN_SCC_LOAD;
+
+ // Wait 10ms
+ delay(10);
+
+ // Release CFG_nRST to allow SCC config
+ LPC_GPIO->SET[PIN_CFG_nRST_PORT] = PIN_CFG_nRST;
+
+ // Wait 10ms
+ delay(10);
+
+ // Configure SCC
+#if (defined MUSCA_B_BOOT_CODE_SRAM)
+ configure_syscon(MUSCA_B_S_CODE_SRAM_START);
+#elif (defined MUSCA_B_BOOT_EFLASH1)
+ configure_syscon(MUSCA_B_S_EFLASH1_START);
+#elif (defined MUSCA_B_BOOT_EFLASH0)
+ configure_syscon(MUSCA_B_S_EFLASH0_START);
+#elif (defined MUSCA_B_BOOT_QSPI_FLASH)
+ configure_syscon(MUSCA_B_S_FLASH_START);
+#endif
+
+ // Wait 10ms
+ delay(10);
+
+ // Release SCC signals
+ LPC_GPIO->DIR[PIN_SCC_CLK_PORT] &= ~PIN_SCC_CLK;
+ LPC_GPIO->DIR[PIN_SCC_DATAIN_PORT] &= ~PIN_SCC_DATAIN;
+ LPC_GPIO->DIR[PIN_SCC_DATAOUT_PORT] &= ~PIN_SCC_DATAOUT;
+ LPC_GPIO->DIR[PIN_SCC_WNR_PORT] &= ~PIN_SCC_WNR;
+ LPC_GPIO->DIR[PIN_SCC_LOAD_PORT] &= ~PIN_SCC_LOAD;
+
+ // Wait 10ms
+ delay(10);
+
+ // Release CB_nRST
+ LPC_GPIO->SET[PIN_CB_nRST_PORT] = PIN_CB_nRST;
+
+ // Wait 10ms
+ delay(10);
+
+ // Release CS_nSRST
+ LPC_GPIO->SET[PIN_nRESET_PORT] = PIN_nRESET;
+
+ // Wait 10ms
+ delay(10);
+
+ // Enable Brown Out Detection
+ enable_BOD(1);
+}
+
+// BOD Interrupt Service Routine
+void BOD_IRQHandler(void)
+{
+ NVIC_DisableIRQ(BOD_IRQn);
+ gpio_set_cdc_led(GPIO_LED_OFF); // ON GREEN
+
+ // go into controlled shutdown
+ power_off_sequence();
+
+ // Turn OFF power
+ i2cio_power_off();
+
+ while(1)
+ {
+ delay(100);
+ gpio_set_hid_led(GPIO_LED_ON);
+ delay(100);
+ gpio_set_hid_led(GPIO_LED_OFF);
+ }
+}
+
+// Function to wait till PBON button is pressed and released
+void wait_for_pbon(void)
+{
+ // Standby - wait for PBON
+ while (!gpio_get_pbon_btn())
+ {
+ // Do something with leds?
+ gpio_set_cdc_led(GPIO_LED_ON);
+ delay(100);
+ gpio_set_cdc_led(GPIO_LED_OFF);
+ delay(100);
+ }
+ // Wait for PBON to go low then high
+ while (gpio_get_pbon_btn())
+ {
+ // Do something with leds?
+ gpio_set_hid_led(GPIO_LED_ON);
+ delay(100);
+ gpio_set_hid_led(GPIO_LED_OFF);
+ delay(100);
+ }
+ // Wait 10ms
+ delay(10);
+
+}
diff -r 000000000000 -r 01f31e923fe2 source/family/arm/musca_b/power_ctrl.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/family/arm/musca_b/power_ctrl.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,38 @@ +/** + * @file power_ctrl.h + * @brief power control sequence logic for Musca A + * + * DAPLink Interface Firmware + * Copyright (c) 2018-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +void BOD_IRQHandler(void); + +void wait_for_pbon(void); + +void configure_syscon(unsigned int pc); + +void enable_BOD(int enable); + +void power_off_sequence(void); + +void power_on_sequence(void); + +void i2cio_power_off(void); + +void i2cio_power_on(void); + +void i2cio_init(void);
diff -r 000000000000 -r 01f31e923fe2 source/family/arm/musca_b/region_defs.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/family/arm/musca_b/region_defs.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,41 @@ +/** + * @file utils.h + * @brief Region defines for Musca B target + * + * DAPLink Interface Firmware + * Copyright (c) 2018-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#define MUSCA_B_NS_FLASH_START 0x00000000 +#define MUSCA_B_S_FLASH_START 0x10000000 +#define MUSCA_B_FLASH_SIZE MB(8) + +#define MUSCA_B_NS_EFLASH0_START 0x0A000000 +#define MUSCA_B_S_EFLASH0_START 0x1A000000 +#define MUSCA_B_EFLASH0_SIZE MB(2) + +#define MUSCA_B_NS_EFLASH1_START 0x0A200000 +#define MUSCA_B_S_EFLASH1_START 0x1A200000 +#define MUSCA_B_EFLASH1_SIZE MUSCA_B_EFLASH0_SIZE + +#define MUSCA_B_NS_CODE_SRAM_START 0x0A400000 +#define MUSCA_B_S_CODE_SRAM_START 0x1A400000 +#define MUSCA_B_CODE_SRAM_SIZE KB(512) + +#define MUSCA_B_NS_RAM_START 0x20000000 +#define MUSCA_B_S_RAM_START 0x30000000 +#define MUSCA_B_RAM_SIZE KB(512)
diff -r 000000000000 -r 01f31e923fe2 source/family/arm/musca_b/syscon.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/arm/musca_b/syscon.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,215 @@
+/**
+ * @file syscon.c
+ * @brief System Controller serial interface
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2008-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ctype.h> // character functions
+#include <string.h> // string and memory functions
+
+#include "IO_Config_Override.h" // I/O pin definitions
+
+#include "syscon.h" // SCC interface
+
+// SYSCON timing
+#define TSUH 2 // Clock setup and hold
+#define TCLK 2 // Clock high time
+
+// Misc defines
+#define GPIOIMSK 0x003F // GPIOI SCC bit mask
+
+/*----------------------------------------------------------------------------
+ System Controller serial interface
+ *----------------------------------------------------------------------------*/
+static void Sleepns(uint32_t cycles)
+{
+ volatile uint32_t i = cycles; // fudge factor to give approximate 1 ns
+
+ while (i > 0) {
+ i--;
+ }
+}
+/*----------------------------------------------------------------------------
+ System Controller 32bit register read (16uS)
+ *----------------------------------------------------------------------------*/
+void syscon_readreg(unsigned int addr, unsigned int *din)
+{
+ volatile unsigned int loop, data;
+
+ // Write the 12bit address value
+ for(loop = 0; loop < 12; loop++)
+ {
+ if (addr & 0x800)
+ {
+ LPC_GPIO->SET[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
+ }
+ else
+ {
+ LPC_GPIO->CLR[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
+ }
+ Sleepns(TCLK);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ // Set next address bit
+ addr = (addr << 1) & 0xFFF;
+ }
+
+ LPC_GPIO->CLR[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
+ Sleepns(TCLK);
+
+ // Config load
+ LPC_GPIO->SET[PIN_SCC_LOAD_PORT] = PIN_SCC_LOAD;
+ Sleepns(TCLK * 2);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK * 3);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ LPC_GPIO->CLR[PIN_SCC_LOAD_PORT] = PIN_SCC_LOAD;
+ Sleepns(TCLK * 2);
+
+ // Read the 32bit data value
+ data = 0;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ data = (data >> 8) & 0x00FFFFFF;
+ Sleepns(TCLK);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK * 2);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK);
+ data |= ((LPC_GPIO->PIN[PIN_SCC_DATAOUT_PORT] & PIN_SCC_DATAOUT) << (24 - PIN_SCC_DATAOUT_BIT));
+ Sleepns(TCLK);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK * 2);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK);
+ data |= ((LPC_GPIO->PIN[PIN_SCC_DATAOUT_PORT] & PIN_SCC_DATAOUT) << (25 - PIN_SCC_DATAOUT_BIT));
+ Sleepns(TCLK);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK * 2);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK);
+ data |= ((LPC_GPIO->PIN[PIN_SCC_DATAOUT_PORT] & PIN_SCC_DATAOUT) << (26 - PIN_SCC_DATAOUT_BIT));
+ Sleepns(TCLK);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK * 2);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK);
+ data |= ((LPC_GPIO->PIN[PIN_SCC_DATAOUT_PORT] & PIN_SCC_DATAOUT) << (27 - PIN_SCC_DATAOUT_BIT));
+ Sleepns(TCLK);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK * 2);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK);
+ data |= ((LPC_GPIO->PIN[PIN_SCC_DATAOUT_PORT] & PIN_SCC_DATAOUT) << (28 - PIN_SCC_DATAOUT_BIT));
+ Sleepns(TCLK);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK * 2);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK);
+ data |= ((LPC_GPIO->PIN[PIN_SCC_DATAOUT_PORT] & PIN_SCC_DATAOUT) << (29 - PIN_SCC_DATAOUT_BIT));
+ Sleepns(TCLK);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK * 2);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK);
+ data |= ((LPC_GPIO->PIN[PIN_SCC_DATAOUT_PORT] & PIN_SCC_DATAOUT) << (30 - PIN_SCC_DATAOUT_BIT));
+ Sleepns(TCLK);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK * 2);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK);
+ data |= ((LPC_GPIO->PIN[PIN_SCC_DATAOUT_PORT] & PIN_SCC_DATAOUT) << (31 - PIN_SCC_DATAOUT_BIT));
+ Sleepns(TCLK);
+ }
+
+ // Return the 32bit data value
+ *din = data;
+}
+
+/*----------------------------------------------------------------------------
+ System Controller 32bit register write (20uS)
+ *----------------------------------------------------------------------------*/
+void syscon_writereg(unsigned int addr, unsigned int dout)
+{
+ volatile unsigned int loop, data;
+
+ // Set write enable
+ LPC_GPIO->SET[PIN_SCC_WNR_PORT] = PIN_SCC_WNR;
+
+ // Write the 12bit address value
+ for(loop = 0; loop < 12; loop++)
+ {
+ if (addr & 0x800)
+ {
+ LPC_GPIO->SET[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
+ }
+ else
+ {
+ LPC_GPIO->CLR[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
+ }
+ Sleepns(TCLK);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ // Set next address bit
+ addr = (addr << 1) & 0xFFF;
+ }
+
+ LPC_GPIO->CLR[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
+ Sleepns(TCLK);
+
+ // Write the 32bit data value
+ data = dout;
+ for (loop = 0; loop < 32; loop++)
+ {
+ if (data & 0x80000000)
+ {
+ LPC_GPIO->SET[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
+ }
+ else
+ {
+ LPC_GPIO->CLR[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
+ }
+ Sleepns(TCLK);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ // Set next address bit
+ data = (data << 1);
+ Sleepns(TCLK);
+ }
+
+ LPC_GPIO->CLR[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
+ Sleepns(TCLK);
+
+ // Config load
+ LPC_GPIO->SET[PIN_SCC_LOAD_PORT] = PIN_SCC_LOAD;
+ Sleepns(TCLK * 2);
+ LPC_GPIO->SET[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ Sleepns(TCLK * 3);
+ LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
+ LPC_GPIO->CLR[PIN_SCC_LOAD_PORT] = PIN_SCC_LOAD;
+ Sleepns(TCLK * 2);
+
+ // Set to read
+ LPC_GPIO->CLR[PIN_SCC_WNR_PORT] = PIN_SCC_WNR;
+}
+
+// end of syscon.c
diff -r 000000000000 -r 01f31e923fe2 source/family/arm/musca_b/syscon.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/family/arm/musca_b/syscon.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,43 @@ +/** + * @file syscon.h + * @brief System Controller serial interface + * + * DAPLink Interface Firmware + * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __SYSCON_H +#define __SYSCON_H + +/* SCC registers */ +#define SCC_RESET_CTRL 0x00 // RESET Control register +#define SCC_CLK_CTRL 0x04 // CLOCK Control register +#define SCC_PWR_CTRL 0x08 // Power Control register +#define SCC_PLL_CTRL 0x0C // System Clock divider register +#define SCC_DBG_CTRL 0x10 // Debug Security override +#define SCC_SRAM_CTRL 0x14 // SRAM Bank power gate enable +#define SCC_INTR_CTRL 0x18 // Combined interrupt mask +#define SCC_CORDIO_CTRL 0x1C // REF to LLC Control and multiplex +#define SCC_CPU0_VTOR_SRAM 0x20 // CPU0 SRAM Boot vector +#define SCC_SPARE0 0x24 // CPU0 Spare +#define SCC_CPU1_VTOR_SRAM 0x28 // CPU1 SRAM Boot vector +#define SCC_SPARE1 0x2C // CPU1 Spare + +void syscon_readreg(unsigned int addr, unsigned int *din); +void syscon_writereg(unsigned int addr, unsigned int dout); + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/family/arm/musca_b/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/arm/musca_b/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,81 @@
+
+/**
+ * @file target.c
+ * @brief Target information for the Musca B qspi
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2016-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+#include "region_defs.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+
+ .flash_regions[0].start = (MUSCA_B_NS_FLASH_START),
+ .flash_regions[0].end = (MUSCA_B_NS_FLASH_START + MUSCA_B_FLASH_SIZE),
+#if (defined MUSCA_B_BOOT_QSPI_FLASH)
+ .flash_regions[0].flags = kRegionIsDefault,
+#endif
+ .flash_regions[0].flash_algo = (program_target_t *) &qspi_flash,
+
+ .flash_regions[1].start = (MUSCA_B_S_FLASH_START),
+ .flash_regions[1].end = (MUSCA_B_S_FLASH_START + MUSCA_B_FLASH_SIZE),
+ .flash_regions[1].flash_algo = (program_target_t *) &qspi_flash,
+
+ .flash_regions[2].start = (MUSCA_B_NS_EFLASH0_START),
+ .flash_regions[2].end = (MUSCA_B_NS_EFLASH0_START + MUSCA_B_EFLASH0_SIZE),
+ .flash_regions[2].flash_algo = (program_target_t *) &eflash,
+#if (defined MUSCA_B_BOOT_EFLASH0)
+ .flash_regions[2].flags = kRegionIsDefault,
+#endif
+
+ .flash_regions[3].start = (MUSCA_B_S_EFLASH0_START),
+ .flash_regions[3].end = (MUSCA_B_S_EFLASH0_START + MUSCA_B_EFLASH0_SIZE),
+ .flash_regions[3].flash_algo = (program_target_t *) &eflash,
+
+ .flash_regions[4].start = (MUSCA_B_NS_EFLASH1_START),
+ .flash_regions[4].end = (MUSCA_B_NS_EFLASH1_START + MUSCA_B_EFLASH1_SIZE),
+ .flash_regions[4].flash_algo = (program_target_t *) &eflash,
+#if (defined MUSCA_B_BOOT_EFLASH1)
+ .flash_regions[4].flags = kRegionIsDefault,
+#endif
+
+ .flash_regions[5].start = (MUSCA_B_S_EFLASH1_START),
+ .flash_regions[5].end = (MUSCA_B_S_EFLASH1_START + MUSCA_B_EFLASH1_SIZE),
+ .flash_regions[5].flash_algo = (program_target_t *) &eflash,
+
+ .flash_regions[6].start = (MUSCA_B_NS_CODE_SRAM_START),
+ .flash_regions[6].end = (MUSCA_B_NS_CODE_SRAM_START + MUSCA_B_CODE_SRAM_SIZE),
+#if (defined MUSCA_B_BOOT_CODE_SRAM)
+ .flash_regions[6].flags = kRegionIsDefault,
+#endif
+
+ .flash_regions[7].start = (MUSCA_B_S_CODE_SRAM_START),
+ .flash_regions[7].end = (MUSCA_B_S_CODE_SRAM_START + MUSCA_B_CODE_SRAM_SIZE),
+
+ .ram_regions[0].start = (MUSCA_B_NS_RAM_START),
+ .ram_regions[0].end = (MUSCA_B_NS_RAM_START + MUSCA_B_RAM_SIZE),
+ .ram_regions[1].start = (MUSCA_B_S_RAM_START),
+ .ram_regions[1].end = (MUSCA_B_S_RAM_START + MUSCA_B_RAM_SIZE),
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/arm/musca_b/target_reset.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/arm/musca_b/target_reset.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,167 @@
+/**
+ * @file target_reset.c
+ * @brief Target reset for Musca B target
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_family.h"
+#include "target_config.h" // for target_device
+#include "swd_host.h"
+#include "gpio.h"
+#include "i2c_gpio.h"
+#include "debug_cm.h"
+#include "utils.h"
+#include "power_ctrl.h"
+#include "uart.h"
+
+static void musca_b_target_before_init_debug(void)
+{
+ uint8_t buf[12];
+
+ // go into controlled shutdown
+ power_off_sequence();
+
+ // Drive SCC signals
+ LPC_GPIO->DIR[PIN_SCC_CLK_PORT] |= PIN_SCC_CLK;
+ LPC_GPIO->DIR[PIN_SCC_DATAIN_PORT] |= PIN_SCC_DATAIN;
+ LPC_GPIO->DIR[PIN_SCC_DATAOUT_PORT] &= ~PIN_SCC_DATAOUT;
+ LPC_GPIO->DIR[PIN_SCC_WNR_PORT] |= PIN_SCC_WNR;
+ LPC_GPIO->DIR[PIN_SCC_LOAD_PORT] |= PIN_SCC_LOAD;
+
+ // Wait 10ms
+ delay(10);
+
+ // Release CFG_nRST to allow SCC config
+ LPC_GPIO->SET[PIN_CFG_nRST_PORT] = PIN_CFG_nRST;
+
+ // Wait 10ms
+ delay(10);
+
+ // Configure SCC
+ configure_syscon(0x1A400000);
+
+ // Wait 10ms
+ delay(10);
+
+ // Creating branch to self in SRAM
+ buf[0] = 0x00;
+ buf[1] = 0x00;
+ buf[2] = 0x08;
+ buf[3] = 0x30;
+ buf[4] = 0x09;
+ buf[5] = 0x00;
+ buf[6] = 0x40;
+ buf[7] = 0x1A;
+ buf[8] = 0xFE;
+ buf[9] = 0xE7;
+ buf[10] = 0xFE;
+ buf[11] = 0xE7;
+
+ swd_write_memory(0x1A400000, (uint8_t *)buf, 12);
+
+// swd_write_word(0x1A400000, 0x30008000);
+// swd_write_word(0x1A400004, 0x1A400009);
+// swd_write_word(0x1A400008, 0xE7FEE7FE);
+
+ // Wait 10ms
+ delay(10);
+
+ // Release SCC signals
+ LPC_GPIO->DIR[PIN_SCC_CLK_PORT] &= ~PIN_SCC_CLK;
+ LPC_GPIO->DIR[PIN_SCC_DATAIN_PORT] &= ~PIN_SCC_DATAIN;
+ LPC_GPIO->DIR[PIN_SCC_DATAOUT_PORT] &= ~PIN_SCC_DATAOUT;
+ LPC_GPIO->DIR[PIN_SCC_WNR_PORT] &= ~PIN_SCC_WNR;
+ LPC_GPIO->DIR[PIN_SCC_LOAD_PORT] &= ~PIN_SCC_LOAD;
+
+ // Wait 10ms
+ delay(10);
+
+ // Release CB_nRST (nPORESET)
+ LPC_GPIO->SET[PIN_CB_nRST_PORT] = PIN_CB_nRST;
+
+ // Wait 10ms
+ delay(10);
+
+ // Release CS_nSRST
+ LPC_GPIO->SET[PIN_nRESET_PORT] = PIN_nRESET;
+
+ // Wait 10ms
+ delay(10);
+
+ return;
+}
+
+static uint8_t musca_b_target_set_state(target_state_t state)
+{
+ if(state == RESET_RUN)
+ {
+ // go through controlled reset
+ power_off_sequence();
+
+ power_on_sequence();
+
+ // Wait 10ms
+ delay(10);
+
+ swd_off();
+
+ return 1;
+ }
+ if(state == SHUTDOWN)
+ {
+ // go through controlled shutdown
+ power_off_sequence();
+
+ // Turn OFF power
+ i2cio_power_off();
+
+ // Wait 10ms
+ delay(10);
+
+ uart_reset();
+
+ return 1;
+ }
+ if(state == POWER_ON)
+ {
+ // Turn ON power
+ i2cio_power_on();
+
+ // Wait 10ms
+ delay(10);
+
+ // power on the target
+ power_on_sequence();
+
+ // Wait 10ms
+ delay(10);
+
+ swd_off();
+ return 1;
+ }
+
+ return swd_set_target_state_sw(state);
+}
+
+const target_family_descriptor_t g_target_family_musca_b = {
+ .target_before_init_debug = musca_b_target_before_init_debug,
+ .target_set_state = musca_b_target_set_state,
+ .apsel = 0x01000000,
+};
+
+const target_family_descriptor_t *g_target_family = &g_target_family_musca_b;
diff -r 000000000000 -r 01f31e923fe2 source/family/arm/musca_b/utils.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/arm/musca_b/utils.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,42 @@
+/**
+ * @file utils.c
+ * @brief Utilities for Musca B target
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2018-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "stdint.h"
+
+void delay(uint32_t cycles)
+{
+ volatile uint32_t i;
+ i = cycles * 4000; // fudge factor to give approximate 1 ms
+
+ while (i > 0) {
+ i--;
+ }
+}
+
+void delay_us(uint32_t cycles)
+{
+ volatile uint32_t i;
+ i = cycles * 4; // fudge factor to give approximate 1 us
+
+ while (i > 0) {
+ i--;
+ }
+}
diff -r 000000000000 -r 01f31e923fe2 source/family/arm/musca_b/utils.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/family/arm/musca_b/utils.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,24 @@ +/** + * @file utils.h + * @brief Utilities for Musca B target + * + * DAPLink Interface Firmware + * Copyright (c) 2018-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +void delay(uint32_t cycles); + +void delay_us(uint32_t cycles);
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/k20dx/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/k20dx/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,88 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the k20dx
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t K20D50M_FLM[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0xb510482c, 0x5120f24c, 0xf64d81c1, 0x81c11128, 0xf0218801, 0x80010101, 0x44484827, 0xf884f000,
+ 0xd0002800, 0xbd102001, 0x47702000, 0xb5104822, 0xf0004448, 0xb920f86f, 0x2100481f, 0xf0004448,
+ 0x491ef903, 0xf442684a, 0x604a0270, 0xb510bd10, 0x46014604, 0x22014818, 0xf0004448, 0xb930f831,
+ 0x23004815, 0x46212201, 0xf0004448, 0x4913f8b7, 0xf442684a, 0x604a0270, 0xb5febd10, 0x460b460c,
+ 0x46014606, 0x4615480c, 0xf0004448, 0xb958f87f, 0x21012000, 0x1000e9cd, 0x48079002, 0x4622462b,
+ 0x44484631, 0xf8dcf000, 0x684a4904, 0x0270f442, 0xbdfe604a, 0x40052000, 0x00000004, 0x4001f000,
+ 0x41f0e92d, 0x460d4614, 0xf846f000, 0xd11b2800, 0x1e64442c, 0xd00505a1, 0xeb012101, 0x1e422194,
+ 0x2481eb02, 0x447e4e09, 0x8024f8df, 0x42a52709, 0x6830d80a, 0xf8886005, 0xf0007007, 0x2800f8e9,
+ 0xf505d102, 0xe7f26580, 0x81f0e8bd, 0x00000236, 0x40020000, 0x4903b120, 0x71c82044, 0xb8d8f000,
+ 0x47702004, 0x40020000, 0x4916b190, 0x4a166cc9, 0x6103f3c1, 0xf832447a, 0x03091011, 0x2200d00a,
+ 0x2100e9c0, 0x60812101, 0x60c10289, 0x47704610, 0x47702004, 0x47702064, 0xea41b128, 0x079b0302,
+ 0x2065d003, 0x20044770, 0x68034770, 0xd804428b, 0x44116840, 0x42884418, 0x2066d201, 0x20004770,
+ 0x00004770, 0x40048000, 0x000001c8, 0x47f0e92d, 0x0014461d, 0xd01a460e, 0xf7ff461a, 0x2800ffdd,
+ 0x4f0cd116, 0xf8df447f, 0xf04fa030, 0x2d000806, 0x6838d00e, 0x68396006, 0x6048cc01, 0x8007f88a,
+ 0xf886f000, 0xd1032800, 0x1f2d1d36, 0x2004e7ef, 0x87f0e8bd, 0x00000178, 0x40020000, 0x47f0e92d,
+ 0x4614469a, 0x4605460e, 0xffb6f7ff, 0xd1252800, 0x0101e9d5, 0xf8f1fbb0, 0xf1c84271, 0x40010000,
+ 0x42b5424d, 0x4445d100, 0x1bafb1bc, 0xd90042a7, 0x480b4627, 0x447808b9, 0x60066800, 0x22014809,
+ 0x0a0a71c2, 0x728172c2, 0xa009f880, 0xf850f000, 0xd1032800, 0x443e1be4, 0x2000e7e5, 0x87f0e8bd,
+ 0x00000106, 0x40020000, 0x4804b128, 0x71c22240, 0xf0007181, 0x2004b83d, 0x00004770, 0x40020000,
+ 0x4df0e92d, 0xe9dd001c, 0x46168709, 0xd025460d, 0xff72f7ff, 0xd11f2800, 0xb04cf8df, 0xf8df44fb,
+ 0x2e00a04c, 0xf8dbd018, 0x600d1000, 0xf88a2202, 0x9a082007, 0x200bf88a, 0x0000f8db, 0x60816821,
+ 0xf816f000, 0xf1b8b160, 0xd0010f00, 0x5000f8c8, 0xd0012f00, 0x60392100, 0x8df0e8bd, 0xe7fb2004,
+ 0x1d241f36, 0xe7dc1d2d, 0x000000a0, 0x40020000, 0x2170480a, 0x21807001, 0x78017001, 0xd5fc0609,
+ 0x06817800, 0x2067d501, 0x06c14770, 0x2068d501, 0x07c04770, 0x2069d0fc, 0x00004770, 0x40020000,
+ 0x00000000, 0x00080000, 0x00100000, 0x00200000, 0x00400000, 0x00800000, 0x01000000, 0x01000000,
+ 0x40020004, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 1024},
+ };
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000049, // UnInit
+ 0x2000004D, // EraseChip
+ 0x2000006F, // EraseSector
+ 0x2000009B, // ProgramPage
+ 0x0, // Verify
+
+ // breakpoint = RAM start + 1
+ // RSB : base address is address of Execution Region PrgData in map file
+ // to access global/static data
+ // RSP : Initial stack pointer
+ {
+ 0x20000001, // breakpoint instruction address
+ 0x20000000 + 0x20 + 0x324, // static base register value (image start + header + static base offset)
+ 0x20000c00 // initial stack pointer
+ },
+
+ 0x20001c00, // program_buffer, any valid RAM location with +512 bytes of headroom
+ 0x20000000, // algo_start, start of RAM
+ sizeof(K20D50M_FLM), // algo_size, size of array above
+ K20D50M_FLM, // image, flash algo instruction array
+ 512 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/k20dx/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/k20dx/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the k20dx
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(128),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x1FFF8000,
+ .ram_regions[0].end = 0x20008000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/k22f/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/k22f/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,93 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t MK_P512_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0xb5104938, 0x60084449, 0xf24c4837, 0x81c15120, 0x1128f64d, 0x880181c1, 0x0101f021, 0x48348001,
+ 0x44484932, 0x2200f44f, 0x21006001, 0x1201e9c0, 0x52a0f04f, 0xf44f6142, 0x61825280, 0x1020f880,
+ 0x62411e49, 0xf939f000, 0xd0002800, 0xbd102001, 0x47702000, 0x4a27b508, 0x9200447a, 0x02cff3c1,
+ 0x48234601, 0x44482300, 0xf979f000, 0xd0002800, 0xbd082001, 0x491fb508, 0x481d4479, 0x44483920,
+ 0xf89ff000, 0xd10f2800, 0x4478481a, 0x38324b1a, 0x9000447b, 0x22044816, 0x410cf240, 0xf0004448,
+ 0x2800f911, 0x2001d000, 0x4b12bd08, 0x4601447b, 0x3b54480f, 0x6200f44f, 0xf0004448, 0xb508b8b6,
+ 0x1dc94613, 0x0207f021, 0x4479490a, 0x91003972, 0x48074601, 0xf0004448, 0x2800f8f5, 0x2001d000,
+ 0x0000bd08, 0x00000004, 0x40052000, 0x40020000, 0x00000008, 0x000000a1, 0x0000035c, 0x4604b570,
+ 0x25006800, 0x061b7803, 0x2370d5fc, 0x20007003, 0x280ce03a, 0xe8dfd236, 0x0a06f000, 0x1a16120e,
+ 0x2a26221e, 0x6826322e, 0x71f37813, 0x6826e02a, 0x71b37853, 0x6826e026, 0x71737893, 0x6826e022,
+ 0x713378d3, 0x6826e01e, 0x72f37913, 0x6826e01a, 0x72b37953, 0x6826e016, 0x72737993, 0x6826e012,
+ 0x723379d3, 0x6826e00e, 0x73f37a13, 0x6826e00a, 0x73b37a53, 0x6826e006, 0x73737a93, 0x6826e002,
+ 0x73337ad3, 0xb2c01c40, 0xd9c24288, 0x20806821, 0xe0037008, 0x1c416a60, 0x4780d000, 0x78006820,
+ 0xd5f70600, 0x78006820, 0xd5010681, 0xe0062504, 0xd50106c1, 0xe0022508, 0xd00007c0, 0x46282510,
+ 0xb508bd70, 0x460b2244, 0x2000f88d, 0x2100466a, 0xbd084798, 0x4614b538, 0xd002078a, 0x7080f44f,
+ 0x6843bd38, 0xd803428b, 0x441a6882, 0xd80c428a, 0x428b68c3, 0x6902d803, 0x428a441a, 0x2002d801,
+ 0x1ac9bd38, 0x0100f501, 0x1ac9e000, 0xf88d2208, 0x0c0a2000, 0x2001f88d, 0xf88d0a0a, 0xf88d2002,
+ 0x466a1003, 0x47a02103, 0xe92dbd38, 0x460745f8, 0x46164698, 0x2000687b, 0x428b198a, 0x68bcd803,
+ 0x4294441c, 0x68fbd20e, 0xd803428b, 0x441c693c, 0xd2024294, 0xe8bd2002, 0x1acc85f8, 0xf5042500,
+ 0xe0020400, 0xf44f1acc, 0xfbb46500, 0xfb05f1f5, 0xb1114111, 0x7080f44f, 0xfbb6e7ed, 0xfb05f1f5,
+ 0xb1a96111, 0xe7e62001, 0xa000f88d, 0xf88d0c20, 0x0a200001, 0x0002f88d, 0x4003f88d, 0x2103466a,
+ 0x46434638, 0x28004798, 0x1b76d1d5, 0xe001442c, 0x0a09f04f, 0xd1e72e00, 0x4601e7cd, 0x61082000,
+ 0x477061c8, 0x47fce92d, 0x46074616, 0x2000461d, 0xf8dd198a, 0x078b8028, 0xf44fd003, 0xe8bd7080,
+ 0x07b387fc, 0x2001d001, 0x687be7f9, 0xd803428b, 0x441c68bc, 0xd20c4294, 0x428b68fb, 0x693cd803,
+ 0x4294441c, 0x2002d201, 0x1acce7e9, 0x0400f504, 0x1acce000, 0x0a06f04f, 0xd0e02e00, 0xa000f88d,
+ 0xf88d0c20, 0x0a200001, 0x0002f88d, 0x4003f88d, 0xf88d78e8, 0x78a80004, 0x0005f88d, 0xf88d7868,
+ 0x78280006, 0x0007f88d, 0x2107466a, 0x46434638, 0x28004798, 0x1d24d1c3, 0x1f361d2d, 0xe92de7dc,
+ 0x684641fc, 0xeb019d08, 0x428e04c2, 0x6887d803, 0x428f4437, 0x68c7d80a, 0xd804428f, 0xc010f8d0,
+ 0x428f4467, 0x2002d802, 0x81fce8bd, 0xd80642a6, 0x44376887, 0xd30242a7, 0x24081b89, 0x68c6e00a,
+ 0xd90342a6, 0x44376907, 0xd3ec42a7, 0x24081b89, 0x0100f501, 0xf6f4fbb1, 0x1416fb04, 0xf44fb114,
+ 0xe7e17080, 0xf88d2401, 0x0c0c4000, 0x4001f88d, 0xf88d0a0c, 0xf88d4002, 0x0a111003, 0x1004f88d,
+ 0x2005f88d, 0x3006f88d, 0x2106466a, 0xe7cb47a8, 0xfffffffe, 0x00000000, 0xffffffff, 0xfffffffe,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000
+};
+
+// Start address of flash
+static const uint32_t flash_start = 0x00000000;
+// Size of flash
+static const uint32_t flash_size = 0x00080000;
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ { 0x00000000, 0x00000800 },
+};
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000071, // UnInit
+ 0x20000095, // EraseChip
+ 0x200000cb, // EraseSector
+ 0x200000df, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x20000420,
+ 0x20000700
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(MK_P512_flash_prog_blob), // prog_blob size
+ MK_P512_flash_prog_blob, // address of prog_blob
+ 0x00000200 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/k22f/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/k22f/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the k22f
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(512),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x1FFF0000,
+ .ram_regions[0].end = 0x20010000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/k28f/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/k28f/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,97 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the k66f
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t mk28f15_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0xb510482e, 0x5120f24c, 0xf64d81c1, 0x81c11128, 0xf0218801, 0x80010101, 0x44484829, 0xf856f000,
+ 0xbf182800, 0xbd102001, 0x47702000, 0xb5104824, 0x44484924, 0xf926f000, 0x4821b920, 0x44482100,
+ 0xf9daf000, 0x684a4920, 0x0270f442, 0xbd10604a, 0x4c1bb570, 0x444c4605, 0x4b1a4601, 0x68e24620,
+ 0xf88ef000, 0x2300b928, 0x46204629, 0xf00068e2, 0x4915f91f, 0xf442684a, 0x604a0270, 0xb570bd70,
+ 0x460b460c, 0x46014606, 0xb084480d, 0x44484615, 0xf8b8f000, 0x2000b958, 0xe9cd2101, 0x90021000,
+ 0x462b4807, 0x46314622, 0xf0004448, 0x4906f963, 0xf442684a, 0x604a0270, 0xbd70b004, 0x40052000,
+ 0x00000004, 0x6b65666b, 0x4001f000, 0xbf042800, 0x47702004, 0x6cc94926, 0x0e094a26, 0xf832447a,
+ 0x03091011, 0x2064bf04, 0x22004770, 0x2100e9c0, 0x60812104, 0x60c10289, 0x780b491f, 0x7c80f44f,
+ 0xf303fa0c, 0x78c96103, 0x1205e9c0, 0x47704610, 0xbf0e2800, 0x61812004, 0x47702000, 0xbf042800,
+ 0x47702004, 0x42191e5b, 0x421abf0e, 0x47702065, 0x428b6803, 0x6840d806, 0x44184411, 0xbf244288,
+ 0x47702000, 0x47702066, 0x4288490c, 0x206bbf14, 0x47702000, 0x290fb140, 0x2a04d802, 0xe005d104,
+ 0xbf982913, 0xd0012a08, 0x47702004, 0x47702000, 0x40048000, 0x0000036c, 0x40020028, 0x6b65666b,
+ 0x4df0e92d, 0x46154606, 0x4618460c, 0xffdcf7ff, 0xbf182800, 0x8df0e8bd, 0x462a2310, 0x46304621,
+ 0xffbcf7ff, 0xbf180007, 0x8df0e8bd, 0x1e451960, 0xfbb568f0, 0xfb00f1f0, 0xb1125211, 0x43481c49,
+ 0x42ac1e45, 0xf8dfd817, 0x44f88034, 0xb030f8df, 0x0a09f04f, 0x0000f8d8, 0xf88b6004, 0xf000a007,
+ 0x4607f917, 0x280069b0, 0x4780bf18, 0x68f0b91f, 0x42ac4404, 0x4638d9ee, 0x8df0e8bd, 0x0000027a,
+ 0x40020000, 0xbf042a00, 0x47702004, 0x4df0e92d, 0x4614461d, 0x4607460e, 0x462a2308, 0xff7ef7ff,
+ 0x0b00ea5f, 0xe8bdbf18, 0x2d008df0, 0xf8dfbf1e, 0x44f8804c, 0x0a07f04f, 0xf8d8d01c, 0x60060000,
+ 0x1000f8d8, 0x0b04f854, 0xf8d86048, 0xf8541000, 0x60880b04, 0xf880480a, 0xf000a007, 0x4683f8d9,
+ 0x280069b8, 0x4780bf18, 0x0f00f1bb, 0x3608d102, 0xd1e23d08, 0xe8bd4658, 0x00008df0, 0x00000212,
+ 0x40020000, 0x4604b510, 0xf7ff4608, 0x2800ff5d, 0xbd10bf18, 0xbf042c00, 0xbd102004, 0x49032044,
+ 0xe8bd71c8, 0xf0004010, 0x0000b8b3, 0x40020000, 0x4df0e92d, 0x4614469a, 0x4605460e, 0xf7ff2310,
+ 0x2800ff2d, 0xe8bdbf18, 0xe9d58df0, 0xfbb00101, 0x4270f8f1, 0x0100f1c8, 0x42474008, 0xbf0842b7,
+ 0x2c004447, 0xf8dfbf18, 0xd01cb044, 0x42a51bbd, 0x4625bf88, 0x490e0928, 0x68094479, 0x2101600e,
+ 0x1007f88b, 0xf88b0a01, 0xf88b100b, 0xf88b000a, 0xf000a009, 0x2800f87d, 0xe8bdbf18, 0x1b648df0,
+ 0x4447442e, 0x2000d1e2, 0x8df0e8bd, 0x40020000, 0x0000014c, 0xbf122800, 0x20042a00, 0x29084770,
+ 0xe8dfd215, 0x0604f001, 0x0c0a0806, 0x68c0100e, 0x6840e00a, 0x6880e008, 0x6800e006, 0x2001e004,
+ 0x6900e002, 0x6940e000, 0x20006010, 0x206a4770, 0x00004770, 0xbf042b00, 0x47702004, 0x4df0e92d,
+ 0xe9dd461c, 0x46158709, 0x2304460e, 0xa020f8dd, 0xfec4f7ff, 0xbf182800, 0x8df0e8bd, 0xbf1a2d00,
+ 0xb04cf8df, 0xe8bd44fb, 0xf8db8df0, 0x60060000, 0x21024810, 0xf88071c1, 0xf8dba00b, 0x68201000,
+ 0xf0006088, 0xb150f825, 0x0f00f1b8, 0xf8c8bf18, 0x2f006000, 0x2100bf1c, 0xe8bd6039, 0x1f2d8df0,
+ 0x0404f104, 0x0604f106, 0xe8bdd1df, 0x00008df0, 0x000000a0, 0x40020000, 0xbf042800, 0x47702004,
+ 0x48022240, 0x718171c2, 0xb802f000, 0x40020000, 0x2170480c, 0x21807001, 0x78017001, 0x0f80f011,
+ 0x7800d0fb, 0x0f20f010, 0x2067bf1c, 0xf0104770, 0xbf1c0f10, 0x47702068, 0x0001f010, 0x2069bf18,
+ 0x00004770, 0x40020000, 0x40020004, 0x00000000, 0x00080000, 0x00100000, 0x00200000, 0x00400000,
+ 0x00800000, 0x01000000, 0x02000000, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ { 0, 4096 },
+};
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000049, // UnInit
+ 0x2000004D, // EraseChip
+ 0x20000071, // EraseSector
+ 0x2000009F, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000000 + 0x00000001,
+ 0x20000000 + 0x00000020 + 0x0000046c,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(mk28f15_flash_prog_blob), // prog_blob size
+ mk28f15_flash_prog_blob, // address of prog_blob
+ 0x00000200 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/k28f/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/k28f/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the k66f
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = MB(2),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x1FFC0000,
+ .ram_regions[0].end = 0x20040000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/k32w042/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/k32w042/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,134 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t k32w042s1m2_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x4838b510, 0x60414936, 0x60814937, 0x22806801, 0x22204391, 0x60014311, 0x69014834, 0x0f890589,
+ 0xd01c2902, 0x4a322100, 0x444a2900, 0xd0087011, 0x22036901, 0x43910212, 0x69016101, 0x0f890589,
+ 0x482cd1fb, 0x22016841, 0x43110792, 0x482a6041, 0xf0004448, 0x2800f855, 0x2001d000, 0x2101bd10,
+ 0x4823e7e1, 0x78004448, 0xd00d2800, 0x6901481f, 0x02122203, 0x31ff4391, 0x310231ff, 0x69016101,
+ 0x0f890589, 0xd1fa2902, 0x47702000, 0xb510481a, 0x4448491a, 0xf93af000, 0x4601bd10, 0xb5104816,
+ 0x22104b16, 0xf0004448, 0xbd10f8e4, 0x460cb570, 0x4606460b, 0x48104601, 0x4615b084, 0xf0004448,
+ 0x2800f963, 0x9001d10a, 0x21019002, 0x9100480a, 0x4622462b, 0x44484631, 0xfb0bf000, 0xbd70b004,
+ 0xd928c520, 0x4002a000, 0x0000ffff, 0x40020000, 0x00000004, 0x4002b000, 0x00000008, 0x6b65666b,
+ 0xd00a2800, 0x68c949fe, 0x290f0f09, 0x4afdd007, 0x447a0049, 0x02895a51, 0x2004e003, 0x21014770,
+ 0xb4300509, 0x60032300, 0x21026041, 0x02cc7201, 0x49f560c4, 0x158a7a45, 0xd00c2d01, 0x40aa7b0d,
+ 0x7b496142, 0x61816103, 0x06c92109, 0x62016244, 0x2000bc30, 0x7b8d4770, 0x614240aa, 0xe7f17bc9,
+ 0xd0022800, 0x20006101, 0x20044770, 0x48e74770, 0x49e76800, 0x42880a00, 0x48e6d101, 0x48e6e000,
+ 0x22016801, 0x60014311, 0x8f6ff3bf, 0x8f4ff3bf, 0xb5104770, 0xf0002101, 0xbd10fb82, 0x217048df,
+ 0x21807001, 0x78017001, 0xd5fc0609, 0x06817800, 0x2067d501, 0x06c14770, 0x2068d501, 0x07c04770,
+ 0x2069d0fc, 0x28004770, 0x2004d101, 0xb5704770, 0x4ad24604, 0x605048d2, 0x428148d2, 0x206bd001,
+ 0x2000e000, 0xd10c2800, 0x46202100, 0xfb57f000, 0xf7ff4620, 0x4605ffd3, 0x46202101, 0xfb4ff000,
+ 0xbd704628, 0xd0012800, 0xd1012a00, 0x47702004, 0x2000b410, 0x60906050, 0x611060d0, 0x61906150,
+ 0x621061d0, 0x23ff6250, 0x061b0248, 0x0a4018cc, 0x04892101, 0x60102308, 0xd209428c, 0x4320014c,
+ 0x01886010, 0x60d06111, 0x60911340, 0xe0066050, 0x05002001, 0x12006110, 0x01c06050, 0x20106090,
+ 0x61536190, 0x61d06213, 0x62502004, 0x2000bc10, 0xb5ff4770, 0x4615b08d, 0x460e461c, 0x980daa02,
+ 0xffc0f7ff, 0x9000a802, 0x4631462a, 0x980d9b08, 0xfb19f000, 0xd1082800, 0x428448a2, 0x266bd001,
+ 0x2600e000, 0xd0022e00, 0xb0114630, 0x9c02bdf0, 0x19659f03, 0x46391e6d, 0xf0004628, 0x2900fb37,
+ 0x1c40d002, 0x1e454378, 0x980d2100, 0xfae7f000, 0xd81442ac, 0x20090221, 0x06000a09, 0x488f1809,
+ 0x980d6041, 0xff5af7ff, 0x980d4606, 0x28006900, 0x4780d000, 0xd1022e00, 0x42ac19e4, 0x2101d9ea,
+ 0xf000980d, 0x4630facc, 0xbdf0b011, 0xd1012800, 0x47702004, 0x4604b570, 0x48834a80, 0x48816050,
+ 0xd0014281, 0xe000206b, 0x28002000, 0x2100d10c, 0xf0004620, 0x4620fab4, 0xff30f7ff, 0x21014605,
+ 0xf0004620, 0x4628faac, 0x2800bd70, 0x2004d101, 0xb5704770, 0x4a714604, 0x60504874, 0x42814871,
+ 0x206bd001, 0x2000e000, 0xd10c2800, 0x46202100, 0xfa95f000, 0xf7ff4620, 0x4605ff11, 0x46202101,
+ 0xfa8df000, 0xbd704628, 0xd1012a00, 0x47702004, 0xb08db5ff, 0x461e4614, 0xaa02460d, 0xf7ff980d,
+ 0xa802ff31, 0x46329000, 0x9b074629, 0xf000980d, 0x0007fa8a, 0x2100d132, 0x980d9d02, 0xfa6ff000,
+ 0xd0262e00, 0x4855cc02, 0x99076081, 0xd0022904, 0xd0072908, 0x022ae00e, 0x0a122103, 0x18510649,
+ 0xe0076041, 0x60c1cc02, 0x2107022a, 0x06090a12, 0x60411851, 0xf7ff980d, 0x4607fed1, 0x6900980d,
+ 0xd0002800, 0x2f004780, 0x9807d103, 0x1a361945, 0x2101d1d8, 0xf000980d, 0x4638fa42, 0xbdf0b011,
+ 0xd0012800, 0xd1012a00, 0x47702004, 0x4604b570, 0x0a010608, 0x1809483e, 0x60414838, 0x60816811,
+ 0x60c16851, 0x46202100, 0xfa29f000, 0xf7ff4620, 0x4605fea5, 0x46202101, 0xfa21f000, 0xbd704628,
+ 0xb08db5ff, 0x460c980f, 0xd02a2800, 0x980daa02, 0xfec8f7ff, 0x9000a802, 0x9b094621, 0x980d9a10,
+ 0xfa21f000, 0x28009000, 0x9803d11c, 0x9e029001, 0x980d2100, 0xfa03f000, 0x28009810, 0x9801d06b,
+ 0x900c4240, 0x4270990c, 0x42404008, 0x42b02500, 0x9901d101, 0x99101840, 0x42811989, 0x1b84d904,
+ 0x2004e003, 0xbdf0b011, 0x2c009c10, 0x2701d049, 0x42bc02bf, 0x4627d800, 0x980f08a9, 0x18090089,
+ 0x463a2009, 0xf00006c0, 0x1970fa37, 0x200b0201, 0x06000a09, 0x48091809, 0x46386041, 0xe0199909,
+ 0x40026040, 0x00000872, 0x40023020, 0x40001000, 0x00434d30, 0xf0003034, 0xe0080034, 0x40023000,
+ 0x44ffffff, 0x6b65666b, 0x49ffffff, 0x4bffffff, 0x4300ffff, 0xf9faf000, 0x48f10401, 0x48f11809,
+ 0x980d6081, 0xfe2af7ff, 0x980d9000, 0x28006900, 0x4780d000, 0x28009800, 0x1be4d10d, 0x2c0019ed,
+ 0x08a9d1b5, 0x0089980f, 0x900f1808, 0x19769810, 0x90101b40, 0x2101d196, 0xf000980d, 0x9800f990,
+ 0xbdf0b011, 0xd0012800, 0xd1012a00, 0x47702004, 0x4614b570, 0x4adc0609, 0x4dda0a09, 0x60691889,
+ 0xfdfcf7ff, 0xd1032800, 0x602168a9, 0x606168e9, 0x2800bd70, 0x2900d00e, 0x48d2d00c, 0x07827880,
+ 0x2a020f92, 0x0980d008, 0xd0082802, 0x70082002, 0x47702000, 0x47702004, 0x70082000, 0x2001e7f8,
+ 0x2800e7f5, 0x2900d001, 0x2004d101, 0xb5704770, 0x23004dc4, 0x079278aa, 0x2a020f92, 0x4ac3d026,
+ 0x780c606a, 0x462278cb, 0x061b784c, 0x43220224, 0x0424788c, 0x431a4322, 0x0a12ba12, 0x021278cb,
+ 0x60aa431a, 0x79cb790c, 0x794c4622, 0x0224061b, 0x798c4322, 0x042479c9, 0x431a4322, 0x0a12ba12,
+ 0x430a0212, 0xf7ff60ea, 0x4603fda9, 0xbd704618, 0xd1012800, 0x47702004, 0x04094aad, 0xb5101889,
+ 0x60514aa8, 0xfd9af7ff, 0xb5ffbd10, 0x4614b08d, 0x460d461e, 0x980daa02, 0xfdc4f7ff, 0x9000a802,
+ 0x46294622, 0x980d9b09, 0xf91df000, 0xd12e2800, 0x98049d02, 0x42699000, 0x40014240, 0x42af424f,
+ 0x9800d101, 0x2c00183f, 0x0230d020, 0x1b7e9001, 0xd90042a6, 0x46304626, 0xf0009909, 0x022af937,
+ 0x0a122101, 0x18520609, 0x604a498e, 0x04009a01, 0x30ff4310, 0x980d6088, 0xfd60f7ff, 0xd1062800,
+ 0x1ba49800, 0x183f19ad, 0xd1e02c00, 0xb0112000, 0x2b00bdf0, 0x2004d101, 0xb5ff4770, 0x4616b08d,
+ 0x460c461d, 0x9f16aa02, 0xf7ff980d, 0xa802fd7b, 0x46329000, 0x9b0b4621, 0xf000980d, 0x2800f8d4,
+ 0x9c02d11d, 0xd01a2e00, 0x0638497a, 0x02211847, 0x0a092001, 0x18090640, 0x60414872, 0x68296087,
+ 0x980d60c1, 0xfd2af7ff, 0xd00a2800, 0x29009917, 0x600cd000, 0x29009918, 0x2200d001, 0xb011600a,
+ 0x990bbdf0, 0x08891a76, 0x194d0089, 0x190c990b, 0xd1dc2e00, 0xbdf0b011, 0xd1012800, 0x47702004,
+ 0x04094a65, 0xb5101889, 0x60514a5e, 0xfd06f7ff, 0x2800bd10, 0x2a00d001, 0x2004d101, 0xb5104770,
+ 0x290a4614, 0x000ad222, 0x7912447a, 0x44971892, 0x0d080604, 0x1513110f, 0x68c01917, 0x6840e013,
+ 0x7a01e011, 0xf0006840, 0xe00cf8b1, 0xe00a7a00, 0xe0086800, 0xe0062001, 0xe0046940, 0xe0026980,
+ 0xe0006a00, 0x60206a40, 0xbd102000, 0xbd10206a, 0x28002300, 0x2004d101, 0xb4104770, 0xd0232906,
+ 0x2905dc02, 0xe01fd80d, 0xd01d2909, 0x2907dc04, 0x2908d01a, 0xe017d105, 0x2920b2d4, 0x2921d005,
+ 0x236ad009, 0x4618bc10, 0x2a004770, 0x2a01d001, 0x7244d105, 0x2a00e7f6, 0x2a01d004, 0xbc10d002,
+ 0x47702077, 0xe7ed7284, 0xe7eb2376, 0xd00e2800, 0x680a482c, 0x680a61c2, 0x429a69c3, 0x684ad105,
+ 0x68496182, 0x42816980, 0x2069d003, 0x20044770, 0x20004770, 0x28004770, 0x2900d008, 0x4821d006,
+ 0x600a69c2, 0x60486980, 0x47702000, 0x47702004, 0x47702000, 0x70012100, 0x46087041, 0x29014770,
+ 0x481ed110, 0x491e6800, 0x42880a00, 0x481dd101, 0x481de000, 0x22016801, 0x60014311, 0x8f6ff3bf,
+ 0x8f4ff3bf, 0x28004770, 0x2004d101, 0xb4104770, 0x9c011e5b, 0xd1014219, 0xd002421a, 0x2065bc10,
+ 0x68e04770, 0xd8074288, 0x18896923, 0x428818c0, 0xbc10d302, 0x47702000, 0x2066bc10, 0x00004770,
+ 0x0000ffff, 0x40023000, 0x4100ffff, 0x45ffffff, 0x4000ffff, 0x00ffffff, 0x4a00ffff, 0x40001000,
+ 0x00434d30, 0xf0003034, 0xe0080034, 0x460bb530, 0x20004601, 0x24012220, 0x460de009, 0x429d40d5,
+ 0x461dd305, 0x1b494095, 0x40954625, 0x46151940, 0x2d001e52, 0xbd30dcf1, 0x430b4603, 0xd003079b,
+ 0xc908e009, 0xc0081f12, 0xd2fa2a04, 0x780be003, 0x1c407003, 0x1e521c49, 0x4770d2f9, 0x40023004,
+ 0x4002301c, 0x40023018, 0x00100008, 0x00200018, 0x00400030, 0x00800060, 0x010000c0, 0x02000180,
+ 0x04000300, 0x00000600, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x00000000, 0x00001000},
+ };
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000083, // UnInit
+ 0x200000ad, // EraseChip
+ 0x200000bb, // EraseSector
+ 0x200000cd, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x200009c8,
+ 0x20001400
+ },
+
+ 0x20000000 + 0x00002000, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(k32w042s1m2_flash_prog_blob), // prog_blob size
+ k32w042s1m2_flash_prog_blob, // address of prog_blob
+ 0x00000400 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/k32w042/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/k32w042/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the k32w042
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(1024),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000, // M4 DTCM
+ .ram_regions[0].end = 0x20030000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/k64f/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/k64f/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,101 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t mk64f12_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0xb510483e, 0x5120f24c, 0xf64d81c1, 0x81c11128, 0xf0218801, 0x80010101, 0x78414839, 0x0160f001,
+ 0xbf0c2940, 0x21002101, 0x444a4a36, 0xb1397011, 0xf0217841, 0x70410160, 0xf0117841, 0xd1fb0f60,
+ 0x44484831, 0xf864f000, 0xbf182800, 0xbd102001, 0x4448482c, 0xb1587800, 0x78414829, 0x0160f021,
+ 0x0140f041, 0x78417041, 0x0160f001, 0xd1fa2940, 0x47702000, 0xb5104824, 0x44484924, 0xf891f000,
+ 0xbf182800, 0x2100bd10, 0xe8bd481f, 0x44484010, 0xb958f000, 0x4c1cb570, 0x444c4605, 0x4b1b4601,
+ 0x68e24620, 0xf8b6f000, 0xbf182800, 0x2300bd70, 0x68e24629, 0x4070e8bd, 0x44484813, 0xb94cf000,
+ 0x460cb570, 0x4606460b, 0x480f4601, 0x4615b084, 0xf0004448, 0x2800f8eb, 0xb004bf1c, 0x2000bd70,
+ 0xe9cd2101, 0x90021000, 0x462b4807, 0x46314622, 0xf0004448, 0xb004f97f, 0x0000bd70, 0x40052000,
+ 0x4007e000, 0x00000004, 0x00000008, 0x6b65666b, 0xbf042800, 0x47702004, 0x6cc949ea, 0x6103f3c1,
+ 0xbf08290f, 0x1180f44f, 0x4ae7bf1f, 0xf832447a, 0x02891011, 0xe9c02200, 0x21022100, 0x61426081,
+ 0x618202c9, 0x1203e9c0, 0x52a0f04f, 0x2108e9c0, 0x47702000, 0xbf0e2800, 0x61012004, 0x47702000,
+ 0x48da4602, 0x49d96840, 0x0070f440, 0x47706048, 0x217048d7, 0x21807001, 0x78017001, 0x0f80f011,
+ 0x7800d0fb, 0x0f20f010, 0x2067bf1c, 0xf0104770, 0xbf1c0f10, 0x47702068, 0x0001f010, 0x2069bf18,
+ 0x28004770, 0x2004bf04, 0xb5104770, 0x4ac84604, 0x403bf06f, 0x48c76050, 0xbf144281, 0x2000206b,
+ 0xbf182800, 0x4620bd10, 0xffd2f7ff, 0x46204603, 0xffc6f7ff, 0xbd104618, 0xbf042800, 0x47702004,
+ 0x60532300, 0x60d36093, 0x61536113, 0x61d36193, 0x68c16011, 0xe9d06051, 0xfbb11001, 0x6090f0f0,
+ 0x21102008, 0x0103e9c2, 0x1005e9c2, 0x61d02004, 0x47702000, 0x4df0e92d, 0x4615b088, 0x460c4698,
+ 0x466a4682, 0xffd8f7ff, 0x4621462a, 0x9b044650, 0xf931f000, 0xbf1c0007, 0xe8bdb008, 0xe9dd8df0,
+ 0x19604600, 0xfbb51e45, 0xfb06f0f6, 0xb1205010, 0xf0f6fbb5, 0x43701c40, 0x42ac1e45, 0xf8dfbf98,
+ 0xd81cb270, 0x407ff024, 0x6010f040, 0x0004f8cb, 0x45804898, 0x206bbf14, 0x28002000, 0xb008bf1c,
+ 0x8df0e8bd, 0xf7ff4650, 0x4607ff73, 0x0010f8da, 0xbf182800, 0xb9174780, 0x42ac4434, 0x4650d9e2,
+ 0xff5ef7ff, 0x4638b008, 0x8df0e8bd, 0xbf042a00, 0x47702004, 0x45f0e92d, 0x4614b089, 0x460d461e,
+ 0x466a4680, 0xff88f7ff, 0x46294632, 0x9b034640, 0xf8e1f000, 0xbf1c0007, 0xe8bdb009, 0x9d0085f0,
+ 0xbf182e00, 0xa1e8f8df, 0xf854d025, 0xf8ca0b04, 0x98030008, 0xbf042804, 0x407ff025, 0x60c0f040,
+ 0x2808d009, 0xf854d109, 0xf8ca0b04, 0xf025000c, 0xf040407f, 0xf8ca60e0, 0x46400004, 0xff28f7ff,
+ 0x1010f8d8, 0x29004607, 0x4788bf18, 0x9803b91f, 0x1a364405, 0x4640d1d9, 0xff12f7ff, 0x4638b009,
+ 0x85f0e8bd, 0xbf042800, 0x47702004, 0xea424a62, 0x4a5f4101, 0xe70b6051, 0x4dffe92d, 0x4614b088,
+ 0x460d469a, 0x9808466a, 0xff36f7ff, 0x46294622, 0x98089b05, 0xf88ff000, 0xbf1c2800, 0xe8bdb00c,
+ 0x466a8df0, 0x98084629, 0xff26f7ff, 0xf8dd9e00, 0x42708008, 0x0100f1c8, 0x42474008, 0xbf0842b7,
+ 0x2c004447, 0xf8dfbf18, 0xd01fb128, 0x42a51bbd, 0x4625bf88, 0xf0269805, 0xfbb5417f, 0xf041f0f0,
+ 0xf8cb7180, 0x04001004, 0x200aea40, 0x00fff040, 0x0008f8cb, 0xf7ff9808, 0x2800fecb, 0xb00cbf1c,
+ 0x8df0e8bd, 0x442e1b64, 0xd1df4447, 0x2000b00c, 0x8df0e8bd, 0xbf042b00, 0x47702004, 0x4dffe92d,
+ 0x4616b088, 0x7a14e9dd, 0x460c461d, 0xf8dd466a, 0x98088058, 0xfee0f7ff, 0x3007e9dd, 0x46214632,
+ 0xf839f000, 0xbf1c2800, 0xe8bdb00c, 0x9c008df0, 0xbf042e00, 0xe8bdb00c, 0xf8df8df0, 0xf06fb094,
+ 0xea40407f, 0xf0246707, 0xf040407f, 0xf8cb7000, 0xf8cb0004, 0x68287008, 0x000cf8cb, 0xf7ff9808,
+ 0xb168fe87, 0x0f00f1ba, 0xf8cabf18, 0xf1b84000, 0xbf1c0f00, 0xf8c82100, 0xb00c1000, 0x8df0e8bd,
+ 0x1a769907, 0x0103f021, 0x9907440d, 0xd1da440c, 0xe8bdb00c, 0x28008df0, 0x2004bf04, 0xf1a34770,
+ 0x42190301, 0x421abf0e, 0x47702065, 0x428b6803, 0x6840d806, 0x44184411, 0xbf244288, 0x47702000,
+ 0x47702066, 0x40048000, 0x000003b4, 0x4001f000, 0x40020000, 0x6b65666b, 0x4000ffff, 0x40020004,
+ 0x40020010, 0x00100008, 0x00200018, 0x00400030, 0x00800060, 0x010000c0, 0x02000180, 0x04000300,
+ 0x00000600, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+};
+
+// Start address of flash
+static const uint32_t flash_start = 0x00000000;
+// Size of flash
+static const uint32_t flash_size = 0x00100000;
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ { 0x00000000, 0x00001000 },
+};
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000071, // UnInit
+ 0x20000095, // EraseChip
+ 0x200000b5, // EraseSector
+ 0x200000e1, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x20000524,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(mk64f12_flash_prog_blob), // prog_blob size
+ mk64f12_flash_prog_blob, // address of prog_blob
+ 0x00000400 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/k64f/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/k64f/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the k64f
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x00000000,
+ .flash_regions[0].end = 0x00100000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x1fff0000,
+ .ram_regions[0].end = 0x20030000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/k66f/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/k66f/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,97 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the k66f
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t mk66f18_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0xb510482e, 0x5120f24c, 0xf64d81c1, 0x81c11128, 0xf0218801, 0x80010101, 0x44484829, 0xf856f000,
+ 0xbf182800, 0xbd102001, 0x47702000, 0xb5104824, 0x44484924, 0xf926f000, 0x4821b920, 0x44482100,
+ 0xf9daf000, 0x684a4920, 0x0270f442, 0xbd10604a, 0x4c1bb570, 0x444c4605, 0x4b1a4601, 0x68e24620,
+ 0xf88ef000, 0x2300b928, 0x46204629, 0xf00068e2, 0x4915f91f, 0xf442684a, 0x604a0270, 0xb570bd70,
+ 0x460b460c, 0x46014606, 0xb084480d, 0x44484615, 0xf8b8f000, 0x2000b958, 0xe9cd2101, 0x90021000,
+ 0x462b4807, 0x46314622, 0xf0004448, 0x4906f963, 0xf442684a, 0x604a0270, 0xbd70b004, 0x40052000,
+ 0x00000004, 0x6b65666b, 0x4001f000, 0xbf042800, 0x47702004, 0x6cc94926, 0x0e094a26, 0xf832447a,
+ 0x03091011, 0x2064bf04, 0x22004770, 0x2100e9c0, 0x60812104, 0x60c10289, 0x780b491f, 0x7c80f44f,
+ 0xf303fa0c, 0x78c96103, 0x1205e9c0, 0x47704610, 0xbf0e2800, 0x61812004, 0x47702000, 0xbf042800,
+ 0x47702004, 0x42191e5b, 0x421abf0e, 0x47702065, 0x428b6803, 0x6840d806, 0x44184411, 0xbf244288,
+ 0x47702000, 0x47702066, 0x4288490c, 0x206bbf14, 0x47702000, 0x290fb140, 0x2a04d802, 0xe005d104,
+ 0xbf982913, 0xd0012a08, 0x47702004, 0x47702000, 0x40048000, 0x0000036c, 0x40020028, 0x6b65666b,
+ 0x4df0e92d, 0x46154606, 0x4618460c, 0xffdcf7ff, 0xbf182800, 0x8df0e8bd, 0x462a2310, 0x46304621,
+ 0xffbcf7ff, 0xbf180007, 0x8df0e8bd, 0x1e451960, 0xfbb568f0, 0xfb00f1f0, 0xb1125211, 0x43481c49,
+ 0x42ac1e45, 0xf8dfd817, 0x44f88034, 0xb030f8df, 0x0a09f04f, 0x0000f8d8, 0xf88b6004, 0xf000a007,
+ 0x4607f917, 0x280069b0, 0x4780bf18, 0x68f0b91f, 0x42ac4404, 0x4638d9ee, 0x8df0e8bd, 0x0000027a,
+ 0x40020000, 0xbf042a00, 0x47702004, 0x4df0e92d, 0x4614461d, 0x4607460e, 0x462a2308, 0xff7ef7ff,
+ 0x0b00ea5f, 0xe8bdbf18, 0x2d008df0, 0xf8dfbf1e, 0x44f8804c, 0x0a07f04f, 0xf8d8d01c, 0x60060000,
+ 0x1000f8d8, 0x0b04f854, 0xf8d86048, 0xf8541000, 0x60880b04, 0xf880480a, 0xf000a007, 0x4683f8d9,
+ 0x280069b8, 0x4780bf18, 0x0f00f1bb, 0x3608d102, 0xd1e23d08, 0xe8bd4658, 0x00008df0, 0x00000212,
+ 0x40020000, 0x4604b510, 0xf7ff4608, 0x2800ff5d, 0xbd10bf18, 0xbf042c00, 0xbd102004, 0x49032044,
+ 0xe8bd71c8, 0xf0004010, 0x0000b8b3, 0x40020000, 0x4df0e92d, 0x4614469a, 0x4605460e, 0xf7ff2310,
+ 0x2800ff2d, 0xe8bdbf18, 0xe9d58df0, 0xfbb00101, 0x4270f8f1, 0x0100f1c8, 0x42474008, 0xbf0842b7,
+ 0x2c004447, 0xf8dfbf18, 0xd01cb044, 0x42a51bbd, 0x4625bf88, 0x490e0928, 0x68094479, 0x2101600e,
+ 0x1007f88b, 0xf88b0a01, 0xf88b100b, 0xf88b000a, 0xf000a009, 0x2800f87d, 0xe8bdbf18, 0x1b648df0,
+ 0x4447442e, 0x2000d1e2, 0x8df0e8bd, 0x40020000, 0x0000014c, 0xbf122800, 0x20042a00, 0x29084770,
+ 0xe8dfd215, 0x0604f001, 0x0c0a0806, 0x68c0100e, 0x6840e00a, 0x6880e008, 0x6800e006, 0x2001e004,
+ 0x6900e002, 0x6940e000, 0x20006010, 0x206a4770, 0x00004770, 0xbf042b00, 0x47702004, 0x4df0e92d,
+ 0xe9dd461c, 0x46158709, 0x2304460e, 0xa020f8dd, 0xfec4f7ff, 0xbf182800, 0x8df0e8bd, 0xbf1a2d00,
+ 0xb04cf8df, 0xe8bd44fb, 0xf8db8df0, 0x60060000, 0x21024810, 0xf88071c1, 0xf8dba00b, 0x68201000,
+ 0xf0006088, 0xb150f825, 0x0f00f1b8, 0xf8c8bf18, 0x2f006000, 0x2100bf1c, 0xe8bd6039, 0x1f2d8df0,
+ 0x0404f104, 0x0604f106, 0xe8bdd1df, 0x00008df0, 0x000000a0, 0x40020000, 0xbf042800, 0x47702004,
+ 0x48022240, 0x718171c2, 0xb802f000, 0x40020000, 0x2170480c, 0x21807001, 0x78017001, 0x0f80f011,
+ 0x7800d0fb, 0x0f20f010, 0x2067bf1c, 0xf0104770, 0xbf1c0f10, 0x47702068, 0x0001f010, 0x2069bf18,
+ 0x00004770, 0x40020000, 0x40020004, 0x00000000, 0x00080000, 0x00100000, 0x00200000, 0x00400000,
+ 0x00800000, 0x01000000, 0x02000000, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x00000000, 0x00001000},
+ };
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000049, // UnInit
+ 0x2000004D, // EraseChip
+ 0x20000071, // EraseSector
+ 0x2000009F, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000000 + 0x00000001,
+ 0x20000000 + 0x00000020 + 0x0000046c,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(mk66f18_flash_prog_blob), // prog_blob size
+ mk66f18_flash_prog_blob, // address of prog_blob
+ 0x00000200 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/k66f/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/k66f/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the k66f
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x00000000,
+ .flash_regions[0].end = 0x00200000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x1fff0000,
+ .ram_regions[0].end = 0x20030000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/k82f/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/k82f/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,95 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t mk82f25615_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0xb510483e, 0x5120f24c, 0xf64d81c1, 0x81c11128, 0xf0218801, 0x80010101, 0x78414839, 0x0160f001,
+ 0xbf0c2940, 0x21002101, 0x444a4a36, 0xb1397011, 0xf0217841, 0x70410160, 0xf0117841, 0xd1fb0f60,
+ 0x44484831, 0xf864f000, 0xbf182800, 0xbd102001, 0x4448482c, 0xb1587800, 0x78414829, 0x0160f021,
+ 0x0140f041, 0x78417041, 0x0160f001, 0xd1fa2940, 0x47702000, 0xb5104824, 0x44484924, 0xf897f000,
+ 0xbf182800, 0x2100bd10, 0xe8bd481f, 0x44484010, 0xb95df000, 0x4c1cb570, 0x444c4605, 0x4b1b4601,
+ 0x68e24620, 0xf8bbf000, 0xbf182800, 0x2300bd70, 0x68e24629, 0x4070e8bd, 0x44484813, 0xb951f000,
+ 0x460cb570, 0x4606460b, 0x480f4601, 0x4615b084, 0xf0004448, 0x2800f8f0, 0xb004bf1c, 0x2000bd70,
+ 0xe9cd2101, 0x90021000, 0x462b4807, 0x46314622, 0xf0004448, 0xb004f984, 0x0000bd70, 0x40052000,
+ 0x4007e000, 0x00000004, 0x00000008, 0x6b65666b, 0xbf042800, 0x47702004, 0x6cc949ec, 0x6103f3c1,
+ 0xbf08290f, 0x2180f44f, 0x4ae9bf1f, 0xf832447a, 0x02891011, 0xe9c02200, 0x21012100, 0x03096081,
+ 0x49e460c1, 0x3f28f811, 0x7c80f44f, 0xf303fa0c, 0x78c96143, 0x62026102, 0x61816242, 0x47704610,
+ 0xbf0e2800, 0x61012004, 0x47702000, 0x48da4602, 0x49d96840, 0x0070f440, 0x47706048, 0x217048d5,
+ 0x21807001, 0x78017001, 0x0f80f011, 0x7800d0fb, 0x0f20f010, 0x2067bf1c, 0xf0104770, 0xbf1c0f10,
+ 0x47702068, 0x0001f010, 0x2069bf18, 0x28004770, 0x2004bf04, 0xb5104770, 0x4ac64604, 0x403bf06f,
+ 0x48c66050, 0xbf144281, 0x2000206b, 0xbf182800, 0x4620bd10, 0xffd2f7ff, 0x46204603, 0xffc6f7ff,
+ 0xbd104618, 0xbf042800, 0x47702004, 0x60532300, 0x60d36093, 0x61536113, 0x61d36193, 0x68c16011,
+ 0xe9d06051, 0xfbb11001, 0x6090f0f0, 0x21102004, 0x0103e9c2, 0x1005e9c2, 0x200061d0, 0xe92d4770,
+ 0xb0884df0, 0x46984615, 0x4682460c, 0xf7ff466a, 0x462affd9, 0x46504621, 0xf0009b04, 0x0007f931,
+ 0xb008bf1c, 0x8df0e8bd, 0x4600e9dd, 0x1e451960, 0xf0f6fbb5, 0x5010fb06, 0xfbb5b120, 0x1c40f0f6,
+ 0x1e454370, 0xbf9842ac, 0xb268f8df, 0xf024d81c, 0xf040407f, 0xf8cb6010, 0x48980004, 0xbf144580,
+ 0x2000206b, 0xbf1c2800, 0xe8bdb008, 0x46508df0, 0xff74f7ff, 0xf8da4607, 0x28000010, 0x4780bf18,
+ 0x4434b917, 0xd9e242ac, 0xf7ff4650, 0xb008ff5f, 0xe8bd4638, 0x2a008df0, 0x2004bf04, 0xe92d4770,
+ 0xb08945f0, 0x461e4614, 0x4680460d, 0xf7ff466a, 0x4632ff89, 0x46404629, 0xf0009b03, 0x0007f8e1,
+ 0xb009bf1c, 0x85f0e8bd, 0x2e009d00, 0xf8dfbf18, 0xd025a1e4, 0x0b04f854, 0x0008f8ca, 0x28049803,
+ 0xf025bf04, 0xf040407f, 0xd00960c0, 0xd1092808, 0x0b04f854, 0x000cf8ca, 0x407ff025, 0x60e0f040,
+ 0x0004f8ca, 0xf7ff4640, 0xf8d8ff29, 0x46071010, 0xbf182900, 0xb91f4788, 0x44059803, 0xd1d91a36,
+ 0xf7ff4640, 0xb009ff13, 0xe8bd4638, 0x280085f0, 0x2004bf04, 0x4a624770, 0x4101ea42, 0x60514a5d,
+ 0xe92de70c, 0xb0884dff, 0x469a4614, 0x466a460d, 0xf7ff9808, 0x4622ff37, 0x9b054629, 0xf0009808,
+ 0x2800f88f, 0xb00cbf1c, 0x8df0e8bd, 0x4629466a, 0xf7ff9808, 0x9e00ff27, 0x8008f8dd, 0xf1c84270,
+ 0x40080100, 0x42b74247, 0x4447bf08, 0xbf182c00, 0xb120f8df, 0x1bbdd01f, 0xbf8842a5, 0x98054625,
+ 0x417ff026, 0xf0f0fbb5, 0x7180f041, 0x1004f8cb, 0xea400400, 0xf040200a, 0xf8cb00ff, 0x98080008,
+ 0xfeccf7ff, 0xbf1c2800, 0xe8bdb00c, 0x1b648df0, 0x4447442e, 0xb00cd1df, 0xe8bd2000, 0x2b008df0,
+ 0x2004bf04, 0xe92d4770, 0xb0884dff, 0xe9dd4616, 0x461d7a14, 0x466a460c, 0x8058f8dd, 0xf7ff9808,
+ 0xe9ddfee1, 0x46323007, 0xf0004621, 0x2800f839, 0xb00cbf1c, 0x8df0e8bd, 0x2e009c00, 0xb00cbf04,
+ 0x8df0e8bd, 0xb08cf8df, 0x407ff06f, 0x6707ea40, 0x407ff024, 0x7000f040, 0x0004f8cb, 0x7008f8cb,
+ 0xf8cb6828, 0x9808000c, 0xfe88f7ff, 0xf1bab168, 0xbf180f00, 0x4000f8ca, 0x0f00f1b8, 0x2100bf1c,
+ 0x1000f8c8, 0xe8bdb00c, 0x99078df0, 0xf0211a76, 0x440d0103, 0x440c9907, 0xb00cd1da, 0x8df0e8bd,
+ 0xbf042800, 0x47702004, 0x42191e5b, 0x421abf0e, 0x47702065, 0x428b6803, 0x6840d806, 0x44184411,
+ 0xbf244288, 0x47702000, 0x47702066, 0x40048000, 0x000003bc, 0x40020000, 0x4001f000, 0x6b65666b,
+ 0x4000ffff, 0x40020004, 0x40020010, 0x00100008, 0x00200018, 0x00400030, 0x00800060, 0x010000c0,
+ 0x02000180, 0x04000300, 0x00000600, 0x00000000, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 4096},
+ };
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000071, // UnInit
+ 0x20000095, // EraseChip
+ 0x200000B5, // EraseSector
+ 0x200000E1, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000000 + 0x00000001,
+ 0x20000000 + 0x00000020 + 0x0000050c,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(mk82f25615_flash_prog_blob), // prog_blob size
+ mk82f25615_flash_prog_blob, // address of prog_blob
+ 0x00000200 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/k82f/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/k82f/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the k66f
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(256),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x1FFF0000,
+ .ram_regions[0].end = 0x20030000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/ke15z/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/ke15z/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,102 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the ke15z
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t mke15z7_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x483cb510, 0x6041493a, 0x6081493b, 0x22806801, 0x22204391, 0x60014311, 0x68c14838, 0x0f890649,
+ 0xd0152902, 0x4a362100, 0x444a2900, 0xd0077011, 0x226068c1, 0x60c14391, 0x064968c1, 0xd1fb0f89,
+ 0x44484830, 0xf862f000, 0xd0002800, 0xbd102001, 0xe7e82101, 0x4448482a, 0x28007800, 0x4827d00a,
+ 0x226068c1, 0x31404391, 0x68c160c1, 0x0f890649, 0xd1fa2902, 0x47702000, 0xb5104822, 0x44484922,
+ 0xf892f000, 0xd1042800, 0x2100481e, 0xf0004448, 0xbd10f94c, 0x4c1bb570, 0x444c4605, 0x4b1a4601,
+ 0x68e24620, 0xf8b9f000, 0xd1052800, 0x46292300, 0x68e24620, 0xf943f000, 0xb570bd70, 0x460b460c,
+ 0x46014606, 0xb084480f, 0x44484615, 0xf8e8f000, 0xd10a2800, 0x90029001, 0x480a2101, 0x462b9100,
+ 0x46314622, 0xf0004448, 0xb004f971, 0x0000bd70, 0xd928c520, 0x40052000, 0x0000ffff, 0x4007e000,
+ 0x00000004, 0x00000008, 0x6b65666b, 0xd00b2800, 0x68c949dd, 0x0f090109, 0xd007290f, 0x00494adb,
+ 0x5a51447a, 0xe0030289, 0x47702004, 0x04892101, 0x2300b430, 0x60416003, 0x02cc2101, 0x608160c4,
+ 0x7a0d49d3, 0x40aa158a, 0x7ac96142, 0x61816103, 0x06892105, 0x62016244, 0x2000bc30, 0x28004770,
+ 0x6101d002, 0x47702000, 0x47702004, 0x48c94602, 0x210168c0, 0x43080289, 0x60c849c6, 0x48c64770,
+ 0x70012170, 0x70012180, 0x06097801, 0x7800d5fc, 0xd5010681, 0x47702067, 0xd50106c1, 0x47702068,
+ 0xd0fc07c0, 0x47702069, 0xd1012800, 0x47702004, 0x4604b510, 0x48b94ab8, 0x48b96050, 0xd0014281,
+ 0xe000206b, 0x28002000, 0x4620d107, 0xffd7f7ff, 0x46204603, 0xffcaf7ff, 0xbd104618, 0xd1012800,
+ 0x47702004, 0x4614b510, 0x60622200, 0x60e260a2, 0x61626122, 0x61e261a2, 0x68c16021, 0x68816061,
+ 0xf0006840, 0x60a0f953, 0x60e02008, 0x61606120, 0x200461a0, 0x200061e0, 0xb5ffbd10, 0x4615b089,
+ 0x466a460c, 0xf7ff9809, 0x462affd9, 0x9b044621, 0xf0009809, 0x0007f90c, 0x9c00d130, 0x19659e01,
+ 0x46311e6d, 0xf0004628, 0x2900f931, 0x1c40d002, 0x1e454370, 0xd81d42ac, 0x20090221, 0x06000a09,
+ 0x488d1809, 0x498e6041, 0x4288980c, 0x206bd001, 0x2000e000, 0xd1112800, 0xf7ff9809, 0x4607ff80,
+ 0x69009809, 0xd0002800, 0x2f004780, 0x19a4d102, 0xd9e142ac, 0xf7ff9809, 0x4638ff69, 0xbdf0b00d,
+ 0xd1012a00, 0x47702004, 0xb089b5ff, 0x461e4614, 0x466a460d, 0xf7ff9809, 0x4632ff91, 0x9b034629,
+ 0xf0009809, 0x0007f8c4, 0x9d00d12d, 0xd0262e00, 0x4871cc02, 0x99036081, 0xd0022904, 0xd0072908,
+ 0x022ae00e, 0x0a122103, 0x18510649, 0xe0076041, 0x60c1cc02, 0x2107022a, 0x06090a12, 0x60411851,
+ 0xf7ff9809, 0x4607ff3c, 0x69009809, 0xd0002800, 0x2f004780, 0x9803d103, 0x1a361945, 0x9809d1d8,
+ 0xff24f7ff, 0xb00d4638, 0x2800bdf0, 0x4a5dd005, 0x18890409, 0x60514a58, 0x2004e721, 0xb5ff4770,
+ 0x4614b08b, 0x460d461e, 0x980b466a, 0xff46f7ff, 0x46294622, 0x980b9b05, 0xf879f000, 0xd1332800,
+ 0x4629466a, 0xf7ff980b, 0x9d00ff39, 0x90089802, 0x42404269, 0x424f4001, 0xd10142af, 0x183f9808,
+ 0xd0202c00, 0x90090230, 0x42a61b7e, 0x4626d900, 0x99054630, 0xf88af000, 0x2101022a, 0x06090a12,
+ 0x493d1852, 0x9a09604a, 0x43100400, 0x608830ff, 0xf7ff980b, 0x2800fee4, 0x9808d106, 0x19ad1ba4,
+ 0x2c00183f, 0x2000d1e0, 0xbdf0b00f, 0xd1012b00, 0x47702004, 0xb089b5ff, 0x461d4616, 0x466a460c,
+ 0x98099f12, 0xfefaf7ff, 0x46214632, 0x98099b07, 0xf82df000, 0xd11d2800, 0x2e009c00, 0x492ad01a,
+ 0x18470638, 0x20010221, 0x06400a09, 0x48221809, 0x60876041, 0x60c16829, 0xf7ff9809, 0x2800feb0,
+ 0x9913d00a, 0xd0002900, 0x9914600c, 0xd0012900, 0x600a2200, 0xbdf0b00d, 0x1a769907, 0x00890889,
+ 0x9907194d, 0x2e00190c, 0xb00dd1dc, 0x2800bdf0, 0x2004d101, 0xb4104770, 0x460c1e5b, 0xd101421c,
+ 0xd002421a, 0x2065bc10, 0x68034770, 0xd804428b, 0x18896840, 0x42881818, 0xbc10d202, 0x47702066,
+ 0x2000bc10, 0x00004770, 0x40048040, 0x000003bc, 0x40020020, 0xf0003000, 0x40020000, 0x44ffffff,
+ 0x6b65666b, 0x4000ffff, 0x00ffffff, 0x460bb530, 0x20004601, 0x24012220, 0x460de009, 0x429d40d5,
+ 0x461dd305, 0x1b494095, 0x40954625, 0x46151940, 0x2d001e52, 0xbd30dcf1, 0x40020004, 0x40020010,
+ 0x00100008, 0x00200018, 0x00400030, 0x00800060, 0x010000c0, 0x02000180, 0x04000300, 0x00000600,
+ 0x00000000, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 2048},
+ };
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000075, // UnInit
+ 0x20000099, // EraseChip
+ 0x200000B5, // EraseSector
+ 0x200000DB, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000000 + 0x00000001,
+ 0x20000000 + 0x00000020 + 0x00000500,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(mke15z7_flash_prog_blob), // prog_blob size
+ mke15z7_flash_prog_blob, // address of prog_blob
+ 0x00000200 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/ke15z/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/ke15z/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the ke15z
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(256),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x1FFFE000,
+ .ram_regions[0].end = 0x20006000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/ke18f/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/ke18f/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,102 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the ke18f
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t mke18f16_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0xb510483f, 0x6041493d, 0x71fff64f, 0x68016081, 0x0180f021, 0x0120f041, 0x483a6001, 0xf00168c1,
+ 0x29400160, 0x2101bf0c, 0x4a372100, 0x7011444a, 0x68c1b139, 0x0160f021, 0x68c160c1, 0x0f60f011,
+ 0x4832d1fb, 0xf0004448, 0x2800f865, 0x2001bf18, 0x482dbd10, 0x78004448, 0x482ab158, 0xf02168c1,
+ 0xf0410160, 0x60c10140, 0xf00168c1, 0x29400160, 0x2000d1fa, 0x48254770, 0x4925b510, 0xf0004448,
+ 0x2800f8a1, 0xbd10bf18, 0x48202100, 0x4010e8bd, 0xf0004448, 0xb570b966, 0x46054c1c, 0x4601444c,
+ 0x46204b1b, 0xf00068e2, 0x2800f8c6, 0xbd70bf18, 0x46292300, 0xe8bd68e2, 0x48144070, 0xf0004448,
+ 0xb570b95a, 0x460b460c, 0x46014606, 0xb084480f, 0x44484615, 0xf8f9f000, 0xbf1c2800, 0xbd70b004,
+ 0x21012000, 0x1000e9cd, 0x48089002, 0x4622462b, 0x44484631, 0xf98df000, 0xbd70b004, 0xd928c520,
+ 0x40052000, 0x4007e000, 0x00000004, 0x00000008, 0x6b65666b, 0xbf042800, 0x47702004, 0x6cc949f0,
+ 0x6103f3c1, 0xbf08290f, 0x2100f44f, 0x4aedbf1f, 0xf832447a, 0x02891011, 0x2200b410, 0x2100e9c0,
+ 0x60812101, 0x03094be8, 0xf89360c1, 0x110cc000, 0xfc0cfa04, 0xc014f8c0, 0x618378db, 0xf04f6102,
+ 0xe9c052a0, 0xbc102108, 0x47702000, 0xbf0e2800, 0x61012004, 0x47702000, 0x48dc4602, 0x49db6800,
+ 0x0020f040, 0x46086008, 0xf0406800, 0x60080010, 0x48d74770, 0x70012170, 0x70012180, 0xf0117801,
+ 0xd0fb0f80, 0xf0107800, 0xbf1c0f20, 0x47702067, 0x0f10f010, 0x2068bf1c, 0xf0104770, 0xbf180001,
+ 0x47702069, 0xbf042800, 0x47702004, 0x4604b510, 0xf06f4ac7, 0x6050403b, 0x428148c6, 0x206bbf14,
+ 0x28002000, 0xbd10bf18, 0xf7ff4620, 0x4603ffd2, 0xf7ff4620, 0x4618ffc1, 0x2800bd10, 0x2004bf04,
+ 0x23004770, 0x60936053, 0x611360d3, 0x61936153, 0x601161d3, 0x605168c1, 0x1001e9d0, 0xf0f0fbb1,
+ 0x20086090, 0xe9c22110, 0xe9c20103, 0x20041005, 0x200061d0, 0xe92d4770, 0xb0884df0, 0x46984615,
+ 0x4682460c, 0xf7ff466a, 0x462affd8, 0x46504621, 0xf0009b04, 0x0007f92f, 0xb008bf1c, 0x8df0e8bd,
+ 0x4600e9dd, 0x1e451960, 0xf0f6fbb5, 0x5110fb06, 0x1c40b111, 0x1e454370, 0xbf9842ac, 0xb270f8df,
+ 0xf024d81c, 0xf040407f, 0xf8cb6010, 0x48990004, 0xbf144580, 0x2000206b, 0xbf1c2800, 0xe8bdb008,
+ 0x46508df0, 0xff75f7ff, 0xf8da4607, 0x28000010, 0x4780bf18, 0x4434b917, 0xd9e242ac, 0xf7ff4650,
+ 0xb008ff5b, 0xe8bd4638, 0x2a008df0, 0x2004bf04, 0xe92d4770, 0xb08945f0, 0x461e4614, 0x4680460d,
+ 0xf7ff466a, 0x4632ff8a, 0x46404629, 0xf0009b03, 0x0007f8e1, 0xb009bf1c, 0x85f0e8bd, 0x2e009d00,
+ 0xf8dfbf18, 0xd025a1ec, 0x0b04f854, 0x0008f8ca, 0x28049803, 0xf025bf04, 0xf040407f, 0xd00960c0,
+ 0xd1092808, 0x0b04f854, 0x000cf8ca, 0x407ff025, 0x60e0f040, 0x0004f8ca, 0xf7ff4640, 0xf8d8ff2a,
+ 0x46071010, 0xbf182900, 0xb91f4788, 0x44059803, 0xd1d91a36, 0xf7ff4640, 0xb009ff0f, 0xe8bd4638,
+ 0x280085f0, 0x2004bf04, 0x4a634770, 0x4101ea42, 0x60514a5f, 0xe92de70d, 0xb0884dff, 0x469a4614,
+ 0x466a460d, 0xf7ff9808, 0x4622ff38, 0x9b054629, 0xf0009808, 0x2800f88f, 0xb00cbf1c, 0x8df0e8bd,
+ 0x4629466a, 0xf7ff9808, 0x9e00ff28, 0x8008f8dd, 0xf1c84270, 0x40080100, 0x42b74247, 0x4447bf08,
+ 0xbf182c00, 0xb128f8df, 0x1bbdd01f, 0xbf8842a5, 0x98054625, 0x417ff026, 0xf0f0fbb5, 0x7180f041,
+ 0x1004f8cb, 0xea400400, 0xf040200a, 0xf8cb00ff, 0x98080008, 0xfecdf7ff, 0xbf1c2800, 0xe8bdb00c,
+ 0x1b648df0, 0x4447442e, 0xb00cd1df, 0xe8bd2000, 0x2b008df0, 0x2004bf04, 0xe92d4770, 0xb0884dff,
+ 0xe9dd4616, 0x461d7a14, 0x466a460c, 0x8058f8dd, 0xf7ff9808, 0xe9ddfee2, 0x46323007, 0xf0004621,
+ 0x2800f839, 0xb00cbf1c, 0x8df0e8bd, 0x2e009c00, 0xb00cbf04, 0x8df0e8bd, 0xb094f8df, 0x407ff06f,
+ 0x6707ea40, 0x407ff024, 0x7000f040, 0x0004f8cb, 0x7008f8cb, 0xf8cb6828, 0x9808000c, 0xfe89f7ff,
+ 0xf1bab168, 0xbf180f00, 0x4000f8ca, 0x0f00f1b8, 0x2100bf1c, 0x1000f8c8, 0xe8bdb00c, 0x99078df0,
+ 0xf0211a76, 0x440d0103, 0x440c9907, 0xb00cd1da, 0x8df0e8bd, 0xbf042800, 0x47702004, 0x42191e5b,
+ 0x421abf0e, 0x47702065, 0x428b6803, 0x6840d806, 0x44184411, 0xbf244288, 0x47702000, 0x47702066,
+ 0x40048000, 0x000003d0, 0x40020028, 0x40001400, 0x40020000, 0x6b65666b, 0x4000ffff, 0x40020004,
+ 0x40020010, 0x00100008, 0x00200018, 0x00400030, 0x00800060, 0x010000c0, 0x02000180, 0x04000300,
+ 0x00000600, 0x00000000, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 4096},
+ };
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000073, // UnInit
+ 0x20000097, // EraseChip
+ 0x200000B7, // EraseSector
+ 0x200000E3, // ProgramPage
+ 0x0, // Verify
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000000 + 0x00000001,
+ 0x20000000 + 0x00000020 + 0x00000524,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(mke18f16_flash_prog_blob), // prog_blob size
+ mke18f16_flash_prog_blob, // address of prog_blob
+ 0x00000200 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/ke18f/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/ke18f/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the ke18f
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(512),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x1FFF8000,
+ .ram_regions[0].end = 0x20008000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/kl02z/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/kl02z/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,98 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the kl02z
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t KL02Z_FLM[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x492bb510, 0x60082000, 0x4448482a, 0xf88af000, 0xd0002800, 0xbd102001, 0x47702000, 0xb5104825,
+ 0xf0004448, 0x0004f871, 0x4822d105, 0x44482100, 0xf908f000, 0xf0004604, 0x4620f834, 0xb570bd10,
+ 0x46014605, 0x2201481b, 0xf0004448, 0x0004f837, 0x4818d107, 0x22012300, 0x44484629, 0xf8baf000,
+ 0xf0004604, 0x4620f81e, 0xb5febd70, 0x460b460d, 0x46014607, 0x4616480f, 0xf0004448, 0x0004f887,
+ 0x9001d10b, 0x21019002, 0x9100480a, 0x462a4633, 0x44484639, 0xf8e4f000, 0xf0004604, 0x4620f802,
+ 0x4805bdfe, 0x220168c1, 0x43110292, 0x477060c1, 0x40048100, 0x00000004, 0xf0003000, 0x4614b5f8,
+ 0xf000460d, 0x2800f848, 0x192cd118, 0x05a11e64, 0x0aa1d003, 0x028c1c49, 0x4e091e64, 0x2709447e,
+ 0xd80b42a5, 0x60056830, 0x71c74806, 0xf8e8f000, 0xd1032800, 0x02892101, 0xe7f1186d, 0x0000bdf8,
+ 0x0000038c, 0x40020000, 0x2800b510, 0x4904d005, 0x71c82044, 0xf8d4f000, 0x2004bd10, 0x0000bd10,
+ 0x40020000, 0xd0122800, 0x68c94916, 0x01094a16, 0x00490f09, 0x5a51447a, 0xd00a0309, 0x60022200,
+ 0x21016041, 0x02896081, 0x461060c1, 0x20044770, 0x20644770, 0x28004770, 0x460bd005, 0x079b4313,
+ 0x2065d003, 0x20044770, 0x68034770, 0xd804428b, 0x18896840, 0x42881818, 0x2066d201, 0x20004770,
+ 0x00004770, 0x40048040, 0x00000312, 0x461db5f8, 0x460e0014, 0x461ad017, 0xffddf7ff, 0xd1132800,
+ 0x447f4f0a, 0xd00f2d00, 0x60066838, 0x6839cc01, 0x49076048, 0x71c82006, 0xf882f000, 0xd1032800,
+ 0x1f2d1d36, 0x2004e7ee, 0x0000bdf8, 0x000002c6, 0x40020000, 0xb081b5ff, 0x460e4614, 0xf7ff4605,
+ 0x2800ffba, 0x68a9d127, 0xf0006868, 0x9000f881, 0x42404271, 0x424d4001, 0xd10142b5, 0x182d9800,
+ 0xd0172c00, 0x42a71baf, 0x4627d900, 0x08b9480b, 0x68004478, 0x480a6006, 0x71c22201, 0x72c20a0a,
+ 0x99047281, 0xf0007241, 0x2800f84b, 0x1be4d103, 0xe7e319f6, 0xb0052000, 0x0000bdf0, 0x00000258,
+ 0x40020000, 0x2800b510, 0x4804d006, 0x71c22240, 0xf0007181, 0xbd10f835, 0xbd102004, 0x40020000,
+ 0x9f08b5f8, 0x4616001c, 0xd004460d, 0xff73f7ff, 0xd1012800, 0x2004e01d, 0x480fbdf8, 0x68014478,
+ 0x490e600d, 0x71ca2202, 0x72ca9a06, 0x68216800, 0xf0006081, 0x2800f815, 0x9907d008, 0xd0002900,
+ 0x2f00600d, 0x2100d0e8, 0xbdf86039, 0x1d241f36, 0x2e001d2d, 0xbdf8d1e1, 0x000001ec, 0x40020000,
+ 0x2170480a, 0x21807001, 0x78017001, 0xd0fc09c9, 0x06817800, 0x2067d501, 0x06c14770, 0x2068d501,
+ 0x07c04770, 0x2069d0fc, 0x00004770, 0x40020000, 0x09032200, 0xd32c428b, 0x428b0a03, 0x2300d311,
+ 0xe04e469c, 0x430b4603, 0x2200d43c, 0x428b0843, 0x0903d331, 0xd31c428b, 0x428b0a03, 0x4694d301,
+ 0x09c3e03f, 0xd301428b, 0x1ac001cb, 0x09834152, 0xd301428b, 0x1ac0018b, 0x09434152, 0xd301428b,
+ 0x1ac0014b, 0x09034152, 0xd301428b, 0x1ac0010b, 0x08c34152, 0xd301428b, 0x1ac000cb, 0x08834152,
+ 0xd301428b, 0x1ac0008b, 0x08434152, 0xd301428b, 0x1ac0004b, 0x1a414152, 0x4601d200, 0x46104152,
+ 0xe05d4770, 0xd0000fca, 0x10034249, 0x4240d300, 0x22004053, 0x0903469c, 0xd32d428b, 0x428b0a03,
+ 0x22fcd312, 0xba120189, 0x428b0a03, 0x0189d30c, 0x428b1192, 0x0189d308, 0x428b1192, 0x0189d304,
+ 0x1192d03a, 0x0989e000, 0x428b09c3, 0x01cbd301, 0x41521ac0, 0x428b0983, 0x018bd301, 0x41521ac0,
+ 0x428b0943, 0x014bd301, 0x41521ac0, 0x428b0903, 0x010bd301, 0x41521ac0, 0x428b08c3, 0x00cbd301,
+ 0x41521ac0, 0x428b0883, 0x008bd301, 0x41521ac0, 0x0843d2d9, 0xd301428b, 0x1ac0004b, 0x1a414152,
+ 0x4601d200, 0x41524663, 0x4610105b, 0x4240d301, 0xd5002b00, 0x47704249, 0x105b4663, 0x4240d300,
+ 0x2000b501, 0x46c046c0, 0x0002bd02, 0x00000004, 0x00000008, 0x00000010, 0x00000020, 0x00000040,
+ 0x00000000, 0x00000000, 0x00000020, 0x40020004, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 1024},
+ };
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000039, // UnInit
+ 0x2000003D, // EraseChip
+ 0x2000005F, // EraseSector
+ 0x2000008B, // ProgramPage
+ 0x0, // Verify
+
+ // breakpoint = RAM start + 1
+ // RSB : base address is address of Execution Region PrgData in map file
+ // to access global/static data
+ // RSP : Initial stack pointer
+ {
+ 0x20000001, // breakpoint instruction address
+ 0x20000000 + 0x20 + 0x470, // static base register value (image start + header + static base offset)
+ 0x20000800 // initial stack pointer
+ },
+
+ 0x20000a00, // program_buffer, any valid RAM location with +512 bytes of headroom
+ 0x20000000, // algo_start, start of RAM
+ sizeof(KL02Z_FLM), // algo_size, size of array above
+ KL02Z_FLM, // image, flash algo instruction array
+ 512 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/kl02z/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/kl02z/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the kl02z
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(32),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x1FFFFC00,
+ .ram_regions[0].end = 0x20000C00,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/kl05z/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/kl05z/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,97 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the kl05
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t KL05Z_FLM[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x492bb510, 0x60082000, 0x4448482a, 0xf88af000, 0xd0002800, 0xbd102001, 0x47702000, 0xb5104825,
+ 0xf0004448, 0x0004f871, 0x4822d105, 0x44482100, 0xf908f000, 0xf0004604, 0x4620f834, 0xb570bd10,
+ 0x46014605, 0x2201481b, 0xf0004448, 0x0004f837, 0x4818d107, 0x22012300, 0x44484629, 0xf8baf000,
+ 0xf0004604, 0x4620f81e, 0xb5febd70, 0x460b460d, 0x46014607, 0x4616480f, 0xf0004448, 0x0004f887,
+ 0x9001d10b, 0x21019002, 0x9100480a, 0x462a4633, 0x44484639, 0xf8e4f000, 0xf0004604, 0x4620f802,
+ 0x4805bdfe, 0x220168c1, 0x43110292, 0x477060c1, 0x40048100, 0x00000004, 0xf0003000, 0x4614b5f8,
+ 0xf000460d, 0x2800f848, 0x192cd118, 0x05a11e64, 0x0aa1d003, 0x028c1c49, 0x4e091e64, 0x2709447e,
+ 0xd80b42a5, 0x60056830, 0x71c74806, 0xf8e8f000, 0xd1032800, 0x02892101, 0xe7f1186d, 0x0000bdf8,
+ 0x0000038c, 0x40020000, 0x2800b510, 0x4904d005, 0x71c82044, 0xf8d4f000, 0x2004bd10, 0x0000bd10,
+ 0x40020000, 0xd0122800, 0x68c94916, 0x01094a16, 0x00490f09, 0x5a51447a, 0xd00a0309, 0x60022200,
+ 0x21016041, 0x02896081, 0x461060c1, 0x20044770, 0x20644770, 0x28004770, 0x460bd005, 0x079b4313,
+ 0x2065d003, 0x20044770, 0x68034770, 0xd804428b, 0x18896840, 0x42881818, 0x2066d201, 0x20004770,
+ 0x00004770, 0x40048040, 0x00000312, 0x461db5f8, 0x460e0014, 0x461ad017, 0xffddf7ff, 0xd1132800,
+ 0x447f4f0a, 0xd00f2d00, 0x60066838, 0x6839cc01, 0x49076048, 0x71c82006, 0xf882f000, 0xd1032800,
+ 0x1f2d1d36, 0x2004e7ee, 0x0000bdf8, 0x000002c6, 0x40020000, 0xb081b5ff, 0x460e4614, 0xf7ff4605,
+ 0x2800ffba, 0x68a9d127, 0xf0006868, 0x9000f881, 0x42404271, 0x424d4001, 0xd10142b5, 0x182d9800,
+ 0xd0172c00, 0x42a71baf, 0x4627d900, 0x08b9480b, 0x68004478, 0x480a6006, 0x71c22201, 0x72c20a0a,
+ 0x99047281, 0xf0007241, 0x2800f84b, 0x1be4d103, 0xe7e319f6, 0xb0052000, 0x0000bdf0, 0x00000258,
+ 0x40020000, 0x2800b510, 0x4804d006, 0x71c22240, 0xf0007181, 0xbd10f835, 0xbd102004, 0x40020000,
+ 0x9f08b5f8, 0x4616001c, 0xd004460d, 0xff73f7ff, 0xd1012800, 0x2004e01d, 0x480fbdf8, 0x68014478,
+ 0x490e600d, 0x71ca2202, 0x72ca9a06, 0x68216800, 0xf0006081, 0x2800f815, 0x9907d008, 0xd0002900,
+ 0x2f00600d, 0x2100d0e8, 0xbdf86039, 0x1d241f36, 0x2e001d2d, 0xbdf8d1e1, 0x000001ec, 0x40020000,
+ 0x2170480a, 0x21807001, 0x78017001, 0xd0fc09c9, 0x06817800, 0x2067d501, 0x06c14770, 0x2068d501,
+ 0x07c04770, 0x2069d0fc, 0x00004770, 0x40020000, 0x09032200, 0xd32c428b, 0x428b0a03, 0x2300d311,
+ 0xe04e469c, 0x430b4603, 0x2200d43c, 0x428b0843, 0x0903d331, 0xd31c428b, 0x428b0a03, 0x4694d301,
+ 0x09c3e03f, 0xd301428b, 0x1ac001cb, 0x09834152, 0xd301428b, 0x1ac0018b, 0x09434152, 0xd301428b,
+ 0x1ac0014b, 0x09034152, 0xd301428b, 0x1ac0010b, 0x08c34152, 0xd301428b, 0x1ac000cb, 0x08834152,
+ 0xd301428b, 0x1ac0008b, 0x08434152, 0xd301428b, 0x1ac0004b, 0x1a414152, 0x4601d200, 0x46104152,
+ 0xe05d4770, 0xd0000fca, 0x10034249, 0x4240d300, 0x22004053, 0x0903469c, 0xd32d428b, 0x428b0a03,
+ 0x22fcd312, 0xba120189, 0x428b0a03, 0x0189d30c, 0x428b1192, 0x0189d308, 0x428b1192, 0x0189d304,
+ 0x1192d03a, 0x0989e000, 0x428b09c3, 0x01cbd301, 0x41521ac0, 0x428b0983, 0x018bd301, 0x41521ac0,
+ 0x428b0943, 0x014bd301, 0x41521ac0, 0x428b0903, 0x010bd301, 0x41521ac0, 0x428b08c3, 0x00cbd301,
+ 0x41521ac0, 0x428b0883, 0x008bd301, 0x41521ac0, 0x0843d2d9, 0xd301428b, 0x1ac0004b, 0x1a414152,
+ 0x4601d200, 0x41524663, 0x4610105b, 0x4240d301, 0xd5002b00, 0x47704249, 0x105b4663, 0x4240d300,
+ 0x2000b501, 0x46c046c0, 0x0002bd02, 0x00000004, 0x00000008, 0x00000010, 0x00000020, 0x00000040,
+ 0x00000000, 0x00000000, 0x00000020, 0x40020004, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 1024},
+ };
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000039, // UnInit
+ 0x2000003D, // EraseChip
+ 0x2000005F, // EraseSector
+ 0x2000008B, // ProgramPage
+ 0x0, // Verify
+ // breakpoint = RAM start + 1
+ // RSB : base address is address of Execution Region PrgData in map file
+ // to access global/static data
+ // RSP : Initial stack pointer
+ {
+ 0x20000001, // breakpoint instruction address
+ 0x20000000 + 0x20 + 0x470, // static base register value (image start + header + static base offset)
+ 0x20000800 // initial stack pointer
+ },
+
+ 0x20000a00, // program_buffer, any valid RAM location with +512 bytes of headroom
+ 0x20000000, // algo_start, start of RAM
+ sizeof(KL05Z_FLM), // algo_size, size of array above
+ KL05Z_FLM, // image, flash algo instruction array
+ 512 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/kl05z/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/kl05z/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the kl05z
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(32),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x1FFFFC00,
+ .ram_regions[0].end = 0x20000C00,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/kl25z/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/kl25z/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,110 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the kl25z
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t KL25Z_FLM[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x4604b570, 0x4616460d, 0x49302000, 0x48306008, 0xf0004448, 0x2800f8e9, 0x2001d001, 0x2000bd70,
+ 0x4601e7fc, 0x47702000, 0x492ab510, 0x44484828, 0xf8c2f000, 0x2c004604, 0x2100d105, 0x44484824,
+ 0xf9bef000, 0xf0004604, 0x4620f838, 0xb570bd10, 0x481f4604, 0x4b1f4448, 0x68c24621, 0xf862f000,
+ 0x2d004605, 0x481ad107, 0x23004448, 0x68c24621, 0xf956f000, 0xf0004605, 0x4628f820, 0xb5febd70,
+ 0x460c4605, 0x46234616, 0x46294632, 0x44484810, 0xf90af000, 0x2f004607, 0x2201d10b, 0x46339001,
+ 0x90029200, 0x46294622, 0x44484809, 0xf99af000, 0xf0004607, 0x4638f802, 0x4807bdfe, 0x210168c0,
+ 0x43880289, 0x49041840, 0x477060c8, 0x40048100, 0x00000004, 0x6b65666b, 0xf0003000, 0x4a102070,
+ 0x20807010, 0xbf007010, 0x7800480d, 0x280009c0, 0x480bd0fa, 0x20207801, 0x28004008, 0x2067d001,
+ 0x20104770, 0x28004008, 0x2068d001, 0x07c8e7f8, 0x28000fc0, 0x2069d001, 0x2000e7f2, 0x0000e7f0,
+ 0x40020000, 0xb081b5ff, 0x460d4604, 0xf0009804, 0x4606f89f, 0xd0022e00, 0xb0054630, 0x2304bdf0,
+ 0x46204629, 0xf0009a03, 0x4606f876, 0xd0012e00, 0xe7f24630, 0x18289803, 0x46381e47, 0xf00068e1,
+ 0x2900f983, 0x4638d009, 0xf00068e1, 0x1c40f97d, 0x68e19000, 0x43489800, 0xe0131e47, 0x4478480c,
+ 0x60056800, 0x490b2009, 0xf7ff71c8, 0x4606ffa7, 0x280069a0, 0x69a0d001, 0x2e004780, 0xe003d000,
+ 0x194568e0, 0xd9e942bd, 0x4630bf00, 0x0000e7c5, 0x00000462, 0x40020000, 0x4604b570, 0x4628460d,
+ 0xf856f000, 0x2e004606, 0x4630d001, 0x2c00bd70, 0x2004d101, 0x2044e7fa, 0x71c84902, 0xff7ef7ff,
+ 0x0000e7f4, 0x40020000, 0x29004601, 0x2004d101, 0x482a4770, 0x010068c0, 0x00400f00, 0x447b4b28,
+ 0x03025a18, 0xd1012a00, 0xe7f12064, 0x60082000, 0x2001604a, 0x02806088, 0x200060c8, 0x61486108,
+ 0xbf006188, 0x4602e7e4, 0xd1012a00, 0x47702004, 0x20006191, 0xb530e7fb, 0x2c004604, 0x2004d101,
+ 0x1e58bd30, 0x28004008, 0x1e58d103, 0x28004010, 0x2065d001, 0x6820e7f4, 0xd8054288, 0x68206865,
+ 0x188d1940, 0xd20142a8, 0xe7e92066, 0xe7e72000, 0x480c4601, 0xd0014281, 0x4770206b, 0xe7fc2000,
+ 0x2b004603, 0x2004d101, 0x290f4770, 0x2a04d801, 0x2004d001, 0x2000e7f8, 0x0000e7f6, 0x40048040,
+ 0x000003c0, 0x6b65666b, 0xb081b5ff, 0x46144607, 0x2c00461d, 0x2004d102, 0xbdf0b005, 0x462a2304,
+ 0x99024638, 0xffb7f7ff, 0x2e004606, 0x4630d001, 0xe01ce7f2, 0x44794910, 0x68099802, 0xcc016008,
+ 0x4479490d, 0x6809390c, 0x20066048, 0x71c8490b, 0xfef4f7ff, 0x69b84606, 0xd0012800, 0x478069b8,
+ 0xd0002e00, 0x9802e005, 0x90021d00, 0x2d001f2d, 0xbf00d1e0, 0xe7cf4630, 0x0000030a, 0x40020000,
+ 0xb083b5ff, 0x2304460c, 0x9a054621, 0xf7ff9803, 0x9002ff82, 0x28009802, 0x9802d002, 0xbdf0b007,
+ 0x68919a03, 0xf0006850, 0x4605f88f, 0x42684261, 0x424e4001, 0xd10042a6, 0x9f051976, 0x1b30e027,
+ 0x98019001, 0xd90042b8, 0x98019701, 0x90000880, 0x44784811, 0x60046800, 0x49102001, 0x980071c8,
+ 0x0e010400, 0x72c1480d, 0x9800490c, 0x98067288, 0xf7ff7248, 0x9002fea3, 0x28009802, 0x9802d001,
+ 0x9801e7cc, 0x98011a3f, 0x19761824, 0x2f00bf00, 0x2000d1d5, 0x0000e7c2, 0x0000026e, 0x40020000,
+ 0x4604b570, 0x2c00460d, 0x2004d101, 0x2040bd70, 0x71c84903, 0x71854608, 0xfe80f7ff, 0x0000e7f6,
+ 0x40020000, 0xb081b5ff, 0x4617460c, 0x2d00461d, 0x2004d102, 0xbdf0b005, 0x463a2304, 0x98014621,
+ 0xff19f7ff, 0x2e004606, 0x4630d001, 0xe022e7f2, 0x44784813, 0x60046800, 0x49122002, 0x980a71c8,
+ 0x490f72c8, 0x39124479, 0x68096828, 0xf7ff6088, 0x4606fe55, 0xd00b2e00, 0x2800980b, 0x980bd001,
+ 0x980c6004, 0xd0022800, 0x980c2100, 0xe0046001, 0x1d2d1f3f, 0x2f001d24, 0xbf00d1da, 0xe7c94630,
+ 0x000001ce, 0x40020000, 0x09032200, 0xd32c428b, 0x428b0a03, 0x2300d311, 0xe04e469c, 0x430b4603,
+ 0x2200d43c, 0x428b0843, 0x0903d331, 0xd31c428b, 0x428b0a03, 0x4694d301, 0x09c3e03f, 0xd301428b,
+ 0x1ac001cb, 0x09834152, 0xd301428b, 0x1ac0018b, 0x09434152, 0xd301428b, 0x1ac0014b, 0x09034152,
+ 0xd301428b, 0x1ac0010b, 0x08c34152, 0xd301428b, 0x1ac000cb, 0x08834152, 0xd301428b, 0x1ac0008b,
+ 0x08434152, 0xd301428b, 0x1ac0004b, 0x1a414152, 0x4601d200, 0x46104152, 0xe05d4770, 0xd0000fca,
+ 0x10034249, 0x4240d300, 0x22004053, 0x0903469c, 0xd32d428b, 0x428b0a03, 0x22fcd312, 0xba120189,
+ 0x428b0a03, 0x0189d30c, 0x428b1192, 0x0189d308, 0x428b1192, 0x0189d304, 0x1192d03a, 0x0989e000,
+ 0x428b09c3, 0x01cbd301, 0x41521ac0, 0x428b0983, 0x018bd301, 0x41521ac0, 0x428b0943, 0x014bd301,
+ 0x41521ac0, 0x428b0903, 0x010bd301, 0x41521ac0, 0x428b08c3, 0x00cbd301, 0x41521ac0, 0x428b0883,
+ 0x008bd301, 0x41521ac0, 0x0843d2d9, 0xd301428b, 0x1ac0004b, 0x1a414152, 0x4601d200, 0x41524663,
+ 0x4610105b, 0x4240d301, 0xd5002b00, 0x47704249, 0x105b4663, 0x4240d300, 0x2000b501, 0x46c046c0,
+ 0x0002bd02, 0x00000004, 0x00000008, 0x00000010, 0x00000020, 0x00000040, 0x00000000, 0x00000000,
+ 0x00000020, 0x40020004, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 1024},
+ };
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000039, // UnInit
+ 0x20000049, // EraseChip
+ 0x2000006F, // EraseSector
+ 0x2000009F, // ProgramPage
+ 0x0, // Verify
+
+ // breakpoint = RAM start + 1
+ // RSB : base address is address of Execution Region PrgData in map file
+ // to access global/static data
+ // RSP : Initial stack pointer
+ {
+ 0x20000001, // breakpoint instruction address
+ 0x20000000 + 0x20 + 0x5E8, // static base register value (image start + header + static base offset)
+ 0x20000800 // initial stack pointer
+ },
+
+ 0x20000a00, // program_buffer, any valid RAM location with +512 bytes of headroom
+ 0x20000000, // algo_start, start of RAM
+ sizeof(KL25Z_FLM), // algo_size, size of array above
+ KL25Z_FLM, // image, flash algo instruction array
+ 512 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/kl25z/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/kl25z/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the kl25z
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(128),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x1FFF0000,
+ .ram_regions[0].end = 0x20004000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/kl26z/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/kl26z/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,98 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the kl26z
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t KL26Z_FLM[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x492bb510, 0x60082000, 0x4448482a, 0xf88af000, 0xd0002800, 0xbd102001, 0x47702000, 0xb5104825,
+ 0xf0004448, 0x0004f871, 0x4822d105, 0x44482100, 0xf908f000, 0xf0004604, 0x4620f834, 0xb570bd10,
+ 0x46014605, 0x2201481b, 0xf0004448, 0x0004f837, 0x4818d107, 0x22012300, 0x44484629, 0xf8baf000,
+ 0xf0004604, 0x4620f81e, 0xb5febd70, 0x460b460d, 0x46014607, 0x4616480f, 0xf0004448, 0x0004f887,
+ 0x9001d10b, 0x21019002, 0x9100480a, 0x462a4633, 0x44484639, 0xf8e4f000, 0xf0004604, 0x4620f802,
+ 0x4805bdfe, 0x220168c1, 0x43110292, 0x477060c1, 0x40048100, 0x00000004, 0xf0003000, 0x4614b5f8,
+ 0xf000460d, 0x2800f848, 0x192cd118, 0x05a11e64, 0x0aa1d003, 0x028c1c49, 0x4e091e64, 0x2709447e,
+ 0xd80b42a5, 0x60056830, 0x71c74806, 0xf8e8f000, 0xd1032800, 0x02892101, 0xe7f1186d, 0x0000bdf8,
+ 0x0000038c, 0x40020000, 0x2800b510, 0x4904d005, 0x71c82044, 0xf8d4f000, 0x2004bd10, 0x0000bd10,
+ 0x40020000, 0xd0122800, 0x68c94916, 0x01094a16, 0x00490f09, 0x5a51447a, 0xd00a0309, 0x60022200,
+ 0x21016041, 0x02896081, 0x461060c1, 0x20044770, 0x20644770, 0x28004770, 0x460bd005, 0x079b4313,
+ 0x2065d003, 0x20044770, 0x68034770, 0xd804428b, 0x18896840, 0x42881818, 0x2066d201, 0x20004770,
+ 0x00004770, 0x40048040, 0x00000312, 0x461db5f8, 0x460e0014, 0x461ad017, 0xffddf7ff, 0xd1132800,
+ 0x447f4f0a, 0xd00f2d00, 0x60066838, 0x6839cc01, 0x49076048, 0x71c82006, 0xf882f000, 0xd1032800,
+ 0x1f2d1d36, 0x2004e7ee, 0x0000bdf8, 0x000002c6, 0x40020000, 0xb081b5ff, 0x460e4614, 0xf7ff4605,
+ 0x2800ffba, 0x68a9d127, 0xf0006868, 0x9000f881, 0x42404271, 0x424d4001, 0xd10142b5, 0x182d9800,
+ 0xd0172c00, 0x42a71baf, 0x4627d900, 0x08b9480b, 0x68004478, 0x480a6006, 0x71c22201, 0x72c20a0a,
+ 0x99047281, 0xf0007241, 0x2800f84b, 0x1be4d103, 0xe7e319f6, 0xb0052000, 0x0000bdf0, 0x00000258,
+ 0x40020000, 0x2800b510, 0x4804d006, 0x71c22240, 0xf0007181, 0xbd10f835, 0xbd102004, 0x40020000,
+ 0x9f08b5f8, 0x4616001c, 0xd004460d, 0xff73f7ff, 0xd1012800, 0x2004e01d, 0x480fbdf8, 0x68014478,
+ 0x490e600d, 0x71ca2202, 0x72ca9a06, 0x68216800, 0xf0006081, 0x2800f815, 0x9907d008, 0xd0002900,
+ 0x2f00600d, 0x2100d0e8, 0xbdf86039, 0x1d241f36, 0x2e001d2d, 0xbdf8d1e1, 0x000001ec, 0x40020000,
+ 0x2170480a, 0x21807001, 0x78017001, 0xd0fc09c9, 0x06817800, 0x2067d501, 0x06c14770, 0x2068d501,
+ 0x07c04770, 0x2069d0fc, 0x00004770, 0x40020000, 0x09032200, 0xd32c428b, 0x428b0a03, 0x2300d311,
+ 0xe04e469c, 0x430b4603, 0x2200d43c, 0x428b0843, 0x0903d331, 0xd31c428b, 0x428b0a03, 0x4694d301,
+ 0x09c3e03f, 0xd301428b, 0x1ac001cb, 0x09834152, 0xd301428b, 0x1ac0018b, 0x09434152, 0xd301428b,
+ 0x1ac0014b, 0x09034152, 0xd301428b, 0x1ac0010b, 0x08c34152, 0xd301428b, 0x1ac000cb, 0x08834152,
+ 0xd301428b, 0x1ac0008b, 0x08434152, 0xd301428b, 0x1ac0004b, 0x1a414152, 0x4601d200, 0x46104152,
+ 0xe05d4770, 0xd0000fca, 0x10034249, 0x4240d300, 0x22004053, 0x0903469c, 0xd32d428b, 0x428b0a03,
+ 0x22fcd312, 0xba120189, 0x428b0a03, 0x0189d30c, 0x428b1192, 0x0189d308, 0x428b1192, 0x0189d304,
+ 0x1192d03a, 0x0989e000, 0x428b09c3, 0x01cbd301, 0x41521ac0, 0x428b0983, 0x018bd301, 0x41521ac0,
+ 0x428b0943, 0x014bd301, 0x41521ac0, 0x428b0903, 0x010bd301, 0x41521ac0, 0x428b08c3, 0x00cbd301,
+ 0x41521ac0, 0x428b0883, 0x008bd301, 0x41521ac0, 0x0843d2d9, 0xd301428b, 0x1ac0004b, 0x1a414152,
+ 0x4601d200, 0x41524663, 0x4610105b, 0x4240d301, 0xd5002b00, 0x47704249, 0x105b4663, 0x4240d300,
+ 0x2000b501, 0x46c046c0, 0x0002bd02, 0x00000004, 0x00000008, 0x00000010, 0x00000020, 0x00000040,
+ 0x00000000, 0x00000000, 0x00000020, 0x40020004, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 1024},
+ };
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000039, // UnInit
+ 0x2000003D, // EraseChip
+ 0x2000005F, // EraseSector
+ 0x2000008B, // ProgramPage
+ 0x0, // Verify
+
+ // breakpoint = RAM start + 1
+ // RSB : base address is address of Execution Region PrgData in map file
+ // to access global/static data
+ // RSP : Initial stack pointer
+ {
+ 0x20000001, // breakpoint instruction address
+ 0x20000000 + 0x20 + 0x474, // static base register value (image start + header + static base offset)
+ 0x20000800 // initial stack pointer
+ },
+
+ 0x20000a00, // program_buffer, any valid RAM location with +512 bytes of headroom
+ 0x20000000, // algo_start, start of RAM
+ sizeof(KL26Z_FLM), // algo_size, size of array above
+ KL26Z_FLM, // image, flash algo instruction array
+ 512 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/kl26z/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/kl26z/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the kl26z
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(128),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x1FFF0000,
+ .ram_regions[0].end = 0x20004000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/kl27z/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/kl27z/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,98 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the kl27z
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t KL27Z_FLM[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x492bb510, 0x60082000, 0x4448482a, 0xf88af000, 0xd0002800, 0xbd102001, 0x47702000, 0xb5104825,
+ 0xf0004448, 0x0004f871, 0x4822d105, 0x44482100, 0xf908f000, 0xf0004604, 0x4620f834, 0xb570bd10,
+ 0x46014605, 0x2201481b, 0xf0004448, 0x0004f837, 0x4818d107, 0x22012300, 0x44484629, 0xf8baf000,
+ 0xf0004604, 0x4620f81e, 0xb5febd70, 0x460b460d, 0x46014607, 0x4616480f, 0xf0004448, 0x0004f887,
+ 0x9001d10b, 0x21019002, 0x9100480a, 0x462a4633, 0x44484639, 0xf8e4f000, 0xf0004604, 0x4620f802,
+ 0x4805bdfe, 0x220168c1, 0x43110292, 0x477060c1, 0x40048100, 0x00000004, 0xf0003000, 0x4614b5f8,
+ 0xf000460d, 0x2800f848, 0x192cd118, 0x05a11e64, 0x0aa1d003, 0x028c1c49, 0x4e091e64, 0x2709447e,
+ 0xd80b42a5, 0x60056830, 0x71c74806, 0xf8e8f000, 0xd1032800, 0x02892101, 0xe7f1186d, 0x0000bdf8,
+ 0x0000038c, 0x40020000, 0x2800b510, 0x4904d005, 0x71c82044, 0xf8d4f000, 0x2004bd10, 0x0000bd10,
+ 0x40020000, 0xd0122800, 0x68c94916, 0x01094a16, 0x00490f09, 0x5a51447a, 0xd00a0309, 0x60022200,
+ 0x21016041, 0x02896081, 0x461060c1, 0x20044770, 0x20644770, 0x28004770, 0x460bd005, 0x079b4313,
+ 0x2065d003, 0x20044770, 0x68034770, 0xd804428b, 0x18896840, 0x42881818, 0x2066d201, 0x20004770,
+ 0x00004770, 0x40048040, 0x00000312, 0x461db5f8, 0x460e0014, 0x461ad017, 0xffddf7ff, 0xd1132800,
+ 0x447f4f0a, 0xd00f2d00, 0x60066838, 0x6839cc01, 0x49076048, 0x71c82006, 0xf882f000, 0xd1032800,
+ 0x1f2d1d36, 0x2004e7ee, 0x0000bdf8, 0x000002c6, 0x40020000, 0xb081b5ff, 0x460e4614, 0xf7ff4605,
+ 0x2800ffba, 0x68a9d127, 0xf0006868, 0x9000f881, 0x42404271, 0x424d4001, 0xd10142b5, 0x182d9800,
+ 0xd0172c00, 0x42a71baf, 0x4627d900, 0x08b9480b, 0x68004478, 0x480a6006, 0x71c22201, 0x72c20a0a,
+ 0x99047281, 0xf0007241, 0x2800f84b, 0x1be4d103, 0xe7e319f6, 0xb0052000, 0x0000bdf0, 0x00000258,
+ 0x40020000, 0x2800b510, 0x4804d006, 0x71c22240, 0xf0007181, 0xbd10f835, 0xbd102004, 0x40020000,
+ 0x9f08b5f8, 0x4616001c, 0xd004460d, 0xff73f7ff, 0xd1012800, 0x2004e01d, 0x480fbdf8, 0x68014478,
+ 0x490e600d, 0x71ca2202, 0x72ca9a06, 0x68216800, 0xf0006081, 0x2800f815, 0x9907d008, 0xd0002900,
+ 0x2f00600d, 0x2100d0e8, 0xbdf86039, 0x1d241f36, 0x2e001d2d, 0xbdf8d1e1, 0x000001ec, 0x40020000,
+ 0x2170480a, 0x21807001, 0x78017001, 0xd0fc09c9, 0x06817800, 0x2067d501, 0x06c14770, 0x2068d501,
+ 0x07c04770, 0x2069d0fc, 0x00004770, 0x40020000, 0x09032200, 0xd32c428b, 0x428b0a03, 0x2300d311,
+ 0xe04e469c, 0x430b4603, 0x2200d43c, 0x428b0843, 0x0903d331, 0xd31c428b, 0x428b0a03, 0x4694d301,
+ 0x09c3e03f, 0xd301428b, 0x1ac001cb, 0x09834152, 0xd301428b, 0x1ac0018b, 0x09434152, 0xd301428b,
+ 0x1ac0014b, 0x09034152, 0xd301428b, 0x1ac0010b, 0x08c34152, 0xd301428b, 0x1ac000cb, 0x08834152,
+ 0xd301428b, 0x1ac0008b, 0x08434152, 0xd301428b, 0x1ac0004b, 0x1a414152, 0x4601d200, 0x46104152,
+ 0xe05d4770, 0xd0000fca, 0x10034249, 0x4240d300, 0x22004053, 0x0903469c, 0xd32d428b, 0x428b0a03,
+ 0x22fcd312, 0xba120189, 0x428b0a03, 0x0189d30c, 0x428b1192, 0x0189d308, 0x428b1192, 0x0189d304,
+ 0x1192d03a, 0x0989e000, 0x428b09c3, 0x01cbd301, 0x41521ac0, 0x428b0983, 0x018bd301, 0x41521ac0,
+ 0x428b0943, 0x014bd301, 0x41521ac0, 0x428b0903, 0x010bd301, 0x41521ac0, 0x428b08c3, 0x00cbd301,
+ 0x41521ac0, 0x428b0883, 0x008bd301, 0x41521ac0, 0x0843d2d9, 0xd301428b, 0x1ac0004b, 0x1a414152,
+ 0x4601d200, 0x41524663, 0x4610105b, 0x4240d301, 0xd5002b00, 0x47704249, 0x105b4663, 0x4240d300,
+ 0x2000b501, 0x46c046c0, 0x0002bd02, 0x00000004, 0x00000008, 0x00000010, 0x00000020, 0x00000040,
+ 0x00000000, 0x00000000, 0x00000020, 0x40020004, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 1024},
+ };
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000039, // UnInit
+ 0x2000003D, // EraseChip
+ 0x2000005F, // EraseSector
+ 0x2000008B, // ProgramPage
+ 0x0, // Verify
+
+ // breakpoint = RAM start + 1
+ // RSB : base address is address of Execution Region PrgData in map file
+ // to access global/static data
+ // RSP : Initial stack pointer
+ {
+ 0x20000001, // breakpoint instruction address
+ 0x20000000 + 0x20 + 0x474, // static base register value (image start + header + static base offset)
+ 0x20000800 // initial stack pointer
+ },
+
+ 0x20000a00, // program_buffer, any valid RAM location with +512 bytes of headroom
+ 0x20000000, // algo_start, start of RAM
+ sizeof(KL27Z_FLM), // algo_size, size of array above
+ KL27Z_FLM, // image, flash algo instruction array
+ 512 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/kl27z/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/kl27z/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the kl27z
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(64),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x1FFFF000,
+ .ram_regions[0].end = 0x20003000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/kl28z/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/kl28z/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,112 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the kl46z
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t KL28Z_FLM[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x4832b510, 0x60414930, 0x60814931, 0x22806801, 0x22204391, 0x60014311, 0x4448482e, 0xf860f000,
+ 0xd0002800, 0xbd102001, 0x47702000, 0xb5104829, 0x44484929, 0xf922f000, 0xd1042800, 0x21004825,
+ 0xf0004448, 0x4a25f9c3, 0x230168d1, 0x4319029b, 0xbd1060d1, 0x4c1fb570, 0x444c4605, 0x4b1e4601,
+ 0x68e24620, 0xf89ef000, 0xd1052800, 0x46292300, 0x68e24620, 0xf916f000, 0x68ca4918, 0x029b2301,
+ 0x60ca431a, 0xb570bd70, 0x460b460c, 0x46014606, 0xb0844810, 0x44484615, 0xf8bef000, 0xd10a2800,
+ 0x90029001, 0x480b2101, 0x462b9100, 0x46314622, 0xf0004448, 0x4909f957, 0x230168ca, 0x431a029b,
+ 0xb00460ca, 0x0000bd70, 0xd928c520, 0x40076000, 0x0000ffff, 0x00000004, 0x6b65666b, 0xf0003000,
+ 0xd00a2800, 0x68c9492b, 0x0e094a2b, 0x447a0049, 0x03095a51, 0x2064d103, 0x20044770, 0xb4104770,
+ 0x60032300, 0x21026041, 0x02896081, 0x492360c1, 0x158a7a0c, 0x610240a2, 0x61837ac9, 0xbc106141,
+ 0x47704618, 0xd0022800, 0x20006181, 0x20044770, 0x28004770, 0x2004d101, 0xb4104770, 0x42191e5b,
+ 0x421ad101, 0xbc10d002, 0x47702065, 0x428b6803, 0x6840d804, 0x18181889, 0xd2024288, 0x2066bc10,
+ 0xbc104770, 0x47702000, 0x4288490d, 0x206bd001, 0x20004770, 0x28004770, 0x290fd008, 0x2a04d802,
+ 0xe005d104, 0xd8012913, 0xd0012a08, 0x47702004, 0x47702000, 0x40075040, 0x00000512, 0x40020020,
+ 0x6b65666b, 0x4605b5f8, 0x460c4616, 0xf7ff4618, 0x2800ffdb, 0x2308d12b, 0x46214632, 0xf7ff4628,
+ 0x0007ffb8, 0x19a6d123, 0x1e7668e9, 0x91004630, 0xf922f000, 0xd0032900, 0x1c409e00, 0x1e764346,
+ 0xd81342b4, 0x4478480a, 0x60046800, 0x20094909, 0xf00071c8, 0x4607f8f9, 0x280069a8, 0x4780d000,
+ 0xd1032f00, 0x190468e8, 0xd9eb42b4, 0xbdf84638, 0x00000416, 0x40020000, 0xd1012a00, 0x47702004,
+ 0x461cb5ff, 0x4615b081, 0x2304460e, 0x98014622, 0xff7ff7ff, 0xd11a0007, 0xd0172c00, 0x4478480d,
+ 0x600e6801, 0x6800cd02, 0x490b6041, 0x71c82006, 0xf8caf000, 0x98014607, 0x28006980, 0x4780d000,
+ 0xd1032f00, 0x1d361f24, 0xd1e72c00, 0xb0054638, 0x0000bdf0, 0x000003be, 0x40020000, 0x4604b510,
+ 0xf7ff4608, 0x2800ff71, 0x2c00d106, 0x4904d005, 0x71c82044, 0xf8a8f000, 0x2004bd10, 0x0000bd10,
+ 0x40020000, 0xb081b5ff, 0x460e4614, 0x23084605, 0xff3ff7ff, 0xd12a2800, 0x686868a9, 0xf8acf000,
+ 0x42719000, 0x40014240, 0x42b7424f, 0x9800d101, 0x2c00183f, 0x1bbdd01a, 0xd90042a5, 0x490d4625,
+ 0x447908e8, 0x600e6809, 0x2201490b, 0x0a0271ca, 0x728872ca, 0x72489804, 0xf876f000, 0xd1062800,
+ 0x1b649800, 0x183f1976, 0xd1e42c00, 0xb0052000, 0x0000bdf0, 0x0000031a, 0x40020000, 0xd00c2800,
+ 0xd00a2a00, 0xd21a2908, 0x447b000b, 0x18db791b, 0x0705449f, 0x0d0b0907, 0x2004110f, 0x68c04770,
+ 0x6840e00a, 0x6880e008, 0x6800e006, 0x2001e004, 0x6900e002, 0x6940e000, 0x20006010, 0x206a4770,
+ 0x00004770, 0xd1012b00, 0x47702004, 0x461cb5f8, 0x460e4615, 0x9f082304, 0xfedbf7ff, 0xd1192800,
+ 0xd0172d00, 0x447a4a0f, 0x60066810, 0x2102480e, 0x990671c1, 0x681172c1, 0x60886820, 0xf824f000,
+ 0xd0082800, 0x29009907, 0x600ed000, 0xd0012f00, 0x60392100, 0x1d24bdf8, 0x1d361f2d, 0xd1e12d00,
+ 0x0000bdf8, 0x00000276, 0x40020000, 0xd1012800, 0x47702004, 0x4803b510, 0x71c22240, 0xf0007181,
+ 0xbd10f803, 0x40020000, 0x2170480a, 0x21807001, 0x78017001, 0xd5fc0609, 0x06817800, 0x2067d501,
+ 0x06c14770, 0x2068d501, 0x07c04770, 0x2069d0fc, 0x00004770, 0x40020000, 0x09032200, 0xd373428b,
+ 0x428b0a03, 0x0b03d358, 0xd33c428b, 0x428b0c03, 0xe012d321, 0x430b4603, 0x2200d47f, 0x428b0843,
+ 0x0903d374, 0xd35f428b, 0x428b0a03, 0x0b03d344, 0xd328428b, 0x428b0c03, 0x22ffd30d, 0xba120209,
+ 0x428b0c03, 0x1212d302, 0xd0650209, 0x428b0b03, 0xe000d319, 0x0bc30a09, 0xd301428b, 0x1ac003cb,
+ 0x0b834152, 0xd301428b, 0x1ac0038b, 0x0b434152, 0xd301428b, 0x1ac0034b, 0x0b034152, 0xd301428b,
+ 0x1ac0030b, 0x0ac34152, 0xd301428b, 0x1ac002cb, 0x0a834152, 0xd301428b, 0x1ac0028b, 0x0a434152,
+ 0xd301428b, 0x1ac0024b, 0x0a034152, 0xd301428b, 0x1ac0020b, 0xd2cd4152, 0x428b09c3, 0x01cbd301,
+ 0x41521ac0, 0x428b0983, 0x018bd301, 0x41521ac0, 0x428b0943, 0x014bd301, 0x41521ac0, 0x428b0903,
+ 0x010bd301, 0x41521ac0, 0x428b08c3, 0x00cbd301, 0x41521ac0, 0x428b0883, 0x008bd301, 0x41521ac0,
+ 0x428b0843, 0x004bd301, 0x41521ac0, 0xd2001a41, 0x41524601, 0x47704610, 0x0fcae05d, 0x4249d000,
+ 0xd3001003, 0x40534240, 0x469c2200, 0x428b0903, 0x0a03d32d, 0xd312428b, 0x018922fc, 0x0a03ba12,
+ 0xd30c428b, 0x11920189, 0xd308428b, 0x11920189, 0xd304428b, 0xd03a0189, 0xe0001192, 0x09c30989,
+ 0xd301428b, 0x1ac001cb, 0x09834152, 0xd301428b, 0x1ac0018b, 0x09434152, 0xd301428b, 0x1ac0014b,
+ 0x09034152, 0xd301428b, 0x1ac0010b, 0x08c34152, 0xd301428b, 0x1ac000cb, 0x08834152, 0xd301428b,
+ 0x1ac0008b, 0xd2d94152, 0x428b0843, 0x004bd301, 0x41521ac0, 0xd2001a41, 0x46634601, 0x105b4152,
+ 0xd3014610, 0x2b004240, 0x4249d500, 0x46634770, 0xd300105b, 0xb5014240, 0x46c02000, 0xbd0246c0,
+ 0x40020004, 0x00000000, 0x00000000, 0x00100000, 0x00200000, 0x00400000, 0x00800000, 0x00000000,
+ 0x00800000, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 1024},
+ };
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000049, // UnInit
+ 0x2000004D, // EraseChip
+ 0x20000075, // EraseSector
+ 0x200000A7, // ProgramPage
+ 0x0, // Verify
+
+ // breakpoint = RAM start + 1
+ // RSB : base address is address of Execution Region PrgData in map file
+ // to access global/static data
+ // RSP : Initial stack pointer
+ {
+ 0x20000001, // breakpoint instruction address
+ 0x20000000 + 0x20 + 0x624, // static base register value (image start + header + static base offset)
+ 0x20000800 // initial stack pointer
+ },
+
+ 0x20000a00, // program_buffer, any valid RAM location with +512 bytes of headroom
+ 0x20000000, // algo_start, start of RAM
+ sizeof(KL28Z_FLM), // algo_size, size of array above
+ KL28Z_FLM, // image, flash algo instruction array
+ 512 // program_buffer_size, largest size that can be written in a single call to program page
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/kl28z/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/kl28z/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the kl46z
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(256),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x1FFF8000,
+ .ram_regions[0].end = 0x20018000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/kl43z/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/kl43z/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,100 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the kl43z
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t mkl43z4_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x4937b510, 0x60082000, 0x78414836, 0x0f890649, 0xd0152902, 0x4a342100, 0x444a2900, 0xd0077011,
+ 0x229f7841, 0x70414011, 0x06497841, 0xd1fb0f89, 0x4448482e, 0xf85ef000, 0xd0002800, 0xbd102001,
+ 0xe7e82101, 0x44484828, 0x28007800, 0x4825d00a, 0x229f7841, 0x31404011, 0x78417041, 0x0f890649,
+ 0xd1fa2902, 0x47702000, 0xb5104820, 0x44484920, 0xf885f000, 0xd1042800, 0x2100481c, 0xf0004448,
+ 0xbd10f93e, 0x4c19b570, 0x444c4605, 0x4b184601, 0x68e24620, 0xf8abf000, 0xd1052800, 0x46292300,
+ 0x68e24620, 0xf935f000, 0xb570bd70, 0x460b460c, 0x46014606, 0xb084480d, 0x44484615, 0xf8daf000,
+ 0xd10a2800, 0x90029001, 0x48082101, 0x462b9100, 0x46314622, 0xf0004448, 0xb004f963, 0x0000bd70,
+ 0x40048100, 0x4007e000, 0x00000004, 0x00000008, 0x6b65666b, 0xd0182800, 0x68c949d7, 0x0f090109,
+ 0xd014290f, 0x00494ad5, 0x5a51447a, 0x22000289, 0x60416002, 0x60812102, 0x61826142, 0x62026102,
+ 0x62420249, 0x461060c1, 0x20044770, 0x21014770, 0xe7ec0489, 0xd0022800, 0x20006101, 0x20044770,
+ 0x46024770, 0x68c048c6, 0x02892101, 0x49c44308, 0x477060c8, 0x217048c3, 0x21807001, 0x78017001,
+ 0xd5fc0609, 0x06817800, 0x2067d501, 0x06c14770, 0x2068d501, 0x07c04770, 0x2069d0fc, 0x28004770,
+ 0x2004d101, 0xb5104770, 0x4ab64604, 0x605048b6, 0x428148b6, 0x206bd001, 0x2000e000, 0xd1072800,
+ 0xf7ff4620, 0x4603ffd7, 0xf7ff4620, 0x4618ffca, 0x2800bd10, 0x2004d101, 0xb5104770, 0x22004614,
+ 0x60a26062, 0x612260e2, 0x61a26162, 0x602161e2, 0x606168c1, 0x68406881, 0xf94ef000, 0x200460a0,
+ 0x612060e0, 0x61a06160, 0x200061e0, 0xb5ffbd10, 0x4615b089, 0x466a460c, 0xf7ff9809, 0x462affda,
+ 0x9b044621, 0xf0009809, 0x0007f90c, 0x9c00d130, 0x19659e01, 0x46311e6d, 0xf0004628, 0x2900f92d,
+ 0x1c40d002, 0x1e454370, 0xd81d42ac, 0x20090221, 0x06000a09, 0x488b1809, 0x498c6041, 0x4288980c,
+ 0x206bd001, 0x2000e000, 0xd1112800, 0xf7ff9809, 0x4607ff81, 0x69009809, 0xd0002800, 0x2f004780,
+ 0x19a4d102, 0xd9e142ac, 0xf7ff9809, 0x4638ff6a, 0xbdf0b00d, 0xd1012a00, 0x47702004, 0xb089b5ff,
+ 0x461e4614, 0x466a460d, 0xf7ff9809, 0x4632ff92, 0x9b034629, 0xf0009809, 0x0007f8c4, 0x9d00d12d,
+ 0xd0262e00, 0x486fcc02, 0x99036081, 0xd0022904, 0xd0072908, 0x022ae00e, 0x0a122103, 0x18510649,
+ 0xe0076041, 0x60c1cc02, 0x2107022a, 0x06090a12, 0x60411851, 0xf7ff9809, 0x4607ff3d, 0x69009809,
+ 0xd0002800, 0x2f004780, 0x9803d103, 0x1a361945, 0x9809d1d8, 0xff25f7ff, 0xb00d4638, 0x2800bdf0,
+ 0x4a5bd005, 0x18890409, 0x60514a56, 0x2004e722, 0xb5ff4770, 0x4614b08b, 0x460d461e, 0x980b466a,
+ 0xff47f7ff, 0x46294622, 0x980b9b05, 0xf879f000, 0xd1332800, 0x4629466a, 0xf7ff980b, 0x9d00ff3a,
+ 0x90089802, 0x42404269, 0x424f4001, 0xd10142af, 0x183f9808, 0xd0202c00, 0x90090230, 0x42a61b7e,
+ 0x4626d900, 0x99054630, 0xf886f000, 0x2101022a, 0x06090a12, 0x493b1852, 0x9a09604a, 0x43100400,
+ 0x608830ff, 0xf7ff980b, 0x2800fee5, 0x9808d106, 0x19ad1ba4, 0x2c00183f, 0x2000d1e0, 0xbdf0b00f,
+ 0xd1012b00, 0x47702004, 0xb089b5ff, 0x461d4616, 0x466a460c, 0x98099f12, 0xfefbf7ff, 0x46214632,
+ 0x98099b07, 0xf82df000, 0xd11d2800, 0x2e009c00, 0x4928d01a, 0x18470638, 0x20010221, 0x06400a09,
+ 0x48201809, 0x60876041, 0x60c16829, 0xf7ff9809, 0x2800feb1, 0x9913d00a, 0xd0002900, 0x9914600c,
+ 0xd0012900, 0x600a2200, 0xbdf0b00d, 0x1a769907, 0x00890889, 0x9907194d, 0x2e00190c, 0xb00dd1dc,
+ 0x2800bdf0, 0x2004d101, 0xb4104770, 0x42191e5b, 0x421ad101, 0xbc10d002, 0x47702065, 0x428b6803,
+ 0x6840d804, 0x18181889, 0xd2024288, 0x2066bc10, 0xbc104770, 0x47702000, 0x40048040, 0x000003a0,
+ 0xf0003000, 0x40020000, 0x44ffffff, 0x6b65666b, 0x4000ffff, 0x00ffffff, 0x460bb530, 0x20004601,
+ 0x24012220, 0x460de009, 0x429d40d5, 0x461dd305, 0x1b494095, 0x40954625, 0x46151940, 0x2d001e52,
+ 0xbd30dcf1, 0x40020004, 0x40020010, 0x00100008, 0x00200018, 0x00400030, 0x00800060, 0x010000c0,
+ 0x02000180, 0x04000300, 0x00000600, 0x00000000, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 1024},
+ };
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000065, // UnInit
+ 0x20000089, // EraseChip
+ 0x200000A5, // EraseSector
+ 0x200000CB, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000000 + 0x00000001,
+ 0x20000000 + 0x00000020 + 0x000004cc,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(mkl43z4_flash_prog_blob), // prog_blob size
+ mkl43z4_flash_prog_blob, // address of prog_blob
+ 0x00000200 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/kl43z/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/kl43z/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the kl43z
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(256),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x1fffe000,
+ .ram_regions[0].end = 0x20006000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/kl46z/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/kl46z/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,110 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the kl46z
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t KL46Z_FLM[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x4604b570, 0x4616460d, 0x49302000, 0x48306008, 0xf0004448, 0x2800f8e9, 0x2001d001, 0x2000bd70,
+ 0x4601e7fc, 0x47702000, 0x492ab510, 0x44484828, 0xf8c2f000, 0x2c004604, 0x2100d105, 0x44484824,
+ 0xf9bef000, 0xf0004604, 0x4620f838, 0xb570bd10, 0x481f4604, 0x4b1f4448, 0x68c24621, 0xf862f000,
+ 0x2d004605, 0x481ad107, 0x23004448, 0x68c24621, 0xf956f000, 0xf0004605, 0x4628f820, 0xb5febd70,
+ 0x460c4605, 0x46234616, 0x46294632, 0x44484810, 0xf90af000, 0x2f004607, 0x2201d10b, 0x46339001,
+ 0x90029200, 0x46294622, 0x44484809, 0xf99af000, 0xf0004607, 0x4638f802, 0x4807bdfe, 0x210168c0,
+ 0x43880289, 0x49041840, 0x477060c8, 0x40048100, 0x00000004, 0x6b65666b, 0xf0003000, 0x4a102070,
+ 0x20807010, 0xbf007010, 0x7800480d, 0x280009c0, 0x480bd0fa, 0x20207801, 0x28004008, 0x2067d001,
+ 0x20104770, 0x28004008, 0x2068d001, 0x07c8e7f8, 0x28000fc0, 0x2069d001, 0x2000e7f2, 0x0000e7f0,
+ 0x40020000, 0xb081b5ff, 0x460d4604, 0xf0009804, 0x4606f89f, 0xd0022e00, 0xb0054630, 0x2304bdf0,
+ 0x46204629, 0xf0009a03, 0x4606f876, 0xd0012e00, 0xe7f24630, 0x18289803, 0x46381e47, 0xf00068e1,
+ 0x2900f983, 0x4638d009, 0xf00068e1, 0x1c40f97d, 0x68e19000, 0x43489800, 0xe0131e47, 0x4478480c,
+ 0x60056800, 0x490b2009, 0xf7ff71c8, 0x4606ffa7, 0x280069a0, 0x69a0d001, 0x2e004780, 0xe003d000,
+ 0x194568e0, 0xd9e942bd, 0x4630bf00, 0x0000e7c5, 0x00000462, 0x40020000, 0x4604b570, 0x4628460d,
+ 0xf856f000, 0x2e004606, 0x4630d001, 0x2c00bd70, 0x2004d101, 0x2044e7fa, 0x71c84902, 0xff7ef7ff,
+ 0x0000e7f4, 0x40020000, 0x29004601, 0x2004d101, 0x482a4770, 0x010068c0, 0x00400f00, 0x447b4b28,
+ 0x03025a18, 0xd1012a00, 0xe7f12064, 0x60082000, 0x2001604a, 0x02806088, 0x200060c8, 0x61486108,
+ 0xbf006188, 0x4602e7e4, 0xd1012a00, 0x47702004, 0x20006191, 0xb530e7fb, 0x2c004604, 0x2004d101,
+ 0x1e58bd30, 0x28004008, 0x1e58d103, 0x28004010, 0x2065d001, 0x6820e7f4, 0xd8054288, 0x68206865,
+ 0x188d1940, 0xd20142a8, 0xe7e92066, 0xe7e72000, 0x480c4601, 0xd0014281, 0x4770206b, 0xe7fc2000,
+ 0x2b004603, 0x2004d101, 0x290f4770, 0x2a04d801, 0x2004d001, 0x2000e7f8, 0x0000e7f6, 0x40048040,
+ 0x000003c0, 0x6b65666b, 0xb081b5ff, 0x46144607, 0x2c00461d, 0x2004d102, 0xbdf0b005, 0x462a2304,
+ 0x99024638, 0xffb7f7ff, 0x2e004606, 0x4630d001, 0xe01ce7f2, 0x44794910, 0x68099802, 0xcc016008,
+ 0x4479490d, 0x6809390c, 0x20066048, 0x71c8490b, 0xfef4f7ff, 0x69b84606, 0xd0012800, 0x478069b8,
+ 0xd0002e00, 0x9802e005, 0x90021d00, 0x2d001f2d, 0xbf00d1e0, 0xe7cf4630, 0x0000030a, 0x40020000,
+ 0xb083b5ff, 0x2304460c, 0x9a054621, 0xf7ff9803, 0x9002ff82, 0x28009802, 0x9802d002, 0xbdf0b007,
+ 0x68919a03, 0xf0006850, 0x4605f88f, 0x42684261, 0x424e4001, 0xd10042a6, 0x9f051976, 0x1b30e027,
+ 0x98019001, 0xd90042b8, 0x98019701, 0x90000880, 0x44784811, 0x60046800, 0x49102001, 0x980071c8,
+ 0x0e010400, 0x72c1480d, 0x9800490c, 0x98067288, 0xf7ff7248, 0x9002fea3, 0x28009802, 0x9802d001,
+ 0x9801e7cc, 0x98011a3f, 0x19761824, 0x2f00bf00, 0x2000d1d5, 0x0000e7c2, 0x0000026e, 0x40020000,
+ 0x4604b570, 0x2c00460d, 0x2004d101, 0x2040bd70, 0x71c84903, 0x71854608, 0xfe80f7ff, 0x0000e7f6,
+ 0x40020000, 0xb081b5ff, 0x4617460c, 0x2d00461d, 0x2004d102, 0xbdf0b005, 0x463a2304, 0x98014621,
+ 0xff19f7ff, 0x2e004606, 0x4630d001, 0xe022e7f2, 0x44784813, 0x60046800, 0x49122002, 0x980a71c8,
+ 0x490f72c8, 0x39124479, 0x68096828, 0xf7ff6088, 0x4606fe55, 0xd00b2e00, 0x2800980b, 0x980bd001,
+ 0x980c6004, 0xd0022800, 0x980c2100, 0xe0046001, 0x1d2d1f3f, 0x2f001d24, 0xbf00d1da, 0xe7c94630,
+ 0x000001ce, 0x40020000, 0x09032200, 0xd32c428b, 0x428b0a03, 0x2300d311, 0xe04e469c, 0x430b4603,
+ 0x2200d43c, 0x428b0843, 0x0903d331, 0xd31c428b, 0x428b0a03, 0x4694d301, 0x09c3e03f, 0xd301428b,
+ 0x1ac001cb, 0x09834152, 0xd301428b, 0x1ac0018b, 0x09434152, 0xd301428b, 0x1ac0014b, 0x09034152,
+ 0xd301428b, 0x1ac0010b, 0x08c34152, 0xd301428b, 0x1ac000cb, 0x08834152, 0xd301428b, 0x1ac0008b,
+ 0x08434152, 0xd301428b, 0x1ac0004b, 0x1a414152, 0x4601d200, 0x46104152, 0xe05d4770, 0xd0000fca,
+ 0x10034249, 0x4240d300, 0x22004053, 0x0903469c, 0xd32d428b, 0x428b0a03, 0x22fcd312, 0xba120189,
+ 0x428b0a03, 0x0189d30c, 0x428b1192, 0x0189d308, 0x428b1192, 0x0189d304, 0x1192d03a, 0x0989e000,
+ 0x428b09c3, 0x01cbd301, 0x41521ac0, 0x428b0983, 0x018bd301, 0x41521ac0, 0x428b0943, 0x014bd301,
+ 0x41521ac0, 0x428b0903, 0x010bd301, 0x41521ac0, 0x428b08c3, 0x00cbd301, 0x41521ac0, 0x428b0883,
+ 0x008bd301, 0x41521ac0, 0x0843d2d9, 0xd301428b, 0x1ac0004b, 0x1a414152, 0x4601d200, 0x41524663,
+ 0x4610105b, 0x4240d301, 0xd5002b00, 0x47704249, 0x105b4663, 0x4240d300, 0x2000b501, 0x46c046c0,
+ 0x0002bd02, 0x00000004, 0x00000008, 0x00000010, 0x00000020, 0x00000040, 0x00000000, 0x00000000,
+ 0x00000020, 0x40020004, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 1024},
+ };
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000021, // UnInit
+ 0x20000049, // EraseChip
+ 0x2000006F, // EraseSector
+ 0x2000009F, // ProgramPage
+ 0x0, // Verify
+
+ // breakpoint = RAM start + 1
+ // RSB : base address is address of Execution Region PrgData in map file
+ // to access global/static data
+ // RSP : Initial stack pointer
+ {
+ 0x20000001, // breakpoint instruction address
+ 0x20000000 + 0x20 + 0x5E8, // static base register value (image start + header + static base offset)
+ 0x20000800 // initial stack pointer
+ },
+
+ 0x20000a00, // program_buffer, any valid RAM location with +512 bytes of headroom
+ 0x20000000, // algo_start, start of RAM
+ sizeof(KL46Z_FLM), // algo_size, size of array above
+ KL46Z_FLM, // image, flash algo instruction array
+ 512 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/kl46z/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/kl46z/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the kl46z
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(256),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x1FFFE000,
+ .ram_regions[0].end = 0x20006000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/kl82z/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/kl82z/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,94 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t mkl82z7_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x483bb510, 0x81c14939, 0x81c1493a, 0x08498801, 0x80010049, 0x78414838, 0x0f890649, 0xd0152902,
+ 0x4a362100, 0x444a2900, 0xd0077011, 0x229f7841, 0x70414011, 0x06497841, 0xd1fb0f89, 0x44484830,
+ 0xf862f000, 0xd0002800, 0xbd102001, 0xe7e82101, 0x4448482a, 0x28007800, 0x4827d00a, 0x229f7841,
+ 0x31404011, 0x78417041, 0x0f890649, 0xd1fa2902, 0x47702000, 0xb5104822, 0x44484922, 0xf890f000,
+ 0xd1042800, 0x2100481e, 0xf0004448, 0xbd10f94a, 0x4c1bb570, 0x444c4605, 0x4b1a4601, 0x68e24620,
+ 0xf8b7f000, 0xd1052800, 0x46292300, 0x68e24620, 0xf941f000, 0xb570bd70, 0x460b460c, 0x46014606,
+ 0xb084480f, 0x44484615, 0xf8e6f000, 0xd10a2800, 0x90029001, 0x480a2101, 0x462b9100, 0x46314622,
+ 0xf0004448, 0xb004f96f, 0x0000bd70, 0x0000c520, 0x40052000, 0x0000d928, 0x4007e000, 0x00000004,
+ 0x00000008, 0x6b65666b, 0xd00b2800, 0x68c949db, 0x0f090109, 0xd007290f, 0x00494ad9, 0x5a51447a,
+ 0xe0030289, 0x47702004, 0x04492101, 0x2200b410, 0x60416002, 0x60812101, 0x60c102c9, 0x7a0c49d1,
+ 0x40a3158b, 0x7ac96143, 0x62026102, 0x61816242, 0x2000bc10, 0x28004770, 0x6101d002, 0x47702000,
+ 0x47702004, 0x48c84602, 0x210168c0, 0x43080289, 0x60c849c5, 0x48c54770, 0x70012170, 0x70012180,
+ 0x06097801, 0x7800d5fc, 0xd5010681, 0x47702067, 0xd50106c1, 0x47702068, 0xd0fc07c0, 0x47702069,
+ 0xd1012800, 0x47702004, 0x4604b510, 0x48b84ab7, 0x48b86050, 0xd0014281, 0xe000206b, 0x28002000,
+ 0x4620d107, 0xffd7f7ff, 0x46204603, 0xffcaf7ff, 0xbd104618, 0xd1012800, 0x47702004, 0x4614b510,
+ 0x60622200, 0x60e260a2, 0x61626122, 0x61e261a2, 0x68c16021, 0x68816061, 0xf0006840, 0x60a0f951,
+ 0x20042108, 0x60e06121, 0x616161a0, 0x200061e0, 0xb5ffbd10, 0x4615b089, 0x466a460c, 0xf7ff9809,
+ 0x462affd9, 0x9b044621, 0xf0009809, 0x0007f90c, 0x9c00d130, 0x19659e01, 0x46311e6d, 0xf0004628,
+ 0x2900f92f, 0x1c40d002, 0x1e454370, 0xd81d42ac, 0x20090221, 0x06000a09, 0x488c1809, 0x498d6041,
+ 0x4288980c, 0x206bd001, 0x2000e000, 0xd1112800, 0xf7ff9809, 0x4607ff80, 0x69009809, 0xd0002800,
+ 0x2f004780, 0x19a4d102, 0xd9e142ac, 0xf7ff9809, 0x4638ff69, 0xbdf0b00d, 0xd1012a00, 0x47702004,
+ 0xb089b5ff, 0x461e4614, 0x466a460d, 0xf7ff9809, 0x4632ff91, 0x9b034629, 0xf0009809, 0x0007f8c4,
+ 0x9d00d12d, 0xd0262e00, 0x4870cc02, 0x99036081, 0xd0022904, 0xd0072908, 0x022ae00e, 0x0a122103,
+ 0x18510649, 0xe0076041, 0x60c1cc02, 0x2107022a, 0x06090a12, 0x60411851, 0xf7ff9809, 0x4607ff3c,
+ 0x69009809, 0xd0002800, 0x2f004780, 0x9803d103, 0x1a361945, 0x9809d1d8, 0xff24f7ff, 0xb00d4638,
+ 0x2800bdf0, 0x4a5cd005, 0x18890409, 0x60514a57, 0x2004e721, 0xb5ff4770, 0x4614b08b, 0x460d461e,
+ 0x980b466a, 0xff46f7ff, 0x46294622, 0x980b9b05, 0xf879f000, 0xd1332800, 0x4629466a, 0xf7ff980b,
+ 0x9d00ff39, 0x90089802, 0x42404269, 0x424f4001, 0xd10142af, 0x183f9808, 0xd0202c00, 0x90090230,
+ 0x42a61b7e, 0x4626d900, 0x99054630, 0xf888f000, 0x2101022a, 0x06090a12, 0x493c1852, 0x9a09604a,
+ 0x43100400, 0x608830ff, 0xf7ff980b, 0x2800fee4, 0x9808d106, 0x19ad1ba4, 0x2c00183f, 0x2000d1e0,
+ 0xbdf0b00f, 0xd1012b00, 0x47702004, 0xb089b5ff, 0x461d4616, 0x466a460c, 0x98099f12, 0xfefaf7ff,
+ 0x46214632, 0x98099b07, 0xf82df000, 0xd11d2800, 0x2e009c00, 0x4929d01a, 0x18470638, 0x20010221,
+ 0x06400a09, 0x48211809, 0x60876041, 0x60c16829, 0xf7ff9809, 0x2800feb0, 0x9913d00a, 0xd0002900,
+ 0x9914600c, 0xd0012900, 0x600a2200, 0xbdf0b00d, 0x1a769907, 0x00890889, 0x9907194d, 0x2e00190c,
+ 0xb00dd1dc, 0x2800bdf0, 0x2004d101, 0xb4104770, 0x42191e5b, 0x421ad101, 0xbc10d002, 0x47702065,
+ 0x428b6803, 0x6840d804, 0x18181889, 0xd2024288, 0x2066bc10, 0xbc104770, 0x47702000, 0x40048040,
+ 0x000003b4, 0x40020020, 0xf0003000, 0x40020000, 0x44ffffff, 0x6b65666b, 0x4000ffff, 0x00ffffff,
+ 0x460bb530, 0x20004601, 0x24012220, 0x460de009, 0x429d40d5, 0x461dd305, 0x1b494095, 0x40954625,
+ 0x46151940, 0x2d001e52, 0xbd30dcf1, 0x40020004, 0x40020010, 0x00100008, 0x00200018, 0x00400030,
+ 0x00800060, 0x010000c0, 0x02000180, 0x04000300, 0x00000600, 0x00000000, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 1024},
+ };
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000071, // UnInit
+ 0x20000095, // EraseChip
+ 0x200000B1, // EraseSector
+ 0x200000D7, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000000 + 0x00000001,
+ 0x20000000 + 0x00000020 + 0x000004f4,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(mkl82z7_flash_prog_blob), // prog_blob size
+ mkl82z7_flash_prog_blob, // address of prog_blob
+ 0x00000200 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/kl82z/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/kl82z/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the kl46z
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(128),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x1FFFA000,
+ .ram_regions[0].end = 0x20012000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/kw24d/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/kw24d/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,102 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the kw24d
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+const uint32_t mkw24d5_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0xb510483e, 0x5120f24c, 0xf64d81c1, 0x81c11128, 0xf0218801, 0x80010101, 0x78414839, 0x0160f001,
+ 0xbf0c2940, 0x21002101, 0x444a4a36, 0xb1397011, 0xf0217841, 0x70410160, 0xf0117841, 0xd1fb0f60,
+ 0x44484831, 0xf864f000, 0xbf182800, 0xbd102001, 0x4448482c, 0xb1587800, 0x78414829, 0x0160f021,
+ 0x0140f041, 0x78417041, 0x0160f001, 0xd1fa2940, 0x47702000, 0xb5104824, 0x44484924, 0xf893f000,
+ 0xbf182800, 0x2100bd10, 0xe8bd481f, 0x44484010, 0xb959f000, 0x4c1cb570, 0x444c4605, 0x4b1b4601,
+ 0x68e24620, 0xf8b7f000, 0xbf182800, 0x2300bd70, 0x68e24629, 0x4070e8bd, 0x44484813, 0xb94df000,
+ 0x460cb570, 0x4606460b, 0x480f4601, 0x4615b084, 0xf0004448, 0x2800f8ec, 0xb004bf1c, 0x2000bd70,
+ 0xe9cd2101, 0x90021000, 0x462b4807, 0x46314622, 0xf0004448, 0xb004f980, 0x0000bd70, 0x40052000,
+ 0x4007e000, 0x00000004, 0x00000008, 0x6b65666b, 0xbf042800, 0x47702004, 0x6cc949eb, 0x6103f3c1,
+ 0xbf08290f, 0x2100f44f, 0x4ae8bf1f, 0xf832447a, 0x02891011, 0xe9c02200, 0x21022100, 0x61426081,
+ 0x61820289, 0x1203e9c0, 0x51a0f04f, 0xf44f6201, 0x62415180, 0x47704610, 0xbf0e2800, 0x61012004,
+ 0x47702000, 0x48da4602, 0x49d96840, 0x0070f440, 0x47706048, 0x217048d7, 0x21807001, 0x78017001,
+ 0x0f80f011, 0x7800d0fb, 0x0f20f010, 0x2067bf1c, 0xf0104770, 0xbf1c0f10, 0x47702068, 0x0001f010,
+ 0x2069bf18, 0x28004770, 0x2004bf04, 0xb5104770, 0x4ac84604, 0x403bf06f, 0x48c76050, 0xbf144281,
+ 0x2000206b, 0xbf182800, 0x4620bd10, 0xffd2f7ff, 0x46204603, 0xffc6f7ff, 0xbd104618, 0xbf042800,
+ 0x47702004, 0x60532300, 0x60d36093, 0x61536113, 0x61d36193, 0x68c16011, 0xe9d06051, 0xfbb11001,
+ 0x6090f0f0, 0x21082004, 0x0103e9c2, 0x1005e9c2, 0x200061d0, 0xe92d4770, 0xb0884df0, 0x46984615,
+ 0x4682460c, 0xf7ff466a, 0x462affd9, 0x46504621, 0xf0009b04, 0x0007f931, 0xb008bf1c, 0x8df0e8bd,
+ 0x4600e9dd, 0x1e451960, 0xf0f6fbb5, 0x5010fb06, 0xfbb5b120, 0x1c40f0f6, 0x1e454370, 0xbf9842ac,
+ 0xb270f8df, 0xf024d81c, 0xf040407f, 0xf8cb6010, 0x48990004, 0xbf144580, 0x2000206b, 0xbf1c2800,
+ 0xe8bdb008, 0x46508df0, 0xff74f7ff, 0xf8da4607, 0x28000010, 0x4780bf18, 0x4434b917, 0xd9e242ac,
+ 0xf7ff4650, 0xb008ff5f, 0xe8bd4638, 0x2a008df0, 0x2004bf04, 0xe92d4770, 0xb08945f0, 0x461e4614,
+ 0x4680460d, 0xf7ff466a, 0x4632ff89, 0x46404629, 0xf0009b03, 0x0007f8e1, 0xb009bf1c, 0x85f0e8bd,
+ 0x2e009d00, 0xf8dfbf18, 0xd025a1ec, 0x0b04f854, 0x0008f8ca, 0x28049803, 0xf025bf04, 0xf040407f,
+ 0xd00960c0, 0xd1092808, 0x0b04f854, 0x000cf8ca, 0x407ff025, 0x60e0f040, 0x0004f8ca, 0xf7ff4640,
+ 0xf8d8ff29, 0x46071010, 0xbf182900, 0xb91f4788, 0x44059803, 0xd1d91a36, 0xf7ff4640, 0xb009ff13,
+ 0xe8bd4638, 0x280085f0, 0x2004bf04, 0x4a634770, 0x4101ea42, 0x60514a5f, 0xe92de70c, 0xb0884dff,
+ 0x469a4614, 0x466a460d, 0xf7ff9808, 0x4622ff37, 0x9b054629, 0xf0009808, 0x2800f88f, 0xb00cbf1c,
+ 0x8df0e8bd, 0x4629466a, 0xf7ff9808, 0x9e00ff27, 0x8008f8dd, 0xf1c84270, 0x40080100, 0x42b74247,
+ 0x4447bf08, 0xbf182c00, 0xb128f8df, 0x1bbdd01f, 0xbf8842a5, 0x98054625, 0x417ff026, 0xf0f0fbb5,
+ 0x7180f041, 0x1004f8cb, 0xea400400, 0xf040200a, 0xf8cb00ff, 0x98080008, 0xfeccf7ff, 0xbf1c2800,
+ 0xe8bdb00c, 0x1b648df0, 0x4447442e, 0xb00cd1df, 0xe8bd2000, 0x2b008df0, 0x2004bf04, 0xe92d4770,
+ 0xb0884dff, 0xe9dd4616, 0x461d7a14, 0x466a460c, 0x8058f8dd, 0xf7ff9808, 0xe9ddfee1, 0x46323007,
+ 0xf0004621, 0x2800f839, 0xb00cbf1c, 0x8df0e8bd, 0x2e009c00, 0xb00cbf04, 0x8df0e8bd, 0xb094f8df,
+ 0x407ff06f, 0x6707ea40, 0x407ff024, 0x7000f040, 0x0004f8cb, 0x7008f8cb, 0xf8cb6828, 0x9808000c,
+ 0xfe88f7ff, 0xf1bab168, 0xbf180f00, 0x4000f8ca, 0x0f00f1b8, 0x2100bf1c, 0x1000f8c8, 0xe8bdb00c,
+ 0x99078df0, 0xf0211a76, 0x440d0103, 0x440c9907, 0xb00cd1da, 0x8df0e8bd, 0xbf042800, 0x47702004,
+ 0x0301f1a3, 0xbf0e4219, 0x2065421a, 0x68034770, 0xd806428b, 0x44116840, 0x42884418, 0x2000bf24,
+ 0x20664770, 0x00004770, 0x40048000, 0x000003b8, 0x4001f000, 0x40020000, 0x6b65666b, 0x4000ffff,
+ 0x40020004, 0x40020010, 0x00100008, 0x00200018, 0x00400030, 0x00800060, 0x010000c0, 0x02000180,
+ 0x04000300, 0x00000600, 0x00000000, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 2048},
+ };
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000071, // UnInit
+ 0x20000095, // EraseChip
+ 0x200000B5, // EraseSector
+ 0x200000E1, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000000 + 0x00000001,
+ 0x20000000 + 0x00000020 + 0x00000508,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(mkw24d5_flash_prog_blob), // prog_blob size
+ mkw24d5_flash_prog_blob, // address of prog_blob
+ 0x00000200 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/kw24d/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/kw24d/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the kw24d
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(512),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x1FFF8000,
+ .ram_regions[0].end = 0x20008000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/kw41z/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/kw41z/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,127 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the kw41z
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t mkw41z4_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x492db510, 0x60082000, 0x4448482c, 0xf85cf000, 0xd0002800, 0xbd102001, 0x47702000, 0xb5104827,
+ 0x44484927, 0xf91ef000, 0xd1042800, 0x21004823, 0xf0004448, 0x4a23f9bf, 0x230168d1, 0x4319029b,
+ 0xbd1060d1, 0x4c1db570, 0x444c4605, 0x4b1c4601, 0x68e24620, 0xf89af000, 0xd1052800, 0x46292300,
+ 0x68e24620, 0xf912f000, 0x68ca4916, 0x029b2301, 0x60ca431a, 0xb570bd70, 0x460b460c, 0x46014606,
+ 0xb084480e, 0x44484615, 0xf8baf000, 0xd10a2800, 0x90029001, 0x48092101, 0x462b9100, 0x46314622,
+ 0xf0004448, 0x4907f953, 0x230168ca, 0x431a029b, 0xb00460ca, 0x0000bd70, 0x40048100, 0x00000004,
+ 0x6b65666b, 0xf0003000, 0xd00a2800, 0x68c9492b, 0x0e094a2b, 0x447a0049, 0x03095a51, 0x2064d103,
+ 0x20044770, 0xb4104770, 0x60032300, 0x21026041, 0x02896081, 0x492360c1, 0x158a7a0c, 0x610240a2,
+ 0x61837ac9, 0xbc106141, 0x47704618, 0xd0022800, 0x20006181, 0x20044770, 0x28004770, 0x2004d101,
+ 0xb4104770, 0x42191e5b, 0x421ad101, 0xbc10d002, 0x47702065, 0x428b6803, 0x6840d804, 0x18181889,
+ 0xd2024288, 0x2066bc10, 0xbc104770, 0x47702000, 0x4288490d, 0x206bd001, 0x20004770, 0x28004770,
+ 0x290fd008, 0x2a04d802, 0xe005d104, 0xd8012913, 0xd0012a08, 0x47702004, 0x47702000, 0x40048040,
+ 0x00000512, 0x40020020, 0x6b65666b, 0x4605b5f8, 0x460c4616, 0xf7ff4618, 0x2800ffdb, 0x2304d12b,
+ 0x46214632, 0xf7ff4628, 0x0007ffb8, 0x19a6d123, 0x1e7668e9, 0x91004630, 0xf922f000, 0xd0032900,
+ 0x1c409e00, 0x1e764346, 0xd81342b4, 0x4478480a, 0x60046800, 0x20094909, 0xf00071c8, 0x4607f8f9,
+ 0x280069a8, 0x4780d000, 0xd1032f00, 0x190468e8, 0xd9eb42b4, 0xbdf84638, 0x00000416, 0x40020000,
+ 0xd1012a00, 0x47702004, 0x461cb5ff, 0x4615b081, 0x2304460e, 0x98014622, 0xff7ff7ff, 0xd11a0007,
+ 0xd0172c00, 0x4478480d, 0x600e6801, 0x6800cd02, 0x490b6041, 0x71c82006, 0xf8caf000, 0x98014607,
+ 0x28006980, 0x4780d000, 0xd1032f00, 0x1d361f24, 0xd1e72c00, 0xb0054638, 0x0000bdf0, 0x000003be,
+ 0x40020000, 0x4604b510, 0xf7ff4608, 0x2800ff71, 0x2c00d106, 0x4904d005, 0x71c82044, 0xf8a8f000,
+ 0x2004bd10, 0x0000bd10, 0x40020000, 0xb081b5ff, 0x460e4614, 0x23044605, 0xff3ff7ff, 0xd12a2800,
+ 0x686868a9, 0xf8acf000, 0x42719000, 0x40014240, 0x42b7424f, 0x9800d101, 0x2c00183f, 0x1bbdd01a,
+ 0xd90042a5, 0x490d4625, 0x447908a8, 0x600e6809, 0x2201490b, 0x0a0271ca, 0x728872ca, 0x72489804,
+ 0xf876f000, 0xd1062800, 0x1b649800, 0x183f1976, 0xd1e42c00, 0xb0052000, 0x0000bdf0, 0x0000031a,
+ 0x40020000, 0xd00c2800, 0xd00a2a00, 0xd21a2908, 0x447b000b, 0x18db791b, 0x0705449f, 0x0d0b0907,
+ 0x2004110f, 0x68c04770, 0x6840e00a, 0x6880e008, 0x6800e006, 0x2001e004, 0x6900e002, 0x6940e000,
+ 0x20006010, 0x206a4770, 0x00004770, 0xd1012b00, 0x47702004, 0x461cb5f8, 0x460e4615, 0x9f082304,
+ 0xfedbf7ff, 0xd1192800, 0xd0172d00, 0x447a4a0f, 0x60066810, 0x2102480e, 0x990671c1, 0x681172c1,
+ 0x60886820, 0xf824f000, 0xd0082800, 0x29009907, 0x600ed000, 0xd0012f00, 0x60392100, 0x1d24bdf8,
+ 0x1d361f2d, 0xd1e12d00, 0x0000bdf8, 0x00000276, 0x40020000, 0xd1012800, 0x47702004, 0x4803b510,
+ 0x71c22240, 0xf0007181, 0xbd10f803, 0x40020000, 0x2170480a, 0x21807001, 0x78017001, 0xd5fc0609,
+ 0x06817800, 0x2067d501, 0x06c14770, 0x2068d501, 0x07c04770, 0x2069d0fc, 0x00004770, 0x40020000,
+ 0x09032200, 0xd373428b, 0x428b0a03, 0x0b03d358, 0xd33c428b, 0x428b0c03, 0xe012d321, 0x430b4603,
+ 0x2200d47f, 0x428b0843, 0x0903d374, 0xd35f428b, 0x428b0a03, 0x0b03d344, 0xd328428b, 0x428b0c03,
+ 0x22ffd30d, 0xba120209, 0x428b0c03, 0x1212d302, 0xd0650209, 0x428b0b03, 0xe000d319, 0x0bc30a09,
+ 0xd301428b, 0x1ac003cb, 0x0b834152, 0xd301428b, 0x1ac0038b, 0x0b434152, 0xd301428b, 0x1ac0034b,
+ 0x0b034152, 0xd301428b, 0x1ac0030b, 0x0ac34152, 0xd301428b, 0x1ac002cb, 0x0a834152, 0xd301428b,
+ 0x1ac0028b, 0x0a434152, 0xd301428b, 0x1ac0024b, 0x0a034152, 0xd301428b, 0x1ac0020b, 0xd2cd4152,
+ 0x428b09c3, 0x01cbd301, 0x41521ac0, 0x428b0983, 0x018bd301, 0x41521ac0, 0x428b0943, 0x014bd301,
+ 0x41521ac0, 0x428b0903, 0x010bd301, 0x41521ac0, 0x428b08c3, 0x00cbd301, 0x41521ac0, 0x428b0883,
+ 0x008bd301, 0x41521ac0, 0x428b0843, 0x004bd301, 0x41521ac0, 0xd2001a41, 0x41524601, 0x47704610,
+ 0x0fcae05d, 0x4249d000, 0xd3001003, 0x40534240, 0x469c2200, 0x428b0903, 0x0a03d32d, 0xd312428b,
+ 0x018922fc, 0x0a03ba12, 0xd30c428b, 0x11920189, 0xd308428b, 0x11920189, 0xd304428b, 0xd03a0189,
+ 0xe0001192, 0x09c30989, 0xd301428b, 0x1ac001cb, 0x09834152, 0xd301428b, 0x1ac0018b, 0x09434152,
+ 0xd301428b, 0x1ac0014b, 0x09034152, 0xd301428b, 0x1ac0010b, 0x08c34152, 0xd301428b, 0x1ac000cb,
+ 0x08834152, 0xd301428b, 0x1ac0008b, 0xd2d94152, 0x428b0843, 0x004bd301, 0x41521ac0, 0xd2001a41,
+ 0x46634601, 0x105b4152, 0xd3014610, 0x2b004240, 0x4249d500, 0x46634770, 0xd300105b, 0xb5014240,
+ 0x46c02000, 0xbd0246c0, 0x40020004, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000,
+ 0x00800000, 0x00000000, 0x00800000, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 2048},
+ };
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000039, // UnInit
+ 0x2000003D, // EraseChip
+ 0x20000065, // EraseSector
+ 0x20000097, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000000 + 0x00000001,
+ 0x20000000 + 0x00000020 + 0x0000060c,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(mkw41z4_flash_prog_blob), // prog_blob size
+ mkw41z4_flash_prog_blob, // address of prog_blob
+ 0x00000200 // ram_to_flash_bytes_to_be_written
+};
+
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/kw41z/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/kw41z/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the kw41z
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(512),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x1FFF8000,
+ .ram_regions[0].end = 0x20018000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/mimxrt1020_spi_flash/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/mimxrt1020_spi_flash/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,646 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t RT1020_S25LP064A_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x4605b570, 0x4616460c, 0xcc0fe002, 0x3e10c50f, 0xd2fa2e10, 0xd3022e08, 0xc503cc03, 0x2e043e08,
+ 0xcc01d307, 0x1f36c501, 0x7821e003, 0x1c647029, 0x1e761c6d, 0xbd70d2f9, 0x4770ba40, 0x4770ba40,
+ 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770bac0,
+ 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x4770bac0,
+ 0x4605b5fe, 0x460c4610, 0xd0734318, 0x468c46ae, 0x1aad2000, 0x419c4601, 0x4666d367, 0x24012700,
+ 0x1ab6463d, 0xd302419d, 0x463a4613, 0x46652421, 0x042f4676, 0x433e0c36, 0x1ab60c2d, 0xd304419d,
+ 0x041b0c15, 0x0412432b, 0x46653410, 0x062f4676, 0x433e0a36, 0x1ab60a2d, 0xd304419d, 0x021b0e15,
+ 0x0212432b, 0x46653408, 0x072f4676, 0x433e0936, 0x1ab6092d, 0xd304419d, 0x011b0f15, 0x0112432b,
+ 0x46651d24, 0x07af4676, 0x433e08b6, 0x1ab608ad, 0xd304419d, 0x009b0f95, 0x0092432b, 0x46651ca4,
+ 0x07ef4676, 0x433e0876, 0x1ab6086d, 0xd31a419d, 0x415b1892, 0xe0161c64, 0x46761800, 0x41494665,
+ 0x419d1ab7, 0x90009101, 0x4660d309, 0x41981ab1, 0x4684468e, 0x99019800, 0x1c402500, 0x07dd4169,
+ 0x432a0852, 0x1e64085b, 0x4672d5e6, 0xb0034663, 0xe7ffbdf0, 0x46012000, 0x46c046c0, 0x4623462a,
+ 0xb510e7f5, 0xf0002000, 0x46c0f907, 0x200146c0, 0xf8fcf000, 0x4603bd10, 0x430bb510, 0xd10f079b,
+ 0xd30d2a04, 0xc910c808, 0x42a31f12, 0xba18d0f8, 0x4288ba21, 0x2001d901, 0x2000bd10, 0xbd1043c0,
+ 0xd0032a00, 0xd00307d3, 0xe0071c52, 0xbd102000, 0x780c7803, 0x1c491c40, 0xd1071b1b, 0x780c7803,
+ 0x1c491c40, 0xd1011b1b, 0xd1f11e92, 0xbd104618, 0xc004e001, 0x29041f09, 0x078bd2fb, 0x8002d501,
+ 0x07c91c80, 0x7002d000, 0x29004770, 0x07c3d00b, 0x7002d002, 0x1e491c40, 0xd3042902, 0xd5020783,
+ 0x1c808002, 0xe7e31e89, 0xe7ee2200, 0xe7df2200, 0x09032200, 0xd32c428b, 0x428b0a03, 0x2300d311,
+ 0xe04e469c, 0x430b4603, 0x2200d43c, 0x428b0843, 0x0903d331, 0xd31c428b, 0x428b0a03, 0x4694d301,
+ 0x09c3e03f, 0xd301428b, 0x1ac001cb, 0x09834152, 0xd301428b, 0x1ac0018b, 0x09434152, 0xd301428b,
+ 0x1ac0014b, 0x09034152, 0xd301428b, 0x1ac0010b, 0x08c34152, 0xd301428b, 0x1ac000cb, 0x08834152,
+ 0xd301428b, 0x1ac0008b, 0x08434152, 0xd301428b, 0x1ac0004b, 0x1a414152, 0x4601d200, 0x46104152,
+ 0xe05d4770, 0xd0000fca, 0x10034249, 0x4240d300, 0x22004053, 0x0903469c, 0xd32d428b, 0x428b0a03,
+ 0x22fcd312, 0xba120189, 0x428b0a03, 0x0189d30c, 0x428b1192, 0x0189d308, 0x428b1192, 0x0189d304,
+ 0x1192d03a, 0x0989e000, 0x428b09c3, 0x01cbd301, 0x41521ac0, 0x428b0983, 0x018bd301, 0x41521ac0,
+ 0x428b0943, 0x014bd301, 0x41521ac0, 0x428b0903, 0x010bd301, 0x41521ac0, 0x428b08c3, 0x00cbd301,
+ 0x41521ac0, 0x428b0883, 0x008bd301, 0x41521ac0, 0x0843d2d9, 0xd301428b, 0x1ac0004b, 0x1a414152,
+ 0x4601d200, 0x41524663, 0x4610105b, 0x4240d301, 0xd5002b00, 0x47704249, 0x105b4663, 0x4240d300,
+ 0x2000b501, 0x46c046c0, 0x0000bd02, 0x20184901, 0xe7febeab, 0x00020026, 0xf000b510, 0xf000f80b,
+ 0xbd10f802, 0xb5104770, 0xd0012800, 0xffeef7ff, 0x0000bd10, 0x2100b510, 0xf000a002, 0x2001f813,
+ 0x0000bd10, 0x41474953, 0x3a545242, 0x6e624120, 0x616d726f, 0x6574206c, 0x6e696d72, 0x6f697461,
+ 0x0000006e, 0x4605b570, 0x200a460c, 0x1c6de000, 0xf812f000, 0xd0062d00, 0x28007828, 0xe002d1f7,
+ 0xf0001c64, 0x2c00f809, 0x7820d002, 0xd1f72800, 0xf000200a, 0xbd70f801, 0x4669b508, 0x20037008,
+ 0xbd08beab, 0x06c00a02, 0x0ec0b510, 0xd9012a06, 0xfea7f7ff, 0x00924b05, 0x681318d2, 0x40842403,
+ 0x408143a3, 0x6013430b, 0x0000bd10, 0x400fc068, 0x06c00a02, 0x0ec0b510, 0xd9012a06, 0xfe91f7ff,
+ 0x00924b05, 0x681318d2, 0x40842403, 0x408143a3, 0x6013430b, 0x0000bd10, 0x400fc068, 0x49022001,
+ 0x63080300, 0x00004770, 0x400d8040, 0x49022001, 0x62080300, 0x00004770, 0x400d80c0, 0x49022001,
+ 0x61480780, 0x00004770, 0x400d8140, 0x6b014802, 0x00490849, 0x47706301, 0x400d8240, 0x680a4903,
+ 0x208000c3, 0x43024098, 0x4770600a, 0x400d8100, 0x49022001, 0x63080300, 0x00004770, 0x400d8000,
+ 0x6b0a4903, 0x208000c3, 0x43024098, 0x4770630a, 0x400d80c0, 0x20004901, 0x47706108, 0x400d8000,
+ 0x20004904, 0x48046108, 0x04826b01, 0x63014311, 0x00004770, 0x400d8000, 0x400d9000, 0x480eb508,
+ 0x22036801, 0x60014311, 0x6801480c, 0x43112202, 0x20006001, 0x480a9000, 0x9900bf00, 0x91001c49,
+ 0xd3f94281, 0x6a084907, 0x0212221f, 0x4a064390, 0x62084310, 0xbd082001, 0x400fc080, 0x402e0140,
+ 0x00061a80, 0x400d8100, 0x00001701, 0x2200b508, 0x92004668, 0xfa7af000, 0x6b014808, 0x08490049,
+ 0x6b016301, 0x43990483, 0x60026301, 0x22636b01, 0x43110392, 0x20016301, 0x0000bd08, 0x400d9000,
+ 0x4c34b510, 0xf0010003, 0x0d17f843, 0x362a120d, 0x3e3c6339, 0x63444240, 0x4e4c4a48, 0x59565450,
+ 0x00635f5c, 0xf870f000, 0x0a896961, 0x6960e011, 0xd50a0640, 0x06006960, 0x2001d503, 0xf966f000,
+ 0x2002e005, 0xf93cf000, 0xf000e001, 0x6961f85d, 0x07490c09, 0x1c490f49, 0xfe1af7ff, 0xf000bd10,
+ 0x6961f853, 0x0f4904c9, 0xf7ff1c49, 0x6961fe11, 0x0f890589, 0xf000e7ef, 0xbd10f837, 0x03c02001,
+ 0x4815bd10, 0x2000e021, 0x2001e004, 0x2002e002, 0x2003e000, 0xf93af000, 0x4810bd10, 0x2000e015,
+ 0x2001e004, 0x2002e002, 0x2003e000, 0xf908f000, 0x480bbd10, 0x480ae009, 0xe0061dc0, 0x30084808,
+ 0x4807e003, 0xe0003009, 0xf0004806, 0xbd10f85f, 0xbd102000, 0x400fc000, 0x0010000d, 0x0030000d,
+ 0x00e0000d, 0x0070000d, 0x6b004804, 0xd50106c0, 0x47704803, 0x44484803, 0x47706800, 0x400d8240,
+ 0x016e3600, 0x00000050, 0x4c1cb510, 0x01816960, 0x69a1481b, 0x1202d517, 0xd00d4011, 0x03122201,
+ 0xd00d1a89, 0xd0084291, 0x69612000, 0x0f490089, 0xf7ff1c49, 0xbd10fdad, 0xf0004812, 0xe7f4f827,
+ 0xffd2f7ff, 0x2203e7f1, 0x40110492, 0x2201d00b, 0x1a880492, 0x1a80d00a, 0x4290d00c, 0x480ad101,
+ 0x2000bd10, 0xf000bd10, 0xbd10f811, 0xf0002003, 0xbd10f8a7, 0xf0002003, 0xbd10f8c9, 0x400fc000,
+ 0x0030000d, 0x0010000d, 0x1dcd6500, 0x4605b5f0, 0xb0854843, 0xc80f4478, 0xc40f466c, 0x01284e41,
+ 0x59f00d07, 0x0ed206ea, 0x40912101, 0xd00a4008, 0x040059f0, 0xd0080f80, 0x46042000, 0x03c059f0,
+ 0xd0050fc0, 0xb0054620, 0xf7ffbdf0, 0xe7f4ff8d, 0x4b344935, 0x33c01a68, 0x428d466a, 0xdc31d056,
+ 0x18284832, 0x2101d046, 0x4f310549, 0xd02f1a40, 0x42880049, 0x6b38d12a, 0x0646492d, 0x31400e76,
+ 0x4620690d, 0xf0006809, 0x462aff2b, 0xf7ff2300, 0x4374fc67, 0x18206b39, 0x04d22203, 0xd0314011,
+ 0x04d22201, 0xd1004291, 0x49220840, 0x4a226b09, 0x22014011, 0x1a8903d2, 0x0212d026, 0xd1c24291,
+ 0xe7c00880, 0xd0232807, 0xd0272808, 0xe7ba2000, 0x46206a3d, 0xf0006939, 0x462aff03, 0xf7ff2300,
+ 0x6b31fc3f, 0xd00107c9, 0xe0002116, 0x434c2114, 0xe7a81820, 0x07806930, 0x2016d001, 0x2014e000,
+ 0xe7a04360, 0xe7d00880, 0xe79c0840, 0xe0016a18, 0x08806a18, 0x0f000780, 0xe7945810, 0xe7924807,
+ 0x00003f40, 0x400d8000, 0x00e0000d, 0xffeffff3, 0x400d8040, 0x400d8140, 0x00808000, 0x017d7840,
+ 0x4604b510, 0xf7ff480f, 0x490fff61, 0xd0092c00, 0xd0092c01, 0xd00e2c02, 0xd00f2c03, 0x21122000,
+ 0xbd104348, 0xe0016809, 0x0a096809, 0x0e890689, 0xfccef7ff, 0x6809e7f3, 0xe7f70c09, 0x0e096809,
+ 0x0000e7f4, 0x0030000d, 0x400d8100, 0x4604b510, 0xf7ff480f, 0x490fff3b, 0xd0092c00, 0xd0092c01,
+ 0xd00e2c02, 0xd00f2c03, 0x21122000, 0xbd104348, 0xe0016b09, 0x0a096b09, 0x0e890689, 0xfca8f7ff,
+ 0x6b09e7f3, 0xe7f70c09, 0x0e096b09, 0x0000e7f4, 0x0010000d, 0x400d80c0, 0x6841b530, 0x008b2200,
+ 0x089b4918, 0x6883600b, 0x089b009b, 0x7801610b, 0x06492301, 0x0e49035b, 0x18c97840, 0x2802019d,
+ 0x4b11d01d, 0x2804006c, 0x2808d017, 0x2810d013, 0x4321d00f, 0x33c04b0b, 0x4c0b6b18, 0x402043e4,
+ 0x63184310, 0x38404807, 0x6b016301, 0xdafc2900, 0x461abd30, 0x4329e7ee, 0x4321e7fb, 0x4329e7f9,
+ 0x0000e7e8, 0x400d8080, 0x00808000, 0x79027941, 0x07920789, 0x0f920f09, 0x78024311, 0xd0022a00,
+ 0x03522201, 0x78424311, 0xd0022a00, 0x05122201, 0x78824311, 0xd0022a00, 0x05522201, 0x78c04311,
+ 0xd0022800, 0x05802001, 0x48034301, 0x6a016201, 0xdafc2900, 0x00004770, 0x400d80c0, 0x2800b510,
+ 0xf7ffd001, 0x2101fbde, 0x07894807, 0x49076181, 0x03d26b0a, 0x2201d5fc, 0x61420412, 0x04096901,
+ 0x6182d5fc, 0x0000bd10, 0x400d8140, 0x400d8240, 0x6b014802, 0x43112201, 0x47706301, 0x400d8240,
+ 0x4b08b510, 0x00c0681a, 0x408424bf, 0x248043a2, 0x43144084, 0x0689601c, 0x40810e89, 0x60194311,
+ 0x0000bd10, 0x400d8100, 0x21017800, 0x0fc007c0, 0x18410349, 0x63014802, 0x29006b01, 0x4770dafc,
+ 0x400d8000, 0x4b08b510, 0x00c06b1a, 0x408424bf, 0x248043a2, 0x43144084, 0x0689631c, 0x40810e89,
+ 0x63194311, 0x0000bd10, 0x400d80c0, 0x21c17800, 0x0f800780, 0x18410189, 0x61014802, 0x29006901,
+ 0x4770dafc, 0x400d8000, 0x49032210, 0xd0012800, 0x4770638a, 0x4770634a, 0x400d8240, 0xb5104906,
+ 0x22002301, 0x444904db, 0xf0014610, 0x4803fd98, 0x68404448, 0x0000bd10, 0x0000005c, 0x00000004,
+ 0x49050102, 0x0912b510, 0x20004449, 0xfea2f001, 0x44494902, 0xbd106048, 0x0000005c, 0x00000004,
+ 0xf3bfb57c, 0xf3bf8f4f, 0x48188f6f, 0x22016a41, 0x43910412, 0x48156241, 0x69413080, 0x00490849,
+ 0x49136141, 0x62881740, 0x630862c8, 0x63886348, 0x490f63c8, 0x60083140, 0xfd98f000, 0xf926f003,
+ 0x2500480c, 0x9000490c, 0x4449466a, 0x46289501, 0xfd20f002, 0x49084c09, 0x6060444c, 0x20004449,
+ 0xfec2f001, 0x70256060, 0x0000bd7c, 0xe000ed00, 0x400fc040, 0xc0000005, 0x0000005c, 0x00000004,
+ 0xb5104805, 0x68414448, 0xd0032900, 0xf0004803, 0xbd10f96f, 0xfb05f7ff, 0x0000025c, 0x40184000,
+ 0xf7ffb510, 0xbd10ffed, 0xb5104805, 0x68814448, 0xd0032900, 0xf0004803, 0xbd10f95b, 0xfaf1f7ff,
+ 0x0000025c, 0x40188000, 0xf7ffb510, 0xbd10ffed, 0xb5104805, 0x68c14448, 0xd0032900, 0xf0004803,
+ 0xbd10f947, 0xfaddf7ff, 0x0000025c, 0x4018c000, 0xf7ffb510, 0xbd10ffed, 0xb5104805, 0x69014448,
+ 0xd0032900, 0xf0004803, 0xbd10f933, 0xfac9f7ff, 0x0000025c, 0x40190000, 0xf7ffb510, 0xbd10ffed,
+ 0xb5104805, 0x69414448, 0xd0032900, 0xf0004803, 0xbd10f91f, 0xfab5f7ff, 0x0000025c, 0x40194000,
+ 0xf7ffb510, 0xbd10ffed, 0x460cb510, 0x29006989, 0x2141d103, 0xf0000549, 0x2000f887, 0x20026120,
+ 0x73603420, 0xb510bd10, 0x2103460c, 0xf0000589, 0x2000f87b, 0x34206060, 0xbd107320, 0x460bb510,
+ 0x079a6a81, 0x00890889, 0x430a0f92, 0x69416282, 0x00490fda, 0x07d20849, 0x490b430a, 0x400a4c0a,
+ 0x43e44619, 0x43114021, 0x03a42401, 0x43a1461a, 0x430a4022, 0x43116941, 0xf0006141, 0x4018f8d1,
+ 0x4802d000, 0x0000bd10, 0xbfe0ffff, 0x0000051a, 0x461eb5f8, 0x000c4617, 0xd0264605, 0x46202130,
+ 0xfab4f7ff, 0x46202102, 0x73413020, 0x73012100, 0x62a66267, 0x21106ae8, 0x62e84388, 0xf0004628,
+ 0x4a0bf871, 0x444a0081, 0x490a5054, 0x44790040, 0x28005e08, 0x06c2db08, 0x21010ed2, 0x09404091,
+ 0x00804a05, 0x60011880, 0xf7ffbdf8, 0x0000fa3a, 0x0000025c, 0x00003962, 0xe000e100, 0x6ac1b510,
+ 0x0f490549, 0x6941d1fb, 0xd5fc0249, 0x61812100, 0xf848f000, 0x00404903, 0x5e084479, 0xf7ff2100,
+ 0xbd10fb87, 0x0000392a, 0x23c06902, 0x021b400b, 0x6102439a, 0x078b6a82, 0x439a0d9b, 0x0a096282,
+ 0x02096982, 0x6182438a, 0x69024770, 0x400b23c0, 0x431a021b, 0x6a826102, 0x0d9b078b, 0x6282431a,
+ 0x69820a09, 0x430a0209, 0x47706182, 0x2800b510, 0x21e1d00a, 0x60010249, 0x71012100, 0x71817141,
+ 0x720171c1, 0xbd107241, 0xf9ebf7ff, 0x22c06901, 0x40110a09, 0x69806a82, 0x0f920592, 0x4310430a,
+ 0x00004770, 0xb5104a08, 0x20004601, 0x0083447a, 0x428b58d3, 0x1c40d003, 0xd3f82808, 0x2808e001,
+ 0xf7ffd301, 0xbd10f9ce, 0x00003860, 0x5c40202d, 0xd0072802, 0xd0072a00, 0x69096948, 0x60101a40,
+ 0x47702000, 0x47702006, 0x47702004, 0x8c0a8c48, 0x8c084290, 0x69cad901, 0x8c491880, 0x47701a40,
+ 0x5c40202c, 0xd0072800, 0xd0072a00, 0x68496888, 0x60101a40, 0x47702000, 0x47702006, 0x47702004,
+ 0x6a806941, 0x0c0022c3, 0x43084010, 0x47704770, 0x4605b5f8, 0x460c6940, 0xd50d0300, 0x466969e8,
+ 0x78087008, 0x70081c40, 0x2e006a66, 0x4a5ed004, 0x46284621, 0x47b06aa3, 0x02816968, 0x30204620,
+ 0x29009000, 0x69a8da71, 0xd56e0280, 0x01406ae8, 0xe0260f46, 0x42b06920, 0x6920d201, 0x4630e000,
+ 0xb2c168e2, 0xe0022000, 0x541369eb, 0x460b1c40, 0xd3f94288, 0x184068e0, 0x692060e0, 0x61201a40,
+ 0xb2c61af0, 0x28006920, 0x9800d10b, 0x73412102, 0x2f006a67, 0x4a44d005, 0x1f924621, 0x6aa34628,
+ 0x2e0047b8, 0x6920d002, 0xd1d32800, 0x280069a0, 0xe032d12d, 0x46284621, 0xf926f000, 0xd0082800,
+ 0x2f006a67, 0x4a38d005, 0x1e524621, 0x6aa34628, 0x462147b8, 0xf0004628, 0x2800f917, 0x8c60d009,
+ 0x1c4069e1, 0xd1014288, 0xe0012000, 0x1c408c60, 0x69e88460, 0x69a18c22, 0x8c205488, 0x1c4069e1,
+ 0xd1014288, 0xe0012000, 0x1c408c20, 0x46308420, 0xb2f61e76, 0xd1cd2800, 0x6920e007, 0xd1042800,
+ 0x05492141, 0xf7ff4628, 0x6968feef, 0xd5390200, 0x020069a8, 0x6ae8d536, 0x05402104, 0x1a080f40,
+ 0xe02ab2c6, 0x42b06860, 0x6860d201, 0x4630e000, 0xb2c16822, 0xe0022000, 0x61eb5c13, 0x460b1c40,
+ 0xd3f94288, 0x18406820, 0x68606020, 0x60601a40, 0xb2c61af0, 0x28006860, 0x9900d10f, 0x69a87308,
+ 0x05c92101, 0x61a84388, 0x2f006a67, 0x4a06d005, 0x1fd24621, 0x6aa34628, 0x2e0047b8, 0x6860d002,
+ 0xd1cf2800, 0x0000bdf8, 0x0000051d, 0xb086b5f7, 0x4604000f, 0x6838d009, 0x28009005, 0x79b8d005,
+ 0xd8022804, 0x280479f8, 0xf7ffd901, 0x9805f8ba, 0x20009000, 0x25049001, 0x99059002, 0x43699808,
+ 0xf906f7ff, 0x0c360406, 0x2601d100, 0x43714629, 0xf7ff9808, 0x9905f8fd, 0x1c701a41, 0x46299103,
+ 0x43419004, 0xf7ff9808, 0x9905f8f3, 0x99031a08, 0xd2024288, 0x98049003, 0x9900b286, 0x42889803,
+ 0x4669d801, 0x1c6dc161, 0xd9d62d20, 0x98052164, 0xf8def7ff, 0x18410041, 0x42819800, 0x4830d202,
+ 0xbdf0b009, 0xf7ff4620, 0x0041fe9d, 0x4478482d, 0x21035e40, 0xf9dcf7ff, 0x210369a0, 0x43880489,
+ 0x692061a0, 0x1f099901, 0xd2022904, 0x04492101, 0x211f4308, 0x43880609, 0x1e499901, 0x08c906c9,
+ 0x0b484301, 0x03409902, 0x0cc904c9, 0x61214301, 0x21016920, 0x43880749, 0x69a06120, 0x43882110,
+ 0x69a061a0, 0x00800880, 0x69a061a0, 0x43087939, 0x692061a0, 0x03492101, 0x79794388, 0x0c8907c9,
+ 0x61214301, 0x79b979f8, 0x43080400, 0x6aa062e0, 0x43082188, 0x6aa062a0, 0x03892103, 0x62a04308,
+ 0x7a3969a0, 0xd0022900, 0x04c92101, 0x7a794308, 0xd0022900, 0x04892101, 0x61a04308, 0xe79f2000,
+ 0x00000521, 0x000035d4, 0x460cb510, 0xfe5ef7ff, 0x1e4969e1, 0xd1014288, 0xbd102001, 0xbd102000,
+ 0x6ac3e006, 0x0f5b015b, 0x69c3d0fb, 0x1c49700b, 0xd2f61e52, 0x00004770, 0x460cb5ff, 0x3120b083,
+ 0x7b499100, 0x29034617, 0x69a1d013, 0x687d2600, 0xd0322900, 0x8110f3ef, 0xb6729101, 0xf7ff4621,
+ 0x2800fe35, 0x4285d01b, 0x4628d200, 0x21001a2d, 0x481ae013, 0xbdf0b007, 0x69a28c63, 0x683b5cd2,
+ 0x8c62559a, 0x1c5269e3, 0x429a1c76, 0x2200d101, 0x8c62e001, 0x84621c52, 0x42811c49, 0x2d00d3ec,
+ 0x6838d007, 0x60e01980, 0x61656125, 0x21039800, 0x98017341, 0x8810f380, 0x6811e00a, 0x612560e1,
+ 0x9a006165, 0x73512103, 0x05492141, 0xfdadf7ff, 0x28009806, 0x6006d000, 0xe7cb2000, 0x00000515,
+ 0x460bb510, 0x7b1c3320, 0xd00c2c01, 0x600c6814, 0x604c6854, 0x608a6852, 0x73192101, 0xf7ff05c9,
+ 0x2000fd94, 0x4801bd10, 0x0000bd10, 0x00000514, 0xb084b5f7, 0xd00d000f, 0x90012000, 0x97002404,
+ 0x46399002, 0x98064361, 0xffe2f7fe, 0x0c2d0405, 0xe002d002, 0xff85f7fe, 0x46212501, 0x98064369,
+ 0xffd6f7fe, 0x1c681bc6, 0x43414621, 0x98069003, 0xffcef7fe, 0x42b01a38, 0x4606d202, 0xb2859803,
+ 0x42869800, 0x9600d802, 0x94019502, 0x2c201c64, 0x2164d9d7, 0xf7fe4638, 0x0041ffbb, 0x98001841,
+ 0xd9254281, 0x69819804, 0x22036980, 0x43900492, 0x61909a04, 0x69009804, 0x1f129a01, 0xd2022a04,
+ 0x04522201, 0x221f4310, 0x43900612, 0x1e529a01, 0x08d206d2, 0x0b504302, 0x03409a02, 0x0cd204d2,
+ 0x98044302, 0x98046102, 0x20006181, 0xbdf0b007, 0xe7fb4800, 0x00000521, 0x2900b510, 0x2a00d00b,
+ 0x61cbd008, 0x2200618a, 0x844a840a, 0x05492141, 0xfd1bf7ff, 0xf7febd10, 0xb510ff24, 0xd004000c,
+ 0x5d09212d, 0xd0022902, 0xf7fee005, 0x2141ff1a, 0xf7ff0549, 0x2000fcf9, 0x61e061a0, 0x84608420,
+ 0xe005bd10, 0x021b6943, 0x780bd5fc, 0x1c4961c3, 0xd2f71e52, 0x00004770, 0x0105b5f7, 0x98024c22,
+ 0x444c092d, 0x2001d007, 0x42850340, 0x7820d132, 0xd0072800, 0x6800e02e, 0x4288491c, 0x2001d12a,
+ 0xe0277020, 0x22004e1a, 0x4631444e, 0xf0014610, 0x2701fa31, 0x6060033f, 0x4631463a, 0xf0012000,
+ 0x2200fa29, 0x46336060, 0x46104631, 0xfa91f001, 0x60601df3, 0x113a33f9, 0x20004631, 0xfa89f001,
+ 0x60604b09, 0x3308444b, 0x4631463a, 0xf0012000, 0x6060fa80, 0x462a4906, 0x20004449, 0xf0019b02,
+ 0x6060fa78, 0x0000bdfe, 0x00000004, 0x42464346, 0x0000005c, 0x4c35b5f8, 0x49356960, 0x01804f35,
+ 0x69a0d51b, 0x03122203, 0xd0054010, 0x03122201, 0xd00d4290, 0xe00c2000, 0x07c068e0, 0x6938d008,
+ 0xd0010780, 0xe0002016, 0x49292014, 0xe0004348, 0x69614608, 0x0f490089, 0x6b38e029, 0xd00107c0,
+ 0xe0002516, 0x48222514, 0x48224345, 0x6a063040, 0xf0006900, 0x4632f8c5, 0xf7fe2300, 0x6939fe01,
+ 0x07891940, 0x0f894a1a, 0x084a4351, 0x230369a1, 0x4019049b, 0x2301d010, 0x1ac9049b, 0x1ac8d016,
+ 0x4298d019, 0x6920d107, 0x48130741, 0x1c490f49, 0xfebef7fe, 0x2000e000, 0x04c96961, 0x1c490f49,
+ 0xfeb6f7fe, 0x4449490d, 0xbdf86008, 0x6809490c, 0x0e890089, 0x480ae005, 0x6b003840, 0x0e810080,
+ 0xf7fe4610, 0x2112fea5, 0xe7e54348, 0x400fc000, 0x016e3600, 0x400d8000, 0x1dcd6500, 0x00000058,
+ 0x400d8100, 0x482db570, 0x074a8801, 0x2a002104, 0x8802da02, 0x8002438a, 0x88024829, 0xd5020752,
+ 0x438a8802, 0x48288002, 0x60414926, 0x60814927, 0x22806801, 0x22204391, 0x60014311, 0x69014824,
+ 0xd00307c9, 0x08496901, 0x61010049, 0x8f4ff3bf, 0x8f6ff3bf, 0x21004d1f, 0xf3bf6129, 0xf3bf8f4f,
+ 0x4c1d8f6f, 0x22016960, 0x43100452, 0xf3bf6160, 0xf3bf8f4f, 0x48188f6f, 0x60413080, 0x8f4ff3bf,
+ 0x01016800, 0x04c00c49, 0x05ca0d83, 0x0c964618, 0x43320782, 0x1e40622a, 0x1e49d2fa, 0xf3bfd2f5,
+ 0x69608f4f, 0x04092101, 0x61604308, 0x8f4ff3bf, 0x8f6ff3bf, 0xf812f000, 0x0000bd70, 0x400b8000,
+ 0x400d0000, 0xd928c520, 0x400bc000, 0x0000ffff, 0xe000e000, 0xe000ef40, 0xe000ed00, 0x20004770,
+ 0xb5704770, 0x460d4613, 0x4604460a, 0x46184601, 0xfdd1f7fe, 0xd0012800, 0xbd702000, 0xbd701960,
+ 0x0c04b5f8, 0x4626b28b, 0x435eb282, 0x46100c0d, 0x43580c37, 0x19800436, 0x41792100, 0x436e4616,
+ 0x04360c37, 0x41791980, 0x436e4626, 0xbdf81989, 0x4674b430, 0x78251e64, 0x42ab1c64, 0x461dd200,
+ 0x005b5d63, 0xbc3018e3, 0x00004718, 0x4959b5f8, 0x44494857, 0x49586008, 0x24016b08, 0x0f800240,
+ 0x6a084084, 0x07404e55, 0x6b300fc5, 0xd57d03c0, 0x21016b30, 0x43880309, 0x6b306330, 0xdafc2800,
+ 0x21016b30, 0x43080409, 0x4a4d6330, 0x4f4d6810, 0x40382303, 0x18c002db, 0x43184b4b, 0x20036010,
+ 0x61300300, 0x28006930, 0x6930dafc, 0x04092101, 0x61304388, 0x38404842, 0x22236b01, 0x02124039,
+ 0x4a421889, 0x63014311, 0xd0032d00, 0x2c080064, 0x2408d900, 0xd0062d00, 0x4621483d, 0xfda8f7fe,
+ 0x90002701, 0x483be002, 0x1c7fe7f7, 0x98004639, 0xfd9ef7fe, 0x42884938, 0x4838d8f7, 0x4a386941,
+ 0x40112307, 0x07521e7a, 0x43110b52, 0x029b02a2, 0x04d218d2, 0x43110cd2, 0x3aff023a, 0x05923a01,
+ 0x43110d92, 0x6a416141, 0x01c909c9, 0x62411cc9, 0x04892103, 0x2d006982, 0x438ad002, 0xe0046182,
+ 0x2101438a, 0x185104c9, 0x69816181, 0x40114a25, 0x06922203, 0x61811889, 0x4a2369c1, 0x22034011,
+ 0x18890752, 0x43114a21, 0xe00061c1, 0x69c1e014, 0x04122203, 0x61c14311, 0x22e76a41, 0x439102d2,
+ 0x02d22221, 0x62411889, 0x20016b31, 0x43810400, 0x69316331, 0x61314381, 0xd0072d00, 0x4621480c,
+ 0xfd46f7fe, 0x44494912, 0xbdf86008, 0xe7f64809, 0x016e3600, 0x00000050, 0x401f4440, 0x400d8000,
+ 0x400d8100, 0xc0c0c0c0, 0x18131818, 0x0f1a2323, 0x1f78a400, 0x179a7b00, 0x08954400, 0x400fc000,
+ 0xfff8e0ff, 0xe3ffffcf, 0x9c7fff80, 0x03800001, 0x00000058, 0x2800b510, 0xf7ffd101, 0xbd10ff27,
+ 0xb5104770, 0x02402003, 0xf7fe2100, 0xbd10fe0b, 0xb5f74770, 0x4616b082, 0xd051000d, 0xd84f2e01,
+ 0x34ff462c, 0x7a2034c1, 0xd0002800, 0x28002001, 0x6c28d046, 0x0fc70640, 0xf0029802, 0x2e00f94f,
+ 0x7a20d02b, 0xd0092800, 0x5d412046, 0x9802463a, 0xf852f000, 0x98024629, 0xfa74f000, 0x28007ba0,
+ 0x2100d003, 0xf0009802, 0x466afcdf, 0x98022102, 0xfc70f000, 0xd0022f00, 0x08409800, 0xaa019000,
+ 0x98022100, 0xfc66f000, 0x98019900, 0xfcd0f7fe, 0x1c40210a, 0x08804348, 0x7a21e010, 0xd0072900,
+ 0x9802463a, 0xf828f000, 0x98024629, 0xfa4af000, 0x28007ba0, 0x2101d0d9, 0xbf00e7d4, 0xd2fc1e40,
+ 0xbdf0b005, 0xf000b510, 0x2800fc83, 0xf002d001, 0xbd10f8ca, 0xf000b510, 0x2800fc7b, 0x2100d00b,
+ 0x07db2301, 0x1812008a, 0x68143280, 0x6014431c, 0x29041c49, 0xbd10d3f6, 0x460cb5f7, 0xb08a4927,
+ 0x22144615, 0x46684479, 0xfb7af7fe, 0x22144923, 0x31084479, 0xf7fea805, 0x2d00fb73, 0x2d01d001,
+ 0x4e1fd137, 0x09876b30, 0x01bf481e, 0x200769c2, 0x438205c0, 0xd02e2d00, 0x2c00a805, 0x2c09d029,
+ 0x2401d900, 0x5c430061, 0x78401808, 0x05c02107, 0x069b05c9, 0x0e9b1840, 0x4d130184, 0x09a4433b,
+ 0x43146828, 0x43382702, 0x980a6028, 0xf81ef000, 0x42986b30, 0x6333d000, 0x69c1480a, 0xd00042a1,
+ 0x980a61c4, 0xf81ef000, 0x43b86828, 0xf3bf6028, 0xb00d8f6f, 0x4668bdf0, 0x0000e7cf, 0x00002c1c,
+ 0x400d80c0, 0x400fc000, 0x402a8000, 0x68014804, 0x02922203, 0x60014391, 0x8f6ff3bf, 0x00004770,
+ 0x400fc080, 0x68014804, 0x02922203, 0x60014311, 0x8f6ff3bf, 0x00004770, 0x400fc080, 0x4605b5fe,
+ 0x90002004, 0x4628460e, 0xfbf2f000, 0xd07d0004, 0xd0fc2e00, 0x28037830, 0x7c30d878, 0x27009001,
+ 0xf0024620, 0x4628f875, 0xff64f7ff, 0x211e6960, 0x61604308, 0x35804625, 0x62286870, 0x28027830,
+ 0x2803d002, 0xe003d002, 0xe0008b30, 0xb2878c30, 0x7a307b31, 0x07001e49, 0x0b000749, 0x43080949,
+ 0x07c99901, 0x43384308, 0x78306268, 0xd14b2803, 0x6a3269f0, 0xd1490783, 0x211c2340, 0x63a9469e,
+ 0x21016bab, 0x63ab430b, 0x07db6bab, 0x6b2bd1fc, 0x632b430b, 0x1de1e036, 0x467331f9, 0xd30f4572,
+ 0x089b6967, 0xd40206bf, 0xc980e029, 0x1e5bc080, 0x4671d2fb, 0x69611a52, 0x43192320, 0xe01e6161,
+ 0x061b6f2b, 0x42930d5b, 0xe018d203, 0x1f12c908, 0x2a04c008, 0x2a00d2fa, 0x6809d010, 0xa9019101,
+ 0x4601468c, 0xe0072300, 0x783f4667, 0x4667700f, 0x1c491c7f, 0x1c5b46bc, 0xd3f54293, 0x69612200,
+ 0xd4010709, 0xd1c62a00, 0xe0007830, 0x2802e058, 0x2801d001, 0x6971d13d, 0x078869b2, 0x2040d150,
+ 0x201c4684, 0x6be863e8, 0x43182301, 0x6be863e8, 0xd1fc07c0, 0xe02a4686, 0x30ff4620, 0x30816963,
+ 0xd521065b, 0x089b4663, 0xd2024562, 0xc980e00e, 0x1e5bc080, 0x4660d2fb, 0xe0091a12, 0xdd032a00,
+ 0xc080c980, 0xe0011f12, 0xc0802700, 0xd2f51e5b, 0x28004670, 0x6b28d104, 0x43182301, 0x469e6328,
+ 0x23406960, 0x61604318, 0x07006960, 0x2a00d401, 0x7830dcd2, 0xd1032800, 0x21016b28, 0x63284308,
+ 0xf0014620, 0x6960ffb5, 0xd50b0700, 0x01006e68, 0x280e0f00, 0x4804d001, 0x4803e001, 0x90001e40,
+ 0xbdfe9800, 0xe7fa2000, 0x00001771, 0xb5104602, 0x2a002004, 0x2900d021, 0x2044d01f, 0x28015c40,
+ 0x68d0d10c, 0x005b0843, 0x43032040, 0xf0004608, 0x2800fcdd, 0x2001d001, 0x60d34303, 0x212068d0,
+ 0x60d04308, 0x20004b05, 0x18890081, 0x401c6a0c, 0x1c40620c, 0xd3f72803, 0xbd102000, 0xfcf0ff00,
+ 0xb087b5f3, 0x90002000, 0x2504460c, 0xf0009807, 0x9003fadf, 0xd0542800, 0xd0522c00, 0x30404620,
+ 0x90054627, 0x26003750, 0x304130ff, 0x68389002, 0x0a8100b2, 0x18109803, 0x66019001, 0x1d3f7ba0,
+ 0x7b6006c5, 0x06c00eed, 0x43050d80, 0x07007be0, 0x43050c40, 0xf0004620, 0x2800fca0, 0x2001d002,
+ 0x43050280, 0x28006f60, 0xaa04d00d, 0x98072102, 0xfa70f000, 0x6f612301, 0x9a044668, 0xfab2f000,
+ 0x04009800, 0x98014305, 0x98056705, 0x280079c0, 0x9802d00e, 0x07417c00, 0x9902d00a, 0x7c492207,
+ 0x07090340, 0x03520d09, 0xb2801880, 0xe0014308, 0x02002009, 0x31809901, 0x1c766008, 0xd3b62e04,
+ 0x46282500, 0xbdf0b009, 0xb085b5f0, 0x460e4d1b, 0x95004607, 0xf0009501, 0x0004fa7b, 0x2e00d02b,
+ 0xaa02d029, 0x46382102, 0xfa34f000, 0x2101aa03, 0xf0004638, 0x2601fa2f, 0x02b64f11, 0x46394633,
+ 0x9a024668, 0xfa6ef000, 0x46394633, 0x9a03a801, 0xfa68f000, 0x42a89800, 0x9500d900, 0x42a89801,
+ 0x9501d900, 0x99019800, 0xb2890400, 0x60604308, 0xb0052000, 0x2004bdf0, 0x0000e7fb, 0x0000ffff,
+ 0x1dcd6500, 0xb085b5f3, 0x2404460e, 0xf0009805, 0x0005fa3f, 0x2e00d07e, 0x7b30d07c, 0xd8792803,
+ 0xd00a2800, 0xd0082801, 0xd0062802, 0xd1042803, 0xf0004630, 0x2800fbf1, 0x20ffd002, 0xe00c3001,
+ 0x2102aa03, 0xf0009805, 0x4938f9e5, 0x42889803, 0x6c30d306, 0xd4030600, 0x90002079, 0xe0219001,
+ 0x00602400, 0x31601981, 0x7e0f7e48, 0xd10b2800, 0x43472064, 0x214bd01d, 0xf7fe4638, 0x214bfa39,
+ 0x42b94341, 0x1c40d200, 0x283f213f, 0x4608d900, 0x0c400680, 0x30ff00a2, 0x46693001, 0x50881c64,
+ 0xd3de2c02, 0x22026828, 0x28000780, 0x2000da1c, 0x4630e01e, 0xfbb7f000, 0x46024607, 0x9805a902,
+ 0xf9daf000, 0x9902481a, 0xd0092f00, 0xfa10f7fe, 0x217d0880, 0x434800c9, 0xf7fe214b, 0xe7d2fa09,
+ 0xfa06f7fe, 0xe7f40840, 0x20016829, 0x60294311, 0x29006d31, 0x6d71d102, 0xd0022900, 0x9b0021c0,
+ 0x6db1514b, 0xd1022900, 0x29006df1, 0x21c4d004, 0xe0009b01, 0x514be006, 0xd0022800, 0x43906828,
+ 0x24006028, 0xb0074620, 0x0000bdf0, 0x05f5e100, 0x3b9aca00, 0xb08ab5f7, 0x2604460d, 0xf000980a,
+ 0x0007f9a7, 0x2d00d054, 0x2001d052, 0x70084669, 0x9001980c, 0x74082000, 0x24002004, 0x00a09006,
+ 0x46101942, 0x78413020, 0xd03e2900, 0x025b2301, 0x059b59db, 0xd0030f9b, 0x7f5b192b, 0xd0342b02,
+ 0x78009102, 0x92053230, 0x22009003, 0x9b0c4629, 0xf000980a, 0x2800f911, 0x9802d12b, 0x01002101,
+ 0x32801942, 0x980a9b03, 0xfdc6f001, 0x90022001, 0x980a4669, 0xfd72f7ff, 0xd11a0006, 0x28008a68,
+ 0x1929d10e, 0x29027f49, 0x2903d00a, 0x2200d008, 0x9b0c4629, 0xf000980a, 0x0006f80f, 0xe004d109,
+ 0x43482164, 0xf0012100, 0x1c64fd8c, 0xd3b62c03, 0xb00d4630, 0x0000bdf0, 0x2004b5ff, 0x460db091,
+ 0x2900900e, 0x4628d079, 0x8f823040, 0x460c2101, 0x8fc24094, 0x92009302, 0x466b2203, 0x9104711a,
+ 0xa90c9103, 0x99139108, 0xd0012900, 0xe0002108, 0x91092104, 0x75199913, 0x280079c0, 0x4628d009,
+ 0x308130ff, 0x29007901, 0x7941d003, 0x79009103, 0x98039004, 0x01009b04, 0x32801942, 0x98119903,
+ 0xfd6af001, 0x2d006f2d, 0x2001d001, 0x2000e000, 0x900f2600, 0x9811a901, 0xfd10f7ff, 0x2800900e,
+ 0x9813d13b, 0xd0192800, 0xa80ba90a, 0x2208ab0c, 0x700f781f, 0x7007785f, 0x1c491c40, 0x1c9b1e92,
+ 0xd1f52a00, 0x990b9800, 0x980a2800, 0x4008d004, 0x43814621, 0xe00ed10a, 0xe00a4308, 0x28009800,
+ 0x990cd006, 0x43884620, 0xd0042800, 0xe0032701, 0x4020980c, 0x2700e7f8, 0x4207980f, 0x4628d00b,
+ 0xd00d4330, 0x00c0207d, 0xf0012100, 0x2000fd0a, 0x1e6d43c0, 0x2f004146, 0x980ed1bc, 0xbdf0b015,
+ 0x900e4801, 0x0000e7f9, 0x00001772, 0xb089b5f0, 0x460c4616, 0x25044607, 0xf8baf000, 0xd0482800,
+ 0xd0462c00, 0x30ff30ff, 0x68003002, 0x0f800580, 0x7c60d002, 0xd0252802, 0x46692501, 0x9601700d,
+ 0x90027d60, 0x90037d20, 0x74082000, 0x30184620, 0x20049005, 0x46339006, 0x46212200, 0xf0004638,
+ 0x9802f82b, 0x01002101, 0x46381902, 0x9b033280, 0xfce2f001, 0x46384669, 0xf7ff9502, 0x0005fc8f,
+ 0xe001d117, 0xe0142500, 0x29008a61, 0x7c60d10c, 0xd0092802, 0xd0072803, 0x22004633, 0x46384621,
+ 0xff2af7ff, 0xe0044605, 0x43482064, 0xf0012100, 0x4628fca8, 0xbdf0b009, 0x4604b570, 0xb08a2004,
+ 0xd0242900, 0x466e2000, 0x20037030, 0x90022501, 0x74329503, 0x93012047, 0x28005c40, 0x4608d009,
+ 0x308130ff, 0x2a007a02, 0x7a42d003, 0x7a009202, 0x98029003, 0x01009b03, 0x21011842, 0x32804620,
+ 0xfc9af001, 0x46204669, 0xf7ff9502, 0xb00afc47, 0x0000bd70, 0x4616b570, 0x20004a13, 0x6812444a,
+ 0x29004604, 0x4d11d008, 0xd0072901, 0xd00a2902, 0x60302404, 0xbd704620, 0xe7fa4610, 0x05806968,
+ 0x46100f81, 0x69e8e00c, 0x6b004809, 0x0e890681, 0xf7fe4808, 0x2112f84d, 0x69e94348, 0x0f490189,
+ 0xf7fe1c49, 0xe7e4f845, 0x00000058, 0x400fc000, 0x400d80c0, 0x1c9c3800, 0x20044602, 0xd1042a00,
+ 0xd0022900, 0x60084801, 0x47702000, 0x07ed6b40, 0x20004601, 0xd1022900, 0x44784801, 0x47706800,
+ 0x0000236e, 0x4607b5f8, 0x461c2004, 0x2f00460e, 0x2a00d016, 0x2c00d014, 0x4611d012, 0xf7fe4809,
+ 0x4601f817, 0x43614605, 0xf7fe4630, 0xe000f811, 0x46011c40, 0x43614369, 0xd3f942b1, 0x20006038,
+ 0x0000bdf8, 0x3b9aca00, 0x460db570, 0xffd0f7ff, 0xd00a0004, 0xfc5cf001, 0x02c02001, 0x2d006821,
+ 0x4301d001, 0x4381e000, 0xbd706021, 0xb087b5f3, 0x2604460d, 0xf7ff9807, 0x0004ffbb, 0x2d00d07e,
+ 0x7c28d0fc, 0xd1022800, 0x28007f28, 0x6c28d009, 0xd40406c0, 0xf0004628, 0x2800f976, 0x2001d001,
+ 0x2000e000, 0x49619003, 0x42886828, 0x9807d166, 0xfb8cf7ff, 0x98074629, 0xf8bef000, 0x30404628,
+ 0x90029903, 0xd0022900, 0x21012200, 0x4628e005, 0xf959f000, 0x98024602, 0x98077981, 0xfb1cf7ff,
+ 0xf7ff9807, 0x6820fb7f, 0x43b02602, 0x46206020, 0xfbc9f001, 0x43306820, 0x68206020, 0x4008494c,
+ 0x79499902, 0xd1012908, 0x43080289, 0x43084949, 0x07897b29, 0x43010e89, 0x46296021, 0xf7ff9807,
+ 0x68a0fce3, 0x03c92101, 0x60a04388, 0xf0004628, 0x2800f931, 0x68a0d004, 0x04c92101, 0x60a04308,
+ 0x46204629, 0xfc42f7ff, 0x98074629, 0xfc68f7ff, 0x98074629, 0xfd06f7ff, 0x21026820, 0x60204388,
+ 0xf0014620, 0x4628fb90, 0x30507c29, 0x29009004, 0x9807d01c, 0x20049005, 0xe0002100, 0x9e04e052,
+ 0x460f9100, 0x9101ce02, 0xd00a2900, 0x9a004629, 0xf7ff9805, 0x2800fe6b, 0x9a01d106, 0x18899900,
+ 0x1c7f9100, 0xd3ed2f04, 0xd13b0006, 0x28007f28, 0x9807d01c, 0x20049005, 0xd0152d00, 0x9e042100,
+ 0x460f9100, 0x9101ce02, 0xd00a2900, 0x9a004629, 0xf7ff9805, 0x2800fd5f, 0x9a01d106, 0x18899900,
+ 0x1c7f9100, 0xd3ed2f04, 0xd11b0006, 0x28009803, 0x6820d017, 0x43302602, 0x46286020, 0xf8c3f000,
+ 0x98024602, 0x98077981, 0xfa86f7ff, 0x98074629, 0xfc6af7ff, 0x98074629, 0xfca4f7ff, 0x43b06820,
+ 0x26006020, 0xb0094630, 0x0000bdf0, 0x42464346, 0x0000df0f, 0xffff0000, 0x4d4bb5f8, 0x462e484b,
+ 0x460c9000, 0x46084637, 0xf8a9f000, 0xd0042800, 0x6ee06e26, 0x6e679000, 0x6d206ea5, 0x6d602800,
+ 0x2800d025, 0x4942d004, 0x63c82006, 0x63064841, 0x6d204b3f, 0x28003380, 0x2001d004, 0x483d6058,
+ 0x63863040, 0x20114a3a, 0x63503240, 0x30404839, 0x21016287, 0x62c56391, 0x63456019, 0x630563d1,
+ 0x62456311, 0x5d002045, 0xd0032808, 0x2800e00f, 0xe025d1d9, 0x2001492e, 0x62083140, 0x32404a2d,
+ 0x62886155, 0x624861d5, 0x61886195, 0x7b2060d5, 0xd0012803, 0xd1072801, 0x21114825, 0x62c13040,
+ 0x98004924, 0x62083140, 0xf0004620, 0x2800f853, 0x481fd006, 0x30402101, 0x481e61c1, 0x61073040,
+ 0x28006da0, 0xd02b6de0, 0xd0052800, 0x20064918, 0x60083140, 0x63464817, 0x28006da0, 0x4814d006,
+ 0x30402104, 0x481360c1, 0x60063040, 0x21114810, 0x61c13040, 0x3140490f, 0x2201610f, 0x614d6202,
+ 0x61cd6282, 0x618d6242, 0x60cd6182, 0x2a037b22, 0x2a01d001, 0x2214d103, 0x98006102, 0xbdf86048,
+ 0xd1d32800, 0x0000bdf8, 0x000010f1, 0x000130f1, 0x401f8100, 0x401f8280, 0x07806c00, 0x2001d501,
+ 0x20004770, 0x6c004770, 0xd5010640, 0x47702001, 0x47702000, 0x07c06c00, 0x2001d000, 0x6c004770,
+ 0xd5010680, 0x47702001, 0x47702000, 0x07406c00, 0x2001d501, 0x20004770, 0x6c004770, 0xd5010700,
+ 0x47702001, 0x47702000, 0xb08ab570, 0x20004605, 0x7030466e, 0x2401200f, 0x94039002, 0x460a7432,
+ 0x930132ff, 0x46233271, 0x46284621, 0xfa54f001, 0x46284669, 0xf7ff9402, 0xb00afa01, 0xb5ffbd70,
+ 0xb0812004, 0x2900460f, 0x463dd01e, 0x358135ff, 0x42496c69, 0x4014460c, 0x425218d2, 0x21ff400a,
+ 0x5dc931ca, 0x29004256, 0x6d29d10c, 0xd0092900, 0x4622e02a, 0x98014639, 0xf8fcf000, 0xd1032800,
+ 0x190c6c69, 0xd3f442b4, 0xbdf0b005, 0x46206d29, 0xd00e4388, 0x1b322000, 0xd00c2800, 0xd80a4291,
+ 0x46394622, 0xf0009801, 0x2800f88b, 0x6d29d1ec, 0x2001e009, 0x4622e7ef, 0x98014639, 0xf8daf000,
+ 0xd1e12800, 0x190c6c69, 0xd3df42b4, 0xb5f3e7dc, 0x2600b08b, 0x9d0c4669, 0x2101700e, 0x210b9103,
+ 0x46699102, 0x2047740e, 0x46375d40, 0x28004634, 0x4628d009, 0x308130ff, 0x29007d01, 0x7d41d003,
+ 0x7d009102, 0x22009003, 0x980b990c, 0xf8b1f7ff, 0x950a3550, 0x9009cd01, 0xd01a2800, 0x22004633,
+ 0x980b990c, 0xf96ff001, 0xd13e0004, 0x96019802, 0x980c0101, 0x180a9b03, 0x32802101, 0xf001980b,
+ 0x2001f9cb, 0x46699002, 0xf7ff980b, 0x0004f977, 0x9809d12b, 0x18361c7f, 0xd3db2f04, 0xd1242c00,
+ 0x90092000, 0x980c4606, 0x30ff9d0a, 0x900a30c1, 0x2f00cd80, 0x2200d013, 0x990c9b09, 0xf001980b,
+ 0x0004f919, 0x980ad111, 0x28007bc0, 0x2200d007, 0x990c9b09, 0xf001980b, 0x0004f84d, 0x9809d105,
+ 0x19c01c76, 0x2e049009, 0x980bd3e2, 0xf8baf7ff, 0x990c2201, 0xf7ff980b, 0x4620f85c, 0xbdf0b00d,
+ 0xb08ab5f7, 0x460d4617, 0xf7ff4608, 0x4606ff0f, 0x46292200, 0xf7ff980a, 0x463bf84c, 0x46294632,
+ 0xf001980a, 0x0004f910, 0x4669d139, 0x70089701, 0x24012008, 0x94039002, 0x2047740e, 0x28005d40,
+ 0x4628d009, 0x308130ff, 0x29007f01, 0x7f41d003, 0x7f009102, 0x98029003, 0x01002101, 0x32801942,
+ 0x980a9b03, 0xf958f001, 0x94024669, 0xf7ff980a, 0x0004f905, 0x463bd113, 0x46294632, 0xf001980a,
+ 0x0004f8b9, 0x20ffd10b, 0x5d4030d0, 0xd0062800, 0x4632463b, 0x980a4629, 0xffecf000, 0x980a4604,
+ 0xf860f7ff, 0x46292201, 0xf7ff980a, 0x4620f802, 0xbdf0b00d, 0xb08ab5f7, 0x460d4617, 0xf7ff4608,
+ 0x4606feb5, 0x46292200, 0xf7fe980a, 0x463bfff2, 0x46294632, 0xf001980a, 0x0004f8b6, 0x4669d139,
+ 0x70089701, 0x24012005, 0x94039002, 0x2047740e, 0x28005d40, 0x4628d009, 0x308130ff, 0x29007b01,
+ 0x7b41d003, 0x7b009102, 0x98029003, 0x01002101, 0x32801942, 0x980a9b03, 0xf8fef001, 0x94024669,
+ 0xf7ff980a, 0x0004f8ab, 0x463bd113, 0x46294632, 0xf001980a, 0x0004f85f, 0x20ffd10b, 0x5d4030d0,
+ 0xd0062800, 0x4632463b, 0x980a4629, 0xff92f000, 0x980a4604, 0xf806f7ff, 0x46292201, 0xf7fe980a,
+ 0x4620ffa8, 0xbdf0b00d, 0x460cb570, 0xf7ff4606, 0x0005fcbd, 0x4622d10b, 0x32802301, 0x46302100,
+ 0xf8caf001, 0x28017c60, 0x2000d101, 0x46287420, 0xb5ffbd70, 0x4617b089, 0x4608460d, 0xfe46f7ff,
+ 0x22004606, 0x98094629, 0xff83f7fe, 0x4632463b, 0x98094629, 0xf847f001, 0xd13f0004, 0x46692002,
+ 0x20097008, 0x90022401, 0x20479403, 0x46285d41, 0x308130ff, 0xd0062900, 0x29007c01, 0x7c41d003,
+ 0x7c019102, 0x46699103, 0x740e9701, 0x9105990c, 0x90066c00, 0x21019802, 0x19420100, 0x9b033280,
+ 0xf0019809, 0x4669f889, 0x98099402, 0xf836f7ff, 0xd1130004, 0x4632463b, 0x98094629, 0xffeaf000,
+ 0xd10b0004, 0x30d020ff, 0x28005d40, 0x463bd006, 0x46294632, 0xf0009809, 0x4604ff1d, 0xf7fe9809,
+ 0x2201ff91, 0x98094629, 0xff33f7fe, 0xb00d4620, 0x0000bdf0, 0xb089b5ff, 0x9c122004, 0x4616461f,
+ 0xd0222900, 0xd0202e00, 0xd01e2c00, 0xf7ff4608, 0x2103fddd, 0x7011466a, 0x91032101, 0x91022100,
+ 0x4d0b7410, 0xd80042ac, 0x46694625, 0x96079701, 0x98099508, 0xfff2f7fe, 0xd1062800, 0x008908a9,
+ 0x197f1b64, 0x2c00198e, 0xb00dd1eb, 0x0000bdf0, 0x0000ffff, 0xb0b4b5f7, 0x900048ab, 0x46156810,
+ 0x0f000200, 0x2809460c, 0x2600d01b, 0x225049a7, 0xa81e4479, 0xfae4f7fd, 0x90022000, 0x30404620,
+ 0x90012104, 0x68287141, 0x04000301, 0x20100f05, 0x64200f0f, 0xd0062f00, 0xd01b2f02, 0xd01c2f03,
+ 0x2601e129, 0xa804e7e2, 0xfe14f000, 0x20009000, 0xffccf000, 0x28009800, 0xaa04d107, 0x98344621,
+ 0xfecaf000, 0x28009000, 0x9901d1ea, 0x71482001, 0xe0002000, 0x73202003, 0x2003e008, 0x20087320,
+ 0x2e009901, 0xd1017148, 0x90022001, 0xd0032d00, 0xd0012d02, 0xd1d32d03, 0x43284638, 0x2601d100,
+ 0xd0022d02, 0xd0022d03, 0x2004e004, 0x2008e000, 0x71489901, 0x6c202140, 0xd0012e00, 0xe0004388,
+ 0x64204308, 0x98344621, 0xfeeef7ff, 0x28009000, 0x2e00d1b6, 0x2f02d008, 0x2f03d002, 0xe001d10c,
+ 0xe0092001, 0xe0072002, 0xd0022f02, 0xd1032f03, 0x2003e001, 0x2004e000, 0xa91e0100, 0x23011842,
+ 0x98344619, 0xffa8f000, 0x9a02a905, 0xf0009834, 0x9000fdd5, 0xd17d2800, 0xaa32ab33, 0x4620a905,
+ 0xfffef000, 0x73202003, 0x30804620, 0x63014960, 0x61014960, 0xd0012e00, 0xe0002302, 0x2e002322,
+ 0x210cd001, 0x212ce000, 0x2e00468e, 0x2109d001, 0x2129e000, 0x2e009102, 0x2208d001, 0x2228e000,
+ 0x0d8f07a9, 0x46399204, 0x07aa9701, 0x370b0992, 0x4317069b, 0x431f469c, 0x431f4b4f, 0x46736007,
+ 0x029b1d0f, 0x9b02431f, 0x069b4317, 0x9302431f, 0x049b2301, 0x6047431f, 0x3720460f, 0x46634317,
+ 0x4b45431f, 0x431f4696, 0x460f6507, 0x431737d8, 0x431f4663, 0x431f4b40, 0x33f91de3, 0x1c8f601f,
+ 0x46624317, 0x4a3c4317, 0x611f4317, 0x9a04460f, 0x02923780, 0x22014317, 0x31600292, 0x4311615f,
+ 0x63192702, 0xd0012d02, 0xd10f2d03, 0x46739901, 0x43191d49, 0x43199b02, 0x43194b30, 0x99016201,
+ 0x43111d89, 0x32cd22ff, 0x55176401, 0x61a12100, 0xe0002d02, 0xd002e03f, 0xd0032d03, 0x2201e005,
+ 0xe0010492, 0x04d22201, 0x2e0061a2, 0x6c22d010, 0x431a2380, 0x64222301, 0x55132279, 0x66024a20,
+ 0x66424a20, 0x74202001, 0xd0072d00, 0xe0067467, 0x69a22301, 0x431a05db, 0xe7ef61a2, 0x22067461,
+ 0x75207562, 0x46688260, 0x2e007301, 0x2d02d008, 0x2d03d002, 0xe007d002, 0xe0122041, 0xe0102081,
+ 0xd00b2d02, 0xd00b2d03, 0x20087341, 0x73c84669, 0xf0009803, 0x9800feab, 0xbdf0b037, 0xe0002042,
+ 0x46692082, 0xe7f07348, 0x00004e8d, 0x00001bac, 0x00000406, 0x24040405, 0x00200400, 0x00040400,
+ 0x04000471, 0x00002003, 0x460db5f7, 0x2103b088, 0x73e94628, 0x30402308, 0x23587143, 0x2401642b,
+ 0x2a007329, 0x2159d001, 0x71c46429, 0x8781210f, 0x462e87c4, 0x36ff2001, 0x36810240, 0x02406430,
+ 0x65306470, 0x30404630, 0x72449007, 0x98084629, 0xfdcaf7ff, 0xd1392800, 0x2700485d, 0x485d9000,
+ 0x23019703, 0x97029001, 0x4619466a, 0xf0009808, 0x9702fe93, 0x4f569703, 0x37804857, 0x23019001,
+ 0x2100466a, 0x98089700, 0xfe86f000, 0x02c02013, 0x23029006, 0x4951aa06, 0xf0009808, 0x2800fc77,
+ 0x2308d114, 0x2110aa04, 0xf0009808, 0x2800fc5b, 0x9805d10c, 0xb280494a, 0x98049005, 0xd1044288,
+ 0x98052159, 0x42880209, 0x4846d002, 0xbdf0b00b, 0xaa042308, 0x98082127, 0xfc44f000, 0xd1f52800,
+ 0x04009804, 0x90040e00, 0x28093817, 0x9904d8ed, 0x40882001, 0x200f6528, 0x90060300, 0xaa062302,
+ 0x98082100, 0xfc42f000, 0xd1df2800, 0x4930462c, 0x31803480, 0x49346021, 0x49346061, 0x493460a1,
+ 0x4b354a34, 0x34104f35, 0x4f29c48e, 0x378035ff, 0x4f336027, 0x4f2d6067, 0x341060a7, 0x4f31c40e,
+ 0x602260a7, 0x4f306061, 0x4f2e60e7, 0x4f2f6127, 0xc58e3511, 0x34144f1e, 0x602f3f20, 0x606f4f2c,
+ 0xc48e4f2c, 0x4f27c40e, 0x602260a7, 0x4f266061, 0x4f2460e7, 0x4c166127, 0x3c203d20, 0x4c26602c,
+ 0x4c26606c, 0x462f60ac, 0x37304c22, 0xc70ec71e, 0x656c4c1c, 0x652964ea, 0x65ac4c1b, 0x37144c19,
+ 0xc70e65ec, 0x66e9491e, 0x72312102, 0x72722203, 0x22017131, 0x74317172, 0x74712109, 0x73312104,
+ 0x73732305, 0x210b7531, 0x99077571, 0xe77d730a, 0x8b188720, 0xa3028f10, 0xa7048f10, 0x00000555,
+ 0x52005100, 0x00004e8d, 0xb3068f10, 0x0000a704, 0x87008700, 0x87aa8700, 0x87058700, 0x87708700,
+ 0xb70b8f10, 0x87558700, 0x87028700, 0x87a08700, 0xa3808f10, 0x87808700, 0x87008f10, 0x00008730,
+ 0x87108700, 0x460cb5f7, 0xb0a64979, 0x22204617, 0xa81d4479, 0xf874f7fd, 0x02016838, 0x29070f09,
+ 0x2100d008, 0x91000300, 0xd0050f00, 0x73202003, 0xe0142050, 0xe7f52101, 0xf000a801, 0x4605fbab,
+ 0xf0002000, 0x2d00fd63, 0xaa01d106, 0x98264621, 0xfc62f000, 0xd1140006, 0x73202000, 0x46252010,
+ 0x35402108, 0x71696420, 0x98264621, 0xfcacf7ff, 0xd1f00006, 0x03006838, 0xd0030f01, 0x28030f00,
+ 0xe0b1d003, 0xaa1d2301, 0x2301e001, 0x2101aa21, 0xf0009826, 0x2008fd71, 0x22007168, 0x9826a904,
+ 0xfb9cf000, 0xd12b0006, 0xaa02ab03, 0x4620a904, 0xfdc6f000, 0x98004625, 0x35802206, 0xd0202800,
+ 0x6628484c, 0x6668484c, 0x66a8484c, 0x61a0200c, 0x74202001, 0x75207562, 0x63284849, 0x61284849,
+ 0x03086839, 0x46200f03, 0x30c130ff, 0x38c09001, 0xd00b2b03, 0x0f0b0409, 0xd0072b03, 0xd0200f09,
+ 0x2050e072, 0x20036420, 0xe7e57320, 0x6229493e, 0x6029493e, 0x6069493e, 0x6429493e, 0x39dc493b,
+ 0x493a6529, 0x60013921, 0x0149213b, 0x49376301, 0x610139eb, 0x61414938, 0x03006838, 0xd0360f00,
+ 0x2101e04f, 0x06096d27, 0xd302428f, 0x218e2220, 0x2218e001, 0x9b0221c2, 0xb2db0412, 0x43134c2f,
+ 0x652b4323, 0x43119b03, 0x4313b2db, 0x60034323, 0x43194b2b, 0x21476101, 0x614101c9, 0x29009900,
+ 0x21cbd00d, 0x42a7039c, 0x21ccd300, 0x43194311, 0x49246029, 0x21236069, 0x63010149, 0x4922e024,
+ 0x491b6029, 0x9a016069, 0x73912101, 0x2000e7f3, 0x70084669, 0x208270ca, 0x46177048, 0xf0009800,
+ 0x2001fca5, 0x21027420, 0x21e77461, 0x756761a1, 0x82607520, 0x66284807, 0x38814806, 0x48076668,
+ 0x990166a8, 0x73082002, 0xb0294630, 0x0000bdf0, 0x000016ac, 0x04000481, 0x04010400, 0x00002001,
+ 0x00000406, 0x24040405, 0xa7040705, 0x8b2007fd, 0xa704b306, 0x00000706, 0x0000a304, 0x08000400,
+ 0x0b000400, 0x2704330c, 0x8b2004fd, 0xb09cb5f7, 0x460c981e, 0x02286805, 0x28050f00, 0x2600d011,
+ 0x223049cb, 0xa80d4479, 0xff5af7fc, 0x0f000428, 0x0328900a, 0x980a0f05, 0xd0042800, 0xd1132803,
+ 0x2601e001, 0x2d00e7ec, 0x2d03d010, 0x2800d10c, 0x2003d00a, 0x20107320, 0x981e6420, 0x02006800,
+ 0x28040f00, 0xe019d018, 0xe16e2704, 0xf0004668, 0x4607fa81, 0xf0002000, 0x2f00fc39, 0x466ad106,
+ 0x981c4621, 0xfb38f000, 0xd1ee0007, 0x73202000, 0x64202010, 0xe0022003, 0x64202050, 0x90092006,
+ 0x4328980a, 0x2601d100, 0x990a4620, 0x29033040, 0x2101d008, 0x46217141, 0xf7ff981c, 0x0007fb75,
+ 0xe001d1d3, 0xe7f52108, 0x2d002000, 0x2e00d004, 0x2001d001, 0x2002e000, 0xa90d0100, 0x23011842,
+ 0x981c4619, 0xfc38f000, 0x46692000, 0x75089002, 0x71082003, 0x90032001, 0xa80b9004, 0xa9019008,
+ 0xf7fe981c, 0x0007fbdb, 0xa808d1af, 0x28c27b00, 0x2101d1ab, 0x2d000409, 0xd01da808, 0x460a7c40,
+ 0x40823830, 0x46206522, 0x30ff2201, 0x30810312, 0x11126442, 0x65016402, 0x73202003, 0x64202010,
+ 0x40462001, 0x46294620, 0x30c130ff, 0x35804625, 0x29009019, 0xe045d002, 0xe7e07b80, 0x2803980a,
+ 0x2101d140, 0x20027421, 0x82617460, 0x75622206, 0x23007521, 0x22074669, 0x70ca700b, 0xd0172e00,
+ 0x466a2182, 0x61a07051, 0x66284872, 0x38724871, 0x48716668, 0x981e66a8, 0x06007800, 0x28030f00,
+ 0x9919d002, 0xe01a728b, 0x20019919, 0xe0167288, 0x466b2181, 0x61a07059, 0x48684b66, 0x6668662b,
+ 0x66a84865, 0x46202101, 0x30207721, 0x70017042, 0x63214860, 0x672b3872, 0x485f6768, 0x980067a8,
+ 0xfb84f000, 0x6328485e, 0x6128485e, 0x990a1de0, 0x290030f9, 0x2e00d003, 0x2321d016, 0x2101e015,
+ 0x49597321, 0x49596029, 0x49576069, 0x61011d89, 0x61414957, 0x31154954, 0x49536529, 0x600131d0,
+ 0x01492123, 0xe0906301, 0x2e002301, 0x2122d001, 0x2102e000, 0x2e00468c, 0x212cd001, 0x210ce000,
+ 0x2e00911a, 0x2129d001, 0x2109e000, 0x2e00910a, 0x2128d001, 0x2108e000, 0x2e009100, 0x4a40d007,
+ 0x3a180299, 0x069a1889, 0x4a424311, 0x22fbe006, 0x00920299, 0x069a1889, 0x4a3f4311, 0x60294311,
+ 0x22194661, 0x01520289, 0x991a188a, 0x06894696, 0x4a3a4311, 0x60694311, 0x22c1990a, 0x00920289,
+ 0x920a188a, 0x60aa0299, 0x069b4a35, 0x469c188a, 0x4b34431a, 0x642b4313, 0x1e5b4b31, 0x466318ca,
+ 0x4b31431a, 0x622b4313, 0x021b2303, 0x466318ca, 0x2303431a, 0x4313061b, 0x62ab626b, 0x9a0a4b28,
+ 0x62ea330c, 0x466318ca, 0x4b28431a, 0x61034313, 0x46729b00, 0x431a069b, 0x049b23c1, 0x61434313,
+ 0x331b4b1f, 0x466318ca, 0x4b21431a, 0x46724313, 0x656a652b, 0x009222f7, 0x4663188d, 0x4b1d431d,
+ 0x431d4672, 0x60426005, 0x0152221b, 0x46631889, 0x43194a19, 0x63014311, 0xd0032e00, 0x21406c20,
+ 0x64204308, 0x20029919, 0x46387308, 0xbdf0b01f, 0x00001448, 0x04000472, 0x20010400, 0x04020400,
+ 0x00000406, 0x24040405, 0x0820040c, 0x24043008, 0x00002004, 0x03110000, 0x03130000, 0x03060000,
+ 0x00000306, 0x03f90000, 0x03fa0000, 0x03ed0000, 0x03de0000, 0x03230000, 0x039f0000, 0x4607b5f0,
+ 0xb0a92000, 0x4616460d, 0x49262404, 0x90269025, 0x22309027, 0x90284479, 0xf7fca819, 0x6830fd91,
+ 0x0f000300, 0x2104d13b, 0x55412045, 0x491e4628, 0x60013080, 0x6041491d, 0x46384629, 0xf9e4f7ff,
+ 0xd12c0004, 0x06007830, 0x28010f00, 0x1de8d10e, 0x30f94917, 0x67416701, 0x67811409, 0x461a2300,
+ 0x46384629, 0xf840f7ff, 0xd1180004, 0xa9196830, 0x0f000300, 0x18420100, 0x46192301, 0xf0004638,
+ 0x2200fa9b, 0x46384669, 0xf8c8f000, 0xd1060004, 0x466a4633, 0x46384629, 0xfc42f000, 0x46204604,
+ 0xbdf0b029, 0x00001088, 0x08180403, 0x00012404, 0x06ff06ff, 0x2704b5f7, 0x460c4615, 0xd05a2900,
+ 0xd0582d00, 0x462001f9, 0xfe50f7fc, 0x46262101, 0x71b13640, 0x65200608, 0x60204828, 0x60604828,
+ 0x73602003, 0x20ff73a0, 0x550130c9, 0x01006828, 0xd0080f00, 0x03006868, 0x28010f00, 0x6c20d103,
+ 0x43080209, 0x68286420, 0x0f000200, 0xf7fe0003, 0x060af82f, 0x17110c06, 0x231d1d17, 0x462a3023,
+ 0x98004621, 0xff6af7ff, 0x2201e001, 0x0007e003, 0xe01ed018, 0x46212200, 0xf7ff9800, 0xe7f6fb75,
+ 0x4621462a, 0xf7ff9800, 0xe7f0fd91, 0x4621462a, 0xf7ff9800, 0xe7eafc77, 0x4621462a, 0xf7ff9800,
+ 0xe7e4f9f9, 0xf0004620, 0x7828f9f7, 0x0f000700, 0x200171b0, 0x46387130, 0x0000bdfe, 0x42464346,
+ 0x56010400, 0xb089b530, 0x466d2403, 0x2501702c, 0x24000049, 0x91019503, 0x466d9402, 0x4669742c,
+ 0x92079308, 0xf9baf7fe, 0xbd30b009, 0xb089b530, 0x466d2402, 0x2401702c, 0x91010049, 0x94039402,
+ 0x74292100, 0x93064669, 0xf7fe9205, 0xb009f9a7, 0x0000bd30, 0x6a894902, 0x20006001, 0x00004770,
+ 0x400f8000, 0x4607b5f0, 0xb0892004, 0x4614461d, 0x2a00460e, 0x2124d00f, 0xf7fc4668, 0x2003fdb7,
+ 0x70084669, 0x90022001, 0x90039508, 0x94079601, 0xf7fe4638, 0xb009f983, 0x0000bdf0, 0x4e3ab5f7,
+ 0x000db098, 0x2308d008, 0x2100466a, 0xf7ff9818, 0x0004ffd9, 0xe001d164, 0xe0612404, 0x98004933,
+ 0xd0014288, 0xe05b4634, 0x79004668, 0x46686028, 0x1c407980, 0xd900280a, 0x9016200a, 0x2108981a,
+ 0xd0002800, 0x98160209, 0x00c3aa02, 0xf7ff9818, 0x0004ffb9, 0x2164d144, 0xf7fc4628, 0x2600fd77,
+ 0x00f0e03b, 0x5c11aa02, 0x79d81883, 0x180a0200, 0x020020ff, 0xd0024282, 0x4282481d, 0x2100d12c,
+ 0x020f2002, 0x79091819, 0x1e404339, 0x78d8d5f9, 0x981a0087, 0xd0002800, 0x20ff0209, 0x42820200,
+ 0x2f50d10c, 0x2750d900, 0x463b462a, 0x98183208, 0xff88f7ff, 0xd1130004, 0xe00d606f, 0x4282480c,
+ 0x462ad10a, 0x325c463b, 0xf7ff9818, 0x0004ff7b, 0x2101d106, 0x55412058, 0x98161c76, 0xd3c04286,
+ 0xb01b4620, 0x0000bdf0, 0x00004e8b, 0x50444653, 0x0000ff84, 0xb089b5ff, 0x4616461d, 0x9809460c,
+ 0xf8e1f000, 0xd1142800, 0x70084669, 0x200e2701, 0x90029703, 0x4622740e, 0x326132ff, 0x4639463b,
+ 0x98099501, 0xf938f000, 0x97024669, 0xf7fe9809, 0xb00df8e5, 0x0000bdf0, 0x2504b5f7, 0x4617b092,
+ 0x2a00460c, 0x7878d004, 0x42887839, 0x2500d101, 0x4620e087, 0x21083040, 0x71419011, 0x25037878,
+ 0x28422601, 0x2841d001, 0x2502d103, 0x21049811, 0x78787141, 0xd0012882, 0xd1002842, 0x20002621,
+ 0x90014669, 0x70087408, 0x90022001, 0xa8092120, 0xfcdcf7fc, 0x200278f9, 0x29060242, 0x2907d00b,
+ 0x2908d012, 0x2001d001, 0x0229e02b, 0x43131d8b, 0x930931ff, 0x0229e005, 0x3366460b, 0x31994313,
+ 0x43119309, 0xe01c910d, 0x460f0229, 0x376602b2, 0x4317062b, 0x431f06b5, 0x432f46ac, 0x31992599,
+ 0x4311042d, 0x4319432f, 0x22334665, 0x04524329, 0x97094311, 0x2e21910d, 0x6c21d103, 0x43112240,
+ 0x90036421, 0x20019911, 0x06017188, 0x49166521, 0x49166021, 0x21036061, 0x73a17361, 0x31c921ff,
+ 0x200a5508, 0x46216760, 0xf7fe9812, 0x0005ffdd, 0xaa09d117, 0x9b032101, 0xf0009812, 0x4669f8ad,
+ 0xf7fe9812, 0x4605f85b, 0x217d4809, 0x00c94448, 0xf7fc6800, 0xe001fc7d, 0x1e40bf00, 0x28009011,
+ 0x4628d1fa, 0xbdf0b015, 0x42464346, 0x56010400, 0x00000058, 0x2004b5ff, 0x469cb083, 0x29004696,
+ 0x460dd01f, 0x35c135ff, 0x460c7b28, 0x28023480, 0x4620d10b, 0xc8893010, 0x69e6466a, 0x4620c289,
+ 0xc88d3020, 0xc48d3410, 0x46633c20, 0x98034672, 0xfad2f7fe, 0x29027b29, 0x466dd103, 0x3410cd0e,
+ 0xb007c44e, 0xb5ffbdf0, 0xb0832004, 0x2900460d, 0x462ed029, 0x36c136ff, 0x28007b70, 0x9b06d006,
+ 0x98039a05, 0xfdf0f7fe, 0xd11c2800, 0x462c7b30, 0x28023480, 0x4620d10a, 0xc8873030, 0xc307466b,
+ 0x30404620, 0x3430c80f, 0x3c40c40f, 0x9b064629, 0x98039a05, 0xfb80f7fe, 0x29027b31, 0x466dd103,
+ 0x3430cd0e, 0xb007c48e, 0x0000bdf0, 0x62884901, 0x47702000, 0x400f8000, 0x28002104, 0x7b01d00f,
+ 0xd10b2903, 0x30606c01, 0x29000649, 0x2113da01, 0x7e41e003, 0xd1012900, 0x76012126, 0x46082100,
+ 0xb5f84770, 0x460f4606, 0x2001e002, 0xf94ef000, 0x463c2000, 0x1e7643c0, 0x46274144, 0x43f943f0,
+ 0xd1f24308, 0x6801bdf8, 0x43112201, 0x68016001, 0xd1fc07c9, 0x00004770, 0x460eb5f8, 0x461f2104,
+ 0x91004615, 0xfba4f7fe, 0xd0230004, 0xd0212d00, 0x19f22100, 0x23104149, 0x1a9a2000, 0xd3194188,
+ 0xf0004620, 0x4a0cf825, 0x200261a2, 0x19f161e0, 0x008b00b0, 0x19090081, 0x31ff31ff, 0xe0023102,
+ 0xc140cd40, 0x42981c40, 0x61a2d3fa, 0x61e02001, 0x90002000, 0xbdf89800, 0x5af05af0, 0xf7feb510,
+ 0x2800fb77, 0x3080d003, 0x07896e01, 0xbd10d5fc, 0x6e013080, 0xd0fc07c9, 0x07896e01, 0x4770d5fc,
+ 0x4805b510, 0x05806940, 0x48040f81, 0x44481c49, 0xf7fc6800, 0xbd10fb8d, 0x400fc000, 0x00000058,
+ 0x4805b510, 0x05806940, 0x48040f81, 0x44481c49, 0xf7fc6800, 0xbd10fb7d, 0x400fc000, 0x00000058,
+ 0x4608b5ff, 0x305cb082, 0x460b9000, 0x330868c8, 0x28002701, 0x463ada03, 0x40821ec0, 0x1c40e001,
+ 0x980208c2, 0x650224ff, 0x92019e02, 0x36ff6848, 0x36813401, 0xd2012840, 0xe00a6434, 0x06008d18,
+ 0x46380f02, 0x22014090, 0x429003d2, 0x4620d100, 0x4d316430, 0x46202400, 0x18d20042, 0x2f007f17,
+ 0x2201d00d, 0x42aa40ba, 0x4615d201, 0x42a24684, 0x2701d905, 0x42ba053f, 0x4614d201, 0x1c404686,
+ 0xd3e92804, 0x65346475, 0x30ff9802, 0x42a530c1, 0x2201d101, 0x2200e000, 0x22017242, 0x06129801,
+ 0xd92d4290, 0x7e083140, 0xd0082800, 0x44609800, 0x98047901, 0x98006001, 0x79014470, 0x4660e018,
+ 0x18c00040, 0x21217f40, 0x282022dc, 0x28d8d002, 0xe002d105, 0x60019804, 0x9804e001, 0x46706002,
+ 0x18c00040, 0x28207f40, 0x28d8d002, 0xe002d105, 0x60019805, 0x9805e001, 0x20006002, 0xbdf0b006,
+ 0x00404660, 0x7f4118c0, 0x60019804, 0x00404670, 0x7f4118c0, 0x0000e7ec, 0x00ffffff, 0x20ff4a0e,
+ 0x68526851, 0x0f890609, 0x0f920692, 0xd0072900, 0xd00f2901, 0xd0072902, 0xd1002903, 0x47702002,
+ 0xd0032a00, 0xd0032a01, 0x47702008, 0x47702001, 0x47702010, 0x47702020, 0x400f8000, 0x47704800,
+ 0x01312d00, 0x2003b510, 0x21030240, 0xfbbaf7fc, 0x2000bd10, 0x20004770, 0x00004770, 0xb5104903,
+ 0x00c04449, 0xf7fc6809, 0xbd10fab3, 0x0000004c, 0xb5104905, 0x68094449, 0xfc92f7fd, 0x08c0074a,
+ 0x08c94310, 0x0000bd10, 0x0000004c, 0x4602b570, 0xf832f000, 0x4909460d, 0x44494604, 0x68094610,
+ 0xfc7ef7fd, 0x08c3074a, 0x08ca4313, 0x416a191c, 0xf822f000, 0x41911b00, 0xbd70d3fa, 0x0000004c,
+ 0x4809b510, 0x69c06941, 0x0f890589, 0x48070684, 0x44480ea4, 0x1c496800, 0xf7fc1c64, 0x4621fa79,
+ 0xfa76f7fc, 0x0000bd10, 0x400fc000, 0x00000058, 0xf7ffb510, 0xbd10fed5, 0x4803b508, 0x6a406a01,
+ 0x43c09000, 0xbd0843c9, 0x400840c0, 0x4813b510, 0x68012304, 0x03122203, 0x43114391, 0x48106001,
+ 0x60012100, 0x1e4a480f, 0x61816102, 0x61c42401, 0x43196981, 0x69816181, 0x61814321, 0x60c46002,
+ 0xf7ff6084, 0x00c0ffbd, 0xf7fc4907, 0x4907fa41, 0x44492800, 0xd1006008, 0xbd10600c, 0x400fc06c,
+ 0x40084000, 0x40084100, 0x000f4240, 0x0000004c, 0x68014802, 0x43112202, 0x47706001, 0x40084000,
+ 0xb08bb5ff, 0x90032004, 0x460f980d, 0x90013008, 0x305c980d, 0x20009008, 0x980e9002, 0x02006800,
+ 0x28010f00, 0x9801d105, 0x03006800, 0x90020fc0, 0x2000d07e, 0x990e7338, 0x78094606, 0x070aab0a,
+ 0x21460f12, 0x900055ca, 0x90042018, 0x90052000, 0x4638aa09, 0xf7ff990d, 0x2101fe83, 0x06096d38,
+ 0xd9014288, 0x90042020, 0x8800980e, 0x0f000400, 0x4639d15e, 0x9a0d9b0e, 0xf000980b, 0x9003f9cb,
+ 0xd1f52800, 0x68009801, 0xd5080281, 0x90052002, 0x7a009801, 0x0f4e0601, 0x0ec006c0, 0x0240e007,
+ 0x9801d506, 0x02016880, 0x02c00f4e, 0x90000ec0, 0x9a04980d, 0x1dfc3040, 0x34f949a2, 0x2a209007,
+ 0x48a1d002, 0xe0116120, 0x4ba07e00, 0xd03c2800, 0x4a9f9808, 0x05c56800, 0x489ed501, 0x0600e003,
+ 0x489ad533, 0x61623022, 0xe0006120, 0x20016161, 0x463d7338, 0x35804898, 0x48986328, 0x98096128,
+ 0xb2c14a97, 0x04009804, 0x43114301, 0x65299006, 0xb2c9990a, 0x43114301, 0x01402023, 0x63206021,
+ 0x6800980e, 0x0f010100, 0x990ed011, 0xe0006849, 0x060ae0e3, 0xd00a0e12, 0x9902b2c8, 0x90002600,
+ 0xd0212900, 0x90000040, 0x6123e01e, 0x9902e7ce, 0xd0192900, 0xd1170f00, 0x28209804, 0x487bd104,
+ 0x60281c40, 0x6068487f, 0x980b4639, 0xfcbcf7fe, 0x28009003, 0x466ad185, 0x980b4639, 0xf9e8f000,
+ 0x28009003, 0x2600d1f6, 0x28189804, 0xd0039802, 0xd01c2800, 0xe00220ee, 0xd0082800, 0x6c3920ed,
+ 0x43112240, 0x99066439, 0x486f4301, 0x9801e033, 0x02816800, 0x9801d503, 0x04008900, 0x0240e003,
+ 0x9801d503, 0x0e006880, 0x2003e01f, 0x9807e010, 0x28007e00, 0x9808d010, 0x06816800, 0x20ecd502,
+ 0xe0032102, 0xd52706c0, 0x2100206c, 0xe00c9105, 0x460e2100, 0xe0089100, 0x68009801, 0xd5010281,
+ 0xe00220ec, 0xd5170240, 0x9906206c, 0x98054301, 0x43010600, 0x463a4852, 0x60294301, 0x32ff990e,
+ 0x32c17809, 0x20000609, 0x92050f0b, 0xd0052b00, 0x29010f09, 0xe06dd006, 0xe7d92013, 0x19809800,
+ 0xe0499000, 0x6849990d, 0xd3f72940, 0x6b899901, 0xd5f3058a, 0x0f090309, 0x42112205, 0x20a5d001,
+ 0x0789e00b, 0x4639d509, 0x9a0d9b0e, 0xf000980b, 0x9003f895, 0xd14d2800, 0x99012001, 0x8f09220a,
+ 0x0e890409, 0xd0074211, 0x67214938, 0x99046761, 0xd1092920, 0xe0064936, 0x42112211, 0x4935d03a,
+ 0x67616721, 0x67a14934, 0x9a052101, 0x73512e00, 0x9902d011, 0xd0332900, 0xd02e2e01, 0x02892127,
+ 0x99004308, 0x0a090609, 0x492c4308, 0x60684308, 0x60a8482b, 0x9800e017, 0xd00f2800, 0x49299a02,
+ 0xd0052a00, 0x1840b2c0, 0x43084927, 0xe00a6068, 0x1840b2c0, 0x43084925, 0xe00b6068, 0x60684824,
+ 0x28009802, 0x9905d006, 0x73882001, 0x21406c38, 0x64384308, 0xb00f9803, 0x2126bdf0, 0xe7ce0900,
+ 0xd00c2e01, 0x02892107, 0x99004308, 0x0a090609, 0x49184308, 0x60684308, 0x60a84817, 0x2106e7ea,
+ 0xe7f00900, 0x00002004, 0x08180402, 0x08200412, 0x00002204, 0x0a20043e, 0x00000406, 0x24040405,
+ 0x08000400, 0x00012404, 0x8a000400, 0x06ff06ff, 0x000006ff, 0x06000600, 0x32101e00, 0xb2000200,
+ 0x7c01a604, 0x00040200, 0xa604b000, 0x26043000, 0x00002404, 0x32000200, 0x7c012604, 0xb08eb570,
+ 0x2100460c, 0x9100910c, 0x910d910b, 0x9102466a, 0x75114606, 0x71102003, 0x95032501, 0x95094813,
+ 0x900a9208, 0x9504462b, 0x4629aa0a, 0xf7ff4630, 0xa901fc63, 0xf7fd4630, 0x2800fc11, 0x9900d113,
+ 0x401122f7, 0x040a4b0a, 0x910018d3, 0x742522ff, 0x51133261, 0x220e7525, 0x61a17562, 0x74612104,
+ 0x34c134ff, 0xb00e73e5, 0x0000bd70, 0x24010485, 0x04000481, 0xb08fb5ff, 0x460c2000, 0x900b900a,
+ 0x900d900c, 0x25016811, 0x2905461e, 0x6851d202, 0xd3152940, 0x6c117425, 0x0f490249, 0xf7fd000b,
+ 0x0d07fa07, 0x050b0905, 0x000d0705, 0xe00b2702, 0xe0092704, 0xe0072701, 0xe0052703, 0xe06d7420,
+ 0x05098831, 0xd0690f0f, 0x90002000, 0x90024669, 0x20037508, 0x95097108, 0x95049503, 0x2f019108,
+ 0x2f02d007, 0x2f03d003, 0x2f04d02a, 0x482dd104, 0x482ce001, 0x900a3830, 0xaa0a2301, 0x980f4619,
+ 0xfbfaf7ff, 0x980fa901, 0xfba8f7fd, 0xd1462800, 0x01006830, 0xd0050f00, 0x040088b0, 0xd0010e01,
+ 0x90000e00, 0x74202000, 0x30804620, 0xd00a2f01, 0x2f022202, 0x2f03d010, 0x2f04d026, 0xe01bd12e,
+ 0x300a4818, 0x9900e7d7, 0xd427064a, 0x66024a16, 0x400120c3, 0xe01e2040, 0x078b9900, 0x4b13d41e,
+ 0x66034311, 0x90000208, 0x75257425, 0x75602006, 0x61a09800, 0xe0117465, 0x078b9900, 0x4b0ad40e,
+ 0x43113330, 0xe0076603, 0x060a9900, 0x4a07d406, 0x6602323d, 0x43012080, 0xe7e59100, 0xb0132000,
+ 0x0000bdf0, 0x24010435, 0x20010401, 0x20020401, 0x2001b5f7, 0xb0980240, 0x90012700, 0x74074668,
+ 0x460d2401, 0x94039702, 0xd0722900, 0x4478485b, 0xa90dc84d, 0x2003c14d, 0x7010466a, 0x9007a809,
+ 0x90082010, 0x3280462a, 0x9b032101, 0xf7ff9818, 0x4669fb83, 0x98189402, 0xfb30f7fd, 0xd1582800,
+ 0x1c409809, 0x980ad108, 0xd1051c40, 0x1c40980b, 0x980cd102, 0xd0071c40, 0xa9092210, 0xf7fba80d,
+ 0x2800fefa, 0xe034d145, 0x461a2300, 0x98184629, 0xfaf9f7ff, 0xd17b2800, 0x90022009, 0x46692002,
+ 0xa80d7008, 0x2610462a, 0x32ff9005, 0x32119606, 0x9b032101, 0xf7ff9818, 0x4669fb4f, 0x98189402,
+ 0xfafcf7fd, 0xd1632800, 0x461a2300, 0x98184629, 0xfda2f7fd, 0xd15b2800, 0x20039002, 0x70084669,
+ 0x9007a809, 0x98189608, 0xfae8f7fd, 0xd14f2800, 0x2032e7c2, 0x20009016, 0x6c289015, 0x43082140,
+ 0x20466428, 0x26025d41, 0x98182201, 0xfa64f7fd, 0xe03de038, 0x94112400, 0x94139412, 0x21019414,
+ 0x06096d28, 0xd9014288, 0xe000481d, 0x9011481d, 0xb2f0491d, 0x491d1840, 0x43082301, 0xaa119012,
+ 0x98182100, 0xfb08f7ff, 0x46692003, 0x70089402, 0x9007a809, 0x90082010, 0xf7fd9818, 0x0004faaf,
+ 0x2f00d006, 0x981ad014, 0x60062f00, 0xe010d010, 0xa9092210, 0xf7fba80d, 0x2800fe7e, 0x1c76d00c,
+ 0xd1f02f00, 0x99169815, 0x90151c40, 0xd3c14288, 0xb01b4c07, 0xbdf04620, 0xe7e42701, 0x000001fe,
+ 0x8a2004ee, 0x8a1804ed, 0x00040200, 0xa604b000, 0x00004e8e, 0x00004770, 0x6801480d, 0x43112203,
+ 0x480c6001, 0x61412140, 0x480b0401, 0x04816381, 0x21006381, 0x48096001, 0x04d26b01, 0x63014311,
+ 0x68014807, 0x00490849, 0x20016001, 0x00004770, 0x400fc080, 0x400d8000, 0x400d9000, 0x400d8180,
+ 0x402e0140, 0x08220000, 0x06180816, 0x0612041e, 0x050d060e, 0x0216040d, 0x06180000, 0x060c0416,
+ 0x0312021e, 0x01210216, 0x0116020d, 0x402a8000, 0x33221100, 0x77665544, 0xbbaa9988, 0xffeeddcc,
+ 0x0818045a, 0x24ff3008, 0x00000000, 0x00000000, 0x0918055a, 0x25ff3108, 0x00000000, 0x00000000,
+ 0x0a18065a, 0x26ff3208, 0x00000000, 0x00000000, 0x2403049f, 0x00000000, 0x00000000, 0x00000000,
+ 0x0760079f, 0x27040b20, 0x00000000, 0x00000000, 0x8760879f, 0xa7048b20, 0x00000000, 0x00000000,
+ 0x0818045a, 0x24ff3008, 0x00000000, 0x00000000, 0x8b20075a, 0x0000a7ff, 0x00000000, 0x00000000,
+ 0x0818045a, 0x24ff3008, 0x00000000, 0x00000000, 0x0a18065a, 0x000026ff, 0x00000000, 0x00000000,
+ 0x0b18075a, 0x000027ff, 0x00000000, 0x00000000, 0x8a18065a, 0x0000a6ff, 0x00000000, 0x00000000,
+ 0x8b20075a, 0x0000a7ff, 0x00000000, 0x00000000, 0x00000000, 0x40184000, 0x40188000, 0x4018c000,
+ 0x40190000, 0x40194000, 0x40198000, 0x4019c000, 0x401a0000, 0x0014ff80, 0x00160015, 0x00180017,
+ 0x001a0019, 0xffff001b, 0x001c0518, 0x0118000c, 0x03060302, 0x060e051a, 0x017d7840, 0x02faf080,
+ 0x05f5e100, 0x07735940, 0x00000000, 0x00000000, 0x00000000, 0x412000d1, 0x60002000, 0x00000000,
+ 0x00000000, 0x60001020, 0x60001000, 0x00000000, 0x00000000, 0x60000000, 0x00800000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x11b3dc40, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000
+};
+
+// Start address of flash
+static const uint32_t flash_start = 0x60000000;
+// Size of flash
+static const uint32_t flash_size = 0x00800000;
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x60000000, 0x00001000},
+ };
+
+static const program_target_t flash = {
+ 0x20000b01, // Init
+ 0x200015ff, // UnInit
+ 0x20000abd, // EraseChip
+ 0x20000ae1, // EraseSector
+ 0x20001399, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x200046a8,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(RT1020_S25LP064A_flash_prog_blob), // prog_blob size
+ RT1020_S25LP064A_flash_prog_blob, // address of prog_blob
+ 0x00000100 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/mimxrt1020_spi_flash/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/mimxrt1020_spi_flash/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,38 @@
+/**
+ * @file target.c
+ * @brief Target information for the i.MXRT1020
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x60000000,
+ .flash_regions[0].end = 0x60000000 + MB(64),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20000000 + MB(64),
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/mimxrt1050_hyper_flash/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/mimxrt1050_hyper_flash/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,498 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the i.MXRT1050 HyperFlash
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t RT1050_IS26KS512S_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x4605b570, 0x4616460c, 0xcc0fe002, 0x3e10c50f, 0xd2fa2e10, 0xd3022e08, 0xc503cc03, 0x2e043e08,
+ 0xcc01d307, 0x1f36c501, 0x7821e003, 0x1c647029, 0x1e761c6d, 0xbd70d2f9, 0x4770ba40, 0x4770ba40,
+ 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770bac0, 0x4770bac0, 0x4770bac0,
+ 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x2000b510, 0xf906f000, 0x46c046c0, 0xf0002001,
+ 0xbd10f8fb, 0xb5104603, 0x079b430b, 0x2a04d10f, 0xc808d30d, 0x1f12c910, 0xd0f842a3, 0xba21ba18,
+ 0xd9014288, 0xbd102001, 0x43c02000, 0x2a00bd10, 0x07d3d003, 0x1c52d003, 0x2000e007, 0x7803bd10,
+ 0x1c40780c, 0x1b1b1c49, 0x7803d107, 0x1c40780c, 0x1b1b1c49, 0x1e92d101, 0x4618d1f1, 0xe001bd10,
+ 0x1f09c004, 0xd2fb2904, 0xd501078b, 0x1c808002, 0xd00007c9, 0x47707002, 0xd00b2900, 0xd00207c3,
+ 0x1c407002, 0x29021e49, 0x0783d304, 0x8002d502, 0x1e891c80, 0x2200e7e3, 0x2200e7ee, 0x2200e7df,
+ 0x428b0903, 0x0a03d32c, 0xd311428b, 0x469c2300, 0x4603e04e, 0xd43c430b, 0x08432200, 0xd331428b,
+ 0x428b0903, 0x0a03d31c, 0xd301428b, 0xe03f4694, 0x428b09c3, 0x01cbd301, 0x41521ac0, 0x428b0983,
+ 0x018bd301, 0x41521ac0, 0x428b0943, 0x014bd301, 0x41521ac0, 0x428b0903, 0x010bd301, 0x41521ac0,
+ 0x428b08c3, 0x00cbd301, 0x41521ac0, 0x428b0883, 0x008bd301, 0x41521ac0, 0x428b0843, 0x004bd301,
+ 0x41521ac0, 0xd2001a41, 0x41524601, 0x47704610, 0x0fcae05d, 0x4249d000, 0xd3001003, 0x40534240,
+ 0x469c2200, 0x428b0903, 0x0a03d32d, 0xd312428b, 0x018922fc, 0x0a03ba12, 0xd30c428b, 0x11920189,
+ 0xd308428b, 0x11920189, 0xd304428b, 0xd03a0189, 0xe0001192, 0x09c30989, 0xd301428b, 0x1ac001cb,
+ 0x09834152, 0xd301428b, 0x1ac0018b, 0x09434152, 0xd301428b, 0x1ac0014b, 0x09034152, 0xd301428b,
+ 0x1ac0010b, 0x08c34152, 0xd301428b, 0x1ac000cb, 0x08834152, 0xd301428b, 0x1ac0008b, 0xd2d94152,
+ 0x428b0843, 0x004bd301, 0x41521ac0, 0xd2001a41, 0x46634601, 0x105b4152, 0xd3014610, 0x2b004240,
+ 0x4249d500, 0x46634770, 0xd300105b, 0xb5014240, 0x46c02000, 0xbd0246c0, 0x20184901, 0xe7febeab,
+ 0x00020026, 0xf000b510, 0xf000f80b, 0xbd10f802, 0xb5104770, 0xd0012800, 0xffeef7ff, 0x0000bd10,
+ 0x2100b510, 0xf000a002, 0x2001f813, 0x0000bd10, 0x41474953, 0x3a545242, 0x6e624120, 0x616d726f,
+ 0x6574206c, 0x6e696d72, 0x6f697461, 0x0000006e, 0x4605b570, 0x200a460c, 0x1c6de000, 0xf812f000,
+ 0xd0062d00, 0x28007828, 0xe002d1f7, 0xf0001c64, 0x2c00f809, 0x7820d002, 0xd1f72800, 0xf000200a,
+ 0xbd70f801, 0x4669b508, 0x20037008, 0xbd08beab, 0x06c00a02, 0x0ec0b510, 0xd9012a07, 0xfea8f7ff,
+ 0x00924b05, 0x681318d2, 0x40842403, 0x408143a3, 0x6013430b, 0x0000bd10, 0x400fc068, 0x4d08b570,
+ 0x444d2400, 0x04a24907, 0x20004449, 0xfcd3f001, 0x28006068, 0x1c64d102, 0xdbf32c04, 0x0000bd70,
+ 0x00000004, 0x0000005c, 0x49050102, 0x0912b510, 0x20004449, 0xfcbff001, 0x44494902, 0xbd106048,
+ 0x0000005c, 0x00000004, 0x2000b57c, 0x43c04914, 0x62c86288, 0x63486308, 0x63c86388, 0x31404910,
+ 0x49106008, 0x094068c8, 0x300e0140, 0xf00060c8, 0xf002fc9b, 0x480cfc37, 0x490c2500, 0x466a9000,
+ 0x95014449, 0xf0024628, 0x4c09f9a5, 0x444c4907, 0x44496060, 0xf0012000, 0x6060fce8, 0xbd7c7025,
+ 0x400fc040, 0x40080000, 0xe0233008, 0x0000005c, 0x00000004, 0xb5104805, 0x68414448, 0xd0032900,
+ 0xf0004803, 0xbd10f96f, 0xfe32f7ff, 0x0000025c, 0x40184000, 0xf7ffb510, 0xbd10ffed, 0xb5104805,
+ 0x68814448, 0xd0032900, 0xf0004803, 0xbd10f95b, 0xfe1ef7ff, 0x0000025c, 0x40188000, 0xf7ffb510,
+ 0xbd10ffed, 0xb5104805, 0x68c14448, 0xd0032900, 0xf0004803, 0xbd10f947, 0xfe0af7ff, 0x0000025c,
+ 0x4018c000, 0xf7ffb510, 0xbd10ffed, 0xb5104805, 0x69014448, 0xd0032900, 0xf0004803, 0xbd10f933,
+ 0xfdf6f7ff, 0x0000025c, 0x40190000, 0xf7ffb510, 0xbd10ffed, 0xb5104805, 0x69414448, 0xd0032900,
+ 0xf0004803, 0xbd10f91f, 0xfde2f7ff, 0x0000025c, 0x40194000, 0xf7ffb510, 0xbd10ffed, 0x460cb510,
+ 0x29006989, 0x2141d103, 0xf0000549, 0x2000f887, 0x20026120, 0x73603420, 0xb510bd10, 0x2103460c,
+ 0xf0000589, 0x2000f87b, 0x34206060, 0xbd107320, 0x460bb510, 0x079a6a81, 0x00890889, 0x430a0f92,
+ 0x69416282, 0x00490fda, 0x07d20849, 0x490b430a, 0x400a4c0a, 0x43e44619, 0x43114021, 0x03a42401,
+ 0x43a1461a, 0x430a4022, 0x43116941, 0xf0006141, 0x4018f8d1, 0x4802d000, 0x0000bd10, 0xbfe0ffff,
+ 0x0000051a, 0x461eb5f8, 0x000c4617, 0xd0264605, 0x46202130, 0xfde1f7ff, 0x46202102, 0x73413020,
+ 0x73012100, 0x62a66267, 0x21106ae8, 0x62e84388, 0xf0004628, 0x4a0bf871, 0x444a0081, 0x490a5054,
+ 0x44790040, 0x28005e08, 0x06c2db08, 0x21010ed2, 0x09404091, 0x00804a05, 0x60011880, 0xf7ffbdf8,
+ 0x0000fd67, 0x0000025c, 0x00002eb6, 0xe000e100, 0x6ac1b510, 0x0f490549, 0x6941d1fb, 0xd5fc0249,
+ 0x61812100, 0xf848f000, 0x00404903, 0x5e084479, 0xf7ff2100, 0xbd10fe9d, 0x00002e7e, 0x23c06902,
+ 0x021b400b, 0x6102439a, 0x078b6a82, 0x439a0d9b, 0x0a096282, 0x02096982, 0x6182438a, 0x69024770,
+ 0x400b23c0, 0x431a021b, 0x6a826102, 0x0d9b078b, 0x6282431a, 0x69820a09, 0x430a0209, 0x47706182,
+ 0x2800b510, 0x21e1d00a, 0x60010249, 0x71012100, 0x71817141, 0x720171c1, 0xbd107241, 0xfd18f7ff,
+ 0x22c06901, 0x40110a09, 0x69806a82, 0x0f920592, 0x4310430a, 0x00004770, 0xb5104a08, 0x20004601,
+ 0x0083447a, 0x428b58d3, 0x1c40d003, 0xd3f82808, 0x2808e001, 0xf7ffd301, 0xbd10fcfb, 0x00002db4,
+ 0x5c40202d, 0xd0072802, 0xd0072a00, 0x69096948, 0x60101a40, 0x47702000, 0x47702006, 0x47702004,
+ 0x8c0a8c48, 0x8c084290, 0x69cad901, 0x8c491880, 0x47701a40, 0x5c40202c, 0xd0072800, 0xd0072a00,
+ 0x68496888, 0x60101a40, 0x47702000, 0x47702006, 0x47702004, 0x6a806941, 0x0c0022c3, 0x43084010,
+ 0x47704770, 0x4605b5f8, 0x460c6940, 0xd50d0300, 0x466969e8, 0x78087008, 0x70081c40, 0x2e006a66,
+ 0x4a5ed004, 0x46284621, 0x47b06aa3, 0x02816968, 0x30204620, 0x29009000, 0x69a8da71, 0xd56e0280,
+ 0x01406ae8, 0xe0260f46, 0x42b06920, 0x6920d201, 0x4630e000, 0xb2c168e2, 0xe0022000, 0x541369eb,
+ 0x460b1c40, 0xd3f94288, 0x184068e0, 0x692060e0, 0x61201a40, 0xb2c61af0, 0x28006920, 0x9800d10b,
+ 0x73412102, 0x2f006a67, 0x4a44d005, 0x1f924621, 0x6aa34628, 0x2e0047b8, 0x6920d002, 0xd1d32800,
+ 0x280069a0, 0xe032d12d, 0x46284621, 0xf926f000, 0xd0082800, 0x2f006a67, 0x4a38d005, 0x1e524621,
+ 0x6aa34628, 0x462147b8, 0xf0004628, 0x2800f917, 0x8c60d009, 0x1c4069e1, 0xd1014288, 0xe0012000,
+ 0x1c408c60, 0x69e88460, 0x69a18c22, 0x8c205488, 0x1c4069e1, 0xd1014288, 0xe0012000, 0x1c408c20,
+ 0x46308420, 0xb2f61e76, 0xd1cd2800, 0x6920e007, 0xd1042800, 0x05492141, 0xf7ff4628, 0x6968feef,
+ 0xd5390200, 0x020069a8, 0x6ae8d536, 0x05402104, 0x1a080f40, 0xe02ab2c6, 0x42b06860, 0x6860d201,
+ 0x4630e000, 0xb2c16822, 0xe0022000, 0x61eb5c13, 0x460b1c40, 0xd3f94288, 0x18406820, 0x68606020,
+ 0x60601a40, 0xb2c61af0, 0x28006860, 0x9900d10f, 0x69a87308, 0x05c92101, 0x61a84388, 0x2f006a67,
+ 0x4a06d005, 0x1fd24621, 0x6aa34628, 0x2e0047b8, 0x6860d002, 0xd1cf2800, 0x0000bdf8, 0x0000051d,
+ 0xb086b5f7, 0x4604000f, 0x6838d009, 0x28009005, 0x79b8d005, 0xd8022804, 0x280479f8, 0xf7ffd901,
+ 0x9805fbe7, 0x20009000, 0x25049001, 0x99059002, 0x43699808, 0xfc33f7ff, 0x0c360406, 0x2601d100,
+ 0x43714629, 0xf7ff9808, 0x9905fc2a, 0x1c701a41, 0x46299103, 0x43419004, 0xf7ff9808, 0x9905fc20,
+ 0x99031a08, 0xd2024288, 0x98049003, 0x9900b286, 0x42889803, 0x4669d801, 0x1c6dc161, 0xd9d62d20,
+ 0x98052164, 0xfc0bf7ff, 0x18410041, 0x42819800, 0x4830d202, 0xbdf0b009, 0xf7ff4620, 0x0041fe9d,
+ 0x4478482d, 0x21035e40, 0xfcf2f7ff, 0x210369a0, 0x43880489, 0x692061a0, 0x1f099901, 0xd2022904,
+ 0x04492101, 0x211f4308, 0x43880609, 0x1e499901, 0x08c906c9, 0x0b484301, 0x03409902, 0x0cc904c9,
+ 0x61214301, 0x21016920, 0x43880749, 0x69a06120, 0x43882110, 0x69a061a0, 0x00800880, 0x69a061a0,
+ 0x43087939, 0x692061a0, 0x03492101, 0x79794388, 0x0c8907c9, 0x61214301, 0x79b979f8, 0x43080400,
+ 0x6aa062e0, 0x43082188, 0x6aa062a0, 0x03892103, 0x62a04308, 0x7a3969a0, 0xd0022900, 0x04c92101,
+ 0x7a794308, 0xd0022900, 0x04892101, 0x61a04308, 0xe79f2000, 0x00000521, 0x00002b28, 0x460cb510,
+ 0xfe5ef7ff, 0x1e4969e1, 0xd1014288, 0xbd102001, 0xbd102000, 0x6ac3e006, 0x0f5b015b, 0x69c3d0fb,
+ 0x1c49700b, 0xd2f61e52, 0x00004770, 0x460cb5ff, 0x3120b083, 0x7b499100, 0x29034617, 0x69a1d013,
+ 0x687d2600, 0xd0322900, 0x8110f3ef, 0xb6729101, 0xf7ff4621, 0x2800fe35, 0x4285d01b, 0x4628d200,
+ 0x21001a2d, 0x481ae013, 0xbdf0b007, 0x69a28c63, 0x683b5cd2, 0x8c62559a, 0x1c5269e3, 0x429a1c76,
+ 0x2200d101, 0x8c62e001, 0x84621c52, 0x42811c49, 0x2d00d3ec, 0x6838d007, 0x60e01980, 0x61656125,
+ 0x21039800, 0x98017341, 0x8810f380, 0x6811e00a, 0x612560e1, 0x9a006165, 0x73512103, 0x05492141,
+ 0xfdadf7ff, 0x28009806, 0x6006d000, 0xe7cb2000, 0x00000515, 0x460bb510, 0x7b1c3320, 0xd00c2c01,
+ 0x600c6814, 0x604c6854, 0x608a6852, 0x73192101, 0xf7ff05c9, 0x2000fd94, 0x4801bd10, 0x0000bd10,
+ 0x00000514, 0xb084b5f7, 0xd00d000f, 0x90012000, 0x97002404, 0x46399002, 0x98064361, 0xfb0ff7ff,
+ 0x0c2d0405, 0xe002d002, 0xfab2f7ff, 0x46212501, 0x98064369, 0xfb03f7ff, 0x1c681bc6, 0x43414621,
+ 0x98069003, 0xfafbf7ff, 0x42b01a38, 0x4606d202, 0xb2859803, 0x42869800, 0x9600d802, 0x94019502,
+ 0x2c201c64, 0x2164d9d7, 0xf7ff4638, 0x0041fae8, 0x98001841, 0xd9254281, 0x69819804, 0x22036980,
+ 0x43900492, 0x61909a04, 0x69009804, 0x1f129a01, 0xd2022a04, 0x04522201, 0x221f4310, 0x43900612,
+ 0x1e529a01, 0x08d206d2, 0x0b504302, 0x03409a02, 0x0cd204d2, 0x98044302, 0x98046102, 0x20006181,
+ 0xbdf0b007, 0xe7fb4800, 0x00000521, 0x2900b510, 0x2a00d00b, 0x61cbd008, 0x2200618a, 0x844a840a,
+ 0x05492141, 0xfd1bf7ff, 0xf7ffbd10, 0xb510fa51, 0xd004000c, 0x5d09212d, 0xd0022902, 0xf7ffe005,
+ 0x2141fa47, 0xf7ff0549, 0x2000fcf9, 0x61e061a0, 0x84608420, 0xe005bd10, 0x021b6943, 0x780bd5fc,
+ 0x1c4961c3, 0xd2f71e52, 0x00004770, 0x4d18b570, 0x46160104, 0x444d0924, 0x2001d007, 0x42840340,
+ 0x7828d11d, 0xd0072800, 0x4912e019, 0x42886830, 0x2001d115, 0xe0127028, 0x22004b0f, 0x4619444b,
+ 0xf0014610, 0x4b0af8da, 0x444b490b, 0x60682201, 0x03123308, 0x20004449, 0xf8cff001, 0x49066068,
+ 0x46224633, 0x20004449, 0xf8c7f001, 0xbd706068, 0x00000004, 0x42464346, 0x0000005c, 0x47702000,
+ 0x4613b570, 0x460a460d, 0x46014604, 0xf7ff4618, 0x2800f9f9, 0x2000d001, 0x1960bd70, 0xb5f8bd70,
+ 0xb28b0c04, 0xb2824626, 0x0c0d435e, 0x0c374610, 0x04364358, 0x21001980, 0x46164179, 0x0c37436e,
+ 0x19800436, 0x46264179, 0x1989436e, 0xb430bdf8, 0x1e644674, 0x1c647825, 0xd20042ab, 0x5d63461d,
+ 0x18e3005b, 0x4718bc30, 0x494db5f8, 0x24016b08, 0x0f800240, 0x6a084084, 0x07404d4a, 0x68280fc2,
+ 0x03c14f4a, 0xd57d4848, 0xd0012a00, 0xe0002158, 0x23092142, 0x18c9035b, 0x68296029, 0xdafc2900,
+ 0x23016b29, 0x4399031b, 0x6b296329, 0xdafc2900, 0x6809493f, 0x23034e3f, 0x02db4031, 0x4b3e18c9,
+ 0x4b3b4319, 0x21036019, 0x61290309, 0x29006929, 0x6929dafc, 0x041b2301, 0x61294399, 0x3b404b34,
+ 0x40316b19, 0x02362623, 0x4e341989, 0x63194331, 0x21014e33, 0x2a006131, 0x4638d000, 0xf7ff4621,
+ 0x4930f9ce, 0x44492701, 0x90006008, 0x1c7fe000, 0x98004639, 0xf9c3f7ff, 0x4288492b, 0x6970d8f7,
+ 0x2207492a, 0x1e794008, 0x0b490749, 0x02a14308, 0x18890292, 0x0cc904c9, 0x02394308, 0x390139ff,
+ 0x0d890589, 0x61704308, 0x09c06a70, 0x1cc001c0, 0x69b06270, 0x04892103, 0x61b04308, 0x491c69f0,
+ 0x21034008, 0x18400749, 0x4308491a, 0x682961f0, 0x04002001, 0x60294381, 0x43816b29, 0x69296329,
+ 0xe0004381, 0x6129e001, 0x2a00bdf8, 0x4638d000, 0xf7ff4621, 0x490bf984, 0x60084449, 0x0000bdf8,
+ 0x401f4440, 0x400d8000, 0x179a7b00, 0x1f78a400, 0x400d8100, 0xc0c0c0c0, 0x18131818, 0x0f1a2323,
+ 0x400fc000, 0x0000004c, 0x08954400, 0xfff8e0ff, 0x9c7fff80, 0x03800001, 0x4614b5f8, 0x4607000d,
+ 0x2c01d024, 0x6c28d822, 0x0fc60640, 0xf0014638, 0x4621fde3, 0x34ff462c, 0x290034c1, 0x7a20d017,
+ 0xd0092800, 0x5d412046, 0x46384632, 0xf83af000, 0x46384629, 0xfa4ef000, 0x28007ba0, 0x2100d003,
+ 0xf0004638, 0x4638fca5, 0xf811f000, 0x7a21bdf8, 0xd0072900, 0x46384632, 0xf824f000, 0x46384629,
+ 0xfa38f000, 0x28007ba0, 0x2101d0ed, 0xb510e7e8, 0xfc66f000, 0xd0012800, 0xfd6ff001, 0xb510bd10,
+ 0xfc5ef000, 0xd00b2800, 0x23012100, 0x008a07db, 0x32801812, 0x431c6814, 0x1c496014, 0xd3f62904,
+ 0x0000bd10, 0x460cb5f0, 0xb08b4922, 0x46064615, 0x44792214, 0xf7ff4668, 0x491ef873, 0x44792214,
+ 0xa8053108, 0xf86cf7ff, 0xd0012d00, 0xd12c2d01, 0x6b184b19, 0x09814f19, 0x018969f8, 0x05d22207,
+ 0x2d004390, 0xaa05d023, 0xd01e2c00, 0xd9002c09, 0x00642401, 0x18a25d15, 0x785206ac, 0x430c0ea4,
+ 0x220705d1, 0x188905d2, 0x09ad018d, 0x46304305, 0xf816f000, 0x42a06b18, 0x631cd000, 0x42a869f8,
+ 0x61fdd000, 0xf0004630, 0xb00bf815, 0x466abdf0, 0x0000e7da, 0x00002416, 0x400d80c0, 0x400fc000,
+ 0x68014803, 0x02922203, 0x60014391, 0x00004770, 0x400fc080, 0x68014803, 0x02922203, 0x60014311,
+ 0x00004770, 0x400fc080, 0x4605b5fe, 0x90002004, 0x4628460e, 0xfbe4f000, 0xd07d0004, 0xd0fc2e00,
+ 0x28037830, 0x7c30d878, 0x27009001, 0xf0014620, 0x4628fd2d, 0xff73f7ff, 0x211e6960, 0x61604308,
+ 0x35804625, 0x62286870, 0x28027830, 0x2803d002, 0xe003d002, 0xe0008b30, 0xb2878c30, 0x7a307b31,
+ 0x07001e49, 0x0b000749, 0x43080949, 0x07c99901, 0x43384308, 0x78306268, 0xd1502803, 0x6a3069f1,
+ 0xd149078b, 0x469e2340, 0x221c6bab, 0x43bb273c, 0x63aa431a, 0x22016bab, 0x63ab4313, 0x07db6bab,
+ 0x6b2bd1fc, 0x632b4313, 0x1de2e035, 0x32f94673, 0x4570089b, 0x6967d30a, 0xd40206bf, 0xca80e028,
+ 0x1e5bc180, 0x4672d2fb, 0xe01d1a80, 0x061b6f2b, 0xd1030e1b, 0xca08e01c, 0xc1081f00, 0xd2fa2804,
+ 0xd0102800, 0x92016812, 0x4694aa01, 0x2300460a, 0x4667e007, 0x7017783f, 0x1c7f4667, 0x46bc1c52,
+ 0x42831c5b, 0x2000d3f5, 0x23206962, 0x6162431a, 0x07126962, 0xe000d403, 0x2800e05f, 0x7830d1c5,
+ 0xd0012802, 0xd1412801, 0x69b26971, 0xd1540788, 0x46842040, 0x201c6beb, 0x43bb273c, 0x63e84318,
+ 0x20016beb, 0x63eb4303, 0x07db6beb, 0x6b2bd1fc, 0x632b4303, 0x4620e028, 0x696330ff, 0x065b3081,
+ 0x4663d51f, 0x4562089b, 0xe014d202, 0xc080c980, 0xd2fb1e5b, 0x1a124660, 0x2a04e00f, 0xc980d903,
+ 0x1f12c080, 0x2a00e007, 0xc980d003, 0xc0802200, 0x2700e001, 0x1e5bc080, 0x6960d2ef, 0x43182340,
+ 0x69606160, 0xd4010700, 0xd1d42a00, 0x28007830, 0x6b28d103, 0x43082101, 0x46206328, 0xfc66f001,
+ 0x07006960, 0x6e68d50b, 0x0f000100, 0xd001280e, 0xe0014804, 0x1e404803, 0x98009000, 0x2000bdfe,
+ 0x0000e7fa, 0x00001771, 0xb5104602, 0x2a002004, 0x2900d021, 0x2044d01f, 0x28015c40, 0x68d0d10c,
+ 0x005b0843, 0x43032040, 0xf0004608, 0x2800fcd3, 0x2001d001, 0x60d34303, 0x212068d0, 0x60d04308,
+ 0x20004b05, 0x18890081, 0x401c6a0c, 0x1c40620c, 0xd3f72803, 0xbd102000, 0xfcf0ff00, 0xb087b5f3,
+ 0x2504460c, 0xf0009807, 0x9002facb, 0xd0542800, 0xd0522c00, 0x30404620, 0x90054627, 0x26003750,
+ 0x304130ff, 0x68389001, 0x0a8100b2, 0x18109802, 0x66019000, 0x1d3f7ba0, 0x7b6006c5, 0x06c00eed,
+ 0x43050d80, 0x07007be0, 0x43050c40, 0xf0004620, 0x2800fc98, 0x2001d002, 0x43050280, 0x28006f60,
+ 0xaa03d00d, 0x98072101, 0xfa60f000, 0x6f612301, 0x9a03a804, 0xfa9ef000, 0x04009804, 0x98004305,
+ 0x98056705, 0x280079c0, 0x9801d00e, 0x07417c00, 0x9901d00a, 0x7c490342, 0x07092007, 0x03400d09,
+ 0xb2801810, 0xe0014308, 0x02002009, 0x31809900, 0x1c766008, 0xd3b62e04, 0x46282500, 0xbdf0b009,
+ 0x460db57f, 0xf0004606, 0x0004fa6b, 0x2d00d02c, 0xaa02d02a, 0x46302101, 0xfa28f000, 0x2100aa03,
+ 0xf0004630, 0x2501fa23, 0x02ad4e10, 0x4631462b, 0x9a024668, 0xfa5ef000, 0x4631462b, 0x9a03a801,
+ 0xfa58f000, 0x9900480a, 0xd9004281, 0x99019000, 0xd9004281, 0x98009001, 0x04009901, 0x4308b289,
+ 0x20006060, 0xbd70b004, 0xe7fb2004, 0x1dcd6500, 0x0000ffff, 0xb085b5f3, 0x2404460e, 0xf0009805,
+ 0x0005fa2f, 0x2e00d07e, 0x7b30d07e, 0xd87b2803, 0xd00a2800, 0xd0082801, 0xd0062802, 0xd1042803,
+ 0xf0004630, 0x2800fbed, 0x20ffd002, 0xe0093001, 0x2101aa03, 0xf0009805, 0x4935f9d9, 0x42889803,
+ 0x2079d303, 0x90019000, 0x2400e01e, 0x19800060, 0x8f073040, 0x43472064, 0x214bd01d, 0xf7fe4638,
+ 0x214bfebe, 0x42b94341, 0x1c40d200, 0x283f213f, 0x4608d900, 0x0c410680, 0x31ff00a2, 0x46683101,
+ 0x50811c64, 0xd3e12c02, 0x22026828, 0x28000780, 0x2000da1c, 0x4630e01e, 0xfbb9f000, 0x46024607,
+ 0x9805a902, 0xf9d0f000, 0x9902481a, 0xd0092f00, 0xfe95f7fe, 0x217d0880, 0x434800c9, 0xf7fe214b,
+ 0xe7d2fe8e, 0xfe8bf7fe, 0xe7f40840, 0x20016829, 0x60294311, 0x29006d31, 0x6d71d102, 0xd0022900,
+ 0x9b0021c0, 0x6db1514b, 0xd1022900, 0x29006df1, 0x21c4d002, 0x514b9b01, 0xd0022800, 0x43906828,
+ 0xe0006028, 0x2400e000, 0xb0074620, 0x0000bdf0, 0x05f5e100, 0x3b9aca00, 0xb08ab5f7, 0x2604460d,
+ 0xf000980a, 0x0007f99d, 0x2d00d053, 0x2001d051, 0x70084669, 0x9001980c, 0x74082000, 0x24002004,
+ 0x00a09006, 0x46101942, 0x78413020, 0xd03d2900, 0x025b2301, 0x059b59db, 0xd0030f9b, 0x7f5b192b,
+ 0xd0332b02, 0x78009102, 0x92053230, 0x22009003, 0x9b0c4629, 0xf000980a, 0x2800f90c, 0x9802d12a,
+ 0x01002101, 0x32801942, 0x980a9b03, 0xfa82f001, 0x90022001, 0x980a4669, 0xfd76f7ff, 0xd1190006,
+ 0x28008a68, 0x1929d10e, 0x29027f49, 0x2903d00a, 0x2200d008, 0x9b0c4629, 0xf000980a, 0x0006f80d,
+ 0xe003d108, 0x43482164, 0xfb4cf001, 0x2c031c64, 0x4630d3b7, 0xbdf0b00d, 0x2004b5ff, 0x460cb08f,
+ 0xd04b2900, 0x900e2000, 0x30404620, 0x21018f82, 0x4095460d, 0x93028fc2, 0x22039200, 0x711a466b,
+ 0x91039104, 0x9108a90c, 0x29009911, 0x2108d001, 0x2104e000, 0x99119109, 0x79c07519, 0xd0092800,
+ 0x30ff4620, 0x79013081, 0xd0032900, 0x91037941, 0x90047900, 0x21029803, 0x19020100, 0x9b043280,
+ 0xf001980f, 0x2002fa27, 0x6f209003, 0xd0022800, 0xfb3ef001, 0x6f20900e, 0xd0112800, 0xfb38f001,
+ 0x1a40990e, 0xfaf4f001, 0x6f23217d, 0x434b00c9, 0x46112200, 0x41911a18, 0x481ad202, 0xbdf0b013,
+ 0x980fa901, 0xfd00f7ff, 0xd1f72800, 0x29009911, 0xa90ad019, 0xaa0cab0b, 0x78172608, 0x7857700f,
+ 0x1c49701f, 0x1c5b1c92, 0xd1f61eb6, 0x9a0b9900, 0x990a2900, 0x4011d005, 0x438a462a, 0x2100d10e,
+ 0x4311e00d, 0x9900e007, 0xd0032900, 0x46299a0c, 0xe0014391, 0x4029990c, 0xd0002900, 0x29002101,
+ 0xe7cbd1b9, 0x00001772, 0xb089b5f0, 0x460c4616, 0x25044607, 0xf8b4f000, 0xd0472800, 0xd0452c00,
+ 0x30ff30ff, 0x68003002, 0x0f800580, 0x7c60d002, 0xd0252802, 0x46692501, 0x9601700d, 0x90027d60,
+ 0x90037d20, 0x74082000, 0x30184620, 0x20049005, 0x46339006, 0x46212200, 0xf0004638, 0x9802f82a,
+ 0x01002101, 0x46381902, 0x9b033280, 0xf9a2f001, 0x46384669, 0xf7ff9502, 0x0005fc97, 0xe001d116,
+ 0xe0132500, 0x29008a61, 0x7c60d10c, 0xd0092802, 0xd0072803, 0x22004633, 0x46384621, 0xff2cf7ff,
+ 0xe0034605, 0x43482064, 0xfa6cf001, 0xb0094628, 0xb570bdf0, 0x20044604, 0x2900b08a, 0x2000d024,
+ 0x7030466e, 0x25012003, 0x95039002, 0x20477432, 0x5c409301, 0xd0092800, 0x30ff4608, 0x7a023081,
+ 0xd0032a00, 0x92027a42, 0x90037a00, 0x9b039802, 0x18420100, 0x46202101, 0xf0013280, 0x4669f95b,
+ 0x95024620, 0xfc50f7ff, 0xbd70b00a, 0x4616b570, 0x20004a11, 0x6812444a, 0x46044d10, 0xd0052900,
+ 0xd0082901, 0x60302404, 0xbd704620, 0x05806968, 0x46100f81, 0x69e8e00c, 0x6b004809, 0x0e890681,
+ 0xf7fe4808, 0x2112fcdc, 0x69e94348, 0x0f490189, 0xf7fe1c49, 0xe7e6fcd4, 0x0000004c, 0x400fc000,
+ 0x400d80c0, 0x1c9c3800, 0x20044603, 0xd1042b01, 0xd0022900, 0x60084801, 0x47702000, 0x09e4f580,
+ 0x20004601, 0xd1022900, 0x44784801, 0x47706800, 0x00001ba6, 0x4607b5f8, 0x461d2004, 0x2f00460e,
+ 0x4611d012, 0xf7fe4809, 0x4601fcaa, 0x43694604, 0xf7fe4630, 0xe000fca4, 0x46011c40, 0x43694361,
+ 0xd3f942b1, 0x20006038, 0x0000bdf8, 0x3b9aca00, 0x460db570, 0xffd4f7ff, 0xd00a0004, 0xf926f001,
+ 0x02c02001, 0x2d006821, 0x4301d001, 0x4381e000, 0xbd706021, 0xb087b5f3, 0x2604460d, 0xf7ff9807,
+ 0x0004ffbf, 0x2d00d07e, 0x7c28d0fc, 0xd1022800, 0x28007f28, 0x6c28d009, 0xd40406c0, 0xf0004628,
+ 0x2800f986, 0x2001d001, 0x2000e000, 0x49619003, 0x42886828, 0x9807d166, 0xfba2f7ff, 0x98074629,
+ 0xf8bef000, 0x30404628, 0x90029903, 0xd0022900, 0x21012200, 0x4628e005, 0xf969f000, 0x98024602,
+ 0x98077981, 0xfb3ef7ff, 0xf7ff9807, 0x6820fb93, 0x43b02602, 0x46206020, 0xf88ff001, 0x43306820,
+ 0x68206020, 0x4008494c, 0x79499902, 0xd1012908, 0x43080289, 0x43084949, 0x07897b29, 0x43010e89,
+ 0x46296021, 0xf7ff9807, 0x68a0fcfb, 0x03c92101, 0x60a04388, 0xf0004628, 0x2800f941, 0x68a0d004,
+ 0x04c92101, 0x60a04308, 0x46204629, 0xfc5cf7ff, 0x98074629, 0xfc82f7ff, 0x98074629, 0xfd1af7ff,
+ 0x21026820, 0x60204388, 0xf0014620, 0x4628f856, 0x30507c29, 0x29009004, 0x9807d01c, 0x20049005,
+ 0xe0002100, 0x9e04e052, 0x460f9100, 0x9101ce02, 0xd00a2900, 0x9a004629, 0xf7ff9805, 0x2800fe75,
+ 0x9a01d106, 0x18899900, 0x1c7f9100, 0xd3ed2f04, 0xd13b0006, 0x28007f28, 0x9807d01c, 0x20049005,
+ 0xd0152d00, 0x9e042100, 0x460f9100, 0x9101ce02, 0xd00a2900, 0x9a004629, 0xf7ff9805, 0x2800fd6d,
+ 0x9a01d106, 0x18899900, 0x1c7f9100, 0xd3ed2f04, 0xd11b0006, 0x28009803, 0x6820d017, 0x43302602,
+ 0x46286020, 0xf8d3f000, 0x98024602, 0x98077981, 0xfaa8f7ff, 0x98074629, 0xfc82f7ff, 0x98074629,
+ 0xfcb8f7ff, 0x43b06820, 0x26006020, 0xb0094630, 0x0000bdf0, 0x42464346, 0x0000df0f, 0xffff0000,
+ 0x4d53b5fe, 0x462e4853, 0x460c9001, 0x46084637, 0xf8b9f000, 0xd0042800, 0x6ee06e26, 0x6e679001,
+ 0x46206ea5, 0x6d213040, 0x6d609000, 0xd0232900, 0xd0042800, 0x20064948, 0x484863c8, 0x6d2062c6,
+ 0xd0062800, 0x20014944, 0x62c83140, 0x30404843, 0x484161c6, 0x30402311, 0x49406303, 0x620f3140,
+ 0x63422201, 0x6382624d, 0x9800628d, 0x28047940, 0x2808d005, 0xe01bd003, 0xd1db2800, 0x4936e030,
+ 0x31402001, 0x493563c8, 0x62cd3140, 0x32804a32, 0x630d6010, 0x79529a00, 0xd1092a08, 0x32404a2e,
+ 0x610d6210, 0x60cd61d0, 0x608d6190, 0x604d6150, 0x28037b20, 0x2801d001, 0x4827d106, 0x62833040,
+ 0x98014926, 0x61883140, 0xf0004620, 0x2800f857, 0x4921d006, 0x31402001, 0x48206248, 0x61473040,
+ 0x28006da0, 0xd0216de0, 0xd0052800, 0x2006491a, 0x60083140, 0x63064819, 0x28006da0, 0x4816d005,
+ 0x30402104, 0x481560c1, 0x491363c6, 0x31402011, 0x4a126248, 0x61573240, 0x62082001, 0x61c86115,
+ 0x9b0060d5, 0x2b04795b, 0xe006d003, 0xd1dd2800, 0x6188bdfe, 0x61486095, 0x7b206055, 0xd0012803,
+ 0xd1f52801, 0x61082014, 0x60109801, 0x0000bdfe, 0x000010f1, 0x000130f1, 0x401f8180, 0x401f8380,
+ 0x07806c00, 0x2001d501, 0x20004770, 0x6c004770, 0xd5010640, 0x47702001, 0x47702000, 0x07c06c00,
+ 0x2001d000, 0x6c004770, 0xd5010680, 0x47702001, 0x47702000, 0x07406c00, 0x2001d501, 0x20004770,
+ 0x6c004770, 0xd5010700, 0x47702001, 0x47702000, 0xb08ab570, 0x20004605, 0x7030466e, 0x2401200f,
+ 0x94039002, 0x460a7432, 0x930132ff, 0x46233271, 0x46284621, 0xff0ef000, 0x46284669, 0xf7ff9402,
+ 0xb00afa03, 0xb5ffbd70, 0xb0812004, 0x2900460f, 0x463dd016, 0x358135ff, 0x46146c6e, 0x18b21e71,
+ 0x438c1e5b, 0x438e18d6, 0x4622e008, 0x98014639, 0xf881f000, 0xd1032800, 0x190c6c69, 0xd3f442b4,
+ 0xbdf0b005, 0xb08bb5f3, 0x46692000, 0x70089d0c, 0x91032101, 0x9102210b, 0x74084669, 0x5d402047,
+ 0xd0092800, 0x30ff4628, 0x7d013081, 0xd0032900, 0x91027d41, 0x90037d00, 0x990c2200, 0xf7ff980b,
+ 0x2600f90b, 0x46373550, 0xcd01950a, 0x28009009, 0x4633d01a, 0x990c2200, 0xf000980b, 0x0004fe86,
+ 0x9802d13e, 0x01019601, 0x9b03980c, 0x2101180a, 0x980b3280, 0xfeaef000, 0x90022001, 0x980b4669,
+ 0xf9a2f7ff, 0xd12b0004, 0x1c7f9809, 0x2f041836, 0x2c00d3db, 0x2000d124, 0x46069009, 0x9d0a980c,
+ 0x30c130ff, 0xcd80900a, 0xd0132f00, 0x9b092200, 0x980b990c, 0xfc30f7ff, 0xd1110004, 0x7bc0980a,
+ 0xd0072800, 0x9b092200, 0x980b990c, 0xfe2cf000, 0xd1050004, 0x1c769809, 0x900919c0, 0xd3e22e04,
+ 0xf7ff980b, 0x2201f8f4, 0x980b990c, 0xf8b4f7ff, 0xb00d4620, 0xb5f7bdf0, 0x4617b08a, 0x4608460d,
+ 0xff38f7ff, 0x22004606, 0x980a4629, 0xf8a4f7ff, 0x4632463b, 0x980a4629, 0xfe27f000, 0xd1390004,
+ 0x97014669, 0x20057008, 0x90022401, 0x740e9403, 0x5d402047, 0xd0092800, 0x30ff4628, 0x7b013081,
+ 0xd0032900, 0x91027b41, 0x90037b00, 0x21019802, 0x19420100, 0x9b033280, 0xf000980a, 0x4669fe3b,
+ 0x980a9402, 0xf930f7ff, 0xd1130004, 0x4632463b, 0x980a4629, 0xfbd0f7ff, 0xd10b0004, 0x30d020ff,
+ 0x28005d40, 0x463bd006, 0x46294632, 0xf000980a, 0x4604fdcb, 0xf7ff980a, 0x2201f89a, 0x980a4629,
+ 0xf85af7ff, 0xb00d4620, 0xb5f8bdf0, 0x4607460d, 0xfd30f7ff, 0xd11e0006, 0x3280462a, 0x46142301,
+ 0x46382100, 0xfe06f000, 0x30cd20ff, 0x28025d40, 0x7c68d003, 0xd00c2801, 0x4620e00d, 0xc80f3020,
+ 0x35104625, 0x4620c50f, 0xc80f3040, 0xc40f3430, 0x2000e001, 0x46307428, 0xb5ffbdf8, 0x4617b089,
+ 0x4608460d, 0xfeb6f7ff, 0x22004606, 0x98094629, 0xf822f7ff, 0x4632463b, 0x98094629, 0xfda5f000,
+ 0xd13f0004, 0x46692002, 0x20097008, 0x90022401, 0x20479403, 0x46285d41, 0x308130ff, 0xd0062900,
+ 0x29007c01, 0x7c41d003, 0x7c019102, 0x46699103, 0x740e9701, 0x9105990c, 0x90066c00, 0x21019802,
+ 0x19420100, 0x9b033280, 0xf0009809, 0x4669fdb3, 0x98099402, 0xf8a8f7ff, 0xd1130004, 0x4632463b,
+ 0x98094629, 0xfb48f7ff, 0xd10b0004, 0x30d020ff, 0x28005d40, 0x463bd006, 0x46294632, 0xf0009809,
+ 0x4604fd43, 0xf7ff9809, 0x2201f812, 0x98094629, 0xffd2f7fe, 0xb00d4620, 0x0000bdf0, 0xb089b5ff,
+ 0x9c122004, 0x4616461f, 0xd0222900, 0xd0202e00, 0xd01e2c00, 0xf7ff4608, 0x2103fe4d, 0x7011466a,
+ 0x91032101, 0x91022100, 0x4d0b7410, 0xd80042ac, 0x46694625, 0x96079701, 0x98099508, 0xf864f7ff,
+ 0xd1062800, 0x008908a9, 0x197f1b64, 0x2c00198e, 0xb00dd1eb, 0x0000bdf0, 0x0000ffff, 0x460cb5f7,
+ 0xb0a64958, 0x4f564615, 0x44792240, 0xf7fea815, 0x2000f867, 0x46269000, 0x36402004, 0x68287170,
+ 0x0f010300, 0x0f00d005, 0xd0062802, 0xd0092803, 0x2010e093, 0x20006420, 0x2050e002, 0x20036420,
+ 0xe0077320, 0x64202050, 0x73202003, 0x71702008, 0x90002001, 0x98264621, 0xff17f7ff, 0xd17c0007,
+ 0xa9156828, 0x0f000300, 0x18420100, 0x46192301, 0xf0009826, 0xa901fd1f, 0x98269a00, 0xfc54f000,
+ 0xd16a0007, 0xa901aa25, 0xf0004620, 0x2050fd77, 0x20036420, 0x46207320, 0x30804933, 0x49336301,
+ 0x88296101, 0x04092302, 0x1de10f0a, 0x2a0231f9, 0x2a03d002, 0xe050d027, 0x71722204, 0x0312682a,
+ 0xd10d0f12, 0x04922221, 0x4a2961a2, 0x4a296602, 0x22016642, 0x74637422, 0x75652506, 0x82627522,
+ 0x60024a25, 0x60424a25, 0x64024a25, 0x32154a22, 0x22336502, 0x630a0152, 0x3a094a1f, 0x4a21610a,
+ 0x4921614a, 0x2208e025, 0x682a7172, 0x0f120312, 0x2211d10d, 0x61a204d2, 0x66024a15, 0x66424a15,
+ 0x74222201, 0x25067463, 0x75227565, 0x4a178262, 0x4a176002, 0x4a176042, 0x4a146402, 0x65023215,
+ 0x0152223b, 0x4a11630a, 0x610a3a09, 0x614a4a12, 0x34ff4912, 0x620134c1, 0x46387323, 0xbdf0b029,
+ 0x00004e8d, 0x000014aa, 0x00000406, 0x24040405, 0x04000471, 0x00002003, 0x8a20060b, 0x0000a604,
+ 0x00000606, 0x0000a280, 0xa6040605, 0x8b20070b, 0x0000a704, 0x00000706, 0x0000a380, 0xa7040705,
+ 0x460fb5f7, 0x2103b088, 0x73f94638, 0x30402308, 0x23587143, 0x2401643b, 0x2a007339, 0x2159d001,
+ 0x71c46439, 0x8781210f, 0x463e87c4, 0x36ff2001, 0x36810240, 0x02406430, 0x46396470, 0xf7ff9808,
+ 0x2800fe54, 0x4862d139, 0x90002500, 0x95034861, 0x90012301, 0x466a9502, 0x98084619, 0xfc5af000,
+ 0x95039502, 0x485c4d5a, 0x90013580, 0x466a2301, 0x95002100, 0xf0009808, 0x2013fc4d, 0x900602c0,
+ 0xaa062302, 0x98084955, 0xfb50f000, 0xd1142800, 0xaa042308, 0x98082110, 0xfb34f000, 0xd10c2800,
+ 0x494f9805, 0x9005b280, 0x42889804, 0x2159d104, 0x02099805, 0xd0024288, 0xb00b484a, 0x2308bdf0,
+ 0x2127aa04, 0xf0009808, 0x2800fb1d, 0x9804d1f5, 0x0e000400, 0x38179004, 0xd8ed2809, 0x20019904,
+ 0x65384088, 0x0300200f, 0x23029006, 0x2100aa06, 0xf0009808, 0x2800fb1b, 0x463cd1df, 0x49363480,
+ 0x60616025, 0x4a394938, 0x34104b39, 0x4b39c40e, 0x60236065, 0x60a34b38, 0x60e34b38, 0x34144b34,
+ 0x4b37c40e, 0x602260a3, 0x4b366061, 0x4b3460e3, 0x61234625, 0x4b2e3554, 0x4b33c50e, 0x4b24602b,
+ 0x3b203414, 0x4b31606b, 0x4b2960ab, 0x4b30c40e, 0xc4083d1c, 0xc40e4b26, 0x60a34b29, 0x60616022,
+ 0x60e34b28, 0x61234b26, 0x462c4b19, 0x602b3b20, 0x606b4b28, 0x60ab4b28, 0x34304b1d, 0x4b24c40e,
+ 0x4b1b63eb, 0xc40e1d24, 0x656b4b1d, 0x652964ea, 0x65ab4b1c, 0x65eb4b1a, 0x6629666a, 0x66a94914,
+ 0x66e9491e, 0x72312102, 0x72722203, 0x22017131, 0x74317172, 0x74712109, 0x73312104, 0x73732305,
+ 0x210b7531, 0x757137ff, 0x733a37c1, 0x0000e775, 0x8b188720, 0xa3028f10, 0xa7048f10, 0x00000555,
+ 0x52005100, 0x00004e8d, 0x87008700, 0x87aa8700, 0x87058700, 0x87708700, 0xb70b8f10, 0x0000a704,
+ 0x87558700, 0x87028700, 0x87a08700, 0xa3808f10, 0x87808700, 0x87008f10, 0x00008730, 0x87108700,
+ 0x460cb5f7, 0xb09e4954, 0x22204616, 0xa8144479, 0xfe86f7fd, 0x03006830, 0xd00e0f00, 0x73202003,
+ 0x46272050, 0x37402108, 0x71796420, 0x981e4621, 0xfd4bf7ff, 0xd10b0005, 0x2000e003, 0x20107320,
+ 0x6830e7ef, 0x0f010300, 0x0f00d003, 0xd0032803, 0x2301e07e, 0xe001aa14, 0xaa182301, 0x981e2101,
+ 0xfb48f000, 0x71782008, 0x46692200, 0xf000981e, 0x0005fa7b, 0xaa1cd16c, 0x46204669, 0xfb9ef000,
+ 0x64202050, 0x73202003, 0x49344620, 0x63013080, 0x61014933, 0x46236832, 0x0f0f0311, 0x1de133ff,
+ 0x31f933c1, 0xd0062f03, 0x0f170412, 0xd0022f03, 0xd01a0f12, 0x4a2be04c, 0x4a2b6202, 0x4a2b6002,
+ 0x4a2b6042, 0x4a286402, 0x65023adc, 0x0152223b, 0x4a25630a, 0x610a3aeb, 0x614a4a26, 0x22026831,
+ 0x0f090309, 0xd0222900, 0x6d22e031, 0x06242401, 0xd30242a2, 0x228e2420, 0x2418e001, 0x9e1c22c2,
+ 0xb2f60424, 0x4f1c4326, 0x4c1c4322, 0x4322433e, 0x610a6506, 0x01d22247, 0x4a19614a, 0x4a136002,
+ 0x20236042, 0x63080140, 0x73982001, 0x2101e010, 0x74627421, 0x61a626e7, 0x75662606, 0x82617521,
+ 0x66014910, 0x3981490f, 0x490f6641, 0x731a6681, 0xb0214628, 0x0000bdf0, 0x000010c8, 0x00000406,
+ 0x24040405, 0xa7040705, 0x8b2007fd, 0x0000a704, 0x00000706, 0x0000a304, 0x08000400, 0x0b000400,
+ 0x8b2004fd, 0x04000481, 0x00002001, 0x460cb5f7, 0xb092494b, 0x22204615, 0xa8094479, 0xfdc0f7fd,
+ 0x26006828, 0x0f010300, 0x29002703, 0x0f00d005, 0xd0072803, 0xb0152004, 0x7326bdf0, 0x64202010,
+ 0xe0049708, 0x20507327, 0x20066420, 0x21089008, 0x55012045, 0x98124621, 0xfc77f7ff, 0xd1ea2800,
+ 0x03006828, 0xd0370f00, 0xaa0d2301, 0x98122101, 0xfa80f000, 0x96014668, 0x70077406, 0x48312601,
+ 0x44489602, 0x90079603, 0x98124669, 0xfd6cf7fe, 0xd1d02800, 0x4449492b, 0x2ac2780a, 0x682ad1cb,
+ 0x0f130312, 0xd01a4a28, 0x23027949, 0x408a3930, 0x46216522, 0x31ff2201, 0x31810312, 0x1112644a,
+ 0x7327640a, 0x64212150, 0x03096829, 0x46210f0a, 0x2a003180, 0xe012d005, 0xaa092301, 0x7889e7c6,
+ 0x7426e7e3, 0x82667463, 0x75622206, 0x4a177526, 0x660a61a3, 0x3a724a15, 0x4a15664a, 0x4a15668a,
+ 0x4a15600a, 0x4a15604a, 0x4a15630a, 0x4a15640a, 0x4a15610a, 0x4a15620a, 0x628a624a, 0x62ca4a14,
+ 0x32f91de2, 0x61154d13, 0x61554d13, 0x650d4d13, 0x654d4d13, 0x34ff4913, 0x631134c1, 0xe77a7323,
+ 0x00000f1c, 0x00000054, 0x00010000, 0x04000472, 0x20010400, 0x871187ee, 0xa7048b20, 0x00000406,
+ 0x87f98706, 0x24040405, 0x87fa8705, 0x87008700, 0x0000a704, 0x87ed8712, 0xa3048b20, 0x87de8721,
+ 0x00008b20, 0x879f8760, 0x2000b5f7, 0x460cb0b2, 0x25044616, 0x900c4941, 0x900e900d, 0x44792230,
+ 0x4668900f, 0xfcfcf7fd, 0x03006830, 0xd1720f00, 0x20044627, 0x71783740, 0x49394620, 0x60013080,
+ 0x60414938, 0x98324621, 0xfbbff7ff, 0xd1620005, 0x06007830, 0x28010f00, 0x1de0d10e, 0x30f94932,
+ 0x67416701, 0x67811409, 0x461a2300, 0x98324621, 0xfa9ef7ff, 0xd14e0005, 0x46696830, 0x0f000300,
+ 0x18420100, 0x46192301, 0xf0009832, 0x2200f9b3, 0x9832a91d, 0xf8e8f000, 0xd13c0005, 0xa9102003,
+ 0x20017008, 0x20009013, 0x74089012, 0xa8199011, 0x20109017, 0x98329018, 0xfc96f7fe, 0xd12a0005,
+ 0x9919481a, 0xd11f4281, 0x02402001, 0xa9109018, 0x98329417, 0xfc88f7fe, 0xd11c0005, 0x30ff4620,
+ 0x6c013081, 0xd0021c49, 0x1c406c40, 0x2101d113, 0x46200249, 0xfd21f7fd, 0x6020480c, 0x6060480c,
+ 0x71b82001, 0x65200600, 0xaa1d4633, 0x98324621, 0xfacaf000, 0x46284605, 0xbdf0b035, 0x00000d66,
+ 0x08180403, 0x00012404, 0x06ff06ff, 0x42464346, 0x56010400, 0x2604b5f7, 0x460c4615, 0xd04b2900,
+ 0xd0492d00, 0x462001f1, 0xfcf7f7fd, 0x46272101, 0x71b93740, 0x65200608, 0x60204820, 0x60604820,
+ 0x73602003, 0x20ff73a0, 0x550130c9, 0x02006828, 0x00030f00, 0xfabbf7fe, 0x0c060609, 0x1d301711,
+ 0x00302330, 0x4621462a, 0xf7ff9800, 0xe001ff3d, 0xe0032201, 0xd0180006, 0x2200e01e, 0x98004621,
+ 0xfc9ef7ff, 0x462ae7f6, 0x98004621, 0xfe6ef7ff, 0x462ae7f0, 0x98004621, 0xfda2f7ff, 0x462ae7ea,
+ 0x98004621, 0xfbbaf7ff, 0x4620e7e4, 0xf8f3f000, 0x07007828, 0x71b80f00, 0xbdfe4630, 0x42464346,
+ 0x56010400, 0xb089b530, 0x466d2403, 0x2501702c, 0x24000049, 0x91019503, 0x466d9402, 0x4669742c,
+ 0x92079308, 0xfbf0f7fe, 0xbd30b009, 0xb089b530, 0x466d2402, 0x2401702c, 0x91010049, 0x94039402,
+ 0x74292100, 0x93064669, 0xf7fe9205, 0xb009fbdd, 0xb5f0bd30, 0x20044607, 0x461db089, 0x460e4614,
+ 0xd00f2a00, 0x46682124, 0xfc77f7fd, 0x46692003, 0x20017008, 0x95089002, 0x96019003, 0x46389407,
+ 0xfbc2f7fe, 0xbdf0b009, 0xb098b5f7, 0x4d33460e, 0x466a2308, 0x98182100, 0xffdbf7ff, 0xd15a0004,
+ 0x9800492f, 0xd0014288, 0xe054462c, 0x79804668, 0x280a1c40, 0x200ad900, 0x981a9016, 0x28002108,
+ 0x0209d000, 0xaa029816, 0x981800c3, 0xffc1f7ff, 0xd1400004, 0x46302150, 0xfc3ff7fd, 0xe0372500,
+ 0xaa0200e8, 0x18835c11, 0x020079d8, 0x20ff180a, 0x42820200, 0x481bd002, 0xd1284282, 0x20022100,
+ 0x1819020f, 0x43397909, 0xd5f91e40, 0x008778d8, 0x2800981a, 0x0209d000, 0x020020ff, 0xd1084282,
+ 0x1d32463b, 0xf7ff9818, 0x0004ff94, 0x6037d113, 0x480ce00d, 0xd10a4282, 0x463b4632, 0x98183248,
+ 0xff87f7ff, 0xd1060004, 0x20442101, 0x1c6d5581, 0x42859816, 0x4620d3c4, 0xbdf0b01b, 0x00004e8b,
+ 0x50444653, 0x0000ff84, 0xb089b5ff, 0x4616461d, 0x9809460c, 0xfecdf7fe, 0xd1142800, 0x70084669,
+ 0x200e2701, 0x90029703, 0x4622740e, 0x326132ff, 0x4639463b, 0x98099501, 0xf83cf000, 0x97024669,
+ 0xf7fe9809, 0xb00dfb31, 0xb5f8bdf0, 0x20ff4607, 0x5c4030ce, 0x4616461d, 0x2800460c, 0x4638d004,
+ 0xf906f7ff, 0xd1052800, 0x4632462b, 0x46384621, 0xfe9ff7fe, 0x2104bdf8, 0xd00c2800, 0x29037b01,
+ 0x6c01d108, 0x06493040, 0xda012900, 0xe000210f, 0x8701211e, 0x46082100, 0x68014770, 0x43112201,
+ 0x68016001, 0xd1fc07c9, 0x8f4ff3bf, 0x8f6ff3bf, 0x00004770, 0x460eb5f8, 0x461f2104, 0x91004615,
+ 0xfedef7fe, 0xd0230004, 0xd0212d00, 0x19f22100, 0x23104149, 0x1a9a2000, 0xd3194188, 0xf0004620,
+ 0x4a0cf825, 0x200261a2, 0x19f161e0, 0x008b00b0, 0x19090081, 0x31ff31ff, 0xe0023102, 0xc140cd40,
+ 0x42981c40, 0x61a2d3fa, 0x61e02001, 0x90002000, 0xbdf89800, 0x5af05af0, 0xf7feb510, 0x2800feb1,
+ 0x3080d003, 0x07896e01, 0xbd10d5fc, 0x6e013080, 0xd0fc07c9, 0x07896e01, 0x4770d5fc, 0x4805b510,
+ 0x05806940, 0x48040f81, 0x44481c49, 0xf7fd6800, 0xbd10fb56, 0x400fc000, 0x0000004c, 0x4805b510,
+ 0x05806940, 0x48040f81, 0x44481c49, 0xf7fd6800, 0xbd10fb46, 0x400fc000, 0x0000004c, 0x460ab5f7,
+ 0x46963248, 0x1d0d688a, 0x2a002301, 0x461cda03, 0x40941ed2, 0x1c52e001, 0x650408d4, 0x30ff27ff,
+ 0x3701680a, 0x46a43081, 0xd2012a40, 0xe00a6407, 0x06128d2a, 0x461a0f14, 0x240140a2, 0x42a203e4,
+ 0x463ad100, 0x4c126402, 0x00532200, 0x7f1f195b, 0xd0052f00, 0x40bb2301, 0xd20142a3, 0x4616461c,
+ 0x2a041c52, 0x2201d3f1, 0x64440612, 0xd9074594, 0x79083140, 0xd0032800, 0x19804670, 0xe0027901,
+ 0x19400070, 0x98027f41, 0x20006001, 0x0000bdfe, 0x0000ffff, 0x20ff4a0e, 0x68526851, 0x0f890609,
+ 0x0f920692, 0xd0072900, 0xd00f2901, 0xd00d2902, 0xd1002903, 0x47702002, 0xd0032a00, 0xd0032a01,
+ 0x47702020, 0x47702001, 0x47702010, 0x47702008, 0x400f8000, 0x47704800, 0x01312d00, 0x68024803,
+ 0x438a2103, 0x6002430a, 0x00004770, 0x400fc080, 0xb5104903, 0x00c04449, 0xf7fd6809, 0xbd10fac0,
+ 0x00000050, 0x4602b570, 0xf832f000, 0x4909460d, 0x44494604, 0x68094610, 0xf871f7fe, 0x08c3074a,
+ 0x08ca4313, 0x416a191c, 0xf822f000, 0x41911b00, 0xbd70d3fa, 0x00000050, 0x4809b510, 0x69c06941,
+ 0x0f890589, 0x48070684, 0x44480ea4, 0x1c496800, 0xf7fd1c64, 0x4621fa94, 0xfa91f7fd, 0x0000bd10,
+ 0x400fc000, 0x0000004c, 0xf7ffb510, 0xbd10ff27, 0x4803b508, 0x6a406a01, 0x43c09000, 0xbd0843c9,
+ 0x400840c0, 0x4813b510, 0x68012304, 0x03122203, 0x43114391, 0x48106001, 0x60012100, 0x1e4a480f,
+ 0x61816102, 0x61c42401, 0x43196981, 0x69816181, 0x61814321, 0x60c46002, 0xf7ff6084, 0x00c0ffbd,
+ 0xf7fd4907, 0x4907fa5c, 0x44492800, 0xd1006008, 0xbd10600c, 0x400fc06c, 0x40084000, 0x40084100,
+ 0x000f4240, 0x00000050, 0xb089b5ff, 0x90032004, 0x460e980b, 0x90021d00, 0x3048980b, 0x20009007,
+ 0x980c9001, 0x02006800, 0x28010f00, 0x9802d105, 0x03006800, 0x90010fc0, 0x2000d07e, 0x980c7330,
+ 0x7800aa08, 0x0f090701, 0x55812046, 0x90042018, 0x90052000, 0x990b4630, 0xfee0f7ff, 0x6d302101,
+ 0x42880609, 0x980bd906, 0x79003040, 0xd0012800, 0x90042020, 0x8800980c, 0x0f000400, 0x4631d15c,
+ 0x9a0b9b0c, 0xf0009809, 0x9003f9af, 0xd1f52800, 0x68009802, 0xd5080281, 0x90052002, 0x7a009802,
+ 0x0f4f0601, 0x0ec006c0, 0x0240e007, 0x9802d506, 0x02016880, 0x02c00f4f, 0x90000ec0, 0x98041df4,
+ 0x34f94a95, 0xd0012820, 0xe00e4894, 0x49949807, 0x05c36800, 0x4893d501, 0x0600e002, 0x4892d503,
+ 0x61206161, 0x4890e003, 0x61623011, 0x20016120, 0x46357330, 0x3580488d, 0x488d6328, 0x98086128,
+ 0x9804b2c1, 0x43010400, 0x488a9006, 0x20234301, 0x65290140, 0x980c6320, 0x01006800, 0xd00f0f00,
+ 0x6840980c, 0x0e090601, 0x9901d00a, 0xb2c02700, 0x29009000, 0xe000d01f, 0x0040e069, 0xe01a9000,
+ 0x28009801, 0x9804d017, 0xd1042820, 0x30124876, 0x48796028, 0x46316068, 0xf7fe9809, 0x9003ffe6,
+ 0xd18b2800, 0x4631466a, 0xf0009809, 0x9003f9b5, 0xd14c2800, 0x98042700, 0xd0062818, 0x90052002,
+ 0x28009801, 0x20eed01d, 0x9801e003, 0xd0082800, 0x6c3120ed, 0x43112240, 0x99066431, 0x48674301,
+ 0x9802e025, 0x02816800, 0x9802d503, 0x04008900, 0x0240e003, 0x9802d503, 0x0e006880, 0x2003e011,
+ 0x9807e00c, 0x06816800, 0x20ecd501, 0x06c0e009, 0x206cd503, 0x91052100, 0x2013e003, 0x460f2100,
+ 0x99069100, 0x98054301, 0x43010600, 0x46334851, 0x60294301, 0x33ff990c, 0x33c17809, 0x20000609,
+ 0x93050f0a, 0xd0032a00, 0x29010f09, 0xe06bd004, 0x19c09800, 0xe0499000, 0x6809990b, 0xd3f72940,
+ 0x6b899902, 0xd5f3058a, 0x0f090309, 0x42112205, 0x20a5d001, 0x0789e00b, 0x4631d509, 0x9a0b9b0c,
+ 0xf0009809, 0x9003f895, 0xd14d2800, 0x99022001, 0x8f09220a, 0x0e890409, 0xd0074211, 0x67214938,
+ 0x99046761, 0xd1092920, 0xe0064936, 0x42112211, 0x4935d03a, 0x67616721, 0x67a14934, 0x9a052101,
+ 0x73512f00, 0x9901d011, 0xd0332900, 0xd02e2f01, 0x02892127, 0x99004308, 0x0a090609, 0x492c4308,
+ 0x60684308, 0x60a8482b, 0x9800e017, 0xd00f2800, 0x49299a01, 0xd0052a00, 0x1840b2c0, 0x43084927,
+ 0xe00a6068, 0x1840b2c0, 0x43084925, 0xe00b6068, 0x60684824, 0x28009801, 0x9905d006, 0x73882001,
+ 0x21406c30, 0x64304308, 0xb00d9803, 0x2126bdf0, 0xe7ce0900, 0xd00c2f01, 0x02892107, 0x99004308,
+ 0x0a090609, 0x49184308, 0x60684308, 0x60a84817, 0x2106e7ea, 0xe7f00900, 0x00002004, 0x08180402,
+ 0x00002204, 0x0a20043e, 0x08200401, 0x00000406, 0x24040405, 0x08000400, 0x00012404, 0x8a000400,
+ 0x06ff06ff, 0x000006ff, 0x06000600, 0x32101e00, 0xb2000200, 0x7c01a604, 0x00040200, 0xa604b000,
+ 0x26043000, 0x00002404, 0x32000200, 0x7c012604, 0xb08eb570, 0x2100460c, 0x9100910c, 0x910d910b,
+ 0x9102466a, 0x75114606, 0x71102003, 0x95032501, 0x95094813, 0x900a9208, 0x9504462b, 0x4629aa0a,
+ 0xf7ff4630, 0xa901fcd7, 0xf7fd4630, 0x2800ffcd, 0x9900d113, 0x401122f7, 0x040a4b0a, 0x910018d3,
+ 0x742522ff, 0x51133261, 0x220e7525, 0x61a17562, 0x74612104, 0x34c134ff, 0xb00e73e5, 0x0000bd70,
+ 0x24010485, 0x04000481, 0xb08fb5ff, 0x460c2000, 0x900b900a, 0x900d900c, 0x26016811, 0x2940461d,
+ 0x7426d318, 0x02496bd1, 0x000b0f49, 0xfe1ff7fd, 0x07041006, 0x1004040c, 0x492c2702, 0x492be002,
+ 0x39302701, 0xe009910a, 0x27034928, 0xe7f9310a, 0xe0417420, 0x05098829, 0xd03d0f0f, 0x90002000,
+ 0x90024669, 0x20037508, 0x96037108, 0x23019609, 0xaa0a9108, 0x46199604, 0xf7ff980f, 0xa901fc7b,
+ 0xf7fd980f, 0x2800ff71, 0x6828d127, 0x0f000100, 0x88a8d005, 0x0e010400, 0x0e00d001, 0x46209000,
+ 0x74263080, 0xd0052f01, 0xd0082f02, 0xd0162f03, 0xe7cd2000, 0x6401490e, 0x98002140, 0x490de014,
+ 0x98006401, 0x43082102, 0x90000200, 0x20047526, 0x98007560, 0x746661a0, 0xb0132000, 0x4905bdf0,
+ 0x6401313d, 0x21809800, 0xe7ee4308, 0x24010435, 0x20010401, 0x20020401, 0x460cb5f7, 0x30c520ff,
+ 0x59006d09, 0x1a08b098, 0x90012600, 0x74064668, 0x96022501, 0x2c009503, 0x4866d07b, 0xc88d4478,
+ 0xc18da90d, 0x466a2003, 0xa8097010, 0x20109007, 0x46229008, 0x21013280, 0x98189b03, 0xfc1af7ff,
+ 0x95024669, 0xf7fd9818, 0x2800ff0f, 0x2001d161, 0x98099011, 0xd1081c40, 0x1c40980a, 0x980bd105,
+ 0xd1021c40, 0x1c40980c, 0x2210d008, 0xa80da909, 0xff58f7fc, 0xd14c2800, 0xe03a9011, 0x461a2300,
+ 0x98184621, 0xfbc1f7ff, 0xd1422800, 0x90022009, 0x46692002, 0xa80d7008, 0x27104622, 0x32ff9005,
+ 0x32119706, 0x9b032101, 0xf7ff9818, 0x4669fbe3, 0x98189502, 0xfed8f7fd, 0xd1742800, 0x461a2300,
+ 0x98184621, 0xf978f7fe, 0xd16c2800, 0x20039002, 0x70084669, 0x9007a809, 0x98189708, 0xfec4f7fd,
+ 0xd1602800, 0xa9092210, 0xf7fca80d, 0x2800ff1b, 0x2032d159, 0x20009013, 0x6c209012, 0x43082140,
+ 0x20466420, 0x25045d01, 0x98182201, 0xfe4af7fd, 0xe048e043, 0x90142000, 0x90169015, 0x21019017,
+ 0x06096d20, 0xd9014288, 0xe0004823, 0x90144823, 0xb2e84923, 0x49231840, 0x43082301, 0xaa149015,
+ 0x98182100, 0xfb96f7ff, 0x46692003, 0xa8097008, 0x20109007, 0x98189008, 0xfe86f7fd, 0xd0120007,
+ 0xd0202e00, 0x6005981a, 0x28009811, 0x4621d008, 0x98189a01, 0xfd0ff7fe, 0x98184607, 0xfdf7f7fd,
+ 0xd0102e00, 0x2210e010, 0xa80da909, 0xfecaf7fc, 0xd00c2800, 0x2e001c6d, 0x9812d1e4, 0x1c409913,
+ 0x42889012, 0x4f08d3b6, 0x4638b01b, 0x2601bdf0, 0x0000e7d8, 0x000001d8, 0x8a2004ee, 0x8a1804ed,
+ 0x00040200, 0xa604b000, 0x00004e8e, 0x08220000, 0x06180816, 0x0612041e, 0x0411060e, 0x0216060c,
+ 0x06180000, 0x060c0416, 0x0312021e, 0x01210216, 0x0116011a, 0x402a8000, 0x33221100, 0x77665544,
+ 0xbbaa9988, 0xffeeddcc, 0x0818045a, 0x24ff3008, 0x00000000, 0x00000000, 0x0918055a, 0x25ff3108,
+ 0x00000000, 0x00000000, 0x0a18065a, 0x26ff3208, 0x00000000, 0x00000000, 0x2403049f, 0x00000000,
+ 0x00000000, 0x00000000, 0x8760879f, 0xa7048b20, 0x00000000, 0x00000000, 0x0818045a, 0x24ff3008,
+ 0x00000000, 0x00000000, 0x8b20075a, 0x0000a7ff, 0x00000000, 0x00000000, 0x0818045a, 0x24ff3008,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8a18065a, 0x0000a6ff,
+ 0x00000000, 0x00000000, 0x8b20075a, 0x0000a7ff, 0x00000000, 0x00000000, 0x00000000, 0x40184000,
+ 0x40188000, 0x4018c000, 0x40190000, 0x40194000, 0x40198000, 0x4019c000, 0x401a0000, 0x0014ff80,
+ 0x00160015, 0x00180017, 0x001a0019, 0xffff001b, 0x001c0518, 0x0118000c, 0x03060302, 0x060e051a,
+ 0x00000000, 0x00000000, 0x00000000, 0x412000d1, 0x60002000, 0x00000000, 0x00000000, 0x60001020,
+ 0x60001000, 0x00000000, 0x00000000, 0x60000000, 0x00800000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00b71b00, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x60000000, 0x00000400},
+ };
+
+static const program_target_t flash = {
+ 0x200003a9, // Init
+ 0x20000c9d, // UnInit
+ 0x2000035d, // EraseChip
+ 0x20000389, // EraseSector
+ 0x20000c2d, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x20003480,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(RT1050_IS26KS512S_flash_prog_blob), // prog_blob size
+ RT1050_IS26KS512S_flash_prog_blob, // address of prog_blob
+ 0x00000200 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/mimxrt1050_hyper_flash/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/mimxrt1050_hyper_flash/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the i.MXRT1050
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x60000000,
+ .flash_regions[0].end = 0x60000000 + MB(64),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20000000 + MB(64),
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/mimxrt1050_spi_flash/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/mimxrt1050_spi_flash/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,540 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the i.MXRT1050 QSPI
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t MIMXRT105x_QuadSPI_4KB_SEC_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x4605b570, 0x4616460c, 0xcc0fe002, 0x3e10c50f, 0xd2fa2e10, 0xd3022e08, 0xc503cc03, 0x2e043e08,
+ 0xcc01d307, 0x1f36c501, 0x7821e003, 0x1c647029, 0x1e761c6d, 0xbd70d2f9, 0x4770ba40, 0x4770ba40,
+ 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770bac0, 0x4770bac0, 0x4770bac0,
+ 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x481db51c, 0x9000491d, 0x4449466a, 0xf0022000,
+ 0x2800fa9e, 0x4919d105, 0xf0004449, 0x2800fde3, 0x2001d000, 0x2000bd1c, 0x49144770, 0x4449b510,
+ 0xf0002000, 0x2800ff3a, 0x2001d000, 0x2105bd10, 0x18420749, 0xb510490d, 0x049b2301, 0x20004449,
+ 0xfad3f002, 0xd0002800, 0xbd102001, 0x46132105, 0x18420749, 0xb5104905, 0x20004449, 0xfebef000,
+ 0xd0002800, 0xbd102001, 0xc0000006, 0x00000010, 0x49a4b5f8, 0x444948a2, 0x4ea46008, 0x603048a2,
+ 0x28006830, 0x6b30dafc, 0x03092101, 0x63304388, 0x28006b30, 0x489edafc, 0x499e6802, 0x400a2303,
+ 0x18d202db, 0x431a4b9c, 0x20036002, 0x61300300, 0x28006930, 0x6930dafc, 0x043f2701, 0x613043b8,
+ 0x3a404a93, 0x40086b10, 0x02092123, 0x49931840, 0x63104308, 0x20014c92, 0x49936120, 0x44494891,
+ 0x25016008, 0xe0009000, 0x46291c6d, 0xf0039800, 0x498efa9b, 0xd8f74288, 0x498d6960, 0x1e694008,
+ 0x0b490749, 0x02294308, 0x390139ff, 0x0d890589, 0x61604308, 0x09c06a60, 0x1cc001c0, 0x69a06260,
+ 0x04892103, 0x61a04308, 0x498269a0, 0x21054008, 0x18400689, 0x69e061a0, 0x4008497f, 0x07492103,
+ 0x497e1840, 0x61e04308, 0x210369e0, 0x43080409, 0x6a6061e0, 0x02c921e7, 0x21214388, 0x184002c9,
+ 0x68306260, 0x603043b8, 0x43b86b30, 0x69306330, 0x613043b8, 0x486abdf8, 0x68013080, 0x02922203,
+ 0x60014311, 0x48664770, 0x68013080, 0x02922203, 0x60014391, 0xb5f74770, 0x4969460c, 0x4615b08a,
+ 0x44792214, 0xf7ff4668, 0x4965feeb, 0x44792214, 0xa8053108, 0xfee4f7ff, 0xd0012d00, 0xd1362d01,
+ 0x3e404e53, 0x09876b30, 0x01bf4855, 0x200769c2, 0x438205c0, 0xd02c2d00, 0x2c00a805, 0x2c09d027,
+ 0x2401d900, 0x5c430061, 0x78401808, 0x05c02107, 0x069b05c9, 0x0e9b1840, 0x4d520184, 0x09a4433b,
+ 0x43146828, 0x43382702, 0x980a6028, 0xffbbf7ff, 0x42986b30, 0x6333d000, 0x69c14841, 0xd00042a1,
+ 0x980a61c4, 0xffa7f7ff, 0x43b86828, 0xb00d6028, 0x4668bdf0, 0xb570e7d1, 0x4a3b4616, 0x444a2000,
+ 0x46046812, 0xd0082900, 0x29014d35, 0x2902d007, 0x2404d00a, 0x46206030, 0x4610bd70, 0x6968e7fa,
+ 0x0f810580, 0xe00d4610, 0x482969e8, 0x6b003840, 0x0e890681, 0xf0034834, 0x2112f9d7, 0x69e94348,
+ 0x0f490189, 0xf0031c49, 0xe7e3f9cf, 0x20044603, 0xd1042b00, 0xd0022900, 0x6008482c, 0x47702000,
+ 0x44484821, 0x47706800, 0x481db510, 0x05806940, 0x481d0f81, 0x44481c49, 0xf0036800, 0xbd10f9b5,
+ 0x4604b5f8, 0x460d4818, 0x68004448, 0xf0034920, 0x4606f9ab, 0x2103e009, 0xf0034630, 0x9000f9a5,
+ 0xbf00e000, 0x90001e40, 0x2200d2fb, 0x46281e64, 0x415043d2, 0x43e14605, 0x430143e8, 0xbdf8d1eb,
+ 0x016e3600, 0x00000004, 0x00012058, 0x400d8000, 0x400d8100, 0xc0c0c0c0, 0x18131818, 0x0f1a2323,
+ 0x400fc000, 0x1f78a400, 0x0000000c, 0x08954400, 0xfff8e0ff, 0xe3ffffcf, 0x9c7fff80, 0x03800001,
+ 0x000036c2, 0x402a8000, 0x1c9c3800, 0x09e4f580, 0x000f4240, 0x4d5ab5f8, 0x462e485a, 0x460c9000,
+ 0x46084637, 0xfa8bf002, 0xd0042800, 0x6ee06e26, 0x6e679000, 0x6d206ea5, 0x6d602800, 0x2800d027,
+ 0x4951d004, 0x63c82006, 0x62c64850, 0x28006d20, 0x494dd006, 0x31402001, 0x484c62c8, 0x61c63040,
+ 0x23114949, 0x630b3140, 0x30404848, 0x22016207, 0x6245634a, 0x6285638a, 0x62c563ca, 0x31804942,
+ 0x6305600a, 0x5d002045, 0xd0032808, 0x2800e00f, 0xe024d1d7, 0x2001493c, 0x62083140, 0x32404a3b,
+ 0x61c86115, 0x618860d5, 0x61486095, 0x7b206055, 0xd0012803, 0xd1062801, 0x30404833, 0x49336283,
+ 0x31409800, 0x46206188, 0xfa40f002, 0xd0062800, 0x2101482d, 0x62413040, 0x3040482c, 0x6da06147,
+ 0x6de02800, 0x2800d02a, 0x4927d005, 0x31402006, 0x48266008, 0x6da06306, 0xd0052800, 0x21044822,
+ 0x62413040, 0x63c64821, 0x2111481f, 0x62413040, 0x3140491e, 0x2201614f, 0x610d6202, 0x60cd61c2,
+ 0x608d6182, 0x604d6142, 0x2a037b22, 0x2a01d001, 0x2214d103, 0x98006102, 0xbdf86008, 0xd1d42800,
+ 0x2104bdf8, 0xd00f2800, 0x29037b01, 0x6c01d10b, 0x06493060, 0xda012900, 0xe003210f, 0x29007e41,
+ 0x211ed101, 0x21007601, 0x47704608, 0x62884908, 0x47702000, 0x6a894906, 0x20006001, 0x00004770,
+ 0x000010f1, 0x000130f1, 0x401f8180, 0x401f8380, 0x400f8000, 0x49fcb5f0, 0x4479b085, 0x466dc91e,
+ 0x4efac51e, 0x4df94ff9, 0x4cf84669, 0x37803640, 0x000335c0, 0xf9aaf003, 0x220d0609, 0x8381582b,
+ 0x00918b89, 0xfb42f000, 0x06496821, 0x43480e49, 0xf000e048, 0x6a37fb3b, 0x69314605, 0xf97ef003,
+ 0x2300463a, 0xffa8f002, 0x07c96b21, 0x2116d001, 0x2114e000, 0x1828434d, 0xbdf0b005, 0xfb26f000,
+ 0xe0676921, 0xe0002116, 0x43482114, 0xf000e7f4, 0x4604fb1d, 0x06456b30, 0x693f4638, 0x68010e6d,
+ 0xf0034620, 0x463af95b, 0xf0022300, 0x436cff85, 0x18206b31, 0x04d22203, 0xd0114011, 0x04d22201,
+ 0xd1004291, 0x49d20840, 0x4ad26b09, 0x22014011, 0x1a8903d2, 0x0212d006, 0xd1cd4291, 0xe7cb0880,
+ 0xe7f00880, 0xe7c70840, 0xfaf0f000, 0x6a384604, 0x0646682d, 0x6b390e76, 0xf0034620, 0x462af92f,
+ 0xf0022300, 0x4374ff59, 0x18206a39, 0x04d22203, 0xd0104011, 0x04d22201, 0xd1004291, 0x49bc0840,
+ 0x22016b09, 0x07890f89, 0x18890792, 0x0052d0d6, 0xd1a142d1, 0x0880e7d6, 0x6a28e7f1, 0x6a28e001,
+ 0x07800880, 0x58080f00, 0x48b3e796, 0xf000e794, 0x6a21fabd, 0xd0970789, 0x2000e794, 0xb510e78c,
+ 0x20014604, 0xff56f7ff, 0x394049a9, 0xd0092c00, 0xd0092c01, 0xd00e2c02, 0xd00f2c03, 0x21122000,
+ 0xbd104348, 0xe0016809, 0x0a096809, 0x0e890689, 0xffeaf002, 0x6809e7f3, 0xe7f70c09, 0x0e096809,
+ 0xb510e7f4, 0x69604c9d, 0x69a00180, 0x2103d512, 0x40080309, 0x2101d005, 0x42880309, 0x2000d005,
+ 0x2002e005, 0xff26f7ff, 0xf000e001, 0x6961fa7f, 0xe00f0ec9, 0x04892103, 0xd0134008, 0x04892101,
+ 0xd0131a40, 0xd0121a40, 0xd1094288, 0xf7ff2000, 0x6921ff11, 0x0f490749, 0xf0021c49, 0xbd10ffb5,
+ 0xbd102000, 0xf7ff2001, 0xbd10ff05, 0xf7ff2002, 0xbd10ffa6, 0x2800b510, 0xf002d001, 0x2101ff4e,
+ 0x0789487b, 0x497e6181, 0x03d26b0a, 0x2201d5fc, 0x61420412, 0x04096901, 0x6182d5fc, 0x2001bd10,
+ 0x07804973, 0x47706148, 0x49752210, 0xd0012800, 0x4770638a, 0x4770634a, 0x6b014871, 0x43112201,
+ 0x47706301, 0x6b01486e, 0x00490849, 0x47706301, 0x4604b510, 0xf7ff2002, 0x4965fecd, 0x2c003980,
+ 0x2c01d009, 0x2c02d009, 0x2c03d00e, 0x2000d00f, 0x43482112, 0x6b09bd10, 0x6b09e001, 0x06890a09,
+ 0xf0020e89, 0xe7f3ff61, 0x0c096b09, 0x6b09e7f7, 0xe7f40e09, 0x4c59b510, 0xf0030003, 0x0d17f867,
+ 0x362a120d, 0x403e3c39, 0x4a464442, 0x52504e4c, 0x5c5a5854, 0x0064605e, 0xff63f7ff, 0x0a896961,
+ 0x6960e011, 0xd50a0640, 0x06006960, 0x2001d503, 0xffbef7ff, 0x2002e005, 0xff31f7ff, 0xf7ffe001,
+ 0x6961ff50, 0x07490c09, 0x1c490f49, 0xff2cf002, 0xf7ffbd10, 0x6961ff46, 0x0f4904c9, 0xf0021c49,
+ 0x6961ff23, 0x0f890589, 0xf000e7ef, 0xbd10f9cf, 0x03c02001, 0x2000bd10, 0x2002e022, 0x2000e020,
+ 0x2001e004, 0x2002e002, 0x2003e000, 0xff90f7ff, 0x2008bd10, 0x2001e014, 0x2000e012, 0x2001e004,
+ 0x2002e002, 0x2003e000, 0xfef9f7ff, 0x2005bd10, 0x2006e006, 0x2007e004, 0x2003e002, 0x2004e000,
+ 0xfe48f7ff, 0x2000bd10, 0x7800bd10, 0x06402101, 0x03490e40, 0x481d1841, 0x68016001, 0xdafc2900,
+ 0x20014770, 0x03004919, 0x47706008, 0x21017800, 0x0fc007c0, 0x18410349, 0x63014814, 0x29006b01,
+ 0x4770dafc, 0x49112001, 0x63080300, 0x78004770, 0x078021c1, 0x01890f80, 0x480c1841, 0x69016101,
+ 0xdafc2900, 0x49094770, 0x61082000, 0x78004770, 0x078021c1, 0x01890f80, 0x48041841, 0x6a016201,
+ 0xdafc2900, 0x00004770, 0x000033b2, 0x400d8000, 0x400d8140, 0x00808000, 0x017d7840, 0x400fc000,
+ 0x400d8240, 0x200049ae, 0xe7eb6208, 0x6841b530, 0x008b2200, 0x089b49aa, 0x600b3180, 0x009b6883,
+ 0x610b089b, 0x23017801, 0x035b0649, 0x78400e49, 0x019d18c9, 0xd01c2802, 0x006c4ba2, 0xd0162804,
+ 0xd0122808, 0xd00e2810, 0x4b9f4321, 0x4c9d6b18, 0x402043e4, 0x63184310, 0x30404899, 0x6b016301,
+ 0xdafc2900, 0x461abd30, 0x4329e7ef, 0x4321e7fb, 0x4329e7f9, 0x2001e7e9, 0x03004991, 0x63083140,
+ 0xb570e7b0, 0x4b8e6841, 0x22000089, 0x33800889, 0x68816319, 0x00894c8c, 0x3c800889, 0x78016021,
+ 0x06492401, 0x0e490364, 0x19097840, 0x280201a5, 0x2403d01a, 0x006e07a4, 0xd0132804, 0xd00f2808,
+ 0xd00b2810, 0x48804331, 0x00a46b04, 0x431408a4, 0x62196304, 0x28006a18, 0xbd70dafc, 0xe7f24622,
+ 0xe7fb4329, 0xe7f94331, 0xe7ec4329, 0x49742001, 0x31800300, 0xe7756208, 0x78c27901, 0x07920789,
+ 0x0f920f09, 0x78024311, 0xd0022a00, 0x03522201, 0x78424311, 0xd0022a00, 0x05122201, 0x78804311,
+ 0xd0022800, 0x05402001, 0x48674301, 0x62013880, 0x29006a01, 0xe755dafc, 0x49632001, 0x39800300,
+ 0xe74f6208, 0xb5104b60, 0x681a3b40, 0x24bf00c0, 0x43a24084, 0x40842480, 0x601c4314, 0x0e890689,
+ 0x43114081, 0xbd106019, 0x39404957, 0x00c3680a, 0x40982080, 0x600a4302, 0x4b53e734, 0x3b80b510,
+ 0x00c06b1a, 0x408424bf, 0x248043a2, 0x43144084, 0x0689631c, 0x40810e89, 0x63194311, 0x494abd10,
+ 0x6b0a3980, 0x208000c3, 0x43024098, 0xe719630a, 0x4846b508, 0x22036801, 0x60014311, 0x68014844,
+ 0x43112202, 0x20006001, 0x48429000, 0x9900bf00, 0x91001c49, 0xd3f94281, 0x3940493b, 0x221f6a08,
+ 0x43900212, 0x43104a3c, 0x20016208, 0xb508bd08, 0x68014836, 0x43112203, 0x48386001, 0x22026801,
+ 0x60014311, 0x90002000, 0xbf004832, 0x1c499900, 0x42819100, 0x492cd3f9, 0x6a083940, 0x0212221f,
+ 0x4a2d4390, 0x62084310, 0xbd082001, 0x2200b508, 0x92004668, 0xfebbf7ff, 0x6b014829, 0x08490049,
+ 0x6b016301, 0x43990483, 0x60026301, 0x22636b01, 0x43110392, 0x20016301, 0xb508bd08, 0x46682200,
+ 0xf7ff9200, 0x481ffeb4, 0x00496b01, 0x63010849, 0x04436b01, 0x63014399, 0x6b016002, 0x03922263,
+ 0x63014311, 0xbd082001, 0x2000490d, 0x48146108, 0x04826b01, 0x63014311, 0x4909e6a4, 0x62082000,
+ 0x6b014810, 0x43110442, 0xe69b6301, 0x6b00480e, 0xd50106c0, 0xe695480d, 0x4448480d, 0xe6916800,
+ 0x400d8000, 0x00808000, 0x400d8140, 0x400fc080, 0x402e0140, 0x00061a80, 0x00001701, 0x402e0340,
+ 0x400d9000, 0x400da000, 0x400d8240, 0x016e3600, 0x00000004, 0x460cb570, 0xf0024606, 0x0005fa31,
+ 0x4622d10b, 0x32802301, 0x46302100, 0xf8e2f002, 0x28017c60, 0x2000d101, 0x46287420, 0xb570bd70,
+ 0x4605b08a, 0x466e2000, 0x200f7030, 0x90022401, 0x74329403, 0x32ff460a, 0x32719301, 0x46214623,
+ 0xf0024628, 0x4669f8c7, 0x94024628, 0xffd1f001, 0xbd70b00a, 0x2004b5ff, 0x460db083, 0xd0292900,
+ 0x36ff462e, 0x7b7036c1, 0xd0062800, 0x9a059b06, 0xf7ff9803, 0x2800ffd4, 0x7b30d11c, 0x3480462c,
+ 0xd10a2802, 0x30304620, 0x466bc887, 0x4620c307, 0xc80f3040, 0xc40f3430, 0x46293c40, 0x9a059b06,
+ 0xf0029803, 0x7b31f8c7, 0xd1032902, 0xcd0e466d, 0xc48e3430, 0xbdf0b007, 0xb089b5ff, 0x4616461d,
+ 0x9809460c, 0xffc6f7ff, 0xd1142800, 0x70084669, 0x200e2701, 0x90029703, 0x4622740e, 0x326132ff,
+ 0x4639463b, 0x98099501, 0xf874f002, 0x97024669, 0xf0019809, 0xb00dff7e, 0xb5ffbdf0, 0xb0832004,
+ 0x4696469c, 0xd0d52900, 0x35ff460d, 0x7b2835c1, 0x3480460c, 0xd10b2802, 0x30104620, 0x466ac889,
+ 0xc28969e6, 0x30204620, 0x3410c88d, 0x3c20c48d, 0x46724663, 0xf0029803, 0x7b29f8aa, 0xd1b92902,
+ 0xcd0e466d, 0xc44e3410, 0xb5f7e7b4, 0x4616b082, 0xd051000d, 0xd84f2e01, 0x34ff462c, 0x7a2034c1,
+ 0xd0002800, 0x28002001, 0x6c28d046, 0x0fc70640, 0xf0029802, 0x2e00fa5e, 0x7a20d02b, 0xd0092800,
+ 0x5d412046, 0x9802463a, 0xfa15f7ff, 0x98024629, 0xfda6f001, 0x28007ba0, 0x2100d003, 0xf0029802,
+ 0x466afa5a, 0x98022102, 0xfa55f7ff, 0xd0022f00, 0x08409800, 0xaa019000, 0x98022100, 0xfa4bf7ff,
+ 0x98019900, 0xfc40f002, 0x1c40210a, 0x08804348, 0x7a21e010, 0xd0072900, 0x9802463a, 0xf9ebf7ff,
+ 0x98024629, 0xfd7cf001, 0x28007ba0, 0x2101d0d9, 0xbf00e7d4, 0xd2fc1e40, 0xbdf0b005, 0xb089b5ff,
+ 0x460d4617, 0xf0014608, 0x4606fd43, 0x46292200, 0xf7ff9809, 0x463bff9a, 0x46294632, 0xf7ff9809,
+ 0x0004ff19, 0x2002d13f, 0x70084669, 0x24012009, 0x94039002, 0x5d412047, 0x30ff4628, 0x29003081,
+ 0x7c01d006, 0xd0032900, 0x91027c41, 0x91037c01, 0x97014669, 0x990c740e, 0x6c009105, 0x98029006,
+ 0x01002101, 0x32801942, 0x98099b03, 0xffb2f001, 0x94024669, 0xf0019809, 0x0004febc, 0x463bd113,
+ 0x46294632, 0xf7ff9809, 0x0004ff38, 0x20ffd10b, 0x5d4030d0, 0xd0062800, 0x4632463b, 0x98094629,
+ 0xff0af7ff, 0x98094604, 0xf9cdf002, 0x46292201, 0xf7ff9809, 0x4620ff4a, 0xb5f3e71d, 0x2600b08b,
+ 0x9d0c4669, 0x2101700e, 0x210b9103, 0x46699102, 0x2047740e, 0x46375d40, 0x28004634, 0x4628d009,
+ 0x308130ff, 0x29007d01, 0x7d41d003, 0x7d009102, 0x22009003, 0x980b990c, 0xff27f7ff, 0x950a3550,
+ 0x9009cd01, 0xd01a2800, 0x22004633, 0x980b990c, 0xfea0f7ff, 0xd13e0004, 0x96019802, 0x980c0101,
+ 0x180a9b03, 0x32802101, 0xf001980b, 0x2001ff53, 0x46699002, 0xf001980b, 0x0004fe5c, 0x9809d12b,
+ 0x18361c7f, 0xd3db2f04, 0xd1242c00, 0x90092000, 0x980c4606, 0x30ff9d0a, 0x900a30c1, 0x2f00cd80,
+ 0x2200d013, 0x990c9b09, 0xf7ff980b, 0x0004fec6, 0x980ad111, 0x28007bc0, 0x2200d007, 0x990c9b09,
+ 0xf7ff980b, 0x0004fe99, 0x9809d105, 0x19c01c76, 0x2e049009, 0x980bd3e2, 0xf955f002, 0x990c2201,
+ 0xf7ff980b, 0x4620fed2, 0xb5f7e6a5, 0x4617b08a, 0x4608460d, 0xfc6cf001, 0x22004606, 0x980a4629,
+ 0xfec3f7ff, 0x4632463b, 0x980a4629, 0xfe42f7ff, 0xd1390004, 0x97014669, 0x20057008, 0x90022401,
+ 0x740e9403, 0x5d402047, 0xd0092800, 0x30ff4628, 0x7b013081, 0xd0032900, 0x91027b41, 0x90037b00,
+ 0x21019802, 0x19420100, 0x9b033280, 0xf001980a, 0x4669fee1, 0x980a9402, 0xfdebf001, 0xd1130004,
+ 0x4632463b, 0x980a4629, 0xfe67f7ff, 0xd10b0004, 0x30d020ff, 0x28005d40, 0x463bd006, 0x46294632,
+ 0xf7ff980a, 0x4604fe39, 0xf002980a, 0x2201f8fc, 0x980a4629, 0xfe79f7ff, 0xe64c4620, 0xb08ab5f7,
+ 0x460d4617, 0xf0014608, 0x4606fc13, 0x46292200, 0xf7ff980a, 0x463bfe6a, 0x46294632, 0xf7ff980a,
+ 0x0004fde9, 0x4669d139, 0x70089701, 0x24012008, 0x94039002, 0x2047740e, 0x28005d40, 0x4628d009,
+ 0x308130ff, 0x29007f01, 0x7f41d003, 0x7f009102, 0x98029003, 0x01002101, 0x32801942, 0x980a9b03,
+ 0xfe88f001, 0x94024669, 0xf001980a, 0x0004fd92, 0x463bd113, 0x46294632, 0xf7ff980a, 0x0004fe0e,
+ 0x20ffd10b, 0x5d4030d0, 0xd0062800, 0x4632463b, 0x980a4629, 0xfde0f7ff, 0x980a4604, 0xf8a3f002,
+ 0x46292201, 0xf7ff980a, 0x4620fe20, 0xb5f0e5f3, 0x20044607, 0x461db089, 0x460e4614, 0xd00f2a00,
+ 0x46682124, 0xfa8ef002, 0x46692003, 0x20017008, 0x95089002, 0x96019003, 0x46389407, 0xfd59f001,
+ 0xbdf0b009, 0xb08fb5ff, 0x460c2000, 0x900b900a, 0x900d900c, 0x25016811, 0x2905461e, 0x6851d202,
+ 0xd3152940, 0x6c117425, 0x0f490249, 0xf002000b, 0x0d07fb7d, 0x050b0905, 0x000d0705, 0xe00b2702,
+ 0xe0092704, 0xe0072701, 0xe0052703, 0xe06d7420, 0x05098831, 0xd0690f0f, 0x90002000, 0x90024669,
+ 0x20037508, 0x95097108, 0x95049503, 0x2f019108, 0x2f02d007, 0x2f03d003, 0x2f04d02a, 0x48fdd104,
+ 0x48fce001, 0x900a3830, 0xaa0a2301, 0x980f4619, 0xfe00f001, 0x980fa901, 0xfd0bf001, 0xd1462800,
+ 0x01006830, 0xd0050f00, 0x040088b0, 0xd0010e01, 0x90000e00, 0x74202000, 0x30804620, 0xd00a2f01,
+ 0x2f022202, 0x2f03d010, 0x2f04d026, 0xe01bd12e, 0x300a48e8, 0x9900e7d7, 0xd427064a, 0x64024ae6,
+ 0x400120c3, 0xe01e2040, 0x078b9900, 0x4be3d41e, 0x64034311, 0x90000208, 0x75257425, 0x75602004,
+ 0x61a09800, 0xe0117465, 0x078b9900, 0x4bdad40e, 0x43113330, 0xe0076403, 0x060a9900, 0x4ad7d406,
+ 0x6402323d, 0x43012080, 0xe7e59100, 0xb0132000, 0xb5f7bdf0, 0x02402001, 0x2700b098, 0x46689001,
+ 0x24017407, 0x9702460d, 0x29009403, 0x48ccd072, 0xc84d4478, 0xc14da90d, 0x466a2003, 0xa8097010,
+ 0x20109007, 0x462a9008, 0x21013280, 0x98189b03, 0xfd90f001, 0x94024669, 0xf0019818, 0x2800fc9a,
+ 0x9809d158, 0xd1081c40, 0x1c40980a, 0x980bd105, 0xd1021c40, 0x1c40980c, 0x2210d007, 0xa80da909,
+ 0xf965f002, 0xd1452800, 0x2300e034, 0x4629461a, 0xf7ff9818, 0x2800fcaf, 0x2009d17b, 0x20029002,
+ 0x70084669, 0x462aa80d, 0x90052610, 0x960632ff, 0x21013211, 0x98189b03, 0xfd5cf001, 0x94024669,
+ 0xf0019818, 0x2800fc66, 0x2300d163, 0x4629461a, 0xf0019818, 0x2800fdac, 0x9002d15b, 0x46692003,
+ 0xa8097008, 0x96089007, 0xf0019818, 0x2800fc52, 0xe7c2d14f, 0x90162032, 0x90152000, 0x21406c28,
+ 0x64284308, 0x5d412046, 0x22012602, 0xf7fe9818, 0xe038ff22, 0x2400e03d, 0x94129411, 0x94149413,
+ 0x6d282101, 0x42880609, 0x488ed901, 0x488ee000, 0x498e9011, 0x1840b2f0, 0x2301498d, 0x90124308,
+ 0x2100aa11, 0xf0019818, 0x2003fd15, 0x94024669, 0xa8097008, 0x20109007, 0x98189008, 0xfc19f001,
+ 0xd0060004, 0xd0142f00, 0x2f00981a, 0xd0106006, 0x2210e010, 0xa80da909, 0xf8e9f002, 0xd00c2800,
+ 0x2f001c76, 0x9815d1f0, 0x1c409916, 0x42889015, 0x4c78d3c1, 0xb01b4620, 0x2701bdf0, 0xb5ffe7e4,
+ 0xb0824608, 0x9000305c, 0x68c8460b, 0x27013308, 0xda032800, 0x1ec0463a, 0xe0014082, 0x08c21c40,
+ 0x24ff9802, 0x9e026502, 0x68489201, 0x340136ff, 0x28403681, 0x6434d201, 0x8d18e00a, 0x0f020600,
+ 0x40904638, 0x03d22201, 0xd1004290, 0x64304620, 0x24004d61, 0x00424620, 0x7f1718d2, 0xd00d2f00,
+ 0x40ba2201, 0xd20142aa, 0x46844615, 0xd90542a2, 0x053f2701, 0xd20142ba, 0x46864614, 0x28041c40,
+ 0x6475d3e9, 0x98026534, 0x30c130ff, 0xd10142a5, 0xe0002201, 0x72422200, 0x98012201, 0x42900612,
+ 0x3140d92d, 0x28007e08, 0x9800d008, 0x79014460, 0x60019804, 0x44709800, 0xe0187901, 0x00404660,
+ 0x7f4018c0, 0x22dc2121, 0xd0022820, 0xd10528d8, 0x9804e002, 0xe0016001, 0x60029804, 0x00404670,
+ 0x7f4018c0, 0xd0022820, 0xd10528d8, 0x9805e002, 0xe0016001, 0x60029805, 0xb0062000, 0x4660bdf0,
+ 0x18c00040, 0x98047f41, 0x46706001, 0x18c00040, 0xe7ec7f41, 0xb08db5ff, 0x90052004, 0x460f980f,
+ 0x90033008, 0x305c980f, 0x20009009, 0x98109004, 0x02006800, 0x28010f00, 0x9803d105, 0x03006800,
+ 0x90040fc0, 0x2000d071, 0x99107338, 0x78094606, 0x070aab0b, 0x21460f12, 0x900055ca, 0x90062018,
+ 0x90072000, 0x4638aa0a, 0xf7ff990f, 0x2101ff48, 0x06096d38, 0xd9014288, 0x90062020, 0x88009810,
+ 0x0f000400, 0x4639d151, 0x9a0f9b10, 0xf7ff980d, 0x9005fdd9, 0xd1f52800, 0x68009803, 0xd51d0281,
+ 0x90072002, 0x7a009803, 0x0f4e0601, 0x0ec006c0, 0x0000e01c, 0x24010435, 0x20010401, 0x20020401,
+ 0x0000262c, 0x8a2004ee, 0x8a1804ed, 0x00040200, 0xa604b000, 0x00004e2a, 0x00ffffff, 0xd5060240,
+ 0x68809803, 0x0f4e0201, 0x0ec002c0, 0x980f9000, 0x30409a06, 0x49fc1dfc, 0x900834f9, 0xd0022a20,
+ 0x612048fa, 0x7e00e012, 0x28004bf9, 0x9809d03b, 0x68004af8, 0xd50105c5, 0xe00348f7, 0xd5320600,
+ 0x302248f3, 0x61206162, 0xe0a9e001, 0x20016161, 0x463d7338, 0x358048f1, 0x48f16328, 0x980a6128,
+ 0xb2c14af0, 0x04009806, 0x43114301, 0x65299001, 0xb2c9990b, 0x43114301, 0x01402023, 0x63206021,
+ 0x68009810, 0x0f010100, 0x9910d00f, 0x060a6849, 0xd00a0e12, 0x9904b2c8, 0x90002600, 0xd0212900,
+ 0x90000040, 0x6123e01e, 0x9904e7d0, 0xd0192900, 0xd1170f00, 0x28209806, 0x48d5d104, 0x60281c40,
+ 0x606848d9, 0x980d4639, 0xfaa4f7ff, 0x28009005, 0x466ad166, 0x980d4639, 0xfddbf7ff, 0x28009005,
+ 0x2600d1f6, 0x28189806, 0x2002d006, 0x98049007, 0xd0202800, 0xe00320ee, 0x28009804, 0x20edd00a,
+ 0x22406c39, 0x64394311, 0x43019901, 0x430148c7, 0xe0376029, 0x68009803, 0xd5030281, 0x89009803,
+ 0xe0030400, 0xd5040240, 0x68809803, 0x90020e00, 0x2003e01f, 0x9808e019, 0x28007e00, 0x9809d00a,
+ 0x06816800, 0x06c0d40a, 0x206cd513, 0x20009002, 0xe00e9007, 0x68009803, 0xd5010281, 0xe7e620ec,
+ 0xd5010240, 0xe7e2206c, 0x90022013, 0x46062000, 0x99029000, 0x43089801, 0x06099907, 0x49a94308,
+ 0x60284308, 0x463a9910, 0x32ff7809, 0x32c10609, 0x0f0b2000, 0x2b009201, 0x0f09d003, 0xd0042901,
+ 0x9800e06b, 0x90001980, 0x990fe049, 0x29406849, 0x9903d3f7, 0x058a6b89, 0x0309d5f3, 0x22050f09,
+ 0xd0014211, 0xe00b20a5, 0xd5090789, 0x9b104639, 0x980d9a0f, 0xff9ef000, 0x28009005, 0x2001d14d,
+ 0x220a9903, 0x04098f09, 0x42110e89, 0x4990d007, 0x67616721, 0x29209906, 0x498ed109, 0x2211e006,
+ 0xd03a4211, 0x6721498c, 0x498c6761, 0x210167a1, 0x2e009a01, 0xd0117351, 0x29009904, 0x2e01d033,
+ 0x2127d02e, 0x43080289, 0x06099900, 0x43080a09, 0x43084983, 0x48836068, 0xe01760a8, 0x28009800,
+ 0x9a04d00f, 0x2a004980, 0xb2c0d005, 0x497f1840, 0x60684308, 0xb2c0e00a, 0x497d1840, 0x60684308,
+ 0x487ce00b, 0x98046068, 0xd0062800, 0x20019901, 0x6c387388, 0x43082140, 0x98056438, 0xbdf0b011,
+ 0x09002126, 0x2e01e7ce, 0x2107d00c, 0x43080289, 0x06099900, 0x43080a09, 0x4308496f, 0x486f6068,
+ 0xe7ea60a8, 0x09002106, 0xb5f7e7f0, 0xb0984e6c, 0xd008000d, 0x466a2308, 0x98182100, 0xfc37f7ff,
+ 0xd1640004, 0x2404e001, 0x4966e061, 0x42889800, 0x4634d001, 0x4668e05b, 0x60287900, 0x79804668,
+ 0x280a1c40, 0x200ad900, 0x981a9016, 0x28002108, 0x0209d000, 0xaa029816, 0x981800c3, 0xfc17f7ff,
+ 0xd1440004, 0x46282164, 0xfeacf001, 0xe03b2600, 0xaa0200f0, 0x18835c11, 0x020079d8, 0x20ff180a,
+ 0x42820200, 0x4850d002, 0xd12c4282, 0x20022100, 0x1819020f, 0x43397909, 0xd5f91e40, 0x008778d8,
+ 0x2800981a, 0x0209d000, 0x020020ff, 0xd10c4282, 0xd9002f50, 0x462a2750, 0x3208463b, 0xf7ff9818,
+ 0x0004fbe6, 0x606fd113, 0x483fe00d, 0xd10a4282, 0x463b462a, 0x9818325c, 0xfbd9f7ff, 0xd1060004,
+ 0x20582101, 0x1c765541, 0x42869816, 0x4620d3c0, 0xb5f7e541, 0xb088460d, 0x46282103, 0x230873e9,
+ 0x71433040, 0x642b2358, 0x73292401, 0xd0012a00, 0x64292159, 0x210f71c4, 0x87c48781, 0x2001462e,
+ 0x024036ff, 0x64303681, 0x64700240, 0x46306530, 0x90073040, 0x46297244, 0xf7ff9808, 0x2800f91b,
+ 0x4822d172, 0x90002700, 0x97034821, 0x90012301, 0x466a9702, 0x98084619, 0xf9fcf001, 0x97039702,
+ 0x481c4f1a, 0xe0373780, 0x00002004, 0x08180402, 0x08200412, 0x00002204, 0x0a20043e, 0x00000406,
+ 0x24040405, 0x08000400, 0x00012404, 0x8a000400, 0x06ff06ff, 0x000006ff, 0x06000600, 0x32101e00,
+ 0xb2000200, 0x7c01a604, 0x00040200, 0xa604b000, 0x26043000, 0x00002404, 0x32000200, 0x7c012604,
+ 0x00004e27, 0x50444653, 0x0000ff84, 0x8b188720, 0xa3028f10, 0xa7048f10, 0x23019001, 0x2100466a,
+ 0x98089700, 0xf9b6f001, 0x02c02013, 0x23029006, 0x49feaa06, 0xf0009808, 0x2800fef9, 0x2308d114,
+ 0x2110aa04, 0xf0009808, 0x2800fedd, 0x9805d10c, 0xb28049f7, 0x98049005, 0xd1044288, 0x98052159,
+ 0x42880209, 0x48f3d002, 0xbdf0b00b, 0xaa042308, 0x98082127, 0xfec6f000, 0xd1f52800, 0x04009804,
+ 0x90040e00, 0x28093817, 0x9904d8ed, 0x40882001, 0x200f6528, 0x90060300, 0xaa062302, 0x98082100,
+ 0xfec4f000, 0xd1df2800, 0x49e3462c, 0x60213480, 0x606149e2, 0x60a149e2, 0x4ae349e2, 0x4fe44be3,
+ 0xc48e3410, 0x60274fdc, 0x60674fe2, 0x60a74fdc, 0xc40e3410, 0x60a74fe0, 0x60616022, 0x60e74fdf,
+ 0x61274fdd, 0x4fde35ff, 0xc58e3511, 0x34144fd2, 0x602f3fa0, 0x606f4fdb, 0xc48e4fdb, 0x4fd6c40e,
+ 0x602260a7, 0x4fd56061, 0x4fd360e7, 0x4cca6127, 0x3ca03d20, 0x4cd5602c, 0x4cd5606c, 0x462f60ac,
+ 0x37304cd1, 0xc70ec71e, 0x656c4ccb, 0x652964ea, 0x65ac4cca, 0x37144cc8, 0xc70e65ec, 0x66e949cd,
+ 0x72312102, 0x72722203, 0x22017131, 0x74317172, 0x74712109, 0x73312104, 0x73732305, 0x210b7531,
+ 0x99077571, 0xe77f730a, 0x2504b5f7, 0x4617b092, 0x2a00460c, 0x7878d004, 0x42887839, 0x2500d101,
+ 0x4620e087, 0x21083040, 0x71419011, 0x25037878, 0x28422601, 0x2841d001, 0x2502d103, 0x21049811,
+ 0x78787141, 0xd0012882, 0xd1002842, 0x20002621, 0x90014669, 0x70087408, 0x90022001, 0xa8092120,
+ 0xfd20f001, 0x200278f9, 0x29060242, 0x2907d00b, 0x2908d012, 0x2001d001, 0x0229e02b, 0x43131d8b,
+ 0x930931ff, 0x0229e005, 0x3366460b, 0x31994313, 0x43119309, 0xe01c910d, 0x460f0229, 0x376602b2,
+ 0x4317062b, 0x431f06b5, 0x432f46ac, 0x31992599, 0x4311042d, 0x4319432f, 0x22334665, 0x04524329,
+ 0x97094311, 0x2e21910d, 0x6c21d103, 0x43112240, 0x90036421, 0x20019911, 0x06017188, 0x498e6521,
+ 0x498e6021, 0x21036061, 0x73a17361, 0x31c921ff, 0x200a5508, 0x46216760, 0xf7fe9812, 0x0005ffab,
+ 0xaa09d117, 0x9b032101, 0xf0019812, 0x4669f893, 0xf0009812, 0x4605ff9e, 0x217d4881, 0x00c94448,
+ 0xf0016800, 0xe001fcc1, 0x1e40bf00, 0x28009011, 0x4628d1fa, 0xbdf0b015, 0xb09cb5f7, 0x460c981e,
+ 0x02286805, 0x28050f00, 0x2700d011, 0x22304975, 0xa80d4479, 0xf954f7fe, 0x0f000428, 0x0328900a,
+ 0x980a0f05, 0xd0042800, 0xd1132803, 0x2701e001, 0x2d00e7ec, 0x2d03d010, 0x2800d10c, 0x2003d00a,
+ 0x20107320, 0x981e6420, 0x02006800, 0x28040f00, 0xe019d018, 0xe1952604, 0xf7fe4668, 0x4606fbcb,
+ 0xf7fe2000, 0x2e00fbc3, 0x466ad106, 0x981c4621, 0xff2af7ff, 0xd1ee0006, 0x73202000, 0x64202010,
+ 0xe0022003, 0x64202050, 0x90092006, 0x4328980a, 0x2701d100, 0x990a4620, 0x29033040, 0x2101d008,
+ 0x46217141, 0xf7fe981c, 0x0006ff35, 0xe001d1d3, 0xe7f52108, 0x2d002000, 0x2f00d004, 0x2001d001,
+ 0x2002e000, 0xa90d0100, 0x23011842, 0x981c4619, 0xf810f001, 0x46692000, 0x75089002, 0x71082003,
+ 0x90032001, 0xa80b9004, 0xa9019008, 0xf000981c, 0x0006ff10, 0xa808d1af, 0x28c27b00, 0x2101d1ab,
+ 0x2d000409, 0xd01da808, 0x460a7c40, 0x40823830, 0x46206522, 0x30ff2201, 0x30810312, 0x11126442,
+ 0x65016402, 0x73202003, 0x64202010, 0x40472001, 0x46294620, 0x30c130ff, 0x35804625, 0x29009019,
+ 0xe078d002, 0xe7e07b80, 0x2803980a, 0x2101d173, 0x20027421, 0x82617460, 0x75622206, 0x23007521,
+ 0x22074669, 0x70ca700b, 0xd04a2f00, 0x466a2182, 0x61a07051, 0x6628481c, 0x3872481b, 0x481b6668,
+ 0x981e66a8, 0x06007800, 0xe0310f00, 0x00000555, 0x52005100, 0x00004e29, 0x8b1887a0, 0xb3068f10,
+ 0x0000a704, 0x87008700, 0x87aa8700, 0x87058700, 0x87708700, 0xb70b8f10, 0x87558700, 0x87028700,
+ 0x87a08700, 0xa3808f10, 0x87808700, 0x87008f10, 0x00008730, 0x87108700, 0x42464346, 0x56010400,
+ 0x0000000c, 0x00001c0c, 0x04000472, 0x20010400, 0xd0022803, 0x728b9919, 0x9919e01a, 0x72882001,
+ 0x2181e016, 0x7059466b, 0x4bfe61a0, 0x662b48fe, 0x48fe6668, 0x210166a8, 0x77214620, 0x70423020,
+ 0x48f87001, 0x38726321, 0x6768672b, 0x67a848f7, 0xf7fe9800, 0x48f6fadb, 0x48f66328, 0x1de06128,
+ 0x30f9990a, 0xd0032900, 0xd0162f00, 0xe0152321, 0x73212101, 0x602949f0, 0x606949f0, 0x1d8949ee,
+ 0x49ef6101, 0x49ec6141, 0x65293115, 0x31d049ea, 0x21236001, 0x63010149, 0x2301e084, 0xd0012f00,
+ 0xe0002122, 0x468e2102, 0xd0012f00, 0xe000212c, 0x911a210c, 0xd0012f00, 0xe0002129, 0x910a2109,
+ 0xd0012f00, 0xe0002128, 0x91002108, 0x4ad80299, 0x3a18069b, 0x469c188a, 0x4bda431a, 0x602a431a,
+ 0x23194672, 0x015b0292, 0x9b1a18d2, 0x069b4696, 0x4bd5431a, 0x606b4313, 0x029a9b0a, 0x009b23c1,
+ 0x920a18d2, 0x1c9a60aa, 0x4663188a, 0x4bcf431a, 0x4acf4313, 0x188a642b, 0x431a4663, 0x43134bcd,
+ 0x02122203, 0x188a622b, 0x431a4663, 0x061b2303, 0x626a431a, 0x4ac662aa, 0x320d9b0a, 0x188a62eb,
+ 0x431a4663, 0x43134bc4, 0x9b006103, 0x069b4672, 0x23c1431a, 0x4313049b, 0x61434abd, 0x188a321c,
+ 0x431a4663, 0x43134bbd, 0x4672652b, 0x22f7656a, 0x188d0092, 0x431d4663, 0x46724bb9, 0x6005431d,
+ 0x221b6042, 0x18890152, 0x4ab64663, 0x43114319, 0x2f006301, 0x6c20d003, 0x43082140, 0x99196420,
+ 0x73082002, 0xb01f4630, 0xb5f7bdf0, 0x49ae460c, 0x4617b0a6, 0x44792220, 0xf7fda81d, 0x6838ff91,
+ 0x0f000200, 0xd0092807, 0x90002000, 0x03006838, 0xd0050f00, 0x73202003, 0xe0142050, 0xe7f42001,
+ 0xf7fea801, 0x4605fa17, 0xf7fe2000, 0x2d00fa0f, 0xaa01d106, 0x98264621, 0xfd76f7ff, 0xd1140006,
+ 0x73202000, 0x46252010, 0x35402108, 0x71696420, 0x98264621, 0xfd8ef7fe, 0xd1f00006, 0x03006838,
+ 0xd0030f01, 0x28030f00, 0xe09ed003, 0xaa1d2301, 0x2301e001, 0x2101aa21, 0xf0009826, 0x2008fe6b,
+ 0x22007168, 0x9826a904, 0xfbbff7ff, 0xd1220006, 0xaa02ab03, 0x4620a904, 0xf971f7ff, 0x28009800,
+ 0x2050d103, 0x20036420, 0x46257320, 0x35804870, 0x48706328, 0x68396128, 0x0f020308, 0x30ff4620,
+ 0x900130c1, 0x2a0338c0, 0x0409d006, 0x2a030f0a, 0x0f09d002, 0xe068d01b, 0x62294974, 0x60294974,
+ 0x60694974, 0x64294974, 0x39dc4971, 0x49706529, 0x60013921, 0x0149213b, 0x496d6301, 0x610139eb,
+ 0x6141496e, 0x03006838, 0xd02f0f00, 0x2201e04a, 0x06126d21, 0xd3024291, 0x218e2220, 0x2218e001,
+ 0x9b0221c2, 0xb2db0412, 0x43134c65, 0x652b4323, 0x43119b03, 0x4313b2db, 0x43234a62, 0x60034311,
+ 0x21476101, 0x614101c9, 0x29009900, 0x495ed00a, 0x495e6029, 0x21236069, 0x63010149, 0x20019901,
+ 0xe0227388, 0x6029495a, 0xe7f34952, 0x46692000, 0x27067008, 0x208270cf, 0x98007048, 0xf966f7fe,
+ 0x74202001, 0x74612102, 0x61a121e7, 0x75207567, 0x48348260, 0x6628300f, 0x38724832, 0x48386668,
+ 0x66a81ec0, 0x20029901, 0x46307308, 0xbdf0b029, 0xb0b4b5f7, 0x90004847, 0x46156810, 0x0f000200,
+ 0x2809460c, 0x2600d01b, 0x22504943, 0xa81e4479, 0xfea6f7fd, 0x90022000, 0x30404620, 0x90012104,
+ 0x68287141, 0x04000301, 0x20100f05, 0x64200f0f, 0xd0062f00, 0xd01b2f02, 0xd01c2f03, 0x2601e166,
+ 0xa804e7e2, 0xf926f7fe, 0x20009000, 0xf91ef7fe, 0x28009800, 0xaa04d107, 0x98344621, 0xfc84f7ff,
+ 0x28009000, 0x9901d1ea, 0x71482001, 0xe0002000, 0x73202003, 0x2003e008, 0x20087320, 0x2e009901,
+ 0xd1017148, 0x90022001, 0xd0032d00, 0xd0012d02, 0xd1d32d03, 0x43284638, 0x2601d100, 0xd03f2d02,
+ 0xe03b2d03, 0x04000472, 0x04020400, 0x20010400, 0x00000406, 0x24040405, 0x0820040c, 0x24043308,
+ 0x00002004, 0x03110000, 0x03060000, 0x03f90000, 0x00000305, 0x03fa0000, 0x03ed0000, 0x03de0000,
+ 0x03230000, 0x039f0000, 0x000018b6, 0xa7040705, 0x8b2007fd, 0xa704b306, 0x00000706, 0x0000a304,
+ 0x08000400, 0x0b000400, 0x0b2004fc, 0x27043306, 0x8b2004fd, 0x00004e29, 0x00001700, 0xe004d002,
+ 0xe0002004, 0x99012008, 0x21407148, 0x2e006c20, 0x4388d001, 0x4308e000, 0x46216420, 0xf7fe9834,
+ 0x9000fc39, 0xd18d2800, 0xd0082e00, 0xd0022f02, 0xd10c2f03, 0x2001e001, 0x2002e009, 0x2f02e007,
+ 0x2f03d002, 0xe001d103, 0xe0002003, 0x01002004, 0x1842a91e, 0x46192301, 0xf0009834, 0xa905fd0b,
+ 0x98349a02, 0xfa61f7ff, 0x28009000, 0xab33d17e, 0xa905aa32, 0xf7ff4620, 0x2003f812, 0x46207320,
+ 0x49fd3080, 0x49fd6301, 0x2e006101, 0x2302d001, 0x2322e000, 0xd0012e00, 0xe000210c, 0x468e212c,
+ 0xd0012e00, 0xe0002109, 0x91022129, 0xd0012e00, 0xe0002208, 0x07a92228, 0x92040d8f, 0x97014639,
+ 0x099207aa, 0x069b370b, 0x469c4317, 0x4bec431f, 0x6007431f, 0x1d0f4673, 0x431f029b, 0x43179b02,
+ 0x431f069b, 0x23019302, 0x431f049b, 0x460f6047, 0x43173720, 0x431f4663, 0x46964be1, 0x6507431f,
+ 0x37d8460f, 0x46634317, 0x4bdd431f, 0x1de3431f, 0x601f33f9, 0x43171c8f, 0x43174662, 0x43174ad8,
+ 0x460f611f, 0x37809a04, 0x43170292, 0x02922201, 0x615f3160, 0x27024311, 0x2d026319, 0x2d03d001,
+ 0x9901d10f, 0x1d494673, 0x9b024319, 0x4bcd4319, 0x62014319, 0x1d899901, 0x22ff4311, 0x640132cd,
+ 0x21005517, 0x2d0261a1, 0xe000d004, 0x2d03e03e, 0xe005d003, 0x04922201, 0x2201e001, 0x61a204d2,
+ 0xd0102e00, 0x23806c22, 0x2301431a, 0x22796422, 0x4abd5513, 0x4abd6602, 0x20016642, 0x2d007420,
+ 0x7467d007, 0x2301e006, 0x05db69a2, 0x61a2431a, 0x7461e7ef, 0x75622206, 0x82607520, 0x73014668,
+ 0xd0082e00, 0xd0022d02, 0xd0022d03, 0x2041e007, 0x2081e012, 0x2d02e010, 0x2d03d00b, 0x7341d00b,
+ 0x46692008, 0x980373c8, 0xffc0f7fd, 0xb0379800, 0x2042bdf0, 0x2082e000, 0x73484669, 0xb5f7e7f0,
+ 0x46162704, 0x2900460c, 0x2e00d04d, 0x01f9d04b, 0xf0014620, 0x2101f867, 0x35404625, 0x060871a9,
+ 0x489b6520, 0x489b6020, 0x20036060, 0x73a07360, 0x30c920ff, 0x68305501, 0x0f000200, 0xf0010003,
+ 0x060af965, 0x17110c06, 0x231d1d17, 0x46323023, 0x98004621, 0xf8d6f000, 0x2201e001, 0x0007e003,
+ 0xe01ed018, 0x46212200, 0xf7ff9800, 0xe7f6f9d2, 0x46214632, 0xf7ff9800, 0xe7f0fb7f, 0x46214632,
+ 0xf7ff9800, 0xe7eafd42, 0x46214632, 0xf7ff9800, 0xe7e4fe1f, 0xf7fd4620, 0x7830ff54, 0x0f000700,
+ 0x200171a8, 0x46387128, 0xb5ffbdfe, 0xb0812004, 0x2900460f, 0x463dd01e, 0x358135ff, 0x42496c69,
+ 0x4014460c, 0x425218d2, 0x21ff400a, 0x5dc931ca, 0x29004256, 0x6d29d10c, 0xd0092900, 0x4622e02a,
+ 0x98014639, 0xfcb1f7fe, 0xd1032800, 0x190c6c69, 0xd3f442b4, 0xbdf0b005, 0x46206d29, 0xd00e4388,
+ 0x1b322000, 0xd00c2800, 0xd80a4291, 0x46394622, 0xf7fe9801, 0x2800fcf3, 0x6d29d1ec, 0x2001e009,
+ 0x4622e7ef, 0x98014639, 0xfc8ff7fe, 0xd1e12800, 0x190c6c69, 0xd3df42b4, 0xb5ffe7dc, 0x2004b089,
+ 0x461f9c12, 0x29004616, 0x2e00d022, 0x2c00d020, 0x4608d01e, 0xf8ecf000, 0x466a2103, 0x21017011,
+ 0x21009103, 0x74109102, 0x42ac4d4b, 0x4625d800, 0x97014669, 0x95089607, 0xf0009809, 0x2800fa8a,
+ 0x08a9d106, 0x1b640089, 0x198e197f, 0xd1eb2c00, 0xbdf0b00d, 0xb08eb570, 0x2100460c, 0x9100910c,
+ 0x910d910b, 0x9102466a, 0x75114606, 0x71102003, 0x95032501, 0x95094839, 0x900a9208, 0x9504462b,
+ 0x4629aa0a, 0xf0004630, 0xa901fb55, 0xf0004630, 0x2800fa60, 0x9900d114, 0x401122f7, 0x040a4b2a,
+ 0x18d33310, 0x22ff9100, 0x32617425, 0x75255113, 0x7562220e, 0x210461a1, 0x34ff7461, 0x73e534c1,
+ 0xbd70b00e, 0x4607b5f0, 0xb0a92000, 0x4616460d, 0x49232404, 0x90269025, 0x22309027, 0x90284479,
+ 0xf7fda819, 0x6830fc0d, 0x0f000300, 0x2104d158, 0x55412045, 0x491b4628, 0x60013080, 0x6041491a,
+ 0x46384629, 0xfa26f7fe, 0xd1490004, 0x06007830, 0x28010f00, 0x1de8d10e, 0x30f94914, 0x67416701,
+ 0x67811409, 0x461a2300, 0x46384629, 0xfa27f7fe, 0xd1350004, 0xe01b6830, 0x00000406, 0x24040405,
+ 0x00200400, 0x00040400, 0x04000471, 0x00002003, 0x42464346, 0x56010400, 0x0000ffff, 0x24010485,
+ 0x00001150, 0x08180403, 0x00012404, 0x06ff06ff, 0x0f000300, 0xa9190100, 0x23011842, 0x46384619,
+ 0xfad8f000, 0x46692200, 0xf7ff4638, 0x0004f82e, 0x4633d106, 0x4629466a, 0xf7fe4638, 0x4604fe6b,
+ 0xe4f34620, 0xb089b530, 0x466d2403, 0x2501702c, 0x24000049, 0x91019503, 0x466d9402, 0x4669742c,
+ 0x92079308, 0xf9c5f000, 0xbd30b009, 0xb089b530, 0x466d2402, 0x2401702c, 0x91010049, 0x94039402,
+ 0x74292100, 0x93064669, 0xf0009205, 0xe7ebf9b2, 0x07406c00, 0x2001d501, 0x20004770, 0x6c004770,
+ 0xd5010680, 0x47702001, 0x47702000, 0x07c06c00, 0x2001d000, 0x6c004770, 0xd5010700, 0x47702001,
+ 0x47702000, 0x07806c00, 0x2001d501, 0x20004770, 0x6c004770, 0xd5010640, 0x47702001, 0x47702000,
+ 0xb085b5f3, 0x2404460e, 0xf0009805, 0x0005fcce, 0x2e00d07e, 0x7b30d07c, 0xd8792803, 0xd00a2800,
+ 0xd0082801, 0xd0062802, 0xd1042803, 0xf7ff4630, 0x2800ffd9, 0x20ffd002, 0xe00c3001, 0x2102aa03,
+ 0xf7fd9805, 0x49fefc98, 0x42889803, 0x6c30d306, 0xd4030600, 0x90002079, 0xe0219001, 0x00602400,
+ 0x31601981, 0x7e0f7e48, 0xd10b2800, 0x43472064, 0x214bd01d, 0xf0004638, 0x214bfe77, 0x42b94341,
+ 0x1c40d200, 0x283f213f, 0x4608d900, 0x0c400680, 0x30ff00a2, 0x46693001, 0x50881c64, 0xd3de2c02,
+ 0x22026828, 0x28000780, 0x2000da1c, 0x4630e01e, 0xff9ff7ff, 0x46024607, 0x9805a902, 0xfc86f7fd,
+ 0x990248e0, 0xd0092f00, 0xfe4ef000, 0x217d0880, 0x434800c9, 0xf000214b, 0xe7d2fe47, 0xfe44f000,
+ 0xe7f40840, 0x20016829, 0x60294311, 0x29006d31, 0x6d71d102, 0xd0022900, 0x9b0021c0, 0x6db1514b,
+ 0xd1022900, 0x29006df1, 0x21c4d004, 0xe0009b01, 0x514be006, 0xd0022800, 0x43906828, 0x24006028,
+ 0xb0074620, 0xb5f8bdf0, 0x20044607, 0x460e461c, 0xd0162f00, 0xd0142a00, 0xd0122c00, 0x48c14611,
+ 0xfe12f000, 0x46054601, 0x46304361, 0xfe0cf000, 0x1c40e000, 0x43694601, 0x42b14361, 0x6038d3f9,
+ 0xbdf82000, 0xb085b5f0, 0x460e4db7, 0x95004607, 0xf0009501, 0x0004fc1a, 0x2e00d02b, 0xaa02d029,
+ 0x46382102, 0xfbf7f7fd, 0x2101aa03, 0xf7fd4638, 0x2601fbf2, 0x02b64fad, 0x46394633, 0x9a024668,
+ 0xffc1f7ff, 0x46394633, 0x9a03a801, 0xffbbf7ff, 0x42a89800, 0x9500d900, 0x42a89801, 0x9501d900,
+ 0x99019800, 0xb2890400, 0x60604308, 0xb0052000, 0x2004bdf0, 0xb5f3e7fb, 0x2000b087, 0x460c9000,
+ 0x98072504, 0xfbe1f000, 0x28009003, 0x2c00d054, 0x4620d052, 0x46273040, 0x37509005, 0x30ff2600,
+ 0x90023041, 0x00b26838, 0x98030a81, 0x90011810, 0x7ba06601, 0x06c51d3f, 0x0eed7b60, 0x0d8006c0,
+ 0x7be04305, 0x0c400700, 0x46204305, 0xfed3f7ff, 0xd0022800, 0x02802001, 0x6f604305, 0xd00d2800,
+ 0x2102aa04, 0xf7fd9807, 0x2301fb96, 0x46686f61, 0xf7ff9a04, 0x9800ff68, 0x43050400, 0x67059801,
+ 0x79c09805, 0xd00e2800, 0x7c009802, 0xd00a0741, 0x22079902, 0x03407c49, 0x0d090709, 0x18800352,
+ 0x4308b280, 0x2009e001, 0x99010200, 0x60083180, 0x2e041c76, 0x2500d3b6, 0xb0094628, 0x4602bdf0,
+ 0x2004b510, 0xd0212a00, 0xd01f2900, 0x5c402044, 0xd10c2801, 0x084368d0, 0x2040005b, 0x46084303,
+ 0xfe76f7ff, 0xd0012800, 0x43032001, 0x68d060d3, 0x43082120, 0x4b5e60d0, 0x00812000, 0x6a0c1889,
+ 0x620c401c, 0x28031c40, 0x2000d3f7, 0xb510bd10, 0xfb5bf000, 0xd00b2800, 0x23012100, 0x008a07db,
+ 0x32801812, 0x431c6814, 0x1c496014, 0xd3f62904, 0xb5febd10, 0x20044605, 0x460e9000, 0xf0004628,
+ 0x0004fb44, 0x2e00d07e, 0x7830d0fc, 0xd8792803, 0x90017c30, 0x46202700, 0xfb3ff000, 0xf7ff4628,
+ 0x6960ffd6, 0x4308211e, 0x46256160, 0x68703580, 0x78306228, 0xd0022802, 0xd0022803, 0x8b30e003,
+ 0x8c30e000, 0x7b31b287, 0x1e497a30, 0x07490700, 0x09490b00, 0x99014308, 0x430807c9, 0x62684338,
+ 0x28037830, 0x69f0d14b, 0x07836a32, 0x2340d14a, 0x469e211c, 0x6bab63a9, 0x430b2101, 0x6bab63ab,
+ 0xd1fc07db, 0x430b6b2b, 0xe036632b, 0x31f91de1, 0x45724673, 0x6967d30f, 0x06bf089b, 0xe029d402,
+ 0xc080c980, 0xd2fb1e5b, 0x1a524671, 0x23206961, 0x61614319, 0x6f2be01e, 0x0d5b061b, 0xd2034293,
+ 0xc908e018, 0xc0081f12, 0xd2fa2a04, 0xd0102a00, 0x91016809, 0x468ca901, 0x23004601, 0x4667e007,
+ 0x700f783f, 0x1c7f4667, 0x46bc1c49, 0x42931c5b, 0x2200d3f5, 0x07096961, 0x2a00d401, 0x7830d1c6,
+ 0xe0002802, 0xd001e062, 0xd1482801, 0x69b26971, 0xd15b0788, 0x46842040, 0x63e8201c, 0xe0096be8,
+ 0x05f5e100, 0x3b9aca00, 0x0000ffff, 0x1dcd6500, 0xfcf0ff00, 0x43182301, 0x6be863e8, 0xd1fc07c0,
+ 0xe02a4686, 0x30ff4620, 0x30816963, 0xd521065b, 0x089b4663, 0xd2024562, 0xc980e00e, 0x1e5bc080,
+ 0x4660d2fb, 0xe0091a12, 0xdd032a00, 0xc080c980, 0xe0011f12, 0xc0802700, 0xd2f51e5b, 0x28004670,
+ 0x6b28d104, 0x43182301, 0x469e6328, 0x23406960, 0x61604318, 0x07006960, 0x2a00d401, 0x7830dcd2,
+ 0xd1032800, 0x21016b28, 0x63284308, 0xf0004620, 0x6960fa74, 0xd50b0700, 0x01006e68, 0x280e0f00,
+ 0x48fed001, 0x48fde001, 0x90001e40, 0xbdfe9800, 0xe7fa2000, 0x460eb5f8, 0x461f2104, 0x91004615,
+ 0xfa53f000, 0xd0230004, 0xd0212d00, 0x19f22100, 0x23104149, 0x1a9a2000, 0xd3194188, 0xf0004620,
+ 0x4aeffa4c, 0x200261a2, 0x19f161e0, 0x008b00b0, 0x19090081, 0x31ff31ff, 0xe0023102, 0xc140cd40,
+ 0x42981c40, 0x61a2d3fa, 0x61e02001, 0x90002000, 0xbdf89800, 0x4604b570, 0xb08a2004, 0xd0242900,
+ 0x466e2000, 0x20037030, 0x90022501, 0x74329503, 0x93012047, 0x28005c40, 0x4608d009, 0x308130ff,
+ 0x2a007a02, 0x7a42d003, 0x7a009202, 0x98029003, 0x01009b03, 0x21011842, 0x32804620, 0xffaaf7ff,
+ 0x46204669, 0xf7ff9502, 0xb00afeb4, 0xb5ffbd70, 0xb0912004, 0x900e460d, 0xd0792900, 0x30404628,
+ 0x21018f82, 0x4094460c, 0x93028fc2, 0x22039200, 0x711a466b, 0x91039104, 0x9108a90c, 0x29009913,
+ 0x2108d001, 0x2104e000, 0x99139109, 0x79c07519, 0xd0092800, 0x30ff4628, 0x79013081, 0xd0032900,
+ 0x91037941, 0x90047900, 0x9b049803, 0x19420100, 0x99033280, 0xf7ff9811, 0x6f2dff6d, 0xd0012d00,
+ 0xe0002001, 0x26002000, 0xa901900f, 0xf7ff9811, 0x900efe70, 0xd13b2800, 0x28009813, 0xa90ad019,
+ 0xab0ca80b, 0x781f2208, 0x785f700f, 0x1c407007, 0x1e921c49, 0x2a001c9b, 0x9800d1f5, 0x2800990b,
+ 0xd004980a, 0x46214008, 0xd10a4381, 0x4308e00e, 0x9800e00a, 0xd0062800, 0x4620990c, 0x28004388,
+ 0x2701d004, 0x980ce003, 0xe7f84020, 0x980f2700, 0xd00b4207, 0x43304628, 0x207dd00d, 0x210000c0,
+ 0xf9aef7fd, 0x43c02000, 0x41461e6d, 0xd1bc2f00, 0xb015980e, 0x4889bdf0, 0x900e1c40, 0xb5f7e7f8,
+ 0x460db08a, 0x980a2604, 0xf96ff000, 0xd0540007, 0xd0522d00, 0x46692001, 0x980c7008, 0x20009001,
+ 0x20047408, 0x90062400, 0x194200a0, 0x30204610, 0x29007841, 0x2301d03e, 0x59db025b, 0x0f9b059b,
+ 0x192bd003, 0x2b027f5b, 0x9102d034, 0x32307800, 0x90039205, 0x46292200, 0x980a9b0c, 0xff1af7ff,
+ 0xd12b2800, 0x21019802, 0x19420100, 0x9b033280, 0xf7ff980a, 0x2001fedf, 0x46699002, 0xf7ff980a,
+ 0x0006fde8, 0x8a68d11a, 0xd10e2800, 0x7f491929, 0xd00a2902, 0xd0082903, 0x46292200, 0x980a9b0c,
+ 0xff25f7ff, 0xd1090006, 0x2164e004, 0x21004348, 0xf946f7fd, 0x2c031c64, 0x4630d3b6, 0xbdf0b00d,
+ 0xb087b5f3, 0x2604460d, 0xf0009807, 0x0004f90e, 0x2d00d07e, 0x7c28d0fc, 0xd1022800, 0x28007f28,
+ 0x6c28d009, 0xd40406c0, 0xf7ff4628, 0x2800fc22, 0x2001d001, 0x2000e000, 0x494a9003, 0x42886828,
+ 0x9807d166, 0xf87ff7fd, 0x98074629, 0xf962f7fd, 0x30404628, 0x90029903, 0xd0022900, 0x21012200,
+ 0x4628e005, 0xfc05f7ff, 0x98024602, 0x98077981, 0xf871f7fd, 0xf7fd9807, 0x6820f85e, 0x43b02602,
+ 0x46206020, 0xf8c9f000, 0x43306820, 0x68206020, 0x40084935, 0x79499902, 0xd1012908, 0x43080289,
+ 0x43084932, 0x07897b29, 0x43010e89, 0x46296021, 0xf7ff9807, 0x68a0fc97, 0x03c92101, 0x60a04388,
+ 0xf7ff4628, 0x2800fbc3, 0x68a0d004, 0x04c92101, 0x60a04308, 0x46204629, 0xfd21f7ff, 0x98074629,
+ 0xfcb9f7ff, 0x98074629, 0xfbcaf7ff, 0x21026820, 0x60204388, 0xf0004620, 0x4628f890, 0x30507c29,
+ 0x29009004, 0x9807d01c, 0x20049005, 0xe0002100, 0x9e04e05d, 0x460f9100, 0x9101ce02, 0xd00a2900,
+ 0x9a004629, 0xf0009805, 0x2800f890, 0x9a01d106, 0x18899900, 0x1c7f9100, 0xd3ed2f04, 0xd1460006,
+ 0x28007f28, 0x9807d027, 0x20049005, 0xd0202d00, 0x9e042100, 0x460f9100, 0xe009ce02, 0x00001b59,
+ 0x5af05af0, 0x42464346, 0x0000df0f, 0xffff0000, 0x29009101, 0x4629d00a, 0x98059a00, 0xfedff7ff,
+ 0xd1062800, 0x99009a01, 0x91001889, 0x2f041c7f, 0x0006d3e2, 0x9803d11b, 0xd0172800, 0x26026820,
+ 0x60204330, 0xf7ff4628, 0x4602fb64, 0x79819802, 0xf7fc9807, 0x4629ffd0, 0xf7ff9807, 0x4629fc13,
+ 0xf7ff9807, 0x6820fb5d, 0x602043b0, 0x46302600, 0xb510e4a3, 0xf829f000, 0xd0032800, 0x6e013080,
+ 0xd5fc0789, 0xb510bd10, 0xf81ff000, 0xd0012800, 0xf813f000, 0xb570bd10, 0xf000460d, 0x0004f816,
+ 0xf000d00a, 0x2001f81a, 0x682102c0, 0xd0012d00, 0xe0004301, 0x60214381, 0x6801bd70, 0x43112201,
+ 0x68016001, 0xd1fc07c9, 0x46014770, 0x29002000, 0x4830d102, 0x68004478, 0x30804770, 0x07c96e01,
+ 0x6e01d0fc, 0xd5fc0789, 0xb5f04770, 0x4616b089, 0x4607460c, 0xf7ff2504, 0x2800ffe8, 0x2c00d048,
+ 0x30ffd046, 0x300230ff, 0x05806800, 0xd0020f80, 0x28027c60, 0x2501d025, 0x700d4669, 0x7d609601,
+ 0x7d209002, 0x20009003, 0x46207408, 0x90053018, 0x90062004, 0x22004633, 0x46384621, 0xfd9af7ff,
+ 0x21019802, 0x19020100, 0x32804638, 0xf7ff9b03, 0x4669fd61, 0x95024638, 0xfc6bf7ff, 0xd1170005,
+ 0x2500e001, 0x8a61e014, 0xd10c2900, 0x28027c60, 0x2803d009, 0x4633d007, 0x46212200, 0xf7ff4638,
+ 0x4605fda6, 0x2064e004, 0x21004348, 0xffc8f7fc, 0xe4124628, 0x00000708, 0x88014843, 0x07492204,
+ 0xda022900, 0x43918801, 0x48408001, 0x07498801, 0x8801d502, 0x80014391, 0x493d483e, 0x493e6041,
+ 0x68016081, 0x43912280, 0x43112220, 0x483b6001, 0x07c96901, 0x6901d003, 0x00490849, 0x47706101,
+ 0x4c37b5f8, 0x4a376960, 0x01804937, 0x69a0d518, 0x031b2303, 0xd0054018, 0x03122201, 0xd00a4290,
+ 0xe0092000, 0x07806910, 0x2016d001, 0x2014e000, 0x4348492d, 0x4608e000, 0x00896961, 0xe0290f49,
+ 0x4b296810, 0x0e400640, 0x08474358, 0x07c06b10, 0x2516d001, 0x2514e000, 0x43454823, 0x30404821,
+ 0x69006a06, 0xfa1af000, 0x23004632, 0xf844f000, 0x194069a1, 0x40114a1d, 0x2201d011, 0x4b1c0492,
+ 0xd0161a89, 0xd0171a89, 0xd1074291, 0x07416920, 0x46380f49, 0xf0001c49, 0xe000f907, 0x69612000,
+ 0x0f4904c9, 0xf0001c49, 0x4912f8ff, 0x60084449, 0x6819bdf8, 0xe0000c09, 0x06896819, 0xf0000e89,
+ 0x2112f8f3, 0xe7ea4348, 0x400b8000, 0x400d0000, 0xd928c520, 0x400bc000, 0x0000ffff, 0xe000e000,
+ 0x400fc000, 0x400d8000, 0x016e3600, 0x000c0000, 0x400d8100, 0x0000000c, 0x4605b5fe, 0x460c4610,
+ 0xd0734318, 0x468c46ae, 0x1aad2000, 0x419c4601, 0x4666d367, 0x24012700, 0x1ab6463d, 0xd302419d,
+ 0x463a4613, 0x46652421, 0x042f4676, 0x433e0c36, 0x1ab60c2d, 0xd304419d, 0x041b0c15, 0x0412432b,
+ 0x46653410, 0x062f4676, 0x433e0a36, 0x1ab60a2d, 0xd304419d, 0x021b0e15, 0x0212432b, 0x46653408,
+ 0x072f4676, 0x433e0936, 0x1ab6092d, 0xd304419d, 0x011b0f15, 0x0112432b, 0x46651d24, 0x07af4676,
+ 0x433e08b6, 0x1ab608ad, 0xd304419d, 0x009b0f95, 0x0092432b, 0x46651ca4, 0x07ef4676, 0x433e0876,
+ 0x1ab6086d, 0xd31a419d, 0x415b1892, 0xe0161c64, 0x46761800, 0x41494665, 0x419d1ab7, 0x90009101,
+ 0x4660d309, 0x41981ab1, 0x4684468e, 0x99019800, 0x1c402500, 0x07dd4169, 0x432a0852, 0x1e64085b,
+ 0x4672d5e6, 0xb0034663, 0xe7ffbdf0, 0x46012000, 0x46c046c0, 0x4623462a, 0xb510e7f5, 0xf0002000,
+ 0x46c0f907, 0x200146c0, 0xf8fcf000, 0x4603bd10, 0x430bb510, 0xd10f079b, 0xd30d2a04, 0xc910c808,
+ 0x42a31f12, 0xba18d0f8, 0x4288ba21, 0x2001d901, 0x2000bd10, 0xbd1043c0, 0xd0032a00, 0xd00307d3,
+ 0xe0071c52, 0xbd102000, 0x780c7803, 0x1c491c40, 0xd1071b1b, 0x780c7803, 0x1c491c40, 0xd1011b1b,
+ 0xd1f11e92, 0xbd104618, 0xc004e001, 0x29041f09, 0x078bd2fb, 0x8002d501, 0x07c91c80, 0x7002d000,
+ 0x29004770, 0x07c3d00b, 0x7002d002, 0x1e491c40, 0xd3042902, 0xd5020783, 0x1c808002, 0xe7e31e89,
+ 0xe7ee2200, 0xe7df2200, 0x09032200, 0xd32c428b, 0x428b0a03, 0x2300d311, 0xe04e469c, 0x430b4603,
+ 0x2200d43c, 0x428b0843, 0x0903d331, 0xd31c428b, 0x428b0a03, 0x4694d301, 0x09c3e03f, 0xd301428b,
+ 0x1ac001cb, 0x09834152, 0xd301428b, 0x1ac0018b, 0x09434152, 0xd301428b, 0x1ac0014b, 0x09034152,
+ 0xd301428b, 0x1ac0010b, 0x08c34152, 0xd301428b, 0x1ac000cb, 0x08834152, 0xd301428b, 0x1ac0008b,
+ 0x08434152, 0xd301428b, 0x1ac0004b, 0x1a414152, 0x4601d200, 0x46104152, 0xe05d4770, 0xd0000fca,
+ 0x10034249, 0x4240d300, 0x22004053, 0x0903469c, 0xd32d428b, 0x428b0a03, 0x22fcd312, 0xba120189,
+ 0x428b0a03, 0x0189d30c, 0x428b1192, 0x0189d308, 0x428b1192, 0x0189d304, 0x1192d03a, 0x0989e000,
+ 0x428b09c3, 0x01cbd301, 0x41521ac0, 0x428b0983, 0x018bd301, 0x41521ac0, 0x428b0943, 0x014bd301,
+ 0x41521ac0, 0x428b0903, 0x010bd301, 0x41521ac0, 0x428b08c3, 0x00cbd301, 0x41521ac0, 0x428b0883,
+ 0x008bd301, 0x41521ac0, 0x0843d2d9, 0xd301428b, 0x1ac0004b, 0x1a414152, 0x4601d200, 0x41524663,
+ 0x4610105b, 0x4240d301, 0xd5002b00, 0x47704249, 0x105b4663, 0x4240d300, 0x2000b501, 0x46c046c0,
+ 0x0000bd02, 0x20184901, 0xe7febeab, 0x00020026, 0xf000b510, 0xf000f80b, 0xbd10f802, 0xb5104770,
+ 0xd0012800, 0xffeef7ff, 0x0000bd10, 0x2100b510, 0xf000a002, 0x2001f813, 0x0000bd10, 0x41474953,
+ 0x3a545242, 0x6e624120, 0x616d726f, 0x6574206c, 0x6e696d72, 0x6f697461, 0x0000006e, 0x4605b570,
+ 0x200a460c, 0x1c6de000, 0xf812f000, 0xd0062d00, 0x28007828, 0xe002d1f7, 0xf0001c64, 0x2c00f809,
+ 0x7820d002, 0xd1f72800, 0xf000200a, 0xbd70f801, 0x4669b508, 0x20037008, 0xbd08beab, 0x0c04b5f8,
+ 0x4626b28b, 0x435eb282, 0x46100c0d, 0x43580c37, 0x19800436, 0x41792100, 0x436e4616, 0x04360c37,
+ 0x41791980, 0x436e4626, 0xbdf81989, 0x4674b430, 0x78251e64, 0x42ab1c64, 0x461dd200, 0x005b5d63,
+ 0xbc3018e3, 0x00004718, 0x08220000, 0x06180816, 0x0612041e, 0x0411060e, 0x0216060c, 0x06180000,
+ 0x060c0416, 0x0312021e, 0x01210216, 0x0116011a, 0x017d7840, 0x02faf080, 0x05f5e100, 0x07735940,
+ 0x33221100, 0x77665544, 0xbbaa9988, 0xffeeddcc, 0x0818045a, 0x24ff3008, 0x00000000, 0x00000000,
+ 0x0918055a, 0x25ff3108, 0x00000000, 0x00000000, 0x0a18065a, 0x26ff3208, 0x00000000, 0x00000000,
+ 0x2403049f, 0x00000000, 0x00000000, 0x00000000, 0x0760079f, 0x27040b20, 0x00000000, 0x00000000,
+ 0x8760879f, 0xa7048b20, 0x00000000, 0x00000000, 0x0818045a, 0x24ff3008, 0x00000000, 0x00000000,
+ 0x8b20075a, 0x0000a7ff, 0x00000000, 0x00000000, 0x0818045a, 0x24ff3008, 0x00000000, 0x00000000,
+ 0x0a18065a, 0x000026ff, 0x00000000, 0x00000000, 0x0b18075a, 0x000027ff, 0x00000000, 0x00000000,
+ 0x8a18065a, 0x0000a6ff, 0x00000000, 0x00000000, 0x8b20075a, 0x0000a7ff, 0x00000000, 0x00000000,
+ 0x402a8000, 0x00000000, 0x00000000, 0x00000000, 0x1f78a400, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x60000000, 0x00001000},
+};
+
+static const program_target_t flash = {
+ 0x20000091, // Init
+ 0x200000b7, // UnInit
+ 0x200000bb, // EraseChip
+ 0x200000cf, // EraseSector
+ 0x200000ed, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x20003a24,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(MIMXRT105x_QuadSPI_4KB_SEC_flash_prog_blob), // prog_blob size
+ MIMXRT105x_QuadSPI_4KB_SEC_flash_prog_blob, // address of prog_blob
+ 0x00000100 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/mimxrt1050_spi_flash/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/mimxrt1050_spi_flash/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the i.MXRT1050
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x60000000,
+ .flash_regions[0].end = 0x60000000 + MB(64),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20000000 + MB(64),
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/rapid_iot/flash_blob_k64.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/rapid_iot/flash_blob_k64.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,98 @@
+/**
+ * @file flash_blob_k64.c
+ * @brief Flash algorithm for the k64f
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t K64F_FLM[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x4604b570, 0x4616460d, 0x5020f24c, 0x81c84932, 0x1028f64d, 0x460881c8, 0xf0208800, 0x80080001,
+ 0x4448482e, 0xf8dcf000, 0x2001b108, 0x2000bd70, 0x4601e7fc, 0x47702000, 0x4929b510, 0x44484827,
+ 0xf8b8f000, 0xb92c4604, 0x48242100, 0xf0004448, 0x4604f9a9, 0xf837f000, 0xbd104620, 0x4604b570,
+ 0x4448481e, 0x46214b1e, 0xf00068c2, 0x4605f85d, 0x481ab93d, 0x23004448, 0x68c24621, 0xf946f000,
+ 0xf0004605, 0x4628f820, 0xb5febd70, 0x460c4605, 0x46234616, 0x46294632, 0x44484810, 0xf8f8f000,
+ 0xb9674607, 0x22012000, 0x2000e9cd, 0x46224633, 0x90024629, 0x44484809, 0xf984f000, 0xf0004607,
+ 0x4638f802, 0x4807bdfe, 0xf4206840, 0xf5000070, 0x49040070, 0x47706048, 0x40052000, 0x00000004,
+ 0x6b65666b, 0x4001f000, 0x4a0e2070, 0x20807010, 0xbf007010, 0x7800480b, 0x280009c0, 0x4809d0fa,
+ 0xf0017801, 0xb1080020, 0x47702067, 0x0010f001, 0x2068b108, 0xf001e7f9, 0xb1080001, 0xe7f42069,
+ 0xe7f22000, 0x40020000, 0x4df0e92d, 0x460d4604, 0x469a4690, 0xf0004650, 0x4606f891, 0x4630b116,
+ 0x8df0e8bd, 0x46422310, 0x46204629, 0xf86cf000, 0xb10e4606, 0xe7f34630, 0x0008eb05, 0x68e01e47,
+ 0xf1f0fbb7, 0x7011fb00, 0x68e0b140, 0xf0f0fbb7, 0x0b01f100, 0xfb0068e0, 0x1e47f00b, 0x480be011,
+ 0x68004478, 0x20096005, 0x71c84909, 0xffacf7ff, 0x69a04606, 0x69a0b108, 0xb1064780, 0x68e0e003,
+ 0x42bd4405, 0xbf00d9eb, 0xe7c94630, 0x000002ec, 0x40020000, 0x4604b570, 0x4628460d, 0xf84ef000,
+ 0xb10e4606, 0xbd704630, 0x2004b90c, 0x2044e7fb, 0x71c84902, 0xff88f7ff, 0x0000e7f5, 0x40020000,
+ 0xb9094601, 0x47702004, 0x6cc04826, 0x6003f3c0, 0x447b4b25, 0x0010f833, 0xb90a0302, 0xe7f22064,
+ 0x60082000, 0x2002604a, 0x02c06088, 0x200060c8, 0x61486108, 0xbf006188, 0x4602e7e5, 0x2004b90a,
+ 0x61914770, 0xe7fb2000, 0x4604b530, 0x2004b90c, 0x1e58bd30, 0xb9104008, 0x40101e58, 0x2065b108,
+ 0x6820e7f6, 0xd8054288, 0x0500e9d4, 0x188d4428, 0xd20142a8, 0xe7eb2066, 0xe7e92000, 0x480b4601,
+ 0xd0014281, 0x4770206b, 0xe7fc2000, 0xb90b4603, 0x47702004, 0xd801290f, 0xd0012a04, 0xe7f82004,
+ 0xe7f62000, 0x40048000, 0x0000025a, 0x6b65666b, 0x41f0e92d, 0x46884607, 0x461d4614, 0x2004b914,
+ 0x81f0e8bd, 0x462a2308, 0x46384641, 0xffbcf7ff, 0xb10e4606, 0xe7f34630, 0x4812e01f, 0x68004478,
+ 0x8000f8c0, 0x490fcc01, 0x390c4479, 0x60486809, 0x490ccc01, 0x39184479, 0x60886809, 0x490a2007,
+ 0xf7ff71c8, 0x4606ff01, 0xb10869b8, 0x478069b8, 0xe004b106, 0x0808f108, 0x2d003d08, 0xbf00d1dd,
+ 0xe7cd4630, 0x000001b0, 0x40020000, 0x4dffe92d, 0x4682b082, 0x2310460c, 0x46504621, 0xf7ff9a04,
+ 0x4683ff83, 0x0f00f1bb, 0x4658d003, 0xe8bdb006, 0xe9da8df0, 0xfbb00101, 0x4260f7f1, 0x40084279,
+ 0x42a54245, 0x443dd100, 0xe0229e04, 0x0804eba5, 0xd90045b0, 0xea4f46b0, 0x90011018, 0x4478480f,
+ 0x60046800, 0x490e2001, 0x980171c8, 0x72c80a00, 0x72889801, 0x72489805, 0xfeb6f7ff, 0xf1bb4683,
+ 0xd0010f00, 0xe7d14658, 0x0608eba6, 0x443d4444, 0x2e00bf00, 0x2000d1da, 0x0000e7c8, 0x0000010e,
+ 0x40020000, 0x4604b570, 0xb90c460d, 0xbd702004, 0x49032040, 0x460871c8, 0xf7ff7185, 0xe7f6fe95,
+ 0x40020000, 0x4dffe92d, 0x4617460c, 0xe9dd461d, 0xf8ddb80c, 0xb91da038, 0xb0042004, 0x8df0e8bd,
+ 0x463a2304, 0x98004621, 0xff1ef7ff, 0xb10e4606, 0xe7f24630, 0x4814e022, 0x68004478, 0x20026004,
+ 0x71c84912, 0xf8804608, 0x490fb00b, 0x39144479, 0x68096828, 0xf7ff6088, 0x4606fe67, 0xf1b8b15e,
+ 0xd0010f00, 0x4000f8c8, 0x0f00f1ba, 0x2000d002, 0x0000f8ca, 0x1f3fe004, 0x1d241d2d, 0xd1da2f00,
+ 0x4630bf00, 0x0000e7c9, 0x00000074, 0x40020000, 0x00000000, 0x00080000, 0x00100000, 0x00200000,
+ 0x00400000, 0x00800000, 0x01000000, 0x01000000, 0x40020004, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info_k64[] = {
+ {0, 4096},
+ };
+
+static const program_target_t flash_k64 = {
+ 0x20000021, // Init
+ 0x20000049, // UnInit
+ 0x20000059, // EraseChip
+ 0x2000007D, // EraseSector
+ 0x200000AB, // ProgramPage
+ 0x0, // Verify
+
+ // breakpoint = RAM start + 1
+ // RSB : base address is address of Execution Region PrgData in map file
+ // to access global/static data
+ // RSP : Initial stack pointer
+ {
+ 0x20000001, // breakpoint instruction address
+ 0x20000000 + 0x20 + 0x474, // static base register value (image start + header + static base offset)
+ 0x20001000 // initial stack pointer
+ },
+
+ 0x20003000, // program_buffer, any valid RAM location with +512 bytes of headroom
+ 0x20000000, // algo_start, start of RAM
+ sizeof(K64F_FLM), // algo_size, size of array above
+ K64F_FLM, // image, flash algo instruction array
+ 512 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/rapid_iot/flash_blob_kw40.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/rapid_iot/flash_blob_kw40.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,114 @@
+/**
+ * @file flash_blob_kw40.c
+ * @brief Flash algorithm for the kw40z
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+
+static const uint32_t mkw40z4_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x09032200, 0xd373428b, 0x428b0a03, 0x0b03d358, 0xd33c428b, 0x428b0c03, 0xe012d321, 0x430b4603,
+ 0x2200d47f, 0x428b0843, 0x0903d374, 0xd35f428b, 0x428b0a03, 0x0b03d344, 0xd328428b, 0x428b0c03,
+ 0x22ffd30d, 0xba120209, 0x428b0c03, 0x1212d302, 0xd0650209, 0x428b0b03, 0xe000d319, 0x0bc30a09,
+ 0xd301428b, 0x1ac003cb, 0x0b834152, 0xd301428b, 0x1ac0038b, 0x0b434152, 0xd301428b, 0x1ac0034b,
+ 0x0b034152, 0xd301428b, 0x1ac0030b, 0x0ac34152, 0xd301428b, 0x1ac002cb, 0x0a834152, 0xd301428b,
+ 0x1ac0028b, 0x0a434152, 0xd301428b, 0x1ac0024b, 0x0a034152, 0xd301428b, 0x1ac0020b, 0xd2cd4152,
+ 0x428b09c3, 0x01cbd301, 0x41521ac0, 0x428b0983, 0x018bd301, 0x41521ac0, 0x428b0943, 0x014bd301,
+ 0x41521ac0, 0x428b0903, 0x010bd301, 0x41521ac0, 0x428b08c3, 0x00cbd301, 0x41521ac0, 0x428b0883,
+ 0x008bd301, 0x41521ac0, 0x428b0843, 0x004bd301, 0x41521ac0, 0xd2001a41, 0x41524601, 0x47704610,
+ 0x0fcae05d, 0x4249d000, 0xd3001003, 0x40534240, 0x469c2200, 0x428b0903, 0x0a03d32d, 0xd312428b,
+ 0x018922fc, 0x0a03ba12, 0xd30c428b, 0x11920189, 0xd308428b, 0x11920189, 0xd304428b, 0xd03a0189,
+ 0xe0001192, 0x09c30989, 0xd301428b, 0x1ac001cb, 0x09834152, 0xd301428b, 0x1ac0018b, 0x09434152,
+ 0xd301428b, 0x1ac0014b, 0x09034152, 0xd301428b, 0x1ac0010b, 0x08c34152, 0xd301428b, 0x1ac000cb,
+ 0x08834152, 0xd301428b, 0x1ac0008b, 0xd2d94152, 0x428b0843, 0x004bd301, 0x41521ac0, 0xd2001a41,
+ 0x46634601, 0x105b4152, 0xd3014610, 0x2b004240, 0x4249d500, 0x46634770, 0xd300105b, 0xb5014240,
+ 0x46c02000, 0xbd0246c0, 0xb510480a, 0x44484908, 0xf8f0f000, 0xd1042800, 0x21004806, 0xf0004448,
+ 0x4a05f9bf, 0x230168d1, 0x4319029b, 0xbd1060d1, 0x6b65666b, 0x00000004, 0xf0003000, 0x4c0cb570,
+ 0x444c4605, 0x4b0b4601, 0x68e24620, 0xf898f000, 0xd1052800, 0x46292300, 0x68e24620, 0xf964f000,
+ 0x68ca4905, 0x029b2301, 0x60ca431a, 0x0000bd70, 0x00000004, 0x6b65666b, 0xf0003000, 0x4905b510,
+ 0x60082000, 0x44484804, 0xf8ecf000, 0xd0002800, 0xbd102001, 0x40048100, 0x00000004, 0x460cb570,
+ 0x4606460b, 0x480d4601, 0x4615b084, 0xf0004448, 0x2800f901, 0x9001d10a, 0x21019002, 0x91004807,
+ 0x4622462b, 0x44484631, 0xf978f000, 0x68ca4904, 0x029b2301, 0x60ca431a, 0xbd70b004, 0x00000004,
+ 0xf0003000, 0x47702000, 0xd0082800, 0xd802290f, 0xd1042a04, 0x2913e005, 0x2a08d801, 0x2004d001,
+ 0x20004770, 0x28004770, 0x2004d101, 0xb4104770, 0x42191e5b, 0x421ad101, 0xbc10d002, 0x47702065,
+ 0x428b6803, 0x6840d804, 0x18181889, 0xd2024288, 0x2066bc10, 0xbc104770, 0x47702000, 0x42884903,
+ 0x206bd001, 0x20004770, 0x00004770, 0x6b65666b, 0x2170480a, 0x21807001, 0x78017001, 0xd5fc0609,
+ 0x06817800, 0x2067d501, 0x06c14770, 0x2068d501, 0x07c04770, 0x2069d0fc, 0x00004770, 0x40020000,
+ 0x4605b5f8, 0x460c4616, 0xf7ff4618, 0x2800ffd7, 0x2304d12b, 0x46214632, 0xf7ff4628, 0x0007ffb4,
+ 0x19a6d123, 0x1e7668e9, 0x91004630, 0xfe38f7ff, 0xd0032900, 0x1c409e00, 0x1e764346, 0xd81342b4,
+ 0x4478480a, 0x60046800, 0x20094909, 0xf7ff71c8, 0x4607ffbf, 0x280069a8, 0x4780d000, 0xd1032f00,
+ 0x190468e8, 0xd9eb42b4, 0xbdf84638, 0x0000027e, 0x40020000, 0x4604b510, 0xf7ff4608, 0x2800ff9f,
+ 0x2c00d106, 0x4904d005, 0x71c82044, 0xffa0f7ff, 0x2004bd10, 0x0000bd10, 0x40020000, 0xd00c2800,
+ 0xd00a2a00, 0xd21a2908, 0x447b000b, 0x18db791b, 0x0705449f, 0x0d0b0907, 0x2004110f, 0x68c04770,
+ 0x6840e00a, 0x6880e008, 0x6800e006, 0x2001e004, 0x6900e002, 0x6940e000, 0x20006010, 0x206a4770,
+ 0x00004770, 0xd00a2800, 0x68c9490f, 0x0e094a0f, 0x447a0049, 0x03095a51, 0x2064d103, 0x20044770,
+ 0xb4104770, 0x60032300, 0x21026041, 0x02496081, 0x490760c1, 0x158a7a0c, 0x610240a2, 0x61837ac9,
+ 0xbc106141, 0x47704618, 0x40048040, 0x000001ae, 0x40020020, 0xd1012a00, 0x47702004, 0x461cb5ff,
+ 0x4615b081, 0x2304460e, 0x98014622, 0xff1bf7ff, 0xd11a0007, 0xd0172c00, 0x4478480d, 0x600e6801,
+ 0x6800cd02, 0x490b6041, 0x71c82006, 0xff30f7ff, 0x98014607, 0x28006980, 0x4780d000, 0xd1032f00,
+ 0x1d361f24, 0xd1e72c00, 0xb0054638, 0x0000bdf0, 0x00000166, 0x40020000, 0xd0022800, 0x20006181,
+ 0x20044770, 0x00004770, 0xb081b5ff, 0x460e4614, 0x23044605, 0xfee7f7ff, 0xd12a2800, 0x686868a9,
+ 0xfd6ef7ff, 0x42719000, 0x40014240, 0x42b7424f, 0x9800d101, 0x2c00183f, 0x1bbdd01a, 0xd90042a5,
+ 0x490d4625, 0x447908a8, 0x600e6809, 0x2201490b, 0x0a0271ca, 0x728872ca, 0x72489804, 0xfee8f7ff,
+ 0xd1062800, 0x1b649800, 0x183f1976, 0xd1e42c00, 0xb0052000, 0x0000bdf0, 0x000000da, 0x40020000,
+ 0xd1012800, 0x47702004, 0x4803b510, 0x71c22240, 0xf7ff7181, 0xbd10fecd, 0x40020000, 0xd1012b00,
+ 0x47702004, 0x461cb5f8, 0x460e4615, 0x9f082304, 0xfe99f7ff, 0xd1192800, 0xd0172d00, 0x447a4a0f,
+ 0x60066810, 0x2102480e, 0x990671c1, 0x681172c1, 0x60886820, 0xfeacf7ff, 0xd0082800, 0x29009907,
+ 0x600ed000, 0xd0012f00, 0x60392100, 0x1d24bdf8, 0x1d361f2d, 0xd1e12d00, 0x0000bdf8, 0x00000062,
+ 0x40020000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00280000, 0x40020004, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info_kw40[] = {
+ {0, 1024},
+ };
+
+static const program_target_t flash_kw40 = {
+ 0x2000027D, // Init
+ 0x200002E5, // UnInit
+ 0x20000209, // EraseChip
+ 0x2000023D, // EraseSector
+ 0x2000029D, // ProgramPage
+ 0x0, // Verify
+
+ // breakpoint = RAM start + 1
+ // RSB : base address is address of Execution Region PrgData in map file
+ // to access global/static data
+ // RSP : Initial stack pointer
+ {
+ 0x20000001, // breakpoint instruction address
+ 0x20000000 + 0x20 + 0x00000628, // static base register value (image start + header + static base offset)
+ 0x20000800 // initial stack pointer
+ },
+
+ 0x20000A00, // program_buffer, any valid RAM location with +512 bytes of headroom
+ 0x20000000, // algo_start, start of RAM
+ sizeof(mkw40z4_flash_prog_blob), // algo_size, size of array above
+ mkw40z4_flash_prog_blob, // image, flash algo instruction array
+ 512 // ram_to_flash_bytes_to_be_written
+};
+
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/rapid_iot/flash_blob_kw41.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/rapid_iot/flash_blob_kw41.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,118 @@
+/**
+ * @file flash_blob_kw41.c
+ * @brief Flash algorithm for the kw41z
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t mkw41z4_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x4937b510, 0x60082000, 0x78414836, 0x0f890649, 0xd0152902, 0x4a342100, 0x444a2900, 0xd0077011,
+ 0x229f7841, 0x70414011, 0x06497841, 0xd1fb0f89, 0x4448482e, 0xf85ef000, 0xd0002800, 0xbd102001,
+ 0xe7e82101, 0x44484828, 0x28007800, 0x4825d00a, 0x229f7841, 0x31404011, 0x78417041, 0x0f890649,
+ 0xd1fa2902, 0x47702000, 0xb5104820, 0x44484920, 0xf88cf000, 0xd1042800, 0x2100481c, 0xf0004448,
+ 0xbd10f946, 0x4c19b570, 0x444c4605, 0x4b184601, 0x68e24620, 0xf8b3f000, 0xd1052800, 0x46292300,
+ 0x68e24620, 0xf93df000, 0xb570bd70, 0x460b460c, 0x46014606, 0xb084480d, 0x44484615, 0xf8e2f000,
+ 0xd10a2800, 0x90029001, 0x48082101, 0x462b9100, 0x46314622, 0xf0004448, 0xb004f96b, 0x0000bd70,
+ 0x40048100, 0x4007e000, 0x00000004, 0x00000008, 0x6b65666b, 0xd00b2800, 0x68c949db, 0x0f090109,
+ 0xd007290f, 0x00494ad9, 0x5a51447a, 0xe0030289, 0x47702004, 0x04c92101, 0x2200b410, 0x60416002,
+ 0x60812102, 0x60c10289, 0x7a0c49d1, 0x40a3158b, 0x7ac96143, 0x62026102, 0x61816242, 0x2000bc10,
+ 0x28004770, 0x6101d002, 0x47702000, 0x47702004, 0x48c84602, 0x210168c0, 0x43080289, 0x60c849c5,
+ 0x48c54770, 0x70012170, 0x70012180, 0x06097801, 0x7800d5fc, 0xd5010681, 0x47702067, 0xd50106c1,
+ 0x47702068, 0xd0fc07c0, 0x47702069, 0xd1012800, 0x47702004, 0x4604b510, 0x48b84ab7, 0x48b86050,
+ 0xd0014281, 0xe000206b, 0x28002000, 0x4620d107, 0xffd7f7ff, 0x46204603, 0xffcaf7ff, 0xbd104618,
+ 0xd1012800, 0x47702004, 0x4614b510, 0x60622200, 0x60e260a2, 0x61626122, 0x61e261a2, 0x68c16021,
+ 0x68816061, 0xf0006840, 0x60a0f951, 0x20042108, 0x60e06121, 0x616161a0, 0x200061e0, 0xb5ffbd10,
+ 0x4615b089, 0x466a460c, 0xf7ff9809, 0x462affd9, 0x9b044621, 0xf0009809, 0x0007f90c, 0x9c00d130,
+ 0x19659e01, 0x46311e6d, 0xf0004628, 0x2900f92f, 0x1c40d002, 0x1e454370, 0xd81d42ac, 0x20090221,
+ 0x06000a09, 0x488c1809, 0x498d6041, 0x4288980c, 0x206bd001, 0x2000e000, 0xd1112800, 0xf7ff9809,
+ 0x4607ff80, 0x69009809, 0xd0002800, 0x2f004780, 0x19a4d102, 0xd9e142ac, 0xf7ff9809, 0x4638ff69,
+ 0xbdf0b00d, 0xd1012a00, 0x47702004, 0xb089b5ff, 0x461e4614, 0x466a460d, 0xf7ff9809, 0x4632ff91,
+ 0x9b034629, 0xf0009809, 0x0007f8c4, 0x9d00d12d, 0xd0262e00, 0x4870cc02, 0x99036081, 0xd0022904,
+ 0xd0072908, 0x022ae00e, 0x0a122103, 0x18510649, 0xe0076041, 0x60c1cc02, 0x2107022a, 0x06090a12,
+ 0x60411851, 0xf7ff9809, 0x4607ff3c, 0x69009809, 0xd0002800, 0x2f004780, 0x9803d103, 0x1a361945,
+ 0x9809d1d8, 0xff24f7ff, 0xb00d4638, 0x2800bdf0, 0x4a5cd005, 0x18890409, 0x60514a57, 0x2004e721,
+ 0xb5ff4770, 0x4614b08b, 0x460d461e, 0x980b466a, 0xff46f7ff, 0x46294622, 0x980b9b05, 0xf879f000,
+ 0xd1332800, 0x4629466a, 0xf7ff980b, 0x9d00ff39, 0x90089802, 0x42404269, 0x424f4001, 0xd10142af,
+ 0x183f9808, 0xd0202c00, 0x90090230, 0x42a61b7e, 0x4626d900, 0x99054630, 0xf888f000, 0x2101022a,
+ 0x06090a12, 0x493c1852, 0x9a09604a, 0x43100400, 0x608830ff, 0xf7ff980b, 0x2800fee4, 0x9808d106,
+ 0x19ad1ba4, 0x2c00183f, 0x2000d1e0, 0xbdf0b00f, 0xd1012b00, 0x47702004, 0xb089b5ff, 0x461d4616,
+ 0x466a460c, 0x98099f12, 0xfefaf7ff, 0x46214632, 0x98099b07, 0xf82df000, 0xd11d2800, 0x2e009c00,
+ 0x4929d01a, 0x18470638, 0x20010221, 0x06400a09, 0x48211809, 0x60876041, 0x60c16829, 0xf7ff9809,
+ 0x2800feb0, 0x9913d00a, 0xd0002900, 0x9914600c, 0xd0012900, 0x600a2200, 0xbdf0b00d, 0x1a769907,
+ 0x00890889, 0x9907194d, 0x2e00190c, 0xb00dd1dc, 0x2800bdf0, 0x2004d101, 0xb4104770, 0x42191e5b,
+ 0x421ad101, 0xbc10d002, 0x47702065, 0x428b6803, 0x6840d804, 0x18181889, 0xd2024288, 0x2066bc10,
+ 0xbc104770, 0x47702000, 0x40048040, 0x000003b4, 0x40020020, 0xf0003000, 0x40020000, 0x44ffffff,
+ 0x6b65666b, 0x4000ffff, 0x00ffffff, 0x460bb530, 0x20004601, 0x24012220, 0x460de009, 0x429d40d5,
+ 0x461dd305, 0x1b494095, 0x40954625, 0x46151940, 0x2d001e52, 0xbd30dcf1, 0x40020004, 0x40020010,
+ 0x00100008, 0x00200018, 0x00400030, 0x00800060, 0x010000c0, 0x02000180, 0x04000300, 0x00000600,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info_kw41[] = {
+ {0, 2048},
+ };
+
+static const program_target_t flash_kw41 = {
+ 0x20000021, // Init
+ 0x20000065, // UnInit
+ 0x20000089, // EraseChip
+ 0x200000a5, // EraseSector
+ 0x200000cb, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x20000500,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(mkw41z4_flash_prog_blob), // prog_blob size
+ mkw41z4_flash_prog_blob, // address of prog_blob
+ 0x00000400 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/rapid_iot/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/rapid_iot/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,65 @@
+/**
+ * @file target.c
+ * @brief Target information for the rapid-iot
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob_k64.c"
+#include "flash_blob_kw40.c"
+#include "flash_blob_kw41.c"
+
+// default target information is k64f
+target_cfg_t target_device = {
+ .sectors_info = sectors_info_k64,
+ .sector_info_length = (sizeof(sectors_info_k64))/(sizeof(sector_info_t)),
+#ifdef BOARD_RAPID_IOT
+ .flash_regions[0].start = 0x00014000,
+#else
+ .flash_regions[0].start = 0x00000000,
+#endif
+ .flash_regions[0].end = MB(1),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash_k64,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20030000,
+};
+
+target_cfg_t target_device_kw40 = {
+ .sectors_info = sectors_info_kw40,
+ .sector_info_length = (sizeof(sectors_info_kw40))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(160),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash_kw40,
+ .ram_regions[0].start = 0x1FFFF000,
+ .ram_regions[0].end = 0x20004000,
+};
+
+target_cfg_t target_device_kw41 = {
+ .sectors_info = sectors_info_kw41,
+ .sector_info_length = (sizeof(sectors_info_kw41))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x4000,
+ .flash_regions[0].end = KB(512),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash_kw41,
+ .ram_regions[0].start = 0x1FFF8000,
+ .ram_regions[0].end = 0x20018000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/target_reset_Kseries.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/target_reset_Kseries.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,137 @@
+/**
+ * @file target_reset_Kseries.c
+ * @brief Target reset for the Kinetis K series
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "swd_host.h"
+#include "info.h"
+#include "target_family.h"
+
+#define MDM_STATUS 0x01000000
+#define MDM_CTRL 0x01000004
+#define MDM_IDR 0x010000fc
+#define MDM_ID 0x001c0000 // K64, K22 (K series)
+
+static void target_before_init_debug(void)
+{
+ swd_set_target_reset(1);
+}
+
+static uint8_t target_unlock_sequence(void)
+{
+ uint32_t val;
+
+ // read the device ID
+ if (!swd_read_ap(MDM_IDR, &val)) {
+ return 0;
+ }
+
+ // verify the result
+ if (val != MDM_ID) {
+ return 0;
+ }
+
+ if (!swd_read_ap(MDM_STATUS, &val)) {
+ return 0;
+ }
+
+ // flash in secured mode
+ if (val & (1 << 2)) {
+ // hold the device in reset
+ swd_set_target_reset(1);
+
+ // write the mass-erase enable bit
+ if (!swd_write_ap(MDM_CTRL, 1)) {
+ return 0;
+ }
+
+ while (1) {
+ // wait until mass erase is started
+ if (!swd_read_ap(MDM_STATUS, &val)) {
+ return 0;
+ }
+
+ if (val & 1) {
+ break;
+ }
+ }
+
+ // mass erase in progress
+ while (1) {
+ // keep reading until procedure is complete
+ if (!swd_read_ap(MDM_CTRL, &val)) {
+ return 0;
+ }
+
+ if (val == 0) {
+ break;
+ }
+ }
+ }
+
+ return 1;
+}
+
+// Check Flash Configuration Field bytes at address 0x400-0x40f to ensure that flash security
+// won't be enabled.
+//
+// FCF bytes:
+// [0x0-0x7]=backdoor key
+// [0x8-0xb]=flash protection bytes
+// [0xc]=FSEC:
+// [7:6]=KEYEN (2'b10 is backdoor key enabled, all others backdoor key disabled)
+// [5:4]=MEEN (2'b10 mass erase disabled, all other mass erase enabled)
+// [3:2]=FSLACC (2'b00 and 2'b11 factory access enabled, 2'b01 and 2'b10 factory access disabled)
+// [1:0]=SEC (2'b10 flash security disabled, all other flash security enabled)
+// [0xd]=FOPT
+// [0xe]=EEPROM protection bytes (FlexNVM devices only)
+// [0xf]=data flash protection bytes (FlexNVM devices only)
+//
+// This function checks that:
+// - FSEC does not disable mass erase or secure the device.
+//
+static uint8_t security_bits_set(uint32_t addr, uint8_t *data, uint32_t size)
+{
+ const uint32_t fsec_addr = 0x40C;
+
+ if ((addr <= fsec_addr) && (addr + size) > fsec_addr) {
+ uint8_t fsec = data[fsec_addr - addr];
+
+ // make sure we can unsecure the device or dont program at all
+ if ((fsec & 0x30) == 0x20) {
+ // Dont allow programming mass-erase disabled state
+ return 1;
+ }
+
+ // Security is OK long as we can mass-erase (comment the following out to enable target security)
+ if ((fsec & 0x03) != 0x02) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+const target_family_descriptor_t g_nxp_kinetis_kseries = {
+ .family_id = kNXP_KinetisK_FamilyID,
+ .default_reset_type = kHardwareReset,
+ .target_before_init_debug = target_before_init_debug,
+ .target_unlock_sequence = target_unlock_sequence,
+ .security_bits_set = security_bits_set,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/target_reset_Lseries.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/target_reset_Lseries.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,137 @@
+/**
+ * @file target_reset_Lseries.c
+ * @brief Target reset for the Kinetis L series
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "swd_host.h"
+#include "info.h"
+#include "target_family.h"
+
+#define MDM_STATUS 0x01000000
+#define MDM_CTRL 0x01000004 //
+#define MDM_IDR 0x010000fc // read-only identification register
+#define MDM_ID 0x001c0020 // L series
+
+static void target_before_init_debug(void)
+{
+ swd_set_target_reset(1);
+}
+
+static uint8_t target_unlock_sequence(void)
+{
+ uint32_t val;
+
+ // read the device ID
+ if (!swd_read_ap(MDM_IDR, &val)) {
+ return 0;
+ }
+
+ // verify the result
+ if (val != MDM_ID) {
+ return 0;
+ }
+
+ if (!swd_read_ap(MDM_STATUS, &val)) {
+ return 0;
+ }
+
+ // flash in secured mode
+ if (val & (1 << 2)) {
+ // hold the device in reset
+ swd_set_target_reset(1);
+
+ // write the mass-erase enable bit
+ if (!swd_write_ap(MDM_CTRL, 1)) {
+ return 0;
+ }
+
+ while (1) {
+ // wait until mass erase is started
+ if (!swd_read_ap(MDM_STATUS, &val)) {
+ return 0;
+ }
+
+ if (val & 1) {
+ break;
+ }
+ }
+
+ // mass erase in progress
+ while (1) {
+ // keep reading until procedure is complete
+ if (!swd_read_ap(MDM_CTRL, &val)) {
+ return 0;
+ }
+
+ if (val == 0) {
+ break;
+ }
+ }
+ }
+
+ return 1;
+}
+
+// Check Flash Configuration Field bytes at address 0x400-0x40f to ensure that flash security
+// won't be enabled.
+//
+// FCF bytes:
+// [0x0-0x7]=backdoor key
+// [0x8-0xb]=flash protection bytes
+// [0xc]=FSEC:
+// [7:6]=KEYEN (2'b10 is backdoor key enabled, all others backdoor key disabled)
+// [5:4]=MEEN (2'b10 mass erase disabled, all other mass erase enabled)
+// [3:2]=FSLACC (2'b00 and 2'b11 factory access enabled, 2'b01 and 2'b10 factory access disabled)
+// [1:0]=SEC (2'b10 flash security disabled, all other flash security enabled)
+// [0xd]=FOPT
+// [0xe]=EEPROM protection bytes (FlexNVM devices only)
+// [0xf]=data flash protection bytes (FlexNVM devices only)
+//
+// This function checks that:
+// - FSEC does not disable mass erase or secure the device.
+//
+uint8_t static security_bits_set(uint32_t addr, uint8_t *data, uint32_t size)
+{
+ const uint32_t fsec_addr = 0x40C;
+
+ if ((addr <= fsec_addr) && (addr + size) > fsec_addr) {
+ uint8_t fsec = data[fsec_addr - addr];
+
+ // make sure we can unsecure the device or dont program at all
+ if ((fsec & 0x30) == 0x20) {
+ // Dont allow programming mass-erase disabled state
+ return 1;
+ }
+
+ // Security is OK long as we can mass-erase (comment the following out to enable target security)
+ if ((fsec & 0x03) != 0x02) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+const target_family_descriptor_t g_nxp_kinetis_lseries = {
+ .family_id = kNXP_KinetisL_FamilyID,
+ .default_reset_type = kHardwareReset,
+ .target_before_init_debug = target_before_init_debug,
+ .target_unlock_sequence = target_unlock_sequence,
+ .security_bits_set = security_bits_set,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/target_reset_k32w_series.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/target_reset_k32w_series.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,149 @@
+/**
+ * @file target_reset_K32W_series.c
+ * @brief Target reset for the Kinetis K32W series
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2016-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "swd_host.h"
+#include "info.h"
+#include "target_family.h"
+
+#define MDM_STATUS 0x01000000
+#define MDM_CTRL 0x01000004
+#define MDM_IDR 0x010000fc
+#define MDM_ID 0x001c0040 // K32 series
+
+#define MDM_STATUS_FLASH_MASS_ERASE_ACKNOWLEDGE (1 << 0)
+#define MDM_STATUS_FLASH_READY (1 << 1)
+#define MDM_STATUS_SYSTEM_SECURITY (1 << 2)
+#define MDM_STATUS_MASS_ERASE_ENABLE (1 << 5)
+
+#define MDM_CTRL_FLASH_MASS_ERASE_IN_PROGRESS (1 << 0)
+#define MDM_CTRL_SYSTEM_RESET_REQUEST (1 << 3)
+
+#define TIMEOUT_COUNT (1000000)
+
+void target_before_init_debug(void)
+{
+ swd_set_target_reset(1);
+}
+
+uint8_t target_unlock_sequence(void)
+{
+ uint32_t val;
+ uint32_t timeoutCounter = 0;
+
+ // read the device ID
+ if (!swd_read_ap(MDM_IDR, &val)) {
+ return 0;
+ }
+
+ // verify the result
+ if (val != MDM_ID) {
+ return 0;
+ }
+
+ // Wait until flash is ready.
+ do {
+ if (!swd_read_ap(MDM_STATUS, &val)) {
+ return 0;
+ }
+
+ if (++timeoutCounter > TIMEOUT_COUNT) {
+ return 0;
+ }
+ } while (!(val & MDM_STATUS_FLASH_READY));
+
+ // Check if security is enabled.
+ if (!swd_read_ap(MDM_STATUS, &val)) {
+ swd_set_target_reset(0);
+ return 0;
+ }
+
+ // flash in secured mode
+ if (val & MDM_STATUS_SYSTEM_SECURITY) {
+ // Make sure mass erase is enabled.
+ if (!(val & MDM_STATUS_MASS_ERASE_ENABLE)) {
+ return 0;
+ }
+
+ // hold the device in reset
+ swd_set_target_reset(1);
+
+ // Write the mass-erase enable and system reset request bits.
+ if (!swd_write_ap(MDM_CTRL, (MDM_CTRL_FLASH_MASS_ERASE_IN_PROGRESS | MDM_CTRL_SYSTEM_RESET_REQUEST))) {
+ swd_set_target_reset(0);
+ return 0;
+ }
+
+ // Verify mass erase has started.
+ timeoutCounter = 0;
+ do {
+ // wait until mass erase is started
+ if (!swd_read_ap(MDM_STATUS, &val)) {
+ swd_set_target_reset(0);
+ return 0;
+ }
+
+ if (++timeoutCounter > TIMEOUT_COUNT) {
+ swd_write_ap(MDM_CTRL, 0);
+ swd_set_target_reset(0);
+ return 0;
+ }
+ } while (!(val & MDM_STATUS_FLASH_MASS_ERASE_ACKNOWLEDGE));
+
+ // Wait until mass erase completes.
+ timeoutCounter = 0;
+ do {
+ // keep reading until procedure is complete
+ if (!swd_read_ap(MDM_CTRL, &val)) {
+ swd_set_target_reset(0);
+ return 0;
+ }
+
+ if (++timeoutCounter > TIMEOUT_COUNT) {
+ swd_write_ap(MDM_CTRL, 0);
+ swd_set_target_reset(0);
+ return 0;
+ }
+ } while (val & MDM_CTRL_FLASH_MASS_ERASE_IN_PROGRESS);
+
+ // Confirm the mass erase was successful.
+ if (!swd_read_ap(MDM_STATUS, &val)) {
+ swd_set_target_reset(0);
+ return 0;
+ }
+
+ // Release the device from reset.
+ swd_write_ap(MDM_CTRL, 0);
+ swd_set_target_reset(0);
+
+ if (val & MDM_STATUS_SYSTEM_SECURITY) {
+ return 0;
+ }
+ }
+
+ return 1;
+}
+
+const target_family_descriptor_t g_nxp_kinetis_k32w_series = {
+ .family_id = kNXP_KinetisK32W_FamilyID,
+ .default_reset_type = kHardwareReset,
+ .target_before_init_debug = target_before_init_debug,
+ .target_unlock_sequence = target_unlock_sequence,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/target_reset_mimxrt.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/target_reset_mimxrt.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,67 @@
+/**
+ * @file target_reset_mimxrt.c
+ * @brief Target reset for the i.MX RT series
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "swd_host.h"
+#include "info.h"
+#include "target_family.h"
+#include "cmsis_os2.h"
+
+static void target_before_init_debug(void)
+{
+ // This is for the hardware conflict (the EVK are not consider >2 debugger connection
+ // situation) with another external debugger(such as JLINK). Before drag&pull, issue a
+ // hardware reset to bring the platform to a known state and also force
+ // RESET pin to high state ensure a successfully access.
+ swd_set_target_reset(1);
+ osDelay(5);
+ swd_set_target_reset(0);
+ osDelay(5);
+}
+
+static void prerun_target_config(void)
+{
+ // In some case the CPU will enter "cannot debug" state (low power, SWD pin mux changed, etc.).
+ // Doing a hardware reset will clear those states (probably, depends on app). Also, if the
+ // external flash's data is not a valid bootable image, DAPLink cannot attached to target. A
+ // hardware reset will increase the chance to connect in this situation.
+ target_set_state(RESET_RUN);
+}
+
+static uint8_t validate_bin_nvic(const uint8_t *buf)
+{
+ if(buf[0] == 'F' && buf[1] == 'C' && buf[2] == 'F' && buf[3] == 'B')
+ {
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+const target_family_descriptor_t g_nxp_mimxrt = {
+ .family_id = kNXP_Mimxrt_FamilyID,
+ .default_reset_type = kSoftwareReset,
+ .soft_reset_type = VECTRESET,
+ .target_before_init_debug = target_before_init_debug,
+ .prerun_target_config = prerun_target_config,
+ .validate_bin_nvic = validate_bin_nvic,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/freescale/target_reset_rapid_iot.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/freescale/target_reset_rapid_iot.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,142 @@
+/**
+ * @file target_reset.c
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "swd_host.h"
+#include "info.h"
+#include "target_config.h"
+#include "target_family.h"
+
+#define MDM_STATUS 0x01000000
+#define MDM_CTRL 0x01000004
+#define MDM_IDR 0x010000fc
+#define MDM_ID_K64 0x001c0000 // K64
+#define MDM_ID_KW4 0x001c0020 // KW4
+
+/* Kinetis series ID */
+#define K_SERIES 0
+#define KW_SERIES 5
+
+/* KW4 subfamily defines */
+#define KW40 0
+#define KW41 1
+
+static uint8_t target_unlock_sequence(void)
+{
+ uint32_t val;
+
+ // read the device ID
+ if (!swd_read_ap(MDM_IDR, &val)) {
+ return 0;
+ }
+ /*
+ // verify the result
+ if (val != mdm_id) {
+ return 0;
+ }
+ */
+
+ if (!swd_read_ap(MDM_STATUS, &val)) {
+ return 0;
+ }
+
+ // flash in secured mode
+ if (val & (1 << 2)) {
+ // hold the device in reset
+ swd_set_target_reset(1);
+
+ // write the mass-erase enable bit
+ if (!swd_write_ap(MDM_CTRL, 1)) {
+ return 0;
+ }
+
+ while (1) {
+ // wait until mass erase is started
+ if (!swd_read_ap(MDM_STATUS, &val)) {
+ return 0;
+ }
+
+ if (val & 1) {
+ break;
+ }
+ }
+
+ // mass erase in progress
+ while (1) {
+ // keep reading until procedure is complete
+ if (!swd_read_ap(MDM_CTRL, &val)) {
+ return 0;
+ }
+
+ if (val == 0) {
+ break;
+ }
+ }
+ }
+
+ return 1;
+}
+
+// Check Flash Configuration Field bytes at address 0x400-0x40f to ensure that flash security
+// won't be enabled.
+//
+// FCF bytes:
+// [0x0-0x7]=backdoor key
+// [0x8-0xb]=flash protection bytes
+// [0xc]=FSEC:
+// [7:6]=KEYEN (2'b10 is backdoor key enabled, all others backdoor key disabled)
+// [5:4]=MEEN (2'b10 mass erase disabled, all other mass erase enabled)
+// [3:2]=FSLACC (2'b00 and 2'b11 factory access enabled, 2'b01 and 2'b10 factory access disabled)
+// [1:0]=SEC (2'b10 flash security disabled, all other flash security enabled)
+// [0xd]=FOPT
+// [0xe]=EEPROM protection bytes (FlexNVM devices only)
+// [0xf]=data flash protection bytes (FlexNVM devices only)
+//
+// This function checks that:
+// - FSEC does not disable mass erase or secure the device.
+//
+static uint8_t security_bits_set(uint32_t addr, uint8_t *data, uint32_t size)
+{
+ const uint32_t fsec_addr = 0x40C;
+
+ if ((addr <= fsec_addr) && (addr + size) > fsec_addr) {
+ uint8_t fsec = data[fsec_addr - addr];
+
+ // make sure we can unsecure the device or dont program at all
+ if ((fsec & 0x30) == 0x20) {
+ // Dont allow programming mass-erase disabled state
+ return 1;
+ }
+
+ // Security is OK long as we can mass-erase (comment the following out to enable target security)
+ if ((fsec & 0x03) != 0x02) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+
+const target_family_descriptor_t g_nxp_rapid_iot = {
+ .family_id = kNXP_RapidIot_FamilyID,
+ .default_reset_type = kHardwareReset,
+ .target_unlock_sequence = target_unlock_sequence,
+ .security_bits_set = security_bits_set,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/maxim/max32620/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/maxim/max32620/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,89 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the MAX32620
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+#define FLC_BASE 0x40002000
+#define CLK_DIV 0x00000060
+#define BRST_SIZE 0x00000020
+#define FLASH_BASE 0x00000000
+#define FLASH_SIZE 0x00200000
+#define FLASH_SECTOR 0x00002000
+
+#define DEV_CFG_TARGET_ADDRESS (0x0000025cUL) // From flash_algo map file
+#define FLASH_ALGO_GEN_ADDER 32
+#define DEV_CFG_LOCAL_ADDRESS ((uint8_t*)((unsigned int)flash_algo_blob + DEV_CFG_TARGET_ADDRESS + FLASH_ALGO_GEN_ADDER))
+
+const uint32_t flash_algo_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x4603b510, 0x4893460c, 0x68414448, 0xf0006888, 0xb1087080, 0xbd102001, 0x4448488e, 0x60486880,
+ 0xe7f82000, 0x488b4602, 0x68414448, 0xf0206888, 0x60884070, 0x47702000, 0x44484886, 0x68886841,
+ 0x7080f000, 0x2001b108, 0x6a484770, 0x2000b148, 0x6a486248, 0x2002b128, 0x6a486248, 0x2001b108,
+ 0x6888e7f2, 0x4070f020, 0x5000f040, 0x20006088, 0xb510e7ea, 0x44484877, 0xf7ff6844, 0xb108ffdd,
+ 0xbd102001, 0xf42068a0, 0xf440407f, 0x60a0402a, 0xf04068a0, 0x60a00002, 0x68a0bf00, 0x7080f000,
+ 0xd1fa2800, 0xf02068a0, 0x60a04070, 0xf0006a60, 0xb1080002, 0xe7e42001, 0xe7e22000, 0x4605b570,
+ 0x44484864, 0xf7ff6844, 0xb108ffb7, 0xbd702001, 0xf42068a0, 0xf440407f, 0x60a040aa, 0x68a06025,
+ 0x0004f040, 0xbf0060a0, 0xf00068a0, 0x28007080, 0x68a0d1fa, 0x4070f020, 0x6a6060a0, 0x0002f000,
+ 0x2001b108, 0x2000e7e3, 0xe92de7e1, 0x460747f0, 0x4690468a, 0x4448484f, 0x46566844, 0xf0084645,
+ 0xb1100003, 0xe8bd2001, 0x464587f0, 0xff84f7ff, 0x2001b108, 0x68a0e7f7, 0x6000f020, 0x68a060a0,
+ 0x0010f040, 0xe00e60a0, 0xcd016027, 0x68a06320, 0x0001f040, 0xbf0060a0, 0xf00068a0, 0x28007080,
+ 0x1d3fd1fa, 0x2e041f36, 0xf007d303, 0x2800001f, 0x4838d1ea, 0x68c04448, 0xd1212880, 0xd31f2e10,
+ 0xf02068a0, 0x60a00010, 0xf04068a0, 0x60a06000, 0x6027e014, 0x6320cd01, 0x6360cd01, 0x63a0cd01,
+ 0x63e0cd01, 0xf04068a0, 0x60a00001, 0x68a0bf00, 0x7080f000, 0xd1fa2800, 0x3e103710, 0xd2e82e10,
+ 0xd3192e04, 0xf02068a0, 0x60a06000, 0xf04068a0, 0x60a00010, 0x6027e00e, 0x6320cd01, 0xf04068a0,
+ 0x60a00001, 0x68a0bf00, 0x7080f000, 0xd1fa2800, 0x1f361d3f, 0xd2ee2e04, 0x68a2b306, 0x6200f022,
+ 0x68a260a2, 0x0210f042, 0xf04f60a2, 0x21ff30ff, 0x682ae005, 0x0201ea62, 0x02094010, 0x2e001e76,
+ 0x6027d1f7, 0x68a26320, 0x0201f042, 0xbf0060a2, 0xf00268a2, 0x2a007280, 0xbf00d1fa, 0xf02068a0,
+ 0x60a04070, 0xf0006a60, 0xb1080002, 0xe76a2001, 0xe7682000, 0x00000004, 0x00000000, 0x00000000,
+ FLC_BASE, CLK_DIV, BRST_SIZE, FLASH_BASE, FLASH_SIZE, FLASH_SECTOR,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 0x2000},
+ };
+
+const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000045, // UnInit
+ 0x20000093, // EraseChip
+ 0x200000DD, // EraseSector
+ 0x2000012B, // ProgramPage
+ 0x00000000, // Verify
+
+ // RSB : base address is address of Execution Region PrgData in map file
+ // to access global/static data
+ // RSP : Initial stack pointer
+ {0x20000001, 0x20000258 + FLASH_ALGO_GEN_ADDER, 0x20001000}, // {breakpoint, RSB, RSP}
+
+ 0x20000400, // program_buffer
+ 0x20000000, // algo_start
+ sizeof(flash_algo_blob), // algo_size
+ flash_algo_blob, // image
+
+ 512 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/maxim/max32620/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/maxim/max32620/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,36 @@
+/**
+ * @file target.c
+ * @brief Target information for the MAX32620
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+#include "flash_blob.c"
+
+/* ME02 -- MAX32620 2MiB Flash, 256KiB RAM */
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = 0x200000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20040000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/maxim/max32620/target_reset.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/maxim/max32620/target_reset.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,54 @@
+/**
+ * @file target_reset.c
+ * @brief Target reset for the MAX32620
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "swd_host.h"
+
+void target_before_init_debug(void)
+{
+ // any target specific sequences needed before attaching
+ // to the DAP across JTAG or SWD
+ return;
+}
+
+uint8_t target_unlock_sequence(void)
+{
+ // if the device can secure the flash and there is a way to
+ // erase all it should be implemented here.
+ return 1;
+}
+
+uint8_t target_set_state(target_state_t state)
+{
+ // invoke reset by sw (VECT_REQ or SYS_REQ) or hw (hardware IO toggle)
+ // return swd_set_target_state_sw(state);
+ //or
+ return swd_set_target_state_hw(state);
+}
+
+uint8_t security_bits_set(uint32_t addr, uint8_t *data, uint32_t size)
+{
+ // if there are security bits in the programmable flash region
+ // a check should be performed. This method is used when programming
+ // by drag-n-drop and should refuse to program an image requesting
+ // to set the device security. This can be performed with the debug channel
+ // if needed.
+ return 0;
+}
diff -r 000000000000 -r 01f31e923fe2 source/family/maxim/max32625/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/maxim/max32625/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,89 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the MAX32625
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+#define FLC_BASE 0x40002000
+#define CLK_DIV 0x00000060
+#define BRST_SIZE 0x00000020
+#define FLASH_BASE 0x00000000
+#define FLASH_SIZE 0x00080000
+#define FLASH_SECTOR 0x00002000
+
+#define DEV_CFG_TARGET_ADDRESS (0x0000025cUL) // From flash_algo map file
+#define FLASH_ALGO_GEN_ADDER 32
+#define DEV_CFG_LOCAL_ADDRESS ((uint8_t*)((unsigned int)flash_algo_blob + DEV_CFG_TARGET_ADDRESS + FLASH_ALGO_GEN_ADDER))
+
+const uint32_t flash_algo_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x4603b510, 0x4893460c, 0x68414448, 0xf0006888, 0xb1087080, 0xbd102001, 0x4448488e, 0x60486880,
+ 0xe7f82000, 0x488b4602, 0x68414448, 0xf0206888, 0x60884070, 0x47702000, 0x44484886, 0x68886841,
+ 0x7080f000, 0x2001b108, 0x6a484770, 0x2000b148, 0x6a486248, 0x2002b128, 0x6a486248, 0x2001b108,
+ 0x6888e7f2, 0x4070f020, 0x5000f040, 0x20006088, 0xb510e7ea, 0x44484877, 0xf7ff6844, 0xb108ffdd,
+ 0xbd102001, 0xf42068a0, 0xf440407f, 0x60a0402a, 0xf04068a0, 0x60a00002, 0x68a0bf00, 0x7080f000,
+ 0xd1fa2800, 0xf02068a0, 0x60a04070, 0xf0006a60, 0xb1080002, 0xe7e42001, 0xe7e22000, 0x4605b570,
+ 0x44484864, 0xf7ff6844, 0xb108ffb7, 0xbd702001, 0xf42068a0, 0xf440407f, 0x60a040aa, 0x68a06025,
+ 0x0004f040, 0xbf0060a0, 0xf00068a0, 0x28007080, 0x68a0d1fa, 0x4070f020, 0x6a6060a0, 0x0002f000,
+ 0x2001b108, 0x2000e7e3, 0xe92de7e1, 0x460747f0, 0x4690468a, 0x4448484f, 0x46566844, 0xf0084645,
+ 0xb1100003, 0xe8bd2001, 0x464587f0, 0xff84f7ff, 0x2001b108, 0x68a0e7f7, 0x6000f020, 0x68a060a0,
+ 0x0010f040, 0xe00e60a0, 0xcd016027, 0x68a06320, 0x0001f040, 0xbf0060a0, 0xf00068a0, 0x28007080,
+ 0x1d3fd1fa, 0x2e041f36, 0xf007d303, 0x2800001f, 0x4838d1ea, 0x68c04448, 0xd1212880, 0xd31f2e10,
+ 0xf02068a0, 0x60a00010, 0xf04068a0, 0x60a06000, 0x6027e014, 0x6320cd01, 0x6360cd01, 0x63a0cd01,
+ 0x63e0cd01, 0xf04068a0, 0x60a00001, 0x68a0bf00, 0x7080f000, 0xd1fa2800, 0x3e103710, 0xd2e82e10,
+ 0xd3192e04, 0xf02068a0, 0x60a06000, 0xf04068a0, 0x60a00010, 0x6027e00e, 0x6320cd01, 0xf04068a0,
+ 0x60a00001, 0x68a0bf00, 0x7080f000, 0xd1fa2800, 0x1f361d3f, 0xd2ee2e04, 0x68a2b306, 0x6200f022,
+ 0x68a260a2, 0x0210f042, 0xf04f60a2, 0x21ff30ff, 0x682ae005, 0x0201ea62, 0x02094010, 0x2e001e76,
+ 0x6027d1f7, 0x68a26320, 0x0201f042, 0xbf0060a2, 0xf00268a2, 0x2a007280, 0xbf00d1fa, 0xf02068a0,
+ 0x60a04070, 0xf0006a60, 0xb1080002, 0xe76a2001, 0xe7682000, 0x00000004, 0x00000000, 0x00000000,
+ FLC_BASE, CLK_DIV, BRST_SIZE, FLASH_BASE, FLASH_SIZE, FLASH_SECTOR,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 0x2000},
+ };
+
+const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000045, // UnInit
+ 0x20000093, // EraseChip
+ 0x200000DD, // EraseSector
+ 0x2000012B, // ProgramPage
+ 0x00000000, // Verify
+
+ // RSB : base address is address of Execution Region PrgData in map file
+ // to access global/static data
+ // RSP : Initial stack pointer
+ {0x20000001, 0x20000258 + FLASH_ALGO_GEN_ADDER, 0x20001000}, // {breakpoint, RSB, RSP}
+
+ 0x20000400, // program_buffer
+ 0x20000000, // algo_start
+ sizeof(flash_algo_blob), // algo_size
+ flash_algo_blob, // image
+
+ 512 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/maxim/max32625/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/maxim/max32625/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,36 @@
+/**
+ * @file target.c
+ * @brief Target information for the MAX32625
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+#include "flash_blob.c"
+
+/* ME03 -- MAX32625 512KiB Flash, 160KiB RAM */
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = 0x80000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20028000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/maxim/max32625/target_reset.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/maxim/max32625/target_reset.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,54 @@
+/**
+ * @file target_reset.c
+ * @brief Target reset for the MAX32625
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "swd_host.h"
+
+void target_before_init_debug(void)
+{
+ // any target specific sequences needed before attaching
+ // to the DAP across JTAG or SWD
+ return;
+}
+
+uint8_t target_unlock_sequence(void)
+{
+ // if the device can secure the flash and there is a way to
+ // erase all it should be implemented here.
+ return 1;
+}
+
+uint8_t target_set_state(target_state_t state)
+{
+ // invoke reset by sw (VECT_REQ or SYS_REQ) or hw (hardware IO toggle)
+ // return swd_set_target_state_sw(state);
+ //or
+ return swd_set_target_state_hw(state);
+}
+
+uint8_t security_bits_set(uint32_t addr, uint8_t *data, uint32_t size)
+{
+ // if there are security bits in the programmable flash region
+ // a check should be performed. This method is used when programming
+ // by drag-n-drop and should refuse to program an image requesting
+ // to set the device security. This can be performed with the debug channel
+ // if needed.
+ return 0;
+}
diff -r 000000000000 -r 01f31e923fe2 source/family/maxim/max32630/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/maxim/max32630/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,89 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the MAX32630
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+#define FLC_BASE 0x40002000
+#define CLK_DIV 0x00000060
+#define BRST_SIZE 0x00000020
+#define FLASH_BASE 0x00000000
+#define FLASH_SIZE 0x00200000
+#define FLASH_SECTOR 0x00002000
+
+#define DEV_CFG_TARGET_ADDRESS (0x0000025cUL) // From flash_algo map file
+#define FLASH_ALGO_GEN_ADDER 32
+#define DEV_CFG_LOCAL_ADDRESS ((uint8_t*)((unsigned int)flash_algo_blob + DEV_CFG_TARGET_ADDRESS + FLASH_ALGO_GEN_ADDER))
+
+const uint32_t flash_algo_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x4603b510, 0x4893460c, 0x68414448, 0xf0006888, 0xb1087080, 0xbd102001, 0x4448488e, 0x60486880,
+ 0xe7f82000, 0x488b4602, 0x68414448, 0xf0206888, 0x60884070, 0x47702000, 0x44484886, 0x68886841,
+ 0x7080f000, 0x2001b108, 0x6a484770, 0x2000b148, 0x6a486248, 0x2002b128, 0x6a486248, 0x2001b108,
+ 0x6888e7f2, 0x4070f020, 0x5000f040, 0x20006088, 0xb510e7ea, 0x44484877, 0xf7ff6844, 0xb108ffdd,
+ 0xbd102001, 0xf42068a0, 0xf440407f, 0x60a0402a, 0xf04068a0, 0x60a00002, 0x68a0bf00, 0x7080f000,
+ 0xd1fa2800, 0xf02068a0, 0x60a04070, 0xf0006a60, 0xb1080002, 0xe7e42001, 0xe7e22000, 0x4605b570,
+ 0x44484864, 0xf7ff6844, 0xb108ffb7, 0xbd702001, 0xf42068a0, 0xf440407f, 0x60a040aa, 0x68a06025,
+ 0x0004f040, 0xbf0060a0, 0xf00068a0, 0x28007080, 0x68a0d1fa, 0x4070f020, 0x6a6060a0, 0x0002f000,
+ 0x2001b108, 0x2000e7e3, 0xe92de7e1, 0x460747f0, 0x4690468a, 0x4448484f, 0x46566844, 0xf0084645,
+ 0xb1100003, 0xe8bd2001, 0x464587f0, 0xff84f7ff, 0x2001b108, 0x68a0e7f7, 0x6000f020, 0x68a060a0,
+ 0x0010f040, 0xe00e60a0, 0xcd016027, 0x68a06320, 0x0001f040, 0xbf0060a0, 0xf00068a0, 0x28007080,
+ 0x1d3fd1fa, 0x2e041f36, 0xf007d303, 0x2800001f, 0x4838d1ea, 0x68c04448, 0xd1212880, 0xd31f2e10,
+ 0xf02068a0, 0x60a00010, 0xf04068a0, 0x60a06000, 0x6027e014, 0x6320cd01, 0x6360cd01, 0x63a0cd01,
+ 0x63e0cd01, 0xf04068a0, 0x60a00001, 0x68a0bf00, 0x7080f000, 0xd1fa2800, 0x3e103710, 0xd2e82e10,
+ 0xd3192e04, 0xf02068a0, 0x60a06000, 0xf04068a0, 0x60a00010, 0x6027e00e, 0x6320cd01, 0xf04068a0,
+ 0x60a00001, 0x68a0bf00, 0x7080f000, 0xd1fa2800, 0x1f361d3f, 0xd2ee2e04, 0x68a2b306, 0x6200f022,
+ 0x68a260a2, 0x0210f042, 0xf04f60a2, 0x21ff30ff, 0x682ae005, 0x0201ea62, 0x02094010, 0x2e001e76,
+ 0x6027d1f7, 0x68a26320, 0x0201f042, 0xbf0060a2, 0xf00268a2, 0x2a007280, 0xbf00d1fa, 0xf02068a0,
+ 0x60a04070, 0xf0006a60, 0xb1080002, 0xe76a2001, 0xe7682000, 0x00000004, 0x00000000, 0x00000000,
+ FLC_BASE, CLK_DIV, BRST_SIZE, FLASH_BASE, FLASH_SIZE, FLASH_SECTOR,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 0x2000},
+ };
+
+const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000045, // UnInit
+ 0x20000093, // EraseChip
+ 0x200000DD, // EraseSector
+ 0x2000012B, // ProgramPage
+ 0x00000000, // Verify
+
+ // RSB : base address is address of Execution Region PrgData in map file
+ // to access global/static data
+ // RSP : Initial stack pointer
+ {0x20000001, 0x20000258 + FLASH_ALGO_GEN_ADDER, 0x20001000}, // {breakpoint, RSB, RSP}
+
+ 0x20000400, // program_buffer
+ 0x20000000, // algo_start
+ sizeof(flash_algo_blob), // algo_size
+ flash_algo_blob, // image
+
+ 512 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/maxim/max32630/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/maxim/max32630/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,36 @@
+/**
+ * @file target.c
+ * @brief Target information for the MAX32630
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+#include "flash_blob.c"
+
+/* ME03 -- MAX32630 2MiB Flash, 512KiB RAM */
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = 0x200000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20080000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nordic/nrf51822/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nordic/nrf51822/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,64 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the nrf51
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t nRF51822AA_FLM[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+
+ /*0x020*/ 0x47702000, 0x47702000, 0x4c26b570, 0x60602002, 0x60e02001, 0x68284d24, 0xd00207c0L, 0x60602000,
+ /*0x040*/ 0xf000bd70L, 0xe7f6f82cL, 0x4c1eb570, 0x60612102, 0x4288491e, 0x2001d302, 0xe0006160L, 0x4d1a60a0,
+ /*0x060*/ 0xf81df000L, 0x7c06828, 0x2000d0fa, 0xbd706060L, 0x4605b5f8, 0x4813088e, 0x46142101, 0x4f126041,
+ /*0x080*/ 0xc501cc01L, 0x7c06838, 0x1e76d006, 0x480dd1f8, 0x60412100, 0xbdf84608L, 0xf801f000L, 0x480ce7f2,
+ /*0x0A0*/ 0x6006840, 0xd00b0e00L, 0x6849490a, 0xd0072900L, 0x4a0a4909, 0xd00007c3L, 0x1d09600a, 0xd1f90840L,
+ /*0x0C0*/ 0x4770, 0x4001e500, 0x4001e400, 0x10001000, 0x40010400, 0x40010500, 0x40010600, 0x6e524635,
+ /*0x0E0*/ 0x0,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 1024},
+ };
+
+static const program_target_t flash = {
+ .init = 0x20000021,
+ .uninit = 0x20000025,
+ .erase_chip = 0x20000029,
+ .erase_sector = 0x20000049,
+ .program_page = 0x20000071,
+ .verify = 0x0,
+ {
+ .breakpoint = 0x20000001,
+ .static_base = 0x20000020 + 0x00000150,
+ .stack_pointer = 0x20001000
+ },
+ .program_buffer = 0x20000200,
+ .algo_start = 0x20000000,
+ .algo_size = 0x00000150,
+ .algo_blob = nRF51822AA_FLM,
+ .program_buffer_size = 512 // should be USBD_MSC_BlockSize
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nordic/nrf51822/target_16.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nordic/nrf51822/target_16.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,38 @@
+/**
+ * @file target_16.c
+ * @brief Target information for the nrf51
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(256),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20004000,
+ .erase_reset = 1,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nordic/nrf51822/target_32.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nordic/nrf51822/target_32.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,38 @@
+/**
+ * @file target_32.c
+ * @brief Target information for the nrf51
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(256),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20008000,
+ .erase_reset = 1,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nordic/nrf5x/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nordic/nrf5x/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,98 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the nrf51
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t nRF51822AA_FLM[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+
+ /*0x020*/ 0x47702000, 0x47702000, 0x4c26b570, 0x60602002, 0x60e02001, 0x68284d24, 0xd00207c0L, 0x60602000,
+ /*0x040*/ 0xf000bd70L, 0xe7f6f82cL, 0x4c1eb570, 0x60612102, 0x4288491e, 0x2001d302, 0xe0006160L, 0x4d1a60a0,
+ /*0x060*/ 0xf81df000L, 0x7c06828, 0x2000d0fa, 0xbd706060L, 0x4605b5f8, 0x4813088e, 0x46142101, 0x4f126041,
+ /*0x080*/ 0xc501cc01L, 0x7c06838, 0x1e76d006, 0x480dd1f8, 0x60412100, 0xbdf84608L, 0xf801f000L, 0x480ce7f2,
+ /*0x0A0*/ 0x6006840, 0xd00b0e00L, 0x6849490a, 0xd0072900L, 0x4a0a4909, 0xd00007c3L, 0x1d09600a, 0xd1f90840L,
+ /*0x0C0*/ 0x4770, 0x4001e500, 0x4001e400, 0x10001000, 0x40010400, 0x40010500, 0x40010600, 0x6e524635,
+ /*0x0E0*/ 0x0,
+};
+
+static const uint32_t nRF52832AA_FLM[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x47702000, 0x47702000, 0x4c2bb570, 0x60202002, 0x20014929, 0x60083108, 0x68284d28, 0xd00207c0,
+ 0x60202000, 0xf000bd70, 0xe7f6f833, 0x4c22b570, 0x60212102, 0x2f10f1b0, 0x491fd303, 0x31102001,
+ 0x491de001, 0x60081d09, 0xf0004d1c, 0x6828f821, 0xd0fa07c0, 0x60202000, 0xe92dbd70, 0xf8df41f0,
+ 0x088e8058, 0x46142101, 0xf8c84605, 0x4f131000, 0xc501cc01, 0x07c06838, 0x1e76d007, 0x2100d1f8,
+ 0x1000f8c8, 0xe8bd4608, 0xf00081f0, 0xe7f1f801, 0x6800480b, 0x00fff010, 0x490ad00c, 0x29006809,
+ 0x4908d008, 0x31fc4a08, 0xd00007c3, 0x1d09600a, 0xd1f90840, 0x00004770, 0x4001e504, 0x4001e400,
+ 0x40010404, 0x40010504, 0x6e524635, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 1024},
+ };
+
+static const program_target_t flash = { // Default is nrf51
+ .init = 0x20000021,
+ .uninit = 0x20000025,
+ .erase_chip = 0x20000029,
+ .erase_sector = 0x20000049,
+ .program_page = 0x20000071,
+ .verify = 0x0,
+ {
+ .breakpoint = 0x20000001,
+ .static_base = 0x20000020 + 0x00000150,
+ .stack_pointer = 0x20001000
+ },
+ .program_buffer = 0x20000200,
+ .algo_start = 0x20000000,
+ .algo_size = 0x00000150,
+ .algo_blob = nRF51822AA_FLM,
+ .program_buffer_size = 512 // should be USBD_MSC_BlockSize
+};
+
+static const sector_info_t sectors_info_nrf52[] = {
+ {0, 4096},
+ };
+
+static const program_target_t flash_nrf52 = {
+ .init = 0x20000021,
+ .uninit = 0x20000025,
+ .erase_chip = 0x20000029,
+ .erase_sector = 0x2000004D,
+ .program_page = 0x2000007B,
+ .verify = 0x0,
+ {
+ .breakpoint = 0x20000001,
+ .static_base = 0x20000020 + 0x00000150,
+ .stack_pointer = 0x20001000
+ },
+ .program_buffer = 0x20000200,
+ .algo_start = 0x20000000,
+ .algo_size = 0x00000150,
+ .algo_blob = nRF52832AA_FLM,
+ .program_buffer_size = 512 // should be USBD_MSC_BlockSize
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nordic/nrf5x/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nordic/nrf5x/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,86 @@
+/**
+ * @file target.c
+ * @brief Target information for the nrf51
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = { // Default is nRF51
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(256),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20004000,
+ .erase_reset = 1,
+};
+
+target_cfg_t target_device_nrf52 = {
+ .sectors_info = sectors_info_nrf52,
+ .sector_info_length = (sizeof(sectors_info_nrf52))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(512),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash_nrf52,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20008000,
+ .erase_reset = 1,
+};
+
+target_cfg_t target_device_nrf52840 = {
+ .sectors_info = sectors_info_nrf52,
+ .sector_info_length = (sizeof(sectors_info_nrf52))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(1024),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash_nrf52,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20008000,
+ .erase_reset = 1,
+};
+
+target_cfg_t target_device_nrf52840_256 = {
+ .sectors_info = sectors_info_nrf52,
+ .sector_info_length = (sizeof(sectors_info_nrf52))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(1024),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash_nrf52,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20040000,
+ .erase_reset = 1,
+};
+
+target_cfg_t target_device_nrf52_64 = {
+ .sectors_info = sectors_info_nrf52,
+ .sector_info_length = (sizeof(sectors_info_nrf52))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(512),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash_nrf52,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20010000,
+ .erase_reset = 1,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nordic/target_reset_nrf51.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nordic/target_reset_nrf51.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,62 @@
+/**
+ * @file target_reset.c
+ * @brief Target reset for the nrf51
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "swd_host.h"
+#include "DAP_config.h"
+#include "target_family.h"
+#include "target_board.h"
+
+static void swd_set_target_reset_nrf(uint8_t asserted)
+{
+ if (asserted) {
+ swd_init_debug();
+
+ //Set POWER->RESET on NRF to 1
+ if (!swd_write_ap(AP_TAR, 0x40000000 + 0x544)) {
+ return;
+ }
+
+ if (!swd_write_ap(AP_DRW, 1)) {
+ return;
+ }
+
+ //Hold RESET and SWCLK low for a minimum of 100us
+ if(g_board_info.swd_set_target_reset){
+ g_board_info.swd_set_target_reset(asserted);
+ }
+ PIN_SWCLK_TCK_CLR();
+ PIN_SWDIO_TMS_CLR();
+ //osDelay(1);
+ } else {
+ PIN_SWCLK_TCK_SET();
+ PIN_SWDIO_TMS_SET();
+ if(g_board_info.swd_set_target_reset){
+ g_board_info.swd_set_target_reset(asserted);
+ }
+ }
+}
+
+const target_family_descriptor_t g_nordic_nrf51 = {
+ .family_id = kNordic_Nrf51_FamilyID,
+ .default_reset_type = kSoftwareReset,
+ .soft_reset_type = SYSRESETREQ,
+ .swd_set_target_reset = swd_set_target_reset_nrf,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nordic/target_reset_nrf52.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nordic/target_reset_nrf52.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,68 @@
+/**
+ * @file target_reset_nrf52.c
+ * @brief Target reset for the nrf52
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "swd_host.h"
+#include "DAP_config.h"
+#include "target_family.h"
+#include "target_board.h"
+
+static void swd_set_target_reset_nrf(uint8_t asserted)
+{
+ uint32_t ap_index_return;
+
+ if (asserted) {
+ swd_init_debug();
+
+ swd_read_ap(0x010000FC, &ap_index_return);
+ if (ap_index_return == 0x02880000) {
+ // Have CTRL-AP
+ swd_write_ap(0x01000000, 1); // CTRL-AP reset hold
+ }
+ else {
+ // No CTRL-AP - Perform a soft reset
+ // 0x05FA0000 = VECTKEY, 0x4 = SYSRESETREQ
+ uint32_t swd_mem_write_data = 0x05FA0000 | 0x4;
+ swd_write_memory(0xE000ED0C, (uint8_t *) &swd_mem_write_data, 4);
+ }
+ if(g_board_info.swd_set_target_reset){ //aditional reset
+ g_board_info.swd_set_target_reset(asserted);
+ }
+ } else {
+ swd_read_ap(0x010000FC, &ap_index_return);
+ if (ap_index_return == 0x02880000) {
+ // Device has CTRL-AP
+ swd_write_ap(0x01000000, 0); // CTRL-AP reset release
+ }
+ else {
+ // No CTRL-AP - Soft reset has been performed
+ }
+ if(g_board_info.swd_set_target_reset){
+ g_board_info.swd_set_target_reset(asserted);
+ }
+ }
+}
+
+const target_family_descriptor_t g_nordic_nrf52 = {
+ .family_id = kNordic_Nrf52_FamilyID,
+ .default_reset_type = kSoftwareReset,
+ .soft_reset_type = SYSRESETREQ,
+ .swd_set_target_reset = swd_set_target_reset_nrf,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nuvoton/m252kg6ae/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nuvoton/m252kg6ae/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,195 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t M251_AP_256_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0xb088b5b0, 0x460c4613, 0x90064605, 0x92049105, 0x90032064, 0x1000f240, 0x0000f2c4, 0x60012159,
+ 0x60012116, 0x60012188, 0x21016800, 0x93024208, 0x95009401, 0xe7ffd103, 0x90072001, 0xf240e038,
+ 0xf2c42000, 0x68010000, 0x43112204, 0xf2406001, 0xf2c42004, 0x68010000, 0x60014311, 0x9803e7ff,
+ 0x91031e41, 0xd0012800, 0xe7f8e7ff, 0x0000f24c, 0x0000f2c4, 0x222d6801, 0x60014311, 0x011cf24c,
+ 0x0100f2c4, 0x2301680a, 0x600a431a, 0x42186800, 0xe7ffd103, 0x90072001, 0xf24ce00a, 0xf2c40000,
+ 0x68010000, 0x43112240, 0x20006001, 0xe7ff9007, 0xb0089807, 0xb082bdb0, 0x90014601, 0xe7ff9100,
+ 0x0010f24c, 0x0000f2c4, 0x21016800, 0xd0014208, 0xe7f5e7ff, 0x0000f24c, 0x0000f2c4, 0x222d6801,
+ 0x60014391, 0x001cf24c, 0x0000f2c4, 0x22016801, 0x60014391, 0xb0022000, 0xb0854770, 0x4603460a,
+ 0xa8029003, 0x92017001, 0xe7ff9300, 0x0010f24c, 0x0000f2c4, 0x21016800, 0xd0014208, 0xe7f5e7ff,
+ 0x0000f24c, 0x0000f2c4, 0x22406801, 0x60014311, 0x000cf24c, 0x0000f2c4, 0x60012122, 0xf24c9803,
+ 0xf2c40104, 0x60080100, 0x7800a802, 0xd1082800, 0x2000e7ff, 0xf24c43c0, 0xf2c40108, 0x60080100,
+ 0xf24ce009, 0xf2c40008, 0xf64a0000, 0xf2c02103, 0x60010155, 0xf24ce7ff, 0xf2c40010, 0x21010000,
+ 0xf3bf6001, 0xe7ff8f6f, 0x0010f24c, 0x0000f2c4, 0x21016800, 0xd0014208, 0xe7f5e7ff, 0x0000f24c,
+ 0x0000f2c4, 0x21406800, 0xd00b4208, 0xf24ce7ff, 0xf2c40000, 0x68010000, 0x43112240, 0x20016001,
+ 0xe0029004, 0x90042000, 0x9804e7ff, 0x4770b005, 0xb084b580, 0x90024601, 0x220f9802, 0x40100512,
+ 0x05522201, 0x91014290, 0xe7ffd10b, 0xf2409802, 0xf6cf0100, 0x184071e0, 0xf7ff2101, 0x9003ff7e,
+ 0x9802e005, 0xf7ff2100, 0x9003ff78, 0x9803e7ff, 0xbd80b004, 0xb088b580, 0x4603460a, 0x91059006,
+ 0x90042000, 0x93019202, 0x9804e7ff, 0x42889905, 0xe7ffd210, 0x99049806, 0x92041c4a, 0x58400089,
+ 0xffc6f7ff, 0x28009003, 0xe7ffd003, 0x90079803, 0xe7eae003, 0x90072000, 0x9807e7ff, 0xbd80b008,
+ 0xb08ab5b0, 0x460c4613, 0x90084605, 0x92069107, 0x90042000, 0x93029003, 0x95009401, 0xf24ce7ff,
+ 0xf2c40010, 0x68000000, 0x42082101, 0xe7ffd001, 0xf24ce7f5, 0xf2c40000, 0x68010000, 0x43112240,
+ 0x98076001, 0x21031cc0, 0x90074388, 0x9807e7ff, 0xd04c2800, 0xa808e7ff, 0x06407800, 0xd10f2800,
+ 0x9807e7ff, 0xd30b2880, 0x2080e7ff, 0x98089005, 0x9a069905, 0x18d29b04, 0xf83ff000, 0xe0229003,
+ 0x7800a808, 0x28000640, 0xe7ffd111, 0x28109807, 0xe7ffd30d, 0x210f9807, 0x90054388, 0x99059808,
+ 0x9b049a06, 0xf00018d2, 0x9003f828, 0x9807e00a, 0x98089005, 0x9a069905, 0x18d29b04, 0xf8e0f000,
+ 0xe7ff9003, 0x9805e7ff, 0x18089908, 0x98059008, 0x18089904, 0x98059004, 0x1a089907, 0x98039007,
+ 0xd0032800, 0x2001e7ff, 0xe0039009, 0x2000e7af, 0xe7ff9009, 0xb00a9809, 0xb5b0bdb0, 0x4613b088,
+ 0x4605460c, 0x91069007, 0x20009205, 0x98059003, 0x98069004, 0x210f300f, 0x90064388, 0x94019302,
+ 0xe7ff9500, 0x0010f24c, 0x0000f2c4, 0x21016800, 0xd0014208, 0xe7f5e7ff, 0x0000f24c, 0x0000f2c4,
+ 0x22406801, 0x60014311, 0x210f9807, 0xf24c4388, 0xf2c40104, 0x60080100, 0x000cf24c, 0x0000f2c4,
+ 0x60012127, 0x99039804, 0x92031c4a, 0x58400089, 0x0180f24c, 0x0100f2c4, 0x98046008, 0x1c4a9903,
+ 0x00899203, 0xf24c5840, 0xf2c40184, 0x60080100, 0x99039804, 0x92031c4a, 0x58400089, 0x0188f24c,
+ 0x0100f2c4, 0x98046008, 0x1c4a9903, 0x00899203, 0xf24c5840, 0xf2c4018c, 0x60080100, 0x0010f24c,
+ 0x0000f2c4, 0x60012101, 0x38109806, 0xe7ff9006, 0x28009806, 0xe7ffd046, 0xf24ce7ff, 0xf2c400c0,
+ 0x68000000, 0x42082130, 0xe7ffd001, 0x9804e7f5, 0x1c4a9903, 0x00899203, 0xf24c5840, 0xf2c40180,
+ 0x60080100, 0x99039804, 0x92031c4a, 0x58400089, 0x0184f24c, 0x0100f2c4, 0xe7ff6008, 0x00c0f24c,
+ 0x0000f2c4, 0x21c06800, 0xd0014208, 0xe7f5e7ff, 0x99039804, 0x92031c4a, 0x58400089, 0x0188f24c,
+ 0x0100f2c4, 0x98046008, 0x1c4a9903, 0x00899203, 0xf24c5840, 0xf2c4018c, 0x60080100, 0x38109806,
+ 0xe7b59006, 0xf24ce7ff, 0xf2c40010, 0x68000000, 0x42082101, 0xe7ffd001, 0x2000e7f5, 0xbdb0b008,
+ 0xb087b5b0, 0x460c4613, 0x90054605, 0x92039104, 0x1cc09804, 0x43882103, 0x93029004, 0x95009401,
+ 0xf24ce7ff, 0xf2c40010, 0x68000000, 0x42082101, 0xe7ffd001, 0xf24ce7f5, 0xf2c40000, 0x68010000,
+ 0x43112240, 0xf24c6001, 0xf2c4000c, 0x21210000, 0xe7ff6001, 0x28009804, 0xe7ffd040, 0x21039805,
+ 0xf24c4388, 0xf2c40104, 0x60080100, 0x68009803, 0x0108f24c, 0x0100f2c4, 0xf24c6008, 0xf2c40010,
+ 0x21010000, 0xf3bf6001, 0xe7ff8f6f, 0x0010f24c, 0x0000f2c4, 0x21016800, 0xd0014208, 0xe7f5e7ff,
+ 0x0000f24c, 0x0000f2c4, 0x21406800, 0xd00b4208, 0xf24ce7ff, 0xf2c40000, 0x68010000, 0x43112240,
+ 0x20016001, 0xe00c9006, 0x1d009805, 0x98039005, 0x90031d00, 0x1f009804, 0xe7bb9004, 0x90062000,
+ 0x9806e7ff, 0xbdb0b007, 0xb087b5b0, 0x460c4613, 0x90054605, 0x92039104, 0x1cc09804, 0x43882103,
+ 0x93029004, 0x95009401, 0xf24ce7ff, 0xf2c40010, 0x68000000, 0x42082101, 0xe7ffd001, 0xf24ce7f5,
+ 0xf2c40000, 0x68010000, 0x43112240, 0xf24c6001, 0xf2c4000c, 0x21000000, 0xe7ff6001, 0x28009804,
+ 0xe7ffd04c, 0x21039805, 0xf24c4388, 0xf2c40104, 0x60080100, 0x0008f24c, 0x0000f2c4, 0x60012100,
+ 0x0010f24c, 0x0000f2c4, 0x60012101, 0x8f6ff3bf, 0xf24ce7ff, 0xf2c40010, 0x68000000, 0x42082101,
+ 0xe7ffd001, 0xf24ce7f5, 0xf2c40000, 0x68000000, 0x42082140, 0xe7ffd00b, 0x0000f24c, 0x0000f2c4,
+ 0x22406801, 0x60014311, 0x90062001, 0xf24ce019, 0xf2c40008, 0x68000000, 0x68099903, 0xd0034288,
+ 0x2001e7ff, 0xe00c9006, 0x1d009805, 0x98039005, 0x90031d00, 0x1f009804, 0xe7af9004, 0x90062000,
+ 0x9806e7ff, 0xbdb0b007, 0x00000000
+};
+
+static const uint32_t M251_LD_4_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0xb089b5b0, 0x460c4613, 0x90074605, 0x92059106, 0x90032064, 0x1000f240, 0x0000f2c4, 0x60012159,
+ 0x60012116, 0x60012188, 0x21016800, 0x93024208, 0x95009401, 0xe7ffd103, 0x90082001, 0xf240e044,
+ 0xf2c42000, 0x68010000, 0x43112204, 0xf2406001, 0xf2c42004, 0x68010000, 0x60014311, 0x9803e7ff,
+ 0x91031e41, 0xd0012800, 0xe7f8e7ff, 0x0000f24c, 0x0000f2c4, 0x222d6801, 0x60014311, 0x011cf24c,
+ 0x0100f2c4, 0x2301680a, 0x600a431a, 0x42186800, 0xe7ffd103, 0x90082001, 0xf24ce016, 0xf2c40000,
+ 0x68000000, 0x42082120, 0xe7ffd103, 0x90082001, 0xf24ce00a, 0xf2c40000, 0x68010000, 0x43112240,
+ 0x20006001, 0xe7ff9008, 0xb0099808, 0xb082bdb0, 0x90014601, 0xe7ff9100, 0x0010f24c, 0x0000f2c4,
+ 0x21016800, 0xd0014208, 0xe7f5e7ff, 0x0000f24c, 0x0000f2c4, 0x222d6801, 0x60014391, 0x001cf24c,
+ 0x0000f2c4, 0x22016801, 0x60014391, 0xb0022000, 0xb5b04770, 0x4613b086, 0x4605460c, 0x91049005,
+ 0x7002a803, 0x93022001, 0x95009401, 0xbdb0b006, 0x460ab085, 0x90034603, 0x7001a802, 0x93009201,
+ 0xf24ce7ff, 0xf2c40010, 0x68000000, 0x42082101, 0xe7ffd001, 0xf24ce7f5, 0xf2c40000, 0x68010000,
+ 0x43112240, 0xf24c6001, 0xf2c4000c, 0x21220000, 0x98036001, 0x0104f24c, 0x0100f2c4, 0xa8026008,
+ 0x28007800, 0xe7ffd108, 0x43c02000, 0x0108f24c, 0x0100f2c4, 0xe0096008, 0x0008f24c, 0x0000f2c4,
+ 0x2103f64a, 0x0155f2c0, 0xe7ff6001, 0x0010f24c, 0x0000f2c4, 0x60012101, 0x8f6ff3bf, 0xf24ce7ff,
+ 0xf2c40010, 0x68000000, 0x42082101, 0xe7ffd001, 0xf24ce7f5, 0xf2c40000, 0x68000000, 0x42082140,
+ 0xe7ffd00b, 0x0000f24c, 0x0000f2c4, 0x22406801, 0x60014311, 0x90042001, 0x2000e002, 0xe7ff9004,
+ 0xb0059804, 0xb5804770, 0x4601b084, 0x98029002, 0x0512220f, 0x22014010, 0x42900552, 0xd10b9101,
+ 0x9802e7ff, 0x0100f240, 0x71e0f6cf, 0x21011840, 0xff7ef7ff, 0xe0059003, 0x21009802, 0xff78f7ff,
+ 0xe7ff9003, 0xb0049803, 0xb580bd80, 0x460ab088, 0x90064603, 0x20009105, 0x92029004, 0xe7ff9301,
+ 0x99059804, 0xd2104288, 0x9806e7ff, 0x1c4a9904, 0x00899204, 0xf7ff5840, 0x9003ffc6, 0xd0032800,
+ 0x9803e7ff, 0xe0039007, 0x2000e7ea, 0xe7ff9007, 0xb0089807, 0xb5b0bd80, 0x4613b08a, 0x4605460c,
+ 0x91079008, 0x20009206, 0x90039004, 0x94019302, 0xe7ff9500, 0x0010f24c, 0x0000f2c4, 0x21016800,
+ 0xd0014208, 0xe7f5e7ff, 0x0000f24c, 0x0000f2c4, 0x22406801, 0x60014311, 0x1cc09807, 0x43882103,
+ 0xe7ff9007, 0x28009807, 0xe7ffd04c, 0x7800a808, 0x28000640, 0xe7ffd10f, 0x28809807, 0xe7ffd30b,
+ 0x90052080, 0x99059808, 0x9b049a06, 0xf00018d2, 0x9003f83f, 0xa808e022, 0x06407800, 0xd1112800,
+ 0x9807e7ff, 0xd30d2810, 0x9807e7ff, 0x4388210f, 0x98089005, 0x9a069905, 0x18d29b04, 0xf828f000,
+ 0xe00a9003, 0x90059807, 0x99059808, 0x9b049a06, 0xf00018d2, 0x9003f8e0, 0xe7ffe7ff, 0x99089805,
+ 0x90081808, 0x99049805, 0x90041808, 0x99079805, 0x90071a08, 0x28009803, 0xe7ffd003, 0x90092001,
+ 0xe7afe003, 0x90092000, 0x9809e7ff, 0xbdb0b00a, 0xb088b5b0, 0x460c4613, 0x90074605, 0x92059106,
+ 0x90032000, 0x90049805, 0x300f9806, 0x4388210f, 0x93029006, 0x95009401, 0xf24ce7ff, 0xf2c40010,
+ 0x68000000, 0x42082101, 0xe7ffd001, 0xf24ce7f5, 0xf2c40000, 0x68010000, 0x43112240, 0x98076001,
+ 0x4388210f, 0x0104f24c, 0x0100f2c4, 0xf24c6008, 0xf2c4000c, 0x21270000, 0x98046001, 0x1c4a9903,
+ 0x00899203, 0xf24c5840, 0xf2c40180, 0x60080100, 0x99039804, 0x92031c4a, 0x58400089, 0x0184f24c,
+ 0x0100f2c4, 0x98046008, 0x1c4a9903, 0x00899203, 0xf24c5840, 0xf2c40188, 0x60080100, 0x99039804,
+ 0x92031c4a, 0x58400089, 0x018cf24c, 0x0100f2c4, 0xf24c6008, 0xf2c40010, 0x21010000, 0x98066001,
+ 0x90063810, 0x9806e7ff, 0xd0462800, 0xe7ffe7ff, 0x00c0f24c, 0x0000f2c4, 0x21306800, 0xd0014208,
+ 0xe7f5e7ff, 0x99039804, 0x92031c4a, 0x58400089, 0x0180f24c, 0x0100f2c4, 0x98046008, 0x1c4a9903,
+ 0x00899203, 0xf24c5840, 0xf2c40184, 0x60080100, 0xf24ce7ff, 0xf2c400c0, 0x68000000, 0x420821c0,
+ 0xe7ffd001, 0x9804e7f5, 0x1c4a9903, 0x00899203, 0xf24c5840, 0xf2c40188, 0x60080100, 0x99039804,
+ 0x92031c4a, 0x58400089, 0x018cf24c, 0x0100f2c4, 0x98066008, 0x90063810, 0xe7ffe7b5, 0x0010f24c,
+ 0x0000f2c4, 0x21016800, 0xd0014208, 0xe7f5e7ff, 0xb0082000, 0xb5b0bdb0, 0x4613b087, 0x4605460c,
+ 0x91049005, 0x98049203, 0x21031cc0, 0x90044388, 0x94019302, 0xe7ff9500, 0x0010f24c, 0x0000f2c4,
+ 0x21016800, 0xd0014208, 0xe7f5e7ff, 0x0000f24c, 0x0000f2c4, 0x22406801, 0x60014311, 0x000cf24c,
+ 0x0000f2c4, 0x60012121, 0x9804e7ff, 0xd0402800, 0x9805e7ff, 0x43882103, 0x0104f24c, 0x0100f2c4,
+ 0x98036008, 0xf24c6800, 0xf2c40108, 0x60080100, 0x0010f24c, 0x0000f2c4, 0x60012101, 0x8f6ff3bf,
+ 0xf24ce7ff, 0xf2c40010, 0x68000000, 0x42082101, 0xe7ffd001, 0xf24ce7f5, 0xf2c40000, 0x68000000,
+ 0x42082140, 0xe7ffd00b, 0x0000f24c, 0x0000f2c4, 0x22406801, 0x60014311, 0x90062001, 0x9805e00c,
+ 0x90051d00, 0x1d009803, 0x98049003, 0x90041f00, 0x2000e7bb, 0xe7ff9006, 0xb0079806, 0xb5b0bdb0,
+ 0x4613b087, 0x4605460c, 0x91049005, 0x98049203, 0x21031cc0, 0x90044388, 0x94019302, 0xe7ff9500,
+ 0x0010f24c, 0x0000f2c4, 0x21016800, 0xd0014208, 0xe7f5e7ff, 0x0000f24c, 0x0000f2c4, 0x22406801,
+ 0x60014311, 0x000cf24c, 0x0000f2c4, 0x60012100, 0x9804e7ff, 0xd04c2800, 0x9805e7ff, 0x43882103,
+ 0x0104f24c, 0x0100f2c4, 0xf24c6008, 0xf2c40008, 0x21000000, 0xf24c6001, 0xf2c40010, 0x21010000,
+ 0xf3bf6001, 0xe7ff8f6f, 0x0010f24c, 0x0000f2c4, 0x21016800, 0xd0014208, 0xe7f5e7ff, 0x0000f24c,
+ 0x0000f2c4, 0x21406800, 0xd00b4208, 0xf24ce7ff, 0xf2c40000, 0x68010000, 0x43112240, 0x20016001,
+ 0xe0199006, 0x0008f24c, 0x0000f2c4, 0x99036800, 0x42886809, 0xe7ffd003, 0x90062001, 0x9805e00c,
+ 0x90051d00, 0x1d009803, 0x98049003, 0x90041f00, 0x2000e7af, 0xe7ff9006, 0xb0079806, 0x0000bdb0,
+ 0x00000000
+};
+
+/**
+* List of start and size for each size of flash sector - even indexes are start, odd are size
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address flash_start + flash_size.
+*/
+static const sector_info_t sectors_info[] = {
+ { 0x00000000, 0x00000200 },
+ { 0x00100000, 0x00000200 },
+};
+
+static const program_target_t M251_AP_256_flash = {
+ 0x20000021, // Init
+ 0x200000d7, // UnInit
+ 0x0, // EraseChip
+ 0x200001f1, // EraseSector
+ 0x20000281, // ProgramPage
+ 0x200005e9, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x200006e8,
+ 0x20000900
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(M251_AP_256_flash_prog_blob), // prog_blob size
+ M251_AP_256_flash_prog_blob, // address of prog_blob
+ 0x00000200 // ram_to_flash_bytes_to_be_written
+};
+
+static const program_target_t M251_LD_4_flash = {
+ 0x20000021, // Init
+ 0x200000ef, // UnInit
+ 0x0, // EraseChip
+ 0x20000227, // EraseSector
+ 0x200002b7, // ProgramPage
+ 0x2000061f, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x20000720,
+ 0x20000a00
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(M251_LD_4_flash_prog_blob), // prog_blob size
+ M251_LD_4_flash_prog_blob, // address of prog_blob
+ 0x00000200 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nuvoton/m252kg6ae/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nuvoton/m252kg6ae/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,41 @@
+/**
+ * @file target.c
+ * @brief Target information for the m252kg6ae
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x00000000,
+ .flash_regions[0].end = 0x00040000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *)&M251_AP_256_flash,
+ .flash_regions[1].start = 0x00100000,
+ .flash_regions[1].end = 0x00101000,
+ .flash_regions[1].flags = kRegionIsDefault,
+ .flash_regions[1].flash_algo = (program_target_t *)&M251_LD_4_flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20008000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nuvoton/m263kiaae/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nuvoton/m263kiaae/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,147 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t M261_AP_512_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0xb087b5b0, 0x460c4613, 0x90054605, 0x92039104, 0x94019302, 0xe7ff9500, 0x6800481f, 0x42082101,
+ 0xe7ffd001, 0x481de7f8, 0x22406801, 0x60014311, 0x491b9805, 0x98046008, 0x6008491a, 0x28009803,
+ 0xe7ffd105, 0x43c02000, 0x60084917, 0x4816e003, 0x60014916, 0x4816e7ff, 0x60012101, 0x8f6ff3bf,
+ 0x480de7ff, 0x21016800, 0xd0014208, 0xe7f8e7ff, 0x6800480a, 0x42082140, 0xe7ffd008, 0x68014807,
+ 0x43112240, 0x20016001, 0xe0029006, 0x90062000, 0x9806e7ff, 0xbdb0b007, 0x4000c0c0, 0x4000c000,
+ 0x4000c00c, 0x4000c004, 0x4000c008, 0x0055aa03, 0x4000c010, 0xb087b5b0, 0x460c4613, 0x90054605,
+ 0x92039104, 0x2159481d, 0x21166001, 0x21886001, 0x68006001, 0x42082101, 0x94019302, 0xd1039500,
+ 0x2001e7ff, 0xe0269006, 0x68014815, 0x43112204, 0x48146001, 0x43116801, 0xe7ff6001, 0x68004812,
+ 0x42082110, 0xe7ffd101, 0x4810e7f8, 0x22016801, 0x60014311, 0x600a490e, 0x42106800, 0xe7ffd103,
+ 0x90062001, 0x4809e007, 0x22406801, 0x60014311, 0x90062000, 0x9806e7ff, 0xbdb0b007, 0x40000100,
+ 0x40000200, 0x40000204, 0x40000250, 0x4000c000, 0x4000c01c, 0x4601b082, 0x91009001, 0x4809e7ff,
+ 0x21016800, 0xd0014208, 0xe7f8e7ff, 0x68014806, 0x43912201, 0x48056001, 0x60012100, 0xb0024608,
+ 0x46c04770, 0x4000c0c0, 0x4000c000, 0x4000c01c, 0xb084b580, 0x90034601, 0x22019803, 0x43980713,
+ 0x98039003, 0x40184b0e, 0x98039003, 0x051b230f, 0x05524018, 0x91014290, 0xe7ffd107, 0x49099803,
+ 0x90031840, 0x90022001, 0x2000e002, 0xe7ff9002, 0x9a029903, 0xf7ff2022, 0xb004ff13, 0x46c0bd80,
+ 0xfffff800, 0xffe00000, 0xb086b580, 0x4603460a, 0x91039004, 0x90022000, 0x93009201, 0x9802e7ff,
+ 0x42889903, 0xe7ffd20f, 0x99029804, 0x92021c4a, 0x58400089, 0xffbcf7ff, 0xd0032800, 0x2001e7ff,
+ 0xe0039005, 0x2000e7eb, 0xe7ff9005, 0xb0069805, 0x46c0bd80, 0xb087b5b0, 0x460c4613, 0x90054605,
+ 0x92039104, 0x1cc09804, 0x43882103, 0x98059004, 0x07092101, 0x90054388, 0x94019302, 0xe7ff9500,
+ 0x68004822, 0x42082101, 0xe7ffd001, 0x4820e7f8, 0x22406801, 0x60014311, 0x2121481e, 0xe7ff6001,
+ 0x28009804, 0xe7ffd02c, 0x491b9805, 0x98036008, 0x491a6800, 0x481a6008, 0x60012101, 0x8f6ff3bf,
+ 0x4812e7ff, 0x21016800, 0xd0014208, 0xe7f8e7ff, 0x6800480f, 0x42082140, 0xe7ffd008, 0x6801480c,
+ 0x43112240, 0x20016001, 0xe00c9006, 0x1d009805, 0x98039005, 0x90031d00, 0x1f009804, 0xe7cf9004,
+ 0x90062000, 0x9806e7ff, 0xbdb0b007, 0x4000c0c0, 0x4000c000, 0x4000c00c, 0x4000c004, 0x4000c008,
+ 0x4000c010, 0xb088b5b0, 0x460c4613, 0x90064605, 0x92049105, 0x1cc09805, 0x43882103, 0x98069005,
+ 0x07092101, 0x90034008, 0x43889806, 0x93029006, 0x95009401, 0x4826e7ff, 0x21016800, 0xd0014208,
+ 0xe7f8e7ff, 0x68014823, 0x43112240, 0x48226001, 0x60012100, 0x9805e7ff, 0xd0322800, 0x9806e7ff,
+ 0x6008491e, 0x2101481e, 0xf3bf6001, 0xe7ff8f6f, 0x68004817, 0x42082101, 0xe7ffd001, 0x4815e7f8,
+ 0x21406800, 0xd0084208, 0x4812e7ff, 0x22406801, 0x60014311, 0x90072001, 0x4812e016, 0x99046800,
+ 0x42886809, 0xe7ffd003, 0x90072001, 0x9806e00c, 0x90061d00, 0x1d009804, 0x98059004, 0x90051f00,
+ 0x2000e7c9, 0xe7ff9007, 0xb0089807, 0x46c0bdb0, 0x4000c0c0, 0x4000c000, 0x4000c00c, 0x4000c004,
+ 0x4000c010, 0x4000c008, 0x00000000
+};
+
+static const uint32_t M261_LD_4_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0xb087b5b0, 0x460c4613, 0x90054605, 0x92039104, 0x94019302, 0xe7ff9500, 0x6800481f, 0x42082101,
+ 0xe7ffd001, 0x481de7f8, 0x22406801, 0x60014311, 0x491b9805, 0x98046008, 0x6008491a, 0x28009803,
+ 0xe7ffd105, 0x43c02000, 0x60084917, 0x4816e003, 0x60014916, 0x4816e7ff, 0x60012101, 0x8f6ff3bf,
+ 0x480de7ff, 0x21016800, 0xd0014208, 0xe7f8e7ff, 0x6800480a, 0x42082140, 0xe7ffd008, 0x68014807,
+ 0x43112240, 0x20016001, 0xe0029006, 0x90062000, 0x9806e7ff, 0xbdb0b007, 0x4000c0c0, 0x4000c000,
+ 0x4000c00c, 0x4000c004, 0x4000c008, 0x0055aa03, 0x4000c010, 0xb087b5b0, 0x460c4613, 0x90054605,
+ 0x92039104, 0x2159481d, 0x21166001, 0x21886001, 0x68006001, 0x42082101, 0x94019302, 0xd1039500,
+ 0x2001e7ff, 0xe0269006, 0x68014815, 0x43112204, 0x48146001, 0x43116801, 0xe7ff6001, 0x68004812,
+ 0x42082110, 0xe7ffd101, 0x4810e7f8, 0x22016801, 0x60014311, 0x600a490e, 0x42106800, 0xe7ffd103,
+ 0x90062001, 0x4809e007, 0x22406801, 0x60014311, 0x90062000, 0x9806e7ff, 0xbdb0b007, 0x40000100,
+ 0x40000200, 0x40000204, 0x40000250, 0x4000c000, 0x4000c01c, 0x4601b082, 0x91009001, 0x4809e7ff,
+ 0x21016800, 0xd0014208, 0xe7f8e7ff, 0x68014806, 0x43912201, 0x48056001, 0x60012100, 0xb0024608,
+ 0x46c04770, 0x4000c0c0, 0x4000c000, 0x4000c01c, 0xb084b580, 0x90034601, 0x22019803, 0x43980713,
+ 0x98039003, 0x40184b0e, 0x98039003, 0x051b230f, 0x05524018, 0x91014290, 0xe7ffd107, 0x49099803,
+ 0x90031840, 0x90022001, 0x2000e002, 0xe7ff9002, 0x9a029903, 0xf7ff2022, 0xb004ff13, 0x46c0bd80,
+ 0xfffff800, 0xffe00000, 0xb086b580, 0x4603460a, 0x91039004, 0x90022000, 0x93009201, 0x9802e7ff,
+ 0x42889903, 0xe7ffd20f, 0x99029804, 0x92021c4a, 0x58400089, 0xffbcf7ff, 0xd0032800, 0x2001e7ff,
+ 0xe0039005, 0x2000e7eb, 0xe7ff9005, 0xb0069805, 0x46c0bd80, 0xb087b5b0, 0x460c4613, 0x90054605,
+ 0x92039104, 0x1cc09804, 0x43882103, 0x98059004, 0x07092101, 0x90054388, 0x94019302, 0xe7ff9500,
+ 0x68004822, 0x42082101, 0xe7ffd001, 0x4820e7f8, 0x22406801, 0x60014311, 0x2121481e, 0xe7ff6001,
+ 0x28009804, 0xe7ffd02c, 0x491b9805, 0x98036008, 0x491a6800, 0x481a6008, 0x60012101, 0x8f6ff3bf,
+ 0x4812e7ff, 0x21016800, 0xd0014208, 0xe7f8e7ff, 0x6800480f, 0x42082140, 0xe7ffd008, 0x6801480c,
+ 0x43112240, 0x20016001, 0xe00c9006, 0x1d009805, 0x98039005, 0x90031d00, 0x1f009804, 0xe7cf9004,
+ 0x90062000, 0x9806e7ff, 0xbdb0b007, 0x4000c0c0, 0x4000c000, 0x4000c00c, 0x4000c004, 0x4000c008,
+ 0x4000c010, 0xb088b5b0, 0x460c4613, 0x90064605, 0x92049105, 0x1cc09805, 0x43882103, 0x98069005,
+ 0x07092101, 0x90034008, 0x43889806, 0x93029006, 0x95009401, 0x4826e7ff, 0x21016800, 0xd0014208,
+ 0xe7f8e7ff, 0x68014823, 0x43112240, 0x48226001, 0x60012100, 0x9805e7ff, 0xd0322800, 0x9806e7ff,
+ 0x6008491e, 0x2101481e, 0xf3bf6001, 0xe7ff8f6f, 0x68004817, 0x42082101, 0xe7ffd001, 0x4815e7f8,
+ 0x21406800, 0xd0084208, 0x4812e7ff, 0x22406801, 0x60014311, 0x90072001, 0x4812e016, 0x99046800,
+ 0x42886809, 0xe7ffd003, 0x90072001, 0x9806e00c, 0x90061d00, 0x1d009804, 0x98059004, 0x90051f00,
+ 0x2000e7c9, 0xe7ff9007, 0xb0089807, 0x46c0bdb0, 0x4000c0c0, 0x4000c000, 0x4000c00c, 0x4000c004,
+ 0x4000c010, 0x4000c008, 0x00000000
+};
+
+/**
+* List of start and size for each size of flash sector - even indexes are start, odd are size
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address flash_start + flash_size.
+*/
+static const sector_info_t sectors_info[] = {
+ { 0x00000000, 0x00000800 },
+ { 0x00100000, 0x00000800 },
+};
+
+static const program_target_t M261_AP_512_flash = {
+ 0x200000d5, // Init
+ 0x20000175, // UnInit
+ 0x0, // EraseChip
+ 0x200001b1, // EraseSector
+ 0x20000255, // ProgramPage
+ 0x20000325, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x20000408,
+ 0x20000700
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(M261_AP_512_flash_prog_blob), // prog_blob size
+ M261_AP_512_flash_prog_blob, // address of prog_blob
+ 0x00000800 // ram_to_flash_bytes_to_be_written
+};
+
+static const program_target_t M261_LD_4_flash = {
+ 0x200000d5, // Init
+ 0x20000175, // UnInit
+ 0x0, // EraseChip
+ 0x200001b1, // EraseSector
+ 0x20000255, // ProgramPage
+ 0x20000325, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x20000408,
+ 0x20000700
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(M261_LD_4_flash_prog_blob), // prog_blob size
+ M261_LD_4_flash_prog_blob, // address of prog_blob
+ 0x00000800 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nuvoton/m263kiaae/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nuvoton/m263kiaae/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,41 @@
+/**
+ * @file target.c
+ * @brief Target information for the m263kiaae
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x00000000,
+ .flash_regions[0].end = 0x00080000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *)&M261_AP_512_flash,
+ .flash_regions[1].start = 0x00100000,
+ .flash_regions[1].end = 0x00101000,
+ .flash_regions[1].flags = kRegionIsDefault,
+ .flash_regions[1].flash_algo = (program_target_t *)&M261_LD_4_flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20018000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nxp/lpc1114/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nxp/lpc1114/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,67 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the lpc1114
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t LPC1114_FLM[] = {
+ /*0x000*/ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ /*0x020*/ 0x47700b00, 0x21004841, 0x22016301, 0x63416342, 0x6b416342, 0xd0fc07c9, 0x493c6382, 0x39402002,
+ /*0x040*/ 0x20006008, 0x20004770, 0xb5f84770, 0x20324c38, 0x2500444c, 0x46222607, 0x4621c261, 0x4f353114,
+ /*0x060*/ 0x91004620, 0x696047b8, 0xd10a2800, 0x46212034, 0x4831c161, 0x462060e0, 0x47b89900, 0x28006960,
+ /*0x080*/ 0x2001d000, 0xb5f8bdf8, 0x0b044d29, 0x2032444d, 0x4629606c, 0x311460ac, 0x4e266028, 0x4628460f,
+ /*0x0A0*/ 0x696847b0, 0xd10b2800, 0x2034606c, 0x602860ac, 0x60e84821, 0x46284639, 0x696847b0, 0xd0002800,
+ /*0x0C0*/ 0xbdf82001, 0x4614b5f8, 0xd10e0006, 0x68206861, 0x184068e2, 0x188968a1, 0x69211840, 0x69611840,
+ /*0x0E0*/ 0x69a11840, 0x42401840, 0x4d1161e0, 0x444d0b30, 0x60682132, 0x60a86029, 0x31144629, 0x46284f0d,
+ /*0x100*/ 0x47b89100, 0x28006968, 0x606ed10e, 0x60ac2033, 0x20ff6028, 0x60e83001, 0x61284807, 0x99004628,
+ /*0x120*/ 0x696847b8, 0xd0002800, 0xbdf82001, 0x40048040, 0x00000004, 0x1fff1ff1, 0x00002ee0, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 4096},
+ };
+
+static const program_target_t flash = {
+ 0x10000025, // Init
+ 0x10000047, // UnInit
+ 0x1000004B, // EraseChip
+ 0x10000087, // EraseSector
+ 0x100000C5, // ProgramPage
+ 0x0, // Verify
+
+ // RSB : base adreess is address of Execution Region PrgData in map file
+ // to access global/static data
+ // RSP : Initial stack pointer
+ {0x10000001, 0x10000020 + 0x00000120, 0x10001000 - 32}, // {breakpoint, RSB, RSP}
+
+ 0x10000200, // program_buffer
+ 0x10000000, // algo_start
+ 0x00000150, // algo_size
+ LPC1114_FLM,// algo_blob
+
+ 256 // program_buffer_size
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nxp/lpc1114/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nxp/lpc1114/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the lpc1114
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(32),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x10000000,
+ .ram_regions[0].end = 0x10001000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nxp/lpc1768/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nxp/lpc1768/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,68 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the lpc1768
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t LPC1768_FLM[] = {
+ 0xe00abe00, 0x062d780d, 0x24084068, 0xd3000040, 0x1e644058, 0x1c49d1fa, 0x2a001e52, 0x4770d1f2,
+
+ /*0x20*/ 0x28100b00, 0x210ed302, 0xd0eb01, 0x494f4770, 0x607af44f, 0x60084449, 0x2100484d, 0x21aa7001,
+ /*0x40*/ 0x21557301, 0x21017301, 0x1c40f800, 0x47702000, 0x47702000, 0x41f0e92d, 0x20324c46, 0x2500444c,
+ /*0x60*/ 0xe884261dL, 0xf1040061L, 0x4f430114, 0x46204688, 0x696047b8, 0x2034b960, 0x61e884, 0x4641483b,
+ /*0x80*/ 0x68004448, 0x462060e0, 0x696047b8, 0xd0002800L, 0xe8bd2001L, 0xe92d81f0L, 0xf7ff41f0L, 0x4d35ffc1,
+ /*0xa0*/ 0x444d4604, 0xe9c52032L, 0xf1050400L, 0x4e320114, 0x4628460f, 0x47b060ac, 0xb9686968L, 0xe9c52034L,
+ /*0xc0*/ 0x482a0400, 0x444860ac, 0x68004639, 0x462860e8, 0x696847b0, 0xd0dc2800L, 0xe7da2001L, 0x41f0e92d,
+ /*0xe0*/ 0x64614, 0x4825d11d, 0x12fcf8d4, 0xd03a4281L, 0x42814823, 0x4823d037, 0xd0344281L, 0x4030ea4f,
+ /*0x100*/ 0xd0304281L, 0x100e9d4, 0xe9d44408L, 0x44111202, 0x69214408, 0x69614408, 0x69a14408, 0x42404408,
+ /*0x120*/ 0x463061e0, 0xff7cf7ffL, 0x21324d12, 0x4f12444d, 0x1000e9c5, 0x114f105, 0x468860a8, 0x47b84628,
+ /*0x140*/ 0xb9806968L, 0xe9c52033L, 0xf44f0600L, 0xe9c57000L, 0x48064002, 0x44484641, 0x61286800, 0x47b84628,
+ /*0x160*/ 0x28006968, 0x2001d095, 0xe793, 0x4, 0x400fc080, 0x8, 0x1fff1ff1, 0x4e697370,
+ /*0x180*/ 0x12345678, 0x87654321L, 0x0, 0x0
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 1024},
+ };
+
+static const program_target_t flash = {
+ 0x1000002f, // init
+ 0x10000051, // uninit
+ 0x10000055, // erase_chip
+ 0x10000097, // erase_sector
+ 0x100000dd, // program_page
+ 0x0, // Verify
+
+ {0x10000001, 0x10000214, 0x10001000}, // {breakpoint, RSB, RSP}
+
+ 0x1000023c, // program_buffer
+ 0x10000000, // algo_start
+ 0x00000190, // algo_size
+ LPC1768_FLM, // image
+
+ 512 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nxp/lpc1768/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nxp/lpc1768/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the lpc1768
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(512),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x10000000,
+ .ram_regions[0].end = 0x10008000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nxp/lpc4088/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nxp/lpc4088/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,90 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the lpc4088
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+
+static const uint32_t lpc4088_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x28100b00, 0x210ebf24, 0x00d0eb01, 0xe92d4770, 0xf8df4df0, 0x46068320, 0x460c44c8, 0x0000f8d8,
+ 0x1c402500, 0x0f01f010, 0x0000f8c8, 0x461749c2, 0x2080f44f, 0x63c8bf14, 0x05306388, 0xa2fcf8df,
+ 0xf04f0d00, 0x44ca0b00, 0xf8cad111, 0xf44fb010, 0xf8ca5080, 0xe9ca6000, 0xf8ca0b01, 0xf8d8b00c,
+ 0x4651000c, 0xf1a16882, 0x47900080, 0x2018b9c0, 0xb008f8ca, 0xb003e9ca, 0xf5b4b1cc, 0xbf8c7f80,
+ 0x7b80f44f, 0x197046a3, 0x0b00e9ca, 0x000cf8d8, 0x19794aaa, 0x6843444a, 0x0080f1a2, 0xb1104798,
+ 0xe8bd2001, 0x445d8df0, 0x040bebb4, 0x2000d1e5, 0x8df0e8bd, 0x41f0e92d, 0x8278f8df, 0x60e0f642,
+ 0x4d9f44c8, 0x0008f8c8, 0xf8052000, 0x20aa0f80, 0x20557328, 0x20017328, 0x0c40f805, 0x21122200,
+ 0xf91af000, 0x210d2200, 0xf0004610, 0x2200f915, 0x2001210d, 0xf910f000, 0x21132200, 0xf0002002,
+ 0x4c8df90b, 0xf4406820, 0x60205000, 0xf4406a20, 0x62202084, 0xf4406c20, 0x64202000, 0x2780f44f,
+ 0x117e63e7, 0x6c6861a6, 0x3080f440, 0x20026468, 0x0134f8c5, 0x21072205, 0xf8eef000, 0x21162205,
+ 0xf0002000, 0x2205f8e9, 0x2000210f, 0xf8e4f000, 0x21102205, 0xf0002000, 0x2205f8df, 0x20002111,
+ 0xf8daf000, 0x21122205, 0xf0002000, 0x4875f8d5, 0x727af44f, 0x69406800, 0x000cf8c8, 0x1008f8d8,
+ 0xf1f2fbb1, 0x2134f8d5, 0xc000f8d0, 0x021ff002, 0xf3f2fbb1, 0x486d496c, 0x2103fba1, 0x22c00889,
+ 0x47e04448, 0xbf042800, 0xe8bd61e6, 0x63a781f0, 0x200161e6, 0x81f0e8bd, 0x47702000, 0x41f0e92d,
+ 0x20324c63, 0x2700444c, 0x60a5251d, 0x0700e9c4, 0xf1044e60, 0x46200114, 0x696047b0, 0x2034b980,
+ 0xe9c460a5, 0x48530700, 0x0114f104, 0x68804448, 0x462060e0, 0x696047b0, 0xbf082800, 0x81f0e8bd,
+ 0xe8bd2001, 0xf1b081f0, 0xbf325f20, 0x2f00f5b0, 0x47702000, 0x0b04b570, 0xbf242c10, 0xeb00200e,
+ 0x203204d4, 0x4e4b4d4a, 0xf105444d, 0xe9c50114, 0x46280400, 0x47b060ac, 0xb9786968, 0xe9c52034,
+ 0x483c0400, 0x444860ac, 0x0114f105, 0x60e86880, 0x47b04628, 0x28006968, 0xbd70bf08, 0xbd702001,
+ 0x41f0e92d, 0x46054f33, 0x4614444f, 0x4a326878, 0xf0101c40, 0x60780f01, 0x5000f44f, 0x61d0bf14,
+ 0xf1b56190, 0xd3055f20, 0xf1a54622, 0xe8bd5020, 0xe6bc41f0, 0x2f00f5b5, 0x4622d305, 0x2000f5a5,
+ 0x41f0e8bd, 0xb975e6b3, 0x0100e9d4, 0xe9d44408, 0x44111202, 0x69214408, 0x69614408, 0x69a14408,
+ 0x42404408, 0x0b2861e0, 0xbf242810, 0xeb01210e, 0x213200d0, 0xf8df4e1e, 0x444e807c, 0x1000e9c6,
+ 0xf10660b0, 0x46300114, 0x697047c0, 0x2033b988, 0x0500e9c6, 0x7000f44f, 0x4002e9c6, 0x613068b8,
+ 0x0114f106, 0x47c04630, 0x28006970, 0xe8bdbf08, 0x200181f0, 0x81f0e8bd, 0x1040eb01, 0xeb01490e,
+ 0x68010080, 0x0107f021, 0x68016001, 0x60014311, 0x00004770, 0x00000004, 0x20098000, 0x000000b4,
+ 0x400fc000, 0x1fff1ff8, 0xcccccccd, 0x00000034, 0x00000014, 0x1fff1ff1, 0x4002c000, 0x00000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, KB(4)},
+ };
+
+static const program_target_t flash = {
+ 0x200000D5, // Init
+ 0x200001D9, // UnInit
+ 0x200001DD, // EraseChip
+ 0x20000227, // EraseSector
+ 0x20000281, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000000 + 0x00000001,
+ 0x20000000 + 0x00000020 + 0x00000400,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(lpc4088_flash_prog_blob), // prog_blob size
+ lpc4088_flash_prog_blob, // address of prog_blob
+ 0x00000200 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nxp/lpc4088/target_lpc4088dm.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nxp/lpc4088/target_lpc4088dm.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the lpc4088
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// The LPC4088 Display Module has 512K internal flash and 16M external QSPI flash
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = MB(16) + KB(512),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x10000000,
+ .ram_regions[0].end = 0x10010000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nxp/lpc4088/target_lpc4088qsb.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nxp/lpc4088/target_lpc4088qsb.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the lpc4088
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// The LPC4088 QuickStart Board has 512K internal flash and 8M external QSPI flash
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = MB(8) + KB(512),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x10000000,
+ .ram_regions[0].end = 0x10010000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nxp/lpc54018/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nxp/lpc54018/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,102 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t lpc54018_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x4d70b570, 0x444d4c70, 0x0110f105, 0xf0004620, 0x69e1fa08, 0x0f20f011, 0x7d21d0fb, 0x0f01f011,
+ 0xbd70d1f2, 0x4d67b570, 0x444d4c67, 0x0120f105, 0xf0004620, 0xf105f9f6, 0x46200128, 0xf9f1f000,
+ 0x75212102, 0x4070e8bd, 0x4860e7da, 0xf0106800, 0xd10b0f10, 0x6801485e, 0x4f80f011, 0x6800d006,
+ 0x4f80f410, 0x485bbf0c, 0x4770485b, 0x47702000, 0xb083b530, 0xf44f2000, 0x90005100, 0x90029001,
+ 0xf240044a, 0xf8c23026, 0x49541220, 0x66486608, 0x66c86708, 0x668865c8, 0xf8c22003, 0x484b02a0,
+ 0xf0106800, 0xd10b0f10, 0x68014849, 0x4f80f011, 0x6800d006, 0x4f80f410, 0x4846bf0c, 0xe0004846,
+ 0x49472000, 0xf0f1fbb0, 0xf8c21e40, 0x46680390, 0xf90bf000, 0x46694c3c, 0xf0004620, 0x4d39f918,
+ 0x444d4620, 0x0120f105, 0xf99bf000, 0x0128f105, 0xf0004620, 0x2102f996, 0xf7ff7521, 0xb003ff81,
+ 0xbd302000, 0x47702000, 0x4c2fb570, 0x61e02010, 0xf01169e1, 0xd1fb0f10, 0x46204d2a, 0xf105444d,
+ 0xf0000120, 0x2100f97e, 0xf10560a1, 0x46200130, 0xf977f000, 0xff64f7ff, 0xbd702000, 0x4c22b570,
+ 0x20104606, 0x69e161e0, 0x0f10f011, 0x4d1dd1fb, 0x444d4620, 0x0120f105, 0xf963f000, 0x5180f1a6,
+ 0xf10560a1, 0x46200118, 0xf95bf000, 0xff48f7ff, 0xbd702000, 0x41f0e92d, 0x46064d13, 0x46142010,
+ 0x69e861e8, 0x0f10f010, 0x4f0ed1fb, 0x444f4628, 0x0120f107, 0xf945f000, 0x5080f1a6, 0xf10760a8,
+ 0x46280108, 0xf93df000, 0xf8542100, 0x616a2b04, 0xf5b11d09, 0xd3f87f80, 0xff22f7ff, 0xe8bd2000,
+ 0x000081f0, 0x00000004, 0x40080000, 0x40000610, 0x40000500, 0x02dc6c00, 0x05b8d800, 0x40001000,
+ 0x016e3600, 0xb2820c01, 0xb5102001, 0x2a204090, 0xf3afd301, 0x29038000, 0x4932bf27, 0x00896048,
+ 0x4180f101, 0xf8c1bf38, 0xd3030120, 0x4202680a, 0xbd10d0fc, 0x2100f8d1, 0xd0fb4202, 0x0c01bd10,
+ 0x2001b282, 0x4090b510, 0xd3012a20, 0x8000f3af, 0xbf272903, 0x60884923, 0xf1010089, 0xbf384180,
+ 0x0140f8c1, 0x680ad304, 0x0202ea30, 0xbd10d0fb, 0x2100f8d1, 0x0202ea30, 0xbd10d0fa, 0x0c05b570,
+ 0x2101b282, 0x460e4091, 0xd2172a20, 0x00920c02, 0x4c80f102, 0x2d034a13, 0x6051bf2e, 0xf8cc4663,
+ 0xd3031120, 0x420c6814, 0xe003d0fc, 0x4100f8d3, 0xd0fb420c, 0x4631b280, 0xd3012820, 0x8000f3af,
+ 0xbf2c2d03, 0xf8cc6091, 0xd3041140, 0xea316810, 0xd0fb0000, 0xf8dcbd70, 0xea310100, 0xd0fa0000,
+ 0x0000bd70, 0x40040000, 0xb5104a84, 0x20004601, 0xf852447a, 0x428b3020, 0x1c40d002, 0xe002d0f9,
+ 0xbf082800, 0xf3afbd10, 0xb5108000, 0xf0004604, 0xf64ff907, 0x802070ff, 0x70a0200f, 0x70e02000,
+ 0x21017120, 0x71a07161, 0x722071e1, 0xb570bd10, 0x4605000c, 0x4601d02b, 0x22004871, 0xf8504478,
+ 0x428b3022, 0x1c52d002, 0xe020d0f9, 0x496db9fa, 0x23014479, 0x0a0a8809, 0x4479496b, 0xfa037809,
+ 0x079ef101, 0xbf3d2a03, 0xf1020092, 0xf8c24280, 0x64f31220, 0x4a65bf24, 0x46296151, 0xf8502200,
+ 0x428b3022, 0x1c52d002, 0xe000d0f9, 0xf3afb10a, 0x485f8000, 0x68004478, 0xff70f7ff, 0x61e82010,
+ 0xf01069e8, 0xd1fb0f10, 0x882078a1, 0x2270f44f, 0x4101ea02, 0x78e14308, 0x1200f44f, 0x5141ea02,
+ 0xf44f79a2, 0xea030300, 0x431152c2, 0x79214308, 0xea02011a, 0x430861c1, 0x00527a21, 0x7101ea02,
+ 0x79e14308, 0xea020052, 0x43087141, 0xea067961, 0x43087181, 0xbd706028, 0xb5104a46, 0x447a2100,
+ 0x3021f852, 0xd0024283, 0xd0f91c49, 0xb109e000, 0x8000f3af, 0x44784840, 0x88004a40, 0x20010a01,
+ 0x7812447a, 0x29034090, 0x0089d205, 0x4180f101, 0x0240f8c1, 0x4935bd10, 0x20006188, 0x64c80309,
+ 0x69c2bd10, 0x0f01f012, 0x2210bf1c, 0xd00361c2, 0xf01269c2, 0xd1fb0f10, 0xf01269c2, 0xd1fb0f02,
+ 0x788b880a, 0x4c80f44f, 0x020df3c2, 0x3383ea0c, 0x78cb431a, 0x4c00f44f, 0x33c3ea0c, 0x790b431a,
+ 0x2ce0f44f, 0x4303ea0c, 0x794b431a, 0x1cc0f44f, 0x43c3ea0c, 0x798b431a, 0x0c60f44f, 0x5343ea0c,
+ 0x431a79c9, 0x6101ea42, 0x47706041, 0xf01269c2, 0xd1fb0f02, 0xf44f790a, 0xea0323e0, 0x794b4202,
+ 0x1cc0f44f, 0x43c3ea0c, 0x798b431a, 0x0c60f44f, 0x5343ea0c, 0x431a79c9, 0x6101ea42, 0x69c16181,
+ 0x0f01f011, 0x4770d0fb, 0x0a097501, 0x47707541, 0x7d407d01, 0x2000ea41, 0x00004770, 0x0000023c,
+ 0x000001f0, 0x000001d8, 0x000001ce, 0x40040000, 0x0000019c, 0x0000012e, 0x00000112, 0x00000108,
+ 0x60012100, 0x81016041, 0x00004770, 0x0000000a, 0x40080000, 0x0000000a, 0x00000000, 0x00000100,
+ 0x6b040101, 0x01000100, 0x32040100, 0x00000001, 0x05010000, 0x01000000, 0x20040000, 0x01000000,
+ 0x06010000, 0x01000001, 0x31010000, 0x01000000, 0xc7010000
+};
+
+// Start address of flash
+static const uint32_t flash_start = 0x10000000;
+// Size of flash
+static const uint32_t flash_size = 0x01000000;
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x10000000, 0x00001000},
+};
+
+static const program_target_t flash = {
+ 0x20000091, // Init
+ 0x20000125, // UnInit
+ 0x20000129, // EraseChip
+ 0x2000015d, // EraseSector
+ 0x20000195, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x20000538,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(lpc54018_flash_prog_blob), // prog_blob size
+ lpc54018_flash_prog_blob, // address of prog_blob
+ 0x00000100 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nxp/lpc54018/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nxp/lpc54018/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the lpc54018
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2018-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+#include "daplink_debug.h"
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x10000000,
+ .flash_regions[0].end = 0x11000000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x00000000,
+ .ram_regions[0].end = 0x00030000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nxp/lpc54114/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nxp/lpc54114/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,69 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t lpc54114_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x21002210, 0xf8c00690, 0x4a2c2630, 0xf0236813, 0x60134380, 0x1280f8c0, 0x1284f8c0, 0x68134a28,
+ 0x4370f423, 0xf8c06013, 0x21021380, 0x20006001, 0x20004770, 0xb5104770, 0x20002107, 0xf844f000,
+ 0xbf182800, 0x4a1fbd10, 0xe8bd2107, 0x20004010, 0xb864f000, 0x0bc4b510, 0x46084621, 0xf834f000,
+ 0xbf182800, 0x4a17bd10, 0xe8bd4621, 0x46084010, 0xb854f000, 0x4614b570, 0xd10e0005, 0x0100e9d4,
+ 0xe9d44408, 0x44111202, 0x69214408, 0x69614408, 0x69a14408, 0x42404408, 0x0be861e0, 0xf0004601,
+ 0x2800f813, 0xbd70bf18, 0x46214b06, 0xe8bd4628, 0xf44f4070, 0xf0007280, 0x0000b818, 0x40000500,
+ 0x40000400, 0x00b71b00, 0xb08bb500, 0x92002232, 0x0101e9cd, 0x46684a39, 0x4790a906, 0x28009806,
+ 0xf600bf18, 0xb00b10c4, 0xb500bd00, 0xf04fb08b, 0x92030c33, 0xc000f8cd, 0x0101e9cd, 0x707af44f,
+ 0xf0f0fbb3, 0x4a2d9004, 0xa9064668, 0x98064790, 0xbf182800, 0x10c4f600, 0xbd00b00b, 0xb08bb500,
+ 0x93002334, 0x0101e9cd, 0x707af44f, 0xf0f0fbb2, 0x4a229003, 0xa9064668, 0x98064790, 0xbf182800,
+ 0x10c4f600, 0xbd00b00b, 0xb08bb500, 0x9300233b, 0x0101e9cd, 0x707af44f, 0xf0f0fbb2, 0x4a179003,
+ 0xa9064668, 0x98064790, 0xbf182800, 0x10c4f600, 0xbd00b00b, 0xb08bb500, 0x92002235, 0x0101e9cd,
+ 0x46684a0e, 0x4790a906, 0x28009806, 0xf600bf18, 0xb00b10c4, 0xb500bd00, 0x2338b08b, 0x93009203,
+ 0x0101e9cd, 0x46684a05, 0x4790a906, 0x28009806, 0xf600bf18, 0xb00b10c4, 0x0000bd00, 0x03000205,
+ 0x00000000
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 32768},
+};
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000053, // UnInit
+ 0x20000057, // EraseChip
+ 0x20000075, // EraseSector
+ 0x20000095, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x200001e0,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(lpc54114_flash_prog_blob), // prog_blob size
+ lpc54114_flash_prog_blob, // address of prog_blob
+ 0x00000100 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nxp/lpc54114/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nxp/lpc54114/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the lpc812
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(256),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20028000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nxp/lpc54608/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nxp/lpc54608/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,74 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t lpc54608_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x21002210, 0xf8c00690, 0x4a2c2630, 0xf0236813, 0x60134380, 0x1280f8c0, 0x1284f8c0, 0x68134a28,
+ 0x4370f423, 0xf8c06013, 0x21021380, 0x20006001, 0x20004770, 0xb5104770, 0x2000210f, 0xf844f000,
+ 0xbf182800, 0x4a1fbd10, 0xe8bd210f, 0x20004010, 0xb864f000, 0x0bc4b510, 0x46084621, 0xf834f000,
+ 0xbf182800, 0x4a17bd10, 0xe8bd4621, 0x46084010, 0xb854f000, 0x4614b570, 0xd10e0005, 0x0100e9d4,
+ 0xe9d44408, 0x44111202, 0x69214408, 0x69614408, 0x69a14408, 0x42404408, 0x0be861e0, 0xf0004601,
+ 0x2800f813, 0xbd70bf18, 0x46214b06, 0xe8bd4628, 0xf44f4070, 0xf0007280, 0x0000b818, 0x40000500,
+ 0x40000400, 0x00b71b00, 0xb08bb500, 0x92002232, 0x0101e9cd, 0x46684a39, 0x4790a906, 0x28009806,
+ 0xf600bf18, 0xb00b10c4, 0xb500bd00, 0xf04fb08b, 0x92030c33, 0xc000f8cd, 0x0101e9cd, 0x707af44f,
+ 0xf0f0fbb3, 0x4a2d9004, 0xa9064668, 0x98064790, 0xbf182800, 0x10c4f600, 0xbd00b00b, 0xb08bb500,
+ 0x93002334, 0x0101e9cd, 0x707af44f, 0xf0f0fbb2, 0x4a229003, 0xa9064668, 0x98064790, 0xbf182800,
+ 0x10c4f600, 0xbd00b00b, 0xb08bb500, 0x9300233b, 0x0101e9cd, 0x707af44f, 0xf0f0fbb2, 0x4a179003,
+ 0xa9064668, 0x98064790, 0xbf182800, 0x10c4f600, 0xbd00b00b, 0xb08bb500, 0x92002235, 0x0101e9cd,
+ 0x46684a0e, 0x4790a906, 0x28009806, 0xf600bf18, 0xb00b10c4, 0xb500bd00, 0x2338b08b, 0x93009203,
+ 0x0101e9cd, 0x46684a05, 0x4790a906, 0x28009806, 0xf600bf18, 0xb00b10c4, 0x0000bd00, 0x03000205,
+ 0x00000000
+};
+
+// Start address of flash
+static const uint32_t flash_start = 0x00000000;
+// Size of flash
+static const uint32_t flash_size = 0x00080000;
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x00000000, 0x00008000},
+};
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000053, // UnInit
+ 0x20000057, // EraseChip
+ 0x20000075, // EraseSector
+ 0x20000095, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x200001e0,
+ 0x20000400
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(lpc54608_flash_prog_blob), // prog_blob size
+ lpc54608_flash_prog_blob, // address of prog_blob
+ 0x00000100 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nxp/lpc54608/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nxp/lpc54608/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the lpc54608
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(512),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20028000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nxp/lpc55S6X/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nxp/lpc55S6X/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,104 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t lpc55S69_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x20c8b580, 0x0002f2c4, 0x60012120, 0x6080f64f, 0x4100f240, 0x70fff6cf, 0x0100f2c4, 0x500a2200,
+ 0x6084f64f, 0x70fff6cf, 0x6808500a, 0x6300f04f, 0x30f8f440, 0xf64f6008, 0xf6cf5048, 0x500b70ff,
+ 0x6028f64f, 0x70fff6cf, 0xf243500b, 0xf2c40010, 0x68030001, 0x4380f443, 0xf8416003, 0xf04f2c80,
+ 0x21024080, 0xf2406001, 0xf2c0000c, 0x44480000, 0xf862f000, 0xbf182800, 0xbd802001, 0x47702000,
+ 0xf240b510, 0xf2c0040c, 0xf2460400, 0xeb09636c, 0xf6c60004, 0x21003365, 0x2218f44f, 0xf86cf000,
+ 0xbf182800, 0xeb09bd10, 0x21000004, 0x2218f44f, 0x4010e8bd, 0xb8b0f000, 0xf240b5b0, 0xf2c0050c,
+ 0xeb090500, 0x690a0105, 0xf2464604, 0xf6c6636c, 0x46083365, 0xf0004621, 0x2800f84f, 0xbdb0bf18,
+ 0x0005eb09, 0x46216902, 0x40b0e8bd, 0xb894f000, 0xb085b5f0, 0x070cf240, 0x4606460d, 0x0700f2c0,
+ 0x0007eb09, 0x462b4631, 0xf0004614, 0xb108f85d, 0xbdf0b005, 0xf10da804, 0x90000c0c, 0x0007eb09,
+ 0x462a4631, 0xf8cd4623, 0xf000c004, 0xb005f88b, 0x0000bdf0, 0xe7fdbe00, 0x1100f241, 0x3100f2c1,
+ 0x29006809, 0x680ad00a, 0x0308f240, 0x2207f3c2, 0x0300f2c0, 0x2003f849, 0x47086849, 0x309ef240,
+ 0x0000f2c0, 0x31abf240, 0x0100f2c0, 0x44794478, 0xf7ff2276, 0xbf00ffdf, 0x0c08f240, 0x0c00f2c0,
+ 0xc00cf859, 0x0f00f1bc, 0xf241d00b, 0xf2c11c00, 0xf8dc3c00, 0xf1bcc000, 0xd0070f00, 0xc008f8dc,
+ 0xf2444760, 0xf2c11c3b, 0x47603c00, 0x304ef240, 0x0000f2c0, 0x315bf240, 0x0100f2c0, 0x44794478,
+ 0xf7ff2286, 0xbf00ffb7, 0x0c08f240, 0x0c00f2c0, 0xc00cf859, 0x0f00f1bc, 0xf241d00b, 0xf2c11c00,
+ 0xf8dc3c00, 0xf1bcc000, 0xd0070f00, 0xc00cf8dc, 0xf2444760, 0xf2c11c9d, 0x47603c00, 0x20fef240,
+ 0x0000f2c0, 0x310bf240, 0x0100f2c0, 0x44794478, 0xf7ff2296, 0xbf00ff8f, 0x1300f241, 0x3300f2c1,
+ 0x2b00681b, 0x691bd001, 0xf2404718, 0xf2c020d0, 0xf2400000, 0xf2c021dd, 0x44780100, 0x229e4479,
+ 0xff78f7ff, 0x0c08f240, 0x0c00f2c0, 0xc00cf859, 0x0f00f1bc, 0xf241d00b, 0xf2c11c00, 0xf8dc3c00,
+ 0xf1bcc000, 0xd0070f00, 0xc014f8dc, 0xf2444760, 0xf2c12c7d, 0x47603c00, 0x2082f240, 0x0000f2c0,
+ 0x218ff240, 0x0100f2c0, 0x44794478, 0xf7ff22b2, 0xbf00ff51, 0x1300f241, 0x3300f2c1, 0x2b00681b,
+ 0x699bd001, 0xf2404718, 0xf2c02054, 0xf2400000, 0xf2c02161, 0x44780100, 0x22bb4479, 0xff3af7ff,
+ 0x1100f241, 0x3100f2c1, 0x29006809, 0x69c9d001, 0xf2404708, 0xf2c02028, 0xf2400000, 0xf2c02135,
+ 0x44780100, 0x22c54479, 0xff24f7ff, 0x1100f241, 0x3100f2c1, 0x29006809, 0x6a09d001, 0xf2404708,
+ 0xf2c010fc, 0xf2400000, 0xf2c02109, 0x44780100, 0x22cc4479, 0xff0ef7ff, 0x1100f241, 0x3100f2c1,
+ 0x29006809, 0xf644d004, 0xf2c11151, 0x47083100, 0x10caf240, 0x0000f2c0, 0x11d7f240, 0x0100f2c0,
+ 0x44794478, 0xf7ff22d2, 0xbf00fef5, 0x230bf644, 0x3300f2c1, 0xbf004718, 0x1c00f241, 0x3c00f2c1,
+ 0xc000f8dc, 0x0f00f1bc, 0xf8dcd002, 0x4760c040, 0x108af240, 0x0000f2c0, 0x1197f240, 0x0100f2c0,
+ 0x44794478, 0xf7ff22e0, 0xbf00fed5, 0x21fff644, 0x3100f2c1, 0xbf004708, 0x313df644, 0x3100f2c1,
+ 0xbf004708, 0x1200f241, 0x3200f2c1, 0x2a006812, 0xf644d004, 0xf2c1328b, 0x47103200, 0x103ef240,
+ 0x0000f2c0, 0x114bf240, 0x0100f2c0, 0x44794478, 0xf7ff22f5, 0xbf00feaf, 0x1300f241, 0x3300f2c1,
+ 0x2b00681b, 0x6a5bd001, 0xf2404718, 0xf2c01010, 0xf2400000, 0xf2c0111d, 0x44780100, 0x22fc4479,
+ 0xfe98f7ff, 0x62a7f644, 0x3200f2c1, 0xbf004710, 0x1c00f241, 0x3c00f2c1, 0xc000f8dc, 0x0f00f1bc,
+ 0xf8dcd002, 0x4760c02c, 0x00d2f240, 0x0000f2c0, 0x01dff240, 0x0100f2c0, 0x44794478, 0x7284f44f,
+ 0xfe78f7ff, 0x1200f241, 0x3200f2c1, 0x2a006812, 0x6b12d001, 0xf2404710, 0xf2c000a4, 0xf2400000,
+ 0xf2c001b1, 0x44780100, 0xf2404479, 0xf7ff120f, 0xbf00fe61, 0x1200f241, 0x3200f2c1, 0x2a006812,
+ 0x6b52d001, 0xf2404710, 0xf2c00074, 0xf2400000, 0xf2c00181, 0x44780100, 0xf44f4479, 0xf7ff728b,
+ 0xbf00fe49, 0x1300f241, 0x3300f2c1, 0x2b00681b, 0x6b9bd001, 0xf2404718, 0xf2c00044, 0xf2400000,
+ 0xf2c00151, 0x44780100, 0xf2404479, 0xf7ff121d, 0xbf00fe31, 0x6c15f644, 0x3c00f2c1, 0xbf004760,
+ 0x1200f241, 0x3200f2c1, 0x2a006812, 0x6a92d001, 0xf2404710, 0xf2c00008, 0xf2400000, 0xf2c00115,
+ 0x44780100, 0xf44f4479, 0xf7ff7295, 0x4c46fe13, 0x5f485341, 0x5f495041, 0x45455254, 0x2f2e2e00,
+ 0x2e2f2e2e, 0x6f732f2e, 0x65637275, 0x70786e2f, 0x63706c2f, 0x36533535, 0x73662f39, 0x61695f6c,
+ 0x00632e70, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000
+};
+
+// Start address of flash
+static const uint32_t flash_start = 0x00000000;
+// Size of flash
+static const uint32_t flash_size = 0x00098000;
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x00000000, 0x00008000},
+};
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x2000009d, // UnInit
+ 0x200000a1, // EraseChip
+ 0x200000d9, // EraseSector
+ 0x20000111, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x20000564,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(lpc55S69_flash_prog_blob), // prog_blob size
+ lpc55S69_flash_prog_blob, // address of prog_blob
+ 0x00000200 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nxp/lpc55S6X/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nxp/lpc55S6X/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,42 @@
+/**
+ * @file target.c
+ * @brief Target information for the lpc55S6X
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(608),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .flash_regions[1].start = 0x10000000,
+ .flash_regions[1].end = 0x10000000 + KB(608),
+ .flash_regions[1].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20044000,
+ .ram_regions[1].start = 0x30000000,
+ .ram_regions[1].end = 0x30000000 + 0x00044000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nxp/lpc55S6X/target_reset.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nxp/lpc55S6X/target_reset.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,113 @@
+/**
+ * @file target_reset.c
+ * @brief Target reset for the lpc812
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "target_family.h"
+#include "swd_host.h"
+#include "cmsis_os2.h"
+
+#define DBG_Addr (0xE000EDF0)
+#define DWT_COMP0 (0xE0001020)
+#define DWT_FUNCTION0 (0xE0001028)
+#define DWT_FUNCTION_MATCH (0x4 << 0)
+#define DWT_FUNCTION_ACTION (0x1 << 4)
+#define DWT_FUNCTION_DATAVSIZE (0x2 << 10)
+
+/* Debug mailbox AP registers */
+#define DEBUGMB_CSW 0x02000000
+#define DEBUGMB_REQ 0x02000004
+#define DEBUGMB_RET 0x02000008
+#define DEBUGMB_ID 0x020000FC
+
+static uint8_t lpc55s6x_target_set_state(target_state_t state)
+{
+ uint32_t val;
+ int8_t ap_retries = 2;
+
+ if (state == RESET_PROGRAM) {
+ if (!swd_init_debug()) {
+ return 0;
+ }
+
+ // Enable debug
+ while(swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN) == 0) {
+ if( --ap_retries <=0 )
+ return 0;
+ // Target is in invalid state?
+ swd_set_target_reset(1);
+ osDelay(2);
+ swd_set_target_reset(0);
+ osDelay(2);
+ }
+
+ // Set Trace Enable bit
+ if (!swd_read_word(DBG_EMCR, &val)) {
+ return 0;
+ }
+
+ if (!swd_write_word(DBG_EMCR, val | TRCENA)) {
+ return 0;
+ }
+
+ // Clear the comparator function register
+ if (!swd_write_word(DWT_FUNCTION0, 0x0)) {
+ return 0;
+ }
+
+ // Set the address
+ if (!swd_write_word(DWT_COMP0, 0x50000040)) {
+ return 0;
+ }
+
+ // Update the comparator function register
+ if (!swd_write_word(DWT_FUNCTION0, (DWT_FUNCTION_MATCH | DWT_FUNCTION_ACTION | DWT_FUNCTION_DATAVSIZE))) {
+ return 0;
+ }
+
+ // Reset using the debug mailbox
+ if (!swd_write_ap(DEBUGMB_CSW, 0x20)) {
+ return 0;
+ }
+
+ osDelay(5);
+
+ do {
+ if (!swd_read_word(DBG_HCSR, &val)) {
+ return 0;
+ }
+ } while ((val & S_HALT) == 0);
+
+ // Disable halt on reset
+ if (!swd_write_word(DBG_EMCR, 0)) {
+ return 0;
+ }
+
+ return 1;
+
+ } else {
+ return swd_set_target_state_sw(state);
+ }
+}
+
+const target_family_descriptor_t g_target_family_lpc55S6X = {
+ .family_id = VENDOR_TO_FAMILY(kNXP_VendorID, 0), //ID not maching the predefined family ids
+ .target_set_state = lpc55s6x_target_set_state,
+};
+
+const target_family_descriptor_t *g_target_family = &g_target_family_lpc55S6X;
diff -r 000000000000 -r 01f31e923fe2 source/family/nxp/lpc812/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nxp/lpc812/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,67 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the lpc812
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t LPC812_FLM[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+
+ // flash algo begins here
+ /* 0x20 */ 0x47700a80, 0x48454946, 0x60084449, 0x22004845, 0x21016302, 0x63426341, 0x63816341, 0x20024941,
+ /* 0x40 */ 0x70083940, 0x47704610, 0x47702000, 0x4c3eb5f8, 0x444c2032, 0x260f2500, 0xc2614622L, 0x31144621,
+ /* 0x60 */ 0x46204f3a, 0x47b89100, 0x28006960, 0x2034d10c, 0xc1614621L, 0x44484832, 0x60e06800, 0x99004620L,
+ /* 0x80 */ 0x696047b8, 0xd0002800L, 0xbdf82001L, 0x4d2eb5f8, 0x444d0a84, 0x60282032, 0x46292000, 0x311460ac,
+ /* 0xa0 */ 0x4e2a6068, 0x4628460f, 0x696847b0, 0xd10d2800L, 0x2034606c, 0x602860ac, 0x46394821, 0x68004448,
+ /* 0xc0 */ 0x462860e8, 0x696847b0, 0xd0002800L, 0xbdf82001L, 0x6b5f8, 0xd10e4614L, 0x68206861, 0x184068e2,
+ /* 0xe0 */ 0x188968a1, 0x69211840, 0x69611840, 0x69a11840, 0x42401840, 0x4d1461e0, 0x444d2132, 0x21006029,
+ /* 0x100 */ 0xab06069, 0x462960a8, 0x4f103114, 0x91004628L, 0x696847b8, 0xd10f2800L, 0x2033606e, 0x602860ac,
+ /* 0x120 */ 0x60e82040, 0x44484806, 0x61286800, 0x99004628L, 0x696847b8, 0xd0002800L, 0xbdf82001L, 0x2ee0,
+ /* 0x140 */ 0x4, 0x40048040, 0x8, 0x1fff1ff1
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x00000000, 0x1000},
+};
+
+static const program_target_t flash = {
+ 0x10000025, // init
+ 0x10000049, // uninit
+ 0x1000004d, // erase_chip
+ 0x1000008d, // erase_sector
+ 0x100000d1, // program_page
+ 0x0, // Verify
+
+ {0x10000001, 0x10000300, 0x10001000}, // {breakpoint, RSB, RSP}
+
+ 0x10000400, // program_buffer
+ 0x10000000, // algo_start
+ 0x00000150, // algo_size
+ LPC812_FLM, // image
+
+ 64 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nxp/lpc812/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nxp/lpc812/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the lpc812
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(64),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x10000000,
+ .ram_regions[0].end = 0x10001000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nxp/lpc824/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nxp/lpc824/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,100 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the lpc824
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t LPC824_FLM[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+
+ /*0x020*/ 0x47700a80, 0x21004841, 0x22016301, 0x63416342, 0x6b416342, 0xd0fc07c9L, 0x493c6382, 0x39402002,
+ /*0x040*/ 0x20006008, 0x20004770, 0xb5f84770L, 0x20324c38, 0x2500444c, 0x4622261f, 0x4621c261, 0x4f353114,
+ /*0x060*/ 0x91004620L, 0x696047b8, 0xd10a2800L, 0x46212034, 0x4831c161, 0x462060e0, 0x47b89900, 0x28006960,
+ /*0x080*/ 0x2001d000, 0xb5f8bdf8L, 0xa844d29, 0x2032444d, 0x4629606c, 0x311460ac, 0x4e266028, 0x4628460f,
+ /*0x0A0*/ 0x696847b0, 0xd10b2800L, 0x2034606c, 0x602860ac, 0x60e84821, 0x46284639, 0x696847b0, 0xd0002800L,
+ /*0x0C0*/ 0xbdf82001L, 0x4614b5f8, 0xd10e0006L, 0x68206861, 0x184068e2, 0x188968a1, 0x69211840, 0x69611840,
+ /*0x0E0*/ 0x69a11840, 0x42401840, 0x4d1161e0, 0x444d0ab0, 0x60682132, 0x60a86029, 0x31144629, 0x46284f0d,
+ /*0x100*/ 0x47b89100, 0x28006968, 0x606ed10e, 0x60ac2033, 0x20016028, 0x60e80240, 0x61284807, 0x99004628L,
+ /*0x120*/ 0x696847b8, 0xd0002800L, 0xbdf82001L, 0x40048040, 0x4, 0x1fff1ff1, 0x2ee0, 0x0,
+ /*0x140*/
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 1024},
+};
+
+static const program_target_t flash = {
+ 0x10000025, // Init
+ 0x10000047, // UnInit
+ 0x1000004B, // EraseChip
+ 0x10000087, // EraseSector
+ 0x100000C5, // ProgramPage
+ 0x0, // Verify
+
+ // static_base : base address is address of Execution Region PrgData in map file
+ // to access global/static data
+ // stack_pointer : Initial stack pointer
+ {0x10000001, 0x10000200, 0x10001000}, // {breakpoint, static_base, stack_pointer}
+
+ 0x10000400, // program_buffer
+ 0x10000000, // algo_start
+ 0x00000140, // algo_size
+
+ /*
+ 0x10000000 ---------------------- algo_start
+ | FLASH ALGORITHM |
+ 0x10000001 | | breakpoint
+ 0x10000025 | | Init
+ 0x10000047 | | UnInit
+ 0x1000004b | | EraseChip
+ 0x10000087 | | EraseSector
+ 0x100000c5 | | ProgramPage
+ | |
+ ---------------------- algo_start + algo_size
+ | unused |
+ 0x10000200 ---------------------- static_base
+ | GLOBAL/STATIC DATA |
+ | |
+ 0x10000400 ---------------------- program_buffer
+ | DATA TO BE WRITTEN |
+ | |
+ ---------------------- program_buffer + ram_to_flash_bytes_to_be_written
+ | unused |
+ ----------------------
+ | SPACE FOR STACK |
+ 0x10001000 ---------------------- stack_pointer
+ | unused |
+ ----------------------
+ | 32 BYTES FOR IAP |
+ 0x10?????? ---------------------- CHIP MEMORY LIMIT
+ */
+
+ LPC824_FLM, // image
+
+ 512 // ram_to_flash_bytes_to_be_written
+};
+
diff -r 000000000000 -r 01f31e923fe2 source/family/nxp/lpc824/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nxp/lpc824/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the lpc824
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = KB(32),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x10000000,
+ .ram_regions[0].end = 0x10002000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/nxp/target_reset_lpc4088.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/nxp/target_reset_lpc4088.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,78 @@
+/**
+ * @file target_reset.c
+ * @brief Target reset for the lpc4088
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "swd_host.h"
+#include "gpio.h"
+#include "target_family.h"
+
+#define PIN_ISPCTRL1 (1<<12)
+#define PIN_ISPCTRL2 (1<<15)
+
+static void gpio_set_isp_pin(uint8_t state) {
+ if (state) {
+ // High => Both pins are inputs
+ LPC_GPIO->DIR[0] &= ~(PIN_ISPCTRL1);
+ LPC_GPIO->DIR[1] &= ~(PIN_ISPCTRL2);
+ } else {
+ // Low => Both pins are outputs with 0
+ LPC_GPIO->CLR[0] = (PIN_ISPCTRL1);
+ LPC_GPIO->CLR[1] = (PIN_ISPCTRL2);
+ LPC_GPIO->DIR[0] |= (PIN_ISPCTRL1);
+ LPC_GPIO->DIR[1] |= (PIN_ISPCTRL2);
+ }
+}
+
+static void prerun_target_config(void)
+{
+ // Configure ISPCTRL as output and high
+ // We use two ISP pins to cover different hardware versions
+ LPC_IOCON->TMS_PIO0_12 |= 0x01;
+ LPC_IOCON->PIO1_15 &= ~0x07;
+ gpio_set_isp_pin(1);
+}
+
+
+static uint8_t lpc4088_target_set_state(target_state_t state)
+{
+ //return swd_set_target_state_hw(state);
+ uint8_t res;
+ if (state == RESET_PROGRAM)
+ {
+ gpio_set_isp_pin(0);
+ res = swd_set_target_state_hw(state);
+ gpio_set_isp_pin(1);
+ }
+ else
+ {
+ gpio_set_isp_pin(1);
+ res = swd_set_target_state_hw(state);
+ }
+ return res;
+}
+
+const target_family_descriptor_t g_nxp_lpc4088 = {
+ .family_id = VENDOR_TO_FAMILY(kNXP_VendorID, 0), //ID not maching the predefined family ids
+ .prerun_target_config = prerun_target_config,
+ .target_set_state = lpc4088_target_set_state,
+};
+
+const target_family_descriptor_t *g_target_family = &g_nxp_lpc4088;
+
diff -r 000000000000 -r 01f31e923fe2 source/family/onsemi/ncs36510/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/onsemi/ncs36510/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,83 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t ncs36510_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x4770ba40, 0x4770bac0, 0x4770ba40, 0x4770bac0, 0x49876842, 0x68016111, 0xf4116840, 0x49851f80,
+ 0x6181bf14, 0x47706141, 0x68406801, 0x1f80f411, 0x6801d004, 0x0f02f011, 0x4770d1fb, 0xf0116801,
+ 0xd1fb0f01, 0x68014770, 0xf4116840, 0x68411f80, 0xf041bf14, 0xf0410101, 0x60410102, 0x68014770,
+ 0xf4116840, 0x68411f80, 0xf021bf14, 0xf0210101, 0x60410102, 0x68434770, 0x611a4a6d, 0x68436802,
+ 0x1f80f412, 0xbf144a6b, 0x615a619a, 0x60d16842, 0x21016842, 0xe7c76091, 0xf4116801, 0x68411f80,
+ 0xf44fbf14, 0xf44f1281, 0x60ca5200, 0x49606842, 0x68016111, 0xf4116842, 0x495e1f80, 0x6191bf14,
+ 0x21026151, 0x60916842, 0x4770e7ae, 0x1e5b6808, 0xf810d305, 0xf802cb01, 0x1e5bcb01, 0x6008d2f9,
+ 0x47702001, 0x4604b510, 0x46116808, 0x5f00f5b0, 0x020af3c0, 0xb132d20b, 0x020af3c0, 0x6200f5c2,
+ 0xd205429a, 0xf5b3e00a, 0xd8076f00, 0xb13ae00b, 0x020af3c0, 0x6200f5c2, 0xd204429a, 0xbd102000,
+ 0x6f00f5b3, 0x6862d8fa, 0xc004f8d2, 0x0c40f04c, 0xc004f8c2, 0xc004f8d4, 0xf8cc4a3d, 0x68222010,
+ 0xc004f8d4, 0x1f80f412, 0xbf144a3a, 0x2018f8cc, 0x2014f8cc, 0xf000461a, 0x4620f8f7, 0xff64f7ff,
+ 0xbd102001, 0x4d32b530, 0x46844c32, 0xd2562906, 0xf001e8df, 0x421f0355, 0x68015334, 0x1f80f411,
+ 0xf44fbf14, 0xf44f1181, 0x68425100, 0x684160d1, 0x6801610d, 0x1f80f411, 0xbf146841, 0x614c618c,
+ 0x68422102, 0xf7ff6091, 0x4660ff3f, 0xff3cf7ff, 0x6811e035, 0x61156842, 0xf4126802, 0x68421f80,
+ 0x6194bf14, 0x68426154, 0x684260d1, 0x60912101, 0xff2af7ff, 0xf7ff4660, 0xe020ff27, 0x0000f8dc,
+ 0x1f80f410, 0x0004f8dc, 0xbf146841, 0x0101f041, 0x0102f041, 0xe0126041, 0x0000f8dc, 0x1f80f410,
+ 0x0004f8dc, 0xbf146841, 0x0101f021, 0x0102f021, 0x46606041, 0xff08f7ff, 0xf7ffe001, 0x2001ff05,
+ 0x69c1bd30, 0x0f01f011, 0x69c0bf18, 0x00004770, 0xbb781ae9, 0xb56d9099, 0xb5104838, 0xf4216901,
+ 0x61010100, 0xf0216901, 0x61014180, 0x49354834, 0xf04f6001, 0x211f20e0, 0x1180f8c0, 0x1280f8c0,
+ 0xf04f4931, 0x60086020, 0x22004830, 0x44782103, 0xff78f7ff, 0xbd102000, 0x47702000, 0x47702000,
+ 0xb510482b, 0xf7ff4478, 0x482aff07, 0xf7ff4478, 0x2000ff03, 0xb501bd10, 0xf5b09800, 0xbf3c5f00,
+ 0xbd082001, 0x5100f5a0, 0x2fa0f5b1, 0x4822d204, 0x2102466a, 0xe0084478, 0x1081f5a0, 0x2fa0f5b0,
+ 0x481ed205, 0x2102466a, 0xf7ff4478, 0x2000ff4b, 0xb507bd08, 0xf5b09800, 0xd3165f00, 0x5c00f5a0,
+ 0x2fa0f5bc, 0x4816d204, 0x4669460b, 0xe0084478, 0x1081f5a0, 0x2fa0f5b0, 0x4812d20a, 0x4669460b,
+ 0xf7ff4478, 0x2801feef, 0xb003d002, 0xbd002001, 0x2000b003, 0x2000bd00, 0x00004770, 0x4001b000,
+ 0x4001e000, 0x2082353f, 0xe000ed04, 0x00000106, 0x000000e4, 0x000000e8, 0x000000b4, 0x000000ac,
+ 0x0000007c, 0x00000074, 0x0301ea40, 0xd003079b, 0xc908e009, 0xc0081f12, 0xd2fa2a04, 0xf811e003,
+ 0xf8003b01, 0x1e523b01, 0x4770d2f9, 0x00000000, 0x40017000, 0x00000008, 0x00100000, 0x40017000,
+ 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x00002000, 0x800},
+};
+
+static const program_target_t flash = {
+ 0x3fff4259, // Init
+ 0x3fff4299, // UnInit
+ 0x3fff42a1, // EraseChip
+ 0x3fff42b7, // EraseSector
+ 0x3fff42f3, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x3fff4001,
+ 0x3fff43a4,
+ 0x3fff4800
+ },
+
+ 0x3fff4000 + 0x00000A00, // mem buffer location
+ 0x3fff4000, // location to write prog_blob in target RAM
+ sizeof(ncs36510_flash_prog_blob), // prog_blob size
+ ncs36510_flash_prog_blob, // address of prog_blob
+ 0x00000200 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/onsemi/ncs36510/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/onsemi/ncs36510/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,32 @@
+/* CMSIS-DAP Interface Firmware
+ * Copyright (c) 2009-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x00002000,
+ .flash_regions[0].end = 0x00151FFF,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x3FFF4000,
+ .ram_regions[0].end = 0x3FFFFFFF,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/realtek/rtl8195am/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/realtek/rtl8195am/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,100 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t rtl8195am_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x01f8e92d, 0x8400f8df, 0x46172200, 0x0604f1a8, 0x4cff4dfe, 0x0c04f108, 0x5330f247, 0xf8cc2000,
+ 0x20010000, 0x0000f8c8, 0x21002005, 0x1000f8cc, 0xf4216831, 0xf4412170, 0x60317140, 0x20017020,
+ 0x0000f8cc, 0x97002000, 0x1c406829, 0x0101f001, 0x42989100, 0x2900d801, 0x7820d1f6, 0xf8cc2100,
+ 0xf0101000, 0xd0060f01, 0x42931c52, 0xe8bdd8d6, 0x200001f8, 0xe8bd4770, 0x200101f8, 0xe92d4770,
+ 0xb0814df7, 0xffbcf7ff, 0x20004ee2, 0xf1a66030, 0x20010b04, 0x0000f8cb, 0x21002005, 0xf1ab6031,
+ 0x468a0704, 0xf4216839, 0xf4412170, 0x60397140, 0x835cf8df, 0x0000f888, 0x60302001, 0x20004cd3,
+ 0x5530f247, 0xa000f8cd, 0x1c406821, 0x0101f001, 0x42a89100, 0x2900d801, 0xf898d1f6, 0x21000000,
+ 0xf0106031, 0xd1420f02, 0x21002006, 0x4aca6031, 0x60112101, 0xf4216839, 0xf4217140, 0x60392170,
+ 0x0000f888, 0x60302001, 0xf8cd2000, 0x6821a000, 0xf0011c40, 0x91000101, 0xd80142a8, 0xd1f62900,
+ 0xff6ef7ff, 0x60302000, 0xf8cb2001, 0x20050000, 0x60312100, 0xf4216839, 0xf4412170, 0x60397140,
+ 0x0000f888, 0x60302001, 0xf8cd2000, 0x6821a000, 0xf0011c40, 0x91000101, 0xd80142a8, 0xd1f62900,
+ 0x0000f898, 0x60312100, 0x0f02f010, 0xe9ddd0bc, 0x23000102, 0x60339a01, 0xc29cf8df, 0xf8cc2301,
+ 0x683b3000, 0x7340f423, 0x2370f423, 0xf888603b, 0x22002000, 0xd9062800, 0xf8885c8b, 0x1c523000,
+ 0x4290b2d2, 0x2001d8f8, 0x20006030, 0xa000f8cd, 0x1c406821, 0x0101f001, 0x42a89100, 0x2900d801,
+ 0xf7ffd1f6, 0x2000ff1d, 0x20016030, 0x0000f8cb, 0x21002005, 0x68396031, 0x2170f421, 0x7140f441,
+ 0xf8886039, 0x20010000, 0x20006030, 0xa000f8cd, 0x1c406821, 0x0101f001, 0x42a89100, 0x2900d801,
+ 0xf898d1f6, 0x21000000, 0xf0106031, 0xd1da0f02, 0xe8bdb004, 0x4a818df0, 0x2000b081, 0x91006811,
+ 0xd0042921, 0x60112121, 0x28141c40, 0x487cdbf6, 0xf0416801, 0x60010101, 0x680b497a, 0x0310f043,
+ 0x4979600b, 0xf443680b, 0x600b7380, 0xf443680b, 0x600b7300, 0x68194b75, 0x0120f041, 0x68016019,
+ 0x0106f021, 0x68106001, 0x1002f3c0, 0xbf282803, 0x4a6f2003, 0xf1a2444a, 0xf8120c04, 0xeb021020,
+ 0xf88c0080, 0x78421000, 0x2001f88c, 0xf88c7880, 0x48680002, 0xf0106800, 0xd0160f01, 0x68004866,
+ 0x0f20f010, 0x4865d011, 0xf0136803, 0xd00c7f80, 0xf3c06800, 0xf0004007, 0xeb03031f, 0xf88c0343,
+ 0xeb023002, 0xf88c1050, 0x23010001, 0xf88c4a51, 0x20003003, 0x485a6010, 0x1f006001, 0x49596003,
+ 0x90006808, 0x3001f89c, 0x000ff36f, 0x60084318, 0x68084955, 0xf89c9000, 0xf0203002, 0x431800ff,
+ 0x20046008, 0x60081f11, 0x1f0b2000, 0xf4216819, 0x9100117c, 0x60106019, 0x21384a4c, 0x4a4c6011,
+ 0x601121eb, 0x68114a4b, 0x71fff421, 0xb0016011, 0x20004770, 0x22004770, 0x0382eb00, 0x43d0f1a3,
+ 0xf841681b, 0x1c523022, 0x6f80f5b2, 0xf44fd3f4, 0x47705080, 0x45f8e92d, 0xf8df2400, 0x460e80b0,
+ 0x46a24607, 0x5530f247, 0x0084eb07, 0x40d0f1a0, 0x1024f856, 0x22006001, 0xa000f8cd, 0x0000f8d8,
+ 0xf0001c52, 0x90000001, 0xd80142aa, 0xd1f52800, 0xfe36f7ff, 0xf5b41c64, 0xd3e56f80, 0x5080f44f,
+ 0x85f8e8bd, 0x39080b01, 0xbf9c2902, 0x47702000, 0xf1a0b508, 0x0c0140d0, 0x1000f88d, 0xf88d0a01,
+ 0xf88d1001, 0x466a0002, 0x20202103, 0xfe57f7ff, 0xbd082000, 0x2700b5f8, 0x7000f88d, 0x7001f88d,
+ 0x4d1e4e1d, 0xf88d4c1e, 0x466a7002, 0x20202103, 0xfe45f7ff, 0xf88d2004, 0xf88d0000, 0xf88d7001,
+ 0x466a7002, 0xe02d2103, 0x40006004, 0x40006028, 0x40006060, 0x40006008, 0x40006118, 0x40000014,
+ 0x400002c0, 0x40000210, 0x40000230, 0x40000320, 0x00000008, 0x400001f4, 0x400000e0, 0x40000038,
+ 0x40006014, 0x4000611c, 0x40000300, 0x40006104, 0x400060f0, 0x40006120, 0x1fff8000, 0x1fff9000,
+ 0x1fffa000, 0xf7ff2020, 0xf44ffe0a, 0x46324300, 0xeb032000, 0xf1a10180, 0x680941d0, 0x1020f842,
+ 0xf5b01c40, 0xd3f46f80, 0x4310f44f, 0x2000462a, 0x0180eb03, 0x41d0f1a1, 0xf8426809, 0x1c401020,
+ 0x6f80f5b0, 0xf44fd3f4, 0x46214320, 0xeb032000, 0xf1a20280, 0x681242d0, 0x2020f841, 0xf5b01c40,
+ 0xd3f46f80, 0x46112200, 0xf7ff20c7, 0x4631fdd8, 0x4000f44f, 0xff3ef7ff, 0xf44f4629, 0xf7ff4010,
+ 0x4621ff39, 0x4020f44f, 0xff34f7ff, 0xbdf82000, 0x4ff8e92d, 0x000e4615, 0xf04f4607, 0xd01c0400,
+ 0x8078f8df, 0xf24746a3, 0x19385a30, 0x40d0f1a0, 0x60016829, 0xf8cd2000, 0xf8d8b000, 0x1c401000,
+ 0x0101f001, 0x45509100, 0x2900d801, 0xf7ffd1f5, 0x1d24fd67, 0x42b41d2d, 0x2000d3e7, 0x8ff8e8bd,
+ 0xf5a0b410, 0xf5b34300, 0xd9145f40, 0xebb32300, 0xd2100f91, 0x0c83eb00, 0x4cd0f1ac, 0xc000f8dc,
+ 0x4023f852, 0xd00245a4, 0x2001bc10, 0x1c5b4770, 0x0f91ebb3, 0xbc10d3ee, 0x47702000, 0x40006028,
+ 0x00000000, 0x00000000, 0x005e0101, 0x00000101, 0x00230201, 0x00050501
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, KB(4)},
+};
+
+static const program_target_t flash = {
+ 0x10007237, // Init
+ 0x10007353, // UnInit
+ 0x100073f5, // EraseChip
+ 0x100073c5, // EraseSector
+ 0x10007511, // ProgramPage
+
+ 0x10007561, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x10007001,
+ 0x100075a0,
+ 0x10007800
+ },
+
+ 0x10007000 + 0x00000A00, // mem buffer location
+ 0x10007000, // location to write prog_blob in target RAM
+ sizeof(rtl8195am_flash_prog_blob), // prog_blob size
+ rtl8195am_flash_prog_blob, // address of prog_blob
+ 0x00000400 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/realtek/rtl8195am/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/realtek/rtl8195am/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,52 @@
+/**
+ * @file target.c
+ * @brief Target information for Realtek RTL8195AM
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2016-2019, Realtek Semiconductor Corp., All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x00000000,
+ .flash_regions[0].end = 0x00000000 + MB(2),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x10007000,
+ .ram_regions[0].end = 0x10070000,
+};
+
+// RTL8195AM's main cpu can only talk 38400 with DAP UART
+#include "uart.h"
+static UART_Configuration UART_Config;
+
+int32_t USBD_CDC_ACM_SetLineCoding(void)
+{
+ UART_Config.Baudrate = 38400;
+ UART_Config.DataBits = UART_DATA_BITS_8;
+ UART_Config.Parity = UART_PARITY_NONE;
+ UART_Config.StopBits = UART_STOP_BITS_1;
+ UART_Config.FlowControl = UART_FLOW_CONTROL_NONE;
+
+ return uart_set_configuration(&UART_Config);
+}
diff -r 000000000000 -r 01f31e923fe2 source/family/realtek/target_reset_realtek_rtl8195am.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/realtek/target_reset_realtek_rtl8195am.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,41 @@
+/* CMSIS-DAP Interface Firmware
+ * Copyright (c) 2015-2019 Realtek Semiconductor Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <string.h>
+#include "swd_host.h"
+#include "DAP_config.h"
+#include "target_family.h"
+
+static void swd_set_target_reset_realtek(uint8_t asserted)
+{
+ if (asserted) {
+ swd_write_word(0xE000ED0C, 0x05FA0004);
+ }
+}
+
+static uint8_t validate_bin_nvic_realtek(const uint8_t *buf)
+{
+ const char header[] = {0x99, 0x99, 0x96, 0x96, 0x3F, 0xCC, 0x66, 0xFC,
+ 0xC0, 0x33, 0xCC, 0x03, 0xE5, 0xDC, 0x31, 0x62};
+
+ return !memcmp(header, buf, sizeof(header));
+}
+
+const target_family_descriptor_t g_realtek_rtl8195am = {
+ .family_id = kRealtek_Rtl8195am_FamilyID,
+ .default_reset_type = kHardwareReset,
+ .swd_set_target_reset = swd_set_target_reset_realtek,
+ .validate_bin_nvic = validate_bin_nvic_realtek,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/renesas/rza1h/gr-peach/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/renesas/rza1h/gr-peach/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,115 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t rza1xx_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x41f0e92d, 0x4efa4604, 0xf0106830, 0xd07d0f01, 0x4ff76961, 0xf44f220e, 0x3f184380, 0xf0004638,
+ 0x4df3fafb, 0x087ff44f, 0x3d246960, 0xf894b160, 0x22101046, 0x46284643, 0xfaeef000, 0x06bb6821,
+ 0x4638221e, 0xfae8f000, 0x220c69a1, 0x5380f44f, 0xf0004638, 0x69a0fae1, 0xf894b168, 0x23ff1047,
+ 0x46282200, 0xfad8f000, 0x221c6861, 0x5340f04f, 0xf0004638, 0x69e1fad1, 0xf44f2208, 0x46386370,
+ 0xfacaf000, 0xb17069e0, 0x220048d9, 0xf04f6ca1, 0x382033ff, 0xfac0f000, 0x221868a1, 0x7340f04f,
+ 0xf0004638, 0x6a21fab9, 0x220423f0, 0xf0004638, 0x6a20fab3, 0xf814b328, 0x22181f4c, 0xf04f4dcc,
+ 0x3d1c437f, 0xf0004628, 0x7861faa7, 0x46432210, 0xf0004628, 0x78a1faa1, 0xf44f2208, 0x4628437f,
+ 0xfa9af000, 0x23ff78e1, 0x46282200, 0xfa94f000, 0x1c40f854, 0x3c4c2214, 0x1340f44f, 0xf0004638,
+ 0x220ffa8b, 0x4300f44f, 0xe0004638, 0x6b61e027, 0xfa82f000, 0xf44f6b60, 0xb1783840, 0x1044f894,
+ 0x4db32210, 0x35184643, 0xf0004628, 0xf894fa75, 0x23071045, 0x46282200, 0xfa6ef000, 0x230f6a61,
+ 0x46382200, 0xfa68f000, 0x6a604da9, 0xb1d83d48, 0xd0072808, 0xd00a280c, 0xd00d280f, 0x2001e00e,
+ 0x81f0e8bd, 0x0058f894, 0x0040f885, 0xf8b4e006, 0xf8a50058, 0xe0010040, 0x64286da0, 0x69212210,
+ 0x46384643, 0xfa48f000, 0x8264f8df, 0x7780f44f, 0x22086aa1, 0xf1a8463b, 0x46400828, 0xfa3cf000,
+ 0x23046ae1, 0x46402202, 0xfa36f000, 0x23026b21, 0x46402201, 0xfa30f000, 0x4f8d463b, 0x22086ba1,
+ 0x4638371c, 0xfa28f000, 0x23106be1, 0x46382204, 0xfa22f000, 0x23016c21, 0x46382200, 0xfa1cf000,
+ 0x22002301, 0x46404619, 0xfa16f000, 0xf0106830, 0xd0fb0f01, 0x28086a60, 0x280cd004, 0x280fd005,
+ 0xe006d005, 0x0038f895, 0x8f28e002, 0x6ba8e000, 0x20006520, 0x2100e7a4, 0x60016141, 0x1046f880,
+ 0x60416181, 0x1047f880, 0x638161c1, 0x64816081, 0x63c16201, 0xf88060c1, 0xf880104c, 0xf880104d,
+ 0xf880104e, 0x6341104f, 0x1044f880, 0x1045f880, 0x64016241, 0x62816101, 0x630162c1, 0xb5704770,
+ 0x48644606, 0x4448460d, 0xffd5f7ff, 0x22004c61, 0x444c2001, 0x61606022, 0x6046f884, 0x200ae9c4,
+ 0x20086320, 0x61226422, 0x65e265a2, 0x46206260, 0xfeb6f7ff, 0xd1022800, 0x1050f894, 0xbd707029,
+ 0x2000b538, 0x1e424954, 0x1c40c104, 0xdbfb2810, 0x48522101, 0x68006001, 0x0035f241, 0x82084950,
+ 0x4950200f, 0x484f8008, 0x78013030, 0x0108f021, 0x78007001, 0x48462200, 0x46112301, 0xf000383c,
+ 0x4c43f99b, 0x6ca13c48, 0xd4fc0789, 0x23032200, 0x46204611, 0xf990f000, 0xf8b14943, 0xf0400224,
+ 0xf8a100fc, 0x48410224, 0x1324f8b0, 0x01fcf021, 0x1324f8a0, 0x8801483e, 0x01fcf041, 0x483d8001,
+ 0xf0218801, 0x800101fc, 0x8801483b, 0x01fcf021, 0x483a8001, 0xf0418801, 0x800101fc, 0x49386820,
+ 0x60204308, 0xf0206820, 0xf0400078, 0x60200020, 0x49346860, 0x60604008, 0xf2406de0, 0x43881111,
+ 0x68a065e0, 0x7103f64f, 0xf4404388, 0x60a07000, 0xf88d2000, 0x20050000, 0xf7ff4669, 0xb108ff70,
+ 0xbd382001, 0x0000f89d, 0x003cf020, 0x0140f040, 0xf88d2001, 0xf0001000, 0x221ff946, 0xf04f2101,
+ 0x46204300, 0xf938f000, 0x20006820, 0xb510bd38, 0x4c0f221f, 0xf04f2100, 0x3c484300, 0xf0004620,
+ 0x2100f92b, 0x221060e1, 0x21eb4809, 0x037ff44f, 0xf0003838, 0x4806f921, 0x22002307, 0x38342101,
+ 0xf91af000, 0x7103f64f, 0x200061e1, 0x0000bd10, 0x3fefa048, 0x00000004, 0xe8201180, 0x3fffff80,
+ 0xfcfe0000, 0xfcfe0408, 0xfcfe7000, 0xfcfe3000, 0xfcfe3524, 0xfcfe3624, 0xfcfe3a24, 0xfcfe3424,
+ 0x00fff300, 0xfffcfcfc, 0xf000b510, 0x2800f924, 0x4899d1dc, 0xf7ff4448, 0x4897feee, 0x44482101,
+ 0x21006141, 0x21c76001, 0x1046f880, 0xfdd8f7ff, 0xd1cb2800, 0x4010e8bd, 0xb901f000, 0xb510e7c6,
+ 0xf0004604, 0x2800f908, 0x488bd1c0, 0xf7ff4448, 0x4889fed2, 0x22202101, 0x61414448, 0x60012100,
+ 0x2046f880, 0x63812207, 0x61c26484, 0xf7ff6081, 0x2800fdb7, 0xe8bdd1aa, 0xf0004010, 0xe7a5b8e0,
+ 0x47f0e92d, 0x4616000c, 0xd0564605, 0xf8e3f000, 0xd1522800, 0x44484878, 0xfeadf7ff, 0xf04f4f76,
+ 0xf04f0a00, 0x22020801, 0x4638444f, 0xa000f8c7, 0x8014f8c7, 0x2046f887, 0xf8c72207, 0xf8c7a038,
+ 0xf8c7a008, 0x64bd8028, 0xf7ff61fa, 0x2800fd89, 0x4638d133, 0xfe8ff7ff, 0x8028f8c7, 0x8030f8c7,
+ 0xf8c746d0, 0xf8c7a010, 0xe020a040, 0xd3052c04, 0x6278200f, 0x68302504, 0xe00c65b8, 0xd3052c02,
+ 0x6278200c, 0x88302502, 0xe00465b8, 0x25012008, 0x78306278, 0x42ac65b8, 0xf8c7d801, 0x48568028,
+ 0xf7ff4448, 0x2800fd5d, 0x1b64d107, 0x2c00442e, 0xe8bdd1dc, 0xf00047f0, 0xe8bdb882, 0xe92d87f0,
+ 0x468247f0, 0x4616484c, 0x4448460d, 0xfe53f7ff, 0xf04f4f49, 0x24010800, 0x444f2103, 0xf8c74638,
+ 0x617c8000, 0x1046f887, 0xf8c72107, 0xf8c78038, 0xf8c7a048, 0x62bc8008, 0xf7ff61f9, 0xbb98fd31,
+ 0xf7ff4638, 0x62bcfe38, 0x8010f8c7, 0x8040f8c7, 0xe02d62fc, 0xd3032d04, 0x2404200f, 0xe0086278,
+ 0xd3032d02, 0x2402200c, 0xe0026278, 0x24012008, 0x42a56278, 0xf8c7d801, 0x482f8028, 0xf7ff4448,
+ 0x2800fd0f, 0x2c04d1b9, 0x2c02d005, 0xf897d006, 0x78310050, 0x6d38e006, 0xe0036831, 0x0050f8b7,
+ 0xb2808831, 0xd0014288, 0xe7a62001, 0x44261b2d, 0xd1cf2d00, 0xe7a02000, 0x6804b510, 0x439c4091,
+ 0x6004430c, 0xb570e6e2, 0x481b4605, 0x4448460c, 0xfdf1f7ff, 0x23004a18, 0x444a2001, 0x61506013,
+ 0x5046f882, 0x300ae9c2, 0x20086310, 0x61136413, 0x46106250, 0x4316e9c2, 0x4070e8bd, 0xb508e4d0,
+ 0x46692005, 0xfdfbf7ff, 0xd1032800, 0x1000f89d, 0xd1f507c9, 0x4808bd08, 0x4448b510, 0xfdcbf7ff,
+ 0x21014805, 0x61414448, 0x60012100, 0xf8802106, 0xe8bd1046, 0xe4b34010, 0x00000004, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+};
+
+// Start address of flash
+static const uint32_t flash_start = 0x18000000;
+// Size of flash
+static const uint32_t flash_size = 0x00800000;
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, KB(4)},
+};
+
+static const program_target_t flash = {
+ 0x200202c1, // Init
+ 0x200203cf, // UnInit
+ 0x20020449, // EraseChip
+ 0x2002047f, // EraseSector
+ 0x200204c1, // ProgramPage
+ 0x2002057f, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20020001,
+ 0x200206bc,
+ 0x20020900
+ },
+
+ 0x20020000 + 0x00004000, // mem buffer location
+ 0x20020000, // location to write prog_blob in target RAM
+ sizeof(rza1xx_flash_prog_blob), // prog_blob size
+ rza1xx_flash_prog_blob, // address of prog_blob
+ 0x00000100 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/renesas/rza1h/gr-peach/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/renesas/rza1h/gr-peach/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the GR-PEACH
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = MB(8),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20A00000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/renesas/rza1lu/gr-lychee/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/renesas/rza1lu/gr-lychee/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,118 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t rza1xx_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x41f0e92d, 0x4efe4604, 0xf0106830, 0xd07d0f01, 0x4ffb6961, 0xf44f220e, 0x3f184380, 0xf0004638,
+ 0x4df7fb08, 0x087ff44f, 0x3d246960, 0xf894b160, 0x22101046, 0x46284643, 0xfafbf000, 0x06bb6821,
+ 0x4638221e, 0xfaf5f000, 0x220c69a1, 0x5380f44f, 0xf0004638, 0x69a0faee, 0xf894b168, 0x23ff1047,
+ 0x46282200, 0xfae5f000, 0x221c6861, 0x5340f04f, 0xf0004638, 0x69e1fade, 0xf44f2208, 0x46386370,
+ 0xfad7f000, 0xb17069e0, 0x220048dd, 0xf04f6ca1, 0x382033ff, 0xfacdf000, 0x221868a1, 0x7340f04f,
+ 0xf0004638, 0x6a21fac6, 0x220423f0, 0xf0004638, 0x6a20fac0, 0xf814b328, 0x22181f4c, 0xf04f4dd0,
+ 0x3d1c437f, 0xf0004628, 0x7861fab4, 0x46432210, 0xf0004628, 0x78a1faae, 0xf44f2208, 0x4628437f,
+ 0xfaa7f000, 0x23ff78e1, 0x46282200, 0xfaa1f000, 0x1c40f854, 0x3c4c2214, 0x1340f44f, 0xf0004638,
+ 0x220ffa98, 0x4300f44f, 0xe0004638, 0x6b61e027, 0xfa8ff000, 0xf44f6b60, 0xb1783840, 0x1044f894,
+ 0x4db72210, 0x35184643, 0xf0004628, 0xf894fa82, 0x23071045, 0x46282200, 0xfa7bf000, 0x230f6a61,
+ 0x46382200, 0xfa75f000, 0x6a604dad, 0xb1d83d48, 0xd0072808, 0xd00a280c, 0xd00d280f, 0x2001e00e,
+ 0x81f0e8bd, 0x0058f894, 0x0040f885, 0xf8b4e006, 0xf8a50058, 0xe0010040, 0x64286da0, 0x69212210,
+ 0x46384643, 0xfa55f000, 0x8274f8df, 0x7780f44f, 0x22086aa1, 0xf1a8463b, 0x46400828, 0xfa49f000,
+ 0x23046ae1, 0x46402202, 0xfa43f000, 0x23026b21, 0x46402201, 0xfa3df000, 0x4f91463b, 0x22086ba1,
+ 0x4638371c, 0xfa35f000, 0x23106be1, 0x46382204, 0xfa2ff000, 0x23016c21, 0x46382200, 0xfa29f000,
+ 0x22002301, 0x46404619, 0xfa23f000, 0xf0106830, 0xd0fb0f01, 0x28086a60, 0x280cd004, 0x280fd005,
+ 0xe006d005, 0x0038f895, 0x8f28e002, 0x6ba8e000, 0x20006520, 0x2100e7a4, 0x60016141, 0x1046f880,
+ 0x60416181, 0x1047f880, 0x638161c1, 0x64816081, 0x63c16201, 0xf88060c1, 0xf880104c, 0xf880104d,
+ 0xf880104e, 0x6341104f, 0x1044f880, 0x1045f880, 0x64016241, 0x62816101, 0x630162c1, 0xb5704770,
+ 0x48684605, 0x4448460c, 0xffd5f7ff, 0x23004a65, 0x444a2001, 0x61506013, 0x5046f882, 0x300ae9c2,
+ 0x20086310, 0x61136413, 0x46106250, 0x4316e9c2, 0x4070e8bd, 0xb570e6b4, 0x485a4606, 0x4448460d,
+ 0xffb9f7ff, 0x22004c57, 0x444c2001, 0x61606022, 0x6046f884, 0x200ae9c4, 0x20086320, 0x61226422,
+ 0x65e265a2, 0x46206260, 0xfe9af7ff, 0xd1022800, 0x1050f894, 0xbd707029, 0x2000494b, 0x1e42b510,
+ 0x1c40c104, 0xdbfb2810, 0x48482101, 0x68006001, 0x0035f241, 0x82084946, 0x4946200f, 0x48458008,
+ 0x78013030, 0x0108f021, 0x78007001, 0x483c2200, 0x46112301, 0xf000383c, 0x4c39f98c, 0x6ca13c48,
+ 0xd4fc0789, 0x23032200, 0x46204611, 0xf981f000, 0xf8b14939, 0xf0400210, 0xf8a100fc, 0x49370210,
+ 0x0310f8b1, 0x00fcf020, 0x0310f8a1, 0x88014834, 0x01fcf041, 0x48338001, 0xf0218801, 0x800101fc,
+ 0x88014831, 0x01fcf021, 0x48308001, 0xf0418801, 0x800101fc, 0x492e6820, 0x60204308, 0xf0206820,
+ 0xf0400078, 0x60200020, 0x492a6860, 0x60604008, 0xf2406de0, 0x43881111, 0x68a065e0, 0x7103f64f,
+ 0xf4404388, 0x60a07000, 0xf94af000, 0x2001b108, 0x221fbd10, 0xf04f2101, 0x46204300, 0xf939f000,
+ 0x20006820, 0xb510bd10, 0x4c0d221f, 0xf04f2100, 0x3c484300, 0xf0004620, 0x2100f92c, 0x221060e1,
+ 0x21eb4807, 0x037ff44f, 0xf0003838, 0x4804f922, 0x22002307, 0x38342101, 0xf91bf000, 0x0000e01c,
+ 0x3fefa048, 0x00000004, 0xe8201180, 0x3fffff80, 0xfcfe0000, 0xfcfe0408, 0xfcfe7000, 0xfcfe3000,
+ 0xfcfe3510, 0xfcfe3610, 0xfcfe3a10, 0xfcfe3410, 0x00fff300, 0xfffcfcfc, 0x7103f64f, 0x200061e1,
+ 0xb510bd10, 0xf93cf000, 0xd1142800, 0x444848a5, 0xfee1f7ff, 0x210148a3, 0x61414448, 0x60012100,
+ 0xf88021c7, 0xf7ff1046, 0x2800fdcb, 0xe8bdd103, 0xf0004010, 0xbd10b919, 0x4604b510, 0xf920f000,
+ 0xd1192800, 0x44484897, 0xfec5f7ff, 0x21014895, 0x44482220, 0x21006141, 0xf8806001, 0x22072046,
+ 0x64846381, 0x608161c2, 0xfdaaf7ff, 0xd1032800, 0x4010e8bd, 0xb8f8f000, 0xe92dbd10, 0x000c47f0,
+ 0x46054616, 0xf000d056, 0x2800f8fb, 0x4885d152, 0xf7ff4448, 0x4f83fea0, 0x0a00f04f, 0x0801f04f,
+ 0x444f2202, 0xf8c74638, 0xf8c7a000, 0xf8878014, 0x22072046, 0xa038f8c7, 0xa008f8c7, 0x8028f8c7,
+ 0x61fa64bd, 0xfd7cf7ff, 0xd1332800, 0xf7ff4638, 0xf8c7fe82, 0xf8c78028, 0x46d08030, 0xa010f8c7,
+ 0xa040f8c7, 0x2c04e020, 0x200fd305, 0x25046278, 0x65b86830, 0x2c02e00c, 0x200cd305, 0x25026278,
+ 0x65b88830, 0x2008e004, 0x62782501, 0x65b87830, 0xd80142ac, 0x8028f8c7, 0x44484862, 0xfd50f7ff,
+ 0xd1072800, 0x442e1b64, 0xd1dc2c00, 0x47f0e8bd, 0xb89af000, 0x87f0e8bd, 0x47f0e92d, 0x48594682,
+ 0x460d4616, 0xf7ff4448, 0x4f56fe46, 0x0800f04f, 0x21032401, 0x4638444f, 0x8000f8c7, 0xf887617c,
+ 0x21071046, 0x8038f8c7, 0xa048f8c7, 0x8008f8c7, 0x61f962bc, 0xfd24f7ff, 0x4638bb98, 0xfe2bf7ff,
+ 0xf8c762bc, 0xf8c78010, 0x62fc8040, 0x2d04e02d, 0x200fd303, 0x62782404, 0x2d02e008, 0x200cd303,
+ 0x62782402, 0x2008e002, 0x62782401, 0xd80142a5, 0x8028f8c7, 0x4448483b, 0xfd02f7ff, 0xd1b92800,
+ 0xd0052c04, 0xd0062c02, 0x0050f897, 0xe0067831, 0x68316d38, 0xf8b7e003, 0x88310050, 0x4288b280,
+ 0x2001d001, 0x1b2de7a6, 0x2d004426, 0x2000d1cf, 0xb510e7a0, 0x40916804, 0x430c439c, 0xbd106004,
+ 0x2000b508, 0xf88d4669, 0x20050000, 0xfe23f7ff, 0xf89db9e8, 0xf0200000, 0x2001011c, 0x1000f88d,
+ 0xfdfdf7ff, 0x46692035, 0xfe15f7ff, 0xf89db978, 0xf0200000, 0xf0400039, 0x20310102, 0x1000f88d,
+ 0xfdedf7ff, 0x46692015, 0xfe05f7ff, 0x2001b108, 0xf89dbd08, 0xf0200000, 0x20110104, 0x1000f88d,
+ 0xfdddf7ff, 0xbd082000, 0x2005b508, 0xf7ff4669, 0x2800fdf2, 0xf89dd103, 0x07c91000, 0xbd08d1f5,
+ 0xb5104808, 0xf7ff4448, 0x4806fda6, 0x44482101, 0x21006141, 0x21066001, 0x1046f880, 0x4010e8bd,
+ 0x0000e48e, 0x00000004, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000
+};
+
+// Start address of flash
+static const uint32_t flash_start = 0x18000000;
+// Size of flash
+static const uint32_t flash_size = 0x00800000;
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, KB(4)},
+};
+
+static const program_target_t flash = {
+ 0x200202f9, // Init
+ 0x200203e7, // UnInit
+ 0x20020463, // EraseChip
+ 0x20020499, // EraseSector
+ 0x200204db, // ProgramPage
+ 0x20020599, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20020001,
+ 0x20020708,
+ 0x20020a00
+ },
+
+ 0x20020000 + 0x00004000, // mem buffer location
+ 0x20020000, // location to write prog_blob in target RAM
+ sizeof(rza1xx_flash_prog_blob), // prog_blob size
+ rza1xx_flash_prog_blob, // address of prog_blob
+ 0x00000100 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/renesas/rza1lu/gr-lychee/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/renesas/rza1lu/gr-lychee/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the GR-LYCHEE
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = MB(8),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20300000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/renesas/target_reset_rza.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/renesas/target_reset_rza.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,58 @@
+/**
+ * @file target_reset.c
+ * @brief Target reset for the rza1h
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "swd_host.h"
+#include "target_family.h"
+
+static uint8_t target_set_state_rza(target_state_t state)
+{
+ return swd_set_target_state_hw(state);
+}
+
+#define BINARY_DETECTION (0xE59FF000)
+
+static uint8_t validate_bin_nvic_rza(const uint8_t *buf)
+{
+ // Very dirty hacking here for ARMv7-A (non Cortex-M) binary detection
+ // This returns validated result when start instrunction
+ // of the buffer is BINARY_DETECTION (LDR PC, Label)
+ // Compared with the high-order 3byte
+ if ((buf[1] == ((BINARY_DETECTION >> 8) & 0xFF))
+ && (buf[2] == ((BINARY_DETECTION >> 16) & 0xFF))
+ && (buf[3] == ((BINARY_DETECTION >> 24) & 0xFF))) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+static uint8_t validate_hexfile_rza(const uint8_t *buf)
+{
+ return 0;
+}
+
+const target_family_descriptor_t g_renesas_family = {
+ .family_id = kRenesas_FamilyID,
+ .target_set_state = target_set_state_rza,
+ .validate_bin_nvic = validate_bin_nvic_rza,
+ .validate_hexfile = validate_hexfile_rza,
+};
+
diff -r 000000000000 -r 01f31e923fe2 source/family/siliconlabs/efm32gg/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/siliconlabs/efm32gg/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,82 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the efm32gg
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t efm32gg_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x4770ba40, 0x4770bac0, 0x4c0cb510, 0xf04068a0, 0x60a00001, 0x301af246, 0xf44f6560, 0x60e07040,
+ 0x20012100, 0xf83ef000, 0x65612100, 0xf02168a1, 0x60a10101, 0xbf182800, 0xbd102001, 0x400c0000,
+ 0x4684b510, 0xf44f2300, 0xf8505180, 0x1f092b04, 0x1c52d002, 0xe001d0f9, 0xd0131c50, 0x68a04c0c,
+ 0x0001f040, 0xf8c460a0, 0x2001c010, 0x200260e0, 0x210060e0, 0xf0002001, 0x4603f815, 0xf02068a0,
+ 0x60a00001, 0xbf142b00, 0x20002001, 0x0000bd10, 0x400c0000, 0xf6414902, 0x63c83071, 0x47702000,
+ 0x400c0000, 0x4b14b410, 0xc050f8df, 0x201cf8dc, 0x0f16f012, 0xf8dcd014, 0xf0200008, 0xf8cc0005,
+ 0xf0120008, 0xbf1e0f02, 0x0001f06f, 0x4770bc10, 0x0f04f012, 0xf04fbf1e, 0xbc1030ff, 0xe0074770,
+ 0x428a4002, 0xbc10d102, 0x47702000, 0xd1dd1e5b, 0xf06fbc10, 0x47700002, 0x00989680, 0x400c0000,
+ 0x4df0e92d, 0x1cc84604, 0x0603f020, 0x46904859, 0xf0416881, 0x60810101, 0xd9732e07, 0x0f07f014,
+ 0xf8d8d011, 0x61041000, 0x60c22201, 0x21086181, 0x210060c1, 0xf7ff4610, 0x2800ffb5, 0x1d24d17e,
+ 0x0810f108, 0x484b1f36, 0xf0416881, 0x60810104, 0xbf882e07, 0x0a02f06f, 0xf504d966, 0x46015080,
+ 0x010bf36f, 0x42b11b09, 0x4635bf8e, 0x000bf36f, 0xf0151b05, 0xbf180f04, 0x46471f2d, 0x20012100,
+ 0xff90f7ff, 0xd13b2800, 0xe0e8f8df, 0x4010f8ce, 0xf8ce2001, 0xf857000c, 0xf8ce0b04, 0xf8570018,
+ 0xf8ce0b04, 0x20080018, 0x000cf8ce, 0x0208f1a5, 0xd9332a07, 0x0b08f04f, 0x46dc482f, 0x101cf8de,
+ 0x0f16f011, 0xf8ded012, 0xf0200008, 0xf8ce0005, 0xf0110008, 0xbf180f02, 0x0001f06f, 0xf011d10f,
+ 0xbf180f04, 0x30fff04f, 0xe007d109, 0x010bea01, 0xd1014561, 0xe0022000, 0xd1df1e40, 0xb1104650,
+ 0xe00bb9e0, 0xf857e01c, 0xf8ce0b04, 0xf8570018, 0xf8ce0b04, 0x3a080018, 0xd8cb2a07, 0xeb081b76,
+ 0x442c0885, 0xd8982e07, 0x20012100, 0xff3af7ff, 0x4810b920, 0xf0216881, 0xe0000104, 0x6081e00f,
+ 0x480cb186, 0x1000f8d8, 0x22016104, 0x618160c2, 0x60c12108, 0x46102100, 0xff24f7ff, 0x2001b110,
+ 0x8df0e8bd, 0x68814803, 0x0101f021, 0x20006081, 0x8df0e8bd, 0x400c0000, 0x00989680, 0x68814803,
+ 0x0105f021, 0x20006081, 0x00004770, 0x400c0000, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 4096},
+};
+
+static const program_target_t flash = {
+ 0x200000B5, // Init
+ 0x2000029D, // UnInit
+ 0x20000029, // EraseChip
+ 0x20000061, // EraseSector
+ 0x20000121, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000000 + 0x00000001,
+ 0x20000000 + 0x00000020 + 0x00000290,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(efm32gg_flash_prog_blob), // prog_blob size
+ efm32gg_flash_prog_blob, // address of prog_blob
+ 0x00000200 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/siliconlabs/efm32gg/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/siliconlabs/efm32gg/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the efm32gg
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = MB(1),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20010000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/nz32_sc151/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/nz32_sc151/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,77 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t stm32l1xx_256_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0xbf182a01, 0xd11e2a02, 0x680148a5, 0x6170f441, 0x48a56001, 0x600149a3, 0x600149a4, 0x0004f100,
+ 0x600149a3, 0x600149a3, 0x680048a3, 0x1f80f410, 0x48a2d109, 0x5155f245, 0xf04f6001, 0x60410106,
+ 0x71fff640, 0xf04f6081, 0x47700000, 0xbf182801, 0xd1082802, 0x6801489a, 0x0102f041, 0x68016001,
+ 0x0101f041, 0xf04f6001, 0x47700000, 0xc250f8df, 0x1000f8dc, 0x0f01f011, 0x498bd004, 0x600a4a89,
+ 0x600a4a8a, 0x1000f8dc, 0x0f02f011, 0x498dd004, 0x600a4a87, 0x600a4a87, 0x1000f8dc, 0x7100f441,
+ 0x1000f8cc, 0x1000f8dc, 0x0108f041, 0x1000f8cc, 0x60012100, 0x6801487a, 0x0f01f011, 0xf64abf1c,
+ 0x4a7e21aa, 0x6011d004, 0xf0136803, 0xd1fa0f01, 0xf4116801, 0xd0056f70, 0xf4416801, 0x60016170,
+ 0x47702001, 0x0000f8dc, 0x7000f420, 0x0000f8cc, 0x0000f8dc, 0x0008f020, 0x0000f8cc, 0x47702000,
+ 0x4df0e92d, 0x4f674c68, 0x81a0f8df, 0xa1a0f8df, 0xb1a0f8df, 0x4a624e69, 0xf04f4b69, 0x1d256100,
+ 0x0e00f04f, 0x2caaf64a, 0xf0106818, 0xbf1c0f01, 0xf8c46027, 0x68188000, 0x0f02f010, 0xf8c5bf1c,
+ 0xf8c5a000, 0x6818b000, 0x7000f440, 0x68186018, 0x0008f040, 0xf8c16018, 0x6810e000, 0x0f01f010,
+ 0xf8c6d005, 0x6810c000, 0x0f01f010, 0x6810d1f9, 0x6f70f410, 0x6810d005, 0x6070f440, 0x20016010,
+ 0x6818e008, 0x7000f420, 0x68186018, 0x0008f020, 0x20006018, 0xbf182800, 0x8df0e8bd, 0xf501484a,
+ 0x42817180, 0x2000d3c0, 0x8df0e8bd, 0x47702001, 0x4e43b4f0, 0x31ff2380, 0xc000f8d6, 0x01fff021,
+ 0x6c80f44c, 0xc000f8c6, 0xc000f8d6, 0x0c08f04c, 0xc000f8c6, 0xf852e005, 0xf840cb04, 0x1f09cb04,
+ 0x29001f1b, 0x2b00bf18, 0xf8dfd1f5, 0xf8dcc0b4, 0x4d323000, 0x0f01f013, 0x24aaf64a, 0x602cd005,
+ 0x3000f8dc, 0x0f01f013, 0xf8dcd1f9, 0xf4133000, 0xd12e6f70, 0xf4236833, 0x60336380, 0xf0236833,
+ 0x60330308, 0xf4436833, 0x60336380, 0xf0436833, 0x60330308, 0x0380f04f, 0xf852e007, 0xf8407b04,
+ 0xf1a17b04, 0xf1a30104, 0x29000304, 0x2b00bf18, 0xf8dcd1f3, 0xf0100000, 0xd0050f01, 0xf8dc602c,
+ 0xf0100000, 0xd1f90f01, 0x0000f8dc, 0x6f70f410, 0xf8dcd009, 0xf4400000, 0xf8cc6070, 0xbcf00000,
+ 0x0001f04f, 0x68304770, 0x6080f420, 0x68306030, 0x0008f020, 0xbcf06030, 0x0000f04f, 0x00004770,
+ 0x40023c18, 0x89abcdef, 0x40023c0c, 0x02030405, 0x8c9daebf, 0x13141516, 0x40023c1c, 0x40003000,
+ 0x40023c04, 0x40023c10, 0x08040000, 0x00000000
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x08000000, 256},
+};
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x2000006d, // UnInit
+ 0x20000121, // EraseChip
+ 0x2000008d, // EraseSector
+ 0x200001d1, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x200002ec,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(stm32l1xx_256_flash_prog_blob), // prog_blob size
+ stm32l1xx_256_flash_prog_blob, // address of prog_blob
+ 0x00000100 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/nz32_sc151/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/nz32_sc151/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the stm32l151
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x08000000,
+ .flash_regions[0].end = 0x08000000 + KB(256),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20000000 + KB(32),
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f072rb/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f072rb/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,64 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t STM32F072RB_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x49454846, 0x49466041, 0x21006041, 0x68c16001, 0x43112214, 0x69c060c1, 0xd4060740, 0x49414842,
+ 0x21066001, 0x49416041, 0x20006081, 0x483b4770, 0x22806901, 0x61014311, 0x47702000, 0x4837b530,
+ 0x241468c1, 0x60c14321, 0x25046901, 0x61014329, 0x22406901, 0x61014311, 0x4a334935, 0x6011e000,
+ 0x07db68c3, 0x6901d1fb, 0x610143a9, 0x422168c1, 0x68c1d004, 0x60c14321, 0xbd302001, 0xbd302000,
+ 0x4926b530, 0x231468ca, 0x60ca431a, 0x2402690a, 0x610a4322, 0x69086148, 0x43102240, 0x48246108,
+ 0xe0004a21, 0x68cd6010, 0xd1fb07ed, 0x43a06908, 0x68c86108, 0xd0034018, 0x431868c8, 0x200160c8,
+ 0xb5f0bd30, 0x1c494d15, 0x68eb0849, 0x24040049, 0x60eb4323, 0x4c162714, 0x692be01a, 0x43332601,
+ 0x8813612b, 0x4b108003, 0x601ce000, 0x07f668ee, 0x692bd1fb, 0x005b085b, 0x68eb612b, 0xd004423b,
+ 0x433868e8, 0x200160e8, 0x1c80bdf0, 0x1e891c92, 0xd1e22900, 0xbdf02000, 0x45670123, 0x40022000,
+ 0xcdef89ab, 0x00005555, 0x40003000, 0x00000fff, 0x0000aaaa, 0x00000000
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x08000000, 0x400},
+};
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x2000004f, // UnInit
+ 0x2000005d, // EraseChip
+ 0x200000a1, // EraseSector
+ 0x200000e3, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x20000154,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(STM32F072RB_flash_prog_blob), // prog_blob size
+ STM32F072RB_flash_prog_blob, // address of prog_blob
+ 0x00000400 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f072rb/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f072rb/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x08000000,
+ .flash_regions[0].end = 0x08020000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20004000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f103rb/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f103rb/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,64 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t STM32F103RB_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x4603b510, 0x4c442000, 0x48446020, 0x48446060, 0x46206060, 0xf01069c0, 0xd1080f04, 0x5055f245,
+ 0x60204c40, 0x60602006, 0x70fff640, 0x200060a0, 0x4601bd10, 0x69004838, 0x0080f040, 0x61104a36,
+ 0x47702000, 0x69004834, 0x0004f040, 0x61084932, 0x69004608, 0x0040f040, 0xe0036108, 0x20aaf64a,
+ 0x60084930, 0x68c0482c, 0x0f01f010, 0x482ad1f6, 0xf0206900, 0x49280004, 0x20006108, 0x46014770,
+ 0x69004825, 0x0002f040, 0x61104a23, 0x61414610, 0xf0406900, 0x61100040, 0xf64ae003, 0x4a2120aa,
+ 0x481d6010, 0xf01068c0, 0xd1f60f01, 0x6900481a, 0x0002f020, 0x61104a18, 0x47702000, 0x4603b510,
+ 0xf0201c48, 0xe0220101, 0x69004813, 0x0001f040, 0x61204c11, 0x80188810, 0x480fbf00, 0xf01068c0,
+ 0xd1fa0f01, 0x6900480c, 0x0001f020, 0x61204c0a, 0x68c04620, 0x0f14f010, 0x4620d006, 0xf04068c0,
+ 0x60e00014, 0xbd102001, 0x1c921c9b, 0x29001e89, 0x2000d1da, 0x0000e7f7, 0x40022000, 0x45670123,
+ 0xcdef89ab, 0x40003000, 0x00000000
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x08000000, 0x400},
+};
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000053, // UnInit
+ 0x20000065, // EraseChip
+ 0x2000009f, // EraseSector
+ 0x200000dd, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x20000148,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(STM32F103RB_flash_prog_blob), // prog_blob size
+ STM32F103RB_flash_prog_blob, // address of prog_blob
+ 0x00000400 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f103rb/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f103rb/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x08000000,
+ .flash_regions[0].end = 0x08020000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20005000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f207zg/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f207zg/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,65 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t STM32F207ZG_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x0e000300, 0xd3022820, 0x1d000940, 0x28104770, 0x0900d302, 0x47701cc0, 0x47700880, 0x49414842,
+ 0x49426041, 0x21006041, 0x68c16001, 0x431122f0, 0x694060c1, 0xd4060680, 0x493d483e, 0x21066001,
+ 0x493d6041, 0x20006081, 0x48374770, 0x05426901, 0x61014311, 0x47702000, 0x4833b510, 0x24046901,
+ 0x61014321, 0x03a26901, 0x61014311, 0x4a314933, 0x6011e000, 0x03db68c3, 0x6901d4fb, 0x610143a1,
+ 0xbd102000, 0xf7ffb530, 0x4927ffbb, 0x23f068ca, 0x60ca431a, 0x610c2402, 0x0700690a, 0x43020e40,
+ 0x6908610a, 0x431003e2, 0x48246108, 0xe0004a21, 0x68cd6010, 0xd4fb03ed, 0x43a06908, 0x68c86108,
+ 0x0f000600, 0x68c8d003, 0x60c84318, 0xbd302001, 0x4d15b570, 0x08891cc9, 0x008968eb, 0x433326f0,
+ 0x230060eb, 0x4b16612b, 0x692ce017, 0x612c431c, 0x60046814, 0x03e468ec, 0x692cd4fc, 0x00640864,
+ 0x68ec612c, 0x0f240624, 0x68e8d004, 0x60e84330, 0xbd702001, 0x1d121d00, 0x29001f09, 0x2000d1e5,
+ 0x0000bd70, 0x45670123, 0x40023c00, 0xcdef89ab, 0x00005555, 0x40003000, 0x00000fff, 0x0000aaaa,
+ 0x00000201, 0x00000000
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x08000000, 0x4000},
+};
+
+static const program_target_t flash = {
+ 0x2000003d, // Init
+ 0x2000006b, // UnInit
+ 0x20000079, // EraseChip
+ 0x200000a5, // EraseSector
+ 0x200000f1, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x20000164,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(STM32F207ZG_flash_prog_blob), // prog_blob size
+ STM32F207ZG_flash_prog_blob, // address of prog_blob
+ 0x00000400 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f207zg/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f207zg/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x08000000,
+ .flash_regions[0].end = 0x08100000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20020000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f334r8/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f334r8/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,62 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t STM32F334R8_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x49364837, 0x49376041, 0x21006041, 0x68c16001, 0x43112214, 0x69c060c1, 0xd40605c0, 0x49324833,
+ 0x21066001, 0x49326041, 0x20006081, 0x482c4770, 0x22806901, 0x61014311, 0x47702000, 0x4828b510,
+ 0x24046901, 0x61014321, 0x22406901, 0x61014311, 0x4a264928, 0x6011e000, 0x07db68c3, 0x6901d1fb,
+ 0x610143a1, 0xbd102000, 0x491db510, 0x2402690a, 0x610a4322, 0x69086148, 0x43102240, 0x481d6108,
+ 0xe0004a1a, 0x68cb6010, 0xd1fb07db, 0x43a06908, 0x20006108, 0xb570bd10, 0x08491c49, 0x26140049,
+ 0x23014d0f, 0x692ce016, 0x612c431c, 0x80048814, 0x07e468ec, 0x692cd1fc, 0x00640864, 0x68ec612c,
+ 0xd0044234, 0x433068e8, 0x200160e8, 0x1c80bd70, 0x1e891c92, 0xd1e62900, 0xbd702000, 0x45670123,
+ 0x40022000, 0xcdef89ab, 0x00005555, 0x40003000, 0x00000fff, 0x0000aaaa, 0x00000000
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x08000000, 0x800},
+};
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x2000004f, // UnInit
+ 0x2000005d, // EraseChip
+ 0x20000089, // EraseSector
+ 0x200000b7, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x20000118,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(STM32F334R8_flash_prog_blob), // prog_blob size
+ STM32F334R8_flash_prog_blob, // address of prog_blob
+ 0x00000400 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f334r8/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f334r8/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x08000000,
+ .flash_regions[0].end = 0x08010000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20003000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f401re/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f401re/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,65 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t STM32F401RE_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x03004601, 0x28200e00, 0x0940d302, 0xe0051d00, 0xd3022810, 0x1cc00900, 0x0880e000, 0xd50102c9,
+ 0x43082110, 0x48424770, 0x60414940, 0x60414941, 0x60012100, 0x22f068c1, 0x60c14311, 0x06806940,
+ 0x483ed406, 0x6001493c, 0x60412106, 0x6081493c, 0x47702000, 0x69014836, 0x43110542, 0x20006101,
+ 0xb5104770, 0x69014832, 0x43212404, 0x69016101, 0x431103a2, 0x49336101, 0xe0004a30, 0x68c36011,
+ 0xd4fb03db, 0x43a16901, 0x20006101, 0xb530bd10, 0xffb6f7ff, 0x68ca4926, 0x431a23f0, 0x240260ca,
+ 0x690a610c, 0x0e0006c0, 0x610a4302, 0x03e26908, 0x61084310, 0x4a214823, 0x6010e000, 0x03ed68cd,
+ 0x6908d4fb, 0x610843a0, 0x060068c8, 0xd0030f00, 0x431868c8, 0x200160c8, 0xb570bd30, 0x1cc94d14,
+ 0x68eb0889, 0x26f00089, 0x60eb4333, 0x612b2300, 0xe0174b15, 0x431c692c, 0x6814612c, 0x68ec6004,
+ 0xd4fc03e4, 0x0864692c, 0x612c0064, 0x062468ec, 0xd0040f24, 0x433068e8, 0x200160e8, 0x1d00bd70,
+ 0x1f091d12, 0xd1e52900, 0xbd702000, 0x45670123, 0x40023c00, 0xcdef89ab, 0x00005555, 0x40003000,
+ 0x00000fff, 0x0000aaaa, 0x00000201, 0x00000000
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x08000000, 0x4000},
+};
+
+static const program_target_t flash = {
+ 0x20000047, // Init
+ 0x20000075, // UnInit
+ 0x20000083, // EraseChip
+ 0x200000af, // EraseSector
+ 0x200000fb, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x2000016c,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(STM32F401RE_flash_prog_blob), // prog_blob size
+ STM32F401RE_flash_prog_blob, // address of prog_blob
+ 0x00000400 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f401re/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f401re/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x08000000,
+ .flash_regions[0].end = 0x08080000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20018000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f407/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f407/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,71 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the stm32f407
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+
+static const uint32_t STM32F407_FLM[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+
+ /*0x020*/ 0xe000300, 0xd3022820L, 0x1d000940, 0x28104770, 0x900d302, 0x47701cc0, 0x47700880, 0x49414842,
+ /*0x040*/ 0x49426041, 0x21006041, 0x68c16001, 0x431122f0, 0x694060c1, 0xd4060680L, 0x493d483e, 0x21066001,
+ /*0x060*/ 0x493d6041, 0x20006081, 0x48374770, 0x5426901, 0x61014311, 0x47702000, 0x4833b510, 0x24046901,
+ /*0x080*/ 0x61014321, 0x3a26901, 0x61014311, 0x4a314933, 0x6011e000, 0x3db68c3, 0x6901d4fb, 0x610143a1,
+ /*0x0A0*/ 0xbd102000L, 0xf7ffb530L, 0x4927ffbb, 0x23f068ca, 0x60ca431a, 0x610c2402, 0x700690a, 0x43020e40,
+ /*0x0C0*/ 0x6908610a, 0x431003e2, 0x48246108, 0xe0004a21L, 0x68cd6010, 0xd4fb03edL, 0x43a06908, 0x68c86108,
+ /*0x0E0*/ 0xf000600, 0x68c8d003, 0x60c84318, 0xbd302001L, 0x4d15b570, 0x8891cc9, 0x8968eb, 0x433326f0,
+ /*0x100*/ 0x230060eb, 0x4b16612b, 0x692ce017, 0x612c431c, 0x60046814, 0x3e468ec, 0x692cd4fc, 0x640864,
+ /*0x120*/ 0x68ec612c, 0xf240624, 0x68e8d004, 0x60e84330, 0xbd702001L, 0x1d121d00, 0x29001f09, 0x2000d1e5,
+ /*0x140*/ 0xbd70, 0x45670123, 0x40023c00, 0xcdef89abL, 0x5555, 0x40003000, 0xfff, 0xaaaa,
+ /*0x160*/ 0x201, 0x0,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x08000000, 1024},
+};
+
+static const program_target_t flash = {
+ 0x2000003D, // Init
+ 0x2000006B, // UnInit
+ 0x20000079, // EraseChip
+ 0x200000A5, // EraseSector
+ 0x200000F1, // ProgramPage
+ 0x0, // Verify
+
+// RSB : base adreess is address of Execution Region PrgData in map file
+// to access global/static data
+// RSP : Initial stack pointer
+
+ {0x20000001, 0x20000020 + 0x00000144, 0x20002000}, // {breakpoint, RSB, RSP}
+
+ 0x20001000, // program_buffer
+ 0x20000000, // algo_start
+ 0x00000170, // algo_size
+ STM32F407_FLM,// image
+ 512 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f407/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f407/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the stm32f407
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x08000000,
+ .flash_regions[0].end = 0x08100000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20020000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f407ve/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f407ve/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,84 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the stm32f407
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t stm32f4xx_512_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0xf3c04601, 0x28203007, 0x2204bf24, 0x1050eb02, 0x2810d205, 0x2203bf26, 0x1010eb02, 0xf4110880,
+ 0xbf181f80, 0x0010f040, 0x486b4770, 0x60014969, 0x6001496a, 0x6801486a, 0x01f0f041, 0x48696001,
+ 0xf0106800, 0xd1080f20, 0xf2454867, 0x60015155, 0x60412106, 0x71fff640, 0x20006081, 0x49634770,
+ 0xf4206808, 0x600a52f8, 0x48616008, 0xf0416801, 0x60014100, 0x47702000, 0xc174f8df, 0x0000f8dc,
+ 0x0004f040, 0x0000f8cc, 0x0000f8dc, 0x3080f440, 0x0000f8cc, 0x0004f1ac, 0xf4116801, 0xbf1c3f80,
+ 0x21aaf64a, 0xd0044a50, 0x68036011, 0x3f80f413, 0xf8dcd1fa, 0xf0200000, 0xf8cc0004, 0x20000000,
+ 0xf3c04770, 0x29203107, 0x2204bf24, 0x1151eb02, 0x2910d205, 0x2203bf26, 0x1111eb02, 0xf4100889,
+ 0xbf181f80, 0x0110f041, 0x6802483d, 0x02f0f042, 0xf1006002, 0x22020c04, 0x2000f8cc, 0x2000f8dc,
+ 0xea0323f8, 0x431101c1, 0x1000f8cc, 0x1000f8dc, 0x3180f441, 0x1000f8cc, 0xf4116801, 0xbf1c3f80,
+ 0x21aaf64a, 0xd0044a30, 0x68036011, 0x3f80f413, 0xf8dcd1fa, 0xf0211000, 0xf8cc0102, 0x68011000,
+ 0x0ff0f011, 0x2000bf04, 0x68014770, 0x01f0f041, 0x20016001, 0x4b224770, 0x1cc9b430, 0xc000f8d3,
+ 0x0103f031, 0x0cf0f04c, 0xc000f8c3, 0x0404f103, 0x0c00f04f, 0xc000f8c4, 0xf240bf18, 0xd0252501,
+ 0xc000f8d4, 0x0c05ea4c, 0xc000f8c4, 0xc000f8d2, 0xc000f8c0, 0xc000f8d3, 0x3f80f41c, 0xf8d4d1fa,
+ 0xf02cc000, 0xf8c40c01, 0xf8d3c000, 0xf01cc000, 0xd0060ff0, 0xf0406818, 0x601800f0, 0x2001bc30,
+ 0x1d004770, 0xf1021f09, 0xd1d90204, 0x2000bc30, 0x00004770, 0x45670123, 0x40023c04, 0xcdef89ab,
+ 0x40023c0c, 0x40023c14, 0x40003000, 0x40023c00, 0x40023c10, 0x00000000
+};
+
+// Start address of flash
+static const uint32_t flash_start = 0x08000000;
+// Size of flash
+static const uint32_t flash_size = 0x00080000;
+
+/**
+* List of start and size for each size of flash sector - even indexes are start, odd are size
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address flash_start + flash_size.
+*/
+static const sector_info_t sectors_info[] = {
+ { 0x08000000, 0x00004000 },
+ { 0x08010000, 0x00010000 },
+ { 0x08020000, 0x00020000 },
+};
+
+static const program_target_t flash = {
+ 0x2000004b, // Init
+ 0x2000007f, // UnInit
+ 0x20000099, // EraseChip
+ 0x200000e3, // EraseSector
+ 0x20000177, // ProgramPage
+ 0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x20000214,
+ 0x20002000
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(stm32f4xx_512_flash_prog_blob), // prog_blob size
+ stm32f4xx_512_flash_prog_blob, // address of prog_blob
+ 0x00000400 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f407ve/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f407ve/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the stm32f407
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x08000000,
+ .flash_regions[0].end = 0x08080000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20020000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f411/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f411/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,72 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the stm32f411
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t output_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x03004601, 0x28200e00, 0x0940d302, 0xe0051d00, 0xd3022810, 0x1cc00900, 0x0880e000, 0xd50102c9,
+ 0x43082110, 0x48424770, 0x60414940, 0x60414941, 0x60012100, 0x22f068c1, 0x60c14311, 0x06806940,
+ 0x483ed406, 0x6001493c, 0x60412106, 0x6081493c, 0x47702000, 0x69014836, 0x43110542, 0x20006101,
+ 0xb5104770, 0x69014832, 0x43212404, 0x69016101, 0x431103a2, 0x49336101, 0xe0004a30, 0x68c36011,
+ 0xd4fb03db, 0x43a16901, 0x20006101, 0xb530bd10, 0xffb6f7ff, 0x68ca4926, 0x431a23f0, 0x240260ca,
+ 0x690a610c, 0x0e0006c0, 0x610a4302, 0x03e26908, 0x61084310, 0x4a214823, 0x6010e000, 0x03ed68cd,
+ 0x6908d4fb, 0x610843a0, 0x060068c8, 0xd0030f00, 0x431868c8, 0x200160c8, 0xb570bd30, 0x1cc94d14,
+ 0x68eb0889, 0x26f00089, 0x60eb4333, 0x612b2300, 0xe0174b15, 0x431c692c, 0x6814612c, 0x68ec6004,
+ 0xd4fc03e4, 0x0864692c, 0x612c0064, 0x062468ec, 0xd0040f24, 0x433068e8, 0x200160e8, 0x1d00bd70,
+ 0x1f091d12, 0xd1e52900, 0xbd702000, 0x45670123, 0x40023c00, 0xcdef89ab, 0x00005555, 0x40003000,
+ 0x00000fff, 0x0000aaaa, 0x00000201, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x08000000, KB(16)},
+};
+
+static const program_target_t flash = {
+ 0x20000047, // Init
+ 0x20000075, // UnInit
+ 0x20000083, // EraseChip
+ 0x200000AF, // EraseSector
+ 0x200000FB, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000000 + 0x00000001,
+ 0x20000000 + 0x00000020 + 0x0000014c,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(output_flash_prog_blob), // prog_blob size
+ output_flash_prog_blob, // address of prog_blob
+ 0x00000200 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f411/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f411/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the stm32f411
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x08000000,
+ .flash_regions[0].end = 0x08000000 + KB(512),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20020000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f412re/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f412re/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,73 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ #include "flash_blob.h"
+
+static const uint32_t _flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x03004601, 0x28200e00, 0x0940d302, 0xe0051d00, 0xd3022810, 0x1cc00900, 0x0880e000, 0xd50102c9,
+ 0x43082110, 0x48424770, 0x60414940, 0x60414941, 0x60012100, 0x22f068c1, 0x60c14311, 0x06806940,
+ 0x483ed406, 0x6001493c, 0x60412106, 0x6081493c, 0x47702000, 0x69014836, 0x43110542, 0x20006101,
+ 0xb5104770, 0x69014832, 0x43212404, 0x69016101, 0x431103a2, 0x49336101, 0xe0004a30, 0x68c36011,
+ 0xd4fb03db, 0x43a16901, 0x20006101, 0xb530bd10, 0xffb6f7ff, 0x68ca4926, 0x431a23f0, 0x240260ca,
+ 0x690a610c, 0x0e0006c0, 0x610a4302, 0x03e26908, 0x61084310, 0x4a214823, 0x6010e000, 0x03ed68cd,
+ 0x6908d4fb, 0x610843a0, 0x060068c8, 0xd0030f00, 0x431868c8, 0x200160c8, 0xb570bd30, 0x1cc94d14,
+ 0x68eb0889, 0x26f00089, 0x60eb4333, 0x612b2300, 0xe0174b15, 0x431c692c, 0x6814612c, 0x68ec6004,
+ 0xd4fc03e4, 0x0864692c, 0x612c0064, 0x062468ec, 0xd0040f24, 0x433068e8, 0x200160e8, 0x1d00bd70,
+ 0x1f091d12, 0xd1e52900, 0xbd702000, 0x45670123, 0x40023c00, 0xcdef89ab, 0x00005555, 0x40003000,
+ 0x00000fff, 0x0000aaaa, 0x00000201, 0x00000000
+};
+
+// Start address of flash
+static const uint32_t flash_start = 0x08000000;
+// Size of flash
+static const uint32_t flash_size = 0x00080000;
+
+/**
+* List of start and size for each size of flash sector - even indexes are start, odd are size
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address flash_start + flash_size.
+*/
+static const sector_info_t sectors_info[] = {
+ { 0x08000000, 0x00004000 },
+ { 0x08010000, 0x00010000 },
+ { 0x08020000, 0x00010000 },
+};
+
+static const program_target_t flash = {
+ 0x20000047, // Init
+ 0x20000075, // UnInit
+ 0x20000083, // EraseChip
+ 0x200000af, // EraseSector
+ 0x200000fb, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x2000016c,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(_flash_prog_blob), // prog_blob size
+ _flash_prog_blob, // address of prog_blob
+ 0x00000400 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f412re/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f412re/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the stm32f412re
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x08000000,
+ .flash_regions[0].end = 0x08080000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20040000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f412rg/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f412rg/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,73 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ #include "flash_blob.h"
+
+static const uint32_t _flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x03004601, 0x28200e00, 0x0940d302, 0xe0051d00, 0xd3022810, 0x1cc00900, 0x0880e000, 0xd50102c9,
+ 0x43082110, 0x48424770, 0x60414940, 0x60414941, 0x60012100, 0x22f068c1, 0x60c14311, 0x06806940,
+ 0x483ed406, 0x6001493c, 0x60412106, 0x6081493c, 0x47702000, 0x69014836, 0x43110542, 0x20006101,
+ 0xb5104770, 0x69014832, 0x43212404, 0x69016101, 0x431103a2, 0x49336101, 0xe0004a30, 0x68c36011,
+ 0xd4fb03db, 0x43a16901, 0x20006101, 0xb530bd10, 0xffb6f7ff, 0x68ca4926, 0x431a23f0, 0x240260ca,
+ 0x690a610c, 0x0e0006c0, 0x610a4302, 0x03e26908, 0x61084310, 0x4a214823, 0x6010e000, 0x03ed68cd,
+ 0x6908d4fb, 0x610843a0, 0x060068c8, 0xd0030f00, 0x431868c8, 0x200160c8, 0xb570bd30, 0x1cc94d14,
+ 0x68eb0889, 0x26f00089, 0x60eb4333, 0x612b2300, 0xe0174b15, 0x431c692c, 0x6814612c, 0x68ec6004,
+ 0xd4fc03e4, 0x0864692c, 0x612c0064, 0x062468ec, 0xd0040f24, 0x433068e8, 0x200160e8, 0x1d00bd70,
+ 0x1f091d12, 0xd1e52900, 0xbd702000, 0x45670123, 0x40023c00, 0xcdef89ab, 0x00005555, 0x40003000,
+ 0x00000fff, 0x0000aaaa, 0x00000201, 0x00000000
+};
+
+// Start address of flash
+static const uint32_t flash_start = 0x08000000;
+// Size of flash
+static const uint32_t flash_size = 0x00080000;
+
+/**
+* List of start and size for each size of flash sector - even indexes are start, odd are size
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address flash_start + flash_size.
+*/
+static const sector_info_t sectors_info[] = {
+ { 0x08000000, 0x00004000 },
+ { 0x08010000, 0x00010000 },
+ { 0x08020000, 0x00020000 },
+};
+
+static const program_target_t flash = {
+ 0x20000047, // Init
+ 0x20000075, // UnInit
+ 0x20000083, // EraseChip
+ 0x200000af, // EraseSector
+ 0x200000fb, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x2000016c,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(_flash_prog_blob), // prog_blob size
+ _flash_prog_blob, // address of prog_blob
+ 0x00000400 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f412rg/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f412rg/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the stm32f412rg
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x08000000,
+ .flash_regions[0].end = 0x08100000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20040000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f429zi/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f429zi/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,67 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t STM32F429ZI_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x03004601, 0x28200e00, 0x0940d302, 0xe0051d00, 0xd3022810, 0x1cc00900, 0x0880e000, 0xd50102c9,
+ 0x43082110, 0x48464770, 0x60414944, 0x60414945, 0x60012100, 0x22f068c1, 0x60c14311, 0x06806940,
+ 0x4842d406, 0x60014940, 0x60412106, 0x60814940, 0x47702000, 0x6901483a, 0x43110542, 0x20006101,
+ 0xb5304770, 0x69014836, 0x43212404, 0x69016101, 0x43290365, 0x69016101, 0x431103a2, 0x49356101,
+ 0xe0004a32, 0x68c36011, 0xd4fb03db, 0x43a16901, 0x69016101, 0x610143a9, 0xbd302000, 0xf7ffb530,
+ 0x4927ffaf, 0x23f068ca, 0x60ca431a, 0x610c2402, 0x06c0690a, 0x43020e00, 0x6908610a, 0x431003e2,
+ 0x48246108, 0xe0004a21, 0x68cd6010, 0xd4fb03ed, 0x43a06908, 0x68c86108, 0x0f000600, 0x68c8d003,
+ 0x60c84318, 0xbd302001, 0x4d15b570, 0x08891cc9, 0x008968eb, 0x433326f0, 0x230060eb, 0x4b16612b,
+ 0x692ce017, 0x612c431c, 0x60046814, 0x03e468ec, 0x692cd4fc, 0x00640864, 0x68ec612c, 0x0f240624,
+ 0x68e8d004, 0x60e84330, 0xbd702001, 0x1d121d00, 0x29001f09, 0x2000d1e5, 0x0000bd70, 0x45670123,
+ 0x40023c00, 0xcdef89ab, 0x00005555, 0x40003000, 0x00000fff, 0x0000aaaa, 0x00000201, 0x00000000
+};
+
+/**
+ * @brief List of start and size for each size of flash sector.
+ *
+ * Even indexes are start, odd are size. The size will apply to all sectors between the listed
+ * address and the next address in the list. The last pair in the list will have sectors starting
+ * at that address and ending at address flash_start + flash_size.
+*/
+static const sector_info_t sectors_info[] = {
+ { 0x08000000, 0x00004000 }, // 4 x 16KB
+ { 0x08010000, 0x00010000 }, // 1 x 64KB
+ { 0x08020000, 0x00020000 }, // 7 x 128KB
+};
+
+static const program_target_t flash = {
+ 0x20000047, // Init
+ 0x20000075, // UnInit
+ 0x20000083, // EraseChip
+ 0x200000bd, // EraseSector
+ 0x20000109, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x2000017c,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(STM32F429ZI_flash_prog_blob), // prog_blob size
+ STM32F429ZI_flash_prog_blob, // address of prog_blob
+ 0x00000400 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f429zi/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f429zi/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x08000000,
+ .flash_regions[0].end = 0x08200000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20030000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f437vg/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f437vg/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,65 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t STM32F437VG_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x0e000300, 0xd3022820, 0x1d000940, 0x28104770, 0x0900d302, 0x47701cc0, 0x47700880, 0x49414842,
+ 0x49426041, 0x21006041, 0x68c16001, 0x431122f0, 0x694060c1, 0xd4060680, 0x493d483e, 0x21066001,
+ 0x493d6041, 0x20006081, 0x48374770, 0x05426901, 0x61014311, 0x47702000, 0x4833b510, 0x24046901,
+ 0x61014321, 0x03a26901, 0x61014311, 0x4a314933, 0x6011e000, 0x03db68c3, 0x6901d4fb, 0x610143a1,
+ 0xbd102000, 0xf7ffb530, 0x4927ffbb, 0x23f068ca, 0x60ca431a, 0x610c2402, 0x0700690a, 0x43020e40,
+ 0x6908610a, 0x431003e2, 0x48246108, 0xe0004a21, 0x68cd6010, 0xd4fb03ed, 0x43a06908, 0x68c86108,
+ 0x0f000600, 0x68c8d003, 0x60c84318, 0xbd302001, 0x4d15b570, 0x08891cc9, 0x008968eb, 0x433326f0,
+ 0x230060eb, 0x4b16612b, 0x692ce017, 0x612c431c, 0x60046814, 0x03e468ec, 0x692cd4fc, 0x00640864,
+ 0x68ec612c, 0x0f240624, 0x68e8d004, 0x60e84330, 0xbd702001, 0x1d121d00, 0x29001f09, 0x2000d1e5,
+ 0x0000bd70, 0x45670123, 0x40023c00, 0xcdef89ab, 0x00005555, 0x40003000, 0x00000fff, 0x0000aaaa,
+ 0x00000201, 0x00000000
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x08000000, 0x4000},
+};
+
+static const program_target_t flash = {
+ 0x2000003d, // Init
+ 0x2000006b, // UnInit
+ 0x20000079, // EraseChip
+ 0x200000a5, // EraseSector
+ 0x200000f1, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x20000164,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(STM32F437VG_flash_prog_blob), // prog_blob size
+ STM32F437VG_flash_prog_blob, // address of prog_blob
+ 0x00000400 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f437vg/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f437vg/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x08000000,
+ .flash_regions[0].end = 0x08100000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20030000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f439zi/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f439zi/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,70 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t STM32F439ZI_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x03004601, 0x28200e00, 0x0940d302, 0xe0051d00, 0xd3022810, 0x1cc00900, 0x0880e000, 0xd50102c9,
+ 0x43082110, 0x48464770, 0x60414944, 0x60414945, 0x60012100, 0x22f068c1, 0x60c14311, 0x06806940,
+ 0x4842d406, 0x60014940, 0x60412106, 0x60814940, 0x47702000, 0x6901483a, 0x43110542, 0x20006101,
+ 0xb5304770, 0x69014836, 0x43212404, 0x69016101, 0x43290365, 0x69016101, 0x431103a2, 0x49356101,
+ 0xe0004a32, 0x68c36011, 0xd4fb03db, 0x43a16901, 0x69016101, 0x610143a9, 0xbd302000, 0xf7ffb530,
+ 0x4927ffaf, 0x23f068ca, 0x60ca431a, 0x610c2402, 0x06c0690a, 0x43020e00, 0x6908610a, 0x431003e2,
+ 0x48246108, 0xe0004a21, 0x68cd6010, 0xd4fb03ed, 0x43a06908, 0x68c86108, 0x0f000600, 0x68c8d003,
+ 0x60c84318, 0xbd302001, 0x4d15b570, 0x08891cc9, 0x008968eb, 0x433326f0, 0x230060eb, 0x4b16612b,
+ 0x692ce017, 0x612c431c, 0x60046814, 0x03e468ec, 0x692cd4fc, 0x00640864, 0x68ec612c, 0x0f240624,
+ 0x68e8d004, 0x60e84330, 0xbd702001, 0x1d121d00, 0x29001f09, 0x2000d1e5, 0x0000bd70, 0x45670123,
+ 0x40023c00, 0xcdef89ab, 0x00005555, 0x40003000, 0x00000fff, 0x0000aaaa, 0x00000201, 0x00000000
+};
+
+/**
+ * @brief List of start and size for each size of flash sector.
+ *
+ * Even indexes are start, odd are size. The size will apply to all sectors between the listed
+ * address and the next address in the list. The last pair in the list will have sectors starting
+ * at that address and ending at address flash_start + flash_size.
+*/
+static const sector_info_t sectors_info[] = {
+ { 0x08000000, 0x00004000 }, // 4 x 16KB
+ { 0x08010000, 0x00010000 }, // 1 x 64KB
+ { 0x08020000, 0x00020000 }, // 7 x 128KB
+ { 0x08100000, 0x00004000 },
+ { 0x08110000, 0x00010000 },
+ { 0x08120000, 0x00020000 },
+};
+
+static const program_target_t flash = {
+ 0x20000047, // Init
+ 0x20000075, // UnInit
+ 0x20000083, // EraseChip
+ 0x200000bd, // EraseSector
+ 0x20000109, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x2000017c,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(STM32F439ZI_flash_prog_blob), // prog_blob size
+ STM32F439ZI_flash_prog_blob, // address of prog_blob
+ 0x00000400 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f439zi/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f439zi/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x08000000,
+ .flash_regions[0].end = 0x08200000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20030000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f746zg/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f746zg/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,65 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t STM32F746ZG_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x8f4ff3bf, 0x03004770, 0x28400e00, 0x0980d302, 0x47701d00, 0x477008c0, 0x49474848, 0x49486041,
+ 0x21006041, 0x68c16001, 0x431122f0, 0x694060c1, 0xd4060680, 0x49434844, 0x21066001, 0x49436041,
+ 0x20006081, 0x483d4770, 0x05426901, 0x61014311, 0x47702000, 0x4839b510, 0x24046901, 0x61014321,
+ 0x03a26901, 0x61014311, 0x4a374939, 0x6011e000, 0x03db68c3, 0x6901d4fb, 0x610143a1, 0xbd102000,
+ 0xf7ffb530, 0x492dffc0, 0x23f068ca, 0x60ca431a, 0x610c2402, 0x0700690a, 0x43020e40, 0x6908610a,
+ 0x431003e2, 0x482a6108, 0xe0004a27, 0x68cd6010, 0xd4fb03ed, 0x43a06908, 0x68c86108, 0x0f000600,
+ 0x68c8d003, 0x60c84318, 0xbd302001, 0x4c1bb5f0, 0x08891cc9, 0x008968e5, 0x431d23f0, 0x230060e5,
+ 0x27016123, 0x4d1a06ff, 0x6923e021, 0x43334e19, 0x03066123, 0x19f60b36, 0x60336813, 0x8f4ff3bf,
+ 0xe0004e11, 0x68e36035, 0xd4fb03db, 0x085b6923, 0x6123005b, 0x061b68e3, 0xd0050f1b, 0x21f068e0,
+ 0x60e04308, 0xbdf02001, 0x1f091d00, 0x29001d12, 0x2000d1db, 0x0000bdf0, 0x45670123, 0x40023c00,
+ 0xcdef89ab, 0x00005555, 0x40003000, 0x00000fff, 0x0000aaaa, 0x00000201, 0x00000000
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x08000000, 0x8000},
+};
+
+static const program_target_t flash = {
+ 0x20000039, // Init
+ 0x20000067, // UnInit
+ 0x20000075, // EraseChip
+ 0x200000a1, // EraseSector
+ 0x200000ed, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x20000178,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(STM32F746ZG_flash_prog_blob), // prog_blob size
+ STM32F746ZG_flash_prog_blob, // address of prog_blob
+ 0x00000400 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32f746zg/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32f746zg/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x08000000,
+ .flash_regions[0].end = 0x08100000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20000000 + 0x50000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32l082cz/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32l082cz/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,73 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+
+static const uint32_t stm32l0xx_192_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x4603b510, 0x69804851, 0x0224240f, 0x4c4f4320, 0x484f61a0, 0x484f60e0, 0x484f60e0, 0x484f6120,
+ 0x46206120, 0x240169c0, 0x40200524, 0xd1062800, 0x4c4c484b, 0x20066020, 0x484b6060, 0x200060a0,
+ 0x4601bd10, 0x68404841, 0x43102202, 0x60504a3f, 0x68404610, 0x43102201, 0x60504a3c, 0x47702000,
+ 0x483a4601, 0x22016840, 0x43100252, 0x60504a37, 0x68404610, 0x43102208, 0x60504a34, 0x60082000,
+ 0x483ae002, 0x60104a37, 0x69804830, 0x0fc007c0, 0xd1f62800, 0x6840482d, 0x02522201, 0x4a2b4390,
+ 0x46106050, 0x22086840, 0x4a284390, 0x20006050, 0x46034770, 0x47702001, 0x4603b570, 0x303f4608,
+ 0x01890981, 0xe03b2500, 0x68404820, 0x02b62601, 0x4e1e4330, 0x46306070, 0x26086840, 0x4e1b4330,
+ 0x24406070, 0x6810e004, 0x1d1b6018, 0x1f241d12, 0xd1f82c00, 0x481de002, 0x60304e1a, 0x69804813,
+ 0x0fc007c0, 0xd1f62800, 0x69804810, 0x0236260f, 0x28004030, 0x480dd006, 0x43306980, 0x61b04e0b,
+ 0xbd702001, 0x68404809, 0x02b62601, 0x4e0743b0, 0x46306070, 0x26086840, 0x4e0443b0, 0x1c6d6070,
+ 0x42a80988, 0x2000d8c0, 0x0000e7eb, 0x40022000, 0x89abcdef, 0x02030405, 0x8c9daebf, 0x13141516,
+ 0x00005555, 0x40003000, 0x00000fff, 0x0000aaaa, 0x00000000
+};
+
+// Start address of flash
+static const uint32_t flash_start = 0x08000000;
+// Size of flash
+static const uint32_t flash_size = 0x00030000;
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x08000000, 0x00000080},
+};
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000063, // UnInit
+ 0x00000000, // EraseChip - NOT SUPPORTED
+ 0x20000081, // EraseSector
+ 0x200000d9, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x20000190,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(stm32l0xx_192_flash_prog_blob), // prog_blob size
+ stm32l0xx_192_flash_prog_blob, // address of prog_blob
+ 0x00000080 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32l082cz/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32l082cz/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the stm32l082cz
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x08000000,
+ .flash_regions[0].end = 0x08030000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20005000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32l151cbxxa/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32l151cbxxa/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,75 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t stm32l1xx_128_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x4603b510, 0x6980486e, 0x0224240f, 0x4c6c4320, 0x486c61a0, 0x486c60e0, 0x486c60e0, 0x486c6120,
+ 0x46206120, 0x240169c0, 0x40200524, 0xd1062800, 0x4c694868, 0x20066020, 0x48686060, 0x200060a0,
+ 0x4601bd10, 0x6840485e, 0x43102202, 0x60504a5c, 0x68404610, 0x43102201, 0x60504a59, 0x47702000,
+ 0x48574601, 0x22016840, 0x43100252, 0x60504a54, 0x68404610, 0x43102208, 0x60504a51, 0x60082000,
+ 0x4857e002, 0x60104a54, 0x6980484d, 0x0fc007c0, 0xd1f62800, 0x6840484a, 0x02522201, 0x4a484390,
+ 0x46106050, 0x22086840, 0x4a454390, 0x20006050, 0x46034770, 0x47702001, 0x4603b530, 0x1dc82480,
+ 0x0a0130f8, 0x483e0209, 0x00e56840, 0x4d3c4328, 0x46286068, 0x25086840, 0x4d394328, 0xbf006068,
+ 0x6810e005, 0x1d1b6018, 0x1f091d12, 0x29001f24, 0x2c00d001, 0xe002d1f5, 0x4d374839, 0x48306028,
+ 0x07c06980, 0x28000fc0, 0x482dd1f6, 0x250f6980, 0x4028022d, 0xd0062800, 0x69804829, 0x4d284328,
+ 0x200161a8, 0x4826bd30, 0x25016840, 0x43a802ad, 0x60684d23, 0x68404628, 0x43a82508, 0x60684d20,
+ 0x68404628, 0x4328152d, 0x60684d1d, 0x68404628, 0x43282508, 0x60684d1a, 0xe0052480, 0x60186810,
+ 0x1d121d1b, 0x1f241f09, 0xd0012900, 0xd1f52c00, 0x481be002, 0x60284d18, 0x69804811, 0x0fc007c0,
+ 0xd1f62800, 0x6980480e, 0x022d250f, 0x28004028, 0x480bd006, 0x43286980, 0x61a84d09, 0xe7c12001,
+ 0x68404807, 0x02ad2501, 0x4d0543a8, 0x46286068, 0x25086840, 0x4d0243a8, 0x20006068, 0x0000e7b2,
+ 0x40023c00, 0x89abcdef, 0x02030405, 0x8c9daebf, 0x13141516, 0x00005555, 0x40003000, 0x00000fff,
+ 0x0000aaaa, 0x00000000
+};
+
+// Start address of flash
+static const uint32_t flash_start = 0x08000000;
+// Size of flash
+static const uint32_t flash_size = 0x00020000;
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x08000000, 0x00000100},
+};
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000063, // UnInit
+ 0xffffffff, // EraseChip - NOT SUPPORTED
+ 0x20000081, // EraseSector
+ 0x200000d9, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x20000204,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(stm32l1xx_128_flash_prog_blob), // prog_blob size
+ stm32l1xx_128_flash_prog_blob, // address of prog_blob
+ 0x00000100 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32l151cbxxa/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32l151cbxxa/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the stm32l151cbxxa
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2018-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x08000000,
+ .flash_regions[0].end = 0x08000000 + KB(128),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20000000 + KB(32),
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32l443rc/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32l443rc/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,73 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ #include "flash_blob.h"
+
+static const uint32_t _flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x8f4ff3bf, 0x48584770, 0x49586800, 0x0d000500, 0xd0001840, 0x47702001, 0x6a004855, 0x0fc00280,
+ 0xb5004770, 0xf7ff4602, 0x2801ffee, 0xf7ffd108, 0x2801fff3, 0x484fd104, 0xd3014282, 0xbd002001,
+ 0xbd002000, 0x4602b500, 0xffddf7ff, 0xd0022801, 0x0d8002d0, 0x4948bd00, 0x40080ad0, 0xd5f90391,
+ 0x300130ff, 0x4842bd00, 0x60814944, 0x60814944, 0x60012100, 0x61014943, 0x03c06a00, 0x4843d406,
+ 0x60014941, 0x60412106, 0x60814941, 0x47702000, 0x49372001, 0x614807c0, 0x47702000, 0x47702001,
+ 0x49384833, 0x13c16101, 0x69416141, 0x04122201, 0x61414311, 0x4a354937, 0x6011e000, 0x03db6903,
+ 0x2100d4fb, 0x46086141, 0xb5104770, 0xf7ff4604, 0x4603ffa8, 0xf7ff4620, 0x4925ffb5, 0x610c4c29,
+ 0x02d800c2, 0x43021c92, 0x6948614a, 0x04122201, 0x61484310, 0x8f4ff3bf, 0x4a244826, 0x6010e000,
+ 0x03db690b, 0x2000d4fb, 0x69086148, 0xd0014020, 0x2001610c, 0xb5f0bd10, 0x4d151dc9, 0x4f1908c9,
+ 0x612f00c9, 0x616b2300, 0xe0184c1a, 0x616b2301, 0x60036813, 0x60436853, 0x8f4ff3bf, 0xe0004b13,
+ 0x692e601c, 0xd4fb03f6, 0x616b2300, 0x423b692b, 0x612fd002, 0xbdf02001, 0x39083008, 0x29003208,
+ 0x2000d1e4, 0x0000bdf0, 0xe0042000, 0xfffffbcb, 0x40022000, 0x08020000, 0x000003bf, 0x45670123,
+ 0xcdef89ab, 0x0000c3fa, 0x00005555, 0x40003000, 0x00000fff, 0x0000aaaa, 0x00000000
+};
+
+// Start address of flash
+static const uint32_t flash_start = 0x08000000;
+// Size of flash
+static const uint32_t flash_size = 0x00040000;
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x08000000, 0x00000800},
+};
+
+static const program_target_t flash = {
+ 0x20000087, // Init
+ 0x200000b1, // UnInit
+ 0x200000c1, // EraseChip
+ 0x200000eb, // EraseSector
+ 0x20000137, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x200001b8,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(_flash_prog_blob), // prog_blob size
+ _flash_prog_blob, // address of prog_blob
+ 0x00000400 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32l443rc/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32l443rc/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the stm32l443rc
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x08000000,
+ .flash_regions[0].end = 0x08040000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x2000c000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32l476rg/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32l476rg/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,66 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t STM32L476RG_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x6a094953, 0xd5040289, 0x42884952, 0x2001d301, 0x20004770, 0x484e4770, 0x6081494f, 0x6081494f,
+ 0x60012100, 0x31faf244, 0x6a006101, 0xd40803c0, 0xf245484b, 0x60015155, 0x60412106, 0x71fff640,
+ 0x20006081, 0x48424770, 0xf0416941, 0x61414100, 0x47702000, 0x47702001, 0xf64ab510, 0x494022aa,
+ 0xe000483b, 0x6903600a, 0xd4fb03db, 0x34faf244, 0xf2486104, 0x61430304, 0xf4436943, 0x61433380,
+ 0x600ae000, 0x03db6903, 0x2100d4fb, 0x69016141, 0xd0024221, 0x20016104, 0x2000bd10, 0xb570bd10,
+ 0xf7ff4602, 0xf3c2ffad, 0xf64a25c7, 0x4a2c23aa, 0xe0004927, 0x690c6013, 0xd4fb03e4, 0x34faf244,
+ 0x2602610c, 0x05c5eb06, 0x20c0ea45, 0x69486148, 0x3080f440, 0xe0006148, 0x69086013, 0xd4fb03c0,
+ 0x61482000, 0x40206908, 0x610cd001, 0xbd702001, 0x1dc9b5f0, 0x0107f021, 0x25aaf64a, 0x4c144e18,
+ 0x6035e000, 0x03db6923, 0xf244d4fb, 0x612737fa, 0x0e01f04f, 0x0c00f04f, 0xf8c4e015, 0x6813e014,
+ 0x68536003, 0xe0006043, 0x69236035, 0xd4fb03db, 0xc014f8c4, 0x423b6923, 0x6127d002, 0xbdf02001,
+ 0x39083008, 0x29003208, 0x2000d1e7, 0x0000bdf0, 0x40022000, 0x08080000, 0x45670123, 0xcdef89ab,
+ 0x40003000, 0x00000000
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x08000000, 0x800},
+};
+
+static const program_target_t flash = {
+ 0x20000037, // Init
+ 0x20000067, // UnInit
+ 0x20000079, // EraseChip
+ 0x200000bf, // EraseSector
+ 0x20000111, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x20000184,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(STM32L476RG_flash_prog_blob), // prog_blob size
+ STM32L476RG_flash_prog_blob, // address of prog_blob
+ 0x00000400 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32l476rg/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32l476rg/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x08000000,
+ .flash_regions[0].end = 0x08100000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20018000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32l486jg/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32l486jg/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,73 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ #include "flash_blob.h"
+
+static const uint32_t _flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x8f4ff3bf, 0x48584770, 0x49586800, 0x0d000500, 0xd0001840, 0x47702001, 0x6a004855, 0x0fc00280,
+ 0xb5004770, 0xf7ff4602, 0x2801ffee, 0xf7ffd108, 0x2801fff3, 0x484fd104, 0xd3014282, 0xbd002001,
+ 0xbd002000, 0x4602b500, 0xffddf7ff, 0xd0022801, 0x0d8002d0, 0x4948bd00, 0x40080ad0, 0xd5f90311,
+ 0x300130ff, 0x4842bd00, 0x60814944, 0x60814944, 0x60012100, 0x61014943, 0x03c06a00, 0x4843d406,
+ 0x60014941, 0x60412106, 0x60814941, 0x47702000, 0x49372001, 0x614807c0, 0x47702000, 0x47702001,
+ 0x49384833, 0x13c16101, 0x69416141, 0x04122201, 0x61414311, 0x4a354937, 0x6011e000, 0x03db6903,
+ 0x2100d4fb, 0x46086141, 0xb5104770, 0xf7ff4604, 0x4603ffa8, 0xf7ff4620, 0x4925ffb5, 0x610c4c29,
+ 0x02d800c2, 0x43021c92, 0x6948614a, 0x04122201, 0x61484310, 0x8f4ff3bf, 0x4a244826, 0x6010e000,
+ 0x03db690b, 0x2000d4fb, 0x69086148, 0xd0014020, 0x2001610c, 0xb5f0bd10, 0x4d151dc9, 0x4f1908c9,
+ 0x612f00c9, 0x616b2300, 0xe0184c1a, 0x616b2301, 0x60036813, 0x60436853, 0x8f4ff3bf, 0xe0004b13,
+ 0x692e601c, 0xd4fb03f6, 0x616b2300, 0x423b692b, 0x612fd002, 0xbdf02001, 0x39083008, 0x29003208,
+ 0x2000d1e4, 0x0000bdf0, 0xe0042000, 0xfffffbcb, 0x40022000, 0x08080000, 0x000002ff, 0x45670123,
+ 0xcdef89ab, 0x0000c3fa, 0x00005555, 0x40003000, 0x00000fff, 0x0000aaaa, 0x00000000
+};
+
+// Start address of flash
+static const uint32_t flash_start = 0x08000000;
+// Size of flash
+static const uint32_t flash_size = 0x00100000;
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x08000000, 0x00000800},
+};
+
+static const program_target_t flash = {
+ 0x20000087, // Init
+ 0x200000b1, // UnInit
+ 0x200000c1, // EraseChip
+ 0x200000eb, // EraseSector
+ 0x20000137, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x200001b8,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(_flash_prog_blob), // prog_blob size
+ _flash_prog_blob, // address of prog_blob
+ 0x00000400 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32l486jg/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32l486jg/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the stm32l486jg
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x08000000,
+ .flash_regions[0].end = 0x08100000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20018000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32l4xx_1024/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32l4xx_1024/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,72 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t STM32L4xx_1024_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x8f4ff3bf, 0x48584770, 0x49586800, 0x0d000500, 0xd0001840, 0x47702001, 0x6a004855, 0x0fc00280,
+ 0xb5004770, 0xf7ff4602, 0x2801ffee, 0xf7ffd108, 0x2801fff3, 0x484fd104, 0xd3014282, 0xbd002001,
+ 0xbd002000, 0x4602b500, 0xffddf7ff, 0xd0022801, 0x0d8002d0, 0x4948bd00, 0x40080ad0, 0xd5f90311,
+ 0x300130ff, 0x4842bd00, 0x60814944, 0x60814944, 0x60012100, 0x61014943, 0x03c06a00, 0x4843d406,
+ 0x60014941, 0x60412106, 0x60814941, 0x47702000, 0x49372001, 0x614807c0, 0x47702000, 0x47702001,
+ 0x49384833, 0x13c16101, 0x69416141, 0x04122201, 0x61414311, 0x4a354937, 0x6011e000, 0x03db6903,
+ 0x2100d4fb, 0x46086141, 0xb5104770, 0xf7ff4604, 0x4603ffa8, 0xf7ff4620, 0x4925ffb5, 0x610c4c29,
+ 0x02d800c2, 0x43021c92, 0x6948614a, 0x04122201, 0x61484310, 0x8f4ff3bf, 0x4a244826, 0x6010e000,
+ 0x03db690b, 0x2000d4fb, 0x69086148, 0xd0014020, 0x2001610c, 0xb5f0bd10, 0x4d151dc9, 0x4f1908c9,
+ 0x612f00c9, 0x616b2300, 0xe0184c1a, 0x616b2301, 0x60036813, 0x60436853, 0x8f4ff3bf, 0xe0004b13,
+ 0x692e601c, 0xd4fb03f6, 0x616b2300, 0x423b692b, 0x612fd002, 0xbdf02001, 0x39083008, 0x29003208,
+ 0x2000d1e4, 0x0000bdf0, 0xe0042000, 0xfffffbcb, 0x40022000, 0x08080000, 0x000002ff, 0x45670123,
+ 0xcdef89ab, 0x0000c3fa, 0x00005555, 0x40003000, 0x00000fff, 0x0000aaaa, 0x00000000
+};
+
+// Start address of flash
+static const uint32_t flash_start = 0x08000000;
+// Size of flash
+static const uint32_t flash_size = 0x00100000;
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x08000000, 0x00000800},
+};
+
+static const program_target_t flash = {
+ 0x20000087, // Init
+ 0x200000b1, // UnInit
+ 0x200000c1, // EraseChip
+ 0x200000eb, // EraseSector
+ 0x20000137, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x200001b8,
+ 0x20000400
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(STM32L4xx_1024_flash_prog_blob), // prog_blob size
+ STM32L4xx_1024_flash_prog_blob, // address of prog_blob
+ 0x00000400 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/stm32l4xx_1024/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/stm32l4xx_1024/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,39 @@
+/**
+ * @file target.c
+ * @brief Target information for the stm32l486jg
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device_stm32l475 = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x08000000,
+ .flash_regions[0].end = 0x08100000,
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20000000 + 0x00018000,
+ .ram_regions[1].start = 0x10000188,
+ .ram_regions[1].end = 0x10008000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/xDot-L151/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/xDot-L151/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,74 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t stm32l151_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0xbf182a01, 0xd1042a02, 0x6801488e, 0x6170f441, 0x20006001, 0x28014770, 0x2802bf18, 0x488ad108,
+ 0xf0416801, 0x60010102, 0xf0416801, 0x60010101, 0x47702000, 0x68114a84, 0x0f01f011, 0x4984d004,
+ 0x600b4b82, 0x600b4b83, 0xf0116811, 0xd0040f02, 0x4b814982, 0x4b82600b, 0x6811600b, 0x7100f441,
+ 0x68116011, 0x0108f041, 0x21006011, 0x49756001, 0xf0106808, 0xd1fb0f01, 0xf4106808, 0xd0056f70,
+ 0x680a6808, 0x6270f442, 0x4770600a, 0xf4206810, 0x60107000, 0xf0206810, 0x60100008, 0x47702000,
+ 0x4df0e92d, 0xc1a8f8df, 0x4e6a4d68, 0xf8df4f6a, 0x4a6481b0, 0xf8df4b64, 0xf04fe1ac, 0xf10c6100,
+ 0xf04f0404, 0x68180a00, 0x0f01f010, 0xf8ccbf1c, 0xf8cc5000, 0x68186000, 0x0f02f010, 0x6027bf1c,
+ 0x8000f8c4, 0xf4406818, 0x60187000, 0xf0406818, 0x60180008, 0xa000f8c1, 0xf0106810, 0xd1fb0f01,
+ 0xf4106810, 0xd0076f70, 0xf8d26810, 0xf44bb000, 0xf8c26b70, 0xe008b000, 0xf4206818, 0x60187000,
+ 0xf0206818, 0x60180008, 0x28002000, 0xe8bdbf18, 0xf5018df0, 0x45717180, 0x2000d3c5, 0x8df0e8bd,
+ 0x47702001, 0x4df0e92d, 0x68294d3f, 0x80fcf8df, 0xf8df4e3f, 0xf011a100, 0xbf1c0f01, 0x8000f8c6,
+ 0xa000f8c6, 0xf8df6829, 0x4f3cb0f0, 0xe0f0f8df, 0x0f02f011, 0xf8c7bf1c, 0xf8c7b000, 0x6829e000,
+ 0x0f01f011, 0x6829bf04, 0x0f02f011, 0x2001d002, 0x8df0e8bd, 0xf4416829, 0x60296180, 0xf0416829,
+ 0x60290108, 0x68214c27, 0x0f01f011, 0x2100d1fb, 0xf852460b, 0xf840c023, 0x1d09c001, 0x29801c5b,
+ 0x6821dbf7, 0x6f70f411, 0x6829d134, 0x0f01f011, 0xf8c6bf1c, 0xf8c68000, 0x6829a000, 0x0f02f011,
+ 0xf8c7bf1c, 0xf8c7b000, 0x6829e000, 0x0f01f011, 0x6829bf04, 0x0f02f011, 0x6829d1c9, 0x6180f441,
+ 0x68296029, 0x0108f041, 0x68216029, 0x0f01f011, 0x2180d1fb, 0xf8522320, 0xf840c023, 0x1d09c001,
+ 0xf5b11c5b, 0xdbf67f80, 0xf4106820, 0xbf086070, 0x8df0e8bd, 0x68216820, 0x6170f441, 0xe8bd6021,
+ 0x00008df0, 0x40023c18, 0x40023c04, 0x89abcdef, 0x40023c0c, 0x02030405, 0x8c9daebf, 0x40023c10,
+ 0x13141516, 0x08040000, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x08000000, 256},
+};
+
+static const program_target_t flash = {
+ 0x20000021, // Init
+ 0x20000037, // UnInit
+ 0x200000C1, // EraseChip
+ 0x20000055, // EraseSector
+ 0x20000165, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000000 + 0x00000001,
+ 0x20000000 + 0x00000020 + 0x00000268,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(stm32l151_flash_prog_blob), // prog_blob size
+ stm32l151_flash_prog_blob, // address of prog_blob
+ 0x00000200 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/st/xDot-L151/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/st/xDot-L151/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the stm32l151
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x08000000,
+ .flash_regions[0].end = 0x08000000 + KB(256),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20000000 + KB(32),
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/ti/cc3220sf/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/ti/cc3220sf/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,86 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t cc3220sf_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0xd1fd3801, 0x49964770, 0x6e48b418, 0x0000f440, 0x4b946648, 0xf241681a, 0x380140d5, 0xf042d1fd,
+ 0x60180010, 0x40d5f241, 0xd1fd3801, 0xf8d24a8e, 0xf040016c, 0xf8c2003c, 0x4b8c016c, 0xf0406c98,
+ 0x64980001, 0x6480f44f, 0x6cd86820, 0x0001f040, 0xf04f64d8, 0xf8cd0c00, 0x9800c000, 0x90001c40,
+ 0xd3fa2810, 0xf0206cd8, 0x64d80001, 0xf0206c98, 0x64980001, 0x68c0487e, 0x0ffff010, 0x487dd106,
+ 0xc000f8c0, 0x40d5f241, 0xd1fd3801, 0x00c8f8d1, 0x2802b2c0, 0xf8d2d113, 0xf0200110, 0xf420000f,
+ 0xf0406040, 0xf8c20002, 0xf8d20110, 0xf0200114, 0xf420000f, 0xf0406040, 0xf8c20002, 0xf8d20114,
+ 0xf0400184, 0xf8c20002, 0x486b0184, 0xf3c06800, 0x280e5083, 0x00b0f8d1, 0x007cf420, 0xf440bf0c,
+ 0xf4400048, 0xf8c10024, 0x486400b0, 0xf0236803, 0x60035380, 0xb2806820, 0xd2062802, 0x00a8f8d1,
+ 0x0004f040, 0x00a8f8c1, 0x6820e022, 0xd01f0c00, 0x0188f8d2, 0x00e1f040, 0x0188f8c2, 0x68034858,
+ 0x0f01f013, 0x6803d014, 0x0301f023, 0xf8d26003, 0xf4400188, 0xf8c27000, 0x48520188, 0xf0226802,
+ 0x60020201, 0xf8c01d00, 0x1d00c000, 0xc000f8c0, 0x6800484d, 0xf3c00f02, 0x2a036003, 0xd22cd00f,
+ 0x6800484a, 0x1080f3c0, 0x6a88b158, 0x0080f020, 0x69086288, 0x4070f020, 0x5080f040, 0xb9e0e01c,
+ 0x6a48e7ee, 0x000ff020, 0x6070f420, 0x30c0f420, 0x0001f040, 0x60a0f440, 0x3080f440, 0x6a886248,
+ 0x0080f020, 0x4070f020, 0x007ff420, 0x104cf440, 0x69086288, 0x4070f020, 0xbc186108, 0x0000f04f,
+ 0x20004770, 0x48324770, 0x2201f640, 0x49316142, 0x68816081, 0x0f04f011, 0x68c0d1fb, 0xbf184010,
+ 0x47702001, 0x2201f640, 0x614a4929, 0x482a6008, 0x68886088, 0x0f02f010, 0x68c8d1fb, 0xbf184010,
+ 0x47702001, 0xf242b430, 0x4b216c01, 0xc014f8c3, 0xbf182900, 0xc084f8df, 0xf020d01e, 0x601c047f,
+ 0xf000e00b, 0xf105057c, 0xf5054580, 0xf852257d, 0xf8c54b04, 0x1d004100, 0xf0101f09, 0xd1010f7c,
+ 0xb90c6b1c, 0xd1ec2900, 0xc020f8c3, 0xf0146a1c, 0xd1fb0f01, 0xd1e02900, 0x2000bc30, 0x00004770,
+ 0x4402f000, 0x4402fc18, 0x4402e000, 0x44025000, 0x4402d000, 0x4402f804, 0x4402dc78, 0x4402fc74,
+ 0x4402fc20, 0x4402f818, 0x4402dc80, 0x4402f840, 0x400fd000, 0xa4420004, 0xa4420002, 0xa4420001,
+ 0x00000004, 0x00000008, 0x00000014, 0x00000018, 0x00000024, 0x00000028, 0x00000030, 0x00000034,
+ 0x00000040, 0x00000044, 0x00000048, 0x0000004c, 0x00000050, 0x00000054, 0x00000058, 0x0000005c,
+ 0x00000060, 0x00000064, 0x00000068, 0x0000006c, 0x00000070, 0x00000074, 0x00000078, 0x0000007c,
+ 0x00000080, 0x00000084, 0x00000088, 0x0000008c, 0x00000090, 0x00000094, 0x00000098, 0x0000009c,
+ 0x000000a0, 0x000000a4, 0x000000a8, 0x000000ac, 0x000000b8, 0x000000bc, 0x000000c8, 0x000000cc,
+ 0x000000d8, 0x000000dc, 0x00000000
+};
+
+// Start address of flash
+static const uint32_t flash_start = 0x01000000;
+// Size of flash
+static const uint32_t flash_size = 0x00100000;
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0x01000000, 2048},
+};
+
+static const program_target_t flash = {
+ 0x20000027, // Init
+ 0x200001e3, // UnInit
+ 0x200001e7, // EraseChip
+ 0x20000205, // EraseSector
+ 0x20000225, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000001,
+ 0x20000368,
+ 0x20000600
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(cc3220sf_flash_prog_blob), // prog_blob size
+ cc3220sf_flash_prog_blob, // address of prog_blob
+ 0x00000400 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/ti/cc3220sf/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/ti/cc3220sf/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the cc3220sf
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x01000000,
+ .flash_regions[0].end = 0x01000000 + MB(1),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20040000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/ti/target_reset_ti.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/ti/target_reset_ti.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,62 @@
+/**
+ * @file target_reset.c
+ * @brief Target reset for the cc3220sf
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "swd_host.h"
+#include "target_family.h"
+
+#define GPRCM_0_APPS_SOFT_RESET_ADDR 0x4402D000
+#define GPRCM_0_RESET_MCU_VALUE 0x1
+#define GPRCM_0_RESET_MCU_PERIPH_VALUE 0x2
+
+static uint8_t target_set_state_ti(target_state_t state)
+{
+ swd_set_soft_reset(VECTRESET);
+ if (state == POST_FLASH_RESET)
+ {
+ // TI recommends reset via writing to PRCM register instead of AIRCR.
+ // Reset apps processor and associated peripheral.
+ uint32_t write_value = GPRCM_0_RESET_MCU_PERIPH_VALUE;
+ swd_write_memory(GPRCM_0_APPS_SOFT_RESET_ADDR, (uint8_t *)&write_value, sizeof(write_value));
+ return 1;
+ }
+ return swd_set_target_state_sw(state);
+}
+
+const uint32_t cookieList[]=
+{
+ 0x5AA5A55A,
+ 0x000FF800,
+ 0xEFA3247D
+};
+
+// Override the weak validate_bin_nvic function. The weak function expects NVIC at the beginning of the flash.
+// On CC3220SF, the beginning of the flash is the cookie list, which allows the boot ROM code to jump into onchip flash directly bypassing external flash.
+static uint8_t validate_bin_nvic_ti(const uint8_t *buf)
+{
+ return (memcmp(buf, cookieList, sizeof(cookieList)) == 0);
+}
+
+const target_family_descriptor_t g_ti_family = {
+ .family_id = kTI_Cc3220sf_FamilyID,
+ .target_set_state = target_set_state_ti,
+ .validate_bin_nvic = validate_bin_nvic_ti,
+};
+
diff -r 000000000000 -r 01f31e923fe2 source/family/toshiba/target_reset_tz.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/toshiba/target_reset_tz.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,40 @@
+/**
+ * @file target_reset.c
+ * @brief Target reset for the lpc812
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "cmsis_os2.h"
+#include "swd_host.h"
+#include "target_family.h"
+
+static void target_before_init_debug_tz(void) {
+ swd_set_target_reset(1);
+ osDelay(2);
+ swd_set_target_reset(0);
+ osDelay(2);
+ return;
+}
+
+
+const target_family_descriptor_t g_toshiba_tz_family = {
+ .family_id = kToshiba_Tz_FamilyID,
+ .default_reset_type = kSoftwareReset,
+ .soft_reset_type = SYSRESETREQ,
+ .target_before_init_debug = target_before_init_debug_tz,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/toshiba/tz10xx/target_remap0.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/toshiba/tz10xx/target_remap0.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,38 @@
+/**
+ * @file target.c
+ * @brief Target information for the lpc1114
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// FlashAlgo
+#include "flash_blob.h"
+#include "tz10xx_prog_blob.h"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0,
+ .flash_regions[0].end = MB(1),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20008000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/toshiba/tz10xx/tz10xx_prog_blob.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/toshiba/tz10xx/tz10xx_prog_blob.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,81 @@
+/* Flash OS Routines (Automagically Generated)
+ * Copyright (c) 2009-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+static const uint32_t tz10xx_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x43f8e92d, 0xf44f2206, 0xf44f7144, 0xf0007080, 0xbb20f938, 0x7480f44f, 0xf44f00a5, 0xf44f52fa,
+ 0xf04f760c, 0xf04f0c01, 0xf04f0800, 0x270f2340, 0x629c2005, 0x631e62dd, 0x0100f8c3, 0xc034f8c3,
+ 0x50faf44f, 0x10a0f8d3, 0x0f01f011, 0xb158d00a, 0x70a0f8c3, 0x0200f8d3, 0x46409000, 0x2001b130,
+ 0x83f8e8bd, 0xd1ed1e40, 0xe7f74660, 0xf0109800, 0xd1010f02, 0xd1db1e52, 0xe8bd2000, 0x49ad83f8,
+ 0xf8c12000, 0x2a030154, 0xf04fd103, 0x20012140, 0x20006508, 0x20004770, 0xe92d4770, 0xf7ff45f8,
+ 0x2800ffaf, 0x2060bf08, 0xbf00d12f, 0xd1fc1e40, 0xf44f22c7, 0xf44f7144, 0xf0007080, 0xbb20f8e2,
+ 0xf44f2200, 0x00a57480, 0x760cf44f, 0x0c01f04f, 0xf04f4692, 0x270f2340, 0x7810f242, 0x629c2005,
+ 0x631e62dd, 0x0100f8c3, 0xc034f8c3, 0x50faf44f, 0x10a0f8d3, 0x0f01f011, 0xb158d00a, 0x70a0f8c3,
+ 0x0200f8d3, 0x46509000, 0x2001b130, 0x85f8e8bd, 0xd1ed1e40, 0xe7f74660, 0xf0109800, 0xbf180f01,
+ 0x60e0f642, 0xbf00d005, 0xd1fc1e40, 0x45421c52, 0x2000dbd4, 0x85f8e8bd, 0x4604b510, 0xff60f7ff,
+ 0xbf082800, 0xd1102160, 0x1e49bf00, 0xba20d1fc, 0x0220f040, 0xf44f4978, 0xf0007080, 0xb920f892,
+ 0xf8aaf000, 0xbf082800, 0x2001bd10, 0xe92dbd10, 0x461543f8, 0x4606460c, 0xff42f7ff, 0xd17a2800,
+ 0x2c40f04f, 0x7780f44f, 0xf8cc2135, 0x00b87028, 0x002cf8cc, 0x720cf44f, 0x2030f8cc, 0x1100f8cc,
+ 0xf8cc2201, 0xf44f2034, 0xf8dc51fa, 0xf01330a0, 0xd00a0f01, 0x210fb159, 0x10a0f8cc, 0x1200f8dc,
+ 0x21009100, 0xd1562900, 0x1e49e003, 0x4611d1ed, 0x9900e7f8, 0x8164f8df, 0x0f02f011, 0x0101f1a4,
+ 0x6101ea48, 0xf44fd00b, 0xf8cc7381, 0xf8cc3028, 0xf8cc002c, 0xba301030, 0x0032f040, 0xf8cce008,
+ 0xf8cc7028, 0xf8cc002c, 0xba301030, 0x0002f040, 0x0100f8cc, 0xf0242000, 0x2c000103, 0xf020d907,
+ 0x4e470303, 0x503358eb, 0x42841d00, 0x42a1d8f7, 0xf021d006, 0xf1010003, 0x58282140, 0x0200f8c1,
+ 0xd2082ce0, 0xeba02008, 0xeb001054, 0x00800040, 0x1e40bf00, 0xf8ccd1fc, 0xf44f2034, 0xf8dc50fa,
+ 0xf01110a0, 0xd0090f02, 0xf000b128, 0x2800f825, 0xe8bdbf08, 0x200183f8, 0x83f8e8bd, 0xd1ee1e40,
+ 0xf04fe7f9, 0x62982340, 0x62d81518, 0xf8c36319, 0x20012100, 0xf44f6358, 0xf8d350fa, 0xf01110a0,
+ 0xd0050f02, 0x200fb130, 0x00a0f8c3, 0x47702000, 0xd1f21e40, 0x47702001, 0x01f8e92d, 0x7480f44f,
+ 0xf44f00a5, 0xf44f52fa, 0xf04f760c, 0xf04f0c01, 0xf04f0800, 0x270f2340, 0x629c2005, 0x631e62dd,
+ 0x0100f8c3, 0xc034f8c3, 0x50faf44f, 0x10a0f8d3, 0x0f01f011, 0xb160d00b, 0x70a0f8c3, 0x0200f8d3,
+ 0x46409000, 0xe8bdb138, 0x200101f8, 0x1e404770, 0x4660d1ec, 0x9800e7f6, 0x0f01f010, 0x2000bf18,
+ 0x1c40d004, 0xdbfc2864, 0xd1d51e52, 0x01f8e8bd, 0x47702000, 0x4004a000, 0x00030310, 0x00030330,
+ 0x40004200, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 1024},
+};
+
+static const program_target_t flash = {
+ 0x2000009F, // Init
+ 0x200000B7, // UnInit
+ 0x200000BB, // EraseChip
+ 0x20000159, // EraseSector
+ 0x2000018F, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000000 + 0x00000001,
+ 0x20000000 + 0x00000020 + 0x00000344,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(tz10xx_flash_prog_blob), // prog_blob size
+ tz10xx_flash_prog_blob, // address of prog_blob
+ 0x00000100 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/wiznet/target_reset_wiznet.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/wiznet/target_reset_wiznet.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,55 @@
+/**
+ * @file target_reset.c
+ * @brief Target reset for the W7500
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "cmsis_os2.h"
+#include "swd_host.h"
+#include "target_family.h"
+#include "target_board.h"
+
+static uint8_t target_set_state_wiznet(target_state_t state) {
+ uint8_t status;
+
+ if( state == RESET_RUN )
+ {
+ do
+ {
+ swd_set_target_reset(1);
+ osDelay(2);
+ swd_set_target_reset(0);
+ osDelay(2);
+ } while(!swd_init_debug());
+
+ swd_off();
+ status = 1;
+ }
+ else
+ {
+ status = swd_set_target_state_sw(state);
+ }
+
+ return status;
+}
+
+
+const target_family_descriptor_t g_wiznet_family = {
+ .family_id = kWiznet_W7500_FamilyID,
+ .target_set_state = target_set_state_wiznet,
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/wiznet/w7500/flash_blob.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/wiznet/w7500/flash_blob.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,68 @@
+/**
+ * @file flash_blob.c
+ * @brief Flash algorithm for the W7500
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_blob.h"
+static const uint32_t w7500_flash_prog_blob[] = {
+ 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,
+ 0x4d27b430, 0x606c2400, 0x1e644d26, 0x4c26602c, 0x086d6925, 0x6125006d, 0x46a44c24, 0x4760bc30,
+ 0x47702000, 0x47702000, 0x2014b570, 0x21004c1c, 0x4d1c6061, 0x602c1e4c, 0x69224c1b, 0x006d0855,
+ 0x460b6125, 0x461a4c19, 0x200047a0, 0xb570bd70, 0x49132512, 0x604a2200, 0x17494b12, 0x4c126019,
+ 0x08496921, 0x61210049, 0x4c104601, 0x46284613, 0x200047a0, 0xb570bd70, 0x4b092422, 0x605d2500,
+ 0x175b4d08, 0x4d08602b, 0x085e692b, 0x612e0076, 0x4601460b, 0x4c054620, 0x200047a0, 0x0000bd70,
+ 0xe000ed00, 0xe000e180, 0xe000e000, 0x1fff1001, 0x00000000,
+};
+
+/**
+* List of start and size for each size of flash sector
+* The size will apply to all sectors between the listed address and the next address
+* in the list.
+* The last pair in the list will have sectors starting at that address and ending
+* at address start + size.
+*/
+static const sector_info_t sectors_info[] = {
+ {0, 256},
+};
+
+static const program_target_t flash = {
+ 0x20000041, // Init
+ 0x20000045, // UnInit
+ 0x20000049, // EraseChip
+ 0x2000006F, // EraseSector
+ 0x20000097, // ProgramPage
+ 0x0, // Verify
+
+ // BKPT : start of blob + 1
+ // RSB : blob start + header + rw data offset
+ // RSP : stack pointer
+ {
+ 0x20000000 + 0x00000001,
+ 0x20000000 + 0x00000020 + 0x000000b0,
+ 0x20000800
+ },
+
+ 0x20000000 + 0x00000A00, // mem buffer location
+ 0x20000000, // location to write prog_blob in target RAM
+ sizeof(w7500_flash_prog_blob), // prog_blob size
+ w7500_flash_prog_blob, // address of prog_blob
+
+ // Do not modify. program_buffer_size of W7500 must be set to 0x00000100
+ 0x00000100 // ram_to_flash_bytes_to_be_written
+};
diff -r 000000000000 -r 01f31e923fe2 source/family/wiznet/w7500/target.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/family/wiznet/w7500/target.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file target.c
+ * @brief Target information for the W7500
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_config.h"
+
+// The file flash_blob.c must only be included in target.c
+#include "flash_blob.c"
+
+// target information
+target_cfg_t target_device = {
+ .sectors_info = sectors_info,
+ .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)),
+ .flash_regions[0].start = 0x00000000,
+ .flash_regions[0].end = 0x00000000 + KB(128),
+ .flash_regions[0].flags = kRegionIsDefault,
+ .flash_regions[0].flash_algo = (program_target_t *) &flash,
+ .ram_regions[0].start = 0x20000000,
+ .ram_regions[0].end = 0x20004000,
+};
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/FlashOS.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/FlashOS.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,77 @@
+/**
+ * @file FlashOS.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef FLASHOS_H
+#define FLASHOS_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define VERS 1 // Interface Version 1.01
+#define NAME_MAX 128 // Max size of the routine name
+#define PAGE_MAX 65536 // Max Page Size for Programming
+#define SECTOR_NUM 512 // Max Number of Sector Items
+#define SECTOR_END 0xFFFFFFFF, 0xFFFFFFFF
+
+// FlashDevice.devType interface mechanism
+#define UNKNOWN 0
+#define ONCHIP 1
+#define EXT8BIT 2
+#define EXT16BIT 3
+#define EXT32BIT 4
+#define EXTSPI 5
+
+/**
+ @struct FlashSector
+ @brief A structure to describe the size and start address of a flash sector
+ */
+struct FlashSector {
+ uint32_t szSector; /*!< Sector Size in Bytes */
+ uint32_t adrSector; /*!< Address of Sector */
+};
+
+/**
+ @struct FlashDevice
+ @brief A structure to describe particulars of a flash memory sub-system
+ and requirements of the driver
+ */
+struct FlashDevice {
+ uint16_t vers; /*!< Version Number and Architecture */
+ char devName[NAME_MAX]; /*!< Device Name and Description */
+ uint16_t devType; /*!< Device Type: ONCHIP, EXT8BIT, EXT16BIT, ... */
+ uint32_t devAdr; /*!< Default Device Start Address */
+ uint32_t szDev; /*!< Total Size of Device */
+ uint32_t szPage; /*!< Programming Page Size */
+ uint32_t res; /*!< Reserved for future Extension */
+ uint8_t valEmpty; /*!< Content of Erased Memory */
+ uint32_t toProg; /*!< Time Out of Program Page Function */
+ uint32_t toErase; /*!< Time Out of Erase Sector Function */
+ struct FlashSector sectors[SECTOR_NUM]; /*!< Entries to describe flash memory layout */
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/FlashPrg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/FlashPrg.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,84 @@
+/**
+ * @file FlashPrg.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef FLASHPRG_H
+#define FLASHPRG_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Initialize programming functions
+ * @param adr device base address
+ * @param clk clock frequency (Hz)
+ * @param fnc function code (1 - Erase, 2 - Program, 3 - Verify)
+ * @return 0 on success, an error code otherwise
+ */
+uint32_t Init(uint32_t adr, uint32_t clk, uint32_t fnc);
+
+/** De-Initialize programming functions [optional]
+ * @param fnc function code (1 - Erase, 2 - Program, 3 - Verify)
+ * @return 0 on success, an error code otherwise
+ */
+uint32_t UnInit(uint32_t fnc);
+
+/** Check region for erased memory
+ * @param adr address to start from
+ * @param sz the amount of memory to check
+ * @param pat the pattern of erased memory (usually 0xff)
+ * @return 0 on success, an error code otherwise
+ */
+uint32_t BlankCheck(uint32_t adr, uint32_t sz, uint8_t pat);
+
+/** Perform a full chip erase
+ * @return 0 on success, an error code otherwise
+ */
+uint32_t EraseChip(void);
+
+/** Erase a single sector of memory
+ * @param adr address of a sector to erase
+ * @return 0 on success, an error code otherwise
+ */
+uint32_t EraseSector(uint32_t adr);
+
+/** Program data into memory
+ * @param adr address to start programming from
+ * @param sz the amount of data to program
+ * @param buf memory contents to be programmed
+ * @return 0 on success, an error code otherwise
+ */
+uint32_t ProgramPage(uint32_t adr, uint32_t sz, uint32_t *buf);
+
+/** Verify contents in memory
+ * @param adr start address of the verification
+ * @param sz the amount of data to be verified
+ * @param buf memory contents to be compared against
+ * @return 0 on success, an error code otherwise
+ */
+uint32_t Verify(uint32_t adr, uint32_t sz, uint32_t *buf);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/DAP_config.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/DAP_config.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,510 @@
+/**
+ * @file DAP_config.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __DAP_CONFIG_H__
+#define __DAP_CONFIG_H__
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
+\ingroup DAP_ConfigIO_gr
+@{
+Provides definitions about:
+ - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
+ - Debug Unit communication packet size.
+ - Debug Access Port communication mode (JTAG or SWD).
+ - Optional information about a connected Target Device (for Evaluation Boards).
+*/
+
+#include "IO_Config.h"
+
+/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
+/// This value is used to calculate the SWD/JTAG clock speed.
+#define CPU_CLOCK SystemCoreClock ///< Specifies the CPU Clock in Hz
+
+/// Number of processor cycles for I/O Port write operations.
+/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
+/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
+/// requrie 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
+/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
+/// requrired.
+#define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
+
+/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available
+
+/// Indicate that JTAG communication mode is available at the Debug Port.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available.
+
+/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
+/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
+#define DAP_JTAG_DEV_CNT 0 ///< Maximum number of JTAG devices on scan chain
+
+/// Default communication mode on the Debug Access Port.
+/// Used for the command \ref DAP_Connect when Port Default mode is selected.
+#define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
+
+/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
+/// Used to initialize the default SWD/JTAG clock frequency.
+/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
+#define DAP_DEFAULT_SWJ_CLOCK 2000000 ///< Default SWD/JTAG clock frequency in Hz.
+
+/// Maximum Package Size for Command and Response data.
+/// This configuration settings is used to optimized the communication performance with the
+/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
+#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed.
+
+/// Maximum Package Buffers for Command and Response data.
+/// This configuration settings is used to optimized the communication performance with the
+/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
+/// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
+#define DAP_PACKET_COUNT 4 ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
+
+/// Indicate that UART Serial Wire Output (SWO) trace is available.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available
+
+/// Maximum SWO UART Baudrate
+#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz
+
+/// Indicate that Manchester Serial Wire Output (SWO) trace is available.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available
+
+/// SWO Trace Buffer Size.
+#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n)
+
+/// SWO Streaming Trace.
+#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available.
+
+/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
+#define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported).
+
+
+/// Debug Unit is connected to fixed Target Device.
+/// The Debug Unit may be part of an evaluation board and always connected to a fixed
+/// known device. In this case a Device Vendor and Device Name string is stored which
+/// may be used by the debugger or IDE to configure device parameters.
+#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
+
+#if TARGET_DEVICE_FIXED
+#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor
+#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device
+#endif
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
+\ingroup DAP_ConfigIO_gr
+@{
+
+Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
+and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
+interface of a device. The following I/O Pins are provided:
+
+JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
+---------------------------- | -------------------- | ---------------------------------------------
+TCK: Test Clock | SWCLK: Clock | Output Push/Pull
+TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
+TDI: Test Data Input | | Output Push/Pull
+TDO: Test Data Output | | Input
+nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
+nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
+
+
+DAP Hardware I/O Pin Access Functions
+-------------------------------------
+The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
+these I/O Pins.
+
+For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
+This functions are provided to achieve faster I/O that is possible with some advanced GPIO
+peripherals that can independently write/read a single I/O pin without affecting any other pins
+of the same I/O port. The following SWDIO I/O Pin functions are provided:
+ - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
+ - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
+ - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
+ - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
+*/
+
+
+// Configure DAP I/O pins ------------------------------
+
+/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
+Configures the DAP Hardware I/O pins for JTAG mode:
+ - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
+ - TDO to input mode.
+*/
+__STATIC_INLINE void PORT_JTAG_SETUP(void) {}
+
+/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
+Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
+ - SWCLK, SWDIO, nRESET to output mode and set to default high level.
+ - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
+*/
+__STATIC_INLINE void PORT_SWD_SETUP(void)
+{
+ PMC->PMC_PCER0 = (1 << 10) | (1 << 11) | (1 << 12); // Enable clock for all PIOs
+
+ PIN_nRESET_PORT->PIO_MDDR = PIN_nRESET; // Disable multi drive
+ PIN_nRESET_PORT->PIO_PUER = PIN_nRESET; // pull-up enable
+ PIN_nRESET_PORT->PIO_SODR = PIN_nRESET; // HIGH
+ PIN_nRESET_PORT->PIO_OER = PIN_nRESET; // output
+ PIN_nRESET_PORT->PIO_PER = PIN_nRESET; // GPIO control
+
+ PIN_SWCLK_PORT->PIO_MDDR = PIN_SWCLK; // Disable multi drive
+ PIN_SWCLK_PORT->PIO_PUER = PIN_SWCLK; // pull-up enable
+ PIN_SWCLK_PORT->PIO_SODR = PIN_SWCLK; // HIGH
+ PIN_SWCLK_PORT->PIO_OER = PIN_SWCLK; // output
+ PIN_SWCLK_PORT->PIO_PER = PIN_SWCLK; // GPIO control
+
+ PIN_SWDIO_PORT->PIO_MDDR = PIN_SWDIO; // Disable multi drive
+ PIN_SWDIO_PORT->PIO_PUER = PIN_SWDIO; // pull-up enable
+ PIN_SWDIO_PORT->PIO_SODR = PIN_SWDIO; // HIGH
+ PIN_SWDIO_PORT->PIO_OER = PIN_SWDIO; // output
+ PIN_SWDIO_PORT->PIO_PER = PIN_SWDIO; // GPIO control
+}
+
+/** Disable JTAG/SWD I/O Pins.
+Disables the DAP Hardware I/O pins which configures:
+ - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
+*/
+__STATIC_INLINE void PORT_OFF(void)
+{
+ PIN_nRESET_PORT->PIO_PUER = PIN_nRESET; // pull-up enable
+ PIN_nRESET_PORT->PIO_ODR = PIN_nRESET; // input
+ PIN_nRESET_PORT->PIO_PER = PIN_nRESET; // GPIO control
+
+ PIN_SWCLK_PORT->PIO_PUER = PIN_SWCLK; // pull-up enable
+ PIN_SWCLK_PORT->PIO_ODR = PIN_SWCLK; // input
+ PIN_SWCLK_PORT->PIO_PER = PIN_SWCLK; // GPIO control
+
+ PIN_SWDIO_PORT->PIO_PUER = PIN_SWDIO; // pull-up enable
+ PIN_SWDIO_PORT->PIO_ODR = PIN_SWDIO; // input
+ PIN_SWDIO_PORT->PIO_PER = PIN_SWDIO; // GPIO control
+
+}
+
+// SWCLK/TCK I/O pin -------------------------------------
+
+/** SWCLK/TCK I/O pin: Get Input.
+\return Current status of the SWCLK/TCK DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void)
+{
+ return ((PIN_SWCLK_PORT->PIO_PDSR >> PIN_SWCLK_BIT) & 1);
+}
+
+/** SWCLK/TCK I/O pin: Set Output to High.
+Set the SWCLK/TCK DAP hardware I/O pin to high level.
+*/
+__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET(void)
+{
+ PIN_SWCLK_PORT->PIO_SODR = PIN_SWCLK;
+}
+
+/** SWCLK/TCK I/O pin: Set Output to Low.
+Set the SWCLK/TCK DAP hardware I/O pin to low level.
+*/
+__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void)
+{
+ PIN_SWCLK_PORT->PIO_CODR = PIN_SWCLK;
+}
+
+// SWDIO/TMS Pin I/O --------------------------------------
+
+/** SWDIO/TMS I/O pin: Get Input.
+\return Current status of the SWDIO/TMS DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void)
+{
+ return ((PIN_SWDIO_PORT->PIO_PDSR >> PIN_SWDIO_BIT) & 1);
+}
+
+/** SWDIO/TMS I/O pin: Set Output to High.
+Set the SWDIO/TMS DAP hardware I/O pin to high level.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET(void)
+{
+ PIN_SWDIO_PORT->PIO_SODR = PIN_SWDIO;
+}
+
+/** SWDIO/TMS I/O pin: Set Output to Low.
+Set the SWDIO/TMS DAP hardware I/O pin to low level.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void)
+{
+ PIN_SWDIO_PORT->PIO_CODR = PIN_SWDIO;
+}
+
+/** SWDIO I/O pin: Get Input (used in SWD mode only).
+\return Current status of the SWDIO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
+{
+ return ((PIN_SWDIO_PORT->PIO_PDSR >> PIN_SWDIO_BIT) & 1);
+}
+
+/** SWDIO I/O pin: Set Output (used in SWD mode only).
+\param bit Output value for the SWDIO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT(uint32_t bit)
+{
+ if (bit & 1) {
+ PIN_SWDIO_PORT->PIO_SODR = PIN_SWDIO;
+
+ } else {
+ PIN_SWDIO_PORT->PIO_CODR = PIN_SWDIO;
+ }
+}
+
+/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
+Configure the SWDIO DAP hardware I/O pin to output mode. This function is
+called prior \ref PIN_SWDIO_OUT function calls.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void)
+{
+ PIN_SWDIO_PORT->PIO_OER = PIN_SWDIO;
+}
+
+/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
+Configure the SWDIO DAP hardware I/O pin to input mode. This function is
+called prior \ref PIN_SWDIO_IN function calls.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void)
+{
+ PIN_SWDIO_PORT->PIO_ODR = PIN_SWDIO;
+}
+
+
+// TDI Pin I/O ---------------------------------------------
+
+/** TDI I/O pin: Get Input.
+\return Current status of the TDI DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void)
+{
+ return (0); // Not available
+}
+
+/** TDI I/O pin: Set Output.
+\param bit Output value for the TDI DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE void PIN_TDI_OUT(uint32_t bit)
+{
+ ; // Not available
+}
+
+
+// TDO Pin I/O ---------------------------------------------
+
+/** TDO I/O pin: Get Input.
+\return Current status of the TDO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void)
+{
+ return (0); // Not available
+}
+
+
+// nTRST Pin I/O -------------------------------------------
+
+/** nTRST I/O pin: Get Input.
+\return Current status of the nTRST DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void)
+{
+ return (0); // Not available
+}
+
+/** nTRST I/O pin: Set Output.
+\param bit JTAG TRST Test Reset pin status:
+ - 0: issue a JTAG TRST Test Reset.
+ - 1: release JTAG TRST Test Reset.
+*/
+__STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit)
+{
+ ; // Not available
+}
+
+// nRESET Pin I/O------------------------------------------
+
+/** nRESET I/O pin: Get Input.
+\return Current status of the nRESET DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void)
+{
+ return ((PIN_nRESET_PORT->PIO_PDSR >> PIN_nRESET_BIT) & 1);
+}
+
+/** nRESET I/O pin: Set Output.
+\param bit target device hardware reset pin status:
+ - 0: issue a device hardware reset.
+ - 1: release device hardware reset.
+*/
+// TODO - sw specific implementation should be created
+#if defined (DBG_NRF51822AA)
+__STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit)
+{
+ /**There is no reset pin on the nRF51822, so we need to use a reset routine:
+ Enable reset through the RESET register in the POWER peripheral.
+ Hold the SWDCLK and SWDIO/nRESET line low for a minimum of 100 us.
+ */
+ if (bit & 1) {
+ PIN_SWDIO_PORT->PIO_SODR = PIN_SWDIO;
+
+ PIN_SWDIO_PORT->PIO_MDER = PIN_SWDIO;
+ PIN_SWCLK_PORT->PIO_MDER = PIN_SWCLK;
+ PIN_nRESET_PORT->PIO_MDER = PIN_nRESET;
+
+ } else {
+ swd_init_debug();
+
+ //Set POWER->RESET on NRF to 1
+ if (!swd_write_ap(AP_TAR, 0x40000000 + 0x544)) {
+ return;
+ }
+
+ if (!swd_write_ap(AP_DRW, 1)) {
+ return;
+ }
+
+ //Hold RESET and SWCLK low for a minimum of 100us
+ PIN_SWDIO_PORT->PIO_OER = PIN_SWDIO;
+ PIN_SWCLK_PORT->PIO_OER = PIN_SWCLK;
+ PIN_SWDIO_PORT->PIO_CODR = PIN_SWDIO;
+ PIN_SWCLK_PORT->PIO_CODR = PIN_SWCLK;
+ osDelay(1);
+ }
+}
+#else
+__STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit)
+{
+ if (bit & 1) {
+ PIN_nRESET_PORT->PIO_SODR = PIN_nRESET;
+
+ } else {
+ PIN_nRESET_PORT->PIO_CODR = PIN_nRESET;
+ }
+}
+#endif
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
+\ingroup DAP_ConfigIO_gr
+@{
+
+CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
+
+It is recommended to provide the following LEDs for status indication:
+ - Connect LED: is active when the DAP hardware is connected to a debugger.
+ - Running LED: is active when the debugger has put the target device into running state.
+*/
+
+/** Debug Unit: Set status of Connected LED.
+\param bit status of the Connect LED.
+ - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
+ - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
+*/
+__STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit)
+{
+}
+
+/** Debug Unit: Set status Target Running LED.
+\param bit status of the Target Running LED.
+ - 1: Target Running LED ON: program execution in target started.
+ - 0: Target Running LED OFF: program execution in target stopped.
+*/
+__STATIC_INLINE void LED_RUNNING_OUT(uint32_t bit)
+{
+ ; // Not available
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
+\ingroup DAP_ConfigIO_gr
+@{
+Access function for Test Domain Timer.
+
+The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
+default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
+
+*/
+
+/** Get timestamp of Test Domain Timer.
+\return Current timestamp value.
+*/
+__STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
+ return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK);
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
+\ingroup DAP_ConfigIO_gr
+@{
+
+CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
+*/
+
+/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
+This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
+Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
+ - I/O clock system enabled.
+ - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
+ - for nTRST, nRESET a weak pull-up (if available) is enabled.
+ - LED output pins are enabled and LEDs are turned off.
+*/
+__STATIC_INLINE void DAP_SETUP(void)
+{
+}
+
+/** Reset Target Device with custom specific I/O pin or command sequence.
+This function allows the optional implementation of a device specific reset sequence.
+It is called when the command \ref DAP_ResetTarget and is for example required
+when a device needs a time-critical unlock sequence that enables the debug port.
+\return 0 = no device specific reset sequence is implemented.\n
+ 1 = a device specific reset sequence is implemented.
+*/
+__STATIC_INLINE uint32_t RESET_TARGET(void)
+{
+ return (0); // change to '1' when a device reset sequence is implemented
+}
+
+///@}
+
+
+#endif /* __DAP_CONFIG_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/IO_Config.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/IO_Config.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,90 @@ +/** + * @file IO_Config.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ + +#include "sam3u2c.h" +#include "daplink.h" + +#ifdef IO_CONFIG_OVERRIDE +#include "IO_Config_Override.h" +#endif + +// This GPIO configuration is only valid for the LPC11U35 HIC +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_SAM3U2C); + +// DAP LED +#ifndef PIN_DAP_LED +#define PIN_DAP_LED_PORT PIOA +#define PIN_DAP_LED_BIT 29 +#define PIN_DAP_LED (1UL << PIN_DAP_LED_BIT) +#endif + +// MSD LED +#ifndef PIN_MSD_LED +#define PIN_MSD_LED_PORT PIOA +#define PIN_MSD_LED_BIT 28 +#define PIN_MSD_LED (1UL << PIN_MSD_LED_BIT) +#endif + +// CDC LED +#ifndef PIN_CDC_LED +#define PIN_CDC_LED_PORT PIOA +#define PIN_CDC_LED_BIT 31 +#define PIN_CDC_LED (1UL << PIN_CDC_LED_BIT) +#endif + +// Non-Forwarded Reset in PIN - Not used + +// Forwarded Reset in PIN +#ifndef PIN_RESET_IN_FWRD +#define PIN_RESET_IN_FWRD_PORT PIOA +#define PIN_RESET_IN_FWRD_BIT 25 +#define PIN_RESET_IN_FWRD (1UL << PIN_RESET_IN_FWRD_BIT) +#endif + +// nRESET OUT Pin +#ifndef PIN_nRESET +#define PIN_nRESET_PORT PIOA +#define PIN_nRESET_BIT 4 +#define PIN_nRESET (1UL << PIN_nRESET_BIT) +#endif + +// SWCLK/TCK Pin +#ifndef PIN_SWCLK +#define PIN_SWCLK_PORT PIOA +#define PIN_SWCLK_BIT 17 +#define PIN_SWCLK (1UL << PIN_SWCLK_BIT) +#endif + +// SWDIO/TMS In/Out Pin +#ifndef PIN_SWDIO +#define PIN_SWDIO_PORT PIOA +#define PIN_SWDIO_BIT 18 +#define PIN_SWDIO (1UL << PIN_SWDIO_BIT) +#endif + +// TDI Pin - Not used + +// SWO/TDO Pin - Not used + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/armcc/startup_SAM3U.s --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/armcc/startup_SAM3U.s Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,261 @@ +;/***************************************************************************** +; * @file: startup_SAM3U.s +; * @purpose: CMSIS Cortex-M3 Core Device Startup File +; * for the Atmel SAM3U Device Series +; * @version: V1.10 +; * @date: 17. April 2013 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * Copyright (C) 2009-2013 ARM Limited. All rights reserved. +; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; *****************************************************************************/ + + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + IMPORT g_board_info +__Vectors DCD __initial_sp ; 0: Top of Stack + DCD Reset_Handler ; 1: Reset Handler + DCD NMI_Handler ; 2: NMI Handler + DCD HardFault_Handler ; 3: Hard Fault Handler + DCD MemManage_Handler ; 4: MPU Fault Handler + DCD BusFault_Handler ; 5: Bus Fault Handler + DCD UsageFault_Handler ; 6: Usage Fault Handler + DCD 0 ; 7: Reserved + DCD DAPLINK_BUILD_KEY ; 8: Build type - BL/IF + DCD DAPLINK_HIC_ID ; 9: Compatibility + DCD DAPLINK_VERSION ; 10:Version + DCD SVC_Handler ; 11: SVCall Handler + DCD DebugMon_Handler ; 12: Debug Monitor Handler + DCD g_board_info ; 13: Ptr to Board info, family info other target details + DCD PendSV_Handler ; 14: PendSV Handler + DCD SysTick_Handler ; 15: SysTick Handler + + ; External Interrupts + DCD SUPC_IRQHandler ; 0: Supply Controller + DCD RSTC_IRQHandler ; 1: Reset Controller + DCD RTC_IRQHandler ; 2: Real Time Clock + DCD RTT_IRQHandler ; 3: Real Time Timer + DCD WDT_IRQHandler ; 4: Watchdog Timer + DCD PMC_IRQHandler ; 5: Power Management Controller + DCD EEFC0_IRQHandler ; 6: Enhanced Embedded Flash Controller 0 + DCD EEFC1_IRQHandler ; 7: Enhanced Embedded Flash Controller 1 + DCD UART_IRQHandler ; 8: UART + DCD SMC_IRQHandler ; 9: Static Memory Controller + DCD PIOA_IRQHandler ; 10: Parallel I/O Controller A + DCD PIOB_IRQHandler ; 11: Parallel I/O Controller B + DCD PIOC_IRQHandler ; 12: Parallel I/O Controller C + DCD USART0_IRQHandler ; 13: USART 0 + DCD USART1_IRQHandler ; 14: USART 1 + DCD USART2_IRQHandler ; 15: USART 2 + DCD USART3_IRQHandler ; 16: USART 3 + DCD HSMCI_IRQHandler ; 17: High Speed Multimedia Card Interface + DCD TWI0_IRQHandler ; 18: Two-wire Interface 0 + DCD TWI1_IRQHandler ; 19: Two-wire Interface 1 + DCD SPI_IRQHandler ; 20: Synchronous Peripheral Interface + DCD SSC_IRQHandler ; 21: Synchronous Serial Controller + DCD TC0_IRQHandler ; 22: Timer Counter 0 + DCD TC1_IRQHandler ; 23: Timer Counter 1 + DCD TC2_IRQHandler ; 24: Timer Counter 2 + DCD PWM_IRQHandler ; 25: Pulse Width Modulation Controller + DCD ADC12B_IRQHandler ; 26: 12-bit ADC Controller + DCD ADC_IRQHandler ; 27: 10-bit ADC Controller + DCD DMAC_IRQHandler ; 28: DMA Controller + DCD UDPHS_IRQHandler ; 29: USB Device High Speed + + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT SUPC_IRQHandler [WEAK] + EXPORT RSTC_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT RTT_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT PMC_IRQHandler [WEAK] + EXPORT EEFC0_IRQHandler [WEAK] + EXPORT EEFC1_IRQHandler [WEAK] + EXPORT UART_IRQHandler [WEAK] + EXPORT SMC_IRQHandler [WEAK] + EXPORT PIOA_IRQHandler [WEAK] + EXPORT PIOB_IRQHandler [WEAK] + EXPORT PIOC_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT HSMCI_IRQHandler [WEAK] + EXPORT TWI0_IRQHandler [WEAK] + EXPORT TWI1_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + EXPORT SSC_IRQHandler [WEAK] + EXPORT TC0_IRQHandler [WEAK] + EXPORT TC1_IRQHandler [WEAK] + EXPORT TC2_IRQHandler [WEAK] + EXPORT PWM_IRQHandler [WEAK] + EXPORT ADC12B_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT DMAC_IRQHandler [WEAK] + EXPORT UDPHS_IRQHandler [WEAK] + +SUPC_IRQHandler +RSTC_IRQHandler +RTC_IRQHandler +RTT_IRQHandler +WDT_IRQHandler +PMC_IRQHandler +EEFC0_IRQHandler +EEFC1_IRQHandler +UART_IRQHandler +SMC_IRQHandler +PIOA_IRQHandler +PIOB_IRQHandler +PIOC_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +HSMCI_IRQHandler +TWI0_IRQHandler +TWI1_IRQHandler +SPI_IRQHandler +SSC_IRQHandler +TC0_IRQHandler +TC1_IRQHandler +TC2_IRQHandler +PWM_IRQHandler +ADC12B_IRQHandler +ADC_IRQHandler +DMAC_IRQHandler +UDPHS_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/component/adc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/component/adc.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,229 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U_ADC_COMPONENT_
+#define _SAM3U_ADC_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Analog-to-Digital Converter */
+/* ============================================================================= */
+/** \addtogroup SAM3U_ADC Analog-to-Digital Converter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Adc hardware registers */
+typedef struct {
+ WoReg ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */
+ RwReg ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */
+ RoReg Reserved1[2];
+ WoReg ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */
+ WoReg ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */
+ RoReg ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */
+ RoReg ADC_SR; /**< \brief (Adc Offset: 0x1C) Status Register */
+ RoReg ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */
+ WoReg ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */
+ WoReg ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */
+ RoReg ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */
+ RoReg ADC_CDR[8]; /**< \brief (Adc Offset: 0x30) Channel Data Register */
+ RoReg Reserved2[44];
+ RwReg ADC_RPR; /**< \brief (Adc Offset: 0x100) Receive Pointer Register */
+ RwReg ADC_RCR; /**< \brief (Adc Offset: 0x104) Receive Counter Register */
+ RoReg Reserved3[2];
+ RwReg ADC_RNPR; /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */
+ RwReg ADC_RNCR; /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */
+ RoReg Reserved4[2];
+ WoReg ADC_PTCR; /**< \brief (Adc Offset: 0x120) Transfer Control Register */
+ RoReg ADC_PTSR; /**< \brief (Adc Offset: 0x124) Transfer Status Register */
+} Adc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */
+#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */
+#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */
+/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */
+#define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */
+#define ADC_MR_TRGSEL_Pos 1
+#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */
+#define ADC_MR_TRGSEL(value) ((ADC_MR_TRGSEL_Msk & ((value) << ADC_MR_TRGSEL_Pos)))
+#define ADC_MR_LOWRES (0x1u << 4) /**< \brief (ADC_MR) Resolution */
+#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */
+#define ADC_MR_PRESCAL_Pos 8
+#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */
+#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))
+#define ADC_MR_STARTUP_Pos 16
+#define ADC_MR_STARTUP_Msk (0x7fu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */
+#define ADC_MR_STARTUP(value) ((ADC_MR_STARTUP_Msk & ((value) << ADC_MR_STARTUP_Pos)))
+#define ADC_MR_SHTIM_Pos 24
+#define ADC_MR_SHTIM_Msk (0xfu << ADC_MR_SHTIM_Pos) /**< \brief (ADC_MR) Sample & Hold Time */
+#define ADC_MR_SHTIM(value) ((ADC_MR_SHTIM_Msk & ((value) << ADC_MR_SHTIM_Pos)))
+/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */
+#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */
+#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */
+#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */
+#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */
+#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */
+#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */
+#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */
+#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */
+/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */
+#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */
+#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */
+#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */
+#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */
+#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */
+#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */
+#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */
+#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */
+/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */
+#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */
+#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */
+#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */
+#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */
+#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */
+#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */
+#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */
+#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */
+/* -------- ADC_SR : (ADC Offset: 0x1C) Status Register -------- */
+#define ADC_SR_EOC0 (0x1u << 0) /**< \brief (ADC_SR) End of Conversion 0 */
+#define ADC_SR_EOC1 (0x1u << 1) /**< \brief (ADC_SR) End of Conversion 1 */
+#define ADC_SR_EOC2 (0x1u << 2) /**< \brief (ADC_SR) End of Conversion 2 */
+#define ADC_SR_EOC3 (0x1u << 3) /**< \brief (ADC_SR) End of Conversion 3 */
+#define ADC_SR_EOC4 (0x1u << 4) /**< \brief (ADC_SR) End of Conversion 4 */
+#define ADC_SR_EOC5 (0x1u << 5) /**< \brief (ADC_SR) End of Conversion 5 */
+#define ADC_SR_EOC6 (0x1u << 6) /**< \brief (ADC_SR) End of Conversion 6 */
+#define ADC_SR_EOC7 (0x1u << 7) /**< \brief (ADC_SR) End of Conversion 7 */
+#define ADC_SR_OVRE0 (0x1u << 8) /**< \brief (ADC_SR) Overrun Error 0 */
+#define ADC_SR_OVRE1 (0x1u << 9) /**< \brief (ADC_SR) Overrun Error 1 */
+#define ADC_SR_OVRE2 (0x1u << 10) /**< \brief (ADC_SR) Overrun Error 2 */
+#define ADC_SR_OVRE3 (0x1u << 11) /**< \brief (ADC_SR) Overrun Error 3 */
+#define ADC_SR_OVRE4 (0x1u << 12) /**< \brief (ADC_SR) Overrun Error 4 */
+#define ADC_SR_OVRE5 (0x1u << 13) /**< \brief (ADC_SR) Overrun Error 5 */
+#define ADC_SR_OVRE6 (0x1u << 14) /**< \brief (ADC_SR) Overrun Error 6 */
+#define ADC_SR_OVRE7 (0x1u << 15) /**< \brief (ADC_SR) Overrun Error 7 */
+#define ADC_SR_DRDY (0x1u << 16) /**< \brief (ADC_SR) Data Ready */
+#define ADC_SR_GOVRE (0x1u << 17) /**< \brief (ADC_SR) General Overrun Error */
+#define ADC_SR_ENDRX (0x1u << 18) /**< \brief (ADC_SR) End of RX Buffer */
+#define ADC_SR_RXBUFF (0x1u << 19) /**< \brief (ADC_SR) RX Buffer Full */
+/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */
+#define ADC_LCDR_LDATA_Pos 0
+#define ADC_LCDR_LDATA_Msk (0x3ffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */
+/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */
+#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */
+#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */
+#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */
+#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */
+#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */
+#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */
+#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */
+#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */
+#define ADC_IER_OVRE0 (0x1u << 8) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 0 */
+#define ADC_IER_OVRE1 (0x1u << 9) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 1 */
+#define ADC_IER_OVRE2 (0x1u << 10) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 2 */
+#define ADC_IER_OVRE3 (0x1u << 11) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 3 */
+#define ADC_IER_OVRE4 (0x1u << 12) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 4 */
+#define ADC_IER_OVRE5 (0x1u << 13) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 5 */
+#define ADC_IER_OVRE6 (0x1u << 14) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 6 */
+#define ADC_IER_OVRE7 (0x1u << 15) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 7 */
+#define ADC_IER_DRDY (0x1u << 16) /**< \brief (ADC_IER) Data Ready Interrupt Enable */
+#define ADC_IER_GOVRE (0x1u << 17) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */
+#define ADC_IER_ENDRX (0x1u << 18) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */
+#define ADC_IER_RXBUFF (0x1u << 19) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */
+/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */
+#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */
+#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */
+#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */
+#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */
+#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */
+#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */
+#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */
+#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */
+#define ADC_IDR_OVRE0 (0x1u << 8) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 0 */
+#define ADC_IDR_OVRE1 (0x1u << 9) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 1 */
+#define ADC_IDR_OVRE2 (0x1u << 10) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 2 */
+#define ADC_IDR_OVRE3 (0x1u << 11) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 3 */
+#define ADC_IDR_OVRE4 (0x1u << 12) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 4 */
+#define ADC_IDR_OVRE5 (0x1u << 13) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 5 */
+#define ADC_IDR_OVRE6 (0x1u << 14) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 6 */
+#define ADC_IDR_OVRE7 (0x1u << 15) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 7 */
+#define ADC_IDR_DRDY (0x1u << 16) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */
+#define ADC_IDR_GOVRE (0x1u << 17) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */
+#define ADC_IDR_ENDRX (0x1u << 18) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */
+#define ADC_IDR_RXBUFF (0x1u << 19) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */
+/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */
+#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */
+#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */
+#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */
+#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */
+#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */
+#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */
+#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */
+#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */
+#define ADC_IMR_OVRE0 (0x1u << 8) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 0 */
+#define ADC_IMR_OVRE1 (0x1u << 9) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 1 */
+#define ADC_IMR_OVRE2 (0x1u << 10) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 2 */
+#define ADC_IMR_OVRE3 (0x1u << 11) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 3 */
+#define ADC_IMR_OVRE4 (0x1u << 12) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 4 */
+#define ADC_IMR_OVRE5 (0x1u << 13) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 5 */
+#define ADC_IMR_OVRE6 (0x1u << 14) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 6 */
+#define ADC_IMR_OVRE7 (0x1u << 15) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 7 */
+#define ADC_IMR_DRDY (0x1u << 16) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */
+#define ADC_IMR_GOVRE (0x1u << 17) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */
+#define ADC_IMR_ENDRX (0x1u << 18) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */
+#define ADC_IMR_RXBUFF (0x1u << 19) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */
+/* -------- ADC_CDR[8] : (ADC Offset: 0x30) Channel Data Register -------- */
+#define ADC_CDR_DATA_Pos 0
+#define ADC_CDR_DATA_Msk (0x3ffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[8]) Converted Data */
+/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */
+#define ADC_RPR_RXPTR_Pos 0
+#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */
+#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos)))
+/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */
+#define ADC_RCR_RXCTR_Pos 0
+#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */
+#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos)))
+/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */
+#define ADC_RNPR_RXNPTR_Pos 0
+#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */
+#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos)))
+/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */
+#define ADC_RNCR_RXNCTR_Pos 0
+#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */
+#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos)))
+/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */
+#define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */
+#define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */
+#define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */
+#define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */
+/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */
+#define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */
+#define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3U_ADC_COMPONENT_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/component/adc12b.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/component/adc12b.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,246 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U_ADC12B_COMPONENT_
+#define _SAM3U_ADC12B_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Analog-to-Digital Converter 12bits */
+/* ============================================================================= */
+/** \addtogroup SAM3U_ADC12B Analog-to-Digital Converter 12bits */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Adc12b hardware registers */
+typedef struct {
+ WoReg ADC12B_CR; /**< \brief (Adc12b Offset: 0x00) Control Register */
+ RwReg ADC12B_MR; /**< \brief (Adc12b Offset: 0x04) Mode Register */
+ RoReg Reserved1[2];
+ WoReg ADC12B_CHER; /**< \brief (Adc12b Offset: 0x10) Channel Enable Register */
+ WoReg ADC12B_CHDR; /**< \brief (Adc12b Offset: 0x14) Channel Disable Register */
+ RoReg ADC12B_CHSR; /**< \brief (Adc12b Offset: 0x18) Channel Status Register */
+ RoReg ADC12B_SR; /**< \brief (Adc12b Offset: 0x1C) Status Register */
+ RoReg ADC12B_LCDR; /**< \brief (Adc12b Offset: 0x20) Last Converted Data Register */
+ WoReg ADC12B_IER; /**< \brief (Adc12b Offset: 0x24) Interrupt Enable Register */
+ WoReg ADC12B_IDR; /**< \brief (Adc12b Offset: 0x28) Interrupt Disable Register */
+ RoReg ADC12B_IMR; /**< \brief (Adc12b Offset: 0x2C) Interrupt Mask Register */
+ RoReg ADC12B_CDR[8]; /**< \brief (Adc12b Offset: 0x30) Channel Data Register */
+ RoReg Reserved2[5];
+ RwReg ADC12B_ACR; /**< \brief (Adc12b Offset: 0x64) Analog Control Register */
+ RwReg ADC12B_EMR; /**< \brief (Adc12b Offset: 0x68) Extended Mode Register */
+ RoReg Reserved3[37];
+ RwReg ADC12B_RPR; /**< \brief (Adc12b Offset: 0x100) Receive Pointer Register */
+ RwReg ADC12B_RCR; /**< \brief (Adc12b Offset: 0x104) Receive Counter Register */
+ RoReg Reserved4[2];
+ RwReg ADC12B_RNPR; /**< \brief (Adc12b Offset: 0x110) Receive Next Pointer Register */
+ RwReg ADC12B_RNCR; /**< \brief (Adc12b Offset: 0x114) Receive Next Counter Register */
+ RoReg Reserved5[2];
+ WoReg ADC12B_PTCR; /**< \brief (Adc12b Offset: 0x120) Transfer Control Register */
+ RoReg ADC12B_PTSR; /**< \brief (Adc12b Offset: 0x124) Transfer Status Register */
+} Adc12b;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- ADC12B_CR : (ADC12B Offset: 0x00) Control Register -------- */
+#define ADC12B_CR_SWRST (0x1u << 0) /**< \brief (ADC12B_CR) Software Reset */
+#define ADC12B_CR_START (0x1u << 1) /**< \brief (ADC12B_CR) Start Conversion */
+/* -------- ADC12B_MR : (ADC12B Offset: 0x04) Mode Register -------- */
+#define ADC12B_MR_TRGEN (0x1u << 0) /**< \brief (ADC12B_MR) Trigger Enable */
+#define ADC12B_MR_TRGSEL_Pos 1
+#define ADC12B_MR_TRGSEL_Msk (0x7u << ADC12B_MR_TRGSEL_Pos) /**< \brief (ADC12B_MR) Trigger Selection */
+#define ADC12B_MR_TRGSEL(value) ((ADC12B_MR_TRGSEL_Msk & ((value) << ADC12B_MR_TRGSEL_Pos)))
+#define ADC12B_MR_LOWRES (0x1u << 4) /**< \brief (ADC12B_MR) Resolution */
+#define ADC12B_MR_SLEEP (0x1u << 5) /**< \brief (ADC12B_MR) Sleep Mode */
+#define ADC12B_MR_PRESCAL_Pos 8
+#define ADC12B_MR_PRESCAL_Msk (0xffu << ADC12B_MR_PRESCAL_Pos) /**< \brief (ADC12B_MR) Prescaler Rate Selection */
+#define ADC12B_MR_PRESCAL(value) ((ADC12B_MR_PRESCAL_Msk & ((value) << ADC12B_MR_PRESCAL_Pos)))
+#define ADC12B_MR_STARTUP_Pos 16
+#define ADC12B_MR_STARTUP_Msk (0xffu << ADC12B_MR_STARTUP_Pos) /**< \brief (ADC12B_MR) Start Up Time */
+#define ADC12B_MR_STARTUP(value) ((ADC12B_MR_STARTUP_Msk & ((value) << ADC12B_MR_STARTUP_Pos)))
+#define ADC12B_MR_SHTIM_Pos 24
+#define ADC12B_MR_SHTIM_Msk (0xfu << ADC12B_MR_SHTIM_Pos) /**< \brief (ADC12B_MR) Sample & Hold Time */
+#define ADC12B_MR_SHTIM(value) ((ADC12B_MR_SHTIM_Msk & ((value) << ADC12B_MR_SHTIM_Pos)))
+/* -------- ADC12B_CHER : (ADC12B Offset: 0x10) Channel Enable Register -------- */
+#define ADC12B_CHER_CH0 (0x1u << 0) /**< \brief (ADC12B_CHER) Channel 0 Enable */
+#define ADC12B_CHER_CH1 (0x1u << 1) /**< \brief (ADC12B_CHER) Channel 1 Enable */
+#define ADC12B_CHER_CH2 (0x1u << 2) /**< \brief (ADC12B_CHER) Channel 2 Enable */
+#define ADC12B_CHER_CH3 (0x1u << 3) /**< \brief (ADC12B_CHER) Channel 3 Enable */
+#define ADC12B_CHER_CH4 (0x1u << 4) /**< \brief (ADC12B_CHER) Channel 4 Enable */
+#define ADC12B_CHER_CH5 (0x1u << 5) /**< \brief (ADC12B_CHER) Channel 5 Enable */
+#define ADC12B_CHER_CH6 (0x1u << 6) /**< \brief (ADC12B_CHER) Channel 6 Enable */
+#define ADC12B_CHER_CH7 (0x1u << 7) /**< \brief (ADC12B_CHER) Channel 7 Enable */
+/* -------- ADC12B_CHDR : (ADC12B Offset: 0x14) Channel Disable Register -------- */
+#define ADC12B_CHDR_CH0 (0x1u << 0) /**< \brief (ADC12B_CHDR) */
+#define ADC12B_CHDR_CH1 (0x1u << 1) /**< \brief (ADC12B_CHDR) */
+#define ADC12B_CHDR_CH2 (0x1u << 2) /**< \brief (ADC12B_CHDR) */
+#define ADC12B_CHDR_CH3 (0x1u << 3) /**< \brief (ADC12B_CHDR) */
+#define ADC12B_CHDR_CH4 (0x1u << 4) /**< \brief (ADC12B_CHDR) */
+#define ADC12B_CHDR_CH5 (0x1u << 5) /**< \brief (ADC12B_CHDR) */
+#define ADC12B_CHDR_CH6 (0x1u << 6) /**< \brief (ADC12B_CHDR) */
+#define ADC12B_CHDR_CH7 (0x1u << 7) /**< \brief (ADC12B_CHDR) */
+/* -------- ADC12B_CHSR : (ADC12B Offset: 0x18) Channel Status Register -------- */
+#define ADC12B_CHSR_CH0 (0x1u << 0) /**< \brief (ADC12B_CHSR) Channel 0 Status */
+#define ADC12B_CHSR_CH1 (0x1u << 1) /**< \brief (ADC12B_CHSR) Channel 1 Status */
+#define ADC12B_CHSR_CH2 (0x1u << 2) /**< \brief (ADC12B_CHSR) Channel 2 Status */
+#define ADC12B_CHSR_CH3 (0x1u << 3) /**< \brief (ADC12B_CHSR) Channel 3 Status */
+#define ADC12B_CHSR_CH4 (0x1u << 4) /**< \brief (ADC12B_CHSR) Channel 4 Status */
+#define ADC12B_CHSR_CH5 (0x1u << 5) /**< \brief (ADC12B_CHSR) Channel 5 Status */
+#define ADC12B_CHSR_CH6 (0x1u << 6) /**< \brief (ADC12B_CHSR) Channel 6 Status */
+#define ADC12B_CHSR_CH7 (0x1u << 7) /**< \brief (ADC12B_CHSR) Channel 7 Status */
+/* -------- ADC12B_SR : (ADC12B Offset: 0x1C) Status Register -------- */
+#define ADC12B_SR_EOC0 (0x1u << 0) /**< \brief (ADC12B_SR) End of Conversion 0 */
+#define ADC12B_SR_EOC1 (0x1u << 1) /**< \brief (ADC12B_SR) End of Conversion 1 */
+#define ADC12B_SR_EOC2 (0x1u << 2) /**< \brief (ADC12B_SR) End of Conversion 2 */
+#define ADC12B_SR_EOC3 (0x1u << 3) /**< \brief (ADC12B_SR) End of Conversion 3 */
+#define ADC12B_SR_EOC4 (0x1u << 4) /**< \brief (ADC12B_SR) End of Conversion 4 */
+#define ADC12B_SR_EOC5 (0x1u << 5) /**< \brief (ADC12B_SR) End of Conversion 5 */
+#define ADC12B_SR_EOC6 (0x1u << 6) /**< \brief (ADC12B_SR) End of Conversion 6 */
+#define ADC12B_SR_EOC7 (0x1u << 7) /**< \brief (ADC12B_SR) End of Conversion 7 */
+#define ADC12B_SR_OVRE0 (0x1u << 8) /**< \brief (ADC12B_SR) Overrun Error 0 */
+#define ADC12B_SR_OVRE1 (0x1u << 9) /**< \brief (ADC12B_SR) Overrun Error 1 */
+#define ADC12B_SR_OVRE2 (0x1u << 10) /**< \brief (ADC12B_SR) Overrun Error 2 */
+#define ADC12B_SR_OVRE3 (0x1u << 11) /**< \brief (ADC12B_SR) Overrun Error 3 */
+#define ADC12B_SR_OVRE4 (0x1u << 12) /**< \brief (ADC12B_SR) Overrun Error 4 */
+#define ADC12B_SR_OVRE5 (0x1u << 13) /**< \brief (ADC12B_SR) Overrun Error 5 */
+#define ADC12B_SR_OVRE6 (0x1u << 14) /**< \brief (ADC12B_SR) Overrun Error 6 */
+#define ADC12B_SR_OVRE7 (0x1u << 15) /**< \brief (ADC12B_SR) Overrun Error 7 */
+#define ADC12B_SR_DRDY (0x1u << 16) /**< \brief (ADC12B_SR) Data Ready */
+#define ADC12B_SR_GOVRE (0x1u << 17) /**< \brief (ADC12B_SR) General Overrun Error */
+#define ADC12B_SR_ENDRX (0x1u << 18) /**< \brief (ADC12B_SR) End of RX Buffer */
+#define ADC12B_SR_RXBUFF (0x1u << 19) /**< \brief (ADC12B_SR) RX Buffer Full */
+/* -------- ADC12B_LCDR : (ADC12B Offset: 0x20) Last Converted Data Register -------- */
+#define ADC12B_LCDR_LDATA_Pos 0
+#define ADC12B_LCDR_LDATA_Msk (0xfffu << ADC12B_LCDR_LDATA_Pos) /**< \brief (ADC12B_LCDR) Last Data Converted */
+/* -------- ADC12B_IER : (ADC12B Offset: 0x24) Interrupt Enable Register -------- */
+#define ADC12B_IER_EOC0 (0x1u << 0) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 0 */
+#define ADC12B_IER_EOC1 (0x1u << 1) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 1 */
+#define ADC12B_IER_EOC2 (0x1u << 2) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 2 */
+#define ADC12B_IER_EOC3 (0x1u << 3) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 3 */
+#define ADC12B_IER_EOC4 (0x1u << 4) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 4 */
+#define ADC12B_IER_EOC5 (0x1u << 5) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 5 */
+#define ADC12B_IER_EOC6 (0x1u << 6) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 6 */
+#define ADC12B_IER_EOC7 (0x1u << 7) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 7 */
+#define ADC12B_IER_OVRE0 (0x1u << 8) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 0 */
+#define ADC12B_IER_OVRE1 (0x1u << 9) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 1 */
+#define ADC12B_IER_OVRE2 (0x1u << 10) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 2 */
+#define ADC12B_IER_OVRE3 (0x1u << 11) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 3 */
+#define ADC12B_IER_OVRE4 (0x1u << 12) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 4 */
+#define ADC12B_IER_OVRE5 (0x1u << 13) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 5 */
+#define ADC12B_IER_OVRE6 (0x1u << 14) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 6 */
+#define ADC12B_IER_OVRE7 (0x1u << 15) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 7 */
+#define ADC12B_IER_DRDY (0x1u << 16) /**< \brief (ADC12B_IER) Data Ready Interrupt Enable */
+#define ADC12B_IER_GOVRE (0x1u << 17) /**< \brief (ADC12B_IER) General Overrun Error Interrupt Enable */
+#define ADC12B_IER_ENDRX (0x1u << 18) /**< \brief (ADC12B_IER) End of Receive Buffer Interrupt Enable */
+#define ADC12B_IER_RXBUFF (0x1u << 19) /**< \brief (ADC12B_IER) Receive Buffer Full Interrupt Enable */
+/* -------- ADC12B_IDR : (ADC12B Offset: 0x28) Interrupt Disable Register -------- */
+#define ADC12B_IDR_EOC0 (0x1u << 0) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 0 */
+#define ADC12B_IDR_EOC1 (0x1u << 1) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 1 */
+#define ADC12B_IDR_EOC2 (0x1u << 2) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 2 */
+#define ADC12B_IDR_EOC3 (0x1u << 3) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 3 */
+#define ADC12B_IDR_EOC4 (0x1u << 4) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 4 */
+#define ADC12B_IDR_EOC5 (0x1u << 5) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 5 */
+#define ADC12B_IDR_EOC6 (0x1u << 6) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 6 */
+#define ADC12B_IDR_EOC7 (0x1u << 7) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 7 */
+#define ADC12B_IDR_OVRE0 (0x1u << 8) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 0 */
+#define ADC12B_IDR_OVRE1 (0x1u << 9) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 1 */
+#define ADC12B_IDR_OVRE2 (0x1u << 10) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 2 */
+#define ADC12B_IDR_OVRE3 (0x1u << 11) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 3 */
+#define ADC12B_IDR_OVRE4 (0x1u << 12) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 4 */
+#define ADC12B_IDR_OVRE5 (0x1u << 13) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 5 */
+#define ADC12B_IDR_OVRE6 (0x1u << 14) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 6 */
+#define ADC12B_IDR_OVRE7 (0x1u << 15) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 7 */
+#define ADC12B_IDR_DRDY (0x1u << 16) /**< \brief (ADC12B_IDR) Data Ready Interrupt Disable */
+#define ADC12B_IDR_GOVRE (0x1u << 17) /**< \brief (ADC12B_IDR) General Overrun Error Interrupt Disable */
+#define ADC12B_IDR_ENDRX (0x1u << 18) /**< \brief (ADC12B_IDR) End of Receive Buffer Interrupt Disable */
+#define ADC12B_IDR_RXBUFF (0x1u << 19) /**< \brief (ADC12B_IDR) Receive Buffer Full Interrupt Disable */
+/* -------- ADC12B_IMR : (ADC12B Offset: 0x2C) Interrupt Mask Register -------- */
+#define ADC12B_IMR_EOC0 (0x1u << 0) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 0 */
+#define ADC12B_IMR_EOC1 (0x1u << 1) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 1 */
+#define ADC12B_IMR_EOC2 (0x1u << 2) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 2 */
+#define ADC12B_IMR_EOC3 (0x1u << 3) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 3 */
+#define ADC12B_IMR_EOC4 (0x1u << 4) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 4 */
+#define ADC12B_IMR_EOC5 (0x1u << 5) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 5 */
+#define ADC12B_IMR_EOC6 (0x1u << 6) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 6 */
+#define ADC12B_IMR_EOC7 (0x1u << 7) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 7 */
+#define ADC12B_IMR_OVRE0 (0x1u << 8) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 0 */
+#define ADC12B_IMR_OVRE1 (0x1u << 9) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 1 */
+#define ADC12B_IMR_OVRE2 (0x1u << 10) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 2 */
+#define ADC12B_IMR_OVRE3 (0x1u << 11) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 3 */
+#define ADC12B_IMR_OVRE4 (0x1u << 12) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 4 */
+#define ADC12B_IMR_OVRE5 (0x1u << 13) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 5 */
+#define ADC12B_IMR_OVRE6 (0x1u << 14) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 6 */
+#define ADC12B_IMR_OVRE7 (0x1u << 15) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 7 */
+#define ADC12B_IMR_DRDY (0x1u << 16) /**< \brief (ADC12B_IMR) Data Ready Interrupt Mask */
+#define ADC12B_IMR_GOVRE (0x1u << 17) /**< \brief (ADC12B_IMR) General Overrun Error Interrupt Mask */
+#define ADC12B_IMR_ENDRX (0x1u << 18) /**< \brief (ADC12B_IMR) End of Receive Buffer Interrupt Mask */
+#define ADC12B_IMR_RXBUFF (0x1u << 19) /**< \brief (ADC12B_IMR) Receive Buffer Full Interrupt Mask */
+/* -------- ADC12B_CDR[8] : (ADC12B Offset: 0x30) Channel Data Register -------- */
+#define ADC12B_CDR_DATA_Pos 0
+#define ADC12B_CDR_DATA_Msk (0xfffu << ADC12B_CDR_DATA_Pos) /**< \brief (ADC12B_CDR[8]) Converted Data */
+/* -------- ADC12B_ACR : (ADC12B Offset: 0x64) Analog Control Register -------- */
+#define ADC12B_ACR_GAIN_Pos 0
+#define ADC12B_ACR_GAIN_Msk (0x3u << ADC12B_ACR_GAIN_Pos) /**< \brief (ADC12B_ACR) Input Gain */
+#define ADC12B_ACR_GAIN(value) ((ADC12B_ACR_GAIN_Msk & ((value) << ADC12B_ACR_GAIN_Pos)))
+#define ADC12B_ACR_IBCTL_Pos 8
+#define ADC12B_ACR_IBCTL_Msk (0x3u << ADC12B_ACR_IBCTL_Pos) /**< \brief (ADC12B_ACR) Bias Current Control */
+#define ADC12B_ACR_IBCTL(value) ((ADC12B_ACR_IBCTL_Msk & ((value) << ADC12B_ACR_IBCTL_Pos)))
+#define ADC12B_ACR_DIFF (0x1u << 16) /**< \brief (ADC12B_ACR) Differential Mode */
+#define ADC12B_ACR_OFFSET (0x1u << 17) /**< \brief (ADC12B_ACR) Input OFFSET */
+/* -------- ADC12B_EMR : (ADC12B Offset: 0x68) Extended Mode Register -------- */
+#define ADC12B_EMR_OFFMODES (0x1u << 0) /**< \brief (ADC12B_EMR) Off Mode if Sleep Bit (ADC12B_MR) = 1 */
+#define ADC12B_EMR_OFF_MODE_STARTUP_TIME_Pos 16
+#define ADC12B_EMR_OFF_MODE_STARTUP_TIME_Msk (0xffu << ADC12B_EMR_OFF_MODE_STARTUP_TIME_Pos) /**< \brief (ADC12B_EMR) Startup Time */
+#define ADC12B_EMR_OFF_MODE_STARTUP_TIME(value) ((ADC12B_EMR_OFF_MODE_STARTUP_TIME_Msk & ((value) << ADC12B_EMR_OFF_MODE_STARTUP_TIME_Pos)))
+/* -------- ADC12B_RPR : (ADC12B Offset: 0x100) Receive Pointer Register -------- */
+#define ADC12B_RPR_RXPTR_Pos 0
+#define ADC12B_RPR_RXPTR_Msk (0xffffffffu << ADC12B_RPR_RXPTR_Pos) /**< \brief (ADC12B_RPR) Receive Pointer Register */
+#define ADC12B_RPR_RXPTR(value) ((ADC12B_RPR_RXPTR_Msk & ((value) << ADC12B_RPR_RXPTR_Pos)))
+/* -------- ADC12B_RCR : (ADC12B Offset: 0x104) Receive Counter Register -------- */
+#define ADC12B_RCR_RXCTR_Pos 0
+#define ADC12B_RCR_RXCTR_Msk (0xffffu << ADC12B_RCR_RXCTR_Pos) /**< \brief (ADC12B_RCR) Receive Counter Register */
+#define ADC12B_RCR_RXCTR(value) ((ADC12B_RCR_RXCTR_Msk & ((value) << ADC12B_RCR_RXCTR_Pos)))
+/* -------- ADC12B_RNPR : (ADC12B Offset: 0x110) Receive Next Pointer Register -------- */
+#define ADC12B_RNPR_RXNPTR_Pos 0
+#define ADC12B_RNPR_RXNPTR_Msk (0xffffffffu << ADC12B_RNPR_RXNPTR_Pos) /**< \brief (ADC12B_RNPR) Receive Next Pointer */
+#define ADC12B_RNPR_RXNPTR(value) ((ADC12B_RNPR_RXNPTR_Msk & ((value) << ADC12B_RNPR_RXNPTR_Pos)))
+/* -------- ADC12B_RNCR : (ADC12B Offset: 0x114) Receive Next Counter Register -------- */
+#define ADC12B_RNCR_RXNCTR_Pos 0
+#define ADC12B_RNCR_RXNCTR_Msk (0xffffu << ADC12B_RNCR_RXNCTR_Pos) /**< \brief (ADC12B_RNCR) Receive Next Counter */
+#define ADC12B_RNCR_RXNCTR(value) ((ADC12B_RNCR_RXNCTR_Msk & ((value) << ADC12B_RNCR_RXNCTR_Pos)))
+/* -------- ADC12B_PTCR : (ADC12B Offset: 0x120) Transfer Control Register -------- */
+#define ADC12B_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC12B_PTCR) Receiver Transfer Enable */
+#define ADC12B_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC12B_PTCR) Receiver Transfer Disable */
+#define ADC12B_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC12B_PTCR) Transmitter Transfer Enable */
+#define ADC12B_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC12B_PTCR) Transmitter Transfer Disable */
+/* -------- ADC12B_PTSR : (ADC12B Offset: 0x124) Transfer Status Register -------- */
+#define ADC12B_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC12B_PTSR) Receiver Transfer Enable */
+#define ADC12B_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC12B_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3U_ADC12B_COMPONENT_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/component/chipid.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/component/chipid.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,159 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U_CHIPID_COMPONENT_
+#define _SAM3U_CHIPID_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Chip Identifier */
+/* ============================================================================= */
+/** \addtogroup SAM3U_CHIPID Chip Identifier */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Chipid hardware registers */
+typedef struct {
+ RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */
+ RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */
+} Chipid;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */
+#define CHIPID_CIDR_VERSION_Pos 0
+#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */
+#define CHIPID_CIDR_EPROC_Pos 5
+#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */
+#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */
+#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */
+#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */
+#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */
+#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */
+#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */
+#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */
+#define CHIPID_CIDR_NVPSIZ_Pos 8
+#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */
+#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */
+#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_NVPSIZ2_Pos 12
+#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */
+#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */
+#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_SRAMSIZ_Pos 16
+#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */
+#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48K bytes */
+#define CHIPID_CIDR_SRAMSIZ_1K (0x1u << 16) /**< \brief (CHIPID_CIDR) 1K bytes */
+#define CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2K bytes */
+#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6K bytes */
+#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24K bytes */
+#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4K bytes */
+#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80K bytes */
+#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160K bytes */
+#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96K bytes */
+#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define CHIPID_CIDR_ARCH_Pos 20
+#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */
+#define CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */
+#define CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */
+#define CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */
+#define CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */
+#define CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */
+#define CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */
+#define CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */
+#define CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */
+#define CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */
+#define CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */
+#define CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */
+#define CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */
+#define CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */
+#define CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */
+#define CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */
+#define CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */
+#define CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */
+#define CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */
+#define CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */
+#define CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */
+#define CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC Series (100-pin version) */
+#define CHIPID_CIDR_ARCH_SAM4AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM4AxC Series (100-pin version) */
+#define CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxC Series (100-pin version) */
+#define CHIPID_CIDR_ARCH_SAM4XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM4XxC Series (100-pin version) */
+#define CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxE Series (144-pin version) */
+#define CHIPID_CIDR_ARCH_SAM4XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM4XxE Series (144-pin version) */
+#define CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxG Series (208/217-pin version) */
+#define CHIPID_CIDR_ARCH_SAM4XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM4XxG Series (208/217-pin version) */
+#define CHIPID_CIDR_ARCH_SAM3SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM3SxASeries (48-pin version) */
+#define CHIPID_CIDR_ARCH_SAM4SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM4SxA Series (48-pin version) */
+#define CHIPID_CIDR_ARCH_SAM3SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM3SxB Series (64-pin version) */
+#define CHIPID_CIDR_ARCH_SAM4SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM4SxB Series (64-pin version) */
+#define CHIPID_CIDR_ARCH_SAM3SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM3SxC Series (100-pin version) */
+#define CHIPID_CIDR_ARCH_SAM4SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM4SxC Series (100-pin version) */
+#define CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */
+#define CHIPID_CIDR_ARCH_SAM3NxA (0x93u << 20) /**< \brief (CHIPID_CIDR) SAM3NxA Series (48-pin version) */
+#define CHIPID_CIDR_ARCH_SAM3NxB (0x94u << 20) /**< \brief (CHIPID_CIDR) SAM3NxB Series (64-pin version) */
+#define CHIPID_CIDR_ARCH_SAM3NxC (0x95u << 20) /**< \brief (CHIPID_CIDR) SAM3NxC Series (100-pin version) */
+#define CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */
+#define CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */
+#define CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */
+#define CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */
+#define CHIPID_CIDR_NVPTYP_Pos 28
+#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */
+#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */
+#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */
+#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */
+#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size NVPSIZ2 is Flash size */
+#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */
+#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */
+/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */
+#define CHIPID_EXID_EXID_Pos 0
+#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */
+
+/*@}*/
+
+
+#endif /* _SAM3U_CHIPID_COMPONENT_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/component/dmac.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/component/dmac.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,313 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U_DMAC_COMPONENT_
+#define _SAM3U_DMAC_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR DMA Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_DMAC DMA Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief DmacCh_num hardware registers */
+typedef struct {
+ RwReg DMAC_SADDR; /**< \brief (DmacCh_num Offset: 0x0) DMAC Channel Source Address Register */
+ RwReg DMAC_DADDR; /**< \brief (DmacCh_num Offset: 0x4) DMAC Channel Destination Address Register */
+ RwReg DMAC_DSCR; /**< \brief (DmacCh_num Offset: 0x8) DMAC Channel Descriptor Address Register */
+ RwReg DMAC_CTRLA; /**< \brief (DmacCh_num Offset: 0xC) DMAC Channel Control A Register */
+ RwReg DMAC_CTRLB; /**< \brief (DmacCh_num Offset: 0x10) DMAC Channel Control B Register */
+ RwReg DMAC_CFG; /**< \brief (DmacCh_num Offset: 0x14) DMAC Channel Configuration Register */
+ RoReg Reserved1[4];
+} DmacCh_num;
+/** \brief Dmac hardware registers */
+#define DMACCH_NUM_NUMBER 4
+typedef struct {
+ RwReg DMAC_GCFG; /**< \brief (Dmac Offset: 0x000) DMAC Global Configuration Register */
+ RwReg DMAC_EN; /**< \brief (Dmac Offset: 0x004) DMAC Enable Register */
+ RwReg DMAC_SREQ; /**< \brief (Dmac Offset: 0x008) DMAC Software Single Request Register */
+ RwReg DMAC_CREQ; /**< \brief (Dmac Offset: 0x00C) DMAC Software Chunk Transfer Request Register */
+ RwReg DMAC_LAST; /**< \brief (Dmac Offset: 0x010) DMAC Software Last Transfer Flag Register */
+ RoReg Reserved1[1];
+ WoReg DMAC_EBCIER; /**< \brief (Dmac Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */
+ WoReg DMAC_EBCIDR; /**< \brief (Dmac Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */
+ RoReg DMAC_EBCIMR; /**< \brief (Dmac Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */
+ RoReg DMAC_EBCISR; /**< \brief (Dmac Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */
+ WoReg DMAC_CHER; /**< \brief (Dmac Offset: 0x028) DMAC Channel Handler Enable Register */
+ WoReg DMAC_CHDR; /**< \brief (Dmac Offset: 0x02C) DMAC Channel Handler Disable Register */
+ RoReg DMAC_CHSR; /**< \brief (Dmac Offset: 0x030) DMAC Channel Handler Status Register */
+ RoReg Reserved2[2];
+ DmacCh_num DMAC_CH_NUM[DMACCH_NUM_NUMBER]; /**< \brief (Dmac Offset: 0x3C) ch_num = 0 .. 3 */
+ RoReg Reserved3[66];
+ RwReg DMAC_WPMR; /**< \brief (Dmac Offset: 0x1E4) DMAC Write Protect Mode Register */
+ RoReg DMAC_WPSR; /**< \brief (Dmac Offset: 0x1E8) DMAC Write Protect Status Register */
+} Dmac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- DMAC_GCFG : (DMAC Offset: 0x000) DMAC Global Configuration Register -------- */
+#define DMAC_GCFG_ARB_CFG (0x1u << 4) /**< \brief (DMAC_GCFG) Arbiter Configuration */
+#define DMAC_GCFG_ARB_CFG_FIXED (0x0u << 4) /**< \brief (DMAC_GCFG) Fixed priority arbiter. */
+#define DMAC_GCFG_ARB_CFG_ROUND_ROBIN (0x1u << 4) /**< \brief (DMAC_GCFG) Modified round robin arbiter. */
+/* -------- DMAC_EN : (DMAC Offset: 0x004) DMAC Enable Register -------- */
+#define DMAC_EN_ENABLE (0x1u << 0) /**< \brief (DMAC_EN) */
+/* -------- DMAC_SREQ : (DMAC Offset: 0x008) DMAC Software Single Request Register -------- */
+#define DMAC_SREQ_SSREQ0 (0x1u << 0) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ0 (0x1u << 1) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ1 (0x1u << 2) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ1 (0x1u << 3) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ2 (0x1u << 4) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ2 (0x1u << 5) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ3 (0x1u << 6) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ3 (0x1u << 7) /**< \brief (DMAC_SREQ) Destination Request */
+/* -------- DMAC_CREQ : (DMAC Offset: 0x00C) DMAC Software Chunk Transfer Request Register -------- */
+#define DMAC_CREQ_SCREQ0 (0x1u << 0) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ0 (0x1u << 1) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ1 (0x1u << 2) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ1 (0x1u << 3) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ2 (0x1u << 4) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ2 (0x1u << 5) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ3 (0x1u << 6) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ3 (0x1u << 7) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+/* -------- DMAC_LAST : (DMAC Offset: 0x010) DMAC Software Last Transfer Flag Register -------- */
+#define DMAC_LAST_SLAST0 (0x1u << 0) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST0 (0x1u << 1) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST1 (0x1u << 2) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST1 (0x1u << 3) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST2 (0x1u << 4) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST2 (0x1u << 5) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST3 (0x1u << 6) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST3 (0x1u << 7) /**< \brief (DMAC_LAST) Destination Last */
+/* -------- DMAC_EBCIER : (DMAC Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. -------- */
+#define DMAC_EBCIER_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIER_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIER_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIER_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIER_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIER_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIER_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIER_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIER_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIER) Access Error [3:0] */
+#define DMAC_EBCIER_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIER) Access Error [3:0] */
+#define DMAC_EBCIER_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIER) Access Error [3:0] */
+#define DMAC_EBCIER_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIER) Access Error [3:0] */
+/* -------- DMAC_EBCIDR : (DMAC Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. -------- */
+#define DMAC_EBCIDR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIDR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIDR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIDR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIDR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIDR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIDR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIDR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIDR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIDR) Access Error [3:0] */
+#define DMAC_EBCIDR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIDR) Access Error [3:0] */
+#define DMAC_EBCIDR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIDR) Access Error [3:0] */
+#define DMAC_EBCIDR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIDR) Access Error [3:0] */
+/* -------- DMAC_EBCIMR : (DMAC Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. -------- */
+#define DMAC_EBCIMR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIMR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIMR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIMR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIMR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIMR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIMR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIMR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIMR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIMR) Access Error [3:0] */
+#define DMAC_EBCIMR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIMR) Access Error [3:0] */
+#define DMAC_EBCIMR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIMR) Access Error [3:0] */
+#define DMAC_EBCIMR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIMR) Access Error [3:0] */
+/* -------- DMAC_EBCISR : (DMAC Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. -------- */
+#define DMAC_EBCISR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCISR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCISR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCISR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCISR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCISR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCISR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCISR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCISR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCISR) Access Error [3:0] */
+#define DMAC_EBCISR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCISR) Access Error [3:0] */
+#define DMAC_EBCISR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCISR) Access Error [3:0] */
+#define DMAC_EBCISR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCISR) Access Error [3:0] */
+/* -------- DMAC_CHER : (DMAC Offset: 0x028) DMAC Channel Handler Enable Register -------- */
+#define DMAC_CHER_ENA0 (0x1u << 0) /**< \brief (DMAC_CHER) Enable [3:0] */
+#define DMAC_CHER_ENA1 (0x1u << 1) /**< \brief (DMAC_CHER) Enable [3:0] */
+#define DMAC_CHER_ENA2 (0x1u << 2) /**< \brief (DMAC_CHER) Enable [3:0] */
+#define DMAC_CHER_ENA3 (0x1u << 3) /**< \brief (DMAC_CHER) Enable [3:0] */
+#define DMAC_CHER_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHER) Suspend [3:0] */
+#define DMAC_CHER_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHER) Suspend [3:0] */
+#define DMAC_CHER_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHER) Suspend [3:0] */
+#define DMAC_CHER_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHER) Suspend [3:0] */
+#define DMAC_CHER_KEEP0 (0x1u << 24) /**< \brief (DMAC_CHER) Keep on [3:0] */
+#define DMAC_CHER_KEEP1 (0x1u << 25) /**< \brief (DMAC_CHER) Keep on [3:0] */
+#define DMAC_CHER_KEEP2 (0x1u << 26) /**< \brief (DMAC_CHER) Keep on [3:0] */
+#define DMAC_CHER_KEEP3 (0x1u << 27) /**< \brief (DMAC_CHER) Keep on [3:0] */
+/* -------- DMAC_CHDR : (DMAC Offset: 0x02C) DMAC Channel Handler Disable Register -------- */
+#define DMAC_CHDR_DIS0 (0x1u << 0) /**< \brief (DMAC_CHDR) Disable [3:0] */
+#define DMAC_CHDR_DIS1 (0x1u << 1) /**< \brief (DMAC_CHDR) Disable [3:0] */
+#define DMAC_CHDR_DIS2 (0x1u << 2) /**< \brief (DMAC_CHDR) Disable [3:0] */
+#define DMAC_CHDR_DIS3 (0x1u << 3) /**< \brief (DMAC_CHDR) Disable [3:0] */
+#define DMAC_CHDR_RES0 (0x1u << 8) /**< \brief (DMAC_CHDR) Resume [3:0] */
+#define DMAC_CHDR_RES1 (0x1u << 9) /**< \brief (DMAC_CHDR) Resume [3:0] */
+#define DMAC_CHDR_RES2 (0x1u << 10) /**< \brief (DMAC_CHDR) Resume [3:0] */
+#define DMAC_CHDR_RES3 (0x1u << 11) /**< \brief (DMAC_CHDR) Resume [3:0] */
+/* -------- DMAC_CHSR : (DMAC Offset: 0x030) DMAC Channel Handler Status Register -------- */
+#define DMAC_CHSR_ENA0 (0x1u << 0) /**< \brief (DMAC_CHSR) Enable [3:0] */
+#define DMAC_CHSR_ENA1 (0x1u << 1) /**< \brief (DMAC_CHSR) Enable [3:0] */
+#define DMAC_CHSR_ENA2 (0x1u << 2) /**< \brief (DMAC_CHSR) Enable [3:0] */
+#define DMAC_CHSR_ENA3 (0x1u << 3) /**< \brief (DMAC_CHSR) Enable [3:0] */
+#define DMAC_CHSR_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHSR) Suspend [3:0] */
+#define DMAC_CHSR_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHSR) Suspend [3:0] */
+#define DMAC_CHSR_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHSR) Suspend [3:0] */
+#define DMAC_CHSR_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHSR) Suspend [3:0] */
+#define DMAC_CHSR_EMPT0 (0x1u << 16) /**< \brief (DMAC_CHSR) Empty [3:0] */
+#define DMAC_CHSR_EMPT1 (0x1u << 17) /**< \brief (DMAC_CHSR) Empty [3:0] */
+#define DMAC_CHSR_EMPT2 (0x1u << 18) /**< \brief (DMAC_CHSR) Empty [3:0] */
+#define DMAC_CHSR_EMPT3 (0x1u << 19) /**< \brief (DMAC_CHSR) Empty [3:0] */
+#define DMAC_CHSR_STAL0 (0x1u << 24) /**< \brief (DMAC_CHSR) Stalled [3:0] */
+#define DMAC_CHSR_STAL1 (0x1u << 25) /**< \brief (DMAC_CHSR) Stalled [3:0] */
+#define DMAC_CHSR_STAL2 (0x1u << 26) /**< \brief (DMAC_CHSR) Stalled [3:0] */
+#define DMAC_CHSR_STAL3 (0x1u << 27) /**< \brief (DMAC_CHSR) Stalled [3:0] */
+/* -------- DMAC_SADDR : (DMAC Offset: N/A) DMAC Channel Source Address Register -------- */
+#define DMAC_SADDR_SADDR_Pos 0
+#define DMAC_SADDR_SADDR_Msk (0xffffffffu << DMAC_SADDR_SADDR_Pos) /**< \brief (DMAC_SADDR) Channel x Source Address */
+#define DMAC_SADDR_SADDR(value) ((DMAC_SADDR_SADDR_Msk & ((value) << DMAC_SADDR_SADDR_Pos)))
+/* -------- DMAC_DADDR : (DMAC Offset: N/A) DMAC Channel Destination Address Register -------- */
+#define DMAC_DADDR_DADDR_Pos 0
+#define DMAC_DADDR_DADDR_Msk (0xffffffffu << DMAC_DADDR_DADDR_Pos) /**< \brief (DMAC_DADDR) Channel x Destination Address */
+#define DMAC_DADDR_DADDR(value) ((DMAC_DADDR_DADDR_Msk & ((value) << DMAC_DADDR_DADDR_Pos)))
+/* -------- DMAC_DSCR : (DMAC Offset: N/A) DMAC Channel Descriptor Address Register -------- */
+#define DMAC_DSCR_DSCR_Pos 2
+#define DMAC_DSCR_DSCR_Msk (0x3fffffffu << DMAC_DSCR_DSCR_Pos) /**< \brief (DMAC_DSCR) Buffer Transfer Descriptor Address */
+#define DMAC_DSCR_DSCR(value) ((DMAC_DSCR_DSCR_Msk & ((value) << DMAC_DSCR_DSCR_Pos)))
+/* -------- DMAC_CTRLA : (DMAC Offset: N/A) DMAC Channel Control A Register -------- */
+#define DMAC_CTRLA_BTSIZE_Pos 0
+#define DMAC_CTRLA_BTSIZE_Msk (0xffffu << DMAC_CTRLA_BTSIZE_Pos) /**< \brief (DMAC_CTRLA) Buffer Transfer Size */
+#define DMAC_CTRLA_BTSIZE(value) ((DMAC_CTRLA_BTSIZE_Msk & ((value) << DMAC_CTRLA_BTSIZE_Pos)))
+#define DMAC_CTRLA_SCSIZE_Pos 16
+#define DMAC_CTRLA_SCSIZE_Msk (0x7u << DMAC_CTRLA_SCSIZE_Pos) /**< \brief (DMAC_CTRLA) Source Chunk Transfer Size. */
+#define DMAC_CTRLA_SCSIZE_CHK_1 (0x0u << 16) /**< \brief (DMAC_CTRLA) 1 data transferred */
+#define DMAC_CTRLA_SCSIZE_CHK_4 (0x1u << 16) /**< \brief (DMAC_CTRLA) 4 data transferred */
+#define DMAC_CTRLA_SCSIZE_CHK_8 (0x2u << 16) /**< \brief (DMAC_CTRLA) 8 data transferred */
+#define DMAC_CTRLA_SCSIZE_CHK_16 (0x3u << 16) /**< \brief (DMAC_CTRLA) 16 data transferred */
+#define DMAC_CTRLA_SCSIZE_CHK_32 (0x4u << 16) /**< \brief (DMAC_CTRLA) 32 data transferred */
+#define DMAC_CTRLA_SCSIZE_CHK_64 (0x5u << 16) /**< \brief (DMAC_CTRLA) 64 data transferred */
+#define DMAC_CTRLA_SCSIZE_CHK_128 (0x6u << 16) /**< \brief (DMAC_CTRLA) 128 data transferred */
+#define DMAC_CTRLA_SCSIZE_CHK_256 (0x7u << 16) /**< \brief (DMAC_CTRLA) 256 data transferred */
+#define DMAC_CTRLA_DCSIZE_Pos 20
+#define DMAC_CTRLA_DCSIZE_Msk (0x7u << DMAC_CTRLA_DCSIZE_Pos) /**< \brief (DMAC_CTRLA) Destination Chunk Transfer Size */
+#define DMAC_CTRLA_DCSIZE_CHK_1 (0x0u << 20) /**< \brief (DMAC_CTRLA) 1 data transferred */
+#define DMAC_CTRLA_DCSIZE_CHK_4 (0x1u << 20) /**< \brief (DMAC_CTRLA) 4 data transferred */
+#define DMAC_CTRLA_DCSIZE_CHK_8 (0x2u << 20) /**< \brief (DMAC_CTRLA) 8 data transferred */
+#define DMAC_CTRLA_DCSIZE_CHK_16 (0x3u << 20) /**< \brief (DMAC_CTRLA) 16 data transferred */
+#define DMAC_CTRLA_DCSIZE_CHK_32 (0x4u << 20) /**< \brief (DMAC_CTRLA) 32 data transferred */
+#define DMAC_CTRLA_DCSIZE_CHK_64 (0x5u << 20) /**< \brief (DMAC_CTRLA) 64 data transferred */
+#define DMAC_CTRLA_DCSIZE_CHK_128 (0x6u << 20) /**< \brief (DMAC_CTRLA) 128 data transferred */
+#define DMAC_CTRLA_DCSIZE_CHK_256 (0x7u << 20) /**< \brief (DMAC_CTRLA) 256 data transferred */
+#define DMAC_CTRLA_SRC_WIDTH_Pos 24
+#define DMAC_CTRLA_SRC_WIDTH_Msk (0x3u << DMAC_CTRLA_SRC_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Source */
+#define DMAC_CTRLA_SRC_WIDTH_BYTE (0x0u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */
+#define DMAC_CTRLA_SRC_WIDTH_HALF_WORD (0x1u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */
+#define DMAC_CTRLA_SRC_WIDTH_WORD (0x2u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */
+#define DMAC_CTRLA_DST_WIDTH_Pos 28
+#define DMAC_CTRLA_DST_WIDTH_Msk (0x3u << DMAC_CTRLA_DST_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Destination */
+#define DMAC_CTRLA_DST_WIDTH_BYTE (0x0u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */
+#define DMAC_CTRLA_DST_WIDTH_HALF_WORD (0x1u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */
+#define DMAC_CTRLA_DST_WIDTH_WORD (0x2u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */
+#define DMAC_CTRLA_DONE (0x1u << 31) /**< \brief (DMAC_CTRLA) */
+/* -------- DMAC_CTRLB : (DMAC Offset: N/A) DMAC Channel Control B Register -------- */
+#define DMAC_CTRLB_SRC_DSCR (0x1u << 16) /**< \brief (DMAC_CTRLB) Source Address Descriptor */
+#define DMAC_CTRLB_SRC_DSCR_FETCH_FROM_MEM (0x0u << 16) /**< \brief (DMAC_CTRLB) Source address is updated when the descriptor is fetched from the memory. */
+#define DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE (0x1u << 16) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the source. */
+#define DMAC_CTRLB_DST_DSCR (0x1u << 20) /**< \brief (DMAC_CTRLB) Destination Address Descriptor */
+#define DMAC_CTRLB_DST_DSCR_FETCH_FROM_MEM (0x0u << 20) /**< \brief (DMAC_CTRLB) Destination address is updated when the descriptor is fetched from the memory. */
+#define DMAC_CTRLB_DST_DSCR_FETCH_DISABLE (0x1u << 20) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the destination. */
+#define DMAC_CTRLB_FC_Pos 21
+#define DMAC_CTRLB_FC_Msk (0x7u << DMAC_CTRLB_FC_Pos) /**< \brief (DMAC_CTRLB) Flow Control */
+#define DMAC_CTRLB_FC_MEM2MEM_DMA_FC (0x0u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Memory Transfer DMAC is flow controller */
+#define DMAC_CTRLB_FC_MEM2PER_DMA_FC (0x1u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Peripheral Transfer DMAC is flow controller */
+#define DMAC_CTRLB_FC_PER2MEM_DMA_FC (0x2u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Memory Transfer DMAC is flow controller */
+#define DMAC_CTRLB_FC_PER2PER_DMA_FC (0x3u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Peripheral Transfer DMAC is flow controller */
+#define DMAC_CTRLB_SRC_INCR_Pos 24
+#define DMAC_CTRLB_SRC_INCR_Msk (0x3u << DMAC_CTRLB_SRC_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Source */
+#define DMAC_CTRLB_SRC_INCR_INCREMENTING (0x0u << 24) /**< \brief (DMAC_CTRLB) The source address is incremented */
+#define DMAC_CTRLB_SRC_INCR_DECREMENTING (0x1u << 24) /**< \brief (DMAC_CTRLB) The source address is decremented */
+#define DMAC_CTRLB_SRC_INCR_FIXED (0x2u << 24) /**< \brief (DMAC_CTRLB) The source address remains unchanged */
+#define DMAC_CTRLB_DST_INCR_Pos 28
+#define DMAC_CTRLB_DST_INCR_Msk (0x3u << DMAC_CTRLB_DST_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Destination */
+#define DMAC_CTRLB_DST_INCR_INCREMENTING (0x0u << 28) /**< \brief (DMAC_CTRLB) The destination address is incremented */
+#define DMAC_CTRLB_DST_INCR_DECREMENTING (0x1u << 28) /**< \brief (DMAC_CTRLB) The destination address is decremented */
+#define DMAC_CTRLB_DST_INCR_FIXED (0x2u << 28) /**< \brief (DMAC_CTRLB) The destination address remains unchanged */
+#define DMAC_CTRLB_IEN (0x1u << 30) /**< \brief (DMAC_CTRLB) */
+/* -------- DMAC_CFG : (DMAC Offset: N/A) DMAC Channel Configuration Register -------- */
+#define DMAC_CFG_SRC_PER_Pos 0
+#define DMAC_CFG_SRC_PER_Msk (0xfu << DMAC_CFG_SRC_PER_Pos) /**< \brief (DMAC_CFG) Source with Peripheral identifier */
+#define DMAC_CFG_SRC_PER(value) ((DMAC_CFG_SRC_PER_Msk & ((value) << DMAC_CFG_SRC_PER_Pos)))
+#define DMAC_CFG_DST_PER_Pos 4
+#define DMAC_CFG_DST_PER_Msk (0xfu << DMAC_CFG_DST_PER_Pos) /**< \brief (DMAC_CFG) Destination with Peripheral identifier */
+#define DMAC_CFG_DST_PER(value) ((DMAC_CFG_DST_PER_Msk & ((value) << DMAC_CFG_DST_PER_Pos)))
+#define DMAC_CFG_SRC_H2SEL (0x1u << 9) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Source */
+#define DMAC_CFG_SRC_H2SEL_SW (0x0u << 9) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */
+#define DMAC_CFG_SRC_H2SEL_HW (0x1u << 9) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */
+#define DMAC_CFG_DST_H2SEL (0x1u << 13) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Destination */
+#define DMAC_CFG_DST_H2SEL_SW (0x0u << 13) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */
+#define DMAC_CFG_DST_H2SEL_HW (0x1u << 13) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */
+#define DMAC_CFG_SOD (0x1u << 16) /**< \brief (DMAC_CFG) Stop On Done */
+#define DMAC_CFG_SOD_DISABLE (0x0u << 16) /**< \brief (DMAC_CFG) STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. */
+#define DMAC_CFG_SOD_ENABLE (0x1u << 16) /**< \brief (DMAC_CFG) STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. */
+#define DMAC_CFG_LOCK_IF (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock */
+#define DMAC_CFG_LOCK_IF_DISABLE (0x0u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is disabled */
+#define DMAC_CFG_LOCK_IF_ENABLE (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is enabled */
+#define DMAC_CFG_LOCK_B (0x1u << 21) /**< \brief (DMAC_CFG) Bus Lock */
+#define DMAC_CFG_LOCK_B_DISABLE (0x0u << 21) /**< \brief (DMAC_CFG) AHB Bus Locking capability is disabled. */
+#define DMAC_CFG_LOCK_IF_L (0x1u << 22) /**< \brief (DMAC_CFG) Master Interface Arbiter Lock */
+#define DMAC_CFG_LOCK_IF_L_CHUNK (0x0u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a chunk transfer. */
+#define DMAC_CFG_LOCK_IF_L_BUFFER (0x1u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a buffer transfer. */
+#define DMAC_CFG_AHB_PROT_Pos 24
+#define DMAC_CFG_AHB_PROT_Msk (0x7u << DMAC_CFG_AHB_PROT_Pos) /**< \brief (DMAC_CFG) AHB Protection */
+#define DMAC_CFG_AHB_PROT(value) ((DMAC_CFG_AHB_PROT_Msk & ((value) << DMAC_CFG_AHB_PROT_Pos)))
+#define DMAC_CFG_FIFOCFG_Pos 28
+#define DMAC_CFG_FIFOCFG_Msk (0x3u << DMAC_CFG_FIFOCFG_Pos) /**< \brief (DMAC_CFG) FIFO Configuration */
+#define DMAC_CFG_FIFOCFG_ALAP_CFG (0x0u << 28) /**< \brief (DMAC_CFG) The largest defined length AHB burst is performed on the destination AHB interface. */
+#define DMAC_CFG_FIFOCFG_HALF_CFG (0x1u << 28) /**< \brief (DMAC_CFG) When half FIFO size is available/filled, a source/destination request is serviced. */
+#define DMAC_CFG_FIFOCFG_ASAP_CFG (0x2u << 28) /**< \brief (DMAC_CFG) When there is enough space/data available to perform a single AHB access, then the request is serviced. */
+/* -------- DMAC_WPMR : (DMAC Offset: 0x1E4) DMAC Write Protect Mode Register -------- */
+#define DMAC_WPMR_WPEN (0x1u << 0) /**< \brief (DMAC_WPMR) Write Protect Enable */
+#define DMAC_WPMR_WPKEY_Pos 8
+#define DMAC_WPMR_WPKEY_Msk (0xffffffu << DMAC_WPMR_WPKEY_Pos) /**< \brief (DMAC_WPMR) Write Protect KEY */
+#define DMAC_WPMR_WPKEY(value) ((DMAC_WPMR_WPKEY_Msk & ((value) << DMAC_WPMR_WPKEY_Pos)))
+/* -------- DMAC_WPSR : (DMAC Offset: 0x1E8) DMAC Write Protect Status Register -------- */
+#define DMAC_WPSR_WPVS (0x1u << 0) /**< \brief (DMAC_WPSR) Write Protect Violation Status */
+#define DMAC_WPSR_WPVSRC_Pos 8
+#define DMAC_WPSR_WPVSRC_Msk (0xffffu << DMAC_WPSR_WPVSRC_Pos) /**< \brief (DMAC_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3U_DMAC_COMPONENT_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/component/efc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/component/efc.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,89 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U_EFC_COMPONENT_
+#define _SAM3U_EFC_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_EFC Embedded Flash Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Efc hardware registers */
+typedef struct {
+ RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */
+ WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */
+ RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */
+ RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */
+} Efc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
+#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */
+#define EEFC_FMR_FWS_Pos 8
+#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */
+#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))
+#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */
+#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */
+/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
+#define EEFC_FCR_FCMD_Pos 0
+#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */
+#define EEFC_FCR_FCMD_GETD (0x0u << 0) /**< \brief (EEFC_FCR) Get Flash Descriptor */
+#define EEFC_FCR_FCMD_WP (0x1u << 0) /**< \brief (EEFC_FCR) Write page */
+#define EEFC_FCR_FCMD_WPL (0x2u << 0) /**< \brief (EEFC_FCR) Write page and lock */
+#define EEFC_FCR_FCMD_EWP (0x3u << 0) /**< \brief (EEFC_FCR) Erase page and write page */
+#define EEFC_FCR_FCMD_EWPL (0x4u << 0) /**< \brief (EEFC_FCR) Erase page and write page then lock */
+#define EEFC_FCR_FCMD_EA (0x5u << 0) /**< \brief (EEFC_FCR) Erase all */
+#define EEFC_FCR_FCMD_SLB (0x8u << 0) /**< \brief (EEFC_FCR) Set Lock Bit */
+#define EEFC_FCR_FCMD_CLB (0x9u << 0) /**< \brief (EEFC_FCR) Clear Lock Bit */
+#define EEFC_FCR_FCMD_GLB (0xAu << 0) /**< \brief (EEFC_FCR) Get Lock Bit */
+#define EEFC_FCR_FCMD_SGPB (0xBu << 0) /**< \brief (EEFC_FCR) Set GPNVM Bit */
+#define EEFC_FCR_FCMD_CGPB (0xCu << 0) /**< \brief (EEFC_FCR) Clear GPNVM Bit */
+#define EEFC_FCR_FCMD_GGPB (0xDu << 0) /**< \brief (EEFC_FCR) Get GPNVM Bit */
+#define EEFC_FCR_FCMD_STUI (0xEu << 0) /**< \brief (EEFC_FCR) Start Read Unique Identifier */
+#define EEFC_FCR_FCMD_SPUI (0xFu << 0) /**< \brief (EEFC_FCR) Stop Read Unique Identifier */
+#define EEFC_FCR_FARG_Pos 8
+#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */
+#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))
+#define EEFC_FCR_FKEY_Pos 24
+#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */
+#define EEFC_FCR_FKEY_PASSWD (0x5Au << 24) /**< \brief (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */
+/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
+#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */
+#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */
+#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */
+/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
+#define EEFC_FRR_FVALUE_Pos 0
+#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */
+
+/*@}*/
+
+
+#endif /* _SAM3U_EFC_COMPONENT_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/component/gpbr.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/component/gpbr.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,53 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U_GPBR_COMPONENT_
+#define _SAM3U_GPBR_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */
+/* ============================================================================= */
+/** \addtogroup SAM3U_GPBR General Purpose Backup Register */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Gpbr hardware registers */
+typedef struct {
+ RwReg SYS_GPBR[4]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */
+} Gpbr;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SYS_GPBR[4] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */
+#define SYS_GPBR_GPBR_VALUE_Pos 0
+#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[4]) Value of GPBR x */
+#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3U_GPBR_COMPONENT_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/component/hsmci.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/component/hsmci.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,337 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U_HSMCI_COMPONENT_
+#define _SAM3U_HSMCI_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3U_HSMCI High Speed MultiMedia Card Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Hsmci hardware registers */
+typedef struct {
+ WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */
+ RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */
+ RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */
+ RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */
+ RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */
+ WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */
+ RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */
+ RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */
+ RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */
+ RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */
+ WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */
+ RoReg Reserved1[2];
+ RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */
+ WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */
+ WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */
+ RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */
+ RwReg HSMCI_DMA; /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */
+ RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */
+ RoReg Reserved2[35];
+ RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */
+ RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */
+ RoReg Reserved3[69];
+ RwReg HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */
+} Hsmci;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */
+#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */
+#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */
+#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */
+#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */
+#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */
+/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */
+#define HSMCI_MR_CLKDIV_Pos 0
+#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */
+#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))
+#define HSMCI_MR_PWSDIV_Pos 8
+#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */
+#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))
+#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) */
+#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) */
+#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */
+#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */
+/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */
+#define HSMCI_DTOR_DTOCYC_Pos 0
+#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */
+#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))
+#define HSMCI_DTOR_DTOMUL_Pos 4
+#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */
+#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */
+#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */
+#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */
+#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */
+#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */
+#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */
+#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */
+#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */
+/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */
+#define HSMCI_SDCR_SDCSEL_Pos 0
+#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */
+#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */
+#define HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) - */
+#define HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */
+#define HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */
+#define HSMCI_SDCR_SDCBUS_Pos 6
+#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */
+#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */
+#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */
+#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */
+/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */
+#define HSMCI_ARGR_ARG_Pos 0
+#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */
+#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))
+/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */
+#define HSMCI_CMDR_CMDNB_Pos 0
+#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */
+#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))
+#define HSMCI_CMDR_RSPTYP_Pos 6
+#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */
+#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */
+#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */
+#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */
+#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */
+#define HSMCI_CMDR_SPCMD_Pos 8
+#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */
+#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */
+#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */
+#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */
+#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */
+#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */
+#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */
+#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */
+#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */
+#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */
+#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */
+#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */
+#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */
+#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */
+#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */
+#define HSMCI_CMDR_TRCMD_Pos 16
+#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */
+#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */
+#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */
+#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */
+#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */
+#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */
+#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */
+#define HSMCI_CMDR_TRTYP_Pos 19
+#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */
+#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */
+#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */
+#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */
+#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */
+#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */
+#define HSMCI_CMDR_IOSPCMD_Pos 24
+#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */
+#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */
+#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */
+#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */
+#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */
+#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */
+#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */
+#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */
+/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */
+#define HSMCI_BLKR_BCNT_Pos 0
+#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */
+#define HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */
+#define HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */
+#define HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */
+#define HSMCI_BLKR_BLKLEN_Pos 16
+#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */
+#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))
+/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */
+#define HSMCI_CSTOR_CSTOCYC_Pos 0
+#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */
+#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))
+#define HSMCI_CSTOR_CSTOMUL_Pos 4
+#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */
+#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */
+#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */
+#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */
+#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */
+#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */
+#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */
+#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */
+#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */
+/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */
+#define HSMCI_RSPR_RSP_Pos 0
+#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */
+/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */
+#define HSMCI_RDR_DATA_Pos 0
+#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */
+/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */
+#define HSMCI_TDR_DATA_Pos 0
+#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */
+#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))
+/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */
+#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */
+#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */
+#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */
+#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */
+#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */
+#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */
+#define HSMCI_SR_MCI_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) */
+#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */
+#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */
+#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */
+#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */
+#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */
+#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */
+#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */
+#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */
+#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */
+#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */
+#define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error */
+#define HSMCI_SR_DMADONE (0x1u << 25) /**< \brief (HSMCI_SR) DMA Transfer done */
+#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */
+#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */
+#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */
+#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */
+#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */
+#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */
+/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */
+#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */
+#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */
+#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */
+#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */
+#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */
+#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */
+#define HSMCI_IER_MCI_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) */
+#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */
+#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */
+#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */
+#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */
+#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */
+#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */
+#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */
+#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */
+#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */
+#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */
+#define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */
+#define HSMCI_IER_DMADONE (0x1u << 25) /**< \brief (HSMCI_IER) DMA Transfer completed Interrupt Enable */
+#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */
+#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */
+#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */
+#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */
+#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */
+#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */
+/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */
+#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */
+#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */
+#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */
+#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */
+#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */
+#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */
+#define HSMCI_IDR_MCI_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) */
+#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */
+#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */
+#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */
+#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */
+#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */
+#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */
+#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */
+#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */
+#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */
+#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */
+#define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */
+#define HSMCI_IDR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IDR) DMA Transfer completed Interrupt Disable */
+#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */
+#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */
+#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */
+#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */
+#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */
+#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */
+/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */
+#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */
+#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */
+#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */
+#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */
+#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */
+#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */
+#define HSMCI_IMR_MCI_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) */
+#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */
+#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */
+#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */
+#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */
+#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */
+#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */
+#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */
+#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */
+#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */
+#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */
+#define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */
+#define HSMCI_IMR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IMR) DMA Transfer Completed Interrupt Mask */
+#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */
+#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */
+#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */
+#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */
+#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */
+#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */
+/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */
+#define HSMCI_DMA_OFFSET_Pos 0
+#define HSMCI_DMA_OFFSET_Msk (0x3u << HSMCI_DMA_OFFSET_Pos) /**< \brief (HSMCI_DMA) DMA Write Buffer Offset */
+#define HSMCI_DMA_OFFSET(value) ((HSMCI_DMA_OFFSET_Msk & ((value) << HSMCI_DMA_OFFSET_Pos)))
+#define HSMCI_DMA_CHKSIZE (0x1u << 4) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */
+#define HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */
+#define HSMCI_DMA_CHKSIZE_4 (0x1u << 4) /**< \brief (HSMCI_DMA) 4 data available */
+#define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */
+#define HSMCI_DMA_ROPT (0x1u << 12) /**< \brief (HSMCI_DMA) Read Optimization with padding */
+/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */
+#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */
+#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */
+#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */
+#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */
+/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */
+#define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */
+#define HSMCI_WPMR_WP_KEY_Pos 8
+#define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */
+#define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos)))
+/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */
+#define HSMCI_WPSR_WP_VS_Pos 0
+#define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */
+#define HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */
+#define HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */
+#define HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */
+#define HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */
+#define HSMCI_WPSR_WP_VSRC_Pos 8
+#define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */
+/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */
+#define HSMCI_FIFO_DATA_Pos 0
+#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */
+#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3U_HSMCI_COMPONENT_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/component/matrix.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/component/matrix.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,269 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U_MATRIX_COMPONENT_
+#define _SAM3U_MATRIX_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */
+/* ============================================================================= */
+/** \addtogroup SAM3U_MATRIX AHB Bus Matrix */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Matrix hardware registers */
+typedef struct {
+ RwReg MATRIX_MCFG[5]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */
+ RoReg Reserved1[11];
+ RwReg MATRIX_SCFG[10]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */
+ RoReg Reserved2[6];
+ RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */
+ RoReg Reserved3[1];
+ RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */
+ RoReg Reserved4[1];
+ RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */
+ RoReg Reserved5[1];
+ RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */
+ RoReg Reserved6[1];
+ RwReg MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */
+ RoReg Reserved7[1];
+ RwReg MATRIX_PRAS5; /**< \brief (Matrix Offset: 0x00A8) Priority Register A for Slave 5 */
+ RoReg Reserved8[1];
+ RwReg MATRIX_PRAS6; /**< \brief (Matrix Offset: 0x00B0) Priority Register A for Slave 6 */
+ RoReg Reserved9[1];
+ RwReg MATRIX_PRAS7; /**< \brief (Matrix Offset: 0x00B8) Priority Register A for Slave 7 */
+ RoReg Reserved10[1];
+ RwReg MATRIX_PRAS8; /**< \brief (Matrix Offset: 0x00C0) Priority Register A for Slave 8 */
+ RoReg Reserved11[1];
+ RwReg MATRIX_PRAS9; /**< \brief (Matrix Offset: 0x00C8) Priority Register A for Slave 9 */
+ RoReg Reserved12[1];
+ RoReg Reserved13[12];
+ RwReg MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */
+ RoReg Reserved14[56];
+ RwReg MATRIX_WPMR; /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */
+ RoReg MATRIX_WPSR; /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */
+} Matrix;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- MATRIX_MCFG[5] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */
+#define MATRIX_MCFG_ULBT_Pos 0
+#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[5]) Undefined Length Burst Type */
+#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))
+/* -------- MATRIX_SCFG[10] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
+#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[10]) Maximum Number of Allowed Cycles for a Burst */
+#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[10]) Default Master Type */
+#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
+#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[10]) Fixed Default Master */
+#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
+#define MATRIX_SCFG_ARBT_Pos 24
+#define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[10]) Arbitration Type */
+#define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos)))
+/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */
+#define MATRIX_PRAS0_M0PR_Pos 0
+#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */
+#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))
+#define MATRIX_PRAS0_M1PR_Pos 4
+#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */
+#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))
+#define MATRIX_PRAS0_M2PR_Pos 8
+#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */
+#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))
+#define MATRIX_PRAS0_M3PR_Pos 12
+#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */
+#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))
+#define MATRIX_PRAS0_M4PR_Pos 16
+#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */
+#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos)))
+/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */
+#define MATRIX_PRAS1_M0PR_Pos 0
+#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */
+#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))
+#define MATRIX_PRAS1_M1PR_Pos 4
+#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */
+#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))
+#define MATRIX_PRAS1_M2PR_Pos 8
+#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */
+#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))
+#define MATRIX_PRAS1_M3PR_Pos 12
+#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */
+#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))
+#define MATRIX_PRAS1_M4PR_Pos 16
+#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */
+#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos)))
+/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */
+#define MATRIX_PRAS2_M0PR_Pos 0
+#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */
+#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))
+#define MATRIX_PRAS2_M1PR_Pos 4
+#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */
+#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))
+#define MATRIX_PRAS2_M2PR_Pos 8
+#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */
+#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))
+#define MATRIX_PRAS2_M3PR_Pos 12
+#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */
+#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))
+#define MATRIX_PRAS2_M4PR_Pos 16
+#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */
+#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos)))
+/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */
+#define MATRIX_PRAS3_M0PR_Pos 0
+#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */
+#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))
+#define MATRIX_PRAS3_M1PR_Pos 4
+#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */
+#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))
+#define MATRIX_PRAS3_M2PR_Pos 8
+#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */
+#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))
+#define MATRIX_PRAS3_M3PR_Pos 12
+#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */
+#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))
+#define MATRIX_PRAS3_M4PR_Pos 16
+#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */
+#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos)))
+/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */
+#define MATRIX_PRAS4_M0PR_Pos 0
+#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */
+#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos)))
+#define MATRIX_PRAS4_M1PR_Pos 4
+#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */
+#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos)))
+#define MATRIX_PRAS4_M2PR_Pos 8
+#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */
+#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos)))
+#define MATRIX_PRAS4_M3PR_Pos 12
+#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */
+#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos)))
+#define MATRIX_PRAS4_M4PR_Pos 16
+#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */
+#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos)))
+/* -------- MATRIX_PRAS5 : (MATRIX Offset: 0x00A8) Priority Register A for Slave 5 -------- */
+#define MATRIX_PRAS5_M0PR_Pos 0
+#define MATRIX_PRAS5_M0PR_Msk (0x3u << MATRIX_PRAS5_M0PR_Pos) /**< \brief (MATRIX_PRAS5) Master 0 Priority */
+#define MATRIX_PRAS5_M0PR(value) ((MATRIX_PRAS5_M0PR_Msk & ((value) << MATRIX_PRAS5_M0PR_Pos)))
+#define MATRIX_PRAS5_M1PR_Pos 4
+#define MATRIX_PRAS5_M1PR_Msk (0x3u << MATRIX_PRAS5_M1PR_Pos) /**< \brief (MATRIX_PRAS5) Master 1 Priority */
+#define MATRIX_PRAS5_M1PR(value) ((MATRIX_PRAS5_M1PR_Msk & ((value) << MATRIX_PRAS5_M1PR_Pos)))
+#define MATRIX_PRAS5_M2PR_Pos 8
+#define MATRIX_PRAS5_M2PR_Msk (0x3u << MATRIX_PRAS5_M2PR_Pos) /**< \brief (MATRIX_PRAS5) Master 2 Priority */
+#define MATRIX_PRAS5_M2PR(value) ((MATRIX_PRAS5_M2PR_Msk & ((value) << MATRIX_PRAS5_M2PR_Pos)))
+#define MATRIX_PRAS5_M3PR_Pos 12
+#define MATRIX_PRAS5_M3PR_Msk (0x3u << MATRIX_PRAS5_M3PR_Pos) /**< \brief (MATRIX_PRAS5) Master 3 Priority */
+#define MATRIX_PRAS5_M3PR(value) ((MATRIX_PRAS5_M3PR_Msk & ((value) << MATRIX_PRAS5_M3PR_Pos)))
+#define MATRIX_PRAS5_M4PR_Pos 16
+#define MATRIX_PRAS5_M4PR_Msk (0x3u << MATRIX_PRAS5_M4PR_Pos) /**< \brief (MATRIX_PRAS5) Master 4 Priority */
+#define MATRIX_PRAS5_M4PR(value) ((MATRIX_PRAS5_M4PR_Msk & ((value) << MATRIX_PRAS5_M4PR_Pos)))
+/* -------- MATRIX_PRAS6 : (MATRIX Offset: 0x00B0) Priority Register A for Slave 6 -------- */
+#define MATRIX_PRAS6_M0PR_Pos 0
+#define MATRIX_PRAS6_M0PR_Msk (0x3u << MATRIX_PRAS6_M0PR_Pos) /**< \brief (MATRIX_PRAS6) Master 0 Priority */
+#define MATRIX_PRAS6_M0PR(value) ((MATRIX_PRAS6_M0PR_Msk & ((value) << MATRIX_PRAS6_M0PR_Pos)))
+#define MATRIX_PRAS6_M1PR_Pos 4
+#define MATRIX_PRAS6_M1PR_Msk (0x3u << MATRIX_PRAS6_M1PR_Pos) /**< \brief (MATRIX_PRAS6) Master 1 Priority */
+#define MATRIX_PRAS6_M1PR(value) ((MATRIX_PRAS6_M1PR_Msk & ((value) << MATRIX_PRAS6_M1PR_Pos)))
+#define MATRIX_PRAS6_M2PR_Pos 8
+#define MATRIX_PRAS6_M2PR_Msk (0x3u << MATRIX_PRAS6_M2PR_Pos) /**< \brief (MATRIX_PRAS6) Master 2 Priority */
+#define MATRIX_PRAS6_M2PR(value) ((MATRIX_PRAS6_M2PR_Msk & ((value) << MATRIX_PRAS6_M2PR_Pos)))
+#define MATRIX_PRAS6_M3PR_Pos 12
+#define MATRIX_PRAS6_M3PR_Msk (0x3u << MATRIX_PRAS6_M3PR_Pos) /**< \brief (MATRIX_PRAS6) Master 3 Priority */
+#define MATRIX_PRAS6_M3PR(value) ((MATRIX_PRAS6_M3PR_Msk & ((value) << MATRIX_PRAS6_M3PR_Pos)))
+#define MATRIX_PRAS6_M4PR_Pos 16
+#define MATRIX_PRAS6_M4PR_Msk (0x3u << MATRIX_PRAS6_M4PR_Pos) /**< \brief (MATRIX_PRAS6) Master 4 Priority */
+#define MATRIX_PRAS6_M4PR(value) ((MATRIX_PRAS6_M4PR_Msk & ((value) << MATRIX_PRAS6_M4PR_Pos)))
+/* -------- MATRIX_PRAS7 : (MATRIX Offset: 0x00B8) Priority Register A for Slave 7 -------- */
+#define MATRIX_PRAS7_M0PR_Pos 0
+#define MATRIX_PRAS7_M0PR_Msk (0x3u << MATRIX_PRAS7_M0PR_Pos) /**< \brief (MATRIX_PRAS7) Master 0 Priority */
+#define MATRIX_PRAS7_M0PR(value) ((MATRIX_PRAS7_M0PR_Msk & ((value) << MATRIX_PRAS7_M0PR_Pos)))
+#define MATRIX_PRAS7_M1PR_Pos 4
+#define MATRIX_PRAS7_M1PR_Msk (0x3u << MATRIX_PRAS7_M1PR_Pos) /**< \brief (MATRIX_PRAS7) Master 1 Priority */
+#define MATRIX_PRAS7_M1PR(value) ((MATRIX_PRAS7_M1PR_Msk & ((value) << MATRIX_PRAS7_M1PR_Pos)))
+#define MATRIX_PRAS7_M2PR_Pos 8
+#define MATRIX_PRAS7_M2PR_Msk (0x3u << MATRIX_PRAS7_M2PR_Pos) /**< \brief (MATRIX_PRAS7) Master 2 Priority */
+#define MATRIX_PRAS7_M2PR(value) ((MATRIX_PRAS7_M2PR_Msk & ((value) << MATRIX_PRAS7_M2PR_Pos)))
+#define MATRIX_PRAS7_M3PR_Pos 12
+#define MATRIX_PRAS7_M3PR_Msk (0x3u << MATRIX_PRAS7_M3PR_Pos) /**< \brief (MATRIX_PRAS7) Master 3 Priority */
+#define MATRIX_PRAS7_M3PR(value) ((MATRIX_PRAS7_M3PR_Msk & ((value) << MATRIX_PRAS7_M3PR_Pos)))
+#define MATRIX_PRAS7_M4PR_Pos 16
+#define MATRIX_PRAS7_M4PR_Msk (0x3u << MATRIX_PRAS7_M4PR_Pos) /**< \brief (MATRIX_PRAS7) Master 4 Priority */
+#define MATRIX_PRAS7_M4PR(value) ((MATRIX_PRAS7_M4PR_Msk & ((value) << MATRIX_PRAS7_M4PR_Pos)))
+/* -------- MATRIX_PRAS8 : (MATRIX Offset: 0x00C0) Priority Register A for Slave 8 -------- */
+#define MATRIX_PRAS8_M0PR_Pos 0
+#define MATRIX_PRAS8_M0PR_Msk (0x3u << MATRIX_PRAS8_M0PR_Pos) /**< \brief (MATRIX_PRAS8) Master 0 Priority */
+#define MATRIX_PRAS8_M0PR(value) ((MATRIX_PRAS8_M0PR_Msk & ((value) << MATRIX_PRAS8_M0PR_Pos)))
+#define MATRIX_PRAS8_M1PR_Pos 4
+#define MATRIX_PRAS8_M1PR_Msk (0x3u << MATRIX_PRAS8_M1PR_Pos) /**< \brief (MATRIX_PRAS8) Master 1 Priority */
+#define MATRIX_PRAS8_M1PR(value) ((MATRIX_PRAS8_M1PR_Msk & ((value) << MATRIX_PRAS8_M1PR_Pos)))
+#define MATRIX_PRAS8_M2PR_Pos 8
+#define MATRIX_PRAS8_M2PR_Msk (0x3u << MATRIX_PRAS8_M2PR_Pos) /**< \brief (MATRIX_PRAS8) Master 2 Priority */
+#define MATRIX_PRAS8_M2PR(value) ((MATRIX_PRAS8_M2PR_Msk & ((value) << MATRIX_PRAS8_M2PR_Pos)))
+#define MATRIX_PRAS8_M3PR_Pos 12
+#define MATRIX_PRAS8_M3PR_Msk (0x3u << MATRIX_PRAS8_M3PR_Pos) /**< \brief (MATRIX_PRAS8) Master 3 Priority */
+#define MATRIX_PRAS8_M3PR(value) ((MATRIX_PRAS8_M3PR_Msk & ((value) << MATRIX_PRAS8_M3PR_Pos)))
+#define MATRIX_PRAS8_M4PR_Pos 16
+#define MATRIX_PRAS8_M4PR_Msk (0x3u << MATRIX_PRAS8_M4PR_Pos) /**< \brief (MATRIX_PRAS8) Master 4 Priority */
+#define MATRIX_PRAS8_M4PR(value) ((MATRIX_PRAS8_M4PR_Msk & ((value) << MATRIX_PRAS8_M4PR_Pos)))
+/* -------- MATRIX_PRAS9 : (MATRIX Offset: 0x00C8) Priority Register A for Slave 9 -------- */
+#define MATRIX_PRAS9_M0PR_Pos 0
+#define MATRIX_PRAS9_M0PR_Msk (0x3u << MATRIX_PRAS9_M0PR_Pos) /**< \brief (MATRIX_PRAS9) Master 0 Priority */
+#define MATRIX_PRAS9_M0PR(value) ((MATRIX_PRAS9_M0PR_Msk & ((value) << MATRIX_PRAS9_M0PR_Pos)))
+#define MATRIX_PRAS9_M1PR_Pos 4
+#define MATRIX_PRAS9_M1PR_Msk (0x3u << MATRIX_PRAS9_M1PR_Pos) /**< \brief (MATRIX_PRAS9) Master 1 Priority */
+#define MATRIX_PRAS9_M1PR(value) ((MATRIX_PRAS9_M1PR_Msk & ((value) << MATRIX_PRAS9_M1PR_Pos)))
+#define MATRIX_PRAS9_M2PR_Pos 8
+#define MATRIX_PRAS9_M2PR_Msk (0x3u << MATRIX_PRAS9_M2PR_Pos) /**< \brief (MATRIX_PRAS9) Master 2 Priority */
+#define MATRIX_PRAS9_M2PR(value) ((MATRIX_PRAS9_M2PR_Msk & ((value) << MATRIX_PRAS9_M2PR_Pos)))
+#define MATRIX_PRAS9_M3PR_Pos 12
+#define MATRIX_PRAS9_M3PR_Msk (0x3u << MATRIX_PRAS9_M3PR_Pos) /**< \brief (MATRIX_PRAS9) Master 3 Priority */
+#define MATRIX_PRAS9_M3PR(value) ((MATRIX_PRAS9_M3PR_Msk & ((value) << MATRIX_PRAS9_M3PR_Pos)))
+#define MATRIX_PRAS9_M4PR_Pos 16
+#define MATRIX_PRAS9_M4PR_Msk (0x3u << MATRIX_PRAS9_M4PR_Pos) /**< \brief (MATRIX_PRAS9) Master 4 Priority */
+#define MATRIX_PRAS9_M4PR(value) ((MATRIX_PRAS9_M4PR_Msk & ((value) << MATRIX_PRAS9_M4PR_Pos)))
+/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */
+#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 0 */
+#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 1 */
+#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 2 */
+#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 3 */
+#define MATRIX_MRCR_RCB4 (0x1u << 4) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 4 */
+/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */
+#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */
+#define MATRIX_WPMR_WPKEY_Pos 8
+#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */
+#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
+/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */
+#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */
+#define MATRIX_WPSR_WPVSRC_Pos 8
+#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3U_MATRIX_COMPONENT_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/component/pdc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/component/pdc.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,98 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U_PDC_COMPONENT_
+#define _SAM3U_PDC_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_PDC Peripheral DMA Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pdc hardware registers */
+typedef struct {
+ RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x0) Receive Pointer Register */
+ RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x4) Receive Counter Register */
+ RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x8) Transmit Pointer Register */
+ RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0xC) Transmit Counter Register */
+ RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */
+ RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */
+ RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */
+ RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */
+ WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */
+ RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */
+} Pdc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PERIPH_RPR : (PDC Offset: 0x0) Receive Pointer Register -------- */
+#define PERIPH_RPR_RXPTR_Pos 0
+#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */
+#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos)))
+/* -------- PERIPH_RCR : (PDC Offset: 0x4) Receive Counter Register -------- */
+#define PERIPH_RCR_RXCTR_Pos 0
+#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */
+#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos)))
+/* -------- PERIPH_TPR : (PDC Offset: 0x8) Transmit Pointer Register -------- */
+#define PERIPH_TPR_TXPTR_Pos 0
+#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */
+#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos)))
+/* -------- PERIPH_TCR : (PDC Offset: 0xC) Transmit Counter Register -------- */
+#define PERIPH_TCR_TXCTR_Pos 0
+#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */
+#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos)))
+/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */
+#define PERIPH_RNPR_RXNPTR_Pos 0
+#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */
+#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos)))
+/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */
+#define PERIPH_RNCR_RXNCTR_Pos 0
+#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */
+#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos)))
+/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */
+#define PERIPH_TNPR_TXNPTR_Pos 0
+#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */
+#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos)))
+/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */
+#define PERIPH_TNCR_TXNCTR_Pos 0
+#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */
+#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos)))
+/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */
+#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */
+#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */
+#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */
+#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */
+/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */
+#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */
+#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3U_PDC_COMPONENT_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/component/pio.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/component/pio.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1435 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U_PIO_COMPONENT_
+#define _SAM3U_PIO_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_PIO Parallel Input/Output Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pio hardware registers */
+typedef struct {
+ WoReg PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */
+ WoReg PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */
+ RoReg PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */
+ RoReg Reserved1[1];
+ WoReg PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */
+ WoReg PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */
+ RoReg PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */
+ RoReg Reserved2[1];
+ WoReg PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */
+ WoReg PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */
+ RoReg PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */
+ RoReg Reserved3[1];
+ WoReg PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */
+ WoReg PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */
+ RwReg PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */
+ RoReg PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */
+ WoReg PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */
+ WoReg PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */
+ RoReg PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */
+ RoReg PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */
+ WoReg PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */
+ WoReg PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */
+ RoReg PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */
+ RoReg Reserved4[1];
+ WoReg PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */
+ WoReg PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */
+ RoReg PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */
+ RoReg Reserved5[1];
+ RwReg PIO_ABSR; /**< \brief (Pio Offset: 0x0070) Peripheral AB Select Register */
+ RoReg Reserved6[3];
+ WoReg PIO_SCIFSR; /**< \brief (Pio Offset: 0x0080) System Clock Glitch Input Filter Select Register */
+ WoReg PIO_DIFSR; /**< \brief (Pio Offset: 0x0084) Debouncing Input Filter Select Register */
+ RoReg PIO_IFDGSR; /**< \brief (Pio Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register */
+ RwReg PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */
+ RoReg Reserved7[4];
+ WoReg PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */
+ WoReg PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */
+ RoReg PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */
+ RoReg Reserved8[1];
+ WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */
+ WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */
+ RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */
+ RoReg Reserved9[1];
+ WoReg PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */
+ WoReg PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */
+ RoReg PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */
+ RoReg Reserved10[1];
+ WoReg PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */
+ WoReg PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */
+ RoReg PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */
+ RoReg Reserved11[1];
+ RoReg PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */
+ RwReg PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */
+ RoReg PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */
+} Pio;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */
+#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */
+/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */
+#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */
+/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */
+#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */
+/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */
+#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */
+/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */
+#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */
+/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */
+#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */
+/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */
+#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */
+/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */
+#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */
+/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */
+#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */
+/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */
+#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */
+/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */
+#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */
+/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */
+#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */
+/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */
+#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */
+/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */
+#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */
+#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */
+#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */
+#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */
+#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */
+/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */
+#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */
+#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */
+/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */
+#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */
+/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */
+#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */
+/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */
+#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */
+/* -------- PIO_ABSR : (PIO Offset: 0x0070) Peripheral AB Select Register -------- */
+#define PIO_ABSR_P0 (0x1u << 0) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P1 (0x1u << 1) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P2 (0x1u << 2) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P3 (0x1u << 3) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P4 (0x1u << 4) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P5 (0x1u << 5) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P6 (0x1u << 6) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P7 (0x1u << 7) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P8 (0x1u << 8) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P9 (0x1u << 9) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P10 (0x1u << 10) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P11 (0x1u << 11) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P12 (0x1u << 12) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P13 (0x1u << 13) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P14 (0x1u << 14) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P15 (0x1u << 15) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P16 (0x1u << 16) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P17 (0x1u << 17) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P18 (0x1u << 18) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P19 (0x1u << 19) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P20 (0x1u << 20) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P21 (0x1u << 21) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P22 (0x1u << 22) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P23 (0x1u << 23) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P24 (0x1u << 24) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P25 (0x1u << 25) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P26 (0x1u << 26) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P27 (0x1u << 27) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P28 (0x1u << 28) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P29 (0x1u << 29) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P30 (0x1u << 30) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P31 (0x1u << 31) /**< \brief (PIO_ABSR) Peripheral A Select. */
+/* -------- PIO_SCIFSR : (PIO Offset: 0x0080) System Clock Glitch Input Filter Select Register -------- */
+#define PIO_SCIFSR_P0 (0x1u << 0) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P1 (0x1u << 1) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P2 (0x1u << 2) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P3 (0x1u << 3) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P4 (0x1u << 4) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P5 (0x1u << 5) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P6 (0x1u << 6) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P7 (0x1u << 7) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P8 (0x1u << 8) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P9 (0x1u << 9) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P10 (0x1u << 10) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P11 (0x1u << 11) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P12 (0x1u << 12) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P13 (0x1u << 13) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P14 (0x1u << 14) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P15 (0x1u << 15) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P16 (0x1u << 16) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P17 (0x1u << 17) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P18 (0x1u << 18) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P19 (0x1u << 19) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P20 (0x1u << 20) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P21 (0x1u << 21) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P22 (0x1u << 22) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P23 (0x1u << 23) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P24 (0x1u << 24) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P25 (0x1u << 25) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P26 (0x1u << 26) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P27 (0x1u << 27) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P28 (0x1u << 28) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P29 (0x1u << 29) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P30 (0x1u << 30) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P31 (0x1u << 31) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+/* -------- PIO_DIFSR : (PIO Offset: 0x0084) Debouncing Input Filter Select Register -------- */
+#define PIO_DIFSR_P0 (0x1u << 0) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P1 (0x1u << 1) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P2 (0x1u << 2) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P3 (0x1u << 3) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P4 (0x1u << 4) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P5 (0x1u << 5) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P6 (0x1u << 6) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P7 (0x1u << 7) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P8 (0x1u << 8) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P9 (0x1u << 9) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P10 (0x1u << 10) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P11 (0x1u << 11) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P12 (0x1u << 12) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P13 (0x1u << 13) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P14 (0x1u << 14) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P15 (0x1u << 15) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P16 (0x1u << 16) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P17 (0x1u << 17) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P18 (0x1u << 18) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P19 (0x1u << 19) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P20 (0x1u << 20) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P21 (0x1u << 21) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P22 (0x1u << 22) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P23 (0x1u << 23) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P24 (0x1u << 24) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P25 (0x1u << 25) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P26 (0x1u << 26) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P27 (0x1u << 27) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P28 (0x1u << 28) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P29 (0x1u << 29) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P30 (0x1u << 30) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P31 (0x1u << 31) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+/* -------- PIO_IFDGSR : (PIO Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register -------- */
+#define PIO_IFDGSR_P0 (0x1u << 0) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P1 (0x1u << 1) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P2 (0x1u << 2) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P3 (0x1u << 3) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P4 (0x1u << 4) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P5 (0x1u << 5) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P6 (0x1u << 6) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P7 (0x1u << 7) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P8 (0x1u << 8) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P9 (0x1u << 9) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P10 (0x1u << 10) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P11 (0x1u << 11) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P12 (0x1u << 12) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P13 (0x1u << 13) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P14 (0x1u << 14) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P15 (0x1u << 15) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P16 (0x1u << 16) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P17 (0x1u << 17) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P18 (0x1u << 18) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P19 (0x1u << 19) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P20 (0x1u << 20) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P21 (0x1u << 21) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P22 (0x1u << 22) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P23 (0x1u << 23) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P24 (0x1u << 24) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P25 (0x1u << 25) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P26 (0x1u << 26) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P27 (0x1u << 27) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P28 (0x1u << 28) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P29 (0x1u << 29) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P30 (0x1u << 30) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P31 (0x1u << 31) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */
+#define PIO_SCDR_DIV_Pos 0
+#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */
+#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))
+/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */
+#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable. */
+/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */
+#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable. */
+/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */
+#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status. */
+/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */
+#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */
+#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */
+#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */
+#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */
+#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */
+#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */
+#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */
+#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */
+#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */
+#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status. */
+/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */
+#define PIO_WPMR_WPKEY_Pos 8
+#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY */
+#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)))
+/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */
+#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */
+#define PIO_WPSR_WPVSRC_Pos 8
+#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3U_PIO_COMPONENT_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/component/pmc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/component/pmc.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,339 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U_PMC_COMPONENT_
+#define _SAM3U_PMC_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Power Management Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_PMC Power Management Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pmc hardware registers */
+typedef struct {
+ WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */
+ WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */
+ RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */
+ RoReg Reserved1[1];
+ WoReg PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */
+ WoReg PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */
+ RoReg PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */
+ RwReg CKGR_UCKR; /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */
+ RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */
+ RoReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */
+ RwReg CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */
+ RoReg Reserved2[1];
+ RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */
+ RoReg Reserved3[3];
+ RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */
+ RoReg Reserved4[5];
+ WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */
+ WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */
+ RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */
+ RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */
+ RwReg PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */
+ RwReg PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */
+ WoReg PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */
+ RoReg Reserved5[26];
+ RwReg PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */
+ RoReg PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */
+} Pmc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
+#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */
+#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */
+#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */
+/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
+#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */
+#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */
+#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */
+/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
+#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */
+#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */
+#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */
+/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
+#define PMC_PCER0_PID2 (0x1u << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */
+#define PMC_PCER0_PID3 (0x1u << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */
+#define PMC_PCER0_PID4 (0x1u << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */
+#define PMC_PCER0_PID5 (0x1u << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */
+#define PMC_PCER0_PID6 (0x1u << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */
+#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */
+#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */
+#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */
+#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */
+#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */
+#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */
+#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */
+#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */
+#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */
+#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */
+#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */
+#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */
+#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */
+#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */
+#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */
+#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */
+#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */
+#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */
+#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */
+#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */
+#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */
+#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */
+/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
+#define PMC_PCDR0_PID2 (0x1u << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */
+#define PMC_PCDR0_PID3 (0x1u << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */
+#define PMC_PCDR0_PID4 (0x1u << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */
+#define PMC_PCDR0_PID5 (0x1u << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */
+#define PMC_PCDR0_PID6 (0x1u << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */
+#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */
+#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */
+#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */
+#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */
+#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */
+#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */
+#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */
+#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */
+#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */
+#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */
+#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */
+#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */
+#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */
+#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */
+#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */
+#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */
+#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */
+#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */
+#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */
+#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */
+#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */
+#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */
+/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
+#define PMC_PCSR0_PID2 (0x1u << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */
+#define PMC_PCSR0_PID3 (0x1u << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */
+#define PMC_PCSR0_PID4 (0x1u << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */
+#define PMC_PCSR0_PID5 (0x1u << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */
+#define PMC_PCSR0_PID6 (0x1u << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */
+#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */
+#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */
+#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */
+#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */
+#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */
+#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */
+#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */
+#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */
+#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */
+#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */
+#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */
+#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */
+#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */
+#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */
+#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */
+#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */
+#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */
+#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */
+#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */
+#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */
+#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */
+#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */
+/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */
+#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */
+#define CKGR_UCKR_UPLLCOUNT_Pos 20
+#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */
+#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)))
+/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
+#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */
+#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */
+#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */
+#define CKGR_MOR_MOSCRCF_Pos 4
+#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */
+#define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */
+#define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */
+#define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */
+#define CKGR_MOR_MOSCXTST_Pos 8
+#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */
+#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
+#define CKGR_MOR_KEY_Pos 16
+#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */
+#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
+#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */
+#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */
+/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
+#define CKGR_MCFR_MAINF_Pos 0
+#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */
+#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */
+/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
+#define CKGR_PLLAR_DIVA_Pos 0
+#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider */
+#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
+#define CKGR_PLLAR_PLLACOUNT_Pos 8
+#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */
+#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
+#define CKGR_PLLAR_MULA_Pos 16
+#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */
+#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
+#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */
+/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
+#define PMC_MCKR_CSS_Pos 0
+#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */
+#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */
+#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */
+#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */
+#define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) UPLLClock is selected */
+#define PMC_MCKR_PRES_Pos 4
+#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */
+#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */
+#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */
+#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */
+#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */
+#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */
+#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */
+#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */
+#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */
+#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */
+#define PMC_MCKR_UPLLDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) UPLL Divisor by 2 */
+/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
+#define PMC_PCK_CSS_Pos 0
+#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */
+#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */
+#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */
+#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */
+#define PMC_PCK_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) UPLL Clock is selected */
+#define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */
+#define PMC_PCK_PRES_Pos 4
+#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */
+#define PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */
+#define PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */
+#define PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */
+#define PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */
+#define PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */
+#define PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */
+#define PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */
+/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
+#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */
+#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */
+#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */
+#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */
+#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */
+#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */
+#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */
+#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */
+#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */
+#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */
+/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
+#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */
+#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */
+#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */
+#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */
+#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */
+#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */
+#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */
+#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */
+#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */
+#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */
+/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
+#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */
+#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */
+#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */
+#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */
+#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */
+#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */
+#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */
+#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */
+#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */
+#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */
+/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
+#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */
+#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */
+#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */
+#define PMC_IMR_LOCKU (0x1u << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */
+#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */
+#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */
+#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */
+#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */
+#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */
+#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */
+/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
+#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */
+#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */
+#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */
+#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */
+#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */
+#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */
+#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */
+#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */
+#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */
+#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */
+#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */
+#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */
+#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */
+#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */
+#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */
+#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */
+#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */
+#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */
+#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */
+#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low Power Mode */
+/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
+#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
+#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */
+/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */
+#define PMC_WPMR_WPKEY_Pos 8
+#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */
+#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
+/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */
+#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */
+#define PMC_WPSR_WPVSRC_Pos 8
+#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3U_PMC_COMPONENT_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/component/pwm.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/component/pwm.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,545 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U_PWM_COMPONENT_
+#define _SAM3U_PWM_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_PWM Pulse Width Modulation Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief PwmCh_num hardware registers */
+typedef struct {
+ RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */
+ RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */
+ RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */
+ RwReg PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */
+ RwReg PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */
+ RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */
+ RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */
+ RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */
+} PwmCh_num;
+/** \brief PwmCmp hardware registers */
+typedef struct {
+ RwReg PWM_CMPV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */
+ RwReg PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */
+ RwReg PWM_CMPM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */
+ RwReg PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */
+} PwmCmp;
+/** \brief Pwm hardware registers */
+#define PWMCMP_NUMBER 8
+#define PWMCH_NUM_NUMBER 4
+typedef struct {
+ RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */
+ WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */
+ WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */
+ RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */
+ WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */
+ WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */
+ RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */
+ RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */
+ RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */
+ RoReg Reserved1[1];
+ RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */
+ RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */
+ WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */
+ WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */
+ WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */
+ RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */
+ RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */
+ RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */
+ RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */
+ WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */
+ WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */
+ WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */
+ WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */
+ RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */
+ RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */
+ WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */
+ RwReg PWM_FPV; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */
+ RwReg PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */
+ RoReg Reserved2[3];
+ RwReg PWM_ELMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */
+ RoReg Reserved3[11];
+ RwReg PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */
+ RoReg Reserved4[12];
+ WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */
+ RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */
+ RoReg Reserved5[7];
+ RwReg PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */
+ RwReg PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */
+ RoReg Reserved6[2];
+ RwReg PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */
+ RwReg PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */
+ WoReg PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */
+ RoReg PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */
+ RoReg Reserved7[2];
+ PwmCmp PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */
+ RoReg Reserved8[20];
+ PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */
+} Pwm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */
+#define PWM_CLK_DIVA_Pos 0
+#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
+#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))
+#define PWM_CLK_PREA_Pos 8
+#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
+#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))
+#define PWM_CLK_DIVB_Pos 16
+#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
+#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))
+#define PWM_CLK_PREB_Pos 24
+#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
+#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))
+/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
+#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */
+/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
+#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */
+/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
+#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */
+/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */
+#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */
+#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */
+#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */
+#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */
+#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */
+#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */
+#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */
+#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */
+/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */
+#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */
+#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */
+#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */
+#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */
+#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */
+#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */
+#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */
+#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */
+/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */
+#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */
+#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */
+#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */
+#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */
+#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */
+#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */
+#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */
+#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */
+/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */
+#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */
+#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */
+#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */
+#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */
+#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */
+#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */
+#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */
+#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */
+/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */
+#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */
+#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */
+#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */
+#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */
+#define PWM_SCM_UPDM_Pos 16
+#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */
+#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */
+#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */
+#define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels */
+#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */
+#define PWM_SCM_PTRCS_Pos 21
+#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */
+#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))
+/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */
+#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */
+/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */
+#define PWM_SCUP_UPR_Pos 0
+#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */
+#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))
+#define PWM_SCUP_UPRCNT_Pos 4
+#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */
+#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))
+/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */
+#define PWM_SCUPUPD_UPRUPD_Pos 0
+#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */
+#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))
+/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */
+#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */
+#define PWM_IER2_ENDTX (0x1u << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */
+#define PWM_IER2_TXBUFE (0x1u << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */
+#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */
+#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */
+#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */
+#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */
+#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */
+#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */
+#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */
+#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */
+#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */
+#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */
+#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */
+#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */
+#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */
+#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */
+#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */
+#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */
+#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */
+/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */
+#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */
+#define PWM_IDR2_ENDTX (0x1u << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */
+#define PWM_IDR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */
+#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */
+#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */
+#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */
+#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */
+#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */
+#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */
+#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */
+#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */
+#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */
+#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */
+#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */
+#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */
+#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */
+#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */
+#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */
+#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */
+#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */
+/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */
+#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */
+#define PWM_IMR2_ENDTX (0x1u << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */
+#define PWM_IMR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */
+#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */
+#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */
+#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */
+#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */
+#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */
+#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */
+#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */
+#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */
+#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */
+#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */
+#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */
+#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */
+#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */
+#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */
+#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */
+#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */
+#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */
+/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */
+#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */
+#define PWM_ISR2_ENDTX (0x1u << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */
+#define PWM_ISR2_TXBUFE (0x1u << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */
+#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */
+#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */
+#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */
+#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */
+#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */
+#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */
+#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */
+#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */
+#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */
+#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */
+#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */
+#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */
+#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */
+#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */
+#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */
+#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */
+#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */
+/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */
+#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */
+#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */
+#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */
+#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */
+#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */
+#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */
+#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */
+#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */
+/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */
+#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */
+#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */
+#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */
+#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */
+#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */
+#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */
+#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */
+#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */
+/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */
+#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */
+/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */
+#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */
+/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */
+#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */
+/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */
+#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */
+/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */
+#define PWM_FMR_FPOL_Pos 0
+#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to 3) */
+#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))
+#define PWM_FMR_FMOD_Pos 8
+#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to 3) */
+#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))
+#define PWM_FMR_FFIL_Pos 16
+#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to 3) */
+#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))
+/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */
+#define PWM_FSR_FIV_Pos 0
+#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to 3) */
+#define PWM_FSR_FS_Pos 8
+#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to 3) */
+/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */
+#define PWM_FCR_FCLR_Pos 0
+#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to 3) */
+#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))
+/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */
+#define PWM_FPV_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */
+#define PWM_FPV_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */
+#define PWM_FPV_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */
+#define PWM_FPV_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */
+#define PWM_FPV_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */
+#define PWM_FPV_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */
+#define PWM_FPV_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */
+#define PWM_FPV_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */
+/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */
+#define PWM_FPE_FPE0_Pos 0
+#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 (fault input bit varies from 0 to 3) */
+#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)))
+#define PWM_FPE_FPE1_Pos 8
+#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 (fault input bit varies from 0 to 3) */
+#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)))
+#define PWM_FPE_FPE2_Pos 16
+#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 (fault input bit varies from 0 to 3) */
+#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)))
+#define PWM_FPE_FPE3_Pos 24
+#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 (fault input bit varies from 0 to 3) */
+#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)))
+/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */
+#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */
+#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */
+#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */
+#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */
+#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */
+#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */
+#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */
+#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */
+/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */
+#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */
+#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */
+/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */
+#define PWM_WPCR_WPCMD_Pos 0
+#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */
+#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))
+#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */
+#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */
+#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */
+#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */
+#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */
+#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */
+#define PWM_WPCR_WPKEY_Pos 8
+#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */
+#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))
+/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */
+#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */
+#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPVSRC_Pos 16
+#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */
+/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */
+#define PWM_TPR_TXPTR_Pos 0
+#define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos) /**< \brief (PWM_TPR) Transmit Counter Register */
+#define PWM_TPR_TXPTR(value) ((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos)))
+/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */
+#define PWM_TCR_TXCTR_Pos 0
+#define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos) /**< \brief (PWM_TCR) Transmit Counter Register */
+#define PWM_TCR_TXCTR(value) ((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos)))
+/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */
+#define PWM_TNPR_TXNPTR_Pos 0
+#define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos) /**< \brief (PWM_TNPR) Transmit Next Pointer */
+#define PWM_TNPR_TXNPTR(value) ((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos)))
+/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */
+#define PWM_TNCR_TXNCTR_Pos 0
+#define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos) /**< \brief (PWM_TNCR) Transmit Counter Next */
+#define PWM_TNCR_TXNCTR(value) ((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos)))
+/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */
+#define PWM_PTCR_RXTEN (0x1u << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */
+#define PWM_PTCR_RXTDIS (0x1u << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */
+#define PWM_PTCR_TXTEN (0x1u << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */
+#define PWM_PTCR_TXTDIS (0x1u << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */
+/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */
+#define PWM_PTSR_RXTEN (0x1u << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */
+#define PWM_PTSR_TXTEN (0x1u << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */
+/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */
+#define PWM_CMPV_CV_Pos 0
+#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */
+#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))
+#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */
+/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */
+#define PWM_CMPVUPD_CVUPD_Pos 0
+#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */
+#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))
+#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */
+/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */
+#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */
+#define PWM_CMPM_CTR_Pos 4
+#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */
+#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))
+#define PWM_CMPM_CPR_Pos 8
+#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */
+#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))
+#define PWM_CMPM_CPRCNT_Pos 12
+#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */
+#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))
+#define PWM_CMPM_CUPR_Pos 16
+#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */
+#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))
+#define PWM_CMPM_CUPRCNT_Pos 20
+#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */
+#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))
+/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */
+#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */
+#define PWM_CMPMUPD_CTRUPD_Pos 4
+#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */
+#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))
+#define PWM_CMPMUPD_CPRUPD_Pos 8
+#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */
+#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))
+#define PWM_CMPMUPD_CUPRUPD_Pos 16
+#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */
+#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))
+/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */
+#define PWM_CMR_CPRE_Pos 0
+#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */
+#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master clock */
+#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Master clock/2 */
+#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Master clock/4 */
+#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Master clock/8 */
+#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Master clock/16 */
+#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Master clock/32 */
+#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Master clock/64 */
+#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Master clock/128 */
+#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Master clock/256 */
+#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Master clock/512 */
+#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Master clock/1024 */
+#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */
+#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */
+#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */
+#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */
+#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */
+#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */
+#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */
+#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */
+/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */
+#define PWM_CDTY_CDTY_Pos 0
+#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */
+#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
+/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */
+#define PWM_CDTYUPD_CDTYUPD_Pos 0
+#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */
+#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))
+/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */
+#define PWM_CPRD_CPRD_Pos 0
+#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */
+#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
+/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */
+#define PWM_CPRDUPD_CPRDUPD_Pos 0
+#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */
+#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))
+/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */
+#define PWM_CCNT_CNT_Pos 0
+#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */
+/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */
+#define PWM_DT_DTH_Pos 0
+#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */
+#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))
+#define PWM_DT_DTL_Pos 16
+#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */
+#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))
+/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */
+#define PWM_DTUPD_DTHUPD_Pos 0
+#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */
+#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))
+#define PWM_DTUPD_DTLUPD_Pos 16
+#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */
+#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3U_PWM_COMPONENT_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/component/rstc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/component/rstc.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,73 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U_RSTC_COMPONENT_
+#define _SAM3U_RSTC_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Reset Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_RSTC Reset Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rstc hardware registers */
+typedef struct {
+ WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
+ RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
+ RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
+} Rstc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
+#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
+#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */
+#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */
+#define RSTC_CR_KEY_Pos 24
+#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */
+#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
+/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
+#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
+#define RSTC_SR_RSTTYP_Pos 8
+#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
+#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
+#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
+/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
+#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */
+#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
+#define RSTC_MR_ERSTL_Pos 8
+#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */
+#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
+#define RSTC_MR_KEY_Pos 24
+#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */
+#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3U_RSTC_COMPONENT_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/component/rtc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/component/rtc.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,168 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U_RTC_COMPONENT_
+#define _SAM3U_RTC_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Real-time Clock */
+/* ============================================================================= */
+/** \addtogroup SAM3U_RTC Real-time Clock */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rtc hardware registers */
+typedef struct {
+ RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */
+ RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */
+ RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */
+ RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */
+ RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
+ RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
+ RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */
+ WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
+ WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
+ WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
+ RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
+ RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
+ RoReg Reserved1[45];
+ RwReg RTC_WPMR; /**< \brief (Rtc Offset: 0xE4) Write Protect Mode Register */
+} Rtc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
+#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */
+#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
+#define RTC_CR_TIMEVSEL_Pos 8
+#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */
+#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */
+#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */
+#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */
+#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */
+#define RTC_CR_CALEVSEL_Pos 16
+#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */
+#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */
+#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */
+#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */
+/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
+#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
+/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
+#define RTC_TIMR_SEC_Pos 0
+#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */
+#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
+#define RTC_TIMR_MIN_Pos 8
+#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */
+#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
+#define RTC_TIMR_HOUR_Pos 16
+#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */
+#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
+#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
+/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
+#define RTC_CALR_CENT_Pos 0
+#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */
+#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
+#define RTC_CALR_YEAR_Pos 8
+#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */
+#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
+#define RTC_CALR_MONTH_Pos 16
+#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */
+#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
+#define RTC_CALR_DAY_Pos 21
+#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */
+#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
+#define RTC_CALR_DATE_Pos 24
+#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */
+#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
+/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
+#define RTC_TIMALR_SEC_Pos 0
+#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */
+#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
+#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
+#define RTC_TIMALR_MIN_Pos 8
+#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */
+#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
+#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
+#define RTC_TIMALR_HOUR_Pos 16
+#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */
+#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
+#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
+#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
+/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
+#define RTC_CALALR_MONTH_Pos 16
+#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */
+#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
+#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
+#define RTC_CALALR_DATE_Pos 24
+#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */
+#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
+#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
+/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
+#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */
+#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */
+#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */
+#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */
+#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */
+/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
+#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
+#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */
+#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */
+#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */
+#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */
+/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
+#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
+#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
+#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
+#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
+#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
+/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
+#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
+#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
+#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
+#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
+#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
+/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
+#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
+#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
+#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
+#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
+#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
+/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
+#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */
+#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */
+#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
+#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */
+/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protect Mode Register -------- */
+#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protect Enable */
+#define RTC_WPMR_WPKEY_Pos 8
+#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR) */
+#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3U_RTC_COMPONENT_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/component/rtt.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/component/rtt.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,69 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U_RTT_COMPONENT_
+#define _SAM3U_RTT_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Real-time Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3U_RTT Real-time Timer */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rtt hardware registers */
+typedef struct {
+ RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */
+ RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */
+ RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */
+ RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */
+} Rtt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */
+#define RTT_MR_RTPRES_Pos 0
+#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */
+#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))
+#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */
+#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */
+#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */
+/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */
+#define RTT_AR_ALMV_Pos 0
+#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */
+#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))
+/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */
+#define RTT_VR_CRTV_Pos 0
+#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */
+/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */
+#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */
+#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */
+
+/*@}*/
+
+
+#endif /* _SAM3U_RTT_COMPONENT_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/component/smc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/component/smc.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,485 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U_SMC_COMPONENT_
+#define _SAM3U_SMC_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Static Memory Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_SMC Static Memory Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief SmcCs_number hardware registers */
+typedef struct {
+ RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */
+ RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */
+ RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */
+ RwReg SMC_TIMINGS; /**< \brief (SmcCs_number Offset: 0xC) SMC Timings Register */
+ RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0x10) SMC Mode Register */
+} SmcCs_number;
+/** \brief Smc hardware registers */
+#define SMCCS_NUMBER_NUMBER 4
+typedef struct {
+ RwReg SMC_CFG; /**< \brief (Smc Offset: 0x000) SMC NFC Configuration Register */
+ WoReg SMC_CTRL; /**< \brief (Smc Offset: 0x004) SMC NFC Control Register */
+ RoReg SMC_SR; /**< \brief (Smc Offset: 0x008) SMC NFC Status Register */
+ WoReg SMC_IER; /**< \brief (Smc Offset: 0x00C) SMC NFC Interrupt Enable Register */
+ WoReg SMC_IDR; /**< \brief (Smc Offset: 0x010) SMC NFC Interrupt Disable Register */
+ RoReg SMC_IMR; /**< \brief (Smc Offset: 0x014) SMC NFC Interrupt Mask Register */
+ RwReg SMC_ADDR; /**< \brief (Smc Offset: 0x018) SMC NFC Address Cycle Zero Register */
+ RwReg SMC_BANK; /**< \brief (Smc Offset: 0x01C) SMC Bank Address Register */
+ WoReg SMC_ECC_CTRL; /**< \brief (Smc Offset: 0x020) SMC ECC Control Register */
+ RwReg SMC_ECC_MD; /**< \brief (Smc Offset: 0x024) SMC ECC Mode Register */
+ RoReg SMC_ECC_SR1; /**< \brief (Smc Offset: 0x028) SMC ECC Status 1 Register */
+ RoReg SMC_ECC_PR0; /**< \brief (Smc Offset: 0x02C) SMC ECC Parity 0 Register */
+ RoReg SMC_ECC_PR1; /**< \brief (Smc Offset: 0x030) SMC ECC parity 1 Register */
+ RoReg SMC_ECC_SR2; /**< \brief (Smc Offset: 0x034) SMC ECC status 2 Register */
+ RoReg SMC_ECC_PR2; /**< \brief (Smc Offset: 0x038) SMC ECC parity 2 Register */
+ RoReg SMC_ECC_PR3; /**< \brief (Smc Offset: 0x03C) SMC ECC parity 3 Register */
+ RoReg SMC_ECC_PR4; /**< \brief (Smc Offset: 0x040) SMC ECC parity 4 Register */
+ RoReg SMC_ECC_PR5; /**< \brief (Smc Offset: 0x044) SMC ECC parity 5 Register */
+ RoReg SMC_ECC_PR6; /**< \brief (Smc Offset: 0x048) SMC ECC parity 6 Register */
+ RoReg SMC_ECC_PR7; /**< \brief (Smc Offset: 0x04C) SMC ECC parity 7 Register */
+ RoReg SMC_ECC_PR8; /**< \brief (Smc Offset: 0x050) SMC ECC parity 8 Register */
+ RoReg SMC_ECC_PR9; /**< \brief (Smc Offset: 0x054) SMC ECC parity 9 Register */
+ RoReg SMC_ECC_PR10; /**< \brief (Smc Offset: 0x058) SMC ECC parity 10 Register */
+ RoReg SMC_ECC_PR11; /**< \brief (Smc Offset: 0x05C) SMC ECC parity 11 Register */
+ RoReg SMC_ECC_PR12; /**< \brief (Smc Offset: 0x060) SMC ECC parity 12 Register */
+ RoReg SMC_ECC_PR13; /**< \brief (Smc Offset: 0x064) SMC ECC parity 13 Register */
+ RoReg SMC_ECC_PR14; /**< \brief (Smc Offset: 0x068) SMC ECC parity 14 Register */
+ RoReg SMC_ECC_PR15; /**< \brief (Smc Offset: 0x06C) SMC ECC parity 15 Register */
+ SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x70) CS_number = 0 .. 3 */
+ RoReg Reserved1[20];
+ RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x110) SMC OCMS Register */
+ WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x114) SMC OCMS KEY1 Register */
+ WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x118) SMC OCMS KEY2 Register */
+ RoReg Reserved2[50];
+ WoReg SMC_WPCR; /**< \brief (Smc Offset: 0x1E4) Write Protection Control Register */
+ RoReg SMC_WPSR; /**< \brief (Smc Offset: 0x1E8) Write Protection Status Register */
+} Smc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SMC_CFG : (SMC Offset: 0x000) SMC NFC Configuration Register -------- */
+#define SMC_CFG_PAGESIZE_Pos 0
+#define SMC_CFG_PAGESIZE_Msk (0x3u << SMC_CFG_PAGESIZE_Pos) /**< \brief (SMC_CFG) */
+#define SMC_CFG_PAGESIZE_PS512_16 (0x0u << 0) /**< \brief (SMC_CFG) Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes */
+#define SMC_CFG_PAGESIZE_PS1024_32 (0x1u << 0) /**< \brief (SMC_CFG) Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes */
+#define SMC_CFG_PAGESIZE_PS2048_64 (0x2u << 0) /**< \brief (SMC_CFG) Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes */
+#define SMC_CFG_PAGESIZE_PS4096_128 (0x3u << 0) /**< \brief (SMC_CFG) Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes */
+#define SMC_CFG_WSPARE (0x1u << 8) /**< \brief (SMC_CFG) Write Spare Area */
+#define SMC_CFG_RSPARE (0x1u << 9) /**< \brief (SMC_CFG) Read Spare Area */
+#define SMC_CFG_EDGECTRL (0x1u << 12) /**< \brief (SMC_CFG) Rising/Falling Edge Detection Control */
+#define SMC_CFG_RBEDGE (0x1u << 13) /**< \brief (SMC_CFG) Ready/Busy Signal Edge Detection */
+#define SMC_CFG_DTOCYC_Pos 16
+#define SMC_CFG_DTOCYC_Msk (0xfu << SMC_CFG_DTOCYC_Pos) /**< \brief (SMC_CFG) Data Timeout Cycle Number */
+#define SMC_CFG_DTOCYC(value) ((SMC_CFG_DTOCYC_Msk & ((value) << SMC_CFG_DTOCYC_Pos)))
+#define SMC_CFG_DTOMUL_Pos 20
+#define SMC_CFG_DTOMUL_Msk (0x7u << SMC_CFG_DTOMUL_Pos) /**< \brief (SMC_CFG) Data Timeout Multiplier */
+#define SMC_CFG_DTOMUL_X1 (0x0u << 20) /**< \brief (SMC_CFG) DTOCYC */
+#define SMC_CFG_DTOMUL_X16 (0x1u << 20) /**< \brief (SMC_CFG) DTOCYC x 16 */
+#define SMC_CFG_DTOMUL_X128 (0x2u << 20) /**< \brief (SMC_CFG) DTOCYC x 128 */
+#define SMC_CFG_DTOMUL_X256 (0x3u << 20) /**< \brief (SMC_CFG) DTOCYC x 256 */
+#define SMC_CFG_DTOMUL_X1024 (0x4u << 20) /**< \brief (SMC_CFG) DTOCYC x 1024 */
+#define SMC_CFG_DTOMUL_X4096 (0x5u << 20) /**< \brief (SMC_CFG) DTOCYC x 4096 */
+#define SMC_CFG_DTOMUL_X65536 (0x6u << 20) /**< \brief (SMC_CFG) DTOCYC x 65536 */
+#define SMC_CFG_DTOMUL_X1048576 (0x7u << 20) /**< \brief (SMC_CFG) DTOCYC x 1048576 */
+/* -------- SMC_CTRL : (SMC Offset: 0x004) SMC NFC Control Register -------- */
+#define SMC_CTRL_NFCEN (0x1u << 0) /**< \brief (SMC_CTRL) NAND Flash Controller Enable */
+#define SMC_CTRL_NFCDIS (0x1u << 1) /**< \brief (SMC_CTRL) NAND Flash Controller Disable */
+/* -------- SMC_SR : (SMC Offset: 0x008) SMC NFC Status Register -------- */
+#define SMC_SR_SMCSTS (0x1u << 0) /**< \brief (SMC_SR) NAND Flash Controller status (this field cannot be reset) */
+#define SMC_SR_RB_RISE (0x1u << 4) /**< \brief (SMC_SR) Selected Ready Busy Rising Edge Detected */
+#define SMC_SR_RB_FALL (0x1u << 5) /**< \brief (SMC_SR) Selected Ready Busy Falling Edge Detected */
+#define SMC_SR_NFCBUSY (0x1u << 8) /**< \brief (SMC_SR) NFC Busy (this field cannot be reset) */
+#define SMC_SR_NFCWR (0x1u << 11) /**< \brief (SMC_SR) NFC Write/Read Operation (this field cannot be reset) */
+#define SMC_SR_NFCSID_Pos 12
+#define SMC_SR_NFCSID_Msk (0x7u << SMC_SR_NFCSID_Pos) /**< \brief (SMC_SR) NFC Chip Select ID (this field cannot be reset) */
+#define SMC_SR_XFRDONE (0x1u << 16) /**< \brief (SMC_SR) NFC Data Transfer Terminated */
+#define SMC_SR_CMDDONE (0x1u << 17) /**< \brief (SMC_SR) Command Done */
+#define SMC_SR_DTOE (0x1u << 20) /**< \brief (SMC_SR) Data Timeout Error */
+#define SMC_SR_UNDEF (0x1u << 21) /**< \brief (SMC_SR) Undefined Area Error */
+#define SMC_SR_AWB (0x1u << 22) /**< \brief (SMC_SR) Accessing While Busy */
+#define SMC_SR_NFCASE (0x1u << 23) /**< \brief (SMC_SR) NFC Access Size Error */
+#define SMC_SR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_SR) Ready/Busy Line 0 Edge Detected */
+/* -------- SMC_IER : (SMC Offset: 0x00C) SMC NFC Interrupt Enable Register -------- */
+#define SMC_IER_RB_RISE (0x1u << 4) /**< \brief (SMC_IER) Ready Busy Rising Edge Detection Interrupt Enable */
+#define SMC_IER_RB_FALL (0x1u << 5) /**< \brief (SMC_IER) Ready Busy Falling Edge Detection Interrupt Enable */
+#define SMC_IER_XFRDONE (0x1u << 16) /**< \brief (SMC_IER) Transfer Done Interrupt Enable */
+#define SMC_IER_CMDDONE (0x1u << 17) /**< \brief (SMC_IER) Command Done Interrupt Enable */
+#define SMC_IER_DTOE (0x1u << 20) /**< \brief (SMC_IER) Data Timeout Error Interrupt Enable */
+#define SMC_IER_UNDEF (0x1u << 21) /**< \brief (SMC_IER) Undefined Area Access Interrupt Enable */
+#define SMC_IER_AWB (0x1u << 22) /**< \brief (SMC_IER) Accessing While Busy Interrupt Enable */
+#define SMC_IER_NFCASE (0x1u << 23) /**< \brief (SMC_IER) NFC Access Size Error Interrupt Enable */
+#define SMC_IER_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IER) Ready/Busy Line 0 Interrupt Enable */
+/* -------- SMC_IDR : (SMC Offset: 0x010) SMC NFC Interrupt Disable Register -------- */
+#define SMC_IDR_RB_RISE (0x1u << 4) /**< \brief (SMC_IDR) Ready Busy Rising Edge Detection Interrupt Disable */
+#define SMC_IDR_RB_FALL (0x1u << 5) /**< \brief (SMC_IDR) Ready Busy Falling Edge Detection Interrupt Disable */
+#define SMC_IDR_XFRDONE (0x1u << 16) /**< \brief (SMC_IDR) Transfer Done Interrupt Disable */
+#define SMC_IDR_CMDDONE (0x1u << 17) /**< \brief (SMC_IDR) Command Done Interrupt Disable */
+#define SMC_IDR_DTOE (0x1u << 20) /**< \brief (SMC_IDR) Data Timeout Error Interrupt Disable */
+#define SMC_IDR_UNDEF (0x1u << 21) /**< \brief (SMC_IDR) Undefined Area Access Interrupt Disable */
+#define SMC_IDR_AWB (0x1u << 22) /**< \brief (SMC_IDR) Accessing While Busy Interrupt Disable */
+#define SMC_IDR_NFCASE (0x1u << 23) /**< \brief (SMC_IDR) NFC Access Size Error Interrupt Disable */
+#define SMC_IDR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IDR) Ready/Busy Line 0 Interrupt Disable */
+/* -------- SMC_IMR : (SMC Offset: 0x014) SMC NFC Interrupt Mask Register -------- */
+#define SMC_IMR_RB_RISE (0x1u << 4) /**< \brief (SMC_IMR) Ready Busy Rising Edge Detection Interrupt Mask */
+#define SMC_IMR_RB_FALL (0x1u << 5) /**< \brief (SMC_IMR) Ready Busy Falling Edge Detection Interrupt Mask */
+#define SMC_IMR_XFRDONE (0x1u << 16) /**< \brief (SMC_IMR) Transfer Done Interrupt Mask */
+#define SMC_IMR_CMDDONE (0x1u << 17) /**< \brief (SMC_IMR) Command Done Interrupt Mask */
+#define SMC_IMR_DTOE (0x1u << 20) /**< \brief (SMC_IMR) Data Timeout Error Interrupt Mask */
+#define SMC_IMR_UNDEF (0x1u << 21) /**< \brief (SMC_IMR) Undefined Area Access Interrupt Mask5 */
+#define SMC_IMR_AWB (0x1u << 22) /**< \brief (SMC_IMR) Accessing While Busy Interrupt Mask */
+#define SMC_IMR_NFCASE (0x1u << 23) /**< \brief (SMC_IMR) NFC Access Size Error Interrupt Mask */
+#define SMC_IMR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IMR) Ready/Busy Line 0 Interrupt Mask */
+/* -------- SMC_ADDR : (SMC Offset: 0x018) SMC NFC Address Cycle Zero Register -------- */
+#define SMC_ADDR_ADDR_CYCLE0_Pos 0
+#define SMC_ADDR_ADDR_CYCLE0_Msk (0xffu << SMC_ADDR_ADDR_CYCLE0_Pos) /**< \brief (SMC_ADDR) NAND Flash Array Address cycle 0 */
+#define SMC_ADDR_ADDR_CYCLE0(value) ((SMC_ADDR_ADDR_CYCLE0_Msk & ((value) << SMC_ADDR_ADDR_CYCLE0_Pos)))
+/* -------- SMC_BANK : (SMC Offset: 0x01C) SMC Bank Address Register -------- */
+#define SMC_BANK_BANK_Pos 0
+#define SMC_BANK_BANK_Msk (0x7u << SMC_BANK_BANK_Pos) /**< \brief (SMC_BANK) Bank Identifier */
+#define SMC_BANK_BANK(value) ((SMC_BANK_BANK_Msk & ((value) << SMC_BANK_BANK_Pos)))
+/* -------- SMC_ECC_CTRL : (SMC Offset: 0x020) SMC ECC Control Register -------- */
+#define SMC_ECC_CTRL_RST (0x1u << 0) /**< \brief (SMC_ECC_CTRL) Reset ECC */
+#define SMC_ECC_CTRL_SWRST (0x1u << 1) /**< \brief (SMC_ECC_CTRL) Software Reset */
+/* -------- SMC_ECC_MD : (SMC Offset: 0x024) SMC ECC Mode Register -------- */
+#define SMC_ECC_MD_ECC_PAGESIZE_Pos 0
+#define SMC_ECC_MD_ECC_PAGESIZE_Msk (0x3u << SMC_ECC_MD_ECC_PAGESIZE_Pos) /**< \brief (SMC_ECC_MD) ECC Page Size */
+#define SMC_ECC_MD_ECC_PAGESIZE_PS512_16 (0x0u << 0) /**< \brief (SMC_ECC_MD) Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes */
+#define SMC_ECC_MD_ECC_PAGESIZE_PS1024_32 (0x1u << 0) /**< \brief (SMC_ECC_MD) Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes */
+#define SMC_ECC_MD_ECC_PAGESIZE_PS2048_64 (0x2u << 0) /**< \brief (SMC_ECC_MD) Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes */
+#define SMC_ECC_MD_ECC_PAGESIZE_PS4096_128 (0x3u << 0) /**< \brief (SMC_ECC_MD) Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes */
+#define SMC_ECC_MD_TYPCORREC_Pos 4
+#define SMC_ECC_MD_TYPCORREC_Msk (0x3u << SMC_ECC_MD_TYPCORREC_Pos) /**< \brief (SMC_ECC_MD) Type of Correction */
+#define SMC_ECC_MD_TYPCORREC_CPAGE (0x0u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for a page of 512/1024/2048/4096 Bytes (for 8 or 16-bit NAND Flash) */
+#define SMC_ECC_MD_TYPCORREC_C256B (0x1u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 256 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */
+#define SMC_ECC_MD_TYPCORREC_C512B (0x2u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 512 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */
+/* -------- SMC_ECC_SR1 : (SMC Offset: 0x028) SMC ECC Status 1 Register -------- */
+#define SMC_ECC_SR1_RECERR0 (0x1u << 0) /**< \brief (SMC_ECC_SR1) Recoverable Error */
+#define SMC_ECC_SR1_ECCERR0_Pos 1
+#define SMC_ECC_SR1_ECCERR0_Msk (0x3u << SMC_ECC_SR1_ECCERR0_Pos) /**< \brief (SMC_ECC_SR1) ECC Error */
+#define SMC_ECC_SR1_RECERR1 (0x1u << 4) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 256th and the 511th bytes or the 512nd and the 1023rd bytes */
+#define SMC_ECC_SR1_ECCERR1 (0x1u << 5) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */
+#define SMC_ECC_SR1_MULERR1 (0x1u << 6) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */
+#define SMC_ECC_SR1_RECERR2 (0x1u << 8) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
+#define SMC_ECC_SR1_ECCERR2 (0x1u << 9) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
+#define SMC_ECC_SR1_MULERR2 (0x1u << 10) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
+#define SMC_ECC_SR1_RECERR3 (0x1u << 12) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
+#define SMC_ECC_SR1_ECCERR3 (0x1u << 13) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
+#define SMC_ECC_SR1_MULERR3 (0x1u << 14) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
+#define SMC_ECC_SR1_RECERR4 (0x1u << 16) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */
+#define SMC_ECC_SR1_ECCERR4_Pos 17
+#define SMC_ECC_SR1_ECCERR4_Msk (0x3u << SMC_ECC_SR1_ECCERR4_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */
+#define SMC_ECC_SR1_RECERR5 (0x1u << 20) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */
+#define SMC_ECC_SR1_ECCERR5_Pos 21
+#define SMC_ECC_SR1_ECCERR5_Msk (0x3u << SMC_ECC_SR1_ECCERR5_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */
+#define SMC_ECC_SR1_RECERR6 (0x1u << 24) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */
+#define SMC_ECC_SR1_ECCERR6_Pos 25
+#define SMC_ECC_SR1_ECCERR6_Msk (0x3u << SMC_ECC_SR1_ECCERR6_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */
+#define SMC_ECC_SR1_RECERR7 (0x1u << 28) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */
+#define SMC_ECC_SR1_ECCERR7_Pos 29
+#define SMC_ECC_SR1_ECCERR7_Msk (0x3u << SMC_ECC_SR1_ECCERR7_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */
+/* -------- SMC_ECC_PR0 : (SMC Offset: 0x02C) SMC ECC Parity 0 Register -------- */
+#define SMC_ECC_PR0_BITADDR_Pos 0
+#define SMC_ECC_PR0_BITADDR_Msk (0xfu << SMC_ECC_PR0_BITADDR_Pos) /**< \brief (SMC_ECC_PR0) Bit Address */
+#define SMC_ECC_PR0_WORDADDR_Pos 4
+#define SMC_ECC_PR0_WORDADDR_Msk (0xfffu << SMC_ECC_PR0_WORDADDR_Pos) /**< \brief (SMC_ECC_PR0) Word Address */
+#define SMC_ECC_PR0_BITADDR_W9BIT_Pos 0
+#define SMC_ECC_PR0_BITADDR_W9BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W9BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_WORDADDR_W9BIT_Pos 3
+#define SMC_ECC_PR0_WORDADDR_W9BIT_Msk (0x1ffu << SMC_ECC_PR0_WORDADDR_W9BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_NPARITY_Pos 12
+#define SMC_ECC_PR0_NPARITY_Msk (0xfffu << SMC_ECC_PR0_NPARITY_Pos) /**< \brief (SMC_ECC_PR0) Parity N */
+#define SMC_ECC_PR0_BITADDR_W8BIT_Pos 0
+#define SMC_ECC_PR0_BITADDR_W8BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR0_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR0_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR0_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR0_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Parity N */
+/* -------- SMC_ECC_PR1 : (SMC Offset: 0x030) SMC ECC parity 1 Register -------- */
+#define SMC_ECC_PR1_NPARITY_Pos 0
+#define SMC_ECC_PR1_NPARITY_Msk (0xffffu << SMC_ECC_PR1_NPARITY_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
+#define SMC_ECC_PR1_BITADDR_Pos 0
+#define SMC_ECC_PR1_BITADDR_Msk (0x7u << SMC_ECC_PR1_BITADDR_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR1_WORDADDR_Pos 3
+#define SMC_ECC_PR1_WORDADDR_Msk (0x1ffu << SMC_ECC_PR1_WORDADDR_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR1_NPARITY_W9BIT_Pos 12
+#define SMC_ECC_PR1_NPARITY_W9BIT_Msk (0xfffu << SMC_ECC_PR1_NPARITY_W9BIT_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
+#define SMC_ECC_PR1_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR1_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR1_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR1_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR1_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR1_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
+/* -------- SMC_ECC_SR2 : (SMC Offset: 0x034) SMC ECC status 2 Register -------- */
+#define SMC_ECC_SR2_RECERR8 (0x1u << 0) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2048th and the 2303rd bytes */
+#define SMC_ECC_SR2_ECCERR8_Pos 1
+#define SMC_ECC_SR2_ECCERR8_Msk (0x3u << SMC_ECC_SR2_ECCERR8_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2048th and the 2303rd bytes */
+#define SMC_ECC_SR2_RECERR9 (0x1u << 4) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2304th and the 2559th bytes */
+#define SMC_ECC_SR2_ECCERR9 (0x1u << 5) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2304th and the 2559th bytes */
+#define SMC_ECC_SR2_MULERR9 (0x1u << 6) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2304th and the 2559th bytes */
+#define SMC_ECC_SR2_RECERR10 (0x1u << 8) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2560th and the 2815th bytes */
+#define SMC_ECC_SR2_ECCERR10 (0x1u << 9) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2560th and the 2815th bytes */
+#define SMC_ECC_SR2_MULERR10 (0x1u << 10) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2560th and the 2815th bytes */
+#define SMC_ECC_SR2_RECERR11 (0x1u << 12) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2816th and the 3071st bytes */
+#define SMC_ECC_SR2_ECCERR11 (0x1u << 13) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2816th and the 3071st bytes */
+#define SMC_ECC_SR2_MULERR11 (0x1u << 14) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2816th and the 3071st bytes */
+#define SMC_ECC_SR2_RECERR12 (0x1u << 16) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3072nd and the 3327th bytes */
+#define SMC_ECC_SR2_ECCERR12_Pos 17
+#define SMC_ECC_SR2_ECCERR12_Msk (0x3u << SMC_ECC_SR2_ECCERR12_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3072nd and the 3327th bytes */
+#define SMC_ECC_SR2_RECERR13 (0x1u << 20) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3328th and the 3583rd bytes */
+#define SMC_ECC_SR2_ECCERR13_Pos 21
+#define SMC_ECC_SR2_ECCERR13_Msk (0x3u << SMC_ECC_SR2_ECCERR13_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3328th and the 3583rd bytes */
+#define SMC_ECC_SR2_RECERR14 (0x1u << 24) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3584th and the 3839th bytes */
+#define SMC_ECC_SR2_ECCERR14_Pos 25
+#define SMC_ECC_SR2_ECCERR14_Msk (0x3u << SMC_ECC_SR2_ECCERR14_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3584th and the 3839th bytes */
+#define SMC_ECC_SR2_RECERR15 (0x1u << 28) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3840th and the 4095th bytes */
+#define SMC_ECC_SR2_ECCERR15_Pos 29
+#define SMC_ECC_SR2_ECCERR15_Msk (0x3u << SMC_ECC_SR2_ECCERR15_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3840th and the 4095th bytes */
+/* -------- SMC_ECC_PR2 : (SMC Offset: 0x038) SMC ECC parity 2 Register -------- */
+#define SMC_ECC_PR2_BITADDR_Pos 0
+#define SMC_ECC_PR2_BITADDR_Msk (0x7u << SMC_ECC_PR2_BITADDR_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR2_WORDADDR_Pos 3
+#define SMC_ECC_PR2_WORDADDR_Msk (0x1ffu << SMC_ECC_PR2_WORDADDR_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR2_NPARITY_Pos 12
+#define SMC_ECC_PR2_NPARITY_Msk (0xfffu << SMC_ECC_PR2_NPARITY_Pos) /**< \brief (SMC_ECC_PR2) Parity N */
+#define SMC_ECC_PR2_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR2_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR2_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR2_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR2_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR2_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR2) Parity N */
+/* -------- SMC_ECC_PR3 : (SMC Offset: 0x03C) SMC ECC parity 3 Register -------- */
+#define SMC_ECC_PR3_BITADDR_Pos 0
+#define SMC_ECC_PR3_BITADDR_Msk (0x7u << SMC_ECC_PR3_BITADDR_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR3_WORDADDR_Pos 3
+#define SMC_ECC_PR3_WORDADDR_Msk (0x1ffu << SMC_ECC_PR3_WORDADDR_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR3_NPARITY_Pos 12
+#define SMC_ECC_PR3_NPARITY_Msk (0xfffu << SMC_ECC_PR3_NPARITY_Pos) /**< \brief (SMC_ECC_PR3) Parity N */
+#define SMC_ECC_PR3_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR3_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR3_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR3_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR3_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR3_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR3) Parity N */
+/* -------- SMC_ECC_PR4 : (SMC Offset: 0x040) SMC ECC parity 4 Register -------- */
+#define SMC_ECC_PR4_BITADDR_Pos 0
+#define SMC_ECC_PR4_BITADDR_Msk (0x7u << SMC_ECC_PR4_BITADDR_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR4_WORDADDR_Pos 3
+#define SMC_ECC_PR4_WORDADDR_Msk (0x1ffu << SMC_ECC_PR4_WORDADDR_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR4_NPARITY_Pos 12
+#define SMC_ECC_PR4_NPARITY_Msk (0xfffu << SMC_ECC_PR4_NPARITY_Pos) /**< \brief (SMC_ECC_PR4) Parity N */
+#define SMC_ECC_PR4_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR4_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR4_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR4_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR4_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR4_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR4) Parity N */
+/* -------- SMC_ECC_PR5 : (SMC Offset: 0x044) SMC ECC parity 5 Register -------- */
+#define SMC_ECC_PR5_BITADDR_Pos 0
+#define SMC_ECC_PR5_BITADDR_Msk (0x7u << SMC_ECC_PR5_BITADDR_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR5_WORDADDR_Pos 3
+#define SMC_ECC_PR5_WORDADDR_Msk (0x1ffu << SMC_ECC_PR5_WORDADDR_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR5_NPARITY_Pos 12
+#define SMC_ECC_PR5_NPARITY_Msk (0xfffu << SMC_ECC_PR5_NPARITY_Pos) /**< \brief (SMC_ECC_PR5) Parity N */
+#define SMC_ECC_PR5_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR5_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR5_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR5_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR5_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR5_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR5) Parity N */
+/* -------- SMC_ECC_PR6 : (SMC Offset: 0x048) SMC ECC parity 6 Register -------- */
+#define SMC_ECC_PR6_BITADDR_Pos 0
+#define SMC_ECC_PR6_BITADDR_Msk (0x7u << SMC_ECC_PR6_BITADDR_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR6_WORDADDR_Pos 3
+#define SMC_ECC_PR6_WORDADDR_Msk (0x1ffu << SMC_ECC_PR6_WORDADDR_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR6_NPARITY_Pos 12
+#define SMC_ECC_PR6_NPARITY_Msk (0xfffu << SMC_ECC_PR6_NPARITY_Pos) /**< \brief (SMC_ECC_PR6) Parity N */
+#define SMC_ECC_PR6_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR6_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR6_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR6_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR6_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR6_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR6) Parity N */
+/* -------- SMC_ECC_PR7 : (SMC Offset: 0x04C) SMC ECC parity 7 Register -------- */
+#define SMC_ECC_PR7_BITADDR_Pos 0
+#define SMC_ECC_PR7_BITADDR_Msk (0x7u << SMC_ECC_PR7_BITADDR_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR7_WORDADDR_Pos 3
+#define SMC_ECC_PR7_WORDADDR_Msk (0x1ffu << SMC_ECC_PR7_WORDADDR_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR7_NPARITY_Pos 12
+#define SMC_ECC_PR7_NPARITY_Msk (0xfffu << SMC_ECC_PR7_NPARITY_Pos) /**< \brief (SMC_ECC_PR7) Parity N */
+#define SMC_ECC_PR7_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR7_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR7_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR7_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR7_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR7_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR7) Parity N */
+/* -------- SMC_ECC_PR8 : (SMC Offset: 0x050) SMC ECC parity 8 Register -------- */
+#define SMC_ECC_PR8_BITADDR_Pos 0
+#define SMC_ECC_PR8_BITADDR_Msk (0x7u << SMC_ECC_PR8_BITADDR_Pos) /**< \brief (SMC_ECC_PR8) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR8_WORDADDR_Pos 3
+#define SMC_ECC_PR8_WORDADDR_Msk (0xffu << SMC_ECC_PR8_WORDADDR_Pos) /**< \brief (SMC_ECC_PR8) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR8_NPARITY_Pos 12
+#define SMC_ECC_PR8_NPARITY_Msk (0x7ffu << SMC_ECC_PR8_NPARITY_Pos) /**< \brief (SMC_ECC_PR8) Parity N */
+/* -------- SMC_ECC_PR9 : (SMC Offset: 0x054) SMC ECC parity 9 Register -------- */
+#define SMC_ECC_PR9_BITADDR_Pos 0
+#define SMC_ECC_PR9_BITADDR_Msk (0x7u << SMC_ECC_PR9_BITADDR_Pos) /**< \brief (SMC_ECC_PR9) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR9_WORDADDR_Pos 3
+#define SMC_ECC_PR9_WORDADDR_Msk (0xffu << SMC_ECC_PR9_WORDADDR_Pos) /**< \brief (SMC_ECC_PR9) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR9_NPARITY_Pos 12
+#define SMC_ECC_PR9_NPARITY_Msk (0x7ffu << SMC_ECC_PR9_NPARITY_Pos) /**< \brief (SMC_ECC_PR9) Parity N */
+/* -------- SMC_ECC_PR10 : (SMC Offset: 0x058) SMC ECC parity 10 Register -------- */
+#define SMC_ECC_PR10_BITADDR_Pos 0
+#define SMC_ECC_PR10_BITADDR_Msk (0x7u << SMC_ECC_PR10_BITADDR_Pos) /**< \brief (SMC_ECC_PR10) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR10_WORDADDR_Pos 3
+#define SMC_ECC_PR10_WORDADDR_Msk (0xffu << SMC_ECC_PR10_WORDADDR_Pos) /**< \brief (SMC_ECC_PR10) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR10_NPARITY_Pos 12
+#define SMC_ECC_PR10_NPARITY_Msk (0x7ffu << SMC_ECC_PR10_NPARITY_Pos) /**< \brief (SMC_ECC_PR10) Parity N */
+/* -------- SMC_ECC_PR11 : (SMC Offset: 0x05C) SMC ECC parity 11 Register -------- */
+#define SMC_ECC_PR11_BITADDR_Pos 0
+#define SMC_ECC_PR11_BITADDR_Msk (0x7u << SMC_ECC_PR11_BITADDR_Pos) /**< \brief (SMC_ECC_PR11) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR11_WORDADDR_Pos 3
+#define SMC_ECC_PR11_WORDADDR_Msk (0xffu << SMC_ECC_PR11_WORDADDR_Pos) /**< \brief (SMC_ECC_PR11) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR11_NPARITY_Pos 12
+#define SMC_ECC_PR11_NPARITY_Msk (0x7ffu << SMC_ECC_PR11_NPARITY_Pos) /**< \brief (SMC_ECC_PR11) Parity N */
+/* -------- SMC_ECC_PR12 : (SMC Offset: 0x060) SMC ECC parity 12 Register -------- */
+#define SMC_ECC_PR12_BITADDR_Pos 0
+#define SMC_ECC_PR12_BITADDR_Msk (0x7u << SMC_ECC_PR12_BITADDR_Pos) /**< \brief (SMC_ECC_PR12) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR12_WORDADDR_Pos 3
+#define SMC_ECC_PR12_WORDADDR_Msk (0xffu << SMC_ECC_PR12_WORDADDR_Pos) /**< \brief (SMC_ECC_PR12) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR12_NPARITY_Pos 12
+#define SMC_ECC_PR12_NPARITY_Msk (0x7ffu << SMC_ECC_PR12_NPARITY_Pos) /**< \brief (SMC_ECC_PR12) Parity N */
+/* -------- SMC_ECC_PR13 : (SMC Offset: 0x064) SMC ECC parity 13 Register -------- */
+#define SMC_ECC_PR13_BITADDR_Pos 0
+#define SMC_ECC_PR13_BITADDR_Msk (0x7u << SMC_ECC_PR13_BITADDR_Pos) /**< \brief (SMC_ECC_PR13) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR13_WORDADDR_Pos 3
+#define SMC_ECC_PR13_WORDADDR_Msk (0xffu << SMC_ECC_PR13_WORDADDR_Pos) /**< \brief (SMC_ECC_PR13) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR13_NPARITY_Pos 12
+#define SMC_ECC_PR13_NPARITY_Msk (0x7ffu << SMC_ECC_PR13_NPARITY_Pos) /**< \brief (SMC_ECC_PR13) Parity N */
+/* -------- SMC_ECC_PR14 : (SMC Offset: 0x068) SMC ECC parity 14 Register -------- */
+#define SMC_ECC_PR14_BITADDR_Pos 0
+#define SMC_ECC_PR14_BITADDR_Msk (0x7u << SMC_ECC_PR14_BITADDR_Pos) /**< \brief (SMC_ECC_PR14) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR14_WORDADDR_Pos 3
+#define SMC_ECC_PR14_WORDADDR_Msk (0xffu << SMC_ECC_PR14_WORDADDR_Pos) /**< \brief (SMC_ECC_PR14) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR14_NPARITY_Pos 12
+#define SMC_ECC_PR14_NPARITY_Msk (0x7ffu << SMC_ECC_PR14_NPARITY_Pos) /**< \brief (SMC_ECC_PR14) Parity N */
+/* -------- SMC_ECC_PR15 : (SMC Offset: 0x06C) SMC ECC parity 15 Register -------- */
+#define SMC_ECC_PR15_BITADDR_Pos 0
+#define SMC_ECC_PR15_BITADDR_Msk (0x7u << SMC_ECC_PR15_BITADDR_Pos) /**< \brief (SMC_ECC_PR15) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR15_WORDADDR_Pos 3
+#define SMC_ECC_PR15_WORDADDR_Msk (0xffu << SMC_ECC_PR15_WORDADDR_Pos) /**< \brief (SMC_ECC_PR15) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR15_NPARITY_Pos 12
+#define SMC_ECC_PR15_NPARITY_Msk (0x7ffu << SMC_ECC_PR15_NPARITY_Pos) /**< \brief (SMC_ECC_PR15) Parity N */
+/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */
+#define SMC_SETUP_NWE_SETUP_Pos 0
+#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */
+#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))
+#define SMC_SETUP_NCS_WR_SETUP_Pos 8
+#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Write Access */
+#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))
+#define SMC_SETUP_NRD_SETUP_Pos 16
+#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */
+#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))
+#define SMC_SETUP_NCS_RD_SETUP_Pos 24
+#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Read Access */
+#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))
+/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */
+#define SMC_PULSE_NWE_PULSE_Pos 0
+#define SMC_PULSE_NWE_PULSE_Msk (0x3fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */
+#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))
+#define SMC_PULSE_NCS_WR_PULSE_Pos 8
+#define SMC_PULSE_NCS_WR_PULSE_Msk (0x3fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */
+#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))
+#define SMC_PULSE_NRD_PULSE_Pos 16
+#define SMC_PULSE_NRD_PULSE_Msk (0x3fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */
+#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))
+#define SMC_PULSE_NCS_RD_PULSE_Pos 24
+#define SMC_PULSE_NCS_RD_PULSE_Msk (0x3fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */
+#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))
+/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */
+#define SMC_CYCLE_NWE_CYCLE_Pos 0
+#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */
+#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))
+#define SMC_CYCLE_NRD_CYCLE_Pos 16
+#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */
+#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))
+/* -------- SMC_TIMINGS : (SMC Offset: N/A) SMC Timings Register -------- */
+#define SMC_TIMINGS_TCLR_Pos 0
+#define SMC_TIMINGS_TCLR_Msk (0xfu << SMC_TIMINGS_TCLR_Pos) /**< \brief (SMC_TIMINGS) CLE to REN Low Delay */
+#define SMC_TIMINGS_TCLR(value) ((SMC_TIMINGS_TCLR_Msk & ((value) << SMC_TIMINGS_TCLR_Pos)))
+#define SMC_TIMINGS_TADL_Pos 4
+#define SMC_TIMINGS_TADL_Msk (0xfu << SMC_TIMINGS_TADL_Pos) /**< \brief (SMC_TIMINGS) ALE to Data Start */
+#define SMC_TIMINGS_TADL(value) ((SMC_TIMINGS_TADL_Msk & ((value) << SMC_TIMINGS_TADL_Pos)))
+#define SMC_TIMINGS_TAR_Pos 8
+#define SMC_TIMINGS_TAR_Msk (0xfu << SMC_TIMINGS_TAR_Pos) /**< \brief (SMC_TIMINGS) ALE to REN Low Delay */
+#define SMC_TIMINGS_TAR(value) ((SMC_TIMINGS_TAR_Msk & ((value) << SMC_TIMINGS_TAR_Pos)))
+#define SMC_TIMINGS_OCMS (0x1u << 12) /**< \brief (SMC_TIMINGS) Off Chip Memory Scrambling Enable */
+#define SMC_TIMINGS_TRR_Pos 16
+#define SMC_TIMINGS_TRR_Msk (0xfu << SMC_TIMINGS_TRR_Pos) /**< \brief (SMC_TIMINGS) Ready to REN Low Delay */
+#define SMC_TIMINGS_TRR(value) ((SMC_TIMINGS_TRR_Msk & ((value) << SMC_TIMINGS_TRR_Pos)))
+#define SMC_TIMINGS_TWB_Pos 24
+#define SMC_TIMINGS_TWB_Msk (0xfu << SMC_TIMINGS_TWB_Pos) /**< \brief (SMC_TIMINGS) WEN High to REN to Busy */
+#define SMC_TIMINGS_TWB(value) ((SMC_TIMINGS_TWB_Msk & ((value) << SMC_TIMINGS_TWB_Pos)))
+#define SMC_TIMINGS_RBNSEL_Pos 28
+#define SMC_TIMINGS_RBNSEL_Msk (0x7u << SMC_TIMINGS_RBNSEL_Pos) /**< \brief (SMC_TIMINGS) Ready/Busy Line Selection */
+#define SMC_TIMINGS_RBNSEL(value) ((SMC_TIMINGS_RBNSEL_Msk & ((value) << SMC_TIMINGS_RBNSEL_Pos)))
+#define SMC_TIMINGS_NFSEL (0x1u << 31) /**< \brief (SMC_TIMINGS) NAND Flash Selection */
+/* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */
+#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) */
+#define SMC_MODE_READ_MODE_NCS_CTRL (0x0u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NCS signal. */
+#define SMC_MODE_READ_MODE_NRD_CTRL (0x1u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NRD signal. */
+#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) */
+#define SMC_MODE_WRITE_MODE_NCS_CTRL (0x0u << 1) /**< \brief (SMC_MODE) The Write operation is controller by the NCS signal. */
+#define SMC_MODE_WRITE_MODE_NWE_CTRL (0x1u << 1) /**< \brief (SMC_MODE) The Write operation is controlled by the NWE signal. */
+#define SMC_MODE_EXNW_MODE_Pos 4
+#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */
+#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */
+#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */
+#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */
+#define SMC_MODE_BAT (0x1u << 8) /**< \brief (SMC_MODE) Byte Access Type */
+#define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */
+#define SMC_MODE_DBW_BIT_8 (0x0u << 12) /**< \brief (SMC_MODE) 8-bit bus */
+#define SMC_MODE_DBW_BIT_16 (0x1u << 12) /**< \brief (SMC_MODE) 16-bit bus */
+#define SMC_MODE_TDF_CYCLES_Pos 16
+#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */
+#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))
+#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */
+/* -------- SMC_OCMS : (SMC Offset: 0x110) SMC OCMS Register -------- */
+#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */
+#define SMC_OCMS_SRSE (0x1u << 1) /**< \brief (SMC_OCMS) SRAM Scrambling Enable */
+/* -------- SMC_KEY1 : (SMC Offset: 0x114) SMC OCMS KEY1 Register -------- */
+#define SMC_KEY1_KEY1_Pos 0
+#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */
+#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))
+/* -------- SMC_KEY2 : (SMC Offset: 0x118) SMC OCMS KEY2 Register -------- */
+#define SMC_KEY2_KEY2_Pos 0
+#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */
+#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))
+/* -------- SMC_WPCR : (SMC Offset: 0x1E4) Write Protection Control Register -------- */
+#define SMC_WPCR_WP_EN (0x1u << 0) /**< \brief (SMC_WPCR) Write Protection Enable */
+#define SMC_WPCR_WP_KEY_Pos 8
+#define SMC_WPCR_WP_KEY_Msk (0xffffffu << SMC_WPCR_WP_KEY_Pos) /**< \brief (SMC_WPCR) Write Protection KEY password */
+#define SMC_WPCR_WP_KEY(value) ((SMC_WPCR_WP_KEY_Msk & ((value) << SMC_WPCR_WP_KEY_Pos)))
+/* -------- SMC_WPSR : (SMC Offset: 0x1E8) Write Protection Status Register -------- */
+#define SMC_WPSR_WP_VS_Pos 0
+#define SMC_WPSR_WP_VS_Msk (0xfu << SMC_WPSR_WP_VS_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Status */
+#define SMC_WPSR_WP_VSRC_Pos 8
+#define SMC_WPSR_WP_VSRC_Msk (0xffffu << SMC_WPSR_WP_VSRC_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3U_SMC_COMPONENT_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/component/spi.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/component/spi.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,159 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U_SPI_COMPONENT_
+#define _SAM3U_SPI_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3U_SPI Serial Peripheral Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Spi hardware registers */
+typedef struct {
+ WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */
+ RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */
+ RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */
+ WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */
+ RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */
+ WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */
+ WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */
+ RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */
+ RoReg Reserved1[4];
+ RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */
+ RoReg Reserved2[41];
+ RwReg SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */
+ RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */
+} Spi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
+#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */
+#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */
+#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */
+#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */
+/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
+#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */
+#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */
+#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */
+#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */
+#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */
+#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */
+#define SPI_MR_PCS_Pos 16
+#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */
+#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
+#define SPI_MR_DLYBCS_Pos 24
+#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */
+#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
+/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
+#define SPI_RDR_RD_Pos 0
+#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */
+#define SPI_RDR_PCS_Pos 16
+#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */
+/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
+#define SPI_TDR_TD_Pos 0
+#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */
+#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
+#define SPI_TDR_PCS_Pos 16
+#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */
+#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
+#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */
+#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */
+#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */
+#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */
+#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */
+#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */
+#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */
+#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */
+#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */
+#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */
+#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */
+#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */
+#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */
+#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */
+#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */
+#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */
+#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */
+#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */
+#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */
+#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */
+/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
+#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */
+#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */
+#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */
+#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */
+#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */
+#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */
+#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */
+/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
+#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */
+#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */
+#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Active After Transfer */
+#define SPI_CSR_BITS_Pos 4
+#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */
+#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */
+#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */
+#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */
+#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */
+#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */
+#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */
+#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */
+#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */
+#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */
+#define SPI_CSR_SCBR_Pos 8
+#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */
+#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
+#define SPI_CSR_DLYBS_Pos 16
+#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */
+#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
+#define SPI_CSR_DLYBCT_Pos 24
+#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */
+#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
+/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */
+#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */
+#define SPI_WPMR_WPKEY_Pos 8
+#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key Password */
+#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)))
+/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
+#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */
+#define SPI_WPSR_WPVSRC_Pos 8
+#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3U_SPI_COMPONENT_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/component/ssc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/component/ssc.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,270 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U_SSC_COMPONENT_
+#define _SAM3U_SSC_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_SSC Synchronous Serial Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Ssc hardware registers */
+typedef struct {
+ WoReg SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */
+ RwReg SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */
+ RoReg Reserved1[2];
+ RwReg SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */
+ RwReg SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */
+ RwReg SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */
+ RwReg SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */
+ RoReg SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */
+ WoReg SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */
+ RoReg Reserved2[2];
+ RoReg SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */
+ RwReg SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */
+ RwReg SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */
+ RwReg SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */
+ RoReg SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */
+ WoReg SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */
+ WoReg SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */
+ RoReg SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */
+ RoReg Reserved3[37];
+ RwReg SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */
+ RoReg SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */
+} Ssc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */
+#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */
+#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */
+#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */
+#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */
+#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */
+/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */
+#define SSC_CMR_DIV_Pos 0
+#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */
+#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))
+/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */
+#define SSC_RCMR_CKS_Pos 0
+#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */
+#define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */
+#define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */
+#define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */
+#define SSC_RCMR_CKO_Pos 2
+#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */
+#define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None */
+#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock */
+#define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
+#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */
+#define SSC_RCMR_CKG_Pos 6
+#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */
+#define SSC_RCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_RCMR) None */
+#define SSC_RCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_RCMR) Continuous Receive Clock */
+#define SSC_RCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
+#define SSC_RCMR_START_Pos 8
+#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */
+#define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
+#define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */
+#define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */
+#define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */
+#define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */
+#define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */
+#define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */
+#define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */
+#define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */
+#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */
+#define SSC_RCMR_STTDLY_Pos 16
+#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */
+#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))
+#define SSC_RCMR_PERIOD_Pos 24
+#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */
+#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))
+/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */
+#define SSC_RFMR_DATLEN_Pos 0
+#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */
+#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))
+#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */
+#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */
+#define SSC_RFMR_DATNB_Pos 8
+#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */
+#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))
+#define SSC_RFMR_FSLEN_Pos 16
+#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */
+#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))
+#define SSC_RFMR_FSOS_Pos 20
+#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */
+#define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None */
+#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse */
+#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse */
+#define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer */
+#define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer */
+#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer */
+#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */
+#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */
+#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */
+#define SSC_RFMR_FSLEN_EXT_Pos 28
+#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */
+#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */
+#define SSC_TCMR_CKS_Pos 0
+#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */
+#define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */
+#define SSC_TCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_TCMR) TK Clock signal */
+#define SSC_TCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_TCMR) RK pin */
+#define SSC_TCMR_CKO_Pos 2
+#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */
+#define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None */
+#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Receive Clock */
+#define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers */
+#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */
+#define SSC_TCMR_CKG_Pos 6
+#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */
+#define SSC_TCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_TCMR) None */
+#define SSC_TCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */
+#define SSC_TCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */
+#define SSC_TCMR_START_Pos 8
+#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */
+#define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. */
+#define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */
+#define SSC_TCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */
+#define SSC_TCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */
+#define SSC_TCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */
+#define SSC_TCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */
+#define SSC_TCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */
+#define SSC_TCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */
+#define SSC_TCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_TCMR) Compare 0 */
+#define SSC_TCMR_STTDLY_Pos 16
+#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */
+#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))
+#define SSC_TCMR_PERIOD_Pos 24
+#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */
+#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))
+/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */
+#define SSC_TFMR_DATLEN_Pos 0
+#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */
+#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))
+#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */
+#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */
+#define SSC_TFMR_DATNB_Pos 8
+#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */
+#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))
+#define SSC_TFMR_FSLEN_Pos 16
+#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */
+#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))
+#define SSC_TFMR_FSOS_Pos 20
+#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */
+#define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None */
+#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse */
+#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse */
+#define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */
+#define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */
+#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */
+#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */
+#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */
+#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */
+#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */
+#define SSC_TFMR_FSLEN_EXT_Pos 28
+#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */
+#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */
+#define SSC_RHR_RDAT_Pos 0
+#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */
+/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */
+#define SSC_THR_TDAT_Pos 0
+#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */
+#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))
+/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */
+#define SSC_RSHR_RSDAT_Pos 0
+#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */
+/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */
+#define SSC_TSHR_TSDAT_Pos 0
+#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */
+#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))
+/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */
+#define SSC_RC0R_CP0_Pos 0
+#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */
+#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))
+/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */
+#define SSC_RC1R_CP1_Pos 0
+#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */
+#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))
+/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */
+#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */
+#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */
+#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */
+#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */
+#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */
+#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */
+#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */
+#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */
+#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */
+#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */
+/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */
+#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */
+#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */
+#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */
+#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */
+#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */
+#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */
+#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */
+#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */
+/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */
+#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */
+#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */
+#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */
+#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */
+#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */
+#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */
+#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */
+#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */
+/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */
+#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */
+#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */
+#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */
+#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */
+#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */
+#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */
+#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */
+#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */
+/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */
+#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */
+#define SSC_WPMR_WPKEY_Pos 8
+#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */
+#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))
+/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */
+#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */
+#define SSC_WPSR_WPVSRC_Pos 8
+#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3U_SSC_COMPONENT_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/component/supc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/component/supc.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,312 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U_SUPC_COMPONENT_
+#define _SAM3U_SUPC_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Supply Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_SUPC Supply Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Supc hardware registers */
+typedef struct {
+ WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */
+ RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */
+ RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */
+ RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */
+ RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */
+ RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */
+} Supc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */
+#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */
+#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */
+#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */
+#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */
+#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */
+#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */
+#define SUPC_CR_KEY_Pos 24
+#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */
+#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))
+/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */
+#define SUPC_SMMR_SMTH_Pos 0
+#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */
+#define SUPC_SMMR_SMTH_1_9V (0x0u << 0) /**< \brief (SUPC_SMMR) 1.9 V */
+#define SUPC_SMMR_SMTH_2_0V (0x1u << 0) /**< \brief (SUPC_SMMR) 2.0 V */
+#define SUPC_SMMR_SMTH_2_1V (0x2u << 0) /**< \brief (SUPC_SMMR) 2.1 V */
+#define SUPC_SMMR_SMTH_2_2V (0x3u << 0) /**< \brief (SUPC_SMMR) 2.2 V */
+#define SUPC_SMMR_SMTH_2_3V (0x4u << 0) /**< \brief (SUPC_SMMR) 2.3 V */
+#define SUPC_SMMR_SMTH_2_4V (0x5u << 0) /**< \brief (SUPC_SMMR) 2.4 V */
+#define SUPC_SMMR_SMTH_2_5V (0x6u << 0) /**< \brief (SUPC_SMMR) 2.5 V */
+#define SUPC_SMMR_SMTH_2_6V (0x7u << 0) /**< \brief (SUPC_SMMR) 2.6 V */
+#define SUPC_SMMR_SMTH_2_7V (0x8u << 0) /**< \brief (SUPC_SMMR) 2.7 V */
+#define SUPC_SMMR_SMTH_2_8V (0x9u << 0) /**< \brief (SUPC_SMMR) 2.8 V */
+#define SUPC_SMMR_SMTH_2_9V (0xAu << 0) /**< \brief (SUPC_SMMR) 2.9 V */
+#define SUPC_SMMR_SMTH_3_0V (0xBu << 0) /**< \brief (SUPC_SMMR) 3.0 V */
+#define SUPC_SMMR_SMTH_3_1V (0xCu << 0) /**< \brief (SUPC_SMMR) 3.1 V */
+#define SUPC_SMMR_SMTH_3_2V (0xDu << 0) /**< \brief (SUPC_SMMR) 3.2 V */
+#define SUPC_SMMR_SMTH_3_3V (0xEu << 0) /**< \brief (SUPC_SMMR) 3.3 V */
+#define SUPC_SMMR_SMTH_3_4V (0xFu << 0) /**< \brief (SUPC_SMMR) 3.4 V */
+#define SUPC_SMMR_SMSMPL_Pos 8
+#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */
+#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */
+#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */
+#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */
+#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */
+#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */
+#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */
+#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */
+#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */
+#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */
+#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */
+#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */
+/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */
+#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */
+#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */
+#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */
+#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */
+#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */
+#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */
+#define SUPC_MR_VDDIORDYONREG (0x1u << 14) /**< \brief (SUPC_MR) */
+#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */
+#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */
+#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */
+#define SUPC_MR_KEY_Pos 24
+#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */
+#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))
+/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */
+#define SUPC_WUMR_FWUPEN (0x1u << 0) /**< \brief (SUPC_WUMR) Force Wake Up Enable */
+#define SUPC_WUMR_FWUPEN_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin has no wake up effect. */
+#define SUPC_WUMR_FWUPEN_ENABLE (0x1u << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin low forces the wake up of the core power supply. */
+#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */
+#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */
+#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */
+#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */
+#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */
+#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */
+#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_FWUPDBC_Pos 8
+#define SUPC_WUMR_FWUPDBC_Msk (0x7u << SUPC_WUMR_FWUPDBC_Pos) /**< \brief (SUPC_WUMR) Force Wake Up Debouncer Period */
+#define SUPC_WUMR_FWUPDBC_IMMEDIATE (0x0u << 8) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
+#define SUPC_WUMR_FWUPDBC_3_SCLK (0x1u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 3 SLCK periods */
+#define SUPC_WUMR_FWUPDBC_32_SCLK (0x2u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32 SLCK periods */
+#define SUPC_WUMR_FWUPDBC_512_SCLK (0x3u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 512 SLCK periods */
+#define SUPC_WUMR_FWUPDBC_4096_SCLK (0x4u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 4,096 SLCK periods */
+#define SUPC_WUMR_FWUPDBC_32768_SCLK (0x5u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32,768 SLCK periods */
+#define SUPC_WUMR_WKUPDBC_Pos 12
+#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer Period */
+#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
+#define SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */
+#define SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */
+#define SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */
+#define SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */
+#define SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */
+/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */
+#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */
+#define SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */
+#define SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */
+#define SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */
+#define SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */
+#define SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */
+#define SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */
+#define SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */
+#define SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */
+#define SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */
+#define SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */
+#define SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */
+#define SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */
+#define SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */
+#define SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */
+#define SUPC_WUIR_WKUPEN14_DISABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */
+#define SUPC_WUIR_WKUPEN15_DISABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake Up Input Type 0 */
+#define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake Up Input Type 1 */
+#define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake Up Input Type 2 */
+#define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake Up Input Type 3 */
+#define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake Up Input Type 4 */
+#define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake Up Input Type 5 */
+#define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake Up Input Type 6 */
+#define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake Up Input Type 7 */
+#define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake Up Input Type 8 */
+#define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake Up Input Type 9 */
+#define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake Up Input Type 10 */
+#define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake Up Input Type 11 */
+#define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake Up Input Type 12 */
+#define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake Up Input Type 13 */
+#define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake Up Input Type 14 */
+#define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake Up Input Type 15 */
+#define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */
+#define SUPC_SR_FWUPS (0x1u << 0) /**< \brief (SUPC_SR) FWUP Wake Up Status */
+#define SUPC_SR_FWUPS_NO (0x0u << 0) /**< \brief (SUPC_SR) no wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_FWUPS_PRESENT (0x1u << 0) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */
+#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */
+#define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */
+#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */
+#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */
+#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */
+#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */
+#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */
+#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */
+#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */
+#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI higher than its threshold at its last measurement. */
+#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI lower than its threshold at its last measurement. */
+#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */
+#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */
+#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */
+#define SUPC_SR_FWUPIS (0x1u << 12) /**< \brief (SUPC_SR) FWUP Input Status */
+#define SUPC_SR_FWUPIS_LOW (0x0u << 12) /**< \brief (SUPC_SR) FWUP input is tied low. */
+#define SUPC_SR_FWUPIS_HIGH (0x1u << 12) /**< \brief (SUPC_SR) FWUP input is tied high. */
+#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */
+#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */
+#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */
+#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */
+#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */
+#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */
+#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */
+#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */
+#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */
+#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */
+#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */
+#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */
+#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */
+#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */
+#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */
+#define SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */
+#define SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+
+/*@}*/
+
+
+#endif /* _SAM3U_SUPC_COMPONENT_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/component/tc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/component/tc.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,288 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U_TC_COMPONENT_
+#define _SAM3U_TC_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Timer Counter */
+/* ============================================================================= */
+/** \addtogroup SAM3U_TC Timer Counter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief TcChannel hardware registers */
+typedef struct {
+ RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
+ RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
+ RoReg Reserved1[2];
+ RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */
+ RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */
+ RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */
+ RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */
+ RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */
+ RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
+ RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
+ RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
+ RoReg Reserved2[4];
+} TcChannel;
+/** \brief Tc hardware registers */
+#define TCCHANNEL_NUMBER 3
+typedef struct {
+ TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
+ WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */
+ RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */
+ WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */
+ WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */
+ RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */
+ RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */
+} Tc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
+#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */
+#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */
+#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */
+/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
+#define TC_CMR_TCCLKS_Pos 0
+#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */
+#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */
+#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */
+#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */
+#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */
+#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */
+#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */
+#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */
+#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */
+#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */
+#define TC_CMR_BURST_Pos 4
+#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */
+#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */
+#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */
+#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */
+#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */
+#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */
+#define TC_CMR_ETRGEDG_Pos 8
+#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */
+#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */
+#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */
+#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */
+#define TC_CMR_LDRA_Pos 16
+#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */
+#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_LDRB_Pos 18
+#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */
+#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */
+#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */
+#define TC_CMR_EEVTEDG_Pos 8
+#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */
+#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */
+#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_EEVT_Pos 10
+#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */
+#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */
+#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */
+#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */
+#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */
+#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */
+#define TC_CMR_WAVSEL_Pos 13
+#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */
+#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */
+#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */
+#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */
+#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */
+#define TC_CMR_ACPA_Pos 16
+#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */
+#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */
+#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */
+#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ACPC_Pos 18
+#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */
+#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */
+#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */
+#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_AEEVT_Pos 20
+#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */
+#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */
+#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */
+#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */
+#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ASWTRG_Pos 22
+#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */
+#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */
+#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */
+#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */
+#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPB_Pos 24
+#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */
+#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */
+#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */
+#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */
+#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPC_Pos 26
+#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */
+#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */
+#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */
+#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */
+#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BEEVT_Pos 28
+#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */
+#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */
+#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */
+#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */
+#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BSWTRG_Pos 30
+#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */
+#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */
+#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */
+#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */
+#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */
+/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
+#define TC_CV_CV_Pos 0
+#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */
+/* -------- TC_RA : (TC Offset: N/A) Register A -------- */
+#define TC_RA_RA_Pos 0
+#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */
+#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
+/* -------- TC_RB : (TC Offset: N/A) Register B -------- */
+#define TC_RB_RB_Pos 0
+#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */
+#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
+/* -------- TC_RC : (TC Offset: N/A) Register C -------- */
+#define TC_RC_RC_Pos 0
+#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */
+#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
+/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
+#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */
+#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */
+#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */
+#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */
+#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */
+#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */
+#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */
+#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */
+#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */
+#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */
+#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */
+/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
+#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */
+#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */
+#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */
+#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */
+#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */
+#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */
+#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */
+#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */
+/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
+#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */
+#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */
+#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */
+#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */
+#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */
+#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */
+#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */
+#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */
+/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
+#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */
+#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */
+#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */
+#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */
+#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */
+#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */
+#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */
+#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */
+/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
+#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */
+/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
+#define TC_BMR_TC0XC0S_Pos 0
+#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
+#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */
+#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */
+#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */
+#define TC_BMR_TC1XC1S_Pos 2
+#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
+#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */
+#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */
+#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */
+#define TC_BMR_TC2XC2S_Pos 4
+#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
+#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */
+#define TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */
+#define TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */
+#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */
+#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */
+#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */
+#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */
+#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */
+#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */
+#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */
+#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */
+#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */
+#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */
+#define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR) */
+#define TC_BMR_MAXFILT_Pos 20
+#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */
+#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))
+/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
+#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */
+#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */
+#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */
+/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
+#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */
+#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */
+#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */
+/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
+#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */
+#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */
+#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */
+/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
+#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */
+#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */
+#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */
+#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) DIRection */
+
+/*@}*/
+
+
+#endif /* _SAM3U_TC_COMPONENT_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/component/twi.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/component/twi.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,217 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U_TWI_COMPONENT_
+#define _SAM3U_TWI_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Two-wire Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3U_TWI Two-wire Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Twi hardware registers */
+typedef struct {
+ WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */
+ RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */
+ RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */
+ RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */
+ RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */
+ RoReg Reserved1[3];
+ RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */
+ WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */
+ WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */
+ RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */
+ RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */
+ WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */
+ RoReg Reserved2[50];
+ RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */
+ RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */
+ RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */
+ RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */
+ RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */
+ RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */
+ RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */
+ RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */
+ WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */
+ RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */
+} Twi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */
+#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */
+#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */
+#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */
+#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */
+#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */
+#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */
+#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */
+#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */
+/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */
+#define TWI_MMR_IADRSZ_Pos 8
+#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */
+#define TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */
+#define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */
+#define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */
+#define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */
+#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */
+#define TWI_MMR_DADR_Pos 16
+#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */
+#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))
+/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
+#define TWI_SMR_SADR_Pos 16
+#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */
+#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))
+/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
+#define TWI_IADR_IADR_Pos 0
+#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */
+#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))
+/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
+#define TWI_CWGR_CLDIV_Pos 0
+#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */
+#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))
+#define TWI_CWGR_CHDIV_Pos 8
+#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */
+#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))
+#define TWI_CWGR_CKDIV_Pos 16
+#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */
+#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))
+/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
+#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */
+#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */
+#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */
+#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */
+#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */
+#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */
+#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */
+#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */
+#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */
+#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */
+#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */
+#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */
+#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */
+#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */
+#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */
+/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */
+#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */
+#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */
+#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */
+#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */
+#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */
+#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */
+#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */
+#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */
+#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */
+#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */
+#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */
+#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */
+#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */
+#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */
+/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */
+#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */
+#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */
+#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */
+#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */
+#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */
+#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */
+#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */
+#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */
+#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */
+#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */
+#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */
+#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */
+#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */
+#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */
+/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */
+#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */
+#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */
+#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */
+#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */
+#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */
+#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */
+#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */
+#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */
+#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */
+#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */
+#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */
+#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */
+#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */
+#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */
+/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */
+#define TWI_RHR_RXDATA_Pos 0
+#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */
+/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */
+#define TWI_THR_TXDATA_Pos 0
+#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */
+#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))
+/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */
+#define TWI_RPR_RXPTR_Pos 0
+#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */
+#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos)))
+/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */
+#define TWI_RCR_RXCTR_Pos 0
+#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */
+#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos)))
+/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */
+#define TWI_TPR_TXPTR_Pos 0
+#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */
+#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos)))
+/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */
+#define TWI_TCR_TXCTR_Pos 0
+#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */
+#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos)))
+/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */
+#define TWI_RNPR_RXNPTR_Pos 0
+#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */
+#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos)))
+/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */
+#define TWI_RNCR_RXNCTR_Pos 0
+#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */
+#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos)))
+/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define TWI_TNPR_TXNPTR_Pos 0
+#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */
+#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos)))
+/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define TWI_TNCR_TXNCTR_Pos 0
+#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */
+#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos)))
+/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */
+#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */
+#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */
+#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */
+#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */
+/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */
+#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */
+#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3U_TWI_COMPONENT_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/component/uart.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/component/uart.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,185 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U_UART_COMPONENT_
+#define _SAM3U_UART_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3U_UART Universal Asynchronous Receiver Transmitter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Uart hardware registers */
+typedef struct {
+ WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */
+ RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */
+ WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */
+ WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */
+ RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */
+ RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */
+ RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */
+ WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */
+ RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */
+ RoReg Reserved1[55];
+ RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */
+ RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */
+ RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */
+ RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */
+ RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */
+ RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */
+ RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */
+ RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */
+ WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */
+ RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */
+} Uart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
+#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */
+#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */
+#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */
+#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */
+#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */
+#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */
+#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */
+/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
+#define UART_MR_PAR_Pos 9
+#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */
+#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */
+#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */
+#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */
+#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */
+#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */
+#define UART_MR_CHMODE_Pos 14
+#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */
+#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */
+#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */
+#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */
+#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */
+/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
+#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */
+#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */
+#define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */
+#define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */
+#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */
+#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */
+#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */
+#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */
+#define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */
+#define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */
+/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
+#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */
+#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */
+#define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */
+#define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */
+#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */
+#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */
+#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */
+#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */
+#define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */
+#define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */
+/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
+#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */
+#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */
+#define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */
+#define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */
+#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */
+#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */
+#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */
+#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */
+#define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */
+#define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */
+/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
+#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */
+#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */
+#define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */
+#define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */
+#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */
+#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */
+#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */
+#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */
+#define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */
+#define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */
+/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
+#define UART_RHR_RXCHR_Pos 0
+#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */
+/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
+#define UART_THR_TXCHR_Pos 0
+#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */
+#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
+/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define UART_BRGR_CD_Pos 0
+#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */
+#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
+/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */
+#define UART_RPR_RXPTR_Pos 0
+#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */
+#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos)))
+/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */
+#define UART_RCR_RXCTR_Pos 0
+#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */
+#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos)))
+/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */
+#define UART_TPR_TXPTR_Pos 0
+#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */
+#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos)))
+/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */
+#define UART_TCR_TXCTR_Pos 0
+#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */
+#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos)))
+/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */
+#define UART_RNPR_RXNPTR_Pos 0
+#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */
+#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos)))
+/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */
+#define UART_RNCR_RXNCTR_Pos 0
+#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */
+#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos)))
+/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define UART_TNPR_TXNPTR_Pos 0
+#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */
+#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos)))
+/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define UART_TNCR_TXNCTR_Pos 0
+#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */
+#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos)))
+/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */
+#define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */
+#define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */
+#define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */
+#define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */
+/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */
+#define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */
+#define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3U_UART_COMPONENT_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/component/udphs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/component/udphs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,337 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U_UDPHS_COMPONENT_
+#define _SAM3U_UDPHS_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR USB High Speed Device Port */
+/* ============================================================================= */
+/** \addtogroup SAM3U_UDPHS USB High Speed Device Port */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief UdphsDma hardware registers */
+typedef struct {
+ RwReg UDPHS_DMANXTDSC; /**< \brief (UdphsDma Offset: 0x0) UDPHS DMA Next Descriptor Address Register */
+ RwReg UDPHS_DMAADDRESS; /**< \brief (UdphsDma Offset: 0x4) UDPHS DMA Channel Address Register */
+ RwReg UDPHS_DMACONTROL; /**< \brief (UdphsDma Offset: 0x8) UDPHS DMA Channel Control Register */
+ RwReg UDPHS_DMASTATUS; /**< \brief (UdphsDma Offset: 0xC) UDPHS DMA Channel Status Register */
+} UdphsDma;
+/** \brief UdphsEpt hardware registers */
+typedef struct {
+ RwReg UDPHS_EPTCFG; /**< \brief (UdphsEpt Offset: 0x0) UDPHS Endpoint Configuration Register */
+ RwReg UDPHS_EPTCTLENB; /**< \brief (UdphsEpt Offset: 0x4) UDPHS Endpoint Control Enable Register */
+ RwReg UDPHS_EPTCTLDIS; /**< \brief (UdphsEpt Offset: 0x8) UDPHS Endpoint Control Disable Register */
+ RwReg UDPHS_EPTCTL; /**< \brief (UdphsEpt Offset: 0xC) UDPHS Endpoint Control Register */
+ RoReg Reserved1[1];
+ RwReg UDPHS_EPTSETSTA; /**< \brief (UdphsEpt Offset: 0x14) UDPHS Endpoint Set Status Register */
+ RwReg UDPHS_EPTCLRSTA; /**< \brief (UdphsEpt Offset: 0x18) UDPHS Endpoint Clear Status Register */
+ RwReg UDPHS_EPTSTA; /**< \brief (UdphsEpt Offset: 0x1C) UDPHS Endpoint Status Register */
+} UdphsEpt;
+/** \brief Udphs hardware registers */
+#define UDPHSEPT_NUMBER 7
+#define UDPHSDMA_NUMBER 6
+typedef struct {
+ RwReg UDPHS_CTRL; /**< \brief (Udphs Offset: 0x00) UDPHS Control Register */
+ RoReg UDPHS_FNUM; /**< \brief (Udphs Offset: 0x04) UDPHS Frame Number Register */
+ RoReg Reserved1[2];
+ RwReg UDPHS_IEN; /**< \brief (Udphs Offset: 0x10) UDPHS Interrupt Enable Register */
+ RoReg UDPHS_INTSTA; /**< \brief (Udphs Offset: 0x14) UDPHS Interrupt Status Register */
+ WoReg UDPHS_CLRINT; /**< \brief (Udphs Offset: 0x18) UDPHS Clear Interrupt Register */
+ WoReg UDPHS_EPTRST; /**< \brief (Udphs Offset: 0x1C) UDPHS Endpoints Reset Register */
+ RoReg Reserved2[48];
+ RwReg UDPHS_TST; /**< \brief (Udphs Offset: 0xE0) UDPHS Test Register */
+ RoReg Reserved3[7];
+ UdphsEpt UDPHS_EPT[UDPHSEPT_NUMBER]; /**< \brief (Udphs Offset: 0x100) endpoint = 0 .. 6 */
+ RoReg Reserved4[72];
+ UdphsDma UDPHS_DMA[UDPHSDMA_NUMBER]; /**< \brief (Udphs Offset: 0x300) channel = 0 .. 5 */
+} Udphs;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- UDPHS_CTRL : (UDPHS Offset: 0x00) UDPHS Control Register -------- */
+#define UDPHS_CTRL_DEV_ADDR_Pos 0
+#define UDPHS_CTRL_DEV_ADDR_Msk (0x7fu << UDPHS_CTRL_DEV_ADDR_Pos) /**< \brief (UDPHS_CTRL) UDPHS Address */
+#define UDPHS_CTRL_DEV_ADDR(value) ((UDPHS_CTRL_DEV_ADDR_Msk & ((value) << UDPHS_CTRL_DEV_ADDR_Pos)))
+#define UDPHS_CTRL_FADDR_EN (0x1u << 7) /**< \brief (UDPHS_CTRL) Function Address Enable */
+#define UDPHS_CTRL_EN_UDPHS (0x1u << 8) /**< \brief (UDPHS_CTRL) UDPHS Enable */
+#define UDPHS_CTRL_DETACH (0x1u << 9) /**< \brief (UDPHS_CTRL) Detach Command */
+#define UDPHS_CTRL_REWAKEUP (0x1u << 10) /**< \brief (UDPHS_CTRL) Send Remote Wake Up */
+#define UDPHS_CTRL_PULLD_DIS (0x1u << 11) /**< \brief (UDPHS_CTRL) Pull-Down Disable */
+/* -------- UDPHS_FNUM : (UDPHS Offset: 0x04) UDPHS Frame Number Register -------- */
+#define UDPHS_FNUM_MICRO_FRAME_NUM_Pos 0
+#define UDPHS_FNUM_MICRO_FRAME_NUM_Msk (0x7u << UDPHS_FNUM_MICRO_FRAME_NUM_Pos) /**< \brief (UDPHS_FNUM) Microframe Number */
+#define UDPHS_FNUM_FRAME_NUMBER_Pos 3
+#define UDPHS_FNUM_FRAME_NUMBER_Msk (0x7ffu << UDPHS_FNUM_FRAME_NUMBER_Pos) /**< \brief (UDPHS_FNUM) Frame Number as defined in the Packet Field Formats */
+#define UDPHS_FNUM_FNUM_ERR (0x1u << 31) /**< \brief (UDPHS_FNUM) Frame Number CRC Error */
+/* -------- UDPHS_IEN : (UDPHS Offset: 0x10) UDPHS Interrupt Enable Register -------- */
+#define UDPHS_IEN_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_IEN) Suspend Interrupt Enable */
+#define UDPHS_IEN_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_IEN) Micro-SOF Interrupt Enable */
+#define UDPHS_IEN_INT_SOF (0x1u << 3) /**< \brief (UDPHS_IEN) SOF Interrupt Enable */
+#define UDPHS_IEN_ENDRESET (0x1u << 4) /**< \brief (UDPHS_IEN) End Of Reset Interrupt Enable */
+#define UDPHS_IEN_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_IEN) Wake Up CPU Interrupt Enable */
+#define UDPHS_IEN_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_IEN) End Of Resume Interrupt Enable */
+#define UDPHS_IEN_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_IEN) Upstream Resume Interrupt Enable */
+#define UDPHS_IEN_EPT_0 (0x1u << 8) /**< \brief (UDPHS_IEN) Endpoint 0 Interrupt Enable */
+#define UDPHS_IEN_EPT_1 (0x1u << 9) /**< \brief (UDPHS_IEN) Endpoint 1 Interrupt Enable */
+#define UDPHS_IEN_EPT_2 (0x1u << 10) /**< \brief (UDPHS_IEN) Endpoint 2 Interrupt Enable */
+#define UDPHS_IEN_EPT_3 (0x1u << 11) /**< \brief (UDPHS_IEN) Endpoint 3 Interrupt Enable */
+#define UDPHS_IEN_EPT_4 (0x1u << 12) /**< \brief (UDPHS_IEN) Endpoint 4 Interrupt Enable */
+#define UDPHS_IEN_EPT_5 (0x1u << 13) /**< \brief (UDPHS_IEN) Endpoint 5 Interrupt Enable */
+#define UDPHS_IEN_EPT_6 (0x1u << 14) /**< \brief (UDPHS_IEN) Endpoint 6 Interrupt Enable */
+#define UDPHS_IEN_DMA_1 (0x1u << 25) /**< \brief (UDPHS_IEN) DMA Channel 1 Interrupt Enable */
+#define UDPHS_IEN_DMA_2 (0x1u << 26) /**< \brief (UDPHS_IEN) DMA Channel 2 Interrupt Enable */
+#define UDPHS_IEN_DMA_3 (0x1u << 27) /**< \brief (UDPHS_IEN) DMA Channel 3 Interrupt Enable */
+#define UDPHS_IEN_DMA_4 (0x1u << 28) /**< \brief (UDPHS_IEN) DMA Channel 4 Interrupt Enable */
+#define UDPHS_IEN_DMA_5 (0x1u << 29) /**< \brief (UDPHS_IEN) DMA Channel 5 Interrupt Enable */
+#define UDPHS_IEN_DMA_6 (0x1u << 30) /**< \brief (UDPHS_IEN) DMA Channel 6 Interrupt Enable */
+/* -------- UDPHS_INTSTA : (UDPHS Offset: 0x14) UDPHS Interrupt Status Register -------- */
+#define UDPHS_INTSTA_SPEED (0x1u << 0) /**< \brief (UDPHS_INTSTA) Speed Status */
+#define UDPHS_INTSTA_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_INTSTA) Suspend Interrupt */
+#define UDPHS_INTSTA_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_INTSTA) Micro Start Of Frame Interrupt */
+#define UDPHS_INTSTA_INT_SOF (0x1u << 3) /**< \brief (UDPHS_INTSTA) Start Of Frame Interrupt */
+#define UDPHS_INTSTA_ENDRESET (0x1u << 4) /**< \brief (UDPHS_INTSTA) End Of Reset Interrupt */
+#define UDPHS_INTSTA_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_INTSTA) Wake Up CPU Interrupt */
+#define UDPHS_INTSTA_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_INTSTA) End Of Resume Interrupt */
+#define UDPHS_INTSTA_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_INTSTA) Upstream Resume Interrupt */
+#define UDPHS_INTSTA_EPT_0 (0x1u << 8) /**< \brief (UDPHS_INTSTA) Endpoint 0 Interrupt */
+#define UDPHS_INTSTA_EPT_1 (0x1u << 9) /**< \brief (UDPHS_INTSTA) Endpoint 1 Interrupt */
+#define UDPHS_INTSTA_EPT_2 (0x1u << 10) /**< \brief (UDPHS_INTSTA) Endpoint 2 Interrupt */
+#define UDPHS_INTSTA_EPT_3 (0x1u << 11) /**< \brief (UDPHS_INTSTA) Endpoint 3 Interrupt */
+#define UDPHS_INTSTA_EPT_4 (0x1u << 12) /**< \brief (UDPHS_INTSTA) Endpoint 4 Interrupt */
+#define UDPHS_INTSTA_EPT_5 (0x1u << 13) /**< \brief (UDPHS_INTSTA) Endpoint 5 Interrupt */
+#define UDPHS_INTSTA_EPT_6 (0x1u << 14) /**< \brief (UDPHS_INTSTA) Endpoint 6 Interrupt */
+#define UDPHS_INTSTA_DMA_1 (0x1u << 25) /**< \brief (UDPHS_INTSTA) DMA Channel 1 Interrupt */
+#define UDPHS_INTSTA_DMA_2 (0x1u << 26) /**< \brief (UDPHS_INTSTA) DMA Channel 2 Interrupt */
+#define UDPHS_INTSTA_DMA_3 (0x1u << 27) /**< \brief (UDPHS_INTSTA) DMA Channel 3 Interrupt */
+#define UDPHS_INTSTA_DMA_4 (0x1u << 28) /**< \brief (UDPHS_INTSTA) DMA Channel 4 Interrupt */
+#define UDPHS_INTSTA_DMA_5 (0x1u << 29) /**< \brief (UDPHS_INTSTA) DMA Channel 5 Interrupt */
+#define UDPHS_INTSTA_DMA_6 (0x1u << 30) /**< \brief (UDPHS_INTSTA) DMA Channel 6 Interrupt */
+/* -------- UDPHS_CLRINT : (UDPHS Offset: 0x18) UDPHS Clear Interrupt Register -------- */
+#define UDPHS_CLRINT_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_CLRINT) Suspend Interrupt Clear */
+#define UDPHS_CLRINT_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_CLRINT) Micro Start Of Frame Interrupt Clear */
+#define UDPHS_CLRINT_INT_SOF (0x1u << 3) /**< \brief (UDPHS_CLRINT) Start Of Frame Interrupt Clear */
+#define UDPHS_CLRINT_ENDRESET (0x1u << 4) /**< \brief (UDPHS_CLRINT) End Of Reset Interrupt Clear */
+#define UDPHS_CLRINT_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_CLRINT) Wake Up CPU Interrupt Clear */
+#define UDPHS_CLRINT_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_CLRINT) End Of Resume Interrupt Clear */
+#define UDPHS_CLRINT_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_CLRINT) Upstream Resume Interrupt Clear */
+/* -------- UDPHS_EPTRST : (UDPHS Offset: 0x1C) UDPHS Endpoints Reset Register -------- */
+#define UDPHS_EPTRST_EPT_0 (0x1u << 0) /**< \brief (UDPHS_EPTRST) Endpoint 0 Reset */
+#define UDPHS_EPTRST_EPT_1 (0x1u << 1) /**< \brief (UDPHS_EPTRST) Endpoint 1 Reset */
+#define UDPHS_EPTRST_EPT_2 (0x1u << 2) /**< \brief (UDPHS_EPTRST) Endpoint 2 Reset */
+#define UDPHS_EPTRST_EPT_3 (0x1u << 3) /**< \brief (UDPHS_EPTRST) Endpoint 3 Reset */
+#define UDPHS_EPTRST_EPT_4 (0x1u << 4) /**< \brief (UDPHS_EPTRST) Endpoint 4 Reset */
+#define UDPHS_EPTRST_EPT_5 (0x1u << 5) /**< \brief (UDPHS_EPTRST) Endpoint 5 Reset */
+#define UDPHS_EPTRST_EPT_6 (0x1u << 6) /**< \brief (UDPHS_EPTRST) Endpoint 6 Reset */
+/* -------- UDPHS_TST : (UDPHS Offset: 0xE0) UDPHS Test Register -------- */
+#define UDPHS_TST_SPEED_CFG_Pos 0
+#define UDPHS_TST_SPEED_CFG_Msk (0x3u << UDPHS_TST_SPEED_CFG_Pos) /**< \brief (UDPHS_TST) Speed Configuration */
+#define UDPHS_TST_SPEED_CFG_NORMAL (0x0u << 0) /**< \brief (UDPHS_TST) Normal Mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host supports it and then to automatically switch to High Speed mode */
+#define UDPHS_TST_SPEED_CFG_HIGH_SPEED (0x2u << 0) /**< \brief (UDPHS_TST) Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug or test purpose. */
+#define UDPHS_TST_SPEED_CFG_FULL_SPEED (0x3u << 0) /**< \brief (UDPHS_TST) Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this configuration, the macro will not respond to a High Speed reset handshake. */
+#define UDPHS_TST_TST_J (0x1u << 2) /**< \brief (UDPHS_TST) Test J Mode */
+#define UDPHS_TST_TST_K (0x1u << 3) /**< \brief (UDPHS_TST) Test K Mode */
+#define UDPHS_TST_TST_PKT (0x1u << 4) /**< \brief (UDPHS_TST) Test Packet Mode */
+#define UDPHS_TST_OPMODE2 (0x1u << 5) /**< \brief (UDPHS_TST) OpMode2 */
+/* -------- UDPHS_EPTCFG : (UDPHS Offset: N/A) UDPHS Endpoint Configuration Register -------- */
+#define UDPHS_EPTCFG_EPT_SIZE_Pos 0
+#define UDPHS_EPTCFG_EPT_SIZE_Msk (0x7u << UDPHS_EPTCFG_EPT_SIZE_Pos) /**< \brief (UDPHS_EPTCFG) Endpoint Size */
+#define UDPHS_EPTCFG_EPT_SIZE_8 (0x0u << 0) /**< \brief (UDPHS_EPTCFG) 8 bytes */
+#define UDPHS_EPTCFG_EPT_SIZE_16 (0x1u << 0) /**< \brief (UDPHS_EPTCFG) 16 bytes */
+#define UDPHS_EPTCFG_EPT_SIZE_32 (0x2u << 0) /**< \brief (UDPHS_EPTCFG) 32 bytes */
+#define UDPHS_EPTCFG_EPT_SIZE_64 (0x3u << 0) /**< \brief (UDPHS_EPTCFG) 64 bytes */
+#define UDPHS_EPTCFG_EPT_SIZE_128 (0x4u << 0) /**< \brief (UDPHS_EPTCFG) 128 bytes */
+#define UDPHS_EPTCFG_EPT_SIZE_256 (0x5u << 0) /**< \brief (UDPHS_EPTCFG) 256 bytes */
+#define UDPHS_EPTCFG_EPT_SIZE_512 (0x6u << 0) /**< \brief (UDPHS_EPTCFG) 512 bytes */
+#define UDPHS_EPTCFG_EPT_SIZE_1024 (0x7u << 0) /**< \brief (UDPHS_EPTCFG) 1024 bytes */
+#define UDPHS_EPTCFG_EPT_DIR (0x1u << 3) /**< \brief (UDPHS_EPTCFG) Endpoint Direction */
+#define UDPHS_EPTCFG_EPT_TYPE_Pos 4
+#define UDPHS_EPTCFG_EPT_TYPE_Msk (0x3u << UDPHS_EPTCFG_EPT_TYPE_Pos) /**< \brief (UDPHS_EPTCFG) Endpoint Type */
+#define UDPHS_EPTCFG_EPT_TYPE_CTRL8 (0x0u << 4) /**< \brief (UDPHS_EPTCFG) Control endpoint */
+#define UDPHS_EPTCFG_EPT_TYPE_ISO (0x1u << 4) /**< \brief (UDPHS_EPTCFG) Isochronous endpoint */
+#define UDPHS_EPTCFG_EPT_TYPE_BULK (0x2u << 4) /**< \brief (UDPHS_EPTCFG) Bulk endpoint */
+#define UDPHS_EPTCFG_EPT_TYPE_INT (0x3u << 4) /**< \brief (UDPHS_EPTCFG) Interrupt endpoint */
+#define UDPHS_EPTCFG_BK_NUMBER_Pos 6
+#define UDPHS_EPTCFG_BK_NUMBER_Msk (0x3u << UDPHS_EPTCFG_BK_NUMBER_Pos) /**< \brief (UDPHS_EPTCFG) Number of Banks */
+#define UDPHS_EPTCFG_BK_NUMBER_0 (0x0u << 6) /**< \brief (UDPHS_EPTCFG) Zero bank, the endpoint is not mapped in memory */
+#define UDPHS_EPTCFG_BK_NUMBER_1 (0x1u << 6) /**< \brief (UDPHS_EPTCFG) One bank (bank 0) */
+#define UDPHS_EPTCFG_BK_NUMBER_2 (0x2u << 6) /**< \brief (UDPHS_EPTCFG) Double bank (Ping-Pong: bank0/bank1) */
+#define UDPHS_EPTCFG_BK_NUMBER_3 (0x3u << 6) /**< \brief (UDPHS_EPTCFG) Triple bank (bank0/bank1/bank2) */
+#define UDPHS_EPTCFG_NB_TRANS_Pos 8
+#define UDPHS_EPTCFG_NB_TRANS_Msk (0x3u << UDPHS_EPTCFG_NB_TRANS_Pos) /**< \brief (UDPHS_EPTCFG) Number Of Transaction per Microframe */
+#define UDPHS_EPTCFG_NB_TRANS(value) ((UDPHS_EPTCFG_NB_TRANS_Msk & ((value) << UDPHS_EPTCFG_NB_TRANS_Pos)))
+#define UDPHS_EPTCFG_EPT_MAPD (0x1u << 31) /**< \brief (UDPHS_EPTCFG) Endpoint Mapped */
+/* -------- UDPHS_EPTCTLENB : (UDPHS Offset: N/A) UDPHS Endpoint Control Enable Register -------- */
+#define UDPHS_EPTCTLENB_EPT_ENABL (0x1u << 0) /**< \brief (UDPHS_EPTCTLENB) Endpoint Enable */
+#define UDPHS_EPTCTLENB_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTLENB) Packet Auto-Valid Enable */
+#define UDPHS_EPTCTLENB_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTLENB) Interrupts Disable DMA */
+#define UDPHS_EPTCTLENB_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTLENB) NYET Disable (Only for High Speed Bulk OUT endpoints) */
+#define UDPHS_EPTCTLENB_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTLENB) Overflow Error Interrupt Enable */
+#define UDPHS_EPTCTLENB_RXRDY_TXKL (0x1u << 9) /**< \brief (UDPHS_EPTCTLENB) Received OUT Data Interrupt Enable */
+#define UDPHS_EPTCTLENB_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTLENB) Transmitted IN Data Complete Interrupt Enable */
+#define UDPHS_EPTCTLENB_TXRDY (0x1u << 11) /**< \brief (UDPHS_EPTCTLENB) TX Packet Ready Interrupt Enable */
+#define UDPHS_EPTCTLENB_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTLENB) Received SETUP */
+#define UDPHS_EPTCTLENB_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTLENB) Stall Sent Interrupt Enable */
+#define UDPHS_EPTCTLENB_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTLENB) NAKIN Interrupt Enable */
+#define UDPHS_EPTCTLENB_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTLENB) NAKOUT Interrupt Enable */
+#define UDPHS_EPTCTLENB_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTLENB) Busy Bank Interrupt Enable */
+#define UDPHS_EPTCTLENB_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTLENB) Short Packet Send/Short Packet Interrupt Enable */
+#define UDPHS_EPTCTLENB_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTLENB) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
+#define UDPHS_EPTCTLENB_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTLENB) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
+#define UDPHS_EPTCTLENB_TXRDY_TRER (0x1u << 11) /**< \brief (UDPHS_EPTCTLENB) TX Packet Ready/Transaction Error Interrupt Enable */
+#define UDPHS_EPTCTLENB_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTLENB) Error Flow Interrupt Enable */
+#define UDPHS_EPTCTLENB_ERR_CRC_NTR (0x1u << 13) /**< \brief (UDPHS_EPTCTLENB) ISO CRC Error/Number of Transaction Error Interrupt Enable */
+#define UDPHS_EPTCTLENB_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTLENB) Bank Flush Error Interrupt Enable */
+/* -------- UDPHS_EPTCTLDIS : (UDPHS Offset: N/A) UDPHS Endpoint Control Disable Register -------- */
+#define UDPHS_EPTCTLDIS_EPT_DISABL (0x1u << 0) /**< \brief (UDPHS_EPTCTLDIS) Endpoint Disable */
+#define UDPHS_EPTCTLDIS_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTLDIS) Packet Auto-Valid Disable */
+#define UDPHS_EPTCTLDIS_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTLDIS) Interrupts Disable DMA */
+#define UDPHS_EPTCTLDIS_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTLDIS) NYET Enable (Only for High Speed Bulk OUT endpoints) */
+#define UDPHS_EPTCTLDIS_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTLDIS) Overflow Error Interrupt Disable */
+#define UDPHS_EPTCTLDIS_RXRDY_TXKL (0x1u << 9) /**< \brief (UDPHS_EPTCTLDIS) Received OUT Data Interrupt Disable */
+#define UDPHS_EPTCTLDIS_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTLDIS) Transmitted IN Data Complete Interrupt Disable */
+#define UDPHS_EPTCTLDIS_TXRDY (0x1u << 11) /**< \brief (UDPHS_EPTCTLDIS) TX Packet Ready Interrupt Disable */
+#define UDPHS_EPTCTLDIS_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTLDIS) Received SETUP Interrupt Disable */
+#define UDPHS_EPTCTLDIS_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTLDIS) Stall Sent Interrupt Disable */
+#define UDPHS_EPTCTLDIS_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTLDIS) NAKIN Interrupt Disable */
+#define UDPHS_EPTCTLDIS_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTLDIS) NAKOUT Interrupt Disable */
+#define UDPHS_EPTCTLDIS_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTLDIS) Busy Bank Interrupt Disable */
+#define UDPHS_EPTCTLDIS_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTLDIS) Short Packet Interrupt Disable */
+#define UDPHS_EPTCTLDIS_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTLDIS) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
+#define UDPHS_EPTCTLDIS_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTLDIS) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
+#define UDPHS_EPTCTLDIS_TXRDY_TRER (0x1u << 11) /**< \brief (UDPHS_EPTCTLDIS) TX Packet Ready/Transaction Error Interrupt Disable */
+#define UDPHS_EPTCTLDIS_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTLDIS) Error Flow Interrupt Disable */
+#define UDPHS_EPTCTLDIS_ERR_CRC_NTR (0x1u << 13) /**< \brief (UDPHS_EPTCTLDIS) ISO CRC Error/Number of Transaction Error Interrupt Disable */
+#define UDPHS_EPTCTLDIS_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTLDIS) bank flush error Interrupt Disable */
+/* -------- UDPHS_EPTCTL : (UDPHS Offset: N/A) UDPHS Endpoint Control Register -------- */
+#define UDPHS_EPTCTL_EPT_ENABL (0x1u << 0) /**< \brief (UDPHS_EPTCTL) Endpoint Enable */
+#define UDPHS_EPTCTL_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTL) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */
+#define UDPHS_EPTCTL_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTL) Interrupt Disables DMA */
+#define UDPHS_EPTCTL_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTL) NYET Disable (Only for High Speed Bulk OUT endpoints) */
+#define UDPHS_EPTCTL_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTL) Overflow Error Interrupt Enabled */
+#define UDPHS_EPTCTL_RXRDY_TXKL (0x1u << 9) /**< \brief (UDPHS_EPTCTL) Received OUT Data Interrupt Enabled */
+#define UDPHS_EPTCTL_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTL) Transmitted IN Data Complete Interrupt Enabled */
+#define UDPHS_EPTCTL_TXRDY (0x1u << 11) /**< \brief (UDPHS_EPTCTL) TX Packet Ready Interrupt Enabled */
+#define UDPHS_EPTCTL_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTL) Received SETUP Interrupt Enabled */
+#define UDPHS_EPTCTL_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTL) Stall Sent Interrupt Enabled */
+#define UDPHS_EPTCTL_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTL) NAKIN Interrupt Enabled */
+#define UDPHS_EPTCTL_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTL) NAKOUT Interrupt Enabled */
+#define UDPHS_EPTCTL_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTL) Busy Bank Interrupt Enabled */
+#define UDPHS_EPTCTL_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTL) Short Packet Interrupt Enabled */
+#define UDPHS_EPTCTL_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTL) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */
+#define UDPHS_EPTCTL_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTL) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */
+#define UDPHS_EPTCTL_TXRDY_TRER (0x1u << 11) /**< \brief (UDPHS_EPTCTL) TX Packet Ready/Transaction Error Interrupt Enabled */
+#define UDPHS_EPTCTL_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTL) Error Flow Interrupt Enabled */
+#define UDPHS_EPTCTL_ERR_CRC_NTR (0x1u << 13) /**< \brief (UDPHS_EPTCTL) ISO CRC Error/Number of Transaction Error Interrupt Enabled */
+#define UDPHS_EPTCTL_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTL) Bank Flush Error Interrupt Enabled */
+/* -------- UDPHS_EPTSETSTA : (UDPHS Offset: N/A) UDPHS Endpoint Set Status Register -------- */
+#define UDPHS_EPTSETSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTSETSTA) Stall Handshake Request Set */
+#define UDPHS_EPTSETSTA_RXRDY_TXKL (0x1u << 9) /**< \brief (UDPHS_EPTSETSTA) KILL Bank Set (for IN Endpoint) */
+#define UDPHS_EPTSETSTA_TXRDY (0x1u << 11) /**< \brief (UDPHS_EPTSETSTA) TX Packet Ready Set */
+#define UDPHS_EPTSETSTA_TXRDY_TRER (0x1u << 11) /**< \brief (UDPHS_EPTSETSTA) TX Packet Ready Set */
+/* -------- UDPHS_EPTCLRSTA : (UDPHS Offset: N/A) UDPHS Endpoint Clear Status Register -------- */
+#define UDPHS_EPTCLRSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTCLRSTA) Stall Handshake Request Clear */
+#define UDPHS_EPTCLRSTA_TOGGLESQ (0x1u << 6) /**< \brief (UDPHS_EPTCLRSTA) Data Toggle Clear */
+#define UDPHS_EPTCLRSTA_RXRDY_TXKL (0x1u << 9) /**< \brief (UDPHS_EPTCLRSTA) Received OUT Data Clear */
+#define UDPHS_EPTCLRSTA_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCLRSTA) Transmitted IN Data Complete Clear */
+#define UDPHS_EPTCLRSTA_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCLRSTA) Received SETUP Clear */
+#define UDPHS_EPTCLRSTA_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCLRSTA) Stall Sent Clear */
+#define UDPHS_EPTCLRSTA_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCLRSTA) NAKIN Clear */
+#define UDPHS_EPTCLRSTA_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCLRSTA) NAKOUT Clear */
+#define UDPHS_EPTCLRSTA_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCLRSTA) Error Flow Clear */
+#define UDPHS_EPTCLRSTA_ERR_CRC_NTR (0x1u << 13) /**< \brief (UDPHS_EPTCLRSTA) Number of Transaction Error Clear */
+#define UDPHS_EPTCLRSTA_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCLRSTA) Bank Flush Error Clear */
+/* -------- UDPHS_EPTSTA : (UDPHS Offset: N/A) UDPHS Endpoint Status Register -------- */
+#define UDPHS_EPTSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTSTA) Stall Handshake Request */
+#define UDPHS_EPTSTA_TOGGLESQ_STA_Pos 6
+#define UDPHS_EPTSTA_TOGGLESQ_STA_Msk (0x3u << UDPHS_EPTSTA_TOGGLESQ_STA_Pos) /**< \brief (UDPHS_EPTSTA) Toggle Sequencing */
+#define UDPHS_EPTSTA_TOGGLESQ_STA_DATA0 (0x0u << 6) /**< \brief (UDPHS_EPTSTA) DATA0 */
+#define UDPHS_EPTSTA_TOGGLESQ_STA_DATA1 (0x1u << 6) /**< \brief (UDPHS_EPTSTA) DATA1 */
+#define UDPHS_EPTSTA_TOGGLESQ_STA_DATA2 (0x2u << 6) /**< \brief (UDPHS_EPTSTA) Reserved for High Bandwidth Isochronous Endpoint */
+#define UDPHS_EPTSTA_TOGGLESQ_STA_MDATA (0x3u << 6) /**< \brief (UDPHS_EPTSTA) Reserved for High Bandwidth Isochronous Endpoint */
+#define UDPHS_EPTSTA_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTSTA) Overflow Error */
+#define UDPHS_EPTSTA_RXRDY_TXKL (0x1u << 9) /**< \brief (UDPHS_EPTSTA) Received OUT Data/KILL Bank */
+#define UDPHS_EPTSTA_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTSTA) Transmitted IN Data Complete */
+#define UDPHS_EPTSTA_TXRDY (0x1u << 11) /**< \brief (UDPHS_EPTSTA) TX Packet Ready */
+#define UDPHS_EPTSTA_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTSTA) Received SETUP */
+#define UDPHS_EPTSTA_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTSTA) Stall Sent */
+#define UDPHS_EPTSTA_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTSTA) NAK IN */
+#define UDPHS_EPTSTA_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTSTA) NAK OUT */
+#define UDPHS_EPTSTA_CURBK_CTLDIR_Pos 16
+#define UDPHS_EPTSTA_CURBK_CTLDIR_Msk (0x3u << UDPHS_EPTSTA_CURBK_CTLDIR_Pos) /**< \brief (UDPHS_EPTSTA) Current Bank/Control Direction */
+#define UDPHS_EPTSTA_BUSY_BANK_STA_Pos 18
+#define UDPHS_EPTSTA_BUSY_BANK_STA_Msk (0x3u << UDPHS_EPTSTA_BUSY_BANK_STA_Pos) /**< \brief (UDPHS_EPTSTA) Busy Bank Number */
+#define UDPHS_EPTSTA_BUSY_BANK_STA_1BUSYBANK (0x0u << 18) /**< \brief (UDPHS_EPTSTA) 1 busy bank */
+#define UDPHS_EPTSTA_BUSY_BANK_STA_2BUSYBANKS (0x1u << 18) /**< \brief (UDPHS_EPTSTA) 2 busy banks */
+#define UDPHS_EPTSTA_BUSY_BANK_STA_3BUSYBANKS (0x2u << 18) /**< \brief (UDPHS_EPTSTA) 3 busy banks */
+#define UDPHS_EPTSTA_BYTE_COUNT_Pos 20
+#define UDPHS_EPTSTA_BYTE_COUNT_Msk (0x7ffu << UDPHS_EPTSTA_BYTE_COUNT_Pos) /**< \brief (UDPHS_EPTSTA) UDPHS Byte Count */
+#define UDPHS_EPTSTA_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTSTA) Short Packet */
+#define UDPHS_EPTSTA_TXRDY_TRER (0x1u << 11) /**< \brief (UDPHS_EPTSTA) TX Packet Ready/Transaction Error */
+#define UDPHS_EPTSTA_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTSTA) Error Flow */
+#define UDPHS_EPTSTA_ERR_CRC_NTR (0x1u << 13) /**< \brief (UDPHS_EPTSTA) CRC ISO Error/Number of Transaction Error */
+#define UDPHS_EPTSTA_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTSTA) Bank Flush Error */
+#define UDPHS_EPTSTA_CURBK_Pos 16
+#define UDPHS_EPTSTA_CURBK_Msk (0x3u << UDPHS_EPTSTA_CURBK_Pos) /**< \brief (UDPHS_EPTSTA) Current Bank */
+#define UDPHS_EPTSTA_CURBK_BANK0 (0x0u << 16) /**< \brief (UDPHS_EPTSTA) Bank 0 (or single bank) */
+#define UDPHS_EPTSTA_CURBK_BANK1 (0x1u << 16) /**< \brief (UDPHS_EPTSTA) Bank 1 */
+#define UDPHS_EPTSTA_CURBK_BANK2 (0x2u << 16) /**< \brief (UDPHS_EPTSTA) Bank 2 */
+/* -------- UDPHS_DMANXTDSC : (UDPHS Offset: N/A) UDPHS DMA Next Descriptor Address Register -------- */
+#define UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos 0
+#define UDPHS_DMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UDPHS_DMANXTDSC) Next Descriptor Address */
+#define UDPHS_DMANXTDSC_NXT_DSC_ADD(value) ((UDPHS_DMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos)))
+/* -------- UDPHS_DMAADDRESS : (UDPHS Offset: N/A) UDPHS DMA Channel Address Register -------- */
+#define UDPHS_DMAADDRESS_BUFF_ADD_Pos 0
+#define UDPHS_DMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UDPHS_DMAADDRESS_BUFF_ADD_Pos) /**< \brief (UDPHS_DMAADDRESS) Buffer Address */
+#define UDPHS_DMAADDRESS_BUFF_ADD(value) ((UDPHS_DMAADDRESS_BUFF_ADD_Msk & ((value) << UDPHS_DMAADDRESS_BUFF_ADD_Pos)))
+/* -------- UDPHS_DMACONTROL : (UDPHS Offset: N/A) UDPHS DMA Channel Control Register -------- */
+#define UDPHS_DMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UDPHS_DMACONTROL) (Channel Enable Command) */
+#define UDPHS_DMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UDPHS_DMACONTROL) Load Next Channel Transfer Descriptor Enable (Command) */
+#define UDPHS_DMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UDPHS_DMACONTROL) End of Transfer Enable (Control) */
+#define UDPHS_DMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UDPHS_DMACONTROL) End of Buffer Enable (Control) */
+#define UDPHS_DMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UDPHS_DMACONTROL) End of Transfer Interrupt Enable */
+#define UDPHS_DMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UDPHS_DMACONTROL) End of Buffer Interrupt Enable */
+#define UDPHS_DMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UDPHS_DMACONTROL) Descriptor Loaded Interrupt Enable */
+#define UDPHS_DMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UDPHS_DMACONTROL) Burst Lock Enable */
+#define UDPHS_DMACONTROL_BUFF_LENGTH_Pos 16
+#define UDPHS_DMACONTROL_BUFF_LENGTH_Msk (0xffffu << UDPHS_DMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UDPHS_DMACONTROL) Buffer Byte Length (Write-only) */
+#define UDPHS_DMACONTROL_BUFF_LENGTH(value) ((UDPHS_DMACONTROL_BUFF_LENGTH_Msk & ((value) << UDPHS_DMACONTROL_BUFF_LENGTH_Pos)))
+/* -------- UDPHS_DMASTATUS : (UDPHS Offset: N/A) UDPHS DMA Channel Status Register -------- */
+#define UDPHS_DMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UDPHS_DMASTATUS) Channel Enable Status */
+#define UDPHS_DMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UDPHS_DMASTATUS) Channel Active Status */
+#define UDPHS_DMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UDPHS_DMASTATUS) End of Channel Transfer Status */
+#define UDPHS_DMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UDPHS_DMASTATUS) End of Channel Buffer Status */
+#define UDPHS_DMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UDPHS_DMASTATUS) Descriptor Loaded Status */
+#define UDPHS_DMASTATUS_BUFF_COUNT_Pos 16
+#define UDPHS_DMASTATUS_BUFF_COUNT_Msk (0xffffu << UDPHS_DMASTATUS_BUFF_COUNT_Pos) /**< \brief (UDPHS_DMASTATUS) Buffer Byte Count */
+#define UDPHS_DMASTATUS_BUFF_COUNT(value) ((UDPHS_DMASTATUS_BUFF_COUNT_Msk & ((value) << UDPHS_DMASTATUS_BUFF_COUNT_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3U_UDPHS_COMPONENT_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/component/usart.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/component/usart.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,356 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U_USART_COMPONENT_
+#define _SAM3U_USART_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3U_USART Universal Synchronous Asynchronous Receiver Transmitter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Usart hardware registers */
+typedef struct {
+ WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */
+ RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */
+ WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */
+ WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */
+ RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */
+ RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */
+ RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */
+ WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */
+ RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */
+ RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */
+ RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */
+ RoReg Reserved1[5];
+ RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */
+ RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */
+ RoReg Reserved2[1];
+ RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */
+ RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */
+ RoReg Reserved3[36];
+ RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */
+ RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */
+ RoReg Reserved4[5];
+ RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */
+ RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */
+ RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */
+ RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */
+ RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */
+ RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */
+ RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */
+ RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */
+ WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */
+ RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */
+} Usart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
+#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */
+#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */
+#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */
+#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */
+#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */
+#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */
+#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */
+#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */
+#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */
+#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */
+#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */
+#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */
+#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */
+#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */
+#define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */
+#define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */
+#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */
+#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */
+#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */
+#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */
+/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
+#define US_MR_USART_MODE_Pos 0
+#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) USART Mode of Operation */
+#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */
+#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */
+#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */
+#define US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */
+#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */
+#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */
+#define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */
+#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */
+#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */
+#define US_MR_USCLKS_Pos 4
+#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */
+#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */
+#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */
+#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */
+#define US_MR_CHRL_Pos 6
+#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */
+#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */
+#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */
+#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */
+#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */
+#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */
+#define US_MR_PAR_Pos 9
+#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */
+#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */
+#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */
+#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */
+#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */
+#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */
+#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */
+#define US_MR_NBSTOP_Pos 12
+#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */
+#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */
+#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */
+#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */
+#define US_MR_CHMODE_Pos 14
+#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */
+#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */
+#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */
+#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */
+#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */
+#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */
+#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */
+#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */
+#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */
+#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */
+#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */
+#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */
+#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) INverted Data */
+#define US_MR_MAX_ITERATION_Pos 24
+#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) Maximum Number of Automatic Iteration */
+#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
+#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */
+#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */
+#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */
+#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */
+#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */
+#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */
+#define US_MR_WRDBT (0x1u << 20) /**< \brief (US_MR) Wait Read Data Before Transfer */
+/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
+#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
+#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
+#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
+#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable (available in all USART modes of operation) */
+#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable (available in all USART modes of operation) */
+#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
+#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
+#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
+#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */
+#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
+#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached Interrupt Enable */
+#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable (available in all USART modes of operation) */
+#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable (available in all USART modes of operation) */
+#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non AcknowledgeInterrupt Enable */
+#define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */
+#define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */
+#define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */
+#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
+#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */
+#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error Interrupt Enable */
+/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
+#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
+#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
+#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
+#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable (available in all USART modes of operation) */
+#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable (available in all USART modes of operation) */
+#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Enable */
+#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
+#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
+#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */
+#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
+#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max number of Repetitions Reached Interrupt Disable */
+#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable (available in all USART modes of operation) */
+#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable (available in all USART modes of operation) */
+#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non AcknowledgeInterrupt Disable */
+#define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */
+#define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */
+#define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */
+#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
+#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */
+#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Interrupt Disable */
+/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
+#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
+#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
+#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
+#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask (available in all USART modes of operation) */
+#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask (available in all USART modes of operation) */
+#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
+#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
+#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
+#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */
+#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
+#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max number of Repetitions Reached Interrupt Mask */
+#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask (available in all USART modes of operation) */
+#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask (available in all USART modes of operation) */
+#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non AcknowledgeInterrupt Mask */
+#define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */
+#define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */
+#define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */
+#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
+#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */
+#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Interrupt Mask */
+/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
+#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */
+#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */
+#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */
+#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */
+#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */
+#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */
+#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */
+#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */
+#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */
+#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */
+#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */
+#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */
+#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */
+#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non AcknowledgeInterrupt */
+#define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */
+#define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */
+#define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */
+#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */
+#define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */
+#define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */
+#define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */
+#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */
+#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */
+#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) Underrun Error */
+/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */
+#define US_RHR_RXCHR_Pos 0
+#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */
+#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */
+/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */
+#define US_THR_TXCHR_Pos 0
+#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */
+#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
+#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */
+/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define US_BRGR_CD_Pos 0
+#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */
+#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
+#define US_BRGR_FP_Pos 16
+#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */
+#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
+/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
+#define US_RTOR_TO_Pos 0
+#define US_RTOR_TO_Msk (0xffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */
+#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
+/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
+#define US_TTGR_TG_Pos 0
+#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */
+#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
+/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
+#define US_FIDI_FI_DI_RATIO_Pos 0
+#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */
+#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
+/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
+#define US_NER_NB_ERRORS_Pos 0
+#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */
+/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
+#define US_IF_IRDA_FILTER_Pos 0
+#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */
+#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))
+/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */
+#define US_MAN_TX_PL_Pos 0
+#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */
+#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))
+#define US_MAN_TX_PP_Pos 8
+#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */
+#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */
+#define US_MAN_RX_PL_Pos 16
+#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */
+#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))
+#define US_MAN_RX_PP_Pos 24
+#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */
+#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */
+#define US_MAN_ONE (0x1u << 29) /**< \brief (US_MAN) Must Be Set to 1 */
+#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift compensation */
+/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */
+#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */
+#define US_WPMR_WPKEY_Pos 8
+#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */
+#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
+/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */
+#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */
+#define US_WPSR_WPVSRC_Pos 8
+#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */
+/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */
+#define US_RPR_RXPTR_Pos 0
+#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */
+#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos)))
+/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */
+#define US_RCR_RXCTR_Pos 0
+#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */
+#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos)))
+/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */
+#define US_TPR_TXPTR_Pos 0
+#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */
+#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos)))
+/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */
+#define US_TCR_TXCTR_Pos 0
+#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */
+#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos)))
+/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */
+#define US_RNPR_RXNPTR_Pos 0
+#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */
+#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos)))
+/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */
+#define US_RNCR_RXNCTR_Pos 0
+#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */
+#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos)))
+/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define US_TNPR_TXNPTR_Pos 0
+#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */
+#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos)))
+/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define US_TNCR_TXNCTR_Pos 0
+#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */
+#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos)))
+/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */
+#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */
+#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */
+#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */
+#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */
+/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */
+#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */
+#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3U_USART_COMPONENT_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/component/wdt.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/component/wdt.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,72 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U_WDT_COMPONENT_
+#define _SAM3U_WDT_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Watchdog Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3U_WDT Watchdog Timer */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Wdt hardware registers */
+typedef struct {
+ WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */
+ RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */
+ RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */
+} Wdt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */
+#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */
+#define WDT_CR_KEY_Pos 24
+#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */
+#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))
+/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */
+#define WDT_MR_WDV_Pos 0
+#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */
+#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))
+#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */
+#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */
+#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */
+#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */
+#define WDT_MR_WDD_Pos 16
+#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */
+#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))
+#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */
+#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */
+/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */
+#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */
+#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */
+
+/*@}*/
+
+
+#endif /* _SAM3U_WDT_COMPONENT_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/daplink_addr.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/daplink_addr.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,82 @@ +/** + * @file daplink_addr.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef DAPLINK_ADDR_H +#define DAPLINK_ADDR_H + +/* Device sizes */ + +#define DAPLINK_ROM_START 0x00080000 +#define DAPLINK_ROM_SIZE 0x00020000 + +#define DAPLINK_RAM_START 0x2007C000 +#define DAPLINK_RAM_SIZE 0x00008000 + +/* ROM sizes */ + +#define DAPLINK_ROM_BL_START 0x00080000 +#define DAPLINK_ROM_BL_SIZE 0x00008000 + +#define DAPLINK_ROM_CONFIG_ADMIN_START 0x00088000 +#define DAPLINK_ROM_CONFIG_ADMIN_SIZE 0x00000000 + +#define DAPLINK_ROM_IF_START 0x00088000 +#define DAPLINK_ROM_IF_SIZE 0x00017000 + +#define DAPLINK_ROM_CONFIG_USER_START 0x0009F000 +#define DAPLINK_ROM_CONFIG_USER_SIZE 0x00001000 + +/* RAM sizes */ + +#define DAPLINK_RAM_APP_START 0x2007C000 +#define DAPLINK_RAM_APP_SIZE 0x00007F00 + +#define DAPLINK_RAM_SHARED_START 0x20083F00 +#define DAPLINK_RAM_SHARED_SIZE 0x00000100 + +/* Flash Programming Info */ + +#define DAPLINK_SECTOR_SIZE 0x00000400 +#define DAPLINK_MIN_WRITE_SIZE 0x00000400 + +/* Current build */ + +#if defined(DAPLINK_BL) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_BL_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_IF_SIZE + +#elif defined(DAPLINK_IF) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_IF_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_BL_SIZE + +#else + +#error "Build must be either bootloader or interface" + +#endif + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/flash_hal_SAM3U.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/flash_hal_SAM3U.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,216 @@
+/**
+ * @file flash_hal_SAM3U.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+//#include "flash_hal.h" // FlashOS Structures //TODO - uncomment
+#include "target_config.h" // target_device
+#include "cortex_m.h"
+#include "target_board.h"
+
+#define KEY_VALUE (0x5A)
+#define FCMD_WP (0x1) // "Write page" command
+#define FCMD_EWP (0x3) // "Erase page and write page" command
+#define FCMD_CLB (0x9) // "Clear lock bit" command
+#define FCMD_GLB (0xA) // "Get lock bit" command
+#define FCMD_SGPB (0xB) // "Set General Purpose Bit" command
+#define FCMD_CGPB (0xC) // "Clear General Purpose Bit" command
+#define FCMD_GGPB (0xD) // "Get General Purpose Bit" command
+#define FCMD_EA (0x5) // "Erase all" command
+#define FMR_FWS (0xF << 8)
+
+#define WDT_CR *(volatile uint32_t*)(0x400E1250)
+#define WDT_MR *(volatile uint32_t*)(0x400E1254)
+#define WDT_SR *(volatile uint32_t*)(0x400E1258)
+
+#define EEFC0_BASEADDR (0x400E0800)
+#define EEFC1_BASEADDR (0x400E0A00)
+#define FMR_FAM (1 << 24)
+#define GPNVMB_BMS (1)
+
+typedef struct {
+ volatile uint32_t MC_FMR;
+ volatile uint32_t MC_FCR;
+ volatile uint32_t MC_FSR;
+ volatile uint32_t MC_FRR;
+} SFR_TABLE;
+
+__attribute__((section("ram_func")))
+static void _FeedWDT(void)
+{
+ //
+ // Feed watchdog if enabled
+ //
+ if ((WDT_MR & (1 << 15)) == 0) { // Is watchdog enabled ?
+ WDT_CR = 0xA5000001; // Feed it!
+ }
+}
+
+/*********************************************************************
+*
+* Static code
+*
+**********************************************************************
+*/
+
+__attribute__((section("ram_func")))
+static void _WritePage(uint32_t Addr, volatile uint32_t *pSrc, int PerformErase)
+{
+ SFR_TABLE *pSFRs;
+ volatile uint32_t *pDest;
+ uint32_t NumItemsInPageLeft;
+ uint32_t iPage;
+ uint32_t Status;
+ //
+ // Return value 0 == O.K.
+ // Return value 1 == Error
+ // Application assumes that this function always erases 4 KB
+ // Application always calls this function with 4 KB aligned addresses
+ //
+ Addr |= 0x80000; // Convert to physical flash address
+ pSFRs = (SFR_TABLE *)(EEFC0_BASEADDR);
+ pDest = (volatile uint32_t *)Addr;
+ //
+ // Fill page buffer use blank data in case of erase is requested
+ //
+ iPage = ((Addr - 0x80000) >> 8);
+ NumItemsInPageLeft = (1 << 8) >> 2;
+
+ if (PerformErase) {
+ do {
+ *pDest++ = 0xFFFFFFFF;
+ } while (--NumItemsInPageLeft);
+
+ } else {
+ do {
+ *pDest++ = *pSrc++;
+ } while (--NumItemsInPageLeft);
+ }
+
+ //
+ // Trigger flash operation
+ //
+ pSFRs->MC_FCR = (KEY_VALUE << 24) | (FCMD_EWP << 0) | (iPage << 8); // Erase page and write with blank data
+
+ do {
+ _FeedWDT();
+ Status = pSFRs->MC_FSR;
+ } while ((Status & 1) == 0);
+}
+
+/*********************************************************************
+*
+* Public code
+*
+**********************************************************************
+*/
+__attribute__((section("ram_func")))
+uint32_t Init(uint32_t adr, uint32_t clk, uint32_t fnc)
+{
+ //
+ // No special init required
+ //
+ return (0);
+}
+
+__attribute__((section("ram_func")))
+uint32_t UnInit(uint32_t fnc)
+{
+ //
+ // No special uninit required
+ //
+ return (0);
+}
+
+__attribute__((section("ram_func")))
+uint32_t EraseChip(void)
+{
+ if (g_board_info.target_cfg) {
+ uint32_t Addr;
+ //
+ // Return value 0 == O.K.
+ // Return value 1 == Error
+ // Erase complete chip by erasing sector-by-sector
+ Addr = g_board_info.target_cfg->flash_regions[0].start; //bootloader, interface flashing only concerns 1 flash region
+
+ cortex_int_state_t state = cortex_int_get_and_disable();
+ do {
+ _WritePage(Addr, (volatile uint32_t *)0, 1);
+ Addr += (1 << 8);
+ } while (Addr < g_board_info.target_cfg->flash_regions[0].end);
+ cortex_int_restore(state);
+
+ return (0); // O.K.
+ }else {
+ return (1); //No flash algo
+ }
+}
+
+__attribute__((section("ram_func")))
+uint32_t EraseSector(uint32_t adr)
+{
+ uint32_t NumPagesLeft;
+ //
+ // Return value 0 == O.K.
+ // Return value 1 == Error
+ // Application assumes that this function always erases 1 KB
+ // Application always calls this function with 1 KB aligned addresses
+ //
+ NumPagesLeft = 0x400 >> 8; // SAM3U has 256 byte pages, DAPLink BTL/FW assumes 1 KB sectors
+
+ cortex_int_state_t state = cortex_int_get_and_disable();
+ do {
+ _WritePage(adr, (volatile uint32_t *)0, 1);
+ adr += (1 << 8);
+ } while (--NumPagesLeft);
+ cortex_int_restore(state);
+
+ return (0); // O.K.
+}
+
+__attribute__((section("ram_func")))
+uint32_t ProgramPage(uint32_t adr, uint32_t sz, uint32_t *buf)
+{
+ uint32_t NumPagesLeft;
+ unsigned char *temp_buf = (unsigned char *)buf;
+ //
+ // Return value 0 == O.K.
+ // Return value 1 == Error
+ // Seems to program page-wise
+ // 1 page seems to be 1 KB
+ // App always calls this function with 1 KB aligned start-adresses
+ // Always called with multiple of 1 page to program
+ //
+ sz = ROUND_UP(sz, 256); // Round up to page size
+ NumPagesLeft = sz >> 8; // SAM3U has 256 byte pages, DAPLink BTL/FW assumes 1 KB pages
+
+ if (0 == NumPagesLeft) {
+ return 1;
+ }
+
+ cortex_int_state_t state = cortex_int_get_and_disable();
+ do {
+ _WritePage(adr, (volatile uint32_t *)temp_buf, 0);
+ adr += (1 << 8);
+ temp_buf += (1 << 8);
+ } while (--NumPagesLeft);
+ cortex_int_restore(state);
+
+ return (0); // Finished without Errors
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/gpio.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/gpio.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,116 @@
+/**
+ * @file gpio.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "sam3u.h"
+#include "gpio.h"
+#include "uart.h"
+#include "compiler.h"
+#include "daplink.h"
+
+// This GPIO configuration is only valid for the SAM3U2C
+COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_SAM3U2C);
+
+void gpio_init(void)
+{
+ volatile int Cnt;
+ //
+ // Initially enable clock for GPIO and initialize LED ports as output with LED == off
+ //
+ PMC->PMC_PCER0 = (1 << 10) | (1 << 11) | (1 << 12); // Enable clock for all PIOs
+
+ // DAP LED
+ PIN_DAP_LED_PORT->PIO_PER = PIN_DAP_LED;
+ PIN_DAP_LED_PORT->PIO_SODR = PIN_DAP_LED;
+ PIN_DAP_LED_PORT->PIO_OER = PIN_DAP_LED;
+
+ // MSD LED
+ PIN_MSD_LED_PORT->PIO_PER = PIN_MSD_LED;
+ PIN_MSD_LED_PORT->PIO_SODR = PIN_MSD_LED;
+ PIN_MSD_LED_PORT->PIO_OER = PIN_MSD_LED;
+
+ // CDC LED
+ PIN_CDC_LED_PORT->PIO_PER = PIN_CDC_LED;
+ PIN_CDC_LED_PORT->PIO_SODR = PIN_CDC_LED;
+ PIN_CDC_LED_PORT->PIO_OER = PIN_CDC_LED;
+
+ // Forwarded reset
+ PIN_RESET_IN_FWRD_PORT->PIO_PER = PIN_RESET_IN_FWRD; // Pin == GPIO control
+ PIN_RESET_IN_FWRD_PORT->PIO_ODR = PIN_RESET_IN_FWRD; // Disable output
+ PIN_RESET_IN_FWRD_PORT->PIO_PUER = PIN_RESET_IN_FWRD; // Enable pull-up
+ Cnt = 1000000;
+ do {} while (--Cnt); // Give pull-up some time to become active
+
+ // Enable port A interrupts in the NVIC
+ NVIC_EnableIRQ(PIOA_IRQn);
+}
+
+void gpio_set_hid_led(gpio_led_state_t state)
+{
+ if (GPIO_LED_ON == state) {
+ PIN_DAP_LED_PORT->PIO_CODR = PIN_DAP_LED; // LED == on
+ } else {
+ PIN_DAP_LED_PORT->PIO_SODR = PIN_DAP_LED; // LED == off
+ }
+}
+
+void gpio_set_cdc_led(gpio_led_state_t state)
+{
+ if (GPIO_LED_ON == state) {
+ PIN_CDC_LED_PORT->PIO_CODR = PIN_CDC_LED; // LED == on
+ } else {
+ PIN_CDC_LED_PORT->PIO_SODR = PIN_CDC_LED; // LED == off
+ }
+}
+
+void gpio_set_msc_led(gpio_led_state_t state)
+{
+ if (GPIO_LED_ON == state) {
+ PIN_MSD_LED_PORT->PIO_CODR = PIN_MSD_LED; // LED == on
+ } else {
+ PIN_MSD_LED_PORT->PIO_SODR = PIN_MSD_LED; // LED == off
+ }
+}
+
+void PIOA_IRQHandler(void)
+{
+ //
+ // ISR is called when flow control is de-asserted
+ //
+ uint32_t interrupts = PIOA->PIO_ISR;
+
+ if ((interrupts >> 9) & 1) { //CTS
+ uart_software_flow_control();
+ }
+}
+
+uint8_t gpio_get_reset_btn_no_fwrd(void)
+{
+ return 0;
+}
+
+uint8_t gpio_get_reset_btn_fwrd()
+{
+ return (PIN_RESET_IN_FWRD_PORT->PIO_PDSR & PIN_RESET_IN_FWRD) == 0;
+}
+
+void gpio_set_board_power(bool powerEnabled)
+{
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/adc.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/adc.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_ADC_INSTANCE_ +#define _SAM3U_ADC_INSTANCE_ + +/* ========== Register definition for ADC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_ADC_CR (0x400AC000U) /**< \brief (ADC) Control Register */ +#define REG_ADC_MR (0x400AC004U) /**< \brief (ADC) Mode Register */ +#define REG_ADC_CHER (0x400AC010U) /**< \brief (ADC) Channel Enable Register */ +#define REG_ADC_CHDR (0x400AC014U) /**< \brief (ADC) Channel Disable Register */ +#define REG_ADC_CHSR (0x400AC018U) /**< \brief (ADC) Channel Status Register */ +#define REG_ADC_SR (0x400AC01CU) /**< \brief (ADC) Status Register */ +#define REG_ADC_LCDR (0x400AC020U) /**< \brief (ADC) Last Converted Data Register */ +#define REG_ADC_IER (0x400AC024U) /**< \brief (ADC) Interrupt Enable Register */ +#define REG_ADC_IDR (0x400AC028U) /**< \brief (ADC) Interrupt Disable Register */ +#define REG_ADC_IMR (0x400AC02CU) /**< \brief (ADC) Interrupt Mask Register */ +#define REG_ADC_CDR (0x400AC030U) /**< \brief (ADC) Channel Data Register */ +#define REG_ADC_RPR (0x400AC100U) /**< \brief (ADC) Receive Pointer Register */ +#define REG_ADC_RCR (0x400AC104U) /**< \brief (ADC) Receive Counter Register */ +#define REG_ADC_RNPR (0x400AC110U) /**< \brief (ADC) Receive Next Pointer Register */ +#define REG_ADC_RNCR (0x400AC114U) /**< \brief (ADC) Receive Next Counter Register */ +#define REG_ADC_PTCR (0x400AC120U) /**< \brief (ADC) Transfer Control Register */ +#define REG_ADC_PTSR (0x400AC124U) /**< \brief (ADC) Transfer Status Register */ +#else +#define REG_ADC_CR (*(WoReg*)0x400AC000U) /**< \brief (ADC) Control Register */ +#define REG_ADC_MR (*(RwReg*)0x400AC004U) /**< \brief (ADC) Mode Register */ +#define REG_ADC_CHER (*(WoReg*)0x400AC010U) /**< \brief (ADC) Channel Enable Register */ +#define REG_ADC_CHDR (*(WoReg*)0x400AC014U) /**< \brief (ADC) Channel Disable Register */ +#define REG_ADC_CHSR (*(RoReg*)0x400AC018U) /**< \brief (ADC) Channel Status Register */ +#define REG_ADC_SR (*(RoReg*)0x400AC01CU) /**< \brief (ADC) Status Register */ +#define REG_ADC_LCDR (*(RoReg*)0x400AC020U) /**< \brief (ADC) Last Converted Data Register */ +#define REG_ADC_IER (*(WoReg*)0x400AC024U) /**< \brief (ADC) Interrupt Enable Register */ +#define REG_ADC_IDR (*(WoReg*)0x400AC028U) /**< \brief (ADC) Interrupt Disable Register */ +#define REG_ADC_IMR (*(RoReg*)0x400AC02CU) /**< \brief (ADC) Interrupt Mask Register */ +#define REG_ADC_CDR (*(RoReg*)0x400AC030U) /**< \brief (ADC) Channel Data Register */ +#define REG_ADC_RPR (*(RwReg*)0x400AC100U) /**< \brief (ADC) Receive Pointer Register */ +#define REG_ADC_RCR (*(RwReg*)0x400AC104U) /**< \brief (ADC) Receive Counter Register */ +#define REG_ADC_RNPR (*(RwReg*)0x400AC110U) /**< \brief (ADC) Receive Next Pointer Register */ +#define REG_ADC_RNCR (*(RwReg*)0x400AC114U) /**< \brief (ADC) Receive Next Counter Register */ +#define REG_ADC_PTCR (*(WoReg*)0x400AC120U) /**< \brief (ADC) Transfer Control Register */ +#define REG_ADC_PTSR (*(RoReg*)0x400AC124U) /**< \brief (ADC) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_ADC_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/adc12b.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/adc12b.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,76 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_ADC12B_INSTANCE_ +#define _SAM3U_ADC12B_INSTANCE_ + +/* ========== Register definition for ADC12B peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_ADC12B_CR (0x400A8000U) /**< \brief (ADC12B) Control Register */ +#define REG_ADC12B_MR (0x400A8004U) /**< \brief (ADC12B) Mode Register */ +#define REG_ADC12B_CHER (0x400A8010U) /**< \brief (ADC12B) Channel Enable Register */ +#define REG_ADC12B_CHDR (0x400A8014U) /**< \brief (ADC12B) Channel Disable Register */ +#define REG_ADC12B_CHSR (0x400A8018U) /**< \brief (ADC12B) Channel Status Register */ +#define REG_ADC12B_SR (0x400A801CU) /**< \brief (ADC12B) Status Register */ +#define REG_ADC12B_LCDR (0x400A8020U) /**< \brief (ADC12B) Last Converted Data Register */ +#define REG_ADC12B_IER (0x400A8024U) /**< \brief (ADC12B) Interrupt Enable Register */ +#define REG_ADC12B_IDR (0x400A8028U) /**< \brief (ADC12B) Interrupt Disable Register */ +#define REG_ADC12B_IMR (0x400A802CU) /**< \brief (ADC12B) Interrupt Mask Register */ +#define REG_ADC12B_CDR (0x400A8030U) /**< \brief (ADC12B) Channel Data Register */ +#define REG_ADC12B_ACR (0x400A8064U) /**< \brief (ADC12B) Analog Control Register */ +#define REG_ADC12B_EMR (0x400A8068U) /**< \brief (ADC12B) Extended Mode Register */ +#define REG_ADC12B_RPR (0x400A8100U) /**< \brief (ADC12B) Receive Pointer Register */ +#define REG_ADC12B_RCR (0x400A8104U) /**< \brief (ADC12B) Receive Counter Register */ +#define REG_ADC12B_RNPR (0x400A8110U) /**< \brief (ADC12B) Receive Next Pointer Register */ +#define REG_ADC12B_RNCR (0x400A8114U) /**< \brief (ADC12B) Receive Next Counter Register */ +#define REG_ADC12B_PTCR (0x400A8120U) /**< \brief (ADC12B) Transfer Control Register */ +#define REG_ADC12B_PTSR (0x400A8124U) /**< \brief (ADC12B) Transfer Status Register */ +#else +#define REG_ADC12B_CR (*(WoReg*)0x400A8000U) /**< \brief (ADC12B) Control Register */ +#define REG_ADC12B_MR (*(RwReg*)0x400A8004U) /**< \brief (ADC12B) Mode Register */ +#define REG_ADC12B_CHER (*(WoReg*)0x400A8010U) /**< \brief (ADC12B) Channel Enable Register */ +#define REG_ADC12B_CHDR (*(WoReg*)0x400A8014U) /**< \brief (ADC12B) Channel Disable Register */ +#define REG_ADC12B_CHSR (*(RoReg*)0x400A8018U) /**< \brief (ADC12B) Channel Status Register */ +#define REG_ADC12B_SR (*(RoReg*)0x400A801CU) /**< \brief (ADC12B) Status Register */ +#define REG_ADC12B_LCDR (*(RoReg*)0x400A8020U) /**< \brief (ADC12B) Last Converted Data Register */ +#define REG_ADC12B_IER (*(WoReg*)0x400A8024U) /**< \brief (ADC12B) Interrupt Enable Register */ +#define REG_ADC12B_IDR (*(WoReg*)0x400A8028U) /**< \brief (ADC12B) Interrupt Disable Register */ +#define REG_ADC12B_IMR (*(RoReg*)0x400A802CU) /**< \brief (ADC12B) Interrupt Mask Register */ +#define REG_ADC12B_CDR (*(RoReg*)0x400A8030U) /**< \brief (ADC12B) Channel Data Register */ +#define REG_ADC12B_ACR (*(RwReg*)0x400A8064U) /**< \brief (ADC12B) Analog Control Register */ +#define REG_ADC12B_EMR (*(RwReg*)0x400A8068U) /**< \brief (ADC12B) Extended Mode Register */ +#define REG_ADC12B_RPR (*(RwReg*)0x400A8100U) /**< \brief (ADC12B) Receive Pointer Register */ +#define REG_ADC12B_RCR (*(RwReg*)0x400A8104U) /**< \brief (ADC12B) Receive Counter Register */ +#define REG_ADC12B_RNPR (*(RwReg*)0x400A8110U) /**< \brief (ADC12B) Receive Next Pointer Register */ +#define REG_ADC12B_RNCR (*(RwReg*)0x400A8114U) /**< \brief (ADC12B) Receive Next Counter Register */ +#define REG_ADC12B_PTCR (*(WoReg*)0x400A8120U) /**< \brief (ADC12B) Transfer Control Register */ +#define REG_ADC12B_PTSR (*(RoReg*)0x400A8124U) /**< \brief (ADC12B) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_ADC12B_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/chipid.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/chipid.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,42 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_CHIPID_INSTANCE_ +#define _SAM3U_CHIPID_INSTANCE_ + +/* ========== Register definition for CHIPID peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_CHIPID_CIDR (0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ +#define REG_CHIPID_EXID (0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ +#else +#define REG_CHIPID_CIDR (*(RoReg*)0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ +#define REG_CHIPID_EXID (*(RoReg*)0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_CHIPID_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/dmac.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/dmac.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,114 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_DMAC_INSTANCE_ +#define _SAM3U_DMAC_INSTANCE_ + +/* ========== Register definition for DMAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DMAC_GCFG (0x400B0000U) /**< \brief (DMAC) DMAC Global Configuration Register */ +#define REG_DMAC_EN (0x400B0004U) /**< \brief (DMAC) DMAC Enable Register */ +#define REG_DMAC_SREQ (0x400B0008U) /**< \brief (DMAC) DMAC Software Single Request Register */ +#define REG_DMAC_CREQ (0x400B000CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */ +#define REG_DMAC_LAST (0x400B0010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */ +#define REG_DMAC_EBCIER (0x400B0018U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */ +#define REG_DMAC_EBCIDR (0x400B001CU) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */ +#define REG_DMAC_EBCIMR (0x400B0020U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */ +#define REG_DMAC_EBCISR (0x400B0024U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */ +#define REG_DMAC_CHER (0x400B0028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */ +#define REG_DMAC_CHDR (0x400B002CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */ +#define REG_DMAC_CHSR (0x400B0030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */ +#define REG_DMAC_SADDR0 (0x400B003CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */ +#define REG_DMAC_DADDR0 (0x400B0040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */ +#define REG_DMAC_DSCR0 (0x400B0044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */ +#define REG_DMAC_CTRLA0 (0x400B0048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */ +#define REG_DMAC_CTRLB0 (0x400B004CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */ +#define REG_DMAC_CFG0 (0x400B0050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */ +#define REG_DMAC_SADDR1 (0x400B0064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */ +#define REG_DMAC_DADDR1 (0x400B0068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */ +#define REG_DMAC_DSCR1 (0x400B006CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */ +#define REG_DMAC_CTRLA1 (0x400B0070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */ +#define REG_DMAC_CTRLB1 (0x400B0074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */ +#define REG_DMAC_CFG1 (0x400B0078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */ +#define REG_DMAC_SADDR2 (0x400B008CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */ +#define REG_DMAC_DADDR2 (0x400B0090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */ +#define REG_DMAC_DSCR2 (0x400B0094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */ +#define REG_DMAC_CTRLA2 (0x400B0098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */ +#define REG_DMAC_CTRLB2 (0x400B009CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */ +#define REG_DMAC_CFG2 (0x400B00A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */ +#define REG_DMAC_SADDR3 (0x400B00B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */ +#define REG_DMAC_DADDR3 (0x400B00B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */ +#define REG_DMAC_DSCR3 (0x400B00BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */ +#define REG_DMAC_CTRLA3 (0x400B00C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */ +#define REG_DMAC_CTRLB3 (0x400B00C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */ +#define REG_DMAC_CFG3 (0x400B00C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */ +#define REG_DMAC_WPMR (0x400B01E4U) /**< \brief (DMAC) DMAC Write Protect Mode Register */ +#define REG_DMAC_WPSR (0x400B01E8U) /**< \brief (DMAC) DMAC Write Protect Status Register */ +#else +#define REG_DMAC_GCFG (*(RwReg*)0x400B0000U) /**< \brief (DMAC) DMAC Global Configuration Register */ +#define REG_DMAC_EN (*(RwReg*)0x400B0004U) /**< \brief (DMAC) DMAC Enable Register */ +#define REG_DMAC_SREQ (*(RwReg*)0x400B0008U) /**< \brief (DMAC) DMAC Software Single Request Register */ +#define REG_DMAC_CREQ (*(RwReg*)0x400B000CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */ +#define REG_DMAC_LAST (*(RwReg*)0x400B0010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */ +#define REG_DMAC_EBCIER (*(WoReg*)0x400B0018U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */ +#define REG_DMAC_EBCIDR (*(WoReg*)0x400B001CU) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */ +#define REG_DMAC_EBCIMR (*(RoReg*)0x400B0020U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */ +#define REG_DMAC_EBCISR (*(RoReg*)0x400B0024U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */ +#define REG_DMAC_CHER (*(WoReg*)0x400B0028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */ +#define REG_DMAC_CHDR (*(WoReg*)0x400B002CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */ +#define REG_DMAC_CHSR (*(RoReg*)0x400B0030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */ +#define REG_DMAC_SADDR0 (*(RwReg*)0x400B003CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */ +#define REG_DMAC_DADDR0 (*(RwReg*)0x400B0040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */ +#define REG_DMAC_DSCR0 (*(RwReg*)0x400B0044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */ +#define REG_DMAC_CTRLA0 (*(RwReg*)0x400B0048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */ +#define REG_DMAC_CTRLB0 (*(RwReg*)0x400B004CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */ +#define REG_DMAC_CFG0 (*(RwReg*)0x400B0050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */ +#define REG_DMAC_SADDR1 (*(RwReg*)0x400B0064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */ +#define REG_DMAC_DADDR1 (*(RwReg*)0x400B0068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */ +#define REG_DMAC_DSCR1 (*(RwReg*)0x400B006CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */ +#define REG_DMAC_CTRLA1 (*(RwReg*)0x400B0070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */ +#define REG_DMAC_CTRLB1 (*(RwReg*)0x400B0074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */ +#define REG_DMAC_CFG1 (*(RwReg*)0x400B0078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */ +#define REG_DMAC_SADDR2 (*(RwReg*)0x400B008CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */ +#define REG_DMAC_DADDR2 (*(RwReg*)0x400B0090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */ +#define REG_DMAC_DSCR2 (*(RwReg*)0x400B0094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */ +#define REG_DMAC_CTRLA2 (*(RwReg*)0x400B0098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */ +#define REG_DMAC_CTRLB2 (*(RwReg*)0x400B009CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */ +#define REG_DMAC_CFG2 (*(RwReg*)0x400B00A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */ +#define REG_DMAC_SADDR3 (*(RwReg*)0x400B00B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */ +#define REG_DMAC_DADDR3 (*(RwReg*)0x400B00B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */ +#define REG_DMAC_DSCR3 (*(RwReg*)0x400B00BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */ +#define REG_DMAC_CTRLA3 (*(RwReg*)0x400B00C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */ +#define REG_DMAC_CTRLB3 (*(RwReg*)0x400B00C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */ +#define REG_DMAC_CFG3 (*(RwReg*)0x400B00C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */ +#define REG_DMAC_WPMR (*(RwReg*)0x400B01E4U) /**< \brief (DMAC) DMAC Write Protect Mode Register */ +#define REG_DMAC_WPSR (*(RoReg*)0x400B01E8U) /**< \brief (DMAC) DMAC Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_DMAC_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/efc0.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/efc0.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,46 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_EFC0_INSTANCE_ +#define _SAM3U_EFC0_INSTANCE_ + +/* ========== Register definition for EFC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_EFC0_FMR (0x400E0800U) /**< \brief (EFC0) EEFC Flash Mode Register */ +#define REG_EFC0_FCR (0x400E0804U) /**< \brief (EFC0) EEFC Flash Command Register */ +#define REG_EFC0_FSR (0x400E0808U) /**< \brief (EFC0) EEFC Flash Status Register */ +#define REG_EFC0_FRR (0x400E080CU) /**< \brief (EFC0) EEFC Flash Result Register */ +#else +#define REG_EFC0_FMR (*(RwReg*)0x400E0800U) /**< \brief (EFC0) EEFC Flash Mode Register */ +#define REG_EFC0_FCR (*(WoReg*)0x400E0804U) /**< \brief (EFC0) EEFC Flash Command Register */ +#define REG_EFC0_FSR (*(RoReg*)0x400E0808U) /**< \brief (EFC0) EEFC Flash Status Register */ +#define REG_EFC0_FRR (*(RoReg*)0x400E080CU) /**< \brief (EFC0) EEFC Flash Result Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_EFC0_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/efc1.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/efc1.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,46 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_EFC1_INSTANCE_ +#define _SAM3U_EFC1_INSTANCE_ + +/* ========== Register definition for EFC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_EFC1_FMR (0x400E0A00U) /**< \brief (EFC1) EEFC Flash Mode Register */ +#define REG_EFC1_FCR (0x400E0A04U) /**< \brief (EFC1) EEFC Flash Command Register */ +#define REG_EFC1_FSR (0x400E0A08U) /**< \brief (EFC1) EEFC Flash Status Register */ +#define REG_EFC1_FRR (0x400E0A0CU) /**< \brief (EFC1) EEFC Flash Result Register */ +#else +#define REG_EFC1_FMR (*(RwReg*)0x400E0A00U) /**< \brief (EFC1) EEFC Flash Mode Register */ +#define REG_EFC1_FCR (*(WoReg*)0x400E0A04U) /**< \brief (EFC1) EEFC Flash Command Register */ +#define REG_EFC1_FSR (*(RoReg*)0x400E0A08U) /**< \brief (EFC1) EEFC Flash Status Register */ +#define REG_EFC1_FRR (*(RoReg*)0x400E0A0CU) /**< \brief (EFC1) EEFC Flash Result Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_EFC1_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/gpbr.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/gpbr.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,40 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_GPBR_INSTANCE_ +#define _SAM3U_GPBR_INSTANCE_ + +/* ========== Register definition for GPBR peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_GPBR_GPBR (0x400E1290U) /**< \brief (GPBR) General Purpose Backup Register */ +#else +#define REG_GPBR_GPBR (*(RwReg*)0x400E1290U) /**< \brief (GPBR) General Purpose Backup Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_GPBR_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/hsmci.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/hsmci.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,78 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_HSMCI_INSTANCE_ +#define _SAM3U_HSMCI_INSTANCE_ + +/* ========== Register definition for HSMCI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_HSMCI_CR (0x40000000U) /**< \brief (HSMCI) Control Register */ +#define REG_HSMCI_MR (0x40000004U) /**< \brief (HSMCI) Mode Register */ +#define REG_HSMCI_DTOR (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ +#define REG_HSMCI_SDCR (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ +#define REG_HSMCI_ARGR (0x40000010U) /**< \brief (HSMCI) Argument Register */ +#define REG_HSMCI_CMDR (0x40000014U) /**< \brief (HSMCI) Command Register */ +#define REG_HSMCI_BLKR (0x40000018U) /**< \brief (HSMCI) Block Register */ +#define REG_HSMCI_CSTOR (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ +#define REG_HSMCI_RSPR (0x40000020U) /**< \brief (HSMCI) Response Register */ +#define REG_HSMCI_RDR (0x40000030U) /**< \brief (HSMCI) Receive Data Register */ +#define REG_HSMCI_TDR (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ +#define REG_HSMCI_SR (0x40000040U) /**< \brief (HSMCI) Status Register */ +#define REG_HSMCI_IER (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ +#define REG_HSMCI_IDR (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ +#define REG_HSMCI_IMR (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ +#define REG_HSMCI_DMA (0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */ +#define REG_HSMCI_CFG (0x40000054U) /**< \brief (HSMCI) Configuration Register */ +#define REG_HSMCI_WPMR (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ +#define REG_HSMCI_WPSR (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ +#define REG_HSMCI_FIFO (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */ +#else +#define REG_HSMCI_CR (*(WoReg*)0x40000000U) /**< \brief (HSMCI) Control Register */ +#define REG_HSMCI_MR (*(RwReg*)0x40000004U) /**< \brief (HSMCI) Mode Register */ +#define REG_HSMCI_DTOR (*(RwReg*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ +#define REG_HSMCI_SDCR (*(RwReg*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ +#define REG_HSMCI_ARGR (*(RwReg*)0x40000010U) /**< \brief (HSMCI) Argument Register */ +#define REG_HSMCI_CMDR (*(WoReg*)0x40000014U) /**< \brief (HSMCI) Command Register */ +#define REG_HSMCI_BLKR (*(RwReg*)0x40000018U) /**< \brief (HSMCI) Block Register */ +#define REG_HSMCI_CSTOR (*(RwReg*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ +#define REG_HSMCI_RSPR (*(RoReg*)0x40000020U) /**< \brief (HSMCI) Response Register */ +#define REG_HSMCI_RDR (*(RoReg*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */ +#define REG_HSMCI_TDR (*(WoReg*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ +#define REG_HSMCI_SR (*(RoReg*)0x40000040U) /**< \brief (HSMCI) Status Register */ +#define REG_HSMCI_IER (*(WoReg*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ +#define REG_HSMCI_IDR (*(WoReg*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ +#define REG_HSMCI_IMR (*(RoReg*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ +#define REG_HSMCI_DMA (*(RwReg*)0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */ +#define REG_HSMCI_CFG (*(RwReg*)0x40000054U) /**< \brief (HSMCI) Configuration Register */ +#define REG_HSMCI_WPMR (*(RwReg*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ +#define REG_HSMCI_WPSR (*(RoReg*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ +#define REG_HSMCI_FIFO (*(RwReg*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_HSMCI_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/matrix.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/matrix.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,68 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_MATRIX_INSTANCE_ +#define _SAM3U_MATRIX_INSTANCE_ + +/* ========== Register definition for MATRIX peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_MATRIX_MCFG (0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ +#define REG_MATRIX_SCFG (0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ +#define REG_MATRIX_PRAS0 (0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ +#define REG_MATRIX_PRAS1 (0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ +#define REG_MATRIX_PRAS2 (0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ +#define REG_MATRIX_PRAS3 (0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ +#define REG_MATRIX_PRAS4 (0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ +#define REG_MATRIX_PRAS5 (0x400E02A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */ +#define REG_MATRIX_PRAS6 (0x400E02B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */ +#define REG_MATRIX_PRAS7 (0x400E02B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */ +#define REG_MATRIX_PRAS8 (0x400E02C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */ +#define REG_MATRIX_PRAS9 (0x400E02C8U) /**< \brief (MATRIX) Priority Register A for Slave 9 */ +#define REG_MATRIX_MRCR (0x400E0300U) /**< \brief (MATRIX) Master Remap Control Register */ +#define REG_MATRIX_WPMR (0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */ +#define REG_MATRIX_WPSR (0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */ +#else +#define REG_MATRIX_MCFG (*(RwReg*)0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ +#define REG_MATRIX_SCFG (*(RwReg*)0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ +#define REG_MATRIX_PRAS0 (*(RwReg*)0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ +#define REG_MATRIX_PRAS1 (*(RwReg*)0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ +#define REG_MATRIX_PRAS2 (*(RwReg*)0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ +#define REG_MATRIX_PRAS3 (*(RwReg*)0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ +#define REG_MATRIX_PRAS4 (*(RwReg*)0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ +#define REG_MATRIX_PRAS5 (*(RwReg*)0x400E02A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */ +#define REG_MATRIX_PRAS6 (*(RwReg*)0x400E02B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */ +#define REG_MATRIX_PRAS7 (*(RwReg*)0x400E02B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */ +#define REG_MATRIX_PRAS8 (*(RwReg*)0x400E02C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */ +#define REG_MATRIX_PRAS9 (*(RwReg*)0x400E02C8U) /**< \brief (MATRIX) Priority Register A for Slave 9 */ +#define REG_MATRIX_MRCR (*(RwReg*)0x400E0300U) /**< \brief (MATRIX) Master Remap Control Register */ +#define REG_MATRIX_WPMR (*(RwReg*)0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */ +#define REG_MATRIX_WPSR (*(RoReg*)0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_MATRIX_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/pioa.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/pioa.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,124 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_PIOA_INSTANCE_ +#define _SAM3U_PIOA_INSTANCE_ + +/* ========== Register definition for PIOA peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOA_PER (0x400E0C00U) /**< \brief (PIOA) PIO Enable Register */ +#define REG_PIOA_PDR (0x400E0C04U) /**< \brief (PIOA) PIO Disable Register */ +#define REG_PIOA_PSR (0x400E0C08U) /**< \brief (PIOA) PIO Status Register */ +#define REG_PIOA_OER (0x400E0C10U) /**< \brief (PIOA) Output Enable Register */ +#define REG_PIOA_ODR (0x400E0C14U) /**< \brief (PIOA) Output Disable Register */ +#define REG_PIOA_OSR (0x400E0C18U) /**< \brief (PIOA) Output Status Register */ +#define REG_PIOA_IFER (0x400E0C20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ +#define REG_PIOA_IFDR (0x400E0C24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ +#define REG_PIOA_IFSR (0x400E0C28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ +#define REG_PIOA_SODR (0x400E0C30U) /**< \brief (PIOA) Set Output Data Register */ +#define REG_PIOA_CODR (0x400E0C34U) /**< \brief (PIOA) Clear Output Data Register */ +#define REG_PIOA_ODSR (0x400E0C38U) /**< \brief (PIOA) Output Data Status Register */ +#define REG_PIOA_PDSR (0x400E0C3CU) /**< \brief (PIOA) Pin Data Status Register */ +#define REG_PIOA_IER (0x400E0C40U) /**< \brief (PIOA) Interrupt Enable Register */ +#define REG_PIOA_IDR (0x400E0C44U) /**< \brief (PIOA) Interrupt Disable Register */ +#define REG_PIOA_IMR (0x400E0C48U) /**< \brief (PIOA) Interrupt Mask Register */ +#define REG_PIOA_ISR (0x400E0C4CU) /**< \brief (PIOA) Interrupt Status Register */ +#define REG_PIOA_MDER (0x400E0C50U) /**< \brief (PIOA) Multi-driver Enable Register */ +#define REG_PIOA_MDDR (0x400E0C54U) /**< \brief (PIOA) Multi-driver Disable Register */ +#define REG_PIOA_MDSR (0x400E0C58U) /**< \brief (PIOA) Multi-driver Status Register */ +#define REG_PIOA_PUDR (0x400E0C60U) /**< \brief (PIOA) Pull-up Disable Register */ +#define REG_PIOA_PUER (0x400E0C64U) /**< \brief (PIOA) Pull-up Enable Register */ +#define REG_PIOA_PUSR (0x400E0C68U) /**< \brief (PIOA) Pad Pull-up Status Register */ +#define REG_PIOA_ABSR (0x400E0C70U) /**< \brief (PIOA) Peripheral AB Select Register */ +#define REG_PIOA_SCIFSR (0x400E0C80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */ +#define REG_PIOA_DIFSR (0x400E0C84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */ +#define REG_PIOA_IFDGSR (0x400E0C88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOA_SCDR (0x400E0C8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ +#define REG_PIOA_OWER (0x400E0CA0U) /**< \brief (PIOA) Output Write Enable */ +#define REG_PIOA_OWDR (0x400E0CA4U) /**< \brief (PIOA) Output Write Disable */ +#define REG_PIOA_OWSR (0x400E0CA8U) /**< \brief (PIOA) Output Write Status Register */ +#define REG_PIOA_AIMER (0x400E0CB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ +#define REG_PIOA_AIMDR (0x400E0CB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ +#define REG_PIOA_AIMMR (0x400E0CB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ +#define REG_PIOA_ESR (0x400E0CC0U) /**< \brief (PIOA) Edge Select Register */ +#define REG_PIOA_LSR (0x400E0CC4U) /**< \brief (PIOA) Level Select Register */ +#define REG_PIOA_ELSR (0x400E0CC8U) /**< \brief (PIOA) Edge/Level Status Register */ +#define REG_PIOA_FELLSR (0x400E0CD0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ +#define REG_PIOA_REHLSR (0x400E0CD4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ +#define REG_PIOA_FRLHSR (0x400E0CD8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ +#define REG_PIOA_LOCKSR (0x400E0CE0U) /**< \brief (PIOA) Lock Status */ +#define REG_PIOA_WPMR (0x400E0CE4U) /**< \brief (PIOA) Write Protect Mode Register */ +#define REG_PIOA_WPSR (0x400E0CE8U) /**< \brief (PIOA) Write Protect Status Register */ +#else +#define REG_PIOA_PER (*(WoReg*)0x400E0C00U) /**< \brief (PIOA) PIO Enable Register */ +#define REG_PIOA_PDR (*(WoReg*)0x400E0C04U) /**< \brief (PIOA) PIO Disable Register */ +#define REG_PIOA_PSR (*(RoReg*)0x400E0C08U) /**< \brief (PIOA) PIO Status Register */ +#define REG_PIOA_OER (*(WoReg*)0x400E0C10U) /**< \brief (PIOA) Output Enable Register */ +#define REG_PIOA_ODR (*(WoReg*)0x400E0C14U) /**< \brief (PIOA) Output Disable Register */ +#define REG_PIOA_OSR (*(RoReg*)0x400E0C18U) /**< \brief (PIOA) Output Status Register */ +#define REG_PIOA_IFER (*(WoReg*)0x400E0C20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ +#define REG_PIOA_IFDR (*(WoReg*)0x400E0C24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ +#define REG_PIOA_IFSR (*(RoReg*)0x400E0C28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ +#define REG_PIOA_SODR (*(WoReg*)0x400E0C30U) /**< \brief (PIOA) Set Output Data Register */ +#define REG_PIOA_CODR (*(WoReg*)0x400E0C34U) /**< \brief (PIOA) Clear Output Data Register */ +#define REG_PIOA_ODSR (*(RwReg*)0x400E0C38U) /**< \brief (PIOA) Output Data Status Register */ +#define REG_PIOA_PDSR (*(RoReg*)0x400E0C3CU) /**< \brief (PIOA) Pin Data Status Register */ +#define REG_PIOA_IER (*(WoReg*)0x400E0C40U) /**< \brief (PIOA) Interrupt Enable Register */ +#define REG_PIOA_IDR (*(WoReg*)0x400E0C44U) /**< \brief (PIOA) Interrupt Disable Register */ +#define REG_PIOA_IMR (*(RoReg*)0x400E0C48U) /**< \brief (PIOA) Interrupt Mask Register */ +#define REG_PIOA_ISR (*(RoReg*)0x400E0C4CU) /**< \brief (PIOA) Interrupt Status Register */ +#define REG_PIOA_MDER (*(WoReg*)0x400E0C50U) /**< \brief (PIOA) Multi-driver Enable Register */ +#define REG_PIOA_MDDR (*(WoReg*)0x400E0C54U) /**< \brief (PIOA) Multi-driver Disable Register */ +#define REG_PIOA_MDSR (*(RoReg*)0x400E0C58U) /**< \brief (PIOA) Multi-driver Status Register */ +#define REG_PIOA_PUDR (*(WoReg*)0x400E0C60U) /**< \brief (PIOA) Pull-up Disable Register */ +#define REG_PIOA_PUER (*(WoReg*)0x400E0C64U) /**< \brief (PIOA) Pull-up Enable Register */ +#define REG_PIOA_PUSR (*(RoReg*)0x400E0C68U) /**< \brief (PIOA) Pad Pull-up Status Register */ +#define REG_PIOA_ABSR (*(RwReg*)0x400E0C70U) /**< \brief (PIOA) Peripheral AB Select Register */ +#define REG_PIOA_SCIFSR (*(WoReg*)0x400E0C80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */ +#define REG_PIOA_DIFSR (*(WoReg*)0x400E0C84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */ +#define REG_PIOA_IFDGSR (*(RoReg*)0x400E0C88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOA_SCDR (*(RwReg*)0x400E0C8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ +#define REG_PIOA_OWER (*(WoReg*)0x400E0CA0U) /**< \brief (PIOA) Output Write Enable */ +#define REG_PIOA_OWDR (*(WoReg*)0x400E0CA4U) /**< \brief (PIOA) Output Write Disable */ +#define REG_PIOA_OWSR (*(RoReg*)0x400E0CA8U) /**< \brief (PIOA) Output Write Status Register */ +#define REG_PIOA_AIMER (*(WoReg*)0x400E0CB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ +#define REG_PIOA_AIMDR (*(WoReg*)0x400E0CB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ +#define REG_PIOA_AIMMR (*(RoReg*)0x400E0CB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ +#define REG_PIOA_ESR (*(WoReg*)0x400E0CC0U) /**< \brief (PIOA) Edge Select Register */ +#define REG_PIOA_LSR (*(WoReg*)0x400E0CC4U) /**< \brief (PIOA) Level Select Register */ +#define REG_PIOA_ELSR (*(RoReg*)0x400E0CC8U) /**< \brief (PIOA) Edge/Level Status Register */ +#define REG_PIOA_FELLSR (*(WoReg*)0x400E0CD0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ +#define REG_PIOA_REHLSR (*(WoReg*)0x400E0CD4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ +#define REG_PIOA_FRLHSR (*(RoReg*)0x400E0CD8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ +#define REG_PIOA_LOCKSR (*(RoReg*)0x400E0CE0U) /**< \brief (PIOA) Lock Status */ +#define REG_PIOA_WPMR (*(RwReg*)0x400E0CE4U) /**< \brief (PIOA) Write Protect Mode Register */ +#define REG_PIOA_WPSR (*(RoReg*)0x400E0CE8U) /**< \brief (PIOA) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_PIOA_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/piob.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/piob.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,124 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_PIOB_INSTANCE_ +#define _SAM3U_PIOB_INSTANCE_ + +/* ========== Register definition for PIOB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOB_PER (0x400E0E00U) /**< \brief (PIOB) PIO Enable Register */ +#define REG_PIOB_PDR (0x400E0E04U) /**< \brief (PIOB) PIO Disable Register */ +#define REG_PIOB_PSR (0x400E0E08U) /**< \brief (PIOB) PIO Status Register */ +#define REG_PIOB_OER (0x400E0E10U) /**< \brief (PIOB) Output Enable Register */ +#define REG_PIOB_ODR (0x400E0E14U) /**< \brief (PIOB) Output Disable Register */ +#define REG_PIOB_OSR (0x400E0E18U) /**< \brief (PIOB) Output Status Register */ +#define REG_PIOB_IFER (0x400E0E20U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ +#define REG_PIOB_IFDR (0x400E0E24U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ +#define REG_PIOB_IFSR (0x400E0E28U) /**< \brief (PIOB) Glitch Input Filter Status Register */ +#define REG_PIOB_SODR (0x400E0E30U) /**< \brief (PIOB) Set Output Data Register */ +#define REG_PIOB_CODR (0x400E0E34U) /**< \brief (PIOB) Clear Output Data Register */ +#define REG_PIOB_ODSR (0x400E0E38U) /**< \brief (PIOB) Output Data Status Register */ +#define REG_PIOB_PDSR (0x400E0E3CU) /**< \brief (PIOB) Pin Data Status Register */ +#define REG_PIOB_IER (0x400E0E40U) /**< \brief (PIOB) Interrupt Enable Register */ +#define REG_PIOB_IDR (0x400E0E44U) /**< \brief (PIOB) Interrupt Disable Register */ +#define REG_PIOB_IMR (0x400E0E48U) /**< \brief (PIOB) Interrupt Mask Register */ +#define REG_PIOB_ISR (0x400E0E4CU) /**< \brief (PIOB) Interrupt Status Register */ +#define REG_PIOB_MDER (0x400E0E50U) /**< \brief (PIOB) Multi-driver Enable Register */ +#define REG_PIOB_MDDR (0x400E0E54U) /**< \brief (PIOB) Multi-driver Disable Register */ +#define REG_PIOB_MDSR (0x400E0E58U) /**< \brief (PIOB) Multi-driver Status Register */ +#define REG_PIOB_PUDR (0x400E0E60U) /**< \brief (PIOB) Pull-up Disable Register */ +#define REG_PIOB_PUER (0x400E0E64U) /**< \brief (PIOB) Pull-up Enable Register */ +#define REG_PIOB_PUSR (0x400E0E68U) /**< \brief (PIOB) Pad Pull-up Status Register */ +#define REG_PIOB_ABSR (0x400E0E70U) /**< \brief (PIOB) Peripheral AB Select Register */ +#define REG_PIOB_SCIFSR (0x400E0E80U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */ +#define REG_PIOB_DIFSR (0x400E0E84U) /**< \brief (PIOB) Debouncing Input Filter Select Register */ +#define REG_PIOB_IFDGSR (0x400E0E88U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOB_SCDR (0x400E0E8CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ +#define REG_PIOB_OWER (0x400E0EA0U) /**< \brief (PIOB) Output Write Enable */ +#define REG_PIOB_OWDR (0x400E0EA4U) /**< \brief (PIOB) Output Write Disable */ +#define REG_PIOB_OWSR (0x400E0EA8U) /**< \brief (PIOB) Output Write Status Register */ +#define REG_PIOB_AIMER (0x400E0EB0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ +#define REG_PIOB_AIMDR (0x400E0EB4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ +#define REG_PIOB_AIMMR (0x400E0EB8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ +#define REG_PIOB_ESR (0x400E0EC0U) /**< \brief (PIOB) Edge Select Register */ +#define REG_PIOB_LSR (0x400E0EC4U) /**< \brief (PIOB) Level Select Register */ +#define REG_PIOB_ELSR (0x400E0EC8U) /**< \brief (PIOB) Edge/Level Status Register */ +#define REG_PIOB_FELLSR (0x400E0ED0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ +#define REG_PIOB_REHLSR (0x400E0ED4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ +#define REG_PIOB_FRLHSR (0x400E0ED8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ +#define REG_PIOB_LOCKSR (0x400E0EE0U) /**< \brief (PIOB) Lock Status */ +#define REG_PIOB_WPMR (0x400E0EE4U) /**< \brief (PIOB) Write Protect Mode Register */ +#define REG_PIOB_WPSR (0x400E0EE8U) /**< \brief (PIOB) Write Protect Status Register */ +#else +#define REG_PIOB_PER (*(WoReg*)0x400E0E00U) /**< \brief (PIOB) PIO Enable Register */ +#define REG_PIOB_PDR (*(WoReg*)0x400E0E04U) /**< \brief (PIOB) PIO Disable Register */ +#define REG_PIOB_PSR (*(RoReg*)0x400E0E08U) /**< \brief (PIOB) PIO Status Register */ +#define REG_PIOB_OER (*(WoReg*)0x400E0E10U) /**< \brief (PIOB) Output Enable Register */ +#define REG_PIOB_ODR (*(WoReg*)0x400E0E14U) /**< \brief (PIOB) Output Disable Register */ +#define REG_PIOB_OSR (*(RoReg*)0x400E0E18U) /**< \brief (PIOB) Output Status Register */ +#define REG_PIOB_IFER (*(WoReg*)0x400E0E20U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ +#define REG_PIOB_IFDR (*(WoReg*)0x400E0E24U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ +#define REG_PIOB_IFSR (*(RoReg*)0x400E0E28U) /**< \brief (PIOB) Glitch Input Filter Status Register */ +#define REG_PIOB_SODR (*(WoReg*)0x400E0E30U) /**< \brief (PIOB) Set Output Data Register */ +#define REG_PIOB_CODR (*(WoReg*)0x400E0E34U) /**< \brief (PIOB) Clear Output Data Register */ +#define REG_PIOB_ODSR (*(RwReg*)0x400E0E38U) /**< \brief (PIOB) Output Data Status Register */ +#define REG_PIOB_PDSR (*(RoReg*)0x400E0E3CU) /**< \brief (PIOB) Pin Data Status Register */ +#define REG_PIOB_IER (*(WoReg*)0x400E0E40U) /**< \brief (PIOB) Interrupt Enable Register */ +#define REG_PIOB_IDR (*(WoReg*)0x400E0E44U) /**< \brief (PIOB) Interrupt Disable Register */ +#define REG_PIOB_IMR (*(RoReg*)0x400E0E48U) /**< \brief (PIOB) Interrupt Mask Register */ +#define REG_PIOB_ISR (*(RoReg*)0x400E0E4CU) /**< \brief (PIOB) Interrupt Status Register */ +#define REG_PIOB_MDER (*(WoReg*)0x400E0E50U) /**< \brief (PIOB) Multi-driver Enable Register */ +#define REG_PIOB_MDDR (*(WoReg*)0x400E0E54U) /**< \brief (PIOB) Multi-driver Disable Register */ +#define REG_PIOB_MDSR (*(RoReg*)0x400E0E58U) /**< \brief (PIOB) Multi-driver Status Register */ +#define REG_PIOB_PUDR (*(WoReg*)0x400E0E60U) /**< \brief (PIOB) Pull-up Disable Register */ +#define REG_PIOB_PUER (*(WoReg*)0x400E0E64U) /**< \brief (PIOB) Pull-up Enable Register */ +#define REG_PIOB_PUSR (*(RoReg*)0x400E0E68U) /**< \brief (PIOB) Pad Pull-up Status Register */ +#define REG_PIOB_ABSR (*(RwReg*)0x400E0E70U) /**< \brief (PIOB) Peripheral AB Select Register */ +#define REG_PIOB_SCIFSR (*(WoReg*)0x400E0E80U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */ +#define REG_PIOB_DIFSR (*(WoReg*)0x400E0E84U) /**< \brief (PIOB) Debouncing Input Filter Select Register */ +#define REG_PIOB_IFDGSR (*(RoReg*)0x400E0E88U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOB_SCDR (*(RwReg*)0x400E0E8CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ +#define REG_PIOB_OWER (*(WoReg*)0x400E0EA0U) /**< \brief (PIOB) Output Write Enable */ +#define REG_PIOB_OWDR (*(WoReg*)0x400E0EA4U) /**< \brief (PIOB) Output Write Disable */ +#define REG_PIOB_OWSR (*(RoReg*)0x400E0EA8U) /**< \brief (PIOB) Output Write Status Register */ +#define REG_PIOB_AIMER (*(WoReg*)0x400E0EB0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ +#define REG_PIOB_AIMDR (*(WoReg*)0x400E0EB4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ +#define REG_PIOB_AIMMR (*(RoReg*)0x400E0EB8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ +#define REG_PIOB_ESR (*(WoReg*)0x400E0EC0U) /**< \brief (PIOB) Edge Select Register */ +#define REG_PIOB_LSR (*(WoReg*)0x400E0EC4U) /**< \brief (PIOB) Level Select Register */ +#define REG_PIOB_ELSR (*(RoReg*)0x400E0EC8U) /**< \brief (PIOB) Edge/Level Status Register */ +#define REG_PIOB_FELLSR (*(WoReg*)0x400E0ED0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ +#define REG_PIOB_REHLSR (*(WoReg*)0x400E0ED4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ +#define REG_PIOB_FRLHSR (*(RoReg*)0x400E0ED8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ +#define REG_PIOB_LOCKSR (*(RoReg*)0x400E0EE0U) /**< \brief (PIOB) Lock Status */ +#define REG_PIOB_WPMR (*(RwReg*)0x400E0EE4U) /**< \brief (PIOB) Write Protect Mode Register */ +#define REG_PIOB_WPSR (*(RoReg*)0x400E0EE8U) /**< \brief (PIOB) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_PIOB_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/pioc.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/pioc.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,124 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_PIOC_INSTANCE_ +#define _SAM3U_PIOC_INSTANCE_ + +/* ========== Register definition for PIOC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOC_PER (0x400E1000U) /**< \brief (PIOC) PIO Enable Register */ +#define REG_PIOC_PDR (0x400E1004U) /**< \brief (PIOC) PIO Disable Register */ +#define REG_PIOC_PSR (0x400E1008U) /**< \brief (PIOC) PIO Status Register */ +#define REG_PIOC_OER (0x400E1010U) /**< \brief (PIOC) Output Enable Register */ +#define REG_PIOC_ODR (0x400E1014U) /**< \brief (PIOC) Output Disable Register */ +#define REG_PIOC_OSR (0x400E1018U) /**< \brief (PIOC) Output Status Register */ +#define REG_PIOC_IFER (0x400E1020U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ +#define REG_PIOC_IFDR (0x400E1024U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ +#define REG_PIOC_IFSR (0x400E1028U) /**< \brief (PIOC) Glitch Input Filter Status Register */ +#define REG_PIOC_SODR (0x400E1030U) /**< \brief (PIOC) Set Output Data Register */ +#define REG_PIOC_CODR (0x400E1034U) /**< \brief (PIOC) Clear Output Data Register */ +#define REG_PIOC_ODSR (0x400E1038U) /**< \brief (PIOC) Output Data Status Register */ +#define REG_PIOC_PDSR (0x400E103CU) /**< \brief (PIOC) Pin Data Status Register */ +#define REG_PIOC_IER (0x400E1040U) /**< \brief (PIOC) Interrupt Enable Register */ +#define REG_PIOC_IDR (0x400E1044U) /**< \brief (PIOC) Interrupt Disable Register */ +#define REG_PIOC_IMR (0x400E1048U) /**< \brief (PIOC) Interrupt Mask Register */ +#define REG_PIOC_ISR (0x400E104CU) /**< \brief (PIOC) Interrupt Status Register */ +#define REG_PIOC_MDER (0x400E1050U) /**< \brief (PIOC) Multi-driver Enable Register */ +#define REG_PIOC_MDDR (0x400E1054U) /**< \brief (PIOC) Multi-driver Disable Register */ +#define REG_PIOC_MDSR (0x400E1058U) /**< \brief (PIOC) Multi-driver Status Register */ +#define REG_PIOC_PUDR (0x400E1060U) /**< \brief (PIOC) Pull-up Disable Register */ +#define REG_PIOC_PUER (0x400E1064U) /**< \brief (PIOC) Pull-up Enable Register */ +#define REG_PIOC_PUSR (0x400E1068U) /**< \brief (PIOC) Pad Pull-up Status Register */ +#define REG_PIOC_ABSR (0x400E1070U) /**< \brief (PIOC) Peripheral AB Select Register */ +#define REG_PIOC_SCIFSR (0x400E1080U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */ +#define REG_PIOC_DIFSR (0x400E1084U) /**< \brief (PIOC) Debouncing Input Filter Select Register */ +#define REG_PIOC_IFDGSR (0x400E1088U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOC_SCDR (0x400E108CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ +#define REG_PIOC_OWER (0x400E10A0U) /**< \brief (PIOC) Output Write Enable */ +#define REG_PIOC_OWDR (0x400E10A4U) /**< \brief (PIOC) Output Write Disable */ +#define REG_PIOC_OWSR (0x400E10A8U) /**< \brief (PIOC) Output Write Status Register */ +#define REG_PIOC_AIMER (0x400E10B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ +#define REG_PIOC_AIMDR (0x400E10B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ +#define REG_PIOC_AIMMR (0x400E10B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ +#define REG_PIOC_ESR (0x400E10C0U) /**< \brief (PIOC) Edge Select Register */ +#define REG_PIOC_LSR (0x400E10C4U) /**< \brief (PIOC) Level Select Register */ +#define REG_PIOC_ELSR (0x400E10C8U) /**< \brief (PIOC) Edge/Level Status Register */ +#define REG_PIOC_FELLSR (0x400E10D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ +#define REG_PIOC_REHLSR (0x400E10D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ +#define REG_PIOC_FRLHSR (0x400E10D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ +#define REG_PIOC_LOCKSR (0x400E10E0U) /**< \brief (PIOC) Lock Status */ +#define REG_PIOC_WPMR (0x400E10E4U) /**< \brief (PIOC) Write Protect Mode Register */ +#define REG_PIOC_WPSR (0x400E10E8U) /**< \brief (PIOC) Write Protect Status Register */ +#else +#define REG_PIOC_PER (*(WoReg*)0x400E1000U) /**< \brief (PIOC) PIO Enable Register */ +#define REG_PIOC_PDR (*(WoReg*)0x400E1004U) /**< \brief (PIOC) PIO Disable Register */ +#define REG_PIOC_PSR (*(RoReg*)0x400E1008U) /**< \brief (PIOC) PIO Status Register */ +#define REG_PIOC_OER (*(WoReg*)0x400E1010U) /**< \brief (PIOC) Output Enable Register */ +#define REG_PIOC_ODR (*(WoReg*)0x400E1014U) /**< \brief (PIOC) Output Disable Register */ +#define REG_PIOC_OSR (*(RoReg*)0x400E1018U) /**< \brief (PIOC) Output Status Register */ +#define REG_PIOC_IFER (*(WoReg*)0x400E1020U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ +#define REG_PIOC_IFDR (*(WoReg*)0x400E1024U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ +#define REG_PIOC_IFSR (*(RoReg*)0x400E1028U) /**< \brief (PIOC) Glitch Input Filter Status Register */ +#define REG_PIOC_SODR (*(WoReg*)0x400E1030U) /**< \brief (PIOC) Set Output Data Register */ +#define REG_PIOC_CODR (*(WoReg*)0x400E1034U) /**< \brief (PIOC) Clear Output Data Register */ +#define REG_PIOC_ODSR (*(RwReg*)0x400E1038U) /**< \brief (PIOC) Output Data Status Register */ +#define REG_PIOC_PDSR (*(RoReg*)0x400E103CU) /**< \brief (PIOC) Pin Data Status Register */ +#define REG_PIOC_IER (*(WoReg*)0x400E1040U) /**< \brief (PIOC) Interrupt Enable Register */ +#define REG_PIOC_IDR (*(WoReg*)0x400E1044U) /**< \brief (PIOC) Interrupt Disable Register */ +#define REG_PIOC_IMR (*(RoReg*)0x400E1048U) /**< \brief (PIOC) Interrupt Mask Register */ +#define REG_PIOC_ISR (*(RoReg*)0x400E104CU) /**< \brief (PIOC) Interrupt Status Register */ +#define REG_PIOC_MDER (*(WoReg*)0x400E1050U) /**< \brief (PIOC) Multi-driver Enable Register */ +#define REG_PIOC_MDDR (*(WoReg*)0x400E1054U) /**< \brief (PIOC) Multi-driver Disable Register */ +#define REG_PIOC_MDSR (*(RoReg*)0x400E1058U) /**< \brief (PIOC) Multi-driver Status Register */ +#define REG_PIOC_PUDR (*(WoReg*)0x400E1060U) /**< \brief (PIOC) Pull-up Disable Register */ +#define REG_PIOC_PUER (*(WoReg*)0x400E1064U) /**< \brief (PIOC) Pull-up Enable Register */ +#define REG_PIOC_PUSR (*(RoReg*)0x400E1068U) /**< \brief (PIOC) Pad Pull-up Status Register */ +#define REG_PIOC_ABSR (*(RwReg*)0x400E1070U) /**< \brief (PIOC) Peripheral AB Select Register */ +#define REG_PIOC_SCIFSR (*(WoReg*)0x400E1080U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */ +#define REG_PIOC_DIFSR (*(WoReg*)0x400E1084U) /**< \brief (PIOC) Debouncing Input Filter Select Register */ +#define REG_PIOC_IFDGSR (*(RoReg*)0x400E1088U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOC_SCDR (*(RwReg*)0x400E108CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ +#define REG_PIOC_OWER (*(WoReg*)0x400E10A0U) /**< \brief (PIOC) Output Write Enable */ +#define REG_PIOC_OWDR (*(WoReg*)0x400E10A4U) /**< \brief (PIOC) Output Write Disable */ +#define REG_PIOC_OWSR (*(RoReg*)0x400E10A8U) /**< \brief (PIOC) Output Write Status Register */ +#define REG_PIOC_AIMER (*(WoReg*)0x400E10B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ +#define REG_PIOC_AIMDR (*(WoReg*)0x400E10B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ +#define REG_PIOC_AIMMR (*(RoReg*)0x400E10B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ +#define REG_PIOC_ESR (*(WoReg*)0x400E10C0U) /**< \brief (PIOC) Edge Select Register */ +#define REG_PIOC_LSR (*(WoReg*)0x400E10C4U) /**< \brief (PIOC) Level Select Register */ +#define REG_PIOC_ELSR (*(RoReg*)0x400E10C8U) /**< \brief (PIOC) Edge/Level Status Register */ +#define REG_PIOC_FELLSR (*(WoReg*)0x400E10D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ +#define REG_PIOC_REHLSR (*(WoReg*)0x400E10D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ +#define REG_PIOC_FRLHSR (*(RoReg*)0x400E10D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ +#define REG_PIOC_LOCKSR (*(RoReg*)0x400E10E0U) /**< \brief (PIOC) Lock Status */ +#define REG_PIOC_WPMR (*(RwReg*)0x400E10E4U) /**< \brief (PIOC) Write Protect Mode Register */ +#define REG_PIOC_WPSR (*(RoReg*)0x400E10E8U) /**< \brief (PIOC) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_PIOC_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/pmc.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/pmc.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_PMC_INSTANCE_ +#define _SAM3U_PMC_INSTANCE_ + +/* ========== Register definition for PMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PMC_SCER (0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ +#define REG_PMC_SCDR (0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ +#define REG_PMC_SCSR (0x400E0408U) /**< \brief (PMC) System Clock Status Register */ +#define REG_PMC_PCER0 (0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ +#define REG_PMC_PCDR0 (0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ +#define REG_PMC_PCSR0 (0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ +#define REG_CKGR_UCKR (0x400E041CU) /**< \brief (PMC) UTMI Clock Register */ +#define REG_CKGR_MOR (0x400E0420U) /**< \brief (PMC) Main Oscillator Register */ +#define REG_CKGR_MCFR (0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */ +#define REG_CKGR_PLLAR (0x400E0428U) /**< \brief (PMC) PLLA Register */ +#define REG_PMC_MCKR (0x400E0430U) /**< \brief (PMC) Master Clock Register */ +#define REG_PMC_PCK (0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */ +#define REG_PMC_IER (0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */ +#define REG_PMC_IDR (0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */ +#define REG_PMC_SR (0x400E0468U) /**< \brief (PMC) Status Register */ +#define REG_PMC_IMR (0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */ +#define REG_PMC_FSMR (0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */ +#define REG_PMC_FSPR (0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */ +#define REG_PMC_FOCR (0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ +#define REG_PMC_WPMR (0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */ +#define REG_PMC_WPSR (0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */ +#else +#define REG_PMC_SCER (*(WoReg*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ +#define REG_PMC_SCDR (*(WoReg*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ +#define REG_PMC_SCSR (*(RoReg*)0x400E0408U) /**< \brief (PMC) System Clock Status Register */ +#define REG_PMC_PCER0 (*(WoReg*)0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ +#define REG_PMC_PCDR0 (*(WoReg*)0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ +#define REG_PMC_PCSR0 (*(RoReg*)0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ +#define REG_CKGR_UCKR (*(RwReg*)0x400E041CU) /**< \brief (PMC) UTMI Clock Register */ +#define REG_CKGR_MOR (*(RwReg*)0x400E0420U) /**< \brief (PMC) Main Oscillator Register */ +#define REG_CKGR_MCFR (*(RoReg*)0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */ +#define REG_CKGR_PLLAR (*(RwReg*)0x400E0428U) /**< \brief (PMC) PLLA Register */ +#define REG_PMC_MCKR (*(RwReg*)0x400E0430U) /**< \brief (PMC) Master Clock Register */ +#define REG_PMC_PCK (*(RwReg*)0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */ +#define REG_PMC_IER (*(WoReg*)0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */ +#define REG_PMC_IDR (*(WoReg*)0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */ +#define REG_PMC_SR (*(RoReg*)0x400E0468U) /**< \brief (PMC) Status Register */ +#define REG_PMC_IMR (*(RoReg*)0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */ +#define REG_PMC_FSMR (*(RwReg*)0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */ +#define REG_PMC_FSPR (*(RwReg*)0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */ +#define REG_PMC_FOCR (*(WoReg*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ +#define REG_PMC_WPMR (*(RwReg*)0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */ +#define REG_PMC_WPSR (*(RoReg*)0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_PMC_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/pwm.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/pwm.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,240 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_PWM_INSTANCE_ +#define _SAM3U_PWM_INSTANCE_ + +/* ========== Register definition for PWM peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PWM_CLK (0x4008C000U) /**< \brief (PWM) PWM Clock Register */ +#define REG_PWM_ENA (0x4008C004U) /**< \brief (PWM) PWM Enable Register */ +#define REG_PWM_DIS (0x4008C008U) /**< \brief (PWM) PWM Disable Register */ +#define REG_PWM_SR (0x4008C00CU) /**< \brief (PWM) PWM Status Register */ +#define REG_PWM_IER1 (0x4008C010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ +#define REG_PWM_IDR1 (0x4008C014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ +#define REG_PWM_IMR1 (0x4008C018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ +#define REG_PWM_ISR1 (0x4008C01CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ +#define REG_PWM_SCM (0x4008C020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ +#define REG_PWM_SCUC (0x4008C028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ +#define REG_PWM_SCUP (0x4008C02CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ +#define REG_PWM_SCUPUPD (0x4008C030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ +#define REG_PWM_IER2 (0x4008C034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ +#define REG_PWM_IDR2 (0x4008C038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ +#define REG_PWM_IMR2 (0x4008C03CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ +#define REG_PWM_ISR2 (0x4008C040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ +#define REG_PWM_OOV (0x4008C044U) /**< \brief (PWM) PWM Output Override Value Register */ +#define REG_PWM_OS (0x4008C048U) /**< \brief (PWM) PWM Output Selection Register */ +#define REG_PWM_OSS (0x4008C04CU) /**< \brief (PWM) PWM Output Selection Set Register */ +#define REG_PWM_OSC (0x4008C050U) /**< \brief (PWM) PWM Output Selection Clear Register */ +#define REG_PWM_OSSUPD (0x4008C054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ +#define REG_PWM_OSCUPD (0x4008C058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ +#define REG_PWM_FMR (0x4008C05CU) /**< \brief (PWM) PWM Fault Mode Register */ +#define REG_PWM_FSR (0x4008C060U) /**< \brief (PWM) PWM Fault Status Register */ +#define REG_PWM_FCR (0x4008C064U) /**< \brief (PWM) PWM Fault Clear Register */ +#define REG_PWM_FPV (0x4008C068U) /**< \brief (PWM) PWM Fault Protection Value Register */ +#define REG_PWM_FPE (0x4008C06CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ +#define REG_PWM_ELMR (0x4008C07CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ +#define REG_PWM_SMMR (0x4008C0B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */ +#define REG_PWM_WPCR (0x4008C0E4U) /**< \brief (PWM) PWM Write Protect Control Register */ +#define REG_PWM_WPSR (0x4008C0E8U) /**< \brief (PWM) PWM Write Protect Status Register */ +#define REG_PWM_TPR (0x4008C108U) /**< \brief (PWM) Transmit Pointer Register */ +#define REG_PWM_TCR (0x4008C10CU) /**< \brief (PWM) Transmit Counter Register */ +#define REG_PWM_TNPR (0x4008C118U) /**< \brief (PWM) Transmit Next Pointer Register */ +#define REG_PWM_TNCR (0x4008C11CU) /**< \brief (PWM) Transmit Next Counter Register */ +#define REG_PWM_PTCR (0x4008C120U) /**< \brief (PWM) Transfer Control Register */ +#define REG_PWM_PTSR (0x4008C124U) /**< \brief (PWM) Transfer Status Register */ +#define REG_PWM_CMPV0 (0x4008C130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ +#define REG_PWM_CMPVUPD0 (0x4008C134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ +#define REG_PWM_CMPM0 (0x4008C138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ +#define REG_PWM_CMPMUPD0 (0x4008C13CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ +#define REG_PWM_CMPV1 (0x4008C140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ +#define REG_PWM_CMPVUPD1 (0x4008C144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ +#define REG_PWM_CMPM1 (0x4008C148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ +#define REG_PWM_CMPMUPD1 (0x4008C14CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ +#define REG_PWM_CMPV2 (0x4008C150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ +#define REG_PWM_CMPVUPD2 (0x4008C154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ +#define REG_PWM_CMPM2 (0x4008C158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ +#define REG_PWM_CMPMUPD2 (0x4008C15CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ +#define REG_PWM_CMPV3 (0x4008C160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ +#define REG_PWM_CMPVUPD3 (0x4008C164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ +#define REG_PWM_CMPM3 (0x4008C168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ +#define REG_PWM_CMPMUPD3 (0x4008C16CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ +#define REG_PWM_CMPV4 (0x4008C170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ +#define REG_PWM_CMPVUPD4 (0x4008C174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ +#define REG_PWM_CMPM4 (0x4008C178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ +#define REG_PWM_CMPMUPD4 (0x4008C17CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ +#define REG_PWM_CMPV5 (0x4008C180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ +#define REG_PWM_CMPVUPD5 (0x4008C184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ +#define REG_PWM_CMPM5 (0x4008C188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ +#define REG_PWM_CMPMUPD5 (0x4008C18CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ +#define REG_PWM_CMPV6 (0x4008C190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ +#define REG_PWM_CMPVUPD6 (0x4008C194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ +#define REG_PWM_CMPM6 (0x4008C198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ +#define REG_PWM_CMPMUPD6 (0x4008C19CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ +#define REG_PWM_CMPV7 (0x4008C1A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ +#define REG_PWM_CMPVUPD7 (0x4008C1A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ +#define REG_PWM_CMPM7 (0x4008C1A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ +#define REG_PWM_CMPMUPD7 (0x4008C1ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ +#define REG_PWM_CMR0 (0x4008C200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ +#define REG_PWM_CDTY0 (0x4008C204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ +#define REG_PWM_CDTYUPD0 (0x4008C208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ +#define REG_PWM_CPRD0 (0x4008C20CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ +#define REG_PWM_CPRDUPD0 (0x4008C210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ +#define REG_PWM_CCNT0 (0x4008C214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ +#define REG_PWM_DT0 (0x4008C218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ +#define REG_PWM_DTUPD0 (0x4008C21CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ +#define REG_PWM_CMR1 (0x4008C220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ +#define REG_PWM_CDTY1 (0x4008C224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ +#define REG_PWM_CDTYUPD1 (0x4008C228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ +#define REG_PWM_CPRD1 (0x4008C22CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ +#define REG_PWM_CPRDUPD1 (0x4008C230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ +#define REG_PWM_CCNT1 (0x4008C234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ +#define REG_PWM_DT1 (0x4008C238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ +#define REG_PWM_DTUPD1 (0x4008C23CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ +#define REG_PWM_CMR2 (0x4008C240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ +#define REG_PWM_CDTY2 (0x4008C244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ +#define REG_PWM_CDTYUPD2 (0x4008C248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ +#define REG_PWM_CPRD2 (0x4008C24CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ +#define REG_PWM_CPRDUPD2 (0x4008C250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ +#define REG_PWM_CCNT2 (0x4008C254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ +#define REG_PWM_DT2 (0x4008C258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ +#define REG_PWM_DTUPD2 (0x4008C25CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ +#define REG_PWM_CMR3 (0x4008C260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ +#define REG_PWM_CDTY3 (0x4008C264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ +#define REG_PWM_CDTYUPD3 (0x4008C268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ +#define REG_PWM_CPRD3 (0x4008C26CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ +#define REG_PWM_CPRDUPD3 (0x4008C270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ +#define REG_PWM_CCNT3 (0x4008C274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ +#define REG_PWM_DT3 (0x4008C278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ +#define REG_PWM_DTUPD3 (0x4008C27CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ +#else +#define REG_PWM_CLK (*(RwReg*)0x4008C000U) /**< \brief (PWM) PWM Clock Register */ +#define REG_PWM_ENA (*(WoReg*)0x4008C004U) /**< \brief (PWM) PWM Enable Register */ +#define REG_PWM_DIS (*(WoReg*)0x4008C008U) /**< \brief (PWM) PWM Disable Register */ +#define REG_PWM_SR (*(RoReg*)0x4008C00CU) /**< \brief (PWM) PWM Status Register */ +#define REG_PWM_IER1 (*(WoReg*)0x4008C010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ +#define REG_PWM_IDR1 (*(WoReg*)0x4008C014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ +#define REG_PWM_IMR1 (*(RoReg*)0x4008C018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ +#define REG_PWM_ISR1 (*(RoReg*)0x4008C01CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ +#define REG_PWM_SCM (*(RwReg*)0x4008C020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ +#define REG_PWM_SCUC (*(RwReg*)0x4008C028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ +#define REG_PWM_SCUP (*(RwReg*)0x4008C02CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ +#define REG_PWM_SCUPUPD (*(WoReg*)0x4008C030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ +#define REG_PWM_IER2 (*(WoReg*)0x4008C034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ +#define REG_PWM_IDR2 (*(WoReg*)0x4008C038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ +#define REG_PWM_IMR2 (*(RoReg*)0x4008C03CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ +#define REG_PWM_ISR2 (*(RoReg*)0x4008C040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ +#define REG_PWM_OOV (*(RwReg*)0x4008C044U) /**< \brief (PWM) PWM Output Override Value Register */ +#define REG_PWM_OS (*(RwReg*)0x4008C048U) /**< \brief (PWM) PWM Output Selection Register */ +#define REG_PWM_OSS (*(WoReg*)0x4008C04CU) /**< \brief (PWM) PWM Output Selection Set Register */ +#define REG_PWM_OSC (*(WoReg*)0x4008C050U) /**< \brief (PWM) PWM Output Selection Clear Register */ +#define REG_PWM_OSSUPD (*(WoReg*)0x4008C054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ +#define REG_PWM_OSCUPD (*(WoReg*)0x4008C058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ +#define REG_PWM_FMR (*(RwReg*)0x4008C05CU) /**< \brief (PWM) PWM Fault Mode Register */ +#define REG_PWM_FSR (*(RoReg*)0x4008C060U) /**< \brief (PWM) PWM Fault Status Register */ +#define REG_PWM_FCR (*(WoReg*)0x4008C064U) /**< \brief (PWM) PWM Fault Clear Register */ +#define REG_PWM_FPV (*(RwReg*)0x4008C068U) /**< \brief (PWM) PWM Fault Protection Value Register */ +#define REG_PWM_FPE (*(RwReg*)0x4008C06CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ +#define REG_PWM_ELMR (*(RwReg*)0x4008C07CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ +#define REG_PWM_SMMR (*(RwReg*)0x4008C0B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */ +#define REG_PWM_WPCR (*(WoReg*)0x4008C0E4U) /**< \brief (PWM) PWM Write Protect Control Register */ +#define REG_PWM_WPSR (*(RoReg*)0x4008C0E8U) /**< \brief (PWM) PWM Write Protect Status Register */ +#define REG_PWM_TPR (*(RwReg*)0x4008C108U) /**< \brief (PWM) Transmit Pointer Register */ +#define REG_PWM_TCR (*(RwReg*)0x4008C10CU) /**< \brief (PWM) Transmit Counter Register */ +#define REG_PWM_TNPR (*(RwReg*)0x4008C118U) /**< \brief (PWM) Transmit Next Pointer Register */ +#define REG_PWM_TNCR (*(RwReg*)0x4008C11CU) /**< \brief (PWM) Transmit Next Counter Register */ +#define REG_PWM_PTCR (*(WoReg*)0x4008C120U) /**< \brief (PWM) Transfer Control Register */ +#define REG_PWM_PTSR (*(RoReg*)0x4008C124U) /**< \brief (PWM) Transfer Status Register */ +#define REG_PWM_CMPV0 (*(RwReg*)0x4008C130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ +#define REG_PWM_CMPVUPD0 (*(WoReg*)0x4008C134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ +#define REG_PWM_CMPM0 (*(RwReg*)0x4008C138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ +#define REG_PWM_CMPMUPD0 (*(WoReg*)0x4008C13CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ +#define REG_PWM_CMPV1 (*(RwReg*)0x4008C140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ +#define REG_PWM_CMPVUPD1 (*(WoReg*)0x4008C144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ +#define REG_PWM_CMPM1 (*(RwReg*)0x4008C148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ +#define REG_PWM_CMPMUPD1 (*(WoReg*)0x4008C14CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ +#define REG_PWM_CMPV2 (*(RwReg*)0x4008C150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ +#define REG_PWM_CMPVUPD2 (*(WoReg*)0x4008C154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ +#define REG_PWM_CMPM2 (*(RwReg*)0x4008C158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ +#define REG_PWM_CMPMUPD2 (*(WoReg*)0x4008C15CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ +#define REG_PWM_CMPV3 (*(RwReg*)0x4008C160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ +#define REG_PWM_CMPVUPD3 (*(WoReg*)0x4008C164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ +#define REG_PWM_CMPM3 (*(RwReg*)0x4008C168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ +#define REG_PWM_CMPMUPD3 (*(WoReg*)0x4008C16CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ +#define REG_PWM_CMPV4 (*(RwReg*)0x4008C170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ +#define REG_PWM_CMPVUPD4 (*(WoReg*)0x4008C174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ +#define REG_PWM_CMPM4 (*(RwReg*)0x4008C178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ +#define REG_PWM_CMPMUPD4 (*(WoReg*)0x4008C17CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ +#define REG_PWM_CMPV5 (*(RwReg*)0x4008C180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ +#define REG_PWM_CMPVUPD5 (*(WoReg*)0x4008C184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ +#define REG_PWM_CMPM5 (*(RwReg*)0x4008C188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ +#define REG_PWM_CMPMUPD5 (*(WoReg*)0x4008C18CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ +#define REG_PWM_CMPV6 (*(RwReg*)0x4008C190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ +#define REG_PWM_CMPVUPD6 (*(WoReg*)0x4008C194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ +#define REG_PWM_CMPM6 (*(RwReg*)0x4008C198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ +#define REG_PWM_CMPMUPD6 (*(WoReg*)0x4008C19CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ +#define REG_PWM_CMPV7 (*(RwReg*)0x4008C1A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ +#define REG_PWM_CMPVUPD7 (*(WoReg*)0x4008C1A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ +#define REG_PWM_CMPM7 (*(RwReg*)0x4008C1A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ +#define REG_PWM_CMPMUPD7 (*(WoReg*)0x4008C1ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ +#define REG_PWM_CMR0 (*(RwReg*)0x4008C200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ +#define REG_PWM_CDTY0 (*(RwReg*)0x4008C204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ +#define REG_PWM_CDTYUPD0 (*(WoReg*)0x4008C208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ +#define REG_PWM_CPRD0 (*(RwReg*)0x4008C20CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ +#define REG_PWM_CPRDUPD0 (*(WoReg*)0x4008C210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ +#define REG_PWM_CCNT0 (*(RoReg*)0x4008C214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ +#define REG_PWM_DT0 (*(RwReg*)0x4008C218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ +#define REG_PWM_DTUPD0 (*(WoReg*)0x4008C21CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ +#define REG_PWM_CMR1 (*(RwReg*)0x4008C220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ +#define REG_PWM_CDTY1 (*(RwReg*)0x4008C224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ +#define REG_PWM_CDTYUPD1 (*(WoReg*)0x4008C228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ +#define REG_PWM_CPRD1 (*(RwReg*)0x4008C22CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ +#define REG_PWM_CPRDUPD1 (*(WoReg*)0x4008C230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ +#define REG_PWM_CCNT1 (*(RoReg*)0x4008C234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ +#define REG_PWM_DT1 (*(RwReg*)0x4008C238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ +#define REG_PWM_DTUPD1 (*(WoReg*)0x4008C23CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ +#define REG_PWM_CMR2 (*(RwReg*)0x4008C240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ +#define REG_PWM_CDTY2 (*(RwReg*)0x4008C244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ +#define REG_PWM_CDTYUPD2 (*(WoReg*)0x4008C248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ +#define REG_PWM_CPRD2 (*(RwReg*)0x4008C24CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ +#define REG_PWM_CPRDUPD2 (*(WoReg*)0x4008C250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ +#define REG_PWM_CCNT2 (*(RoReg*)0x4008C254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ +#define REG_PWM_DT2 (*(RwReg*)0x4008C258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ +#define REG_PWM_DTUPD2 (*(WoReg*)0x4008C25CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ +#define REG_PWM_CMR3 (*(RwReg*)0x4008C260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ +#define REG_PWM_CDTY3 (*(RwReg*)0x4008C264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ +#define REG_PWM_CDTYUPD3 (*(WoReg*)0x4008C268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ +#define REG_PWM_CPRD3 (*(RwReg*)0x4008C26CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ +#define REG_PWM_CPRDUPD3 (*(WoReg*)0x4008C270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ +#define REG_PWM_CCNT3 (*(RoReg*)0x4008C274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ +#define REG_PWM_DT3 (*(RwReg*)0x4008C278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ +#define REG_PWM_DTUPD3 (*(WoReg*)0x4008C27CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_PWM_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/rstc.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/rstc.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,44 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_RSTC_INSTANCE_ +#define _SAM3U_RSTC_INSTANCE_ + +/* ========== Register definition for RSTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RSTC_CR (0x400E1200U) /**< \brief (RSTC) Control Register */ +#define REG_RSTC_SR (0x400E1204U) /**< \brief (RSTC) Status Register */ +#define REG_RSTC_MR (0x400E1208U) /**< \brief (RSTC) Mode Register */ +#else +#define REG_RSTC_CR (*(WoReg*)0x400E1200U) /**< \brief (RSTC) Control Register */ +#define REG_RSTC_SR (*(RoReg*)0x400E1204U) /**< \brief (RSTC) Status Register */ +#define REG_RSTC_MR (*(RwReg*)0x400E1208U) /**< \brief (RSTC) Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_RSTC_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/rtc.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/rtc.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,64 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_RTC_INSTANCE_ +#define _SAM3U_RTC_INSTANCE_ + +/* ========== Register definition for RTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RTC_CR (0x400E1260U) /**< \brief (RTC) Control Register */ +#define REG_RTC_MR (0x400E1264U) /**< \brief (RTC) Mode Register */ +#define REG_RTC_TIMR (0x400E1268U) /**< \brief (RTC) Time Register */ +#define REG_RTC_CALR (0x400E126CU) /**< \brief (RTC) Calendar Register */ +#define REG_RTC_TIMALR (0x400E1270U) /**< \brief (RTC) Time Alarm Register */ +#define REG_RTC_CALALR (0x400E1274U) /**< \brief (RTC) Calendar Alarm Register */ +#define REG_RTC_SR (0x400E1278U) /**< \brief (RTC) Status Register */ +#define REG_RTC_SCCR (0x400E127CU) /**< \brief (RTC) Status Clear Command Register */ +#define REG_RTC_IER (0x400E1280U) /**< \brief (RTC) Interrupt Enable Register */ +#define REG_RTC_IDR (0x400E1284U) /**< \brief (RTC) Interrupt Disable Register */ +#define REG_RTC_IMR (0x400E1288U) /**< \brief (RTC) Interrupt Mask Register */ +#define REG_RTC_VER (0x400E128CU) /**< \brief (RTC) Valid Entry Register */ +#define REG_RTC_WPMR (0x400E1344U) /**< \brief (RTC) Write Protect Mode Register */ +#else +#define REG_RTC_CR (*(RwReg*)0x400E1260U) /**< \brief (RTC) Control Register */ +#define REG_RTC_MR (*(RwReg*)0x400E1264U) /**< \brief (RTC) Mode Register */ +#define REG_RTC_TIMR (*(RwReg*)0x400E1268U) /**< \brief (RTC) Time Register */ +#define REG_RTC_CALR (*(RwReg*)0x400E126CU) /**< \brief (RTC) Calendar Register */ +#define REG_RTC_TIMALR (*(RwReg*)0x400E1270U) /**< \brief (RTC) Time Alarm Register */ +#define REG_RTC_CALALR (*(RwReg*)0x400E1274U) /**< \brief (RTC) Calendar Alarm Register */ +#define REG_RTC_SR (*(RoReg*)0x400E1278U) /**< \brief (RTC) Status Register */ +#define REG_RTC_SCCR (*(WoReg*)0x400E127CU) /**< \brief (RTC) Status Clear Command Register */ +#define REG_RTC_IER (*(WoReg*)0x400E1280U) /**< \brief (RTC) Interrupt Enable Register */ +#define REG_RTC_IDR (*(WoReg*)0x400E1284U) /**< \brief (RTC) Interrupt Disable Register */ +#define REG_RTC_IMR (*(RoReg*)0x400E1288U) /**< \brief (RTC) Interrupt Mask Register */ +#define REG_RTC_VER (*(RoReg*)0x400E128CU) /**< \brief (RTC) Valid Entry Register */ +#define REG_RTC_WPMR (*(RwReg*)0x400E1344U) /**< \brief (RTC) Write Protect Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_RTC_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/rtt.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/rtt.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,46 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_RTT_INSTANCE_ +#define _SAM3U_RTT_INSTANCE_ + +/* ========== Register definition for RTT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RTT_MR (0x400E1230U) /**< \brief (RTT) Mode Register */ +#define REG_RTT_AR (0x400E1234U) /**< \brief (RTT) Alarm Register */ +#define REG_RTT_VR (0x400E1238U) /**< \brief (RTT) Value Register */ +#define REG_RTT_SR (0x400E123CU) /**< \brief (RTT) Status Register */ +#else +#define REG_RTT_MR (*(RwReg*)0x400E1230U) /**< \brief (RTT) Mode Register */ +#define REG_RTT_AR (*(RwReg*)0x400E1234U) /**< \brief (RTT) Alarm Register */ +#define REG_RTT_VR (*(RoReg*)0x400E1238U) /**< \brief (RTT) Value Register */ +#define REG_RTT_SR (*(RoReg*)0x400E123CU) /**< \brief (RTT) Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_RTT_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/smc.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/smc.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,144 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_SMC_INSTANCE_ +#define _SAM3U_SMC_INSTANCE_ + +/* ========== Register definition for SMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SMC_CFG (0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */ +#define REG_SMC_CTRL (0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */ +#define REG_SMC_SR (0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */ +#define REG_SMC_IER (0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */ +#define REG_SMC_IDR (0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */ +#define REG_SMC_IMR (0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */ +#define REG_SMC_ADDR (0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */ +#define REG_SMC_BANK (0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */ +#define REG_SMC_ECC_CTRL (0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */ +#define REG_SMC_ECC_MD (0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */ +#define REG_SMC_ECC_SR1 (0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */ +#define REG_SMC_ECC_PR0 (0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */ +#define REG_SMC_ECC_PR1 (0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */ +#define REG_SMC_ECC_SR2 (0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */ +#define REG_SMC_ECC_PR2 (0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */ +#define REG_SMC_ECC_PR3 (0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */ +#define REG_SMC_ECC_PR4 (0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */ +#define REG_SMC_ECC_PR5 (0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */ +#define REG_SMC_ECC_PR6 (0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */ +#define REG_SMC_ECC_PR7 (0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */ +#define REG_SMC_ECC_PR8 (0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */ +#define REG_SMC_ECC_PR9 (0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */ +#define REG_SMC_ECC_PR10 (0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */ +#define REG_SMC_ECC_PR11 (0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */ +#define REG_SMC_ECC_PR12 (0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */ +#define REG_SMC_ECC_PR13 (0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */ +#define REG_SMC_ECC_PR14 (0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */ +#define REG_SMC_ECC_PR15 (0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */ +#define REG_SMC_SETUP0 (0x400E0070U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ +#define REG_SMC_PULSE0 (0x400E0074U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ +#define REG_SMC_CYCLE0 (0x400E0078U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ +#define REG_SMC_TIMINGS0 (0x400E007CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */ +#define REG_SMC_MODE0 (0x400E0080U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ +#define REG_SMC_SETUP1 (0x400E0084U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ +#define REG_SMC_PULSE1 (0x400E0088U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ +#define REG_SMC_CYCLE1 (0x400E008CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ +#define REG_SMC_TIMINGS1 (0x400E0090U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */ +#define REG_SMC_MODE1 (0x400E0094U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ +#define REG_SMC_SETUP2 (0x400E0098U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ +#define REG_SMC_PULSE2 (0x400E009CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ +#define REG_SMC_CYCLE2 (0x400E00A0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ +#define REG_SMC_TIMINGS2 (0x400E00A4U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */ +#define REG_SMC_MODE2 (0x400E00A8U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ +#define REG_SMC_SETUP3 (0x400E00ACU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ +#define REG_SMC_PULSE3 (0x400E00B0U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ +#define REG_SMC_CYCLE3 (0x400E00B4U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ +#define REG_SMC_TIMINGS3 (0x400E00B8U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */ +#define REG_SMC_MODE3 (0x400E00BCU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ +#define REG_SMC_OCMS (0x400E0110U) /**< \brief (SMC) SMC OCMS Register */ +#define REG_SMC_KEY1 (0x400E0114U) /**< \brief (SMC) SMC OCMS KEY1 Register */ +#define REG_SMC_KEY2 (0x400E0118U) /**< \brief (SMC) SMC OCMS KEY2 Register */ +#define REG_SMC_WPCR (0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */ +#define REG_SMC_WPSR (0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */ +#else +#define REG_SMC_CFG (*(RwReg*)0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */ +#define REG_SMC_CTRL (*(WoReg*)0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */ +#define REG_SMC_SR (*(RoReg*)0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */ +#define REG_SMC_IER (*(WoReg*)0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */ +#define REG_SMC_IDR (*(WoReg*)0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */ +#define REG_SMC_IMR (*(RoReg*)0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */ +#define REG_SMC_ADDR (*(RwReg*)0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */ +#define REG_SMC_BANK (*(RwReg*)0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */ +#define REG_SMC_ECC_CTRL (*(WoReg*)0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */ +#define REG_SMC_ECC_MD (*(RwReg*)0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */ +#define REG_SMC_ECC_SR1 (*(RoReg*)0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */ +#define REG_SMC_ECC_PR0 (*(RoReg*)0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */ +#define REG_SMC_ECC_PR1 (*(RoReg*)0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */ +#define REG_SMC_ECC_SR2 (*(RoReg*)0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */ +#define REG_SMC_ECC_PR2 (*(RoReg*)0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */ +#define REG_SMC_ECC_PR3 (*(RoReg*)0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */ +#define REG_SMC_ECC_PR4 (*(RoReg*)0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */ +#define REG_SMC_ECC_PR5 (*(RoReg*)0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */ +#define REG_SMC_ECC_PR6 (*(RoReg*)0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */ +#define REG_SMC_ECC_PR7 (*(RoReg*)0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */ +#define REG_SMC_ECC_PR8 (*(RoReg*)0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */ +#define REG_SMC_ECC_PR9 (*(RoReg*)0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */ +#define REG_SMC_ECC_PR10 (*(RoReg*)0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */ +#define REG_SMC_ECC_PR11 (*(RoReg*)0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */ +#define REG_SMC_ECC_PR12 (*(RoReg*)0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */ +#define REG_SMC_ECC_PR13 (*(RoReg*)0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */ +#define REG_SMC_ECC_PR14 (*(RoReg*)0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */ +#define REG_SMC_ECC_PR15 (*(RoReg*)0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */ +#define REG_SMC_SETUP0 (*(RwReg*)0x400E0070U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ +#define REG_SMC_PULSE0 (*(RwReg*)0x400E0074U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ +#define REG_SMC_CYCLE0 (*(RwReg*)0x400E0078U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ +#define REG_SMC_TIMINGS0 (*(RwReg*)0x400E007CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */ +#define REG_SMC_MODE0 (*(RwReg*)0x400E0080U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ +#define REG_SMC_SETUP1 (*(RwReg*)0x400E0084U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ +#define REG_SMC_PULSE1 (*(RwReg*)0x400E0088U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ +#define REG_SMC_CYCLE1 (*(RwReg*)0x400E008CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ +#define REG_SMC_TIMINGS1 (*(RwReg*)0x400E0090U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */ +#define REG_SMC_MODE1 (*(RwReg*)0x400E0094U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ +#define REG_SMC_SETUP2 (*(RwReg*)0x400E0098U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ +#define REG_SMC_PULSE2 (*(RwReg*)0x400E009CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ +#define REG_SMC_CYCLE2 (*(RwReg*)0x400E00A0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ +#define REG_SMC_TIMINGS2 (*(RwReg*)0x400E00A4U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */ +#define REG_SMC_MODE2 (*(RwReg*)0x400E00A8U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ +#define REG_SMC_SETUP3 (*(RwReg*)0x400E00ACU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ +#define REG_SMC_PULSE3 (*(RwReg*)0x400E00B0U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ +#define REG_SMC_CYCLE3 (*(RwReg*)0x400E00B4U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ +#define REG_SMC_TIMINGS3 (*(RwReg*)0x400E00B8U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */ +#define REG_SMC_MODE3 (*(RwReg*)0x400E00BCU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ +#define REG_SMC_OCMS (*(RwReg*)0x400E0110U) /**< \brief (SMC) SMC OCMS Register */ +#define REG_SMC_KEY1 (*(WoReg*)0x400E0114U) /**< \brief (SMC) SMC OCMS KEY1 Register */ +#define REG_SMC_KEY2 (*(WoReg*)0x400E0118U) /**< \brief (SMC) SMC OCMS KEY2 Register */ +#define REG_SMC_WPCR (*(WoReg*)0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */ +#define REG_SMC_WPSR (*(RoReg*)0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_SMC_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/spi.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/spi.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_SPI_INSTANCE_ +#define _SAM3U_SPI_INSTANCE_ + +/* ========== Register definition for SPI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SPI_CR (0x40008000U) /**< \brief (SPI) Control Register */ +#define REG_SPI_MR (0x40008004U) /**< \brief (SPI) Mode Register */ +#define REG_SPI_RDR (0x40008008U) /**< \brief (SPI) Receive Data Register */ +#define REG_SPI_TDR (0x4000800CU) /**< \brief (SPI) Transmit Data Register */ +#define REG_SPI_SR (0x40008010U) /**< \brief (SPI) Status Register */ +#define REG_SPI_IER (0x40008014U) /**< \brief (SPI) Interrupt Enable Register */ +#define REG_SPI_IDR (0x40008018U) /**< \brief (SPI) Interrupt Disable Register */ +#define REG_SPI_IMR (0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */ +#define REG_SPI_CSR (0x40008030U) /**< \brief (SPI) Chip Select Register */ +#define REG_SPI_WPMR (0x400080E4U) /**< \brief (SPI) Write Protection Control Register */ +#define REG_SPI_WPSR (0x400080E8U) /**< \brief (SPI) Write Protection Status Register */ +#else +#define REG_SPI_CR (*(WoReg*)0x40008000U) /**< \brief (SPI) Control Register */ +#define REG_SPI_MR (*(RwReg*)0x40008004U) /**< \brief (SPI) Mode Register */ +#define REG_SPI_RDR (*(RoReg*)0x40008008U) /**< \brief (SPI) Receive Data Register */ +#define REG_SPI_TDR (*(WoReg*)0x4000800CU) /**< \brief (SPI) Transmit Data Register */ +#define REG_SPI_SR (*(RoReg*)0x40008010U) /**< \brief (SPI) Status Register */ +#define REG_SPI_IER (*(WoReg*)0x40008014U) /**< \brief (SPI) Interrupt Enable Register */ +#define REG_SPI_IDR (*(WoReg*)0x40008018U) /**< \brief (SPI) Interrupt Disable Register */ +#define REG_SPI_IMR (*(RoReg*)0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */ +#define REG_SPI_CSR (*(RwReg*)0x40008030U) /**< \brief (SPI) Chip Select Register */ +#define REG_SPI_WPMR (*(RwReg*)0x400080E4U) /**< \brief (SPI) Write Protection Control Register */ +#define REG_SPI_WPSR (*(RoReg*)0x400080E8U) /**< \brief (SPI) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_SPI_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/ssc.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/ssc.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_SSC_INSTANCE_ +#define _SAM3U_SSC_INSTANCE_ + +/* ========== Register definition for SSC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SSC_CR (0x40004000U) /**< \brief (SSC) Control Register */ +#define REG_SSC_CMR (0x40004004U) /**< \brief (SSC) Clock Mode Register */ +#define REG_SSC_RCMR (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ +#define REG_SSC_RFMR (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ +#define REG_SSC_TCMR (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ +#define REG_SSC_TFMR (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ +#define REG_SSC_RHR (0x40004020U) /**< \brief (SSC) Receive Holding Register */ +#define REG_SSC_THR (0x40004024U) /**< \brief (SSC) Transmit Holding Register */ +#define REG_SSC_RSHR (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ +#define REG_SSC_TSHR (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ +#define REG_SSC_RC0R (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ +#define REG_SSC_RC1R (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ +#define REG_SSC_SR (0x40004040U) /**< \brief (SSC) Status Register */ +#define REG_SSC_IER (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ +#define REG_SSC_IDR (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ +#define REG_SSC_IMR (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ +#define REG_SSC_WPMR (0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */ +#define REG_SSC_WPSR (0x400040E8U) /**< \brief (SSC) Write Protect Status Register */ +#else +#define REG_SSC_CR (*(WoReg*)0x40004000U) /**< \brief (SSC) Control Register */ +#define REG_SSC_CMR (*(RwReg*)0x40004004U) /**< \brief (SSC) Clock Mode Register */ +#define REG_SSC_RCMR (*(RwReg*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ +#define REG_SSC_RFMR (*(RwReg*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ +#define REG_SSC_TCMR (*(RwReg*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ +#define REG_SSC_TFMR (*(RwReg*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ +#define REG_SSC_RHR (*(RoReg*)0x40004020U) /**< \brief (SSC) Receive Holding Register */ +#define REG_SSC_THR (*(WoReg*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */ +#define REG_SSC_RSHR (*(RoReg*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ +#define REG_SSC_TSHR (*(RwReg*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ +#define REG_SSC_RC0R (*(RwReg*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ +#define REG_SSC_RC1R (*(RwReg*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ +#define REG_SSC_SR (*(RoReg*)0x40004040U) /**< \brief (SSC) Status Register */ +#define REG_SSC_IER (*(WoReg*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ +#define REG_SSC_IDR (*(WoReg*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ +#define REG_SSC_IMR (*(RoReg*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ +#define REG_SSC_WPMR (*(RwReg*)0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */ +#define REG_SSC_WPSR (*(RoReg*)0x400040E8U) /**< \brief (SSC) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_SSC_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/supc.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/supc.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,50 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_SUPC_INSTANCE_ +#define _SAM3U_SUPC_INSTANCE_ + +/* ========== Register definition for SUPC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SUPC_CR (0x400E1210U) /**< \brief (SUPC) Supply Controller Control Register */ +#define REG_SUPC_SMMR (0x400E1214U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ +#define REG_SUPC_MR (0x400E1218U) /**< \brief (SUPC) Supply Controller Mode Register */ +#define REG_SUPC_WUMR (0x400E121CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */ +#define REG_SUPC_WUIR (0x400E1220U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */ +#define REG_SUPC_SR (0x400E1224U) /**< \brief (SUPC) Supply Controller Status Register */ +#else +#define REG_SUPC_CR (*(WoReg*)0x400E1210U) /**< \brief (SUPC) Supply Controller Control Register */ +#define REG_SUPC_SMMR (*(RwReg*)0x400E1214U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ +#define REG_SUPC_MR (*(RwReg*)0x400E1218U) /**< \brief (SUPC) Supply Controller Mode Register */ +#define REG_SUPC_WUMR (*(RwReg*)0x400E121CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */ +#define REG_SUPC_WUIR (*(RwReg*)0x400E1220U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */ +#define REG_SUPC_SR (*(RoReg*)0x400E1224U) /**< \brief (SUPC) Supply Controller Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_SUPC_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/tc0.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/tc0.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,110 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_TC0_INSTANCE_ +#define _SAM3U_TC0_INSTANCE_ + +/* ========== Register definition for TC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC0_CCR0 (0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ +#define REG_TC0_CMR0 (0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ +#define REG_TC0_CV0 (0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */ +#define REG_TC0_RA0 (0x40080014U) /**< \brief (TC0) Register A (channel = 0) */ +#define REG_TC0_RB0 (0x40080018U) /**< \brief (TC0) Register B (channel = 0) */ +#define REG_TC0_RC0 (0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */ +#define REG_TC0_SR0 (0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */ +#define REG_TC0_IER0 (0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ +#define REG_TC0_IDR0 (0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ +#define REG_TC0_IMR0 (0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ +#define REG_TC0_CCR1 (0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ +#define REG_TC0_CMR1 (0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ +#define REG_TC0_CV1 (0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */ +#define REG_TC0_RA1 (0x40080054U) /**< \brief (TC0) Register A (channel = 1) */ +#define REG_TC0_RB1 (0x40080058U) /**< \brief (TC0) Register B (channel = 1) */ +#define REG_TC0_RC1 (0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */ +#define REG_TC0_SR1 (0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */ +#define REG_TC0_IER1 (0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ +#define REG_TC0_IDR1 (0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ +#define REG_TC0_IMR1 (0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ +#define REG_TC0_CCR2 (0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ +#define REG_TC0_CMR2 (0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ +#define REG_TC0_CV2 (0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */ +#define REG_TC0_RA2 (0x40080094U) /**< \brief (TC0) Register A (channel = 2) */ +#define REG_TC0_RB2 (0x40080098U) /**< \brief (TC0) Register B (channel = 2) */ +#define REG_TC0_RC2 (0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */ +#define REG_TC0_SR2 (0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */ +#define REG_TC0_IER2 (0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ +#define REG_TC0_IDR2 (0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ +#define REG_TC0_IMR2 (0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ +#define REG_TC0_BCR (0x400800C0U) /**< \brief (TC0) Block Control Register */ +#define REG_TC0_BMR (0x400800C4U) /**< \brief (TC0) Block Mode Register */ +#define REG_TC0_QIER (0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ +#define REG_TC0_QIDR (0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ +#define REG_TC0_QIMR (0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ +#define REG_TC0_QISR (0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ +#else +#define REG_TC0_CCR0 (*(WoReg*)0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ +#define REG_TC0_CMR0 (*(RwReg*)0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ +#define REG_TC0_CV0 (*(RoReg*)0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */ +#define REG_TC0_RA0 (*(RwReg*)0x40080014U) /**< \brief (TC0) Register A (channel = 0) */ +#define REG_TC0_RB0 (*(RwReg*)0x40080018U) /**< \brief (TC0) Register B (channel = 0) */ +#define REG_TC0_RC0 (*(RwReg*)0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */ +#define REG_TC0_SR0 (*(RoReg*)0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */ +#define REG_TC0_IER0 (*(WoReg*)0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ +#define REG_TC0_IDR0 (*(WoReg*)0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ +#define REG_TC0_IMR0 (*(RoReg*)0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ +#define REG_TC0_CCR1 (*(WoReg*)0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ +#define REG_TC0_CMR1 (*(RwReg*)0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ +#define REG_TC0_CV1 (*(RoReg*)0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */ +#define REG_TC0_RA1 (*(RwReg*)0x40080054U) /**< \brief (TC0) Register A (channel = 1) */ +#define REG_TC0_RB1 (*(RwReg*)0x40080058U) /**< \brief (TC0) Register B (channel = 1) */ +#define REG_TC0_RC1 (*(RwReg*)0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */ +#define REG_TC0_SR1 (*(RoReg*)0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */ +#define REG_TC0_IER1 (*(WoReg*)0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ +#define REG_TC0_IDR1 (*(WoReg*)0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ +#define REG_TC0_IMR1 (*(RoReg*)0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ +#define REG_TC0_CCR2 (*(WoReg*)0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ +#define REG_TC0_CMR2 (*(RwReg*)0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ +#define REG_TC0_CV2 (*(RoReg*)0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */ +#define REG_TC0_RA2 (*(RwReg*)0x40080094U) /**< \brief (TC0) Register A (channel = 2) */ +#define REG_TC0_RB2 (*(RwReg*)0x40080098U) /**< \brief (TC0) Register B (channel = 2) */ +#define REG_TC0_RC2 (*(RwReg*)0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */ +#define REG_TC0_SR2 (*(RoReg*)0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */ +#define REG_TC0_IER2 (*(WoReg*)0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ +#define REG_TC0_IDR2 (*(WoReg*)0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ +#define REG_TC0_IMR2 (*(RoReg*)0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ +#define REG_TC0_BCR (*(WoReg*)0x400800C0U) /**< \brief (TC0) Block Control Register */ +#define REG_TC0_BMR (*(RwReg*)0x400800C4U) /**< \brief (TC0) Block Mode Register */ +#define REG_TC0_QIER (*(WoReg*)0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ +#define REG_TC0_QIDR (*(WoReg*)0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ +#define REG_TC0_QIMR (*(RoReg*)0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ +#define REG_TC0_QISR (*(RoReg*)0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_TC0_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/twi0.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/twi0.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_TWI0_INSTANCE_ +#define _SAM3U_TWI0_INSTANCE_ + +/* ========== Register definition for TWI0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TWI0_CR (0x40084000U) /**< \brief (TWI0) Control Register */ +#define REG_TWI0_MMR (0x40084004U) /**< \brief (TWI0) Master Mode Register */ +#define REG_TWI0_SMR (0x40084008U) /**< \brief (TWI0) Slave Mode Register */ +#define REG_TWI0_IADR (0x4008400CU) /**< \brief (TWI0) Internal Address Register */ +#define REG_TWI0_CWGR (0x40084010U) /**< \brief (TWI0) Clock Waveform Generator Register */ +#define REG_TWI0_SR (0x40084020U) /**< \brief (TWI0) Status Register */ +#define REG_TWI0_IER (0x40084024U) /**< \brief (TWI0) Interrupt Enable Register */ +#define REG_TWI0_IDR (0x40084028U) /**< \brief (TWI0) Interrupt Disable Register */ +#define REG_TWI0_IMR (0x4008402CU) /**< \brief (TWI0) Interrupt Mask Register */ +#define REG_TWI0_RHR (0x40084030U) /**< \brief (TWI0) Receive Holding Register */ +#define REG_TWI0_THR (0x40084034U) /**< \brief (TWI0) Transmit Holding Register */ +#define REG_TWI0_RPR (0x40084100U) /**< \brief (TWI0) Receive Pointer Register */ +#define REG_TWI0_RCR (0x40084104U) /**< \brief (TWI0) Receive Counter Register */ +#define REG_TWI0_TPR (0x40084108U) /**< \brief (TWI0) Transmit Pointer Register */ +#define REG_TWI0_TCR (0x4008410CU) /**< \brief (TWI0) Transmit Counter Register */ +#define REG_TWI0_RNPR (0x40084110U) /**< \brief (TWI0) Receive Next Pointer Register */ +#define REG_TWI0_RNCR (0x40084114U) /**< \brief (TWI0) Receive Next Counter Register */ +#define REG_TWI0_TNPR (0x40084118U) /**< \brief (TWI0) Transmit Next Pointer Register */ +#define REG_TWI0_TNCR (0x4008411CU) /**< \brief (TWI0) Transmit Next Counter Register */ +#define REG_TWI0_PTCR (0x40084120U) /**< \brief (TWI0) Transfer Control Register */ +#define REG_TWI0_PTSR (0x40084124U) /**< \brief (TWI0) Transfer Status Register */ +#else +#define REG_TWI0_CR (*(WoReg*)0x40084000U) /**< \brief (TWI0) Control Register */ +#define REG_TWI0_MMR (*(RwReg*)0x40084004U) /**< \brief (TWI0) Master Mode Register */ +#define REG_TWI0_SMR (*(RwReg*)0x40084008U) /**< \brief (TWI0) Slave Mode Register */ +#define REG_TWI0_IADR (*(RwReg*)0x4008400CU) /**< \brief (TWI0) Internal Address Register */ +#define REG_TWI0_CWGR (*(RwReg*)0x40084010U) /**< \brief (TWI0) Clock Waveform Generator Register */ +#define REG_TWI0_SR (*(RoReg*)0x40084020U) /**< \brief (TWI0) Status Register */ +#define REG_TWI0_IER (*(WoReg*)0x40084024U) /**< \brief (TWI0) Interrupt Enable Register */ +#define REG_TWI0_IDR (*(WoReg*)0x40084028U) /**< \brief (TWI0) Interrupt Disable Register */ +#define REG_TWI0_IMR (*(RoReg*)0x4008402CU) /**< \brief (TWI0) Interrupt Mask Register */ +#define REG_TWI0_RHR (*(RoReg*)0x40084030U) /**< \brief (TWI0) Receive Holding Register */ +#define REG_TWI0_THR (*(WoReg*)0x40084034U) /**< \brief (TWI0) Transmit Holding Register */ +#define REG_TWI0_RPR (*(RwReg*)0x40084100U) /**< \brief (TWI0) Receive Pointer Register */ +#define REG_TWI0_RCR (*(RwReg*)0x40084104U) /**< \brief (TWI0) Receive Counter Register */ +#define REG_TWI0_TPR (*(RwReg*)0x40084108U) /**< \brief (TWI0) Transmit Pointer Register */ +#define REG_TWI0_TCR (*(RwReg*)0x4008410CU) /**< \brief (TWI0) Transmit Counter Register */ +#define REG_TWI0_RNPR (*(RwReg*)0x40084110U) /**< \brief (TWI0) Receive Next Pointer Register */ +#define REG_TWI0_RNCR (*(RwReg*)0x40084114U) /**< \brief (TWI0) Receive Next Counter Register */ +#define REG_TWI0_TNPR (*(RwReg*)0x40084118U) /**< \brief (TWI0) Transmit Next Pointer Register */ +#define REG_TWI0_TNCR (*(RwReg*)0x4008411CU) /**< \brief (TWI0) Transmit Next Counter Register */ +#define REG_TWI0_PTCR (*(WoReg*)0x40084120U) /**< \brief (TWI0) Transfer Control Register */ +#define REG_TWI0_PTSR (*(RoReg*)0x40084124U) /**< \brief (TWI0) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_TWI0_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/twi1.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/twi1.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_TWI1_INSTANCE_ +#define _SAM3U_TWI1_INSTANCE_ + +/* ========== Register definition for TWI1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TWI1_CR (0x40088000U) /**< \brief (TWI1) Control Register */ +#define REG_TWI1_MMR (0x40088004U) /**< \brief (TWI1) Master Mode Register */ +#define REG_TWI1_SMR (0x40088008U) /**< \brief (TWI1) Slave Mode Register */ +#define REG_TWI1_IADR (0x4008800CU) /**< \brief (TWI1) Internal Address Register */ +#define REG_TWI1_CWGR (0x40088010U) /**< \brief (TWI1) Clock Waveform Generator Register */ +#define REG_TWI1_SR (0x40088020U) /**< \brief (TWI1) Status Register */ +#define REG_TWI1_IER (0x40088024U) /**< \brief (TWI1) Interrupt Enable Register */ +#define REG_TWI1_IDR (0x40088028U) /**< \brief (TWI1) Interrupt Disable Register */ +#define REG_TWI1_IMR (0x4008802CU) /**< \brief (TWI1) Interrupt Mask Register */ +#define REG_TWI1_RHR (0x40088030U) /**< \brief (TWI1) Receive Holding Register */ +#define REG_TWI1_THR (0x40088034U) /**< \brief (TWI1) Transmit Holding Register */ +#define REG_TWI1_RPR (0x40088100U) /**< \brief (TWI1) Receive Pointer Register */ +#define REG_TWI1_RCR (0x40088104U) /**< \brief (TWI1) Receive Counter Register */ +#define REG_TWI1_TPR (0x40088108U) /**< \brief (TWI1) Transmit Pointer Register */ +#define REG_TWI1_TCR (0x4008810CU) /**< \brief (TWI1) Transmit Counter Register */ +#define REG_TWI1_RNPR (0x40088110U) /**< \brief (TWI1) Receive Next Pointer Register */ +#define REG_TWI1_RNCR (0x40088114U) /**< \brief (TWI1) Receive Next Counter Register */ +#define REG_TWI1_TNPR (0x40088118U) /**< \brief (TWI1) Transmit Next Pointer Register */ +#define REG_TWI1_TNCR (0x4008811CU) /**< \brief (TWI1) Transmit Next Counter Register */ +#define REG_TWI1_PTCR (0x40088120U) /**< \brief (TWI1) Transfer Control Register */ +#define REG_TWI1_PTSR (0x40088124U) /**< \brief (TWI1) Transfer Status Register */ +#else +#define REG_TWI1_CR (*(WoReg*)0x40088000U) /**< \brief (TWI1) Control Register */ +#define REG_TWI1_MMR (*(RwReg*)0x40088004U) /**< \brief (TWI1) Master Mode Register */ +#define REG_TWI1_SMR (*(RwReg*)0x40088008U) /**< \brief (TWI1) Slave Mode Register */ +#define REG_TWI1_IADR (*(RwReg*)0x4008800CU) /**< \brief (TWI1) Internal Address Register */ +#define REG_TWI1_CWGR (*(RwReg*)0x40088010U) /**< \brief (TWI1) Clock Waveform Generator Register */ +#define REG_TWI1_SR (*(RoReg*)0x40088020U) /**< \brief (TWI1) Status Register */ +#define REG_TWI1_IER (*(WoReg*)0x40088024U) /**< \brief (TWI1) Interrupt Enable Register */ +#define REG_TWI1_IDR (*(WoReg*)0x40088028U) /**< \brief (TWI1) Interrupt Disable Register */ +#define REG_TWI1_IMR (*(RoReg*)0x4008802CU) /**< \brief (TWI1) Interrupt Mask Register */ +#define REG_TWI1_RHR (*(RoReg*)0x40088030U) /**< \brief (TWI1) Receive Holding Register */ +#define REG_TWI1_THR (*(WoReg*)0x40088034U) /**< \brief (TWI1) Transmit Holding Register */ +#define REG_TWI1_RPR (*(RwReg*)0x40088100U) /**< \brief (TWI1) Receive Pointer Register */ +#define REG_TWI1_RCR (*(RwReg*)0x40088104U) /**< \brief (TWI1) Receive Counter Register */ +#define REG_TWI1_TPR (*(RwReg*)0x40088108U) /**< \brief (TWI1) Transmit Pointer Register */ +#define REG_TWI1_TCR (*(RwReg*)0x4008810CU) /**< \brief (TWI1) Transmit Counter Register */ +#define REG_TWI1_RNPR (*(RwReg*)0x40088110U) /**< \brief (TWI1) Receive Next Pointer Register */ +#define REG_TWI1_RNCR (*(RwReg*)0x40088114U) /**< \brief (TWI1) Receive Next Counter Register */ +#define REG_TWI1_TNPR (*(RwReg*)0x40088118U) /**< \brief (TWI1) Transmit Next Pointer Register */ +#define REG_TWI1_TNCR (*(RwReg*)0x4008811CU) /**< \brief (TWI1) Transmit Next Counter Register */ +#define REG_TWI1_PTCR (*(WoReg*)0x40088120U) /**< \brief (TWI1) Transfer Control Register */ +#define REG_TWI1_PTSR (*(RoReg*)0x40088124U) /**< \brief (TWI1) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_TWI1_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/uart.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/uart.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,76 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_UART_INSTANCE_ +#define _SAM3U_UART_INSTANCE_ + +/* ========== Register definition for UART peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_UART_CR (0x400E0600U) /**< \brief (UART) Control Register */ +#define REG_UART_MR (0x400E0604U) /**< \brief (UART) Mode Register */ +#define REG_UART_IER (0x400E0608U) /**< \brief (UART) Interrupt Enable Register */ +#define REG_UART_IDR (0x400E060CU) /**< \brief (UART) Interrupt Disable Register */ +#define REG_UART_IMR (0x400E0610U) /**< \brief (UART) Interrupt Mask Register */ +#define REG_UART_SR (0x400E0614U) /**< \brief (UART) Status Register */ +#define REG_UART_RHR (0x400E0618U) /**< \brief (UART) Receive Holding Register */ +#define REG_UART_THR (0x400E061CU) /**< \brief (UART) Transmit Holding Register */ +#define REG_UART_BRGR (0x400E0620U) /**< \brief (UART) Baud Rate Generator Register */ +#define REG_UART_RPR (0x400E0700U) /**< \brief (UART) Receive Pointer Register */ +#define REG_UART_RCR (0x400E0704U) /**< \brief (UART) Receive Counter Register */ +#define REG_UART_TPR (0x400E0708U) /**< \brief (UART) Transmit Pointer Register */ +#define REG_UART_TCR (0x400E070CU) /**< \brief (UART) Transmit Counter Register */ +#define REG_UART_RNPR (0x400E0710U) /**< \brief (UART) Receive Next Pointer Register */ +#define REG_UART_RNCR (0x400E0714U) /**< \brief (UART) Receive Next Counter Register */ +#define REG_UART_TNPR (0x400E0718U) /**< \brief (UART) Transmit Next Pointer Register */ +#define REG_UART_TNCR (0x400E071CU) /**< \brief (UART) Transmit Next Counter Register */ +#define REG_UART_PTCR (0x400E0720U) /**< \brief (UART) Transfer Control Register */ +#define REG_UART_PTSR (0x400E0724U) /**< \brief (UART) Transfer Status Register */ +#else +#define REG_UART_CR (*(WoReg*)0x400E0600U) /**< \brief (UART) Control Register */ +#define REG_UART_MR (*(RwReg*)0x400E0604U) /**< \brief (UART) Mode Register */ +#define REG_UART_IER (*(WoReg*)0x400E0608U) /**< \brief (UART) Interrupt Enable Register */ +#define REG_UART_IDR (*(WoReg*)0x400E060CU) /**< \brief (UART) Interrupt Disable Register */ +#define REG_UART_IMR (*(RoReg*)0x400E0610U) /**< \brief (UART) Interrupt Mask Register */ +#define REG_UART_SR (*(RoReg*)0x400E0614U) /**< \brief (UART) Status Register */ +#define REG_UART_RHR (*(RoReg*)0x400E0618U) /**< \brief (UART) Receive Holding Register */ +#define REG_UART_THR (*(WoReg*)0x400E061CU) /**< \brief (UART) Transmit Holding Register */ +#define REG_UART_BRGR (*(RwReg*)0x400E0620U) /**< \brief (UART) Baud Rate Generator Register */ +#define REG_UART_RPR (*(RwReg*)0x400E0700U) /**< \brief (UART) Receive Pointer Register */ +#define REG_UART_RCR (*(RwReg*)0x400E0704U) /**< \brief (UART) Receive Counter Register */ +#define REG_UART_TPR (*(RwReg*)0x400E0708U) /**< \brief (UART) Transmit Pointer Register */ +#define REG_UART_TCR (*(RwReg*)0x400E070CU) /**< \brief (UART) Transmit Counter Register */ +#define REG_UART_RNPR (*(RwReg*)0x400E0710U) /**< \brief (UART) Receive Next Pointer Register */ +#define REG_UART_RNCR (*(RwReg*)0x400E0714U) /**< \brief (UART) Receive Next Counter Register */ +#define REG_UART_TNPR (*(RwReg*)0x400E0718U) /**< \brief (UART) Transmit Next Pointer Register */ +#define REG_UART_TNCR (*(RwReg*)0x400E071CU) /**< \brief (UART) Transmit Next Counter Register */ +#define REG_UART_PTCR (*(WoReg*)0x400E0720U) /**< \brief (UART) Transfer Control Register */ +#define REG_UART_PTSR (*(RoReg*)0x400E0724U) /**< \brief (UART) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_UART_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/udphs.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/udphs.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,198 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_UDPHS_INSTANCE_ +#define _SAM3U_UDPHS_INSTANCE_ + +/* ========== Register definition for UDPHS peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_UDPHS_CTRL (0x400A4000U) /**< \brief (UDPHS) UDPHS Control Register */ +#define REG_UDPHS_FNUM (0x400A4004U) /**< \brief (UDPHS) UDPHS Frame Number Register */ +#define REG_UDPHS_IEN (0x400A4010U) /**< \brief (UDPHS) UDPHS Interrupt Enable Register */ +#define REG_UDPHS_INTSTA (0x400A4014U) /**< \brief (UDPHS) UDPHS Interrupt Status Register */ +#define REG_UDPHS_CLRINT (0x400A4018U) /**< \brief (UDPHS) UDPHS Clear Interrupt Register */ +#define REG_UDPHS_EPTRST (0x400A401CU) /**< \brief (UDPHS) UDPHS Endpoints Reset Register */ +#define REG_UDPHS_TST (0x400A40E0U) /**< \brief (UDPHS) UDPHS Test Register */ +#define REG_UDPHS_EPTCFG0 (0x400A4100U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 0) */ +#define REG_UDPHS_EPTCTLENB0 (0x400A4104U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 0) */ +#define REG_UDPHS_EPTCTLDIS0 (0x400A4108U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 0) */ +#define REG_UDPHS_EPTCTL0 (0x400A410CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 0) */ +#define REG_UDPHS_EPTSETSTA0 (0x400A4114U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 0) */ +#define REG_UDPHS_EPTCLRSTA0 (0x400A4118U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 0) */ +#define REG_UDPHS_EPTSTA0 (0x400A411CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 0) */ +#define REG_UDPHS_EPTCFG1 (0x400A4120U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 1) */ +#define REG_UDPHS_EPTCTLENB1 (0x400A4124U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 1) */ +#define REG_UDPHS_EPTCTLDIS1 (0x400A4128U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 1) */ +#define REG_UDPHS_EPTCTL1 (0x400A412CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 1) */ +#define REG_UDPHS_EPTSETSTA1 (0x400A4134U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 1) */ +#define REG_UDPHS_EPTCLRSTA1 (0x400A4138U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 1) */ +#define REG_UDPHS_EPTSTA1 (0x400A413CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 1) */ +#define REG_UDPHS_EPTCFG2 (0x400A4140U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 2) */ +#define REG_UDPHS_EPTCTLENB2 (0x400A4144U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 2) */ +#define REG_UDPHS_EPTCTLDIS2 (0x400A4148U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 2) */ +#define REG_UDPHS_EPTCTL2 (0x400A414CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 2) */ +#define REG_UDPHS_EPTSETSTA2 (0x400A4154U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 2) */ +#define REG_UDPHS_EPTCLRSTA2 (0x400A4158U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 2) */ +#define REG_UDPHS_EPTSTA2 (0x400A415CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 2) */ +#define REG_UDPHS_EPTCFG3 (0x400A4160U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 3) */ +#define REG_UDPHS_EPTCTLENB3 (0x400A4164U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 3) */ +#define REG_UDPHS_EPTCTLDIS3 (0x400A4168U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 3) */ +#define REG_UDPHS_EPTCTL3 (0x400A416CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 3) */ +#define REG_UDPHS_EPTSETSTA3 (0x400A4174U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 3) */ +#define REG_UDPHS_EPTCLRSTA3 (0x400A4178U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 3) */ +#define REG_UDPHS_EPTSTA3 (0x400A417CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 3) */ +#define REG_UDPHS_EPTCFG4 (0x400A4180U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 4) */ +#define REG_UDPHS_EPTCTLENB4 (0x400A4184U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 4) */ +#define REG_UDPHS_EPTCTLDIS4 (0x400A4188U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 4) */ +#define REG_UDPHS_EPTCTL4 (0x400A418CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 4) */ +#define REG_UDPHS_EPTSETSTA4 (0x400A4194U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 4) */ +#define REG_UDPHS_EPTCLRSTA4 (0x400A4198U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 4) */ +#define REG_UDPHS_EPTSTA4 (0x400A419CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 4) */ +#define REG_UDPHS_EPTCFG5 (0x400A41A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 5) */ +#define REG_UDPHS_EPTCTLENB5 (0x400A41A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 5) */ +#define REG_UDPHS_EPTCTLDIS5 (0x400A41A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 5) */ +#define REG_UDPHS_EPTCTL5 (0x400A41ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 5) */ +#define REG_UDPHS_EPTSETSTA5 (0x400A41B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 5) */ +#define REG_UDPHS_EPTCLRSTA5 (0x400A41B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 5) */ +#define REG_UDPHS_EPTSTA5 (0x400A41BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 5) */ +#define REG_UDPHS_EPTCFG6 (0x400A41C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 6) */ +#define REG_UDPHS_EPTCTLENB6 (0x400A41C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 6) */ +#define REG_UDPHS_EPTCTLDIS6 (0x400A41C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 6) */ +#define REG_UDPHS_EPTCTL6 (0x400A41CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 6) */ +#define REG_UDPHS_EPTSETSTA6 (0x400A41D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 6) */ +#define REG_UDPHS_EPTCLRSTA6 (0x400A41D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 6) */ +#define REG_UDPHS_EPTSTA6 (0x400A41DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 6) */ +#define REG_UDPHS_DMANXTDSC0 (0x400A4300U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 0) */ +#define REG_UDPHS_DMAADDRESS0 (0x400A4304U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 0) */ +#define REG_UDPHS_DMACONTROL0 (0x400A4308U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 0) */ +#define REG_UDPHS_DMASTATUS0 (0x400A430CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 0) */ +#define REG_UDPHS_DMANXTDSC1 (0x400A4310U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 1) */ +#define REG_UDPHS_DMAADDRESS1 (0x400A4314U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 1) */ +#define REG_UDPHS_DMACONTROL1 (0x400A4318U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 1) */ +#define REG_UDPHS_DMASTATUS1 (0x400A431CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 1) */ +#define REG_UDPHS_DMANXTDSC2 (0x400A4320U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 2) */ +#define REG_UDPHS_DMAADDRESS2 (0x400A4324U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 2) */ +#define REG_UDPHS_DMACONTROL2 (0x400A4328U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 2) */ +#define REG_UDPHS_DMASTATUS2 (0x400A432CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 2) */ +#define REG_UDPHS_DMANXTDSC3 (0x400A4330U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 3) */ +#define REG_UDPHS_DMAADDRESS3 (0x400A4334U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 3) */ +#define REG_UDPHS_DMACONTROL3 (0x400A4338U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 3) */ +#define REG_UDPHS_DMASTATUS3 (0x400A433CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 3) */ +#define REG_UDPHS_DMANXTDSC4 (0x400A4340U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 4) */ +#define REG_UDPHS_DMAADDRESS4 (0x400A4344U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 4) */ +#define REG_UDPHS_DMACONTROL4 (0x400A4348U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 4) */ +#define REG_UDPHS_DMASTATUS4 (0x400A434CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 4) */ +#define REG_UDPHS_DMANXTDSC5 (0x400A4350U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 5) */ +#define REG_UDPHS_DMAADDRESS5 (0x400A4354U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 5) */ +#define REG_UDPHS_DMACONTROL5 (0x400A4358U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 5) */ +#define REG_UDPHS_DMASTATUS5 (0x400A435CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 5) */ +#else +#define REG_UDPHS_CTRL (*(RwReg*)0x400A4000U) /**< \brief (UDPHS) UDPHS Control Register */ +#define REG_UDPHS_FNUM (*(RoReg*)0x400A4004U) /**< \brief (UDPHS) UDPHS Frame Number Register */ +#define REG_UDPHS_IEN (*(RwReg*)0x400A4010U) /**< \brief (UDPHS) UDPHS Interrupt Enable Register */ +#define REG_UDPHS_INTSTA (*(RoReg*)0x400A4014U) /**< \brief (UDPHS) UDPHS Interrupt Status Register */ +#define REG_UDPHS_CLRINT (*(WoReg*)0x400A4018U) /**< \brief (UDPHS) UDPHS Clear Interrupt Register */ +#define REG_UDPHS_EPTRST (*(WoReg*)0x400A401CU) /**< \brief (UDPHS) UDPHS Endpoints Reset Register */ +#define REG_UDPHS_TST (*(RwReg*)0x400A40E0U) /**< \brief (UDPHS) UDPHS Test Register */ +#define REG_UDPHS_EPTCFG0 (*(RwReg*)0x400A4100U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 0) */ +#define REG_UDPHS_EPTCTLENB0 (*(WoReg*)0x400A4104U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 0) */ +#define REG_UDPHS_EPTCTLDIS0 (*(WoReg*)0x400A4108U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 0) */ +#define REG_UDPHS_EPTCTL0 (*(RoReg*)0x400A410CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 0) */ +#define REG_UDPHS_EPTSETSTA0 (*(WoReg*)0x400A4114U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 0) */ +#define REG_UDPHS_EPTCLRSTA0 (*(WoReg*)0x400A4118U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 0) */ +#define REG_UDPHS_EPTSTA0 (*(RoReg*)0x400A411CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 0) */ +#define REG_UDPHS_EPTCFG1 (*(RwReg*)0x400A4120U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 1) */ +#define REG_UDPHS_EPTCTLENB1 (*(WoReg*)0x400A4124U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 1) */ +#define REG_UDPHS_EPTCTLDIS1 (*(WoReg*)0x400A4128U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 1) */ +#define REG_UDPHS_EPTCTL1 (*(RoReg*)0x400A412CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 1) */ +#define REG_UDPHS_EPTSETSTA1 (*(WoReg*)0x400A4134U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 1) */ +#define REG_UDPHS_EPTCLRSTA1 (*(WoReg*)0x400A4138U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 1) */ +#define REG_UDPHS_EPTSTA1 (*(RoReg*)0x400A413CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 1) */ +#define REG_UDPHS_EPTCFG2 (*(RwReg*)0x400A4140U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 2) */ +#define REG_UDPHS_EPTCTLENB2 (*(WoReg*)0x400A4144U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 2) */ +#define REG_UDPHS_EPTCTLDIS2 (*(WoReg*)0x400A4148U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 2) */ +#define REG_UDPHS_EPTCTL2 (*(RoReg*)0x400A414CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 2) */ +#define REG_UDPHS_EPTSETSTA2 (*(WoReg*)0x400A4154U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 2) */ +#define REG_UDPHS_EPTCLRSTA2 (*(WoReg*)0x400A4158U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 2) */ +#define REG_UDPHS_EPTSTA2 (*(RoReg*)0x400A415CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 2) */ +#define REG_UDPHS_EPTCFG3 (*(RwReg*)0x400A4160U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 3) */ +#define REG_UDPHS_EPTCTLENB3 (*(WoReg*)0x400A4164U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 3) */ +#define REG_UDPHS_EPTCTLDIS3 (*(WoReg*)0x400A4168U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 3) */ +#define REG_UDPHS_EPTCTL3 (*(RoReg*)0x400A416CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 3) */ +#define REG_UDPHS_EPTSETSTA3 (*(WoReg*)0x400A4174U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 3) */ +#define REG_UDPHS_EPTCLRSTA3 (*(WoReg*)0x400A4178U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 3) */ +#define REG_UDPHS_EPTSTA3 (*(RoReg*)0x400A417CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 3) */ +#define REG_UDPHS_EPTCFG4 (*(RwReg*)0x400A4180U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 4) */ +#define REG_UDPHS_EPTCTLENB4 (*(WoReg*)0x400A4184U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 4) */ +#define REG_UDPHS_EPTCTLDIS4 (*(WoReg*)0x400A4188U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 4) */ +#define REG_UDPHS_EPTCTL4 (*(RoReg*)0x400A418CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 4) */ +#define REG_UDPHS_EPTSETSTA4 (*(WoReg*)0x400A4194U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 4) */ +#define REG_UDPHS_EPTCLRSTA4 (*(WoReg*)0x400A4198U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 4) */ +#define REG_UDPHS_EPTSTA4 (*(RoReg*)0x400A419CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 4) */ +#define REG_UDPHS_EPTCFG5 (*(RwReg*)0x400A41A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 5) */ +#define REG_UDPHS_EPTCTLENB5 (*(WoReg*)0x400A41A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 5) */ +#define REG_UDPHS_EPTCTLDIS5 (*(WoReg*)0x400A41A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 5) */ +#define REG_UDPHS_EPTCTL5 (*(RoReg*)0x400A41ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 5) */ +#define REG_UDPHS_EPTSETSTA5 (*(WoReg*)0x400A41B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 5) */ +#define REG_UDPHS_EPTCLRSTA5 (*(WoReg*)0x400A41B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 5) */ +#define REG_UDPHS_EPTSTA5 (*(RoReg*)0x400A41BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 5) */ +#define REG_UDPHS_EPTCFG6 (*(RwReg*)0x400A41C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 6) */ +#define REG_UDPHS_EPTCTLENB6 (*(WoReg*)0x400A41C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 6) */ +#define REG_UDPHS_EPTCTLDIS6 (*(WoReg*)0x400A41C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 6) */ +#define REG_UDPHS_EPTCTL6 (*(RoReg*)0x400A41CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 6) */ +#define REG_UDPHS_EPTSETSTA6 (*(WoReg*)0x400A41D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 6) */ +#define REG_UDPHS_EPTCLRSTA6 (*(WoReg*)0x400A41D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 6) */ +#define REG_UDPHS_EPTSTA6 (*(RoReg*)0x400A41DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 6) */ +#define REG_UDPHS_DMANXTDSC0 (*(RwReg*)0x400A4300U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 0) */ +#define REG_UDPHS_DMAADDRESS0 (*(RwReg*)0x400A4304U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 0) */ +#define REG_UDPHS_DMACONTROL0 (*(RwReg*)0x400A4308U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 0) */ +#define REG_UDPHS_DMASTATUS0 (*(RwReg*)0x400A430CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 0) */ +#define REG_UDPHS_DMANXTDSC1 (*(RwReg*)0x400A4310U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 1) */ +#define REG_UDPHS_DMAADDRESS1 (*(RwReg*)0x400A4314U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 1) */ +#define REG_UDPHS_DMACONTROL1 (*(RwReg*)0x400A4318U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 1) */ +#define REG_UDPHS_DMASTATUS1 (*(RwReg*)0x400A431CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 1) */ +#define REG_UDPHS_DMANXTDSC2 (*(RwReg*)0x400A4320U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 2) */ +#define REG_UDPHS_DMAADDRESS2 (*(RwReg*)0x400A4324U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 2) */ +#define REG_UDPHS_DMACONTROL2 (*(RwReg*)0x400A4328U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 2) */ +#define REG_UDPHS_DMASTATUS2 (*(RwReg*)0x400A432CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 2) */ +#define REG_UDPHS_DMANXTDSC3 (*(RwReg*)0x400A4330U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 3) */ +#define REG_UDPHS_DMAADDRESS3 (*(RwReg*)0x400A4334U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 3) */ +#define REG_UDPHS_DMACONTROL3 (*(RwReg*)0x400A4338U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 3) */ +#define REG_UDPHS_DMASTATUS3 (*(RwReg*)0x400A433CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 3) */ +#define REG_UDPHS_DMANXTDSC4 (*(RwReg*)0x400A4340U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 4) */ +#define REG_UDPHS_DMAADDRESS4 (*(RwReg*)0x400A4344U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 4) */ +#define REG_UDPHS_DMACONTROL4 (*(RwReg*)0x400A4348U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 4) */ +#define REG_UDPHS_DMASTATUS4 (*(RwReg*)0x400A434CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 4) */ +#define REG_UDPHS_DMANXTDSC5 (*(RwReg*)0x400A4350U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 5) */ +#define REG_UDPHS_DMAADDRESS5 (*(RwReg*)0x400A4354U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 5) */ +#define REG_UDPHS_DMACONTROL5 (*(RwReg*)0x400A4358U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 5) */ +#define REG_UDPHS_DMASTATUS5 (*(RwReg*)0x400A435CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 5) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_UDPHS_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/usart0.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/usart0.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_USART0_INSTANCE_ +#define _SAM3U_USART0_INSTANCE_ + +/* ========== Register definition for USART0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART0_CR (0x40090000U) /**< \brief (USART0) Control Register */ +#define REG_USART0_MR (0x40090004U) /**< \brief (USART0) Mode Register */ +#define REG_USART0_IER (0x40090008U) /**< \brief (USART0) Interrupt Enable Register */ +#define REG_USART0_IDR (0x4009000CU) /**< \brief (USART0) Interrupt Disable Register */ +#define REG_USART0_IMR (0x40090010U) /**< \brief (USART0) Interrupt Mask Register */ +#define REG_USART0_CSR (0x40090014U) /**< \brief (USART0) Channel Status Register */ +#define REG_USART0_RHR (0x40090018U) /**< \brief (USART0) Receiver Holding Register */ +#define REG_USART0_THR (0x4009001CU) /**< \brief (USART0) Transmitter Holding Register */ +#define REG_USART0_BRGR (0x40090020U) /**< \brief (USART0) Baud Rate Generator Register */ +#define REG_USART0_RTOR (0x40090024U) /**< \brief (USART0) Receiver Time-out Register */ +#define REG_USART0_TTGR (0x40090028U) /**< \brief (USART0) Transmitter Timeguard Register */ +#define REG_USART0_FIDI (0x40090040U) /**< \brief (USART0) FI DI Ratio Register */ +#define REG_USART0_NER (0x40090044U) /**< \brief (USART0) Number of Errors Register */ +#define REG_USART0_IF (0x4009004CU) /**< \brief (USART0) IrDA Filter Register */ +#define REG_USART0_MAN (0x40090050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ +#define REG_USART0_WPMR (0x400900E4U) /**< \brief (USART0) Write Protect Mode Register */ +#define REG_USART0_WPSR (0x400900E8U) /**< \brief (USART0) Write Protect Status Register */ +#define REG_USART0_RPR (0x40090100U) /**< \brief (USART0) Receive Pointer Register */ +#define REG_USART0_RCR (0x40090104U) /**< \brief (USART0) Receive Counter Register */ +#define REG_USART0_TPR (0x40090108U) /**< \brief (USART0) Transmit Pointer Register */ +#define REG_USART0_TCR (0x4009010CU) /**< \brief (USART0) Transmit Counter Register */ +#define REG_USART0_RNPR (0x40090110U) /**< \brief (USART0) Receive Next Pointer Register */ +#define REG_USART0_RNCR (0x40090114U) /**< \brief (USART0) Receive Next Counter Register */ +#define REG_USART0_TNPR (0x40090118U) /**< \brief (USART0) Transmit Next Pointer Register */ +#define REG_USART0_TNCR (0x4009011CU) /**< \brief (USART0) Transmit Next Counter Register */ +#define REG_USART0_PTCR (0x40090120U) /**< \brief (USART0) Transfer Control Register */ +#define REG_USART0_PTSR (0x40090124U) /**< \brief (USART0) Transfer Status Register */ +#else +#define REG_USART0_CR (*(WoReg*)0x40090000U) /**< \brief (USART0) Control Register */ +#define REG_USART0_MR (*(RwReg*)0x40090004U) /**< \brief (USART0) Mode Register */ +#define REG_USART0_IER (*(WoReg*)0x40090008U) /**< \brief (USART0) Interrupt Enable Register */ +#define REG_USART0_IDR (*(WoReg*)0x4009000CU) /**< \brief (USART0) Interrupt Disable Register */ +#define REG_USART0_IMR (*(RoReg*)0x40090010U) /**< \brief (USART0) Interrupt Mask Register */ +#define REG_USART0_CSR (*(RoReg*)0x40090014U) /**< \brief (USART0) Channel Status Register */ +#define REG_USART0_RHR (*(RoReg*)0x40090018U) /**< \brief (USART0) Receiver Holding Register */ +#define REG_USART0_THR (*(WoReg*)0x4009001CU) /**< \brief (USART0) Transmitter Holding Register */ +#define REG_USART0_BRGR (*(RwReg*)0x40090020U) /**< \brief (USART0) Baud Rate Generator Register */ +#define REG_USART0_RTOR (*(RwReg*)0x40090024U) /**< \brief (USART0) Receiver Time-out Register */ +#define REG_USART0_TTGR (*(RwReg*)0x40090028U) /**< \brief (USART0) Transmitter Timeguard Register */ +#define REG_USART0_FIDI (*(RwReg*)0x40090040U) /**< \brief (USART0) FI DI Ratio Register */ +#define REG_USART0_NER (*(RoReg*)0x40090044U) /**< \brief (USART0) Number of Errors Register */ +#define REG_USART0_IF (*(RwReg*)0x4009004CU) /**< \brief (USART0) IrDA Filter Register */ +#define REG_USART0_MAN (*(RwReg*)0x40090050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ +#define REG_USART0_WPMR (*(RwReg*)0x400900E4U) /**< \brief (USART0) Write Protect Mode Register */ +#define REG_USART0_WPSR (*(RoReg*)0x400900E8U) /**< \brief (USART0) Write Protect Status Register */ +#define REG_USART0_RPR (*(RwReg*)0x40090100U) /**< \brief (USART0) Receive Pointer Register */ +#define REG_USART0_RCR (*(RwReg*)0x40090104U) /**< \brief (USART0) Receive Counter Register */ +#define REG_USART0_TPR (*(RwReg*)0x40090108U) /**< \brief (USART0) Transmit Pointer Register */ +#define REG_USART0_TCR (*(RwReg*)0x4009010CU) /**< \brief (USART0) Transmit Counter Register */ +#define REG_USART0_RNPR (*(RwReg*)0x40090110U) /**< \brief (USART0) Receive Next Pointer Register */ +#define REG_USART0_RNCR (*(RwReg*)0x40090114U) /**< \brief (USART0) Receive Next Counter Register */ +#define REG_USART0_TNPR (*(RwReg*)0x40090118U) /**< \brief (USART0) Transmit Next Pointer Register */ +#define REG_USART0_TNCR (*(RwReg*)0x4009011CU) /**< \brief (USART0) Transmit Next Counter Register */ +#define REG_USART0_PTCR (*(WoReg*)0x40090120U) /**< \brief (USART0) Transfer Control Register */ +#define REG_USART0_PTSR (*(RoReg*)0x40090124U) /**< \brief (USART0) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_USART0_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/usart1.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/usart1.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_USART1_INSTANCE_ +#define _SAM3U_USART1_INSTANCE_ + +/* ========== Register definition for USART1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART1_CR (0x40094000U) /**< \brief (USART1) Control Register */ +#define REG_USART1_MR (0x40094004U) /**< \brief (USART1) Mode Register */ +#define REG_USART1_IER (0x40094008U) /**< \brief (USART1) Interrupt Enable Register */ +#define REG_USART1_IDR (0x4009400CU) /**< \brief (USART1) Interrupt Disable Register */ +#define REG_USART1_IMR (0x40094010U) /**< \brief (USART1) Interrupt Mask Register */ +#define REG_USART1_CSR (0x40094014U) /**< \brief (USART1) Channel Status Register */ +#define REG_USART1_RHR (0x40094018U) /**< \brief (USART1) Receiver Holding Register */ +#define REG_USART1_THR (0x4009401CU) /**< \brief (USART1) Transmitter Holding Register */ +#define REG_USART1_BRGR (0x40094020U) /**< \brief (USART1) Baud Rate Generator Register */ +#define REG_USART1_RTOR (0x40094024U) /**< \brief (USART1) Receiver Time-out Register */ +#define REG_USART1_TTGR (0x40094028U) /**< \brief (USART1) Transmitter Timeguard Register */ +#define REG_USART1_FIDI (0x40094040U) /**< \brief (USART1) FI DI Ratio Register */ +#define REG_USART1_NER (0x40094044U) /**< \brief (USART1) Number of Errors Register */ +#define REG_USART1_IF (0x4009404CU) /**< \brief (USART1) IrDA Filter Register */ +#define REG_USART1_MAN (0x40094050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ +#define REG_USART1_WPMR (0x400940E4U) /**< \brief (USART1) Write Protect Mode Register */ +#define REG_USART1_WPSR (0x400940E8U) /**< \brief (USART1) Write Protect Status Register */ +#define REG_USART1_RPR (0x40094100U) /**< \brief (USART1) Receive Pointer Register */ +#define REG_USART1_RCR (0x40094104U) /**< \brief (USART1) Receive Counter Register */ +#define REG_USART1_TPR (0x40094108U) /**< \brief (USART1) Transmit Pointer Register */ +#define REG_USART1_TCR (0x4009410CU) /**< \brief (USART1) Transmit Counter Register */ +#define REG_USART1_RNPR (0x40094110U) /**< \brief (USART1) Receive Next Pointer Register */ +#define REG_USART1_RNCR (0x40094114U) /**< \brief (USART1) Receive Next Counter Register */ +#define REG_USART1_TNPR (0x40094118U) /**< \brief (USART1) Transmit Next Pointer Register */ +#define REG_USART1_TNCR (0x4009411CU) /**< \brief (USART1) Transmit Next Counter Register */ +#define REG_USART1_PTCR (0x40094120U) /**< \brief (USART1) Transfer Control Register */ +#define REG_USART1_PTSR (0x40094124U) /**< \brief (USART1) Transfer Status Register */ +#else +#define REG_USART1_CR (*(WoReg*)0x40094000U) /**< \brief (USART1) Control Register */ +#define REG_USART1_MR (*(RwReg*)0x40094004U) /**< \brief (USART1) Mode Register */ +#define REG_USART1_IER (*(WoReg*)0x40094008U) /**< \brief (USART1) Interrupt Enable Register */ +#define REG_USART1_IDR (*(WoReg*)0x4009400CU) /**< \brief (USART1) Interrupt Disable Register */ +#define REG_USART1_IMR (*(RoReg*)0x40094010U) /**< \brief (USART1) Interrupt Mask Register */ +#define REG_USART1_CSR (*(RoReg*)0x40094014U) /**< \brief (USART1) Channel Status Register */ +#define REG_USART1_RHR (*(RoReg*)0x40094018U) /**< \brief (USART1) Receiver Holding Register */ +#define REG_USART1_THR (*(WoReg*)0x4009401CU) /**< \brief (USART1) Transmitter Holding Register */ +#define REG_USART1_BRGR (*(RwReg*)0x40094020U) /**< \brief (USART1) Baud Rate Generator Register */ +#define REG_USART1_RTOR (*(RwReg*)0x40094024U) /**< \brief (USART1) Receiver Time-out Register */ +#define REG_USART1_TTGR (*(RwReg*)0x40094028U) /**< \brief (USART1) Transmitter Timeguard Register */ +#define REG_USART1_FIDI (*(RwReg*)0x40094040U) /**< \brief (USART1) FI DI Ratio Register */ +#define REG_USART1_NER (*(RoReg*)0x40094044U) /**< \brief (USART1) Number of Errors Register */ +#define REG_USART1_IF (*(RwReg*)0x4009404CU) /**< \brief (USART1) IrDA Filter Register */ +#define REG_USART1_MAN (*(RwReg*)0x40094050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ +#define REG_USART1_WPMR (*(RwReg*)0x400940E4U) /**< \brief (USART1) Write Protect Mode Register */ +#define REG_USART1_WPSR (*(RoReg*)0x400940E8U) /**< \brief (USART1) Write Protect Status Register */ +#define REG_USART1_RPR (*(RwReg*)0x40094100U) /**< \brief (USART1) Receive Pointer Register */ +#define REG_USART1_RCR (*(RwReg*)0x40094104U) /**< \brief (USART1) Receive Counter Register */ +#define REG_USART1_TPR (*(RwReg*)0x40094108U) /**< \brief (USART1) Transmit Pointer Register */ +#define REG_USART1_TCR (*(RwReg*)0x4009410CU) /**< \brief (USART1) Transmit Counter Register */ +#define REG_USART1_RNPR (*(RwReg*)0x40094110U) /**< \brief (USART1) Receive Next Pointer Register */ +#define REG_USART1_RNCR (*(RwReg*)0x40094114U) /**< \brief (USART1) Receive Next Counter Register */ +#define REG_USART1_TNPR (*(RwReg*)0x40094118U) /**< \brief (USART1) Transmit Next Pointer Register */ +#define REG_USART1_TNCR (*(RwReg*)0x4009411CU) /**< \brief (USART1) Transmit Next Counter Register */ +#define REG_USART1_PTCR (*(WoReg*)0x40094120U) /**< \brief (USART1) Transfer Control Register */ +#define REG_USART1_PTSR (*(RoReg*)0x40094124U) /**< \brief (USART1) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_USART1_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/usart2.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/usart2.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_USART2_INSTANCE_ +#define _SAM3U_USART2_INSTANCE_ + +/* ========== Register definition for USART2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART2_CR (0x40098000U) /**< \brief (USART2) Control Register */ +#define REG_USART2_MR (0x40098004U) /**< \brief (USART2) Mode Register */ +#define REG_USART2_IER (0x40098008U) /**< \brief (USART2) Interrupt Enable Register */ +#define REG_USART2_IDR (0x4009800CU) /**< \brief (USART2) Interrupt Disable Register */ +#define REG_USART2_IMR (0x40098010U) /**< \brief (USART2) Interrupt Mask Register */ +#define REG_USART2_CSR (0x40098014U) /**< \brief (USART2) Channel Status Register */ +#define REG_USART2_RHR (0x40098018U) /**< \brief (USART2) Receiver Holding Register */ +#define REG_USART2_THR (0x4009801CU) /**< \brief (USART2) Transmitter Holding Register */ +#define REG_USART2_BRGR (0x40098020U) /**< \brief (USART2) Baud Rate Generator Register */ +#define REG_USART2_RTOR (0x40098024U) /**< \brief (USART2) Receiver Time-out Register */ +#define REG_USART2_TTGR (0x40098028U) /**< \brief (USART2) Transmitter Timeguard Register */ +#define REG_USART2_FIDI (0x40098040U) /**< \brief (USART2) FI DI Ratio Register */ +#define REG_USART2_NER (0x40098044U) /**< \brief (USART2) Number of Errors Register */ +#define REG_USART2_IF (0x4009804CU) /**< \brief (USART2) IrDA Filter Register */ +#define REG_USART2_MAN (0x40098050U) /**< \brief (USART2) Manchester Encoder Decoder Register */ +#define REG_USART2_WPMR (0x400980E4U) /**< \brief (USART2) Write Protect Mode Register */ +#define REG_USART2_WPSR (0x400980E8U) /**< \brief (USART2) Write Protect Status Register */ +#define REG_USART2_RPR (0x40098100U) /**< \brief (USART2) Receive Pointer Register */ +#define REG_USART2_RCR (0x40098104U) /**< \brief (USART2) Receive Counter Register */ +#define REG_USART2_TPR (0x40098108U) /**< \brief (USART2) Transmit Pointer Register */ +#define REG_USART2_TCR (0x4009810CU) /**< \brief (USART2) Transmit Counter Register */ +#define REG_USART2_RNPR (0x40098110U) /**< \brief (USART2) Receive Next Pointer Register */ +#define REG_USART2_RNCR (0x40098114U) /**< \brief (USART2) Receive Next Counter Register */ +#define REG_USART2_TNPR (0x40098118U) /**< \brief (USART2) Transmit Next Pointer Register */ +#define REG_USART2_TNCR (0x4009811CU) /**< \brief (USART2) Transmit Next Counter Register */ +#define REG_USART2_PTCR (0x40098120U) /**< \brief (USART2) Transfer Control Register */ +#define REG_USART2_PTSR (0x40098124U) /**< \brief (USART2) Transfer Status Register */ +#else +#define REG_USART2_CR (*(WoReg*)0x40098000U) /**< \brief (USART2) Control Register */ +#define REG_USART2_MR (*(RwReg*)0x40098004U) /**< \brief (USART2) Mode Register */ +#define REG_USART2_IER (*(WoReg*)0x40098008U) /**< \brief (USART2) Interrupt Enable Register */ +#define REG_USART2_IDR (*(WoReg*)0x4009800CU) /**< \brief (USART2) Interrupt Disable Register */ +#define REG_USART2_IMR (*(RoReg*)0x40098010U) /**< \brief (USART2) Interrupt Mask Register */ +#define REG_USART2_CSR (*(RoReg*)0x40098014U) /**< \brief (USART2) Channel Status Register */ +#define REG_USART2_RHR (*(RoReg*)0x40098018U) /**< \brief (USART2) Receiver Holding Register */ +#define REG_USART2_THR (*(WoReg*)0x4009801CU) /**< \brief (USART2) Transmitter Holding Register */ +#define REG_USART2_BRGR (*(RwReg*)0x40098020U) /**< \brief (USART2) Baud Rate Generator Register */ +#define REG_USART2_RTOR (*(RwReg*)0x40098024U) /**< \brief (USART2) Receiver Time-out Register */ +#define REG_USART2_TTGR (*(RwReg*)0x40098028U) /**< \brief (USART2) Transmitter Timeguard Register */ +#define REG_USART2_FIDI (*(RwReg*)0x40098040U) /**< \brief (USART2) FI DI Ratio Register */ +#define REG_USART2_NER (*(RoReg*)0x40098044U) /**< \brief (USART2) Number of Errors Register */ +#define REG_USART2_IF (*(RwReg*)0x4009804CU) /**< \brief (USART2) IrDA Filter Register */ +#define REG_USART2_MAN (*(RwReg*)0x40098050U) /**< \brief (USART2) Manchester Encoder Decoder Register */ +#define REG_USART2_WPMR (*(RwReg*)0x400980E4U) /**< \brief (USART2) Write Protect Mode Register */ +#define REG_USART2_WPSR (*(RoReg*)0x400980E8U) /**< \brief (USART2) Write Protect Status Register */ +#define REG_USART2_RPR (*(RwReg*)0x40098100U) /**< \brief (USART2) Receive Pointer Register */ +#define REG_USART2_RCR (*(RwReg*)0x40098104U) /**< \brief (USART2) Receive Counter Register */ +#define REG_USART2_TPR (*(RwReg*)0x40098108U) /**< \brief (USART2) Transmit Pointer Register */ +#define REG_USART2_TCR (*(RwReg*)0x4009810CU) /**< \brief (USART2) Transmit Counter Register */ +#define REG_USART2_RNPR (*(RwReg*)0x40098110U) /**< \brief (USART2) Receive Next Pointer Register */ +#define REG_USART2_RNCR (*(RwReg*)0x40098114U) /**< \brief (USART2) Receive Next Counter Register */ +#define REG_USART2_TNPR (*(RwReg*)0x40098118U) /**< \brief (USART2) Transmit Next Pointer Register */ +#define REG_USART2_TNCR (*(RwReg*)0x4009811CU) /**< \brief (USART2) Transmit Next Counter Register */ +#define REG_USART2_PTCR (*(WoReg*)0x40098120U) /**< \brief (USART2) Transfer Control Register */ +#define REG_USART2_PTSR (*(RoReg*)0x40098124U) /**< \brief (USART2) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_USART2_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/usart3.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/usart3.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_USART3_INSTANCE_ +#define _SAM3U_USART3_INSTANCE_ + +/* ========== Register definition for USART3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART3_CR (0x4009C000U) /**< \brief (USART3) Control Register */ +#define REG_USART3_MR (0x4009C004U) /**< \brief (USART3) Mode Register */ +#define REG_USART3_IER (0x4009C008U) /**< \brief (USART3) Interrupt Enable Register */ +#define REG_USART3_IDR (0x4009C00CU) /**< \brief (USART3) Interrupt Disable Register */ +#define REG_USART3_IMR (0x4009C010U) /**< \brief (USART3) Interrupt Mask Register */ +#define REG_USART3_CSR (0x4009C014U) /**< \brief (USART3) Channel Status Register */ +#define REG_USART3_RHR (0x4009C018U) /**< \brief (USART3) Receiver Holding Register */ +#define REG_USART3_THR (0x4009C01CU) /**< \brief (USART3) Transmitter Holding Register */ +#define REG_USART3_BRGR (0x4009C020U) /**< \brief (USART3) Baud Rate Generator Register */ +#define REG_USART3_RTOR (0x4009C024U) /**< \brief (USART3) Receiver Time-out Register */ +#define REG_USART3_TTGR (0x4009C028U) /**< \brief (USART3) Transmitter Timeguard Register */ +#define REG_USART3_FIDI (0x4009C040U) /**< \brief (USART3) FI DI Ratio Register */ +#define REG_USART3_NER (0x4009C044U) /**< \brief (USART3) Number of Errors Register */ +#define REG_USART3_IF (0x4009C04CU) /**< \brief (USART3) IrDA Filter Register */ +#define REG_USART3_MAN (0x4009C050U) /**< \brief (USART3) Manchester Encoder Decoder Register */ +#define REG_USART3_WPMR (0x4009C0E4U) /**< \brief (USART3) Write Protect Mode Register */ +#define REG_USART3_WPSR (0x4009C0E8U) /**< \brief (USART3) Write Protect Status Register */ +#define REG_USART3_RPR (0x4009C100U) /**< \brief (USART3) Receive Pointer Register */ +#define REG_USART3_RCR (0x4009C104U) /**< \brief (USART3) Receive Counter Register */ +#define REG_USART3_TPR (0x4009C108U) /**< \brief (USART3) Transmit Pointer Register */ +#define REG_USART3_TCR (0x4009C10CU) /**< \brief (USART3) Transmit Counter Register */ +#define REG_USART3_RNPR (0x4009C110U) /**< \brief (USART3) Receive Next Pointer Register */ +#define REG_USART3_RNCR (0x4009C114U) /**< \brief (USART3) Receive Next Counter Register */ +#define REG_USART3_TNPR (0x4009C118U) /**< \brief (USART3) Transmit Next Pointer Register */ +#define REG_USART3_TNCR (0x4009C11CU) /**< \brief (USART3) Transmit Next Counter Register */ +#define REG_USART3_PTCR (0x4009C120U) /**< \brief (USART3) Transfer Control Register */ +#define REG_USART3_PTSR (0x4009C124U) /**< \brief (USART3) Transfer Status Register */ +#else +#define REG_USART3_CR (*(WoReg*)0x4009C000U) /**< \brief (USART3) Control Register */ +#define REG_USART3_MR (*(RwReg*)0x4009C004U) /**< \brief (USART3) Mode Register */ +#define REG_USART3_IER (*(WoReg*)0x4009C008U) /**< \brief (USART3) Interrupt Enable Register */ +#define REG_USART3_IDR (*(WoReg*)0x4009C00CU) /**< \brief (USART3) Interrupt Disable Register */ +#define REG_USART3_IMR (*(RoReg*)0x4009C010U) /**< \brief (USART3) Interrupt Mask Register */ +#define REG_USART3_CSR (*(RoReg*)0x4009C014U) /**< \brief (USART3) Channel Status Register */ +#define REG_USART3_RHR (*(RoReg*)0x4009C018U) /**< \brief (USART3) Receiver Holding Register */ +#define REG_USART3_THR (*(WoReg*)0x4009C01CU) /**< \brief (USART3) Transmitter Holding Register */ +#define REG_USART3_BRGR (*(RwReg*)0x4009C020U) /**< \brief (USART3) Baud Rate Generator Register */ +#define REG_USART3_RTOR (*(RwReg*)0x4009C024U) /**< \brief (USART3) Receiver Time-out Register */ +#define REG_USART3_TTGR (*(RwReg*)0x4009C028U) /**< \brief (USART3) Transmitter Timeguard Register */ +#define REG_USART3_FIDI (*(RwReg*)0x4009C040U) /**< \brief (USART3) FI DI Ratio Register */ +#define REG_USART3_NER (*(RoReg*)0x4009C044U) /**< \brief (USART3) Number of Errors Register */ +#define REG_USART3_IF (*(RwReg*)0x4009C04CU) /**< \brief (USART3) IrDA Filter Register */ +#define REG_USART3_MAN (*(RwReg*)0x4009C050U) /**< \brief (USART3) Manchester Encoder Decoder Register */ +#define REG_USART3_WPMR (*(RwReg*)0x4009C0E4U) /**< \brief (USART3) Write Protect Mode Register */ +#define REG_USART3_WPSR (*(RoReg*)0x4009C0E8U) /**< \brief (USART3) Write Protect Status Register */ +#define REG_USART3_RPR (*(RwReg*)0x4009C100U) /**< \brief (USART3) Receive Pointer Register */ +#define REG_USART3_RCR (*(RwReg*)0x4009C104U) /**< \brief (USART3) Receive Counter Register */ +#define REG_USART3_TPR (*(RwReg*)0x4009C108U) /**< \brief (USART3) Transmit Pointer Register */ +#define REG_USART3_TCR (*(RwReg*)0x4009C10CU) /**< \brief (USART3) Transmit Counter Register */ +#define REG_USART3_RNPR (*(RwReg*)0x4009C110U) /**< \brief (USART3) Receive Next Pointer Register */ +#define REG_USART3_RNCR (*(RwReg*)0x4009C114U) /**< \brief (USART3) Receive Next Counter Register */ +#define REG_USART3_TNPR (*(RwReg*)0x4009C118U) /**< \brief (USART3) Transmit Next Pointer Register */ +#define REG_USART3_TNCR (*(RwReg*)0x4009C11CU) /**< \brief (USART3) Transmit Next Counter Register */ +#define REG_USART3_PTCR (*(WoReg*)0x4009C120U) /**< \brief (USART3) Transfer Control Register */ +#define REG_USART3_PTSR (*(RoReg*)0x4009C124U) /**< \brief (USART3) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_USART3_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/instance/wdt.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/instance/wdt.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,44 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U_WDT_INSTANCE_ +#define _SAM3U_WDT_INSTANCE_ + +/* ========== Register definition for WDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_WDT_CR (0x400E1250U) /**< \brief (WDT) Control Register */ +#define REG_WDT_MR (0x400E1254U) /**< \brief (WDT) Mode Register */ +#define REG_WDT_SR (0x400E1258U) /**< \brief (WDT) Status Register */ +#else +#define REG_WDT_CR (*(WoReg*)0x400E1250U) /**< \brief (WDT) Control Register */ +#define REG_WDT_MR (*(RwReg*)0x400E1254U) /**< \brief (WDT) Mode Register */ +#define REG_WDT_SR (*(RoReg*)0x400E1258U) /**< \brief (WDT) Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3U_WDT_INSTANCE_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/pio/sam3u2c.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/pio/sam3u2c.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,356 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3U2C_PIO_ +#define _SAM3U2C_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ +#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */ +#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */ +#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */ +#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */ +#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */ +#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */ +#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */ +#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */ +#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */ +#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PB5X1_AD0 (1u << 5) /**< \brief Adc signal: AD0 */ +#define PIO_PB6X1_AD1 (1u << 6) /**< \brief Adc signal: AD1 */ +#define PIO_PB7X1_AD2 (1u << 7) /**< \brief Adc signal: AD2 */ +#define PIO_PB8X1_AD3 (1u << 8) /**< \brief Adc signal: AD3 */ +#define PIO_PC28X1_AD4 (1u << 28) /**< \brief Adc signal: AD4 */ +#define PIO_PC29X1_AD5 (1u << 29) /**< \brief Adc signal: AD5 */ +#define PIO_PC30X1_AD6 (1u << 30) /**< \brief Adc signal: AD6 */ +#define PIO_PC31X1_AD7 (1u << 31) /**< \brief Adc signal: AD7 */ +#define PIO_PA17B_ADTRG (1u << 17) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for ADC12B peripheral ========== */ +#define PIO_PA22X1_AD12B0 (1u << 22) /**< \brief Adc12b signal: AD12B0 */ +#define PIO_PA30X1_AD12B1 (1u << 30) /**< \brief Adc12b signal: AD12B1 */ +#define PIO_PB3X1_AD12B2 (1u << 3) /**< \brief Adc12b signal: AD12B2 */ +#define PIO_PB4X1_AD12B3 (1u << 4) /**< \brief Adc12b signal: AD12B3 */ +#define PIO_PC15X1_AD12B4 (1u << 15) /**< \brief Adc12b signal: AD12B4 */ +#define PIO_PC16X1_AD12B5 (1u << 16) /**< \brief Adc12b signal: AD12B5 */ +#define PIO_PC17X1_AD12B6 (1u << 17) /**< \brief Adc12b signal: AD12B6 */ +#define PIO_PC18X1_AD12B7 (1u << 18) /**< \brief Adc12b signal: AD12B7 */ +#define PIO_PA2B_AD12BTRG (1u << 2) /**< \brief Adc12b signal: AD12BTRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PB7B_A0 (1u << 7) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PB7B_NBS0 (1u << 7) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PB8B_A1 (1u << 8) /**< \brief Ebi signal: A1 */ +#define PIO_PC8A_A10 (1u << 8) /**< \brief Ebi signal: A10 */ +#define PIO_PC9A_A11 (1u << 9) /**< \brief Ebi signal: A11 */ +#define PIO_PC10A_A12 (1u << 10) /**< \brief Ebi signal: A12 */ +#define PIO_PC11A_A13 (1u << 11) /**< \brief Ebi signal: A13 */ +#define PIO_PC20A_A14 (1u << 20) /**< \brief Ebi signal: A14 */ +#define PIO_PC21A_A15 (1u << 21) /**< \brief Ebi signal: A15 */ +#define PIO_PC22A_A16 (1u << 22) /**< \brief Ebi signal: A16 */ +#define PIO_PC23A_A17 (1u << 23) /**< \brief Ebi signal: A17 */ +#define PIO_PC24A_A18 (1u << 24) /**< \brief Ebi signal: A18 */ +#define PIO_PC25A_A19 (1u << 25) /**< \brief Ebi signal: A19 */ +#define PIO_PB0B_A2 (1u << 0) /**< \brief Ebi signal: A2 */ +#define PIO_PC0A_A2 (1u << 0) /**< \brief Ebi signal: A2 */ +#define PIO_PC13A_A2 (1u << 13) /**< \brief Ebi signal: A2 */ +#define PIO_PC26A_A20 (1u << 26) /**< \brief Ebi signal: A20 */ +#define PIO_PB21A_A21 (1u << 21) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PB21A_NANDALE (1u << 21) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PB22A_A22 (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PB22A_NANDCLE (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC27A_A23 (1u << 27) /**< \brief Ebi signal: A23 */ +#define PIO_PB1B_A3 (1u << 1) /**< \brief Ebi signal: A3 */ +#define PIO_PC1A_A3 (1u << 1) /**< \brief Ebi signal: A3 */ +#define PIO_PC14A_A3 (1u << 14) /**< \brief Ebi signal: A3 */ +#define PIO_PB2B_A4 (1u << 2) /**< \brief Ebi signal: A4 */ +#define PIO_PC2A_A4 (1u << 2) /**< \brief Ebi signal: A4 */ +#define PIO_PB3B_A5 (1u << 3) /**< \brief Ebi signal: A5 */ +#define PIO_PC3A_A5 (1u << 3) /**< \brief Ebi signal: A5 */ +#define PIO_PB4B_A6 (1u << 4) /**< \brief Ebi signal: A6 */ +#define PIO_PC4A_A6 (1u << 4) /**< \brief Ebi signal: A6 */ +#define PIO_PB5B_A7 (1u << 5) /**< \brief Ebi signal: A7 */ +#define PIO_PC5A_A7 (1u << 5) /**< \brief Ebi signal: A7 */ +#define PIO_PC6A_A8 (1u << 6) /**< \brief Ebi signal: A8 */ +#define PIO_PC7A_A9 (1u << 7) /**< \brief Ebi signal: A9 */ +#define PIO_PB9A_D0 (1u << 9) /**< \brief Ebi signal: D0 */ +#define PIO_PB10A_D1 (1u << 10) /**< \brief Ebi signal: D1 */ +#define PIO_PB27A_D10 (1u << 27) /**< \brief Ebi signal: D10 */ +#define PIO_PB28A_D11 (1u << 28) /**< \brief Ebi signal: D11 */ +#define PIO_PB29A_D12 (1u << 29) /**< \brief Ebi signal: D12 */ +#define PIO_PB30A_D13 (1u << 30) /**< \brief Ebi signal: D13 */ +#define PIO_PB31A_D14 (1u << 31) /**< \brief Ebi signal: D14 */ +#define PIO_PB6B_D15 (1u << 6) /**< \brief Ebi signal: D15 */ +#define PIO_PB11A_D2 (1u << 11) /**< \brief Ebi signal: D2 */ +#define PIO_PB12A_D3 (1u << 12) /**< \brief Ebi signal: D3 */ +#define PIO_PB13A_D4 (1u << 13) /**< \brief Ebi signal: D4 */ +#define PIO_PB14A_D5 (1u << 14) /**< \brief Ebi signal: D5 */ +#define PIO_PB15A_D6 (1u << 15) /**< \brief Ebi signal: D6 */ +#define PIO_PB16A_D7 (1u << 16) /**< \brief Ebi signal: D7 */ +#define PIO_PB25A_D8 (1u << 25) /**< \brief Ebi signal: D8 */ +#define PIO_PB26A_D9 (1u << 26) /**< \brief Ebi signal: D9 */ +#define PIO_PB17A_NANDOE (1u << 17) /**< \brief Ebi signal: NANDOE */ +#define PIO_PB24A_NANDRDY (1u << 24) /**< \brief Ebi signal: NANDRDY */ +#define PIO_PB18A_NANDWE (1u << 18) /**< \brief Ebi signal: NANDWE */ +#define PIO_PB20A_NCS0 (1u << 20) /**< \brief Ebi signal: NCS0 */ +#define PIO_PA16B_NCS1 (1u << 16) /**< \brief Ebi signal: NCS1 */ +#define PIO_PC12A_NCS1 (1u << 12) /**< \brief Ebi signal: NCS1 */ +#define PIO_PC16A_NCS2 (1u << 16) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC17A_NCS3 (1u << 17) /**< \brief Ebi signal: NCS3 */ +#define PIO_PB19A_NRD (1u << 19) /**< \brief Ebi signal: NRD */ +#define PIO_PC18A_NWAIT (1u << 18) /**< \brief Ebi signal: NWAIT */ +#define PIO_PB23A_NWR0 (1u << 23) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PB23A_NWE (1u << 23) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC15A_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PC15A_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA4A_MCCDA (1u << 4) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA3A_MCCK (1u << 3) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA5A_MCDA0 (1u << 5) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA6A_MCDA1 (1u << 6) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA7A_MCDA2 (1u << 7) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA8A_MCDA3 (1u << 8) /**< \brief Hsmci signal: MCDA3 */ +#define PIO_PC28B_MCDA4 (1u << 28) /**< \brief Hsmci signal: MCDA4 */ +#define PIO_PC29B_MCDA5 (1u << 29) /**< \brief Hsmci signal: MCDA5 */ +#define PIO_PC30B_MCDA6 (1u << 30) /**< \brief Hsmci signal: MCDA6 */ +#define PIO_PC31B_MCDA7 (1u << 31) /**< \brief Hsmci signal: MCDA7 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA21B_PCK0 (1u << 21) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA27B_PCK0 (1u << 27) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA3B_PCK1 (1u << 3) /**< \brief Pmc signal: PCK1 */ +#define PIO_PB24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */ +#define PIO_PB23B_PCK2 (1u << 23) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM peripheral ========== */ +#define PIO_PA11B_PWMFI0 (1u << 11) /**< \brief Pwm signal: PWMFI0 */ +#define PIO_PA12B_PWMFI1 (1u << 12) /**< \brief Pwm signal: PWMFI1 */ +#define PIO_PA18B_PWMFI2 (1u << 18) /**< \brief Pwm signal: PWMFI2 */ +#define PIO_PA4B_PWMH0 (1u << 4) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA28B_PWMH0 (1u << 28) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB13B_PWMH0 (1u << 13) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PC24B_PWMH0 (1u << 24) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA29B_PWMH1 (1u << 29) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB14B_PWMH1 (1u << 14) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PC25B_PWMH1 (1u << 25) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA6B_PWMH2 (1u << 6) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA15B_PWMH2 (1u << 15) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB15B_PWMH2 (1u << 15) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PC26B_PWMH2 (1u << 26) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA20B_PWMH3 (1u << 20) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PB3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PB16B_PWMH3 (1u << 16) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC27B_PWMH3 (1u << 27) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA7B_PWML0 (1u << 7) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB17B_PWML0 (1u << 17) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB25B_PWML0 (1u << 25) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC6B_PWML0 (1u << 6) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC29A_PWML0 (1u << 29) /**< \brief Pwm signal: PWML0 */ +#define PIO_PA8B_PWML1 (1u << 8) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB18B_PWML1 (1u << 18) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB26B_PWML1 (1u << 26) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC7B_PWML1 (1u << 7) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC30A_PWML1 (1u << 30) /**< \brief Pwm signal: PWML1 */ +#define PIO_PA9B_PWML2 (1u << 9) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB19B_PWML2 (1u << 19) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB27B_PWML2 (1u << 27) /**< \brief Pwm signal: PWML2 */ +#define PIO_PC8B_PWML2 (1u << 8) /**< \brief Pwm signal: PWML2 */ +#define PIO_PC31A_PWML2 (1u << 31) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA10B_PWML3 (1u << 10) /**< \brief Pwm signal: PWML3 */ +#define PIO_PB20B_PWML3 (1u << 20) /**< \brief Pwm signal: PWML3 */ +#define PIO_PB28B_PWML3 (1u << 28) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC9B_PWML3 (1u << 9) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC16B_PWML3 (1u << 16) /**< \brief Pwm signal: PWML3 */ +/* ========== Pio definition for SPI peripheral ========== */ +#define PIO_PA13A_MISO (1u << 13) /**< \brief Spi signal: MISO */ +#define PIO_PA14A_MOSI (1u << 14) /**< \brief Spi signal: MOSI */ +#define PIO_PA16A_NPCS0 (1u << 16) /**< \brief Spi signal: NPCS0 */ +#define PIO_PA0B_NPCS1 (1u << 0) /**< \brief Spi signal: NPCS1 */ +#define PIO_PC3B_NPCS1 (1u << 3) /**< \brief Spi signal: NPCS1 */ +#define PIO_PC19B_NPCS1 (1u << 19) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA1B_NPCS2 (1u << 1) /**< \brief Spi signal: NPCS2 */ +#define PIO_PC4B_NPCS2 (1u << 4) /**< \brief Spi signal: NPCS2 */ +#define PIO_PC14B_NPCS2 (1u << 14) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA19B_NPCS3 (1u << 19) /**< \brief Spi signal: NPCS3 */ +#define PIO_PC5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA15A_SPCK (1u << 15) /**< \brief Spi signal: SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA27A_RD (1u << 27) /**< \brief Ssc signal: RD */ +#define PIO_PA31A_RF (1u << 31) /**< \brief Ssc signal: RF */ +#define PIO_PA29A_RK (1u << 29) /**< \brief Ssc signal: RK */ +#define PIO_PA26A_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PA30A_TF (1u << 30) /**< \brief Ssc signal: TF */ +#define PIO_PA28A_TK (1u << 28) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA2A_TCLK0 (1u << 2) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PB4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA26B_TCLK2 (1u << 26) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA1A_TIOA0 (1u << 1) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PB5A_TIOA1 (1u << 5) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA30B_TIOA2 (1u << 30) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA0A_TIOB0 (1u << 0) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PB6A_TIOB1 (1u << 6) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA31B_TIOB2 (1u << 31) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA10A_TWCK0 (1u << 10) /**< \brief Twi0 signal: TWCK0 */ +#define PIO_PA9A_TWD0 (1u << 9) /**< \brief Twi0 signal: TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PA25A_TWCK1 (1u << 25) /**< \brief Twi1 signal: TWCK1 */ +#define PIO_PA24A_TWD1 (1u << 24) /**< \brief Twi1 signal: TWD1 */ +/* ========== Pio definition for UART peripheral ========== */ +#define PIO_PA11A_URXD (1u << 11) /**< \brief Uart signal: URXD */ +#define PIO_PA12A_UTXD (1u << 12) /**< \brief Uart signal: UTXD */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PB11B_DCD0 (1u << 11) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PB10B_DSR0 (1u << 10) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PB9B_DTR0 (1u << 9) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PB12B_RI0 (1u << 12) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PA19A_RXD0 (1u << 19) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PA17A_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PA18A_TXD0 (1u << 18) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA23B_CTS1 (1u << 23) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA22B_RTS1 (1u << 22) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA24B_SCK1 (1u << 24) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PA20A_TXD1 (1u << 20) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PB22B_CTS2 (1u << 22) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PB21B_RTS2 (1u << 21) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PA23A_RXD2 (1u << 23) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PA25B_SCK2 (1u << 25) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PA22A_TXD2 (1u << 22) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PB14_IDX 46 +#define PIO_PB15_IDX 47 +#define PIO_PB16_IDX 48 +#define PIO_PB17_IDX 49 +#define PIO_PB18_IDX 50 +#define PIO_PB19_IDX 51 +#define PIO_PB20_IDX 52 +#define PIO_PB21_IDX 53 +#define PIO_PB22_IDX 54 +#define PIO_PB23_IDX 55 +#define PIO_PB24_IDX 56 + +#endif /* _SAM3U2C_PIO_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/read_uid.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/read_uid.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,65 @@
+/**
+ * @file read_uid.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "stdbool.h"
+
+#include "read_uid.h"
+#include "sam3u.h"
+#include "cortex_m.h"
+
+bool unique_id_created = false;
+static uint32_t unique_id[4];
+void read_unique_id(uint32_t *id)
+{
+ if (!unique_id_created) {
+ create_unique_id();
+ unique_id_created = true;
+ }
+
+ id[0] = unique_id[0];
+ id[1] = unique_id[1];
+ id[2] = unique_id[2];
+ id[3] = unique_id[3];
+}
+
+__attribute__((section("ram_func")))
+void create_unique_id(void)
+{
+ cortex_int_state_t state;
+ state = cortex_int_get_and_disable();
+ EFC0->EEFC_FMR |= (1UL << 16);
+ EFC0->EEFC_FCR = 0x5A00000E;
+
+ /*Monitor FRDY*/
+ while ((EFC0->EEFC_FSR & EEFC_FSR_FRDY) == EEFC_FSR_FRDY);
+
+ unique_id[0] = *(uint32_t *)0x80000;
+ unique_id[1] = *(uint32_t *)0x80004;
+ unique_id[2] = *(uint32_t *)0x80008;
+ unique_id[3] = *(uint32_t *)0x8000C;
+ EFC0->EEFC_FCR = 0x5A00000F;
+
+ /*Monitor FRDY*/
+ while ((EFC0->EEFC_FSR & EEFC_FSR_FRDY) != EEFC_FSR_FRDY);
+
+ EFC0->EEFC_FMR &= ~(1UL << 16);
+ cortex_int_restore(state);
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/sam3u.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/sam3u.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,46 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ +#ifndef _SAM3U_ +#define _SAM3U_ + +#if defined (__SAM3U4E__) +#include "sam3u4e.h" +#elif defined (__SAM3U4C__) +#include "sam3u4c.h" +#elif defined (__SAM3U2E__) +#include "sam3u2e.h" +#elif defined (__SAM3U2C__) +#include "sam3u2c.h" +#elif defined (__SAM3U1E__) +#include "sam3u1e.h" +#elif defined (__SAM3U1C__) +#include "sam3u1c.h" +#endif + +#endif /* _SAM3U_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/sam3u2c.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/sam3u2c.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,484 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) %copyright_year%, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAM3U2C_
+#define _SAM3U2C_
+
+/** \addtogroup SAM3U2C_definitions SAM3U2C definitions
+ This file defines all structures and symbols for SAM3U2C:
+ - registers and bitfields
+ - peripheral base address
+ - peripheral ID
+ - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include "stdint.h"
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/* CMSIS DEFINITIONS FOR SAM3U2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/****** Cortex-M3 Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */
+/****** SAM3U2C specific Interrupt Numbers *********************************/
+
+ SUPC_IRQn = 0, /**< 0 SAM3U2C Supply Controller (SUPC) */
+ RSTC_IRQn = 1, /**< 1 SAM3U2C Reset Controller (RSTC) */
+ RTC_IRQn = 2, /**< 2 SAM3U2C Real Time Clock (RTC) */
+ RTT_IRQn = 3, /**< 3 SAM3U2C Real Time Timer (RTT) */
+ WDT_IRQn = 4, /**< 4 SAM3U2C Watchdog Timer (WDT) */
+ PMC_IRQn = 5, /**< 5 SAM3U2C Power Management Controller (PMC) */
+ EFC0_IRQn = 6, /**< 6 SAM3U2C Enhanced Embedded Flash Controller 0 (EFC0) */
+ UART_IRQn = 8, /**< 8 SAM3U2C Universal Asynchronous Receiver Transmitter (UART) */
+ SMC_IRQn = 9, /**< 9 SAM3U2C Static Memory Controller (SMC) */
+ PIOA_IRQn = 10, /**< 10 SAM3U2C Parallel I/O Controller A, (PIOA) */
+ PIOB_IRQn = 11, /**< 11 SAM3U2C Parallel I/O Controller B (PIOB) */
+ USART0_IRQn = 13, /**< 13 SAM3U2C USART 0 (USART0) */
+ USART1_IRQn = 14, /**< 14 SAM3U2C USART 1 (USART1) */
+ USART2_IRQn = 15, /**< 15 SAM3U2C USART 2 (USART2) */
+ HSMCI_IRQn = 17, /**< 17 SAM3U2C High Speed Multimedia Card Interface (HSMCI) */
+ TWI0_IRQn = 18, /**< 18 SAM3U2C Two-Wire Interface 0 (TWI0) */
+ TWI1_IRQn = 19, /**< 19 SAM3U2C Two-Wire Interface 1 (TWI1) */
+ SPI_IRQn = 20, /**< 20 SAM3U2C Serial Peripheral Interface (SPI) */
+ SSC_IRQn = 21, /**< 21 SAM3U2C Synchronous Serial Controller (SSC) */
+ TC0_IRQn = 22, /**< 22 SAM3U2C Timer Counter 0 (TC0) */
+ TC1_IRQn = 23, /**< 23 SAM3U2C Timer Counter 1 (TC1) */
+ TC2_IRQn = 24, /**< 24 SAM3U2C Timer Counter 2 (TC2) */
+ PWM_IRQn = 25, /**< 25 SAM3U2C Pulse Width Modulation Controller (PWM) */
+ ADC12B_IRQn = 26, /**< 26 SAM3U2C 12-bit ADC Controller (ADC12B) */
+ ADC_IRQn = 27, /**< 27 SAM3U2C 10-bit ADC Controller (ADC) */
+ DMAC_IRQn = 28, /**< 28 SAM3U2C DMA Controller (DMAC) */
+ UDPHS_IRQn = 29, /**< 29 SAM3U2C USB Device High Speed (UDPHS) */
+
+ PERIPH_COUNT_IRQn = 30 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnMemManage_Handler;
+ void* pfnBusFault_Handler;
+ void* pfnUsageFault_Handler;
+ void* pfnReserved1_Handler;
+ void* pfnReserved2_Handler;
+ void* pfnReserved3_Handler;
+ void* pfnReserved4_Handler;
+ void* pfnSVC_Handler;
+ void* pfnDebugMon_Handler;
+ void* pfnReserved5_Handler;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnSUPC_Handler; /* 0 Supply Controller */
+ void* pfnRSTC_Handler; /* 1 Reset Controller */
+ void* pfnRTC_Handler; /* 2 Real Time Clock */
+ void* pfnRTT_Handler; /* 3 Real Time Timer */
+ void* pfnWDT_Handler; /* 4 Watchdog Timer */
+ void* pfnPMC_Handler; /* 5 Power Management Controller */
+ void* pfnEFC0_Handler; /* 6 Enhanced Embedded Flash Controller 0 */
+ void* pvReserved7;
+ void* pfnUART_Handler; /* 8 Universal Asynchronous Receiver Transmitter */
+ void* pfnSMC_Handler; /* 9 Static Memory Controller */
+ void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A, */
+ void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
+ void* pvReserved12;
+ void* pfnUSART0_Handler; /* 13 USART 0 */
+ void* pfnUSART1_Handler; /* 14 USART 1 */
+ void* pfnUSART2_Handler; /* 15 USART 2 */
+ void* pvReserved16;
+ void* pfnHSMCI_Handler; /* 17 High Speed Multimedia Card Interface */
+ void* pfnTWI0_Handler; /* 18 Two-Wire Interface 0 */
+ void* pfnTWI1_Handler; /* 19 Two-Wire Interface 1 */
+ void* pfnSPI_Handler; /* 20 Serial Peripheral Interface */
+ void* pfnSSC_Handler; /* 21 Synchronous Serial Controller */
+ void* pfnTC0_Handler; /* 22 Timer Counter 0 */
+ void* pfnTC1_Handler; /* 23 Timer Counter 1 */
+ void* pfnTC2_Handler; /* 24 Timer Counter 2 */
+ void* pfnPWM_Handler; /* 25 Pulse Width Modulation Controller */
+ void* pfnADC12B_Handler; /* 26 12-bit ADC Controller */
+ void* pfnADC_Handler; /* 27 10-bit ADC Controller */
+ void* pfnDMAC_Handler; /* 28 DMA Controller */
+ void* pfnUDPHS_Handler; /* 29 USB Device High Speed */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void MemManage_Handler ( void );
+void BusFault_Handler ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler ( void );
+void DebugMon_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void ADC_Handler ( void );
+void ADC12B_Handler ( void );
+void DMAC_Handler ( void );
+void EFC0_Handler ( void );
+void HSMCI_Handler ( void );
+void PIOA_Handler ( void );
+void PIOB_Handler ( void );
+void PMC_Handler ( void );
+void PWM_Handler ( void );
+void RSTC_Handler ( void );
+void RTC_Handler ( void );
+void RTT_Handler ( void );
+void SMC_Handler ( void );
+void SPI_Handler ( void );
+void SSC_Handler ( void );
+void SUPC_Handler ( void );
+void TC0_Handler ( void );
+void TC1_Handler ( void );
+void TC2_Handler ( void );
+void TWI0_Handler ( void );
+void TWI1_Handler ( void );
+void UART_Handler ( void );
+void UDPHS_Handler ( void );
+void USART0_Handler ( void );
+void USART1_Handler ( void );
+void USART2_Handler ( void );
+void WDT_Handler ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV 0x0200 /**< SAM3U2C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT 1 /**< SAM3U2C does provide a MPU */
+#define __NVIC_PRIO_BITS 4 /**< SAM3U2C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include "core_cm3.h"
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_SAM3U.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3U2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2C_api Peripheral Software API */
+/*@{*/
+
+#include "component/adc.h"
+#include "component/adc12b.h"
+#include "component/chipid.h"
+#include "component/dmac.h"
+#include "component/efc.h"
+#include "component/gpbr.h"
+#include "component/hsmci.h"
+#include "component/matrix.h"
+#include "component/pdc.h"
+#include "component/pio.h"
+#include "component/pmc.h"
+#include "component/pwm.h"
+#include "component/rstc.h"
+#include "component/rtc.h"
+#include "component/rtt.h"
+#include "component/smc.h"
+#include "component/spi.h"
+#include "component/ssc.h"
+#include "component/supc.h"
+#include "component/tc.h"
+#include "component/twi.h"
+#include "component/uart.h"
+#include "component/udphs.h"
+#include "component/usart.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/* REGISTER ACCESS DEFINITIONS FOR SAM3U2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/hsmci.h"
+#include "instance/ssc.h"
+#include "instance/spi.h"
+#include "instance/tc0.h"
+#include "instance/twi0.h"
+#include "instance/twi1.h"
+#include "instance/pwm.h"
+#include "instance/usart0.h"
+#include "instance/usart1.h"
+#include "instance/usart2.h"
+#include "instance/udphs.h"
+#include "instance/adc12b.h"
+#include "instance/adc.h"
+#include "instance/dmac.h"
+#include "instance/smc.h"
+#include "instance/matrix.h"
+#include "instance/pmc.h"
+#include "instance/uart.h"
+#include "instance/chipid.h"
+#include "instance/efc0.h"
+#include "instance/pioa.h"
+#include "instance/piob.h"
+#include "instance/rstc.h"
+#include "instance/supc.h"
+#include "instance/rtt.h"
+#include "instance/wdt.h"
+#include "instance/rtc.h"
+#include "instance/gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/* PERIPHERAL ID DEFINITIONS FOR SAM3U2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0 ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */
+#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART) */
+#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA (10) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
+#define ID_HSMCI (17) /**< \brief High Speed Multimedia Card Interface (HSMCI) */
+#define ID_TWI0 (18) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1 (19) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI (20) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC (21) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0 (22) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1 (23) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2 (24) /**< \brief Timer Counter 2 (TC2) */
+#define ID_PWM (25) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC12B (26) /**< \brief 12-bit ADC Controller (ADC12B) */
+#define ID_ADC (27) /**< \brief 10-bit ADC Controller (ADC) */
+#define ID_DMAC (28) /**< \brief DMA Controller (DMAC) */
+#define ID_UDPHS (29) /**< \brief USB Device High Speed (UDPHS) */
+
+#define ID_PERIPH_COUNT (30) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/* BASE ADDRESS DEFINITIONS FOR SAM3U2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
+#define SPI (0x40008000U) /**< \brief (SPI ) Base Address */
+#define TC0 (0x40080000U) /**< \brief (TC0 ) Base Address */
+#define TWI0 (0x40084000U) /**< \brief (TWI0 ) Base Address */
+#define PDC_TWI0 (0x40084100U) /**< \brief (PDC_TWI0 ) Base Address */
+#define TWI1 (0x40088000U) /**< \brief (TWI1 ) Base Address */
+#define PDC_TWI1 (0x40088100U) /**< \brief (PDC_TWI1 ) Base Address */
+#define PWM (0x4008C000U) /**< \brief (PWM ) Base Address */
+#define PDC_PWM (0x4008C100U) /**< \brief (PDC_PWM ) Base Address */
+#define USART0 (0x40090000U) /**< \brief (USART0 ) Base Address */
+#define PDC_USART0 (0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1 (0x40094000U) /**< \brief (USART1 ) Base Address */
+#define PDC_USART1 (0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2 (0x40098000U) /**< \brief (USART2 ) Base Address */
+#define PDC_USART2 (0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define UDPHS (0x400A4000U) /**< \brief (UDPHS ) Base Address */
+#define ADC12B (0x400A8000U) /**< \brief (ADC12B ) Base Address */
+#define PDC_ADC12B (0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC (0x400AC000U) /**< \brief (ADC ) Base Address */
+#define PDC_ADC (0x400AC100U) /**< \brief (PDC_ADC ) Base Address */
+#define DMAC (0x400B0000U) /**< \brief (DMAC ) Base Address */
+#define SMC (0x400E0000U) /**< \brief (SMC ) Base Address */
+#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */
+#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */
+#define UART (0x400E0600U) /**< \brief (UART ) Base Address */
+#define PDC_UART (0x400E0700U) /**< \brief (PDC_UART ) Base Address */
+#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */
+#define EFC0 (0x400E0800U) /**< \brief (EFC0 ) Base Address */
+#define PIOA (0x400E0C00U) /**< \brief (PIOA ) Base Address */
+#define PIOB (0x400E0E00U) /**< \brief (PIOB ) Base Address */
+#define RSTC (0x400E1200U) /**< \brief (RSTC ) Base Address */
+#define SUPC (0x400E1210U) /**< \brief (SUPC ) Base Address */
+#define RTT (0x400E1230U) /**< \brief (RTT ) Base Address */
+#define WDT (0x400E1250U) /**< \brief (WDT ) Base Address */
+#define RTC (0x400E1260U) /**< \brief (RTC ) Base Address */
+#define GPBR (0x400E1290U) /**< \brief (GPBR ) Base Address */
+#else
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
+#define SPI ((Spi *)0x40008000U) /**< \brief (SPI ) Base Address */
+#define TC0 ((Tc *)0x40080000U) /**< \brief (TC0 ) Base Address */
+#define TWI0 ((Twi *)0x40084000U) /**< \brief (TWI0 ) Base Address */
+#define PDC_TWI0 ((Pdc *)0x40084100U) /**< \brief (PDC_TWI0 ) Base Address */
+#define TWI1 ((Twi *)0x40088000U) /**< \brief (TWI1 ) Base Address */
+#define PDC_TWI1 ((Pdc *)0x40088100U) /**< \brief (PDC_TWI1 ) Base Address */
+#define PWM ((Pwm *)0x4008C000U) /**< \brief (PWM ) Base Address */
+#define PDC_PWM ((Pdc *)0x4008C100U) /**< \brief (PDC_PWM ) Base Address */
+#define USART0 ((Usart *)0x40090000U) /**< \brief (USART0 ) Base Address */
+#define PDC_USART0 ((Pdc *)0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1 ((Usart *)0x40094000U) /**< \brief (USART1 ) Base Address */
+#define PDC_USART1 ((Pdc *)0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2 ((Usart *)0x40098000U) /**< \brief (USART2 ) Base Address */
+#define PDC_USART2 ((Pdc *)0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define UDPHS ((Udphs *)0x400A4000U) /**< \brief (UDPHS ) Base Address */
+#define ADC12B ((Adc12b *)0x400A8000U) /**< \brief (ADC12B ) Base Address */
+#define PDC_ADC12B ((Pdc *)0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC ((Adc *)0x400AC000U) /**< \brief (ADC ) Base Address */
+#define PDC_ADC ((Pdc *)0x400AC100U) /**< \brief (PDC_ADC ) Base Address */
+#define DMAC ((Dmac *)0x400B0000U) /**< \brief (DMAC ) Base Address */
+#define SMC ((Smc *)0x400E0000U) /**< \brief (SMC ) Base Address */
+#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */
+#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */
+#define UART ((Uart *)0x400E0600U) /**< \brief (UART ) Base Address */
+#define PDC_UART ((Pdc *)0x400E0700U) /**< \brief (PDC_UART ) Base Address */
+#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */
+#define EFC0 ((Efc *)0x400E0800U) /**< \brief (EFC0 ) Base Address */
+#define PIOA ((Pio *)0x400E0C00U) /**< \brief (PIOA ) Base Address */
+#define PIOB ((Pio *)0x400E0E00U) /**< \brief (PIOB ) Base Address */
+#define RSTC ((Rstc *)0x400E1200U) /**< \brief (RSTC ) Base Address */
+#define SUPC ((Supc *)0x400E1210U) /**< \brief (SUPC ) Base Address */
+#define RTT ((Rtt *)0x400E1230U) /**< \brief (RTT ) Base Address */
+#define WDT ((Wdt *)0x400E1250U) /**< \brief (WDT ) Base Address */
+#define RTC ((Rtc *)0x400E1260U) /**< \brief (RTC ) Base Address */
+#define GPBR ((Gpbr *)0x400E1290U) /**< \brief (GPBR ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/* PIO DEFINITIONS FOR SAM3U2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/sam3u2c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/* MEMORY MAPPING DEFINITIONS FOR SAM3U2C */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE (0x20000u)
+#define IFLASH0_PAGE_SIZE (256u)
+#define IFLASH0_LOCK_REGION_SIZE (8192u)
+#define IFLASH0_NB_OF_PAGES (64u)
+#define IFLASH0_NB_OF_LOCK_BITS (32u)
+#define IRAM0_SIZE (0x4000u)
+#define IRAM1_SIZE (0x4000u)
+#define NFCRAM_SIZE (0x1000u)
+#define IFLASH_SIZE (IFLASH0_SIZE)
+#define IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE)
+
+#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */
+#define IROM_ADDR (0x00180000u) /**< Internal ROM base address */
+#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UDPHS_RAM_ADDR (0x20180000u) /**< USB High Speed Device Port RAM base address */
+
+/* ************************************************************************** */
+/* MISCELLANEOUS DEFINITIONS FOR SAM3U2C */
+/* ************************************************************************** */
+
+#define CHIP_JTAGID (0x05B2A01FUL)
+#define CHIP_CIDR (0x280A0760UL)
+#define CHIP_EXID (0x0UL)
+
+/* ************************************************************************** */
+/* ELECTRICAL DEFINITIONS FOR SAM3U2C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
+#define CHIP_FREQ_SLCK_RC (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
+#define CHIP_FREQ_CPU_MAX (96000000UL)
+#define CHIP_FREQ_XTAL_32K (32768UL)
+#define CHIP_FREQ_XTAL_12M (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0 (24000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2 (72000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3 (84000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3U2C_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/system_SAM3U.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/system_SAM3U.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,512 @@
+/**************************************************************************//**
+ * @file system_SAM3U.c
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
+ * for the Atmel SAM3U Device Series
+ * @version V1.10
+ * @date 16. April 2013
+ *
+ * @note
+ * Copyright (C) 2019-2013 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include "sam3u.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Embedded Flash Controllers Configuration -------------
+//
+// <e0> Embedded Flash Controller 0 (EEFC0)
+// <o1.8..11> FWS: Flash Wait State <1-16><#-1>
+// <o1.24> FAM: Flash Access Mode
+// <0=> 128-bit in read mode (enhance speed)
+// <1=> 64-bit in read mode (enhance power consumption)
+// </e0>
+//
+// <e2> Embedded Flash Controller 1 (EEFC1)
+// <o3.8..11> FWS: Flash Wait State <1-16><#-1>
+// <o3.24> FAM: Flash Access Mode
+// <0=> 128-bit in read mode (enhance speed)
+// <1=> 64-bit in read mode (enhance power consumption)
+// </e2>
+*/
+#define EEFC0_SETUP 1 // Reset values:
+#define EEFC0_FMR_Val 0x00000300 // 0x00000000
+#define EEFC1_SETUP 1 // Reset values:
+#define EEFC1_FMR_Val 0x00000300 // 0x00000000
+
+
+/*--------------------- Power Management Controller Configuration ------------
+//
+// <e> Power Management Controller (PMC)
+// <h> System Clock Enable Register (PMC_SCER)
+// <o1.8> PCK0: Programmable Clock 0 Output Enable
+// <o1.9> PCK1: Programmable Clock 1 Output Enable
+// <o1.10> PCK2: Programmable Clock 2 Output Enable
+// </h>
+//
+// <h> Peripheral Clock Enable Register (PMC_PCER)
+// <o2.2> PID2: Real Time Clock Clock Enable
+// <o2.3> PID3: Real Time Timer Clock Enable
+// <o2.4> PID4: Watchdog Timer Clock Enable
+// <o2.5> PID5: Power Management Controller Clock Enable
+// <o2.6> PID6: Enhanced Embedded Flash Controller 0 Clock Enable
+// <o2.7> PID7: Enhanced Embedded Flash Controller 1 Clock Enable
+// <o2.8> PID8: UART Clock Enable
+// <o2.9> PID9: Static Memory Controller Clock Enable
+// <o2.10> PID10: Parallel I/O Controller A Clock Enable
+// <o2.11> PID11: Parallel I/O Controller B Clock Enable
+// <o2.12> PID12: Parallel I/O Controller C Clock Enable
+// <o2.13> PID13: USART 0 Clock Enable
+// <o2.14> PID14: USART 1 Clock Enable
+// <o2.15> PID15: USART 2 Clock Enable
+// <o2.16> PID16: USART 3 Clock Enable
+// <o2.17> PID17: High Speed Multimedia Card Interface Clock Enable
+// <o2.18> PID18: Two-wire Interface 0 Clock Enable
+// <o2.19> PID19: Two-wire Interface 1 Clock Enable
+// <o2.20> PID20: Synchronous Peripheral Interface Clock Enable
+// <o2.21> PID21: Synchronous Serial Controller Clock Enable
+// <o2.22> PID22: Timer Counter 0 Clock Enable
+// <o2.23> PID23: Timer Counter 1 Clock Enable
+// <o2.24> PID24: Timer Counter 2 Clock Enable
+// <o2.25> PID25: Pulse Width Modulation Controller Clock Enable
+// <o2.26> PID26: 12-bit ADC Controller Clock Enable
+// <o2.27> PID27: 10-bit ADC Controller Clock Enable
+// <o2.28> PID28: DMA Controller Clock Enable
+// <o2.29> PID29: USB Device High Speed Clock Enable
+// </h>
+//
+// <h> UTMI Clock Configuration Register (CKGR_UCKR)
+// <o3.16> UPLLEN: UTMI PLL Enable
+// <o3.20..23> UPLLCOUNT: UTMI PLL Startup Time <0-15>
+// </h>
+//
+// <h> Main Oscillator Register (CKGR_MOR)
+// <o4.0> MOSCXTEN: Main Crystal Oscillator Enable
+// <o4.1> MOSCXTBY: Main Crystal Oscillator Bypass
+// <o4.2> WAITMODE: Wait Mode Command
+// <o4.3> MOSCRCEN: Main On-chip RC Oscillator Enable
+// <o4.4..6> MOSCRCF: Main On-chip RC Oscillator Frequency Selection
+// <0=> 4MHz <1=> 8 MHz <2=> 12 MHz <3=> Reserved
+// <o4.8..15> MOSCXTST: Main Crystal Oscillator Startup Time <0-255>
+// <o4.24> MOSCSEL: Main Oscillator Selection
+// <0=> Main On-chip RC Oscillator <1=> Main Crystal Oscillator
+// <o4.25> CFDEN: Clock Failure Detector Enable
+// </h>
+//
+// <h> Clock Generator Phase Locked Loop A Register (CKGR_PLLAR)
+// <i> PLL A Freq = (Main CLOCK Freq / DIVA) * (MULA + 1)
+// <i> Example: XTAL = 12 MHz, DIVA = 1, MULA = 14 => PLLA = 168 MHz
+// <o5.0..7> DIVA: PLL Divider A <0-255>
+// <i> 0 - Divider output is 0
+// <i> 1 - Divider is bypassed
+// <i> 2 .. 255 - Divider output is the Main Clock divided by DIVA
+// <o5.8..13> PLLACOUNT: PLL A Counter <0-63>
+// <i> Number of Slow Clocks before the LOCKA bit is set in
+// <i> PMC_SR after CKGR_PLLAR is written
+// <o5.14..15> STMODE: Start Mode
+// <0=> Fast Startup <1=> Reserved <2=> Normal Startup <3=> Reserved
+// <i> Must be set to "Normal Startup" when PLL A is Off
+// <o5.16..26> MULA: PLL A Multiplier <0-2047>
+// <i> 0 - The PLL A is deactivated
+// <i> 1 .. 2047 - The PLL A Clock frequency is the PLL a input
+// <i> frequency multiplied by MULA + 1
+// </h>
+//
+// <h> Master Clock Register (CKGR_MCKR)
+// <o6.0..1> CSS: Master Clock Selection
+// <0=> Slow Clock
+// <1=> Main Clock
+// <2=> PLL A Clock
+// <3=> UPLL Clock
+// <o6.4..6> PRES: Master Clock Prescaler
+// <0=> Clock <1=> Clock / 2
+// <2=> Clock / 4 <3=> Clock / 8
+// <4=> Clock / 16 <5=> Clock / 32
+// <6=> Clock / 64 <7=> Clock / 6
+// </h>
+//
+// <h> Programmable Clock Register 0 (PMC_PCK0)
+// <o7.0..2> CSS: Master Clock Selection
+// <0=> Slow Clock
+// <1=> Main Clock
+// <2=> PLL A Clock
+// <3=> UPLL Clock
+// <4=> Master Clock
+// <5=> Master Clock
+// <6=> Master Clock
+// <7=> Master Clock
+// <o7.4..6> PRES: Programmable Clock Prescaler
+// <0=> Clock <1=> Clock / 2
+// <2=> Clock / 4 <3=> Clock / 8
+// <4=> Clock / 16 <5=> Clock / 32
+// <6=> Clock / 64 <7=> Reserved
+// </h>
+//
+// <h> Programmable Clock Register 1 (PMC_PCK1)
+// <o8.0..2> CSS: Master Clock Selection
+// <0=> Slow Clock
+// <1=> Main Clock
+// <2=> PLL A Clock
+// <3=> UPLL Clock
+// <4=> Master Clock
+// <5=> Master Clock
+// <6=> Master Clock
+// <7=> Master Clock
+// <o8.4..6> PRES: Programmable Clock Prescaler
+// <0=> None <1=> Clock / 2
+// <2=> Clock / 4 <3=> Clock / 8
+// <4=> Clock / 16 <5=> Clock / 32
+// <6=> Clock / 64 <7=> Reserved
+// </h>
+//
+// <h> Programmable Clock Register 2 (PMC_PCK2)
+// <o9.0..2> CSS: Master Clock Selection
+// <0=> Slow Clock
+// <1=> Main Clock
+// <2=> PLL A Clock
+// <3=> UPLL Clock
+// <4=> Master Clock
+// <5=> Master Clock
+// <6=> Master Clock
+// <7=> Master Clock
+// <o9.4..6> PRES: Programmable Clock Prescaler
+// <0=> None <1=> Clock / 2
+// <2=> Clock / 4 <3=> Clock / 8
+// <4=> Clock / 16 <5=> Clock / 32
+// <6=> Clock / 64 <7=> Reserved
+// </h>
+// </e>
+*/
+#define PMC_SETUP 1 // Reset values:
+#define PMC_SCER_Val 0x00000000 // WO register (0x00000001)
+#define PMC_PCER_Val 0x00001C00 // WO register (0x00000000)
+#define CKGR_UCKR_Val 0x10200000 // 0x10200800
+#define CKGR_MOR_Val 0x01370101 // 0x00000001
+#define CKGR_PLLAR_Val 0x200F8601 //0x200D8601 // 0x00003F00
+#define PMC_MCKR_Val 0x00000012 // 0x00000001
+#define PMC_PCK0_Val 0x00000000 // 0x00000000
+#define PMC_PCK1_Val 0x00000000 // 0x00000000
+#define PMC_PCK2_Val 0x00000000 // 0x00000000
+
+
+/*--------------------- Watchdog Configuration -------------------------------
+//
+// <e> Watchdog Disable
+// </e>
+*/
+#define WDT_SETUP 1 // Reset values:
+
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+/* Embedded Flash Controllers Configuration ----------------------------------*/
+#if (CHECK_RSVD((EEFC0_FMR_Val), ~0x01000F01))
+ #error "EEFC0_FMR: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((EEFC1_FMR_Val), ~0x01000F01))
+ #error "EEFC1_FMR: Invalid values of reserved bits!"
+#endif
+
+/* Power Management Controller Configuration ---------------------------------*/
+#if (CHECK_RSVD((PMC_SCER_Val), ~0x00000700))
+ #error "PMC_SCER: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PMC_PCER_Val), ~0xFFFFFFFC))
+ #error "PMC_PCER: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((CKGR_UCKR_Val), ~0x10F10000))
+ #error "CKGR_UCKR: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((CKGR_MOR_Val), ~0x03FFFF7F))
+ #error "CKGR_MOR: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((CKGR_PLLAR_Val), ~0x27FFFFFF))
+ #error "CKGR_PLLAR: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PMC_MCKR_Val), ~0x00000073))
+ #error "PMC_MCKR: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PMC_PCK0_Val), ~0x00000077))
+ #error "PMC_PCK0: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PMC_PCK1_Val), ~0x00000077))
+ #error "PMC_PCK1: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PMC_PCK2_Val), ~0x00000077))
+ #error "PMC_PCK2: Invalid values of reserved bits!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL (12000000UL) /* Crystal frequency */
+#define XTAL32 ( 32768UL) /* 32k crystal frequency */
+#define OSC_CLK ( XTAL) /* Main oscillator frequency */
+#define OSC32_CLK ( XTAL32) /* 32k oscillator frequency */
+#define ERC_OSC ( 32000UL) /* Embedded RC oscillator freqquency */
+#define EFRC_OSC ( 4000000UL) /* Embedded fast RC oscillator freq */
+
+
+
+#if (PMC_SETUP)
+ /* Determine clock frequency according to clock register values */
+ #if ((PMC_MCKR_Val & 3) == 0) /* Slow Clock is selected */
+ #if (1 /* PMC_SR & (1 << 7) */) /* MUST be checked with correct register */
+ #define __CORE_CLK_PRE (OSC32_CLK)
+ #else
+ #define __CORE_CLK_PRE (ERC_OSC)
+ #endif
+ #elif ((PMC_MCKR_Val & 3) == 1) /* Main Clock is selected */
+ #if (CKGR_MOR_Val & (1 << 24))
+ #if ((CKGR_MOR_Val & (1<< 0)) == 0)
+ #error "CKGR_MOR: Main Crystal Oscillator selected but not enabled!"
+ #endif
+ #define __CORE_CLK_PRE (OSC_CLK)
+ #else
+ #if ((CKGR_MOR_Val & (1<< 3)) == 0)
+ #error "CKGR_MOR: Main On-Chip RC Oscillator selected but not enabled!"
+ #endif
+ #if (((CKGR_MOR_Val >> 4) & 3) == 0)
+ #define __CORE_CLK_PRE (EFRC_OSC)
+ #elif (((CKGR_MOR_Val >> 4) & 3) == 1)
+ #define __CORE_CLK_PRE (EFRC_OSC * 2)
+ #elif (((CKGR_MOR_Val >> 4) & 3) == 2)
+ #define __CORE_CLK_PRE (EFRC_OSC * 3)
+ #else
+ #define __CORE_CLK_PRE (EFRC_OSC)
+ #endif
+ #endif
+ #elif ((PMC_MCKR_Val & 3) == 2) /* PLLA Clock is selected */
+ #if (CKGR_MOR_Val & (1 << 24))
+ #if ((CKGR_MOR_Val & (1<< 0)) == 0)
+ #error "CKGR_MOR: Main Crystal Oscillator selected but not enabled!"
+ #endif
+ #define __PLLA_CLK (OSC_CLK)
+ #else
+ #if ((CKGR_MOR_Val & (1<< 3)) == 0)
+ #error "CKGR_MOR: Main On-Chip RC Oscillator selected but not enabled!"
+ #endif
+ #if (((CKGR_MOR_Val >> 4) & 3) == 0)
+ #define __PLLA_CLK (EFRC_OSC)
+ #elif (((CKGR_MOR_Val >> 4) & 3) == 1)
+ #define __PLLA_CLK (EFRC_OSC * 2)
+ #elif (((CKGR_MOR_Val >> 4) & 3) == 2)
+ #define __PLLA_CLK (EFRC_OSC * 3)
+ #else
+ #define __PLLA_CLK (EFRC_OSC)
+ #endif
+ #endif
+
+ #define __PLLA_MUL ((((CKGR_PLLAR_Val) >> 16) & 0x7FF) + 1)
+ #define __PLLA_DIV ((((CKGR_PLLAR_Val) >> 0) & 0x0FF))
+ #define __CORE_CLK_PRE (__PLLA_CLK * __PLLA_MUL / __PLLA_DIV)
+ #else /* UPLL Clock is selected */
+ #define __CORE_CLK_PRE (OSC_CLK * 40)
+ #endif
+
+ #if (((PMC_MCKR_Val >> 4) & 7) == 7)
+ #define __CORE_CLK (__CORE_CLK_PRE / 6)
+ #else
+ #define __CORE_CLK (__CORE_CLK_PRE >> ((PMC_MCKR_Val >> 4) & 7))
+ #endif
+
+#else
+ #define __CORE_CLK (EFRC_OSC)
+#endif
+
+#if (__CORE_CLK > 96000000UL)
+ #error "Core Clock > 96MHz!"
+#endif
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ /* Determine clock frequency according to clock register values */
+ switch (PMC->PMC_MCKR & 3) {
+ case 0: /* Slow clock */
+ if (SUPC->SUPC_SR & (1 << 7))
+ SystemCoreClock = OSC32_CLK;
+ else
+ SystemCoreClock = ERC_OSC;
+ break;
+ case 1: /* Main clock */
+ if (PMC->CKGR_MOR & (1 << 24))
+ SystemCoreClock = OSC_CLK;
+ else {
+ SystemCoreClock = EFRC_OSC;
+ switch ((PMC->CKGR_MOR >> 4) & 3) {
+ case 0:
+ break;
+ case 1:
+ SystemCoreClock *= 2;
+ break;
+ case 2:
+ SystemCoreClock *= 3;
+ break;
+ case 3:
+ break;
+ }
+ }
+ break;
+ case 2: /* PLLA clock */
+ if (PMC->CKGR_MOR & (1 << 24))
+ SystemCoreClock = OSC_CLK;
+ else {
+ SystemCoreClock = EFRC_OSC;
+ switch ((PMC->CKGR_MOR >> 4) & 3) {
+ case 0:
+ break;
+ case 1:
+ SystemCoreClock *= 2;
+ break;
+ case 2:
+ SystemCoreClock *= 3;
+ break;
+ case 3:
+ break;
+ }
+ }
+ SystemCoreClock *= ((((PMC->CKGR_PLLAR) >> 16) & 0x7FF) + 1);
+ SystemCoreClock /= ((((PMC->CKGR_PLLAR) >> 0) & 0x0FF));
+ break;
+ case 3: /* UPLL clock */
+ SystemCoreClock = OSC_CLK * 40;
+ break;
+ }
+
+ if (((PMC->PMC_MCKR >> 4) & 7) == 7)
+ SystemCoreClock /= 6;
+ else
+ SystemCoreClock >>= ((PMC->PMC_MCKR >> 4) & 7);
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemFrequency variable.
+ */
+void SystemInit (void)
+{
+#if (EEFC0_SETUP == 1) /* Embedded Flash Controller 0 Setup */
+ EFC0->EEFC_FMR = EEFC0_FMR_Val;
+#endif
+
+#if (EEFC1_SETUP == 1) /* Embedded Flash Controller 1 Setup */
+ #ifdef EFC1 /* some SAM3U devices do not have EFC1*/
+ EFC1->EEFC_FMR = EEFC1_FMR_Val;
+ #endif
+#endif
+
+#if (PMC_SETUP == 1) /* Power Management Controller Setup */
+
+PMC->PMC_WPMR = 0x504D4300; /* Disable write protect */
+
+#if (CKGR_UCKR_Val & (1 << 16)) /* If UPLL Enabled */
+ PMC->CKGR_UCKR = CKGR_UCKR_Val;
+ while (!(PMC->PMC_SR & (1 << 6))); /* Wait for LOCKU */
+#endif
+
+#if (CKGR_MOR_Val & ((1<<3)|(1<<0))) /* If MOSCRCEN or MOSCXTEN set */
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & (1<<24)) | /* Keep the current MOSCSEL */
+ (CKGR_MOR_Val & ~(1<<24)) | /* Set value except MOSCSEL */
+ ((1<<3)|(1<<0)); /* and enable bothe OSC */
+#if (CKGR_MOR_Val & ((1 << 3)))
+ while (!(PMC->PMC_SR & (1 << 17))); /* Wait for MOSCRCS */
+#endif
+#if (CKGR_MOR_Val & ((1 << 0)))
+ while (!(PMC->PMC_SR & (1 << 0))); /* Wait for MOSCXTS */
+#endif
+ PMC->CKGR_MOR = CKGR_MOR_Val; /* set the desired selection */
+ while (!(PMC->PMC_SR & (1 << 16))); /* Wait for MOSCSELS */
+#endif
+
+#if (CKGR_PLLAR_Val & ((0x7FF<<16))) /* If MULA != 0 */
+ PMC->CKGR_PLLAR = CKGR_PLLAR_Val;
+ while (!(PMC->PMC_SR & (1 << 1))); /* Wait for LOCKA */
+#endif
+
+ if ((PMC_MCKR_Val & 0x03) >= 2) {
+ /* Write PRES field only */
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & ~0x70) | (PMC_MCKR_Val & 0x70);
+ } else {
+ /* Write CSS field only */
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & ~0x03) | (PMC_MCKR_Val & 0x03);
+ }
+ while (!(PMC->PMC_SR & (1 << 3))); /* Wait for MCKRDY */
+ PMC->PMC_MCKR = PMC_MCKR_Val; /* Write all MCKR */
+ while (!(PMC->PMC_SR & (1 << 3))); /* Wait for MCKRDY */
+
+#if (PMC_PCK0_Val)
+ PMC->PMC_PCKR[0] = PMC_PCK0_Val; /* Write PCK0 */
+ while (!(PMC->PMC_SR & (1 << 8))); /* Wait for PCKRDY0 */
+#endif
+#if (PMC_PCK1_Val)
+ PMC->PMC_PCKR[1] = PMC_PCK1_Val; /* Write PCK1 */
+ while (!(PMC->PMC_SR & (1 << 9))); /* Wait for PCKRDY1 */
+#endif
+#if (PMC_PCK2_Val)
+ PMC->PMC_PCKR[2] = PMC_PCK2_Val; /* Write PCK2 */
+ while (!(PMC->PMC_SR & (1 << 10))); /* Wait for PCKRDY2 */
+#endif
+
+ PMC->PMC_SCER = PMC_SCER_Val;
+ PMC->PMC_PCER0 = PMC_PCER_Val;
+
+PMC->PMC_WPMR = 0x504D4301; /* Enable write protect */
+#endif
+
+#if (WDT_SETUP == 1) /* Watchdog Setup */
+ WDT->WDT_MR = WDT_MR_WDDIS;
+#endif
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/system_SAM3U.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/system_SAM3U.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,62 @@
+/**************************************************************************//**
+ * @file system_SAM3U.h
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File
+ * for the Atmel SAM3U Device Series
+ * @version V1.10
+ * @date 17. April 2013
+ *
+ * @note
+ * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_SAM3U_H
+#define __SYSTEM_SAM3U_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_SAM3U_H */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/uart.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/uart.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,452 @@
+/**
+ * @file uart.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "string.h"
+
+#include "sam3u.h"
+#include "uart.h"
+#include "circ_buf.h"
+#include "cortex_m.h"
+#include "util.h"
+#include "settings.h" // for config_get_overflow_detect
+
+#define BUFFER_SIZE 512
+#define _CPU_CLK_HZ SystemCoreClock
+
+#define RX_OVRF_MSG "<DAPLink:Overflow>\n"
+#define RX_OVRF_MSG_SIZE (sizeof(RX_OVRF_MSG) - 1)
+
+
+#define I8 int8_t
+#define I16 int16_t
+#define I32 int32_t
+#define U8 uint8_t
+#define U16 uint16_t
+#define U32 uint32_t
+
+#define BIT_CDC_USB2UART_CTS (9)
+#define BIT_CDC_USB2UART_RTS (10)
+
+#define UART_PID (8)
+#define UART_RX_PIN (11)
+#define UART_TX_PIN (12)
+#define UART_RXRDY_FLAG (1uL << 0) // Rx status flag
+#define UART_TXRDY_FLAG (1uL << 1) // Tx RDY Status flag
+#define UART_TXEMPTY_FLAG (1uL << 9) // Tx EMPTY Status flag
+#define UART_ENDTX_FLAG (1uL << 4) // Tx end flag
+#define UART_RX_ERR_FLAGS (0xE0) // Parity, framing, overrun error
+#define UART_TX_INT_FLAG UART_TXEMPTY_FLAG
+#define PIO_UART_PIN_MASK ((1uL << UART_RX_PIN) | (1uL << UART_TX_PIN))
+
+#define PMC_BASE_ADDR (0x400E0400)
+#define PMC_PCER *(volatile U32*)(PMC_BASE_ADDR + 0x10) // Peripheral clock enable register
+
+#define UART_BASE_ADDR (0x400E0600)
+#define OFF_UART_CR (0x00)
+#define OFF_UART_MR (0x04)
+#define OFF_UART_IER (0x08)
+#define OFF_UART_IDR (0x0C)
+#define OFF_UART_IMR (0x10)
+#define OFF_UART_SR (0x14)
+#define OFF_UART_RHR (0x18)
+#define OFF_UART_THR (0x1C)
+#define OFF_UART_BRGR (0x20)
+#define UART_CR *(volatile U32*)(UART_BASE_ADDR + OFF_UART_CR)
+#define UART_MR *(volatile U32*)(UART_BASE_ADDR + OFF_UART_MR)
+#define UART_IER *(volatile U32*)(UART_BASE_ADDR + OFF_UART_IER)
+#define UART_IDR *(volatile U32*)(UART_BASE_ADDR + OFF_UART_IDR)
+#define UART_IMR *(volatile U32*)(UART_BASE_ADDR + OFF_UART_IMR)
+#define UART_SR *(volatile U32*)(UART_BASE_ADDR + OFF_UART_SR)
+#define UART_RHR *(volatile U32*)(UART_BASE_ADDR + OFF_UART_RHR)
+#define UART_THR *(volatile U32*)(UART_BASE_ADDR + OFF_UART_THR)
+#define UART_BRGR *(volatile U32*)(UART_BASE_ADDR + OFF_UART_BRGR)
+#define OFF_PDC_RPR (0x100)
+#define OFF_PDC_RCR (0x104)
+#define OFF_PDC_TPR (0x108)
+#define OFF_PDC_TCR (0x10C)
+#define OFF_PDC_RNPR (0x110)
+#define OFF_PDC_RNCR (0x114)
+#define OFF_PDC_TNPR (0x118)
+#define OFF_PDC_TNCR (0x11C)
+#define OFF_PDC_PTCR (0x120)
+#define OFF_PDC_PTSR (0x124)
+#define UART_PDC_RPR *(volatile U32*)(UART_BASE_ADDR + OFF_PDC_RPR)
+#define UART_PDC_RCR *(volatile U32*)(UART_BASE_ADDR + OFF_PDC_RCR)
+#define UART_PDC_TPR *(volatile U32*)(UART_BASE_ADDR + OFF_PDC_TPR)
+#define UART_PDC_TCR *(volatile U32*)(UART_BASE_ADDR + OFF_PDC_TCR)
+#define UART_PDC_RNPR *(volatile U32*)(UART_BASE_ADDR + OFF_PDC_RNPR)
+#define UART_PDC_RNCR *(volatile U32*)(UART_BASE_ADDR + OFF_PDC_RNCR)
+#define UART_PDC_TNPR *(volatile U32*)(UART_BASE_ADDR + OFF_PDC_TNPR)
+#define UART_PDC_TNCR *(volatile U32*)(UART_BASE_ADDR + OFF_PDC_TNCR)
+#define UART_PDC_PTCR *(volatile U32*)(UART_BASE_ADDR + OFF_PDC_PTCR)
+#define UART_PDC_PTSR *(volatile U32*)(UART_BASE_ADDR + OFF_PDC_PTSR)
+
+#define PIOA_BASE_ADDR (0x400E0C00)
+#define PIOA_PDR (*(volatile U32*) (PIOA_BASE_ADDR + 0x04)) // PIO Disable Register
+#define PIOA_IFER (*(volatile U32*) (PIOA_BASE_ADDR + 0x20)) // Input Filter Enable Register
+#define PIOA_SODR (*(volatile U32*) (PIOA_BASE_ADDR + 0x30)) // Set output data
+#define PIOA_CODR (*(volatile U32*) (PIOA_BASE_ADDR + 0x34)) // Clear output data register
+#define PIOA_PDSR (*(volatile U32*) (PIOA_BASE_ADDR + 0x3c)) // pin data status register
+#define PIOA_IER (*(volatile U32*) (PIOA_BASE_ADDR + 0x40)) // Interrupt Enable Register
+#define PIOA_ISR (*(volatile U32*) (PIOA_BASE_ADDR + 0x4c)) // Interrupt Status Register
+#define PIOA_ABSR (*(volatile U32*) (PIOA_BASE_ADDR + 0x70)) // Peripheral AB Select Register
+#define PIOA_SCIFSR (*(volatile U32*) (PIOA_BASE_ADDR + 0x80)) // System Clock Glitch Input Filtering Select Register
+#define PIOA_AIMER (*(volatile U32*) (PIOA_BASE_ADDR + 0xB0)) // Additional Interrupt Modes Enable Register
+#define PIOA_ESR (*(volatile U32*) (PIOA_BASE_ADDR + 0xC0)) // Edge Select Register
+#define PIOA_FELLSR (*(volatile U32*) (PIOA_BASE_ADDR + 0xD0)) // Falling Edge/Low Level Select Register
+#define PIOA_REHLSR (*(volatile U32*) (PIOA_BASE_ADDR + 0xD4)) // Rising Edge/High Level Select Register
+
+circ_buf_t write_buffer;
+uint8_t write_buffer_data[BUFFER_SIZE];
+circ_buf_t read_buffer;
+uint8_t read_buffer_data[BUFFER_SIZE];
+
+static U32 _Baudrate;
+static U8 _FlowControl;
+static U8 _UARTChar0; // Use static here since PDC starts transferring the byte when we already left this function
+static U32 _TxInProgress;
+static U8 _FlowControlEnabled = 1;
+
+static U32 _DetermineDivider(U32 Baudrate)
+{
+ U32 Div;
+ //
+ // Calculate divider for baudrate and round it correctly.
+ // This is necessary to get a tolerance as small as possible.
+ //
+ Div = Baudrate << 4;
+ Div = ((_CPU_CLK_HZ << 1) / Div) ;//+ 1;
+ Div = Div >> 1;
+ return Div;
+}
+
+static int _SetBaudrate(U32 Baudrate)
+{
+ U32 Div;
+ Div = _DetermineDivider(Baudrate);
+
+ if (Div >= 1) {
+ UART_BRGR = Div;
+ _Baudrate = _CPU_CLK_HZ / Div / 16;
+ return _Baudrate;
+ }
+
+ return -1;
+}
+
+static void _Send1(void)
+{
+ // Assert that there is data in the buffer
+ util_assert(circ_buf_count_used(&write_buffer) > 0);
+
+ //
+ // Use PDC for transferring the byte to the UART since direct write to UART_THR does not seem to work properly.
+ //
+ PIOA->PIO_MDDR = (1 << UART_TX_PIN); //Disable open-drain on TX pin
+ _UARTChar0 = circ_buf_pop(&write_buffer);
+
+ _TxInProgress = 1;
+ UART_PDC_TPR = (U32)&_UARTChar0;
+ UART_PDC_TCR = 1;
+ UART_PDC_PTCR = (1 << 8); // Enable transmission
+ UART_IER = UART_TX_INT_FLAG; // enable Tx interrupt
+}
+
+static void _ResetBuffers(void)
+{
+ //TODO - assert that transmit is off
+ circ_buf_init(&write_buffer, write_buffer_data, sizeof(write_buffer_data));
+ circ_buf_init(&read_buffer, read_buffer_data, sizeof(read_buffer_data));
+ _TxInProgress = 0;
+}
+
+static int get_tx_ready()
+{
+ if (!_FlowControlEnabled) {
+ return 1;
+ }
+ return ((PIOA->PIO_PDSR >> BIT_CDC_USB2UART_CTS) & 1) == 0;
+}
+
+static void set_rx_ready(int ready)
+{
+ if (ready || !_FlowControlEnabled) {
+ PIOA->PIO_CODR = 1 << BIT_CDC_USB2UART_RTS;
+ } else {
+ PIOA->PIO_SODR = 1 << BIT_CDC_USB2UART_RTS;
+ }
+}
+
+void UART_IntrEna(void)
+{
+ NVIC_EnableIRQ(UART_IRQn); // Enable USB interrupt
+}
+
+void UART_IntrDis(void)
+{
+ NVIC_DisableIRQ(UART_IRQn); // Enable USB interrupt
+}
+
+void uart_set_control_line_state(uint16_t ctrl_bmp)
+{
+}
+
+void uart_software_flow_control()
+{
+ int v;
+
+ if (((PIOA->PIO_PDSR >> BIT_CDC_USB2UART_CTS) & 1) == 0) {
+ _TxInProgress = 0;
+ v = circ_buf_count_used(&write_buffer); // NumBytes in write buffer
+
+ if (v == 0) { // No more characters to send ?: Disable further tx interrupts
+ UART_IER = UART_TX_INT_FLAG;
+ } else {
+ _Send1(); //More bytes to send? Trigger sending of next byte
+ }
+
+ } else {
+ UART_IDR = UART_TX_INT_FLAG;
+ }
+}
+
+int32_t uart_initialize(void)
+{
+ //
+ // Initially, disable UART interrupt
+ //
+ UART_IntrDis();
+ PMC->PMC_WPMR = 0x504D4300; // Disable write protect
+ PMC->PMC_PCER0 = (1 << UART_PID) | (1 << 10); // Enable peripheral clock for UART + PIOA
+ PMC->PMC_WPMR = 0x504D4301; // Enable write protect
+ PIOA_PDR = PIO_UART_PIN_MASK; // Enable peripheral output signals (disable PIO Port A)
+ PIOA_ABSR &= ~PIO_UART_PIN_MASK; // Select "A" peripherals on PIO A (UART Rx, Tx)
+ PIOA->PIO_MDER = PIO_UART_PIN_MASK; //Enable Multi Drive Control (Open Drain) on the UART Lines so that they don't power nRF51
+ UART_CR = (0)
+ | (1 << 2) // RSTRX: Reset Receiver: 1 = The receiver logic is reset.
+ | (1 << 3) // RSTTX: Reset Transmitter: 1 = The transmitter logic is reset.
+ ;
+ UART_CR = (0)
+ | (0 << 2) // RSTRX: Release Receiver reset
+ | (0 << 3) // RSTTX: Release Transmitter reset
+ | (1 << 4) // RXEN: Receiver Enable
+ | (0 << 5) // RXDIS: Do not disable receiver
+ | (1 << 6) // TXEN: Transmitter Enable
+ | (0 << 7) // TXDIS: Do not disable transmitter
+ | (1 << 8) // RSTSTA: Reset status/error bits
+ ;
+ UART_MR = (0)
+ | (4 << 9) // PAR: Parity Type: 4 => No parity
+ | (0 << 14) // CHMODE: Channel Mode: 0 => Normal mode
+ ;
+ _SetBaudrate(9600);
+ _FlowControl = UART_FLOW_CONTROL_NONE;
+ UART_IDR = (0xFFFFFFFF); // Disable all interrupts
+ //
+ // Reset all status variables
+ //
+ _ResetBuffers();
+ //
+ // Enable UART Tx/Rx interrupts
+ //
+ UART_IER = (0)
+ | (1 << 0) // Enable Rx Interrupt
+ | (0 << 9) // Initially disable TxEmpty Interrupt
+ | (0 << 4) // Initially disable ENDTx Interrupt
+ ;
+ //
+ //Set "RTS" to LOW to indicate that we are ready to receive
+ //
+ PIOA_CODR = (1uL << BIT_CDC_USB2UART_RTS); // RTS low: Ready to receive data
+ PIOA->PIO_OER = (1uL << BIT_CDC_USB2UART_RTS); // Pins == output
+ PIOA->PIO_PER = (1uL << BIT_CDC_USB2UART_RTS); // Pins == GPIO control
+ //Set CTS as input
+ PIOA->PIO_PER = (1uL << BIT_CDC_USB2UART_CTS); // Pins == GPIO control
+ PIOA->PIO_ODR = (1uL << BIT_CDC_USB2UART_CTS); // Pins == Input
+ PIOA->PIO_IER = (1uL << BIT_CDC_USB2UART_CTS);
+ //
+ // Finally, re-enable UART interrupt
+ //
+ //NVIC_SetPriority(UART_IRQn, 1);
+ UART_IntrEna();
+ return 1; // O.K. ???
+}
+
+int32_t uart_uninitialize(void)
+{
+ UART_IntrDis();
+ UART_IDR = (0xFFFFFFFF); // Disable all interrupts
+ _ResetBuffers();
+ return 1;
+}
+
+int32_t uart_reset(void)
+{
+ uart_initialize();
+ return 1;
+}
+
+int32_t uart_set_configuration(UART_Configuration *config)
+{
+ //
+ // UART always works with no parity, 1-stop bit
+ // Parity bit is configurable but not used in current implementation
+ //
+ UART_IntrDis();
+ UART_IDR = (0xFFFFFFFF); // Disable all interrupts
+ UART_CR = (0)
+ | (1 << 5) // RXDIS: Disable receiver
+ | (1 << 7) // TXDIS: Disable transmitter
+ | (1 << 8) // RSTSTA: Reset status/error bits
+ ;
+ _FlowControl = config->FlowControl;
+ _SetBaudrate(config->Baudrate);
+ UART_CR = (0)
+ | (0 << 2) // RSTRX: Release Receiver reset
+ | (0 << 3) // RSTTX: Release Transmitter reset
+ | (1 << 4) // RXEN: Receiver Enable
+ | (0 << 5) // RXDIS: Do not disable receiver
+ | (1 << 6) // TXEN: Transmitter Enable
+ | (0 << 7) // TXDIS: Do not disable transmitter
+ | (1 << 8) // RSTSTA: Reset status/error bits
+ ;
+ UART_IER = (0)
+ | (1 << 0) // Enable Rx Interrupt
+ | (0 << 9) // Initially disable TxEmpty Interrupt
+ | (0 << 4) // Initially disable ENDTx Interrupt
+ ;
+ _ResetBuffers();
+ UART_IntrEna();
+ return 1;
+}
+
+
+int32_t uart_get_configuration(UART_Configuration *config)
+{
+ config->Baudrate = _Baudrate;
+ config->DataBits = UART_DATA_BITS_8;
+ config->FlowControl = (UART_FlowControl) _FlowControl;//UART_FLOW_CONTROL_NONE;
+ config->Parity = UART_PARITY_NONE;
+ config->StopBits = UART_STOP_BITS_1;
+ return 1;
+}
+
+int32_t uart_write_free(void)
+{
+ return circ_buf_count_free(&write_buffer);
+}
+
+
+int32_t uart_write_data(uint8_t *data, uint16_t size)
+{
+ cortex_int_state_t state;
+ uint32_t cnt;
+
+ cnt = circ_buf_write(&write_buffer, data, size);
+
+ //
+ // Atomically trigger transfer if not already in progress
+ //
+ state = cortex_int_get_and_disable();
+ if (_TxInProgress == 0 && get_tx_ready()) {
+ _Send1();
+ }
+ cortex_int_restore(state);
+
+ return cnt;
+}
+
+int32_t uart_read_data(uint8_t *data, uint16_t size)
+{
+ cortex_int_state_t state;
+ uint32_t cnt;
+
+ cnt = circ_buf_read(&read_buffer, data, size);
+
+ // Atomically check if RTS had been asserted, if there is space on the buffer then deassert RTS
+ state = cortex_int_get_and_disable();
+ if (circ_buf_count_free(&read_buffer) > RX_OVRF_MSG_SIZE) {
+ set_rx_ready(1);
+ }
+ cortex_int_restore(state);
+
+ return cnt;
+}
+
+void uart_enable_flow_control(bool enabled)
+{
+ _FlowControlEnabled = (U8)enabled;
+}
+
+void UART_IRQHandler(void)
+{
+ int Status;
+ int32_t cnt;
+ U8 data;
+ Status = UART_SR; // Examine status register
+
+ if (Status & UART_RX_ERR_FLAGS) { // In case of error: Set RSTSTA to reset status bits PARE, FRAME, OVRE and RXBRK
+ UART_CR = (1 << 8);
+ }
+
+ //
+ // Handle Rx event
+ //
+ if (Status & UART_RXRDY_FLAG) { // Data received?
+ data = UART_RHR;
+ cnt = (int32_t)circ_buf_count_free(&read_buffer) - RX_OVRF_MSG_SIZE;
+ if (cnt > 0) {
+ circ_buf_push(&read_buffer, data);
+ } else if (config_get_overflow_detect()) {
+ if (0 == cnt) {
+ circ_buf_write(&read_buffer, (uint8_t*)RX_OVRF_MSG, RX_OVRF_MSG_SIZE);
+ } else {
+ // Drop newest
+ }
+ } else {
+ // Drop oldest
+ circ_buf_pop(&read_buffer);
+ circ_buf_push(&read_buffer, data);
+ }
+
+ //If this was the last available byte on the buffer then assert RTS
+ if (cnt == 1) {
+ set_rx_ready(0);
+ }
+ }
+
+ //
+ // Handle Tx event
+ //
+ if (Status & UART_IMR & UART_TX_INT_FLAG) { // Byte has been send by UART
+ cnt = circ_buf_count_used(&write_buffer); // NumBytes in write buffer
+ if (cnt == 0) { // No more characters to send ?: Disable further tx interrupts
+ UART_IDR = UART_TX_INT_FLAG;
+ PIOA->PIO_MDER = (1 << UART_TX_PIN); //enable open-drain
+ _TxInProgress = 0;
+ } else if (get_tx_ready()) {
+ _Send1(); //More bytes to send? Trigger sending of next byte
+ } else {
+ UART_IDR = UART_TX_INT_FLAG; // disable Tx interrupt
+ PIOA->PIO_MDER = (1 << UART_TX_PIN); //enable open-drain
+ }
+ }
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/unused_usb_driver/usbd_SAM3U2C.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/unused_usb_driver/usbd_SAM3U2C.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,707 @@
+/*----------------------------------------------------------------------------
+ * RL-ARM - USB
+ *----------------------------------------------------------------------------
+ * Name: usbd_SAM3U.c
+ * Purpose: Hardware Layer module for Atmel SAM3U
+ * Rev.: V4.70
+ *----------------------------------------------------------------------------
+ * This code is part of the RealView Run-Time Library.
+ * Copyright (c) 2004-2013 KEIL - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+
+#include "RTL.h"
+#include "rl_usb.h"
+#include "sam3u.h"
+
+#define __NO_USB_LIB_C
+#include "usb_config.c"
+
+#define UDPHS_EPTFIFO_BASE (0x20180000) /* (UDPHS_EPTFIFO) Base Address */
+
+
+/*
+ * Calculate EP size code Function
+ * Called during EndPoint configuration
+ * Return Value: EP size code for given EP size
+ */
+
+static int USBD_CalcSizeEP (uint32_t size) {
+
+ if (size <= 8) {
+ return (0);
+ }
+ else if (size <= 16) {
+ return (1);
+ }
+ else if (size <= 32) {
+ return (2);
+ }
+ else if (size <= 64) {
+ return (3);
+ }
+ else if (size <= 128) {
+ return (4);
+ }
+ else if (size <= 256) {
+ return (5);
+ }
+ else if (size <= 512) {
+ return (6);
+ }
+ else if (size <= 1024) {
+ return (7);
+ }
+ return (0);
+}
+
+
+/*
+ * Retrieve bank number Function
+ * Called during EndPoint configuration
+ * Return Value: Bank number for given EP
+ */
+
+static int USBD_GetBankEP (uint32_t EPNum) {
+
+ EPNum &= 0x0F; /* Set EP number */
+ switch (EPNum) {
+ case 0:
+ return (1); /* One bank (Bank0) */
+ case 1:
+ case 2:
+ return (2); /* Double bank (Ping-Pong: Bnk0/Bnk1) */
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ return (3); /* Triple bank (Bank0 / Bank1 / Bank2)*/
+ default:
+ return (0); /* Zero bank, the EP not mapped in mem*/
+ }
+}
+
+
+/*
+ * Retrieve maximum EP size Function
+ * Called during EndPoint configuration
+ * Return Value: maximum size for given EP
+ */
+
+static int USBD_GetSizeEP (uint32_t EPNum) {
+ switch (EPNum & 0x0F) {
+ case 0:
+ return (64); /* Maximum size is 64 bytes */
+ case 1:
+ case 2:
+ return (512); /* Maximum size is 512 bytes */
+ case 3:
+ case 4:
+ return (64); /* Maximum size is 64 bytes */
+ case 5:
+ case 6:
+ return (1024); /* Maximum size is 1024 bytes */
+ default:
+ return (0); /* Non existant endpoint */
+ }
+}
+
+
+/*
+ * USB Device Interrupt enable
+ * Called by USBD_Init to enable the USB Interrupt
+ * Return Value: None
+ */
+
+void USBD_IntrEna (void) {
+ NVIC_EnableIRQ(UDPHS_IRQn); /* Enable USB interrupt */
+}
+
+
+/*
+ * USB Device Initialize Function
+ * Called by the User to initialize USB Device
+ * Return Value: None
+ */
+
+void USBD_Init (void) {
+ uint32_t n;
+
+ /* Enables the 48MHz USB Clock UDPCK and System Peripheral USB Clock */
+ PMC->PMC_WPMR = 0x504D4300; /* Disable write protect */
+ PMC->PMC_PCER0 = (1 << ID_UDPHS); /* enable clock for UPDHS */
+ PMC->CKGR_UCKR = (CKGR_UCKR_UPLLCOUNT(15) | CKGR_UCKR_UPLLEN);
+ while (!(PMC->PMC_SR & PMC_SR_LOCKU)); /* wait until PLL is locked */
+ PMC->PMC_WPMR = 0x504D4301; /* Enable write protect */
+
+ /* Configure the pull-up on D+ and disconnect it */
+ UDPHS->UDPHS_CTRL |= UDPHS_CTRL_DETACH; /* Detach */
+ UDPHS->UDPHS_CTRL |= UDPHS_CTRL_PULLD_DIS; /* Disable Pull Down */
+
+ /* Reset IP UDPHS */
+ UDPHS->UDPHS_CTRL &= ~UDPHS_CTRL_EN_UDPHS;
+ UDPHS->UDPHS_CTRL |= UDPHS_CTRL_EN_UDPHS;
+
+#if (!USBD_HS_ENABLE) /* If HS disabled */
+ UDPHS->UDPHS_TST |= (3 & UDPHS_TST_SPEED_CFG_Msk);
+#endif
+
+ /* Disable DMA for UDPHS */
+ for (n = 1; n < (UDPHSDMA_NUMBER); n++) {
+ /* RESET endpoint canal DMA: */
+ UDPHS->UDPHS_DMA[n].UDPHS_DMACONTROL = 0; /* STOP command */
+ /* Disable endpoint */
+ UDPHS->UDPHS_EPT[n].UDPHS_EPTCTLDIS = 0xFFFFFFFF;
+ /* Clear status endpoint */
+ UDPHS->UDPHS_EPT[n].UDPHS_EPTCLRSTA = 0xFFFFFFFF;
+ /* Reset endpoint config */
+ UDPHS->UDPHS_EPT[n].UDPHS_EPTCTLENB = 0;
+ /* Reset DMA channel (Buff count and Control field) */
+ UDPHS->UDPHS_DMA[n].UDPHS_DMACONTROL = (0x1 << 1); /* NON STOP command */
+ /* Reset DMA channel 0 (STOP) */
+ UDPHS->UDPHS_DMA[n].UDPHS_DMACONTROL = 0; /* STOP command */
+ /* Clear DMA channel status (read the register for clear it) */
+ UDPHS->UDPHS_DMA[n].UDPHS_DMASTATUS = UDPHS->UDPHS_DMA[n].UDPHS_DMASTATUS;
+ }
+
+ UDPHS->UDPHS_IEN = 0;
+ UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_UPSTR_RES |
+ UDPHS_CLRINT_ENDOFRSM |
+ UDPHS_CLRINT_WAKE_UP |
+ UDPHS_CLRINT_ENDRESET |
+ UDPHS_CLRINT_INT_SOF |
+ UDPHS_CLRINT_MICRO_SOF |
+ UDPHS_CLRINT_DET_SUSPD;
+
+ USBD_IntrEna(); /* Enable USB interrupt */
+}
+
+
+/*
+ * USB Device Connect Function
+ * Called by the User to Connect/Disconnect USB Device
+ * Parameters: con: Connect/Disconnect
+ * Return Value: None
+ */
+
+void USBD_Connect (BOOL con) {
+ if (con) {
+ UDPHS->UDPHS_CTRL &= ~UDPHS_CTRL_DETACH; /* Pull Up on DP */
+ UDPHS->UDPHS_CTRL |= UDPHS_CTRL_PULLD_DIS; /* Disable Pull Down */
+ } else {
+ UDPHS->UDPHS_CTRL |= UDPHS_CTRL_DETACH; /* Detach */
+ UDPHS->UDPHS_CTRL &= ~UDPHS_CTRL_PULLD_DIS; /* Enable Pull Down */
+ }
+}
+
+
+/*
+ * USB Device Reset Function
+ * Called automatically on USB Device Reset
+ * Return Value: None
+ */
+
+void USBD_Reset (void) {
+ uint32_t ep, EPMask;
+
+ EPMask = ((1 << (USBD_EP_NUM+1)) - 1);
+
+ /* Reset & Disable USB Endpoints */
+ for (ep = 0; ep <= USBD_EP_NUM; ep++) {
+ UDPHS->UDPHS_EPT[ep].UDPHS_EPTCFG = 0;
+ UDPHS->UDPHS_EPT[ep].UDPHS_EPTCTLDIS = (0x1 << 0); /* Disable EP */
+ }
+ UDPHS->UDPHS_EPTRST = EPMask; /* Reset EPs */
+ UDPHS->UDPHS_EPTRST = 0;
+
+ /* Setup USB Interrupts */ /* note: Micro_SOF not yet handled */
+#ifdef __RTX
+ UDPHS->UDPHS_IEN = ((USBD_RTX_DevTask != 0) ? UDPHS_IEN_DET_SUSPD : 0) |
+ ((USBD_RTX_DevTask != 0) ? UDPHS_IEN_MICRO_SOF : 0) |
+ ((USBD_RTX_DevTask != 0) ? UDPHS_IEN_INT_SOF : 0) |
+ ((USBD_RTX_DevTask != 0) ? UDPHS_IEN_ENDRESET : 0) |
+// ((USBD_RTX_DevTask != 0) ? UDPHS_IEN_WAKE_UP : 0) |
+// ((USBD_RTX_DevTask != 0) ? UDPHS_IEN_UPSTR_RES : 0) |
+#else
+ UDPHS->UDPHS_IEN = ((USBD_P_Suspend_Event != 0) ? UDPHS_IEN_DET_SUSPD : 0) |
+ ((USBD_P_SOF_Event != 0) ? UDPHS_IEN_MICRO_SOF : 0) |
+ ((USBD_P_SOF_Event != 0) ? UDPHS_IEN_INT_SOF : 0) |
+ ((USBD_P_Reset_Event != 0) ? UDPHS_IEN_ENDRESET : 0) |
+// ((USBD_P_WakeUp_Event != 0) ? UDPHS_IEN_WAKE_UP : 0) |
+// ((USBD_P_Resume_Event != 0) ? UDPHS_IEN_UPSTR_RES : 0) |
+#endif
+ (EPMask << 8);
+
+ /* Setup Control Endpoint 0 */
+ UDPHS->UDPHS_EPT[0].UDPHS_EPTCFG = UDPHS_EPTCFG_BK_NUMBER_1 |
+ UDPHS_EPTCFG_EPT_TYPE_CTRL8 |
+ USBD_CalcSizeEP(USBD_MAX_PACKET0) ;
+ UDPHS->UDPHS_EPT[0].UDPHS_EPTCTLENB = UDPHS_EPTCTLENB_RXRDY_TXKL |
+ UDPHS_EPTCTLENB_TX_COMPLT |
+ UDPHS_EPTCTLENB_RX_SETUP |
+ UDPHS_EPTCTLENB_STALL_SNT |
+ UDPHS_EPTCTLENB_NYET_DIS |
+ UDPHS_EPTCTLENB_EPT_ENABL;
+}
+
+
+/*
+ * USB Device Suspend Function
+ * Called automatically on USB Device Suspend
+ * Return Value: None
+ */
+
+void USBD_Suspend (void) {
+ UDPHS->UDPHS_IEN &= ~UDPHS_IEN_DET_SUSPD;
+ UDPHS->UDPHS_IEN |= UDPHS_IEN_WAKE_UP;
+}
+
+
+/*
+ * USB Device Resume Function
+ * Called automatically on USB Device Resume
+ * Return Value: None
+ */
+
+void USBD_Resume (void) {
+ UDPHS->UDPHS_IEN &= ~UDPHS_IEN_WAKE_UP;
+ UDPHS->UDPHS_IEN |= UDPHS_IEN_DET_SUSPD;
+}
+
+
+/*
+ * USB Device Remote Wakeup Function
+ * Called automatically on USB Device Remote Wakeup
+ * Return Value: None
+ */
+
+void USBD_WakeUp (void) {
+ UDPHS->UDPHS_IEN |= UDPHS_IEN_UPSTR_RES;
+ UDPHS->UDPHS_CTRL |= UDPHS_CTRL_REWAKEUP;
+}
+
+
+/*
+ * USB Device Remote Wakeup Configuration Function
+ * Parameters: cfg: Device Enable/Disable
+ * Return Value: None
+ */
+
+void USBD_WakeUpCfg (BOOL cfg) {
+ if (cfg) {
+ /* Enable wakeup mechanism */
+ } else {
+ UDPHS->UDPHS_CTRL &= ~UDPHS_CTRL_REWAKEUP;
+ UDPHS->UDPHS_IEN &= ~UDPHS_IEN_UPSTR_RES;
+ }
+}
+
+
+/*
+ * USB Device Set Address Function
+ * Parameters: adr: USB Device Address
+ * setup: Called in setup stage (!=0), else after status stage
+ * Return Value: None
+ */
+
+void USBD_SetAddress (uint32_t adr, uint32_t setup) {
+ if (setup) return;
+ if (adr) {
+ UDPHS->UDPHS_CTRL |= (UDPHS_CTRL_FADDR_EN | adr);
+ } else {
+ UDPHS->UDPHS_CTRL &= ~(UDPHS_CTRL_FADDR_EN | UDPHS_CTRL_DEV_ADDR_Msk);
+ }
+}
+
+
+/*
+ * USB Device Configure Function
+ * Parameters: cfg: Device Configure/Deconfigure
+ * Return Value: None
+ */
+
+void USBD_Configure (BOOL cfg) {
+ /* Performed by Hardware */
+}
+
+
+/*
+ * Configure USB Device Endpoint according to Descriptor
+ * Parameters: pEPD: Pointer to Device Endpoint Descriptor
+ * Return Value: None
+ */
+
+void USBD_ConfigEP (USB_ENDPOINT_DESCRIPTOR *pEPD) {
+ uint32_t num, type, dir, size, bank, interval;
+
+ num = pEPD->bEndpointAddress & 0x0F;
+ type = pEPD->bmAttributes & USB_ENDPOINT_TYPE_MASK;
+ dir = pEPD->bEndpointAddress >> 7;
+ interval = pEPD->bInterval;
+ size = USBD_CalcSizeEP(pEPD->wMaxPacketSize);
+ bank = USBD_GetBankEP(num);
+
+ /* Check if MaxPacketSize fits for EndPoint */
+ if (pEPD->wMaxPacketSize <= USBD_GetSizeEP(num)) {
+ UDPHS->UDPHS_EPT[num].UDPHS_EPTCFG = (interval << 8) |
+ (bank << 6) |
+ (type << 4) |
+ (dir << 3) |
+ (size << 0) ;
+
+ UDPHS->UDPHS_EPT[num].UDPHS_EPTCTLENB =
+ (0x1 << 9) | /* Received OUT Data Interrupt Enable */
+ (0x1 << 10) | /* Transmitted IN Data Complete Interrupt Enable */
+ (0x1 << 4) | /* NYET Disable (Only for High Speed Bulk OUT endpoints) */
+ (0x1 << 13) ; /* Stall Sent /ISO CRC Error/Number of Transaction Error */
+ }
+}
+
+
+/*
+ * Set Direction for USB Device Control Endpoint
+ * Parameters: dir: Out (dir == 0), In (dir <> 0)
+ * Return Value: None
+ */
+
+void USBD_DirCtrlEP (uint32_t dir) {
+ /* Performed by Hardware */
+}
+
+
+/*
+ * Enable USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_EnableEP (uint32_t EPNum) {
+ UDPHS->UDPHS_EPT[EPNum & 0x0F].UDPHS_EPTCTLENB = (0x1 << 0); /* EP Enable */
+}
+
+
+/*
+ * Disable USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_DisableEP (uint32_t EPNum) {
+ UDPHS->UDPHS_EPT[EPNum & 0x0F].UDPHS_EPTCTLDIS = (0x1 << 0); /* EP Disable */
+}
+
+
+/*
+ * Reset USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_ResetEP (uint32_t EPNum) {
+ EPNum &= 0x0F;
+ UDPHS->UDPHS_EPT[EPNum].UDPHS_EPTCLRSTA = (0x1 << 6) | /* Data Toggle Clear*/
+ (0x1 << 5); /* Stall Req Set */
+
+ UDPHS->UDPHS_EPTRST |= (1 << EPNum); /* Reset endpoint */
+ UDPHS->UDPHS_EPTRST &= ~(1 << EPNum);
+}
+
+
+/*
+ * Set Stall for USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_SetStallEP (uint32_t EPNum) {
+ UDPHS->UDPHS_EPT[EPNum & 0x0F].UDPHS_EPTSETSTA = (0x1 << 5); /* Stall Set */
+}
+
+
+/*
+ * Clear Stall for USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_ClrStallEP (uint32_t EPNum) {
+ UDPHS->UDPHS_EPT[EPNum & 0x0F].UDPHS_EPTCLRSTA = (0x1 << 6) | /* Clr Toggle */
+ (0x1 << 5); /* Stall Clear*/
+}
+
+
+/*
+ * Read USB Device Endpoint Data
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * pData: Pointer to Data Buffer
+ * Return Value: Number of bytes read
+ */
+
+uint32_t USBD_ReadEP (uint32_t EPNum, uint8_t *pData) {
+ uint32_t cnt, n;
+ uint8_t *pEPFIFO; /* Pointer to EP FIFO */
+
+ EPNum &= 0x0F;
+ pEPFIFO = (uint8_t *)((uint32_t *)UDPHS_EPTFIFO_BASE + (16384*EPNum));
+ cnt = (UDPHS->UDPHS_EPT[EPNum].UDPHS_EPTSTA >> 20) & 0x07FF; /* Get by */
+ for (n = 0; n < cnt; n++) {
+ *pData++ = *pEPFIFO++;
+ }
+ UDPHS->UDPHS_EPT[EPNum].UDPHS_EPTCLRSTA = (0x1 << 9); /* Rece OUT Clear */
+
+ /* RX_Setup must be cleared after Setup packet is read */
+ UDPHS->UDPHS_EPT[EPNum].UDPHS_EPTCLRSTA = (0x1 << 12); /* Rece SETUP Clear */
+
+ UDPHS->UDPHS_IEN |= (1 << (EPNum + 8)); /* Enable EP int after data read*/
+
+ return (cnt);
+}
+
+
+/*
+ * Write USB Device Endpoint Data
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * pData: Pointer to Data Buffer
+ * cnt: Number of bytes to write
+ * Return Value: Number of bytes written
+ */
+
+uint32_t USBD_WriteEP (uint32_t EPNum, uint8_t *pData, uint32_t cnt) {
+ uint32_t n;
+ uint8_t *pEPFIFO; /* Pointer to the endpoint FIFO */
+
+ EPNum &= 0x0F;
+ if (UDPHS->UDPHS_EPT[EPNum].UDPHS_EPTSTA & (0x1 << 5)) { /* If EP is stall */
+ return (cnt);
+ }
+
+ if (UDPHS->UDPHS_EPT[EPNum].UDPHS_EPTSTA & (0x1 << 11)) { /* Bank not ready */
+ return (0);
+ }
+
+ pEPFIFO = (uint8_t *)((uint32_t *)UDPHS_EPTFIFO_BASE + (16384*EPNum));
+ for (n = 0; n < cnt; n++) {
+ *pEPFIFO++ = *pData++; /* Write data to FIFO */
+ }
+
+ UDPHS->UDPHS_EPT[EPNum].UDPHS_EPTSETSTA = (0x1 << 11); /* Set packet ready */
+
+ return (cnt);
+}
+
+
+/*
+ * Get USB Device Last Frame Number
+ * Parameters: None
+ * Return Value: Frame Number
+ */
+
+uint32_t USBD_GetFrame (void) {
+ uint32_t val;
+
+ if ((UDPHS->UDPHS_FNUM & (1UL << 31)) == 0) {
+ if (USBD_HighSpeed) val = UDPHS->UDPHS_FNUM & 0x7FFFFFFF;
+ else val = (UDPHS->UDPHS_FNUM & UDPHS_FNUM_FRAME_NUMBER_Msk) >> 3;
+ } else {
+ val = 0xFFFFFFFF;
+ }
+
+ return (val);
+}
+
+
+#ifdef __RTX
+uint32_t LastError; /* Last Error */
+
+/*
+ * Get USB Device Last Error Code
+ * Parameters: None
+ * Return Value: Error Code
+ */
+
+uint32_t USBD_GetError (void) {
+ return (LastError);
+}
+#endif
+
+
+/*
+ * USB Device Interrupt Service Routine
+ */
+
+void UDPHS_IRQHandler (void) {
+ uint32_t intsta, eptsta, n;
+
+ intsta = UDPHS->UDPHS_INTSTA & UDPHS->UDPHS_IEN;
+
+ /* End of Bus Reset Interrupt */
+ if (intsta & UDPHS_INTSTA_ENDRESET) {
+ /* Get used speed (HighSpeed or FullSpeed) */
+ USBD_HighSpeed = (UDPHS->UDPHS_INTSTA & UDPHS_INTSTA_SPEED) ? 1 : 0;
+
+ USBD_Reset();
+ usbd_reset_core();
+#ifdef __RTX
+ UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_ENDRESET;
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_RESET, USBD_RTX_DevTask);
+ }
+#else
+ if (USBD_P_Reset_Event) {
+ USBD_P_Reset_Event();
+ }
+ UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_ENDRESET;
+#endif
+ }
+
+ /* USB Suspend Interrupt */
+ if (intsta & UDPHS_INTSTA_DET_SUSPD) {
+ USBD_Suspend();
+#ifdef __RTX
+ UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_DET_SUSPD;
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_SUSPEND, USBD_RTX_DevTask);
+ }
+#else
+ if (USBD_P_Suspend_Event) {
+ USBD_P_Suspend_Event();
+ }
+ UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_DET_SUSPD;
+#endif
+ }
+
+ /* USB Resume Interrupt */
+ if (intsta & UDPHS_INTSTA_WAKE_UP) {
+ USBD_Resume();
+#ifdef __RTX
+ UDPHS->UDPHS_CLRINT = UDPHS_INTSTA_WAKE_UP;
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_RESUME, USBD_RTX_DevTask);
+ }
+#else
+ if (USBD_P_Resume_Event) {
+ USBD_P_Resume_Event();
+ }
+ UDPHS->UDPHS_CLRINT = UDPHS_INTSTA_WAKE_UP;
+#endif
+ }
+
+ /* USB Remote Wakeup Interrupt */
+ if (intsta & UDPHS_INTSTA_UPSTR_RES) {
+ UDPHS->UDPHS_CLRINT = UDPHS_INTSTA_UPSTR_RES;
+ }
+
+ /* Start of Frame Interrupt */
+ if (intsta & UDPHS_INTSTA_INT_SOF) {
+ if (USBD_HighSpeed == 0) {
+#ifdef __RTX
+ UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_INT_SOF;
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_SOF, USBD_RTX_DevTask);
+ }
+#else
+ if (USBD_P_SOF_Event) {
+ USBD_P_SOF_Event();
+ }
+ UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_INT_SOF;
+#endif
+ }
+ else UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_INT_SOF;
+ }
+
+ /* Micro Frame Interrupt */
+ if (intsta & UDPHS_INTSTA_MICRO_SOF) {
+ if (USBD_HighSpeed == 1) {
+#ifdef __RTX
+ UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_MICRO_SOF;
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_SOF, USBD_RTX_DevTask);
+ }
+#else
+ if (USBD_P_SOF_Event) {
+ USBD_P_SOF_Event();
+ }
+ UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_MICRO_SOF;
+#endif
+ }
+ else UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_MICRO_SOF;
+ }
+
+ /* Endpoint Interrupts */
+ for (n = 0; n <= USBD_EP_NUM; n++) {
+ if (intsta & (1 << (n + 8))) {
+ eptsta = UDPHS->UDPHS_EPT[n].UDPHS_EPTSTA; /* Read EP status */
+
+ /* Data Packet Sent Interrupt */
+ if (eptsta & (1 << 10)) { /* Transmitted IN Data Complete Int */
+ UDPHS->UDPHS_EPT[n].UDPHS_EPTCLRSTA = (1 << 10); /* Tx IN Clear */
+#ifdef __RTX
+ if (USBD_RTX_EPTask[n]) { /* IN Packet */
+ isr_evt_set(USBD_EVT_IN, USBD_RTX_EPTask[n]);
+ }
+#else
+ if (USBD_P_EP[n]) {
+ USBD_P_EP[n](USBD_EVT_IN);
+ }
+#endif
+ }
+
+ /* Data Packet Received Interrupt */
+ if (eptsta & (1 << 9)) { /* Received OUT Data Interrupt */
+ UDPHS->UDPHS_IEN &= ~(1 << (n + 8)); /* Disable EP int until read*/
+#ifdef __RTX
+ if (USBD_RTX_EPTask[n]) { /* OUT Packet */
+ isr_evt_set(USBD_EVT_OUT, USBD_RTX_EPTask[n]);
+ }
+#else
+ if (USBD_P_EP[n]) {
+ USBD_P_EP[n](USBD_EVT_OUT);
+ }
+#endif
+ }
+
+ /* STALL Packet Sent Interrupt */
+ if (eptsta & (0x1 << 13)) { /* Stall Sent */
+ if ((UDPHS->UDPHS_EPT[n].UDPHS_EPTCFG & UDPHS_EPTCFG_EPT_TYPE_Msk) == UDPHS_EPTCFG_EPT_TYPE_CTRL8) {
+#ifdef __RTX
+ if (USBD_RTX_EPTask[n]) {
+ isr_evt_set(USBD_EVT_IN_STALL, USBD_RTX_EPTask[n]);
+ }
+#else
+ if (USBD_P_EP[n]) {
+ USBD_P_EP[n](USBD_EVT_IN_STALL);
+ }
+#endif
+ }
+ UDPHS->UDPHS_EPT[n].UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_STALL_SNT;
+ }
+
+ /* Setup Packet Received Interrupt */
+ if (eptsta & (0x1 << 12)) { /* Received SETUP Interrupt */
+ UDPHS->UDPHS_IEN &= ~(1 << (n + 8)); /* Disable EP int until read*/
+#ifdef __RTX
+ if (USBD_RTX_EPTask[n]) { /* SETUP Packet */
+ isr_evt_set(USBD_EVT_SETUP, USBD_RTX_EPTask[n]);
+ }
+#else
+ if (USBD_P_EP[n]) {
+ USBD_P_EP[n](USBD_EVT_SETUP);
+ }
+#endif
+ }
+ }
+ }
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/usb_buf.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/usb_buf.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,31 @@ +/** + * @file usb_buf.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef USB_BUF_H +#define USB_BUF_H + + +#include "stdint.h" + +#define USB_MSC_BUF_SIZE (512) +uint32_t usb_buffer[USB_MSC_BUF_SIZE / sizeof(uint32_t)]; + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/usb_config.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/usb_config.c Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,555 @@ +/** + * @file usb_config.c + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +// <e> USB Device +// <i> Enable the USB Device functionality +#define USBD_ENABLE 1 +#define USBD_RTX_CORE_STACK 0 +#define USBD_RTX_DEVICE_STACK 0 +#define USBD_RTX_ENDPOINT0_STACK 0 + +// <o0.0> High-speed +// <i> Enable high-speed functionality (if device supports it) +#define USBD_HS_ENABLE 1 +#if (defined(WEBUSB_INTERFACE) || defined(WINUSB_INTERFACE) || defined(BULK_ENDPOINT)) +#define USBD_BOS_ENABLE 1 +#else +#define USBD_BOS_ENABLE 0 +#endif +// <h> Device Settings +// <i> These settings affect Device Descriptor +// <o0> Power +// <i> Default Power Setting +// <0=> Bus-powered +// <1=> Self-powered +// <o1> Max Endpoint 0 Packet Size +// <i> Maximum packet size for endpoint zero (bMaxPacketSize0) +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes +// <o2.0..15> Vendor ID <0x0000-0xFFFF> +// <i> Vendor ID assigned by the USB-IF (idVendor) +// <o3.0..15> Product ID <0x0000-0xFFFF> +// <i> Product ID assigned by the manufacturer (idProduct) +// <o4.0..15> Device Release Number <0x0000-0xFFFF> +// <i> Device release number in binary-coded decimal (bcdDevice) +// </h> +#define USBD_POWER 0 +#define USBD_MAX_PACKET0 64 +#define USBD_DEVDESC_IDVENDOR 0x0D28 +#define USBD_DEVDESC_IDPRODUCT 0x0204 +#define USBD_DEVDESC_BCDDEVICE 0x0100 + +// <h> Configuration Settings +// <i> These settings affect Configuration Descriptor +// <o0.5> Remote Wakeup +// <i> Configuration support for remote wakeup (D5: of bmAttributes) +// <o1.0..7> Maximum Power Consumption (in mA) <0-510><#/2> +// <i> Maximum power consumption of the USB device +// <i> from the bus in this specific configuration +// <i> when the device is fully operational (bMaxPower) +// </h> +#define USBD_CFGDESC_BMATTRIBUTES 0x80 +#define USBD_CFGDESC_BMAXPOWER 0xFA + +// <h> String Settings +// <i> These settings affect String Descriptor +// <o0.0..15> Language ID <0x0000-0xFCFF> +// <i> English (United States) = 0x0409 +// <s0.126> Manufacturer String +// <i> String descriptor describing manufacturer +// <s1.126> Product String +// <i> String descriptor describing product +// <e1.0> Serial Number +// <i> Enable serial number string +// <i> If disabled serial number string will not be assigned to the USB Device +// <s2.126> Serial Number String +// <i> String descriptor describing device's serial number +// </e> +// </h> +#define USBD_STRDESC_LANGID 0x0409 +#define USBD_STRDESC_MAN L"ARM" +#ifndef USB_PROD_STR +#define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" +#else +#define _TOWIDE(x) L ## #x +#define TOWIDE(x) _TOWIDE(x) +#define USBD_STRDESC_PROD TOWIDE(USB_PROD_STR) +#endif +#define USBD_STRDESC_SER_ENABLE 1 +#define USBD_STRDESC_SER L"0001A0000000" + +// <e0> Class Support +// <i> Enables USB Device Class specific Requests +#define USBD_CLASS_ENABLE 1 + +// <e0.0> Human Interface Device (HID) +// <i> Enable class support for Human Interface Device (HID) +// <h> Interrupt Endpoint Settings +// <o1.0..4> Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o2.0..4> Interrupt Out Endpoint Number <0=> Not used <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <i> If interrupt out endpoint is not used select "Not used" +// <h> Endpoint Settings +// <o3.0..7> Maximum Endpoint Packet Size (in bytes) <0-64> +// <o4.0..7> Endpoint polling Interval (in ms) <1-255> +// <e5> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o6.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o6.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// <o7.0..7> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// </e> +// </h> +// </h> +// <h> Human Interface Device Settings +// <i> Device specific settings +// <s0.126> HID Interface String +// <o8.0..4> Number of Input Reports <1-32> +// <o9.0..4> Number of Output Reports <1-32> +// <o10.0..15> Maximum Input Report Size (in bytes) <1-65535> +// <o11.0..15> Maximum Output Report Size (in bytes) <1-65535> +// <o12.0..15> Maximum Feature Report Size (in bytes) <1-65535> +// </h> +// </e> +#ifndef HID_ENDPOINT +#define HID_ENDPOINT 0 +#else +#define HID_ENDPOINT 1 +#endif + +#ifndef WEBUSB_INTERFACE +#define WEBUSB_INTERFACE 0 +#else +#define WEBUSB_INTERFACE 1 +#endif + +#define USBD_HID_ENABLE HID_ENDPOINT +#define USBD_HID_EP_INTIN 3 +#define USBD_HID_EP_INTIN_STACK 0 +#define USBD_HID_EP_INTOUT 0 +#define USBD_HID_EP_INTOUT_STACK 0 +#define USBD_HID_WMAXPACKETSIZE 64 +#define USBD_HID_BINTERVAL 1 +#define USBD_HID_HS_ENABLE 1 +#define USBD_HID_HS_WMAXPACKETSIZE 64 +#define USBD_HID_HS_BINTERVAL 1 +#define USBD_HID_STRDESC L"CMSIS-DAP v1" +#define USBD_WEBUSB_STRDESC L"WebUSB: CMSIS-DAP" +#define USBD_HID_INREPORT_NUM 1 +#define USBD_HID_OUTREPORT_NUM 1 +#define USBD_HID_INREPORT_MAX_SZ 64 +#define USBD_HID_OUTREPORT_MAX_SZ 64 +#define USBD_HID_FEATREPORT_MAX_SZ 1 + +// <e0.0> Mass Storage Device (MSC) +// <i> Enable class support for Mass Storage Device (MSC) +// <h> Bulk Endpoint Settings +// <o1.0..4> Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o2.0..4> Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o3> Maximum Packet Size <1-1024> +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5> Maximum Packet Size <1-1024> +// <o6> Maximum NAK Rate <0-255> +// </e> +// </h> +// </h> +// <h> Mass Storage Device Settings +// <i> Device specific settings +// <s0.126> MSC Interface String +// <h> Inquiry Data +// <s1.8> Vendor Identification +// <s2.16> Product Identification +// <s3.4> Product Revision Level +// </h> +// </h> +// </e> +#ifndef MSC_ENDPOINT +#define MSC_ENDPOINT 0 +#else +#define MSC_ENDPOINT 1 +#endif +#define USBD_MSC_ENABLE MSC_ENDPOINT +#define USBD_MSC_EP_BULKIN 1 +#define USBD_MSC_EP_BULKIN_STACK 0 +#define USBD_MSC_EP_BULKOUT 2 +#define USBD_MSC_EP_BULKOUT_STACK 0 +#define USBD_MSC_WMAXPACKETSIZE 64 +#define USBD_MSC_HS_ENABLE 1 +#define USBD_MSC_HS_WMAXPACKETSIZE 512 +#define USBD_MSC_HS_BINTERVAL 0 +#define USBD_MSC_STRDESC L"USB_MSC" +// Make sure changes to USBD_MSC_INQUIRY_DATA are coordinated with mbed-ls +// since this is used to detect DAPLink drives +#define USBD_MSC_INQUIRY_DATA "MBED " \ + "VFS " \ + "0.1" + +// <e0.0> Audio Device (ADC) +// <i> Enable class support for Audio Device (ADC) +// <h> Isochronous Endpoint Settings +// <o1.0..4> Isochronous Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o2.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o3.0..10> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o5.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// </e> +// </h> +// </h> +// <h> Audio Device Settings +// <i> Device specific settings +// <s0.126> Audio Control Interface String +// <s1.126> Audio Streaming (Zero Bandwidth) Interface String +// <s2.126> Audio Streaming (Operational) Interface String +// <o6.0..7> Audio Subframe Size (in bytes) <0-255> +// <o7.0..7> Sample Resolution (in bits) <0-255> +// <o8.0..23> Sample Frequency (in Hz) <0-16777215> +// <o9> Packet Size (in bytes) <1-256> +// <o10> Packet Count <1-16> +// </h> +// </e> +#define USBD_ADC_ENABLE 0 +#define USBD_ADC_EP_ISOOUT 3 +#define USBD_ADC_WMAXPACKETSIZE 64 +#define USBD_ADC_BINTERVAL 1 +#define USBD_ADC_HS_ENABLE 0 +#define USBD_ADC_HS_WMAXPACKETSIZE 64 +#define USBD_ADC_CIF_STRDESC L"USB_ADC" +#define USBD_ADC_SIF1_STRDESC L"USB_ADC1" +#define USBD_ADC_SIF2_STRDESC L"USB_ADC2" +#define USBD_ADC_BSUBFRAMESIZE 2 +#define USBD_ADC_BBITRESOLUTION 16 +#define USBD_ADC_TSAMFREQ 32000 +#define USBD_ADC_CFG_P_S 32 +#define USBD_ADC_CFG_P_C 1 + +// <e0> Communication Device (CDC) - Abstract Control Model (ACM) +// <i> Enable class support for Communication Device (CDC) - Abstract Control Model (ACM) +// <h> Interrupt Endpoint Settings +// <o1.0..4> Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o2.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o3.0..10> Endpoint polling Interval (in ms) <0-255> +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o5.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// <o6.0..10> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// </e4> +// </h> +// </h> +// <h> Bulk Endpoint Settings +// <o7.0..4> Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o8.0..4> Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o9> Maximum Packet Size <1-1024> +// <e10> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o11> Maximum Packet Size <1-1024> +// <o12> Maximum NAK Rate <0-255> +// </e10> +// </h> +// </h> +// <h> Communication Device Settings +// <i> Device specific settings +// <s0.126> Communication Class Interface String +// <s1.126> Data Class Interface String +// <o13> Maximum Communication Device Send Buffer Size +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// <o14> Maximum Communication Device Receive Buffer Size +// <i> Minimum size must be as big as maximum packet size for Bulk Out Endpoint +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// </h> +// </e> +#ifndef CDC_ENDPOINT +#define CDC_ENDPOINT 0 +#else +#define CDC_ENDPOINT 1 +#endif +#define USBD_CDC_ACM_ENABLE CDC_ENDPOINT +#define USBD_CDC_ACM_EP_INTIN 4 +#define USBD_CDC_ACM_EP_INTIN_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE 16 +#define USBD_CDC_ACM_BINTERVAL 32 +#define USBD_CDC_ACM_HS_ENABLE 1 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE 64 +#define USBD_CDC_ACM_HS_BINTERVAL 2 +#define USBD_CDC_ACM_EP_BULKIN 6 +#define USBD_CDC_ACM_EP_BULKIN_STACK 0 +#define USBD_CDC_ACM_EP_BULKOUT 5 +#define USBD_CDC_ACM_EP_BULKOUT_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE1 64 +#define USBD_CDC_ACM_HS_ENABLE1 1 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE1 512 +#define USBD_CDC_ACM_HS_BINTERVAL1 1 +#define USBD_CDC_ACM_CIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_DIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_SENDBUF_SIZE USBD_CDC_ACM_HS_WMAXPACKETSIZE1 +#define USBD_CDC_ACM_RECEIVEBUF_SIZE USBD_CDC_ACM_HS_WMAXPACKETSIZE1 +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Send Buffer size must be larger or equal to Bulk In maximum packet size!" +#endif +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Receive Buffer size must be larger or equal to Bulk Out maximum packet size!" +#endif + +// <e0> Custom Class Device +// <i> Enables USB Custom Class Requests +// <i> Class IDs: +// <i> 0x00 - Class Reserved ID +// <i> 0x01 - Class Audio ID +// <i> 0x02 - Class Communications ID +// <i> 0x03 - Class Human Interface ID +// <i> 0x04 - Class Monitor ID +// <i> 0x05 - Class Physical Interface ID +// <i> 0x06 - Class Power ID +// <i> 0x07 - Class Printer ID +// <i> 0x08 - Class Storage ID +// <i> 0x09 - Class HUB ID +// <i> 0xEF - Class Miscellaneous ID +// <i> 0xFF - Class Vendor Specific ID +// </e> +#define USBD_CLS_ENABLE 0 + +// WebUSB support +#define USBD_WEBUSB_ENABLE WEBUSB_INTERFACE +#define USBD_WEBUSB_VENDOR_CODE 0x21 +#define USBD_WEBUSB_LANDING_URL "os.mbed.com/webusb/landing-page/?bid=" +#define USBD_WEBUSB_ORIGIN_URL "os.mbed.com/" + +// Microsoft OS Descriptors 2.0 (WinUSB) support +#define USBD_WINUSB_ENABLE WINUSB_INTERFACE +#define USBD_WINUSB_VENDOR_CODE 0x20 +// </e> +// </e> + +#ifndef BULK_ENDPOINT +#define BULK_ENDPOINT 0 +#else +#define BULK_ENDPOINT 1 +#endif +#define USBD_BULK_ENABLE BULK_ENDPOINT //no endpts left +#define USBD_BULK_EP_BULKIN 7 +#define USBD_BULK_EP_BULKOUT 8 +#define USBD_BULK_WMAXPACKETSIZE 64 +#define USBD_BULK_HS_ENABLE 1 +#define USBD_BULK_HS_WMAXPACKETSIZE 512 +#define USBD_BULK_STRDESC L"CMSIS-DAP v2" + + +/* USB Device Calculations ---------------------------------------------------*/ + +#define USBD_IF_NUM_MAX (USBD_BULK_ENABLE+USBD_WEBUSB_ENABLE+USBD_HID_ENABLE+USBD_MSC_ENABLE+(USBD_ADC_ENABLE*2)+(USBD_CDC_ACM_ENABLE*2)+USBD_CLS_ENABLE) +#define USBD_MULTI_IF (USBD_CDC_ACM_ENABLE*(USBD_HID_ENABLE|USBD_MSC_ENABLE|USBD_ADC_ENABLE|USBD_CLS_ENABLE|USBD_WEBUSB_ENABLE|USBD_BULK_ENABLE)) +#define MAX(x, y) (((x) < (y)) ? (y) : (x)) +#define USBD_EP_NUM_CALC0 MAX((USBD_HID_ENABLE *(USBD_HID_EP_INTIN )), (USBD_HID_ENABLE *(USBD_HID_EP_INTOUT!=0)*(USBD_HID_EP_INTOUT))) +#define USBD_EP_NUM_CALC1 MAX((USBD_MSC_ENABLE *(USBD_MSC_EP_BULKIN )), (USBD_MSC_ENABLE *(USBD_MSC_EP_BULKOUT))) +#define USBD_EP_NUM_CALC2 MAX((USBD_ADC_ENABLE *(USBD_ADC_EP_ISOOUT )), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_INTIN))) +#define USBD_EP_NUM_CALC3 MAX((USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKIN)), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKOUT))) +#define USBD_EP_NUM_CALC4 MAX(USBD_EP_NUM_CALC0, USBD_EP_NUM_CALC1) +#define USBD_EP_NUM_CALC5 MAX(USBD_EP_NUM_CALC2, USBD_EP_NUM_CALC3) +#define USBD_EP_NUM_CALC6 MAX(USBD_EP_NUM_CALC4, USBD_EP_NUM_CALC5) +#define USBD_EP_NUM_CALC7 MAX((USBD_BULK_ENABLE*(USBD_BULK_EP_BULKIN)), (USBD_BULK_ENABLE*(USBD_BULK_EP_BULKOUT))) +#define USBD_EP_NUM MAX(USBD_EP_NUM_CALC6, USBD_EP_NUM_CALC7) + +#if (USBD_EP_NUM > 6) +#error "SAM3U only have 7 endpoints including EP0!" +#endif + +#if (USBD_HID_ENABLE) +#if (USBD_MSC_ENABLE) +#if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_MSC_EP_BULKOUT))) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKOUT))) +#error "HID and Mass Storage Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_ADC_ENABLE) +#if ((USBD_HID_EP_INTIN == USBD_ADC_EP_ISOOUT) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_ADC_EP_ISOOUT))) +#error "HID and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (((USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKOUT))|| \ + ((USBD_HID_EP_INTOUT != 0) && \ + ((USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKOUT)))) +#error "HID and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_MSC_ENABLE) +#if (USBD_ADC_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_ADC_EP_ISOOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_ADC_EP_ISOOUT)) +#error "Mass Storage Device and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Mass Storage Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_ADC_ENABLE) +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Audio Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#define USBD_ADC_CIF_NUM (0) +#define USBD_ADC_SIF1_NUM (1) +#define USBD_ADC_SIF2_NUM (2) + +#define USBD_ADC_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+0) +#define USBD_ADC_SIF1_STR_NUM (3+USBD_STRDESC_SER_ENABLE+1) +#define USBD_ADC_SIF2_STR_NUM (3+USBD_STRDESC_SER_ENABLE+2) +#define USBD_CDC_ACM_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+0) +#define USBD_CDC_ACM_DIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+1) +#define USBD_HID_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2) +#define USBD_WEBUSB_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) +#define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) +#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) + +#if (USBD_HID_ENABLE) +#if (USBD_HID_HS_ENABLE) +#define USBD_HID_MAX_PACKET ((USBD_HID_HS_WMAXPACKETSIZE > USBD_HID_WMAXPACKETSIZE) ? USBD_HID_HS_WMAXPACKETSIZE : USBD_HID_WMAXPACKETSIZE) +#else +#define USBD_HID_MAX_PACKET (USBD_HID_WMAXPACKETSIZE) +#endif +#else +#define USBD_HID_MAX_PACKET (0) +#endif +#if (USBD_MSC_ENABLE) +#if (USBD_MSC_HS_ENABLE) +#define USBD_MSC_MAX_PACKET ((USBD_MSC_HS_WMAXPACKETSIZE > USBD_MSC_WMAXPACKETSIZE) ? USBD_MSC_HS_WMAXPACKETSIZE : USBD_MSC_WMAXPACKETSIZE) +#else +#define USBD_MSC_MAX_PACKET (USBD_MSC_WMAXPACKETSIZE) +#endif +#else +#define USBD_MSC_MAX_PACKET (0) +#endif +#if (USBD_ADC_ENABLE) +#if (USBD_ADC_HS_ENABLE) +#define USBD_ADC_MAX_PACKET ((USBD_ADC_HS_WMAXPACKETSIZE > USBD_ADC_WMAXPACKETSIZE) ? USBD_ADC_HS_WMAXPACKETSIZE : USBD_ADC_WMAXPACKETSIZE) +#else +#define USBD_ADC_MAX_PACKET (USBD_ADC_WMAXPACKETSIZE) +#endif +#else +#define USBD_ADC_MAX_PACKET (0) +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (USBD_CDC_ACM_HS_ENABLE) +#define USBD_CDC_ACM_MAX_PACKET ((USBD_CDC_ACM_HS_WMAXPACKETSIZE > USBD_CDC_ACM_WMAXPACKETSIZE) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE : USBD_CDC_ACM_WMAXPACKETSIZE) +#else +#define USBD_CDC_ACM_MAX_PACKET (USBD_CDC_ACM_WMAXPACKETSIZE) +#endif +#if (USBD_CDC_ACM_HS_ENABLE1) +#define USBD_CDC_ACM_MAX_PACKET1 ((USBD_CDC_ACM_HS_WMAXPACKETSIZE1 > USBD_CDC_ACM_WMAXPACKETSIZE1) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE1 : USBD_CDC_ACM_WMAXPACKETSIZE1) +#else +#define USBD_CDC_ACM_MAX_PACKET1 (USBD_CDC_ACM_WMAXPACKETSIZE1) +#endif +#else +#define USBD_CDC_ACM_MAX_PACKET (0) +#define USBD_CDC_ACM_MAX_PACKET1 (0) +#endif +#if (USBD_BULK_ENABLE) +#if (USBD_BULK_HS_ENABLE) +#define USBD_BULK_MAX_PACKET ((USBD_BULK_HS_WMAXPACKETSIZE > USBD_BULK_WMAXPACKETSIZE) ? USBD_BULK_HS_WMAXPACKETSIZE : USBD_BULK_WMAXPACKETSIZE) +#else +#define USBD_BULK_MAX_PACKET (USBD_BULK_WMAXPACKETSIZE) +#endif +#else +#define USBD_BULK_MAX_PACKET (0) +#endif +#define USBD_MAX_PACKET_CALC0 ((USBD_HID_MAX_PACKET > USBD_HID_MAX_PACKET ) ? (USBD_HID_MAX_PACKET ) : (USBD_HID_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC1 ((USBD_ADC_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET ) ? (USBD_ADC_MAX_PACKET ) : (USBD_CDC_ACM_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC2 ((USBD_MAX_PACKET_CALC0 > USBD_MAX_PACKET_CALC1 ) ? (USBD_MAX_PACKET_CALC0) : (USBD_MAX_PACKET_CALC1 )) +#define USBD_MAX_PACKET_CALC3 ((USBD_BULK_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET1 ) ? (USBD_BULK_MAX_PACKET) : (USBD_CDC_ACM_MAX_PACKET1 )) +#define USBD_MAX_PACKET ((USBD_MAX_PACKET_CALC3 > USBD_MAX_PACKET_CALC2 ) ? (USBD_MAX_PACKET_CALC3) : (USBD_MAX_PACKET_CALC2 )) + + +/*------------------------------------------------------------------------------ + * USB Config Functions + *----------------------------------------------------------------------------*/ + +#ifndef __USB_CONFIG___ +#define __USB_CONFIG__ + +#ifndef __NO_USB_LIB_C +#include "usb_lib.c" +#endif + +#endif /* __USB_CONFIG__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/usbcfg_SAM3U.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/usbcfg_SAM3U.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,135 @@ +/** + * @file usbcfg_SAM3U.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __USBCFG_H_SAM3U +#define __USBCFG_H_SAM3U + + +//*** <<< Use Configuration Wizard in Context Menu >>> *** + + +/* +// <h> USB Configuration +// <o0> USB Power +// <i> Default Power Setting +// <0=> Bus-powered +// <1=> Self-powered +// <o1> Max Number of Interfaces <1-256> +// <o2> Max Number of Endpoints <1-32> +// <o3> Max Endpoint 0 Packet Size +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes +// </h> +*/ + +#define USB_POWER 1 +#define USB_IF_NUM 1 +#define USB_EP_NUM 3 +#define USB_MAX_PACKET0 64 + + +/* +// <h> USB Event Handlers +// <h> Device Events +// <o0.0> Power Event +// <o1.0> Reset Event +// <o2.0> Suspend Event +// <o3.0> Resume Event +// <o4.0> Remote Wakeup Event +// <o5.0> Start of Frame Event +// <o6.0> Error Event +// </h> +// <h> Endpoint Events +// <o7.0> Endpoint 0 Event +// <o7.1> Endpoint 1 Event +// <o7.2> Endpoint 2 Event +// <o7.3> Endpoint 3 Event +// <o7.4> Endpoint 4 Event +// <o7.5> Endpoint 5 Event +// <o7.6> Endpoint 6 Event + +// </h> +// <h> USB Core Events +// <o8.0> Set Configuration Event +// <o9.0> Set Interface Event +// <o10.0> Set/Clear Feature Event +// </h> +// </h> +*/ + +#define USB_POWER_EVENT 0 +#define USB_RESET_EVENT 1 +#define USB_SUSPEND_EVENT 1 +#define USB_RESUME_EVENT 1 +#define USB_WAKEUP_EVENT 0 +#define USB_SOF_EVENT 0 +#define USB_ERROR_EVENT 0 +#define USB_EP_EVENT 0x0007 +#define USB_CONFIGURE_EVENT 1 +#define USB_INTERFACE_EVENT 0 +#define USB_FEATURE_EVENT 0 + + +/* +// <e0> USB Class Support +// <i> enables USB Class specific Requests +// <e1> Human Interface Device (HID) +// <o2> Interface Number <0-255> +// </e> +// <e3> Mass Storage +// <o4> Interface Number <0-255> +// </e> +// <e5> Audio Device +// <o6> Control Interface Number <0-255> +// <o7> Streaming Interface 1 Number <0-255> +// <o8> Streaming Interface 2 Number <0-255> +// </e> +// <e9> Communication Device +// <o10> Control Interface Number <0-255> +// <o11> Bulk Interface Number <0-255> +// <o12> Max Communication Device Buffer Size +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes +// </e> +// </e> +*/ + +#define USB_CLASS 1 +#define USB_HID 0 +#define USB_HID_IF_NUM 0 +#define USB_MSC 1 +#define USB_MSC_IF_NUM 0 +#define USB_AUDIO 0 +#define USB_ADC_CIF_NUM 0 +#define USB_ADC_SIF1_NUM 1 +#define USB_ADC_SIF2_NUM 2 +#define USB_CDC 0 +#define USB_CDC_CIF_NUM 0 +#define USB_CDC_DIF_NUM 1 +#define USB_CDC_BUFSIZE 64 + +/* +// <e0> USB Vendor Support +// <i> enables USB Vendor specific Requests +// </e> +*/ +#define USB_VENDOR 0 + + +#endif /* __USBCFG_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/usbd_ATSAM3U2C.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/atmel/sam3u2c/usbd_ATSAM3U2C.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,807 @@
+/**
+ * @file usbd_ATSAM3U2C.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "rl_usb.h"
+#include "sam3u.h"
+#include "util.h"
+
+#define __NO_USB_LIB_C
+#include "usb_config.c"
+
+#define UDPHS_EPTFIFO_BASE (0x20180000) /* (UDPHS_EPTFIFO) Base Address */
+uint32_t eptsta_copy[USBD_EP_NUM + 1];
+
+/*
+ * Calculate EP size code Function
+ * Called during EndPoint configuration
+ * Return Value: EP size code for given EP size
+ */
+
+static int USBD_CalcSizeEP(uint32_t size)
+{
+ if (size <= 8) {
+ return (0);
+ } else if (size <= 16) {
+ return (1);
+ } else if (size <= 32) {
+ return (2);
+ } else if (size <= 64) {
+ return (3);
+ } else if (size <= 128) {
+ return (4);
+ } else if (size <= 256) {
+ return (5);
+ } else if (size <= 512) {
+ return (6);
+ } else if (size <= 1024) {
+ return (7);
+ }
+
+ return (0);
+}
+
+
+/*
+ * Retrieve maximum EP size Function
+ * Called during EndPoint configuration
+ * Return Value: maximum size for given EP
+ */
+
+static int USBD_GetSizeEP(uint32_t EPNum)
+{
+ switch (EPNum & 0x0F) {
+ case 0:
+ return (64); /* Maximum size is 64 bytes */
+
+ case 1:
+ case 2:
+ return (512); /* Maximum size is 512 bytes */
+
+ case 3:
+ case 4:
+ return (64); /* Maximum size is 64 bytes */
+
+ case 5:
+ case 6:
+ return (1024); /* Maximum size is 1024 bytes */
+
+ default:
+ return (0); /* Non existant endpoint */
+ }
+}
+
+
+/*
+ * USB Device Interrupt enable
+ * Called by USBD_Init to enable the USB Interrupt
+ * Return Value: None
+ */
+
+void USBD_IntrEna(void)
+{
+ NVIC_EnableIRQ(UDPHS_IRQn); /* Enable USB interrupt */
+}
+
+
+/*
+ * USB Device Initialize Function
+ * Called by the User to initialize USB Device
+ * Return Value: None
+ */
+
+void USBD_Init(void)
+{
+ uint32_t n;
+ /* Enables the 48MHz USB Clock UDPCK and System Peripheral USB Clock */
+ PMC->PMC_WPMR = 0x504D4300; /* Disable write protect */
+ PMC->PMC_PCER0 = (1 << ID_UDPHS); /* enable clock for UPDHS */
+ PMC->CKGR_UCKR = (CKGR_UCKR_UPLLCOUNT(15) | CKGR_UCKR_UPLLEN);
+
+ while (!(PMC->PMC_SR & PMC_SR_LOCKU)); /* wait until PLL is locked */
+
+ PMC->PMC_WPMR = 0x504D4301; /* Enable write protect */
+ /* Configure the pull-up on D+ and disconnect it */
+ UDPHS->UDPHS_CTRL |= UDPHS_CTRL_DETACH; /* Detach */
+ UDPHS->UDPHS_CTRL |= UDPHS_CTRL_PULLD_DIS; /* Disable Pull Down */
+ /* Reset IP UDPHS */
+ UDPHS->UDPHS_CTRL &= ~UDPHS_CTRL_EN_UDPHS;
+ UDPHS->UDPHS_CTRL |= UDPHS_CTRL_EN_UDPHS;
+#if (!USBD_HS_ENABLE) /* If HS disabled */
+ UDPHS->UDPHS_TST |= (3 & UDPHS_TST_SPEED_CFG_Msk);
+#endif
+
+ /* Disable DMA for UDPHS */
+ for (n = 1; n < (UDPHSDMA_NUMBER); n++) {
+ /* RESET endpoint canal DMA: */
+ UDPHS->UDPHS_DMA[n].UDPHS_DMACONTROL = 0; /* STOP command */
+ /* Disable endpoint */
+ UDPHS->UDPHS_EPT[n].UDPHS_EPTCTLDIS = 0xFFFFFFFF;
+ /* Clear status endpoint */
+ UDPHS->UDPHS_EPT[n].UDPHS_EPTCLRSTA = 0xFFFFFFFF;
+ /* Reset endpoint config */
+ UDPHS->UDPHS_EPT[n].UDPHS_EPTCTLENB = 0;
+ /* Reset DMA channel (Buff count and Control field) */
+ UDPHS->UDPHS_DMA[n].UDPHS_DMACONTROL = (0x1 << 1); /* NON STOP command */
+ /* Reset DMA channel 0 (STOP) */
+ UDPHS->UDPHS_DMA[n].UDPHS_DMACONTROL = 0; /* STOP command */
+ /* Clear DMA channel status (read the register for clear it) */
+ UDPHS->UDPHS_DMA[n].UDPHS_DMASTATUS = UDPHS->UDPHS_DMA[n].UDPHS_DMASTATUS;
+ }
+
+ UDPHS->UDPHS_IEN = 0;
+ UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_UPSTR_RES |
+ UDPHS_CLRINT_ENDOFRSM |
+ UDPHS_CLRINT_WAKE_UP |
+ UDPHS_CLRINT_ENDRESET |
+ UDPHS_CLRINT_INT_SOF |
+ UDPHS_CLRINT_MICRO_SOF |
+ UDPHS_CLRINT_DET_SUSPD;
+ USBD_IntrEna(); /* Enable USB interrupt */
+}
+
+
+/*
+ * USB Device Connect Function
+ * Called by the User to Connect/Disconnect USB Device
+ * Parameters: con: Connect/Disconnect
+ * Return Value: None
+ */
+
+void USBD_Connect(BOOL con)
+{
+ if (con) {
+ UDPHS->UDPHS_CTRL &= ~UDPHS_CTRL_DETACH; /* Pull Up on DP */
+ UDPHS->UDPHS_CTRL |= UDPHS_CTRL_PULLD_DIS; /* Disable Pull Down */
+ } else {
+ UDPHS->UDPHS_CTRL |= UDPHS_CTRL_DETACH; /* Detach */
+ UDPHS->UDPHS_CTRL &= ~UDPHS_CTRL_PULLD_DIS; /* Enable Pull Down */
+ }
+}
+
+/*
+ * USB Device Reset Function
+ * Called automatically on USB Device Reset
+ * Return Value: None
+ */
+extern U8 USBD_ConfigDescriptor_HS[];
+extern U8 USBD_ConfigDescriptor[];
+void USBD_Reset(void)
+{
+ uint32_t ep, EPMask;
+ EPMask = ((1 << (USBD_EP_NUM + 1)) - 1);
+
+ /* Reset & Disable USB Endpoints */
+ for (ep = 0; ep <= USBD_EP_NUM; ep++) {
+ UDPHS->UDPHS_EPT[ep].UDPHS_EPTCFG = 0;
+ UDPHS->UDPHS_EPT[ep].UDPHS_EPTCTLDIS = (0x1 << 0); /* Disable EP */
+ eptsta_copy[ep] = 0;
+ }
+
+ UDPHS->UDPHS_EPTRST = EPMask; /* Reset EPs */
+ UDPHS->UDPHS_EPTRST = 0;
+ /* Setup USB Interrupts */ /* note: Micro_SOF not yet handled */
+#ifdef __RTX
+ UDPHS->UDPHS_IEN = ((USBD_RTX_DevTask != 0) ? UDPHS_IEN_DET_SUSPD : 0) |
+ ((USBD_RTX_DevTask != 0) ? UDPHS_IEN_MICRO_SOF : 0) |
+ ((USBD_RTX_DevTask != 0) ? UDPHS_IEN_INT_SOF : 0) |
+ ((USBD_RTX_DevTask != 0) ? UDPHS_IEN_ENDRESET : 0) |
+// ((USBD_RTX_DevTask != 0) ? UDPHS_IEN_WAKE_UP : 0) |
+// ((USBD_RTX_DevTask != 0) ? UDPHS_IEN_UPSTR_RES : 0) |
+#else
+ UDPHS->UDPHS_IEN = ((USBD_P_Suspend_Event != 0) ? UDPHS_IEN_DET_SUSPD : 0) |
+ ((USBD_P_SOF_Event != 0) ? UDPHS_IEN_MICRO_SOF : 0) |
+ ((USBD_P_SOF_Event != 0) ? UDPHS_IEN_INT_SOF : 0) |
+ ((USBD_P_Reset_Event != 0) ? UDPHS_IEN_ENDRESET : 0) |
+// ((USBD_P_WakeUp_Event != 0) ? UDPHS_IEN_WAKE_UP : 0) |
+// ((USBD_P_Resume_Event != 0) ? UDPHS_IEN_UPSTR_RES : 0) |
+#endif
+ (EPMask << 8);
+ /* Setup Control Endpoint 0 */
+ UDPHS->UDPHS_EPT[0].UDPHS_EPTCFG = UDPHS_EPTCFG_BK_NUMBER_1 |
+ UDPHS_EPTCFG_EPT_TYPE_CTRL8 |
+ USBD_CalcSizeEP(USBD_MAX_PACKET0) ;
+ UDPHS->UDPHS_EPT[0].UDPHS_EPTCTLENB = UDPHS_EPTCTLENB_RXRDY_TXKL |
+ UDPHS_EPTCTLENB_TX_COMPLT |
+ UDPHS_EPTCTLENB_RX_SETUP |
+ UDPHS_EPTCTLENB_STALL_SNT |
+ UDPHS_EPTCTLENB_NYET_DIS |
+ UDPHS_EPTCTLENB_EPT_ENABL;
+
+
+#if (USBD_HS_ENABLE == 1)
+ U8 * config_desc = USBD_ConfigDescriptor_HS;
+#else
+ U8 * config_desc = USBD_ConfigDescriptor;
+#endif
+
+ while (((USB_ENDPOINT_DESCRIPTOR *)config_desc)->bLength > 0) {
+ if (((USB_ENDPOINT_DESCRIPTOR *)config_desc)->bDescriptorType == USB_ENDPOINT_DESCRIPTOR_TYPE) {
+ uint32_t num, type, dir, size, banks, interval;
+ USB_ENDPOINT_DESCRIPTOR *pEPD = (USB_ENDPOINT_DESCRIPTOR *)config_desc;
+ num = pEPD->bEndpointAddress & 0x0F;
+ type = pEPD->bmAttributes & USB_ENDPOINT_TYPE_MASK;
+ dir = pEPD->bEndpointAddress >> 7;
+ interval = pEPD->bInterval;
+ size = USBD_CalcSizeEP(pEPD->wMaxPacketSize);
+ banks = 1;
+ UDPHS->UDPHS_EPT[num].UDPHS_EPTCFG = (interval << 8) |
+ (banks << 6) |
+ (type << 4) |
+ (dir << 3) |
+ (size << 0) ;
+ }
+ config_desc += ((USB_ENDPOINT_DESCRIPTOR *)config_desc)->bLength;
+ }
+}
+
+
+/*
+ * USB Device Suspend Function
+ * Called automatically on USB Device Suspend
+ * Return Value: None
+ */
+
+void USBD_Suspend(void)
+{
+ UDPHS->UDPHS_IEN &= ~UDPHS_IEN_DET_SUSPD;
+ UDPHS->UDPHS_IEN |= UDPHS_IEN_WAKE_UP;
+}
+
+
+/*
+ * USB Device Resume Function
+ * Called automatically on USB Device Resume
+ * Return Value: None
+ */
+
+void USBD_Resume(void)
+{
+ UDPHS->UDPHS_IEN &= ~UDPHS_IEN_WAKE_UP;
+ UDPHS->UDPHS_IEN |= UDPHS_IEN_DET_SUSPD;
+}
+
+
+/*
+ * USB Device Remote Wakeup Function
+ * Called automatically on USB Device Remote Wakeup
+ * Return Value: None
+ */
+
+void USBD_WakeUp(void)
+{
+ UDPHS->UDPHS_IEN |= UDPHS_IEN_UPSTR_RES;
+ UDPHS->UDPHS_CTRL |= UDPHS_CTRL_REWAKEUP;
+}
+
+
+/*
+ * USB Device Remote Wakeup Configuration Function
+ * Parameters: cfg: Device Enable/Disable
+ * Return Value: None
+ */
+
+void USBD_WakeUpCfg(BOOL cfg)
+{
+ if (cfg) {
+ /* Enable wakeup mechanism */
+ } else {
+ UDPHS->UDPHS_CTRL &= ~UDPHS_CTRL_REWAKEUP;
+ UDPHS->UDPHS_IEN &= ~UDPHS_IEN_UPSTR_RES;
+ }
+}
+
+
+/*
+ * USB Device Set Address Function
+ * Parameters: adr: USB Device Address
+ * setup: Called in setup stage (!=0), else after status stage
+ * Return Value: None
+ */
+
+void USBD_SetAddress(uint32_t adr, uint32_t setup)
+{
+ if (setup) {
+ return;
+ }
+
+ if (adr) {
+ UDPHS->UDPHS_CTRL |= (UDPHS_CTRL_FADDR_EN | adr);
+ } else {
+ UDPHS->UDPHS_CTRL &= ~(UDPHS_CTRL_FADDR_EN | UDPHS_CTRL_DEV_ADDR_Msk);
+ }
+}
+
+
+/*
+ * USB Device Configure Function
+ * Parameters: cfg: Device Configure/Deconfigure
+ * Return Value: None
+ */
+
+void USBD_Configure(BOOL cfg)
+{
+ /* Performed by Hardware */
+}
+
+
+/*
+ * Configure USB Device Endpoint according to Descriptor
+ * Parameters: pEPD: Pointer to Device Endpoint Descriptor
+ * Return Value: None
+ */
+
+void USBD_ConfigEP(USB_ENDPOINT_DESCRIPTOR *pEPD)
+{
+ uint32_t num;//, type, dir, size, banks, interval;
+ num = pEPD->bEndpointAddress & 0x0F;
+ /*type = pEPD->bmAttributes & USB_ENDPOINT_TYPE_MASK;
+ dir = pEPD->bEndpointAddress >> 7;
+ interval = pEPD->bInterval;
+ size = USBD_CalcSizeEP(pEPD->wMaxPacketSize);
+ banks = 1;
+ */
+ /* Check if MaxPacketSize fits for EndPoint */
+ if (pEPD->wMaxPacketSize <= USBD_GetSizeEP(num)) {
+ /*UDPHS->UDPHS_EPT[num].UDPHS_EPTCFG = (interval << 8) |
+ (banks << 6) |
+ (type << 4) |
+ (dir << 3) |
+ //(size << 0) ;
+ 6;*/
+ UDPHS->UDPHS_EPT[num].UDPHS_EPTCTLENB =
+ (0x1 << 9) | /* Received OUT Data Interrupt Enable */
+ (0x1 << 10) | /* Transmitted IN Data Complete Interrupt Enable */
+ (0x0 << 4) | /* NYET Disable (Only for High Speed Bulk OUT endpoints) */
+ (0x1 << 13) ; /* Stall Sent /ISO CRC Error/Number of Transaction Error */
+ }
+}
+
+
+/*
+ * Set Direction for USB Device Control Endpoint
+ * Parameters: dir: Out (dir == 0), In (dir <> 0)
+ * Return Value: None
+ */
+
+void USBD_DirCtrlEP(uint32_t dir)
+{
+ /* Performed by Hardware */
+}
+
+
+/*
+ * Enable USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_EnableEP(uint32_t EPNum)
+{
+ UDPHS->UDPHS_EPT[EPNum & 0x0F].UDPHS_EPTCTLENB = (0x1 << 0); /* EP Enable */
+ eptsta_copy[EPNum & 0x0F] = UDPHS->UDPHS_EPT[EPNum].UDPHS_EPTSETSTA;
+}
+
+
+/*
+ * Disable USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_DisableEP(uint32_t EPNum)
+{
+ UDPHS->UDPHS_EPT[EPNum & 0x0F].UDPHS_EPTCTLDIS = (0x1 << 0); /* EP Disable */
+ eptsta_copy[EPNum & 0x0F] = UDPHS->UDPHS_EPT[EPNum].UDPHS_EPTSETSTA;
+}
+
+
+/*
+ * Reset USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_ResetEP(uint32_t EPNum)
+{
+ EPNum &= 0x0F;
+ UDPHS->UDPHS_EPT[EPNum].UDPHS_EPTCLRSTA = (0x1 << 6) | /* Data Toggle Clear*/
+ (0x1 << 5); /* Stall Req Set */
+ UDPHS->UDPHS_EPTRST |= (1 << EPNum); /* Reset endpoint */
+ UDPHS->UDPHS_EPTRST &= ~(1 << EPNum);
+ eptsta_copy[EPNum] = UDPHS->UDPHS_EPT[EPNum].UDPHS_EPTSETSTA;
+}
+
+
+/*
+ * Set Stall for USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_SetStallEP(uint32_t EPNum)
+{
+ UDPHS->UDPHS_EPT[EPNum & 0x0F].UDPHS_EPTSETSTA = (0x1 << 5); /* Stall Set */
+ eptsta_copy[EPNum & 0x0F] |= 0x1 << 5;
+}
+
+
+/*
+ * Clear Stall for USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_ClrStallEP(uint32_t EPNum)
+{
+ UDPHS->UDPHS_EPT[EPNum & 0x0F].UDPHS_EPTCLRSTA = (0x1 << 6) | /* Clr Toggle */
+ (0x1 << 5); /* Stall Clear*/
+ eptsta_copy[EPNum & 0x0F] &= ~(0x1 << 5);
+}
+
+
+/*
+ * Read USB Device Endpoint Data
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * pData: Pointer to Data Buffer
+ * Return Value: Number of bytes read
+ */
+
+uint32_t USBD_ReadEP(uint32_t EPNum, uint8_t *pData, uint32_t size)
+{
+ uint32_t cnt, n, copy_sz;
+ uint8_t *pEPFIFO; /* Pointer to EP FIFO */
+ uint32_t eptsta;
+ EPNum &= 0x0F;
+ eptsta = eptsta_copy[EPNum];
+ pEPFIFO = (uint8_t *)((uint32_t *)UDPHS_EPTFIFO_BASE + (16384 * EPNum));
+ cnt = (eptsta >> 20) & 0x07FF; /* Get by */
+ copy_sz = cnt > size ? size : cnt;
+
+ for (n = 0; n < copy_sz; n++) {
+ *pData++ = *pEPFIFO++;
+ }
+
+ util_assert(cnt == copy_sz);
+
+ if ((cnt == copy_sz) && (eptsta & (0x1 << 9))) {
+ UDPHS->UDPHS_EPT[EPNum].UDPHS_EPTCLRSTA = (0x1 << 9); /* Rece OUT Clear */
+ }
+
+ /* RX_Setup must be cleared after Setup packet is read */
+ if (eptsta & (0x1 << 12)) {
+ UDPHS->UDPHS_EPT[EPNum].UDPHS_EPTCLRSTA = (0x1 << 12); /* Rece SETUP Clear */
+ }
+ UDPHS->UDPHS_IEN |= (1 << (EPNum + 8)); /* Enable EP int after data read*/
+ return (cnt);
+}
+
+
+/*
+ * Write USB Device Endpoint Data
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * pData: Pointer to Data Buffer
+ * cnt: Number of bytes to write
+ * Return Value: Number of bytes written
+ */
+
+uint32_t USBD_WriteEP(uint32_t EPNum, uint8_t *pData, uint32_t cnt)
+{
+ uint32_t n;
+ uint8_t *pEPFIFO; /* Pointer to the endpoint FIFO */
+ uint32_t eptsta;
+ EPNum &= 0x0F;
+ eptsta = eptsta_copy[EPNum];
+
+ // Cached value should match the real value
+ util_assert((UDPHS->UDPHS_EPT[EPNum].UDPHS_EPTSTA & (0x1 << 5)) == (eptsta & (0x1 << 5)));
+ if (eptsta & (0x1 << 5)) { /* If EP is stall */
+ return (cnt);
+ }
+
+ // Both register and cached value should indicate that the bank is ready (bit 11 clear)
+ util_assert(!(UDPHS->UDPHS_EPT[EPNum].UDPHS_EPTSTA & (0x1 << 11)));
+ util_assert(!(eptsta & (0x1 << 11)));
+
+ pEPFIFO = (uint8_t *)((uint32_t *)UDPHS_EPTFIFO_BASE + (16384 * EPNum));
+
+ for (n = 0; n < cnt; n++) {
+ *pEPFIFO++ = *pData++; /* Write data to FIFO */
+ }
+
+ UDPHS->UDPHS_EPT[EPNum].UDPHS_EPTSETSTA = (0x1 << 11); /* Set packet ready */
+ return (cnt);
+}
+
+
+/*
+ * Get USB Device Last Frame Number
+ * Parameters: None
+ * Return Value: Frame Number
+ */
+
+uint32_t USBD_GetFrame(void)
+{
+ uint32_t val;
+
+ if ((UDPHS->UDPHS_FNUM & (1UL << 31)) == 0) {
+ if (USBD_HighSpeed) {
+ val = UDPHS->UDPHS_FNUM & 0x7FFFFFFF;
+ } else {
+ val = (UDPHS->UDPHS_FNUM & UDPHS_FNUM_FRAME_NUMBER_Msk) >> 3;
+ }
+ } else {
+ val = 0xFFFFFFFF;
+ }
+
+ return (val);
+}
+
+
+#ifdef __RTX
+uint32_t LastError; /* Last Error */
+
+/*
+ * Get USB Device Last Error Code
+ * Parameters: None
+ * Return Value: Error Code
+ */
+
+uint32_t USBD_GetError(void)
+{
+ return (LastError);
+}
+#endif
+
+
+/*
+ * USB Device Interrupt Service Routine
+ */
+
+void UDPHS_IRQHandler(void)
+{
+ NVIC_DisableIRQ(UDPHS_IRQn);
+ USBD_SignalHandler();
+}
+
+/*
+ * USB Device Service Routine
+ */
+
+void USBD_Handler(void)
+{
+ uint32_t intsta, eptsta, n;
+ intsta = UDPHS->UDPHS_INTSTA & UDPHS->UDPHS_IEN;
+
+ /* End of Bus Reset Interrupt */
+ if (intsta & UDPHS_INTSTA_ENDRESET) {
+ /* Get used speed (HighSpeed or FullSpeed) */
+ USBD_HighSpeed = (UDPHS->UDPHS_INTSTA & UDPHS_INTSTA_SPEED) ? 1 : 0;
+ USBD_Reset();
+ usbd_reset_core();
+#ifdef __RTX
+ UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_ENDRESET;
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_RESET, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Reset_Event) {
+ USBD_P_Reset_Event();
+ }
+
+ UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_ENDRESET;
+#endif
+ }
+
+ /* USB Suspend Interrupt */
+ if (intsta & UDPHS_INTSTA_DET_SUSPD) {
+ USBD_Suspend();
+#ifdef __RTX
+ UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_DET_SUSPD;
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_SUSPEND, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Suspend_Event) {
+ USBD_P_Suspend_Event();
+ }
+
+ UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_DET_SUSPD;
+#endif
+ }
+
+ /* USB Resume Interrupt */
+ if (intsta & UDPHS_INTSTA_WAKE_UP) {
+ USBD_Resume();
+#ifdef __RTX
+ UDPHS->UDPHS_CLRINT = UDPHS_INTSTA_WAKE_UP;
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_RESUME, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Resume_Event) {
+ USBD_P_Resume_Event();
+ }
+
+ UDPHS->UDPHS_CLRINT = UDPHS_INTSTA_WAKE_UP;
+#endif
+ }
+
+ /* USB Remote Wakeup Interrupt */
+ if (intsta & UDPHS_INTSTA_UPSTR_RES) {
+ UDPHS->UDPHS_CLRINT = UDPHS_INTSTA_UPSTR_RES;
+ }
+
+ /* Start of Frame Interrupt */
+ if (intsta & UDPHS_INTSTA_INT_SOF) {
+ /* Process the SOF interrupt even in high speed mode.
+ The SOF and MICRO_SOF interrupt are never generated at the same
+ time. Instead, when in high speed mode there is 1 SOF
+ interrupt and 7 MICRO_SOF interrupts every 1ms. */
+
+#ifdef __RTX
+ UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_INT_SOF;
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_SOF, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_SOF_Event) {
+ USBD_P_SOF_Event();
+ }
+
+ UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_INT_SOF;
+#endif
+ }
+
+ /* Micro Frame Interrupt */
+ if (intsta & UDPHS_INTSTA_MICRO_SOF) {
+ if (USBD_HighSpeed == 1) {
+#ifdef __RTX
+ UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_MICRO_SOF;
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_SOF, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_SOF_Event) {
+ USBD_P_SOF_Event();
+ }
+
+ UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_MICRO_SOF;
+#endif
+
+ } else {
+ UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_MICRO_SOF;
+ }
+ }
+
+ /* Endpoint Interrupts */
+ for (n = 0; n <= USBD_EP_NUM; n++) {
+ if (intsta & (1 << (n + 8))) {
+ eptsta = UDPHS->UDPHS_EPT[n].UDPHS_EPTSTA; /* Read EP status */
+ eptsta_copy[n] = eptsta;
+
+ /* Data Packet Sent Interrupt */
+ if (eptsta & (1 << 10)) { /* Transmitted IN Data Complete Int */
+ UDPHS->UDPHS_EPT[n].UDPHS_EPTCLRSTA = (1 << 10); /* Tx IN Clear */
+#ifdef __RTX
+
+ if (USBD_RTX_EPTask[n]) { /* IN Packet */
+ isr_evt_set(USBD_EVT_IN, USBD_RTX_EPTask[n]);
+ }
+
+#else
+
+ if (USBD_P_EP[n]) {
+ USBD_P_EP[n](USBD_EVT_IN);
+ }
+
+#endif
+ }
+
+ /* Data Packet Received Interrupt */
+ if (eptsta & (1 << 9)) { /* Received OUT Data Interrupt */
+ UDPHS->UDPHS_IEN &= ~(1 << (n + 8)); /* Disable EP int until read*/
+#ifdef __RTX
+
+ if (USBD_RTX_EPTask[n]) { /* OUT Packet */
+ isr_evt_set(USBD_EVT_OUT, USBD_RTX_EPTask[n]);
+ }
+
+#else
+
+ if (USBD_P_EP[n]) {
+ USBD_P_EP[n](USBD_EVT_OUT);
+ }
+
+#endif
+ }
+
+ /* STALL Packet Sent Interrupt */
+ if (eptsta & (0x1 << 13)) { /* Stall Sent */
+ if ((UDPHS->UDPHS_EPT[n].UDPHS_EPTCFG & UDPHS_EPTCFG_EPT_TYPE_Msk) == UDPHS_EPTCFG_EPT_TYPE_CTRL8) {
+#ifdef __RTX
+
+ if (USBD_RTX_EPTask[n]) {
+ isr_evt_set(USBD_EVT_IN_STALL, USBD_RTX_EPTask[n]);
+ }
+
+#else
+
+ if (USBD_P_EP[n]) {
+ USBD_P_EP[n](USBD_EVT_IN_STALL);
+ }
+
+#endif
+ }
+
+ UDPHS->UDPHS_EPT[n].UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_STALL_SNT;
+ }
+
+ /* Setup Packet Received Interrupt */
+ if (eptsta & (0x1 << 12)) { /* Received SETUP Interrupt */
+ UDPHS->UDPHS_IEN &= ~(1 << (n + 8)); /* Disable EP int until read*/
+#ifdef __RTX
+
+ if (USBD_RTX_EPTask[n]) { /* SETUP Packet */
+ isr_evt_set(USBD_EVT_SETUP, USBD_RTX_EPTask[n]);
+ }
+
+#else
+
+ if (USBD_P_EP[n]) {
+ USBD_P_EP[n](USBD_EVT_SETUP);
+ }
+
+#endif
+ }
+ }
+ }
+
+ NVIC_EnableIRQ(UDPHS_IRQn);
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/usbhw_SAM3U.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/usbhw_SAM3U.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,52 @@ +/** + * @file usbhw_SAM3U.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __USBHW_H_SAM3U +#define __USBHW_H_SAM3U + + +/* USB Hardware Variables */ +extern volatile BOOL USB_HighSpeed; + +/* USB Hardware Functions */ +extern void USB_Init(void); +extern void USB_Connect(BOOL con); +extern void USB_Reset(void); +extern void USB_Suspend(void); +extern void USB_Resume(void); +extern void USB_WakeUp(void); +extern void USB_WakeUpCfg(BOOL cfg); +extern void USB_SetAddress(U32 adr); +extern void USB_Configure(BOOL cfg); +extern void USB_ConfigEP(USB_ENDPOINT_DESCRIPTOR *pEPD); +extern void USB_DirCtrlEP(U32 dir); +extern void USB_EnableEP(U32 EPNum); +extern void USB_DisableEP(U32 EPNum); +extern void USB_ResetEP(U32 EPNum); +extern void USB_SetStallEP(U32 EPNum); +extern void USB_ClrStallEP(U32 EPNum); +extern void USB_ClearEPBuf(U32 EPNum); +extern U32 USB_ReadEP(U32 EPNum, U8 *pData); +extern U32 USB_WriteEP(U32 EPNum, U8 *pData, U32 cnt); +extern U32 USB_GetFrame(void); + + +#endif /* __USBHW_H_SAM3U */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/atmel/sam3u2c/usbuser.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/atmel/sam3u2c/usbuser.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,77 @@ +/** + * @file usbuser.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __USBUSER_H +#define __USBUSER_H + + +/* USB Device Events Callback Functions */ +extern void USB_Power_Event(BOOL power); +extern void USB_Reset_Event(void); +extern void USB_Suspend_Event(void); +extern void USB_Resume_Event(void); +extern void USB_WakeUp_Event(void); +extern void USB_SOF_Event(void); +extern void USB_Error_Event(U32 error); + +/* USB Endpoint Callback Events */ +#define USB_EVT_SETUP 1 /* Setup Packet */ +#define USB_EVT_OUT 2 /* OUT Packet */ +#define USB_EVT_IN 3 /* IN Packet */ +#define USB_EVT_OUT_NAK 4 /* OUT Packet - Not Acknowledged */ +#define USB_EVT_IN_NAK 5 /* IN Packet - Not Acknowledged */ +#define USB_EVT_OUT_STALL 6 /* OUT Packet - Stalled */ +#define USB_EVT_IN_STALL 7 /* IN Packet - Stalled */ +#define USB_EVT_OUT_DMA_EOT 8 /* DMA OUT EP - End of Transfer */ +#define USB_EVT_IN_DMA_EOT 9 /* DMA IN EP - End of Transfer */ +#define USB_EVT_OUT_DMA_NDR 10 /* DMA OUT EP - New Descriptor Request */ +#define USB_EVT_IN_DMA_NDR 11 /* DMA IN EP - New Descriptor Request */ +#define USB_EVT_OUT_DMA_ERR 12 /* DMA OUT EP - Error */ +#define USB_EVT_IN_DMA_ERR 13 /* DMA IN EP - Error */ + +/* USB Endpoint Events Callback Pointers */ +extern void (* const USB_P_EP[16])(U32 event); + +/* USB Endpoint Events Callback Functions */ +extern void USB_EndPoint0(U32 event); +extern void USB_EndPoint1(U32 event); +extern void USB_EndPoint2(U32 event); +extern void USB_EndPoint3(U32 event); +extern void USB_EndPoint4(U32 event); +extern void USB_EndPoint5(U32 event); +extern void USB_EndPoint6(U32 event); +extern void USB_EndPoint7(U32 event); +extern void USB_EndPoint8(U32 event); +extern void USB_EndPoint9(U32 event); +extern void USB_EndPoint10(U32 event); +extern void USB_EndPoint11(U32 event); +extern void USB_EndPoint12(U32 event); +extern void USB_EndPoint13(U32 event); +extern void USB_EndPoint14(U32 event); +extern void USB_EndPoint15(U32 event); + +/* USB Core Events Callback Functions */ +extern void USB_Configure_Event(void); +extern void USB_Interface_Event(void); +extern void USB_Feature_Event(void); + + +#endif /* __USBUSER_H */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/device.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/device.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,48 @@ +/** + * @file cmsis.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef DEVICE_H +#define DEVICE_H + +#if defined (INTERFACE_K20D5) \ + || defined (INTERFACE_K26F) \ + || defined (INTERFACE_KL26Z) \ + || defined (INTERFACE_LPC55XX) +#include "fsl_device_registers.h" +#elif defined (INTERFACE_LPC11U35) +#include "LPC11Uxx.h" +#elif defined (INTERFACE_LPC4322) +#include "LPC43xx.h" +#elif defined (INTERFACE_MAX32620) +#include "max32620.h" +#elif defined (INTERFACE_MAX32625) +#include "max32625.h" +#elif defined (INTERFACE_SAM3U2C) +#include "sam3u2c.h" +#elif defined (INTERFACE_STM32F103XB) +#include "stm32f103xb.h" +#elif defined (INTERFACE_M48SSIDAE) +#include "M480.h" +#else +#error "CMSIS core headers needed" +#endif + +#endif // DEVICE_H
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/flash_blob.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/flash_blob.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,71 @@
+/**
+ * @file flash_blob.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * Copyright 2019, Cypress Semiconductor Corporation
+ * or a subsidiary of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef FLASH_BLOB_H
+#define FLASH_BLOB_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Flags for program_target
+enum {
+ kAlgoVerifyReturnsAddress = (1u << 0u), /*!< Verify function returns address if bit set */
+ kAlgoSingleInitType = (1u << 1u), /*!< The init function ignores the function code. */
+ kAlgoSkipChipErase = (1u << 2u), /*!< Skip region when erase.act action triggers. */
+};
+
+typedef struct __attribute__((__packed__)) {
+ uint32_t breakpoint;
+ uint32_t static_base;
+ uint32_t stack_pointer;
+} program_syscall_t;
+
+typedef struct __attribute__((__packed__)) {
+ const uint32_t init;
+ const uint32_t uninit;
+ const uint32_t erase_chip;
+ const uint32_t erase_sector;
+ const uint32_t program_page;
+ const uint32_t verify;
+ const program_syscall_t sys_call_s;
+ const uint32_t program_buffer;
+ const uint32_t algo_start;
+ const uint32_t algo_size;
+ const uint32_t *algo_blob;
+ const uint32_t program_buffer_size;
+ const uint32_t algo_flags; /*!< Combination of kAlgoVerifyReturnsAddress, kAlgoSingleInitType and kAlgoSkipChipErase*/
+} program_target_t;
+
+typedef struct __attribute__((__packed__)) {
+ const uint32_t start;
+ const uint32_t size;
+} sector_info_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/flash_hal.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/flash_hal.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,38 @@
+/**
+ * @file flash_hal.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef FLASH_HAL_H
+#define FLASH_HAL_H
+
+#include "FlashPrg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+uint32_t flash_program_page(uint32_t adr, uint32_t sz, uint8_t *buf);
+uint32_t flash_erase_sector(uint32_t addr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/iap/FlashDev.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/iap/FlashDev.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,40 @@
+/**
+ * @file FlashDev.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "FlashOS.h" // FlashOS Structures
+
+#define FLASH_DRV_VERS (0x0100+VERS) // Driver Version, do not modify!
+#define DEVICE_NAME "MKXX"
+
+struct FlashDevice const FlashDevice = {
+ FLASH_DRV_VERS, // Driver Version, do not modify!
+ DEVICE_NAME, // Device Name
+ ONCHIP, // Device Type
+ 0x00000000, // Device Start Address
+ 0x00000000, // Device Size
+ 1024, // Programming Page Size
+ 0, // Reserved, must be 0
+ 0xFF, // Initial Content of Erased Memory
+ 100, // Program Page Timeout 100 mSec
+ 3000, // Erase Sector Timeout 3000 mSec
+ {{0x000400, 0x000000}, // Sector Size 1kB
+ {SECTOR_END}}
+};
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/iap/FlashPrg.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/iap/FlashPrg.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,151 @@
+/**
+ * @file FlashPrg.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "FlashOS.h" // FlashOS Structures
+#include "fsl_flash.h"
+#include "string.h"
+#include "cortex_m.h"
+
+flash_config_t g_flash; //!< Storage for flash driver.
+
+uint32_t Init(uint32_t adr, uint32_t clk, uint32_t fnc)
+{
+ cortex_int_state_t state = cortex_int_get_and_disable();
+#if defined (WDOG)
+ /* Write 0xC520 to the unlock register */
+ WDOG->UNLOCK = 0xC520;
+ /* Followed by 0xD928 to complete the unlock */
+ WDOG->UNLOCK = 0xD928;
+ /* Clear the WDOGEN bit to disable the watchdog */
+ WDOG->STCTRLH &= ~WDOG_STCTRLH_WDOGEN_MASK;
+#else
+ SIM->COPC = 0x00u;
+#endif
+ cortex_int_restore(state);
+
+ return (FLASH_Init(&g_flash) != kStatus_Success);
+}
+
+
+/*
+ * De-Initialize Flash Programming Functions
+ * Parameter: fnc: Function Code (1 - Erase, 2 - Program, 3 - Verify)
+ * Return Value: 0 - OK, 1 - Failed
+ */
+
+uint32_t UnInit(uint32_t fnc)
+{
+ return (0);
+}
+
+
+/* Blank Check Block in Flash Memory
+ * Parameter: adr: Block Start Address
+ * sz: Block Size (in bytes)
+ * pat: Block Pattern
+ * Return Value: 0 - OK, 1 - Failed
+ */
+
+// int BlankCheck (unsigned long adr, unsigned long sz, unsigned char pat)
+// {
+// return (flash_verify_erase(&g_flash, adr, sz, kFlashMargin_Normal) != kStatus_Success);
+// }
+//
+// /*
+// * Verify Flash Contents
+// * Parameter: adr: Start Address
+// * sz: Size (in bytes)
+// * buf: Data
+// * Return Value: (adr+sz) - OK, Failed Address
+// */
+// unsigned long Verify (unsigned long adr, unsigned long sz, unsigned char *buf)
+// {
+// uint32_t failedAddress;
+// status_t status = flash_verify_program(&g_flash, adr, sz,
+// (const uint8_t *)buf, kFlashMargin_Normal,
+// &failedAddress, NULL);
+//
+// if (status == kStatus_Success)
+// {
+// // Finished without Errors
+// return (adr+sz);
+// }
+// else
+// {
+// return failedAddress;
+// }
+// }
+
+/*
+ * Erase complete Flash Memory
+ * Return Value: 0 - OK, 1 - Failed
+ */
+uint32_t EraseChip(void)
+{
+ cortex_int_state_t state = cortex_int_get_and_disable();
+ int status = FLASH_EraseAll(&g_flash, kFLASH_apiEraseKey);
+ if (status == kStatus_Success)
+ {
+ status = FLASH_VerifyEraseAll(&g_flash, kFLASH_marginValueNormal);
+ }
+ cortex_int_restore(state);
+ return status;
+}
+
+/*
+ * Erase Sector in Flash Memory
+ * Parameter: adr: Sector Address
+ * Return Value: 0 - OK, 1 - Failed
+ */
+uint32_t EraseSector(uint32_t adr)
+{
+ cortex_int_state_t state = cortex_int_get_and_disable();
+ int status = FLASH_Erase(&g_flash, adr, g_flash.PFlashSectorSize, kFLASH_apiEraseKey);
+ if (status == kStatus_Success)
+ {
+ status = FLASH_VerifyErase(&g_flash, adr, g_flash.PFlashSectorSize, kFLASH_marginValueNormal);
+ }
+ cortex_int_restore(state);
+ return status;
+}
+
+/*
+ * Program Page in Flash Memory
+ * Parameter: adr: Page Start Address
+ * sz: Page Size
+ * buf: Page Data
+ * Return Value: 0 - OK, 1 - Failed
+ */
+uint32_t ProgramPage(uint32_t adr, uint32_t sz, uint32_t *buf)
+{
+ cortex_int_state_t state = cortex_int_get_and_disable();
+ int status = FLASH_Program(&g_flash, adr, buf, sz);
+ if (status == kStatus_Success)
+ {
+ // Must use kFlashMargin_User, or kFlashMargin_Factory for verify program
+ status = FLASH_VerifyProgram(&g_flash, adr, sz,
+ buf, kFLASH_marginValueUser,
+ NULL, NULL);
+ }
+ cortex_int_restore(state);
+ return status;
+}
+
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/iap/fsl_common.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/iap/fsl_common.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_COMMON_H_
+#define _FSL_COMMON_H_
+
+// #include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include "fsl_device_registers.h"
+#include "util.h"
+
+/*!
+ * @addtogroup ksdk_common
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+// Redefine assert to DAPLink's assert utility for code size savings.
+#define assert(x) util_assert((x));
+
+/*! @brief Construct a status code value from a group and code number. */
+#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
+
+/*! @brief Construct the version number for drivers. */
+#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
+
+/* Debug console type definition. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */
+
+/*! @brief Status group numbers. */
+enum _status_groups
+{
+ kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */
+ kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */
+ kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */
+ kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */
+ kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */
+ kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */
+ kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */
+ kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */
+ kStatusGroup_UART = 10, /*!< Group number for UART status codes. */
+ kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */
+ kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */
+ kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */
+ kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/
+ kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/
+ kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/
+ kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */
+ kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */
+ kStatusGroup_SAI = 19, /*!< Group number for SAI status code */
+ kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */
+ kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */
+ kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */
+ kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */
+ kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */
+ kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */
+ kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */
+ kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */
+ kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */
+ kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */
+ kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */
+ kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */
+ kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */
+ kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */
+ kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */
+ kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */
+ kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */
+ kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */
+ kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
+ kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
+ kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */
+};
+
+/*! @brief Generic status return codes. */
+enum _generic_status
+{
+ kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
+ kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
+ kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
+ kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
+ kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
+ kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
+ kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
+};
+
+/*! @brief Type used for all status and error return values. */
+typedef int32_t status_t;
+
+// #include "fsl_clock.h"
+
+/*! @name Min/max macros */
+/* @{ */
+// #if !defined(MIN)
+// #define MIN(a, b) ((a) < (b) ? (a) : (b))
+// #endif
+//
+// #if !defined(MAX)
+// #define MAX(a, b) ((a) > (b) ? (a) : (b))
+// #endif
+// /* @} */
+//
+// /*! @brief Computes the number of elements in an array. */
+// #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/*! @name UINT16_MAX/UINT32_MAX value */
+/* @{ */
+#if !defined(UINT16_MAX)
+#define UINT16_MAX ((uint16_t)-1)
+#endif
+
+#if !defined(UINT32_MAX)
+#define UINT32_MAX ((uint32_t)-1)
+#endif
+/* @} */
+
+/*! @name Timer utilities */
+/* @{ */
+/*! Macro to convert a microsecond period to raw count value */
+#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)
+/*! Macro to convert a raw count value to microsecond */
+#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
+
+/*! Macro to convert a millisecond period to raw count value */
+#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
+/*! Macro to convert a raw count value to millisecond */
+#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
+/* @} */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Enable specific interrupt.
+ *
+ * Enable the interrupt not routed from intmux.
+ *
+ * @param interrupt The IRQ number.
+ */
+static inline void EnableIRQ(IRQn_Type interrupt)
+{
+#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0)
+ if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX)
+#endif
+ {
+ NVIC_EnableIRQ(interrupt);
+ }
+}
+
+/*!
+ * @brief Disable specific interrupt.
+ *
+ * Disable the interrupt not routed from intmux.
+ *
+ * @param interrupt The IRQ number.
+ */
+static inline void DisableIRQ(IRQn_Type interrupt)
+{
+#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0)
+ if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX)
+#endif
+ {
+ NVIC_DisableIRQ(interrupt);
+ }
+}
+
+/*!
+ * @brief Disable the global IRQ
+ *
+ * Disable the global interrupt and return the current primask register. User is required to provided the primask
+ * register for the EnableGlobalIRQ().
+ *
+ * @return Current primask value.
+ */
+static inline uint32_t DisableGlobalIRQ(void)
+{
+ uint32_t regPrimask = __get_PRIMASK();
+
+ __disable_irq();
+
+ return regPrimask;
+}
+
+/*!
+ * @brief Enaable the global IRQ
+ *
+ * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
+ * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
+ * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
+ *
+ * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
+ * DisableGlobalIRQ().
+ */
+static inline void EnableGlobalIRQ(uint32_t primask)
+{
+ __set_PRIMASK(primask);
+}
+
+/*!
+ * @brief install IRQ handler
+ *
+ * @param irq IRQ number
+ * @param irqHandler IRQ handler address
+ */
+void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_COMMON_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/iap/fsl_flash.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/iap/fsl_flash.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,2610 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_flash.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @name Misc utility defines
+ * @{
+ */
+#ifndef ALIGN_DOWN
+#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a))))
+#endif
+#ifndef ALIGN_UP
+#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a))))))
+#endif
+
+#define BYTES_JOIN_TO_WORD_1_3(x, y) ((((uint32_t)(x)&0xFFU) << 24) | ((uint32_t)(y)&0xFFFFFFU))
+#define BYTES_JOIN_TO_WORD_2_2(x, y) ((((uint32_t)(x)&0xFFFFU) << 16) | ((uint32_t)(y)&0xFFFFU))
+#define BYTES_JOIN_TO_WORD_3_1(x, y) ((((uint32_t)(x)&0xFFFFFFU) << 8) | ((uint32_t)(y)&0xFFU))
+#define BYTES_JOIN_TO_WORD_1_1_2(x, y, z) \
+ ((((uint32_t)(x)&0xFFU) << 24) | (((uint32_t)(y)&0xFFU) << 16) | ((uint32_t)(z)&0xFFFFU))
+#define BYTES_JOIN_TO_WORD_1_2_1(x, y, z) \
+ ((((uint32_t)(x)&0xFFU) << 24) | (((uint32_t)(y)&0xFFFFU) << 8) | ((uint32_t)(z)&0xFFU))
+#define BYTES_JOIN_TO_WORD_2_1_1(x, y, z) \
+ ((((uint32_t)(x)&0xFFFFU) << 16) | (((uint32_t)(y)&0xFFU) << 8) | ((uint32_t)(z)&0xFFU))
+#define BYTES_JOIN_TO_WORD_1_1_1_1(x, y, z, w) \
+ ((((uint32_t)(x)&0xFFU) << 24) | (((uint32_t)(y)&0xFFU) << 16) | (((uint32_t)(z)&0xFFU) << 8) | \
+ ((uint32_t)(w)&0xFFU))
+/*@}*/
+
+/*! @brief Data flash IFR map Field*/
+#if defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE
+#define DFLASH_IFR_READRESOURCE_START_ADDRESS 0x8003F8U
+#else /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */
+#define DFLASH_IFR_READRESOURCE_START_ADDRESS 0x8000F8U
+#endif
+
+/*!
+ * @name Reserved FlexNVM size (For a variety of purposes) defines
+ * @{
+ */
+#define FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED 0xFFFFFFFFU
+#define FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED 0xFFFFU
+/*@}*/
+
+/*!
+ * @name Flash Program Once Field defines
+ * @{
+ */
+#if defined(FSL_FEATURE_FLASH_IS_FTFA) && FSL_FEATURE_FLASH_IS_FTFA
+/* FTFA parts(eg. K80, KL80, L5K) support both 4-bytes and 8-bytes unit size */
+#define FLASH_PROGRAM_ONCE_MIN_ID_8BYTES \
+ 0x10U /* Minimum Index indcating one of Progam Once Fields which is accessed in 8-byte records */
+#define FLASH_PROGRAM_ONCE_MAX_ID_8BYTES \
+ 0x13U /* Maximum Index indcating one of Progam Once Fields which is accessed in 8-byte records */
+#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 1
+#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 1
+#elif defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE
+/* FTFE parts(eg. K65, KE18) only support 8-bytes unit size */
+#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 0
+#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 1
+#elif defined(FSL_FEATURE_FLASH_IS_FTFL) && FSL_FEATURE_FLASH_IS_FTFL
+/* FTFL parts(eg. K20) only support 4-bytes unit size */
+#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 1
+#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 0
+#endif
+/*@}*/
+
+/*!
+ * @name Flash security status defines
+ * @{
+ */
+#define FLASH_SECURITY_STATE_KEYEN 0x80U
+#define FLASH_SECURITY_STATE_UNSECURED 0x02U
+#define FLASH_NOT_SECURE 0x01U
+#define FLASH_SECURE_BACKDOOR_ENABLED 0x02U
+#define FLASH_SECURE_BACKDOOR_DISABLED 0x04U
+/*@}*/
+
+/*!
+ * @name Flash controller command numbers
+ * @{
+ */
+#define FTFx_VERIFY_BLOCK 0x00U /*!< RD1BLK*/
+#define FTFx_VERIFY_SECTION 0x01U /*!< RD1SEC*/
+#define FTFx_PROGRAM_CHECK 0x02U /*!< PGMCHK*/
+#define FTFx_READ_RESOURCE 0x03U /*!< RDRSRC*/
+#define FTFx_PROGRAM_LONGWORD 0x06U /*!< PGM4*/
+#define FTFx_PROGRAM_PHRASE 0x07U /*!< PGM8*/
+#define FTFx_ERASE_BLOCK 0x08U /*!< ERSBLK*/
+#define FTFx_ERASE_SECTOR 0x09U /*!< ERSSCR*/
+#define FTFx_PROGRAM_SECTION 0x0BU /*!< PGMSEC*/
+#define FTFx_VERIFY_ALL_BLOCK 0x40U /*!< RD1ALL*/
+#define FTFx_READ_ONCE 0x41U /*!< RDONCE or RDINDEX*/
+#define FTFx_PROGRAM_ONCE 0x43U /*!< PGMONCE or PGMINDEX*/
+#define FTFx_ERASE_ALL_BLOCK 0x44U /*!< ERSALL*/
+#define FTFx_SECURITY_BY_PASS 0x45U /*!< VFYKEY*/
+#define FTFx_SWAP_CONTROL 0x46U /*!< SWAP*/
+#define FTFx_ERASE_ALL_BLOCK_UNSECURE 0x49U /*!< ERSALLU*/
+#define FTFx_VERIFY_ALL_EXECUTE_ONLY_SEGMENT 0x4AU /*!< RD1XA*/
+#define FTFx_ERASE_ALL_EXECUTE_ONLY_SEGMENT 0x4BU /*!< ERSXA*/
+#define FTFx_PROGRAM_PARTITION 0x80U /*!< PGMPART)*/
+#define FTFx_SET_FLEXRAM_FUNCTION 0x81U /*!< SETRAM*/
+ /*@}*/
+
+/*!
+ * @name Common flash register info defines
+ * @{
+ */
+#if defined(FTFA)
+#define FTFx FTFA
+#define FTFx_BASE FTFA_BASE
+#define FTFx_FSTAT_CCIF_MASK FTFA_FSTAT_CCIF_MASK
+#define FTFx_FSTAT_RDCOLERR_MASK FTFA_FSTAT_RDCOLERR_MASK
+#define FTFx_FSTAT_ACCERR_MASK FTFA_FSTAT_ACCERR_MASK
+#define FTFx_FSTAT_FPVIOL_MASK FTFA_FSTAT_FPVIOL_MASK
+#define FTFx_FSTAT_MGSTAT0_MASK FTFA_FSTAT_MGSTAT0_MASK
+#define FTFx_FSEC_SEC_MASK FTFA_FSEC_SEC_MASK
+#define FTFx_FSEC_KEYEN_MASK FTFA_FSEC_KEYEN_MASK
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM
+#define FTFx_FCNFG_RAMRDY_MASK FTFA_FCNFG_RAMRDY_MASK
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM
+#define FTFx_FCNFG_EEERDY_MASK FTFA_FCNFG_EEERDY_MASK
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */
+#elif defined(FTFE)
+#define FTFx FTFE
+#define FTFx_BASE FTFE_BASE
+#define FTFx_FSTAT_CCIF_MASK FTFE_FSTAT_CCIF_MASK
+#define FTFx_FSTAT_RDCOLERR_MASK FTFE_FSTAT_RDCOLERR_MASK
+#define FTFx_FSTAT_ACCERR_MASK FTFE_FSTAT_ACCERR_MASK
+#define FTFx_FSTAT_FPVIOL_MASK FTFE_FSTAT_FPVIOL_MASK
+#define FTFx_FSTAT_MGSTAT0_MASK FTFE_FSTAT_MGSTAT0_MASK
+#define FTFx_FSEC_SEC_MASK FTFE_FSEC_SEC_MASK
+#define FTFx_FSEC_KEYEN_MASK FTFE_FSEC_KEYEN_MASK
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM
+#define FTFx_FCNFG_RAMRDY_MASK FTFE_FCNFG_RAMRDY_MASK
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM
+#define FTFx_FCNFG_EEERDY_MASK FTFE_FCNFG_EEERDY_MASK
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */
+#elif defined(FTFL)
+#define FTFx FTFL
+#define FTFx_BASE FTFL_BASE
+#define FTFx_FSTAT_CCIF_MASK FTFL_FSTAT_CCIF_MASK
+#define FTFx_FSTAT_RDCOLERR_MASK FTFL_FSTAT_RDCOLERR_MASK
+#define FTFx_FSTAT_ACCERR_MASK FTFL_FSTAT_ACCERR_MASK
+#define FTFx_FSTAT_FPVIOL_MASK FTFL_FSTAT_FPVIOL_MASK
+#define FTFx_FSTAT_MGSTAT0_MASK FTFL_FSTAT_MGSTAT0_MASK
+#define FTFx_FSEC_SEC_MASK FTFL_FSEC_SEC_MASK
+#define FTFx_FSEC_KEYEN_MASK FTFL_FSEC_KEYEN_MASK
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM
+#define FTFx_FCNFG_RAMRDY_MASK FTFL_FCNFG_RAMRDY_MASK
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM
+#define FTFx_FCNFG_EEERDY_MASK FTFL_FCNFG_EEERDY_MASK
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */
+#else
+#error "Unknown flash controller"
+#endif
+/*@}*/
+
+/*!
+ * @brief Enumeration for access segment property.
+ */
+enum _flash_access_segment_property
+{
+ kFLASH_accessSegmentBase = 256UL,
+};
+
+/*!
+ * @brief Enumeration for acceleration ram property.
+ */
+enum _flash_acceleration_ram_property
+{
+ kFLASH_accelerationRamSize = 0x400U
+};
+
+/*!
+ * @brief Enumeration for flash config area.
+ */
+enum _flash_config_area_range
+{
+ kFLASH_configAreaStart = 0x400U,
+ kFLASH_configAreaEnd = 0x40FU
+};
+
+/*! @brief program Flash block base address*/
+#define PFLASH_BLOCK_BASE 0x00U
+
+/*! @brief Total flash region count*/
+#define FSL_FEATURE_FTFx_REGION_COUNT (32U)
+
+/*!
+ * @name Flash register access type defines
+ * @{
+ */
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+#define FTFx_REG_ACCESS_TYPE volatile uint8_t *
+#define FTFx_REG32_ACCESS_TYPE volatile uint32_t *
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+ /*@}*/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+/*! @brief Copy flash_run_command() to RAM*/
+static void copy_flash_run_command(uint8_t *flashRunCommand);
+/*! @brief Copy flash_cache_clear_command() to RAM*/
+static void copy_flash_cache_clear_command(uint8_t *flashCacheClearCommand);
+/*! @brief Check whether flash execute-in-ram functions are ready*/
+static status_t flash_check_execute_in_ram_function_info(flash_config_t *config);
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+
+/*! @brief Internal function Flash command sequence. Called by driver APIs only*/
+static status_t flash_command_sequence(flash_config_t *config);
+
+/*! @brief Perform the cache clear to the flash*/
+void flash_cache_clear(flash_config_t *config);
+
+/*! @brief Validates the range and alignment of the given address range.*/
+static status_t flash_check_range(flash_config_t *config,
+ uint32_t startAddress,
+ uint32_t lengthInBytes,
+ uint32_t alignmentBaseline);
+/*! @brief Gets the right address, sector and block size of current flash type which is indicated by address.*/
+static status_t flash_get_matched_operation_info(flash_config_t *config,
+ uint32_t address,
+ flash_operation_config_t *info);
+/*! @brief Validates the given user key for flash erase APIs.*/
+static status_t flash_check_user_key(uint32_t key);
+
+// #if FLASH_SSD_IS_FLEXNVM_ENABLED
+// /*! @brief Updates FlexNVM memory partition status according to data flash 0 IFR.*/
+// static status_t flash_update_flexnvm_memory_partition_status(flash_config_t *config);
+// #endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
+
+// #if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD
+// /*! @brief Validates the range of the given resource address.*/
+// static status_t flash_check_resource_range(uint32_t start,
+// uint32_t lengthInBytes,
+// uint32_t alignmentBaseline,
+// flash_read_resource_option_t option);
+// #endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */
+//
+// #if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD
+// /*! @brief Validates the gived swap control option.*/
+// static status_t flash_check_swap_control_option(flash_swap_control_option_t option);
+// #endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */
+//
+// #if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP
+// /*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/
+// static status_t flash_validate_swap_indicator_address(flash_config_t *config, uint32_t address);
+// #endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */
+//
+// #if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
+// /*! @brief Validates the gived flexram function option.*/
+// static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option);
+// #endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Access to FTFx->FCCOB */
+#if defined(FSL_FEATURE_FLASH_IS_FTFA) && FSL_FEATURE_FLASH_IS_FTFA
+volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFA->FCCOB3;
+#elif defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE
+volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFE->FCCOB3;
+#elif defined(FSL_FEATURE_FLASH_IS_FTFL) && FSL_FEATURE_FLASH_IS_FTFL
+volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFL->FCCOB3;
+#else
+#error "Unknown flash controller"
+#endif
+
+/*! @brief Access to FTFx->FPROT */
+#if defined(FSL_FEATURE_FLASH_IS_FTFA) && FSL_FEATURE_FLASH_IS_FTFA
+volatile uint32_t *const kFPROT = (volatile uint32_t *)&FTFA->FPROT3;
+#elif defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE
+volatile uint32_t *const kFPROT = (volatile uint32_t *)&FTFE->FPROT3;
+#elif defined(FSL_FEATURE_FLASH_IS_FTFL) && FSL_FEATURE_FLASH_IS_FTFL
+volatile uint32_t *const kFPROT = (volatile uint32_t *)&FTFL->FPROT3;
+#else
+#error "Unknown flash controller"
+#endif
+
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+/*! @brief A function pointer used to point to relocated flash_run_command() */
+static void (*callFlashRunCommand)(FTFx_REG_ACCESS_TYPE ftfx_fstat);
+/*! @brief A function pointer used to point to relocated flash_cache_clear_command() */
+static void (*callFlashCacheClearCommand)(FTFx_REG32_ACCESS_TYPE ftfx_reg);
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+
+#if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED)
+/*! @brief A static buffer used to hold flash_run_command() */
+static uint8_t s_flashRunCommand[kFLASH_executeInRamFunctionMaxSize];
+/*! @brief A static buffer used to hold flash_cache_clear_command() */
+static uint8_t s_flashCacheClearCommand[kFLASH_executeInRamFunctionMaxSize];
+/*! @brief Flash execute-in-ram function information */
+static flash_execute_in_ram_function_config_t s_flashExecuteInRamFunctionInfo;
+#endif
+
+/*!
+ * @brief Table of pflash sizes.
+ *
+ * The index into this table is the value of the SIM_FCFG1.PFSIZE bitfield.
+ *
+ * The values in this table have been right shifted 10 bits so that they will all fit within
+ * an 16-bit integer. To get the actual flash density, you must left shift the looked up value
+ * by 10 bits.
+ *
+ * Elements of this table have a value of 0 in cases where the PFSIZE bitfield value is
+ * reserved.
+ *
+ * Code to use the table:
+ * @code
+ * uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT;
+ * flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10;
+ * @endcode
+ */
+const uint16_t kPFlashDensities[] = {
+ 8, /* 0x0 - 8192, 8KB */
+ 16, /* 0x1 - 16384, 16KB */
+ 24, /* 0x2 - 24576, 24KB */
+ 32, /* 0x3 - 32768, 32KB */
+ 48, /* 0x4 - 49152, 48KB */
+ 64, /* 0x5 - 65536, 64KB */
+ 96, /* 0x6 - 98304, 96KB */
+ 128, /* 0x7 - 131072, 128KB */
+ 192, /* 0x8 - 196608, 192KB */
+ 256, /* 0x9 - 262144, 256KB */
+ 384, /* 0xa - 393216, 384KB */
+ 512, /* 0xb - 524288, 512KB */
+ 768, /* 0xc - 786432, 768KB */
+ 1024, /* 0xd - 1048576, 1MB */
+ 1536, /* 0xe - 1572864, 1.5MB */
+ /* 2048, 0xf - 2097152, 2MB */
+};
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+status_t FLASH_Init(flash_config_t *config)
+{
+ uint32_t flashDensity;
+
+ if (config == NULL)
+ {
+ return kStatus_FLASH_InvalidArgument;
+ }
+
+ /* calculate the flash density from SIM_FCFG1.PFSIZE */
+ uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT;
+ /* PFSIZE=0xf means that on customer parts the IFR was not correctly programmed.
+ * We just use the pre-defined flash size in feature file here to support pre-production parts */
+ if (pfsize == 0xf)
+ {
+ flashDensity = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE;
+ }
+ else
+ {
+ flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10;
+ }
+
+ /* fill out a few of the structure members */
+ config->PFlashBlockBase = PFLASH_BLOCK_BASE;
+ config->PFlashTotalSize = flashDensity;
+ config->PFlashBlockCount = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT;
+ config->PFlashSectorSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE;
+
+#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL
+ config->PFlashAccessSegmentSize = kFLASH_accessSegmentBase << FTFx->FACSS;
+ config->PFlashAccessSegmentCount = FTFx->FACSN;
+#else
+ config->PFlashAccessSegmentSize = 0;
+ config->PFlashAccessSegmentCount = 0;
+#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */
+
+ config->PFlashCallback = NULL;
+
+/* copy required flash commands to RAM */
+#if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED)
+ if (kStatus_FLASH_Success != flash_check_execute_in_ram_function_info(config))
+ {
+ s_flashExecuteInRamFunctionInfo.activeFunctionCount = 0;
+ s_flashExecuteInRamFunctionInfo.flashRunCommand = s_flashRunCommand;
+ s_flashExecuteInRamFunctionInfo.flashCacheClearCommand = s_flashCacheClearCommand;
+ config->flashExecuteInRamFunctionInfo = &s_flashExecuteInRamFunctionInfo.activeFunctionCount;
+ FLASH_PrepareExecuteInRamFunctions(config);
+ }
+#endif
+
+ config->FlexRAMBlockBase = FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS;
+ config->FlexRAMTotalSize = FSL_FEATURE_FLASH_FLEX_RAM_SIZE;
+
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+ {
+ status_t returnCode;
+ config->DFlashBlockBase = FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS;
+ returnCode = flash_update_flexnvm_memory_partition_status(config);
+ if (returnCode != kStatus_FLASH_Success)
+ {
+ return returnCode;
+ }
+ }
+#endif
+
+ return kStatus_FLASH_Success;
+}
+
+status_t FLASH_SetCallback(flash_config_t *config, flash_callback_t callback)
+{
+ if (config == NULL)
+ {
+ return kStatus_FLASH_InvalidArgument;
+ }
+
+ config->PFlashCallback = callback;
+
+ return kStatus_FLASH_Success;
+}
+
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+status_t FLASH_PrepareExecuteInRamFunctions(flash_config_t *config)
+{
+ flash_execute_in_ram_function_config_t *flashExecuteInRamFunctionInfo;
+
+ if (config == NULL)
+ {
+ return kStatus_FLASH_InvalidArgument;
+ }
+
+ flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo;
+
+ copy_flash_run_command(flashExecuteInRamFunctionInfo->flashRunCommand);
+ copy_flash_cache_clear_command(flashExecuteInRamFunctionInfo->flashCacheClearCommand);
+ flashExecuteInRamFunctionInfo->activeFunctionCount = kFLASH_executeInRamFunctionTotalNum;
+
+ return kStatus_FLASH_Success;
+}
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+
+status_t FLASH_EraseAll(flash_config_t *config, uint32_t key)
+{
+ status_t returnCode;
+
+ if (config == NULL)
+ {
+ return kStatus_FLASH_InvalidArgument;
+ }
+
+ /* preparing passing parameter to erase all flash blocks */
+ kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_BLOCK, 0xFFFFFFU);
+
+ /* Validate the user key */
+ returnCode = flash_check_user_key(key);
+ if (returnCode)
+ {
+ return returnCode;
+ }
+
+ /* calling flash command sequence function to execute the command */
+ returnCode = flash_command_sequence(config);
+
+ flash_cache_clear(config);
+
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+ /* Data flash IFR will be erased by erase all command, so we need to
+ * update FlexNVM memory partition status synchronously */
+ if (returnCode == kStatus_FLASH_Success)
+ {
+ returnCode = flash_update_flexnvm_memory_partition_status(config);
+ }
+#endif
+
+ return returnCode;
+}
+
+status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key)
+{
+ uint32_t sectorSize;
+ flash_operation_config_t flashInfo;
+ uint32_t endAddress; /* storing end address */
+ uint32_t numberOfSectors; /* number of sectors calculated by endAddress */
+ status_t returnCode;
+
+ flash_get_matched_operation_info(config, start, &flashInfo);
+
+ /* Check the supplied address range. */
+ returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.sectorCmdAddressAligment);
+ if (returnCode)
+ {
+ return returnCode;
+ }
+
+ start = flashInfo.convertedAddress;
+ sectorSize = flashInfo.activeSectorSize;
+
+ /* calculating Flash end address */
+ endAddress = start + lengthInBytes - 1;
+
+ /* re-calculate the endAddress and align it to the start of the next sector
+ * which will be used in the comparison below */
+ if (endAddress % sectorSize)
+ {
+ numberOfSectors = endAddress / sectorSize + 1;
+ endAddress = numberOfSectors * sectorSize - 1;
+ }
+
+ /* the start address will increment to the next sector address
+ * until it reaches the endAdddress */
+ while (start <= endAddress)
+ {
+ /* preparing passing parameter to erase a flash block */
+ kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_SECTOR, start);
+
+ /* Validate the user key */
+ returnCode = flash_check_user_key(key);
+ if (returnCode)
+ {
+ return returnCode;
+ }
+
+ /* calling flash command sequence function to execute the command */
+ returnCode = flash_command_sequence(config);
+
+ /* calling flash callback function if it is available */
+ if (config->PFlashCallback)
+ {
+ config->PFlashCallback();
+ }
+
+ /* checking the success of command execution */
+ if (kStatus_FLASH_Success != returnCode)
+ {
+ break;
+ }
+ else
+ {
+ /* Increment to the next sector */
+ start += sectorSize;
+ }
+ }
+
+ flash_cache_clear(config);
+
+ return (returnCode);
+}
+
+// #if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD
+// status_t FLASH_EraseAllUnsecure(flash_config_t *config, uint32_t key)
+// {
+// status_t returnCode;
+//
+// if (config == NULL)
+// {
+// return kStatus_FLASH_InvalidArgument;
+// }
+//
+// /* Prepare passing parameter to erase all flash blocks (unsecure). */
+// kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_BLOCK_UNSECURE, 0xFFFFFFU);
+//
+// /* Validate the user key */
+// returnCode = flash_check_user_key(key);
+// if (returnCode)
+// {
+// return returnCode;
+// }
+//
+// /* calling flash command sequence function to execute the command */
+// returnCode = flash_command_sequence(config);
+//
+// flash_cache_clear(config);
+//
+// #if FLASH_SSD_IS_FLEXNVM_ENABLED
+// /* Data flash IFR will be erased by erase all unsecure command, so we need to
+// * update FlexNVM memory partition status synchronously */
+// if (returnCode == kStatus_FLASH_Success)
+// {
+// returnCode = flash_update_flexnvm_memory_partition_status(config);
+// }
+// #endif
+//
+// return returnCode;
+// }
+// #endif /* FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD */
+//
+// status_t FLASH_EraseAllExecuteOnlySegments(flash_config_t *config, uint32_t key)
+// {
+// status_t returnCode;
+//
+// if (config == NULL)
+// {
+// return kStatus_FLASH_InvalidArgument;
+// }
+//
+// /* preparing passing parameter to erase all execute-only segments
+// * 1st element for the FCCOB register */
+// kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_EXECUTE_ONLY_SEGMENT, 0xFFFFFFU);
+//
+// /* Validate the user key */
+// returnCode = flash_check_user_key(key);
+// if (returnCode)
+// {
+// return returnCode;
+// }
+//
+// /* calling flash command sequence function to execute the command */
+// returnCode = flash_command_sequence(config);
+//
+// flash_cache_clear(config);
+//
+// return returnCode;
+// }
+
+status_t FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes)
+{
+ status_t returnCode;
+ flash_operation_config_t flashInfo;
+
+ if (src == NULL)
+ {
+ return kStatus_FLASH_InvalidArgument;
+ }
+
+ flash_get_matched_operation_info(config, start, &flashInfo);
+
+ /* Check the supplied address range. */
+ returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.blockWriteUnitSize);
+ if (returnCode)
+ {
+ return returnCode;
+ }
+
+ start = flashInfo.convertedAddress;
+
+ while (lengthInBytes > 0)
+ {
+ /* preparing passing parameter to program the flash block */
+ kFCCOBx[1] = *src++;
+ if (4 == flashInfo.blockWriteUnitSize)
+ {
+ kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_LONGWORD, start);
+ }
+ else if (8 == flashInfo.blockWriteUnitSize)
+ {
+ kFCCOBx[2] = *src++;
+ kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_PHRASE, start);
+ }
+ else
+ {
+ }
+
+ /* calling flash command sequence function to execute the command */
+ returnCode = flash_command_sequence(config);
+
+ /* calling flash callback function if it is available */
+ if (config->PFlashCallback)
+ {
+ config->PFlashCallback();
+ }
+
+ /* checking for the success of command execution */
+ if (kStatus_FLASH_Success != returnCode)
+ {
+ break;
+ }
+ else
+ {
+ /* update start address for next iteration */
+ start += flashInfo.blockWriteUnitSize;
+
+ /* update lengthInBytes for next iteration */
+ lengthInBytes -= flashInfo.blockWriteUnitSize;
+ }
+ }
+
+ flash_cache_clear(config);
+
+ return (returnCode);
+}
+
+// status_t FLASH_ProgramOnce(flash_config_t *config, uint32_t index, uint32_t *src, uint32_t lengthInBytes)
+// {
+// status_t returnCode;
+//
+// if ((config == NULL) || (src == NULL))
+// {
+// return kStatus_FLASH_InvalidArgument;
+// }
+//
+// /* pass paramters to FTFx */
+// kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_PROGRAM_ONCE, index, 0xFFFFU);
+//
+// kFCCOBx[1] = *src;
+//
+// /* Note: Have to seperate the first index from the rest if it equals 0
+// * to avoid a pointless comparison of unsigned int to 0 compiler warning */
+// #if FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT
+// #if FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT
+// if (((index == FLASH_PROGRAM_ONCE_MIN_ID_8BYTES) ||
+// /* Range check */
+// ((index >= FLASH_PROGRAM_ONCE_MIN_ID_8BYTES + 1) && (index <= FLASH_PROGRAM_ONCE_MAX_ID_8BYTES))) &&
+// (lengthInBytes == 8))
+// #endif /* FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT */
+// {
+// kFCCOBx[2] = *(src + 1);
+// }
+// #endif /* FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT */
+//
+// /* calling flash command sequence function to execute the command */
+// returnCode = flash_command_sequence(config);
+//
+// flash_cache_clear(config);
+//
+// return returnCode;
+// }
+//
+// #if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD
+// status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes)
+// {
+// status_t returnCode;
+// uint32_t sectorSize;
+// flash_operation_config_t flashInfo;
+// #if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
+// bool needSwitchFlexRamMode = false;
+// #endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
+//
+// if (src == NULL)
+// {
+// return kStatus_FLASH_InvalidArgument;
+// }
+//
+// flash_get_matched_operation_info(config, start, &flashInfo);
+//
+// /* Check the supplied address range. */
+// returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.sectionCmdAddressAligment);
+// if (returnCode)
+// {
+// return returnCode;
+// }
+//
+// start = flashInfo.convertedAddress;
+// sectorSize = flashInfo.activeSectorSize;
+//
+// #if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
+// /* Switch function of FlexRAM if needed */
+// if (!(FTFx->FCNFG & FTFx_FCNFG_RAMRDY_MASK))
+// {
+// needSwitchFlexRamMode = true;
+//
+// returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableAsRam);
+// if (returnCode != kStatus_FLASH_Success)
+// {
+// return kStatus_FLASH_SetFlexramAsRamError;
+// }
+// }
+// #endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
+//
+// while (lengthInBytes > 0)
+// {
+// /* Make sure the write operation doesn't span two sectors */
+// uint32_t endAddressOfCurrentSector = ALIGN_UP(start, sectorSize);
+// uint32_t lengthTobeProgrammedOfCurrentSector;
+// uint32_t currentOffset = 0;
+//
+// if (endAddressOfCurrentSector == start)
+// {
+// endAddressOfCurrentSector += sectorSize;
+// }
+//
+// if (lengthInBytes + start > endAddressOfCurrentSector)
+// {
+// lengthTobeProgrammedOfCurrentSector = endAddressOfCurrentSector - start;
+// }
+// else
+// {
+// lengthTobeProgrammedOfCurrentSector = lengthInBytes;
+// }
+//
+// /* Program Current Sector */
+// while (lengthTobeProgrammedOfCurrentSector > 0)
+// {
+// /* Make sure the program size doesn't exceeds Acceleration RAM size */
+// uint32_t programSizeOfCurrentPass;
+// uint32_t numberOfPhases;
+//
+// if (lengthTobeProgrammedOfCurrentSector > kFLASH_accelerationRamSize)
+// {
+// programSizeOfCurrentPass = kFLASH_accelerationRamSize;
+// }
+// else
+// {
+// programSizeOfCurrentPass = lengthTobeProgrammedOfCurrentSector;
+// }
+//
+// /* Copy data to FlexRAM */
+// memcpy((void *)FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS, src + currentOffset / 4, programSizeOfCurrentPass);
+// /* Set start address of the data to be programmed */
+// kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_SECTION, start + currentOffset);
+// /* Set program size in terms of FEATURE_FLASH_SECTION_CMD_ADDRESS_ALIGMENT */
+// numberOfPhases = programSizeOfCurrentPass / flashInfo.sectionCmdAddressAligment;
+//
+// kFCCOBx[1] = BYTES_JOIN_TO_WORD_2_2(numberOfPhases, 0xFFFFU);
+//
+// /* Peform command sequence */
+// returnCode = flash_command_sequence(config);
+//
+// /* calling flash callback function if it is available */
+// if (config->PFlashCallback)
+// {
+// config->PFlashCallback();
+// }
+//
+// if (returnCode != kStatus_FLASH_Success)
+// {
+// flash_cache_clear(config);
+// return returnCode;
+// }
+//
+// lengthTobeProgrammedOfCurrentSector -= programSizeOfCurrentPass;
+// currentOffset += programSizeOfCurrentPass;
+// }
+//
+// src += currentOffset / 4;
+// start += currentOffset;
+// lengthInBytes -= currentOffset;
+// }
+//
+// flash_cache_clear(config);
+//
+// #if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
+// /* Restore function of FlexRAM if needed. */
+// if (needSwitchFlexRamMode)
+// {
+// returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableForEeprom);
+// if (returnCode != kStatus_FLASH_Success)
+// {
+// return kStatus_FLASH_RecoverFlexramAsEepromError;
+// }
+// }
+// #endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
+//
+// return returnCode;
+// }
+// #endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD */
+//
+// #if FLASH_SSD_IS_FLEXNVM_ENABLED
+// status_t FLASH_EepromWrite(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes)
+// {
+// status_t returnCode;
+// bool needSwitchFlexRamMode = false;
+//
+// if (config == NULL)
+// {
+// return kStatus_FLASH_InvalidArgument;
+// }
+//
+// /* Validates the range of the given address */
+// if ((start < config->FlexRAMBlockBase) ||
+// ((start + lengthInBytes) > (config->FlexRAMBlockBase + config->EEpromTotalSize)))
+// {
+// return kStatus_FLASH_AddressError;
+// }
+//
+// returnCode = kStatus_FLASH_Success;
+//
+// /* Switch function of FlexRAM if needed */
+// if (!(FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK))
+// {
+// needSwitchFlexRamMode = true;
+//
+// returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableForEeprom);
+// if (returnCode != kStatus_FLASH_Success)
+// {
+// return kStatus_FLASH_SetFlexramAsEepromError;
+// }
+// }
+//
+// /* Write data to FlexRAM when it is used as EEPROM emulator */
+// while (lengthInBytes > 0)
+// {
+// if ((!(start & 0x3U)) && (lengthInBytes >= 4))
+// {
+// *(uint32_t *)start = *(uint32_t *)src;
+// start += 4;
+// src += 4;
+// lengthInBytes -= 4;
+// }
+// else if ((!(start & 0x1U)) && (lengthInBytes >= 2))
+// {
+// *(uint16_t *)start = *(uint16_t *)src;
+// start += 2;
+// src += 2;
+// lengthInBytes -= 2;
+// }
+// else
+// {
+// *(uint8_t *)start = *src;
+// start += 1;
+// src += 1;
+// lengthInBytes -= 1;
+// }
+// /* Wait till EEERDY bit is set */
+// while (!(FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK))
+// {
+// }
+//
+// /* Check for protection violation error */
+// if (FTFx->FSTAT & FTFx_FSTAT_FPVIOL_MASK)
+// {
+// return kStatus_FLASH_ProtectionViolation;
+// }
+// }
+//
+// /* Switch function of FlexRAM if needed */
+// if (needSwitchFlexRamMode)
+// {
+// returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableAsRam);
+// if (returnCode != kStatus_FLASH_Success)
+// {
+// return kStatus_FLASH_RecoverFlexramAsRamError;
+// }
+// }
+//
+// return returnCode;
+// }
+// #endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
+//
+// #if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD
+// status_t FLASH_ReadResource(
+// flash_config_t *config, uint32_t start, uint32_t *dst, uint32_t lengthInBytes, flash_read_resource_option_t option)
+// {
+// status_t returnCode;
+// flash_operation_config_t flashInfo;
+//
+// if ((config == NULL) || (dst == NULL))
+// {
+// return kStatus_FLASH_InvalidArgument;
+// }
+//
+// flash_get_matched_operation_info(config, start, &flashInfo);
+//
+// /* Check the supplied address range. */
+// returnCode = flash_check_resource_range(start, lengthInBytes, flashInfo.resourceCmdAddressAligment, option);
+// if (returnCode != kStatus_FLASH_Success)
+// {
+// return returnCode;
+// }
+//
+// while (lengthInBytes > 0)
+// {
+// /* preparing passing parameter */
+// kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_READ_RESOURCE, start);
+// if (flashInfo.resourceCmdAddressAligment == 4)
+// {
+// kFCCOBx[2] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU);
+// }
+// else if (flashInfo.resourceCmdAddressAligment == 8)
+// {
+// kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU);
+// }
+// else
+// {
+// }
+//
+// /* calling flash command sequence function to execute the command */
+// returnCode = flash_command_sequence(config);
+//
+// if (kStatus_FLASH_Success != returnCode)
+// {
+// break;
+// }
+//
+// /* fetch data */
+// *dst++ = kFCCOBx[1];
+// if (flashInfo.resourceCmdAddressAligment == 8)
+// {
+// *dst++ = kFCCOBx[2];
+// }
+// /* update start address for next iteration */
+// start += flashInfo.resourceCmdAddressAligment;
+// /* update lengthInBytes for next iteration */
+// lengthInBytes -= flashInfo.resourceCmdAddressAligment;
+// }
+//
+// return (returnCode);
+// }
+// #endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */
+//
+// status_t FLASH_ReadOnce(flash_config_t *config, uint32_t index, uint32_t *dst, uint32_t lengthInBytes)
+// {
+// status_t returnCode;
+//
+// if ((config == NULL) || (dst == NULL))
+// {
+// return kStatus_FLASH_InvalidArgument;
+// }
+//
+// /* pass paramters to FTFx */
+// kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_READ_ONCE, index, 0xFFFFU);
+//
+// /* calling flash command sequence function to execute the command */
+// returnCode = flash_command_sequence(config);
+//
+// if (kStatus_FLASH_Success == returnCode)
+// {
+// *dst = kFCCOBx[1];
+// /* Note: Have to seperate the first index from the rest if it equals 0
+// * to avoid a pointless comparison of unsigned int to 0 compiler warning */
+// #if FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT
+// #if FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT
+// if (((index == FLASH_PROGRAM_ONCE_MIN_ID_8BYTES) ||
+// /* Range check */
+// ((index >= FLASH_PROGRAM_ONCE_MIN_ID_8BYTES + 1) && (index <= FLASH_PROGRAM_ONCE_MAX_ID_8BYTES))) &&
+// (lengthInBytes == 8))
+// #endif /* FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT */
+// {
+// *(dst + 1) = kFCCOBx[2];
+// }
+// #endif /* FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT */
+// }
+//
+// return returnCode;
+// }
+//
+// status_t FLASH_GetSecurityState(flash_config_t *config, flash_security_state_t *state)
+// {
+// /* store data read from flash register */
+// uint8_t registerValue;
+//
+// if ((config == NULL) || (state == NULL))
+// {
+// return kStatus_FLASH_InvalidArgument;
+// }
+//
+// /* Get flash security register value */
+// registerValue = FTFx->FSEC;
+//
+// /* check the status of the flash security bits in the security register */
+// if (FLASH_SECURITY_STATE_UNSECURED == (registerValue & FTFx_FSEC_SEC_MASK))
+// {
+// /* Flash in unsecured state */
+// *state = kFLASH_securityStateNotSecure;
+// }
+// else
+// {
+// /* Flash in secured state
+// * check for backdoor key security enable bit */
+// if (FLASH_SECURITY_STATE_KEYEN == (registerValue & FTFx_FSEC_KEYEN_MASK))
+// {
+// /* Backdoor key security enabled */
+// *state = kFLASH_securityStateBackdoorEnabled;
+// }
+// else
+// {
+// /* Backdoor key security disabled */
+// *state = kFLASH_securityStateBackdoorDisabled;
+// }
+// }
+//
+// return (kStatus_FLASH_Success);
+// }
+//
+// status_t FLASH_SecurityBypass(flash_config_t *config, const uint8_t *backdoorKey)
+// {
+// uint8_t registerValue; /* registerValue */
+// status_t returnCode; /* return code variable */
+//
+// if ((config == NULL) || (backdoorKey == NULL))
+// {
+// return kStatus_FLASH_InvalidArgument;
+// }
+//
+// /* set the default return code as kStatus_Success */
+// returnCode = kStatus_FLASH_Success;
+//
+// /* Get flash security register value */
+// registerValue = FTFx->FSEC;
+//
+// /* Check to see if flash is in secure state (any state other than 0x2)
+// * If not, then skip this since flash is not secure */
+// if (0x02 != (registerValue & 0x03))
+// {
+// /* preparing passing parameter to erase a flash block */
+// kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_SECURITY_BY_PASS, 0xFFFFFFU);
+// kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_1_1_1(backdoorKey[0], backdoorKey[1], backdoorKey[2], backdoorKey[3]);
+// kFCCOBx[2] = BYTES_JOIN_TO_WORD_1_1_1_1(backdoorKey[4], backdoorKey[5], backdoorKey[6], backdoorKey[7]);
+//
+// /* calling flash command sequence function to execute the command */
+// returnCode = flash_command_sequence(config);
+// }
+//
+// return (returnCode);
+// }
+
+status_t FLASH_VerifyEraseAll(flash_config_t *config, flash_margin_value_t margin)
+{
+ if (config == NULL)
+ {
+ return kStatus_FLASH_InvalidArgument;
+ }
+
+ /* preparing passing parameter to verify all block command */
+ kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_VERIFY_ALL_BLOCK, margin, 0xFFFFU);
+
+ /* calling flash command sequence function to execute the command */
+ return flash_command_sequence(config);
+}
+
+status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, flash_margin_value_t margin)
+{
+ /* Check arguments. */
+ uint32_t blockSize;
+ flash_operation_config_t flashInfo;
+ uint32_t nextBlockStartAddress;
+ uint32_t remainingBytes;
+ status_t returnCode;
+
+ flash_get_matched_operation_info(config, start, &flashInfo);
+
+ returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.sectionCmdAddressAligment);
+ if (returnCode)
+ {
+ return returnCode;
+ }
+
+ flash_get_matched_operation_info(config, start, &flashInfo);
+ start = flashInfo.convertedAddress;
+ blockSize = flashInfo.activeBlockSize;
+
+ nextBlockStartAddress = ALIGN_UP(start, blockSize);
+ if (nextBlockStartAddress == start)
+ {
+ nextBlockStartAddress += blockSize;
+ }
+
+ remainingBytes = lengthInBytes;
+
+ while (remainingBytes)
+ {
+ uint32_t numberOfPhrases;
+ uint32_t verifyLength = nextBlockStartAddress - start;
+ if (verifyLength > remainingBytes)
+ {
+ verifyLength = remainingBytes;
+ }
+
+ numberOfPhrases = verifyLength / flashInfo.sectionCmdAddressAligment;
+
+ /* Fill in verify section command parameters. */
+ kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_VERIFY_SECTION, start);
+ kFCCOBx[1] = BYTES_JOIN_TO_WORD_2_1_1(numberOfPhrases, margin, 0xFFU);
+
+ /* calling flash command sequence function to execute the command */
+ returnCode = flash_command_sequence(config);
+ if (returnCode)
+ {
+ return returnCode;
+ }
+
+ remainingBytes -= verifyLength;
+ start += verifyLength;
+ nextBlockStartAddress += blockSize;
+ }
+
+ return kStatus_FLASH_Success;
+}
+
+status_t FLASH_VerifyProgram(flash_config_t *config,
+ uint32_t start,
+ uint32_t lengthInBytes,
+ const uint32_t *expectedData,
+ flash_margin_value_t margin,
+ uint32_t *failedAddress,
+ uint32_t *failedData)
+{
+ status_t returnCode;
+ flash_operation_config_t flashInfo;
+
+ if (expectedData == NULL)
+ {
+ return kStatus_FLASH_InvalidArgument;
+ }
+
+ flash_get_matched_operation_info(config, start, &flashInfo);
+
+ returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.checkCmdAddressAligment);
+ if (returnCode)
+ {
+ return returnCode;
+ }
+
+ start = flashInfo.convertedAddress;
+
+ while (lengthInBytes)
+ {
+ /* preparing passing parameter to program check the flash block */
+ kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_CHECK, start);
+ kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(margin, 0xFFFFFFU);
+ kFCCOBx[2] = *expectedData;
+
+ /* calling flash command sequence function to execute the command */
+ returnCode = flash_command_sequence(config);
+
+ /* checking for the success of command execution */
+ if (kStatus_FLASH_Success != returnCode)
+ {
+ if (failedAddress)
+ {
+ *failedAddress = start;
+ }
+ if (failedData)
+ {
+ *failedData = 0;
+ }
+ break;
+ }
+
+ lengthInBytes -= flashInfo.checkCmdAddressAligment;
+ expectedData += flashInfo.checkCmdAddressAligment / sizeof(*expectedData);
+ start += flashInfo.checkCmdAddressAligment;
+ }
+
+ return (returnCode);
+}
+
+// status_t FLASH_VerifyEraseAllExecuteOnlySegments(flash_config_t *config, flash_margin_value_t margin)
+// {
+// if (config == NULL)
+// {
+// return kStatus_FLASH_InvalidArgument;
+// }
+//
+// /* preparing passing parameter to verify erase all execute-only segments command */
+// kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_VERIFY_ALL_EXECUTE_ONLY_SEGMENT, margin, 0xFFFFU);
+//
+// /* calling flash command sequence function to execute the command */
+// return flash_command_sequence(config);
+// }
+//
+// status_t FLASH_IsProtected(flash_config_t *config,
+// uint32_t start,
+// uint32_t lengthInBytes,
+// flash_protection_state_t *protection_state)
+// {
+// uint32_t endAddress; /* end address for protection check */
+// uint32_t protectionRegionSize; /* size of flash protection region */
+// uint32_t regionCheckedCounter; /* increments each time the flash address was checked for
+// * protection status */
+// uint32_t regionCounter; /* incrementing variable used to increment through the flash
+// * protection regions */
+// uint32_t protectStatusCounter; /* increments each time a flash region was detected as protected */
+//
+// uint8_t flashRegionProtectStatus[FSL_FEATURE_FTFx_REGION_COUNT]; /* array of the protection status for each
+// * protection region */
+// uint32_t flashRegionAddress[FSL_FEATURE_FTFx_REGION_COUNT + 1]; /* array of the start addresses for each flash
+// * protection region. Note this is REGION_COUNT+1
+// * due to requiring the next start address after
+// * the end of flash for loop-check purposes below */
+// status_t returnCode;
+//
+// if (protection_state == NULL)
+// {
+// return kStatus_FLASH_InvalidArgument;
+// }
+//
+// /* Check the supplied address range. */
+// returnCode = flash_check_range(config, start, lengthInBytes, FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE);
+// if (returnCode)
+// {
+// return returnCode;
+// }
+//
+// /* calculating Flash end address */
+// endAddress = start + lengthInBytes;
+//
+// /* Calculate the size of the flash protection region
+// * If the flash density is > 32KB, then protection region is 1/32 of total flash density
+// * Else if flash density is < 32KB, then flash protection region is set to 1KB */
+// if (config->PFlashTotalSize > 32 * 1024)
+// {
+// protectionRegionSize = (config->PFlashTotalSize) / FSL_FEATURE_FTFx_REGION_COUNT;
+// }
+// else
+// {
+// protectionRegionSize = 1024;
+// }
+//
+// /* populate the flashRegionAddress array with the start address of each flash region */
+// regionCounter = 0; /* make sure regionCounter is initialized to 0 first */
+//
+// /* populate up to 33rd element of array, this is the next address after end of flash array */
+// while (regionCounter <= FSL_FEATURE_FTFx_REGION_COUNT)
+// {
+// flashRegionAddress[regionCounter] = config->PFlashBlockBase + protectionRegionSize * regionCounter;
+// regionCounter++;
+// }
+//
+// /* populate flashRegionProtectStatus array with status information
+// * Protection status for each region is stored in the FPROT[3:0] registers
+// * Each bit represents one region of flash
+// * 4 registers * 8-bits-per-register = 32-bits (32-regions)
+// * The convention is:
+// * FPROT3[bit 0] is the first protection region (start of flash memory)
+// * FPROT0[bit 7] is the last protection region (end of flash memory)
+// * regionCounter is used to determine which FPROT[3:0] register to check for protection status
+// * Note: FPROT=1 means NOT protected, FPROT=0 means protected */
+// regionCounter = 0; /* make sure regionCounter is initialized to 0 first */
+// while (regionCounter < FSL_FEATURE_FTFx_REGION_COUNT)
+// {
+// if (regionCounter < 8)
+// {
+// flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT3) >> regionCounter) & (0x01u);
+// }
+// else if ((regionCounter >= 8) && (regionCounter < 16))
+// {
+// flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT2) >> (regionCounter - 8)) & (0x01u);
+// }
+// else if ((regionCounter >= 16) && (regionCounter < 24))
+// {
+// flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT1) >> (regionCounter - 16)) & (0x01u);
+// }
+// else
+// {
+// flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT0) >> (regionCounter - 24)) & (0x01u);
+// }
+// regionCounter++;
+// }
+//
+// /* loop through the flash regions and check
+// * desired flash address range for protection status
+// * loop stops when it is detected that start has exceeded the endAddress */
+// regionCounter = 0; /* make sure regionCounter is initialized to 0 first */
+// regionCheckedCounter = 0;
+// protectStatusCounter = 0; /* make sure protectStatusCounter is initialized to 0 first */
+// while (start < endAddress)
+// {
+// /* check to see if the address falls within this protection region
+// * Note that if the entire flash is to be checked, the last protection
+// * region checked would consist of the last protection start address and
+// * the start address following the end of flash */
+// if ((start >= flashRegionAddress[regionCounter]) && (start < flashRegionAddress[regionCounter + 1]))
+// {
+// /* increment regionCheckedCounter to indicate this region was checked */
+// regionCheckedCounter++;
+//
+// /* check the protection status of this region
+// * Note: FPROT=1 means NOT protected, FPROT=0 means protected */
+// if (!flashRegionProtectStatus[regionCounter])
+// {
+// /* increment protectStatusCounter to indicate this region is protected */
+// protectStatusCounter++;
+// }
+// start += protectionRegionSize; /* increment to an address within the next region */
+// }
+// regionCounter++; /* increment regionCounter to check for the next flash protection region */
+// }
+//
+// /* if protectStatusCounter == 0, then no region of the desired flash region is protected */
+// if (protectStatusCounter == 0)
+// {
+// *protection_state = kFLASH_protectionStateUnprotected;
+// }
+// /* if protectStatusCounter == regionCheckedCounter, then each region checked was protected */
+// else if (protectStatusCounter == regionCheckedCounter)
+// {
+// *protection_state = kFLASH_protectionStateProtected;
+// }
+// /* if protectStatusCounter != regionCheckedCounter, then protection status is mixed
+// * In other words, some regions are protected while others are unprotected */
+// else
+// {
+// *protection_state = kFLASH_protectionStateMixed;
+// }
+//
+// return (returnCode);
+// }
+//
+// status_t FLASH_IsExecuteOnly(flash_config_t *config,
+// uint32_t start,
+// uint32_t lengthInBytes,
+// flash_execute_only_access_state_t *access_state)
+// {
+// status_t returnCode;
+//
+// if (access_state == NULL)
+// {
+// return kStatus_FLASH_InvalidArgument;
+// }
+//
+// /* Check the supplied address range. */
+// returnCode = flash_check_range(config, start, lengthInBytes, FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE);
+// if (returnCode)
+// {
+// return returnCode;
+// }
+//
+// #if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL
+// {
+// uint32_t executeOnlySegmentCounter = 0;
+//
+// /* calculating end address */
+// uint32_t endAddress = start + lengthInBytes;
+//
+// /* Aligning start address and end address */
+// uint32_t alignedStartAddress = ALIGN_DOWN(start, config->PFlashAccessSegmentSize);
+// uint32_t alignedEndAddress = ALIGN_UP(endAddress, config->PFlashAccessSegmentSize);
+//
+// uint32_t segmentIndex = 0;
+// uint32_t maxSupportedExecuteOnlySegmentCount =
+// (alignedEndAddress - alignedStartAddress) / config->PFlashAccessSegmentSize;
+//
+// while (start < endAddress)
+// {
+// uint32_t xacc;
+//
+// segmentIndex = start / config->PFlashAccessSegmentSize;
+//
+// if (segmentIndex < 32)
+// {
+// xacc = *(const volatile uint32_t *)&FTFx->XACCL3;
+// }
+// else if (segmentIndex < config->PFlashAccessSegmentCount)
+// {
+// xacc = *(const volatile uint32_t *)&FTFx->XACCH3;
+// segmentIndex -= 32;
+// }
+// else
+// {
+// break;
+// }
+//
+// /* Determine if this address range is in a execute-only protection flash segment. */
+// if ((~xacc) & (1u << segmentIndex))
+// {
+// executeOnlySegmentCounter++;
+// }
+//
+// start += config->PFlashAccessSegmentSize;
+// }
+//
+// if (executeOnlySegmentCounter < 1u)
+// {
+// *access_state = kFLASH_accessStateUnLimited;
+// }
+// else if (executeOnlySegmentCounter < maxSupportedExecuteOnlySegmentCount)
+// {
+// *access_state = kFLASH_accessStateMixed;
+// }
+// else
+// {
+// *access_state = kFLASH_accessStateExecuteOnly;
+// }
+// }
+// #else
+// *access_state = kFLASH_accessStateUnLimited;
+// #endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */
+//
+// return (returnCode);
+// }
+
+// status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value)
+// {
+// if ((config == NULL) || (value == NULL))
+// {
+// return kStatus_FLASH_InvalidArgument;
+// }
+//
+// switch (whichProperty)
+// {
+// case kFLASH_propertyPflashSectorSize:
+// *value = config->PFlashSectorSize;
+// break;
+//
+// case kFLASH_propertyPflashTotalSize:
+// *value = config->PFlashTotalSize;
+// break;
+//
+// case kFLASH_propertyPflashBlockSize:
+// *value = config->PFlashTotalSize / FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT;
+// break;
+//
+// case kFLASH_propertyPflashBlockCount:
+// *value = config->PFlashBlockCount;
+// break;
+//
+// case kFLASH_propertyPflashBlockBaseAddr:
+// *value = config->PFlashBlockBase;
+// break;
+//
+// case kFLASH_propertyPflashFacSupport:
+// #if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL)
+// *value = FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL;
+// #else
+// *value = 0;
+// #endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */
+// break;
+//
+// case kFLASH_propertyPflashAccessSegmentSize:
+// *value = config->PFlashAccessSegmentSize;
+// break;
+//
+// case kFLASH_propertyPflashAccessSegmentCount:
+// *value = config->PFlashAccessSegmentCount;
+// break;
+//
+// #if FLASH_SSD_IS_FLEXNVM_ENABLED
+// case kFLASH_propertyDflashSectorSize:
+// *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE;
+// break;
+// case kFLASH_propertyDflashTotalSize:
+// *value = config->DFlashTotalSize;
+// break;
+// case kFLASH_propertyDflashBlockSize:
+// *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE;
+// break;
+// case kFLASH_propertyDflashBlockCount:
+// *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT;
+// break;
+// case kFLASH_propertyDflashBlockBaseAddr:
+// *value = config->DFlashBlockBase;
+// break;
+// case kFLASH_propertyEepromTotalSize:
+// *value = config->EEpromTotalSize;
+// break;
+// #endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
+//
+// default: /* catch inputs that are not recognized */
+// return kStatus_FLASH_UnknownProperty;
+// }
+//
+// return kStatus_FLASH_Success;
+// }
+
+// #if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
+// status_t FLASH_SetFlexramFunction(flash_config_t *config, flash_flexram_function_option_t option)
+// {
+// status_t status;
+//
+// if (config == NULL)
+// {
+// return kStatus_FLASH_InvalidArgument;
+// }
+//
+// status = flasn_check_flexram_function_option_range(option);
+// if (status != kStatus_FLASH_Success)
+// {
+// return status;
+// }
+//
+// /* preparing passing parameter to verify all block command */
+// kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_SET_FLEXRAM_FUNCTION, option, 0xFFFFU);
+//
+// /* calling flash command sequence function to execute the command */
+// return flash_command_sequence(config);
+// }
+// #endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
+//
+// #if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD
+// status_t FLASH_SwapControl(flash_config_t *config,
+// uint32_t address,
+// flash_swap_control_option_t option,
+// flash_swap_state_config_t *returnInfo)
+// {
+// status_t returnCode;
+//
+// if ((config == NULL) || (returnInfo == NULL))
+// {
+// return kStatus_FLASH_InvalidArgument;
+// }
+//
+// if (address & (FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT - 1))
+// {
+// return kStatus_FLASH_AlignmentError;
+// }
+//
+// /* Make sure address provided is in the lower half of Program flash but not in the Flash Configuration Field */
+// if ((address >= (config->PFlashTotalSize / 2)) ||
+// ((address >= kFLASH_configAreaStart) && (address <= kFLASH_configAreaEnd)))
+// {
+// return kStatus_FLASH_SwapIndicatorAddressError;
+// }
+//
+// /* Check the option. */
+// returnCode = flash_check_swap_control_option(option);
+// if (returnCode)
+// {
+// return returnCode;
+// }
+//
+// kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_SWAP_CONTROL, address);
+// kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU);
+//
+// returnCode = flash_command_sequence(config);
+//
+// returnInfo->flashSwapState = (flash_swap_state_t)FTFx->FCCOB5;
+// returnInfo->currentSwapBlockStatus = (flash_swap_block_status_t)FTFx->FCCOB6;
+// returnInfo->nextSwapBlockStatus = (flash_swap_block_status_t)FTFx->FCCOB7;
+//
+// return returnCode;
+// }
+// #endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */
+//
+// #if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP
+// status_t FLASH_Swap(flash_config_t *config, uint32_t address, flash_swap_function_option_t option)
+// {
+// flash_swap_state_config_t returnInfo;
+// status_t returnCode;
+//
+// memset(&returnInfo, 0xFFU, sizeof(returnInfo));
+//
+// do
+// {
+// returnCode = FLASH_SwapControl(config, address, kFLASH_swapControlOptionReportStatus, &returnInfo);
+// if (returnCode != kStatus_FLASH_Success)
+// {
+// return returnCode;
+// }
+//
+// if (kFLASH_swapFunctionOptionDisable == option)
+// {
+// if (returnInfo.flashSwapState == kFLASH_swapStateDisabled)
+// {
+// return kStatus_FLASH_Success;
+// }
+// else if (returnInfo.flashSwapState == kFLASH_swapStateUninitialized)
+// {
+// /* The swap system changed to the DISABLED state with Program flash block 0
+// * located at relative flash address 0x0_0000 */
+// returnCode = FLASH_SwapControl(config, address, kFLASH_swapControlOptionDisableSystem, &returnInfo);
+// }
+// else
+// {
+// /* Swap disable should be requested only when swap system is in the uninitialized state */
+// return kStatus_FLASH_SwapSystemNotInUninitialized;
+// }
+// }
+// else
+// {
+// /* When first swap: the initial swap state is Uninitialized, flash swap inidicator address is unset,
+// * the swap procedure should be Uninitialized -> Update-Erased -> Complete.
+// * After the first swap has been completed, the flash swap inidicator address cannot be modified
+// * unless EraseAllBlocks command is issued, the swap procedure is changed to Update -> Update-Erased ->
+// * Complete. */
+// switch (returnInfo.flashSwapState)
+// {
+// case kFLASH_swapStateUninitialized:
+// /* If current swap mode is Uninitialized, Initialize Swap to Initialized/READY state. */
+// returnCode =
+// FLASH_SwapControl(config, address, kFLASH_swapControlOptionIntializeSystem, &returnInfo);
+// break;
+// case kFLASH_swapStateReady:
+// /* Validate whether the address provided to the swap system is matched to
+// * swap indicator address in the IFR */
+// returnCode = flash_validate_swap_indicator_address(config, address);
+// if (returnCode == kStatus_FLASH_Success)
+// {
+// /* If current swap mode is Initialized/Ready, Initialize Swap to UPDATE state. */
+// returnCode =
+// FLASH_SwapControl(config, address, kFLASH_swapControlOptionSetInUpdateState, &returnInfo);
+// }
+// break;
+// case kFLASH_swapStateUpdate:
+// /* If current swap mode is Update, Erase indicator sector in non active block
+// * to proceed swap system to update-erased state */
+// returnCode = FLASH_Erase(config, address + (config->PFlashTotalSize >> 1),
+// FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT, kFLASH_apiEraseKey);
+// break;
+// case kFLASH_swapStateUpdateErased:
+// /* If current swap mode is Update or Update-Erased, progress Swap to COMPLETE State */
+// returnCode =
+// FLASH_SwapControl(config, address, kFLASH_swapControlOptionSetInCompleteState, &returnInfo);
+// break;
+// case kFLASH_swapStateComplete:
+// break;
+// case kFLASH_swapStateDisabled:
+// /* When swap system is in disabled state, We need to clear swap system back to uninitialized
+// * by issuing EraseAllBlocks command */
+// returnCode = kStatus_FLASH_SwapSystemNotInUninitialized;
+// break;
+// default:
+// returnCode = kStatus_FLASH_InvalidArgument;
+// break;
+// }
+// }
+// if (returnCode != kStatus_FLASH_Success)
+// {
+// break;
+// }
+// } while (!((kFLASH_swapStateComplete == returnInfo.flashSwapState) && (kFLASH_swapFunctionOptionEnable == option)));
+//
+// return returnCode;
+// }
+// #endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */
+//
+// #if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD
+// status_t FLASH_ProgramPartition(flash_config_t *config,
+// flash_partition_flexram_load_option_t option,
+// uint32_t eepromDataSizeCode,
+// uint32_t flexnvmPartitionCode)
+// {
+// status_t returnCode;
+//
+// if (config == NULL)
+// {
+// return kStatus_FLASH_InvalidArgument;
+// }
+//
+// /* eepromDataSizeCode[7:6], flexnvmPartitionCode[7:4] should be all 1'b0
+// * or it will cause access error. */
+// /* eepromDataSizeCode &= 0x3FU; */
+// /* flexnvmPartitionCode &= 0x0FU; */
+//
+// /* preparing passing parameter to program the flash block */
+// kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_2_1(FTFx_PROGRAM_PARTITION, 0xFFFFU, option);
+// kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_1_2(eepromDataSizeCode, flexnvmPartitionCode, 0xFFFFU);
+//
+// /* calling flash command sequence function to execute the command */
+// returnCode = flash_command_sequence(config);
+//
+// flash_cache_clear(config);
+//
+// #if FLASH_SSD_IS_FLEXNVM_ENABLED
+// /* Data flash IFR will be updated by program partition command during reset sequence,
+// * so we just set reserved values for partitioned FlexNVM size here */
+// config->EEpromTotalSize = FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED;
+// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+// #endif
+//
+// return (returnCode);
+// }
+// #endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD */
+//
+// status_t FLASH_PflashSetProtection(flash_config_t *config, uint32_t protectStatus)
+// {
+// if (config == NULL)
+// {
+// return kStatus_FLASH_InvalidArgument;
+// }
+//
+// *kFPROT = protectStatus;
+//
+// if (protectStatus != *kFPROT)
+// {
+// return kStatus_FLASH_CommandFailure;
+// }
+//
+// return kStatus_FLASH_Success;
+// }
+//
+// status_t FLASH_PflashGetProtection(flash_config_t *config, uint32_t *protectStatus)
+// {
+// if ((config == NULL) || (protectStatus == NULL))
+// {
+// return kStatus_FLASH_InvalidArgument;
+// }
+//
+// *protectStatus = *kFPROT;
+//
+// return kStatus_FLASH_Success;
+// }
+//
+// #if FLASH_SSD_IS_FLEXNVM_ENABLED
+// status_t FLASH_DflashSetProtection(flash_config_t *config, uint8_t protectStatus)
+// {
+// if (config == NULL)
+// {
+// return kStatus_FLASH_InvalidArgument;
+// }
+//
+// if ((config->DFlashTotalSize == 0) || (config->DFlashTotalSize == FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED))
+// {
+// return kStatus_FLASH_CommandNotSupported;
+// }
+//
+// FTFx->FDPROT = protectStatus;
+//
+// if (FTFx->FDPROT != protectStatus)
+// {
+// return kStatus_FLASH_CommandFailure;
+// }
+//
+// return kStatus_FLASH_Success;
+// }
+// #endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
+//
+// #if FLASH_SSD_IS_FLEXNVM_ENABLED
+// status_t FLASH_DflashGetProtection(flash_config_t *config, uint8_t *protectStatus)
+// {
+// if ((config == NULL) || (protectStatus == NULL))
+// {
+// return kStatus_FLASH_InvalidArgument;
+// }
+//
+// if ((config->DFlashTotalSize == 0) || (config->DFlashTotalSize == FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED))
+// {
+// return kStatus_FLASH_CommandNotSupported;
+// }
+//
+// *protectStatus = FTFx->FDPROT;
+//
+// return kStatus_FLASH_Success;
+// }
+// #endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
+//
+// #if FLASH_SSD_IS_FLEXNVM_ENABLED
+// status_t FLASH_EepromSetProtection(flash_config_t *config, uint8_t protectStatus)
+// {
+// if (config == NULL)
+// {
+// return kStatus_FLASH_InvalidArgument;
+// }
+//
+// if ((config->EEpromTotalSize == 0) || (config->EEpromTotalSize == FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED))
+// {
+// return kStatus_FLASH_CommandNotSupported;
+// }
+//
+// FTFx->FEPROT = protectStatus;
+//
+// if (FTFx->FEPROT != protectStatus)
+// {
+// return kStatus_FLASH_CommandFailure;
+// }
+//
+// return kStatus_FLASH_Success;
+// }
+// #endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
+//
+// #if FLASH_SSD_IS_FLEXNVM_ENABLED
+// status_t FLASH_EepromGetProtection(flash_config_t *config, uint8_t *protectStatus)
+// {
+// if ((config == NULL) || (protectStatus == NULL))
+// {
+// return kStatus_FLASH_InvalidArgument;
+// }
+//
+// if ((config->EEpromTotalSize == 0) || (config->EEpromTotalSize == FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED))
+// {
+// return kStatus_FLASH_CommandNotSupported;
+// }
+//
+// *protectStatus = FTFx->FEPROT;
+//
+// return kStatus_FLASH_Success;
+// }
+// #endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
+
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+/*!
+ * @brief Run flash command
+ *
+ * This function should be copied to RAM for execution to make sure that code works
+ * properly even flash cache is disabled.
+ * It is for flash-resident bootloader only, not technically required for ROM or
+ * flashloader (RAM-resident bootloader).
+ */
+void flash_run_command(FTFx_REG_ACCESS_TYPE ftfx_fstat)
+{
+ /* clear CCIF bit */
+ *ftfx_fstat = FTFx_FSTAT_CCIF_MASK;
+
+ /* Check CCIF bit of the flash status register, wait till it is set.
+ * IP team indicates that this loop will always complete. */
+ while (!((*ftfx_fstat) & FTFx_FSTAT_CCIF_MASK))
+ {
+ }
+}
+
+/*!
+ * @brief Be used for determining the size of flash_run_command()
+ *
+ * This function must be defined that lexically follows flash_run_command(),
+ * so we can determine the size of flash_run_command() at runtime and not worry
+ * about toolchain or code generation differences.
+ */
+void flash_run_command_end(void)
+{
+}
+
+/*!
+ * @brief Copy flash_run_command() to RAM
+ *
+ * This function copys the memory between flash_run_command() and flash_run_command_end()
+ * into the buffer which is also means that copying flash_run_command() to RAM.
+ */
+static void copy_flash_run_command(uint8_t *flashRunCommand)
+{
+ /* Calculate the valid length of flash_run_command() memory.
+ * Set max size(64 bytes) as default function size, in case some compiler allocates
+ * flash_run_command_end ahead of flash_run_command. */
+ uint32_t funcLength = kFLASH_executeInRamFunctionMaxSize;
+ uint32_t flash_run_command_start_addr = (uint32_t)flash_run_command & (~1U);
+ uint32_t flash_run_command_end_addr = (uint32_t)flash_run_command_end & (~1U);
+ if (flash_run_command_end_addr > flash_run_command_start_addr)
+ {
+ funcLength = flash_run_command_end_addr - flash_run_command_start_addr;
+
+ assert(funcLength <= kFLASH_executeInRamFunctionMaxSize);
+
+ /* In case some compiler allocates other function in the middle of flash_run_command
+ * and flash_run_command_end. */
+ if (funcLength > kFLASH_executeInRamFunctionMaxSize)
+ {
+ funcLength = kFLASH_executeInRamFunctionMaxSize;
+ }
+ }
+
+ /* Since the value of ARM function pointer is always odd, but the real start address
+ * of function memory should be even, that's why -1 and +1 operation exist. */
+ memcpy((void *)flashRunCommand, (void *)flash_run_command_start_addr, funcLength);
+ callFlashRunCommand = (void (*)(FTFx_REG_ACCESS_TYPE ftfx_fstat))((uint32_t)flashRunCommand + 1);
+}
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+
+/*!
+ * @brief Flash Command Sequence
+ *
+ * This function is used to perform the command write sequence to the flash.
+ *
+ * @param driver Pointer to storage for the driver runtime state.
+ * @return An error code or kStatus_FLASH_Success
+ */
+static status_t flash_command_sequence(flash_config_t *config)
+{
+ uint8_t registerValue;
+
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+ /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */
+ FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK;
+
+ status_t returnCode = flash_check_execute_in_ram_function_info(config);
+ if (kStatus_FLASH_Success != returnCode)
+ {
+ return returnCode;
+ }
+
+ /* We pass the ftfx_fstat address as a parameter to flash_run_comamnd() instead of using
+ * pre-processed MICRO sentences or operating global variable in flash_run_comamnd()
+ * to make sure that flash_run_command() will be compiled into position-independent code (PIC). */
+ callFlashRunCommand((FTFx_REG_ACCESS_TYPE)(&FTFx->FSTAT));
+#else
+ /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */
+ FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK;
+
+ /* clear CCIF bit */
+ FTFx->FSTAT = FTFx_FSTAT_CCIF_MASK;
+
+ /* Check CCIF bit of the flash status register, wait till it is set.
+ * IP team indicates that this loop will always complete. */
+ while (!(FTFx->FSTAT & FTFx_FSTAT_CCIF_MASK))
+ {
+ }
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+
+ /* Check error bits */
+ /* Get flash status register value */
+ registerValue = FTFx->FSTAT;
+
+ /* checking access error */
+ if (registerValue & FTFx_FSTAT_ACCERR_MASK)
+ {
+ return kStatus_FLASH_AccessError;
+ }
+ /* checking protection error */
+ else if (registerValue & FTFx_FSTAT_FPVIOL_MASK)
+ {
+ return kStatus_FLASH_ProtectionViolation;
+ }
+ /* checking MGSTAT0 non-correctable error */
+ else if (registerValue & FTFx_FSTAT_MGSTAT0_MASK)
+ {
+ return kStatus_FLASH_CommandFailure;
+ }
+ else
+ {
+ return kStatus_FLASH_Success;
+ }
+}
+
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+/*!
+ * @brief Run flash cache clear command
+ *
+ * This function should be copied to RAM for execution to make sure that code works
+ * properly even flash cache is disabled.
+ * It is for flash-resident bootloader only, not technically required for ROM or
+ * flashloader (RAM-resident bootloader).
+ */
+void flash_cache_clear_command(FTFx_REG32_ACCESS_TYPE ftfx_reg)
+{
+#if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS
+ *ftfx_reg |= MCM_PLACR_CFCC_MASK;
+#elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS
+#if defined(FMC_PFB01CR_CINV_WAY_MASK)
+ *ftfx_reg = (*ftfx_reg & ~FMC_PFB01CR_CINV_WAY_MASK) | FMC_PFB01CR_CINV_WAY(~0);
+#else
+ *ftfx_reg = (*ftfx_reg & ~FMC_PFB0CR_CINV_WAY_MASK) | FMC_PFB0CR_CINV_WAY(~0);
+#endif
+#elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS
+ *ftfx_reg |= MSCM_OCMDR_OCMC1(2);
+ *ftfx_reg |= MSCM_OCMDR_OCMC1(1);
+#else
+/* #error "Unknown flash cache controller" */
+#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */
+ /* Memory barriers for good measure.
+ * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */
+ __ISB();
+ __DSB();
+}
+
+/*!
+ * @brief Be used for determining the size of flash_cache_clear_command()
+ *
+ * This function must be defined that lexically follows flash_cache_clear_command(),
+ * so we can determine the size of flash_cache_clear_command() at runtime and not worry
+ * about toolchain or code generation differences.
+ */
+void flash_cache_clear_command_end(void)
+{
+}
+
+/*!
+ * @brief Copy flash_cache_clear_command() to RAM
+ *
+ * This function copys the memory between flash_cache_clear_command() and flash_cache_clear_command_end()
+ * into the buffer which is also means that copying flash_cache_clear_command() to RAM.
+ */
+static void copy_flash_cache_clear_command(uint8_t *flashCacheClearCommand)
+{
+ /* Calculate the valid length of flash_cache_clear_command() memory.
+ * Set max size(64 bytes) as default function size, in case some compiler allocates
+ * flash_cache_clear_command_end ahead of flash_cache_clear_command. */
+ uint32_t funcLength = kFLASH_executeInRamFunctionMaxSize;
+ uint32_t flash_cache_clear_command_start_addr = (uint32_t)flash_cache_clear_command & (~1U);
+ uint32_t flash_cache_clear_command_end_addr = (uint32_t)flash_cache_clear_command_end & (~1U);
+ if (flash_cache_clear_command_end_addr > flash_cache_clear_command_start_addr)
+ {
+ funcLength = flash_cache_clear_command_end_addr - flash_cache_clear_command_start_addr;
+
+ assert(funcLength <= kFLASH_executeInRamFunctionMaxSize);
+
+ /* In case some compiler allocates other function in the middle of flash_cache_clear_command
+ * and flash_cache_clear_command_end. */
+ if (funcLength > kFLASH_executeInRamFunctionMaxSize)
+ {
+ funcLength = kFLASH_executeInRamFunctionMaxSize;
+ }
+ }
+
+ /* Since the value of ARM function pointer is always odd, but the real start address
+ * of function memory should be even, that's why -1 and +1 operation exist. */
+ memcpy((void *)flashCacheClearCommand, (void *)flash_cache_clear_command_start_addr, funcLength);
+ callFlashCacheClearCommand = (void (*)(FTFx_REG32_ACCESS_TYPE ftfx_reg))((uint32_t)flashCacheClearCommand + 1);
+}
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+
+/*!
+ * @brief Flash Cache Clear
+ *
+ * This function is used to perform the cache clear to the flash.
+ */
+#if (defined(__ICCARM__))
+#pragma optimize = none
+void flash_cache_clear(flash_config_t *config)
+#elif (defined(__CC_ARM))
+#pragma push
+#pragma O0
+void flash_cache_clear(flash_config_t *config)
+#elif (!defined(__GNUC__))
+/* #pragma GCC push_options */
+/* #pragma GCC optimize("O0") */
+void __attribute__((optimize("O0"))) flash_cache_clear(flash_config_t *config)
+#else
+#error "Unknown compiler"
+#endif
+{
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+ status_t returnCode = flash_check_execute_in_ram_function_info(config);
+ if (kStatus_FLASH_Success != returnCode)
+ {
+ return;
+ }
+
+/* We pass the ftfx register address as a parameter to flash_cache_clear_comamnd() instead of using
+ * pre-processed MACROs or a global variable in flash_cache_clear_comamnd()
+ * to make sure that flash_cache_clear_command() will be compiled into position-independent code (PIC). */
+#if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS
+#if defined(MCM)
+ callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MCM->PLACR);
+#endif
+#if defined(MCM0)
+ callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MCM0->PLACR);
+#endif
+#if defined(MCM1)
+ callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MCM1->PLACR);
+#endif
+#elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS
+#if defined(FMC_PFB01CR_CINV_WAY_MASK)
+ callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR);
+#else
+ callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR);
+#endif
+#elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS
+ callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[0]);
+#else
+ /* #error "Unknown flash cache controller" */
+ /* meaningless code, just a workaround to solve warning*/
+ callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)0);
+#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */
+
+#else
+
+#if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS
+#if defined(MCM)
+ MCM->PLACR |= MCM_PLACR_CFCC_MASK;
+#endif
+#if defined(MCM0)
+ MCM0->PLACR |= MCM_PLACR_CFCC_MASK;
+#endif
+#if defined(MCM1)
+ MCM1->PLACR |= MCM_PLACR_CFCC_MASK;
+#endif
+#elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS
+#if defined(FMC_PFB01CR_CINV_WAY_MASK)
+ FMC->PFB01CR = (FMC->PFB01CR & ~FMC_PFB01CR_CINV_WAY_MASK) | FMC_PFB01CR_CINV_WAY(~0);
+#else
+ FMC->PFB0CR = (FMC->PFB0CR & ~FMC_PFB0CR_CINV_WAY_MASK) | FMC_PFB0CR_CINV_WAY(~0);
+#endif
+#elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS
+ MSCM->OCMDR[0] |= MSCM_OCMDR_OCMC1(2);
+ MSCM->OCMDR[0] |= MSCM_OCMDR_OCMC1(1);
+#else
+/* #error "Unknown flash cache controller" */
+#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+}
+#if (defined(__CC_ARM))
+#pragma pop
+#endif
+#if (defined(__GNUC__))
+/* #pragma GCC pop_options */
+#endif
+
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+/*! @brief Check whether flash execute-in-ram functions are ready */
+static status_t flash_check_execute_in_ram_function_info(flash_config_t *config)
+{
+ flash_execute_in_ram_function_config_t *flashExecuteInRamFunctionInfo;
+
+ if (config == NULL)
+ {
+ return kStatus_FLASH_InvalidArgument;
+ }
+
+ flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo;
+
+ if ((config->flashExecuteInRamFunctionInfo) &&
+ (kFLASH_executeInRamFunctionTotalNum == flashExecuteInRamFunctionInfo->activeFunctionCount))
+ {
+ return kStatus_FLASH_Success;
+ }
+
+ return kStatus_FLASH_ExecuteInRamFunctionNotReady;
+}
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+
+/*! @brief Validates the range and alignment of the given address range.*/
+static status_t flash_check_range(flash_config_t *config,
+ uint32_t startAddress,
+ uint32_t lengthInBytes,
+ uint32_t alignmentBaseline)
+{
+ if (config == NULL)
+ {
+ return kStatus_FLASH_InvalidArgument;
+ }
+
+ /* Verify the start and length are alignmentBaseline aligned. */
+ if ((startAddress & (alignmentBaseline - 1)) || (lengthInBytes & (alignmentBaseline - 1)))
+ {
+ return kStatus_FLASH_AlignmentError;
+ }
+
+/* check for valid range of the target addresses */
+#if !FLASH_SSD_IS_FLEXNVM_ENABLED
+ if ((startAddress < config->PFlashBlockBase) ||
+ ((startAddress + lengthInBytes) > (config->PFlashBlockBase + config->PFlashTotalSize)))
+#else
+ if (!(((startAddress >= config->PFlashBlockBase) &&
+ ((startAddress + lengthInBytes) <= (config->PFlashBlockBase + config->PFlashTotalSize))) ||
+ ((startAddress >= config->DFlashBlockBase) &&
+ ((startAddress + lengthInBytes) <= (config->DFlashBlockBase + config->DFlashTotalSize)))))
+#endif
+ {
+ return kStatus_FLASH_AddressError;
+ }
+
+ return kStatus_FLASH_Success;
+}
+
+/*! @brief Gets the right address, sector and block size of current flash type which is indicated by address.*/
+static status_t flash_get_matched_operation_info(flash_config_t *config,
+ uint32_t address,
+ flash_operation_config_t *info)
+{
+ if (config == NULL)
+ {
+ return kStatus_FLASH_InvalidArgument;
+ }
+
+ /* Clean up info Structure*/
+ memset(info, 0, sizeof(flash_operation_config_t));
+
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+ if ((address >= config->DFlashBlockBase) && (address <= (config->DFlashBlockBase + config->DFlashTotalSize)))
+ {
+ info->convertedAddress = address - config->DFlashBlockBase + 0x800000U;
+ info->activeSectorSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE;
+ info->activeBlockSize = config->DFlashTotalSize / FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT;
+
+ info->blockWriteUnitSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE;
+ info->sectorCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT;
+ info->sectionCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT;
+ info->resourceCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT;
+ info->checkCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT;
+ }
+ else
+#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
+ {
+ info->convertedAddress = address;
+ info->activeSectorSize = config->PFlashSectorSize;
+ info->activeBlockSize = config->PFlashTotalSize / config->PFlashBlockCount;
+
+ info->blockWriteUnitSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE;
+ info->sectorCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT;
+ info->sectionCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT;
+ info->resourceCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT;
+ info->checkCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT;
+ }
+
+ return kStatus_FLASH_Success;
+}
+
+/*! @brief Validates the given user key for flash erase APIs.*/
+static status_t flash_check_user_key(uint32_t key)
+{
+ /* Validate the user key */
+ if (key != kFLASH_apiEraseKey)
+ {
+ return kStatus_FLASH_EraseKeyError;
+ }
+
+ return kStatus_FLASH_Success;
+}
+
+// #if FLASH_SSD_IS_FLEXNVM_ENABLED
+// /*! @brief Updates FlexNVM memory partition status according to data flash 0 IFR.*/
+// static status_t flash_update_flexnvm_memory_partition_status(flash_config_t *config)
+// {
+// struct
+// {
+// uint32_t reserved0;
+// uint8_t FlexNVMPartitionCode;
+// uint8_t EEPROMDataSetSize;
+// uint16_t reserved1;
+// } dataIFRReadOut;
+// status_t returnCode;
+//
+// if (config == NULL)
+// {
+// return kStatus_FLASH_InvalidArgument;
+// }
+//
+// /* Get FlexNVM memory partition info from data flash IFR */
+// returnCode = FLASH_ReadResource(config, DFLASH_IFR_READRESOURCE_START_ADDRESS, (uint32_t *)&dataIFRReadOut,
+// sizeof(dataIFRReadOut), kFLASH_resourceOptionFlashIfr);
+// if (returnCode != kStatus_FLASH_Success)
+// {
+// return kStatus_FLASH_PartitionStatusUpdateFailure;
+// }
+//
+// /* Fill out partitioned EEPROM size */
+// dataIFRReadOut.EEPROMDataSetSize &= 0x0FU;
+// switch (dataIFRReadOut.EEPROMDataSetSize)
+// {
+// case 0x00U:
+// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000;
+// break;
+// case 0x01U:
+// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001;
+// break;
+// case 0x02U:
+// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010;
+// break;
+// case 0x03U:
+// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011;
+// break;
+// case 0x04U:
+// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100;
+// break;
+// case 0x05U:
+// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101;
+// break;
+// case 0x06U:
+// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110;
+// break;
+// case 0x07U:
+// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111;
+// break;
+// case 0x08U:
+// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000;
+// break;
+// case 0x09U:
+// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001;
+// break;
+// case 0x0AU:
+// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010;
+// break;
+// case 0x0BU:
+// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011;
+// break;
+// case 0x0CU:
+// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100;
+// break;
+// case 0x0DU:
+// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101;
+// break;
+// case 0x0EU:
+// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110;
+// break;
+// case 0x0FU:
+// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111;
+// break;
+// default:
+// config->EEpromTotalSize = FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED;
+// break;
+// }
+//
+// /* Fill out partitioned DFlash size */
+// dataIFRReadOut.FlexNVMPartitionCode &= 0x0FU;
+// switch (dataIFRReadOut.FlexNVMPartitionCode)
+// {
+// case 0x00U:
+// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 != 0xFFFFFFFF)
+// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000;
+// #else
+// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 */
+// break;
+// case 0x01U:
+// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 != 0xFFFFFFFF)
+// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001;
+// #else
+// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 */
+// break;
+// case 0x02U:
+// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 != 0xFFFFFFFF)
+// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010;
+// #else
+// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 */
+// break;
+// case 0x03U:
+// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 != 0xFFFFFFFF)
+// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011;
+// #else
+// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 */
+// break;
+// case 0x04U:
+// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 != 0xFFFFFFFF)
+// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100;
+// #else
+// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 */
+// break;
+// case 0x05U:
+// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 != 0xFFFFFFFF)
+// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101;
+// #else
+// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 */
+// break;
+// case 0x06U:
+// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 != 0xFFFFFFFF)
+// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110;
+// #else
+// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 */
+// break;
+// case 0x07U:
+// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 != 0xFFFFFFFF)
+// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111;
+// #else
+// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 */
+// break;
+// case 0x08U:
+// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 != 0xFFFFFFFF)
+// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000;
+// #else
+// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 */
+// break;
+// case 0x09U:
+// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 != 0xFFFFFFFF)
+// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001;
+// #else
+// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 */
+// break;
+// case 0x0AU:
+// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 != 0xFFFFFFFF)
+// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010;
+// #else
+// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 */
+// break;
+// case 0x0BU:
+// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 != 0xFFFFFFFF)
+// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011;
+// #else
+// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 */
+// break;
+// case 0x0CU:
+// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 != 0xFFFFFFFF)
+// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100;
+// #else
+// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 */
+// break;
+// case 0x0DU:
+// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 != 0xFFFFFFFF)
+// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101;
+// #else
+// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 */
+// break;
+// case 0x0EU:
+// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 != 0xFFFFFFFF)
+// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110;
+// #else
+// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 */
+// break;
+// case 0x0FU:
+// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 != 0xFFFFFFFF)
+// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111;
+// #else
+// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 */
+// break;
+// default:
+// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+// break;
+// }
+//
+// return kStatus_FLASH_Success;
+// }
+// #endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
+
+// #if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD
+// /*! @brief Validates the range of the given resource address.*/
+// static status_t flash_check_resource_range(uint32_t start,
+// uint32_t lengthInBytes,
+// uint32_t alignmentBaseline,
+// flash_read_resource_option_t option)
+// {
+// status_t status;
+// uint32_t maxReadbleAddress;
+//
+// if ((start & (alignmentBaseline - 1)) || (lengthInBytes & (alignmentBaseline - 1)))
+// {
+// return kStatus_FLASH_AlignmentError;
+// }
+//
+// status = kStatus_FLASH_Success;
+//
+// maxReadbleAddress = start + lengthInBytes - 1;
+// if (option == kFLASH_resourceOptionVersionId)
+// {
+// if ((start != kFLASH_resourceRangeVersionIdStart) ||
+// ((start + lengthInBytes - 1) != kFLASH_resourceRangeVersionIdEnd))
+// {
+// status = kStatus_FLASH_InvalidArgument;
+// }
+// }
+// else if (option == kFLASH_resourceOptionFlashIfr)
+// {
+// if (maxReadbleAddress < kFLASH_resourceRangePflashIfrSizeInBytes)
+// {
+// }
+// #if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP
+// else if ((start >= kFLASH_resourceRangePflashSwapIfrStart) &&
+// (maxReadbleAddress <= kFLASH_resourceRangePflashSwapIfrEnd))
+// {
+// }
+// #endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */
+// else if ((start >= kFLASH_resourceRangeDflashIfrStart) &&
+// (maxReadbleAddress <= kFLASH_resourceRangeDflashIfrEnd))
+// {
+// }
+// else
+// {
+// status = kStatus_FLASH_InvalidArgument;
+// }
+// }
+// else
+// {
+// status = kStatus_FLASH_InvalidArgument;
+// }
+//
+// return status;
+// }
+// #endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */
+
+// #if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD
+// /*! @brief Validates the gived swap control option.*/
+// static status_t flash_check_swap_control_option(flash_swap_control_option_t option)
+// {
+// if ((option == kFLASH_swapControlOptionIntializeSystem) || (option == kFLASH_swapControlOptionSetInUpdateState) ||
+// (option == kFLASH_swapControlOptionSetInCompleteState) || (option == kFLASH_swapControlOptionReportStatus) ||
+// (option == kFLASH_swapControlOptionDisableSystem))
+// {
+// return kStatus_FLASH_Success;
+// }
+//
+// return kStatus_FLASH_InvalidArgument;
+// }
+// #endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */
+//
+// #if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP
+// /*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/
+// static status_t flash_validate_swap_indicator_address(flash_config_t *config, uint32_t address)
+// {
+// flash_swap_ifr_field_config_t flashSwapIfrField;
+// uint32_t swapIndicatorAddress;
+//
+// status_t returnCode;
+// returnCode = FLASH_ReadResource(config, kFLASH_resourceRangePflashSwapIfrStart, (uint32_t *)&flashSwapIfrField,
+// sizeof(flash_swap_ifr_field_config_t), kFLASH_resourceOptionFlashIfr);
+// if (returnCode != kStatus_FLASH_Success)
+// {
+// return returnCode;
+// }
+//
+// /* The high 2 byte value of Swap Indicator Address is stored in Program Flash Swap IFR Field,
+// * the low 4 bit value of Swap Indicator Address is always 4'b0000 */
+// swapIndicatorAddress =
+// (uint32_t)flashSwapIfrField.swapIndicatorAddress * FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT;
+// if (address != swapIndicatorAddress)
+// {
+// return kStatus_FLASH_SwapIndicatorAddressError;
+// }
+//
+// return returnCode;
+// }
+// #endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */
+//
+// #if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
+// /*! @brief Validates the gived flexram function option.*/
+// static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option)
+// {
+// if ((option != kFLASH_flexramFunctionOptionAvailableAsRam) &&
+// (option != kFLASH_flexramFunctionOptionAvailableForEeprom))
+// {
+// return kStatus_FLASH_InvalidArgument;
+// }
+//
+// return kStatus_FLASH_Success;
+// }
+// #endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/iap/fsl_flash.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/iap/fsl_flash.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1177 @@
+/*
+ * Copyright (c) 2013-2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_FLASH_H_
+#define _FSL_FLASH_H_
+
+#if (defined(BL_TARGET_FLASH) || defined(BL_TARGET_ROM) || defined(BL_TARGET_RAM))
+#include <assert.h>
+#include <string.h>
+#include "fsl_device_registers.h"
+#include "bootloader_common.h"
+#else
+#include "fsl_common.h"
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @addtogroup flash_driver
+ * @{
+ */
+
+/*!
+ * @name Flash version
+ * @{
+ */
+/*! @brief Construct the version number for drivers. */
+#if !defined(MAKE_VERSION)
+#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
+#endif
+
+/*! @brief FLASH driver version for SDK*/
+#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+
+/*! @brief FLASH driver version for ROM*/
+enum _flash_driver_version_constants
+{
+ kFLASH_driverVersionName = 'F', /*!< Flash driver version name.*/
+ kFLASH_driverVersionMajor = 2, /*!< Major flash driver version.*/
+ kFLASH_driverVersionMinor = 0, /*!< Minor flash driver version.*/
+ kFLASH_driverVersionBugfix = 0 /*!< Bugfix for flash driver version.*/
+};
+/*@}*/
+
+/*!
+ * @name Flash configuration
+ * @{
+ */
+/*! @brief Whether to support FlexNVM in flash driver */
+#if !defined(FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT)
+#define FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT 1 /*!< Enable FlexNVM support by default. */
+#endif
+
+/*! @brief Whether the FlexNVM is enabled in flash driver */
+#define FLASH_SSD_IS_FLEXNVM_ENABLED (FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT && FSL_FEATURE_FLASH_HAS_FLEX_NVM)
+
+/*! @brief Flash driver location. */
+#if !defined(FLASH_DRIVER_IS_FLASH_RESIDENT)
+#if (!defined(BL_TARGET_ROM) && !defined(BL_TARGET_RAM))
+#define FLASH_DRIVER_IS_FLASH_RESIDENT 1 /*!< Used for flash resident application. */
+#else
+#define FLASH_DRIVER_IS_FLASH_RESIDENT 0 /*!< Used for non-flash resident application. */
+#endif
+#endif
+
+/*! @brief Flash Driver Export option */
+#if !defined(FLASH_DRIVER_IS_EXPORTED)
+#if (defined(BL_TARGET_ROM) || defined(BL_TARGET_FLASH))
+#define FLASH_DRIVER_IS_EXPORTED 1 /*!< Used for ROM bootloader. */
+#else
+#define FLASH_DRIVER_IS_EXPORTED 0 /*!< Used for SDK application. */
+#endif
+#endif
+/*@}*/
+
+/*!
+ * @name Flash status
+ * @{
+ */
+/*! @brief Flash driver status group. */
+#if defined(kStatusGroup_FlashDriver)
+#define kStatusGroupGeneric kStatusGroup_Generic
+#define kStatusGroupFlashDriver kStatusGroup_FlashDriver
+#elif defined(kStatusGroup_FLASH)
+#define kStatusGroupGeneric kStatusGroup_Generic
+#define kStatusGroupFlashDriver kStatusGroup_FLASH
+#else
+#define kStatusGroupGeneric 0
+#define kStatusGroupFlashDriver 1
+#endif
+
+/*! @brief Construct a status code value from a group and code number. */
+#if !defined(MAKE_STATUS)
+#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
+#endif
+
+/*!
+ * @brief Flash driver status codes.
+ */
+enum _flash_status
+{
+ kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< Api is executed successfully*/
+ kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/
+ kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/
+ kStatus_FLASH_AlignmentError =
+ MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with specified baseline*/
+ kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */
+ kStatus_FLASH_AccessError =
+ MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bounds addresses */
+ kStatus_FLASH_ProtectionViolation = MAKE_STATUS(
+ kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */
+ kStatus_FLASH_CommandFailure =
+ MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */
+ kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/
+ kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< Api erase key is invalid.*/
+ kStatus_FLASH_RegionExecuteOnly = MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< Current region is execute only.*/
+ kStatus_FLASH_ExecuteInRamFunctionNotReady =
+ MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-ram function is not available.*/
+ kStatus_FLASH_PartitionStatusUpdateFailure =
+ MAKE_STATUS(kStatusGroupFlashDriver, 10), /*!< Failed to update partition status.*/
+ kStatus_FLASH_SetFlexramAsEepromError =
+ MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Failed to set flexram as eeprom.*/
+ kStatus_FLASH_RecoverFlexramAsRamError =
+ MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< Failed to recover flexram as ram.*/
+ kStatus_FLASH_SetFlexramAsRamError = MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< Failed to set flexram as ram.*/
+ kStatus_FLASH_RecoverFlexramAsEepromError =
+ MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< Failed to recover flexram as eeprom.*/
+ kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 15), /*!< Flash api is not supported.*/
+ kStatus_FLASH_SwapSystemNotInUninitialized =
+ MAKE_STATUS(kStatusGroupFlashDriver, 16), /*!< Swap system is not in uninitialzed state.*/
+ kStatus_FLASH_SwapIndicatorAddressError =
+ MAKE_STATUS(kStatusGroupFlashDriver, 17), /*!< Swap indicator address is invalid.*/
+};
+/*@}*/
+
+/*!
+ * @name Flash API key
+ * @{
+ */
+/*! @brief Construct the four char code for flash driver API key. */
+#if !defined(FOUR_CHAR_CODE)
+#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a)))
+#endif
+
+/*!
+ * @brief Enumeration for flash driver API keys.
+ *
+ * @note The resulting value is built with a byte order such that the string
+ * being readable in expected order when viewed in a hex editor, if the value
+ * is treated as a 32-bit little endian value.
+ */
+enum _flash_driver_api_keys
+{
+ kFLASH_apiEraseKey = FOUR_CHAR_CODE('k', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/
+};
+/*@}*/
+
+/*!
+ * @brief Enumeration for supported flash margin levels.
+ */
+typedef enum _flash_margin_value
+{
+ kFLASH_marginValueNormal, /*!< Use the 'normal' read level for 1s.*/
+ kFLASH_marginValueUser, /*!< Apply the 'User' margin to the normal read-1 level.*/
+ kFLASH_marginValueFactory, /*!< Apply the 'Factory' margin to the normal read-1 level.*/
+ kFLASH_marginValueInvalid /*!< Not real margin level, Used to determine the range of valid margin level. */
+} flash_margin_value_t;
+
+/*!
+ * @brief Enumeration for the three possible flash security states.
+ */
+typedef enum _flash_security_state
+{
+ kFLASH_securityStateNotSecure, /*!< Flash is not secure.*/
+ kFLASH_securityStateBackdoorEnabled, /*!< Flash backdoor is enabled.*/
+ kFLASH_securityStateBackdoorDisabled /*!< Flash backdoor is disabled.*/
+} flash_security_state_t;
+
+/*!
+ * @brief Enumeration for the three possible flash protection levels.
+ */
+typedef enum _flash_protection_state
+{
+ kFLASH_protectionStateUnprotected, /*!< Flash region is not protected.*/
+ kFLASH_protectionStateProtected, /*!< Flash region is protected.*/
+ kFLASH_protectionStateMixed /*!< Flash is mixed with protected and unprotected region.*/
+} flash_protection_state_t;
+
+/*!
+ * @brief Enumeration for the three possible flash execute access levels.
+ */
+typedef enum _flash_execute_only_access_state
+{
+ kFLASH_accessStateUnLimited, /*!< Flash region is unLimited.*/
+ kFLASH_accessStateExecuteOnly, /*!< Flash region is execute only.*/
+ kFLASH_accessStateMixed /*!< Flash is mixed with unLimited and execute only region.*/
+} flash_execute_only_access_state_t;
+
+/*!
+ * @brief Enumeration for various flash properties.
+ */
+typedef enum _flash_property_tag
+{
+ kFLASH_propertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/
+ kFLASH_propertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/
+ kFLASH_propertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/
+ kFLASH_propertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/
+ kFLASH_propertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/
+ kFLASH_propertyPflashFacSupport = 0x05U, /*!< Pflash fac support property.*/
+ kFLASH_propertyPflashAccessSegmentSize = 0x06U, /*!< Pflash access segment size property.*/
+ kFLASH_propertyPflashAccessSegmentCount = 0x07U, /*!< Pflash access segment count property.*/
+ kFLASH_propertyFlexRamBlockBaseAddr = 0x08U, /*!< FlexRam block base address property.*/
+ kFLASH_propertyFlexRamTotalSize = 0x09U, /*!< FlexRam total size property.*/
+ kFLASH_propertyDflashSectorSize = 0x10U, /*!< Dflash sector size property.*/
+ kFLASH_propertyDflashTotalSize = 0x11U, /*!< Dflash total size property.*/
+ kFLASH_propertyDflashBlockSize = 0x12U, /*!< Dflash block count property.*/
+ kFLASH_propertyDflashBlockCount = 0x13U, /*!< Dflash block base address property.*/
+ kFLASH_propertyDflashBlockBaseAddr = 0x14U, /*!< Eeprom total size property.*/
+ kFLASH_propertyEepromTotalSize = 0x15U
+} flash_property_tag_t;
+
+/*!
+ * @brief Constants for execute-in-ram flash function.
+ */
+enum _flash_execute_in_ram_function_constants
+{
+ kFLASH_executeInRamFunctionMaxSize = 64U, /*!< Max size of execute-in-ram function.*/
+ kFLASH_executeInRamFunctionTotalNum = 2U /*!< Total number of execute-in-ram functions.*/
+};
+
+/*!
+ * @brief Flash execute-in-ram function information.
+ */
+typedef struct _flash_execute_in_ram_function_config
+{
+ uint32_t activeFunctionCount; /*!< Number of available execute-in-ram functions.*/
+ uint8_t *flashRunCommand; /*!< execute-in-ram function: flash_run_command.*/
+ uint8_t *flashCacheClearCommand; /*!< execute-in-ram function: flash_cache_clear_command.*/
+} flash_execute_in_ram_function_config_t;
+
+/*!
+ * @brief Enumeration for the two possible options of flash read resource command.
+ */
+typedef enum _flash_read_resource_option
+{
+ kFLASH_resourceOptionFlashIfr =
+ 0x00U, /*!< Select code for Program flash 0 IFR, Program flash swap 0 IFR, Data flash 0 IFR */
+ kFLASH_resourceOptionVersionId = 0x01U /*!< Select code for Version ID*/
+} flash_read_resource_option_t;
+
+/*!
+ * @brief Enumeration for the range of special-purpose flash resource
+ */
+enum _flash_read_resource_range
+{
+#if (FSL_FEATURE_FLASH_IS_FTFE == 1)
+ kFLASH_resourceRangePflashIfrSizeInBytes = 1024U, /*!< Pflash IFR size in byte.*/
+ kFLASH_resourceRangeVersionIdSizeInBytes = 8U, /*!< Version ID IFR size in byte.*/
+ kFLASH_resourceRangeVersionIdStart = 0x08U, /*!< Version ID IFR start address.*/
+ kFLASH_resourceRangeVersionIdEnd = 0x0FU, /*!< Version ID IFR end address.*/
+#else /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */
+ kFLASH_resourceRangePflashIfrSizeInBytes = 256U, /*!< Pflash IFR size in byte.*/
+ kFLASH_resourceRangeVersionIdSizeInBytes = 8U, /*!< Version ID IFR size in byte.*/
+ kFLASH_resourceRangeVersionIdStart = 0x00U, /*!< Version ID IFR start address.*/
+ kFLASH_resourceRangeVersionIdEnd = 0x07U, /*!< Version ID IFR end address.*/
+#endif
+ kFLASH_resourceRangePflashSwapIfrStart = 0x40000U, /*!< Pflash swap IFR start address.*/
+ kFLASH_resourceRangePflashSwapIfrEnd = 0x403FFU, /*!< Pflash swap IFR end address.*/
+ kFLASH_resourceRangeDflashIfrStart = 0x800000U, /*!< Dflash IFR start address.*/
+ kFLASH_resourceRangeDflashIfrEnd = 0x8003FFU, /*!< Dflash IFR end address.*/
+};
+
+/*!
+ * @brief Enumeration for the two possilbe options of set flexram function command.
+ */
+typedef enum _flash_flexram_function_option
+{
+ kFLASH_flexramFunctionOptionAvailableAsRam = 0xFFU, /*!< Option used to make FlexRAM available as RAM */
+ kFLASH_flexramFunctionOptionAvailableForEeprom = 0x00U /*!< Option used to make FlexRAM available for EEPROM */
+} flash_flexram_function_option_t;
+
+/*!
+ * @brief Enumeration for the possible options of Swap function
+ */
+typedef enum _flash_swap_function_option
+{
+ kFLASH_swapFunctionOptionEnable = 0x00U, /*!< Option used to enable Swap function */
+ kFLASH_swapFunctionOptionDisable = 0x01U /*!< Option used to Disable Swap function */
+} flash_swap_function_option_t;
+
+/*!
+ * @brief Enumeration for the possible options of Swap Control commands
+ */
+typedef enum _flash_swap_control_option
+{
+ kFLASH_swapControlOptionIntializeSystem = 0x01U, /*!< Option used to Intialize Swap System */
+ kFLASH_swapControlOptionSetInUpdateState = 0x02U, /*!< Option used to Set Swap in Update State */
+ kFLASH_swapControlOptionSetInCompleteState = 0x04U, /*!< Option used to Set Swap in Complete State */
+ kFLASH_swapControlOptionReportStatus = 0x08U, /*!< Option used to Report Swap Status */
+ kFLASH_swapControlOptionDisableSystem = 0x10U /*!< Option used to Disable Swap Status */
+} flash_swap_control_option_t;
+
+/*!
+ * @brief Enumeration for the possible flash swap status.
+ */
+typedef enum _flash_swap_state
+{
+ kFLASH_swapStateUninitialized = 0x00U, /*!< Flash swap system is in uninitialized state.*/
+ kFLASH_swapStateReady = 0x01U, /*!< Flash swap system is in ready state.*/
+ kFLASH_swapStateUpdate = 0x02U, /*!< Flash swap system is in update state.*/
+ kFLASH_swapStateUpdateErased = 0x03U, /*!< Flash swap system is in updateErased state.*/
+ kFLASH_swapStateComplete = 0x04U, /*!< Flash swap system is in complete state.*/
+ kFLASH_swapStateDisabled = 0x05U /*!< Flash swap system is in disabled state.*/
+} flash_swap_state_t;
+
+/*!
+ * @breif Enumeration for the possible flash swap block status
+ */
+typedef enum _flash_swap_block_status
+{
+ kFLASH_swapBlockStatusLowerHalfProgramBlocksAtZero =
+ 0x00U, /*!< Swap block status is that lower half program block at zero.*/
+ kFLASH_swapBlockStatusUpperHalfProgramBlocksAtZero =
+ 0x01U, /*!< Swap block status is that upper half program block at zero.*/
+} flash_swap_block_status_t;
+
+/*!
+ * @brief Flash Swap information.
+ */
+typedef struct _flash_swap_state_config
+{
+ flash_swap_state_t flashSwapState; /*!< Current swap system status.*/
+ flash_swap_block_status_t currentSwapBlockStatus; /*!< Current swap block status.*/
+ flash_swap_block_status_t nextSwapBlockStatus; /*!< Next swap block status.*/
+} flash_swap_state_config_t;
+
+/*!
+ * @brief Flash Swap IFR fileds.
+ */
+typedef struct _flash_swap_ifr_field_config
+{
+ uint16_t swapIndicatorAddress; /*!< Swap indicator address field.*/
+ uint16_t swapEnableWord; /*!< Swap enable word field.*/
+ uint8_t reserved0[6]; /*!< Reserved field.*/
+ uint16_t swapDisableWord; /*!< Swap disable word field.*/
+ uint8_t reserved1[4]; /*!< Reserved field.*/
+} flash_swap_ifr_field_config_t;
+
+/*!
+ * @brief Enumeration for FlexRAM load during reset option.
+ */
+typedef enum _flash_partition_flexram_load_option
+{
+ kFLASH_partitionFlexramLoadOptionLoadedWithValidEepromData =
+ 0x00U, /*!< FlexRAM is loaded with valid EEPROM data during reset sequence.*/
+ kFLASH_partitionFlexramLoadOptionNotLoaded = 0x01U /*!< FlexRAM is not loaded during reset sequence.*/
+} flash_partition_flexram_load_option_t;
+
+/*! @brief callback type used for pflash block*/
+typedef void (*flash_callback_t)(void);
+
+/*!
+ * @brief Active flash information for current operation.
+ */
+typedef struct _flash_operation_config
+{
+ uint32_t convertedAddress; /*!< Converted address for current flash type.*/
+ uint32_t activeSectorSize; /*!< Sector size of current flash type.*/
+ uint32_t activeBlockSize; /*!< Block size of current flash type.*/
+ uint32_t blockWriteUnitSize; /*!< write unit size.*/
+ uint32_t sectorCmdAddressAligment; /*!< Erase sector command address alignment.*/
+ uint32_t sectionCmdAddressAligment; /*!< Program/Verify section command address alignment.*/
+ uint32_t resourceCmdAddressAligment; /*!< Read resource command address alignment.*/
+ uint32_t checkCmdAddressAligment; /*!< Program check command address alignment.*/
+} flash_operation_config_t;
+
+/*! @brief Flash driver state information.
+ *
+ * An instance of this structure is allocated by the user of the flash driver and
+ * passed into each of the driver APIs.
+ */
+typedef struct _flash_config
+{
+ uint32_t PFlashBlockBase; /*!< Base address of the first PFlash block */
+ uint32_t PFlashTotalSize; /*!< Size of all combined PFlash block. */
+ uint32_t PFlashBlockCount; /*!< Number of PFlash blocks. */
+ uint32_t PFlashSectorSize; /*!< Size in bytes of a sector of PFlash. */
+ flash_callback_t PFlashCallback; /*!< Callback function for flash API. */
+ uint32_t PFlashAccessSegmentSize; /*!< Size in bytes of a access segment of PFlash. */
+ uint32_t PFlashAccessSegmentCount; /*!< Number of PFlash access segments. */
+ uint32_t *flashExecuteInRamFunctionInfo; /*!< Info struct of flash execute-in-ram function. */
+ uint32_t FlexRAMBlockBase; /*!< For FlexNVM device, this is the base address of FlexRAM
+ For non-FlexNVM device, this is the base address of acceleration RAM memory */
+ uint32_t FlexRAMTotalSize; /*!< For FlexNVM device, this is the size of FlexRAM
+ For non-FlexNVM device, this is the size of acceleration RAM memory */
+ uint32_t DFlashBlockBase; /*!< For FlexNVM device, this is the base address of D-Flash memory (FlexNVM memory);
+ For non-FlexNVM device, this field is unused */
+ uint32_t DFlashTotalSize; /*!< For FlexNVM device, this is total size of the FlexNVM memory;
+ For non-FlexNVM device, this field is unused */
+ uint32_t EEpromTotalSize; /*!< For FlexNVM device, this is the size in byte of EEPROM area which was partitioned
+ from FlexRAM;
+ For non-FlexNVM device, this field is unused */
+} flash_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes global flash properties structure members
+ *
+ * This function checks and initializes Flash module for the other Flash APIs.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update partition status.
+ */
+status_t FLASH_Init(flash_config_t *config);
+
+/*!
+ * @brief Set the desired flash callback function
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param callback callback function to be stored in driver
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ */
+status_t FLASH_SetCallback(flash_config_t *config, flash_callback_t callback);
+
+/*!
+ * @brief Prepare flash execute-in-ram functions
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ */
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+status_t FLASH_PrepareExecuteInRamFunctions(flash_config_t *config);
+#endif
+
+/*@}*/
+
+/*!
+ * @name Erasing
+ * @{
+ */
+
+/*!
+ * @brief Erases entire flash
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param key value used to validate all flash erase APIs.
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_EraseKeyError Api erase key is invalid.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update partition status
+ */
+status_t FLASH_EraseAll(flash_config_t *config, uint32_t key);
+
+/*!
+ * @brief Erases flash sectors encompassed by parameters passed into function
+ *
+ * This function erases the appropriate number of flash sectors based on the
+ * desired start address and length.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be erased.
+ * The start address does not need to be sector aligned but must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * to be erased. Must be word aligned.
+ * @param key value used to validate all flash erase APIs.
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FLASH_AddressError Address is out of range.
+ * @retval #kStatus_FLASH_EraseKeyError Api erase key is invalid.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key);
+
+/*!
+ * @brief Erases entire flash, including protected sectors.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param key value used to validate all flash erase APIs.
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_EraseKeyError Api erase key is invalid.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update partition status
+ */
+#if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD
+status_t FLASH_EraseAllUnsecure(flash_config_t *config, uint32_t key);
+#endif
+
+/*!
+ * @brief Erases all program flash execute-only segments defined by the FXACC registers.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param key value used to validate all flash erase APIs.
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_EraseKeyError Api erase key is invalid.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+status_t FLASH_EraseAllExecuteOnlySegments(flash_config_t *config, uint32_t key);
+
+/*@}*/
+
+/*!
+ * @name Programming
+ * @{
+ */
+
+/*!
+ * @brief Programs flash with data at locations passed in through parameters
+ *
+ * This function programs the flash memory with desired data for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be programmed. Must be
+ * word-aligned.
+ * @param src Pointer to the source buffer of data that is to be programmed
+ * into the flash.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * to be programmed. Must be word-aligned.
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FLASH_AddressError Address is out of range.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+status_t FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes);
+
+/*!
+ * @brief Programs Program Once Field through parameters
+ *
+ * This function programs the Program Once Field with desired data for a given
+ * flash area as determined by the index and length.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param index The index indicating which area of Program Once Field to be programmed.
+ * @param src Pointer to the source buffer of data that is to be programmed
+ * into the Program Once Field.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * to be programmed. Must be word-aligned.
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+status_t FLASH_ProgramOnce(flash_config_t *config, uint32_t index, uint32_t *src, uint32_t lengthInBytes);
+
+/*!
+ * @brief Programs flash with data at locations passed in through parameters via Program Section command
+ *
+ * This function programs the flash memory with desired data for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be programmed. Must be
+ * word-aligned.
+ * @param src Pointer to the source buffer of data that is to be programmed
+ * into the flash.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * to be programmed. Must be word-aligned.
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FLASH_AddressError Address is out of range.
+ * @retval #kStatus_FLASH_SetFlexramAsRamError Failed to set flexram as ram
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_RecoverFlexramAsEepromError Failed to recover flexram as eeprom
+ */
+#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD
+status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes);
+#endif
+
+/*!
+ * @brief Programs EEPROM with data at locations passed in through parameters
+ *
+ * This function programs the Emulated EEPROM with desired data for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be programmed. Must be
+ * word-aligned.
+ * @param src Pointer to the source buffer of data that is to be programmed
+ * into the flash.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * to be programmed. Must be word-aligned.
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_AddressError Address is out of range.
+ * @retval #kStatus_FLASH_SetFlexramAsEepromError Failed to set flexram as eeprom.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_RecoverFlexramAsRamError Failed to recover flexram as ram
+ */
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+status_t FLASH_EepromWrite(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes);
+#endif
+
+/*@}*/
+
+/*!
+ * @name Reading
+ * @{
+ */
+
+/*!
+ * @brief Read resource with data at locations passed in through parameters
+ *
+ * This function reads the flash memory with desired location for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be programmed. Must be
+ * word-aligned.
+ * @param dst Pointer to the destination buffer of data that is used to store
+ * data to be read.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * to be read. Must be word-aligned.
+ * @param option The resource option which indicates which area should be read back.
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD
+status_t FLASH_ReadResource(
+ flash_config_t *config, uint32_t start, uint32_t *dst, uint32_t lengthInBytes, flash_read_resource_option_t option);
+#endif
+
+/*!
+ * @brief Read Program Once Field through parameters
+ *
+ * This function reads the read once feild with given index and length
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param index The index indicating the area of program once field to be read.
+ * @param dst Pointer to the destination buffer of data that is used to store
+ * data to be read.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * to be programmed. Must be word-aligned.
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+status_t FLASH_ReadOnce(flash_config_t *config, uint32_t index, uint32_t *dst, uint32_t lengthInBytes);
+
+/*@}*/
+
+/*!
+ * @name Security
+ * @{
+ */
+
+/*!
+ * @brief Returns the security state via the pointer passed into the function
+ *
+ * This function retrieves the current Flash security status, including the
+ * security enabling state and the backdoor key enabling state.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param state Pointer to the value returned for the current security status code:
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ */
+status_t FLASH_GetSecurityState(flash_config_t *config, flash_security_state_t *state);
+
+/*!
+ * @brief Allows user to bypass security with a backdoor key
+ *
+ * If the MCU is in secured state, this function will unsecure the MCU by
+ * comparing the provided backdoor key with ones in the Flash Configuration
+ * Field.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param backdoorKey Pointer to the user buffer containing the backdoor key.
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+status_t FLASH_SecurityBypass(flash_config_t *config, const uint8_t *backdoorKey);
+
+/*@}*/
+
+/*!
+ * @name Verification
+ * @{
+ */
+
+/*!
+ * @brief Verifies erasure of entire flash at specified margin level
+ *
+ * This function will check to see if the flash have been erased to the
+ * specified read margin level.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param margin Read margin choice
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+status_t FLASH_VerifyEraseAll(flash_config_t *config, flash_margin_value_t margin);
+
+/*!
+ * @brief Verifies erasure of desired flash area at specified margin level
+ *
+ * This function will check the appropriate number of flash sectors based on
+ * the desired start address and length to see if the flash have been erased
+ * to the specified read margin level.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be verified.
+ * The start address does not need to be sector aligned but must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * to be verified. Must be word-aligned.
+ * @param margin Read margin choice
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FLASH_AddressError Address is out of range.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, flash_margin_value_t margin);
+
+/*!
+ * @brief Verifies programming of desired flash area at specified margin level
+ *
+ * This function verifies the data programed in the flash memory using the
+ * Flash Program Check Command and compares it with expected data for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be verified. Must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * to be verified. Must be word-aligned.
+ * @param expectedData Pointer to the expected data that is to be
+ * verified against.
+ * @param margin Read margin choice
+ * @param failedAddress Pointer to returned failing address.
+ * @param failedData Pointer to returned failing data. Some derivitives do
+ * not included failed data as part of the FCCOBx registers. In this
+ * case, zeros are returned upon failure.
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FLASH_AddressError Address is out of range.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+status_t FLASH_VerifyProgram(flash_config_t *config,
+ uint32_t start,
+ uint32_t lengthInBytes,
+ const uint32_t *expectedData,
+ flash_margin_value_t margin,
+ uint32_t *failedAddress,
+ uint32_t *failedData);
+
+/*!
+ * @brief Verifies if the program flash executeonly segments have been erased to
+ * the specified read margin level
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param margin Read margin choice
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+status_t FLASH_VerifyEraseAllExecuteOnlySegments(flash_config_t *config, flash_margin_value_t margin);
+
+/*@}*/
+
+/*!
+ * @name Protection
+ * @{
+ */
+
+/*!
+ * @brief Returns the protection state of desired flash area via the pointer passed into the function
+ *
+ * This function retrieves the current Flash protect status for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be checked. Must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * to be checked. Must be word-aligned.
+ * @param protection_state Pointer to the value returned for the current
+ * protection status code for the desired flash area.
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FLASH_AddressError Address is out of range.
+ */
+status_t FLASH_IsProtected(flash_config_t *config,
+ uint32_t start,
+ uint32_t lengthInBytes,
+ flash_protection_state_t *protection_state);
+
+/*!
+ * @brief Returns the access state of desired flash area via the pointer passed into the function
+ *
+ * This function retrieves the current Flash access status for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be checked. Must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * to be checked. Must be word-aligned.
+ * @param access_state Pointer to the value returned for the current
+ * access status code for the desired flash area.
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FLASH_AddressError Address is out of range.
+ */
+status_t FLASH_IsExecuteOnly(flash_config_t *config,
+ uint32_t start,
+ uint32_t lengthInBytes,
+ flash_execute_only_access_state_t *access_state);
+
+/*@}*/
+
+/*!
+ * @name Properties
+ * @{
+ */
+
+/*!
+ * @brief Returns the desired flash property.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param whichProperty The desired property from the list of properties in
+ * enum flash_property_tag_t
+ * @param value Pointer to the value returned for the desired flash property
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_UnknownProperty unknown property tag
+ */
+status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value);
+
+/*@}*/
+
+/*!
+ * @name FlexRAM
+ * @{
+ */
+
+/*!
+ * @brief Set FlexRAM Function command
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param option The option used to set work mode of FlexRAM
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
+status_t FLASH_SetFlexramFunction(flash_config_t *config, flash_flexram_function_option_t option);
+#endif
+
+/*@}*/
+
+/*!
+ * @name Swap
+ * @{
+ */
+
+/*!
+ * @brief Configure Swap function or Check the swap state of Flash Module
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param address Address used to configure the flash swap function
+ * @param option The possible option used to configure Flash Swap function or check the flash swap status
+ * @param returnInfo Pointer to the data which is used to return the information of flash swap.
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FLASH_SwapIndicatorAddressError Swap indicator address is invalid
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD
+status_t FLASH_SwapControl(flash_config_t *config,
+ uint32_t address,
+ flash_swap_control_option_t option,
+ flash_swap_state_config_t *returnInfo);
+#endif
+
+/*!
+ * @brief Swap the lower half flash with the higher half flaock
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param address Address used to configure the flash swap function
+ * @param option The possible option used to configure Flash Swap function or check the flash swap status
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FLASH_SwapIndicatorAddressError Swap indicator address is invalid
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_SwapSystemNotInUninitialized Swap system is not in uninitialzed state
+ */
+#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP
+status_t FLASH_Swap(flash_config_t *config, uint32_t address, flash_swap_function_option_t option);
+#endif
+
+/*!
+ * @name FlexNVM
+ * @{
+ */
+
+/*!
+ * @brief Prepares the FlexNVM block for use as data flash, EEPROM backup, or a combination of both and initializes the
+ * FlexRAM.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param option The option used to set FlexRAM load behavior during reset.
+ * @param eepromDataSizeCode Determines the amount of FlexRAM used in each of the available EEPROM subsystems.
+ * @param flexnvmPartitionCode Specifies how to split the FlexNVM block between data flash memory and EEPROM backup
+ * memory supporting EEPROM functions.
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD
+status_t FLASH_ProgramPartition(flash_config_t *config,
+ flash_partition_flexram_load_option_t option,
+ uint32_t eepromDataSizeCode,
+ uint32_t flexnvmPartitionCode);
+#endif
+
+/*@}*/
+
+/*!
+* @name Flash Protection Utilities
+* @{
+*/
+
+/*!
+ * @brief Set PFLASH Protection to the intended protection status.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param protectStatus The expected protect status user wants to set to PFlash protection register. Each bit is
+ * corresponding to protection of 1/32 of the total PFlash. The least significant bit is corresponding to the lowest
+ * address area of P-Flash. The most significant bit is corresponding to the highest address area of PFlash. There are
+ * two possible cases as shown below:
+ * 0: this area is protected.
+ * 1: this area is unprotected.
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+status_t FLASH_PflashSetProtection(flash_config_t *config, uint32_t protectStatus);
+
+/*!
+ * @brief Get PFLASH Protection Status.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param protectStatus Protect status returned by PFlash IP. Each bit is corresponding to protection of 1/32 of the
+ * total PFlash. The least significant bit is corresponding to the lowest address area of PFlash. The most significant
+ * bit is corresponding to the highest address area of PFlash. Thee are two possible cases as below:
+ * 0: this area is protected.
+ * 1: this area is unprotected.
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ */
+status_t FLASH_PflashGetProtection(flash_config_t *config, uint32_t *protectStatus);
+
+/*!
+ * @brief Set DFLASH Protection to the intended protection status.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param protectStatus The expected protect status user wants to set to DFlash protection register. Each bit is
+ * corresponding to protection of 1/8 of the total DFlash. The least significant bit is corresponding to the lowest
+ * address area of DFlash. The most significant bit is corresponding to the highest address area of DFlash. There are
+ * two possible cases as shown below:
+ * 0: this area is protected.
+ * 1: this area is unprotected.
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_CommandNotSupported Flash api is not supported
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+status_t FLASH_DflashSetProtection(flash_config_t *config, uint8_t protectStatus);
+#endif
+
+/*!
+ * @brief Get DFLASH Protection Status.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param protectStatus DFlash Protect status returned by PFlash IP. Each bit is corresponding to protection of 1/8 of
+ * the total DFlash. The least significant bit is corresponding to the lowest address area of DFlash. The most
+ * significant bit is corresponding to the highest address area of DFlash and so on. There are two possible cases as
+ * below:
+ * 0: this area is protected.
+ * 1: this area is unprotected.
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_CommandNotSupported Flash api is not supported
+ */
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+status_t FLASH_DflashGetProtection(flash_config_t *config, uint8_t *protectStatus);
+#endif
+
+/*!
+ * @brief Set EEPROM Protection to the intended protection status.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param protectStatus The expected protect status user wants to set to EEPROM protection register. Each bit is
+ * corresponding to protection of 1/8 of the total EEPROM. The least significant bit is corresponding to the lowest
+ * address area of EEPROM. The most significant bit is corresponding to the highest address area of EEPROM, and so on.
+ * There are two possible cases as shown below:
+ * 0: this area is protected.
+ * 1: this area is unprotected.
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_CommandNotSupported Flash api is not supported
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+status_t FLASH_EepromSetProtection(flash_config_t *config, uint8_t protectStatus);
+#endif
+
+/*!
+ * @brief Get DFLASH Protection Status.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param protectStatus DFlash Protect status returned by PFlash IP. Each bit is corresponding to protection of 1/8 of
+ * the total EEPROM. The least significant bit is corresponding to the lowest address area of EEPROM. The most
+ * significant bit is corresponding to the highest address area of EEPROM. There are two possible cases as below:
+ * 0: this area is protected.
+ * 1: this area is unprotected.
+ *
+ * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_CommandNotSupported Flash api is not supported.
+ */
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+status_t FLASH_EepromGetProtection(flash_config_t *config, uint8_t *protectStatus);
+#endif
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_FLASH_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k20dx/DAP_config.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k20dx/DAP_config.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,495 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date: 1. December 2017
+ * $Revision: V2.0.0
+ *
+ * Project: CMSIS-DAP Configuration
+ * Title: DAP_config.h CMSIS-DAP Configuration File (Template)
+ *
+ *---------------------------------------------------------------------------*/
+
+#ifndef __DAP_CONFIG_H__
+#define __DAP_CONFIG_H__
+
+#include "IO_Config.h"
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
+\ingroup DAP_ConfigIO_gr
+@{
+Provides definitions about the hardware and configuration of the Debug Unit.
+
+This information includes:
+ - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
+ - Debug Unit Identification strings (Vendor, Product, Serial Number).
+ - Debug Unit communication packet size.
+ - Debug Access Port supported modes and settings (JTAG/SWD and SWO).
+ - Optional information about a connected Target Device (for Evaluation Boards).
+*/
+
+/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
+/// This value is used to calculate the SWD/JTAG clock speed.
+#define CPU_CLOCK SystemCoreClock ///< Specifies the CPU Clock in Hz.
+
+/// Number of processor cycles for I/O Port write operations.
+/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
+/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
+/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
+/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
+/// required.
+#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0.
+
+/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available.
+
+/// Indicate that JTAG communication mode is available at the Debug Port.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available.
+
+/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
+/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
+#define DAP_JTAG_DEV_CNT 0 ///< Maximum number of JTAG devices on scan chain.
+
+/// Default communication mode on the Debug Access Port.
+/// Used for the command \ref DAP_Connect when Port Default mode is selected.
+#define DAP_DEFAULT_PORT 1U ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
+
+/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
+/// Used to initialize the default SWD/JTAG clock frequency.
+/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
+#define DAP_DEFAULT_SWJ_CLOCK 1000000U ///< Default SWD/JTAG clock frequency in Hz.
+
+/// Maximum Package Size for Command and Response data.
+/// This configuration settings is used to optimize the communication performance with the
+/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB,
+/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB.
+#define DAP_PACKET_SIZE 64U ///< Specifies Packet Size in bytes.
+
+/// Maximum Package Buffers for Command and Response data.
+/// This configuration settings is used to optimize the communication performance with the
+/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
+/// setting can be reduced (valid range is 1 .. 255).
+#define DAP_PACKET_COUNT 5U ///< Specifies number of packets buffered.
+
+/// Indicate that UART Serial Wire Output (SWO) trace is available.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available.
+
+/// Maximum SWO UART Baudrate.
+#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz.
+
+/// Indicate that Manchester Serial Wire Output (SWO) trace is available.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available.
+
+/// SWO Trace Buffer Size.
+#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n).
+
+/// SWO Streaming Trace.
+#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available.
+
+/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
+#define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported).
+
+/// Debug Unit is connected to fixed Target Device.
+/// The Debug Unit may be part of an evaluation board and always connected to a fixed
+/// known device. In this case a Device Vendor and Device Name string is stored which
+/// may be used by the debugger or IDE to configure device parameters.
+#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
+
+#if TARGET_DEVICE_FIXED
+#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor
+#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device
+#endif
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
+\ingroup DAP_ConfigIO_gr
+@{
+
+Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
+and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
+interface of a device. The following I/O Pins are provided:
+
+JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
+---------------------------- | -------------------- | ---------------------------------------------
+TCK: Test Clock | SWCLK: Clock | Output Push/Pull
+TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
+TDI: Test Data Input | | Output Push/Pull
+TDO: Test Data Output | | Input
+nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
+nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
+
+
+DAP Hardware I/O Pin Access Functions
+-------------------------------------
+The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
+these I/O Pins.
+
+For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
+This functions are provided to achieve faster I/O that is possible with some advanced GPIO
+peripherals that can independently write/read a single I/O pin without affecting any other pins
+of the same I/O port. The following SWDIO I/O Pin functions are provided:
+ - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
+ - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
+ - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
+ - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
+*/
+
+
+// Configure DAP I/O pins ------------------------------
+
+/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
+Configures the DAP Hardware I/O pins for JTAG mode:
+ - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
+ - TDO to input mode.
+*/
+__STATIC_INLINE void PORT_JTAG_SETUP (void) {
+ ;
+}
+
+/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
+Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
+ - SWCLK, SWDIO, nRESET to output mode and set to default high level.
+ - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
+*/
+__STATIC_INLINE void PORT_SWD_SETUP(void)
+{
+ PIN_SWCLK_GPIO->PSOR = 1 << PIN_SWCLK_BIT;
+ PIN_SWDIO_OUT_GPIO->PSOR = 1 << PIN_SWDIO_OUT_BIT;
+ PIN_SWDIO_NOE_GPIO->PCOR = 1 << PIN_SWDIO_NOE_BIT;
+ PIN_SWD_NOE_GPIO->PCOR = 1 << PIN_SWD_NOE_BIT;
+ PIN_nRESET_GPIO->PSOR = 1 << PIN_nRESET_BIT;
+ PIN_SWD_NOE_GPIO->PDDR = PIN_SWD_NOE_GPIO->PDDR | (1 << PIN_SWD_NOE_BIT);
+ PIN_SWD_NOE_GPIO->PCOR = 1 << PIN_SWD_NOE_BIT;
+ PIN_SWDIO_NOE_GPIO->PCOR = 1 << PIN_SWDIO_NOE_BIT;
+ PIN_nRESET_GPIO->PSOR = PIN_nRESET;
+ PIN_nRESET_GPIO->PDDR |= PIN_nRESET; //output
+ PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_PFE_MASK | PORT_PCR_MUX(1);
+}
+
+/** Disable JTAG/SWD I/O Pins.
+Disables the DAP Hardware I/O pins which configures:
+ - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
+*/
+__STATIC_INLINE void PORT_OFF(void)
+{
+ PIN_SWDIO_NOE_GPIO->PSOR = 1 << PIN_SWDIO_NOE_BIT;
+ PIN_SWD_NOE_GPIO->PSOR = 1 << PIN_SWD_NOE_BIT;
+ PIN_nRESET_GPIO->PSOR = 1 << PIN_nRESET_BIT;
+ PIN_nRESET_GPIO->PDDR &= ~PIN_nRESET; //input
+ PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] |= PORT_PCR_ISF_MASK;
+ PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_PFE_MASK | PORT_PCR_MUX(1);
+}
+
+
+// SWCLK/TCK I/O pin -------------------------------------
+
+/** SWCLK/TCK I/O pin: Get Input.
+\return Current status of the SWCLK/TCK DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void) {
+ return (0U);
+}
+
+/** SWCLK/TCK I/O pin: Set Output to High.
+Set the SWCLK/TCK DAP hardware I/O pin to high level.
+*/
+__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET(void)
+{
+ PIN_SWCLK_GPIO->PSOR = 1 << PIN_SWCLK_BIT;
+}
+
+/** SWCLK/TCK I/O pin: Set Output to Low.
+Set the SWCLK/TCK DAP hardware I/O pin to low level.
+*/
+__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void)
+{
+ PIN_SWCLK_GPIO->PCOR = 1 << PIN_SWCLK_BIT;
+}
+
+
+// SWDIO/TMS Pin I/O --------------------------------------
+
+/** SWDIO/TMS I/O pin: Get Input.
+\return Current status of the SWDIO/TMS DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void)
+{
+ return ((PIN_SWDIO_IN_GPIO->PDIR >> PIN_SWDIO_IN_BIT) & 1);
+}
+
+/** SWDIO/TMS I/O pin: Set Output to High.
+Set the SWDIO/TMS DAP hardware I/O pin to high level.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET(void)
+{
+ PIN_SWDIO_OUT_GPIO->PSOR = 1 << PIN_SWDIO_OUT_BIT;
+}
+
+/** SWDIO/TMS I/O pin: Set Output to Low.
+Set the SWDIO/TMS DAP hardware I/O pin to low level.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void)
+{
+ PIN_SWDIO_OUT_GPIO->PCOR = 1 << PIN_SWDIO_OUT_BIT;
+}
+
+/** SWDIO I/O pin: Get Input (used in SWD mode only).
+\return Current status of the SWDIO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
+{
+ return (BITBAND_REG(PIN_SWDIO_IN_GPIO->PDIR, PIN_SWDIO_IN_BIT));
+}
+
+/** SWDIO I/O pin: Set Output (used in SWD mode only).
+\param bit Output value for the SWDIO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT(uint32_t bit)
+{
+ BITBAND_REG(PIN_SWDIO_OUT_GPIO->PDOR, PIN_SWDIO_OUT_BIT) = bit;
+}
+
+/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
+Configure the SWDIO DAP hardware I/O pin to output mode. This function is
+called prior \ref PIN_SWDIO_OUT function calls.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void)
+{
+ PIN_SWDIO_NOE_GPIO->PCOR = 1 << PIN_SWDIO_NOE_BIT;
+}
+
+/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
+Configure the SWDIO DAP hardware I/O pin to input mode. This function is
+called prior \ref PIN_SWDIO_IN function calls.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void)
+{
+ PIN_SWDIO_NOE_GPIO->PSOR = 1 << PIN_SWDIO_NOE_BIT;
+}
+
+
+// TDI Pin I/O ---------------------------------------------
+
+/** TDI I/O pin: Get Input.
+\return Current status of the TDI DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_TDI_IN (void) {
+ return (0U);
+}
+
+/** TDI I/O pin: Set Output.
+\param bit Output value for the TDI DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE void PIN_TDI_OUT (uint32_t bit) {
+ ;
+}
+
+
+// TDO Pin I/O ---------------------------------------------
+
+/** TDO I/O pin: Get Input.
+\return Current status of the TDO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_TDO_IN (void) {
+ return (0U);
+}
+
+
+// nTRST Pin I/O -------------------------------------------
+
+/** nTRST I/O pin: Get Input.
+\return Current status of the nTRST DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN (void) {
+ return (0U);
+}
+
+/** nTRST I/O pin: Set Output.
+\param bit JTAG TRST Test Reset pin status:
+ - 0: issue a JTAG TRST Test Reset.
+ - 1: release JTAG TRST Test Reset.
+*/
+__STATIC_FORCEINLINE void PIN_nTRST_OUT (uint32_t bit) {
+ ;
+}
+
+// nRESET Pin I/O------------------------------------------
+
+/** nRESET I/O pin: Get Input.
+\return Current status of the nRESET DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void)
+{
+ return ((PIN_nRESET_GPIO->PDIR >> PIN_nRESET_BIT) & 1);
+}
+
+/** nRESET I/O pin: Set Output.
+\param bit target device hardware reset pin status:
+ - 0: issue a device hardware reset.
+ - 1: release device hardware reset.
+*/
+__STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit)
+{
+ BITBAND_REG(PIN_nRESET_GPIO->PDOR, PIN_nRESET_BIT) = bit;
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
+\ingroup DAP_ConfigIO_gr
+@{
+
+CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
+
+It is recommended to provide the following LEDs for status indication:
+ - Connect LED: is active when the DAP hardware is connected to a debugger.
+ - Running LED: is active when the debugger has put the target device into running state.
+*/
+
+/** Debug Unit: Set status of Connected LED.
+\param bit status of the Connect LED.
+ - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
+ - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
+*/
+__STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit)
+{
+ BITBAND_REG(LED_CONNECTED_GPIO->PDOR, LED_CONNECTED_BIT) = ~bit;
+}
+
+/** Debug Unit: Set status Target Running LED.
+\param bit status of the Target Running LED.
+ - 1: Target Running LED ON: program execution in target started.
+ - 0: Target Running LED OFF: program execution in target stopped.
+*/
+__STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
+\ingroup DAP_ConfigIO_gr
+@{
+Access function for Test Domain Timer.
+
+The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
+default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
+
+*/
+
+/** Get timestamp of Test Domain Timer.
+\return Current timestamp value.
+*/
+__STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
+ return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK);
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
+\ingroup DAP_ConfigIO_gr
+@{
+
+CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
+*/
+
+/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
+This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
+Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
+ - I/O clock system enabled.
+ - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
+ - for nTRST, nRESET a weak pull-up (if available) is enabled.
+ - LED output pins are enabled and LEDs are turned off.
+*/
+__STATIC_INLINE void DAP_SETUP(void)
+{
+ SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK | /* Enable Port A Clock */
+ SIM_SCGC5_PORTB_MASK | /* Enable Port B Clock */
+ SIM_SCGC5_PORTC_MASK | /* Enable Port C Clock */
+ SIM_SCGC5_PORTD_MASK; /* Enable Port D Clock */
+ /* Configure I/O pin SWCLK */
+ PIN_SWCLK_PORT->PCR[PIN_SWCLK_BIT] = PORT_PCR_MUX(1) | /* GPIO */
+ PORT_PCR_DSE_MASK; /* High drive strength */
+ PIN_SWCLK_GPIO->PSOR = 1 << PIN_SWCLK_BIT; /* High level */
+ PIN_SWCLK_GPIO->PDDR |= 1 << PIN_SWCLK_BIT; /* Output */
+ /* Configure I/O pin SWDIO_OUT */
+ PIN_SWDIO_OUT_PORT->PCR[PIN_SWDIO_OUT_BIT] = PORT_PCR_MUX(1) | /* GPIO */
+ PORT_PCR_DSE_MASK; /* High drive strength */
+ PIN_SWDIO_OUT_GPIO->PSOR = 1 << PIN_SWDIO_OUT_BIT; /* High level */
+ PIN_SWDIO_OUT_GPIO->PDDR |= 1 << PIN_SWDIO_OUT_BIT; /* Output */
+ /* Configure I/O pin SWDIO_IN */
+ PIN_SWDIO_IN_PORT->PCR[PIN_SWDIO_IN_BIT] = PORT_PCR_MUX(1) | /* GPIO */
+ PORT_PCR_PE_MASK | /* Pull enable */
+ PORT_PCR_PS_MASK; /* Pull-up */
+ PIN_SWDIO_IN_GPIO->PDDR &= ~(1 << PIN_SWDIO_IN_BIT); /* Input */
+ /* Configure I/O pin SWDIO_NOE */
+ PIN_SWDIO_NOE_PORT->PCR[PIN_SWDIO_NOE_BIT] = PORT_PCR_MUX(1) | /* GPIO */
+ PORT_PCR_DSE_MASK; /* High drive strength */
+ PIN_SWDIO_NOE_GPIO->PSOR = 1 << PIN_SWDIO_NOE_BIT; /* High level */
+ PIN_SWDIO_NOE_GPIO->PDDR |= 1 << PIN_SWDIO_NOE_BIT; /* Output */
+ /* Configure I/O pin SWD_NOE */
+ PIN_SWD_NOE_PORT->PCR[PIN_SWD_NOE_BIT] = PORT_PCR_MUX(1) | /* GPIO */
+ PORT_PCR_DSE_MASK; /* High drive strength */
+ PIN_SWD_NOE_GPIO->PSOR = 1 << PIN_SWD_NOE_BIT; /* High level */
+ PIN_SWD_NOE_GPIO->PDDR |= 1 << PIN_SWD_NOE_BIT; /* Output */
+ /* Configure I/O pin nRESET */
+ PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_MUX(1) | /* GPIO */
+ PORT_PCR_PE_MASK | /* Pull enable */
+ PORT_PCR_PS_MASK | /* Pull-up */
+ PORT_PCR_ODE_MASK; /* Open-drain */
+ PIN_nRESET_GPIO->PSOR = 1 << PIN_nRESET_BIT; /* High level */
+ PIN_nRESET_GPIO->PDDR &= ~(1 << PIN_nRESET_BIT); /* Input */
+ /* Configure LED */
+ LED_CONNECTED_PORT->PCR[LED_CONNECTED_BIT] = PORT_PCR_MUX(1) | /* GPIO */
+ PORT_PCR_ODE_MASK; /* Open-drain */
+ LED_CONNECTED_GPIO->PCOR = 1 << LED_CONNECTED_BIT; /* Turned on */
+ LED_CONNECTED_GPIO->PDDR |= 1 << LED_CONNECTED_BIT; /* Output */
+}
+
+/** Reset Target Device with custom specific I/O pin or command sequence.
+This function allows the optional implementation of a device specific reset sequence.
+It is called when the command \ref DAP_ResetTarget and is for example required
+when a device needs a time-critical unlock sequence that enables the debug port.
+\return 0 = no device specific reset sequence is implemented.\n
+ 1 = a device specific reset sequence is implemented.
+*/
+__STATIC_INLINE uint8_t RESET_TARGET (void) {
+ return (0U); // change to '1' when a device reset sequence is implemented
+}
+
+///@}
+
+
+#endif /* __DAP_CONFIG_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k20dx/IO_Config.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/freescale/k20dx/IO_Config.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,114 @@ +/** + * @file IO_Config.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ + +#include "MK20D5.h" +#include "compiler.h" +#include "daplink.h" + +// This GPIO configuration is only valid for the K20DX HIC +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_K20DX); + + +// Debug Port I/O Pins + +// SWCLK Pin PTC5 +#define PIN_SWCLK_PORT PORTC +#define PIN_SWCLK_GPIO PTC +#define PIN_SWCLK_BIT 5 + +// SWDIO Out Pin PTC6 +#define PIN_SWDIO_OUT_PORT PORTC +#define PIN_SWDIO_OUT_GPIO PTC +#define PIN_SWDIO_OUT_BIT 6 + +// SWDIO In Pin PTC7 +#define PIN_SWDIO_IN_PORT PORTC +#define PIN_SWDIO_IN_GPIO PTC +#define PIN_SWDIO_IN_BIT 7 + +// SWDIO Neg. Output Enable Pin PTB0 +#define PIN_SWDIO_NOE_PORT PORTB +#define PIN_SWDIO_NOE_GPIO PTB +#define PIN_SWDIO_NOE_BIT 0 + +// SWD Neg. Enable Pin PTA4 +#define PIN_SWD_NOE_PORT PORTA +#define PIN_SWD_NOE_GPIO PTA +#define PIN_SWD_NOE_BIT 4 + +// nRESET Pin PTB1 +#define PIN_nRESET_PORT PORTB +#define PIN_nRESET_GPIO PTB +#define PIN_nRESET_BIT 1 +#define PIN_nRESET (1 << PIN_nRESET_BIT) + +// Power and fault detection + +// PWR_REG_EN PTD2 PTD6 +#define PIN_POWER_EN_PORT PORTD +#define PIN_POWER_EN_GPIO PTD +#define PIN_POWER_EN_BIT (6) +#define PIN_POWER_EN (1<<PIN_POWER_EN_BIT) + +// VTRG_FAULT_B PTD7 +#define PIN_VTRG_FAULT_B_PORT PORTD +#define PIN_VTRG_FAULT_B_GPIO PTD +#define PIN_VTRG_FAULT_B_BIT (7) + +// Debug Unit LEDs + +// Connected LED PTD4 +#define LED_CONNECTED_PORT PORTD +#define LED_CONNECTED_GPIO PTD +#define LED_CONNECTED_BIT 4 + +// Target Running LED Not available + +// Debug Unit LEDs + +// HID_LED PTD4 +#define PIN_HID_LED_PORT PORTD +#define PIN_HID_LED_GPIO PTD +#define PIN_HID_LED_BIT (4) +#define PIN_HID_LED (1<<PIN_HID_LED_BIT) + +// MSC_LED PTD4 +#define PIN_MSC_LED_PORT PORTD +#define PIN_MSC_LED_GPIO PTD +#define PIN_MSC_LED_BIT (4) +#define PIN_MSC_LED (1<<PIN_HID_LED_BIT) + +// CDC_LED PTD4 +#define PIN_CDC_LED_PORT PORTD +#define PIN_CDC_LED_GPIO PTD +#define PIN_CDC_LED_BIT (4) +#define PIN_CDC_LED (1<<PIN_HID_LED_BIT) + +// SW RESET BUTTON PTB1 +#define PIN_SW_RESET_PORT PORTB +#define PIN_SW_RESET_GPIO PTB +#define PIN_SW_RESET_BIT (1) +#define PIN_SW_RESET (1<<PIN_SW_RESET_BIT) + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k20dx/MK20D5/MK20D5.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k20dx/MK20D5/MK20D5.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,7732 @@
+/*
+** ###################################################################
+** Compilers: Keil ARM C/C++ Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011
+** K20P32M50SF0RM Rev. 1, Oct 2011
+** K20P48M50SF0RM Rev. 1, Oct 2011
+**
+** Version: rev. 3.4, 2013-10-29
+** Build: b151120
+**
+** Abstract:
+** CMSIS Peripheral Access Layer for MK20D5
+**
+** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 2.0 (2011-11-07)
+** Initial public version.
+** - rev. 2.1 (2011-12-13)
+** Removed registers for AIPS and AXBS modules.
+** - rev. 3.0 (2012-03-19)
+** PDB Peripheral register structure updated.
+** DMA Registers and bits for unsupported DMA channels removed.
+** - rev. 3.1 (2012-04-13)
+** Added new #define symbol MCU_MEM_MAP_VERSION_MINOR.
+** Added new #define symbols <peripheralType>_BASE_PTRS.
+** - rev. 3.2 (2013-04-05)
+** Changed start of doxygen comment.
+** - rev. 3.3 (2013-06-24)
+** NV_FOPT register - NMI_DIS bit added.
+** - rev. 3.4 (2013-10-29)
+** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK20D5.h
+ * @version 3.4
+ * @date 2013-10-29
+ * @brief CMSIS Peripheral Access Layer for MK20D5
+ *
+ * CMSIS Peripheral Access Layer for MK20D5
+ */
+
+#ifndef _MK20D5_H_
+#define _MK20D5_H_ /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0300U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0004U
+
+/**
+ * @brief Macro to calculate address of an aliased word in the peripheral
+ * bitband area for a peripheral register and bit (bit band region 0x40000000 to
+ * 0x400FFFFF).
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Address of the aliased word in the peripheral bitband area.
+ */
+#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ * be used for peripherals with 32bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
+#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ * be used for peripherals with 16bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ * be used for peripherals with 8bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 62 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+ /* Auxiliary constants */
+ NotAvail_IRQn = -128, /**< Not available device specific interrupt */
+
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */
+ DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */
+ DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */
+ DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */
+ DMA_Error_IRQn = 4, /**< DMA error interrupt */
+ Reserved21_IRQn = 5, /**< Reserved interrupt 21 */
+ FTFL_IRQn = 6, /**< FTFL interrupt */
+ Read_Collision_IRQn = 7, /**< Read collision interrupt */
+ LVD_LVW_IRQn = 8, /**< Low Voltage Detect, Low Voltage Warning */
+ LLW_IRQn = 9, /**< Low Leakage Wakeup */
+ Watchdog_IRQn = 10, /**< WDOG interrupt */
+ I2C0_IRQn = 11, /**< I2C0 interrupt */
+ SPI0_IRQn = 12, /**< SPI0 interrupt */
+ I2S0_Tx_IRQn = 13, /**< I2S0 transmit interrupt */
+ I2S0_Rx_IRQn = 14, /**< I2S0 receive interrupt */
+ UART0_LON_IRQn = 15, /**< UART0 LON interrupt */
+ UART0_RX_TX_IRQn = 16, /**< UART0 receive/transmit interrupt */
+ UART0_ERR_IRQn = 17, /**< UART0 error interrupt */
+ UART1_RX_TX_IRQn = 18, /**< UART1 receive/transmit interrupt */
+ UART1_ERR_IRQn = 19, /**< UART1 error interrupt */
+ UART2_RX_TX_IRQn = 20, /**< UART2 receive/transmit interrupt */
+ UART2_ERR_IRQn = 21, /**< UART2 error interrupt */
+ ADC0_IRQn = 22, /**< ADC0 interrupt */
+ CMP0_IRQn = 23, /**< CMP0 interrupt */
+ CMP1_IRQn = 24, /**< CMP1 interrupt */
+ FTM0_IRQn = 25, /**< FTM0 fault, overflow and channels interrupt */
+ FTM1_IRQn = 26, /**< FTM1 fault, overflow and channels interrupt */
+ CMT_IRQn = 27, /**< CMT interrupt */
+ RTC_IRQn = 28, /**< RTC interrupt */
+ RTC_Seconds_IRQn = 29, /**< RTC seconds interrupt */
+ PIT0_IRQn = 30, /**< PIT timer channel 0 interrupt */
+ PIT1_IRQn = 31, /**< PIT timer channel 1 interrupt */
+ PIT2_IRQn = 32, /**< PIT timer channel 2 interrupt */
+ PIT3_IRQn = 33, /**< PIT timer channel 3 interrupt */
+ PDB0_IRQn = 34, /**< PDB0 interrupt */
+ USB0_IRQn = 35, /**< USB0 interrupt */
+ USBDCD_IRQn = 36, /**< USBDCD interrupt */
+ TSI0_IRQn = 37, /**< TSI0 interrupt */
+ MCG_IRQn = 38, /**< MCG interrupt */
+ LPTimer_IRQn = 39, /**< LPTimer interrupt */
+ PORTA_IRQn = 40, /**< Port A interrupt */
+ PORTB_IRQn = 41, /**< Port B interrupt */
+ PORTC_IRQn = 42, /**< Port C interrupt */
+ PORTD_IRQn = 43, /**< Port D interrupt */
+ PORTE_IRQn = 44, /**< Port E interrupt */
+ SWI_IRQn = 45 /**< Software interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M4 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT 0 /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h" /* Core Peripheral Access Layer */
+#include "system_MK20D5.h" /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Mapping Information
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup edma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according to the to SoC.
+ */
+typedef enum _dma_request_source
+{
+ #if defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
+ defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
+ defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
+ defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \
+ defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \
+ defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
+ defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \
+ defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5)
+ kDmaRequestMux0SoftwareDMARequest = 0|0x100U, /**< Disable */
+ kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */
+ kDmaRequestMux0UART0ReceiveDMARequest = 2|0x100U, /**< UART0 Receive. */
+ kDmaRequestMux0UART0TransmitDMARequest = 3|0x100U, /**< UART0 Transmit. */
+ kDmaRequestMux0UART1ReceiveDMARequest = 4|0x100U, /**< UART1 Receive. */
+ kDmaRequestMux0UART1TransmitDMARequest = 5|0x100U, /**< UART1 Transmit. */
+ kDmaRequestMux0UART2ReceiveDMARequest = 6|0x100U, /**< UART2 Receive. */
+ kDmaRequestMux0UART2TransmitDMARequest = 7|0x100U, /**< UART2 Transmit. */
+ kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */
+ kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */
+ kDmaRequestMux0Reserved10 = 10|0x100U, /**< Reserved10 */
+ kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */
+ kDmaRequestMux0Reserved12 = 12|0x100U, /**< Reserved12 */
+ kDmaRequestMux0Reserved13 = 13|0x100U, /**< Reserved13 */
+ kDmaRequestMux0I2S0ReceiveDMARequest = 14|0x100U, /**< I2S0 Receive. */
+ kDmaRequestMux0I2S0TransmitDMARequest = 15|0x100U, /**< I2S0 Transmit. */
+ kDmaRequestMux0SPI0ReceiveDMARequest = 16|0x100U, /**< SPI0 Receive. */
+ kDmaRequestMux0SPI0TransmitDMARequest = 17|0x100U, /**< SPI0 Transmit. */
+ kDmaRequestMux0Reserved18 = 18|0x100U, /**< Reserved18 */
+ kDmaRequestMux0Reserved19 = 19|0x100U, /**< Reserved19 */
+ kDmaRequestMux0Reserved20 = 20|0x100U, /**< Reserved20 */
+ kDmaRequestMux0Reserved21 = 21|0x100U, /**< Reserved21 */
+ kDmaRequestMux0I2C0DMARequest = 22|0x100U, /**< I2C0. */
+ kDmaRequestMux0Reserved23 = 23|0x100U, /**< Reserved23 */
+ kDmaRequestMux0FTM0C0DMARequest = 24|0x100U, /**< FTM0 channel 0. */
+ kDmaRequestMux0FTM0C1DMARequest = 25|0x100U, /**< FTM0 channel 1. */
+ kDmaRequestMux0FTM0C2DMARequest = 26|0x100U, /**< FTM0 channel 2. */
+ kDmaRequestMux0FTM0C3DMARequest = 27|0x100U, /**< FTM0 channel 3. */
+ kDmaRequestMux0FTM0C4DMARequest = 28|0x100U, /**< FTM0 channel 4. */
+ kDmaRequestMux0FTM0C5DMARequest = 29|0x100U, /**< FTM0 channel 5. */
+ kDmaRequestMux0FTM0C6DMARequest = 30|0x100U, /**< FTM0 channel 6. */
+ kDmaRequestMux0FTM0C7DMARequest = 31|0x100U, /**< FTM0 channel 7. */
+ kDmaRequestMux0FTM1C0DMARequest = 32|0x100U, /**< FTM1 channel 0. */
+ kDmaRequestMux0FTM1C1DMARequest = 33|0x100U, /**< FTM1 channel 1. */
+ kDmaRequestMux0Reserved34 = 34|0x100U, /**< Reserved34 */
+ kDmaRequestMux0Reserved35 = 35|0x100U, /**< Reserved35 */
+ kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */
+ kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */
+ kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */
+ kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */
+ kDmaRequestMux0ADC0DMARequest = 40|0x100U, /**< ADC0. */
+ kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */
+ kDmaRequestMux0CMP0DMARequest = 42|0x100U, /**< CMP0. */
+ kDmaRequestMux0CMP1DMARequest = 43|0x100U, /**< CMP1. */
+ kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */
+ kDmaRequestMux0Reserved45 = 45|0x100U, /**< Reserved45 */
+ kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */
+ kDmaRequestMux0CMTDMARequest = 47|0x100U, /**< CMT. */
+ kDmaRequestMux0PDBDMARequest = 48|0x100U, /**< PDB. */
+ kDmaRequestMux0GPIOPortADMARequest = 49|0x100U, /**< GPIO Port A. */
+ kDmaRequestMux0GPIOPortBDMARequest = 50|0x100U, /**< GPIO Port B. */
+ kDmaRequestMux0GPIOPortCDMARequest = 51|0x100U, /**< GPIO Port C. */
+ kDmaRequestMux0GPIOPortDDMARequest = 52|0x100U, /**< GPIO Port D. */
+ kDmaRequestMux0GPIOPortEDMARequest = 53|0x100U, /**< GPIO Port E. */
+ kDmaRequestMux0AlwaysEnabledslot54DMARequest = 54|0x100U, /**< Always enabled. */
+ kDmaRequestMux0AlwaysEnabledslot55DMARequest = 55|0x100U, /**< Always enabled. */
+ kDmaRequestMux0AlwaysEnabledslot56DMARequest = 56|0x100U, /**< Always enabled. */
+ kDmaRequestMux0AlwaysEnabledslot57DMARequest = 57|0x100U, /**< Always enabled. */
+ kDmaRequestMux0AlwaysEnabledslot58DMARequest = 58|0x100U, /**< Always enabled. */
+ kDmaRequestMux0AlwaysEnabledslot59DMARequest = 59|0x100U, /**< Always enabled. */
+ kDmaRequestMux0AlwaysEnabledslot60DMARequest = 60|0x100U, /**< Always enabled. */
+ kDmaRequestMux0AlwaysEnabledslot61DMARequest = 61|0x100U, /**< Always enabled. */
+ kDmaRequestMux0AlwaysEnabledslot62DMARequest = 62|0x100U, /**< Always enabled. */
+ kDmaRequestMux0AlwaysEnabledslot63DMARequest = 63|0x100U, /**< Always enabled. */
+ #else
+ #error "No valid CPU defined!"
+ #endif
+} dma_request_source_t;
+
+/* @} */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */
+ __IO uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */
+ __IO uint32_t CFG2; /**< Configuration register 2, offset: 0xC */
+ __I uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t CV1; /**< Compare value registers, offset: 0x18 */
+ __IO uint32_t CV2; /**< Compare value registers, offset: 0x1C */
+ __IO uint32_t SC2; /**< Status and control register 2, offset: 0x20 */
+ __IO uint32_t SC3; /**< Status and control register 3, offset: 0x24 */
+ __IO uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */
+ __IO uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */
+ __IO uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */
+ __IO uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */
+ __IO uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */
+ __IO uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */
+ __IO uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */
+ __IO uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */
+ __IO uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */
+ __IO uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */
+ __IO uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */
+ __IO uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */
+ __IO uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */
+ __IO uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */
+ __IO uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */
+ __IO uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name SC1 - ADC status and control registers 1 */
+#define ADC_SC1_ADCH_MASK (0x1FU)
+#define ADC_SC1_ADCH_SHIFT (0U)
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK (0x20U)
+#define ADC_SC1_DIFF_SHIFT (5U)
+#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
+#define ADC_SC1_AIEN_MASK (0x40U)
+#define ADC_SC1_AIEN_SHIFT (6U)
+#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
+#define ADC_SC1_COCO_MASK (0x80U)
+#define ADC_SC1_COCO_SHIFT (7U)
+#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
+
+/* The count of ADC_SC1 */
+#define ADC_SC1_COUNT (2U)
+
+/*! @name CFG1 - ADC configuration register 1 */
+#define ADC_CFG1_ADICLK_MASK (0x3U)
+#define ADC_CFG1_ADICLK_SHIFT (0U)
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK (0xCU)
+#define ADC_CFG1_MODE_SHIFT (2U)
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK (0x10U)
+#define ADC_CFG1_ADLSMP_SHIFT (4U)
+#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
+#define ADC_CFG1_ADIV_MASK (0x60U)
+#define ADC_CFG1_ADIV_SHIFT (5U)
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK (0x80U)
+#define ADC_CFG1_ADLPC_SHIFT (7U)
+#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
+
+/*! @name CFG2 - Configuration register 2 */
+#define ADC_CFG2_ADLSTS_MASK (0x3U)
+#define ADC_CFG2_ADLSTS_SHIFT (0U)
+#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK (0x4U)
+#define ADC_CFG2_ADHSC_SHIFT (2U)
+#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
+#define ADC_CFG2_ADACKEN_MASK (0x8U)
+#define ADC_CFG2_ADACKEN_SHIFT (3U)
+#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
+#define ADC_CFG2_MUXSEL_MASK (0x10U)
+#define ADC_CFG2_MUXSEL_SHIFT (4U)
+#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
+
+/*! @name R - ADC data result register */
+#define ADC_R_D_MASK (0xFFFFU)
+#define ADC_R_D_SHIFT (0U)
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
+
+/* The count of ADC_R */
+#define ADC_R_COUNT (2U)
+
+/*! @name CV1 - Compare value registers */
+#define ADC_CV1_CV_MASK (0xFFFFU)
+#define ADC_CV1_CV_SHIFT (0U)
+#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
+
+/*! @name CV2 - Compare value registers */
+#define ADC_CV2_CV_MASK (0xFFFFU)
+#define ADC_CV2_CV_SHIFT (0U)
+#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
+
+/*! @name SC2 - Status and control register 2 */
+#define ADC_SC2_REFSEL_MASK (0x3U)
+#define ADC_SC2_REFSEL_SHIFT (0U)
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK (0x4U)
+#define ADC_SC2_DMAEN_SHIFT (2U)
+#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
+#define ADC_SC2_ACREN_MASK (0x8U)
+#define ADC_SC2_ACREN_SHIFT (3U)
+#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
+#define ADC_SC2_ACFGT_MASK (0x10U)
+#define ADC_SC2_ACFGT_SHIFT (4U)
+#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
+#define ADC_SC2_ACFE_MASK (0x20U)
+#define ADC_SC2_ACFE_SHIFT (5U)
+#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
+#define ADC_SC2_ADTRG_MASK (0x40U)
+#define ADC_SC2_ADTRG_SHIFT (6U)
+#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
+#define ADC_SC2_ADACT_MASK (0x80U)
+#define ADC_SC2_ADACT_SHIFT (7U)
+#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
+
+/*! @name SC3 - Status and control register 3 */
+#define ADC_SC3_AVGS_MASK (0x3U)
+#define ADC_SC3_AVGS_SHIFT (0U)
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK (0x4U)
+#define ADC_SC3_AVGE_SHIFT (2U)
+#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
+#define ADC_SC3_ADCO_MASK (0x8U)
+#define ADC_SC3_ADCO_SHIFT (3U)
+#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
+#define ADC_SC3_CALF_MASK (0x40U)
+#define ADC_SC3_CALF_SHIFT (6U)
+#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
+#define ADC_SC3_CAL_MASK (0x80U)
+#define ADC_SC3_CAL_SHIFT (7U)
+#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
+
+/*! @name OFS - ADC offset correction register */
+#define ADC_OFS_OFS_MASK (0xFFFFU)
+#define ADC_OFS_OFS_SHIFT (0U)
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
+
+/*! @name PG - ADC plus-side gain register */
+#define ADC_PG_PG_MASK (0xFFFFU)
+#define ADC_PG_PG_SHIFT (0U)
+#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
+
+/*! @name MG - ADC minus-side gain register */
+#define ADC_MG_MG_MASK (0xFFFFU)
+#define ADC_MG_MG_SHIFT (0U)
+#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
+
+/*! @name CLPD - ADC plus-side general calibration value register */
+#define ADC_CLPD_CLPD_MASK (0x3FU)
+#define ADC_CLPD_CLPD_SHIFT (0U)
+#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
+
+/*! @name CLPS - ADC plus-side general calibration value register */
+#define ADC_CLPS_CLPS_MASK (0x3FU)
+#define ADC_CLPS_CLPS_SHIFT (0U)
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
+
+/*! @name CLP4 - ADC plus-side general calibration value register */
+#define ADC_CLP4_CLP4_MASK (0x3FFU)
+#define ADC_CLP4_CLP4_SHIFT (0U)
+#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
+
+/*! @name CLP3 - ADC plus-side general calibration value register */
+#define ADC_CLP3_CLP3_MASK (0x1FFU)
+#define ADC_CLP3_CLP3_SHIFT (0U)
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
+
+/*! @name CLP2 - ADC plus-side general calibration value register */
+#define ADC_CLP2_CLP2_MASK (0xFFU)
+#define ADC_CLP2_CLP2_SHIFT (0U)
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
+
+/*! @name CLP1 - ADC plus-side general calibration value register */
+#define ADC_CLP1_CLP1_MASK (0x7FU)
+#define ADC_CLP1_CLP1_SHIFT (0U)
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
+
+/*! @name CLP0 - ADC plus-side general calibration value register */
+#define ADC_CLP0_CLP0_MASK (0x3FU)
+#define ADC_CLP0_CLP0_SHIFT (0U)
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
+
+/*! @name CLMD - ADC minus-side general calibration value register */
+#define ADC_CLMD_CLMD_MASK (0x3FU)
+#define ADC_CLMD_CLMD_SHIFT (0U)
+#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
+
+/*! @name CLMS - ADC minus-side general calibration value register */
+#define ADC_CLMS_CLMS_MASK (0x3FU)
+#define ADC_CLMS_CLMS_SHIFT (0U)
+#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
+
+/*! @name CLM4 - ADC minus-side general calibration value register */
+#define ADC_CLM4_CLM4_MASK (0x3FFU)
+#define ADC_CLM4_CLM4_SHIFT (0U)
+#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
+
+/*! @name CLM3 - ADC minus-side general calibration value register */
+#define ADC_CLM3_CLM3_MASK (0x1FFU)
+#define ADC_CLM3_CLM3_SHIFT (0U)
+#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
+
+/*! @name CLM2 - ADC minus-side general calibration value register */
+#define ADC_CLM2_CLM2_MASK (0xFFU)
+#define ADC_CLM2_CLM2_SHIFT (0U)
+#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
+
+/*! @name CLM1 - ADC minus-side general calibration value register */
+#define ADC_CLM1_CLM1_MASK (0x7FU)
+#define ADC_CLM1_CLM1_SHIFT (0U)
+#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
+
+/*! @name CLM0 - ADC minus-side general calibration value register */
+#define ADC_CLM0_CLM0_MASK (0x3FU)
+#define ADC_CLM0_CLM0_SHIFT (0U)
+#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0 ((ADC_Type *)ADC0_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS { ADC0_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS { ADC0 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS { ADC0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
+ __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
+ __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
+ __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
+ __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
+ __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
+} CMP_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/*! @name CR0 - CMP Control Register 0 */
+#define CMP_CR0_HYSTCTR_MASK (0x3U)
+#define CMP_CR0_HYSTCTR_SHIFT (0U)
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK (0x70U)
+#define CMP_CR0_FILTER_CNT_SHIFT (4U)
+#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
+
+/*! @name CR1 - CMP Control Register 1 */
+#define CMP_CR1_EN_MASK (0x1U)
+#define CMP_CR1_EN_SHIFT (0U)
+#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
+#define CMP_CR1_OPE_MASK (0x2U)
+#define CMP_CR1_OPE_SHIFT (1U)
+#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
+#define CMP_CR1_COS_MASK (0x4U)
+#define CMP_CR1_COS_SHIFT (2U)
+#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
+#define CMP_CR1_INV_MASK (0x8U)
+#define CMP_CR1_INV_SHIFT (3U)
+#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
+#define CMP_CR1_PMODE_MASK (0x10U)
+#define CMP_CR1_PMODE_SHIFT (4U)
+#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
+#define CMP_CR1_WE_MASK (0x40U)
+#define CMP_CR1_WE_SHIFT (6U)
+#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
+#define CMP_CR1_SE_MASK (0x80U)
+#define CMP_CR1_SE_SHIFT (7U)
+#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
+
+/*! @name FPR - CMP Filter Period Register */
+#define CMP_FPR_FILT_PER_MASK (0xFFU)
+#define CMP_FPR_FILT_PER_SHIFT (0U)
+#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
+
+/*! @name SCR - CMP Status and Control Register */
+#define CMP_SCR_COUT_MASK (0x1U)
+#define CMP_SCR_COUT_SHIFT (0U)
+#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
+#define CMP_SCR_CFF_MASK (0x2U)
+#define CMP_SCR_CFF_SHIFT (1U)
+#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
+#define CMP_SCR_CFR_MASK (0x4U)
+#define CMP_SCR_CFR_SHIFT (2U)
+#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
+#define CMP_SCR_IEF_MASK (0x8U)
+#define CMP_SCR_IEF_SHIFT (3U)
+#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
+#define CMP_SCR_IER_MASK (0x10U)
+#define CMP_SCR_IER_SHIFT (4U)
+#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
+#define CMP_SCR_DMAEN_MASK (0x40U)
+#define CMP_SCR_DMAEN_SHIFT (6U)
+#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
+
+/*! @name DACCR - DAC Control Register */
+#define CMP_DACCR_VOSEL_MASK (0x3FU)
+#define CMP_DACCR_VOSEL_SHIFT (0U)
+#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK (0x40U)
+#define CMP_DACCR_VRSEL_SHIFT (6U)
+#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
+#define CMP_DACCR_DACEN_MASK (0x80U)
+#define CMP_DACCR_DACEN_SHIFT (7U)
+#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
+
+/*! @name MUXCR - MUX Control Register */
+#define CMP_MUXCR_MSEL_MASK (0x7U)
+#define CMP_MUXCR_MSEL_SHIFT (0U)
+#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK (0x38U)
+#define CMP_MUXCR_PSEL_SHIFT (3U)
+#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0 ((CMP_Type *)CMP0_BASE)
+/** Peripheral CMP1 base address */
+#define CMP1_BASE (0x40073008u)
+/** Peripheral CMP1 base pointer */
+#define CMP1 ((CMP_Type *)CMP1_BASE)
+/** Array initializer of CMP peripheral base addresses */
+#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE }
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASE_PTRS { CMP0, CMP1 }
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
+ * @{
+ */
+
+/** CMT - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
+ __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
+ __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
+ __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
+ __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
+ __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
+ __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
+ __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
+ __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
+ __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
+ __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
+ __IO uint8_t DMA; /**< CMT Direct Memory Access, offset: 0xB */
+} CMT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CMT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Masks CMT Register Masks
+ * @{
+ */
+
+/*! @name CGH1 - CMT Carrier Generator High Data Register 1 */
+#define CMT_CGH1_PH_MASK (0xFFU)
+#define CMT_CGH1_PH_SHIFT (0U)
+#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
+
+/*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */
+#define CMT_CGL1_PL_MASK (0xFFU)
+#define CMT_CGL1_PL_SHIFT (0U)
+#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
+
+/*! @name CGH2 - CMT Carrier Generator High Data Register 2 */
+#define CMT_CGH2_SH_MASK (0xFFU)
+#define CMT_CGH2_SH_SHIFT (0U)
+#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
+
+/*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */
+#define CMT_CGL2_SL_MASK (0xFFU)
+#define CMT_CGL2_SL_SHIFT (0U)
+#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
+
+/*! @name OC - CMT Output Control Register */
+#define CMT_OC_IROPEN_MASK (0x20U)
+#define CMT_OC_IROPEN_SHIFT (5U)
+#define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
+#define CMT_OC_CMTPOL_MASK (0x40U)
+#define CMT_OC_CMTPOL_SHIFT (6U)
+#define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
+#define CMT_OC_IROL_MASK (0x80U)
+#define CMT_OC_IROL_SHIFT (7U)
+#define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
+
+/*! @name MSC - CMT Modulator Status and Control Register */
+#define CMT_MSC_MCGEN_MASK (0x1U)
+#define CMT_MSC_MCGEN_SHIFT (0U)
+#define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
+#define CMT_MSC_EOCIE_MASK (0x2U)
+#define CMT_MSC_EOCIE_SHIFT (1U)
+#define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
+#define CMT_MSC_FSK_MASK (0x4U)
+#define CMT_MSC_FSK_SHIFT (2U)
+#define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
+#define CMT_MSC_BASE_MASK (0x8U)
+#define CMT_MSC_BASE_SHIFT (3U)
+#define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
+#define CMT_MSC_EXSPC_MASK (0x10U)
+#define CMT_MSC_EXSPC_SHIFT (4U)
+#define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
+#define CMT_MSC_CMTDIV_MASK (0x60U)
+#define CMT_MSC_CMTDIV_SHIFT (5U)
+#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
+#define CMT_MSC_EOCF_MASK (0x80U)
+#define CMT_MSC_EOCF_SHIFT (7U)
+#define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
+
+/*! @name CMD1 - CMT Modulator Data Register Mark High */
+#define CMT_CMD1_MB_MASK (0xFFU)
+#define CMT_CMD1_MB_SHIFT (0U)
+#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
+
+/*! @name CMD2 - CMT Modulator Data Register Mark Low */
+#define CMT_CMD2_MB_MASK (0xFFU)
+#define CMT_CMD2_MB_SHIFT (0U)
+#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
+
+/*! @name CMD3 - CMT Modulator Data Register Space High */
+#define CMT_CMD3_SB_MASK (0xFFU)
+#define CMT_CMD3_SB_SHIFT (0U)
+#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
+
+/*! @name CMD4 - CMT Modulator Data Register Space Low */
+#define CMT_CMD4_SB_MASK (0xFFU)
+#define CMT_CMD4_SB_SHIFT (0U)
+#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
+
+/*! @name PPS - CMT Primary Prescaler Register */
+#define CMT_PPS_PPSDIV_MASK (0xFU)
+#define CMT_PPS_PPSDIV_SHIFT (0U)
+#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
+
+/*! @name DMA - CMT Direct Memory Access */
+#define CMT_DMA_DMA_MASK (0x1U)
+#define CMT_DMA_DMA_SHIFT (0U)
+#define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Masks */
+
+
+/* CMT - Peripheral instance base addresses */
+/** Peripheral CMT base address */
+#define CMT_BASE (0x40062000u)
+/** Peripheral CMT base pointer */
+#define CMT ((CMT_Type *)CMT_BASE)
+/** Array initializer of CMT peripheral base addresses */
+#define CMT_BASE_ADDRS { CMT_BASE }
+/** Array initializer of CMT peripheral base pointers */
+#define CMT_BASE_PTRS { CMT }
+/** Interrupt vectors for the CMT peripheral type */
+#define CMT_IRQS { CMT_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CMT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CRC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+ union { /* offset: 0x0 */
+ struct { /* offset: 0x0 */
+ __IO uint16_t CRCL; /**< CRC_CRCL register., offset: 0x0 */
+ __IO uint16_t CRCH; /**< CRC_CRCH register., offset: 0x2 */
+ } ACCESS16BIT;
+ __IO uint32_t CRC; /**< CRC Data Register, offset: 0x0 */
+ struct { /* offset: 0x0 */
+ __IO uint8_t CRCLL; /**< CRC_CRCLL register., offset: 0x0 */
+ __IO uint8_t CRCLU; /**< CRC_CRCLU register., offset: 0x1 */
+ __IO uint8_t CRCHL; /**< CRC_CRCHL register., offset: 0x2 */
+ __IO uint8_t CRCHU; /**< CRC_CRCHU register., offset: 0x3 */
+ } ACCESS8BIT;
+ };
+ union { /* offset: 0x4 */
+ struct { /* offset: 0x4 */
+ __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
+ __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
+ } GPOLY_ACCESS16BIT;
+ __IO uint32_t GPOLY; /**< CRC Polynomial Register, offset: 0x4 */
+ struct { /* offset: 0x4 */
+ __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
+ __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
+ __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
+ __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
+ } GPOLY_ACCESS8BIT;
+ };
+ union { /* offset: 0x8 */
+ __IO uint32_t CTRL; /**< CRC Control Register, offset: 0x8 */
+ struct { /* offset: 0x8 */
+ uint8_t RESERVED_0[3];
+ __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
+ } CTRL_ACCESS8BIT;
+ };
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CRC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/*! @name CRCL - CRC_CRCL register. */
+#define CRC_CRCL_CRCL_MASK (0xFFFFU)
+#define CRC_CRCL_CRCL_SHIFT (0U)
+#define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x)) << CRC_CRCL_CRCL_SHIFT)) & CRC_CRCL_CRCL_MASK)
+
+/*! @name CRCH - CRC_CRCH register. */
+#define CRC_CRCH_CRCH_MASK (0xFFFFU)
+#define CRC_CRCH_CRCH_SHIFT (0U)
+#define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x)) << CRC_CRCH_CRCH_SHIFT)) & CRC_CRCH_CRCH_MASK)
+
+/*! @name CRC - CRC Data Register */
+#define CRC_CRC_LL_MASK (0xFFU)
+#define CRC_CRC_LL_SHIFT (0U)
+#define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_CRC_LL_SHIFT)) & CRC_CRC_LL_MASK)
+#define CRC_CRC_LU_MASK (0xFF00U)
+#define CRC_CRC_LU_SHIFT (8U)
+#define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_CRC_LU_SHIFT)) & CRC_CRC_LU_MASK)
+#define CRC_CRC_HL_MASK (0xFF0000U)
+#define CRC_CRC_HL_SHIFT (16U)
+#define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_CRC_HL_SHIFT)) & CRC_CRC_HL_MASK)
+#define CRC_CRC_HU_MASK (0xFF000000U)
+#define CRC_CRC_HU_SHIFT (24U)
+#define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_CRC_HU_SHIFT)) & CRC_CRC_HU_MASK)
+
+/*! @name CRCLL - CRC_CRCLL register. */
+#define CRC_CRCLL_CRCLL_MASK (0xFFU)
+#define CRC_CRCLL_CRCLL_SHIFT (0U)
+#define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_CRCLL_CRCLL_SHIFT)) & CRC_CRCLL_CRCLL_MASK)
+
+/*! @name CRCLU - CRC_CRCLU register. */
+#define CRC_CRCLU_CRCLU_MASK (0xFFU)
+#define CRC_CRCLU_CRCLU_SHIFT (0U)
+#define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_CRCLU_CRCLU_SHIFT)) & CRC_CRCLU_CRCLU_MASK)
+
+/*! @name CRCHL - CRC_CRCHL register. */
+#define CRC_CRCHL_CRCHL_MASK (0xFFU)
+#define CRC_CRCHL_CRCHL_SHIFT (0U)
+#define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_CRCHL_CRCHL_SHIFT)) & CRC_CRCHL_CRCHL_MASK)
+
+/*! @name CRCHU - CRC_CRCHU register. */
+#define CRC_CRCHU_CRCHU_MASK (0xFFU)
+#define CRC_CRCHU_CRCHU_SHIFT (0U)
+#define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_CRCHU_CRCHU_SHIFT)) & CRC_CRCHU_CRCHU_MASK)
+
+/*! @name GPOLYL - CRC_GPOLYL register. */
+#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
+#define CRC_GPOLYL_GPOLYL_SHIFT (0U)
+#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
+
+/*! @name GPOLYH - CRC_GPOLYH register. */
+#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
+#define CRC_GPOLYH_GPOLYH_SHIFT (0U)
+#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
+
+/*! @name GPOLY - CRC Polynomial Register */
+#define CRC_GPOLY_LOW_MASK (0xFFFFU)
+#define CRC_GPOLY_LOW_SHIFT (0U)
+#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
+#define CRC_GPOLY_HIGH_SHIFT (16U)
+#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
+
+/*! @name GPOLYLL - CRC_GPOLYLL register. */
+#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
+#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
+#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
+
+/*! @name GPOLYLU - CRC_GPOLYLU register. */
+#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
+#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
+#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
+
+/*! @name GPOLYHL - CRC_GPOLYHL register. */
+#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
+#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
+#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
+
+/*! @name GPOLYHU - CRC_GPOLYHU register. */
+#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
+#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
+#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
+
+/*! @name CTRL - CRC Control Register */
+#define CRC_CTRL_TCRC_MASK (0x1000000U)
+#define CRC_CTRL_TCRC_SHIFT (24U)
+#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
+#define CRC_CTRL_WAS_MASK (0x2000000U)
+#define CRC_CTRL_WAS_SHIFT (25U)
+#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
+#define CRC_CTRL_FXOR_MASK (0x4000000U)
+#define CRC_CTRL_FXOR_SHIFT (26U)
+#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
+#define CRC_CTRL_TOTR_MASK (0x30000000U)
+#define CRC_CTRL_TOTR_SHIFT (28U)
+#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK (0xC0000000U)
+#define CRC_CTRL_TOT_SHIFT (30U)
+#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
+
+/*! @name CTRLHU - CRC_CTRLHU register. */
+#define CRC_CTRLHU_TCRC_MASK (0x1U)
+#define CRC_CTRLHU_TCRC_SHIFT (0U)
+#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
+#define CRC_CTRLHU_WAS_MASK (0x2U)
+#define CRC_CTRLHU_WAS_SHIFT (1U)
+#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
+#define CRC_CTRLHU_FXOR_MASK (0x4U)
+#define CRC_CTRLHU_FXOR_SHIFT (2U)
+#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
+#define CRC_CTRLHU_TOTR_MASK (0x30U)
+#define CRC_CTRLHU_TOTR_SHIFT (4U)
+#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK (0xC0U)
+#define CRC_CTRLHU_TOT_SHIFT (6U)
+#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE (0x40032000u)
+/** Peripheral CRC base pointer */
+#define CRC0 ((CRC_Type *)CRC_BASE)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS { CRC_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS { CRC0 }
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CR; /**< Control Register, offset: 0x0 */
+ __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
+ __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
+ __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
+ __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
+ __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
+ __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
+ __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
+ __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
+ __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
+ uint8_t RESERVED_4[4];
+ __IO uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
+ uint8_t RESERVED_5[200];
+ __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
+ __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
+ __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
+ __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
+ uint8_t RESERVED_6[3836];
+ struct { /* offset: 0x1000, array step: 0x20 */
+ __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
+ __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
+ __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
+ union { /* offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
+ };
+ __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
+ __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
+ __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
+ union { /* offset: 0x1016, array step: 0x20 */
+ __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
+ __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
+ };
+ __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+ __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
+ union { /* offset: 0x101E, array step: 0x20 */
+ __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
+ __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
+ };
+ } TCD[4];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/*! @name CR - Control Register */
+#define DMA_CR_EDBG_MASK (0x2U)
+#define DMA_CR_EDBG_SHIFT (1U)
+#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
+#define DMA_CR_ERCA_MASK (0x4U)
+#define DMA_CR_ERCA_SHIFT (2U)
+#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
+#define DMA_CR_HOE_MASK (0x10U)
+#define DMA_CR_HOE_SHIFT (4U)
+#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
+#define DMA_CR_HALT_MASK (0x20U)
+#define DMA_CR_HALT_SHIFT (5U)
+#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
+#define DMA_CR_CLM_MASK (0x40U)
+#define DMA_CR_CLM_SHIFT (6U)
+#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
+#define DMA_CR_EMLM_MASK (0x80U)
+#define DMA_CR_EMLM_SHIFT (7U)
+#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
+#define DMA_CR_ECX_MASK (0x10000U)
+#define DMA_CR_ECX_SHIFT (16U)
+#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
+#define DMA_CR_CX_MASK (0x20000U)
+#define DMA_CR_CX_SHIFT (17U)
+#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
+
+/*! @name ES - Error Status Register */
+#define DMA_ES_DBE_MASK (0x1U)
+#define DMA_ES_DBE_SHIFT (0U)
+#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
+#define DMA_ES_SBE_MASK (0x2U)
+#define DMA_ES_SBE_SHIFT (1U)
+#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
+#define DMA_ES_SGE_MASK (0x4U)
+#define DMA_ES_SGE_SHIFT (2U)
+#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
+#define DMA_ES_NCE_MASK (0x8U)
+#define DMA_ES_NCE_SHIFT (3U)
+#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
+#define DMA_ES_DOE_MASK (0x10U)
+#define DMA_ES_DOE_SHIFT (4U)
+#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
+#define DMA_ES_DAE_MASK (0x20U)
+#define DMA_ES_DAE_SHIFT (5U)
+#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
+#define DMA_ES_SOE_MASK (0x40U)
+#define DMA_ES_SOE_SHIFT (6U)
+#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
+#define DMA_ES_SAE_MASK (0x80U)
+#define DMA_ES_SAE_SHIFT (7U)
+#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
+#define DMA_ES_ERRCHN_MASK (0xF00U)
+#define DMA_ES_ERRCHN_SHIFT (8U)
+#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK (0x4000U)
+#define DMA_ES_CPE_SHIFT (14U)
+#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
+#define DMA_ES_ECX_MASK (0x10000U)
+#define DMA_ES_ECX_SHIFT (16U)
+#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
+#define DMA_ES_VLD_MASK (0x80000000U)
+#define DMA_ES_VLD_SHIFT (31U)
+#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
+
+/*! @name ERQ - Enable Request Register */
+#define DMA_ERQ_ERQ0_MASK (0x1U)
+#define DMA_ERQ_ERQ0_SHIFT (0U)
+#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
+#define DMA_ERQ_ERQ1_MASK (0x2U)
+#define DMA_ERQ_ERQ1_SHIFT (1U)
+#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
+#define DMA_ERQ_ERQ2_MASK (0x4U)
+#define DMA_ERQ_ERQ2_SHIFT (2U)
+#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
+#define DMA_ERQ_ERQ3_MASK (0x8U)
+#define DMA_ERQ_ERQ3_SHIFT (3U)
+#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
+
+/*! @name EEI - Enable Error Interrupt Register */
+#define DMA_EEI_EEI0_MASK (0x1U)
+#define DMA_EEI_EEI0_SHIFT (0U)
+#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
+#define DMA_EEI_EEI1_MASK (0x2U)
+#define DMA_EEI_EEI1_SHIFT (1U)
+#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
+#define DMA_EEI_EEI2_MASK (0x4U)
+#define DMA_EEI_EEI2_SHIFT (2U)
+#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
+#define DMA_EEI_EEI3_MASK (0x8U)
+#define DMA_EEI_EEI3_SHIFT (3U)
+#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
+
+/*! @name CEEI - Clear Enable Error Interrupt Register */
+#define DMA_CEEI_CEEI_MASK (0xFU)
+#define DMA_CEEI_CEEI_SHIFT (0U)
+#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK (0x40U)
+#define DMA_CEEI_CAEE_SHIFT (6U)
+#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
+#define DMA_CEEI_NOP_MASK (0x80U)
+#define DMA_CEEI_NOP_SHIFT (7U)
+#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
+
+/*! @name SEEI - Set Enable Error Interrupt Register */
+#define DMA_SEEI_SEEI_MASK (0xFU)
+#define DMA_SEEI_SEEI_SHIFT (0U)
+#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK (0x40U)
+#define DMA_SEEI_SAEE_SHIFT (6U)
+#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
+#define DMA_SEEI_NOP_MASK (0x80U)
+#define DMA_SEEI_NOP_SHIFT (7U)
+#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
+
+/*! @name CERQ - Clear Enable Request Register */
+#define DMA_CERQ_CERQ_MASK (0xFU)
+#define DMA_CERQ_CERQ_SHIFT (0U)
+#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK (0x40U)
+#define DMA_CERQ_CAER_SHIFT (6U)
+#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
+#define DMA_CERQ_NOP_MASK (0x80U)
+#define DMA_CERQ_NOP_SHIFT (7U)
+#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
+
+/*! @name SERQ - Set Enable Request Register */
+#define DMA_SERQ_SERQ_MASK (0xFU)
+#define DMA_SERQ_SERQ_SHIFT (0U)
+#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK (0x40U)
+#define DMA_SERQ_SAER_SHIFT (6U)
+#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
+#define DMA_SERQ_NOP_MASK (0x80U)
+#define DMA_SERQ_NOP_SHIFT (7U)
+#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
+
+/*! @name CDNE - Clear DONE Status Bit Register */
+#define DMA_CDNE_CDNE_MASK (0xFU)
+#define DMA_CDNE_CDNE_SHIFT (0U)
+#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK (0x40U)
+#define DMA_CDNE_CADN_SHIFT (6U)
+#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
+#define DMA_CDNE_NOP_MASK (0x80U)
+#define DMA_CDNE_NOP_SHIFT (7U)
+#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
+
+/*! @name SSRT - Set START Bit Register */
+#define DMA_SSRT_SSRT_MASK (0xFU)
+#define DMA_SSRT_SSRT_SHIFT (0U)
+#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK (0x40U)
+#define DMA_SSRT_SAST_SHIFT (6U)
+#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
+#define DMA_SSRT_NOP_MASK (0x80U)
+#define DMA_SSRT_NOP_SHIFT (7U)
+#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
+
+/*! @name CERR - Clear Error Register */
+#define DMA_CERR_CERR_MASK (0xFU)
+#define DMA_CERR_CERR_SHIFT (0U)
+#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK (0x40U)
+#define DMA_CERR_CAEI_SHIFT (6U)
+#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
+#define DMA_CERR_NOP_MASK (0x80U)
+#define DMA_CERR_NOP_SHIFT (7U)
+#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
+
+/*! @name CINT - Clear Interrupt Request Register */
+#define DMA_CINT_CINT_MASK (0xFU)
+#define DMA_CINT_CINT_SHIFT (0U)
+#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK (0x40U)
+#define DMA_CINT_CAIR_SHIFT (6U)
+#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
+#define DMA_CINT_NOP_MASK (0x80U)
+#define DMA_CINT_NOP_SHIFT (7U)
+#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
+
+/*! @name INT - Interrupt Request Register */
+#define DMA_INT_INT0_MASK (0x1U)
+#define DMA_INT_INT0_SHIFT (0U)
+#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
+#define DMA_INT_INT1_MASK (0x2U)
+#define DMA_INT_INT1_SHIFT (1U)
+#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
+#define DMA_INT_INT2_MASK (0x4U)
+#define DMA_INT_INT2_SHIFT (2U)
+#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
+#define DMA_INT_INT3_MASK (0x8U)
+#define DMA_INT_INT3_SHIFT (3U)
+#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
+
+/*! @name ERR - Error Register */
+#define DMA_ERR_ERR0_MASK (0x1U)
+#define DMA_ERR_ERR0_SHIFT (0U)
+#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
+#define DMA_ERR_ERR1_MASK (0x2U)
+#define DMA_ERR_ERR1_SHIFT (1U)
+#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
+#define DMA_ERR_ERR2_MASK (0x4U)
+#define DMA_ERR_ERR2_SHIFT (2U)
+#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
+#define DMA_ERR_ERR3_MASK (0x8U)
+#define DMA_ERR_ERR3_SHIFT (3U)
+#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
+
+/*! @name HRS - Hardware Request Status Register */
+#define DMA_HRS_HRS0_MASK (0x1U)
+#define DMA_HRS_HRS0_SHIFT (0U)
+#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
+#define DMA_HRS_HRS1_MASK (0x2U)
+#define DMA_HRS_HRS1_SHIFT (1U)
+#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
+#define DMA_HRS_HRS2_MASK (0x4U)
+#define DMA_HRS_HRS2_SHIFT (2U)
+#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
+#define DMA_HRS_HRS3_MASK (0x8U)
+#define DMA_HRS_HRS3_SHIFT (3U)
+#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
+
+/*! @name DCHPRI3 - Channel n Priority Register */
+#define DMA_DCHPRI3_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI3_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK (0x40U)
+#define DMA_DCHPRI3_DPA_SHIFT (6U)
+#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
+#define DMA_DCHPRI3_ECP_MASK (0x80U)
+#define DMA_DCHPRI3_ECP_SHIFT (7U)
+#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
+
+/*! @name DCHPRI2 - Channel n Priority Register */
+#define DMA_DCHPRI2_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI2_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK (0x40U)
+#define DMA_DCHPRI2_DPA_SHIFT (6U)
+#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
+#define DMA_DCHPRI2_ECP_MASK (0x80U)
+#define DMA_DCHPRI2_ECP_SHIFT (7U)
+#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
+
+/*! @name DCHPRI1 - Channel n Priority Register */
+#define DMA_DCHPRI1_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI1_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK (0x40U)
+#define DMA_DCHPRI1_DPA_SHIFT (6U)
+#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
+#define DMA_DCHPRI1_ECP_MASK (0x80U)
+#define DMA_DCHPRI1_ECP_SHIFT (7U)
+#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
+
+/*! @name DCHPRI0 - Channel n Priority Register */
+#define DMA_DCHPRI0_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI0_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK (0x40U)
+#define DMA_DCHPRI0_DPA_SHIFT (6U)
+#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
+#define DMA_DCHPRI0_ECP_MASK (0x80U)
+#define DMA_DCHPRI0_ECP_SHIFT (7U)
+#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
+
+/*! @name SADDR - TCD Source Address */
+#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
+#define DMA_SADDR_SADDR_SHIFT (0U)
+#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
+
+/* The count of DMA_SADDR */
+#define DMA_SADDR_COUNT (4U)
+
+/*! @name SOFF - TCD Signed Source Address Offset */
+#define DMA_SOFF_SOFF_MASK (0xFFFFU)
+#define DMA_SOFF_SOFF_SHIFT (0U)
+#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
+
+/* The count of DMA_SOFF */
+#define DMA_SOFF_COUNT (4U)
+
+/*! @name ATTR - TCD Transfer Attributes */
+#define DMA_ATTR_DSIZE_MASK (0x7U)
+#define DMA_ATTR_DSIZE_SHIFT (0U)
+#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK (0xF8U)
+#define DMA_ATTR_DMOD_SHIFT (3U)
+#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK (0x700U)
+#define DMA_ATTR_SSIZE_SHIFT (8U)
+#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK (0xF800U)
+#define DMA_ATTR_SMOD_SHIFT (11U)
+#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
+
+/* The count of DMA_ATTR */
+#define DMA_ATTR_COUNT (4U)
+
+/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) */
+#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
+#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
+
+/* The count of DMA_NBYTES_MLNO */
+#define DMA_NBYTES_MLNO_COUNT (4U)
+
+/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
+#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
+#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
+#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
+
+/* The count of DMA_NBYTES_MLOFFNO */
+#define DMA_NBYTES_MLOFFNO_COUNT (4U)
+
+/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
+#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
+#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
+#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
+#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
+
+/* The count of DMA_NBYTES_MLOFFYES */
+#define DMA_NBYTES_MLOFFYES_COUNT (4U)
+
+/*! @name SLAST - TCD Last Source Address Adjustment */
+#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
+#define DMA_SLAST_SLAST_SHIFT (0U)
+#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
+
+/* The count of DMA_SLAST */
+#define DMA_SLAST_COUNT (4U)
+
+/*! @name DADDR - TCD Destination Address */
+#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
+#define DMA_DADDR_DADDR_SHIFT (0U)
+#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
+
+/* The count of DMA_DADDR */
+#define DMA_DADDR_COUNT (4U)
+
+/*! @name DOFF - TCD Signed Destination Address Offset */
+#define DMA_DOFF_DOFF_MASK (0xFFFFU)
+#define DMA_DOFF_DOFF_SHIFT (0U)
+#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
+
+/* The count of DMA_DOFF */
+#define DMA_DOFF_COUNT (4U)
+
+/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
+#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
+#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
+#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
+#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
+#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
+
+/* The count of DMA_CITER_ELINKNO */
+#define DMA_CITER_ELINKNO_COUNT (4U)
+
+/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
+#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
+#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
+#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK (0x1E00U)
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
+#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
+#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
+#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
+
+/* The count of DMA_CITER_ELINKYES */
+#define DMA_CITER_ELINKYES_COUNT (4U)
+
+/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
+#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
+#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
+
+/* The count of DMA_DLAST_SGA */
+#define DMA_DLAST_SGA_COUNT (4U)
+
+/*! @name CSR - TCD Control and Status */
+#define DMA_CSR_START_MASK (0x1U)
+#define DMA_CSR_START_SHIFT (0U)
+#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
+#define DMA_CSR_INTMAJOR_MASK (0x2U)
+#define DMA_CSR_INTMAJOR_SHIFT (1U)
+#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
+#define DMA_CSR_INTHALF_MASK (0x4U)
+#define DMA_CSR_INTHALF_SHIFT (2U)
+#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
+#define DMA_CSR_DREQ_MASK (0x8U)
+#define DMA_CSR_DREQ_SHIFT (3U)
+#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
+#define DMA_CSR_ESG_MASK (0x10U)
+#define DMA_CSR_ESG_SHIFT (4U)
+#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
+#define DMA_CSR_MAJORELINK_MASK (0x20U)
+#define DMA_CSR_MAJORELINK_SHIFT (5U)
+#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
+#define DMA_CSR_ACTIVE_MASK (0x40U)
+#define DMA_CSR_ACTIVE_SHIFT (6U)
+#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
+#define DMA_CSR_DONE_MASK (0x80U)
+#define DMA_CSR_DONE_SHIFT (7U)
+#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
+#define DMA_CSR_MAJORLINKCH_MASK (0xF00U)
+#define DMA_CSR_MAJORLINKCH_SHIFT (8U)
+#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK (0xC000U)
+#define DMA_CSR_BWC_SHIFT (14U)
+#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
+
+/* The count of DMA_CSR */
+#define DMA_CSR_COUNT (4U)
+
+/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
+#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
+#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
+#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
+#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
+#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
+
+/* The count of DMA_BITER_ELINKNO */
+#define DMA_BITER_ELINKNO_COUNT (4U)
+
+/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
+#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
+#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
+#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK (0x1E00U)
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
+#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
+#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
+#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
+
+/* The count of DMA_BITER_ELINKYES */
+#define DMA_BITER_ELINKYES_COUNT (4U)
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0 ((DMA_Type *)DMA_BASE)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS { DMA_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn }
+#define DMA_ERROR_IRQS { DMA_Error_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CHCFG[4]; /**< Channel Configuration Register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/*! @name CHCFG - Channel Configuration Register */
+#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
+#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK (0x40U)
+#define DMAMUX_CHCFG_TRIG_SHIFT (6U)
+#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
+#define DMAMUX_CHCFG_ENBL_MASK (0x80U)
+#define DMAMUX_CHCFG_ENBL_SHIFT (7U)
+#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
+
+/* The count of DMAMUX_CHCFG */
+#define DMAMUX_CHCFG_COUNT (4U)
+
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX base address */
+#define DMAMUX_BASE (0x40021000u)
+/** Peripheral DMAMUX base pointer */
+#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
+/** Array initializer of DMAMUX peripheral base addresses */
+#define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASE_PTRS { DMAMUX }
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- EWM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
+ * @{
+ */
+
+/** EWM - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
+ __O uint8_t SERV; /**< Service Register, offset: 0x1 */
+ __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
+ __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
+} EWM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- EWM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Masks EWM Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control Register */
+#define EWM_CTRL_EWMEN_MASK (0x1U)
+#define EWM_CTRL_EWMEN_SHIFT (0U)
+#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
+#define EWM_CTRL_ASSIN_MASK (0x2U)
+#define EWM_CTRL_ASSIN_SHIFT (1U)
+#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
+#define EWM_CTRL_INEN_MASK (0x4U)
+#define EWM_CTRL_INEN_SHIFT (2U)
+#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
+#define EWM_CTRL_INTEN_MASK (0x8U)
+#define EWM_CTRL_INTEN_SHIFT (3U)
+#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
+
+/*! @name SERV - Service Register */
+#define EWM_SERV_SERVICE_MASK (0xFFU)
+#define EWM_SERV_SERVICE_SHIFT (0U)
+#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
+
+/*! @name CMPL - Compare Low Register */
+#define EWM_CMPL_COMPAREL_MASK (0xFFU)
+#define EWM_CMPL_COMPAREL_SHIFT (0U)
+#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
+
+/*! @name CMPH - Compare High Register */
+#define EWM_CMPH_COMPAREH_MASK (0xFFU)
+#define EWM_CMPH_COMPAREH_SHIFT (0U)
+#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Masks */
+
+
+/* EWM - Peripheral instance base addresses */
+/** Peripheral EWM base address */
+#define EWM_BASE (0x40061000u)
+/** Peripheral EWM base pointer */
+#define EWM ((EWM_Type *)EWM_BASE)
+/** Array initializer of EWM peripheral base addresses */
+#define EWM_BASE_ADDRS { EWM_BASE }
+/** Array initializer of EWM peripheral base pointers */
+#define EWM_BASE_PTRS { EWM }
+/** Interrupt vectors for the EWM peripheral type */
+#define EWM_IRQS { Watchdog_IRQn }
+
+/*!
+ * @}
+ */ /* end of group EWM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
+ * @{
+ */
+
+/** FMC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
+ __IO uint32_t PFB0CR; /**< Flash Control Register, offset: 0x4 */
+ uint8_t RESERVED_0[248];
+ struct { /* offset: 0x100, array step: 0x20 */
+ __IO uint32_t TAGVD[2]; /**< Cache Tag Storage, array offset: 0x100, array step: index*0x20, index2*0x4 */
+ uint8_t RESERVED_0[24];
+ } TAG_WAY[4];
+ uint8_t RESERVED_1[132];
+ struct { /* offset: 0x204, array step: 0x8 */
+ __IO uint32_t DATAW0S; /**< Cache Data Storage, array offset: 0x204, array step: 0x8 */
+ uint8_t RESERVED_0[4];
+ } DATAW0S[2];
+ uint8_t RESERVED_2[48];
+ struct { /* offset: 0x244, array step: 0x8 */
+ __IO uint32_t DATAW1S; /**< Cache Data Storage, array offset: 0x244, array step: 0x8 */
+ uint8_t RESERVED_0[4];
+ } DATAW1S[2];
+ uint8_t RESERVED_3[48];
+ struct { /* offset: 0x284, array step: 0x8 */
+ __IO uint32_t DATAW2S; /**< Cache Data Storage, array offset: 0x284, array step: 0x8 */
+ uint8_t RESERVED_0[4];
+ } DATAW2S[2];
+ uint8_t RESERVED_4[48];
+ struct { /* offset: 0x2C4, array step: 0x8 */
+ __IO uint32_t DATAW3S; /**< Cache Data Storage, array offset: 0x2C4, array step: 0x8 */
+ uint8_t RESERVED_0[4];
+ } DATAW3S[2];
+} FMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Masks FMC Register Masks
+ * @{
+ */
+
+/*! @name PFAPR - Flash Access Protection Register */
+#define FMC_PFAPR_M0AP_MASK (0x3U)
+#define FMC_PFAPR_M0AP_SHIFT (0U)
+#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M1AP_MASK (0xCU)
+#define FMC_PFAPR_M1AP_SHIFT (2U)
+#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M2AP_MASK (0x30U)
+#define FMC_PFAPR_M2AP_SHIFT (4U)
+#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M3AP_MASK (0xC0U)
+#define FMC_PFAPR_M3AP_SHIFT (6U)
+#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M0PFD_MASK (0x10000U)
+#define FMC_PFAPR_M0PFD_SHIFT (16U)
+#define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
+#define FMC_PFAPR_M1PFD_MASK (0x20000U)
+#define FMC_PFAPR_M1PFD_SHIFT (17U)
+#define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
+#define FMC_PFAPR_M2PFD_MASK (0x40000U)
+#define FMC_PFAPR_M2PFD_SHIFT (18U)
+#define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
+#define FMC_PFAPR_M3PFD_MASK (0x80000U)
+#define FMC_PFAPR_M3PFD_SHIFT (19U)
+#define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
+
+/*! @name PFB0CR - Flash Control Register */
+#define FMC_PFB0CR_B0SEBE_MASK (0x1U)
+#define FMC_PFB0CR_B0SEBE_SHIFT (0U)
+#define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK)
+#define FMC_PFB0CR_B0IPE_MASK (0x2U)
+#define FMC_PFB0CR_B0IPE_SHIFT (1U)
+#define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK)
+#define FMC_PFB0CR_B0DPE_MASK (0x4U)
+#define FMC_PFB0CR_B0DPE_SHIFT (2U)
+#define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK)
+#define FMC_PFB0CR_B0ICE_MASK (0x8U)
+#define FMC_PFB0CR_B0ICE_SHIFT (3U)
+#define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK)
+#define FMC_PFB0CR_B0DCE_MASK (0x10U)
+#define FMC_PFB0CR_B0DCE_SHIFT (4U)
+#define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK)
+#define FMC_PFB0CR_CRC_MASK (0xE0U)
+#define FMC_PFB0CR_CRC_SHIFT (5U)
+#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK)
+#define FMC_PFB0CR_B0MW_MASK (0x60000U)
+#define FMC_PFB0CR_B0MW_SHIFT (17U)
+#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)
+#define FMC_PFB0CR_S_B_INV_MASK (0x80000U)
+#define FMC_PFB0CR_S_B_INV_SHIFT (19U)
+#define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK)
+#define FMC_PFB0CR_CINV_WAY_MASK (0xF00000U)
+#define FMC_PFB0CR_CINV_WAY_SHIFT (20U)
+#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK)
+#define FMC_PFB0CR_CLCK_WAY_MASK (0xF000000U)
+#define FMC_PFB0CR_CLCK_WAY_SHIFT (24U)
+#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK)
+#define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U)
+#define FMC_PFB0CR_B0RWSC_SHIFT (28U)
+#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK)
+
+/*! @name TAGVD - Cache Tag Storage */
+#define FMC_TAGVD_valid_MASK (0x1U)
+#define FMC_TAGVD_valid_SHIFT (0U)
+#define FMC_TAGVD_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVD_valid_SHIFT)) & FMC_TAGVD_valid_MASK)
+#define FMC_TAGVD_tag_MASK (0x7FFC0U)
+#define FMC_TAGVD_tag_SHIFT (6U)
+#define FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVD_tag_SHIFT)) & FMC_TAGVD_tag_MASK)
+
+/* The count of FMC_TAGVD */
+#define FMC_TAGVD_COUNT (4U)
+
+/* The count of FMC_TAGVD */
+#define FMC_TAGVD_COUNT2 (2U)
+
+/*! @name DATAW0S - Cache Data Storage */
+#define FMC_DATAW0S_data_MASK (0xFFFFFFFFU)
+#define FMC_DATAW0S_data_SHIFT (0U)
+#define FMC_DATAW0S_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATAW0S_data_SHIFT)) & FMC_DATAW0S_data_MASK)
+
+/* The count of FMC_DATAW0S */
+#define FMC_DATAW0S_COUNT (2U)
+
+/*! @name DATAW1S - Cache Data Storage */
+#define FMC_DATAW1S_data_MASK (0xFFFFFFFFU)
+#define FMC_DATAW1S_data_SHIFT (0U)
+#define FMC_DATAW1S_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATAW1S_data_SHIFT)) & FMC_DATAW1S_data_MASK)
+
+/* The count of FMC_DATAW1S */
+#define FMC_DATAW1S_COUNT (2U)
+
+/*! @name DATAW2S - Cache Data Storage */
+#define FMC_DATAW2S_data_MASK (0xFFFFFFFFU)
+#define FMC_DATAW2S_data_SHIFT (0U)
+#define FMC_DATAW2S_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATAW2S_data_SHIFT)) & FMC_DATAW2S_data_MASK)
+
+/* The count of FMC_DATAW2S */
+#define FMC_DATAW2S_COUNT (2U)
+
+/*! @name DATAW3S - Cache Data Storage */
+#define FMC_DATAW3S_data_MASK (0xFFFFFFFFU)
+#define FMC_DATAW3S_data_SHIFT (0U)
+#define FMC_DATAW3S_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATAW3S_data_SHIFT)) & FMC_DATAW3S_data_MASK)
+
+/* The count of FMC_DATAW3S */
+#define FMC_DATAW3S_COUNT (2U)
+
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Masks */
+
+
+/* FMC - Peripheral instance base addresses */
+/** Peripheral FMC base address */
+#define FMC_BASE (0x4001F000u)
+/** Peripheral FMC base pointer */
+#define FMC ((FMC_Type *)FMC_BASE)
+/** Array initializer of FMC peripheral base addresses */
+#define FMC_BASE_ADDRS { FMC_BASE }
+/** Array initializer of FMC peripheral base pointers */
+#define FMC_BASE_PTRS { FMC }
+
+/*!
+ * @}
+ */ /* end of group FMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFL Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFL_Peripheral_Access_Layer FTFL Peripheral Access Layer
+ * @{
+ */
+
+/** FTFL - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
+ __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
+ __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
+ __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
+ __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
+ __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
+ __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
+ __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
+ __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
+ __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
+ __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
+ __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
+ __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
+ __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
+ __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
+ __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
+ __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
+ __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
+ __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
+ __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
+ __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
+} FTFL_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FTFL Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFL_Register_Masks FTFL Register Masks
+ * @{
+ */
+
+/*! @name FSTAT - Flash Status Register */
+#define FTFL_FSTAT_MGSTAT0_MASK (0x1U)
+#define FTFL_FSTAT_MGSTAT0_SHIFT (0U)
+#define FTFL_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_MGSTAT0_SHIFT)) & FTFL_FSTAT_MGSTAT0_MASK)
+#define FTFL_FSTAT_FPVIOL_MASK (0x10U)
+#define FTFL_FSTAT_FPVIOL_SHIFT (4U)
+#define FTFL_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_FPVIOL_SHIFT)) & FTFL_FSTAT_FPVIOL_MASK)
+#define FTFL_FSTAT_ACCERR_MASK (0x20U)
+#define FTFL_FSTAT_ACCERR_SHIFT (5U)
+#define FTFL_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_ACCERR_SHIFT)) & FTFL_FSTAT_ACCERR_MASK)
+#define FTFL_FSTAT_RDCOLERR_MASK (0x40U)
+#define FTFL_FSTAT_RDCOLERR_SHIFT (6U)
+#define FTFL_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_RDCOLERR_SHIFT)) & FTFL_FSTAT_RDCOLERR_MASK)
+#define FTFL_FSTAT_CCIF_MASK (0x80U)
+#define FTFL_FSTAT_CCIF_SHIFT (7U)
+#define FTFL_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_CCIF_SHIFT)) & FTFL_FSTAT_CCIF_MASK)
+
+/*! @name FCNFG - Flash Configuration Register */
+#define FTFL_FCNFG_EEERDY_MASK (0x1U)
+#define FTFL_FCNFG_EEERDY_SHIFT (0U)
+#define FTFL_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_EEERDY_SHIFT)) & FTFL_FCNFG_EEERDY_MASK)
+#define FTFL_FCNFG_RAMRDY_MASK (0x2U)
+#define FTFL_FCNFG_RAMRDY_SHIFT (1U)
+#define FTFL_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_RAMRDY_SHIFT)) & FTFL_FCNFG_RAMRDY_MASK)
+#define FTFL_FCNFG_PFLSH_MASK (0x4U)
+#define FTFL_FCNFG_PFLSH_SHIFT (2U)
+#define FTFL_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_PFLSH_SHIFT)) & FTFL_FCNFG_PFLSH_MASK)
+#define FTFL_FCNFG_ERSSUSP_MASK (0x10U)
+#define FTFL_FCNFG_ERSSUSP_SHIFT (4U)
+#define FTFL_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_ERSSUSP_SHIFT)) & FTFL_FCNFG_ERSSUSP_MASK)
+#define FTFL_FCNFG_ERSAREQ_MASK (0x20U)
+#define FTFL_FCNFG_ERSAREQ_SHIFT (5U)
+#define FTFL_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_ERSAREQ_SHIFT)) & FTFL_FCNFG_ERSAREQ_MASK)
+#define FTFL_FCNFG_RDCOLLIE_MASK (0x40U)
+#define FTFL_FCNFG_RDCOLLIE_SHIFT (6U)
+#define FTFL_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_RDCOLLIE_SHIFT)) & FTFL_FCNFG_RDCOLLIE_MASK)
+#define FTFL_FCNFG_CCIE_MASK (0x80U)
+#define FTFL_FCNFG_CCIE_SHIFT (7U)
+#define FTFL_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_CCIE_SHIFT)) & FTFL_FCNFG_CCIE_MASK)
+
+/*! @name FSEC - Flash Security Register */
+#define FTFL_FSEC_SEC_MASK (0x3U)
+#define FTFL_FSEC_SEC_SHIFT (0U)
+#define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_SEC_SHIFT)) & FTFL_FSEC_SEC_MASK)
+#define FTFL_FSEC_FSLACC_MASK (0xCU)
+#define FTFL_FSEC_FSLACC_SHIFT (2U)
+#define FTFL_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_FSLACC_SHIFT)) & FTFL_FSEC_FSLACC_MASK)
+#define FTFL_FSEC_MEEN_MASK (0x30U)
+#define FTFL_FSEC_MEEN_SHIFT (4U)
+#define FTFL_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_MEEN_SHIFT)) & FTFL_FSEC_MEEN_MASK)
+#define FTFL_FSEC_KEYEN_MASK (0xC0U)
+#define FTFL_FSEC_KEYEN_SHIFT (6U)
+#define FTFL_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_KEYEN_SHIFT)) & FTFL_FSEC_KEYEN_MASK)
+
+/*! @name FOPT - Flash Option Register */
+#define FTFL_FOPT_OPT_MASK (0xFFU)
+#define FTFL_FOPT_OPT_SHIFT (0U)
+#define FTFL_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FOPT_OPT_SHIFT)) & FTFL_FOPT_OPT_MASK)
+
+/*! @name FCCOB3 - Flash Common Command Object Registers */
+#define FTFL_FCCOB3_CCOBn_MASK (0xFFU)
+#define FTFL_FCCOB3_CCOBn_SHIFT (0U)
+#define FTFL_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB3_CCOBn_SHIFT)) & FTFL_FCCOB3_CCOBn_MASK)
+
+/*! @name FCCOB2 - Flash Common Command Object Registers */
+#define FTFL_FCCOB2_CCOBn_MASK (0xFFU)
+#define FTFL_FCCOB2_CCOBn_SHIFT (0U)
+#define FTFL_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB2_CCOBn_SHIFT)) & FTFL_FCCOB2_CCOBn_MASK)
+
+/*! @name FCCOB1 - Flash Common Command Object Registers */
+#define FTFL_FCCOB1_CCOBn_MASK (0xFFU)
+#define FTFL_FCCOB1_CCOBn_SHIFT (0U)
+#define FTFL_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB1_CCOBn_SHIFT)) & FTFL_FCCOB1_CCOBn_MASK)
+
+/*! @name FCCOB0 - Flash Common Command Object Registers */
+#define FTFL_FCCOB0_CCOBn_MASK (0xFFU)
+#define FTFL_FCCOB0_CCOBn_SHIFT (0U)
+#define FTFL_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB0_CCOBn_SHIFT)) & FTFL_FCCOB0_CCOBn_MASK)
+
+/*! @name FCCOB7 - Flash Common Command Object Registers */
+#define FTFL_FCCOB7_CCOBn_MASK (0xFFU)
+#define FTFL_FCCOB7_CCOBn_SHIFT (0U)
+#define FTFL_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB7_CCOBn_SHIFT)) & FTFL_FCCOB7_CCOBn_MASK)
+
+/*! @name FCCOB6 - Flash Common Command Object Registers */
+#define FTFL_FCCOB6_CCOBn_MASK (0xFFU)
+#define FTFL_FCCOB6_CCOBn_SHIFT (0U)
+#define FTFL_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB6_CCOBn_SHIFT)) & FTFL_FCCOB6_CCOBn_MASK)
+
+/*! @name FCCOB5 - Flash Common Command Object Registers */
+#define FTFL_FCCOB5_CCOBn_MASK (0xFFU)
+#define FTFL_FCCOB5_CCOBn_SHIFT (0U)
+#define FTFL_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB5_CCOBn_SHIFT)) & FTFL_FCCOB5_CCOBn_MASK)
+
+/*! @name FCCOB4 - Flash Common Command Object Registers */
+#define FTFL_FCCOB4_CCOBn_MASK (0xFFU)
+#define FTFL_FCCOB4_CCOBn_SHIFT (0U)
+#define FTFL_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB4_CCOBn_SHIFT)) & FTFL_FCCOB4_CCOBn_MASK)
+
+/*! @name FCCOBB - Flash Common Command Object Registers */
+#define FTFL_FCCOBB_CCOBn_MASK (0xFFU)
+#define FTFL_FCCOBB_CCOBn_SHIFT (0U)
+#define FTFL_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOBB_CCOBn_SHIFT)) & FTFL_FCCOBB_CCOBn_MASK)
+
+/*! @name FCCOBA - Flash Common Command Object Registers */
+#define FTFL_FCCOBA_CCOBn_MASK (0xFFU)
+#define FTFL_FCCOBA_CCOBn_SHIFT (0U)
+#define FTFL_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOBA_CCOBn_SHIFT)) & FTFL_FCCOBA_CCOBn_MASK)
+
+/*! @name FCCOB9 - Flash Common Command Object Registers */
+#define FTFL_FCCOB9_CCOBn_MASK (0xFFU)
+#define FTFL_FCCOB9_CCOBn_SHIFT (0U)
+#define FTFL_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB9_CCOBn_SHIFT)) & FTFL_FCCOB9_CCOBn_MASK)
+
+/*! @name FCCOB8 - Flash Common Command Object Registers */
+#define FTFL_FCCOB8_CCOBn_MASK (0xFFU)
+#define FTFL_FCCOB8_CCOBn_SHIFT (0U)
+#define FTFL_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB8_CCOBn_SHIFT)) & FTFL_FCCOB8_CCOBn_MASK)
+
+/*! @name FPROT3 - Program Flash Protection Registers */
+#define FTFL_FPROT3_PROT_MASK (0xFFU)
+#define FTFL_FPROT3_PROT_SHIFT (0U)
+#define FTFL_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT3_PROT_SHIFT)) & FTFL_FPROT3_PROT_MASK)
+
+/*! @name FPROT2 - Program Flash Protection Registers */
+#define FTFL_FPROT2_PROT_MASK (0xFFU)
+#define FTFL_FPROT2_PROT_SHIFT (0U)
+#define FTFL_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT2_PROT_SHIFT)) & FTFL_FPROT2_PROT_MASK)
+
+/*! @name FPROT1 - Program Flash Protection Registers */
+#define FTFL_FPROT1_PROT_MASK (0xFFU)
+#define FTFL_FPROT1_PROT_SHIFT (0U)
+#define FTFL_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT1_PROT_SHIFT)) & FTFL_FPROT1_PROT_MASK)
+
+/*! @name FPROT0 - Program Flash Protection Registers */
+#define FTFL_FPROT0_PROT_MASK (0xFFU)
+#define FTFL_FPROT0_PROT_SHIFT (0U)
+#define FTFL_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT0_PROT_SHIFT)) & FTFL_FPROT0_PROT_MASK)
+
+/*! @name FEPROT - EEPROM Protection Register */
+#define FTFL_FEPROT_EPROT_MASK (0xFFU)
+#define FTFL_FEPROT_EPROT_SHIFT (0U)
+#define FTFL_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FEPROT_EPROT_SHIFT)) & FTFL_FEPROT_EPROT_MASK)
+
+/*! @name FDPROT - Data Flash Protection Register */
+#define FTFL_FDPROT_DPROT_MASK (0xFFU)
+#define FTFL_FDPROT_DPROT_SHIFT (0U)
+#define FTFL_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FDPROT_DPROT_SHIFT)) & FTFL_FDPROT_DPROT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group FTFL_Register_Masks */
+
+
+/* FTFL - Peripheral instance base addresses */
+/** Peripheral FTFL base address */
+#define FTFL_BASE (0x40020000u)
+/** Peripheral FTFL base pointer */
+#define FTFL ((FTFL_Type *)FTFL_BASE)
+/** Array initializer of FTFL peripheral base addresses */
+#define FTFL_BASE_ADDRS { FTFL_BASE }
+/** Array initializer of FTFL peripheral base pointers */
+#define FTFL_BASE_PTRS { FTFL }
+/** Interrupt vectors for the FTFL peripheral type */
+#define FTFL_COMMAND_COMPLETE_IRQS { FTFL_IRQn }
+#define FTFL_READ_COLLISION_IRQS { Read_Collision_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FTFL_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
+ * @{
+ */
+
+/** FTM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
+ __IO uint32_t CNT; /**< Counter, offset: 0x4 */
+ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
+ struct { /* offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+ } CONTROLS[8];
+ __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
+ __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
+ __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
+ __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
+ __IO uint32_t OUTINIT; /**< Initial State for Channels Output, offset: 0x5C */
+ __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
+ __IO uint32_t COMBINE; /**< Function for Linked Channels, offset: 0x64 */
+ __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
+ __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
+ __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
+ __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
+ __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
+ __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
+ __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */
+ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
+ __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
+ __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
+ __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
+ __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
+ __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
+} FTM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FTM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Masks FTM Register Masks
+ * @{
+ */
+
+/*! @name SC - Status and Control */
+#define FTM_SC_PS_MASK (0x7U)
+#define FTM_SC_PS_SHIFT (0U)
+#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
+#define FTM_SC_CLKS_MASK (0x18U)
+#define FTM_SC_CLKS_SHIFT (3U)
+#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
+#define FTM_SC_CPWMS_MASK (0x20U)
+#define FTM_SC_CPWMS_SHIFT (5U)
+#define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
+#define FTM_SC_TOIE_MASK (0x40U)
+#define FTM_SC_TOIE_SHIFT (6U)
+#define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
+#define FTM_SC_TOF_MASK (0x80U)
+#define FTM_SC_TOF_SHIFT (7U)
+#define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
+
+/*! @name CNT - Counter */
+#define FTM_CNT_COUNT_MASK (0xFFFFU)
+#define FTM_CNT_COUNT_SHIFT (0U)
+#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
+
+/*! @name MOD - Modulo */
+#define FTM_MOD_MOD_MASK (0xFFFFU)
+#define FTM_MOD_MOD_SHIFT (0U)
+#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
+
+/*! @name CnSC - Channel (n) Status and Control */
+#define FTM_CnSC_DMA_MASK (0x1U)
+#define FTM_CnSC_DMA_SHIFT (0U)
+#define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
+#define FTM_CnSC_ELSA_MASK (0x4U)
+#define FTM_CnSC_ELSA_SHIFT (2U)
+#define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
+#define FTM_CnSC_ELSB_MASK (0x8U)
+#define FTM_CnSC_ELSB_SHIFT (3U)
+#define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
+#define FTM_CnSC_MSA_MASK (0x10U)
+#define FTM_CnSC_MSA_SHIFT (4U)
+#define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
+#define FTM_CnSC_MSB_MASK (0x20U)
+#define FTM_CnSC_MSB_SHIFT (5U)
+#define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
+#define FTM_CnSC_CHIE_MASK (0x40U)
+#define FTM_CnSC_CHIE_SHIFT (6U)
+#define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
+#define FTM_CnSC_CHF_MASK (0x80U)
+#define FTM_CnSC_CHF_SHIFT (7U)
+#define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
+
+/* The count of FTM_CnSC */
+#define FTM_CnSC_COUNT (8U)
+
+/*! @name CnV - Channel (n) Value */
+#define FTM_CnV_VAL_MASK (0xFFFFU)
+#define FTM_CnV_VAL_SHIFT (0U)
+#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
+
+/* The count of FTM_CnV */
+#define FTM_CnV_COUNT (8U)
+
+/*! @name CNTIN - Counter Initial Value */
+#define FTM_CNTIN_INIT_MASK (0xFFFFU)
+#define FTM_CNTIN_INIT_SHIFT (0U)
+#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
+
+/*! @name STATUS - Capture and Compare Status */
+#define FTM_STATUS_CH0F_MASK (0x1U)
+#define FTM_STATUS_CH0F_SHIFT (0U)
+#define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
+#define FTM_STATUS_CH1F_MASK (0x2U)
+#define FTM_STATUS_CH1F_SHIFT (1U)
+#define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
+#define FTM_STATUS_CH2F_MASK (0x4U)
+#define FTM_STATUS_CH2F_SHIFT (2U)
+#define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
+#define FTM_STATUS_CH3F_MASK (0x8U)
+#define FTM_STATUS_CH3F_SHIFT (3U)
+#define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
+#define FTM_STATUS_CH4F_MASK (0x10U)
+#define FTM_STATUS_CH4F_SHIFT (4U)
+#define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
+#define FTM_STATUS_CH5F_MASK (0x20U)
+#define FTM_STATUS_CH5F_SHIFT (5U)
+#define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
+#define FTM_STATUS_CH6F_MASK (0x40U)
+#define FTM_STATUS_CH6F_SHIFT (6U)
+#define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
+#define FTM_STATUS_CH7F_MASK (0x80U)
+#define FTM_STATUS_CH7F_SHIFT (7U)
+#define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
+
+/*! @name MODE - Features Mode Selection */
+#define FTM_MODE_FTMEN_MASK (0x1U)
+#define FTM_MODE_FTMEN_SHIFT (0U)
+#define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
+#define FTM_MODE_INIT_MASK (0x2U)
+#define FTM_MODE_INIT_SHIFT (1U)
+#define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
+#define FTM_MODE_WPDIS_MASK (0x4U)
+#define FTM_MODE_WPDIS_SHIFT (2U)
+#define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
+#define FTM_MODE_PWMSYNC_MASK (0x8U)
+#define FTM_MODE_PWMSYNC_SHIFT (3U)
+#define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
+#define FTM_MODE_CAPTEST_MASK (0x10U)
+#define FTM_MODE_CAPTEST_SHIFT (4U)
+#define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
+#define FTM_MODE_FAULTM_MASK (0x60U)
+#define FTM_MODE_FAULTM_SHIFT (5U)
+#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTIE_MASK (0x80U)
+#define FTM_MODE_FAULTIE_SHIFT (7U)
+#define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
+
+/*! @name SYNC - Synchronization */
+#define FTM_SYNC_CNTMIN_MASK (0x1U)
+#define FTM_SYNC_CNTMIN_SHIFT (0U)
+#define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
+#define FTM_SYNC_CNTMAX_MASK (0x2U)
+#define FTM_SYNC_CNTMAX_SHIFT (1U)
+#define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
+#define FTM_SYNC_REINIT_MASK (0x4U)
+#define FTM_SYNC_REINIT_SHIFT (2U)
+#define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
+#define FTM_SYNC_SYNCHOM_MASK (0x8U)
+#define FTM_SYNC_SYNCHOM_SHIFT (3U)
+#define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
+#define FTM_SYNC_TRIG0_MASK (0x10U)
+#define FTM_SYNC_TRIG0_SHIFT (4U)
+#define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
+#define FTM_SYNC_TRIG1_MASK (0x20U)
+#define FTM_SYNC_TRIG1_SHIFT (5U)
+#define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
+#define FTM_SYNC_TRIG2_MASK (0x40U)
+#define FTM_SYNC_TRIG2_SHIFT (6U)
+#define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
+#define FTM_SYNC_SWSYNC_MASK (0x80U)
+#define FTM_SYNC_SWSYNC_SHIFT (7U)
+#define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
+
+/*! @name OUTINIT - Initial State for Channels Output */
+#define FTM_OUTINIT_CH0OI_MASK (0x1U)
+#define FTM_OUTINIT_CH0OI_SHIFT (0U)
+#define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
+#define FTM_OUTINIT_CH1OI_MASK (0x2U)
+#define FTM_OUTINIT_CH1OI_SHIFT (1U)
+#define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
+#define FTM_OUTINIT_CH2OI_MASK (0x4U)
+#define FTM_OUTINIT_CH2OI_SHIFT (2U)
+#define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
+#define FTM_OUTINIT_CH3OI_MASK (0x8U)
+#define FTM_OUTINIT_CH3OI_SHIFT (3U)
+#define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
+#define FTM_OUTINIT_CH4OI_MASK (0x10U)
+#define FTM_OUTINIT_CH4OI_SHIFT (4U)
+#define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
+#define FTM_OUTINIT_CH5OI_MASK (0x20U)
+#define FTM_OUTINIT_CH5OI_SHIFT (5U)
+#define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
+#define FTM_OUTINIT_CH6OI_MASK (0x40U)
+#define FTM_OUTINIT_CH6OI_SHIFT (6U)
+#define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
+#define FTM_OUTINIT_CH7OI_MASK (0x80U)
+#define FTM_OUTINIT_CH7OI_SHIFT (7U)
+#define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
+
+/*! @name OUTMASK - Output Mask */
+#define FTM_OUTMASK_CH0OM_MASK (0x1U)
+#define FTM_OUTMASK_CH0OM_SHIFT (0U)
+#define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
+#define FTM_OUTMASK_CH1OM_MASK (0x2U)
+#define FTM_OUTMASK_CH1OM_SHIFT (1U)
+#define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
+#define FTM_OUTMASK_CH2OM_MASK (0x4U)
+#define FTM_OUTMASK_CH2OM_SHIFT (2U)
+#define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
+#define FTM_OUTMASK_CH3OM_MASK (0x8U)
+#define FTM_OUTMASK_CH3OM_SHIFT (3U)
+#define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
+#define FTM_OUTMASK_CH4OM_MASK (0x10U)
+#define FTM_OUTMASK_CH4OM_SHIFT (4U)
+#define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
+#define FTM_OUTMASK_CH5OM_MASK (0x20U)
+#define FTM_OUTMASK_CH5OM_SHIFT (5U)
+#define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
+#define FTM_OUTMASK_CH6OM_MASK (0x40U)
+#define FTM_OUTMASK_CH6OM_SHIFT (6U)
+#define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
+#define FTM_OUTMASK_CH7OM_MASK (0x80U)
+#define FTM_OUTMASK_CH7OM_SHIFT (7U)
+#define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
+
+/*! @name COMBINE - Function for Linked Channels */
+#define FTM_COMBINE_COMBINE0_MASK (0x1U)
+#define FTM_COMBINE_COMBINE0_SHIFT (0U)
+#define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
+#define FTM_COMBINE_COMP0_MASK (0x2U)
+#define FTM_COMBINE_COMP0_SHIFT (1U)
+#define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
+#define FTM_COMBINE_DECAPEN0_MASK (0x4U)
+#define FTM_COMBINE_DECAPEN0_SHIFT (2U)
+#define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
+#define FTM_COMBINE_DECAP0_MASK (0x8U)
+#define FTM_COMBINE_DECAP0_SHIFT (3U)
+#define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
+#define FTM_COMBINE_DTEN0_MASK (0x10U)
+#define FTM_COMBINE_DTEN0_SHIFT (4U)
+#define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
+#define FTM_COMBINE_SYNCEN0_MASK (0x20U)
+#define FTM_COMBINE_SYNCEN0_SHIFT (5U)
+#define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
+#define FTM_COMBINE_FAULTEN0_MASK (0x40U)
+#define FTM_COMBINE_FAULTEN0_SHIFT (6U)
+#define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
+#define FTM_COMBINE_COMBINE1_MASK (0x100U)
+#define FTM_COMBINE_COMBINE1_SHIFT (8U)
+#define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
+#define FTM_COMBINE_COMP1_MASK (0x200U)
+#define FTM_COMBINE_COMP1_SHIFT (9U)
+#define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
+#define FTM_COMBINE_DECAPEN1_MASK (0x400U)
+#define FTM_COMBINE_DECAPEN1_SHIFT (10U)
+#define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
+#define FTM_COMBINE_DECAP1_MASK (0x800U)
+#define FTM_COMBINE_DECAP1_SHIFT (11U)
+#define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
+#define FTM_COMBINE_DTEN1_MASK (0x1000U)
+#define FTM_COMBINE_DTEN1_SHIFT (12U)
+#define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
+#define FTM_COMBINE_SYNCEN1_MASK (0x2000U)
+#define FTM_COMBINE_SYNCEN1_SHIFT (13U)
+#define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
+#define FTM_COMBINE_FAULTEN1_MASK (0x4000U)
+#define FTM_COMBINE_FAULTEN1_SHIFT (14U)
+#define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
+#define FTM_COMBINE_COMBINE2_MASK (0x10000U)
+#define FTM_COMBINE_COMBINE2_SHIFT (16U)
+#define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
+#define FTM_COMBINE_COMP2_MASK (0x20000U)
+#define FTM_COMBINE_COMP2_SHIFT (17U)
+#define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
+#define FTM_COMBINE_DECAPEN2_MASK (0x40000U)
+#define FTM_COMBINE_DECAPEN2_SHIFT (18U)
+#define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
+#define FTM_COMBINE_DECAP2_MASK (0x80000U)
+#define FTM_COMBINE_DECAP2_SHIFT (19U)
+#define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
+#define FTM_COMBINE_DTEN2_MASK (0x100000U)
+#define FTM_COMBINE_DTEN2_SHIFT (20U)
+#define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
+#define FTM_COMBINE_SYNCEN2_MASK (0x200000U)
+#define FTM_COMBINE_SYNCEN2_SHIFT (21U)
+#define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
+#define FTM_COMBINE_FAULTEN2_MASK (0x400000U)
+#define FTM_COMBINE_FAULTEN2_SHIFT (22U)
+#define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
+#define FTM_COMBINE_COMBINE3_MASK (0x1000000U)
+#define FTM_COMBINE_COMBINE3_SHIFT (24U)
+#define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
+#define FTM_COMBINE_COMP3_MASK (0x2000000U)
+#define FTM_COMBINE_COMP3_SHIFT (25U)
+#define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
+#define FTM_COMBINE_DECAPEN3_MASK (0x4000000U)
+#define FTM_COMBINE_DECAPEN3_SHIFT (26U)
+#define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
+#define FTM_COMBINE_DECAP3_MASK (0x8000000U)
+#define FTM_COMBINE_DECAP3_SHIFT (27U)
+#define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
+#define FTM_COMBINE_DTEN3_MASK (0x10000000U)
+#define FTM_COMBINE_DTEN3_SHIFT (28U)
+#define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
+#define FTM_COMBINE_SYNCEN3_MASK (0x20000000U)
+#define FTM_COMBINE_SYNCEN3_SHIFT (29U)
+#define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
+#define FTM_COMBINE_FAULTEN3_MASK (0x40000000U)
+#define FTM_COMBINE_FAULTEN3_SHIFT (30U)
+#define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
+
+/*! @name DEADTIME - Deadtime Insertion Control */
+#define FTM_DEADTIME_DTVAL_MASK (0x3FU)
+#define FTM_DEADTIME_DTVAL_SHIFT (0U)
+#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTPS_MASK (0xC0U)
+#define FTM_DEADTIME_DTPS_SHIFT (6U)
+#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
+
+/*! @name EXTTRIG - FTM External Trigger */
+#define FTM_EXTTRIG_CH2TRIG_MASK (0x1U)
+#define FTM_EXTTRIG_CH2TRIG_SHIFT (0U)
+#define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
+#define FTM_EXTTRIG_CH3TRIG_MASK (0x2U)
+#define FTM_EXTTRIG_CH3TRIG_SHIFT (1U)
+#define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
+#define FTM_EXTTRIG_CH4TRIG_MASK (0x4U)
+#define FTM_EXTTRIG_CH4TRIG_SHIFT (2U)
+#define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
+#define FTM_EXTTRIG_CH5TRIG_MASK (0x8U)
+#define FTM_EXTTRIG_CH5TRIG_SHIFT (3U)
+#define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
+#define FTM_EXTTRIG_CH0TRIG_MASK (0x10U)
+#define FTM_EXTTRIG_CH0TRIG_SHIFT (4U)
+#define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
+#define FTM_EXTTRIG_CH1TRIG_MASK (0x20U)
+#define FTM_EXTTRIG_CH1TRIG_SHIFT (5U)
+#define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
+#define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U)
+#define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U)
+#define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
+#define FTM_EXTTRIG_TRIGF_MASK (0x80U)
+#define FTM_EXTTRIG_TRIGF_SHIFT (7U)
+#define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
+
+/*! @name POL - Channels Polarity */
+#define FTM_POL_POL0_MASK (0x1U)
+#define FTM_POL_POL0_SHIFT (0U)
+#define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
+#define FTM_POL_POL1_MASK (0x2U)
+#define FTM_POL_POL1_SHIFT (1U)
+#define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
+#define FTM_POL_POL2_MASK (0x4U)
+#define FTM_POL_POL2_SHIFT (2U)
+#define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
+#define FTM_POL_POL3_MASK (0x8U)
+#define FTM_POL_POL3_SHIFT (3U)
+#define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
+#define FTM_POL_POL4_MASK (0x10U)
+#define FTM_POL_POL4_SHIFT (4U)
+#define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
+#define FTM_POL_POL5_MASK (0x20U)
+#define FTM_POL_POL5_SHIFT (5U)
+#define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
+#define FTM_POL_POL6_MASK (0x40U)
+#define FTM_POL_POL6_SHIFT (6U)
+#define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
+#define FTM_POL_POL7_MASK (0x80U)
+#define FTM_POL_POL7_SHIFT (7U)
+#define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
+
+/*! @name FMS - Fault Mode Status */
+#define FTM_FMS_FAULTF0_MASK (0x1U)
+#define FTM_FMS_FAULTF0_SHIFT (0U)
+#define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
+#define FTM_FMS_FAULTF1_MASK (0x2U)
+#define FTM_FMS_FAULTF1_SHIFT (1U)
+#define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
+#define FTM_FMS_FAULTF2_MASK (0x4U)
+#define FTM_FMS_FAULTF2_SHIFT (2U)
+#define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
+#define FTM_FMS_FAULTF3_MASK (0x8U)
+#define FTM_FMS_FAULTF3_SHIFT (3U)
+#define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
+#define FTM_FMS_FAULTIN_MASK (0x20U)
+#define FTM_FMS_FAULTIN_SHIFT (5U)
+#define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
+#define FTM_FMS_WPEN_MASK (0x40U)
+#define FTM_FMS_WPEN_SHIFT (6U)
+#define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
+#define FTM_FMS_FAULTF_MASK (0x80U)
+#define FTM_FMS_FAULTF_SHIFT (7U)
+#define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
+
+/*! @name FILTER - Input Capture Filter Control */
+#define FTM_FILTER_CH0FVAL_MASK (0xFU)
+#define FTM_FILTER_CH0FVAL_SHIFT (0U)
+#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_MASK (0xF0U)
+#define FTM_FILTER_CH1FVAL_SHIFT (4U)
+#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_MASK (0xF00U)
+#define FTM_FILTER_CH2FVAL_SHIFT (8U)
+#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_MASK (0xF000U)
+#define FTM_FILTER_CH3FVAL_SHIFT (12U)
+#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
+
+/*! @name FLTCTRL - Fault Control */
+#define FTM_FLTCTRL_FAULT0EN_MASK (0x1U)
+#define FTM_FLTCTRL_FAULT0EN_SHIFT (0U)
+#define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
+#define FTM_FLTCTRL_FAULT1EN_MASK (0x2U)
+#define FTM_FLTCTRL_FAULT1EN_SHIFT (1U)
+#define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
+#define FTM_FLTCTRL_FAULT2EN_MASK (0x4U)
+#define FTM_FLTCTRL_FAULT2EN_SHIFT (2U)
+#define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
+#define FTM_FLTCTRL_FAULT3EN_MASK (0x8U)
+#define FTM_FLTCTRL_FAULT3EN_SHIFT (3U)
+#define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
+#define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U)
+#define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U)
+#define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
+#define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U)
+#define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U)
+#define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
+#define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U)
+#define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U)
+#define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
+#define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U)
+#define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U)
+#define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
+#define FTM_FLTCTRL_FFVAL_MASK (0xF00U)
+#define FTM_FLTCTRL_FFVAL_SHIFT (8U)
+#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
+
+/*! @name QDCTRL - Quadrature Decoder Control and Status */
+#define FTM_QDCTRL_QUADEN_MASK (0x1U)
+#define FTM_QDCTRL_QUADEN_SHIFT (0U)
+#define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
+#define FTM_QDCTRL_TOFDIR_MASK (0x2U)
+#define FTM_QDCTRL_TOFDIR_SHIFT (1U)
+#define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
+#define FTM_QDCTRL_QUADIR_MASK (0x4U)
+#define FTM_QDCTRL_QUADIR_SHIFT (2U)
+#define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
+#define FTM_QDCTRL_QUADMODE_MASK (0x8U)
+#define FTM_QDCTRL_QUADMODE_SHIFT (3U)
+#define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
+#define FTM_QDCTRL_PHBPOL_MASK (0x10U)
+#define FTM_QDCTRL_PHBPOL_SHIFT (4U)
+#define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
+#define FTM_QDCTRL_PHAPOL_MASK (0x20U)
+#define FTM_QDCTRL_PHAPOL_SHIFT (5U)
+#define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
+#define FTM_QDCTRL_PHBFLTREN_MASK (0x40U)
+#define FTM_QDCTRL_PHBFLTREN_SHIFT (6U)
+#define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
+#define FTM_QDCTRL_PHAFLTREN_MASK (0x80U)
+#define FTM_QDCTRL_PHAFLTREN_SHIFT (7U)
+#define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
+
+/*! @name CONF - Configuration */
+#define FTM_CONF_NUMTOF_MASK (0x1FU)
+#define FTM_CONF_NUMTOF_SHIFT (0U)
+#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_BDMMODE_MASK (0xC0U)
+#define FTM_CONF_BDMMODE_SHIFT (6U)
+#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_GTBEEN_MASK (0x200U)
+#define FTM_CONF_GTBEEN_SHIFT (9U)
+#define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
+#define FTM_CONF_GTBEOUT_MASK (0x400U)
+#define FTM_CONF_GTBEOUT_SHIFT (10U)
+#define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
+
+/*! @name FLTPOL - FTM Fault Input Polarity */
+#define FTM_FLTPOL_FLT0POL_MASK (0x1U)
+#define FTM_FLTPOL_FLT0POL_SHIFT (0U)
+#define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
+#define FTM_FLTPOL_FLT1POL_MASK (0x2U)
+#define FTM_FLTPOL_FLT1POL_SHIFT (1U)
+#define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
+#define FTM_FLTPOL_FLT2POL_MASK (0x4U)
+#define FTM_FLTPOL_FLT2POL_SHIFT (2U)
+#define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
+#define FTM_FLTPOL_FLT3POL_MASK (0x8U)
+#define FTM_FLTPOL_FLT3POL_SHIFT (3U)
+#define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
+
+/*! @name SYNCONF - Synchronization Configuration */
+#define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U)
+#define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U)
+#define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
+#define FTM_SYNCONF_CNTINC_MASK (0x4U)
+#define FTM_SYNCONF_CNTINC_SHIFT (2U)
+#define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
+#define FTM_SYNCONF_INVC_MASK (0x10U)
+#define FTM_SYNCONF_INVC_SHIFT (4U)
+#define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
+#define FTM_SYNCONF_SWOC_MASK (0x20U)
+#define FTM_SYNCONF_SWOC_SHIFT (5U)
+#define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
+#define FTM_SYNCONF_SYNCMODE_MASK (0x80U)
+#define FTM_SYNCONF_SYNCMODE_SHIFT (7U)
+#define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
+#define FTM_SYNCONF_SWRSTCNT_MASK (0x100U)
+#define FTM_SYNCONF_SWRSTCNT_SHIFT (8U)
+#define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
+#define FTM_SYNCONF_SWWRBUF_MASK (0x200U)
+#define FTM_SYNCONF_SWWRBUF_SHIFT (9U)
+#define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
+#define FTM_SYNCONF_SWOM_MASK (0x400U)
+#define FTM_SYNCONF_SWOM_SHIFT (10U)
+#define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
+#define FTM_SYNCONF_SWINVC_MASK (0x800U)
+#define FTM_SYNCONF_SWINVC_SHIFT (11U)
+#define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
+#define FTM_SYNCONF_SWSOC_MASK (0x1000U)
+#define FTM_SYNCONF_SWSOC_SHIFT (12U)
+#define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
+#define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U)
+#define FTM_SYNCONF_HWRSTCNT_SHIFT (16U)
+#define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
+#define FTM_SYNCONF_HWWRBUF_MASK (0x20000U)
+#define FTM_SYNCONF_HWWRBUF_SHIFT (17U)
+#define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
+#define FTM_SYNCONF_HWOM_MASK (0x40000U)
+#define FTM_SYNCONF_HWOM_SHIFT (18U)
+#define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
+#define FTM_SYNCONF_HWINVC_MASK (0x80000U)
+#define FTM_SYNCONF_HWINVC_SHIFT (19U)
+#define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
+#define FTM_SYNCONF_HWSOC_MASK (0x100000U)
+#define FTM_SYNCONF_HWSOC_SHIFT (20U)
+#define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
+
+/*! @name INVCTRL - FTM Inverting Control */
+#define FTM_INVCTRL_INV0EN_MASK (0x1U)
+#define FTM_INVCTRL_INV0EN_SHIFT (0U)
+#define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
+#define FTM_INVCTRL_INV1EN_MASK (0x2U)
+#define FTM_INVCTRL_INV1EN_SHIFT (1U)
+#define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
+#define FTM_INVCTRL_INV2EN_MASK (0x4U)
+#define FTM_INVCTRL_INV2EN_SHIFT (2U)
+#define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
+#define FTM_INVCTRL_INV3EN_MASK (0x8U)
+#define FTM_INVCTRL_INV3EN_SHIFT (3U)
+#define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
+
+/*! @name SWOCTRL - FTM Software Output Control */
+#define FTM_SWOCTRL_CH0OC_MASK (0x1U)
+#define FTM_SWOCTRL_CH0OC_SHIFT (0U)
+#define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
+#define FTM_SWOCTRL_CH1OC_MASK (0x2U)
+#define FTM_SWOCTRL_CH1OC_SHIFT (1U)
+#define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
+#define FTM_SWOCTRL_CH2OC_MASK (0x4U)
+#define FTM_SWOCTRL_CH2OC_SHIFT (2U)
+#define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
+#define FTM_SWOCTRL_CH3OC_MASK (0x8U)
+#define FTM_SWOCTRL_CH3OC_SHIFT (3U)
+#define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
+#define FTM_SWOCTRL_CH4OC_MASK (0x10U)
+#define FTM_SWOCTRL_CH4OC_SHIFT (4U)
+#define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
+#define FTM_SWOCTRL_CH5OC_MASK (0x20U)
+#define FTM_SWOCTRL_CH5OC_SHIFT (5U)
+#define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
+#define FTM_SWOCTRL_CH6OC_MASK (0x40U)
+#define FTM_SWOCTRL_CH6OC_SHIFT (6U)
+#define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
+#define FTM_SWOCTRL_CH7OC_MASK (0x80U)
+#define FTM_SWOCTRL_CH7OC_SHIFT (7U)
+#define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
+#define FTM_SWOCTRL_CH0OCV_MASK (0x100U)
+#define FTM_SWOCTRL_CH0OCV_SHIFT (8U)
+#define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
+#define FTM_SWOCTRL_CH1OCV_MASK (0x200U)
+#define FTM_SWOCTRL_CH1OCV_SHIFT (9U)
+#define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
+#define FTM_SWOCTRL_CH2OCV_MASK (0x400U)
+#define FTM_SWOCTRL_CH2OCV_SHIFT (10U)
+#define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
+#define FTM_SWOCTRL_CH3OCV_MASK (0x800U)
+#define FTM_SWOCTRL_CH3OCV_SHIFT (11U)
+#define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
+#define FTM_SWOCTRL_CH4OCV_MASK (0x1000U)
+#define FTM_SWOCTRL_CH4OCV_SHIFT (12U)
+#define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
+#define FTM_SWOCTRL_CH5OCV_MASK (0x2000U)
+#define FTM_SWOCTRL_CH5OCV_SHIFT (13U)
+#define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
+#define FTM_SWOCTRL_CH6OCV_MASK (0x4000U)
+#define FTM_SWOCTRL_CH6OCV_SHIFT (14U)
+#define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
+#define FTM_SWOCTRL_CH7OCV_MASK (0x8000U)
+#define FTM_SWOCTRL_CH7OCV_SHIFT (15U)
+#define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
+
+/*! @name PWMLOAD - FTM PWM Load */
+#define FTM_PWMLOAD_CH0SEL_MASK (0x1U)
+#define FTM_PWMLOAD_CH0SEL_SHIFT (0U)
+#define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
+#define FTM_PWMLOAD_CH1SEL_MASK (0x2U)
+#define FTM_PWMLOAD_CH1SEL_SHIFT (1U)
+#define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
+#define FTM_PWMLOAD_CH2SEL_MASK (0x4U)
+#define FTM_PWMLOAD_CH2SEL_SHIFT (2U)
+#define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
+#define FTM_PWMLOAD_CH3SEL_MASK (0x8U)
+#define FTM_PWMLOAD_CH3SEL_SHIFT (3U)
+#define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
+#define FTM_PWMLOAD_CH4SEL_MASK (0x10U)
+#define FTM_PWMLOAD_CH4SEL_SHIFT (4U)
+#define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
+#define FTM_PWMLOAD_CH5SEL_MASK (0x20U)
+#define FTM_PWMLOAD_CH5SEL_SHIFT (5U)
+#define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
+#define FTM_PWMLOAD_CH6SEL_MASK (0x40U)
+#define FTM_PWMLOAD_CH6SEL_SHIFT (6U)
+#define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
+#define FTM_PWMLOAD_CH7SEL_MASK (0x80U)
+#define FTM_PWMLOAD_CH7SEL_SHIFT (7U)
+#define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
+#define FTM_PWMLOAD_LDOK_MASK (0x200U)
+#define FTM_PWMLOAD_LDOK_SHIFT (9U)
+#define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Masks */
+
+
+/* FTM - Peripheral instance base addresses */
+/** Peripheral FTM0 base address */
+#define FTM0_BASE (0x40038000u)
+/** Peripheral FTM0 base pointer */
+#define FTM0 ((FTM_Type *)FTM0_BASE)
+/** Peripheral FTM1 base address */
+#define FTM1_BASE (0x40039000u)
+/** Peripheral FTM1 base pointer */
+#define FTM1 ((FTM_Type *)FTM1_BASE)
+/** Array initializer of FTM peripheral base addresses */
+#define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE }
+/** Array initializer of FTM peripheral base pointers */
+#define FTM_BASE_PTRS { FTM0, FTM1 }
+/** Interrupt vectors for the FTM peripheral type */
+#define FTM_IRQS { FTM0_IRQn, FTM1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FTM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/*! @name PDOR - Port Data Output Register */
+#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
+#define GPIO_PDOR_PDO_SHIFT (0U)
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
+
+/*! @name PSOR - Port Set Output Register */
+#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
+#define GPIO_PSOR_PTSO_SHIFT (0U)
+#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
+
+/*! @name PCOR - Port Clear Output Register */
+#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
+#define GPIO_PCOR_PTCO_SHIFT (0U)
+#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
+
+/*! @name PTOR - Port Toggle Output Register */
+#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
+#define GPIO_PTOR_PTTO_SHIFT (0U)
+#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
+
+/*! @name PDIR - Port Data Input Register */
+#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
+#define GPIO_PDIR_PDI_SHIFT (0U)
+#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
+
+/*! @name PDDR - Port Data Direction Register */
+#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
+#define GPIO_PDDR_PDD_SHIFT (0U)
+#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral PTA base address */
+#define PTA_BASE (0x400FF000u)
+/** Peripheral PTA base pointer */
+#define PTA ((GPIO_Type *)PTA_BASE)
+/** Peripheral PTB base address */
+#define PTB_BASE (0x400FF040u)
+/** Peripheral PTB base pointer */
+#define PTB ((GPIO_Type *)PTB_BASE)
+/** Peripheral PTC base address */
+#define PTC_BASE (0x400FF080u)
+/** Peripheral PTC base pointer */
+#define PTC ((GPIO_Type *)PTC_BASE)
+/** Peripheral PTD base address */
+#define PTD_BASE (0x400FF0C0u)
+/** Peripheral PTD base pointer */
+#define PTD ((GPIO_Type *)PTD_BASE)
+/** Peripheral PTE base address */
+#define PTE_BASE (0x400FF100u)
+/** Peripheral PTE base pointer */
+#define PTE ((GPIO_Type *)PTE_BASE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE }
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
+ __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
+ __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
+ __IO uint8_t S; /**< I2C Status Register, offset: 0x3 */
+ __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
+ __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
+ __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+ __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
+ __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
+ __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
+ __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
+ __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/*! @name A1 - I2C Address Register 1 */
+#define I2C_A1_AD_MASK (0xFEU)
+#define I2C_A1_AD_SHIFT (1U)
+#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
+
+/*! @name F - I2C Frequency Divider register */
+#define I2C_F_ICR_MASK (0x3FU)
+#define I2C_F_ICR_SHIFT (0U)
+#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK (0xC0U)
+#define I2C_F_MULT_SHIFT (6U)
+#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
+
+/*! @name C1 - I2C Control Register 1 */
+#define I2C_C1_DMAEN_MASK (0x1U)
+#define I2C_C1_DMAEN_SHIFT (0U)
+#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
+#define I2C_C1_WUEN_MASK (0x2U)
+#define I2C_C1_WUEN_SHIFT (1U)
+#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
+#define I2C_C1_RSTA_MASK (0x4U)
+#define I2C_C1_RSTA_SHIFT (2U)
+#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
+#define I2C_C1_TXAK_MASK (0x8U)
+#define I2C_C1_TXAK_SHIFT (3U)
+#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
+#define I2C_C1_TX_MASK (0x10U)
+#define I2C_C1_TX_SHIFT (4U)
+#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
+#define I2C_C1_MST_MASK (0x20U)
+#define I2C_C1_MST_SHIFT (5U)
+#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
+#define I2C_C1_IICIE_MASK (0x40U)
+#define I2C_C1_IICIE_SHIFT (6U)
+#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
+#define I2C_C1_IICEN_MASK (0x80U)
+#define I2C_C1_IICEN_SHIFT (7U)
+#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
+
+/*! @name S - I2C Status Register */
+#define I2C_S_RXAK_MASK (0x1U)
+#define I2C_S_RXAK_SHIFT (0U)
+#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
+#define I2C_S_IICIF_MASK (0x2U)
+#define I2C_S_IICIF_SHIFT (1U)
+#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
+#define I2C_S_SRW_MASK (0x4U)
+#define I2C_S_SRW_SHIFT (2U)
+#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
+#define I2C_S_RAM_MASK (0x8U)
+#define I2C_S_RAM_SHIFT (3U)
+#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
+#define I2C_S_ARBL_MASK (0x10U)
+#define I2C_S_ARBL_SHIFT (4U)
+#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
+#define I2C_S_BUSY_MASK (0x20U)
+#define I2C_S_BUSY_SHIFT (5U)
+#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
+#define I2C_S_IAAS_MASK (0x40U)
+#define I2C_S_IAAS_SHIFT (6U)
+#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
+#define I2C_S_TCF_MASK (0x80U)
+#define I2C_S_TCF_SHIFT (7U)
+#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
+
+/*! @name D - I2C Data I/O register */
+#define I2C_D_DATA_MASK (0xFFU)
+#define I2C_D_DATA_SHIFT (0U)
+#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
+
+/*! @name C2 - I2C Control Register 2 */
+#define I2C_C2_AD_MASK (0x7U)
+#define I2C_C2_AD_SHIFT (0U)
+#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK (0x8U)
+#define I2C_C2_RMEN_SHIFT (3U)
+#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
+#define I2C_C2_SBRC_MASK (0x10U)
+#define I2C_C2_SBRC_SHIFT (4U)
+#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
+#define I2C_C2_HDRS_MASK (0x20U)
+#define I2C_C2_HDRS_SHIFT (5U)
+#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
+#define I2C_C2_ADEXT_MASK (0x40U)
+#define I2C_C2_ADEXT_SHIFT (6U)
+#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
+#define I2C_C2_GCAEN_MASK (0x80U)
+#define I2C_C2_GCAEN_SHIFT (7U)
+#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
+
+/*! @name FLT - I2C Programmable Input Glitch Filter register */
+#define I2C_FLT_FLT_MASK (0x1FU)
+#define I2C_FLT_FLT_SHIFT (0U)
+#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
+
+/*! @name RA - I2C Range Address register */
+#define I2C_RA_RAD_MASK (0xFEU)
+#define I2C_RA_RAD_SHIFT (1U)
+#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
+
+/*! @name SMB - I2C SMBus Control and Status register */
+#define I2C_SMB_SHTF2IE_MASK (0x1U)
+#define I2C_SMB_SHTF2IE_SHIFT (0U)
+#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
+#define I2C_SMB_SHTF2_MASK (0x2U)
+#define I2C_SMB_SHTF2_SHIFT (1U)
+#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
+#define I2C_SMB_SHTF1_MASK (0x4U)
+#define I2C_SMB_SHTF1_SHIFT (2U)
+#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
+#define I2C_SMB_SLTF_MASK (0x8U)
+#define I2C_SMB_SLTF_SHIFT (3U)
+#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
+#define I2C_SMB_TCKSEL_MASK (0x10U)
+#define I2C_SMB_TCKSEL_SHIFT (4U)
+#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
+#define I2C_SMB_SIICAEN_MASK (0x20U)
+#define I2C_SMB_SIICAEN_SHIFT (5U)
+#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
+#define I2C_SMB_ALERTEN_MASK (0x40U)
+#define I2C_SMB_ALERTEN_SHIFT (6U)
+#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
+#define I2C_SMB_FACK_MASK (0x80U)
+#define I2C_SMB_FACK_SHIFT (7U)
+#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
+
+/*! @name A2 - I2C Address Register 2 */
+#define I2C_A2_SAD_MASK (0xFEU)
+#define I2C_A2_SAD_SHIFT (1U)
+#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
+
+/*! @name SLTH - I2C SCL Low Timeout Register High */
+#define I2C_SLTH_SSLT_MASK (0xFFU)
+#define I2C_SLTH_SSLT_SHIFT (0U)
+#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
+
+/*! @name SLTL - I2C SCL Low Timeout Register Low */
+#define I2C_SLTL_SSLT_MASK (0xFFU)
+#define I2C_SLTL_SSLT_SHIFT (0U)
+#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0 ((I2C_Type *)I2C0_BASE)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS { I2C0_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS { I2C0 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS { I2C0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
+ __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
+ __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+ __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+ __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+ __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+ uint8_t RESERVED_0[8];
+ __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+ uint8_t RESERVED_1[24];
+ __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
+ uint8_t RESERVED_2[24];
+ __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
+ uint8_t RESERVED_3[28];
+ __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
+ __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
+ __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+ __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+ __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+ __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+ uint8_t RESERVED_4[8];
+ __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+ uint8_t RESERVED_5[24];
+ __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_6[24];
+ __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
+ uint8_t RESERVED_7[28];
+ __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
+ __IO uint32_t MDR; /**< MCLK Divide Register, offset: 0x104 */
+} I2S_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2S Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/*! @name TCSR - SAI Transmit Control Register */
+#define I2S_TCSR_FRDE_MASK (0x1U)
+#define I2S_TCSR_FRDE_SHIFT (0U)
+#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
+#define I2S_TCSR_FWDE_MASK (0x2U)
+#define I2S_TCSR_FWDE_SHIFT (1U)
+#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
+#define I2S_TCSR_FRIE_MASK (0x100U)
+#define I2S_TCSR_FRIE_SHIFT (8U)
+#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
+#define I2S_TCSR_FWIE_MASK (0x200U)
+#define I2S_TCSR_FWIE_SHIFT (9U)
+#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
+#define I2S_TCSR_FEIE_MASK (0x400U)
+#define I2S_TCSR_FEIE_SHIFT (10U)
+#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
+#define I2S_TCSR_SEIE_MASK (0x800U)
+#define I2S_TCSR_SEIE_SHIFT (11U)
+#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
+#define I2S_TCSR_WSIE_MASK (0x1000U)
+#define I2S_TCSR_WSIE_SHIFT (12U)
+#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
+#define I2S_TCSR_FRF_MASK (0x10000U)
+#define I2S_TCSR_FRF_SHIFT (16U)
+#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
+#define I2S_TCSR_FWF_MASK (0x20000U)
+#define I2S_TCSR_FWF_SHIFT (17U)
+#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
+#define I2S_TCSR_FEF_MASK (0x40000U)
+#define I2S_TCSR_FEF_SHIFT (18U)
+#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
+#define I2S_TCSR_SEF_MASK (0x80000U)
+#define I2S_TCSR_SEF_SHIFT (19U)
+#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
+#define I2S_TCSR_WSF_MASK (0x100000U)
+#define I2S_TCSR_WSF_SHIFT (20U)
+#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
+#define I2S_TCSR_SR_MASK (0x1000000U)
+#define I2S_TCSR_SR_SHIFT (24U)
+#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
+#define I2S_TCSR_FR_MASK (0x2000000U)
+#define I2S_TCSR_FR_SHIFT (25U)
+#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
+#define I2S_TCSR_BCE_MASK (0x10000000U)
+#define I2S_TCSR_BCE_SHIFT (28U)
+#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
+#define I2S_TCSR_DBGE_MASK (0x20000000U)
+#define I2S_TCSR_DBGE_SHIFT (29U)
+#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
+#define I2S_TCSR_STOPE_MASK (0x40000000U)
+#define I2S_TCSR_STOPE_SHIFT (30U)
+#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
+#define I2S_TCSR_TE_MASK (0x80000000U)
+#define I2S_TCSR_TE_SHIFT (31U)
+#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
+
+/*! @name TCR1 - SAI Transmit Configuration 1 Register */
+#define I2S_TCR1_TFW_MASK (0x7U)
+#define I2S_TCR1_TFW_SHIFT (0U)
+#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
+
+/*! @name TCR2 - SAI Transmit Configuration 2 Register */
+#define I2S_TCR2_DIV_MASK (0xFFU)
+#define I2S_TCR2_DIV_SHIFT (0U)
+#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK (0x1000000U)
+#define I2S_TCR2_BCD_SHIFT (24U)
+#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
+#define I2S_TCR2_BCP_MASK (0x2000000U)
+#define I2S_TCR2_BCP_SHIFT (25U)
+#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
+#define I2S_TCR2_MSEL_MASK (0xC000000U)
+#define I2S_TCR2_MSEL_SHIFT (26U)
+#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK (0x10000000U)
+#define I2S_TCR2_BCI_SHIFT (28U)
+#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
+#define I2S_TCR2_BCS_MASK (0x20000000U)
+#define I2S_TCR2_BCS_SHIFT (29U)
+#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
+#define I2S_TCR2_SYNC_MASK (0xC0000000U)
+#define I2S_TCR2_SYNC_SHIFT (30U)
+#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
+
+/*! @name TCR3 - SAI Transmit Configuration 3 Register */
+#define I2S_TCR3_WDFL_MASK (0x1FU)
+#define I2S_TCR3_WDFL_SHIFT (0U)
+#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK (0x30000U)
+#define I2S_TCR3_TCE_SHIFT (16U)
+#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
+
+/*! @name TCR4 - SAI Transmit Configuration 4 Register */
+#define I2S_TCR4_FSD_MASK (0x1U)
+#define I2S_TCR4_FSD_SHIFT (0U)
+#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
+#define I2S_TCR4_FSP_MASK (0x2U)
+#define I2S_TCR4_FSP_SHIFT (1U)
+#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
+#define I2S_TCR4_FSE_MASK (0x8U)
+#define I2S_TCR4_FSE_SHIFT (3U)
+#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
+#define I2S_TCR4_MF_MASK (0x10U)
+#define I2S_TCR4_MF_SHIFT (4U)
+#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
+#define I2S_TCR4_SYWD_MASK (0x1F00U)
+#define I2S_TCR4_SYWD_SHIFT (8U)
+#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK (0x1F0000U)
+#define I2S_TCR4_FRSZ_SHIFT (16U)
+#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
+
+/*! @name TCR5 - SAI Transmit Configuration 5 Register */
+#define I2S_TCR5_FBT_MASK (0x1F00U)
+#define I2S_TCR5_FBT_SHIFT (8U)
+#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK (0x1F0000U)
+#define I2S_TCR5_W0W_SHIFT (16U)
+#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK (0x1F000000U)
+#define I2S_TCR5_WNW_SHIFT (24U)
+#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
+
+/*! @name TDR - SAI Transmit Data Register */
+#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
+#define I2S_TDR_TDR_SHIFT (0U)
+#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
+
+/* The count of I2S_TDR */
+#define I2S_TDR_COUNT (2U)
+
+/*! @name TFR - SAI Transmit FIFO Register */
+#define I2S_TFR_RFP_MASK (0xFU)
+#define I2S_TFR_RFP_SHIFT (0U)
+#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
+#define I2S_TFR_WFP_MASK (0xF0000U)
+#define I2S_TFR_WFP_SHIFT (16U)
+#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
+
+/* The count of I2S_TFR */
+#define I2S_TFR_COUNT (2U)
+
+/*! @name TMR - SAI Transmit Mask Register */
+#define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
+#define I2S_TMR_TWM_SHIFT (0U)
+#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
+
+/*! @name RCSR - SAI Receive Control Register */
+#define I2S_RCSR_FRDE_MASK (0x1U)
+#define I2S_RCSR_FRDE_SHIFT (0U)
+#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
+#define I2S_RCSR_FWDE_MASK (0x2U)
+#define I2S_RCSR_FWDE_SHIFT (1U)
+#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
+#define I2S_RCSR_FRIE_MASK (0x100U)
+#define I2S_RCSR_FRIE_SHIFT (8U)
+#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
+#define I2S_RCSR_FWIE_MASK (0x200U)
+#define I2S_RCSR_FWIE_SHIFT (9U)
+#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
+#define I2S_RCSR_FEIE_MASK (0x400U)
+#define I2S_RCSR_FEIE_SHIFT (10U)
+#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
+#define I2S_RCSR_SEIE_MASK (0x800U)
+#define I2S_RCSR_SEIE_SHIFT (11U)
+#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
+#define I2S_RCSR_WSIE_MASK (0x1000U)
+#define I2S_RCSR_WSIE_SHIFT (12U)
+#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
+#define I2S_RCSR_FRF_MASK (0x10000U)
+#define I2S_RCSR_FRF_SHIFT (16U)
+#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
+#define I2S_RCSR_FWF_MASK (0x20000U)
+#define I2S_RCSR_FWF_SHIFT (17U)
+#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
+#define I2S_RCSR_FEF_MASK (0x40000U)
+#define I2S_RCSR_FEF_SHIFT (18U)
+#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
+#define I2S_RCSR_SEF_MASK (0x80000U)
+#define I2S_RCSR_SEF_SHIFT (19U)
+#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
+#define I2S_RCSR_WSF_MASK (0x100000U)
+#define I2S_RCSR_WSF_SHIFT (20U)
+#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
+#define I2S_RCSR_SR_MASK (0x1000000U)
+#define I2S_RCSR_SR_SHIFT (24U)
+#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
+#define I2S_RCSR_FR_MASK (0x2000000U)
+#define I2S_RCSR_FR_SHIFT (25U)
+#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
+#define I2S_RCSR_BCE_MASK (0x10000000U)
+#define I2S_RCSR_BCE_SHIFT (28U)
+#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
+#define I2S_RCSR_DBGE_MASK (0x20000000U)
+#define I2S_RCSR_DBGE_SHIFT (29U)
+#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
+#define I2S_RCSR_STOPE_MASK (0x40000000U)
+#define I2S_RCSR_STOPE_SHIFT (30U)
+#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
+#define I2S_RCSR_RE_MASK (0x80000000U)
+#define I2S_RCSR_RE_SHIFT (31U)
+#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
+
+/*! @name RCR1 - SAI Receive Configuration 1 Register */
+#define I2S_RCR1_RFW_MASK (0x7U)
+#define I2S_RCR1_RFW_SHIFT (0U)
+#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
+
+/*! @name RCR2 - SAI Receive Configuration 2 Register */
+#define I2S_RCR2_DIV_MASK (0xFFU)
+#define I2S_RCR2_DIV_SHIFT (0U)
+#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK (0x1000000U)
+#define I2S_RCR2_BCD_SHIFT (24U)
+#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
+#define I2S_RCR2_BCP_MASK (0x2000000U)
+#define I2S_RCR2_BCP_SHIFT (25U)
+#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
+#define I2S_RCR2_MSEL_MASK (0xC000000U)
+#define I2S_RCR2_MSEL_SHIFT (26U)
+#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK (0x10000000U)
+#define I2S_RCR2_BCI_SHIFT (28U)
+#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
+#define I2S_RCR2_BCS_MASK (0x20000000U)
+#define I2S_RCR2_BCS_SHIFT (29U)
+#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
+#define I2S_RCR2_SYNC_MASK (0xC0000000U)
+#define I2S_RCR2_SYNC_SHIFT (30U)
+#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
+
+/*! @name RCR3 - SAI Receive Configuration 3 Register */
+#define I2S_RCR3_WDFL_MASK (0x1FU)
+#define I2S_RCR3_WDFL_SHIFT (0U)
+#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK (0x30000U)
+#define I2S_RCR3_RCE_SHIFT (16U)
+#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
+
+/*! @name RCR4 - SAI Receive Configuration 4 Register */
+#define I2S_RCR4_FSD_MASK (0x1U)
+#define I2S_RCR4_FSD_SHIFT (0U)
+#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
+#define I2S_RCR4_FSP_MASK (0x2U)
+#define I2S_RCR4_FSP_SHIFT (1U)
+#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
+#define I2S_RCR4_FSE_MASK (0x8U)
+#define I2S_RCR4_FSE_SHIFT (3U)
+#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
+#define I2S_RCR4_MF_MASK (0x10U)
+#define I2S_RCR4_MF_SHIFT (4U)
+#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
+#define I2S_RCR4_SYWD_MASK (0x1F00U)
+#define I2S_RCR4_SYWD_SHIFT (8U)
+#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK (0x1F0000U)
+#define I2S_RCR4_FRSZ_SHIFT (16U)
+#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
+
+/*! @name RCR5 - SAI Receive Configuration 5 Register */
+#define I2S_RCR5_FBT_MASK (0x1F00U)
+#define I2S_RCR5_FBT_SHIFT (8U)
+#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK (0x1F0000U)
+#define I2S_RCR5_W0W_SHIFT (16U)
+#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK (0x1F000000U)
+#define I2S_RCR5_WNW_SHIFT (24U)
+#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
+
+/*! @name RDR - SAI Receive Data Register */
+#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
+#define I2S_RDR_RDR_SHIFT (0U)
+#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
+
+/* The count of I2S_RDR */
+#define I2S_RDR_COUNT (2U)
+
+/*! @name RFR - SAI Receive FIFO Register */
+#define I2S_RFR_RFP_MASK (0xFU)
+#define I2S_RFR_RFP_SHIFT (0U)
+#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
+#define I2S_RFR_WFP_MASK (0xF0000U)
+#define I2S_RFR_WFP_SHIFT (16U)
+#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
+
+/* The count of I2S_RFR */
+#define I2S_RFR_COUNT (2U)
+
+/*! @name RMR - SAI Receive Mask Register */
+#define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
+#define I2S_RMR_RWM_SHIFT (0U)
+#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
+
+/*! @name MCR - SAI MCLK Control Register */
+#define I2S_MCR_MICS_MASK (0x3000000U)
+#define I2S_MCR_MICS_SHIFT (24U)
+#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK (0x40000000U)
+#define I2S_MCR_MOE_SHIFT (30U)
+#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
+#define I2S_MCR_DUF_MASK (0x80000000U)
+#define I2S_MCR_DUF_SHIFT (31U)
+#define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
+
+/*! @name MDR - MCLK Divide Register */
+#define I2S_MDR_DIVIDE_MASK (0xFFFU)
+#define I2S_MDR_DIVIDE_SHIFT (0U)
+#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK (0xFF000U)
+#define I2S_MDR_FRACT_SHIFT (12U)
+#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0 ((I2S_Type *)I2S0_BASE)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS { I2S0_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS { I2S0 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_RX_IRQS { I2S0_Rx_IRQn }
+#define I2S_TX_IRQS { I2S0_Tx_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PE1; /**< LLWU Pin Enable 1 Register, offset: 0x0 */
+ __IO uint8_t PE2; /**< LLWU Pin Enable 2 Register, offset: 0x1 */
+ __IO uint8_t PE3; /**< LLWU Pin Enable 3 Register, offset: 0x2 */
+ __IO uint8_t PE4; /**< LLWU Pin Enable 4 Register, offset: 0x3 */
+ __IO uint8_t ME; /**< LLWU Module Enable Register, offset: 0x4 */
+ __IO uint8_t F1; /**< LLWU Flag 1 Register, offset: 0x5 */
+ __IO uint8_t F2; /**< LLWU Flag 2 Register, offset: 0x6 */
+ __I uint8_t F3; /**< LLWU Flag 3 Register, offset: 0x7 */
+ __IO uint8_t FILT1; /**< LLWU Pin Filter 1 Register, offset: 0x8 */
+ __IO uint8_t FILT2; /**< LLWU Pin Filter 2 Register, offset: 0x9 */
+ __IO uint8_t RST; /**< LLWU Reset Enable Register, offset: 0xA */
+} LLWU_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/*! @name PE1 - LLWU Pin Enable 1 Register */
+#define LLWU_PE1_WUPE0_MASK (0x3U)
+#define LLWU_PE1_WUPE0_SHIFT (0U)
+#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK (0xCU)
+#define LLWU_PE1_WUPE1_SHIFT (2U)
+#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK (0x30U)
+#define LLWU_PE1_WUPE2_SHIFT (4U)
+#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK (0xC0U)
+#define LLWU_PE1_WUPE3_SHIFT (6U)
+#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
+
+/*! @name PE2 - LLWU Pin Enable 2 Register */
+#define LLWU_PE2_WUPE4_MASK (0x3U)
+#define LLWU_PE2_WUPE4_SHIFT (0U)
+#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK (0xCU)
+#define LLWU_PE2_WUPE5_SHIFT (2U)
+#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK (0x30U)
+#define LLWU_PE2_WUPE6_SHIFT (4U)
+#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK (0xC0U)
+#define LLWU_PE2_WUPE7_SHIFT (6U)
+#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
+
+/*! @name PE3 - LLWU Pin Enable 3 Register */
+#define LLWU_PE3_WUPE8_MASK (0x3U)
+#define LLWU_PE3_WUPE8_SHIFT (0U)
+#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK (0xCU)
+#define LLWU_PE3_WUPE9_SHIFT (2U)
+#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK (0x30U)
+#define LLWU_PE3_WUPE10_SHIFT (4U)
+#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK (0xC0U)
+#define LLWU_PE3_WUPE11_SHIFT (6U)
+#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
+
+/*! @name PE4 - LLWU Pin Enable 4 Register */
+#define LLWU_PE4_WUPE12_MASK (0x3U)
+#define LLWU_PE4_WUPE12_SHIFT (0U)
+#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK (0xCU)
+#define LLWU_PE4_WUPE13_SHIFT (2U)
+#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK (0x30U)
+#define LLWU_PE4_WUPE14_SHIFT (4U)
+#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK (0xC0U)
+#define LLWU_PE4_WUPE15_SHIFT (6U)
+#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
+
+/*! @name ME - LLWU Module Enable Register */
+#define LLWU_ME_WUME0_MASK (0x1U)
+#define LLWU_ME_WUME0_SHIFT (0U)
+#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
+#define LLWU_ME_WUME1_MASK (0x2U)
+#define LLWU_ME_WUME1_SHIFT (1U)
+#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
+#define LLWU_ME_WUME2_MASK (0x4U)
+#define LLWU_ME_WUME2_SHIFT (2U)
+#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
+#define LLWU_ME_WUME3_MASK (0x8U)
+#define LLWU_ME_WUME3_SHIFT (3U)
+#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
+#define LLWU_ME_WUME4_MASK (0x10U)
+#define LLWU_ME_WUME4_SHIFT (4U)
+#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
+#define LLWU_ME_WUME5_MASK (0x20U)
+#define LLWU_ME_WUME5_SHIFT (5U)
+#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
+#define LLWU_ME_WUME6_MASK (0x40U)
+#define LLWU_ME_WUME6_SHIFT (6U)
+#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
+#define LLWU_ME_WUME7_MASK (0x80U)
+#define LLWU_ME_WUME7_SHIFT (7U)
+#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
+
+/*! @name F1 - LLWU Flag 1 Register */
+#define LLWU_F1_WUF0_MASK (0x1U)
+#define LLWU_F1_WUF0_SHIFT (0U)
+#define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
+#define LLWU_F1_WUF1_MASK (0x2U)
+#define LLWU_F1_WUF1_SHIFT (1U)
+#define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
+#define LLWU_F1_WUF2_MASK (0x4U)
+#define LLWU_F1_WUF2_SHIFT (2U)
+#define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
+#define LLWU_F1_WUF3_MASK (0x8U)
+#define LLWU_F1_WUF3_SHIFT (3U)
+#define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
+#define LLWU_F1_WUF4_MASK (0x10U)
+#define LLWU_F1_WUF4_SHIFT (4U)
+#define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
+#define LLWU_F1_WUF5_MASK (0x20U)
+#define LLWU_F1_WUF5_SHIFT (5U)
+#define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
+#define LLWU_F1_WUF6_MASK (0x40U)
+#define LLWU_F1_WUF6_SHIFT (6U)
+#define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
+#define LLWU_F1_WUF7_MASK (0x80U)
+#define LLWU_F1_WUF7_SHIFT (7U)
+#define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
+
+/*! @name F2 - LLWU Flag 2 Register */
+#define LLWU_F2_WUF8_MASK (0x1U)
+#define LLWU_F2_WUF8_SHIFT (0U)
+#define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
+#define LLWU_F2_WUF9_MASK (0x2U)
+#define LLWU_F2_WUF9_SHIFT (1U)
+#define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
+#define LLWU_F2_WUF10_MASK (0x4U)
+#define LLWU_F2_WUF10_SHIFT (2U)
+#define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
+#define LLWU_F2_WUF11_MASK (0x8U)
+#define LLWU_F2_WUF11_SHIFT (3U)
+#define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
+#define LLWU_F2_WUF12_MASK (0x10U)
+#define LLWU_F2_WUF12_SHIFT (4U)
+#define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
+#define LLWU_F2_WUF13_MASK (0x20U)
+#define LLWU_F2_WUF13_SHIFT (5U)
+#define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
+#define LLWU_F2_WUF14_MASK (0x40U)
+#define LLWU_F2_WUF14_SHIFT (6U)
+#define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
+#define LLWU_F2_WUF15_MASK (0x80U)
+#define LLWU_F2_WUF15_SHIFT (7U)
+#define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
+
+/*! @name F3 - LLWU Flag 3 Register */
+#define LLWU_F3_MWUF0_MASK (0x1U)
+#define LLWU_F3_MWUF0_SHIFT (0U)
+#define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
+#define LLWU_F3_MWUF1_MASK (0x2U)
+#define LLWU_F3_MWUF1_SHIFT (1U)
+#define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
+#define LLWU_F3_MWUF2_MASK (0x4U)
+#define LLWU_F3_MWUF2_SHIFT (2U)
+#define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
+#define LLWU_F3_MWUF3_MASK (0x8U)
+#define LLWU_F3_MWUF3_SHIFT (3U)
+#define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
+#define LLWU_F3_MWUF4_MASK (0x10U)
+#define LLWU_F3_MWUF4_SHIFT (4U)
+#define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
+#define LLWU_F3_MWUF5_MASK (0x20U)
+#define LLWU_F3_MWUF5_SHIFT (5U)
+#define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
+#define LLWU_F3_MWUF6_MASK (0x40U)
+#define LLWU_F3_MWUF6_SHIFT (6U)
+#define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
+#define LLWU_F3_MWUF7_MASK (0x80U)
+#define LLWU_F3_MWUF7_SHIFT (7U)
+#define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
+
+/*! @name FILT1 - LLWU Pin Filter 1 Register */
+#define LLWU_FILT1_FILTSEL_MASK (0xFU)
+#define LLWU_FILT1_FILTSEL_SHIFT (0U)
+#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK (0x60U)
+#define LLWU_FILT1_FILTE_SHIFT (5U)
+#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK (0x80U)
+#define LLWU_FILT1_FILTF_SHIFT (7U)
+#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
+
+/*! @name FILT2 - LLWU Pin Filter 2 Register */
+#define LLWU_FILT2_FILTSEL_MASK (0xFU)
+#define LLWU_FILT2_FILTSEL_SHIFT (0U)
+#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK (0x60U)
+#define LLWU_FILT2_FILTE_SHIFT (5U)
+#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK (0x80U)
+#define LLWU_FILT2_FILTF_SHIFT (7U)
+#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
+
+/*! @name RST - LLWU Reset Enable Register */
+#define LLWU_RST_RSTFILT_MASK (0x1U)
+#define LLWU_RST_RSTFILT_SHIFT (0U)
+#define LLWU_RST_RSTFILT(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_RSTFILT_SHIFT)) & LLWU_RST_RSTFILT_MASK)
+#define LLWU_RST_LLRSTE_MASK (0x2U)
+#define LLWU_RST_LLRSTE_SHIFT (1U)
+#define LLWU_RST_LLRSTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_LLRSTE_SHIFT)) & LLWU_RST_LLRSTE_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU ((LLWU_Type *)LLWU_BASE)
+/** Array initializer of LLWU peripheral base addresses */
+#define LLWU_BASE_ADDRS { LLWU_BASE }
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASE_PTRS { LLWU }
+/** Interrupt vectors for the LLWU peripheral type */
+#define LLWU_IRQS { LLW_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
+ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
+ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
+ __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/*! @name CSR - Low Power Timer Control Status Register */
+#define LPTMR_CSR_TEN_MASK (0x1U)
+#define LPTMR_CSR_TEN_SHIFT (0U)
+#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
+#define LPTMR_CSR_TMS_MASK (0x2U)
+#define LPTMR_CSR_TMS_SHIFT (1U)
+#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
+#define LPTMR_CSR_TFC_MASK (0x4U)
+#define LPTMR_CSR_TFC_SHIFT (2U)
+#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
+#define LPTMR_CSR_TPP_MASK (0x8U)
+#define LPTMR_CSR_TPP_SHIFT (3U)
+#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
+#define LPTMR_CSR_TPS_MASK (0x30U)
+#define LPTMR_CSR_TPS_SHIFT (4U)
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK (0x40U)
+#define LPTMR_CSR_TIE_SHIFT (6U)
+#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
+#define LPTMR_CSR_TCF_MASK (0x80U)
+#define LPTMR_CSR_TCF_SHIFT (7U)
+#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
+
+/*! @name PSR - Low Power Timer Prescale Register */
+#define LPTMR_PSR_PCS_MASK (0x3U)
+#define LPTMR_PSR_PCS_SHIFT (0U)
+#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK (0x4U)
+#define LPTMR_PSR_PBYP_SHIFT (2U)
+#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
+#define LPTMR_PSR_PRESCALE_MASK (0x78U)
+#define LPTMR_PSR_PRESCALE_SHIFT (3U)
+#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
+
+/*! @name CMR - Low Power Timer Compare Register */
+#define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
+#define LPTMR_CMR_COMPARE_SHIFT (0U)
+#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
+
+/*! @name CNR - Low Power Timer Counter Register */
+#define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
+#define LPTMR_CNR_COUNTER_SHIFT (0U)
+#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
+/** Array initializer of LPTMR peripheral base addresses */
+#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASE_PTRS { LPTMR0 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS { LPTimer_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
+ __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
+ __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
+ __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
+ __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
+ __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
+ __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+ __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+ __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
+ __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
+} MCG_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MCG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/*! @name C1 - MCG Control 1 Register */
+#define MCG_C1_IREFSTEN_MASK (0x1U)
+#define MCG_C1_IREFSTEN_SHIFT (0U)
+#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
+#define MCG_C1_IRCLKEN_MASK (0x2U)
+#define MCG_C1_IRCLKEN_SHIFT (1U)
+#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
+#define MCG_C1_IREFS_MASK (0x4U)
+#define MCG_C1_IREFS_SHIFT (2U)
+#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
+#define MCG_C1_FRDIV_MASK (0x38U)
+#define MCG_C1_FRDIV_SHIFT (3U)
+#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK (0xC0U)
+#define MCG_C1_CLKS_SHIFT (6U)
+#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
+
+/*! @name C2 - MCG Control 2 Register */
+#define MCG_C2_IRCS_MASK (0x1U)
+#define MCG_C2_IRCS_SHIFT (0U)
+#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
+#define MCG_C2_LP_MASK (0x2U)
+#define MCG_C2_LP_SHIFT (1U)
+#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
+#define MCG_C2_EREFS0_MASK (0x4U)
+#define MCG_C2_EREFS0_SHIFT (2U)
+#define MCG_C2_EREFS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS0_SHIFT)) & MCG_C2_EREFS0_MASK)
+#define MCG_C2_HGO0_MASK (0x8U)
+#define MCG_C2_HGO0_SHIFT (3U)
+#define MCG_C2_HGO0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO0_SHIFT)) & MCG_C2_HGO0_MASK)
+#define MCG_C2_RANGE0_MASK (0x30U)
+#define MCG_C2_RANGE0_SHIFT (4U)
+#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE0_SHIFT)) & MCG_C2_RANGE0_MASK)
+#define MCG_C2_LOCRE0_MASK (0x80U)
+#define MCG_C2_LOCRE0_SHIFT (7U)
+#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
+
+/*! @name C3 - MCG Control 3 Register */
+#define MCG_C3_SCTRIM_MASK (0xFFU)
+#define MCG_C3_SCTRIM_SHIFT (0U)
+#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
+
+/*! @name C4 - MCG Control 4 Register */
+#define MCG_C4_SCFTRIM_MASK (0x1U)
+#define MCG_C4_SCFTRIM_SHIFT (0U)
+#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
+#define MCG_C4_FCTRIM_MASK (0x1EU)
+#define MCG_C4_FCTRIM_SHIFT (1U)
+#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK (0x60U)
+#define MCG_C4_DRST_DRS_SHIFT (5U)
+#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK (0x80U)
+#define MCG_C4_DMX32_SHIFT (7U)
+#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
+
+/*! @name C5 - MCG Control 5 Register */
+#define MCG_C5_PRDIV0_MASK (0x1FU)
+#define MCG_C5_PRDIV0_SHIFT (0U)
+#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK (0x20U)
+#define MCG_C5_PLLSTEN0_SHIFT (5U)
+#define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)
+#define MCG_C5_PLLCLKEN0_MASK (0x40U)
+#define MCG_C5_PLLCLKEN0_SHIFT (6U)
+#define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)
+
+/*! @name C6 - MCG Control 6 Register */
+#define MCG_C6_VDIV0_MASK (0x1FU)
+#define MCG_C6_VDIV0_SHIFT (0U)
+#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK (0x20U)
+#define MCG_C6_CME0_SHIFT (5U)
+#define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
+#define MCG_C6_PLLS_MASK (0x40U)
+#define MCG_C6_PLLS_SHIFT (6U)
+#define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
+#define MCG_C6_LOLIE0_MASK (0x80U)
+#define MCG_C6_LOLIE0_SHIFT (7U)
+#define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
+
+/*! @name S - MCG Status Register */
+#define MCG_S_IRCST_MASK (0x1U)
+#define MCG_S_IRCST_SHIFT (0U)
+#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
+#define MCG_S_OSCINIT0_MASK (0x2U)
+#define MCG_S_OSCINIT0_SHIFT (1U)
+#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
+#define MCG_S_CLKST_MASK (0xCU)
+#define MCG_S_CLKST_SHIFT (2U)
+#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK (0x10U)
+#define MCG_S_IREFST_SHIFT (4U)
+#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
+#define MCG_S_PLLST_MASK (0x20U)
+#define MCG_S_PLLST_SHIFT (5U)
+#define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
+#define MCG_S_LOCK0_MASK (0x40U)
+#define MCG_S_LOCK0_SHIFT (6U)
+#define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
+#define MCG_S_LOLS0_MASK (0x80U)
+#define MCG_S_LOLS0_SHIFT (7U)
+#define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
+
+/*! @name SC - MCG Status and Control Register */
+#define MCG_SC_LOCS0_MASK (0x1U)
+#define MCG_SC_LOCS0_SHIFT (0U)
+#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
+#define MCG_SC_FCRDIV_MASK (0xEU)
+#define MCG_SC_FCRDIV_SHIFT (1U)
+#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK (0x10U)
+#define MCG_SC_FLTPRSRV_SHIFT (4U)
+#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
+#define MCG_SC_ATMF_MASK (0x20U)
+#define MCG_SC_ATMF_SHIFT (5U)
+#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
+#define MCG_SC_ATMS_MASK (0x40U)
+#define MCG_SC_ATMS_SHIFT (6U)
+#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
+#define MCG_SC_ATME_MASK (0x80U)
+#define MCG_SC_ATME_SHIFT (7U)
+#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
+
+/*! @name ATCVH - MCG Auto Trim Compare Value High Register */
+#define MCG_ATCVH_ATCVH_MASK (0xFFU)
+#define MCG_ATCVH_ATCVH_SHIFT (0U)
+#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
+
+/*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
+#define MCG_ATCVL_ATCVL_MASK (0xFFU)
+#define MCG_ATCVL_ATCVL_SHIFT (0U)
+#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
+
+/*! @name C7 - MCG Control 7 Register */
+#define MCG_C7_OSCSEL_MASK (0x1U)
+#define MCG_C7_OSCSEL_SHIFT (0U)
+#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
+
+/*! @name C8 - MCG Control 8 Register */
+#define MCG_C8_LOCS1_MASK (0x1U)
+#define MCG_C8_LOCS1_SHIFT (0U)
+#define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
+#define MCG_C8_CME1_MASK (0x20U)
+#define MCG_C8_CME1_SHIFT (5U)
+#define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
+#define MCG_C8_LOLRE_MASK (0x40U)
+#define MCG_C8_LOLRE_SHIFT (6U)
+#define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
+#define MCG_C8_LOCRE1_MASK (0x80U)
+#define MCG_C8_LOCRE1_SHIFT (7U)
+#define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG ((MCG_Type *)MCG_BASE)
+/** Array initializer of MCG peripheral base addresses */
+#define MCG_BASE_ADDRS { MCG_BASE }
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASE_PTRS { MCG }
+/* MCG C2[EREFS] backward compatibility */
+#define MCG_C2_EREFS_MASK (MCG_C2_EREFS0_MASK)
+#define MCG_C2_EREFS_SHIFT (MCG_C2_EREFS0_SHIFT)
+#define MCG_C2_EREFS_WIDTH (MCG_C2_EREFS0_WIDTH)
+#define MCG_C2_EREFS(x) (MCG_C2_EREFS0(x))
+
+/* MCG C2[HGO] backward compatibility */
+#define MCG_C2_HGO_MASK (MCG_C2_HGO0_MASK)
+#define MCG_C2_HGO_SHIFT (MCG_C2_HGO0_SHIFT)
+#define MCG_C2_HGO_WIDTH (MCG_C2_HGO0_WIDTH)
+#define MCG_C2_HGO(x) (MCG_C2_HGO0(x))
+
+/* MCG C2[RANGE] backward compatibility */
+#define MCG_C2_RANGE_MASK (MCG_C2_RANGE0_MASK)
+#define MCG_C2_RANGE_SHIFT (MCG_C2_RANGE0_SHIFT)
+#define MCG_C2_RANGE_WIDTH (MCG_C2_RANGE0_WIDTH)
+#define MCG_C2_RANGE(x) (MCG_C2_RANGE0(x))
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+ __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
+ __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
+ __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
+ __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
+ __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
+ __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
+ __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
+ __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
+ __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+ __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+ __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+ __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+ __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
+ __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
+ __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
+ __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
+} NV_Type;
+
+/* ----------------------------------------------------------------------------
+ -- NV Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/*! @name BACKKEY3 - Backdoor Comparison Key 3. */
+#define NV_BACKKEY3_KEY_MASK (0xFFU)
+#define NV_BACKKEY3_KEY_SHIFT (0U)
+#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
+
+/*! @name BACKKEY2 - Backdoor Comparison Key 2. */
+#define NV_BACKKEY2_KEY_MASK (0xFFU)
+#define NV_BACKKEY2_KEY_SHIFT (0U)
+#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
+
+/*! @name BACKKEY1 - Backdoor Comparison Key 1. */
+#define NV_BACKKEY1_KEY_MASK (0xFFU)
+#define NV_BACKKEY1_KEY_SHIFT (0U)
+#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
+
+/*! @name BACKKEY0 - Backdoor Comparison Key 0. */
+#define NV_BACKKEY0_KEY_MASK (0xFFU)
+#define NV_BACKKEY0_KEY_SHIFT (0U)
+#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
+
+/*! @name BACKKEY7 - Backdoor Comparison Key 7. */
+#define NV_BACKKEY7_KEY_MASK (0xFFU)
+#define NV_BACKKEY7_KEY_SHIFT (0U)
+#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
+
+/*! @name BACKKEY6 - Backdoor Comparison Key 6. */
+#define NV_BACKKEY6_KEY_MASK (0xFFU)
+#define NV_BACKKEY6_KEY_SHIFT (0U)
+#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
+
+/*! @name BACKKEY5 - Backdoor Comparison Key 5. */
+#define NV_BACKKEY5_KEY_MASK (0xFFU)
+#define NV_BACKKEY5_KEY_SHIFT (0U)
+#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
+
+/*! @name BACKKEY4 - Backdoor Comparison Key 4. */
+#define NV_BACKKEY4_KEY_MASK (0xFFU)
+#define NV_BACKKEY4_KEY_SHIFT (0U)
+#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
+
+/*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
+#define NV_FPROT3_PROT_MASK (0xFFU)
+#define NV_FPROT3_PROT_SHIFT (0U)
+#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
+
+/*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
+#define NV_FPROT2_PROT_MASK (0xFFU)
+#define NV_FPROT2_PROT_SHIFT (0U)
+#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
+
+/*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
+#define NV_FPROT1_PROT_MASK (0xFFU)
+#define NV_FPROT1_PROT_SHIFT (0U)
+#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
+
+/*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
+#define NV_FPROT0_PROT_MASK (0xFFU)
+#define NV_FPROT0_PROT_SHIFT (0U)
+#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
+
+/*! @name FSEC - Non-volatile Flash Security Register */
+#define NV_FSEC_SEC_MASK (0x3U)
+#define NV_FSEC_SEC_SHIFT (0U)
+#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK (0xCU)
+#define NV_FSEC_FSLACC_SHIFT (2U)
+#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK (0x30U)
+#define NV_FSEC_MEEN_SHIFT (4U)
+#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK (0xC0U)
+#define NV_FSEC_KEYEN_SHIFT (6U)
+#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
+
+/*! @name FOPT - Non-volatile Flash Option Register */
+#define NV_FOPT_LPBOOT_MASK (0x1U)
+#define NV_FOPT_LPBOOT_SHIFT (0U)
+#define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
+#define NV_FOPT_EZPORT_DIS_MASK (0x2U)
+#define NV_FOPT_EZPORT_DIS_SHIFT (1U)
+#define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK)
+#define NV_FOPT_NMI_DIS_MASK (0x4U)
+#define NV_FOPT_NMI_DIS_SHIFT (2U)
+#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
+
+/*! @name FEPROT - Non-volatile EERAM Protection Register */
+#define NV_FEPROT_EPROT_MASK (0xFFU)
+#define NV_FEPROT_EPROT_SHIFT (0U)
+#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FEPROT_EPROT_SHIFT)) & NV_FEPROT_EPROT_MASK)
+
+/*! @name FDPROT - Non-volatile D-Flash Protection Register */
+#define NV_FDPROT_DPROT_MASK (0xFFU)
+#define NV_FDPROT_DPROT_SHIFT (0U)
+#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FDPROT_DPROT_SHIFT)) & NV_FDPROT_DPROT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFL_FlashConfig base address */
+#define FTFL_FlashConfig_BASE (0x400u)
+/** Peripheral FTFL_FlashConfig base pointer */
+#define FTFL_FlashConfig ((NV_Type *)FTFL_FlashConfig_BASE)
+/** Array initializer of NV peripheral base addresses */
+#define NV_BASE_ADDRS { FTFL_FlashConfig_BASE }
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASE_PTRS { FTFL_FlashConfig }
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
+} OSC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- OSC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/*! @name CR - OSC Control Register */
+#define OSC_CR_SC16P_MASK (0x1U)
+#define OSC_CR_SC16P_SHIFT (0U)
+#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
+#define OSC_CR_SC8P_MASK (0x2U)
+#define OSC_CR_SC8P_SHIFT (1U)
+#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
+#define OSC_CR_SC4P_MASK (0x4U)
+#define OSC_CR_SC4P_SHIFT (2U)
+#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
+#define OSC_CR_SC2P_MASK (0x8U)
+#define OSC_CR_SC2P_SHIFT (3U)
+#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
+#define OSC_CR_EREFSTEN_MASK (0x20U)
+#define OSC_CR_EREFSTEN_SHIFT (5U)
+#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
+#define OSC_CR_ERCLKEN_MASK (0x80U)
+#define OSC_CR_ERCLKEN_SHIFT (7U)
+#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC0 base address */
+#define OSC0_BASE (0x40065000u)
+/** Peripheral OSC0 base pointer */
+#define OSC0 ((OSC_Type *)OSC0_BASE)
+/** Array initializer of OSC peripheral base addresses */
+#define OSC_BASE_ADDRS { OSC0_BASE }
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASE_PTRS { OSC0 }
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PDB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
+ * @{
+ */
+
+/** PDB - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control Register, offset: 0x0 */
+ __IO uint32_t MOD; /**< Modulus Register, offset: 0x4 */
+ __I uint32_t CNT; /**< Counter Register, offset: 0x8 */
+ __IO uint32_t IDLY; /**< Interrupt Delay Register, offset: 0xC */
+ struct { /* offset: 0x10, array step: 0x10 */
+ __IO uint32_t C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x10 */
+ __IO uint32_t S; /**< Channel n Status Register, array offset: 0x14, array step: 0x10 */
+ __IO uint32_t DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x10, index2*0x4 */
+ } CH[1];
+ uint8_t RESERVED_0[368];
+ __IO uint32_t POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */
+ __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */
+} PDB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PDB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Masks PDB Register Masks
+ * @{
+ */
+
+/*! @name SC - Status and Control Register */
+#define PDB_SC_LDOK_MASK (0x1U)
+#define PDB_SC_LDOK_SHIFT (0U)
+#define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
+#define PDB_SC_CONT_MASK (0x2U)
+#define PDB_SC_CONT_SHIFT (1U)
+#define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
+#define PDB_SC_MULT_MASK (0xCU)
+#define PDB_SC_MULT_SHIFT (2U)
+#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
+#define PDB_SC_PDBIE_MASK (0x20U)
+#define PDB_SC_PDBIE_SHIFT (5U)
+#define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
+#define PDB_SC_PDBIF_MASK (0x40U)
+#define PDB_SC_PDBIF_SHIFT (6U)
+#define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
+#define PDB_SC_PDBEN_MASK (0x80U)
+#define PDB_SC_PDBEN_SHIFT (7U)
+#define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
+#define PDB_SC_TRGSEL_MASK (0xF00U)
+#define PDB_SC_TRGSEL_SHIFT (8U)
+#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
+#define PDB_SC_PRESCALER_MASK (0x7000U)
+#define PDB_SC_PRESCALER_SHIFT (12U)
+#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
+#define PDB_SC_DMAEN_MASK (0x8000U)
+#define PDB_SC_DMAEN_SHIFT (15U)
+#define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
+#define PDB_SC_SWTRIG_MASK (0x10000U)
+#define PDB_SC_SWTRIG_SHIFT (16U)
+#define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
+#define PDB_SC_PDBEIE_MASK (0x20000U)
+#define PDB_SC_PDBEIE_SHIFT (17U)
+#define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
+#define PDB_SC_LDMOD_MASK (0xC0000U)
+#define PDB_SC_LDMOD_SHIFT (18U)
+#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
+
+/*! @name MOD - Modulus Register */
+#define PDB_MOD_MOD_MASK (0xFFFFU)
+#define PDB_MOD_MOD_SHIFT (0U)
+#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
+
+/*! @name CNT - Counter Register */
+#define PDB_CNT_CNT_MASK (0xFFFFU)
+#define PDB_CNT_CNT_SHIFT (0U)
+#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
+
+/*! @name IDLY - Interrupt Delay Register */
+#define PDB_IDLY_IDLY_MASK (0xFFFFU)
+#define PDB_IDLY_IDLY_SHIFT (0U)
+#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
+
+/*! @name C1 - Channel n Control Register 1 */
+#define PDB_C1_EN_MASK (0xFFU)
+#define PDB_C1_EN_SHIFT (0U)
+#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
+#define PDB_C1_TOS_MASK (0xFF00U)
+#define PDB_C1_TOS_SHIFT (8U)
+#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
+#define PDB_C1_BB_MASK (0xFF0000U)
+#define PDB_C1_BB_SHIFT (16U)
+#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
+
+/* The count of PDB_C1 */
+#define PDB_C1_COUNT (1U)
+
+/*! @name S - Channel n Status Register */
+#define PDB_S_ERR_MASK (0xFFU)
+#define PDB_S_ERR_SHIFT (0U)
+#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
+#define PDB_S_CF_MASK (0xFF0000U)
+#define PDB_S_CF_SHIFT (16U)
+#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
+
+/* The count of PDB_S */
+#define PDB_S_COUNT (1U)
+
+/*! @name DLY - Channel n Delay 0 Register..Channel n Delay 1 Register */
+#define PDB_DLY_DLY_MASK (0xFFFFU)
+#define PDB_DLY_DLY_SHIFT (0U)
+#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
+
+/* The count of PDB_DLY */
+#define PDB_DLY_COUNT (1U)
+
+/* The count of PDB_DLY */
+#define PDB_DLY_COUNT2 (2U)
+
+/*! @name POEN - Pulse-Out n Enable Register */
+#define PDB_POEN_POEN_MASK (0xFFU)
+#define PDB_POEN_POEN_SHIFT (0U)
+#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
+
+/*! @name PODLY - Pulse-Out n Delay Register */
+#define PDB_PODLY_DLY2_MASK (0xFFFFU)
+#define PDB_PODLY_DLY2_SHIFT (0U)
+#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY1_MASK (0xFFFF0000U)
+#define PDB_PODLY_DLY1_SHIFT (16U)
+#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
+
+/* The count of PDB_PODLY */
+#define PDB_PODLY_COUNT (2U)
+
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Masks */
+
+
+/* PDB - Peripheral instance base addresses */
+/** Peripheral PDB0 base address */
+#define PDB0_BASE (0x40036000u)
+/** Peripheral PDB0 base pointer */
+#define PDB0 ((PDB_Type *)PDB0_BASE)
+/** Array initializer of PDB peripheral base addresses */
+#define PDB_BASE_ADDRS { PDB0_BASE }
+/** Array initializer of PDB peripheral base pointers */
+#define PDB_BASE_PTRS { PDB0 }
+/** Interrupt vectors for the PDB peripheral type */
+#define PDB_IRQS { PDB0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PDB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[252];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+ __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+ __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+ } CHANNEL[4];
+} PIT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PIT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/*! @name MCR - PIT Module Control Register */
+#define PIT_MCR_FRZ_MASK (0x1U)
+#define PIT_MCR_FRZ_SHIFT (0U)
+#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
+#define PIT_MCR_MDIS_MASK (0x2U)
+#define PIT_MCR_MDIS_SHIFT (1U)
+#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
+
+/*! @name LDVAL - Timer Load Value Register */
+#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
+#define PIT_LDVAL_TSV_SHIFT (0U)
+#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
+
+/* The count of PIT_LDVAL */
+#define PIT_LDVAL_COUNT (4U)
+
+/*! @name CVAL - Current Timer Value Register */
+#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
+#define PIT_CVAL_TVL_SHIFT (0U)
+#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
+
+/* The count of PIT_CVAL */
+#define PIT_CVAL_COUNT (4U)
+
+/*! @name TCTRL - Timer Control Register */
+#define PIT_TCTRL_TEN_MASK (0x1U)
+#define PIT_TCTRL_TEN_SHIFT (0U)
+#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
+#define PIT_TCTRL_TIE_MASK (0x2U)
+#define PIT_TCTRL_TIE_SHIFT (1U)
+#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
+
+/* The count of PIT_TCTRL */
+#define PIT_TCTRL_COUNT (4U)
+
+/*! @name TFLG - Timer Flag Register */
+#define PIT_TFLG_TIF_MASK (0x1U)
+#define PIT_TFLG_TIF_SHIFT (0U)
+#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
+
+/* The count of PIT_TFLG */
+#define PIT_TFLG_COUNT (4U)
+
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT ((PIT_Type *)PIT_BASE)
+/** Array initializer of PIT peripheral base addresses */
+#define PIT_BASE_ADDRS { PIT_BASE }
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASE_PTRS { PIT }
+/** Interrupt vectors for the PIT peripheral type */
+#define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t LVDSC1; /**< Low Voltage Detect Status and Control 1 Register, offset: 0x0 */
+ __IO uint8_t LVDSC2; /**< Low Voltage Detect Status and Control 2 Register, offset: 0x1 */
+ __IO uint8_t REGSC; /**< Regulator Status and Control Register, offset: 0x2 */
+} PMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/*! @name LVDSC1 - Low Voltage Detect Status and Control 1 Register */
+#define PMC_LVDSC1_LVDV_MASK (0x3U)
+#define PMC_LVDSC1_LVDV_SHIFT (0U)
+#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK (0x10U)
+#define PMC_LVDSC1_LVDRE_SHIFT (4U)
+#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
+#define PMC_LVDSC1_LVDIE_MASK (0x20U)
+#define PMC_LVDSC1_LVDIE_SHIFT (5U)
+#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
+#define PMC_LVDSC1_LVDACK_MASK (0x40U)
+#define PMC_LVDSC1_LVDACK_SHIFT (6U)
+#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
+#define PMC_LVDSC1_LVDF_MASK (0x80U)
+#define PMC_LVDSC1_LVDF_SHIFT (7U)
+#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
+
+/*! @name LVDSC2 - Low Voltage Detect Status and Control 2 Register */
+#define PMC_LVDSC2_LVWV_MASK (0x3U)
+#define PMC_LVDSC2_LVWV_SHIFT (0U)
+#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK (0x20U)
+#define PMC_LVDSC2_LVWIE_SHIFT (5U)
+#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
+#define PMC_LVDSC2_LVWACK_MASK (0x40U)
+#define PMC_LVDSC2_LVWACK_SHIFT (6U)
+#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
+#define PMC_LVDSC2_LVWF_MASK (0x80U)
+#define PMC_LVDSC2_LVWF_SHIFT (7U)
+#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
+
+/*! @name REGSC - Regulator Status and Control Register */
+#define PMC_REGSC_BGBE_MASK (0x1U)
+#define PMC_REGSC_BGBE_SHIFT (0U)
+#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
+#define PMC_REGSC_REGONS_MASK (0x4U)
+#define PMC_REGSC_REGONS_SHIFT (2U)
+#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
+#define PMC_REGSC_ACKISO_MASK (0x8U)
+#define PMC_REGSC_ACKISO_SHIFT (3U)
+#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC ((PMC_Type *)PMC_BASE)
+/** Array initializer of PMC peripheral base addresses */
+#define PMC_BASE_ADDRS { PMC_BASE }
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASE_PTRS { PMC }
+/** Interrupt vectors for the PMC peripheral type */
+#define PMC_IRQS { LVD_LVW_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
+ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
+ uint8_t RESERVED_0[24];
+ __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
+ uint8_t RESERVED_1[28];
+ __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
+ __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
+ __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
+} PORT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PORT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/*! @name PCR - Pin Control Register n */
+#define PORT_PCR_PS_MASK (0x1U)
+#define PORT_PCR_PS_SHIFT (0U)
+#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
+#define PORT_PCR_PE_MASK (0x2U)
+#define PORT_PCR_PE_SHIFT (1U)
+#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
+#define PORT_PCR_SRE_MASK (0x4U)
+#define PORT_PCR_SRE_SHIFT (2U)
+#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
+#define PORT_PCR_PFE_MASK (0x10U)
+#define PORT_PCR_PFE_SHIFT (4U)
+#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
+#define PORT_PCR_ODE_MASK (0x20U)
+#define PORT_PCR_ODE_SHIFT (5U)
+#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
+#define PORT_PCR_DSE_MASK (0x40U)
+#define PORT_PCR_DSE_SHIFT (6U)
+#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
+#define PORT_PCR_MUX_MASK (0x700U)
+#define PORT_PCR_MUX_SHIFT (8U)
+#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
+#define PORT_PCR_LK_MASK (0x8000U)
+#define PORT_PCR_LK_SHIFT (15U)
+#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
+#define PORT_PCR_IRQC_MASK (0xF0000U)
+#define PORT_PCR_IRQC_SHIFT (16U)
+#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK (0x1000000U)
+#define PORT_PCR_ISF_SHIFT (24U)
+#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
+
+/* The count of PORT_PCR */
+#define PORT_PCR_COUNT (32U)
+
+/*! @name GPCLR - Global Pin Control Low Register */
+#define PORT_GPCLR_GPWD_MASK (0xFFFFU)
+#define PORT_GPCLR_GPWD_SHIFT (0U)
+#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
+#define PORT_GPCLR_GPWE_SHIFT (16U)
+#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
+
+/*! @name GPCHR - Global Pin Control High Register */
+#define PORT_GPCHR_GPWD_MASK (0xFFFFU)
+#define PORT_GPCHR_GPWD_SHIFT (0U)
+#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
+#define PORT_GPCHR_GPWE_SHIFT (16U)
+#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
+
+/*! @name ISFR - Interrupt Status Flag Register */
+#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
+#define PORT_ISFR_ISF_SHIFT (0U)
+#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
+
+/*! @name DFER - Digital Filter Enable Register */
+#define PORT_DFER_DFE_MASK (0xFFFFFFFFU)
+#define PORT_DFER_DFE_SHIFT (0U)
+#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
+
+/*! @name DFCR - Digital Filter Clock Register */
+#define PORT_DFCR_CS_MASK (0x1U)
+#define PORT_DFCR_CS_SHIFT (0U)
+#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
+
+/*! @name DFWR - Digital Filter Width Register */
+#define PORT_DFWR_FILT_MASK (0x1FU)
+#define PORT_DFWR_FILT_SHIFT (0U)
+#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA ((PORT_Type *)PORTA_BASE)
+/** Peripheral PORTB base address */
+#define PORTB_BASE (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB ((PORT_Type *)PORTB_BASE)
+/** Peripheral PORTC base address */
+#define PORTC_BASE (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC ((PORT_Type *)PORTC_BASE)
+/** Peripheral PORTD base address */
+#define PORTD_BASE (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD ((PORT_Type *)PORTD_BASE)
+/** Peripheral PORTE base address */
+#define PORTE_BASE (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE ((PORT_Type *)PORTE_BASE)
+/** Array initializer of PORT peripheral base addresses */
+#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
+/** Interrupt vectors for the PORT peripheral type */
+#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+ __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
+ __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t RPFC; /**< Reset Pin Filter Control Register, offset: 0x4 */
+ __IO uint8_t RPFW; /**< Reset Pin Filter Width Register, offset: 0x5 */
+ uint8_t RESERVED_1[1];
+ __I uint8_t MR; /**< Mode Register, offset: 0x7 */
+} RCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/*! @name SRS0 - System Reset Status Register 0 */
+#define RCM_SRS0_WAKEUP_MASK (0x1U)
+#define RCM_SRS0_WAKEUP_SHIFT (0U)
+#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
+#define RCM_SRS0_LVD_MASK (0x2U)
+#define RCM_SRS0_LVD_SHIFT (1U)
+#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
+#define RCM_SRS0_LOC_MASK (0x4U)
+#define RCM_SRS0_LOC_SHIFT (2U)
+#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
+#define RCM_SRS0_LOL_MASK (0x8U)
+#define RCM_SRS0_LOL_SHIFT (3U)
+#define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
+#define RCM_SRS0_WDOG_MASK (0x20U)
+#define RCM_SRS0_WDOG_SHIFT (5U)
+#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
+#define RCM_SRS0_PIN_MASK (0x40U)
+#define RCM_SRS0_PIN_SHIFT (6U)
+#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
+#define RCM_SRS0_POR_MASK (0x80U)
+#define RCM_SRS0_POR_SHIFT (7U)
+#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
+
+/*! @name SRS1 - System Reset Status Register 1 */
+#define RCM_SRS1_JTAG_MASK (0x1U)
+#define RCM_SRS1_JTAG_SHIFT (0U)
+#define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
+#define RCM_SRS1_LOCKUP_MASK (0x2U)
+#define RCM_SRS1_LOCKUP_SHIFT (1U)
+#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
+#define RCM_SRS1_SW_MASK (0x4U)
+#define RCM_SRS1_SW_SHIFT (2U)
+#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
+#define RCM_SRS1_MDM_AP_MASK (0x8U)
+#define RCM_SRS1_MDM_AP_SHIFT (3U)
+#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
+#define RCM_SRS1_EZPT_MASK (0x10U)
+#define RCM_SRS1_EZPT_SHIFT (4U)
+#define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK)
+#define RCM_SRS1_SACKERR_MASK (0x20U)
+#define RCM_SRS1_SACKERR_SHIFT (5U)
+#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
+
+/*! @name RPFC - Reset Pin Filter Control Register */
+#define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
+#define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
+#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK (0x4U)
+#define RCM_RPFC_RSTFLTSS_SHIFT (2U)
+#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
+
+/*! @name RPFW - Reset Pin Filter Width Register */
+#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
+#define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
+#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
+
+/*! @name MR - Mode Register */
+#define RCM_MR_EZP_MS_MASK (0x2U)
+#define RCM_MR_EZP_MS_SHIFT (1U)
+#define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM ((RCM_Type *)RCM_BASE)
+/** Array initializer of RCM peripheral base addresses */
+#define RCM_BASE_ADDRS { RCM_BASE }
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASE_PTRS { RCM }
+
+/*!
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
+ * @{
+ */
+
+/** RFSYS - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
+} RFSYS_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
+ * @{
+ */
+
+/*! @name REG - Register file register */
+#define RFSYS_REG_LL_MASK (0xFFU)
+#define RFSYS_REG_LL_SHIFT (0U)
+#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK (0xFF00U)
+#define RFSYS_REG_LH_SHIFT (8U)
+#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK (0xFF0000U)
+#define RFSYS_REG_HL_SHIFT (16U)
+#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK (0xFF000000U)
+#define RFSYS_REG_HH_SHIFT (24U)
+#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
+
+/* The count of RFSYS_REG */
+#define RFSYS_REG_COUNT (8U)
+
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Masks */
+
+
+/* RFSYS - Peripheral instance base addresses */
+/** Peripheral RFSYS base address */
+#define RFSYS_BASE (0x40041000u)
+/** Peripheral RFSYS base pointer */
+#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
+/** Array initializer of RFSYS peripheral base addresses */
+#define RFSYS_BASE_ADDRS { RFSYS_BASE }
+/** Array initializer of RFSYS peripheral base pointers */
+#define RFSYS_BASE_PTRS { RFSYS }
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
+ * @{
+ */
+
+/** RFVBAT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
+} RFVBAT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
+ * @{
+ */
+
+/*! @name REG - VBAT register file register */
+#define RFVBAT_REG_LL_MASK (0xFFU)
+#define RFVBAT_REG_LL_SHIFT (0U)
+#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LH_MASK (0xFF00U)
+#define RFVBAT_REG_LH_SHIFT (8U)
+#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_HL_MASK (0xFF0000U)
+#define RFVBAT_REG_HL_SHIFT (16U)
+#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HH_MASK (0xFF000000U)
+#define RFVBAT_REG_HH_SHIFT (24U)
+#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
+
+/* The count of RFVBAT_REG */
+#define RFVBAT_REG_COUNT (8U)
+
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Masks */
+
+
+/* RFVBAT - Peripheral instance base addresses */
+/** Peripheral RFVBAT base address */
+#define RFVBAT_BASE (0x4003E000u)
+/** Peripheral RFVBAT base pointer */
+#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
+/** Array initializer of RFVBAT peripheral base addresses */
+#define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
+/** Array initializer of RFVBAT peripheral base pointers */
+#define RFVBAT_BASE_PTRS { RFVBAT }
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
+ __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
+ __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
+ __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
+ __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
+ __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
+ __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
+ __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
+ uint8_t RESERVED_0[2016];
+ __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
+ __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/*! @name TSR - RTC Time Seconds Register */
+#define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
+#define RTC_TSR_TSR_SHIFT (0U)
+#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
+
+/*! @name TPR - RTC Time Prescaler Register */
+#define RTC_TPR_TPR_MASK (0xFFFFU)
+#define RTC_TPR_TPR_SHIFT (0U)
+#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
+
+/*! @name TAR - RTC Time Alarm Register */
+#define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
+#define RTC_TAR_TAR_SHIFT (0U)
+#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
+
+/*! @name TCR - RTC Time Compensation Register */
+#define RTC_TCR_TCR_MASK (0xFFU)
+#define RTC_TCR_TCR_SHIFT (0U)
+#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK (0xFF00U)
+#define RTC_TCR_CIR_SHIFT (8U)
+#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK (0xFF0000U)
+#define RTC_TCR_TCV_SHIFT (16U)
+#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK (0xFF000000U)
+#define RTC_TCR_CIC_SHIFT (24U)
+#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
+
+/*! @name CR - RTC Control Register */
+#define RTC_CR_SWR_MASK (0x1U)
+#define RTC_CR_SWR_SHIFT (0U)
+#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
+#define RTC_CR_WPE_MASK (0x2U)
+#define RTC_CR_WPE_SHIFT (1U)
+#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
+#define RTC_CR_SUP_MASK (0x4U)
+#define RTC_CR_SUP_SHIFT (2U)
+#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
+#define RTC_CR_UM_MASK (0x8U)
+#define RTC_CR_UM_SHIFT (3U)
+#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
+#define RTC_CR_OSCE_MASK (0x100U)
+#define RTC_CR_OSCE_SHIFT (8U)
+#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
+#define RTC_CR_CLKO_MASK (0x200U)
+#define RTC_CR_CLKO_SHIFT (9U)
+#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
+#define RTC_CR_SC16P_MASK (0x400U)
+#define RTC_CR_SC16P_SHIFT (10U)
+#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
+#define RTC_CR_SC8P_MASK (0x800U)
+#define RTC_CR_SC8P_SHIFT (11U)
+#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
+#define RTC_CR_SC4P_MASK (0x1000U)
+#define RTC_CR_SC4P_SHIFT (12U)
+#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
+#define RTC_CR_SC2P_MASK (0x2000U)
+#define RTC_CR_SC2P_SHIFT (13U)
+#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
+
+/*! @name SR - RTC Status Register */
+#define RTC_SR_TIF_MASK (0x1U)
+#define RTC_SR_TIF_SHIFT (0U)
+#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
+#define RTC_SR_TOF_MASK (0x2U)
+#define RTC_SR_TOF_SHIFT (1U)
+#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
+#define RTC_SR_TAF_MASK (0x4U)
+#define RTC_SR_TAF_SHIFT (2U)
+#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
+#define RTC_SR_TCE_MASK (0x10U)
+#define RTC_SR_TCE_SHIFT (4U)
+#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
+
+/*! @name LR - RTC Lock Register */
+#define RTC_LR_TCL_MASK (0x8U)
+#define RTC_LR_TCL_SHIFT (3U)
+#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
+#define RTC_LR_CRL_MASK (0x10U)
+#define RTC_LR_CRL_SHIFT (4U)
+#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
+#define RTC_LR_SRL_MASK (0x20U)
+#define RTC_LR_SRL_SHIFT (5U)
+#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
+#define RTC_LR_LRL_MASK (0x40U)
+#define RTC_LR_LRL_SHIFT (6U)
+#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
+
+/*! @name IER - RTC Interrupt Enable Register */
+#define RTC_IER_TIIE_MASK (0x1U)
+#define RTC_IER_TIIE_SHIFT (0U)
+#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
+#define RTC_IER_TOIE_MASK (0x2U)
+#define RTC_IER_TOIE_SHIFT (1U)
+#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
+#define RTC_IER_TAIE_MASK (0x4U)
+#define RTC_IER_TAIE_SHIFT (2U)
+#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
+#define RTC_IER_TSIE_MASK (0x10U)
+#define RTC_IER_TSIE_SHIFT (4U)
+#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
+
+/*! @name WAR - RTC Write Access Register */
+#define RTC_WAR_TSRW_MASK (0x1U)
+#define RTC_WAR_TSRW_SHIFT (0U)
+#define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
+#define RTC_WAR_TPRW_MASK (0x2U)
+#define RTC_WAR_TPRW_SHIFT (1U)
+#define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
+#define RTC_WAR_TARW_MASK (0x4U)
+#define RTC_WAR_TARW_SHIFT (2U)
+#define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
+#define RTC_WAR_TCRW_MASK (0x8U)
+#define RTC_WAR_TCRW_SHIFT (3U)
+#define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
+#define RTC_WAR_CRW_MASK (0x10U)
+#define RTC_WAR_CRW_SHIFT (4U)
+#define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
+#define RTC_WAR_SRW_MASK (0x20U)
+#define RTC_WAR_SRW_SHIFT (5U)
+#define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
+#define RTC_WAR_LRW_MASK (0x40U)
+#define RTC_WAR_LRW_SHIFT (6U)
+#define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
+#define RTC_WAR_IERW_MASK (0x80U)
+#define RTC_WAR_IERW_SHIFT (7U)
+#define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
+
+/*! @name RAR - RTC Read Access Register */
+#define RTC_RAR_TSRR_MASK (0x1U)
+#define RTC_RAR_TSRR_SHIFT (0U)
+#define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
+#define RTC_RAR_TPRR_MASK (0x2U)
+#define RTC_RAR_TPRR_SHIFT (1U)
+#define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
+#define RTC_RAR_TARR_MASK (0x4U)
+#define RTC_RAR_TARR_SHIFT (2U)
+#define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
+#define RTC_RAR_TCRR_MASK (0x8U)
+#define RTC_RAR_TCRR_SHIFT (3U)
+#define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
+#define RTC_RAR_CRR_MASK (0x10U)
+#define RTC_RAR_CRR_SHIFT (4U)
+#define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
+#define RTC_RAR_SRR_MASK (0x20U)
+#define RTC_RAR_SRR_SHIFT (5U)
+#define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
+#define RTC_RAR_LRR_MASK (0x40U)
+#define RTC_RAR_LRR_SHIFT (6U)
+#define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
+#define RTC_RAR_IERR_MASK (0x80U)
+#define RTC_RAR_IERR_SHIFT (7U)
+#define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS { RTC_IRQn }
+#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
+ __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
+ uint8_t RESERVED_0[4092];
+ __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
+ __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
+ uint8_t RESERVED_3[8];
+ __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
+ uint8_t RESERVED_4[12];
+ __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
+ __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
+ __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
+ __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
+ __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
+ __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
+ __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
+ __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
+ __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
+ __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
+ __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
+ __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
+} SIM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SIM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/*! @name SOPT1 - System Options Register 1 */
+#define SIM_SOPT1_RAMSIZE_MASK (0xF000U)
+#define SIM_SOPT1_RAMSIZE_SHIFT (12U)
+#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
+#define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
+#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK (0x20000000U)
+#define SIM_SOPT1_USBVSTBY_SHIFT (29U)
+#define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
+#define SIM_SOPT1_USBSSTBY_MASK (0x40000000U)
+#define SIM_SOPT1_USBSSTBY_SHIFT (30U)
+#define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
+#define SIM_SOPT1_USBREGEN_MASK (0x80000000U)
+#define SIM_SOPT1_USBREGEN_SHIFT (31U)
+#define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
+
+/*! @name SOPT1CFG - SOPT1 Configuration Register */
+#define SIM_SOPT1CFG_URWE_MASK (0x1000000U)
+#define SIM_SOPT1CFG_URWE_SHIFT (24U)
+#define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
+#define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U)
+#define SIM_SOPT1CFG_UVSWE_SHIFT (25U)
+#define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
+#define SIM_SOPT1CFG_USSWE_MASK (0x4000000U)
+#define SIM_SOPT1CFG_USSWE_SHIFT (26U)
+#define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
+
+/*! @name SOPT2 - System Options Register 2 */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
+#define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
+#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
+#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
+#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_PTD7PAD_MASK (0x800U)
+#define SIM_SOPT2_PTD7PAD_SHIFT (11U)
+#define SIM_SOPT2_PTD7PAD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PTD7PAD_SHIFT)) & SIM_SOPT2_PTD7PAD_MASK)
+#define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U)
+#define SIM_SOPT2_TRACECLKSEL_SHIFT (12U)
+#define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
+#define SIM_SOPT2_PLLFLLSEL_MASK (0x10000U)
+#define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
+#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
+#define SIM_SOPT2_USBSRC_MASK (0x40000U)
+#define SIM_SOPT2_USBSRC_SHIFT (18U)
+#define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
+
+/*! @name SOPT4 - System Options Register 4 */
+#define SIM_SOPT4_FTM0FLT0_MASK (0x1U)
+#define SIM_SOPT4_FTM0FLT0_SHIFT (0U)
+#define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
+#define SIM_SOPT4_FTM0FLT1_MASK (0x2U)
+#define SIM_SOPT4_FTM0FLT1_SHIFT (1U)
+#define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
+#define SIM_SOPT4_FTM1FLT0_MASK (0x10U)
+#define SIM_SOPT4_FTM1FLT0_SHIFT (4U)
+#define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
+#define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U)
+#define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U)
+#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U)
+#define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U)
+#define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
+#define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U)
+#define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U)
+#define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
+#define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U)
+#define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U)
+#define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
+
+/*! @name SOPT5 - System Options Register 5 */
+#define SIM_SOPT5_UART0TXSRC_MASK (0x1U)
+#define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
+#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK (0xCU)
+#define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
+#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_MASK (0x10U)
+#define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
+#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK (0xC0U)
+#define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
+#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
+
+/*! @name SOPT7 - System Options Register 7 */
+#define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
+#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
+#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
+#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
+
+/*! @name SDID - System Device Identification Register */
+#define SIM_SDID_PINID_MASK (0xFU)
+#define SIM_SDID_PINID_SHIFT (0U)
+#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
+#define SIM_SDID_FAMID_MASK (0x70U)
+#define SIM_SDID_FAMID_SHIFT (4U)
+#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
+#define SIM_SDID_REVID_MASK (0xF000U)
+#define SIM_SDID_REVID_SHIFT (12U)
+#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
+
+/*! @name SCGC4 - System Clock Gating Control Register 4 */
+#define SIM_SCGC4_EWM_MASK (0x2U)
+#define SIM_SCGC4_EWM_SHIFT (1U)
+#define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
+#define SIM_SCGC4_CMT_MASK (0x4U)
+#define SIM_SCGC4_CMT_SHIFT (2U)
+#define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
+#define SIM_SCGC4_I2C0_MASK (0x40U)
+#define SIM_SCGC4_I2C0_SHIFT (6U)
+#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
+#define SIM_SCGC4_UART0_MASK (0x400U)
+#define SIM_SCGC4_UART0_SHIFT (10U)
+#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
+#define SIM_SCGC4_UART1_MASK (0x800U)
+#define SIM_SCGC4_UART1_SHIFT (11U)
+#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
+#define SIM_SCGC4_UART2_MASK (0x1000U)
+#define SIM_SCGC4_UART2_SHIFT (12U)
+#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
+#define SIM_SCGC4_USBOTG_MASK (0x40000U)
+#define SIM_SCGC4_USBOTG_SHIFT (18U)
+#define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
+#define SIM_SCGC4_CMP_MASK (0x80000U)
+#define SIM_SCGC4_CMP_SHIFT (19U)
+#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
+#define SIM_SCGC4_VREF_MASK (0x100000U)
+#define SIM_SCGC4_VREF_SHIFT (20U)
+#define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
+
+/*! @name SCGC5 - System Clock Gating Control Register 5 */
+#define SIM_SCGC5_LPTIMER_MASK (0x1U)
+#define SIM_SCGC5_LPTIMER_SHIFT (0U)
+#define SIM_SCGC5_LPTIMER(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTIMER_SHIFT)) & SIM_SCGC5_LPTIMER_MASK)
+#define SIM_SCGC5_TSI_MASK (0x20U)
+#define SIM_SCGC5_TSI_SHIFT (5U)
+#define SIM_SCGC5_TSI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
+#define SIM_SCGC5_PORTA_MASK (0x200U)
+#define SIM_SCGC5_PORTA_SHIFT (9U)
+#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
+#define SIM_SCGC5_PORTB_MASK (0x400U)
+#define SIM_SCGC5_PORTB_SHIFT (10U)
+#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
+#define SIM_SCGC5_PORTC_MASK (0x800U)
+#define SIM_SCGC5_PORTC_SHIFT (11U)
+#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
+#define SIM_SCGC5_PORTD_MASK (0x1000U)
+#define SIM_SCGC5_PORTD_SHIFT (12U)
+#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
+#define SIM_SCGC5_PORTE_MASK (0x2000U)
+#define SIM_SCGC5_PORTE_SHIFT (13U)
+#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
+
+/*! @name SCGC6 - System Clock Gating Control Register 6 */
+#define SIM_SCGC6_FTFL_MASK (0x1U)
+#define SIM_SCGC6_FTFL_SHIFT (0U)
+#define SIM_SCGC6_FTFL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTFL_SHIFT)) & SIM_SCGC6_FTFL_MASK)
+#define SIM_SCGC6_DMAMUX_MASK (0x2U)
+#define SIM_SCGC6_DMAMUX_SHIFT (1U)
+#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
+#define SIM_SCGC6_SPI0_MASK (0x1000U)
+#define SIM_SCGC6_SPI0_SHIFT (12U)
+#define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
+#define SIM_SCGC6_I2S_MASK (0x8000U)
+#define SIM_SCGC6_I2S_SHIFT (15U)
+#define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
+#define SIM_SCGC6_CRC_MASK (0x40000U)
+#define SIM_SCGC6_CRC_SHIFT (18U)
+#define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
+#define SIM_SCGC6_USBDCD_MASK (0x200000U)
+#define SIM_SCGC6_USBDCD_SHIFT (21U)
+#define SIM_SCGC6_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)
+#define SIM_SCGC6_PDB_MASK (0x400000U)
+#define SIM_SCGC6_PDB_SHIFT (22U)
+#define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
+#define SIM_SCGC6_PIT_MASK (0x800000U)
+#define SIM_SCGC6_PIT_SHIFT (23U)
+#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
+#define SIM_SCGC6_FTM0_MASK (0x1000000U)
+#define SIM_SCGC6_FTM0_SHIFT (24U)
+#define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
+#define SIM_SCGC6_FTM1_MASK (0x2000000U)
+#define SIM_SCGC6_FTM1_SHIFT (25U)
+#define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
+#define SIM_SCGC6_ADC0_MASK (0x8000000U)
+#define SIM_SCGC6_ADC0_SHIFT (27U)
+#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
+#define SIM_SCGC6_RTC_MASK (0x20000000U)
+#define SIM_SCGC6_RTC_SHIFT (29U)
+#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
+
+/*! @name SCGC7 - System Clock Gating Control Register 7 */
+#define SIM_SCGC7_DMA_MASK (0x2U)
+#define SIM_SCGC7_DMA_SHIFT (1U)
+#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
+
+/*! @name CLKDIV1 - System Clock Divider Register 1 */
+#define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U)
+#define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
+#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U)
+#define SIM_CLKDIV1_OUTDIV2_SHIFT (24U)
+#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
+#define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
+#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
+
+/*! @name CLKDIV2 - System Clock Divider Register 2 */
+#define SIM_CLKDIV2_USBFRAC_MASK (0x1U)
+#define SIM_CLKDIV2_USBFRAC_SHIFT (0U)
+#define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
+#define SIM_CLKDIV2_USBDIV_MASK (0xEU)
+#define SIM_CLKDIV2_USBDIV_SHIFT (1U)
+#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
+
+/*! @name FCFG1 - Flash Configuration Register 1 */
+#define SIM_FCFG1_FLASHDIS_MASK (0x1U)
+#define SIM_FCFG1_FLASHDIS_SHIFT (0U)
+#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
+#define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
+#define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
+#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
+#define SIM_FCFG1_DEPART_MASK (0xF00U)
+#define SIM_FCFG1_DEPART_SHIFT (8U)
+#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK)
+#define SIM_FCFG1_EESIZE_MASK (0xF0000U)
+#define SIM_FCFG1_EESIZE_SHIFT (16U)
+#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)
+#define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
+#define SIM_FCFG1_PFSIZE_SHIFT (24U)
+#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
+#define SIM_FCFG1_NVMSIZE_MASK (0xF0000000U)
+#define SIM_FCFG1_NVMSIZE_SHIFT (28U)
+#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)
+
+/*! @name FCFG2 - Flash Configuration Register 2 */
+#define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
+#define SIM_FCFG2_MAXADDR1_SHIFT (16U)
+#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_PFLSH_MASK (0x800000U)
+#define SIM_FCFG2_PFLSH_SHIFT (23U)
+#define SIM_FCFG2_PFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)
+#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
+#define SIM_FCFG2_MAXADDR0_SHIFT (24U)
+#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
+
+/*! @name UIDH - Unique Identification Register High */
+#define SIM_UIDH_UID_MASK (0xFFFFFFFFU)
+#define SIM_UIDH_UID_SHIFT (0U)
+#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
+
+/*! @name UIDMH - Unique Identification Register Mid-High */
+#define SIM_UIDMH_UID_MASK (0xFFFFFFFFU)
+#define SIM_UIDMH_UID_SHIFT (0U)
+#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
+
+/*! @name UIDML - Unique Identification Register Mid Low */
+#define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
+#define SIM_UIDML_UID_SHIFT (0U)
+#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
+
+/*! @name UIDL - Unique Identification Register Low */
+#define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
+#define SIM_UIDL_UID_SHIFT (0U)
+#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM ((SIM_Type *)SIM_BASE)
+/** Array initializer of SIM peripheral base addresses */
+#define SIM_BASE_ADDRS { SIM_BASE }
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASE_PTRS { SIM }
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PMPROT; /**< Power Mode Protection Register, offset: 0x0 */
+ __IO uint8_t PMCTRL; /**< Power Mode Control Register, offset: 0x1 */
+ __IO uint8_t VLLSCTRL; /**< VLLS Control Register, offset: 0x2 */
+ __I uint8_t PMSTAT; /**< Power Mode Status Register, offset: 0x3 */
+} SMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/*! @name PMPROT - Power Mode Protection Register */
+#define SMC_PMPROT_AVLLS_MASK (0x2U)
+#define SMC_PMPROT_AVLLS_SHIFT (1U)
+#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
+#define SMC_PMPROT_ALLS_MASK (0x8U)
+#define SMC_PMPROT_ALLS_SHIFT (3U)
+#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
+#define SMC_PMPROT_AVLP_MASK (0x20U)
+#define SMC_PMPROT_AVLP_SHIFT (5U)
+#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
+
+/*! @name PMCTRL - Power Mode Control Register */
+#define SMC_PMCTRL_STOPM_MASK (0x7U)
+#define SMC_PMCTRL_STOPM_SHIFT (0U)
+#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK (0x8U)
+#define SMC_PMCTRL_STOPA_SHIFT (3U)
+#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
+#define SMC_PMCTRL_RUNM_MASK (0x60U)
+#define SMC_PMCTRL_RUNM_SHIFT (5U)
+#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
+#define SMC_PMCTRL_LPWUI_MASK (0x80U)
+#define SMC_PMCTRL_LPWUI_SHIFT (7U)
+#define SMC_PMCTRL_LPWUI(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_LPWUI_SHIFT)) & SMC_PMCTRL_LPWUI_MASK)
+
+/*! @name VLLSCTRL - VLLS Control Register */
+#define SMC_VLLSCTRL_VLLSM_MASK (0x7U)
+#define SMC_VLLSCTRL_VLLSM_SHIFT (0U)
+#define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_VLLSM_SHIFT)) & SMC_VLLSCTRL_VLLSM_MASK)
+#define SMC_VLLSCTRL_PORPO_MASK (0x20U)
+#define SMC_VLLSCTRL_PORPO_SHIFT (5U)
+#define SMC_VLLSCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_PORPO_SHIFT)) & SMC_VLLSCTRL_PORPO_MASK)
+
+/*! @name PMSTAT - Power Mode Status Register */
+#define SMC_PMSTAT_PMSTAT_MASK (0x7FU)
+#define SMC_PMSTAT_PMSTAT_SHIFT (0U)
+#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC ((SMC_Type *)SMC_BASE)
+/** Array initializer of SMC peripheral base addresses */
+#define SMC_BASE_ADDRS { SMC_BASE }
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASE_PTRS { SMC }
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< DSPI Module Configuration Register, offset: 0x0 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t TCR; /**< DSPI Transfer Count Register, offset: 0x8 */
+ union { /* offset: 0xC */
+ __IO uint32_t CTAR[2]; /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
+ __IO uint32_t CTAR_SLAVE[1]; /**< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
+ };
+ uint8_t RESERVED_1[24];
+ __IO uint32_t SR; /**< DSPI Status Register, offset: 0x2C */
+ __IO uint32_t RSER; /**< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
+ union { /* offset: 0x34 */
+ __IO uint32_t PUSHR; /**< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */
+ __IO uint32_t PUSHR_SLAVE; /**< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
+ };
+ __I uint32_t POPR; /**< DSPI POP RX FIFO Register, offset: 0x38 */
+ __I uint32_t TXFR0; /**< DSPI Transmit FIFO Registers, offset: 0x3C */
+ __I uint32_t TXFR1; /**< DSPI Transmit FIFO Registers, offset: 0x40 */
+ __I uint32_t TXFR2; /**< DSPI Transmit FIFO Registers, offset: 0x44 */
+ __I uint32_t TXFR3; /**< DSPI Transmit FIFO Registers, offset: 0x48 */
+ uint8_t RESERVED_2[48];
+ __I uint32_t RXFR0; /**< DSPI Receive FIFO Registers, offset: 0x7C */
+ __I uint32_t RXFR1; /**< DSPI Receive FIFO Registers, offset: 0x80 */
+ __I uint32_t RXFR2; /**< DSPI Receive FIFO Registers, offset: 0x84 */
+ __I uint32_t RXFR3; /**< DSPI Receive FIFO Registers, offset: 0x88 */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/*! @name MCR - DSPI Module Configuration Register */
+#define SPI_MCR_HALT_MASK (0x1U)
+#define SPI_MCR_HALT_SHIFT (0U)
+#define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
+#define SPI_MCR_SMPL_PT_MASK (0x300U)
+#define SPI_MCR_SMPL_PT_SHIFT (8U)
+#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
+#define SPI_MCR_CLR_RXF_MASK (0x400U)
+#define SPI_MCR_CLR_RXF_SHIFT (10U)
+#define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
+#define SPI_MCR_CLR_TXF_MASK (0x800U)
+#define SPI_MCR_CLR_TXF_SHIFT (11U)
+#define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
+#define SPI_MCR_DIS_RXF_MASK (0x1000U)
+#define SPI_MCR_DIS_RXF_SHIFT (12U)
+#define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
+#define SPI_MCR_DIS_TXF_MASK (0x2000U)
+#define SPI_MCR_DIS_TXF_SHIFT (13U)
+#define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
+#define SPI_MCR_MDIS_MASK (0x4000U)
+#define SPI_MCR_MDIS_SHIFT (14U)
+#define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
+#define SPI_MCR_DOZE_MASK (0x8000U)
+#define SPI_MCR_DOZE_SHIFT (15U)
+#define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
+#define SPI_MCR_PCSIS_MASK (0x3F0000U)
+#define SPI_MCR_PCSIS_SHIFT (16U)
+#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
+#define SPI_MCR_ROOE_MASK (0x1000000U)
+#define SPI_MCR_ROOE_SHIFT (24U)
+#define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
+#define SPI_MCR_PCSSE_MASK (0x2000000U)
+#define SPI_MCR_PCSSE_SHIFT (25U)
+#define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
+#define SPI_MCR_MTFE_MASK (0x4000000U)
+#define SPI_MCR_MTFE_SHIFT (26U)
+#define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
+#define SPI_MCR_FRZ_MASK (0x8000000U)
+#define SPI_MCR_FRZ_SHIFT (27U)
+#define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
+#define SPI_MCR_DCONF_MASK (0x30000000U)
+#define SPI_MCR_DCONF_SHIFT (28U)
+#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
+#define SPI_MCR_CONT_SCKE_MASK (0x40000000U)
+#define SPI_MCR_CONT_SCKE_SHIFT (30U)
+#define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
+#define SPI_MCR_MSTR_MASK (0x80000000U)
+#define SPI_MCR_MSTR_SHIFT (31U)
+#define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
+
+/*! @name TCR - DSPI Transfer Count Register */
+#define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U)
+#define SPI_TCR_SPI_TCNT_SHIFT (16U)
+#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
+
+/*! @name CTAR - DSPI Clock and Transfer Attributes Register (In Master Mode) */
+#define SPI_CTAR_BR_MASK (0xFU)
+#define SPI_CTAR_BR_SHIFT (0U)
+#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
+#define SPI_CTAR_DT_MASK (0xF0U)
+#define SPI_CTAR_DT_SHIFT (4U)
+#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
+#define SPI_CTAR_ASC_MASK (0xF00U)
+#define SPI_CTAR_ASC_SHIFT (8U)
+#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
+#define SPI_CTAR_CSSCK_MASK (0xF000U)
+#define SPI_CTAR_CSSCK_SHIFT (12U)
+#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
+#define SPI_CTAR_PBR_MASK (0x30000U)
+#define SPI_CTAR_PBR_SHIFT (16U)
+#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
+#define SPI_CTAR_PDT_MASK (0xC0000U)
+#define SPI_CTAR_PDT_SHIFT (18U)
+#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
+#define SPI_CTAR_PASC_MASK (0x300000U)
+#define SPI_CTAR_PASC_SHIFT (20U)
+#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
+#define SPI_CTAR_PCSSCK_MASK (0xC00000U)
+#define SPI_CTAR_PCSSCK_SHIFT (22U)
+#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
+#define SPI_CTAR_LSBFE_MASK (0x1000000U)
+#define SPI_CTAR_LSBFE_SHIFT (24U)
+#define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
+#define SPI_CTAR_CPHA_MASK (0x2000000U)
+#define SPI_CTAR_CPHA_SHIFT (25U)
+#define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
+#define SPI_CTAR_CPOL_MASK (0x4000000U)
+#define SPI_CTAR_CPOL_SHIFT (26U)
+#define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
+#define SPI_CTAR_FMSZ_MASK (0x78000000U)
+#define SPI_CTAR_FMSZ_SHIFT (27U)
+#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
+#define SPI_CTAR_DBR_MASK (0x80000000U)
+#define SPI_CTAR_DBR_SHIFT (31U)
+#define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
+
+/* The count of SPI_CTAR */
+#define SPI_CTAR_COUNT (2U)
+
+/*! @name CTAR_SLAVE - DSPI Clock and Transfer Attributes Register (In Slave Mode) */
+#define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U)
+#define SPI_CTAR_SLAVE_CPHA_SHIFT (25U)
+#define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
+#define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U)
+#define SPI_CTAR_SLAVE_CPOL_SHIFT (26U)
+#define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
+#define SPI_CTAR_SLAVE_FMSZ_MASK (0xF8000000U)
+#define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U)
+#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
+
+/* The count of SPI_CTAR_SLAVE */
+#define SPI_CTAR_SLAVE_COUNT (1U)
+
+/*! @name SR - DSPI Status Register */
+#define SPI_SR_POPNXTPTR_MASK (0xFU)
+#define SPI_SR_POPNXTPTR_SHIFT (0U)
+#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
+#define SPI_SR_RXCTR_MASK (0xF0U)
+#define SPI_SR_RXCTR_SHIFT (4U)
+#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
+#define SPI_SR_TXNXTPTR_MASK (0xF00U)
+#define SPI_SR_TXNXTPTR_SHIFT (8U)
+#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
+#define SPI_SR_TXCTR_MASK (0xF000U)
+#define SPI_SR_TXCTR_SHIFT (12U)
+#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
+#define SPI_SR_RFDF_MASK (0x20000U)
+#define SPI_SR_RFDF_SHIFT (17U)
+#define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
+#define SPI_SR_RFOF_MASK (0x80000U)
+#define SPI_SR_RFOF_SHIFT (19U)
+#define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
+#define SPI_SR_TFFF_MASK (0x2000000U)
+#define SPI_SR_TFFF_SHIFT (25U)
+#define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
+#define SPI_SR_TFUF_MASK (0x8000000U)
+#define SPI_SR_TFUF_SHIFT (27U)
+#define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
+#define SPI_SR_EOQF_MASK (0x10000000U)
+#define SPI_SR_EOQF_SHIFT (28U)
+#define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
+#define SPI_SR_TXRXS_MASK (0x40000000U)
+#define SPI_SR_TXRXS_SHIFT (30U)
+#define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
+#define SPI_SR_TCF_MASK (0x80000000U)
+#define SPI_SR_TCF_SHIFT (31U)
+#define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
+
+/*! @name RSER - DSPI DMA/Interrupt Request Select and Enable Register */
+#define SPI_RSER_RFDF_DIRS_MASK (0x10000U)
+#define SPI_RSER_RFDF_DIRS_SHIFT (16U)
+#define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
+#define SPI_RSER_RFDF_RE_MASK (0x20000U)
+#define SPI_RSER_RFDF_RE_SHIFT (17U)
+#define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
+#define SPI_RSER_RFOF_RE_MASK (0x80000U)
+#define SPI_RSER_RFOF_RE_SHIFT (19U)
+#define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
+#define SPI_RSER_TFFF_DIRS_MASK (0x1000000U)
+#define SPI_RSER_TFFF_DIRS_SHIFT (24U)
+#define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
+#define SPI_RSER_TFFF_RE_MASK (0x2000000U)
+#define SPI_RSER_TFFF_RE_SHIFT (25U)
+#define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
+#define SPI_RSER_TFUF_RE_MASK (0x8000000U)
+#define SPI_RSER_TFUF_RE_SHIFT (27U)
+#define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
+#define SPI_RSER_EOQF_RE_MASK (0x10000000U)
+#define SPI_RSER_EOQF_RE_SHIFT (28U)
+#define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
+#define SPI_RSER_TCF_RE_MASK (0x80000000U)
+#define SPI_RSER_TCF_RE_SHIFT (31U)
+#define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
+
+/*! @name PUSHR - DSPI PUSH TX FIFO Register In Master Mode */
+#define SPI_PUSHR_TXDATA_MASK (0xFFFFU)
+#define SPI_PUSHR_TXDATA_SHIFT (0U)
+#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
+#define SPI_PUSHR_PCS_MASK (0x3F0000U)
+#define SPI_PUSHR_PCS_SHIFT (16U)
+#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
+#define SPI_PUSHR_CTCNT_MASK (0x4000000U)
+#define SPI_PUSHR_CTCNT_SHIFT (26U)
+#define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
+#define SPI_PUSHR_EOQ_MASK (0x8000000U)
+#define SPI_PUSHR_EOQ_SHIFT (27U)
+#define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
+#define SPI_PUSHR_CTAS_MASK (0x70000000U)
+#define SPI_PUSHR_CTAS_SHIFT (28U)
+#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
+#define SPI_PUSHR_CONT_MASK (0x80000000U)
+#define SPI_PUSHR_CONT_SHIFT (31U)
+#define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
+
+/*! @name PUSHR_SLAVE - DSPI PUSH TX FIFO Register In Slave Mode */
+#define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFFFFFU)
+#define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U)
+#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
+
+/*! @name POPR - DSPI POP RX FIFO Register */
+#define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU)
+#define SPI_POPR_RXDATA_SHIFT (0U)
+#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
+
+/*! @name TXFR0 - DSPI Transmit FIFO Registers */
+#define SPI_TXFR0_TXDATA_MASK (0xFFFFU)
+#define SPI_TXFR0_TXDATA_SHIFT (0U)
+#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
+#define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U)
+#define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U)
+#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
+
+/*! @name TXFR1 - DSPI Transmit FIFO Registers */
+#define SPI_TXFR1_TXDATA_MASK (0xFFFFU)
+#define SPI_TXFR1_TXDATA_SHIFT (0U)
+#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
+#define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U)
+#define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U)
+#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
+
+/*! @name TXFR2 - DSPI Transmit FIFO Registers */
+#define SPI_TXFR2_TXDATA_MASK (0xFFFFU)
+#define SPI_TXFR2_TXDATA_SHIFT (0U)
+#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
+#define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U)
+#define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U)
+#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
+
+/*! @name TXFR3 - DSPI Transmit FIFO Registers */
+#define SPI_TXFR3_TXDATA_MASK (0xFFFFU)
+#define SPI_TXFR3_TXDATA_SHIFT (0U)
+#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
+#define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U)
+#define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U)
+#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
+
+/*! @name RXFR0 - DSPI Receive FIFO Registers */
+#define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU)
+#define SPI_RXFR0_RXDATA_SHIFT (0U)
+#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
+
+/*! @name RXFR1 - DSPI Receive FIFO Registers */
+#define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU)
+#define SPI_RXFR1_RXDATA_SHIFT (0U)
+#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
+
+/*! @name RXFR2 - DSPI Receive FIFO Registers */
+#define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU)
+#define SPI_RXFR2_RXDATA_SHIFT (0U)
+#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
+
+/*! @name RXFR3 - DSPI Receive FIFO Registers */
+#define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU)
+#define SPI_RXFR3_RXDATA_SHIFT (0U)
+#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE (0x4002C000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0 ((SPI_Type *)SPI0_BASE)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS { SPI0_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS { SPI0 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS { SPI0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TSI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
+ * @{
+ */
+
+/** TSI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t GENCS; /**< General Control and Status Register, offset: 0x0 */
+ __IO uint32_t SCANC; /**< SCAN Control Register, offset: 0x4 */
+ __IO uint32_t PEN; /**< Pin Enable Register, offset: 0x8 */
+ __I uint32_t WUCNTR; /**< Wake-Up Channel Counter Register, offset: 0xC */
+ uint8_t RESERVED_0[240];
+ __I uint32_t CNTR1; /**< Counter Register, offset: 0x100 */
+ __I uint32_t CNTR3; /**< Counter Register, offset: 0x104 */
+ __I uint32_t CNTR5; /**< Counter Register, offset: 0x108 */
+ __I uint32_t CNTR7; /**< Counter Register, offset: 0x10C */
+ __I uint32_t CNTR9; /**< Counter Register, offset: 0x110 */
+ __I uint32_t CNTR11; /**< Counter Register, offset: 0x114 */
+ __I uint32_t CNTR13; /**< Counter Register, offset: 0x118 */
+ __I uint32_t CNTR15; /**< Counter Register, offset: 0x11C */
+ __IO uint32_t THRESHOLD; /**< Low Power Channel Threshold Register, offset: 0x120 */
+} TSI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TSI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TSI_Register_Masks TSI Register Masks
+ * @{
+ */
+
+/*! @name GENCS - General Control and Status Register */
+#define TSI_GENCS_STPE_MASK (0x1U)
+#define TSI_GENCS_STPE_SHIFT (0U)
+#define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
+#define TSI_GENCS_STM_MASK (0x2U)
+#define TSI_GENCS_STM_SHIFT (1U)
+#define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
+#define TSI_GENCS_ESOR_MASK (0x10U)
+#define TSI_GENCS_ESOR_SHIFT (4U)
+#define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
+#define TSI_GENCS_ERIE_MASK (0x20U)
+#define TSI_GENCS_ERIE_SHIFT (5U)
+#define TSI_GENCS_ERIE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ERIE_SHIFT)) & TSI_GENCS_ERIE_MASK)
+#define TSI_GENCS_TSIIE_MASK (0x40U)
+#define TSI_GENCS_TSIIE_SHIFT (6U)
+#define TSI_GENCS_TSIIE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIE_SHIFT)) & TSI_GENCS_TSIIE_MASK)
+#define TSI_GENCS_TSIEN_MASK (0x80U)
+#define TSI_GENCS_TSIEN_SHIFT (7U)
+#define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
+#define TSI_GENCS_SWTS_MASK (0x100U)
+#define TSI_GENCS_SWTS_SHIFT (8U)
+#define TSI_GENCS_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SWTS_SHIFT)) & TSI_GENCS_SWTS_MASK)
+#define TSI_GENCS_SCNIP_MASK (0x200U)
+#define TSI_GENCS_SCNIP_SHIFT (9U)
+#define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
+#define TSI_GENCS_OVRF_MASK (0x1000U)
+#define TSI_GENCS_OVRF_SHIFT (12U)
+#define TSI_GENCS_OVRF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OVRF_SHIFT)) & TSI_GENCS_OVRF_MASK)
+#define TSI_GENCS_EXTERF_MASK (0x2000U)
+#define TSI_GENCS_EXTERF_SHIFT (13U)
+#define TSI_GENCS_EXTERF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTERF_SHIFT)) & TSI_GENCS_EXTERF_MASK)
+#define TSI_GENCS_OUTRGF_MASK (0x4000U)
+#define TSI_GENCS_OUTRGF_SHIFT (14U)
+#define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
+#define TSI_GENCS_EOSF_MASK (0x8000U)
+#define TSI_GENCS_EOSF_SHIFT (15U)
+#define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
+#define TSI_GENCS_PS_MASK (0x70000U)
+#define TSI_GENCS_PS_SHIFT (16U)
+#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
+#define TSI_GENCS_NSCN_MASK (0xF80000U)
+#define TSI_GENCS_NSCN_SHIFT (19U)
+#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
+#define TSI_GENCS_LPSCNITV_MASK (0xF000000U)
+#define TSI_GENCS_LPSCNITV_SHIFT (24U)
+#define TSI_GENCS_LPSCNITV(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_LPSCNITV_SHIFT)) & TSI_GENCS_LPSCNITV_MASK)
+#define TSI_GENCS_LPCLKS_MASK (0x10000000U)
+#define TSI_GENCS_LPCLKS_SHIFT (28U)
+#define TSI_GENCS_LPCLKS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_LPCLKS_SHIFT)) & TSI_GENCS_LPCLKS_MASK)
+
+/*! @name SCANC - SCAN Control Register */
+#define TSI_SCANC_AMPSC_MASK (0x7U)
+#define TSI_SCANC_AMPSC_SHIFT (0U)
+#define TSI_SCANC_AMPSC(x) (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_AMPSC_SHIFT)) & TSI_SCANC_AMPSC_MASK)
+#define TSI_SCANC_AMCLKS_MASK (0x18U)
+#define TSI_SCANC_AMCLKS_SHIFT (3U)
+#define TSI_SCANC_AMCLKS(x) (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_AMCLKS_SHIFT)) & TSI_SCANC_AMCLKS_MASK)
+#define TSI_SCANC_SMOD_MASK (0xFF00U)
+#define TSI_SCANC_SMOD_SHIFT (8U)
+#define TSI_SCANC_SMOD(x) (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_SMOD_SHIFT)) & TSI_SCANC_SMOD_MASK)
+#define TSI_SCANC_EXTCHRG_MASK (0xF0000U)
+#define TSI_SCANC_EXTCHRG_SHIFT (16U)
+#define TSI_SCANC_EXTCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_EXTCHRG_SHIFT)) & TSI_SCANC_EXTCHRG_MASK)
+#define TSI_SCANC_REFCHRG_MASK (0xF000000U)
+#define TSI_SCANC_REFCHRG_SHIFT (24U)
+#define TSI_SCANC_REFCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_REFCHRG_SHIFT)) & TSI_SCANC_REFCHRG_MASK)
+
+/*! @name PEN - Pin Enable Register */
+#define TSI_PEN_PEN0_MASK (0x1U)
+#define TSI_PEN_PEN0_SHIFT (0U)
+#define TSI_PEN_PEN0(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN0_SHIFT)) & TSI_PEN_PEN0_MASK)
+#define TSI_PEN_PEN1_MASK (0x2U)
+#define TSI_PEN_PEN1_SHIFT (1U)
+#define TSI_PEN_PEN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN1_SHIFT)) & TSI_PEN_PEN1_MASK)
+#define TSI_PEN_PEN2_MASK (0x4U)
+#define TSI_PEN_PEN2_SHIFT (2U)
+#define TSI_PEN_PEN2(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN2_SHIFT)) & TSI_PEN_PEN2_MASK)
+#define TSI_PEN_PEN3_MASK (0x8U)
+#define TSI_PEN_PEN3_SHIFT (3U)
+#define TSI_PEN_PEN3(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN3_SHIFT)) & TSI_PEN_PEN3_MASK)
+#define TSI_PEN_PEN4_MASK (0x10U)
+#define TSI_PEN_PEN4_SHIFT (4U)
+#define TSI_PEN_PEN4(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN4_SHIFT)) & TSI_PEN_PEN4_MASK)
+#define TSI_PEN_PEN5_MASK (0x20U)
+#define TSI_PEN_PEN5_SHIFT (5U)
+#define TSI_PEN_PEN5(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN5_SHIFT)) & TSI_PEN_PEN5_MASK)
+#define TSI_PEN_PEN6_MASK (0x40U)
+#define TSI_PEN_PEN6_SHIFT (6U)
+#define TSI_PEN_PEN6(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN6_SHIFT)) & TSI_PEN_PEN6_MASK)
+#define TSI_PEN_PEN7_MASK (0x80U)
+#define TSI_PEN_PEN7_SHIFT (7U)
+#define TSI_PEN_PEN7(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN7_SHIFT)) & TSI_PEN_PEN7_MASK)
+#define TSI_PEN_PEN8_MASK (0x100U)
+#define TSI_PEN_PEN8_SHIFT (8U)
+#define TSI_PEN_PEN8(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN8_SHIFT)) & TSI_PEN_PEN8_MASK)
+#define TSI_PEN_PEN9_MASK (0x200U)
+#define TSI_PEN_PEN9_SHIFT (9U)
+#define TSI_PEN_PEN9(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN9_SHIFT)) & TSI_PEN_PEN9_MASK)
+#define TSI_PEN_PEN10_MASK (0x400U)
+#define TSI_PEN_PEN10_SHIFT (10U)
+#define TSI_PEN_PEN10(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN10_SHIFT)) & TSI_PEN_PEN10_MASK)
+#define TSI_PEN_PEN11_MASK (0x800U)
+#define TSI_PEN_PEN11_SHIFT (11U)
+#define TSI_PEN_PEN11(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN11_SHIFT)) & TSI_PEN_PEN11_MASK)
+#define TSI_PEN_PEN12_MASK (0x1000U)
+#define TSI_PEN_PEN12_SHIFT (12U)
+#define TSI_PEN_PEN12(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN12_SHIFT)) & TSI_PEN_PEN12_MASK)
+#define TSI_PEN_PEN13_MASK (0x2000U)
+#define TSI_PEN_PEN13_SHIFT (13U)
+#define TSI_PEN_PEN13(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN13_SHIFT)) & TSI_PEN_PEN13_MASK)
+#define TSI_PEN_PEN14_MASK (0x4000U)
+#define TSI_PEN_PEN14_SHIFT (14U)
+#define TSI_PEN_PEN14(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN14_SHIFT)) & TSI_PEN_PEN14_MASK)
+#define TSI_PEN_PEN15_MASK (0x8000U)
+#define TSI_PEN_PEN15_SHIFT (15U)
+#define TSI_PEN_PEN15(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN15_SHIFT)) & TSI_PEN_PEN15_MASK)
+#define TSI_PEN_LPSP_MASK (0xF0000U)
+#define TSI_PEN_LPSP_SHIFT (16U)
+#define TSI_PEN_LPSP(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_LPSP_SHIFT)) & TSI_PEN_LPSP_MASK)
+
+/*! @name WUCNTR - Wake-Up Channel Counter Register */
+#define TSI_WUCNTR_WUCNT_MASK (0xFFFFU)
+#define TSI_WUCNTR_WUCNT_SHIFT (0U)
+#define TSI_WUCNTR_WUCNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_WUCNTR_WUCNT_SHIFT)) & TSI_WUCNTR_WUCNT_MASK)
+
+/*! @name CNTR1 - Counter Register */
+#define TSI_CNTR1_CTN1_MASK (0xFFFFU)
+#define TSI_CNTR1_CTN1_SHIFT (0U)
+#define TSI_CNTR1_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR1_CTN1_SHIFT)) & TSI_CNTR1_CTN1_MASK)
+#define TSI_CNTR1_CTN_MASK (0xFFFF0000U)
+#define TSI_CNTR1_CTN_SHIFT (16U)
+#define TSI_CNTR1_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR1_CTN_SHIFT)) & TSI_CNTR1_CTN_MASK)
+
+/*! @name CNTR3 - Counter Register */
+#define TSI_CNTR3_CTN1_MASK (0xFFFFU)
+#define TSI_CNTR3_CTN1_SHIFT (0U)
+#define TSI_CNTR3_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR3_CTN1_SHIFT)) & TSI_CNTR3_CTN1_MASK)
+#define TSI_CNTR3_CTN_MASK (0xFFFF0000U)
+#define TSI_CNTR3_CTN_SHIFT (16U)
+#define TSI_CNTR3_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR3_CTN_SHIFT)) & TSI_CNTR3_CTN_MASK)
+
+/*! @name CNTR5 - Counter Register */
+#define TSI_CNTR5_CTN1_MASK (0xFFFFU)
+#define TSI_CNTR5_CTN1_SHIFT (0U)
+#define TSI_CNTR5_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR5_CTN1_SHIFT)) & TSI_CNTR5_CTN1_MASK)
+#define TSI_CNTR5_CTN_MASK (0xFFFF0000U)
+#define TSI_CNTR5_CTN_SHIFT (16U)
+#define TSI_CNTR5_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR5_CTN_SHIFT)) & TSI_CNTR5_CTN_MASK)
+
+/*! @name CNTR7 - Counter Register */
+#define TSI_CNTR7_CTN1_MASK (0xFFFFU)
+#define TSI_CNTR7_CTN1_SHIFT (0U)
+#define TSI_CNTR7_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR7_CTN1_SHIFT)) & TSI_CNTR7_CTN1_MASK)
+#define TSI_CNTR7_CTN_MASK (0xFFFF0000U)
+#define TSI_CNTR7_CTN_SHIFT (16U)
+#define TSI_CNTR7_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR7_CTN_SHIFT)) & TSI_CNTR7_CTN_MASK)
+
+/*! @name CNTR9 - Counter Register */
+#define TSI_CNTR9_CTN1_MASK (0xFFFFU)
+#define TSI_CNTR9_CTN1_SHIFT (0U)
+#define TSI_CNTR9_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR9_CTN1_SHIFT)) & TSI_CNTR9_CTN1_MASK)
+#define TSI_CNTR9_CTN_MASK (0xFFFF0000U)
+#define TSI_CNTR9_CTN_SHIFT (16U)
+#define TSI_CNTR9_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR9_CTN_SHIFT)) & TSI_CNTR9_CTN_MASK)
+
+/*! @name CNTR11 - Counter Register */
+#define TSI_CNTR11_CTN1_MASK (0xFFFFU)
+#define TSI_CNTR11_CTN1_SHIFT (0U)
+#define TSI_CNTR11_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR11_CTN1_SHIFT)) & TSI_CNTR11_CTN1_MASK)
+#define TSI_CNTR11_CTN_MASK (0xFFFF0000U)
+#define TSI_CNTR11_CTN_SHIFT (16U)
+#define TSI_CNTR11_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR11_CTN_SHIFT)) & TSI_CNTR11_CTN_MASK)
+
+/*! @name CNTR13 - Counter Register */
+#define TSI_CNTR13_CTN1_MASK (0xFFFFU)
+#define TSI_CNTR13_CTN1_SHIFT (0U)
+#define TSI_CNTR13_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR13_CTN1_SHIFT)) & TSI_CNTR13_CTN1_MASK)
+#define TSI_CNTR13_CTN_MASK (0xFFFF0000U)
+#define TSI_CNTR13_CTN_SHIFT (16U)
+#define TSI_CNTR13_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR13_CTN_SHIFT)) & TSI_CNTR13_CTN_MASK)
+
+/*! @name CNTR15 - Counter Register */
+#define TSI_CNTR15_CTN1_MASK (0xFFFFU)
+#define TSI_CNTR15_CTN1_SHIFT (0U)
+#define TSI_CNTR15_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR15_CTN1_SHIFT)) & TSI_CNTR15_CTN1_MASK)
+#define TSI_CNTR15_CTN_MASK (0xFFFF0000U)
+#define TSI_CNTR15_CTN_SHIFT (16U)
+#define TSI_CNTR15_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR15_CTN_SHIFT)) & TSI_CNTR15_CTN_MASK)
+
+/*! @name THRESHOLD - Low Power Channel Threshold Register */
+#define TSI_THRESHOLD_HTHH_MASK (0xFFFFU)
+#define TSI_THRESHOLD_HTHH_SHIFT (0U)
+#define TSI_THRESHOLD_HTHH(x) (((uint32_t)(((uint32_t)(x)) << TSI_THRESHOLD_HTHH_SHIFT)) & TSI_THRESHOLD_HTHH_MASK)
+#define TSI_THRESHOLD_LTHH_MASK (0xFFFF0000U)
+#define TSI_THRESHOLD_LTHH_SHIFT (16U)
+#define TSI_THRESHOLD_LTHH(x) (((uint32_t)(((uint32_t)(x)) << TSI_THRESHOLD_LTHH_SHIFT)) & TSI_THRESHOLD_LTHH_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group TSI_Register_Masks */
+
+
+/* TSI - Peripheral instance base addresses */
+/** Peripheral TSI0 base address */
+#define TSI0_BASE (0x40045000u)
+/** Peripheral TSI0 base pointer */
+#define TSI0 ((TSI_Type *)TSI0_BASE)
+/** Array initializer of TSI peripheral base addresses */
+#define TSI_BASE_ADDRS { TSI0_BASE }
+/** Array initializer of TSI peripheral base pointers */
+#define TSI_BASE_PTRS { TSI0 }
+/** Interrupt vectors for the TSI peripheral type */
+#define TSI_IRQS { TSI0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group TSI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Registers:High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
+ __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
+ __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
+ __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
+ __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
+ __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
+ __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
+ __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
+ __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
+ __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
+ __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
+ __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
+ __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
+ __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
+ union { /* offset: 0x1B */
+ __IO uint8_t WP7816T0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+ __IO uint8_t WP7816T1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+ };
+ __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
+ __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
+ __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
+ __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
+ uint8_t RESERVED_2[1];
+ __IO uint8_t C6; /**< UART CEA709.1-B Control Register 6, offset: 0x21 */
+ __IO uint8_t PCTH; /**< UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22 */
+ __IO uint8_t PCTL; /**< UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23 */
+ __IO uint8_t B1T; /**< UART CEA709.1-B Beta1 Timer, offset: 0x24 */
+ __IO uint8_t SDTH; /**< UART CEA709.1-B Secondary Delay Timer High, offset: 0x25 */
+ __IO uint8_t SDTL; /**< UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26 */
+ __IO uint8_t PRE; /**< UART CEA709.1-B Preamble, offset: 0x27 */
+ __IO uint8_t TPL; /**< UART CEA709.1-B Transmit Packet Length, offset: 0x28 */
+ __IO uint8_t IE; /**< UART CEA709.1-B Interrupt Enable Register, offset: 0x29 */
+ __IO uint8_t WB; /**< UART CEA709.1-B WBASE, offset: 0x2A */
+ __IO uint8_t S3; /**< UART CEA709.1-B Status Register, offset: 0x2B */
+ __IO uint8_t S4; /**< UART CEA709.1-B Status Register, offset: 0x2C */
+ __I uint8_t RPL; /**< UART CEA709.1-B Received Packet Length, offset: 0x2D */
+ __I uint8_t RPREL; /**< UART CEA709.1-B Received Preamble Length, offset: 0x2E */
+ __IO uint8_t CPW; /**< UART CEA709.1-B Collision Pulse Width, offset: 0x2F */
+ __IO uint8_t RIDT; /**< UART CEA709.1-B Receive Indeterminate Time, offset: 0x30 */
+ __IO uint8_t TIDT; /**< UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31 */
+} UART_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/*! @name BDH - UART Baud Rate Registers:High */
+#define UART_BDH_SBR_MASK (0x1FU)
+#define UART_BDH_SBR_SHIFT (0U)
+#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
+#define UART_BDH_RXEDGIE_MASK (0x40U)
+#define UART_BDH_RXEDGIE_SHIFT (6U)
+#define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
+#define UART_BDH_LBKDIE_MASK (0x80U)
+#define UART_BDH_LBKDIE_SHIFT (7U)
+#define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
+
+/*! @name BDL - UART Baud Rate Registers: Low */
+#define UART_BDL_SBR_MASK (0xFFU)
+#define UART_BDL_SBR_SHIFT (0U)
+#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
+
+/*! @name C1 - UART Control Register 1 */
+#define UART_C1_PT_MASK (0x1U)
+#define UART_C1_PT_SHIFT (0U)
+#define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
+#define UART_C1_PE_MASK (0x2U)
+#define UART_C1_PE_SHIFT (1U)
+#define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
+#define UART_C1_ILT_MASK (0x4U)
+#define UART_C1_ILT_SHIFT (2U)
+#define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
+#define UART_C1_WAKE_MASK (0x8U)
+#define UART_C1_WAKE_SHIFT (3U)
+#define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
+#define UART_C1_M_MASK (0x10U)
+#define UART_C1_M_SHIFT (4U)
+#define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
+#define UART_C1_RSRC_MASK (0x20U)
+#define UART_C1_RSRC_SHIFT (5U)
+#define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
+#define UART_C1_UARTSWAI_MASK (0x40U)
+#define UART_C1_UARTSWAI_SHIFT (6U)
+#define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
+#define UART_C1_LOOPS_MASK (0x80U)
+#define UART_C1_LOOPS_SHIFT (7U)
+#define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
+
+/*! @name C2 - UART Control Register 2 */
+#define UART_C2_SBK_MASK (0x1U)
+#define UART_C2_SBK_SHIFT (0U)
+#define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
+#define UART_C2_RWU_MASK (0x2U)
+#define UART_C2_RWU_SHIFT (1U)
+#define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
+#define UART_C2_RE_MASK (0x4U)
+#define UART_C2_RE_SHIFT (2U)
+#define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
+#define UART_C2_TE_MASK (0x8U)
+#define UART_C2_TE_SHIFT (3U)
+#define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
+#define UART_C2_ILIE_MASK (0x10U)
+#define UART_C2_ILIE_SHIFT (4U)
+#define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
+#define UART_C2_RIE_MASK (0x20U)
+#define UART_C2_RIE_SHIFT (5U)
+#define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
+#define UART_C2_TCIE_MASK (0x40U)
+#define UART_C2_TCIE_SHIFT (6U)
+#define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
+#define UART_C2_TIE_MASK (0x80U)
+#define UART_C2_TIE_SHIFT (7U)
+#define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
+
+/*! @name S1 - UART Status Register 1 */
+#define UART_S1_PF_MASK (0x1U)
+#define UART_S1_PF_SHIFT (0U)
+#define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
+#define UART_S1_FE_MASK (0x2U)
+#define UART_S1_FE_SHIFT (1U)
+#define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
+#define UART_S1_NF_MASK (0x4U)
+#define UART_S1_NF_SHIFT (2U)
+#define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
+#define UART_S1_OR_MASK (0x8U)
+#define UART_S1_OR_SHIFT (3U)
+#define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
+#define UART_S1_IDLE_MASK (0x10U)
+#define UART_S1_IDLE_SHIFT (4U)
+#define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
+#define UART_S1_RDRF_MASK (0x20U)
+#define UART_S1_RDRF_SHIFT (5U)
+#define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
+#define UART_S1_TC_MASK (0x40U)
+#define UART_S1_TC_SHIFT (6U)
+#define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
+#define UART_S1_TDRE_MASK (0x80U)
+#define UART_S1_TDRE_SHIFT (7U)
+#define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
+
+/*! @name S2 - UART Status Register 2 */
+#define UART_S2_RAF_MASK (0x1U)
+#define UART_S2_RAF_SHIFT (0U)
+#define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
+#define UART_S2_LBKDE_MASK (0x2U)
+#define UART_S2_LBKDE_SHIFT (1U)
+#define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
+#define UART_S2_BRK13_MASK (0x4U)
+#define UART_S2_BRK13_SHIFT (2U)
+#define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
+#define UART_S2_RWUID_MASK (0x8U)
+#define UART_S2_RWUID_SHIFT (3U)
+#define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
+#define UART_S2_RXINV_MASK (0x10U)
+#define UART_S2_RXINV_SHIFT (4U)
+#define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
+#define UART_S2_MSBF_MASK (0x20U)
+#define UART_S2_MSBF_SHIFT (5U)
+#define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK)
+#define UART_S2_RXEDGIF_MASK (0x40U)
+#define UART_S2_RXEDGIF_SHIFT (6U)
+#define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
+#define UART_S2_LBKDIF_MASK (0x80U)
+#define UART_S2_LBKDIF_SHIFT (7U)
+#define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
+
+/*! @name C3 - UART Control Register 3 */
+#define UART_C3_PEIE_MASK (0x1U)
+#define UART_C3_PEIE_SHIFT (0U)
+#define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
+#define UART_C3_FEIE_MASK (0x2U)
+#define UART_C3_FEIE_SHIFT (1U)
+#define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
+#define UART_C3_NEIE_MASK (0x4U)
+#define UART_C3_NEIE_SHIFT (2U)
+#define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
+#define UART_C3_ORIE_MASK (0x8U)
+#define UART_C3_ORIE_SHIFT (3U)
+#define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
+#define UART_C3_TXINV_MASK (0x10U)
+#define UART_C3_TXINV_SHIFT (4U)
+#define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
+#define UART_C3_TXDIR_MASK (0x20U)
+#define UART_C3_TXDIR_SHIFT (5U)
+#define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
+#define UART_C3_T8_MASK (0x40U)
+#define UART_C3_T8_SHIFT (6U)
+#define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
+#define UART_C3_R8_MASK (0x80U)
+#define UART_C3_R8_SHIFT (7U)
+#define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
+
+/*! @name D - UART Data Register */
+#define UART_D_RT_MASK (0xFFU)
+#define UART_D_RT_SHIFT (0U)
+#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK)
+
+/*! @name MA1 - UART Match Address Registers 1 */
+#define UART_MA1_MA_MASK (0xFFU)
+#define UART_MA1_MA_SHIFT (0U)
+#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK)
+
+/*! @name MA2 - UART Match Address Registers 2 */
+#define UART_MA2_MA_MASK (0xFFU)
+#define UART_MA2_MA_SHIFT (0U)
+#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK)
+
+/*! @name C4 - UART Control Register 4 */
+#define UART_C4_BRFA_MASK (0x1FU)
+#define UART_C4_BRFA_SHIFT (0U)
+#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK (0x20U)
+#define UART_C4_M10_SHIFT (5U)
+#define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK)
+#define UART_C4_MAEN2_MASK (0x40U)
+#define UART_C4_MAEN2_SHIFT (6U)
+#define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK)
+#define UART_C4_MAEN1_MASK (0x80U)
+#define UART_C4_MAEN1_SHIFT (7U)
+#define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK)
+
+/*! @name C5 - UART Control Register 5 */
+#define UART_C5_RDMAS_MASK (0x20U)
+#define UART_C5_RDMAS_SHIFT (5U)
+#define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK)
+#define UART_C5_TDMAS_MASK (0x80U)
+#define UART_C5_TDMAS_SHIFT (7U)
+#define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK)
+
+/*! @name ED - UART Extended Data Register */
+#define UART_ED_PARITYE_MASK (0x40U)
+#define UART_ED_PARITYE_SHIFT (6U)
+#define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK)
+#define UART_ED_NOISY_MASK (0x80U)
+#define UART_ED_NOISY_SHIFT (7U)
+#define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK)
+
+/*! @name MODEM - UART Modem Register */
+#define UART_MODEM_TXCTSE_MASK (0x1U)
+#define UART_MODEM_TXCTSE_SHIFT (0U)
+#define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK)
+#define UART_MODEM_TXRTSE_MASK (0x2U)
+#define UART_MODEM_TXRTSE_SHIFT (1U)
+#define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK)
+#define UART_MODEM_TXRTSPOL_MASK (0x4U)
+#define UART_MODEM_TXRTSPOL_SHIFT (2U)
+#define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK)
+#define UART_MODEM_RXRTSE_MASK (0x8U)
+#define UART_MODEM_RXRTSE_SHIFT (3U)
+#define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK)
+
+/*! @name IR - UART Infrared Register */
+#define UART_IR_TNP_MASK (0x3U)
+#define UART_IR_TNP_SHIFT (0U)
+#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK)
+#define UART_IR_IREN_MASK (0x4U)
+#define UART_IR_IREN_SHIFT (2U)
+#define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK)
+
+/*! @name PFIFO - UART FIFO Parameters */
+#define UART_PFIFO_RXFIFOSIZE_MASK (0x7U)
+#define UART_PFIFO_RXFIFOSIZE_SHIFT (0U)
+#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK)
+#define UART_PFIFO_RXFE_MASK (0x8U)
+#define UART_PFIFO_RXFE_SHIFT (3U)
+#define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK)
+#define UART_PFIFO_TXFIFOSIZE_MASK (0x70U)
+#define UART_PFIFO_TXFIFOSIZE_SHIFT (4U)
+#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK)
+#define UART_PFIFO_TXFE_MASK (0x80U)
+#define UART_PFIFO_TXFE_SHIFT (7U)
+#define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK)
+
+/*! @name CFIFO - UART FIFO Control Register */
+#define UART_CFIFO_RXUFE_MASK (0x1U)
+#define UART_CFIFO_RXUFE_SHIFT (0U)
+#define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK)
+#define UART_CFIFO_TXOFE_MASK (0x2U)
+#define UART_CFIFO_TXOFE_SHIFT (1U)
+#define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK)
+#define UART_CFIFO_RXFLUSH_MASK (0x40U)
+#define UART_CFIFO_RXFLUSH_SHIFT (6U)
+#define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK)
+#define UART_CFIFO_TXFLUSH_MASK (0x80U)
+#define UART_CFIFO_TXFLUSH_SHIFT (7U)
+#define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK)
+
+/*! @name SFIFO - UART FIFO Status Register */
+#define UART_SFIFO_RXUF_MASK (0x1U)
+#define UART_SFIFO_RXUF_SHIFT (0U)
+#define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK)
+#define UART_SFIFO_TXOF_MASK (0x2U)
+#define UART_SFIFO_TXOF_SHIFT (1U)
+#define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK)
+#define UART_SFIFO_RXEMPT_MASK (0x40U)
+#define UART_SFIFO_RXEMPT_SHIFT (6U)
+#define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK)
+#define UART_SFIFO_TXEMPT_MASK (0x80U)
+#define UART_SFIFO_TXEMPT_SHIFT (7U)
+#define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK)
+
+/*! @name TWFIFO - UART FIFO Transmit Watermark */
+#define UART_TWFIFO_TXWATER_MASK (0xFFU)
+#define UART_TWFIFO_TXWATER_SHIFT (0U)
+#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK)
+
+/*! @name TCFIFO - UART FIFO Transmit Count */
+#define UART_TCFIFO_TXCOUNT_MASK (0xFFU)
+#define UART_TCFIFO_TXCOUNT_SHIFT (0U)
+#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK)
+
+/*! @name RWFIFO - UART FIFO Receive Watermark */
+#define UART_RWFIFO_RXWATER_MASK (0xFFU)
+#define UART_RWFIFO_RXWATER_SHIFT (0U)
+#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK)
+
+/*! @name RCFIFO - UART FIFO Receive Count */
+#define UART_RCFIFO_RXCOUNT_MASK (0xFFU)
+#define UART_RCFIFO_RXCOUNT_SHIFT (0U)
+#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK)
+
+/*! @name C7816 - UART 7816 Control Register */
+#define UART_C7816_ISO_7816E_MASK (0x1U)
+#define UART_C7816_ISO_7816E_SHIFT (0U)
+#define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK)
+#define UART_C7816_TTYPE_MASK (0x2U)
+#define UART_C7816_TTYPE_SHIFT (1U)
+#define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK)
+#define UART_C7816_INIT_MASK (0x4U)
+#define UART_C7816_INIT_SHIFT (2U)
+#define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK)
+#define UART_C7816_ANACK_MASK (0x8U)
+#define UART_C7816_ANACK_SHIFT (3U)
+#define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK)
+#define UART_C7816_ONACK_MASK (0x10U)
+#define UART_C7816_ONACK_SHIFT (4U)
+#define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK)
+
+/*! @name IE7816 - UART 7816 Interrupt Enable Register */
+#define UART_IE7816_RXTE_MASK (0x1U)
+#define UART_IE7816_RXTE_SHIFT (0U)
+#define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK)
+#define UART_IE7816_TXTE_MASK (0x2U)
+#define UART_IE7816_TXTE_SHIFT (1U)
+#define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK)
+#define UART_IE7816_GTVE_MASK (0x4U)
+#define UART_IE7816_GTVE_SHIFT (2U)
+#define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK)
+#define UART_IE7816_INITDE_MASK (0x10U)
+#define UART_IE7816_INITDE_SHIFT (4U)
+#define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK)
+#define UART_IE7816_BWTE_MASK (0x20U)
+#define UART_IE7816_BWTE_SHIFT (5U)
+#define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK)
+#define UART_IE7816_CWTE_MASK (0x40U)
+#define UART_IE7816_CWTE_SHIFT (6U)
+#define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK)
+#define UART_IE7816_WTE_MASK (0x80U)
+#define UART_IE7816_WTE_SHIFT (7U)
+#define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK)
+
+/*! @name IS7816 - UART 7816 Interrupt Status Register */
+#define UART_IS7816_RXT_MASK (0x1U)
+#define UART_IS7816_RXT_SHIFT (0U)
+#define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK)
+#define UART_IS7816_TXT_MASK (0x2U)
+#define UART_IS7816_TXT_SHIFT (1U)
+#define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK)
+#define UART_IS7816_GTV_MASK (0x4U)
+#define UART_IS7816_GTV_SHIFT (2U)
+#define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK)
+#define UART_IS7816_INITD_MASK (0x10U)
+#define UART_IS7816_INITD_SHIFT (4U)
+#define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK)
+#define UART_IS7816_BWT_MASK (0x20U)
+#define UART_IS7816_BWT_SHIFT (5U)
+#define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK)
+#define UART_IS7816_CWT_MASK (0x40U)
+#define UART_IS7816_CWT_SHIFT (6U)
+#define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK)
+#define UART_IS7816_WT_MASK (0x80U)
+#define UART_IS7816_WT_SHIFT (7U)
+#define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK)
+
+/*! @name WP7816T0 - UART 7816 Wait Parameter Register */
+#define UART_WP7816T0_WI_MASK (0xFFU)
+#define UART_WP7816T0_WI_SHIFT (0U)
+#define UART_WP7816T0_WI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T0_WI_SHIFT)) & UART_WP7816T0_WI_MASK)
+
+/*! @name WP7816T1 - UART 7816 Wait Parameter Register */
+#define UART_WP7816T1_BWI_MASK (0xFU)
+#define UART_WP7816T1_BWI_SHIFT (0U)
+#define UART_WP7816T1_BWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_BWI_SHIFT)) & UART_WP7816T1_BWI_MASK)
+#define UART_WP7816T1_CWI_MASK (0xF0U)
+#define UART_WP7816T1_CWI_SHIFT (4U)
+#define UART_WP7816T1_CWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_CWI_SHIFT)) & UART_WP7816T1_CWI_MASK)
+
+/*! @name WN7816 - UART 7816 Wait N Register */
+#define UART_WN7816_GTN_MASK (0xFFU)
+#define UART_WN7816_GTN_SHIFT (0U)
+#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
+
+/*! @name WF7816 - UART 7816 Wait FD Register */
+#define UART_WF7816_GTFD_MASK (0xFFU)
+#define UART_WF7816_GTFD_SHIFT (0U)
+#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
+
+/*! @name ET7816 - UART 7816 Error Threshold Register */
+#define UART_ET7816_RXTHRESHOLD_MASK (0xFU)
+#define UART_ET7816_RXTHRESHOLD_SHIFT (0U)
+#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK (0xF0U)
+#define UART_ET7816_TXTHRESHOLD_SHIFT (4U)
+#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
+
+/*! @name TL7816 - UART 7816 Transmit Length Register */
+#define UART_TL7816_TLEN_MASK (0xFFU)
+#define UART_TL7816_TLEN_SHIFT (0U)
+#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
+
+/*! @name C6 - UART CEA709.1-B Control Register 6 */
+#define UART_C6_CP_MASK (0x10U)
+#define UART_C6_CP_SHIFT (4U)
+#define UART_C6_CP(x) (((uint8_t)(((uint8_t)(x)) << UART_C6_CP_SHIFT)) & UART_C6_CP_MASK)
+#define UART_C6_CE_MASK (0x20U)
+#define UART_C6_CE_SHIFT (5U)
+#define UART_C6_CE(x) (((uint8_t)(((uint8_t)(x)) << UART_C6_CE_SHIFT)) & UART_C6_CE_MASK)
+#define UART_C6_TX709_MASK (0x40U)
+#define UART_C6_TX709_SHIFT (6U)
+#define UART_C6_TX709(x) (((uint8_t)(((uint8_t)(x)) << UART_C6_TX709_SHIFT)) & UART_C6_TX709_MASK)
+#define UART_C6_EN709_MASK (0x80U)
+#define UART_C6_EN709_SHIFT (7U)
+#define UART_C6_EN709(x) (((uint8_t)(((uint8_t)(x)) << UART_C6_EN709_SHIFT)) & UART_C6_EN709_MASK)
+
+/*! @name PCTH - UART CEA709.1-B Packet Cycle Time Counter High */
+#define UART_PCTH_PCTH_MASK (0xFFU)
+#define UART_PCTH_PCTH_SHIFT (0U)
+#define UART_PCTH_PCTH(x) (((uint8_t)(((uint8_t)(x)) << UART_PCTH_PCTH_SHIFT)) & UART_PCTH_PCTH_MASK)
+
+/*! @name PCTL - UART CEA709.1-B Packet Cycle Time Counter Low */
+#define UART_PCTL_PCTL_MASK (0xFFU)
+#define UART_PCTL_PCTL_SHIFT (0U)
+#define UART_PCTL_PCTL(x) (((uint8_t)(((uint8_t)(x)) << UART_PCTL_PCTL_SHIFT)) & UART_PCTL_PCTL_MASK)
+
+/*! @name B1T - UART CEA709.1-B Beta1 Timer */
+#define UART_B1T_B1T_MASK (0xFFU)
+#define UART_B1T_B1T_SHIFT (0U)
+#define UART_B1T_B1T(x) (((uint8_t)(((uint8_t)(x)) << UART_B1T_B1T_SHIFT)) & UART_B1T_B1T_MASK)
+
+/*! @name SDTH - UART CEA709.1-B Secondary Delay Timer High */
+#define UART_SDTH_SDTH_MASK (0xFFU)
+#define UART_SDTH_SDTH_SHIFT (0U)
+#define UART_SDTH_SDTH(x) (((uint8_t)(((uint8_t)(x)) << UART_SDTH_SDTH_SHIFT)) & UART_SDTH_SDTH_MASK)
+
+/*! @name SDTL - UART CEA709.1-B Secondary Delay Timer Low */
+#define UART_SDTL_SDTL_MASK (0xFFU)
+#define UART_SDTL_SDTL_SHIFT (0U)
+#define UART_SDTL_SDTL(x) (((uint8_t)(((uint8_t)(x)) << UART_SDTL_SDTL_SHIFT)) & UART_SDTL_SDTL_MASK)
+
+/*! @name PRE - UART CEA709.1-B Preamble */
+#define UART_PRE_PREAMBLE_MASK (0xFFU)
+#define UART_PRE_PREAMBLE_SHIFT (0U)
+#define UART_PRE_PREAMBLE(x) (((uint8_t)(((uint8_t)(x)) << UART_PRE_PREAMBLE_SHIFT)) & UART_PRE_PREAMBLE_MASK)
+
+/*! @name TPL - UART CEA709.1-B Transmit Packet Length */
+#define UART_TPL_TPL_MASK (0xFFU)
+#define UART_TPL_TPL_SHIFT (0U)
+#define UART_TPL_TPL(x) (((uint8_t)(((uint8_t)(x)) << UART_TPL_TPL_SHIFT)) & UART_TPL_TPL_MASK)
+
+/*! @name IE - UART CEA709.1-B Interrupt Enable Register */
+#define UART_IE_TXFIE_MASK (0x1U)
+#define UART_IE_TXFIE_SHIFT (0U)
+#define UART_IE_TXFIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_TXFIE_SHIFT)) & UART_IE_TXFIE_MASK)
+#define UART_IE_PSIE_MASK (0x2U)
+#define UART_IE_PSIE_SHIFT (1U)
+#define UART_IE_PSIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_PSIE_SHIFT)) & UART_IE_PSIE_MASK)
+#define UART_IE_PCTEIE_MASK (0x4U)
+#define UART_IE_PCTEIE_SHIFT (2U)
+#define UART_IE_PCTEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_PCTEIE_SHIFT)) & UART_IE_PCTEIE_MASK)
+#define UART_IE_PTXIE_MASK (0x8U)
+#define UART_IE_PTXIE_SHIFT (3U)
+#define UART_IE_PTXIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_PTXIE_SHIFT)) & UART_IE_PTXIE_MASK)
+#define UART_IE_PRXIE_MASK (0x10U)
+#define UART_IE_PRXIE_SHIFT (4U)
+#define UART_IE_PRXIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_PRXIE_SHIFT)) & UART_IE_PRXIE_MASK)
+#define UART_IE_ISDIE_MASK (0x20U)
+#define UART_IE_ISDIE_SHIFT (5U)
+#define UART_IE_ISDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_ISDIE_SHIFT)) & UART_IE_ISDIE_MASK)
+#define UART_IE_WBEIE_MASK (0x40U)
+#define UART_IE_WBEIE_SHIFT (6U)
+#define UART_IE_WBEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_WBEIE_SHIFT)) & UART_IE_WBEIE_MASK)
+
+/*! @name WB - UART CEA709.1-B WBASE */
+#define UART_WB_WBASE_MASK (0xFFU)
+#define UART_WB_WBASE_SHIFT (0U)
+#define UART_WB_WBASE(x) (((uint8_t)(((uint8_t)(x)) << UART_WB_WBASE_SHIFT)) & UART_WB_WBASE_MASK)
+
+/*! @name S3 - UART CEA709.1-B Status Register */
+#define UART_S3_TXFF_MASK (0x1U)
+#define UART_S3_TXFF_SHIFT (0U)
+#define UART_S3_TXFF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_TXFF_SHIFT)) & UART_S3_TXFF_MASK)
+#define UART_S3_PSF_MASK (0x2U)
+#define UART_S3_PSF_SHIFT (1U)
+#define UART_S3_PSF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_PSF_SHIFT)) & UART_S3_PSF_MASK)
+#define UART_S3_PCTEF_MASK (0x4U)
+#define UART_S3_PCTEF_SHIFT (2U)
+#define UART_S3_PCTEF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_PCTEF_SHIFT)) & UART_S3_PCTEF_MASK)
+#define UART_S3_PTXF_MASK (0x8U)
+#define UART_S3_PTXF_SHIFT (3U)
+#define UART_S3_PTXF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_PTXF_SHIFT)) & UART_S3_PTXF_MASK)
+#define UART_S3_PRXF_MASK (0x10U)
+#define UART_S3_PRXF_SHIFT (4U)
+#define UART_S3_PRXF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_PRXF_SHIFT)) & UART_S3_PRXF_MASK)
+#define UART_S3_ISD_MASK (0x20U)
+#define UART_S3_ISD_SHIFT (5U)
+#define UART_S3_ISD(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_ISD_SHIFT)) & UART_S3_ISD_MASK)
+#define UART_S3_WBEF_MASK (0x40U)
+#define UART_S3_WBEF_SHIFT (6U)
+#define UART_S3_WBEF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_WBEF_SHIFT)) & UART_S3_WBEF_MASK)
+#define UART_S3_PEF_MASK (0x80U)
+#define UART_S3_PEF_SHIFT (7U)
+#define UART_S3_PEF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_PEF_SHIFT)) & UART_S3_PEF_MASK)
+
+/*! @name S4 - UART CEA709.1-B Status Register */
+#define UART_S4_FE_MASK (0x1U)
+#define UART_S4_FE_SHIFT (0U)
+#define UART_S4_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S4_FE_SHIFT)) & UART_S4_FE_MASK)
+#define UART_S4_ILCV_MASK (0x2U)
+#define UART_S4_ILCV_SHIFT (1U)
+#define UART_S4_ILCV(x) (((uint8_t)(((uint8_t)(x)) << UART_S4_ILCV_SHIFT)) & UART_S4_ILCV_MASK)
+#define UART_S4_CDET_MASK (0xCU)
+#define UART_S4_CDET_SHIFT (2U)
+#define UART_S4_CDET(x) (((uint8_t)(((uint8_t)(x)) << UART_S4_CDET_SHIFT)) & UART_S4_CDET_MASK)
+#define UART_S4_INITF_MASK (0x10U)
+#define UART_S4_INITF_SHIFT (4U)
+#define UART_S4_INITF(x) (((uint8_t)(((uint8_t)(x)) << UART_S4_INITF_SHIFT)) & UART_S4_INITF_MASK)
+
+/*! @name RPL - UART CEA709.1-B Received Packet Length */
+#define UART_RPL_RPL_MASK (0xFFU)
+#define UART_RPL_RPL_SHIFT (0U)
+#define UART_RPL_RPL(x) (((uint8_t)(((uint8_t)(x)) << UART_RPL_RPL_SHIFT)) & UART_RPL_RPL_MASK)
+
+/*! @name RPREL - UART CEA709.1-B Received Preamble Length */
+#define UART_RPREL_RPREL_MASK (0xFFU)
+#define UART_RPREL_RPREL_SHIFT (0U)
+#define UART_RPREL_RPREL(x) (((uint8_t)(((uint8_t)(x)) << UART_RPREL_RPREL_SHIFT)) & UART_RPREL_RPREL_MASK)
+
+/*! @name CPW - UART CEA709.1-B Collision Pulse Width */
+#define UART_CPW_CPW_MASK (0xFFU)
+#define UART_CPW_CPW_SHIFT (0U)
+#define UART_CPW_CPW(x) (((uint8_t)(((uint8_t)(x)) << UART_CPW_CPW_SHIFT)) & UART_CPW_CPW_MASK)
+
+/*! @name RIDT - UART CEA709.1-B Receive Indeterminate Time */
+#define UART_RIDT_RIDT_MASK (0xFFU)
+#define UART_RIDT_RIDT_SHIFT (0U)
+#define UART_RIDT_RIDT(x) (((uint8_t)(((uint8_t)(x)) << UART_RIDT_RIDT_SHIFT)) & UART_RIDT_RIDT_MASK)
+
+/*! @name TIDT - UART CEA709.1-B Transmit Indeterminate Time */
+#define UART_TIDT_TIDT_MASK (0xFFU)
+#define UART_TIDT_TIDT_SHIFT (0U)
+#define UART_TIDT_TIDT(x) (((uint8_t)(((uint8_t)(x)) << UART_TIDT_TIDT_SHIFT)) & UART_TIDT_TIDT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0 ((UART_Type *)UART0_BASE)
+/** Peripheral UART1 base address */
+#define UART1_BASE (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1 ((UART_Type *)UART1_BASE)
+/** Peripheral UART2 base address */
+#define UART2_BASE (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2 ((UART_Type *)UART2_BASE)
+/** Array initializer of UART peripheral base addresses */
+#define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE }
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASE_PTRS { UART0, UART1, UART2 }
+/** Interrupt vectors for the UART peripheral type */
+#define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn }
+#define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn }
+#define UART_LON_IRQS { UART0_LON_IRQn, NotAvail_IRQn, NotAvail_IRQn }
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+ __I uint8_t PERID; /**< Peripheral ID Register, offset: 0x0 */
+ uint8_t RESERVED_0[3];
+ __I uint8_t IDCOMP; /**< Peripheral ID Complement Register, offset: 0x4 */
+ uint8_t RESERVED_1[3];
+ __I uint8_t REV; /**< Peripheral Revision Register, offset: 0x8 */
+ uint8_t RESERVED_2[3];
+ __I uint8_t ADDINFO; /**< Peripheral Additional Info Register, offset: 0xC */
+ uint8_t RESERVED_3[3];
+ __IO uint8_t OTGISTAT; /**< OTG Interrupt Status Register, offset: 0x10 */
+ uint8_t RESERVED_4[3];
+ __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
+ uint8_t RESERVED_5[3];
+ __IO uint8_t OTGSTAT; /**< OTG Status Register, offset: 0x18 */
+ uint8_t RESERVED_6[3];
+ __IO uint8_t OTGCTL; /**< OTG Control Register, offset: 0x1C */
+ uint8_t RESERVED_7[99];
+ __IO uint8_t ISTAT; /**< Interrupt Status Register, offset: 0x80 */
+ uint8_t RESERVED_8[3];
+ __IO uint8_t INTEN; /**< Interrupt Enable Register, offset: 0x84 */
+ uint8_t RESERVED_9[3];
+ __IO uint8_t ERRSTAT; /**< Error Interrupt Status Register, offset: 0x88 */
+ uint8_t RESERVED_10[3];
+ __IO uint8_t ERREN; /**< Error Interrupt Enable Register, offset: 0x8C */
+ uint8_t RESERVED_11[3];
+ __I uint8_t STAT; /**< Status Register, offset: 0x90 */
+ uint8_t RESERVED_12[3];
+ __IO uint8_t CTL; /**< Control Register, offset: 0x94 */
+ uint8_t RESERVED_13[3];
+ __IO uint8_t ADDR; /**< Address Register, offset: 0x98 */
+ uint8_t RESERVED_14[3];
+ __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
+ uint8_t RESERVED_15[3];
+ __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
+ uint8_t RESERVED_16[3];
+ __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
+ uint8_t RESERVED_17[3];
+ __IO uint8_t TOKEN; /**< Token Register, offset: 0xA8 */
+ uint8_t RESERVED_18[3];
+ __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
+ uint8_t RESERVED_19[3];
+ __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
+ uint8_t RESERVED_20[3];
+ __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
+ uint8_t RESERVED_21[11];
+ struct { /* offset: 0xC0, array step: 0x4 */
+ __IO uint8_t ENDPT; /**< Endpoint Control Register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_0[3];
+ } ENDPOINT[16];
+ __IO uint8_t USBCTRL; /**< USB Control Register, offset: 0x100 */
+ uint8_t RESERVED_22[3];
+ __I uint8_t OBSERVE; /**< USB OTG Observe Register, offset: 0x104 */
+ uint8_t RESERVED_23[3];
+ __IO uint8_t CONTROL; /**< USB OTG Control Register, offset: 0x108 */
+ uint8_t RESERVED_24[3];
+ __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
+ uint8_t RESERVED_25[7];
+ __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
+} USB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/*! @name PERID - Peripheral ID Register */
+#define USB_PERID_ID_MASK (0x3FU)
+#define USB_PERID_ID_SHIFT (0U)
+#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
+
+/*! @name IDCOMP - Peripheral ID Complement Register */
+#define USB_IDCOMP_NID_MASK (0x3FU)
+#define USB_IDCOMP_NID_SHIFT (0U)
+#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
+
+/*! @name REV - Peripheral Revision Register */
+#define USB_REV_REV_MASK (0xFFU)
+#define USB_REV_REV_SHIFT (0U)
+#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
+
+/*! @name ADDINFO - Peripheral Additional Info Register */
+#define USB_ADDINFO_IEHOST_MASK (0x1U)
+#define USB_ADDINFO_IEHOST_SHIFT (0U)
+#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
+#define USB_ADDINFO_IRQNUM_MASK (0xF8U)
+#define USB_ADDINFO_IRQNUM_SHIFT (3U)
+#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IRQNUM_SHIFT)) & USB_ADDINFO_IRQNUM_MASK)
+
+/*! @name OTGISTAT - OTG Interrupt Status Register */
+#define USB_OTGISTAT_AVBUSCHG_MASK (0x1U)
+#define USB_OTGISTAT_AVBUSCHG_SHIFT (0U)
+#define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK)
+#define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U)
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U)
+#define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK)
+#define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U)
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U)
+#define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK)
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
+#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
+#define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
+#define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
+#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
+#define USB_OTGISTAT_IDCHG_MASK (0x80U)
+#define USB_OTGISTAT_IDCHG_SHIFT (7U)
+#define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK)
+
+/*! @name OTGICR - OTG Interrupt Control Register */
+#define USB_OTGICR_AVBUSEN_MASK (0x1U)
+#define USB_OTGICR_AVBUSEN_SHIFT (0U)
+#define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK)
+#define USB_OTGICR_BSESSEN_MASK (0x4U)
+#define USB_OTGICR_BSESSEN_SHIFT (2U)
+#define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK)
+#define USB_OTGICR_SESSVLDEN_MASK (0x8U)
+#define USB_OTGICR_SESSVLDEN_SHIFT (3U)
+#define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK)
+#define USB_OTGICR_LINESTATEEN_MASK (0x20U)
+#define USB_OTGICR_LINESTATEEN_SHIFT (5U)
+#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
+#define USB_OTGICR_ONEMSECEN_MASK (0x40U)
+#define USB_OTGICR_ONEMSECEN_SHIFT (6U)
+#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
+#define USB_OTGICR_IDEN_MASK (0x80U)
+#define USB_OTGICR_IDEN_SHIFT (7U)
+#define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK)
+
+/*! @name OTGSTAT - OTG Status Register */
+#define USB_OTGSTAT_AVBUSVLD_MASK (0x1U)
+#define USB_OTGSTAT_AVBUSVLD_SHIFT (0U)
+#define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK)
+#define USB_OTGSTAT_BSESSEND_MASK (0x4U)
+#define USB_OTGSTAT_BSESSEND_SHIFT (2U)
+#define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK)
+#define USB_OTGSTAT_SESS_VLD_MASK (0x8U)
+#define USB_OTGSTAT_SESS_VLD_SHIFT (3U)
+#define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK)
+#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
+#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
+#define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
+#define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
+#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
+#define USB_OTGSTAT_ID_MASK (0x80U)
+#define USB_OTGSTAT_ID_SHIFT (7U)
+#define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK)
+
+/*! @name OTGCTL - OTG Control Register */
+#define USB_OTGCTL_OTGEN_MASK (0x4U)
+#define USB_OTGCTL_OTGEN_SHIFT (2U)
+#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
+#define USB_OTGCTL_DMLOW_MASK (0x10U)
+#define USB_OTGCTL_DMLOW_SHIFT (4U)
+#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
+#define USB_OTGCTL_DPLOW_MASK (0x20U)
+#define USB_OTGCTL_DPLOW_SHIFT (5U)
+#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
+#define USB_OTGCTL_DPHIGH_MASK (0x80U)
+#define USB_OTGCTL_DPHIGH_SHIFT (7U)
+#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
+
+/*! @name ISTAT - Interrupt Status Register */
+#define USB_ISTAT_USBRST_MASK (0x1U)
+#define USB_ISTAT_USBRST_SHIFT (0U)
+#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
+#define USB_ISTAT_ERROR_MASK (0x2U)
+#define USB_ISTAT_ERROR_SHIFT (1U)
+#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
+#define USB_ISTAT_SOFTOK_MASK (0x4U)
+#define USB_ISTAT_SOFTOK_SHIFT (2U)
+#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
+#define USB_ISTAT_TOKDNE_MASK (0x8U)
+#define USB_ISTAT_TOKDNE_SHIFT (3U)
+#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
+#define USB_ISTAT_SLEEP_MASK (0x10U)
+#define USB_ISTAT_SLEEP_SHIFT (4U)
+#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
+#define USB_ISTAT_RESUME_MASK (0x20U)
+#define USB_ISTAT_RESUME_SHIFT (5U)
+#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
+#define USB_ISTAT_ATTACH_MASK (0x40U)
+#define USB_ISTAT_ATTACH_SHIFT (6U)
+#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
+#define USB_ISTAT_STALL_MASK (0x80U)
+#define USB_ISTAT_STALL_SHIFT (7U)
+#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
+
+/*! @name INTEN - Interrupt Enable Register */
+#define USB_INTEN_USBRSTEN_MASK (0x1U)
+#define USB_INTEN_USBRSTEN_SHIFT (0U)
+#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
+#define USB_INTEN_ERROREN_MASK (0x2U)
+#define USB_INTEN_ERROREN_SHIFT (1U)
+#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
+#define USB_INTEN_SOFTOKEN_MASK (0x4U)
+#define USB_INTEN_SOFTOKEN_SHIFT (2U)
+#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
+#define USB_INTEN_TOKDNEEN_MASK (0x8U)
+#define USB_INTEN_TOKDNEEN_SHIFT (3U)
+#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
+#define USB_INTEN_SLEEPEN_MASK (0x10U)
+#define USB_INTEN_SLEEPEN_SHIFT (4U)
+#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
+#define USB_INTEN_RESUMEEN_MASK (0x20U)
+#define USB_INTEN_RESUMEEN_SHIFT (5U)
+#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
+#define USB_INTEN_ATTACHEN_MASK (0x40U)
+#define USB_INTEN_ATTACHEN_SHIFT (6U)
+#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
+#define USB_INTEN_STALLEN_MASK (0x80U)
+#define USB_INTEN_STALLEN_SHIFT (7U)
+#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
+
+/*! @name ERRSTAT - Error Interrupt Status Register */
+#define USB_ERRSTAT_PIDERR_MASK (0x1U)
+#define USB_ERRSTAT_PIDERR_SHIFT (0U)
+#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
+#define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
+#define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
+#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
+#define USB_ERRSTAT_CRC16_MASK (0x4U)
+#define USB_ERRSTAT_CRC16_SHIFT (2U)
+#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
+#define USB_ERRSTAT_DFN8_MASK (0x8U)
+#define USB_ERRSTAT_DFN8_SHIFT (3U)
+#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
+#define USB_ERRSTAT_BTOERR_MASK (0x10U)
+#define USB_ERRSTAT_BTOERR_SHIFT (4U)
+#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
+#define USB_ERRSTAT_DMAERR_MASK (0x20U)
+#define USB_ERRSTAT_DMAERR_SHIFT (5U)
+#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
+#define USB_ERRSTAT_BTSERR_MASK (0x80U)
+#define USB_ERRSTAT_BTSERR_SHIFT (7U)
+#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
+
+/*! @name ERREN - Error Interrupt Enable Register */
+#define USB_ERREN_PIDERREN_MASK (0x1U)
+#define USB_ERREN_PIDERREN_SHIFT (0U)
+#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
+#define USB_ERREN_CRC5EOFEN_MASK (0x2U)
+#define USB_ERREN_CRC5EOFEN_SHIFT (1U)
+#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
+#define USB_ERREN_CRC16EN_MASK (0x4U)
+#define USB_ERREN_CRC16EN_SHIFT (2U)
+#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
+#define USB_ERREN_DFN8EN_MASK (0x8U)
+#define USB_ERREN_DFN8EN_SHIFT (3U)
+#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
+#define USB_ERREN_BTOERREN_MASK (0x10U)
+#define USB_ERREN_BTOERREN_SHIFT (4U)
+#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
+#define USB_ERREN_DMAERREN_MASK (0x20U)
+#define USB_ERREN_DMAERREN_SHIFT (5U)
+#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
+#define USB_ERREN_BTSERREN_MASK (0x80U)
+#define USB_ERREN_BTSERREN_SHIFT (7U)
+#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
+
+/*! @name STAT - Status Register */
+#define USB_STAT_ODD_MASK (0x4U)
+#define USB_STAT_ODD_SHIFT (2U)
+#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
+#define USB_STAT_TX_MASK (0x8U)
+#define USB_STAT_TX_SHIFT (3U)
+#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
+#define USB_STAT_ENDP_MASK (0xF0U)
+#define USB_STAT_ENDP_SHIFT (4U)
+#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
+
+/*! @name CTL - Control Register */
+#define USB_CTL_USBENSOFEN_MASK (0x1U)
+#define USB_CTL_USBENSOFEN_SHIFT (0U)
+#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
+#define USB_CTL_ODDRST_MASK (0x2U)
+#define USB_CTL_ODDRST_SHIFT (1U)
+#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
+#define USB_CTL_RESUME_MASK (0x4U)
+#define USB_CTL_RESUME_SHIFT (2U)
+#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
+#define USB_CTL_HOSTMODEEN_MASK (0x8U)
+#define USB_CTL_HOSTMODEEN_SHIFT (3U)
+#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
+#define USB_CTL_RESET_MASK (0x10U)
+#define USB_CTL_RESET_SHIFT (4U)
+#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
+#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
+#define USB_CTL_SE0_MASK (0x40U)
+#define USB_CTL_SE0_SHIFT (6U)
+#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
+#define USB_CTL_JSTATE_MASK (0x80U)
+#define USB_CTL_JSTATE_SHIFT (7U)
+#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
+
+/*! @name ADDR - Address Register */
+#define USB_ADDR_ADDR_MASK (0x7FU)
+#define USB_ADDR_ADDR_SHIFT (0U)
+#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK (0x80U)
+#define USB_ADDR_LSEN_SHIFT (7U)
+#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
+
+/*! @name BDTPAGE1 - BDT Page Register 1 */
+#define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
+#define USB_BDTPAGE1_BDTBA_SHIFT (1U)
+#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
+
+/*! @name FRMNUML - Frame Number Register Low */
+#define USB_FRMNUML_FRM_MASK (0xFFU)
+#define USB_FRMNUML_FRM_SHIFT (0U)
+#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
+
+/*! @name FRMNUMH - Frame Number Register High */
+#define USB_FRMNUMH_FRM_MASK (0x7U)
+#define USB_FRMNUMH_FRM_SHIFT (0U)
+#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
+
+/*! @name TOKEN - Token Register */
+#define USB_TOKEN_TOKENENDPT_MASK (0xFU)
+#define USB_TOKEN_TOKENENDPT_SHIFT (0U)
+#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK (0xF0U)
+#define USB_TOKEN_TOKENPID_SHIFT (4U)
+#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
+
+/*! @name SOFTHLD - SOF Threshold Register */
+#define USB_SOFTHLD_CNT_MASK (0xFFU)
+#define USB_SOFTHLD_CNT_SHIFT (0U)
+#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
+
+/*! @name BDTPAGE2 - BDT Page Register 2 */
+#define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
+#define USB_BDTPAGE2_BDTBA_SHIFT (0U)
+#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
+
+/*! @name BDTPAGE3 - BDT Page Register 3 */
+#define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
+#define USB_BDTPAGE3_BDTBA_SHIFT (0U)
+#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
+
+/*! @name ENDPT - Endpoint Control Register */
+#define USB_ENDPT_EPHSHK_MASK (0x1U)
+#define USB_ENDPT_EPHSHK_SHIFT (0U)
+#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
+#define USB_ENDPT_EPSTALL_MASK (0x2U)
+#define USB_ENDPT_EPSTALL_SHIFT (1U)
+#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
+#define USB_ENDPT_EPTXEN_MASK (0x4U)
+#define USB_ENDPT_EPTXEN_SHIFT (2U)
+#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
+#define USB_ENDPT_EPRXEN_MASK (0x8U)
+#define USB_ENDPT_EPRXEN_SHIFT (3U)
+#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
+#define USB_ENDPT_EPCTLDIS_MASK (0x10U)
+#define USB_ENDPT_EPCTLDIS_SHIFT (4U)
+#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
+#define USB_ENDPT_RETRYDIS_MASK (0x40U)
+#define USB_ENDPT_RETRYDIS_SHIFT (6U)
+#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
+#define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
+#define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
+#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
+
+/* The count of USB_ENDPT */
+#define USB_ENDPT_COUNT (16U)
+
+/*! @name USBCTRL - USB Control Register */
+#define USB_USBCTRL_PDE_MASK (0x40U)
+#define USB_USBCTRL_PDE_SHIFT (6U)
+#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
+#define USB_USBCTRL_SUSP_MASK (0x80U)
+#define USB_USBCTRL_SUSP_SHIFT (7U)
+#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
+
+/*! @name OBSERVE - USB OTG Observe Register */
+#define USB_OBSERVE_DMPD_MASK (0x10U)
+#define USB_OBSERVE_DMPD_SHIFT (4U)
+#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
+#define USB_OBSERVE_DPPD_MASK (0x40U)
+#define USB_OBSERVE_DPPD_SHIFT (6U)
+#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
+#define USB_OBSERVE_DPPU_MASK (0x80U)
+#define USB_OBSERVE_DPPU_SHIFT (7U)
+#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
+
+/*! @name CONTROL - USB OTG Control Register */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
+#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
+
+/*! @name USBTRC0 - USB Transceiver Control Register 0 */
+#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
+#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
+#define USB_USBTRC0_SYNC_DET_MASK (0x2U)
+#define USB_USBTRC0_SYNC_DET_SHIFT (1U)
+#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
+#define USB_USBTRC0_USBRESMEN_MASK (0x20U)
+#define USB_USBTRC0_USBRESMEN_SHIFT (5U)
+#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
+#define USB_USBTRC0_USBRESET_MASK (0x80U)
+#define USB_USBTRC0_USBRESET_SHIFT (7U)
+#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
+
+/*! @name USBFRMADJUST - Frame Adjust Register */
+#define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
+#define USB_USBFRMADJUST_ADJ_SHIFT (0U)
+#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0 ((USB_Type *)USB0_BASE)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS { USB0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBDCD Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
+ * @{
+ */
+
+/** USBDCD - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CONTROL; /**< Control Register, offset: 0x0 */
+ __IO uint32_t CLOCK; /**< Clock Register, offset: 0x4 */
+ __I uint32_t STATUS; /**< Status Register, offset: 0x8 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t TIMER0; /**< TIMER0 Register, offset: 0x10 */
+ __IO uint32_t TIMER1; /**< , offset: 0x14 */
+ __IO uint32_t TIMER2; /**< , offset: 0x18 */
+} USBDCD_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USBDCD Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
+ * @{
+ */
+
+/*! @name CONTROL - Control Register */
+#define USBDCD_CONTROL_IACK_MASK (0x1U)
+#define USBDCD_CONTROL_IACK_SHIFT (0U)
+#define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK)
+#define USBDCD_CONTROL_IF_MASK (0x100U)
+#define USBDCD_CONTROL_IF_SHIFT (8U)
+#define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK)
+#define USBDCD_CONTROL_IE_MASK (0x10000U)
+#define USBDCD_CONTROL_IE_SHIFT (16U)
+#define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK)
+#define USBDCD_CONTROL_START_MASK (0x1000000U)
+#define USBDCD_CONTROL_START_SHIFT (24U)
+#define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK)
+#define USBDCD_CONTROL_SR_MASK (0x2000000U)
+#define USBDCD_CONTROL_SR_SHIFT (25U)
+#define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK)
+
+/*! @name CLOCK - Clock Register */
+#define USBDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)
+#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)
+#define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK)
+#define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)
+#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)
+#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK)
+
+/*! @name STATUS - Status Register */
+#define USBDCD_STATUS_SEQ_RES_MASK (0x30000U)
+#define USBDCD_STATUS_SEQ_RES_SHIFT (16U)
+#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK)
+#define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U)
+#define USBDCD_STATUS_SEQ_STAT_SHIFT (18U)
+#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK)
+#define USBDCD_STATUS_ERR_MASK (0x100000U)
+#define USBDCD_STATUS_ERR_SHIFT (20U)
+#define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK)
+#define USBDCD_STATUS_TO_MASK (0x200000U)
+#define USBDCD_STATUS_TO_SHIFT (21U)
+#define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK)
+#define USBDCD_STATUS_ACTIVE_MASK (0x400000U)
+#define USBDCD_STATUS_ACTIVE_SHIFT (22U)
+#define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK)
+
+/*! @name TIMER0 - TIMER0 Register */
+#define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU)
+#define USBDCD_TIMER0_TUNITCON_SHIFT (0U)
+#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK)
+#define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)
+#define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U)
+#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK)
+
+/*! @name TIMER1 - */
+#define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)
+#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)
+#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)
+#define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U)
+#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK)
+
+/*! @name TIMER2 - */
+#define USBDCD_TIMER2_CHECK_DM_MASK (0xFU)
+#define USBDCD_TIMER2_CHECK_DM_SHIFT (0U)
+#define USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_CHECK_DM_SHIFT)) & USBDCD_TIMER2_CHECK_DM_MASK)
+#define USBDCD_TIMER2_TVDPSRC_CON_MASK (0x3FF0000U)
+#define USBDCD_TIMER2_TVDPSRC_CON_SHIFT (16U)
+#define USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_TVDPSRC_CON_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Masks */
+
+
+/* USBDCD - Peripheral instance base addresses */
+/** Peripheral USBDCD base address */
+#define USBDCD_BASE (0x40035000u)
+/** Peripheral USBDCD base pointer */
+#define USBDCD ((USBDCD_Type *)USBDCD_BASE)
+/** Array initializer of USBDCD peripheral base addresses */
+#define USBDCD_BASE_ADDRS { USBDCD_BASE }
+/** Array initializer of USBDCD peripheral base pointers */
+#define USBDCD_BASE_PTRS { USBDCD }
+/** Interrupt vectors for the USBDCD peripheral type */
+#define USBDCD_IRQS { USBDCD_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- VREF Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
+ __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
+} VREF_Type;
+
+/* ----------------------------------------------------------------------------
+ -- VREF Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/*! @name TRM - VREF Trim Register */
+#define VREF_TRM_TRIM_MASK (0x3FU)
+#define VREF_TRM_TRIM_SHIFT (0U)
+#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK (0x40U)
+#define VREF_TRM_CHOPEN_SHIFT (6U)
+#define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
+
+/*! @name SC - VREF Status and Control Register */
+#define VREF_SC_MODE_LV_MASK (0x3U)
+#define VREF_SC_MODE_LV_SHIFT (0U)
+#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK (0x4U)
+#define VREF_SC_VREFST_SHIFT (2U)
+#define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
+#define VREF_SC_REGEN_MASK (0x40U)
+#define VREF_SC_REGEN_SHIFT (6U)
+#define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
+#define VREF_SC_VREFEN_MASK (0x80U)
+#define VREF_SC_VREFEN_SHIFT (7U)
+#define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE (0x40074000u)
+/** Peripheral VREF base pointer */
+#define VREF ((VREF_Type *)VREF_BASE)
+/** Array initializer of VREF peripheral base addresses */
+#define VREF_BASE_ADDRS { VREF_BASE }
+/** Array initializer of VREF peripheral base pointers */
+#define VREF_BASE_PTRS { VREF }
+
+/*!
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- WDOG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
+ * @{
+ */
+
+/** WDOG - Register Layout Typedef */
+typedef struct {
+ __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
+ __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
+ __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
+ __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
+ __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
+ __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
+ __IO uint16_t REFRESH; /**< Watchdog Refresh Register, offset: 0xC */
+ __IO uint16_t UNLOCK; /**< Watchdog Unlock Register, offset: 0xE */
+ __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
+ __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
+ __IO uint16_t RSTCNT; /**< Watchdog Reset Count Register, offset: 0x14 */
+ __IO uint16_t PRESC; /**< Watchdog Prescaler Register, offset: 0x16 */
+} WDOG_Type;
+
+/* ----------------------------------------------------------------------------
+ -- WDOG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Masks WDOG Register Masks
+ * @{
+ */
+
+/*! @name STCTRLH - Watchdog Status and Control Register High */
+#define WDOG_STCTRLH_WDOGEN_MASK (0x1U)
+#define WDOG_STCTRLH_WDOGEN_SHIFT (0U)
+#define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK)
+#define WDOG_STCTRLH_CLKSRC_MASK (0x2U)
+#define WDOG_STCTRLH_CLKSRC_SHIFT (1U)
+#define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
+#define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U)
+#define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U)
+#define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
+#define WDOG_STCTRLH_WINEN_MASK (0x8U)
+#define WDOG_STCTRLH_WINEN_SHIFT (3U)
+#define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
+#define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U)
+#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U)
+#define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
+#define WDOG_STCTRLH_DBGEN_MASK (0x20U)
+#define WDOG_STCTRLH_DBGEN_SHIFT (5U)
+#define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
+#define WDOG_STCTRLH_STOPEN_MASK (0x40U)
+#define WDOG_STCTRLH_STOPEN_SHIFT (6U)
+#define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
+#define WDOG_STCTRLH_WAITEN_MASK (0x80U)
+#define WDOG_STCTRLH_WAITEN_SHIFT (7U)
+#define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
+#define WDOG_STCTRLH_TESTWDOG_MASK (0x400U)
+#define WDOG_STCTRLH_TESTWDOG_SHIFT (10U)
+#define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
+#define WDOG_STCTRLH_TESTSEL_MASK (0x800U)
+#define WDOG_STCTRLH_TESTSEL_SHIFT (11U)
+#define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
+#define WDOG_STCTRLH_BYTESEL_MASK (0x3000U)
+#define WDOG_STCTRLH_BYTESEL_SHIFT (12U)
+#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U)
+#define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U)
+#define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
+
+/*! @name STCTRLL - Watchdog Status and Control Register Low */
+#define WDOG_STCTRLL_INTFLG_MASK (0x8000U)
+#define WDOG_STCTRLL_INTFLG_SHIFT (15U)
+#define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
+
+/*! @name TOVALH - Watchdog Time-out Value Register High */
+#define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU)
+#define WDOG_TOVALH_TOVALHIGH_SHIFT (0U)
+#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
+
+/*! @name TOVALL - Watchdog Time-out Value Register Low */
+#define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU)
+#define WDOG_TOVALL_TOVALLOW_SHIFT (0U)
+#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
+
+/*! @name WINH - Watchdog Window Register High */
+#define WDOG_WINH_WINHIGH_MASK (0xFFFFU)
+#define WDOG_WINH_WINHIGH_SHIFT (0U)
+#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
+
+/*! @name WINL - Watchdog Window Register Low */
+#define WDOG_WINL_WINLOW_MASK (0xFFFFU)
+#define WDOG_WINL_WINLOW_SHIFT (0U)
+#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
+
+/*! @name REFRESH - Watchdog Refresh Register */
+#define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU)
+#define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U)
+#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
+
+/*! @name UNLOCK - Watchdog Unlock Register */
+#define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU)
+#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U)
+#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
+
+/*! @name TMROUTH - Watchdog Timer Output Register High */
+#define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU)
+#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U)
+#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+
+/*! @name TMROUTL - Watchdog Timer Output Register Low */
+#define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU)
+#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U)
+#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
+
+/*! @name RSTCNT - Watchdog Reset Count Register */
+#define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU)
+#define WDOG_RSTCNT_RSTCNT_SHIFT (0U)
+#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
+
+/*! @name PRESC - Watchdog Prescaler Register */
+#define WDOG_PRESC_PRESCVAL_MASK (0x700U)
+#define WDOG_PRESC_PRESCVAL_SHIFT (8U)
+#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Masks */
+
+
+/* WDOG - Peripheral instance base addresses */
+/** Peripheral WDOG base address */
+#define WDOG_BASE (0x40052000u)
+/** Peripheral WDOG base pointer */
+#define WDOG ((WDOG_Type *)WDOG_BASE)
+/** Array initializer of WDOG peripheral base addresses */
+#define WDOG_BASE_ADDRS { WDOG_BASE }
+/** Array initializer of WDOG peripheral base pointers */
+#define WDOG_BASE_PTRS { WDOG }
+/** Interrupt vectors for the WDOG peripheral type */
+#define WDOG_IRQS { Watchdog_IRQn }
+
+/*!
+ * @}
+ */ /* end of group WDOG_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma pop
+#elif defined(__CWCC__)
+ #pragma pop
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=default
+#else
+ #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SDK Compatibility
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
+ * @{
+ */
+
+#define PDB_CHC1_REG(base,index) PDB_C1_REG(base,index)
+#define PDB_CHDLY0_REG(base,index) PDB_DLY_REG(base,index,0)
+#define PDB_CHDLY1_REG(base,index) PDB_DLY_REG(base,index,1)
+#define PDB_CHC1_EN_MASK PDB_C1_EN_MASK
+#define PDB_CHC1_EN_SHIFT PDB_C1_EN_SHIFT
+#define PDB_CHC1_EN(x) PDB_C1_EN(x)
+#define PDB_CHC1_TOS_MASK PDB_C1_TOS_MASK
+#define PDB_CHC1_TOS_SHIFT PDB_C1_TOS_SHIFT
+#define PDB_CHC1_TOS(x) PDB_C1_TOS(x)
+#define PDB_CHC1_BB_MASK PDB_C1_BB_MASK
+#define PDB_CHC1_BB_SHIFT PDB_C1_BB_SHIFT
+#define PDB_CHC1_BB(x) PDB_C1_BB(x)
+#define PDB_CHDLY0_DLY_MASK PDB_DLY_DLY_MASK
+#define PDB_CHDLY0_DLY_SHIFT PDB_DLY_DLY_SHIFT
+#define PDB_CHDLY0_DLY(x) PDB_DLY_DLY(x)
+#define PDB_CHDLY1_DLY_MASK PDB_DLY_DLY_MASK
+#define PDB_CHDLY1_DLY_SHIFT PDB_DLY_DLY_SHIFT
+#define PDB_CHDLY1_DLY(x) PDB_DLY_DLY(x)
+#define PDB0_CHC1(index) PDB0_C1(index)
+#define PDB0_CHDLY0(index) PDB0_DLY(index,0)
+#define PDB0_CHDLY1(index) PDB0_DLY(index,1)
+#define GPIOA_BASE PTA_BASE
+#define GPIOA PTA
+#define GPIOB_BASE PTB_BASE
+#define GPIOB PTB
+#define GPIOC_BASE PTC_BASE
+#define GPIOC PTC
+#define GPIOD_BASE PTD_BASE
+#define GPIOD PTD
+#define GPIOE_BASE PTE_BASE
+#define GPIOE PTE
+#define DMAMUX0 DMAMUX
+
+/*!
+ * @}
+ */ /* end of group SDK_Compatibility_Symbols */
+
+
+#endif /* _MK20D5_H_ */
+
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k20dx/MK20D5/MK20D5_features.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/freescale/k20dx/MK20D5/MK20D5_features.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,3040 @@ +/* +** ################################################################### +** Version: rev. 2.7, 2015-06-08 +** Build: b151210 +** +** Abstract: +** Chip specific module features. +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2011-12-15) +** Initial version +** - rev. 2.0 (2012-03-19) +** PDB Peripheral register structure updated. +** DMA Registers and bits for unsupported DMA channels removed. +** - rev. 2.1 (2013-06-24) +** NV_FOPT register - NMI_DIS bit added. +** - rev. 2.2 (2014-01-30) +** Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum. +** - rev. 2.3 (2015-01-21) +** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances +** - rev. 2.4 (2015-05-19) +** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT. +** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC. +** Added features for PDB and PORT. +** - rev. 2.5 (2015-05-25) +** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS +** - rev. 2.6 (2015-05-27) +** Several USB features added. +** - rev. 2.7 (2015-06-08) +** FTM features BUS_CLOCK and FAST_CLOCK removed. +** +** ################################################################### +*/ + +#ifndef _MK20D5_FEATURES_H_ +#define _MK20D5_FEATURES_H_ + +/* SOC module features */ + +#if defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ + defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) + /* @brief ACMP availability on the SoC. */ + #define FSL_FEATURE_SOC_ACMP_COUNT (0) + /* @brief ADC16 availability on the SoC. */ + #define FSL_FEATURE_SOC_ADC16_COUNT (1) + /* @brief ADC12 availability on the SoC. */ + #define FSL_FEATURE_SOC_ADC12_COUNT (0) + /* @brief AFE availability on the SoC. */ + #define FSL_FEATURE_SOC_AFE_COUNT (0) + /* @brief AIPS availability on the SoC. */ + #define FSL_FEATURE_SOC_AIPS_COUNT (0) + /* @brief AOI availability on the SoC. */ + #define FSL_FEATURE_SOC_AOI_COUNT (0) + /* @brief AXBS availability on the SoC. */ + #define FSL_FEATURE_SOC_AXBS_COUNT (0) + /* @brief ASMC availability on the SoC. */ + #define FSL_FEATURE_SOC_ASMC_COUNT (0) + /* @brief CADC availability on the SoC. */ + #define FSL_FEATURE_SOC_CADC_COUNT (0) + /* @brief FLEXCAN availability on the SoC. */ + #define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) + /* @brief MMCAU availability on the SoC. */ + #define FSL_FEATURE_SOC_MMCAU_COUNT (0) + /* @brief CMP availability on the SoC. */ + #define FSL_FEATURE_SOC_CMP_COUNT (2) + /* @brief CMT availability on the SoC. */ + #define FSL_FEATURE_SOC_CMT_COUNT (1) + /* @brief CNC availability on the SoC. */ + #define FSL_FEATURE_SOC_CNC_COUNT (0) + /* @brief CRC availability on the SoC. */ + #define FSL_FEATURE_SOC_CRC_COUNT (1) + /* @brief DAC availability on the SoC. */ + #define FSL_FEATURE_SOC_DAC_COUNT (0) + /* @brief DAC32 availability on the SoC. */ + #define FSL_FEATURE_SOC_DAC32_COUNT (0) + /* @brief DCDC availability on the SoC. */ + #define FSL_FEATURE_SOC_DCDC_COUNT (0) + /* @brief DDR availability on the SoC. */ + #define FSL_FEATURE_SOC_DDR_COUNT (0) + /* @brief DMA availability on the SoC. */ + #define FSL_FEATURE_SOC_DMA_COUNT (0) + /* @brief DMAMUX availability on the SoC. */ + #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) + /* @brief DRY availability on the SoC. */ + #define FSL_FEATURE_SOC_DRY_COUNT (0) + /* @brief DSPI availability on the SoC. */ + #define FSL_FEATURE_SOC_DSPI_COUNT (1) + /* @brief EDMA availability on the SoC. */ + #define FSL_FEATURE_SOC_EDMA_COUNT (1) + /* @brief EMVSIM availability on the SoC. */ + #define FSL_FEATURE_SOC_EMVSIM_COUNT (0) + /* @brief ENC availability on the SoC. */ + #define FSL_FEATURE_SOC_ENC_COUNT (0) + /* @brief ENET availability on the SoC. */ + #define FSL_FEATURE_SOC_ENET_COUNT (0) + /* @brief EWM availability on the SoC. */ + #define FSL_FEATURE_SOC_EWM_COUNT (1) + /* @brief FB availability on the SoC. */ + #define FSL_FEATURE_SOC_FB_COUNT (0) + /* @brief FGPIO availability on the SoC. */ + #define FSL_FEATURE_SOC_FGPIO_COUNT (0) + /* @brief FLEXIO availability on the SoC. */ + #define FSL_FEATURE_SOC_FLEXIO_COUNT (0) + /* @brief FMC availability on the SoC. */ + #define FSL_FEATURE_SOC_FMC_COUNT (1) + /* @brief FSKDT availability on the SoC. */ + #define FSL_FEATURE_SOC_FSKDT_COUNT (0) + /* @brief FTFA availability on the SoC. */ + #define FSL_FEATURE_SOC_FTFA_COUNT (0) + /* @brief FTFE availability on the SoC. */ + #define FSL_FEATURE_SOC_FTFE_COUNT (0) + /* @brief FTFL availability on the SoC. */ + #define FSL_FEATURE_SOC_FTFL_COUNT (1) + /* @brief FTM availability on the SoC. */ + #define FSL_FEATURE_SOC_FTM_COUNT (2) + /* @brief FTMRA availability on the SoC. */ + #define FSL_FEATURE_SOC_FTMRA_COUNT (0) + /* @brief FTMRE availability on the SoC. */ + #define FSL_FEATURE_SOC_FTMRE_COUNT (0) + /* @brief FTMRH availability on the SoC. */ + #define FSL_FEATURE_SOC_FTMRH_COUNT (0) + /* @brief GPIO availability on the SoC. */ + #define FSL_FEATURE_SOC_GPIO_COUNT (5) + /* @brief HSADC availability on the SoC. */ + #define FSL_FEATURE_SOC_HSADC_COUNT (0) + /* @brief I2C availability on the SoC. */ + #define FSL_FEATURE_SOC_I2C_COUNT (1) + /* @brief I2S availability on the SoC. */ + #define FSL_FEATURE_SOC_I2S_COUNT (1) + /* @brief ICS availability on the SoC. */ + #define FSL_FEATURE_SOC_ICS_COUNT (0) + /* @brief IRQ availability on the SoC. */ + #define FSL_FEATURE_SOC_IRQ_COUNT (0) + /* @brief INTMUX availability on the SoC. */ + #define FSL_FEATURE_SOC_INTMUX_COUNT (0) + /* @brief KBI availability on the SoC. */ + #define FSL_FEATURE_SOC_KBI_COUNT (0) + /* @brief SLCD availability on the SoC. */ + #define FSL_FEATURE_SOC_SLCD_COUNT (0) + /* @brief LCDC availability on the SoC. */ + #define FSL_FEATURE_SOC_LCDC_COUNT (0) + /* @brief LDO availability on the SoC. */ + #define FSL_FEATURE_SOC_LDO_COUNT (0) + /* @brief LLWU availability on the SoC. */ + #define FSL_FEATURE_SOC_LLWU_COUNT (1) + /* @brief LMEM availability on the SoC. */ + #define FSL_FEATURE_SOC_LMEM_COUNT (0) + /* @brief LPSCI availability on the SoC. */ + #define FSL_FEATURE_SOC_LPSCI_COUNT (0) + /* @brief LPTMR availability on the SoC. */ + #define FSL_FEATURE_SOC_LPTMR_COUNT (1) + /* @brief LPTPM availability on the SoC. */ + #define FSL_FEATURE_SOC_LPTPM_COUNT (0) + /* @brief LPUART availability on the SoC. */ + #define FSL_FEATURE_SOC_LPUART_COUNT (0) + /* @brief LTC availability on the SoC. */ + #define FSL_FEATURE_SOC_LTC_COUNT (0) + /* @brief LPI2C availability on the SoC. */ + #define FSL_FEATURE_SOC_LPI2C_COUNT (0) + /* @brief LPSPI availability on the SoC. */ + #define FSL_FEATURE_SOC_LPSPI_COUNT (0) + /* @brief LPIT availability on the SoC. */ + #define FSL_FEATURE_SOC_LPIT_COUNT (0) + /* @brief MC availability on the SoC. */ + #define FSL_FEATURE_SOC_MC_COUNT (0) + /* @brief MCG availability on the SoC. */ + #define FSL_FEATURE_SOC_MCG_COUNT (1) + /* @brief MCGLITE availability on the SoC. */ + #define FSL_FEATURE_SOC_MCGLITE_COUNT (0) + /* @brief MCM availability on the SoC. */ + #define FSL_FEATURE_SOC_MCM_COUNT (0) + /* @brief MMAU availability on the SoC. */ + #define FSL_FEATURE_SOC_MMAU_COUNT (0) + /* @brief MMDVSQ availability on the SoC. */ + #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) + /* @brief MPU availability on the SoC. */ + #define FSL_FEATURE_SOC_MPU_COUNT (0) + /* @brief MSCAN availability on the SoC. */ + #define FSL_FEATURE_SOC_MSCAN_COUNT (0) + /* @brief MSCM availability on the SoC. */ + #define FSL_FEATURE_SOC_MSCM_COUNT (0) + /* @brief MTB availability on the SoC. */ + #define FSL_FEATURE_SOC_MTB_COUNT (0) + /* @brief MTBDWT availability on the SoC. */ + #define FSL_FEATURE_SOC_MTBDWT_COUNT (0) + /* @brief MU availability on the SoC. */ + #define FSL_FEATURE_SOC_MU_COUNT (0) + /* @brief NFC availability on the SoC. */ + #define FSL_FEATURE_SOC_NFC_COUNT (0) + /* @brief OPAMP availability on the SoC. */ + #define FSL_FEATURE_SOC_OPAMP_COUNT (0) + /* @brief OSC availability on the SoC. */ + #define FSL_FEATURE_SOC_OSC_COUNT (1) + /* @brief OSC32 availability on the SoC. */ + #define FSL_FEATURE_SOC_OSC32_COUNT (0) + /* @brief OTFAD availability on the SoC. */ + #define FSL_FEATURE_SOC_OTFAD_COUNT (0) + /* @brief PDB availability on the SoC. */ + #define FSL_FEATURE_SOC_PDB_COUNT (1) + /* @brief PGA availability on the SoC. */ + #define FSL_FEATURE_SOC_PGA_COUNT (0) + /* @brief PIT availability on the SoC. */ + #define FSL_FEATURE_SOC_PIT_COUNT (1) + /* @brief PMC availability on the SoC. */ + #define FSL_FEATURE_SOC_PMC_COUNT (1) + /* @brief PORT availability on the SoC. */ + #define FSL_FEATURE_SOC_PORT_COUNT (5) + /* @brief PWM availability on the SoC. */ + #define FSL_FEATURE_SOC_PWM_COUNT (0) + /* @brief PWT availability on the SoC. */ + #define FSL_FEATURE_SOC_PWT_COUNT (0) + /* @brief PCC availability on the SoC. */ + #define FSL_FEATURE_SOC_PCC_COUNT (0) + /* @brief QuadSPI availability on the SoC. */ + #define FSL_FEATURE_SOC_QuadSPI_COUNT (0) + /* @brief RCM availability on the SoC. */ + #define FSL_FEATURE_SOC_RCM_COUNT (1) + /* @brief RFSYS availability on the SoC. */ + #define FSL_FEATURE_SOC_RFSYS_COUNT (1) + /* @brief RFVBAT availability on the SoC. */ + #define FSL_FEATURE_SOC_RFVBAT_COUNT (1) + /* @brief RNG availability on the SoC. */ + #define FSL_FEATURE_SOC_RNG_COUNT (0) + /* @brief RNGB availability on the SoC. */ + #define FSL_FEATURE_SOC_RNGB_COUNT (0) + /* @brief ROM availability on the SoC. */ + #define FSL_FEATURE_SOC_ROM_COUNT (0) + /* @brief RSIM availability on the SoC. */ + #define FSL_FEATURE_SOC_RSIM_COUNT (0) + /* @brief RTC availability on the SoC. */ + #define FSL_FEATURE_SOC_RTC_COUNT (1) + /* @brief SCI availability on the SoC. */ + #define FSL_FEATURE_SOC_SCI_COUNT (0) + /* @brief SDHC availability on the SoC. */ + #define FSL_FEATURE_SOC_SDHC_COUNT (0) + /* @brief SDRAM availability on the SoC. */ + #define FSL_FEATURE_SOC_SDRAM_COUNT (0) + /* @brief SIM availability on the SoC. */ + #define FSL_FEATURE_SOC_SIM_COUNT (1) + /* @brief SMC availability on the SoC. */ + #define FSL_FEATURE_SOC_SMC_COUNT (1) + /* @brief SPI availability on the SoC. */ + #define FSL_FEATURE_SOC_SPI_COUNT (0) + /* @brief SCG availability on the SoC. */ + #define FSL_FEATURE_SOC_SCG_COUNT (0) + /* @brief SEMA42 availability on the SoC. */ + #define FSL_FEATURE_SOC_SEMA42_COUNT (0) + /* @brief TMR availability on the SoC. */ + #define FSL_FEATURE_SOC_TMR_COUNT (0) + /* @brief TPM availability on the SoC. */ + #define FSL_FEATURE_SOC_TPM_COUNT (0) + /* @brief TRIAMP availability on the SoC. */ + #define FSL_FEATURE_SOC_TRIAMP_COUNT (0) + /* @brief TRNG availability on the SoC. */ + #define FSL_FEATURE_SOC_TRNG_COUNT (0) + /* @brief TSI availability on the SoC. */ + #define FSL_FEATURE_SOC_TSI_COUNT (1) + /* @brief TRGMUX availability on the SoC. */ + #define FSL_FEATURE_SOC_TRGMUX_COUNT (0) + /* @brief TSTMR availability on the SoC. */ + #define FSL_FEATURE_SOC_TSTMR_COUNT (0) + /* @brief UART availability on the SoC. */ + #define FSL_FEATURE_SOC_UART_COUNT (3) + /* @brief USB availability on the SoC. */ + #define FSL_FEATURE_SOC_USB_COUNT (1) + /* @brief USBDCD availability on the SoC. */ + #define FSL_FEATURE_SOC_USBDCD_COUNT (1) + /* @brief USBHSDCD availability on the SoC. */ + #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) + /* @brief USBPHY availability on the SoC. */ + #define FSL_FEATURE_SOC_USBPHY_COUNT (0) + /* @brief VREF availability on the SoC. */ + #define FSL_FEATURE_SOC_VREF_COUNT (0) + /* @brief WDOG availability on the SoC. */ + #define FSL_FEATURE_SOC_WDOG_COUNT (1) + /* @brief XBAR availability on the SoC. */ + #define FSL_FEATURE_SOC_XBAR_COUNT (0) + /* @brief XBARA availability on the SoC. */ + #define FSL_FEATURE_SOC_XBARA_COUNT (0) + /* @brief XBARB availability on the SoC. */ + #define FSL_FEATURE_SOC_XBARB_COUNT (0) + /* @brief XCVR availability on the SoC. */ + #define FSL_FEATURE_SOC_XCVR_COUNT (0) + /* @brief XRDC availability on the SoC. */ + #define FSL_FEATURE_SOC_XRDC_COUNT (0) + /* @brief ZLL availability on the SoC. */ + #define FSL_FEATURE_SOC_ZLL_COUNT (0) +#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ + defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ + defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ + defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ + defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ + defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) + /* @brief ACMP availability on the SoC. */ + #define FSL_FEATURE_SOC_ACMP_COUNT (0) + /* @brief ADC16 availability on the SoC. */ + #define FSL_FEATURE_SOC_ADC16_COUNT (1) + /* @brief ADC12 availability on the SoC. */ + #define FSL_FEATURE_SOC_ADC12_COUNT (0) + /* @brief AFE availability on the SoC. */ + #define FSL_FEATURE_SOC_AFE_COUNT (0) + /* @brief AIPS availability on the SoC. */ + #define FSL_FEATURE_SOC_AIPS_COUNT (0) + /* @brief AOI availability on the SoC. */ + #define FSL_FEATURE_SOC_AOI_COUNT (0) + /* @brief AXBS availability on the SoC. */ + #define FSL_FEATURE_SOC_AXBS_COUNT (0) + /* @brief ASMC availability on the SoC. */ + #define FSL_FEATURE_SOC_ASMC_COUNT (0) + /* @brief CADC availability on the SoC. */ + #define FSL_FEATURE_SOC_CADC_COUNT (0) + /* @brief FLEXCAN availability on the SoC. */ + #define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) + /* @brief MMCAU availability on the SoC. */ + #define FSL_FEATURE_SOC_MMCAU_COUNT (0) + /* @brief CMP availability on the SoC. */ + #define FSL_FEATURE_SOC_CMP_COUNT (2) + /* @brief CMT availability on the SoC. */ + #define FSL_FEATURE_SOC_CMT_COUNT (1) + /* @brief CNC availability on the SoC. */ + #define FSL_FEATURE_SOC_CNC_COUNT (0) + /* @brief CRC availability on the SoC. */ + #define FSL_FEATURE_SOC_CRC_COUNT (1) + /* @brief DAC availability on the SoC. */ + #define FSL_FEATURE_SOC_DAC_COUNT (0) + /* @brief DAC32 availability on the SoC. */ + #define FSL_FEATURE_SOC_DAC32_COUNT (0) + /* @brief DCDC availability on the SoC. */ + #define FSL_FEATURE_SOC_DCDC_COUNT (0) + /* @brief DDR availability on the SoC. */ + #define FSL_FEATURE_SOC_DDR_COUNT (0) + /* @brief DMA availability on the SoC. */ + #define FSL_FEATURE_SOC_DMA_COUNT (0) + /* @brief DMAMUX availability on the SoC. */ + #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) + /* @brief DRY availability on the SoC. */ + #define FSL_FEATURE_SOC_DRY_COUNT (0) + /* @brief DSPI availability on the SoC. */ + #define FSL_FEATURE_SOC_DSPI_COUNT (1) + /* @brief EDMA availability on the SoC. */ + #define FSL_FEATURE_SOC_EDMA_COUNT (1) + /* @brief EMVSIM availability on the SoC. */ + #define FSL_FEATURE_SOC_EMVSIM_COUNT (0) + /* @brief ENC availability on the SoC. */ + #define FSL_FEATURE_SOC_ENC_COUNT (0) + /* @brief ENET availability on the SoC. */ + #define FSL_FEATURE_SOC_ENET_COUNT (0) + /* @brief EWM availability on the SoC. */ + #define FSL_FEATURE_SOC_EWM_COUNT (1) + /* @brief FB availability on the SoC. */ + #define FSL_FEATURE_SOC_FB_COUNT (0) + /* @brief FGPIO availability on the SoC. */ + #define FSL_FEATURE_SOC_FGPIO_COUNT (0) + /* @brief FLEXIO availability on the SoC. */ + #define FSL_FEATURE_SOC_FLEXIO_COUNT (0) + /* @brief FMC availability on the SoC. */ + #define FSL_FEATURE_SOC_FMC_COUNT (1) + /* @brief FSKDT availability on the SoC. */ + #define FSL_FEATURE_SOC_FSKDT_COUNT (0) + /* @brief FTFA availability on the SoC. */ + #define FSL_FEATURE_SOC_FTFA_COUNT (0) + /* @brief FTFE availability on the SoC. */ + #define FSL_FEATURE_SOC_FTFE_COUNT (0) + /* @brief FTFL availability on the SoC. */ + #define FSL_FEATURE_SOC_FTFL_COUNT (1) + /* @brief FTM availability on the SoC. */ + #define FSL_FEATURE_SOC_FTM_COUNT (2) + /* @brief FTMRA availability on the SoC. */ + #define FSL_FEATURE_SOC_FTMRA_COUNT (0) + /* @brief FTMRE availability on the SoC. */ + #define FSL_FEATURE_SOC_FTMRE_COUNT (0) + /* @brief FTMRH availability on the SoC. */ + #define FSL_FEATURE_SOC_FTMRH_COUNT (0) + /* @brief GPIO availability on the SoC. */ + #define FSL_FEATURE_SOC_GPIO_COUNT (5) + /* @brief HSADC availability on the SoC. */ + #define FSL_FEATURE_SOC_HSADC_COUNT (0) + /* @brief I2C availability on the SoC. */ + #define FSL_FEATURE_SOC_I2C_COUNT (1) + /* @brief I2S availability on the SoC. */ + #define FSL_FEATURE_SOC_I2S_COUNT (1) + /* @brief ICS availability on the SoC. */ + #define FSL_FEATURE_SOC_ICS_COUNT (0) + /* @brief IRQ availability on the SoC. */ + #define FSL_FEATURE_SOC_IRQ_COUNT (0) + /* @brief INTMUX availability on the SoC. */ + #define FSL_FEATURE_SOC_INTMUX_COUNT (0) + /* @brief KBI availability on the SoC. */ + #define FSL_FEATURE_SOC_KBI_COUNT (0) + /* @brief SLCD availability on the SoC. */ + #define FSL_FEATURE_SOC_SLCD_COUNT (0) + /* @brief LCDC availability on the SoC. */ + #define FSL_FEATURE_SOC_LCDC_COUNT (0) + /* @brief LDO availability on the SoC. */ + #define FSL_FEATURE_SOC_LDO_COUNT (0) + /* @brief LLWU availability on the SoC. */ + #define FSL_FEATURE_SOC_LLWU_COUNT (1) + /* @brief LMEM availability on the SoC. */ + #define FSL_FEATURE_SOC_LMEM_COUNT (0) + /* @brief LPSCI availability on the SoC. */ + #define FSL_FEATURE_SOC_LPSCI_COUNT (0) + /* @brief LPTMR availability on the SoC. */ + #define FSL_FEATURE_SOC_LPTMR_COUNT (1) + /* @brief LPTPM availability on the SoC. */ + #define FSL_FEATURE_SOC_LPTPM_COUNT (0) + /* @brief LPUART availability on the SoC. */ + #define FSL_FEATURE_SOC_LPUART_COUNT (0) + /* @brief LTC availability on the SoC. */ + #define FSL_FEATURE_SOC_LTC_COUNT (0) + /* @brief LPI2C availability on the SoC. */ + #define FSL_FEATURE_SOC_LPI2C_COUNT (0) + /* @brief LPSPI availability on the SoC. */ + #define FSL_FEATURE_SOC_LPSPI_COUNT (0) + /* @brief LPIT availability on the SoC. */ + #define FSL_FEATURE_SOC_LPIT_COUNT (0) + /* @brief MC availability on the SoC. */ + #define FSL_FEATURE_SOC_MC_COUNT (0) + /* @brief MCG availability on the SoC. */ + #define FSL_FEATURE_SOC_MCG_COUNT (1) + /* @brief MCGLITE availability on the SoC. */ + #define FSL_FEATURE_SOC_MCGLITE_COUNT (0) + /* @brief MCM availability on the SoC. */ + #define FSL_FEATURE_SOC_MCM_COUNT (0) + /* @brief MMAU availability on the SoC. */ + #define FSL_FEATURE_SOC_MMAU_COUNT (0) + /* @brief MMDVSQ availability on the SoC. */ + #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) + /* @brief MPU availability on the SoC. */ + #define FSL_FEATURE_SOC_MPU_COUNT (0) + /* @brief MSCAN availability on the SoC. */ + #define FSL_FEATURE_SOC_MSCAN_COUNT (0) + /* @brief MSCM availability on the SoC. */ + #define FSL_FEATURE_SOC_MSCM_COUNT (0) + /* @brief MTB availability on the SoC. */ + #define FSL_FEATURE_SOC_MTB_COUNT (0) + /* @brief MTBDWT availability on the SoC. */ + #define FSL_FEATURE_SOC_MTBDWT_COUNT (0) + /* @brief MU availability on the SoC. */ + #define FSL_FEATURE_SOC_MU_COUNT (0) + /* @brief NFC availability on the SoC. */ + #define FSL_FEATURE_SOC_NFC_COUNT (0) + /* @brief OPAMP availability on the SoC. */ + #define FSL_FEATURE_SOC_OPAMP_COUNT (0) + /* @brief OSC availability on the SoC. */ + #define FSL_FEATURE_SOC_OSC_COUNT (1) + /* @brief OSC32 availability on the SoC. */ + #define FSL_FEATURE_SOC_OSC32_COUNT (0) + /* @brief OTFAD availability on the SoC. */ + #define FSL_FEATURE_SOC_OTFAD_COUNT (0) + /* @brief PDB availability on the SoC. */ + #define FSL_FEATURE_SOC_PDB_COUNT (1) + /* @brief PGA availability on the SoC. */ + #define FSL_FEATURE_SOC_PGA_COUNT (0) + /* @brief PIT availability on the SoC. */ + #define FSL_FEATURE_SOC_PIT_COUNT (1) + /* @brief PMC availability on the SoC. */ + #define FSL_FEATURE_SOC_PMC_COUNT (1) + /* @brief PORT availability on the SoC. */ + #define FSL_FEATURE_SOC_PORT_COUNT (5) + /* @brief PWM availability on the SoC. */ + #define FSL_FEATURE_SOC_PWM_COUNT (0) + /* @brief PWT availability on the SoC. */ + #define FSL_FEATURE_SOC_PWT_COUNT (0) + /* @brief PCC availability on the SoC. */ + #define FSL_FEATURE_SOC_PCC_COUNT (0) + /* @brief QuadSPI availability on the SoC. */ + #define FSL_FEATURE_SOC_QuadSPI_COUNT (0) + /* @brief RCM availability on the SoC. */ + #define FSL_FEATURE_SOC_RCM_COUNT (1) + /* @brief RFSYS availability on the SoC. */ + #define FSL_FEATURE_SOC_RFSYS_COUNT (1) + /* @brief RFVBAT availability on the SoC. */ + #define FSL_FEATURE_SOC_RFVBAT_COUNT (1) + /* @brief RNG availability on the SoC. */ + #define FSL_FEATURE_SOC_RNG_COUNT (0) + /* @brief RNGB availability on the SoC. */ + #define FSL_FEATURE_SOC_RNGB_COUNT (0) + /* @brief ROM availability on the SoC. */ + #define FSL_FEATURE_SOC_ROM_COUNT (0) + /* @brief RSIM availability on the SoC. */ + #define FSL_FEATURE_SOC_RSIM_COUNT (0) + /* @brief RTC availability on the SoC. */ + #define FSL_FEATURE_SOC_RTC_COUNT (1) + /* @brief SCI availability on the SoC. */ + #define FSL_FEATURE_SOC_SCI_COUNT (0) + /* @brief SDHC availability on the SoC. */ + #define FSL_FEATURE_SOC_SDHC_COUNT (0) + /* @brief SDRAM availability on the SoC. */ + #define FSL_FEATURE_SOC_SDRAM_COUNT (0) + /* @brief SIM availability on the SoC. */ + #define FSL_FEATURE_SOC_SIM_COUNT (1) + /* @brief SMC availability on the SoC. */ + #define FSL_FEATURE_SOC_SMC_COUNT (1) + /* @brief SPI availability on the SoC. */ + #define FSL_FEATURE_SOC_SPI_COUNT (0) + /* @brief SCG availability on the SoC. */ + #define FSL_FEATURE_SOC_SCG_COUNT (0) + /* @brief SEMA42 availability on the SoC. */ + #define FSL_FEATURE_SOC_SEMA42_COUNT (0) + /* @brief TMR availability on the SoC. */ + #define FSL_FEATURE_SOC_TMR_COUNT (0) + /* @brief TPM availability on the SoC. */ + #define FSL_FEATURE_SOC_TPM_COUNT (0) + /* @brief TRIAMP availability on the SoC. */ + #define FSL_FEATURE_SOC_TRIAMP_COUNT (0) + /* @brief TRNG availability on the SoC. */ + #define FSL_FEATURE_SOC_TRNG_COUNT (0) + /* @brief TSI availability on the SoC. */ + #define FSL_FEATURE_SOC_TSI_COUNT (1) + /* @brief TRGMUX availability on the SoC. */ + #define FSL_FEATURE_SOC_TRGMUX_COUNT (0) + /* @brief TSTMR availability on the SoC. */ + #define FSL_FEATURE_SOC_TSTMR_COUNT (0) + /* @brief UART availability on the SoC. */ + #define FSL_FEATURE_SOC_UART_COUNT (3) + /* @brief USB availability on the SoC. */ + #define FSL_FEATURE_SOC_USB_COUNT (1) + /* @brief USBDCD availability on the SoC. */ + #define FSL_FEATURE_SOC_USBDCD_COUNT (1) + /* @brief USBHSDCD availability on the SoC. */ + #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) + /* @brief USBPHY availability on the SoC. */ + #define FSL_FEATURE_SOC_USBPHY_COUNT (0) + /* @brief VREF availability on the SoC. */ + #define FSL_FEATURE_SOC_VREF_COUNT (1) + /* @brief WDOG availability on the SoC. */ + #define FSL_FEATURE_SOC_WDOG_COUNT (1) + /* @brief XBAR availability on the SoC. */ + #define FSL_FEATURE_SOC_XBAR_COUNT (0) + /* @brief XBARA availability on the SoC. */ + #define FSL_FEATURE_SOC_XBARA_COUNT (0) + /* @brief XBARB availability on the SoC. */ + #define FSL_FEATURE_SOC_XBARB_COUNT (0) + /* @brief XCVR availability on the SoC. */ + #define FSL_FEATURE_SOC_XCVR_COUNT (0) + /* @brief XRDC availability on the SoC. */ + #define FSL_FEATURE_SOC_XRDC_COUNT (0) + /* @brief ZLL availability on the SoC. */ + #define FSL_FEATURE_SOC_ZLL_COUNT (0) +#endif + +/* ADC16 module features */ + +#if defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ + defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) + /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ + #define FSL_FEATURE_ADC16_HAS_PGA (0) + /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ + #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) + /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ + #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) + /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ + #define FSL_FEATURE_ADC16_HAS_DMA (1) + /* @brief Has differential mode (bitfield SC1x[DIFF]). */ + #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (0) + /* @brief Has FIFO (bit SC4[AFDEP]). */ + #define FSL_FEATURE_ADC16_HAS_FIFO (0) + /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ + #define FSL_FEATURE_ADC16_FIFO_SIZE (0) + /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ + #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) + /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ + #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) + /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ + #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) + /* @brief Has HW averaging (bit SC3[AVGE]). */ + #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) + /* @brief Has offset correction (register OFS). */ + #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) + /* @brief Maximum ADC resolution. */ + #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) + /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ + #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) +#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ + defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ + defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ + defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ + defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ + defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) + /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ + #define FSL_FEATURE_ADC16_HAS_PGA (0) + /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ + #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) + /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ + #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) + /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ + #define FSL_FEATURE_ADC16_HAS_DMA (1) + /* @brief Has differential mode (bitfield SC1x[DIFF]). */ + #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) + /* @brief Has FIFO (bit SC4[AFDEP]). */ + #define FSL_FEATURE_ADC16_HAS_FIFO (0) + /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ + #define FSL_FEATURE_ADC16_FIFO_SIZE (0) + /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ + #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) + /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ + #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) + /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ + #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) + /* @brief Has HW averaging (bit SC3[AVGE]). */ + #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) + /* @brief Has offset correction (register OFS). */ + #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) + /* @brief Maximum ADC resolution. */ + #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) + /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ + #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) +#endif /* defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ + defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) */ + +/* CMP module features */ + +/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ +#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0) +/* @brief Has Window mode in CMP (register bit field CR1[WE]). */ +#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) +/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ +#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) +/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ +#define FSL_FEATURE_CMP_HAS_DMA (1) +/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ +#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) +/* @brief Has DAC Test function in CMP (register DACTEST). */ +#define FSL_FEATURE_CMP_HAS_DAC_TEST (0) + +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (4) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 4) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0) + +/* DMAMUX module features */ + +/* @brief Number of DMA channels (related to number of register CHCFGn). */ +#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 4) +/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ +#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) + +/* EWM module features */ + +/* @brief Has clock select (register CLKCTRL). */ +#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0) +/* @brief Has clock prescaler (register CLKPRESCALER). */ +#define FSL_FEATURE_EWM_HAS_PRESCALER (0) + +/* FLASH module features */ + +#if defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DX128VFT5) || \ + defined(CPU_MK20DX128VLF5) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (0) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (0) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (1) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x10000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (1) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (32768) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (1024) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (4) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (2048) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (1) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (4) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (4) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0x00008000) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0x00006000) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0x00004000) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0x00000000) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0x00000000) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0x00002000) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0x00004000) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0x00008000) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0x00008000) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) +#elif defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DN128VFT5) || \ + defined(CPU_MK20DN128VLF5) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (0) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (0) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (1) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (2048) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) +#elif defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DX64VFT5) || \ + defined(CPU_MK20DX64VLF5) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (0) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (0) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (1) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (65536) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x10000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (1) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (32768) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (1024) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (4) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (2048) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (1) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (4) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (4) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0x00008000) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0x00006000) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0x00004000) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0x00000000) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0x00000000) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0x00002000) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0x00004000) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0x00008000) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0x00008000) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) +#elif defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DN64VFT5) || \ + defined(CPU_MK20DN64VLF5) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (0) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (0) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (1) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (65536) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (2048) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) +#elif defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DX32VFT5) || \ + defined(CPU_MK20DX32VLF5) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (0) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (0) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (1) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (32768) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x10000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (1) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (32768) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (1024) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (4) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (2048) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (1) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (4) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (4) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0x00008000) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0x00006000) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0x00004000) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0x00000000) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0x00000000) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0x00002000) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0x00004000) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0x00008000) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0x00008000) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) +#elif defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DN32VLH5) || defined(CPU_MK20DN32VFT5) || \ + defined(CPU_MK20DN32VLF5) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (0) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (0) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (1) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (32768) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (2048) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) +#endif /* defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DX128VFT5) || \ + defined(CPU_MK20DX128VLF5) */ + +/* FTM module features */ + +/* @brief Number of channels. */ +#define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ + ((x) == FTM0 ? (8) : \ + ((x) == FTM1 ? (2) : (-1))) +/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ +#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) +/* @brief Enable pwm output for the module. */ +#define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0) +/* @brief Has half-cycle reload for the module. */ +#define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0) +/* @brief Has reload interrupt. */ +#define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0) +/* @brief Has reload initialization trigger. */ +#define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0) + +/* I2C module features */ + +/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ +#define FSL_FEATURE_I2C_HAS_SMBUS (1) +/* @brief Maximum supported baud rate in kilobit per second. */ +#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) +/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ +#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) +/* @brief Has DMA support (register bit C1[DMAEN]). */ +#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) +/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (0) +/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) +/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ +#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (0) +/* @brief Maximum width of the glitch filter in number of bus clocks. */ +#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (31) +/* @brief Has control of the drive capability of the I2C pins. */ +#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) +/* @brief Has double buffering support (register S2). */ +#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) + +/* SAI module features */ + +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +#define FSL_FEATURE_SAI_FIFO_COUNT (8) +/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ +#define FSL_FEATURE_SAI_CHANNEL_COUNT (2) +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ +#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0) +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0) +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0) +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ +#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1) +/* @brief Ihe interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) +/* @brief Has register of MCR. */ +#define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has register of MDR */ +#define FSL_FEATURE_SAI_HAS_MDR (1) + +/* LLWU module features */ + +#if defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ + defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) + /* @brief Maximum number of pins connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) + /* @brief Has pins 8-15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) + /* @brief Maximum number of internal modules connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) + /* @brief Number of digital filters. */ + #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) + /* @brief Has MF5 register. */ + #define FSL_FEATURE_LLWU_HAS_MF (0) + /* @brief Has PF register. */ + #define FSL_FEATURE_LLWU_HAS_PF (0) + /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ + #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1) + /* @brief Has external pin 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0) + /* @brief Has external pin 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0) + /* @brief Has external pin 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0) + /* @brief Has external pin 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) + /* @brief Has external pin 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0) + /* @brief Has external pin 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) + /* @brief Has external pin 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) + /* @brief Has external pin 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) + /* @brief Has external pin 8 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) + /* @brief Has external pin 9 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) + /* @brief Has external pin 10 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) + /* @brief Has external pin 11 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0) + /* @brief Has external pin 12 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) + /* @brief Has external pin 13 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (0) + /* @brief Has external pin 14 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) + /* @brief Has external pin 15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) + /* @brief Has external pin 16 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) + /* @brief Has external pin 17 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) + /* @brief Has external pin 18 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) + /* @brief Has external pin 19 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) + /* @brief Has external pin 20 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) + /* @brief Has external pin 21 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) + /* @brief Has external pin 22 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) + /* @brief Has external pin 23 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) + /* @brief Has external pin 24 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) + /* @brief Has external pin 25 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) + /* @brief Has external pin 26 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) + /* @brief Has external pin 27 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) + /* @brief Has external pin 28 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) + /* @brief Has external pin 29 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) + /* @brief Has external pin 30 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) + /* @brief Has external pin 31 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) + /* @brief Has internal module 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) + /* @brief Has internal module 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) + /* @brief Has internal module 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) + /* @brief Has internal module 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) + /* @brief Has internal module 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) + /* @brief Has internal module 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) + /* @brief Has internal module 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) + /* @brief Has internal module 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) + /* @brief Has Version ID Register (LLWU_VERID). */ + #define FSL_FEATURE_LLWU_HAS_VERID (0) + /* @brief Has Parameter Register (LLWU_PARAM). */ + #define FSL_FEATURE_LLWU_HAS_PARAM (0) + /* @brief Width of registers of the LLWU. */ + #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) + /* @brief Has DMA Enable register (LLWU_DE). */ + #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) +#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ + defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ + defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) + /* @brief Maximum number of pins connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) + /* @brief Has pins 8-15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) + /* @brief Maximum number of internal modules connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) + /* @brief Number of digital filters. */ + #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) + /* @brief Has MF5 register. */ + #define FSL_FEATURE_LLWU_HAS_MF (0) + /* @brief Has PF register. */ + #define FSL_FEATURE_LLWU_HAS_PF (0) + /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ + #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1) + /* @brief Has external pin 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) + /* @brief Has external pin 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0) + /* @brief Has external pin 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0) + /* @brief Has external pin 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) + /* @brief Has external pin 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) + /* @brief Has external pin 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) + /* @brief Has external pin 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) + /* @brief Has external pin 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) + /* @brief Has external pin 8 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) + /* @brief Has external pin 9 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) + /* @brief Has external pin 10 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) + /* @brief Has external pin 11 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) + /* @brief Has external pin 12 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) + /* @brief Has external pin 13 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) + /* @brief Has external pin 14 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) + /* @brief Has external pin 15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) + /* @brief Has external pin 16 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) + /* @brief Has external pin 17 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) + /* @brief Has external pin 18 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) + /* @brief Has external pin 19 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) + /* @brief Has external pin 20 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) + /* @brief Has external pin 21 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) + /* @brief Has external pin 22 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) + /* @brief Has external pin 23 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) + /* @brief Has external pin 24 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) + /* @brief Has external pin 25 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) + /* @brief Has external pin 26 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) + /* @brief Has external pin 27 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) + /* @brief Has external pin 28 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) + /* @brief Has external pin 29 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) + /* @brief Has external pin 30 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) + /* @brief Has external pin 31 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) + /* @brief Has internal module 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) + /* @brief Has internal module 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) + /* @brief Has internal module 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) + /* @brief Has internal module 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) + /* @brief Has internal module 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) + /* @brief Has internal module 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) + /* @brief Has internal module 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) + /* @brief Has internal module 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) + /* @brief Has Version ID Register (LLWU_VERID). */ + #define FSL_FEATURE_LLWU_HAS_VERID (0) + /* @brief Has Parameter Register (LLWU_PARAM). */ + #define FSL_FEATURE_LLWU_HAS_PARAM (0) + /* @brief Width of registers of the LLWU. */ + #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) + /* @brief Has DMA Enable register (LLWU_DE). */ + #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) +#elif defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ + defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ + defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) + /* @brief Maximum number of pins connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) + /* @brief Has pins 8-15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) + /* @brief Maximum number of internal modules connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) + /* @brief Number of digital filters. */ + #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) + /* @brief Has MF5 register. */ + #define FSL_FEATURE_LLWU_HAS_MF (0) + /* @brief Has PF register. */ + #define FSL_FEATURE_LLWU_HAS_PF (0) + /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ + #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1) + /* @brief Has external pin 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0) + /* @brief Has external pin 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0) + /* @brief Has external pin 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0) + /* @brief Has external pin 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) + /* @brief Has external pin 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0) + /* @brief Has external pin 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) + /* @brief Has external pin 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) + /* @brief Has external pin 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) + /* @brief Has external pin 8 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) + /* @brief Has external pin 9 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) + /* @brief Has external pin 10 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) + /* @brief Has external pin 11 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0) + /* @brief Has external pin 12 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) + /* @brief Has external pin 13 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) + /* @brief Has external pin 14 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) + /* @brief Has external pin 15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) + /* @brief Has external pin 16 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) + /* @brief Has external pin 17 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) + /* @brief Has external pin 18 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) + /* @brief Has external pin 19 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) + /* @brief Has external pin 20 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) + /* @brief Has external pin 21 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) + /* @brief Has external pin 22 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) + /* @brief Has external pin 23 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) + /* @brief Has external pin 24 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) + /* @brief Has external pin 25 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) + /* @brief Has external pin 26 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) + /* @brief Has external pin 27 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) + /* @brief Has external pin 28 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) + /* @brief Has external pin 29 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) + /* @brief Has external pin 30 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) + /* @brief Has external pin 31 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) + /* @brief Has internal module 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) + /* @brief Has internal module 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) + /* @brief Has internal module 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) + /* @brief Has internal module 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) + /* @brief Has internal module 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) + /* @brief Has internal module 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) + /* @brief Has internal module 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) + /* @brief Has internal module 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) + /* @brief Has Version ID Register (LLWU_VERID). */ + #define FSL_FEATURE_LLWU_HAS_VERID (0) + /* @brief Has Parameter Register (LLWU_PARAM). */ + #define FSL_FEATURE_LLWU_HAS_PARAM (0) + /* @brief Width of registers of the LLWU. */ + #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) + /* @brief Has DMA Enable register (LLWU_DE). */ + #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) +#endif /* defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ + defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) */ + +/* LPTMR module features */ + +/* No feature definitions */ + +/* MCG module features */ + +/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ +#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1) +/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ +#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24) +/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ +#define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) +/* @brief PLL reference clock low range. OSCCLK/PLL_R. */ +#define FSL_FEATURE_MCG_PLL_REF_MIN (2000000) +/* @brief PLL reference clock high range. OSCCLK/PLL_R. */ +#define FSL_FEATURE_MCG_PLL_REF_MAX (4000000) +/* @brief The PLL clock is divided by 2 before VCO divider. */ +#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) +/* @brief FRDIV supports 1280. */ +#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) +/* @brief FRDIV supports 1536. */ +#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) +/* @brief MCGFFCLK divider. */ +#define FSL_FEATURE_MCG_FFCLK_DIV (1) +/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ +#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) +/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ +#define FSL_FEATURE_MCG_HAS_RTC_32K (1) +/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ +#define FSL_FEATURE_MCG_HAS_PLL1 (0) +/* @brief Has 48MHz internal oscillator. */ +#define FSL_FEATURE_MCG_HAS_IRC_48M (0) +/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ +#define FSL_FEATURE_MCG_HAS_OSC1 (0) +/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ +#define FSL_FEATURE_MCG_HAS_FCFTRIM (0) +/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ +#define FSL_FEATURE_MCG_HAS_LOLRE (1) +/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ +#define FSL_FEATURE_MCG_USE_OSCSEL (1) +/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ +#define FSL_FEATURE_MCG_USE_PLLREFSEL (0) +/* @brief TBD */ +#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) +/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ +#define FSL_FEATURE_MCG_HAS_PLL (1) +/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ +#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1) +/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ +#define FSL_FEATURE_MCG_HAS_PLL_VDIV (1) +/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ +#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) +/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ +#define FSL_FEATURE_MCG_HAS_FLL (1) +/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ +#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) +/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ +#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) +/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ +#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) +/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ +#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) +/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ +#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) +/* @brief Has external clock monitor (register bit C6[CME]). */ +#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) +/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ +#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) +/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ +#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) +/* @brief Has PEI mode or PBI mode. */ +#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) +/* @brief Reset clock mode is BLPI. */ +#define FSL_FEATURE_MCG_RESET_IS_BLPI (0) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105) + +/* OSC module features */ + +/* @brief Has OSC1 external oscillator. */ +#define FSL_FEATURE_OSC_HAS_OSC1 (0) +/* @brief Has OSC0 external oscillator. */ +#define FSL_FEATURE_OSC_HAS_OSC0 (1) +/* @brief Has OSC external oscillator (without index). */ +#define FSL_FEATURE_OSC_HAS_OSC (0) +/* @brief Number of OSC external oscillators. */ +#define FSL_FEATURE_OSC_OSC_COUNT (1) +/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ +#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) + +/* PDB module features */ + +/* @brief Define the count of supporting ADC pre-trigger for each channel. */ +#define FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (2) +/* @brief Has DAC support. */ +#define FSL_FEATURE_PDB_HAS_DAC (0) +/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ +#define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0) + +/* PIT module features */ + +/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ +#define FSL_FEATURE_PIT_TIMER_COUNT (4) +/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ +#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0) +/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ +#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (0) +/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ +#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0) + +/* PMC module features */ + +/* @brief Has Bandgap Enable In VLPx Operation support. */ +#define FSL_FEATURE_PMC_HAS_BGEN (0) +/* @brief Has Bandgap Buffer Enable. */ +#define FSL_FEATURE_PMC_HAS_BGBE (1) +/* @brief Has Bandgap Buffer Drive Select. */ +#define FSL_FEATURE_PMC_HAS_BGBDS (0) +/* @brief Has Low-Voltage Detect Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVDV (1) +/* @brief Has Low-Voltage Warning Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVWV (1) +/* @brief Has LPO. */ +#define FSL_FEATURE_PMC_HAS_LPO (0) +/* @brief Has VLPx option PMC_REGSC[VLPO]. */ +#define FSL_FEATURE_PMC_HAS_VLPO (0) +/* @brief Has acknowledge isolation support. */ +#define FSL_FEATURE_PMC_HAS_ACKISO (1) +/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ +#define FSL_FEATURE_PMC_HAS_REGFPM (0) +/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ +#define FSL_FEATURE_PMC_HAS_REGONS (1) +/* @brief Has PMC_HVDSC1. */ +#define FSL_FEATURE_PMC_HAS_HVDSC1 (0) +/* @brief Has PMC_PARAM. */ +#define FSL_FEATURE_PMC_HAS_PARAM (0) +/* @brief Has PMC_VERID. */ +#define FSL_FEATURE_PMC_HAS_VERID (0) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) +/* @brief Has DMA request (register bit field PCR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Has separate drive strength register (HDRVE). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) +/* @brief Has glitch filter (register IOFLT). */ +#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (0) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* GPIO module features */ + +/* @brief Has fast (single cycle) access capability via a dedicated memory region. */ +#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0) +/* @brief Has port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) + +/* RCM module features */ + +/* @brief Has Loss-of-Lock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOL (1) +/* @brief Has Loss-of-Clock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOC (1) +/* @brief Has JTAG generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_JTAG (1) +/* @brief Has EzPort generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_EZPORT (1) +/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ +#define FSL_FEATURE_RCM_HAS_EZPMS (1) +/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ +#define FSL_FEATURE_RCM_HAS_BOOTROM (0) +/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ +#define FSL_FEATURE_RCM_HAS_SSRS (0) +/* @brief Has Version ID Register (RCM_VERID). */ +#define FSL_FEATURE_RCM_HAS_VERID (0) +/* @brief Has Parameter Register (RCM_PARAM). */ +#define FSL_FEATURE_RCM_HAS_PARAM (0) +/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ +#define FSL_FEATURE_RCM_HAS_SRIE (0) +/* @brief Width of registers of the RCM. */ +#define FSL_FEATURE_RCM_REG_WIDTH (8) +/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ +#define FSL_FEATURE_RCM_HAS_CORE1 (0) +/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ +#define FSL_FEATURE_RCM_HAS_MDM_AP (1) +/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ +#define FSL_FEATURE_RCM_HAS_WAKEUP (1) + +/* RTC module features */ + +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (0) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) + +/* SMC module features */ + +/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ +#define FSL_FEATURE_SMC_HAS_PSTOPO (0) +/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ +#define FSL_FEATURE_SMC_HAS_LPOPO (0) +/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ +#define FSL_FEATURE_SMC_HAS_PORPO (1) +/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ +#define FSL_FEATURE_SMC_HAS_LPWUI (1) +/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ +#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) +/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ +#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) +/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1) +/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) +/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ +#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) +/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ +#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ +#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has stop submode. */ +#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) +/* @brief Has stop submode 0(VLLS0). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) +/* @brief Has stop submode 2(VLLS2). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) +/* @brief Has SMC_PARAM. */ +#define FSL_FEATURE_SMC_HAS_PARAM (0) +/* @brief Has SMC_VERID. */ +#define FSL_FEATURE_SMC_HAS_VERID (0) + +/* DSPI module features */ + +#if defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ + defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) + /* @brief Receive/transmit FIFO size in number of items. */ + #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4) + /* @brief Maximum transfer data width in bits. */ + #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) + /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ + #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) + /* @brief Number of chip select pins. */ + #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (4) + /* @brief Has chip select strobe capability on the PCS5 pin. */ + #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) + /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ + #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) + /* @brief Has 16-bit data transfer support. */ + #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) + /* @brief Has separate DMA RX and TX requests. */ + #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +#elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ + defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ + defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ + defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ + defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ + defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) + /* @brief Receive/transmit FIFO size in number of items. */ + #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4) + /* @brief Maximum transfer data width in bits. */ + #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) + /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ + #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) + /* @brief Number of chip select pins. */ + #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5) + /* @brief Has chip select strobe capability on the PCS5 pin. */ + #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) + /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ + #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) + /* @brief Has 16-bit data transfer support. */ + #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) + /* @brief Has separate DMA RX and TX requests. */ + #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +#endif /* defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ + defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) */ + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* TSI module features */ + +/* @brief TSI module version. */ +#define FSL_FEATURE_TSI_VERSION (2) +/* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */ +#define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0) +/* @brief Number of TSI channels. */ +#define FSL_FEATURE_TSI_CHANNEL_COUNT (16) + +/* UART module features */ + +#if defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ + defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ + defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ + defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ + defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ + defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) + /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ + #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (0) + /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) + /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_HAS_FIFO (1) + /* @brief Hardware flow control (RTS, CTS) is supported. */ + #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) + /* @brief Infrared (modulation) is supported. */ + #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) + /* @brief 2 bits long stop bit is available. */ + #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) + /* @brief Baud rate fine adjustment is available. */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) + /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) + /* @brief Peripheral type. */ + #define FSL_FEATURE_UART_IS_SCI (0) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ + ((x) == UART0 ? (8) : \ + ((x) == UART1 ? (1) : \ + ((x) == UART2 ? (1) : (-1)))) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) + /* @brief Maximal data width with parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) + /* @brief Supports two match addresses to filter incoming frames. */ + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) + /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) + /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ + #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) + /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) + /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) + /* @brief Has improved smart card (ISO7816 protocol) support. */ + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) + /* @brief Has local operation network (CEA709.1-B protocol) support. */ + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (1) + /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ + #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) + /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ + #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) + /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ + #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) + /* @brief Has separate DMA RX and TX requests. */ + #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +#elif defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ + defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) + /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ + #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (0) + /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) + /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_HAS_FIFO (1) + /* @brief Hardware flow control (RTS, CTS) is supported. */ + #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) + /* @brief Infrared (modulation) is supported. */ + #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) + /* @brief 2 bits long stop bit is available. */ + #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) + /* @brief Baud rate fine adjustment is available. */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) + /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) + /* @brief Peripheral type. */ + #define FSL_FEATURE_UART_IS_SCI (0) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ + ((x) == UART0 ? (8) : \ + ((x) == UART1 ? (1) : (-1))) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) + /* @brief Maximal data width with parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) + /* @brief Supports two match addresses to filter incoming frames. */ + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) + /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) + /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ + #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) + /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) + /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) + /* @brief Has improved smart card (ISO7816 protocol) support. */ + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) + /* @brief Has local operation network (CEA709.1-B protocol) support. */ + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (1) + /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ + #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) + /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ + #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) + /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ + #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) + /* @brief Has separate DMA RX and TX requests. */ + #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +#endif /* defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ + defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ + defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ + defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ + defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ + defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) */ + +/* USB module features */ + +/* @brief HOST mode enabled */ +#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) +/* @brief OTG mode enabled */ +#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM (0) +/* @brief Has KEEP_ALIVE_CTRL register */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) +/* @brief Has the Dynamic SOF threshold compare support */ +#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0) +/* @brief Has the VBUS detect support */ +#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) +/* @brief Has the IRC48M module clock support */ +#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (0) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USB_ENDPT_COUNT (16) + +/* VREF module features */ + +#if defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ + defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ + defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ + defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ + defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ + defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) + /* @brief Has chop oscillator (bit TRM[CHOPEN]) */ + #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) + /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ + #define FSL_FEATURE_VREF_HAS_COMPENSATION (0) + /* @brief If high/low buffer mode supported */ + #define FSL_FEATURE_VREF_MODE_LV_TYPE (0) + /* @brief Module has also low reference (registers VREFL/VREFH) */ + #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) + /* @brief Has VREF_TRM4. */ + #define FSL_FEATURE_VREF_HAS_TRM4 (0) +#endif /* defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ + defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ + defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ + defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ + defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ + defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) */ + +/* WDOG module features */ + +/* @brief Watchdog is available. */ +#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) +/* @brief Has Wait mode support. */ +#define FSL_FEATURE_WDOG_HAS_WAITEN (1) + +#endif /* _MK20D5_FEATURES_H_ */ +
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k20dx/MK20D5/fsl_device_registers.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/freescale/k20dx/MK20D5/fsl_device_registers.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || \ + defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \ + defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || \ + defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ + defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || \ + defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \ + defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || \ + defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ + defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || \ + defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5)) + +#define K20D5_SERIES + +/* CMSIS-style register definitions */ +#include "MK20D5.h" +/* CPU specific feature definitions */ +#include "MK20D5_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k20dx/MK20D5/system_MK20D5.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k20dx/MK20D5/system_MK20D5.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,284 @@
+/*
+** ###################################################################
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011
+** K20P32M50SF0RM Rev. 1, Oct 2011
+** K20P48M50SF0RM Rev. 1, Oct 2011
+**
+** Version: rev. 1.0, 2011-12-15
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2011-12-15)
+** Initial version
+**
+** ###################################################################
+*/
+
+/**
+ * @file MK20D5
+ * @version 1.0
+ * @date 2011-12-15
+ * @brief Device specific configuration file for MK20D5 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include "stdint.h"
+#include "MK20D5.h"
+
+#define DISABLE_WDOG 1
+
+#define CLOCK_SETUP 1
+/* Predefined clock setups
+ 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
+ Reference clock source for MCG module is the slow internal clock source 32.768kHz
+ Core clock = 41.94MHz, BusClock = 41.94MHz
+ 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
+ Reference clock source for MCG module is an external crystal 8MHz
+ Core clock = 48MHz, BusClock = 48MHz
+ 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
+ Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
+ Core clock = 8MHz, BusClock = 8MHz
+*/
+
+/*----------------------------------------------------------------------------
+ Define clock source values
+ *----------------------------------------------------------------------------*/
+#if (CLOCK_SETUP == 0)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
+#elif (CLOCK_SETUP == 1)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
+#elif (CLOCK_SETUP == 2)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
+#endif /* (CLOCK_SETUP == 2) */
+
+
+/* ----------------------------------------------------------------------------
+ -- Core clock
+ ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+ -- SystemInit()
+ ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if (DISABLE_WDOG)
+ /* Disable the WDOG module */
+ /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
+ WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */
+ /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
+ WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */
+ /* WDOG_STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
+ WDOG->STCTRLH = (uint16_t)0x01D2u;
+#endif /* (DISABLE_WDOG) */
+#if (CLOCK_SETUP == 0)
+ /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */
+ SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
+ /* Switch to FEI Mode */
+ /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x06u;
+ /* MCG->C2: ?=0,?=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */
+ MCG->C2 = (uint8_t)0x00u;
+ /* MCG_C4: DMX32=0,DRST_DRS=1 */
+ MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u);
+ /* MCG->C5: ?=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
+ MCG->C5 = (uint8_t)0x00u;
+ /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00u;
+ while((MCG->S & MCG_S_IREFST_MASK) == 0u) { /* Check that the source of the FLL reference clock is the internal reference clock. */
+ }
+ while((MCG->S & 0x0Cu) != 0x00u) { /* Wait until output of the FLL is selected */
+ }
+#elif (CLOCK_SETUP == 1)
+ /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */
+ SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
+ /* Switch to FBE Mode */
+ /* OSC0->CR: ERCLKEN=0,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ OSC0->CR = (uint8_t)0x00u;
+ /* MCG->C7: OSCSEL=0 */
+ MCG->C7 = (uint8_t)0x00u;
+ /* MCG->C2: ?=0,?=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+ MCG->C2 = (uint8_t)0x24u;
+ /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x9Au;
+ /* MCG->C4: DMX32=0,DRST_DRS=0 */
+ MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
+ /* MCG->C5: ?=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
+ MCG->C5 = (uint8_t)0x03u;
+ /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00u;
+ while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
+ }
+#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
+ while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
+ }
+#endif
+ while((MCG->S & 0x0Cu) != 0x08u) { /* Wait until external reference clock is selected as MCG output */
+ }
+ /* Switch to PBE Mode */
+ /* MCG_C5: ?=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
+ MCG->C5 = (uint8_t)0x03u;
+ /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x40u;
+ while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */
+ }
+ while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
+ }
+ /* Switch to PEE Mode */
+ /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x1Au;
+ while((MCG->S & 0x0Cu) != 0x0Cu) { /* Wait until output of the PLL is selected */
+ }
+ while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
+ }
+#elif (CLOCK_SETUP == 2)
+ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */
+ SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
+ /* Switch to FBE Mode */
+ /* OSC0->CR: ERCLKEN=0,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ OSC0->CR = (uint8_t)0x00u;
+ /* MCG->C7: OSCSEL=0 */
+ MCG->C7 = (uint8_t)0x00u;
+ /* MCG->C2: ?=0,?=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+ MCG->C2 = (uint8_t)0x24u;
+ /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x9Au;
+ /* MCG->C4: DMX32=0,DRST_DRS=0 */
+ MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
+ /* MCG->C5: ?=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
+ MCG->C5 = (uint8_t)0x00u;
+ /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00u;
+ while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
+ }
+#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
+ while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
+ }
+#endif
+ while((MCG->S & 0x0CU) != 0x08u) { /* Wait until external reference clock is selected as MCG output */
+ }
+ /* Switch to BLPE Mode */
+ /* MCG->C2: ?=0,?=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+ MCG->C2 = (uint8_t)0x24u;
+#endif /* (CLOCK_SETUP == 2) */
+
+#if defined(OFFSET_VTABLE_32K)
+ SCB->VTOR = 0x8000u;
+#elif defined(OFFSET_VTABLE_20K)
+ SCB->VTOR = 0x5000u;
+#endif
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemCoreClockUpdate()
+ ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+ uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+ uint8_t Divider;
+
+ if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
+ /* Output of FLL or PLL is selected */
+ if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
+ /* FLL is selected */
+ if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
+ /* External reference clock is selected */
+ if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+ } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+ Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+ MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+ if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
+ MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
+ } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
+ } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+ } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+ /* Select correct multiplier to calculate the MCG output clock */
+ switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+ case 0x0u:
+ MCGOUTClock *= 640u;
+ break;
+ case 0x20u:
+ MCGOUTClock *= 1280u;
+ break;
+ case 0x40u:
+ MCGOUTClock *= 1920u;
+ break;
+ case 0x60u:
+ MCGOUTClock *= 2560u;
+ break;
+ case 0x80u:
+ MCGOUTClock *= 732u;
+ break;
+ case 0xA0u:
+ MCGOUTClock *= 1464u;
+ break;
+ case 0xC0u:
+ MCGOUTClock *= 2197u;
+ break;
+ case 0xE0u:
+ MCGOUTClock *= 2929u;
+ break;
+ default:
+ break;
+ }
+ } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+ /* PLL is selected */
+ Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
+ MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+ Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
+ MCGOUTClock *= Divider; /* Calculate the MCG output clock */
+ } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
+ /* Internal reference clock is selected */
+ if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+ } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
+ } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
+ /* External reference clock is selected */
+ if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+ } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+ } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+ /* Reserved value */
+ return;
+ } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+ SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k20dx/MK20D5/system_MK20D5.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k20dx/MK20D5/system_MK20D5.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,87 @@
+/*
+** ###################################################################
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011
+** K20P32M50SF0RM Rev. 1, Oct 2011
+** K20P48M50SF0RM Rev. 1, Oct 2011
+**
+** Version: rev. 2.0, 2012-03-19
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2011-12-15)
+** Initial version
+** - rev. 2.0 (2012-03-19)
+** PDB Peripheral register structure updated.
+** DMA Registers and bits for unsupported DMA channels removed.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MK20D5
+ * @version 2.0
+ * @date 2012-03-19
+ * @brief Device specific configuration file for MK20D5 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MK20D5_H_
+#define SYSTEM_MK20D5_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "stdint.h"
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if !defined(SYSTEM_MK20D5_H_) */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k20dx/armcc/startup_MK20D5.s --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/freescale/k20dx/armcc/startup_MK20D5.s Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,664 @@ +;/** +; * @file startup_MK20D5.s +; * @brief +; * +; * DAPLink Interface Firmware +; * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x0000100 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT g_board_info +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD DAPLINK_BUILD_KEY ; Build type - BL/IF + DCD DAPLINK_HIC_ID ; Compatibility + DCD DAPLINK_VERSION ; Version + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD g_board_info ; Ptr to Board info, family info other target details + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt + DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt + DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt + DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt + DCD DMA_Error_IRQHandler ; DMA error interrupt + DCD Reserved21_IRQHandler ; Reserved interrupt 21 + DCD FTFL_IRQHandler ; FTFL interrupt + DCD Read_Collision_IRQHandler ; Read collision interrupt + DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning + DCD LLW_IRQHandler ; Low Leakage Wakeup + DCD Watchdog_IRQHandler ; WDOG interrupt + DCD I2C0_IRQHandler ; I2C0 interrupt + DCD SPI0_IRQHandler ; SPI0 interrupt + DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt + DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt + DCD UART0_LON_IRQHandler ; UART0 LON interrupt + DCD UART0_RX_TX_IRQHandler ; UART0 receive/transmit interrupt + DCD UART0_ERR_IRQHandler ; UART0 error interrupt + DCD UART1_RX_TX_IRQHandler ; UART1 receive/transmit interrupt + DCD UART1_ERR_IRQHandler ; UART1 error interrupt + DCD UART2_RX_TX_IRQHandler ; UART2 receive/transmit interrupt + DCD UART2_ERR_IRQHandler ; UART2 error interrupt + DCD ADC0_IRQHandler ; ADC0 interrupt + DCD CMP0_IRQHandler ; CMP0 interrupt + DCD CMP1_IRQHandler ; CMP1 interrupt + DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt + DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt + DCD CMT_IRQHandler ; CMT interrupt + DCD RTC_IRQHandler ; RTC interrupt + DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt + DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt + DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt + DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt + DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt + DCD PDB0_IRQHandler ; PDB0 interrupt + DCD USB0_IRQHandler ; USB0 interrupt + DCD USBDCD_IRQHandler ; USBDCD interrupt + DCD TSI0_IRQHandler ; TSI0 interrupt + DCD MCG_IRQHandler ; MCG interrupt + DCD LPTimer_IRQHandler ; LPTimer interrupt + DCD PORTA_IRQHandler ; Port A interrupt + DCD PORTB_IRQHandler ; Port B interrupt + DCD PORTC_IRQHandler ; Port C interrupt + DCD PORTD_IRQHandler ; Port D interrupt + DCD PORTE_IRQHandler ; Port E interrupt + DCD SWI_IRQHandler ; Software interrupt + DCD DefaultISR ; 62 + DCD DefaultISR ; 63 + DCD DefaultISR ; 64 + DCD DefaultISR ; 65 + DCD DefaultISR ; 66 + DCD DefaultISR ; 67 + DCD DefaultISR ; 68 + DCD DefaultISR ; 69 + DCD DefaultISR ; 70 + DCD DefaultISR ; 71 + DCD DefaultISR ; 72 + DCD DefaultISR ; 73 + DCD DefaultISR ; 74 + DCD DefaultISR ; 75 + DCD DefaultISR ; 76 + DCD DefaultISR ; 77 + DCD DefaultISR ; 78 + DCD DefaultISR ; 79 + DCD DefaultISR ; 80 + DCD DefaultISR ; 81 + DCD DefaultISR ; 82 + DCD DefaultISR ; 83 + DCD DefaultISR ; 84 + DCD DefaultISR ; 85 + DCD DefaultISR ; 86 + DCD DefaultISR ; 87 + DCD DefaultISR ; 88 + DCD DefaultISR ; 89 + DCD DefaultISR ; 90 + DCD DefaultISR ; 91 + DCD DefaultISR ; 92 + DCD DefaultISR ; 93 + DCD DefaultISR ; 94 + DCD DefaultISR ; 95 + DCD DefaultISR ; 96 + DCD DefaultISR ; 97 + DCD DefaultISR ; 98 + DCD DefaultISR ; 99 + DCD DefaultISR ; 100 + DCD DefaultISR ; 101 + DCD DefaultISR ; 102 + DCD DefaultISR ; 103 + DCD DefaultISR ; 104 + DCD DefaultISR ; 105 + DCD DefaultISR ; 106 + DCD DefaultISR ; 107 + DCD DefaultISR ; 108 + DCD DefaultISR ; 109 + DCD DefaultISR ; 110 + DCD DefaultISR ; 111 + DCD DefaultISR ; 112 + DCD DefaultISR ; 113 + DCD DefaultISR ; 114 + DCD DefaultISR ; 115 + DCD DefaultISR ; 116 + DCD DefaultISR ; 117 + DCD DefaultISR ; 118 + DCD DefaultISR ; 119 + DCD DefaultISR ; 120 + DCD DefaultISR ; 121 + DCD DefaultISR ; 122 + DCD DefaultISR ; 123 + DCD DefaultISR ; 124 + DCD DefaultISR ; 125 + DCD DefaultISR ; 126 + DCD DefaultISR ; 127 + DCD DefaultISR ; 128 + DCD DefaultISR ; 129 + DCD DefaultISR ; 130 + DCD DefaultISR ; 131 + DCD DefaultISR ; 132 + DCD DefaultISR ; 133 + DCD DefaultISR ; 134 + DCD DefaultISR ; 135 + DCD DefaultISR ; 136 + DCD DefaultISR ; 137 + DCD DefaultISR ; 138 + DCD DefaultISR ; 139 + DCD DefaultISR ; 140 + DCD DefaultISR ; 141 + DCD DefaultISR ; 142 + DCD DefaultISR ; 143 + DCD DefaultISR ; 144 + DCD DefaultISR ; 145 + DCD DefaultISR ; 146 + DCD DefaultISR ; 147 + DCD DefaultISR ; 148 + DCD DefaultISR ; 149 + DCD DefaultISR ; 150 + DCD DefaultISR ; 151 + DCD DefaultISR ; 152 + DCD DefaultISR ; 153 + DCD DefaultISR ; 154 + DCD DefaultISR ; 155 + DCD DefaultISR ; 156 + DCD DefaultISR ; 157 + DCD DefaultISR ; 158 + DCD DefaultISR ; 159 + DCD DefaultISR ; 160 + DCD DefaultISR ; 161 + DCD DefaultISR ; 162 + DCD DefaultISR ; 163 + DCD DefaultISR ; 164 + DCD DefaultISR ; 165 + DCD DefaultISR ; 166 + DCD DefaultISR ; 167 + DCD DefaultISR ; 168 + DCD DefaultISR ; 169 + DCD DefaultISR ; 170 + DCD DefaultISR ; 171 + DCD DefaultISR ; 172 + DCD DefaultISR ; 173 + DCD DefaultISR ; 174 + DCD DefaultISR ; 175 + DCD DefaultISR ; 176 + DCD DefaultISR ; 177 + DCD DefaultISR ; 178 + DCD DefaultISR ; 179 + DCD DefaultISR ; 180 + DCD DefaultISR ; 181 + DCD DefaultISR ; 182 + DCD DefaultISR ; 183 + DCD DefaultISR ; 184 + DCD DefaultISR ; 185 + DCD DefaultISR ; 186 + DCD DefaultISR ; 187 + DCD DefaultISR ; 188 + DCD DefaultISR ; 189 + DCD DefaultISR ; 190 + DCD DefaultISR ; 191 + DCD DefaultISR ; 192 + DCD DefaultISR ; 193 + DCD DefaultISR ; 194 + DCD DefaultISR ; 195 + DCD DefaultISR ; 196 + DCD DefaultISR ; 197 + DCD DefaultISR ; 198 + DCD DefaultISR ; 199 + DCD DefaultISR ; 200 + DCD DefaultISR ; 201 + DCD DefaultISR ; 202 + DCD DefaultISR ; 203 + DCD DefaultISR ; 204 + DCD DefaultISR ; 205 + DCD DefaultISR ; 206 + DCD DefaultISR ; 207 + DCD DefaultISR ; 208 + DCD DefaultISR ; 209 + DCD DefaultISR ; 210 + DCD DefaultISR ; 211 + DCD DefaultISR ; 212 + DCD DefaultISR ; 213 + DCD DefaultISR ; 214 + DCD DefaultISR ; 215 + DCD DefaultISR ; 216 + DCD DefaultISR ; 217 + DCD DefaultISR ; 218 + DCD DefaultISR ; 219 + DCD DefaultISR ; 220 + DCD DefaultISR ; 221 + DCD DefaultISR ; 222 + DCD DefaultISR ; 223 + DCD DefaultISR ; 224 + DCD DefaultISR ; 225 + DCD DefaultISR ; 226 + DCD DefaultISR ; 227 + DCD DefaultISR ; 228 + DCD DefaultISR ; 229 + DCD DefaultISR ; 230 + DCD DefaultISR ; 231 + DCD DefaultISR ; 232 + DCD DefaultISR ; 233 + DCD DefaultISR ; 234 + DCD DefaultISR ; 235 + DCD DefaultISR ; 236 + DCD DefaultISR ; 237 + DCD DefaultISR ; 238 + DCD DefaultISR ; 239 + DCD DefaultISR ; 240 + DCD DefaultISR ; 241 + DCD DefaultISR ; 242 + DCD DefaultISR ; 243 + DCD DefaultISR ; 244 + DCD DefaultISR ; 245 + DCD DefaultISR ; 246 + DCD DefaultISR ; 247 + DCD DefaultISR ; 248 + DCD DefaultISR ; 249 + DCD DefaultISR ; 250 + DCD DefaultISR ; 251 + DCD DefaultISR ; 252 + DCD DefaultISR ; 253 + DCD DefaultISR ; 254 + DCD DefaultISR ; 255 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +; <h> Flash Configuration +; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset) +; <i> and security information that allows the MCU to restrict acces to the FTFL module. +; <h> Backdoor Comparison Key +; <o0> Backdoor Key 0 <0x0-0xFF:2> +; <o1> Backdoor Key 1 <0x0-0xFF:2> +; <o2> Backdoor Key 2 <0x0-0xFF:2> +; <o3> Backdoor Key 3 <0x0-0xFF:2> +; <o4> Backdoor Key 4 <0x0-0xFF:2> +; <o5> Backdoor Key 5 <0x0-0xFF:2> +; <o6> Backdoor Key 6 <0x0-0xFF:2> +; <o7> Backdoor Key 7 <0x0-0xFF:2> +BackDoorK0 EQU 0xFF +BackDoorK1 EQU 0xFF +BackDoorK2 EQU 0xFF +BackDoorK3 EQU 0xFF +BackDoorK4 EQU 0xFF +BackDoorK5 EQU 0xFF +BackDoorK6 EQU 0xFF +BackDoorK7 EQU 0xFF +; </h> +; <h> Program flash protection bytes (FPROT) +; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit. +; <i> Each bit protects a 1/32 region of the program flash memory. +; <h> FPROT0 +; <i> Program flash protection bytes +; <i> 1/32 - 8/32 region +; <o.0> FPROT0.0 +; <o.1> FPROT0.1 +; <o.2> FPROT0.2 +; <o.3> FPROT0.3 +; <o.4> FPROT0.4 +; <o.5> FPROT0.5 +; <o.6> FPROT0.6 +; <o.7> FPROT0.7 +nFPROT0 EQU 0x00 +FPROT0 EQU nFPROT0:EOR:0xFF +; </h> +; <h> FPROT1 +; <i> Program Flash Region Protect Register 1 +; <i> 9/32 - 16/32 region +; <o.0> FPROT1.0 +; <o.1> FPROT1.1 +; <o.2> FPROT1.2 +; <o.3> FPROT1.3 +; <o.4> FPROT1.4 +; <o.5> FPROT1.5 +; <o.6> FPROT1.6 +; <o.7> FPROT1.7 +nFPROT1 EQU 0x00 +FPROT1 EQU nFPROT1:EOR:0xFF +; </h> +; <h> FPROT2 +; <i> Program Flash Region Protect Register 2 +; <i> 17/32 - 24/32 region +; <o.0> FPROT2.0 +; <o.1> FPROT2.1 +; <o.2> FPROT2.2 +; <o.3> FPROT2.3 +; <o.4> FPROT2.4 +; <o.5> FPROT2.5 +; <o.6> FPROT2.6 +; <o.7> FPROT2.7 +nFPROT2 EQU 0x00 +FPROT2 EQU nFPROT2:EOR:0xFF +; </h> +; <h> FPROT3 +; <i> Program Flash Region Protect Register 3 +; <i> 25/32 - 32/32 region +; <o.0> FPROT3.0 +; <o.1> FPROT3.1 +; <o.2> FPROT3.2 +; <o.3> FPROT3.3 +; <o.4> FPROT3.4 +; <o.5> FPROT3.5 +; <o.6> FPROT3.6 +; <o.7> FPROT3.7 +nFPROT3 EQU 0x00 +FPROT3 EQU nFPROT3:EOR:0xFF +; </h> +; </h> +; <h> Data flash protection byte (FDPROT) +; <i> Each bit protects a 1/8 region of the data flash memory. +; <i> (Program flash only devices: Reserved) +; <o.0> FDPROT.0 +; <o.1> FDPROT.1 +; <o.2> FDPROT.2 +; <o.3> FDPROT.3 +; <o.4> FDPROT.4 +; <o.5> FDPROT.5 +; <o.6> FDPROT.6 +; <o.7> FDPROT.7 +nFDPROT EQU 0x00 +FDPROT EQU nFDPROT:EOR:0xFF +; </h> +; <h> EEPROM protection byte (FEPROT) +; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM. +; <i> (Program flash only devices: Reserved) +; <o.0> FEPROT.0 +; <o.1> FEPROT.1 +; <o.2> FEPROT.2 +; <o.3> FEPROT.3 +; <o.4> FEPROT.4 +; <o.5> FEPROT.5 +; <o.6> FEPROT.6 +; <o.7> FEPROT.7 +nFEPROT EQU 0x00 +FEPROT EQU nFEPROT:EOR:0xFF +; </h> +; <h> Flash nonvolatile option byte (FOPT) +; <i> Allows the user to customize the operation of the MCU at boot time. +; <o.0> LPBOOT +; <0=> Low-power boot +; <1=> normal boot +; <o.1> EZPORT_DIS +; <0=> EzPort operation is enabled +; <1=> EzPort operation is disabled +FOPT EQU 0xFD +; </h> +; <h> Flash security byte (FSEC) +; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", +; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! +; <o.0..1> SEC +; <2=> MCU security status is unsecure +; <3=> MCU security status is secure +; <i> Flash Security +; <i> This bits define the security state of the MCU. +; <o.2..3> FSLACC +; <2=> Freescale factory access denied +; <3=> Freescale factory access granted +; <i> Freescale Failure Analysis Access Code +; <i> This bits define the security state of the MCU. +; <o.4..5> MEEN +; <2=> Mass erase is disabled +; <3=> Mass erase is enabled +; <i> Mass Erase Enable Bits +; <i> Enables and disables mass erase capability of the FTFL module +; <o.6..7> KEYEN +; <2=> Backdoor key access enabled +; <3=> Backdoor key access disabled +; <i> Backdoor key Security Enable +; <i> These bits enable and disable backdoor key access to the FTFL module. +FSEC EQU 0xFE +; </h> +; </h> + #if defined(DAPLINK_IF) + AREA |.ARM.__at_0x8400|, CODE, READONLY + #else + AREA |.ARM.__at_0x400 |, CODE, READONLY + #endif + + DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 + DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 + DCB FPROT0, FPROT1, FPROT2, FPROT3 + DCB FSEC, FOPT, FEPROT, FDPROT + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DMA0_IRQHandler [WEAK] + EXPORT DMA1_IRQHandler [WEAK] + EXPORT DMA2_IRQHandler [WEAK] + EXPORT DMA3_IRQHandler [WEAK] + EXPORT DMA_Error_IRQHandler [WEAK] + EXPORT Reserved21_IRQHandler [WEAK] + EXPORT FTFL_IRQHandler [WEAK] + EXPORT Read_Collision_IRQHandler [WEAK] + EXPORT LVD_LVW_IRQHandler [WEAK] + EXPORT LLW_IRQHandler [WEAK] + EXPORT Watchdog_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT I2S0_Tx_IRQHandler [WEAK] + EXPORT I2S0_Rx_IRQHandler [WEAK] + EXPORT UART0_LON_IRQHandler [WEAK] + EXPORT UART0_RX_TX_IRQHandler [WEAK] + EXPORT UART0_ERR_IRQHandler [WEAK] + EXPORT UART1_RX_TX_IRQHandler [WEAK] + EXPORT UART1_ERR_IRQHandler [WEAK] + EXPORT UART2_RX_TX_IRQHandler [WEAK] + EXPORT UART2_ERR_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT FTM0_IRQHandler [WEAK] + EXPORT FTM1_IRQHandler [WEAK] + EXPORT CMT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT RTC_Seconds_IRQHandler [WEAK] + EXPORT PIT0_IRQHandler [WEAK] + EXPORT PIT1_IRQHandler [WEAK] + EXPORT PIT2_IRQHandler [WEAK] + EXPORT PIT3_IRQHandler [WEAK] + EXPORT PDB0_IRQHandler [WEAK] + EXPORT USB0_IRQHandler [WEAK] + EXPORT USBDCD_IRQHandler [WEAK] + EXPORT TSI0_IRQHandler [WEAK] + EXPORT MCG_IRQHandler [WEAK] + EXPORT LPTimer_IRQHandler [WEAK] + EXPORT PORTA_IRQHandler [WEAK] + EXPORT PORTB_IRQHandler [WEAK] + EXPORT PORTC_IRQHandler [WEAK] + EXPORT PORTD_IRQHandler [WEAK] + EXPORT PORTE_IRQHandler [WEAK] + EXPORT SWI_IRQHandler [WEAK] + EXPORT DefaultISR [WEAK] + +DMA0_IRQHandler +DMA1_IRQHandler +DMA2_IRQHandler +DMA3_IRQHandler +DMA_Error_IRQHandler +Reserved21_IRQHandler +FTFL_IRQHandler +Read_Collision_IRQHandler +LVD_LVW_IRQHandler +LLW_IRQHandler +Watchdog_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +I2S0_Tx_IRQHandler +I2S0_Rx_IRQHandler +UART0_LON_IRQHandler +UART0_RX_TX_IRQHandler +UART0_ERR_IRQHandler +UART1_RX_TX_IRQHandler +UART1_ERR_IRQHandler +UART2_RX_TX_IRQHandler +UART2_ERR_IRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +FTM0_IRQHandler +FTM1_IRQHandler +CMT_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT0_IRQHandler +PIT1_IRQHandler +PIT2_IRQHandler +PIT3_IRQHandler +PDB0_IRQHandler +USB0_IRQHandler +USBDCD_IRQHandler +TSI0_IRQHandler +MCG_IRQHandler +LPTimer_IRQHandler +PORTA_IRQHandler +PORTB_IRQHandler +PORTC_IRQHandler +PORTD_IRQHandler +PORTE_IRQHandler +SWI_IRQHandler +DefaultISR + + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k20dx/daplink_addr.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/freescale/k20dx/daplink_addr.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,82 @@ +/** + * @file daplink_addr.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef DAPLINK_ADDR_H +#define DAPLINK_ADDR_H + +/* Device sizes */ + +#define DAPLINK_ROM_START 0x00000000 +#define DAPLINK_ROM_SIZE 0x00020000 + +#define DAPLINK_RAM_START 0x1FFFE000 +#define DAPLINK_RAM_SIZE 0x00004000 + +/* ROM sizes */ + +#define DAPLINK_ROM_BL_START 0x00000000 +#define DAPLINK_ROM_BL_SIZE 0x00008000 + +#define DAPLINK_ROM_CONFIG_ADMIN_START 0x00008000 +#define DAPLINK_ROM_CONFIG_ADMIN_SIZE 0x00000000 + +#define DAPLINK_ROM_IF_START 0x00008000 +#define DAPLINK_ROM_IF_SIZE 0x00017C00 + +#define DAPLINK_ROM_CONFIG_USER_START 0x0001FC00 +#define DAPLINK_ROM_CONFIG_USER_SIZE 0x00000400 + +/* RAM sizes */ + +#define DAPLINK_RAM_APP_START 0x1FFFE000 +#define DAPLINK_RAM_APP_SIZE 0x00003F00 + +#define DAPLINK_RAM_SHARED_START 0x20001F00 +#define DAPLINK_RAM_SHARED_SIZE 0x00000100 + +/* Flash Programming Info */ + +#define DAPLINK_SECTOR_SIZE 0x00000400 +#define DAPLINK_MIN_WRITE_SIZE 0x00000100 + +/* Current build */ + +#if defined(DAPLINK_BL) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_BL_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_IF_SIZE + +#elif defined(DAPLINK_IF) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_IF_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_BL_SIZE + +#else + +#error "Build must be either bootloader or interface" + +#endif + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k20dx/gpio.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k20dx/gpio.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,114 @@
+/**
+ * @file gpio.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "MK20D5.h"
+#include "DAP_config.h"
+#include "gpio.h"
+#include "daplink.h"
+
+static void busy_wait(uint32_t cycles)
+{
+ volatile uint32_t i;
+ i = cycles;
+
+ while (i > 0) {
+ i--;
+ }
+}
+
+void gpio_init(void)
+{
+ // Enable hardfault on unaligned access for the interface only.
+ // If this is done in the bootloader than then it might (will) break
+ // older application firmware or firmware from 3rd party vendors.
+#if defined(DAPLINK_IF)
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+ // enable clock to ports
+ SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTB_MASK;
+ // configure pin as GPIO
+ LED_CONNECTED_PORT->PCR[LED_CONNECTED_BIT] = PORT_PCR_MUX(1);
+ // led off - enable output
+ LED_CONNECTED_GPIO->PDOR = 1UL << LED_CONNECTED_BIT;
+ LED_CONNECTED_GPIO->PDDR = 1UL << LED_CONNECTED_BIT;
+ // led on
+ LED_CONNECTED_GPIO->PCOR = 1UL << LED_CONNECTED_BIT;
+ // reset button configured as gpio input
+ PIN_nRESET_GPIO->PDDR &= ~PIN_nRESET;
+ PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_MUX(1);
+
+ // configure pin as GPIO
+ PIN_POWER_EN_PORT->PCR[PIN_POWER_EN_BIT] = PORT_PCR_MUX(1);
+ // set output to 0
+ PIN_POWER_EN_GPIO->PCOR = PIN_POWER_EN;
+ // switch gpio to output
+ PIN_POWER_EN_GPIO->PDDR |= PIN_POWER_EN;
+
+ // Let the voltage rails stabilize. This is especailly important
+ // during software resets, since the target's 3.3v rail can take
+ // 20-50ms to drain. During this time the target could be driving
+ // the reset pin low, causing the bootloader to think the reset
+ // button is pressed.
+ // Note: With optimization set to -O2 the value 1000000 delays for ~85ms
+ busy_wait(1000000);
+}
+
+void gpio_set_board_power(bool powerEnabled)
+{
+ if (powerEnabled) {
+ // enable power switch
+ PIN_POWER_EN_GPIO->PSOR = PIN_POWER_EN;
+ }
+ else {
+ // disable power switch
+ PIN_POWER_EN_GPIO->PCOR = PIN_POWER_EN;
+ }
+}
+
+void gpio_set_hid_led(gpio_led_state_t state)
+{
+ if (state) {
+ LED_CONNECTED_GPIO->PCOR = 1UL << LED_CONNECTED_BIT; // LED on
+ } else {
+ LED_CONNECTED_GPIO->PSOR = 1UL << LED_CONNECTED_BIT; // LED off
+ }
+}
+
+void gpio_set_cdc_led(gpio_led_state_t state)
+{
+ gpio_set_hid_led(state);
+}
+
+void gpio_set_msc_led(gpio_led_state_t state)
+{
+ gpio_set_hid_led(state);
+}
+
+uint8_t gpio_get_reset_btn_no_fwrd(void)
+{
+ return (PIN_nRESET_GPIO->PDIR & PIN_nRESET) ? 0 : 1;
+
+}
+
+uint8_t gpio_get_reset_btn_fwrd(void)
+{
+ return 0;
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k20dx/read_uid.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k20dx/read_uid.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,31 @@
+/**
+ * @file read_uid.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "MK20D5.h"
+#include "read_uid.h"
+
+void read_unique_id(uint32_t *id)
+{
+ id[0] = SIM->UIDL;
+ id[1] = SIM->UIDML;
+ id[2] = SIM->UIDMH;
+ id[3] = SIM->UIDH;
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k20dx/uart.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k20dx/uart.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,247 @@
+/**
+ * @file uart.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "string.h"
+
+#include "MK20D5.h"
+#include "uart.h"
+#include "util.h"
+#include "cortex_m.h"
+#include "circ_buf.h"
+#include "settings.h" // for config_get_overflow_detect
+
+extern uint32_t SystemCoreClock;
+
+static void clear_buffers(void);
+
+#define RX_OVRF_MSG "<DAPLink:Overflow>\n"
+#define RX_OVRF_MSG_SIZE (sizeof(RX_OVRF_MSG) - 1)
+#define BUFFER_SIZE (512)
+
+
+circ_buf_t write_buffer;
+uint8_t write_buffer_data[BUFFER_SIZE];
+circ_buf_t read_buffer;
+uint8_t read_buffer_data[BUFFER_SIZE];
+
+void clear_buffers(void)
+{
+ util_assert(!(UART1->C2 & UART_C2_TIE_MASK));
+ circ_buf_init(&write_buffer, write_buffer_data, sizeof(write_buffer_data));
+ circ_buf_init(&read_buffer, read_buffer_data, sizeof(read_buffer_data));
+}
+
+int32_t uart_initialize(void)
+{
+ NVIC_DisableIRQ(UART1_RX_TX_IRQn);
+ // enable clk PORTC
+ SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
+ // enable clk uart
+ SIM->SCGC4 |= SIM_SCGC4_UART1_MASK;
+
+ // disable interrupt
+ NVIC_DisableIRQ(UART1_RX_TX_IRQn);
+ // transmitter and receiver disabled
+ UART1->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);
+ // disable interrupt
+ UART1->C2 &= ~(UART_C2_RIE_MASK | UART_C2_TIE_MASK);
+
+ clear_buffers();
+
+ // Enable receiver and transmitter
+ UART1->C2 |= UART_C2_RE_MASK | UART_C2_TE_MASK;
+ // alternate 3: UART1
+ PORTC->PCR[3] = (3 << 8);
+ PORTC->PCR[4] = (3 << 8);
+ // Enable receive interrupt
+ UART1->C2 |= UART_C2_RIE_MASK;
+ NVIC_ClearPendingIRQ(UART1_RX_TX_IRQn);
+ NVIC_EnableIRQ(UART1_RX_TX_IRQn);
+ return 1;
+}
+
+int32_t uart_uninitialize(void)
+{
+ // transmitter and receiver disabled
+ UART1->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);
+ // disable interrupt
+ UART1->C2 &= ~(UART_C2_RIE_MASK | UART_C2_TIE_MASK);
+ clear_buffers();
+ return 1;
+}
+
+int32_t uart_reset(void)
+{
+ // disable interrupt
+ NVIC_DisableIRQ(UART1_RX_TX_IRQn);
+ // disable TIE interrupt
+ UART1->C2 &= ~(UART_C2_TIE_MASK);
+ clear_buffers();
+ // enable interrupt
+ NVIC_EnableIRQ(UART1_RX_TX_IRQn);
+ return 1;
+}
+
+int32_t uart_set_configuration(UART_Configuration *config)
+{
+ uint8_t data_bits = 8;
+ uint8_t parity_enable = 0;
+ uint8_t parity_type = 0;
+ uint32_t dll;
+ // disable interrupt
+ NVIC_DisableIRQ(UART1_RX_TX_IRQn);
+ UART1->C2 &= ~(UART_C2_RIE_MASK | UART_C2_TIE_MASK);
+ // Disable receiver and transmitter while updating
+ UART1->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);
+ clear_buffers();
+
+ // set data bits, stop bits, parity
+ if ((config->DataBits < 8) || (config->DataBits > 9)) {
+ data_bits = 8;
+ }
+
+ data_bits -= 8;
+
+ if (config->Parity == 1) {
+ parity_enable = 1;
+ parity_type = 1;
+ data_bits++;
+ } else if (config->Parity == 2) {
+ parity_enable = 1;
+ parity_type = 0;
+ data_bits++;
+ }
+
+ // does not support 10 bit data comm
+ if (data_bits == 2) {
+ data_bits = 0;
+ parity_enable = 0;
+ parity_type = 0;
+ }
+
+ // data bits, parity and parity mode
+ UART1->C1 = data_bits << UART_C1_M_SHIFT
+ | parity_enable << UART_C1_PE_SHIFT
+ | parity_type << UART_C1_PT_SHIFT;
+ dll = SystemCoreClock / (16 * config->Baudrate);
+ // set baudrate
+ UART1->BDH = (UART1->BDH & ~(UART_BDH_SBR_MASK)) | ((dll >> 8) & UART_BDH_SBR_MASK);
+ UART1->BDL = (UART1->BDL & ~(UART_BDL_SBR_MASK)) | (dll & UART_BDL_SBR_MASK);
+ // Enable transmitter and receiver
+ UART1->C2 |= UART_C2_RE_MASK | UART_C2_TE_MASK;
+ // Enable UART interrupt
+ NVIC_ClearPendingIRQ(UART1_RX_TX_IRQn);
+ NVIC_EnableIRQ(UART1_RX_TX_IRQn);
+ UART1->C2 |= UART_C2_RIE_MASK;
+ return 1;
+}
+
+int32_t uart_get_configuration(UART_Configuration *config)
+{
+ return 1;
+}
+
+int32_t uart_write_free(void)
+{
+ return circ_buf_count_free(&write_buffer);
+}
+
+int32_t uart_write_data(uint8_t *data, uint16_t size)
+{
+ cortex_int_state_t state;
+ uint32_t cnt;
+
+ cnt = circ_buf_write(&write_buffer, data, size);
+
+ // Atomically enable TX
+ state = cortex_int_get_and_disable();
+ if (circ_buf_count_used(&write_buffer)) {
+ UART1->C2 |= UART_C2_TIE_MASK;
+ }
+ cortex_int_restore(state);
+
+ return cnt;
+}
+
+int32_t uart_read_data(uint8_t *data, uint16_t size)
+{
+ return circ_buf_read(&read_buffer, data, size);
+}
+
+void uart_enable_flow_control(bool enabled)
+{
+ // Flow control not implemented for this platform
+}
+
+void UART1_RX_TX_IRQHandler(void)
+{
+ uint32_t s1;
+ volatile uint8_t errorData;
+ // read interrupt status
+ s1 = UART1->S1;
+ // mask off interrupts that are not enabled
+ if (!(UART1->C2 & UART_C2_RIE_MASK)) {
+ s1 &= ~UART_S1_RDRF_MASK;
+ }
+ if (!(UART1->C2 & UART_C2_TIE_MASK)) {
+ s1 &= ~UART_S1_TDRE_MASK;
+ }
+
+ // handle character to transmit
+ if (s1 & UART_S1_TDRE_MASK) {
+ // Assert that there is data in the buffer
+ util_assert(circ_buf_count_used(&write_buffer) > 0);
+
+ // Send out data
+ UART1->D = circ_buf_pop(&write_buffer);
+ // Turn off the transmitter if that was the last byte
+ if (circ_buf_count_used(&write_buffer) == 0) {
+ // disable TIE interrupt
+ UART1->C2 &= ~(UART_C2_TIE_MASK);
+ }
+ }
+
+ // handle received character
+ if (s1 & UART_S1_RDRF_MASK) {
+ if ((s1 & UART_S1_NF_MASK) || (s1 & UART_S1_FE_MASK)) {
+ errorData = UART1->D;
+ } else {
+ uint32_t free;
+ uint8_t data;
+
+ data = UART1->D;
+ free = circ_buf_count_free(&read_buffer);
+ if (free > RX_OVRF_MSG_SIZE) {
+ circ_buf_push(&read_buffer, data);
+ } else if (config_get_overflow_detect()) {
+ if (RX_OVRF_MSG_SIZE == free) {
+ circ_buf_write(&read_buffer, (uint8_t*)RX_OVRF_MSG, RX_OVRF_MSG_SIZE);
+ } else {
+ // Drop newest
+ }
+ } else {
+ // Drop oldest
+ circ_buf_pop(&read_buffer);
+ circ_buf_push(&read_buffer, data);
+ }
+ }
+ }
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k20dx/usb_buf.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/freescale/k20dx/usb_buf.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,29 @@ +/** + * @file usb_buf.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef USB_BUF_H +#define USB_BUF_H + +#include "stdint.h" + +uint32_t usb_buffer[512 / 4]; + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k20dx/usb_config.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/freescale/k20dx/usb_config.c Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,552 @@ +/** + * @file usb_config.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "util.h" + +// <e> USB Device +// <i> Enable the USB Device functionality +#define USBD_ENABLE 1 +#define USBD_RTX_CORE_STACK 0 +#define USBD_RTX_DEVICE_STACK 0 +#define USBD_RTX_ENDPOINT0_STACK 0 + +// <o0.0> High-speed +// <i> Enable high-speed functionality (if device supports it) +#define USBD_HS_ENABLE 0 +#if (defined(WEBUSB_INTERFACE) || defined(WINUSB_INTERFACE) || defined(BULK_ENDPOINT)) +#define USBD_BOS_ENABLE 1 +#else +#define USBD_BOS_ENABLE 0 +#endif +// <h> Device Settings +// <i> These settings affect Device Descriptor +// <o0> Power +// <i> Default Power Setting +// <0=> Bus-powered +// <1=> Self-powered +// <o1> Max Endpoint 0 Packet Size +// <i> Maximum packet size for endpoint zero (bMaxPacketSize0) +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes +// <o2.0..15> Vendor ID <0x0000-0xFFFF> +// <i> Vendor ID assigned by the USB-IF (idVendor) +// <o3.0..15> Product ID <0x0000-0xFFFF> +// <i> Product ID assigned by the manufacturer (idProduct) +// <o4.0..15> Device Release Number <0x0000-0xFFFF> +// <i> Device release number in binary-coded decimal (bcdDevice) +// </h> +#define USBD_POWER 0 +#define USBD_MAX_PACKET0 64 +#define USBD_DEVDESC_IDVENDOR 0x0D28 +#define USBD_DEVDESC_IDPRODUCT 0x0204 +#define USBD_DEVDESC_BCDDEVICE 0x1000 //was 0x0100 + +// <h> Configuration Settings +// <i> These settings affect Configuration Descriptor +// <o0.5> Remote Wakeup +// <i> Configuration support for remote wakeup (D5: of bmAttributes) +// <o1.0..7> Maximum Power Consumption (in mA) <0-510><#/2> +// <i> Maximum power consumption of the USB device +// <i> from the bus in this specific configuration +// <i> when the device is fully operational (bMaxPower) +// </h> +#define USBD_CFGDESC_BMATTRIBUTES 0x80 +#define USBD_CFGDESC_BMAXPOWER 0xFA + +// <h> String Settings +// <i> These settings affect String Descriptor +// <o0.0..15> Language ID <0x0000-0xFCFF> +// <i> English (United States) = 0x0409 +// <s0.126> Manufacturer String +// <i> String descriptor describing manufacturer +// <s1.126> Product String +// <i> String descriptor describing product +// <e1.0> Serial Number +// <i> Enable serial number string +// <i> If disabled serial number string will not be assigned to the USB Device +// <s2.126> Serial Number String +// <i> String descriptor describing device's serial number +// </e> +// </h> +#define USBD_STRDESC_LANGID 0x0409 +#define USBD_STRDESC_MAN L"ARM" +#ifndef USB_PROD_STR +#define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" +#else +#define _TOWIDE(x) L ## #x +#define TOWIDE(x) _TOWIDE(x) +#define USBD_STRDESC_PROD TOWIDE(USB_PROD_STR) +#endif +#define USBD_STRDESC_SER_ENABLE 1 +#define USBD_STRDESC_SER L"0001A0000000" + +// <e0> Class Support +// <i> Enables USB Device Class specific Requests +#define USBD_CLASS_ENABLE 1 + +// <e0.0> Human Interface Device (HID) +// <i> Enable class support for Human Interface Device (HID) +// <h> Interrupt Endpoint Settings +// <o1.0..4> Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o2.0..4> Interrupt Out Endpoint Number <0=> Not used <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <i> If interrupt out endpoint is not used select "Not used" +// <h> Endpoint Settings +// <o3.0..7> Maximum Endpoint Packet Size (in bytes) <0-64> +// <o4.0..7> Endpoint polling Interval (in ms) <1-255> +// <e5> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o6.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o6.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// <o7.0..7> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// </e> +// </h> +// </h> +// <h> Human Interface Device Settings +// <i> Device specific settings +// <s0.126> HID Interface String +// <o8.0..4> Number of Input Reports <1-32> +// <o9.0..4> Number of Output Reports <1-32> +// <o10.0..15> Maximum Input Report Size (in bytes) <1-65535> +// <o11.0..15> Maximum Output Report Size (in bytes) <1-65535> +// <o12.0..15> Maximum Feature Report Size (in bytes) <1-65535> +// </h> +// </e> +#ifndef HID_ENDPOINT +#define HID_ENDPOINT 0 +#else +#define HID_ENDPOINT 1 +#endif + +#ifndef WEBUSB_INTERFACE +#define WEBUSB_INTERFACE 0 +#else +#define WEBUSB_INTERFACE 1 +#endif + +#define USBD_HID_ENABLE HID_ENDPOINT +#define USBD_HID_EP_INTIN 1 +#define USBD_HID_EP_INTOUT 1 + +#define USBD_HID_EP_INTIN_STACK 0 +#define USBD_HID_WMAXPACKETSIZE 64 +#define USBD_HID_BINTERVAL 1 +#define USBD_HID_HS_ENABLE 0 +#define USBD_HID_HS_WMAXPACKETSIZE 64 +#define USBD_HID_HS_BINTERVAL 6 +#define USBD_HID_STRDESC L"CMSIS-DAP v1" +#define USBD_WEBUSB_STRDESC L"WebUSB: CMSIS-DAP" +#define USBD_HID_INREPORT_NUM 1 +#define USBD_HID_OUTREPORT_NUM 1 +#define USBD_HID_INREPORT_MAX_SZ 64 +#define USBD_HID_OUTREPORT_MAX_SZ 64 +#define USBD_HID_FEATREPORT_MAX_SZ 1 + +// <e0.0> Mass Storage Device (MSC) +// <i> Enable class support for Mass Storage Device (MSC) +// <h> Bulk Endpoint Settings +// <o1.0..4> Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o2.0..4> Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o3> Maximum Packet Size <1-1024> +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5> Maximum Packet Size <1-1024> +// <o6> Maximum NAK Rate <0-255> +// </e> +// </h> +// </h> +// <h> Mass Storage Device Settings +// <i> Device specific settings +// <s0.126> MSC Interface String +// <h> Inquiry Data +// <s1.8> Vendor Identification +// <s2.16> Product Identification +// <s3.4> Product Revision Level +// </h> +// </h> +// </e> +#ifndef MSC_ENDPOINT +#define MSC_ENDPOINT 0 +#else +#define MSC_ENDPOINT 1 +#endif +#define USBD_MSC_ENABLE MSC_ENDPOINT +#define USBD_MSC_EP_BULKIN 2 +#define USBD_MSC_EP_BULKOUT 2 +#define USBD_MSC_EP_BULKIN_STACK 0 +#define USBD_MSC_WMAXPACKETSIZE 64 +#define USBD_MSC_HS_ENABLE 0 +#define USBD_MSC_HS_WMAXPACKETSIZE 512 +#define USBD_MSC_HS_BINTERVAL 0 +#define USBD_MSC_STRDESC L"USB_MSC" +// Make sure changes to USBD_MSC_INQUIRY_DATA are coordinated with mbed-ls +// since this is used to detect DAPLink drives +#define USBD_MSC_INQUIRY_DATA "MBED " \ + "VFS " \ + "0.1" + +// <e0.0> Audio Device (ADC) +// <i> Enable class support for Audio Device (ADC) +// <h> Isochronous Endpoint Settings +// <o1.0..4> Isochronous Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o2.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o3.0..10> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o5.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// </e> +// </h> +// </h> +// <h> Audio Device Settings +// <i> Device specific settings +// <s0.126> Audio Control Interface String +// <s1.126> Audio Streaming (Zero Bandwidth) Interface String +// <s2.126> Audio Streaming (Operational) Interface String +// <o6.0..7> Audio Subframe Size (in bytes) <0-255> +// <o7.0..7> Sample Resolution (in bits) <0-255> +// <o8.0..23> Sample Frequency (in Hz) <0-16777215> +// <o9> Packet Size (in bytes) <1-256> +// <o10> Packet Count <1-16> +// </h> +// </e> +#define USBD_ADC_ENABLE 0 +#define USBD_ADC_EP_ISOOUT 3 +#define USBD_ADC_WMAXPACKETSIZE 64 +#define USBD_ADC_BINTERVAL 1 +#define USBD_ADC_HS_ENABLE 0 +#define USBD_ADC_HS_WMAXPACKETSIZE 64 +#define USBD_ADC_CIF_STRDESC L"USB_ADC" +#define USBD_ADC_SIF1_STRDESC L"USB_ADC1" +#define USBD_ADC_SIF2_STRDESC L"USB_ADC2" +#define USBD_ADC_BSUBFRAMESIZE 2 +#define USBD_ADC_BBITRESOLUTION 16 +#define USBD_ADC_TSAMFREQ 32000 +#define USBD_ADC_CFG_P_S 32 +#define USBD_ADC_CFG_P_C 1 + +// <e0> Communication Device (CDC) - Abstract Control Model (ACM) +// <i> Enable class support for Communication Device (CDC) - Abstract Control Model (ACM) +// <h> Interrupt Endpoint Settings +// <o1.0..4> Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o2.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o3.0..10> Endpoint polling Interval (in ms) <0-255> +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o5.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// <o6.0..10> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// </e4> +// </h> +// </h> +// <h> Bulk Endpoint Settings +// <o7.0..4> Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o8.0..4> Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o9> Maximum Packet Size <1-1024> +// <e10> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o11> Maximum Packet Size <1-1024> +// <o12> Maximum NAK Rate <0-255> +// </e10> +// </h> +// </h> +// <h> Communication Device Settings +// <i> Device specific settings +// <s0.126> Communication Class Interface String +// <s1.126> Data Class Interface String +// <o13> Maximum Communication Device Send Buffer Size +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// <o14> Maximum Communication Device Receive Buffer Size +// <i> Minimum size must be as big as maximum packet size for Bulk Out Endpoint +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// </h> +// </e> + +#ifndef CDC_ENDPOINT +#define CDC_ENDPOINT 0 +#else +#define CDC_ENDPOINT 1 +#endif +#define USBD_CDC_ACM_ENABLE CDC_ENDPOINT +#define USBD_CDC_ACM_EP_INTIN 3 +#define USBD_CDC_ACM_EP_INTIN_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE 16 +#define USBD_CDC_ACM_BINTERVAL 32 +#define USBD_CDC_ACM_HS_ENABLE 0 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE 16 +#define USBD_CDC_ACM_HS_BINTERVAL 2 +#define USBD_CDC_ACM_EP_BULKIN 4 +#define USBD_CDC_ACM_EP_BULKOUT 4 +#define USBD_CDC_ACM_EP_BULKIN_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE1 64 +#define USBD_CDC_ACM_HS_ENABLE1 0 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE1 64 +#define USBD_CDC_ACM_HS_BINTERVAL1 0 +#define USBD_CDC_ACM_CIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_DIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_SENDBUF_SIZE 64 +#define USBD_CDC_ACM_RECEIVEBUF_SIZE 64 +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Send Buffer size must be larger or equal to Bulk In maximum packet size!" +#endif +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Receive Buffer size must be larger or equal to Bulk Out maximum packet size!" +#endif + +// <e0> Custom Class Device +// <i> Enables USB Custom Class Requests +// <i> Class IDs: +// <i> 0x00 - Class Reserved ID +// <i> 0x01 - Class Audio ID +// <i> 0x02 - Class Communications ID +// <i> 0x03 - Class Human Interface ID +// <i> 0x04 - Class Monitor ID +// <i> 0x05 - Class Physical Interface ID +// <i> 0x06 - Class Power ID +// <i> 0x07 - Class Printer ID +// <i> 0x08 - Class Storage ID +// <i> 0x09 - Class HUB ID +// <i> 0xEF - Class Miscellaneous ID +// <i> 0xFF - Class Vendor Specific ID +// </e> +#define USBD_CLS_ENABLE 0 + +// WebUSB support +#define USBD_WEBUSB_ENABLE WEBUSB_INTERFACE +#define USBD_WEBUSB_VENDOR_CODE 0x21 +#define USBD_WEBUSB_LANDING_URL "os.mbed.com/webusb/landing-page/?bid=" +#define USBD_WEBUSB_ORIGIN_URL "os.mbed.com/" + +// Microsoft OS Descriptors 2.0 (WinUSB) support +#define USBD_WINUSB_ENABLE WINUSB_INTERFACE +#define USBD_WINUSB_VENDOR_CODE 0x20 +// </e> +// </e> + +#ifndef BULK_ENDPOINT +#define BULK_ENDPOINT 0 +#else +#define BULK_ENDPOINT 1 +#endif +#define USBD_BULK_ENABLE BULK_ENDPOINT +#define USBD_BULK_EP_BULKIN 5 +#define USBD_BULK_EP_BULKOUT 5 +#define USBD_BULK_WMAXPACKETSIZE 64 +#define USBD_BULK_HS_ENABLE 0 +#define USBD_BULK_HS_WMAXPACKETSIZE 512 +#define USBD_BULK_STRDESC L"CMSIS-DAP v2" + +/* USB Device Calculations ---------------------------------------------------*/ + +#define USBD_IF_NUM_MAX (USBD_BULK_ENABLE+USBD_WEBUSB_ENABLE+USBD_HID_ENABLE+USBD_MSC_ENABLE+(USBD_ADC_ENABLE*2)+(USBD_CDC_ACM_ENABLE*2)+USBD_CLS_ENABLE) +#define USBD_MULTI_IF (USBD_CDC_ACM_ENABLE*(USBD_HID_ENABLE|USBD_MSC_ENABLE|USBD_ADC_ENABLE|USBD_CLS_ENABLE|USBD_WEBUSB_ENABLE|USBD_BULK_ENABLE)) +// #define MAX(x, y) (((x) < (y)) ? (y) : (x)) +#define USBD_EP_NUM_CALC0 MAX((USBD_HID_ENABLE *(USBD_HID_EP_INTIN )), (USBD_HID_ENABLE *(USBD_HID_EP_INTOUT!=0)*(USBD_HID_EP_INTOUT))) +#define USBD_EP_NUM_CALC1 MAX((USBD_MSC_ENABLE *(USBD_MSC_EP_BULKIN )), (USBD_MSC_ENABLE *(USBD_MSC_EP_BULKOUT))) +#define USBD_EP_NUM_CALC2 MAX((USBD_ADC_ENABLE *(USBD_ADC_EP_ISOOUT )), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_INTIN))) +#define USBD_EP_NUM_CALC3 MAX((USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKIN)), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKOUT))) +#define USBD_EP_NUM_CALC4 MAX(USBD_EP_NUM_CALC0, USBD_EP_NUM_CALC1) +#define USBD_EP_NUM_CALC5 MAX(USBD_EP_NUM_CALC2, USBD_EP_NUM_CALC3) +#define USBD_EP_NUM_CALC6 MAX(USBD_EP_NUM_CALC4, USBD_EP_NUM_CALC5) +#define USBD_EP_NUM_CALC7 MAX((USBD_BULK_ENABLE*(USBD_BULK_EP_BULKIN)), (USBD_BULK_ENABLE*(USBD_BULK_EP_BULKOUT))) +#define USBD_EP_NUM MAX(USBD_EP_NUM_CALC6, USBD_EP_NUM_CALC7) + +#if (USBD_HID_ENABLE) +#if (USBD_MSC_ENABLE) +#if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_MSC_EP_BULKOUT))) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKOUT))) +#error "HID and Mass Storage Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_ADC_ENABLE) +#if ((USBD_HID_EP_INTIN == USBD_ADC_EP_ISOOUT) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_ADC_EP_ISOOUT))) +#error "HID and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (((USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKOUT))|| \ + ((USBD_HID_EP_INTOUT != 0) && \ + ((USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKOUT)))) +#error "HID and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_MSC_ENABLE) +#if (USBD_ADC_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_ADC_EP_ISOOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_ADC_EP_ISOOUT)) +#error "Mass Storage Device and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Mass Storage Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_ADC_ENABLE) +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Audio Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#define USBD_ADC_CIF_NUM (0) +#define USBD_ADC_SIF1_NUM (1) +#define USBD_ADC_SIF2_NUM (2) + +#define USBD_ADC_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+0) +#define USBD_ADC_SIF1_STR_NUM (3+USBD_STRDESC_SER_ENABLE+1) +#define USBD_ADC_SIF2_STR_NUM (3+USBD_STRDESC_SER_ENABLE+2) +#define USBD_CDC_ACM_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+0) +#define USBD_CDC_ACM_DIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+1) +#define USBD_HID_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2) +#define USBD_WEBUSB_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) +#define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) +#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) + +#if (USBD_HID_ENABLE) +#if (USBD_HID_HS_ENABLE) +#define USBD_HID_MAX_PACKET ((USBD_HID_HS_WMAXPACKETSIZE > USBD_HID_WMAXPACKETSIZE) ? USBD_HID_HS_WMAXPACKETSIZE : USBD_HID_WMAXPACKETSIZE) +#else +#define USBD_HID_MAX_PACKET (USBD_HID_WMAXPACKETSIZE) +#endif +#else +#define USBD_HID_MAX_PACKET (0) +#endif +#if (USBD_MSC_ENABLE) +#if (USBD_MSC_HS_ENABLE) +#define USBD_MSC_MAX_PACKET ((USBD_MSC_HS_WMAXPACKETSIZE > USBD_MSC_WMAXPACKETSIZE) ? USBD_MSC_HS_WMAXPACKETSIZE : USBD_MSC_WMAXPACKETSIZE) +#else +#define USBD_MSC_MAX_PACKET (USBD_MSC_WMAXPACKETSIZE) +#endif +#else +#define USBD_MSC_MAX_PACKET (0) +#endif +#if (USBD_ADC_ENABLE) +#if (USBD_ADC_HS_ENABLE) +#define USBD_ADC_MAX_PACKET ((USBD_ADC_HS_WMAXPACKETSIZE > USBD_ADC_WMAXPACKETSIZE) ? USBD_ADC_HS_WMAXPACKETSIZE : USBD_ADC_WMAXPACKETSIZE) +#else +#define USBD_ADC_MAX_PACKET (USBD_ADC_WMAXPACKETSIZE) +#endif +#else +#define USBD_ADC_MAX_PACKET (0) +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (USBD_CDC_ACM_HS_ENABLE) +#define USBD_CDC_ACM_MAX_PACKET ((USBD_CDC_ACM_HS_WMAXPACKETSIZE > USBD_CDC_ACM_WMAXPACKETSIZE) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE : USBD_CDC_ACM_WMAXPACKETSIZE) +#else +#define USBD_CDC_ACM_MAX_PACKET (USBD_CDC_ACM_WMAXPACKETSIZE) +#endif +#if (USBD_CDC_ACM_HS_ENABLE1) +#define USBD_CDC_ACM_MAX_PACKET1 ((USBD_CDC_ACM_HS_WMAXPACKETSIZE1 > USBD_CDC_ACM_WMAXPACKETSIZE1) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE1 : USBD_CDC_ACM_WMAXPACKETSIZE1) +#else +#define USBD_CDC_ACM_MAX_PACKET1 (USBD_CDC_ACM_WMAXPACKETSIZE1) +#endif +#else +#define USBD_CDC_ACM_MAX_PACKET (0) +#define USBD_CDC_ACM_MAX_PACKET1 (0) +#endif +#if (USBD_BULK_ENABLE) +#if (USBD_BULK_HS_ENABLE) +#define USBD_BULK_MAX_PACKET ((USBD_BULK_HS_WMAXPACKETSIZE > USBD_BULK_WMAXPACKETSIZE) ? USBD_BULK_HS_WMAXPACKETSIZE : USBD_BULK_WMAXPACKETSIZE) +#else +#define USBD_BULK_MAX_PACKET (USBD_BULK_WMAXPACKETSIZE) +#endif +#else +#define USBD_BULK_MAX_PACKET (0) +#endif +#define USBD_MAX_PACKET_CALC0 ((USBD_HID_MAX_PACKET > USBD_HID_MAX_PACKET ) ? (USBD_HID_MAX_PACKET ) : (USBD_HID_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC1 ((USBD_ADC_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET ) ? (USBD_ADC_MAX_PACKET ) : (USBD_CDC_ACM_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC2 ((USBD_MAX_PACKET_CALC0 > USBD_MAX_PACKET_CALC1 ) ? (USBD_MAX_PACKET_CALC0) : (USBD_MAX_PACKET_CALC1 )) +#define USBD_MAX_PACKET_CALC3 ((USBD_BULK_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET1 ) ? (USBD_BULK_MAX_PACKET) : (USBD_CDC_ACM_MAX_PACKET1 )) +#define USBD_MAX_PACKET ((USBD_MAX_PACKET_CALC3 > USBD_MAX_PACKET_CALC2 ) ? (USBD_MAX_PACKET_CALC3) : (USBD_MAX_PACKET_CALC2 )) + + + +/*------------------------------------------------------------------------------ + * USB Config Functions + *----------------------------------------------------------------------------*/ + +#ifndef __USB_CONFIG___ +#define __USB_CONFIG__ + +#ifndef __NO_USB_LIB_C +#include "usb_lib.c" +#endif + +#endif /* __USB_CONFIG__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/DAP_config.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/DAP_config.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,508 @@
+/**
+ * @file DAP_config.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __DAP_CONFIG_H__
+#define __DAP_CONFIG_H__
+
+#include "IO_Config.h"
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
+\ingroup DAP_ConfigIO_gr
+@{
+Provides definitions about the hardware and configuration of the Debug Unit.
+
+This information includes:
+ - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
+ - Debug Unit communication packet size.
+ - Debug Access Port communication mode (JTAG or SWD).
+ - Optional information about a connected Target Device (for Evaluation Boards).
+*/
+
+#include "fsl_device_registers.h" // Debug Unit Cortex-M Processor Header File
+
+/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
+/// This value is used to calculate the SWD/JTAG clock speed.
+#define CPU_CLOCK SystemCoreClock ///< Specifies the CPU Clock in Hz
+
+/// Number of processor cycles for I/O Port write operations.
+/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
+/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
+/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
+/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
+/// required.
+#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
+
+/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available
+
+/// Indicate that JTAG communication mode is available at the Debug Port.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available.
+
+/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
+/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
+#define DAP_JTAG_DEV_CNT 0 ///< Maximum number of JTAG devices on scan chain
+
+/// Default communication mode on the Debug Access Port.
+/// Used for the command \ref DAP_Connect when Port Default mode is selected.
+#define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
+
+/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
+/// Used to initialize the default SWD/JTAG clock frequency.
+/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
+#define DAP_DEFAULT_SWJ_CLOCK 4000000 ///< Default SWD/JTAG clock frequency in Hz.
+
+/// Maximum Package Size for Command and Response data.
+/// This configuration settings is used to optimized the communication performance with the
+/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
+#ifndef HID_ENDPOINT //HID end points currently set limits to 64
+#define DAP_PACKET_SIZE 512 ///< USB: 64 = Full-Speed, 512 = High-Speed.
+#else
+#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 512 = High-Speed.
+#endif
+
+/// Maximum Package Buffers for Command and Response data.
+/// This configuration settings is used to optimized the communication performance with the
+/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
+/// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
+#define DAP_PACKET_COUNT 64U ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
+
+/// Indicate that UART Serial Wire Output (SWO) trace is available.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define SWO_UART 1 ///< SWO UART: 1 = available, 0 = not available
+
+/// Maximum SWO UART Baudrate
+#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz
+
+/// Indicate that Manchester Serial Wire Output (SWO) trace is available.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available
+
+/// SWO Trace Buffer Size.
+#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n)
+
+#define SWO_USART_PORT 1 ///< UART1 is used for the SWO UART.
+
+/// SWO Streaming Trace.
+#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available.
+
+/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
+#define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported).
+
+/// Debug Unit is connected to fixed Target Device.
+/// The Debug Unit may be part of an evaluation board and always connected to a fixed
+/// known device. In this case a Device Vendor and Device Name string is stored which
+/// may be used by the debugger or IDE to configure device parameters.
+#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
+
+#if TARGET_DEVICE_FIXED
+#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor
+#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device
+#endif
+
+///@}
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
+\ingroup DAP_ConfigIO_gr
+@{
+
+Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
+and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
+interface of a device. The following I/O Pins are provided:
+
+JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
+---------------------------- | -------------------- | ---------------------------------------------
+TCK: Test Clock | SWCLK: Clock | Output Push/Pull
+TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
+TDI: Test Data Input | | Output Push/Pull
+TDO: Test Data Output | | Input
+nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
+nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
+
+
+DAP Hardware I/O Pin Access Functions
+-------------------------------------
+The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
+these I/O Pins.
+
+For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
+This functions are provided to achieve faster I/O that is possible with some advanced GPIO
+peripherals that can independently write/read a single I/O pin without affecting any other pins
+of the same I/O port. The following SWDIO I/O Pin functions are provided:
+ - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
+ - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
+ - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
+ - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
+*/
+
+
+// Configure DAP I/O pins ------------------------------
+
+/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
+Configures the DAP Hardware I/O pins for JTAG mode:
+ - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
+ - TDO to input mode.
+*/
+static inline void PORT_JTAG_SETUP(void) {}
+
+/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
+Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
+ - SWCLK, SWDIO, nRESET to output mode and set to default high level.
+ - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
+*/
+static inline void PORT_SWD_SETUP(void)
+{
+ PIN_SWCLK_GPIO->PSOR = 1 << PIN_SWCLK_BIT;
+ PIN_SWDIO_OUT_GPIO->PSOR = 1 << PIN_SWDIO_OUT_BIT;
+ PIN_SWDIO_OE_GPIO->PSOR = 1 << PIN_SWDIO_OE_BIT;
+ PIN_SWD_OE_GPIO->PSOR = 1 << PIN_SWD_OE_BIT;
+ PIN_nRESET_GPIO->PSOR = 1 << PIN_nRESET_BIT;
+ PIN_SWD_OE_GPIO->PDDR = PIN_SWD_OE_GPIO->PDDR | (1 << PIN_SWD_OE_BIT);
+ PIN_nRESET_GPIO->PSOR = PIN_nRESET;
+ PIN_nRESET_GPIO->PDDR |= PIN_nRESET; //output
+ PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_PFE_MASK | PORT_PCR_MUX(1);
+}
+
+/** Disable JTAG/SWD I/O Pins.
+Disables the DAP Hardware I/O pins which configures:
+ - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
+*/
+static inline void PORT_OFF(void)
+{
+ PIN_SWDIO_OE_GPIO->PCOR = 1 << PIN_SWDIO_OE_BIT;
+ PIN_SWD_OE_GPIO->PCOR = 1 << PIN_SWD_OE_BIT;
+ PIN_nRESET_GPIO->PSOR = 1 << PIN_nRESET_BIT;
+ PIN_nRESET_GPIO->PDDR &= ~PIN_nRESET; //input
+ PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] |= PORT_PCR_ISF_MASK;
+ PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_PFE_MASK | PORT_PCR_MUX(1);
+}
+
+
+// SWCLK/TCK I/O pin -------------------------------------
+
+/** SWCLK/TCK I/O pin: Get Input.
+\return Current status of the SWCLK/TCK DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void)
+{
+ return (0); // Not available
+}
+
+/** SWCLK/TCK I/O pin: Set Output to High.
+Set the SWCLK/TCK DAP hardware I/O pin to high level.
+*/
+__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET(void)
+{
+ PIN_SWCLK_GPIO->PSOR = 1 << PIN_SWCLK_BIT;
+}
+
+/** SWCLK/TCK I/O pin: Set Output to Low.
+Set the SWCLK/TCK DAP hardware I/O pin to low level.
+*/
+__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void)
+{
+ PIN_SWCLK_GPIO->PCOR = 1 << PIN_SWCLK_BIT;
+}
+
+
+// SWDIO/TMS Pin I/O --------------------------------------
+
+/** SWDIO/TMS I/O pin: Get Input.
+\return Current status of the SWDIO/TMS DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void)
+{
+ return ((PIN_SWDIO_IN_GPIO->PDIR >> PIN_SWDIO_IN_BIT) & 1);
+}
+
+/** SWDIO/TMS I/O pin: Set Output to High.
+Set the SWDIO/TMS DAP hardware I/O pin to high level.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET(void)
+{
+ PIN_SWDIO_OUT_GPIO->PSOR = 1 << PIN_SWDIO_OUT_BIT;
+}
+
+/** SWDIO/TMS I/O pin: Set Output to Low.
+Set the SWDIO/TMS DAP hardware I/O pin to low level.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void)
+{
+ PIN_SWDIO_OUT_GPIO->PCOR = 1 << PIN_SWDIO_OUT_BIT;
+}
+
+/** SWDIO I/O pin: Get Input (used in SWD mode only).
+\return Current status of the SWDIO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
+{
+ return (BITBAND_REG(PIN_SWDIO_IN_GPIO->PDIR, PIN_SWDIO_IN_BIT));
+}
+
+/** SWDIO I/O pin: Set Output (used in SWD mode only).
+\param bit Output value for the SWDIO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT(uint32_t bit)
+{
+ BITBAND_REG(PIN_SWDIO_OUT_GPIO->PDOR, PIN_SWDIO_OUT_BIT) = bit;
+}
+
+/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
+Configure the SWDIO DAP hardware I/O pin to output mode. This function is
+called prior \ref PIN_SWDIO_OUT function calls.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void)
+{
+ PIN_SWDIO_OE_GPIO->PSOR = 1 << PIN_SWDIO_OE_BIT;
+}
+
+/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
+Configure the SWDIO DAP hardware I/O pin to input mode. This function is
+called prior \ref PIN_SWDIO_IN function calls.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void)
+{
+ PIN_SWDIO_OE_GPIO->PCOR = 1 << PIN_SWDIO_OE_BIT;
+}
+
+
+// TDI Pin I/O ---------------------------------------------
+
+/** TDI I/O pin: Get Input.
+\return Current status of the TDI DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void)
+{
+ return (0); // Not available
+}
+
+/** TDI I/O pin: Set Output.
+\param bit Output value for the TDI DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE void PIN_TDI_OUT(uint32_t bit)
+{
+ ; // Not available
+}
+
+
+// TDO Pin I/O ---------------------------------------------
+
+/** TDO I/O pin: Get Input.
+\return Current status of the TDO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void)
+{
+ return (0); // Not available
+}
+
+
+// nTRST Pin I/O -------------------------------------------
+
+/** nTRST I/O pin: Get Input.
+\return Current status of the nTRST DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void)
+{
+ return (0); // Not available
+}
+
+/** nTRST I/O pin: Set Output.
+\param bit JTAG TRST Test Reset pin status:
+ - 0: issue a JTAG TRST Test Reset.
+ - 1: release JTAG TRST Test Reset.
+*/
+__STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit)
+{
+ ; // Not available
+}
+
+// nRESET Pin I/O------------------------------------------
+
+/** nRESET I/O pin: Get Input.
+\return Current status of the nRESET DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void)
+{
+ return ((PIN_nRESET_GPIO->PDIR >> PIN_nRESET_BIT) & 1);
+}
+
+/** nRESET I/O pin: Set Output.
+\param bit target device hardware reset pin status:
+ - 0: issue a device hardware reset.
+ - 1: release device hardware reset.
+*/
+__STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit)
+{
+ BITBAND_REG(PIN_nRESET_GPIO->PDOR, PIN_nRESET_BIT) = bit;
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
+\ingroup DAP_ConfigIO_gr
+@{
+
+CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
+
+It is recommended to provide the following LEDs for status indication:
+ - Connect LED: is active when the DAP hardware is connected to a debugger.
+ - Running LED: is active when the debugger has put the target device into running state.
+*/
+
+/** Debug Unit: Set status of Connected LED.
+\param bit status of the Connect LED.
+ - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
+ - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
+*/
+static inline void LED_CONNECTED_OUT(uint32_t bit)
+{
+ BITBAND_REG(LED_CONNECTED_GPIO->PDOR, LED_CONNECTED_BIT) = ~bit;
+}
+
+/** Debug Unit: Set status Target Running LED.
+\param bit status of the Target Running LED.
+ - 1: Target Running LED ON: program execution in target started.
+ - 0: Target Running LED OFF: program execution in target stopped.
+*/
+static inline void LED_RUNNING_OUT(uint32_t bit)
+{
+ ; // Not available
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
+\ingroup DAP_ConfigIO_gr
+@{
+Access function for Test Domain Timer.
+
+The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
+default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
+
+*/
+
+/** Get timestamp of Test Domain Timer.
+\return Current timestamp value.
+*/
+__STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
+ return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK);
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
+\ingroup DAP_ConfigIO_gr
+@{
+
+CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
+*/
+
+/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
+This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
+Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
+ - I/O clock system enabled.
+ - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
+ - for nTRST, nRESET a weak pull-up (if available) is enabled.
+ - LED output pins are enabled and LEDs are turned off.
+*/
+static inline void DAP_SETUP(void)
+{
+ SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK | /* Enable Port A Clock */
+ SIM_SCGC5_PORTB_MASK | /* Enable Port B Clock */
+ SIM_SCGC5_PORTC_MASK | /* Enable Port C Clock */
+ SIM_SCGC5_PORTD_MASK; /* Enable Port D Clock */
+ /* Configure I/O pin SWCLK */
+ PIN_SWCLK_PORT->PCR[PIN_SWCLK_BIT] = PORT_PCR_MUX(1) | /* GPIO */
+ PORT_PCR_DSE_MASK; /* High drive strength */
+ PIN_SWCLK_GPIO->PSOR = 1 << PIN_SWCLK_BIT; /* High level */
+ PIN_SWCLK_GPIO->PDDR |= 1 << PIN_SWCLK_BIT; /* Output */
+ /* Configure I/O pin SWDIO_OUT */
+ PIN_SWDIO_OUT_PORT->PCR[PIN_SWDIO_OUT_BIT] = PORT_PCR_MUX(1) | /* GPIO */
+ PORT_PCR_DSE_MASK; /* High drive strength */
+ PIN_SWDIO_OUT_GPIO->PSOR = 1 << PIN_SWDIO_OUT_BIT; /* High level */
+ PIN_SWDIO_OUT_GPIO->PDDR |= 1 << PIN_SWDIO_OUT_BIT; /* Output */
+ /* Configure I/O pin SWDIO_IN */
+ PIN_SWDIO_IN_PORT->PCR[PIN_SWDIO_IN_BIT] = PORT_PCR_MUX(1) | /* GPIO */
+ PORT_PCR_PE_MASK | /* Pull enable */
+ PORT_PCR_PS_MASK; /* Pull-up */
+ PIN_SWDIO_IN_GPIO->PDDR &= ~(1 << PIN_SWDIO_IN_BIT); /* Input */
+ /* Configure I/O pin SWDIO_OE */
+ PIN_SWDIO_OE_PORT->PCR[PIN_SWDIO_OE_BIT] = PORT_PCR_MUX(1) | /* GPIO */
+ PORT_PCR_DSE_MASK; /* High drive strength */
+ PIN_SWDIO_OE_GPIO->PCOR = 1 << PIN_SWDIO_OE_BIT; /* Low level */
+ PIN_SWDIO_OE_GPIO->PDDR |= 1 << PIN_SWDIO_OE_BIT; /* Output */
+ /* Configure I/O pin SWD_OE */
+ PIN_SWD_OE_PORT->PCR[PIN_SWD_OE_BIT] = PORT_PCR_MUX(1) | /* GPIO */
+ PORT_PCR_DSE_MASK; /* High drive strength */
+ PIN_SWD_OE_GPIO->PCOR = 1 << PIN_SWD_OE_BIT; /* Low level */
+ PIN_SWD_OE_GPIO->PDDR |= 1 << PIN_SWD_OE_BIT; /* Output */
+ /* Configure I/O pin nRESET */
+ PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_MUX(1) | /* GPIO */
+ PORT_PCR_PE_MASK | /* Pull enable */
+ PORT_PCR_PS_MASK | /* Pull-up */
+ PORT_PCR_ODE_MASK; /* Open-drain */
+ PIN_nRESET_GPIO->PSOR = 1 << PIN_nRESET_BIT; /* High level */
+ PIN_nRESET_GPIO->PDDR &= ~(1 << PIN_nRESET_BIT); /* Input */
+ // Configure I/O pin LVLRST_EN
+ // The nRESET level translator is enabled by default. The translator is auto-
+ // direction sensing. So as long as we don't drive nRESET from our side, we won't
+ // interfere with another debug probe connected to the target SWD header.
+ PIN_nRESET_EN_PORT->PCR[PIN_nRESET_EN_BIT] = PORT_PCR_MUX(1) | /* GPIO */
+ PORT_PCR_ODE_MASK; /* Open-drain */
+ PIN_nRESET_EN_GPIO->PSOR = PIN_nRESET_EN; /* High level */
+ PIN_nRESET_EN_GPIO->PDDR |= PIN_nRESET_EN; /* Output */
+ /* Configure LED */
+ LED_CONNECTED_PORT->PCR[LED_CONNECTED_BIT] = PORT_PCR_MUX(1) | /* GPIO */
+ PORT_PCR_ODE_MASK; /* Open-drain */
+ LED_CONNECTED_GPIO->PCOR = 1 << LED_CONNECTED_BIT; /* Turned on */
+ LED_CONNECTED_GPIO->PDDR |= 1 << LED_CONNECTED_BIT; /* Output */
+}
+
+/** Reset Target Device with custom specific I/O pin or command sequence.
+This function allows the optional implementation of a device specific reset sequence.
+It is called when the command \ref DAP_ResetTarget and is for example required
+when a device needs a time-critical unlock sequence that enables the debug port.
+\return 0 = no device specific reset sequence is implemented.\n
+ 1 = a device specific reset sequence is implemented.
+*/
+static inline uint32_t RESET_TARGET(void)
+{
+ return (0); // change to '1' when a device reset sequence is implemented
+}
+
+///@}
+
+
+#endif /* __DAP_CONFIG_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/Driver_Common.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/Driver_Common.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date: 2. Feb 2017
+ * $Revision: V2.0
+ *
+ * Project: Common Driver definitions
+ */
+
+/* History:
+ * Version 2.0
+ * Changed prefix ARM_DRV -> ARM_DRIVER
+ * Added General return codes definitions
+ * Version 1.10
+ * Namespace prefix ARM_ added
+ * Version 1.00
+ * Initial release
+ */
+
+#ifndef DRIVER_COMMON_H_
+#define DRIVER_COMMON_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor))
+
+/**
+\brief Driver Version
+*/
+typedef struct _ARM_DRIVER_VERSION {
+ uint16_t api; ///< API version
+ uint16_t drv; ///< Driver version
+} ARM_DRIVER_VERSION;
+
+/* General return codes */
+#define ARM_DRIVER_OK 0 ///< Operation succeeded
+#define ARM_DRIVER_ERROR -1 ///< Unspecified error
+#define ARM_DRIVER_ERROR_BUSY -2 ///< Driver is busy
+#define ARM_DRIVER_ERROR_TIMEOUT -3 ///< Timeout occurred
+#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported
+#define ARM_DRIVER_ERROR_PARAMETER -5 ///< Parameter error
+#define ARM_DRIVER_ERROR_SPECIFIC -6 ///< Start of driver specific errors
+
+/**
+\brief General power states
+*/
+typedef enum _ARM_POWER_STATE {
+ ARM_POWER_OFF, ///< Power off: no operation possible
+ ARM_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events
+ ARM_POWER_FULL ///< Power on: full operation at maximum performance
+} ARM_POWER_STATE;
+
+#endif /* DRIVER_COMMON_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/Driver_USART.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/Driver_USART.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,341 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date: 2. Feb 2017
+ * $Revision: V2.3
+ *
+ * Project: USART (Universal Synchronous Asynchronous Receiver Transmitter)
+ * Driver definitions
+ */
+
+/* History:
+ * Version 2.3
+ * ARM_USART_STATUS and ARM_USART_MODEM_STATUS made volatile
+ * Version 2.2
+ * Corrected ARM_USART_CPOL_Pos and ARM_USART_CPHA_Pos definitions
+ * Version 2.1
+ * Removed optional argument parameter from Signal Event
+ * Version 2.0
+ * New simplified driver:
+ * complexity moved to upper layer (especially data handling)
+ * more unified API for different communication interfaces
+ * renamed driver UART -> USART (Asynchronous & Synchronous)
+ * Added modes:
+ * Synchronous
+ * Single-wire
+ * IrDA
+ * Smart Card
+ * Changed prefix ARM_DRV -> ARM_DRIVER
+ * Version 1.10
+ * Namespace prefix ARM_ added
+ * Version 1.01
+ * Added events:
+ * ARM_UART_EVENT_TX_EMPTY, ARM_UART_EVENT_RX_TIMEOUT
+ * ARM_UART_EVENT_TX_THRESHOLD, ARM_UART_EVENT_RX_THRESHOLD
+ * Added functions: SetTxThreshold, SetRxThreshold
+ * Added "rx_timeout_event" to capabilities
+ * Version 1.00
+ * Initial release
+ */
+
+#ifndef DRIVER_USART_H_
+#define DRIVER_USART_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */
+
+
+/****** USART Control Codes *****/
+
+#define ARM_USART_CONTROL_Pos 0
+#define ARM_USART_CONTROL_Msk (0xFFUL << ARM_USART_CONTROL_Pos)
+
+/*----- USART Control Codes: Mode -----*/
+#define ARM_USART_MODE_ASYNCHRONOUS (0x01UL << ARM_USART_CONTROL_Pos) ///< UART (Asynchronous); arg = Baudrate
+#define ARM_USART_MODE_SYNCHRONOUS_MASTER (0x02UL << ARM_USART_CONTROL_Pos) ///< Synchronous Master (generates clock signal); arg = Baudrate
+#define ARM_USART_MODE_SYNCHRONOUS_SLAVE (0x03UL << ARM_USART_CONTROL_Pos) ///< Synchronous Slave (external clock signal)
+#define ARM_USART_MODE_SINGLE_WIRE (0x04UL << ARM_USART_CONTROL_Pos) ///< UART Single-wire (half-duplex); arg = Baudrate
+#define ARM_USART_MODE_IRDA (0x05UL << ARM_USART_CONTROL_Pos) ///< UART IrDA; arg = Baudrate
+#define ARM_USART_MODE_SMART_CARD (0x06UL << ARM_USART_CONTROL_Pos) ///< UART Smart Card; arg = Baudrate
+
+/*----- USART Control Codes: Mode Parameters: Data Bits -----*/
+#define ARM_USART_DATA_BITS_Pos 8
+#define ARM_USART_DATA_BITS_Msk (7UL << ARM_USART_DATA_BITS_Pos)
+#define ARM_USART_DATA_BITS_5 (5UL << ARM_USART_DATA_BITS_Pos) ///< 5 Data bits
+#define ARM_USART_DATA_BITS_6 (6UL << ARM_USART_DATA_BITS_Pos) ///< 6 Data bit
+#define ARM_USART_DATA_BITS_7 (7UL << ARM_USART_DATA_BITS_Pos) ///< 7 Data bits
+#define ARM_USART_DATA_BITS_8 (0UL << ARM_USART_DATA_BITS_Pos) ///< 8 Data bits (default)
+#define ARM_USART_DATA_BITS_9 (1UL << ARM_USART_DATA_BITS_Pos) ///< 9 Data bits
+
+/*----- USART Control Codes: Mode Parameters: Parity -----*/
+#define ARM_USART_PARITY_Pos 12
+#define ARM_USART_PARITY_Msk (3UL << ARM_USART_PARITY_Pos)
+#define ARM_USART_PARITY_NONE (0UL << ARM_USART_PARITY_Pos) ///< No Parity (default)
+#define ARM_USART_PARITY_EVEN (1UL << ARM_USART_PARITY_Pos) ///< Even Parity
+#define ARM_USART_PARITY_ODD (2UL << ARM_USART_PARITY_Pos) ///< Odd Parity
+
+/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/
+#define ARM_USART_STOP_BITS_Pos 14
+#define ARM_USART_STOP_BITS_Msk (3UL << ARM_USART_STOP_BITS_Pos)
+#define ARM_USART_STOP_BITS_1 (0UL << ARM_USART_STOP_BITS_Pos) ///< 1 Stop bit (default)
+#define ARM_USART_STOP_BITS_2 (1UL << ARM_USART_STOP_BITS_Pos) ///< 2 Stop bits
+#define ARM_USART_STOP_BITS_1_5 (2UL << ARM_USART_STOP_BITS_Pos) ///< 1.5 Stop bits
+#define ARM_USART_STOP_BITS_0_5 (3UL << ARM_USART_STOP_BITS_Pos) ///< 0.5 Stop bits
+
+/*----- USART Control Codes: Mode Parameters: Flow Control -----*/
+#define ARM_USART_FLOW_CONTROL_Pos 16
+#define ARM_USART_FLOW_CONTROL_Msk (3UL << ARM_USART_FLOW_CONTROL_Pos)
+#define ARM_USART_FLOW_CONTROL_NONE (0UL << ARM_USART_FLOW_CONTROL_Pos) ///< No Flow Control (default)
+#define ARM_USART_FLOW_CONTROL_RTS (1UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS Flow Control
+#define ARM_USART_FLOW_CONTROL_CTS (2UL << ARM_USART_FLOW_CONTROL_Pos) ///< CTS Flow Control
+#define ARM_USART_FLOW_CONTROL_RTS_CTS (3UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS/CTS Flow Control
+
+/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/
+#define ARM_USART_CPOL_Pos 18
+#define ARM_USART_CPOL_Msk (1UL << ARM_USART_CPOL_Pos)
+#define ARM_USART_CPOL0 (0UL << ARM_USART_CPOL_Pos) ///< CPOL = 0 (default)
+#define ARM_USART_CPOL1 (1UL << ARM_USART_CPOL_Pos) ///< CPOL = 1
+
+/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/
+#define ARM_USART_CPHA_Pos 19
+#define ARM_USART_CPHA_Msk (1UL << ARM_USART_CPHA_Pos)
+#define ARM_USART_CPHA0 (0UL << ARM_USART_CPHA_Pos) ///< CPHA = 0 (default)
+#define ARM_USART_CPHA1 (1UL << ARM_USART_CPHA_Pos) ///< CPHA = 1
+
+
+/*----- USART Control Codes: Miscellaneous Controls -----*/
+#define ARM_USART_SET_DEFAULT_TX_VALUE (0x10UL << ARM_USART_CONTROL_Pos) ///< Set default Transmit value (Synchronous Receive only); arg = value
+#define ARM_USART_SET_IRDA_PULSE (0x11UL << ARM_USART_CONTROL_Pos) ///< Set IrDA Pulse in ns; arg: 0=3/16 of bit period
+#define ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Guard Time; arg = number of bit periods
+#define ARM_USART_SET_SMART_CARD_CLOCK (0x13UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Clock in Hz; arg: 0=Clock not generated
+#define ARM_USART_CONTROL_SMART_CARD_NACK (0x14UL << ARM_USART_CONTROL_Pos) ///< Smart Card NACK generation; arg: 0=disabled, 1=enabled
+#define ARM_USART_CONTROL_TX (0x15UL << ARM_USART_CONTROL_Pos) ///< Transmitter; arg: 0=disabled, 1=enabled
+#define ARM_USART_CONTROL_RX (0x16UL << ARM_USART_CONTROL_Pos) ///< Receiver; arg: 0=disabled, 1=enabled
+#define ARM_USART_CONTROL_BREAK (0x17UL << ARM_USART_CONTROL_Pos) ///< Continuous Break transmission; arg: 0=disabled, 1=enabled
+#define ARM_USART_ABORT_SEND (0x18UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Send
+#define ARM_USART_ABORT_RECEIVE (0x19UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Receive
+#define ARM_USART_ABORT_TRANSFER (0x1AUL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Transfer
+
+
+
+/****** USART specific error codes *****/
+#define ARM_USART_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported
+#define ARM_USART_ERROR_BAUDRATE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified baudrate not supported
+#define ARM_USART_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported
+#define ARM_USART_ERROR_PARITY (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Parity not supported
+#define ARM_USART_ERROR_STOP_BITS (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified number of Stop bits not supported
+#define ARM_USART_ERROR_FLOW_CONTROL (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Specified Flow Control not supported
+#define ARM_USART_ERROR_CPOL (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Specified Clock Polarity not supported
+#define ARM_USART_ERROR_CPHA (ARM_DRIVER_ERROR_SPECIFIC - 8) ///< Specified Clock Phase not supported
+
+
+/**
+\brief USART Status
+*/
+typedef volatile struct _ARM_USART_STATUS {
+ uint32_t tx_busy : 1; ///< Transmitter busy flag
+ uint32_t rx_busy : 1; ///< Receiver busy flag
+ uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation)
+ uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation)
+ uint32_t rx_break : 1; ///< Break detected on receive (cleared on start of next receive operation)
+ uint32_t rx_framing_error : 1; ///< Framing error detected on receive (cleared on start of next receive operation)
+ uint32_t rx_parity_error : 1; ///< Parity error detected on receive (cleared on start of next receive operation)
+ uint32_t reserved : 25;
+} ARM_USART_STATUS;
+
+/**
+\brief USART Modem Control
+*/
+typedef enum _ARM_USART_MODEM_CONTROL {
+ ARM_USART_RTS_CLEAR, ///< Deactivate RTS
+ ARM_USART_RTS_SET, ///< Activate RTS
+ ARM_USART_DTR_CLEAR, ///< Deactivate DTR
+ ARM_USART_DTR_SET ///< Activate DTR
+} ARM_USART_MODEM_CONTROL;
+
+/**
+\brief USART Modem Status
+*/
+typedef volatile struct _ARM_USART_MODEM_STATUS {
+ uint32_t cts : 1; ///< CTS state: 1=Active, 0=Inactive
+ uint32_t dsr : 1; ///< DSR state: 1=Active, 0=Inactive
+ uint32_t dcd : 1; ///< DCD state: 1=Active, 0=Inactive
+ uint32_t ri : 1; ///< RI state: 1=Active, 0=Inactive
+ uint32_t reserved : 28;
+} ARM_USART_MODEM_STATUS;
+
+
+/****** USART Event *****/
+#define ARM_USART_EVENT_SEND_COMPLETE (1UL << 0) ///< Send completed; however USART may still transmit data
+#define ARM_USART_EVENT_RECEIVE_COMPLETE (1UL << 1) ///< Receive completed
+#define ARM_USART_EVENT_TRANSFER_COMPLETE (1UL << 2) ///< Transfer completed
+#define ARM_USART_EVENT_TX_COMPLETE (1UL << 3) ///< Transmit completed (optional)
+#define ARM_USART_EVENT_TX_UNDERFLOW (1UL << 4) ///< Transmit data not available (Synchronous Slave)
+#define ARM_USART_EVENT_RX_OVERFLOW (1UL << 5) ///< Receive data overflow
+#define ARM_USART_EVENT_RX_TIMEOUT (1UL << 6) ///< Receive character timeout (optional)
+#define ARM_USART_EVENT_RX_BREAK (1UL << 7) ///< Break detected on receive
+#define ARM_USART_EVENT_RX_FRAMING_ERROR (1UL << 8) ///< Framing error detected on receive
+#define ARM_USART_EVENT_RX_PARITY_ERROR (1UL << 9) ///< Parity error detected on receive
+#define ARM_USART_EVENT_CTS (1UL << 10) ///< CTS state changed (optional)
+#define ARM_USART_EVENT_DSR (1UL << 11) ///< DSR state changed (optional)
+#define ARM_USART_EVENT_DCD (1UL << 12) ///< DCD state changed (optional)
+#define ARM_USART_EVENT_RI (1UL << 13) ///< RI state changed (optional)
+
+
+// Function documentation
+/**
+ \fn ARM_DRIVER_VERSION ARM_USART_GetVersion (void)
+ \brief Get driver version.
+ \return \ref ARM_DRIVER_VERSION
+
+ \fn ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void)
+ \brief Get driver capabilities
+ \return \ref ARM_USART_CAPABILITIES
+
+ \fn int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event)
+ \brief Initialize USART Interface.
+ \param[in] cb_event Pointer to \ref ARM_USART_SignalEvent
+ \return \ref execution_status
+
+ \fn int32_t ARM_USART_Uninitialize (void)
+ \brief De-initialize USART Interface.
+ \return \ref execution_status
+
+ \fn int32_t ARM_USART_PowerControl (ARM_POWER_STATE state)
+ \brief Control USART Interface Power.
+ \param[in] state Power state
+ \return \ref execution_status
+
+ \fn int32_t ARM_USART_Send (const void *data, uint32_t num)
+ \brief Start sending data to USART transmitter.
+ \param[in] data Pointer to buffer with data to send to USART transmitter
+ \param[in] num Number of data items to send
+ \return \ref execution_status
+
+ \fn int32_t ARM_USART_Receive (void *data, uint32_t num)
+ \brief Start receiving data from USART receiver.
+ \param[out] data Pointer to buffer for data to receive from USART receiver
+ \param[in] num Number of data items to receive
+ \return \ref execution_status
+
+ \fn int32_t ARM_USART_Transfer (const void *data_out,
+ void *data_in,
+ uint32_t num)
+ \brief Start sending/receiving data to/from USART transmitter/receiver.
+ \param[in] data_out Pointer to buffer with data to send to USART transmitter
+ \param[out] data_in Pointer to buffer for data to receive from USART receiver
+ \param[in] num Number of data items to transfer
+ \return \ref execution_status
+
+ \fn uint32_t ARM_USART_GetTxCount (void)
+ \brief Get transmitted data count.
+ \return number of data items transmitted
+
+ \fn uint32_t ARM_USART_GetRxCount (void)
+ \brief Get received data count.
+ \return number of data items received
+
+ \fn int32_t ARM_USART_Control (uint32_t control, uint32_t arg)
+ \brief Control USART Interface.
+ \param[in] control Operation
+ \param[in] arg Argument of operation (optional)
+ \return common \ref execution_status and driver specific \ref usart_execution_status
+
+ \fn ARM_USART_STATUS ARM_USART_GetStatus (void)
+ \brief Get USART status.
+ \return USART status \ref ARM_USART_STATUS
+
+ \fn int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control)
+ \brief Set USART Modem Control line state.
+ \param[in] control \ref ARM_USART_MODEM_CONTROL
+ \return \ref execution_status
+
+ \fn ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void)
+ \brief Get USART Modem Status lines state.
+ \return modem status \ref ARM_USART_MODEM_STATUS
+
+ \fn void ARM_USART_SignalEvent (uint32_t event)
+ \brief Signal USART Events.
+ \param[in] event \ref USART_events notification mask
+ \return none
+*/
+
+typedef void (*ARM_USART_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_USART_SignalEvent : Signal USART Event.
+
+
+/**
+\brief USART Device Driver Capabilities.
+*/
+typedef struct _ARM_USART_CAPABILITIES {
+ uint32_t asynchronous : 1; ///< supports UART (Asynchronous) mode
+ uint32_t synchronous_master : 1; ///< supports Synchronous Master mode
+ uint32_t synchronous_slave : 1; ///< supports Synchronous Slave mode
+ uint32_t single_wire : 1; ///< supports UART Single-wire mode
+ uint32_t irda : 1; ///< supports UART IrDA mode
+ uint32_t smart_card : 1; ///< supports UART Smart Card mode
+ uint32_t smart_card_clock : 1; ///< Smart Card Clock generator available
+ uint32_t flow_control_rts : 1; ///< RTS Flow Control available
+ uint32_t flow_control_cts : 1; ///< CTS Flow Control available
+ uint32_t event_tx_complete : 1; ///< Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE
+ uint32_t event_rx_timeout : 1; ///< Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT
+ uint32_t rts : 1; ///< RTS Line: 0=not available, 1=available
+ uint32_t cts : 1; ///< CTS Line: 0=not available, 1=available
+ uint32_t dtr : 1; ///< DTR Line: 0=not available, 1=available
+ uint32_t dsr : 1; ///< DSR Line: 0=not available, 1=available
+ uint32_t dcd : 1; ///< DCD Line: 0=not available, 1=available
+ uint32_t ri : 1; ///< RI Line: 0=not available, 1=available
+ uint32_t event_cts : 1; ///< Signal CTS change event: \ref ARM_USART_EVENT_CTS
+ uint32_t event_dsr : 1; ///< Signal DSR change event: \ref ARM_USART_EVENT_DSR
+ uint32_t event_dcd : 1; ///< Signal DCD change event: \ref ARM_USART_EVENT_DCD
+ uint32_t event_ri : 1; ///< Signal RI change event: \ref ARM_USART_EVENT_RI
+ uint32_t reserved : 11; ///< Reserved (must be zero)
+} ARM_USART_CAPABILITIES;
+
+
+/**
+\brief Access structure of the USART Driver.
+*/
+typedef struct _ARM_DRIVER_USART {
+ ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USART_GetVersion : Get driver version.
+ ARM_USART_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USART_GetCapabilities : Get driver capabilities.
+ int32_t (*Initialize) (ARM_USART_SignalEvent_t cb_event); ///< Pointer to \ref ARM_USART_Initialize : Initialize USART Interface.
+ int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USART_Uninitialize : De-initialize USART Interface.
+ int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USART_PowerControl : Control USART Interface Power.
+ int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Send : Start sending data to USART transmitter.
+ int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver.
+ int32_t (*Transfer) (const void *data_out,
+ void *data_in,
+ uint32_t num); ///< Pointer to \ref ARM_USART_Transfer : Start sending/receiving data to/from USART.
+ uint32_t (*GetTxCount) (void); ///< Pointer to \ref ARM_USART_GetTxCount : Get transmitted data count.
+ uint32_t (*GetRxCount) (void); ///< Pointer to \ref ARM_USART_GetRxCount : Get received data count.
+ int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_USART_Control : Control USART Interface.
+ ARM_USART_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_USART_GetStatus : Get USART status.
+ int32_t (*SetModemControl) (ARM_USART_MODEM_CONTROL control); ///< Pointer to \ref ARM_USART_SetModemControl : Set USART Modem Control line state.
+ ARM_USART_MODEM_STATUS (*GetModemStatus) (void); ///< Pointer to \ref ARM_USART_GetModemStatus : Get USART Modem Status lines state.
+} const ARM_DRIVER_USART;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DRIVER_USART_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/IO_Config.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/freescale/k26f/IO_Config.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,207 @@ +/** + * @file IO_Config.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ + +#include "fsl_device_registers.h" +#include "compiler.h" +#include "daplink.h" + +// This GPIO configuration is only valid for the K26F HIC +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_K26F); + + +// Debug Port I/O Pins + +// SWCLK Pin PTC5 +// (SDA_SWD_SCK on schematic) +#define PIN_SWCLK_PORT PORTC +#define PIN_SWCLK_GPIO PTC +#define PIN_SWCLK_BIT 5 + +// SWDIO Out Pin PTC6 +// (SDA_SWD_DOUT on schematic) +#define PIN_SWDIO_OUT_PORT PORTC +#define PIN_SWDIO_OUT_GPIO PTC +#define PIN_SWDIO_OUT_BIT 6 + +// SWDIO In Pin PTC7 +// (SDA_SWD_DIN on schematic) +#define PIN_SWDIO_IN_PORT PORTC +#define PIN_SWDIO_IN_GPIO PTC +#define PIN_SWDIO_IN_BIT 7 + +// SWDIO Output Enable Pin PTA5 +// (SDA_SWD_OE on schematic) +#define PIN_SWDIO_OE_PORT PORTA +#define PIN_SWDIO_OE_GPIO PTA +#define PIN_SWDIO_OE_BIT 5 + +// SWD Enable Pin PTA4 +// (SDA_SWD_EN on schematic) +#define PIN_SWD_OE_PORT PORTA +#define PIN_SWD_OE_GPIO PTA +#define PIN_SWD_OE_BIT 9 + +// SWO Input Pin PTC3 +// (SDA_SWD_SWO on schematic) +#define PIN_SWO_RX_PORT PORTC +#define PIN_SWO_RX_GPIO PTC +#define PIN_SWO_RX_BIT 3 + +// nRESET Pin PTA7 +#define PIN_nRESET_PORT PORTA +#define PIN_nRESET_GPIO PTA +#define PIN_nRESET_BIT 7 +#define PIN_nRESET (1 << PIN_nRESET_BIT) + +// nRESET Pin Level Shifter Enable PTA6 +// (SDA_LVLRST_EN on schematic) +#define PIN_nRESET_EN_PORT PORTA +#define PIN_nRESET_EN_GPIO PTA +#define PIN_nRESET_EN_BIT 6 +#define PIN_nRESET_EN (1 << PIN_nRESET_EN_BIT) + +// SWD Detect Pin PTA8 +// (x_SWD_DETECT on schematic) +#define PIN_SWD_DETECT_PORT PORTA +#define PIN_SWD_DETECTGPIO PTA +#define PIN_SWD_DETECT_BIT 8 +#define PIN_SWD_DETECT (1 << PIN_SWD_DETECT_BIT) + + +// Power monitor + +// SDA_G1 Pin PTE17 +#define PIN_G1_PORT PORTE +#define PIN_G1_GPIO PTE +#define PIN_G1_BIT 17 +#define PIN_G1 (1 << PIN_G1_BIT) + +// SDA_G2 Pin PTE18 +#define PIN_G2_PORT PORTE +#define PIN_G2_GPIO PTE +#define PIN_G2_BIT 18 +#define PIN_G2 (1 << PIN_G2_BIT) + +// SDA_LOW_RANGE_EN Pin PTE19 +#define PIN_LOW_RANGE_EN_PORT PORTE +#define PIN_LOW_RANGE_EN_GPIO PTE +#define PIN_LOW_RANGE_EN_BIT 19 +#define PIN_LOW_RANGE_EN (1 << PIN_LOW_RANGE_EN_BIT) + +// SDA_CAL_EN Pin PTE24 +#define PIN_CAL_EN_PORT PORTE +#define PIN_CAL_EN_GPIO PTE +#define PIN_CAL_EN_BIT 24 +#define PIN_CAL_EN (1 << PIN_CAL_EN_BIT) + +// SDA_CTRL0 Pin PTE25 +#define PIN_CTRL0_PORT PORTE +#define PIN_CTRL0_GPIO PTE +#define PIN_CTRL0_BIT 25 +#define PIN_CTRL0 (1 << PIN_CTRL0_BIT) + +// SDA_CTRL1 Pin PTE26 +#define PIN_CTRL1_PORT PORTE +#define PIN_CTRL1_GPIO PTE +#define PIN_CTRL1_BIT 26 +#define PIN_CTRL1 (1 << PIN_CTRL1_BIT) + +// SDA_CTRL2 Pin PTE27 +#define PIN_CTRL2_PORT PORTE +#define PIN_CTRL2_GPIO PTE +#define PIN_CTRL2_BIT 27 +#define PIN_CTRL2 (1 << PIN_CTRL2_BIT) + +// SDA_CTRL3 Pin PTE28 +#define PIN_CTRL3_PORT PORTE +#define PIN_CTRL3_GPIO PTE +#define PIN_CTRL3_BIT 28 +#define PIN_CTRL3 (1 << PIN_CTRL3_BIT) + + +// Misc target connections + +// SDA_GPIO0_B Pin PTB22 +#define PIN_GPIO0_B_PORT PORTB +#define PIN_GPIO0_B_GPIO PTB +#define PIN_GPIO0_B_BIT 22 +#define PIN_GPIO0_B (1 < PIN_GPIO0_B_BIT) + +// SDA_CLKOUT_B Pin PTC +#define PIN_CLKOUT_B_PORT PORTC +#define PIN_CLKOUT_B_GPIO PTC +#define PIN_CLKOUT_B_BIT 3 +#define PIN_CLKOUT_B (1 << PIN_CLKOUT_B_BIT) + + +// Power and fault detection + +// PWR_REG_EN PTE12 +#define PIN_POWER_EN_PORT PORTE +#define PIN_POWER_EN_GPIO PTE +#define PIN_POWER_EN_BIT 12 +#define PIN_POWER_EN (1 << PIN_POWER_EN_BIT) + +// VTRG_FAULT_B PTE11 +#define PIN_VTRG_FAULT_B_PORT PORTE +#define PIN_VTRG_FAULT_B_GPIO PTE +#define PIN_VTRG_FAULT_B_BIT 11 + +// Debug Unit LEDs + +// Connected LED PTD4 +#define LED_CONNECTED_PORT PORTD +#define LED_CONNECTED_GPIO PTD +#define LED_CONNECTED_BIT 4 +#define LED_CONNECTED (1 << LED_CONNECTED_BIT) + +// Target Running LED Not available + +// Debug Unit LEDs + +// HID_LED PTD4 +#define PIN_HID_LED_PORT PORTD +#define PIN_HID_LED_GPIO PTD +#define PIN_HID_LED_BIT (4) +#define PIN_HID_LED (1<<PIN_HID_LED_BIT) + +// MSC_LED PTD4 +#define PIN_MSC_LED_PORT PORTD +#define PIN_MSC_LED_GPIO PTD +#define PIN_MSC_LED_BIT (4) +#define PIN_MSC_LED (1<<PIN_HID_LED_BIT) + +// CDC_LED PTD4 +#define PIN_CDC_LED_PORT PORTD +#define PIN_CDC_LED_GPIO PTD +#define PIN_CDC_LED_BIT (4) +#define PIN_CDC_LED (1<<PIN_HID_LED_BIT) + +// SW RESET BUTTON PTB1 +#define PIN_SW_RESET_PORT PORTB +#define PIN_SW_RESET_GPIO PTB +#define PIN_SW_RESET_BIT (1) +#define PIN_SW_RESET (1<<PIN_SW_RESET_BIT) + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/MK26F18/MK26F18.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/MK26F18/MK26F18.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,29290 @@
+/*
+** ###################################################################
+** Processors: MK26FN2M0CAC18
+** MK26FN2M0VLQ18
+** MK26FN2M0VMD18
+** MK26FN2M0VMI18
+**
+** Compilers: Keil ARM C/C++ Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+** MCUXpresso Compiler
+**
+** Reference manual: MK26P169M180SF5RM, Rev. 1, Mar 2015
+** Version: rev. 2.0, 2015-03-25
+** Build: b180801
+**
+** Abstract:
+** CMSIS Peripheral Access Layer for MK26F18
+**
+** Copyright 1997-2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2018 NXP
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** Revisions:
+** - rev. 1.0 (2014-12-04)
+** Initial version.
+** - rev. 1.1 (2015-02-19)
+** Renamed interrupt vector LLW to LLWU.
+** - rev. 2.0 (2015-03-25)
+** Registers updated according to the reference manual revision 1, March 2015
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK26F18.h
+ * @version 2.0
+ * @date 2015-03-25
+ * @brief CMSIS Peripheral Access Layer for MK26F18
+ *
+ * CMSIS Peripheral Access Layer for MK26F18
+ */
+
+#ifndef _MK26F18_H_
+#define _MK26F18_H_ /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0200U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
+
+/**
+ * @brief Macro to calculate address of an aliased word in the peripheral
+ * bitband area for a peripheral register and bit (bit band region 0x40000000 to
+ * 0x400FFFFF).
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Address of the aliased word in the peripheral bitband area.
+ */
+#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ * be used for peripherals with 32bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
+#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ * be used for peripherals with 16bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ * be used for peripherals with 8bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 116 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+ /* Auxiliary constants */
+ NotAvail_IRQn = -128, /**< Not available device specific interrupt */
+
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ DMA0_DMA16_IRQn = 0, /**< DMA Channel 0, 16 Transfer Complete */
+ DMA1_DMA17_IRQn = 1, /**< DMA Channel 1, 17 Transfer Complete */
+ DMA2_DMA18_IRQn = 2, /**< DMA Channel 2, 18 Transfer Complete */
+ DMA3_DMA19_IRQn = 3, /**< DMA Channel 3, 19 Transfer Complete */
+ DMA4_DMA20_IRQn = 4, /**< DMA Channel 4, 20 Transfer Complete */
+ DMA5_DMA21_IRQn = 5, /**< DMA Channel 5, 21 Transfer Complete */
+ DMA6_DMA22_IRQn = 6, /**< DMA Channel 6, 22 Transfer Complete */
+ DMA7_DMA23_IRQn = 7, /**< DMA Channel 7, 23 Transfer Complete */
+ DMA8_DMA24_IRQn = 8, /**< DMA Channel 8, 24 Transfer Complete */
+ DMA9_DMA25_IRQn = 9, /**< DMA Channel 9, 25 Transfer Complete */
+ DMA10_DMA26_IRQn = 10, /**< DMA Channel 10, 26 Transfer Complete */
+ DMA11_DMA27_IRQn = 11, /**< DMA Channel 11, 27 Transfer Complete */
+ DMA12_DMA28_IRQn = 12, /**< DMA Channel 12, 28 Transfer Complete */
+ DMA13_DMA29_IRQn = 13, /**< DMA Channel 13, 29 Transfer Complete */
+ DMA14_DMA30_IRQn = 14, /**< DMA Channel 14, 30 Transfer Complete */
+ DMA15_DMA31_IRQn = 15, /**< DMA Channel 15, 31 Transfer Complete */
+ DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
+ MCM_IRQn = 17, /**< Normal Interrupt */
+ FTFE_IRQn = 18, /**< FTFE Command complete interrupt */
+ Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
+ LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
+ LLWU_IRQn = 21, /**< Low Leakage Wakeup Unit */
+ WDOG_EWM_IRQn = 22, /**< WDOG Interrupt */
+ RNG_IRQn = 23, /**< RNG Interrupt */
+ I2C0_IRQn = 24, /**< I2C0 interrupt */
+ I2C1_IRQn = 25, /**< I2C1 interrupt */
+ SPI0_IRQn = 26, /**< SPI0 Interrupt */
+ SPI1_IRQn = 27, /**< SPI1 Interrupt */
+ I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
+ I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
+ Reserved46_IRQn = 30, /**< Reserved interrupt 46 */
+ UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
+ UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
+ UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
+ UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
+ UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
+ UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
+ UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */
+ UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */
+ ADC0_IRQn = 39, /**< ADC0 interrupt */
+ CMP0_IRQn = 40, /**< CMP0 interrupt */
+ CMP1_IRQn = 41, /**< CMP1 interrupt */
+ FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
+ FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
+ FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
+ CMT_IRQn = 45, /**< CMT interrupt */
+ RTC_IRQn = 46, /**< RTC interrupt */
+ RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
+ PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
+ PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
+ PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
+ PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
+ PDB0_IRQn = 52, /**< PDB0 Interrupt */
+ USB0_IRQn = 53, /**< USB0 interrupt */
+ USBDCD_IRQn = 54, /**< USBDCD Interrupt */
+ Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
+ DAC0_IRQn = 56, /**< DAC0 interrupt */
+ MCG_IRQn = 57, /**< MCG Interrupt */
+ LPTMR0_IRQn = 58, /**< LPTimer interrupt */
+ PORTA_IRQn = 59, /**< Port A interrupt */
+ PORTB_IRQn = 60, /**< Port B interrupt */
+ PORTC_IRQn = 61, /**< Port C interrupt */
+ PORTD_IRQn = 62, /**< Port D interrupt */
+ PORTE_IRQn = 63, /**< Port E interrupt */
+ SWI_IRQn = 64, /**< Software interrupt */
+ SPI2_IRQn = 65, /**< SPI2 Interrupt */
+ UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */
+ UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */
+ Reserved84_IRQn = 68, /**< Reserved interrupt 84 */
+ Reserved85_IRQn = 69, /**< Reserved interrupt 85 */
+ CMP2_IRQn = 70, /**< CMP2 interrupt */
+ FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */
+ DAC1_IRQn = 72, /**< DAC1 interrupt */
+ ADC1_IRQn = 73, /**< ADC1 interrupt */
+ I2C2_IRQn = 74, /**< I2C2 interrupt */
+ CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */
+ CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */
+ CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */
+ CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */
+ CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */
+ CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */
+ SDHC_IRQn = 81, /**< SDHC interrupt */
+ Reserved98_IRQn = 82, /**< Reserved Interrupt 98 */
+ Reserved99_IRQn = 83, /**< Reserved Interrupt 99 */
+ Reserved100_IRQn = 84, /**< Reserved Interrupt 100 */
+ Reserved101_IRQn = 85, /**< Reserved Interrupt 101 */
+ LPUART0_IRQn = 86, /**< LPUART0 status/error interrupt */
+ TSI0_IRQn = 87, /**< TSI0 interrupt */
+ TPM1_IRQn = 88, /**< TPM1 fault, overflow and channels interrupt */
+ TPM2_IRQn = 89, /**< TPM2 fault, overflow and channels interrupt */
+ USBHSDCD_IRQn = 90, /**< USBHSDCD, USBHS Phy Interrupt */
+ I2C3_IRQn = 91, /**< I2C3 interrupt */
+ CMP3_IRQn = 92, /**< CMP3 interrupt */
+ USBHS_IRQn = 93, /**< USB high speed OTG interrupt */
+ CAN1_ORed_Message_buffer_IRQn = 94, /**< CAN1 OR'd message buffers interrupt */
+ CAN1_Bus_Off_IRQn = 95, /**< CAN1 bus off interrupt */
+ CAN1_Error_IRQn = 96, /**< CAN1 error interrupt */
+ CAN1_Tx_Warning_IRQn = 97, /**< CAN1 Tx warning interrupt */
+ CAN1_Rx_Warning_IRQn = 98, /**< CAN1 Rx warning interrupt */
+ CAN1_Wake_Up_IRQn = 99 /**< CAN1 wake up interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M4 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h" /* Core Peripheral Access Layer */
+#include "system_MK26F18.h" /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Mapping Information
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup edma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according to the to SoC.
+ */
+typedef enum _dma_request_source
+{
+ kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */
+ kDmaRequestMux0TSI0 = 1|0x100U, /**< TSI0. */
+ kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */
+ kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */
+ kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */
+ kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */
+ kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */
+ kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */
+ kDmaRequestMux0UART3Rx = 8|0x100U, /**< UART3 Receive. */
+ kDmaRequestMux0UART3Tx = 9|0x100U, /**< UART3 Transmit. */
+ kDmaRequestMux0UART4 = 10|0x100U, /**< UART4 Transmit or Receive. */
+ kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */
+ kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */
+ kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */
+ kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */
+ kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */
+ kDmaRequestMux0SPI1Rx = 16|0x100U, /**< SPI1 Receive. */
+ kDmaRequestMux0SPI1Tx = 17|0x100U, /**< SPI1 Transmit. */
+ kDmaRequestMux0I2C0I2C3 = 18|0x100U, /**< I2C0 and I2C3. */
+ kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0 and I2C3. */
+ kDmaRequestMux0I2C3 = 18|0x100U, /**< I2C0 and I2C3. */
+ kDmaRequestMux0I2C1I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
+ kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1 and I2C2. */
+ kDmaRequestMux0I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
+ kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */
+ kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */
+ kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */
+ kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */
+ kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */
+ kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */
+ kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */
+ kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */
+ kDmaRequestMux0FTM1TPM1Channel0 = 28|0x100U, /**< FTM1 C0V and TPM1 C0V. */
+ kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V and TPM1 C0V. */
+ kDmaRequestMux0TPM1Channel0 = 28|0x100U, /**< FTM1 C0V and TPM1 C0V. */
+ kDmaRequestMux0FTM1TPM1Channel1 = 29|0x100U, /**< FTM1 C1V and TPM1 C1V. */
+ kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V and TPM1 C1V. */
+ kDmaRequestMux0TPM1Channel1 = 29|0x100U, /**< FTM1 C1V and TPM1 C1V. */
+ kDmaRequestMux0FTM2TPM2Channel0 = 30|0x100U, /**< FTM2 C0V and TPM2 C0V. */
+ kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V and TPM2 C0V. */
+ kDmaRequestMux0TPM2Channel0 = 30|0x100U, /**< FTM2 C0V and TPM2 C0V. */
+ kDmaRequestMux0FTM2TPM2Channel1 = 31|0x100U, /**< FTM2 C1V and TPM2 C1V. */
+ kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V and TPM2 C1V. */
+ kDmaRequestMux0TPM2Channel1 = 31|0x100U, /**< FTM2 C1V and TPM2 C1V. */
+ kDmaRequestMux0FTM3Channel0 = 32|0x100U, /**< FTM3 C0V. */
+ kDmaRequestMux0FTM3Channel1 = 33|0x100U, /**< FTM3 C1V. */
+ kDmaRequestMux0FTM3Channel2 = 34|0x100U, /**< FTM3 C2V. */
+ kDmaRequestMux0FTM3Channel3 = 35|0x100U, /**< FTM3 C3V. */
+ kDmaRequestMux0FTM3Channel4 = 36|0x100U, /**< FTM3 C4V. */
+ kDmaRequestMux0FTM3Channel5 = 37|0x100U, /**< FTM3 C5V. */
+ kDmaRequestMux0FTM3Channel6SPI2Rx = 38|0x100U, /**< FTM3 C6V and SPI2 Receive. */
+ kDmaRequestMux0FTM3Channel6 = 38|0x100U, /**< FTM3 C6V and SPI2 Receive. */
+ kDmaRequestMux0SPI2Rx = 38|0x100U, /**< FTM3 C6V and SPI2 Receive. */
+ kDmaRequestMux0FTM3Channel7SPI2Tx = 39|0x100U, /**< FTM3 C7V and SPI2 Transmit. */
+ kDmaRequestMux0FTM3Channel7 = 39|0x100U, /**< FTM3 C7V and SPI2 Transmit. */
+ kDmaRequestMux0SPI2Tx = 39|0x100U, /**< FTM3 C7V and SPI2 Transmit. */
+ kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */
+ kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1. */
+ kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */
+ kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */
+ kDmaRequestMux0CMP2CMP3 = 44|0x100U, /**< CMP2 and CMP3. */
+ kDmaRequestMux0CMP2 = 44|0x100U, /**< CMP2 and CMP3. */
+ kDmaRequestMux0CMP3 = 44|0x100U, /**< CMP2 and CMP3. */
+ kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */
+ kDmaRequestMux0DAC1 = 46|0x100U, /**< DAC1. */
+ kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */
+ kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */
+ kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */
+ kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */
+ kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */
+ kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */
+ kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */
+ kDmaRequestMux0Reserved54 = 54|0x100U, /**< Reserved54 */
+ kDmaRequestMux0TPM1Overflow = 55|0x100U, /**< TPM1. */
+ kDmaRequestMux0TPM2Overflow = 56|0x100U, /**< TPM2. */
+ kDmaRequestMux0Reserved57 = 57|0x100U, /**< Reserved57 */
+ kDmaRequestMux0LPUART0Rx = 58|0x100U, /**< LPUART0 Receive. */
+ kDmaRequestMux0LPUART0Tx = 59|0x100U, /**< LPUART0 Transmit. */
+ kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */
+ kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */
+ kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */
+ kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */
+} dma_request_source_t;
+
+/* @} */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #if (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #else
+ #pragma push
+ #pragma anon_unions
+ #endif
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+ __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
+ __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
+ __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
+ __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
+ __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
+ __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
+ __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
+ __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
+ __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
+ __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+ __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+ __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+ __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+ __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+ __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+ __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+ __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+ __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+ __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+ __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+ __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+ __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name SC1 - ADC Status and Control Registers 1 */
+/*! @{ */
+#define ADC_SC1_ADCH_MASK (0x1FU)
+#define ADC_SC1_ADCH_SHIFT (0U)
+/*! ADCH - Input channel select
+ * 0b00000..When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.
+ * 0b00001..When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.
+ * 0b00010..When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.
+ * 0b00011..When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.
+ * 0b00100..When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
+ * 0b00101..When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
+ * 0b00110..When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
+ * 0b00111..When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
+ * 0b01000..When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
+ * 0b01001..When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
+ * 0b01010..When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
+ * 0b01011..When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
+ * 0b01100..When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
+ * 0b01101..When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
+ * 0b01110..When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
+ * 0b01111..When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
+ * 0b10000..When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
+ * 0b10001..When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
+ * 0b10010..When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
+ * 0b10011..When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
+ * 0b10100..When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
+ * 0b10101..When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
+ * 0b10110..When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
+ * 0b10111..When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
+ * 0b11000..Reserved.
+ * 0b11001..Reserved.
+ * 0b11010..When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input.
+ * 0b11011..When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.
+ * 0b11100..Reserved.
+ * 0b11101..When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].
+ * 0b11110..When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].
+ * 0b11111..Module is disabled.
+ */
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK (0x20U)
+#define ADC_SC1_DIFF_SHIFT (5U)
+/*! DIFF - Differential Mode Enable
+ * 0b0..Single-ended conversions and input channels are selected.
+ * 0b1..Differential conversions and input channels are selected.
+ */
+#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
+#define ADC_SC1_AIEN_MASK (0x40U)
+#define ADC_SC1_AIEN_SHIFT (6U)
+/*! AIEN - Interrupt Enable
+ * 0b0..Conversion complete interrupt is disabled.
+ * 0b1..Conversion complete interrupt is enabled.
+ */
+#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
+#define ADC_SC1_COCO_MASK (0x80U)
+#define ADC_SC1_COCO_SHIFT (7U)
+/*! COCO - Conversion Complete Flag
+ * 0b0..Conversion is not completed.
+ * 0b1..Conversion is completed.
+ */
+#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
+/*! @} */
+
+/* The count of ADC_SC1 */
+#define ADC_SC1_COUNT (2U)
+
+/*! @name CFG1 - ADC Configuration Register 1 */
+/*! @{ */
+#define ADC_CFG1_ADICLK_MASK (0x3U)
+#define ADC_CFG1_ADICLK_SHIFT (0U)
+/*! ADICLK - Input Clock Select
+ * 0b00..Bus clock
+ * 0b01..Bus clock divided by 2(BUSCLK/2)
+ * 0b10..Alternate clock (ALTCLK)
+ * 0b11..Asynchronous clock (ADACK)
+ */
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK (0xCU)
+#define ADC_CFG1_MODE_SHIFT (2U)
+/*! MODE - Conversion mode selection
+ * 0b00..When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output.
+ * 0b01..When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output.
+ * 0b10..When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output
+ * 0b11..When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output
+ */
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK (0x10U)
+#define ADC_CFG1_ADLSMP_SHIFT (4U)
+/*! ADLSMP - Sample Time Configuration
+ * 0b0..Short sample time.
+ * 0b1..Long sample time.
+ */
+#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
+#define ADC_CFG1_ADIV_MASK (0x60U)
+#define ADC_CFG1_ADIV_SHIFT (5U)
+/*! ADIV - Clock Divide Select
+ * 0b00..The divide ratio is 1 and the clock rate is input clock.
+ * 0b01..The divide ratio is 2 and the clock rate is (input clock)/2.
+ * 0b10..The divide ratio is 4 and the clock rate is (input clock)/4.
+ * 0b11..The divide ratio is 8 and the clock rate is (input clock)/8.
+ */
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK (0x80U)
+#define ADC_CFG1_ADLPC_SHIFT (7U)
+/*! ADLPC - Low-Power Configuration
+ * 0b0..Normal power configuration.
+ * 0b1..Low-power configuration. The power is reduced at the expense of maximum clock speed.
+ */
+#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
+/*! @} */
+
+/*! @name CFG2 - ADC Configuration Register 2 */
+/*! @{ */
+#define ADC_CFG2_ADLSTS_MASK (0x3U)
+#define ADC_CFG2_ADLSTS_SHIFT (0U)
+/*! ADLSTS - Long Sample Time Select
+ * 0b00..Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
+ * 0b01..12 extra ADCK cycles; 16 ADCK cycles total sample time.
+ * 0b10..6 extra ADCK cycles; 10 ADCK cycles total sample time.
+ * 0b11..2 extra ADCK cycles; 6 ADCK cycles total sample time.
+ */
+#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK (0x4U)
+#define ADC_CFG2_ADHSC_SHIFT (2U)
+/*! ADHSC - High-Speed Configuration
+ * 0b0..Normal conversion sequence selected.
+ * 0b1..High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.
+ */
+#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
+#define ADC_CFG2_ADACKEN_MASK (0x8U)
+#define ADC_CFG2_ADACKEN_SHIFT (3U)
+/*! ADACKEN - Asynchronous Clock Output Enable
+ * 0b0..Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.
+ * 0b1..Asynchronous clock and clock output is enabled regardless of the state of the ADC.
+ */
+#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
+#define ADC_CFG2_MUXSEL_MASK (0x10U)
+#define ADC_CFG2_MUXSEL_SHIFT (4U)
+/*! MUXSEL - ADC Mux Select
+ * 0b0..ADxxa channels are selected.
+ * 0b1..ADxxb channels are selected.
+ */
+#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
+/*! @} */
+
+/*! @name R - ADC Data Result Register */
+/*! @{ */
+#define ADC_R_D_MASK (0xFFFFU)
+#define ADC_R_D_SHIFT (0U)
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
+/*! @} */
+
+/* The count of ADC_R */
+#define ADC_R_COUNT (2U)
+
+/*! @name CV1 - Compare Value Registers */
+/*! @{ */
+#define ADC_CV1_CV_MASK (0xFFFFU)
+#define ADC_CV1_CV_SHIFT (0U)
+#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
+/*! @} */
+
+/*! @name CV2 - Compare Value Registers */
+/*! @{ */
+#define ADC_CV2_CV_MASK (0xFFFFU)
+#define ADC_CV2_CV_SHIFT (0U)
+#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
+/*! @} */
+
+/*! @name SC2 - Status and Control Register 2 */
+/*! @{ */
+#define ADC_SC2_REFSEL_MASK (0x3U)
+#define ADC_SC2_REFSEL_SHIFT (0U)
+/*! REFSEL - Voltage Reference Selection
+ * 0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL
+ * 0b01..Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU
+ * 0b10..Reserved
+ * 0b11..Reserved
+ */
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK (0x4U)
+#define ADC_SC2_DMAEN_SHIFT (2U)
+/*! DMAEN - DMA Enable
+ * 0b0..DMA is disabled.
+ * 0b1..DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.
+ */
+#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
+#define ADC_SC2_ACREN_MASK (0x8U)
+#define ADC_SC2_ACREN_SHIFT (3U)
+/*! ACREN - Compare Function Range Enable
+ * 0b0..Range function disabled. Only CV1 is compared.
+ * 0b1..Range function enabled. Both CV1 and CV2 are compared.
+ */
+#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
+#define ADC_SC2_ACFGT_MASK (0x10U)
+#define ADC_SC2_ACFGT_SHIFT (4U)
+/*! ACFGT - Compare Function Greater Than Enable
+ * 0b0..Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.
+ * 0b1..Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.
+ */
+#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
+#define ADC_SC2_ACFE_MASK (0x20U)
+#define ADC_SC2_ACFE_SHIFT (5U)
+/*! ACFE - Compare Function Enable
+ * 0b0..Compare function disabled.
+ * 0b1..Compare function enabled.
+ */
+#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
+#define ADC_SC2_ADTRG_MASK (0x40U)
+#define ADC_SC2_ADTRG_SHIFT (6U)
+/*! ADTRG - Conversion Trigger Select
+ * 0b0..Software trigger selected.
+ * 0b1..Hardware trigger selected.
+ */
+#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
+#define ADC_SC2_ADACT_MASK (0x80U)
+#define ADC_SC2_ADACT_SHIFT (7U)
+/*! ADACT - Conversion Active
+ * 0b0..Conversion not in progress.
+ * 0b1..Conversion in progress.
+ */
+#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
+/*! @} */
+
+/*! @name SC3 - Status and Control Register 3 */
+/*! @{ */
+#define ADC_SC3_AVGS_MASK (0x3U)
+#define ADC_SC3_AVGS_SHIFT (0U)
+/*! AVGS - Hardware Average Select
+ * 0b00..4 samples averaged.
+ * 0b01..8 samples averaged.
+ * 0b10..16 samples averaged.
+ * 0b11..32 samples averaged.
+ */
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK (0x4U)
+#define ADC_SC3_AVGE_SHIFT (2U)
+/*! AVGE - Hardware Average Enable
+ * 0b0..Hardware average function disabled.
+ * 0b1..Hardware average function enabled.
+ */
+#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
+#define ADC_SC3_ADCO_MASK (0x8U)
+#define ADC_SC3_ADCO_SHIFT (3U)
+/*! ADCO - Continuous Conversion Enable
+ * 0b0..One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
+ * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
+ */
+#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
+#define ADC_SC3_CALF_MASK (0x40U)
+#define ADC_SC3_CALF_SHIFT (6U)
+/*! CALF - Calibration Failed Flag
+ * 0b0..Calibration completed normally.
+ * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed.
+ */
+#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
+#define ADC_SC3_CAL_MASK (0x80U)
+#define ADC_SC3_CAL_SHIFT (7U)
+#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
+/*! @} */
+
+/*! @name OFS - ADC Offset Correction Register */
+/*! @{ */
+#define ADC_OFS_OFS_MASK (0xFFFFU)
+#define ADC_OFS_OFS_SHIFT (0U)
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
+/*! @} */
+
+/*! @name PG - ADC Plus-Side Gain Register */
+/*! @{ */
+#define ADC_PG_PG_MASK (0xFFFFU)
+#define ADC_PG_PG_SHIFT (0U)
+#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
+/*! @} */
+
+/*! @name MG - ADC Minus-Side Gain Register */
+/*! @{ */
+#define ADC_MG_MG_MASK (0xFFFFU)
+#define ADC_MG_MG_SHIFT (0U)
+#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
+/*! @} */
+
+/*! @name CLPD - ADC Plus-Side General Calibration Value Register */
+/*! @{ */
+#define ADC_CLPD_CLPD_MASK (0x3FU)
+#define ADC_CLPD_CLPD_SHIFT (0U)
+#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
+/*! @} */
+
+/*! @name CLPS - ADC Plus-Side General Calibration Value Register */
+/*! @{ */
+#define ADC_CLPS_CLPS_MASK (0x3FU)
+#define ADC_CLPS_CLPS_SHIFT (0U)
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
+/*! @} */
+
+/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
+/*! @{ */
+#define ADC_CLP4_CLP4_MASK (0x3FFU)
+#define ADC_CLP4_CLP4_SHIFT (0U)
+#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
+/*! @} */
+
+/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
+/*! @{ */
+#define ADC_CLP3_CLP3_MASK (0x1FFU)
+#define ADC_CLP3_CLP3_SHIFT (0U)
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
+/*! @} */
+
+/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
+/*! @{ */
+#define ADC_CLP2_CLP2_MASK (0xFFU)
+#define ADC_CLP2_CLP2_SHIFT (0U)
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
+/*! @} */
+
+/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
+/*! @{ */
+#define ADC_CLP1_CLP1_MASK (0x7FU)
+#define ADC_CLP1_CLP1_SHIFT (0U)
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
+/*! @} */
+
+/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
+/*! @{ */
+#define ADC_CLP0_CLP0_MASK (0x3FU)
+#define ADC_CLP0_CLP0_SHIFT (0U)
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
+/*! @} */
+
+/*! @name CLMD - ADC Minus-Side General Calibration Value Register */
+/*! @{ */
+#define ADC_CLMD_CLMD_MASK (0x3FU)
+#define ADC_CLMD_CLMD_SHIFT (0U)
+#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
+/*! @} */
+
+/*! @name CLMS - ADC Minus-Side General Calibration Value Register */
+/*! @{ */
+#define ADC_CLMS_CLMS_MASK (0x3FU)
+#define ADC_CLMS_CLMS_SHIFT (0U)
+#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
+/*! @} */
+
+/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
+/*! @{ */
+#define ADC_CLM4_CLM4_MASK (0x3FFU)
+#define ADC_CLM4_CLM4_SHIFT (0U)
+#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
+/*! @} */
+
+/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
+/*! @{ */
+#define ADC_CLM3_CLM3_MASK (0x1FFU)
+#define ADC_CLM3_CLM3_SHIFT (0U)
+#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
+/*! @} */
+
+/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
+/*! @{ */
+#define ADC_CLM2_CLM2_MASK (0xFFU)
+#define ADC_CLM2_CLM2_SHIFT (0U)
+#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
+/*! @} */
+
+/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
+/*! @{ */
+#define ADC_CLM1_CLM1_MASK (0x7FU)
+#define ADC_CLM1_CLM1_SHIFT (0U)
+#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
+/*! @} */
+
+/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
+/*! @{ */
+#define ADC_CLM0_CLM0_MASK (0x3FU)
+#define ADC_CLM0_CLM0_SHIFT (0U)
+#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0 ((ADC_Type *)ADC0_BASE)
+/** Peripheral ADC1 base address */
+#define ADC1_BASE (0x400BB000u)
+/** Peripheral ADC1 base pointer */
+#define ADC1 ((ADC_Type *)ADC1_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS { ADC0, ADC1 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- AIPS Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
+ * @{
+ */
+
+/** AIPS - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
+ uint8_t RESERVED_0[28];
+ __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
+ __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
+ __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
+ __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
+ uint8_t RESERVED_1[16];
+ __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
+ __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
+ __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
+ __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
+ __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
+ __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
+ __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
+ __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
+ __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
+ __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
+ __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
+ __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
+} AIPS_Type;
+
+/* ----------------------------------------------------------------------------
+ -- AIPS Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Masks AIPS Register Masks
+ * @{
+ */
+
+/*! @name MPRA - Master Privilege Register A */
+/*! @{ */
+#define AIPS_MPRA_MPL6_MASK (0x10U)
+#define AIPS_MPRA_MPL6_SHIFT (4U)
+/*! MPL6 - Master 6 Privilege Level
+ * 0b0..Accesses from this master are forced to user-mode.
+ * 0b1..Accesses from this master are not forced to user-mode.
+ */
+#define AIPS_MPRA_MPL6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL6_SHIFT)) & AIPS_MPRA_MPL6_MASK)
+#define AIPS_MPRA_MTW6_MASK (0x20U)
+#define AIPS_MPRA_MTW6_SHIFT (5U)
+/*! MTW6 - Master 6 Trusted for Writes
+ * 0b0..This master is not trusted for write accesses.
+ * 0b1..This master is trusted for write accesses.
+ */
+#define AIPS_MPRA_MTW6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW6_SHIFT)) & AIPS_MPRA_MTW6_MASK)
+#define AIPS_MPRA_MTR6_MASK (0x40U)
+#define AIPS_MPRA_MTR6_SHIFT (6U)
+/*! MTR6 - Master 6 Trusted for Read
+ * 0b0..This master is not trusted for read accesses.
+ * 0b1..This master is trusted for read accesses.
+ */
+#define AIPS_MPRA_MTR6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR6_SHIFT)) & AIPS_MPRA_MTR6_MASK)
+#define AIPS_MPRA_MPL5_MASK (0x100U)
+#define AIPS_MPRA_MPL5_SHIFT (8U)
+/*! MPL5 - Master 5 Privilege Level
+ * 0b0..Accesses from this master are forced to user-mode.
+ * 0b1..Accesses from this master are not forced to user-mode.
+ */
+#define AIPS_MPRA_MPL5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK)
+#define AIPS_MPRA_MTW5_MASK (0x200U)
+#define AIPS_MPRA_MTW5_SHIFT (9U)
+/*! MTW5 - Master 5 Trusted For Writes
+ * 0b0..This master is not trusted for write accesses.
+ * 0b1..This master is trusted for write accesses.
+ */
+#define AIPS_MPRA_MTW5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK)
+#define AIPS_MPRA_MTR5_MASK (0x400U)
+#define AIPS_MPRA_MTR5_SHIFT (10U)
+/*! MTR5 - Master 5 Trusted For Read
+ * 0b0..This master is not trusted for read accesses.
+ * 0b1..This master is trusted for read accesses.
+ */
+#define AIPS_MPRA_MTR5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK)
+#define AIPS_MPRA_MPL4_MASK (0x1000U)
+#define AIPS_MPRA_MPL4_SHIFT (12U)
+/*! MPL4 - Master 4 Privilege Level
+ * 0b0..Accesses from this master are forced to user-mode.
+ * 0b1..Accesses from this master are not forced to user-mode.
+ */
+#define AIPS_MPRA_MPL4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
+#define AIPS_MPRA_MTW4_MASK (0x2000U)
+#define AIPS_MPRA_MTW4_SHIFT (13U)
+/*! MTW4 - Master 4 Trusted For Writes
+ * 0b0..This master is not trusted for write accesses.
+ * 0b1..This master is trusted for write accesses.
+ */
+#define AIPS_MPRA_MTW4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
+#define AIPS_MPRA_MTR4_MASK (0x4000U)
+#define AIPS_MPRA_MTR4_SHIFT (14U)
+/*! MTR4 - Master 4 Trusted For Read
+ * 0b0..This master is not trusted for read accesses.
+ * 0b1..This master is trusted for read accesses.
+ */
+#define AIPS_MPRA_MTR4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
+#define AIPS_MPRA_MPL3_MASK (0x10000U)
+#define AIPS_MPRA_MPL3_SHIFT (16U)
+/*! MPL3 - Master 3 Privilege Level
+ * 0b0..Accesses from this master are forced to user-mode.
+ * 0b1..Accesses from this master are not forced to user-mode.
+ */
+#define AIPS_MPRA_MPL3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
+#define AIPS_MPRA_MTW3_MASK (0x20000U)
+#define AIPS_MPRA_MTW3_SHIFT (17U)
+/*! MTW3 - Master 3 Trusted For Writes
+ * 0b0..This master is not trusted for write accesses.
+ * 0b1..This master is trusted for write accesses.
+ */
+#define AIPS_MPRA_MTW3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
+#define AIPS_MPRA_MTR3_MASK (0x40000U)
+#define AIPS_MPRA_MTR3_SHIFT (18U)
+/*! MTR3 - Master 3 Trusted For Read
+ * 0b0..This master is not trusted for read accesses.
+ * 0b1..This master is trusted for read accesses.
+ */
+#define AIPS_MPRA_MTR3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
+#define AIPS_MPRA_MPL2_MASK (0x100000U)
+#define AIPS_MPRA_MPL2_SHIFT (20U)
+/*! MPL2 - Master 2 Privilege Level
+ * 0b0..Accesses from this master are forced to user-mode.
+ * 0b1..Accesses from this master are not forced to user-mode.
+ */
+#define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
+#define AIPS_MPRA_MTW2_MASK (0x200000U)
+#define AIPS_MPRA_MTW2_SHIFT (21U)
+/*! MTW2 - Master 2 Trusted For Writes
+ * 0b0..This master is not trusted for write accesses.
+ * 0b1..This master is trusted for write accesses.
+ */
+#define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
+#define AIPS_MPRA_MTR2_MASK (0x400000U)
+#define AIPS_MPRA_MTR2_SHIFT (22U)
+/*! MTR2 - Master 2 Trusted For Read
+ * 0b0..This master is not trusted for read accesses.
+ * 0b1..This master is trusted for read accesses.
+ */
+#define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
+#define AIPS_MPRA_MPL1_MASK (0x1000000U)
+#define AIPS_MPRA_MPL1_SHIFT (24U)
+/*! MPL1 - Master 1 Privilege Level
+ * 0b0..Accesses from this master are forced to user-mode.
+ * 0b1..Accesses from this master are not forced to user-mode.
+ */
+#define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
+#define AIPS_MPRA_MTW1_MASK (0x2000000U)
+#define AIPS_MPRA_MTW1_SHIFT (25U)
+/*! MTW1 - Master 1 Trusted for Writes
+ * 0b0..This master is not trusted for write accesses.
+ * 0b1..This master is trusted for write accesses.
+ */
+#define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
+#define AIPS_MPRA_MTR1_MASK (0x4000000U)
+#define AIPS_MPRA_MTR1_SHIFT (26U)
+/*! MTR1 - Master 1 Trusted for Read
+ * 0b0..This master is not trusted for read accesses.
+ * 0b1..This master is trusted for read accesses.
+ */
+#define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
+#define AIPS_MPRA_MPL0_MASK (0x10000000U)
+#define AIPS_MPRA_MPL0_SHIFT (28U)
+/*! MPL0 - Master 0 Privilege Level
+ * 0b0..Accesses from this master are forced to user-mode.
+ * 0b1..Accesses from this master are not forced to user-mode.
+ */
+#define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
+#define AIPS_MPRA_MTW0_MASK (0x20000000U)
+#define AIPS_MPRA_MTW0_SHIFT (29U)
+/*! MTW0 - Master 0 Trusted For Writes
+ * 0b0..This master is not trusted for write accesses.
+ * 0b1..This master is trusted for write accesses.
+ */
+#define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
+#define AIPS_MPRA_MTR0_MASK (0x40000000U)
+#define AIPS_MPRA_MTR0_SHIFT (30U)
+/*! MTR0 - Master 0 Trusted For Read
+ * 0b0..This master is not trusted for read accesses.
+ * 0b1..This master is trusted for read accesses.
+ */
+#define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
+/*! @} */
+
+/*! @name PACRA - Peripheral Access Control Register */
+/*! @{ */
+#define AIPS_PACRA_TP7_MASK (0x1U)
+#define AIPS_PACRA_TP7_SHIFT (0U)
+/*! TP7 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
+#define AIPS_PACRA_WP7_MASK (0x2U)
+#define AIPS_PACRA_WP7_SHIFT (1U)
+/*! WP7 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
+#define AIPS_PACRA_SP7_MASK (0x4U)
+#define AIPS_PACRA_SP7_SHIFT (2U)
+/*! SP7 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
+#define AIPS_PACRA_TP6_MASK (0x10U)
+#define AIPS_PACRA_TP6_SHIFT (4U)
+/*! TP6 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
+#define AIPS_PACRA_WP6_MASK (0x20U)
+#define AIPS_PACRA_WP6_SHIFT (5U)
+/*! WP6 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
+#define AIPS_PACRA_SP6_MASK (0x40U)
+#define AIPS_PACRA_SP6_SHIFT (6U)
+/*! SP6 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
+#define AIPS_PACRA_TP5_MASK (0x100U)
+#define AIPS_PACRA_TP5_SHIFT (8U)
+/*! TP5 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
+#define AIPS_PACRA_WP5_MASK (0x200U)
+#define AIPS_PACRA_WP5_SHIFT (9U)
+/*! WP5 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
+#define AIPS_PACRA_SP5_MASK (0x400U)
+#define AIPS_PACRA_SP5_SHIFT (10U)
+/*! SP5 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
+#define AIPS_PACRA_TP4_MASK (0x1000U)
+#define AIPS_PACRA_TP4_SHIFT (12U)
+/*! TP4 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
+#define AIPS_PACRA_WP4_MASK (0x2000U)
+#define AIPS_PACRA_WP4_SHIFT (13U)
+/*! WP4 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
+#define AIPS_PACRA_SP4_MASK (0x4000U)
+#define AIPS_PACRA_SP4_SHIFT (14U)
+/*! SP4 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
+#define AIPS_PACRA_TP3_MASK (0x10000U)
+#define AIPS_PACRA_TP3_SHIFT (16U)
+/*! TP3 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
+#define AIPS_PACRA_WP3_MASK (0x20000U)
+#define AIPS_PACRA_WP3_SHIFT (17U)
+/*! WP3 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
+#define AIPS_PACRA_SP3_MASK (0x40000U)
+#define AIPS_PACRA_SP3_SHIFT (18U)
+/*! SP3 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
+#define AIPS_PACRA_TP2_MASK (0x100000U)
+#define AIPS_PACRA_TP2_SHIFT (20U)
+/*! TP2 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
+#define AIPS_PACRA_WP2_MASK (0x200000U)
+#define AIPS_PACRA_WP2_SHIFT (21U)
+/*! WP2 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
+#define AIPS_PACRA_SP2_MASK (0x400000U)
+#define AIPS_PACRA_SP2_SHIFT (22U)
+/*! SP2 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
+#define AIPS_PACRA_TP1_MASK (0x1000000U)
+#define AIPS_PACRA_TP1_SHIFT (24U)
+/*! TP1 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
+#define AIPS_PACRA_WP1_MASK (0x2000000U)
+#define AIPS_PACRA_WP1_SHIFT (25U)
+/*! WP1 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
+#define AIPS_PACRA_SP1_MASK (0x4000000U)
+#define AIPS_PACRA_SP1_SHIFT (26U)
+/*! SP1 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
+#define AIPS_PACRA_TP0_MASK (0x10000000U)
+#define AIPS_PACRA_TP0_SHIFT (28U)
+/*! TP0 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
+#define AIPS_PACRA_WP0_MASK (0x20000000U)
+#define AIPS_PACRA_WP0_SHIFT (29U)
+/*! WP0 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
+#define AIPS_PACRA_SP0_MASK (0x40000000U)
+#define AIPS_PACRA_SP0_SHIFT (30U)
+/*! SP0 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
+/*! @} */
+
+/*! @name PACRB - Peripheral Access Control Register */
+/*! @{ */
+#define AIPS_PACRB_TP7_MASK (0x1U)
+#define AIPS_PACRB_TP7_SHIFT (0U)
+/*! TP7 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
+#define AIPS_PACRB_WP7_MASK (0x2U)
+#define AIPS_PACRB_WP7_SHIFT (1U)
+/*! WP7 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
+#define AIPS_PACRB_SP7_MASK (0x4U)
+#define AIPS_PACRB_SP7_SHIFT (2U)
+/*! SP7 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
+#define AIPS_PACRB_TP6_MASK (0x10U)
+#define AIPS_PACRB_TP6_SHIFT (4U)
+/*! TP6 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
+#define AIPS_PACRB_WP6_MASK (0x20U)
+#define AIPS_PACRB_WP6_SHIFT (5U)
+/*! WP6 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
+#define AIPS_PACRB_SP6_MASK (0x40U)
+#define AIPS_PACRB_SP6_SHIFT (6U)
+/*! SP6 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
+#define AIPS_PACRB_TP5_MASK (0x100U)
+#define AIPS_PACRB_TP5_SHIFT (8U)
+/*! TP5 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
+#define AIPS_PACRB_WP5_MASK (0x200U)
+#define AIPS_PACRB_WP5_SHIFT (9U)
+/*! WP5 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
+#define AIPS_PACRB_SP5_MASK (0x400U)
+#define AIPS_PACRB_SP5_SHIFT (10U)
+/*! SP5 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
+#define AIPS_PACRB_TP4_MASK (0x1000U)
+#define AIPS_PACRB_TP4_SHIFT (12U)
+/*! TP4 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
+#define AIPS_PACRB_WP4_MASK (0x2000U)
+#define AIPS_PACRB_WP4_SHIFT (13U)
+/*! WP4 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
+#define AIPS_PACRB_SP4_MASK (0x4000U)
+#define AIPS_PACRB_SP4_SHIFT (14U)
+/*! SP4 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
+#define AIPS_PACRB_TP3_MASK (0x10000U)
+#define AIPS_PACRB_TP3_SHIFT (16U)
+/*! TP3 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
+#define AIPS_PACRB_WP3_MASK (0x20000U)
+#define AIPS_PACRB_WP3_SHIFT (17U)
+/*! WP3 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
+#define AIPS_PACRB_SP3_MASK (0x40000U)
+#define AIPS_PACRB_SP3_SHIFT (18U)
+/*! SP3 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
+#define AIPS_PACRB_TP2_MASK (0x100000U)
+#define AIPS_PACRB_TP2_SHIFT (20U)
+/*! TP2 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
+#define AIPS_PACRB_WP2_MASK (0x200000U)
+#define AIPS_PACRB_WP2_SHIFT (21U)
+/*! WP2 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
+#define AIPS_PACRB_SP2_MASK (0x400000U)
+#define AIPS_PACRB_SP2_SHIFT (22U)
+/*! SP2 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
+#define AIPS_PACRB_TP1_MASK (0x1000000U)
+#define AIPS_PACRB_TP1_SHIFT (24U)
+/*! TP1 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
+#define AIPS_PACRB_WP1_MASK (0x2000000U)
+#define AIPS_PACRB_WP1_SHIFT (25U)
+/*! WP1 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
+#define AIPS_PACRB_SP1_MASK (0x4000000U)
+#define AIPS_PACRB_SP1_SHIFT (26U)
+/*! SP1 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
+#define AIPS_PACRB_TP0_MASK (0x10000000U)
+#define AIPS_PACRB_TP0_SHIFT (28U)
+/*! TP0 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
+#define AIPS_PACRB_WP0_MASK (0x20000000U)
+#define AIPS_PACRB_WP0_SHIFT (29U)
+/*! WP0 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
+#define AIPS_PACRB_SP0_MASK (0x40000000U)
+#define AIPS_PACRB_SP0_SHIFT (30U)
+/*! SP0 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
+/*! @} */
+
+/*! @name PACRC - Peripheral Access Control Register */
+/*! @{ */
+#define AIPS_PACRC_TP7_MASK (0x1U)
+#define AIPS_PACRC_TP7_SHIFT (0U)
+/*! TP7 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
+#define AIPS_PACRC_WP7_MASK (0x2U)
+#define AIPS_PACRC_WP7_SHIFT (1U)
+/*! WP7 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
+#define AIPS_PACRC_SP7_MASK (0x4U)
+#define AIPS_PACRC_SP7_SHIFT (2U)
+/*! SP7 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
+#define AIPS_PACRC_TP6_MASK (0x10U)
+#define AIPS_PACRC_TP6_SHIFT (4U)
+/*! TP6 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
+#define AIPS_PACRC_WP6_MASK (0x20U)
+#define AIPS_PACRC_WP6_SHIFT (5U)
+/*! WP6 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
+#define AIPS_PACRC_SP6_MASK (0x40U)
+#define AIPS_PACRC_SP6_SHIFT (6U)
+/*! SP6 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
+#define AIPS_PACRC_TP5_MASK (0x100U)
+#define AIPS_PACRC_TP5_SHIFT (8U)
+/*! TP5 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
+#define AIPS_PACRC_WP5_MASK (0x200U)
+#define AIPS_PACRC_WP5_SHIFT (9U)
+/*! WP5 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
+#define AIPS_PACRC_SP5_MASK (0x400U)
+#define AIPS_PACRC_SP5_SHIFT (10U)
+/*! SP5 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
+#define AIPS_PACRC_TP4_MASK (0x1000U)
+#define AIPS_PACRC_TP4_SHIFT (12U)
+/*! TP4 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
+#define AIPS_PACRC_WP4_MASK (0x2000U)
+#define AIPS_PACRC_WP4_SHIFT (13U)
+/*! WP4 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
+#define AIPS_PACRC_SP4_MASK (0x4000U)
+#define AIPS_PACRC_SP4_SHIFT (14U)
+/*! SP4 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
+#define AIPS_PACRC_TP3_MASK (0x10000U)
+#define AIPS_PACRC_TP3_SHIFT (16U)
+/*! TP3 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
+#define AIPS_PACRC_WP3_MASK (0x20000U)
+#define AIPS_PACRC_WP3_SHIFT (17U)
+/*! WP3 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
+#define AIPS_PACRC_SP3_MASK (0x40000U)
+#define AIPS_PACRC_SP3_SHIFT (18U)
+/*! SP3 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
+#define AIPS_PACRC_TP2_MASK (0x100000U)
+#define AIPS_PACRC_TP2_SHIFT (20U)
+/*! TP2 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
+#define AIPS_PACRC_WP2_MASK (0x200000U)
+#define AIPS_PACRC_WP2_SHIFT (21U)
+/*! WP2 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
+#define AIPS_PACRC_SP2_MASK (0x400000U)
+#define AIPS_PACRC_SP2_SHIFT (22U)
+/*! SP2 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
+#define AIPS_PACRC_TP1_MASK (0x1000000U)
+#define AIPS_PACRC_TP1_SHIFT (24U)
+/*! TP1 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
+#define AIPS_PACRC_WP1_MASK (0x2000000U)
+#define AIPS_PACRC_WP1_SHIFT (25U)
+/*! WP1 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
+#define AIPS_PACRC_SP1_MASK (0x4000000U)
+#define AIPS_PACRC_SP1_SHIFT (26U)
+/*! SP1 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
+#define AIPS_PACRC_TP0_MASK (0x10000000U)
+#define AIPS_PACRC_TP0_SHIFT (28U)
+/*! TP0 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
+#define AIPS_PACRC_WP0_MASK (0x20000000U)
+#define AIPS_PACRC_WP0_SHIFT (29U)
+/*! WP0 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
+#define AIPS_PACRC_SP0_MASK (0x40000000U)
+#define AIPS_PACRC_SP0_SHIFT (30U)
+/*! SP0 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
+/*! @} */
+
+/*! @name PACRD - Peripheral Access Control Register */
+/*! @{ */
+#define AIPS_PACRD_TP7_MASK (0x1U)
+#define AIPS_PACRD_TP7_SHIFT (0U)
+/*! TP7 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
+#define AIPS_PACRD_WP7_MASK (0x2U)
+#define AIPS_PACRD_WP7_SHIFT (1U)
+/*! WP7 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
+#define AIPS_PACRD_SP7_MASK (0x4U)
+#define AIPS_PACRD_SP7_SHIFT (2U)
+/*! SP7 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
+#define AIPS_PACRD_TP6_MASK (0x10U)
+#define AIPS_PACRD_TP6_SHIFT (4U)
+/*! TP6 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
+#define AIPS_PACRD_WP6_MASK (0x20U)
+#define AIPS_PACRD_WP6_SHIFT (5U)
+/*! WP6 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
+#define AIPS_PACRD_SP6_MASK (0x40U)
+#define AIPS_PACRD_SP6_SHIFT (6U)
+/*! SP6 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
+#define AIPS_PACRD_TP5_MASK (0x100U)
+#define AIPS_PACRD_TP5_SHIFT (8U)
+/*! TP5 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
+#define AIPS_PACRD_WP5_MASK (0x200U)
+#define AIPS_PACRD_WP5_SHIFT (9U)
+/*! WP5 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
+#define AIPS_PACRD_SP5_MASK (0x400U)
+#define AIPS_PACRD_SP5_SHIFT (10U)
+/*! SP5 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
+#define AIPS_PACRD_TP4_MASK (0x1000U)
+#define AIPS_PACRD_TP4_SHIFT (12U)
+/*! TP4 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
+#define AIPS_PACRD_WP4_MASK (0x2000U)
+#define AIPS_PACRD_WP4_SHIFT (13U)
+/*! WP4 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
+#define AIPS_PACRD_SP4_MASK (0x4000U)
+#define AIPS_PACRD_SP4_SHIFT (14U)
+/*! SP4 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
+#define AIPS_PACRD_TP3_MASK (0x10000U)
+#define AIPS_PACRD_TP3_SHIFT (16U)
+/*! TP3 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
+#define AIPS_PACRD_WP3_MASK (0x20000U)
+#define AIPS_PACRD_WP3_SHIFT (17U)
+/*! WP3 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
+#define AIPS_PACRD_SP3_MASK (0x40000U)
+#define AIPS_PACRD_SP3_SHIFT (18U)
+/*! SP3 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
+#define AIPS_PACRD_TP2_MASK (0x100000U)
+#define AIPS_PACRD_TP2_SHIFT (20U)
+/*! TP2 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
+#define AIPS_PACRD_WP2_MASK (0x200000U)
+#define AIPS_PACRD_WP2_SHIFT (21U)
+/*! WP2 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
+#define AIPS_PACRD_SP2_MASK (0x400000U)
+#define AIPS_PACRD_SP2_SHIFT (22U)
+/*! SP2 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
+#define AIPS_PACRD_TP1_MASK (0x1000000U)
+#define AIPS_PACRD_TP1_SHIFT (24U)
+/*! TP1 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
+#define AIPS_PACRD_WP1_MASK (0x2000000U)
+#define AIPS_PACRD_WP1_SHIFT (25U)
+/*! WP1 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
+#define AIPS_PACRD_SP1_MASK (0x4000000U)
+#define AIPS_PACRD_SP1_SHIFT (26U)
+/*! SP1 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
+#define AIPS_PACRD_TP0_MASK (0x10000000U)
+#define AIPS_PACRD_TP0_SHIFT (28U)
+/*! TP0 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
+#define AIPS_PACRD_WP0_MASK (0x20000000U)
+#define AIPS_PACRD_WP0_SHIFT (29U)
+/*! WP0 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
+#define AIPS_PACRD_SP0_MASK (0x40000000U)
+#define AIPS_PACRD_SP0_SHIFT (30U)
+/*! SP0 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
+/*! @} */
+
+/*! @name PACRE - Peripheral Access Control Register */
+/*! @{ */
+#define AIPS_PACRE_TP7_MASK (0x1U)
+#define AIPS_PACRE_TP7_SHIFT (0U)
+/*! TP7 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
+#define AIPS_PACRE_WP7_MASK (0x2U)
+#define AIPS_PACRE_WP7_SHIFT (1U)
+/*! WP7 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
+#define AIPS_PACRE_SP7_MASK (0x4U)
+#define AIPS_PACRE_SP7_SHIFT (2U)
+/*! SP7 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
+#define AIPS_PACRE_TP6_MASK (0x10U)
+#define AIPS_PACRE_TP6_SHIFT (4U)
+/*! TP6 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
+#define AIPS_PACRE_WP6_MASK (0x20U)
+#define AIPS_PACRE_WP6_SHIFT (5U)
+/*! WP6 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
+#define AIPS_PACRE_SP6_MASK (0x40U)
+#define AIPS_PACRE_SP6_SHIFT (6U)
+/*! SP6 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
+#define AIPS_PACRE_TP5_MASK (0x100U)
+#define AIPS_PACRE_TP5_SHIFT (8U)
+/*! TP5 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
+#define AIPS_PACRE_WP5_MASK (0x200U)
+#define AIPS_PACRE_WP5_SHIFT (9U)
+/*! WP5 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
+#define AIPS_PACRE_SP5_MASK (0x400U)
+#define AIPS_PACRE_SP5_SHIFT (10U)
+/*! SP5 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
+#define AIPS_PACRE_TP4_MASK (0x1000U)
+#define AIPS_PACRE_TP4_SHIFT (12U)
+/*! TP4 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
+#define AIPS_PACRE_WP4_MASK (0x2000U)
+#define AIPS_PACRE_WP4_SHIFT (13U)
+/*! WP4 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
+#define AIPS_PACRE_SP4_MASK (0x4000U)
+#define AIPS_PACRE_SP4_SHIFT (14U)
+/*! SP4 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
+#define AIPS_PACRE_TP3_MASK (0x10000U)
+#define AIPS_PACRE_TP3_SHIFT (16U)
+/*! TP3 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
+#define AIPS_PACRE_WP3_MASK (0x20000U)
+#define AIPS_PACRE_WP3_SHIFT (17U)
+/*! WP3 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
+#define AIPS_PACRE_SP3_MASK (0x40000U)
+#define AIPS_PACRE_SP3_SHIFT (18U)
+/*! SP3 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
+#define AIPS_PACRE_TP2_MASK (0x100000U)
+#define AIPS_PACRE_TP2_SHIFT (20U)
+/*! TP2 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
+#define AIPS_PACRE_WP2_MASK (0x200000U)
+#define AIPS_PACRE_WP2_SHIFT (21U)
+/*! WP2 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
+#define AIPS_PACRE_SP2_MASK (0x400000U)
+#define AIPS_PACRE_SP2_SHIFT (22U)
+/*! SP2 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
+#define AIPS_PACRE_TP1_MASK (0x1000000U)
+#define AIPS_PACRE_TP1_SHIFT (24U)
+/*! TP1 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
+#define AIPS_PACRE_WP1_MASK (0x2000000U)
+#define AIPS_PACRE_WP1_SHIFT (25U)
+/*! WP1 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
+#define AIPS_PACRE_SP1_MASK (0x4000000U)
+#define AIPS_PACRE_SP1_SHIFT (26U)
+/*! SP1 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
+#define AIPS_PACRE_TP0_MASK (0x10000000U)
+#define AIPS_PACRE_TP0_SHIFT (28U)
+/*! TP0 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
+#define AIPS_PACRE_WP0_MASK (0x20000000U)
+#define AIPS_PACRE_WP0_SHIFT (29U)
+/*! WP0 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
+#define AIPS_PACRE_SP0_MASK (0x40000000U)
+#define AIPS_PACRE_SP0_SHIFT (30U)
+/*! SP0 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
+/*! @} */
+
+/*! @name PACRF - Peripheral Access Control Register */
+/*! @{ */
+#define AIPS_PACRF_TP7_MASK (0x1U)
+#define AIPS_PACRF_TP7_SHIFT (0U)
+/*! TP7 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
+#define AIPS_PACRF_WP7_MASK (0x2U)
+#define AIPS_PACRF_WP7_SHIFT (1U)
+/*! WP7 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
+#define AIPS_PACRF_SP7_MASK (0x4U)
+#define AIPS_PACRF_SP7_SHIFT (2U)
+/*! SP7 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
+#define AIPS_PACRF_TP6_MASK (0x10U)
+#define AIPS_PACRF_TP6_SHIFT (4U)
+/*! TP6 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
+#define AIPS_PACRF_WP6_MASK (0x20U)
+#define AIPS_PACRF_WP6_SHIFT (5U)
+/*! WP6 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
+#define AIPS_PACRF_SP6_MASK (0x40U)
+#define AIPS_PACRF_SP6_SHIFT (6U)
+/*! SP6 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
+#define AIPS_PACRF_TP5_MASK (0x100U)
+#define AIPS_PACRF_TP5_SHIFT (8U)
+/*! TP5 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
+#define AIPS_PACRF_WP5_MASK (0x200U)
+#define AIPS_PACRF_WP5_SHIFT (9U)
+/*! WP5 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
+#define AIPS_PACRF_SP5_MASK (0x400U)
+#define AIPS_PACRF_SP5_SHIFT (10U)
+/*! SP5 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
+#define AIPS_PACRF_TP4_MASK (0x1000U)
+#define AIPS_PACRF_TP4_SHIFT (12U)
+/*! TP4 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
+#define AIPS_PACRF_WP4_MASK (0x2000U)
+#define AIPS_PACRF_WP4_SHIFT (13U)
+/*! WP4 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
+#define AIPS_PACRF_SP4_MASK (0x4000U)
+#define AIPS_PACRF_SP4_SHIFT (14U)
+/*! SP4 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
+#define AIPS_PACRF_TP3_MASK (0x10000U)
+#define AIPS_PACRF_TP3_SHIFT (16U)
+/*! TP3 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
+#define AIPS_PACRF_WP3_MASK (0x20000U)
+#define AIPS_PACRF_WP3_SHIFT (17U)
+/*! WP3 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
+#define AIPS_PACRF_SP3_MASK (0x40000U)
+#define AIPS_PACRF_SP3_SHIFT (18U)
+/*! SP3 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
+#define AIPS_PACRF_TP2_MASK (0x100000U)
+#define AIPS_PACRF_TP2_SHIFT (20U)
+/*! TP2 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
+#define AIPS_PACRF_WP2_MASK (0x200000U)
+#define AIPS_PACRF_WP2_SHIFT (21U)
+/*! WP2 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
+#define AIPS_PACRF_SP2_MASK (0x400000U)
+#define AIPS_PACRF_SP2_SHIFT (22U)
+/*! SP2 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
+#define AIPS_PACRF_TP1_MASK (0x1000000U)
+#define AIPS_PACRF_TP1_SHIFT (24U)
+/*! TP1 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
+#define AIPS_PACRF_WP1_MASK (0x2000000U)
+#define AIPS_PACRF_WP1_SHIFT (25U)
+/*! WP1 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
+#define AIPS_PACRF_SP1_MASK (0x4000000U)
+#define AIPS_PACRF_SP1_SHIFT (26U)
+/*! SP1 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
+#define AIPS_PACRF_TP0_MASK (0x10000000U)
+#define AIPS_PACRF_TP0_SHIFT (28U)
+/*! TP0 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
+#define AIPS_PACRF_WP0_MASK (0x20000000U)
+#define AIPS_PACRF_WP0_SHIFT (29U)
+/*! WP0 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
+#define AIPS_PACRF_SP0_MASK (0x40000000U)
+#define AIPS_PACRF_SP0_SHIFT (30U)
+/*! SP0 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
+/*! @} */
+
+/*! @name PACRG - Peripheral Access Control Register */
+/*! @{ */
+#define AIPS_PACRG_TP7_MASK (0x1U)
+#define AIPS_PACRG_TP7_SHIFT (0U)
+/*! TP7 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
+#define AIPS_PACRG_WP7_MASK (0x2U)
+#define AIPS_PACRG_WP7_SHIFT (1U)
+/*! WP7 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
+#define AIPS_PACRG_SP7_MASK (0x4U)
+#define AIPS_PACRG_SP7_SHIFT (2U)
+/*! SP7 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
+#define AIPS_PACRG_TP6_MASK (0x10U)
+#define AIPS_PACRG_TP6_SHIFT (4U)
+/*! TP6 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
+#define AIPS_PACRG_WP6_MASK (0x20U)
+#define AIPS_PACRG_WP6_SHIFT (5U)
+/*! WP6 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
+#define AIPS_PACRG_SP6_MASK (0x40U)
+#define AIPS_PACRG_SP6_SHIFT (6U)
+/*! SP6 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
+#define AIPS_PACRG_TP5_MASK (0x100U)
+#define AIPS_PACRG_TP5_SHIFT (8U)
+/*! TP5 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
+#define AIPS_PACRG_WP5_MASK (0x200U)
+#define AIPS_PACRG_WP5_SHIFT (9U)
+/*! WP5 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
+#define AIPS_PACRG_SP5_MASK (0x400U)
+#define AIPS_PACRG_SP5_SHIFT (10U)
+/*! SP5 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
+#define AIPS_PACRG_TP4_MASK (0x1000U)
+#define AIPS_PACRG_TP4_SHIFT (12U)
+/*! TP4 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
+#define AIPS_PACRG_WP4_MASK (0x2000U)
+#define AIPS_PACRG_WP4_SHIFT (13U)
+/*! WP4 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
+#define AIPS_PACRG_SP4_MASK (0x4000U)
+#define AIPS_PACRG_SP4_SHIFT (14U)
+/*! SP4 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
+#define AIPS_PACRG_TP3_MASK (0x10000U)
+#define AIPS_PACRG_TP3_SHIFT (16U)
+/*! TP3 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
+#define AIPS_PACRG_WP3_MASK (0x20000U)
+#define AIPS_PACRG_WP3_SHIFT (17U)
+/*! WP3 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
+#define AIPS_PACRG_SP3_MASK (0x40000U)
+#define AIPS_PACRG_SP3_SHIFT (18U)
+/*! SP3 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
+#define AIPS_PACRG_TP2_MASK (0x100000U)
+#define AIPS_PACRG_TP2_SHIFT (20U)
+/*! TP2 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
+#define AIPS_PACRG_WP2_MASK (0x200000U)
+#define AIPS_PACRG_WP2_SHIFT (21U)
+/*! WP2 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
+#define AIPS_PACRG_SP2_MASK (0x400000U)
+#define AIPS_PACRG_SP2_SHIFT (22U)
+/*! SP2 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
+#define AIPS_PACRG_TP1_MASK (0x1000000U)
+#define AIPS_PACRG_TP1_SHIFT (24U)
+/*! TP1 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
+#define AIPS_PACRG_WP1_MASK (0x2000000U)
+#define AIPS_PACRG_WP1_SHIFT (25U)
+/*! WP1 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
+#define AIPS_PACRG_SP1_MASK (0x4000000U)
+#define AIPS_PACRG_SP1_SHIFT (26U)
+/*! SP1 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
+#define AIPS_PACRG_TP0_MASK (0x10000000U)
+#define AIPS_PACRG_TP0_SHIFT (28U)
+/*! TP0 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
+#define AIPS_PACRG_WP0_MASK (0x20000000U)
+#define AIPS_PACRG_WP0_SHIFT (29U)
+/*! WP0 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
+#define AIPS_PACRG_SP0_MASK (0x40000000U)
+#define AIPS_PACRG_SP0_SHIFT (30U)
+/*! SP0 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
+/*! @} */
+
+/*! @name PACRH - Peripheral Access Control Register */
+/*! @{ */
+#define AIPS_PACRH_TP7_MASK (0x1U)
+#define AIPS_PACRH_TP7_SHIFT (0U)
+/*! TP7 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
+#define AIPS_PACRH_WP7_MASK (0x2U)
+#define AIPS_PACRH_WP7_SHIFT (1U)
+/*! WP7 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
+#define AIPS_PACRH_SP7_MASK (0x4U)
+#define AIPS_PACRH_SP7_SHIFT (2U)
+/*! SP7 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
+#define AIPS_PACRH_TP6_MASK (0x10U)
+#define AIPS_PACRH_TP6_SHIFT (4U)
+/*! TP6 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
+#define AIPS_PACRH_WP6_MASK (0x20U)
+#define AIPS_PACRH_WP6_SHIFT (5U)
+/*! WP6 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
+#define AIPS_PACRH_SP6_MASK (0x40U)
+#define AIPS_PACRH_SP6_SHIFT (6U)
+/*! SP6 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
+#define AIPS_PACRH_TP5_MASK (0x100U)
+#define AIPS_PACRH_TP5_SHIFT (8U)
+/*! TP5 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
+#define AIPS_PACRH_WP5_MASK (0x200U)
+#define AIPS_PACRH_WP5_SHIFT (9U)
+/*! WP5 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
+#define AIPS_PACRH_SP5_MASK (0x400U)
+#define AIPS_PACRH_SP5_SHIFT (10U)
+/*! SP5 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
+#define AIPS_PACRH_TP4_MASK (0x1000U)
+#define AIPS_PACRH_TP4_SHIFT (12U)
+/*! TP4 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
+#define AIPS_PACRH_WP4_MASK (0x2000U)
+#define AIPS_PACRH_WP4_SHIFT (13U)
+/*! WP4 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
+#define AIPS_PACRH_SP4_MASK (0x4000U)
+#define AIPS_PACRH_SP4_SHIFT (14U)
+/*! SP4 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
+#define AIPS_PACRH_TP3_MASK (0x10000U)
+#define AIPS_PACRH_TP3_SHIFT (16U)
+/*! TP3 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
+#define AIPS_PACRH_WP3_MASK (0x20000U)
+#define AIPS_PACRH_WP3_SHIFT (17U)
+/*! WP3 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
+#define AIPS_PACRH_SP3_MASK (0x40000U)
+#define AIPS_PACRH_SP3_SHIFT (18U)
+/*! SP3 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
+#define AIPS_PACRH_TP2_MASK (0x100000U)
+#define AIPS_PACRH_TP2_SHIFT (20U)
+/*! TP2 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
+#define AIPS_PACRH_WP2_MASK (0x200000U)
+#define AIPS_PACRH_WP2_SHIFT (21U)
+/*! WP2 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
+#define AIPS_PACRH_SP2_MASK (0x400000U)
+#define AIPS_PACRH_SP2_SHIFT (22U)
+/*! SP2 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
+#define AIPS_PACRH_TP1_MASK (0x1000000U)
+#define AIPS_PACRH_TP1_SHIFT (24U)
+/*! TP1 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
+#define AIPS_PACRH_WP1_MASK (0x2000000U)
+#define AIPS_PACRH_WP1_SHIFT (25U)
+/*! WP1 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
+#define AIPS_PACRH_SP1_MASK (0x4000000U)
+#define AIPS_PACRH_SP1_SHIFT (26U)
+/*! SP1 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
+#define AIPS_PACRH_TP0_MASK (0x10000000U)
+#define AIPS_PACRH_TP0_SHIFT (28U)
+/*! TP0 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
+#define AIPS_PACRH_WP0_MASK (0x20000000U)
+#define AIPS_PACRH_WP0_SHIFT (29U)
+/*! WP0 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
+#define AIPS_PACRH_SP0_MASK (0x40000000U)
+#define AIPS_PACRH_SP0_SHIFT (30U)
+/*! SP0 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
+/*! @} */
+
+/*! @name PACRI - Peripheral Access Control Register */
+/*! @{ */
+#define AIPS_PACRI_TP7_MASK (0x1U)
+#define AIPS_PACRI_TP7_SHIFT (0U)
+/*! TP7 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
+#define AIPS_PACRI_WP7_MASK (0x2U)
+#define AIPS_PACRI_WP7_SHIFT (1U)
+/*! WP7 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
+#define AIPS_PACRI_SP7_MASK (0x4U)
+#define AIPS_PACRI_SP7_SHIFT (2U)
+/*! SP7 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
+#define AIPS_PACRI_TP6_MASK (0x10U)
+#define AIPS_PACRI_TP6_SHIFT (4U)
+/*! TP6 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
+#define AIPS_PACRI_WP6_MASK (0x20U)
+#define AIPS_PACRI_WP6_SHIFT (5U)
+/*! WP6 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
+#define AIPS_PACRI_SP6_MASK (0x40U)
+#define AIPS_PACRI_SP6_SHIFT (6U)
+/*! SP6 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
+#define AIPS_PACRI_TP5_MASK (0x100U)
+#define AIPS_PACRI_TP5_SHIFT (8U)
+/*! TP5 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
+#define AIPS_PACRI_WP5_MASK (0x200U)
+#define AIPS_PACRI_WP5_SHIFT (9U)
+/*! WP5 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
+#define AIPS_PACRI_SP5_MASK (0x400U)
+#define AIPS_PACRI_SP5_SHIFT (10U)
+/*! SP5 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
+#define AIPS_PACRI_TP4_MASK (0x1000U)
+#define AIPS_PACRI_TP4_SHIFT (12U)
+/*! TP4 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
+#define AIPS_PACRI_WP4_MASK (0x2000U)
+#define AIPS_PACRI_WP4_SHIFT (13U)
+/*! WP4 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
+#define AIPS_PACRI_SP4_MASK (0x4000U)
+#define AIPS_PACRI_SP4_SHIFT (14U)
+/*! SP4 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
+#define AIPS_PACRI_TP3_MASK (0x10000U)
+#define AIPS_PACRI_TP3_SHIFT (16U)
+/*! TP3 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
+#define AIPS_PACRI_WP3_MASK (0x20000U)
+#define AIPS_PACRI_WP3_SHIFT (17U)
+/*! WP3 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
+#define AIPS_PACRI_SP3_MASK (0x40000U)
+#define AIPS_PACRI_SP3_SHIFT (18U)
+/*! SP3 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
+#define AIPS_PACRI_TP2_MASK (0x100000U)
+#define AIPS_PACRI_TP2_SHIFT (20U)
+/*! TP2 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
+#define AIPS_PACRI_WP2_MASK (0x200000U)
+#define AIPS_PACRI_WP2_SHIFT (21U)
+/*! WP2 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
+#define AIPS_PACRI_SP2_MASK (0x400000U)
+#define AIPS_PACRI_SP2_SHIFT (22U)
+/*! SP2 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
+#define AIPS_PACRI_TP1_MASK (0x1000000U)
+#define AIPS_PACRI_TP1_SHIFT (24U)
+/*! TP1 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
+#define AIPS_PACRI_WP1_MASK (0x2000000U)
+#define AIPS_PACRI_WP1_SHIFT (25U)
+/*! WP1 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
+#define AIPS_PACRI_SP1_MASK (0x4000000U)
+#define AIPS_PACRI_SP1_SHIFT (26U)
+/*! SP1 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
+#define AIPS_PACRI_TP0_MASK (0x10000000U)
+#define AIPS_PACRI_TP0_SHIFT (28U)
+/*! TP0 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
+#define AIPS_PACRI_WP0_MASK (0x20000000U)
+#define AIPS_PACRI_WP0_SHIFT (29U)
+/*! WP0 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
+#define AIPS_PACRI_SP0_MASK (0x40000000U)
+#define AIPS_PACRI_SP0_SHIFT (30U)
+/*! SP0 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
+/*! @} */
+
+/*! @name PACRJ - Peripheral Access Control Register */
+/*! @{ */
+#define AIPS_PACRJ_TP7_MASK (0x1U)
+#define AIPS_PACRJ_TP7_SHIFT (0U)
+/*! TP7 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
+#define AIPS_PACRJ_WP7_MASK (0x2U)
+#define AIPS_PACRJ_WP7_SHIFT (1U)
+/*! WP7 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
+#define AIPS_PACRJ_SP7_MASK (0x4U)
+#define AIPS_PACRJ_SP7_SHIFT (2U)
+/*! SP7 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
+#define AIPS_PACRJ_TP6_MASK (0x10U)
+#define AIPS_PACRJ_TP6_SHIFT (4U)
+/*! TP6 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
+#define AIPS_PACRJ_WP6_MASK (0x20U)
+#define AIPS_PACRJ_WP6_SHIFT (5U)
+/*! WP6 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
+#define AIPS_PACRJ_SP6_MASK (0x40U)
+#define AIPS_PACRJ_SP6_SHIFT (6U)
+/*! SP6 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
+#define AIPS_PACRJ_TP5_MASK (0x100U)
+#define AIPS_PACRJ_TP5_SHIFT (8U)
+/*! TP5 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
+#define AIPS_PACRJ_WP5_MASK (0x200U)
+#define AIPS_PACRJ_WP5_SHIFT (9U)
+/*! WP5 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
+#define AIPS_PACRJ_SP5_MASK (0x400U)
+#define AIPS_PACRJ_SP5_SHIFT (10U)
+/*! SP5 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
+#define AIPS_PACRJ_TP4_MASK (0x1000U)
+#define AIPS_PACRJ_TP4_SHIFT (12U)
+/*! TP4 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
+#define AIPS_PACRJ_WP4_MASK (0x2000U)
+#define AIPS_PACRJ_WP4_SHIFT (13U)
+/*! WP4 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
+#define AIPS_PACRJ_SP4_MASK (0x4000U)
+#define AIPS_PACRJ_SP4_SHIFT (14U)
+/*! SP4 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
+#define AIPS_PACRJ_TP3_MASK (0x10000U)
+#define AIPS_PACRJ_TP3_SHIFT (16U)
+/*! TP3 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
+#define AIPS_PACRJ_WP3_MASK (0x20000U)
+#define AIPS_PACRJ_WP3_SHIFT (17U)
+/*! WP3 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
+#define AIPS_PACRJ_SP3_MASK (0x40000U)
+#define AIPS_PACRJ_SP3_SHIFT (18U)
+/*! SP3 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
+#define AIPS_PACRJ_TP2_MASK (0x100000U)
+#define AIPS_PACRJ_TP2_SHIFT (20U)
+/*! TP2 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
+#define AIPS_PACRJ_WP2_MASK (0x200000U)
+#define AIPS_PACRJ_WP2_SHIFT (21U)
+/*! WP2 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
+#define AIPS_PACRJ_SP2_MASK (0x400000U)
+#define AIPS_PACRJ_SP2_SHIFT (22U)
+/*! SP2 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
+#define AIPS_PACRJ_TP1_MASK (0x1000000U)
+#define AIPS_PACRJ_TP1_SHIFT (24U)
+/*! TP1 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
+#define AIPS_PACRJ_WP1_MASK (0x2000000U)
+#define AIPS_PACRJ_WP1_SHIFT (25U)
+/*! WP1 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
+#define AIPS_PACRJ_SP1_MASK (0x4000000U)
+#define AIPS_PACRJ_SP1_SHIFT (26U)
+/*! SP1 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
+#define AIPS_PACRJ_TP0_MASK (0x10000000U)
+#define AIPS_PACRJ_TP0_SHIFT (28U)
+/*! TP0 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
+#define AIPS_PACRJ_WP0_MASK (0x20000000U)
+#define AIPS_PACRJ_WP0_SHIFT (29U)
+/*! WP0 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
+#define AIPS_PACRJ_SP0_MASK (0x40000000U)
+#define AIPS_PACRJ_SP0_SHIFT (30U)
+/*! SP0 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
+/*! @} */
+
+/*! @name PACRK - Peripheral Access Control Register */
+/*! @{ */
+#define AIPS_PACRK_TP7_MASK (0x1U)
+#define AIPS_PACRK_TP7_SHIFT (0U)
+/*! TP7 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
+#define AIPS_PACRK_WP7_MASK (0x2U)
+#define AIPS_PACRK_WP7_SHIFT (1U)
+/*! WP7 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
+#define AIPS_PACRK_SP7_MASK (0x4U)
+#define AIPS_PACRK_SP7_SHIFT (2U)
+/*! SP7 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
+#define AIPS_PACRK_TP6_MASK (0x10U)
+#define AIPS_PACRK_TP6_SHIFT (4U)
+/*! TP6 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
+#define AIPS_PACRK_WP6_MASK (0x20U)
+#define AIPS_PACRK_WP6_SHIFT (5U)
+/*! WP6 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
+#define AIPS_PACRK_SP6_MASK (0x40U)
+#define AIPS_PACRK_SP6_SHIFT (6U)
+/*! SP6 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
+#define AIPS_PACRK_TP5_MASK (0x100U)
+#define AIPS_PACRK_TP5_SHIFT (8U)
+/*! TP5 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
+#define AIPS_PACRK_WP5_MASK (0x200U)
+#define AIPS_PACRK_WP5_SHIFT (9U)
+/*! WP5 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
+#define AIPS_PACRK_SP5_MASK (0x400U)
+#define AIPS_PACRK_SP5_SHIFT (10U)
+/*! SP5 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
+#define AIPS_PACRK_TP4_MASK (0x1000U)
+#define AIPS_PACRK_TP4_SHIFT (12U)
+/*! TP4 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
+#define AIPS_PACRK_WP4_MASK (0x2000U)
+#define AIPS_PACRK_WP4_SHIFT (13U)
+/*! WP4 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
+#define AIPS_PACRK_SP4_MASK (0x4000U)
+#define AIPS_PACRK_SP4_SHIFT (14U)
+/*! SP4 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
+#define AIPS_PACRK_TP3_MASK (0x10000U)
+#define AIPS_PACRK_TP3_SHIFT (16U)
+/*! TP3 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
+#define AIPS_PACRK_WP3_MASK (0x20000U)
+#define AIPS_PACRK_WP3_SHIFT (17U)
+/*! WP3 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
+#define AIPS_PACRK_SP3_MASK (0x40000U)
+#define AIPS_PACRK_SP3_SHIFT (18U)
+/*! SP3 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
+#define AIPS_PACRK_TP2_MASK (0x100000U)
+#define AIPS_PACRK_TP2_SHIFT (20U)
+/*! TP2 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
+#define AIPS_PACRK_WP2_MASK (0x200000U)
+#define AIPS_PACRK_WP2_SHIFT (21U)
+/*! WP2 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
+#define AIPS_PACRK_SP2_MASK (0x400000U)
+#define AIPS_PACRK_SP2_SHIFT (22U)
+/*! SP2 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
+#define AIPS_PACRK_TP1_MASK (0x1000000U)
+#define AIPS_PACRK_TP1_SHIFT (24U)
+/*! TP1 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
+#define AIPS_PACRK_WP1_MASK (0x2000000U)
+#define AIPS_PACRK_WP1_SHIFT (25U)
+/*! WP1 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
+#define AIPS_PACRK_SP1_MASK (0x4000000U)
+#define AIPS_PACRK_SP1_SHIFT (26U)
+/*! SP1 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
+#define AIPS_PACRK_TP0_MASK (0x10000000U)
+#define AIPS_PACRK_TP0_SHIFT (28U)
+/*! TP0 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
+#define AIPS_PACRK_WP0_MASK (0x20000000U)
+#define AIPS_PACRK_WP0_SHIFT (29U)
+/*! WP0 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
+#define AIPS_PACRK_SP0_MASK (0x40000000U)
+#define AIPS_PACRK_SP0_SHIFT (30U)
+/*! SP0 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
+/*! @} */
+
+/*! @name PACRL - Peripheral Access Control Register */
+/*! @{ */
+#define AIPS_PACRL_TP7_MASK (0x1U)
+#define AIPS_PACRL_TP7_SHIFT (0U)
+/*! TP7 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
+#define AIPS_PACRL_WP7_MASK (0x2U)
+#define AIPS_PACRL_WP7_SHIFT (1U)
+/*! WP7 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
+#define AIPS_PACRL_SP7_MASK (0x4U)
+#define AIPS_PACRL_SP7_SHIFT (2U)
+/*! SP7 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
+#define AIPS_PACRL_TP6_MASK (0x10U)
+#define AIPS_PACRL_TP6_SHIFT (4U)
+/*! TP6 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
+#define AIPS_PACRL_WP6_MASK (0x20U)
+#define AIPS_PACRL_WP6_SHIFT (5U)
+/*! WP6 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
+#define AIPS_PACRL_SP6_MASK (0x40U)
+#define AIPS_PACRL_SP6_SHIFT (6U)
+/*! SP6 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
+#define AIPS_PACRL_TP5_MASK (0x100U)
+#define AIPS_PACRL_TP5_SHIFT (8U)
+/*! TP5 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
+#define AIPS_PACRL_WP5_MASK (0x200U)
+#define AIPS_PACRL_WP5_SHIFT (9U)
+/*! WP5 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
+#define AIPS_PACRL_SP5_MASK (0x400U)
+#define AIPS_PACRL_SP5_SHIFT (10U)
+/*! SP5 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
+#define AIPS_PACRL_TP4_MASK (0x1000U)
+#define AIPS_PACRL_TP4_SHIFT (12U)
+/*! TP4 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
+#define AIPS_PACRL_WP4_MASK (0x2000U)
+#define AIPS_PACRL_WP4_SHIFT (13U)
+/*! WP4 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
+#define AIPS_PACRL_SP4_MASK (0x4000U)
+#define AIPS_PACRL_SP4_SHIFT (14U)
+/*! SP4 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
+#define AIPS_PACRL_TP3_MASK (0x10000U)
+#define AIPS_PACRL_TP3_SHIFT (16U)
+/*! TP3 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
+#define AIPS_PACRL_WP3_MASK (0x20000U)
+#define AIPS_PACRL_WP3_SHIFT (17U)
+/*! WP3 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
+#define AIPS_PACRL_SP3_MASK (0x40000U)
+#define AIPS_PACRL_SP3_SHIFT (18U)
+/*! SP3 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
+#define AIPS_PACRL_TP2_MASK (0x100000U)
+#define AIPS_PACRL_TP2_SHIFT (20U)
+/*! TP2 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
+#define AIPS_PACRL_WP2_MASK (0x200000U)
+#define AIPS_PACRL_WP2_SHIFT (21U)
+/*! WP2 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
+#define AIPS_PACRL_SP2_MASK (0x400000U)
+#define AIPS_PACRL_SP2_SHIFT (22U)
+/*! SP2 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
+#define AIPS_PACRL_TP1_MASK (0x1000000U)
+#define AIPS_PACRL_TP1_SHIFT (24U)
+/*! TP1 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
+#define AIPS_PACRL_WP1_MASK (0x2000000U)
+#define AIPS_PACRL_WP1_SHIFT (25U)
+/*! WP1 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
+#define AIPS_PACRL_SP1_MASK (0x4000000U)
+#define AIPS_PACRL_SP1_SHIFT (26U)
+/*! SP1 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
+#define AIPS_PACRL_TP0_MASK (0x10000000U)
+#define AIPS_PACRL_TP0_SHIFT (28U)
+/*! TP0 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
+#define AIPS_PACRL_WP0_MASK (0x20000000U)
+#define AIPS_PACRL_WP0_SHIFT (29U)
+/*! WP0 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
+#define AIPS_PACRL_SP0_MASK (0x40000000U)
+#define AIPS_PACRL_SP0_SHIFT (30U)
+/*! SP0 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
+/*! @} */
+
+/*! @name PACRM - Peripheral Access Control Register */
+/*! @{ */
+#define AIPS_PACRM_TP7_MASK (0x1U)
+#define AIPS_PACRM_TP7_SHIFT (0U)
+/*! TP7 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
+#define AIPS_PACRM_WP7_MASK (0x2U)
+#define AIPS_PACRM_WP7_SHIFT (1U)
+/*! WP7 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
+#define AIPS_PACRM_SP7_MASK (0x4U)
+#define AIPS_PACRM_SP7_SHIFT (2U)
+/*! SP7 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
+#define AIPS_PACRM_TP6_MASK (0x10U)
+#define AIPS_PACRM_TP6_SHIFT (4U)
+/*! TP6 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
+#define AIPS_PACRM_WP6_MASK (0x20U)
+#define AIPS_PACRM_WP6_SHIFT (5U)
+/*! WP6 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
+#define AIPS_PACRM_SP6_MASK (0x40U)
+#define AIPS_PACRM_SP6_SHIFT (6U)
+/*! SP6 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
+#define AIPS_PACRM_TP5_MASK (0x100U)
+#define AIPS_PACRM_TP5_SHIFT (8U)
+/*! TP5 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
+#define AIPS_PACRM_WP5_MASK (0x200U)
+#define AIPS_PACRM_WP5_SHIFT (9U)
+/*! WP5 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
+#define AIPS_PACRM_SP5_MASK (0x400U)
+#define AIPS_PACRM_SP5_SHIFT (10U)
+/*! SP5 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
+#define AIPS_PACRM_TP4_MASK (0x1000U)
+#define AIPS_PACRM_TP4_SHIFT (12U)
+/*! TP4 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
+#define AIPS_PACRM_WP4_MASK (0x2000U)
+#define AIPS_PACRM_WP4_SHIFT (13U)
+/*! WP4 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
+#define AIPS_PACRM_SP4_MASK (0x4000U)
+#define AIPS_PACRM_SP4_SHIFT (14U)
+/*! SP4 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
+#define AIPS_PACRM_TP3_MASK (0x10000U)
+#define AIPS_PACRM_TP3_SHIFT (16U)
+/*! TP3 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
+#define AIPS_PACRM_WP3_MASK (0x20000U)
+#define AIPS_PACRM_WP3_SHIFT (17U)
+/*! WP3 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
+#define AIPS_PACRM_SP3_MASK (0x40000U)
+#define AIPS_PACRM_SP3_SHIFT (18U)
+/*! SP3 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
+#define AIPS_PACRM_TP2_MASK (0x100000U)
+#define AIPS_PACRM_TP2_SHIFT (20U)
+/*! TP2 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
+#define AIPS_PACRM_WP2_MASK (0x200000U)
+#define AIPS_PACRM_WP2_SHIFT (21U)
+/*! WP2 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
+#define AIPS_PACRM_SP2_MASK (0x400000U)
+#define AIPS_PACRM_SP2_SHIFT (22U)
+/*! SP2 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
+#define AIPS_PACRM_TP1_MASK (0x1000000U)
+#define AIPS_PACRM_TP1_SHIFT (24U)
+/*! TP1 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
+#define AIPS_PACRM_WP1_MASK (0x2000000U)
+#define AIPS_PACRM_WP1_SHIFT (25U)
+/*! WP1 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
+#define AIPS_PACRM_SP1_MASK (0x4000000U)
+#define AIPS_PACRM_SP1_SHIFT (26U)
+/*! SP1 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
+#define AIPS_PACRM_TP0_MASK (0x10000000U)
+#define AIPS_PACRM_TP0_SHIFT (28U)
+/*! TP0 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
+#define AIPS_PACRM_WP0_MASK (0x20000000U)
+#define AIPS_PACRM_WP0_SHIFT (29U)
+/*! WP0 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
+#define AIPS_PACRM_SP0_MASK (0x40000000U)
+#define AIPS_PACRM_SP0_SHIFT (30U)
+/*! SP0 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
+/*! @} */
+
+/*! @name PACRN - Peripheral Access Control Register */
+/*! @{ */
+#define AIPS_PACRN_TP7_MASK (0x1U)
+#define AIPS_PACRN_TP7_SHIFT (0U)
+/*! TP7 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
+#define AIPS_PACRN_WP7_MASK (0x2U)
+#define AIPS_PACRN_WP7_SHIFT (1U)
+/*! WP7 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
+#define AIPS_PACRN_SP7_MASK (0x4U)
+#define AIPS_PACRN_SP7_SHIFT (2U)
+/*! SP7 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
+#define AIPS_PACRN_TP6_MASK (0x10U)
+#define AIPS_PACRN_TP6_SHIFT (4U)
+/*! TP6 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
+#define AIPS_PACRN_WP6_MASK (0x20U)
+#define AIPS_PACRN_WP6_SHIFT (5U)
+/*! WP6 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
+#define AIPS_PACRN_SP6_MASK (0x40U)
+#define AIPS_PACRN_SP6_SHIFT (6U)
+/*! SP6 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
+#define AIPS_PACRN_TP5_MASK (0x100U)
+#define AIPS_PACRN_TP5_SHIFT (8U)
+/*! TP5 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
+#define AIPS_PACRN_WP5_MASK (0x200U)
+#define AIPS_PACRN_WP5_SHIFT (9U)
+/*! WP5 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
+#define AIPS_PACRN_SP5_MASK (0x400U)
+#define AIPS_PACRN_SP5_SHIFT (10U)
+/*! SP5 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
+#define AIPS_PACRN_TP4_MASK (0x1000U)
+#define AIPS_PACRN_TP4_SHIFT (12U)
+/*! TP4 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
+#define AIPS_PACRN_WP4_MASK (0x2000U)
+#define AIPS_PACRN_WP4_SHIFT (13U)
+/*! WP4 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
+#define AIPS_PACRN_SP4_MASK (0x4000U)
+#define AIPS_PACRN_SP4_SHIFT (14U)
+/*! SP4 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
+#define AIPS_PACRN_TP3_MASK (0x10000U)
+#define AIPS_PACRN_TP3_SHIFT (16U)
+/*! TP3 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
+#define AIPS_PACRN_WP3_MASK (0x20000U)
+#define AIPS_PACRN_WP3_SHIFT (17U)
+/*! WP3 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
+#define AIPS_PACRN_SP3_MASK (0x40000U)
+#define AIPS_PACRN_SP3_SHIFT (18U)
+/*! SP3 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
+#define AIPS_PACRN_TP2_MASK (0x100000U)
+#define AIPS_PACRN_TP2_SHIFT (20U)
+/*! TP2 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
+#define AIPS_PACRN_WP2_MASK (0x200000U)
+#define AIPS_PACRN_WP2_SHIFT (21U)
+/*! WP2 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
+#define AIPS_PACRN_SP2_MASK (0x400000U)
+#define AIPS_PACRN_SP2_SHIFT (22U)
+/*! SP2 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
+#define AIPS_PACRN_TP1_MASK (0x1000000U)
+#define AIPS_PACRN_TP1_SHIFT (24U)
+/*! TP1 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
+#define AIPS_PACRN_WP1_MASK (0x2000000U)
+#define AIPS_PACRN_WP1_SHIFT (25U)
+/*! WP1 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
+#define AIPS_PACRN_SP1_MASK (0x4000000U)
+#define AIPS_PACRN_SP1_SHIFT (26U)
+/*! SP1 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
+#define AIPS_PACRN_TP0_MASK (0x10000000U)
+#define AIPS_PACRN_TP0_SHIFT (28U)
+/*! TP0 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
+#define AIPS_PACRN_WP0_MASK (0x20000000U)
+#define AIPS_PACRN_WP0_SHIFT (29U)
+/*! WP0 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
+#define AIPS_PACRN_SP0_MASK (0x40000000U)
+#define AIPS_PACRN_SP0_SHIFT (30U)
+/*! SP0 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
+/*! @} */
+
+/*! @name PACRO - Peripheral Access Control Register */
+/*! @{ */
+#define AIPS_PACRO_TP7_MASK (0x1U)
+#define AIPS_PACRO_TP7_SHIFT (0U)
+/*! TP7 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
+#define AIPS_PACRO_WP7_MASK (0x2U)
+#define AIPS_PACRO_WP7_SHIFT (1U)
+/*! WP7 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
+#define AIPS_PACRO_SP7_MASK (0x4U)
+#define AIPS_PACRO_SP7_SHIFT (2U)
+/*! SP7 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
+#define AIPS_PACRO_TP6_MASK (0x10U)
+#define AIPS_PACRO_TP6_SHIFT (4U)
+/*! TP6 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
+#define AIPS_PACRO_WP6_MASK (0x20U)
+#define AIPS_PACRO_WP6_SHIFT (5U)
+/*! WP6 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
+#define AIPS_PACRO_SP6_MASK (0x40U)
+#define AIPS_PACRO_SP6_SHIFT (6U)
+/*! SP6 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
+#define AIPS_PACRO_TP5_MASK (0x100U)
+#define AIPS_PACRO_TP5_SHIFT (8U)
+/*! TP5 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
+#define AIPS_PACRO_WP5_MASK (0x200U)
+#define AIPS_PACRO_WP5_SHIFT (9U)
+/*! WP5 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
+#define AIPS_PACRO_SP5_MASK (0x400U)
+#define AIPS_PACRO_SP5_SHIFT (10U)
+/*! SP5 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
+#define AIPS_PACRO_TP4_MASK (0x1000U)
+#define AIPS_PACRO_TP4_SHIFT (12U)
+/*! TP4 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
+#define AIPS_PACRO_WP4_MASK (0x2000U)
+#define AIPS_PACRO_WP4_SHIFT (13U)
+/*! WP4 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
+#define AIPS_PACRO_SP4_MASK (0x4000U)
+#define AIPS_PACRO_SP4_SHIFT (14U)
+/*! SP4 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
+#define AIPS_PACRO_TP3_MASK (0x10000U)
+#define AIPS_PACRO_TP3_SHIFT (16U)
+/*! TP3 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
+#define AIPS_PACRO_WP3_MASK (0x20000U)
+#define AIPS_PACRO_WP3_SHIFT (17U)
+/*! WP3 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
+#define AIPS_PACRO_SP3_MASK (0x40000U)
+#define AIPS_PACRO_SP3_SHIFT (18U)
+/*! SP3 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
+#define AIPS_PACRO_TP2_MASK (0x100000U)
+#define AIPS_PACRO_TP2_SHIFT (20U)
+/*! TP2 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
+#define AIPS_PACRO_WP2_MASK (0x200000U)
+#define AIPS_PACRO_WP2_SHIFT (21U)
+/*! WP2 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
+#define AIPS_PACRO_SP2_MASK (0x400000U)
+#define AIPS_PACRO_SP2_SHIFT (22U)
+/*! SP2 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
+#define AIPS_PACRO_TP1_MASK (0x1000000U)
+#define AIPS_PACRO_TP1_SHIFT (24U)
+/*! TP1 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
+#define AIPS_PACRO_WP1_MASK (0x2000000U)
+#define AIPS_PACRO_WP1_SHIFT (25U)
+/*! WP1 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
+#define AIPS_PACRO_SP1_MASK (0x4000000U)
+#define AIPS_PACRO_SP1_SHIFT (26U)
+/*! SP1 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
+#define AIPS_PACRO_TP0_MASK (0x10000000U)
+#define AIPS_PACRO_TP0_SHIFT (28U)
+/*! TP0 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
+#define AIPS_PACRO_WP0_MASK (0x20000000U)
+#define AIPS_PACRO_WP0_SHIFT (29U)
+/*! WP0 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
+#define AIPS_PACRO_SP0_MASK (0x40000000U)
+#define AIPS_PACRO_SP0_SHIFT (30U)
+/*! SP0 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
+/*! @} */
+
+/*! @name PACRP - Peripheral Access Control Register */
+/*! @{ */
+#define AIPS_PACRP_TP7_MASK (0x1U)
+#define AIPS_PACRP_TP7_SHIFT (0U)
+/*! TP7 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
+#define AIPS_PACRP_WP7_MASK (0x2U)
+#define AIPS_PACRP_WP7_SHIFT (1U)
+/*! WP7 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
+#define AIPS_PACRP_SP7_MASK (0x4U)
+#define AIPS_PACRP_SP7_SHIFT (2U)
+/*! SP7 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
+#define AIPS_PACRP_TP6_MASK (0x10U)
+#define AIPS_PACRP_TP6_SHIFT (4U)
+/*! TP6 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
+#define AIPS_PACRP_WP6_MASK (0x20U)
+#define AIPS_PACRP_WP6_SHIFT (5U)
+/*! WP6 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
+#define AIPS_PACRP_SP6_MASK (0x40U)
+#define AIPS_PACRP_SP6_SHIFT (6U)
+/*! SP6 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
+#define AIPS_PACRP_TP5_MASK (0x100U)
+#define AIPS_PACRP_TP5_SHIFT (8U)
+/*! TP5 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
+#define AIPS_PACRP_WP5_MASK (0x200U)
+#define AIPS_PACRP_WP5_SHIFT (9U)
+/*! WP5 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
+#define AIPS_PACRP_SP5_MASK (0x400U)
+#define AIPS_PACRP_SP5_SHIFT (10U)
+/*! SP5 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
+#define AIPS_PACRP_TP4_MASK (0x1000U)
+#define AIPS_PACRP_TP4_SHIFT (12U)
+/*! TP4 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
+#define AIPS_PACRP_WP4_MASK (0x2000U)
+#define AIPS_PACRP_WP4_SHIFT (13U)
+/*! WP4 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
+#define AIPS_PACRP_SP4_MASK (0x4000U)
+#define AIPS_PACRP_SP4_SHIFT (14U)
+/*! SP4 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
+#define AIPS_PACRP_TP3_MASK (0x10000U)
+#define AIPS_PACRP_TP3_SHIFT (16U)
+/*! TP3 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
+#define AIPS_PACRP_WP3_MASK (0x20000U)
+#define AIPS_PACRP_WP3_SHIFT (17U)
+/*! WP3 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
+#define AIPS_PACRP_SP3_MASK (0x40000U)
+#define AIPS_PACRP_SP3_SHIFT (18U)
+/*! SP3 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
+#define AIPS_PACRP_TP2_MASK (0x100000U)
+#define AIPS_PACRP_TP2_SHIFT (20U)
+/*! TP2 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
+#define AIPS_PACRP_WP2_MASK (0x200000U)
+#define AIPS_PACRP_WP2_SHIFT (21U)
+/*! WP2 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
+#define AIPS_PACRP_SP2_MASK (0x400000U)
+#define AIPS_PACRP_SP2_SHIFT (22U)
+/*! SP2 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
+#define AIPS_PACRP_TP1_MASK (0x1000000U)
+#define AIPS_PACRP_TP1_SHIFT (24U)
+/*! TP1 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
+#define AIPS_PACRP_WP1_MASK (0x2000000U)
+#define AIPS_PACRP_WP1_SHIFT (25U)
+/*! WP1 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
+#define AIPS_PACRP_SP1_MASK (0x4000000U)
+#define AIPS_PACRP_SP1_SHIFT (26U)
+/*! SP1 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
+#define AIPS_PACRP_TP0_MASK (0x10000000U)
+#define AIPS_PACRP_TP0_SHIFT (28U)
+/*! TP0 - Trusted Protect
+ * 0b0..Accesses from an untrusted master are allowed.
+ * 0b1..Accesses from an untrusted master are not allowed.
+ */
+#define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
+#define AIPS_PACRP_WP0_MASK (0x20000000U)
+#define AIPS_PACRP_WP0_SHIFT (29U)
+/*! WP0 - Write Protect
+ * 0b0..This peripheral allows write accesses.
+ * 0b1..This peripheral is write protected.
+ */
+#define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
+#define AIPS_PACRP_SP0_MASK (0x40000000U)
+#define AIPS_PACRP_SP0_SHIFT (30U)
+/*! SP0 - Supervisor Protect
+ * 0b0..This peripheral does not require supervisor privilege level for accesses.
+ * 0b1..This peripheral requires supervisor privilege level for accesses.
+ */
+#define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Masks */
+
+
+/* AIPS - Peripheral instance base addresses */
+/** Peripheral AIPS0 base address */
+#define AIPS0_BASE (0x40000000u)
+/** Peripheral AIPS0 base pointer */
+#define AIPS0 ((AIPS_Type *)AIPS0_BASE)
+/** Peripheral AIPS1 base address */
+#define AIPS1_BASE (0x40080000u)
+/** Peripheral AIPS1 base pointer */
+#define AIPS1 ((AIPS_Type *)AIPS1_BASE)
+/** Array initializer of AIPS peripheral base addresses */
+#define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE }
+/** Array initializer of AIPS peripheral base pointers */
+#define AIPS_BASE_PTRS { AIPS0, AIPS1 }
+
+/*!
+ * @}
+ */ /* end of group AIPS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- AXBS Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
+ * @{
+ */
+
+/** AXBS - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x100 */
+ __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
+ uint8_t RESERVED_1[236];
+ } SLAVE[5];
+ uint8_t RESERVED_0[768];
+ __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
+ uint8_t RESERVED_1[252];
+ __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
+ uint8_t RESERVED_2[252];
+ __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
+ uint8_t RESERVED_3[508];
+ __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
+ uint8_t RESERVED_4[252];
+ __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
+ uint8_t RESERVED_5[252];
+ __IO uint32_t MGPCR6; /**< Master General Purpose Control Register, offset: 0xE00 */
+} AXBS_Type;
+
+/* ----------------------------------------------------------------------------
+ -- AXBS Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Masks AXBS Register Masks
+ * @{
+ */
+
+/*! @name PRS - Priority Registers Slave */
+/*! @{ */
+#define AXBS_PRS_M0_MASK (0x7U)
+#define AXBS_PRS_M0_SHIFT (0U)
+/*! M0 - Master 0 Priority. Sets the arbitration priority for this port on the associated slave port.
+ * 0b000..This master has level 1, or highest, priority when accessing the slave port.
+ * 0b001..This master has level 2 priority when accessing the slave port.
+ * 0b010..This master has level 3 priority when accessing the slave port.
+ * 0b011..This master has level 4 priority when accessing the slave port.
+ * 0b100..This master has level 5 priority when accessing the slave port.
+ * 0b101..This master has level 6 priority when accessing the slave port.
+ * 0b110..This master has level 7 priority when accessing the slave port.
+ * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
+ */
+#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
+#define AXBS_PRS_M1_MASK (0x70U)
+#define AXBS_PRS_M1_SHIFT (4U)
+/*! M1 - Master 1 Priority. Sets the arbitration priority for this port on the associated slave port.
+ * 0b000..This master has level 1, or highest, priority when accessing the slave port.
+ * 0b001..This master has level 2 priority when accessing the slave port.
+ * 0b010..This master has level 3 priority when accessing the slave port.
+ * 0b011..This master has level 4 priority when accessing the slave port.
+ * 0b100..This master has level 5 priority when accessing the slave port.
+ * 0b101..This master has level 6 priority when accessing the slave port.
+ * 0b110..This master has level 7 priority when accessing the slave port.
+ * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
+ */
+#define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
+#define AXBS_PRS_M2_MASK (0x700U)
+#define AXBS_PRS_M2_SHIFT (8U)
+/*! M2 - Master 2 Priority. Sets the arbitration priority for this port on the associated slave port.
+ * 0b000..This master has level 1, or highest, priority when accessing the slave port.
+ * 0b001..This master has level 2 priority when accessing the slave port.
+ * 0b010..This master has level 3 priority when accessing the slave port.
+ * 0b011..This master has level 4 priority when accessing the slave port.
+ * 0b100..This master has level 5 priority when accessing the slave port.
+ * 0b101..This master has level 6 priority when accessing the slave port.
+ * 0b110..This master has level 7 priority when accessing the slave port.
+ * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
+ */
+#define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
+#define AXBS_PRS_M4_MASK (0x70000U)
+#define AXBS_PRS_M4_SHIFT (16U)
+/*! M4 - Master 4 Priority. Sets the arbitration priority for this port on the associated slave port.
+ * 0b000..This master has level 1, or highest, priority when accessing the slave port.
+ * 0b001..This master has level 2 priority when accessing the slave port.
+ * 0b010..This master has level 3 priority when accessing the slave port.
+ * 0b011..This master has level 4 priority when accessing the slave port.
+ * 0b100..This master has level 5 priority when accessing the slave port.
+ * 0b101..This master has level 6 priority when accessing the slave port.
+ * 0b110..This master has level 7 priority when accessing the slave port.
+ * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
+ */
+#define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
+#define AXBS_PRS_M5_MASK (0x700000U)
+#define AXBS_PRS_M5_SHIFT (20U)
+/*! M5 - Master 5 Priority. Sets the arbitration priority for this port on the associated slave port.
+ * 0b000..This master has level 1, or highest, priority when accessing the slave port.
+ * 0b001..This master has level 2 priority when accessing the slave port.
+ * 0b010..This master has level 3 priority when accessing the slave port.
+ * 0b011..This master has level 4 priority when accessing the slave port.
+ * 0b100..This master has level 5 priority when accessing the slave port.
+ * 0b101..This master has level 6 priority when accessing the slave port.
+ * 0b110..This master has level 7 priority when accessing the slave port.
+ * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
+ */
+#define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
+#define AXBS_PRS_M6_MASK (0x7000000U)
+#define AXBS_PRS_M6_SHIFT (24U)
+/*! M6 - Master 6 Priority. Sets the arbitration priority for this port on the associated slave port.
+ * 0b000..This master has level 1, or highest, priority when accessing the slave port.
+ * 0b001..This master has level 2 priority when accessing the slave port.
+ * 0b010..This master has level 3 priority when accessing the slave port.
+ * 0b011..This master has level 4 priority when accessing the slave port.
+ * 0b100..This master has level 5 priority when accessing the slave port.
+ * 0b101..This master has level 6 priority when accessing the slave port.
+ * 0b110..This master has level 7 priority when accessing the slave port.
+ * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
+ */
+#define AXBS_PRS_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M6_SHIFT)) & AXBS_PRS_M6_MASK)
+/*! @} */
+
+/* The count of AXBS_PRS */
+#define AXBS_PRS_COUNT (5U)
+
+/*! @name CRS - Control Register */
+/*! @{ */
+#define AXBS_CRS_PARK_MASK (0x7U)
+#define AXBS_CRS_PARK_SHIFT (0U)
+/*! PARK - Park
+ * 0b000..Park on master port M0
+ * 0b001..Park on master port M1
+ * 0b010..Park on master port M2
+ * 0b011..Park on master port M3
+ * 0b100..Park on master port M4
+ * 0b101..Park on master port M5
+ * 0b110..Park on master port M6
+ * 0b111..Park on master port M7
+ */
+#define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
+#define AXBS_CRS_PCTL_MASK (0x30U)
+#define AXBS_CRS_PCTL_SHIFT (4U)
+/*! PCTL - Parking Control
+ * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field
+ * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port
+ * 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state
+ * 0b11..Reserved
+ */
+#define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
+#define AXBS_CRS_ARB_MASK (0x300U)
+#define AXBS_CRS_ARB_SHIFT (8U)
+/*! ARB - Arbitration Mode
+ * 0b00..Fixed priority
+ * 0b01..Round-robin, or rotating, priority
+ * 0b10..Reserved
+ * 0b11..Reserved
+ */
+#define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
+#define AXBS_CRS_HLP_MASK (0x40000000U)
+#define AXBS_CRS_HLP_SHIFT (30U)
+/*! HLP - Halt Low Priority
+ * 0b0..The low power mode request has the highest priority for arbitration on this slave port
+ * 0b1..The low power mode request has the lowest initial priority for arbitration on this slave port
+ */
+#define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
+#define AXBS_CRS_RO_MASK (0x80000000U)
+#define AXBS_CRS_RO_SHIFT (31U)
+/*! RO - Read Only
+ * 0b0..The slave port's registers are writeable
+ * 0b1..The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response.
+ */
+#define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
+/*! @} */
+
+/* The count of AXBS_CRS */
+#define AXBS_CRS_COUNT (5U)
+
+/*! @name MGPCR0 - Master General Purpose Control Register */
+/*! @{ */
+#define AXBS_MGPCR0_AULB_MASK (0x7U)
+#define AXBS_MGPCR0_AULB_SHIFT (0U)
+/*! AULB - Arbitrates On Undefined Length Bursts
+ * 0b000..No arbitration is allowed during an undefined length burst
+ * 0b001..Arbitration is allowed at any time during an undefined length burst
+ * 0b010..Arbitration is allowed after four beats of an undefined length burst
+ * 0b011..Arbitration is allowed after eight beats of an undefined length burst
+ * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..Reserved
+ */
+#define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
+/*! @} */
+
+/*! @name MGPCR1 - Master General Purpose Control Register */
+/*! @{ */
+#define AXBS_MGPCR1_AULB_MASK (0x7U)
+#define AXBS_MGPCR1_AULB_SHIFT (0U)
+/*! AULB - Arbitrates On Undefined Length Bursts
+ * 0b000..No arbitration is allowed during an undefined length burst
+ * 0b001..Arbitration is allowed at any time during an undefined length burst
+ * 0b010..Arbitration is allowed after four beats of an undefined length burst
+ * 0b011..Arbitration is allowed after eight beats of an undefined length burst
+ * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..Reserved
+ */
+#define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
+/*! @} */
+
+/*! @name MGPCR2 - Master General Purpose Control Register */
+/*! @{ */
+#define AXBS_MGPCR2_AULB_MASK (0x7U)
+#define AXBS_MGPCR2_AULB_SHIFT (0U)
+/*! AULB - Arbitrates On Undefined Length Bursts
+ * 0b000..No arbitration is allowed during an undefined length burst
+ * 0b001..Arbitration is allowed at any time during an undefined length burst
+ * 0b010..Arbitration is allowed after four beats of an undefined length burst
+ * 0b011..Arbitration is allowed after eight beats of an undefined length burst
+ * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..Reserved
+ */
+#define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
+/*! @} */
+
+/*! @name MGPCR4 - Master General Purpose Control Register */
+/*! @{ */
+#define AXBS_MGPCR4_AULB_MASK (0x7U)
+#define AXBS_MGPCR4_AULB_SHIFT (0U)
+/*! AULB - Arbitrates On Undefined Length Bursts
+ * 0b000..No arbitration is allowed during an undefined length burst
+ * 0b001..Arbitration is allowed at any time during an undefined length burst
+ * 0b010..Arbitration is allowed after four beats of an undefined length burst
+ * 0b011..Arbitration is allowed after eight beats of an undefined length burst
+ * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..Reserved
+ */
+#define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
+/*! @} */
+
+/*! @name MGPCR5 - Master General Purpose Control Register */
+/*! @{ */
+#define AXBS_MGPCR5_AULB_MASK (0x7U)
+#define AXBS_MGPCR5_AULB_SHIFT (0U)
+/*! AULB - Arbitrates On Undefined Length Bursts
+ * 0b000..No arbitration is allowed during an undefined length burst
+ * 0b001..Arbitration is allowed at any time during an undefined length burst
+ * 0b010..Arbitration is allowed after four beats of an undefined length burst
+ * 0b011..Arbitration is allowed after eight beats of an undefined length burst
+ * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..Reserved
+ */
+#define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
+/*! @} */
+
+/*! @name MGPCR6 - Master General Purpose Control Register */
+/*! @{ */
+#define AXBS_MGPCR6_AULB_MASK (0x7U)
+#define AXBS_MGPCR6_AULB_SHIFT (0U)
+/*! AULB - Arbitrates On Undefined Length Bursts
+ * 0b000..No arbitration is allowed during an undefined length burst
+ * 0b001..Arbitration is allowed at any time during an undefined length burst
+ * 0b010..Arbitration is allowed after four beats of an undefined length burst
+ * 0b011..Arbitration is allowed after eight beats of an undefined length burst
+ * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..Reserved
+ */
+#define AXBS_MGPCR6_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR6_AULB_SHIFT)) & AXBS_MGPCR6_AULB_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Masks */
+
+
+/* AXBS - Peripheral instance base addresses */
+/** Peripheral AXBS base address */
+#define AXBS_BASE (0x40004000u)
+/** Peripheral AXBS base pointer */
+#define AXBS ((AXBS_Type *)AXBS_BASE)
+/** Array initializer of AXBS peripheral base addresses */
+#define AXBS_BASE_ADDRS { AXBS_BASE }
+/** Array initializer of AXBS peripheral base pointers */
+#define AXBS_BASE_PTRS { AXBS }
+
+/*!
+ * @}
+ */ /* end of group AXBS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CAN Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
+ * @{
+ */
+
+/** CAN - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
+ __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
+ __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
+ __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
+ __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
+ __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
+ __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
+ __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
+ __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
+ uint8_t RESERVED_3[8];
+ __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
+ __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
+ __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
+ uint8_t RESERVED_4[48];
+ struct { /* offset: 0x80, array step: 0x10 */
+ __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
+ __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
+ __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
+ __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
+ } MB[16];
+ uint8_t RESERVED_5[1792];
+ __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
+} CAN_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CAN Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Masks CAN Register Masks
+ * @{
+ */
+
+/*! @name MCR - Module Configuration Register */
+/*! @{ */
+#define CAN_MCR_MAXMB_MASK (0x7FU)
+#define CAN_MCR_MAXMB_SHIFT (0U)
+#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
+#define CAN_MCR_IDAM_MASK (0x300U)
+#define CAN_MCR_IDAM_SHIFT (8U)
+/*! IDAM - ID Acceptance Mode
+ * 0b00..Format A: One full ID (standard and extended) per ID Filter Table element.
+ * 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element.
+ * 0b10..Format C: Four partial 8-bit Standard IDs per ID Filter Table element.
+ * 0b11..Format D: All frames rejected.
+ */
+#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
+#define CAN_MCR_AEN_MASK (0x1000U)
+#define CAN_MCR_AEN_SHIFT (12U)
+/*! AEN - Abort Enable
+ * 0b0..Abort disabled.
+ * 0b1..Abort enabled.
+ */
+#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
+#define CAN_MCR_LPRIOEN_MASK (0x2000U)
+#define CAN_MCR_LPRIOEN_SHIFT (13U)
+/*! LPRIOEN - Local Priority Enable
+ * 0b0..Local Priority disabled.
+ * 0b1..Local Priority enabled.
+ */
+#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
+#define CAN_MCR_IRMQ_MASK (0x10000U)
+#define CAN_MCR_IRMQ_SHIFT (16U)
+/*! IRMQ - Individual Rx Masking And Queue Enable
+ * 0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY.
+ * 0b1..Individual Rx masking and queue feature are enabled.
+ */
+#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
+#define CAN_MCR_SRXDIS_MASK (0x20000U)
+#define CAN_MCR_SRXDIS_SHIFT (17U)
+/*! SRXDIS - Self Reception Disable
+ * 0b0..Self reception enabled.
+ * 0b1..Self reception disabled.
+ */
+#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
+#define CAN_MCR_WAKSRC_MASK (0x80000U)
+#define CAN_MCR_WAKSRC_SHIFT (19U)
+/*! WAKSRC - Wake Up Source
+ * 0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus.
+ * 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.
+ */
+#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
+#define CAN_MCR_LPMACK_MASK (0x100000U)
+#define CAN_MCR_LPMACK_SHIFT (20U)
+/*! LPMACK - Low-Power Mode Acknowledge
+ * 0b0..FlexCAN is not in a low-power mode.
+ * 0b1..FlexCAN is in a low-power mode.
+ */
+#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
+#define CAN_MCR_WRNEN_MASK (0x200000U)
+#define CAN_MCR_WRNEN_SHIFT (21U)
+/*! WRNEN - Warning Interrupt Enable
+ * 0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters.
+ * 0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.
+ */
+#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
+#define CAN_MCR_SLFWAK_MASK (0x400000U)
+#define CAN_MCR_SLFWAK_SHIFT (22U)
+/*! SLFWAK - Self Wake Up
+ * 0b0..FlexCAN Self Wake Up feature is disabled.
+ * 0b1..FlexCAN Self Wake Up feature is enabled.
+ */
+#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
+#define CAN_MCR_SUPV_MASK (0x800000U)
+#define CAN_MCR_SUPV_SHIFT (23U)
+/*! SUPV - Supervisor Mode
+ * 0b0..FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses .
+ * 0b1..FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location .
+ */
+#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
+#define CAN_MCR_FRZACK_MASK (0x1000000U)
+#define CAN_MCR_FRZACK_SHIFT (24U)
+/*! FRZACK - Freeze Mode Acknowledge
+ * 0b0..FlexCAN not in Freeze mode, prescaler running.
+ * 0b1..FlexCAN in Freeze mode, prescaler stopped.
+ */
+#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
+#define CAN_MCR_SOFTRST_MASK (0x2000000U)
+#define CAN_MCR_SOFTRST_SHIFT (25U)
+/*! SOFTRST - Soft Reset
+ * 0b0..No reset request.
+ * 0b1..Resets the registers affected by soft reset.
+ */
+#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
+#define CAN_MCR_WAKMSK_MASK (0x4000000U)
+#define CAN_MCR_WAKMSK_SHIFT (26U)
+/*! WAKMSK - Wake Up Interrupt Mask
+ * 0b0..Wake Up Interrupt is disabled.
+ * 0b1..Wake Up Interrupt is enabled.
+ */
+#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
+#define CAN_MCR_NOTRDY_MASK (0x8000000U)
+#define CAN_MCR_NOTRDY_SHIFT (27U)
+/*! NOTRDY - FlexCAN Not Ready
+ * 0b0..FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode.
+ * 0b1..FlexCAN module is either in Disable mode , Stop mode or Freeze mode.
+ */
+#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
+#define CAN_MCR_HALT_MASK (0x10000000U)
+#define CAN_MCR_HALT_SHIFT (28U)
+/*! HALT - Halt FlexCAN
+ * 0b0..No Freeze mode request.
+ * 0b1..Enters Freeze mode if the FRZ bit is asserted.
+ */
+#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
+#define CAN_MCR_RFEN_MASK (0x20000000U)
+#define CAN_MCR_RFEN_SHIFT (29U)
+/*! RFEN - Rx FIFO Enable
+ * 0b0..Rx FIFO not enabled.
+ * 0b1..Rx FIFO enabled.
+ */
+#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
+#define CAN_MCR_FRZ_MASK (0x40000000U)
+#define CAN_MCR_FRZ_SHIFT (30U)
+/*! FRZ - Freeze Enable
+ * 0b0..Not enabled to enter Freeze mode.
+ * 0b1..Enabled to enter Freeze mode.
+ */
+#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
+#define CAN_MCR_MDIS_MASK (0x80000000U)
+#define CAN_MCR_MDIS_SHIFT (31U)
+/*! MDIS - Module Disable
+ * 0b0..Enable the FlexCAN module.
+ * 0b1..Disable the FlexCAN module.
+ */
+#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
+/*! @} */
+
+/*! @name CTRL1 - Control 1 register */
+/*! @{ */
+#define CAN_CTRL1_PROPSEG_MASK (0x7U)
+#define CAN_CTRL1_PROPSEG_SHIFT (0U)
+#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
+#define CAN_CTRL1_LOM_MASK (0x8U)
+#define CAN_CTRL1_LOM_SHIFT (3U)
+/*! LOM - Listen-Only Mode
+ * 0b0..Listen-Only mode is deactivated.
+ * 0b1..FlexCAN module operates in Listen-Only mode.
+ */
+#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
+#define CAN_CTRL1_LBUF_MASK (0x10U)
+#define CAN_CTRL1_LBUF_SHIFT (4U)
+/*! LBUF - Lowest Buffer Transmitted First
+ * 0b0..Buffer with highest priority is transmitted first.
+ * 0b1..Lowest number buffer is transmitted first.
+ */
+#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
+#define CAN_CTRL1_TSYN_MASK (0x20U)
+#define CAN_CTRL1_TSYN_SHIFT (5U)
+/*! TSYN - Timer Sync
+ * 0b0..Timer Sync feature disabled
+ * 0b1..Timer Sync feature enabled
+ */
+#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
+#define CAN_CTRL1_BOFFREC_MASK (0x40U)
+#define CAN_CTRL1_BOFFREC_SHIFT (6U)
+/*! BOFFREC - Bus Off Recovery
+ * 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B.
+ * 0b1..Automatic recovering from Bus Off state disabled.
+ */
+#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
+#define CAN_CTRL1_SMP_MASK (0x80U)
+#define CAN_CTRL1_SMP_SHIFT (7U)
+/*! SMP - CAN Bit Sampling
+ * 0b0..Just one sample is used to determine the bit value.
+ * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used.
+ */
+#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
+#define CAN_CTRL1_RWRNMSK_MASK (0x400U)
+#define CAN_CTRL1_RWRNMSK_SHIFT (10U)
+/*! RWRNMSK - Rx Warning Interrupt Mask
+ * 0b0..Rx Warning Interrupt disabled.
+ * 0b1..Rx Warning Interrupt enabled.
+ */
+#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
+#define CAN_CTRL1_TWRNMSK_MASK (0x800U)
+#define CAN_CTRL1_TWRNMSK_SHIFT (11U)
+/*! TWRNMSK - Tx Warning Interrupt Mask
+ * 0b0..Tx Warning Interrupt disabled.
+ * 0b1..Tx Warning Interrupt enabled.
+ */
+#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
+#define CAN_CTRL1_LPB_MASK (0x1000U)
+#define CAN_CTRL1_LPB_SHIFT (12U)
+/*! LPB - Loop Back Mode
+ * 0b0..Loop Back disabled.
+ * 0b1..Loop Back enabled.
+ */
+#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
+#define CAN_CTRL1_CLKSRC_MASK (0x2000U)
+#define CAN_CTRL1_CLKSRC_SHIFT (13U)
+/*! CLKSRC - CAN Engine Clock Source
+ * 0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock.
+ * 0b1..The CAN engine clock source is the peripheral clock.
+ */
+#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
+#define CAN_CTRL1_ERRMSK_MASK (0x4000U)
+#define CAN_CTRL1_ERRMSK_SHIFT (14U)
+/*! ERRMSK - Error Mask
+ * 0b0..Error interrupt disabled.
+ * 0b1..Error interrupt enabled.
+ */
+#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
+#define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
+#define CAN_CTRL1_BOFFMSK_SHIFT (15U)
+/*! BOFFMSK - Bus Off Mask
+ * 0b0..Bus Off interrupt disabled.
+ * 0b1..Bus Off interrupt enabled.
+ */
+#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
+#define CAN_CTRL1_PSEG2_MASK (0x70000U)
+#define CAN_CTRL1_PSEG2_SHIFT (16U)
+#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
+#define CAN_CTRL1_PSEG1_MASK (0x380000U)
+#define CAN_CTRL1_PSEG1_SHIFT (19U)
+#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
+#define CAN_CTRL1_RJW_MASK (0xC00000U)
+#define CAN_CTRL1_RJW_SHIFT (22U)
+#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
+#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
+#define CAN_CTRL1_PRESDIV_SHIFT (24U)
+#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
+/*! @} */
+
+/*! @name TIMER - Free Running Timer */
+/*! @{ */
+#define CAN_TIMER_TIMER_MASK (0xFFFFU)
+#define CAN_TIMER_TIMER_SHIFT (0U)
+#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
+/*! @} */
+
+/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */
+/*! @{ */
+#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
+#define CAN_RXMGMASK_MG_SHIFT (0U)
+/*! MG - Rx Mailboxes Global Mask Bits
+ * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care."
+ * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.
+ */
+#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
+/*! @} */
+
+/*! @name RX14MASK - Rx 14 Mask register */
+/*! @{ */
+#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
+#define CAN_RX14MASK_RX14M_SHIFT (0U)
+/*! RX14M - Rx Buffer 14 Mask Bits
+ * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care."
+ * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.
+ */
+#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
+/*! @} */
+
+/*! @name RX15MASK - Rx 15 Mask register */
+/*! @{ */
+#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
+#define CAN_RX15MASK_RX15M_SHIFT (0U)
+/*! RX15M - Rx Buffer 15 Mask Bits
+ * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care."
+ * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.
+ */
+#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
+/*! @} */
+
+/*! @name ECR - Error Counter */
+/*! @{ */
+#define CAN_ECR_TXERRCNT_MASK (0xFFU)
+#define CAN_ECR_TXERRCNT_SHIFT (0U)
+#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
+#define CAN_ECR_RXERRCNT_MASK (0xFF00U)
+#define CAN_ECR_RXERRCNT_SHIFT (8U)
+#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
+/*! @} */
+
+/*! @name ESR1 - Error and Status 1 register */
+/*! @{ */
+#define CAN_ESR1_WAKINT_MASK (0x1U)
+#define CAN_ESR1_WAKINT_SHIFT (0U)
+/*! WAKINT - Wake-Up Interrupt
+ * 0b0..No such occurrence.
+ * 0b1..Indicates a recessive to dominant transition was received on the CAN bus.
+ */
+#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
+#define CAN_ESR1_ERRINT_MASK (0x2U)
+#define CAN_ESR1_ERRINT_SHIFT (1U)
+/*! ERRINT - Error Interrupt
+ * 0b0..No such occurrence.
+ * 0b1..Indicates setting of any Error Bit in the Error and Status Register.
+ */
+#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
+#define CAN_ESR1_BOFFINT_MASK (0x4U)
+#define CAN_ESR1_BOFFINT_SHIFT (2U)
+/*! BOFFINT - Bus Off Interrupt
+ * 0b0..No such occurrence.
+ * 0b1..FlexCAN module entered Bus Off state.
+ */
+#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
+#define CAN_ESR1_RX_MASK (0x8U)
+#define CAN_ESR1_RX_SHIFT (3U)
+/*! RX - FlexCAN In Reception
+ * 0b0..FlexCAN is not receiving a message.
+ * 0b1..FlexCAN is receiving a message.
+ */
+#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
+#define CAN_ESR1_FLTCONF_MASK (0x30U)
+#define CAN_ESR1_FLTCONF_SHIFT (4U)
+/*! FLTCONF - Fault Confinement State
+ * 0b00..Error Active
+ * 0b01..Error Passive
+ * 0b1x..Bus Off
+ */
+#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
+#define CAN_ESR1_TX_MASK (0x40U)
+#define CAN_ESR1_TX_SHIFT (6U)
+/*! TX - FlexCAN In Transmission
+ * 0b0..FlexCAN is not transmitting a message.
+ * 0b1..FlexCAN is transmitting a message.
+ */
+#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
+#define CAN_ESR1_IDLE_MASK (0x80U)
+#define CAN_ESR1_IDLE_SHIFT (7U)
+/*! IDLE
+ * 0b0..No such occurrence.
+ * 0b1..CAN bus is now IDLE.
+ */
+#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
+#define CAN_ESR1_RXWRN_MASK (0x100U)
+#define CAN_ESR1_RXWRN_SHIFT (8U)
+/*! RXWRN - Rx Error Warning
+ * 0b0..No such occurrence.
+ * 0b1..RXERRCNT is greater than or equal to 96.
+ */
+#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
+#define CAN_ESR1_TXWRN_MASK (0x200U)
+#define CAN_ESR1_TXWRN_SHIFT (9U)
+/*! TXWRN - TX Error Warning
+ * 0b0..No such occurrence.
+ * 0b1..TXERRCNT is greater than or equal to 96.
+ */
+#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
+#define CAN_ESR1_STFERR_MASK (0x400U)
+#define CAN_ESR1_STFERR_SHIFT (10U)
+/*! STFERR - Stuffing Error
+ * 0b0..No such occurrence.
+ * 0b1..A Stuffing Error occurred since last read of this register.
+ */
+#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
+#define CAN_ESR1_FRMERR_MASK (0x800U)
+#define CAN_ESR1_FRMERR_SHIFT (11U)
+/*! FRMERR - Form Error
+ * 0b0..No such occurrence.
+ * 0b1..A Form Error occurred since last read of this register.
+ */
+#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
+#define CAN_ESR1_CRCERR_MASK (0x1000U)
+#define CAN_ESR1_CRCERR_SHIFT (12U)
+/*! CRCERR - Cyclic Redundancy Check Error
+ * 0b0..No such occurrence.
+ * 0b1..A CRC error occurred since last read of this register.
+ */
+#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
+#define CAN_ESR1_ACKERR_MASK (0x2000U)
+#define CAN_ESR1_ACKERR_SHIFT (13U)
+/*! ACKERR - Acknowledge Error
+ * 0b0..No such occurrence.
+ * 0b1..An ACK error occurred since last read of this register.
+ */
+#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
+#define CAN_ESR1_BIT0ERR_MASK (0x4000U)
+#define CAN_ESR1_BIT0ERR_SHIFT (14U)
+/*! BIT0ERR - Bit0 Error
+ * 0b0..No such occurrence.
+ * 0b1..At least one bit sent as dominant is received as recessive.
+ */
+#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
+#define CAN_ESR1_BIT1ERR_MASK (0x8000U)
+#define CAN_ESR1_BIT1ERR_SHIFT (15U)
+/*! BIT1ERR - Bit1 Error
+ * 0b0..No such occurrence.
+ * 0b1..At least one bit sent as recessive is received as dominant.
+ */
+#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
+#define CAN_ESR1_RWRNINT_MASK (0x10000U)
+#define CAN_ESR1_RWRNINT_SHIFT (16U)
+/*! RWRNINT - Rx Warning Interrupt Flag
+ * 0b0..No such occurrence.
+ * 0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96.
+ */
+#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
+#define CAN_ESR1_TWRNINT_MASK (0x20000U)
+#define CAN_ESR1_TWRNINT_SHIFT (17U)
+/*! TWRNINT - Tx Warning Interrupt Flag
+ * 0b0..No such occurrence.
+ * 0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96.
+ */
+#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
+#define CAN_ESR1_SYNCH_MASK (0x40000U)
+#define CAN_ESR1_SYNCH_SHIFT (18U)
+/*! SYNCH - CAN Synchronization Status
+ * 0b0..FlexCAN is not synchronized to the CAN bus.
+ * 0b1..FlexCAN is synchronized to the CAN bus.
+ */
+#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
+/*! @} */
+
+/*! @name IMASK1 - Interrupt Masks 1 register */
+/*! @{ */
+#define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)
+#define CAN_IMASK1_BUFLM_SHIFT (0U)
+/*! BUFLM - Buffer MB i Mask
+ * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled.
+ * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled.
+ */
+#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
+/*! @} */
+
+/*! @name IFLAG1 - Interrupt Flags 1 register */
+/*! @{ */
+#define CAN_IFLAG1_BUF0I_MASK (0x1U)
+#define CAN_IFLAG1_BUF0I_SHIFT (0U)
+/*! BUF0I - Buffer MB0 Interrupt Or "reserved"
+ * 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0.
+ * 0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
+ */
+#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
+#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)
+#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U)
+/*! BUF4TO1I - Buffer MB i Interrupt Or "reserved"
+ * 0b0000..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0.
+ * 0b0001..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
+ */
+#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
+#define CAN_IFLAG1_BUF5I_MASK (0x20U)
+#define CAN_IFLAG1_BUF5I_SHIFT (5U)
+/*! BUF5I - Buffer MB5 Interrupt Or "Frames available in Rx FIFO"
+ * 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
+ * 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1
+ */
+#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
+#define CAN_IFLAG1_BUF6I_MASK (0x40U)
+#define CAN_IFLAG1_BUF6I_SHIFT (6U)
+/*! BUF6I - Buffer MB6 Interrupt Or "Rx FIFO Warning"
+ * 0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
+ * 0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1
+ */
+#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
+#define CAN_IFLAG1_BUF7I_MASK (0x80U)
+#define CAN_IFLAG1_BUF7I_SHIFT (7U)
+/*! BUF7I - Buffer MB7 Interrupt Or "Rx FIFO Overflow"
+ * 0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
+ * 0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1
+ */
+#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
+#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
+#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
+/*! BUF31TO8I - Buffer MBi Interrupt
+ * 0b000000000000000000000000..The corresponding buffer has no occurrence of successfully completed transmission or reception.
+ * 0b000000000000000000000001..The corresponding buffer has successfully completed transmission or reception.
+ */
+#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
+/*! @} */
+
+/*! @name CTRL2 - Control 2 register */
+/*! @{ */
+#define CAN_CTRL2_EACEN_MASK (0x10000U)
+#define CAN_CTRL2_EACEN_SHIFT (16U)
+/*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes
+ * 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
+ * 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply.
+ */
+#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
+#define CAN_CTRL2_RRS_MASK (0x20000U)
+#define CAN_CTRL2_RRS_SHIFT (17U)
+/*! RRS - Remote Request Storing
+ * 0b0..Remote Response Frame is generated.
+ * 0b1..Remote Request Frame is stored.
+ */
+#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
+#define CAN_CTRL2_MRP_MASK (0x40000U)
+#define CAN_CTRL2_MRP_SHIFT (18U)
+/*! MRP - Mailboxes Reception Priority
+ * 0b0..Matching starts from Rx FIFO and continues on Mailboxes.
+ * 0b1..Matching starts from Mailboxes and continues on Rx FIFO.
+ */
+#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
+#define CAN_CTRL2_TASD_MASK (0xF80000U)
+#define CAN_CTRL2_TASD_SHIFT (19U)
+#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
+#define CAN_CTRL2_RFFN_MASK (0xF000000U)
+#define CAN_CTRL2_RFFN_SHIFT (24U)
+#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
+#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
+#define CAN_CTRL2_WRMFRZ_SHIFT (28U)
+/*! WRMFRZ - Write-Access To Memory In Freeze Mode
+ * 0b0..Maintain the write access restrictions.
+ * 0b1..Enable unrestricted write access to FlexCAN memory.
+ */
+#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
+/*! @} */
+
+/*! @name ESR2 - Error and Status 2 register */
+/*! @{ */
+#define CAN_ESR2_IMB_MASK (0x2000U)
+#define CAN_ESR2_IMB_SHIFT (13U)
+/*! IMB - Inactive Mailbox
+ * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
+ * 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one.
+ */
+#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
+#define CAN_ESR2_VPS_MASK (0x4000U)
+#define CAN_ESR2_VPS_SHIFT (14U)
+/*! VPS - Valid Priority Status
+ * 0b0..Contents of IMB and LPTM are invalid.
+ * 0b1..Contents of IMB and LPTM are valid.
+ */
+#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
+#define CAN_ESR2_LPTM_MASK (0x7F0000U)
+#define CAN_ESR2_LPTM_SHIFT (16U)
+#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
+/*! @} */
+
+/*! @name CRCR - CRC Register */
+/*! @{ */
+#define CAN_CRCR_TXCRC_MASK (0x7FFFU)
+#define CAN_CRCR_TXCRC_SHIFT (0U)
+#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
+#define CAN_CRCR_MBCRC_MASK (0x7F0000U)
+#define CAN_CRCR_MBCRC_SHIFT (16U)
+#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
+/*! @} */
+
+/*! @name RXFGMASK - Rx FIFO Global Mask register */
+/*! @{ */
+#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
+#define CAN_RXFGMASK_FGM_SHIFT (0U)
+/*! FGM - Rx FIFO Global Mask Bits
+ * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care."
+ * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.
+ */
+#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
+/*! @} */
+
+/*! @name RXFIR - Rx FIFO Information Register */
+/*! @{ */
+#define CAN_RXFIR_IDHIT_MASK (0x1FFU)
+#define CAN_RXFIR_IDHIT_SHIFT (0U)
+#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
+/*! @} */
+
+/*! @name CS - Message Buffer 0 CS Register..Message Buffer 15 CS Register */
+/*! @{ */
+#define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
+#define CAN_CS_TIME_STAMP_SHIFT (0U)
+#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
+#define CAN_CS_DLC_MASK (0xF0000U)
+#define CAN_CS_DLC_SHIFT (16U)
+#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
+#define CAN_CS_RTR_MASK (0x100000U)
+#define CAN_CS_RTR_SHIFT (20U)
+#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
+#define CAN_CS_IDE_MASK (0x200000U)
+#define CAN_CS_IDE_SHIFT (21U)
+#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
+#define CAN_CS_SRR_MASK (0x400000U)
+#define CAN_CS_SRR_SHIFT (22U)
+#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
+#define CAN_CS_CODE_MASK (0xF000000U)
+#define CAN_CS_CODE_SHIFT (24U)
+#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
+/*! @} */
+
+/* The count of CAN_CS */
+#define CAN_CS_COUNT (16U)
+
+/*! @name ID - Message Buffer 0 ID Register..Message Buffer 15 ID Register */
+/*! @{ */
+#define CAN_ID_EXT_MASK (0x3FFFFU)
+#define CAN_ID_EXT_SHIFT (0U)
+#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
+#define CAN_ID_STD_MASK (0x1FFC0000U)
+#define CAN_ID_STD_SHIFT (18U)
+#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
+#define CAN_ID_PRIO_MASK (0xE0000000U)
+#define CAN_ID_PRIO_SHIFT (29U)
+#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
+/*! @} */
+
+/* The count of CAN_ID */
+#define CAN_ID_COUNT (16U)
+
+/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register */
+/*! @{ */
+#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
+#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
+#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
+#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
+#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
+#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
+#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
+#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
+#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
+#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
+#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
+#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
+/*! @} */
+
+/* The count of CAN_WORD0 */
+#define CAN_WORD0_COUNT (16U)
+
+/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register */
+/*! @{ */
+#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
+#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
+#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
+#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
+#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
+#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
+#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
+#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
+#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
+#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
+#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
+#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
+/*! @} */
+
+/* The count of CAN_WORD1 */
+#define CAN_WORD1_COUNT (16U)
+
+/*! @name RXIMR - Rx Individual Mask Registers */
+/*! @{ */
+#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
+#define CAN_RXIMR_MI_SHIFT (0U)
+/*! MI - Individual Mask Bits
+ * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care."
+ * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.
+ */
+#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
+/*! @} */
+
+/* The count of CAN_RXIMR */
+#define CAN_RXIMR_COUNT (16U)
+
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Masks */
+
+
+/* CAN - Peripheral instance base addresses */
+/** Peripheral CAN0 base address */
+#define CAN0_BASE (0x40024000u)
+/** Peripheral CAN0 base pointer */
+#define CAN0 ((CAN_Type *)CAN0_BASE)
+/** Peripheral CAN1 base address */
+#define CAN1_BASE (0x400A4000u)
+/** Peripheral CAN1 base pointer */
+#define CAN1 ((CAN_Type *)CAN1_BASE)
+/** Array initializer of CAN peripheral base addresses */
+#define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE }
+/** Array initializer of CAN peripheral base pointers */
+#define CAN_BASE_PTRS { CAN0, CAN1 }
+/** Interrupt vectors for the CAN peripheral type */
+#define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn, CAN1_Rx_Warning_IRQn }
+#define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn, CAN1_Tx_Warning_IRQn }
+#define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn, CAN1_Wake_Up_IRQn }
+#define CAN_Error_IRQS { CAN0_Error_IRQn, CAN1_Error_IRQn }
+#define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn, CAN1_Bus_Off_IRQn }
+#define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn, CAN1_ORed_Message_buffer_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CAN_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CAU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
+ * @{
+ */
+
+/** CAU - Register Layout Typedef */
+typedef struct {
+ __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
+ uint8_t RESERVED_0[2048];
+ __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
+ __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
+ __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
+ uint8_t RESERVED_1[20];
+ __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
+ __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
+ __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
+ uint8_t RESERVED_2[20];
+ __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
+ __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
+ __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
+ uint8_t RESERVED_3[20];
+ __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
+ __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
+ __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
+ uint8_t RESERVED_4[84];
+ __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
+ __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
+ __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
+ uint8_t RESERVED_5[20];
+ __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
+ __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
+ __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
+ uint8_t RESERVED_6[276];
+ __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
+ __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
+ __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
+ uint8_t RESERVED_7[20];
+ __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
+ __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
+ __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
+} CAU_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CAU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Masks CAU Register Masks
+ * @{
+ */
+
+/*! @name DIRECT - Direct access register 0..Direct access register 15 */
+/*! @{ */
+#define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U)
+#define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
+#define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U)
+#define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
+#define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U)
+#define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
+#define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U)
+#define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
+#define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U)
+#define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
+#define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U)
+#define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
+#define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U)
+#define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
+#define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U)
+#define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
+#define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U)
+#define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
+#define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U)
+#define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
+#define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U)
+#define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
+#define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U)
+#define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
+#define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U)
+#define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
+#define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U)
+#define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
+#define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U)
+#define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
+#define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U)
+#define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
+/*! @} */
+
+/* The count of CAU_DIRECT */
+#define CAU_DIRECT_COUNT (16U)
+
+/*! @name LDR_CASR - Status register - Load Register command */
+/*! @{ */
+#define CAU_LDR_CASR_IC_MASK (0x1U)
+#define CAU_LDR_CASR_IC_SHIFT (0U)
+/*! IC
+ * 0b0..No illegal commands issued
+ * 0b1..Illegal command issued
+ */
+#define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
+#define CAU_LDR_CASR_DPE_MASK (0x2U)
+#define CAU_LDR_CASR_DPE_SHIFT (1U)
+/*! DPE
+ * 0b0..No error detected
+ * 0b1..DES key parity error detected
+ */
+#define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
+#define CAU_LDR_CASR_VER_MASK (0xF0000000U)
+#define CAU_LDR_CASR_VER_SHIFT (28U)
+/*! VER - CAU version
+ * 0b0001..Initial CAU version
+ * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
+ */
+#define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
+/*! @} */
+
+/*! @name LDR_CAA - Accumulator register - Load Register command */
+/*! @{ */
+#define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU)
+#define CAU_LDR_CAA_ACC_SHIFT (0U)
+#define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
+/*! @} */
+
+/*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command */
+/*! @{ */
+#define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA0_SHIFT (0U)
+#define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
+#define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA1_SHIFT (0U)
+#define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
+#define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA2_SHIFT (0U)
+#define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
+#define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA3_SHIFT (0U)
+#define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
+#define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA4_SHIFT (0U)
+#define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
+#define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA5_SHIFT (0U)
+#define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
+#define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA6_SHIFT (0U)
+#define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
+#define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA7_SHIFT (0U)
+#define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
+#define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA8_SHIFT (0U)
+#define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
+/*! @} */
+
+/* The count of CAU_LDR_CA */
+#define CAU_LDR_CA_COUNT (9U)
+
+/*! @name STR_CASR - Status register - Store Register command */
+/*! @{ */
+#define CAU_STR_CASR_IC_MASK (0x1U)
+#define CAU_STR_CASR_IC_SHIFT (0U)
+/*! IC
+ * 0b0..No illegal commands issued
+ * 0b1..Illegal command issued
+ */
+#define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
+#define CAU_STR_CASR_DPE_MASK (0x2U)
+#define CAU_STR_CASR_DPE_SHIFT (1U)
+/*! DPE
+ * 0b0..No error detected
+ * 0b1..DES key parity error detected
+ */
+#define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
+#define CAU_STR_CASR_VER_MASK (0xF0000000U)
+#define CAU_STR_CASR_VER_SHIFT (28U)
+/*! VER - CAU version
+ * 0b0001..Initial CAU version
+ * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
+ */
+#define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
+/*! @} */
+
+/*! @name STR_CAA - Accumulator register - Store Register command */
+/*! @{ */
+#define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU)
+#define CAU_STR_CAA_ACC_SHIFT (0U)
+#define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
+/*! @} */
+
+/*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command */
+/*! @{ */
+#define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU)
+#define CAU_STR_CA_CA0_SHIFT (0U)
+#define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
+#define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU)
+#define CAU_STR_CA_CA1_SHIFT (0U)
+#define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
+#define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU)
+#define CAU_STR_CA_CA2_SHIFT (0U)
+#define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
+#define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU)
+#define CAU_STR_CA_CA3_SHIFT (0U)
+#define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
+#define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU)
+#define CAU_STR_CA_CA4_SHIFT (0U)
+#define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
+#define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU)
+#define CAU_STR_CA_CA5_SHIFT (0U)
+#define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
+#define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU)
+#define CAU_STR_CA_CA6_SHIFT (0U)
+#define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
+#define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU)
+#define CAU_STR_CA_CA7_SHIFT (0U)
+#define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
+#define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU)
+#define CAU_STR_CA_CA8_SHIFT (0U)
+#define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
+/*! @} */
+
+/* The count of CAU_STR_CA */
+#define CAU_STR_CA_COUNT (9U)
+
+/*! @name ADR_CASR - Status register - Add Register command */
+/*! @{ */
+#define CAU_ADR_CASR_IC_MASK (0x1U)
+#define CAU_ADR_CASR_IC_SHIFT (0U)
+/*! IC
+ * 0b0..No illegal commands issued
+ * 0b1..Illegal command issued
+ */
+#define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
+#define CAU_ADR_CASR_DPE_MASK (0x2U)
+#define CAU_ADR_CASR_DPE_SHIFT (1U)
+/*! DPE
+ * 0b0..No error detected
+ * 0b1..DES key parity error detected
+ */
+#define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
+#define CAU_ADR_CASR_VER_MASK (0xF0000000U)
+#define CAU_ADR_CASR_VER_SHIFT (28U)
+/*! VER - CAU version
+ * 0b0001..Initial CAU version
+ * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
+ */
+#define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
+/*! @} */
+
+/*! @name ADR_CAA - Accumulator register - Add to register command */
+/*! @{ */
+#define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU)
+#define CAU_ADR_CAA_ACC_SHIFT (0U)
+#define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
+/*! @} */
+
+/*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command */
+/*! @{ */
+#define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA0_SHIFT (0U)
+#define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
+#define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA1_SHIFT (0U)
+#define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
+#define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA2_SHIFT (0U)
+#define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
+#define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA3_SHIFT (0U)
+#define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
+#define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA4_SHIFT (0U)
+#define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
+#define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA5_SHIFT (0U)
+#define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
+#define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA6_SHIFT (0U)
+#define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
+#define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA7_SHIFT (0U)
+#define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
+#define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA8_SHIFT (0U)
+#define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
+/*! @} */
+
+/* The count of CAU_ADR_CA */
+#define CAU_ADR_CA_COUNT (9U)
+
+/*! @name RADR_CASR - Status register - Reverse and Add to Register command */
+/*! @{ */
+#define CAU_RADR_CASR_IC_MASK (0x1U)
+#define CAU_RADR_CASR_IC_SHIFT (0U)
+/*! IC
+ * 0b0..No illegal commands issued
+ * 0b1..Illegal command issued
+ */
+#define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
+#define CAU_RADR_CASR_DPE_MASK (0x2U)
+#define CAU_RADR_CASR_DPE_SHIFT (1U)
+/*! DPE
+ * 0b0..No error detected
+ * 0b1..DES key parity error detected
+ */
+#define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
+#define CAU_RADR_CASR_VER_MASK (0xF0000000U)
+#define CAU_RADR_CASR_VER_SHIFT (28U)
+/*! VER - CAU version
+ * 0b0001..Initial CAU version
+ * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
+ */
+#define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
+/*! @} */
+
+/*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */
+/*! @{ */
+#define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU)
+#define CAU_RADR_CAA_ACC_SHIFT (0U)
+#define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
+/*! @} */
+
+/*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command */
+/*! @{ */
+#define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA0_SHIFT (0U)
+#define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
+#define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA1_SHIFT (0U)
+#define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
+#define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA2_SHIFT (0U)
+#define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
+#define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA3_SHIFT (0U)
+#define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
+#define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA4_SHIFT (0U)
+#define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
+#define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA5_SHIFT (0U)
+#define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
+#define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA6_SHIFT (0U)
+#define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
+#define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA7_SHIFT (0U)
+#define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
+#define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA8_SHIFT (0U)
+#define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
+/*! @} */
+
+/* The count of CAU_RADR_CA */
+#define CAU_RADR_CA_COUNT (9U)
+
+/*! @name XOR_CASR - Status register - Exclusive Or command */
+/*! @{ */
+#define CAU_XOR_CASR_IC_MASK (0x1U)
+#define CAU_XOR_CASR_IC_SHIFT (0U)
+/*! IC
+ * 0b0..No illegal commands issued
+ * 0b1..Illegal command issued
+ */
+#define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
+#define CAU_XOR_CASR_DPE_MASK (0x2U)
+#define CAU_XOR_CASR_DPE_SHIFT (1U)
+/*! DPE
+ * 0b0..No error detected
+ * 0b1..DES key parity error detected
+ */
+#define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
+#define CAU_XOR_CASR_VER_MASK (0xF0000000U)
+#define CAU_XOR_CASR_VER_SHIFT (28U)
+/*! VER - CAU version
+ * 0b0001..Initial CAU version
+ * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
+ */
+#define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
+/*! @} */
+
+/*! @name XOR_CAA - Accumulator register - Exclusive Or command */
+/*! @{ */
+#define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU)
+#define CAU_XOR_CAA_ACC_SHIFT (0U)
+#define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
+/*! @} */
+
+/*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command */
+/*! @{ */
+#define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA0_SHIFT (0U)
+#define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
+#define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA1_SHIFT (0U)
+#define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
+#define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA2_SHIFT (0U)
+#define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
+#define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA3_SHIFT (0U)
+#define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
+#define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA4_SHIFT (0U)
+#define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
+#define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA5_SHIFT (0U)
+#define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
+#define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA6_SHIFT (0U)
+#define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
+#define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA7_SHIFT (0U)
+#define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
+#define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA8_SHIFT (0U)
+#define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
+/*! @} */
+
+/* The count of CAU_XOR_CA */
+#define CAU_XOR_CA_COUNT (9U)
+
+/*! @name ROTL_CASR - Status register - Rotate Left command */
+/*! @{ */
+#define CAU_ROTL_CASR_IC_MASK (0x1U)
+#define CAU_ROTL_CASR_IC_SHIFT (0U)
+/*! IC
+ * 0b0..No illegal commands issued
+ * 0b1..Illegal command issued
+ */
+#define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
+#define CAU_ROTL_CASR_DPE_MASK (0x2U)
+#define CAU_ROTL_CASR_DPE_SHIFT (1U)
+/*! DPE
+ * 0b0..No error detected
+ * 0b1..DES key parity error detected
+ */
+#define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
+#define CAU_ROTL_CASR_VER_MASK (0xF0000000U)
+#define CAU_ROTL_CASR_VER_SHIFT (28U)
+/*! VER - CAU version
+ * 0b0001..Initial CAU version
+ * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
+ */
+#define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
+/*! @} */
+
+/*! @name ROTL_CAA - Accumulator register - Rotate Left command */
+/*! @{ */
+#define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU)
+#define CAU_ROTL_CAA_ACC_SHIFT (0U)
+#define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
+/*! @} */
+
+/*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command */
+/*! @{ */
+#define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA0_SHIFT (0U)
+#define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
+#define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA1_SHIFT (0U)
+#define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
+#define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA2_SHIFT (0U)
+#define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
+#define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA3_SHIFT (0U)
+#define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
+#define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA4_SHIFT (0U)
+#define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
+#define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA5_SHIFT (0U)
+#define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
+#define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA6_SHIFT (0U)
+#define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
+#define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA7_SHIFT (0U)
+#define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
+#define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA8_SHIFT (0U)
+#define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
+/*! @} */
+
+/* The count of CAU_ROTL_CA */
+#define CAU_ROTL_CA_COUNT (9U)
+
+/*! @name AESC_CASR - Status register - AES Column Operation command */
+/*! @{ */
+#define CAU_AESC_CASR_IC_MASK (0x1U)
+#define CAU_AESC_CASR_IC_SHIFT (0U)
+/*! IC
+ * 0b0..No illegal commands issued
+ * 0b1..Illegal command issued
+ */
+#define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
+#define CAU_AESC_CASR_DPE_MASK (0x2U)
+#define CAU_AESC_CASR_DPE_SHIFT (1U)
+/*! DPE
+ * 0b0..No error detected
+ * 0b1..DES key parity error detected
+ */
+#define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
+#define CAU_AESC_CASR_VER_MASK (0xF0000000U)
+#define CAU_AESC_CASR_VER_SHIFT (28U)
+/*! VER - CAU version
+ * 0b0001..Initial CAU version
+ * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
+ */
+#define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
+/*! @} */
+
+/*! @name AESC_CAA - Accumulator register - AES Column Operation command */
+/*! @{ */
+#define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU)
+#define CAU_AESC_CAA_ACC_SHIFT (0U)
+#define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
+/*! @} */
+
+/*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command */
+/*! @{ */
+#define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA0_SHIFT (0U)
+#define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
+#define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA1_SHIFT (0U)
+#define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
+#define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA2_SHIFT (0U)
+#define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
+#define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA3_SHIFT (0U)
+#define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
+#define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA4_SHIFT (0U)
+#define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
+#define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA5_SHIFT (0U)
+#define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
+#define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA6_SHIFT (0U)
+#define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
+#define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA7_SHIFT (0U)
+#define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
+#define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA8_SHIFT (0U)
+#define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
+/*! @} */
+
+/* The count of CAU_AESC_CA */
+#define CAU_AESC_CA_COUNT (9U)
+
+/*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */
+/*! @{ */
+#define CAU_AESIC_CASR_IC_MASK (0x1U)
+#define CAU_AESIC_CASR_IC_SHIFT (0U)
+/*! IC
+ * 0b0..No illegal commands issued
+ * 0b1..Illegal command issued
+ */
+#define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
+#define CAU_AESIC_CASR_DPE_MASK (0x2U)
+#define CAU_AESIC_CASR_DPE_SHIFT (1U)
+/*! DPE
+ * 0b0..No error detected
+ * 0b1..DES key parity error detected
+ */
+#define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
+#define CAU_AESIC_CASR_VER_MASK (0xF0000000U)
+#define CAU_AESIC_CASR_VER_SHIFT (28U)
+/*! VER - CAU version
+ * 0b0001..Initial CAU version
+ * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
+ */
+#define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
+/*! @} */
+
+/*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */
+/*! @{ */
+#define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU)
+#define CAU_AESIC_CAA_ACC_SHIFT (0U)
+#define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
+/*! @} */
+
+/*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command */
+/*! @{ */
+#define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA0_SHIFT (0U)
+#define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
+#define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA1_SHIFT (0U)
+#define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
+#define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA2_SHIFT (0U)
+#define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
+#define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA3_SHIFT (0U)
+#define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
+#define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA4_SHIFT (0U)
+#define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
+#define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA5_SHIFT (0U)
+#define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
+#define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA6_SHIFT (0U)
+#define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
+#define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA7_SHIFT (0U)
+#define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
+#define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA8_SHIFT (0U)
+#define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
+/*! @} */
+
+/* The count of CAU_AESIC_CA */
+#define CAU_AESIC_CA_COUNT (9U)
+
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Masks */
+
+
+/* CAU - Peripheral instance base addresses */
+/** Peripheral CAU base address */
+#define CAU_BASE (0xE0081000u)
+/** Peripheral CAU base pointer */
+#define CAU ((CAU_Type *)CAU_BASE)
+/** Array initializer of CAU peripheral base addresses */
+#define CAU_BASE_ADDRS { CAU_BASE }
+/** Array initializer of CAU peripheral base pointers */
+#define CAU_BASE_PTRS { CAU }
+
+/*!
+ * @}
+ */ /* end of group CAU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
+ __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
+ __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
+ __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
+ __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
+ __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
+} CMP_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/*! @name CR0 - CMP Control Register 0 */
+/*! @{ */
+#define CMP_CR0_HYSTCTR_MASK (0x3U)
+#define CMP_CR0_HYSTCTR_SHIFT (0U)
+/*! HYSTCTR - Comparator hard block hysteresis control
+ * 0b00..Level 0
+ * 0b01..Level 1
+ * 0b10..Level 2
+ * 0b11..Level 3
+ */
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK (0x70U)
+#define CMP_CR0_FILTER_CNT_SHIFT (4U)
+/*! FILTER_CNT - Filter Sample Count
+ * 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.
+ * 0b001..One sample must agree. The comparator output is simply sampled.
+ * 0b010..2 consecutive samples must agree.
+ * 0b011..3 consecutive samples must agree.
+ * 0b100..4 consecutive samples must agree.
+ * 0b101..5 consecutive samples must agree.
+ * 0b110..6 consecutive samples must agree.
+ * 0b111..7 consecutive samples must agree.
+ */
+#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
+/*! @} */
+
+/*! @name CR1 - CMP Control Register 1 */
+/*! @{ */
+#define CMP_CR1_EN_MASK (0x1U)
+#define CMP_CR1_EN_SHIFT (0U)
+/*! EN - Comparator Module Enable
+ * 0b0..Analog Comparator is disabled.
+ * 0b1..Analog Comparator is enabled.
+ */
+#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
+#define CMP_CR1_OPE_MASK (0x2U)
+#define CMP_CR1_OPE_SHIFT (1U)
+/*! OPE - Comparator Output Pin Enable
+ * 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.
+ * 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.
+ */
+#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
+#define CMP_CR1_COS_MASK (0x4U)
+#define CMP_CR1_COS_SHIFT (2U)
+/*! COS - Comparator Output Select
+ * 0b0..Set the filtered comparator output (CMPO) to equal COUT.
+ * 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.
+ */
+#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
+#define CMP_CR1_INV_MASK (0x8U)
+#define CMP_CR1_INV_SHIFT (3U)
+/*! INV - Comparator INVERT
+ * 0b0..Does not invert the comparator output.
+ * 0b1..Inverts the comparator output.
+ */
+#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
+#define CMP_CR1_PMODE_MASK (0x10U)
+#define CMP_CR1_PMODE_SHIFT (4U)
+/*! PMODE - Power Mode Select
+ * 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
+ * 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
+ */
+#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
+#define CMP_CR1_TRIGM_MASK (0x20U)
+#define CMP_CR1_TRIGM_SHIFT (5U)
+/*! TRIGM - Trigger Mode Enable
+ * 0b0..Trigger mode is disabled.
+ * 0b1..Trigger mode is enabled.
+ */
+#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
+#define CMP_CR1_WE_MASK (0x40U)
+#define CMP_CR1_WE_SHIFT (6U)
+/*! WE - Windowing Enable
+ * 0b0..Windowing mode is not selected.
+ * 0b1..Windowing mode is selected.
+ */
+#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
+#define CMP_CR1_SE_MASK (0x80U)
+#define CMP_CR1_SE_SHIFT (7U)
+/*! SE - Sample Enable
+ * 0b0..Sampling mode is not selected.
+ * 0b1..Sampling mode is selected.
+ */
+#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
+/*! @} */
+
+/*! @name FPR - CMP Filter Period Register */
+/*! @{ */
+#define CMP_FPR_FILT_PER_MASK (0xFFU)
+#define CMP_FPR_FILT_PER_SHIFT (0U)
+#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
+/*! @} */
+
+/*! @name SCR - CMP Status and Control Register */
+/*! @{ */
+#define CMP_SCR_COUT_MASK (0x1U)
+#define CMP_SCR_COUT_SHIFT (0U)
+#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
+#define CMP_SCR_CFF_MASK (0x2U)
+#define CMP_SCR_CFF_SHIFT (1U)
+/*! CFF - Analog Comparator Flag Falling
+ * 0b0..Falling-edge on COUT has not been detected.
+ * 0b1..Falling-edge on COUT has occurred.
+ */
+#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
+#define CMP_SCR_CFR_MASK (0x4U)
+#define CMP_SCR_CFR_SHIFT (2U)
+/*! CFR - Analog Comparator Flag Rising
+ * 0b0..Rising-edge on COUT has not been detected.
+ * 0b1..Rising-edge on COUT has occurred.
+ */
+#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
+#define CMP_SCR_IEF_MASK (0x8U)
+#define CMP_SCR_IEF_SHIFT (3U)
+/*! IEF - Comparator Interrupt Enable Falling
+ * 0b0..Interrupt is disabled.
+ * 0b1..Interrupt is enabled.
+ */
+#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
+#define CMP_SCR_IER_MASK (0x10U)
+#define CMP_SCR_IER_SHIFT (4U)
+/*! IER - Comparator Interrupt Enable Rising
+ * 0b0..Interrupt is disabled.
+ * 0b1..Interrupt is enabled.
+ */
+#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
+#define CMP_SCR_DMAEN_MASK (0x40U)
+#define CMP_SCR_DMAEN_SHIFT (6U)
+/*! DMAEN - DMA Enable Control
+ * 0b0..DMA is disabled.
+ * 0b1..DMA is enabled.
+ */
+#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
+/*! @} */
+
+/*! @name DACCR - DAC Control Register */
+/*! @{ */
+#define CMP_DACCR_VOSEL_MASK (0x3FU)
+#define CMP_DACCR_VOSEL_SHIFT (0U)
+#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK (0x40U)
+#define CMP_DACCR_VRSEL_SHIFT (6U)
+/*! VRSEL - Supply Voltage Reference Source Select
+ * 0b0..Vin1 is selected as resistor ladder network supply reference.
+ * 0b1..Vin2 is selected as resistor ladder network supply reference.
+ */
+#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
+#define CMP_DACCR_DACEN_MASK (0x80U)
+#define CMP_DACCR_DACEN_SHIFT (7U)
+/*! DACEN - DAC Enable
+ * 0b0..DAC is disabled.
+ * 0b1..DAC is enabled.
+ */
+#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
+/*! @} */
+
+/*! @name MUXCR - MUX Control Register */
+/*! @{ */
+#define CMP_MUXCR_MSEL_MASK (0x7U)
+#define CMP_MUXCR_MSEL_SHIFT (0U)
+/*! MSEL - Minus Input Mux Control
+ * 0b000..IN0
+ * 0b001..IN1
+ * 0b010..IN2
+ * 0b011..IN3
+ * 0b100..IN4
+ * 0b101..IN5
+ * 0b110..IN6
+ * 0b111..IN7
+ */
+#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK (0x38U)
+#define CMP_MUXCR_PSEL_SHIFT (3U)
+/*! PSEL - Plus Input Mux Control
+ * 0b000..IN0
+ * 0b001..IN1
+ * 0b010..IN2
+ * 0b011..IN3
+ * 0b100..IN4
+ * 0b101..IN5
+ * 0b110..IN6
+ * 0b111..IN7
+ */
+#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK (0x80U)
+#define CMP_MUXCR_PSTM_SHIFT (7U)
+/*! PSTM - Pass Through Mode Enable
+ * 0b0..Pass Through Mode is disabled.
+ * 0b1..Pass Through Mode is enabled.
+ */
+#define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0 ((CMP_Type *)CMP0_BASE)
+/** Peripheral CMP1 base address */
+#define CMP1_BASE (0x40073008u)
+/** Peripheral CMP1 base pointer */
+#define CMP1 ((CMP_Type *)CMP1_BASE)
+/** Peripheral CMP2 base address */
+#define CMP2_BASE (0x40073010u)
+/** Peripheral CMP2 base pointer */
+#define CMP2 ((CMP_Type *)CMP2_BASE)
+/** Peripheral CMP3 base address */
+#define CMP3_BASE (0x40073018u)
+/** Peripheral CMP3 base pointer */
+#define CMP3 ((CMP_Type *)CMP3_BASE)
+/** Array initializer of CMP peripheral base addresses */
+#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE, CMP3_BASE }
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASE_PTRS { CMP0, CMP1, CMP2, CMP3 }
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn, CMP3_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
+ * @{
+ */
+
+/** CMT - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
+ __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
+ __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
+ __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
+ __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
+ __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
+ __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
+ __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
+ __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
+ __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
+ __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
+ __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
+} CMT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CMT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Masks CMT Register Masks
+ * @{
+ */
+
+/*! @name CGH1 - CMT Carrier Generator High Data Register 1 */
+/*! @{ */
+#define CMT_CGH1_PH_MASK (0xFFU)
+#define CMT_CGH1_PH_SHIFT (0U)
+#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
+/*! @} */
+
+/*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */
+/*! @{ */
+#define CMT_CGL1_PL_MASK (0xFFU)
+#define CMT_CGL1_PL_SHIFT (0U)
+#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
+/*! @} */
+
+/*! @name CGH2 - CMT Carrier Generator High Data Register 2 */
+/*! @{ */
+#define CMT_CGH2_SH_MASK (0xFFU)
+#define CMT_CGH2_SH_SHIFT (0U)
+#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
+/*! @} */
+
+/*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */
+/*! @{ */
+#define CMT_CGL2_SL_MASK (0xFFU)
+#define CMT_CGL2_SL_SHIFT (0U)
+#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
+/*! @} */
+
+/*! @name OC - CMT Output Control Register */
+/*! @{ */
+#define CMT_OC_IROPEN_MASK (0x20U)
+#define CMT_OC_IROPEN_SHIFT (5U)
+/*! IROPEN - IRO Pin Enable
+ * 0b0..The IRO signal is disabled.
+ * 0b1..The IRO signal is enabled as output.
+ */
+#define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
+#define CMT_OC_CMTPOL_MASK (0x40U)
+#define CMT_OC_CMTPOL_SHIFT (6U)
+/*! CMTPOL - CMT Output Polarity
+ * 0b0..The IRO signal is active-low.
+ * 0b1..The IRO signal is active-high.
+ */
+#define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
+#define CMT_OC_IROL_MASK (0x80U)
+#define CMT_OC_IROL_SHIFT (7U)
+#define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
+/*! @} */
+
+/*! @name MSC - CMT Modulator Status and Control Register */
+/*! @{ */
+#define CMT_MSC_MCGEN_MASK (0x1U)
+#define CMT_MSC_MCGEN_SHIFT (0U)
+/*! MCGEN - Modulator and Carrier Generator Enable
+ * 0b0..Modulator and carrier generator disabled
+ * 0b1..Modulator and carrier generator enabled
+ */
+#define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
+#define CMT_MSC_EOCIE_MASK (0x2U)
+#define CMT_MSC_EOCIE_SHIFT (1U)
+/*! EOCIE - End of Cycle Interrupt Enable
+ * 0b0..CPU interrupt is disabled.
+ * 0b1..CPU interrupt is enabled.
+ */
+#define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
+#define CMT_MSC_FSK_MASK (0x4U)
+#define CMT_MSC_FSK_SHIFT (2U)
+/*! FSK - FSK Mode Select
+ * 0b0..The CMT operates in Time or Baseband mode.
+ * 0b1..The CMT operates in FSK mode.
+ */
+#define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
+#define CMT_MSC_BASE_MASK (0x8U)
+#define CMT_MSC_BASE_SHIFT (3U)
+/*! BASE - Baseband Enable
+ * 0b0..Baseband mode is disabled.
+ * 0b1..Baseband mode is enabled.
+ */
+#define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
+#define CMT_MSC_EXSPC_MASK (0x10U)
+#define CMT_MSC_EXSPC_SHIFT (4U)
+/*! EXSPC - Extended Space Enable
+ * 0b0..Extended space is disabled.
+ * 0b1..Extended space is enabled.
+ */
+#define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
+#define CMT_MSC_CMTDIV_MASK (0x60U)
+#define CMT_MSC_CMTDIV_SHIFT (5U)
+/*! CMTDIV - CMT Clock Divide Prescaler
+ * 0b00..IF * 1
+ * 0b01..IF * 2
+ * 0b10..IF * 4
+ * 0b11..IF * 8
+ */
+#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
+#define CMT_MSC_EOCF_MASK (0x80U)
+#define CMT_MSC_EOCF_SHIFT (7U)
+/*! EOCF - End Of Cycle Status Flag
+ * 0b0..End of modulation cycle has not occured since the flag last cleared.
+ * 0b1..End of modulator cycle has occurred.
+ */
+#define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
+/*! @} */
+
+/*! @name CMD1 - CMT Modulator Data Register Mark High */
+/*! @{ */
+#define CMT_CMD1_MB_MASK (0xFFU)
+#define CMT_CMD1_MB_SHIFT (0U)
+#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
+/*! @} */
+
+/*! @name CMD2 - CMT Modulator Data Register Mark Low */
+/*! @{ */
+#define CMT_CMD2_MB_MASK (0xFFU)
+#define CMT_CMD2_MB_SHIFT (0U)
+#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
+/*! @} */
+
+/*! @name CMD3 - CMT Modulator Data Register Space High */
+/*! @{ */
+#define CMT_CMD3_SB_MASK (0xFFU)
+#define CMT_CMD3_SB_SHIFT (0U)
+#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
+/*! @} */
+
+/*! @name CMD4 - CMT Modulator Data Register Space Low */
+/*! @{ */
+#define CMT_CMD4_SB_MASK (0xFFU)
+#define CMT_CMD4_SB_SHIFT (0U)
+#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
+/*! @} */
+
+/*! @name PPS - CMT Primary Prescaler Register */
+/*! @{ */
+#define CMT_PPS_PPSDIV_MASK (0xFU)
+#define CMT_PPS_PPSDIV_SHIFT (0U)
+/*! PPSDIV - Primary Prescaler Divider
+ * 0b0000..Bus clock * 1
+ * 0b0001..Bus clock * 2
+ * 0b0010..Bus clock * 3
+ * 0b0011..Bus clock * 4
+ * 0b0100..Bus clock * 5
+ * 0b0101..Bus clock * 6
+ * 0b0110..Bus clock * 7
+ * 0b0111..Bus clock * 8
+ * 0b1000..Bus clock * 9
+ * 0b1001..Bus clock * 10
+ * 0b1010..Bus clock * 11
+ * 0b1011..Bus clock * 12
+ * 0b1100..Bus clock * 13
+ * 0b1101..Bus clock * 14
+ * 0b1110..Bus clock * 15
+ * 0b1111..Bus clock * 16
+ */
+#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
+/*! @} */
+
+/*! @name DMA - CMT Direct Memory Access Register */
+/*! @{ */
+#define CMT_DMA_DMA_MASK (0x1U)
+#define CMT_DMA_DMA_SHIFT (0U)
+/*! DMA - DMA Enable
+ * 0b0..DMA transfer request and done are disabled.
+ * 0b1..DMA transfer request and done are enabled.
+ */
+#define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Masks */
+
+
+/* CMT - Peripheral instance base addresses */
+/** Peripheral CMT base address */
+#define CMT_BASE (0x40062000u)
+/** Peripheral CMT base pointer */
+#define CMT ((CMT_Type *)CMT_BASE)
+/** Array initializer of CMT peripheral base addresses */
+#define CMT_BASE_ADDRS { CMT_BASE }
+/** Array initializer of CMT peripheral base pointers */
+#define CMT_BASE_PTRS { CMT }
+/** Interrupt vectors for the CMT peripheral type */
+#define CMT_IRQS { CMT_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CMT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CRC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+ union { /* offset: 0x0 */
+ struct { /* offset: 0x0 */
+ __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
+ __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
+ } ACCESS16BIT;
+ __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
+ struct { /* offset: 0x0 */
+ __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
+ __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
+ __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
+ __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
+ } ACCESS8BIT;
+ };
+ union { /* offset: 0x4 */
+ struct { /* offset: 0x4 */
+ __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
+ __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
+ } GPOLY_ACCESS16BIT;
+ __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
+ struct { /* offset: 0x4 */
+ __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
+ __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
+ __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
+ __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
+ } GPOLY_ACCESS8BIT;
+ };
+ union { /* offset: 0x8 */
+ __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
+ struct { /* offset: 0x8 */
+ uint8_t RESERVED_0[3];
+ __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
+ } CTRL_ACCESS8BIT;
+ };
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CRC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/*! @name DATAL - CRC_DATAL register. */
+/*! @{ */
+#define CRC_DATAL_DATAL_MASK (0xFFFFU)
+#define CRC_DATAL_DATAL_SHIFT (0U)
+#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
+/*! @} */
+
+/*! @name DATAH - CRC_DATAH register. */
+/*! @{ */
+#define CRC_DATAH_DATAH_MASK (0xFFFFU)
+#define CRC_DATAH_DATAH_SHIFT (0U)
+#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
+/*! @} */
+
+/*! @name DATA - CRC Data register */
+/*! @{ */
+#define CRC_DATA_LL_MASK (0xFFU)
+#define CRC_DATA_LL_SHIFT (0U)
+#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
+#define CRC_DATA_LU_MASK (0xFF00U)
+#define CRC_DATA_LU_SHIFT (8U)
+#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
+#define CRC_DATA_HL_MASK (0xFF0000U)
+#define CRC_DATA_HL_SHIFT (16U)
+#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
+#define CRC_DATA_HU_MASK (0xFF000000U)
+#define CRC_DATA_HU_SHIFT (24U)
+#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
+/*! @} */
+
+/*! @name DATALL - CRC_DATALL register. */
+/*! @{ */
+#define CRC_DATALL_DATALL_MASK (0xFFU)
+#define CRC_DATALL_DATALL_SHIFT (0U)
+#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
+/*! @} */
+
+/*! @name DATALU - CRC_DATALU register. */
+/*! @{ */
+#define CRC_DATALU_DATALU_MASK (0xFFU)
+#define CRC_DATALU_DATALU_SHIFT (0U)
+#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
+/*! @} */
+
+/*! @name DATAHL - CRC_DATAHL register. */
+/*! @{ */
+#define CRC_DATAHL_DATAHL_MASK (0xFFU)
+#define CRC_DATAHL_DATAHL_SHIFT (0U)
+#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
+/*! @} */
+
+/*! @name DATAHU - CRC_DATAHU register. */
+/*! @{ */
+#define CRC_DATAHU_DATAHU_MASK (0xFFU)
+#define CRC_DATAHU_DATAHU_SHIFT (0U)
+#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
+/*! @} */
+
+/*! @name GPOLYL - CRC_GPOLYL register. */
+/*! @{ */
+#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
+#define CRC_GPOLYL_GPOLYL_SHIFT (0U)
+#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
+/*! @} */
+
+/*! @name GPOLYH - CRC_GPOLYH register. */
+/*! @{ */
+#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
+#define CRC_GPOLYH_GPOLYH_SHIFT (0U)
+#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
+/*! @} */
+
+/*! @name GPOLY - CRC Polynomial register */
+/*! @{ */
+#define CRC_GPOLY_LOW_MASK (0xFFFFU)
+#define CRC_GPOLY_LOW_SHIFT (0U)
+#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
+#define CRC_GPOLY_HIGH_SHIFT (16U)
+#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
+/*! @} */
+
+/*! @name GPOLYLL - CRC_GPOLYLL register. */
+/*! @{ */
+#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
+#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
+#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
+/*! @} */
+
+/*! @name GPOLYLU - CRC_GPOLYLU register. */
+/*! @{ */
+#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
+#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
+#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
+/*! @} */
+
+/*! @name GPOLYHL - CRC_GPOLYHL register. */
+/*! @{ */
+#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
+#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
+#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
+/*! @} */
+
+/*! @name GPOLYHU - CRC_GPOLYHU register. */
+/*! @{ */
+#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
+#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
+#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
+/*! @} */
+
+/*! @name CTRL - CRC Control register */
+/*! @{ */
+#define CRC_CTRL_TCRC_MASK (0x1000000U)
+#define CRC_CTRL_TCRC_SHIFT (24U)
+/*! TCRC
+ * 0b0..16-bit CRC protocol.
+ * 0b1..32-bit CRC protocol.
+ */
+#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
+#define CRC_CTRL_WAS_MASK (0x2000000U)
+#define CRC_CTRL_WAS_SHIFT (25U)
+/*! WAS - Write CRC Data Register As Seed
+ * 0b0..Writes to the CRC data register are data values.
+ * 0b1..Writes to the CRC data register are seed values.
+ */
+#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
+#define CRC_CTRL_FXOR_MASK (0x4000000U)
+#define CRC_CTRL_FXOR_SHIFT (26U)
+/*! FXOR - Complement Read Of CRC Data Register
+ * 0b0..No XOR on reading.
+ * 0b1..Invert or complement the read value of the CRC Data register.
+ */
+#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
+#define CRC_CTRL_TOTR_MASK (0x30000000U)
+#define CRC_CTRL_TOTR_SHIFT (28U)
+/*! TOTR - Type Of Transpose For Read
+ * 0b00..No transposition.
+ * 0b01..Bits in bytes are transposed; bytes are not transposed.
+ * 0b10..Both bits in bytes and bytes are transposed.
+ * 0b11..Only bytes are transposed; no bits in a byte are transposed.
+ */
+#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK (0xC0000000U)
+#define CRC_CTRL_TOT_SHIFT (30U)
+/*! TOT - Type Of Transpose For Writes
+ * 0b00..No transposition.
+ * 0b01..Bits in bytes are transposed; bytes are not transposed.
+ * 0b10..Both bits in bytes and bytes are transposed.
+ * 0b11..Only bytes are transposed; no bits in a byte are transposed.
+ */
+#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
+/*! @} */
+
+/*! @name CTRLHU - CRC_CTRLHU register. */
+/*! @{ */
+#define CRC_CTRLHU_TCRC_MASK (0x1U)
+#define CRC_CTRLHU_TCRC_SHIFT (0U)
+/*! TCRC
+ * 0b0..16-bit CRC protocol.
+ * 0b1..32-bit CRC protocol.
+ */
+#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
+#define CRC_CTRLHU_WAS_MASK (0x2U)
+#define CRC_CTRLHU_WAS_SHIFT (1U)
+/*! WAS
+ * 0b0..Writes to CRC data register are data values.
+ * 0b1..Writes to CRC data reguster are seed values.
+ */
+#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
+#define CRC_CTRLHU_FXOR_MASK (0x4U)
+#define CRC_CTRLHU_FXOR_SHIFT (2U)
+/*! FXOR
+ * 0b0..No XOR on reading.
+ * 0b1..Invert or complement the read value of CRC data register.
+ */
+#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
+#define CRC_CTRLHU_TOTR_MASK (0x30U)
+#define CRC_CTRLHU_TOTR_SHIFT (4U)
+/*! TOTR
+ * 0b00..No Transposition.
+ * 0b01..Bits in bytes are transposed, bytes are not transposed.
+ * 0b10..Both bits in bytes and bytes are transposed.
+ * 0b11..Only bytes are transposed; no bits in a byte are transposed.
+ */
+#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK (0xC0U)
+#define CRC_CTRLHU_TOT_SHIFT (6U)
+/*! TOT
+ * 0b00..No Transposition.
+ * 0b01..Bits in bytes are transposed, bytes are not transposed.
+ * 0b10..Both bits in bytes and bytes are transposed.
+ * 0b11..Only bytes are transposed; no bits in a byte are transposed.
+ */
+#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE (0x40032000u)
+/** Peripheral CRC base pointer */
+#define CRC0 ((CRC_Type *)CRC_BASE)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS { CRC_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS { CRC0 }
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+ } DAT[16];
+ __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
+ __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
+ __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
+ __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DAC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/*! @name DATL - DAC Data Low Register */
+/*! @{ */
+#define DAC_DATL_DATA0_MASK (0xFFU)
+#define DAC_DATL_DATA0_SHIFT (0U)
+#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
+/*! @} */
+
+/* The count of DAC_DATL */
+#define DAC_DATL_COUNT (16U)
+
+/*! @name DATH - DAC Data High Register */
+/*! @{ */
+#define DAC_DATH_DATA1_MASK (0xFU)
+#define DAC_DATH_DATA1_SHIFT (0U)
+#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
+/*! @} */
+
+/* The count of DAC_DATH */
+#define DAC_DATH_COUNT (16U)
+
+/*! @name SR - DAC Status Register */
+/*! @{ */
+#define DAC_SR_DACBFRPBF_MASK (0x1U)
+#define DAC_SR_DACBFRPBF_SHIFT (0U)
+/*! DACBFRPBF - DAC Buffer Read Pointer Bottom Position Flag
+ * 0b0..The DAC buffer read pointer is not equal to C2[DACBFUP].
+ * 0b1..The DAC buffer read pointer is equal to C2[DACBFUP].
+ */
+#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
+#define DAC_SR_DACBFRPTF_MASK (0x2U)
+#define DAC_SR_DACBFRPTF_SHIFT (1U)
+/*! DACBFRPTF - DAC Buffer Read Pointer Top Position Flag
+ * 0b0..The DAC buffer read pointer is not zero.
+ * 0b1..The DAC buffer read pointer is zero.
+ */
+#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
+#define DAC_SR_DACBFWMF_MASK (0x4U)
+#define DAC_SR_DACBFWMF_SHIFT (2U)
+/*! DACBFWMF - DAC Buffer Watermark Flag
+ * 0b0..The DAC buffer read pointer has not reached the watermark level.
+ * 0b1..The DAC buffer read pointer has reached the watermark level.
+ */
+#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
+/*! @} */
+
+/*! @name C0 - DAC Control Register */
+/*! @{ */
+#define DAC_C0_DACBBIEN_MASK (0x1U)
+#define DAC_C0_DACBBIEN_SHIFT (0U)
+/*! DACBBIEN - DAC Buffer Read Pointer Bottom Flag Interrupt Enable
+ * 0b0..The DAC buffer read pointer bottom flag interrupt is disabled.
+ * 0b1..The DAC buffer read pointer bottom flag interrupt is enabled.
+ */
+#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
+#define DAC_C0_DACBTIEN_MASK (0x2U)
+#define DAC_C0_DACBTIEN_SHIFT (1U)
+/*! DACBTIEN - DAC Buffer Read Pointer Top Flag Interrupt Enable
+ * 0b0..The DAC buffer read pointer top flag interrupt is disabled.
+ * 0b1..The DAC buffer read pointer top flag interrupt is enabled.
+ */
+#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
+#define DAC_C0_DACBWIEN_MASK (0x4U)
+#define DAC_C0_DACBWIEN_SHIFT (2U)
+/*! DACBWIEN - DAC Buffer Watermark Interrupt Enable
+ * 0b0..The DAC buffer watermark interrupt is disabled.
+ * 0b1..The DAC buffer watermark interrupt is enabled.
+ */
+#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
+#define DAC_C0_LPEN_MASK (0x8U)
+#define DAC_C0_LPEN_SHIFT (3U)
+/*! LPEN - DAC Low Power Control
+ * 0b0..High-Power mode
+ * 0b1..Low-Power mode
+ */
+#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
+#define DAC_C0_DACSWTRG_MASK (0x10U)
+#define DAC_C0_DACSWTRG_SHIFT (4U)
+/*! DACSWTRG - DAC Software Trigger
+ * 0b0..The DAC soft trigger is not valid.
+ * 0b1..The DAC soft trigger is valid.
+ */
+#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
+#define DAC_C0_DACTRGSEL_MASK (0x20U)
+#define DAC_C0_DACTRGSEL_SHIFT (5U)
+/*! DACTRGSEL - DAC Trigger Select
+ * 0b0..The DAC hardware trigger is selected.
+ * 0b1..The DAC software trigger is selected.
+ */
+#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
+#define DAC_C0_DACRFS_MASK (0x40U)
+#define DAC_C0_DACRFS_SHIFT (6U)
+/*! DACRFS - DAC Reference Select
+ * 0b0..The DAC selects DACREF_1 as the reference voltage.
+ * 0b1..The DAC selects DACREF_2 as the reference voltage.
+ */
+#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
+#define DAC_C0_DACEN_MASK (0x80U)
+#define DAC_C0_DACEN_SHIFT (7U)
+/*! DACEN - DAC Enable
+ * 0b0..The DAC system is disabled.
+ * 0b1..The DAC system is enabled.
+ */
+#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
+/*! @} */
+
+/*! @name C1 - DAC Control Register 1 */
+/*! @{ */
+#define DAC_C1_DACBFEN_MASK (0x1U)
+#define DAC_C1_DACBFEN_SHIFT (0U)
+/*! DACBFEN - DAC Buffer Enable
+ * 0b0..Buffer read pointer is disabled. The converted data is always the first word of the buffer.
+ * 0b1..Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer.
+ */
+#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
+#define DAC_C1_DACBFMD_MASK (0x6U)
+#define DAC_C1_DACBFMD_SHIFT (1U)
+/*! DACBFMD - DAC Buffer Work Mode Select
+ * 0b00..Normal mode
+ * 0b01..Swing mode
+ * 0b10..One-Time Scan mode
+ * 0b11..Reserved
+ */
+#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DACBFWM_MASK (0x18U)
+#define DAC_C1_DACBFWM_SHIFT (3U)
+/*! DACBFWM - DAC Buffer Watermark Select
+ * 0b00..1 word
+ * 0b01..2 words
+ * 0b10..3 words
+ * 0b11..4 words
+ */
+#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
+#define DAC_C1_DMAEN_MASK (0x80U)
+#define DAC_C1_DMAEN_SHIFT (7U)
+/*! DMAEN - DMA Enable Select
+ * 0b0..DMA is disabled.
+ * 0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time.
+ */
+#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
+/*! @} */
+
+/*! @name C2 - DAC Control Register 2 */
+/*! @{ */
+#define DAC_C2_DACBFUP_MASK (0xFU)
+#define DAC_C2_DACBFUP_SHIFT (0U)
+#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFRP_MASK (0xF0U)
+#define DAC_C2_DACBFRP_SHIFT (4U)
+#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE (0x400CC000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0 ((DAC_Type *)DAC0_BASE)
+/** Peripheral DAC1 base address */
+#define DAC1_BASE (0x400CD000u)
+/** Peripheral DAC1 base pointer */
+#define DAC1 ((DAC_Type *)DAC1_BASE)
+/** Array initializer of DAC peripheral base addresses */
+#define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASE_PTRS { DAC0, DAC1 }
+/** Interrupt vectors for the DAC peripheral type */
+#define DAC_IRQS { DAC0_IRQn, DAC1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CR; /**< Control Register, offset: 0x0 */
+ __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
+ __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
+ __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
+ __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
+ __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
+ __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
+ __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
+ __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
+ __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
+ uint8_t RESERVED_4[4];
+ __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
+ uint8_t RESERVED_5[12];
+ __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
+ uint8_t RESERVED_6[184];
+ __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
+ __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
+ __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
+ __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
+ __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
+ __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
+ __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
+ __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
+ __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
+ __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
+ __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
+ __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
+ __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
+ __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
+ __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
+ __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
+ __IO uint8_t DCHPRI19; /**< Channel n Priority Register, offset: 0x110 */
+ __IO uint8_t DCHPRI18; /**< Channel n Priority Register, offset: 0x111 */
+ __IO uint8_t DCHPRI17; /**< Channel n Priority Register, offset: 0x112 */
+ __IO uint8_t DCHPRI16; /**< Channel n Priority Register, offset: 0x113 */
+ __IO uint8_t DCHPRI23; /**< Channel n Priority Register, offset: 0x114 */
+ __IO uint8_t DCHPRI22; /**< Channel n Priority Register, offset: 0x115 */
+ __IO uint8_t DCHPRI21; /**< Channel n Priority Register, offset: 0x116 */
+ __IO uint8_t DCHPRI20; /**< Channel n Priority Register, offset: 0x117 */
+ __IO uint8_t DCHPRI27; /**< Channel n Priority Register, offset: 0x118 */
+ __IO uint8_t DCHPRI26; /**< Channel n Priority Register, offset: 0x119 */
+ __IO uint8_t DCHPRI25; /**< Channel n Priority Register, offset: 0x11A */
+ __IO uint8_t DCHPRI24; /**< Channel n Priority Register, offset: 0x11B */
+ __IO uint8_t DCHPRI31; /**< Channel n Priority Register, offset: 0x11C */
+ __IO uint8_t DCHPRI30; /**< Channel n Priority Register, offset: 0x11D */
+ __IO uint8_t DCHPRI29; /**< Channel n Priority Register, offset: 0x11E */
+ __IO uint8_t DCHPRI28; /**< Channel n Priority Register, offset: 0x11F */
+ uint8_t RESERVED_7[3808];
+ struct { /* offset: 0x1000, array step: 0x20 */
+ __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
+ __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
+ __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
+ union { /* offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
+ };
+ __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
+ __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
+ __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
+ union { /* offset: 0x1016, array step: 0x20 */
+ __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
+ __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
+ };
+ __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+ __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
+ union { /* offset: 0x101E, array step: 0x20 */
+ __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
+ __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
+ };
+ } TCD[32];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/*! @name CR - Control Register */
+/*! @{ */
+#define DMA_CR_EDBG_MASK (0x2U)
+#define DMA_CR_EDBG_SHIFT (1U)
+/*! EDBG - Enable Debug
+ * 0b0..When in debug mode, the DMA continues to operate.
+ * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
+ */
+#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
+#define DMA_CR_ERCA_MASK (0x4U)
+#define DMA_CR_ERCA_SHIFT (2U)
+/*! ERCA - Enable Round Robin Channel Arbitration
+ * 0b0..Fixed priority arbitration is used for channel selection within each group.
+ * 0b1..Round robin arbitration is used for channel selection within each group.
+ */
+#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
+#define DMA_CR_ERGA_MASK (0x8U)
+#define DMA_CR_ERGA_SHIFT (3U)
+/*! ERGA - Enable Round Robin Group Arbitration
+ * 0b0..Fixed priority arbitration is used for selection among the groups.
+ * 0b1..Round robin arbitration is used for selection among the groups.
+ */
+#define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
+#define DMA_CR_HOE_MASK (0x10U)
+#define DMA_CR_HOE_SHIFT (4U)
+/*! HOE - Halt On Error
+ * 0b0..Normal operation
+ * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.
+ */
+#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
+#define DMA_CR_HALT_MASK (0x20U)
+#define DMA_CR_HALT_SHIFT (5U)
+/*! HALT - Halt DMA Operations
+ * 0b0..Normal operation
+ * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.
+ */
+#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
+#define DMA_CR_CLM_MASK (0x40U)
+#define DMA_CR_CLM_SHIFT (6U)
+/*! CLM - Continuous Link Mode
+ * 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again.
+ * 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.
+ */
+#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
+#define DMA_CR_EMLM_MASK (0x80U)
+#define DMA_CR_EMLM_SHIFT (7U)
+/*! EMLM - Enable Minor Loop Mapping
+ * 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
+ * 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.
+ */
+#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
+#define DMA_CR_GRP0PRI_MASK (0x100U)
+#define DMA_CR_GRP0PRI_SHIFT (8U)
+#define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
+#define DMA_CR_GRP1PRI_MASK (0x400U)
+#define DMA_CR_GRP1PRI_SHIFT (10U)
+#define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
+#define DMA_CR_ECX_MASK (0x10000U)
+#define DMA_CR_ECX_SHIFT (16U)
+/*! ECX - Error Cancel Transfer
+ * 0b0..Normal operation
+ * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.
+ */
+#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
+#define DMA_CR_CX_MASK (0x20000U)
+#define DMA_CR_CX_SHIFT (17U)
+/*! CX - Cancel Transfer
+ * 0b0..Normal operation
+ * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
+ */
+#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
+/*! @} */
+
+/*! @name ES - Error Status Register */
+/*! @{ */
+#define DMA_ES_DBE_MASK (0x1U)
+#define DMA_ES_DBE_SHIFT (0U)
+/*! DBE - Destination Bus Error
+ * 0b0..No destination bus error
+ * 0b1..The last recorded error was a bus error on a destination write
+ */
+#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
+#define DMA_ES_SBE_MASK (0x2U)
+#define DMA_ES_SBE_SHIFT (1U)
+/*! SBE - Source Bus Error
+ * 0b0..No source bus error
+ * 0b1..The last recorded error was a bus error on a source read
+ */
+#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
+#define DMA_ES_SGE_MASK (0x4U)
+#define DMA_ES_SGE_SHIFT (2U)
+/*! SGE - Scatter/Gather Configuration Error
+ * 0b0..No scatter/gather configuration error
+ * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
+ */
+#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
+#define DMA_ES_NCE_MASK (0x8U)
+#define DMA_ES_NCE_SHIFT (3U)
+/*! NCE - NBYTES/CITER Configuration Error
+ * 0b0..No NBYTES/CITER configuration error
+ * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
+ */
+#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
+#define DMA_ES_DOE_MASK (0x10U)
+#define DMA_ES_DOE_SHIFT (4U)
+/*! DOE - Destination Offset Error
+ * 0b0..No destination offset configuration error
+ * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
+ */
+#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
+#define DMA_ES_DAE_MASK (0x20U)
+#define DMA_ES_DAE_SHIFT (5U)
+/*! DAE - Destination Address Error
+ * 0b0..No destination address configuration error
+ * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
+ */
+#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
+#define DMA_ES_SOE_MASK (0x40U)
+#define DMA_ES_SOE_SHIFT (6U)
+/*! SOE - Source Offset Error
+ * 0b0..No source offset configuration error
+ * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
+ */
+#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
+#define DMA_ES_SAE_MASK (0x80U)
+#define DMA_ES_SAE_SHIFT (7U)
+/*! SAE - Source Address Error
+ * 0b0..No source address configuration error.
+ * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
+ */
+#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
+#define DMA_ES_ERRCHN_MASK (0x1F00U)
+#define DMA_ES_ERRCHN_SHIFT (8U)
+#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK (0x4000U)
+#define DMA_ES_CPE_SHIFT (14U)
+/*! CPE - Channel Priority Error
+ * 0b0..No channel priority error
+ * 0b1..The last recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique.
+ */
+#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
+#define DMA_ES_GPE_MASK (0x8000U)
+#define DMA_ES_GPE_SHIFT (15U)
+/*! GPE - Group Priority Error
+ * 0b0..No group priority error
+ * 0b1..The last recorded error was a configuration error among the group priorities. All group priorities are not unique.
+ */
+#define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
+#define DMA_ES_ECX_MASK (0x10000U)
+#define DMA_ES_ECX_SHIFT (16U)
+/*! ECX - Transfer Canceled
+ * 0b0..No canceled transfers
+ * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input
+ */
+#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
+#define DMA_ES_VLD_MASK (0x80000000U)
+#define DMA_ES_VLD_SHIFT (31U)
+/*! VLD
+ * 0b0..No ERR bits are set.
+ * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared.
+ */
+#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
+/*! @} */
+
+/*! @name ERQ - Enable Request Register */
+/*! @{ */
+#define DMA_ERQ_ERQ0_MASK (0x1U)
+#define DMA_ERQ_ERQ0_SHIFT (0U)
+/*! ERQ0 - Enable DMA Request 0
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
+#define DMA_ERQ_ERQ1_MASK (0x2U)
+#define DMA_ERQ_ERQ1_SHIFT (1U)
+/*! ERQ1 - Enable DMA Request 1
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
+#define DMA_ERQ_ERQ2_MASK (0x4U)
+#define DMA_ERQ_ERQ2_SHIFT (2U)
+/*! ERQ2 - Enable DMA Request 2
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
+#define DMA_ERQ_ERQ3_MASK (0x8U)
+#define DMA_ERQ_ERQ3_SHIFT (3U)
+/*! ERQ3 - Enable DMA Request 3
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
+#define DMA_ERQ_ERQ4_MASK (0x10U)
+#define DMA_ERQ_ERQ4_SHIFT (4U)
+/*! ERQ4 - Enable DMA Request 4
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
+#define DMA_ERQ_ERQ5_MASK (0x20U)
+#define DMA_ERQ_ERQ5_SHIFT (5U)
+/*! ERQ5 - Enable DMA Request 5
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
+#define DMA_ERQ_ERQ6_MASK (0x40U)
+#define DMA_ERQ_ERQ6_SHIFT (6U)
+/*! ERQ6 - Enable DMA Request 6
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
+#define DMA_ERQ_ERQ7_MASK (0x80U)
+#define DMA_ERQ_ERQ7_SHIFT (7U)
+/*! ERQ7 - Enable DMA Request 7
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
+#define DMA_ERQ_ERQ8_MASK (0x100U)
+#define DMA_ERQ_ERQ8_SHIFT (8U)
+/*! ERQ8 - Enable DMA Request 8
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
+#define DMA_ERQ_ERQ9_MASK (0x200U)
+#define DMA_ERQ_ERQ9_SHIFT (9U)
+/*! ERQ9 - Enable DMA Request 9
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
+#define DMA_ERQ_ERQ10_MASK (0x400U)
+#define DMA_ERQ_ERQ10_SHIFT (10U)
+/*! ERQ10 - Enable DMA Request 10
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
+#define DMA_ERQ_ERQ11_MASK (0x800U)
+#define DMA_ERQ_ERQ11_SHIFT (11U)
+/*! ERQ11 - Enable DMA Request 11
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
+#define DMA_ERQ_ERQ12_MASK (0x1000U)
+#define DMA_ERQ_ERQ12_SHIFT (12U)
+/*! ERQ12 - Enable DMA Request 12
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
+#define DMA_ERQ_ERQ13_MASK (0x2000U)
+#define DMA_ERQ_ERQ13_SHIFT (13U)
+/*! ERQ13 - Enable DMA Request 13
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
+#define DMA_ERQ_ERQ14_MASK (0x4000U)
+#define DMA_ERQ_ERQ14_SHIFT (14U)
+/*! ERQ14 - Enable DMA Request 14
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
+#define DMA_ERQ_ERQ15_MASK (0x8000U)
+#define DMA_ERQ_ERQ15_SHIFT (15U)
+/*! ERQ15 - Enable DMA Request 15
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
+#define DMA_ERQ_ERQ16_MASK (0x10000U)
+#define DMA_ERQ_ERQ16_SHIFT (16U)
+/*! ERQ16 - Enable DMA Request 16
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
+#define DMA_ERQ_ERQ17_MASK (0x20000U)
+#define DMA_ERQ_ERQ17_SHIFT (17U)
+/*! ERQ17 - Enable DMA Request 17
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
+#define DMA_ERQ_ERQ18_MASK (0x40000U)
+#define DMA_ERQ_ERQ18_SHIFT (18U)
+/*! ERQ18 - Enable DMA Request 18
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
+#define DMA_ERQ_ERQ19_MASK (0x80000U)
+#define DMA_ERQ_ERQ19_SHIFT (19U)
+/*! ERQ19 - Enable DMA Request 19
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
+#define DMA_ERQ_ERQ20_MASK (0x100000U)
+#define DMA_ERQ_ERQ20_SHIFT (20U)
+/*! ERQ20 - Enable DMA Request 20
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
+#define DMA_ERQ_ERQ21_MASK (0x200000U)
+#define DMA_ERQ_ERQ21_SHIFT (21U)
+/*! ERQ21 - Enable DMA Request 21
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
+#define DMA_ERQ_ERQ22_MASK (0x400000U)
+#define DMA_ERQ_ERQ22_SHIFT (22U)
+/*! ERQ22 - Enable DMA Request 22
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
+#define DMA_ERQ_ERQ23_MASK (0x800000U)
+#define DMA_ERQ_ERQ23_SHIFT (23U)
+/*! ERQ23 - Enable DMA Request 23
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
+#define DMA_ERQ_ERQ24_MASK (0x1000000U)
+#define DMA_ERQ_ERQ24_SHIFT (24U)
+/*! ERQ24 - Enable DMA Request 24
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
+#define DMA_ERQ_ERQ25_MASK (0x2000000U)
+#define DMA_ERQ_ERQ25_SHIFT (25U)
+/*! ERQ25 - Enable DMA Request 25
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
+#define DMA_ERQ_ERQ26_MASK (0x4000000U)
+#define DMA_ERQ_ERQ26_SHIFT (26U)
+/*! ERQ26 - Enable DMA Request 26
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
+#define DMA_ERQ_ERQ27_MASK (0x8000000U)
+#define DMA_ERQ_ERQ27_SHIFT (27U)
+/*! ERQ27 - Enable DMA Request 27
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
+#define DMA_ERQ_ERQ28_MASK (0x10000000U)
+#define DMA_ERQ_ERQ28_SHIFT (28U)
+/*! ERQ28 - Enable DMA Request 28
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
+#define DMA_ERQ_ERQ29_MASK (0x20000000U)
+#define DMA_ERQ_ERQ29_SHIFT (29U)
+/*! ERQ29 - Enable DMA Request 29
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
+#define DMA_ERQ_ERQ30_MASK (0x40000000U)
+#define DMA_ERQ_ERQ30_SHIFT (30U)
+/*! ERQ30 - Enable DMA Request 30
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
+#define DMA_ERQ_ERQ31_MASK (0x80000000U)
+#define DMA_ERQ_ERQ31_SHIFT (31U)
+/*! ERQ31 - Enable DMA Request 31
+ * 0b0..The DMA request signal for the corresponding channel is disabled
+ * 0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
+/*! @} */
+
+/*! @name EEI - Enable Error Interrupt Register */
+/*! @{ */
+#define DMA_EEI_EEI0_MASK (0x1U)
+#define DMA_EEI_EEI0_SHIFT (0U)
+/*! EEI0 - Enable Error Interrupt 0
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
+#define DMA_EEI_EEI1_MASK (0x2U)
+#define DMA_EEI_EEI1_SHIFT (1U)
+/*! EEI1 - Enable Error Interrupt 1
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
+#define DMA_EEI_EEI2_MASK (0x4U)
+#define DMA_EEI_EEI2_SHIFT (2U)
+/*! EEI2 - Enable Error Interrupt 2
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
+#define DMA_EEI_EEI3_MASK (0x8U)
+#define DMA_EEI_EEI3_SHIFT (3U)
+/*! EEI3 - Enable Error Interrupt 3
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
+#define DMA_EEI_EEI4_MASK (0x10U)
+#define DMA_EEI_EEI4_SHIFT (4U)
+/*! EEI4 - Enable Error Interrupt 4
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
+#define DMA_EEI_EEI5_MASK (0x20U)
+#define DMA_EEI_EEI5_SHIFT (5U)
+/*! EEI5 - Enable Error Interrupt 5
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
+#define DMA_EEI_EEI6_MASK (0x40U)
+#define DMA_EEI_EEI6_SHIFT (6U)
+/*! EEI6 - Enable Error Interrupt 6
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
+#define DMA_EEI_EEI7_MASK (0x80U)
+#define DMA_EEI_EEI7_SHIFT (7U)
+/*! EEI7 - Enable Error Interrupt 7
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
+#define DMA_EEI_EEI8_MASK (0x100U)
+#define DMA_EEI_EEI8_SHIFT (8U)
+/*! EEI8 - Enable Error Interrupt 8
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
+#define DMA_EEI_EEI9_MASK (0x200U)
+#define DMA_EEI_EEI9_SHIFT (9U)
+/*! EEI9 - Enable Error Interrupt 9
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
+#define DMA_EEI_EEI10_MASK (0x400U)
+#define DMA_EEI_EEI10_SHIFT (10U)
+/*! EEI10 - Enable Error Interrupt 10
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
+#define DMA_EEI_EEI11_MASK (0x800U)
+#define DMA_EEI_EEI11_SHIFT (11U)
+/*! EEI11 - Enable Error Interrupt 11
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
+#define DMA_EEI_EEI12_MASK (0x1000U)
+#define DMA_EEI_EEI12_SHIFT (12U)
+/*! EEI12 - Enable Error Interrupt 12
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
+#define DMA_EEI_EEI13_MASK (0x2000U)
+#define DMA_EEI_EEI13_SHIFT (13U)
+/*! EEI13 - Enable Error Interrupt 13
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
+#define DMA_EEI_EEI14_MASK (0x4000U)
+#define DMA_EEI_EEI14_SHIFT (14U)
+/*! EEI14 - Enable Error Interrupt 14
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
+#define DMA_EEI_EEI15_MASK (0x8000U)
+#define DMA_EEI_EEI15_SHIFT (15U)
+/*! EEI15 - Enable Error Interrupt 15
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
+#define DMA_EEI_EEI16_MASK (0x10000U)
+#define DMA_EEI_EEI16_SHIFT (16U)
+/*! EEI16 - Enable Error Interrupt 16
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
+#define DMA_EEI_EEI17_MASK (0x20000U)
+#define DMA_EEI_EEI17_SHIFT (17U)
+/*! EEI17 - Enable Error Interrupt 17
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
+#define DMA_EEI_EEI18_MASK (0x40000U)
+#define DMA_EEI_EEI18_SHIFT (18U)
+/*! EEI18 - Enable Error Interrupt 18
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
+#define DMA_EEI_EEI19_MASK (0x80000U)
+#define DMA_EEI_EEI19_SHIFT (19U)
+/*! EEI19 - Enable Error Interrupt 19
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
+#define DMA_EEI_EEI20_MASK (0x100000U)
+#define DMA_EEI_EEI20_SHIFT (20U)
+/*! EEI20 - Enable Error Interrupt 20
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
+#define DMA_EEI_EEI21_MASK (0x200000U)
+#define DMA_EEI_EEI21_SHIFT (21U)
+/*! EEI21 - Enable Error Interrupt 21
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
+#define DMA_EEI_EEI22_MASK (0x400000U)
+#define DMA_EEI_EEI22_SHIFT (22U)
+/*! EEI22 - Enable Error Interrupt 22
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
+#define DMA_EEI_EEI23_MASK (0x800000U)
+#define DMA_EEI_EEI23_SHIFT (23U)
+/*! EEI23 - Enable Error Interrupt 23
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
+#define DMA_EEI_EEI24_MASK (0x1000000U)
+#define DMA_EEI_EEI24_SHIFT (24U)
+/*! EEI24 - Enable Error Interrupt 24
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
+#define DMA_EEI_EEI25_MASK (0x2000000U)
+#define DMA_EEI_EEI25_SHIFT (25U)
+/*! EEI25 - Enable Error Interrupt 25
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
+#define DMA_EEI_EEI26_MASK (0x4000000U)
+#define DMA_EEI_EEI26_SHIFT (26U)
+/*! EEI26 - Enable Error Interrupt 26
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
+#define DMA_EEI_EEI27_MASK (0x8000000U)
+#define DMA_EEI_EEI27_SHIFT (27U)
+/*! EEI27 - Enable Error Interrupt 27
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
+#define DMA_EEI_EEI28_MASK (0x10000000U)
+#define DMA_EEI_EEI28_SHIFT (28U)
+/*! EEI28 - Enable Error Interrupt 28
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
+#define DMA_EEI_EEI29_MASK (0x20000000U)
+#define DMA_EEI_EEI29_SHIFT (29U)
+/*! EEI29 - Enable Error Interrupt 29
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
+#define DMA_EEI_EEI30_MASK (0x40000000U)
+#define DMA_EEI_EEI30_SHIFT (30U)
+/*! EEI30 - Enable Error Interrupt 30
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
+#define DMA_EEI_EEI31_MASK (0x80000000U)
+#define DMA_EEI_EEI31_SHIFT (31U)
+/*! EEI31 - Enable Error Interrupt 31
+ * 0b0..The error signal for corresponding channel does not generate an error interrupt
+ * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
+/*! @} */
+
+/*! @name CEEI - Clear Enable Error Interrupt Register */
+/*! @{ */
+#define DMA_CEEI_CEEI_MASK (0x1FU)
+#define DMA_CEEI_CEEI_SHIFT (0U)
+#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK (0x40U)
+#define DMA_CEEI_CAEE_SHIFT (6U)
+/*! CAEE - Clear All Enable Error Interrupts
+ * 0b0..Clear only the EEI bit specified in the CEEI field
+ * 0b1..Clear all bits in EEI
+ */
+#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
+#define DMA_CEEI_NOP_MASK (0x80U)
+#define DMA_CEEI_NOP_SHIFT (7U)
+/*! NOP - No Op enable
+ * 0b0..Normal operation
+ * 0b1..No operation, ignore the other bits in this register
+ */
+#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
+/*! @} */
+
+/*! @name SEEI - Set Enable Error Interrupt Register */
+/*! @{ */
+#define DMA_SEEI_SEEI_MASK (0x1FU)
+#define DMA_SEEI_SEEI_SHIFT (0U)
+#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK (0x40U)
+#define DMA_SEEI_SAEE_SHIFT (6U)
+/*! SAEE - Sets All Enable Error Interrupts
+ * 0b0..Set only the EEI bit specified in the SEEI field.
+ * 0b1..Sets all bits in EEI
+ */
+#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
+#define DMA_SEEI_NOP_MASK (0x80U)
+#define DMA_SEEI_NOP_SHIFT (7U)
+/*! NOP - No Op enable
+ * 0b0..Normal operation
+ * 0b1..No operation, ignore the other bits in this register
+ */
+#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
+/*! @} */
+
+/*! @name CERQ - Clear Enable Request Register */
+/*! @{ */
+#define DMA_CERQ_CERQ_MASK (0x1FU)
+#define DMA_CERQ_CERQ_SHIFT (0U)
+#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK (0x40U)
+#define DMA_CERQ_CAER_SHIFT (6U)
+/*! CAER - Clear All Enable Requests
+ * 0b0..Clear only the ERQ bit specified in the CERQ field
+ * 0b1..Clear all bits in ERQ
+ */
+#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
+#define DMA_CERQ_NOP_MASK (0x80U)
+#define DMA_CERQ_NOP_SHIFT (7U)
+/*! NOP - No Op enable
+ * 0b0..Normal operation
+ * 0b1..No operation, ignore the other bits in this register
+ */
+#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
+/*! @} */
+
+/*! @name SERQ - Set Enable Request Register */
+/*! @{ */
+#define DMA_SERQ_SERQ_MASK (0x1FU)
+#define DMA_SERQ_SERQ_SHIFT (0U)
+#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK (0x40U)
+#define DMA_SERQ_SAER_SHIFT (6U)
+/*! SAER - Set All Enable Requests
+ * 0b0..Set only the ERQ bit specified in the SERQ field
+ * 0b1..Set all bits in ERQ
+ */
+#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
+#define DMA_SERQ_NOP_MASK (0x80U)
+#define DMA_SERQ_NOP_SHIFT (7U)
+/*! NOP - No Op enable
+ * 0b0..Normal operation
+ * 0b1..No operation, ignore the other bits in this register
+ */
+#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
+/*! @} */
+
+/*! @name CDNE - Clear DONE Status Bit Register */
+/*! @{ */
+#define DMA_CDNE_CDNE_MASK (0x1FU)
+#define DMA_CDNE_CDNE_SHIFT (0U)
+#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK (0x40U)
+#define DMA_CDNE_CADN_SHIFT (6U)
+/*! CADN - Clears All DONE Bits
+ * 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
+ * 0b1..Clears all bits in TCDn_CSR[DONE]
+ */
+#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
+#define DMA_CDNE_NOP_MASK (0x80U)
+#define DMA_CDNE_NOP_SHIFT (7U)
+/*! NOP - No Op enable
+ * 0b0..Normal operation
+ * 0b1..No operation, ignore the other bits in this register
+ */
+#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
+/*! @} */
+
+/*! @name SSRT - Set START Bit Register */
+/*! @{ */
+#define DMA_SSRT_SSRT_MASK (0x1FU)
+#define DMA_SSRT_SSRT_SHIFT (0U)
+#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK (0x40U)
+#define DMA_SSRT_SAST_SHIFT (6U)
+/*! SAST - Set All START Bits (activates all channels)
+ * 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field
+ * 0b1..Set all bits in TCDn_CSR[START]
+ */
+#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
+#define DMA_SSRT_NOP_MASK (0x80U)
+#define DMA_SSRT_NOP_SHIFT (7U)
+/*! NOP - No Op enable
+ * 0b0..Normal operation
+ * 0b1..No operation, ignore the other bits in this register
+ */
+#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
+/*! @} */
+
+/*! @name CERR - Clear Error Register */
+/*! @{ */
+#define DMA_CERR_CERR_MASK (0x1FU)
+#define DMA_CERR_CERR_SHIFT (0U)
+#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK (0x40U)
+#define DMA_CERR_CAEI_SHIFT (6U)
+/*! CAEI - Clear All Error Indicators
+ * 0b0..Clear only the ERR bit specified in the CERR field
+ * 0b1..Clear all bits in ERR
+ */
+#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
+#define DMA_CERR_NOP_MASK (0x80U)
+#define DMA_CERR_NOP_SHIFT (7U)
+/*! NOP - No Op enable
+ * 0b0..Normal operation
+ * 0b1..No operation, ignore the other bits in this register
+ */
+#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
+/*! @} */
+
+/*! @name CINT - Clear Interrupt Request Register */
+/*! @{ */
+#define DMA_CINT_CINT_MASK (0x1FU)
+#define DMA_CINT_CINT_SHIFT (0U)
+#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK (0x40U)
+#define DMA_CINT_CAIR_SHIFT (6U)
+/*! CAIR - Clear All Interrupt Requests
+ * 0b0..Clear only the INT bit specified in the CINT field
+ * 0b1..Clear all bits in INT
+ */
+#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
+#define DMA_CINT_NOP_MASK (0x80U)
+#define DMA_CINT_NOP_SHIFT (7U)
+/*! NOP - No Op enable
+ * 0b0..Normal operation
+ * 0b1..No operation, ignore the other bits in this register
+ */
+#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
+/*! @} */
+
+/*! @name INT - Interrupt Request Register */
+/*! @{ */
+#define DMA_INT_INT0_MASK (0x1U)
+#define DMA_INT_INT0_SHIFT (0U)
+/*! INT0 - Interrupt Request 0
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
+#define DMA_INT_INT1_MASK (0x2U)
+#define DMA_INT_INT1_SHIFT (1U)
+/*! INT1 - Interrupt Request 1
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
+#define DMA_INT_INT2_MASK (0x4U)
+#define DMA_INT_INT2_SHIFT (2U)
+/*! INT2 - Interrupt Request 2
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
+#define DMA_INT_INT3_MASK (0x8U)
+#define DMA_INT_INT3_SHIFT (3U)
+/*! INT3 - Interrupt Request 3
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
+#define DMA_INT_INT4_MASK (0x10U)
+#define DMA_INT_INT4_SHIFT (4U)
+/*! INT4 - Interrupt Request 4
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
+#define DMA_INT_INT5_MASK (0x20U)
+#define DMA_INT_INT5_SHIFT (5U)
+/*! INT5 - Interrupt Request 5
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
+#define DMA_INT_INT6_MASK (0x40U)
+#define DMA_INT_INT6_SHIFT (6U)
+/*! INT6 - Interrupt Request 6
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
+#define DMA_INT_INT7_MASK (0x80U)
+#define DMA_INT_INT7_SHIFT (7U)
+/*! INT7 - Interrupt Request 7
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
+#define DMA_INT_INT8_MASK (0x100U)
+#define DMA_INT_INT8_SHIFT (8U)
+/*! INT8 - Interrupt Request 8
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
+#define DMA_INT_INT9_MASK (0x200U)
+#define DMA_INT_INT9_SHIFT (9U)
+/*! INT9 - Interrupt Request 9
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
+#define DMA_INT_INT10_MASK (0x400U)
+#define DMA_INT_INT10_SHIFT (10U)
+/*! INT10 - Interrupt Request 10
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
+#define DMA_INT_INT11_MASK (0x800U)
+#define DMA_INT_INT11_SHIFT (11U)
+/*! INT11 - Interrupt Request 11
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
+#define DMA_INT_INT12_MASK (0x1000U)
+#define DMA_INT_INT12_SHIFT (12U)
+/*! INT12 - Interrupt Request 12
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
+#define DMA_INT_INT13_MASK (0x2000U)
+#define DMA_INT_INT13_SHIFT (13U)
+/*! INT13 - Interrupt Request 13
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
+#define DMA_INT_INT14_MASK (0x4000U)
+#define DMA_INT_INT14_SHIFT (14U)
+/*! INT14 - Interrupt Request 14
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
+#define DMA_INT_INT15_MASK (0x8000U)
+#define DMA_INT_INT15_SHIFT (15U)
+/*! INT15 - Interrupt Request 15
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
+#define DMA_INT_INT16_MASK (0x10000U)
+#define DMA_INT_INT16_SHIFT (16U)
+/*! INT16 - Interrupt Request 16
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
+#define DMA_INT_INT17_MASK (0x20000U)
+#define DMA_INT_INT17_SHIFT (17U)
+/*! INT17 - Interrupt Request 17
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
+#define DMA_INT_INT18_MASK (0x40000U)
+#define DMA_INT_INT18_SHIFT (18U)
+/*! INT18 - Interrupt Request 18
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
+#define DMA_INT_INT19_MASK (0x80000U)
+#define DMA_INT_INT19_SHIFT (19U)
+/*! INT19 - Interrupt Request 19
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
+#define DMA_INT_INT20_MASK (0x100000U)
+#define DMA_INT_INT20_SHIFT (20U)
+/*! INT20 - Interrupt Request 20
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
+#define DMA_INT_INT21_MASK (0x200000U)
+#define DMA_INT_INT21_SHIFT (21U)
+/*! INT21 - Interrupt Request 21
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
+#define DMA_INT_INT22_MASK (0x400000U)
+#define DMA_INT_INT22_SHIFT (22U)
+/*! INT22 - Interrupt Request 22
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
+#define DMA_INT_INT23_MASK (0x800000U)
+#define DMA_INT_INT23_SHIFT (23U)
+/*! INT23 - Interrupt Request 23
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
+#define DMA_INT_INT24_MASK (0x1000000U)
+#define DMA_INT_INT24_SHIFT (24U)
+/*! INT24 - Interrupt Request 24
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
+#define DMA_INT_INT25_MASK (0x2000000U)
+#define DMA_INT_INT25_SHIFT (25U)
+/*! INT25 - Interrupt Request 25
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
+#define DMA_INT_INT26_MASK (0x4000000U)
+#define DMA_INT_INT26_SHIFT (26U)
+/*! INT26 - Interrupt Request 26
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
+#define DMA_INT_INT27_MASK (0x8000000U)
+#define DMA_INT_INT27_SHIFT (27U)
+/*! INT27 - Interrupt Request 27
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
+#define DMA_INT_INT28_MASK (0x10000000U)
+#define DMA_INT_INT28_SHIFT (28U)
+/*! INT28 - Interrupt Request 28
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
+#define DMA_INT_INT29_MASK (0x20000000U)
+#define DMA_INT_INT29_SHIFT (29U)
+/*! INT29 - Interrupt Request 29
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
+#define DMA_INT_INT30_MASK (0x40000000U)
+#define DMA_INT_INT30_SHIFT (30U)
+/*! INT30 - Interrupt Request 30
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
+#define DMA_INT_INT31_MASK (0x80000000U)
+#define DMA_INT_INT31_SHIFT (31U)
+/*! INT31 - Interrupt Request 31
+ * 0b0..The interrupt request for corresponding channel is cleared
+ * 0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
+/*! @} */
+
+/*! @name ERR - Error Register */
+/*! @{ */
+#define DMA_ERR_ERR0_MASK (0x1U)
+#define DMA_ERR_ERR0_SHIFT (0U)
+/*! ERR0 - Error In Channel 0
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
+#define DMA_ERR_ERR1_MASK (0x2U)
+#define DMA_ERR_ERR1_SHIFT (1U)
+/*! ERR1 - Error In Channel 1
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
+#define DMA_ERR_ERR2_MASK (0x4U)
+#define DMA_ERR_ERR2_SHIFT (2U)
+/*! ERR2 - Error In Channel 2
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
+#define DMA_ERR_ERR3_MASK (0x8U)
+#define DMA_ERR_ERR3_SHIFT (3U)
+/*! ERR3 - Error In Channel 3
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
+#define DMA_ERR_ERR4_MASK (0x10U)
+#define DMA_ERR_ERR4_SHIFT (4U)
+/*! ERR4 - Error In Channel 4
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
+#define DMA_ERR_ERR5_MASK (0x20U)
+#define DMA_ERR_ERR5_SHIFT (5U)
+/*! ERR5 - Error In Channel 5
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
+#define DMA_ERR_ERR6_MASK (0x40U)
+#define DMA_ERR_ERR6_SHIFT (6U)
+/*! ERR6 - Error In Channel 6
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
+#define DMA_ERR_ERR7_MASK (0x80U)
+#define DMA_ERR_ERR7_SHIFT (7U)
+/*! ERR7 - Error In Channel 7
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
+#define DMA_ERR_ERR8_MASK (0x100U)
+#define DMA_ERR_ERR8_SHIFT (8U)
+/*! ERR8 - Error In Channel 8
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
+#define DMA_ERR_ERR9_MASK (0x200U)
+#define DMA_ERR_ERR9_SHIFT (9U)
+/*! ERR9 - Error In Channel 9
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
+#define DMA_ERR_ERR10_MASK (0x400U)
+#define DMA_ERR_ERR10_SHIFT (10U)
+/*! ERR10 - Error In Channel 10
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
+#define DMA_ERR_ERR11_MASK (0x800U)
+#define DMA_ERR_ERR11_SHIFT (11U)
+/*! ERR11 - Error In Channel 11
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
+#define DMA_ERR_ERR12_MASK (0x1000U)
+#define DMA_ERR_ERR12_SHIFT (12U)
+/*! ERR12 - Error In Channel 12
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
+#define DMA_ERR_ERR13_MASK (0x2000U)
+#define DMA_ERR_ERR13_SHIFT (13U)
+/*! ERR13 - Error In Channel 13
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
+#define DMA_ERR_ERR14_MASK (0x4000U)
+#define DMA_ERR_ERR14_SHIFT (14U)
+/*! ERR14 - Error In Channel 14
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
+#define DMA_ERR_ERR15_MASK (0x8000U)
+#define DMA_ERR_ERR15_SHIFT (15U)
+/*! ERR15 - Error In Channel 15
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
+#define DMA_ERR_ERR16_MASK (0x10000U)
+#define DMA_ERR_ERR16_SHIFT (16U)
+/*! ERR16 - Error In Channel 16
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
+#define DMA_ERR_ERR17_MASK (0x20000U)
+#define DMA_ERR_ERR17_SHIFT (17U)
+/*! ERR17 - Error In Channel 17
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
+#define DMA_ERR_ERR18_MASK (0x40000U)
+#define DMA_ERR_ERR18_SHIFT (18U)
+/*! ERR18 - Error In Channel 18
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
+#define DMA_ERR_ERR19_MASK (0x80000U)
+#define DMA_ERR_ERR19_SHIFT (19U)
+/*! ERR19 - Error In Channel 19
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
+#define DMA_ERR_ERR20_MASK (0x100000U)
+#define DMA_ERR_ERR20_SHIFT (20U)
+/*! ERR20 - Error In Channel 20
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
+#define DMA_ERR_ERR21_MASK (0x200000U)
+#define DMA_ERR_ERR21_SHIFT (21U)
+/*! ERR21 - Error In Channel 21
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
+#define DMA_ERR_ERR22_MASK (0x400000U)
+#define DMA_ERR_ERR22_SHIFT (22U)
+/*! ERR22 - Error In Channel 22
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
+#define DMA_ERR_ERR23_MASK (0x800000U)
+#define DMA_ERR_ERR23_SHIFT (23U)
+/*! ERR23 - Error In Channel 23
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
+#define DMA_ERR_ERR24_MASK (0x1000000U)
+#define DMA_ERR_ERR24_SHIFT (24U)
+/*! ERR24 - Error In Channel 24
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
+#define DMA_ERR_ERR25_MASK (0x2000000U)
+#define DMA_ERR_ERR25_SHIFT (25U)
+/*! ERR25 - Error In Channel 25
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
+#define DMA_ERR_ERR26_MASK (0x4000000U)
+#define DMA_ERR_ERR26_SHIFT (26U)
+/*! ERR26 - Error In Channel 26
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
+#define DMA_ERR_ERR27_MASK (0x8000000U)
+#define DMA_ERR_ERR27_SHIFT (27U)
+/*! ERR27 - Error In Channel 27
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
+#define DMA_ERR_ERR28_MASK (0x10000000U)
+#define DMA_ERR_ERR28_SHIFT (28U)
+/*! ERR28 - Error In Channel 28
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
+#define DMA_ERR_ERR29_MASK (0x20000000U)
+#define DMA_ERR_ERR29_SHIFT (29U)
+/*! ERR29 - Error In Channel 29
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
+#define DMA_ERR_ERR30_MASK (0x40000000U)
+#define DMA_ERR_ERR30_SHIFT (30U)
+/*! ERR30 - Error In Channel 30
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
+#define DMA_ERR_ERR31_MASK (0x80000000U)
+#define DMA_ERR_ERR31_SHIFT (31U)
+/*! ERR31 - Error In Channel 31
+ * 0b0..An error in this channel has not occurred
+ * 0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
+/*! @} */
+
+/*! @name HRS - Hardware Request Status Register */
+/*! @{ */
+#define DMA_HRS_HRS0_MASK (0x1U)
+#define DMA_HRS_HRS0_SHIFT (0U)
+/*! HRS0 - Hardware Request Status Channel 0
+ * 0b0..A hardware service request for channel 0 is not present
+ * 0b1..A hardware service request for channel 0 is present
+ */
+#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
+#define DMA_HRS_HRS1_MASK (0x2U)
+#define DMA_HRS_HRS1_SHIFT (1U)
+/*! HRS1 - Hardware Request Status Channel 1
+ * 0b0..A hardware service request for channel 1 is not present
+ * 0b1..A hardware service request for channel 1 is present
+ */
+#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
+#define DMA_HRS_HRS2_MASK (0x4U)
+#define DMA_HRS_HRS2_SHIFT (2U)
+/*! HRS2 - Hardware Request Status Channel 2
+ * 0b0..A hardware service request for channel 2 is not present
+ * 0b1..A hardware service request for channel 2 is present
+ */
+#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
+#define DMA_HRS_HRS3_MASK (0x8U)
+#define DMA_HRS_HRS3_SHIFT (3U)
+/*! HRS3 - Hardware Request Status Channel 3
+ * 0b0..A hardware service request for channel 3 is not present
+ * 0b1..A hardware service request for channel 3 is present
+ */
+#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
+#define DMA_HRS_HRS4_MASK (0x10U)
+#define DMA_HRS_HRS4_SHIFT (4U)
+/*! HRS4 - Hardware Request Status Channel 4
+ * 0b0..A hardware service request for channel 4 is not present
+ * 0b1..A hardware service request for channel 4 is present
+ */
+#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
+#define DMA_HRS_HRS5_MASK (0x20U)
+#define DMA_HRS_HRS5_SHIFT (5U)
+/*! HRS5 - Hardware Request Status Channel 5
+ * 0b0..A hardware service request for channel 5 is not present
+ * 0b1..A hardware service request for channel 5 is present
+ */
+#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
+#define DMA_HRS_HRS6_MASK (0x40U)
+#define DMA_HRS_HRS6_SHIFT (6U)
+/*! HRS6 - Hardware Request Status Channel 6
+ * 0b0..A hardware service request for channel 6 is not present
+ * 0b1..A hardware service request for channel 6 is present
+ */
+#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
+#define DMA_HRS_HRS7_MASK (0x80U)
+#define DMA_HRS_HRS7_SHIFT (7U)
+/*! HRS7 - Hardware Request Status Channel 7
+ * 0b0..A hardware service request for channel 7 is not present
+ * 0b1..A hardware service request for channel 7 is present
+ */
+#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
+#define DMA_HRS_HRS8_MASK (0x100U)
+#define DMA_HRS_HRS8_SHIFT (8U)
+/*! HRS8 - Hardware Request Status Channel 8
+ * 0b0..A hardware service request for channel 8 is not present
+ * 0b1..A hardware service request for channel 8 is present
+ */
+#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
+#define DMA_HRS_HRS9_MASK (0x200U)
+#define DMA_HRS_HRS9_SHIFT (9U)
+/*! HRS9 - Hardware Request Status Channel 9
+ * 0b0..A hardware service request for channel 9 is not present
+ * 0b1..A hardware service request for channel 9 is present
+ */
+#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
+#define DMA_HRS_HRS10_MASK (0x400U)
+#define DMA_HRS_HRS10_SHIFT (10U)
+/*! HRS10 - Hardware Request Status Channel 10
+ * 0b0..A hardware service request for channel 10 is not present
+ * 0b1..A hardware service request for channel 10 is present
+ */
+#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
+#define DMA_HRS_HRS11_MASK (0x800U)
+#define DMA_HRS_HRS11_SHIFT (11U)
+/*! HRS11 - Hardware Request Status Channel 11
+ * 0b0..A hardware service request for channel 11 is not present
+ * 0b1..A hardware service request for channel 11 is present
+ */
+#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
+#define DMA_HRS_HRS12_MASK (0x1000U)
+#define DMA_HRS_HRS12_SHIFT (12U)
+/*! HRS12 - Hardware Request Status Channel 12
+ * 0b0..A hardware service request for channel 12 is not present
+ * 0b1..A hardware service request for channel 12 is present
+ */
+#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
+#define DMA_HRS_HRS13_MASK (0x2000U)
+#define DMA_HRS_HRS13_SHIFT (13U)
+/*! HRS13 - Hardware Request Status Channel 13
+ * 0b0..A hardware service request for channel 13 is not present
+ * 0b1..A hardware service request for channel 13 is present
+ */
+#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
+#define DMA_HRS_HRS14_MASK (0x4000U)
+#define DMA_HRS_HRS14_SHIFT (14U)
+/*! HRS14 - Hardware Request Status Channel 14
+ * 0b0..A hardware service request for channel 14 is not present
+ * 0b1..A hardware service request for channel 14 is present
+ */
+#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
+#define DMA_HRS_HRS15_MASK (0x8000U)
+#define DMA_HRS_HRS15_SHIFT (15U)
+/*! HRS15 - Hardware Request Status Channel 15
+ * 0b0..A hardware service request for channel 15 is not present
+ * 0b1..A hardware service request for channel 15 is present
+ */
+#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
+#define DMA_HRS_HRS16_MASK (0x10000U)
+#define DMA_HRS_HRS16_SHIFT (16U)
+/*! HRS16 - Hardware Request Status Channel 16
+ * 0b0..A hardware service request for channel 16 is not present
+ * 0b1..A hardware service request for channel 16 is present
+ */
+#define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
+#define DMA_HRS_HRS17_MASK (0x20000U)
+#define DMA_HRS_HRS17_SHIFT (17U)
+/*! HRS17 - Hardware Request Status Channel 17
+ * 0b0..A hardware service request for channel 17 is not present
+ * 0b1..A hardware service request for channel 17 is present
+ */
+#define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
+#define DMA_HRS_HRS18_MASK (0x40000U)
+#define DMA_HRS_HRS18_SHIFT (18U)
+/*! HRS18 - Hardware Request Status Channel 18
+ * 0b0..A hardware service request for channel 18 is not present
+ * 0b1..A hardware service request for channel 18 is present
+ */
+#define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
+#define DMA_HRS_HRS19_MASK (0x80000U)
+#define DMA_HRS_HRS19_SHIFT (19U)
+/*! HRS19 - Hardware Request Status Channel 19
+ * 0b0..A hardware service request for channel 19 is not present
+ * 0b1..A hardware service request for channel 19 is present
+ */
+#define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
+#define DMA_HRS_HRS20_MASK (0x100000U)
+#define DMA_HRS_HRS20_SHIFT (20U)
+/*! HRS20 - Hardware Request Status Channel 20
+ * 0b0..A hardware service request for channel 20 is not present
+ * 0b1..A hardware service request for channel 20 is present
+ */
+#define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
+#define DMA_HRS_HRS21_MASK (0x200000U)
+#define DMA_HRS_HRS21_SHIFT (21U)
+/*! HRS21 - Hardware Request Status Channel 21
+ * 0b0..A hardware service request for channel 21 is not present
+ * 0b1..A hardware service request for channel 21 is present
+ */
+#define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
+#define DMA_HRS_HRS22_MASK (0x400000U)
+#define DMA_HRS_HRS22_SHIFT (22U)
+/*! HRS22 - Hardware Request Status Channel 22
+ * 0b0..A hardware service request for channel 22 is not present
+ * 0b1..A hardware service request for channel 22 is present
+ */
+#define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
+#define DMA_HRS_HRS23_MASK (0x800000U)
+#define DMA_HRS_HRS23_SHIFT (23U)
+/*! HRS23 - Hardware Request Status Channel 23
+ * 0b0..A hardware service request for channel 23 is not present
+ * 0b1..A hardware service request for channel 23 is present
+ */
+#define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
+#define DMA_HRS_HRS24_MASK (0x1000000U)
+#define DMA_HRS_HRS24_SHIFT (24U)
+/*! HRS24 - Hardware Request Status Channel 24
+ * 0b0..A hardware service request for channel 24 is not present
+ * 0b1..A hardware service request for channel 24 is present
+ */
+#define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
+#define DMA_HRS_HRS25_MASK (0x2000000U)
+#define DMA_HRS_HRS25_SHIFT (25U)
+/*! HRS25 - Hardware Request Status Channel 25
+ * 0b0..A hardware service request for channel 25 is not present
+ * 0b1..A hardware service request for channel 25 is present
+ */
+#define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
+#define DMA_HRS_HRS26_MASK (0x4000000U)
+#define DMA_HRS_HRS26_SHIFT (26U)
+/*! HRS26 - Hardware Request Status Channel 26
+ * 0b0..A hardware service request for channel 26 is not present
+ * 0b1..A hardware service request for channel 26 is present
+ */
+#define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
+#define DMA_HRS_HRS27_MASK (0x8000000U)
+#define DMA_HRS_HRS27_SHIFT (27U)
+/*! HRS27 - Hardware Request Status Channel 27
+ * 0b0..A hardware service request for channel 27 is not present
+ * 0b1..A hardware service request for channel 27 is present
+ */
+#define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
+#define DMA_HRS_HRS28_MASK (0x10000000U)
+#define DMA_HRS_HRS28_SHIFT (28U)
+/*! HRS28 - Hardware Request Status Channel 28
+ * 0b0..A hardware service request for channel 28 is not present
+ * 0b1..A hardware service request for channel 28 is present
+ */
+#define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
+#define DMA_HRS_HRS29_MASK (0x20000000U)
+#define DMA_HRS_HRS29_SHIFT (29U)
+/*! HRS29 - Hardware Request Status Channel 29
+ * 0b0..A hardware service request for channel 29 is not preset
+ * 0b1..A hardware service request for channel 29 is present
+ */
+#define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
+#define DMA_HRS_HRS30_MASK (0x40000000U)
+#define DMA_HRS_HRS30_SHIFT (30U)
+/*! HRS30 - Hardware Request Status Channel 30
+ * 0b0..A hardware service request for channel 30 is not present
+ * 0b1..A hardware service request for for channel 30 is present
+ */
+#define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
+#define DMA_HRS_HRS31_MASK (0x80000000U)
+#define DMA_HRS_HRS31_SHIFT (31U)
+/*! HRS31 - Hardware Request Status Channel 31
+ * 0b0..A hardware service request for channel 31 is not present
+ * 0b1..A hardware service request for channel 31 is present
+ */
+#define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
+/*! @} */
+
+/*! @name EARS - Enable Asynchronous Request in Stop Register */
+/*! @{ */
+#define DMA_EARS_EDREQ_0_MASK (0x1U)
+#define DMA_EARS_EDREQ_0_SHIFT (0U)
+/*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0.
+ * 0b0..Disable asynchronous DMA request for channel 0.
+ * 0b1..Enable asynchronous DMA request for channel 0.
+ */
+#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
+#define DMA_EARS_EDREQ_1_MASK (0x2U)
+#define DMA_EARS_EDREQ_1_SHIFT (1U)
+/*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1.
+ * 0b0..Disable asynchronous DMA request for channel 1
+ * 0b1..Enable asynchronous DMA request for channel 1.
+ */
+#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
+#define DMA_EARS_EDREQ_2_MASK (0x4U)
+#define DMA_EARS_EDREQ_2_SHIFT (2U)
+/*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2.
+ * 0b0..Disable asynchronous DMA request for channel 2.
+ * 0b1..Enable asynchronous DMA request for channel 2.
+ */
+#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
+#define DMA_EARS_EDREQ_3_MASK (0x8U)
+#define DMA_EARS_EDREQ_3_SHIFT (3U)
+/*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3.
+ * 0b0..Disable asynchronous DMA request for channel 3.
+ * 0b1..Enable asynchronous DMA request for channel 3.
+ */
+#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
+#define DMA_EARS_EDREQ_4_MASK (0x10U)
+#define DMA_EARS_EDREQ_4_SHIFT (4U)
+/*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4
+ * 0b0..Disable asynchronous DMA request for channel 4.
+ * 0b1..Enable asynchronous DMA request for channel 4.
+ */
+#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
+#define DMA_EARS_EDREQ_5_MASK (0x20U)
+#define DMA_EARS_EDREQ_5_SHIFT (5U)
+/*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5
+ * 0b0..Disable asynchronous DMA request for channel 5.
+ * 0b1..Enable asynchronous DMA request for channel 5.
+ */
+#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
+#define DMA_EARS_EDREQ_6_MASK (0x40U)
+#define DMA_EARS_EDREQ_6_SHIFT (6U)
+/*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6
+ * 0b0..Disable asynchronous DMA request for channel 6.
+ * 0b1..Enable asynchronous DMA request for channel 6.
+ */
+#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
+#define DMA_EARS_EDREQ_7_MASK (0x80U)
+#define DMA_EARS_EDREQ_7_SHIFT (7U)
+/*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7
+ * 0b0..Disable asynchronous DMA request for channel 7.
+ * 0b1..Enable asynchronous DMA request for channel 7.
+ */
+#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
+#define DMA_EARS_EDREQ_8_MASK (0x100U)
+#define DMA_EARS_EDREQ_8_SHIFT (8U)
+/*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8
+ * 0b0..Disable asynchronous DMA request for channel 8.
+ * 0b1..Enable asynchronous DMA request for channel 8.
+ */
+#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
+#define DMA_EARS_EDREQ_9_MASK (0x200U)
+#define DMA_EARS_EDREQ_9_SHIFT (9U)
+/*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9
+ * 0b0..Disable asynchronous DMA request for channel 9.
+ * 0b1..Enable asynchronous DMA request for channel 9.
+ */
+#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
+#define DMA_EARS_EDREQ_10_MASK (0x400U)
+#define DMA_EARS_EDREQ_10_SHIFT (10U)
+/*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10
+ * 0b0..Disable asynchronous DMA request for channel 10.
+ * 0b1..Enable asynchronous DMA request for channel 10.
+ */
+#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
+#define DMA_EARS_EDREQ_11_MASK (0x800U)
+#define DMA_EARS_EDREQ_11_SHIFT (11U)
+/*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11
+ * 0b0..Disable asynchronous DMA request for channel 11.
+ * 0b1..Enable asynchronous DMA request for channel 11.
+ */
+#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
+#define DMA_EARS_EDREQ_12_MASK (0x1000U)
+#define DMA_EARS_EDREQ_12_SHIFT (12U)
+/*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12
+ * 0b0..Disable asynchronous DMA request for channel 12.
+ * 0b1..Enable asynchronous DMA request for channel 12.
+ */
+#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
+#define DMA_EARS_EDREQ_13_MASK (0x2000U)
+#define DMA_EARS_EDREQ_13_SHIFT (13U)
+/*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13
+ * 0b0..Disable asynchronous DMA request for channel 13.
+ * 0b1..Enable asynchronous DMA request for channel 13.
+ */
+#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
+#define DMA_EARS_EDREQ_14_MASK (0x4000U)
+#define DMA_EARS_EDREQ_14_SHIFT (14U)
+/*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14
+ * 0b0..Disable asynchronous DMA request for channel 14.
+ * 0b1..Enable asynchronous DMA request for channel 14.
+ */
+#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
+#define DMA_EARS_EDREQ_15_MASK (0x8000U)
+#define DMA_EARS_EDREQ_15_SHIFT (15U)
+/*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15
+ * 0b0..Disable asynchronous DMA request for channel 15.
+ * 0b1..Enable asynchronous DMA request for channel 15.
+ */
+#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
+#define DMA_EARS_EDREQ_16_MASK (0x10000U)
+#define DMA_EARS_EDREQ_16_SHIFT (16U)
+/*! EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16
+ * 0b0..Disable asynchronous DMA request for channel 16
+ * 0b1..Enable asynchronous DMA request for channel 16
+ */
+#define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
+#define DMA_EARS_EDREQ_17_MASK (0x20000U)
+#define DMA_EARS_EDREQ_17_SHIFT (17U)
+/*! EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17
+ * 0b0..Disable asynchronous DMA request for channel 17
+ * 0b1..Enable asynchronous DMA request for channel 17
+ */
+#define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
+#define DMA_EARS_EDREQ_18_MASK (0x40000U)
+#define DMA_EARS_EDREQ_18_SHIFT (18U)
+/*! EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18
+ * 0b0..Disable asynchronous DMA request for channel 18
+ * 0b1..Enable asynchronous DMA request for channel 18
+ */
+#define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
+#define DMA_EARS_EDREQ_19_MASK (0x80000U)
+#define DMA_EARS_EDREQ_19_SHIFT (19U)
+/*! EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19
+ * 0b0..Disable asynchronous DMA request for channel 19
+ * 0b1..Enable asynchronous DMA request for channel 19
+ */
+#define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
+#define DMA_EARS_EDREQ_20_MASK (0x100000U)
+#define DMA_EARS_EDREQ_20_SHIFT (20U)
+/*! EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20
+ * 0b0..Disable asynchronous DMA request for channel 20
+ * 0b1..Enable asynchronous DMA request for channel 20
+ */
+#define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
+#define DMA_EARS_EDREQ_21_MASK (0x200000U)
+#define DMA_EARS_EDREQ_21_SHIFT (21U)
+/*! EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21
+ * 0b0..Disable asynchronous DMA request for channel 21
+ * 0b1..Enable asynchronous DMA request for channel 21
+ */
+#define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
+#define DMA_EARS_EDREQ_22_MASK (0x400000U)
+#define DMA_EARS_EDREQ_22_SHIFT (22U)
+/*! EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22
+ * 0b0..Disable asynchronous DMA request for channel 22
+ * 0b1..Enable asynchronous DMA request for channel 22
+ */
+#define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
+#define DMA_EARS_EDREQ_23_MASK (0x800000U)
+#define DMA_EARS_EDREQ_23_SHIFT (23U)
+/*! EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23
+ * 0b0..Disable asynchronous DMA request for channel 23
+ * 0b1..Enable asynchronous DMA request for channel 23
+ */
+#define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
+#define DMA_EARS_EDREQ_24_MASK (0x1000000U)
+#define DMA_EARS_EDREQ_24_SHIFT (24U)
+/*! EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24
+ * 0b0..Disable asynchronous DMA request for channel 24
+ * 0b1..Enable asynchronous DMA request for channel 24
+ */
+#define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
+#define DMA_EARS_EDREQ_25_MASK (0x2000000U)
+#define DMA_EARS_EDREQ_25_SHIFT (25U)
+/*! EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25
+ * 0b0..Disable asynchronous DMA request for channel 25
+ * 0b1..Enable asynchronous DMA request for channel 25
+ */
+#define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
+#define DMA_EARS_EDREQ_26_MASK (0x4000000U)
+#define DMA_EARS_EDREQ_26_SHIFT (26U)
+/*! EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26
+ * 0b0..Disable asynchronous DMA request for channel 26
+ * 0b1..Enable asynchronous DMA request for channel 26
+ */
+#define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
+#define DMA_EARS_EDREQ_27_MASK (0x8000000U)
+#define DMA_EARS_EDREQ_27_SHIFT (27U)
+/*! EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27
+ * 0b0..Disable asynchronous DMA request for channel 27
+ * 0b1..Enable asynchronous DMA request for channel 27
+ */
+#define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
+#define DMA_EARS_EDREQ_28_MASK (0x10000000U)
+#define DMA_EARS_EDREQ_28_SHIFT (28U)
+/*! EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28
+ * 0b0..Disable asynchronous DMA request for channel 28
+ * 0b1..Enable asynchronous DMA request for channel 28
+ */
+#define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
+#define DMA_EARS_EDREQ_29_MASK (0x20000000U)
+#define DMA_EARS_EDREQ_29_SHIFT (29U)
+/*! EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29
+ * 0b0..Disable asynchronous DMA request for channel 29
+ * 0b1..Enable asynchronous DMA request for channel 29
+ */
+#define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
+#define DMA_EARS_EDREQ_30_MASK (0x40000000U)
+#define DMA_EARS_EDREQ_30_SHIFT (30U)
+/*! EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30
+ * 0b0..Disable asynchronous DMA request for channel 30
+ * 0b1..Enable asynchronous DMA request for channel 30
+ */
+#define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
+#define DMA_EARS_EDREQ_31_MASK (0x80000000U)
+#define DMA_EARS_EDREQ_31_SHIFT (31U)
+/*! EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31
+ * 0b0..Disable asynchronous DMA request for channel 31
+ * 0b1..Enable asynchronous DMA request for channel 31
+ */
+#define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
+/*! @} */
+
+/*! @name DCHPRI3 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI3_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI3_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI3_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK (0x40U)
+#define DMA_DCHPRI3_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
+#define DMA_DCHPRI3_ECP_MASK (0x80U)
+#define DMA_DCHPRI3_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI2 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI2_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI2_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI2_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK (0x40U)
+#define DMA_DCHPRI2_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
+#define DMA_DCHPRI2_ECP_MASK (0x80U)
+#define DMA_DCHPRI2_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI1 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI1_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI1_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI1_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK (0x40U)
+#define DMA_DCHPRI1_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
+#define DMA_DCHPRI1_ECP_MASK (0x80U)
+#define DMA_DCHPRI1_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI0 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI0_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI0_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI0_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK (0x40U)
+#define DMA_DCHPRI0_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
+#define DMA_DCHPRI0_ECP_MASK (0x80U)
+#define DMA_DCHPRI0_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI7 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI7_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI7_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
+#define DMA_DCHPRI7_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI7_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
+#define DMA_DCHPRI7_DPA_MASK (0x40U)
+#define DMA_DCHPRI7_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
+#define DMA_DCHPRI7_ECP_MASK (0x80U)
+#define DMA_DCHPRI7_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI6 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI6_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI6_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
+#define DMA_DCHPRI6_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI6_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
+#define DMA_DCHPRI6_DPA_MASK (0x40U)
+#define DMA_DCHPRI6_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
+#define DMA_DCHPRI6_ECP_MASK (0x80U)
+#define DMA_DCHPRI6_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI5 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI5_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI5_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
+#define DMA_DCHPRI5_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI5_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
+#define DMA_DCHPRI5_DPA_MASK (0x40U)
+#define DMA_DCHPRI5_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
+#define DMA_DCHPRI5_ECP_MASK (0x80U)
+#define DMA_DCHPRI5_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI4 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI4_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI4_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
+#define DMA_DCHPRI4_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI4_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
+#define DMA_DCHPRI4_DPA_MASK (0x40U)
+#define DMA_DCHPRI4_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
+#define DMA_DCHPRI4_ECP_MASK (0x80U)
+#define DMA_DCHPRI4_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI11 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI11_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI11_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
+#define DMA_DCHPRI11_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI11_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
+#define DMA_DCHPRI11_DPA_MASK (0x40U)
+#define DMA_DCHPRI11_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
+#define DMA_DCHPRI11_ECP_MASK (0x80U)
+#define DMA_DCHPRI11_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI10 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI10_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI10_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
+#define DMA_DCHPRI10_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI10_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
+#define DMA_DCHPRI10_DPA_MASK (0x40U)
+#define DMA_DCHPRI10_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
+#define DMA_DCHPRI10_ECP_MASK (0x80U)
+#define DMA_DCHPRI10_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI9 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI9_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI9_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
+#define DMA_DCHPRI9_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI9_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
+#define DMA_DCHPRI9_DPA_MASK (0x40U)
+#define DMA_DCHPRI9_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
+#define DMA_DCHPRI9_ECP_MASK (0x80U)
+#define DMA_DCHPRI9_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI8 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI8_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI8_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
+#define DMA_DCHPRI8_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI8_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
+#define DMA_DCHPRI8_DPA_MASK (0x40U)
+#define DMA_DCHPRI8_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
+#define DMA_DCHPRI8_ECP_MASK (0x80U)
+#define DMA_DCHPRI8_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI15 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI15_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI15_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
+#define DMA_DCHPRI15_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI15_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
+#define DMA_DCHPRI15_DPA_MASK (0x40U)
+#define DMA_DCHPRI15_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
+#define DMA_DCHPRI15_ECP_MASK (0x80U)
+#define DMA_DCHPRI15_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI14 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI14_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI14_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
+#define DMA_DCHPRI14_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI14_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
+#define DMA_DCHPRI14_DPA_MASK (0x40U)
+#define DMA_DCHPRI14_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
+#define DMA_DCHPRI14_ECP_MASK (0x80U)
+#define DMA_DCHPRI14_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI13 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI13_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI13_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
+#define DMA_DCHPRI13_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI13_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
+#define DMA_DCHPRI13_DPA_MASK (0x40U)
+#define DMA_DCHPRI13_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
+#define DMA_DCHPRI13_ECP_MASK (0x80U)
+#define DMA_DCHPRI13_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI12 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI12_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI12_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
+#define DMA_DCHPRI12_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI12_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
+#define DMA_DCHPRI12_DPA_MASK (0x40U)
+#define DMA_DCHPRI12_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
+#define DMA_DCHPRI12_ECP_MASK (0x80U)
+#define DMA_DCHPRI12_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI19 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI19_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI19_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
+#define DMA_DCHPRI19_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI19_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
+#define DMA_DCHPRI19_DPA_MASK (0x40U)
+#define DMA_DCHPRI19_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
+#define DMA_DCHPRI19_ECP_MASK (0x80U)
+#define DMA_DCHPRI19_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI18 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI18_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI18_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
+#define DMA_DCHPRI18_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI18_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
+#define DMA_DCHPRI18_DPA_MASK (0x40U)
+#define DMA_DCHPRI18_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
+#define DMA_DCHPRI18_ECP_MASK (0x80U)
+#define DMA_DCHPRI18_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI17 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI17_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI17_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
+#define DMA_DCHPRI17_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI17_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
+#define DMA_DCHPRI17_DPA_MASK (0x40U)
+#define DMA_DCHPRI17_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
+#define DMA_DCHPRI17_ECP_MASK (0x80U)
+#define DMA_DCHPRI17_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI16 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI16_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI16_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
+#define DMA_DCHPRI16_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI16_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
+#define DMA_DCHPRI16_DPA_MASK (0x40U)
+#define DMA_DCHPRI16_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
+#define DMA_DCHPRI16_ECP_MASK (0x80U)
+#define DMA_DCHPRI16_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI23 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI23_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI23_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
+#define DMA_DCHPRI23_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI23_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
+#define DMA_DCHPRI23_DPA_MASK (0x40U)
+#define DMA_DCHPRI23_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
+#define DMA_DCHPRI23_ECP_MASK (0x80U)
+#define DMA_DCHPRI23_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI22 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI22_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI22_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
+#define DMA_DCHPRI22_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI22_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
+#define DMA_DCHPRI22_DPA_MASK (0x40U)
+#define DMA_DCHPRI22_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
+#define DMA_DCHPRI22_ECP_MASK (0x80U)
+#define DMA_DCHPRI22_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI21 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI21_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI21_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
+#define DMA_DCHPRI21_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI21_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
+#define DMA_DCHPRI21_DPA_MASK (0x40U)
+#define DMA_DCHPRI21_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
+#define DMA_DCHPRI21_ECP_MASK (0x80U)
+#define DMA_DCHPRI21_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI20 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI20_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI20_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
+#define DMA_DCHPRI20_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI20_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
+#define DMA_DCHPRI20_DPA_MASK (0x40U)
+#define DMA_DCHPRI20_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
+#define DMA_DCHPRI20_ECP_MASK (0x80U)
+#define DMA_DCHPRI20_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI27 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI27_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI27_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
+#define DMA_DCHPRI27_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI27_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
+#define DMA_DCHPRI27_DPA_MASK (0x40U)
+#define DMA_DCHPRI27_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
+#define DMA_DCHPRI27_ECP_MASK (0x80U)
+#define DMA_DCHPRI27_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI26 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI26_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI26_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
+#define DMA_DCHPRI26_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI26_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
+#define DMA_DCHPRI26_DPA_MASK (0x40U)
+#define DMA_DCHPRI26_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
+#define DMA_DCHPRI26_ECP_MASK (0x80U)
+#define DMA_DCHPRI26_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI25 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI25_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI25_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
+#define DMA_DCHPRI25_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI25_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
+#define DMA_DCHPRI25_DPA_MASK (0x40U)
+#define DMA_DCHPRI25_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
+#define DMA_DCHPRI25_ECP_MASK (0x80U)
+#define DMA_DCHPRI25_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI24 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI24_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI24_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
+#define DMA_DCHPRI24_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI24_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
+#define DMA_DCHPRI24_DPA_MASK (0x40U)
+#define DMA_DCHPRI24_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
+#define DMA_DCHPRI24_ECP_MASK (0x80U)
+#define DMA_DCHPRI24_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI31 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI31_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI31_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
+#define DMA_DCHPRI31_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI31_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
+#define DMA_DCHPRI31_DPA_MASK (0x40U)
+#define DMA_DCHPRI31_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
+#define DMA_DCHPRI31_ECP_MASK (0x80U)
+#define DMA_DCHPRI31_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI30 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI30_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI30_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
+#define DMA_DCHPRI30_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI30_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
+#define DMA_DCHPRI30_DPA_MASK (0x40U)
+#define DMA_DCHPRI30_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
+#define DMA_DCHPRI30_ECP_MASK (0x80U)
+#define DMA_DCHPRI30_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI29 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI29_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI29_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
+#define DMA_DCHPRI29_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI29_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
+#define DMA_DCHPRI29_DPA_MASK (0x40U)
+#define DMA_DCHPRI29_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
+#define DMA_DCHPRI29_ECP_MASK (0x80U)
+#define DMA_DCHPRI29_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI28 - Channel n Priority Register */
+/*! @{ */
+#define DMA_DCHPRI28_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI28_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
+#define DMA_DCHPRI28_GRPPRI_MASK (0x30U)
+#define DMA_DCHPRI28_GRPPRI_SHIFT (4U)
+#define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
+#define DMA_DCHPRI28_DPA_MASK (0x40U)
+#define DMA_DCHPRI28_DPA_SHIFT (6U)
+/*! DPA - Disable Preempt Ability.
+ * 0b0..Channel n can suspend a lower priority channel.
+ * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
+#define DMA_DCHPRI28_ECP_MASK (0x80U)
+#define DMA_DCHPRI28_ECP_SHIFT (7U)
+/*! ECP - Enable Channel Preemption.
+ * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
+/*! @} */
+
+/*! @name SADDR - TCD Source Address */
+/*! @{ */
+#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
+#define DMA_SADDR_SADDR_SHIFT (0U)
+#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
+/*! @} */
+
+/* The count of DMA_SADDR */
+#define DMA_SADDR_COUNT (32U)
+
+/*! @name SOFF - TCD Signed Source Address Offset */
+/*! @{ */
+#define DMA_SOFF_SOFF_MASK (0xFFFFU)
+#define DMA_SOFF_SOFF_SHIFT (0U)
+#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
+/*! @} */
+
+/* The count of DMA_SOFF */
+#define DMA_SOFF_COUNT (32U)
+
+/*! @name ATTR - TCD Transfer Attributes */
+/*! @{ */
+#define DMA_ATTR_DSIZE_MASK (0x7U)
+#define DMA_ATTR_DSIZE_SHIFT (0U)
+#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK (0xF8U)
+#define DMA_ATTR_DMOD_SHIFT (3U)
+#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK (0x700U)
+#define DMA_ATTR_SSIZE_SHIFT (8U)
+/*! SSIZE - Source data transfer size
+ * 0b000..8-bit
+ * 0b001..16-bit
+ * 0b010..32-bit
+ * 0b011..Reserved
+ * 0b100..16-byte burst
+ * 0b101..32-byte burst
+ * 0b110..Reserved
+ * 0b111..Reserved
+ */
+#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK (0xF800U)
+#define DMA_ATTR_SMOD_SHIFT (11U)
+/*! SMOD - Source Address Modulo
+ * 0b00000..Source address modulo feature is disabled
+ */
+#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
+/*! @} */
+
+/* The count of DMA_ATTR */
+#define DMA_ATTR_COUNT (32U)
+
+/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
+/*! @{ */
+#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
+#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
+/*! @} */
+
+/* The count of DMA_NBYTES_MLNO */
+#define DMA_NBYTES_MLNO_COUNT (32U)
+
+/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
+/*! @{ */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
+#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
+/*! DMLOE - Destination Minor Loop Offset enable
+ * 0b0..The minor loop offset is not applied to the DADDR
+ * 0b1..The minor loop offset is applied to the DADDR
+ */
+#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
+/*! SMLOE - Source Minor Loop Offset Enable
+ * 0b0..The minor loop offset is not applied to the SADDR
+ * 0b1..The minor loop offset is applied to the SADDR
+ */
+#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
+/*! @} */
+
+/* The count of DMA_NBYTES_MLOFFNO */
+#define DMA_NBYTES_MLOFFNO_COUNT (32U)
+
+/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
+/*! @{ */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
+#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
+#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
+/*! DMLOE - Destination Minor Loop Offset enable
+ * 0b0..The minor loop offset is not applied to the DADDR
+ * 0b1..The minor loop offset is applied to the DADDR
+ */
+#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
+/*! SMLOE - Source Minor Loop Offset Enable
+ * 0b0..The minor loop offset is not applied to the SADDR
+ * 0b1..The minor loop offset is applied to the SADDR
+ */
+#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
+/*! @} */
+
+/* The count of DMA_NBYTES_MLOFFYES */
+#define DMA_NBYTES_MLOFFYES_COUNT (32U)
+
+/*! @name SLAST - TCD Last Source Address Adjustment */
+/*! @{ */
+#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
+#define DMA_SLAST_SLAST_SHIFT (0U)
+#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
+/*! @} */
+
+/* The count of DMA_SLAST */
+#define DMA_SLAST_COUNT (32U)
+
+/*! @name DADDR - TCD Destination Address */
+/*! @{ */
+#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
+#define DMA_DADDR_DADDR_SHIFT (0U)
+#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
+/*! @} */
+
+/* The count of DMA_DADDR */
+#define DMA_DADDR_COUNT (32U)
+
+/*! @name DOFF - TCD Signed Destination Address Offset */
+/*! @{ */
+#define DMA_DOFF_DOFF_MASK (0xFFFFU)
+#define DMA_DOFF_DOFF_SHIFT (0U)
+#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
+/*! @} */
+
+/* The count of DMA_DOFF */
+#define DMA_DOFF_COUNT (32U)
+
+/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
+/*! @{ */
+#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
+#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
+#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
+#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
+/*! ELINK - Enable channel-to-channel linking on minor-loop complete
+ * 0b0..The channel-to-channel linking is disabled
+ * 0b1..The channel-to-channel linking is enabled
+ */
+#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
+/*! @} */
+
+/* The count of DMA_CITER_ELINKNO */
+#define DMA_CITER_ELINKNO_COUNT (32U)
+
+/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
+/*! @{ */
+#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
+#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
+#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
+#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
+#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
+/*! ELINK - Enable channel-to-channel linking on minor-loop complete
+ * 0b0..The channel-to-channel linking is disabled
+ * 0b1..The channel-to-channel linking is enabled
+ */
+#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
+/*! @} */
+
+/* The count of DMA_CITER_ELINKYES */
+#define DMA_CITER_ELINKYES_COUNT (32U)
+
+/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
+/*! @{ */
+#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
+#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
+/*! @} */
+
+/* The count of DMA_DLAST_SGA */
+#define DMA_DLAST_SGA_COUNT (32U)
+
+/*! @name CSR - TCD Control and Status */
+/*! @{ */
+#define DMA_CSR_START_MASK (0x1U)
+#define DMA_CSR_START_SHIFT (0U)
+/*! START - Channel Start
+ * 0b0..The channel is not explicitly started.
+ * 0b1..The channel is explicitly started via a software initiated service request.
+ */
+#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
+#define DMA_CSR_INTMAJOR_MASK (0x2U)
+#define DMA_CSR_INTMAJOR_SHIFT (1U)
+/*! INTMAJOR - Enable an interrupt when major iteration count completes.
+ * 0b0..The end-of-major loop interrupt is disabled.
+ * 0b1..The end-of-major loop interrupt is enabled.
+ */
+#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
+#define DMA_CSR_INTHALF_MASK (0x4U)
+#define DMA_CSR_INTHALF_SHIFT (2U)
+/*! INTHALF - Enable an interrupt when major counter is half complete.
+ * 0b0..The half-point interrupt is disabled.
+ * 0b1..The half-point interrupt is enabled.
+ */
+#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
+#define DMA_CSR_DREQ_MASK (0x8U)
+#define DMA_CSR_DREQ_SHIFT (3U)
+/*! DREQ - Disable Request
+ * 0b0..The channel's ERQ bit is not affected.
+ * 0b1..The channel's ERQ bit is cleared when the major loop is complete.
+ */
+#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
+#define DMA_CSR_ESG_MASK (0x10U)
+#define DMA_CSR_ESG_SHIFT (4U)
+/*! ESG - Enable Scatter/Gather Processing
+ * 0b0..The current channel's TCD is normal format.
+ * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
+ */
+#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
+#define DMA_CSR_MAJORELINK_MASK (0x20U)
+#define DMA_CSR_MAJORELINK_SHIFT (5U)
+/*! MAJORELINK - Enable channel-to-channel linking on major loop complete
+ * 0b0..The channel-to-channel linking is disabled.
+ * 0b1..The channel-to-channel linking is enabled.
+ */
+#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
+#define DMA_CSR_ACTIVE_MASK (0x40U)
+#define DMA_CSR_ACTIVE_SHIFT (6U)
+#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
+#define DMA_CSR_DONE_MASK (0x80U)
+#define DMA_CSR_DONE_SHIFT (7U)
+#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
+#define DMA_CSR_MAJORLINKCH_MASK (0x1F00U)
+#define DMA_CSR_MAJORLINKCH_SHIFT (8U)
+#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK (0xC000U)
+#define DMA_CSR_BWC_SHIFT (14U)
+/*! BWC - Bandwidth Control
+ * 0b00..No eDMA engine stalls
+ * 0b01..Reserved
+ * 0b10..eDMA engine stalls for 4 cycles after each R/W.
+ * 0b11..eDMA engine stalls for 8 cycles after each R/W.
+ */
+#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
+/*! @} */
+
+/* The count of DMA_CSR */
+#define DMA_CSR_COUNT (32U)
+
+/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
+/*! @{ */
+#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
+#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
+#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
+#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
+/*! ELINK - Enables channel-to-channel linking on minor loop complete
+ * 0b0..The channel-to-channel linking is disabled
+ * 0b1..The channel-to-channel linking is enabled
+ */
+#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
+/*! @} */
+
+/* The count of DMA_BITER_ELINKNO */
+#define DMA_BITER_ELINKNO_COUNT (32U)
+
+/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
+/*! @{ */
+#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
+#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
+#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
+#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
+#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
+/*! ELINK - Enables channel-to-channel linking on minor loop complete
+ * 0b0..The channel-to-channel linking is disabled
+ * 0b1..The channel-to-channel linking is enabled
+ */
+#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
+/*! @} */
+
+/* The count of DMA_BITER_ELINKYES */
+#define DMA_BITER_ELINKYES_COUNT (32U)
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0 ((DMA_Type *)DMA_BASE)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS { DMA_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
+#define DMA_ERROR_IRQS { DMA_Error_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CHCFG[32]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/*! @name CHCFG - Channel Configuration register */
+/*! @{ */
+#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
+#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
+/*! SOURCE - DMA Channel Source (Slot)
+ * 0b000000..Disable_Signal
+ * 0b000001..TSI0_Signal
+ * 0b000010..UART0_Rx_Signal
+ * 0b000011..UART0_Tx_Signal
+ * 0b000100..UART1_Rx_Signal
+ * 0b000101..UART1_Tx_Signal
+ * 0b000110..UART2_Rx_Signal
+ * 0b000111..UART2_Tx_Signal
+ * 0b001000..UART3_Rx_Signal
+ * 0b001001..UART3_Tx_Signal
+ * 0b001010..UART4_Signal
+ * 0b001100..I2S0_Rx_Signal
+ * 0b001101..I2S0_Tx_Signal
+ * 0b001110..SPI0_Rx_Signal
+ * 0b001111..SPI0_Tx_Signal
+ * 0b010000..SPI1_Rx_Signal
+ * 0b010001..SPI1_Tx_Signal
+ * 0b010010..I2C0_I2C3_Signal
+ * 0b010011..I2C1_I2C2_Signal
+ * 0b010100..FTM0_Channel0_Signal
+ * 0b010101..FTM0_Channel1_Signal
+ * 0b010110..FTM0_Channel2_Signal
+ * 0b010111..FTM0_Channel3_Signal
+ * 0b011000..FTM0_Channel4_Signal
+ * 0b011001..FTM0_Channel5_Signal
+ * 0b011010..FTM0_Channel6_Signal
+ * 0b011011..FTM0_Channel7_Signal
+ * 0b011100..FTM1_TPM1_Channel0_Signal
+ * 0b011101..FTM1_TPM1_Channel1_Signal
+ * 0b011110..FTM2_TPM2_Channel0_Signal
+ * 0b011111..FTM2_TPM2_Channel1_Signal
+ * 0b100000..FTM3_Channel0_Signal
+ * 0b100001..FTM3_Channel1_Signal
+ * 0b100010..FTM3_Channel2_Signal
+ * 0b100011..FTM3_Channel3_Signal
+ * 0b100100..FTM3_Channel4_Signal
+ * 0b100101..FTM3_Channel5_Signal
+ * 0b100110..FTM3_Channel6_SPI2_Rx_Signal
+ * 0b100111..FTM3_Channel7_SPI2_Tx_Signal
+ * 0b101000..ADC0_Signal
+ * 0b101001..ADC1_Signal
+ * 0b101010..CMP0_Signal
+ * 0b101011..CMP1_Signal
+ * 0b101100..CMP2_CMP3_Signal
+ * 0b101101..DAC0_Signal
+ * 0b101110..DAC1_Signal
+ * 0b101111..CMT_Signal
+ * 0b110000..PDB_Signal
+ * 0b110001..PortA_Signal
+ * 0b110010..PortB_Signal
+ * 0b110011..PortC_Signal
+ * 0b110100..PortD_Signal
+ * 0b110101..PortE_Signal
+ * 0b110111..TPM1_Overflow_Signal
+ * 0b111000..TPM2_Overflow_Signal
+ * 0b111010..LPUART0_Rx_Signal
+ * 0b111011..LPUART0_Tx_Signal
+ * 0b111100..AlwaysOn60_Signal
+ * 0b111101..AlwaysOn61_Signal
+ * 0b111110..AlwaysOn62_Signal
+ * 0b111111..AlwaysOn63_Signal
+ */
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK (0x40U)
+#define DMAMUX_CHCFG_TRIG_SHIFT (6U)
+/*! TRIG - DMA Channel Trigger Enable
+ * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
+ * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
+ */
+#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
+#define DMAMUX_CHCFG_ENBL_MASK (0x80U)
+#define DMAMUX_CHCFG_ENBL_SHIFT (7U)
+/*! ENBL - DMA Channel Enable
+ * 0b0..DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
+ * 0b1..DMA channel is enabled
+ */
+#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
+/*! @} */
+
+/* The count of DMAMUX_CHCFG */
+#define DMAMUX_CHCFG_COUNT (32U)
+
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX base address */
+#define DMAMUX_BASE (0x40021000u)
+/** Peripheral DMAMUX base pointer */
+#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
+/** Array initializer of DMAMUX peripheral base addresses */
+#define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASE_PTRS { DMAMUX }
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- EWM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
+ * @{
+ */
+
+/** EWM - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
+ __O uint8_t SERV; /**< Service Register, offset: 0x1 */
+ __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
+ __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
+} EWM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- EWM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Masks EWM Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control Register */
+/*! @{ */
+#define EWM_CTRL_EWMEN_MASK (0x1U)
+#define EWM_CTRL_EWMEN_SHIFT (0U)
+#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
+#define EWM_CTRL_ASSIN_MASK (0x2U)
+#define EWM_CTRL_ASSIN_SHIFT (1U)
+#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
+#define EWM_CTRL_INEN_MASK (0x4U)
+#define EWM_CTRL_INEN_SHIFT (2U)
+#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
+#define EWM_CTRL_INTEN_MASK (0x8U)
+#define EWM_CTRL_INTEN_SHIFT (3U)
+#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
+/*! @} */
+
+/*! @name SERV - Service Register */
+/*! @{ */
+#define EWM_SERV_SERVICE_MASK (0xFFU)
+#define EWM_SERV_SERVICE_SHIFT (0U)
+#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
+/*! @} */
+
+/*! @name CMPL - Compare Low Register */
+/*! @{ */
+#define EWM_CMPL_COMPAREL_MASK (0xFFU)
+#define EWM_CMPL_COMPAREL_SHIFT (0U)
+#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
+/*! @} */
+
+/*! @name CMPH - Compare High Register */
+/*! @{ */
+#define EWM_CMPH_COMPAREH_MASK (0xFFU)
+#define EWM_CMPH_COMPAREH_SHIFT (0U)
+#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Masks */
+
+
+/* EWM - Peripheral instance base addresses */
+/** Peripheral EWM base address */
+#define EWM_BASE (0x40061000u)
+/** Peripheral EWM base pointer */
+#define EWM ((EWM_Type *)EWM_BASE)
+/** Array initializer of EWM peripheral base addresses */
+#define EWM_BASE_ADDRS { EWM_BASE }
+/** Array initializer of EWM peripheral base pointers */
+#define EWM_BASE_PTRS { EWM }
+/** Interrupt vectors for the EWM peripheral type */
+#define EWM_IRQS { WDOG_EWM_IRQn }
+
+/*!
+ * @}
+ */ /* end of group EWM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
+ * @{
+ */
+
+/** FB - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0xC */
+ __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
+ __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
+ __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
+ } CS[6];
+ uint8_t RESERVED_0[24];
+ __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
+} FB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Masks FB Register Masks
+ * @{
+ */
+
+/*! @name CSAR - Chip Select Address Register */
+/*! @{ */
+#define FB_CSAR_BA_MASK (0xFFFF0000U)
+#define FB_CSAR_BA_SHIFT (16U)
+#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
+/*! @} */
+
+/* The count of FB_CSAR */
+#define FB_CSAR_COUNT (6U)
+
+/*! @name CSMR - Chip Select Mask Register */
+/*! @{ */
+#define FB_CSMR_V_MASK (0x1U)
+#define FB_CSMR_V_SHIFT (0U)
+/*! V - Valid
+ * 0b0..Chip-select is invalid.
+ * 0b1..Chip-select is valid.
+ */
+#define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
+#define FB_CSMR_WP_MASK (0x100U)
+#define FB_CSMR_WP_SHIFT (8U)
+/*! WP - Write Protect
+ * 0b0..Write accesses are allowed.
+ * 0b1..Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle.
+ */
+#define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
+#define FB_CSMR_BAM_MASK (0xFFFF0000U)
+#define FB_CSMR_BAM_SHIFT (16U)
+/*! BAM - Base Address Mask
+ * 0b0000000000000000..The corresponding address bit in CSAR is used in the chip-select decode.
+ * 0b0000000000000001..The corresponding address bit in CSAR is a don't care in the chip-select decode.
+ */
+#define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
+/*! @} */
+
+/* The count of FB_CSMR */
+#define FB_CSMR_COUNT (6U)
+
+/*! @name CSCR - Chip Select Control Register */
+/*! @{ */
+#define FB_CSCR_BSTW_MASK (0x8U)
+#define FB_CSCR_BSTW_SHIFT (3U)
+/*! BSTW - Burst-Write Enable
+ * 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes.
+ * 0b1..Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
+ */
+#define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
+#define FB_CSCR_BSTR_MASK (0x10U)
+#define FB_CSCR_BSTR_SHIFT (4U)
+/*! BSTR - Burst-Read Enable
+ * 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads.
+ * 0b1..Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.
+ */
+#define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
+#define FB_CSCR_BEM_MASK (0x20U)
+#define FB_CSCR_BEM_SHIFT (5U)
+/*! BEM - Byte-Enable Mode
+ * 0b0..FB_BE is asserted for data write only.
+ * 0b1..FB_BE is asserted for data read and write accesses.
+ */
+#define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
+#define FB_CSCR_PS_MASK (0xC0U)
+#define FB_CSCR_PS_SHIFT (6U)
+/*! PS - Port Size
+ * 0b00..32-bit port size. Valid data is sampled and driven on FB_D[31:0].
+ * 0b01..8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b.
+ * 0b1x..16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b.
+ */
+#define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
+#define FB_CSCR_AA_MASK (0x100U)
+#define FB_CSCR_AA_SHIFT (8U)
+/*! AA - Auto-Acknowledge Enable
+ * 0b0..Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally.
+ * 0b1..Enabled. Internal transfer acknowledge is asserted as specified by WS.
+ */
+#define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
+#define FB_CSCR_BLS_MASK (0x200U)
+#define FB_CSCR_BLS_SHIFT (9U)
+/*! BLS - Byte-Lane Shift
+ * 0b0..Not shifted. Data is left-aligned on FB_AD.
+ * 0b1..Shifted. Data is right-aligned on FB_AD.
+ */
+#define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
+#define FB_CSCR_WS_MASK (0xFC00U)
+#define FB_CSCR_WS_SHIFT (10U)
+#define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
+#define FB_CSCR_WRAH_MASK (0x30000U)
+#define FB_CSCR_WRAH_SHIFT (16U)
+/*! WRAH - Write Address Hold or Deselect
+ * 0b00..1 cycle (default for all but FB_CS0 )
+ * 0b01..2 cycles
+ * 0b10..3 cycles
+ * 0b11..4 cycles (default for FB_CS0 )
+ */
+#define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
+#define FB_CSCR_RDAH_MASK (0xC0000U)
+#define FB_CSCR_RDAH_SHIFT (18U)
+/*! RDAH - Read Address Hold or Deselect
+ * 0b00..When AA is 1b, 1 cycle. When AA is 0b, 0 cycles.
+ * 0b01..When AA is 1b, 2 cycles. When AA is 0b, 1 cycle.
+ * 0b10..When AA is 1b, 3 cycles. When AA is 0b, 2 cycles.
+ * 0b11..When AA is 1b, 4 cycles. When AA is 0b, 3 cycles.
+ */
+#define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
+#define FB_CSCR_ASET_MASK (0x300000U)
+#define FB_CSCR_ASET_SHIFT (20U)
+/*! ASET - Address Setup
+ * 0b00..Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but FB_CS0 ).
+ * 0b01..Assert FB_CSn on the second rising clock edge after the address is asserted.
+ * 0b10..Assert FB_CSn on the third rising clock edge after the address is asserted.
+ * 0b11..Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ).
+ */
+#define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
+#define FB_CSCR_EXTS_MASK (0x400000U)
+#define FB_CSCR_EXTS_SHIFT (22U)
+/*! EXTS
+ * 0b0..Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
+ * 0b1..Enabled. FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts.
+ */
+#define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
+#define FB_CSCR_SWSEN_MASK (0x800000U)
+#define FB_CSCR_SWSEN_SHIFT (23U)
+/*! SWSEN - Secondary Wait State Enable
+ * 0b0..Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers.
+ * 0b1..Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations.
+ */
+#define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
+#define FB_CSCR_SWS_MASK (0xFC000000U)
+#define FB_CSCR_SWS_SHIFT (26U)
+#define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
+/*! @} */
+
+/* The count of FB_CSCR */
+#define FB_CSCR_COUNT (6U)
+
+/*! @name CSPMCR - Chip Select port Multiplexing Control Register */
+/*! @{ */
+#define FB_CSPMCR_GROUP5_MASK (0xF000U)
+#define FB_CSPMCR_GROUP5_SHIFT (12U)
+/*! GROUP5 - FlexBus Signal Group 5 Multiplex control
+ * 0b0000..FB_TA
+ * 0b0001..FB_CS3 . You must also write 1b to CSCR[AA].
+ * 0b0010..FB_BE_7_0 . You must also write 1b to CSCR[AA].
+ */
+#define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
+#define FB_CSPMCR_GROUP4_MASK (0xF0000U)
+#define FB_CSPMCR_GROUP4_SHIFT (16U)
+/*! GROUP4 - FlexBus Signal Group 4 Multiplex control
+ * 0b0000..FB_TBST
+ * 0b0001..FB_CS2
+ * 0b0010..FB_BE_15_8
+ */
+#define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
+#define FB_CSPMCR_GROUP3_MASK (0xF00000U)
+#define FB_CSPMCR_GROUP3_SHIFT (20U)
+/*! GROUP3 - FlexBus Signal Group 3 Multiplex control
+ * 0b0000..FB_CS5
+ * 0b0001..FB_TSIZ1
+ * 0b0010..FB_BE_23_16
+ */
+#define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
+#define FB_CSPMCR_GROUP2_MASK (0xF000000U)
+#define FB_CSPMCR_GROUP2_SHIFT (24U)
+/*! GROUP2 - FlexBus Signal Group 2 Multiplex control
+ * 0b0000..FB_CS4
+ * 0b0001..FB_TSIZ0
+ * 0b0010..FB_BE_31_24
+ */
+#define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
+#define FB_CSPMCR_GROUP1_MASK (0xF0000000U)
+#define FB_CSPMCR_GROUP1_SHIFT (28U)
+/*! GROUP1 - FlexBus Signal Group 1 Multiplex control
+ * 0b0000..FB_ALE
+ * 0b0001..FB_CS1
+ * 0b0010..FB_TS
+ */
+#define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Masks */
+
+
+/* FB - Peripheral instance base addresses */
+/** Peripheral FB base address */
+#define FB_BASE (0x4000C000u)
+/** Peripheral FB base pointer */
+#define FB ((FB_Type *)FB_BASE)
+/** Array initializer of FB peripheral base addresses */
+#define FB_BASE_ADDRS { FB_BASE }
+/** Array initializer of FB peripheral base pointers */
+#define FB_BASE_PTRS { FB }
+
+/*!
+ * @}
+ */ /* end of group FB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
+ * @{
+ */
+
+/** FMC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
+ __IO uint32_t PFB01CR; /**< Flash Bank 0-1 Control Register, offset: 0x4 */
+ __IO uint32_t PFB23CR; /**< Flash Bank 2-3 Control Register, offset: 0x8 */
+ uint8_t RESERVED_0[244];
+ __IO uint32_t TAGVDW0S[4]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
+ __IO uint32_t TAGVDW1S[4]; /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
+ __IO uint32_t TAGVDW2S[4]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
+ __IO uint32_t TAGVDW3S[4]; /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
+ uint8_t RESERVED_1[192];
+ struct { /* offset: 0x200, array step: index*0x40, index2*0x10 */
+ __IO uint32_t DATA_UM; /**< Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10 */
+ __IO uint32_t DATA_MU; /**< Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10 */
+ __IO uint32_t DATA_ML; /**< Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 */
+ __IO uint32_t DATA_LM; /**< Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 */
+ } SET[4][4];
+} FMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Masks FMC Register Masks
+ * @{
+ */
+
+/*! @name PFAPR - Flash Access Protection Register */
+/*! @{ */
+#define FMC_PFAPR_M0AP_MASK (0x3U)
+#define FMC_PFAPR_M0AP_SHIFT (0U)
+/*! M0AP - Master 0 Access Protection
+ * 0b00..No access may be performed by this master
+ * 0b01..Only read accesses may be performed by this master
+ * 0b10..Only write accesses may be performed by this master
+ * 0b11..Both read and write accesses may be performed by this master
+ */
+#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M1AP_MASK (0xCU)
+#define FMC_PFAPR_M1AP_SHIFT (2U)
+/*! M1AP - Master 1 Access Protection
+ * 0b00..No access may be performed by this master
+ * 0b01..Only read accesses may be performed by this master
+ * 0b10..Only write accesses may be performed by this master
+ * 0b11..Both read and write accesses may be performed by this master
+ */
+#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M2AP_MASK (0x30U)
+#define FMC_PFAPR_M2AP_SHIFT (4U)
+/*! M2AP - Master 2 Access Protection
+ * 0b00..No access may be performed by this master
+ * 0b01..Only read accesses may be performed by this master
+ * 0b10..Only write accesses may be performed by this master
+ * 0b11..Both read and write accesses may be performed by this master
+ */
+#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M3AP_MASK (0xC0U)
+#define FMC_PFAPR_M3AP_SHIFT (6U)
+/*! M3AP - Master 3 Access Protection
+ * 0b00..No access may be performed by this master
+ * 0b01..Only read accesses may be performed by this master
+ * 0b10..Only write accesses may be performed by this master
+ * 0b11..Both read and write accesses may be performed by this master
+ */
+#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M4AP_MASK (0x300U)
+#define FMC_PFAPR_M4AP_SHIFT (8U)
+/*! M4AP - Master 4 Access Protection
+ * 0b00..No access may be performed by this master
+ * 0b01..Only read accesses may be performed by this master
+ * 0b10..Only write accesses may be performed by this master
+ * 0b11..Both read and write accesses may be performed by this master
+ */
+#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
+#define FMC_PFAPR_M5AP_MASK (0xC00U)
+#define FMC_PFAPR_M5AP_SHIFT (10U)
+/*! M5AP - Master 5 Access Protection
+ * 0b00..No access may be performed by this master
+ * 0b01..Only read accesses may be performed by this master
+ * 0b10..Only write accesses may be performed by this master
+ * 0b11..Both read and write accesses may be performed by this master
+ */
+#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
+#define FMC_PFAPR_M6AP_MASK (0x3000U)
+#define FMC_PFAPR_M6AP_SHIFT (12U)
+/*! M6AP - Master 6 Access Protection
+ * 0b00..No access may be performed by this master
+ * 0b01..Only read accesses may be performed by this master
+ * 0b10..Only write accesses may be performed by this master
+ * 0b11..Both read and write accesses may be performed by this master
+ */
+#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
+#define FMC_PFAPR_M7AP_MASK (0xC000U)
+#define FMC_PFAPR_M7AP_SHIFT (14U)
+/*! M7AP - Master 7 Access Protection
+ * 0b00..No access may be performed by this master.
+ * 0b01..Only read accesses may be performed by this master.
+ * 0b10..Only write accesses may be performed by this master.
+ * 0b11..Both read and write accesses may be performed by this master.
+ */
+#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
+#define FMC_PFAPR_M0PFD_MASK (0x10000U)
+#define FMC_PFAPR_M0PFD_SHIFT (16U)
+/*! M0PFD - Master 0 Prefetch Disable
+ * 0b0..Prefetching for this master is enabled.
+ * 0b1..Prefetching for this master is disabled.
+ */
+#define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
+#define FMC_PFAPR_M1PFD_MASK (0x20000U)
+#define FMC_PFAPR_M1PFD_SHIFT (17U)
+/*! M1PFD - Master 1 Prefetch Disable
+ * 0b0..Prefetching for this master is enabled.
+ * 0b1..Prefetching for this master is disabled.
+ */
+#define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
+#define FMC_PFAPR_M2PFD_MASK (0x40000U)
+#define FMC_PFAPR_M2PFD_SHIFT (18U)
+/*! M2PFD - Master 2 Prefetch Disable
+ * 0b0..Prefetching for this master is enabled.
+ * 0b1..Prefetching for this master is disabled.
+ */
+#define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
+#define FMC_PFAPR_M3PFD_MASK (0x80000U)
+#define FMC_PFAPR_M3PFD_SHIFT (19U)
+/*! M3PFD - Master 3 Prefetch Disable
+ * 0b0..Prefetching for this master is enabled.
+ * 0b1..Prefetching for this master is disabled.
+ */
+#define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
+#define FMC_PFAPR_M4PFD_MASK (0x100000U)
+#define FMC_PFAPR_M4PFD_SHIFT (20U)
+/*! M4PFD - Master 4 Prefetch Disable
+ * 0b0..Prefetching for this master is enabled.
+ * 0b1..Prefetching for this master is disabled.
+ */
+#define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
+#define FMC_PFAPR_M5PFD_MASK (0x200000U)
+#define FMC_PFAPR_M5PFD_SHIFT (21U)
+/*! M5PFD - Master 5 Prefetch Disable
+ * 0b0..Prefetching for this master is enabled.
+ * 0b1..Prefetching for this master is disabled.
+ */
+#define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
+#define FMC_PFAPR_M6PFD_MASK (0x400000U)
+#define FMC_PFAPR_M6PFD_SHIFT (22U)
+/*! M6PFD - Master 6 Prefetch Disable
+ * 0b0..Prefetching for this master is enabled.
+ * 0b1..Prefetching for this master is disabled.
+ */
+#define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
+#define FMC_PFAPR_M7PFD_MASK (0x800000U)
+#define FMC_PFAPR_M7PFD_SHIFT (23U)
+/*! M7PFD - Master 7 Prefetch Disable
+ * 0b0..Prefetching for this master is enabled.
+ * 0b1..Prefetching for this master is disabled.
+ */
+#define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)
+/*! @} */
+
+/*! @name PFB01CR - Flash Bank 0-1 Control Register */
+/*! @{ */
+#define FMC_PFB01CR_RFU_MASK (0x1U)
+#define FMC_PFB01CR_RFU_SHIFT (0U)
+#define FMC_PFB01CR_RFU(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_RFU_SHIFT)) & FMC_PFB01CR_RFU_MASK)
+#define FMC_PFB01CR_B0IPE_MASK (0x2U)
+#define FMC_PFB01CR_B0IPE_SHIFT (1U)
+/*! B0IPE - Bank 0 Instruction Prefetch Enable
+ * 0b0..Do not prefetch in response to instruction fetches.
+ * 0b1..Enable prefetches in response to instruction fetches.
+ */
+#define FMC_PFB01CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0IPE_SHIFT)) & FMC_PFB01CR_B0IPE_MASK)
+#define FMC_PFB01CR_B0DPE_MASK (0x4U)
+#define FMC_PFB01CR_B0DPE_SHIFT (2U)
+/*! B0DPE - Bank 0 Data Prefetch Enable
+ * 0b0..Do not prefetch in response to data references.
+ * 0b1..Enable prefetches in response to data references.
+ */
+#define FMC_PFB01CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0DPE_SHIFT)) & FMC_PFB01CR_B0DPE_MASK)
+#define FMC_PFB01CR_B0ICE_MASK (0x8U)
+#define FMC_PFB01CR_B0ICE_SHIFT (3U)
+/*! B0ICE - Bank 0 Instruction Cache Enable
+ * 0b0..Do not cache instruction fetches.
+ * 0b1..Cache instruction fetches.
+ */
+#define FMC_PFB01CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0ICE_SHIFT)) & FMC_PFB01CR_B0ICE_MASK)
+#define FMC_PFB01CR_B0DCE_MASK (0x10U)
+#define FMC_PFB01CR_B0DCE_SHIFT (4U)
+/*! B0DCE - Bank 0 Data Cache Enable
+ * 0b0..Do not cache data references.
+ * 0b1..Cache data references.
+ */
+#define FMC_PFB01CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0DCE_SHIFT)) & FMC_PFB01CR_B0DCE_MASK)
+#define FMC_PFB01CR_CRC_MASK (0xE0U)
+#define FMC_PFB01CR_CRC_SHIFT (5U)
+/*! CRC - Cache Replacement Control
+ * 0b000..LRU replacement algorithm per set across all four ways
+ * 0b001..Reserved
+ * 0b010..Independent LRU with ways [0-1] for ifetches, [2-3] for data
+ * 0b011..Independent LRU with ways [0-2] for ifetches, [3] for data
+ * 0b1xx..Reserved
+ */
+#define FMC_PFB01CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CRC_SHIFT)) & FMC_PFB01CR_CRC_MASK)
+#define FMC_PFB01CR_B0MW_MASK (0x60000U)
+#define FMC_PFB01CR_B0MW_SHIFT (17U)
+/*! B0MW - Bank 0 Memory Width
+ * 0b00..32 bits
+ * 0b01..64 bits
+ * 0b10..128 bits
+ * 0b11..Reserved
+ */
+#define FMC_PFB01CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0MW_SHIFT)) & FMC_PFB01CR_B0MW_MASK)
+#define FMC_PFB01CR_S_B_INV_MASK (0x80000U)
+#define FMC_PFB01CR_S_B_INV_SHIFT (19U)
+/*! S_B_INV - Invalidate Prefetch Speculation Buffer
+ * 0b0..Speculation buffer is not affected
+ * 0b1..Invalidate (clear) speculation buffer
+ */
+#define FMC_PFB01CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_S_B_INV_SHIFT)) & FMC_PFB01CR_S_B_INV_MASK)
+#define FMC_PFB01CR_CINV_WAY_MASK (0xF00000U)
+#define FMC_PFB01CR_CINV_WAY_SHIFT (20U)
+/*! CINV_WAY - Cache Invalidate Way x
+ * 0b0000..No cache way invalidation for the corresponding cache
+ * 0b0001..Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected
+ */
+#define FMC_PFB01CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CINV_WAY_SHIFT)) & FMC_PFB01CR_CINV_WAY_MASK)
+#define FMC_PFB01CR_CLCK_WAY_MASK (0xF000000U)
+#define FMC_PFB01CR_CLCK_WAY_SHIFT (24U)
+/*! CLCK_WAY - Cache Lock Way x
+ * 0b0000..Cache way is unlocked and may be displaced
+ * 0b0001..Cache way is locked and its contents are not displaced
+ */
+#define FMC_PFB01CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CLCK_WAY_SHIFT)) & FMC_PFB01CR_CLCK_WAY_MASK)
+#define FMC_PFB01CR_B0RWSC_MASK (0xF0000000U)
+#define FMC_PFB01CR_B0RWSC_SHIFT (28U)
+#define FMC_PFB01CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0RWSC_SHIFT)) & FMC_PFB01CR_B0RWSC_MASK)
+/*! @} */
+
+/*! @name PFB23CR - Flash Bank 2-3 Control Register */
+/*! @{ */
+#define FMC_PFB23CR_RFU_MASK (0x1U)
+#define FMC_PFB23CR_RFU_SHIFT (0U)
+#define FMC_PFB23CR_RFU(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_RFU_SHIFT)) & FMC_PFB23CR_RFU_MASK)
+#define FMC_PFB23CR_B1IPE_MASK (0x2U)
+#define FMC_PFB23CR_B1IPE_SHIFT (1U)
+/*! B1IPE - Bank 1 Instruction Prefetch Enable
+ * 0b0..Do not prefetch in response to instruction fetches.
+ * 0b1..Enable prefetches in response to instruction fetches.
+ */
+#define FMC_PFB23CR_B1IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1IPE_SHIFT)) & FMC_PFB23CR_B1IPE_MASK)
+#define FMC_PFB23CR_B1DPE_MASK (0x4U)
+#define FMC_PFB23CR_B1DPE_SHIFT (2U)
+/*! B1DPE - Bank 1 Data Prefetch Enable
+ * 0b0..Do not prefetch in response to data references.
+ * 0b1..Enable prefetches in response to data references.
+ */
+#define FMC_PFB23CR_B1DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1DPE_SHIFT)) & FMC_PFB23CR_B1DPE_MASK)
+#define FMC_PFB23CR_B1ICE_MASK (0x8U)
+#define FMC_PFB23CR_B1ICE_SHIFT (3U)
+/*! B1ICE - Bank 1 Instruction Cache Enable
+ * 0b0..Do not cache instruction fetches.
+ * 0b1..Cache instruction fetches.
+ */
+#define FMC_PFB23CR_B1ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1ICE_SHIFT)) & FMC_PFB23CR_B1ICE_MASK)
+#define FMC_PFB23CR_B1DCE_MASK (0x10U)
+#define FMC_PFB23CR_B1DCE_SHIFT (4U)
+/*! B1DCE - Bank 1 Data Cache Enable
+ * 0b0..Do not cache data references.
+ * 0b1..Cache data references.
+ */
+#define FMC_PFB23CR_B1DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1DCE_SHIFT)) & FMC_PFB23CR_B1DCE_MASK)
+#define FMC_PFB23CR_B1MW_MASK (0x60000U)
+#define FMC_PFB23CR_B1MW_SHIFT (17U)
+/*! B1MW - Bank 1 Memory Width
+ * 0b00..32 bits
+ * 0b01..64 bits
+ * 0b10..128 bits
+ * 0b11..Reserved
+ */
+#define FMC_PFB23CR_B1MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1MW_SHIFT)) & FMC_PFB23CR_B1MW_MASK)
+#define FMC_PFB23CR_B1RWSC_MASK (0xF0000000U)
+#define FMC_PFB23CR_B1RWSC_SHIFT (28U)
+#define FMC_PFB23CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1RWSC_SHIFT)) & FMC_PFB23CR_B1RWSC_MASK)
+/*! @} */
+
+/*! @name TAGVDW0S - Cache Tag Storage */
+/*! @{ */
+#define FMC_TAGVDW0S_valid_MASK (0x1U)
+#define FMC_TAGVDW0S_valid_SHIFT (0U)
+#define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK)
+#define FMC_TAGVDW0S_tag_MASK (0x3FFFC0U)
+#define FMC_TAGVDW0S_tag_SHIFT (6U)
+#define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK)
+/*! @} */
+
+/* The count of FMC_TAGVDW0S */
+#define FMC_TAGVDW0S_COUNT (4U)
+
+/*! @name TAGVDW1S - Cache Tag Storage */
+/*! @{ */
+#define FMC_TAGVDW1S_valid_MASK (0x1U)
+#define FMC_TAGVDW1S_valid_SHIFT (0U)
+#define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK)
+#define FMC_TAGVDW1S_tag_MASK (0x3FFFC0U)
+#define FMC_TAGVDW1S_tag_SHIFT (6U)
+#define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK)
+/*! @} */
+
+/* The count of FMC_TAGVDW1S */
+#define FMC_TAGVDW1S_COUNT (4U)
+
+/*! @name TAGVDW2S - Cache Tag Storage */
+/*! @{ */
+#define FMC_TAGVDW2S_valid_MASK (0x1U)
+#define FMC_TAGVDW2S_valid_SHIFT (0U)
+#define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK)
+#define FMC_TAGVDW2S_tag_MASK (0x3FFFC0U)
+#define FMC_TAGVDW2S_tag_SHIFT (6U)
+#define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK)
+/*! @} */
+
+/* The count of FMC_TAGVDW2S */
+#define FMC_TAGVDW2S_COUNT (4U)
+
+/*! @name TAGVDW3S - Cache Tag Storage */
+/*! @{ */
+#define FMC_TAGVDW3S_valid_MASK (0x1U)
+#define FMC_TAGVDW3S_valid_SHIFT (0U)
+#define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK)
+#define FMC_TAGVDW3S_tag_MASK (0x3FFFC0U)
+#define FMC_TAGVDW3S_tag_SHIFT (6U)
+#define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK)
+/*! @} */
+
+/* The count of FMC_TAGVDW3S */
+#define FMC_TAGVDW3S_COUNT (4U)
+
+/*! @name DATA_UM - Cache Data Storage (uppermost word) */
+/*! @{ */
+#define FMC_DATA_UM_data_MASK (0xFFFFFFFFU)
+#define FMC_DATA_UM_data_SHIFT (0U)
+#define FMC_DATA_UM_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_UM_data_SHIFT)) & FMC_DATA_UM_data_MASK)
+/*! @} */
+
+/* The count of FMC_DATA_UM */
+#define FMC_DATA_UM_COUNT (4U)
+
+/* The count of FMC_DATA_UM */
+#define FMC_DATA_UM_COUNT2 (4U)
+
+/*! @name DATA_MU - Cache Data Storage (mid-upper word) */
+/*! @{ */
+#define FMC_DATA_MU_data_MASK (0xFFFFFFFFU)
+#define FMC_DATA_MU_data_SHIFT (0U)
+#define FMC_DATA_MU_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_MU_data_SHIFT)) & FMC_DATA_MU_data_MASK)
+/*! @} */
+
+/* The count of FMC_DATA_MU */
+#define FMC_DATA_MU_COUNT (4U)
+
+/* The count of FMC_DATA_MU */
+#define FMC_DATA_MU_COUNT2 (4U)
+
+/*! @name DATA_ML - Cache Data Storage (mid-lower word) */
+/*! @{ */
+#define FMC_DATA_ML_data_MASK (0xFFFFFFFFU)
+#define FMC_DATA_ML_data_SHIFT (0U)
+#define FMC_DATA_ML_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_ML_data_SHIFT)) & FMC_DATA_ML_data_MASK)
+/*! @} */
+
+/* The count of FMC_DATA_ML */
+#define FMC_DATA_ML_COUNT (4U)
+
+/* The count of FMC_DATA_ML */
+#define FMC_DATA_ML_COUNT2 (4U)
+
+/*! @name DATA_LM - Cache Data Storage (lowermost word) */
+/*! @{ */
+#define FMC_DATA_LM_data_MASK (0xFFFFFFFFU)
+#define FMC_DATA_LM_data_SHIFT (0U)
+#define FMC_DATA_LM_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_LM_data_SHIFT)) & FMC_DATA_LM_data_MASK)
+/*! @} */
+
+/* The count of FMC_DATA_LM */
+#define FMC_DATA_LM_COUNT (4U)
+
+/* The count of FMC_DATA_LM */
+#define FMC_DATA_LM_COUNT2 (4U)
+
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Masks */
+
+
+/* FMC - Peripheral instance base addresses */
+/** Peripheral FMC base address */
+#define FMC_BASE (0x4001F000u)
+/** Peripheral FMC base pointer */
+#define FMC ((FMC_Type *)FMC_BASE)
+/** Array initializer of FMC peripheral base addresses */
+#define FMC_BASE_ADDRS { FMC_BASE }
+/** Array initializer of FMC peripheral base pointers */
+#define FMC_BASE_PTRS { FMC }
+
+/*!
+ * @}
+ */ /* end of group FMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFE Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
+ * @{
+ */
+
+/** FTFE - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
+ __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
+ __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
+ __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
+ __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
+ __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
+ __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
+ __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
+ __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
+ __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
+ __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
+ __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
+ __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
+ __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
+ __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
+ __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
+ __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
+ __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
+ __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
+ __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
+ __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
+ __I uint8_t XACCH3; /**< Execute-only Access Registers, offset: 0x18 */
+ __I uint8_t XACCH2; /**< Execute-only Access Registers, offset: 0x19 */
+ __I uint8_t XACCH1; /**< Execute-only Access Registers, offset: 0x1A */
+ __I uint8_t XACCH0; /**< Execute-only Access Registers, offset: 0x1B */
+ __I uint8_t XACCL3; /**< Execute-only Access Registers, offset: 0x1C */
+ __I uint8_t XACCL2; /**< Execute-only Access Registers, offset: 0x1D */
+ __I uint8_t XACCL1; /**< Execute-only Access Registers, offset: 0x1E */
+ __I uint8_t XACCL0; /**< Execute-only Access Registers, offset: 0x1F */
+ __I uint8_t SACCH3; /**< Supervisor-only Access Registers, offset: 0x20 */
+ __I uint8_t SACCH2; /**< Supervisor-only Access Registers, offset: 0x21 */
+ __I uint8_t SACCH1; /**< Supervisor-only Access Registers, offset: 0x22 */
+ __I uint8_t SACCH0; /**< Supervisor-only Access Registers, offset: 0x23 */
+ __I uint8_t SACCL3; /**< Supervisor-only Access Registers, offset: 0x24 */
+ __I uint8_t SACCL2; /**< Supervisor-only Access Registers, offset: 0x25 */
+ __I uint8_t SACCL1; /**< Supervisor-only Access Registers, offset: 0x26 */
+ __I uint8_t SACCL0; /**< Supervisor-only Access Registers, offset: 0x27 */
+ __I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */
+ uint8_t RESERVED_1[2];
+ __I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */
+} FTFE_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FTFE Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Masks FTFE Register Masks
+ * @{
+ */
+
+/*! @name FSTAT - Flash Status Register */
+/*! @{ */
+#define FTFE_FSTAT_MGSTAT0_MASK (0x1U)
+#define FTFE_FSTAT_MGSTAT0_SHIFT (0U)
+#define FTFE_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK)
+#define FTFE_FSTAT_FPVIOL_MASK (0x10U)
+#define FTFE_FSTAT_FPVIOL_SHIFT (4U)
+/*! FPVIOL - Flash Protection Violation Flag
+ * 0b0..No protection violation detected
+ * 0b1..Protection violation detected
+ */
+#define FTFE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)
+#define FTFE_FSTAT_ACCERR_MASK (0x20U)
+#define FTFE_FSTAT_ACCERR_SHIFT (5U)
+/*! ACCERR - Flash Access Error Flag
+ * 0b0..No access error detected
+ * 0b1..Access error detected
+ */
+#define FTFE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)
+#define FTFE_FSTAT_RDCOLERR_MASK (0x40U)
+#define FTFE_FSTAT_RDCOLERR_SHIFT (6U)
+/*! RDCOLERR - FTFE Read Collision Error Flag
+ * 0b0..No collision error detected
+ * 0b1..Collision error detected
+ */
+#define FTFE_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)
+#define FTFE_FSTAT_CCIF_MASK (0x80U)
+#define FTFE_FSTAT_CCIF_SHIFT (7U)
+/*! CCIF - Command Complete Interrupt Flag
+ * 0b0..FTFE command or EEPROM file system operation in progress
+ * 0b1..FTFE command or EEPROM file system operation has completed
+ */
+#define FTFE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)
+/*! @} */
+
+/*! @name FCNFG - Flash Configuration Register */
+/*! @{ */
+#define FTFE_FCNFG_EEERDY_MASK (0x1U)
+#define FTFE_FCNFG_EEERDY_SHIFT (0U)
+/*! EEERDY
+ * 0b0..For devices with FlexNVM: FlexRAM is not available for EEPROM operation For devices without FlexNVM: See RAMRDY for availability of programming acceleration RAM
+ * 0b1..For devices with FlexNVM: FlexRAM is available for EEPROM operations where: reads from the FlexRAM return data previously written to the FlexRAM in EEPROM mode and writes launch an EEPROM operation to store the written data in the FlexRAM and EEPROM backup For devices without FlexNVM: Reserved
+ */
+#define FTFE_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK)
+#define FTFE_FCNFG_RAMRDY_MASK (0x2U)
+#define FTFE_FCNFG_RAMRDY_SHIFT (1U)
+/*! RAMRDY - RAM Ready
+ * 0b0..For devices with FlexNVM: FlexRAM is not available for traditional RAM access For devices without FlexNVM: Programming acceleration RAM is not available
+ * 0b1..For devices with FlexNVM: FlexRAM is available as traditional RAM only; writes to the FlexRAM do not trigger EEPROM operations For devices without FlexNVM: Programming acceleration RAM is available
+ */
+#define FTFE_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)
+#define FTFE_FCNFG_PFLSH_MASK (0x4U)
+#define FTFE_FCNFG_PFLSH_SHIFT (2U)
+/*! PFLSH - FTFE configuration
+ * 0b0..For devices with FlexNVM: FTFE configuration supports two or three program flash blocks and two FlexNVM blocks For devices with program flash only: Reserved
+ * 0b1..For devices with FlexNVM: Reserved For devices with program flash only: FTFE configuration supports four program flash blocks
+ */
+#define FTFE_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK)
+#define FTFE_FCNFG_SWAP_MASK (0x8U)
+#define FTFE_FCNFG_SWAP_SHIFT (3U)
+/*! SWAP - Swap
+ * 0b0..For devices with FlexNVM: Program flash 0 block is located at relative address 0x0000 For devices with program flash only: Program flash 0/1 blocks are located at relative address 0x0000
+ * 0b1..For devices with FlexNVM: Reserved For devices with program flash only: Program flash 2/3 blocks are located at relative address 0x0000
+ */
+#define FTFE_FCNFG_SWAP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK)
+#define FTFE_FCNFG_ERSSUSP_MASK (0x10U)
+#define FTFE_FCNFG_ERSSUSP_SHIFT (4U)
+/*! ERSSUSP - Erase Suspend
+ * 0b0..No suspend requested
+ * 0b1..Suspend the current Erase Flash Sector command execution
+ */
+#define FTFE_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK)
+#define FTFE_FCNFG_ERSAREQ_MASK (0x20U)
+#define FTFE_FCNFG_ERSAREQ_SHIFT (5U)
+/*! ERSAREQ - Erase All Request
+ * 0b0..No request or request complete
+ * 0b1..Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state
+ */
+#define FTFE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK)
+#define FTFE_FCNFG_RDCOLLIE_MASK (0x40U)
+#define FTFE_FCNFG_RDCOLLIE_SHIFT (6U)
+/*! RDCOLLIE - Read Collision Error Interrupt Enable
+ * 0b0..Read collision error interrupt disabled
+ * 0b1..Read collision error interrupt enabled. An interrupt request is generated whenever an FTFE read collision error is detected (see the description of FSTAT[RDCOLERR]).
+ */
+#define FTFE_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK)
+#define FTFE_FCNFG_CCIE_MASK (0x80U)
+#define FTFE_FCNFG_CCIE_SHIFT (7U)
+/*! CCIE - Command Complete Interrupt Enable
+ * 0b0..Command complete interrupt disabled
+ * 0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.
+ */
+#define FTFE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK)
+/*! @} */
+
+/*! @name FSEC - Flash Security Register */
+/*! @{ */
+#define FTFE_FSEC_SEC_MASK (0x3U)
+#define FTFE_FSEC_SEC_SHIFT (0U)
+/*! SEC - Flash Security
+ * 0b00..MCU security status is secure
+ * 0b01..MCU security status is secure
+ * 0b10..MCU security status is unsecure (The standard shipping condition of the FTFE is unsecure.)
+ * 0b11..MCU security status is secure
+ */
+#define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)
+#define FTFE_FSEC_FSLACC_MASK (0xCU)
+#define FTFE_FSEC_FSLACC_SHIFT (2U)
+/*! FSLACC - Freescale Failure Analysis Access Code
+ * 0b00..Freescale factory access granted
+ * 0b01..Freescale factory access denied
+ * 0b10..Freescale factory access denied
+ * 0b11..Freescale factory access granted
+ */
+#define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)
+#define FTFE_FSEC_MEEN_MASK (0x30U)
+#define FTFE_FSEC_MEEN_SHIFT (4U)
+/*! MEEN - Mass Erase Enable Bits
+ * 0b00..Mass erase is enabled
+ * 0b01..Mass erase is enabled
+ * 0b10..Mass erase is disabled
+ * 0b11..Mass erase is enabled
+ */
+#define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)
+#define FTFE_FSEC_KEYEN_MASK (0xC0U)
+#define FTFE_FSEC_KEYEN_SHIFT (6U)
+/*! KEYEN - Backdoor Key Security Enable
+ * 0b00..Backdoor key access disabled
+ * 0b01..Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
+ * 0b10..Backdoor key access enabled
+ * 0b11..Backdoor key access disabled
+ */
+#define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)
+/*! @} */
+
+/*! @name FOPT - Flash Option Register */
+/*! @{ */
+#define FTFE_FOPT_OPT_MASK (0xFFU)
+#define FTFE_FOPT_OPT_SHIFT (0U)
+#define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT_OPT_SHIFT)) & FTFE_FOPT_OPT_MASK)
+/*! @} */
+
+/*! @name FCCOB3 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB3_CCOBn_MASK (0xFFU)
+#define FTFE_FCCOB3_CCOBn_SHIFT (0U)
+#define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB2 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB2_CCOBn_MASK (0xFFU)
+#define FTFE_FCCOB2_CCOBn_SHIFT (0U)
+#define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB1 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB1_CCOBn_MASK (0xFFU)
+#define FTFE_FCCOB1_CCOBn_SHIFT (0U)
+#define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB0 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB0_CCOBn_MASK (0xFFU)
+#define FTFE_FCCOB0_CCOBn_SHIFT (0U)
+#define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB7 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB7_CCOBn_MASK (0xFFU)
+#define FTFE_FCCOB7_CCOBn_SHIFT (0U)
+#define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB6 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB6_CCOBn_MASK (0xFFU)
+#define FTFE_FCCOB6_CCOBn_SHIFT (0U)
+#define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB5 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB5_CCOBn_MASK (0xFFU)
+#define FTFE_FCCOB5_CCOBn_SHIFT (0U)
+#define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB4 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB4_CCOBn_MASK (0xFFU)
+#define FTFE_FCCOB4_CCOBn_SHIFT (0U)
+#define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOBB - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOBB_CCOBn_MASK (0xFFU)
+#define FTFE_FCCOBB_CCOBn_SHIFT (0U)
+#define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOBA - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOBA_CCOBn_MASK (0xFFU)
+#define FTFE_FCCOBA_CCOBn_SHIFT (0U)
+#define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB9 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB9_CCOBn_MASK (0xFFU)
+#define FTFE_FCCOB9_CCOBn_SHIFT (0U)
+#define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB8 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB8_CCOBn_MASK (0xFFU)
+#define FTFE_FCCOB8_CCOBn_SHIFT (0U)
+#define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK)
+/*! @} */
+
+/*! @name FPROT3 - Program Flash Protection Registers */
+/*! @{ */
+#define FTFE_FPROT3_PROT_MASK (0xFFU)
+#define FTFE_FPROT3_PROT_SHIFT (0U)
+/*! PROT - Program Flash Region Protect
+ * 0b00000000..Program flash region is protected.
+ * 0b00000001..Program flash region is not protected
+ */
+#define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK)
+/*! @} */
+
+/*! @name FPROT2 - Program Flash Protection Registers */
+/*! @{ */
+#define FTFE_FPROT2_PROT_MASK (0xFFU)
+#define FTFE_FPROT2_PROT_SHIFT (0U)
+/*! PROT - Program Flash Region Protect
+ * 0b00000000..Program flash region is protected.
+ * 0b00000001..Program flash region is not protected
+ */
+#define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK)
+/*! @} */
+
+/*! @name FPROT1 - Program Flash Protection Registers */
+/*! @{ */
+#define FTFE_FPROT1_PROT_MASK (0xFFU)
+#define FTFE_FPROT1_PROT_SHIFT (0U)
+/*! PROT - Program Flash Region Protect
+ * 0b00000000..Program flash region is protected.
+ * 0b00000001..Program flash region is not protected
+ */
+#define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK)
+/*! @} */
+
+/*! @name FPROT0 - Program Flash Protection Registers */
+/*! @{ */
+#define FTFE_FPROT0_PROT_MASK (0xFFU)
+#define FTFE_FPROT0_PROT_SHIFT (0U)
+/*! PROT - Program Flash Region Protect
+ * 0b00000000..Program flash region is protected.
+ * 0b00000001..Program flash region is not protected
+ */
+#define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK)
+/*! @} */
+
+/*! @name FEPROT - EEPROM Protection Register */
+/*! @{ */
+#define FTFE_FEPROT_EPROT_MASK (0xFFU)
+#define FTFE_FEPROT_EPROT_SHIFT (0U)
+/*! EPROT - EEPROM Region Protect
+ * 0b00000000..For devices with program flash only: Reserved For devices with FlexNVM: EEPROM region is protected
+ * 0b00000001..For devices with program flash only: Reserved For devices with FlexNVM: EEPROM region is not protected
+ */
+#define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FEPROT_EPROT_SHIFT)) & FTFE_FEPROT_EPROT_MASK)
+/*! @} */
+
+/*! @name FDPROT - Data Flash Protection Register */
+/*! @{ */
+#define FTFE_FDPROT_DPROT_MASK (0xFFU)
+#define FTFE_FDPROT_DPROT_SHIFT (0U)
+/*! DPROT - Data Flash Region Protect
+ * 0b00000000..Data Flash region is protected
+ * 0b00000001..Data Flash region is not protected
+ */
+#define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FDPROT_DPROT_SHIFT)) & FTFE_FDPROT_DPROT_MASK)
+/*! @} */
+
+/*! @name XACCH3 - Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCH3_XA_MASK (0xFFU)
+#define FTFE_XACCH3_XA_SHIFT (0U)
+/*! XA - Execute-only access control
+ * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
+ * 0b00000001..Associated segment is accessible as data or in execute mode
+ */
+#define FTFE_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH3_XA_SHIFT)) & FTFE_XACCH3_XA_MASK)
+/*! @} */
+
+/*! @name XACCH2 - Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCH2_XA_MASK (0xFFU)
+#define FTFE_XACCH2_XA_SHIFT (0U)
+/*! XA - Execute-only access control
+ * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
+ * 0b00000001..Associated segment is accessible as data or in execute mode
+ */
+#define FTFE_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH2_XA_SHIFT)) & FTFE_XACCH2_XA_MASK)
+/*! @} */
+
+/*! @name XACCH1 - Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCH1_XA_MASK (0xFFU)
+#define FTFE_XACCH1_XA_SHIFT (0U)
+/*! XA - Execute-only access control
+ * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
+ * 0b00000001..Associated segment is accessible as data or in execute mode
+ */
+#define FTFE_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH1_XA_SHIFT)) & FTFE_XACCH1_XA_MASK)
+/*! @} */
+
+/*! @name XACCH0 - Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCH0_XA_MASK (0xFFU)
+#define FTFE_XACCH0_XA_SHIFT (0U)
+/*! XA - Execute-only access control
+ * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
+ * 0b00000001..Associated segment is accessible as data or in execute mode
+ */
+#define FTFE_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH0_XA_SHIFT)) & FTFE_XACCH0_XA_MASK)
+/*! @} */
+
+/*! @name XACCL3 - Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCL3_XA_MASK (0xFFU)
+#define FTFE_XACCL3_XA_SHIFT (0U)
+/*! XA - Execute-only access control
+ * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
+ * 0b00000001..Associated segment is accessible as data or in execute mode
+ */
+#define FTFE_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL3_XA_SHIFT)) & FTFE_XACCL3_XA_MASK)
+/*! @} */
+
+/*! @name XACCL2 - Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCL2_XA_MASK (0xFFU)
+#define FTFE_XACCL2_XA_SHIFT (0U)
+/*! XA - Execute-only access control
+ * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
+ * 0b00000001..Associated segment is accessible as data or in execute mode
+ */
+#define FTFE_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL2_XA_SHIFT)) & FTFE_XACCL2_XA_MASK)
+/*! @} */
+
+/*! @name XACCL1 - Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCL1_XA_MASK (0xFFU)
+#define FTFE_XACCL1_XA_SHIFT (0U)
+/*! XA - Execute-only access control
+ * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
+ * 0b00000001..Associated segment is accessible as data or in execute mode
+ */
+#define FTFE_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL1_XA_SHIFT)) & FTFE_XACCL1_XA_MASK)
+/*! @} */
+
+/*! @name XACCL0 - Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCL0_XA_MASK (0xFFU)
+#define FTFE_XACCL0_XA_SHIFT (0U)
+/*! XA - Execute-only access control
+ * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
+ * 0b00000001..Associated segment is accessible as data or in execute mode
+ */
+#define FTFE_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL0_XA_SHIFT)) & FTFE_XACCL0_XA_MASK)
+/*! @} */
+
+/*! @name SACCH3 - Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCH3_SA_MASK (0xFFU)
+#define FTFE_SACCH3_SA_SHIFT (0U)
+/*! SA - Supervisor-only access control
+ * 0b00000000..Associated segment is accessible in supervisor mode only
+ * 0b00000001..Associated segment is accessible in user or supervisor mode
+ */
+#define FTFE_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH3_SA_SHIFT)) & FTFE_SACCH3_SA_MASK)
+/*! @} */
+
+/*! @name SACCH2 - Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCH2_SA_MASK (0xFFU)
+#define FTFE_SACCH2_SA_SHIFT (0U)
+/*! SA - Supervisor-only access control
+ * 0b00000000..Associated segment is accessible in supervisor mode only
+ * 0b00000001..Associated segment is accessible in user or supervisor mode
+ */
+#define FTFE_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH2_SA_SHIFT)) & FTFE_SACCH2_SA_MASK)
+/*! @} */
+
+/*! @name SACCH1 - Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCH1_SA_MASK (0xFFU)
+#define FTFE_SACCH1_SA_SHIFT (0U)
+/*! SA - Supervisor-only access control
+ * 0b00000000..Associated segment is accessible in supervisor mode only
+ * 0b00000001..Associated segment is accessible in user or supervisor mode
+ */
+#define FTFE_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH1_SA_SHIFT)) & FTFE_SACCH1_SA_MASK)
+/*! @} */
+
+/*! @name SACCH0 - Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCH0_SA_MASK (0xFFU)
+#define FTFE_SACCH0_SA_SHIFT (0U)
+/*! SA - Supervisor-only access control
+ * 0b00000000..Associated segment is accessible in supervisor mode only
+ * 0b00000001..Associated segment is accessible in user or supervisor mode
+ */
+#define FTFE_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH0_SA_SHIFT)) & FTFE_SACCH0_SA_MASK)
+/*! @} */
+
+/*! @name SACCL3 - Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCL3_SA_MASK (0xFFU)
+#define FTFE_SACCL3_SA_SHIFT (0U)
+/*! SA - Supervisor-only access control
+ * 0b00000000..Associated segment is accessible in supervisor mode only
+ * 0b00000001..Associated segment is accessible in user or supervisor mode
+ */
+#define FTFE_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL3_SA_SHIFT)) & FTFE_SACCL3_SA_MASK)
+/*! @} */
+
+/*! @name SACCL2 - Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCL2_SA_MASK (0xFFU)
+#define FTFE_SACCL2_SA_SHIFT (0U)
+/*! SA - Supervisor-only access control
+ * 0b00000000..Associated segment is accessible in supervisor mode only
+ * 0b00000001..Associated segment is accessible in user or supervisor mode
+ */
+#define FTFE_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL2_SA_SHIFT)) & FTFE_SACCL2_SA_MASK)
+/*! @} */
+
+/*! @name SACCL1 - Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCL1_SA_MASK (0xFFU)
+#define FTFE_SACCL1_SA_SHIFT (0U)
+/*! SA - Supervisor-only access control
+ * 0b00000000..Associated segment is accessible in supervisor mode only
+ * 0b00000001..Associated segment is accessible in user or supervisor mode
+ */
+#define FTFE_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL1_SA_SHIFT)) & FTFE_SACCL1_SA_MASK)
+/*! @} */
+
+/*! @name SACCL0 - Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCL0_SA_MASK (0xFFU)
+#define FTFE_SACCL0_SA_SHIFT (0U)
+/*! SA - Supervisor-only access control
+ * 0b00000000..Associated segment is accessible in supervisor mode only
+ * 0b00000001..Associated segment is accessible in user or supervisor mode
+ */
+#define FTFE_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL0_SA_SHIFT)) & FTFE_SACCL0_SA_MASK)
+/*! @} */
+
+/*! @name FACSS - Flash Access Segment Size Register */
+/*! @{ */
+#define FTFE_FACSS_SGSIZE_MASK (0xFFU)
+#define FTFE_FACSS_SGSIZE_SHIFT (0U)
+#define FTFE_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSS_SGSIZE_SHIFT)) & FTFE_FACSS_SGSIZE_MASK)
+/*! @} */
+
+/*! @name FACSN - Flash Access Segment Number Register */
+/*! @{ */
+#define FTFE_FACSN_NUMSG_MASK (0xFFU)
+#define FTFE_FACSN_NUMSG_SHIFT (0U)
+/*! NUMSG - Number of Segments Indicator
+ * 0b00110000..Program flash memory is divided into 48 segments (768 Kbytes, 1.5 Mbytes)
+ * 0b01000000..Program flash memory is divided into 64 segments (512 Kbytes, 1 Mbyte, 2 Mbytes)
+ */
+#define FTFE_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSN_NUMSG_SHIFT)) & FTFE_FACSN_NUMSG_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Masks */
+
+
+/* FTFE - Peripheral instance base addresses */
+/** Peripheral FTFE base address */
+#define FTFE_BASE (0x40020000u)
+/** Peripheral FTFE base pointer */
+#define FTFE ((FTFE_Type *)FTFE_BASE)
+/** Array initializer of FTFE peripheral base addresses */
+#define FTFE_BASE_ADDRS { FTFE_BASE }
+/** Array initializer of FTFE peripheral base pointers */
+#define FTFE_BASE_PTRS { FTFE }
+/** Interrupt vectors for the FTFE peripheral type */
+#define FTFE_COMMAND_COMPLETE_IRQS { FTFE_IRQn }
+#define FTFE_READ_COLLISION_IRQS { Read_Collision_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FTFE_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
+ * @{
+ */
+
+/** FTM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
+ __IO uint32_t CNT; /**< Counter, offset: 0x4 */
+ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
+ struct { /* offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+ } CONTROLS[8];
+ __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
+ __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
+ __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
+ __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
+ __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
+ __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
+ __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
+ __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
+ __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
+ __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
+ __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
+ __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
+ __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
+ __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
+ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
+ __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
+ __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
+ __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
+ __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
+ __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
+} FTM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FTM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Masks FTM Register Masks
+ * @{
+ */
+
+/*! @name SC - Status And Control */
+/*! @{ */
+#define FTM_SC_PS_MASK (0x7U)
+#define FTM_SC_PS_SHIFT (0U)
+/*! PS - Prescale Factor Selection
+ * 0b000..Divide by 1
+ * 0b001..Divide by 2
+ * 0b010..Divide by 4
+ * 0b011..Divide by 8
+ * 0b100..Divide by 16
+ * 0b101..Divide by 32
+ * 0b110..Divide by 64
+ * 0b111..Divide by 128
+ */
+#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
+#define FTM_SC_CLKS_MASK (0x18U)
+#define FTM_SC_CLKS_SHIFT (3U)
+/*! CLKS - Clock Source Selection
+ * 0b00..No clock selected. This in effect disables the FTM counter.
+ * 0b01..System clock
+ * 0b10..Fixed frequency clock
+ * 0b11..External clock
+ */
+#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
+#define FTM_SC_CPWMS_MASK (0x20U)
+#define FTM_SC_CPWMS_SHIFT (5U)
+/*! CPWMS - Center-Aligned PWM Select
+ * 0b0..FTM counter operates in Up Counting mode.
+ * 0b1..FTM counter operates in Up-Down Counting mode.
+ */
+#define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
+#define FTM_SC_TOIE_MASK (0x40U)
+#define FTM_SC_TOIE_SHIFT (6U)
+/*! TOIE - Timer Overflow Interrupt Enable
+ * 0b0..Disable TOF interrupts. Use software polling.
+ * 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.
+ */
+#define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
+#define FTM_SC_TOF_MASK (0x80U)
+#define FTM_SC_TOF_SHIFT (7U)
+/*! TOF - Timer Overflow Flag
+ * 0b0..FTM counter has not overflowed.
+ * 0b1..FTM counter has overflowed.
+ */
+#define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
+/*! @} */
+
+/*! @name CNT - Counter */
+/*! @{ */
+#define FTM_CNT_COUNT_MASK (0xFFFFU)
+#define FTM_CNT_COUNT_SHIFT (0U)
+#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
+/*! @} */
+
+/*! @name MOD - Modulo */
+/*! @{ */
+#define FTM_MOD_MOD_MASK (0xFFFFU)
+#define FTM_MOD_MOD_SHIFT (0U)
+#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
+/*! @} */
+
+/*! @name CnSC - Channel (n) Status And Control */
+/*! @{ */
+#define FTM_CnSC_DMA_MASK (0x1U)
+#define FTM_CnSC_DMA_SHIFT (0U)
+/*! DMA - DMA Enable
+ * 0b0..Disable DMA transfers.
+ * 0b1..Enable DMA transfers.
+ */
+#define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
+#define FTM_CnSC_ELSA_MASK (0x4U)
+#define FTM_CnSC_ELSA_SHIFT (2U)
+#define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
+#define FTM_CnSC_ELSB_MASK (0x8U)
+#define FTM_CnSC_ELSB_SHIFT (3U)
+#define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
+#define FTM_CnSC_MSA_MASK (0x10U)
+#define FTM_CnSC_MSA_SHIFT (4U)
+#define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
+#define FTM_CnSC_MSB_MASK (0x20U)
+#define FTM_CnSC_MSB_SHIFT (5U)
+#define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
+#define FTM_CnSC_CHIE_MASK (0x40U)
+#define FTM_CnSC_CHIE_SHIFT (6U)
+/*! CHIE - Channel Interrupt Enable
+ * 0b0..Disable channel interrupts. Use software polling.
+ * 0b1..Enable channel interrupts.
+ */
+#define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
+#define FTM_CnSC_CHF_MASK (0x80U)
+#define FTM_CnSC_CHF_SHIFT (7U)
+/*! CHF - Channel Flag
+ * 0b0..No channel event has occurred.
+ * 0b1..A channel event has occurred.
+ */
+#define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
+/*! @} */
+
+/* The count of FTM_CnSC */
+#define FTM_CnSC_COUNT (8U)
+
+/*! @name CnV - Channel (n) Value */
+/*! @{ */
+#define FTM_CnV_VAL_MASK (0xFFFFU)
+#define FTM_CnV_VAL_SHIFT (0U)
+#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
+/*! @} */
+
+/* The count of FTM_CnV */
+#define FTM_CnV_COUNT (8U)
+
+/*! @name CNTIN - Counter Initial Value */
+/*! @{ */
+#define FTM_CNTIN_INIT_MASK (0xFFFFU)
+#define FTM_CNTIN_INIT_SHIFT (0U)
+#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
+/*! @} */
+
+/*! @name STATUS - Capture And Compare Status */
+/*! @{ */
+#define FTM_STATUS_CH0F_MASK (0x1U)
+#define FTM_STATUS_CH0F_SHIFT (0U)
+/*! CH0F - Channel 0 Flag
+ * 0b0..No channel event has occurred.
+ * 0b1..A channel event has occurred.
+ */
+#define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
+#define FTM_STATUS_CH1F_MASK (0x2U)
+#define FTM_STATUS_CH1F_SHIFT (1U)
+/*! CH1F - Channel 1 Flag
+ * 0b0..No channel event has occurred.
+ * 0b1..A channel event has occurred.
+ */
+#define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
+#define FTM_STATUS_CH2F_MASK (0x4U)
+#define FTM_STATUS_CH2F_SHIFT (2U)
+/*! CH2F - Channel 2 Flag
+ * 0b0..No channel event has occurred.
+ * 0b1..A channel event has occurred.
+ */
+#define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
+#define FTM_STATUS_CH3F_MASK (0x8U)
+#define FTM_STATUS_CH3F_SHIFT (3U)
+/*! CH3F - Channel 3 Flag
+ * 0b0..No channel event has occurred.
+ * 0b1..A channel event has occurred.
+ */
+#define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
+#define FTM_STATUS_CH4F_MASK (0x10U)
+#define FTM_STATUS_CH4F_SHIFT (4U)
+/*! CH4F - Channel 4 Flag
+ * 0b0..No channel event has occurred.
+ * 0b1..A channel event has occurred.
+ */
+#define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
+#define FTM_STATUS_CH5F_MASK (0x20U)
+#define FTM_STATUS_CH5F_SHIFT (5U)
+/*! CH5F - Channel 5 Flag
+ * 0b0..No channel event has occurred.
+ * 0b1..A channel event has occurred.
+ */
+#define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
+#define FTM_STATUS_CH6F_MASK (0x40U)
+#define FTM_STATUS_CH6F_SHIFT (6U)
+/*! CH6F - Channel 6 Flag
+ * 0b0..No channel event has occurred.
+ * 0b1..A channel event has occurred.
+ */
+#define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
+#define FTM_STATUS_CH7F_MASK (0x80U)
+#define FTM_STATUS_CH7F_SHIFT (7U)
+/*! CH7F - Channel 7 Flag
+ * 0b0..No channel event has occurred.
+ * 0b1..A channel event has occurred.
+ */
+#define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
+/*! @} */
+
+/*! @name MODE - Features Mode Selection */
+/*! @{ */
+#define FTM_MODE_FTMEN_MASK (0x1U)
+#define FTM_MODE_FTMEN_SHIFT (0U)
+/*! FTMEN - FTM Enable
+ * 0b0..TPM compatibility. Free running counter and synchronization compatible with TPM.
+ * 0b1..Free running counter and synchronization are different from TPM behavior.
+ */
+#define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
+#define FTM_MODE_INIT_MASK (0x2U)
+#define FTM_MODE_INIT_SHIFT (1U)
+#define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
+#define FTM_MODE_WPDIS_MASK (0x4U)
+#define FTM_MODE_WPDIS_SHIFT (2U)
+/*! WPDIS - Write Protection Disable
+ * 0b0..Write protection is enabled.
+ * 0b1..Write protection is disabled.
+ */
+#define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
+#define FTM_MODE_PWMSYNC_MASK (0x8U)
+#define FTM_MODE_PWMSYNC_SHIFT (3U)
+/*! PWMSYNC - PWM Synchronization Mode
+ * 0b0..No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.
+ * 0b1..Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.
+ */
+#define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
+#define FTM_MODE_CAPTEST_MASK (0x10U)
+#define FTM_MODE_CAPTEST_SHIFT (4U)
+/*! CAPTEST - Capture Test Mode Enable
+ * 0b0..Capture test mode is disabled.
+ * 0b1..Capture test mode is enabled.
+ */
+#define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
+#define FTM_MODE_FAULTM_MASK (0x60U)
+#define FTM_MODE_FAULTM_SHIFT (5U)
+/*! FAULTM - Fault Control Mode
+ * 0b00..Fault control is disabled for all channels.
+ * 0b01..Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.
+ * 0b10..Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
+ * 0b11..Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
+ */
+#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTIE_MASK (0x80U)
+#define FTM_MODE_FAULTIE_SHIFT (7U)
+/*! FAULTIE - Fault Interrupt Enable
+ * 0b0..Fault control interrupt is disabled.
+ * 0b1..Fault control interrupt is enabled.
+ */
+#define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
+/*! @} */
+
+/*! @name SYNC - Synchronization */
+/*! @{ */
+#define FTM_SYNC_CNTMIN_MASK (0x1U)
+#define FTM_SYNC_CNTMIN_SHIFT (0U)
+/*! CNTMIN - Minimum Loading Point Enable
+ * 0b0..The minimum loading point is disabled.
+ * 0b1..The minimum loading point is enabled.
+ */
+#define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
+#define FTM_SYNC_CNTMAX_MASK (0x2U)
+#define FTM_SYNC_CNTMAX_SHIFT (1U)
+/*! CNTMAX - Maximum Loading Point Enable
+ * 0b0..The maximum loading point is disabled.
+ * 0b1..The maximum loading point is enabled.
+ */
+#define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
+#define FTM_SYNC_REINIT_MASK (0x4U)
+#define FTM_SYNC_REINIT_SHIFT (2U)
+/*! REINIT - FTM Counter Reinitialization By Synchronization (FTM counter synchronization)
+ * 0b0..FTM counter continues to count normally.
+ * 0b1..FTM counter is updated with its initial value when the selected trigger is detected.
+ */
+#define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
+#define FTM_SYNC_SYNCHOM_MASK (0x8U)
+#define FTM_SYNC_SYNCHOM_SHIFT (3U)
+/*! SYNCHOM - Output Mask Synchronization
+ * 0b0..OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.
+ * 0b1..OUTMASK register is updated with the value of its buffer only by the PWM synchronization.
+ */
+#define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
+#define FTM_SYNC_TRIG0_MASK (0x10U)
+#define FTM_SYNC_TRIG0_SHIFT (4U)
+/*! TRIG0 - PWM Synchronization Hardware Trigger 0
+ * 0b0..Trigger is disabled.
+ * 0b1..Trigger is enabled.
+ */
+#define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
+#define FTM_SYNC_TRIG1_MASK (0x20U)
+#define FTM_SYNC_TRIG1_SHIFT (5U)
+/*! TRIG1 - PWM Synchronization Hardware Trigger 1
+ * 0b0..Trigger is disabled.
+ * 0b1..Trigger is enabled.
+ */
+#define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
+#define FTM_SYNC_TRIG2_MASK (0x40U)
+#define FTM_SYNC_TRIG2_SHIFT (6U)
+/*! TRIG2 - PWM Synchronization Hardware Trigger 2
+ * 0b0..Trigger is disabled.
+ * 0b1..Trigger is enabled.
+ */
+#define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
+#define FTM_SYNC_SWSYNC_MASK (0x80U)
+#define FTM_SYNC_SWSYNC_SHIFT (7U)
+/*! SWSYNC - PWM Synchronization Software Trigger
+ * 0b0..Software trigger is not selected.
+ * 0b1..Software trigger is selected.
+ */
+#define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
+/*! @} */
+
+/*! @name OUTINIT - Initial State For Channels Output */
+/*! @{ */
+#define FTM_OUTINIT_CH0OI_MASK (0x1U)
+#define FTM_OUTINIT_CH0OI_SHIFT (0U)
+/*! CH0OI - Channel 0 Output Initialization Value
+ * 0b0..The initialization value is 0.
+ * 0b1..The initialization value is 1.
+ */
+#define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
+#define FTM_OUTINIT_CH1OI_MASK (0x2U)
+#define FTM_OUTINIT_CH1OI_SHIFT (1U)
+/*! CH1OI - Channel 1 Output Initialization Value
+ * 0b0..The initialization value is 0.
+ * 0b1..The initialization value is 1.
+ */
+#define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
+#define FTM_OUTINIT_CH2OI_MASK (0x4U)
+#define FTM_OUTINIT_CH2OI_SHIFT (2U)
+/*! CH2OI - Channel 2 Output Initialization Value
+ * 0b0..The initialization value is 0.
+ * 0b1..The initialization value is 1.
+ */
+#define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
+#define FTM_OUTINIT_CH3OI_MASK (0x8U)
+#define FTM_OUTINIT_CH3OI_SHIFT (3U)
+/*! CH3OI - Channel 3 Output Initialization Value
+ * 0b0..The initialization value is 0.
+ * 0b1..The initialization value is 1.
+ */
+#define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
+#define FTM_OUTINIT_CH4OI_MASK (0x10U)
+#define FTM_OUTINIT_CH4OI_SHIFT (4U)
+/*! CH4OI - Channel 4 Output Initialization Value
+ * 0b0..The initialization value is 0.
+ * 0b1..The initialization value is 1.
+ */
+#define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
+#define FTM_OUTINIT_CH5OI_MASK (0x20U)
+#define FTM_OUTINIT_CH5OI_SHIFT (5U)
+/*! CH5OI - Channel 5 Output Initialization Value
+ * 0b0..The initialization value is 0.
+ * 0b1..The initialization value is 1.
+ */
+#define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
+#define FTM_OUTINIT_CH6OI_MASK (0x40U)
+#define FTM_OUTINIT_CH6OI_SHIFT (6U)
+/*! CH6OI - Channel 6 Output Initialization Value
+ * 0b0..The initialization value is 0.
+ * 0b1..The initialization value is 1.
+ */
+#define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
+#define FTM_OUTINIT_CH7OI_MASK (0x80U)
+#define FTM_OUTINIT_CH7OI_SHIFT (7U)
+/*! CH7OI - Channel 7 Output Initialization Value
+ * 0b0..The initialization value is 0.
+ * 0b1..The initialization value is 1.
+ */
+#define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
+/*! @} */
+
+/*! @name OUTMASK - Output Mask */
+/*! @{ */
+#define FTM_OUTMASK_CH0OM_MASK (0x1U)
+#define FTM_OUTMASK_CH0OM_SHIFT (0U)
+/*! CH0OM - Channel 0 Output Mask
+ * 0b0..Channel output is not masked. It continues to operate normally.
+ * 0b1..Channel output is masked. It is forced to its inactive state.
+ */
+#define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
+#define FTM_OUTMASK_CH1OM_MASK (0x2U)
+#define FTM_OUTMASK_CH1OM_SHIFT (1U)
+/*! CH1OM - Channel 1 Output Mask
+ * 0b0..Channel output is not masked. It continues to operate normally.
+ * 0b1..Channel output is masked. It is forced to its inactive state.
+ */
+#define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
+#define FTM_OUTMASK_CH2OM_MASK (0x4U)
+#define FTM_OUTMASK_CH2OM_SHIFT (2U)
+/*! CH2OM - Channel 2 Output Mask
+ * 0b0..Channel output is not masked. It continues to operate normally.
+ * 0b1..Channel output is masked. It is forced to its inactive state.
+ */
+#define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
+#define FTM_OUTMASK_CH3OM_MASK (0x8U)
+#define FTM_OUTMASK_CH3OM_SHIFT (3U)
+/*! CH3OM - Channel 3 Output Mask
+ * 0b0..Channel output is not masked. It continues to operate normally.
+ * 0b1..Channel output is masked. It is forced to its inactive state.
+ */
+#define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
+#define FTM_OUTMASK_CH4OM_MASK (0x10U)
+#define FTM_OUTMASK_CH4OM_SHIFT (4U)
+/*! CH4OM - Channel 4 Output Mask
+ * 0b0..Channel output is not masked. It continues to operate normally.
+ * 0b1..Channel output is masked. It is forced to its inactive state.
+ */
+#define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
+#define FTM_OUTMASK_CH5OM_MASK (0x20U)
+#define FTM_OUTMASK_CH5OM_SHIFT (5U)
+/*! CH5OM - Channel 5 Output Mask
+ * 0b0..Channel output is not masked. It continues to operate normally.
+ * 0b1..Channel output is masked. It is forced to its inactive state.
+ */
+#define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
+#define FTM_OUTMASK_CH6OM_MASK (0x40U)
+#define FTM_OUTMASK_CH6OM_SHIFT (6U)
+/*! CH6OM - Channel 6 Output Mask
+ * 0b0..Channel output is not masked. It continues to operate normally.
+ * 0b1..Channel output is masked. It is forced to its inactive state.
+ */
+#define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
+#define FTM_OUTMASK_CH7OM_MASK (0x80U)
+#define FTM_OUTMASK_CH7OM_SHIFT (7U)
+/*! CH7OM - Channel 7 Output Mask
+ * 0b0..Channel output is not masked. It continues to operate normally.
+ * 0b1..Channel output is masked. It is forced to its inactive state.
+ */
+#define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
+/*! @} */
+
+/*! @name COMBINE - Function For Linked Channels */
+/*! @{ */
+#define FTM_COMBINE_COMBINE0_MASK (0x1U)
+#define FTM_COMBINE_COMBINE0_SHIFT (0U)
+/*! COMBINE0 - Combine Channels For n = 0
+ * 0b0..Channels (n) and (n+1) are independent.
+ * 0b1..Channels (n) and (n+1) are combined.
+ */
+#define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
+#define FTM_COMBINE_COMP0_MASK (0x2U)
+#define FTM_COMBINE_COMP0_SHIFT (1U)
+/*! COMP0 - Complement Of Channel (n) For n = 0
+ * 0b0..The channel (n+1) output is the same as the channel (n) output.
+ * 0b1..The channel (n+1) output is the complement of the channel (n) output.
+ */
+#define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
+#define FTM_COMBINE_DECAPEN0_MASK (0x4U)
+#define FTM_COMBINE_DECAPEN0_SHIFT (2U)
+/*! DECAPEN0 - Dual Edge Capture Mode Enable For n = 0
+ * 0b0..The Dual Edge Capture mode in this pair of channels is disabled.
+ * 0b1..The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+#define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
+#define FTM_COMBINE_DECAP0_MASK (0x8U)
+#define FTM_COMBINE_DECAP0_SHIFT (3U)
+/*! DECAP0 - Dual Edge Capture Mode Captures For n = 0
+ * 0b0..The dual edge captures are inactive.
+ * 0b1..The dual edge captures are active.
+ */
+#define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
+#define FTM_COMBINE_DTEN0_MASK (0x10U)
+#define FTM_COMBINE_DTEN0_SHIFT (4U)
+/*! DTEN0 - Deadtime Enable For n = 0
+ * 0b0..The deadtime insertion in this pair of channels is disabled.
+ * 0b1..The deadtime insertion in this pair of channels is enabled.
+ */
+#define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
+#define FTM_COMBINE_SYNCEN0_MASK (0x20U)
+#define FTM_COMBINE_SYNCEN0_SHIFT (5U)
+/*! SYNCEN0 - Synchronization Enable For n = 0
+ * 0b0..The PWM synchronization in this pair of channels is disabled.
+ * 0b1..The PWM synchronization in this pair of channels is enabled.
+ */
+#define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
+#define FTM_COMBINE_FAULTEN0_MASK (0x40U)
+#define FTM_COMBINE_FAULTEN0_SHIFT (6U)
+/*! FAULTEN0 - Fault Control Enable For n = 0
+ * 0b0..The fault control in this pair of channels is disabled.
+ * 0b1..The fault control in this pair of channels is enabled.
+ */
+#define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
+#define FTM_COMBINE_COMBINE1_MASK (0x100U)
+#define FTM_COMBINE_COMBINE1_SHIFT (8U)
+/*! COMBINE1 - Combine Channels For n = 2
+ * 0b0..Channels (n) and (n+1) are independent.
+ * 0b1..Channels (n) and (n+1) are combined.
+ */
+#define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
+#define FTM_COMBINE_COMP1_MASK (0x200U)
+#define FTM_COMBINE_COMP1_SHIFT (9U)
+/*! COMP1 - Complement Of Channel (n) For n = 2
+ * 0b0..The channel (n+1) output is the same as the channel (n) output.
+ * 0b1..The channel (n+1) output is the complement of the channel (n) output.
+ */
+#define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
+#define FTM_COMBINE_DECAPEN1_MASK (0x400U)
+#define FTM_COMBINE_DECAPEN1_SHIFT (10U)
+/*! DECAPEN1 - Dual Edge Capture Mode Enable For n = 2
+ * 0b0..The Dual Edge Capture mode in this pair of channels is disabled.
+ * 0b1..The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+#define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
+#define FTM_COMBINE_DECAP1_MASK (0x800U)
+#define FTM_COMBINE_DECAP1_SHIFT (11U)
+/*! DECAP1 - Dual Edge Capture Mode Captures For n = 2
+ * 0b0..The dual edge captures are inactive.
+ * 0b1..The dual edge captures are active.
+ */
+#define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
+#define FTM_COMBINE_DTEN1_MASK (0x1000U)
+#define FTM_COMBINE_DTEN1_SHIFT (12U)
+/*! DTEN1 - Deadtime Enable For n = 2
+ * 0b0..The deadtime insertion in this pair of channels is disabled.
+ * 0b1..The deadtime insertion in this pair of channels is enabled.
+ */
+#define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
+#define FTM_COMBINE_SYNCEN1_MASK (0x2000U)
+#define FTM_COMBINE_SYNCEN1_SHIFT (13U)
+/*! SYNCEN1 - Synchronization Enable For n = 2
+ * 0b0..The PWM synchronization in this pair of channels is disabled.
+ * 0b1..The PWM synchronization in this pair of channels is enabled.
+ */
+#define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
+#define FTM_COMBINE_FAULTEN1_MASK (0x4000U)
+#define FTM_COMBINE_FAULTEN1_SHIFT (14U)
+/*! FAULTEN1 - Fault Control Enable For n = 2
+ * 0b0..The fault control in this pair of channels is disabled.
+ * 0b1..The fault control in this pair of channels is enabled.
+ */
+#define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
+#define FTM_COMBINE_COMBINE2_MASK (0x10000U)
+#define FTM_COMBINE_COMBINE2_SHIFT (16U)
+/*! COMBINE2 - Combine Channels For n = 4
+ * 0b0..Channels (n) and (n+1) are independent.
+ * 0b1..Channels (n) and (n+1) are combined.
+ */
+#define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
+#define FTM_COMBINE_COMP2_MASK (0x20000U)
+#define FTM_COMBINE_COMP2_SHIFT (17U)
+/*! COMP2 - Complement Of Channel (n) For n = 4
+ * 0b0..The channel (n+1) output is the same as the channel (n) output.
+ * 0b1..The channel (n+1) output is the complement of the channel (n) output.
+ */
+#define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
+#define FTM_COMBINE_DECAPEN2_MASK (0x40000U)
+#define FTM_COMBINE_DECAPEN2_SHIFT (18U)
+/*! DECAPEN2 - Dual Edge Capture Mode Enable For n = 4
+ * 0b0..The Dual Edge Capture mode in this pair of channels is disabled.
+ * 0b1..The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+#define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
+#define FTM_COMBINE_DECAP2_MASK (0x80000U)
+#define FTM_COMBINE_DECAP2_SHIFT (19U)
+/*! DECAP2 - Dual Edge Capture Mode Captures For n = 4
+ * 0b0..The dual edge captures are inactive.
+ * 0b1..The dual edge captures are active.
+ */
+#define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
+#define FTM_COMBINE_DTEN2_MASK (0x100000U)
+#define FTM_COMBINE_DTEN2_SHIFT (20U)
+/*! DTEN2 - Deadtime Enable For n = 4
+ * 0b0..The deadtime insertion in this pair of channels is disabled.
+ * 0b1..The deadtime insertion in this pair of channels is enabled.
+ */
+#define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
+#define FTM_COMBINE_SYNCEN2_MASK (0x200000U)
+#define FTM_COMBINE_SYNCEN2_SHIFT (21U)
+/*! SYNCEN2 - Synchronization Enable For n = 4
+ * 0b0..The PWM synchronization in this pair of channels is disabled.
+ * 0b1..The PWM synchronization in this pair of channels is enabled.
+ */
+#define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
+#define FTM_COMBINE_FAULTEN2_MASK (0x400000U)
+#define FTM_COMBINE_FAULTEN2_SHIFT (22U)
+/*! FAULTEN2 - Fault Control Enable For n = 4
+ * 0b0..The fault control in this pair of channels is disabled.
+ * 0b1..The fault control in this pair of channels is enabled.
+ */
+#define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
+#define FTM_COMBINE_COMBINE3_MASK (0x1000000U)
+#define FTM_COMBINE_COMBINE3_SHIFT (24U)
+/*! COMBINE3 - Combine Channels For n = 6
+ * 0b0..Channels (n) and (n+1) are independent.
+ * 0b1..Channels (n) and (n+1) are combined.
+ */
+#define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
+#define FTM_COMBINE_COMP3_MASK (0x2000000U)
+#define FTM_COMBINE_COMP3_SHIFT (25U)
+/*! COMP3 - Complement Of Channel (n) for n = 6
+ * 0b0..The channel (n+1) output is the same as the channel (n) output.
+ * 0b1..The channel (n+1) output is the complement of the channel (n) output.
+ */
+#define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
+#define FTM_COMBINE_DECAPEN3_MASK (0x4000000U)
+#define FTM_COMBINE_DECAPEN3_SHIFT (26U)
+/*! DECAPEN3 - Dual Edge Capture Mode Enable For n = 6
+ * 0b0..The Dual Edge Capture mode in this pair of channels is disabled.
+ * 0b1..The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+#define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
+#define FTM_COMBINE_DECAP3_MASK (0x8000000U)
+#define FTM_COMBINE_DECAP3_SHIFT (27U)
+/*! DECAP3 - Dual Edge Capture Mode Captures For n = 6
+ * 0b0..The dual edge captures are inactive.
+ * 0b1..The dual edge captures are active.
+ */
+#define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
+#define FTM_COMBINE_DTEN3_MASK (0x10000000U)
+#define FTM_COMBINE_DTEN3_SHIFT (28U)
+/*! DTEN3 - Deadtime Enable For n = 6
+ * 0b0..The deadtime insertion in this pair of channels is disabled.
+ * 0b1..The deadtime insertion in this pair of channels is enabled.
+ */
+#define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
+#define FTM_COMBINE_SYNCEN3_MASK (0x20000000U)
+#define FTM_COMBINE_SYNCEN3_SHIFT (29U)
+/*! SYNCEN3 - Synchronization Enable For n = 6
+ * 0b0..The PWM synchronization in this pair of channels is disabled.
+ * 0b1..The PWM synchronization in this pair of channels is enabled.
+ */
+#define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
+#define FTM_COMBINE_FAULTEN3_MASK (0x40000000U)
+#define FTM_COMBINE_FAULTEN3_SHIFT (30U)
+/*! FAULTEN3 - Fault Control Enable For n = 6
+ * 0b0..The fault control in this pair of channels is disabled.
+ * 0b1..The fault control in this pair of channels is enabled.
+ */
+#define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
+/*! @} */
+
+/*! @name DEADTIME - Deadtime Insertion Control */
+/*! @{ */
+#define FTM_DEADTIME_DTVAL_MASK (0x3FU)
+#define FTM_DEADTIME_DTVAL_SHIFT (0U)
+#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTPS_MASK (0xC0U)
+#define FTM_DEADTIME_DTPS_SHIFT (6U)
+/*! DTPS - Deadtime Prescaler Value
+ * 0b0x..Divide the system clock by 1.
+ * 0b10..Divide the system clock by 4.
+ * 0b11..Divide the system clock by 16.
+ */
+#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
+/*! @} */
+
+/*! @name EXTTRIG - FTM External Trigger */
+/*! @{ */
+#define FTM_EXTTRIG_CH2TRIG_MASK (0x1U)
+#define FTM_EXTTRIG_CH2TRIG_SHIFT (0U)
+/*! CH2TRIG - Channel 2 Trigger Enable
+ * 0b0..The generation of the channel trigger is disabled.
+ * 0b1..The generation of the channel trigger is enabled.
+ */
+#define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
+#define FTM_EXTTRIG_CH3TRIG_MASK (0x2U)
+#define FTM_EXTTRIG_CH3TRIG_SHIFT (1U)
+/*! CH3TRIG - Channel 3 Trigger Enable
+ * 0b0..The generation of the channel trigger is disabled.
+ * 0b1..The generation of the channel trigger is enabled.
+ */
+#define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
+#define FTM_EXTTRIG_CH4TRIG_MASK (0x4U)
+#define FTM_EXTTRIG_CH4TRIG_SHIFT (2U)
+/*! CH4TRIG - Channel 4 Trigger Enable
+ * 0b0..The generation of the channel trigger is disabled.
+ * 0b1..The generation of the channel trigger is enabled.
+ */
+#define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
+#define FTM_EXTTRIG_CH5TRIG_MASK (0x8U)
+#define FTM_EXTTRIG_CH5TRIG_SHIFT (3U)
+/*! CH5TRIG - Channel 5 Trigger Enable
+ * 0b0..The generation of the channel trigger is disabled.
+ * 0b1..The generation of the channel trigger is enabled.
+ */
+#define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
+#define FTM_EXTTRIG_CH0TRIG_MASK (0x10U)
+#define FTM_EXTTRIG_CH0TRIG_SHIFT (4U)
+/*! CH0TRIG - Channel 0 Trigger Enable
+ * 0b0..The generation of the channel trigger is disabled.
+ * 0b1..The generation of the channel trigger is enabled.
+ */
+#define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
+#define FTM_EXTTRIG_CH1TRIG_MASK (0x20U)
+#define FTM_EXTTRIG_CH1TRIG_SHIFT (5U)
+/*! CH1TRIG - Channel 1 Trigger Enable
+ * 0b0..The generation of the channel trigger is disabled.
+ * 0b1..The generation of the channel trigger is enabled.
+ */
+#define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
+#define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U)
+#define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U)
+/*! INITTRIGEN - Initialization Trigger Enable
+ * 0b0..The generation of initialization trigger is disabled.
+ * 0b1..The generation of initialization trigger is enabled.
+ */
+#define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
+#define FTM_EXTTRIG_TRIGF_MASK (0x80U)
+#define FTM_EXTTRIG_TRIGF_SHIFT (7U)
+/*! TRIGF - Channel Trigger Flag
+ * 0b0..No channel trigger was generated.
+ * 0b1..A channel trigger was generated.
+ */
+#define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
+/*! @} */
+
+/*! @name POL - Channels Polarity */
+/*! @{ */
+#define FTM_POL_POL0_MASK (0x1U)
+#define FTM_POL_POL0_SHIFT (0U)
+/*! POL0 - Channel 0 Polarity
+ * 0b0..The channel polarity is active high.
+ * 0b1..The channel polarity is active low.
+ */
+#define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
+#define FTM_POL_POL1_MASK (0x2U)
+#define FTM_POL_POL1_SHIFT (1U)
+/*! POL1 - Channel 1 Polarity
+ * 0b0..The channel polarity is active high.
+ * 0b1..The channel polarity is active low.
+ */
+#define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
+#define FTM_POL_POL2_MASK (0x4U)
+#define FTM_POL_POL2_SHIFT (2U)
+/*! POL2 - Channel 2 Polarity
+ * 0b0..The channel polarity is active high.
+ * 0b1..The channel polarity is active low.
+ */
+#define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
+#define FTM_POL_POL3_MASK (0x8U)
+#define FTM_POL_POL3_SHIFT (3U)
+/*! POL3 - Channel 3 Polarity
+ * 0b0..The channel polarity is active high.
+ * 0b1..The channel polarity is active low.
+ */
+#define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
+#define FTM_POL_POL4_MASK (0x10U)
+#define FTM_POL_POL4_SHIFT (4U)
+/*! POL4 - Channel 4 Polarity
+ * 0b0..The channel polarity is active high.
+ * 0b1..The channel polarity is active low.
+ */
+#define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
+#define FTM_POL_POL5_MASK (0x20U)
+#define FTM_POL_POL5_SHIFT (5U)
+/*! POL5 - Channel 5 Polarity
+ * 0b0..The channel polarity is active high.
+ * 0b1..The channel polarity is active low.
+ */
+#define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
+#define FTM_POL_POL6_MASK (0x40U)
+#define FTM_POL_POL6_SHIFT (6U)
+/*! POL6 - Channel 6 Polarity
+ * 0b0..The channel polarity is active high.
+ * 0b1..The channel polarity is active low.
+ */
+#define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
+#define FTM_POL_POL7_MASK (0x80U)
+#define FTM_POL_POL7_SHIFT (7U)
+/*! POL7 - Channel 7 Polarity
+ * 0b0..The channel polarity is active high.
+ * 0b1..The channel polarity is active low.
+ */
+#define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
+/*! @} */
+
+/*! @name FMS - Fault Mode Status */
+/*! @{ */
+#define FTM_FMS_FAULTF0_MASK (0x1U)
+#define FTM_FMS_FAULTF0_SHIFT (0U)
+/*! FAULTF0 - Fault Detection Flag 0
+ * 0b0..No fault condition was detected at the fault input.
+ * 0b1..A fault condition was detected at the fault input.
+ */
+#define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
+#define FTM_FMS_FAULTF1_MASK (0x2U)
+#define FTM_FMS_FAULTF1_SHIFT (1U)
+/*! FAULTF1 - Fault Detection Flag 1
+ * 0b0..No fault condition was detected at the fault input.
+ * 0b1..A fault condition was detected at the fault input.
+ */
+#define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
+#define FTM_FMS_FAULTF2_MASK (0x4U)
+#define FTM_FMS_FAULTF2_SHIFT (2U)
+/*! FAULTF2 - Fault Detection Flag 2
+ * 0b0..No fault condition was detected at the fault input.
+ * 0b1..A fault condition was detected at the fault input.
+ */
+#define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
+#define FTM_FMS_FAULTF3_MASK (0x8U)
+#define FTM_FMS_FAULTF3_SHIFT (3U)
+/*! FAULTF3 - Fault Detection Flag 3
+ * 0b0..No fault condition was detected at the fault input.
+ * 0b1..A fault condition was detected at the fault input.
+ */
+#define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
+#define FTM_FMS_FAULTIN_MASK (0x20U)
+#define FTM_FMS_FAULTIN_SHIFT (5U)
+/*! FAULTIN - Fault Inputs
+ * 0b0..The logic OR of the enabled fault inputs is 0.
+ * 0b1..The logic OR of the enabled fault inputs is 1.
+ */
+#define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
+#define FTM_FMS_WPEN_MASK (0x40U)
+#define FTM_FMS_WPEN_SHIFT (6U)
+/*! WPEN - Write Protection Enable
+ * 0b0..Write protection is disabled. Write protected bits can be written.
+ * 0b1..Write protection is enabled. Write protected bits cannot be written.
+ */
+#define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
+#define FTM_FMS_FAULTF_MASK (0x80U)
+#define FTM_FMS_FAULTF_SHIFT (7U)
+/*! FAULTF - Fault Detection Flag
+ * 0b0..No fault condition was detected.
+ * 0b1..A fault condition was detected.
+ */
+#define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
+/*! @} */
+
+/*! @name FILTER - Input Capture Filter Control */
+/*! @{ */
+#define FTM_FILTER_CH0FVAL_MASK (0xFU)
+#define FTM_FILTER_CH0FVAL_SHIFT (0U)
+#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_MASK (0xF0U)
+#define FTM_FILTER_CH1FVAL_SHIFT (4U)
+#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_MASK (0xF00U)
+#define FTM_FILTER_CH2FVAL_SHIFT (8U)
+#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_MASK (0xF000U)
+#define FTM_FILTER_CH3FVAL_SHIFT (12U)
+#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
+/*! @} */
+
+/*! @name FLTCTRL - Fault Control */
+/*! @{ */
+#define FTM_FLTCTRL_FAULT0EN_MASK (0x1U)
+#define FTM_FLTCTRL_FAULT0EN_SHIFT (0U)
+/*! FAULT0EN - Fault Input 0 Enable
+ * 0b0..Fault input is disabled.
+ * 0b1..Fault input is enabled.
+ */
+#define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
+#define FTM_FLTCTRL_FAULT1EN_MASK (0x2U)
+#define FTM_FLTCTRL_FAULT1EN_SHIFT (1U)
+/*! FAULT1EN - Fault Input 1 Enable
+ * 0b0..Fault input is disabled.
+ * 0b1..Fault input is enabled.
+ */
+#define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
+#define FTM_FLTCTRL_FAULT2EN_MASK (0x4U)
+#define FTM_FLTCTRL_FAULT2EN_SHIFT (2U)
+/*! FAULT2EN - Fault Input 2 Enable
+ * 0b0..Fault input is disabled.
+ * 0b1..Fault input is enabled.
+ */
+#define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
+#define FTM_FLTCTRL_FAULT3EN_MASK (0x8U)
+#define FTM_FLTCTRL_FAULT3EN_SHIFT (3U)
+/*! FAULT3EN - Fault Input 3 Enable
+ * 0b0..Fault input is disabled.
+ * 0b1..Fault input is enabled.
+ */
+#define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
+#define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U)
+#define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U)
+/*! FFLTR0EN - Fault Input 0 Filter Enable
+ * 0b0..Fault input filter is disabled.
+ * 0b1..Fault input filter is enabled.
+ */
+#define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
+#define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U)
+#define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U)
+/*! FFLTR1EN - Fault Input 1 Filter Enable
+ * 0b0..Fault input filter is disabled.
+ * 0b1..Fault input filter is enabled.
+ */
+#define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
+#define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U)
+#define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U)
+/*! FFLTR2EN - Fault Input 2 Filter Enable
+ * 0b0..Fault input filter is disabled.
+ * 0b1..Fault input filter is enabled.
+ */
+#define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
+#define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U)
+#define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U)
+/*! FFLTR3EN - Fault Input 3 Filter Enable
+ * 0b0..Fault input filter is disabled.
+ * 0b1..Fault input filter is enabled.
+ */
+#define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
+#define FTM_FLTCTRL_FFVAL_MASK (0xF00U)
+#define FTM_FLTCTRL_FFVAL_SHIFT (8U)
+#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
+/*! @} */
+
+/*! @name QDCTRL - Quadrature Decoder Control And Status */
+/*! @{ */
+#define FTM_QDCTRL_QUADEN_MASK (0x1U)
+#define FTM_QDCTRL_QUADEN_SHIFT (0U)
+/*! QUADEN - Quadrature Decoder Mode Enable
+ * 0b0..Quadrature Decoder mode is disabled.
+ * 0b1..Quadrature Decoder mode is enabled.
+ */
+#define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
+#define FTM_QDCTRL_TOFDIR_MASK (0x2U)
+#define FTM_QDCTRL_TOFDIR_SHIFT (1U)
+/*! TOFDIR - Timer Overflow Direction In Quadrature Decoder Mode
+ * 0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register).
+ * 0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).
+ */
+#define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
+#define FTM_QDCTRL_QUADIR_MASK (0x4U)
+#define FTM_QDCTRL_QUADIR_SHIFT (2U)
+/*! QUADIR - FTM Counter Direction In Quadrature Decoder Mode
+ * 0b0..Counting direction is decreasing (FTM counter decrement).
+ * 0b1..Counting direction is increasing (FTM counter increment).
+ */
+#define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
+#define FTM_QDCTRL_QUADMODE_MASK (0x8U)
+#define FTM_QDCTRL_QUADMODE_SHIFT (3U)
+/*! QUADMODE - Quadrature Decoder Mode
+ * 0b0..Phase A and phase B encoding mode.
+ * 0b1..Count and direction encoding mode.
+ */
+#define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
+#define FTM_QDCTRL_PHBPOL_MASK (0x10U)
+#define FTM_QDCTRL_PHBPOL_SHIFT (4U)
+/*! PHBPOL - Phase B Input Polarity
+ * 0b0..Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.
+ * 0b1..Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.
+ */
+#define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
+#define FTM_QDCTRL_PHAPOL_MASK (0x20U)
+#define FTM_QDCTRL_PHAPOL_SHIFT (5U)
+/*! PHAPOL - Phase A Input Polarity
+ * 0b0..Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.
+ * 0b1..Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.
+ */
+#define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
+#define FTM_QDCTRL_PHBFLTREN_MASK (0x40U)
+#define FTM_QDCTRL_PHBFLTREN_SHIFT (6U)
+/*! PHBFLTREN - Phase B Input Filter Enable
+ * 0b0..Phase B input filter is disabled.
+ * 0b1..Phase B input filter is enabled.
+ */
+#define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
+#define FTM_QDCTRL_PHAFLTREN_MASK (0x80U)
+#define FTM_QDCTRL_PHAFLTREN_SHIFT (7U)
+/*! PHAFLTREN - Phase A Input Filter Enable
+ * 0b0..Phase A input filter is disabled.
+ * 0b1..Phase A input filter is enabled.
+ */
+#define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
+/*! @} */
+
+/*! @name CONF - Configuration */
+/*! @{ */
+#define FTM_CONF_NUMTOF_MASK (0x1FU)
+#define FTM_CONF_NUMTOF_SHIFT (0U)
+#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_BDMMODE_MASK (0xC0U)
+#define FTM_CONF_BDMMODE_SHIFT (6U)
+#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_GTBEEN_MASK (0x200U)
+#define FTM_CONF_GTBEEN_SHIFT (9U)
+/*! GTBEEN - Global Time Base Enable
+ * 0b0..Use of an external global time base is disabled.
+ * 0b1..Use of an external global time base is enabled.
+ */
+#define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
+#define FTM_CONF_GTBEOUT_MASK (0x400U)
+#define FTM_CONF_GTBEOUT_SHIFT (10U)
+/*! GTBEOUT - Global Time Base Output
+ * 0b0..A global time base signal generation is disabled.
+ * 0b1..A global time base signal generation is enabled.
+ */
+#define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
+/*! @} */
+
+/*! @name FLTPOL - FTM Fault Input Polarity */
+/*! @{ */
+#define FTM_FLTPOL_FLT0POL_MASK (0x1U)
+#define FTM_FLTPOL_FLT0POL_SHIFT (0U)
+/*! FLT0POL - Fault Input 0 Polarity
+ * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
+ * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
+ */
+#define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
+#define FTM_FLTPOL_FLT1POL_MASK (0x2U)
+#define FTM_FLTPOL_FLT1POL_SHIFT (1U)
+/*! FLT1POL - Fault Input 1 Polarity
+ * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
+ * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
+ */
+#define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
+#define FTM_FLTPOL_FLT2POL_MASK (0x4U)
+#define FTM_FLTPOL_FLT2POL_SHIFT (2U)
+/*! FLT2POL - Fault Input 2 Polarity
+ * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
+ * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
+ */
+#define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
+#define FTM_FLTPOL_FLT3POL_MASK (0x8U)
+#define FTM_FLTPOL_FLT3POL_SHIFT (3U)
+/*! FLT3POL - Fault Input 3 Polarity
+ * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
+ * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
+ */
+#define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
+/*! @} */
+
+/*! @name SYNCONF - Synchronization Configuration */
+/*! @{ */
+#define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U)
+#define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U)
+/*! HWTRIGMODE - Hardware Trigger Mode
+ * 0b0..FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
+ * 0b1..FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
+ */
+#define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
+#define FTM_SYNCONF_CNTINC_MASK (0x4U)
+#define FTM_SYNCONF_CNTINC_SHIFT (2U)
+/*! CNTINC - CNTIN Register Synchronization
+ * 0b0..CNTIN register is updated with its buffer value at all rising edges of system clock.
+ * 0b1..CNTIN register is updated with its buffer value by the PWM synchronization.
+ */
+#define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
+#define FTM_SYNCONF_INVC_MASK (0x10U)
+#define FTM_SYNCONF_INVC_SHIFT (4U)
+/*! INVC - INVCTRL Register Synchronization
+ * 0b0..INVCTRL register is updated with its buffer value at all rising edges of system clock.
+ * 0b1..INVCTRL register is updated with its buffer value by the PWM synchronization.
+ */
+#define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
+#define FTM_SYNCONF_SWOC_MASK (0x20U)
+#define FTM_SYNCONF_SWOC_SHIFT (5U)
+/*! SWOC - SWOCTRL Register Synchronization
+ * 0b0..SWOCTRL register is updated with its buffer value at all rising edges of system clock.
+ * 0b1..SWOCTRL register is updated with its buffer value by the PWM synchronization.
+ */
+#define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
+#define FTM_SYNCONF_SYNCMODE_MASK (0x80U)
+#define FTM_SYNCONF_SYNCMODE_SHIFT (7U)
+/*! SYNCMODE - Synchronization Mode
+ * 0b0..Legacy PWM synchronization is selected.
+ * 0b1..Enhanced PWM synchronization is selected.
+ */
+#define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
+#define FTM_SYNCONF_SWRSTCNT_MASK (0x100U)
+#define FTM_SYNCONF_SWRSTCNT_SHIFT (8U)
+/*! SWRSTCNT
+ * 0b0..The software trigger does not activate the FTM counter synchronization.
+ * 0b1..The software trigger activates the FTM counter synchronization.
+ */
+#define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
+#define FTM_SYNCONF_SWWRBUF_MASK (0x200U)
+#define FTM_SYNCONF_SWWRBUF_SHIFT (9U)
+/*! SWWRBUF
+ * 0b0..The software trigger does not activate MOD, CNTIN, and CV registers synchronization.
+ * 0b1..The software trigger activates MOD, CNTIN, and CV registers synchronization.
+ */
+#define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
+#define FTM_SYNCONF_SWOM_MASK (0x400U)
+#define FTM_SYNCONF_SWOM_SHIFT (10U)
+/*! SWOM
+ * 0b0..The software trigger does not activate the OUTMASK register synchronization.
+ * 0b1..The software trigger activates the OUTMASK register synchronization.
+ */
+#define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
+#define FTM_SYNCONF_SWINVC_MASK (0x800U)
+#define FTM_SYNCONF_SWINVC_SHIFT (11U)
+/*! SWINVC
+ * 0b0..The software trigger does not activate the INVCTRL register synchronization.
+ * 0b1..The software trigger activates the INVCTRL register synchronization.
+ */
+#define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
+#define FTM_SYNCONF_SWSOC_MASK (0x1000U)
+#define FTM_SYNCONF_SWSOC_SHIFT (12U)
+/*! SWSOC
+ * 0b0..The software trigger does not activate the SWOCTRL register synchronization.
+ * 0b1..The software trigger activates the SWOCTRL register synchronization.
+ */
+#define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
+#define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U)
+#define FTM_SYNCONF_HWRSTCNT_SHIFT (16U)
+/*! HWRSTCNT
+ * 0b0..A hardware trigger does not activate the FTM counter synchronization.
+ * 0b1..A hardware trigger activates the FTM counter synchronization.
+ */
+#define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
+#define FTM_SYNCONF_HWWRBUF_MASK (0x20000U)
+#define FTM_SYNCONF_HWWRBUF_SHIFT (17U)
+/*! HWWRBUF
+ * 0b0..A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.
+ * 0b1..A hardware trigger activates MOD, CNTIN, and CV registers synchronization.
+ */
+#define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
+#define FTM_SYNCONF_HWOM_MASK (0x40000U)
+#define FTM_SYNCONF_HWOM_SHIFT (18U)
+/*! HWOM
+ * 0b0..A hardware trigger does not activate the OUTMASK register synchronization.
+ * 0b1..A hardware trigger activates the OUTMASK register synchronization.
+ */
+#define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
+#define FTM_SYNCONF_HWINVC_MASK (0x80000U)
+#define FTM_SYNCONF_HWINVC_SHIFT (19U)
+/*! HWINVC
+ * 0b0..A hardware trigger does not activate the INVCTRL register synchronization.
+ * 0b1..A hardware trigger activates the INVCTRL register synchronization.
+ */
+#define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
+#define FTM_SYNCONF_HWSOC_MASK (0x100000U)
+#define FTM_SYNCONF_HWSOC_SHIFT (20U)
+/*! HWSOC
+ * 0b0..A hardware trigger does not activate the SWOCTRL register synchronization.
+ * 0b1..A hardware trigger activates the SWOCTRL register synchronization.
+ */
+#define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
+/*! @} */
+
+/*! @name INVCTRL - FTM Inverting Control */
+/*! @{ */
+#define FTM_INVCTRL_INV0EN_MASK (0x1U)
+#define FTM_INVCTRL_INV0EN_SHIFT (0U)
+/*! INV0EN - Pair Channels 0 Inverting Enable
+ * 0b0..Inverting is disabled.
+ * 0b1..Inverting is enabled.
+ */
+#define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
+#define FTM_INVCTRL_INV1EN_MASK (0x2U)
+#define FTM_INVCTRL_INV1EN_SHIFT (1U)
+/*! INV1EN - Pair Channels 1 Inverting Enable
+ * 0b0..Inverting is disabled.
+ * 0b1..Inverting is enabled.
+ */
+#define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
+#define FTM_INVCTRL_INV2EN_MASK (0x4U)
+#define FTM_INVCTRL_INV2EN_SHIFT (2U)
+/*! INV2EN - Pair Channels 2 Inverting Enable
+ * 0b0..Inverting is disabled.
+ * 0b1..Inverting is enabled.
+ */
+#define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
+#define FTM_INVCTRL_INV3EN_MASK (0x8U)
+#define FTM_INVCTRL_INV3EN_SHIFT (3U)
+/*! INV3EN - Pair Channels 3 Inverting Enable
+ * 0b0..Inverting is disabled.
+ * 0b1..Inverting is enabled.
+ */
+#define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
+/*! @} */
+
+/*! @name SWOCTRL - FTM Software Output Control */
+/*! @{ */
+#define FTM_SWOCTRL_CH0OC_MASK (0x1U)
+#define FTM_SWOCTRL_CH0OC_SHIFT (0U)
+/*! CH0OC - Channel 0 Software Output Control Enable
+ * 0b0..The channel output is not affected by software output control.
+ * 0b1..The channel output is affected by software output control.
+ */
+#define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
+#define FTM_SWOCTRL_CH1OC_MASK (0x2U)
+#define FTM_SWOCTRL_CH1OC_SHIFT (1U)
+/*! CH1OC - Channel 1 Software Output Control Enable
+ * 0b0..The channel output is not affected by software output control.
+ * 0b1..The channel output is affected by software output control.
+ */
+#define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
+#define FTM_SWOCTRL_CH2OC_MASK (0x4U)
+#define FTM_SWOCTRL_CH2OC_SHIFT (2U)
+/*! CH2OC - Channel 2 Software Output Control Enable
+ * 0b0..The channel output is not affected by software output control.
+ * 0b1..The channel output is affected by software output control.
+ */
+#define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
+#define FTM_SWOCTRL_CH3OC_MASK (0x8U)
+#define FTM_SWOCTRL_CH3OC_SHIFT (3U)
+/*! CH3OC - Channel 3 Software Output Control Enable
+ * 0b0..The channel output is not affected by software output control.
+ * 0b1..The channel output is affected by software output control.
+ */
+#define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
+#define FTM_SWOCTRL_CH4OC_MASK (0x10U)
+#define FTM_SWOCTRL_CH4OC_SHIFT (4U)
+/*! CH4OC - Channel 4 Software Output Control Enable
+ * 0b0..The channel output is not affected by software output control.
+ * 0b1..The channel output is affected by software output control.
+ */
+#define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
+#define FTM_SWOCTRL_CH5OC_MASK (0x20U)
+#define FTM_SWOCTRL_CH5OC_SHIFT (5U)
+/*! CH5OC - Channel 5 Software Output Control Enable
+ * 0b0..The channel output is not affected by software output control.
+ * 0b1..The channel output is affected by software output control.
+ */
+#define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
+#define FTM_SWOCTRL_CH6OC_MASK (0x40U)
+#define FTM_SWOCTRL_CH6OC_SHIFT (6U)
+/*! CH6OC - Channel 6 Software Output Control Enable
+ * 0b0..The channel output is not affected by software output control.
+ * 0b1..The channel output is affected by software output control.
+ */
+#define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
+#define FTM_SWOCTRL_CH7OC_MASK (0x80U)
+#define FTM_SWOCTRL_CH7OC_SHIFT (7U)
+/*! CH7OC - Channel 7 Software Output Control Enable
+ * 0b0..The channel output is not affected by software output control.
+ * 0b1..The channel output is affected by software output control.
+ */
+#define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
+#define FTM_SWOCTRL_CH0OCV_MASK (0x100U)
+#define FTM_SWOCTRL_CH0OCV_SHIFT (8U)
+/*! CH0OCV - Channel 0 Software Output Control Value
+ * 0b0..The software output control forces 0 to the channel output.
+ * 0b1..The software output control forces 1 to the channel output.
+ */
+#define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
+#define FTM_SWOCTRL_CH1OCV_MASK (0x200U)
+#define FTM_SWOCTRL_CH1OCV_SHIFT (9U)
+/*! CH1OCV - Channel 1 Software Output Control Value
+ * 0b0..The software output control forces 0 to the channel output.
+ * 0b1..The software output control forces 1 to the channel output.
+ */
+#define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
+#define FTM_SWOCTRL_CH2OCV_MASK (0x400U)
+#define FTM_SWOCTRL_CH2OCV_SHIFT (10U)
+/*! CH2OCV - Channel 2 Software Output Control Value
+ * 0b0..The software output control forces 0 to the channel output.
+ * 0b1..The software output control forces 1 to the channel output.
+ */
+#define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
+#define FTM_SWOCTRL_CH3OCV_MASK (0x800U)
+#define FTM_SWOCTRL_CH3OCV_SHIFT (11U)
+/*! CH3OCV - Channel 3 Software Output Control Value
+ * 0b0..The software output control forces 0 to the channel output.
+ * 0b1..The software output control forces 1 to the channel output.
+ */
+#define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
+#define FTM_SWOCTRL_CH4OCV_MASK (0x1000U)
+#define FTM_SWOCTRL_CH4OCV_SHIFT (12U)
+/*! CH4OCV - Channel 4 Software Output Control Value
+ * 0b0..The software output control forces 0 to the channel output.
+ * 0b1..The software output control forces 1 to the channel output.
+ */
+#define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
+#define FTM_SWOCTRL_CH5OCV_MASK (0x2000U)
+#define FTM_SWOCTRL_CH5OCV_SHIFT (13U)
+/*! CH5OCV - Channel 5 Software Output Control Value
+ * 0b0..The software output control forces 0 to the channel output.
+ * 0b1..The software output control forces 1 to the channel output.
+ */
+#define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
+#define FTM_SWOCTRL_CH6OCV_MASK (0x4000U)
+#define FTM_SWOCTRL_CH6OCV_SHIFT (14U)
+/*! CH6OCV - Channel 6 Software Output Control Value
+ * 0b0..The software output control forces 0 to the channel output.
+ * 0b1..The software output control forces 1 to the channel output.
+ */
+#define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
+#define FTM_SWOCTRL_CH7OCV_MASK (0x8000U)
+#define FTM_SWOCTRL_CH7OCV_SHIFT (15U)
+/*! CH7OCV - Channel 7 Software Output Control Value
+ * 0b0..The software output control forces 0 to the channel output.
+ * 0b1..The software output control forces 1 to the channel output.
+ */
+#define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
+/*! @} */
+
+/*! @name PWMLOAD - FTM PWM Load */
+/*! @{ */
+#define FTM_PWMLOAD_CH0SEL_MASK (0x1U)
+#define FTM_PWMLOAD_CH0SEL_SHIFT (0U)
+/*! CH0SEL - Channel 0 Select
+ * 0b0..Do not include the channel in the matching process.
+ * 0b1..Include the channel in the matching process.
+ */
+#define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
+#define FTM_PWMLOAD_CH1SEL_MASK (0x2U)
+#define FTM_PWMLOAD_CH1SEL_SHIFT (1U)
+/*! CH1SEL - Channel 1 Select
+ * 0b0..Do not include the channel in the matching process.
+ * 0b1..Include the channel in the matching process.
+ */
+#define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
+#define FTM_PWMLOAD_CH2SEL_MASK (0x4U)
+#define FTM_PWMLOAD_CH2SEL_SHIFT (2U)
+/*! CH2SEL - Channel 2 Select
+ * 0b0..Do not include the channel in the matching process.
+ * 0b1..Include the channel in the matching process.
+ */
+#define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
+#define FTM_PWMLOAD_CH3SEL_MASK (0x8U)
+#define FTM_PWMLOAD_CH3SEL_SHIFT (3U)
+/*! CH3SEL - Channel 3 Select
+ * 0b0..Do not include the channel in the matching process.
+ * 0b1..Include the channel in the matching process.
+ */
+#define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
+#define FTM_PWMLOAD_CH4SEL_MASK (0x10U)
+#define FTM_PWMLOAD_CH4SEL_SHIFT (4U)
+/*! CH4SEL - Channel 4 Select
+ * 0b0..Do not include the channel in the matching process.
+ * 0b1..Include the channel in the matching process.
+ */
+#define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
+#define FTM_PWMLOAD_CH5SEL_MASK (0x20U)
+#define FTM_PWMLOAD_CH5SEL_SHIFT (5U)
+/*! CH5SEL - Channel 5 Select
+ * 0b0..Do not include the channel in the matching process.
+ * 0b1..Include the channel in the matching process.
+ */
+#define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
+#define FTM_PWMLOAD_CH6SEL_MASK (0x40U)
+#define FTM_PWMLOAD_CH6SEL_SHIFT (6U)
+/*! CH6SEL - Channel 6 Select
+ * 0b0..Do not include the channel in the matching process.
+ * 0b1..Include the channel in the matching process.
+ */
+#define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
+#define FTM_PWMLOAD_CH7SEL_MASK (0x80U)
+#define FTM_PWMLOAD_CH7SEL_SHIFT (7U)
+/*! CH7SEL - Channel 7 Select
+ * 0b0..Do not include the channel in the matching process.
+ * 0b1..Include the channel in the matching process.
+ */
+#define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
+#define FTM_PWMLOAD_LDOK_MASK (0x200U)
+#define FTM_PWMLOAD_LDOK_SHIFT (9U)
+/*! LDOK - Load Enable
+ * 0b0..Loading updated values is disabled.
+ * 0b1..Loading updated values is enabled.
+ */
+#define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Masks */
+
+
+/* FTM - Peripheral instance base addresses */
+/** Peripheral FTM0 base address */
+#define FTM0_BASE (0x40038000u)
+/** Peripheral FTM0 base pointer */
+#define FTM0 ((FTM_Type *)FTM0_BASE)
+/** Peripheral FTM1 base address */
+#define FTM1_BASE (0x40039000u)
+/** Peripheral FTM1 base pointer */
+#define FTM1 ((FTM_Type *)FTM1_BASE)
+/** Peripheral FTM2 base address */
+#define FTM2_BASE (0x4003A000u)
+/** Peripheral FTM2 base pointer */
+#define FTM2 ((FTM_Type *)FTM2_BASE)
+/** Peripheral FTM3 base address */
+#define FTM3_BASE (0x400B9000u)
+/** Peripheral FTM3 base pointer */
+#define FTM3 ((FTM_Type *)FTM3_BASE)
+/** Array initializer of FTM peripheral base addresses */
+#define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
+/** Array initializer of FTM peripheral base pointers */
+#define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
+/** Interrupt vectors for the FTM peripheral type */
+#define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FTM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/*! @name PDOR - Port Data Output Register */
+/*! @{ */
+#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
+#define GPIO_PDOR_PDO_SHIFT (0U)
+/*! PDO - Port Data Output
+ * 0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
+ * 0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
+ */
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
+/*! @} */
+
+/*! @name PSOR - Port Set Output Register */
+/*! @{ */
+#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
+#define GPIO_PSOR_PTSO_SHIFT (0U)
+/*! PTSO - Port Set Output
+ * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
+ * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1.
+ */
+#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
+/*! @} */
+
+/*! @name PCOR - Port Clear Output Register */
+/*! @{ */
+#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
+#define GPIO_PCOR_PTCO_SHIFT (0U)
+/*! PTCO - Port Clear Output
+ * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
+ * 0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0.
+ */
+#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
+/*! @} */
+
+/*! @name PTOR - Port Toggle Output Register */
+/*! @{ */
+#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
+#define GPIO_PTOR_PTTO_SHIFT (0U)
+/*! PTTO - Port Toggle Output
+ * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
+ * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state.
+ */
+#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
+/*! @} */
+
+/*! @name PDIR - Port Data Input Register */
+/*! @{ */
+#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
+#define GPIO_PDIR_PDI_SHIFT (0U)
+/*! PDI - Port Data Input
+ * 0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function.
+ * 0b00000000000000000000000000000001..Pin logic level is logic 1.
+ */
+#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
+/*! @} */
+
+/*! @name PDDR - Port Data Direction Register */
+/*! @{ */
+#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
+#define GPIO_PDDR_PDD_SHIFT (0U)
+/*! PDD - Port Data Direction
+ * 0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function.
+ * 0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function.
+ */
+#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral GPIOA base address */
+#define GPIOA_BASE (0x400FF000u)
+/** Peripheral GPIOA base pointer */
+#define GPIOA ((GPIO_Type *)GPIOA_BASE)
+/** Peripheral GPIOB base address */
+#define GPIOB_BASE (0x400FF040u)
+/** Peripheral GPIOB base pointer */
+#define GPIOB ((GPIO_Type *)GPIOB_BASE)
+/** Peripheral GPIOC base address */
+#define GPIOC_BASE (0x400FF080u)
+/** Peripheral GPIOC base pointer */
+#define GPIOC ((GPIO_Type *)GPIOC_BASE)
+/** Peripheral GPIOD base address */
+#define GPIOD_BASE (0x400FF0C0u)
+/** Peripheral GPIOD base pointer */
+#define GPIOD ((GPIO_Type *)GPIOD_BASE)
+/** Peripheral GPIOE base address */
+#define GPIOE_BASE (0x400FF100u)
+/** Peripheral GPIOE base pointer */
+#define GPIOE ((GPIO_Type *)GPIOE_BASE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
+ __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
+ __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
+ __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
+ __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
+ __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
+ __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */
+ __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
+ __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
+ __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
+ __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
+ __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/*! @name A1 - I2C Address Register 1 */
+/*! @{ */
+#define I2C_A1_AD_MASK (0xFEU)
+#define I2C_A1_AD_SHIFT (1U)
+#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
+/*! @} */
+
+/*! @name F - I2C Frequency Divider register */
+/*! @{ */
+#define I2C_F_ICR_MASK (0x3FU)
+#define I2C_F_ICR_SHIFT (0U)
+#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK (0xC0U)
+#define I2C_F_MULT_SHIFT (6U)
+/*! MULT - Multiplier Factor
+ * 0b00..mul = 1
+ * 0b01..mul = 2
+ * 0b10..mul = 4
+ * 0b11..Reserved
+ */
+#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
+/*! @} */
+
+/*! @name C1 - I2C Control Register 1 */
+/*! @{ */
+#define I2C_C1_DMAEN_MASK (0x1U)
+#define I2C_C1_DMAEN_SHIFT (0U)
+/*! DMAEN - DMA Enable
+ * 0b0..All DMA signalling disabled.
+ * 0b1..DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.
+ */
+#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
+#define I2C_C1_WUEN_MASK (0x2U)
+#define I2C_C1_WUEN_SHIFT (1U)
+/*! WUEN - Wakeup Enable
+ * 0b0..Normal operation. No interrupt generated when address matching in low power mode.
+ * 0b1..Enables the wakeup function in low power mode.
+ */
+#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
+#define I2C_C1_RSTA_MASK (0x4U)
+#define I2C_C1_RSTA_SHIFT (2U)
+#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
+#define I2C_C1_TXAK_MASK (0x8U)
+#define I2C_C1_TXAK_SHIFT (3U)
+/*! TXAK - Transmit Acknowledge Enable
+ * 0b0..An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).
+ * 0b1..No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).
+ */
+#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
+#define I2C_C1_TX_MASK (0x10U)
+#define I2C_C1_TX_SHIFT (4U)
+/*! TX - Transmit Mode Select
+ * 0b0..Receive
+ * 0b1..Transmit
+ */
+#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
+#define I2C_C1_MST_MASK (0x20U)
+#define I2C_C1_MST_SHIFT (5U)
+/*! MST - Master Mode Select
+ * 0b0..Slave mode
+ * 0b1..Master mode
+ */
+#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
+#define I2C_C1_IICIE_MASK (0x40U)
+#define I2C_C1_IICIE_SHIFT (6U)
+/*! IICIE - I2C Interrupt Enable
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
+#define I2C_C1_IICEN_MASK (0x80U)
+#define I2C_C1_IICEN_SHIFT (7U)
+/*! IICEN - I2C Enable
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
+/*! @} */
+
+/*! @name S - I2C Status register */
+/*! @{ */
+#define I2C_S_RXAK_MASK (0x1U)
+#define I2C_S_RXAK_SHIFT (0U)
+/*! RXAK - Receive Acknowledge
+ * 0b0..Acknowledge signal was received after the completion of one byte of data transmission on the bus
+ * 0b1..No acknowledge signal detected
+ */
+#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
+#define I2C_S_IICIF_MASK (0x2U)
+#define I2C_S_IICIF_SHIFT (1U)
+/*! IICIF - Interrupt Flag
+ * 0b0..No interrupt pending
+ * 0b1..Interrupt pending
+ */
+#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
+#define I2C_S_SRW_MASK (0x4U)
+#define I2C_S_SRW_SHIFT (2U)
+/*! SRW - Slave Read/Write
+ * 0b0..Slave receive, master writing to slave
+ * 0b1..Slave transmit, master reading from slave
+ */
+#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
+#define I2C_S_RAM_MASK (0x8U)
+#define I2C_S_RAM_SHIFT (3U)
+/*! RAM - Range Address Match
+ * 0b0..Not addressed
+ * 0b1..Addressed as a slave
+ */
+#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
+#define I2C_S_ARBL_MASK (0x10U)
+#define I2C_S_ARBL_SHIFT (4U)
+/*! ARBL - Arbitration Lost
+ * 0b0..Standard bus operation.
+ * 0b1..Loss of arbitration.
+ */
+#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
+#define I2C_S_BUSY_MASK (0x20U)
+#define I2C_S_BUSY_SHIFT (5U)
+/*! BUSY - Bus Busy
+ * 0b0..Bus is idle
+ * 0b1..Bus is busy
+ */
+#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
+#define I2C_S_IAAS_MASK (0x40U)
+#define I2C_S_IAAS_SHIFT (6U)
+/*! IAAS - Addressed As A Slave
+ * 0b0..Not addressed
+ * 0b1..Addressed as a slave
+ */
+#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
+#define I2C_S_TCF_MASK (0x80U)
+#define I2C_S_TCF_SHIFT (7U)
+/*! TCF - Transfer Complete Flag
+ * 0b0..Transfer in progress
+ * 0b1..Transfer complete
+ */
+#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
+/*! @} */
+
+/*! @name D - I2C Data I/O register */
+/*! @{ */
+#define I2C_D_DATA_MASK (0xFFU)
+#define I2C_D_DATA_SHIFT (0U)
+#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
+/*! @} */
+
+/*! @name C2 - I2C Control Register 2 */
+/*! @{ */
+#define I2C_C2_AD_MASK (0x7U)
+#define I2C_C2_AD_SHIFT (0U)
+#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK (0x8U)
+#define I2C_C2_RMEN_SHIFT (3U)
+/*! RMEN - Range Address Matching Enable
+ * 0b0..Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers.
+ * 0b1..Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.
+ */
+#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
+#define I2C_C2_SBRC_MASK (0x10U)
+#define I2C_C2_SBRC_SHIFT (4U)
+/*! SBRC - Slave Baud Rate Control
+ * 0b0..The slave baud rate follows the master baud rate and clock stretching may occur
+ * 0b1..Slave baud rate is independent of the master baud rate
+ */
+#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
+#define I2C_C2_HDRS_MASK (0x20U)
+#define I2C_C2_HDRS_SHIFT (5U)
+/*! HDRS - High Drive Select
+ * 0b0..Normal drive mode
+ * 0b1..High drive mode
+ */
+#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
+#define I2C_C2_ADEXT_MASK (0x40U)
+#define I2C_C2_ADEXT_SHIFT (6U)
+/*! ADEXT - Address Extension
+ * 0b0..7-bit address scheme
+ * 0b1..10-bit address scheme
+ */
+#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
+#define I2C_C2_GCAEN_MASK (0x80U)
+#define I2C_C2_GCAEN_SHIFT (7U)
+/*! GCAEN - General Call Address Enable
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
+/*! @} */
+
+/*! @name FLT - I2C Programmable Input Glitch Filter Register */
+/*! @{ */
+#define I2C_FLT_FLT_MASK (0xFU)
+#define I2C_FLT_FLT_SHIFT (0U)
+/*! FLT - I2C Programmable Filter Factor
+ * 0b0000..No filter/bypass
+ */
+#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
+#define I2C_FLT_STARTF_MASK (0x10U)
+#define I2C_FLT_STARTF_SHIFT (4U)
+/*! STARTF - I2C Bus Start Detect Flag
+ * 0b0..No start happens on I2C bus
+ * 0b1..Start detected on I2C bus
+ */
+#define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
+#define I2C_FLT_SSIE_MASK (0x20U)
+#define I2C_FLT_SSIE_SHIFT (5U)
+/*! SSIE - I2C Bus Stop or Start Interrupt Enable
+ * 0b0..Stop or start detection interrupt is disabled
+ * 0b1..Stop or start detection interrupt is enabled
+ */
+#define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
+#define I2C_FLT_STOPF_MASK (0x40U)
+#define I2C_FLT_STOPF_SHIFT (6U)
+/*! STOPF - I2C Bus Stop Detect Flag
+ * 0b0..No stop happens on I2C bus
+ * 0b1..Stop detected on I2C bus
+ */
+#define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
+#define I2C_FLT_SHEN_MASK (0x80U)
+#define I2C_FLT_SHEN_SHIFT (7U)
+/*! SHEN - Stop Hold Enable
+ * 0b0..Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
+ * 0b1..Stop holdoff is enabled.
+ */
+#define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
+/*! @} */
+
+/*! @name RA - I2C Range Address register */
+/*! @{ */
+#define I2C_RA_RAD_MASK (0xFEU)
+#define I2C_RA_RAD_SHIFT (1U)
+#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
+/*! @} */
+
+/*! @name SMB - I2C SMBus Control and Status register */
+/*! @{ */
+#define I2C_SMB_SHTF2IE_MASK (0x1U)
+#define I2C_SMB_SHTF2IE_SHIFT (0U)
+/*! SHTF2IE - SHTF2 Interrupt Enable
+ * 0b0..SHTF2 interrupt is disabled
+ * 0b1..SHTF2 interrupt is enabled
+ */
+#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
+#define I2C_SMB_SHTF2_MASK (0x2U)
+#define I2C_SMB_SHTF2_SHIFT (1U)
+/*! SHTF2 - SCL High Timeout Flag 2
+ * 0b0..No SCL high and SDA low timeout occurs
+ * 0b1..SCL high and SDA low timeout occurs
+ */
+#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
+#define I2C_SMB_SHTF1_MASK (0x4U)
+#define I2C_SMB_SHTF1_SHIFT (2U)
+/*! SHTF1 - SCL High Timeout Flag 1
+ * 0b0..No SCL high and SDA high timeout occurs
+ * 0b1..SCL high and SDA high timeout occurs
+ */
+#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
+#define I2C_SMB_SLTF_MASK (0x8U)
+#define I2C_SMB_SLTF_SHIFT (3U)
+/*! SLTF - SCL Low Timeout Flag
+ * 0b0..No low timeout occurs
+ * 0b1..Low timeout occurs
+ */
+#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
+#define I2C_SMB_TCKSEL_MASK (0x10U)
+#define I2C_SMB_TCKSEL_SHIFT (4U)
+/*! TCKSEL - Timeout Counter Clock Select
+ * 0b0..Timeout counter counts at the frequency of the I2C module clock / 64
+ * 0b1..Timeout counter counts at the frequency of the I2C module clock
+ */
+#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
+#define I2C_SMB_SIICAEN_MASK (0x20U)
+#define I2C_SMB_SIICAEN_SHIFT (5U)
+/*! SIICAEN - Second I2C Address Enable
+ * 0b0..I2C address register 2 matching is disabled
+ * 0b1..I2C address register 2 matching is enabled
+ */
+#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
+#define I2C_SMB_ALERTEN_MASK (0x40U)
+#define I2C_SMB_ALERTEN_SHIFT (6U)
+/*! ALERTEN - SMBus Alert Response Address Enable
+ * 0b0..SMBus alert response address matching is disabled
+ * 0b1..SMBus alert response address matching is enabled
+ */
+#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
+#define I2C_SMB_FACK_MASK (0x80U)
+#define I2C_SMB_FACK_SHIFT (7U)
+/*! FACK - Fast NACK/ACK Enable
+ * 0b0..An ACK or NACK is sent on the following receiving data byte
+ * 0b1..Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.
+ */
+#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
+/*! @} */
+
+/*! @name A2 - I2C Address Register 2 */
+/*! @{ */
+#define I2C_A2_SAD_MASK (0xFEU)
+#define I2C_A2_SAD_SHIFT (1U)
+#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
+/*! @} */
+
+/*! @name SLTH - I2C SCL Low Timeout Register High */
+/*! @{ */
+#define I2C_SLTH_SSLT_MASK (0xFFU)
+#define I2C_SLTH_SSLT_SHIFT (0U)
+#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
+/*! @} */
+
+/*! @name SLTL - I2C SCL Low Timeout Register Low */
+/*! @{ */
+#define I2C_SLTL_SSLT_MASK (0xFFU)
+#define I2C_SLTL_SSLT_SHIFT (0U)
+#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0 ((I2C_Type *)I2C0_BASE)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1 ((I2C_Type *)I2C1_BASE)
+/** Peripheral I2C2 base address */
+#define I2C2_BASE (0x400E6000u)
+/** Peripheral I2C2 base pointer */
+#define I2C2 ((I2C_Type *)I2C2_BASE)
+/** Peripheral I2C3 base address */
+#define I2C3_BASE (0x400E7000u)
+/** Peripheral I2C3 base pointer */
+#define I2C3 ((I2C_Type *)I2C3_BASE)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn, I2C3_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
+ __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
+ __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+ __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+ __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+ __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+ uint8_t RESERVED_0[8];
+ __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+ uint8_t RESERVED_1[24];
+ __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
+ uint8_t RESERVED_2[24];
+ __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
+ uint8_t RESERVED_3[28];
+ __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
+ __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
+ __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+ __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+ __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+ __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+ uint8_t RESERVED_4[8];
+ __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+ uint8_t RESERVED_5[24];
+ __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_6[24];
+ __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
+ uint8_t RESERVED_7[28];
+ __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
+ __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
+} I2S_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2S Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/*! @name TCSR - SAI Transmit Control Register */
+/*! @{ */
+#define I2S_TCSR_FRDE_MASK (0x1U)
+#define I2S_TCSR_FRDE_SHIFT (0U)
+/*! FRDE - FIFO Request DMA Enable
+ * 0b0..Disables the DMA request.
+ * 0b1..Enables the DMA request.
+ */
+#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
+#define I2S_TCSR_FWDE_MASK (0x2U)
+#define I2S_TCSR_FWDE_SHIFT (1U)
+/*! FWDE - FIFO Warning DMA Enable
+ * 0b0..Disables the DMA request.
+ * 0b1..Enables the DMA request.
+ */
+#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
+#define I2S_TCSR_FRIE_MASK (0x100U)
+#define I2S_TCSR_FRIE_SHIFT (8U)
+/*! FRIE - FIFO Request Interrupt Enable
+ * 0b0..Disables the interrupt.
+ * 0b1..Enables the interrupt.
+ */
+#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
+#define I2S_TCSR_FWIE_MASK (0x200U)
+#define I2S_TCSR_FWIE_SHIFT (9U)
+/*! FWIE - FIFO Warning Interrupt Enable
+ * 0b0..Disables the interrupt.
+ * 0b1..Enables the interrupt.
+ */
+#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
+#define I2S_TCSR_FEIE_MASK (0x400U)
+#define I2S_TCSR_FEIE_SHIFT (10U)
+/*! FEIE - FIFO Error Interrupt Enable
+ * 0b0..Disables the interrupt.
+ * 0b1..Enables the interrupt.
+ */
+#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
+#define I2S_TCSR_SEIE_MASK (0x800U)
+#define I2S_TCSR_SEIE_SHIFT (11U)
+/*! SEIE - Sync Error Interrupt Enable
+ * 0b0..Disables interrupt.
+ * 0b1..Enables interrupt.
+ */
+#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
+#define I2S_TCSR_WSIE_MASK (0x1000U)
+#define I2S_TCSR_WSIE_SHIFT (12U)
+/*! WSIE - Word Start Interrupt Enable
+ * 0b0..Disables interrupt.
+ * 0b1..Enables interrupt.
+ */
+#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
+#define I2S_TCSR_FRF_MASK (0x10000U)
+#define I2S_TCSR_FRF_SHIFT (16U)
+/*! FRF - FIFO Request Flag
+ * 0b0..Transmit FIFO watermark has not been reached.
+ * 0b1..Transmit FIFO watermark has been reached.
+ */
+#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
+#define I2S_TCSR_FWF_MASK (0x20000U)
+#define I2S_TCSR_FWF_SHIFT (17U)
+/*! FWF - FIFO Warning Flag
+ * 0b0..No enabled transmit FIFO is empty.
+ * 0b1..Enabled transmit FIFO is empty.
+ */
+#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
+#define I2S_TCSR_FEF_MASK (0x40000U)
+#define I2S_TCSR_FEF_SHIFT (18U)
+/*! FEF - FIFO Error Flag
+ * 0b0..Transmit underrun not detected.
+ * 0b1..Transmit underrun detected.
+ */
+#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
+#define I2S_TCSR_SEF_MASK (0x80000U)
+#define I2S_TCSR_SEF_SHIFT (19U)
+/*! SEF - Sync Error Flag
+ * 0b0..Sync error not detected.
+ * 0b1..Frame sync error detected.
+ */
+#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
+#define I2S_TCSR_WSF_MASK (0x100000U)
+#define I2S_TCSR_WSF_SHIFT (20U)
+/*! WSF - Word Start Flag
+ * 0b0..Start of word not detected.
+ * 0b1..Start of word detected.
+ */
+#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
+#define I2S_TCSR_SR_MASK (0x1000000U)
+#define I2S_TCSR_SR_SHIFT (24U)
+/*! SR - Software Reset
+ * 0b0..No effect.
+ * 0b1..Software reset.
+ */
+#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
+#define I2S_TCSR_FR_MASK (0x2000000U)
+#define I2S_TCSR_FR_SHIFT (25U)
+/*! FR - FIFO Reset
+ * 0b0..No effect.
+ * 0b1..FIFO reset.
+ */
+#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
+#define I2S_TCSR_BCE_MASK (0x10000000U)
+#define I2S_TCSR_BCE_SHIFT (28U)
+/*! BCE - Bit Clock Enable
+ * 0b0..Transmit bit clock is disabled.
+ * 0b1..Transmit bit clock is enabled.
+ */
+#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
+#define I2S_TCSR_DBGE_MASK (0x20000000U)
+#define I2S_TCSR_DBGE_SHIFT (29U)
+/*! DBGE - Debug Enable
+ * 0b0..Transmitter is disabled in Debug mode, after completing the current frame.
+ * 0b1..Transmitter is enabled in Debug mode.
+ */
+#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
+#define I2S_TCSR_STOPE_MASK (0x40000000U)
+#define I2S_TCSR_STOPE_SHIFT (30U)
+/*! STOPE - Stop Enable
+ * 0b0..Transmitter disabled in Stop mode.
+ * 0b1..Transmitter enabled in Stop mode.
+ */
+#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
+#define I2S_TCSR_TE_MASK (0x80000000U)
+#define I2S_TCSR_TE_SHIFT (31U)
+/*! TE - Transmitter Enable
+ * 0b0..Transmitter is disabled.
+ * 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
+ */
+#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
+/*! @} */
+
+/*! @name TCR1 - SAI Transmit Configuration 1 Register */
+/*! @{ */
+#define I2S_TCR1_TFW_MASK (0x7U)
+#define I2S_TCR1_TFW_SHIFT (0U)
+#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
+/*! @} */
+
+/*! @name TCR2 - SAI Transmit Configuration 2 Register */
+/*! @{ */
+#define I2S_TCR2_DIV_MASK (0xFFU)
+#define I2S_TCR2_DIV_SHIFT (0U)
+#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK (0x1000000U)
+#define I2S_TCR2_BCD_SHIFT (24U)
+/*! BCD - Bit Clock Direction
+ * 0b0..Bit clock is generated externally in Slave mode.
+ * 0b1..Bit clock is generated internally in Master mode.
+ */
+#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
+#define I2S_TCR2_BCP_MASK (0x2000000U)
+#define I2S_TCR2_BCP_SHIFT (25U)
+/*! BCP - Bit Clock Polarity
+ * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
+ * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
+ */
+#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
+#define I2S_TCR2_MSEL_MASK (0xC000000U)
+#define I2S_TCR2_MSEL_SHIFT (26U)
+/*! MSEL - MCLK Select
+ * 0b00..Bus Clock selected.
+ * 0b01..Master Clock (MCLK) 1 option selected.
+ * 0b10..Master Clock (MCLK) 2 option selected.
+ * 0b11..Master Clock (MCLK) 3 option selected.
+ */
+#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK (0x10000000U)
+#define I2S_TCR2_BCI_SHIFT (28U)
+/*! BCI - Bit Clock Input
+ * 0b0..No effect.
+ * 0b1..Internal logic is clocked as if bit clock was externally generated.
+ */
+#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
+#define I2S_TCR2_BCS_MASK (0x20000000U)
+#define I2S_TCR2_BCS_SHIFT (29U)
+/*! BCS - Bit Clock Swap
+ * 0b0..Use the normal bit clock source.
+ * 0b1..Swap the bit clock source.
+ */
+#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
+#define I2S_TCR2_SYNC_MASK (0xC0000000U)
+#define I2S_TCR2_SYNC_SHIFT (30U)
+/*! SYNC - Synchronous Mode
+ * 0b00..Asynchronous mode.
+ * 0b01..Synchronous with receiver.
+ * 0b10..Synchronous with another SAI transmitter.
+ * 0b11..Synchronous with another SAI receiver.
+ */
+#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
+/*! @} */
+
+/*! @name TCR3 - SAI Transmit Configuration 3 Register */
+/*! @{ */
+#define I2S_TCR3_WDFL_MASK (0x1FU)
+#define I2S_TCR3_WDFL_SHIFT (0U)
+#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK (0x30000U)
+#define I2S_TCR3_TCE_SHIFT (16U)
+/*! TCE - Transmit Channel Enable
+ * 0b00..Transmit data channel N is disabled.
+ * 0b01..Transmit data channel N is enabled.
+ */
+#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
+#define I2S_TCR3_CFR_MASK (0x3000000U)
+#define I2S_TCR3_CFR_SHIFT (24U)
+/*! CFR - Channel FIFO Reset
+ * 0b00..No effect.
+ * 0b01..Transmit data channel N FIFO is reset.
+ */
+#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
+/*! @} */
+
+/*! @name TCR4 - SAI Transmit Configuration 4 Register */
+/*! @{ */
+#define I2S_TCR4_FSD_MASK (0x1U)
+#define I2S_TCR4_FSD_SHIFT (0U)
+/*! FSD - Frame Sync Direction
+ * 0b0..Frame sync is generated externally in Slave mode.
+ * 0b1..Frame sync is generated internally in Master mode.
+ */
+#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
+#define I2S_TCR4_FSP_MASK (0x2U)
+#define I2S_TCR4_FSP_SHIFT (1U)
+/*! FSP - Frame Sync Polarity
+ * 0b0..Frame sync is active high.
+ * 0b1..Frame sync is active low.
+ */
+#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
+#define I2S_TCR4_ONDEM_MASK (0x4U)
+#define I2S_TCR4_ONDEM_SHIFT (2U)
+/*! ONDEM - On Demand Mode
+ * 0b0..Internal frame sync is generated continuously.
+ * 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
+ */
+#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
+#define I2S_TCR4_FSE_MASK (0x8U)
+#define I2S_TCR4_FSE_SHIFT (3U)
+/*! FSE - Frame Sync Early
+ * 0b0..Frame sync asserts with the first bit of the frame.
+ * 0b1..Frame sync asserts one bit before the first bit of the frame.
+ */
+#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
+#define I2S_TCR4_MF_MASK (0x10U)
+#define I2S_TCR4_MF_SHIFT (4U)
+/*! MF - MSB First
+ * 0b0..LSB is transmitted first.
+ * 0b1..MSB is transmitted first.
+ */
+#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
+#define I2S_TCR4_SYWD_MASK (0x1F00U)
+#define I2S_TCR4_SYWD_SHIFT (8U)
+#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK (0x1F0000U)
+#define I2S_TCR4_FRSZ_SHIFT (16U)
+#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
+#define I2S_TCR4_FPACK_MASK (0x3000000U)
+#define I2S_TCR4_FPACK_SHIFT (24U)
+/*! FPACK - FIFO Packing Mode
+ * 0b00..FIFO packing is disabled
+ * 0b01..Reserved
+ * 0b10..8-bit FIFO packing is enabled
+ * 0b11..16-bit FIFO packing is enabled
+ */
+#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
+#define I2S_TCR4_FCOMB_MASK (0xC000000U)
+#define I2S_TCR4_FCOMB_SHIFT (26U)
+/*! FCOMB - FIFO Combine Mode
+ * 0b00..FIFO combine mode disabled.
+ * 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers).
+ * 0b10..FIFO combine mode enabled on FIFO writes (by software).
+ * 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).
+ */
+#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
+#define I2S_TCR4_FCONT_MASK (0x10000000U)
+#define I2S_TCR4_FCONT_SHIFT (28U)
+/*! FCONT - FIFO Continue on Error
+ * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
+ * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
+ */
+#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
+/*! @} */
+
+/*! @name TCR5 - SAI Transmit Configuration 5 Register */
+/*! @{ */
+#define I2S_TCR5_FBT_MASK (0x1F00U)
+#define I2S_TCR5_FBT_SHIFT (8U)
+#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK (0x1F0000U)
+#define I2S_TCR5_W0W_SHIFT (16U)
+#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK (0x1F000000U)
+#define I2S_TCR5_WNW_SHIFT (24U)
+#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
+/*! @} */
+
+/*! @name TDR - SAI Transmit Data Register */
+/*! @{ */
+#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
+#define I2S_TDR_TDR_SHIFT (0U)
+#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
+/*! @} */
+
+/* The count of I2S_TDR */
+#define I2S_TDR_COUNT (2U)
+
+/*! @name TFR - SAI Transmit FIFO Register */
+/*! @{ */
+#define I2S_TFR_RFP_MASK (0xFU)
+#define I2S_TFR_RFP_SHIFT (0U)
+#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
+#define I2S_TFR_WFP_MASK (0xF0000U)
+#define I2S_TFR_WFP_SHIFT (16U)
+#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
+#define I2S_TFR_WCP_MASK (0x80000000U)
+#define I2S_TFR_WCP_SHIFT (31U)
+/*! WCP - Write Channel Pointer
+ * 0b0..No effect.
+ * 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
+ */
+#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
+/*! @} */
+
+/* The count of I2S_TFR */
+#define I2S_TFR_COUNT (2U)
+
+/*! @name TMR - SAI Transmit Mask Register */
+/*! @{ */
+#define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
+#define I2S_TMR_TWM_SHIFT (0U)
+/*! TWM - Transmit Word Mask
+ * 0b00000000000000000000000000000000..Word N is enabled.
+ * 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated when masked.
+ */
+#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
+/*! @} */
+
+/*! @name RCSR - SAI Receive Control Register */
+/*! @{ */
+#define I2S_RCSR_FRDE_MASK (0x1U)
+#define I2S_RCSR_FRDE_SHIFT (0U)
+/*! FRDE - FIFO Request DMA Enable
+ * 0b0..Disables the DMA request.
+ * 0b1..Enables the DMA request.
+ */
+#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
+#define I2S_RCSR_FWDE_MASK (0x2U)
+#define I2S_RCSR_FWDE_SHIFT (1U)
+/*! FWDE - FIFO Warning DMA Enable
+ * 0b0..Disables the DMA request.
+ * 0b1..Enables the DMA request.
+ */
+#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
+#define I2S_RCSR_FRIE_MASK (0x100U)
+#define I2S_RCSR_FRIE_SHIFT (8U)
+/*! FRIE - FIFO Request Interrupt Enable
+ * 0b0..Disables the interrupt.
+ * 0b1..Enables the interrupt.
+ */
+#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
+#define I2S_RCSR_FWIE_MASK (0x200U)
+#define I2S_RCSR_FWIE_SHIFT (9U)
+/*! FWIE - FIFO Warning Interrupt Enable
+ * 0b0..Disables the interrupt.
+ * 0b1..Enables the interrupt.
+ */
+#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
+#define I2S_RCSR_FEIE_MASK (0x400U)
+#define I2S_RCSR_FEIE_SHIFT (10U)
+/*! FEIE - FIFO Error Interrupt Enable
+ * 0b0..Disables the interrupt.
+ * 0b1..Enables the interrupt.
+ */
+#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
+#define I2S_RCSR_SEIE_MASK (0x800U)
+#define I2S_RCSR_SEIE_SHIFT (11U)
+/*! SEIE - Sync Error Interrupt Enable
+ * 0b0..Disables interrupt.
+ * 0b1..Enables interrupt.
+ */
+#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
+#define I2S_RCSR_WSIE_MASK (0x1000U)
+#define I2S_RCSR_WSIE_SHIFT (12U)
+/*! WSIE - Word Start Interrupt Enable
+ * 0b0..Disables interrupt.
+ * 0b1..Enables interrupt.
+ */
+#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
+#define I2S_RCSR_FRF_MASK (0x10000U)
+#define I2S_RCSR_FRF_SHIFT (16U)
+/*! FRF - FIFO Request Flag
+ * 0b0..Receive FIFO watermark not reached.
+ * 0b1..Receive FIFO watermark has been reached.
+ */
+#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
+#define I2S_RCSR_FWF_MASK (0x20000U)
+#define I2S_RCSR_FWF_SHIFT (17U)
+/*! FWF - FIFO Warning Flag
+ * 0b0..No enabled receive FIFO is full.
+ * 0b1..Enabled receive FIFO is full.
+ */
+#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
+#define I2S_RCSR_FEF_MASK (0x40000U)
+#define I2S_RCSR_FEF_SHIFT (18U)
+/*! FEF - FIFO Error Flag
+ * 0b0..Receive overflow not detected.
+ * 0b1..Receive overflow detected.
+ */
+#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
+#define I2S_RCSR_SEF_MASK (0x80000U)
+#define I2S_RCSR_SEF_SHIFT (19U)
+/*! SEF - Sync Error Flag
+ * 0b0..Sync error not detected.
+ * 0b1..Frame sync error detected.
+ */
+#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
+#define I2S_RCSR_WSF_MASK (0x100000U)
+#define I2S_RCSR_WSF_SHIFT (20U)
+/*! WSF - Word Start Flag
+ * 0b0..Start of word not detected.
+ * 0b1..Start of word detected.
+ */
+#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
+#define I2S_RCSR_SR_MASK (0x1000000U)
+#define I2S_RCSR_SR_SHIFT (24U)
+/*! SR - Software Reset
+ * 0b0..No effect.
+ * 0b1..Software reset.
+ */
+#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
+#define I2S_RCSR_FR_MASK (0x2000000U)
+#define I2S_RCSR_FR_SHIFT (25U)
+/*! FR - FIFO Reset
+ * 0b0..No effect.
+ * 0b1..FIFO reset.
+ */
+#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
+#define I2S_RCSR_BCE_MASK (0x10000000U)
+#define I2S_RCSR_BCE_SHIFT (28U)
+/*! BCE - Bit Clock Enable
+ * 0b0..Receive bit clock is disabled.
+ * 0b1..Receive bit clock is enabled.
+ */
+#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
+#define I2S_RCSR_DBGE_MASK (0x20000000U)
+#define I2S_RCSR_DBGE_SHIFT (29U)
+/*! DBGE - Debug Enable
+ * 0b0..Receiver is disabled in Debug mode, after completing the current frame.
+ * 0b1..Receiver is enabled in Debug mode.
+ */
+#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
+#define I2S_RCSR_STOPE_MASK (0x40000000U)
+#define I2S_RCSR_STOPE_SHIFT (30U)
+/*! STOPE - Stop Enable
+ * 0b0..Receiver disabled in Stop mode.
+ * 0b1..Receiver enabled in Stop mode.
+ */
+#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
+#define I2S_RCSR_RE_MASK (0x80000000U)
+#define I2S_RCSR_RE_SHIFT (31U)
+/*! RE - Receiver Enable
+ * 0b0..Receiver is disabled.
+ * 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
+ */
+#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
+/*! @} */
+
+/*! @name RCR1 - SAI Receive Configuration 1 Register */
+/*! @{ */
+#define I2S_RCR1_RFW_MASK (0x7U)
+#define I2S_RCR1_RFW_SHIFT (0U)
+#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
+/*! @} */
+
+/*! @name RCR2 - SAI Receive Configuration 2 Register */
+/*! @{ */
+#define I2S_RCR2_DIV_MASK (0xFFU)
+#define I2S_RCR2_DIV_SHIFT (0U)
+#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK (0x1000000U)
+#define I2S_RCR2_BCD_SHIFT (24U)
+/*! BCD - Bit Clock Direction
+ * 0b0..Bit clock is generated externally in Slave mode.
+ * 0b1..Bit clock is generated internally in Master mode.
+ */
+#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
+#define I2S_RCR2_BCP_MASK (0x2000000U)
+#define I2S_RCR2_BCP_SHIFT (25U)
+/*! BCP - Bit Clock Polarity
+ * 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
+ * 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
+ */
+#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
+#define I2S_RCR2_MSEL_MASK (0xC000000U)
+#define I2S_RCR2_MSEL_SHIFT (26U)
+/*! MSEL - MCLK Select
+ * 0b00..Bus Clock selected.
+ * 0b01..Master Clock (MCLK) 1 option selected.
+ * 0b10..Master Clock (MCLK) 2 option selected.
+ * 0b11..Master Clock (MCLK) 3 option selected.
+ */
+#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK (0x10000000U)
+#define I2S_RCR2_BCI_SHIFT (28U)
+/*! BCI - Bit Clock Input
+ * 0b0..No effect.
+ * 0b1..Internal logic is clocked as if bit clock was externally generated.
+ */
+#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
+#define I2S_RCR2_BCS_MASK (0x20000000U)
+#define I2S_RCR2_BCS_SHIFT (29U)
+/*! BCS - Bit Clock Swap
+ * 0b0..Use the normal bit clock source.
+ * 0b1..Swap the bit clock source.
+ */
+#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
+#define I2S_RCR2_SYNC_MASK (0xC0000000U)
+#define I2S_RCR2_SYNC_SHIFT (30U)
+/*! SYNC - Synchronous Mode
+ * 0b00..Asynchronous mode.
+ * 0b01..Synchronous with transmitter.
+ * 0b10..Synchronous with another SAI receiver.
+ * 0b11..Synchronous with another SAI transmitter.
+ */
+#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
+/*! @} */
+
+/*! @name RCR3 - SAI Receive Configuration 3 Register */
+/*! @{ */
+#define I2S_RCR3_WDFL_MASK (0x1FU)
+#define I2S_RCR3_WDFL_SHIFT (0U)
+#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK (0x30000U)
+#define I2S_RCR3_RCE_SHIFT (16U)
+/*! RCE - Receive Channel Enable
+ * 0b00..Receive data channel N is disabled.
+ * 0b01..Receive data channel N is enabled.
+ */
+#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
+#define I2S_RCR3_CFR_MASK (0x3000000U)
+#define I2S_RCR3_CFR_SHIFT (24U)
+/*! CFR - Channel FIFO Reset
+ * 0b00..No effect.
+ * 0b01..Receive data channel N FIFO is reset.
+ */
+#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
+/*! @} */
+
+/*! @name RCR4 - SAI Receive Configuration 4 Register */
+/*! @{ */
+#define I2S_RCR4_FSD_MASK (0x1U)
+#define I2S_RCR4_FSD_SHIFT (0U)
+/*! FSD - Frame Sync Direction
+ * 0b0..Frame Sync is generated externally in Slave mode.
+ * 0b1..Frame Sync is generated internally in Master mode.
+ */
+#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
+#define I2S_RCR4_FSP_MASK (0x2U)
+#define I2S_RCR4_FSP_SHIFT (1U)
+/*! FSP - Frame Sync Polarity
+ * 0b0..Frame sync is active high.
+ * 0b1..Frame sync is active low.
+ */
+#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
+#define I2S_RCR4_ONDEM_MASK (0x4U)
+#define I2S_RCR4_ONDEM_SHIFT (2U)
+/*! ONDEM - On Demand Mode
+ * 0b0..Internal frame sync is generated continuously.
+ * 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
+ */
+#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
+#define I2S_RCR4_FSE_MASK (0x8U)
+#define I2S_RCR4_FSE_SHIFT (3U)
+/*! FSE - Frame Sync Early
+ * 0b0..Frame sync asserts with the first bit of the frame.
+ * 0b1..Frame sync asserts one bit before the first bit of the frame.
+ */
+#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
+#define I2S_RCR4_MF_MASK (0x10U)
+#define I2S_RCR4_MF_SHIFT (4U)
+/*! MF - MSB First
+ * 0b0..LSB is received first.
+ * 0b1..MSB is received first.
+ */
+#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
+#define I2S_RCR4_SYWD_MASK (0x1F00U)
+#define I2S_RCR4_SYWD_SHIFT (8U)
+#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK (0x1F0000U)
+#define I2S_RCR4_FRSZ_SHIFT (16U)
+#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
+#define I2S_RCR4_FPACK_MASK (0x3000000U)
+#define I2S_RCR4_FPACK_SHIFT (24U)
+/*! FPACK - FIFO Packing Mode
+ * 0b00..FIFO packing is disabled
+ * 0b01..Reserved.
+ * 0b10..8-bit FIFO packing is enabled
+ * 0b11..16-bit FIFO packing is enabled
+ */
+#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
+#define I2S_RCR4_FCOMB_MASK (0xC000000U)
+#define I2S_RCR4_FCOMB_SHIFT (26U)
+/*! FCOMB - FIFO Combine Mode
+ * 0b00..FIFO combine mode disabled.
+ * 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers).
+ * 0b10..FIFO combine mode enabled on FIFO reads (by software).
+ * 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).
+ */
+#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
+#define I2S_RCR4_FCONT_MASK (0x10000000U)
+#define I2S_RCR4_FCONT_SHIFT (28U)
+/*! FCONT - FIFO Continue on Error
+ * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
+ * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
+ */
+#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
+/*! @} */
+
+/*! @name RCR5 - SAI Receive Configuration 5 Register */
+/*! @{ */
+#define I2S_RCR5_FBT_MASK (0x1F00U)
+#define I2S_RCR5_FBT_SHIFT (8U)
+#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK (0x1F0000U)
+#define I2S_RCR5_W0W_SHIFT (16U)
+#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK (0x1F000000U)
+#define I2S_RCR5_WNW_SHIFT (24U)
+#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
+/*! @} */
+
+/*! @name RDR - SAI Receive Data Register */
+/*! @{ */
+#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
+#define I2S_RDR_RDR_SHIFT (0U)
+#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
+/*! @} */
+
+/* The count of I2S_RDR */
+#define I2S_RDR_COUNT (2U)
+
+/*! @name RFR - SAI Receive FIFO Register */
+/*! @{ */
+#define I2S_RFR_RFP_MASK (0xFU)
+#define I2S_RFR_RFP_SHIFT (0U)
+#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
+#define I2S_RFR_RCP_MASK (0x8000U)
+#define I2S_RFR_RCP_SHIFT (15U)
+/*! RCP - Receive Channel Pointer
+ * 0b0..No effect.
+ * 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
+ */
+#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
+#define I2S_RFR_WFP_MASK (0xF0000U)
+#define I2S_RFR_WFP_SHIFT (16U)
+#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
+/*! @} */
+
+/* The count of I2S_RFR */
+#define I2S_RFR_COUNT (2U)
+
+/*! @name RMR - SAI Receive Mask Register */
+/*! @{ */
+#define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
+#define I2S_RMR_RWM_SHIFT (0U)
+/*! RWM - Receive Word Mask
+ * 0b00000000000000000000000000000000..Word N is enabled.
+ * 0b00000000000000000000000000000001..Word N is masked.
+ */
+#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
+/*! @} */
+
+/*! @name MCR - SAI MCLK Control Register */
+/*! @{ */
+#define I2S_MCR_MICS_MASK (0x3000000U)
+#define I2S_MCR_MICS_SHIFT (24U)
+/*! MICS - MCLK Input Clock Select
+ * 0b00..MCLK divider input clock 0 is selected.
+ * 0b01..MCLK divider input clock 1 is selected.
+ * 0b10..MCLK divider input clock 2 is selected.
+ * 0b11..MCLK divider input clock 3 is selected.
+ */
+#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK (0x40000000U)
+#define I2S_MCR_MOE_SHIFT (30U)
+/*! MOE - MCLK Output Enable
+ * 0b0..MCLK signal pin is configured as an input that bypasses the MCLK divider.
+ * 0b1..MCLK signal pin is configured as an output from the MCLK divider and the MCLK divider is enabled.
+ */
+#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
+#define I2S_MCR_DUF_MASK (0x80000000U)
+#define I2S_MCR_DUF_SHIFT (31U)
+/*! DUF - Divider Update Flag
+ * 0b0..MCLK divider ratio is not being updated currently.
+ * 0b1..MCLK divider ratio is updating on-the-fly. Further updates to the MCLK divider ratio are blocked while this flag remains set.
+ */
+#define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
+/*! @} */
+
+/*! @name MDR - SAI MCLK Divide Register */
+/*! @{ */
+#define I2S_MDR_DIVIDE_MASK (0xFFFU)
+#define I2S_MDR_DIVIDE_SHIFT (0U)
+#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK (0xFF000U)
+#define I2S_MDR_FRACT_SHIFT (12U)
+#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0 ((I2S_Type *)I2S0_BASE)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS { I2S0_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS { I2S0 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_RX_IRQS { I2S0_Rx_IRQn }
+#define I2S_TX_IRQS { I2S0_Tx_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
+ __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
+ __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
+ __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
+ __IO uint8_t PE5; /**< LLWU Pin Enable 5 register, offset: 0x4 */
+ __IO uint8_t PE6; /**< LLWU Pin Enable 6 register, offset: 0x5 */
+ __IO uint8_t PE7; /**< LLWU Pin Enable 7 register, offset: 0x6 */
+ __IO uint8_t PE8; /**< LLWU Pin Enable 8 register, offset: 0x7 */
+ __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x8 */
+ __IO uint8_t PF1; /**< LLWU Pin Flag 1 register, offset: 0x9 */
+ __IO uint8_t PF2; /**< LLWU Pin Flag 2 register, offset: 0xA */
+ __IO uint8_t PF3; /**< LLWU Pin Flag 3 register, offset: 0xB */
+ __IO uint8_t PF4; /**< LLWU Pin Flag 4 register, offset: 0xC */
+ __I uint8_t MF5; /**< LLWU Module Flag 5 register, offset: 0xD */
+ __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0xE */
+ __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0xF */
+ __IO uint8_t FILT3; /**< LLWU Pin Filter 3 register, offset: 0x10 */
+ __IO uint8_t FILT4; /**< LLWU Pin Filter 4 register, offset: 0x11 */
+} LLWU_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/*! @name PE1 - LLWU Pin Enable 1 register */
+/*! @{ */
+#define LLWU_PE1_WUPE0_MASK (0x3U)
+#define LLWU_PE1_WUPE0_SHIFT (0U)
+/*! WUPE0 - Wakeup Pin Enable For LLWU_P0
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK (0xCU)
+#define LLWU_PE1_WUPE1_SHIFT (2U)
+/*! WUPE1 - Wakeup Pin Enable For LLWU_P1
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK (0x30U)
+#define LLWU_PE1_WUPE2_SHIFT (4U)
+/*! WUPE2 - Wakeup Pin Enable For LLWU_P2
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK (0xC0U)
+#define LLWU_PE1_WUPE3_SHIFT (6U)
+/*! WUPE3 - Wakeup Pin Enable For LLWU_P3
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
+/*! @} */
+
+/*! @name PE2 - LLWU Pin Enable 2 register */
+/*! @{ */
+#define LLWU_PE2_WUPE4_MASK (0x3U)
+#define LLWU_PE2_WUPE4_SHIFT (0U)
+/*! WUPE4 - Wakeup Pin Enable For LLWU_P4
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK (0xCU)
+#define LLWU_PE2_WUPE5_SHIFT (2U)
+/*! WUPE5 - Wakeup Pin Enable For LLWU_P5
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK (0x30U)
+#define LLWU_PE2_WUPE6_SHIFT (4U)
+/*! WUPE6 - Wakeup Pin Enable For LLWU_P6
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK (0xC0U)
+#define LLWU_PE2_WUPE7_SHIFT (6U)
+/*! WUPE7 - Wakeup Pin Enable For LLWU_P7
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
+/*! @} */
+
+/*! @name PE3 - LLWU Pin Enable 3 register */
+/*! @{ */
+#define LLWU_PE3_WUPE8_MASK (0x3U)
+#define LLWU_PE3_WUPE8_SHIFT (0U)
+/*! WUPE8 - Wakeup Pin Enable For LLWU_P8
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK (0xCU)
+#define LLWU_PE3_WUPE9_SHIFT (2U)
+/*! WUPE9 - Wakeup Pin Enable For LLWU_P9
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK (0x30U)
+#define LLWU_PE3_WUPE10_SHIFT (4U)
+/*! WUPE10 - Wakeup Pin Enable For LLWU_P10
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK (0xC0U)
+#define LLWU_PE3_WUPE11_SHIFT (6U)
+/*! WUPE11 - Wakeup Pin Enable For LLWU_P11
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
+/*! @} */
+
+/*! @name PE4 - LLWU Pin Enable 4 register */
+/*! @{ */
+#define LLWU_PE4_WUPE12_MASK (0x3U)
+#define LLWU_PE4_WUPE12_SHIFT (0U)
+/*! WUPE12 - Wakeup Pin Enable For LLWU_P12
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK (0xCU)
+#define LLWU_PE4_WUPE13_SHIFT (2U)
+/*! WUPE13 - Wakeup Pin Enable For LLWU_P13
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK (0x30U)
+#define LLWU_PE4_WUPE14_SHIFT (4U)
+/*! WUPE14 - Wakeup Pin Enable For LLWU_P14
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK (0xC0U)
+#define LLWU_PE4_WUPE15_SHIFT (6U)
+/*! WUPE15 - Wakeup Pin Enable For LLWU_P15
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
+/*! @} */
+
+/*! @name PE5 - LLWU Pin Enable 5 register */
+/*! @{ */
+#define LLWU_PE5_WUPE16_MASK (0x3U)
+#define LLWU_PE5_WUPE16_SHIFT (0U)
+/*! WUPE16 - Wakeup Pin Enable For LLWU_P16
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE5_WUPE16(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE16_SHIFT)) & LLWU_PE5_WUPE16_MASK)
+#define LLWU_PE5_WUPE17_MASK (0xCU)
+#define LLWU_PE5_WUPE17_SHIFT (2U)
+/*! WUPE17 - Wakeup Pin Enable For LLWU_P17
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE5_WUPE17(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE17_SHIFT)) & LLWU_PE5_WUPE17_MASK)
+#define LLWU_PE5_WUPE18_MASK (0x30U)
+#define LLWU_PE5_WUPE18_SHIFT (4U)
+/*! WUPE18 - Wakeup Pin Enable For LLWU_P18
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE5_WUPE18(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE18_SHIFT)) & LLWU_PE5_WUPE18_MASK)
+#define LLWU_PE5_WUPE19_MASK (0xC0U)
+#define LLWU_PE5_WUPE19_SHIFT (6U)
+/*! WUPE19 - Wakeup Pin Enable For LLWU_P19
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE5_WUPE19(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE19_SHIFT)) & LLWU_PE5_WUPE19_MASK)
+/*! @} */
+
+/*! @name PE6 - LLWU Pin Enable 6 register */
+/*! @{ */
+#define LLWU_PE6_WUPE20_MASK (0x3U)
+#define LLWU_PE6_WUPE20_SHIFT (0U)
+/*! WUPE20 - Wakeup Pin Enable For LLWU_P20
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE6_WUPE20(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE20_SHIFT)) & LLWU_PE6_WUPE20_MASK)
+#define LLWU_PE6_WUPE21_MASK (0xCU)
+#define LLWU_PE6_WUPE21_SHIFT (2U)
+/*! WUPE21 - Wakeup Pin Enable For LLWU_P21
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE6_WUPE21(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE21_SHIFT)) & LLWU_PE6_WUPE21_MASK)
+#define LLWU_PE6_WUPE22_MASK (0x30U)
+#define LLWU_PE6_WUPE22_SHIFT (4U)
+/*! WUPE22 - Wakeup Pin Enable For LLWU_P22
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE6_WUPE22(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE22_SHIFT)) & LLWU_PE6_WUPE22_MASK)
+#define LLWU_PE6_WUPE23_MASK (0xC0U)
+#define LLWU_PE6_WUPE23_SHIFT (6U)
+/*! WUPE23 - Wakeup Pin Enable For LLWU_P23
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE6_WUPE23(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE23_SHIFT)) & LLWU_PE6_WUPE23_MASK)
+/*! @} */
+
+/*! @name PE7 - LLWU Pin Enable 7 register */
+/*! @{ */
+#define LLWU_PE7_WUPE24_MASK (0x3U)
+#define LLWU_PE7_WUPE24_SHIFT (0U)
+/*! WUPE24 - Wakeup Pin Enable For LLWU_P24
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE7_WUPE24(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE24_SHIFT)) & LLWU_PE7_WUPE24_MASK)
+#define LLWU_PE7_WUPE25_MASK (0xCU)
+#define LLWU_PE7_WUPE25_SHIFT (2U)
+/*! WUPE25 - Wakeup Pin Enable For LLWU_P25
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE7_WUPE25(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE25_SHIFT)) & LLWU_PE7_WUPE25_MASK)
+#define LLWU_PE7_WUPE26_MASK (0x30U)
+#define LLWU_PE7_WUPE26_SHIFT (4U)
+/*! WUPE26 - Wakeup Pin Enable For LLWU_P26
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE7_WUPE26(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE26_SHIFT)) & LLWU_PE7_WUPE26_MASK)
+#define LLWU_PE7_WUPE27_MASK (0xC0U)
+#define LLWU_PE7_WUPE27_SHIFT (6U)
+/*! WUPE27 - Wakeup Pin Enable For LLWU_P27
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE7_WUPE27(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE27_SHIFT)) & LLWU_PE7_WUPE27_MASK)
+/*! @} */
+
+/*! @name PE8 - LLWU Pin Enable 8 register */
+/*! @{ */
+#define LLWU_PE8_WUPE28_MASK (0x3U)
+#define LLWU_PE8_WUPE28_SHIFT (0U)
+/*! WUPE28 - Wakeup Pin Enable For LLWU_P28
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE8_WUPE28(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE28_SHIFT)) & LLWU_PE8_WUPE28_MASK)
+#define LLWU_PE8_WUPE29_MASK (0xCU)
+#define LLWU_PE8_WUPE29_SHIFT (2U)
+/*! WUPE29 - Wakeup Pin Enable For LLWU_P29
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE8_WUPE29(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE29_SHIFT)) & LLWU_PE8_WUPE29_MASK)
+#define LLWU_PE8_WUPE30_MASK (0x30U)
+#define LLWU_PE8_WUPE30_SHIFT (4U)
+/*! WUPE30 - Wakeup Pin Enable For LLWU_P30
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE8_WUPE30(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE30_SHIFT)) & LLWU_PE8_WUPE30_MASK)
+#define LLWU_PE8_WUPE31_MASK (0xC0U)
+#define LLWU_PE8_WUPE31_SHIFT (6U)
+/*! WUPE31 - Wakeup Pin Enable For LLWU_P31
+ * 0b00..External input pin disabled as wakeup input
+ * 0b01..External input pin enabled with rising edge detection
+ * 0b10..External input pin enabled with falling edge detection
+ * 0b11..External input pin enabled with any change detection
+ */
+#define LLWU_PE8_WUPE31(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE31_SHIFT)) & LLWU_PE8_WUPE31_MASK)
+/*! @} */
+
+/*! @name ME - LLWU Module Enable register */
+/*! @{ */
+#define LLWU_ME_WUME0_MASK (0x1U)
+#define LLWU_ME_WUME0_SHIFT (0U)
+/*! WUME0 - Wakeup Module Enable For Module 0
+ * 0b0..Internal module flag not used as wakeup source
+ * 0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
+#define LLWU_ME_WUME1_MASK (0x2U)
+#define LLWU_ME_WUME1_SHIFT (1U)
+/*! WUME1 - Wakeup Module Enable for Module 1
+ * 0b0..Internal module flag not used as wakeup source
+ * 0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
+#define LLWU_ME_WUME2_MASK (0x4U)
+#define LLWU_ME_WUME2_SHIFT (2U)
+/*! WUME2 - Wakeup Module Enable For Module 2
+ * 0b0..Internal module flag not used as wakeup source
+ * 0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
+#define LLWU_ME_WUME3_MASK (0x8U)
+#define LLWU_ME_WUME3_SHIFT (3U)
+/*! WUME3 - Wakeup Module Enable For Module 3
+ * 0b0..Internal module flag not used as wakeup source
+ * 0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
+#define LLWU_ME_WUME4_MASK (0x10U)
+#define LLWU_ME_WUME4_SHIFT (4U)
+/*! WUME4 - Wakeup Module Enable For Module 4
+ * 0b0..Internal module flag not used as wakeup source
+ * 0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
+#define LLWU_ME_WUME5_MASK (0x20U)
+#define LLWU_ME_WUME5_SHIFT (5U)
+/*! WUME5 - Wakeup Module Enable For Module 5
+ * 0b0..Internal module flag not used as wakeup source
+ * 0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
+#define LLWU_ME_WUME6_MASK (0x40U)
+#define LLWU_ME_WUME6_SHIFT (6U)
+/*! WUME6 - Wakeup Module Enable For Module 6
+ * 0b0..Internal module flag not used as wakeup source
+ * 0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
+#define LLWU_ME_WUME7_MASK (0x80U)
+#define LLWU_ME_WUME7_SHIFT (7U)
+/*! WUME7 - Wakeup Module Enable For Module 7
+ * 0b0..Internal module flag not used as wakeup source
+ * 0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
+/*! @} */
+
+/*! @name PF1 - LLWU Pin Flag 1 register */
+/*! @{ */
+#define LLWU_PF1_WUF0_MASK (0x1U)
+#define LLWU_PF1_WUF0_SHIFT (0U)
+/*! WUF0 - Wakeup Flag For LLWU_P0
+ * 0b0..LLWU_P0 input was not a wakeup source
+ * 0b1..LLWU_P0 input was a wakeup source
+ */
+#define LLWU_PF1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF0_SHIFT)) & LLWU_PF1_WUF0_MASK)
+#define LLWU_PF1_WUF1_MASK (0x2U)
+#define LLWU_PF1_WUF1_SHIFT (1U)
+/*! WUF1 - Wakeup Flag For LLWU_P1
+ * 0b0..LLWU_P1 input was not a wakeup source
+ * 0b1..LLWU_P1 input was a wakeup source
+ */
+#define LLWU_PF1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF1_SHIFT)) & LLWU_PF1_WUF1_MASK)
+#define LLWU_PF1_WUF2_MASK (0x4U)
+#define LLWU_PF1_WUF2_SHIFT (2U)
+/*! WUF2 - Wakeup Flag For LLWU_P2
+ * 0b0..LLWU_P2 input was not a wakeup source
+ * 0b1..LLWU_P2 input was a wakeup source
+ */
+#define LLWU_PF1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF2_SHIFT)) & LLWU_PF1_WUF2_MASK)
+#define LLWU_PF1_WUF3_MASK (0x8U)
+#define LLWU_PF1_WUF3_SHIFT (3U)
+/*! WUF3 - Wakeup Flag For LLWU_P3
+ * 0b0..LLWU_P3 input was not a wakeup source
+ * 0b1..LLWU_P3 input was a wakeup source
+ */
+#define LLWU_PF1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF3_SHIFT)) & LLWU_PF1_WUF3_MASK)
+#define LLWU_PF1_WUF4_MASK (0x10U)
+#define LLWU_PF1_WUF4_SHIFT (4U)
+/*! WUF4 - Wakeup Flag For LLWU_P4
+ * 0b0..LLWU_P4 input was not a wakeup source
+ * 0b1..LLWU_P4 input was a wakeup source
+ */
+#define LLWU_PF1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF4_SHIFT)) & LLWU_PF1_WUF4_MASK)
+#define LLWU_PF1_WUF5_MASK (0x20U)
+#define LLWU_PF1_WUF5_SHIFT (5U)
+/*! WUF5 - Wakeup Flag For LLWU_P5
+ * 0b0..LLWU_P5 input was not a wakeup source
+ * 0b1..LLWU_P5 input was a wakeup source
+ */
+#define LLWU_PF1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF5_SHIFT)) & LLWU_PF1_WUF5_MASK)
+#define LLWU_PF1_WUF6_MASK (0x40U)
+#define LLWU_PF1_WUF6_SHIFT (6U)
+/*! WUF6 - Wakeup Flag For LLWU_P6
+ * 0b0..LLWU_P6 input was not a wakeup source
+ * 0b1..LLWU_P6 input was a wakeup source
+ */
+#define LLWU_PF1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF6_SHIFT)) & LLWU_PF1_WUF6_MASK)
+#define LLWU_PF1_WUF7_MASK (0x80U)
+#define LLWU_PF1_WUF7_SHIFT (7U)
+/*! WUF7 - Wakeup Flag For LLWU_P7
+ * 0b0..LLWU_P7 input was not a wakeup source
+ * 0b1..LLWU_P7 input was a wakeup source
+ */
+#define LLWU_PF1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF7_SHIFT)) & LLWU_PF1_WUF7_MASK)
+/*! @} */
+
+/*! @name PF2 - LLWU Pin Flag 2 register */
+/*! @{ */
+#define LLWU_PF2_WUF8_MASK (0x1U)
+#define LLWU_PF2_WUF8_SHIFT (0U)
+/*! WUF8 - Wakeup Flag For LLWU_P8
+ * 0b0..LLWU_P8 input was not a wakeup source
+ * 0b1..LLWU_P8 input was a wakeup source
+ */
+#define LLWU_PF2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF8_SHIFT)) & LLWU_PF2_WUF8_MASK)
+#define LLWU_PF2_WUF9_MASK (0x2U)
+#define LLWU_PF2_WUF9_SHIFT (1U)
+/*! WUF9 - Wakeup Flag For LLWU_P9
+ * 0b0..LLWU_P9 input was not a wakeup source
+ * 0b1..LLWU_P9 input was a wakeup source
+ */
+#define LLWU_PF2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF9_SHIFT)) & LLWU_PF2_WUF9_MASK)
+#define LLWU_PF2_WUF10_MASK (0x4U)
+#define LLWU_PF2_WUF10_SHIFT (2U)
+/*! WUF10 - Wakeup Flag For LLWU_P10
+ * 0b0..LLWU_P10 input was not a wakeup source
+ * 0b1..LLWU_P10 input was a wakeup source
+ */
+#define LLWU_PF2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF10_SHIFT)) & LLWU_PF2_WUF10_MASK)
+#define LLWU_PF2_WUF11_MASK (0x8U)
+#define LLWU_PF2_WUF11_SHIFT (3U)
+/*! WUF11 - Wakeup Flag For LLWU_P11
+ * 0b0..LLWU_P11 input was not a wakeup source
+ * 0b1..LLWU_P11 input was a wakeup source
+ */
+#define LLWU_PF2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF11_SHIFT)) & LLWU_PF2_WUF11_MASK)
+#define LLWU_PF2_WUF12_MASK (0x10U)
+#define LLWU_PF2_WUF12_SHIFT (4U)
+/*! WUF12 - Wakeup Flag For LLWU_P12
+ * 0b0..LLWU_P12 input was not a wakeup source
+ * 0b1..LLWU_P12 input was a wakeup source
+ */
+#define LLWU_PF2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF12_SHIFT)) & LLWU_PF2_WUF12_MASK)
+#define LLWU_PF2_WUF13_MASK (0x20U)
+#define LLWU_PF2_WUF13_SHIFT (5U)
+/*! WUF13 - Wakeup Flag For LLWU_P13
+ * 0b0..LLWU_P13 input was not a wakeup source
+ * 0b1..LLWU_P13 input was a wakeup source
+ */
+#define LLWU_PF2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF13_SHIFT)) & LLWU_PF2_WUF13_MASK)
+#define LLWU_PF2_WUF14_MASK (0x40U)
+#define LLWU_PF2_WUF14_SHIFT (6U)
+/*! WUF14 - Wakeup Flag For LLWU_P14
+ * 0b0..LLWU_P14 input was not a wakeup source
+ * 0b1..LLWU_P14 input was a wakeup source
+ */
+#define LLWU_PF2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF14_SHIFT)) & LLWU_PF2_WUF14_MASK)
+#define LLWU_PF2_WUF15_MASK (0x80U)
+#define LLWU_PF2_WUF15_SHIFT (7U)
+/*! WUF15 - Wakeup Flag For LLWU_P15
+ * 0b0..LLWU_P15 input was not a wakeup source
+ * 0b1..LLWU_P15 input was a wakeup source
+ */
+#define LLWU_PF2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF15_SHIFT)) & LLWU_PF2_WUF15_MASK)
+/*! @} */
+
+/*! @name PF3 - LLWU Pin Flag 3 register */
+/*! @{ */
+#define LLWU_PF3_WUF16_MASK (0x1U)
+#define LLWU_PF3_WUF16_SHIFT (0U)
+/*! WUF16 - Wakeup Flag For LLWU_P16
+ * 0b0..LLWU_P16 input was not a wakeup source
+ * 0b1..LLWU_P16 input was a wakeup source
+ */
+#define LLWU_PF3_WUF16(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF16_SHIFT)) & LLWU_PF3_WUF16_MASK)
+#define LLWU_PF3_WUF17_MASK (0x2U)
+#define LLWU_PF3_WUF17_SHIFT (1U)
+/*! WUF17 - Wakeup Flag For LLWU_P17
+ * 0b0..LLWU_P17 input was not a wakeup source
+ * 0b1..LLWU_P17 input was a wakeup source
+ */
+#define LLWU_PF3_WUF17(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF17_SHIFT)) & LLWU_PF3_WUF17_MASK)
+#define LLWU_PF3_WUF18_MASK (0x4U)
+#define LLWU_PF3_WUF18_SHIFT (2U)
+/*! WUF18 - Wakeup Flag For LLWU_P18
+ * 0b0..LLWU_P18 input was not a wakeup source
+ * 0b1..LLWU_P18 input was a wakeup source
+ */
+#define LLWU_PF3_WUF18(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF18_SHIFT)) & LLWU_PF3_WUF18_MASK)
+#define LLWU_PF3_WUF19_MASK (0x8U)
+#define LLWU_PF3_WUF19_SHIFT (3U)
+/*! WUF19 - Wakeup Flag For LLWU_P19
+ * 0b0..LLWU_P19 input was not a wakeup source
+ * 0b1..LLWU_P19 input was a wakeup source
+ */
+#define LLWU_PF3_WUF19(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF19_SHIFT)) & LLWU_PF3_WUF19_MASK)
+#define LLWU_PF3_WUF20_MASK (0x10U)
+#define LLWU_PF3_WUF20_SHIFT (4U)
+/*! WUF20 - Wakeup Flag For LLWU_P20
+ * 0b0..LLWU_P20 input was not a wakeup source
+ * 0b1..LLWU_P20 input was a wakeup source
+ */
+#define LLWU_PF3_WUF20(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF20_SHIFT)) & LLWU_PF3_WUF20_MASK)
+#define LLWU_PF3_WUF21_MASK (0x20U)
+#define LLWU_PF3_WUF21_SHIFT (5U)
+/*! WUF21 - Wakeup Flag For LLWU_P21
+ * 0b0..LLWU_P21 input was not a wakeup source
+ * 0b1..LLWU_P21 input was a wakeup source
+ */
+#define LLWU_PF3_WUF21(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF21_SHIFT)) & LLWU_PF3_WUF21_MASK)
+#define LLWU_PF3_WUF22_MASK (0x40U)
+#define LLWU_PF3_WUF22_SHIFT (6U)
+/*! WUF22 - Wakeup Flag For LLWU_P22
+ * 0b0..LLWU_P22 input was not a wakeup source
+ * 0b1..LLWU_P22 input was a wakeup source
+ */
+#define LLWU_PF3_WUF22(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF22_SHIFT)) & LLWU_PF3_WUF22_MASK)
+#define LLWU_PF3_WUF23_MASK (0x80U)
+#define LLWU_PF3_WUF23_SHIFT (7U)
+/*! WUF23 - Wakeup Flag For LLWU_P23
+ * 0b0..LLWU_P23 input was not a wakeup source
+ * 0b1..LLWU_P23 input was a wakeup source
+ */
+#define LLWU_PF3_WUF23(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF23_SHIFT)) & LLWU_PF3_WUF23_MASK)
+/*! @} */
+
+/*! @name PF4 - LLWU Pin Flag 4 register */
+/*! @{ */
+#define LLWU_PF4_WUF24_MASK (0x1U)
+#define LLWU_PF4_WUF24_SHIFT (0U)
+/*! WUF24 - Wakeup Flag For LLWU_P24
+ * 0b0..LLWU_P24 input was not a wakeup source
+ * 0b1..LLWU_P24 input was a wakeup source
+ */
+#define LLWU_PF4_WUF24(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF24_SHIFT)) & LLWU_PF4_WUF24_MASK)
+#define LLWU_PF4_WUF25_MASK (0x2U)
+#define LLWU_PF4_WUF25_SHIFT (1U)
+/*! WUF25 - Wakeup Flag For LLWU_P25
+ * 0b0..LLWU_P25 input was not a wakeup source
+ * 0b1..LLWU_P25 input was a wakeup source
+ */
+#define LLWU_PF4_WUF25(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF25_SHIFT)) & LLWU_PF4_WUF25_MASK)
+#define LLWU_PF4_WUF26_MASK (0x4U)
+#define LLWU_PF4_WUF26_SHIFT (2U)
+/*! WUF26 - Wakeup Flag For LLWU_P26
+ * 0b0..LLWU_P26 input was not a wakeup source
+ * 0b1..LLWU_P26 input was a wakeup source
+ */
+#define LLWU_PF4_WUF26(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF26_SHIFT)) & LLWU_PF4_WUF26_MASK)
+#define LLWU_PF4_WUF27_MASK (0x8U)
+#define LLWU_PF4_WUF27_SHIFT (3U)
+/*! WUF27 - Wakeup Flag For LLWU_P27
+ * 0b0..LLWU_P27 input was not a wakeup source
+ * 0b1..LLWU_P27 input was a wakeup source
+ */
+#define LLWU_PF4_WUF27(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF27_SHIFT)) & LLWU_PF4_WUF27_MASK)
+#define LLWU_PF4_WUF28_MASK (0x10U)
+#define LLWU_PF4_WUF28_SHIFT (4U)
+/*! WUF28 - Wakeup Flag For LLWU_P28
+ * 0b0..LLWU_P28 input was not a wakeup source
+ * 0b1..LLWU_P28 input was a wakeup source
+ */
+#define LLWU_PF4_WUF28(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF28_SHIFT)) & LLWU_PF4_WUF28_MASK)
+#define LLWU_PF4_WUF29_MASK (0x20U)
+#define LLWU_PF4_WUF29_SHIFT (5U)
+/*! WUF29 - Wakeup Flag For LLWU_P29
+ * 0b0..LLWU_P29 input was not a wakeup source
+ * 0b1..LLWU_P29 input was a wakeup source
+ */
+#define LLWU_PF4_WUF29(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF29_SHIFT)) & LLWU_PF4_WUF29_MASK)
+#define LLWU_PF4_WUF30_MASK (0x40U)
+#define LLWU_PF4_WUF30_SHIFT (6U)
+/*! WUF30 - Wakeup Flag For LLWU_P30
+ * 0b0..LLWU_P30 input was not a wakeup source
+ * 0b1..LLWU_P30 input was a wakeup source
+ */
+#define LLWU_PF4_WUF30(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF30_SHIFT)) & LLWU_PF4_WUF30_MASK)
+#define LLWU_PF4_WUF31_MASK (0x80U)
+#define LLWU_PF4_WUF31_SHIFT (7U)
+/*! WUF31 - Wakeup Flag For LLWU_P31
+ * 0b0..LLWU_P31 input was not a wakeup source
+ * 0b1..LLWU_P31 input was a wakeup source
+ */
+#define LLWU_PF4_WUF31(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF31_SHIFT)) & LLWU_PF4_WUF31_MASK)
+/*! @} */
+
+/*! @name MF5 - LLWU Module Flag 5 register */
+/*! @{ */
+#define LLWU_MF5_MWUF0_MASK (0x1U)
+#define LLWU_MF5_MWUF0_SHIFT (0U)
+/*! MWUF0 - Wakeup flag For module 0
+ * 0b0..Module 0 input was not a wakeup source
+ * 0b1..Module 0 input was a wakeup source
+ */
+#define LLWU_MF5_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF0_SHIFT)) & LLWU_MF5_MWUF0_MASK)
+#define LLWU_MF5_MWUF1_MASK (0x2U)
+#define LLWU_MF5_MWUF1_SHIFT (1U)
+/*! MWUF1 - Wakeup flag For module 1
+ * 0b0..Module 1 input was not a wakeup source
+ * 0b1..Module 1 input was a wakeup source
+ */
+#define LLWU_MF5_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF1_SHIFT)) & LLWU_MF5_MWUF1_MASK)
+#define LLWU_MF5_MWUF2_MASK (0x4U)
+#define LLWU_MF5_MWUF2_SHIFT (2U)
+/*! MWUF2 - Wakeup flag For module 2
+ * 0b0..Module 2 input was not a wakeup source
+ * 0b1..Module 2 input was a wakeup source
+ */
+#define LLWU_MF5_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF2_SHIFT)) & LLWU_MF5_MWUF2_MASK)
+#define LLWU_MF5_MWUF3_MASK (0x8U)
+#define LLWU_MF5_MWUF3_SHIFT (3U)
+/*! MWUF3 - Wakeup flag For module 3
+ * 0b0..Module 3 input was not a wakeup source
+ * 0b1..Module 3 input was a wakeup source
+ */
+#define LLWU_MF5_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF3_SHIFT)) & LLWU_MF5_MWUF3_MASK)
+#define LLWU_MF5_MWUF4_MASK (0x10U)
+#define LLWU_MF5_MWUF4_SHIFT (4U)
+/*! MWUF4 - Wakeup flag For module 4
+ * 0b0..Module 4 input was not a wakeup source
+ * 0b1..Module 4 input was a wakeup source
+ */
+#define LLWU_MF5_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF4_SHIFT)) & LLWU_MF5_MWUF4_MASK)
+#define LLWU_MF5_MWUF5_MASK (0x20U)
+#define LLWU_MF5_MWUF5_SHIFT (5U)
+/*! MWUF5 - Wakeup flag For module 5
+ * 0b0..Module 5 input was not a wakeup source
+ * 0b1..Module 5 input was a wakeup source
+ */
+#define LLWU_MF5_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF5_SHIFT)) & LLWU_MF5_MWUF5_MASK)
+#define LLWU_MF5_MWUF6_MASK (0x40U)
+#define LLWU_MF5_MWUF6_SHIFT (6U)
+/*! MWUF6 - Wakeup flag For module 6
+ * 0b0..Module 6 input was not a wakeup source
+ * 0b1..Module 6 input was a wakeup source
+ */
+#define LLWU_MF5_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF6_SHIFT)) & LLWU_MF5_MWUF6_MASK)
+#define LLWU_MF5_MWUF7_MASK (0x80U)
+#define LLWU_MF5_MWUF7_SHIFT (7U)
+/*! MWUF7 - Wakeup flag For module 7
+ * 0b0..Module 7 input was not a wakeup source
+ * 0b1..Module 7 input was a wakeup source
+ */
+#define LLWU_MF5_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF7_SHIFT)) & LLWU_MF5_MWUF7_MASK)
+/*! @} */
+
+/*! @name FILT1 - LLWU Pin Filter 1 register */
+/*! @{ */
+#define LLWU_FILT1_FILTSEL_MASK (0x1FU)
+#define LLWU_FILT1_FILTSEL_SHIFT (0U)
+/*! FILTSEL - Filter Pin Select
+ * 0b00000..Select LLWU_P0 for filter
+ * 0b11111..Select LLWU_P31 for filter
+ */
+#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK (0x60U)
+#define LLWU_FILT1_FILTE_SHIFT (5U)
+/*! FILTE - Digital Filter On External Pin
+ * 0b00..Filter disabled
+ * 0b01..Filter posedge detect enabled
+ * 0b10..Filter negedge detect enabled
+ * 0b11..Filter any edge detect enabled
+ */
+#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK (0x80U)
+#define LLWU_FILT1_FILTF_SHIFT (7U)
+/*! FILTF - Filter Detect Flag
+ * 0b0..Pin Filter 1 was not a wakeup source
+ * 0b1..Pin Filter 1 was a wakeup source
+ */
+#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
+/*! @} */
+
+/*! @name FILT2 - LLWU Pin Filter 2 register */
+/*! @{ */
+#define LLWU_FILT2_FILTSEL_MASK (0x1FU)
+#define LLWU_FILT2_FILTSEL_SHIFT (0U)
+/*! FILTSEL - Filter Pin Select
+ * 0b00000..Select LLWU_P0 for filter
+ * 0b11111..Select LLWU_P31 for filter
+ */
+#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK (0x60U)
+#define LLWU_FILT2_FILTE_SHIFT (5U)
+/*! FILTE - Digital Filter On External Pin
+ * 0b00..Filter disabled
+ * 0b01..Filter posedge detect enabled
+ * 0b10..Filter negedge detect enabled
+ * 0b11..Filter any edge detect enabled
+ */
+#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK (0x80U)
+#define LLWU_FILT2_FILTF_SHIFT (7U)
+/*! FILTF - Filter Detect Flag
+ * 0b0..Pin Filter 2 was not a wakeup source
+ * 0b1..Pin Filter 2 was a wakeup source
+ */
+#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
+/*! @} */
+
+/*! @name FILT3 - LLWU Pin Filter 3 register */
+/*! @{ */
+#define LLWU_FILT3_FILTSEL_MASK (0x1FU)
+#define LLWU_FILT3_FILTSEL_SHIFT (0U)
+/*! FILTSEL - Filter Pin Select
+ * 0b00000..Select LLWU_P0 for filter
+ * 0b11111..Select LLWU_P31 for filter
+ */
+#define LLWU_FILT3_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTSEL_SHIFT)) & LLWU_FILT3_FILTSEL_MASK)
+#define LLWU_FILT3_FILTE_MASK (0x60U)
+#define LLWU_FILT3_FILTE_SHIFT (5U)
+/*! FILTE - Digital Filter On External Pin
+ * 0b00..Filter disabled
+ * 0b01..Filter posedge detect enabled
+ * 0b10..Filter negedge detect enabled
+ * 0b11..Filter any edge detect enabled
+ */
+#define LLWU_FILT3_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTE_SHIFT)) & LLWU_FILT3_FILTE_MASK)
+#define LLWU_FILT3_FILTF_MASK (0x80U)
+#define LLWU_FILT3_FILTF_SHIFT (7U)
+/*! FILTF - Filter Detect Flag
+ * 0b0..Pin Filter 3 was not a wakeup source
+ * 0b1..Pin Filter 3 was a wakeup source
+ */
+#define LLWU_FILT3_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTF_SHIFT)) & LLWU_FILT3_FILTF_MASK)
+/*! @} */
+
+/*! @name FILT4 - LLWU Pin Filter 4 register */
+/*! @{ */
+#define LLWU_FILT4_FILTSEL_MASK (0x1FU)
+#define LLWU_FILT4_FILTSEL_SHIFT (0U)
+/*! FILTSEL - Filter Pin Select
+ * 0b00000..Select LLWU_P0 for filter
+ * 0b11111..Select LLWU_P31 for filter
+ */
+#define LLWU_FILT4_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTSEL_SHIFT)) & LLWU_FILT4_FILTSEL_MASK)
+#define LLWU_FILT4_FILTE_MASK (0x60U)
+#define LLWU_FILT4_FILTE_SHIFT (5U)
+/*! FILTE - Digital Filter On External Pin
+ * 0b00..Filter disabled
+ * 0b01..Filter posedge detect enabled
+ * 0b10..Filter negedge detect enabled
+ * 0b11..Filter any edge detect enabled
+ */
+#define LLWU_FILT4_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTE_SHIFT)) & LLWU_FILT4_FILTE_MASK)
+#define LLWU_FILT4_FILTF_MASK (0x80U)
+#define LLWU_FILT4_FILTF_SHIFT (7U)
+/*! FILTF - Filter Detect Flag
+ * 0b0..Pin Filter 4 was not a wakeup source
+ * 0b1..Pin Filter 4 was a wakeup source
+ */
+#define LLWU_FILT4_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTF_SHIFT)) & LLWU_FILT4_FILTF_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU ((LLWU_Type *)LLWU_BASE)
+/** Array initializer of LLWU peripheral base addresses */
+#define LLWU_BASE_ADDRS { LLWU_BASE }
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASE_PTRS { LLWU }
+/** Interrupt vectors for the LLWU peripheral type */
+#define LLWU_IRQS { LLWU_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LMEM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LMEM_Peripheral_Access_Layer LMEM Peripheral Access Layer
+ * @{
+ */
+
+/** LMEM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PCCCR; /**< Cache control register, offset: 0x0 */
+ __IO uint32_t PCCLCR; /**< Cache line control register, offset: 0x4 */
+ __IO uint32_t PCCSAR; /**< Cache search address register, offset: 0x8 */
+ __IO uint32_t PCCCVR; /**< Cache read/write value register, offset: 0xC */
+ uint8_t RESERVED_0[16];
+ __IO uint32_t PCCRMR; /**< Cache regions mode register, offset: 0x20 */
+} LMEM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LMEM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LMEM_Register_Masks LMEM Register Masks
+ * @{
+ */
+
+/*! @name PCCCR - Cache control register */
+/*! @{ */
+#define LMEM_PCCCR_ENCACHE_MASK (0x1U)
+#define LMEM_PCCCR_ENCACHE_SHIFT (0U)
+/*! ENCACHE - Cache enable
+ * 0b0..Cache disabled
+ * 0b1..Cache enabled
+ */
+#define LMEM_PCCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK)
+#define LMEM_PCCCR_ENWRBUF_MASK (0x2U)
+#define LMEM_PCCCR_ENWRBUF_SHIFT (1U)
+/*! ENWRBUF - Enable Write Buffer
+ * 0b0..Write buffer disabled
+ * 0b1..Write buffer enabled
+ */
+#define LMEM_PCCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK)
+#define LMEM_PCCCR_PCCR2_MASK (0x4U)
+#define LMEM_PCCCR_PCCR2_SHIFT (2U)
+#define LMEM_PCCCR_PCCR2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR2_SHIFT)) & LMEM_PCCCR_PCCR2_MASK)
+#define LMEM_PCCCR_PCCR3_MASK (0x8U)
+#define LMEM_PCCCR_PCCR3_SHIFT (3U)
+#define LMEM_PCCCR_PCCR3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR3_SHIFT)) & LMEM_PCCCR_PCCR3_MASK)
+#define LMEM_PCCCR_INVW0_MASK (0x1000000U)
+#define LMEM_PCCCR_INVW0_SHIFT (24U)
+/*! INVW0 - Invalidate Way 0
+ * 0b0..No operation
+ * 0b1..When setting the GO bit, invalidate all lines in way 0.
+ */
+#define LMEM_PCCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK)
+#define LMEM_PCCCR_PUSHW0_MASK (0x2000000U)
+#define LMEM_PCCCR_PUSHW0_SHIFT (25U)
+/*! PUSHW0 - Push Way 0
+ * 0b0..No operation
+ * 0b1..When setting the GO bit, push all modified lines in way 0
+ */
+#define LMEM_PCCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK)
+#define LMEM_PCCCR_INVW1_MASK (0x4000000U)
+#define LMEM_PCCCR_INVW1_SHIFT (26U)
+/*! INVW1 - Invalidate Way 1
+ * 0b0..No operation
+ * 0b1..When setting the GO bit, invalidate all lines in way 1
+ */
+#define LMEM_PCCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK)
+#define LMEM_PCCCR_PUSHW1_MASK (0x8000000U)
+#define LMEM_PCCCR_PUSHW1_SHIFT (27U)
+/*! PUSHW1 - Push Way 1
+ * 0b0..No operation
+ * 0b1..When setting the GO bit, push all modified lines in way 1
+ */
+#define LMEM_PCCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK)
+#define LMEM_PCCCR_GO_MASK (0x80000000U)
+#define LMEM_PCCCR_GO_SHIFT (31U)
+/*! GO - Initiate Cache Command
+ * 0b0..Write: no effect. Read: no cache command active.
+ * 0b1..Write: initiate command indicated by bits 27-24. Read: cache command active.
+ */
+#define LMEM_PCCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK)
+/*! @} */
+
+/*! @name PCCLCR - Cache line control register */
+/*! @{ */
+#define LMEM_PCCLCR_LGO_MASK (0x1U)
+#define LMEM_PCCLCR_LGO_SHIFT (0U)
+/*! LGO - Initiate Cache Line Command
+ * 0b0..Write: no effect. Read: no line command active.
+ * 0b1..Write: initiate line command indicated by bits 27-24. Read: line command active.
+ */
+#define LMEM_PCCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK)
+#define LMEM_PCCLCR_CACHEADDR_MASK (0xFFCU)
+#define LMEM_PCCLCR_CACHEADDR_SHIFT (2U)
+#define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_CACHEADDR_SHIFT)) & LMEM_PCCLCR_CACHEADDR_MASK)
+#define LMEM_PCCLCR_WSEL_MASK (0x4000U)
+#define LMEM_PCCLCR_WSEL_SHIFT (14U)
+/*! WSEL - Way select
+ * 0b0..Way 0
+ * 0b1..Way 1
+ */
+#define LMEM_PCCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK)
+#define LMEM_PCCLCR_TDSEL_MASK (0x10000U)
+#define LMEM_PCCLCR_TDSEL_SHIFT (16U)
+/*! TDSEL - Tag/Data Select
+ * 0b0..Data
+ * 0b1..Tag
+ */
+#define LMEM_PCCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK)
+#define LMEM_PCCLCR_LCIVB_MASK (0x100000U)
+#define LMEM_PCCLCR_LCIVB_SHIFT (20U)
+#define LMEM_PCCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIVB_SHIFT)) & LMEM_PCCLCR_LCIVB_MASK)
+#define LMEM_PCCLCR_LCIMB_MASK (0x200000U)
+#define LMEM_PCCLCR_LCIMB_SHIFT (21U)
+#define LMEM_PCCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIMB_SHIFT)) & LMEM_PCCLCR_LCIMB_MASK)
+#define LMEM_PCCLCR_LCWAY_MASK (0x400000U)
+#define LMEM_PCCLCR_LCWAY_SHIFT (22U)
+#define LMEM_PCCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCWAY_SHIFT)) & LMEM_PCCLCR_LCWAY_MASK)
+#define LMEM_PCCLCR_LCMD_MASK (0x3000000U)
+#define LMEM_PCCLCR_LCMD_SHIFT (24U)
+/*! LCMD - Line Command
+ * 0b00..Search and read or write
+ * 0b01..Invalidate
+ * 0b10..Push
+ * 0b11..Clear
+ */
+#define LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK)
+#define LMEM_PCCLCR_LADSEL_MASK (0x4000000U)
+#define LMEM_PCCLCR_LADSEL_SHIFT (26U)
+/*! LADSEL - Line Address Select
+ * 0b0..Cache address
+ * 0b1..Physical address
+ */
+#define LMEM_PCCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK)
+#define LMEM_PCCLCR_LACC_MASK (0x8000000U)
+#define LMEM_PCCLCR_LACC_SHIFT (27U)
+/*! LACC - Line access type
+ * 0b0..Read
+ * 0b1..Write
+ */
+#define LMEM_PCCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK)
+/*! @} */
+
+/*! @name PCCSAR - Cache search address register */
+/*! @{ */
+#define LMEM_PCCSAR_LGO_MASK (0x1U)
+#define LMEM_PCCSAR_LGO_SHIFT (0U)
+/*! LGO - Initiate Cache Line Command
+ * 0b0..Write: no effect. Read: no line command active.
+ * 0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active.
+ */
+#define LMEM_PCCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK)
+#define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU)
+#define LMEM_PCCSAR_PHYADDR_SHIFT (2U)
+#define LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
+/*! @} */
+
+/*! @name PCCCVR - Cache read/write value register */
+/*! @{ */
+#define LMEM_PCCCVR_DATA_MASK (0xFFFFFFFFU)
+#define LMEM_PCCCVR_DATA_SHIFT (0U)
+#define LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCVR_DATA_SHIFT)) & LMEM_PCCCVR_DATA_MASK)
+/*! @} */
+
+/*! @name PCCRMR - Cache regions mode register */
+/*! @{ */
+#define LMEM_PCCRMR_R15_MASK (0x3U)
+#define LMEM_PCCRMR_R15_SHIFT (0U)
+/*! R15 - Region 15 mode
+ * 0b00..Non-cacheable
+ * 0b01..Non-cacheable
+ * 0b10..Write-through
+ * 0b11..Write-back
+ */
+#define LMEM_PCCRMR_R15(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R15_SHIFT)) & LMEM_PCCRMR_R15_MASK)
+#define LMEM_PCCRMR_R14_MASK (0xCU)
+#define LMEM_PCCRMR_R14_SHIFT (2U)
+/*! R14 - Region 14 mode
+ * 0b00..Non-cacheable
+ * 0b01..Non-cacheable
+ * 0b10..Write-through
+ * 0b11..Write-back
+ */
+#define LMEM_PCCRMR_R14(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R14_SHIFT)) & LMEM_PCCRMR_R14_MASK)
+#define LMEM_PCCRMR_R13_MASK (0x30U)
+#define LMEM_PCCRMR_R13_SHIFT (4U)
+/*! R13 - Region 13 mode
+ * 0b00..Non-cacheable
+ * 0b01..Non-cacheable
+ * 0b10..Write-through
+ * 0b11..Write-back
+ */
+#define LMEM_PCCRMR_R13(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R13_SHIFT)) & LMEM_PCCRMR_R13_MASK)
+#define LMEM_PCCRMR_R12_MASK (0xC0U)
+#define LMEM_PCCRMR_R12_SHIFT (6U)
+/*! R12 - Region 12 mode
+ * 0b00..Non-cacheable
+ * 0b01..Non-cacheable
+ * 0b10..Write-through
+ * 0b11..Write-back
+ */
+#define LMEM_PCCRMR_R12(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R12_SHIFT)) & LMEM_PCCRMR_R12_MASK)
+#define LMEM_PCCRMR_R11_MASK (0x300U)
+#define LMEM_PCCRMR_R11_SHIFT (8U)
+/*! R11 - Region 11 mode
+ * 0b00..Non-cacheable
+ * 0b01..Non-cacheable
+ * 0b10..Write-through
+ * 0b11..Write-back
+ */
+#define LMEM_PCCRMR_R11(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R11_SHIFT)) & LMEM_PCCRMR_R11_MASK)
+#define LMEM_PCCRMR_R10_MASK (0xC00U)
+#define LMEM_PCCRMR_R10_SHIFT (10U)
+/*! R10 - Region 10 mode
+ * 0b00..Non-cacheable
+ * 0b01..Non-cacheable
+ * 0b10..Write-through
+ * 0b11..Write-back
+ */
+#define LMEM_PCCRMR_R10(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R10_SHIFT)) & LMEM_PCCRMR_R10_MASK)
+#define LMEM_PCCRMR_R9_MASK (0x3000U)
+#define LMEM_PCCRMR_R9_SHIFT (12U)
+/*! R9 - Region 9 mode
+ * 0b00..Non-cacheable
+ * 0b01..Non-cacheable
+ * 0b10..Write-through
+ * 0b11..Write-back
+ */
+#define LMEM_PCCRMR_R9(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R9_SHIFT)) & LMEM_PCCRMR_R9_MASK)
+#define LMEM_PCCRMR_R8_MASK (0xC000U)
+#define LMEM_PCCRMR_R8_SHIFT (14U)
+/*! R8 - Region 8 mode
+ * 0b00..Non-cacheable
+ * 0b01..Non-cacheable
+ * 0b10..Write-through
+ * 0b11..Write-back
+ */
+#define LMEM_PCCRMR_R8(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R8_SHIFT)) & LMEM_PCCRMR_R8_MASK)
+#define LMEM_PCCRMR_R7_MASK (0x30000U)
+#define LMEM_PCCRMR_R7_SHIFT (16U)
+/*! R7 - Region 7 mode
+ * 0b00..Non-cacheable
+ * 0b01..Non-cacheable
+ * 0b10..Write-through
+ * 0b11..Write-back
+ */
+#define LMEM_PCCRMR_R7(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R7_SHIFT)) & LMEM_PCCRMR_R7_MASK)
+#define LMEM_PCCRMR_R6_MASK (0xC0000U)
+#define LMEM_PCCRMR_R6_SHIFT (18U)
+/*! R6 - Region 6 mode
+ * 0b00..Non-cacheable
+ * 0b01..Non-cacheable
+ * 0b10..Write-through
+ * 0b11..Write-back
+ */
+#define LMEM_PCCRMR_R6(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R6_SHIFT)) & LMEM_PCCRMR_R6_MASK)
+#define LMEM_PCCRMR_R5_MASK (0x300000U)
+#define LMEM_PCCRMR_R5_SHIFT (20U)
+/*! R5 - Region 5 mode
+ * 0b00..Non-cacheable
+ * 0b01..Non-cacheable
+ * 0b10..Write-through
+ * 0b11..Write-back
+ */
+#define LMEM_PCCRMR_R5(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R5_SHIFT)) & LMEM_PCCRMR_R5_MASK)
+#define LMEM_PCCRMR_R4_MASK (0xC00000U)
+#define LMEM_PCCRMR_R4_SHIFT (22U)
+/*! R4 - Region 4 mode
+ * 0b00..Non-cacheable
+ * 0b01..Non-cacheable
+ * 0b10..Write-through
+ * 0b11..Write-back
+ */
+#define LMEM_PCCRMR_R4(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R4_SHIFT)) & LMEM_PCCRMR_R4_MASK)
+#define LMEM_PCCRMR_R3_MASK (0x3000000U)
+#define LMEM_PCCRMR_R3_SHIFT (24U)
+/*! R3 - Region 3 mode
+ * 0b00..Non-cacheable
+ * 0b01..Non-cacheable
+ * 0b10..Write-through
+ * 0b11..Write-back
+ */
+#define LMEM_PCCRMR_R3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R3_SHIFT)) & LMEM_PCCRMR_R3_MASK)
+#define LMEM_PCCRMR_R2_MASK (0xC000000U)
+#define LMEM_PCCRMR_R2_SHIFT (26U)
+/*! R2 - Region 2 mode
+ * 0b00..Non-cacheable
+ * 0b01..Non-cacheable
+ * 0b10..Write-through
+ * 0b11..Write-back
+ */
+#define LMEM_PCCRMR_R2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R2_SHIFT)) & LMEM_PCCRMR_R2_MASK)
+#define LMEM_PCCRMR_R1_MASK (0x30000000U)
+#define LMEM_PCCRMR_R1_SHIFT (28U)
+/*! R1 - Region 1 mode
+ * 0b00..Non-cacheable
+ * 0b01..Non-cacheable
+ * 0b10..Write-through
+ * 0b11..Write-back
+ */
+#define LMEM_PCCRMR_R1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R1_SHIFT)) & LMEM_PCCRMR_R1_MASK)
+#define LMEM_PCCRMR_R0_MASK (0xC0000000U)
+#define LMEM_PCCRMR_R0_SHIFT (30U)
+/*! R0 - Region 0 mode
+ * 0b00..Non-cacheable
+ * 0b01..Non-cacheable
+ * 0b10..Write-through
+ * 0b11..Write-back
+ */
+#define LMEM_PCCRMR_R0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R0_SHIFT)) & LMEM_PCCRMR_R0_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LMEM_Register_Masks */
+
+
+/* LMEM - Peripheral instance base addresses */
+/** Peripheral LMEM base address */
+#define LMEM_BASE (0xE0082000u)
+/** Peripheral LMEM base pointer */
+#define LMEM ((LMEM_Type *)LMEM_BASE)
+/** Array initializer of LMEM peripheral base addresses */
+#define LMEM_BASE_ADDRS { LMEM_BASE }
+/** Array initializer of LMEM peripheral base pointers */
+#define LMEM_BASE_PTRS { LMEM }
+
+/*!
+ * @}
+ */ /* end of group LMEM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
+ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
+ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
+ __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/*! @name CSR - Low Power Timer Control Status Register */
+/*! @{ */
+#define LPTMR_CSR_TEN_MASK (0x1U)
+#define LPTMR_CSR_TEN_SHIFT (0U)
+/*! TEN - Timer Enable
+ * 0b0..LPTMR is disabled and internal logic is reset.
+ * 0b1..LPTMR is enabled.
+ */
+#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
+#define LPTMR_CSR_TMS_MASK (0x2U)
+#define LPTMR_CSR_TMS_SHIFT (1U)
+/*! TMS - Timer Mode Select
+ * 0b0..Time Counter mode.
+ * 0b1..Pulse Counter mode.
+ */
+#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
+#define LPTMR_CSR_TFC_MASK (0x4U)
+#define LPTMR_CSR_TFC_SHIFT (2U)
+/*! TFC - Timer Free-Running Counter
+ * 0b0..CNR is reset whenever TCF is set.
+ * 0b1..CNR is reset on overflow.
+ */
+#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
+#define LPTMR_CSR_TPP_MASK (0x8U)
+#define LPTMR_CSR_TPP_SHIFT (3U)
+/*! TPP - Timer Pin Polarity
+ * 0b0..Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.
+ * 0b1..Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.
+ */
+#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
+#define LPTMR_CSR_TPS_MASK (0x30U)
+#define LPTMR_CSR_TPS_SHIFT (4U)
+/*! TPS - Timer Pin Select
+ * 0b00..Pulse counter input 0 is selected.
+ * 0b01..Pulse counter input 1 is selected.
+ * 0b10..Pulse counter input 2 is selected.
+ * 0b11..Pulse counter input 3 is selected.
+ */
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK (0x40U)
+#define LPTMR_CSR_TIE_SHIFT (6U)
+/*! TIE - Timer Interrupt Enable
+ * 0b0..Timer interrupt disabled.
+ * 0b1..Timer interrupt enabled.
+ */
+#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
+#define LPTMR_CSR_TCF_MASK (0x80U)
+#define LPTMR_CSR_TCF_SHIFT (7U)
+/*! TCF - Timer Compare Flag
+ * 0b0..The value of CNR is not equal to CMR and increments.
+ * 0b1..The value of CNR is equal to CMR and increments.
+ */
+#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
+/*! @} */
+
+/*! @name PSR - Low Power Timer Prescale Register */
+/*! @{ */
+#define LPTMR_PSR_PCS_MASK (0x3U)
+#define LPTMR_PSR_PCS_SHIFT (0U)
+/*! PCS - Prescaler Clock Select
+ * 0b00..Prescaler/glitch filter clock 0 selected.
+ * 0b01..Prescaler/glitch filter clock 1 selected.
+ * 0b10..Prescaler/glitch filter clock 2 selected.
+ * 0b11..Prescaler/glitch filter clock 3 selected.
+ */
+#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK (0x4U)
+#define LPTMR_PSR_PBYP_SHIFT (2U)
+/*! PBYP - Prescaler Bypass
+ * 0b0..Prescaler/glitch filter is enabled.
+ * 0b1..Prescaler/glitch filter is bypassed.
+ */
+#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
+#define LPTMR_PSR_PRESCALE_MASK (0x78U)
+#define LPTMR_PSR_PRESCALE_SHIFT (3U)
+/*! PRESCALE - Prescale Value
+ * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.
+ * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.
+ * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.
+ * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.
+ * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.
+ * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.
+ * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.
+ * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.
+ * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.
+ * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.
+ * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges.
+ * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges.
+ * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges.
+ * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges.
+ * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges.
+ * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.
+ */
+#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
+/*! @} */
+
+/*! @name CMR - Low Power Timer Compare Register */
+/*! @{ */
+#define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
+#define LPTMR_CMR_COMPARE_SHIFT (0U)
+#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
+/*! @} */
+
+/*! @name CNR - Low Power Timer Counter Register */
+/*! @{ */
+#define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
+#define LPTMR_CNR_COUNTER_SHIFT (0U)
+#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
+/** Array initializer of LPTMR peripheral base addresses */
+#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASE_PTRS { LPTMR0 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS { LPTMR0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPUART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
+ * @{
+ */
+
+/** LPUART - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */
+ __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */
+ __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */
+ __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
+ __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
+ __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x14 */
+} LPUART_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LPUART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Register_Masks LPUART Register Masks
+ * @{
+ */
+
+/*! @name BAUD - LPUART Baud Rate Register */
+/*! @{ */
+#define LPUART_BAUD_SBR_MASK (0x1FFFU)
+#define LPUART_BAUD_SBR_SHIFT (0U)
+#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
+#define LPUART_BAUD_SBNS_MASK (0x2000U)
+#define LPUART_BAUD_SBNS_SHIFT (13U)
+/*! SBNS - Stop Bit Number Select
+ * 0b0..One stop bit.
+ * 0b1..Two stop bits.
+ */
+#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
+#define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
+#define LPUART_BAUD_RXEDGIE_SHIFT (14U)
+/*! RXEDGIE - RX Input Active Edge Interrupt Enable
+ * 0b0..Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling).
+ * 0b1..Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1.
+ */
+#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
+#define LPUART_BAUD_LBKDIE_MASK (0x8000U)
+#define LPUART_BAUD_LBKDIE_SHIFT (15U)
+/*! LBKDIE - LIN Break Detect Interrupt Enable
+ * 0b0..Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling).
+ * 0b1..Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1.
+ */
+#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
+#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
+#define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
+/*! RESYNCDIS - Resynchronization Disable
+ * 0b0..Resynchronization during received data word is supported
+ * 0b1..Resynchronization during received data word is disabled
+ */
+#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
+#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
+#define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
+/*! BOTHEDGE - Both Edge Sampling
+ * 0b0..Receiver samples input data using the rising edge of the baud rate clock.
+ * 0b1..Receiver samples input data using the rising and falling edge of the baud rate clock.
+ */
+#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
+#define LPUART_BAUD_MATCFG_MASK (0xC0000U)
+#define LPUART_BAUD_MATCFG_SHIFT (18U)
+/*! MATCFG - Match Configuration
+ * 0b00..Address Match Wakeup
+ * 0b01..Idle Match Wakeup
+ * 0b10..Match On and Match Off
+ * 0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input
+ */
+#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
+#define LPUART_BAUD_RDMAE_MASK (0x200000U)
+#define LPUART_BAUD_RDMAE_SHIFT (21U)
+/*! RDMAE - Receiver Full DMA Enable
+ * 0b0..DMA request disabled.
+ * 0b1..DMA request enabled.
+ */
+#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
+#define LPUART_BAUD_TDMAE_MASK (0x800000U)
+#define LPUART_BAUD_TDMAE_SHIFT (23U)
+/*! TDMAE - Transmitter DMA Enable
+ * 0b0..DMA request disabled.
+ * 0b1..DMA request enabled.
+ */
+#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
+#define LPUART_BAUD_OSR_MASK (0x1F000000U)
+#define LPUART_BAUD_OSR_SHIFT (24U)
+#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
+#define LPUART_BAUD_M10_MASK (0x20000000U)
+#define LPUART_BAUD_M10_SHIFT (29U)
+/*! M10 - 10-bit Mode select
+ * 0b0..Receiver and transmitter use 8-bit or 9-bit data characters.
+ * 0b1..Receiver and transmitter use 10-bit data characters.
+ */
+#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
+#define LPUART_BAUD_MAEN2_MASK (0x40000000U)
+#define LPUART_BAUD_MAEN2_SHIFT (30U)
+/*! MAEN2 - Match Address Mode Enable 2
+ * 0b0..Normal operation.
+ * 0b1..Enables automatic address matching or data matching mode for MATCH[MA2].
+ */
+#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
+#define LPUART_BAUD_MAEN1_MASK (0x80000000U)
+#define LPUART_BAUD_MAEN1_SHIFT (31U)
+/*! MAEN1 - Match Address Mode Enable 1
+ * 0b0..Normal operation.
+ * 0b1..Enables automatic address matching or data matching mode for MATCH[MA1].
+ */
+#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
+/*! @} */
+
+/*! @name STAT - LPUART Status Register */
+/*! @{ */
+#define LPUART_STAT_MA2F_MASK (0x4000U)
+#define LPUART_STAT_MA2F_SHIFT (14U)
+/*! MA2F - Match 2 Flag
+ * 0b0..Received data is not equal to MA2
+ * 0b1..Received data is equal to MA2
+ */
+#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
+#define LPUART_STAT_MA1F_MASK (0x8000U)
+#define LPUART_STAT_MA1F_SHIFT (15U)
+/*! MA1F - Match 1 Flag
+ * 0b0..Received data is not equal to MA1
+ * 0b1..Received data is equal to MA1
+ */
+#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
+#define LPUART_STAT_PF_MASK (0x10000U)
+#define LPUART_STAT_PF_SHIFT (16U)
+/*! PF - Parity Error Flag
+ * 0b0..No parity error.
+ * 0b1..Parity error.
+ */
+#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
+#define LPUART_STAT_FE_MASK (0x20000U)
+#define LPUART_STAT_FE_SHIFT (17U)
+/*! FE - Framing Error Flag
+ * 0b0..No framing error detected. This does not guarantee the framing is correct.
+ * 0b1..Framing error.
+ */
+#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
+#define LPUART_STAT_NF_MASK (0x40000U)
+#define LPUART_STAT_NF_SHIFT (18U)
+/*! NF - Noise Flag
+ * 0b0..No noise detected.
+ * 0b1..Noise detected in the received character in LPUART_DATA.
+ */
+#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
+#define LPUART_STAT_OR_MASK (0x80000U)
+#define LPUART_STAT_OR_SHIFT (19U)
+/*! OR - Receiver Overrun Flag
+ * 0b0..No overrun.
+ * 0b1..Receive overrun (new LPUART data lost).
+ */
+#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
+#define LPUART_STAT_IDLE_MASK (0x100000U)
+#define LPUART_STAT_IDLE_SHIFT (20U)
+/*! IDLE - Idle Line Flag
+ * 0b0..No idle line detected.
+ * 0b1..Idle line was detected.
+ */
+#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
+#define LPUART_STAT_RDRF_MASK (0x200000U)
+#define LPUART_STAT_RDRF_SHIFT (21U)
+/*! RDRF - Receive Data Register Full Flag
+ * 0b0..Receive data buffer empty.
+ * 0b1..Receive data buffer full.
+ */
+#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
+#define LPUART_STAT_TC_MASK (0x400000U)
+#define LPUART_STAT_TC_SHIFT (22U)
+/*! TC - Transmission Complete Flag
+ * 0b0..Transmitter active (sending data, a preamble, or a break).
+ * 0b1..Transmitter idle (transmission activity complete).
+ */
+#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
+#define LPUART_STAT_TDRE_MASK (0x800000U)
+#define LPUART_STAT_TDRE_SHIFT (23U)
+/*! TDRE - Transmit Data Register Empty Flag
+ * 0b0..Transmit data buffer full.
+ * 0b1..Transmit data buffer empty.
+ */
+#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
+#define LPUART_STAT_RAF_MASK (0x1000000U)
+#define LPUART_STAT_RAF_SHIFT (24U)
+/*! RAF - Receiver Active Flag
+ * 0b0..LPUART receiver idle waiting for a start bit.
+ * 0b1..LPUART receiver active (LPUART_RX input not idle).
+ */
+#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
+#define LPUART_STAT_LBKDE_MASK (0x2000000U)
+#define LPUART_STAT_LBKDE_SHIFT (25U)
+/*! LBKDE - LIN Break Detection Enable
+ * 0b0..Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
+ * 0b1..Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).
+ */
+#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
+#define LPUART_STAT_BRK13_MASK (0x4000000U)
+#define LPUART_STAT_BRK13_SHIFT (26U)
+/*! BRK13 - Break Character Generation Length
+ * 0b0..Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
+ * 0b1..Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).
+ */
+#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
+#define LPUART_STAT_RWUID_MASK (0x8000000U)
+#define LPUART_STAT_RWUID_SHIFT (27U)
+/*! RWUID - Receive Wake Up Idle Detect
+ * 0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match.
+ * 0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match.
+ */
+#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
+#define LPUART_STAT_RXINV_MASK (0x10000000U)
+#define LPUART_STAT_RXINV_SHIFT (28U)
+/*! RXINV - Receive Data Inversion
+ * 0b0..Receive data not inverted.
+ * 0b1..Receive data inverted.
+ */
+#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
+#define LPUART_STAT_MSBF_MASK (0x20000000U)
+#define LPUART_STAT_MSBF_SHIFT (29U)
+/*! MSBF - MSB First
+ * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
+ * 0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].
+ */
+#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
+#define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
+#define LPUART_STAT_RXEDGIF_SHIFT (30U)
+/*! RXEDGIF - LPUART_RX Pin Active Edge Interrupt Flag
+ * 0b0..No active edge on the receive pin has occurred.
+ * 0b1..An active edge on the receive pin has occurred.
+ */
+#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
+#define LPUART_STAT_LBKDIF_MASK (0x80000000U)
+#define LPUART_STAT_LBKDIF_SHIFT (31U)
+/*! LBKDIF - LIN Break Detect Interrupt Flag
+ * 0b0..No LIN break character has been detected.
+ * 0b1..LIN break character has been detected.
+ */
+#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
+/*! @} */
+
+/*! @name CTRL - LPUART Control Register */
+/*! @{ */
+#define LPUART_CTRL_PT_MASK (0x1U)
+#define LPUART_CTRL_PT_SHIFT (0U)
+/*! PT - Parity Type
+ * 0b0..Even parity.
+ * 0b1..Odd parity.
+ */
+#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
+#define LPUART_CTRL_PE_MASK (0x2U)
+#define LPUART_CTRL_PE_SHIFT (1U)
+/*! PE - Parity Enable
+ * 0b0..No hardware parity generation or checking.
+ * 0b1..Parity enabled.
+ */
+#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
+#define LPUART_CTRL_ILT_MASK (0x4U)
+#define LPUART_CTRL_ILT_SHIFT (2U)
+/*! ILT - Idle Line Type Select
+ * 0b0..Idle character bit count starts after start bit.
+ * 0b1..Idle character bit count starts after stop bit.
+ */
+#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
+#define LPUART_CTRL_WAKE_MASK (0x8U)
+#define LPUART_CTRL_WAKE_SHIFT (3U)
+/*! WAKE - Receiver Wakeup Method Select
+ * 0b0..Configures RWU for idle-line wakeup.
+ * 0b1..Configures RWU with address-mark wakeup.
+ */
+#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
+#define LPUART_CTRL_M_MASK (0x10U)
+#define LPUART_CTRL_M_SHIFT (4U)
+/*! M - 9-Bit or 8-Bit Mode Select
+ * 0b0..Receiver and transmitter use 8-bit data characters.
+ * 0b1..Receiver and transmitter use 9-bit data characters.
+ */
+#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
+#define LPUART_CTRL_RSRC_MASK (0x20U)
+#define LPUART_CTRL_RSRC_SHIFT (5U)
+/*! RSRC - Receiver Source Select
+ * 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin.
+ * 0b1..Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input.
+ */
+#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
+#define LPUART_CTRL_DOZEEN_MASK (0x40U)
+#define LPUART_CTRL_DOZEEN_SHIFT (6U)
+/*! DOZEEN - Doze Enable
+ * 0b0..LPUART is enabled in Doze mode.
+ * 0b1..LPUART is disabled in Doze mode.
+ */
+#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
+#define LPUART_CTRL_LOOPS_MASK (0x80U)
+#define LPUART_CTRL_LOOPS_SHIFT (7U)
+/*! LOOPS - Loop Mode Select
+ * 0b0..Normal operation - LPUART_RX and LPUART_TX use separate pins.
+ * 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).
+ */
+#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
+#define LPUART_CTRL_IDLECFG_MASK (0x700U)
+#define LPUART_CTRL_IDLECFG_SHIFT (8U)
+/*! IDLECFG - Idle Configuration
+ * 0b000..1 idle character
+ * 0b001..2 idle characters
+ * 0b010..4 idle characters
+ * 0b011..8 idle characters
+ * 0b100..16 idle characters
+ * 0b101..32 idle characters
+ * 0b110..64 idle characters
+ * 0b111..128 idle characters
+ */
+#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
+#define LPUART_CTRL_MA2IE_MASK (0x4000U)
+#define LPUART_CTRL_MA2IE_SHIFT (14U)
+/*! MA2IE - Match 2 Interrupt Enable
+ * 0b0..MA2F interrupt disabled
+ * 0b1..MA2F interrupt enabled
+ */
+#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
+#define LPUART_CTRL_MA1IE_MASK (0x8000U)
+#define LPUART_CTRL_MA1IE_SHIFT (15U)
+/*! MA1IE - Match 1 Interrupt Enable
+ * 0b0..MA1F interrupt disabled
+ * 0b1..MA1F interrupt enabled
+ */
+#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
+#define LPUART_CTRL_SBK_MASK (0x10000U)
+#define LPUART_CTRL_SBK_SHIFT (16U)
+/*! SBK - Send Break
+ * 0b0..Normal transmitter operation.
+ * 0b1..Queue break character(s) to be sent.
+ */
+#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
+#define LPUART_CTRL_RWU_MASK (0x20000U)
+#define LPUART_CTRL_RWU_SHIFT (17U)
+/*! RWU - Receiver Wakeup Control
+ * 0b0..Normal receiver operation.
+ * 0b1..LPUART receiver in standby waiting for wakeup condition.
+ */
+#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
+#define LPUART_CTRL_RE_MASK (0x40000U)
+#define LPUART_CTRL_RE_SHIFT (18U)
+/*! RE - Receiver Enable
+ * 0b0..Receiver disabled.
+ * 0b1..Receiver enabled.
+ */
+#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
+#define LPUART_CTRL_TE_MASK (0x80000U)
+#define LPUART_CTRL_TE_SHIFT (19U)
+/*! TE - Transmitter Enable
+ * 0b0..Transmitter disabled.
+ * 0b1..Transmitter enabled.
+ */
+#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
+#define LPUART_CTRL_ILIE_MASK (0x100000U)
+#define LPUART_CTRL_ILIE_SHIFT (20U)
+/*! ILIE - Idle Line Interrupt Enable
+ * 0b0..Hardware interrupts from IDLE disabled; use polling.
+ * 0b1..Hardware interrupt requested when IDLE flag is 1.
+ */
+#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
+#define LPUART_CTRL_RIE_MASK (0x200000U)
+#define LPUART_CTRL_RIE_SHIFT (21U)
+/*! RIE - Receiver Interrupt Enable
+ * 0b0..Hardware interrupts from RDRF disabled; use polling.
+ * 0b1..Hardware interrupt requested when RDRF flag is 1.
+ */
+#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
+#define LPUART_CTRL_TCIE_MASK (0x400000U)
+#define LPUART_CTRL_TCIE_SHIFT (22U)
+/*! TCIE - Transmission Complete Interrupt Enable for
+ * 0b0..Hardware interrupts from TC disabled; use polling.
+ * 0b1..Hardware interrupt requested when TC flag is 1.
+ */
+#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
+#define LPUART_CTRL_TIE_MASK (0x800000U)
+#define LPUART_CTRL_TIE_SHIFT (23U)
+/*! TIE - Transmit Interrupt Enable
+ * 0b0..Hardware interrupts from TDRE disabled; use polling.
+ * 0b1..Hardware interrupt requested when TDRE flag is 1.
+ */
+#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
+#define LPUART_CTRL_PEIE_MASK (0x1000000U)
+#define LPUART_CTRL_PEIE_SHIFT (24U)
+/*! PEIE - Parity Error Interrupt Enable
+ * 0b0..PF interrupts disabled; use polling).
+ * 0b1..Hardware interrupt requested when PF is set.
+ */
+#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
+#define LPUART_CTRL_FEIE_MASK (0x2000000U)
+#define LPUART_CTRL_FEIE_SHIFT (25U)
+/*! FEIE - Framing Error Interrupt Enable
+ * 0b0..FE interrupts disabled; use polling.
+ * 0b1..Hardware interrupt requested when FE is set.
+ */
+#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
+#define LPUART_CTRL_NEIE_MASK (0x4000000U)
+#define LPUART_CTRL_NEIE_SHIFT (26U)
+/*! NEIE - Noise Error Interrupt Enable
+ * 0b0..NF interrupts disabled; use polling.
+ * 0b1..Hardware interrupt requested when NF is set.
+ */
+#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
+#define LPUART_CTRL_ORIE_MASK (0x8000000U)
+#define LPUART_CTRL_ORIE_SHIFT (27U)
+/*! ORIE - Overrun Interrupt Enable
+ * 0b0..OR interrupts disabled; use polling.
+ * 0b1..Hardware interrupt requested when OR is set.
+ */
+#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
+#define LPUART_CTRL_TXINV_MASK (0x10000000U)
+#define LPUART_CTRL_TXINV_SHIFT (28U)
+/*! TXINV - Transmit Data Inversion
+ * 0b0..Transmit data not inverted.
+ * 0b1..Transmit data inverted.
+ */
+#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
+#define LPUART_CTRL_TXDIR_MASK (0x20000000U)
+#define LPUART_CTRL_TXDIR_SHIFT (29U)
+/*! TXDIR - LPUART_TX Pin Direction in Single-Wire Mode
+ * 0b0..LPUART_TX pin is an input in single-wire mode.
+ * 0b1..LPUART_TX pin is an output in single-wire mode.
+ */
+#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
+#define LPUART_CTRL_R9T8_MASK (0x40000000U)
+#define LPUART_CTRL_R9T8_SHIFT (30U)
+#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
+#define LPUART_CTRL_R8T9_MASK (0x80000000U)
+#define LPUART_CTRL_R8T9_SHIFT (31U)
+#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
+/*! @} */
+
+/*! @name DATA - LPUART Data Register */
+/*! @{ */
+#define LPUART_DATA_R0T0_MASK (0x1U)
+#define LPUART_DATA_R0T0_SHIFT (0U)
+#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
+#define LPUART_DATA_R1T1_MASK (0x2U)
+#define LPUART_DATA_R1T1_SHIFT (1U)
+#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
+#define LPUART_DATA_R2T2_MASK (0x4U)
+#define LPUART_DATA_R2T2_SHIFT (2U)
+#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
+#define LPUART_DATA_R3T3_MASK (0x8U)
+#define LPUART_DATA_R3T3_SHIFT (3U)
+#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
+#define LPUART_DATA_R4T4_MASK (0x10U)
+#define LPUART_DATA_R4T4_SHIFT (4U)
+#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
+#define LPUART_DATA_R5T5_MASK (0x20U)
+#define LPUART_DATA_R5T5_SHIFT (5U)
+#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
+#define LPUART_DATA_R6T6_MASK (0x40U)
+#define LPUART_DATA_R6T6_SHIFT (6U)
+#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
+#define LPUART_DATA_R7T7_MASK (0x80U)
+#define LPUART_DATA_R7T7_SHIFT (7U)
+#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
+#define LPUART_DATA_R8T8_MASK (0x100U)
+#define LPUART_DATA_R8T8_SHIFT (8U)
+#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
+#define LPUART_DATA_R9T9_MASK (0x200U)
+#define LPUART_DATA_R9T9_SHIFT (9U)
+#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
+#define LPUART_DATA_IDLINE_MASK (0x800U)
+#define LPUART_DATA_IDLINE_SHIFT (11U)
+/*! IDLINE - Idle Line
+ * 0b0..Receiver was not idle before receiving this character.
+ * 0b1..Receiver was idle before receiving this character.
+ */
+#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
+#define LPUART_DATA_RXEMPT_MASK (0x1000U)
+#define LPUART_DATA_RXEMPT_SHIFT (12U)
+/*! RXEMPT - Receive Buffer Empty
+ * 0b0..Receive buffer contains valid data.
+ * 0b1..Receive buffer is empty, data returned on read is not valid.
+ */
+#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
+#define LPUART_DATA_FRETSC_MASK (0x2000U)
+#define LPUART_DATA_FRETSC_SHIFT (13U)
+/*! FRETSC - Frame Error / Transmit Special Character
+ * 0b0..The dataword was received without a frame error on read, transmit a normal character on write.
+ * 0b1..The dataword was received with a frame error, transmit an idle or break character on transmit.
+ */
+#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
+#define LPUART_DATA_PARITYE_MASK (0x4000U)
+#define LPUART_DATA_PARITYE_SHIFT (14U)
+/*! PARITYE
+ * 0b0..The dataword was received without a parity error.
+ * 0b1..The dataword was received with a parity error.
+ */
+#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
+#define LPUART_DATA_NOISY_MASK (0x8000U)
+#define LPUART_DATA_NOISY_SHIFT (15U)
+/*! NOISY
+ * 0b0..The dataword was received without noise.
+ * 0b1..The data was received with noise.
+ */
+#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
+/*! @} */
+
+/*! @name MATCH - LPUART Match Address Register */
+/*! @{ */
+#define LPUART_MATCH_MA1_MASK (0x3FFU)
+#define LPUART_MATCH_MA1_SHIFT (0U)
+#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
+#define LPUART_MATCH_MA2_MASK (0x3FF0000U)
+#define LPUART_MATCH_MA2_SHIFT (16U)
+#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
+/*! @} */
+
+/*! @name MODIR - LPUART Modem IrDA Register */
+/*! @{ */
+#define LPUART_MODIR_TXCTSE_MASK (0x1U)
+#define LPUART_MODIR_TXCTSE_SHIFT (0U)
+/*! TXCTSE - Transmitter clear-to-send enable
+ * 0b0..CTS has no effect on the transmitter.
+ * 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
+ */
+#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
+#define LPUART_MODIR_TXRTSE_MASK (0x2U)
+#define LPUART_MODIR_TXRTSE_SHIFT (1U)
+/*! TXRTSE - Transmitter request-to-send enable
+ * 0b0..The transmitter has no effect on RTS.
+ * 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit.
+ */
+#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
+#define LPUART_MODIR_TXRTSPOL_MASK (0x4U)
+#define LPUART_MODIR_TXRTSPOL_SHIFT (2U)
+/*! TXRTSPOL - Transmitter request-to-send polarity
+ * 0b0..Transmitter RTS is active low.
+ * 0b1..Transmitter RTS is active high.
+ */
+#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
+#define LPUART_MODIR_RXRTSE_MASK (0x8U)
+#define LPUART_MODIR_RXRTSE_SHIFT (3U)
+/*! RXRTSE - Receiver request-to-send enable
+ * 0b0..The receiver has no effect on RTS.
+ * 0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full.
+ */
+#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
+#define LPUART_MODIR_TXCTSC_MASK (0x10U)
+#define LPUART_MODIR_TXCTSC_SHIFT (4U)
+/*! TXCTSC - Transmit CTS Configuration
+ * 0b0..CTS input is sampled at the start of each character.
+ * 0b1..CTS input is sampled when the transmitter is idle.
+ */
+#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
+#define LPUART_MODIR_TXCTSSRC_MASK (0x20U)
+#define LPUART_MODIR_TXCTSSRC_SHIFT (5U)
+/*! TXCTSSRC - Transmit CTS Source
+ * 0b0..CTS input is the LPUART_CTS pin.
+ * 0b1..CTS input is the inverted Receiver Match result.
+ */
+#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
+#define LPUART_MODIR_TNP_MASK (0x30000U)
+#define LPUART_MODIR_TNP_SHIFT (16U)
+/*! TNP - Transmitter narrow pulse
+ * 0b00..1/OSR.
+ * 0b01..2/OSR.
+ * 0b10..3/OSR.
+ * 0b11..4/OSR.
+ */
+#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
+#define LPUART_MODIR_IREN_MASK (0x40000U)
+#define LPUART_MODIR_IREN_SHIFT (18U)
+/*! IREN - Infrared enable
+ * 0b0..IR disabled.
+ * 0b1..IR enabled.
+ */
+#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LPUART_Register_Masks */
+
+
+/* LPUART - Peripheral instance base addresses */
+/** Peripheral LPUART0 base address */
+#define LPUART0_BASE (0x400C4000u)
+/** Peripheral LPUART0 base pointer */
+#define LPUART0 ((LPUART_Type *)LPUART0_BASE)
+/** Array initializer of LPUART peripheral base addresses */
+#define LPUART_BASE_ADDRS { LPUART0_BASE }
+/** Array initializer of LPUART peripheral base pointers */
+#define LPUART_BASE_PTRS { LPUART0 }
+/** Interrupt vectors for the LPUART peripheral type */
+#define LPUART_RX_TX_IRQS { LPUART0_IRQn }
+#define LPUART_ERR_IRQS { LPUART0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LPUART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
+ __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
+ __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
+ __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
+ __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
+ __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
+ __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+ __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+ __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
+ __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
+ __IO uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
+ uint8_t RESERVED_2[1];
+ __IO uint8_t C11; /**< MCG Control 11 Register, offset: 0x10 */
+ uint8_t RESERVED_3[1];
+ __I uint8_t S2; /**< MCG Status 2 Register, offset: 0x12 */
+} MCG_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MCG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/*! @name C1 - MCG Control 1 Register */
+/*! @{ */
+#define MCG_C1_IREFSTEN_MASK (0x1U)
+#define MCG_C1_IREFSTEN_SHIFT (0U)
+/*! IREFSTEN - Internal Reference Stop Enable
+ * 0b0..Internal reference clock is disabled in Stop mode.
+ * 0b1..Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
+ */
+#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
+#define MCG_C1_IRCLKEN_MASK (0x2U)
+#define MCG_C1_IRCLKEN_SHIFT (1U)
+/*! IRCLKEN - Internal Reference Clock Enable
+ * 0b0..MCGIRCLK inactive.
+ * 0b1..MCGIRCLK active.
+ */
+#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
+#define MCG_C1_IREFS_MASK (0x4U)
+#define MCG_C1_IREFS_SHIFT (2U)
+/*! IREFS - Internal Reference Select
+ * 0b0..External reference clock is selected.
+ * 0b1..The slow internal reference clock is selected.
+ */
+#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
+#define MCG_C1_FRDIV_MASK (0x38U)
+#define MCG_C1_FRDIV_SHIFT (3U)
+/*! FRDIV - FLL External Reference Divider
+ * 0b000..If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32.
+ * 0b001..If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64.
+ * 0b010..If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128.
+ * 0b011..If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256.
+ * 0b100..If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512.
+ * 0b101..If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024.
+ * 0b110..If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 .
+ * 0b111..If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 .
+ */
+#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK (0xC0U)
+#define MCG_C1_CLKS_SHIFT (6U)
+/*! CLKS - Clock Source Select
+ * 0b00..Encoding 0 - Output of FLL or PLLCS is selected (depends on PLLS control bit).
+ * 0b01..Encoding 1 - Internal reference clock is selected.
+ * 0b10..Encoding 2 - External reference clock is selected.
+ * 0b11..Encoding 3 - Reserved.
+ */
+#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
+/*! @} */
+
+/*! @name C2 - MCG Control 2 Register */
+/*! @{ */
+#define MCG_C2_IRCS_MASK (0x1U)
+#define MCG_C2_IRCS_SHIFT (0U)
+/*! IRCS - Internal Reference Clock Select
+ * 0b0..Slow internal reference clock selected.
+ * 0b1..Fast internal reference clock selected.
+ */
+#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
+#define MCG_C2_LP_MASK (0x2U)
+#define MCG_C2_LP_SHIFT (1U)
+/*! LP - Low Power Select
+ * 0b0..FLL or PLL is not disabled in bypass modes.
+ * 0b1..FLL or PLL is disabled in bypass modes (lower power)
+ */
+#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
+#define MCG_C2_EREFS_MASK (0x4U)
+#define MCG_C2_EREFS_SHIFT (2U)
+/*! EREFS - External Reference Select
+ * 0b0..External reference clock requested.
+ * 0b1..Oscillator requested.
+ */
+#define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
+#define MCG_C2_HGO_MASK (0x8U)
+#define MCG_C2_HGO_SHIFT (3U)
+/*! HGO - High Gain Oscillator Select
+ * 0b0..Configure crystal oscillator for low-power operation.
+ * 0b1..Configure crystal oscillator for high-gain operation.
+ */
+#define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
+#define MCG_C2_RANGE_MASK (0x30U)
+#define MCG_C2_RANGE_SHIFT (4U)
+/*! RANGE - Frequency Range Select
+ * 0b00..Encoding 0 - Low frequency range selected for the crystal oscillator .
+ * 0b01..Encoding 1 - High frequency range selected for the crystal oscillator .
+ * 0b1x..Encoding 2 - Very high frequency range selected for the crystal oscillator .
+ */
+#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
+#define MCG_C2_FCFTRIM_MASK (0x40U)
+#define MCG_C2_FCFTRIM_SHIFT (6U)
+#define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
+#define MCG_C2_LOCRE0_MASK (0x80U)
+#define MCG_C2_LOCRE0_SHIFT (7U)
+/*! LOCRE0 - Loss of Clock Reset Enable
+ * 0b0..Interrupt request is generated on a loss of OSC0 external reference clock.
+ * 0b1..Generate a reset request on a loss of OSC0 external reference clock.
+ */
+#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
+/*! @} */
+
+/*! @name C3 - MCG Control 3 Register */
+/*! @{ */
+#define MCG_C3_SCTRIM_MASK (0xFFU)
+#define MCG_C3_SCTRIM_SHIFT (0U)
+#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
+/*! @} */
+
+/*! @name C4 - MCG Control 4 Register */
+/*! @{ */
+#define MCG_C4_SCFTRIM_MASK (0x1U)
+#define MCG_C4_SCFTRIM_SHIFT (0U)
+#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
+#define MCG_C4_FCTRIM_MASK (0x1EU)
+#define MCG_C4_FCTRIM_SHIFT (1U)
+#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK (0x60U)
+#define MCG_C4_DRST_DRS_SHIFT (5U)
+/*! DRST_DRS - DCO Range Select
+ * 0b00..Encoding 0 - Low range (reset default).
+ * 0b01..Encoding 1 - Mid range.
+ * 0b10..Encoding 2 - Mid-high range.
+ * 0b11..Encoding 3 - High range.
+ */
+#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK (0x80U)
+#define MCG_C4_DMX32_SHIFT (7U)
+/*! DMX32 - DCO Maximum Frequency with 32.768 kHz Reference
+ * 0b0..DCO has a default range of 25%.
+ * 0b1..DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
+ */
+#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
+/*! @} */
+
+/*! @name C5 - MCG Control 5 Register */
+/*! @{ */
+#define MCG_C5_PRDIV_MASK (0x7U)
+#define MCG_C5_PRDIV_SHIFT (0U)
+/*! PRDIV - PLL External Reference Divider
+ * 0b000..Divide Factor is 1
+ * 0b001..Divide Factor is 2
+ * 0b010..Divide Factor is 3
+ * 0b011..Divide Factor is 4
+ * 0b100..Divide Factor is 5
+ * 0b101..Divide Factor is 6
+ * 0b110..Divide Factor is 7
+ * 0b111..Divide Factor is 8
+ */
+#define MCG_C5_PRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV_SHIFT)) & MCG_C5_PRDIV_MASK)
+#define MCG_C5_PLLSTEN_MASK (0x20U)
+#define MCG_C5_PLLSTEN_SHIFT (5U)
+/*! PLLSTEN - PLL Stop Enable
+ * 0b0..MCGPLLCLK and MCGPLLCLK2X are disabled in any of the Stop modes.
+ * 0b1..MCGPLLCLK and MCGPLLCLK2X are enabled if system is in Normal Stop mode.
+ */
+#define MCG_C5_PLLSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN_SHIFT)) & MCG_C5_PLLSTEN_MASK)
+#define MCG_C5_PLLCLKEN_MASK (0x40U)
+#define MCG_C5_PLLCLKEN_SHIFT (6U)
+/*! PLLCLKEN - PLL Clock Enable
+ * 0b0..MCGPLLCLK is inactive.
+ * 0b1..MCGPLLCLK is active.
+ */
+#define MCG_C5_PLLCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN_SHIFT)) & MCG_C5_PLLCLKEN_MASK)
+/*! @} */
+
+/*! @name C6 - MCG Control 6 Register */
+/*! @{ */
+#define MCG_C6_VDIV_MASK (0x1FU)
+#define MCG_C6_VDIV_SHIFT (0U)
+/*! VDIV - VCO Divider
+ * 0b00000..Multiply Factor is 16
+ * 0b00001..Multiply Factor is 17
+ * 0b00010..Multiply Factor is 18
+ * 0b00011..Multiply Factor is 19
+ * 0b00100..Multiply Factor is 20
+ * 0b00101..Multiply Factor is 21
+ * 0b00110..Multiply Factor is 22
+ * 0b00111..Multiply Factor is 23
+ * 0b01000..Multiply Factor is 24
+ * 0b01001..Multiply Factor is 25
+ * 0b01010..Multiply Factor is 26
+ * 0b01011..Multiply Factor is 27
+ * 0b01100..Multiply Factor is 28
+ * 0b01101..Multiply Factor is 29
+ * 0b01110..Multiply Factor is 30
+ * 0b01111..Multiply Factor is 31
+ * 0b10000..Multiply Factor is 32
+ * 0b10001..Multiply Factor is 33
+ * 0b10010..Multiply Factor is 34
+ * 0b10011..Multiply Factor is 35
+ * 0b10100..Multiply Factor is 36
+ * 0b10101..Multiply Factor is 37
+ * 0b10110..Multiply Factor is 38
+ * 0b10111..Multiply Factor is 39
+ * 0b11000..Multiply Factor is 40
+ * 0b11001..Multiply Factor is 41
+ * 0b11010..Multiply Factor is 42
+ * 0b11011..Multiply Factor is 43
+ * 0b11100..Multiply Factor is 44
+ * 0b11101..Multiply Factor is 45
+ * 0b11110..Multiply Factor is 46
+ * 0b11111..Multiply Factor is 47
+ */
+#define MCG_C6_VDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV_SHIFT)) & MCG_C6_VDIV_MASK)
+#define MCG_C6_CME0_MASK (0x20U)
+#define MCG_C6_CME0_SHIFT (5U)
+/*! CME0 - Clock Monitor Enable
+ * 0b0..External clock monitor is disabled for OSC0.
+ * 0b1..External clock monitor is enabled for OSC0.
+ */
+#define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
+#define MCG_C6_PLLS_MASK (0x40U)
+#define MCG_C6_PLLS_SHIFT (6U)
+/*! PLLS - PLL Select
+ * 0b0..FLL is selected.
+ * 0b1..PLLCS output clock is selected (PRDIV0 bits of PLL in the C5 register need to be programmed to the correct divider to generate a PLL reference clock in the range specified in the data sheet (fpll_ref) prior to setting the PLLS bit).
+ */
+#define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
+#define MCG_C6_LOLIE0_MASK (0x80U)
+#define MCG_C6_LOLIE0_SHIFT (7U)
+/*! LOLIE0 - Loss of Lock Interrrupt Enable
+ * 0b0..No interrupt request is generated on loss of lock.
+ * 0b1..Generate an interrupt request on loss of lock.
+ */
+#define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
+/*! @} */
+
+/*! @name S - MCG Status Register */
+/*! @{ */
+#define MCG_S_IRCST_MASK (0x1U)
+#define MCG_S_IRCST_SHIFT (0U)
+/*! IRCST - Internal Reference Clock Status
+ * 0b0..Source of internal reference clock is the slow clock (32 kHz IRC).
+ * 0b1..Source of internal reference clock is the fast clock (4 MHz IRC).
+ */
+#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
+#define MCG_S_OSCINIT0_MASK (0x2U)
+#define MCG_S_OSCINIT0_SHIFT (1U)
+#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
+#define MCG_S_CLKST_MASK (0xCU)
+#define MCG_S_CLKST_SHIFT (2U)
+/*! CLKST - Clock Mode Status
+ * 0b00..Encoding 0 - Output of the FLL is selected (reset default).
+ * 0b01..Encoding 1 - Internal reference clock is selected.
+ * 0b10..Encoding 2 - External reference clock is selected.
+ * 0b11..Encoding 3 - Output of the PLL is selected.
+ */
+#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK (0x10U)
+#define MCG_S_IREFST_SHIFT (4U)
+/*! IREFST - Internal Reference Status
+ * 0b0..Source of FLL reference clock is the external reference clock.
+ * 0b1..Source of FLL reference clock is the internal reference clock.
+ */
+#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
+#define MCG_S_PLLST_MASK (0x20U)
+#define MCG_S_PLLST_SHIFT (5U)
+/*! PLLST - PLL Select Status
+ * 0b0..Source of PLLS clock is FLL clock.
+ * 0b1..Source of PLLS clock is PLLCS output clock.
+ */
+#define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
+#define MCG_S_LOCK0_MASK (0x40U)
+#define MCG_S_LOCK0_SHIFT (6U)
+/*! LOCK0 - Lock Status
+ * 0b0..PLL is currently unlocked.
+ * 0b1..PLL is currently locked.
+ */
+#define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
+#define MCG_S_LOLS0_MASK (0x80U)
+#define MCG_S_LOLS0_SHIFT (7U)
+/*! LOLS0 - Loss of Lock Status
+ * 0b0..PLL has not lost lock since LOLS 0 was last cleared.
+ * 0b1..PLL has lost lock since LOLS 0 was last cleared.
+ */
+#define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
+/*! @} */
+
+/*! @name SC - MCG Status and Control Register */
+/*! @{ */
+#define MCG_SC_LOCS0_MASK (0x1U)
+#define MCG_SC_LOCS0_SHIFT (0U)
+/*! LOCS0 - OSC0 Loss of Clock Status
+ * 0b0..Loss of OSC0 has not occurred.
+ * 0b1..Loss of OSC0 has occurred.
+ */
+#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
+#define MCG_SC_FCRDIV_MASK (0xEU)
+#define MCG_SC_FCRDIV_SHIFT (1U)
+/*! FCRDIV - Fast Clock Internal Reference Divider
+ * 0b000..Divide Factor is 1
+ * 0b001..Divide Factor is 2.
+ * 0b010..Divide Factor is 4.
+ * 0b011..Divide Factor is 8.
+ * 0b100..Divide Factor is 16
+ * 0b101..Divide Factor is 32
+ * 0b110..Divide Factor is 64
+ * 0b111..Divide Factor is 128.
+ */
+#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK (0x10U)
+#define MCG_SC_FLTPRSRV_SHIFT (4U)
+/*! FLTPRSRV - FLL Filter Preserve Enable
+ * 0b0..FLL filter and FLL frequency will reset on changes to currect clock mode.
+ * 0b1..Fll filter and FLL frequency retain their previous values during new clock mode change.
+ */
+#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
+#define MCG_SC_ATMF_MASK (0x20U)
+#define MCG_SC_ATMF_SHIFT (5U)
+/*! ATMF - Automatic Trim Machine Fail Flag
+ * 0b0..Automatic Trim Machine completed normally.
+ * 0b1..Automatic Trim Machine failed.
+ */
+#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
+#define MCG_SC_ATMS_MASK (0x40U)
+#define MCG_SC_ATMS_SHIFT (6U)
+/*! ATMS - Automatic Trim Machine Select
+ * 0b0..32 kHz Internal Reference Clock selected.
+ * 0b1..4 MHz Internal Reference Clock selected.
+ */
+#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
+#define MCG_SC_ATME_MASK (0x80U)
+#define MCG_SC_ATME_SHIFT (7U)
+/*! ATME - Automatic Trim Machine Enable
+ * 0b0..Auto Trim Machine disabled.
+ * 0b1..Auto Trim Machine enabled.
+ */
+#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
+/*! @} */
+
+/*! @name ATCVH - MCG Auto Trim Compare Value High Register */
+/*! @{ */
+#define MCG_ATCVH_ATCVH_MASK (0xFFU)
+#define MCG_ATCVH_ATCVH_SHIFT (0U)
+#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
+/*! @} */
+
+/*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
+/*! @{ */
+#define MCG_ATCVL_ATCVL_MASK (0xFFU)
+#define MCG_ATCVL_ATCVL_SHIFT (0U)
+#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
+/*! @} */
+
+/*! @name C7 - MCG Control 7 Register */
+/*! @{ */
+#define MCG_C7_OSCSEL_MASK (0x3U)
+#define MCG_C7_OSCSEL_SHIFT (0U)
+/*! OSCSEL - MCG OSC Clock Select
+ * 0b00..Selects Oscillator (OSCCLK0).
+ * 0b01..Selects 32 kHz RTC Oscillator.
+ * 0b10..Selects Oscillator (OSCCLK1).
+ * 0b11..RESERVED
+ */
+#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
+/*! @} */
+
+/*! @name C8 - MCG Control 8 Register */
+/*! @{ */
+#define MCG_C8_LOCS1_MASK (0x1U)
+#define MCG_C8_LOCS1_SHIFT (0U)
+/*! LOCS1 - RTC Loss of Clock Status
+ * 0b0..Loss of RTC has not occur.
+ * 0b1..Loss of RTC has occur
+ */
+#define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
+#define MCG_C8_CME1_MASK (0x20U)
+#define MCG_C8_CME1_SHIFT (5U)
+/*! CME1 - Clock Monitor Enable1
+ * 0b0..External clock monitor is disabled for RTC clock.
+ * 0b1..External clock monitor is enabled for RTC clock.
+ */
+#define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
+#define MCG_C8_LOLRE_MASK (0x40U)
+#define MCG_C8_LOLRE_SHIFT (6U)
+/*! LOLRE - PLL Loss of Lock Reset Enable
+ * 0b0..Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable bit must also be set to generate the interrupt request.
+ * 0b1..Generate a reset request on a PLL loss of lock indication.
+ */
+#define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
+#define MCG_C8_LOCRE1_MASK (0x80U)
+#define MCG_C8_LOCRE1_SHIFT (7U)
+/*! LOCRE1 - Loss of Clock Reset Enable
+ * 0b0..Interrupt request is generated on a loss of RTC external reference clock.
+ * 0b1..Generate a reset request on a loss of RTC external reference clock
+ */
+#define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
+/*! @} */
+
+/*! @name C9 - MCG Control 9 Register */
+/*! @{ */
+#define MCG_C9_EXT_PLL_LOCS_MASK (0x1U)
+#define MCG_C9_EXT_PLL_LOCS_SHIFT (0U)
+/*! EXT_PLL_LOCS - External PLL Loss of Clock Status
+ * 0b0..Loss of MCG EXT_PLL has not occurred.
+ * 0b1..Loss of MCG EXT_PLL has occurred.
+ */
+#define MCG_C9_EXT_PLL_LOCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C9_EXT_PLL_LOCS_SHIFT)) & MCG_C9_EXT_PLL_LOCS_MASK)
+#define MCG_C9_PLL_LOCRE_MASK (0x10U)
+#define MCG_C9_PLL_LOCRE_SHIFT (4U)
+/*! PLL_LOCRE - MCG External PLL Loss of Clock Reset Enable
+ * 0b0..Interrupt request is generated on a invalid or loss of the MCG external PLL clock.
+ * 0b1..Generates a system reset request on a invalid or loss of the MCG external PLL clock.
+ */
+#define MCG_C9_PLL_LOCRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C9_PLL_LOCRE_SHIFT)) & MCG_C9_PLL_LOCRE_MASK)
+#define MCG_C9_PLL_CME_MASK (0x20U)
+#define MCG_C9_PLL_CME_SHIFT (5U)
+/*! PLL_CME - MCG External PLL Clock Monitor Enable
+ * 0b0..External clock monitor is disabled for EXT_PLL clock.
+ * 0b1..External clock monitor is enabled for EXT_PLL clock.
+ */
+#define MCG_C9_PLL_CME(x) (((uint8_t)(((uint8_t)(x)) << MCG_C9_PLL_CME_SHIFT)) & MCG_C9_PLL_CME_MASK)
+/*! @} */
+
+/*! @name C11 - MCG Control 11 Register */
+/*! @{ */
+#define MCG_C11_PLLCS_MASK (0x10U)
+#define MCG_C11_PLLCS_SHIFT (4U)
+/*! PLLCS - PLL Clock Select
+ * 0b0..PLL0 output clock is selected.
+ * 0b1..External PLL clock is selected.
+ */
+#define MCG_C11_PLLCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C11_PLLCS_SHIFT)) & MCG_C11_PLLCS_MASK)
+/*! @} */
+
+/*! @name S2 - MCG Status 2 Register */
+/*! @{ */
+#define MCG_S2_PLLCST_MASK (0x10U)
+#define MCG_S2_PLLCST_SHIFT (4U)
+/*! PLLCST - PLL Clock Select Status
+ * 0b0..Source of PLLCS is PLL clock.
+ * 0b1..Source of PLLCS is EXT_PLL clock.
+ */
+#define MCG_S2_PLLCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S2_PLLCST_SHIFT)) & MCG_S2_PLLCST_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG ((MCG_Type *)MCG_BASE)
+/** Array initializer of MCG peripheral base addresses */
+#define MCG_BASE_ADDRS { MCG_BASE }
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASE_PTRS { MCG }
+/* MCG C5[PLLCLKEN0] backward compatibility */
+#define MCG_C5_PLLCLKEN0_MASK (MCG_C5_PLLCLKEN_MASK)
+#define MCG_C5_PLLCLKEN0_SHIFT (MCG_C5_PLLCLKEN_SHIFT)
+#define MCG_C5_PLLCLKEN0_WIDTH (MCG_C5_PLLCLKEN_WIDTH)
+#define MCG_C5_PLLCLKEN0(x) (MCG_C5_PLLCLKEN(x))
+
+/* MCG C5[PLLSTEN0] backward compatibility */
+#define MCG_C5_PLLSTEN0_MASK (MCG_C5_PLLSTEN_MASK)
+#define MCG_C5_PLLSTEN0_SHIFT (MCG_C5_PLLSTEN_SHIFT)
+#define MCG_C5_PLLSTEN0_WIDTH (MCG_C5_PLLSTEN_WIDTH)
+#define MCG_C5_PLLSTEN0(x) (MCG_C5_PLLSTEN(x))
+
+/* MCG C5[PRDIV0] backward compatibility */
+#define MCG_C5_PRDIV0_MASK (MCG_C5_PRDIV_MASK)
+#define MCG_C5_PRDIV0_SHIFT (MCG_C5_PRDIV_SHIFT)
+#define MCG_C5_PRDIV0_WIDTH (MCG_C5_PRDIV_WIDTH)
+#define MCG_C5_PRDIV0(x) (MCG_C5_PRDIV(x))
+
+/* MCG C6[VDIV0] backward compatibility */
+#define MCG_C6_VDIV0_MASK (MCG_C6_VDIV_MASK)
+#define MCG_C6_VDIV0_SHIFT (MCG_C6_VDIV_SHIFT)
+#define MCG_C6_VDIV0_WIDTH (MCG_C6_VDIV_WIDTH)
+#define MCG_C6_VDIV0(x) (MCG_C6_VDIV(x))
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[8];
+ __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+ __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+ __IO uint32_t CR; /**< Control Register, offset: 0xC */
+ __IO uint32_t ISCR; /**< Interrupt Status Register, offset: 0x10 */
+ __IO uint32_t ETBCC; /**< ETB Counter Control register, offset: 0x14 */
+ __IO uint32_t ETBRL; /**< ETB Reload register, offset: 0x18 */
+ __I uint32_t ETBCNT; /**< ETB Counter Value register, offset: 0x1C */
+ __I uint32_t FADR; /**< Fault address register, offset: 0x20 */
+ __I uint32_t FATR; /**< Fault attributes register, offset: 0x24 */
+ __I uint32_t FDR; /**< Fault data register, offset: 0x28 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t PID; /**< Process ID register, offset: 0x30 */
+ uint8_t RESERVED_2[12];
+ __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
+} MCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
+/*! @{ */
+#define MCM_PLASC_ASC_MASK (0xFFU)
+#define MCM_PLASC_ASC_SHIFT (0U)
+/*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port.
+ * 0b00000000..A bus slave connection to AXBS input port n is absent
+ * 0b00000001..A bus slave connection to AXBS input port n is present
+ */
+#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
+/*! @} */
+
+/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
+/*! @{ */
+#define MCM_PLAMC_AMC_MASK (0xFFU)
+#define MCM_PLAMC_AMC_SHIFT (0U)
+/*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.
+ * 0b00000000..A bus master connection to AXBS input port n is absent
+ * 0b00000001..A bus master connection to AXBS input port n is present
+ */
+#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
+/*! @} */
+
+/*! @name CR - Control Register */
+/*! @{ */
+#define MCM_CR_SRAMUAP_MASK (0x3000000U)
+#define MCM_CR_SRAMUAP_SHIFT (24U)
+/*! SRAMUAP - SRAM_U arbitration priority
+ * 0b00..Round robin
+ * 0b01..Special round robin (favors SRAM backoor accesses over the processor)
+ * 0b10..Fixed priority. Processor has highest, backdoor has lowest
+ * 0b11..Fixed priority. Backdoor has highest, processor has lowest
+ */
+#define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)
+#define MCM_CR_SRAMUWP_MASK (0x4000000U)
+#define MCM_CR_SRAMUWP_SHIFT (26U)
+#define MCM_CR_SRAMUWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK)
+#define MCM_CR_SRAMLAP_MASK (0x30000000U)
+#define MCM_CR_SRAMLAP_SHIFT (28U)
+/*! SRAMLAP - SRAM_L arbitration priority
+ * 0b00..Round robin
+ * 0b01..Special round robin (favors SRAM backoor accesses over the processor)
+ * 0b10..Fixed priority. Processor has highest, backdoor has lowest
+ * 0b11..Fixed priority. Backdoor has highest, processor has lowest
+ */
+#define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)
+#define MCM_CR_SRAMLWP_MASK (0x40000000U)
+#define MCM_CR_SRAMLWP_SHIFT (30U)
+#define MCM_CR_SRAMLWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK)
+/*! @} */
+
+/*! @name ISCR - Interrupt Status Register */
+/*! @{ */
+#define MCM_ISCR_IRQ_MASK (0x2U)
+#define MCM_ISCR_IRQ_SHIFT (1U)
+/*! IRQ - Normal Interrupt Pending
+ * 0b0..No pending interrupt
+ * 0b1..Due to the ETB counter expiring, a normal interrupt is pending
+ */
+#define MCM_ISCR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_IRQ_SHIFT)) & MCM_ISCR_IRQ_MASK)
+#define MCM_ISCR_NMI_MASK (0x4U)
+#define MCM_ISCR_NMI_SHIFT (2U)
+/*! NMI - Non-maskable Interrupt Pending
+ * 0b0..No pending NMI
+ * 0b1..Due to the ETB counter expiring, an NMI is pending
+ */
+#define MCM_ISCR_NMI(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_NMI_SHIFT)) & MCM_ISCR_NMI_MASK)
+#define MCM_ISCR_DHREQ_MASK (0x8U)
+#define MCM_ISCR_DHREQ_SHIFT (3U)
+/*! DHREQ - Debug Halt Request Indicator
+ * 0b0..No debug halt request
+ * 0b1..Debug halt request initiated
+ */
+#define MCM_ISCR_DHREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_DHREQ_SHIFT)) & MCM_ISCR_DHREQ_MASK)
+#define MCM_ISCR_FIOC_MASK (0x100U)
+#define MCM_ISCR_FIOC_SHIFT (8U)
+/*! FIOC - FPU invalid operation interrupt status
+ * 0b0..No interrupt
+ * 0b1..Interrupt occurred
+ */
+#define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
+#define MCM_ISCR_FDZC_MASK (0x200U)
+#define MCM_ISCR_FDZC_SHIFT (9U)
+/*! FDZC - FPU divide-by-zero interrupt status
+ * 0b0..No interrupt
+ * 0b1..Interrupt occurred
+ */
+#define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
+#define MCM_ISCR_FOFC_MASK (0x400U)
+#define MCM_ISCR_FOFC_SHIFT (10U)
+/*! FOFC - FPU overflow interrupt status
+ * 0b0..No interrupt
+ * 0b1..Interrupt occurred
+ */
+#define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
+#define MCM_ISCR_FUFC_MASK (0x800U)
+#define MCM_ISCR_FUFC_SHIFT (11U)
+/*! FUFC - FPU underflow interrupt status
+ * 0b0..No interrupt
+ * 0b1..Interrupt occurred
+ */
+#define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
+#define MCM_ISCR_FIXC_MASK (0x1000U)
+#define MCM_ISCR_FIXC_SHIFT (12U)
+/*! FIXC - FPU inexact interrupt status
+ * 0b0..No interrupt
+ * 0b1..Interrupt occurred
+ */
+#define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
+#define MCM_ISCR_FIDC_MASK (0x8000U)
+#define MCM_ISCR_FIDC_SHIFT (15U)
+/*! FIDC - FPU input denormal interrupt status
+ * 0b0..No interrupt
+ * 0b1..Interrupt occurred
+ */
+#define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
+#define MCM_ISCR_FIOCE_MASK (0x1000000U)
+#define MCM_ISCR_FIOCE_SHIFT (24U)
+/*! FIOCE - FPU invalid operation interrupt enable
+ * 0b0..Disable interrupt
+ * 0b1..Enable interrupt
+ */
+#define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
+#define MCM_ISCR_FDZCE_MASK (0x2000000U)
+#define MCM_ISCR_FDZCE_SHIFT (25U)
+/*! FDZCE - FPU divide-by-zero interrupt enable
+ * 0b0..Disable interrupt
+ * 0b1..Enable interrupt
+ */
+#define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
+#define MCM_ISCR_FOFCE_MASK (0x4000000U)
+#define MCM_ISCR_FOFCE_SHIFT (26U)
+/*! FOFCE - FPU overflow interrupt enable
+ * 0b0..Disable interrupt
+ * 0b1..Enable interrupt
+ */
+#define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
+#define MCM_ISCR_FUFCE_MASK (0x8000000U)
+#define MCM_ISCR_FUFCE_SHIFT (27U)
+/*! FUFCE - FPU underflow interrupt enable
+ * 0b0..Disable interrupt
+ * 0b1..Enable interrupt
+ */
+#define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
+#define MCM_ISCR_FIXCE_MASK (0x10000000U)
+#define MCM_ISCR_FIXCE_SHIFT (28U)
+/*! FIXCE - FPU inexact interrupt enable
+ * 0b0..Disable interrupt
+ * 0b1..Enable interrupt
+ */
+#define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
+#define MCM_ISCR_FIDCE_MASK (0x80000000U)
+#define MCM_ISCR_FIDCE_SHIFT (31U)
+/*! FIDCE - FPU input denormal interrupt enable
+ * 0b0..Disable interrupt
+ * 0b1..Enable interrupt
+ */
+#define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
+/*! @} */
+
+/*! @name ETBCC - ETB Counter Control register */
+/*! @{ */
+#define MCM_ETBCC_CNTEN_MASK (0x1U)
+#define MCM_ETBCC_CNTEN_SHIFT (0U)
+/*! CNTEN - Counter Enable
+ * 0b0..ETB counter disabled
+ * 0b1..ETB counter enabled
+ */
+#define MCM_ETBCC_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK)
+#define MCM_ETBCC_RSPT_MASK (0x6U)
+#define MCM_ETBCC_RSPT_SHIFT (1U)
+/*! RSPT - Response Type
+ * 0b00..No response when the ETB count expires
+ * 0b01..Generate a normal interrupt when the ETB count expires
+ * 0b10..Generate an NMI when the ETB count expires
+ * 0b11..Generate a debug halt when the ETB count expires
+ */
+#define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK)
+#define MCM_ETBCC_RLRQ_MASK (0x8U)
+#define MCM_ETBCC_RLRQ_SHIFT (3U)
+/*! RLRQ - Reload Request
+ * 0b0..No effect
+ * 0b1..Clears pending debug halt, NMI, or IRQ interrupt requests
+ */
+#define MCM_ETBCC_RLRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK)
+#define MCM_ETBCC_ETDIS_MASK (0x10U)
+#define MCM_ETBCC_ETDIS_SHIFT (4U)
+/*! ETDIS - ETM-To-TPIU Disable
+ * 0b0..ETM-to-TPIU trace path enabled
+ * 0b1..ETM-to-TPIU trace path disabled
+ */
+#define MCM_ETBCC_ETDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK)
+#define MCM_ETBCC_ITDIS_MASK (0x20U)
+#define MCM_ETBCC_ITDIS_SHIFT (5U)
+/*! ITDIS - ITM-To-TPIU Disable
+ * 0b0..ITM-to-TPIU trace path enabled
+ * 0b1..ITM-to-TPIU trace path disabled
+ */
+#define MCM_ETBCC_ITDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK)
+/*! @} */
+
+/*! @name ETBRL - ETB Reload register */
+/*! @{ */
+#define MCM_ETBRL_RELOAD_MASK (0x7FFU)
+#define MCM_ETBRL_RELOAD_SHIFT (0U)
+#define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK)
+/*! @} */
+
+/*! @name ETBCNT - ETB Counter Value register */
+/*! @{ */
+#define MCM_ETBCNT_COUNTER_MASK (0x7FFU)
+#define MCM_ETBCNT_COUNTER_SHIFT (0U)
+#define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK)
+/*! @} */
+
+/*! @name FADR - Fault address register */
+/*! @{ */
+#define MCM_FADR_ADDRESS_MASK (0xFFFFFFFFU)
+#define MCM_FADR_ADDRESS_SHIFT (0U)
+#define MCM_FADR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK)
+/*! @} */
+
+/*! @name FATR - Fault attributes register */
+/*! @{ */
+#define MCM_FATR_BEDA_MASK (0x1U)
+#define MCM_FATR_BEDA_SHIFT (0U)
+/*! BEDA - Bus error access type
+ * 0b0..Instruction
+ * 0b1..Data
+ */
+#define MCM_FATR_BEDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK)
+#define MCM_FATR_BEMD_MASK (0x2U)
+#define MCM_FATR_BEMD_SHIFT (1U)
+/*! BEMD - Bus error privilege level
+ * 0b0..User mode
+ * 0b1..Supervisor/privileged mode
+ */
+#define MCM_FATR_BEMD(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK)
+#define MCM_FATR_BESZ_MASK (0x30U)
+#define MCM_FATR_BESZ_SHIFT (4U)
+/*! BESZ - Bus error size
+ * 0b00..8-bit access
+ * 0b01..16-bit access
+ * 0b10..32-bit access
+ * 0b11..Reserved
+ */
+#define MCM_FATR_BESZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK)
+#define MCM_FATR_BEWT_MASK (0x80U)
+#define MCM_FATR_BEWT_SHIFT (7U)
+/*! BEWT - Bus error write
+ * 0b0..Read access
+ * 0b1..Write access
+ */
+#define MCM_FATR_BEWT(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK)
+#define MCM_FATR_BEMN_MASK (0xF00U)
+#define MCM_FATR_BEMN_SHIFT (8U)
+#define MCM_FATR_BEMN(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK)
+#define MCM_FATR_BEOVR_MASK (0x80000000U)
+#define MCM_FATR_BEOVR_SHIFT (31U)
+/*! BEOVR - Bus error overrun
+ * 0b0..No bus error overrun
+ * 0b1..Bus error overrun occurred. The FADR and FDR registers and the other FATR bits are not updated to reflect this new bus error.
+ */
+#define MCM_FATR_BEOVR(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK)
+/*! @} */
+
+/*! @name FDR - Fault data register */
+/*! @{ */
+#define MCM_FDR_DATA_MASK (0xFFFFFFFFU)
+#define MCM_FDR_DATA_SHIFT (0U)
+#define MCM_FDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK)
+/*! @} */
+
+/*! @name PID - Process ID register */
+/*! @{ */
+#define MCM_PID_PID_MASK (0xFFU)
+#define MCM_PID_PID_SHIFT (0U)
+#define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK)
+/*! @} */
+
+/*! @name CPO - Compute Operation Control Register */
+/*! @{ */
+#define MCM_CPO_CPOREQ_MASK (0x1U)
+#define MCM_CPO_CPOREQ_SHIFT (0U)
+/*! CPOREQ - Compute Operation request
+ * 0b0..Request is cleared.
+ * 0b1..Request Compute Operation.
+ */
+#define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
+#define MCM_CPO_CPOACK_MASK (0x2U)
+#define MCM_CPO_CPOACK_SHIFT (1U)
+/*! CPOACK - Compute Operation acknowledge
+ * 0b0..Compute operation entry has not completed or compute operation exit has completed.
+ * 0b1..Compute operation entry has completed or compute operation exit has not completed.
+ */
+#define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
+#define MCM_CPO_CPOWOI_MASK (0x4U)
+#define MCM_CPO_CPOWOI_SHIFT (2U)
+/*! CPOWOI - Compute Operation wakeup on interrupt
+ * 0b0..No effect.
+ * 0b1..When set, the CPOREQ is cleared on any interrupt or exception vector fetch.
+ */
+#define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE (0xE0080000u)
+/** Peripheral MCM base pointer */
+#define MCM ((MCM_Type *)MCM_BASE)
+/** Array initializer of MCM peripheral base addresses */
+#define MCM_BASE_ADDRS { MCM_BASE }
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASE_PTRS { MCM }
+/** Interrupt vectors for the MCM peripheral type */
+#define MCM_IRQS { MCM_IRQn }
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+ __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
+ __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
+ __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
+ __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
+ __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
+ __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
+ __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
+ __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
+ __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+ __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+ __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+ __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+ __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
+ __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
+ __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
+ __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
+} NV_Type;
+
+/* ----------------------------------------------------------------------------
+ -- NV Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/*! @name BACKKEY3 - Backdoor Comparison Key 3. */
+/*! @{ */
+#define NV_BACKKEY3_KEY_MASK (0xFFU)
+#define NV_BACKKEY3_KEY_SHIFT (0U)
+#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
+/*! @} */
+
+/*! @name BACKKEY2 - Backdoor Comparison Key 2. */
+/*! @{ */
+#define NV_BACKKEY2_KEY_MASK (0xFFU)
+#define NV_BACKKEY2_KEY_SHIFT (0U)
+#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
+/*! @} */
+
+/*! @name BACKKEY1 - Backdoor Comparison Key 1. */
+/*! @{ */
+#define NV_BACKKEY1_KEY_MASK (0xFFU)
+#define NV_BACKKEY1_KEY_SHIFT (0U)
+#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
+/*! @} */
+
+/*! @name BACKKEY0 - Backdoor Comparison Key 0. */
+/*! @{ */
+#define NV_BACKKEY0_KEY_MASK (0xFFU)
+#define NV_BACKKEY0_KEY_SHIFT (0U)
+#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
+/*! @} */
+
+/*! @name BACKKEY7 - Backdoor Comparison Key 7. */
+/*! @{ */
+#define NV_BACKKEY7_KEY_MASK (0xFFU)
+#define NV_BACKKEY7_KEY_SHIFT (0U)
+#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
+/*! @} */
+
+/*! @name BACKKEY6 - Backdoor Comparison Key 6. */
+/*! @{ */
+#define NV_BACKKEY6_KEY_MASK (0xFFU)
+#define NV_BACKKEY6_KEY_SHIFT (0U)
+#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
+/*! @} */
+
+/*! @name BACKKEY5 - Backdoor Comparison Key 5. */
+/*! @{ */
+#define NV_BACKKEY5_KEY_MASK (0xFFU)
+#define NV_BACKKEY5_KEY_SHIFT (0U)
+#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
+/*! @} */
+
+/*! @name BACKKEY4 - Backdoor Comparison Key 4. */
+/*! @{ */
+#define NV_BACKKEY4_KEY_MASK (0xFFU)
+#define NV_BACKKEY4_KEY_SHIFT (0U)
+#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
+/*! @} */
+
+/*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
+/*! @{ */
+#define NV_FPROT3_PROT_MASK (0xFFU)
+#define NV_FPROT3_PROT_SHIFT (0U)
+#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
+/*! @} */
+
+/*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
+/*! @{ */
+#define NV_FPROT2_PROT_MASK (0xFFU)
+#define NV_FPROT2_PROT_SHIFT (0U)
+#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
+/*! @} */
+
+/*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
+/*! @{ */
+#define NV_FPROT1_PROT_MASK (0xFFU)
+#define NV_FPROT1_PROT_SHIFT (0U)
+#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
+/*! @} */
+
+/*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
+/*! @{ */
+#define NV_FPROT0_PROT_MASK (0xFFU)
+#define NV_FPROT0_PROT_SHIFT (0U)
+#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
+/*! @} */
+
+/*! @name FSEC - Non-volatile Flash Security Register */
+/*! @{ */
+#define NV_FSEC_SEC_MASK (0x3U)
+#define NV_FSEC_SEC_SHIFT (0U)
+/*! SEC - Flash Security
+ * 0b10..MCU security status is unsecure
+ * 0b11..MCU security status is secure
+ */
+#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK (0xCU)
+#define NV_FSEC_FSLACC_SHIFT (2U)
+/*! FSLACC - Freescale Failure Analysis Access Code
+ * 0b10..Freescale factory access denied
+ * 0b11..Freescale factory access granted
+ */
+#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK (0x30U)
+#define NV_FSEC_MEEN_SHIFT (4U)
+/*! MEEN
+ * 0b10..Mass erase is disabled
+ * 0b11..Mass erase is enabled
+ */
+#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK (0xC0U)
+#define NV_FSEC_KEYEN_SHIFT (6U)
+/*! KEYEN - Backdoor Key Security Enable
+ * 0b10..Backdoor key access enabled
+ * 0b11..Backdoor key access disabled
+ */
+#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
+/*! @} */
+
+/*! @name FOPT - Non-volatile Flash Option Register */
+/*! @{ */
+#define NV_FOPT_LPBOOT_MASK (0x1U)
+#define NV_FOPT_LPBOOT_SHIFT (0U)
+/*! LPBOOT
+ * 0b0..Low-power boot
+ * 0b1..Normal boot
+ */
+#define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
+#define NV_FOPT_EZPORT_DIS_MASK (0x2U)
+#define NV_FOPT_EZPORT_DIS_SHIFT (1U)
+/*! EZPORT_DIS
+ * 0b0..EzPort operation is disabled
+ * 0b1..EzPort operation is enabled
+ */
+#define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK)
+#define NV_FOPT_NMI_DIS_MASK (0x4U)
+#define NV_FOPT_NMI_DIS_SHIFT (2U)
+/*! NMI_DIS
+ * 0b0..NMI interrupts are always blocked
+ * 0b1..NMI_b pin/interrupts reset default to enabled
+ */
+#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
+/*! @} */
+
+/*! @name FEPROT - Non-volatile EERAM Protection Register */
+/*! @{ */
+#define NV_FEPROT_EPROT_MASK (0xFFU)
+#define NV_FEPROT_EPROT_SHIFT (0U)
+#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FEPROT_EPROT_SHIFT)) & NV_FEPROT_EPROT_MASK)
+/*! @} */
+
+/*! @name FDPROT - Non-volatile D-Flash Protection Register */
+/*! @{ */
+#define NV_FDPROT_DPROT_MASK (0xFFU)
+#define NV_FDPROT_DPROT_SHIFT (0U)
+#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FDPROT_DPROT_SHIFT)) & NV_FDPROT_DPROT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFE_FlashConfig base address */
+#define FTFE_FlashConfig_BASE (0x400u)
+/** Peripheral FTFE_FlashConfig base pointer */
+#define FTFE_FlashConfig ((NV_Type *)FTFE_FlashConfig_BASE)
+/** Array initializer of NV peripheral base addresses */
+#define NV_BASE_ADDRS { FTFE_FlashConfig_BASE }
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASE_PTRS { FTFE_FlashConfig }
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t DIV; /**< OSC_DIV, offset: 0x2 */
+} OSC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- OSC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/*! @name CR - OSC Control Register */
+/*! @{ */
+#define OSC_CR_SC16P_MASK (0x1U)
+#define OSC_CR_SC16P_SHIFT (0U)
+/*! SC16P - Oscillator 16 pF Capacitor Load Configure
+ * 0b0..Disable the selection.
+ * 0b1..Add 16 pF capacitor to the oscillator load.
+ */
+#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
+#define OSC_CR_SC8P_MASK (0x2U)
+#define OSC_CR_SC8P_SHIFT (1U)
+/*! SC8P - Oscillator 8 pF Capacitor Load Configure
+ * 0b0..Disable the selection.
+ * 0b1..Add 8 pF capacitor to the oscillator load.
+ */
+#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
+#define OSC_CR_SC4P_MASK (0x4U)
+#define OSC_CR_SC4P_SHIFT (2U)
+/*! SC4P - Oscillator 4 pF Capacitor Load Configure
+ * 0b0..Disable the selection.
+ * 0b1..Add 4 pF capacitor to the oscillator load.
+ */
+#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
+#define OSC_CR_SC2P_MASK (0x8U)
+#define OSC_CR_SC2P_SHIFT (3U)
+/*! SC2P - Oscillator 2 pF Capacitor Load Configure
+ * 0b0..Disable the selection.
+ * 0b1..Add 2 pF capacitor to the oscillator load.
+ */
+#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
+#define OSC_CR_EREFSTEN_MASK (0x20U)
+#define OSC_CR_EREFSTEN_SHIFT (5U)
+/*! EREFSTEN - External Reference Stop Enable
+ * 0b0..External reference clock is disabled in Stop mode.
+ * 0b1..External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode.
+ */
+#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
+#define OSC_CR_ERCLKEN_MASK (0x80U)
+#define OSC_CR_ERCLKEN_SHIFT (7U)
+/*! ERCLKEN - External Reference Enable
+ * 0b0..External reference clock is inactive.
+ * 0b1..External reference clock is enabled.
+ */
+#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
+/*! @} */
+
+/*! @name DIV - OSC_DIV */
+/*! @{ */
+#define OSC_DIV_ERPS_MASK (0xC0U)
+#define OSC_DIV_ERPS_SHIFT (6U)
+/*! ERPS
+ * 0b00..The divisor ratio is 1.
+ * 0b01..The divisor ratio is 2.
+ * 0b10..The divisor ratio is 4.
+ * 0b11..The divisor ratio is 8.
+ */
+#define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x)) << OSC_DIV_ERPS_SHIFT)) & OSC_DIV_ERPS_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC base address */
+#define OSC_BASE (0x40065000u)
+/** Peripheral OSC base pointer */
+#define OSC ((OSC_Type *)OSC_BASE)
+/** Array initializer of OSC peripheral base addresses */
+#define OSC_BASE_ADDRS { OSC_BASE }
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASE_PTRS { OSC }
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PDB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
+ * @{
+ */
+
+/** PDB - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
+ __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
+ __I uint32_t CNT; /**< Counter register, offset: 0x8 */
+ __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
+ struct { /* offset: 0x10, array step: 0x28 */
+ __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
+ __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
+ __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
+ uint8_t RESERVED_0[24];
+ } CH[2];
+ uint8_t RESERVED_0[240];
+ struct { /* offset: 0x150, array step: 0x8 */
+ __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
+ __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
+ } DAC[2];
+ uint8_t RESERVED_1[48];
+ __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
+ __IO uint32_t PODLY[4]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
+} PDB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PDB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Masks PDB Register Masks
+ * @{
+ */
+
+/*! @name SC - Status and Control register */
+/*! @{ */
+#define PDB_SC_LDOK_MASK (0x1U)
+#define PDB_SC_LDOK_SHIFT (0U)
+#define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
+#define PDB_SC_CONT_MASK (0x2U)
+#define PDB_SC_CONT_SHIFT (1U)
+/*! CONT - Continuous Mode Enable
+ * 0b0..PDB operation in One-Shot mode
+ * 0b1..PDB operation in Continuous mode
+ */
+#define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
+#define PDB_SC_MULT_MASK (0xCU)
+#define PDB_SC_MULT_SHIFT (2U)
+/*! MULT - Multiplication Factor Select for Prescaler
+ * 0b00..Multiplication factor is 1.
+ * 0b01..Multiplication factor is 10.
+ * 0b10..Multiplication factor is 20.
+ * 0b11..Multiplication factor is 40.
+ */
+#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
+#define PDB_SC_PDBIE_MASK (0x20U)
+#define PDB_SC_PDBIE_SHIFT (5U)
+/*! PDBIE - PDB Interrupt Enable
+ * 0b0..PDB interrupt disabled.
+ * 0b1..PDB interrupt enabled.
+ */
+#define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
+#define PDB_SC_PDBIF_MASK (0x40U)
+#define PDB_SC_PDBIF_SHIFT (6U)
+#define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
+#define PDB_SC_PDBEN_MASK (0x80U)
+#define PDB_SC_PDBEN_SHIFT (7U)
+/*! PDBEN - PDB Enable
+ * 0b0..PDB disabled. Counter is off.
+ * 0b1..PDB enabled.
+ */
+#define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
+#define PDB_SC_TRGSEL_MASK (0xF00U)
+#define PDB_SC_TRGSEL_SHIFT (8U)
+/*! TRGSEL - Trigger Input Source Select
+ * 0b0000..Trigger-In 0 is selected.
+ * 0b0001..Trigger-In 1 is selected.
+ * 0b0010..Trigger-In 2 is selected.
+ * 0b0011..Trigger-In 3 is selected.
+ * 0b0100..Trigger-In 4 is selected.
+ * 0b0101..Trigger-In 5 is selected.
+ * 0b0110..Trigger-In 6 is selected.
+ * 0b0111..Trigger-In 7 is selected.
+ * 0b1000..Trigger-In 8 is selected.
+ * 0b1001..Trigger-In 9 is selected.
+ * 0b1010..Trigger-In 10 is selected.
+ * 0b1011..Trigger-In 11 is selected.
+ * 0b1100..Trigger-In 12 is selected.
+ * 0b1101..Trigger-In 13 is selected.
+ * 0b1110..Trigger-In 14 is selected.
+ * 0b1111..Software trigger is selected.
+ */
+#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
+#define PDB_SC_PRESCALER_MASK (0x7000U)
+#define PDB_SC_PRESCALER_SHIFT (12U)
+/*! PRESCALER - Prescaler Divider Select
+ * 0b000..Counting uses the peripheral clock divided by multiplication factor selected by MULT.
+ * 0b001..Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT.
+ * 0b010..Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT.
+ * 0b011..Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT.
+ * 0b100..Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT.
+ * 0b101..Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT.
+ * 0b110..Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT.
+ * 0b111..Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT.
+ */
+#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
+#define PDB_SC_DMAEN_MASK (0x8000U)
+#define PDB_SC_DMAEN_SHIFT (15U)
+/*! DMAEN - DMA Enable
+ * 0b0..DMA disabled.
+ * 0b1..DMA enabled.
+ */
+#define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
+#define PDB_SC_SWTRIG_MASK (0x10000U)
+#define PDB_SC_SWTRIG_SHIFT (16U)
+#define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
+#define PDB_SC_PDBEIE_MASK (0x20000U)
+#define PDB_SC_PDBEIE_SHIFT (17U)
+/*! PDBEIE - PDB Sequence Error Interrupt Enable
+ * 0b0..PDB sequence error interrupt disabled.
+ * 0b1..PDB sequence error interrupt enabled.
+ */
+#define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
+#define PDB_SC_LDMOD_MASK (0xC0000U)
+#define PDB_SC_LDMOD_SHIFT (18U)
+/*! LDMOD - Load Mode Select
+ * 0b00..The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK.
+ * 0b01..The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK.
+ * 0b10..The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK.
+ * 0b11..The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK.
+ */
+#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
+/*! @} */
+
+/*! @name MOD - Modulus register */
+/*! @{ */
+#define PDB_MOD_MOD_MASK (0xFFFFU)
+#define PDB_MOD_MOD_SHIFT (0U)
+#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
+/*! @} */
+
+/*! @name CNT - Counter register */
+/*! @{ */
+#define PDB_CNT_CNT_MASK (0xFFFFU)
+#define PDB_CNT_CNT_SHIFT (0U)
+#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
+/*! @} */
+
+/*! @name IDLY - Interrupt Delay register */
+/*! @{ */
+#define PDB_IDLY_IDLY_MASK (0xFFFFU)
+#define PDB_IDLY_IDLY_SHIFT (0U)
+#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
+/*! @} */
+
+/*! @name C1 - Channel n Control register 1 */
+/*! @{ */
+#define PDB_C1_EN_MASK (0xFFU)
+#define PDB_C1_EN_SHIFT (0U)
+/*! EN - PDB Channel Pre-Trigger Enable
+ * 0b00000000..PDB channel's corresponding pre-trigger disabled.
+ * 0b00000001..PDB channel's corresponding pre-trigger enabled.
+ */
+#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
+#define PDB_C1_TOS_MASK (0xFF00U)
+#define PDB_C1_TOS_SHIFT (8U)
+/*! TOS - PDB Channel Pre-Trigger Output Select
+ * 0b00000000..PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
+ * 0b00000001..PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.
+ */
+#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
+#define PDB_C1_BB_MASK (0xFF0000U)
+#define PDB_C1_BB_SHIFT (16U)
+/*! BB - PDB Channel Pre-Trigger Back-to-Back Operation Enable
+ * 0b00000000..PDB channel's corresponding pre-trigger back-to-back operation disabled.
+ * 0b00000001..PDB channel's corresponding pre-trigger back-to-back operation enabled.
+ */
+#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
+/*! @} */
+
+/* The count of PDB_C1 */
+#define PDB_C1_COUNT (2U)
+
+/*! @name S - Channel n Status register */
+/*! @{ */
+#define PDB_S_ERR_MASK (0xFFU)
+#define PDB_S_ERR_SHIFT (0U)
+/*! ERR - PDB Channel Sequence Error Flags
+ * 0b00000000..Sequence error not detected on PDB channel's corresponding pre-trigger.
+ * 0b00000001..Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags.
+ */
+#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
+#define PDB_S_CF_MASK (0xFF0000U)
+#define PDB_S_CF_SHIFT (16U)
+#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
+/*! @} */
+
+/* The count of PDB_S */
+#define PDB_S_COUNT (2U)
+
+/*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */
+/*! @{ */
+#define PDB_DLY_DLY_MASK (0xFFFFU)
+#define PDB_DLY_DLY_SHIFT (0U)
+#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
+/*! @} */
+
+/* The count of PDB_DLY */
+#define PDB_DLY_COUNT (2U)
+
+/* The count of PDB_DLY */
+#define PDB_DLY_COUNT2 (2U)
+
+/*! @name INTC - DAC Interval Trigger n Control register */
+/*! @{ */
+#define PDB_INTC_TOE_MASK (0x1U)
+#define PDB_INTC_TOE_SHIFT (0U)
+/*! TOE - DAC Interval Trigger Enable
+ * 0b0..DAC interval trigger disabled.
+ * 0b1..DAC interval trigger enabled.
+ */
+#define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK)
+#define PDB_INTC_EXT_MASK (0x2U)
+#define PDB_INTC_EXT_SHIFT (1U)
+/*! EXT - DAC External Trigger Input Enable
+ * 0b0..DAC external trigger input disabled. DAC interval counter is reset and counting starts when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
+ * 0b1..DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger.
+ */
+#define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK)
+/*! @} */
+
+/* The count of PDB_INTC */
+#define PDB_INTC_COUNT (2U)
+
+/*! @name INT - DAC Interval n register */
+/*! @{ */
+#define PDB_INT_INT_MASK (0xFFFFU)
+#define PDB_INT_INT_SHIFT (0U)
+#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
+/*! @} */
+
+/* The count of PDB_INT */
+#define PDB_INT_COUNT (2U)
+
+/*! @name POEN - Pulse-Out n Enable register */
+/*! @{ */
+#define PDB_POEN_POEN_MASK (0xFFU)
+#define PDB_POEN_POEN_SHIFT (0U)
+/*! POEN - PDB Pulse-Out Enable
+ * 0b00000000..PDB Pulse-Out disabled
+ * 0b00000001..PDB Pulse-Out enabled
+ */
+#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
+/*! @} */
+
+/*! @name PODLY - Pulse-Out n Delay register */
+/*! @{ */
+#define PDB_PODLY_DLY2_MASK (0xFFFFU)
+#define PDB_PODLY_DLY2_SHIFT (0U)
+#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY1_MASK (0xFFFF0000U)
+#define PDB_PODLY_DLY1_SHIFT (16U)
+#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
+/*! @} */
+
+/* The count of PDB_PODLY */
+#define PDB_PODLY_COUNT (4U)
+
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Masks */
+
+
+/* PDB - Peripheral instance base addresses */
+/** Peripheral PDB0 base address */
+#define PDB0_BASE (0x40036000u)
+/** Peripheral PDB0 base pointer */
+#define PDB0 ((PDB_Type *)PDB0_BASE)
+/** Array initializer of PDB peripheral base addresses */
+#define PDB_BASE_ADDRS { PDB0_BASE }
+/** Array initializer of PDB peripheral base pointers */
+#define PDB_BASE_PTRS { PDB0 }
+/** Interrupt vectors for the PDB peripheral type */
+#define PDB_IRQS { PDB0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PDB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[220];
+ __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
+ __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
+ uint8_t RESERVED_1[24];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+ __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+ __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+ } CHANNEL[4];
+} PIT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PIT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/*! @name MCR - PIT Module Control Register */
+/*! @{ */
+#define PIT_MCR_FRZ_MASK (0x1U)
+#define PIT_MCR_FRZ_SHIFT (0U)
+/*! FRZ - Freeze
+ * 0b0..Timers continue to run in Debug mode.
+ * 0b1..Timers are stopped in Debug mode.
+ */
+#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
+#define PIT_MCR_MDIS_MASK (0x2U)
+#define PIT_MCR_MDIS_SHIFT (1U)
+/*! MDIS - Module Disable - (PIT section)
+ * 0b0..Clock for standard PIT timers is enabled.
+ * 0b1..Clock for standard PIT timers is disabled.
+ */
+#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
+/*! @} */
+
+/*! @name LTMR64H - PIT Upper Lifetime Timer Register */
+/*! @{ */
+#define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)
+#define PIT_LTMR64H_LTH_SHIFT (0U)
+#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
+/*! @} */
+
+/*! @name LTMR64L - PIT Lower Lifetime Timer Register */
+/*! @{ */
+#define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)
+#define PIT_LTMR64L_LTL_SHIFT (0U)
+#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
+/*! @} */
+
+/*! @name LDVAL - Timer Load Value Register */
+/*! @{ */
+#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
+#define PIT_LDVAL_TSV_SHIFT (0U)
+#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
+/*! @} */
+
+/* The count of PIT_LDVAL */
+#define PIT_LDVAL_COUNT (4U)
+
+/*! @name CVAL - Current Timer Value Register */
+/*! @{ */
+#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
+#define PIT_CVAL_TVL_SHIFT (0U)
+#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
+/*! @} */
+
+/* The count of PIT_CVAL */
+#define PIT_CVAL_COUNT (4U)
+
+/*! @name TCTRL - Timer Control Register */
+/*! @{ */
+#define PIT_TCTRL_TEN_MASK (0x1U)
+#define PIT_TCTRL_TEN_SHIFT (0U)
+/*! TEN - Timer Enable
+ * 0b0..Timer n is disabled.
+ * 0b1..Timer n is enabled.
+ */
+#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
+#define PIT_TCTRL_TIE_MASK (0x2U)
+#define PIT_TCTRL_TIE_SHIFT (1U)
+/*! TIE - Timer Interrupt Enable
+ * 0b0..Interrupt requests from Timer n are disabled.
+ * 0b1..Interrupt will be requested whenever TIF is set.
+ */
+#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
+#define PIT_TCTRL_CHN_MASK (0x4U)
+#define PIT_TCTRL_CHN_SHIFT (2U)
+/*! CHN - Chain Mode
+ * 0b0..Timer is not chained.
+ * 0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.
+ */
+#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
+/*! @} */
+
+/* The count of PIT_TCTRL */
+#define PIT_TCTRL_COUNT (4U)
+
+/*! @name TFLG - Timer Flag Register */
+/*! @{ */
+#define PIT_TFLG_TIF_MASK (0x1U)
+#define PIT_TFLG_TIF_SHIFT (0U)
+/*! TIF - Timer Interrupt Flag
+ * 0b0..Timeout has not yet occurred.
+ * 0b1..Timeout has occurred.
+ */
+#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
+/*! @} */
+
+/* The count of PIT_TFLG */
+#define PIT_TFLG_COUNT (4U)
+
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT ((PIT_Type *)PIT_BASE)
+/** Array initializer of PIT peripheral base addresses */
+#define PIT_BASE_ADDRS { PIT_BASE }
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASE_PTRS { PIT }
+/** Interrupt vectors for the PIT peripheral type */
+#define PIT_IRQS { { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } }
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+ __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+ __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
+/*! @{ */
+#define PMC_LVDSC1_LVDV_MASK (0x3U)
+#define PMC_LVDSC1_LVDV_SHIFT (0U)
+/*! LVDV - Low-Voltage Detect Voltage Select
+ * 0b00..Low trip point selected (V LVD = V LVDL )
+ * 0b01..High trip point selected (V LVD = V LVDH )
+ * 0b10..Reserved
+ * 0b11..Reserved
+ */
+#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK (0x10U)
+#define PMC_LVDSC1_LVDRE_SHIFT (4U)
+/*! LVDRE - Low-Voltage Detect Reset Enable
+ * 0b0..LVDF does not generate hardware resets
+ * 0b1..Force an MCU reset when LVDF = 1
+ */
+#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
+#define PMC_LVDSC1_LVDIE_MASK (0x20U)
+#define PMC_LVDSC1_LVDIE_SHIFT (5U)
+/*! LVDIE - Low-Voltage Detect Interrupt Enable
+ * 0b0..Hardware interrupt disabled (use polling)
+ * 0b1..Request a hardware interrupt when LVDF = 1
+ */
+#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
+#define PMC_LVDSC1_LVDACK_MASK (0x40U)
+#define PMC_LVDSC1_LVDACK_SHIFT (6U)
+#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
+#define PMC_LVDSC1_LVDF_MASK (0x80U)
+#define PMC_LVDSC1_LVDF_SHIFT (7U)
+/*! LVDF - Low-Voltage Detect Flag
+ * 0b0..Low-voltage event not detected
+ * 0b1..Low-voltage event detected
+ */
+#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
+/*! @} */
+
+/*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
+/*! @{ */
+#define PMC_LVDSC2_LVWV_MASK (0x3U)
+#define PMC_LVDSC2_LVWV_SHIFT (0U)
+/*! LVWV - Low-Voltage Warning Voltage Select
+ * 0b00..Low trip point selected (VLVW = VLVW1)
+ * 0b01..Mid 1 trip point selected (VLVW = VLVW2)
+ * 0b10..Mid 2 trip point selected (VLVW = VLVW3)
+ * 0b11..High trip point selected (VLVW = VLVW4)
+ */
+#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK (0x20U)
+#define PMC_LVDSC2_LVWIE_SHIFT (5U)
+/*! LVWIE - Low-Voltage Warning Interrupt Enable
+ * 0b0..Hardware interrupt disabled (use polling)
+ * 0b1..Request a hardware interrupt when LVWF = 1
+ */
+#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
+#define PMC_LVDSC2_LVWACK_MASK (0x40U)
+#define PMC_LVDSC2_LVWACK_SHIFT (6U)
+#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
+#define PMC_LVDSC2_LVWF_MASK (0x80U)
+#define PMC_LVDSC2_LVWF_SHIFT (7U)
+/*! LVWF - Low-Voltage Warning Flag
+ * 0b0..Low-voltage warning event not detected
+ * 0b1..Low-voltage warning event detected
+ */
+#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
+/*! @} */
+
+/*! @name REGSC - Regulator Status And Control register */
+/*! @{ */
+#define PMC_REGSC_BGBE_MASK (0x1U)
+#define PMC_REGSC_BGBE_SHIFT (0U)
+/*! BGBE - Bandgap Buffer Enable
+ * 0b0..Bandgap buffer not enabled
+ * 0b1..Bandgap buffer enabled
+ */
+#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
+#define PMC_REGSC_REGONS_MASK (0x4U)
+#define PMC_REGSC_REGONS_SHIFT (2U)
+/*! REGONS - Regulator In Run Regulation Status
+ * 0b0..Regulator is in stop regulation or in transition to/from it
+ * 0b1..Regulator is in run regulation
+ */
+#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
+#define PMC_REGSC_ACKISO_MASK (0x8U)
+#define PMC_REGSC_ACKISO_SHIFT (3U)
+/*! ACKISO - Acknowledge Isolation
+ * 0b0..Peripherals and I/O pads are in normal run state.
+ * 0b1..Certain peripherals and I/O pads are in an isolated and latched state.
+ */
+#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
+#define PMC_REGSC_BGEN_MASK (0x10U)
+#define PMC_REGSC_BGEN_SHIFT (4U)
+/*! BGEN - Bandgap Enable In VLPx Operation
+ * 0b0..Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
+ * 0b1..Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
+ */
+#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC ((PMC_Type *)PMC_BASE)
+/** Array initializer of PMC peripheral base addresses */
+#define PMC_BASE_ADDRS { PMC_BASE }
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASE_PTRS { PMC }
+/** Interrupt vectors for the PMC peripheral type */
+#define PMC_IRQS { LVD_LVW_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
+ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
+ uint8_t RESERVED_0[24];
+ __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
+ uint8_t RESERVED_1[28];
+ __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
+ __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
+ __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
+} PORT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PORT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/*! @name PCR - Pin Control Register n */
+/*! @{ */
+#define PORT_PCR_PS_MASK (0x1U)
+#define PORT_PCR_PS_SHIFT (0U)
+/*! PS - Pull Select
+ * 0b0..Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
+ * 0b1..Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
+ */
+#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
+#define PORT_PCR_PE_MASK (0x2U)
+#define PORT_PCR_PE_SHIFT (1U)
+/*! PE - Pull Enable
+ * 0b0..Internal pullup or pulldown resistor is not enabled on the corresponding pin.
+ * 0b1..Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
+ */
+#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
+#define PORT_PCR_SRE_MASK (0x4U)
+#define PORT_PCR_SRE_SHIFT (2U)
+/*! SRE - Slew Rate Enable
+ * 0b0..Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
+ * 0b1..Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
+ */
+#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
+#define PORT_PCR_PFE_MASK (0x10U)
+#define PORT_PCR_PFE_SHIFT (4U)
+/*! PFE - Passive Filter Enable
+ * 0b0..Passive input filter is disabled on the corresponding pin.
+ * 0b1..Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
+ */
+#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
+#define PORT_PCR_ODE_MASK (0x20U)
+#define PORT_PCR_ODE_SHIFT (5U)
+/*! ODE - Open Drain Enable
+ * 0b0..Open drain output is disabled on the corresponding pin.
+ * 0b1..Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
+ */
+#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
+#define PORT_PCR_DSE_MASK (0x40U)
+#define PORT_PCR_DSE_SHIFT (6U)
+/*! DSE - Drive Strength Enable
+ * 0b0..Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
+ * 0b1..High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
+ */
+#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
+#define PORT_PCR_MUX_MASK (0x700U)
+#define PORT_PCR_MUX_SHIFT (8U)
+/*! MUX - Pin Mux Control
+ * 0b000..Pin disabled (analog).
+ * 0b001..Alternative 1 (GPIO).
+ * 0b010..Alternative 2 (chip-specific).
+ * 0b011..Alternative 3 (chip-specific).
+ * 0b100..Alternative 4 (chip-specific).
+ * 0b101..Alternative 5 (chip-specific).
+ * 0b110..Alternative 6 (chip-specific).
+ * 0b111..Alternative 7 (chip-specific).
+ */
+#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
+#define PORT_PCR_LK_MASK (0x8000U)
+#define PORT_PCR_LK_SHIFT (15U)
+/*! LK - Lock Register
+ * 0b0..Pin Control Register fields [15:0] are not locked.
+ * 0b1..Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
+ */
+#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
+#define PORT_PCR_IRQC_MASK (0xF0000U)
+#define PORT_PCR_IRQC_SHIFT (16U)
+/*! IRQC - Interrupt Configuration
+ * 0b0000..Interrupt Status Flag (ISF) is disabled.
+ * 0b0001..ISF flag and DMA request on rising edge.
+ * 0b0010..ISF flag and DMA request on falling edge.
+ * 0b0011..ISF flag and DMA request on either edge.
+ * 0b0100..Reserved.
+ * 0b0101..Reserved.
+ * 0b0110..Reserved.
+ * 0b0111..Reserved.
+ * 0b1000..ISF flag and Interrupt when logic 0.
+ * 0b1001..ISF flag and Interrupt on rising-edge.
+ * 0b1010..ISF flag and Interrupt on falling-edge.
+ * 0b1011..ISF flag and Interrupt on either edge.
+ * 0b1100..ISF flag and Interrupt when logic 1.
+ * 0b1101..Reserved.
+ * 0b1110..Reserved.
+ * 0b1111..Reserved.
+ */
+#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK (0x1000000U)
+#define PORT_PCR_ISF_SHIFT (24U)
+/*! ISF - Interrupt Status Flag
+ * 0b0..Configured interrupt is not detected.
+ * 0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
+ */
+#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
+/*! @} */
+
+/* The count of PORT_PCR */
+#define PORT_PCR_COUNT (32U)
+
+/*! @name GPCLR - Global Pin Control Low Register */
+/*! @{ */
+#define PORT_GPCLR_GPWD_MASK (0xFFFFU)
+#define PORT_GPCLR_GPWD_SHIFT (0U)
+#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
+#define PORT_GPCLR_GPWE_SHIFT (16U)
+/*! GPWE - Global Pin Write Enable
+ * 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD.
+ * 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.
+ */
+#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
+/*! @} */
+
+/*! @name GPCHR - Global Pin Control High Register */
+/*! @{ */
+#define PORT_GPCHR_GPWD_MASK (0xFFFFU)
+#define PORT_GPCHR_GPWD_SHIFT (0U)
+#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
+#define PORT_GPCHR_GPWE_SHIFT (16U)
+/*! GPWE - Global Pin Write Enable
+ * 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD.
+ * 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.
+ */
+#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
+/*! @} */
+
+/*! @name ISFR - Interrupt Status Flag Register */
+/*! @{ */
+#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
+#define PORT_ISFR_ISF_SHIFT (0U)
+/*! ISF - Interrupt Status Flag
+ * 0b00000000000000000000000000000000..Configured interrupt is not detected.
+ * 0b00000000000000000000000000000001..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
+ */
+#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
+/*! @} */
+
+/*! @name DFER - Digital Filter Enable Register */
+/*! @{ */
+#define PORT_DFER_DFE_MASK (0xFFFFFFFFU)
+#define PORT_DFER_DFE_SHIFT (0U)
+/*! DFE - Digital Filter Enable
+ * 0b00000000000000000000000000000000..Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
+ * 0b00000000000000000000000000000001..Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
+ */
+#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
+/*! @} */
+
+/*! @name DFCR - Digital Filter Clock Register */
+/*! @{ */
+#define PORT_DFCR_CS_MASK (0x1U)
+#define PORT_DFCR_CS_SHIFT (0U)
+/*! CS - Clock Source
+ * 0b0..Digital filters are clocked by the bus clock.
+ * 0b1..Digital filters are clocked by the LPO clock.
+ */
+#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
+/*! @} */
+
+/*! @name DFWR - Digital Filter Width Register */
+/*! @{ */
+#define PORT_DFWR_FILT_MASK (0x1FU)
+#define PORT_DFWR_FILT_SHIFT (0U)
+#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA ((PORT_Type *)PORTA_BASE)
+/** Peripheral PORTB base address */
+#define PORTB_BASE (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB ((PORT_Type *)PORTB_BASE)
+/** Peripheral PORTC base address */
+#define PORTC_BASE (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC ((PORT_Type *)PORTC_BASE)
+/** Peripheral PORTD base address */
+#define PORTD_BASE (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD ((PORT_Type *)PORTD_BASE)
+/** Peripheral PORTE base address */
+#define PORTE_BASE (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE ((PORT_Type *)PORTE_BASE)
+/** Array initializer of PORT peripheral base addresses */
+#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
+/** Interrupt vectors for the PORT peripheral type */
+#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+ __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
+ __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
+ __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
+ uint8_t RESERVED_1[1];
+ __I uint8_t MR; /**< Mode Register, offset: 0x7 */
+ __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
+ __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
+} RCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/*! @name SRS0 - System Reset Status Register 0 */
+/*! @{ */
+#define RCM_SRS0_WAKEUP_MASK (0x1U)
+#define RCM_SRS0_WAKEUP_SHIFT (0U)
+/*! WAKEUP - Low Leakage Wakeup Reset
+ * 0b0..Reset not caused by LLWU module wakeup source
+ * 0b1..Reset caused by LLWU module wakeup source
+ */
+#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
+#define RCM_SRS0_LVD_MASK (0x2U)
+#define RCM_SRS0_LVD_SHIFT (1U)
+/*! LVD - Low-Voltage Detect Reset
+ * 0b0..Reset not caused by LVD trip or POR
+ * 0b1..Reset caused by LVD trip or POR
+ */
+#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
+#define RCM_SRS0_LOC_MASK (0x4U)
+#define RCM_SRS0_LOC_SHIFT (2U)
+/*! LOC - Loss-of-Clock Reset
+ * 0b0..Reset not caused by a loss of external clock.
+ * 0b1..Reset caused by a loss of external clock.
+ */
+#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
+#define RCM_SRS0_LOL_MASK (0x8U)
+#define RCM_SRS0_LOL_SHIFT (3U)
+/*! LOL - Loss-of-Lock Reset
+ * 0b0..Reset not caused by a loss of lock in the PLL
+ * 0b1..Reset caused by a loss of lock in the PLL
+ */
+#define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
+#define RCM_SRS0_WDOG_MASK (0x20U)
+#define RCM_SRS0_WDOG_SHIFT (5U)
+/*! WDOG - Watchdog
+ * 0b0..Reset not caused by watchdog timeout
+ * 0b1..Reset caused by watchdog timeout
+ */
+#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
+#define RCM_SRS0_PIN_MASK (0x40U)
+#define RCM_SRS0_PIN_SHIFT (6U)
+/*! PIN - External Reset Pin
+ * 0b0..Reset not caused by external reset pin
+ * 0b1..Reset caused by external reset pin
+ */
+#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
+#define RCM_SRS0_POR_MASK (0x80U)
+#define RCM_SRS0_POR_SHIFT (7U)
+/*! POR - Power-On Reset
+ * 0b0..Reset not caused by POR
+ * 0b1..Reset caused by POR
+ */
+#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
+/*! @} */
+
+/*! @name SRS1 - System Reset Status Register 1 */
+/*! @{ */
+#define RCM_SRS1_JTAG_MASK (0x1U)
+#define RCM_SRS1_JTAG_SHIFT (0U)
+/*! JTAG - JTAG Generated Reset
+ * 0b0..Reset not caused by JTAG
+ * 0b1..Reset caused by JTAG
+ */
+#define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
+#define RCM_SRS1_LOCKUP_MASK (0x2U)
+#define RCM_SRS1_LOCKUP_SHIFT (1U)
+/*! LOCKUP - Core Lockup
+ * 0b0..Reset not caused by core LOCKUP event
+ * 0b1..Reset caused by core LOCKUP event
+ */
+#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
+#define RCM_SRS1_SW_MASK (0x4U)
+#define RCM_SRS1_SW_SHIFT (2U)
+/*! SW - Software
+ * 0b0..Reset not caused by software setting of SYSRESETREQ bit
+ * 0b1..Reset caused by software setting of SYSRESETREQ bit
+ */
+#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
+#define RCM_SRS1_MDM_AP_MASK (0x8U)
+#define RCM_SRS1_MDM_AP_SHIFT (3U)
+/*! MDM_AP - MDM-AP System Reset Request
+ * 0b0..Reset not caused by host debugger system setting of the System Reset Request bit
+ * 0b1..Reset caused by host debugger system setting of the System Reset Request bit
+ */
+#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
+#define RCM_SRS1_EZPT_MASK (0x10U)
+#define RCM_SRS1_EZPT_SHIFT (4U)
+/*! EZPT - EzPort Reset
+ * 0b0..Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode
+ * 0b1..Reset caused by EzPort receiving the RESET command while the device is in EzPort mode
+ */
+#define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK)
+#define RCM_SRS1_SACKERR_MASK (0x20U)
+#define RCM_SRS1_SACKERR_SHIFT (5U)
+/*! SACKERR - Stop Mode Acknowledge Error Reset
+ * 0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
+ * 0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode
+ */
+#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
+/*! @} */
+
+/*! @name RPFC - Reset Pin Filter Control register */
+/*! @{ */
+#define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
+#define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
+/*! RSTFLTSRW - Reset Pin Filter Select in Run and Wait Modes
+ * 0b00..All filtering disabled
+ * 0b01..Bus clock filter enabled for normal operation
+ * 0b10..LPO clock filter enabled for normal operation
+ * 0b11..Reserved
+ */
+#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK (0x4U)
+#define RCM_RPFC_RSTFLTSS_SHIFT (2U)
+/*! RSTFLTSS - Reset Pin Filter Select in Stop Mode
+ * 0b0..All filtering disabled
+ * 0b1..LPO clock filter enabled
+ */
+#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
+/*! @} */
+
+/*! @name RPFW - Reset Pin Filter Width register */
+/*! @{ */
+#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
+#define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
+/*! RSTFLTSEL - Reset Pin Filter Bus Clock Select
+ * 0b00000..Bus clock filter count is 1
+ * 0b00001..Bus clock filter count is 2
+ * 0b00010..Bus clock filter count is 3
+ * 0b00011..Bus clock filter count is 4
+ * 0b00100..Bus clock filter count is 5
+ * 0b00101..Bus clock filter count is 6
+ * 0b00110..Bus clock filter count is 7
+ * 0b00111..Bus clock filter count is 8
+ * 0b01000..Bus clock filter count is 9
+ * 0b01001..Bus clock filter count is 10
+ * 0b01010..Bus clock filter count is 11
+ * 0b01011..Bus clock filter count is 12
+ * 0b01100..Bus clock filter count is 13
+ * 0b01101..Bus clock filter count is 14
+ * 0b01110..Bus clock filter count is 15
+ * 0b01111..Bus clock filter count is 16
+ * 0b10000..Bus clock filter count is 17
+ * 0b10001..Bus clock filter count is 18
+ * 0b10010..Bus clock filter count is 19
+ * 0b10011..Bus clock filter count is 20
+ * 0b10100..Bus clock filter count is 21
+ * 0b10101..Bus clock filter count is 22
+ * 0b10110..Bus clock filter count is 23
+ * 0b10111..Bus clock filter count is 24
+ * 0b11000..Bus clock filter count is 25
+ * 0b11001..Bus clock filter count is 26
+ * 0b11010..Bus clock filter count is 27
+ * 0b11011..Bus clock filter count is 28
+ * 0b11100..Bus clock filter count is 29
+ * 0b11101..Bus clock filter count is 30
+ * 0b11110..Bus clock filter count is 31
+ * 0b11111..Bus clock filter count is 32
+ */
+#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
+/*! @} */
+
+/*! @name MR - Mode Register */
+/*! @{ */
+#define RCM_MR_EZP_MS_MASK (0x2U)
+#define RCM_MR_EZP_MS_SHIFT (1U)
+/*! EZP_MS - EZP_MS_B pin state
+ * 0b0..Pin deasserted (logic 1)
+ * 0b1..Pin asserted (logic 0)
+ */
+#define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK)
+/*! @} */
+
+/*! @name SSRS0 - Sticky System Reset Status Register 0 */
+/*! @{ */
+#define RCM_SSRS0_SWAKEUP_MASK (0x1U)
+#define RCM_SSRS0_SWAKEUP_SHIFT (0U)
+/*! SWAKEUP - Sticky Low Leakage Wakeup Reset
+ * 0b0..Reset not caused by LLWU module wakeup source
+ * 0b1..Reset caused by LLWU module wakeup source
+ */
+#define RCM_SSRS0_SWAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK)
+#define RCM_SSRS0_SLVD_MASK (0x2U)
+#define RCM_SSRS0_SLVD_SHIFT (1U)
+/*! SLVD - Sticky Low-Voltage Detect Reset
+ * 0b0..Reset not caused by LVD trip or POR
+ * 0b1..Reset caused by LVD trip or POR
+ */
+#define RCM_SSRS0_SLVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK)
+#define RCM_SSRS0_SLOC_MASK (0x4U)
+#define RCM_SSRS0_SLOC_SHIFT (2U)
+/*! SLOC - Sticky Loss-of-Clock Reset
+ * 0b0..Reset not caused by a loss of external clock.
+ * 0b1..Reset caused by a loss of external clock.
+ */
+#define RCM_SSRS0_SLOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOC_SHIFT)) & RCM_SSRS0_SLOC_MASK)
+#define RCM_SSRS0_SLOL_MASK (0x8U)
+#define RCM_SSRS0_SLOL_SHIFT (3U)
+/*! SLOL - Sticky Loss-of-Lock Reset
+ * 0b0..Reset not caused by a loss of lock in the PLL
+ * 0b1..Reset caused by a loss of lock in the PLL
+ */
+#define RCM_SSRS0_SLOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOL_SHIFT)) & RCM_SSRS0_SLOL_MASK)
+#define RCM_SSRS0_SWDOG_MASK (0x20U)
+#define RCM_SSRS0_SWDOG_SHIFT (5U)
+/*! SWDOG - Sticky Watchdog
+ * 0b0..Reset not caused by watchdog timeout
+ * 0b1..Reset caused by watchdog timeout
+ */
+#define RCM_SSRS0_SWDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK)
+#define RCM_SSRS0_SPIN_MASK (0x40U)
+#define RCM_SSRS0_SPIN_SHIFT (6U)
+/*! SPIN - Sticky External Reset Pin
+ * 0b0..Reset not caused by external reset pin
+ * 0b1..Reset caused by external reset pin
+ */
+#define RCM_SSRS0_SPIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK)
+#define RCM_SSRS0_SPOR_MASK (0x80U)
+#define RCM_SSRS0_SPOR_SHIFT (7U)
+/*! SPOR - Sticky Power-On Reset
+ * 0b0..Reset not caused by POR
+ * 0b1..Reset caused by POR
+ */
+#define RCM_SSRS0_SPOR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK)
+/*! @} */
+
+/*! @name SSRS1 - Sticky System Reset Status Register 1 */
+/*! @{ */
+#define RCM_SSRS1_SJTAG_MASK (0x1U)
+#define RCM_SSRS1_SJTAG_SHIFT (0U)
+/*! SJTAG - Sticky JTAG Generated Reset
+ * 0b0..Reset not caused by JTAG
+ * 0b1..Reset caused by JTAG
+ */
+#define RCM_SSRS1_SJTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SJTAG_SHIFT)) & RCM_SSRS1_SJTAG_MASK)
+#define RCM_SSRS1_SLOCKUP_MASK (0x2U)
+#define RCM_SSRS1_SLOCKUP_SHIFT (1U)
+/*! SLOCKUP - Sticky Core Lockup
+ * 0b0..Reset not caused by core LOCKUP event
+ * 0b1..Reset caused by core LOCKUP event
+ */
+#define RCM_SSRS1_SLOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK)
+#define RCM_SSRS1_SSW_MASK (0x4U)
+#define RCM_SSRS1_SSW_SHIFT (2U)
+/*! SSW - Sticky Software
+ * 0b0..Reset not caused by software setting of SYSRESETREQ bit
+ * 0b1..Reset caused by software setting of SYSRESETREQ bit
+ */
+#define RCM_SSRS1_SSW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK)
+#define RCM_SSRS1_SMDM_AP_MASK (0x8U)
+#define RCM_SSRS1_SMDM_AP_SHIFT (3U)
+/*! SMDM_AP - Sticky MDM-AP System Reset Request
+ * 0b0..Reset not caused by host debugger system setting of the System Reset Request bit
+ * 0b1..Reset caused by host debugger system setting of the System Reset Request bit
+ */
+#define RCM_SSRS1_SMDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK)
+#define RCM_SSRS1_SEZPT_MASK (0x10U)
+#define RCM_SSRS1_SEZPT_SHIFT (4U)
+/*! SEZPT - Sticky EzPort Reset
+ * 0b0..Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode
+ * 0b1..Reset caused by EzPort receiving the RESET command while the device is in EzPort mode
+ */
+#define RCM_SSRS1_SEZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SEZPT_SHIFT)) & RCM_SSRS1_SEZPT_MASK)
+#define RCM_SSRS1_SSACKERR_MASK (0x20U)
+#define RCM_SSRS1_SSACKERR_SHIFT (5U)
+/*! SSACKERR - Sticky Stop Mode Acknowledge Error Reset
+ * 0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
+ * 0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode
+ */
+#define RCM_SSRS1_SSACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM ((RCM_Type *)RCM_BASE)
+/** Array initializer of RCM peripheral base addresses */
+#define RCM_BASE_ADDRS { RCM_BASE }
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASE_PTRS { RCM }
+
+/*!
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
+ * @{
+ */
+
+/** RFSYS - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
+} RFSYS_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
+ * @{
+ */
+
+/*! @name REG - Register file register */
+/*! @{ */
+#define RFSYS_REG_LL_MASK (0xFFU)
+#define RFSYS_REG_LL_SHIFT (0U)
+#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK (0xFF00U)
+#define RFSYS_REG_LH_SHIFT (8U)
+#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK (0xFF0000U)
+#define RFSYS_REG_HL_SHIFT (16U)
+#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK (0xFF000000U)
+#define RFSYS_REG_HH_SHIFT (24U)
+#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
+/*! @} */
+
+/* The count of RFSYS_REG */
+#define RFSYS_REG_COUNT (8U)
+
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Masks */
+
+
+/* RFSYS - Peripheral instance base addresses */
+/** Peripheral RFSYS base address */
+#define RFSYS_BASE (0x40041000u)
+/** Peripheral RFSYS base pointer */
+#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
+/** Array initializer of RFSYS peripheral base addresses */
+#define RFSYS_BASE_ADDRS { RFSYS_BASE }
+/** Array initializer of RFSYS peripheral base pointers */
+#define RFSYS_BASE_PTRS { RFSYS }
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
+ * @{
+ */
+
+/** RFVBAT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
+} RFVBAT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
+ * @{
+ */
+
+/*! @name REG - VBAT register file register */
+/*! @{ */
+#define RFVBAT_REG_LL_MASK (0xFFU)
+#define RFVBAT_REG_LL_SHIFT (0U)
+#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LH_MASK (0xFF00U)
+#define RFVBAT_REG_LH_SHIFT (8U)
+#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_HL_MASK (0xFF0000U)
+#define RFVBAT_REG_HL_SHIFT (16U)
+#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HH_MASK (0xFF000000U)
+#define RFVBAT_REG_HH_SHIFT (24U)
+#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
+/*! @} */
+
+/* The count of RFVBAT_REG */
+#define RFVBAT_REG_COUNT (8U)
+
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Masks */
+
+
+/* RFVBAT - Peripheral instance base addresses */
+/** Peripheral RFVBAT base address */
+#define RFVBAT_BASE (0x4003E000u)
+/** Peripheral RFVBAT base pointer */
+#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
+/** Array initializer of RFVBAT peripheral base addresses */
+#define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
+/** Array initializer of RFVBAT peripheral base pointers */
+#define RFVBAT_BASE_PTRS { RFVBAT }
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RNG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
+ * @{
+ */
+
+/** RNG - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
+ __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
+ __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
+ __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
+} RNG_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RNG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Masks RNG Register Masks
+ * @{
+ */
+
+/*! @name CR - RNGA Control Register */
+/*! @{ */
+#define RNG_CR_GO_MASK (0x1U)
+#define RNG_CR_GO_SHIFT (0U)
+/*! GO - Go
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define RNG_CR_GO(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK)
+#define RNG_CR_HA_MASK (0x2U)
+#define RNG_CR_HA_SHIFT (1U)
+/*! HA - High Assurance
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define RNG_CR_HA(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK)
+#define RNG_CR_INTM_MASK (0x4U)
+#define RNG_CR_INTM_SHIFT (2U)
+/*! INTM - Interrupt Mask
+ * 0b0..Not masked
+ * 0b1..Masked
+ */
+#define RNG_CR_INTM(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK)
+#define RNG_CR_CLRI_MASK (0x8U)
+#define RNG_CR_CLRI_SHIFT (3U)
+/*! CLRI - Clear Interrupt
+ * 0b0..Do not clear the interrupt.
+ * 0b1..Clear the interrupt. When you write 1 to this field, RNGA then resets the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
+ */
+#define RNG_CR_CLRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK)
+#define RNG_CR_SLP_MASK (0x10U)
+#define RNG_CR_SLP_SHIFT (4U)
+/*! SLP - Sleep
+ * 0b0..Normal mode
+ * 0b1..Sleep (low-power) mode
+ */
+#define RNG_CR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK)
+/*! @} */
+
+/*! @name SR - RNGA Status Register */
+/*! @{ */
+#define RNG_SR_SECV_MASK (0x1U)
+#define RNG_SR_SECV_SHIFT (0U)
+/*! SECV - Security Violation
+ * 0b0..No security violation
+ * 0b1..Security violation
+ */
+#define RNG_SR_SECV(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK)
+#define RNG_SR_LRS_MASK (0x2U)
+#define RNG_SR_LRS_SHIFT (1U)
+/*! LRS - Last Read Status
+ * 0b0..No underflow
+ * 0b1..Underflow
+ */
+#define RNG_SR_LRS(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK)
+#define RNG_SR_ORU_MASK (0x4U)
+#define RNG_SR_ORU_SHIFT (2U)
+/*! ORU - Output Register Underflow
+ * 0b0..No underflow
+ * 0b1..Underflow
+ */
+#define RNG_SR_ORU(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK)
+#define RNG_SR_ERRI_MASK (0x8U)
+#define RNG_SR_ERRI_SHIFT (3U)
+/*! ERRI - Error Interrupt
+ * 0b0..No underflow
+ * 0b1..Underflow
+ */
+#define RNG_SR_ERRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK)
+#define RNG_SR_SLP_MASK (0x10U)
+#define RNG_SR_SLP_SHIFT (4U)
+/*! SLP - Sleep
+ * 0b0..Normal mode
+ * 0b1..Sleep (low-power) mode
+ */
+#define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK)
+#define RNG_SR_OREG_LVL_MASK (0xFF00U)
+#define RNG_SR_OREG_LVL_SHIFT (8U)
+/*! OREG_LVL - Output Register Level
+ * 0b00000000..No words (empty)
+ * 0b00000001..One word (valid)
+ */
+#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)
+#define RNG_SR_OREG_SIZE_MASK (0xFF0000U)
+#define RNG_SR_OREG_SIZE_SHIFT (16U)
+/*! OREG_SIZE - Output Register Size
+ * 0b00000001..One word (this value is fixed)
+ */
+#define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)
+/*! @} */
+
+/*! @name ER - RNGA Entropy Register */
+/*! @{ */
+#define RNG_ER_EXT_ENT_MASK (0xFFFFFFFFU)
+#define RNG_ER_EXT_ENT_SHIFT (0U)
+#define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK)
+/*! @} */
+
+/*! @name OR - RNGA Output Register */
+/*! @{ */
+#define RNG_OR_RANDOUT_MASK (0xFFFFFFFFU)
+#define RNG_OR_RANDOUT_SHIFT (0U)
+/*! RANDOUT - Random Output
+ * 0b00000000000000000000000000000000..Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt request to the interrupt controller).
+ */
+#define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Masks */
+
+
+/* RNG - Peripheral instance base addresses */
+/** Peripheral RNG base address */
+#define RNG_BASE (0x400A0000u)
+/** Peripheral RNG base pointer */
+#define RNG ((RNG_Type *)RNG_BASE)
+/** Array initializer of RNG peripheral base addresses */
+#define RNG_BASE_ADDRS { RNG_BASE }
+/** Array initializer of RNG peripheral base pointers */
+#define RNG_BASE_PTRS { RNG }
+/** Interrupt vectors for the RNG peripheral type */
+#define RNG_IRQS { RNG_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RNG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
+ __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
+ __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
+ __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
+ __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
+ __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
+ __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
+ __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
+ __I uint32_t TTSR; /**< RTC Tamper Time Seconds Register, offset: 0x20 */
+ __IO uint32_t MER; /**< RTC Monotonic Enable Register, offset: 0x24 */
+ __IO uint32_t MCLR; /**< RTC Monotonic Counter Low Register, offset: 0x28 */
+ __IO uint32_t MCHR; /**< RTC Monotonic Counter High Register, offset: 0x2C */
+ uint8_t RESERVED_0[2000];
+ __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
+ __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/*! @name TSR - RTC Time Seconds Register */
+/*! @{ */
+#define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
+#define RTC_TSR_TSR_SHIFT (0U)
+#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
+/*! @} */
+
+/*! @name TPR - RTC Time Prescaler Register */
+/*! @{ */
+#define RTC_TPR_TPR_MASK (0xFFFFU)
+#define RTC_TPR_TPR_SHIFT (0U)
+#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
+/*! @} */
+
+/*! @name TAR - RTC Time Alarm Register */
+/*! @{ */
+#define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
+#define RTC_TAR_TAR_SHIFT (0U)
+#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
+/*! @} */
+
+/*! @name TCR - RTC Time Compensation Register */
+/*! @{ */
+#define RTC_TCR_TCR_MASK (0xFFU)
+#define RTC_TCR_TCR_SHIFT (0U)
+/*! TCR - Time Compensation Register
+ * 0b10000000..Time Prescaler Register overflows every 32896 clock cycles.
+ * 0b11111111..Time Prescaler Register overflows every 32769 clock cycles.
+ * 0b00000000..Time Prescaler Register overflows every 32768 clock cycles.
+ * 0b00000001..Time Prescaler Register overflows every 32767 clock cycles.
+ * 0b01111111..Time Prescaler Register overflows every 32641 clock cycles.
+ */
+#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK (0xFF00U)
+#define RTC_TCR_CIR_SHIFT (8U)
+#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK (0xFF0000U)
+#define RTC_TCR_TCV_SHIFT (16U)
+#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK (0xFF000000U)
+#define RTC_TCR_CIC_SHIFT (24U)
+#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
+/*! @} */
+
+/*! @name CR - RTC Control Register */
+/*! @{ */
+#define RTC_CR_SWR_MASK (0x1U)
+#define RTC_CR_SWR_SHIFT (0U)
+/*! SWR - Software Reset
+ * 0b0..No effect.
+ * 0b1..Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software explicitly clearing it.
+ */
+#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
+#define RTC_CR_WPE_MASK (0x2U)
+#define RTC_CR_WPE_SHIFT (1U)
+/*! WPE - Wakeup Pin Enable
+ * 0b0..Wakeup pin is disabled.
+ * 0b1..Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on.
+ */
+#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
+#define RTC_CR_SUP_MASK (0x4U)
+#define RTC_CR_SUP_SHIFT (2U)
+/*! SUP - Supervisor Access
+ * 0b0..Non-supervisor mode write accesses are not supported and generate a bus error.
+ * 0b1..Non-supervisor mode write accesses are supported.
+ */
+#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
+#define RTC_CR_UM_MASK (0x8U)
+#define RTC_CR_UM_SHIFT (3U)
+/*! UM - Update Mode
+ * 0b0..Registers cannot be written when locked.
+ * 0b1..Registers can be written when locked under limited conditions.
+ */
+#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
+#define RTC_CR_WPS_MASK (0x10U)
+#define RTC_CR_WPS_SHIFT (4U)
+/*! WPS - Wakeup Pin Select
+ * 0b0..Wakeup pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on.
+ * 0b1..Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals.
+ */
+#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
+#define RTC_CR_OSCE_MASK (0x100U)
+#define RTC_CR_OSCE_SHIFT (8U)
+/*! OSCE - Oscillator Enable
+ * 0b0..32.768 kHz oscillator is disabled.
+ * 0b1..32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize.
+ */
+#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
+#define RTC_CR_CLKO_MASK (0x200U)
+#define RTC_CR_CLKO_SHIFT (9U)
+/*! CLKO - Clock Output
+ * 0b0..The 32 kHz clock is output to other peripherals.
+ * 0b1..The 32 kHz clock is not output to other peripherals.
+ */
+#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
+#define RTC_CR_SC16P_MASK (0x400U)
+#define RTC_CR_SC16P_SHIFT (10U)
+/*! SC16P - Oscillator 16pF Load Configure
+ * 0b0..Disable the load.
+ * 0b1..Enable the additional load.
+ */
+#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
+#define RTC_CR_SC8P_MASK (0x800U)
+#define RTC_CR_SC8P_SHIFT (11U)
+/*! SC8P - Oscillator 8pF Load Configure
+ * 0b0..Disable the load.
+ * 0b1..Enable the additional load.
+ */
+#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
+#define RTC_CR_SC4P_MASK (0x1000U)
+#define RTC_CR_SC4P_SHIFT (12U)
+/*! SC4P - Oscillator 4pF Load Configure
+ * 0b0..Disable the load.
+ * 0b1..Enable the additional load.
+ */
+#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
+#define RTC_CR_SC2P_MASK (0x2000U)
+#define RTC_CR_SC2P_SHIFT (13U)
+/*! SC2P - Oscillator 2pF Load Configure
+ * 0b0..Disable the load.
+ * 0b1..Enable the additional load.
+ */
+#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
+/*! @} */
+
+/*! @name SR - RTC Status Register */
+/*! @{ */
+#define RTC_SR_TIF_MASK (0x1U)
+#define RTC_SR_TIF_SHIFT (0U)
+/*! TIF - Time Invalid Flag
+ * 0b0..Time is valid.
+ * 0b1..Time is invalid and time counter is read as zero.
+ */
+#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
+#define RTC_SR_TOF_MASK (0x2U)
+#define RTC_SR_TOF_SHIFT (1U)
+/*! TOF - Time Overflow Flag
+ * 0b0..Time overflow has not occurred.
+ * 0b1..Time overflow has occurred and time counter is read as zero.
+ */
+#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
+#define RTC_SR_TAF_MASK (0x4U)
+#define RTC_SR_TAF_SHIFT (2U)
+/*! TAF - Time Alarm Flag
+ * 0b0..Time alarm has not occurred.
+ * 0b1..Time alarm has occurred.
+ */
+#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
+#define RTC_SR_MOF_MASK (0x8U)
+#define RTC_SR_MOF_SHIFT (3U)
+/*! MOF - Monotonic Overflow Flag
+ * 0b0..Monotonic counter overflow has not occurred.
+ * 0b1..Monotonic counter overflow has occurred and monotonic counter is read as zero.
+ */
+#define RTC_SR_MOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_MOF_SHIFT)) & RTC_SR_MOF_MASK)
+#define RTC_SR_TCE_MASK (0x10U)
+#define RTC_SR_TCE_SHIFT (4U)
+/*! TCE - Time Counter Enable
+ * 0b0..Time counter is disabled.
+ * 0b1..Time counter is enabled.
+ */
+#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
+/*! @} */
+
+/*! @name LR - RTC Lock Register */
+/*! @{ */
+#define RTC_LR_TCL_MASK (0x8U)
+#define RTC_LR_TCL_SHIFT (3U)
+/*! TCL - Time Compensation Lock
+ * 0b0..Time Compensation Register is locked and writes are ignored.
+ * 0b1..Time Compensation Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
+#define RTC_LR_CRL_MASK (0x10U)
+#define RTC_LR_CRL_SHIFT (4U)
+/*! CRL - Control Register Lock
+ * 0b0..Control Register is locked and writes are ignored.
+ * 0b1..Control Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
+#define RTC_LR_SRL_MASK (0x20U)
+#define RTC_LR_SRL_SHIFT (5U)
+/*! SRL - Status Register Lock
+ * 0b0..Status Register is locked and writes are ignored.
+ * 0b1..Status Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
+#define RTC_LR_LRL_MASK (0x40U)
+#define RTC_LR_LRL_SHIFT (6U)
+/*! LRL - Lock Register Lock
+ * 0b0..Lock Register is locked and writes are ignored.
+ * 0b1..Lock Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
+#define RTC_LR_TTSL_MASK (0x100U)
+#define RTC_LR_TTSL_SHIFT (8U)
+/*! TTSL - Tamper Time Seconds Lock
+ * 0b0..Tamper Time Seconds Register is locked and writes are ignored.
+ * 0b1..Tamper Time Seconds Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_TTSL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TTSL_SHIFT)) & RTC_LR_TTSL_MASK)
+#define RTC_LR_MEL_MASK (0x200U)
+#define RTC_LR_MEL_SHIFT (9U)
+/*! MEL - Monotonic Enable Lock
+ * 0b0..Monotonic Enable Register is locked and writes are ignored.
+ * 0b1..Monotonic Enable Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_MEL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MEL_SHIFT)) & RTC_LR_MEL_MASK)
+#define RTC_LR_MCLL_MASK (0x400U)
+#define RTC_LR_MCLL_SHIFT (10U)
+/*! MCLL - Monotonic Counter Low Lock
+ * 0b0..Monotonic Counter Low Register is locked and writes are ignored.
+ * 0b1..Monotonic Counter Low Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_MCLL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCLL_SHIFT)) & RTC_LR_MCLL_MASK)
+#define RTC_LR_MCHL_MASK (0x800U)
+#define RTC_LR_MCHL_SHIFT (11U)
+/*! MCHL - Monotonic Counter High Lock
+ * 0b0..Monotonic Counter High Register is locked and writes are ignored.
+ * 0b1..Monotonic Counter High Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_MCHL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCHL_SHIFT)) & RTC_LR_MCHL_MASK)
+/*! @} */
+
+/*! @name IER - RTC Interrupt Enable Register */
+/*! @{ */
+#define RTC_IER_TIIE_MASK (0x1U)
+#define RTC_IER_TIIE_SHIFT (0U)
+/*! TIIE - Time Invalid Interrupt Enable
+ * 0b0..Time invalid flag does not generate an interrupt.
+ * 0b1..Time invalid flag does generate an interrupt.
+ */
+#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
+#define RTC_IER_TOIE_MASK (0x2U)
+#define RTC_IER_TOIE_SHIFT (1U)
+/*! TOIE - Time Overflow Interrupt Enable
+ * 0b0..Time overflow flag does not generate an interrupt.
+ * 0b1..Time overflow flag does generate an interrupt.
+ */
+#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
+#define RTC_IER_TAIE_MASK (0x4U)
+#define RTC_IER_TAIE_SHIFT (2U)
+/*! TAIE - Time Alarm Interrupt Enable
+ * 0b0..Time alarm flag does not generate an interrupt.
+ * 0b1..Time alarm flag does generate an interrupt.
+ */
+#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
+#define RTC_IER_MOIE_MASK (0x8U)
+#define RTC_IER_MOIE_SHIFT (3U)
+/*! MOIE - Monotonic Overflow Interrupt Enable
+ * 0b0..Monotonic overflow flag does not generate an interrupt.
+ * 0b1..Monotonic overflow flag does generate an interrupt.
+ */
+#define RTC_IER_MOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_MOIE_SHIFT)) & RTC_IER_MOIE_MASK)
+#define RTC_IER_TSIE_MASK (0x10U)
+#define RTC_IER_TSIE_SHIFT (4U)
+/*! TSIE - Time Seconds Interrupt Enable
+ * 0b0..Seconds interrupt is disabled.
+ * 0b1..Seconds interrupt is enabled.
+ */
+#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
+#define RTC_IER_WPON_MASK (0x80U)
+#define RTC_IER_WPON_SHIFT (7U)
+/*! WPON - Wakeup Pin On
+ * 0b0..No effect.
+ * 0b1..If the wakeup pin is enabled, then the wakeup pin will assert.
+ */
+#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
+/*! @} */
+
+/*! @name TTSR - RTC Tamper Time Seconds Register */
+/*! @{ */
+#define RTC_TTSR_TTS_MASK (0xFFFFFFFFU)
+#define RTC_TTSR_TTS_SHIFT (0U)
+#define RTC_TTSR_TTS(x) (((uint32_t)(((uint32_t)(x)) << RTC_TTSR_TTS_SHIFT)) & RTC_TTSR_TTS_MASK)
+/*! @} */
+
+/*! @name MER - RTC Monotonic Enable Register */
+/*! @{ */
+#define RTC_MER_MCE_MASK (0x10U)
+#define RTC_MER_MCE_SHIFT (4U)
+/*! MCE - Monotonic Counter Enable
+ * 0b0..Writes to the monotonic counter load the counter with the value written.
+ * 0b1..Writes to the monotonic counter increment the counter.
+ */
+#define RTC_MER_MCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_MER_MCE_SHIFT)) & RTC_MER_MCE_MASK)
+/*! @} */
+
+/*! @name MCLR - RTC Monotonic Counter Low Register */
+/*! @{ */
+#define RTC_MCLR_MCL_MASK (0xFFFFFFFFU)
+#define RTC_MCLR_MCL_SHIFT (0U)
+#define RTC_MCLR_MCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MCLR_MCL_SHIFT)) & RTC_MCLR_MCL_MASK)
+/*! @} */
+
+/*! @name MCHR - RTC Monotonic Counter High Register */
+/*! @{ */
+#define RTC_MCHR_MCH_MASK (0xFFFFFFFFU)
+#define RTC_MCHR_MCH_SHIFT (0U)
+#define RTC_MCHR_MCH(x) (((uint32_t)(((uint32_t)(x)) << RTC_MCHR_MCH_SHIFT)) & RTC_MCHR_MCH_MASK)
+/*! @} */
+
+/*! @name WAR - RTC Write Access Register */
+/*! @{ */
+#define RTC_WAR_TSRW_MASK (0x1U)
+#define RTC_WAR_TSRW_SHIFT (0U)
+/*! TSRW - Time Seconds Register Write
+ * 0b0..Writes to the Time Seconds Register are ignored.
+ * 0b1..Writes to the Time Seconds Register complete as normal.
+ */
+#define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
+#define RTC_WAR_TPRW_MASK (0x2U)
+#define RTC_WAR_TPRW_SHIFT (1U)
+/*! TPRW - Time Prescaler Register Write
+ * 0b0..Writes to the Time Prescaler Register are ignored.
+ * 0b1..Writes to the Time Prescaler Register complete as normal.
+ */
+#define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
+#define RTC_WAR_TARW_MASK (0x4U)
+#define RTC_WAR_TARW_SHIFT (2U)
+/*! TARW - Time Alarm Register Write
+ * 0b0..Writes to the Time Alarm Register are ignored.
+ * 0b1..Writes to the Time Alarm Register complete as normal.
+ */
+#define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
+#define RTC_WAR_TCRW_MASK (0x8U)
+#define RTC_WAR_TCRW_SHIFT (3U)
+/*! TCRW - Time Compensation Register Write
+ * 0b0..Writes to the Time Compensation Register are ignored.
+ * 0b1..Writes to the Time Compensation Register complete as normal.
+ */
+#define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
+#define RTC_WAR_CRW_MASK (0x10U)
+#define RTC_WAR_CRW_SHIFT (4U)
+/*! CRW - Control Register Write
+ * 0b0..Writes to the Control Register are ignored.
+ * 0b1..Writes to the Control Register complete as normal.
+ */
+#define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
+#define RTC_WAR_SRW_MASK (0x20U)
+#define RTC_WAR_SRW_SHIFT (5U)
+/*! SRW - Status Register Write
+ * 0b0..Writes to the Status Register are ignored.
+ * 0b1..Writes to the Status Register complete as normal.
+ */
+#define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
+#define RTC_WAR_LRW_MASK (0x40U)
+#define RTC_WAR_LRW_SHIFT (6U)
+/*! LRW - Lock Register Write
+ * 0b0..Writes to the Lock Register are ignored.
+ * 0b1..Writes to the Lock Register complete as normal.
+ */
+#define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
+#define RTC_WAR_IERW_MASK (0x80U)
+#define RTC_WAR_IERW_SHIFT (7U)
+/*! IERW - Interrupt Enable Register Write
+ * 0b0..Writes to the Interupt Enable Register are ignored.
+ * 0b1..Writes to the Interrupt Enable Register complete as normal.
+ */
+#define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
+#define RTC_WAR_TTSW_MASK (0x100U)
+#define RTC_WAR_TTSW_SHIFT (8U)
+/*! TTSW - Tamper Time Seconds Write
+ * 0b0..Writes to the Tamper Time Seconds Register are ignored.
+ * 0b1..Writes to the Tamper Time Seconds Register complete as normal.
+ */
+#define RTC_WAR_TTSW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TTSW_SHIFT)) & RTC_WAR_TTSW_MASK)
+#define RTC_WAR_MERW_MASK (0x200U)
+#define RTC_WAR_MERW_SHIFT (9U)
+/*! MERW - Monotonic Enable Register Write
+ * 0b0..Writes to the Monotonic Enable Register are ignored.
+ * 0b1..Writes to the Monotonic Enable Register complete as normal.
+ */
+#define RTC_WAR_MERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MERW_SHIFT)) & RTC_WAR_MERW_MASK)
+#define RTC_WAR_MCLW_MASK (0x400U)
+#define RTC_WAR_MCLW_SHIFT (10U)
+/*! MCLW - Monotonic Counter Low Write
+ * 0b0..Writes to the Monotonic Counter Low Register are ignored.
+ * 0b1..Writes to the Monotonic Counter Low Register complete as normal.
+ */
+#define RTC_WAR_MCLW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCLW_SHIFT)) & RTC_WAR_MCLW_MASK)
+#define RTC_WAR_MCHW_MASK (0x800U)
+#define RTC_WAR_MCHW_SHIFT (11U)
+/*! MCHW - Monotonic Counter High Write
+ * 0b0..Writes to the Monotonic Counter High Register are ignored.
+ * 0b1..Writes to the Monotonic Counter High Register complete as normal.
+ */
+#define RTC_WAR_MCHW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCHW_SHIFT)) & RTC_WAR_MCHW_MASK)
+/*! @} */
+
+/*! @name RAR - RTC Read Access Register */
+/*! @{ */
+#define RTC_RAR_TSRR_MASK (0x1U)
+#define RTC_RAR_TSRR_SHIFT (0U)
+/*! TSRR - Time Seconds Register Read
+ * 0b0..Reads to the Time Seconds Register are ignored.
+ * 0b1..Reads to the Time Seconds Register complete as normal.
+ */
+#define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
+#define RTC_RAR_TPRR_MASK (0x2U)
+#define RTC_RAR_TPRR_SHIFT (1U)
+/*! TPRR - Time Prescaler Register Read
+ * 0b0..Reads to the Time Pprescaler Register are ignored.
+ * 0b1..Reads to the Time Prescaler Register complete as normal.
+ */
+#define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
+#define RTC_RAR_TARR_MASK (0x4U)
+#define RTC_RAR_TARR_SHIFT (2U)
+/*! TARR - Time Alarm Register Read
+ * 0b0..Reads to the Time Alarm Register are ignored.
+ * 0b1..Reads to the Time Alarm Register complete as normal.
+ */
+#define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
+#define RTC_RAR_TCRR_MASK (0x8U)
+#define RTC_RAR_TCRR_SHIFT (3U)
+/*! TCRR - Time Compensation Register Read
+ * 0b0..Reads to the Time Compensation Register are ignored.
+ * 0b1..Reads to the Time Compensation Register complete as normal.
+ */
+#define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
+#define RTC_RAR_CRR_MASK (0x10U)
+#define RTC_RAR_CRR_SHIFT (4U)
+/*! CRR - Control Register Read
+ * 0b0..Reads to the Control Register are ignored.
+ * 0b1..Reads to the Control Register complete as normal.
+ */
+#define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
+#define RTC_RAR_SRR_MASK (0x20U)
+#define RTC_RAR_SRR_SHIFT (5U)
+/*! SRR - Status Register Read
+ * 0b0..Reads to the Status Register are ignored.
+ * 0b1..Reads to the Status Register complete as normal.
+ */
+#define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
+#define RTC_RAR_LRR_MASK (0x40U)
+#define RTC_RAR_LRR_SHIFT (6U)
+/*! LRR - Lock Register Read
+ * 0b0..Reads to the Lock Register are ignored.
+ * 0b1..Reads to the Lock Register complete as normal.
+ */
+#define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
+#define RTC_RAR_IERR_MASK (0x80U)
+#define RTC_RAR_IERR_SHIFT (7U)
+/*! IERR - Interrupt Enable Register Read
+ * 0b0..Reads to the Interrupt Enable Register are ignored.
+ * 0b1..Reads to the Interrupt Enable Register complete as normal.
+ */
+#define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
+#define RTC_RAR_TTSR_MASK (0x100U)
+#define RTC_RAR_TTSR_SHIFT (8U)
+/*! TTSR - Tamper Time Seconds Read
+ * 0b0..Reads to the Tamper Time Seconds Register are ignored.
+ * 0b1..Reads to the Tamper Time Seconds Register complete as normal.
+ */
+#define RTC_RAR_TTSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TTSR_SHIFT)) & RTC_RAR_TTSR_MASK)
+#define RTC_RAR_MERR_MASK (0x200U)
+#define RTC_RAR_MERR_SHIFT (9U)
+/*! MERR - Monotonic Enable Register Read
+ * 0b0..Reads to the Monotonic Enable Register are ignored.
+ * 0b1..Reads to the Monotonic Enable Register complete as normal.
+ */
+#define RTC_RAR_MERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MERR_SHIFT)) & RTC_RAR_MERR_MASK)
+#define RTC_RAR_MCLR_MASK (0x400U)
+#define RTC_RAR_MCLR_SHIFT (10U)
+/*! MCLR - Monotonic Counter Low Read
+ * 0b0..Reads to the Monotonic Counter Low Register are ignored.
+ * 0b1..Reads to the Monotonic Counter Low Register complete as normal.
+ */
+#define RTC_RAR_MCLR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCLR_SHIFT)) & RTC_RAR_MCLR_MASK)
+#define RTC_RAR_MCHR_MASK (0x800U)
+#define RTC_RAR_MCHR_SHIFT (11U)
+/*! MCHR - Monotonic Counter High Read
+ * 0b0..Reads to the Monotonic Counter High Register are ignored.
+ * 0b1..Reads to the Monotonic Counter High Register complete as normal.
+ */
+#define RTC_RAR_MCHR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCHR_SHIFT)) & RTC_RAR_MCHR_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS { RTC_IRQn }
+#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SDHC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
+ * @{
+ */
+
+/** SDHC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */
+ __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */
+ __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */
+ __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */
+ __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */
+ __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */
+ __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */
+ __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */
+ __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */
+ __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */
+ __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */
+ __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */
+ __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */
+ __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */
+ uint8_t RESERVED_0[8];
+ __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */
+ __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */
+ __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */
+ uint8_t RESERVED_1[100];
+ __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */
+ __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */
+ uint8_t RESERVED_2[52];
+ __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */
+} SDHC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SDHC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Masks SDHC Register Masks
+ * @{
+ */
+
+/*! @name DSADDR - DMA System Address register */
+/*! @{ */
+#define SDHC_DSADDR_DSADDR_MASK (0xFFFFFFFCU)
+#define SDHC_DSADDR_DSADDR_SHIFT (2U)
+#define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK)
+/*! @} */
+
+/*! @name BLKATTR - Block Attributes register */
+/*! @{ */
+#define SDHC_BLKATTR_BLKSIZE_MASK (0x1FFFU)
+#define SDHC_BLKATTR_BLKSIZE_SHIFT (0U)
+/*! BLKSIZE - Transfer Block Size
+ * 0b0000000000000..No data transfer.
+ * 0b0000000000001..1 Byte
+ * 0b0000000000010..2 Bytes
+ * 0b0000000000011..3 Bytes
+ * 0b0000000000100..4 Bytes
+ * 0b0000111111111..511 Bytes
+ * 0b0001000000000..512 Bytes
+ * 0b0100000000000..2048 Bytes
+ * 0b1000000000000..4096 Bytes
+ */
+#define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)
+#define SDHC_BLKATTR_BLKCNT_MASK (0xFFFF0000U)
+#define SDHC_BLKATTR_BLKCNT_SHIFT (16U)
+/*! BLKCNT - Blocks Count For Current Transfer
+ * 0b0000000000000000..Stop count.
+ * 0b0000000000000001..1 block
+ * 0b0000000000000010..2 blocks
+ * 0b1111111111111111..65535 blocks
+ */
+#define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)
+/*! @} */
+
+/*! @name CMDARG - Command Argument register */
+/*! @{ */
+#define SDHC_CMDARG_CMDARG_MASK (0xFFFFFFFFU)
+#define SDHC_CMDARG_CMDARG_SHIFT (0U)
+#define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK)
+/*! @} */
+
+/*! @name XFERTYP - Transfer Type register */
+/*! @{ */
+#define SDHC_XFERTYP_DMAEN_MASK (0x1U)
+#define SDHC_XFERTYP_DMAEN_SHIFT (0U)
+/*! DMAEN - DMA Enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SDHC_XFERTYP_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK)
+#define SDHC_XFERTYP_BCEN_MASK (0x2U)
+#define SDHC_XFERTYP_BCEN_SHIFT (1U)
+/*! BCEN - Block Count Enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SDHC_XFERTYP_BCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK)
+#define SDHC_XFERTYP_AC12EN_MASK (0x4U)
+#define SDHC_XFERTYP_AC12EN_SHIFT (2U)
+/*! AC12EN - Auto CMD12 Enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SDHC_XFERTYP_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK)
+#define SDHC_XFERTYP_DTDSEL_MASK (0x10U)
+#define SDHC_XFERTYP_DTDSEL_SHIFT (4U)
+/*! DTDSEL - Data Transfer Direction Select
+ * 0b0..Write host to card.
+ * 0b1..Read card to host.
+ */
+#define SDHC_XFERTYP_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK)
+#define SDHC_XFERTYP_MSBSEL_MASK (0x20U)
+#define SDHC_XFERTYP_MSBSEL_SHIFT (5U)
+/*! MSBSEL - Multi/Single Block Select
+ * 0b0..Single block.
+ * 0b1..Multiple blocks.
+ */
+#define SDHC_XFERTYP_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK)
+#define SDHC_XFERTYP_RSPTYP_MASK (0x30000U)
+#define SDHC_XFERTYP_RSPTYP_SHIFT (16U)
+/*! RSPTYP - Response Type Select
+ * 0b00..No response.
+ * 0b01..Response length 136.
+ * 0b10..Response length 48.
+ * 0b11..Response length 48, check busy after response.
+ */
+#define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)
+#define SDHC_XFERTYP_CCCEN_MASK (0x80000U)
+#define SDHC_XFERTYP_CCCEN_SHIFT (19U)
+/*! CCCEN - Command CRC Check Enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SDHC_XFERTYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK)
+#define SDHC_XFERTYP_CICEN_MASK (0x100000U)
+#define SDHC_XFERTYP_CICEN_SHIFT (20U)
+/*! CICEN - Command Index Check Enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SDHC_XFERTYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK)
+#define SDHC_XFERTYP_DPSEL_MASK (0x200000U)
+#define SDHC_XFERTYP_DPSEL_SHIFT (21U)
+/*! DPSEL - Data Present Select
+ * 0b0..No data present.
+ * 0b1..Data present.
+ */
+#define SDHC_XFERTYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK)
+#define SDHC_XFERTYP_CMDTYP_MASK (0xC00000U)
+#define SDHC_XFERTYP_CMDTYP_SHIFT (22U)
+/*! CMDTYP - Command Type
+ * 0b00..Normal other commands.
+ * 0b01..Suspend CMD52 for writing bus suspend in CCCR.
+ * 0b10..Resume CMD52 for writing function select in CCCR.
+ * 0b11..Abort CMD12, CMD52 for writing I/O abort in CCCR.
+ */
+#define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)
+#define SDHC_XFERTYP_CMDINX_MASK (0x3F000000U)
+#define SDHC_XFERTYP_CMDINX_SHIFT (24U)
+#define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK)
+/*! @} */
+
+/*! @name CMDRSP - Command Response 0..Command Response 3 */
+/*! @{ */
+#define SDHC_CMDRSP_CMDRSP0_MASK (0xFFFFFFFFU)
+#define SDHC_CMDRSP_CMDRSP0_SHIFT (0U)
+#define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK)
+#define SDHC_CMDRSP_CMDRSP1_MASK (0xFFFFFFFFU)
+#define SDHC_CMDRSP_CMDRSP1_SHIFT (0U)
+#define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP1_SHIFT)) & SDHC_CMDRSP_CMDRSP1_MASK)
+#define SDHC_CMDRSP_CMDRSP2_MASK (0xFFFFFFFFU)
+#define SDHC_CMDRSP_CMDRSP2_SHIFT (0U)
+#define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP2_SHIFT)) & SDHC_CMDRSP_CMDRSP2_MASK)
+#define SDHC_CMDRSP_CMDRSP3_MASK (0xFFFFFFFFU)
+#define SDHC_CMDRSP_CMDRSP3_SHIFT (0U)
+#define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK)
+/*! @} */
+
+/* The count of SDHC_CMDRSP */
+#define SDHC_CMDRSP_COUNT (4U)
+
+/*! @name DATPORT - Buffer Data Port register */
+/*! @{ */
+#define SDHC_DATPORT_DATCONT_MASK (0xFFFFFFFFU)
+#define SDHC_DATPORT_DATCONT_SHIFT (0U)
+#define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK)
+/*! @} */
+
+/*! @name PRSSTAT - Present State register */
+/*! @{ */
+#define SDHC_PRSSTAT_CIHB_MASK (0x1U)
+#define SDHC_PRSSTAT_CIHB_SHIFT (0U)
+/*! CIHB - Command Inhibit (CMD)
+ * 0b0..Can issue command using only CMD line.
+ * 0b1..Cannot issue command.
+ */
+#define SDHC_PRSSTAT_CIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK)
+#define SDHC_PRSSTAT_CDIHB_MASK (0x2U)
+#define SDHC_PRSSTAT_CDIHB_SHIFT (1U)
+/*! CDIHB - Command Inhibit (DAT)
+ * 0b0..Can issue command which uses the DAT line.
+ * 0b1..Cannot issue command which uses the DAT line.
+ */
+#define SDHC_PRSSTAT_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK)
+#define SDHC_PRSSTAT_DLA_MASK (0x4U)
+#define SDHC_PRSSTAT_DLA_SHIFT (2U)
+/*! DLA - Data Line Active
+ * 0b0..DAT line inactive.
+ * 0b1..DAT line active.
+ */
+#define SDHC_PRSSTAT_DLA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK)
+#define SDHC_PRSSTAT_SDSTB_MASK (0x8U)
+#define SDHC_PRSSTAT_SDSTB_SHIFT (3U)
+/*! SDSTB - SD Clock Stable
+ * 0b0..Clock is changing frequency and not stable.
+ * 0b1..Clock is stable.
+ */
+#define SDHC_PRSSTAT_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK)
+#define SDHC_PRSSTAT_IPGOFF_MASK (0x10U)
+#define SDHC_PRSSTAT_IPGOFF_SHIFT (4U)
+/*! IPGOFF - Bus Clock Gated Off Internally
+ * 0b0..Bus clock is active.
+ * 0b1..Bus clock is gated off.
+ */
+#define SDHC_PRSSTAT_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK)
+#define SDHC_PRSSTAT_HCKOFF_MASK (0x20U)
+#define SDHC_PRSSTAT_HCKOFF_SHIFT (5U)
+/*! HCKOFF - System Clock Gated Off Internally
+ * 0b0..System clock is active.
+ * 0b1..System clock is gated off.
+ */
+#define SDHC_PRSSTAT_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK)
+#define SDHC_PRSSTAT_PEROFF_MASK (0x40U)
+#define SDHC_PRSSTAT_PEROFF_SHIFT (6U)
+/*! PEROFF - SDHC clock Gated Off Internally
+ * 0b0..SDHC clock is active.
+ * 0b1..SDHC clock is gated off.
+ */
+#define SDHC_PRSSTAT_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK)
+#define SDHC_PRSSTAT_SDOFF_MASK (0x80U)
+#define SDHC_PRSSTAT_SDOFF_SHIFT (7U)
+/*! SDOFF - SD Clock Gated Off Internally
+ * 0b0..SD clock is active.
+ * 0b1..SD clock is gated off.
+ */
+#define SDHC_PRSSTAT_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK)
+#define SDHC_PRSSTAT_WTA_MASK (0x100U)
+#define SDHC_PRSSTAT_WTA_SHIFT (8U)
+/*! WTA - Write Transfer Active
+ * 0b0..No valid data.
+ * 0b1..Transferring data.
+ */
+#define SDHC_PRSSTAT_WTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK)
+#define SDHC_PRSSTAT_RTA_MASK (0x200U)
+#define SDHC_PRSSTAT_RTA_SHIFT (9U)
+/*! RTA - Read Transfer Active
+ * 0b0..No valid data.
+ * 0b1..Transferring data.
+ */
+#define SDHC_PRSSTAT_RTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK)
+#define SDHC_PRSSTAT_BWEN_MASK (0x400U)
+#define SDHC_PRSSTAT_BWEN_SHIFT (10U)
+/*! BWEN - Buffer Write Enable
+ * 0b0..Write disable, the buffer can hold valid data less than the write watermark level.
+ * 0b1..Write enable, the buffer can hold valid data greater than the write watermark level.
+ */
+#define SDHC_PRSSTAT_BWEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK)
+#define SDHC_PRSSTAT_BREN_MASK (0x800U)
+#define SDHC_PRSSTAT_BREN_SHIFT (11U)
+/*! BREN - Buffer Read Enable
+ * 0b0..Read disable, valid data less than the watermark level exist in the buffer.
+ * 0b1..Read enable, valid data greater than the watermark level exist in the buffer.
+ */
+#define SDHC_PRSSTAT_BREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK)
+#define SDHC_PRSSTAT_CINS_MASK (0x10000U)
+#define SDHC_PRSSTAT_CINS_SHIFT (16U)
+/*! CINS - Card Inserted
+ * 0b0..Power on reset or no card.
+ * 0b1..Card inserted.
+ */
+#define SDHC_PRSSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK)
+#define SDHC_PRSSTAT_CLSL_MASK (0x800000U)
+#define SDHC_PRSSTAT_CLSL_SHIFT (23U)
+#define SDHC_PRSSTAT_CLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CLSL_SHIFT)) & SDHC_PRSSTAT_CLSL_MASK)
+#define SDHC_PRSSTAT_DLSL_MASK (0xFF000000U)
+#define SDHC_PRSSTAT_DLSL_SHIFT (24U)
+#define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK)
+/*! @} */
+
+/*! @name PROCTL - Protocol Control register */
+/*! @{ */
+#define SDHC_PROCTL_LCTL_MASK (0x1U)
+#define SDHC_PROCTL_LCTL_SHIFT (0U)
+/*! LCTL - LED Control
+ * 0b0..LED off.
+ * 0b1..LED on.
+ */
+#define SDHC_PROCTL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK)
+#define SDHC_PROCTL_DTW_MASK (0x6U)
+#define SDHC_PROCTL_DTW_SHIFT (1U)
+/*! DTW - Data Transfer Width
+ * 0b00..1-bit mode
+ * 0b01..4-bit mode
+ * 0b10..8-bit mode
+ * 0b11..Reserved
+ */
+#define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)
+#define SDHC_PROCTL_D3CD_MASK (0x8U)
+#define SDHC_PROCTL_D3CD_SHIFT (3U)
+/*! D3CD - DAT3 As Card Detection Pin
+ * 0b0..DAT3 does not monitor card Insertion.
+ * 0b1..DAT3 as card detection pin.
+ */
+#define SDHC_PROCTL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK)
+#define SDHC_PROCTL_EMODE_MASK (0x30U)
+#define SDHC_PROCTL_EMODE_SHIFT (4U)
+/*! EMODE - Endian Mode
+ * 0b00..Big endian mode
+ * 0b01..Half word big endian mode
+ * 0b10..Little endian mode
+ * 0b11..Reserved
+ */
+#define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)
+#define SDHC_PROCTL_CDTL_MASK (0x40U)
+#define SDHC_PROCTL_CDTL_SHIFT (6U)
+/*! CDTL - Card Detect Test Level
+ * 0b0..Card detect test level is 0, no card inserted.
+ * 0b1..Card detect test level is 1, card inserted.
+ */
+#define SDHC_PROCTL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK)
+#define SDHC_PROCTL_CDSS_MASK (0x80U)
+#define SDHC_PROCTL_CDSS_SHIFT (7U)
+/*! CDSS - Card Detect Signal Selection
+ * 0b0..Card detection level is selected for normal purpose.
+ * 0b1..Card detection test level is selected for test purpose.
+ */
+#define SDHC_PROCTL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK)
+#define SDHC_PROCTL_DMAS_MASK (0x300U)
+#define SDHC_PROCTL_DMAS_SHIFT (8U)
+/*! DMAS - DMA Select
+ * 0b00..No DMA or simple DMA is selected.
+ * 0b01..ADMA1 is selected.
+ * 0b10..ADMA2 is selected.
+ * 0b11..Reserved
+ */
+#define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)
+#define SDHC_PROCTL_SABGREQ_MASK (0x10000U)
+#define SDHC_PROCTL_SABGREQ_SHIFT (16U)
+/*! SABGREQ - Stop At Block Gap Request
+ * 0b0..Transfer
+ * 0b1..Stop
+ */
+#define SDHC_PROCTL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK)
+#define SDHC_PROCTL_CREQ_MASK (0x20000U)
+#define SDHC_PROCTL_CREQ_SHIFT (17U)
+/*! CREQ - Continue Request
+ * 0b0..No effect.
+ * 0b1..Restart
+ */
+#define SDHC_PROCTL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK)
+#define SDHC_PROCTL_RWCTL_MASK (0x40000U)
+#define SDHC_PROCTL_RWCTL_SHIFT (18U)
+/*! RWCTL - Read Wait Control
+ * 0b0..Disable read wait control, and stop SD clock at block gap when SABGREQ is set.
+ * 0b1..Enable read wait control, and assert read wait without stopping SD clock at block gap when SABGREQ bit is set.
+ */
+#define SDHC_PROCTL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK)
+#define SDHC_PROCTL_IABG_MASK (0x80000U)
+#define SDHC_PROCTL_IABG_SHIFT (19U)
+/*! IABG - Interrupt At Block Gap
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SDHC_PROCTL_IABG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK)
+#define SDHC_PROCTL_WECINT_MASK (0x1000000U)
+#define SDHC_PROCTL_WECINT_SHIFT (24U)
+/*! WECINT - Wakeup Event Enable On Card Interrupt
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SDHC_PROCTL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK)
+#define SDHC_PROCTL_WECINS_MASK (0x2000000U)
+#define SDHC_PROCTL_WECINS_SHIFT (25U)
+/*! WECINS - Wakeup Event Enable On SD Card Insertion
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SDHC_PROCTL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK)
+#define SDHC_PROCTL_WECRM_MASK (0x4000000U)
+#define SDHC_PROCTL_WECRM_SHIFT (26U)
+/*! WECRM - Wakeup Event Enable On SD Card Removal
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SDHC_PROCTL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK)
+/*! @} */
+
+/*! @name SYSCTL - System Control register */
+/*! @{ */
+#define SDHC_SYSCTL_IPGEN_MASK (0x1U)
+#define SDHC_SYSCTL_IPGEN_SHIFT (0U)
+/*! IPGEN - IPG Clock Enable
+ * 0b0..Bus clock will be internally gated off.
+ * 0b1..Bus clock will not be automatically gated off.
+ */
+#define SDHC_SYSCTL_IPGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK)
+#define SDHC_SYSCTL_HCKEN_MASK (0x2U)
+#define SDHC_SYSCTL_HCKEN_SHIFT (1U)
+/*! HCKEN - System Clock Enable
+ * 0b0..System clock will be internally gated off.
+ * 0b1..System clock will not be automatically gated off.
+ */
+#define SDHC_SYSCTL_HCKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK)
+#define SDHC_SYSCTL_PEREN_MASK (0x4U)
+#define SDHC_SYSCTL_PEREN_SHIFT (2U)
+/*! PEREN - Peripheral Clock Enable
+ * 0b0..SDHC clock will be internally gated off.
+ * 0b1..SDHC clock will not be automatically gated off.
+ */
+#define SDHC_SYSCTL_PEREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK)
+#define SDHC_SYSCTL_SDCLKEN_MASK (0x8U)
+#define SDHC_SYSCTL_SDCLKEN_SHIFT (3U)
+#define SDHC_SYSCTL_SDCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK)
+#define SDHC_SYSCTL_DVS_MASK (0xF0U)
+#define SDHC_SYSCTL_DVS_SHIFT (4U)
+/*! DVS - Divisor
+ * 0b0000..Divisor by 1.
+ * 0b0001..Divisor by 2.
+ * 0b1110..Divisor by 15.
+ * 0b1111..Divisor by 16.
+ */
+#define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)
+#define SDHC_SYSCTL_SDCLKFS_MASK (0xFF00U)
+#define SDHC_SYSCTL_SDCLKFS_SHIFT (8U)
+/*! SDCLKFS - SDCLK Frequency Select
+ * 0b00000001..Base clock divided by 2.
+ * 0b00000010..Base clock divided by 4.
+ * 0b00000100..Base clock divided by 8.
+ * 0b00001000..Base clock divided by 16.
+ * 0b00010000..Base clock divided by 32.
+ * 0b00100000..Base clock divided by 64.
+ * 0b01000000..Base clock divided by 128.
+ * 0b10000000..Base clock divided by 256.
+ */
+#define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)
+#define SDHC_SYSCTL_DTOCV_MASK (0xF0000U)
+#define SDHC_SYSCTL_DTOCV_SHIFT (16U)
+/*! DTOCV - Data Timeout Counter Value
+ * 0b0000..SDCLK x 2 13
+ * 0b0001..SDCLK x 2 14
+ * 0b1110..SDCLK x 2 27
+ * 0b1111..Reserved
+ */
+#define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)
+#define SDHC_SYSCTL_RSTA_MASK (0x1000000U)
+#define SDHC_SYSCTL_RSTA_SHIFT (24U)
+/*! RSTA - Software Reset For ALL
+ * 0b0..No reset.
+ * 0b1..Reset.
+ */
+#define SDHC_SYSCTL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK)
+#define SDHC_SYSCTL_RSTC_MASK (0x2000000U)
+#define SDHC_SYSCTL_RSTC_SHIFT (25U)
+/*! RSTC - Software Reset For CMD Line
+ * 0b0..No reset.
+ * 0b1..Reset.
+ */
+#define SDHC_SYSCTL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK)
+#define SDHC_SYSCTL_RSTD_MASK (0x4000000U)
+#define SDHC_SYSCTL_RSTD_SHIFT (26U)
+/*! RSTD - Software Reset For DAT Line
+ * 0b0..No reset.
+ * 0b1..Reset.
+ */
+#define SDHC_SYSCTL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK)
+#define SDHC_SYSCTL_INITA_MASK (0x8000000U)
+#define SDHC_SYSCTL_INITA_SHIFT (27U)
+#define SDHC_SYSCTL_INITA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK)
+/*! @} */
+
+/*! @name IRQSTAT - Interrupt Status register */
+/*! @{ */
+#define SDHC_IRQSTAT_CC_MASK (0x1U)
+#define SDHC_IRQSTAT_CC_SHIFT (0U)
+/*! CC - Command Complete
+ * 0b0..Command not complete.
+ * 0b1..Command complete.
+ */
+#define SDHC_IRQSTAT_CC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK)
+#define SDHC_IRQSTAT_TC_MASK (0x2U)
+#define SDHC_IRQSTAT_TC_SHIFT (1U)
+/*! TC - Transfer Complete
+ * 0b0..Transfer not complete.
+ * 0b1..Transfer complete.
+ */
+#define SDHC_IRQSTAT_TC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK)
+#define SDHC_IRQSTAT_BGE_MASK (0x4U)
+#define SDHC_IRQSTAT_BGE_SHIFT (2U)
+/*! BGE - Block Gap Event
+ * 0b0..No block gap event.
+ * 0b1..Transaction stopped at block gap.
+ */
+#define SDHC_IRQSTAT_BGE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK)
+#define SDHC_IRQSTAT_DINT_MASK (0x8U)
+#define SDHC_IRQSTAT_DINT_SHIFT (3U)
+/*! DINT - DMA Interrupt
+ * 0b0..No DMA Interrupt.
+ * 0b1..DMA Interrupt is generated.
+ */
+#define SDHC_IRQSTAT_DINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK)
+#define SDHC_IRQSTAT_BWR_MASK (0x10U)
+#define SDHC_IRQSTAT_BWR_SHIFT (4U)
+/*! BWR - Buffer Write Ready
+ * 0b0..Not ready to write buffer.
+ * 0b1..Ready to write buffer.
+ */
+#define SDHC_IRQSTAT_BWR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK)
+#define SDHC_IRQSTAT_BRR_MASK (0x20U)
+#define SDHC_IRQSTAT_BRR_SHIFT (5U)
+/*! BRR - Buffer Read Ready
+ * 0b0..Not ready to read buffer.
+ * 0b1..Ready to read buffer.
+ */
+#define SDHC_IRQSTAT_BRR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK)
+#define SDHC_IRQSTAT_CINS_MASK (0x40U)
+#define SDHC_IRQSTAT_CINS_SHIFT (6U)
+/*! CINS - Card Insertion
+ * 0b0..Card state unstable or removed.
+ * 0b1..Card inserted.
+ */
+#define SDHC_IRQSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK)
+#define SDHC_IRQSTAT_CRM_MASK (0x80U)
+#define SDHC_IRQSTAT_CRM_SHIFT (7U)
+/*! CRM - Card Removal
+ * 0b0..Card state unstable or inserted.
+ * 0b1..Card removed.
+ */
+#define SDHC_IRQSTAT_CRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK)
+#define SDHC_IRQSTAT_CINT_MASK (0x100U)
+#define SDHC_IRQSTAT_CINT_SHIFT (8U)
+/*! CINT - Card Interrupt
+ * 0b0..No Card Interrupt.
+ * 0b1..Generate Card Interrupt.
+ */
+#define SDHC_IRQSTAT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK)
+#define SDHC_IRQSTAT_CTOE_MASK (0x10000U)
+#define SDHC_IRQSTAT_CTOE_SHIFT (16U)
+/*! CTOE - Command Timeout Error
+ * 0b0..No error.
+ * 0b1..Time out.
+ */
+#define SDHC_IRQSTAT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK)
+#define SDHC_IRQSTAT_CCE_MASK (0x20000U)
+#define SDHC_IRQSTAT_CCE_SHIFT (17U)
+/*! CCE - Command CRC Error
+ * 0b0..No error.
+ * 0b1..CRC Error generated.
+ */
+#define SDHC_IRQSTAT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK)
+#define SDHC_IRQSTAT_CEBE_MASK (0x40000U)
+#define SDHC_IRQSTAT_CEBE_SHIFT (18U)
+/*! CEBE - Command End Bit Error
+ * 0b0..No error.
+ * 0b1..End Bit Error generated.
+ */
+#define SDHC_IRQSTAT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK)
+#define SDHC_IRQSTAT_CIE_MASK (0x80000U)
+#define SDHC_IRQSTAT_CIE_SHIFT (19U)
+/*! CIE - Command Index Error
+ * 0b0..No error.
+ * 0b1..Error.
+ */
+#define SDHC_IRQSTAT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK)
+#define SDHC_IRQSTAT_DTOE_MASK (0x100000U)
+#define SDHC_IRQSTAT_DTOE_SHIFT (20U)
+/*! DTOE - Data Timeout Error
+ * 0b0..No error.
+ * 0b1..Time out.
+ */
+#define SDHC_IRQSTAT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK)
+#define SDHC_IRQSTAT_DCE_MASK (0x200000U)
+#define SDHC_IRQSTAT_DCE_SHIFT (21U)
+/*! DCE - Data CRC Error
+ * 0b0..No error.
+ * 0b1..Error.
+ */
+#define SDHC_IRQSTAT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK)
+#define SDHC_IRQSTAT_DEBE_MASK (0x400000U)
+#define SDHC_IRQSTAT_DEBE_SHIFT (22U)
+/*! DEBE - Data End Bit Error
+ * 0b0..No error.
+ * 0b1..Error.
+ */
+#define SDHC_IRQSTAT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK)
+#define SDHC_IRQSTAT_AC12E_MASK (0x1000000U)
+#define SDHC_IRQSTAT_AC12E_SHIFT (24U)
+/*! AC12E - Auto CMD12 Error
+ * 0b0..No error.
+ * 0b1..Error.
+ */
+#define SDHC_IRQSTAT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK)
+#define SDHC_IRQSTAT_DMAE_MASK (0x10000000U)
+#define SDHC_IRQSTAT_DMAE_SHIFT (28U)
+/*! DMAE - DMA Error
+ * 0b0..No error.
+ * 0b1..Error.
+ */
+#define SDHC_IRQSTAT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK)
+/*! @} */
+
+/*! @name IRQSTATEN - Interrupt Status Enable register */
+/*! @{ */
+#define SDHC_IRQSTATEN_CCSEN_MASK (0x1U)
+#define SDHC_IRQSTATEN_CCSEN_SHIFT (0U)
+/*! CCSEN - Command Complete Status Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSTATEN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK)
+#define SDHC_IRQSTATEN_TCSEN_MASK (0x2U)
+#define SDHC_IRQSTATEN_TCSEN_SHIFT (1U)
+/*! TCSEN - Transfer Complete Status Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSTATEN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK)
+#define SDHC_IRQSTATEN_BGESEN_MASK (0x4U)
+#define SDHC_IRQSTATEN_BGESEN_SHIFT (2U)
+/*! BGESEN - Block Gap Event Status Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSTATEN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK)
+#define SDHC_IRQSTATEN_DINTSEN_MASK (0x8U)
+#define SDHC_IRQSTATEN_DINTSEN_SHIFT (3U)
+/*! DINTSEN - DMA Interrupt Status Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSTATEN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK)
+#define SDHC_IRQSTATEN_BWRSEN_MASK (0x10U)
+#define SDHC_IRQSTATEN_BWRSEN_SHIFT (4U)
+/*! BWRSEN - Buffer Write Ready Status Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSTATEN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK)
+#define SDHC_IRQSTATEN_BRRSEN_MASK (0x20U)
+#define SDHC_IRQSTATEN_BRRSEN_SHIFT (5U)
+/*! BRRSEN - Buffer Read Ready Status Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSTATEN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK)
+#define SDHC_IRQSTATEN_CINSEN_MASK (0x40U)
+#define SDHC_IRQSTATEN_CINSEN_SHIFT (6U)
+/*! CINSEN - Card Insertion Status Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSTATEN_CINSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK)
+#define SDHC_IRQSTATEN_CRMSEN_MASK (0x80U)
+#define SDHC_IRQSTATEN_CRMSEN_SHIFT (7U)
+/*! CRMSEN - Card Removal Status Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSTATEN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK)
+#define SDHC_IRQSTATEN_CINTSEN_MASK (0x100U)
+#define SDHC_IRQSTATEN_CINTSEN_SHIFT (8U)
+/*! CINTSEN - Card Interrupt Status Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSTATEN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK)
+#define SDHC_IRQSTATEN_CTOESEN_MASK (0x10000U)
+#define SDHC_IRQSTATEN_CTOESEN_SHIFT (16U)
+/*! CTOESEN - Command Timeout Error Status Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSTATEN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK)
+#define SDHC_IRQSTATEN_CCESEN_MASK (0x20000U)
+#define SDHC_IRQSTATEN_CCESEN_SHIFT (17U)
+/*! CCESEN - Command CRC Error Status Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSTATEN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK)
+#define SDHC_IRQSTATEN_CEBESEN_MASK (0x40000U)
+#define SDHC_IRQSTATEN_CEBESEN_SHIFT (18U)
+/*! CEBESEN - Command End Bit Error Status Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSTATEN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK)
+#define SDHC_IRQSTATEN_CIESEN_MASK (0x80000U)
+#define SDHC_IRQSTATEN_CIESEN_SHIFT (19U)
+/*! CIESEN - Command Index Error Status Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSTATEN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK)
+#define SDHC_IRQSTATEN_DTOESEN_MASK (0x100000U)
+#define SDHC_IRQSTATEN_DTOESEN_SHIFT (20U)
+/*! DTOESEN - Data Timeout Error Status Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSTATEN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK)
+#define SDHC_IRQSTATEN_DCESEN_MASK (0x200000U)
+#define SDHC_IRQSTATEN_DCESEN_SHIFT (21U)
+/*! DCESEN - Data CRC Error Status Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSTATEN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK)
+#define SDHC_IRQSTATEN_DEBESEN_MASK (0x400000U)
+#define SDHC_IRQSTATEN_DEBESEN_SHIFT (22U)
+/*! DEBESEN - Data End Bit Error Status Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSTATEN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK)
+#define SDHC_IRQSTATEN_AC12ESEN_MASK (0x1000000U)
+#define SDHC_IRQSTATEN_AC12ESEN_SHIFT (24U)
+/*! AC12ESEN - Auto CMD12 Error Status Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSTATEN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK)
+#define SDHC_IRQSTATEN_DMAESEN_MASK (0x10000000U)
+#define SDHC_IRQSTATEN_DMAESEN_SHIFT (28U)
+/*! DMAESEN - DMA Error Status Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSTATEN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK)
+/*! @} */
+
+/*! @name IRQSIGEN - Interrupt Signal Enable register */
+/*! @{ */
+#define SDHC_IRQSIGEN_CCIEN_MASK (0x1U)
+#define SDHC_IRQSIGEN_CCIEN_SHIFT (0U)
+/*! CCIEN - Command Complete Interrupt Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSIGEN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK)
+#define SDHC_IRQSIGEN_TCIEN_MASK (0x2U)
+#define SDHC_IRQSIGEN_TCIEN_SHIFT (1U)
+/*! TCIEN - Transfer Complete Interrupt Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSIGEN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK)
+#define SDHC_IRQSIGEN_BGEIEN_MASK (0x4U)
+#define SDHC_IRQSIGEN_BGEIEN_SHIFT (2U)
+/*! BGEIEN - Block Gap Event Interrupt Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSIGEN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK)
+#define SDHC_IRQSIGEN_DINTIEN_MASK (0x8U)
+#define SDHC_IRQSIGEN_DINTIEN_SHIFT (3U)
+/*! DINTIEN - DMA Interrupt Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSIGEN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK)
+#define SDHC_IRQSIGEN_BWRIEN_MASK (0x10U)
+#define SDHC_IRQSIGEN_BWRIEN_SHIFT (4U)
+/*! BWRIEN - Buffer Write Ready Interrupt Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSIGEN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK)
+#define SDHC_IRQSIGEN_BRRIEN_MASK (0x20U)
+#define SDHC_IRQSIGEN_BRRIEN_SHIFT (5U)
+/*! BRRIEN - Buffer Read Ready Interrupt Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSIGEN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK)
+#define SDHC_IRQSIGEN_CINSIEN_MASK (0x40U)
+#define SDHC_IRQSIGEN_CINSIEN_SHIFT (6U)
+/*! CINSIEN - Card Insertion Interrupt Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSIGEN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK)
+#define SDHC_IRQSIGEN_CRMIEN_MASK (0x80U)
+#define SDHC_IRQSIGEN_CRMIEN_SHIFT (7U)
+/*! CRMIEN - Card Removal Interrupt Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSIGEN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK)
+#define SDHC_IRQSIGEN_CINTIEN_MASK (0x100U)
+#define SDHC_IRQSIGEN_CINTIEN_SHIFT (8U)
+/*! CINTIEN - Card Interrupt Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSIGEN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK)
+#define SDHC_IRQSIGEN_CTOEIEN_MASK (0x10000U)
+#define SDHC_IRQSIGEN_CTOEIEN_SHIFT (16U)
+/*! CTOEIEN - Command Timeout Error Interrupt Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSIGEN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK)
+#define SDHC_IRQSIGEN_CCEIEN_MASK (0x20000U)
+#define SDHC_IRQSIGEN_CCEIEN_SHIFT (17U)
+/*! CCEIEN - Command CRC Error Interrupt Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSIGEN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK)
+#define SDHC_IRQSIGEN_CEBEIEN_MASK (0x40000U)
+#define SDHC_IRQSIGEN_CEBEIEN_SHIFT (18U)
+/*! CEBEIEN - Command End Bit Error Interrupt Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSIGEN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK)
+#define SDHC_IRQSIGEN_CIEIEN_MASK (0x80000U)
+#define SDHC_IRQSIGEN_CIEIEN_SHIFT (19U)
+/*! CIEIEN - Command Index Error Interrupt Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSIGEN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK)
+#define SDHC_IRQSIGEN_DTOEIEN_MASK (0x100000U)
+#define SDHC_IRQSIGEN_DTOEIEN_SHIFT (20U)
+/*! DTOEIEN - Data Timeout Error Interrupt Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSIGEN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK)
+#define SDHC_IRQSIGEN_DCEIEN_MASK (0x200000U)
+#define SDHC_IRQSIGEN_DCEIEN_SHIFT (21U)
+/*! DCEIEN - Data CRC Error Interrupt Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSIGEN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK)
+#define SDHC_IRQSIGEN_DEBEIEN_MASK (0x400000U)
+#define SDHC_IRQSIGEN_DEBEIEN_SHIFT (22U)
+/*! DEBEIEN - Data End Bit Error Interrupt Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSIGEN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK)
+#define SDHC_IRQSIGEN_AC12EIEN_MASK (0x1000000U)
+#define SDHC_IRQSIGEN_AC12EIEN_SHIFT (24U)
+/*! AC12EIEN - Auto CMD12 Error Interrupt Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSIGEN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK)
+#define SDHC_IRQSIGEN_DMAEIEN_MASK (0x10000000U)
+#define SDHC_IRQSIGEN_DMAEIEN_SHIFT (28U)
+/*! DMAEIEN - DMA Error Interrupt Enable
+ * 0b0..Masked
+ * 0b1..Enabled
+ */
+#define SDHC_IRQSIGEN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK)
+/*! @} */
+
+/*! @name AC12ERR - Auto CMD12 Error Status Register */
+/*! @{ */
+#define SDHC_AC12ERR_AC12NE_MASK (0x1U)
+#define SDHC_AC12ERR_AC12NE_SHIFT (0U)
+/*! AC12NE - Auto CMD12 Not Executed
+ * 0b0..Executed.
+ * 0b1..Not executed.
+ */
+#define SDHC_AC12ERR_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK)
+#define SDHC_AC12ERR_AC12TOE_MASK (0x2U)
+#define SDHC_AC12ERR_AC12TOE_SHIFT (1U)
+/*! AC12TOE - Auto CMD12 Timeout Error
+ * 0b0..No error.
+ * 0b1..Time out.
+ */
+#define SDHC_AC12ERR_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK)
+#define SDHC_AC12ERR_AC12EBE_MASK (0x4U)
+#define SDHC_AC12ERR_AC12EBE_SHIFT (2U)
+/*! AC12EBE - Auto CMD12 End Bit Error
+ * 0b0..No error.
+ * 0b1..End bit error generated.
+ */
+#define SDHC_AC12ERR_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK)
+#define SDHC_AC12ERR_AC12CE_MASK (0x8U)
+#define SDHC_AC12ERR_AC12CE_SHIFT (3U)
+/*! AC12CE - Auto CMD12 CRC Error
+ * 0b0..No CRC error.
+ * 0b1..CRC error met in Auto CMD12 response.
+ */
+#define SDHC_AC12ERR_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK)
+#define SDHC_AC12ERR_AC12IE_MASK (0x10U)
+#define SDHC_AC12ERR_AC12IE_SHIFT (4U)
+/*! AC12IE - Auto CMD12 Index Error
+ * 0b0..No error.
+ * 0b1..Error, the CMD index in response is not CMD12.
+ */
+#define SDHC_AC12ERR_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK)
+#define SDHC_AC12ERR_CNIBAC12E_MASK (0x80U)
+#define SDHC_AC12ERR_CNIBAC12E_SHIFT (7U)
+/*! CNIBAC12E - Command Not Issued By Auto CMD12 Error
+ * 0b0..No error.
+ * 0b1..Not issued.
+ */
+#define SDHC_AC12ERR_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK)
+/*! @} */
+
+/*! @name HTCAPBLT - Host Controller Capabilities */
+/*! @{ */
+#define SDHC_HTCAPBLT_MBL_MASK (0x70000U)
+#define SDHC_HTCAPBLT_MBL_SHIFT (16U)
+/*! MBL - Max Block Length
+ * 0b000..512 bytes
+ * 0b001..1024 bytes
+ * 0b010..2048 bytes
+ * 0b011..4096 bytes
+ */
+#define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)
+#define SDHC_HTCAPBLT_ADMAS_MASK (0x100000U)
+#define SDHC_HTCAPBLT_ADMAS_SHIFT (20U)
+/*! ADMAS - ADMA Support
+ * 0b0..Advanced DMA not supported.
+ * 0b1..Advanced DMA supported.
+ */
+#define SDHC_HTCAPBLT_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK)
+#define SDHC_HTCAPBLT_HSS_MASK (0x200000U)
+#define SDHC_HTCAPBLT_HSS_SHIFT (21U)
+/*! HSS - High Speed Support
+ * 0b0..High speed not supported.
+ * 0b1..High speed supported.
+ */
+#define SDHC_HTCAPBLT_HSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK)
+#define SDHC_HTCAPBLT_DMAS_MASK (0x400000U)
+#define SDHC_HTCAPBLT_DMAS_SHIFT (22U)
+/*! DMAS - DMA Support
+ * 0b0..DMA not supported.
+ * 0b1..DMA supported.
+ */
+#define SDHC_HTCAPBLT_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK)
+#define SDHC_HTCAPBLT_SRS_MASK (0x800000U)
+#define SDHC_HTCAPBLT_SRS_SHIFT (23U)
+/*! SRS - Suspend/Resume Support
+ * 0b0..Not supported.
+ * 0b1..Supported.
+ */
+#define SDHC_HTCAPBLT_SRS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK)
+#define SDHC_HTCAPBLT_VS33_MASK (0x1000000U)
+#define SDHC_HTCAPBLT_VS33_SHIFT (24U)
+/*! VS33 - Voltage Support 3.3 V
+ * 0b0..3.3 V not supported.
+ * 0b1..3.3 V supported.
+ */
+#define SDHC_HTCAPBLT_VS33(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK)
+/*! @} */
+
+/*! @name WML - Watermark Level Register */
+/*! @{ */
+#define SDHC_WML_RDWML_MASK (0xFFU)
+#define SDHC_WML_RDWML_SHIFT (0U)
+#define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK)
+#define SDHC_WML_WRWML_MASK (0xFF0000U)
+#define SDHC_WML_WRWML_SHIFT (16U)
+#define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK)
+/*! @} */
+
+/*! @name FEVT - Force Event register */
+/*! @{ */
+#define SDHC_FEVT_AC12NE_MASK (0x1U)
+#define SDHC_FEVT_AC12NE_SHIFT (0U)
+#define SDHC_FEVT_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK)
+#define SDHC_FEVT_AC12TOE_MASK (0x2U)
+#define SDHC_FEVT_AC12TOE_SHIFT (1U)
+#define SDHC_FEVT_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12TOE_SHIFT)) & SDHC_FEVT_AC12TOE_MASK)
+#define SDHC_FEVT_AC12CE_MASK (0x4U)
+#define SDHC_FEVT_AC12CE_SHIFT (2U)
+#define SDHC_FEVT_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12CE_SHIFT)) & SDHC_FEVT_AC12CE_MASK)
+#define SDHC_FEVT_AC12EBE_MASK (0x8U)
+#define SDHC_FEVT_AC12EBE_SHIFT (3U)
+#define SDHC_FEVT_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12EBE_SHIFT)) & SDHC_FEVT_AC12EBE_MASK)
+#define SDHC_FEVT_AC12IE_MASK (0x10U)
+#define SDHC_FEVT_AC12IE_SHIFT (4U)
+#define SDHC_FEVT_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12IE_SHIFT)) & SDHC_FEVT_AC12IE_MASK)
+#define SDHC_FEVT_CNIBAC12E_MASK (0x80U)
+#define SDHC_FEVT_CNIBAC12E_SHIFT (7U)
+#define SDHC_FEVT_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CNIBAC12E_SHIFT)) & SDHC_FEVT_CNIBAC12E_MASK)
+#define SDHC_FEVT_CTOE_MASK (0x10000U)
+#define SDHC_FEVT_CTOE_SHIFT (16U)
+#define SDHC_FEVT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CTOE_SHIFT)) & SDHC_FEVT_CTOE_MASK)
+#define SDHC_FEVT_CCE_MASK (0x20000U)
+#define SDHC_FEVT_CCE_SHIFT (17U)
+#define SDHC_FEVT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CCE_SHIFT)) & SDHC_FEVT_CCE_MASK)
+#define SDHC_FEVT_CEBE_MASK (0x40000U)
+#define SDHC_FEVT_CEBE_SHIFT (18U)
+#define SDHC_FEVT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CEBE_SHIFT)) & SDHC_FEVT_CEBE_MASK)
+#define SDHC_FEVT_CIE_MASK (0x80000U)
+#define SDHC_FEVT_CIE_SHIFT (19U)
+#define SDHC_FEVT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CIE_SHIFT)) & SDHC_FEVT_CIE_MASK)
+#define SDHC_FEVT_DTOE_MASK (0x100000U)
+#define SDHC_FEVT_DTOE_SHIFT (20U)
+#define SDHC_FEVT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DTOE_SHIFT)) & SDHC_FEVT_DTOE_MASK)
+#define SDHC_FEVT_DCE_MASK (0x200000U)
+#define SDHC_FEVT_DCE_SHIFT (21U)
+#define SDHC_FEVT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DCE_SHIFT)) & SDHC_FEVT_DCE_MASK)
+#define SDHC_FEVT_DEBE_MASK (0x400000U)
+#define SDHC_FEVT_DEBE_SHIFT (22U)
+#define SDHC_FEVT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DEBE_SHIFT)) & SDHC_FEVT_DEBE_MASK)
+#define SDHC_FEVT_AC12E_MASK (0x1000000U)
+#define SDHC_FEVT_AC12E_SHIFT (24U)
+#define SDHC_FEVT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12E_SHIFT)) & SDHC_FEVT_AC12E_MASK)
+#define SDHC_FEVT_DMAE_MASK (0x10000000U)
+#define SDHC_FEVT_DMAE_SHIFT (28U)
+#define SDHC_FEVT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DMAE_SHIFT)) & SDHC_FEVT_DMAE_MASK)
+#define SDHC_FEVT_CINT_MASK (0x80000000U)
+#define SDHC_FEVT_CINT_SHIFT (31U)
+#define SDHC_FEVT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK)
+/*! @} */
+
+/*! @name ADMAES - ADMA Error Status register */
+/*! @{ */
+#define SDHC_ADMAES_ADMAES_MASK (0x3U)
+#define SDHC_ADMAES_ADMAES_SHIFT (0U)
+#define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK)
+#define SDHC_ADMAES_ADMALME_MASK (0x4U)
+#define SDHC_ADMAES_ADMALME_SHIFT (2U)
+/*! ADMALME - ADMA Length Mismatch Error
+ * 0b0..No error.
+ * 0b1..Error.
+ */
+#define SDHC_ADMAES_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK)
+#define SDHC_ADMAES_ADMADCE_MASK (0x8U)
+#define SDHC_ADMAES_ADMADCE_SHIFT (3U)
+/*! ADMADCE - ADMA Descriptor Error
+ * 0b0..No error.
+ * 0b1..Error.
+ */
+#define SDHC_ADMAES_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK)
+/*! @} */
+
+/*! @name ADSADDR - ADMA System Addressregister */
+/*! @{ */
+#define SDHC_ADSADDR_ADSADDR_MASK (0xFFFFFFFCU)
+#define SDHC_ADSADDR_ADSADDR_SHIFT (2U)
+#define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK)
+/*! @} */
+
+/*! @name VENDOR - Vendor Specific register */
+/*! @{ */
+#define SDHC_VENDOR_EXBLKNU_MASK (0x2U)
+#define SDHC_VENDOR_EXBLKNU_SHIFT (1U)
+/*! EXBLKNU - Exact Block Number Block Read Enable For SDIO CMD53
+ * 0b0..None exact block read.
+ * 0b1..Exact block read for SDIO CMD53.
+ */
+#define SDHC_VENDOR_EXBLKNU(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK)
+#define SDHC_VENDOR_INTSTVAL_MASK (0xFF0000U)
+#define SDHC_VENDOR_INTSTVAL_SHIFT (16U)
+#define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK)
+/*! @} */
+
+/*! @name MMCBOOT - MMC Boot register */
+/*! @{ */
+#define SDHC_MMCBOOT_DTOCVACK_MASK (0xFU)
+#define SDHC_MMCBOOT_DTOCVACK_SHIFT (0U)
+/*! DTOCVACK - Boot ACK Time Out Counter Value
+ * 0b0000..SDCLK x 2^8
+ * 0b0001..SDCLK x 2^9
+ * 0b0010..SDCLK x 2^10
+ * 0b0011..SDCLK x 2^11
+ * 0b0100..SDCLK x 2^12
+ * 0b0101..SDCLK x 2^13
+ * 0b0110..SDCLK x 2^14
+ * 0b0111..SDCLK x 2^15
+ * 0b1110..SDCLK x 2^22
+ * 0b1111..Reserved
+ */
+#define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)
+#define SDHC_MMCBOOT_BOOTACK_MASK (0x10U)
+#define SDHC_MMCBOOT_BOOTACK_SHIFT (4U)
+/*! BOOTACK - Boot Ack Mode Select
+ * 0b0..No ack.
+ * 0b1..Ack.
+ */
+#define SDHC_MMCBOOT_BOOTACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK)
+#define SDHC_MMCBOOT_BOOTMODE_MASK (0x20U)
+#define SDHC_MMCBOOT_BOOTMODE_SHIFT (5U)
+/*! BOOTMODE - Boot Mode Select
+ * 0b0..Normal boot.
+ * 0b1..Alternative boot.
+ */
+#define SDHC_MMCBOOT_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK)
+#define SDHC_MMCBOOT_BOOTEN_MASK (0x40U)
+#define SDHC_MMCBOOT_BOOTEN_SHIFT (6U)
+/*! BOOTEN - Boot Mode Enable
+ * 0b0..Fast boot disable.
+ * 0b1..Fast boot enable.
+ */
+#define SDHC_MMCBOOT_BOOTEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK)
+#define SDHC_MMCBOOT_AUTOSABGEN_MASK (0x80U)
+#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT (7U)
+#define SDHC_MMCBOOT_AUTOSABGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_AUTOSABGEN_SHIFT)) & SDHC_MMCBOOT_AUTOSABGEN_MASK)
+#define SDHC_MMCBOOT_BOOTBLKCNT_MASK (0xFFFF0000U)
+#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT (16U)
+#define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK)
+/*! @} */
+
+/*! @name HOSTVER - Host Controller Version */
+/*! @{ */
+#define SDHC_HOSTVER_SVN_MASK (0xFFU)
+#define SDHC_HOSTVER_SVN_SHIFT (0U)
+/*! SVN - Specification Version Number
+ * 0b00000001..SD host specification version 2.0, supports test event register and ADMA.
+ */
+#define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)
+#define SDHC_HOSTVER_VVN_MASK (0xFF00U)
+#define SDHC_HOSTVER_VVN_SHIFT (8U)
+/*! VVN - Vendor Version Number
+ * 0b00000000..Freescale SDHC version 1.0
+ * 0b00010000..Freescale SDHC version 2.0
+ * 0b00010001..Freescale SDHC version 2.1
+ * 0b00010010..Freescale SDHC version 2.2
+ */
+#define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Masks */
+
+
+/* SDHC - Peripheral instance base addresses */
+/** Peripheral SDHC base address */
+#define SDHC_BASE (0x400B1000u)
+/** Peripheral SDHC base pointer */
+#define SDHC ((SDHC_Type *)SDHC_BASE)
+/** Array initializer of SDHC peripheral base addresses */
+#define SDHC_BASE_ADDRS { SDHC_BASE }
+/** Array initializer of SDHC peripheral base pointers */
+#define SDHC_BASE_PTRS { SDHC }
+/** Interrupt vectors for the SDHC peripheral type */
+#define SDHC_IRQS { SDHC_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SDHC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SDRAM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDRAM_Peripheral_Access_Layer SDRAM Peripheral Access Layer
+ * @{
+ */
+
+/** SDRAM - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[66];
+ __IO uint16_t CTRL; /**< Control Register, offset: 0x42 */
+ uint8_t RESERVED_1[4];
+ struct { /* offset: 0x48, array step: 0x8 */
+ __IO uint32_t AC; /**< Address and Control Register, array offset: 0x48, array step: 0x8 */
+ __IO uint32_t CM; /**< Control Mask, array offset: 0x4C, array step: 0x8 */
+ } BLOCK[2];
+} SDRAM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SDRAM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDRAM_Register_Masks SDRAM Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control Register */
+/*! @{ */
+#define SDRAM_CTRL_RC_MASK (0x1FFU)
+#define SDRAM_CTRL_RC_SHIFT (0U)
+#define SDRAM_CTRL_RC(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RC_SHIFT)) & SDRAM_CTRL_RC_MASK)
+#define SDRAM_CTRL_RTIM_MASK (0x600U)
+#define SDRAM_CTRL_RTIM_SHIFT (9U)
+/*! RTIM - Refresh timing
+ * 0b00..3 clocks
+ * 0b01..6 clocks
+ * 0b10..9 clocks
+ * 0b11..9 clocks
+ */
+#define SDRAM_CTRL_RTIM(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RTIM_SHIFT)) & SDRAM_CTRL_RTIM_MASK)
+#define SDRAM_CTRL_IS_MASK (0x800U)
+#define SDRAM_CTRL_IS_SHIFT (11U)
+/*! IS
+ * 0b0..Take no action or issue a selfx command to exit self refresh.
+ * 0b1..SDRAM controller sends a self command to both SDRAM blocks to put them in low-power, self-refresh state where they remain until IS is cleared. When IS is cleared, the controller sends a selfx command for the SDRAMs to exit self-refresh. The refresh counter is suspended while the SDRAMs are in self-refresh; the SDRAM controls the refresh period.
+ */
+#define SDRAM_CTRL_IS(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_IS_SHIFT)) & SDRAM_CTRL_IS_MASK)
+/*! @} */
+
+/*! @name AC - Address and Control Register */
+/*! @{ */
+#define SDRAM_AC_IP_MASK (0x8U)
+#define SDRAM_AC_IP_SHIFT (3U)
+/*! IP - Initiate precharge all (pall) command.
+ * 0b0..Take no action.
+ * 0b1..A pall command is sent to the associated SDRAM block. During initialization, this command is executed after all DRAM controller registers are programmed. After IP is set, the next write to an appropriate SDRAM address generates the pall command to the SDRAM block.
+ */
+#define SDRAM_AC_IP(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IP_SHIFT)) & SDRAM_AC_IP_MASK)
+#define SDRAM_AC_PS_MASK (0x30U)
+#define SDRAM_AC_PS_SHIFT (4U)
+/*! PS - Port size.
+ * 0b00..32-bit port
+ * 0b01..8-bit port
+ * 0b10..16-bit port
+ * 0b11..16-bit port
+ */
+#define SDRAM_AC_PS(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_PS_SHIFT)) & SDRAM_AC_PS_MASK)
+#define SDRAM_AC_IMRS_MASK (0x40U)
+#define SDRAM_AC_IMRS_SHIFT (6U)
+/*! IMRS - Initiate mode register set (mrs) command.
+ * 0b0..Take no action
+ * 0b1..Initiate mrs command
+ */
+#define SDRAM_AC_IMRS(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IMRS_SHIFT)) & SDRAM_AC_IMRS_MASK)
+#define SDRAM_AC_CBM_MASK (0x700U)
+#define SDRAM_AC_CBM_SHIFT (8U)
+#define SDRAM_AC_CBM(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CBM_SHIFT)) & SDRAM_AC_CBM_MASK)
+#define SDRAM_AC_CASL_MASK (0x3000U)
+#define SDRAM_AC_CASL_SHIFT (12U)
+#define SDRAM_AC_CASL(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CASL_SHIFT)) & SDRAM_AC_CASL_MASK)
+#define SDRAM_AC_RE_MASK (0x8000U)
+#define SDRAM_AC_RE_SHIFT (15U)
+/*! RE - Refresh enable
+ * 0b0..Do not refresh associated DRAM block
+ * 0b1..Refresh associated DRAM block
+ */
+#define SDRAM_AC_RE(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_RE_SHIFT)) & SDRAM_AC_RE_MASK)
+#define SDRAM_AC_BA_MASK (0xFFFC0000U)
+#define SDRAM_AC_BA_SHIFT (18U)
+#define SDRAM_AC_BA(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_BA_SHIFT)) & SDRAM_AC_BA_MASK)
+/*! @} */
+
+/* The count of SDRAM_AC */
+#define SDRAM_AC_COUNT (2U)
+
+/*! @name CM - Control Mask */
+/*! @{ */
+#define SDRAM_CM_V_MASK (0x1U)
+#define SDRAM_CM_V_SHIFT (0U)
+/*! V - Valid.
+ * 0b0..Do not decode DRAM accesses.
+ * 0b1..Registers controlling the DRAM block are initialized; DRAM accesses can be decoded
+ */
+#define SDRAM_CM_V(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_V_SHIFT)) & SDRAM_CM_V_MASK)
+#define SDRAM_CM_WP_MASK (0x100U)
+#define SDRAM_CM_WP_SHIFT (8U)
+/*! WP - Write protect.
+ * 0b0..Allow write accesses
+ * 0b1..Ignore write accesses. The DRAM controller ignores write accesses to the memory block and an address exception occurs. Write accesses to a write-protected DRAM region are compared in the chip select module for a hit. If no hit occurs, an external bus cycle is generated. If this external bus cycle is not acknowledged, an access exception occurs.
+ */
+#define SDRAM_CM_WP(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_WP_SHIFT)) & SDRAM_CM_WP_MASK)
+#define SDRAM_CM_BAM_MASK (0xFFFC0000U)
+#define SDRAM_CM_BAM_SHIFT (18U)
+/*! BAM - Base address mask.
+ * 0b00000000000000..The associated address bit is used in decoding the DRAM hit to a memory block
+ * 0b00000000000001..The associated address bit is not used in the DRAM hit decode
+ */
+#define SDRAM_CM_BAM(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_BAM_SHIFT)) & SDRAM_CM_BAM_MASK)
+/*! @} */
+
+/* The count of SDRAM_CM */
+#define SDRAM_CM_COUNT (2U)
+
+
+/*!
+ * @}
+ */ /* end of group SDRAM_Register_Masks */
+
+
+/* SDRAM - Peripheral instance base addresses */
+/** Peripheral SDRAM base address */
+#define SDRAM_BASE (0x4000F000u)
+/** Peripheral SDRAM base pointer */
+#define SDRAM ((SDRAM_Type *)SDRAM_BASE)
+/** Array initializer of SDRAM peripheral base addresses */
+#define SDRAM_BASE_ADDRS { SDRAM_BASE }
+/** Array initializer of SDRAM peripheral base pointers */
+#define SDRAM_BASE_PTRS { SDRAM }
+
+/*!
+ * @}
+ */ /* end of group SDRAM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
+ __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
+ __IO uint32_t USBPHYCTL; /**< USB PHY Control Register, offset: 0x8 */
+ uint8_t RESERVED_0[4088];
+ __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
+ __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
+ __IO uint32_t SOPT8; /**< System Options Register 8, offset: 0x101C */
+ __IO uint32_t SOPT9; /**< System Options Register 9, offset: 0x1020 */
+ __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
+ __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
+ __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
+ __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
+ __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
+ __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
+ __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
+ __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
+ __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
+ __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
+ __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
+ __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
+ __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
+ __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
+ __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
+ __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
+ __IO uint32_t CLKDIV3; /**< System Clock Divider Register 3, offset: 0x1064 */
+ __IO uint32_t CLKDIV4; /**< System Clock Divider Register 4, offset: 0x1068 */
+} SIM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SIM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/*! @name SOPT1 - System Options Register 1 */
+/*! @{ */
+#define SIM_SOPT1_RAMSIZE_MASK (0xF000U)
+#define SIM_SOPT1_RAMSIZE_SHIFT (12U)
+/*! RAMSIZE - RAM size
+ * 0b0001..8 KB
+ * 0b0011..16 KB
+ * 0b0100..24 KB
+ * 0b0101..32 KB
+ * 0b0110..48 KB
+ * 0b0111..64 KB
+ * 0b1000..96 KB
+ * 0b1001..128 KB
+ * 0b1011..256 KB
+ */
+#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
+#define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
+/*! OSC32KSEL - 32K oscillator clock select
+ * 0b00..System oscillator (OSC32KCLK)
+ * 0b01..Reserved
+ * 0b10..RTC 32.768kHz oscillator
+ * 0b11..LPO 1 kHz
+ */
+#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK (0x20000000U)
+#define SIM_SOPT1_USBVSTBY_SHIFT (29U)
+/*! USBVSTBY - USB voltage regulator in standby mode during VLPR and VLPW modes
+ * 0b0..USB voltage regulator not in standby during VLPR and VLPW modes.
+ * 0b1..USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+#define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
+#define SIM_SOPT1_USBSSTBY_MASK (0x40000000U)
+#define SIM_SOPT1_USBSSTBY_SHIFT (30U)
+/*! USBSSTBY - USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes.
+ * 0b0..USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes.
+ * 0b1..USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.
+ */
+#define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
+#define SIM_SOPT1_USBREGEN_MASK (0x80000000U)
+#define SIM_SOPT1_USBREGEN_SHIFT (31U)
+/*! USBREGEN - USB voltage regulator enable
+ * 0b0..USB voltage regulator is disabled.
+ * 0b1..USB voltage regulator is enabled.
+ */
+#define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
+/*! @} */
+
+/*! @name SOPT1CFG - SOPT1 Configuration Register */
+/*! @{ */
+#define SIM_SOPT1CFG_URWE_MASK (0x1000000U)
+#define SIM_SOPT1CFG_URWE_SHIFT (24U)
+/*! URWE - USB voltage regulator enable write enable
+ * 0b0..SOPT1 USBREGEN cannot be written.
+ * 0b1..SOPT1 USBREGEN can be written.
+ */
+#define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
+#define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U)
+#define SIM_SOPT1CFG_UVSWE_SHIFT (25U)
+/*! UVSWE - USB voltage regulator VLP standby write enable
+ * 0b0..SOPT1 USBVSTBY cannot be written.
+ * 0b1..SOPT1 USBVSTBY can be written.
+ */
+#define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
+#define SIM_SOPT1CFG_USSWE_MASK (0x4000000U)
+#define SIM_SOPT1CFG_USSWE_SHIFT (26U)
+/*! USSWE - USB voltage regulator stop standby write enable
+ * 0b0..SOPT1 USBSSTBY cannot be written.
+ * 0b1..SOPT1 USBSSTBY can be written.
+ */
+#define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
+/*! @} */
+
+/*! @name USBPHYCTL - USB PHY Control Register */
+/*! @{ */
+#define SIM_USBPHYCTL_USBVREGSEL_MASK (0x100U)
+#define SIM_USBPHYCTL_USBVREGSEL_SHIFT (8U)
+/*! USBVREGSEL
+ * 0b0..VREG_IN0 will be selected if both regulator inputs are powered
+ * 0b1..VREG_IN1 will be selected if both regulator inputs are powered
+ */
+#define SIM_USBPHYCTL_USBVREGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBVREGSEL_SHIFT)) & SIM_USBPHYCTL_USBVREGSEL_MASK)
+#define SIM_USBPHYCTL_USBVREGPD_MASK (0x200U)
+#define SIM_USBPHYCTL_USBVREGPD_SHIFT (9U)
+/*! USBVREGPD
+ * 0b0..Regulator output pulldown resistor is not enabled
+ * 0b1..Regulator output pulldown resistor is enabled
+ */
+#define SIM_USBPHYCTL_USBVREGPD(x) (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBVREGPD_SHIFT)) & SIM_USBPHYCTL_USBVREGPD_MASK)
+#define SIM_USBPHYCTL_USB3VOUTTRG_MASK (0x700000U)
+#define SIM_USBPHYCTL_USB3VOUTTRG_SHIFT (20U)
+/*! USB3VOUTTRG - USB 3.3V Output Target
+ * 0b000..2.733V
+ * 0b001..3.020V
+ * 0b010..3.074V
+ * 0b011..3.130V
+ * 0b100..3.188V
+ * 0b101..3.248V
+ * 0b110..3.310V (default)
+ * 0b111..3.662V (For Freescale use only, not for customer use)
+ */
+#define SIM_USBPHYCTL_USB3VOUTTRG(x) (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT)) & SIM_USBPHYCTL_USB3VOUTTRG_MASK)
+#define SIM_USBPHYCTL_USBDISILIM_MASK (0x800000U)
+#define SIM_USBPHYCTL_USBDISILIM_SHIFT (23U)
+/*! USBDISILIM - USB Disable Inrush Current Limit
+ * 0b0..The current limiter for the USB Voltage Regulator is enabled
+ * 0b1..The current limiter for the USB Voltage Regulator is disabled
+ */
+#define SIM_USBPHYCTL_USBDISILIM(x) (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBDISILIM_SHIFT)) & SIM_USBPHYCTL_USBDISILIM_MASK)
+/*! @} */
+
+/*! @name SOPT2 - System Options Register 2 */
+/*! @{ */
+#define SIM_SOPT2_USBSLSRC_MASK (0x1U)
+#define SIM_SOPT2_USBSLSRC_SHIFT (0U)
+/*! USBSLSRC - USB Slow Clock Source
+ * 0b0..MCGIRCLK
+ * 0b1..RTC 32.768kHz clock
+ */
+#define SIM_SOPT2_USBSLSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSLSRC_SHIFT)) & SIM_SOPT2_USBSLSRC_MASK)
+#define SIM_SOPT2_USBREGEN_MASK (0x2U)
+#define SIM_SOPT2_USBREGEN_SHIFT (1U)
+/*! USBREGEN - USB PHY PLL Regulator Enable
+ * 0b0..USB PHY PLL Regulator disabled.
+ * 0b1..USB PHY PLL Regulator enabled.
+ */
+#define SIM_SOPT2_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBREGEN_SHIFT)) & SIM_SOPT2_USBREGEN_MASK)
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
+/*! RTCCLKOUTSEL - RTC clock out select
+ * 0b0..RTC 1 Hz clock is output on the RTC_CLKOUT pin.
+ * 0b1..RTC 32.768kHz clock is output on the RTC_CLKOUT pin.
+ */
+#define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
+#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
+#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
+/*! CLKOUTSEL - CLKOUT select
+ * 0b000..FlexBus CLKOUT
+ * 0b001..Reserved
+ * 0b010..Flash clock
+ * 0b011..LPO clock (1 kHz)
+ * 0b100..MCGIRCLK
+ * 0b101..RTC 32.768kHz clock
+ * 0b110..OSCERCLK0
+ * 0b111..IRC 48 MHz clock
+ */
+#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_FBSL_MASK (0x300U)
+#define SIM_SOPT2_FBSL_SHIFT (8U)
+/*! FBSL - FlexBus security level
+ * 0b00..All off-chip accesses (instruction and data) via the FlexBus or SDRAM are disallowed.
+ * 0b01..All off-chip accesses (instruction and data) via the FlexBus or SDRAM are disallowed.
+ * 0b10..Off-chip instruction accesses are disallowed. Data accesses are allowed.
+ * 0b11..Off-chip instruction accesses and data accesses are allowed.
+ */
+#define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)
+#define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U)
+#define SIM_SOPT2_TRACECLKSEL_SHIFT (12U)
+/*! TRACECLKSEL - Debug trace clock select
+ * 0b0..MCGOUTCLK, divided by the TRACECLK fractional divider as configured by SIM_CLKDIV4[TRACEFRAC, TRACEDIV]
+ * 0b1..Core/system clock
+ */
+#define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
+#define SIM_SOPT2_PLLFLLSEL_MASK (0x30000U)
+#define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
+/*! PLLFLLSEL - PLL/FLL clock select
+ * 0b00..MCGFLLCLK clock
+ * 0b01..MCGPLLCLK clock
+ * 0b10..USB1 PFD clock
+ * 0b11..IRC48 MHz clock
+ */
+#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
+#define SIM_SOPT2_USBSRC_MASK (0x40000U)
+#define SIM_SOPT2_USBSRC_SHIFT (18U)
+/*! USBSRC - USB clock source select
+ * 0b0..External bypass clock (USB_CLKIN).
+ * 0b1..MCGFLLCLK, or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by SIM_CLKDIV2[USBFRAC, USBDIV].
+ */
+#define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
+#define SIM_SOPT2_TPMSRC_MASK (0x3000000U)
+#define SIM_SOPT2_TPMSRC_SHIFT (24U)
+/*! TPMSRC - TPM clock source select
+ * 0b00..Clock disabled
+ * 0b01..MCGFLLCLK , or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL], and then divided by the PLLFLLCLK fractional divider as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV].
+ * 0b10..OSCERCLK clock
+ * 0b11..MCGIRCLK clock
+ */
+#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)
+#define SIM_SOPT2_LPUARTSRC_MASK (0xC000000U)
+#define SIM_SOPT2_LPUARTSRC_SHIFT (26U)
+/*! LPUARTSRC - LPUART clock source select
+ * 0b00..Clock disabled
+ * 0b01..MCGFLLCLK , or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL], and then divided by the PLLFLLCLK fractional divider as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV].
+ * 0b10..OSCERCLK clock
+ * 0b11..MCGIRCLK clock
+ */
+#define SIM_SOPT2_LPUARTSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUARTSRC_SHIFT)) & SIM_SOPT2_LPUARTSRC_MASK)
+#define SIM_SOPT2_SDHCSRC_MASK (0x30000000U)
+#define SIM_SOPT2_SDHCSRC_SHIFT (28U)
+/*! SDHCSRC - SDHC clock source select
+ * 0b00..Core/system clock.
+ * 0b01..MCGFLLCLK, or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL].
+ * 0b10..OSCERCLK clock
+ * 0b11..External bypass clock (SDHC0_CLKIN)
+ */
+#define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)
+/*! @} */
+
+/*! @name SOPT4 - System Options Register 4 */
+/*! @{ */
+#define SIM_SOPT4_FTM0FLT0_MASK (0x1U)
+#define SIM_SOPT4_FTM0FLT0_SHIFT (0U)
+/*! FTM0FLT0 - FTM0 Fault 0 Select
+ * 0b0..FTM0_FLT0 pin
+ * 0b1..CMP0 out
+ */
+#define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
+#define SIM_SOPT4_FTM0FLT1_MASK (0x2U)
+#define SIM_SOPT4_FTM0FLT1_SHIFT (1U)
+/*! FTM0FLT1 - FTM0 Fault 1 Select
+ * 0b0..FTM0_FLT1 pin
+ * 0b1..CMP1 out
+ */
+#define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
+#define SIM_SOPT4_FTM0FLT2_MASK (0x4U)
+#define SIM_SOPT4_FTM0FLT2_SHIFT (2U)
+/*! FTM0FLT2 - FTM0 Fault 2 Select
+ * 0b0..FTM0_FLT2 pin
+ * 0b1..CMP2 out
+ */
+#define SIM_SOPT4_FTM0FLT2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)
+#define SIM_SOPT4_FTM0FLT3_MASK (0x8U)
+#define SIM_SOPT4_FTM0FLT3_SHIFT (3U)
+/*! FTM0FLT3 - FTM0 Fault 3 Select
+ * 0b0..FTM0_FLT3 pin
+ * 0b1..CMP3 out
+ */
+#define SIM_SOPT4_FTM0FLT3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT3_SHIFT)) & SIM_SOPT4_FTM0FLT3_MASK)
+#define SIM_SOPT4_FTM1FLT0_MASK (0x10U)
+#define SIM_SOPT4_FTM1FLT0_SHIFT (4U)
+/*! FTM1FLT0 - FTM1 Fault 0 Select
+ * 0b0..FTM1_FLT0 pin
+ * 0b1..CMP0 out
+ */
+#define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
+#define SIM_SOPT4_FTM2FLT0_MASK (0x100U)
+#define SIM_SOPT4_FTM2FLT0_SHIFT (8U)
+/*! FTM2FLT0 - FTM2 Fault 0 Select
+ * 0b0..FTM2_FLT0 pin
+ * 0b1..CMP0 out
+ */
+#define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
+#define SIM_SOPT4_FTM3FLT0_MASK (0x1000U)
+#define SIM_SOPT4_FTM3FLT0_SHIFT (12U)
+/*! FTM3FLT0 - FTM3 Fault 0 Select
+ * 0b0..FTM3_FLT0 pin
+ * 0b1..CMP0 out
+ */
+#define SIM_SOPT4_FTM3FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK)
+#define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U)
+#define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U)
+/*! FTM1CH0SRC - FTM1 channel 0 input capture source select
+ * 0b00..FTM1_CH0 signal
+ * 0b01..CMP0 output
+ * 0b10..CMP1 output
+ * 0b11..USB start of frame pulse
+ */
+#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U)
+#define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U)
+/*! FTM2CH0SRC - FTM2 channel 0 input capture source select
+ * 0b00..FTM2_CH0 signal
+ * 0b01..CMP0 output
+ * 0b10..CMP1 output
+ * 0b11..Reserved
+ */
+#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH1SRC_MASK (0x400000U)
+#define SIM_SOPT4_FTM2CH1SRC_SHIFT (22U)
+/*! FTM2CH1SRC - FTM2 channel 1 input capture source select
+ * 0b0..FTM2_CH1 signal
+ * 0b1..Exclusive OR of FTM2_CH1, FTM2_CH0 and FTM1_CH1.
+ */
+#define SIM_SOPT4_FTM2CH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH1SRC_SHIFT)) & SIM_SOPT4_FTM2CH1SRC_MASK)
+#define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U)
+#define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U)
+/*! FTM0CLKSEL - FlexTimer 0 External Clock Pin Select
+ * 0b0..FTM_CLK0 pin
+ * 0b1..FTM_CLK1 pin
+ */
+#define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
+#define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U)
+#define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U)
+/*! FTM1CLKSEL - FTM1 External Clock Pin Select
+ * 0b0..FTM_CLK0 pin
+ * 0b1..FTM_CLK1 pin
+ */
+#define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
+#define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U)
+#define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U)
+/*! FTM2CLKSEL - FlexTimer 2 External Clock Pin Select
+ * 0b0..FTM2 external clock driven by FTM_CLK0 pin.
+ * 0b1..FTM2 external clock driven by FTM_CLK1 pin.
+ */
+#define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
+#define SIM_SOPT4_FTM3CLKSEL_MASK (0x8000000U)
+#define SIM_SOPT4_FTM3CLKSEL_SHIFT (27U)
+/*! FTM3CLKSEL - FlexTimer 3 External Clock Pin Select
+ * 0b0..FTM3 external clock driven by FTM_CLK0 pin.
+ * 0b1..FTM3 external clock driven by FTM_CLK1 pin.
+ */
+#define SIM_SOPT4_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK)
+#define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U)
+#define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U)
+/*! FTM0TRG0SRC - FlexTimer 0 Hardware Trigger 0 Source Select
+ * 0b0..HSCMP0 output drives FTM0 hardware trigger 0
+ * 0b1..FTM1 channel match drives FTM0 hardware trigger 0
+ */
+#define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
+#define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U)
+#define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U)
+/*! FTM0TRG1SRC - FlexTimer 0 Hardware Trigger 1 Source Select
+ * 0b0..PDB output trigger 1 drives FTM0 hardware trigger 1
+ * 0b1..FTM2 channel match drives FTM0 hardware trigger 1
+ */
+#define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
+#define SIM_SOPT4_FTM3TRG0SRC_MASK (0x40000000U)
+#define SIM_SOPT4_FTM3TRG0SRC_SHIFT (30U)
+/*! FTM3TRG0SRC - FlexTimer 3 Hardware Trigger 0 Source Select
+ * 0b0..Reserved
+ * 0b1..FTM1 channel match drives FTM3 hardware trigger 0
+ */
+#define SIM_SOPT4_FTM3TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK)
+#define SIM_SOPT4_FTM3TRG1SRC_MASK (0x80000000U)
+#define SIM_SOPT4_FTM3TRG1SRC_SHIFT (31U)
+/*! FTM3TRG1SRC - FlexTimer 3 Hardware Trigger 1 Source Select
+ * 0b0..Reserved
+ * 0b1..FTM2 channel match drives FTM3 hardware trigger 1
+ */
+#define SIM_SOPT4_FTM3TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK)
+/*! @} */
+
+/*! @name SOPT5 - System Options Register 5 */
+/*! @{ */
+#define SIM_SOPT5_UART0TXSRC_MASK (0x3U)
+#define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
+/*! UART0TXSRC - UART 0 transmit data source select
+ * 0b00..UART0_TX pin
+ * 0b01..UART0_TX pin modulated with FTM1 channel 0 output
+ * 0b10..UART0_TX pin modulated with FTM2 channel 0 output
+ * 0b11..Reserved
+ */
+#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK (0xCU)
+#define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
+/*! UART0RXSRC - UART 0 receive data source select
+ * 0b00..UART0_RX pin
+ * 0b01..CMP0
+ * 0b10..CMP1
+ * 0b11..Reserved
+ */
+#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_MASK (0x30U)
+#define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
+/*! UART1TXSRC - UART 1 transmit data source select
+ * 0b00..UART1_TX pin
+ * 0b01..UART1_TX pin modulated with FTM1 channel 0 output
+ * 0b10..UART1_TX pin modulated with FTM2 channel 0 output
+ * 0b11..Reserved
+ */
+#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK (0xC0U)
+#define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
+/*! UART1RXSRC - UART 1 receive data source select
+ * 0b00..UART1_RX pin
+ * 0b01..CMP0
+ * 0b10..CMP1
+ * 0b11..Reserved
+ */
+#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
+#define SIM_SOPT5_LPUART0TXSRC_MASK (0x30000U)
+#define SIM_SOPT5_LPUART0TXSRC_SHIFT (16U)
+/*! LPUART0TXSRC - LPUART0 transmit data source select
+ * 0b00..LPUART0_TX pin
+ * 0b01..LPUART0_TX pin modulated with TPM1 channel 0 output
+ * 0b10..LPUART0_TX pin modulated with TPM2 channel 0 output
+ * 0b11..Reserved
+ */
+#define SIM_SOPT5_LPUART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK)
+#define SIM_SOPT5_LPUART0RXSRC_MASK (0xC0000U)
+#define SIM_SOPT5_LPUART0RXSRC_SHIFT (18U)
+/*! LPUART0RXSRC - LPUART0 receive data source select
+ * 0b00..LPUART0_RX pin
+ * 0b01..CMP0 output
+ * 0b10..CMP1 output
+ * 0b11..Reserved
+ */
+#define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)
+/*! @} */
+
+/*! @name SOPT7 - System Options Register 7 */
+/*! @{ */
+#define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
+/*! ADC0TRGSEL - ADC0 trigger select
+ * 0b0000..PDB external trigger pin input (PDB0_EXTRG)
+ * 0b0001..High speed comparator 0 output
+ * 0b0010..High speed comparator 1 output
+ * 0b0011..High speed comparator 2 output
+ * 0b0100..PIT trigger 0
+ * 0b0101..PIT trigger 1
+ * 0b0110..PIT trigger 2
+ * 0b0111..PIT trigger 3
+ * 0b1000..FTM0 trigger
+ * 0b1001..FTM1 trigger
+ * 0b1010..FTM2 trigger
+ * 0b1011..FTM3 trigger
+ * 0b1100..RTC alarm
+ * 0b1101..RTC seconds
+ * 0b1110..Low-power timer (LPTMR) trigger
+ * 0b1111..TPM1 channel 0 (A pretrigger) and channel 1 (B pretrigger)
+ */
+#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
+/*! ADC0PRETRGSEL - ADC0 pretrigger select
+ * 0b0..Pre-trigger A
+ * 0b1..Pre-trigger B
+ */
+#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
+/*! ADC0ALTTRGEN - ADC0 alternate trigger enable
+ * 0b0..PDB trigger selected for ADC0.
+ * 0b1..Alternate trigger selected for ADC0.
+ */
+#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
+#define SIM_SOPT7_ADC1TRGSEL_MASK (0xF00U)
+#define SIM_SOPT7_ADC1TRGSEL_SHIFT (8U)
+/*! ADC1TRGSEL - ADC1 trigger select
+ * 0b0000..PDB external trigger pin input (PDB0_EXTRG)
+ * 0b0001..High speed comparator 0 output
+ * 0b0010..High speed comparator 1 output
+ * 0b0011..High speed comparator 2 output
+ * 0b0100..PIT trigger 0
+ * 0b0101..PIT trigger 1
+ * 0b0110..PIT trigger 2
+ * 0b0111..PIT trigger 3
+ * 0b1000..FTM0 trigger
+ * 0b1001..FTM1 trigger
+ * 0b1010..FTM2 trigger
+ * 0b1011..FTM3 trigger
+ * 0b1100..RTC alarm
+ * 0b1101..RTC seconds
+ * 0b1110..Low-power timer (LPTMR) trigger
+ * 0b1111..TPM2 channel 0 (A pretrigger) and channel 1 (B pretrigger)
+ */
+#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
+#define SIM_SOPT7_ADC1PRETRGSEL_MASK (0x1000U)
+#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT (12U)
+/*! ADC1PRETRGSEL - ADC1 pre-trigger select
+ * 0b0..Pre-trigger A selected for ADC1.
+ * 0b1..Pre-trigger B selected for ADC1.
+ */
+#define SIM_SOPT7_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC1ALTTRGEN_MASK (0x8000U)
+#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT (15U)
+/*! ADC1ALTTRGEN - ADC1 alternate trigger enable
+ * 0b0..PDB trigger selected for ADC1
+ * 0b1..Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.
+ */
+#define SIM_SOPT7_ADC1ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)
+/*! @} */
+
+/*! @name SOPT8 - System Options Register 8 */
+/*! @{ */
+#define SIM_SOPT8_FTM0SYNCBIT_MASK (0x1U)
+#define SIM_SOPT8_FTM0SYNCBIT_SHIFT (0U)
+/*! FTM0SYNCBIT - FTM0 Hardware Trigger 0 Software Synchronization
+ * 0b0..No effect
+ * 0b1..Write 1 to assert the TRIG0 input to FTM0, software must clear this bit to allow other trigger sources to assert.
+ */
+#define SIM_SOPT8_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK)
+#define SIM_SOPT8_FTM1SYNCBIT_MASK (0x2U)
+#define SIM_SOPT8_FTM1SYNCBIT_SHIFT (1U)
+/*! FTM1SYNCBIT - FTM1 Hardware Trigger 0 Software Synchronization
+ * 0b0..No effect.
+ * 0b1..Write 1 to assert the TRIG0 input to FTM1, software must clear this bit to allow other trigger sources to assert.
+ */
+#define SIM_SOPT8_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK)
+#define SIM_SOPT8_FTM2SYNCBIT_MASK (0x4U)
+#define SIM_SOPT8_FTM2SYNCBIT_SHIFT (2U)
+/*! FTM2SYNCBIT - FTM2 Hardware Trigger 0 Software Synchronization
+ * 0b0..No effect.
+ * 0b1..Write 1 to assert the TRIG0 input to FTM2, software must clear this bit to allow other trigger sources to assert.
+ */
+#define SIM_SOPT8_FTM2SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK)
+#define SIM_SOPT8_FTM3SYNCBIT_MASK (0x8U)
+#define SIM_SOPT8_FTM3SYNCBIT_SHIFT (3U)
+/*! FTM3SYNCBIT - FTM3 Hardware Trigger 0 Software Synchronization
+ * 0b0..No effect.
+ * 0b1..Write 1 to assert the TRIG0 input to FTM3, software must clear this bit to allow other trigger sources to assert.
+ */
+#define SIM_SOPT8_FTM3SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3SYNCBIT_SHIFT)) & SIM_SOPT8_FTM3SYNCBIT_MASK)
+#define SIM_SOPT8_FTM0OCH0SRC_MASK (0x10000U)
+#define SIM_SOPT8_FTM0OCH0SRC_SHIFT (16U)
+/*! FTM0OCH0SRC - FTM0 channel 0 output source
+ * 0b0..FTM0_CH0 pin is output of FTM0 channel 0 output
+ * 0b1..FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by FTM1 channel 1 output
+ */
+#define SIM_SOPT8_FTM0OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK)
+#define SIM_SOPT8_FTM0OCH1SRC_MASK (0x20000U)
+#define SIM_SOPT8_FTM0OCH1SRC_SHIFT (17U)
+/*! FTM0OCH1SRC - FTM0 channel 1 output source
+ * 0b0..FTM0_CH1 pin is output of FTM0 channel 1 output
+ * 0b1..FTM0_CH1 pin is output of FTM0 channel 1 output, modulated by FTM1 channel 1 output
+ */
+#define SIM_SOPT8_FTM0OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK)
+#define SIM_SOPT8_FTM0OCH2SRC_MASK (0x40000U)
+#define SIM_SOPT8_FTM0OCH2SRC_SHIFT (18U)
+/*! FTM0OCH2SRC - FTM0 channel 2 output source
+ * 0b0..FTM0_CH2 pin is output of FTM0 channel 2 output
+ * 0b1..FTM0_CH2 pin is output of FTM0 channel 2 output, modulated by FTM1 channel 1 output
+ */
+#define SIM_SOPT8_FTM0OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK)
+#define SIM_SOPT8_FTM0OCH3SRC_MASK (0x80000U)
+#define SIM_SOPT8_FTM0OCH3SRC_SHIFT (19U)
+/*! FTM0OCH3SRC - FTM0 channel 3 output source
+ * 0b0..FTM0_CH3 pin is output of FTM0 channel 3 output
+ * 0b1..FTM0_CH3 pin is output of FTM0 channel 3 output, modulated by FTM1 channel 1 output
+ */
+#define SIM_SOPT8_FTM0OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK)
+#define SIM_SOPT8_FTM0OCH4SRC_MASK (0x100000U)
+#define SIM_SOPT8_FTM0OCH4SRC_SHIFT (20U)
+/*! FTM0OCH4SRC - FTM0 channel 4 output source
+ * 0b0..FTM0_CH4 pin is output of FTM0 channel 4 output
+ * 0b1..FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by FTM1 channel 1 output
+ */
+#define SIM_SOPT8_FTM0OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK)
+#define SIM_SOPT8_FTM0OCH5SRC_MASK (0x200000U)
+#define SIM_SOPT8_FTM0OCH5SRC_SHIFT (21U)
+/*! FTM0OCH5SRC - FTM0 channel 5 output source
+ * 0b0..FTM0_CH5 pin is output of FTM0 channel 5 output
+ * 0b1..FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by FTM1 channel 1 output
+ */
+#define SIM_SOPT8_FTM0OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK)
+#define SIM_SOPT8_FTM0OCH6SRC_MASK (0x400000U)
+#define SIM_SOPT8_FTM0OCH6SRC_SHIFT (22U)
+/*! FTM0OCH6SRC - FTM0 channel 6 output source
+ * 0b0..FTM0_CH6 pin is output of FTM0 channel 6 output
+ * 0b1..FTM0_CH6 pin is output of FTM0 channel 6 output, modulated by FTM1 channel 1 output
+ */
+#define SIM_SOPT8_FTM0OCH6SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH6SRC_SHIFT)) & SIM_SOPT8_FTM0OCH6SRC_MASK)
+#define SIM_SOPT8_FTM0OCH7SRC_MASK (0x800000U)
+#define SIM_SOPT8_FTM0OCH7SRC_SHIFT (23U)
+/*! FTM0OCH7SRC - FTM0 channel 7 output source
+ * 0b0..FTM0_CH7 pin is output of FTM0 channel 7 output
+ * 0b1..FTM0_CH7 pin is output of FTM0 channel 7 output, modulated by FTM1 channel 1 output
+ */
+#define SIM_SOPT8_FTM0OCH7SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH7SRC_SHIFT)) & SIM_SOPT8_FTM0OCH7SRC_MASK)
+#define SIM_SOPT8_FTM3OCH0SRC_MASK (0x1000000U)
+#define SIM_SOPT8_FTM3OCH0SRC_SHIFT (24U)
+/*! FTM3OCH0SRC - FTM3 channel 0 output source
+ * 0b0..FTM3_CH0 pin is output of FTM3 channel 0 output
+ * 0b1..FTM3_CH0 pin is output of FTM3 channel 0 output modulated by FTM2 channel 1 output.
+ */
+#define SIM_SOPT8_FTM3OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH0SRC_SHIFT)) & SIM_SOPT8_FTM3OCH0SRC_MASK)
+#define SIM_SOPT8_FTM3OCH1SRC_MASK (0x2000000U)
+#define SIM_SOPT8_FTM3OCH1SRC_SHIFT (25U)
+/*! FTM3OCH1SRC - FTM3 channel 1 output source
+ * 0b0..FTM3_CH1 pin is output of FTM3 channel 1 output
+ * 0b1..FTM3_CH1 pin is output of FTM3 channel 1 output modulated by FTM2 channel 1 output.
+ */
+#define SIM_SOPT8_FTM3OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH1SRC_SHIFT)) & SIM_SOPT8_FTM3OCH1SRC_MASK)
+#define SIM_SOPT8_FTM3OCH2SRC_MASK (0x4000000U)
+#define SIM_SOPT8_FTM3OCH2SRC_SHIFT (26U)
+/*! FTM3OCH2SRC - FTM3 channel 2 output source
+ * 0b0..FTM3_CH2 pin is output of FTM3 channel 2 output
+ * 0b1..FTM3_CH2 pin is output of FTM3 channel 2 output modulated by FTM2 channel 1 output.
+ */
+#define SIM_SOPT8_FTM3OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH2SRC_SHIFT)) & SIM_SOPT8_FTM3OCH2SRC_MASK)
+#define SIM_SOPT8_FTM3OCH3SRC_MASK (0x8000000U)
+#define SIM_SOPT8_FTM3OCH3SRC_SHIFT (27U)
+/*! FTM3OCH3SRC - FTM3 channel 3 output source
+ * 0b0..FTM3_CH3 pin is output of FTM3 channel 3 output
+ * 0b1..FTM3_CH3 pin is output of FTM3 channel 3 output modulated by FTM2 channel 1 output.
+ */
+#define SIM_SOPT8_FTM3OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH3SRC_SHIFT)) & SIM_SOPT8_FTM3OCH3SRC_MASK)
+#define SIM_SOPT8_FTM3OCH4SRC_MASK (0x10000000U)
+#define SIM_SOPT8_FTM3OCH4SRC_SHIFT (28U)
+/*! FTM3OCH4SRC - FTM3 channel 4 output source
+ * 0b0..FTM3_CH4 pin is output of FTM3 channel 4 output
+ * 0b1..FTM3_CH4 pin is output of FTM3 channel 4 output modulated by FTM2 channel 1 output.
+ */
+#define SIM_SOPT8_FTM3OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH4SRC_SHIFT)) & SIM_SOPT8_FTM3OCH4SRC_MASK)
+#define SIM_SOPT8_FTM3OCH5SRC_MASK (0x20000000U)
+#define SIM_SOPT8_FTM3OCH5SRC_SHIFT (29U)
+/*! FTM3OCH5SRC - FTM3 channel 5 output source
+ * 0b0..FTM3_CH5 pin is output of FTM3 channel 5 output
+ * 0b1..FTM3_CH5 pin is output of FTM3 channel 5 output modulated by FTM2 channel 1 output.
+ */
+#define SIM_SOPT8_FTM3OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH5SRC_SHIFT)) & SIM_SOPT8_FTM3OCH5SRC_MASK)
+#define SIM_SOPT8_FTM3OCH6SRC_MASK (0x40000000U)
+#define SIM_SOPT8_FTM3OCH6SRC_SHIFT (30U)
+/*! FTM3OCH6SRC - FTM3 channel 6 output source
+ * 0b0..FTM3_CH6 pin is output of FTM3 channel 6 output
+ * 0b1..FTM3_CH6 pin is output of FTM3 channel 6 output modulated by FTM2 channel 1 output.
+ */
+#define SIM_SOPT8_FTM3OCH6SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH6SRC_SHIFT)) & SIM_SOPT8_FTM3OCH6SRC_MASK)
+#define SIM_SOPT8_FTM3OCH7SRC_MASK (0x80000000U)
+#define SIM_SOPT8_FTM3OCH7SRC_SHIFT (31U)
+/*! FTM3OCH7SRC - FTM3 channel 7 output source
+ * 0b0..FTM3_CH7 pin is output of FTM3 channel 7 output
+ * 0b1..FTM3_CH7 pin is output of FTM3 channel 7 output modulated by FTM2 channel 1 output.
+ */
+#define SIM_SOPT8_FTM3OCH7SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH7SRC_SHIFT)) & SIM_SOPT8_FTM3OCH7SRC_MASK)
+/*! @} */
+
+/*! @name SOPT9 - System Options Register 9 */
+/*! @{ */
+#define SIM_SOPT9_TPM1CH0SRC_MASK (0xC0000U)
+#define SIM_SOPT9_TPM1CH0SRC_SHIFT (18U)
+/*! TPM1CH0SRC - TPM1 channel 0 input capture source select
+ * 0b00..TPM1_CH0 signal
+ * 0b01..CMP0 output
+ * 0b10..CMP1 output
+ * 0b11..Reserved
+ */
+#define SIM_SOPT9_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CH0SRC_SHIFT)) & SIM_SOPT9_TPM1CH0SRC_MASK)
+#define SIM_SOPT9_TPM2CH0SRC_MASK (0x300000U)
+#define SIM_SOPT9_TPM2CH0SRC_SHIFT (20U)
+/*! TPM2CH0SRC - TPM2 channel 0 input capture source select
+ * 0b00..TPM2_CH0 signal
+ * 0b01..CMP0 output
+ * 0b10..CMP1 output
+ * 0b11..Reserved
+ */
+#define SIM_SOPT9_TPM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CH0SRC_SHIFT)) & SIM_SOPT9_TPM2CH0SRC_MASK)
+#define SIM_SOPT9_TPM1CLKSEL_MASK (0x2000000U)
+#define SIM_SOPT9_TPM1CLKSEL_SHIFT (25U)
+/*! TPM1CLKSEL - TPM1 External Clock Pin Select
+ * 0b0..TPM_CLKIN0 pin
+ * 0b1..TPM_CLKIN1 pin
+ */
+#define SIM_SOPT9_TPM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CLKSEL_SHIFT)) & SIM_SOPT9_TPM1CLKSEL_MASK)
+#define SIM_SOPT9_TPM2CLKSEL_MASK (0x4000000U)
+#define SIM_SOPT9_TPM2CLKSEL_SHIFT (26U)
+/*! TPM2CLKSEL - TPM2 External Clock Pin Select
+ * 0b0..TPM_CLKIN0 pin
+ * 0b1..TPM_CLKIN1 pin
+ */
+#define SIM_SOPT9_TPM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CLKSEL_SHIFT)) & SIM_SOPT9_TPM2CLKSEL_MASK)
+/*! @} */
+
+/*! @name SDID - System Device Identification Register */
+/*! @{ */
+#define SIM_SDID_PINID_MASK (0xFU)
+#define SIM_SDID_PINID_SHIFT (0U)
+/*! PINID - Pincount identification
+ * 0b0000..Reserved
+ * 0b0001..Reserved
+ * 0b0010..32-pin
+ * 0b0011..Reserved
+ * 0b0100..48-pin
+ * 0b0101..64-pin
+ * 0b0110..80-pin
+ * 0b0111..81-pin or 121-pin
+ * 0b1000..100-pin
+ * 0b1001..121-pin
+ * 0b1010..144-pin
+ * 0b1011..Custom pinout (WLCSP)
+ * 0b1100..169-pin
+ * 0b1101..Reserved
+ * 0b1110..256-pin
+ * 0b1111..Reserved
+ */
+#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
+#define SIM_SDID_FAMID_MASK (0x70U)
+#define SIM_SDID_FAMID_SHIFT (4U)
+/*! FAMID - Kinetis family identification
+ * 0b000..K1x Family (without tamper)
+ * 0b001..K2x Family (without tamper)
+ * 0b010..K3x Family or K1x/K6x Family (with tamper)
+ * 0b011..K4x Family or K2x Family (with tamper)
+ * 0b100..K6x Family (without tamper)
+ * 0b101..K7x Family
+ * 0b110..Reserved
+ * 0b111..Reserved
+ */
+#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
+#define SIM_SDID_DIEID_MASK (0xF80U)
+#define SIM_SDID_DIEID_SHIFT (7U)
+#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK (0xF000U)
+#define SIM_SDID_REVID_SHIFT (12U)
+#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
+#define SIM_SDID_SERIESID_MASK (0xF00000U)
+#define SIM_SDID_SERIESID_SHIFT (20U)
+/*! SERIESID - Kinetis Series ID
+ * 0b0000..Kinetis K series
+ * 0b0001..Kinetis L series
+ * 0b0101..Kinetis W series
+ * 0b0110..Kinetis V series
+ */
+#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK (0xF000000U)
+#define SIM_SDID_SUBFAMID_SHIFT (24U)
+/*! SUBFAMID - Kinetis Sub-Family ID
+ * 0b0000..Kx0 Subfamily
+ * 0b0001..Kx1 Subfamily (tamper detect)
+ * 0b0010..Kx2 Subfamily
+ * 0b0011..Kx3 Subfamily (tamper detect)
+ * 0b0100..Kx4 Subfamily
+ * 0b0101..Kx5 Subfamily (tamper detect)
+ * 0b0110..Kx6 Subfamily
+ */
+#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMILYID_MASK (0xF0000000U)
+#define SIM_SDID_FAMILYID_SHIFT (28U)
+/*! FAMILYID - Kinetis Family ID
+ * 0b0000..K0x Family
+ * 0b0001..K1x Family
+ * 0b0010..K2x Family
+ * 0b0011..K3x Family
+ * 0b0100..K4x Family
+ * 0b0110..K6x Family
+ * 0b0111..K7x Family
+ * 0b1000..K8x Family
+ */
+#define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
+/*! @} */
+
+/*! @name SCGC1 - System Clock Gating Control Register 1 */
+/*! @{ */
+#define SIM_SCGC1_I2C2_MASK (0x40U)
+#define SIM_SCGC1_I2C2_SHIFT (6U)
+/*! I2C2 - I2C2 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC1_I2C2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK)
+#define SIM_SCGC1_I2C3_MASK (0x80U)
+#define SIM_SCGC1_I2C3_SHIFT (7U)
+/*! I2C3 - I2C3 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC1_I2C3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C3_SHIFT)) & SIM_SCGC1_I2C3_MASK)
+#define SIM_SCGC1_UART4_MASK (0x400U)
+#define SIM_SCGC1_UART4_SHIFT (10U)
+/*! UART4 - UART4 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC1_UART4(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)
+/*! @} */
+
+/*! @name SCGC2 - System Clock Gating Control Register 2 */
+/*! @{ */
+#define SIM_SCGC2_LPUART0_MASK (0x10U)
+#define SIM_SCGC2_LPUART0_SHIFT (4U)
+/*! LPUART0 - LPUART0 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC2_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART0_SHIFT)) & SIM_SCGC2_LPUART0_MASK)
+#define SIM_SCGC2_TPM1_MASK (0x200U)
+#define SIM_SCGC2_TPM1_SHIFT (9U)
+/*! TPM1 - TPM1 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC2_TPM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM1_SHIFT)) & SIM_SCGC2_TPM1_MASK)
+#define SIM_SCGC2_TPM2_MASK (0x400U)
+#define SIM_SCGC2_TPM2_SHIFT (10U)
+/*! TPM2 - TPM2 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC2_TPM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM2_SHIFT)) & SIM_SCGC2_TPM2_MASK)
+#define SIM_SCGC2_DAC0_MASK (0x1000U)
+#define SIM_SCGC2_DAC0_SHIFT (12U)
+/*! DAC0 - DAC0 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC2_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK)
+#define SIM_SCGC2_DAC1_MASK (0x2000U)
+#define SIM_SCGC2_DAC1_SHIFT (13U)
+/*! DAC1 - DAC1 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC2_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK)
+/*! @} */
+
+/*! @name SCGC3 - System Clock Gating Control Register 3 */
+/*! @{ */
+#define SIM_SCGC3_RNGA_MASK (0x1U)
+#define SIM_SCGC3_RNGA_SHIFT (0U)
+/*! RNGA - RNGA Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC3_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK)
+#define SIM_SCGC3_USBHS_MASK (0x2U)
+#define SIM_SCGC3_USBHS_SHIFT (1U)
+/*! USBHS - USBHS Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC3_USBHS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHS_SHIFT)) & SIM_SCGC3_USBHS_MASK)
+#define SIM_SCGC3_USBHSPHY_MASK (0x4U)
+#define SIM_SCGC3_USBHSPHY_SHIFT (2U)
+/*! USBHSPHY - USBHS PHY Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC3_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSPHY_SHIFT)) & SIM_SCGC3_USBHSPHY_MASK)
+#define SIM_SCGC3_USBHSDCD_MASK (0x8U)
+#define SIM_SCGC3_USBHSDCD_SHIFT (3U)
+/*! USBHSDCD - USBHS DCD Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC3_USBHSDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSDCD_SHIFT)) & SIM_SCGC3_USBHSDCD_MASK)
+#define SIM_SCGC3_FLEXCAN1_MASK (0x10U)
+#define SIM_SCGC3_FLEXCAN1_SHIFT (4U)
+/*! FLEXCAN1 - FlexCAN1 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC3_FLEXCAN1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FLEXCAN1_SHIFT)) & SIM_SCGC3_FLEXCAN1_MASK)
+#define SIM_SCGC3_SPI2_MASK (0x1000U)
+#define SIM_SCGC3_SPI2_SHIFT (12U)
+/*! SPI2 - SPI2 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC3_SPI2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)
+#define SIM_SCGC3_SDHC_MASK (0x20000U)
+#define SIM_SCGC3_SDHC_SHIFT (17U)
+/*! SDHC - SDHC Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC3_SDHC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK)
+#define SIM_SCGC3_FTM2_MASK (0x1000000U)
+#define SIM_SCGC3_FTM2_SHIFT (24U)
+/*! FTM2 - FTM2 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC3_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK)
+#define SIM_SCGC3_FTM3_MASK (0x2000000U)
+#define SIM_SCGC3_FTM3_SHIFT (25U)
+/*! FTM3 - FTM3 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC3_FTM3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK)
+#define SIM_SCGC3_ADC1_MASK (0x8000000U)
+#define SIM_SCGC3_ADC1_SHIFT (27U)
+/*! ADC1 - ADC1 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC3_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK)
+/*! @} */
+
+/*! @name SCGC4 - System Clock Gating Control Register 4 */
+/*! @{ */
+#define SIM_SCGC4_EWM_MASK (0x2U)
+#define SIM_SCGC4_EWM_SHIFT (1U)
+/*! EWM - EWM Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
+#define SIM_SCGC4_CMT_MASK (0x4U)
+#define SIM_SCGC4_CMT_SHIFT (2U)
+/*! CMT - CMT Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
+#define SIM_SCGC4_I2C0_MASK (0x40U)
+#define SIM_SCGC4_I2C0_SHIFT (6U)
+/*! I2C0 - I2C0 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
+#define SIM_SCGC4_I2C1_MASK (0x80U)
+#define SIM_SCGC4_I2C1_SHIFT (7U)
+/*! I2C1 - I2C1 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
+#define SIM_SCGC4_UART0_MASK (0x400U)
+#define SIM_SCGC4_UART0_SHIFT (10U)
+/*! UART0 - UART0 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
+#define SIM_SCGC4_UART1_MASK (0x800U)
+#define SIM_SCGC4_UART1_SHIFT (11U)
+/*! UART1 - UART1 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
+#define SIM_SCGC4_UART2_MASK (0x1000U)
+#define SIM_SCGC4_UART2_SHIFT (12U)
+/*! UART2 - UART2 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
+#define SIM_SCGC4_UART3_MASK (0x2000U)
+#define SIM_SCGC4_UART3_SHIFT (13U)
+/*! UART3 - UART3 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC4_UART3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)
+#define SIM_SCGC4_USBOTG_MASK (0x40000U)
+#define SIM_SCGC4_USBOTG_SHIFT (18U)
+/*! USBOTG - USB Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
+#define SIM_SCGC4_CMP_MASK (0x80000U)
+#define SIM_SCGC4_CMP_SHIFT (19U)
+/*! CMP - Comparator Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
+#define SIM_SCGC4_VREF_MASK (0x100000U)
+#define SIM_SCGC4_VREF_SHIFT (20U)
+/*! VREF - VREF Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
+/*! @} */
+
+/*! @name SCGC5 - System Clock Gating Control Register 5 */
+/*! @{ */
+#define SIM_SCGC5_LPTMR_MASK (0x1U)
+#define SIM_SCGC5_LPTMR_SHIFT (0U)
+/*! LPTMR - Low Power Timer Access Control
+ * 0b0..Access disabled
+ * 0b1..Access enabled
+ */
+#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
+#define SIM_SCGC5_TSI_MASK (0x20U)
+#define SIM_SCGC5_TSI_SHIFT (5U)
+/*! TSI - TSI Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC5_TSI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
+#define SIM_SCGC5_PORTA_MASK (0x200U)
+#define SIM_SCGC5_PORTA_SHIFT (9U)
+/*! PORTA - Port A Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
+#define SIM_SCGC5_PORTB_MASK (0x400U)
+#define SIM_SCGC5_PORTB_SHIFT (10U)
+/*! PORTB - Port B Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
+#define SIM_SCGC5_PORTC_MASK (0x800U)
+#define SIM_SCGC5_PORTC_SHIFT (11U)
+/*! PORTC - Port C Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
+#define SIM_SCGC5_PORTD_MASK (0x1000U)
+#define SIM_SCGC5_PORTD_SHIFT (12U)
+/*! PORTD - Port D Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
+#define SIM_SCGC5_PORTE_MASK (0x2000U)
+#define SIM_SCGC5_PORTE_SHIFT (13U)
+/*! PORTE - Port E Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
+/*! @} */
+
+/*! @name SCGC6 - System Clock Gating Control Register 6 */
+/*! @{ */
+#define SIM_SCGC6_FTF_MASK (0x1U)
+#define SIM_SCGC6_FTF_SHIFT (0U)
+/*! FTF - Flash Memory Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
+#define SIM_SCGC6_DMAMUX_MASK (0x2U)
+#define SIM_SCGC6_DMAMUX_SHIFT (1U)
+/*! DMAMUX - DMA Mux Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
+#define SIM_SCGC6_FLEXCAN0_MASK (0x10U)
+#define SIM_SCGC6_FLEXCAN0_SHIFT (4U)
+/*! FLEXCAN0 - FlexCAN0 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC6_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)
+#define SIM_SCGC6_RNGA_MASK (0x200U)
+#define SIM_SCGC6_RNGA_SHIFT (9U)
+#define SIM_SCGC6_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RNGA_SHIFT)) & SIM_SCGC6_RNGA_MASK)
+#define SIM_SCGC6_SPI0_MASK (0x1000U)
+#define SIM_SCGC6_SPI0_SHIFT (12U)
+/*! SPI0 - SPI0 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
+#define SIM_SCGC6_SPI1_MASK (0x2000U)
+#define SIM_SCGC6_SPI1_SHIFT (13U)
+/*! SPI1 - SPI1 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
+#define SIM_SCGC6_I2S_MASK (0x8000U)
+#define SIM_SCGC6_I2S_SHIFT (15U)
+/*! I2S - I2S Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
+#define SIM_SCGC6_CRC_MASK (0x40000U)
+#define SIM_SCGC6_CRC_SHIFT (18U)
+/*! CRC - CRC Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
+#define SIM_SCGC6_USBDCD_MASK (0x200000U)
+#define SIM_SCGC6_USBDCD_SHIFT (21U)
+/*! USBDCD - USB DCD Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC6_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)
+#define SIM_SCGC6_PDB_MASK (0x400000U)
+#define SIM_SCGC6_PDB_SHIFT (22U)
+/*! PDB - PDB Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
+#define SIM_SCGC6_PIT_MASK (0x800000U)
+#define SIM_SCGC6_PIT_SHIFT (23U)
+/*! PIT - PIT Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
+#define SIM_SCGC6_FTM0_MASK (0x1000000U)
+#define SIM_SCGC6_FTM0_SHIFT (24U)
+/*! FTM0 - FTM0 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
+#define SIM_SCGC6_FTM1_MASK (0x2000000U)
+#define SIM_SCGC6_FTM1_SHIFT (25U)
+/*! FTM1 - FTM1 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
+#define SIM_SCGC6_FTM2_MASK (0x4000000U)
+#define SIM_SCGC6_FTM2_SHIFT (26U)
+/*! FTM2 - FTM2 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
+#define SIM_SCGC6_ADC0_MASK (0x8000000U)
+#define SIM_SCGC6_ADC0_SHIFT (27U)
+/*! ADC0 - ADC0 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
+#define SIM_SCGC6_RTC_MASK (0x20000000U)
+#define SIM_SCGC6_RTC_SHIFT (29U)
+/*! RTC - RTC Access Control
+ * 0b0..Access and interrupts disabled
+ * 0b1..Access and interrupts enabled
+ */
+#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
+#define SIM_SCGC6_DAC0_MASK (0x80000000U)
+#define SIM_SCGC6_DAC0_SHIFT (31U)
+/*! DAC0 - DAC0 Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
+/*! @} */
+
+/*! @name SCGC7 - System Clock Gating Control Register 7 */
+/*! @{ */
+#define SIM_SCGC7_FLEXBUS_MASK (0x1U)
+#define SIM_SCGC7_FLEXBUS_SHIFT (0U)
+/*! FLEXBUS - FlexBus Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC7_FLEXBUS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)
+#define SIM_SCGC7_DMA_MASK (0x2U)
+#define SIM_SCGC7_DMA_SHIFT (1U)
+/*! DMA - DMA Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
+#define SIM_SCGC7_MPU_MASK (0x4U)
+#define SIM_SCGC7_MPU_SHIFT (2U)
+/*! MPU - MPU Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC7_MPU(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)
+#define SIM_SCGC7_SDRAMC_MASK (0x8U)
+#define SIM_SCGC7_SDRAMC_SHIFT (3U)
+/*! SDRAMC - SDRAMC Clock Gate Control
+ * 0b0..Clock disabled
+ * 0b1..Clock enabled
+ */
+#define SIM_SCGC7_SDRAMC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_SDRAMC_SHIFT)) & SIM_SCGC7_SDRAMC_MASK)
+/*! @} */
+
+/*! @name CLKDIV1 - System Clock Divider Register 1 */
+/*! @{ */
+#define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U)
+#define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
+/*! OUTDIV4 - Clock 4 output divider value
+ * 0b0000..Divide-by-1.
+ * 0b0001..Divide-by-2.
+ * 0b0010..Divide-by-3.
+ * 0b0011..Divide-by-4.
+ * 0b0100..Divide-by-5.
+ * 0b0101..Divide-by-6.
+ * 0b0110..Divide-by-7.
+ * 0b0111..Divide-by-8.
+ * 0b1000..Divide-by-9.
+ * 0b1001..Divide-by-10.
+ * 0b1010..Divide-by-11.
+ * 0b1011..Divide-by-12.
+ * 0b1100..Divide-by-13.
+ * 0b1101..Divide-by-14.
+ * 0b1110..Divide-by-15.
+ * 0b1111..Divide-by-16.
+ */
+#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV3_MASK (0xF00000U)
+#define SIM_CLKDIV1_OUTDIV3_SHIFT (20U)
+/*! OUTDIV3 - Clock 3 output divider value
+ * 0b0000..Divide-by-1.
+ * 0b0001..Divide-by-2.
+ * 0b0010..Divide-by-3.
+ * 0b0011..Divide-by-4.
+ * 0b0100..Divide-by-5.
+ * 0b0101..Divide-by-6.
+ * 0b0110..Divide-by-7.
+ * 0b0111..Divide-by-8.
+ * 0b1000..Divide-by-9.
+ * 0b1001..Divide-by-10.
+ * 0b1010..Divide-by-11.
+ * 0b1011..Divide-by-12.
+ * 0b1100..Divide-by-13.
+ * 0b1101..Divide-by-14.
+ * 0b1110..Divide-by-15.
+ * 0b1111..Divide-by-16.
+ */
+#define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)
+#define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U)
+#define SIM_CLKDIV1_OUTDIV2_SHIFT (24U)
+/*! OUTDIV2 - Clock 2 output divider value
+ * 0b0000..Divide-by-1.
+ * 0b0001..Divide-by-2.
+ * 0b0010..Divide-by-3.
+ * 0b0011..Divide-by-4.
+ * 0b0100..Divide-by-5.
+ * 0b0101..Divide-by-6.
+ * 0b0110..Divide-by-7.
+ * 0b0111..Divide-by-8.
+ * 0b1000..Divide-by-9.
+ * 0b1001..Divide-by-10.
+ * 0b1010..Divide-by-11.
+ * 0b1011..Divide-by-12.
+ * 0b1100..Divide-by-13.
+ * 0b1101..Divide-by-14.
+ * 0b1110..Divide-by-15.
+ * 0b1111..Divide-by-16.
+ */
+#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
+#define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
+/*! OUTDIV1 - Clock 1 output divider value
+ * 0b0000..Divide-by-1.
+ * 0b0001..Divide-by-2.
+ * 0b0010..Divide-by-3.
+ * 0b0011..Divide-by-4.
+ * 0b0100..Divide-by-5.
+ * 0b0101..Divide-by-6.
+ * 0b0110..Divide-by-7.
+ * 0b0111..Divide-by-8.
+ * 0b1000..Divide-by-9.
+ * 0b1001..Divide-by-10.
+ * 0b1010..Divide-by-11.
+ * 0b1011..Divide-by-12.
+ * 0b1100..Divide-by-13.
+ * 0b1101..Divide-by-14.
+ * 0b1110..Divide-by-15.
+ * 0b1111..Divide-by-16.
+ */
+#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
+/*! @} */
+
+/*! @name CLKDIV2 - System Clock Divider Register 2 */
+/*! @{ */
+#define SIM_CLKDIV2_USBFRAC_MASK (0x1U)
+#define SIM_CLKDIV2_USBFRAC_SHIFT (0U)
+#define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
+#define SIM_CLKDIV2_USBDIV_MASK (0xEU)
+#define SIM_CLKDIV2_USBDIV_SHIFT (1U)
+#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
+/*! @} */
+
+/*! @name FCFG1 - Flash Configuration Register 1 */
+/*! @{ */
+#define SIM_FCFG1_FLASHDIS_MASK (0x1U)
+#define SIM_FCFG1_FLASHDIS_SHIFT (0U)
+/*! FLASHDIS - Flash Disable
+ * 0b0..Flash is enabled
+ * 0b1..Flash is disabled
+ */
+#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
+#define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
+#define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
+/*! FLASHDOZE - Flash Doze
+ * 0b0..Flash remains enabled during Wait mode
+ * 0b1..Flash is disabled for the duration of Wait mode
+ */
+#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
+#define SIM_FCFG1_DEPART_MASK (0xF00U)
+#define SIM_FCFG1_DEPART_SHIFT (8U)
+#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK)
+#define SIM_FCFG1_EESIZE_MASK (0xF0000U)
+#define SIM_FCFG1_EESIZE_SHIFT (16U)
+/*! EESIZE - EEPROM size
+ * 0b0000..16 KB
+ * 0b0001..8 KB
+ * 0b0010..4 KB
+ * 0b0011..2 KB
+ * 0b0100..1 KB
+ * 0b0101..512 Bytes
+ * 0b0110..256 Bytes
+ * 0b0111..128 Bytes
+ * 0b1000..64 Bytes
+ * 0b1001..32 Bytes
+ * 0b1111..0 Bytes
+ */
+#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)
+#define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
+#define SIM_FCFG1_PFSIZE_SHIFT (24U)
+/*! PFSIZE - Program flash size
+ * 0b0011..32 KB of program flash memory
+ * 0b0101..64 KB of program flash memory
+ * 0b0111..128 KB of program flash memory
+ * 0b1001..256 KB of program flash memory
+ * 0b1011..512 KB of program flash memory
+ * 0b1101..1024 KB of program flash memory
+ * 0b1111..2048 KB of program flash memory
+ */
+#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
+#define SIM_FCFG1_NVMSIZE_MASK (0xF0000000U)
+#define SIM_FCFG1_NVMSIZE_SHIFT (28U)
+/*! NVMSIZE - FlexNVM size
+ * 0b0000..0 KB of FlexNVM
+ * 0b0011..32 KB of FlexNVM
+ * 0b0101..64 KB of FlexNVM
+ * 0b0111..128 KB of FlexNVM
+ * 0b1001..256 KB of FlexNVM
+ * 0b1011..512 KB of FlexNVM
+ * 0b1111..256 KB of FlexNVM
+ */
+#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)
+/*! @} */
+
+/*! @name FCFG2 - Flash Configuration Register 2 */
+/*! @{ */
+#define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
+#define SIM_FCFG2_MAXADDR1_SHIFT (16U)
+#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_PFLSH_MASK (0x800000U)
+#define SIM_FCFG2_PFLSH_SHIFT (23U)
+/*! PFLSH - Program flash only
+ * 0b0..Device supports FlexNVM
+ * 0b1..Program Flash only, device does not support FlexNVM
+ */
+#define SIM_FCFG2_PFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)
+#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
+#define SIM_FCFG2_MAXADDR0_SHIFT (24U)
+#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
+#define SIM_FCFG2_SWAPPFLSH_MASK (0x80000000U)
+#define SIM_FCFG2_SWAPPFLSH_SHIFT (31U)
+/*! SWAPPFLSH - Swap program flash
+ * 0b0..Swap is not active.
+ * 0b1..Swap is active.
+ */
+#define SIM_FCFG2_SWAPPFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_SWAPPFLSH_SHIFT)) & SIM_FCFG2_SWAPPFLSH_MASK)
+/*! @} */
+
+/*! @name UIDH - Unique Identification Register High */
+/*! @{ */
+#define SIM_UIDH_UID_MASK (0xFFFFFFFFU)
+#define SIM_UIDH_UID_SHIFT (0U)
+#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
+/*! @} */
+
+/*! @name UIDMH - Unique Identification Register Mid-High */
+/*! @{ */
+#define SIM_UIDMH_UID_MASK (0xFFFFFFFFU)
+#define SIM_UIDMH_UID_SHIFT (0U)
+#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
+/*! @} */
+
+/*! @name UIDML - Unique Identification Register Mid Low */
+/*! @{ */
+#define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
+#define SIM_UIDML_UID_SHIFT (0U)
+#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
+/*! @} */
+
+/*! @name UIDL - Unique Identification Register Low */
+/*! @{ */
+#define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
+#define SIM_UIDL_UID_SHIFT (0U)
+#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
+/*! @} */
+
+/*! @name CLKDIV3 - System Clock Divider Register 3 */
+/*! @{ */
+#define SIM_CLKDIV3_PLLFLLFRAC_MASK (0x1U)
+#define SIM_CLKDIV3_PLLFLLFRAC_SHIFT (0U)
+#define SIM_CLKDIV3_PLLFLLFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLFRAC_SHIFT)) & SIM_CLKDIV3_PLLFLLFRAC_MASK)
+#define SIM_CLKDIV3_PLLFLLDIV_MASK (0xEU)
+#define SIM_CLKDIV3_PLLFLLDIV_SHIFT (1U)
+#define SIM_CLKDIV3_PLLFLLDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLDIV_SHIFT)) & SIM_CLKDIV3_PLLFLLDIV_MASK)
+/*! @} */
+
+/*! @name CLKDIV4 - System Clock Divider Register 4 */
+/*! @{ */
+#define SIM_CLKDIV4_TRACEFRAC_MASK (0x1U)
+#define SIM_CLKDIV4_TRACEFRAC_SHIFT (0U)
+#define SIM_CLKDIV4_TRACEFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEFRAC_SHIFT)) & SIM_CLKDIV4_TRACEFRAC_MASK)
+#define SIM_CLKDIV4_TRACEDIV_MASK (0xEU)
+#define SIM_CLKDIV4_TRACEDIV_SHIFT (1U)
+#define SIM_CLKDIV4_TRACEDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEDIV_SHIFT)) & SIM_CLKDIV4_TRACEDIV_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM ((SIM_Type *)SIM_BASE)
+/** Array initializer of SIM peripheral base addresses */
+#define SIM_BASE_ADDRS { SIM_BASE }
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASE_PTRS { SIM }
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
+ __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
+ __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
+ __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/*! @name PMPROT - Power Mode Protection register */
+/*! @{ */
+#define SMC_PMPROT_AVLLS_MASK (0x2U)
+#define SMC_PMPROT_AVLLS_SHIFT (1U)
+/*! AVLLS - Allow Very-Low-Leakage Stop Mode
+ * 0b0..Any VLLSx mode is not allowed
+ * 0b1..Any VLLSx mode is allowed
+ */
+#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
+#define SMC_PMPROT_ALLS_MASK (0x8U)
+#define SMC_PMPROT_ALLS_SHIFT (3U)
+/*! ALLS - Allow Low-Leakage Stop Mode
+ * 0b0..Any LLSx mode is not allowed
+ * 0b1..Any LLSx mode is allowed
+ */
+#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
+#define SMC_PMPROT_AVLP_MASK (0x20U)
+#define SMC_PMPROT_AVLP_SHIFT (5U)
+/*! AVLP - Allow Very-Low-Power Modes
+ * 0b0..VLPR, VLPW, and VLPS are not allowed.
+ * 0b1..VLPR, VLPW, and VLPS are allowed.
+ */
+#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
+#define SMC_PMPROT_AHSRUN_MASK (0x80U)
+#define SMC_PMPROT_AHSRUN_SHIFT (7U)
+/*! AHSRUN - Allow High Speed Run mode
+ * 0b0..HSRUN is not allowed
+ * 0b1..HSRUN is allowed
+ */
+#define SMC_PMPROT_AHSRUN(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK)
+/*! @} */
+
+/*! @name PMCTRL - Power Mode Control register */
+/*! @{ */
+#define SMC_PMCTRL_STOPM_MASK (0x7U)
+#define SMC_PMCTRL_STOPM_SHIFT (0U)
+/*! STOPM - Stop Mode Control
+ * 0b000..Normal Stop (STOP)
+ * 0b001..Reserved
+ * 0b010..Very-Low-Power Stop (VLPS)
+ * 0b011..Low-Leakage Stop (LLSx)
+ * 0b100..Very-Low-Leakage Stop (VLLSx)
+ * 0b101..Reserved
+ * 0b110..Reseved
+ * 0b111..Reserved
+ */
+#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK (0x8U)
+#define SMC_PMCTRL_STOPA_SHIFT (3U)
+/*! STOPA - Stop Aborted
+ * 0b0..The previous stop mode entry was successsful.
+ * 0b1..The previous stop mode entry was aborted.
+ */
+#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
+#define SMC_PMCTRL_RUNM_MASK (0x60U)
+#define SMC_PMCTRL_RUNM_SHIFT (5U)
+/*! RUNM - Run Mode Control
+ * 0b00..Normal Run mode (RUN)
+ * 0b01..Reserved
+ * 0b10..Very-Low-Power Run mode (VLPR)
+ * 0b11..High Speed Run mode (HSRUN)
+ */
+#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
+/*! @} */
+
+/*! @name STOPCTRL - Stop Control Register */
+/*! @{ */
+#define SMC_STOPCTRL_LLSM_MASK (0x7U)
+#define SMC_STOPCTRL_LLSM_SHIFT (0U)
+/*! LLSM - LLS or VLLS Mode Control
+ * 0b000..VLLS0 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx
+ * 0b001..VLLS1 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx
+ * 0b010..VLLS2 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx
+ * 0b011..VLLS3 if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx
+ * 0b100..Reserved
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..Reserved
+ */
+#define SMC_STOPCTRL_LLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LLSM_SHIFT)) & SMC_STOPCTRL_LLSM_MASK)
+#define SMC_STOPCTRL_RAM2PO_MASK (0x10U)
+#define SMC_STOPCTRL_RAM2PO_SHIFT (4U)
+/*! RAM2PO - RAM2 Power Option
+ * 0b0..RAM2 not powered in LLS2/VLLS2
+ * 0b1..RAM2 powered in LLS2/VLLS2
+ */
+#define SMC_STOPCTRL_RAM2PO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_RAM2PO_SHIFT)) & SMC_STOPCTRL_RAM2PO_MASK)
+#define SMC_STOPCTRL_PORPO_MASK (0x20U)
+#define SMC_STOPCTRL_PORPO_SHIFT (5U)
+/*! PORPO - POR Power Option
+ * 0b0..POR detect circuit is enabled in VLLS0
+ * 0b1..POR detect circuit is disabled in VLLS0
+ */
+#define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
+#define SMC_STOPCTRL_PSTOPO_MASK (0xC0U)
+#define SMC_STOPCTRL_PSTOPO_SHIFT (6U)
+/*! PSTOPO - Partial Stop Option
+ * 0b00..STOP - Normal Stop mode
+ * 0b01..PSTOP1 - Partial Stop with both system and bus clocks disabled
+ * 0b10..PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
+ * 0b11..Reserved
+ */
+#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
+/*! @} */
+
+/*! @name PMSTAT - Power Mode Status register */
+/*! @{ */
+#define SMC_PMSTAT_PMSTAT_MASK (0xFFU)
+#define SMC_PMSTAT_PMSTAT_SHIFT (0U)
+#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC ((SMC_Type *)SMC_BASE)
+/** Array initializer of SMC peripheral base addresses */
+#define SMC_BASE_ADDRS { SMC_BASE }
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASE_PTRS { SMC }
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
+ union { /* offset: 0xC */
+ __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
+ __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
+ };
+ uint8_t RESERVED_1[24];
+ __IO uint32_t SR; /**< Status Register, offset: 0x2C */
+ __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
+ union { /* offset: 0x34 */
+ __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
+ __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
+ };
+ __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
+ __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
+ __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
+ __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
+ __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
+ uint8_t RESERVED_2[48];
+ __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
+ __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
+ __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
+ __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/*! @name MCR - Module Configuration Register */
+/*! @{ */
+#define SPI_MCR_HALT_MASK (0x1U)
+#define SPI_MCR_HALT_SHIFT (0U)
+/*! HALT - Halt
+ * 0b0..Start transfers.
+ * 0b1..Stop transfers.
+ */
+#define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
+#define SPI_MCR_SMPL_PT_MASK (0x300U)
+#define SPI_MCR_SMPL_PT_SHIFT (8U)
+/*! SMPL_PT - Sample Point
+ * 0b00..0 protocol clock cycles between SCK edge and SIN sample
+ * 0b01..1 protocol clock cycle between SCK edge and SIN sample
+ * 0b10..2 protocol clock cycles between SCK edge and SIN sample
+ * 0b11..Reserved
+ */
+#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
+#define SPI_MCR_CLR_RXF_MASK (0x400U)
+#define SPI_MCR_CLR_RXF_SHIFT (10U)
+/*! CLR_RXF - CLR_RXF
+ * 0b0..Do not clear the RX FIFO counter.
+ * 0b1..Clear the RX FIFO counter.
+ */
+#define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
+#define SPI_MCR_CLR_TXF_MASK (0x800U)
+#define SPI_MCR_CLR_TXF_SHIFT (11U)
+/*! CLR_TXF - Clear TX FIFO
+ * 0b0..Do not clear the TX FIFO counter.
+ * 0b1..Clear the TX FIFO counter.
+ */
+#define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
+#define SPI_MCR_DIS_RXF_MASK (0x1000U)
+#define SPI_MCR_DIS_RXF_SHIFT (12U)
+/*! DIS_RXF - Disable Receive FIFO
+ * 0b0..RX FIFO is enabled.
+ * 0b1..RX FIFO is disabled.
+ */
+#define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
+#define SPI_MCR_DIS_TXF_MASK (0x2000U)
+#define SPI_MCR_DIS_TXF_SHIFT (13U)
+/*! DIS_TXF - Disable Transmit FIFO
+ * 0b0..TX FIFO is enabled.
+ * 0b1..TX FIFO is disabled.
+ */
+#define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
+#define SPI_MCR_MDIS_MASK (0x4000U)
+#define SPI_MCR_MDIS_SHIFT (14U)
+/*! MDIS - Module Disable
+ * 0b0..Enables the module clocks.
+ * 0b1..Allows external logic to disable the module clocks.
+ */
+#define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
+#define SPI_MCR_DOZE_MASK (0x8000U)
+#define SPI_MCR_DOZE_SHIFT (15U)
+/*! DOZE - Doze Enable
+ * 0b0..Doze mode has no effect on the module.
+ * 0b1..Doze mode disables the module.
+ */
+#define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
+#define SPI_MCR_PCSIS_MASK (0x3F0000U)
+#define SPI_MCR_PCSIS_SHIFT (16U)
+/*! PCSIS - Peripheral Chip Select x Inactive State
+ * 0b000000..The inactive state of PCSx is low.
+ * 0b000001..The inactive state of PCSx is high.
+ */
+#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
+#define SPI_MCR_ROOE_MASK (0x1000000U)
+#define SPI_MCR_ROOE_SHIFT (24U)
+/*! ROOE - Receive FIFO Overflow Overwrite Enable
+ * 0b0..Incoming data is ignored.
+ * 0b1..Incoming data is shifted into the shift register.
+ */
+#define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
+#define SPI_MCR_PCSSE_MASK (0x2000000U)
+#define SPI_MCR_PCSSE_SHIFT (25U)
+/*! PCSSE - Peripheral Chip Select Strobe Enable
+ * 0b0..PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
+ * 0b1..PCS5/ PCSS is used as an active-low PCS Strobe signal.
+ */
+#define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
+#define SPI_MCR_MTFE_MASK (0x4000000U)
+#define SPI_MCR_MTFE_SHIFT (26U)
+/*! MTFE - Modified Transfer Format Enable
+ * 0b0..Modified SPI transfer format disabled.
+ * 0b1..Modified SPI transfer format enabled.
+ */
+#define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
+#define SPI_MCR_FRZ_MASK (0x8000000U)
+#define SPI_MCR_FRZ_SHIFT (27U)
+/*! FRZ - Freeze
+ * 0b0..Do not halt serial transfers in Debug mode.
+ * 0b1..Halt serial transfers in Debug mode.
+ */
+#define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
+#define SPI_MCR_DCONF_MASK (0x30000000U)
+#define SPI_MCR_DCONF_SHIFT (28U)
+/*! DCONF - SPI Configuration.
+ * 0b00..SPI
+ * 0b01..Reserved
+ * 0b10..Reserved
+ * 0b11..Reserved
+ */
+#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
+#define SPI_MCR_CONT_SCKE_MASK (0x40000000U)
+#define SPI_MCR_CONT_SCKE_SHIFT (30U)
+/*! CONT_SCKE - Continuous SCK Enable
+ * 0b0..Continuous SCK disabled.
+ * 0b1..Continuous SCK enabled.
+ */
+#define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
+#define SPI_MCR_MSTR_MASK (0x80000000U)
+#define SPI_MCR_MSTR_SHIFT (31U)
+/*! MSTR - Master/Slave Mode Select
+ * 0b0..Enables Slave mode
+ * 0b1..Enables Master mode
+ */
+#define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
+/*! @} */
+
+/*! @name TCR - Transfer Count Register */
+/*! @{ */
+#define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U)
+#define SPI_TCR_SPI_TCNT_SHIFT (16U)
+#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
+/*! @} */
+
+/*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */
+/*! @{ */
+#define SPI_CTAR_BR_MASK (0xFU)
+#define SPI_CTAR_BR_SHIFT (0U)
+#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
+#define SPI_CTAR_DT_MASK (0xF0U)
+#define SPI_CTAR_DT_SHIFT (4U)
+#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
+#define SPI_CTAR_ASC_MASK (0xF00U)
+#define SPI_CTAR_ASC_SHIFT (8U)
+#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
+#define SPI_CTAR_CSSCK_MASK (0xF000U)
+#define SPI_CTAR_CSSCK_SHIFT (12U)
+#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
+#define SPI_CTAR_PBR_MASK (0x30000U)
+#define SPI_CTAR_PBR_SHIFT (16U)
+/*! PBR - Baud Rate Prescaler
+ * 0b00..Baud Rate Prescaler value is 2.
+ * 0b01..Baud Rate Prescaler value is 3.
+ * 0b10..Baud Rate Prescaler value is 5.
+ * 0b11..Baud Rate Prescaler value is 7.
+ */
+#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
+#define SPI_CTAR_PDT_MASK (0xC0000U)
+#define SPI_CTAR_PDT_SHIFT (18U)
+/*! PDT - Delay after Transfer Prescaler
+ * 0b00..Delay after Transfer Prescaler value is 1.
+ * 0b01..Delay after Transfer Prescaler value is 3.
+ * 0b10..Delay after Transfer Prescaler value is 5.
+ * 0b11..Delay after Transfer Prescaler value is 7.
+ */
+#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
+#define SPI_CTAR_PASC_MASK (0x300000U)
+#define SPI_CTAR_PASC_SHIFT (20U)
+/*! PASC - After SCK Delay Prescaler
+ * 0b00..Delay after Transfer Prescaler value is 1.
+ * 0b01..Delay after Transfer Prescaler value is 3.
+ * 0b10..Delay after Transfer Prescaler value is 5.
+ * 0b11..Delay after Transfer Prescaler value is 7.
+ */
+#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
+#define SPI_CTAR_PCSSCK_MASK (0xC00000U)
+#define SPI_CTAR_PCSSCK_SHIFT (22U)
+/*! PCSSCK - PCS to SCK Delay Prescaler
+ * 0b00..PCS to SCK Prescaler value is 1.
+ * 0b01..PCS to SCK Prescaler value is 3.
+ * 0b10..PCS to SCK Prescaler value is 5.
+ * 0b11..PCS to SCK Prescaler value is 7.
+ */
+#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
+#define SPI_CTAR_LSBFE_MASK (0x1000000U)
+#define SPI_CTAR_LSBFE_SHIFT (24U)
+/*! LSBFE - LSB First
+ * 0b0..Data is transferred MSB first.
+ * 0b1..Data is transferred LSB first.
+ */
+#define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
+#define SPI_CTAR_CPHA_MASK (0x2000000U)
+#define SPI_CTAR_CPHA_SHIFT (25U)
+/*! CPHA - Clock Phase
+ * 0b0..Data is captured on the leading edge of SCK and changed on the following edge.
+ * 0b1..Data is changed on the leading edge of SCK and captured on the following edge.
+ */
+#define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
+#define SPI_CTAR_CPOL_MASK (0x4000000U)
+#define SPI_CTAR_CPOL_SHIFT (26U)
+/*! CPOL - Clock Polarity
+ * 0b0..The inactive state value of SCK is low.
+ * 0b1..The inactive state value of SCK is high.
+ */
+#define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
+#define SPI_CTAR_FMSZ_MASK (0x78000000U)
+#define SPI_CTAR_FMSZ_SHIFT (27U)
+#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
+#define SPI_CTAR_DBR_MASK (0x80000000U)
+#define SPI_CTAR_DBR_SHIFT (31U)
+/*! DBR - Double Baud Rate
+ * 0b0..The baud rate is computed normally with a 50/50 duty cycle.
+ * 0b1..The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.
+ */
+#define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
+/*! @} */
+
+/* The count of SPI_CTAR */
+#define SPI_CTAR_COUNT (2U)
+
+/*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */
+/*! @{ */
+#define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U)
+#define SPI_CTAR_SLAVE_CPHA_SHIFT (25U)
+/*! CPHA - Clock Phase
+ * 0b0..Data is captured on the leading edge of SCK and changed on the following edge.
+ * 0b1..Data is changed on the leading edge of SCK and captured on the following edge.
+ */
+#define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
+#define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U)
+#define SPI_CTAR_SLAVE_CPOL_SHIFT (26U)
+/*! CPOL - Clock Polarity
+ * 0b0..The inactive state value of SCK is low.
+ * 0b1..The inactive state value of SCK is high.
+ */
+#define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
+#define SPI_CTAR_SLAVE_FMSZ_MASK (0x78000000U)
+#define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U)
+#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
+/*! @} */
+
+/* The count of SPI_CTAR_SLAVE */
+#define SPI_CTAR_SLAVE_COUNT (1U)
+
+/*! @name SR - Status Register */
+/*! @{ */
+#define SPI_SR_POPNXTPTR_MASK (0xFU)
+#define SPI_SR_POPNXTPTR_SHIFT (0U)
+#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
+#define SPI_SR_RXCTR_MASK (0xF0U)
+#define SPI_SR_RXCTR_SHIFT (4U)
+#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
+#define SPI_SR_TXNXTPTR_MASK (0xF00U)
+#define SPI_SR_TXNXTPTR_SHIFT (8U)
+#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
+#define SPI_SR_TXCTR_MASK (0xF000U)
+#define SPI_SR_TXCTR_SHIFT (12U)
+#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
+#define SPI_SR_RFDF_MASK (0x20000U)
+#define SPI_SR_RFDF_SHIFT (17U)
+/*! RFDF - Receive FIFO Drain Flag
+ * 0b0..RX FIFO is empty.
+ * 0b1..RX FIFO is not empty.
+ */
+#define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
+#define SPI_SR_RFOF_MASK (0x80000U)
+#define SPI_SR_RFOF_SHIFT (19U)
+/*! RFOF - Receive FIFO Overflow Flag
+ * 0b0..No Rx FIFO overflow.
+ * 0b1..Rx FIFO overflow has occurred.
+ */
+#define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
+#define SPI_SR_TFFF_MASK (0x2000000U)
+#define SPI_SR_TFFF_SHIFT (25U)
+/*! TFFF - Transmit FIFO Fill Flag
+ * 0b0..TX FIFO is full.
+ * 0b1..TX FIFO is not full.
+ */
+#define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
+#define SPI_SR_TFUF_MASK (0x8000000U)
+#define SPI_SR_TFUF_SHIFT (27U)
+/*! TFUF - Transmit FIFO Underflow Flag
+ * 0b0..No TX FIFO underflow.
+ * 0b1..TX FIFO underflow has occurred.
+ */
+#define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
+#define SPI_SR_EOQF_MASK (0x10000000U)
+#define SPI_SR_EOQF_SHIFT (28U)
+/*! EOQF - End of Queue Flag
+ * 0b0..EOQ is not set in the executing command.
+ * 0b1..EOQ is set in the executing SPI command.
+ */
+#define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
+#define SPI_SR_TXRXS_MASK (0x40000000U)
+#define SPI_SR_TXRXS_SHIFT (30U)
+/*! TXRXS - TX and RX Status
+ * 0b0..Transmit and receive operations are disabled (The module is in Stopped state).
+ * 0b1..Transmit and receive operations are enabled (The module is in Running state).
+ */
+#define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
+#define SPI_SR_TCF_MASK (0x80000000U)
+#define SPI_SR_TCF_SHIFT (31U)
+/*! TCF - Transfer Complete Flag
+ * 0b0..Transfer not complete.
+ * 0b1..Transfer complete.
+ */
+#define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
+/*! @} */
+
+/*! @name RSER - DMA/Interrupt Request Select and Enable Register */
+/*! @{ */
+#define SPI_RSER_RFDF_DIRS_MASK (0x10000U)
+#define SPI_RSER_RFDF_DIRS_SHIFT (16U)
+/*! RFDF_DIRS - Receive FIFO Drain DMA or Interrupt Request Select
+ * 0b0..Interrupt request.
+ * 0b1..DMA request.
+ */
+#define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
+#define SPI_RSER_RFDF_RE_MASK (0x20000U)
+#define SPI_RSER_RFDF_RE_SHIFT (17U)
+/*! RFDF_RE - Receive FIFO Drain Request Enable
+ * 0b0..RFDF interrupt or DMA requests are disabled.
+ * 0b1..RFDF interrupt or DMA requests are enabled.
+ */
+#define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
+#define SPI_RSER_RFOF_RE_MASK (0x80000U)
+#define SPI_RSER_RFOF_RE_SHIFT (19U)
+/*! RFOF_RE - Receive FIFO Overflow Request Enable
+ * 0b0..RFOF interrupt requests are disabled.
+ * 0b1..RFOF interrupt requests are enabled.
+ */
+#define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
+#define SPI_RSER_TFFF_DIRS_MASK (0x1000000U)
+#define SPI_RSER_TFFF_DIRS_SHIFT (24U)
+/*! TFFF_DIRS - Transmit FIFO Fill DMA or Interrupt Request Select
+ * 0b0..TFFF flag generates interrupt requests.
+ * 0b1..TFFF flag generates DMA requests.
+ */
+#define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
+#define SPI_RSER_TFFF_RE_MASK (0x2000000U)
+#define SPI_RSER_TFFF_RE_SHIFT (25U)
+/*! TFFF_RE - Transmit FIFO Fill Request Enable
+ * 0b0..TFFF interrupts or DMA requests are disabled.
+ * 0b1..TFFF interrupts or DMA requests are enabled.
+ */
+#define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
+#define SPI_RSER_TFUF_RE_MASK (0x8000000U)
+#define SPI_RSER_TFUF_RE_SHIFT (27U)
+/*! TFUF_RE - Transmit FIFO Underflow Request Enable
+ * 0b0..TFUF interrupt requests are disabled.
+ * 0b1..TFUF interrupt requests are enabled.
+ */
+#define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
+#define SPI_RSER_EOQF_RE_MASK (0x10000000U)
+#define SPI_RSER_EOQF_RE_SHIFT (28U)
+/*! EOQF_RE - Finished Request Enable
+ * 0b0..EOQF interrupt requests are disabled.
+ * 0b1..EOQF interrupt requests are enabled.
+ */
+#define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
+#define SPI_RSER_TCF_RE_MASK (0x80000000U)
+#define SPI_RSER_TCF_RE_SHIFT (31U)
+/*! TCF_RE - Transmission Complete Request Enable
+ * 0b0..TCF interrupt requests are disabled.
+ * 0b1..TCF interrupt requests are enabled.
+ */
+#define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
+/*! @} */
+
+/*! @name PUSHR - PUSH TX FIFO Register In Master Mode */
+/*! @{ */
+#define SPI_PUSHR_TXDATA_MASK (0xFFFFU)
+#define SPI_PUSHR_TXDATA_SHIFT (0U)
+#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
+#define SPI_PUSHR_PCS_MASK (0x3F0000U)
+#define SPI_PUSHR_PCS_SHIFT (16U)
+/*! PCS
+ * 0b000000..Negate the PCS[x] signal.
+ * 0b000001..Assert the PCS[x] signal.
+ */
+#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
+#define SPI_PUSHR_CTCNT_MASK (0x4000000U)
+#define SPI_PUSHR_CTCNT_SHIFT (26U)
+/*! CTCNT - Clear Transfer Counter
+ * 0b0..Do not clear the TCR[TCNT] field.
+ * 0b1..Clear the TCR[TCNT] field.
+ */
+#define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
+#define SPI_PUSHR_EOQ_MASK (0x8000000U)
+#define SPI_PUSHR_EOQ_SHIFT (27U)
+/*! EOQ - End Of Queue
+ * 0b0..The SPI data is not the last data to transfer.
+ * 0b1..The SPI data is the last data to transfer.
+ */
+#define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
+#define SPI_PUSHR_CTAS_MASK (0x70000000U)
+#define SPI_PUSHR_CTAS_SHIFT (28U)
+/*! CTAS - Clock and Transfer Attributes Select
+ * 0b000..CTAR0
+ * 0b001..CTAR1
+ * 0b010..Reserved
+ * 0b011..Reserved
+ * 0b100..Reserved
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..Reserved
+ */
+#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
+#define SPI_PUSHR_CONT_MASK (0x80000000U)
+#define SPI_PUSHR_CONT_SHIFT (31U)
+/*! CONT - Continuous Peripheral Chip Select Enable
+ * 0b0..Return PCSn signals to their inactive state between transfers.
+ * 0b1..Keep PCSn signals asserted between transfers.
+ */
+#define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
+/*! @} */
+
+/*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */
+/*! @{ */
+#define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFFFFFU)
+#define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U)
+#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
+/*! @} */
+
+/*! @name POPR - POP RX FIFO Register */
+/*! @{ */
+#define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU)
+#define SPI_POPR_RXDATA_SHIFT (0U)
+#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
+/*! @} */
+
+/*! @name TXFR0 - Transmit FIFO Registers */
+/*! @{ */
+#define SPI_TXFR0_TXDATA_MASK (0xFFFFU)
+#define SPI_TXFR0_TXDATA_SHIFT (0U)
+#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
+#define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U)
+#define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U)
+#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
+/*! @} */
+
+/*! @name TXFR1 - Transmit FIFO Registers */
+/*! @{ */
+#define SPI_TXFR1_TXDATA_MASK (0xFFFFU)
+#define SPI_TXFR1_TXDATA_SHIFT (0U)
+#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
+#define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U)
+#define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U)
+#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
+/*! @} */
+
+/*! @name TXFR2 - Transmit FIFO Registers */
+/*! @{ */
+#define SPI_TXFR2_TXDATA_MASK (0xFFFFU)
+#define SPI_TXFR2_TXDATA_SHIFT (0U)
+#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
+#define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U)
+#define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U)
+#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
+/*! @} */
+
+/*! @name TXFR3 - Transmit FIFO Registers */
+/*! @{ */
+#define SPI_TXFR3_TXDATA_MASK (0xFFFFU)
+#define SPI_TXFR3_TXDATA_SHIFT (0U)
+#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
+#define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U)
+#define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U)
+#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
+/*! @} */
+
+/*! @name RXFR0 - Receive FIFO Registers */
+/*! @{ */
+#define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU)
+#define SPI_RXFR0_RXDATA_SHIFT (0U)
+#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
+/*! @} */
+
+/*! @name RXFR1 - Receive FIFO Registers */
+/*! @{ */
+#define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU)
+#define SPI_RXFR1_RXDATA_SHIFT (0U)
+#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
+/*! @} */
+
+/*! @name RXFR2 - Receive FIFO Registers */
+/*! @{ */
+#define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU)
+#define SPI_RXFR2_RXDATA_SHIFT (0U)
+#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
+/*! @} */
+
+/*! @name RXFR3 - Receive FIFO Registers */
+/*! @{ */
+#define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU)
+#define SPI_RXFR3_RXDATA_SHIFT (0U)
+#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE (0x4002C000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0 ((SPI_Type *)SPI0_BASE)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE (0x4002D000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1 ((SPI_Type *)SPI1_BASE)
+/** Peripheral SPI2 base address */
+#define SPI2_BASE (0x400AC000u)
+/** Peripheral SPI2 base pointer */
+#define SPI2 ((SPI_Type *)SPI2_BASE)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS { SPI0, SPI1, SPI2 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SYSMPU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSMPU_Peripheral_Access_Layer SYSMPU Peripheral Access Layer
+ * @{
+ */
+
+/** SYSMPU - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
+ uint8_t RESERVED_0[12];
+ struct { /* offset: 0x10, array step: 0x8 */
+ __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
+ __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
+ } SP[5];
+ uint8_t RESERVED_1[968];
+ __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
+ uint8_t RESERVED_2[832];
+ __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
+} SYSMPU_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SYSMPU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSMPU_Register_Masks SYSMPU Register Masks
+ * @{
+ */
+
+/*! @name CESR - Control/Error Status Register */
+/*! @{ */
+#define SYSMPU_CESR_VLD_MASK (0x1U)
+#define SYSMPU_CESR_VLD_SHIFT (0U)
+/*! VLD - Valid
+ * 0b0..MPU is disabled. All accesses from all bus masters are allowed.
+ * 0b1..MPU is enabled
+ */
+#define SYSMPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)
+#define SYSMPU_CESR_NRGD_MASK (0xF00U)
+#define SYSMPU_CESR_NRGD_SHIFT (8U)
+/*! NRGD - Number Of Region Descriptors
+ * 0b0000..8 region descriptors
+ * 0b0001..12 region descriptors
+ * 0b0010..16 region descriptors
+ */
+#define SYSMPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)
+#define SYSMPU_CESR_NSP_MASK (0xF000U)
+#define SYSMPU_CESR_NSP_SHIFT (12U)
+#define SYSMPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK)
+#define SYSMPU_CESR_HRL_MASK (0xF0000U)
+#define SYSMPU_CESR_HRL_SHIFT (16U)
+#define SYSMPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK)
+#define SYSMPU_CESR_SPERR_MASK (0xF8000000U)
+#define SYSMPU_CESR_SPERR_SHIFT (27U)
+/*! SPERR - Slave Port n Error
+ * 0b00000..No error has occurred for slave port n.
+ * 0b00001..An error has occurred for slave port n.
+ */
+#define SYSMPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)
+/*! @} */
+
+/*! @name EAR - Error Address Register, slave port n */
+/*! @{ */
+#define SYSMPU_EAR_EADDR_MASK (0xFFFFFFFFU)
+#define SYSMPU_EAR_EADDR_SHIFT (0U)
+#define SYSMPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK)
+/*! @} */
+
+/* The count of SYSMPU_EAR */
+#define SYSMPU_EAR_COUNT (5U)
+
+/*! @name EDR - Error Detail Register, slave port n */
+/*! @{ */
+#define SYSMPU_EDR_ERW_MASK (0x1U)
+#define SYSMPU_EDR_ERW_SHIFT (0U)
+/*! ERW - Error Read/Write
+ * 0b0..Read
+ * 0b1..Write
+ */
+#define SYSMPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)
+#define SYSMPU_EDR_EATTR_MASK (0xEU)
+#define SYSMPU_EDR_EATTR_SHIFT (1U)
+/*! EATTR - Error Attributes
+ * 0b000..User mode, instruction access
+ * 0b001..User mode, data access
+ * 0b010..Supervisor mode, instruction access
+ * 0b011..Supervisor mode, data access
+ */
+#define SYSMPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)
+#define SYSMPU_EDR_EMN_MASK (0xF0U)
+#define SYSMPU_EDR_EMN_SHIFT (4U)
+#define SYSMPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK)
+#define SYSMPU_EDR_EPID_MASK (0xFF00U)
+#define SYSMPU_EDR_EPID_SHIFT (8U)
+#define SYSMPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EPID_SHIFT)) & SYSMPU_EDR_EPID_MASK)
+#define SYSMPU_EDR_EACD_MASK (0xFFFF0000U)
+#define SYSMPU_EDR_EACD_SHIFT (16U)
+#define SYSMPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK)
+/*! @} */
+
+/* The count of SYSMPU_EDR */
+#define SYSMPU_EDR_COUNT (5U)
+
+/*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */
+/*! @{ */
+#define SYSMPU_WORD_M0UM_MASK (0x7U)
+#define SYSMPU_WORD_M0UM_SHIFT (0U)
+#define SYSMPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK)
+#define SYSMPU_WORD_VLD_MASK (0x1U)
+#define SYSMPU_WORD_VLD_SHIFT (0U)
+/*! VLD - Valid
+ * 0b0..Region descriptor is invalid
+ * 0b1..Region descriptor is valid
+ */
+#define SYSMPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)
+#define SYSMPU_WORD_M0SM_MASK (0x18U)
+#define SYSMPU_WORD_M0SM_SHIFT (3U)
+#define SYSMPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK)
+#define SYSMPU_WORD_ENDADDR_MASK (0xFFFFFFE0U)
+#define SYSMPU_WORD_ENDADDR_SHIFT (5U)
+#define SYSMPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK)
+#define SYSMPU_WORD_M0PE_MASK (0x20U)
+#define SYSMPU_WORD_M0PE_SHIFT (5U)
+#define SYSMPU_WORD_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0PE_SHIFT)) & SYSMPU_WORD_M0PE_MASK)
+#define SYSMPU_WORD_SRTADDR_MASK (0xFFFFFFE0U)
+#define SYSMPU_WORD_SRTADDR_SHIFT (5U)
+#define SYSMPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK)
+#define SYSMPU_WORD_M1UM_MASK (0x1C0U)
+#define SYSMPU_WORD_M1UM_SHIFT (6U)
+#define SYSMPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK)
+#define SYSMPU_WORD_M1SM_MASK (0x600U)
+#define SYSMPU_WORD_M1SM_SHIFT (9U)
+#define SYSMPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK)
+#define SYSMPU_WORD_M1PE_MASK (0x800U)
+#define SYSMPU_WORD_M1PE_SHIFT (11U)
+#define SYSMPU_WORD_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1PE_SHIFT)) & SYSMPU_WORD_M1PE_MASK)
+#define SYSMPU_WORD_M2UM_MASK (0x7000U)
+#define SYSMPU_WORD_M2UM_SHIFT (12U)
+#define SYSMPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK)
+#define SYSMPU_WORD_M2SM_MASK (0x18000U)
+#define SYSMPU_WORD_M2SM_SHIFT (15U)
+#define SYSMPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK)
+#define SYSMPU_WORD_PIDMASK_MASK (0xFF0000U)
+#define SYSMPU_WORD_PIDMASK_SHIFT (16U)
+#define SYSMPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PIDMASK_SHIFT)) & SYSMPU_WORD_PIDMASK_MASK)
+#define SYSMPU_WORD_M2PE_MASK (0x20000U)
+#define SYSMPU_WORD_M2PE_SHIFT (17U)
+#define SYSMPU_WORD_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2PE_SHIFT)) & SYSMPU_WORD_M2PE_MASK)
+#define SYSMPU_WORD_M3UM_MASK (0x1C0000U)
+#define SYSMPU_WORD_M3UM_SHIFT (18U)
+/*! M3UM - Bus Master 3 User Mode Access Control
+ * 0b000..An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.
+ * 0b001..Allows the given access type to occur
+ */
+#define SYSMPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)
+#define SYSMPU_WORD_M3SM_MASK (0x600000U)
+#define SYSMPU_WORD_M3SM_SHIFT (21U)
+/*! M3SM - Bus Master 3 Supervisor Mode Access Control
+ * 0b00..r/w/x; read, write and execute allowed
+ * 0b01..r/x; read and execute allowed, but no write
+ * 0b10..r/w; read and write allowed, but no execute
+ * 0b11..Same as User mode defined in M3UM
+ */
+#define SYSMPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)
+#define SYSMPU_WORD_M3PE_MASK (0x800000U)
+#define SYSMPU_WORD_M3PE_SHIFT (23U)
+/*! M3PE - Bus Master 3 Process Identifier Enable
+ * 0b0..Do not include the process identifier in the evaluation
+ * 0b1..Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation
+ */
+#define SYSMPU_WORD_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK)
+#define SYSMPU_WORD_M4WE_MASK (0x1000000U)
+#define SYSMPU_WORD_M4WE_SHIFT (24U)
+/*! M4WE - Bus Master 4 Write Enable
+ * 0b0..Bus master 4 writes terminate with an access error and the write is not performed
+ * 0b1..Bus master 4 writes allowed
+ */
+#define SYSMPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)
+#define SYSMPU_WORD_PID_MASK (0xFF000000U)
+#define SYSMPU_WORD_PID_SHIFT (24U)
+#define SYSMPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK)
+#define SYSMPU_WORD_M4RE_MASK (0x2000000U)
+#define SYSMPU_WORD_M4RE_SHIFT (25U)
+/*! M4RE - Bus Master 4 Read Enable
+ * 0b0..Bus master 4 reads terminate with an access error and the read is not performed
+ * 0b1..Bus master 4 reads allowed
+ */
+#define SYSMPU_WORD_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)
+#define SYSMPU_WORD_M5WE_MASK (0x4000000U)
+#define SYSMPU_WORD_M5WE_SHIFT (26U)
+/*! M5WE - Bus Master 5 Write Enable
+ * 0b0..Bus master 5 writes terminate with an access error and the write is not performed
+ * 0b1..Bus master 5 writes allowed
+ */
+#define SYSMPU_WORD_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)
+#define SYSMPU_WORD_M5RE_MASK (0x8000000U)
+#define SYSMPU_WORD_M5RE_SHIFT (27U)
+/*! M5RE - Bus Master 5 Read Enable
+ * 0b0..Bus master 5 reads terminate with an access error and the read is not performed
+ * 0b1..Bus master 5 reads allowed
+ */
+#define SYSMPU_WORD_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)
+#define SYSMPU_WORD_M6WE_MASK (0x10000000U)
+#define SYSMPU_WORD_M6WE_SHIFT (28U)
+/*! M6WE - Bus Master 6 Write Enable
+ * 0b0..Bus master 6 writes terminate with an access error and the write is not performed
+ * 0b1..Bus master 6 writes allowed
+ */
+#define SYSMPU_WORD_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)
+#define SYSMPU_WORD_M6RE_MASK (0x20000000U)
+#define SYSMPU_WORD_M6RE_SHIFT (29U)
+/*! M6RE - Bus Master 6 Read Enable
+ * 0b0..Bus master 6 reads terminate with an access error and the read is not performed
+ * 0b1..Bus master 6 reads allowed
+ */
+#define SYSMPU_WORD_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)
+#define SYSMPU_WORD_M7WE_MASK (0x40000000U)
+#define SYSMPU_WORD_M7WE_SHIFT (30U)
+/*! M7WE - Bus Master 7 Write Enable
+ * 0b0..Bus master 7 writes terminate with an access error and the write is not performed
+ * 0b1..Bus master 7 writes allowed
+ */
+#define SYSMPU_WORD_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)
+#define SYSMPU_WORD_M7RE_MASK (0x80000000U)
+#define SYSMPU_WORD_M7RE_SHIFT (31U)
+/*! M7RE - Bus Master 7 Read Enable
+ * 0b0..Bus master 7 reads terminate with an access error and the read is not performed
+ * 0b1..Bus master 7 reads allowed
+ */
+#define SYSMPU_WORD_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)
+/*! @} */
+
+/* The count of SYSMPU_WORD */
+#define SYSMPU_WORD_COUNT (12U)
+
+/* The count of SYSMPU_WORD */
+#define SYSMPU_WORD_COUNT2 (4U)
+
+/*! @name RGDAAC - Region Descriptor Alternate Access Control n */
+/*! @{ */
+#define SYSMPU_RGDAAC_M0UM_MASK (0x7U)
+#define SYSMPU_RGDAAC_M0UM_SHIFT (0U)
+#define SYSMPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK)
+#define SYSMPU_RGDAAC_M0SM_MASK (0x18U)
+#define SYSMPU_RGDAAC_M0SM_SHIFT (3U)
+#define SYSMPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK)
+#define SYSMPU_RGDAAC_M0PE_MASK (0x20U)
+#define SYSMPU_RGDAAC_M0PE_SHIFT (5U)
+#define SYSMPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0PE_SHIFT)) & SYSMPU_RGDAAC_M0PE_MASK)
+#define SYSMPU_RGDAAC_M1UM_MASK (0x1C0U)
+#define SYSMPU_RGDAAC_M1UM_SHIFT (6U)
+#define SYSMPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK)
+#define SYSMPU_RGDAAC_M1SM_MASK (0x600U)
+#define SYSMPU_RGDAAC_M1SM_SHIFT (9U)
+#define SYSMPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK)
+#define SYSMPU_RGDAAC_M1PE_MASK (0x800U)
+#define SYSMPU_RGDAAC_M1PE_SHIFT (11U)
+#define SYSMPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1PE_SHIFT)) & SYSMPU_RGDAAC_M1PE_MASK)
+#define SYSMPU_RGDAAC_M2UM_MASK (0x7000U)
+#define SYSMPU_RGDAAC_M2UM_SHIFT (12U)
+#define SYSMPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK)
+#define SYSMPU_RGDAAC_M2SM_MASK (0x18000U)
+#define SYSMPU_RGDAAC_M2SM_SHIFT (15U)
+#define SYSMPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK)
+#define SYSMPU_RGDAAC_M2PE_MASK (0x20000U)
+#define SYSMPU_RGDAAC_M2PE_SHIFT (17U)
+#define SYSMPU_RGDAAC_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2PE_SHIFT)) & SYSMPU_RGDAAC_M2PE_MASK)
+#define SYSMPU_RGDAAC_M3UM_MASK (0x1C0000U)
+#define SYSMPU_RGDAAC_M3UM_SHIFT (18U)
+/*! M3UM - Bus Master 3 User Mode Access Control
+ * 0b000..An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.
+ * 0b001..Allows the given access type to occur
+ */
+#define SYSMPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)
+#define SYSMPU_RGDAAC_M3SM_MASK (0x600000U)
+#define SYSMPU_RGDAAC_M3SM_SHIFT (21U)
+/*! M3SM - Bus Master 3 Supervisor Mode Access Control
+ * 0b00..r/w/x; read, write and execute allowed
+ * 0b01..r/x; read and execute allowed, but no write
+ * 0b10..r/w; read and write allowed, but no execute
+ * 0b11..Same as User mode defined in M3UM
+ */
+#define SYSMPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)
+#define SYSMPU_RGDAAC_M3PE_MASK (0x800000U)
+#define SYSMPU_RGDAAC_M3PE_SHIFT (23U)
+/*! M3PE - Bus Master 3 Process Identifier Enable
+ * 0b0..Do not include the process identifier in the evaluation
+ * 0b1..Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
+ */
+#define SYSMPU_RGDAAC_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK)
+#define SYSMPU_RGDAAC_M4WE_MASK (0x1000000U)
+#define SYSMPU_RGDAAC_M4WE_SHIFT (24U)
+/*! M4WE - Bus Master 4 Write Enable
+ * 0b0..Bus master 4 writes terminate with an access error and the write is not performed
+ * 0b1..Bus master 4 writes allowed
+ */
+#define SYSMPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)
+#define SYSMPU_RGDAAC_M4RE_MASK (0x2000000U)
+#define SYSMPU_RGDAAC_M4RE_SHIFT (25U)
+/*! M4RE - Bus Master 4 Read Enable
+ * 0b0..Bus master 4 reads terminate with an access error and the read is not performed
+ * 0b1..Bus master 4 reads allowed
+ */
+#define SYSMPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)
+#define SYSMPU_RGDAAC_M5WE_MASK (0x4000000U)
+#define SYSMPU_RGDAAC_M5WE_SHIFT (26U)
+/*! M5WE - Bus Master 5 Write Enable
+ * 0b0..Bus master 5 writes terminate with an access error and the write is not performed
+ * 0b1..Bus master 5 writes allowed
+ */
+#define SYSMPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)
+#define SYSMPU_RGDAAC_M5RE_MASK (0x8000000U)
+#define SYSMPU_RGDAAC_M5RE_SHIFT (27U)
+/*! M5RE - Bus Master 5 Read Enable
+ * 0b0..Bus master 5 reads terminate with an access error and the read is not performed
+ * 0b1..Bus master 5 reads allowed
+ */
+#define SYSMPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)
+#define SYSMPU_RGDAAC_M6WE_MASK (0x10000000U)
+#define SYSMPU_RGDAAC_M6WE_SHIFT (28U)
+/*! M6WE - Bus Master 6 Write Enable
+ * 0b0..Bus master 6 writes terminate with an access error and the write is not performed
+ * 0b1..Bus master 6 writes allowed
+ */
+#define SYSMPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)
+#define SYSMPU_RGDAAC_M6RE_MASK (0x20000000U)
+#define SYSMPU_RGDAAC_M6RE_SHIFT (29U)
+/*! M6RE - Bus Master 6 Read Enable
+ * 0b0..Bus master 6 reads terminate with an access error and the read is not performed
+ * 0b1..Bus master 6 reads allowed
+ */
+#define SYSMPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)
+#define SYSMPU_RGDAAC_M7WE_MASK (0x40000000U)
+#define SYSMPU_RGDAAC_M7WE_SHIFT (30U)
+/*! M7WE - Bus Master 7 Write Enable
+ * 0b0..Bus master 7 writes terminate with an access error and the write is not performed
+ * 0b1..Bus master 7 writes allowed
+ */
+#define SYSMPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)
+#define SYSMPU_RGDAAC_M7RE_MASK (0x80000000U)
+#define SYSMPU_RGDAAC_M7RE_SHIFT (31U)
+/*! M7RE - Bus Master 7 Read Enable
+ * 0b0..Bus master 7 reads terminate with an access error and the read is not performed
+ * 0b1..Bus master 7 reads allowed
+ */
+#define SYSMPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)
+/*! @} */
+
+/* The count of SYSMPU_RGDAAC */
+#define SYSMPU_RGDAAC_COUNT (12U)
+
+
+/*!
+ * @}
+ */ /* end of group SYSMPU_Register_Masks */
+
+
+/* SYSMPU - Peripheral instance base addresses */
+/** Peripheral SYSMPU base address */
+#define SYSMPU_BASE (0x4000D000u)
+/** Peripheral SYSMPU base pointer */
+#define SYSMPU ((SYSMPU_Type *)SYSMPU_BASE)
+/** Array initializer of SYSMPU peripheral base addresses */
+#define SYSMPU_BASE_ADDRS { SYSMPU_BASE }
+/** Array initializer of SYSMPU peripheral base pointers */
+#define SYSMPU_BASE_PTRS { SYSMPU }
+
+/*!
+ * @}
+ */ /* end of group SYSMPU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TPM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
+ * @{
+ */
+
+/** TPM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
+ __IO uint32_t CNT; /**< Counter, offset: 0x4 */
+ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
+ struct { /* offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+ } CONTROLS[2];
+ uint8_t RESERVED_0[52];
+ __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
+ uint8_t RESERVED_1[16];
+ __IO uint32_t COMBINE; /**< Combine Channel Register, offset: 0x64 */
+ uint8_t RESERVED_2[8];
+ __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t FILTER; /**< Filter Control, offset: 0x78 */
+ uint8_t RESERVED_4[4];
+ __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */
+ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
+} TPM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TPM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Register_Masks TPM Register Masks
+ * @{
+ */
+
+/*! @name SC - Status and Control */
+/*! @{ */
+#define TPM_SC_PS_MASK (0x7U)
+#define TPM_SC_PS_SHIFT (0U)
+/*! PS - Prescale Factor Selection
+ * 0b000..Divide by 1
+ * 0b001..Divide by 2
+ * 0b010..Divide by 4
+ * 0b011..Divide by 8
+ * 0b100..Divide by 16
+ * 0b101..Divide by 32
+ * 0b110..Divide by 64
+ * 0b111..Divide by 128
+ */
+#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
+#define TPM_SC_CMOD_MASK (0x18U)
+#define TPM_SC_CMOD_SHIFT (3U)
+/*! CMOD - Clock Mode Selection
+ * 0b00..TPM counter is disabled
+ * 0b01..TPM counter increments on every TPM counter clock
+ * 0b10..TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock
+ * 0b11..Reserved.
+ */
+#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
+#define TPM_SC_CPWMS_MASK (0x20U)
+#define TPM_SC_CPWMS_SHIFT (5U)
+/*! CPWMS - Center-Aligned PWM Select
+ * 0b0..TPM counter operates in up counting mode.
+ * 0b1..TPM counter operates in up-down counting mode.
+ */
+#define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
+#define TPM_SC_TOIE_MASK (0x40U)
+#define TPM_SC_TOIE_SHIFT (6U)
+/*! TOIE - Timer Overflow Interrupt Enable
+ * 0b0..Disable TOF interrupts. Use software polling or DMA request.
+ * 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.
+ */
+#define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
+#define TPM_SC_TOF_MASK (0x80U)
+#define TPM_SC_TOF_SHIFT (7U)
+/*! TOF - Timer Overflow Flag
+ * 0b0..TPM counter has not overflowed.
+ * 0b1..TPM counter has overflowed.
+ */
+#define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
+#define TPM_SC_DMA_MASK (0x100U)
+#define TPM_SC_DMA_SHIFT (8U)
+/*! DMA - DMA Enable
+ * 0b0..Disables DMA transfers.
+ * 0b1..Enables DMA transfers.
+ */
+#define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
+/*! @} */
+
+/*! @name CNT - Counter */
+/*! @{ */
+#define TPM_CNT_COUNT_MASK (0xFFFFU)
+#define TPM_CNT_COUNT_SHIFT (0U)
+#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
+/*! @} */
+
+/*! @name MOD - Modulo */
+/*! @{ */
+#define TPM_MOD_MOD_MASK (0xFFFFU)
+#define TPM_MOD_MOD_SHIFT (0U)
+#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
+/*! @} */
+
+/*! @name CnSC - Channel (n) Status and Control */
+/*! @{ */
+#define TPM_CnSC_DMA_MASK (0x1U)
+#define TPM_CnSC_DMA_SHIFT (0U)
+/*! DMA - DMA Enable
+ * 0b0..Disable DMA transfers.
+ * 0b1..Enable DMA transfers.
+ */
+#define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
+#define TPM_CnSC_ELSA_MASK (0x4U)
+#define TPM_CnSC_ELSA_SHIFT (2U)
+#define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
+#define TPM_CnSC_ELSB_MASK (0x8U)
+#define TPM_CnSC_ELSB_SHIFT (3U)
+#define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
+#define TPM_CnSC_MSA_MASK (0x10U)
+#define TPM_CnSC_MSA_SHIFT (4U)
+#define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
+#define TPM_CnSC_MSB_MASK (0x20U)
+#define TPM_CnSC_MSB_SHIFT (5U)
+#define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
+#define TPM_CnSC_CHIE_MASK (0x40U)
+#define TPM_CnSC_CHIE_SHIFT (6U)
+/*! CHIE - Channel Interrupt Enable
+ * 0b0..Disable channel interrupts.
+ * 0b1..Enable channel interrupts.
+ */
+#define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
+#define TPM_CnSC_CHF_MASK (0x80U)
+#define TPM_CnSC_CHF_SHIFT (7U)
+/*! CHF - Channel Flag
+ * 0b0..No channel event has occurred.
+ * 0b1..A channel event has occurred.
+ */
+#define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
+/*! @} */
+
+/* The count of TPM_CnSC */
+#define TPM_CnSC_COUNT (2U)
+
+/*! @name CnV - Channel (n) Value */
+/*! @{ */
+#define TPM_CnV_VAL_MASK (0xFFFFU)
+#define TPM_CnV_VAL_SHIFT (0U)
+#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
+/*! @} */
+
+/* The count of TPM_CnV */
+#define TPM_CnV_COUNT (2U)
+
+/*! @name STATUS - Capture and Compare Status */
+/*! @{ */
+#define TPM_STATUS_CH0F_MASK (0x1U)
+#define TPM_STATUS_CH0F_SHIFT (0U)
+/*! CH0F - Channel 0 Flag
+ * 0b0..No channel event has occurred.
+ * 0b1..A channel event has occurred.
+ */
+#define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
+#define TPM_STATUS_CH1F_MASK (0x2U)
+#define TPM_STATUS_CH1F_SHIFT (1U)
+/*! CH1F - Channel 1 Flag
+ * 0b0..No channel event has occurred.
+ * 0b1..A channel event has occurred.
+ */
+#define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
+#define TPM_STATUS_TOF_MASK (0x100U)
+#define TPM_STATUS_TOF_SHIFT (8U)
+/*! TOF - Timer Overflow Flag
+ * 0b0..TPM counter has not overflowed.
+ * 0b1..TPM counter has overflowed.
+ */
+#define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
+/*! @} */
+
+/*! @name COMBINE - Combine Channel Register */
+/*! @{ */
+#define TPM_COMBINE_COMBINE0_MASK (0x1U)
+#define TPM_COMBINE_COMBINE0_SHIFT (0U)
+/*! COMBINE0 - Combine Channels 0 and 1
+ * 0b0..Channels 0 and 1 are independent.
+ * 0b1..Channels 0 and 1 are combined.
+ */
+#define TPM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)
+#define TPM_COMBINE_COMSWAP0_MASK (0x2U)
+#define TPM_COMBINE_COMSWAP0_SHIFT (1U)
+/*! COMSWAP0 - Combine Channel 0 and 1 Swap
+ * 0b0..Even channel is used for input capture and 1st compare.
+ * 0b1..Odd channel is used for input capture and 1st compare.
+ */
+#define TPM_COMBINE_COMSWAP0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)
+/*! @} */
+
+/*! @name POL - Channel Polarity */
+/*! @{ */
+#define TPM_POL_POL0_MASK (0x1U)
+#define TPM_POL_POL0_SHIFT (0U)
+/*! POL0 - Channel 0 Polarity
+ * 0b0..The channel polarity is active high.
+ * 0b1..The channel polarity is active low.
+ */
+#define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)
+#define TPM_POL_POL1_MASK (0x2U)
+#define TPM_POL_POL1_SHIFT (1U)
+/*! POL1 - Channel 1 Polarity
+ * 0b0..The channel polarity is active high.
+ * 0b1..The channel polarity is active low.
+ */
+#define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)
+/*! @} */
+
+/*! @name FILTER - Filter Control */
+/*! @{ */
+#define TPM_FILTER_CH0FVAL_MASK (0xFU)
+#define TPM_FILTER_CH0FVAL_SHIFT (0U)
+#define TPM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK)
+#define TPM_FILTER_CH1FVAL_MASK (0xF0U)
+#define TPM_FILTER_CH1FVAL_SHIFT (4U)
+#define TPM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK)
+/*! @} */
+
+/*! @name QDCTRL - Quadrature Decoder Control and Status */
+/*! @{ */
+#define TPM_QDCTRL_QUADEN_MASK (0x1U)
+#define TPM_QDCTRL_QUADEN_SHIFT (0U)
+/*! QUADEN
+ * 0b0..Quadrature decoder mode is disabled.
+ * 0b1..Quadrature decoder mode is enabled.
+ */
+#define TPM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK)
+#define TPM_QDCTRL_TOFDIR_MASK (0x2U)
+#define TPM_QDCTRL_TOFDIR_SHIFT (1U)
+/*! TOFDIR
+ * 0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register).
+ * 0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero).
+ */
+#define TPM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK)
+#define TPM_QDCTRL_QUADIR_MASK (0x4U)
+#define TPM_QDCTRL_QUADIR_SHIFT (2U)
+/*! QUADIR - Counter Direction in Quadrature Decode Mode
+ * 0b0..Counter direction is decreasing (counter decrement).
+ * 0b1..Counter direction is increasing (counter increment).
+ */
+#define TPM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK)
+#define TPM_QDCTRL_QUADMODE_MASK (0x8U)
+#define TPM_QDCTRL_QUADMODE_SHIFT (3U)
+/*! QUADMODE - Quadrature Decoder Mode
+ * 0b0..Phase encoding mode.
+ * 0b1..Count and direction encoding mode.
+ */
+#define TPM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK)
+/*! @} */
+
+/*! @name CONF - Configuration */
+/*! @{ */
+#define TPM_CONF_DOZEEN_MASK (0x20U)
+#define TPM_CONF_DOZEEN_SHIFT (5U)
+/*! DOZEEN - Doze Enable
+ * 0b0..Internal TPM counter continues in Doze mode.
+ * 0b1..Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored.
+ */
+#define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
+#define TPM_CONF_DBGMODE_MASK (0xC0U)
+#define TPM_CONF_DBGMODE_SHIFT (6U)
+/*! DBGMODE - Debug Mode
+ * 0b00..TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored.
+ * 0b11..TPM counter continues in debug mode.
+ */
+#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
+#define TPM_CONF_GTBSYNC_MASK (0x100U)
+#define TPM_CONF_GTBSYNC_SHIFT (8U)
+/*! GTBSYNC - Global Time Base Synchronization
+ * 0b0..Global timebase synchronization disabled.
+ * 0b1..Global timebase synchronization enabled.
+ */
+#define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)
+#define TPM_CONF_GTBEEN_MASK (0x200U)
+#define TPM_CONF_GTBEEN_SHIFT (9U)
+/*! GTBEEN - Global time base enable
+ * 0b0..All channels use the internally generated TPM counter as their timebase
+ * 0b1..All channels use an externally generated global timebase as their timebase
+ */
+#define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
+#define TPM_CONF_CSOT_MASK (0x10000U)
+#define TPM_CONF_CSOT_SHIFT (16U)
+/*! CSOT - Counter Start on Trigger
+ * 0b0..TPM counter starts to increment immediately, once it is enabled.
+ * 0b1..TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow.
+ */
+#define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
+#define TPM_CONF_CSOO_MASK (0x20000U)
+#define TPM_CONF_CSOO_SHIFT (17U)
+/*! CSOO - Counter Stop On Overflow
+ * 0b0..TPM counter continues incrementing or decrementing after overflow
+ * 0b1..TPM counter stops incrementing or decrementing after overflow.
+ */
+#define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
+#define TPM_CONF_CROT_MASK (0x40000U)
+#define TPM_CONF_CROT_SHIFT (18U)
+/*! CROT - Counter Reload On Trigger
+ * 0b0..Counter is not reloaded due to a rising edge on the selected input trigger
+ * 0b1..Counter is reloaded when a rising edge is detected on the selected input trigger
+ */
+#define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
+#define TPM_CONF_CPOT_MASK (0x80000U)
+#define TPM_CONF_CPOT_SHIFT (19U)
+#define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)
+#define TPM_CONF_TRGPOL_MASK (0x400000U)
+#define TPM_CONF_TRGPOL_SHIFT (22U)
+/*! TRGPOL - Trigger Polarity
+ * 0b0..Trigger is active high.
+ * 0b1..Trigger is active low.
+ */
+#define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)
+#define TPM_CONF_TRGSRC_MASK (0x800000U)
+#define TPM_CONF_TRGSRC_SHIFT (23U)
+/*! TRGSRC - Trigger Source
+ * 0b0..Trigger source selected by TRGSEL is external.
+ * 0b1..Trigger source selected by TRGSEL is internal (channel pin input capture).
+ */
+#define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)
+#define TPM_CONF_TRGSEL_MASK (0xF000000U)
+#define TPM_CONF_TRGSEL_SHIFT (24U)
+/*! TRGSEL - Trigger Select
+ * 0b0001..Channel 0 pin input capture
+ * 0b0010..Channel 1 pin input capture
+ * 0b0011..Channel 0 or Channel 1 pin input capture
+ */
+#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group TPM_Register_Masks */
+
+
+/* TPM - Peripheral instance base addresses */
+/** Peripheral TPM1 base address */
+#define TPM1_BASE (0x400C9000u)
+/** Peripheral TPM1 base pointer */
+#define TPM1 ((TPM_Type *)TPM1_BASE)
+/** Peripheral TPM2 base address */
+#define TPM2_BASE (0x400CA000u)
+/** Peripheral TPM2 base pointer */
+#define TPM2 ((TPM_Type *)TPM2_BASE)
+/** Array initializer of TPM peripheral base addresses */
+#define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE }
+/** Array initializer of TPM peripheral base pointers */
+#define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2 }
+/** Interrupt vectors for the TPM peripheral type */
+#define TPM_IRQS { NotAvail_IRQn, TPM1_IRQn, TPM2_IRQn }
+
+/*!
+ * @}
+ */ /* end of group TPM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TSI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
+ * @{
+ */
+
+/** TSI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
+ __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
+ __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
+} TSI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TSI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TSI_Register_Masks TSI Register Masks
+ * @{
+ */
+
+/*! @name GENCS - TSI General Control and Status Register */
+/*! @{ */
+#define TSI_GENCS_EOSDMEO_MASK (0x1U)
+#define TSI_GENCS_EOSDMEO_SHIFT (0U)
+/*! EOSDMEO - End-of-Scan DMA Transfer Request Enable Only
+ * 0b0..Do not enable the End-of-Scan DMA transfer request only. Depending on ESOR state, either Out-of-Range or End-of-Scan can trigger a DMA transfer request and interrupt.
+ * 0b1..Only the End-of-Scan event can trigger a DMA transfer request. The Out-of-Range event only and always triggers an interrupt if TSIIE is set.
+ */
+#define TSI_GENCS_EOSDMEO(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSDMEO_SHIFT)) & TSI_GENCS_EOSDMEO_MASK)
+#define TSI_GENCS_CURSW_MASK (0x2U)
+#define TSI_GENCS_CURSW_SHIFT (1U)
+/*! CURSW - CURSW
+ * 0b0..The current source pair are not swapped.
+ * 0b1..The current source pair are swapped.
+ */
+#define TSI_GENCS_CURSW(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK)
+#define TSI_GENCS_EOSF_MASK (0x4U)
+#define TSI_GENCS_EOSF_SHIFT (2U)
+/*! EOSF - End of Scan Flag
+ * 0b0..Scan not complete.
+ * 0b1..Scan complete.
+ */
+#define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
+#define TSI_GENCS_SCNIP_MASK (0x8U)
+#define TSI_GENCS_SCNIP_SHIFT (3U)
+/*! SCNIP - Scan In Progress Status
+ * 0b0..No scan in progress.
+ * 0b1..Scan in progress.
+ */
+#define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
+#define TSI_GENCS_STM_MASK (0x10U)
+#define TSI_GENCS_STM_SHIFT (4U)
+/*! STM - Scan Trigger Mode
+ * 0b0..Software trigger scan.
+ * 0b1..Hardware trigger scan.
+ */
+#define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
+#define TSI_GENCS_STPE_MASK (0x20U)
+#define TSI_GENCS_STPE_SHIFT (5U)
+/*! STPE - TSI STOP Enable
+ * 0b0..TSI is disabled when MCU goes into low power mode.
+ * 0b1..Allows TSI to continue running in all low power modes.
+ */
+#define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
+#define TSI_GENCS_TSIIEN_MASK (0x40U)
+#define TSI_GENCS_TSIIEN_SHIFT (6U)
+/*! TSIIEN - Touch Sensing Input Interrupt Enable
+ * 0b0..TSI interrupt is disabled.
+ * 0b1..TSI interrupt is enabled.
+ */
+#define TSI_GENCS_TSIIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK)
+#define TSI_GENCS_TSIEN_MASK (0x80U)
+#define TSI_GENCS_TSIEN_SHIFT (7U)
+/*! TSIEN - Touch Sensing Input Module Enable
+ * 0b0..TSI module disabled.
+ * 0b1..TSI module enabled.
+ */
+#define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
+#define TSI_GENCS_NSCN_MASK (0x1F00U)
+#define TSI_GENCS_NSCN_SHIFT (8U)
+/*! NSCN - NSCN
+ * 0b00000..Once per electrode
+ * 0b00001..Twice per electrode
+ * 0b00010..3 times per electrode
+ * 0b00011..4 times per electrode
+ * 0b00100..5 times per electrode
+ * 0b00101..6 times per electrode
+ * 0b00110..7 times per electrode
+ * 0b00111..8 times per electrode
+ * 0b01000..9 times per electrode
+ * 0b01001..10 times per electrode
+ * 0b01010..11 times per electrode
+ * 0b01011..12 times per electrode
+ * 0b01100..13 times per electrode
+ * 0b01101..14 times per electrode
+ * 0b01110..15 times per electrode
+ * 0b01111..16 times per electrode
+ * 0b10000..17 times per electrode
+ * 0b10001..18 times per electrode
+ * 0b10010..19 times per electrode
+ * 0b10011..20 times per electrode
+ * 0b10100..21 times per electrode
+ * 0b10101..22 times per electrode
+ * 0b10110..23 times per electrode
+ * 0b10111..24 times per electrode
+ * 0b11000..25 times per electrode
+ * 0b11001..26 times per electrode
+ * 0b11010..27 times per electrode
+ * 0b11011..28 times per electrode
+ * 0b11100..29 times per electrode
+ * 0b11101..30 times per electrode
+ * 0b11110..31 times per electrode
+ * 0b11111..32 times per electrode
+ */
+#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
+#define TSI_GENCS_PS_MASK (0xE000U)
+#define TSI_GENCS_PS_SHIFT (13U)
+/*! PS - PS
+ * 0b000..Electrode Oscillator Frequency divided by 1
+ * 0b001..Electrode Oscillator Frequency divided by 2
+ * 0b010..Electrode Oscillator Frequency divided by 4
+ * 0b011..Electrode Oscillator Frequency divided by 8
+ * 0b100..Electrode Oscillator Frequency divided by 16
+ * 0b101..Electrode Oscillator Frequency divided by 32
+ * 0b110..Electrode Oscillator Frequency divided by 64
+ * 0b111..Electrode Oscillator Frequency divided by 128
+ */
+#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
+#define TSI_GENCS_EXTCHRG_MASK (0x70000U)
+#define TSI_GENCS_EXTCHRG_SHIFT (16U)
+/*! EXTCHRG - EXTCHRG
+ * 0b000..500 nA.
+ * 0b001..1 uA.
+ * 0b010..2 uA.
+ * 0b011..4 uA.
+ * 0b100..8 uA.
+ * 0b101..16 uA.
+ * 0b110..32 uA.
+ * 0b111..64 uA.
+ */
+#define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK)
+#define TSI_GENCS_DVOLT_MASK (0x180000U)
+#define TSI_GENCS_DVOLT_SHIFT (19U)
+/*! DVOLT - DVOLT
+ * 0b00..DV = 1.026 V; VP = 1.328 V; Vm = 0.302 V.
+ * 0b01..DV = 0.592 V; VP = 1.111 V; Vm = 0.519 V.
+ * 0b10..DV = 0.342 V; VP = 0.986 V; Vm = 0.644 V.
+ * 0b11..DV = 0.197 V; VP = 0.914 V; Vm = 0.716 V.
+ */
+#define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK)
+#define TSI_GENCS_REFCHRG_MASK (0xE00000U)
+#define TSI_GENCS_REFCHRG_SHIFT (21U)
+/*! REFCHRG - REFCHRG
+ * 0b000..500 nA.
+ * 0b001..1 uA.
+ * 0b010..2 uA.
+ * 0b011..4 uA.
+ * 0b100..8 uA.
+ * 0b101..16 uA.
+ * 0b110..32 uA.
+ * 0b111..64 uA.
+ */
+#define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK)
+#define TSI_GENCS_MODE_MASK (0xF000000U)
+#define TSI_GENCS_MODE_SHIFT (24U)
+/*! MODE - TSI analog modes setup and status bits.
+ * 0b0000..Set TSI in capacitive sensing(non-noise detection) mode.
+ * 0b0100..Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is disabled.
+ * 0b1000..Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is enabled to work in higher frequencies operations.
+ * 0b1100..Set TSI analog to work in automatic noise detection mode.
+ */
+#define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK)
+#define TSI_GENCS_ESOR_MASK (0x10000000U)
+#define TSI_GENCS_ESOR_SHIFT (28U)
+/*! ESOR - End-of-scan or Out-of-Range Interrupt Selection
+ * 0b0..Out-of-range interrupt is allowed.
+ * 0b1..End-of-scan interrupt is allowed.
+ */
+#define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
+#define TSI_GENCS_OUTRGF_MASK (0x80000000U)
+#define TSI_GENCS_OUTRGF_SHIFT (31U)
+#define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
+/*! @} */
+
+/*! @name DATA - TSI DATA Register */
+/*! @{ */
+#define TSI_DATA_TSICNT_MASK (0xFFFFU)
+#define TSI_DATA_TSICNT_SHIFT (0U)
+#define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK)
+#define TSI_DATA_SWTS_MASK (0x400000U)
+#define TSI_DATA_SWTS_SHIFT (22U)
+/*! SWTS - Software Trigger Start
+ * 0b0..No effect.
+ * 0b1..Start a scan to determine which channel is specified by TSI_DATA[TSICH].
+ */
+#define TSI_DATA_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK)
+#define TSI_DATA_DMAEN_MASK (0x800000U)
+#define TSI_DATA_DMAEN_SHIFT (23U)
+/*! DMAEN - DMA Transfer Enabled
+ * 0b0..Interrupt is selected when the interrupt enable bit is set and the corresponding TSI events assert.
+ * 0b1..DMA transfer request is selected when the interrupt enable bit is set and the corresponding TSI events assert.
+ */
+#define TSI_DATA_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK)
+#define TSI_DATA_TSICH_MASK (0xF0000000U)
+#define TSI_DATA_TSICH_SHIFT (28U)
+/*! TSICH - TSICH
+ * 0b0000..Channel 0.
+ * 0b0001..Channel 1.
+ * 0b0010..Channel 2.
+ * 0b0011..Channel 3.
+ * 0b0100..Channel 4.
+ * 0b0101..Channel 5.
+ * 0b0110..Channel 6.
+ * 0b0111..Channel 7.
+ * 0b1000..Channel 8.
+ * 0b1001..Channel 9.
+ * 0b1010..Channel 10.
+ * 0b1011..Channel 11.
+ * 0b1100..Channel 12.
+ * 0b1101..Channel 13.
+ * 0b1110..Channel 14.
+ * 0b1111..Channel 15.
+ */
+#define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK)
+/*! @} */
+
+/*! @name TSHD - TSI Threshold Register */
+/*! @{ */
+#define TSI_TSHD_THRESL_MASK (0xFFFFU)
+#define TSI_TSHD_THRESL_SHIFT (0U)
+#define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK)
+#define TSI_TSHD_THRESH_MASK (0xFFFF0000U)
+#define TSI_TSHD_THRESH_SHIFT (16U)
+#define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group TSI_Register_Masks */
+
+
+/* TSI - Peripheral instance base addresses */
+/** Peripheral TSI0 base address */
+#define TSI0_BASE (0x40045000u)
+/** Peripheral TSI0 base pointer */
+#define TSI0 ((TSI_Type *)TSI0_BASE)
+/** Array initializer of TSI peripheral base addresses */
+#define TSI_BASE_ADDRS { TSI0_BASE }
+/** Array initializer of TSI peripheral base pointers */
+#define TSI_BASE_PTRS { TSI0 }
+/** Interrupt vectors for the TSI peripheral type */
+#define TSI_IRQS { TSI0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group TSI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
+ __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
+ __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
+ __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
+ __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
+ __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
+ __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
+ __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
+ __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
+ __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
+ __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
+ __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
+ __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
+ __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
+ __IO uint8_t WP7816; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+ __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
+ __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
+ __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
+ __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
+ uint8_t RESERVED_2[26];
+ __IO uint8_t AP7816A_T0; /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */
+ __IO uint8_t AP7816B_T0; /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */
+ union { /* offset: 0x3C */
+ struct { /* offset: 0x3C */
+ __IO uint8_t WP7816A_T0; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
+ __IO uint8_t WP7816B_T0; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
+ } TYPE0;
+ struct { /* offset: 0x3C */
+ __IO uint8_t WP7816A_T1; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
+ __IO uint8_t WP7816B_T1; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
+ } TYPE1;
+ };
+ __IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
+ __IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
+} UART_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/*! @name BDH - UART Baud Rate Registers: High */
+/*! @{ */
+#define UART_BDH_SBR_MASK (0x1FU)
+#define UART_BDH_SBR_SHIFT (0U)
+#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
+#define UART_BDH_SBNS_MASK (0x20U)
+#define UART_BDH_SBNS_SHIFT (5U)
+/*! SBNS - Stop Bit Number Select
+ * 0b0..Data frame consists of a single stop bit.
+ * 0b1..Data frame consists of two stop bits.
+ */
+#define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK)
+#define UART_BDH_RXEDGIE_MASK (0x40U)
+#define UART_BDH_RXEDGIE_SHIFT (6U)
+/*! RXEDGIE - RxD Input Active Edge Interrupt Enable
+ * 0b0..Hardware interrupts from RXEDGIF disabled using polling.
+ * 0b1..RXEDGIF interrupt request enabled.
+ */
+#define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
+#define UART_BDH_LBKDIE_MASK (0x80U)
+#define UART_BDH_LBKDIE_SHIFT (7U)
+/*! LBKDIE - LIN Break Detect Interrupt Enable
+ * 0b0..LBKDIF interrupt requests disabled.
+ * 0b1..LBKDIF interrupt requests enabled.
+ */
+#define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
+/*! @} */
+
+/*! @name BDL - UART Baud Rate Registers: Low */
+/*! @{ */
+#define UART_BDL_SBR_MASK (0xFFU)
+#define UART_BDL_SBR_SHIFT (0U)
+#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
+/*! @} */
+
+/*! @name C1 - UART Control Register 1 */
+/*! @{ */
+#define UART_C1_PT_MASK (0x1U)
+#define UART_C1_PT_SHIFT (0U)
+/*! PT - Parity Type
+ * 0b0..Even parity.
+ * 0b1..Odd parity.
+ */
+#define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
+#define UART_C1_PE_MASK (0x2U)
+#define UART_C1_PE_SHIFT (1U)
+/*! PE - Parity Enable
+ * 0b0..Parity function disabled.
+ * 0b1..Parity function enabled.
+ */
+#define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
+#define UART_C1_ILT_MASK (0x4U)
+#define UART_C1_ILT_SHIFT (2U)
+/*! ILT - Idle Line Type Select
+ * 0b0..Idle character bit count starts after start bit.
+ * 0b1..Idle character bit count starts after stop bit.
+ */
+#define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
+#define UART_C1_WAKE_MASK (0x8U)
+#define UART_C1_WAKE_SHIFT (3U)
+/*! WAKE - Receiver Wakeup Method Select
+ * 0b0..Idle line wakeup.
+ * 0b1..Address mark wakeup.
+ */
+#define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
+#define UART_C1_M_MASK (0x10U)
+#define UART_C1_M_SHIFT (4U)
+/*! M - 9-bit or 8-bit Mode Select
+ * 0b0..Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
+ * 0b1..Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
+ */
+#define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
+#define UART_C1_RSRC_MASK (0x20U)
+#define UART_C1_RSRC_SHIFT (5U)
+/*! RSRC - Receiver Source Select
+ * 0b0..Selects internal loop back mode. The receiver input is internally connected to transmitter output.
+ * 0b1..Single wire UART mode where the receiver input is connected to the transmit pin input signal.
+ */
+#define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
+#define UART_C1_UARTSWAI_MASK (0x40U)
+#define UART_C1_UARTSWAI_SHIFT (6U)
+/*! UARTSWAI - UART Stops in Wait Mode
+ * 0b0..UART clock continues to run in Wait mode.
+ * 0b1..UART clock freezes while CPU is in Wait mode.
+ */
+#define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
+#define UART_C1_LOOPS_MASK (0x80U)
+#define UART_C1_LOOPS_SHIFT (7U)
+/*! LOOPS - Loop Mode Select
+ * 0b0..Normal operation.
+ * 0b1..Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.
+ */
+#define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
+/*! @} */
+
+/*! @name C2 - UART Control Register 2 */
+/*! @{ */
+#define UART_C2_SBK_MASK (0x1U)
+#define UART_C2_SBK_SHIFT (0U)
+/*! SBK - Send Break
+ * 0b0..Normal transmitter operation.
+ * 0b1..Queue break characters to be sent.
+ */
+#define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
+#define UART_C2_RWU_MASK (0x2U)
+#define UART_C2_RWU_SHIFT (1U)
+/*! RWU - Receiver Wakeup Control
+ * 0b0..Normal operation.
+ * 0b1..RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.
+ */
+#define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
+#define UART_C2_RE_MASK (0x4U)
+#define UART_C2_RE_SHIFT (2U)
+/*! RE - Receiver Enable
+ * 0b0..Receiver off.
+ * 0b1..Receiver on.
+ */
+#define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
+#define UART_C2_TE_MASK (0x8U)
+#define UART_C2_TE_SHIFT (3U)
+/*! TE - Transmitter Enable
+ * 0b0..Transmitter off.
+ * 0b1..Transmitter on.
+ */
+#define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
+#define UART_C2_ILIE_MASK (0x10U)
+#define UART_C2_ILIE_SHIFT (4U)
+/*! ILIE - Idle Line Interrupt Enable
+ * 0b0..IDLE interrupt requests disabled.
+ * 0b1..IDLE interrupt requests enabled.
+ */
+#define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
+#define UART_C2_RIE_MASK (0x20U)
+#define UART_C2_RIE_SHIFT (5U)
+/*! RIE - Receiver Full Interrupt or DMA Transfer Enable
+ * 0b0..RDRF interrupt and DMA transfer requests disabled.
+ * 0b1..RDRF interrupt or DMA transfer requests enabled.
+ */
+#define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
+#define UART_C2_TCIE_MASK (0x40U)
+#define UART_C2_TCIE_SHIFT (6U)
+/*! TCIE - Transmission Complete Interrupt Enable
+ * 0b0..TC interrupt requests disabled.
+ * 0b1..TC interrupt requests enabled.
+ */
+#define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
+#define UART_C2_TIE_MASK (0x80U)
+#define UART_C2_TIE_SHIFT (7U)
+/*! TIE - Transmitter Interrupt or DMA Transfer Enable.
+ * 0b0..TDRE interrupt and DMA transfer requests disabled.
+ * 0b1..TDRE interrupt or DMA transfer requests enabled.
+ */
+#define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
+/*! @} */
+
+/*! @name S1 - UART Status Register 1 */
+/*! @{ */
+#define UART_S1_PF_MASK (0x1U)
+#define UART_S1_PF_SHIFT (0U)
+/*! PF - Parity Error Flag
+ * 0b0..No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error.
+ * 0b1..At least one dataword was received with a parity error since the last time this flag was cleared.
+ */
+#define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
+#define UART_S1_FE_MASK (0x2U)
+#define UART_S1_FE_SHIFT (1U)
+/*! FE - Framing Error Flag
+ * 0b0..No framing error detected.
+ * 0b1..Framing error.
+ */
+#define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
+#define UART_S1_NF_MASK (0x4U)
+#define UART_S1_NF_SHIFT (2U)
+/*! NF - Noise Flag
+ * 0b0..No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.
+ * 0b1..At least one dataword was received with noise detected since the last time the flag was cleared.
+ */
+#define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
+#define UART_S1_OR_MASK (0x8U)
+#define UART_S1_OR_SHIFT (3U)
+/*! OR - Receiver Overrun Flag
+ * 0b0..No overrun has occurred since the last time the flag was cleared.
+ * 0b1..Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.
+ */
+#define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
+#define UART_S1_IDLE_MASK (0x10U)
+#define UART_S1_IDLE_SHIFT (4U)
+/*! IDLE - Idle Line Flag
+ * 0b0..Receiver input is either active now or has never become active since the IDLE flag was last cleared.
+ * 0b1..Receiver input has become idle or the flag has not been cleared since it last asserted.
+ */
+#define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
+#define UART_S1_RDRF_MASK (0x20U)
+#define UART_S1_RDRF_SHIFT (5U)
+/*! RDRF - Receive Data Register Full Flag
+ * 0b0..The number of datawords in the receive buffer is less than the number indicated by RXWATER.
+ * 0b1..The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.
+ */
+#define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
+#define UART_S1_TC_MASK (0x40U)
+#define UART_S1_TC_SHIFT (6U)
+/*! TC - Transmit Complete Flag
+ * 0b0..Transmitter active (sending data, a preamble, or a break).
+ * 0b1..Transmitter idle (transmission activity complete).
+ */
+#define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
+#define UART_S1_TDRE_MASK (0x80U)
+#define UART_S1_TDRE_SHIFT (7U)
+/*! TDRE - Transmit Data Register Empty Flag
+ * 0b0..The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].
+ * 0b1..The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.
+ */
+#define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
+/*! @} */
+
+/*! @name S2 - UART Status Register 2 */
+/*! @{ */
+#define UART_S2_RAF_MASK (0x1U)
+#define UART_S2_RAF_SHIFT (0U)
+/*! RAF - Receiver Active Flag
+ * 0b0..UART receiver idle/inactive waiting for a start bit.
+ * 0b1..UART receiver active, RxD input not idle.
+ */
+#define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
+#define UART_S2_LBKDE_MASK (0x2U)
+#define UART_S2_LBKDE_SHIFT (1U)
+/*! LBKDE - LIN Break Detection Enable
+ * 0b0..Break character detection is disabled.
+ * 0b1..Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1.
+ */
+#define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
+#define UART_S2_BRK13_MASK (0x4U)
+#define UART_S2_BRK13_SHIFT (2U)
+/*! BRK13 - Break Transmit Character Length
+ * 0b0..Break character is 10, 11, or 12 bits long.
+ * 0b1..Break character is 13 or 14 bits long.
+ */
+#define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
+#define UART_S2_RWUID_MASK (0x8U)
+#define UART_S2_RWUID_SHIFT (3U)
+/*! RWUID - Receive Wakeup Idle Detect
+ * 0b0..S1[IDLE] is not set upon detection of an idle character.
+ * 0b1..S1[IDLE] is set upon detection of an idle character.
+ */
+#define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
+#define UART_S2_RXINV_MASK (0x10U)
+#define UART_S2_RXINV_SHIFT (4U)
+/*! RXINV - Receive Data Inversion
+ * 0b0..Receive data is not inverted.
+ * 0b1..Receive data is inverted.
+ */
+#define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
+#define UART_S2_MSBF_MASK (0x20U)
+#define UART_S2_MSBF_SHIFT (5U)
+/*! MSBF - Most Significant Bit First
+ * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
+ * 0b1..MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE].
+ */
+#define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK)
+#define UART_S2_RXEDGIF_MASK (0x40U)
+#define UART_S2_RXEDGIF_SHIFT (6U)
+/*! RXEDGIF - RxD Pin Active Edge Interrupt Flag
+ * 0b0..No active edge on the receive pin has occurred.
+ * 0b1..An active edge on the receive pin has occurred.
+ */
+#define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
+#define UART_S2_LBKDIF_MASK (0x80U)
+#define UART_S2_LBKDIF_SHIFT (7U)
+/*! LBKDIF - LIN Break Detect Interrupt Flag
+ * 0b0..No LIN break character detected.
+ * 0b1..LIN break character detected.
+ */
+#define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
+/*! @} */
+
+/*! @name C3 - UART Control Register 3 */
+/*! @{ */
+#define UART_C3_PEIE_MASK (0x1U)
+#define UART_C3_PEIE_SHIFT (0U)
+/*! PEIE - Parity Error Interrupt Enable
+ * 0b0..PF interrupt requests are disabled.
+ * 0b1..PF interrupt requests are enabled.
+ */
+#define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
+#define UART_C3_FEIE_MASK (0x2U)
+#define UART_C3_FEIE_SHIFT (1U)
+/*! FEIE - Framing Error Interrupt Enable
+ * 0b0..FE interrupt requests are disabled.
+ * 0b1..FE interrupt requests are enabled.
+ */
+#define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
+#define UART_C3_NEIE_MASK (0x4U)
+#define UART_C3_NEIE_SHIFT (2U)
+/*! NEIE - Noise Error Interrupt Enable
+ * 0b0..NF interrupt requests are disabled.
+ * 0b1..NF interrupt requests are enabled.
+ */
+#define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
+#define UART_C3_ORIE_MASK (0x8U)
+#define UART_C3_ORIE_SHIFT (3U)
+/*! ORIE - Overrun Error Interrupt Enable
+ * 0b0..OR interrupts are disabled.
+ * 0b1..OR interrupt requests are enabled.
+ */
+#define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
+#define UART_C3_TXINV_MASK (0x10U)
+#define UART_C3_TXINV_SHIFT (4U)
+/*! TXINV - Transmit Data Inversion.
+ * 0b0..Transmit data is not inverted.
+ * 0b1..Transmit data is inverted.
+ */
+#define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
+#define UART_C3_TXDIR_MASK (0x20U)
+#define UART_C3_TXDIR_SHIFT (5U)
+/*! TXDIR - Transmitter Pin Data Direction in Single-Wire mode
+ * 0b0..TXD pin is an input in single wire mode.
+ * 0b1..TXD pin is an output in single wire mode.
+ */
+#define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
+#define UART_C3_T8_MASK (0x40U)
+#define UART_C3_T8_SHIFT (6U)
+#define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
+#define UART_C3_R8_MASK (0x80U)
+#define UART_C3_R8_SHIFT (7U)
+#define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
+/*! @} */
+
+/*! @name D - UART Data Register */
+/*! @{ */
+#define UART_D_RT_MASK (0xFFU)
+#define UART_D_RT_SHIFT (0U)
+#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK)
+/*! @} */
+
+/*! @name MA1 - UART Match Address Registers 1 */
+/*! @{ */
+#define UART_MA1_MA_MASK (0xFFU)
+#define UART_MA1_MA_SHIFT (0U)
+#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK)
+/*! @} */
+
+/*! @name MA2 - UART Match Address Registers 2 */
+/*! @{ */
+#define UART_MA2_MA_MASK (0xFFU)
+#define UART_MA2_MA_SHIFT (0U)
+#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK)
+/*! @} */
+
+/*! @name C4 - UART Control Register 4 */
+/*! @{ */
+#define UART_C4_BRFA_MASK (0x1FU)
+#define UART_C4_BRFA_SHIFT (0U)
+#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK (0x20U)
+#define UART_C4_M10_SHIFT (5U)
+/*! M10 - 10-bit Mode select
+ * 0b0..The parity bit is the ninth bit in the serial transmission.
+ * 0b1..The parity bit is the tenth bit in the serial transmission.
+ */
+#define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK)
+#define UART_C4_MAEN2_MASK (0x40U)
+#define UART_C4_MAEN2_SHIFT (6U)
+/*! MAEN2 - Match Address Mode Enable 2
+ * 0b0..All data received is transferred to the data buffer if MAEN1 is cleared.
+ * 0b1..All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
+ */
+#define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK)
+#define UART_C4_MAEN1_MASK (0x80U)
+#define UART_C4_MAEN1_SHIFT (7U)
+/*! MAEN1 - Match Address Mode Enable 1
+ * 0b0..All data received is transferred to the data buffer if MAEN2 is cleared.
+ * 0b1..All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
+ */
+#define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK)
+/*! @} */
+
+/*! @name C5 - UART Control Register 5 */
+/*! @{ */
+#define UART_C5_RDMAS_MASK (0x20U)
+#define UART_C5_RDMAS_SHIFT (5U)
+/*! RDMAS - Receiver Full DMA Select
+ * 0b0..If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.
+ * 0b1..If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.
+ */
+#define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK)
+#define UART_C5_TDMAS_MASK (0x80U)
+#define UART_C5_TDMAS_SHIFT (7U)
+/*! TDMAS - Transmitter DMA Select
+ * 0b0..If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.
+ * 0b1..If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.
+ */
+#define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK)
+/*! @} */
+
+/*! @name ED - UART Extended Data Register */
+/*! @{ */
+#define UART_ED_PARITYE_MASK (0x40U)
+#define UART_ED_PARITYE_SHIFT (6U)
+/*! PARITYE
+ * 0b0..The dataword was received without a parity error.
+ * 0b1..The dataword was received with a parity error.
+ */
+#define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK)
+#define UART_ED_NOISY_MASK (0x80U)
+#define UART_ED_NOISY_SHIFT (7U)
+/*! NOISY
+ * 0b0..The dataword was received without noise.
+ * 0b1..The data was received with noise.
+ */
+#define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK)
+/*! @} */
+
+/*! @name MODEM - UART Modem Register */
+/*! @{ */
+#define UART_MODEM_TXCTSE_MASK (0x1U)
+#define UART_MODEM_TXCTSE_SHIFT (0U)
+/*! TXCTSE - Transmitter clear-to-send enable
+ * 0b0..CTS has no effect on the transmitter.
+ * 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
+ */
+#define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK)
+#define UART_MODEM_TXRTSE_MASK (0x2U)
+#define UART_MODEM_TXRTSE_SHIFT (1U)
+/*! TXRTSE - Transmitter request-to-send enable
+ * 0b0..The transmitter has no effect on RTS.
+ * 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO)
+ */
+#define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK)
+#define UART_MODEM_TXRTSPOL_MASK (0x4U)
+#define UART_MODEM_TXRTSPOL_SHIFT (2U)
+/*! TXRTSPOL - Transmitter request-to-send polarity
+ * 0b0..Transmitter RTS is active low.
+ * 0b1..Transmitter RTS is active high.
+ */
+#define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK)
+#define UART_MODEM_RXRTSE_MASK (0x8U)
+#define UART_MODEM_RXRTSE_SHIFT (3U)
+/*! RXRTSE - Receiver request-to-send enable
+ * 0b0..The receiver has no effect on RTS.
+ * 0b1..RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. See Hardware flow control
+ */
+#define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK)
+/*! @} */
+
+/*! @name IR - UART Infrared Register */
+/*! @{ */
+#define UART_IR_TNP_MASK (0x3U)
+#define UART_IR_TNP_SHIFT (0U)
+/*! TNP - Transmitter narrow pulse
+ * 0b00..3/16.
+ * 0b01..1/16.
+ * 0b10..1/32.
+ * 0b11..1/4.
+ */
+#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK)
+#define UART_IR_IREN_MASK (0x4U)
+#define UART_IR_IREN_SHIFT (2U)
+/*! IREN - Infrared enable
+ * 0b0..IR disabled.
+ * 0b1..IR enabled.
+ */
+#define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK)
+/*! @} */
+
+/*! @name PFIFO - UART FIFO Parameters */
+/*! @{ */
+#define UART_PFIFO_RXFIFOSIZE_MASK (0x7U)
+#define UART_PFIFO_RXFIFOSIZE_SHIFT (0U)
+/*! RXFIFOSIZE - Receive FIFO. Buffer Depth
+ * 0b000..Receive FIFO/Buffer depth = 1 dataword.
+ * 0b001..Receive FIFO/Buffer depth = 4 datawords.
+ * 0b010..Receive FIFO/Buffer depth = 8 datawords.
+ * 0b011..Receive FIFO/Buffer depth = 16 datawords.
+ * 0b100..Receive FIFO/Buffer depth = 32 datawords.
+ * 0b101..Receive FIFO/Buffer depth = 64 datawords.
+ * 0b110..Receive FIFO/Buffer depth = 128 datawords.
+ * 0b111..Reserved.
+ */
+#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK)
+#define UART_PFIFO_RXFE_MASK (0x8U)
+#define UART_PFIFO_RXFE_SHIFT (3U)
+/*! RXFE - Receive FIFO Enable
+ * 0b0..Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
+ * 0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
+ */
+#define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK)
+#define UART_PFIFO_TXFIFOSIZE_MASK (0x70U)
+#define UART_PFIFO_TXFIFOSIZE_SHIFT (4U)
+/*! TXFIFOSIZE - Transmit FIFO. Buffer Depth
+ * 0b000..Transmit FIFO/Buffer depth = 1 dataword.
+ * 0b001..Transmit FIFO/Buffer depth = 4 datawords.
+ * 0b010..Transmit FIFO/Buffer depth = 8 datawords.
+ * 0b011..Transmit FIFO/Buffer depth = 16 datawords.
+ * 0b100..Transmit FIFO/Buffer depth = 32 datawords.
+ * 0b101..Transmit FIFO/Buffer depth = 64 datawords.
+ * 0b110..Transmit FIFO/Buffer depth = 128 datawords.
+ * 0b111..Reserved.
+ */
+#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK)
+#define UART_PFIFO_TXFE_MASK (0x80U)
+#define UART_PFIFO_TXFE_SHIFT (7U)
+/*! TXFE - Transmit FIFO Enable
+ * 0b0..Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
+ * 0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
+ */
+#define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK)
+/*! @} */
+
+/*! @name CFIFO - UART FIFO Control Register */
+/*! @{ */
+#define UART_CFIFO_RXUFE_MASK (0x1U)
+#define UART_CFIFO_RXUFE_SHIFT (0U)
+/*! RXUFE - Receive FIFO Underflow Interrupt Enable
+ * 0b0..RXUF flag does not generate an interrupt to the host.
+ * 0b1..RXUF flag generates an interrupt to the host.
+ */
+#define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK)
+#define UART_CFIFO_TXOFE_MASK (0x2U)
+#define UART_CFIFO_TXOFE_SHIFT (1U)
+/*! TXOFE - Transmit FIFO Overflow Interrupt Enable
+ * 0b0..TXOF flag does not generate an interrupt to the host.
+ * 0b1..TXOF flag generates an interrupt to the host.
+ */
+#define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK)
+#define UART_CFIFO_RXOFE_MASK (0x4U)
+#define UART_CFIFO_RXOFE_SHIFT (2U)
+/*! RXOFE - Receive FIFO Overflow Interrupt Enable
+ * 0b0..RXOF flag does not generate an interrupt to the host.
+ * 0b1..RXOF flag generates an interrupt to the host.
+ */
+#define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK)
+#define UART_CFIFO_RXFLUSH_MASK (0x40U)
+#define UART_CFIFO_RXFLUSH_SHIFT (6U)
+/*! RXFLUSH - Receive FIFO/Buffer Flush
+ * 0b0..No flush operation occurs.
+ * 0b1..All data in the receive FIFO/buffer is cleared out.
+ */
+#define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK)
+#define UART_CFIFO_TXFLUSH_MASK (0x80U)
+#define UART_CFIFO_TXFLUSH_SHIFT (7U)
+/*! TXFLUSH - Transmit FIFO/Buffer Flush
+ * 0b0..No flush operation occurs.
+ * 0b1..All data in the transmit FIFO/Buffer is cleared out.
+ */
+#define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK)
+/*! @} */
+
+/*! @name SFIFO - UART FIFO Status Register */
+/*! @{ */
+#define UART_SFIFO_RXUF_MASK (0x1U)
+#define UART_SFIFO_RXUF_SHIFT (0U)
+/*! RXUF - Receiver Buffer Underflow Flag
+ * 0b0..No receive buffer underflow has occurred since the last time the flag was cleared.
+ * 0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared.
+ */
+#define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK)
+#define UART_SFIFO_TXOF_MASK (0x2U)
+#define UART_SFIFO_TXOF_SHIFT (1U)
+/*! TXOF - Transmitter Buffer Overflow Flag
+ * 0b0..No transmit buffer overflow has occurred since the last time the flag was cleared.
+ * 0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared.
+ */
+#define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK)
+#define UART_SFIFO_RXOF_MASK (0x4U)
+#define UART_SFIFO_RXOF_SHIFT (2U)
+/*! RXOF - Receiver Buffer Overflow Flag
+ * 0b0..No receive buffer overflow has occurred since the last time the flag was cleared.
+ * 0b1..At least one receive buffer overflow has occurred since the last time the flag was cleared.
+ */
+#define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK)
+#define UART_SFIFO_RXEMPT_MASK (0x40U)
+#define UART_SFIFO_RXEMPT_SHIFT (6U)
+/*! RXEMPT - Receive Buffer/FIFO Empty
+ * 0b0..Receive buffer is not empty.
+ * 0b1..Receive buffer is empty.
+ */
+#define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK)
+#define UART_SFIFO_TXEMPT_MASK (0x80U)
+#define UART_SFIFO_TXEMPT_SHIFT (7U)
+/*! TXEMPT - Transmit Buffer/FIFO Empty
+ * 0b0..Transmit buffer is not empty.
+ * 0b1..Transmit buffer is empty.
+ */
+#define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK)
+/*! @} */
+
+/*! @name TWFIFO - UART FIFO Transmit Watermark */
+/*! @{ */
+#define UART_TWFIFO_TXWATER_MASK (0xFFU)
+#define UART_TWFIFO_TXWATER_SHIFT (0U)
+#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK)
+/*! @} */
+
+/*! @name TCFIFO - UART FIFO Transmit Count */
+/*! @{ */
+#define UART_TCFIFO_TXCOUNT_MASK (0xFFU)
+#define UART_TCFIFO_TXCOUNT_SHIFT (0U)
+#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK)
+/*! @} */
+
+/*! @name RWFIFO - UART FIFO Receive Watermark */
+/*! @{ */
+#define UART_RWFIFO_RXWATER_MASK (0xFFU)
+#define UART_RWFIFO_RXWATER_SHIFT (0U)
+#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK)
+/*! @} */
+
+/*! @name RCFIFO - UART FIFO Receive Count */
+/*! @{ */
+#define UART_RCFIFO_RXCOUNT_MASK (0xFFU)
+#define UART_RCFIFO_RXCOUNT_SHIFT (0U)
+#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK)
+/*! @} */
+
+/*! @name C7816 - UART 7816 Control Register */
+/*! @{ */
+#define UART_C7816_ISO_7816E_MASK (0x1U)
+#define UART_C7816_ISO_7816E_SHIFT (0U)
+/*! ISO_7816E - ISO-7816 Functionality Enabled
+ * 0b0..ISO-7816 functionality is turned off/not enabled.
+ * 0b1..ISO-7816 functionality is turned on/enabled.
+ */
+#define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK)
+#define UART_C7816_TTYPE_MASK (0x2U)
+#define UART_C7816_TTYPE_SHIFT (1U)
+/*! TTYPE - Transfer Type
+ * 0b0..T = 0 per the ISO-7816 specification.
+ * 0b1..T = 1 per the ISO-7816 specification.
+ */
+#define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK)
+#define UART_C7816_INIT_MASK (0x4U)
+#define UART_C7816_INIT_SHIFT (2U)
+/*! INIT - Detect Initial Character
+ * 0b0..Normal operating mode. Receiver does not seek to identify initial character.
+ * 0b1..Receiver searches for initial character.
+ */
+#define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK)
+#define UART_C7816_ANACK_MASK (0x8U)
+#define UART_C7816_ANACK_SHIFT (3U)
+/*! ANACK - Generate NACK on Error
+ * 0b0..No NACK is automatically generated.
+ * 0b1..A NACK is automatically generated if a parity error is detected or if an invalid initial character is detected.
+ */
+#define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK)
+#define UART_C7816_ONACK_MASK (0x10U)
+#define UART_C7816_ONACK_SHIFT (4U)
+/*! ONACK - Generate NACK on Overflow
+ * 0b0..The received data does not generate a NACK when the receipt of the data results in an overflow event.
+ * 0b1..If the receiver buffer overflows, a NACK is automatically sent on a received character.
+ */
+#define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK)
+/*! @} */
+
+/*! @name IE7816 - UART 7816 Interrupt Enable Register */
+/*! @{ */
+#define UART_IE7816_RXTE_MASK (0x1U)
+#define UART_IE7816_RXTE_SHIFT (0U)
+/*! RXTE - Receive Threshold Exceeded Interrupt Enable
+ * 0b0..The assertion of IS7816[RXT] does not result in the generation of an interrupt.
+ * 0b1..The assertion of IS7816[RXT] results in the generation of an interrupt.
+ */
+#define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK)
+#define UART_IE7816_TXTE_MASK (0x2U)
+#define UART_IE7816_TXTE_SHIFT (1U)
+/*! TXTE - Transmit Threshold Exceeded Interrupt Enable
+ * 0b0..The assertion of IS7816[TXT] does not result in the generation of an interrupt.
+ * 0b1..The assertion of IS7816[TXT] results in the generation of an interrupt.
+ */
+#define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK)
+#define UART_IE7816_GTVE_MASK (0x4U)
+#define UART_IE7816_GTVE_SHIFT (2U)
+/*! GTVE - Guard Timer Violated Interrupt Enable
+ * 0b0..The assertion of IS7816[GTV] does not result in the generation of an interrupt.
+ * 0b1..The assertion of IS7816[GTV] results in the generation of an interrupt.
+ */
+#define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK)
+#define UART_IE7816_ADTE_MASK (0x8U)
+#define UART_IE7816_ADTE_SHIFT (3U)
+/*! ADTE - ATR Duration Timer Interrupt Enable
+ * 0b0..The assertion of IS7816[ADT] does not result in the generation of an interrupt.
+ * 0b1..The assertion of IS7816[ADT] results in the generation of an interrupt.
+ */
+#define UART_IE7816_ADTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_ADTE_SHIFT)) & UART_IE7816_ADTE_MASK)
+#define UART_IE7816_INITDE_MASK (0x10U)
+#define UART_IE7816_INITDE_SHIFT (4U)
+/*! INITDE - Initial Character Detected Interrupt Enable
+ * 0b0..The assertion of IS7816[INITD] does not result in the generation of an interrupt.
+ * 0b1..The assertion of IS7816[INITD] results in the generation of an interrupt.
+ */
+#define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK)
+#define UART_IE7816_BWTE_MASK (0x20U)
+#define UART_IE7816_BWTE_SHIFT (5U)
+/*! BWTE - Block Wait Timer Interrupt Enable
+ * 0b0..The assertion of IS7816[BWT] does not result in the generation of an interrupt.
+ * 0b1..The assertion of IS7816[BWT] results in the generation of an interrupt.
+ */
+#define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK)
+#define UART_IE7816_CWTE_MASK (0x40U)
+#define UART_IE7816_CWTE_SHIFT (6U)
+/*! CWTE - Character Wait Timer Interrupt Enable
+ * 0b0..The assertion of IS7816[CWT] does not result in the generation of an interrupt.
+ * 0b1..The assertion of IS7816[CWT] results in the generation of an interrupt.
+ */
+#define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK)
+#define UART_IE7816_WTE_MASK (0x80U)
+#define UART_IE7816_WTE_SHIFT (7U)
+/*! WTE - Wait Timer Interrupt Enable
+ * 0b0..The assertion of IS7816[WT] does not result in the generation of an interrupt.
+ * 0b1..The assertion of IS7816[WT] results in the generation of an interrupt.
+ */
+#define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK)
+/*! @} */
+
+/*! @name IS7816 - UART 7816 Interrupt Status Register */
+/*! @{ */
+#define UART_IS7816_RXT_MASK (0x1U)
+#define UART_IS7816_RXT_SHIFT (0U)
+/*! RXT - Receive Threshold Exceeded Interrupt
+ * 0b0..The number of consecutive NACKS generated as a result of parity errors and buffer overruns is less than or equal to the value in ET7816[RXTHRESHOLD].
+ * 0b1..The number of consecutive NACKS generated as a result of parity errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].
+ */
+#define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK)
+#define UART_IS7816_TXT_MASK (0x2U)
+#define UART_IS7816_TXT_SHIFT (1U)
+/*! TXT - Transmit Threshold Exceeded Interrupt
+ * 0b0..The number of retries and corresponding NACKS does not exceed the value in ET7816[TXTHRESHOLD].
+ * 0b1..The number of retries and corresponding NACKS exceeds the value in ET7816[TXTHRESHOLD].
+ */
+#define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK)
+#define UART_IS7816_GTV_MASK (0x4U)
+#define UART_IS7816_GTV_SHIFT (2U)
+/*! GTV - Guard Timer Violated Interrupt
+ * 0b0..A guard time (GT, CGT, or BGT) has not been violated.
+ * 0b1..A guard time (GT, CGT, or BGT) has been violated.
+ */
+#define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK)
+#define UART_IS7816_ADT_MASK (0x8U)
+#define UART_IS7816_ADT_SHIFT (3U)
+/*! ADT - ATR Duration Time Interrupt
+ * 0b0..ATR Duration time (ADT) has not been violated.
+ * 0b1..ATR Duration time (ADT) has been violated.
+ */
+#define UART_IS7816_ADT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_ADT_SHIFT)) & UART_IS7816_ADT_MASK)
+#define UART_IS7816_INITD_MASK (0x10U)
+#define UART_IS7816_INITD_SHIFT (4U)
+/*! INITD - Initial Character Detected Interrupt
+ * 0b0..A valid initial character has not been received.
+ * 0b1..A valid initial character has been received.
+ */
+#define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK)
+#define UART_IS7816_BWT_MASK (0x20U)
+#define UART_IS7816_BWT_SHIFT (5U)
+/*! BWT - Block Wait Timer Interrupt
+ * 0b0..Block wait time (BWT) has not been violated.
+ * 0b1..Block wait time (BWT) has been violated.
+ */
+#define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK)
+#define UART_IS7816_CWT_MASK (0x40U)
+#define UART_IS7816_CWT_SHIFT (6U)
+/*! CWT - Character Wait Timer Interrupt
+ * 0b0..Character wait time (CWT) has not been violated.
+ * 0b1..Character wait time (CWT) has been violated.
+ */
+#define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK)
+#define UART_IS7816_WT_MASK (0x80U)
+#define UART_IS7816_WT_SHIFT (7U)
+/*! WT - Wait Timer Interrupt
+ * 0b0..Wait time (WT) has not been violated.
+ * 0b1..Wait time (WT) has been violated.
+ */
+#define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK)
+/*! @} */
+
+/*! @name WP7816 - UART 7816 Wait Parameter Register */
+/*! @{ */
+#define UART_WP7816_WTX_MASK (0xFFU)
+#define UART_WP7816_WTX_SHIFT (0U)
+#define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816_WTX_SHIFT)) & UART_WP7816_WTX_MASK)
+/*! @} */
+
+/*! @name WN7816 - UART 7816 Wait N Register */
+/*! @{ */
+#define UART_WN7816_GTN_MASK (0xFFU)
+#define UART_WN7816_GTN_SHIFT (0U)
+#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
+/*! @} */
+
+/*! @name WF7816 - UART 7816 Wait FD Register */
+/*! @{ */
+#define UART_WF7816_GTFD_MASK (0xFFU)
+#define UART_WF7816_GTFD_SHIFT (0U)
+#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
+/*! @} */
+
+/*! @name ET7816 - UART 7816 Error Threshold Register */
+/*! @{ */
+#define UART_ET7816_RXTHRESHOLD_MASK (0xFU)
+#define UART_ET7816_RXTHRESHOLD_SHIFT (0U)
+#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK (0xF0U)
+#define UART_ET7816_TXTHRESHOLD_SHIFT (4U)
+/*! TXTHRESHOLD - Transmit NACK Threshold
+ * 0b0000..TXT asserts on the first NACK that is received.
+ * 0b0001..TXT asserts on the second NACK that is received.
+ */
+#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
+/*! @} */
+
+/*! @name TL7816 - UART 7816 Transmit Length Register */
+/*! @{ */
+#define UART_TL7816_TLEN_MASK (0xFFU)
+#define UART_TL7816_TLEN_SHIFT (0U)
+#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
+/*! @} */
+
+/*! @name AP7816A_T0 - UART 7816 ATR Duration Timer Register A */
+/*! @{ */
+#define UART_AP7816A_T0_ADTI_H_MASK (0xFFU)
+#define UART_AP7816A_T0_ADTI_H_SHIFT (0U)
+#define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816A_T0_ADTI_H_SHIFT)) & UART_AP7816A_T0_ADTI_H_MASK)
+/*! @} */
+
+/*! @name AP7816B_T0 - UART 7816 ATR Duration Timer Register B */
+/*! @{ */
+#define UART_AP7816B_T0_ADTI_L_MASK (0xFFU)
+#define UART_AP7816B_T0_ADTI_L_SHIFT (0U)
+#define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816B_T0_ADTI_L_SHIFT)) & UART_AP7816B_T0_ADTI_L_MASK)
+/*! @} */
+
+/*! @name WP7816A_T0 - UART 7816 Wait Parameter Register A */
+/*! @{ */
+#define UART_WP7816A_T0_WI_H_MASK (0xFFU)
+#define UART_WP7816A_T0_WI_H_SHIFT (0U)
+#define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T0_WI_H_SHIFT)) & UART_WP7816A_T0_WI_H_MASK)
+/*! @} */
+
+/*! @name WP7816B_T0 - UART 7816 Wait Parameter Register B */
+/*! @{ */
+#define UART_WP7816B_T0_WI_L_MASK (0xFFU)
+#define UART_WP7816B_T0_WI_L_SHIFT (0U)
+#define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T0_WI_L_SHIFT)) & UART_WP7816B_T0_WI_L_MASK)
+/*! @} */
+
+/*! @name WP7816A_T1 - UART 7816 Wait Parameter Register A */
+/*! @{ */
+#define UART_WP7816A_T1_BWI_H_MASK (0xFFU)
+#define UART_WP7816A_T1_BWI_H_SHIFT (0U)
+#define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T1_BWI_H_SHIFT)) & UART_WP7816A_T1_BWI_H_MASK)
+/*! @} */
+
+/*! @name WP7816B_T1 - UART 7816 Wait Parameter Register B */
+/*! @{ */
+#define UART_WP7816B_T1_BWI_L_MASK (0xFFU)
+#define UART_WP7816B_T1_BWI_L_SHIFT (0U)
+#define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T1_BWI_L_SHIFT)) & UART_WP7816B_T1_BWI_L_MASK)
+/*! @} */
+
+/*! @name WGP7816_T1 - UART 7816 Wait and Guard Parameter Register */
+/*! @{ */
+#define UART_WGP7816_T1_BGI_MASK (0xFU)
+#define UART_WGP7816_T1_BGI_SHIFT (0U)
+#define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_BGI_SHIFT)) & UART_WGP7816_T1_BGI_MASK)
+#define UART_WGP7816_T1_CWI1_MASK (0xF0U)
+#define UART_WGP7816_T1_CWI1_SHIFT (4U)
+#define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_CWI1_SHIFT)) & UART_WGP7816_T1_CWI1_MASK)
+/*! @} */
+
+/*! @name WP7816C_T1 - UART 7816 Wait Parameter Register C */
+/*! @{ */
+#define UART_WP7816C_T1_CWI2_MASK (0x1FU)
+#define UART_WP7816C_T1_CWI2_SHIFT (0U)
+#define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816C_T1_CWI2_SHIFT)) & UART_WP7816C_T1_CWI2_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0 ((UART_Type *)UART0_BASE)
+/** Peripheral UART1 base address */
+#define UART1_BASE (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1 ((UART_Type *)UART1_BASE)
+/** Peripheral UART2 base address */
+#define UART2_BASE (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2 ((UART_Type *)UART2_BASE)
+/** Peripheral UART3 base address */
+#define UART3_BASE (0x4006D000u)
+/** Peripheral UART3 base pointer */
+#define UART3 ((UART_Type *)UART3_BASE)
+/** Peripheral UART4 base address */
+#define UART4_BASE (0x400EA000u)
+/** Peripheral UART4 base pointer */
+#define UART4 ((UART_Type *)UART4_BASE)
+/** Array initializer of UART peripheral base addresses */
+#define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE }
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASE_PTRS { UART0, UART1, UART2, UART3, UART4 }
+/** Interrupt vectors for the UART peripheral type */
+#define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn }
+#define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn }
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+ __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
+ uint8_t RESERVED_0[3];
+ __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
+ uint8_t RESERVED_1[3];
+ __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
+ uint8_t RESERVED_2[3];
+ __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
+ uint8_t RESERVED_3[3];
+ __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
+ uint8_t RESERVED_4[3];
+ __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
+ uint8_t RESERVED_5[3];
+ __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
+ uint8_t RESERVED_6[3];
+ __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
+ uint8_t RESERVED_7[99];
+ __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
+ uint8_t RESERVED_8[3];
+ __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
+ uint8_t RESERVED_9[3];
+ __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
+ uint8_t RESERVED_10[3];
+ __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
+ uint8_t RESERVED_11[3];
+ __I uint8_t STAT; /**< Status register, offset: 0x90 */
+ uint8_t RESERVED_12[3];
+ __IO uint8_t CTL; /**< Control register, offset: 0x94 */
+ uint8_t RESERVED_13[3];
+ __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
+ uint8_t RESERVED_14[3];
+ __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
+ uint8_t RESERVED_15[3];
+ __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
+ uint8_t RESERVED_16[3];
+ __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
+ uint8_t RESERVED_17[3];
+ __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
+ uint8_t RESERVED_18[3];
+ __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
+ uint8_t RESERVED_19[3];
+ __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
+ uint8_t RESERVED_20[3];
+ __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
+ uint8_t RESERVED_21[11];
+ struct { /* offset: 0xC0, array step: 0x4 */
+ __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_0[3];
+ } ENDPOINT[16];
+ __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
+ uint8_t RESERVED_22[3];
+ __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
+ uint8_t RESERVED_23[3];
+ __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
+ uint8_t RESERVED_24[3];
+ __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
+ uint8_t RESERVED_25[7];
+ __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
+ uint8_t RESERVED_26[43];
+ __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
+ uint8_t RESERVED_27[3];
+ __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
+ uint8_t RESERVED_28[15];
+ __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */
+ uint8_t RESERVED_29[7];
+ __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
+} USB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/*! @name PERID - Peripheral ID register */
+/*! @{ */
+#define USB_PERID_ID_MASK (0x3FU)
+#define USB_PERID_ID_SHIFT (0U)
+#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
+/*! @} */
+
+/*! @name IDCOMP - Peripheral ID Complement register */
+/*! @{ */
+#define USB_IDCOMP_NID_MASK (0x3FU)
+#define USB_IDCOMP_NID_SHIFT (0U)
+#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
+/*! @} */
+
+/*! @name REV - Peripheral Revision register */
+/*! @{ */
+#define USB_REV_REV_MASK (0xFFU)
+#define USB_REV_REV_SHIFT (0U)
+#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
+/*! @} */
+
+/*! @name ADDINFO - Peripheral Additional Info register */
+/*! @{ */
+#define USB_ADDINFO_IEHOST_MASK (0x1U)
+#define USB_ADDINFO_IEHOST_SHIFT (0U)
+#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
+/*! @} */
+
+/*! @name OTGISTAT - OTG Interrupt Status register */
+/*! @{ */
+#define USB_OTGISTAT_AVBUSCHG_MASK (0x1U)
+#define USB_OTGISTAT_AVBUSCHG_SHIFT (0U)
+#define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK)
+#define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U)
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U)
+#define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK)
+#define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U)
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U)
+#define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK)
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
+#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
+#define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
+#define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
+#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
+#define USB_OTGISTAT_IDCHG_MASK (0x80U)
+#define USB_OTGISTAT_IDCHG_SHIFT (7U)
+#define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK)
+/*! @} */
+
+/*! @name OTGICR - OTG Interrupt Control register */
+/*! @{ */
+#define USB_OTGICR_AVBUSEN_MASK (0x1U)
+#define USB_OTGICR_AVBUSEN_SHIFT (0U)
+/*! AVBUSEN - A VBUS Valid Interrupt Enable
+ * 0b0..Disables the AVBUSCHG interrupt.
+ * 0b1..Enables the AVBUSCHG interrupt.
+ */
+#define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK)
+#define USB_OTGICR_BSESSEN_MASK (0x4U)
+#define USB_OTGICR_BSESSEN_SHIFT (2U)
+/*! BSESSEN - B Session END Interrupt Enable
+ * 0b0..Disables the B_SESS_CHG interrupt.
+ * 0b1..Enables the B_SESS_CHG interrupt.
+ */
+#define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK)
+#define USB_OTGICR_SESSVLDEN_MASK (0x8U)
+#define USB_OTGICR_SESSVLDEN_SHIFT (3U)
+/*! SESSVLDEN - Session Valid Interrupt Enable
+ * 0b0..Disables the SESSVLDCHG interrupt.
+ * 0b1..Enables the SESSVLDCHG interrupt.
+ */
+#define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK)
+#define USB_OTGICR_LINESTATEEN_MASK (0x20U)
+#define USB_OTGICR_LINESTATEEN_SHIFT (5U)
+/*! LINESTATEEN - Line State Change Interrupt Enable
+ * 0b0..Disables the LINE_STAT_CHG interrupt.
+ * 0b1..Enables the LINE_STAT_CHG interrupt.
+ */
+#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
+#define USB_OTGICR_ONEMSECEN_MASK (0x40U)
+#define USB_OTGICR_ONEMSECEN_SHIFT (6U)
+/*! ONEMSECEN - One Millisecond Interrupt Enable
+ * 0b0..Diables the 1ms timer interrupt.
+ * 0b1..Enables the 1ms timer interrupt.
+ */
+#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
+#define USB_OTGICR_IDEN_MASK (0x80U)
+#define USB_OTGICR_IDEN_SHIFT (7U)
+/*! IDEN - ID Interrupt Enable
+ * 0b0..The ID interrupt is disabled
+ * 0b1..The ID interrupt is enabled
+ */
+#define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK)
+/*! @} */
+
+/*! @name OTGSTAT - OTG Status register */
+/*! @{ */
+#define USB_OTGSTAT_AVBUSVLD_MASK (0x1U)
+#define USB_OTGSTAT_AVBUSVLD_SHIFT (0U)
+/*! AVBUSVLD - A VBUS Valid
+ * 0b0..The VBUS voltage is below the A VBUS Valid threshold.
+ * 0b1..The VBUS voltage is above the A VBUS Valid threshold.
+ */
+#define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK)
+#define USB_OTGSTAT_BSESSEND_MASK (0x4U)
+#define USB_OTGSTAT_BSESSEND_SHIFT (2U)
+/*! BSESSEND - B Session End
+ * 0b0..The VBUS voltage is above the B session end threshold.
+ * 0b1..The VBUS voltage is below the B session end threshold.
+ */
+#define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK)
+#define USB_OTGSTAT_SESS_VLD_MASK (0x8U)
+#define USB_OTGSTAT_SESS_VLD_SHIFT (3U)
+/*! SESS_VLD - Session Valid
+ * 0b0..The VBUS voltage is below the B session valid threshold
+ * 0b1..The VBUS voltage is above the B session valid threshold.
+ */
+#define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK)
+#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
+/*! LINESTATESTABLE
+ * 0b0..The LINE_STAT_CHG bit is not yet stable.
+ * 0b1..The LINE_STAT_CHG bit has been debounced and is stable.
+ */
+#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
+#define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
+#define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
+#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
+#define USB_OTGSTAT_ID_MASK (0x80U)
+#define USB_OTGSTAT_ID_SHIFT (7U)
+/*! ID
+ * 0b0..Indicates a Type A cable is plugged into the USB connector.
+ * 0b1..Indicates no cable is attached or a Type B cable is plugged into the USB connector.
+ */
+#define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK)
+/*! @} */
+
+/*! @name OTGCTL - OTG Control register */
+/*! @{ */
+#define USB_OTGCTL_OTGEN_MASK (0x4U)
+#define USB_OTGCTL_OTGEN_SHIFT (2U)
+/*! OTGEN - On-The-Go pullup/pulldown resistor enable
+ * 0b0..If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+ and D- Data Line pull-down resistors are engaged.
+ * 0b1..The pull-up and pull-down controls in this register are used.
+ */
+#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
+#define USB_OTGCTL_DMLOW_MASK (0x10U)
+#define USB_OTGCTL_DMLOW_SHIFT (4U)
+/*! DMLOW - D- Data Line pull-down resistor enable
+ * 0b0..D- pulldown resistor is not enabled.
+ * 0b1..D- pulldown resistor is enabled.
+ */
+#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
+#define USB_OTGCTL_DPLOW_MASK (0x20U)
+#define USB_OTGCTL_DPLOW_SHIFT (5U)
+/*! DPLOW - D+ Data Line pull-down resistor enable
+ * 0b0..D+ pulldown resistor is not enabled.
+ * 0b1..D+ pulldown resistor is enabled.
+ */
+#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
+#define USB_OTGCTL_DPHIGH_MASK (0x80U)
+#define USB_OTGCTL_DPHIGH_SHIFT (7U)
+/*! DPHIGH - D+ Data Line pullup resistor enable
+ * 0b0..D+ pullup resistor is not enabled
+ * 0b1..D+ pullup resistor is enabled
+ */
+#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
+/*! @} */
+
+/*! @name ISTAT - Interrupt Status register */
+/*! @{ */
+#define USB_ISTAT_USBRST_MASK (0x1U)
+#define USB_ISTAT_USBRST_SHIFT (0U)
+#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
+#define USB_ISTAT_ERROR_MASK (0x2U)
+#define USB_ISTAT_ERROR_SHIFT (1U)
+#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
+#define USB_ISTAT_SOFTOK_MASK (0x4U)
+#define USB_ISTAT_SOFTOK_SHIFT (2U)
+#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
+#define USB_ISTAT_TOKDNE_MASK (0x8U)
+#define USB_ISTAT_TOKDNE_SHIFT (3U)
+#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
+#define USB_ISTAT_SLEEP_MASK (0x10U)
+#define USB_ISTAT_SLEEP_SHIFT (4U)
+#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
+#define USB_ISTAT_RESUME_MASK (0x20U)
+#define USB_ISTAT_RESUME_SHIFT (5U)
+#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
+#define USB_ISTAT_ATTACH_MASK (0x40U)
+#define USB_ISTAT_ATTACH_SHIFT (6U)
+/*! ATTACH - Attach Interrupt
+ * 0b0..No Attach is detected since the last time the ATTACH bit was cleared.
+ * 0b1..A peripheral is now present and must be configured (a stable non-SE0 state is detected for more than 2.5 us).
+ */
+#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
+#define USB_ISTAT_STALL_MASK (0x80U)
+#define USB_ISTAT_STALL_SHIFT (7U)
+#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
+/*! @} */
+
+/*! @name INTEN - Interrupt Enable register */
+/*! @{ */
+#define USB_INTEN_USBRSTEN_MASK (0x1U)
+#define USB_INTEN_USBRSTEN_SHIFT (0U)
+/*! USBRSTEN - USBRST Interrupt Enable
+ * 0b0..Disables the USBRST interrupt.
+ * 0b1..Enables the USBRST interrupt.
+ */
+#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
+#define USB_INTEN_ERROREN_MASK (0x2U)
+#define USB_INTEN_ERROREN_SHIFT (1U)
+/*! ERROREN - ERROR Interrupt Enable
+ * 0b0..Disables the ERROR interrupt.
+ * 0b1..Enables the ERROR interrupt.
+ */
+#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
+#define USB_INTEN_SOFTOKEN_MASK (0x4U)
+#define USB_INTEN_SOFTOKEN_SHIFT (2U)
+/*! SOFTOKEN - SOFTOK Interrupt Enable
+ * 0b0..Disbles the SOFTOK interrupt.
+ * 0b1..Enables the SOFTOK interrupt.
+ */
+#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
+#define USB_INTEN_TOKDNEEN_MASK (0x8U)
+#define USB_INTEN_TOKDNEEN_SHIFT (3U)
+/*! TOKDNEEN - TOKDNE Interrupt Enable
+ * 0b0..Disables the TOKDNE interrupt.
+ * 0b1..Enables the TOKDNE interrupt.
+ */
+#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
+#define USB_INTEN_SLEEPEN_MASK (0x10U)
+#define USB_INTEN_SLEEPEN_SHIFT (4U)
+/*! SLEEPEN - SLEEP Interrupt Enable
+ * 0b0..Disables the SLEEP interrupt.
+ * 0b1..Enables the SLEEP interrupt.
+ */
+#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
+#define USB_INTEN_RESUMEEN_MASK (0x20U)
+#define USB_INTEN_RESUMEEN_SHIFT (5U)
+/*! RESUMEEN - RESUME Interrupt Enable
+ * 0b0..Disables the RESUME interrupt.
+ * 0b1..Enables the RESUME interrupt.
+ */
+#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
+#define USB_INTEN_ATTACHEN_MASK (0x40U)
+#define USB_INTEN_ATTACHEN_SHIFT (6U)
+/*! ATTACHEN - ATTACH Interrupt Enable
+ * 0b0..Disables the ATTACH interrupt.
+ * 0b1..Enables the ATTACH interrupt.
+ */
+#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
+#define USB_INTEN_STALLEN_MASK (0x80U)
+#define USB_INTEN_STALLEN_SHIFT (7U)
+/*! STALLEN - STALL Interrupt Enable
+ * 0b0..Diasbles the STALL interrupt.
+ * 0b1..Enables the STALL interrupt.
+ */
+#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
+/*! @} */
+
+/*! @name ERRSTAT - Error Interrupt Status register */
+/*! @{ */
+#define USB_ERRSTAT_PIDERR_MASK (0x1U)
+#define USB_ERRSTAT_PIDERR_SHIFT (0U)
+#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
+#define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
+#define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
+#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
+#define USB_ERRSTAT_CRC16_MASK (0x4U)
+#define USB_ERRSTAT_CRC16_SHIFT (2U)
+#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
+#define USB_ERRSTAT_DFN8_MASK (0x8U)
+#define USB_ERRSTAT_DFN8_SHIFT (3U)
+#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
+#define USB_ERRSTAT_BTOERR_MASK (0x10U)
+#define USB_ERRSTAT_BTOERR_SHIFT (4U)
+#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
+#define USB_ERRSTAT_DMAERR_MASK (0x20U)
+#define USB_ERRSTAT_DMAERR_SHIFT (5U)
+#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
+#define USB_ERRSTAT_BTSERR_MASK (0x80U)
+#define USB_ERRSTAT_BTSERR_SHIFT (7U)
+#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
+/*! @} */
+
+/*! @name ERREN - Error Interrupt Enable register */
+/*! @{ */
+#define USB_ERREN_PIDERREN_MASK (0x1U)
+#define USB_ERREN_PIDERREN_SHIFT (0U)
+/*! PIDERREN - PIDERR Interrupt Enable
+ * 0b0..Disables the PIDERR interrupt.
+ * 0b1..Enters the PIDERR interrupt.
+ */
+#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
+#define USB_ERREN_CRC5EOFEN_MASK (0x2U)
+#define USB_ERREN_CRC5EOFEN_SHIFT (1U)
+/*! CRC5EOFEN - CRC5/EOF Interrupt Enable
+ * 0b0..Disables the CRC5/EOF interrupt.
+ * 0b1..Enables the CRC5/EOF interrupt.
+ */
+#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
+#define USB_ERREN_CRC16EN_MASK (0x4U)
+#define USB_ERREN_CRC16EN_SHIFT (2U)
+/*! CRC16EN - CRC16 Interrupt Enable
+ * 0b0..Disables the CRC16 interrupt.
+ * 0b1..Enables the CRC16 interrupt.
+ */
+#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
+#define USB_ERREN_DFN8EN_MASK (0x8U)
+#define USB_ERREN_DFN8EN_SHIFT (3U)
+/*! DFN8EN - DFN8 Interrupt Enable
+ * 0b0..Disables the DFN8 interrupt.
+ * 0b1..Enables the DFN8 interrupt.
+ */
+#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
+#define USB_ERREN_BTOERREN_MASK (0x10U)
+#define USB_ERREN_BTOERREN_SHIFT (4U)
+/*! BTOERREN - BTOERR Interrupt Enable
+ * 0b0..Disables the BTOERR interrupt.
+ * 0b1..Enables the BTOERR interrupt.
+ */
+#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
+#define USB_ERREN_DMAERREN_MASK (0x20U)
+#define USB_ERREN_DMAERREN_SHIFT (5U)
+/*! DMAERREN - DMAERR Interrupt Enable
+ * 0b0..Disables the DMAERR interrupt.
+ * 0b1..Enables the DMAERR interrupt.
+ */
+#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
+#define USB_ERREN_BTSERREN_MASK (0x80U)
+#define USB_ERREN_BTSERREN_SHIFT (7U)
+/*! BTSERREN - BTSERR Interrupt Enable
+ * 0b0..Disables the BTSERR interrupt.
+ * 0b1..Enables the BTSERR interrupt.
+ */
+#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
+/*! @} */
+
+/*! @name STAT - Status register */
+/*! @{ */
+#define USB_STAT_ODD_MASK (0x4U)
+#define USB_STAT_ODD_SHIFT (2U)
+#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
+#define USB_STAT_TX_MASK (0x8U)
+#define USB_STAT_TX_SHIFT (3U)
+/*! TX - Transmit Indicator
+ * 0b0..The most recent transaction was a receive operation.
+ * 0b1..The most recent transaction was a transmit operation.
+ */
+#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
+#define USB_STAT_ENDP_MASK (0xF0U)
+#define USB_STAT_ENDP_SHIFT (4U)
+#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
+/*! @} */
+
+/*! @name CTL - Control register */
+/*! @{ */
+#define USB_CTL_USBENSOFEN_MASK (0x1U)
+#define USB_CTL_USBENSOFEN_SHIFT (0U)
+/*! USBENSOFEN - USB Enable
+ * 0b0..Disables the USB Module.
+ * 0b1..Enables the USB Module.
+ */
+#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
+#define USB_CTL_ODDRST_MASK (0x2U)
+#define USB_CTL_ODDRST_SHIFT (1U)
+#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
+#define USB_CTL_RESUME_MASK (0x4U)
+#define USB_CTL_RESUME_SHIFT (2U)
+#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
+#define USB_CTL_HOSTMODEEN_MASK (0x8U)
+#define USB_CTL_HOSTMODEEN_SHIFT (3U)
+#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
+#define USB_CTL_RESET_MASK (0x10U)
+#define USB_CTL_RESET_SHIFT (4U)
+#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
+#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
+#define USB_CTL_SE0_MASK (0x40U)
+#define USB_CTL_SE0_SHIFT (6U)
+#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
+#define USB_CTL_JSTATE_MASK (0x80U)
+#define USB_CTL_JSTATE_SHIFT (7U)
+#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
+/*! @} */
+
+/*! @name ADDR - Address register */
+/*! @{ */
+#define USB_ADDR_ADDR_MASK (0x7FU)
+#define USB_ADDR_ADDR_SHIFT (0U)
+#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK (0x80U)
+#define USB_ADDR_LSEN_SHIFT (7U)
+#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
+/*! @} */
+
+/*! @name BDTPAGE1 - BDT Page register 1 */
+/*! @{ */
+#define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
+#define USB_BDTPAGE1_BDTBA_SHIFT (1U)
+#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
+/*! @} */
+
+/*! @name FRMNUML - Frame Number register Low */
+/*! @{ */
+#define USB_FRMNUML_FRM_MASK (0xFFU)
+#define USB_FRMNUML_FRM_SHIFT (0U)
+#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
+/*! @} */
+
+/*! @name FRMNUMH - Frame Number register High */
+/*! @{ */
+#define USB_FRMNUMH_FRM_MASK (0x7U)
+#define USB_FRMNUMH_FRM_SHIFT (0U)
+#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
+/*! @} */
+
+/*! @name TOKEN - Token register */
+/*! @{ */
+#define USB_TOKEN_TOKENENDPT_MASK (0xFU)
+#define USB_TOKEN_TOKENENDPT_SHIFT (0U)
+#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK (0xF0U)
+#define USB_TOKEN_TOKENPID_SHIFT (4U)
+/*! TOKENPID
+ * 0b0001..OUT Token. USB Module performs an OUT (TX) transaction.
+ * 0b1001..IN Token. USB Module performs an In (RX) transaction.
+ * 0b1101..SETUP Token. USB Module performs a SETUP (TX) transaction
+ */
+#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
+/*! @} */
+
+/*! @name SOFTHLD - SOF Threshold register */
+/*! @{ */
+#define USB_SOFTHLD_CNT_MASK (0xFFU)
+#define USB_SOFTHLD_CNT_SHIFT (0U)
+#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
+/*! @} */
+
+/*! @name BDTPAGE2 - BDT Page Register 2 */
+/*! @{ */
+#define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
+#define USB_BDTPAGE2_BDTBA_SHIFT (0U)
+#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
+/*! @} */
+
+/*! @name BDTPAGE3 - BDT Page Register 3 */
+/*! @{ */
+#define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
+#define USB_BDTPAGE3_BDTBA_SHIFT (0U)
+#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
+/*! @} */
+
+/*! @name ENDPT - Endpoint Control register */
+/*! @{ */
+#define USB_ENDPT_EPHSHK_MASK (0x1U)
+#define USB_ENDPT_EPHSHK_SHIFT (0U)
+#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
+#define USB_ENDPT_EPSTALL_MASK (0x2U)
+#define USB_ENDPT_EPSTALL_SHIFT (1U)
+#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
+#define USB_ENDPT_EPTXEN_MASK (0x4U)
+#define USB_ENDPT_EPTXEN_SHIFT (2U)
+#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
+#define USB_ENDPT_EPRXEN_MASK (0x8U)
+#define USB_ENDPT_EPRXEN_SHIFT (3U)
+#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
+#define USB_ENDPT_EPCTLDIS_MASK (0x10U)
+#define USB_ENDPT_EPCTLDIS_SHIFT (4U)
+#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
+#define USB_ENDPT_RETRYDIS_MASK (0x40U)
+#define USB_ENDPT_RETRYDIS_SHIFT (6U)
+#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
+#define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
+#define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
+/*! HOSTWOHUB
+ * 0b0..Low-speed device connected to Host through a hub. PRE_PID will be generated as required.
+ * 0b1..Low-speed device directly connected. No hub, or no low-speed device attached.
+ */
+#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
+/*! @} */
+
+/* The count of USB_ENDPT */
+#define USB_ENDPT_COUNT (16U)
+
+/*! @name USBCTRL - USB Control register */
+/*! @{ */
+#define USB_USBCTRL_PDE_MASK (0x40U)
+#define USB_USBCTRL_PDE_SHIFT (6U)
+/*! PDE
+ * 0b0..Weak pulldowns are disabled on D+ and D-.
+ * 0b1..Weak pulldowns are enabled on D+ and D-.
+ */
+#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
+#define USB_USBCTRL_SUSP_MASK (0x80U)
+#define USB_USBCTRL_SUSP_SHIFT (7U)
+/*! SUSP
+ * 0b0..USB transceiver is not in suspend state.
+ * 0b1..USB transceiver is in suspend state.
+ */
+#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
+/*! @} */
+
+/*! @name OBSERVE - USB OTG Observe register */
+/*! @{ */
+#define USB_OBSERVE_DMPD_MASK (0x10U)
+#define USB_OBSERVE_DMPD_SHIFT (4U)
+/*! DMPD
+ * 0b0..D- pulldown disabled.
+ * 0b1..D- pulldown enabled.
+ */
+#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
+#define USB_OBSERVE_DPPD_MASK (0x40U)
+#define USB_OBSERVE_DPPD_SHIFT (6U)
+/*! DPPD
+ * 0b0..D+ pulldown disabled.
+ * 0b1..D+ pulldown enabled.
+ */
+#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
+#define USB_OBSERVE_DPPU_MASK (0x80U)
+#define USB_OBSERVE_DPPU_SHIFT (7U)
+/*! DPPU
+ * 0b0..D+ pullup disabled.
+ * 0b1..D+ pullup enabled.
+ */
+#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
+/*! @} */
+
+/*! @name CONTROL - USB OTG Control register */
+/*! @{ */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
+/*! DPPULLUPNONOTG
+ * 0b0..DP Pullup in non-OTG device mode is not enabled.
+ * 0b1..DP Pullup in non-OTG device mode is enabled.
+ */
+#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
+/*! @} */
+
+/*! @name USBTRC0 - USB Transceiver Control register 0 */
+/*! @{ */
+#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
+/*! USB_RESUME_INT - USB Asynchronous Interrupt
+ * 0b0..No interrupt was generated.
+ * 0b1..Interrupt was generated because of the USB asynchronous interrupt.
+ */
+#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
+#define USB_USBTRC0_SYNC_DET_MASK (0x2U)
+#define USB_USBTRC0_SYNC_DET_SHIFT (1U)
+/*! SYNC_DET - Synchronous USB Interrupt Detect
+ * 0b0..Synchronous interrupt has not been detected.
+ * 0b1..Synchronous interrupt has been detected.
+ */
+#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
+#define USB_USBTRC0_USBRESMEN_MASK (0x20U)
+#define USB_USBTRC0_USBRESMEN_SHIFT (5U)
+/*! USBRESMEN - Asynchronous Resume Interrupt Enable
+ * 0b0..USB asynchronous wakeup from suspend mode disabled.
+ * 0b1..USB asynchronous wakeup from suspend mode enabled. The asynchronous resume interrupt differs from the synchronous resume interrupt in that it asynchronously detects K-state using the unfiltered state of the D+ and D- pins. This interrupt should only be enabled when the Transceiver is suspended.
+ */
+#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
+#define USB_USBTRC0_USBRESET_MASK (0x80U)
+#define USB_USBTRC0_USBRESET_SHIFT (7U)
+/*! USBRESET - USB Reset
+ * 0b0..Normal USB module operation.
+ * 0b1..Returns the USB module to its reset state.
+ */
+#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
+/*! @} */
+
+/*! @name USBFRMADJUST - Frame Adjust Register */
+/*! @{ */
+#define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
+#define USB_USBFRMADJUST_ADJ_SHIFT (0U)
+#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
+/*! @} */
+
+/*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
+/*! @{ */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
+/*! RESTART_IFRTRIM_EN - Restart from IFR trim value
+ * 0b0..Trim fine adjustment always works based on the previous updated trim fine value (default)
+ * 0b1..Trim fine restarts from the IFR trim value whenever bus_reset/bus_resume is detected or module enable is desasserted
+ */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
+/*! RESET_RESUME_ROUGH_EN - Reset/resume to rough phase enable
+ * 0b0..Always works in tracking phase after the 1st time rough to track transition (default)
+ * 0b1..Go back to rough stage whenever bus reset or bus resume occurs
+ */
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
+/*! CLOCK_RECOVER_EN - Crystal-less USB enable
+ * 0b0..Disable clock recovery block (default)
+ * 0b1..Enable clock recovery block
+ */
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
+/*! @} */
+
+/*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */
+/*! @{ */
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U)
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U)
+/*! REG_EN - IRC48M regulator enable
+ * 0b0..IRC48M local regulator is disabled
+ * 0b1..IRC48M local regulator is enabled (default)
+ */
+#define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U)
+/*! IRC_EN - IRC48M enable
+ * 0b0..Disable the IRC48M module (default)
+ * 0b1..Enable the IRC48M module
+ */
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
+/*! @} */
+
+/*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */
+/*! @{ */
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U)
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U)
+/*! OVF_ERROR_EN
+ * 0b0..The interrupt will be masked
+ * 0b1..The interrupt will be enabled (default)
+ */
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
+/*! @} */
+
+/*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
+/*! @{ */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
+/*! OVF_ERROR
+ * 0b0..No interrupt is reported
+ * 0b1..Unmasked interrupt has been generated
+ */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0 ((USB_Type *)USB0_BASE)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS { USB0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBDCD Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
+ * @{
+ */
+
+/** USBDCD - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
+ __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
+ __I uint32_t STATUS; /**< Status register, offset: 0x8 */
+ __IO uint32_t SIGNAL_OVERRIDE; /**< Signal Override Register, offset: 0xC */
+ __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
+ __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
+ union { /* offset: 0x18 */
+ __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
+ __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
+ };
+} USBDCD_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USBDCD Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
+ * @{
+ */
+
+/*! @name CONTROL - Control register */
+/*! @{ */
+#define USBDCD_CONTROL_IACK_MASK (0x1U)
+#define USBDCD_CONTROL_IACK_SHIFT (0U)
+/*! IACK - Interrupt Acknowledge
+ * 0b0..Do not clear the interrupt.
+ * 0b1..Clear the IF bit (interrupt flag).
+ */
+#define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK)
+#define USBDCD_CONTROL_IF_MASK (0x100U)
+#define USBDCD_CONTROL_IF_SHIFT (8U)
+/*! IF - Interrupt Flag
+ * 0b0..No interrupt is pending.
+ * 0b1..An interrupt is pending.
+ */
+#define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK)
+#define USBDCD_CONTROL_IE_MASK (0x10000U)
+#define USBDCD_CONTROL_IE_SHIFT (16U)
+/*! IE - Interrupt Enable
+ * 0b0..Disable interrupts to the system.
+ * 0b1..Enable interrupts to the system.
+ */
+#define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK)
+#define USBDCD_CONTROL_BC12_MASK (0x20000U)
+#define USBDCD_CONTROL_BC12_SHIFT (17U)
+/*! BC12
+ * 0b0..Compatible with BC1.1 (default)
+ * 0b1..Compatible with BC1.2
+ */
+#define USBDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_BC12_SHIFT)) & USBDCD_CONTROL_BC12_MASK)
+#define USBDCD_CONTROL_START_MASK (0x1000000U)
+#define USBDCD_CONTROL_START_SHIFT (24U)
+/*! START - Start Change Detection Sequence
+ * 0b0..Do not start the sequence. Writes of this value have no effect.
+ * 0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect.
+ */
+#define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK)
+#define USBDCD_CONTROL_SR_MASK (0x2000000U)
+#define USBDCD_CONTROL_SR_SHIFT (25U)
+/*! SR - Software Reset
+ * 0b0..Do not perform a software reset.
+ * 0b1..Perform a software reset.
+ */
+#define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK)
+/*! @} */
+
+/*! @name CLOCK - Clock register */
+/*! @{ */
+#define USBDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)
+#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)
+/*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed
+ * 0b0..kHz Speed (between 1 kHz and 1023 kHz)
+ * 0b1..MHz Speed (between 1 MHz and 1023 MHz)
+ */
+#define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK)
+#define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)
+#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)
+#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK)
+/*! @} */
+
+/*! @name STATUS - Status register */
+/*! @{ */
+#define USBDCD_STATUS_SEQ_RES_MASK (0x30000U)
+#define USBDCD_STATUS_SEQ_RES_SHIFT (16U)
+/*! SEQ_RES - Charger Detection Sequence Results
+ * 0b00..No results to report.
+ * 0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected.
+ * 0b10..Attached to a charging port. The exact meaning depends on bit 18: 0: Attached to either a CDP or a DCP. The charger type detection has not completed. 1: Attached to a CDP. The charger type detection has completed.
+ * 0b11..Attached to a DCP.
+ */
+#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK)
+#define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U)
+#define USBDCD_STATUS_SEQ_STAT_SHIFT (18U)
+/*! SEQ_STAT - Charger Detection Sequence Status
+ * 0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected.
+ * 0b01..Data pin contact detection is complete.
+ * 0b10..Charging port detection is complete.
+ * 0b11..Charger type detection is complete.
+ */
+#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK)
+#define USBDCD_STATUS_ERR_MASK (0x100000U)
+#define USBDCD_STATUS_ERR_SHIFT (20U)
+/*! ERR - Error Flag
+ * 0b0..No sequence errors.
+ * 0b1..Error in the detection sequence. See the SEQ_STAT field to determine the phase in which the error occurred.
+ */
+#define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK)
+#define USBDCD_STATUS_TO_MASK (0x200000U)
+#define USBDCD_STATUS_TO_SHIFT (21U)
+/*! TO - Timeout Flag
+ * 0b0..The detection sequence has not been running for over 1 s.
+ * 0b1..It has been over 1 s since the data pin contact was detected and debounced.
+ */
+#define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK)
+#define USBDCD_STATUS_ACTIVE_MASK (0x400000U)
+#define USBDCD_STATUS_ACTIVE_SHIFT (22U)
+/*! ACTIVE - Active Status Indicator
+ * 0b0..The sequence is not running.
+ * 0b1..The sequence is running.
+ */
+#define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK)
+/*! @} */
+
+/*! @name SIGNAL_OVERRIDE - Signal Override Register */
+/*! @{ */
+#define USBDCD_SIGNAL_OVERRIDE_PS_MASK (0x3U)
+#define USBDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U)
+/*! PS - Phase Selection
+ * 0b00..No overrides. Bit field must remain at this value during normal USB data communication to prevent unexpected conditions on USB_DP and USB_DM pins. (Default)
+ * 0b01..Reserved, not for customer use.
+ * 0b10..Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin.
+ * 0b11..Reserved, not for customer use.
+ */
+#define USBDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBDCD_SIGNAL_OVERRIDE_PS_MASK)
+/*! @} */
+
+/*! @name TIMER0 - TIMER0 register */
+/*! @{ */
+#define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU)
+#define USBDCD_TIMER0_TUNITCON_SHIFT (0U)
+#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK)
+#define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)
+#define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U)
+#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK)
+/*! @} */
+
+/*! @name TIMER1 - TIMER1 register */
+/*! @{ */
+#define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)
+#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)
+#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)
+#define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U)
+#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK)
+/*! @} */
+
+/*! @name TIMER2_BC11 - TIMER2_BC11 register */
+/*! @{ */
+#define USBDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU)
+#define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U)
+#define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK)
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U)
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U)
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
+/*! @} */
+
+/*! @name TIMER2_BC12 - TIMER2_BC12 register */
+/*! @{ */
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU)
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U)
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Masks */
+
+
+/* USBDCD - Peripheral instance base addresses */
+/** Peripheral USBDCD base address */
+#define USBDCD_BASE (0x40035000u)
+/** Peripheral USBDCD base pointer */
+#define USBDCD ((USBDCD_Type *)USBDCD_BASE)
+/** Array initializer of USBDCD peripheral base addresses */
+#define USBDCD_BASE_ADDRS { USBDCD_BASE }
+/** Array initializer of USBDCD peripheral base pointers */
+#define USBDCD_BASE_PTRS { USBDCD }
+/** Interrupt vectors for the USBDCD peripheral type */
+#define USBDCD_IRQS { USBDCD_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBHS Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHS_Peripheral_Access_Layer USBHS Peripheral Access Layer
+ * @{
+ */
+
+/** USBHS - Register Layout Typedef */
+typedef struct {
+ __I uint32_t ID; /**< Identification Register, offset: 0x0 */
+ __I uint32_t HWGENERAL; /**< General Hardware Parameters Register, offset: 0x4 */
+ __I uint32_t HWHOST; /**< Host Hardware Parameters Register, offset: 0x8 */
+ __I uint32_t HWDEVICE; /**< Device Hardware Parameters Register, offset: 0xC */
+ __I uint32_t HWTXBUF; /**< Transmit Buffer Hardware Parameters Register, offset: 0x10 */
+ __I uint32_t HWRXBUF; /**< Receive Buffer Hardware Parameters Register, offset: 0x14 */
+ uint8_t RESERVED_0[104];
+ __IO uint32_t GPTIMER0LD; /**< General Purpose Timer n Load Register, offset: 0x80 */
+ __IO uint32_t GPTIMER0CTL; /**< General Purpose Timer n Control Register, offset: 0x84 */
+ __IO uint32_t GPTIMER1LD; /**< General Purpose Timer n Load Register, offset: 0x88 */
+ __IO uint32_t GPTIMER1CTL; /**< General Purpose Timer n Control Register, offset: 0x8C */
+ __IO uint32_t USB_SBUSCFG; /**< System Bus Interface Configuration Register, offset: 0x90 */
+ uint8_t RESERVED_1[108];
+ __I uint32_t HCIVERSION; /**< Host Controller Interface Version and Capability Registers Length Register, offset: 0x100 */
+ __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters Register, offset: 0x104 */
+ __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters Register, offset: 0x108 */
+ uint8_t RESERVED_2[22];
+ __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x122 */
+ __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */
+ uint8_t RESERVED_3[24];
+ __IO uint32_t USBCMD; /**< USB Command Register, offset: 0x140 */
+ __IO uint32_t USBSTS; /**< USB Status Register, offset: 0x144 */
+ __IO uint32_t USBINTR; /**< USB Interrupt Enable Register, offset: 0x148 */
+ __IO uint32_t FRINDEX; /**< Frame Index Register, offset: 0x14C */
+ uint8_t RESERVED_4[4];
+ union { /* offset: 0x154 */
+ __IO uint32_t DEVICEADDR; /**< Device Address Register, offset: 0x154 */
+ __IO uint32_t PERIODICLISTBASE; /**< Periodic Frame List Base Address Register, offset: 0x154 */
+ };
+ union { /* offset: 0x158 */
+ __IO uint32_t ASYNCLISTADDR; /**< Current Asynchronous List Address Register, offset: 0x158 */
+ __IO uint32_t EPLISTADDR; /**< Endpoint List Address Register, offset: 0x158 */
+ };
+ __I uint32_t TTCTRL; /**< Host TT Asynchronous Buffer Control, offset: 0x15C */
+ __IO uint32_t BURSTSIZE; /**< Master Interface Data Burst Size Register, offset: 0x160 */
+ __IO uint32_t TXFILLTUNING; /**< Transmit FIFO Tuning Control Register, offset: 0x164 */
+ uint8_t RESERVED_5[16];
+ __IO uint32_t ENDPTNAK; /**< Endpoint NAK Register, offset: 0x178 */
+ __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable Register, offset: 0x17C */
+ uint32_t CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */
+ __IO uint32_t PORTSC1; /**< Port Status and Control Registers, offset: 0x184 */
+ uint8_t RESERVED_6[28];
+ __IO uint32_t OTGSC; /**< On-the-Go Status and Control Register, offset: 0x1A4 */
+ __IO uint32_t USBMODE; /**< USB Mode Register, offset: 0x1A8 */
+ __IO uint32_t EPSETUPSR; /**< Endpoint Setup Status Register, offset: 0x1AC */
+ __IO uint32_t EPPRIME; /**< Endpoint Initialization Register, offset: 0x1B0 */
+ __IO uint32_t EPFLUSH; /**< Endpoint Flush Register, offset: 0x1B4 */
+ __I uint32_t EPSR; /**< Endpoint Status Register, offset: 0x1B8 */
+ __IO uint32_t EPCOMPLETE; /**< Endpoint Complete Register, offset: 0x1BC */
+ __IO uint32_t EPCR0; /**< Endpoint Control Register 0, offset: 0x1C0 */
+ __IO uint32_t EPCR[7]; /**< Endpoint Control Register n, array offset: 0x1C4, array step: 0x4 */
+ uint8_t RESERVED_7[32];
+ __IO uint32_t USBGENCTRL; /**< USB General Control Register, offset: 0x200 */
+} USBHS_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USBHS Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHS_Register_Masks USBHS Register Masks
+ * @{
+ */
+
+/*! @name ID - Identification Register */
+/*! @{ */
+#define USBHS_ID_ID_MASK (0x3FU)
+#define USBHS_ID_ID_SHIFT (0U)
+#define USBHS_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_ID_SHIFT)) & USBHS_ID_ID_MASK)
+#define USBHS_ID_NID_MASK (0x3F00U)
+#define USBHS_ID_NID_SHIFT (8U)
+#define USBHS_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_NID_SHIFT)) & USBHS_ID_NID_MASK)
+#define USBHS_ID_TAG_MASK (0x1F0000U)
+#define USBHS_ID_TAG_SHIFT (16U)
+#define USBHS_ID_TAG(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_TAG_SHIFT)) & USBHS_ID_TAG_MASK)
+#define USBHS_ID_REVISION_MASK (0x1E00000U)
+#define USBHS_ID_REVISION_SHIFT (21U)
+#define USBHS_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_REVISION_SHIFT)) & USBHS_ID_REVISION_MASK)
+#define USBHS_ID_VERSION_MASK (0x1E000000U)
+#define USBHS_ID_VERSION_SHIFT (25U)
+#define USBHS_ID_VERSION(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_VERSION_SHIFT)) & USBHS_ID_VERSION_MASK)
+#define USBHS_ID_VERSIONID_MASK (0xE0000000U)
+#define USBHS_ID_VERSIONID_SHIFT (29U)
+#define USBHS_ID_VERSIONID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_VERSIONID_SHIFT)) & USBHS_ID_VERSIONID_MASK)
+/*! @} */
+
+/*! @name HWGENERAL - General Hardware Parameters Register */
+/*! @{ */
+#define USBHS_HWGENERAL_PHYW_MASK (0x30U)
+#define USBHS_HWGENERAL_PHYW_SHIFT (4U)
+/*! PHYW - PHY Width
+ * 0b01..16 bit wide data bus
+ */
+#define USBHS_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYW_SHIFT)) & USBHS_HWGENERAL_PHYW_MASK)
+#define USBHS_HWGENERAL_PHYM_MASK (0x1C0U)
+#define USBHS_HWGENERAL_PHYM_SHIFT (6U)
+/*! PHYM - PHY Mode
+ * 0b000..Controller configured for UTMI/UTMI+ interface.
+ */
+#define USBHS_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYM_SHIFT)) & USBHS_HWGENERAL_PHYM_MASK)
+#define USBHS_HWGENERAL_SM_MASK (0x600U)
+#define USBHS_HWGENERAL_SM_SHIFT (9U)
+/*! SM - Serial mode
+ * 0b00..No Serial Engine, always use parallel signaling.
+ */
+#define USBHS_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_SM_SHIFT)) & USBHS_HWGENERAL_SM_MASK)
+/*! @} */
+
+/*! @name HWHOST - Host Hardware Parameters Register */
+/*! @{ */
+#define USBHS_HWHOST_HC_MASK (0x1U)
+#define USBHS_HWHOST_HC_SHIFT (0U)
+#define USBHS_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_HC_SHIFT)) & USBHS_HWHOST_HC_MASK)
+#define USBHS_HWHOST_NPORT_MASK (0xEU)
+#define USBHS_HWHOST_NPORT_SHIFT (1U)
+#define USBHS_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_NPORT_SHIFT)) & USBHS_HWHOST_NPORT_MASK)
+#define USBHS_HWHOST_TTASY_MASK (0xFF0000U)
+#define USBHS_HWHOST_TTASY_SHIFT (16U)
+#define USBHS_HWHOST_TTASY(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_TTASY_SHIFT)) & USBHS_HWHOST_TTASY_MASK)
+#define USBHS_HWHOST_TTPER_MASK (0xFF000000U)
+#define USBHS_HWHOST_TTPER_SHIFT (24U)
+#define USBHS_HWHOST_TTPER(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_TTPER_SHIFT)) & USBHS_HWHOST_TTPER_MASK)
+/*! @} */
+
+/*! @name HWDEVICE - Device Hardware Parameters Register */
+/*! @{ */
+#define USBHS_HWDEVICE_DC_MASK (0x1U)
+#define USBHS_HWDEVICE_DC_SHIFT (0U)
+#define USBHS_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DC_SHIFT)) & USBHS_HWDEVICE_DC_MASK)
+#define USBHS_HWDEVICE_DEVEP_MASK (0x3EU)
+#define USBHS_HWDEVICE_DEVEP_SHIFT (1U)
+#define USBHS_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DEVEP_SHIFT)) & USBHS_HWDEVICE_DEVEP_MASK)
+/*! @} */
+
+/*! @name HWTXBUF - Transmit Buffer Hardware Parameters Register */
+/*! @{ */
+#define USBHS_HWTXBUF_TXBURST_MASK (0xFFU)
+#define USBHS_HWTXBUF_TXBURST_SHIFT (0U)
+#define USBHS_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXBURST_SHIFT)) & USBHS_HWTXBUF_TXBURST_MASK)
+#define USBHS_HWTXBUF_TXADD_MASK (0xFF00U)
+#define USBHS_HWTXBUF_TXADD_SHIFT (8U)
+#define USBHS_HWTXBUF_TXADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXADD_SHIFT)) & USBHS_HWTXBUF_TXADD_MASK)
+#define USBHS_HWTXBUF_TXCHANADD_MASK (0xFF0000U)
+#define USBHS_HWTXBUF_TXCHANADD_SHIFT (16U)
+#define USBHS_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXCHANADD_SHIFT)) & USBHS_HWTXBUF_TXCHANADD_MASK)
+#define USBHS_HWTXBUF_TXLC_MASK (0x80000000U)
+#define USBHS_HWTXBUF_TXLC_SHIFT (31U)
+/*! TXLC - Transmit local Context Registers
+ * 0b0..Store device transmit contexts in the TX FIFO
+ * 0b1..Store device transmit contexts in a register file
+ */
+#define USBHS_HWTXBUF_TXLC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXLC_SHIFT)) & USBHS_HWTXBUF_TXLC_MASK)
+/*! @} */
+
+/*! @name HWRXBUF - Receive Buffer Hardware Parameters Register */
+/*! @{ */
+#define USBHS_HWRXBUF_RXBURST_MASK (0xFFU)
+#define USBHS_HWRXBUF_RXBURST_SHIFT (0U)
+#define USBHS_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXBURST_SHIFT)) & USBHS_HWRXBUF_RXBURST_MASK)
+#define USBHS_HWRXBUF_RXADD_MASK (0xFF00U)
+#define USBHS_HWRXBUF_RXADD_SHIFT (8U)
+#define USBHS_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXADD_SHIFT)) & USBHS_HWRXBUF_RXADD_MASK)
+/*! @} */
+
+/*! @name GPTIMER0LD - General Purpose Timer n Load Register */
+/*! @{ */
+#define USBHS_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU)
+#define USBHS_GPTIMER0LD_GPTLD_SHIFT (0U)
+#define USBHS_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0LD_GPTLD_SHIFT)) & USBHS_GPTIMER0LD_GPTLD_MASK)
+/*! @} */
+
+/*! @name GPTIMER0CTL - General Purpose Timer n Control Register */
+/*! @{ */
+#define USBHS_GPTIMER0CTL_GPTCNT_MASK (0xFFFFFFU)
+#define USBHS_GPTIMER0CTL_GPTCNT_SHIFT (0U)
+#define USBHS_GPTIMER0CTL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_GPTCNT_SHIFT)) & USBHS_GPTIMER0CTL_GPTCNT_MASK)
+#define USBHS_GPTIMER0CTL_MODE_MASK (0x1000000U)
+#define USBHS_GPTIMER0CTL_MODE_SHIFT (24U)
+/*! MODE - Timer Mode
+ * 0b0..One shot
+ * 0b1..Repeat
+ */
+#define USBHS_GPTIMER0CTL_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_MODE_SHIFT)) & USBHS_GPTIMER0CTL_MODE_MASK)
+#define USBHS_GPTIMER0CTL_RST_MASK (0x40000000U)
+#define USBHS_GPTIMER0CTL_RST_SHIFT (30U)
+/*! RST - Timer Reset
+ * 0b0..No action
+ * 0b1..Load counter value
+ */
+#define USBHS_GPTIMER0CTL_RST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_RST_SHIFT)) & USBHS_GPTIMER0CTL_RST_MASK)
+#define USBHS_GPTIMER0CTL_RUN_MASK (0x80000000U)
+#define USBHS_GPTIMER0CTL_RUN_SHIFT (31U)
+/*! RUN - Timer Run
+ * 0b0..Timer stop
+ * 0b1..Timer run
+ */
+#define USBHS_GPTIMER0CTL_RUN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_RUN_SHIFT)) & USBHS_GPTIMER0CTL_RUN_MASK)
+/*! @} */
+
+/*! @name GPTIMER1LD - General Purpose Timer n Load Register */
+/*! @{ */
+#define USBHS_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU)
+#define USBHS_GPTIMER1LD_GPTLD_SHIFT (0U)
+#define USBHS_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1LD_GPTLD_SHIFT)) & USBHS_GPTIMER1LD_GPTLD_MASK)
+/*! @} */
+
+/*! @name GPTIMER1CTL - General Purpose Timer n Control Register */
+/*! @{ */
+#define USBHS_GPTIMER1CTL_GPTCNT_MASK (0xFFFFFFU)
+#define USBHS_GPTIMER1CTL_GPTCNT_SHIFT (0U)
+#define USBHS_GPTIMER1CTL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_GPTCNT_SHIFT)) & USBHS_GPTIMER1CTL_GPTCNT_MASK)
+#define USBHS_GPTIMER1CTL_MODE_MASK (0x1000000U)
+#define USBHS_GPTIMER1CTL_MODE_SHIFT (24U)
+/*! MODE - Timer Mode
+ * 0b0..One shot
+ * 0b1..Repeat
+ */
+#define USBHS_GPTIMER1CTL_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_MODE_SHIFT)) & USBHS_GPTIMER1CTL_MODE_MASK)
+#define USBHS_GPTIMER1CTL_RST_MASK (0x40000000U)
+#define USBHS_GPTIMER1CTL_RST_SHIFT (30U)
+/*! RST - Timer Reset
+ * 0b0..No action
+ * 0b1..Load counter value
+ */
+#define USBHS_GPTIMER1CTL_RST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_RST_SHIFT)) & USBHS_GPTIMER1CTL_RST_MASK)
+#define USBHS_GPTIMER1CTL_RUN_MASK (0x80000000U)
+#define USBHS_GPTIMER1CTL_RUN_SHIFT (31U)
+/*! RUN - Timer Run
+ * 0b0..Timer stop
+ * 0b1..Timer run
+ */
+#define USBHS_GPTIMER1CTL_RUN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_RUN_SHIFT)) & USBHS_GPTIMER1CTL_RUN_MASK)
+/*! @} */
+
+/*! @name USB_SBUSCFG - System Bus Interface Configuration Register */
+/*! @{ */
+#define USBHS_USB_SBUSCFG_BURSTMODE_MASK (0x7U)
+#define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT (0U)
+/*! BURSTMODE - Burst mode
+ * 0b000..INCR burst of unspecified length
+ * 0b001..INCR4, non-multiple transfers of INCR4 is decomposed into singles.
+ * 0b010..INCR8, non-multiple transfers of INCR8, is decomposed into INCR4 or singles.
+ * 0b011..INCR16, non-multiple transfers of INCR16, is decomposed into INCR8, INCR4 or singles.
+ * 0b100..Reserved, do not use.
+ * 0b101..INCR4, non-multiple transfers of INCR4 is decomposed into smaller unspecified length bursts.
+ * 0b110..INCR8, non-multiple transfers of INCR8 is decomposed into smaller unspecified length bursts.
+ * 0b111..INCR16, non-multiple transfers of INCR16 is decomposed into smaller unspecified length bursts.
+ */
+#define USBHS_USB_SBUSCFG_BURSTMODE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USB_SBUSCFG_BURSTMODE_SHIFT)) & USBHS_USB_SBUSCFG_BURSTMODE_MASK)
+/*! @} */
+
+/*! @name HCIVERSION - Host Controller Interface Version and Capability Registers Length Register */
+/*! @{ */
+#define USBHS_HCIVERSION_CAPLENGTH_MASK (0xFFU)
+#define USBHS_HCIVERSION_CAPLENGTH_SHIFT (0U)
+#define USBHS_HCIVERSION_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCIVERSION_CAPLENGTH_SHIFT)) & USBHS_HCIVERSION_CAPLENGTH_MASK)
+#define USBHS_HCIVERSION_HCIVERSION_MASK (0xFFFF0000U)
+#define USBHS_HCIVERSION_HCIVERSION_SHIFT (16U)
+#define USBHS_HCIVERSION_HCIVERSION(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCIVERSION_HCIVERSION_SHIFT)) & USBHS_HCIVERSION_HCIVERSION_MASK)
+/*! @} */
+
+/*! @name HCSPARAMS - Host Controller Structural Parameters Register */
+/*! @{ */
+#define USBHS_HCSPARAMS_N_PORTS_MASK (0xFU)
+#define USBHS_HCSPARAMS_N_PORTS_SHIFT (0U)
+#define USBHS_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PORTS_SHIFT)) & USBHS_HCSPARAMS_N_PORTS_MASK)
+#define USBHS_HCSPARAMS_PPC_MASK (0x10U)
+#define USBHS_HCSPARAMS_PPC_SHIFT (4U)
+/*! PPC - Power Port Control
+ * 0b1..Ports have power port switches
+ */
+#define USBHS_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PPC_SHIFT)) & USBHS_HCSPARAMS_PPC_MASK)
+#define USBHS_HCSPARAMS_N_PCC_MASK (0xF00U)
+#define USBHS_HCSPARAMS_N_PCC_SHIFT (8U)
+#define USBHS_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PCC_SHIFT)) & USBHS_HCSPARAMS_N_PCC_MASK)
+#define USBHS_HCSPARAMS_N_CC_MASK (0xF000U)
+#define USBHS_HCSPARAMS_N_CC_SHIFT (12U)
+#define USBHS_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_CC_SHIFT)) & USBHS_HCSPARAMS_N_CC_MASK)
+#define USBHS_HCSPARAMS_PI_MASK (0x10000U)
+#define USBHS_HCSPARAMS_PI_SHIFT (16U)
+/*! PI - Port Indicators
+ * 0b0..No port indicator fields
+ * 0b1..The port status and control registers include a R/W field for controlling the state of the port indicator
+ */
+#define USBHS_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PI_SHIFT)) & USBHS_HCSPARAMS_PI_MASK)
+#define USBHS_HCSPARAMS_N_PTT_MASK (0xF00000U)
+#define USBHS_HCSPARAMS_N_PTT_SHIFT (20U)
+#define USBHS_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PTT_SHIFT)) & USBHS_HCSPARAMS_N_PTT_MASK)
+#define USBHS_HCSPARAMS_N_TT_MASK (0xF000000U)
+#define USBHS_HCSPARAMS_N_TT_SHIFT (24U)
+#define USBHS_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_TT_SHIFT)) & USBHS_HCSPARAMS_N_TT_MASK)
+/*! @} */
+
+/*! @name HCCPARAMS - Host Controller Capability Parameters Register */
+/*! @{ */
+#define USBHS_HCCPARAMS_ADC_MASK (0x1U)
+#define USBHS_HCCPARAMS_ADC_SHIFT (0U)
+#define USBHS_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ADC_SHIFT)) & USBHS_HCCPARAMS_ADC_MASK)
+#define USBHS_HCCPARAMS_PFL_MASK (0x2U)
+#define USBHS_HCCPARAMS_PFL_SHIFT (1U)
+#define USBHS_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_PFL_SHIFT)) & USBHS_HCCPARAMS_PFL_MASK)
+#define USBHS_HCCPARAMS_ASP_MASK (0x4U)
+#define USBHS_HCCPARAMS_ASP_SHIFT (2U)
+/*! ASP - Asynchronous Schedule Park capability
+ * 0b0..Park not supported.
+ * 0b1..Park supported.
+ */
+#define USBHS_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ASP_SHIFT)) & USBHS_HCCPARAMS_ASP_MASK)
+#define USBHS_HCCPARAMS_IST_MASK (0xF0U)
+#define USBHS_HCCPARAMS_IST_SHIFT (4U)
+/*! IST - Isochronous Scheduling Threshold
+ * 0b0000..The value of the least significant 3 bits indicates the number of microframes a host controller can hold a set of isochronous data structures (one or more) before flushing the state
+ */
+#define USBHS_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_IST_SHIFT)) & USBHS_HCCPARAMS_IST_MASK)
+#define USBHS_HCCPARAMS_EECP_MASK (0xFF00U)
+#define USBHS_HCCPARAMS_EECP_SHIFT (8U)
+/*! EECP - EHCI Extended Capabilities Pointer
+ * 0b00000000..No extended capabilities are implemented
+ */
+#define USBHS_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_EECP_SHIFT)) & USBHS_HCCPARAMS_EECP_MASK)
+/*! @} */
+
+/*! @name DCIVERSION - Device Controller Interface Version */
+/*! @{ */
+#define USBHS_DCIVERSION_DCIVERSION_MASK (0xFFFFU)
+#define USBHS_DCIVERSION_DCIVERSION_SHIFT (0U)
+#define USBHS_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USBHS_DCIVERSION_DCIVERSION_SHIFT)) & USBHS_DCIVERSION_DCIVERSION_MASK)
+/*! @} */
+
+/*! @name DCCPARAMS - Device Controller Capability Parameters */
+/*! @{ */
+#define USBHS_DCCPARAMS_DEN_MASK (0x1FU)
+#define USBHS_DCCPARAMS_DEN_SHIFT (0U)
+#define USBHS_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DEN_SHIFT)) & USBHS_DCCPARAMS_DEN_MASK)
+#define USBHS_DCCPARAMS_DC_MASK (0x80U)
+#define USBHS_DCCPARAMS_DC_SHIFT (7U)
+#define USBHS_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DC_SHIFT)) & USBHS_DCCPARAMS_DC_MASK)
+#define USBHS_DCCPARAMS_HC_MASK (0x100U)
+#define USBHS_DCCPARAMS_HC_SHIFT (8U)
+#define USBHS_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_HC_SHIFT)) & USBHS_DCCPARAMS_HC_MASK)
+/*! @} */
+
+/*! @name USBCMD - USB Command Register */
+/*! @{ */
+#define USBHS_USBCMD_RS_MASK (0x1U)
+#define USBHS_USBCMD_RS_SHIFT (0U)
+#define USBHS_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RS_SHIFT)) & USBHS_USBCMD_RS_MASK)
+#define USBHS_USBCMD_RST_MASK (0x2U)
+#define USBHS_USBCMD_RST_SHIFT (1U)
+#define USBHS_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RST_SHIFT)) & USBHS_USBCMD_RST_MASK)
+#define USBHS_USBCMD_FS_MASK (0xCU)
+#define USBHS_USBCMD_FS_SHIFT (2U)
+/*! FS - Frame list Size
+ * 0b00..When FS2 = 0, the size is 1024 elements (4096 bytes). When FS2 = 1, the size is 64 elements (256 bytes).
+ * 0b01..When FS2 = 0, the size is 512 elements (2048 bytes). When FS2 = 1, the size is 32 elements (128 bytes).
+ * 0b10..When FS2 = 0, the size is 256 elements (1024 bytes). When FS2 = 1, the size is 16 elements (64 bytes).
+ * 0b11..When FS2 = 0, the size is 128 elements (512 bytes). When FS2 = 1, the size is 8 elements (32 bytes).
+ */
+#define USBHS_USBCMD_FS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_SHIFT)) & USBHS_USBCMD_FS_MASK)
+#define USBHS_USBCMD_PSE_MASK (0x10U)
+#define USBHS_USBCMD_PSE_SHIFT (4U)
+/*! PSE - Periodic Schedule Enable
+ * 0b0..Do not process periodic schedule.
+ * 0b1..Use the PERIODICLISTBASE register to access the periodic schedule.
+ */
+#define USBHS_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_PSE_SHIFT)) & USBHS_USBCMD_PSE_MASK)
+#define USBHS_USBCMD_ASE_MASK (0x20U)
+#define USBHS_USBCMD_ASE_SHIFT (5U)
+/*! ASE - Asynchronous Schedule Enable
+ * 0b0..Do not process asynchronous schedule.
+ * 0b1..Use the ASYNCLISTADDR register to access asynchronous schedule.
+ */
+#define USBHS_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASE_SHIFT)) & USBHS_USBCMD_ASE_MASK)
+#define USBHS_USBCMD_IAA_MASK (0x40U)
+#define USBHS_USBCMD_IAA_SHIFT (6U)
+#define USBHS_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_IAA_SHIFT)) & USBHS_USBCMD_IAA_MASK)
+#define USBHS_USBCMD_ASP_MASK (0x300U)
+#define USBHS_USBCMD_ASP_SHIFT (8U)
+#define USBHS_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASP_SHIFT)) & USBHS_USBCMD_ASP_MASK)
+#define USBHS_USBCMD_ASPE_MASK (0x800U)
+#define USBHS_USBCMD_ASPE_SHIFT (11U)
+/*! ASPE - Asynchronous Schedule Park mode Enable
+ * 0b0..Park mode disabled
+ * 0b1..Park mode enabled
+ */
+#define USBHS_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASPE_SHIFT)) & USBHS_USBCMD_ASPE_MASK)
+#define USBHS_USBCMD_SUTW_MASK (0x2000U)
+#define USBHS_USBCMD_SUTW_SHIFT (13U)
+#define USBHS_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_SUTW_SHIFT)) & USBHS_USBCMD_SUTW_MASK)
+#define USBHS_USBCMD_ATDTW_MASK (0x4000U)
+#define USBHS_USBCMD_ATDTW_SHIFT (14U)
+#define USBHS_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ATDTW_SHIFT)) & USBHS_USBCMD_ATDTW_MASK)
+#define USBHS_USBCMD_FS2_MASK (0x8000U)
+#define USBHS_USBCMD_FS2_SHIFT (15U)
+#define USBHS_USBCMD_FS2(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS2_SHIFT)) & USBHS_USBCMD_FS2_MASK)
+#define USBHS_USBCMD_ITC_MASK (0xFF0000U)
+#define USBHS_USBCMD_ITC_SHIFT (16U)
+/*! ITC - Interrupt Threshold Control
+ * 0b00000000..Immediate (no threshold)
+ * 0b00000001..1 microframe
+ * 0b00000010..2 microframes
+ * 0b00000100..4 microframes
+ * 0b00001000..8 microframes
+ * 0b00010000..16 microframes
+ * 0b00100000..32 microframes
+ * 0b01000000..64 microframes
+ */
+#define USBHS_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ITC_SHIFT)) & USBHS_USBCMD_ITC_MASK)
+/*! @} */
+
+/*! @name USBSTS - USB Status Register */
+/*! @{ */
+#define USBHS_USBSTS_UI_MASK (0x1U)
+#define USBHS_USBSTS_UI_SHIFT (0U)
+#define USBHS_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UI_SHIFT)) & USBHS_USBSTS_UI_MASK)
+#define USBHS_USBSTS_UEI_MASK (0x2U)
+#define USBHS_USBSTS_UEI_SHIFT (1U)
+/*! UEI - USB Error Interrupt
+ * 0b0..No error
+ * 0b1..Error detected
+ */
+#define USBHS_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UEI_SHIFT)) & USBHS_USBSTS_UEI_MASK)
+#define USBHS_USBSTS_PCI_MASK (0x4U)
+#define USBHS_USBSTS_PCI_SHIFT (2U)
+#define USBHS_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PCI_SHIFT)) & USBHS_USBSTS_PCI_MASK)
+#define USBHS_USBSTS_FRI_MASK (0x8U)
+#define USBHS_USBSTS_FRI_SHIFT (3U)
+#define USBHS_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_FRI_SHIFT)) & USBHS_USBSTS_FRI_MASK)
+#define USBHS_USBSTS_SEI_MASK (0x10U)
+#define USBHS_USBSTS_SEI_SHIFT (4U)
+/*! SEI - System Error
+ * 0b0..Normal operation
+ * 0b1..Error
+ */
+#define USBHS_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SEI_SHIFT)) & USBHS_USBSTS_SEI_MASK)
+#define USBHS_USBSTS_AAI_MASK (0x20U)
+#define USBHS_USBSTS_AAI_SHIFT (5U)
+/*! AAI - Interrupt on Async Advance
+ * 0b0..No async advance interrupt
+ * 0b1..Async advance interrupt
+ */
+#define USBHS_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AAI_SHIFT)) & USBHS_USBSTS_AAI_MASK)
+#define USBHS_USBSTS_URI_MASK (0x40U)
+#define USBHS_USBSTS_URI_SHIFT (6U)
+/*! URI - USB Reset received
+ * 0b0..No reset received
+ * 0b1..Reset received
+ */
+#define USBHS_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_URI_SHIFT)) & USBHS_USBSTS_URI_MASK)
+#define USBHS_USBSTS_SRI_MASK (0x80U)
+#define USBHS_USBSTS_SRI_SHIFT (7U)
+#define USBHS_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SRI_SHIFT)) & USBHS_USBSTS_SRI_MASK)
+#define USBHS_USBSTS_SLI_MASK (0x100U)
+#define USBHS_USBSTS_SLI_SHIFT (8U)
+/*! SLI - Device-controller suspend
+ * 0b0..Active
+ * 0b1..Suspended
+ */
+#define USBHS_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SLI_SHIFT)) & USBHS_USBSTS_SLI_MASK)
+#define USBHS_USBSTS_HCH_MASK (0x1000U)
+#define USBHS_USBSTS_HCH_SHIFT (12U)
+/*! HCH - Host Controller Halted
+ * 0b0..Running
+ * 0b1..Halted
+ */
+#define USBHS_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_HCH_SHIFT)) & USBHS_USBSTS_HCH_MASK)
+#define USBHS_USBSTS_RCL_MASK (0x2000U)
+#define USBHS_USBSTS_RCL_SHIFT (13U)
+/*! RCL - Reclamation
+ * 0b0..Non-empty asynchronous schedule
+ * 0b1..Empty asynchronous schedule
+ */
+#define USBHS_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_RCL_SHIFT)) & USBHS_USBSTS_RCL_MASK)
+#define USBHS_USBSTS_PS_MASK (0x4000U)
+#define USBHS_USBSTS_PS_SHIFT (14U)
+/*! PS - Periodic schedule Status
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define USBHS_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PS_SHIFT)) & USBHS_USBSTS_PS_MASK)
+#define USBHS_USBSTS_AS_MASK (0x8000U)
+#define USBHS_USBSTS_AS_SHIFT (15U)
+/*! AS - Asynchronous schedule Status
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define USBHS_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AS_SHIFT)) & USBHS_USBSTS_AS_MASK)
+#define USBHS_USBSTS_NAKI_MASK (0x10000U)
+#define USBHS_USBSTS_NAKI_SHIFT (16U)
+#define USBHS_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_NAKI_SHIFT)) & USBHS_USBSTS_NAKI_MASK)
+#define USBHS_USBSTS_UAI_MASK (0x40000U)
+#define USBHS_USBSTS_UAI_SHIFT (18U)
+#define USBHS_USBSTS_UAI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UAI_SHIFT)) & USBHS_USBSTS_UAI_MASK)
+#define USBHS_USBSTS_UPI_MASK (0x80000U)
+#define USBHS_USBSTS_UPI_SHIFT (19U)
+#define USBHS_USBSTS_UPI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UPI_SHIFT)) & USBHS_USBSTS_UPI_MASK)
+#define USBHS_USBSTS_TI0_MASK (0x1000000U)
+#define USBHS_USBSTS_TI0_SHIFT (24U)
+/*! TI0 - General purpose Timer 0 Interrupt
+ * 0b0..No interrupt
+ * 0b1..Interrupt occurred
+ */
+#define USBHS_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI0_SHIFT)) & USBHS_USBSTS_TI0_MASK)
+#define USBHS_USBSTS_TI1_MASK (0x2000000U)
+#define USBHS_USBSTS_TI1_SHIFT (25U)
+/*! TI1 - General purpose Timer 1 Interrupt
+ * 0b0..No interrupt
+ * 0b1..Interrupt occurred
+ */
+#define USBHS_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI1_SHIFT)) & USBHS_USBSTS_TI1_MASK)
+/*! @} */
+
+/*! @name USBINTR - USB Interrupt Enable Register */
+/*! @{ */
+#define USBHS_USBINTR_UE_MASK (0x1U)
+#define USBHS_USBINTR_UE_SHIFT (0U)
+/*! UE - USB interrupt Enable
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define USBHS_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UE_SHIFT)) & USBHS_USBINTR_UE_MASK)
+#define USBHS_USBINTR_UEE_MASK (0x2U)
+#define USBHS_USBINTR_UEE_SHIFT (1U)
+/*! UEE - USB Error interrupt Enable
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define USBHS_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UEE_SHIFT)) & USBHS_USBINTR_UEE_MASK)
+#define USBHS_USBINTR_PCE_MASK (0x4U)
+#define USBHS_USBINTR_PCE_SHIFT (2U)
+/*! PCE - Port Change detect Enable
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define USBHS_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_PCE_SHIFT)) & USBHS_USBINTR_PCE_MASK)
+#define USBHS_USBINTR_FRE_MASK (0x8U)
+#define USBHS_USBINTR_FRE_SHIFT (3U)
+/*! FRE - Frame list Rollover Enable
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define USBHS_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_FRE_SHIFT)) & USBHS_USBINTR_FRE_MASK)
+#define USBHS_USBINTR_SEE_MASK (0x10U)
+#define USBHS_USBINTR_SEE_SHIFT (4U)
+/*! SEE - System Error Enable
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define USBHS_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SEE_SHIFT)) & USBHS_USBINTR_SEE_MASK)
+#define USBHS_USBINTR_AAE_MASK (0x20U)
+#define USBHS_USBINTR_AAE_SHIFT (5U)
+/*! AAE - Interrupt on Async advance Enable
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define USBHS_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_AAE_SHIFT)) & USBHS_USBINTR_AAE_MASK)
+#define USBHS_USBINTR_URE_MASK (0x40U)
+#define USBHS_USBINTR_URE_SHIFT (6U)
+/*! URE - USB-Reset Enable
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define USBHS_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_URE_SHIFT)) & USBHS_USBINTR_URE_MASK)
+#define USBHS_USBINTR_SRE_MASK (0x80U)
+#define USBHS_USBINTR_SRE_SHIFT (7U)
+/*! SRE - SOF-Received Enable
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define USBHS_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SRE_SHIFT)) & USBHS_USBINTR_SRE_MASK)
+#define USBHS_USBINTR_SLE_MASK (0x100U)
+#define USBHS_USBINTR_SLE_SHIFT (8U)
+/*! SLE - Sleep (DC suspend) Enable
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define USBHS_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SLE_SHIFT)) & USBHS_USBINTR_SLE_MASK)
+#define USBHS_USBINTR_NAKE_MASK (0x10000U)
+#define USBHS_USBINTR_NAKE_SHIFT (16U)
+/*! NAKE - NAK Interrupt Enable
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define USBHS_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_NAKE_SHIFT)) & USBHS_USBINTR_NAKE_MASK)
+#define USBHS_USBINTR_UAIE_MASK (0x40000U)
+#define USBHS_USBINTR_UAIE_SHIFT (18U)
+#define USBHS_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UAIE_SHIFT)) & USBHS_USBINTR_UAIE_MASK)
+#define USBHS_USBINTR_UPIE_MASK (0x80000U)
+#define USBHS_USBINTR_UPIE_SHIFT (19U)
+#define USBHS_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UPIE_SHIFT)) & USBHS_USBINTR_UPIE_MASK)
+#define USBHS_USBINTR_TIE0_MASK (0x1000000U)
+#define USBHS_USBINTR_TIE0_SHIFT (24U)
+/*! TIE0 - General purpose Timer 0 Interrupt Enable
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define USBHS_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE0_SHIFT)) & USBHS_USBINTR_TIE0_MASK)
+#define USBHS_USBINTR_TIE1_MASK (0x2000000U)
+#define USBHS_USBINTR_TIE1_SHIFT (25U)
+/*! TIE1 - General purpose Timer 1 Interrupt Enable
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define USBHS_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE1_SHIFT)) & USBHS_USBINTR_TIE1_MASK)
+/*! @} */
+
+/*! @name FRINDEX - Frame Index Register */
+/*! @{ */
+#define USBHS_FRINDEX_FRINDEX_MASK (0x3FFFU)
+#define USBHS_FRINDEX_FRINDEX_SHIFT (0U)
+#define USBHS_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHS_FRINDEX_FRINDEX_SHIFT)) & USBHS_FRINDEX_FRINDEX_MASK)
+#define USBHS_FRINDEX_Reerved_MASK (0xFFFFC000U)
+#define USBHS_FRINDEX_Reerved_SHIFT (14U)
+#define USBHS_FRINDEX_Reerved(x) (((uint32_t)(((uint32_t)(x)) << USBHS_FRINDEX_Reerved_SHIFT)) & USBHS_FRINDEX_Reerved_MASK)
+/*! @} */
+
+/*! @name DEVICEADDR - Device Address Register */
+/*! @{ */
+#define USBHS_DEVICEADDR_USBADRA_MASK (0x1000000U)
+#define USBHS_DEVICEADDR_USBADRA_SHIFT (24U)
+/*! USBADRA - Device Address Advance
+ * 0b0..Writes to USBADR are instantaneous.
+ * 0b1..When this bit is written to a 1 at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. After an IN occurs on endpoint 0 and is ACKed, USBADR is loaded from the holding register.
+ */
+#define USBHS_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADRA_SHIFT)) & USBHS_DEVICEADDR_USBADRA_MASK)
+#define USBHS_DEVICEADDR_USBADR_MASK (0xFE000000U)
+#define USBHS_DEVICEADDR_USBADR_SHIFT (25U)
+#define USBHS_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADR_SHIFT)) & USBHS_DEVICEADDR_USBADR_MASK)
+/*! @} */
+
+/*! @name PERIODICLISTBASE - Periodic Frame List Base Address Register */
+/*! @{ */
+#define USBHS_PERIODICLISTBASE_PERBASE_MASK (0xFFFFF000U)
+#define USBHS_PERIODICLISTBASE_PERBASE_SHIFT (12U)
+#define USBHS_PERIODICLISTBASE_PERBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PERIODICLISTBASE_PERBASE_SHIFT)) & USBHS_PERIODICLISTBASE_PERBASE_MASK)
+/*! @} */
+
+/*! @name ASYNCLISTADDR - Current Asynchronous List Address Register */
+/*! @{ */
+#define USBHS_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U)
+#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT (5U)
+#define USBHS_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ASYNCLISTADDR_ASYBASE_SHIFT)) & USBHS_ASYNCLISTADDR_ASYBASE_MASK)
+/*! @} */
+
+/*! @name EPLISTADDR - Endpoint List Address Register */
+/*! @{ */
+#define USBHS_EPLISTADDR_EPBASE_MASK (0xFFFFF800U)
+#define USBHS_EPLISTADDR_EPBASE_SHIFT (11U)
+#define USBHS_EPLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPLISTADDR_EPBASE_SHIFT)) & USBHS_EPLISTADDR_EPBASE_MASK)
+/*! @} */
+
+/*! @name TTCTRL - Host TT Asynchronous Buffer Control */
+/*! @{ */
+#define USBHS_TTCTRL_TTHA_MASK (0x7F000000U)
+#define USBHS_TTCTRL_TTHA_SHIFT (24U)
+#define USBHS_TTCTRL_TTHA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TTCTRL_TTHA_SHIFT)) & USBHS_TTCTRL_TTHA_MASK)
+#define USBHS_TTCTRL_Reerved_MASK (0x80000000U)
+#define USBHS_TTCTRL_Reerved_SHIFT (31U)
+#define USBHS_TTCTRL_Reerved(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TTCTRL_Reerved_SHIFT)) & USBHS_TTCTRL_Reerved_MASK)
+/*! @} */
+
+/*! @name BURSTSIZE - Master Interface Data Burst Size Register */
+/*! @{ */
+#define USBHS_BURSTSIZE_RXPBURST_MASK (0xFFU)
+#define USBHS_BURSTSIZE_RXPBURST_SHIFT (0U)
+#define USBHS_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_RXPBURST_SHIFT)) & USBHS_BURSTSIZE_RXPBURST_MASK)
+#define USBHS_BURSTSIZE_TXPBURST_MASK (0xFF00U)
+#define USBHS_BURSTSIZE_TXPBURST_SHIFT (8U)
+#define USBHS_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_TXPBURST_SHIFT)) & USBHS_BURSTSIZE_TXPBURST_MASK)
+/*! @} */
+
+/*! @name TXFILLTUNING - Transmit FIFO Tuning Control Register */
+/*! @{ */
+#define USBHS_TXFILLTUNING_TXSCHOH_MASK (0x7FU)
+#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT (0U)
+#define USBHS_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHOH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHOH_MASK)
+#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U)
+#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U)
+#define USBHS_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHHEALTH_MASK)
+#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U)
+#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U)
+#define USBHS_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USBHS_TXFILLTUNING_TXFIFOTHRES_MASK)
+/*! @} */
+
+/*! @name ENDPTNAK - Endpoint NAK Register */
+/*! @{ */
+#define USBHS_ENDPTNAK_EPRN_MASK (0xFU)
+#define USBHS_ENDPTNAK_EPRN_SHIFT (0U)
+#define USBHS_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPRN_SHIFT)) & USBHS_ENDPTNAK_EPRN_MASK)
+#define USBHS_ENDPTNAK_EPTN_MASK (0xF0000U)
+#define USBHS_ENDPTNAK_EPTN_SHIFT (16U)
+#define USBHS_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPTN_SHIFT)) & USBHS_ENDPTNAK_EPTN_MASK)
+/*! @} */
+
+/*! @name ENDPTNAKEN - Endpoint NAK Enable Register */
+/*! @{ */
+#define USBHS_ENDPTNAKEN_EPRNE_MASK (0xFU)
+#define USBHS_ENDPTNAKEN_EPRNE_SHIFT (0U)
+#define USBHS_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPRNE_SHIFT)) & USBHS_ENDPTNAKEN_EPRNE_MASK)
+#define USBHS_ENDPTNAKEN_EPTNE_MASK (0xF0000U)
+#define USBHS_ENDPTNAKEN_EPTNE_SHIFT (16U)
+#define USBHS_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPTNE_SHIFT)) & USBHS_ENDPTNAKEN_EPTNE_MASK)
+/*! @} */
+
+/*! @name PORTSC1 - Port Status and Control Registers */
+/*! @{ */
+#define USBHS_PORTSC1_CCS_MASK (0x1U)
+#define USBHS_PORTSC1_CCS_SHIFT (0U)
+/*! CCS - Current Connect Status
+ * 0b0..No device present (host mode) or attached (device mode)
+ * 0b1..Device is present (host mode) or attached (device mode)
+ */
+#define USBHS_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CCS_SHIFT)) & USBHS_PORTSC1_CCS_MASK)
+#define USBHS_PORTSC1_CSC_MASK (0x2U)
+#define USBHS_PORTSC1_CSC_SHIFT (1U)
+/*! CSC - Connect Change Status
+ * 0b0..No change
+ * 0b1..Connect status has changed
+ */
+#define USBHS_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CSC_SHIFT)) & USBHS_PORTSC1_CSC_MASK)
+#define USBHS_PORTSC1_PE_MASK (0x4U)
+#define USBHS_PORTSC1_PE_SHIFT (2U)
+#define USBHS_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PE_SHIFT)) & USBHS_PORTSC1_PE_MASK)
+#define USBHS_PORTSC1_PEC_MASK (0x8U)
+#define USBHS_PORTSC1_PEC_SHIFT (3U)
+/*! PEC - Port Enable/disable Change
+ * 0b0..No change
+ * 0b1..Port disabled
+ */
+#define USBHS_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PEC_SHIFT)) & USBHS_PORTSC1_PEC_MASK)
+#define USBHS_PORTSC1_OCA_MASK (0x10U)
+#define USBHS_PORTSC1_OCA_SHIFT (4U)
+/*! OCA - Over-current active
+ * 0b0..Port not in over-current condition
+ * 0b1..Port currently in over-current condition
+ */
+#define USBHS_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCA_SHIFT)) & USBHS_PORTSC1_OCA_MASK)
+#define USBHS_PORTSC1_OCC_MASK (0x20U)
+#define USBHS_PORTSC1_OCC_SHIFT (5U)
+/*! OCC - Over-Current Change
+ * 0b0..No over-current
+ * 0b1..Over-current detect
+ */
+#define USBHS_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCC_SHIFT)) & USBHS_PORTSC1_OCC_MASK)
+#define USBHS_PORTSC1_FPR_MASK (0x40U)
+#define USBHS_PORTSC1_FPR_SHIFT (6U)
+/*! FPR - Force Port Resume
+ * 0b0..No resume (K-state) detected/driven on port
+ * 0b1..Resume detected/driven on port
+ */
+#define USBHS_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_FPR_SHIFT)) & USBHS_PORTSC1_FPR_MASK)
+#define USBHS_PORTSC1_SUSP_MASK (0x80U)
+#define USBHS_PORTSC1_SUSP_SHIFT (7U)
+/*! SUSP - Suspend
+ * 0b0..Port not in suspend state
+ * 0b1..Port in suspend state
+ */
+#define USBHS_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_SUSP_SHIFT)) & USBHS_PORTSC1_SUSP_MASK)
+#define USBHS_PORTSC1_PR_MASK (0x100U)
+#define USBHS_PORTSC1_PR_SHIFT (8U)
+/*! PR - Port Reset
+ * 0b0..Port is not in reset
+ * 0b1..Port is in reset
+ */
+#define USBHS_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PR_SHIFT)) & USBHS_PORTSC1_PR_MASK)
+#define USBHS_PORTSC1_HSP_MASK (0x200U)
+#define USBHS_PORTSC1_HSP_SHIFT (9U)
+/*! HSP - High Speed Port.
+ * 0b0..FS or LS
+ * 0b1..HS
+ */
+#define USBHS_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_HSP_SHIFT)) & USBHS_PORTSC1_HSP_MASK)
+#define USBHS_PORTSC1_LS_MASK (0xC00U)
+#define USBHS_PORTSC1_LS_SHIFT (10U)
+/*! LS - Line Status
+ * 0b00..SE0
+ * 0b01..J-state
+ * 0b10..K-state
+ * 0b11..Undefined
+ */
+#define USBHS_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_LS_SHIFT)) & USBHS_PORTSC1_LS_MASK)
+#define USBHS_PORTSC1_PP_MASK (0x1000U)
+#define USBHS_PORTSC1_PP_SHIFT (12U)
+#define USBHS_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PP_SHIFT)) & USBHS_PORTSC1_PP_MASK)
+#define USBHS_PORTSC1_PO_MASK (0x2000U)
+#define USBHS_PORTSC1_PO_SHIFT (13U)
+#define USBHS_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PO_SHIFT)) & USBHS_PORTSC1_PO_MASK)
+#define USBHS_PORTSC1_PIC_MASK (0xC000U)
+#define USBHS_PORTSC1_PIC_SHIFT (14U)
+#define USBHS_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PIC_SHIFT)) & USBHS_PORTSC1_PIC_MASK)
+#define USBHS_PORTSC1_PTC_MASK (0xF0000U)
+#define USBHS_PORTSC1_PTC_SHIFT (16U)
+/*! PTC - Port Test Control
+ * 0b0000..Not enabled
+ * 0b0001..J_STATE
+ * 0b0010..K_STATE
+ * 0b0011..SE0_NAK
+ * 0b0100..Packet
+ * 0b0101..FORCE_ENABLE_HS
+ * 0b0110..FORCE_ENABLE_FS
+ * 0b0111..FORCE_ENABLE_LS
+ */
+#define USBHS_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTC_SHIFT)) & USBHS_PORTSC1_PTC_MASK)
+#define USBHS_PORTSC1_WKCN_MASK (0x100000U)
+#define USBHS_PORTSC1_WKCN_SHIFT (20U)
+#define USBHS_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKCN_SHIFT)) & USBHS_PORTSC1_WKCN_MASK)
+#define USBHS_PORTSC1_WKDS_MASK (0x200000U)
+#define USBHS_PORTSC1_WKDS_SHIFT (21U)
+#define USBHS_PORTSC1_WKDS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKDS_SHIFT)) & USBHS_PORTSC1_WKDS_MASK)
+#define USBHS_PORTSC1_WKOC_MASK (0x400000U)
+#define USBHS_PORTSC1_WKOC_SHIFT (22U)
+#define USBHS_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKOC_SHIFT)) & USBHS_PORTSC1_WKOC_MASK)
+#define USBHS_PORTSC1_PHCD_MASK (0x800000U)
+#define USBHS_PORTSC1_PHCD_SHIFT (23U)
+#define USBHS_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PHCD_SHIFT)) & USBHS_PORTSC1_PHCD_MASK)
+#define USBHS_PORTSC1_PFSC_MASK (0x1000000U)
+#define USBHS_PORTSC1_PFSC_SHIFT (24U)
+/*! PFSC - Port force Full-Speed Connect
+ * 0b0..Allow the port to identify itself as high speed
+ * 0b1..Force the port to only connect at full speed
+ */
+#define USBHS_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PFSC_SHIFT)) & USBHS_PORTSC1_PFSC_MASK)
+#define USBHS_PORTSC1_PTS2_MASK (0x2000000U)
+#define USBHS_PORTSC1_PTS2_SHIFT (25U)
+#define USBHS_PORTSC1_PTS2(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS2_SHIFT)) & USBHS_PORTSC1_PTS2_MASK)
+#define USBHS_PORTSC1_PSPD_MASK (0xC000000U)
+#define USBHS_PORTSC1_PSPD_SHIFT (26U)
+/*! PSPD - Port Speed
+ * 0b00..Full speed
+ * 0b01..Low speed
+ * 0b10..High speed
+ * 0b11..Undefined
+ */
+#define USBHS_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PSPD_SHIFT)) & USBHS_PORTSC1_PSPD_MASK)
+#define USBHS_PORTSC1_PTS_MASK (0xC0000000U)
+#define USBHS_PORTSC1_PTS_SHIFT (30U)
+/*! PTS - Port Transceiver Select [1:0]
+ * 0b00..Use UTMI transceiver interface.
+ */
+#define USBHS_PORTSC1_PTS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_SHIFT)) & USBHS_PORTSC1_PTS_MASK)
+/*! @} */
+
+/*! @name OTGSC - On-the-Go Status and Control Register */
+/*! @{ */
+#define USBHS_OTGSC_VD_MASK (0x1U)
+#define USBHS_OTGSC_VD_SHIFT (0U)
+#define USBHS_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VD_SHIFT)) & USBHS_OTGSC_VD_MASK)
+#define USBHS_OTGSC_VC_MASK (0x2U)
+#define USBHS_OTGSC_VC_SHIFT (1U)
+#define USBHS_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VC_SHIFT)) & USBHS_OTGSC_VC_MASK)
+#define USBHS_OTGSC_HAAR_MASK (0x4U)
+#define USBHS_OTGSC_HAAR_SHIFT (2U)
+/*! HAAR - Hardware Assist Auto-Reset
+ * 0b0..Disabled.
+ * 0b1..Enable automatic reset after connect on host port.
+ */
+#define USBHS_OTGSC_HAAR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_HAAR_SHIFT)) & USBHS_OTGSC_HAAR_MASK)
+#define USBHS_OTGSC_OT_MASK (0x8U)
+#define USBHS_OTGSC_OT_SHIFT (3U)
+/*! OT - OTG Termination
+ * 0b0..Disable pull-down on DM
+ * 0b1..Enable pull-down on DM
+ */
+#define USBHS_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_OT_SHIFT)) & USBHS_OTGSC_OT_MASK)
+#define USBHS_OTGSC_DP_MASK (0x10U)
+#define USBHS_OTGSC_DP_SHIFT (4U)
+/*! DP - Data Pulsing
+ * 0b0..The pull-up on DP is not asserted
+ * 0b1..The pull-up on DP is asserted for data pulsing during SRP
+ */
+#define USBHS_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DP_SHIFT)) & USBHS_OTGSC_DP_MASK)
+#define USBHS_OTGSC_IDPU_MASK (0x20U)
+#define USBHS_OTGSC_IDPU_SHIFT (5U)
+/*! IDPU - ID Pull-Up
+ * 0b0..Disable pull-up. ID input not sampled.
+ * 0b1..Enable pull-up
+ */
+#define USBHS_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDPU_SHIFT)) & USBHS_OTGSC_IDPU_MASK)
+#define USBHS_OTGSC_HABA_MASK (0x80U)
+#define USBHS_OTGSC_HABA_SHIFT (7U)
+/*! HABA - Hardware Assist B-Disconnect to A-connect
+ * 0b0..Disabled.
+ * 0b1..Enable automatic B-disconnect to A-connect sequence.
+ */
+#define USBHS_OTGSC_HABA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_HABA_SHIFT)) & USBHS_OTGSC_HABA_MASK)
+#define USBHS_OTGSC_ID_MASK (0x100U)
+#define USBHS_OTGSC_ID_SHIFT (8U)
+/*! ID - USB ID
+ * 0b0..A device
+ * 0b1..B device
+ */
+#define USBHS_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ID_SHIFT)) & USBHS_OTGSC_ID_MASK)
+#define USBHS_OTGSC_AVV_MASK (0x200U)
+#define USBHS_OTGSC_AVV_SHIFT (9U)
+/*! AVV - A VBus Valid
+ * 0b0..VBus is below A VBus valid threshold
+ * 0b1..VBus is above A VBus valid threshold
+ */
+#define USBHS_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVV_SHIFT)) & USBHS_OTGSC_AVV_MASK)
+#define USBHS_OTGSC_ASV_MASK (0x400U)
+#define USBHS_OTGSC_ASV_SHIFT (10U)
+/*! ASV - A Session Valid
+ * 0b0..VBus is below A session valid threshold
+ * 0b1..VBus is above A session valid threshold
+ */
+#define USBHS_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASV_SHIFT)) & USBHS_OTGSC_ASV_MASK)
+#define USBHS_OTGSC_BSV_MASK (0x800U)
+#define USBHS_OTGSC_BSV_SHIFT (11U)
+/*! BSV - B Session Valid
+ * 0b0..VBus is below B session valid threshold
+ * 0b1..VBus is above B session valid threshold
+ */
+#define USBHS_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSV_SHIFT)) & USBHS_OTGSC_BSV_MASK)
+#define USBHS_OTGSC_BSE_MASK (0x1000U)
+#define USBHS_OTGSC_BSE_SHIFT (12U)
+/*! BSE - B Session End
+ * 0b0..VBus is above B session end threshold
+ * 0b1..VBus is below B session end threshold
+ */
+#define USBHS_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSE_SHIFT)) & USBHS_OTGSC_BSE_MASK)
+#define USBHS_OTGSC_MST_MASK (0x2000U)
+#define USBHS_OTGSC_MST_SHIFT (13U)
+#define USBHS_OTGSC_MST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MST_SHIFT)) & USBHS_OTGSC_MST_MASK)
+#define USBHS_OTGSC_DPS_MASK (0x4000U)
+#define USBHS_OTGSC_DPS_SHIFT (14U)
+/*! DPS - Data bus Pulsing Status
+ * 0b0..No pulsing on port
+ * 0b1..Pulsing detected on port
+ */
+#define USBHS_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPS_SHIFT)) & USBHS_OTGSC_DPS_MASK)
+#define USBHS_OTGSC_IDIS_MASK (0x10000U)
+#define USBHS_OTGSC_IDIS_SHIFT (16U)
+#define USBHS_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIS_SHIFT)) & USBHS_OTGSC_IDIS_MASK)
+#define USBHS_OTGSC_AVVIS_MASK (0x20000U)
+#define USBHS_OTGSC_AVVIS_SHIFT (17U)
+#define USBHS_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIS_SHIFT)) & USBHS_OTGSC_AVVIS_MASK)
+#define USBHS_OTGSC_ASVIS_MASK (0x40000U)
+#define USBHS_OTGSC_ASVIS_SHIFT (18U)
+#define USBHS_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIS_SHIFT)) & USBHS_OTGSC_ASVIS_MASK)
+#define USBHS_OTGSC_BSVIS_MASK (0x80000U)
+#define USBHS_OTGSC_BSVIS_SHIFT (19U)
+#define USBHS_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIS_SHIFT)) & USBHS_OTGSC_BSVIS_MASK)
+#define USBHS_OTGSC_BSEIS_MASK (0x100000U)
+#define USBHS_OTGSC_BSEIS_SHIFT (20U)
+#define USBHS_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIS_SHIFT)) & USBHS_OTGSC_BSEIS_MASK)
+#define USBHS_OTGSC_MSS_MASK (0x200000U)
+#define USBHS_OTGSC_MSS_SHIFT (21U)
+#define USBHS_OTGSC_MSS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MSS_SHIFT)) & USBHS_OTGSC_MSS_MASK)
+#define USBHS_OTGSC_DPIS_MASK (0x400000U)
+#define USBHS_OTGSC_DPIS_SHIFT (22U)
+#define USBHS_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIS_SHIFT)) & USBHS_OTGSC_DPIS_MASK)
+#define USBHS_OTGSC_IDIE_MASK (0x1000000U)
+#define USBHS_OTGSC_IDIE_SHIFT (24U)
+/*! IDIE - USB ID Interrupt Enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define USBHS_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIE_SHIFT)) & USBHS_OTGSC_IDIE_MASK)
+#define USBHS_OTGSC_AVVIE_MASK (0x2000000U)
+#define USBHS_OTGSC_AVVIE_SHIFT (25U)
+/*! AVVIE - A VBUS Valid Interrupt Enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define USBHS_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIE_SHIFT)) & USBHS_OTGSC_AVVIE_MASK)
+#define USBHS_OTGSC_ASVIE_MASK (0x4000000U)
+#define USBHS_OTGSC_ASVIE_SHIFT (26U)
+/*! ASVIE - A Session Valid Interrupt Enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define USBHS_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIE_SHIFT)) & USBHS_OTGSC_ASVIE_MASK)
+#define USBHS_OTGSC_BSVIE_MASK (0x8000000U)
+#define USBHS_OTGSC_BSVIE_SHIFT (27U)
+/*! BSVIE - B Session Valid Interrupt Enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define USBHS_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIE_SHIFT)) & USBHS_OTGSC_BSVIE_MASK)
+#define USBHS_OTGSC_BSEIE_MASK (0x10000000U)
+#define USBHS_OTGSC_BSEIE_SHIFT (28U)
+/*! BSEIE - B Session End Interrupt Enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define USBHS_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIE_SHIFT)) & USBHS_OTGSC_BSEIE_MASK)
+#define USBHS_OTGSC_MSE_MASK (0x20000000U)
+#define USBHS_OTGSC_MSE_SHIFT (29U)
+/*! MSE - 1 Milli-Second timer interrupt Enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define USBHS_OTGSC_MSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MSE_SHIFT)) & USBHS_OTGSC_MSE_MASK)
+#define USBHS_OTGSC_DPIE_MASK (0x40000000U)
+#define USBHS_OTGSC_DPIE_SHIFT (30U)
+/*! DPIE - Data Pulse Interrupt Enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define USBHS_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIE_SHIFT)) & USBHS_OTGSC_DPIE_MASK)
+/*! @} */
+
+/*! @name USBMODE - USB Mode Register */
+/*! @{ */
+#define USBHS_USBMODE_CM_MASK (0x3U)
+#define USBHS_USBMODE_CM_SHIFT (0U)
+/*! CM - Controller Mode
+ * 0b00..Idle (default for the USBHS module)
+ * 0b01..Reserved
+ * 0b10..Device controller
+ * 0b11..Host controller
+ */
+#define USBHS_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_CM_SHIFT)) & USBHS_USBMODE_CM_MASK)
+#define USBHS_USBMODE_ES_MASK (0x4U)
+#define USBHS_USBMODE_ES_SHIFT (2U)
+/*! ES - Endian Select
+ * 0b0..Little endian. First byte referenced in least significant byte of 32-bit word.
+ * 0b1..Big endian. First byte referenced in most significant byte of 32-bit word.
+ */
+#define USBHS_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_ES_SHIFT)) & USBHS_USBMODE_ES_MASK)
+#define USBHS_USBMODE_SLOM_MASK (0x8U)
+#define USBHS_USBMODE_SLOM_SHIFT (3U)
+#define USBHS_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SLOM_SHIFT)) & USBHS_USBMODE_SLOM_MASK)
+#define USBHS_USBMODE_SDIS_MASK (0x10U)
+#define USBHS_USBMODE_SDIS_SHIFT (4U)
+/*! SDIS - Stream DISable
+ * 0b0..Inactive
+ * 0b1..Active
+ */
+#define USBHS_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SDIS_SHIFT)) & USBHS_USBMODE_SDIS_MASK)
+#define USBHS_USBMODE_TXHSD_MASK (0x7000U)
+#define USBHS_USBMODE_TXHSD_SHIFT (12U)
+/*! TXHSD - Tx to Tx HS Delay
+ * 0b000..10
+ * 0b001..11
+ * 0b010..12
+ * 0b011..13
+ * 0b100..14
+ * 0b101..15
+ * 0b110..16
+ * 0b111..17
+ */
+#define USBHS_USBMODE_TXHSD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_TXHSD_SHIFT)) & USBHS_USBMODE_TXHSD_MASK)
+/*! @} */
+
+/*! @name EPSETUPSR - Endpoint Setup Status Register */
+/*! @{ */
+#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK (0xFU)
+#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT (0U)
+#define USBHS_EPSETUPSR_EPSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT)) & USBHS_EPSETUPSR_EPSETUPSTAT_MASK)
+/*! @} */
+
+/*! @name EPPRIME - Endpoint Initialization Register */
+/*! @{ */
+#define USBHS_EPPRIME_PERB_MASK (0xFU)
+#define USBHS_EPPRIME_PERB_SHIFT (0U)
+#define USBHS_EPPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPPRIME_PERB_SHIFT)) & USBHS_EPPRIME_PERB_MASK)
+#define USBHS_EPPRIME_PETB_MASK (0xF0000U)
+#define USBHS_EPPRIME_PETB_SHIFT (16U)
+#define USBHS_EPPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPPRIME_PETB_SHIFT)) & USBHS_EPPRIME_PETB_MASK)
+/*! @} */
+
+/*! @name EPFLUSH - Endpoint Flush Register */
+/*! @{ */
+#define USBHS_EPFLUSH_FERB_MASK (0xFU)
+#define USBHS_EPFLUSH_FERB_SHIFT (0U)
+#define USBHS_EPFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPFLUSH_FERB_SHIFT)) & USBHS_EPFLUSH_FERB_MASK)
+#define USBHS_EPFLUSH_FETB_MASK (0xF0000U)
+#define USBHS_EPFLUSH_FETB_SHIFT (16U)
+#define USBHS_EPFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPFLUSH_FETB_SHIFT)) & USBHS_EPFLUSH_FETB_MASK)
+/*! @} */
+
+/*! @name EPSR - Endpoint Status Register */
+/*! @{ */
+#define USBHS_EPSR_ERBR_MASK (0xFU)
+#define USBHS_EPSR_ERBR_SHIFT (0U)
+#define USBHS_EPSR_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPSR_ERBR_SHIFT)) & USBHS_EPSR_ERBR_MASK)
+#define USBHS_EPSR_ETBR_MASK (0xF0000U)
+#define USBHS_EPSR_ETBR_SHIFT (16U)
+#define USBHS_EPSR_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPSR_ETBR_SHIFT)) & USBHS_EPSR_ETBR_MASK)
+/*! @} */
+
+/*! @name EPCOMPLETE - Endpoint Complete Register */
+/*! @{ */
+#define USBHS_EPCOMPLETE_ERCE_MASK (0xFU)
+#define USBHS_EPCOMPLETE_ERCE_SHIFT (0U)
+#define USBHS_EPCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCOMPLETE_ERCE_SHIFT)) & USBHS_EPCOMPLETE_ERCE_MASK)
+#define USBHS_EPCOMPLETE_ETCE_MASK (0xF0000U)
+#define USBHS_EPCOMPLETE_ETCE_SHIFT (16U)
+#define USBHS_EPCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCOMPLETE_ETCE_SHIFT)) & USBHS_EPCOMPLETE_ETCE_MASK)
+/*! @} */
+
+/*! @name EPCR0 - Endpoint Control Register 0 */
+/*! @{ */
+#define USBHS_EPCR0_RXS_MASK (0x1U)
+#define USBHS_EPCR0_RXS_SHIFT (0U)
+/*! RXS - RX endpoint Stall
+ * 0b0..Endpoint OK
+ * 0b1..Endpoint stalled
+ */
+#define USBHS_EPCR0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXS_SHIFT)) & USBHS_EPCR0_RXS_MASK)
+#define USBHS_EPCR0_RXT_MASK (0xCU)
+#define USBHS_EPCR0_RXT_SHIFT (2U)
+/*! RXT - RX endpoint Type
+ * 0b00..Control
+ */
+#define USBHS_EPCR0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXT_SHIFT)) & USBHS_EPCR0_RXT_MASK)
+#define USBHS_EPCR0_RXE_MASK (0x80U)
+#define USBHS_EPCR0_RXE_SHIFT (7U)
+/*! RXE - RX endpoint Enable
+ * 0b1..Enabled
+ */
+#define USBHS_EPCR0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXE_SHIFT)) & USBHS_EPCR0_RXE_MASK)
+#define USBHS_EPCR0_TXS_MASK (0x10000U)
+#define USBHS_EPCR0_TXS_SHIFT (16U)
+/*! TXS - TX Endpoint Stall
+ * 0b0..Endpoint OK
+ * 0b1..Endpoint stalled
+ */
+#define USBHS_EPCR0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXS_SHIFT)) & USBHS_EPCR0_TXS_MASK)
+#define USBHS_EPCR0_TXT_MASK (0xC0000U)
+#define USBHS_EPCR0_TXT_SHIFT (18U)
+/*! TXT - TX Endpoint Type
+ * 0b00..Control
+ */
+#define USBHS_EPCR0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXT_SHIFT)) & USBHS_EPCR0_TXT_MASK)
+#define USBHS_EPCR0_TXE_MASK (0x800000U)
+#define USBHS_EPCR0_TXE_SHIFT (23U)
+/*! TXE - TX Endpoint Enable
+ * 0b1..Enable
+ */
+#define USBHS_EPCR0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXE_SHIFT)) & USBHS_EPCR0_TXE_MASK)
+/*! @} */
+
+/*! @name EPCR - Endpoint Control Register n */
+/*! @{ */
+#define USBHS_EPCR_RXS_MASK (0x1U)
+#define USBHS_EPCR_RXS_SHIFT (0U)
+/*! RXS - RX endpoint Stall
+ * 0b0..Endpoint OK
+ * 0b1..Endpoint stalled
+ */
+#define USBHS_EPCR_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXS_SHIFT)) & USBHS_EPCR_RXS_MASK)
+#define USBHS_EPCR_RXD_MASK (0x2U)
+#define USBHS_EPCR_RXD_SHIFT (1U)
+#define USBHS_EPCR_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXD_SHIFT)) & USBHS_EPCR_RXD_MASK)
+#define USBHS_EPCR_RXT_MASK (0xCU)
+#define USBHS_EPCR_RXT_SHIFT (2U)
+/*! RXT - RX endpoint Type
+ * 0b00..Control
+ * 0b01..Isochronous
+ * 0b10..Bulk
+ * 0b11..Interrupt
+ */
+#define USBHS_EPCR_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXT_SHIFT)) & USBHS_EPCR_RXT_MASK)
+#define USBHS_EPCR_RXI_MASK (0x20U)
+#define USBHS_EPCR_RXI_SHIFT (5U)
+/*! RXI - RX data toggle Inhibit
+ * 0b0..PID sequencing enabled
+ * 0b1..PID sequencing disabled
+ */
+#define USBHS_EPCR_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXI_SHIFT)) & USBHS_EPCR_RXI_MASK)
+#define USBHS_EPCR_RXR_MASK (0x40U)
+#define USBHS_EPCR_RXR_SHIFT (6U)
+#define USBHS_EPCR_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXR_SHIFT)) & USBHS_EPCR_RXR_MASK)
+#define USBHS_EPCR_RXE_MASK (0x80U)
+#define USBHS_EPCR_RXE_SHIFT (7U)
+/*! RXE - RX endpoint Enable
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define USBHS_EPCR_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXE_SHIFT)) & USBHS_EPCR_RXE_MASK)
+#define USBHS_EPCR_TXS_MASK (0x10000U)
+#define USBHS_EPCR_TXS_SHIFT (16U)
+/*! TXS - TX endpoint Stall
+ * 0b0..Endpoint OK
+ * 0b1..Endpoint stalled
+ */
+#define USBHS_EPCR_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXS_SHIFT)) & USBHS_EPCR_TXS_MASK)
+#define USBHS_EPCR_TXD_MASK (0x20000U)
+#define USBHS_EPCR_TXD_SHIFT (17U)
+#define USBHS_EPCR_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXD_SHIFT)) & USBHS_EPCR_TXD_MASK)
+#define USBHS_EPCR_TXT_MASK (0xC0000U)
+#define USBHS_EPCR_TXT_SHIFT (18U)
+/*! TXT - TX endpoint Type
+ * 0b00..Control
+ * 0b01..Isochronous
+ * 0b10..Bulk
+ * 0b11..Interrupt
+ */
+#define USBHS_EPCR_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXT_SHIFT)) & USBHS_EPCR_TXT_MASK)
+#define USBHS_EPCR_TXI_MASK (0x200000U)
+#define USBHS_EPCR_TXI_SHIFT (21U)
+/*! TXI - TX data toggle Inhibit
+ * 0b0..PID sequencing enabled
+ * 0b1..PID sequencing disabled
+ */
+#define USBHS_EPCR_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXI_SHIFT)) & USBHS_EPCR_TXI_MASK)
+#define USBHS_EPCR_TXR_MASK (0x400000U)
+#define USBHS_EPCR_TXR_SHIFT (22U)
+#define USBHS_EPCR_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXR_SHIFT)) & USBHS_EPCR_TXR_MASK)
+#define USBHS_EPCR_TXE_MASK (0x800000U)
+#define USBHS_EPCR_TXE_SHIFT (23U)
+/*! TXE - TX endpoint Enable
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define USBHS_EPCR_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXE_SHIFT)) & USBHS_EPCR_TXE_MASK)
+/*! @} */
+
+/* The count of USBHS_EPCR */
+#define USBHS_EPCR_COUNT (7U)
+
+/*! @name USBGENCTRL - USB General Control Register */
+/*! @{ */
+#define USBHS_USBGENCTRL_WU_IE_MASK (0x1U)
+#define USBHS_USBGENCTRL_WU_IE_SHIFT (0U)
+/*! WU_IE - Wakeup Interrupt Enable
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define USBHS_USBGENCTRL_WU_IE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBGENCTRL_WU_IE_SHIFT)) & USBHS_USBGENCTRL_WU_IE_MASK)
+#define USBHS_USBGENCTRL_WU_INT_CLR_MASK (0x20U)
+#define USBHS_USBGENCTRL_WU_INT_CLR_SHIFT (5U)
+/*! WU_INT_CLR - Wakeup Interrupt Clear
+ * 0b0..Default, no action.
+ * 0b1..Clear the wake-up interrupt.
+ */
+#define USBHS_USBGENCTRL_WU_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBGENCTRL_WU_INT_CLR_SHIFT)) & USBHS_USBGENCTRL_WU_INT_CLR_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USBHS_Register_Masks */
+
+
+/* USBHS - Peripheral instance base addresses */
+/** Peripheral USBHS base address */
+#define USBHS_BASE (0x400A1000u)
+/** Peripheral USBHS base pointer */
+#define USBHS ((USBHS_Type *)USBHS_BASE)
+/** Array initializer of USBHS peripheral base addresses */
+#define USBHS_BASE_ADDRS { USBHS_BASE }
+/** Array initializer of USBHS peripheral base pointers */
+#define USBHS_BASE_PTRS { USBHS }
+/** Interrupt vectors for the USBHS peripheral type */
+#define USBHS_IRQS { USBHS_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBHS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBHSDCD Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSDCD_Peripheral_Access_Layer USBHSDCD Peripheral Access Layer
+ * @{
+ */
+
+/** USBHSDCD - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
+ __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
+ __I uint32_t STATUS; /**< Status register, offset: 0x8 */
+ __IO uint32_t SIGNAL_OVERRIDE; /**< Signal Override Register, offset: 0xC */
+ __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
+ __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
+ union { /* offset: 0x18 */
+ __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
+ __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
+ };
+} USBHSDCD_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USBHSDCD Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSDCD_Register_Masks USBHSDCD Register Masks
+ * @{
+ */
+
+/*! @name CONTROL - Control register */
+/*! @{ */
+#define USBHSDCD_CONTROL_IACK_MASK (0x1U)
+#define USBHSDCD_CONTROL_IACK_SHIFT (0U)
+/*! IACK - Interrupt Acknowledge
+ * 0b0..Do not clear the interrupt.
+ * 0b1..Clear the IF bit (interrupt flag).
+ */
+#define USBHSDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK)
+#define USBHSDCD_CONTROL_IF_MASK (0x100U)
+#define USBHSDCD_CONTROL_IF_SHIFT (8U)
+/*! IF - Interrupt Flag
+ * 0b0..No interrupt is pending.
+ * 0b1..An interrupt is pending.
+ */
+#define USBHSDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK)
+#define USBHSDCD_CONTROL_IE_MASK (0x10000U)
+#define USBHSDCD_CONTROL_IE_SHIFT (16U)
+/*! IE - Interrupt Enable
+ * 0b0..Disable interrupts to the system.
+ * 0b1..Enable interrupts to the system.
+ */
+#define USBHSDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK)
+#define USBHSDCD_CONTROL_BC12_MASK (0x20000U)
+#define USBHSDCD_CONTROL_BC12_SHIFT (17U)
+/*! BC12
+ * 0b0..Compatible with BC1.1 (default)
+ * 0b1..Compatible with BC1.2
+ */
+#define USBHSDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK)
+#define USBHSDCD_CONTROL_START_MASK (0x1000000U)
+#define USBHSDCD_CONTROL_START_SHIFT (24U)
+/*! START - Start Change Detection Sequence
+ * 0b0..Do not start the sequence. Writes of this value have no effect.
+ * 0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect.
+ */
+#define USBHSDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK)
+#define USBHSDCD_CONTROL_SR_MASK (0x2000000U)
+#define USBHSDCD_CONTROL_SR_SHIFT (25U)
+/*! SR - Software Reset
+ * 0b0..Do not perform a software reset.
+ * 0b1..Perform a software reset.
+ */
+#define USBHSDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK)
+/*! @} */
+
+/*! @name CLOCK - Clock register */
+/*! @{ */
+#define USBHSDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)
+#define USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)
+/*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed
+ * 0b0..kHz Speed (between 1 kHz and 1023 kHz)
+ * 0b1..MHz Speed (between 1 MHz and 1023 MHz)
+ */
+#define USBHSDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK)
+#define USBHSDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)
+#define USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)
+#define USBHSDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK)
+/*! @} */
+
+/*! @name STATUS - Status register */
+/*! @{ */
+#define USBHSDCD_STATUS_SEQ_RES_MASK (0x30000U)
+#define USBHSDCD_STATUS_SEQ_RES_SHIFT (16U)
+/*! SEQ_RES - Charger Detection Sequence Results
+ * 0b00..No results to report.
+ * 0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected.
+ * 0b10..Attached to a charging port. The exact meaning depends on bit 18: 0: Attached to either a CDP or a DCP. The charger type detection has not completed. 1: Attached to a CDP. The charger type detection has completed.
+ * 0b11..Attached to a DCP.
+ */
+#define USBHSDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK)
+#define USBHSDCD_STATUS_SEQ_STAT_MASK (0xC0000U)
+#define USBHSDCD_STATUS_SEQ_STAT_SHIFT (18U)
+/*! SEQ_STAT - Charger Detection Sequence Status
+ * 0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected.
+ * 0b01..Data pin contact detection is complete.
+ * 0b10..Charging port detection is complete.
+ * 0b11..Charger type detection is complete.
+ */
+#define USBHSDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK)
+#define USBHSDCD_STATUS_ERR_MASK (0x100000U)
+#define USBHSDCD_STATUS_ERR_SHIFT (20U)
+/*! ERR - Error Flag
+ * 0b0..No sequence errors.
+ * 0b1..Error in the detection sequence. See the SEQ_STAT field to determine the phase in which the error occurred.
+ */
+#define USBHSDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK)
+#define USBHSDCD_STATUS_TO_MASK (0x200000U)
+#define USBHSDCD_STATUS_TO_SHIFT (21U)
+/*! TO - Timeout Flag
+ * 0b0..The detection sequence has not been running for over 1 s.
+ * 0b1..It has been over 1 s since the data pin contact was detected and debounced.
+ */
+#define USBHSDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK)
+#define USBHSDCD_STATUS_ACTIVE_MASK (0x400000U)
+#define USBHSDCD_STATUS_ACTIVE_SHIFT (22U)
+/*! ACTIVE - Active Status Indicator
+ * 0b0..The sequence is not running.
+ * 0b1..The sequence is running.
+ */
+#define USBHSDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK)
+/*! @} */
+
+/*! @name SIGNAL_OVERRIDE - Signal Override Register */
+/*! @{ */
+#define USBHSDCD_SIGNAL_OVERRIDE_PS_MASK (0x3U)
+#define USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U)
+/*! PS - Phase Selection
+ * 0b00..No overrides. Bit field must remain at this value during normal USB data communication to prevent unexpected conditions on USB_DP and USB_DM pins. (Default)
+ * 0b01..Reserved, not for customer use.
+ * 0b10..Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin.
+ * 0b11..Reserved, not for customer use.
+ */
+#define USBHSDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK)
+/*! @} */
+
+/*! @name TIMER0 - TIMER0 register */
+/*! @{ */
+#define USBHSDCD_TIMER0_TUNITCON_MASK (0xFFFU)
+#define USBHSDCD_TIMER0_TUNITCON_SHIFT (0U)
+#define USBHSDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK)
+#define USBHSDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)
+#define USBHSDCD_TIMER0_TSEQ_INIT_SHIFT (16U)
+#define USBHSDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK)
+/*! @} */
+
+/*! @name TIMER1 - TIMER1 register */
+/*! @{ */
+#define USBHSDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)
+#define USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)
+#define USBHSDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBHSDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)
+#define USBHSDCD_TIMER1_TDCD_DBNC_SHIFT (16U)
+#define USBHSDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK)
+/*! @} */
+
+/*! @name TIMER2_BC11 - TIMER2_BC11 register */
+/*! @{ */
+#define USBHSDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU)
+#define USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U)
+#define USBHSDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK)
+#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U)
+#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U)
+#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
+/*! @} */
+
+/*! @name TIMER2_BC12 - TIMER2_BC12 register */
+/*! @{ */
+#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU)
+#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U)
+#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
+#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
+#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
+#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USBHSDCD_Register_Masks */
+
+
+/* USBHSDCD - Peripheral instance base addresses */
+/** Peripheral USBHSDCD base address */
+#define USBHSDCD_BASE (0x400A3000u)
+/** Peripheral USBHSDCD base pointer */
+#define USBHSDCD ((USBHSDCD_Type *)USBHSDCD_BASE)
+/** Array initializer of USBHSDCD peripheral base addresses */
+#define USBHSDCD_BASE_ADDRS { USBHSDCD_BASE }
+/** Array initializer of USBHSDCD peripheral base pointers */
+#define USBHSDCD_BASE_PTRS { USBHSDCD }
+/** Interrupt vectors for the USBHSDCD peripheral type */
+#define USBHSDCD_IRQS { USBHSDCD_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBHSDCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBPHY Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer
+ * @{
+ */
+
+/** USBPHY - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */
+ __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */
+ __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */
+ __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */
+ __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */
+ __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */
+ __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */
+ __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */
+ __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */
+ __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */
+ __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */
+ __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */
+ __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */
+ __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */
+ __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */
+ __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */
+ __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t DEBUGr; /**< USB PHY Debug Register, offset: 0x50 */
+ __IO uint32_t DEBUG_SET; /**< USB PHY Debug Register, offset: 0x54 */
+ __IO uint32_t DEBUG_CLR; /**< USB PHY Debug Register, offset: 0x58 */
+ __IO uint32_t DEBUG_TOG; /**< USB PHY Debug Register, offset: 0x5C */
+ __I uint32_t DEBUG0_STATUS; /**< UTMI Debug Status Register 0, offset: 0x60 */
+ uint8_t RESERVED_1[12];
+ __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */
+ __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */
+ __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */
+ __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */
+ __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */
+ uint8_t RESERVED_2[28];
+ __IO uint32_t PLL_SIC; /**< USB PHY PLL Control/Status Register, offset: 0xA0 */
+ __IO uint32_t PLL_SIC_SET; /**< USB PHY PLL Control/Status Register, offset: 0xA4 */
+ __IO uint32_t PLL_SIC_CLR; /**< USB PHY PLL Control/Status Register, offset: 0xA8 */
+ __IO uint32_t PLL_SIC_TOG; /**< USB PHY PLL Control/Status Register, offset: 0xAC */
+ uint8_t RESERVED_3[16];
+ __IO uint32_t USB1_VBUS_DETECT; /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */
+ __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */
+ __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */
+ __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB PHY VBUS Detect Control Register, offset: 0xCC */
+ __I uint32_t USB1_VBUS_DET_STAT; /**< USB PHY VBUS Detector Status Register, offset: 0xD0 */
+ uint8_t RESERVED_4[28];
+ __I uint32_t USB1_CHRG_DET_STAT; /**< USB PHY Charger Detect Status Register, offset: 0xF0 */
+ uint8_t RESERVED_5[12];
+ __IO uint32_t ANACTRL; /**< USB PHY Analog Control Register, offset: 0x100 */
+ __IO uint32_t ANACTRL_SET; /**< USB PHY Analog Control Register, offset: 0x104 */
+ __IO uint32_t ANACTRL_CLR; /**< USB PHY Analog Control Register, offset: 0x108 */
+ __IO uint32_t ANACTRL_TOG; /**< USB PHY Analog Control Register, offset: 0x10C */
+ __IO uint32_t USB1_LOOPBACK; /**< USB PHY Loopback Control/Status Register, offset: 0x110 */
+ __IO uint32_t USB1_LOOPBACK_SET; /**< USB PHY Loopback Control/Status Register, offset: 0x114 */
+ __IO uint32_t USB1_LOOPBACK_CLR; /**< USB PHY Loopback Control/Status Register, offset: 0x118 */
+ __IO uint32_t USB1_LOOPBACK_TOG; /**< USB PHY Loopback Control/Status Register, offset: 0x11C */
+ __IO uint32_t USB1_LOOPBACK_HSFSCNT; /**< USB PHY Loopback Packet Number Select Register, offset: 0x120 */
+ __IO uint32_t USB1_LOOPBACK_HSFSCNT_SET; /**< USB PHY Loopback Packet Number Select Register, offset: 0x124 */
+ __IO uint32_t USB1_LOOPBACK_HSFSCNT_CLR; /**< USB PHY Loopback Packet Number Select Register, offset: 0x128 */
+ __IO uint32_t USB1_LOOPBACK_HSFSCNT_TOG; /**< USB PHY Loopback Packet Number Select Register, offset: 0x12C */
+ __IO uint32_t TRIM_OVERRIDE_EN; /**< USB PHY Trim Override Enable Register, offset: 0x130 */
+ __IO uint32_t TRIM_OVERRIDE_EN_SET; /**< USB PHY Trim Override Enable Register, offset: 0x134 */
+ __IO uint32_t TRIM_OVERRIDE_EN_CLR; /**< USB PHY Trim Override Enable Register, offset: 0x138 */
+ __IO uint32_t TRIM_OVERRIDE_EN_TOG; /**< USB PHY Trim Override Enable Register, offset: 0x13C */
+} USBPHY_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USBPHY Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBPHY_Register_Masks USBPHY Register Masks
+ * @{
+ */
+
+/*! @name PWD - USB PHY Power-Down Register */
+/*! @{ */
+#define USBPHY_PWD_TXPWDFS_MASK (0x400U)
+#define USBPHY_PWD_TXPWDFS_SHIFT (10U)
+/*! TXPWDFS
+ * 0b0..Normal operation.
+ * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output
+ */
+#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
+#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U)
+#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U)
+/*! TXPWDIBIAS
+ * 0b0..Normal operation
+ * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB is in suspend mode. This effectively powers down the entire USB transmit path
+ */
+#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
+#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U)
+#define USBPHY_PWD_TXPWDV2I_SHIFT (12U)
+/*! TXPWDV2I
+ * 0b0..Normal operation.
+ * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
+ */
+#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
+#define USBPHY_PWD_RXPWDENV_MASK (0x20000U)
+#define USBPHY_PWD_RXPWDENV_SHIFT (17U)
+/*! RXPWDENV
+ * 0b0..Normal operation.
+ * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)
+ */
+#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
+#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U)
+#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U)
+/*! RXPWD1PT1
+ * 0b0..Normal operation
+ * 0b1..Power-down the USB full-speed differential receiver.
+ */
+#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
+#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U)
+#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U)
+/*! RXPWDDIFF
+ * 0b0..Normal operation.
+ * 0b1..Power-down the USB high-speed differential receiver
+ */
+#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
+#define USBPHY_PWD_RXPWDRX_MASK (0x100000U)
+#define USBPHY_PWD_RXPWDRX_SHIFT (20U)
+/*! RXPWDRX
+ * 0b0..Normal operation
+ * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
+ */
+#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
+/*! @} */
+
+/*! @name PWD_SET - USB PHY Power-Down Register */
+/*! @{ */
+#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U)
+#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U)
+/*! TXPWDFS
+ * 0b0..Normal operation.
+ * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output
+ */
+#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
+#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U)
+#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U)
+/*! TXPWDIBIAS
+ * 0b0..Normal operation
+ * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB is in suspend mode. This effectively powers down the entire USB transmit path
+ */
+#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
+#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U)
+#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U)
+/*! TXPWDV2I
+ * 0b0..Normal operation.
+ * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
+ */
+#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
+#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U)
+#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U)
+/*! RXPWDENV
+ * 0b0..Normal operation.
+ * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)
+ */
+#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
+#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U)
+#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U)
+/*! RXPWD1PT1
+ * 0b0..Normal operation
+ * 0b1..Power-down the USB full-speed differential receiver.
+ */
+#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
+#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U)
+#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U)
+/*! RXPWDDIFF
+ * 0b0..Normal operation.
+ * 0b1..Power-down the USB high-speed differential receiver
+ */
+#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
+#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U)
+#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U)
+/*! RXPWDRX
+ * 0b0..Normal operation
+ * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
+ */
+#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
+/*! @} */
+
+/*! @name PWD_CLR - USB PHY Power-Down Register */
+/*! @{ */
+#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U)
+#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U)
+/*! TXPWDFS
+ * 0b0..Normal operation.
+ * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output
+ */
+#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
+#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U)
+#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U)
+/*! TXPWDIBIAS
+ * 0b0..Normal operation
+ * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB is in suspend mode. This effectively powers down the entire USB transmit path
+ */
+#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
+#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U)
+#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U)
+/*! TXPWDV2I
+ * 0b0..Normal operation.
+ * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
+ */
+#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
+#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U)
+#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U)
+/*! RXPWDENV
+ * 0b0..Normal operation.
+ * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)
+ */
+#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
+#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U)
+#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U)
+/*! RXPWD1PT1
+ * 0b0..Normal operation
+ * 0b1..Power-down the USB full-speed differential receiver.
+ */
+#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
+#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U)
+#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U)
+/*! RXPWDDIFF
+ * 0b0..Normal operation.
+ * 0b1..Power-down the USB high-speed differential receiver
+ */
+#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
+#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U)
+#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U)
+/*! RXPWDRX
+ * 0b0..Normal operation
+ * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
+ */
+#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
+/*! @} */
+
+/*! @name PWD_TOG - USB PHY Power-Down Register */
+/*! @{ */
+#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U)
+#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U)
+/*! TXPWDFS
+ * 0b0..Normal operation.
+ * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output
+ */
+#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
+#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U)
+#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U)
+/*! TXPWDIBIAS
+ * 0b0..Normal operation
+ * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB is in suspend mode. This effectively powers down the entire USB transmit path
+ */
+#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
+#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U)
+#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U)
+/*! TXPWDV2I
+ * 0b0..Normal operation.
+ * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
+ */
+#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
+#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U)
+#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U)
+/*! RXPWDENV
+ * 0b0..Normal operation.
+ * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)
+ */
+#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
+#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U)
+#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U)
+/*! RXPWD1PT1
+ * 0b0..Normal operation
+ * 0b1..Power-down the USB full-speed differential receiver.
+ */
+#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
+#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U)
+#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U)
+/*! RXPWDDIFF
+ * 0b0..Normal operation.
+ * 0b1..Power-down the USB high-speed differential receiver
+ */
+#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
+#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U)
+#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U)
+/*! RXPWDRX
+ * 0b0..Normal operation
+ * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
+ */
+#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
+/*! @} */
+
+/*! @name TX - USB PHY Transmitter Control Register */
+/*! @{ */
+#define USBPHY_TX_D_CAL_MASK (0xFU)
+#define USBPHY_TX_D_CAL_SHIFT (0U)
+/*! D_CAL
+ * 0b0000..Maximum current, approximately 19% above nominal.
+ * 0b0111..Nominal
+ * 0b1111..Minimum current, approximately 19% below nominal.
+ */
+#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
+#define USBPHY_TX_TXCAL45DM_MASK (0xF00U)
+#define USBPHY_TX_TXCAL45DM_SHIFT (8U)
+#define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK)
+#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U)
+#define USBPHY_TX_TXCAL45DP_SHIFT (16U)
+#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
+#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
+#define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U)
+#define USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK)
+/*! @} */
+
+/*! @name TX_SET - USB PHY Transmitter Control Register */
+/*! @{ */
+#define USBPHY_TX_SET_D_CAL_MASK (0xFU)
+#define USBPHY_TX_SET_D_CAL_SHIFT (0U)
+/*! D_CAL
+ * 0b0000..Maximum current, approximately 19% above nominal.
+ * 0b0111..Nominal
+ * 0b1111..Minimum current, approximately 19% below nominal.
+ */
+#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
+#define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U)
+#define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U)
+#define USBPHY_TX_SET_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK)
+#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U)
+#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U)
+#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
+#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
+#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U)
+#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK)
+/*! @} */
+
+/*! @name TX_CLR - USB PHY Transmitter Control Register */
+/*! @{ */
+#define USBPHY_TX_CLR_D_CAL_MASK (0xFU)
+#define USBPHY_TX_CLR_D_CAL_SHIFT (0U)
+/*! D_CAL
+ * 0b0000..Maximum current, approximately 19% above nominal.
+ * 0b0111..Nominal
+ * 0b1111..Minimum current, approximately 19% below nominal.
+ */
+#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
+#define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U)
+#define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U)
+#define USBPHY_TX_CLR_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK)
+#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U)
+#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U)
+#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
+#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
+#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U)
+#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK)
+/*! @} */
+
+/*! @name TX_TOG - USB PHY Transmitter Control Register */
+/*! @{ */
+#define USBPHY_TX_TOG_D_CAL_MASK (0xFU)
+#define USBPHY_TX_TOG_D_CAL_SHIFT (0U)
+/*! D_CAL
+ * 0b0000..Maximum current, approximately 19% above nominal.
+ * 0b0111..Nominal
+ * 0b1111..Minimum current, approximately 19% below nominal.
+ */
+#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
+#define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U)
+#define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U)
+#define USBPHY_TX_TOG_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK)
+#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U)
+#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U)
+#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
+#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
+#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U)
+#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK)
+/*! @} */
+
+/*! @name RX - USB PHY Receiver Control Register */
+/*! @{ */
+#define USBPHY_RX_ENVADJ_MASK (0x7U)
+#define USBPHY_RX_ENVADJ_SHIFT (0U)
+/*! ENVADJ
+ * 0b000..Trip-Level Voltage is 0.1000 V
+ * 0b001..Trip-Level Voltage is 0.1125 V
+ * 0b010..Trip-Level Voltage is 0.1250 V
+ * 0b011..Trip-Level Voltage is 0.0875 V
+ * 0b1xx..Reserved
+ */
+#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
+#define USBPHY_RX_DISCONADJ_MASK (0x70U)
+#define USBPHY_RX_DISCONADJ_SHIFT (4U)
+/*! DISCONADJ
+ * 0b000..Trip-Level Voltage is 0.56875 V
+ * 0b001..Trip-Level Voltage is 0.55000 V
+ * 0b010..Trip-Level Voltage is 0.58125 V
+ * 0b011..Trip-Level Voltage is 0.60000 V
+ * 0b1xx..Reserved
+ */
+#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
+#define USBPHY_RX_RXDBYPASS_MASK (0x400000U)
+#define USBPHY_RX_RXDBYPASS_SHIFT (22U)
+/*! RXDBYPASS
+ * 0b0..Normal operation.
+ * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
+ */
+#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
+/*! @} */
+
+/*! @name RX_SET - USB PHY Receiver Control Register */
+/*! @{ */
+#define USBPHY_RX_SET_ENVADJ_MASK (0x7U)
+#define USBPHY_RX_SET_ENVADJ_SHIFT (0U)
+/*! ENVADJ
+ * 0b000..Trip-Level Voltage is 0.1000 V
+ * 0b001..Trip-Level Voltage is 0.1125 V
+ * 0b010..Trip-Level Voltage is 0.1250 V
+ * 0b011..Trip-Level Voltage is 0.0875 V
+ * 0b1xx..Reserved
+ */
+#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
+#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U)
+#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U)
+/*! DISCONADJ
+ * 0b000..Trip-Level Voltage is 0.56875 V
+ * 0b001..Trip-Level Voltage is 0.55000 V
+ * 0b010..Trip-Level Voltage is 0.58125 V
+ * 0b011..Trip-Level Voltage is 0.60000 V
+ * 0b1xx..Reserved
+ */
+#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
+#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U)
+#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U)
+/*! RXDBYPASS
+ * 0b0..Normal operation.
+ * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
+ */
+#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
+/*! @} */
+
+/*! @name RX_CLR - USB PHY Receiver Control Register */
+/*! @{ */
+#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U)
+#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U)
+/*! ENVADJ
+ * 0b000..Trip-Level Voltage is 0.1000 V
+ * 0b001..Trip-Level Voltage is 0.1125 V
+ * 0b010..Trip-Level Voltage is 0.1250 V
+ * 0b011..Trip-Level Voltage is 0.0875 V
+ * 0b1xx..Reserved
+ */
+#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
+#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U)
+#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U)
+/*! DISCONADJ
+ * 0b000..Trip-Level Voltage is 0.56875 V
+ * 0b001..Trip-Level Voltage is 0.55000 V
+ * 0b010..Trip-Level Voltage is 0.58125 V
+ * 0b011..Trip-Level Voltage is 0.60000 V
+ * 0b1xx..Reserved
+ */
+#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
+#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U)
+#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U)
+/*! RXDBYPASS
+ * 0b0..Normal operation.
+ * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
+ */
+#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
+/*! @} */
+
+/*! @name RX_TOG - USB PHY Receiver Control Register */
+/*! @{ */
+#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U)
+#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U)
+/*! ENVADJ
+ * 0b000..Trip-Level Voltage is 0.1000 V
+ * 0b001..Trip-Level Voltage is 0.1125 V
+ * 0b010..Trip-Level Voltage is 0.1250 V
+ * 0b011..Trip-Level Voltage is 0.0875 V
+ * 0b1xx..Reserved
+ */
+#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
+#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U)
+#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U)
+/*! DISCONADJ
+ * 0b000..Trip-Level Voltage is 0.56875 V
+ * 0b001..Trip-Level Voltage is 0.55000 V
+ * 0b010..Trip-Level Voltage is 0.58125 V
+ * 0b011..Trip-Level Voltage is 0.60000 V
+ * 0b1xx..Reserved
+ */
+#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
+#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U)
+#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U)
+/*! RXDBYPASS
+ * 0b0..Normal operation.
+ * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
+ */
+#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
+/*! @} */
+
+/*! @name CTRL - USB PHY General Control Register */
+/*! @{ */
+#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U)
+#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U)
+#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
+#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U)
+#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U)
+#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
+#define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U)
+#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U)
+/*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection
+ * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
+ * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins
+ */
+#define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK)
+#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U)
+#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U)
+#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
+#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U)
+#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U)
+#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
+#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U)
+#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U)
+#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
+#define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U)
+#define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U)
+#define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK)
+#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U)
+#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U)
+#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
+#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
+#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U)
+#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
+#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U)
+#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U)
+#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)
+#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U)
+#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U)
+#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)
+#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U)
+#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U)
+#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
+#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U)
+#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U)
+#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
+#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U)
+#define USBPHY_CTRL_CLKGATE_SHIFT (30U)
+#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
+#define USBPHY_CTRL_SFTRST_MASK (0x80000000U)
+#define USBPHY_CTRL_SFTRST_SHIFT (31U)
+#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
+/*! @} */
+
+/*! @name CTRL_SET - USB PHY General Control Register */
+/*! @{ */
+#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U)
+#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
+#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
+#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
+#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
+#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
+#define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U)
+#define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U)
+/*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection
+ * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
+ * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins
+ */
+#define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK)
+#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U)
+#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U)
+#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
+#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U)
+#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U)
+#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
+#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U)
+#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U)
+#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
+#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U)
+#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U)
+#define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK)
+#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U)
+#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U)
+#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
+#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
+#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U)
+#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
+#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U)
+#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U)
+#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)
+#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U)
+#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U)
+#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)
+#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U)
+#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U)
+#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
+#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U)
+#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U)
+#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
+#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U)
+#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U)
+#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
+#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U)
+#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U)
+#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
+/*! @} */
+
+/*! @name CTRL_CLR - USB PHY General Control Register */
+/*! @{ */
+#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U)
+#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
+#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
+#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
+#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
+#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
+#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U)
+#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U)
+/*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection
+ * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
+ * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins
+ */
+#define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK)
+#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U)
+#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U)
+#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
+#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U)
+#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U)
+#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
+#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U)
+#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U)
+#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
+#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U)
+#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U)
+#define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK)
+#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U)
+#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U)
+#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
+#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
+#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U)
+#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
+#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U)
+#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U)
+#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)
+#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U)
+#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U)
+#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)
+#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U)
+#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U)
+#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
+#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U)
+#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U)
+#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
+#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U)
+#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U)
+#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
+#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U)
+#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U)
+#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
+/*! @} */
+
+/*! @name CTRL_TOG - USB PHY General Control Register */
+/*! @{ */
+#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U)
+#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
+#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
+#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
+#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
+#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
+#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U)
+#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U)
+/*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection
+ * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
+ * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins
+ */
+#define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK)
+#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U)
+#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U)
+#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
+#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U)
+#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U)
+#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
+#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U)
+#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U)
+#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
+#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U)
+#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U)
+#define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK)
+#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U)
+#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U)
+#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
+#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
+#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U)
+#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
+#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U)
+#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U)
+#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)
+#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U)
+#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U)
+#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)
+#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U)
+#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U)
+#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
+#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U)
+#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U)
+#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
+#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U)
+#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U)
+#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
+#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U)
+#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U)
+#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
+/*! @} */
+
+/*! @name STATUS - USB PHY Status Register */
+/*! @{ */
+#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
+#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
+/*! HOSTDISCONDETECT_STATUS
+ * 0b0..USB cable disconnect has not been detected at the local host
+ * 0b1..USB cable disconnect has been detected at the local host
+ */
+#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
+#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U)
+#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U)
+/*! DEVPLUGIN_STATUS - Status indicator for non-standard resistive plugged-in detection
+ * 0b0..No attachment to a USB host is detected
+ * 0b1..Cable attachment to a USB host is detected
+ */
+#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
+#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U)
+#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U)
+#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)
+#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U)
+#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U)
+#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
+/*! @} */
+
+/*! @name DEBUG - USB PHY Debug Register */
+/*! @{ */
+#define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U)
+#define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U)
+#define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)
+#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
+#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
+#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)
+#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU)
+#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U)
+#define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U)
+#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U)
+#define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U)
+#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U)
+#define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U)
+#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U)
+#define USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
+#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U)
+#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)
+#define USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U)
+#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U)
+#define USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)
+#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
+#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U)
+#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)
+#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U)
+#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U)
+#define USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)
+#define USBPHY_DEBUG_CLKGATE_MASK (0x40000000U)
+#define USBPHY_DEBUG_CLKGATE_SHIFT (30U)
+#define USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)
+/*! @} */
+
+/*! @name DEBUG_SET - USB PHY Debug Register */
+/*! @{ */
+#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U)
+#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U)
+#define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)
+#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)
+#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)
+#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)
+#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU)
+#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U)
+#define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U)
+#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U)
+#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U)
+#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U)
+#define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U)
+#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U)
+#define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U)
+#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)
+#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)
+#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U)
+#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U)
+#define USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)
+#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)
+#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)
+#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)
+#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U)
+#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)
+#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)
+#define USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U)
+#define USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U)
+#define USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)
+/*! @} */
+
+/*! @name DEBUG_CLR - USB PHY Debug Register */
+/*! @{ */
+#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U)
+#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U)
+#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)
+#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)
+#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)
+#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)
+#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU)
+#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U)
+#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U)
+#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U)
+#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U)
+#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U)
+#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U)
+#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U)
+#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U)
+#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)
+#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)
+#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U)
+#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U)
+#define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)
+#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)
+#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)
+#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)
+#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U)
+#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)
+#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
+#define USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U)
+#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U)
+#define USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)
+/*! @} */
+
+/*! @name DEBUG_TOG - USB PHY Debug Register */
+/*! @{ */
+#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U)
+#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U)
+#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)
+#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
+#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
+#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)
+#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU)
+#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U)
+#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U)
+#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U)
+#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U)
+#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U)
+#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U)
+#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U)
+#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
+#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)
+#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)
+#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U)
+#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U)
+#define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)
+#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
+#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)
+#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)
+#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U)
+#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)
+#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)
+#define USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U)
+#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U)
+#define USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)
+/*! @} */
+
+/*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */
+/*! @{ */
+#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)
+#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)
+#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)
+#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)
+#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)
+#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)
+#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U)
+#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)
+#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
+/*! @} */
+
+/*! @name DEBUG1 - UTMI Debug Status Register 1 */
+/*! @{ */
+#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U)
+#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U)
+/*! ENTAILADJVD
+ * 0b00..Delay is nominal
+ * 0b01..Delay is +20%
+ * 0b10..Delay is -20%
+ * 0b11..Delay is -40%
+ */
+#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)
+/*! @} */
+
+/*! @name DEBUG1_SET - UTMI Debug Status Register 1 */
+/*! @{ */
+#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U)
+#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U)
+/*! ENTAILADJVD
+ * 0b00..Delay is nominal
+ * 0b01..Delay is +20%
+ * 0b10..Delay is -20%
+ * 0b11..Delay is -40%
+ */
+#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
+/*! @} */
+
+/*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */
+/*! @{ */
+#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U)
+#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U)
+/*! ENTAILADJVD
+ * 0b00..Delay is nominal
+ * 0b01..Delay is +20%
+ * 0b10..Delay is -20%
+ * 0b11..Delay is -40%
+ */
+#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
+/*! @} */
+
+/*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */
+/*! @{ */
+#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U)
+#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U)
+/*! ENTAILADJVD
+ * 0b00..Delay is nominal
+ * 0b01..Delay is +20%
+ * 0b10..Delay is -20%
+ * 0b11..Delay is -40%
+ */
+#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
+/*! @} */
+
+/*! @name VERSION - UTMI RTL Version */
+/*! @{ */
+#define USBPHY_VERSION_STEP_MASK (0xFFFFU)
+#define USBPHY_VERSION_STEP_SHIFT (0U)
+#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)
+#define USBPHY_VERSION_MINOR_MASK (0xFF0000U)
+#define USBPHY_VERSION_MINOR_SHIFT (16U)
+#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)
+#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U)
+#define USBPHY_VERSION_MAJOR_SHIFT (24U)
+#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)
+/*! @} */
+
+/*! @name PLL_SIC - USB PHY PLL Control/Status Register */
+/*! @{ */
+#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x3U)
+#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (0U)
+/*! PLL_DIV_SEL
+ * 0b00..PLL reference frequency = 24MHz
+ * 0b01..PLL reference frequency = 16MHz
+ * 0b1x..PLL reference frequency = 12MHz
+ */
+#define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)
+#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U)
+#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U)
+#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK)
+#define USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_MASK (0x800U)
+#define USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_SHIFT (11U)
+#define USBPHY_PLL_SIC_PLL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_MASK)
+#define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U)
+#define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U)
+#define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK)
+#define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U)
+#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U)
+#define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK)
+#define USBPHY_PLL_SIC_PLL_BYPASS_MASK (0x10000U)
+#define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT (16U)
+#define USBPHY_PLL_SIC_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK)
+#define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U)
+#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U)
+/*! PLL_LOCK
+ * 0b0..PLL is not currently locked
+ * 0b1..PLL is currently locked
+ */
+#define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */
+/*! @{ */
+#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x3U)
+#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (0U)
+/*! PLL_DIV_SEL
+ * 0b00..PLL reference frequency = 24MHz
+ * 0b01..PLL reference frequency = 16MHz
+ * 0b1x..PLL reference frequency = 12MHz
+ */
+#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U)
+#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U)
+#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_MASK (0x800U)
+#define USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_SHIFT (11U)
+#define USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U)
+#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U)
+#define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U)
+#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U)
+#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK (0x10000U)
+#define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT (16U)
+#define USBPHY_PLL_SIC_SET_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U)
+#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U)
+/*! PLL_LOCK
+ * 0b0..PLL is not currently locked
+ * 0b1..PLL is currently locked
+ */
+#define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */
+/*! @{ */
+#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x3U)
+#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (0U)
+/*! PLL_DIV_SEL
+ * 0b00..PLL reference frequency = 24MHz
+ * 0b01..PLL reference frequency = 16MHz
+ * 0b1x..PLL reference frequency = 12MHz
+ */
+#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U)
+#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U)
+#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_MASK (0x800U)
+#define USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_SHIFT (11U)
+#define USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U)
+#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U)
+#define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U)
+#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U)
+#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK (0x10000U)
+#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT (16U)
+#define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U)
+#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U)
+/*! PLL_LOCK
+ * 0b0..PLL is not currently locked
+ * 0b1..PLL is currently locked
+ */
+#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */
+/*! @{ */
+#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x3U)
+#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (0U)
+/*! PLL_DIV_SEL
+ * 0b00..PLL reference frequency = 24MHz
+ * 0b01..PLL reference frequency = 16MHz
+ * 0b1x..PLL reference frequency = 12MHz
+ */
+#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U)
+#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U)
+#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_MASK (0x800U)
+#define USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_SHIFT (11U)
+#define USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U)
+#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U)
+#define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U)
+#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U)
+#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK (0x10000U)
+#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT (16U)
+#define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U)
+#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U)
+/*! PLL_LOCK
+ * 0b0..PLL is not currently locked
+ * 0b1..PLL is currently locked
+ */
+#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK)
+/*! @} */
+
+/*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */
+/*! @{ */
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
+/*! VBUSVALID_THRESH
+ * 0b000..4.0 V
+ * 0b001..4.1 V
+ * 0b010..4.2 V
+ * 0b011..4.3 V
+ * 0b100..4.4 V (Default)
+ * 0b101..4.5 V
+ * 0b110..4.6 V
+ * 0b111..4.7 V
+ */
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK)
+#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U)
+#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U)
+/*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
+ * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
+ * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
+ */
+#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U)
+#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U)
+#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U)
+#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U)
+#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U)
+#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U)
+#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U)
+/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
+ * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
+ * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
+ */
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U)
+#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U)
+/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
+ * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
+ * 0b01..Use the Session Valid comparator results for signal reported to the USB controller
+ * 0b10..Use the Session Valid comparator results for signal reported to the USB controller
+ * 0b11..Reserved, do not use
+ */
+#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U)
+/*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
+ * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results
+ * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
+ */
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK)
+#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x100000U)
+#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U)
+/*! PWRUP_CMPS - Enables the VBUS_VALID comparator
+ * 0b0..Powers down the VBUS_VALID comparator
+ * 0b1..Enables the VBUS_VALID comparator (default)
+ */
+#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
+#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
+/*! DISCHARGE_VBUS - Controls VBUS discharge resistor
+ * 0b0..VBUS discharge resistor is disabled (Default)
+ * 0b1..VBUS discharge resistor is enabled
+ */
+#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U)
+#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U)
+/*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
+ * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP
+ * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP
+ */
+#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK)
+/*! @} */
+
+/*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */
+/*! @{ */
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
+/*! VBUSVALID_THRESH
+ * 0b000..4.0 V
+ * 0b001..4.1 V
+ * 0b010..4.2 V
+ * 0b011..4.3 V
+ * 0b100..4.4 V (Default)
+ * 0b101..4.5 V
+ * 0b110..4.6 V
+ * 0b111..4.7 V
+ */
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U)
+/*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
+ * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
+ * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
+ */
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U)
+#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U)
+#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U)
+#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U)
+#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U)
+#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U)
+#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U)
+/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
+ * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
+ * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
+ */
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U)
+/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
+ * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
+ * 0b01..Use the Session Valid comparator results for signal reported to the USB controller
+ * 0b10..Use the Session Valid comparator results for signal reported to the USB controller
+ * 0b11..Reserved, do not use
+ */
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U)
+/*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
+ * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results
+ * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
+ */
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x100000U)
+#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U)
+/*! PWRUP_CMPS - Enables the VBUS_VALID comparator
+ * 0b0..Powers down the VBUS_VALID comparator
+ * 0b1..Enables the VBUS_VALID comparator (default)
+ */
+#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
+#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
+/*! DISCHARGE_VBUS - Controls VBUS discharge resistor
+ * 0b0..VBUS discharge resistor is disabled (Default)
+ * 0b1..VBUS discharge resistor is enabled
+ */
+#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U)
+#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U)
+/*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
+ * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP
+ * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP
+ */
+#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK)
+/*! @} */
+
+/*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */
+/*! @{ */
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
+/*! VBUSVALID_THRESH
+ * 0b000..4.0 V
+ * 0b001..4.1 V
+ * 0b010..4.2 V
+ * 0b011..4.3 V
+ * 0b100..4.4 V (Default)
+ * 0b101..4.5 V
+ * 0b110..4.6 V
+ * 0b111..4.7 V
+ */
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U)
+/*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
+ * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
+ * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
+ */
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U)
+/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
+ * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
+ * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
+ */
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U)
+/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
+ * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
+ * 0b01..Use the Session Valid comparator results for signal reported to the USB controller
+ * 0b10..Use the Session Valid comparator results for signal reported to the USB controller
+ * 0b11..Reserved, do not use
+ */
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U)
+/*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
+ * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results
+ * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
+ */
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x100000U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U)
+/*! PWRUP_CMPS - Enables the VBUS_VALID comparator
+ * 0b0..Powers down the VBUS_VALID comparator
+ * 0b1..Enables the VBUS_VALID comparator (default)
+ */
+#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
+/*! DISCHARGE_VBUS - Controls VBUS discharge resistor
+ * 0b0..VBUS discharge resistor is disabled (Default)
+ * 0b1..VBUS discharge resistor is enabled
+ */
+#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U)
+/*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
+ * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP
+ * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP
+ */
+#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK)
+/*! @} */
+
+/*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */
+/*! @{ */
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
+/*! VBUSVALID_THRESH
+ * 0b000..4.0 V
+ * 0b001..4.1 V
+ * 0b010..4.2 V
+ * 0b011..4.3 V
+ * 0b100..4.4 V (Default)
+ * 0b101..4.5 V
+ * 0b110..4.6 V
+ * 0b111..4.7 V
+ */
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U)
+/*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
+ * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
+ * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
+ */
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U)
+/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
+ * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
+ * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
+ */
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U)
+/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
+ * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
+ * 0b01..Use the Session Valid comparator results for signal reported to the USB controller
+ * 0b10..Use the Session Valid comparator results for signal reported to the USB controller
+ * 0b11..Reserved, do not use
+ */
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U)
+/*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
+ * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results
+ * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
+ */
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x100000U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U)
+/*! PWRUP_CMPS - Enables the VBUS_VALID comparator
+ * 0b0..Powers down the VBUS_VALID comparator
+ * 0b1..Enables the VBUS_VALID comparator (default)
+ */
+#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
+/*! DISCHARGE_VBUS - Controls VBUS discharge resistor
+ * 0b0..VBUS discharge resistor is disabled (Default)
+ * 0b1..VBUS discharge resistor is enabled
+ */
+#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U)
+/*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
+ * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP
+ * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP
+ */
+#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK)
+/*! @} */
+
+/*! @name USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register */
+/*! @{ */
+#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U)
+#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U)
+/*! SESSEND - Session End indicator
+ * 0b0..The VBUS voltage is above the Session Valid threshold
+ * 0b1..The VBUS voltage is below the Session Valid threshold
+ */
+#define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK)
+#define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U)
+#define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U)
+/*! BVALID - B-Device Session Valid status
+ * 0b0..The VBUS voltage is below the Session Valid threshold
+ * 0b1..The VBUS voltage is above the Session Valid threshold
+ */
+#define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK)
+#define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U)
+#define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U)
+/*! AVALID - A-Device Session Valid status
+ * 0b0..The VBUS voltage is below the Session Valid threshold
+ * 0b1..The VBUS voltage is above the Session Valid threshold
+ */
+#define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK)
+#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U)
+#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U)
+/*! VBUS_VALID - VBUS voltage status
+ * 0b0..VBUS is below the comparator threshold
+ * 0b1..VBUS is above the comparator threshold
+ */
+#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK)
+#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U)
+#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U)
+/*! VBUS_VALID_3V - VBUS_VALID_3V detector status
+ * 0b0..VBUS voltage is below VBUS_VALID_3V threshold
+ * 0b1..VBUS voltage is above VBUS_VALID_3V threshold
+ */
+#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK)
+/*! @} */
+
+/*! @name USB1_CHRG_DET_STAT - USB PHY Charger Detect Status Register */
+/*! @{ */
+#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U)
+#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U)
+/*! PLUG_CONTACT - Battery Charging Data Contact Detection phase output
+ * 0b0..No USB cable attachment has been detected
+ * 0b1..A USB cable attachment between the device and host has been detected
+ */
+#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK)
+#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U)
+#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U)
+/*! CHRG_DETECTED - Battery Charging Primary Detection phase output
+ * 0b0..Standard Downstream Port (SDP) has been detected
+ * 0b1..Charging Port has been detected
+ */
+#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK)
+#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK (0x4U)
+#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U)
+/*! DM_STATE
+ * 0b0..USB_DM pin voltage is < 0.8V
+ * 0b1..USB_DM pin voltage is > 2.0V
+ */
+#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK)
+#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK (0x8U)
+#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U)
+/*! DP_STATE
+ * 0b0..USB_DP pin voltage is < 0.8V
+ * 0b1..USB_DP pin voltage is > 2.0V
+ */
+#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK)
+#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U)
+#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U)
+/*! SECDET_DCP - Battery Charging Secondary Detection phase output
+ * 0b0..Charging Downstream Port (CDP) has been detected
+ * 0b1..Downstream Charging Port (DCP) has been detected
+ */
+#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK)
+/*! @} */
+
+/*! @name ANACTRL - USB PHY Analog Control Register */
+/*! @{ */
+#define USBPHY_ANACTRL_TESTCLK_SEL_MASK (0x1U)
+#define USBPHY_ANACTRL_TESTCLK_SEL_SHIFT (0U)
+#define USBPHY_ANACTRL_TESTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_TESTCLK_SEL_MASK)
+#define USBPHY_ANACTRL_PFD_CLKGATE_MASK (0x2U)
+#define USBPHY_ANACTRL_PFD_CLKGATE_SHIFT (1U)
+/*! PFD_CLKGATE
+ * 0b0..PFD clock output is enabled
+ * 0b1..PFD clock output is gated (Default)
+ */
+#define USBPHY_ANACTRL_PFD_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_PFD_CLKGATE_MASK)
+#define USBPHY_ANACTRL_PFD_CLK_SEL_MASK (0xCU)
+#define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT (2U)
+/*! PFD_CLK_SEL
+ * 0b00..USB1PFDCLK is the same frequency as the xtal clock (Default)
+ * 0b01..USB1PFDCLK frequency is pfd_clk divided by 4
+ * 0b10..USB1PFDCLK frequency is pfd_clk divided by 2
+ * 0b11..USB1PFDCLK frequency is the same as pfd_clk frequency
+ */
+#define USBPHY_ANACTRL_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK)
+#define USBPHY_ANACTRL_PFD_FRAC_MASK (0x3F0U)
+#define USBPHY_ANACTRL_PFD_FRAC_SHIFT (4U)
+#define USBPHY_ANACTRL_PFD_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_PFD_FRAC_MASK)
+#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U)
+#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U)
+/*! DEV_PULLDOWN
+ * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.
+ * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.
+ */
+#define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK)
+#define USBPHY_ANACTRL_EMPH_PULSE_CTRL_MASK (0x1800U)
+#define USBPHY_ANACTRL_EMPH_PULSE_CTRL_SHIFT (11U)
+/*! EMPH_PULSE_CTRL
+ * 0b00..Minimum duration of pre-emphasis current after each data transition
+ * 0b11..Maximum duration of pre-emphasis current after each data transition
+ */
+#define USBPHY_ANACTRL_EMPH_PULSE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_EMPH_PULSE_CTRL_MASK)
+#define USBPHY_ANACTRL_EMPH_EN_MASK (0x2000U)
+#define USBPHY_ANACTRL_EMPH_EN_SHIFT (13U)
+/*! EMPH_EN
+ * 0b0..No pre-emphasis is used on HS TX output drivers
+ * 0b1..Enables pre-emphasis for HS TX output drivers
+ */
+#define USBPHY_ANACTRL_EMPH_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_EMPH_EN_MASK)
+#define USBPHY_ANACTRL_EMPH_CUR_CTRL_MASK (0xC000U)
+#define USBPHY_ANACTRL_EMPH_CUR_CTRL_SHIFT (14U)
+/*! EMPH_CUR_CTRL
+ * 0b00..No pre-emphasis current is enabled for the HS TX drivers
+ * 0b01..One unit of pre-emphasis current is enabled for the HS TX drivers
+ * 0b10..Two units of pre-emphasis current are enabled for the HS TX drivers
+ * 0b11..Three units of pre-emphasis current are enabled for the HS TX drivers
+ */
+#define USBPHY_ANACTRL_EMPH_CUR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_EMPH_CUR_CTRL_MASK)
+#define USBPHY_ANACTRL_PFD_STABLE_MASK (0x80000000U)
+#define USBPHY_ANACTRL_PFD_STABLE_SHIFT (31U)
+#define USBPHY_ANACTRL_PFD_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_PFD_STABLE_MASK)
+/*! @} */
+
+/*! @name ANACTRL_SET - USB PHY Analog Control Register */
+/*! @{ */
+#define USBPHY_ANACTRL_SET_TESTCLK_SEL_MASK (0x1U)
+#define USBPHY_ANACTRL_SET_TESTCLK_SEL_SHIFT (0U)
+#define USBPHY_ANACTRL_SET_TESTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_TESTCLK_SEL_MASK)
+#define USBPHY_ANACTRL_SET_PFD_CLKGATE_MASK (0x2U)
+#define USBPHY_ANACTRL_SET_PFD_CLKGATE_SHIFT (1U)
+/*! PFD_CLKGATE
+ * 0b0..PFD clock output is enabled
+ * 0b1..PFD clock output is gated (Default)
+ */
+#define USBPHY_ANACTRL_SET_PFD_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLKGATE_MASK)
+#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK (0xCU)
+#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT (2U)
+/*! PFD_CLK_SEL
+ * 0b00..USB1PFDCLK is the same frequency as the xtal clock (Default)
+ * 0b01..USB1PFDCLK frequency is pfd_clk divided by 4
+ * 0b10..USB1PFDCLK frequency is pfd_clk divided by 2
+ * 0b11..USB1PFDCLK frequency is the same as pfd_clk frequency
+ */
+#define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK)
+#define USBPHY_ANACTRL_SET_PFD_FRAC_MASK (0x3F0U)
+#define USBPHY_ANACTRL_SET_PFD_FRAC_SHIFT (4U)
+#define USBPHY_ANACTRL_SET_PFD_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_SET_PFD_FRAC_MASK)
+#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U)
+#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U)
+/*! DEV_PULLDOWN
+ * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.
+ * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.
+ */
+#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK)
+#define USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_MASK (0x1800U)
+#define USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_SHIFT (11U)
+/*! EMPH_PULSE_CTRL
+ * 0b00..Minimum duration of pre-emphasis current after each data transition
+ * 0b11..Maximum duration of pre-emphasis current after each data transition
+ */
+#define USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_MASK)
+#define USBPHY_ANACTRL_SET_EMPH_EN_MASK (0x2000U)
+#define USBPHY_ANACTRL_SET_EMPH_EN_SHIFT (13U)
+/*! EMPH_EN
+ * 0b0..No pre-emphasis is used on HS TX output drivers
+ * 0b1..Enables pre-emphasis for HS TX output drivers
+ */
+#define USBPHY_ANACTRL_SET_EMPH_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_SET_EMPH_EN_MASK)
+#define USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_MASK (0xC000U)
+#define USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_SHIFT (14U)
+/*! EMPH_CUR_CTRL
+ * 0b00..No pre-emphasis current is enabled for the HS TX drivers
+ * 0b01..One unit of pre-emphasis current is enabled for the HS TX drivers
+ * 0b10..Two units of pre-emphasis current are enabled for the HS TX drivers
+ * 0b11..Three units of pre-emphasis current are enabled for the HS TX drivers
+ */
+#define USBPHY_ANACTRL_SET_EMPH_CUR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_MASK)
+#define USBPHY_ANACTRL_SET_PFD_STABLE_MASK (0x80000000U)
+#define USBPHY_ANACTRL_SET_PFD_STABLE_SHIFT (31U)
+#define USBPHY_ANACTRL_SET_PFD_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_SET_PFD_STABLE_MASK)
+/*! @} */
+
+/*! @name ANACTRL_CLR - USB PHY Analog Control Register */
+/*! @{ */
+#define USBPHY_ANACTRL_CLR_TESTCLK_SEL_MASK (0x1U)
+#define USBPHY_ANACTRL_CLR_TESTCLK_SEL_SHIFT (0U)
+#define USBPHY_ANACTRL_CLR_TESTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_TESTCLK_SEL_MASK)
+#define USBPHY_ANACTRL_CLR_PFD_CLKGATE_MASK (0x2U)
+#define USBPHY_ANACTRL_CLR_PFD_CLKGATE_SHIFT (1U)
+/*! PFD_CLKGATE
+ * 0b0..PFD clock output is enabled
+ * 0b1..PFD clock output is gated (Default)
+ */
+#define USBPHY_ANACTRL_CLR_PFD_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLKGATE_MASK)
+#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK (0xCU)
+#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT (2U)
+/*! PFD_CLK_SEL
+ * 0b00..USB1PFDCLK is the same frequency as the xtal clock (Default)
+ * 0b01..USB1PFDCLK frequency is pfd_clk divided by 4
+ * 0b10..USB1PFDCLK frequency is pfd_clk divided by 2
+ * 0b11..USB1PFDCLK frequency is the same as pfd_clk frequency
+ */
+#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK)
+#define USBPHY_ANACTRL_CLR_PFD_FRAC_MASK (0x3F0U)
+#define USBPHY_ANACTRL_CLR_PFD_FRAC_SHIFT (4U)
+#define USBPHY_ANACTRL_CLR_PFD_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_FRAC_MASK)
+#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U)
+#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U)
+/*! DEV_PULLDOWN
+ * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.
+ * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.
+ */
+#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK)
+#define USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_MASK (0x1800U)
+#define USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_SHIFT (11U)
+/*! EMPH_PULSE_CTRL
+ * 0b00..Minimum duration of pre-emphasis current after each data transition
+ * 0b11..Maximum duration of pre-emphasis current after each data transition
+ */
+#define USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_MASK)
+#define USBPHY_ANACTRL_CLR_EMPH_EN_MASK (0x2000U)
+#define USBPHY_ANACTRL_CLR_EMPH_EN_SHIFT (13U)
+/*! EMPH_EN
+ * 0b0..No pre-emphasis is used on HS TX output drivers
+ * 0b1..Enables pre-emphasis for HS TX output drivers
+ */
+#define USBPHY_ANACTRL_CLR_EMPH_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_CLR_EMPH_EN_MASK)
+#define USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_MASK (0xC000U)
+#define USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_SHIFT (14U)
+/*! EMPH_CUR_CTRL
+ * 0b00..No pre-emphasis current is enabled for the HS TX drivers
+ * 0b01..One unit of pre-emphasis current is enabled for the HS TX drivers
+ * 0b10..Two units of pre-emphasis current are enabled for the HS TX drivers
+ * 0b11..Three units of pre-emphasis current are enabled for the HS TX drivers
+ */
+#define USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_MASK)
+#define USBPHY_ANACTRL_CLR_PFD_STABLE_MASK (0x80000000U)
+#define USBPHY_ANACTRL_CLR_PFD_STABLE_SHIFT (31U)
+#define USBPHY_ANACTRL_CLR_PFD_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_STABLE_MASK)
+/*! @} */
+
+/*! @name ANACTRL_TOG - USB PHY Analog Control Register */
+/*! @{ */
+#define USBPHY_ANACTRL_TOG_TESTCLK_SEL_MASK (0x1U)
+#define USBPHY_ANACTRL_TOG_TESTCLK_SEL_SHIFT (0U)
+#define USBPHY_ANACTRL_TOG_TESTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_TESTCLK_SEL_MASK)
+#define USBPHY_ANACTRL_TOG_PFD_CLKGATE_MASK (0x2U)
+#define USBPHY_ANACTRL_TOG_PFD_CLKGATE_SHIFT (1U)
+/*! PFD_CLKGATE
+ * 0b0..PFD clock output is enabled
+ * 0b1..PFD clock output is gated (Default)
+ */
+#define USBPHY_ANACTRL_TOG_PFD_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLKGATE_MASK)
+#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK (0xCU)
+#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT (2U)
+/*! PFD_CLK_SEL
+ * 0b00..USB1PFDCLK is the same frequency as the xtal clock (Default)
+ * 0b01..USB1PFDCLK frequency is pfd_clk divided by 4
+ * 0b10..USB1PFDCLK frequency is pfd_clk divided by 2
+ * 0b11..USB1PFDCLK frequency is the same as pfd_clk frequency
+ */
+#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK)
+#define USBPHY_ANACTRL_TOG_PFD_FRAC_MASK (0x3F0U)
+#define USBPHY_ANACTRL_TOG_PFD_FRAC_SHIFT (4U)
+#define USBPHY_ANACTRL_TOG_PFD_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_FRAC_MASK)
+#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U)
+#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U)
+/*! DEV_PULLDOWN
+ * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.
+ * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.
+ */
+#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK)
+#define USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_MASK (0x1800U)
+#define USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_SHIFT (11U)
+/*! EMPH_PULSE_CTRL
+ * 0b00..Minimum duration of pre-emphasis current after each data transition
+ * 0b11..Maximum duration of pre-emphasis current after each data transition
+ */
+#define USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_MASK)
+#define USBPHY_ANACTRL_TOG_EMPH_EN_MASK (0x2000U)
+#define USBPHY_ANACTRL_TOG_EMPH_EN_SHIFT (13U)
+/*! EMPH_EN
+ * 0b0..No pre-emphasis is used on HS TX output drivers
+ * 0b1..Enables pre-emphasis for HS TX output drivers
+ */
+#define USBPHY_ANACTRL_TOG_EMPH_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_TOG_EMPH_EN_MASK)
+#define USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_MASK (0xC000U)
+#define USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_SHIFT (14U)
+/*! EMPH_CUR_CTRL
+ * 0b00..No pre-emphasis current is enabled for the HS TX drivers
+ * 0b01..One unit of pre-emphasis current is enabled for the HS TX drivers
+ * 0b10..Two units of pre-emphasis current are enabled for the HS TX drivers
+ * 0b11..Three units of pre-emphasis current are enabled for the HS TX drivers
+ */
+#define USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_MASK)
+#define USBPHY_ANACTRL_TOG_PFD_STABLE_MASK (0x80000000U)
+#define USBPHY_ANACTRL_TOG_PFD_STABLE_SHIFT (31U)
+#define USBPHY_ANACTRL_TOG_PFD_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_STABLE_MASK)
+/*! @} */
+
+/*! @name USB1_LOOPBACK - USB PHY Loopback Control/Status Register */
+/*! @{ */
+#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK (0x1U)
+#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT (0U)
+#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK)
+#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK (0x2U)
+#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT (1U)
+#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK (0x4U)
+#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT (2U)
+#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK (0x8U)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT (3U)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK (0x10U)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT (4U)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK (0x20U)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT (5U)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK (0x40U)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT (6U)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK)
+#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK (0x80U)
+#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT (7U)
+#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK (0x100U)
+#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT (8U)
+#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK (0x8000U)
+#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT (15U)
+#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_TSTPKT_MASK (0xFF0000U)
+#define USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT (16U)
+#define USBPHY_USB1_LOOPBACK_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTPKT_MASK)
+/*! @} */
+
+/*! @name USB1_LOOPBACK_SET - USB PHY Loopback Control/Status Register */
+/*! @{ */
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U)
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK (0x2U)
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT (1U)
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK (0x4U)
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT (2U)
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK (0x8U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT (3U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK (0x10U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT (4U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK (0x20U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT (5U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK (0x40U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT (6U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK (0x80U)
+#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT (7U)
+#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK (0x100U)
+#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT (8U)
+#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK (0x8000U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT (15U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK (0xFF0000U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT (16U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK)
+/*! @} */
+
+/*! @name USB1_LOOPBACK_CLR - USB PHY Loopback Control/Status Register */
+/*! @{ */
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK (0x2U)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT (1U)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK (0x4U)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT (2U)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK (0x8U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT (3U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK (0x10U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT (4U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK (0x20U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT (5U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK (0x40U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT (6U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK (0x80U)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT (7U)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK (0x100U)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT (8U)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK (0x8000U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT (15U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK (0xFF0000U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT (16U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK)
+/*! @} */
+
+/*! @name USB1_LOOPBACK_TOG - USB PHY Loopback Control/Status Register */
+/*! @{ */
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK (0x2U)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT (1U)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK (0x4U)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT (2U)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK (0x8U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT (3U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK (0x10U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT (4U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK (0x20U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT (5U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK (0x40U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT (6U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK (0x80U)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT (7U)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK (0x100U)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT (8U)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK (0x8000U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT (15U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK (0xFF0000U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT (16U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK)
+/*! @} */
+
+/*! @name USB1_LOOPBACK_HSFSCNT - USB PHY Loopback Packet Number Select Register */
+/*! @{ */
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK (0xFFFFU)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT (0U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT (16U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK)
+/*! @} */
+
+/*! @name USB1_LOOPBACK_HSFSCNT_SET - USB PHY Loopback Packet Number Select Register */
+/*! @{ */
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK (0xFFFFU)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT (0U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT (16U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK)
+/*! @} */
+
+/*! @name USB1_LOOPBACK_HSFSCNT_CLR - USB PHY Loopback Packet Number Select Register */
+/*! @{ */
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK (0xFFFFU)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT (0U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT (16U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK)
+/*! @} */
+
+/*! @name USB1_LOOPBACK_HSFSCNT_TOG - USB PHY Loopback Packet Number Select Register */
+/*! @{ */
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK (0xFFFFU)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT (0U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT (16U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK)
+/*! @} */
+
+/*! @name TRIM_OVERRIDE_EN - USB PHY Trim Override Enable Register */
+/*! @{ */
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x30000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (16U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_MASK)
+/*! @} */
+
+/*! @name TRIM_OVERRIDE_EN_SET - USB PHY Trim Override Enable Register */
+/*! @{ */
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x30000U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (16U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_MASK)
+/*! @} */
+
+/*! @name TRIM_OVERRIDE_EN_CLR - USB PHY Trim Override Enable Register */
+/*! @{ */
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x30000U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (16U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_MASK)
+/*! @} */
+
+/*! @name TRIM_OVERRIDE_EN_TOG - USB PHY Trim Override Enable Register */
+/*! @{ */
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x30000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (16U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USBPHY_Register_Masks */
+
+
+/* USBPHY - Peripheral instance base addresses */
+/** Peripheral USBPHY base address */
+#define USBPHY_BASE (0x400A2000u)
+/** Peripheral USBPHY base pointer */
+#define USBPHY ((USBPHY_Type *)USBPHY_BASE)
+/** Array initializer of USBPHY peripheral base addresses */
+#define USBPHY_BASE_ADDRS { USBPHY_BASE }
+/** Array initializer of USBPHY peripheral base pointers */
+#define USBPHY_BASE_PTRS { USBPHY }
+
+/*!
+ * @}
+ */ /* end of group USBPHY_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- VREF Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
+ __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
+} VREF_Type;
+
+/* ----------------------------------------------------------------------------
+ -- VREF Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/*! @name TRM - VREF Trim Register */
+/*! @{ */
+#define VREF_TRM_TRIM_MASK (0x3FU)
+#define VREF_TRM_TRIM_SHIFT (0U)
+/*! TRIM - Trim bits
+ * 0b000000..Min
+ * 0b111111..Max
+ */
+#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK (0x40U)
+#define VREF_TRM_CHOPEN_SHIFT (6U)
+/*! CHOPEN - Chop oscillator enable. When set, internal chopping operation is enabled and the internal analog offset will be minimized.
+ * 0b0..Chop oscillator is disabled.
+ * 0b1..Chop oscillator is enabled.
+ */
+#define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
+/*! @} */
+
+/*! @name SC - VREF Status and Control Register */
+/*! @{ */
+#define VREF_SC_MODE_LV_MASK (0x3U)
+#define VREF_SC_MODE_LV_SHIFT (0U)
+/*! MODE_LV - Buffer Mode selection
+ * 0b00..Bandgap on only, for stabilization and startup
+ * 0b01..High power buffer mode enabled
+ * 0b10..Low-power buffer mode enabled
+ * 0b11..Reserved
+ */
+#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK (0x4U)
+#define VREF_SC_VREFST_SHIFT (2U)
+/*! VREFST - Internal Voltage Reference stable
+ * 0b0..The module is disabled or not stable.
+ * 0b1..The module is stable.
+ */
+#define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
+#define VREF_SC_ICOMPEN_MASK (0x20U)
+#define VREF_SC_ICOMPEN_SHIFT (5U)
+/*! ICOMPEN - Second order curvature compensation enable
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
+#define VREF_SC_REGEN_MASK (0x40U)
+#define VREF_SC_REGEN_SHIFT (6U)
+/*! REGEN - Regulator enable
+ * 0b0..Internal 1.75 V regulator is disabled.
+ * 0b1..Internal 1.75 V regulator is enabled.
+ */
+#define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
+#define VREF_SC_VREFEN_MASK (0x80U)
+#define VREF_SC_VREFEN_SHIFT (7U)
+/*! VREFEN - Internal Voltage Reference enable
+ * 0b0..The module is disabled.
+ * 0b1..The module is enabled.
+ */
+#define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE (0x40074000u)
+/** Peripheral VREF base pointer */
+#define VREF ((VREF_Type *)VREF_BASE)
+/** Array initializer of VREF peripheral base addresses */
+#define VREF_BASE_ADDRS { VREF_BASE }
+/** Array initializer of VREF peripheral base pointers */
+#define VREF_BASE_PTRS { VREF }
+
+/*!
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- WDOG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
+ * @{
+ */
+
+/** WDOG - Register Layout Typedef */
+typedef struct {
+ __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
+ __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
+ __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
+ __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
+ __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
+ __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
+ __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
+ __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
+ __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
+ __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
+ __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
+ __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
+} WDOG_Type;
+
+/* ----------------------------------------------------------------------------
+ -- WDOG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Masks WDOG Register Masks
+ * @{
+ */
+
+/*! @name STCTRLH - Watchdog Status and Control Register High */
+/*! @{ */
+#define WDOG_STCTRLH_WDOGEN_MASK (0x1U)
+#define WDOG_STCTRLH_WDOGEN_SHIFT (0U)
+/*! WDOGEN
+ * 0b0..WDOG is disabled.
+ * 0b1..WDOG is enabled.
+ */
+#define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK)
+#define WDOG_STCTRLH_CLKSRC_MASK (0x2U)
+#define WDOG_STCTRLH_CLKSRC_SHIFT (1U)
+/*! CLKSRC
+ * 0b0..WDOG clock sourced from LPO .
+ * 0b1..WDOG clock sourced from alternate clock source.
+ */
+#define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
+#define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U)
+#define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U)
+/*! IRQRSTEN
+ * 0b0..WDOG time-out generates reset only.
+ * 0b1..WDOG time-out initially generates an interrupt. After WCT, it generates a reset.
+ */
+#define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
+#define WDOG_STCTRLH_WINEN_MASK (0x8U)
+#define WDOG_STCTRLH_WINEN_SHIFT (3U)
+/*! WINEN
+ * 0b0..Windowing mode is disabled.
+ * 0b1..Windowing mode is enabled.
+ */
+#define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
+#define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U)
+#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U)
+/*! ALLOWUPDATE
+ * 0b0..No further updates allowed to WDOG write-once registers.
+ * 0b1..WDOG write-once registers can be unlocked for updating.
+ */
+#define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
+#define WDOG_STCTRLH_DBGEN_MASK (0x20U)
+#define WDOG_STCTRLH_DBGEN_SHIFT (5U)
+/*! DBGEN
+ * 0b0..WDOG is disabled in CPU Debug mode.
+ * 0b1..WDOG is enabled in CPU Debug mode.
+ */
+#define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
+#define WDOG_STCTRLH_STOPEN_MASK (0x40U)
+#define WDOG_STCTRLH_STOPEN_SHIFT (6U)
+/*! STOPEN
+ * 0b0..WDOG is disabled in CPU Stop mode.
+ * 0b1..WDOG is enabled in CPU Stop mode.
+ */
+#define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
+#define WDOG_STCTRLH_WAITEN_MASK (0x80U)
+#define WDOG_STCTRLH_WAITEN_SHIFT (7U)
+/*! WAITEN
+ * 0b0..WDOG is disabled in CPU Wait mode.
+ * 0b1..WDOG is enabled in CPU Wait mode.
+ */
+#define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
+#define WDOG_STCTRLH_TESTWDOG_MASK (0x400U)
+#define WDOG_STCTRLH_TESTWDOG_SHIFT (10U)
+#define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
+#define WDOG_STCTRLH_TESTSEL_MASK (0x800U)
+#define WDOG_STCTRLH_TESTSEL_SHIFT (11U)
+/*! TESTSEL
+ * 0b0..Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test.
+ * 0b1..Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select the byte through BYTESEL[1:0] for testing.
+ */
+#define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
+#define WDOG_STCTRLH_BYTESEL_MASK (0x3000U)
+#define WDOG_STCTRLH_BYTESEL_SHIFT (12U)
+/*! BYTESEL
+ * 0b00..Byte 0 selected
+ * 0b01..Byte 1 selected
+ * 0b10..Byte 2 selected
+ * 0b11..Byte 3 selected
+ */
+#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U)
+#define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U)
+/*! DISTESTWDOG
+ * 0b0..WDOG functional test mode is not disabled.
+ * 0b1..WDOG functional test mode is disabled permanently until reset.
+ */
+#define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
+/*! @} */
+
+/*! @name STCTRLL - Watchdog Status and Control Register Low */
+/*! @{ */
+#define WDOG_STCTRLL_INTFLG_MASK (0x8000U)
+#define WDOG_STCTRLL_INTFLG_SHIFT (15U)
+#define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
+/*! @} */
+
+/*! @name TOVALH - Watchdog Time-out Value Register High */
+/*! @{ */
+#define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU)
+#define WDOG_TOVALH_TOVALHIGH_SHIFT (0U)
+#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
+/*! @} */
+
+/*! @name TOVALL - Watchdog Time-out Value Register Low */
+/*! @{ */
+#define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU)
+#define WDOG_TOVALL_TOVALLOW_SHIFT (0U)
+#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
+/*! @} */
+
+/*! @name WINH - Watchdog Window Register High */
+/*! @{ */
+#define WDOG_WINH_WINHIGH_MASK (0xFFFFU)
+#define WDOG_WINH_WINHIGH_SHIFT (0U)
+#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
+/*! @} */
+
+/*! @name WINL - Watchdog Window Register Low */
+/*! @{ */
+#define WDOG_WINL_WINLOW_MASK (0xFFFFU)
+#define WDOG_WINL_WINLOW_SHIFT (0U)
+#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
+/*! @} */
+
+/*! @name REFRESH - Watchdog Refresh register */
+/*! @{ */
+#define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU)
+#define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U)
+#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
+/*! @} */
+
+/*! @name UNLOCK - Watchdog Unlock register */
+/*! @{ */
+#define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU)
+#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U)
+#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
+/*! @} */
+
+/*! @name TMROUTH - Watchdog Timer Output Register High */
+/*! @{ */
+#define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU)
+#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U)
+#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+/*! @} */
+
+/*! @name TMROUTL - Watchdog Timer Output Register Low */
+/*! @{ */
+#define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU)
+#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U)
+#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
+/*! @} */
+
+/*! @name RSTCNT - Watchdog Reset Count register */
+/*! @{ */
+#define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU)
+#define WDOG_RSTCNT_RSTCNT_SHIFT (0U)
+#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
+/*! @} */
+
+/*! @name PRESC - Watchdog Prescaler register */
+/*! @{ */
+#define WDOG_PRESC_PRESCVAL_MASK (0x700U)
+#define WDOG_PRESC_PRESCVAL_SHIFT (8U)
+#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Masks */
+
+
+/* WDOG - Peripheral instance base addresses */
+/** Peripheral WDOG base address */
+#define WDOG_BASE (0x40052000u)
+/** Peripheral WDOG base pointer */
+#define WDOG ((WDOG_Type *)WDOG_BASE)
+/** Array initializer of WDOG peripheral base addresses */
+#define WDOG_BASE_ADDRS { WDOG_BASE }
+/** Array initializer of WDOG peripheral base pointers */
+#define WDOG_BASE_PTRS { WDOG }
+/** Interrupt vectors for the WDOG peripheral type */
+#define WDOG_IRQS { WDOG_EWM_IRQn }
+
+/*!
+ * @}
+ */ /* end of group WDOG_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #if (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+ #else
+ #pragma pop
+ #endif
+#elif defined(__CWCC__)
+ #pragma pop
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=default
+#else
+ #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+ #if (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header
+ #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SDK Compatibility
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
+ * @{
+ */
+
+#define FMC_PFB0CR_RFU_MASK FMC_PFB01CR_RFU_MASK
+#define FMC_PFB0CR_RFU_SHIFT FMC_PFB01CR_RFU_SHIFT
+#define FMC_PFB0CR_B0IPE_MASK FMC_PFB01CR_B0IPE_MASK
+#define FMC_PFB0CR_B0IPE_SHIFT FMC_PFB01CR_B0IPE_SHIFT
+#define FMC_PFB0CR_B0DPE_MASK FMC_PFB01CR_B0DPE_MASK
+#define FMC_PFB0CR_B0DPE_SHIFT FMC_PFB01CR_B0DPE_SHIFT
+#define FMC_PFB0CR_B0ICE_MASK FMC_PFB01CR_B0ICE_MASK
+#define FMC_PFB0CR_B0ICE_SHIFT FMC_PFB01CR_B0ICE_SHIFT
+#define FMC_PFB0CR_B0DCE_MASK FMC_PFB01CR_B0DCE_MASK
+#define FMC_PFB0CR_B0DCE_SHIFT FMC_PFB01CR_B0DCE_SHIFT
+#define FMC_PFB0CR_CRC_MASK FMC_PFB01CR_CRC_MASK
+#define FMC_PFB0CR_CRC_SHIFT FMC_PFB01CR_CRC_SHIFT
+#define FMC_PFB0CR_CRC(x) FMC_PFB01CR_CRC(x)
+#define FMC_PFB0CR_B0MW_MASK FMC_PFB01CR_B0MW_MASK
+#define FMC_PFB0CR_B0MW_SHIFT FMC_PFB01CR_B0MW_SHIFT
+#define FMC_PFB0CR_B0MW(x) FMC_PFB01CR_B0MW(x)
+#define FMC_PFB0CR_S_B_INV_MASK FMC_PFB01CR_S_B_INV_MASK
+#define FMC_PFB0CR_S_B_INV_SHIFT FMC_PFB01CR_S_B_INV_SHIFT
+#define FMC_PFB0CR_CINV_WAY_MASK FMC_PFB01CR_CINV_WAY_MASK
+#define FMC_PFB0CR_CINV_WAY_SHIFT FMC_PFB01CR_CINV_WAY_SHIFT
+#define FMC_PFB0CR_CINV_WAY(x) FMC_PFB01CR_CINV_WAY(x)
+#define FMC_PFB0CR_CLCK_WAY_MASK FMC_PFB01CR_CLCK_WAY_MASK
+#define FMC_PFB0CR_CLCK_WAY_SHIFT FMC_PFB01CR_CLCK_WAY_SHIFT
+#define FMC_PFB0CR_CLCK_WAY(x) FMC_PFB01CR_CLCK_WAY(x)
+#define FMC_PFB0CR_B0RWSC_MASK FMC_PFB01CR_B0RWSC_MASK
+#define FMC_PFB0CR_B0RWSC_SHIFT FMC_PFB01CR_B0RWSC_SHIFT
+#define FMC_PFB0CR_B0RWSC(x) FMC_PFB01CR_B0RWSC(x)
+#define FMC_PFB1CR_RFU_MASK FMC_PFB23CR_RFU_MASK
+#define FMC_PFB1CR_RFU_SHIFT FMC_PFB23CR_RFU_SHIFT
+#define FMC_PFB1CR_B1IPE_MASK FMC_PFB23CR_B1IPE_MASK
+#define FMC_PFB1CR_B1IPE_SHIFT FMC_PFB23CR_B1IPE_SHIFT
+#define FMC_PFB1CR_B1DPE_MASK FMC_PFB23CR_B1DPE_MASK
+#define FMC_PFB1CR_B1DPE_SHIFT FMC_PFB23CR_B1DPE_SHIFT
+#define FMC_PFB1CR_B1ICE_MASK FMC_PFB23CR_B1ICE_MASK
+#define FMC_PFB1CR_B1ICE_SHIFT FMC_PFB23CR_B1ICE_SHIFT
+#define FMC_PFB1CR_B1DCE_MASK FMC_PFB23CR_B1DCE_MASK
+#define FMC_PFB1CR_B1DCE_SHIFT FMC_PFB23CR_B1DCE_SHIFT
+#define FMC_PFB1CR_B1MW_MASK FMC_PFB23CR_B1MW_MASK
+#define FMC_PFB1CR_B1MW_SHIFT FMC_PFB23CR_B1MW_SHIFT
+#define FMC_PFB1CR_B1MW(x) FMC_PFB23CR_B1MW(x)
+#define FMC_PFB1CR_B1RWSC_MASK FMC_PFB23CR_B1RWSC_MASK
+#define FMC_PFB1CR_B1RWSC_SHIFT FMC_PFB23CR_B1RWSC_SHIFT
+#define FMC_PFB1CR_B1RWSC(x) FMC_PFB23CR_B1RWSC(x)
+#define LLWU_PE8_WUPE130_MASK LLWU_PE8_WUPE30_MASK
+#define LLWU_PE8_WUPE130_SHIFT LLWU_PE8_WUPE30_SHIFT
+#define LLWU_PE8_WUPE130(x) LLWU_PE8_WUPE30(x)
+#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
+#define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
+#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
+#define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
+#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
+#define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
+#define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
+#define PMC_REGSC_BGBDS_MASK This_symbol_has_been_deprecated
+#define PMC_REGSC_BGBDS_SHIFT This_symbol_has_been_deprecated
+#define SDHC_VENDOR_EXTDMAEN_MASK This_symbol_has_been_deprecated
+#define SDHC_VENDOR_EXTDMAEN_SHIFT This_symbol_has_been_deprecated
+#define SDRAM_CTRL_COC_MASK This_symbol_has_been_deprecated
+#define SDRAM_CTRL_COC_SHIFT This_symbol_has_been_deprecated
+#define SDRAM_CTRL_NAM_MASK This_symbol_has_been_deprecated
+#define SDRAM_CTRL_NAM_SHIFT This_symbol_has_been_deprecated
+#define SMC_STOPCTRL_LPOPO_MASK This_symbol_has_been_deprecated
+#define SMC_STOPCTRL_LPOPO_SHIFT This_symbol_has_been_deprecated
+#define UART_C6_CP_MASK This_symbol_has_been_deprecated
+#define UART_C6_CP_SHIFT This_symbol_has_been_deprecated
+#define UART_C6_CE_MASK This_symbol_has_been_deprecated
+#define UART_C6_CE_SHIFT This_symbol_has_been_deprecated
+#define UART_C6_TX709_MASK This_symbol_has_been_deprecated
+#define UART_C6_TX709_SHIFT This_symbol_has_been_deprecated
+#define UART_C6_EN709_MASK This_symbol_has_been_deprecated
+#define UART_C6_EN709_SHIFT This_symbol_has_been_deprecated
+#define UART_PCTH_PCTH_MASK This_symbol_has_been_deprecated
+#define UART_PCTH_PCTH_SHIFT This_symbol_has_been_deprecated
+#define UART_PCTH_PCTH(x) This_symbol_has_been_deprecated
+#define UART_PCTL_PCTL_MASK This_symbol_has_been_deprecated
+#define UART_PCTL_PCTL_SHIFT This_symbol_has_been_deprecated
+#define UART_PCTL_PCTL(x) This_symbol_has_been_deprecated
+#define UART_IE0_CPTXIE_MASK This_symbol_has_been_deprecated
+#define UART_IE0_CPTXIE_SHIFT This_symbol_has_been_deprecated
+#define UART_IE0_CTXDIE_MASK This_symbol_has_been_deprecated
+#define UART_IE0_CTXDIE_SHIFT This_symbol_has_been_deprecated
+#define UART_IE0_RPLOFIE_MASK This_symbol_has_been_deprecated
+#define UART_IE0_RPLOFIE_SHIFT This_symbol_has_been_deprecated
+#define UART_SDTH_SDTH_MASK This_symbol_has_been_deprecated
+#define UART_SDTH_SDTH_SHIFT This_symbol_has_been_deprecated
+#define UART_SDTH_SDTH(x) This_symbol_has_been_deprecated
+#define UART_SDTL_SDTL_MASK This_symbol_has_been_deprecated
+#define UART_SDTL_SDTL_SHIFT This_symbol_has_been_deprecated
+#define UART_SDTL_SDTL(x) This_symbol_has_been_deprecated
+#define UART_PRE_PREAMBLE_MASK This_symbol_has_been_deprecated
+#define UART_PRE_PREAMBLE_SHIFT This_symbol_has_been_deprecated
+#define UART_PRE_PREAMBLE(x) This_symbol_has_been_deprecated
+#define UART_TPL_TPL_MASK This_symbol_has_been_deprecated
+#define UART_TPL_TPL_SHIFT This_symbol_has_been_deprecated
+#define UART_TPL_TPL(x) This_symbol_has_been_deprecated
+#define UART_IE_TXDIE_MASK This_symbol_has_been_deprecated
+#define UART_IE_TXDIE_SHIFT This_symbol_has_been_deprecated
+#define UART_IE_PSIE_MASK This_symbol_has_been_deprecated
+#define UART_IE_PSIE_SHIFT This_symbol_has_been_deprecated
+#define UART_IE_PCTEIE_MASK This_symbol_has_been_deprecated
+#define UART_IE_PCTEIE_SHIFT This_symbol_has_been_deprecated
+#define UART_IE_PTXIE_MASK This_symbol_has_been_deprecated
+#define UART_IE_PTXIE_SHIFT This_symbol_has_been_deprecated
+#define UART_IE_PRXIE_MASK This_symbol_has_been_deprecated
+#define UART_IE_PRXIE_SHIFT This_symbol_has_been_deprecated
+#define UART_IE_ISDIE_MASK This_symbol_has_been_deprecated
+#define UART_IE_ISDIE_SHIFT This_symbol_has_been_deprecated
+#define UART_IE_WBEIE_MASK This_symbol_has_been_deprecated
+#define UART_IE_WBEIE_SHIFT This_symbol_has_been_deprecated
+#define UART_IE_PEIE_MASK This_symbol_has_been_deprecated
+#define UART_IE_PEIE_SHIFT This_symbol_has_been_deprecated
+#define UART_WB_WBASE_MASK This_symbol_has_been_deprecated
+#define UART_WB_WBASE_SHIFT This_symbol_has_been_deprecated
+#define UART_WB_WBASE(x) This_symbol_has_been_deprecated
+#define UART_S3_TXFF_MASK This_symbol_has_been_deprecated
+#define UART_S3_TXFF_SHIFT This_symbol_has_been_deprecated
+#define UART_S3_PSF_MASK This_symbol_has_been_deprecated
+#define UART_S3_PSF_SHIFT This_symbol_has_been_deprecated
+#define UART_S3_PCTEF_MASK This_symbol_has_been_deprecated
+#define UART_S3_PCTEF_SHIFT This_symbol_has_been_deprecated
+#define UART_S3_PTXF_MASK This_symbol_has_been_deprecated
+#define UART_S3_PTXF_SHIFT This_symbol_has_been_deprecated
+#define UART_S3_PRXF_MASK This_symbol_has_been_deprecated
+#define UART_S3_PRXF_SHIFT This_symbol_has_been_deprecated
+#define UART_S3_ISD_MASK This_symbol_has_been_deprecated
+#define UART_S3_ISD_SHIFT This_symbol_has_been_deprecated
+#define UART_S3_WBEF_MASK This_symbol_has_been_deprecated
+#define UART_S3_WBEF_SHIFT This_symbol_has_been_deprecated
+#define UART_S3_PEF_MASK This_symbol_has_been_deprecated
+#define UART_S3_PEF_SHIFT This_symbol_has_been_deprecated
+#define UART_S4_FE_MASK This_symbol_has_been_deprecated
+#define UART_S4_FE_SHIFT This_symbol_has_been_deprecated
+#define UART_S4_TXDF_MASK This_symbol_has_been_deprecated
+#define UART_S4_TXDF_SHIFT This_symbol_has_been_deprecated
+#define UART_S4_CDET_MASK This_symbol_has_been_deprecated
+#define UART_S4_CDET_SHIFT This_symbol_has_been_deprecated
+#define UART_S4_CDET(x) This_symbol_has_been_deprecated
+#define UART_S4_RPLOF_MASK This_symbol_has_been_deprecated
+#define UART_S4_RPLOF_SHIFT This_symbol_has_been_deprecated
+#define UART_S4_LNF_MASK This_symbol_has_been_deprecated
+#define UART_S4_LNF_SHIFT This_symbol_has_been_deprecated
+#define UART_RPL_RPL_MASK This_symbol_has_been_deprecated
+#define UART_RPL_RPL_SHIFT This_symbol_has_been_deprecated
+#define UART_RPL_RPL(x) This_symbol_has_been_deprecated
+#define UART_RPREL_RPREL_MASK This_symbol_has_been_deprecated
+#define UART_RPREL_RPREL_SHIFT This_symbol_has_been_deprecated
+#define UART_RPREL_RPREL(x) This_symbol_has_been_deprecated
+#define UART_CPW_CPW_MASK This_symbol_has_been_deprecated
+#define UART_CPW_CPW_SHIFT This_symbol_has_been_deprecated
+#define UART_CPW_CPW(x) This_symbol_has_been_deprecated
+#define UART_RIDTH_RIDTH_MASK This_symbol_has_been_deprecated
+#define UART_RIDTH_RIDTH_SHIFT This_symbol_has_been_deprecated
+#define UART_RIDTH_RIDTH(x) This_symbol_has_been_deprecated
+#define UART_RIDTL_RIDTL_MASK This_symbol_has_been_deprecated
+#define UART_RIDTL_RIDTL_SHIFT This_symbol_has_been_deprecated
+#define UART_RIDTL_RIDTL(x) This_symbol_has_been_deprecated
+#define UART_TIDTH_TIDTH_MASK This_symbol_has_been_deprecated
+#define UART_TIDTH_TIDTH_SHIFT This_symbol_has_been_deprecated
+#define UART_TIDTH_TIDTH(x) This_symbol_has_been_deprecated
+#define UART_TIDTL_TIDTL_MASK This_symbol_has_been_deprecated
+#define UART_TIDTL_TIDTL_SHIFT This_symbol_has_been_deprecated
+#define UART_TIDTL_TIDTL(x) This_symbol_has_been_deprecated
+#define UART_RB1TH_RB1TH_MASK This_symbol_has_been_deprecated
+#define UART_RB1TH_RB1TH_SHIFT This_symbol_has_been_deprecated
+#define UART_RB1TH_RB1TH(x) This_symbol_has_been_deprecated
+#define UART_RB1TL_RB1TL_MASK This_symbol_has_been_deprecated
+#define UART_RB1TL_RB1TL_SHIFT This_symbol_has_been_deprecated
+#define UART_RB1TL_RB1TL(x) This_symbol_has_been_deprecated
+#define UART_TB1TH_TB1TH_MASK This_symbol_has_been_deprecated
+#define UART_TB1TH_TB1TH_SHIFT This_symbol_has_been_deprecated
+#define UART_TB1TH_TB1TH(x) This_symbol_has_been_deprecated
+#define UART_TB1TL_TB1TL_MASK This_symbol_has_been_deprecated
+#define UART_TB1TL_TB1TL_SHIFT This_symbol_has_been_deprecated
+#define UART_TB1TL_TB1TL(x) This_symbol_has_been_deprecated
+#define UART_PROG_REG_MIN_DMC1_MASK This_symbol_has_been_deprecated
+#define UART_PROG_REG_MIN_DMC1_SHIFT This_symbol_has_been_deprecated
+#define UART_PROG_REG_MIN_DMC1(x) This_symbol_has_been_deprecated
+#define UART_PROG_REG_LCV_LEN_MASK This_symbol_has_been_deprecated
+#define UART_PROG_REG_LCV_LEN_SHIFT This_symbol_has_been_deprecated
+#define UART_PROG_REG_LCV_LEN(x) This_symbol_has_been_deprecated
+#define UART_STATE_REG_SM_STATE_MASK This_symbol_has_been_deprecated
+#define UART_STATE_REG_SM_STATE_SHIFT This_symbol_has_been_deprecated
+#define UART_STATE_REG_SM_STATE(x) This_symbol_has_been_deprecated
+#define UART_STATE_REG_TX_STATE_MASK This_symbol_has_been_deprecated
+#define UART_STATE_REG_TX_STATE_SHIFT This_symbol_has_been_deprecated
+#define UART_STATE_REG_TX_STATE(x) This_symbol_has_been_deprecated
+#define USB_ADDINFO_IRQNUM_MASK This_symbol_has_been_deprecated
+#define USB_ADDINFO_IRQNUM_SHIFT This_symbol_has_been_deprecated
+#define USB_ADDINFO_IRQNUM(x) This_symbol_has_been_deprecated
+#define USBHS_USBSTS_ULPII_MASK This_symbol_has_been_deprecated
+#define USBHS_USBSTS_ULPII_SHIFT This_symbol_has_been_deprecated
+#define USBHS_USBINTR_ULPIE_MASK This_symbol_has_been_deprecated
+#define USBHS_USBINTR_ULPIE_SHIFT This_symbol_has_been_deprecated
+#define USBPHY_CTRL_CLK_SWITCH_ENJ_MASK This_symbol_has_been_deprecated
+#define USBPHY_CTRL_CLK_SWITCH_ENJ_SHIFT This_symbol_has_been_deprecated
+#define USBPHY_CTRL_SET_CLK_SWITCH_ENJ_MASK This_symbol_has_been_deprecated
+#define USBPHY_CTRL_SET_CLK_SWITCH_ENJ_SHIFT This_symbol_has_been_deprecated
+#define USBPHY_CTRL_CLR_CLK_SWITCH_ENJ_MASK This_symbol_has_been_deprecated
+#define USBPHY_CTRL_CLR_CLK_SWITCH_ENJ_SHIFT This_symbol_has_been_deprecated
+#define USBPHY_CTRL_TOG_CLK_SWITCH_ENJ_MASK This_symbol_has_been_deprecated
+#define USBPHY_CTRL_TOG_CLK_SWITCH_ENJ_SHIFT This_symbol_has_been_deprecated
+#define MCM_ISR_REG(base) MCM_ISCR_REG(base)
+#define MCM_ISR_IRQ_MASK MCM_ISCR_IRQ_MASK
+#define MCM_ISR_IRQ_SHIFT MCM_ISCR_IRQ_SHIFT
+#define MCM_ISR_NMI_MASK MCM_ISCR_NMI_MASK
+#define MCM_ISR_NMI_SHIFT MCM_ISCR_NMI_SHIFT
+#define MCM_ISR_DHREQ_MASK MCM_ISCR_DHREQ_MASK
+#define MCM_ISR_DHREQ_SHIFT MCM_ISCR_DHREQ_SHIFT
+#define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
+#define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
+#define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
+#define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
+#define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
+#define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
+#define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
+#define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
+#define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
+#define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
+#define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
+#define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
+#define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
+#define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
+#define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
+#define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
+#define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
+#define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
+#define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
+#define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
+#define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
+#define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
+#define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
+#define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
+#define DMAMUX0 DMAMUX
+#define DSPI0 SPI0
+#define DSPI1 SPI1
+#define DSPI2 SPI2
+#define FLEXCAN0 CAN0
+#define FLEXCAN1 CAN1
+#define PTA_BASE GPIOA_BASE
+#define PTA GPIOA
+#define PTB_BASE GPIOB_BASE
+#define PTB GPIOB
+#define PTC_BASE GPIOC_BASE
+#define PTC GPIOC
+#define PTD_BASE GPIOD_BASE
+#define PTD GPIOD
+#define PTE_BASE GPIOE_BASE
+#define PTE GPIOE
+#define Watchdog_IRQn WDOG_EWM_IRQn
+#define Watchdog_IRQHandler WDOG_EWM_IRQHandler
+#define LPTimer_IRQn LPTMR0_IRQn
+#define LPTimer_IRQHandler LPTMR0_IRQHandler
+#define UART0_LON_IRQn This_symbol_has_been_deprecated
+#define UART0_LON_IRQHandler This_symbol_has_been_deprecated
+#define LLW_IRQn LLWU_IRQn
+#define LLW_IRQHandler LLWU_IRQHandler
+
+/*!
+ * @}
+ */ /* end of group SDK_Compatibility_Symbols */
+
+
+#endif /* _MK26F18_H_ */
+
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/MK26F18/MK26F18_features.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/freescale/k26f/MK26F18/MK26F18_features.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,1878 @@ +/* +** ################################################################### +** Version: rev. 1.6, 2015-06-08 +** Build: b180801 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2014-12-04) +** Initial version. +** - rev. 1.1 (2015-01-21) +** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances +** - rev. 1.2 (2015-02-19) +** Renamed interrupt vector LLW to LLWU. +** - rev. 1.3 (2015-05-19) +** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT. +** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC. +** Added features for PDB and PORT. +** - rev. 1.4 (2015-05-25) +** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS +** - rev. 1.5 (2015-05-27) +** Several USB features added. +** - rev. 1.6 (2015-06-08) +** FTM features BUS_CLOCK and FAST_CLOCK removed. +** +** ################################################################### +*/ + +#ifndef _MK26F18_FEATURES_H_ +#define _MK26F18_FEATURES_H_ + +/* SOC module features */ + +/* @brief ADC16 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC16_COUNT (2) +/* @brief AIPS availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPS_COUNT (2) +/* @brief AXBS availability on the SoC. */ +#define FSL_FEATURE_SOC_AXBS_COUNT (1) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) +/* @brief MMCAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMCAU_COUNT (1) +/* @brief CMP availability on the SoC. */ +#define FSL_FEATURE_SOC_CMP_COUNT (4) +/* @brief CMT availability on the SoC. */ +#define FSL_FEATURE_SOC_CMT_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief DAC availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC_COUNT (2) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief DMAMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_DMAMUX_COUNT (1) +/* @brief DSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_DSPI_COUNT (3) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (1) +/* @brief FB availability on the SoC. */ +#define FSL_FEATURE_SOC_FB_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FTFE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFE_COUNT (1) +/* @brief FTM availability on the SoC. */ +#define FSL_FEATURE_SOC_FTM_COUNT (4) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (5) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (4) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (1) +/* @brief LLWU availability on the SoC. */ +#define FSL_FEATURE_SOC_LLWU_COUNT (1) +/* @brief LMEM availability on the SoC. */ +#define FSL_FEATURE_SOC_LMEM_COUNT (1) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (1) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (1) +/* @brief MCG availability on the SoC. */ +#define FSL_FEATURE_SOC_MCG_COUNT (1) +/* @brief MCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MCM_COUNT (1) +/* @brief SYSMPU availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSMPU_COUNT (1) +/* @brief OSC availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC_COUNT (1) +/* @brief PDB availability on the SoC. */ +#define FSL_FEATURE_SOC_PDB_COUNT (1) +/* @brief PIT availability on the SoC. */ +#define FSL_FEATURE_SOC_PIT_COUNT (1) +/* @brief PMC availability on the SoC. */ +#define FSL_FEATURE_SOC_PMC_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (5) +/* @brief RCM availability on the SoC. */ +#define FSL_FEATURE_SOC_RCM_COUNT (1) +/* @brief RFSYS availability on the SoC. */ +#define FSL_FEATURE_SOC_RFSYS_COUNT (1) +/* @brief RFVBAT availability on the SoC. */ +#define FSL_FEATURE_SOC_RFVBAT_COUNT (1) +/* @brief RNG availability on the SoC. */ +#define FSL_FEATURE_SOC_RNG_COUNT (1) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_SDHC_COUNT (1) +/* @brief SDRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_SDRAM_COUNT (1) +/* @brief SIM availability on the SoC. */ +#define FSL_FEATURE_SOC_SIM_COUNT (1) +/* @brief SMC availability on the SoC. */ +#define FSL_FEATURE_SOC_SMC_COUNT (1) +/* @brief TPM availability on the SoC. */ +#define FSL_FEATURE_SOC_TPM_COUNT (2) +/* @brief TSI availability on the SoC. */ +#define FSL_FEATURE_SOC_TSI_COUNT (1) +/* @brief UART availability on the SoC. */ +#define FSL_FEATURE_SOC_UART_COUNT (5) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief USBDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBDCD_COUNT (1) +/* @brief USBHS availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHS_COUNT (1) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (1) + +/* ADC16 module features */ + +/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ +#define FSL_FEATURE_ADC16_HAS_PGA (0) +/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ +#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) +/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ +#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) +/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ +#define FSL_FEATURE_ADC16_HAS_DMA (1) +/* @brief Has differential mode (bitfield SC1x[DIFF]). */ +#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) +/* @brief Has FIFO (bit SC4[AFDEP]). */ +#define FSL_FEATURE_ADC16_HAS_FIFO (0) +/* @brief FIFO size if available (bitfield SC4[AFDEP]). */ +#define FSL_FEATURE_ADC16_FIFO_SIZE (0) +/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ +#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) +/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ +#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) +/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ +#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) +/* @brief Has HW averaging (bit SC3[AVGE]). */ +#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) +/* @brief Has offset correction (register OFS). */ +#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) +/* @brief Maximum ADC resolution. */ +#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) +/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ +#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (16) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (0) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (0) +/* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */ +#define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1) +/* @brief Has bitfield name BUF31TO0M. */ +#define FSL_FEATURE_FLEXCAN_HAS_BUF31TO0M (0) +/* @brief Number of interrupt vectors. */ +#define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) + +/* CMP module features */ + +/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ +#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) +/* @brief Has Window mode in CMP (register bit field CR1[WE]). */ +#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) +/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ +#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) +/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ +#define FSL_FEATURE_CMP_HAS_DMA (1) +/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ +#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1) +/* @brief Has DAC Test function in CMP (register DACTEST). */ +#define FSL_FEATURE_CMP_HAS_DAC_TEST (0) + +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + +/* DAC module features */ + +/* @brief Define the size of hardware buffer */ +#define FSL_FEATURE_DAC_BUFFER_SIZE (16) +/* @brief Define whether the buffer supports watermark event detection or not. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) +/* @brief Define whether the buffer supports watermark selection detection or not. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) +/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) +/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) +/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) +/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) +/* @brief Define whether FIFO buffer mode is available or not. */ +#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0) +/* @brief Define whether swing buffer mode is available or not.. */ +#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (32) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 32) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (2) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32) + +/* DMAMUX module features */ + +/* @brief Number of DMA channels (related to number of register CHCFGn). */ +#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 32) +/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ +#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) + +/* EWM module features */ + +/* @brief Has clock select (register CLKCTRL). */ +#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0) +/* @brief Has clock prescaler (register CLKPRESCALER). */ +#define FSL_FEATURE_EWM_HAS_PRESCALER (0) + +/* FLEXBUS module features */ + +/* No feature definitions */ + +/* FLASH module features */ + +/* @brief Is of type FTFA. */ +#define FSL_FEATURE_FLASH_IS_FTFA (0) +/* @brief Is of type FTFE. */ +#define FSL_FEATURE_FLASH_IS_FTFE (1) +/* @brief Is of type FTFL. */ +#define FSL_FEATURE_FLASH_IS_FTFL (0) +/* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ +#define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) +/* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ +#define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1) +/* @brief Has EEPROM region protection (register FEPROT). */ +#define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) +/* @brief Has data flash region protection (register FDPROT). */ +#define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) +/* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ +#define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) +/* @brief Has flash cache control in FMC module. */ +#define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) +/* @brief Has flash cache control in MCM module. */ +#define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) +/* @brief Has flash cache control in MSCM module. */ +#define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) +/* @brief Has prefetch speculation control in flash, such as kv5x. */ +#define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) +/* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ +#define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) +/* @brief P-Flash start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (4) +/* @brief P-Flash block size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096) +/* @brief P-Flash write unit size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8) +/* @brief P-Flash data path width. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16) +/* @brief P-Flash block swap feature. */ +#define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1) +/* @brief P-Flash protection region count. */ +#define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) +/* @brief Has FlexNVM memory. */ +#define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) +/* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ +#define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) +/* @brief FlexNVM block count. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) +/* @brief FlexNVM block size. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) +/* @brief FlexNVM sector size. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) +/* @brief FlexNVM write unit size. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) +/* @brief FlexNVM data path width. */ +#define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) +/* @brief Has FlexRAM memory. */ +#define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) +/* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ +#define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) +/* @brief FlexRAM size. */ +#define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096) +/* @brief Has 0x00 Read 1s Block command. */ +#define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) +/* @brief Has 0x01 Read 1s Section command. */ +#define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) +/* @brief Has 0x02 Program Check command. */ +#define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) +/* @brief Has 0x03 Read Resource command. */ +#define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) +/* @brief Has 0x06 Program Longword command. */ +#define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0) +/* @brief Has 0x07 Program Phrase command. */ +#define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1) +/* @brief Has 0x08 Erase Flash Block command. */ +#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) +/* @brief Has 0x09 Erase Flash Sector command. */ +#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) +/* @brief Has 0x0B Program Section command. */ +#define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) +/* @brief Has 0x40 Read 1s All Blocks command. */ +#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) +/* @brief Has 0x41 Read Once command. */ +#define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) +/* @brief Has 0x43 Program Once command. */ +#define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) +/* @brief Has 0x44 Erase All Blocks command. */ +#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) +/* @brief Has 0x45 Verify Backdoor Access Key command. */ +#define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) +/* @brief Has 0x46 Swap Control command. */ +#define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1) +/* @brief Has 0x49 Erase All Blocks Unsecure command. */ +#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) +/* @brief Has 0x4A Read 1s All Execute-only Segments command. */ +#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) +/* @brief Has 0x4B Erase All Execute-only Segments command. */ +#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) +/* @brief Has 0x80 Program Partition command. */ +#define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) +/* @brief Has 0x81 Set FlexRAM Function command. */ +#define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) +/* @brief P-Flash Erase/Read 1st all block command address alignment. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16) +/* @brief P-Flash Erase sector command address alignment. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16) +/* @brief P-Flash Rrogram/Verify section command address alignment. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16) +/* @brief P-Flash Read resource command address alignment. */ +#define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8) +/* @brief P-Flash Program check command address alignment. */ +#define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) +/* @brief P-Flash Program check command address alignment. */ +#define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16) +/* @brief FlexNVM Erase/Read 1st all block command address alignment. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) +/* @brief FlexNVM Erase sector command address alignment. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) +/* @brief FlexNVM Rrogram/Verify section command address alignment. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) +/* @brief FlexNVM Read resource command address alignment. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) +/* @brief FlexNVM Program check command address alignment. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) +/* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) +/* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) +/* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) +/* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) +/* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) +/* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) +/* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) +/* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) +/* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) +/* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) +/* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) +/* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) +/* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) +/* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) +/* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) +/* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) +/* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) +/* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) +/* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000) +/* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) +/* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) +/* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) +/* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) +/* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) +/* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) +/* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) +/* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) +/* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) +/* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) +/* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) +/* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) +/* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) + +/* FTM module features */ + +/* @brief Number of channels. */ +#define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ + ((x) == FTM0 ? (8) : \ + ((x) == FTM1 ? (2) : \ + ((x) == FTM2 ? (2) : \ + ((x) == FTM3 ? (8) : (-1))))) +/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ +#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) +/* @brief Has extended deadtime value. */ +#define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0) +/* @brief Enable pwm output for the module. */ +#define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0) +/* @brief Has half-cycle reload for the module. */ +#define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0) +/* @brief Has reload interrupt. */ +#define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0) +/* @brief Has reload initialization trigger. */ +#define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0) +/* @brief Has DMA support, bitfield CnSC[DMA]. */ +#define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (1) +/* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */ +#define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (0) +/* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */ +#define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (0) +/* @brief Has no QDCTRL. */ +#define FSL_FEATURE_FTM_HAS_NO_QDCTRL (0) + +/* GPIO module features */ + +/* @brief Has fast (single cycle) access capability via a dedicated memory region. */ +#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0) +/* @brief Has port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) + +/* I2C module features */ + +/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ +#define FSL_FEATURE_I2C_HAS_SMBUS (1) +/* @brief Maximum supported baud rate in kilobit per second. */ +#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) +/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ +#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) +/* @brief Has DMA support (register bit C1[DMAEN]). */ +#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) +/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) +/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) +/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ +#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) +/* @brief Maximum width of the glitch filter in number of bus clocks. */ +#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) +/* @brief Has control of the drive capability of the I2C pins. */ +#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) +/* @brief Has double buffering support (register S2). */ +#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) +/* @brief Has double buffer enable. */ +#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0) + +/* SAI module features */ + +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +#define FSL_FEATURE_SAI_FIFO_COUNT (8) +/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ +#define FSL_FEATURE_SAI_CHANNEL_COUNT (2) +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ +#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ +#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1) +/* @brief Ihe interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) +/* @brief Has register of MCR. */ +#define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has register of MDR */ +#define FSL_FEATURE_SAI_HAS_MDR (1) + +/* LLWU module features */ + +#if defined(CPU_MK26FN2M0CAC18) || defined(CPU_MK26FN2M0VMI18) + /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (32) + /* @brief Has pins 8-15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) + /* @brief Maximum number of internal modules connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) + /* @brief Number of digital filters. */ + #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (4) + /* @brief Has MF register. */ + #define FSL_FEATURE_LLWU_HAS_MF (1) + /* @brief Has PF register. */ + #define FSL_FEATURE_LLWU_HAS_PF (1) + /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ + #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) + /* @brief Has no internal module wakeup flag register. */ + #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) + /* @brief Has external pin 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) + /* @brief Has external pin 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) + /* @brief Has external pin 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4) + /* @brief Has external pin 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) + /* @brief Has external pin 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) + /* @brief Has external pin 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) + /* @brief Has external pin 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) + /* @brief Has external pin 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) + /* @brief Has external pin 8 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) + /* @brief Has external pin 9 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) + /* @brief Has external pin 10 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) + /* @brief Has external pin 11 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) + /* @brief Has external pin 12 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) + /* @brief Has external pin 13 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) + /* @brief Has external pin 14 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) + /* @brief Has external pin 15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) + /* @brief Has external pin 16 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOE_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (6) + /* @brief Has external pin 17 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOE_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (9) + /* @brief Has external pin 18 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOE_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (10) + /* @brief Has external pin 19 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOE_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (17) + /* @brief Has external pin 20 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOE_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (18) + /* @brief Has external pin 21 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (25) + /* @brief Has external pin 22 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (10) + /* @brief Has external pin 23 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (11) + /* @brief Has external pin 24 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (8) + /* @brief Has external pin 25 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (11) + /* @brief Has external pin 26 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) + /* @brief Has external pin 27 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) + /* @brief Has external pin 28 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) + /* @brief Has external pin 29 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) + /* @brief Has external pin 30 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) + /* @brief Has external pin 31 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) + /* @brief Has internal module 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) + /* @brief Has internal module 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) + /* @brief Has internal module 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) + /* @brief Has internal module 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) + /* @brief Has internal module 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) + /* @brief Has internal module 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) + /* @brief Has internal module 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) + /* @brief Has internal module 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) + /* @brief Has Version ID Register (LLWU_VERID). */ + #define FSL_FEATURE_LLWU_HAS_VERID (0) + /* @brief Has Parameter Register (LLWU_PARAM). */ + #define FSL_FEATURE_LLWU_HAS_PARAM (0) + /* @brief Width of registers of the LLWU. */ + #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) + /* @brief Has DMA Enable register (LLWU_DE). */ + #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) +#elif defined(CPU_MK26FN2M0VLQ18) || defined(CPU_MK26FN2M0VMD18) + /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (32) + /* @brief Has pins 8-15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) + /* @brief Maximum number of internal modules connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) + /* @brief Number of digital filters. */ + #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (4) + /* @brief Has MF register. */ + #define FSL_FEATURE_LLWU_HAS_MF (1) + /* @brief Has PF register. */ + #define FSL_FEATURE_LLWU_HAS_PF (1) + /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ + #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) + /* @brief Has no internal module wakeup flag register. */ + #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) + /* @brief Has external pin 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) + /* @brief Has external pin 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) + /* @brief Has external pin 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4) + /* @brief Has external pin 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) + /* @brief Has external pin 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) + /* @brief Has external pin 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) + /* @brief Has external pin 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) + /* @brief Has external pin 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) + /* @brief Has external pin 8 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) + /* @brief Has external pin 9 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) + /* @brief Has external pin 10 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) + /* @brief Has external pin 11 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) + /* @brief Has external pin 12 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) + /* @brief Has external pin 13 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) + /* @brief Has external pin 14 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) + /* @brief Has external pin 15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) + /* @brief Has external pin 16 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOE_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (6) + /* @brief Has external pin 17 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOE_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (9) + /* @brief Has external pin 18 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOE_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (10) + /* @brief Has external pin 19 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) + /* @brief Has external pin 20 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) + /* @brief Has external pin 21 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (25) + /* @brief Has external pin 22 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (10) + /* @brief Has external pin 23 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (11) + /* @brief Has external pin 24 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (8) + /* @brief Has external pin 25 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (GPIOD_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (11) + /* @brief Has external pin 26 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) + /* @brief Has external pin 27 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) + /* @brief Has external pin 28 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) + /* @brief Has external pin 29 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) + /* @brief Has external pin 30 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) + /* @brief Has external pin 31 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) + /* @brief Has internal module 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) + /* @brief Has internal module 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) + /* @brief Has internal module 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) + /* @brief Has internal module 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) + /* @brief Has internal module 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) + /* @brief Has internal module 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) + /* @brief Has internal module 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) + /* @brief Has internal module 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) + /* @brief Has Version ID Register (LLWU_VERID). */ + #define FSL_FEATURE_LLWU_HAS_VERID (0) + /* @brief Has Parameter Register (LLWU_PARAM). */ + #define FSL_FEATURE_LLWU_HAS_PARAM (0) + /* @brief Width of registers of the LLWU. */ + #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) + /* @brief Has DMA Enable register (LLWU_DE). */ + #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) +#endif /* defined(CPU_MK26FN2M0CAC18) || defined(CPU_MK26FN2M0VMI18) */ + +/* LMEM module features */ + +/* @brief Has process identifier support. */ +#define FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE (0) +/* @brief Has L1 cache. */ +#define FSL_FEATURE_HAS_L1CACHE (1) +/* @brief L1 ICACHE line size in byte. */ +#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (16) +/* @brief L1 DCACHE line size in byte. */ +#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (16) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) + +/* LPUART module features */ + +/* @brief LPUART0 and LPUART1 has shared interrupt vector. */ +#define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) +/* @brief Maximal data width with parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (0) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (0) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (0) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (0) + +/* MCG module features */ + +/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ +#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1) +/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ +#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (7) +/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ +#define FSL_FEATURE_MCG_PLL_VDIV_BASE (16) +/* @brief PLL reference clock low range. OSCCLK/PLL_R. */ +#define FSL_FEATURE_MCG_PLL_REF_MIN (8000000) +/* @brief PLL reference clock high range. OSCCLK/PLL_R. */ +#define FSL_FEATURE_MCG_PLL_REF_MAX (16000000) +/* @brief The PLL clock is divided by 2 before VCO divider. */ +#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (1) +/* @brief FRDIV supports 1280. */ +#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) +/* @brief FRDIV supports 1536. */ +#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) +/* @brief MCGFFCLK divider. */ +#define FSL_FEATURE_MCG_FFCLK_DIV (1) +/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ +#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) +/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ +#define FSL_FEATURE_MCG_HAS_RTC_32K (1) +/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ +#define FSL_FEATURE_MCG_HAS_PLL1 (0) +/* @brief Has 48MHz internal oscillator. */ +#define FSL_FEATURE_MCG_HAS_IRC_48M (1) +/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ +#define FSL_FEATURE_MCG_HAS_OSC1 (0) +/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ +#define FSL_FEATURE_MCG_HAS_FCFTRIM (1) +/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ +#define FSL_FEATURE_MCG_HAS_LOLRE (1) +/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ +#define FSL_FEATURE_MCG_USE_OSCSEL (1) +/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ +#define FSL_FEATURE_MCG_USE_PLLREFSEL (0) +/* @brief TBD */ +#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) +/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ +#define FSL_FEATURE_MCG_HAS_PLL (1) +/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ +#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1) +/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ +#define FSL_FEATURE_MCG_HAS_PLL_VDIV (1) +/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ +#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) +/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ +#define FSL_FEATURE_MCG_HAS_FLL (1) +/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ +#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (1) +/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ +#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) +/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ +#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) +/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ +#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (1) +/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ +#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) +/* @brief Has external clock monitor (register bit C6[CME]). */ +#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) +/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ +#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) +/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ +#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) +/* @brief Has PEI mode or PBI mode. */ +#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) +/* @brief Reset clock mode is BLPI. */ +#define FSL_FEATURE_MCG_RESET_IS_BLPI (0) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (99) + +/* OSC module features */ + +/* @brief Has OSC1 external oscillator. */ +#define FSL_FEATURE_OSC_HAS_OSC1 (0) +/* @brief Has OSC0 external oscillator. */ +#define FSL_FEATURE_OSC_HAS_OSC0 (0) +/* @brief Has OSC external oscillator (without index). */ +#define FSL_FEATURE_OSC_HAS_OSC (1) +/* @brief Number of OSC external oscillators. */ +#define FSL_FEATURE_OSC_OSC_COUNT (1) +/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ +#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (1) + +/* PDB module features */ + +/* @brief Define the count of supporting ADC pre-trigger for each channel. */ +#define FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (2) +/* @brief Has DAC support. */ +#define FSL_FEATURE_PDB_HAS_DAC (1) +/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ +#define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0) + +/* PIT module features */ + +/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ +#define FSL_FEATURE_PIT_TIMER_COUNT (4) +/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ +#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) +/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ +#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) +/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ +#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Has timer enable control. */ +#define FSL_FEATURE_PIT_HAS_MDIS (1) + +/* PMC module features */ + +/* @brief Has Bandgap Enable In VLPx Operation support. */ +#define FSL_FEATURE_PMC_HAS_BGEN (1) +/* @brief Has Bandgap Buffer Enable. */ +#define FSL_FEATURE_PMC_HAS_BGBE (1) +/* @brief Has Bandgap Buffer Drive Select. */ +#define FSL_FEATURE_PMC_HAS_BGBDS (0) +/* @brief Has Low-Voltage Detect Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVDV (1) +/* @brief Has Low-Voltage Warning Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVWV (1) +/* @brief Has LPO. */ +#define FSL_FEATURE_PMC_HAS_LPO (0) +/* @brief Has VLPx option PMC_REGSC[VLPO]. */ +#define FSL_FEATURE_PMC_HAS_VLPO (0) +/* @brief Has acknowledge isolation support. */ +#define FSL_FEATURE_PMC_HAS_ACKISO (1) +/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ +#define FSL_FEATURE_PMC_HAS_REGFPM (0) +/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ +#define FSL_FEATURE_PMC_HAS_REGONS (1) +/* @brief Has PMC_HVDSC1. */ +#define FSL_FEATURE_PMC_HAS_HVDSC1 (0) +/* @brief Has PMC_PARAM. */ +#define FSL_FEATURE_PMC_HAS_PARAM (0) +/* @brief Has PMC_VERID. */ +#define FSL_FEATURE_PMC_HAS_VERID (0) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) +/* @brief Has DMA request (register bit field PCR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Has separate drive strength register (HDRVE). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) +/* @brief Has glitch filter (register IOFLT). */ +#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* RCM module features */ + +/* @brief Has Loss-of-Lock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOL (1) +/* @brief Has Loss-of-Clock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOC (1) +/* @brief Has JTAG generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_JTAG (1) +/* @brief Has EzPort generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_EZPORT (1) +/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ +#define FSL_FEATURE_RCM_HAS_EZPMS (1) +/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ +#define FSL_FEATURE_RCM_HAS_BOOTROM (0) +/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ +#define FSL_FEATURE_RCM_HAS_SSRS (1) +/* @brief Has Version ID Register (RCM_VERID). */ +#define FSL_FEATURE_RCM_HAS_VERID (0) +/* @brief Has Parameter Register (RCM_PARAM). */ +#define FSL_FEATURE_RCM_HAS_PARAM (0) +/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ +#define FSL_FEATURE_RCM_HAS_SRIE (0) +/* @brief Width of registers of the RCM. */ +#define FSL_FEATURE_RCM_REG_WIDTH (8) +/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ +#define FSL_FEATURE_RCM_HAS_CORE1 (0) +/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ +#define FSL_FEATURE_RCM_HAS_MDM_AP (1) +/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ +#define FSL_FEATURE_RCM_HAS_WAKEUP (1) + +/* RTC module features */ + +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (1) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (1) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (0) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) +/* @brief Has Tamper Interrupt Register (register TIR). */ +#define FSL_FEATURE_RTC_HAS_TIR (0) +/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) +/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_SIE (0) +/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) +/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ +#define FSL_FEATURE_RTC_HAS_SR_TIDF (0) +/* @brief Has Tamper Detect Register (register TDR). */ +#define FSL_FEATURE_RTC_HAS_TDR (0) +/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_TPF (0) +/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_STF (0) +/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) +/* @brief Has Tamper Time Seconds Register (register TTSR). */ +#define FSL_FEATURE_RTC_HAS_TTSR (1) +/* @brief Has Pin Configuration Register (register PCR). */ +#define FSL_FEATURE_RTC_HAS_PCR (0) + +/* SDHC module features */ + +/* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */ +#define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (0) +/* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */ +#define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (0) +/* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */ +#define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (0) + +/* SIM module features */ + +/* @brief Has USB FS divider. */ +#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) +/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ +#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) +/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) +/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ +#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) +/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) +/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ +#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) +/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) +/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) +/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (1) +/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) +/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) +/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PCR (0) +/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_MCC (0) +/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ +#define FSL_FEATURE_SIM_OPT_HAS_ODE (0) +/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ +#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (1) +/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ +#define FSL_FEATURE_SIM_OPT_UART_COUNT (4) +/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) +/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) +/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) +/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) +/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) +/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ +#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) +/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) +/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) +/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) +/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) +/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) +/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) +/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) +/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) +/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) +/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) +/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) +/* @brief Has FTM module(s) configuration. */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM (1) +/* @brief Number of FTM modules. */ +#define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) +/* @brief Number of FTM triggers with selectable source. */ +#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) +/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) +/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) +/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) +/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) +/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) +/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) +/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4) +/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) +/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) +/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) +/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) +/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) +/* @brief Has TPM module(s) configuration. */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM (1) +/* @brief The highest TPM module index. */ +#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) +/* @brief Has TPM module with index 0. */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) +/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0) +/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) +/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) +/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0) +/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) +/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) +/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) +/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) +/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ +#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) +/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) +/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) +/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1) +/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) +/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) +/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) +/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) +/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) +/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) +/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1) +/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) +/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) +/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) +/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) +/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) +/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) +/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) +/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) +/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (1) +/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) +/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) +/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) +/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) +/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) +/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) +/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) +/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) +/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) +/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) +/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) +/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ +#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) +/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) +/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) +/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) +/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) +/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (1) +/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) +/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1) +/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) +/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) +/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) +/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) +/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) +/* @brief Has device die ID (register bit field SDID[DIEID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) +/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) +/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) +/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) +/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) +/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) +/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1) +/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1) +/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) +/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) +/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) +/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) +/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) +/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1) +/* @brief Has miscellanious control register (register MCR). */ +#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) +/* @brief Has COP watchdog (registers COPC and SRVCOP). */ +#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) +/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ +#define FSL_FEATURE_SIM_HAS_COP_STOP (0) +/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ +#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) + +/* SMC module features */ + +/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ +#define FSL_FEATURE_SMC_HAS_PSTOPO (1) +/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ +#define FSL_FEATURE_SMC_HAS_LPOPO (0) +/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ +#define FSL_FEATURE_SMC_HAS_PORPO (1) +/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ +#define FSL_FEATURE_SMC_HAS_LPWUI (0) +/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ +#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) +/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) +/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) +/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ +#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1) +/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ +#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1) +/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ +#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ +#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has stop submode. */ +#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) +/* @brief Has stop submode 0(VLLS0). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) +/* @brief Has stop submode 1(VLLS1). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1) +/* @brief Has stop submode 2(VLLS2). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) +/* @brief Has SMC_PARAM. */ +#define FSL_FEATURE_SMC_HAS_PARAM (0) +/* @brief Has SMC_VERID. */ +#define FSL_FEATURE_SMC_HAS_VERID (0) +/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ +#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) +/* @brief Has tamper reset (register bit SRS[TAMPER]). */ +#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) +/* @brief Has security violation reset (register bit SRS[SECVIO]). */ +#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) + +/* DSPI module features */ + +/* @brief Receive/transmit FIFO size in number of items. */ +#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ + ((x) == SPI0 ? (4) : \ + ((x) == SPI1 ? (1) : \ + ((x) == SPI2 ? (1) : (-1)))) +/* @brief Maximum transfer data width in bits. */ +#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) +/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ +#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) +/* @brief Number of chip select pins. */ +#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6) +/* @brief Number of CTAR registers. */ +#define FSL_FEATURE_DSPI_CTAR_COUNT (2) +/* @brief Has chip select strobe capability on the PCS5 pin. */ +#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) +/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ +#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) +/* @brief Has 16-bit data transfer support. */ +#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) + +/* SYSMPU module features */ + +/* @brief Specifies number of descriptors available. */ +#define FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT (12) +/* @brief Has process identifier support. */ +#define FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER (1) +/* @brief Total number of MPU slave. */ +#define FSL_FEATURE_SYSMPU_SLAVE_COUNT (5) +/* @brief Total number of MPU master. */ +#define FSL_FEATURE_SYSMPU_MASTER_COUNT (7) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* TPM module features */ + +/* @brief Bus clock is the source clock for the module. */ +#define FSL_FEATURE_TPM_BUS_CLOCK (0) +/* @brief Number of channels. */ +#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) (2) +/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ +#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) +/* @brief Has TPM_PARAM. */ +#define FSL_FEATURE_TPM_HAS_PARAM (0) +/* @brief Has TPM_VERID. */ +#define FSL_FEATURE_TPM_HAS_VERID (0) +/* @brief Has TPM_GLOBAL. */ +#define FSL_FEATURE_TPM_HAS_GLOBAL (0) +/* @brief Has TPM_TRIG. */ +#define FSL_FEATURE_TPM_HAS_TRIG (0) +/* @brief Has counter pause on trigger. */ +#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) +/* @brief Has external trigger selection. */ +#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) +/* @brief Has TPM_COMBINE register. */ +#define FSL_FEATURE_TPM_HAS_COMBINE (1) +/* @brief Whether COMBINE register has effect. */ +#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (1) +/* @brief Has TPM_POL. */ +#define FSL_FEATURE_TPM_HAS_POL (1) +/* @brief Has TPM_FILTER register. */ +#define FSL_FEATURE_TPM_HAS_FILTER (1) +/* @brief Whether FILTER register has effect. */ +#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (1) +/* @brief Has TPM_QDCTRL register. */ +#define FSL_FEATURE_TPM_HAS_QDCTRL (1) +/* @brief Whether QDCTRL register has effect. */ +#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (1) + +/* TSI module features */ + +/* @brief TSI module version. */ +#define FSL_FEATURE_TSI_VERSION (4) +/* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */ +#define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (1) +/* @brief Number of TSI channels. */ +#define FSL_FEATURE_TSI_CHANNEL_COUNT (16) + +/* UART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_UART_HAS_FIFO (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) +/* @brief Peripheral type. */ +#define FSL_FEATURE_UART_IS_SCI (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_UART_FIFO_SIZEn(x) \ + ((x) == UART0 ? (8) : \ + ((x) == UART1 ? (8) : \ + ((x) == UART2 ? (1) : \ + ((x) == UART3 ? (1) : \ + ((x) == UART4 ? (1) : (-1)))))) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) +/* @brief Maximal data width with parity bit. */ +#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_UART_HAS_DMA_SELECT (1) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) +/* @brief Lin break detect available (has bit BDH[LBKDIE]). */ +#define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ + ((x) == UART0 ? (1) : \ + ((x) == UART1 ? (1) : \ + ((x) == UART2 ? (1) : \ + ((x) == UART3 ? (1) : \ + ((x) == UART4 ? (0) : (-1)))))) + +/* USB module features */ + +/* @brief KHCI module instance count */ +#define FSL_FEATURE_USB_KHCI_COUNT (1) +/* @brief HOST mode enabled */ +#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) +/* @brief OTG mode enabled */ +#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM (0) +/* @brief Has KEEP_ALIVE_CTRL register */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) +/* @brief Has the Dynamic SOF threshold compare support */ +#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0) +/* @brief Has the VBUS detect support */ +#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) +/* @brief Has the IRC48M module clock support */ +#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USB_ENDPT_COUNT (16) +/* @brief Has STALL_IL/OL_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (0) +/* @brief Has STALL_IH/OH_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (0) + +/* USBHS module features */ + +/* @brief EHCI module instance count */ +#define FSL_FEATURE_USBHS_EHCI_COUNT (1) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USBHS_ENDPT_COUNT (8) + +/* VREF module features */ + +/* @brief Has chop oscillator (bit TRM[CHOPEN]) */ +#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) +/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ +#define FSL_FEATURE_VREF_HAS_COMPENSATION (1) +/* @brief If high/low buffer mode supported */ +#define FSL_FEATURE_VREF_MODE_LV_TYPE (1) +/* @brief Module has also low reference (registers VREFL/VREFH) */ +#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) +/* @brief Has VREF_TRM4. */ +#define FSL_FEATURE_VREF_HAS_TRM4 (0) + +/* WDOG module features */ + +/* @brief Watchdog is available. */ +#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) +/* @brief Has Wait mode support. */ +#define FSL_FEATURE_WDOG_HAS_WAITEN (1) + +#endif /* _MK26F18_FEATURES_H_ */ +
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/MK26F18/fsl_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/MK26F18/fsl_clock.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1896 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_common.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Macro definition remap workaround. */
+#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
+#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
+#endif
+#if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
+#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
+#endif
+#if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
+#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
+#endif
+#if (defined(MCG_C6_CME_MASK) && !(defined(MCG_C6_CME0_MASK)))
+#define MCG_C6_CME0_MASK MCG_C6_CME_MASK
+#endif
+
+/* PLL fixed multiplier when there is not PRDIV and VDIV. */
+#define PLL_FIXED_MULT (375U)
+/* Max frequency of the reference clock used for internal clock trim. */
+#define TRIM_REF_CLK_MIN (8000000U)
+/* Min frequency of the reference clock used for internal clock trim. */
+#define TRIM_REF_CLK_MAX (16000000U)
+/* Max trim value of fast internal reference clock. */
+#define TRIM_FIRC_MAX (5000000U)
+/* Min trim value of fast internal reference clock. */
+#define TRIM_FIRC_MIN (3000000U)
+/* Max trim value of fast internal reference clock. */
+#define TRIM_SIRC_MAX (39063U)
+/* Min trim value of fast internal reference clock. */
+#define TRIM_SIRC_MIN (31250U)
+
+#define MCG_S_IRCST_VAL ((MCG->S & MCG_S_IRCST_MASK) >> MCG_S_IRCST_SHIFT)
+#define MCG_S_CLKST_VAL ((MCG->S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT)
+#define MCG_S_IREFST_VAL ((MCG->S & MCG_S_IREFST_MASK) >> MCG_S_IREFST_SHIFT)
+#define MCG_S_PLLST_VAL ((MCG->S & MCG_S_PLLST_MASK) >> MCG_S_PLLST_SHIFT)
+#define MCG_C1_FRDIV_VAL ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
+#define MCG_C2_LP_VAL ((MCG->C2 & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT)
+#define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
+#define MCG_SC_FCRDIV_VAL ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
+#define MCG_S2_PLLCST_VAL ((MCG->S2 & MCG_S2_PLLCST_MASK) >> MCG_S2_PLLCST_SHIFT)
+#define MCG_C7_OSCSEL_VAL ((MCG->C7 & MCG_C7_OSCSEL_MASK) >> MCG_C7_OSCSEL_SHIFT)
+#define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
+#define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
+#define MCG_C7_PLL32KREFSEL_VAL ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) >> MCG_C7_PLL32KREFSEL_SHIFT)
+#define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
+#define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT)
+#define MCG_C11_PRDIV1_VAL ((MCG->C11 & MCG_C11_PRDIV1_MASK) >> MCG_C11_PRDIV1_SHIFT)
+#define MCG_C12_VDIV1_VAL ((MCG->C12 & MCG_C12_VDIV1_MASK) >> MCG_C12_VDIV1_SHIFT)
+#define MCG_C5_PRDIV0_VAL ((MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
+#define MCG_C6_VDIV0_VAL ((MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)
+
+#define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
+
+#define SIM_CLKDIV1_OUTDIV1_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)
+#define SIM_CLKDIV1_OUTDIV2_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT)
+#define SIM_CLKDIV1_OUTDIV3_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV3_MASK) >> SIM_CLKDIV1_OUTDIV3_SHIFT)
+#define SIM_CLKDIV1_OUTDIV4_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT)
+#define SIM_SOPT1_OSC32KSEL_VAL ((SIM->SOPT1 & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT)
+#define SIM_SOPT2_PLLFLLSEL_VAL ((SIM->SOPT2 & SIM_SOPT2_PLLFLLSEL_MASK) >> SIM_SOPT2_PLLFLLSEL_SHIFT)
+#define SIM_CLKDIV3_PLLFLLDIV_VAL ((SIM->CLKDIV3 & SIM_CLKDIV3_PLLFLLDIV_MASK) >> SIM_CLKDIV3_PLLFLLDIV_SHIFT)
+#define SIM_CLKDIV3_PLLFLLFRAC_VAL ((SIM->CLKDIV3 & SIM_CLKDIV3_PLLFLLFRAC_MASK) >> SIM_CLKDIV3_PLLFLLFRAC_SHIFT)
+
+/* MCG_S_CLKST definition. */
+enum _mcg_clkout_stat
+{
+ kMCG_ClkOutStatFll, /* FLL. */
+ kMCG_ClkOutStatInt, /* Internal clock. */
+ kMCG_ClkOutStatExt, /* External clock. */
+ kMCG_ClkOutStatPll /* PLL. */
+};
+
+/* MCG_S_PLLST definition. */
+enum _mcg_pllst
+{
+ kMCG_PllstFll, /* FLL is used. */
+ kMCG_PllstPll /* PLL is used. */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Slow internal reference clock frequency. */
+static uint32_t s_slowIrcFreq = 32768U;
+/* Fast internal reference clock frequency. */
+static uint32_t s_fastIrcFreq = 4000000U;
+/* The MCG external PLL clock frequency. */
+static uint32_t s_extPllFreq = 0U;
+
+/* External XTAL0 (OSC0) clock frequency. */
+uint32_t g_xtal0Freq;
+/* External XTAL32K clock frequency. */
+uint32_t g_xtal32Freq;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get the MCG external reference clock frequency.
+ *
+ * Get the current MCG external reference clock frequency in Hz. It is
+ * the frequency select by MCG_C7[OSCSEL]. This is an internal function.
+ *
+ * @return MCG external reference clock frequency in Hz.
+ */
+static uint32_t CLOCK_GetMcgExtClkFreq(void);
+
+/*!
+ * @brief Get the MCG FLL external reference clock frequency.
+ *
+ * Get the current MCG FLL external reference clock frequency in Hz. It is
+ * the frequency after by MCG_C1[FRDIV]. This is an internal function.
+ *
+ * @return MCG FLL external reference clock frequency in Hz.
+ */
+static uint32_t CLOCK_GetFllExtRefClkFreq(void);
+
+/*!
+ * @brief Get the MCG FLL reference clock frequency.
+ *
+ * Get the current MCG FLL reference clock frequency in Hz. It is
+ * the frequency select by MCG_C1[IREFS]. This is an internal function.
+ *
+ * @return MCG FLL reference clock frequency in Hz.
+ */
+static uint32_t CLOCK_GetFllRefClkFreq(void);
+
+/*!
+ * @brief Get the frequency of clock selected by MCG_C2[IRCS].
+ *
+ * This clock's two output:
+ * 1. MCGOUTCLK when MCG_S[CLKST]=0.
+ * 2. MCGIRCLK when MCG_C1[IRCLKEN]=1.
+ *
+ * @return The frequency in Hz.
+ */
+static uint32_t CLOCK_GetInternalRefClkSelectFreq(void);
+
+/*!
+ * @brief Get the MCG PLL/PLL0 reference clock frequency.
+ *
+ * Get the current MCG PLL/PLL0 reference clock frequency in Hz.
+ * This is an internal function.
+ *
+ * @return MCG PLL/PLL0 reference clock frequency in Hz.
+ */
+static uint32_t CLOCK_GetPll0RefFreq(void);
+
+/*!
+ * @brief Calculate the RANGE value base on crystal frequency.
+ *
+ * To setup external crystal oscillator, must set the register bits RANGE
+ * base on the crystal frequency. This function returns the RANGE base on the
+ * input frequency. This is an internal function.
+ *
+ * @param freq Crystal frequency in Hz.
+ * @return The RANGE value.
+ */
+static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq);
+
+/*!
+ * @brief Delay function to wait FLL stable.
+ *
+ * Delay function to wait FLL stable in FEI mode or FEE mode, should wait at least
+ * 1ms. Every time changes FLL setting, should wait this time for FLL stable.
+ */
+static void CLOCK_FllStableDelay(void);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t CLOCK_GetMcgExtClkFreq(void)
+{
+ uint32_t freq;
+
+ switch (MCG_C7_OSCSEL_VAL)
+ {
+ case 0U:
+ /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
+ assert(g_xtal0Freq);
+ freq = g_xtal0Freq;
+ break;
+ case 1U:
+ /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
+ assert(g_xtal32Freq);
+ freq = g_xtal32Freq;
+ break;
+ case 2U:
+ freq = MCG_INTERNAL_IRC_48M;
+ break;
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq;
+}
+
+static uint32_t CLOCK_GetFllExtRefClkFreq(void)
+{
+ /* FllExtRef = McgExtRef / FllExtRefDiv */
+ uint8_t frdiv;
+ uint8_t range;
+ uint8_t oscsel;
+
+ uint32_t freq = CLOCK_GetMcgExtClkFreq();
+
+ if (!freq)
+ {
+ return freq;
+ }
+
+ frdiv = MCG_C1_FRDIV_VAL;
+ freq >>= frdiv;
+
+ range = MCG_C2_RANGE_VAL;
+ oscsel = MCG_C7_OSCSEL_VAL;
+
+ /*
+ When should use divider 32, 64, 128, 256, 512, 1024, 1280, 1536.
+ 1. MCG_C7[OSCSEL] selects IRC48M.
+ 2. MCG_C7[OSCSEL] selects OSC0 and MCG_C2[RANGE] is not 0.
+ */
+ if (((0U != range) && (kMCG_OscselOsc == oscsel)) || (kMCG_OscselIrc == oscsel))
+ {
+ switch (frdiv)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ freq >>= 5u;
+ break;
+ case 6:
+ /* 64*20=1280 */
+ freq /= 20u;
+ break;
+ case 7:
+ /* 128*12=1536 */
+ freq /= 12u;
+ break;
+ default:
+ freq = 0u;
+ break;
+ }
+ }
+
+ return freq;
+}
+
+static uint32_t CLOCK_GetInternalRefClkSelectFreq(void)
+{
+ if (kMCG_IrcSlow == MCG_S_IRCST_VAL)
+ {
+ /* Slow internal reference clock selected*/
+ return s_slowIrcFreq;
+ }
+ else
+ {
+ /* Fast internal reference clock selected*/
+ return s_fastIrcFreq >> MCG_SC_FCRDIV_VAL;
+ }
+}
+
+static uint32_t CLOCK_GetFllRefClkFreq(void)
+{
+ /* If use external reference clock. */
+ if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
+ {
+ return CLOCK_GetFllExtRefClkFreq();
+ }
+ /* If use internal reference clock. */
+ else
+ {
+ return s_slowIrcFreq;
+ }
+}
+
+static uint32_t CLOCK_GetPll0RefFreq(void)
+{
+ /* MCG external reference clock. */
+ return CLOCK_GetMcgExtClkFreq();
+}
+
+static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq)
+{
+ uint8_t range;
+
+ if (freq <= 39063U)
+ {
+ range = 0U;
+ }
+ else if (freq <= 8000000U)
+ {
+ range = 1U;
+ }
+ else
+ {
+ range = 2U;
+ }
+
+ return range;
+}
+
+static void CLOCK_FllStableDelay(void)
+{
+ /*
+ Should wait at least 1ms. Because in these modes, the core clock is 100MHz
+ at most, so this function could obtain the 1ms delay.
+ */
+ volatile uint32_t i = 30000U;
+ while (i--)
+ {
+ __NOP();
+ }
+}
+
+uint32_t CLOCK_GetOsc0ErClkUndivFreq(void)
+{
+ if (OSC0->CR & OSC_CR_ERCLKEN_MASK)
+ {
+ /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
+ assert(g_xtal0Freq);
+ return g_xtal0Freq;
+ }
+ else
+ {
+ return 0U;
+ }
+}
+
+uint32_t CLOCK_GetOsc0ErClkDivFreq(void)
+{
+ if (OSC0->CR & OSC_CR_ERCLKEN_MASK)
+ {
+ /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
+ assert(g_xtal0Freq);
+ return g_xtal0Freq >> ((OSC0->DIV & OSC_DIV_ERPS_MASK) >> OSC_DIV_ERPS_SHIFT);
+ }
+ else
+ {
+ return 0U;
+ }
+}
+
+uint32_t CLOCK_GetEr32kClkFreq(void)
+{
+ uint32_t freq;
+
+ switch (SIM_SOPT1_OSC32KSEL_VAL)
+ {
+ case 0U: /* OSC 32k clock */
+ freq = (CLOCK_GetOsc0ErClkDivFreq() == 32768U) ? 32768U : 0U;
+ break;
+ case 2U: /* RTC 32k clock */
+ /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
+ assert(g_xtal32Freq);
+ freq = g_xtal32Freq;
+ break;
+ case 3U: /* LPO clock */
+ freq = LPO_CLK_FREQ;
+ break;
+ default:
+ freq = 0U;
+ break;
+ }
+ return freq;
+}
+
+uint32_t CLOCK_GetPllFllSelClkFreq(void)
+{
+ uint32_t freq;
+
+ switch (SIM_SOPT2_PLLFLLSEL_VAL)
+ {
+ case 0U: /* FLL. */
+ freq = CLOCK_GetFllFreq();
+ break;
+ case 1U: /* PLL. */
+ freq = CLOCK_GetPll0Freq();
+ break;
+ case 2U:
+ freq = CLOCK_GetExtPllFreq();
+ break;
+ case 3U: /* MCG IRC48M. */
+ freq = MCG_INTERNAL_IRC_48M;
+ break;
+ default:
+ freq = 0U;
+ break;
+ }
+
+ freq *= (SIM_CLKDIV3_PLLFLLFRAC_VAL + 1U);
+ freq /= (SIM_CLKDIV3_PLLFLLDIV_VAL + 1U);
+ return freq;
+}
+
+uint32_t CLOCK_GetOsc0ErClkFreq(void)
+{
+ return CLOCK_GetOsc0ErClkDivFreq();
+}
+
+uint32_t CLOCK_GetPlatClkFreq(void)
+{
+ return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1);
+}
+
+uint32_t CLOCK_GetFlashClkFreq(void)
+{
+ return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1);
+}
+
+uint32_t CLOCK_GetFlexBusClkFreq(void)
+{
+ return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1);
+}
+
+uint32_t CLOCK_GetBusClkFreq(void)
+{
+ return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1);
+}
+
+uint32_t CLOCK_GetCoreSysClkFreq(void)
+{
+ return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1);
+}
+
+uint32_t CLOCK_GetFreq(clock_name_t clockName)
+{
+ uint32_t freq;
+
+ switch (clockName)
+ {
+ case kCLOCK_CoreSysClk:
+ case kCLOCK_PlatClk:
+ freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1);
+ break;
+ case kCLOCK_BusClk:
+ freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1);
+ break;
+ case kCLOCK_FlexBusClk:
+ freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1);
+ break;
+ case kCLOCK_FlashClk:
+ freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1);
+ break;
+ case kCLOCK_PllFllSelClk:
+ freq = CLOCK_GetPllFllSelClkFreq();
+ break;
+ case kCLOCK_Er32kClk:
+ freq = CLOCK_GetEr32kClkFreq();
+ break;
+ case kCLOCK_Osc0ErClk:
+ freq = CLOCK_GetOsc0ErClkDivFreq();
+ break;
+ case kCLOCK_Osc0ErClkUndiv:
+ freq = CLOCK_GetOsc0ErClkUndivFreq();
+ break;
+ case kCLOCK_McgFixedFreqClk:
+ freq = CLOCK_GetFixedFreqClkFreq();
+ break;
+ case kCLOCK_McgInternalRefClk:
+ freq = CLOCK_GetInternalRefClkFreq();
+ break;
+ case kCLOCK_McgFllClk:
+ freq = CLOCK_GetFllFreq();
+ break;
+ case kCLOCK_McgPll0Clk:
+ freq = CLOCK_GetPll0Freq();
+ break;
+ case kCLOCK_McgIrc48MClk:
+ freq = MCG_INTERNAL_IRC_48M;
+ break;
+ case kCLOCK_LpoClk:
+ freq = LPO_CLK_FREQ;
+ break;
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq;
+}
+
+void CLOCK_SetSimConfig(sim_clock_config_t const *config)
+{
+ SIM->CLKDIV1 = config->clkdiv1;
+ CLOCK_SetPllFllSelClock(config->pllFllSel, config->pllFllDiv, config->pllFllFrac);
+ CLOCK_SetEr32kClock(config->er32kSrc);
+}
+
+bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
+{
+ /* In current implementation, USBPFDCLK is not used for USB FS. */
+ assert(kCLOCK_UsbSrcUsbPfd != src);
+
+ bool ret = true;
+
+ CLOCK_DisableClock(kCLOCK_Usbfs0);
+
+ if (kCLOCK_UsbSrcExt == src)
+ {
+ SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK;
+ }
+ else
+ {
+ switch (freq)
+ {
+ case 120000000U:
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1);
+ break;
+ case 96000000U:
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0);
+ break;
+ case 72000000U:
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
+ break;
+ case 48000000U:
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0);
+ break;
+ default:
+ ret = false;
+ break;
+ }
+
+ SIM->SOPT2 = ((SIM->SOPT2 & ~(SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK)) | (uint32_t)src);
+ }
+
+ CLOCK_EnableClock(kCLOCK_Usbfs0);
+
+ if (kCLOCK_UsbSrcIrc48M == src)
+ {
+ USB0->CLK_RECOVER_IRC_EN = 0x03U;
+ USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
+ }
+ return ret;
+}
+
+bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq)
+{
+ volatile uint32_t i;
+
+ /*
+ * In order to bring up the internal 480MHz USB PLL clock, should make sure:
+ * 1. 32kHz IRC clock enable by setting IRCLKEN bit in MCG_C1 register.
+ * 2. External reference clock enable on XTAL by setting ERCLKEN bit in OSC_CR register.
+ */
+ assert(MCG->C1 & MCG_C1_IRCLKEN_MASK);
+ assert(!(MCG->C2 & MCG_C2_IRCS_MASK));
+ assert(OSC0->CR & OSC_CR_ERCLKEN_MASK);
+
+ /* Source and freq are not used for USB HS. */
+ src = src;
+ freq = freq;
+
+ SIM->SOPT2 |= SIM_SOPT2_USBREGEN_MASK;
+ SIM->SCGC3 |= (SIM_SCGC3_USBHS_MASK | SIM_SCGC3_USBHSPHY_MASK);
+
+ i = 500000U;
+ while (i--)
+ {
+ __NOP();
+ }
+
+ SIM->USBPHYCTL = ((SIM->USBPHYCTL & ~(SIM_USBPHYCTL_USB3VOUTTRG_MASK)) | SIM_USBPHYCTL_USB3VOUTTRG(6U) /* 3.310V */
+ | SIM_USBPHYCTL_USBVREGSEL_MASK); /* VREG_IN1 */
+
+ return true;
+}
+
+uint32_t CLOCK_GetOutClkFreq(void)
+{
+ uint32_t mcgoutclk;
+ uint32_t clkst = MCG_S_CLKST_VAL;
+ uint32_t pllcst = MCG_S2_PLLCST_VAL;
+
+ switch (clkst)
+ {
+ case kMCG_ClkOutStatPll:
+ switch (pllcst)
+ {
+ case kMCG_PllClkSelExtPll:
+ mcgoutclk = CLOCK_GetExtPllFreq();
+ break;
+ case kMCG_PllClkSelPll0:
+ mcgoutclk = CLOCK_GetPll0Freq();
+ break;
+ default:
+ mcgoutclk = 0U;
+ break;
+ }
+ break;
+ case kMCG_ClkOutStatFll:
+ mcgoutclk = CLOCK_GetFllFreq();
+ break;
+ case kMCG_ClkOutStatInt:
+ mcgoutclk = CLOCK_GetInternalRefClkSelectFreq();
+ break;
+ case kMCG_ClkOutStatExt:
+ mcgoutclk = CLOCK_GetMcgExtClkFreq();
+ break;
+ default:
+ mcgoutclk = 0U;
+ break;
+ }
+ return mcgoutclk;
+}
+
+uint32_t CLOCK_GetFllFreq(void)
+{
+ static const uint16_t fllFactorTable[4][2] = {{640, 732}, {1280, 1464}, {1920, 2197}, {2560, 2929}};
+
+ uint8_t drs, dmx32;
+ uint32_t freq;
+
+ /* If FLL is not enabled currently, then return 0U. */
+ if ((MCG->C2 & MCG_C2_LP_MASK) || (MCG->S & MCG_S_PLLST_MASK))
+ {
+ return 0U;
+ }
+
+ /* Get FLL reference clock frequency. */
+ freq = CLOCK_GetFllRefClkFreq();
+ if (!freq)
+ {
+ return freq;
+ }
+
+ drs = MCG_C4_DRST_DRS_VAL;
+ dmx32 = MCG_C4_DMX32_VAL;
+
+ return freq * fllFactorTable[drs][dmx32];
+}
+
+uint32_t CLOCK_GetInternalRefClkFreq(void)
+{
+ /* If MCGIRCLK is gated. */
+ if (!(MCG->C1 & MCG_C1_IRCLKEN_MASK))
+ {
+ return 0U;
+ }
+
+ return CLOCK_GetInternalRefClkSelectFreq();
+}
+
+uint32_t CLOCK_GetFixedFreqClkFreq(void)
+{
+ uint32_t freq = CLOCK_GetFllRefClkFreq();
+
+ /* MCGFFCLK must be no more than MCGOUTCLK/8. */
+ if ((freq) && (freq <= (CLOCK_GetOutClkFreq() / 8U)))
+ {
+ return freq;
+ }
+ else
+ {
+ return 0U;
+ }
+}
+
+uint32_t CLOCK_GetPll0Freq(void)
+{
+ uint32_t mcgpll0clk;
+
+ /* If PLL0 is not enabled, return 0. */
+ if (!(MCG->S & MCG_S_LOCK0_MASK))
+ {
+ return 0U;
+ }
+
+ mcgpll0clk = CLOCK_GetPll0RefFreq();
+
+ /*
+ * Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock.
+ * Please call CLOCK_SetXtal1Freq base on board setting before using OSC1 clock.
+ */
+ assert(mcgpll0clk);
+
+ mcgpll0clk /= (FSL_FEATURE_MCG_PLL_PRDIV_BASE + MCG_C5_PRDIV0_VAL);
+ mcgpll0clk *= (FSL_FEATURE_MCG_PLL_VDIV_BASE + MCG_C6_VDIV0_VAL);
+
+ mcgpll0clk >>= 1U;
+ return mcgpll0clk;
+}
+
+uint32_t CLOCK_GetExtPllFreq(void)
+{
+ return s_extPllFreq;
+}
+
+void CLOCK_SetExtPllFreq(uint32_t freq)
+{
+ s_extPllFreq = freq;
+}
+
+status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
+{
+ bool needDelay;
+ uint32_t i;
+
+#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
+ /* If change MCG_C7[OSCSEL] and external reference clock is system clock source, return error. */
+ if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK)))
+ {
+ return kStatus_MCG_SourceUsed;
+ }
+#endif /* MCG_CONFIG_CHECK_PARAM */
+
+ if (MCG_C7_OSCSEL_VAL != oscsel)
+ {
+ /* If change OSCSEL, need to delay, ERR009878. */
+ needDelay = true;
+ }
+ else
+ {
+ needDelay = false;
+ }
+
+ MCG->C7 = (MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel);
+ if (kMCG_OscselOsc == oscsel)
+ {
+ if (MCG->C2 & MCG_C2_EREFS_MASK)
+ {
+ while (!(MCG->S & MCG_S_OSCINIT0_MASK))
+ {
+ }
+ }
+ }
+
+ if (needDelay)
+ {
+ /* ERR009878 Delay at least 50 micro-seconds for external clock change valid. */
+ i = 1500U;
+ while (i--)
+ {
+ __NOP();
+ }
+ }
+
+ return kStatus_Success;
+}
+
+status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
+{
+ uint32_t mcgOutClkState = MCG_S_CLKST_VAL;
+ mcg_irc_mode_t curIrcs = (mcg_irc_mode_t)MCG_S_IRCST_VAL;
+ uint8_t curFcrdiv = MCG_SC_FCRDIV_VAL;
+
+#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
+ /* If MCGIRCLK is used as system clock source. */
+ if (kMCG_ClkOutStatInt == mcgOutClkState)
+ {
+ /* If need to change MCGIRCLK source or driver, return error. */
+ if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs))
+ {
+ return kStatus_MCG_SourceUsed;
+ }
+ }
+#endif
+
+ /* If need to update the FCRDIV. */
+ if (fcrdiv != curFcrdiv)
+ {
+ /* If fast IRC is in use currently, change to slow IRC. */
+ if ((kMCG_IrcFast == curIrcs) && ((mcgOutClkState == kMCG_ClkOutStatInt) || (MCG->C1 & MCG_C1_IRCLKEN_MASK)))
+ {
+ MCG->C2 = ((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow)));
+ while (MCG_S_IRCST_VAL != kMCG_IrcSlow)
+ {
+ }
+ }
+ /* Update FCRDIV. */
+ MCG->SC = (MCG->SC & ~(MCG_SC_FCRDIV_MASK | MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK)) | MCG_SC_FCRDIV(fcrdiv);
+ }
+
+ /* Set internal reference clock selection. */
+ MCG->C2 = (MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs));
+ MCG->C1 = (MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode;
+
+ /* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */
+ if ((mcgOutClkState == kMCG_ClkOutStatInt) || (enableMode & kMCG_IrclkEnable))
+ {
+ while (MCG_S_IRCST_VAL != ircs)
+ {
+ }
+ }
+
+ return kStatus_Success;
+}
+
+uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv)
+{
+ uint8_t ret_prdiv = FSL_FEATURE_MCG_PLL_PRDIV_BASE; /* PRDIV to return. */
+ uint8_t ret_vdiv = FSL_FEATURE_MCG_PLL_VDIV_BASE; /* VDIV to return. */
+ uint8_t prdiv_min; /* Min PRDIV value to make reference clock in allowed range. */
+ uint8_t prdiv_max; /* Max PRDIV value to make reference clock in allowed range. */
+ uint8_t prdiv_cur; /* PRDIV value for iteration. */
+ uint8_t vdiv_cur; /* VDIV value for iteration. */
+ uint32_t ret_freq = 0U; /* PLL output fequency to return. */
+ uint32_t diff = 0xFFFFFFFFU; /* Difference between desireFreq and return frequency. */
+ uint32_t ref_div; /* Reference frequency after PRDIV. */
+
+ /*
+ Steps:
+ 1. Get allowed prdiv with such rules:
+ 1). refFreq / prdiv >= FSL_FEATURE_MCG_PLL_REF_MIN.
+ 2). refFreq / prdiv <= FSL_FEATURE_MCG_PLL_REF_MAX.
+ 2. For each allowed prdiv, there are two candidate vdiv values:
+ 1). (desireFreq / (refFreq / prdiv)).
+ 2). (desireFreq / (refFreq / prdiv)) + 1.
+ If could get the precise desired frequency, return current prdiv and
+ vdiv directly. Otherwise choose the one which is closer to desired
+ frequency.
+ */
+
+ /* Reference frequency is out of range. */
+ if ((refFreq < FSL_FEATURE_MCG_PLL_REF_MIN) ||
+ (refFreq > (FSL_FEATURE_MCG_PLL_REF_MAX * (FSL_FEATURE_MCG_PLL_PRDIV_MAX + FSL_FEATURE_MCG_PLL_PRDIV_BASE))))
+ {
+ return 0U;
+ }
+
+ /* refFreq/PRDIV must in a range. First get the allowed PRDIV range. */
+ prdiv_max = refFreq / FSL_FEATURE_MCG_PLL_REF_MIN;
+ prdiv_min = (refFreq + FSL_FEATURE_MCG_PLL_REF_MAX - 1U) / FSL_FEATURE_MCG_PLL_REF_MAX;
+
+ desireFreq *= 2U;
+
+ /* PRDIV traversal. */
+ for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--)
+ {
+ /* Reference frequency after PRDIV. */
+ ref_div = refFreq / prdiv_cur;
+
+ vdiv_cur = desireFreq / ref_div;
+
+ if ((vdiv_cur < FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U) || (vdiv_cur > FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
+ {
+ /* No VDIV is available with this PRDIV. */
+ continue;
+ }
+
+ ret_freq = vdiv_cur * ref_div;
+
+ if (vdiv_cur >= FSL_FEATURE_MCG_PLL_VDIV_BASE)
+ {
+ if (ret_freq == desireFreq) /* If desire frequency is got. */
+ {
+ *prdiv = prdiv_cur - FSL_FEATURE_MCG_PLL_PRDIV_BASE;
+ *vdiv = vdiv_cur - FSL_FEATURE_MCG_PLL_VDIV_BASE;
+ return ret_freq / 2U;
+ }
+ /* New PRDIV/VDIV is closer. */
+ if (diff > desireFreq - ret_freq)
+ {
+ diff = desireFreq - ret_freq;
+ ret_prdiv = prdiv_cur;
+ ret_vdiv = vdiv_cur;
+ }
+ }
+ vdiv_cur++;
+ if (vdiv_cur <= (FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
+ {
+ ret_freq += ref_div;
+ /* New PRDIV/VDIV is closer. */
+ if (diff > ret_freq - desireFreq)
+ {
+ diff = ret_freq - desireFreq;
+ ret_prdiv = prdiv_cur;
+ ret_vdiv = vdiv_cur;
+ }
+ }
+ }
+
+ if (0xFFFFFFFFU != diff)
+ {
+ /* PRDIV/VDIV found. */
+ *prdiv = ret_prdiv - FSL_FEATURE_MCG_PLL_PRDIV_BASE;
+ *vdiv = ret_vdiv - FSL_FEATURE_MCG_PLL_VDIV_BASE;
+ ret_freq = (refFreq / ret_prdiv) * ret_vdiv;
+ return ret_freq / 2U;
+ }
+ else
+ {
+ /* No proper PRDIV/VDIV found. */
+ return 0U;
+ }
+}
+
+void CLOCK_EnablePll0(mcg_pll_config_t const *config)
+{
+ assert(config);
+
+ uint8_t mcg_c5 = 0U;
+
+ mcg_c5 |= MCG_C5_PRDIV0(config->prdiv);
+ MCG->C5 = mcg_c5; /* Disable the PLL first. */
+
+ MCG->C6 = (MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv);
+
+ /* Set enable mode. */
+ MCG->C5 |= ((uint32_t)kMCG_PllEnableIndependent | (uint32_t)config->enableMode);
+
+ /* Wait for PLL lock. */
+ while (!(MCG->S & MCG_S_LOCK0_MASK))
+ {
+ }
+}
+
+void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
+{
+ /* Clear the previous flag, MCG_SC[LOCS0]. */
+ MCG->SC &= ~MCG_SC_ATMF_MASK;
+
+ if (kMCG_MonitorNone == mode)
+ {
+ MCG->C6 &= ~MCG_C6_CME0_MASK;
+ }
+ else
+ {
+ if (kMCG_MonitorInt == mode)
+ {
+ MCG->C2 &= ~MCG_C2_LOCRE0_MASK;
+ }
+ else
+ {
+ MCG->C2 |= MCG_C2_LOCRE0_MASK;
+ }
+ MCG->C6 |= MCG_C6_CME0_MASK;
+ }
+}
+
+void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
+{
+ uint8_t mcg_c8 = MCG->C8;
+
+ mcg_c8 &= ~(MCG_C8_CME1_MASK | MCG_C8_LOCRE1_MASK);
+
+ if (kMCG_MonitorNone != mode)
+ {
+ if (kMCG_MonitorReset == mode)
+ {
+ mcg_c8 |= MCG_C8_LOCRE1_MASK;
+ }
+ mcg_c8 |= MCG_C8_CME1_MASK;
+ }
+ MCG->C8 = mcg_c8;
+}
+
+void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
+{
+ uint8_t mcg_c8;
+
+ /* Clear previous flag. */
+ MCG->S = MCG_S_LOLS0_MASK;
+
+ if (kMCG_MonitorNone == mode)
+ {
+ MCG->C6 &= ~MCG_C6_LOLIE0_MASK;
+ }
+ else
+ {
+ mcg_c8 = MCG->C8;
+
+ mcg_c8 &= ~MCG_C8_LOCS1_MASK;
+
+ if (kMCG_MonitorInt == mode)
+ {
+ mcg_c8 &= ~MCG_C8_LOLRE_MASK;
+ }
+ else
+ {
+ mcg_c8 |= MCG_C8_LOLRE_MASK;
+ }
+ MCG->C8 = mcg_c8;
+ MCG->C6 |= MCG_C6_LOLIE0_MASK;
+ }
+}
+
+void CLOCK_SetExtPllMonitorMode(mcg_monitor_mode_t mode)
+{
+ uint8_t mcg_c9 = MCG->C9;
+
+ mcg_c9 &= ~(MCG_C9_PLL_LOCRE_MASK | MCG_C9_PLL_CME_MASK);
+
+ if (kMCG_MonitorNone != mode)
+ {
+ if (kMCG_MonitorReset == mode)
+ {
+ mcg_c9 |= MCG_C9_PLL_LOCRE_MASK;
+ }
+ mcg_c9 |= MCG_C9_PLL_CME_MASK;
+ }
+ MCG->C9 = mcg_c9;
+}
+
+uint32_t CLOCK_GetStatusFlags(void)
+{
+ uint32_t ret = 0U;
+ uint8_t mcg_s = MCG->S;
+
+ if (MCG->SC & MCG_SC_LOCS0_MASK)
+ {
+ ret |= kMCG_Osc0LostFlag;
+ }
+ if (mcg_s & MCG_S_OSCINIT0_MASK)
+ {
+ ret |= kMCG_Osc0InitFlag;
+ }
+ if (MCG->C8 & MCG_C8_LOCS1_MASK)
+ {
+ ret |= kMCG_RtcOscLostFlag;
+ }
+ if (mcg_s & MCG_S_LOLS0_MASK)
+ {
+ ret |= kMCG_Pll0LostFlag;
+ }
+ if (mcg_s & MCG_S_LOCK0_MASK)
+ {
+ ret |= kMCG_Pll0LockFlag;
+ }
+ if (MCG->C9 & MCG_C9_EXT_PLL_LOCS_MASK)
+ {
+ ret |= kMCG_ExtPllLostFlag;
+ }
+ return ret;
+}
+
+void CLOCK_ClearStatusFlags(uint32_t mask)
+{
+ uint8_t reg;
+
+ if (mask & kMCG_Osc0LostFlag)
+ {
+ MCG->SC &= ~MCG_SC_ATMF_MASK;
+ }
+ if (mask & kMCG_RtcOscLostFlag)
+ {
+ reg = MCG->C8;
+ MCG->C8 = reg;
+ }
+ if (mask & kMCG_Pll0LostFlag)
+ {
+ MCG->S = MCG_S_LOLS0_MASK;
+ }
+ if (mask & kMCG_ExtPllLostFlag)
+ {
+ reg = MCG->C9;
+ MCG->C9 = reg;
+ }
+}
+
+void CLOCK_InitOsc0(osc_config_t const *config)
+{
+ uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq);
+
+ OSC_SetCapLoad(OSC0, config->capLoad);
+ OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig);
+
+ MCG->C2 = ((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode);
+
+ if ((kOSC_ModeExt != config->workMode) && (OSC0->CR & OSC_CR_ERCLKEN_MASK))
+ {
+ /* Wait for stable. */
+ while (!(MCG->S & MCG_S_OSCINIT0_MASK))
+ {
+ }
+ }
+}
+
+void CLOCK_DeinitOsc0(void)
+{
+ OSC0->CR = 0U;
+ MCG->C2 &= ~OSC_MODE_MASK;
+}
+
+status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
+{
+ uint32_t multi; /* extFreq / desireFreq */
+ uint32_t actv; /* Auto trim value. */
+ uint8_t mcg_sc;
+
+ static const uint32_t trimRange[2][2] = {
+ /* Min Max */
+ {TRIM_SIRC_MIN, TRIM_SIRC_MAX}, /* Slow IRC. */
+ {TRIM_FIRC_MIN, TRIM_FIRC_MAX} /* Fast IRC. */
+ };
+
+ if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN))
+ {
+ return kStatus_MCG_AtmBusClockInvalid;
+ }
+
+ /* Check desired frequency range. */
+ if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1]))
+ {
+ return kStatus_MCG_AtmDesiredFreqInvalid;
+ }
+
+ /*
+ Make sure internal reference clock is not used to generate bus clock.
+ Here only need to check (MCG_S_IREFST == 1).
+ */
+ if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK))
+ {
+ return kStatus_MCG_AtmIrcUsed;
+ }
+
+ multi = extFreq / desireFreq;
+ actv = multi * 21U;
+
+ if (kMCG_AtmSel4m == atms)
+ {
+ actv *= 128U;
+ }
+
+ /* Now begin to start trim. */
+ MCG->ATCVL = (uint8_t)actv;
+ MCG->ATCVH = (uint8_t)(actv >> 8U);
+
+ mcg_sc = MCG->SC;
+ mcg_sc &= ~(MCG_SC_ATMS_MASK | MCG_SC_LOCS0_MASK);
+ mcg_sc |= (MCG_SC_ATMF_MASK | MCG_SC_ATMS(atms));
+ MCG->SC = (mcg_sc | MCG_SC_ATME_MASK);
+
+ /* Wait for finished. */
+ while (MCG->SC & MCG_SC_ATME_MASK)
+ {
+ }
+
+ /* Error occurs? */
+ if (MCG->SC & MCG_SC_ATMF_MASK)
+ {
+ /* Clear the failed flag. */
+ MCG->SC = mcg_sc;
+ return kStatus_MCG_AtmHardwareFail;
+ }
+
+ *actualFreq = extFreq / multi;
+
+ if (kMCG_AtmSel4m == atms)
+ {
+ s_fastIrcFreq = *actualFreq;
+ }
+ else
+ {
+ s_slowIrcFreq = *actualFreq;
+ }
+
+ return kStatus_Success;
+}
+
+mcg_mode_t CLOCK_GetMode(void)
+{
+ mcg_mode_t mode = kMCG_ModeError;
+ uint32_t clkst = MCG_S_CLKST_VAL;
+ uint32_t irefst = MCG_S_IREFST_VAL;
+ uint32_t lp = MCG_C2_LP_VAL;
+ uint32_t pllst = MCG_S_PLLST_VAL;
+
+ /*------------------------------------------------------------------
+ Mode and Registers
+ ____________________________________________________________________
+
+ Mode | CLKST | IREFST | PLLST | LP
+ ____________________________________________________________________
+
+ FEI | 00(FLL) | 1(INT) | 0(FLL) | X
+ ____________________________________________________________________
+
+ FEE | 00(FLL) | 0(EXT) | 0(FLL) | X
+ ____________________________________________________________________
+
+ FBE | 10(EXT) | 0(EXT) | 0(FLL) | 0(NORMAL)
+ ____________________________________________________________________
+
+ FBI | 01(INT) | 1(INT) | 0(FLL) | 0(NORMAL)
+ ____________________________________________________________________
+
+ BLPI | 01(INT) | 1(INT) | 0(FLL) | 1(LOW POWER)
+ ____________________________________________________________________
+
+ BLPE | 10(EXT) | 0(EXT) | X | 1(LOW POWER)
+ ____________________________________________________________________
+
+ PEE | 11(PLL) | 0(EXT) | 1(PLL) | X
+ ____________________________________________________________________
+
+ PBE | 10(EXT) | 0(EXT) | 1(PLL) | O(NORMAL)
+ ____________________________________________________________________
+
+ PBI | 01(INT) | 1(INT) | 1(PLL) | 0(NORMAL)
+ ____________________________________________________________________
+
+ PEI | 11(PLL) | 1(INT) | 1(PLL) | X
+ ____________________________________________________________________
+
+ ----------------------------------------------------------------------*/
+
+ switch (clkst)
+ {
+ case kMCG_ClkOutStatFll:
+ if (kMCG_FllSrcExternal == irefst)
+ {
+ mode = kMCG_ModeFEE;
+ }
+ else
+ {
+ mode = kMCG_ModeFEI;
+ }
+ break;
+ case kMCG_ClkOutStatInt:
+ if (lp)
+ {
+ mode = kMCG_ModeBLPI;
+ }
+ else
+ {
+ {
+ mode = kMCG_ModeFBI;
+ }
+ }
+ break;
+ case kMCG_ClkOutStatExt:
+ if (lp)
+ {
+ mode = kMCG_ModeBLPE;
+ }
+ else
+ {
+ if (kMCG_PllstPll == pllst)
+ {
+ mode = kMCG_ModePBE;
+ }
+ else
+ {
+ mode = kMCG_ModeFBE;
+ }
+ }
+ break;
+ case kMCG_ClkOutStatPll:
+ {
+ mode = kMCG_ModePEE;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return mode;
+}
+
+status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
+{
+ uint8_t mcg_c4;
+ bool change_drs = false;
+
+#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
+ mcg_mode_t mode = CLOCK_GetMode();
+ if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode)))
+ {
+ return kStatus_MCG_ModeUnreachable;
+ }
+#endif
+ mcg_c4 = MCG->C4;
+
+ /*
+ Errata: ERR007993
+ Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before
+ reference clock source changes, then reset to previous value after
+ reference clock changes.
+ */
+ if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
+ {
+ change_drs = true;
+ /* Change the LSB of DRST_DRS. */
+ MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
+ }
+
+ /* Set CLKS and IREFS. */
+ MCG->C1 =
+ ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */
+ | MCG_C1_IREFS(kMCG_FllSrcInternal)); /* IREFS = 1 */
+
+ /* Wait and check status. */
+ while (kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
+ {
+ }
+
+ /* Errata: ERR007993 */
+ if (change_drs)
+ {
+ MCG->C4 = mcg_c4;
+ }
+
+ /* In FEI mode, the MCG_C4[DMX32] is set to 0U. */
+ MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs));
+
+ /* Check MCG_S[CLKST] */
+ while (kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
+ {
+ }
+
+ /* Wait for FLL stable time. */
+ if (fllStableDelay)
+ {
+ fllStableDelay();
+ }
+
+ return kStatus_Success;
+}
+
+status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
+{
+ uint8_t mcg_c4;
+ bool change_drs = false;
+
+#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
+ mcg_mode_t mode = CLOCK_GetMode();
+ if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode)))
+ {
+ return kStatus_MCG_ModeUnreachable;
+ }
+#endif
+ mcg_c4 = MCG->C4;
+
+ /*
+ Errata: ERR007993
+ Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before
+ reference clock source changes, then reset to previous value after
+ reference clock changes.
+ */
+ if (kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
+ {
+ change_drs = true;
+ /* Change the LSB of DRST_DRS. */
+ MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
+ }
+
+ /* Set CLKS and IREFS. */
+ MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) |
+ (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */
+ | MCG_C1_FRDIV(frdiv) /* FRDIV */
+ | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
+
+ /* Wait and check status. */
+ while (kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
+ {
+ }
+
+ /* Errata: ERR007993 */
+ if (change_drs)
+ {
+ MCG->C4 = mcg_c4;
+ }
+
+ /* Set DRS and DMX32. */
+ mcg_c4 = ((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
+ MCG->C4 = mcg_c4;
+
+ /* Wait for DRST_DRS update. */
+ while (MCG->C4 != mcg_c4)
+ {
+ }
+
+ /* Check MCG_S[CLKST] */
+ while (kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
+ {
+ }
+
+ /* Wait for FLL stable time. */
+ if (fllStableDelay)
+ {
+ fllStableDelay();
+ }
+
+ return kStatus_Success;
+}
+
+status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
+{
+ uint8_t mcg_c4;
+ bool change_drs = false;
+
+#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
+ mcg_mode_t mode = CLOCK_GetMode();
+
+ if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
+ (kMCG_ModeBLPI == mode)))
+
+ {
+ return kStatus_MCG_ModeUnreachable;
+ }
+#endif
+
+ mcg_c4 = MCG->C4;
+
+ MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */
+
+ /*
+ Errata: ERR007993
+ Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before
+ reference clock source changes, then reset to previous value after
+ reference clock changes.
+ */
+ if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
+ {
+ change_drs = true;
+ /* Change the LSB of DRST_DRS. */
+ MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
+ }
+
+ /* Set CLKS and IREFS. */
+ MCG->C1 =
+ ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* CLKS = 1 */
+ | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
+
+ /* Wait and check status. */
+ while (kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
+ {
+ }
+
+ /* Errata: ERR007993 */
+ if (change_drs)
+ {
+ MCG->C4 = mcg_c4;
+ }
+
+ while (kMCG_ClkOutStatInt != MCG_S_CLKST_VAL)
+ {
+ }
+
+ MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs));
+
+ /* Wait for FLL stable time. */
+ if (fllStableDelay)
+ {
+ fllStableDelay();
+ }
+
+ return kStatus_Success;
+}
+
+status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
+{
+ uint8_t mcg_c4;
+ bool change_drs = false;
+
+#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
+ mcg_mode_t mode = CLOCK_GetMode();
+ if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
+ (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode)))
+ {
+ return kStatus_MCG_ModeUnreachable;
+ }
+#endif
+
+ /* Change to FLL mode. */
+ MCG->C6 &= ~MCG_C6_PLLS_MASK;
+ while (MCG->S & MCG_S_PLLST_MASK)
+ {
+ }
+
+ /* Set LP bit to enable the FLL */
+ MCG->C2 &= ~MCG_C2_LP_MASK;
+
+ mcg_c4 = MCG->C4;
+
+ /*
+ Errata: ERR007993
+ Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before
+ reference clock source changes, then reset to previous value after
+ reference clock changes.
+ */
+ if (kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
+ {
+ change_drs = true;
+ /* Change the LSB of DRST_DRS. */
+ MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
+ }
+
+ /* Set CLKS and IREFS. */
+ MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) |
+ (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */
+ | MCG_C1_FRDIV(frdiv) /* FRDIV = frdiv */
+ | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
+
+ /* Wait for Reference clock Status bit to clear */
+ while (kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
+ {
+ }
+
+ /* Errata: ERR007993 */
+ if (change_drs)
+ {
+ MCG->C4 = mcg_c4;
+ }
+
+ /* Set DRST_DRS and DMX32. */
+ mcg_c4 = ((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
+
+ /* Wait for clock status bits to show clock source is ext ref clk */
+ while (kMCG_ClkOutStatExt != MCG_S_CLKST_VAL)
+ {
+ }
+
+ /* Wait for fll stable time. */
+ if (fllStableDelay)
+ {
+ fllStableDelay();
+ }
+
+ return kStatus_Success;
+}
+
+status_t CLOCK_SetBlpiMode(void)
+{
+#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
+ if (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt)
+ {
+ return kStatus_MCG_ModeUnreachable;
+ }
+#endif /* MCG_CONFIG_CHECK_PARAM */
+
+ /* Set LP. */
+ MCG->C2 |= MCG_C2_LP_MASK;
+
+ return kStatus_Success;
+}
+
+status_t CLOCK_SetBlpeMode(void)
+{
+#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
+ if (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt)
+ {
+ return kStatus_MCG_ModeUnreachable;
+ }
+#endif
+
+ /* Set LP bit to enter BLPE mode. */
+ MCG->C2 |= MCG_C2_LP_MASK;
+
+ return kStatus_Success;
+}
+
+status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
+{
+ /*
+ This function is designed to change MCG to PBE mode from PEE/BLPE/FBE,
+ but with this workflow, the source mode could be all modes except PEI/PBI.
+ */
+ MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */
+
+ /* Change to use external clock first. */
+ MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
+
+ /* Wait for CLKST clock status bits to show clock source is ext ref clk */
+ while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
+ (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
+ {
+ }
+
+ /* Disable PLL first, then configure PLL. */
+ MCG->C6 &= ~MCG_C6_PLLS_MASK;
+ while (MCG->S & MCG_S_PLLST_MASK)
+ {
+ }
+
+ /* Configure the PLL. */
+ if (kMCG_PllClkSelPll0 == pllcs)
+ {
+ CLOCK_EnablePll0(config);
+ }
+
+ MCG->C11 = ((MCG->C11 & ~MCG_C11_PLLCS_MASK)) | MCG_C11_PLLCS(pllcs);
+ while (pllcs != MCG_S2_PLLCST_VAL)
+ {
+ }
+
+ /* Change to PLL mode. */
+ MCG->C6 |= MCG_C6_PLLS_MASK;
+ while (!(MCG->S & MCG_S_PLLST_MASK))
+ {
+ }
+
+ return kStatus_Success;
+}
+
+status_t CLOCK_SetPeeMode(void)
+{
+#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
+ mcg_mode_t mode = CLOCK_GetMode();
+ if (kMCG_ModePBE != mode)
+ {
+ return kStatus_MCG_ModeUnreachable;
+ }
+#endif
+
+ /* Change to use PLL/FLL output clock first. */
+ MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut);
+
+ /* Wait for clock status bits to update */
+ while (MCG_S_CLKST_VAL != kMCG_ClkOutStatPll)
+ {
+ }
+
+ return kStatus_Success;
+}
+
+status_t CLOCK_ExternalModeToFbeModeQuick(void)
+{
+#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
+ if (MCG->S & MCG_S_IREFST_MASK)
+ {
+ return kStatus_MCG_ModeInvalid;
+ }
+#endif /* MCG_CONFIG_CHECK_PARAM */
+
+ /* Disable low power */
+ MCG->C2 &= ~MCG_C2_LP_MASK;
+
+ MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
+ while (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt)
+ {
+ }
+
+ /* Disable PLL. */
+ MCG->C6 &= ~MCG_C6_PLLS_MASK;
+ while (MCG->S & MCG_S_PLLST_MASK)
+ {
+ }
+
+ return kStatus_Success;
+}
+
+status_t CLOCK_InternalModeToFbiModeQuick(void)
+{
+#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
+ if (!(MCG->S & MCG_S_IREFST_MASK))
+ {
+ return kStatus_MCG_ModeInvalid;
+ }
+#endif
+
+ /* Disable low power */
+ MCG->C2 &= ~MCG_C2_LP_MASK;
+
+ MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
+ while (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt)
+ {
+ }
+
+ return kStatus_Success;
+}
+
+status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
+{
+ return CLOCK_SetFeiMode(dmx32, drs, fllStableDelay);
+}
+
+status_t CLOCK_BootToFeeMode(
+ mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
+{
+ CLOCK_SetExternalRefClkConfig(oscsel);
+
+ return CLOCK_SetFeeMode(frdiv, dmx32, drs, fllStableDelay);
+}
+
+status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode)
+{
+ /* If reset mode is FEI mode, set MCGIRCLK and always success. */
+ CLOCK_SetInternalRefClkConfig(ircEnableMode, ircs, fcrdiv);
+
+ /* If reset mode is not BLPI, first enter FBI mode. */
+ MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal);
+ while (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt)
+ {
+ }
+
+ /* Enter BLPI mode. */
+ MCG->C2 |= MCG_C2_LP_MASK;
+
+ return kStatus_Success;
+}
+
+status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
+{
+ CLOCK_SetExternalRefClkConfig(oscsel);
+
+ /* Set to FBE mode. */
+ MCG->C1 =
+ ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */
+ | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
+
+ /* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */
+ while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
+ (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
+ {
+ }
+
+ /* In FBE now, start to enter BLPE. */
+ MCG->C2 |= MCG_C2_LP_MASK;
+
+ return kStatus_Success;
+}
+
+status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
+{
+ assert(config);
+
+ CLOCK_SetExternalRefClkConfig(oscsel);
+
+ CLOCK_SetPbeMode(pllcs, config);
+
+ /* Change to use PLL output clock. */
+ MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut);
+ while (MCG_S_CLKST_VAL != kMCG_ClkOutStatPll)
+ {
+ }
+
+ return kStatus_Success;
+}
+
+/*
+ The transaction matrix. It defines the path for mode switch, the row is for
+ current mode and the column is target mode.
+ For example, switch from FEI to PEE:
+ 1. Current mode FEI, next mode is mcgModeMatrix[FEI][PEE] = FBE, so swith to FBE.
+ 2. Current mode FBE, next mode is mcgModeMatrix[FBE][PEE] = PBE, so swith to PBE.
+ 3. Current mode PBE, next mode is mcgModeMatrix[PBE][PEE] = PEE, so swith to PEE.
+ Thus the MCG mode has changed from FEI to PEE.
+ */
+static const mcg_mode_t mcgModeMatrix[8][8] = {
+ {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE,
+ kMCG_ModeFBE}, /* FEI */
+ {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeBLPI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE,
+ kMCG_ModeFBE}, /* FBI */
+ {kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeBLPI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFBI,
+ kMCG_ModeFBI}, /* BLPI */
+ {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE,
+ kMCG_ModeFBE}, /* FEE */
+ {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeBLPE, kMCG_ModePBE,
+ kMCG_ModePBE}, /* FBE */
+ {kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeBLPE, kMCG_ModePBE,
+ kMCG_ModePBE}, /* BLPE */
+ {kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeBLPE, kMCG_ModePBE,
+ kMCG_ModePEE}, /* PBE */
+ {kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE,
+ kMCG_ModePBE} /* PEE */
+ /* FEI FBI BLPI FEE FBE BLPE PBE PEE */
+};
+
+status_t CLOCK_SetMcgConfig(const mcg_config_t *config)
+{
+ mcg_mode_t next_mode;
+ status_t status = kStatus_Success;
+
+ mcg_pll_clk_select_t pllcs = config->pllcs;
+
+ /* If need to change external clock, MCG_C7[OSCSEL]. */
+ if (MCG_C7_OSCSEL_VAL != config->oscsel)
+ {
+ /* If external clock is in use, change to FEI first. */
+ if (!(MCG->S & MCG_S_IRCST_MASK))
+ {
+ CLOCK_ExternalModeToFbeModeQuick();
+ CLOCK_SetFeiMode(config->dmx32, config->drs, (void (*)(void))0);
+ }
+
+ CLOCK_SetExternalRefClkConfig(config->oscsel);
+ }
+
+ /* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */
+ if (MCG_S_CLKST_VAL == kMCG_ClkOutStatInt)
+ {
+ MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */
+
+ {
+ CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
+ }
+ }
+
+ /* Configure MCGIRCLK. */
+ CLOCK_SetInternalRefClkConfig(config->irclkEnableMode, config->ircs, config->fcrdiv);
+
+ next_mode = CLOCK_GetMode();
+
+ do
+ {
+ next_mode = mcgModeMatrix[next_mode][config->mcgMode];
+
+ switch (next_mode)
+ {
+ case kMCG_ModeFEI:
+ status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
+ break;
+ case kMCG_ModeFEE:
+ status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
+ break;
+ case kMCG_ModeFBI:
+ status = CLOCK_SetFbiMode(config->dmx32, config->drs, (void (*)(void))0);
+ break;
+ case kMCG_ModeFBE:
+ status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, (void (*)(void))0);
+ break;
+ case kMCG_ModeBLPI:
+ status = CLOCK_SetBlpiMode();
+ break;
+ case kMCG_ModeBLPE:
+ status = CLOCK_SetBlpeMode();
+ break;
+ case kMCG_ModePBE:
+ /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */
+ if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode))
+ {
+ if (kMCG_PllClkSelPll0 == pllcs)
+ {
+ status = CLOCK_SetPbeMode(pllcs, &config->pll0Config);
+ }
+ else if (kMCG_PllClkSelExtPll == pllcs)
+ {
+ status = CLOCK_SetPbeMode(pllcs, NULL);
+ }
+ else
+ {
+ }
+ }
+ else
+ {
+ MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
+ while (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt)
+ {
+ }
+ }
+ break;
+ case kMCG_ModePEE:
+ status = CLOCK_SetPeeMode();
+ break;
+ default:
+ break;
+ }
+ if (kStatus_Success != status)
+ {
+ return status;
+ }
+ } while (next_mode != config->mcgMode);
+
+ if (config->pll0Config.enableMode & kMCG_PllEnableIndependent)
+ {
+ CLOCK_EnablePll0(&config->pll0Config);
+ }
+ else
+ {
+ MCG->C5 &= ~(uint32_t)kMCG_PllEnableIndependent;
+ }
+ return kStatus_Success;
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/MK26F18/fsl_clock.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/MK26F18/fsl_clock.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1616 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_CLOCK_H_
+#define _FSL_CLOCK_H_
+
+#include "fsl_device_registers.h"
+#include "fsl_common.h"
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+
+/*! @addtogroup clock */
+/*! @{ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief CLOCK driver version 2.2.0. */
+#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
+/*@}*/
+
+/*! @brief External XTAL0 (OSC0) clock frequency.
+ *
+ * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz, when the clock is setup, use the
+ * function CLOCK_SetXtal0Freq to set the value in to clock driver. For example,
+ * if XTAL0 is 8MHz,
+ * @code
+ * CLOCK_InitOsc0(...); // Setup the OSC0
+ * CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value to clock driver.
+ * @endcode
+ *
+ * This is important for the multicore platforms, only one core needs to setup
+ * OSC0 using CLOCK_InitOsc0, all other cores need to call CLOCK_SetXtal0Freq
+ * to get valid clock frequency.
+ */
+extern uint32_t g_xtal0Freq;
+
+/*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
+ *
+ * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz, when the clock is setup, use the
+ * function CLOCK_SetXtal32Freq to set the value in to clock driver.
+ *
+ * This is important for the multicore platforms, only one core needs to setup
+ * the clock, all other cores need to call CLOCK_SetXtal32Freq
+ * to get valid clock frequency.
+ */
+extern uint32_t g_xtal32Freq;
+
+/*! @brief IRC48M clock frequency in Hz. */
+#define MCG_INTERNAL_IRC_48M 48000000U
+
+#if (defined(OSC) && !(defined(OSC0)))
+#define OSC0 OSC
+#endif
+
+/*! @brief Clock ip name array for DMAMUX. */
+#define DMAMUX_CLOCKS \
+ { \
+ kCLOCK_Dmamux0 \
+ }
+
+/*! @brief Clock ip name array for RTC. */
+#define RTC_CLOCKS \
+ { \
+ kCLOCK_Rtc0 \
+ }
+
+/*! @brief Clock ip name array for PORT. */
+#define PORT_CLOCKS \
+ { \
+ kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
+ }
+
+/*! @brief Clock ip name array for SAI. */
+#define SAI_CLOCKS \
+ { \
+ kCLOCK_Sai0 \
+ }
+
+/*! @brief Clock ip name array for FLEXBUS. */
+#define FLEXBUS_CLOCKS \
+ { \
+ kCLOCK_Flexbus0 \
+ }
+
+/*! @brief Clock ip name array for TSI. */
+#define TSI_CLOCKS \
+ { \
+ kCLOCK_Tsi0 \
+ }
+
+/*! @brief Clock ip name array for LPUART. */
+#define LPUART_CLOCKS \
+ { \
+ kCLOCK_Lpuart0 \
+ }
+
+/*! @brief Clock ip name array for EWM. */
+#define EWM_CLOCKS \
+ { \
+ kCLOCK_Ewm0 \
+ }
+
+/*! @brief Clock ip name array for PIT. */
+#define PIT_CLOCKS \
+ { \
+ kCLOCK_Pit0 \
+ }
+
+/*! @brief Clock ip name array for DSPI. */
+#define DSPI_CLOCKS \
+ { \
+ kCLOCK_Spi0, kCLOCK_Spi1, kCLOCK_Spi2 \
+ }
+
+/*! @brief Clock ip name array for LPTMR. */
+#define LPTMR_CLOCKS \
+ { \
+ kCLOCK_Lptmr0 \
+ }
+
+/*! @brief Clock ip name array for SDHC. */
+#define SDHC_CLOCKS \
+ { \
+ kCLOCK_Sdhc0 \
+ }
+
+/*! @brief Clock ip name array for FTM. */
+#define FTM_CLOCKS \
+ { \
+ kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2, kCLOCK_Ftm3 \
+ }
+
+/*! @brief Clock ip name array for EDMA. */
+#define EDMA_CLOCKS \
+ { \
+ kCLOCK_Dma0 \
+ }
+
+/*! @brief Clock ip name array for FLEXCAN. */
+#define FLEXCAN_CLOCKS \
+ { \
+ kCLOCK_Flexcan0, kCLOCK_Flexcan1 \
+ }
+
+/*! @brief Clock ip name array for DAC. */
+#define DAC_CLOCKS \
+ { \
+ kCLOCK_Dac0, kCLOCK_Dac1 \
+ }
+
+/*! @brief Clock ip name array for ADC16. */
+#define ADC16_CLOCKS \
+ { \
+ kCLOCK_Adc0, kCLOCK_Adc1 \
+ }
+
+/*! @brief Clock ip name array for SDRAM. */
+#define SDRAM_CLOCKS \
+ { \
+ kCLOCK_Sdramc0 \
+ }
+
+/*! @brief Clock ip name array for MPU. */
+#define MPU_CLOCKS \
+ { \
+ kCLOCK_Mpu0 \
+ }
+
+/*! @brief Clock ip name array for VREF. */
+#define VREF_CLOCKS \
+ { \
+ kCLOCK_Vref0 \
+ }
+
+/*! @brief Clock ip name array for CMT. */
+#define CMT_CLOCKS \
+ { \
+ kCLOCK_Cmt0 \
+ }
+
+/*! @brief Clock ip name array for UART. */
+#define UART_CLOCKS \
+ { \
+ kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4 \
+ }
+
+/*! @brief Clock ip name array for TPM. */
+#define TPM_CLOCKS \
+ { \
+ kCLOCK_IpInvalid, kCLOCK_Tpm1, kCLOCK_Tpm2 \
+ }
+
+/*! @brief Clock ip name array for RNGA. */
+#define RNGA_CLOCKS \
+ { \
+ kCLOCK_Rnga0 \
+ }
+
+/*! @brief Clock ip name array for CRC. */
+#define CRC_CLOCKS \
+ { \
+ kCLOCK_Crc0 \
+ }
+
+/*! @brief Clock ip name array for I2C. */
+#define I2C_CLOCKS \
+ { \
+ kCLOCK_I2c0, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3 \
+ }
+
+/*! @brief Clock ip name array for FTF. */
+#define FTF_CLOCKS \
+ { \
+ kCLOCK_Ftf0 \
+ }
+
+/*! @brief Clock ip name array for PDB. */
+#define PDB_CLOCKS \
+ { \
+ kCLOCK_Pdb0 \
+ }
+
+/*! @brief Clock ip name array for CMP. */
+#define CMP_CLOCKS \
+ { \
+ kCLOCK_Cmp0, kCLOCK_Cmp1, kCLOCK_Cmp2, kCLOCK_Cmp3 \
+ }
+
+/*!
+ * @brief LPO clock frequency.
+ */
+#define LPO_CLK_FREQ 1000U
+
+/*! @brief Peripherals clock source definition. */
+#define SYS_CLK kCLOCK_CoreSysClk
+#define BUS_CLK kCLOCK_BusClk
+
+#define I2C0_CLK_SRC BUS_CLK
+#define I2C1_CLK_SRC BUS_CLK
+#define I2C2_CLK_SRC BUS_CLK
+#define I2C3_CLK_SRC BUS_CLK
+#define DSPI0_CLK_SRC BUS_CLK
+#define DSPI1_CLK_SRC BUS_CLK
+#define DSPI2_CLK_SRC BUS_CLK
+#define UART0_CLK_SRC SYS_CLK
+#define UART1_CLK_SRC SYS_CLK
+#define UART2_CLK_SRC BUS_CLK
+#define UART3_CLK_SRC BUS_CLK
+#define UART4_CLK_SRC BUS_CLK
+
+/*! @brief Clock name used to get clock frequency. */
+typedef enum _clock_name
+{
+
+ /* ----------------------------- System layer clock -------------------------------*/
+ kCLOCK_CoreSysClk, /*!< Core/system clock */
+ kCLOCK_PlatClk, /*!< Platform clock */
+ kCLOCK_BusClk, /*!< Bus clock */
+ kCLOCK_FlexBusClk, /*!< FlexBus clock */
+ kCLOCK_FlashClk, /*!< Flash clock */
+ kCLOCK_FastPeriphClk, /*!< Fast peripheral clock */
+ kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */
+
+ /* ---------------------------------- OSC clock -----------------------------------*/
+ kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */
+ kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */
+ kCLOCK_Osc1ErClk, /*!< OSC1 external reference clock (OSC1ERCLK) */
+ kCLOCK_Osc0ErClkUndiv, /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */
+
+ /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
+ kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */
+ kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */
+ kCLOCK_McgFllClk, /*!< MCGFLLCLK */
+ kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */
+ kCLOCK_McgPll1Clk, /*!< MCGPLL1CLK */
+ kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */
+ kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */
+ kCLOCK_McgIrc48MClk, /*!< MCG IRC48M clock */
+
+ /* --------------------------------- Other clock ----------------------------------*/
+ kCLOCK_LpoClk, /*!< LPO clock */
+
+} clock_name_t;
+
+/*! @brief USB clock source definition. */
+typedef enum _clock_usb_src
+{
+ kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(1U), /*!< Use PLL0. */
+ kCLOCK_UsbSrcUsbPfd = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(2U), /*!< Use USBPFDCLK. */
+ kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(3U), /*!< Use IRC48M. */
+ kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U) /*!< Use USB_CLKIN. */
+} clock_usb_src_t;
+
+/*------------------------------------------------------------------------------
+
+ clock_gate_t definition:
+
+ 31 16 0
+ -----------------------------------------------------------------
+ | SIM_SCGC register offset | control bit offset in SCGC |
+ -----------------------------------------------------------------
+
+ For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
+ SIM_SCGC3 offset in SIM is 0x1030, then kClockGateSdhc0 is defined as
+
+ kClockGateSdhc0 = (0x1030 << 16) | 17;
+
+------------------------------------------------------------------------------*/
+
+#define CLK_GATE_REG_OFFSET_SHIFT 16U
+#define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
+#define CLK_GATE_BIT_SHIFT_SHIFT 0U
+#define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
+
+#define CLK_GATE_DEFINE(reg_offset, bit_shift) \
+ ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
+ (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
+
+#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
+#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
+
+/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
+typedef enum _clock_ip_name
+{
+ kCLOCK_IpInvalid = 0U,
+ kCLOCK_I2c2 = CLK_GATE_DEFINE(0x1028U, 6U),
+ kCLOCK_I2c3 = CLK_GATE_DEFINE(0x1028U, 7U),
+ kCLOCK_Uart4 = CLK_GATE_DEFINE(0x1028U, 10U),
+
+ kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x102CU, 4U),
+ kCLOCK_Tpm1 = CLK_GATE_DEFINE(0x102CU, 9U),
+ kCLOCK_Tpm2 = CLK_GATE_DEFINE(0x102CU, 10U),
+ kCLOCK_Dac0 = CLK_GATE_DEFINE(0x102CU, 12U),
+ kCLOCK_Dac1 = CLK_GATE_DEFINE(0x102CU, 13U),
+
+ kCLOCK_Rnga0 = CLK_GATE_DEFINE(0x1030U, 0U),
+ kCLOCK_Usbhs0 = CLK_GATE_DEFINE(0x1030U, 1U),
+ kCLOCK_UsbhsPhy0 = CLK_GATE_DEFINE(0x1030U, 2U),
+ kCLOCK_UsbhsDcd0 = CLK_GATE_DEFINE(0x1030U, 3U),
+ kCLOCK_Flexcan1 = CLK_GATE_DEFINE(0x1030U, 4U),
+ kCLOCK_Spi2 = CLK_GATE_DEFINE(0x1030U, 12U),
+ kCLOCK_Sdhc0 = CLK_GATE_DEFINE(0x1030U, 17U),
+ kCLOCK_Ftm3 = CLK_GATE_DEFINE(0x1030U, 25U),
+ kCLOCK_Adc1 = CLK_GATE_DEFINE(0x1030U, 27U),
+
+ kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U),
+ kCLOCK_Cmt0 = CLK_GATE_DEFINE(0x1034U, 2U),
+ kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U),
+ kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U),
+ kCLOCK_Uart0 = CLK_GATE_DEFINE(0x1034U, 10U),
+ kCLOCK_Uart1 = CLK_GATE_DEFINE(0x1034U, 11U),
+ kCLOCK_Uart2 = CLK_GATE_DEFINE(0x1034U, 12U),
+ kCLOCK_Uart3 = CLK_GATE_DEFINE(0x1034U, 13U),
+ kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U),
+ kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
+ kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U),
+ kCLOCK_Cmp2 = CLK_GATE_DEFINE(0x1034U, 19U),
+ kCLOCK_Cmp3 = CLK_GATE_DEFINE(0x1034U, 19U),
+ kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U),
+
+ kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
+ kCLOCK_Tsi0 = CLK_GATE_DEFINE(0x1038U, 5U),
+ kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U),
+ kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U),
+ kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U),
+ kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U),
+ kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U),
+
+ kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U),
+ kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
+ kCLOCK_Flexcan0 = CLK_GATE_DEFINE(0x103CU, 4U),
+ kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U),
+ kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U),
+ kCLOCK_Sai0 = CLK_GATE_DEFINE(0x103CU, 15U),
+ kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U),
+ kCLOCK_Usbdcd0 = CLK_GATE_DEFINE(0x103CU, 21U),
+ kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U),
+ kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U),
+ kCLOCK_Ftm0 = CLK_GATE_DEFINE(0x103CU, 24U),
+ kCLOCK_Ftm1 = CLK_GATE_DEFINE(0x103CU, 25U),
+ kCLOCK_Ftm2 = CLK_GATE_DEFINE(0x103CU, 26U),
+ kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U),
+ kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U),
+
+ kCLOCK_Flexbus0 = CLK_GATE_DEFINE(0x1040U, 0U),
+ kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U),
+ kCLOCK_Mpu0 = CLK_GATE_DEFINE(0x1040U, 2U),
+ kCLOCK_Sdramc0 = CLK_GATE_DEFINE(0x1040U, 3U),
+} clock_ip_name_t;
+
+/*!@brief SIM configuration structure for clock setting. */
+typedef struct _sim_clock_config
+{
+ uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */
+ uint8_t pllFllDiv; /*!< PLLFLLSEL clock divider divisor. */
+ uint8_t pllFllFrac; /*!< PLLFLLSEL clock divider fraction. */
+ uint8_t er32kSrc; /*!< ERCLK32K source selection. */
+ uint32_t clkdiv1; /*!< SIM_CLKDIV1. */
+} sim_clock_config_t;
+
+/*! @brief OSC work mode. */
+typedef enum _osc_mode
+{
+ kOSC_ModeExt = 0U, /*!< Use external clock. */
+#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
+ kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */
+#else
+ kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */
+#endif
+ kOSC_ModeOscHighGain = 0U
+#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
+ |
+ MCG_C2_EREFS_MASK
+#else
+ |
+ MCG_C2_EREFS0_MASK
+#endif
+#if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
+ |
+ MCG_C2_HGO_MASK, /*!< Oscillator high gain. */
+#else
+ |
+ MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */
+#endif
+} osc_mode_t;
+
+/*! @brief Oscillator capacitor load setting.*/
+enum _osc_cap_load
+{
+ kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */
+ kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */
+ kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */
+ kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */
+};
+
+/*! @brief OSCERCLK enable mode. */
+enum _oscer_enable_mode
+{
+ kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */
+ kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */
+};
+
+/*! @brief OSC configuration for OSCERCLK. */
+typedef struct _oscer_config
+{
+ uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */
+
+ uint8_t erclkDiv; /*!< Divider for OSCERCLK.*/
+} oscer_config_t;
+
+/*!
+ * @brief OSC Initialization Configuration Structure
+ *
+ * Defines the configuration data structure to initialize the OSC.
+ * When porting to a new board, please set the following members
+ * according to board setting:
+ * 1. freq: The external frequency.
+ * 2. workMode: The OSC module mode.
+ */
+typedef struct _osc_config
+{
+ uint32_t freq; /*!< External clock frequency. */
+ uint8_t capLoad; /*!< Capacitor load setting. */
+ osc_mode_t workMode; /*!< OSC work mode setting. */
+ oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */
+} osc_config_t;
+
+/*! @brief MCG FLL reference clock source select. */
+typedef enum _mcg_fll_src
+{
+ kMCG_FllSrcExternal, /*!< External reference clock is selected */
+ kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */
+} mcg_fll_src_t;
+
+/*! @brief MCG internal reference clock select */
+typedef enum _mcg_irc_mode
+{
+ kMCG_IrcSlow, /*!< Slow internal reference clock selected */
+ kMCG_IrcFast /*!< Fast internal reference clock selected */
+} mcg_irc_mode_t;
+
+/*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */
+typedef enum _mcg_dmx32
+{
+ kMCG_Dmx32Default, /*!< DCO has a default range of 25% */
+ kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
+} mcg_dmx32_t;
+
+/*! @brief MCG DCO range select */
+typedef enum _mcg_drs
+{
+ kMCG_DrsLow, /*!< Low frequency range */
+ kMCG_DrsMid, /*!< Mid frequency range */
+ kMCG_DrsMidHigh, /*!< Mid-High frequency range */
+ kMCG_DrsHigh /*!< High frequency range */
+} mcg_drs_t;
+
+/*! @brief MCG PLL reference clock select */
+typedef enum _mcg_pll_ref_src
+{
+ kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */
+ kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */
+} mcg_pll_ref_src_t;
+
+/*! @brief MCGOUT clock source. */
+typedef enum _mcg_clkout_src
+{
+ kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */
+ kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */
+ kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */
+} mcg_clkout_src_t;
+
+/*! @brief MCG Automatic Trim Machine Select */
+typedef enum _mcg_atm_select
+{
+ kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */
+ kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */
+} mcg_atm_select_t;
+
+/*! @brief MCG OSC Clock Select */
+typedef enum _mcg_oscsel
+{
+ kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */
+ kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */
+ kMCG_OscselIrc /*!< Selects 48 MHz IRC Oscillator */
+} mcg_oscsel_t;
+
+/*! @brief MCG PLLCS select */
+typedef enum _mcg_pll_clk_select
+{
+ kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */
+ kMCG_PllClkSelExtPll /* External PLL clock is selected */
+} mcg_pll_clk_select_t;
+
+/*! @brief MCG clock monitor mode. */
+typedef enum _mcg_monitor_mode
+{
+ kMCG_MonitorNone, /*!< Clock monitor is disabled. */
+ kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */
+ kMCG_MonitorReset /*!< System reset when clock lost. */
+} mcg_monitor_mode_t;
+
+/*! @brief MCG status. */
+enum _mcg_status
+{
+ kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0), /*!< Can't switch to target mode. */
+ kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1), /*!< Current mode invalid for the specific
+ function. */
+ kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2), /*!< Invalid bus clock for ATM. */
+ kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3), /*!< Invalid desired frequency for ATM. */
+ kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4), /*!< IRC is used when using ATM. */
+ kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5), /*!< Hardware fail occurs during ATM. */
+ kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6) /*!< Could not change clock source because
+ it is used currently. */
+};
+
+/*! @brief MCG status flags. */
+enum _mcg_status_flags_t
+{
+ kMCG_Osc0LostFlag = (1U << 0U), /*!< OSC0 lost. */
+ kMCG_Osc0InitFlag = (1U << 1U), /*!< OSC0 crystal initialized. */
+ kMCG_RtcOscLostFlag = (1U << 4U), /*!< RTC OSC lost. */
+ kMCG_Pll0LostFlag = (1U << 5U), /*!< PLL0 lost. */
+ kMCG_Pll0LockFlag = (1U << 6U), /*!< PLL0 locked. */
+ kMCG_ExtPllLostFlag = (1U << 9U), /*!< External PLL lost. */
+};
+
+/*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */
+enum _mcg_irclk_enable_mode
+{
+ kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */
+ kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */
+};
+
+/*! @brief MCG PLL clock enable mode definition. */
+enum _mcg_pll_enable_mode
+{
+ kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable indepencent of
+ MCG clock mode. Generally, PLL
+ is disabled in FLL modes
+ (FEI/FBI/FEE/FBE), set PLL clock
+ enable independent will enable
+ PLL in the FLL modes. */
+ kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */
+};
+
+/*! @brief MCG mode definitions */
+typedef enum _mcg_mode
+{
+ kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */
+ kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */
+ kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */
+ kMCG_ModeFEE, /*!< FEE - FLL Engaged External */
+ kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */
+ kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */
+ kMCG_ModePBE, /*!< PBE - PLL Bypassed External */
+ kMCG_ModePEE, /*!< PEE - PLL Engaged External */
+ kMCG_ModeError /*!< Unknown mode */
+} mcg_mode_t;
+
+/*! @brief MCG PLL configuration. */
+typedef struct _mcg_pll_config
+{
+ uint8_t enableMode; /*!< Enable mode. OR'ed value of @ref _mcg_pll_enable_mode. */
+ uint8_t prdiv; /*!< Reference divider PRDIV. */
+ uint8_t vdiv; /*!< VCO divider VDIV. */
+} mcg_pll_config_t;
+
+/*! @brief MCG configure structure for mode change.
+ *
+ * When porting to a new board, please set the following members
+ * according to board setting:
+ * 1. frdiv: If FLL uses the external reference clock, please set this
+ * value to make sure external reference clock divided by frdiv is
+ * in the range 31.25kHz to 39.0625kHz.
+ * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
+ * PRDIV should be in the range of FSL_FEATURE_MCG_PLL_REF_MIN to
+ * FSL_FEATURE_MCG_PLL_REF_MAX.
+ */
+typedef struct _mcg_config
+{
+ mcg_mode_t mcgMode; /*!< MCG mode. */
+
+ /* ----------------------- MCGIRCCLK settings ------------------------ */
+ uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */
+ mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */
+ uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */
+
+ /* ------------------------ MCG FLL settings ------------------------- */
+ uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */
+ mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */
+ mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */
+ mcg_oscsel_t oscsel; /*!< OSC select MCG_C7[OSCSEL]. */
+
+ /* ------------------------ MCG PLL settings ------------------------- */
+ mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
+
+ mcg_pll_clk_select_t pllcs; /*!< PLL select as output, PLLCS.*/
+
+} mcg_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @brief Enable the clock for specific IP.
+ *
+ * @param name Which clock to enable, see \ref clock_ip_name_t.
+ */
+static inline void CLOCK_EnableClock(clock_ip_name_t name)
+{
+ uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
+ (*(volatile uint32_t *)regAddr) |= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
+}
+
+/*!
+ * @brief Disable the clock for specific IP.
+ *
+ * @param name Which clock to disable, see \ref clock_ip_name_t.
+ */
+static inline void CLOCK_DisableClock(clock_ip_name_t name)
+{
+ uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
+ (*(volatile uint32_t *)regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
+}
+
+/*!
+ * @brief Set ERCLK32K source.
+ *
+ * @param src The value to set ERCLK32K clock source.
+ */
+static inline void CLOCK_SetEr32kClock(uint32_t src)
+{
+ SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
+}
+
+/*!
+ * @brief Set SDHC0 clock source.
+ *
+ * @param src The value to set SDHC0 clock source.
+ */
+static inline void CLOCK_SetSdhc0Clock(uint32_t src)
+{
+ SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_SDHCSRC_MASK) | SIM_SOPT2_SDHCSRC(src));
+}
+
+/*!
+ * @brief Set LPUART clock source.
+ *
+ * @param src The value to set LPUART clock source.
+ */
+static inline void CLOCK_SetLpuartClock(uint32_t src)
+{
+ SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUARTSRC_MASK) | SIM_SOPT2_LPUARTSRC(src));
+}
+
+/*!
+ * @brief Set TPM clock source.
+ *
+ * @param src The value to set TPM clock source.
+ */
+static inline void CLOCK_SetTpmClock(uint32_t src)
+{
+ SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TPMSRC_MASK) | SIM_SOPT2_TPMSRC(src));
+}
+
+/*!
+ * @brief Set debug trace clock source.
+ *
+ * @param src The value to set debug trace clock source.
+ */
+static inline void CLOCK_SetTraceClock(uint32_t src, uint32_t divValue, uint32_t fracValue)
+{
+ SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) | SIM_SOPT2_TRACECLKSEL(src));
+ SIM->CLKDIV4 = SIM_CLKDIV4_TRACEDIV(divValue) | SIM_CLKDIV4_TRACEFRAC(fracValue);
+}
+
+/*!
+ * @brief Set PLLFLLSEL clock source.
+ *
+ * @param src The value to set PLLFLLSEL clock source.
+ */
+static inline void CLOCK_SetPllFllSelClock(uint32_t src, uint32_t divValue, uint32_t fracValue)
+{
+ SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) | SIM_SOPT2_PLLFLLSEL(src));
+ SIM->CLKDIV3 = SIM_CLKDIV3_PLLFLLDIV(divValue) | SIM_CLKDIV3_PLLFLLFRAC(fracValue);
+}
+
+/*!
+ * @brief Set CLKOUT source.
+ *
+ * @param src The value to set CLKOUT source.
+ */
+static inline void CLOCK_SetClkOutClock(uint32_t src)
+{
+ SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src));
+}
+
+/*!
+ * @brief Set RTC_CLKOUT source.
+ *
+ * @param src The value to set RTC_CLKOUT source.
+ */
+static inline void CLOCK_SetRtcClkOutClock(uint32_t src)
+{
+ SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src));
+}
+
+/*! @brief Enable USB HS clock.
+ *
+ * @param src USB HS clock source.
+ * @param freq The frequency specified by src.
+ * @retval true The clock is set successfully.
+ * @retval false The clock source is invalid to get proper USB HS clock.
+ */
+bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
+
+/*! @brief Disable USB HS clock.
+ *
+ * Disable USB HS clock.
+ */
+static inline void CLOCK_DisableUsbhs0Clock(void)
+{
+ SIM->SOPT2 &= ~SIM_SOPT2_USBREGEN_MASK;
+ SIM->SCGC3 &= ~(SIM_SCGC3_USBHS_MASK | SIM_SCGC3_USBHSPHY_MASK);
+}
+
+/*! @brief Enable USB FS clock.
+ *
+ * @param src USB FS clock source.
+ * @param freq The frequency specified by src.
+ * @retval true The clock is set successfully.
+ * @retval false The clock source is invalid to get proper USB FS clock.
+ */
+bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);
+
+/*! @brief Disable USB FS clock.
+ *
+ * Disable USB FS clock.
+ */
+static inline void CLOCK_DisableUsbfs0Clock(void)
+{
+ CLOCK_DisableClock(kCLOCK_Usbfs0);
+}
+
+/*!
+ * @brief System clock divider
+ *
+ * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV3], SIM_CLKDIV1[OUTDIV4].
+ *
+ * @param outdiv1 Clock 1 output divider value.
+ *
+ * @param outdiv2 Clock 2 output divider value.
+ *
+ * @param outdiv3 Clock 3 output divider value.
+ *
+ * @param outdiv4 Clock 4 output divider value.
+ */
+static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv3, uint32_t outdiv4)
+{
+ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) | SIM_CLKDIV1_OUTDIV3(outdiv3) |
+ SIM_CLKDIV1_OUTDIV4(outdiv4);
+}
+
+/*!
+ * @brief Gets the clock frequency for a specific clock name.
+ *
+ * This function checks the current clock configurations and then calculates
+ * the clock frequency for a specific clock name defined in clock_name_t.
+ * The MCG must be properly configured before using this function.
+ *
+ * @param clockName Clock names defined in clock_name_t
+ * @return Clock frequency value in Hertz
+ */
+uint32_t CLOCK_GetFreq(clock_name_t clockName);
+
+/*!
+ * @brief Get the core clock or system clock frequency.
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetCoreSysClkFreq(void);
+
+/*!
+ * @brief Get the platform clock frequency.
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetPlatClkFreq(void);
+
+/*!
+ * @brief Get the bus clock frequency.
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetBusClkFreq(void);
+
+/*!
+ * @brief Get the flexbus clock frequency.
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetFlexBusClkFreq(void);
+
+/*!
+ * @brief Get the flash clock frequency.
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetFlashClkFreq(void);
+
+/*!
+ * @brief Get the output clock frequency selected by SIM[PLLFLLSEL].
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetPllFllSelClkFreq(void);
+
+/*!
+ * @brief Get the external reference 32K clock frequency (ERCLK32K).
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetEr32kClkFreq(void);
+
+/*!
+ * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetOsc0ErClkFreq(void);
+
+/*!
+ * @brief Get the OSC0 external reference undivided clock frequency (OSC0ERCLK_UNDIV).
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetOsc0ErClkUndivFreq(void);
+
+/*!
+ * @brief Set the clock configure in SIM module.
+ *
+ * This function sets system layer clock settings in SIM module.
+ *
+ * @param config Pointer to the configure structure.
+ */
+void CLOCK_SetSimConfig(sim_clock_config_t const *config);
+
+/*!
+ * @brief Set the system clock dividers in SIM to safe value.
+ *
+ * The system level clocks (core clock, bus clock, flexbus clock and flash clock)
+ * must be in allowed ranges. During MCG clock mode switch, the MCG output clock
+ * changes then the system level clocks may be out of range. This function could
+ * be used before MCG mode change, to make sure system level clocks are in allowed
+ * range.
+ *
+ * @param config Pointer to the configure structure.
+ */
+static inline void CLOCK_SetSimSafeDivs(void)
+{
+ SIM->CLKDIV1 = 0x03770000U;
+}
+
+/*! @name MCG frequency functions. */
+/*@{*/
+
+/*!
+ * @brief Get the MCG output clock(MCGOUTCLK) frequency.
+ *
+ * This function gets the MCG output clock frequency (Hz) based on current MCG
+ * register value.
+ *
+ * @return The frequency of MCGOUTCLK.
+ */
+uint32_t CLOCK_GetOutClkFreq(void);
+
+/*!
+ * @brief Get the MCG FLL clock(MCGFLLCLK) frequency.
+ *
+ * This function gets the MCG FLL clock frequency (Hz) based on current MCG
+ * register value. The FLL is only enabled in FEI/FBI/FEE/FBE mode, in other
+ * modes, FLL is disabled in low power state.
+ *
+ * @return The frequency of MCGFLLCLK.
+ */
+uint32_t CLOCK_GetFllFreq(void);
+
+/*!
+ * @brief Get the MCG internal reference clock(MCGIRCLK) frequency.
+ *
+ * This function gets the MCG internal reference clock frequency (Hz) based
+ * on current MCG register value.
+ *
+ * @return The frequency of MCGIRCLK.
+ */
+uint32_t CLOCK_GetInternalRefClkFreq(void);
+
+/*!
+ * @brief Get the MCG fixed frequency clock(MCGFFCLK) frequency.
+ *
+ * This function gets the MCG fixed frequency clock frequency (Hz) based
+ * on current MCG register value.
+ *
+ * @return The frequency of MCGFFCLK.
+ */
+uint32_t CLOCK_GetFixedFreqClkFreq(void);
+
+/*!
+ * @brief Get the MCG PLL0 clock(MCGPLL0CLK) frequency.
+ *
+ * This function gets the MCG PLL0 clock frequency (Hz) based on current MCG
+ * register value.
+ *
+ * @return The frequency of MCGPLL0CLK.
+ */
+uint32_t CLOCK_GetPll0Freq(void);
+
+/*!
+ * @brief Get the MCG external PLL frequency.
+ *
+ * This function gets the MCG external PLL frequency (Hz).
+ *
+ * @return The frequency of MCG external PLL.
+ */
+uint32_t CLOCK_GetExtPllFreq(void);
+
+/*!
+ * @brief Set the MCG external PLL frequency.
+ *
+ * This function sets the MCG external PLL frequency (Hz), the MCG external PLL
+ * frequency is passed in to MCG driver through this function. Please call this
+ * function after the external PLL frequency is changed, otherwise the APIs for
+ * get frequency may returns wrong value.
+ *
+ * @param The frequency of MCG external PLL.
+ */
+void CLOCK_SetExtPllFreq(uint32_t freq);
+
+/*@}*/
+
+/*! @name MCG clock configuration. */
+/*@{*/
+
+/*!
+ * @brief Enable or disable MCG low power.
+ *
+ * Enable MCG low power will disable the PLL and FLL in bypass modes. That is,
+ * in FBE and PBE modes, enable low power will set MCG to BLPE mode, in FBI and
+ * PBI mode, enable low power will set MCG to BLPI mode.
+ * When disable MCG low power, the PLL or FLL will be enabled based on MCG setting.
+ *
+ * @param enable True to enable MCG low power, false to disable MCG low power.
+ */
+static inline void CLOCK_SetLowPowerEnable(bool enable)
+{
+ if (enable)
+ {
+ MCG->C2 |= MCG_C2_LP_MASK;
+ }
+ else
+ {
+ MCG->C2 &= ~MCG_C2_LP_MASK;
+ }
+}
+
+/*!
+ * @brief Configure the Internal Reference clock (MCGIRCLK)
+ *
+ * This function setups the \c MCGIRCLK base on parameters. It selects the IRC
+ * source, if fast IRC is used, this function also sets the fast IRC divider.
+ * This function also sets whether enable \c MCGIRCLK in stop mode.
+ * Calling this function in FBI/PBI/BLPI modes may change the system clock, so
+ * it is not allowed to use this in these modes.
+ *
+ * @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
+ * @param ircs MCGIRCLK clock source, choose fast or slow.
+ * @param fcrdiv Fast IRC divider setting (\c FCRDIV).
+ * @retval kStatus_MCG_SourceUsed MCGIRCLK is used as system clock, should not configure MCGIRCLK.
+ * @retval kStatus_Success MCGIRCLK configuration finished successfully.
+ */
+status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
+
+/*!
+ * @brief Select the MCG external reference clock.
+ *
+ * Select the MCG external reference clock source, it changes the MCG_C7[OSCSEL]
+ * and wait for the clock source stable. Should not change external reference
+ * clock in FEE/FBE/BLPE/PBE/PEE mdes, so don't call this function in these modes.
+ *
+ * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
+ * @retval kStatus_MCG_SourceUsed External reference clock is used, should not change.
+ * @retval kStatus_Success External reference clock set successfully.
+ */
+status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
+
+/*!
+ * @brief Enables the PLL0 in FLL mode.
+ *
+ * This function setups the PLL0 in FLL mode, make sure the PLL reference
+ * clock is enabled before calling this function. This function reconfigures
+ * the PLL0, make sure the PLL0 is not used as a clock source while calling
+ * this function. The function CLOCK_CalcPllDiv can help to get the proper PLL
+ * divider values.
+ *
+ * @param config Pointer to the configuration structure.
+ */
+void CLOCK_EnablePll0(mcg_pll_config_t const *config);
+
+/*!
+ * @brief Disables the PLL0 in FLL mode.
+ *
+ * This function disables the PLL0 in FLL mode, it should be used together with
+ * @ref CLOCK_EnablePll0.
+ */
+static inline void CLOCK_DisablePll0(void)
+{
+ MCG->C5 &= ~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK);
+}
+
+/*!
+ * @brief Calculates the PLL divider setting for desired output frequency.
+ *
+ * This function calculates the proper reference clock divider (\c PRDIV) and
+ * VCO divider (\c VDIV) to generate desired PLL output frequency. It returns the
+ * closest frequency PLL could generate, the corresponding \c PRDIV/VDIV are
+ * returned from parameters. If desired frequency is not valid, this function
+ * returns 0.
+ *
+ * @param refFreq PLL reference clock frequency.
+ * @param desireFreq Desired PLL output frequency.
+ * @param prdiv PRDIV value to generate desired PLL frequency.
+ * @param vdiv VDIV value to generate desired PLL frequency.
+ * @return Closest frequency PLL could generate.
+ */
+uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv);
+
+/*@}*/
+
+/*! @name MCG clock lock monitor functions. */
+/*@{*/
+
+/*!
+ * @brief Set the OSC0 clock monitor mode.
+ *
+ * Set the OSC0 clock monitor mode, see @ref mcg_monitor_mode_t for details.
+ *
+ * @param mode The monitor mode to set.
+ */
+void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode);
+
+/*!
+ * @brief Set the RTC OSC clock monitor mode.
+ *
+ * Set the RTC OSC clock monitor mode, see @ref mcg_monitor_mode_t for details.
+ *
+ * @param mode The monitor mode to set.
+ */
+void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode);
+
+/*!
+ * @brief Set the PLL0 clock monitor mode.
+ *
+ * Set the PLL0 clock monitor mode, see @ref mcg_monitor_mode_t for details.
+ *
+ * @param mode The monitor mode to set.
+ */
+void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode);
+
+/*!
+ * @brief Set the external PLL clock monitor mode.
+ *
+ * Set the external PLL clock monitor mode, see @ref mcg_monitor_mode_t
+ * for details.
+ *
+ * @param mode The monitor mode to set.
+ */
+void CLOCK_SetExtPllMonitorMode(mcg_monitor_mode_t mode);
+
+/*!
+ * @brief Get the MCG status flags.
+ *
+ * This function gets the MCG clock status flags, all the status flags are
+ * returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To
+ * check specific flags, compare the return value with the flags.
+ *
+ * Example:
+ * @code
+ // To check the clock lost lock status of OSC0 and PLL0.
+ uint32_t mcgFlags;
+
+ mcgFlags = CLOCK_GetStatusFlags();
+
+ if (mcgFlags & kMCG_Osc0LostFlag)
+ {
+ // OSC0 clock lock lost. Do something.
+ }
+ if (mcgFlags & kMCG_Pll0LostFlag)
+ {
+ // PLL0 clock lock lost. Do something.
+ }
+ @endcode
+ *
+ * @return Logical OR value of the @ref _mcg_status_flags_t.
+ */
+uint32_t CLOCK_GetStatusFlags(void);
+
+/*!
+ * @brief Clears the MCG status flags.
+ *
+ * This function clears the MCG clock lock lost status. The parameter is logical
+ * OR value of the flags to clear, see @ref _mcg_status_flags_t.
+ *
+ * Example:
+ * @code
+ // To clear the clock lost lock status flags of OSC0 and PLL0.
+
+ CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag);
+ @endcode
+ *
+ * @param mask The status flags to clear. This is a logical OR of members of the
+ * enumeration @ref _mcg_status_flags_t.
+ */
+void CLOCK_ClearStatusFlags(uint32_t mask);
+
+/*@}*/
+
+/*!
+ * @name OSC configuration
+ * @{
+ */
+
+/*!
+ * @brief Configures the OSC external reference clock (OSCERCLK).
+ *
+ * This function configures the OSC external reference clock (OSCERCLK).
+ * For example, to enable the OSCERCLK in normal mode and stop mode, and also set
+ * the output divider to 1, as follows:
+ *
+ @code
+ oscer_config_t config =
+ {
+ .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
+ .erclkDiv = 1U,
+ };
+
+ OSC_SetExtRefClkConfig(OSC, &config);
+ @endcode
+ *
+ * @param base OSC peripheral address.
+ * @param config Pointer to the configuration structure.
+ */
+static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config)
+{
+ uint8_t reg = base->CR;
+
+ reg &= ~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK);
+ reg |= config->enableMode;
+
+ base->CR = reg;
+
+ base->DIV = OSC_DIV_ERPS(config->erclkDiv);
+}
+
+/*!
+ * @brief Sets the capacitor load configuration for the oscillator.
+ *
+ * This function sets the specified capacitors configuration for the oscillator.
+ * This should be done in the early system level initialization function call
+ * based on the system configuration.
+ *
+ * @param base OSC peripheral address.
+ * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load.
+ *
+ * Example:
+ @code
+ // To enable only 2 pF and 8 pF capacitor load, please use like this.
+ OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P);
+ @endcode
+ */
+static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad)
+{
+ uint8_t reg = base->CR;
+
+ reg &= ~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK);
+ reg |= capLoad;
+
+ base->CR = reg;
+}
+
+/*!
+ * @brief Initialize OSC0.
+ *
+ * This function initializes OSC0 according to board configuration.
+ *
+ * @param config Pointer to the OSC0 configuration structure.
+ */
+void CLOCK_InitOsc0(osc_config_t const *config);
+
+/*!
+ * @brief Deinitialize OSC0.
+ *
+ * This function deinitializes OSC0.
+ */
+void CLOCK_DeinitOsc0(void);
+
+/* @} */
+
+/*!
+ * @name External clock frequency
+ * @{
+ */
+
+/*!
+ * @brief Set the XTAL0 frequency based on board setting.
+ *
+ * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
+ */
+static inline void CLOCK_SetXtal0Freq(uint32_t freq)
+{
+ g_xtal0Freq = freq;
+}
+
+/*!
+ * @brief Set the XTAL32/RTC_CLKIN frequency based on board setting.
+ *
+ * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
+ */
+static inline void CLOCK_SetXtal32Freq(uint32_t freq)
+{
+ g_xtal32Freq = freq;
+}
+/* @} */
+
+/*!
+ * @name MCG auto-trim machine.
+ * @{
+ */
+
+/*!
+ * @brief Auto trim the internal reference clock.
+ *
+ * This function trims the internal reference clock using external clock. If
+ * successful, it returns the kStatus_Success and the frequency after
+ * trimming is received in the parameter @p actualFreq. If an error occurs,
+ * the error code is returned.
+ *
+ * @param extFreq External clock frequency, should be bus clock.
+ * @param desireFreq Frequency want to trim to.
+ * @param actualFreq Actual frequency after trim.
+ * @param atms Trim fast or slow internal reference clock.
+ * @retval kStatus_Success ATM success.
+ * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for ATM.
+ * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
+ * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as bus clock source.
+ * @retval kStatus_MCG_AtmHardwareFail Hardware fails during trim.
+ */
+status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
+/* @} */
+
+/*! @name MCG mode functions. */
+/*@{*/
+
+/*!
+ * @brief Gets the current MCG mode.
+ *
+ * This function checks the MCG registers and determine current MCG mode.
+ *
+ * @return Current MCG mode or error code, see @ref mcg_mode_t.
+ */
+mcg_mode_t CLOCK_GetMode(void);
+
+/*!
+ * @brief Set MCG to FEI mode.
+ *
+ * This function sets MCG to FEI mode. If could not set to FEI mode directly
+ * from current mode, this function returns error.
+ *
+ * @param dmx32 DMX32 in FEI mode.
+ * @param drs The DCO range selection.
+ * @param fllStableDelay Delay function to make sure FLL is stable, if pass
+ * in NULL, then does not delay.
+ * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
+ * @retval kStatus_Success Switch to target mode successfully.
+ * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
+ * to frequency above 32768Hz.
+ */
+status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
+
+/*!
+ * @brief Set MCG to FEE mode.
+ *
+ * This function sets MCG to FEE mode. If could not set to FEE mode directly
+ * from current mode, this function returns error.
+ *
+ * @param frdiv FLL reference clock divider setting, FRDIV.
+ * @param dmx32 DMX32 in FEE mode.
+ * @param drs The DCO range selection.
+ * @param fllStableDelay Delay function to make sure FLL is stable, if pass
+ * in NULL, then does not delay.
+ *
+ * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
+ * @retval kStatus_Success Switch to target mode successfully.
+ */
+status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
+
+/*!
+ * @brief Set MCG to FBI mode.
+ *
+ * This function sets MCG to FBI mode. If could not set to FBI mode directly
+ * from current mode, this function returns error.
+ *
+ * @param dmx32 DMX32 in FBI mode.
+ * @param drs The DCO range selection.
+ * @param fllStableDelay Delay function to make sure FLL is stable. If FLL
+ * is not used in FBI mode, this parameter could be NULL. Pass in
+ * NULL does not delay.
+ * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
+ * @retval kStatus_Success Switch to target mode successfully.
+ * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
+ * to frequency above 32768Hz.
+ */
+status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
+
+/*!
+ * @brief Set MCG to FBE mode.
+ *
+ * This function sets MCG to FBE mode. If could not set to FBE mode directly
+ * from current mode, this function returns error.
+ *
+ * @param frdiv FLL reference clock divider setting, FRDIV.
+ * @param dmx32 DMX32 in FBE mode.
+ * @param drs The DCO range selection.
+ * @param fllStableDelay Delay function to make sure FLL is stable. If FLL
+ * is not used in FBE mode, this parameter could be NULL. Pass in NULL
+ * does not delay.
+ * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
+ * @retval kStatus_Success Switch to target mode successfully.
+ */
+status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
+
+/*!
+ * @brief Set MCG to BLPI mode.
+ *
+ * This function sets MCG to BLPI mode. If could not set to BLPI mode directly
+ * from current mode, this function returns error.
+ *
+ * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
+ * @retval kStatus_Success Switch to target mode successfully.
+ */
+status_t CLOCK_SetBlpiMode(void);
+
+/*!
+ * @brief Set MCG to BLPE mode.
+ *
+ * This function sets MCG to BLPE mode. If could not set to BLPE mode directly
+ * from current mode, this function returns error.
+ *
+ * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
+ * @retval kStatus_Success Switch to target mode successfully.
+ */
+status_t CLOCK_SetBlpeMode(void);
+
+/*!
+ * @brief Set MCG to PBE mode.
+ *
+ * This function sets MCG to PBE mode. If could not set to PBE mode directly
+ * from current mode, this function returns error.
+ *
+ * @param pllcs The PLL selection, PLLCS.
+ * @param config Pointer to the PLL configuration.
+ * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
+ * @retval kStatus_Success Switch to target mode successfully.
+ *
+ * @note
+ * 1. The parameter \c pllcs selects the PLL, for some platforms, there is
+ * only one PLL, the parameter pllcs is kept for interface compatible.
+ * 2. The parameter \c config is the PLL configuration structure, on some
+ * platforms, could choose the external PLL directly. This means that the
+ * configuration structure is not necessary, pass in NULL for this case.
+ * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
+ */
+status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
+
+/*!
+ * @brief Set MCG to PEE mode.
+ *
+ * This function sets MCG to PEE mode.
+ *
+ * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
+ * @retval kStatus_Success Switch to target mode successfully.
+ *
+ * @note This function only change CLKS to use PLL/FLL output. If the
+ * PRDIV/VDIV are different from PBE mode, please setup these
+ * settings in PBE mode and wait for stable then switch to PEE mode.
+ */
+status_t CLOCK_SetPeeMode(void);
+
+/*!
+ * @brief Switch MCG to FBE mode quickly from external mode.
+ *
+ * This function changes MCG from external modes (PEE/PBE/BLPE/FEE) to FBE mode quickly.
+ * It only changes to use external clock as the system clock souce and disable PLL, but does not
+ * configure FLL settings. This is a lite function with small code size, it is useful
+ * during mode switch. For example, to switch from PEE mode to FEI mode:
+ *
+ * @code
+ * CLOCK_ExternalModeToFbeModeQuick();
+ * CLOCK_SetFeiMode(...);
+ * @endcode
+ *
+ * @retval kStatus_Success Change successfully.
+ * @retval kStatus_MCG_ModeInvalid Current mode is not external modes, should not call this function.
+ */
+status_t CLOCK_ExternalModeToFbeModeQuick(void);
+
+/*!
+ * @brief Switch MCG to FBI mode quickly from internal modes.
+ *
+ * This function changes MCG from internal modes (PEI/PBI/BLPI/FEI) to FBI mode quickly.
+ * It only changes to use MCGIRCLK as the system clock souce and disable PLL, but does not
+ * configure FLL settings. This is a lite function with small code size, it is useful
+ * during mode switch. For example, to switch from PEI mode to FEE mode:
+ *
+ * @code
+ * CLOCK_InternalModeToFbiModeQuick();
+ * CLOCK_SetFeeMode(...);
+ * @endcode
+ *
+ * @retval kStatus_Success Change successfully.
+ * @retval kStatus_MCG_ModeInvalid Current mode is not internal mode, should not call this function.
+ */
+status_t CLOCK_InternalModeToFbiModeQuick(void);
+
+/*!
+ * @brief Set MCG to FEI mode during system boot up.
+ *
+ * This function sets MCG to FEI mode from reset mode, it could be used to
+ * set up MCG during system boot up.
+ *
+ * @param dmx32 DMX32 in FEI mode.
+ * @param drs The DCO range selection.
+ * @param fllStableDelay Delay function to make sure FLL is stable.
+ *
+ * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
+ * @retval kStatus_Success Switch to target mode successfully.
+ * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
+ * to frequency above 32768Hz.
+ */
+status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
+
+/*!
+ * @brief Set MCG to FEE mode during system bootup.
+ *
+ * This function sets MCG to FEE mode from reset mode, it could be used to
+ * set up MCG during system boot up.
+ *
+ * @param oscsel OSC clock select, OSCSEL.
+ * @param frdiv FLL reference clock divider setting, FRDIV.
+ * @param dmx32 DMX32 in FEE mode.
+ * @param drs The DCO range selection.
+ * @param fllStableDelay Delay function to make sure FLL is stable.
+ *
+ * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
+ * @retval kStatus_Success Switch to target mode successfully.
+ */
+status_t CLOCK_BootToFeeMode(
+ mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
+
+/*!
+ * @brief Set MCG to BLPI mode during system boot up.
+ *
+ * This function sets MCG to BLPI mode from reset mode, it could be used to
+ * setup MCG during sytem boot up.
+ *
+ * @param fcrdiv Fast IRC divider, FCRDIV.
+ * @param ircs The internal reference clock to select, IRCS.
+ * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
+ *
+ * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
+ * @retval kStatus_Success Switch to target mode successfully.
+ */
+status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
+
+/*!
+ * @brief Set MCG to BLPE mode during sytem boot up.
+ *
+ * This function sets MCG to BLPE mode from reset mode, it could be used to
+ * setup MCG during sytem boot up.
+ *
+ * @param oscsel OSC clock select, MCG_C7[OSCSEL].
+ *
+ * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
+ * @retval kStatus_Success Switch to target mode successfully.
+ */
+status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
+
+/*!
+ * @brief Set MCG to PEE mode during system boot up.
+ *
+ * This function sets MCG to PEE mode from reset mode, it could be used to
+ * setup MCG during system boot up.
+ *
+ * @param oscsel OSC clock select, MCG_C7[OSCSEL].
+ * @param pllcs The PLL selection, PLLCS.
+ * @param config Pointer to the PLL configuration.
+ *
+ * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
+ * @retval kStatus_Success Switch to target mode successfully.
+ */
+status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
+
+/*!
+ * @brief Set MCG to some target mode.
+ *
+ * This function sets MCG to some target mode defined by the configure
+ * structure, if cannot switch to target mode directly, this function will
+ * choose the proper path.
+ *
+ * @param config Pointer to the target MCG mode configuration structure.
+ * @return Return kStatus_Success if switch successfully, otherwise return error code #_mcg_status.
+ *
+ * @note If external clock is used in the target mode, please make sure it is
+ * enabled, for example, if the OSC0 is used, please setup OSC0 correctly before
+ * this funciton.
+ */
+status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_CLOCK_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/MK26F18/fsl_device_registers.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/freescale/k26f/MK26F18/fsl_device_registers.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,35 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MK26FN2M0CAC18) || defined(CPU_MK26FN2M0VLQ18) || defined(CPU_MK26FN2M0VMD18) || \ + defined(CPU_MK26FN2M0VMI18)) + +#define K26F18_SERIES + +/* CMSIS-style register definitions */ +#include "MK26F18.h" +/* CPU specific feature definitions */ +#include "MK26F18_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/MK26F18/system_MK26F18.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/MK26F18/system_MK26F18.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,223 @@
+/*
+** ###################################################################
+** Processors: MK26FN2M0CAC18
+** MK26FN2M0VLQ18
+** MK26FN2M0VMD18
+** MK26FN2M0VMI18
+**
+** Compilers: Keil ARM C/C++ Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+** MCUXpresso Compiler
+**
+** Reference manual: MK26P169M180SF5RM, Rev. 1, Mar 2015
+** Version: rev. 2.0, 2015-03-25
+** Build: b180801
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2018 NXP
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** Revisions:
+** - rev. 1.0 (2014-12-04)
+** Initial version.
+** - rev. 1.1 (2015-02-19)
+** Renamed interrupt vector LLW to LLWU.
+** - rev. 2.0 (2015-03-25)
+** Registers updated according to the reference manual revision 1, March 2015
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK26F18
+ * @version 2.0
+ * @date 2015-03-25
+ * @brief Device specific configuration file for MK26F18 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+
+
+/* ----------------------------------------------------------------------------
+ -- Core clock
+ ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+ -- SystemInit()
+ ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+ SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+ /* Watchdog disable */
+#if (DISABLE_WDOG)
+ /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
+ WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
+ /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
+ WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
+ /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
+ WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
+ WDOG_STCTRLH_WAITEN_MASK |
+ WDOG_STCTRLH_STOPEN_MASK |
+ WDOG_STCTRLH_ALLOWUPDATE_MASK |
+ WDOG_STCTRLH_CLKSRC_MASK |
+ 0x0100U;
+#endif /* (DISABLE_WDOG) */
+
+ SystemInitHook();
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemCoreClockUpdate()
+ ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+ uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+ uint16_t Divider;
+
+ if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
+ /* Output of FLL or PLL is selected */
+ if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
+ /* FLL is selected */
+ if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
+ /* External reference clock is selected */
+ switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
+ case 0x00U:
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ break;
+ case 0x01U:
+ MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+ break;
+ case 0x02U:
+ default:
+ MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+ break;
+ }
+ if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
+ switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
+ case 0x38U:
+ Divider = 1536U;
+ break;
+ case 0x30U:
+ Divider = 1280U;
+ break;
+ default:
+ Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+ break;
+ }
+ } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
+ Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+ }
+ MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+ } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+ } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+ /* Select correct multiplier to calculate the MCG output clock */
+ switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+ case 0x00U:
+ MCGOUTClock *= 640U;
+ break;
+ case 0x20U:
+ MCGOUTClock *= 1280U;
+ break;
+ case 0x40U:
+ MCGOUTClock *= 1920U;
+ break;
+ case 0x60U:
+ MCGOUTClock *= 2560U;
+ break;
+ case 0x80U:
+ MCGOUTClock *= 732U;
+ break;
+ case 0xA0U:
+ MCGOUTClock *= 1464U;
+ break;
+ case 0xC0U:
+ MCGOUTClock *= 2197U;
+ break;
+ case 0xE0U:
+ MCGOUTClock *= 2929U;
+ break;
+ default:
+ break;
+ }
+ } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+ if ((MCG->C11 & MCG_C11_PLLCS_MASK) == 0x00U) {
+ /* PLL is selected */
+ Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U);
+ MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+ Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U);
+ MCGOUTClock *= Divider; /* Calculate the VCO output clock */
+ MCGOUTClock /= 2; /* Calculate the MCG output clock */
+ } else {
+ /* External PLL is selected */
+ if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == 0x00U) {
+ MCGOUTClock = CPU_XTAL_CLK_HZ;
+ } else {
+ Divider = (((uint16_t)USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_FRAC_MASK) >> 4);
+ if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == USBPHY_ANACTRL_PFD_CLK_SEL(1)) {
+ Divider *= 0x04U;
+ } else if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == USBPHY_ANACTRL_PFD_CLK_SEL(2)) {
+ Divider *= 0x02U;
+ }
+ MCGOUTClock = (uint32_t)(480000000 / Divider);
+ MCGOUTClock *= 18;
+ }
+ }
+ } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
+ /* Internal reference clock is selected */
+ if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+ } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+ Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
+ MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
+ } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
+ /* External reference clock is selected */
+ switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
+ case 0x00U:
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ break;
+ case 0x01U:
+ MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+ break;
+ case 0x02U:
+ default:
+ MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+ break;
+ }
+ } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+ /* Reserved value */
+ return;
+ } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+ SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemInitHook()
+ ---------------------------------------------------------------------------- */
+
+__attribute__ ((weak)) void SystemInitHook (void) {
+ /* Void implementation of the weak function. */
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/MK26F18/system_MK26F18.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/MK26F18/system_MK26F18.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,131 @@
+/*
+** ###################################################################
+** Processors: MK26FN2M0CAC18
+** MK26FN2M0VLQ18
+** MK26FN2M0VMD18
+** MK26FN2M0VMI18
+**
+** Compilers: Keil ARM C/C++ Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+** MCUXpresso Compiler
+**
+** Reference manual: MK26P169M180SF5RM, Rev. 1, Mar 2015
+** Version: rev. 2.0, 2015-03-25
+** Build: b180801
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2018 NXP
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** Revisions:
+** - rev. 1.0 (2014-12-04)
+** Initial version.
+** - rev. 1.1 (2015-02-19)
+** Renamed interrupt vector LLW to LLWU.
+** - rev. 2.0 (2015-03-25)
+** Registers updated according to the reference manual revision 1, March 2015
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK26F18
+ * @version 2.0
+ * @date 2015-03-25
+ * @brief Device specific configuration file for MK26F18 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef _SYSTEM_MK26F18_H_
+#define _SYSTEM_MK26F18_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+#ifndef DISABLE_WDOG
+ #define DISABLE_WDOG 1
+#endif
+
+/* Define clock source values */
+
+#define CPU_XTAL_CLK_HZ 16000000U /* Value of the external crystal or oscillator clock frequency of the system oscillator (OSC) in Hz */
+#define CPU_XTAL32k_CLK_HZ 32768U /* Value of the external 32k crystal or oscillator clock frequency of the RTC in Hz */
+#define CPU_INT_SLOW_CLK_HZ 32768U /* Value of the slow internal oscillator clock frequency in Hz */
+#define CPU_INT_FAST_CLK_HZ 4000000U /* Value of the fast internal oscillator clock frequency in Hz */
+#define CPU_INT_IRC_CLK_HZ 48000000U /* Value of the 48M internal oscillator clock frequency in Hz */
+
+/* RTC oscillator setting */
+/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
+#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
+#define SYSTEM_SMC_PMPROT_VALUE 0xAAU /* SMC_PMPROT */
+
+#define DEFAULT_SYSTEM_CLOCK 20971520u
+
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+/**
+ * @brief SystemInit function hook.
+ *
+ * This weak function allows to call specific initialization code during the
+ * SystemInit() execution.This can be used when an application specific code needs
+ * to be called as close to the reset entry as possible (for example the Multicore
+ * Manager MCMGR_EarlyInit() function call).
+ * NOTE: No global r/w variables can be used in this hook function because the
+ * initialization of these variables happens after this function.
+ */
+void SystemInitHook (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_MK26F18_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/RTE_Device.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/freescale/k26f/RTE_Device.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,32 @@ +/* ----------------------------------------------------------------------------- + * Copyright (C) 2013 ARM Limited. All rights reserved. + * + * $Date: 27. June 2013 + * $Revision: V1.00 + * + * Project: RTE Device Configuration for NXP Kinetis K20 + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +#define RTE_USART1 1 +#define RTE_USART1_DMA_EN 0 + + +#define RTE_USART1_DMA_TX_DMA_BASE (DMA0) +#define RTE_USART1_DMA_TX_CH (0) +#define RTE_USART1_DMA_TX_DMAMUX_BASE (DMAMUX0) +#define RTE_USART1_DMA_TX_PERI_SEL (5) // DMAMUX source 5 is UART1 TX + +#define RTE_USART1_DMA_RX_DMA_BASE (DMA0) +#define RTE_USART1_DMA_RX_CH (1) +#define RTE_USART1_DMA_RX_DMAMUX_BASE (DMAMUX0) +#define RTE_USART1_DMA_RX_PERI_SEL (4) // DMAMUX source 4 is UART1 RX + + +#endif /* __RTE_DEVICE_H */ +
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/armcc/startup_MK26F18.s --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/freescale/k26f/armcc/startup_MK26F18.s Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,1125 @@ +; * --------------------------------------------------------------------------------------- +; * @file: startup_MK26F18.s +; * @purpose: CMSIS Cortex-M4 Core Device Startup File +; * MK26F18 +; * @version: 2.0 +; * @date: 2015-3-25 +; * @build: b151210 +; * --------------------------------------------------------------------------------------- +; * +; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. +; * All rights reserved. +; * +; * Redistribution and use in source and binary forms, with or without modification, +; * are permitted provided that the following conditions are met: +; * +; * o Redistributions of source code must retain the above copyright notice, this list +; * of conditions and the following disclaimer. +; * +; * o Redistributions in binary form must reproduce the above copyright notice, this +; * list of conditions and the following disclaimer in the documentation and/or +; * other materials provided with the distribution. +; * +; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; * contributors may be used to endorse or promote products derived from this +; * software without specific prior written permission. +; * +; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; * +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x0000100 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD MemManage_Handler ;MPU Fault Handler + DCD BusFault_Handler ;Bus Fault Handler + DCD UsageFault_Handler ;Usage Fault Handler + DCD 0 ;Reserved + DCD DAPLINK_BUILD_KEY ; Build type - BL/IF + DCD DAPLINK_HIC_ID ; Compatibility + DCD DAPLINK_VERSION ; Version + DCD SVC_Handler ;SVCall Handler + DCD DebugMon_Handler ;Debug Monitor Handler + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_DMA16_IRQHandler ;DMA Channel 0, 16 Transfer Complete + DCD DMA1_DMA17_IRQHandler ;DMA Channel 1, 17 Transfer Complete + DCD DMA2_DMA18_IRQHandler ;DMA Channel 2, 18 Transfer Complete + DCD DMA3_DMA19_IRQHandler ;DMA Channel 3, 19 Transfer Complete + DCD DMA4_DMA20_IRQHandler ;DMA Channel 4, 20 Transfer Complete + DCD DMA5_DMA21_IRQHandler ;DMA Channel 5, 21 Transfer Complete + DCD DMA6_DMA22_IRQHandler ;DMA Channel 6, 22 Transfer Complete + DCD DMA7_DMA23_IRQHandler ;DMA Channel 7, 23 Transfer Complete + DCD DMA8_DMA24_IRQHandler ;DMA Channel 8, 24 Transfer Complete + DCD DMA9_DMA25_IRQHandler ;DMA Channel 9, 25 Transfer Complete + DCD DMA10_DMA26_IRQHandler ;DMA Channel 10, 26 Transfer Complete + DCD DMA11_DMA27_IRQHandler ;DMA Channel 11, 27 Transfer Complete + DCD DMA12_DMA28_IRQHandler ;DMA Channel 12, 28 Transfer Complete + DCD DMA13_DMA29_IRQHandler ;DMA Channel 13, 29 Transfer Complete + DCD DMA14_DMA30_IRQHandler ;DMA Channel 14, 30 Transfer Complete + DCD DMA15_DMA31_IRQHandler ;DMA Channel 15, 31 Transfer Complete + DCD DMA_Error_IRQHandler ;DMA Error Interrupt + DCD MCM_IRQHandler ;Normal Interrupt + DCD FTFE_IRQHandler ;FTFE Command complete interrupt + DCD Read_Collision_IRQHandler ;Read Collision Interrupt + DCD LVD_LVW_IRQHandler ;Low Voltage Detect, Low Voltage Warning + DCD LLWU_IRQHandler ;Low Leakage Wakeup Unit + DCD WDOG_EWM_IRQHandler ;WDOG Interrupt + DCD RNG_IRQHandler ;RNG Interrupt + DCD I2C0_IRQHandler ;I2C0 interrupt + DCD I2C1_IRQHandler ;I2C1 interrupt + DCD SPI0_IRQHandler ;SPI0 Interrupt + DCD SPI1_IRQHandler ;SPI1 Interrupt + DCD I2S0_Tx_IRQHandler ;I2S0 transmit interrupt + DCD I2S0_Rx_IRQHandler ;I2S0 receive interrupt + DCD Reserved46_IRQHandler ;Reserved interrupt 46 + DCD UART0_RX_TX_IRQHandler ;UART0 Receive/Transmit interrupt + DCD UART0_ERR_IRQHandler ;UART0 Error interrupt + DCD UART1_RX_TX_IRQHandler ;UART1 Receive/Transmit interrupt + DCD UART1_ERR_IRQHandler ;UART1 Error interrupt + DCD UART2_RX_TX_IRQHandler ;UART2 Receive/Transmit interrupt + DCD UART2_ERR_IRQHandler ;UART2 Error interrupt + DCD UART3_RX_TX_IRQHandler ;UART3 Receive/Transmit interrupt + DCD UART3_ERR_IRQHandler ;UART3 Error interrupt + DCD ADC0_IRQHandler ;ADC0 interrupt + DCD CMP0_IRQHandler ;CMP0 interrupt + DCD CMP1_IRQHandler ;CMP1 interrupt + DCD FTM0_IRQHandler ;FTM0 fault, overflow and channels interrupt + DCD FTM1_IRQHandler ;FTM1 fault, overflow and channels interrupt + DCD FTM2_IRQHandler ;FTM2 fault, overflow and channels interrupt + DCD CMT_IRQHandler ;CMT interrupt + DCD RTC_IRQHandler ;RTC interrupt + DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt + DCD PIT0_IRQHandler ;PIT timer channel 0 interrupt + DCD PIT1_IRQHandler ;PIT timer channel 1 interrupt + DCD PIT2_IRQHandler ;PIT timer channel 2 interrupt + DCD PIT3_IRQHandler ;PIT timer channel 3 interrupt + DCD PDB0_IRQHandler ;PDB0 Interrupt + DCD USB0_IRQHandler ;USB0 interrupt + DCD USBDCD_IRQHandler ;USBDCD Interrupt + DCD Reserved71_IRQHandler ;Reserved interrupt 71 + DCD DAC0_IRQHandler ;DAC0 interrupt + DCD MCG_IRQHandler ;MCG Interrupt + DCD LPTMR0_IRQHandler ;LPTimer interrupt + DCD PORTA_IRQHandler ;Port A interrupt + DCD PORTB_IRQHandler ;Port B interrupt + DCD PORTC_IRQHandler ;Port C interrupt + DCD PORTD_IRQHandler ;Port D interrupt + DCD PORTE_IRQHandler ;Port E interrupt + DCD SWI_IRQHandler ;Software interrupt + DCD SPI2_IRQHandler ;SPI2 Interrupt + DCD UART4_RX_TX_IRQHandler ;UART4 Receive/Transmit interrupt + DCD UART4_ERR_IRQHandler ;UART4 Error interrupt + DCD Reserved84_IRQHandler ;Reserved interrupt 84 + DCD Reserved85_IRQHandler ;Reserved interrupt 85 + DCD CMP2_IRQHandler ;CMP2 interrupt + DCD FTM3_IRQHandler ;FTM3 fault, overflow and channels interrupt + DCD DAC1_IRQHandler ;DAC1 interrupt + DCD ADC1_IRQHandler ;ADC1 interrupt + DCD I2C2_IRQHandler ;I2C2 interrupt + DCD CAN0_ORed_Message_buffer_IRQHandler ;CAN0 OR'd message buffers interrupt + DCD CAN0_Bus_Off_IRQHandler ;CAN0 bus off interrupt + DCD CAN0_Error_IRQHandler ;CAN0 error interrupt + DCD CAN0_Tx_Warning_IRQHandler ;CAN0 Tx warning interrupt + DCD CAN0_Rx_Warning_IRQHandler ;CAN0 Rx warning interrupt + DCD CAN0_Wake_Up_IRQHandler ;CAN0 wake up interrupt + DCD SDHC_IRQHandler ;SDHC interrupt + DCD Reserved98_IRQHandler ;Reserved Interrupt 98 + DCD Reserved99_IRQHandler ;Reserved Interrupt 99 + DCD Reserved100_IRQHandler ;Reserved Interrupt 100 + DCD Reserved101_IRQHandler ;Reserved Interrupt 101 + DCD LPUART0_IRQHandler ;LPUART0 status/error interrupt + DCD TSI0_IRQHandler ;TSI0 interrupt + DCD TPM1_IRQHandler ;TPM1 fault, overflow and channels interrupt + DCD TPM2_IRQHandler ;TPM2 fault, overflow and channels interrupt + DCD USBHSDCD_IRQHandler ;USBHSDCD, USBHS Phy Interrupt + DCD I2C3_IRQHandler ;I2C3 interrupt + DCD CMP3_IRQHandler ;CMP3 interrupt + DCD USBHS_IRQHandler ;USB high speed OTG interrupt + DCD CAN1_ORed_Message_buffer_IRQHandler ;CAN1 OR'd message buffers interrupt + DCD CAN1_Bus_Off_IRQHandler ;CAN1 bus off interrupt + DCD CAN1_Error_IRQHandler ;CAN1 error interrupt + DCD CAN1_Tx_Warning_IRQHandler ;CAN1 Tx warning interrupt + DCD CAN1_Rx_Warning_IRQHandler ;CAN1 Rx warning interrupt + DCD CAN1_Wake_Up_IRQHandler ;CAN1 wake up interrupt + DCD DefaultISR ;116 + DCD DefaultISR ;117 + DCD DefaultISR ;118 + DCD DefaultISR ;119 + DCD DefaultISR ;120 + DCD DefaultISR ;121 + DCD DefaultISR ;122 + DCD DefaultISR ;123 + DCD DefaultISR ;124 + DCD DefaultISR ;125 + DCD DefaultISR ;126 + DCD DefaultISR ;127 + DCD DefaultISR ;128 + DCD DefaultISR ;129 + DCD DefaultISR ;130 + DCD DefaultISR ;131 + DCD DefaultISR ;132 + DCD DefaultISR ;133 + DCD DefaultISR ;134 + DCD DefaultISR ;135 + DCD DefaultISR ;136 + DCD DefaultISR ;137 + DCD DefaultISR ;138 + DCD DefaultISR ;139 + DCD DefaultISR ;140 + DCD DefaultISR ;141 + DCD DefaultISR ;142 + DCD DefaultISR ;143 + DCD DefaultISR ;144 + DCD DefaultISR ;145 + DCD DefaultISR ;146 + DCD DefaultISR ;147 + DCD DefaultISR ;148 + DCD DefaultISR ;149 + DCD DefaultISR ;150 + DCD DefaultISR ;151 + DCD DefaultISR ;152 + DCD DefaultISR ;153 + DCD DefaultISR ;154 + DCD DefaultISR ;155 + DCD DefaultISR ;156 + DCD DefaultISR ;157 + DCD DefaultISR ;158 + DCD DefaultISR ;159 + DCD DefaultISR ;160 + DCD DefaultISR ;161 + DCD DefaultISR ;162 + DCD DefaultISR ;163 + DCD DefaultISR ;164 + DCD DefaultISR ;165 + DCD DefaultISR ;166 + DCD DefaultISR ;167 + DCD DefaultISR ;168 + DCD DefaultISR ;169 + DCD DefaultISR ;170 + DCD DefaultISR ;171 + DCD DefaultISR ;172 + DCD DefaultISR ;173 + DCD DefaultISR ;174 + DCD DefaultISR ;175 + DCD DefaultISR ;176 + DCD DefaultISR ;177 + DCD DefaultISR ;178 + DCD DefaultISR ;179 + DCD DefaultISR ;180 + DCD DefaultISR ;181 + DCD DefaultISR ;182 + DCD DefaultISR ;183 + DCD DefaultISR ;184 + DCD DefaultISR ;185 + DCD DefaultISR ;186 + DCD DefaultISR ;187 + DCD DefaultISR ;188 + DCD DefaultISR ;189 + DCD DefaultISR ;190 + DCD DefaultISR ;191 + DCD DefaultISR ;192 + DCD DefaultISR ;193 + DCD DefaultISR ;194 + DCD DefaultISR ;195 + DCD DefaultISR ;196 + DCD DefaultISR ;197 + DCD DefaultISR ;198 + DCD DefaultISR ;199 + DCD DefaultISR ;200 + DCD DefaultISR ;201 + DCD DefaultISR ;202 + DCD DefaultISR ;203 + DCD DefaultISR ;204 + DCD DefaultISR ;205 + DCD DefaultISR ;206 + DCD DefaultISR ;207 + DCD DefaultISR ;208 + DCD DefaultISR ;209 + DCD DefaultISR ;210 + DCD DefaultISR ;211 + DCD DefaultISR ;212 + DCD DefaultISR ;213 + DCD DefaultISR ;214 + DCD DefaultISR ;215 + DCD DefaultISR ;216 + DCD DefaultISR ;217 + DCD DefaultISR ;218 + DCD DefaultISR ;219 + DCD DefaultISR ;220 + DCD DefaultISR ;221 + DCD DefaultISR ;222 + DCD DefaultISR ;223 + DCD DefaultISR ;224 + DCD DefaultISR ;225 + DCD DefaultISR ;226 + DCD DefaultISR ;227 + DCD DefaultISR ;228 + DCD DefaultISR ;229 + DCD DefaultISR ;230 + DCD DefaultISR ;231 + DCD DefaultISR ;232 + DCD DefaultISR ;233 + DCD DefaultISR ;234 + DCD DefaultISR ;235 + DCD DefaultISR ;236 + DCD DefaultISR ;237 + DCD DefaultISR ;238 + DCD DefaultISR ;239 + DCD DefaultISR ;240 + DCD DefaultISR ;241 + DCD DefaultISR ;242 + DCD DefaultISR ;243 + DCD DefaultISR ;244 + DCD DefaultISR ;245 + DCD DefaultISR ;246 + DCD DefaultISR ;247 + DCD DefaultISR ;248 + DCD DefaultISR ;249 + DCD DefaultISR ;250 + DCD DefaultISR ;251 + DCD DefaultISR ;252 + DCD DefaultISR ;253 + DCD DefaultISR ;254 + DCD 0xFFFFFFFF ; Reserved for user TRIM value +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +; <h> Flash Configuration +; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset) +; <i> and security information that allows the MCU to restrict access to the FTFL module. +; <h> Backdoor Comparison Key +; <o0> Backdoor Comparison Key 0. <0x0-0xFF:2> +; <o1> Backdoor Comparison Key 1. <0x0-0xFF:2> +; <o2> Backdoor Comparison Key 2. <0x0-0xFF:2> +; <o3> Backdoor Comparison Key 3. <0x0-0xFF:2> +; <o4> Backdoor Comparison Key 4. <0x0-0xFF:2> +; <o5> Backdoor Comparison Key 5. <0x0-0xFF:2> +; <o6> Backdoor Comparison Key 6. <0x0-0xFF:2> +; <o7> Backdoor Comparison Key 7. <0x0-0xFF:2> +BackDoorK0 EQU 0xFF +BackDoorK1 EQU 0xFF +BackDoorK2 EQU 0xFF +BackDoorK3 EQU 0xFF +BackDoorK4 EQU 0xFF +BackDoorK5 EQU 0xFF +BackDoorK6 EQU 0xFF +BackDoorK7 EQU 0xFF +; </h> +; <h> Program flash protection bytes (FPROT) +; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit. +; <i> Each bit protects a 1/32 region of the program flash memory. +; <h> FPROT0 +; <i> Program Flash Region Protect Register 0 +; <i> 1/32 - 8/32 region +; <o.0> FPROT0.0 +; <o.1> FPROT0.1 +; <o.2> FPROT0.2 +; <o.3> FPROT0.3 +; <o.4> FPROT0.4 +; <o.5> FPROT0.5 +; <o.6> FPROT0.6 +; <o.7> FPROT0.7 +nFPROT0 EQU 0x00 +FPROT0 EQU nFPROT0:EOR:0xFF +; </h> +; <h> FPROT1 +; <i> Program Flash Region Protect Register 1 +; <i> 9/32 - 16/32 region +; <o.0> FPROT1.0 +; <o.1> FPROT1.1 +; <o.2> FPROT1.2 +; <o.3> FPROT1.3 +; <o.4> FPROT1.4 +; <o.5> FPROT1.5 +; <o.6> FPROT1.6 +; <o.7> FPROT1.7 +nFPROT1 EQU 0x00 +FPROT1 EQU nFPROT1:EOR:0xFF +; </h> +; <h> FPROT2 +; <i> Program Flash Region Protect Register 2 +; <i> 17/32 - 24/32 region +; <o.0> FPROT2.0 +; <o.1> FPROT2.1 +; <o.2> FPROT2.2 +; <o.3> FPROT2.3 +; <o.4> FPROT2.4 +; <o.5> FPROT2.5 +; <o.6> FPROT2.6 +; <o.7> FPROT2.7 +nFPROT2 EQU 0x00 +FPROT2 EQU nFPROT2:EOR:0xFF +; </h> +; <h> FPROT3 +; <i> Program Flash Region Protect Register 3 +; <i> 25/32 - 32/32 region +; <o.0> FPROT3.0 +; <o.1> FPROT3.1 +; <o.2> FPROT3.2 +; <o.3> FPROT3.3 +; <o.4> FPROT3.4 +; <o.5> FPROT3.5 +; <o.6> FPROT3.6 +; <o.7> FPROT3.7 +nFPROT3 EQU 0x00 +FPROT3 EQU nFPROT3:EOR:0xFF +; </h> +; </h> +; <h> Data flash protection byte (FDPROT) +; <i> Each bit protects a 1/8 region of the data flash memory. +; <i> (Program flash only devices: Reserved) +; <o.0> FDPROT.0 +; <o.1> FDPROT.1 +; <o.2> FDPROT.2 +; <o.3> FDPROT.3 +; <o.4> FDPROT.4 +; <o.5> FDPROT.5 +; <o.6> FDPROT.6 +; <o.7> FDPROT.7 +nFDPROT EQU 0x00 +FDPROT EQU nFDPROT:EOR:0xFF +; </h> +; <h> EEPROM protection byte (FEPROT) +; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM. +; <i> (Program flash only devices: Reserved) +; <o.0> FEPROT.0 +; <o.1> FEPROT.1 +; <o.2> FEPROT.2 +; <o.3> FEPROT.3 +; <o.4> FEPROT.4 +; <o.5> FEPROT.5 +; <o.6> FEPROT.6 +; <o.7> FEPROT.7 +nFEPROT EQU 0x00 +FEPROT EQU nFEPROT:EOR:0xFF +; </h> +; <h> Flash nonvolatile option byte (FOPT) +; <i> Allows the user to customize the operation of the MCU at boot time. +; <o.0> LPBOOT +; <0=> Low-power boot +; <1=> Normal boot +; <o.1> EZPORT_DIS +; <0=> EzPort operation is disabled +; <1=> EzPort operation is enabled +; <o.2> NMI_DIS +; <0=> NMI interrupts are always blocked +; <1=> NMI_b pin/interrupts reset default to enabled +FOPT EQU 0xF9 +; </h> +; <h> Flash security byte (FSEC) +; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", +; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! +; <o.0..1> SEC +; <2=> MCU security status is unsecure +; <3=> MCU security status is secure +; <i> Flash Security +; <o.2..3> FSLACC +; <2=> Freescale factory access denied +; <3=> Freescale factory access granted +; <i> Freescale Failure Analysis Access Code +; <o.4..5> MEEN +; <2=> Mass erase is disabled +; <3=> Mass erase is enabled +; <o.6..7> KEYEN +; <2=> Backdoor key access enabled +; <3=> Backdoor key access disabled +; <i> Backdoor Key Security Enable +FSEC EQU 0xFE +; </h> +; </h> + #if defined(DAPLINK_IF) + AREA |.ARM.__at_0x20400|, CODE, READONLY + #else + AREA |.ARM.__at_0x400 |, CODE, READONLY + #endif + + DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 + DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 + DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 + DCB FSEC , FOPT , FEPROT , FDPROT + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__Vectors + STR R1, [R0] + LDR R0, =SystemInit + BLX R0 + CPSIE i ; Unmask interrupts + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler\ + PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +DMA0_DMA16_IRQHandler\ + PROC + EXPORT DMA0_DMA16_IRQHandler [WEAK] + LDR R0, =DMA0_DMA16_DriverIRQHandler + BX R0 + ENDP + +DMA1_DMA17_IRQHandler\ + PROC + EXPORT DMA1_DMA17_IRQHandler [WEAK] + LDR R0, =DMA1_DMA17_DriverIRQHandler + BX R0 + ENDP + +DMA2_DMA18_IRQHandler\ + PROC + EXPORT DMA2_DMA18_IRQHandler [WEAK] + LDR R0, =DMA2_DMA18_DriverIRQHandler + BX R0 + ENDP + +DMA3_DMA19_IRQHandler\ + PROC + EXPORT DMA3_DMA19_IRQHandler [WEAK] + LDR R0, =DMA3_DMA19_DriverIRQHandler + BX R0 + ENDP + +DMA4_DMA20_IRQHandler\ + PROC + EXPORT DMA4_DMA20_IRQHandler [WEAK] + LDR R0, =DMA4_DMA20_DriverIRQHandler + BX R0 + ENDP + +DMA5_DMA21_IRQHandler\ + PROC + EXPORT DMA5_DMA21_IRQHandler [WEAK] + LDR R0, =DMA5_DMA21_DriverIRQHandler + BX R0 + ENDP + +DMA6_DMA22_IRQHandler\ + PROC + EXPORT DMA6_DMA22_IRQHandler [WEAK] + LDR R0, =DMA6_DMA22_DriverIRQHandler + BX R0 + ENDP + +DMA7_DMA23_IRQHandler\ + PROC + EXPORT DMA7_DMA23_IRQHandler [WEAK] + LDR R0, =DMA7_DMA23_DriverIRQHandler + BX R0 + ENDP + +DMA8_DMA24_IRQHandler\ + PROC + EXPORT DMA8_DMA24_IRQHandler [WEAK] + LDR R0, =DMA8_DMA24_DriverIRQHandler + BX R0 + ENDP + +DMA9_DMA25_IRQHandler\ + PROC + EXPORT DMA9_DMA25_IRQHandler [WEAK] + LDR R0, =DMA9_DMA25_DriverIRQHandler + BX R0 + ENDP + +DMA10_DMA26_IRQHandler\ + PROC + EXPORT DMA10_DMA26_IRQHandler [WEAK] + LDR R0, =DMA10_DMA26_DriverIRQHandler + BX R0 + ENDP + +DMA11_DMA27_IRQHandler\ + PROC + EXPORT DMA11_DMA27_IRQHandler [WEAK] + LDR R0, =DMA11_DMA27_DriverIRQHandler + BX R0 + ENDP + +DMA12_DMA28_IRQHandler\ + PROC + EXPORT DMA12_DMA28_IRQHandler [WEAK] + LDR R0, =DMA12_DMA28_DriverIRQHandler + BX R0 + ENDP + +DMA13_DMA29_IRQHandler\ + PROC + EXPORT DMA13_DMA29_IRQHandler [WEAK] + LDR R0, =DMA13_DMA29_DriverIRQHandler + BX R0 + ENDP + +DMA14_DMA30_IRQHandler\ + PROC + EXPORT DMA14_DMA30_IRQHandler [WEAK] + LDR R0, =DMA14_DMA30_DriverIRQHandler + BX R0 + ENDP + +DMA15_DMA31_IRQHandler\ + PROC + EXPORT DMA15_DMA31_IRQHandler [WEAK] + LDR R0, =DMA15_DMA31_DriverIRQHandler + BX R0 + ENDP + +DMA_Error_IRQHandler\ + PROC + EXPORT DMA_Error_IRQHandler [WEAK] + LDR R0, =DMA_Error_DriverIRQHandler + BX R0 + ENDP + +I2C0_IRQHandler\ + PROC + EXPORT I2C0_IRQHandler [WEAK] + LDR R0, =I2C0_DriverIRQHandler + BX R0 + ENDP + +I2C1_IRQHandler\ + PROC + EXPORT I2C1_IRQHandler [WEAK] + LDR R0, =I2C1_DriverIRQHandler + BX R0 + ENDP + +SPI0_IRQHandler\ + PROC + EXPORT SPI0_IRQHandler [WEAK] + LDR R0, =SPI0_DriverIRQHandler + BX R0 + ENDP + +SPI1_IRQHandler\ + PROC + EXPORT SPI1_IRQHandler [WEAK] + LDR R0, =SPI1_DriverIRQHandler + BX R0 + ENDP + +I2S0_Tx_IRQHandler\ + PROC + EXPORT I2S0_Tx_IRQHandler [WEAK] + LDR R0, =I2S0_Tx_DriverIRQHandler + BX R0 + ENDP + +I2S0_Rx_IRQHandler\ + PROC + EXPORT I2S0_Rx_IRQHandler [WEAK] + LDR R0, =I2S0_Rx_DriverIRQHandler + BX R0 + ENDP + +UART0_RX_TX_IRQHandler\ + PROC + EXPORT UART0_RX_TX_IRQHandler [WEAK] + LDR R0, =UART0_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART0_ERR_IRQHandler\ + PROC + EXPORT UART0_ERR_IRQHandler [WEAK] + LDR R0, =UART0_ERR_DriverIRQHandler + BX R0 + ENDP + +UART1_RX_TX_IRQHandler\ + PROC + EXPORT UART1_RX_TX_IRQHandler [WEAK] + LDR R0, =UART1_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART1_ERR_IRQHandler\ + PROC + EXPORT UART1_ERR_IRQHandler [WEAK] + LDR R0, =UART1_ERR_DriverIRQHandler + BX R0 + ENDP + +UART2_RX_TX_IRQHandler\ + PROC + EXPORT UART2_RX_TX_IRQHandler [WEAK] + LDR R0, =UART2_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART2_ERR_IRQHandler\ + PROC + EXPORT UART2_ERR_IRQHandler [WEAK] + LDR R0, =UART2_ERR_DriverIRQHandler + BX R0 + ENDP + +UART3_RX_TX_IRQHandler\ + PROC + EXPORT UART3_RX_TX_IRQHandler [WEAK] + LDR R0, =UART3_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART3_ERR_IRQHandler\ + PROC + EXPORT UART3_ERR_IRQHandler [WEAK] + LDR R0, =UART3_ERR_DriverIRQHandler + BX R0 + ENDP + +SPI2_IRQHandler\ + PROC + EXPORT SPI2_IRQHandler [WEAK] + LDR R0, =SPI2_DriverIRQHandler + BX R0 + ENDP + +UART4_RX_TX_IRQHandler\ + PROC + EXPORT UART4_RX_TX_IRQHandler [WEAK] + LDR R0, =UART4_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART4_ERR_IRQHandler\ + PROC + EXPORT UART4_ERR_IRQHandler [WEAK] + LDR R0, =UART4_ERR_DriverIRQHandler + BX R0 + ENDP + +I2C2_IRQHandler\ + PROC + EXPORT I2C2_IRQHandler [WEAK] + LDR R0, =I2C2_DriverIRQHandler + BX R0 + ENDP + +CAN0_ORed_Message_buffer_IRQHandler\ + PROC + EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +CAN0_Bus_Off_IRQHandler\ + PROC + EXPORT CAN0_Bus_Off_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +CAN0_Error_IRQHandler\ + PROC + EXPORT CAN0_Error_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +CAN0_Tx_Warning_IRQHandler\ + PROC + EXPORT CAN0_Tx_Warning_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +CAN0_Rx_Warning_IRQHandler\ + PROC + EXPORT CAN0_Rx_Warning_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +CAN0_Wake_Up_IRQHandler\ + PROC + EXPORT CAN0_Wake_Up_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +SDHC_IRQHandler\ + PROC + EXPORT SDHC_IRQHandler [WEAK] + LDR R0, =SDHC_DriverIRQHandler + BX R0 + ENDP + +LPUART0_IRQHandler\ + PROC + EXPORT LPUART0_IRQHandler [WEAK] + LDR R0, =LPUART0_DriverIRQHandler + BX R0 + ENDP + +I2C3_IRQHandler\ + PROC + EXPORT I2C3_IRQHandler [WEAK] + LDR R0, =I2C3_DriverIRQHandler + BX R0 + ENDP + +CAN1_ORed_Message_buffer_IRQHandler\ + PROC + EXPORT CAN1_ORed_Message_buffer_IRQHandler [WEAK] + LDR R0, =CAN1_DriverIRQHandler + BX R0 + ENDP + +CAN1_Bus_Off_IRQHandler\ + PROC + EXPORT CAN1_Bus_Off_IRQHandler [WEAK] + LDR R0, =CAN1_DriverIRQHandler + BX R0 + ENDP + +CAN1_Error_IRQHandler\ + PROC + EXPORT CAN1_Error_IRQHandler [WEAK] + LDR R0, =CAN1_DriverIRQHandler + BX R0 + ENDP + +CAN1_Tx_Warning_IRQHandler\ + PROC + EXPORT CAN1_Tx_Warning_IRQHandler [WEAK] + LDR R0, =CAN1_DriverIRQHandler + BX R0 + ENDP + +CAN1_Rx_Warning_IRQHandler\ + PROC + EXPORT CAN1_Rx_Warning_IRQHandler [WEAK] + LDR R0, =CAN1_DriverIRQHandler + BX R0 + ENDP + +CAN1_Wake_Up_IRQHandler\ + PROC + EXPORT CAN1_Wake_Up_IRQHandler [WEAK] + LDR R0, =CAN1_DriverIRQHandler + BX R0 + ENDP + +Default_Handler\ + PROC + EXPORT DMA0_DMA16_DriverIRQHandler [WEAK] + EXPORT DMA1_DMA17_DriverIRQHandler [WEAK] + EXPORT DMA2_DMA18_DriverIRQHandler [WEAK] + EXPORT DMA3_DMA19_DriverIRQHandler [WEAK] + EXPORT DMA4_DMA20_DriverIRQHandler [WEAK] + EXPORT DMA5_DMA21_DriverIRQHandler [WEAK] + EXPORT DMA6_DMA22_DriverIRQHandler [WEAK] + EXPORT DMA7_DMA23_DriverIRQHandler [WEAK] + EXPORT DMA8_DMA24_DriverIRQHandler [WEAK] + EXPORT DMA9_DMA25_DriverIRQHandler [WEAK] + EXPORT DMA10_DMA26_DriverIRQHandler [WEAK] + EXPORT DMA11_DMA27_DriverIRQHandler [WEAK] + EXPORT DMA12_DMA28_DriverIRQHandler [WEAK] + EXPORT DMA13_DMA29_DriverIRQHandler [WEAK] + EXPORT DMA14_DMA30_DriverIRQHandler [WEAK] + EXPORT DMA15_DMA31_DriverIRQHandler [WEAK] + EXPORT DMA_Error_DriverIRQHandler [WEAK] + EXPORT MCM_IRQHandler [WEAK] + EXPORT FTFE_IRQHandler [WEAK] + EXPORT Read_Collision_IRQHandler [WEAK] + EXPORT LVD_LVW_IRQHandler [WEAK] + EXPORT LLWU_IRQHandler [WEAK] + EXPORT WDOG_EWM_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT I2C0_DriverIRQHandler [WEAK] + EXPORT I2C1_DriverIRQHandler [WEAK] + EXPORT SPI0_DriverIRQHandler [WEAK] + EXPORT SPI1_DriverIRQHandler [WEAK] + EXPORT I2S0_Tx_DriverIRQHandler [WEAK] + EXPORT I2S0_Rx_DriverIRQHandler [WEAK] + EXPORT Reserved46_IRQHandler [WEAK] + EXPORT UART0_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART0_ERR_DriverIRQHandler [WEAK] + EXPORT UART1_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART1_ERR_DriverIRQHandler [WEAK] + EXPORT UART2_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART2_ERR_DriverIRQHandler [WEAK] + EXPORT UART3_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART3_ERR_DriverIRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT FTM0_IRQHandler [WEAK] + EXPORT FTM1_IRQHandler [WEAK] + EXPORT FTM2_IRQHandler [WEAK] + EXPORT CMT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT RTC_Seconds_IRQHandler [WEAK] + EXPORT PIT0_IRQHandler [WEAK] + EXPORT PIT1_IRQHandler [WEAK] + EXPORT PIT2_IRQHandler [WEAK] + EXPORT PIT3_IRQHandler [WEAK] + EXPORT PDB0_IRQHandler [WEAK] + EXPORT USB0_IRQHandler [WEAK] + EXPORT USBDCD_IRQHandler [WEAK] + EXPORT Reserved71_IRQHandler [WEAK] + EXPORT DAC0_IRQHandler [WEAK] + EXPORT MCG_IRQHandler [WEAK] + EXPORT LPTMR0_IRQHandler [WEAK] + EXPORT PORTA_IRQHandler [WEAK] + EXPORT PORTB_IRQHandler [WEAK] + EXPORT PORTC_IRQHandler [WEAK] + EXPORT PORTD_IRQHandler [WEAK] + EXPORT PORTE_IRQHandler [WEAK] + EXPORT SWI_IRQHandler [WEAK] + EXPORT SPI2_DriverIRQHandler [WEAK] + EXPORT UART4_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART4_ERR_DriverIRQHandler [WEAK] + EXPORT Reserved84_IRQHandler [WEAK] + EXPORT Reserved85_IRQHandler [WEAK] + EXPORT CMP2_IRQHandler [WEAK] + EXPORT FTM3_IRQHandler [WEAK] + EXPORT DAC1_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT I2C2_DriverIRQHandler [WEAK] + EXPORT CAN0_DriverIRQHandler [WEAK] + EXPORT SDHC_DriverIRQHandler [WEAK] + EXPORT Reserved98_IRQHandler [WEAK] + EXPORT Reserved99_IRQHandler [WEAK] + EXPORT Reserved100_IRQHandler [WEAK] + EXPORT Reserved101_IRQHandler [WEAK] + EXPORT LPUART0_DriverIRQHandler [WEAK] + EXPORT TSI0_IRQHandler [WEAK] + EXPORT TPM1_IRQHandler [WEAK] + EXPORT TPM2_IRQHandler [WEAK] + EXPORT USBHSDCD_IRQHandler [WEAK] + EXPORT I2C3_DriverIRQHandler [WEAK] + EXPORT CMP3_IRQHandler [WEAK] + EXPORT USBHS_IRQHandler [WEAK] + EXPORT CAN1_DriverIRQHandler [WEAK] + EXPORT DefaultISR [WEAK] +DMA0_DMA16_DriverIRQHandler +DMA1_DMA17_DriverIRQHandler +DMA2_DMA18_DriverIRQHandler +DMA3_DMA19_DriverIRQHandler +DMA4_DMA20_DriverIRQHandler +DMA5_DMA21_DriverIRQHandler +DMA6_DMA22_DriverIRQHandler +DMA7_DMA23_DriverIRQHandler +DMA8_DMA24_DriverIRQHandler +DMA9_DMA25_DriverIRQHandler +DMA10_DMA26_DriverIRQHandler +DMA11_DMA27_DriverIRQHandler +DMA12_DMA28_DriverIRQHandler +DMA13_DMA29_DriverIRQHandler +DMA14_DMA30_DriverIRQHandler +DMA15_DMA31_DriverIRQHandler +DMA_Error_DriverIRQHandler +MCM_IRQHandler +FTFE_IRQHandler +Read_Collision_IRQHandler +LVD_LVW_IRQHandler +LLWU_IRQHandler +WDOG_EWM_IRQHandler +RNG_IRQHandler +I2C0_DriverIRQHandler +I2C1_DriverIRQHandler +SPI0_DriverIRQHandler +SPI1_DriverIRQHandler +I2S0_Tx_DriverIRQHandler +I2S0_Rx_DriverIRQHandler +Reserved46_IRQHandler +UART0_RX_TX_DriverIRQHandler +UART0_ERR_DriverIRQHandler +UART1_RX_TX_DriverIRQHandler +UART1_ERR_DriverIRQHandler +UART2_RX_TX_DriverIRQHandler +UART2_ERR_DriverIRQHandler +UART3_RX_TX_DriverIRQHandler +UART3_ERR_DriverIRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +FTM0_IRQHandler +FTM1_IRQHandler +FTM2_IRQHandler +CMT_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT0_IRQHandler +PIT1_IRQHandler +PIT2_IRQHandler +PIT3_IRQHandler +PDB0_IRQHandler +USB0_IRQHandler +USBDCD_IRQHandler +Reserved71_IRQHandler +DAC0_IRQHandler +MCG_IRQHandler +LPTMR0_IRQHandler +PORTA_IRQHandler +PORTB_IRQHandler +PORTC_IRQHandler +PORTD_IRQHandler +PORTE_IRQHandler +SWI_IRQHandler +SPI2_DriverIRQHandler +UART4_RX_TX_DriverIRQHandler +UART4_ERR_DriverIRQHandler +Reserved84_IRQHandler +Reserved85_IRQHandler +CMP2_IRQHandler +FTM3_IRQHandler +DAC1_IRQHandler +ADC1_IRQHandler +I2C2_DriverIRQHandler +CAN0_DriverIRQHandler +SDHC_DriverIRQHandler +Reserved98_IRQHandler +Reserved99_IRQHandler +Reserved100_IRQHandler +Reserved101_IRQHandler +LPUART0_DriverIRQHandler +TSI0_IRQHandler +TPM1_IRQHandler +TPM2_IRQHandler +USBHSDCD_IRQHandler +I2C3_DriverIRQHandler +CMP3_IRQHandler +USBHS_IRQHandler +CAN1_DriverIRQHandler +DefaultISR + B DefaultISR + ENDP + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/daplink_addr.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/freescale/k26f/daplink_addr.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,82 @@ +/** + * @file daplink_addr.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef DAPLINK_ADDR_H +#define DAPLINK_ADDR_H + +/* Device sizes */ + +#define DAPLINK_ROM_START 0x00000000 +#define DAPLINK_ROM_SIZE 0x00040000 // Intentionally set to only 256 kB of total 2 MB. + +#define DAPLINK_RAM_START 0x1fff0000 +#define DAPLINK_RAM_SIZE 0x00040000 + +/* ROM sizes */ + +#define DAPLINK_ROM_BL_START 0x00000000 +#define DAPLINK_ROM_BL_SIZE 0x00010000 // 64 kB bootloader + +#define DAPLINK_ROM_CONFIG_ADMIN_START 0x00010000 +#define DAPLINK_ROM_CONFIG_ADMIN_SIZE 0x00000000 + +#define DAPLINK_ROM_IF_START 0x00010000 +#define DAPLINK_ROM_IF_SIZE 0x0002f000 // 192 kB interface + +#define DAPLINK_ROM_CONFIG_USER_START 0x0003f000 +#define DAPLINK_ROM_CONFIG_USER_SIZE 0x00001000 // 4 kB user config + +/* RAM sizes */ + +#define DAPLINK_RAM_APP_START 0x1fff0000 +#define DAPLINK_RAM_APP_SIZE 0x0003ff00 + +#define DAPLINK_RAM_SHARED_START 0x2002ff00 +#define DAPLINK_RAM_SHARED_SIZE 0x00000100 + +/* Flash Programming Info */ + +#define DAPLINK_SECTOR_SIZE 0x00001000 +#define DAPLINK_MIN_WRITE_SIZE 0x00000100 + +/* Current build */ + +#if defined(DAPLINK_BL) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_BL_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_IF_SIZE + +#elif defined(DAPLINK_IF) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_IF_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_BL_SIZE + +#else + +#error "Build must be either bootloader or interface" + +#endif + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/fsl_dmamux.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/fsl_dmamux.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_dmamux.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.dmamux"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get instance number for DMAMUX.
+ *
+ * @param base DMAMUX peripheral base address.
+ */
+static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Array to map DMAMUX instance number to base pointer. */
+static DMAMUX_Type *const s_dmamuxBases[] = DMAMUX_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Array to map DMAMUX instance number to clock name. */
+static const clock_ip_name_t s_dmamuxClockName[] = DMAMUX_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base)
+{
+ uint32_t instance;
+
+ /* Find the instance index from base address mappings. */
+ for (instance = 0; instance < ARRAY_SIZE(s_dmamuxBases); instance++)
+ {
+ if (s_dmamuxBases[instance] == base)
+ {
+ break;
+ }
+ }
+
+ assert(instance < ARRAY_SIZE(s_dmamuxBases));
+
+ return instance;
+}
+
+/*!
+ * brief Initializes the DMAMUX peripheral.
+ *
+ * This function ungates the DMAMUX clock.
+ *
+ * param base DMAMUX peripheral base address.
+ *
+ */
+void DMAMUX_Init(DMAMUX_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ CLOCK_EnableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Deinitializes the DMAMUX peripheral.
+ *
+ * This function gates the DMAMUX clock.
+ *
+ * param base DMAMUX peripheral base address.
+ */
+void DMAMUX_Deinit(DMAMUX_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ CLOCK_DisableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/fsl_dmamux.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/fsl_dmamux.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_DMAMUX_H_
+#define _FSL_DMAMUX_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup dmamux
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief DMAMUX driver version 2.0.2. */
+#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name DMAMUX Initialization and de-initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the DMAMUX peripheral.
+ *
+ * This function ungates the DMAMUX clock.
+ *
+ * @param base DMAMUX peripheral base address.
+ *
+ */
+void DMAMUX_Init(DMAMUX_Type *base);
+
+/*!
+ * @brief Deinitializes the DMAMUX peripheral.
+ *
+ * This function gates the DMAMUX clock.
+ *
+ * @param base DMAMUX peripheral base address.
+ */
+void DMAMUX_Deinit(DMAMUX_Type *base);
+
+/* @} */
+/*!
+ * @name DMAMUX Channel Operation
+ * @{
+ */
+
+/*!
+ * @brief Enables the DMAMUX channel.
+ *
+ * This function enables the DMAMUX channel.
+ *
+ * @param base DMAMUX peripheral base address.
+ * @param channel DMAMUX channel number.
+ */
+static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+ base->CHCFG[channel] |= DMAMUX_CHCFG_ENBL_MASK;
+}
+
+/*!
+ * @brief Disables the DMAMUX channel.
+ *
+ * This function disables the DMAMUX channel.
+ *
+ * @note The user must disable the DMAMUX channel before configuring it.
+ * @param base DMAMUX peripheral base address.
+ * @param channel DMAMUX channel number.
+ */
+static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+ base->CHCFG[channel] &= ~DMAMUX_CHCFG_ENBL_MASK;
+}
+
+/*!
+ * @brief Configures the DMAMUX channel source.
+ *
+ * @param base DMAMUX peripheral base address.
+ * @param channel DMAMUX channel number.
+ * @param source Channel source, which is used to trigger the DMA transfer.
+ */
+static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint32_t source)
+{
+ assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+ base->CHCFG[channel] = ((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source));
+}
+
+#if defined(FSL_FEATURE_DMAMUX_HAS_TRIG) && FSL_FEATURE_DMAMUX_HAS_TRIG > 0U
+/*!
+ * @brief Enables the DMAMUX period trigger.
+ *
+ * This function enables the DMAMUX period trigger feature.
+ *
+ * @param base DMAMUX peripheral base address.
+ * @param channel DMAMUX channel number.
+ */
+static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+ base->CHCFG[channel] |= DMAMUX_CHCFG_TRIG_MASK;
+}
+
+/*!
+ * @brief Disables the DMAMUX period trigger.
+ *
+ * This function disables the DMAMUX period trigger.
+ *
+ * @param base DMAMUX peripheral base address.
+ * @param channel DMAMUX channel number.
+ */
+static inline void DMAMUX_DisablePeriodTrigger(DMAMUX_Type *base, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+ base->CHCFG[channel] &= ~DMAMUX_CHCFG_TRIG_MASK;
+}
+#endif /* FSL_FEATURE_DMAMUX_HAS_TRIG */
+
+#if (defined(FSL_FEATURE_DMAMUX_HAS_A_ON) && FSL_FEATURE_DMAMUX_HAS_A_ON)
+/*!
+ * @brief Enables the DMA channel to be always ON.
+ *
+ * This function enables the DMAMUX channel always ON feature.
+ *
+ * @param base DMAMUX peripheral base address.
+ * @param channel DMAMUX channel number.
+ * @param enable Switcher of the always ON feature. "true" means enabled, "false" means disabled.
+ */
+static inline void DMAMUX_EnableAlwaysOn(DMAMUX_Type *base, uint32_t channel, bool enable)
+{
+ assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+ if (enable)
+ {
+ base->CHCFG[channel] |= DMAMUX_CHCFG_A_ON_MASK;
+ }
+ else
+ {
+ base->CHCFG[channel] &= ~DMAMUX_CHCFG_A_ON_MASK;
+ }
+}
+#endif /* FSL_FEATURE_DMAMUX_HAS_A_ON */
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/* @} */
+
+#endif /* _FSL_DMAMUX_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/fsl_edma.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/fsl_edma.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,2675 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_edma.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.edma"
+#endif
+
+#define EDMA_TRANSFER_ENABLED_MASK 0x80U
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get instance number for EDMA.
+ *
+ * @param base EDMA peripheral base address.
+ */
+static uint32_t EDMA_GetInstance(DMA_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Array to map EDMA instance number to base pointer. */
+static DMA_Type *const s_edmaBases[] = DMA_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Array to map EDMA instance number to clock name. */
+static const clock_ip_name_t s_edmaClockName[] = EDMA_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*! @brief Array to map EDMA instance number to IRQ number. */
+static const IRQn_Type s_edmaIRQNumber[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = DMA_CHN_IRQS;
+
+/*! @brief Pointers to transfer handle for each EDMA channel. */
+static edma_handle_t *s_EDMAHandle[FSL_FEATURE_EDMA_MODULE_CHANNEL * FSL_FEATURE_SOC_EDMA_COUNT];
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t EDMA_GetInstance(DMA_Type *base)
+{
+ uint32_t instance;
+
+ /* Find the instance index from base address mappings. */
+ for (instance = 0; instance < ARRAY_SIZE(s_edmaBases); instance++)
+ {
+ if (s_edmaBases[instance] == base)
+ {
+ break;
+ }
+ }
+
+ assert(instance < ARRAY_SIZE(s_edmaBases));
+
+ return instance;
+}
+
+/*!
+ * brief Push content of TCD structure into hardware TCD register.
+ *
+ * param base EDMA peripheral base address.
+ * param channel EDMA channel number.
+ * param tcd Point to TCD structure.
+ */
+void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ assert(tcd != NULL);
+ assert(((uint32_t)tcd & 0x1FU) == 0);
+
+ /* Push tcd into hardware TCD register */
+ base->TCD[channel].SADDR = tcd->SADDR;
+ base->TCD[channel].SOFF = tcd->SOFF;
+ base->TCD[channel].ATTR = tcd->ATTR;
+ base->TCD[channel].NBYTES_MLNO = tcd->NBYTES;
+ base->TCD[channel].SLAST = tcd->SLAST;
+ base->TCD[channel].DADDR = tcd->DADDR;
+ base->TCD[channel].DOFF = tcd->DOFF;
+ base->TCD[channel].CITER_ELINKNO = tcd->CITER;
+ base->TCD[channel].DLAST_SGA = tcd->DLAST_SGA;
+ /* Clear DONE bit first, otherwise ESG cannot be set */
+ base->TCD[channel].CSR = 0;
+ base->TCD[channel].CSR = tcd->CSR;
+ base->TCD[channel].BITER_ELINKNO = tcd->BITER;
+}
+
+/*!
+ * brief Initializes the eDMA peripheral.
+ *
+ * This function ungates the eDMA clock and configures the eDMA peripheral according
+ * to the configuration structure.
+ *
+ * param base eDMA peripheral base address.
+ * param config A pointer to the configuration structure, see "edma_config_t".
+ * note This function enables the minor loop map feature.
+ */
+void EDMA_Init(DMA_Type *base, const edma_config_t *config)
+{
+ assert(config != NULL);
+
+ uint32_t tmpreg;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Ungate EDMA peripheral clock */
+ CLOCK_EnableClock(s_edmaClockName[EDMA_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+ /* clear all the enabled request, status to make sure EDMA status is in normal condition */
+ base->ERQ = 0U;
+ base->INT = 0xFFFFFFFFU;
+ base->ERR = 0xFFFFFFFFU;
+ /* Configure EDMA peripheral according to the configuration structure. */
+ tmpreg = base->CR;
+ tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK);
+ tmpreg |= (DMA_CR_ERCA(config->enableRoundRobinArbitration) | DMA_CR_HOE(config->enableHaltOnError) |
+ DMA_CR_CLM(config->enableContinuousLinkMode) | DMA_CR_EDBG(config->enableDebugMode) | DMA_CR_EMLM(true));
+ base->CR = tmpreg;
+}
+
+/*!
+ * brief Deinitializes the eDMA peripheral.
+ *
+ * This function gates the eDMA clock.
+ *
+ * param base eDMA peripheral base address.
+ */
+void EDMA_Deinit(DMA_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Gate EDMA peripheral clock */
+ CLOCK_DisableClock(s_edmaClockName[EDMA_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Gets the eDMA default configuration structure.
+ *
+ * This function sets the configuration structure to default values.
+ * The default configuration is set to the following values.
+ * code
+ * config.enableContinuousLinkMode = false;
+ * config.enableHaltOnError = true;
+ * config.enableRoundRobinArbitration = false;
+ * config.enableDebugMode = false;
+ * endcode
+ *
+ * param config A pointer to the eDMA configuration structure.
+ */
+void EDMA_GetDefaultConfig(edma_config_t *config)
+{
+ assert(config != NULL);
+
+ /* Initializes the configure structure to zero. */
+ memset(config, 0, sizeof(*config));
+
+ config->enableRoundRobinArbitration = false;
+ config->enableHaltOnError = true;
+ config->enableContinuousLinkMode = false;
+ config->enableDebugMode = false;
+}
+
+/*!
+ * brief Sets all TCD registers to default values.
+ *
+ * This function sets TCD registers for this channel to default values.
+ *
+ * param base eDMA peripheral base address.
+ * param channel eDMA channel number.
+ * note This function must not be called while the channel transfer is ongoing
+ * or it causes unpredictable results.
+ * note This function enables the auto stop request feature.
+ */
+void EDMA_ResetChannel(DMA_Type *base, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+ EDMA_TcdReset((edma_tcd_t *)&base->TCD[channel]);
+}
+
+/*!
+ * brief Configures the eDMA transfer attribute.
+ *
+ * This function configures the transfer attribute, including source address, destination address,
+ * transfer size, address offset, and so on. It also configures the scatter gather feature if the
+ * user supplies the TCD address.
+ * Example:
+ * code
+ * edma_transfer_t config;
+ * edma_tcd_t tcd;
+ * config.srcAddr = ..;
+ * config.destAddr = ..;
+ * ...
+ * EDMA_SetTransferConfig(DMA0, channel, &config, &stcd);
+ * endcode
+ *
+ * param base eDMA peripheral base address.
+ * param channel eDMA channel number.
+ * param config Pointer to eDMA transfer configuration structure.
+ * param nextTcd Point to TCD structure. It can be NULL if users
+ * do not want to enable scatter/gather feature.
+ * note If nextTcd is not NULL, it means scatter gather feature is enabled
+ * and DREQ bit is cleared in the previous transfer configuration, which
+ * is set in the eDMA_ResetChannel.
+ */
+void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ assert(config != NULL);
+ assert(((uint32_t)nextTcd & 0x1FU) == 0);
+
+ EDMA_TcdSetTransferConfig((edma_tcd_t *)&base->TCD[channel], config, nextTcd);
+}
+
+/*!
+ * brief Configures the eDMA minor offset feature.
+ *
+ * The minor offset means that the signed-extended value is added to the source address or destination
+ * address after each minor loop.
+ *
+ * param base eDMA peripheral base address.
+ * param channel eDMA channel number.
+ * param config A pointer to the minor offset configuration structure.
+ */
+void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ assert(config != NULL);
+
+ uint32_t tmpreg;
+
+ tmpreg = base->TCD[channel].NBYTES_MLOFFYES;
+ tmpreg &= ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK);
+ tmpreg |=
+ (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) |
+ DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset));
+ base->TCD[channel].NBYTES_MLOFFYES = tmpreg;
+}
+
+/*!
+ * brief Sets the channel link for the eDMA transfer.
+ *
+ * This function configures either the minor link or the major link mode. The minor link means that the channel link is
+ * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is
+ * exhausted.
+ *
+ * param base eDMA peripheral base address.
+ * param channel eDMA channel number.
+ * param type A channel link type, which can be one of the following:
+ * arg kEDMA_LinkNone
+ * arg kEDMA_MinorLink
+ * arg kEDMA_MajorLink
+ * param linkedChannel The linked channel number.
+ * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
+ */
+void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+ EDMA_TcdSetChannelLink((edma_tcd_t *)&base->TCD[channel], type, linkedChannel);
+}
+
+/*!
+ * brief Sets the bandwidth for the eDMA transfer.
+ *
+ * Because the eDMA processes the minor loop, it continuously generates read/write sequences
+ * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of
+ * each read/write access to control the bus request bandwidth seen by the crossbar switch.
+ *
+ * param base eDMA peripheral base address.
+ * param channel eDMA channel number.
+ * param bandWidth A bandwidth setting, which can be one of the following:
+ * arg kEDMABandwidthStallNone
+ * arg kEDMABandwidthStall4Cycle
+ * arg kEDMABandwidthStall8Cycle
+ */
+void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+ base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth);
+}
+
+/*!
+ * brief Sets the source modulo and the destination modulo for the eDMA transfer.
+ *
+ * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
+ * calculation is performed or the original register value. It provides the ability to implement a circular data
+ * queue easily.
+ *
+ * param base eDMA peripheral base address.
+ * param channel eDMA channel number.
+ * param srcModulo A source modulo value.
+ * param destModulo A destination modulo value.
+ */
+void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+ uint32_t tmpreg;
+
+ tmpreg = base->TCD[channel].ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK));
+ base->TCD[channel].ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo);
+}
+
+/*!
+ * brief Enables the interrupt source for the eDMA transfer.
+ *
+ * param base eDMA peripheral base address.
+ * param channel eDMA channel number.
+ * param mask The mask of interrupt source to be set. Users need to use
+ * the defined edma_interrupt_enable_t type.
+ */
+void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+ /* Enable error interrupt */
+ if (mask & kEDMA_ErrorInterruptEnable)
+ {
+ base->EEI |= (0x1U << channel);
+ }
+
+ /* Enable Major interrupt */
+ if (mask & kEDMA_MajorInterruptEnable)
+ {
+ base->TCD[channel].CSR |= DMA_CSR_INTMAJOR_MASK;
+ }
+
+ /* Enable Half major interrupt */
+ if (mask & kEDMA_HalfInterruptEnable)
+ {
+ base->TCD[channel].CSR |= DMA_CSR_INTHALF_MASK;
+ }
+}
+
+/*!
+ * brief Disables the interrupt source for the eDMA transfer.
+ *
+ * param base eDMA peripheral base address.
+ * param channel eDMA channel number.
+ * param mask The mask of the interrupt source to be set. Use
+ * the defined edma_interrupt_enable_t type.
+ */
+void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+ /* Disable error interrupt */
+ if (mask & kEDMA_ErrorInterruptEnable)
+ {
+ base->EEI &= ~(0x1U << channel);
+ }
+
+ /* Disable Major interrupt */
+ if (mask & kEDMA_MajorInterruptEnable)
+ {
+ base->TCD[channel].CSR &= ~DMA_CSR_INTMAJOR_MASK;
+ }
+
+ /* Disable Half major interrupt */
+ if (mask & kEDMA_HalfInterruptEnable)
+ {
+ base->TCD[channel].CSR &= ~DMA_CSR_INTHALF_MASK;
+ }
+}
+
+/*!
+ * brief Sets all fields to default values for the TCD structure.
+ *
+ * This function sets all fields for this TCD structure to default value.
+ *
+ * param tcd Pointer to the TCD structure.
+ * note This function enables the auto stop request feature.
+ */
+void EDMA_TcdReset(edma_tcd_t *tcd)
+{
+ assert(tcd != NULL);
+ assert(((uint32_t)tcd & 0x1FU) == 0);
+
+ /* Reset channel TCD */
+ tcd->SADDR = 0U;
+ tcd->SOFF = 0U;
+ tcd->ATTR = 0U;
+ tcd->NBYTES = 0U;
+ tcd->SLAST = 0U;
+ tcd->DADDR = 0U;
+ tcd->DOFF = 0U;
+ tcd->CITER = 0U;
+ tcd->DLAST_SGA = 0U;
+ /* Enable auto disable request feature */
+ tcd->CSR = DMA_CSR_DREQ(true);
+ tcd->BITER = 0U;
+}
+
+/*!
+ * brief Configures the eDMA TCD transfer attribute.
+ *
+ * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers.
+ * The STCD is used in the scatter-gather mode.
+ * This function configures the TCD transfer attribute, including source address, destination address,
+ * transfer size, address offset, and so on. It also configures the scatter gather feature if the
+ * user supplies the next TCD address.
+ * Example:
+ * code
+ * edma_transfer_t config = {
+ * ...
+ * }
+ * edma_tcd_t tcd __aligned(32);
+ * edma_tcd_t nextTcd __aligned(32);
+ * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);
+ * endcode
+ *
+ * param tcd Pointer to the TCD structure.
+ * param config Pointer to eDMA transfer configuration structure.
+ * param nextTcd Pointer to the next TCD structure. It can be NULL if users
+ * do not want to enable scatter/gather feature.
+ * note TCD address should be 32 bytes aligned or it causes an eDMA error.
+ * note If the nextTcd is not NULL, the scatter gather feature is enabled
+ * and DREQ bit is cleared in the previous transfer configuration, which
+ * is set in the EDMA_TcdReset.
+ */
+void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)
+{
+ assert(tcd != NULL);
+ assert(((uint32_t)tcd & 0x1FU) == 0);
+ assert(config != NULL);
+ assert(((uint32_t)nextTcd & 0x1FU) == 0);
+
+ /* source address */
+ tcd->SADDR = config->srcAddr;
+ /* destination address */
+ tcd->DADDR = config->destAddr;
+ /* Source data and destination data transfer size */
+ tcd->ATTR = DMA_ATTR_SSIZE(config->srcTransferSize) | DMA_ATTR_DSIZE(config->destTransferSize);
+ /* Source address signed offset */
+ tcd->SOFF = config->srcOffset;
+ /* Destination address signed offset */
+ tcd->DOFF = config->destOffset;
+ /* Minor byte transfer count */
+ tcd->NBYTES = config->minorLoopBytes;
+ /* Current major iteration count */
+ tcd->CITER = config->majorLoopCounts;
+ /* Starting major iteration count */
+ tcd->BITER = config->majorLoopCounts;
+ /* Enable scatter/gather processing */
+ if (nextTcd != NULL)
+ {
+ tcd->DLAST_SGA = (uint32_t)nextTcd;
+ /*
+ Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig,
+ user must call EDMA_TcdReset or EDMA_ResetChannel which will set
+ DREQ, so must use "|" or "&" rather than "=".
+
+ Clear the DREQ bit because scatter gather has been enabled, so the
+ previous transfer is not the last transfer, and channel request should
+ be enabled at the next transfer(the next TCD).
+ */
+ tcd->CSR = (tcd->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK;
+ }
+}
+
+/*!
+ * brief Configures the eDMA TCD minor offset feature.
+ *
+ * A minor offset is a signed-extended value added to the source address or a destination
+ * address after each minor loop.
+ *
+ * param tcd A point to the TCD structure.
+ * param config A pointer to the minor offset configuration structure.
+ */
+void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config)
+{
+ assert(tcd != NULL);
+ assert(((uint32_t)tcd & 0x1FU) == 0);
+
+ uint32_t tmpreg;
+
+ tmpreg = tcd->NBYTES &
+ ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK);
+ tmpreg |=
+ (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) |
+ DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset));
+ tcd->NBYTES = tmpreg;
+}
+
+/*!
+ * brief Sets the channel link for the eDMA TCD.
+ *
+ * This function configures either a minor link or a major link. The minor link means the channel link is
+ * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is
+ * exhausted.
+ *
+ * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
+ * param tcd Point to the TCD structure.
+ * param type Channel link type, it can be one of:
+ * arg kEDMA_LinkNone
+ * arg kEDMA_MinorLink
+ * arg kEDMA_MajorLink
+ * param linkedChannel The linked channel number.
+ */
+void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)
+{
+ assert(tcd != NULL);
+ assert(((uint32_t)tcd & 0x1FU) == 0);
+ assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+ if (type == kEDMA_MinorLink) /* Minor link config */
+ {
+ uint32_t tmpreg;
+
+ /* Enable minor link */
+ tcd->CITER |= DMA_CITER_ELINKYES_ELINK_MASK;
+ tcd->BITER |= DMA_BITER_ELINKYES_ELINK_MASK;
+ /* Set linked channel */
+ tmpreg = tcd->CITER & (~DMA_CITER_ELINKYES_LINKCH_MASK);
+ tmpreg |= DMA_CITER_ELINKYES_LINKCH(linkedChannel);
+ tcd->CITER = tmpreg;
+ tmpreg = tcd->BITER & (~DMA_BITER_ELINKYES_LINKCH_MASK);
+ tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel);
+ tcd->BITER = tmpreg;
+ }
+ else if (type == kEDMA_MajorLink) /* Major link config */
+ {
+ uint32_t tmpreg;
+
+ /* Enable major link */
+ tcd->CSR |= DMA_CSR_MAJORELINK_MASK;
+ /* Set major linked channel */
+ tmpreg = tcd->CSR & (~DMA_CSR_MAJORLINKCH_MASK);
+ tcd->CSR = tmpreg | DMA_CSR_MAJORLINKCH(linkedChannel);
+ }
+ else /* Link none */
+ {
+ tcd->CITER &= ~DMA_CITER_ELINKYES_ELINK_MASK;
+ tcd->BITER &= ~DMA_BITER_ELINKYES_ELINK_MASK;
+ tcd->CSR &= ~DMA_CSR_MAJORELINK_MASK;
+ }
+}
+
+/*!
+ * brief Sets the source modulo and the destination modulo for the eDMA TCD.
+ *
+ * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
+ * calculation is performed or the original register value. It provides the ability to implement a circular data
+ * queue easily.
+ *
+ * param tcd A pointer to the TCD structure.
+ * param srcModulo A source modulo value.
+ * param destModulo A destination modulo value.
+ */
+void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)
+{
+ assert(tcd != NULL);
+ assert(((uint32_t)tcd & 0x1FU) == 0);
+
+ uint32_t tmpreg;
+
+ tmpreg = tcd->ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK));
+ tcd->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo);
+}
+
+/*!
+ * brief Enables the interrupt source for the eDMA TCD.
+ *
+ * param tcd Point to the TCD structure.
+ * param mask The mask of interrupt source to be set. Users need to use
+ * the defined edma_interrupt_enable_t type.
+ */
+void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask)
+{
+ assert(tcd != NULL);
+
+ /* Enable Major interrupt */
+ if (mask & kEDMA_MajorInterruptEnable)
+ {
+ tcd->CSR |= DMA_CSR_INTMAJOR_MASK;
+ }
+
+ /* Enable Half major interrupt */
+ if (mask & kEDMA_HalfInterruptEnable)
+ {
+ tcd->CSR |= DMA_CSR_INTHALF_MASK;
+ }
+}
+
+/*!
+ * brief Disables the interrupt source for the eDMA TCD.
+ *
+ * param tcd Point to the TCD structure.
+ * param mask The mask of interrupt source to be set. Users need to use
+ * the defined edma_interrupt_enable_t type.
+ */
+void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask)
+{
+ assert(tcd != NULL);
+
+ /* Disable Major interrupt */
+ if (mask & kEDMA_MajorInterruptEnable)
+ {
+ tcd->CSR &= ~DMA_CSR_INTMAJOR_MASK;
+ }
+
+ /* Disable Half major interrupt */
+ if (mask & kEDMA_HalfInterruptEnable)
+ {
+ tcd->CSR &= ~DMA_CSR_INTHALF_MASK;
+ }
+}
+
+/*!
+ * brief Gets the remaining major loop count from the eDMA current channel TCD.
+ *
+ * This function checks the TCD (Task Control Descriptor) status for a specified
+ * eDMA channel and returns the number of major loop count that has not finished.
+ *
+ * param base eDMA peripheral base address.
+ * param channel eDMA channel number.
+ * return Major loop count which has not been transferred yet for the current TCD.
+ * note 1. This function can only be used to get unfinished major loop count of transfer without
+ * the next TCD, or it might be inaccuracy.
+ * 2. The unfinished/remaining transfer bytes cannot be obtained directly from registers while
+ * the channel is running.
+ * Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO
+ * register is needed while the eDMA IP does not support getting it while a channel is active.
+ * In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine
+ * is working with while a channel is running.
+ * Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example
+ * copied before enabling the channel) is needed. The formula to calculate it is shown below:
+ * RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured)
+ */
+uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+ uint32_t remainingCount = 0;
+
+ if (DMA_CSR_DONE_MASK & base->TCD[channel].CSR)
+ {
+ remainingCount = 0;
+ }
+ else
+ {
+ /* Calculate the unfinished bytes */
+ if (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_ELINK_MASK)
+ {
+ remainingCount =
+ (base->TCD[channel].CITER_ELINKYES & DMA_CITER_ELINKYES_CITER_MASK) >> DMA_CITER_ELINKYES_CITER_SHIFT;
+ }
+ else
+ {
+ remainingCount =
+ (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT;
+ }
+ }
+
+ return remainingCount;
+}
+
+/*!
+ * brief Gets the eDMA channel status flags.
+ *
+ * param base eDMA peripheral base address.
+ * param channel eDMA channel number.
+ * return The mask of channel status flags. Users need to use the
+ * _edma_channel_status_flags type to decode the return variables.
+ */
+uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+ uint32_t retval = 0;
+
+ /* Get DONE bit flag */
+ retval |= ((base->TCD[channel].CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT);
+ /* Get ERROR bit flag */
+ retval |= (((base->ERR >> channel) & 0x1U) << 1U);
+ /* Get INT bit flag */
+ retval |= (((base->INT >> channel) & 0x1U) << 2U);
+
+ return retval;
+}
+
+/*!
+ * brief Clears the eDMA channel status flags.
+ *
+ * param base eDMA peripheral base address.
+ * param channel eDMA channel number.
+ * param mask The mask of channel status to be cleared. Users need to use
+ * the defined _edma_channel_status_flags type.
+ */
+void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+ /* Clear DONE bit flag */
+ if (mask & kEDMA_DoneFlag)
+ {
+ base->CDNE = channel;
+ }
+ /* Clear ERROR bit flag */
+ if (mask & kEDMA_ErrorFlag)
+ {
+ base->CERR = channel;
+ }
+ /* Clear INT bit flag */
+ if (mask & kEDMA_InterruptFlag)
+ {
+ base->CINT = channel;
+ }
+}
+
+static uint8_t Get_StartInstance(void)
+{
+ static uint8_t StartInstanceNum;
+
+#if defined(DMA0)
+ StartInstanceNum = EDMA_GetInstance(DMA0);
+#elif defined(DMA1)
+ StartInstanceNum = EDMA_GetInstance(DMA1);
+#elif defined(DMA2)
+ StartInstanceNum = EDMA_GetInstance(DMA2);
+#elif defined(DMA3)
+ StartInstanceNum = EDMA_GetInstance(DMA3);
+#endif
+
+ return StartInstanceNum;
+}
+
+/*!
+ * brief Creates the eDMA handle.
+ *
+ * This function is called if using the transactional API for eDMA. This function
+ * initializes the internal state of the eDMA handle.
+ *
+ * param handle eDMA handle pointer. The eDMA handle stores callback function and
+ * parameters.
+ * param base eDMA peripheral base address.
+ * param channel eDMA channel number.
+ */
+void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel)
+{
+ assert(handle != NULL);
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+ uint32_t edmaInstance;
+ uint32_t channelIndex;
+ uint8_t StartInstance;
+ edma_tcd_t *tcdRegs;
+
+ /* Zero the handle */
+ memset(handle, 0, sizeof(*handle));
+
+ handle->base = base;
+ handle->channel = channel;
+ /* Get the DMA instance number */
+ edmaInstance = EDMA_GetInstance(base);
+ StartInstance = Get_StartInstance();
+ channelIndex = ((edmaInstance - StartInstance) * FSL_FEATURE_EDMA_MODULE_CHANNEL) + channel;
+ s_EDMAHandle[channelIndex] = handle;
+
+ /* Enable NVIC interrupt */
+ EnableIRQ(s_edmaIRQNumber[edmaInstance][channel]);
+
+ /*
+ Reset TCD registers to zero. Unlike the EDMA_TcdReset(DREQ will be set),
+ CSR will be 0. Because in order to suit EDMA busy check mechanism in
+ EDMA_SubmitTransfer, CSR must be set 0.
+ */
+ tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel];
+ tcdRegs->SADDR = 0;
+ tcdRegs->SOFF = 0;
+ tcdRegs->ATTR = 0;
+ tcdRegs->NBYTES = 0;
+ tcdRegs->SLAST = 0;
+ tcdRegs->DADDR = 0;
+ tcdRegs->DOFF = 0;
+ tcdRegs->CITER = 0;
+ tcdRegs->DLAST_SGA = 0;
+ tcdRegs->CSR = 0;
+ tcdRegs->BITER = 0;
+}
+
+/*!
+ * brief Installs the TCDs memory pool into the eDMA handle.
+ *
+ * This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used
+ * while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block
+ * (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer.
+ * Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer.
+ *
+ * param handle eDMA handle pointer.
+ * param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned.
+ * param tcdSize The number of TCD slots.
+ */
+void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize)
+{
+ assert(handle != NULL);
+ assert(((uint32_t)tcdPool & 0x1FU) == 0);
+
+ /* Initialize tcd queue attribute. */
+ handle->header = 0;
+ handle->tail = 0;
+ handle->tcdUsed = 0;
+ handle->tcdSize = tcdSize;
+ handle->flags = 0;
+ handle->tcdPool = tcdPool;
+}
+
+/*!
+ * brief Installs a callback function for the eDMA transfer.
+ *
+ * This callback is called in the eDMA IRQ handler. Use the callback to do something after
+ * the current major loop transfer completes. This function will be called every time one tcd finished transfer.
+ *
+ * param handle eDMA handle pointer.
+ * param callback eDMA callback function pointer.
+ * param userData A parameter for the callback function.
+ */
+void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData)
+{
+ assert(handle != NULL);
+
+ handle->callback = callback;
+ handle->userData = userData;
+}
+
+/*!
+ * brief Prepares the eDMA transfer structure.
+ *
+ * This function prepares the transfer configuration structure according to the user input.
+ *
+ * param config The user configuration structure of type edma_transfer_t.
+ * param srcAddr eDMA transfer source address.
+ * param srcWidth eDMA transfer source address width(bytes).
+ * param destAddr eDMA transfer destination address.
+ * param destWidth eDMA transfer destination address width(bytes).
+ * param bytesEachRequest eDMA transfer bytes per channel request.
+ * param transferBytes eDMA transfer bytes to be transferred.
+ * param type eDMA transfer type.
+ * note The data address and the data width must be consistent. For example, if the SRC
+ * is 4 bytes, the source address must be 4 bytes aligned, or it results in
+ * source address error (SAE).
+ */
+void EDMA_PrepareTransfer(edma_transfer_config_t *config,
+ void *srcAddr,
+ uint32_t srcWidth,
+ void *destAddr,
+ uint32_t destWidth,
+ uint32_t bytesEachRequest,
+ uint32_t transferBytes,
+ edma_transfer_type_t type)
+{
+ assert(config != NULL);
+ assert(srcAddr != NULL);
+ assert(destAddr != NULL);
+ assert((srcWidth == 1U) || (srcWidth == 2U) || (srcWidth == 4U) || (srcWidth == 16U) || (srcWidth == 32U));
+ assert((destWidth == 1U) || (destWidth == 2U) || (destWidth == 4U) || (destWidth == 16U) || (destWidth == 32U));
+ assert(transferBytes % bytesEachRequest == 0);
+
+ /* Initializes the configure structure to zero. */
+ memset(config, 0, sizeof(*config));
+
+ config->destAddr = (uint32_t)destAddr;
+ config->srcAddr = (uint32_t)srcAddr;
+ config->minorLoopBytes = bytesEachRequest;
+ config->majorLoopCounts = transferBytes / bytesEachRequest;
+ switch (srcWidth)
+ {
+ case 1U:
+ config->srcTransferSize = kEDMA_TransferSize1Bytes;
+ break;
+ case 2U:
+ config->srcTransferSize = kEDMA_TransferSize2Bytes;
+ break;
+ case 4U:
+ config->srcTransferSize = kEDMA_TransferSize4Bytes;
+ break;
+ case 16U:
+ config->srcTransferSize = kEDMA_TransferSize16Bytes;
+ break;
+ case 32U:
+ config->srcTransferSize = kEDMA_TransferSize32Bytes;
+ break;
+ default:
+ break;
+ }
+ switch (destWidth)
+ {
+ case 1U:
+ config->destTransferSize = kEDMA_TransferSize1Bytes;
+ break;
+ case 2U:
+ config->destTransferSize = kEDMA_TransferSize2Bytes;
+ break;
+ case 4U:
+ config->destTransferSize = kEDMA_TransferSize4Bytes;
+ break;
+ case 16U:
+ config->destTransferSize = kEDMA_TransferSize16Bytes;
+ break;
+ case 32U:
+ config->destTransferSize = kEDMA_TransferSize32Bytes;
+ break;
+ default:
+ break;
+ }
+ switch (type)
+ {
+ case kEDMA_MemoryToMemory:
+ config->destOffset = destWidth;
+ config->srcOffset = srcWidth;
+ break;
+ case kEDMA_MemoryToPeripheral:
+ config->destOffset = 0U;
+ config->srcOffset = srcWidth;
+ break;
+ case kEDMA_PeripheralToMemory:
+ config->destOffset = destWidth;
+ config->srcOffset = 0U;
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ * brief Submits the eDMA transfer request.
+ *
+ * This function submits the eDMA transfer request according to the transfer configuration structure.
+ * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool.
+ * The tcd pools is setup by call function EDMA_InstallTCDMemory before.
+ *
+ * param handle eDMA handle pointer.
+ * param config Pointer to eDMA transfer configuration structure.
+ * retval kStatus_EDMA_Success It means submit transfer request succeed.
+ * retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed.
+ * retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later.
+ */
+status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config)
+{
+ assert(handle != NULL);
+ assert(config != NULL);
+
+ edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel];
+
+ if (handle->tcdPool == NULL)
+ {
+ /*
+ Check if EDMA is busy: if the given channel started transfer, CSR will be not zero. Because
+ if it is the last transfer, DREQ will be set. If not, ESG will be set. So in order to suit
+ this check mechanism, EDMA_CreatHandle will clear CSR register.
+ */
+ if ((tcdRegs->CSR != 0) && ((tcdRegs->CSR & DMA_CSR_DONE_MASK) == 0))
+ {
+ return kStatus_EDMA_Busy;
+ }
+ else
+ {
+ EDMA_SetTransferConfig(handle->base, handle->channel, config, NULL);
+ /* Enable auto disable request feature */
+ handle->base->TCD[handle->channel].CSR |= DMA_CSR_DREQ_MASK;
+ /* Enable major interrupt */
+ handle->base->TCD[handle->channel].CSR |= DMA_CSR_INTMAJOR_MASK;
+
+ return kStatus_Success;
+ }
+ }
+ else /* Use the TCD queue. */
+ {
+ uint32_t primask;
+ uint32_t csr;
+ int8_t currentTcd;
+ int8_t previousTcd;
+ int8_t nextTcd;
+
+ /* Check if tcd pool is full. */
+ primask = DisableGlobalIRQ();
+ if (handle->tcdUsed >= handle->tcdSize)
+ {
+ EnableGlobalIRQ(primask);
+
+ return kStatus_EDMA_QueueFull;
+ }
+ currentTcd = handle->tail;
+ handle->tcdUsed++;
+ /* Calculate index of next TCD */
+ nextTcd = currentTcd + 1U;
+ if (nextTcd == handle->tcdSize)
+ {
+ nextTcd = 0U;
+ }
+ /* Advance queue tail index */
+ handle->tail = nextTcd;
+ EnableGlobalIRQ(primask);
+ /* Calculate index of previous TCD */
+ previousTcd = currentTcd ? currentTcd - 1U : handle->tcdSize - 1U;
+ /* Configure current TCD block. */
+ EDMA_TcdReset(&handle->tcdPool[currentTcd]);
+ EDMA_TcdSetTransferConfig(&handle->tcdPool[currentTcd], config, NULL);
+ /* Enable major interrupt */
+ handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK;
+ /* Link current TCD with next TCD for identification of current TCD */
+ handle->tcdPool[currentTcd].DLAST_SGA = (uint32_t)&handle->tcdPool[nextTcd];
+ /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */
+ if (currentTcd != previousTcd)
+ {
+ /* Enable scatter/gather feature in the previous TCD block. */
+ csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK;
+ handle->tcdPool[previousTcd].CSR = csr;
+ /*
+ Check if the TCD block in the registers is the previous one (points to current TCD block). It
+ is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to
+ link the TCD register in case link the current TCD with the dead chain when TCD loading occurs
+ before link the previous TCD block.
+ */
+ if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[currentTcd])
+ {
+ /* Clear the DREQ bits for the dynamic scatter gather */
+ tcdRegs->CSR |= DMA_CSR_DREQ_MASK;
+ /* Enable scatter/gather also in the TCD registers. */
+ csr = tcdRegs->CSR | DMA_CSR_ESG_MASK;
+ /* Must write the CSR register one-time, because the transfer maybe finished anytime. */
+ tcdRegs->CSR = csr;
+ /*
+ It is very important to check the ESG bit!
+ Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can
+ be used to check if the dynamic TCD link operation is successful. If ESG bit is not set
+ and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and
+ the current TCD block has been loaded into TCD registers), it means transfer finished
+ and TCD link operation fail, so must install TCD content into TCD registers and enable
+ transfer again. And if ESG is set, it means transfer has not finished, so TCD dynamic
+ link succeed.
+ */
+ if (tcdRegs->CSR & DMA_CSR_ESG_MASK)
+ {
+ tcdRegs->CSR &= ~DMA_CSR_DREQ_MASK;
+ return kStatus_Success;
+ }
+ /*
+ Check whether the current TCD block is already loaded in the TCD registers. It is another
+ condition when ESG bit is not set: it means the dynamic TCD link succeed and the current
+ TCD block has been loaded into TCD registers.
+ */
+ if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[nextTcd])
+ {
+ return kStatus_Success;
+ }
+ /*
+ If go to this, means the previous transfer finished, and the DONE bit is set.
+ So shall configure TCD registers.
+ */
+ }
+ else if (tcdRegs->DLAST_SGA != 0)
+ {
+ /* The current TCD block has been linked successfully. */
+ return kStatus_Success;
+ }
+ else
+ {
+ /*
+ DLAST_SGA is 0 and it means the first submit transfer, so shall configure
+ TCD registers.
+ */
+ }
+ }
+ /* There is no live chain, TCD block need to be installed in TCD registers. */
+ EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]);
+ /* Enable channel request again. */
+ if (handle->flags & EDMA_TRANSFER_ENABLED_MASK)
+ {
+ handle->base->SERQ = DMA_SERQ_SERQ(handle->channel);
+ }
+
+ return kStatus_Success;
+ }
+}
+
+/*!
+ * brief eDMA starts transfer.
+ *
+ * This function enables the channel request. Users can call this function after submitting the transfer request
+ * or before submitting the transfer request.
+ *
+ * param handle eDMA handle pointer.
+ */
+void EDMA_StartTransfer(edma_handle_t *handle)
+{
+ assert(handle != NULL);
+
+ if (handle->tcdPool == NULL)
+ {
+ handle->base->SERQ = DMA_SERQ_SERQ(handle->channel);
+ }
+ else /* Use the TCD queue. */
+ {
+ uint32_t primask;
+ edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel];
+
+ handle->flags |= EDMA_TRANSFER_ENABLED_MASK;
+
+ /* Check if there was at least one descriptor submitted since reset (TCD in registers is valid) */
+ if (tcdRegs->DLAST_SGA != 0U)
+ {
+ primask = DisableGlobalIRQ();
+ /* Check if channel request is actually disable. */
+ if ((handle->base->ERQ & (1U << handle->channel)) == 0U)
+ {
+ /* Check if transfer is paused. */
+ if ((!(tcdRegs->CSR & DMA_CSR_DONE_MASK)) || (tcdRegs->CSR & DMA_CSR_ESG_MASK))
+ {
+ /*
+ Re-enable channel request must be as soon as possible, so must put it into
+ critical section to avoid task switching or interrupt service routine.
+ */
+ handle->base->SERQ = DMA_SERQ_SERQ(handle->channel);
+ }
+ }
+ EnableGlobalIRQ(primask);
+ }
+ }
+}
+
+/*!
+ * brief eDMA stops transfer.
+ *
+ * This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer()
+ * again to resume the transfer.
+ *
+ * param handle eDMA handle pointer.
+ */
+void EDMA_StopTransfer(edma_handle_t *handle)
+{
+ assert(handle != NULL);
+
+ handle->flags &= (~EDMA_TRANSFER_ENABLED_MASK);
+ handle->base->CERQ = DMA_CERQ_CERQ(handle->channel);
+}
+
+/*!
+ * brief eDMA aborts transfer.
+ *
+ * This function disables the channel request and clear transfer status bits.
+ * Users can submit another transfer after calling this API.
+ *
+ * param handle DMA handle pointer.
+ */
+void EDMA_AbortTransfer(edma_handle_t *handle)
+{
+ handle->base->CERQ = DMA_CERQ_CERQ(handle->channel);
+ /*
+ Clear CSR to release channel. Because if the given channel started transfer,
+ CSR will be not zero. Because if it is the last transfer, DREQ will be set.
+ If not, ESG will be set.
+ */
+ handle->base->TCD[handle->channel].CSR = 0;
+ /* Cancel all next TCD transfer. */
+ handle->base->TCD[handle->channel].DLAST_SGA = 0;
+
+ /* Handle the tcd */
+ if (handle->tcdPool != NULL)
+ {
+ handle->header = 0;
+ handle->tail = 0;
+ handle->tcdUsed = 0;
+ }
+}
+
+/*!
+ * brief eDMA IRQ handler for the current major loop transfer completion.
+ *
+ * This function clears the channel major interrupt flag and calls
+ * the callback function if it is not NULL.
+ *
+ * Note:
+ * For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed.
+ * These include the final address adjustments and reloading of the BITER field into the CITER.
+ * Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from
+ * memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled).
+ *
+ * For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine.
+ * As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index
+ * in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be
+ * (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have
+ * been loaded into the eDMA engine at this point already.).
+ *
+ * For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not
+ * load a new TCD) from the memory pool to the eDMA engine when major loop completes.
+ * Therefore, ensure that the header and tcdUsed updated are identical for them.
+ * tcdUsed are both 0 in this case as no TCD to be loaded.
+ *
+ * See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for
+ * further details.
+ *
+ * param handle eDMA handle pointer.
+ */
+void EDMA_HandleIRQ(edma_handle_t *handle)
+{
+ assert(handle != NULL);
+
+ /* Clear EDMA interrupt flag */
+ handle->base->CINT = handle->channel;
+ if ((handle->tcdPool == NULL) && (handle->callback != NULL))
+ {
+ (handle->callback)(handle, handle->userData, true, 0);
+ }
+ else /* Use the TCD queue. Please refer to the API descriptions in the eDMA header file for detailed information. */
+ {
+ uint32_t sga = handle->base->TCD[handle->channel].DLAST_SGA;
+ uint32_t sga_index;
+ int32_t tcds_done;
+ uint8_t new_header;
+ bool transfer_done;
+
+ /* Check if transfer is already finished. */
+ transfer_done = ((handle->base->TCD[handle->channel].CSR & DMA_CSR_DONE_MASK) != 0);
+ /* Get the offset of the next transfer TCD blocks to be loaded into the eDMA engine. */
+ sga -= (uint32_t)handle->tcdPool;
+ /* Get the index of the next transfer TCD blocks to be loaded into the eDMA engine. */
+ sga_index = sga / sizeof(edma_tcd_t);
+ /* Adjust header positions. */
+ if (transfer_done)
+ {
+ /* New header shall point to the next TCD to be loaded (current one is already finished) */
+ new_header = sga_index;
+ }
+ else
+ {
+ /* New header shall point to this descriptor currently loaded (not finished yet) */
+ new_header = sga_index ? sga_index - 1U : handle->tcdSize - 1U;
+ }
+ /* Calculate the number of finished TCDs */
+ if (new_header == handle->header)
+ {
+ if (handle->tcdUsed == handle->tcdSize)
+ {
+ tcds_done = handle->tcdUsed;
+ }
+ else
+ {
+ /* No TCD in the memory are going to be loaded or internal error occurs. */
+ tcds_done = 0;
+ }
+ }
+ else
+ {
+ tcds_done = new_header - handle->header;
+ if (tcds_done < 0)
+ {
+ tcds_done += handle->tcdSize;
+ }
+ }
+ /* Advance header which points to the TCD to be loaded into the eDMA engine from memory. */
+ handle->header = new_header;
+ /* Release TCD blocks. tcdUsed is the TCD number which can be used/loaded in the memory pool. */
+ handle->tcdUsed -= tcds_done;
+ /* Invoke callback function. */
+ if (handle->callback)
+ {
+ (handle->callback)(handle, handle->userData, transfer_done, tcds_done);
+ }
+
+ /* clear the DONE bit here is meaningful for below cases:
+ *1.A new TCD has been loaded to EDMA already:
+ * need to clear the DONE bit in the IRQ handler to avoid TCD in EDMA been overwritten
+ * if peripheral request isn't coming before next transfer request.
+ *2.A new TCD has not been loaded to EDMA:
+ * for the case that transfer request occur in the privious edma callback, this is a case that doesn't
+ * need scatter gather, so keep DONE bit during the next transfer request will re-install the TCD.
+ */
+ if (transfer_done)
+ {
+ handle->base->CDNE = handle->channel;
+ }
+ }
+}
+
+/* 8 channels (Shared): kl28 */
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 8U
+
+#if defined(DMA0)
+void DMA0_04_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[0]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[4]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA0_15_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[1]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[5]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA0_26_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[2]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[6]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA0_37_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[3]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[7]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif
+
+#if defined(DMA1)
+
+#if defined(DMA0)
+void DMA1_04_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[8]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[12]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA1_15_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[9]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[13]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA1_26_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[10]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[14]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA1_37_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[11]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[15]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+#else
+void DMA1_04_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[0]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[4]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA1_15_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[1]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[5]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA1_26_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[2]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[6]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA1_37_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[3]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[7]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif
+#endif
+#endif /* 8 channels (Shared) */
+
+/* 16 channels (Shared): K32H844P */
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 16U
+
+void DMA0_08_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[0]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[8]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA0_19_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[1]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[9]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA0_210_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[2]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[10]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA0_311_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[3]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[11]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA0_412_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[4]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[12]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA0_513_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[5]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[13]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA0_614_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[6]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[14]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA0_715_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[7]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[15]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+#if defined(DMA1)
+void DMA1_08_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[16]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA1, 8U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[24]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA1_19_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[17]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA1, 9U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[25]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA1_210_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[18]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA1, 10U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[26]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA1_311_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[19]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA1, 11U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[27]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA1_412_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[20]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA1, 12U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[28]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA1_513_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[21]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA1, 13U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[29]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA1_614_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[22]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA1, 14U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[30]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA1_715_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[23]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA1, 15U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[31]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif
+#endif /* 16 channels (Shared) */
+
+/* 32 channels (Shared): k80 */
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U
+
+void DMA0_DMA16_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[0]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[16]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA1_DMA17_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[1]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[17]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA2_DMA18_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[2]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[18]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA3_DMA19_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[3]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[19]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA4_DMA20_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[4]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[20]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA5_DMA21_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[5]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[21]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA6_DMA22_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[6]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[22]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA7_DMA23_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[7]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[23]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA8_DMA24_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[8]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[24]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA9_DMA25_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[9]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[25]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA10_DMA26_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[10]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[26]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA11_DMA27_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[11]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[27]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA12_DMA28_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[12]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[28]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA13_DMA29_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[13]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[29]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA14_DMA30_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[14]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[30]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA15_DMA31_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[15]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[31]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif /* 32 channels (Shared) */
+
+/* 32 channels (Shared): MCIMX7U5_M4 */
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U
+
+void DMA0_0_4_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[0]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[4]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA0_1_5_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[1]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[5]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA0_2_6_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[2]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[6]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA0_3_7_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[3]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[7]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA0_8_12_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[8]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[12]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA0_9_13_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[9]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[13]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA0_10_14_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[10]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[14]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA0_11_15_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[11]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[15]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA0_16_20_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[16]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[20]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA0_17_21_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[17]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[21]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA0_18_22_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[18]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[22]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA0_19_23_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[19]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[23]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA0_24_28_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[24]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[28]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA0_25_29_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[25]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[29]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA0_26_30_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[26]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[30]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA0_27_31_DriverIRQHandler(void)
+{
+ if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[27]);
+ }
+ if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U)
+ {
+ EDMA_HandleIRQ(s_EDMAHandle[31]);
+ }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif /* 32 channels (Shared): MCIMX7U5 */
+
+/* 4 channels (No Shared): kv10 */
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 0
+
+void DMA0_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[0]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA1_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[1]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA2_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[2]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA3_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[3]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+/* 8 channels (No Shared) */
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 4U
+
+void DMA4_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[4]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA5_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[5]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA6_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[6]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA7_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[7]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 8 */
+
+/* 16 channels (No Shared) */
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 8U
+
+void DMA8_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[8]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA9_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[9]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA10_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[10]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA11_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[11]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA12_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[12]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA13_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[13]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA14_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[14]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA15_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[15]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 16 */
+
+/* 32 channels (No Shared) */
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 16U
+
+void DMA16_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[16]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA17_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[17]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA18_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[18]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA19_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[19]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA20_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[20]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA21_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[21]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA22_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[22]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA23_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[23]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA24_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[24]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA25_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[25]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA26_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[26]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA27_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[27]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA28_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[28]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA29_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[29]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA30_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[30]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void DMA31_DriverIRQHandler(void)
+{
+ EDMA_HandleIRQ(s_EDMAHandle[31]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 32 */
+
+#endif /* 4/8/16/32 channels (No Shared) */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/fsl_edma.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/fsl_edma.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,931 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_EDMA_H_
+#define _FSL_EDMA_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup edma
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief eDMA driver version */
+#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*!< Version 2.1.4. */
+/*@}*/
+
+/*! @brief Compute the offset unit from DCHPRI3 */
+#define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3 - ((channel)&0x03U)))
+
+/*! @brief Get the pointer of DCHPRIn */
+#define DMA_DCHPRIn(base, channel) ((volatile uint8_t *)&((base)->DCHPRI3))[DMA_DCHPRI_INDEX(channel)]
+
+/*! @brief eDMA transfer configuration */
+typedef enum _edma_transfer_size
+{
+ kEDMA_TransferSize1Bytes = 0x0U, /*!< Source/Destination data transfer size is 1 byte every time */
+ kEDMA_TransferSize2Bytes = 0x1U, /*!< Source/Destination data transfer size is 2 bytes every time */
+ kEDMA_TransferSize4Bytes = 0x2U, /*!< Source/Destination data transfer size is 4 bytes every time */
+ kEDMA_TransferSize8Bytes = 0x3U, /*!< Source/Destination data transfer size is 8 bytes every time */
+ kEDMA_TransferSize16Bytes = 0x4U, /*!< Source/Destination data transfer size is 16 bytes every time */
+ kEDMA_TransferSize32Bytes = 0x5U, /*!< Source/Destination data transfer size is 32 bytes every time */
+} edma_transfer_size_t;
+
+/*! @brief eDMA modulo configuration */
+typedef enum _edma_modulo
+{
+ kEDMA_ModuloDisable = 0x0U, /*!< Disable modulo */
+ kEDMA_Modulo2bytes, /*!< Circular buffer size is 2 bytes. */
+ kEDMA_Modulo4bytes, /*!< Circular buffer size is 4 bytes. */
+ kEDMA_Modulo8bytes, /*!< Circular buffer size is 8 bytes. */
+ kEDMA_Modulo16bytes, /*!< Circular buffer size is 16 bytes. */
+ kEDMA_Modulo32bytes, /*!< Circular buffer size is 32 bytes. */
+ kEDMA_Modulo64bytes, /*!< Circular buffer size is 64 bytes. */
+ kEDMA_Modulo128bytes, /*!< Circular buffer size is 128 bytes. */
+ kEDMA_Modulo256bytes, /*!< Circular buffer size is 256 bytes. */
+ kEDMA_Modulo512bytes, /*!< Circular buffer size is 512 bytes. */
+ kEDMA_Modulo1Kbytes, /*!< Circular buffer size is 1 K bytes. */
+ kEDMA_Modulo2Kbytes, /*!< Circular buffer size is 2 K bytes. */
+ kEDMA_Modulo4Kbytes, /*!< Circular buffer size is 4 K bytes. */
+ kEDMA_Modulo8Kbytes, /*!< Circular buffer size is 8 K bytes. */
+ kEDMA_Modulo16Kbytes, /*!< Circular buffer size is 16 K bytes. */
+ kEDMA_Modulo32Kbytes, /*!< Circular buffer size is 32 K bytes. */
+ kEDMA_Modulo64Kbytes, /*!< Circular buffer size is 64 K bytes. */
+ kEDMA_Modulo128Kbytes, /*!< Circular buffer size is 128 K bytes. */
+ kEDMA_Modulo256Kbytes, /*!< Circular buffer size is 256 K bytes. */
+ kEDMA_Modulo512Kbytes, /*!< Circular buffer size is 512 K bytes. */
+ kEDMA_Modulo1Mbytes, /*!< Circular buffer size is 1 M bytes. */
+ kEDMA_Modulo2Mbytes, /*!< Circular buffer size is 2 M bytes. */
+ kEDMA_Modulo4Mbytes, /*!< Circular buffer size is 4 M bytes. */
+ kEDMA_Modulo8Mbytes, /*!< Circular buffer size is 8 M bytes. */
+ kEDMA_Modulo16Mbytes, /*!< Circular buffer size is 16 M bytes. */
+ kEDMA_Modulo32Mbytes, /*!< Circular buffer size is 32 M bytes. */
+ kEDMA_Modulo64Mbytes, /*!< Circular buffer size is 64 M bytes. */
+ kEDMA_Modulo128Mbytes, /*!< Circular buffer size is 128 M bytes. */
+ kEDMA_Modulo256Mbytes, /*!< Circular buffer size is 256 M bytes. */
+ kEDMA_Modulo512Mbytes, /*!< Circular buffer size is 512 M bytes. */
+ kEDMA_Modulo1Gbytes, /*!< Circular buffer size is 1 G bytes. */
+ kEDMA_Modulo2Gbytes, /*!< Circular buffer size is 2 G bytes. */
+} edma_modulo_t;
+
+/*! @brief Bandwidth control */
+typedef enum _edma_bandwidth
+{
+ kEDMA_BandwidthStallNone = 0x0U, /*!< No eDMA engine stalls. */
+ kEDMA_BandwidthStall4Cycle = 0x2U, /*!< eDMA engine stalls for 4 cycles after each read/write. */
+ kEDMA_BandwidthStall8Cycle = 0x3U, /*!< eDMA engine stalls for 8 cycles after each read/write. */
+} edma_bandwidth_t;
+
+/*! @brief Channel link type */
+typedef enum _edma_channel_link_type
+{
+ kEDMA_LinkNone = 0x0U, /*!< No channel link */
+ kEDMA_MinorLink, /*!< Channel link after each minor loop */
+ kEDMA_MajorLink, /*!< Channel link while major loop count exhausted */
+} edma_channel_link_type_t;
+
+/*!@brief eDMA channel status flags. */
+enum _edma_channel_status_flags
+{
+ kEDMA_DoneFlag = 0x1U, /*!< DONE flag, set while transfer finished, CITER value exhausted*/
+ kEDMA_ErrorFlag = 0x2U, /*!< eDMA error flag, an error occurred in a transfer */
+ kEDMA_InterruptFlag = 0x4U, /*!< eDMA interrupt flag, set while an interrupt occurred of this channel */
+};
+
+/*! @brief eDMA channel error status flags. */
+enum _edma_error_status_flags
+{
+ kEDMA_DestinationBusErrorFlag = DMA_ES_DBE_MASK, /*!< Bus error on destination address */
+ kEDMA_SourceBusErrorFlag = DMA_ES_SBE_MASK, /*!< Bus error on the source address */
+ kEDMA_ScatterGatherErrorFlag = DMA_ES_SGE_MASK, /*!< Error on the Scatter/Gather address, not 32byte aligned. */
+ kEDMA_NbytesErrorFlag = DMA_ES_NCE_MASK, /*!< NBYTES/CITER configuration error */
+ kEDMA_DestinationOffsetErrorFlag = DMA_ES_DOE_MASK, /*!< Destination offset not aligned with destination size */
+ kEDMA_DestinationAddressErrorFlag = DMA_ES_DAE_MASK, /*!< Destination address not aligned with destination size */
+ kEDMA_SourceOffsetErrorFlag = DMA_ES_SOE_MASK, /*!< Source offset not aligned with source size */
+ kEDMA_SourceAddressErrorFlag = DMA_ES_SAE_MASK, /*!< Source address not aligned with source size*/
+ kEDMA_ErrorChannelFlag = DMA_ES_ERRCHN_MASK, /*!< Error channel number of the cancelled channel number */
+ kEDMA_ChannelPriorityErrorFlag = DMA_ES_CPE_MASK, /*!< Channel priority is not unique. */
+ kEDMA_TransferCanceledFlag = DMA_ES_ECX_MASK, /*!< Transfer cancelled */
+#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1
+ kEDMA_GroupPriorityErrorFlag = DMA_ES_GPE_MASK, /*!< Group priority is not unique. */
+#endif
+ kEDMA_ValidFlag = (int)DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */
+};
+
+/*! @brief eDMA interrupt source */
+typedef enum _edma_interrupt_enable
+{
+ kEDMA_ErrorInterruptEnable = 0x1U, /*!< Enable interrupt while channel error occurs. */
+ kEDMA_MajorInterruptEnable = DMA_CSR_INTMAJOR_MASK, /*!< Enable interrupt while major count exhausted. */
+ kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK, /*!< Enable interrupt while major count to half value. */
+} edma_interrupt_enable_t;
+
+/*! @brief eDMA transfer type */
+typedef enum _edma_transfer_type
+{
+ kEDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory */
+ kEDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory */
+ kEDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral */
+} edma_transfer_type_t;
+
+/*! @brief eDMA transfer status */
+enum _edma_transfer_status
+{
+ kStatus_EDMA_QueueFull = MAKE_STATUS(kStatusGroup_EDMA, 0), /*!< TCD queue is full. */
+ kStatus_EDMA_Busy = MAKE_STATUS(kStatusGroup_EDMA, 1), /*!< Channel is busy and can't handle the
+ transfer request. */
+};
+
+/*! @brief eDMA global configuration structure.*/
+typedef struct _edma_config
+{
+ bool enableContinuousLinkMode; /*!< Enable (true) continuous link mode. Upon minor loop completion, the channel
+ activates again if that channel has a minor loop channel link enabled and
+ the link channel is itself. */
+ bool enableHaltOnError; /*!< Enable (true) transfer halt on error. Any error causes the HALT bit to set.
+ Subsequently, all service requests are ignored until the HALT bit is cleared.*/
+ bool enableRoundRobinArbitration; /*!< Enable (true) round robin channel arbitration method or fixed priority
+ arbitration is used for channel selection */
+ bool enableDebugMode; /*!< Enable(true) eDMA debug mode. When in debug mode, the eDMA stalls the start of
+ a new channel. Executing channels are allowed to complete. */
+} edma_config_t;
+
+/*!
+ * @brief eDMA transfer configuration
+ *
+ * This structure configures the source/destination transfer attribute.
+ */
+typedef struct _edma_transfer_config
+{
+ uint32_t srcAddr; /*!< Source data address. */
+ uint32_t destAddr; /*!< Destination data address. */
+ edma_transfer_size_t srcTransferSize; /*!< Source data transfer size. */
+ edma_transfer_size_t destTransferSize; /*!< Destination data transfer size. */
+ int16_t srcOffset; /*!< Sign-extended offset applied to the current source address to
+ form the next-state value as each source read is completed. */
+ int16_t destOffset; /*!< Sign-extended offset applied to the current destination address to
+ form the next-state value as each destination write is completed. */
+ uint32_t minorLoopBytes; /*!< Bytes to transfer in a minor loop*/
+ uint32_t majorLoopCounts; /*!< Major loop iteration count. */
+} edma_transfer_config_t;
+
+/*! @brief eDMA channel priority configuration */
+typedef struct _edma_channel_Preemption_config
+{
+ bool enableChannelPreemption; /*!< If true: a channel can be suspended by other channel with higher priority */
+ bool enablePreemptAbility; /*!< If true: a channel can suspend other channel with low priority */
+ uint8_t channelPriority; /*!< Channel priority */
+} edma_channel_Preemption_config_t;
+
+/*! @brief eDMA minor offset configuration */
+typedef struct _edma_minor_offset_config
+{
+ bool enableSrcMinorOffset; /*!< Enable(true) or Disable(false) source minor loop offset. */
+ bool enableDestMinorOffset; /*!< Enable(true) or Disable(false) destination minor loop offset. */
+ uint32_t minorOffset; /*!< Offset for a minor loop mapping. */
+} edma_minor_offset_config_t;
+
+/*!
+ * @brief eDMA TCD.
+ *
+ * This structure is same as TCD register which is described in reference manual,
+ * and is used to configure the scatter/gather feature as a next hardware TCD.
+ */
+typedef struct _edma_tcd
+{
+ __IO uint32_t SADDR; /*!< SADDR register, used to save source address */
+ __IO uint16_t SOFF; /*!< SOFF register, save offset bytes every transfer */
+ __IO uint16_t ATTR; /*!< ATTR register, source/destination transfer size and modulo */
+ __IO uint32_t NBYTES; /*!< Nbytes register, minor loop length in bytes */
+ __IO uint32_t SLAST; /*!< SLAST register */
+ __IO uint32_t DADDR; /*!< DADDR register, used for destination address */
+ __IO uint16_t DOFF; /*!< DOFF register, used for destination offset */
+ __IO uint16_t CITER; /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/
+ __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next tcd address used in scatter-gather mode */
+ __IO uint16_t CSR; /*!< CSR register, for TCD control status */
+ __IO uint16_t BITER; /*!< BITER register, begin minor loop count. */
+} edma_tcd_t;
+
+/*! @brief Callback for eDMA */
+struct _edma_handle;
+
+/*! @brief Define callback function for eDMA.
+ *
+ * This callback function is called in the EDMA interrupt handle.
+ * In normal mode, run into callback function means the transfer users need is done.
+ * In scatter gather mode, run into callback function means a transfer control block (tcd) is finished. Not
+ * all transfer finished, users can get the finished tcd numbers using interface EDMA_GetUnusedTCDNumber.
+ *
+ * @param handle EDMA handle pointer, users shall not touch the values inside.
+ * @param userData The callback user parameter pointer. Users can use this parameter to involve things users need to
+ * change in EDMA callback function.
+ * @param transferDone If the current loaded transfer done. In normal mode it means if all transfer done. In scatter
+ * gather mode, this parameter shows is the current transfer block in EDMA register is done. As the
+ * load of core is different, it will be different if the new tcd loaded into EDMA registers while
+ * this callback called. If true, it always means new tcd still not loaded into registers, while
+ * false means new tcd already loaded into registers.
+ * @param tcds How many tcds are done from the last callback. This parameter only used in scatter gather mode. It
+ * tells user how many tcds are finished between the last callback and this.
+ */
+typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds);
+
+/*! @brief eDMA transfer handle structure */
+typedef struct _edma_handle
+{
+ edma_callback callback; /*!< Callback function for major count exhausted. */
+ void *userData; /*!< Callback function parameter. */
+ DMA_Type *base; /*!< eDMA peripheral base address. */
+ edma_tcd_t *tcdPool; /*!< Pointer to memory stored TCDs. */
+ uint8_t channel; /*!< eDMA channel number. */
+ volatile int8_t header; /*!< The first TCD index. Should point to the next TCD to be loaded into the eDMA engine. */
+ volatile int8_t tail; /*!< The last TCD index. Should point to the next TCD to be stored into the memory pool. */
+ volatile int8_t tcdUsed; /*!< The number of used TCD slots. Should reflect the number of TCDs can be used/loaded in
+ the memory. */
+ volatile int8_t tcdSize; /*!< The total number of TCD slots in the queue. */
+ uint8_t flags; /*!< The status of the current channel. */
+} edma_handle_t;
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name eDMA initialization and de-initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the eDMA peripheral.
+ *
+ * This function ungates the eDMA clock and configures the eDMA peripheral according
+ * to the configuration structure.
+ *
+ * @param base eDMA peripheral base address.
+ * @param config A pointer to the configuration structure, see "edma_config_t".
+ * @note This function enables the minor loop map feature.
+ */
+void EDMA_Init(DMA_Type *base, const edma_config_t *config);
+
+/*!
+ * @brief Deinitializes the eDMA peripheral.
+ *
+ * This function gates the eDMA clock.
+ *
+ * @param base eDMA peripheral base address.
+ */
+void EDMA_Deinit(DMA_Type *base);
+
+/*!
+ * @brief Push content of TCD structure into hardware TCD register.
+ *
+ * @param base EDMA peripheral base address.
+ * @param channel EDMA channel number.
+ * @param tcd Point to TCD structure.
+ */
+void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd);
+
+/*!
+ * @brief Gets the eDMA default configuration structure.
+ *
+ * This function sets the configuration structure to default values.
+ * The default configuration is set to the following values.
+ * @code
+ * config.enableContinuousLinkMode = false;
+ * config.enableHaltOnError = true;
+ * config.enableRoundRobinArbitration = false;
+ * config.enableDebugMode = false;
+ * @endcode
+ *
+ * @param config A pointer to the eDMA configuration structure.
+ */
+void EDMA_GetDefaultConfig(edma_config_t *config);
+
+/* @} */
+/*!
+ * @name eDMA Channel Operation
+ * @{
+ */
+
+/*!
+ * @brief Sets all TCD registers to default values.
+ *
+ * This function sets TCD registers for this channel to default values.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @note This function must not be called while the channel transfer is ongoing
+ * or it causes unpredictable results.
+ * @note This function enables the auto stop request feature.
+ */
+void EDMA_ResetChannel(DMA_Type *base, uint32_t channel);
+
+/*!
+ * @brief Configures the eDMA transfer attribute.
+ *
+ * This function configures the transfer attribute, including source address, destination address,
+ * transfer size, address offset, and so on. It also configures the scatter gather feature if the
+ * user supplies the TCD address.
+ * Example:
+ * @code
+ * edma_transfer_t config;
+ * edma_tcd_t tcd;
+ * config.srcAddr = ..;
+ * config.destAddr = ..;
+ * ...
+ * EDMA_SetTransferConfig(DMA0, channel, &config, &stcd);
+ * @endcode
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @param config Pointer to eDMA transfer configuration structure.
+ * @param nextTcd Point to TCD structure. It can be NULL if users
+ * do not want to enable scatter/gather feature.
+ * @note If nextTcd is not NULL, it means scatter gather feature is enabled
+ * and DREQ bit is cleared in the previous transfer configuration, which
+ * is set in the eDMA_ResetChannel.
+ */
+void EDMA_SetTransferConfig(DMA_Type *base,
+ uint32_t channel,
+ const edma_transfer_config_t *config,
+ edma_tcd_t *nextTcd);
+
+/*!
+ * @brief Configures the eDMA minor offset feature.
+ *
+ * The minor offset means that the signed-extended value is added to the source address or destination
+ * address after each minor loop.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @param config A pointer to the minor offset configuration structure.
+ */
+void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config);
+
+/*!
+ * @brief Configures the eDMA channel preemption feature.
+ *
+ * This function configures the channel preemption attribute and the priority of the channel.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number
+ * @param config A pointer to the channel preemption configuration structure.
+ */
+static inline void EDMA_SetChannelPreemptionConfig(DMA_Type *base,
+ uint32_t channel,
+ const edma_channel_Preemption_config_t *config)
+{
+ assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+ assert(config != NULL);
+
+ DMA_DCHPRIn(base, channel) =
+ (DMA_DCHPRI0_DPA(!config->enablePreemptAbility) | DMA_DCHPRI0_ECP(config->enableChannelPreemption) |
+ DMA_DCHPRI0_CHPRI(config->channelPriority));
+}
+
+/*!
+ * @brief Sets the channel link for the eDMA transfer.
+ *
+ * This function configures either the minor link or the major link mode. The minor link means that the channel link is
+ * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is
+ * exhausted.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @param type A channel link type, which can be one of the following:
+ * @arg kEDMA_LinkNone
+ * @arg kEDMA_MinorLink
+ * @arg kEDMA_MajorLink
+ * @param linkedChannel The linked channel number.
+ * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
+ */
+void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel);
+
+/*!
+ * @brief Sets the bandwidth for the eDMA transfer.
+ *
+ * Because the eDMA processes the minor loop, it continuously generates read/write sequences
+ * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of
+ * each read/write access to control the bus request bandwidth seen by the crossbar switch.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @param bandWidth A bandwidth setting, which can be one of the following:
+ * @arg kEDMABandwidthStallNone
+ * @arg kEDMABandwidthStall4Cycle
+ * @arg kEDMABandwidthStall8Cycle
+ */
+void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth);
+
+/*!
+ * @brief Sets the source modulo and the destination modulo for the eDMA transfer.
+ *
+ * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
+ * calculation is performed or the original register value. It provides the ability to implement a circular data
+ * queue easily.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @param srcModulo A source modulo value.
+ * @param destModulo A destination modulo value.
+ */
+void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo);
+
+#if defined(FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT) && FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT
+/*!
+ * @brief Enables an async request for the eDMA transfer.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @param enable The command to enable (true) or disable (false).
+ */
+static inline void EDMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, bool enable)
+{
+ assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+ base->EARS = (base->EARS & (~(1U << channel))) | ((uint32_t)enable << channel);
+}
+#endif /* FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT */
+
+/*!
+ * @brief Enables an auto stop request for the eDMA transfer.
+ *
+ * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @param enable The command to enable (true) or disable (false).
+ */
+static inline void EDMA_EnableAutoStopRequest(DMA_Type *base, uint32_t channel, bool enable)
+{
+ assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+ base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable);
+}
+
+/*!
+ * @brief Enables the interrupt source for the eDMA transfer.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @param mask The mask of interrupt source to be set. Users need to use
+ * the defined edma_interrupt_enable_t type.
+ */
+void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask);
+
+/*!
+ * @brief Disables the interrupt source for the eDMA transfer.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @param mask The mask of the interrupt source to be set. Use
+ * the defined edma_interrupt_enable_t type.
+ */
+void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask);
+
+/* @} */
+/*!
+ * @name eDMA TCD Operation
+ * @{
+ */
+
+/*!
+ * @brief Sets all fields to default values for the TCD structure.
+ *
+ * This function sets all fields for this TCD structure to default value.
+ *
+ * @param tcd Pointer to the TCD structure.
+ * @note This function enables the auto stop request feature.
+ */
+void EDMA_TcdReset(edma_tcd_t *tcd);
+
+/*!
+ * @brief Configures the eDMA TCD transfer attribute.
+ *
+ * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers.
+ * The STCD is used in the scatter-gather mode.
+ * This function configures the TCD transfer attribute, including source address, destination address,
+ * transfer size, address offset, and so on. It also configures the scatter gather feature if the
+ * user supplies the next TCD address.
+ * Example:
+ * @code
+ * edma_transfer_t config = {
+ * ...
+ * }
+ * edma_tcd_t tcd __aligned(32);
+ * edma_tcd_t nextTcd __aligned(32);
+ * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);
+ * @endcode
+ *
+ * @param tcd Pointer to the TCD structure.
+ * @param config Pointer to eDMA transfer configuration structure.
+ * @param nextTcd Pointer to the next TCD structure. It can be NULL if users
+ * do not want to enable scatter/gather feature.
+ * @note TCD address should be 32 bytes aligned or it causes an eDMA error.
+ * @note If the nextTcd is not NULL, the scatter gather feature is enabled
+ * and DREQ bit is cleared in the previous transfer configuration, which
+ * is set in the EDMA_TcdReset.
+ */
+void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd);
+
+/*!
+ * @brief Configures the eDMA TCD minor offset feature.
+ *
+ * A minor offset is a signed-extended value added to the source address or a destination
+ * address after each minor loop.
+ *
+ * @param tcd A point to the TCD structure.
+ * @param config A pointer to the minor offset configuration structure.
+ */
+void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config);
+
+/*!
+ * @brief Sets the channel link for the eDMA TCD.
+ *
+ * This function configures either a minor link or a major link. The minor link means the channel link is
+ * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is
+ * exhausted.
+ *
+ * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
+ * @param tcd Point to the TCD structure.
+ * @param type Channel link type, it can be one of:
+ * @arg kEDMA_LinkNone
+ * @arg kEDMA_MinorLink
+ * @arg kEDMA_MajorLink
+ * @param linkedChannel The linked channel number.
+ */
+void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel);
+
+/*!
+ * @brief Sets the bandwidth for the eDMA TCD.
+ *
+ * Because the eDMA processes the minor loop, it continuously generates read/write sequences
+ * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of
+ * each read/write access to control the bus request bandwidth seen by the crossbar switch.
+ * @param tcd A pointer to the TCD structure.
+ * @param bandWidth A bandwidth setting, which can be one of the following:
+ * @arg kEDMABandwidthStallNone
+ * @arg kEDMABandwidthStall4Cycle
+ * @arg kEDMABandwidthStall8Cycle
+ */
+static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth)
+{
+ assert(tcd != NULL);
+ assert(((uint32_t)tcd & 0x1FU) == 0);
+
+ tcd->CSR = (tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth);
+}
+
+/*!
+ * @brief Sets the source modulo and the destination modulo for the eDMA TCD.
+ *
+ * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
+ * calculation is performed or the original register value. It provides the ability to implement a circular data
+ * queue easily.
+ *
+ * @param tcd A pointer to the TCD structure.
+ * @param srcModulo A source modulo value.
+ * @param destModulo A destination modulo value.
+ */
+void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo);
+
+/*!
+ * @brief Sets the auto stop request for the eDMA TCD.
+ *
+ * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.
+ *
+ * @param tcd A pointer to the TCD structure.
+ * @param enable The command to enable (true) or disable (false).
+ */
+static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable)
+{
+ assert(tcd != NULL);
+ assert(((uint32_t)tcd & 0x1FU) == 0);
+
+ tcd->CSR = (tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable);
+}
+
+/*!
+ * @brief Enables the interrupt source for the eDMA TCD.
+ *
+ * @param tcd Point to the TCD structure.
+ * @param mask The mask of interrupt source to be set. Users need to use
+ * the defined edma_interrupt_enable_t type.
+ */
+void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask);
+
+/*!
+ * @brief Disables the interrupt source for the eDMA TCD.
+ *
+ * @param tcd Point to the TCD structure.
+ * @param mask The mask of interrupt source to be set. Users need to use
+ * the defined edma_interrupt_enable_t type.
+ */
+void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask);
+
+/*! @} */
+/*!
+ * @name eDMA Channel Transfer Operation
+ * @{
+ */
+
+/*!
+ * @brief Enables the eDMA hardware channel request.
+ *
+ * This function enables the hardware channel request.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ */
+static inline void EDMA_EnableChannelRequest(DMA_Type *base, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+ base->SERQ = DMA_SERQ_SERQ(channel);
+}
+
+/*!
+ * @brief Disables the eDMA hardware channel request.
+ *
+ * This function disables the hardware channel request.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ */
+static inline void EDMA_DisableChannelRequest(DMA_Type *base, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+ base->CERQ = DMA_CERQ_CERQ(channel);
+}
+
+/*!
+ * @brief Starts the eDMA transfer by using the software trigger.
+ *
+ * This function starts a minor loop transfer.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ */
+static inline void EDMA_TriggerChannelStart(DMA_Type *base, uint32_t channel)
+{
+ assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+ base->SSRT = DMA_SSRT_SSRT(channel);
+}
+
+/*! @} */
+/*!
+ * @name eDMA Channel Status Operation
+ * @{
+ */
+
+/*!
+ * @brief Gets the remaining major loop count from the eDMA current channel TCD.
+ *
+ * This function checks the TCD (Task Control Descriptor) status for a specified
+ * eDMA channel and returns the number of major loop count that has not finished.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @return Major loop count which has not been transferred yet for the current TCD.
+ * @note 1. This function can only be used to get unfinished major loop count of transfer without
+ * the next TCD, or it might be inaccuracy.
+ * 2. The unfinished/remaining transfer bytes cannot be obtained directly from registers while
+ * the channel is running.
+ * Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO
+ * register is needed while the eDMA IP does not support getting it while a channel is active.
+ * In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine
+ * is working with while a channel is running.
+ * Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example
+ * copied before enabling the channel) is needed. The formula to calculate it is shown below:
+ * RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured)
+ */
+uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel);
+
+/*!
+ * @brief Gets the eDMA channel error status flags.
+ *
+ * @param base eDMA peripheral base address.
+ * @return The mask of error status flags. Users need to use the
+* _edma_error_status_flags type to decode the return variables.
+ */
+static inline uint32_t EDMA_GetErrorStatusFlags(DMA_Type *base)
+{
+ return base->ES;
+}
+
+/*!
+ * @brief Gets the eDMA channel status flags.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @return The mask of channel status flags. Users need to use the
+ * _edma_channel_status_flags type to decode the return variables.
+ */
+uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel);
+
+/*!
+ * @brief Clears the eDMA channel status flags.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @param mask The mask of channel status to be cleared. Users need to use
+ * the defined _edma_channel_status_flags type.
+ */
+void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask);
+
+/*! @} */
+/*!
+ * @name eDMA Transactional Operation
+ */
+
+/*!
+ * @brief Creates the eDMA handle.
+ *
+ * This function is called if using the transactional API for eDMA. This function
+ * initializes the internal state of the eDMA handle.
+ *
+ * @param handle eDMA handle pointer. The eDMA handle stores callback function and
+ * parameters.
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ */
+void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel);
+
+/*!
+ * @brief Installs the TCDs memory pool into the eDMA handle.
+ *
+ * This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used
+ * while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block
+ * (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer.
+ * Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer.
+ *
+ * @param handle eDMA handle pointer.
+ * @param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned.
+ * @param tcdSize The number of TCD slots.
+ */
+void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize);
+
+/*!
+ * @brief Installs a callback function for the eDMA transfer.
+ *
+ * This callback is called in the eDMA IRQ handler. Use the callback to do something after
+ * the current major loop transfer completes. This function will be called every time one tcd finished transfer.
+ *
+ * @param handle eDMA handle pointer.
+ * @param callback eDMA callback function pointer.
+ * @param userData A parameter for the callback function.
+ */
+void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData);
+
+/*!
+ * @brief Prepares the eDMA transfer structure.
+ *
+ * This function prepares the transfer configuration structure according to the user input.
+ *
+ * @param config The user configuration structure of type edma_transfer_t.
+ * @param srcAddr eDMA transfer source address.
+ * @param srcWidth eDMA transfer source address width(bytes).
+ * @param destAddr eDMA transfer destination address.
+ * @param destWidth eDMA transfer destination address width(bytes).
+ * @param bytesEachRequest eDMA transfer bytes per channel request.
+ * @param transferBytes eDMA transfer bytes to be transferred.
+ * @param type eDMA transfer type.
+ * @note The data address and the data width must be consistent. For example, if the SRC
+ * is 4 bytes, the source address must be 4 bytes aligned, or it results in
+ * source address error (SAE).
+ */
+void EDMA_PrepareTransfer(edma_transfer_config_t *config,
+ void *srcAddr,
+ uint32_t srcWidth,
+ void *destAddr,
+ uint32_t destWidth,
+ uint32_t bytesEachRequest,
+ uint32_t transferBytes,
+ edma_transfer_type_t type);
+
+/*!
+ * @brief Submits the eDMA transfer request.
+ *
+ * This function submits the eDMA transfer request according to the transfer configuration structure.
+ * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool.
+ * The tcd pools is setup by call function EDMA_InstallTCDMemory before.
+ *
+ * @param handle eDMA handle pointer.
+ * @param config Pointer to eDMA transfer configuration structure.
+ * @retval kStatus_EDMA_Success It means submit transfer request succeed.
+ * @retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed.
+ * @retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later.
+ */
+status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config);
+
+/*!
+ * @brief eDMA starts transfer.
+ *
+ * This function enables the channel request. Users can call this function after submitting the transfer request
+ * or before submitting the transfer request.
+ *
+ * @param handle eDMA handle pointer.
+ */
+void EDMA_StartTransfer(edma_handle_t *handle);
+
+/*!
+ * @brief eDMA stops transfer.
+ *
+ * This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer()
+ * again to resume the transfer.
+ *
+ * @param handle eDMA handle pointer.
+ */
+void EDMA_StopTransfer(edma_handle_t *handle);
+
+/*!
+ * @brief eDMA aborts transfer.
+ *
+ * This function disables the channel request and clear transfer status bits.
+ * Users can submit another transfer after calling this API.
+ *
+ * @param handle DMA handle pointer.
+ */
+void EDMA_AbortTransfer(edma_handle_t *handle);
+
+/*!
+ * @brief Get unused TCD slot number.
+ *
+ * This function gets current tcd index which is run. If the TCD pool pointer is NULL, it will return 0.
+ *
+ * @param handle DMA handle pointer.
+ * @return The unused tcd slot number.
+ */
+static inline uint32_t EDMA_GetUnusedTCDNumber(edma_handle_t *handle)
+{
+ return (handle->tcdSize - handle->tcdUsed);
+}
+
+/*!
+ * @brief Get the next tcd address.
+ *
+ * This function gets the next tcd address. If this is last TCD, return 0.
+ *
+ * @param handle DMA handle pointer.
+ * @return The next TCD address.
+ */
+static inline uint32_t EDMA_GetNextTCDAddress(edma_handle_t *handle)
+{
+ return (handle->base->TCD[handle->channel].DLAST_SGA);
+}
+
+/*!
+ * @brief eDMA IRQ handler for the current major loop transfer completion.
+ *
+ * This function clears the channel major interrupt flag and calls
+ * the callback function if it is not NULL.
+ *
+ * Note:
+ * For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed.
+ * These include the final address adjustments and reloading of the BITER field into the CITER.
+ * Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from
+ * memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled).
+ *
+ * For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine.
+ * As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index
+ * in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be
+ * (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have
+ * been loaded into the eDMA engine at this point already.).
+ *
+ * For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not
+ * load a new TCD) from the memory pool to the eDMA engine when major loop completes.
+ * Therefore, ensure that the header and tcdUsed updated are identical for them.
+ * tcdUsed are both 0 in this case as no TCD to be loaded.
+ *
+ * See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for
+ * further details.
+ *
+ * @param handle eDMA handle pointer.
+ */
+void EDMA_HandleIRQ(edma_handle_t *handle);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/* @} */
+
+#endif /*_FSL_EDMA_H_*/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/fsl_smc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/fsl_smc.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,510 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_smc.h"
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.smc"
+#endif
+
+typedef void (*smc_stop_ram_func_t)(void);
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static void SMC_EnterStopRamFunc(void);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static uint32_t g_savedPrimask;
+
+/*
+ * The ram function code is:
+ *
+ * uint32_t i;
+ * for (i=0; i<0x8; i++)
+ * {
+ * __NOP();
+ * }
+ * __DSB();
+ * __WFI();
+ * __ISB();
+ *
+ * When entring the stop modes, the flash prefetch might be interrupted, thus
+ * the prefetched code or data might be broken. To make sure the flash is idle
+ * when entring the stop modes, the code is moved to ram. And delay for a while
+ * before WFI to make sure previous flash prefetch is finished.
+ *
+ * Only need to do like this when code is in flash, if code is in rom or ram,
+ * this is not necessary.
+ */
+static uint16_t s_stopRamFuncArray[] = {
+ 0x2000, /* MOVS R0, #0 */
+ 0x2808, /* CMP R0, #8 */
+ 0xD202, /* BCS.N */
+ 0xBF00, /* NOP */
+ 0x1C40, /* ADDS R0, R0, #1 */
+ 0xE7FA, /* B.N */
+ 0xF3BF, 0x8F4F, /* DSB */
+ 0xBF30, /* WFI */
+ 0xF3BF, 0x8F6F, /* ISB */
+ 0x4770, /* BX LR */
+};
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static void SMC_EnterStopRamFunc(void)
+{
+ uint32_t ramFuncEntry = ((uint32_t)(s_stopRamFuncArray)) + 1U;
+ smc_stop_ram_func_t stopRamFunc = (smc_stop_ram_func_t)ramFuncEntry;
+ stopRamFunc();
+}
+
+#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM)
+/*!
+ * brief Gets the SMC parameter.
+ *
+ * This function gets the SMC parameter including the enabled power mdoes.
+ *
+ * param base SMC peripheral base address.
+ * param param Pointer to the SMC param structure.
+ */
+void SMC_GetParam(SMC_Type *base, smc_param_t *param)
+{
+ uint32_t reg = base->PARAM;
+ param->hsrunEnable = (bool)(reg & SMC_PARAM_EHSRUN_MASK);
+ param->llsEnable = (bool)(reg & SMC_PARAM_ELLS_MASK);
+ param->lls2Enable = (bool)(reg & SMC_PARAM_ELLS2_MASK);
+ param->vlls0Enable = (bool)(reg & SMC_PARAM_EVLLS0_MASK);
+}
+#endif /* FSL_FEATURE_SMC_HAS_PARAM */
+
+/*!
+ * brief Prepares to enter stop modes.
+ *
+ * This function should be called before entering STOP/VLPS/LLS/VLLS modes.
+ */
+void SMC_PreEnterStopModes(void)
+{
+ g_savedPrimask = DisableGlobalIRQ();
+ __ISB();
+}
+
+/*!
+ * brief Recovers after wake up from stop modes.
+ *
+ * This function should be called after wake up from STOP/VLPS/LLS/VLLS modes.
+ * It is used with ref SMC_PreEnterStopModes.
+ */
+void SMC_PostExitStopModes(void)
+{
+ EnableGlobalIRQ(g_savedPrimask);
+ __ISB();
+}
+
+/*!
+ * brief Prepares to enter wait modes.
+ *
+ * This function should be called before entering WAIT/VLPW modes.
+ */
+void SMC_PreEnterWaitModes(void)
+{
+ g_savedPrimask = DisableGlobalIRQ();
+ __ISB();
+}
+
+/*!
+ * brief Recovers after wake up from stop modes.
+ *
+ * This function should be called after wake up from WAIT/VLPW modes.
+ * It is used with ref SMC_PreEnterWaitModes.
+ */
+void SMC_PostExitWaitModes(void)
+{
+ EnableGlobalIRQ(g_savedPrimask);
+ __ISB();
+}
+
+/*!
+ * brief Configures the system to RUN power mode.
+ *
+ * param base SMC peripheral base address.
+ * return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeRun(SMC_Type *base)
+{
+ uint8_t reg;
+
+ reg = base->PMCTRL;
+ /* configure Normal RUN mode */
+ reg &= ~SMC_PMCTRL_RUNM_MASK;
+ reg |= (kSMC_RunNormal << SMC_PMCTRL_RUNM_SHIFT);
+ base->PMCTRL = reg;
+
+ return kStatus_Success;
+}
+
+#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
+/*!
+ * brief Configures the system to HSRUN power mode.
+ *
+ * param base SMC peripheral base address.
+ * return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeHsrun(SMC_Type *base)
+{
+ uint8_t reg;
+
+ reg = base->PMCTRL;
+ /* configure High Speed RUN mode */
+ reg &= ~SMC_PMCTRL_RUNM_MASK;
+ reg |= (kSMC_Hsrun << SMC_PMCTRL_RUNM_SHIFT);
+ base->PMCTRL = reg;
+
+ return kStatus_Success;
+}
+#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
+
+/*!
+ * brief Configures the system to WAIT power mode.
+ *
+ * param base SMC peripheral base address.
+ * return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeWait(SMC_Type *base)
+{
+ /* configure Normal Wait mode */
+ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+ __DSB();
+ __WFI();
+ __ISB();
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Configures the system to Stop power mode.
+ *
+ * param base SMC peripheral base address.
+ * param option Partial Stop mode option.
+ * return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option)
+{
+ uint8_t reg;
+
+#if (defined(FSL_FEATURE_SMC_HAS_PSTOPO) && FSL_FEATURE_SMC_HAS_PSTOPO)
+ /* configure the Partial Stop mode in Normal Stop mode */
+ reg = base->STOPCTRL;
+ reg &= ~SMC_STOPCTRL_PSTOPO_MASK;
+ reg |= ((uint32_t)option << SMC_STOPCTRL_PSTOPO_SHIFT);
+ base->STOPCTRL = reg;
+#endif
+
+ /* configure Normal Stop mode */
+ reg = base->PMCTRL;
+ reg &= ~SMC_PMCTRL_STOPM_MASK;
+ reg |= (kSMC_StopNormal << SMC_PMCTRL_STOPM_SHIFT);
+ base->PMCTRL = reg;
+
+ /* Set the SLEEPDEEP bit to enable deep sleep mode (stop mode) */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ /* read back to make sure the configuration valid before enter stop mode */
+ (void)base->PMCTRL;
+ SMC_EnterStopRamFunc();
+
+ /* check whether the power mode enter Stop mode succeed */
+ if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
+ {
+ return kStatus_SMC_StopAbort;
+ }
+ else
+ {
+ return kStatus_Success;
+ }
+}
+
+/*!
+ * brief Configures the system to VLPR power mode.
+ *
+ * param base SMC peripheral base address.
+ * return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlpr(SMC_Type *base
+#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
+ ,
+ bool wakeupMode
+#endif
+ )
+{
+ uint8_t reg;
+
+ reg = base->PMCTRL;
+#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
+ /* configure whether the system remains in VLP mode on an interrupt */
+ if (wakeupMode)
+ {
+ /* exits to RUN mode on an interrupt */
+ reg |= SMC_PMCTRL_LPWUI_MASK;
+ }
+ else
+ {
+ /* remains in VLP mode on an interrupt */
+ reg &= ~SMC_PMCTRL_LPWUI_MASK;
+ }
+#endif /* FSL_FEATURE_SMC_HAS_LPWUI */
+
+ /* configure VLPR mode */
+ reg &= ~SMC_PMCTRL_RUNM_MASK;
+ reg |= (kSMC_RunVlpr << SMC_PMCTRL_RUNM_SHIFT);
+ base->PMCTRL = reg;
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Configures the system to VLPW power mode.
+ *
+ * param base SMC peripheral base address.
+ * return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlpw(SMC_Type *base)
+{
+ /* configure VLPW mode */
+ /* Set the SLEEPDEEP bit to enable deep sleep mode */
+ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+ __DSB();
+ __WFI();
+ __ISB();
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Configures the system to VLPS power mode.
+ *
+ * param base SMC peripheral base address.
+ * return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlps(SMC_Type *base)
+{
+ uint8_t reg;
+
+ /* configure VLPS mode */
+ reg = base->PMCTRL;
+ reg &= ~SMC_PMCTRL_STOPM_MASK;
+ reg |= (kSMC_StopVlps << SMC_PMCTRL_STOPM_SHIFT);
+ base->PMCTRL = reg;
+
+ /* Set the SLEEPDEEP bit to enable deep sleep mode */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ /* read back to make sure the configuration valid before enter stop mode */
+ (void)base->PMCTRL;
+ SMC_EnterStopRamFunc();
+
+ /* check whether the power mode enter VLPS mode succeed */
+ if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
+ {
+ return kStatus_SMC_StopAbort;
+ }
+ else
+ {
+ return kStatus_Success;
+ }
+}
+
+#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
+/*!
+ * brief Configures the system to LLS power mode.
+ *
+ * param base SMC peripheral base address.
+ * return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeLls(SMC_Type *base
+#if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \
+ (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO))
+ ,
+ const smc_power_mode_lls_config_t *config
+#endif
+ )
+{
+ uint8_t reg;
+
+ /* configure to LLS mode */
+ reg = base->PMCTRL;
+ reg &= ~SMC_PMCTRL_STOPM_MASK;
+ reg |= (kSMC_StopLls << SMC_PMCTRL_STOPM_SHIFT);
+ base->PMCTRL = reg;
+
+/* configure LLS sub-mode*/
+#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
+ reg = base->STOPCTRL;
+ reg &= ~SMC_STOPCTRL_LLSM_MASK;
+ reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT);
+ base->STOPCTRL = reg;
+#endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */
+
+#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)
+ if (config->enableLpoClock)
+ {
+ base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK;
+ }
+ else
+ {
+ base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK;
+ }
+#endif /* FSL_FEATURE_SMC_HAS_LPOPO */
+
+ /* Set the SLEEPDEEP bit to enable deep sleep mode */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ /* read back to make sure the configuration valid before enter stop mode */
+ (void)base->PMCTRL;
+ SMC_EnterStopRamFunc();
+
+ /* check whether the power mode enter LLS mode succeed */
+ if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
+ {
+ return kStatus_SMC_StopAbort;
+ }
+ else
+ {
+ return kStatus_Success;
+ }
+}
+#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
+
+#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
+/*!
+ * brief Configures the system to VLLS power mode.
+ *
+ * param base SMC peripheral base address.
+ * param config The VLLS power mode configuration structure.
+ * return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config)
+{
+ uint8_t reg;
+
+#if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO)
+#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \
+ (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \
+ (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
+ if (config->subMode == kSMC_StopSub0)
+#endif
+ {
+ /* configure whether the Por Detect work in Vlls0 mode */
+ if (config->enablePorDetectInVlls0)
+ {
+#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
+ base->VLLSCTRL &= ~SMC_VLLSCTRL_PORPO_MASK;
+#else
+ base->STOPCTRL &= ~SMC_STOPCTRL_PORPO_MASK;
+#endif
+ }
+ else
+ {
+#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
+ base->VLLSCTRL |= SMC_VLLSCTRL_PORPO_MASK;
+#else
+ base->STOPCTRL |= SMC_STOPCTRL_PORPO_MASK;
+#endif
+ }
+ }
+#endif /* FSL_FEATURE_SMC_HAS_PORPO */
+
+#if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION)
+ else if (config->subMode == kSMC_StopSub2)
+ {
+ /* configure whether the Por Detect work in Vlls0 mode */
+ if (config->enableRam2InVlls2)
+ {
+#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
+ base->VLLSCTRL |= SMC_VLLSCTRL_RAM2PO_MASK;
+#else
+ base->STOPCTRL |= SMC_STOPCTRL_RAM2PO_MASK;
+#endif
+ }
+ else
+ {
+#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
+ base->VLLSCTRL &= ~SMC_VLLSCTRL_RAM2PO_MASK;
+#else
+ base->STOPCTRL &= ~SMC_STOPCTRL_RAM2PO_MASK;
+#endif
+ }
+ }
+ else
+ {
+ }
+#endif /* FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION */
+
+ /* configure to VLLS mode */
+ reg = base->PMCTRL;
+ reg &= ~SMC_PMCTRL_STOPM_MASK;
+ reg |= (kSMC_StopVlls << SMC_PMCTRL_STOPM_SHIFT);
+ base->PMCTRL = reg;
+
+/* configure the VLLS sub-mode */
+#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
+ reg = base->VLLSCTRL;
+ reg &= ~SMC_VLLSCTRL_VLLSM_MASK;
+ reg |= ((uint32_t)config->subMode << SMC_VLLSCTRL_VLLSM_SHIFT);
+ base->VLLSCTRL = reg;
+#else
+#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
+ reg = base->STOPCTRL;
+ reg &= ~SMC_STOPCTRL_LLSM_MASK;
+ reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT);
+ base->STOPCTRL = reg;
+#else
+ reg = base->STOPCTRL;
+ reg &= ~SMC_STOPCTRL_VLLSM_MASK;
+ reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_VLLSM_SHIFT);
+ base->STOPCTRL = reg;
+#endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */
+#endif
+
+#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)
+ if (config->enableLpoClock)
+ {
+ base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK;
+ }
+ else
+ {
+ base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK;
+ }
+#endif /* FSL_FEATURE_SMC_HAS_LPOPO */
+
+ /* Set the SLEEPDEEP bit to enable deep sleep mode */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ /* read back to make sure the configuration valid before enter stop mode */
+ (void)base->PMCTRL;
+ SMC_EnterStopRamFunc();
+
+ /* check whether the power mode enter LLS mode succeed */
+ if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
+ {
+ return kStatus_SMC_StopAbort;
+ }
+ else
+ {
+ return kStatus_Success;
+ }
+}
+#endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/fsl_smc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/fsl_smc.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,425 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_SMC_H_
+#define _FSL_SMC_H_
+
+#include "fsl_common.h"
+
+/*! @addtogroup smc */
+/*! @{ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief SMC driver version 2.0.4. */
+#define FSL_SMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
+/*@}*/
+
+/*!
+ * @brief Power Modes Protection
+ */
+typedef enum _smc_power_mode_protection
+{
+#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
+ kSMC_AllowPowerModeVlls = SMC_PMPROT_AVLLS_MASK, /*!< Allow Very-low-leakage Stop Mode. */
+#endif
+#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
+ kSMC_AllowPowerModeLls = SMC_PMPROT_ALLS_MASK, /*!< Allow Low-leakage Stop Mode. */
+#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
+ kSMC_AllowPowerModeVlp = SMC_PMPROT_AVLP_MASK, /*!< Allow Very-Low-power Mode. */
+#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
+ kSMC_AllowPowerModeHsrun = SMC_PMPROT_AHSRUN_MASK, /*!< Allow High-speed Run mode. */
+#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
+ kSMC_AllowPowerModeAll = (0U
+#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
+ |
+ SMC_PMPROT_AVLLS_MASK
+#endif
+#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
+ |
+ SMC_PMPROT_ALLS_MASK
+#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
+ |
+ SMC_PMPROT_AVLP_MASK
+#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
+ |
+ kSMC_AllowPowerModeHsrun
+#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
+ ) /*!< Allow all power mode. */
+} smc_power_mode_protection_t;
+
+/*!
+ * @brief Power Modes in PMSTAT
+ */
+typedef enum _smc_power_state
+{
+ kSMC_PowerStateRun = 0x01U << 0U, /*!< 0000_0001 - Current power mode is RUN */
+ kSMC_PowerStateStop = 0x01U << 1U, /*!< 0000_0010 - Current power mode is STOP */
+ kSMC_PowerStateVlpr = 0x01U << 2U, /*!< 0000_0100 - Current power mode is VLPR */
+ kSMC_PowerStateVlpw = 0x01U << 3U, /*!< 0000_1000 - Current power mode is VLPW */
+ kSMC_PowerStateVlps = 0x01U << 4U, /*!< 0001_0000 - Current power mode is VLPS */
+#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
+ kSMC_PowerStateLls = 0x01U << 5U, /*!< 0010_0000 - Current power mode is LLS */
+#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
+#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
+ kSMC_PowerStateVlls = 0x01U << 6U, /*!< 0100_0000 - Current power mode is VLLS */
+#endif
+#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
+ kSMC_PowerStateHsrun = 0x01U << 7U /*!< 1000_0000 - Current power mode is HSRUN */
+#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
+} smc_power_state_t;
+
+/*!
+ * @brief Run mode definition
+ */
+typedef enum _smc_run_mode
+{
+ kSMC_RunNormal = 0U, /*!< Normal RUN mode. */
+ kSMC_RunVlpr = 2U, /*!< Very-low-power RUN mode. */
+#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
+ kSMC_Hsrun = 3U /*!< High-speed Run mode (HSRUN). */
+#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
+} smc_run_mode_t;
+
+/*!
+ * @brief Stop mode definition
+ */
+typedef enum _smc_stop_mode
+{
+ kSMC_StopNormal = 0U, /*!< Normal STOP mode. */
+ kSMC_StopVlps = 2U, /*!< Very-low-power STOP mode. */
+#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
+ kSMC_StopLls = 3U, /*!< Low-leakage Stop mode. */
+#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
+#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
+ kSMC_StopVlls = 4U /*!< Very-low-leakage Stop mode. */
+#endif
+} smc_stop_mode_t;
+
+#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \
+ (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \
+ (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
+/*!
+ * @brief VLLS/LLS stop sub mode definition
+ */
+typedef enum _smc_stop_submode
+{
+ kSMC_StopSub0 = 0U, /*!< Stop submode 0, for VLLS0/LLS0. */
+ kSMC_StopSub1 = 1U, /*!< Stop submode 1, for VLLS1/LLS1. */
+ kSMC_StopSub2 = 2U, /*!< Stop submode 2, for VLLS2/LLS2. */
+ kSMC_StopSub3 = 3U /*!< Stop submode 3, for VLLS3/LLS3. */
+} smc_stop_submode_t;
+#endif
+
+/*!
+ * @brief Partial STOP option
+ */
+typedef enum _smc_partial_stop_mode
+{
+ kSMC_PartialStop = 0U, /*!< STOP - Normal Stop mode*/
+ kSMC_PartialStop1 = 1U, /*!< Partial Stop with both system and bus clocks disabled*/
+ kSMC_PartialStop2 = 2U, /*!< Partial Stop with system clock disabled and bus clock enabled*/
+} smc_partial_stop_option_t;
+
+/*!
+ * @brief SMC configuration status.
+ */
+enum _smc_status
+{
+ kStatus_SMC_StopAbort = MAKE_STATUS(kStatusGroup_POWER, 0) /*!< Entering Stop mode is abort*/
+};
+
+#if (defined(FSL_FEATURE_SMC_HAS_VERID) && FSL_FEATURE_SMC_HAS_VERID)
+/*!
+ * @brief IP version ID definition.
+ */
+typedef struct _smc_version_id
+{
+ uint16_t feature; /*!< Feature Specification Number. */
+ uint8_t minor; /*!< Minor version number. */
+ uint8_t major; /*!< Major version number. */
+} smc_version_id_t;
+#endif /* FSL_FEATURE_SMC_HAS_VERID */
+
+#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM)
+/*!
+ * @brief IP parameter definition.
+ */
+typedef struct _smc_param
+{
+ bool hsrunEnable; /*!< HSRUN mode enable. */
+ bool llsEnable; /*!< LLS mode enable. */
+ bool lls2Enable; /*!< LLS2 mode enable. */
+ bool vlls0Enable; /*!< VLLS0 mode enable. */
+} smc_param_t;
+#endif /* FSL_FEATURE_SMC_HAS_PARAM */
+
+#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \
+ (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)
+/*!
+ * @brief SMC Low-Leakage Stop power mode configuration.
+ */
+typedef struct _smc_power_mode_lls_config
+{
+#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
+ smc_stop_submode_t subMode; /*!< Low-leakage Stop sub-mode */
+#endif
+#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)
+ bool enableLpoClock; /*!< Enable LPO clock in LLS mode */
+#endif
+} smc_power_mode_lls_config_t;
+#endif /* (FSL_FEATURE_SMC_HAS_LLS_SUBMODE || FSL_FEATURE_SMC_HAS_LPOPO) */
+
+#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
+/*!
+ * @brief SMC Very Low-Leakage Stop power mode configuration.
+ */
+typedef struct _smc_power_mode_vlls_config
+{
+#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \
+ (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \
+ (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
+ smc_stop_submode_t subMode; /*!< Very Low-leakage Stop sub-mode */
+#endif
+#if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO)
+ bool enablePorDetectInVlls0; /*!< Enable Power on reset detect in VLLS mode */
+#endif
+#if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION)
+ bool enableRam2InVlls2; /*!< Enable RAM2 power in VLLS2 */
+#endif
+#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)
+ bool enableLpoClock; /*!< Enable LPO clock in VLLS mode */
+#endif
+} smc_power_mode_vlls_config_t;
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*! @name System mode controller APIs*/
+/*@{*/
+
+#if (defined(FSL_FEATURE_SMC_HAS_VERID) && FSL_FEATURE_SMC_HAS_VERID)
+/*!
+ * @brief Gets the SMC version ID.
+ *
+ * This function gets the SMC version ID, including major version number,
+ * minor version number, and feature specification number.
+ *
+ * @param base SMC peripheral base address.
+ * @param versionId Pointer to the version ID structure.
+ */
+static inline void SMC_GetVersionId(SMC_Type *base, smc_version_id_t *versionId)
+{
+ *((uint32_t *)versionId) = base->VERID;
+}
+#endif /* FSL_FEATURE_SMC_HAS_VERID */
+
+#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM)
+/*!
+ * @brief Gets the SMC parameter.
+ *
+ * This function gets the SMC parameter including the enabled power mdoes.
+ *
+ * @param base SMC peripheral base address.
+ * @param param Pointer to the SMC param structure.
+ */
+void SMC_GetParam(SMC_Type *base, smc_param_t *param);
+#endif
+
+/*!
+ * @brief Configures all power mode protection settings.
+ *
+ * This function configures the power mode protection settings for
+ * supported power modes in the specified chip family. The available power modes
+ * are defined in the smc_power_mode_protection_t. This should be done at an early
+ * system level initialization stage. See the reference manual for details.
+ * This register can only write once after the power reset.
+ *
+ * The allowed modes are passed as bit map. For example, to allow LLS and VLLS,
+ * use SMC_SetPowerModeProtection(kSMC_AllowPowerModeVlls | kSMC_AllowPowerModeVlps).
+ * To allow all modes, use SMC_SetPowerModeProtection(kSMC_AllowPowerModeAll).
+ *
+ * @param base SMC peripheral base address.
+ * @param allowedModes Bitmap of the allowed power modes.
+ */
+static inline void SMC_SetPowerModeProtection(SMC_Type *base, uint8_t allowedModes)
+{
+ base->PMPROT = allowedModes;
+}
+
+/*!
+ * @brief Gets the current power mode status.
+ *
+ * This function returns the current power mode status. After the application
+ * switches the power mode, it should always check the status to check whether it
+ * runs into the specified mode or not. The application should check
+ * this mode before switching to a different mode. The system requires that
+ * only certain modes can switch to other specific modes. See the
+ * reference manual for details and the smc_power_state_t for information about
+ * the power status.
+ *
+ * @param base SMC peripheral base address.
+ * @return Current power mode status.
+ */
+static inline smc_power_state_t SMC_GetPowerModeState(SMC_Type *base)
+{
+ return (smc_power_state_t)base->PMSTAT;
+}
+
+/*!
+ * @brief Prepares to enter stop modes.
+ *
+ * This function should be called before entering STOP/VLPS/LLS/VLLS modes.
+ */
+void SMC_PreEnterStopModes(void);
+
+/*!
+ * @brief Recovers after wake up from stop modes.
+ *
+ * This function should be called after wake up from STOP/VLPS/LLS/VLLS modes.
+ * It is used with @ref SMC_PreEnterStopModes.
+ */
+void SMC_PostExitStopModes(void);
+
+/*!
+ * @brief Prepares to enter wait modes.
+ *
+ * This function should be called before entering WAIT/VLPW modes.
+ */
+void SMC_PreEnterWaitModes(void);
+
+/*!
+ * @brief Recovers after wake up from stop modes.
+ *
+ * This function should be called after wake up from WAIT/VLPW modes.
+ * It is used with @ref SMC_PreEnterWaitModes.
+ */
+void SMC_PostExitWaitModes(void);
+
+/*!
+ * @brief Configures the system to RUN power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeRun(SMC_Type *base);
+
+#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
+/*!
+ * @brief Configures the system to HSRUN power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeHsrun(SMC_Type *base);
+#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
+
+/*!
+ * @brief Configures the system to WAIT power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeWait(SMC_Type *base);
+
+/*!
+ * @brief Configures the system to Stop power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @param option Partial Stop mode option.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option);
+
+#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
+/*!
+ * @brief Configures the system to VLPR power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @param wakeupMode Enter Normal Run mode if true, else stay in VLPR mode.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlpr(SMC_Type *base, bool wakeupMode);
+#else
+/*!
+ * @brief Configures the system to VLPR power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlpr(SMC_Type *base);
+#endif /* FSL_FEATURE_SMC_HAS_LPWUI */
+
+/*!
+ * @brief Configures the system to VLPW power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlpw(SMC_Type *base);
+
+/*!
+ * @brief Configures the system to VLPS power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlps(SMC_Type *base);
+
+#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
+#if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \
+ (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO))
+/*!
+ * @brief Configures the system to LLS power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @param config The LLS power mode configuration structure
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeLls(SMC_Type *base, const smc_power_mode_lls_config_t *config);
+#else
+/*!
+ * @brief Configures the system to LLS power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeLls(SMC_Type *base);
+#endif
+#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
+
+#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
+/*!
+ * @brief Configures the system to VLLS power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @param config The VLLS power mode configuration structure.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config);
+#endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_SMC_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/fsl_uart.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/fsl_uart.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1658 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_uart.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.uart"
+#endif
+
+/* UART transfer state. */
+enum _uart_tansfer_states
+{
+ kUART_TxIdle, /* TX idle. */
+ kUART_TxBusy, /* TX busy. */
+ kUART_RxIdle, /* RX idle. */
+ kUART_RxBusy, /* RX busy. */
+ kUART_RxFramingError, /* Rx framing error */
+ kUART_RxParityError /* Rx parity error */
+};
+
+/* Typedef for interrupt handler. */
+typedef void (*uart_isr_t)(UART_Type *base, uart_handle_t *handle);
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Check whether the RX ring buffer is full.
+ *
+ * @param handle UART handle pointer.
+ * @retval true RX ring buffer is full.
+ * @retval false RX ring buffer is not full.
+ */
+static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle);
+
+/*!
+ * @brief Read RX register using non-blocking method.
+ *
+ * This function reads data from the TX register directly, upper layer must make
+ * sure the RX register is full or TX FIFO has data before calling this function.
+ *
+ * @param base UART peripheral base address.
+ * @param data Start addresss of the buffer to store the received data.
+ * @param length Size of the buffer.
+ */
+static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length);
+
+/*!
+ * @brief Write to TX register using non-blocking method.
+ *
+ * This function writes data to the TX register directly, upper layer must make
+ * sure the TX register is empty or TX FIFO has empty room before calling this function.
+ *
+ * @note This function does not check whether all the data has been sent out to bus,
+ * so before disable TX, check kUART_TransmissionCompleteFlag to ensure the TX is
+ * finished.
+ *
+ * @param base UART peripheral base address.
+ * @param data Start address of the data to write.
+ * @param length Size of the buffer to be sent.
+ */
+static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Array of UART handle. */
+#if (defined(UART5))
+#define UART_HANDLE_ARRAY_SIZE 6
+#else /* UART5 */
+#if (defined(UART4))
+#define UART_HANDLE_ARRAY_SIZE 5
+#else /* UART4 */
+#if (defined(UART3))
+#define UART_HANDLE_ARRAY_SIZE 4
+#else /* UART3 */
+#if (defined(UART2))
+#define UART_HANDLE_ARRAY_SIZE 3
+#else /* UART2 */
+#if (defined(UART1))
+#define UART_HANDLE_ARRAY_SIZE 2
+#else /* UART1 */
+#if (defined(UART0))
+#define UART_HANDLE_ARRAY_SIZE 1
+#else /* UART0 */
+#error No UART instance.
+#endif /* UART 0 */
+#endif /* UART 1 */
+#endif /* UART 2 */
+#endif /* UART 3 */
+#endif /* UART 4 */
+#endif /* UART 5 */
+static uart_handle_t *s_uartHandle[UART_HANDLE_ARRAY_SIZE];
+/* Array of UART peripheral base address. */
+static UART_Type *const s_uartBases[] = UART_BASE_PTRS;
+
+/* Array of UART IRQ number. */
+static const IRQn_Type s_uartIRQ[] = UART_RX_TX_IRQS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/* Array of UART clock name. */
+static const clock_ip_name_t s_uartClock[] = UART_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/* UART ISR for transactional APIs. */
+static uart_isr_t s_uartIsr;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * brief Get the UART instance from peripheral base address.
+ *
+ * param base UART peripheral base address.
+ * return UART instance.
+ */
+uint32_t UART_GetInstance(UART_Type *base)
+{
+ uint32_t instance;
+ uint32_t uartArrayCount = (sizeof(s_uartBases) / sizeof(s_uartBases[0]));
+
+ /* Find the instance index from base address mappings. */
+ for (instance = 0; instance < uartArrayCount; instance++)
+ {
+ if (s_uartBases[instance] == base)
+ {
+ break;
+ }
+ }
+
+ assert(instance < uartArrayCount);
+
+ return instance;
+}
+
+/*!
+ * brief Get the length of received data in RX ring buffer.
+ *
+ * param handle UART handle pointer.
+ * return Length of received data in RX ring buffer.
+ */
+size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle)
+{
+ assert(handle);
+
+ size_t size;
+
+ if (handle->rxRingBufferTail > handle->rxRingBufferHead)
+ {
+ size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail);
+ }
+ else
+ {
+ size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail);
+ }
+
+ return size;
+}
+
+static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle)
+{
+ assert(handle);
+
+ bool full;
+
+ if (UART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U))
+ {
+ full = true;
+ }
+ else
+ {
+ full = false;
+ }
+
+ return full;
+}
+
+/*!
+ * brief Initializes a UART instance with a user configuration structure and peripheral clock.
+ *
+ * This function configures the UART module with the user-defined settings. The user can configure the configuration
+ * structure and also get the default configuration by using the UART_GetDefaultConfig() function.
+ * The example below shows how to use this API to configure UART.
+ * code
+ * uart_config_t uartConfig;
+ * uartConfig.baudRate_Bps = 115200U;
+ * uartConfig.parityMode = kUART_ParityDisabled;
+ * uartConfig.stopBitCount = kUART_OneStopBit;
+ * uartConfig.txFifoWatermark = 0;
+ * uartConfig.rxFifoWatermark = 1;
+ * UART_Init(UART1, &uartConfig, 20000000U);
+ * endcode
+ *
+ * param base UART peripheral base address.
+ * param config Pointer to the user-defined configuration structure.
+ * param srcClock_Hz UART clock source frequency in HZ.
+ * retval kStatus_UART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * retval kStatus_Success Status UART initialize succeed
+ */
+status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz)
+{
+ assert(config);
+ assert(config->baudRate_Bps);
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+ assert(FSL_FEATURE_UART_FIFO_SIZEn(base) >= config->txFifoWatermark);
+ assert(FSL_FEATURE_UART_FIFO_SIZEn(base) >= config->rxFifoWatermark);
+#endif
+
+ uint16_t sbr = 0;
+ uint8_t temp = 0;
+ uint32_t baudDiff = 0;
+
+ /* Calculate the baud rate modulo divisor, sbr*/
+ sbr = srcClock_Hz / (config->baudRate_Bps * 16);
+ /* set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate */
+ if (sbr == 0)
+ {
+ sbr = 1;
+ }
+#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
+ /* Determine if a fractional divider is needed to fine tune closer to the
+ * desired baud, each value of brfa is in 1/32 increments,
+ * hence the multiply-by-32. */
+ uint32_t tempBaud = 0;
+
+ uint16_t brfa = (2 * srcClock_Hz / (config->baudRate_Bps)) - 32 * sbr;
+
+ /* Calculate the baud rate based on the temporary SBR values and BRFA */
+ tempBaud = (srcClock_Hz * 2 / ((sbr * 32 + brfa)));
+ baudDiff =
+ (tempBaud > config->baudRate_Bps) ? (tempBaud - config->baudRate_Bps) : (config->baudRate_Bps - tempBaud);
+
+#else
+ /* Calculate the baud rate based on the temporary SBR values */
+ baudDiff = (srcClock_Hz / (sbr * 16)) - config->baudRate_Bps;
+
+ /* Select the better value between sbr and (sbr + 1) */
+ if (baudDiff > (config->baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1)))))
+ {
+ baudDiff = config->baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1)));
+ sbr++;
+ }
+#endif
+
+ /* next, check to see if actual baud rate is within 3% of desired baud rate
+ * based on the calculate SBR value */
+ if (baudDiff > ((config->baudRate_Bps / 100) * 3))
+ {
+ /* Unacceptable baud rate difference of more than 3%*/
+ return kStatus_UART_BaudrateNotSupport;
+ }
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Enable uart clock */
+ CLOCK_EnableClock(s_uartClock[UART_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+ /* Disable UART TX RX before setting. */
+ base->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK);
+
+ /* Write the sbr value to the BDH and BDL registers*/
+ base->BDH = (base->BDH & ~UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8);
+ base->BDL = (uint8_t)sbr;
+
+#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
+ /* Write the brfa value to the register*/
+ base->C4 = (base->C4 & ~UART_C4_BRFA_MASK) | (brfa & UART_C4_BRFA_MASK);
+#endif
+
+ /* Set bit count/parity mode/idle type. */
+ temp = base->C1 & ~(UART_C1_PE_MASK | UART_C1_PT_MASK | UART_C1_M_MASK | UART_C1_ILT_MASK);
+
+ temp |= UART_C1_ILT(config->idleType);
+
+ if (kUART_ParityDisabled != config->parityMode)
+ {
+ temp |= (UART_C1_M_MASK | (uint8_t)config->parityMode);
+ }
+
+ base->C1 = temp;
+
+#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT
+ /* Set stop bit per char */
+ base->BDH = (base->BDH & ~UART_BDH_SBNS_MASK) | UART_BDH_SBNS((uint8_t)config->stopBitCount);
+#endif
+
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+ /* Set tx/rx FIFO watermark
+ Note:
+ Take care of the RX FIFO, RX interrupt request only assert when received bytes
+ equal or more than RX water mark, there is potential issue if RX water
+ mark larger than 1.
+ For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and
+ 5 bytes are received. the last byte will be saved in FIFO but not trigger
+ RX interrupt because the water mark is 2.
+ */
+ base->TWFIFO = config->txFifoWatermark;
+ base->RWFIFO = config->rxFifoWatermark;
+
+ /* Enable tx/rx FIFO */
+ base->PFIFO |= (UART_PFIFO_TXFE_MASK | UART_PFIFO_RXFE_MASK);
+
+ /* Flush FIFO */
+ base->CFIFO |= (UART_CFIFO_TXFLUSH_MASK | UART_CFIFO_RXFLUSH_MASK);
+#endif
+#if defined(FSL_FEATURE_UART_HAS_MODEM_SUPPORT) && FSL_FEATURE_UART_HAS_MODEM_SUPPORT
+ if (config->enableRxRTS)
+ {
+ /* Enable receiver RTS(request-to-send) function. */
+ base->MODEM |= UART_MODEM_RXRTSE_MASK;
+ }
+ if (config->enableTxCTS)
+ {
+ /* Enable transmitter CTS(clear-to-send) function. */
+ base->MODEM |= UART_MODEM_TXCTSE_MASK;
+ }
+#endif
+
+ /* Enable TX/RX base on configure structure. */
+ temp = base->C2;
+
+ if (config->enableTx)
+ {
+ temp |= UART_C2_TE_MASK;
+ }
+
+ if (config->enableRx)
+ {
+ temp |= UART_C2_RE_MASK;
+ }
+
+ base->C2 = temp;
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Deinitializes a UART instance.
+ *
+ * This function waits for TX complete, disables TX and RX, and disables the UART clock.
+ *
+ * param base UART peripheral base address.
+ */
+void UART_Deinit(UART_Type *base)
+{
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+ /* Wait tx FIFO send out*/
+ while (0 != base->TCFIFO)
+ {
+ }
+#endif
+ /* Wait last char shoft out */
+ while (0 == (base->S1 & UART_S1_TC_MASK))
+ {
+ }
+
+ /* Disable the module. */
+ base->C2 = 0;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Disable uart clock */
+ CLOCK_DisableClock(s_uartClock[UART_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Gets the default configuration structure.
+ *
+ * This function initializes the UART configuration structure to a default value. The default
+ * values are as follows.
+ * uartConfig->baudRate_Bps = 115200U;
+ * uartConfig->bitCountPerChar = kUART_8BitsPerChar;
+ * uartConfig->parityMode = kUART_ParityDisabled;
+ * uartConfig->stopBitCount = kUART_OneStopBit;
+ * uartConfig->txFifoWatermark = 0;
+ * uartConfig->rxFifoWatermark = 1;
+ * uartConfig->idleType = kUART_IdleTypeStartBit;
+ * uartConfig->enableTx = false;
+ * uartConfig->enableRx = false;
+ *
+ * param config Pointer to configuration structure.
+ */
+void UART_GetDefaultConfig(uart_config_t *config)
+{
+ assert(config);
+
+ /* Initializes the configure structure to zero. */
+ memset(config, 0, sizeof(*config));
+
+ config->baudRate_Bps = 115200U;
+ config->parityMode = kUART_ParityDisabled;
+#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT
+ config->stopBitCount = kUART_OneStopBit;
+#endif
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+ config->txFifoWatermark = 0;
+ config->rxFifoWatermark = 1;
+#endif
+#if defined(FSL_FEATURE_UART_HAS_MODEM_SUPPORT) && FSL_FEATURE_UART_HAS_MODEM_SUPPORT
+ config->enableRxRTS = false;
+ config->enableTxCTS = false;
+#endif
+ config->idleType = kUART_IdleTypeStartBit;
+ config->enableTx = false;
+ config->enableRx = false;
+}
+
+/*!
+ * brief Sets the UART instance baud rate.
+ *
+ * This function configures the UART module baud rate. This function is used to update
+ * the UART module baud rate after the UART module is initialized by the UART_Init.
+ * code
+ * UART_SetBaudRate(UART1, 115200U, 20000000U);
+ * endcode
+ *
+ * param base UART peripheral base address.
+ * param baudRate_Bps UART baudrate to be set.
+ * param srcClock_Hz UART clock source freqency in Hz.
+ * retval kStatus_UART_BaudrateNotSupport Baudrate is not support in the current clock source.
+ * retval kStatus_Success Set baudrate succeeded.
+ */
+status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
+{
+ assert(baudRate_Bps);
+
+ uint16_t sbr = 0;
+ uint32_t baudDiff = 0;
+ uint8_t oldCtrl;
+
+ /* Calculate the baud rate modulo divisor, sbr*/
+ sbr = srcClock_Hz / (baudRate_Bps * 16);
+ /* set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate */
+ if (sbr == 0)
+ {
+ sbr = 1;
+ }
+#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
+ /* Determine if a fractional divider is needed to fine tune closer to the
+ * desired baud, each value of brfa is in 1/32 increments,
+ * hence the multiply-by-32. */
+ uint32_t tempBaud = 0;
+
+ uint16_t brfa = (2 * srcClock_Hz / (baudRate_Bps)) - 32 * sbr;
+
+ /* Calculate the baud rate based on the temporary SBR values and BRFA */
+ tempBaud = (srcClock_Hz * 2 / ((sbr * 32 + brfa)));
+ baudDiff = (tempBaud > baudRate_Bps) ? (tempBaud - baudRate_Bps) : (baudRate_Bps - tempBaud);
+#else
+ /* Calculate the baud rate based on the temporary SBR values */
+ baudDiff = (srcClock_Hz / (sbr * 16)) - baudRate_Bps;
+
+ /* Select the better value between sbr and (sbr + 1) */
+ if (baudDiff > (baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1)))))
+ {
+ baudDiff = baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1)));
+ sbr++;
+ }
+#endif
+
+ /* next, check to see if actual baud rate is within 3% of desired baud rate
+ * based on the calculate SBR value */
+ if (baudDiff < ((baudRate_Bps / 100) * 3))
+ {
+ /* Store C2 before disable Tx and Rx */
+ oldCtrl = base->C2;
+
+ /* Disable UART TX RX before setting. */
+ base->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK);
+
+ /* Write the sbr value to the BDH and BDL registers*/
+ base->BDH = (base->BDH & ~UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8);
+ base->BDL = (uint8_t)sbr;
+
+#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
+ /* Write the brfa value to the register*/
+ base->C4 = (base->C4 & ~UART_C4_BRFA_MASK) | (brfa & UART_C4_BRFA_MASK);
+#endif
+ /* Restore C2. */
+ base->C2 = oldCtrl;
+
+ return kStatus_Success;
+ }
+ else
+ {
+ /* Unacceptable baud rate difference of more than 3%*/
+ return kStatus_UART_BaudrateNotSupport;
+ }
+}
+
+/*!
+ * brief Enables UART interrupts according to the provided mask.
+ *
+ * This function enables the UART interrupts according to the provided mask. The mask
+ * is a logical OR of enumeration members. See ref _uart_interrupt_enable.
+ * For example, to enable TX empty interrupt and RX full interrupt, do the following.
+ * code
+ * UART_EnableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable);
+ * endcode
+ *
+ * param base UART peripheral base address.
+ * param mask The interrupts to enable. Logical OR of ref _uart_interrupt_enable.
+ */
+void UART_EnableInterrupts(UART_Type *base, uint32_t mask)
+{
+ mask &= kUART_AllInterruptsEnable;
+
+ /* The interrupt mask is combined by control bits from several register: ((CFIFO<<24) | (C3<<16) | (C2<<8) |(BDH))
+ */
+ base->BDH |= mask;
+ base->C2 |= (mask >> 8);
+ base->C3 |= (mask >> 16);
+
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+ base->CFIFO |= (mask >> 24);
+#endif
+}
+
+/*!
+ * brief Disables the UART interrupts according to the provided mask.
+ *
+ * This function disables the UART interrupts according to the provided mask. The mask
+ * is a logical OR of enumeration members. See ref _uart_interrupt_enable.
+ * For example, to disable TX empty interrupt and RX full interrupt do the following.
+ * code
+ * UART_DisableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable);
+ * endcode
+ *
+ * param base UART peripheral base address.
+ * param mask The interrupts to disable. Logical OR of ref _uart_interrupt_enable.
+ */
+void UART_DisableInterrupts(UART_Type *base, uint32_t mask)
+{
+ mask &= kUART_AllInterruptsEnable;
+
+ /* The interrupt mask is combined by control bits from several register: ((CFIFO<<24) | (C3<<16) | (C2<<8) |(BDH))
+ */
+ base->BDH &= ~mask;
+ base->C2 &= ~(mask >> 8);
+ base->C3 &= ~(mask >> 16);
+
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+ base->CFIFO &= ~(mask >> 24);
+#endif
+}
+
+/*!
+ * brief Gets the enabled UART interrupts.
+ *
+ * This function gets the enabled UART interrupts. The enabled interrupts are returned
+ * as the logical OR value of the enumerators ref _uart_interrupt_enable. To check
+ * a specific interrupts enable status, compare the return value with enumerators
+ * in ref _uart_interrupt_enable.
+ * For example, to check whether TX empty interrupt is enabled, do the following.
+ * code
+ * uint32_t enabledInterrupts = UART_GetEnabledInterrupts(UART1);
+ *
+ * if (kUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)
+ * {
+ * ...
+ * }
+ * endcode
+ *
+ * param base UART peripheral base address.
+ * return UART interrupt flags which are logical OR of the enumerators in ref _uart_interrupt_enable.
+ */
+uint32_t UART_GetEnabledInterrupts(UART_Type *base)
+{
+ uint32_t temp;
+
+ temp = base->BDH | ((uint32_t)(base->C2) << 8) | ((uint32_t)(base->C3) << 16);
+
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+ temp |= ((uint32_t)(base->CFIFO) << 24);
+#endif
+
+ return temp & kUART_AllInterruptsEnable;
+}
+
+/*!
+ * brief Gets UART status flags.
+ *
+ * This function gets all UART status flags. The flags are returned as the logical
+ * OR value of the enumerators ref _uart_flags. To check a specific status,
+ * compare the return value with enumerators in ref _uart_flags.
+ * For example, to check whether the TX is empty, do the following.
+ * code
+ * if (kUART_TxDataRegEmptyFlag & UART_GetStatusFlags(UART1))
+ * {
+ * ...
+ * }
+ * endcode
+ *
+ * param base UART peripheral base address.
+ * return UART status flags which are ORed by the enumerators in the _uart_flags.
+ */
+uint32_t UART_GetStatusFlags(UART_Type *base)
+{
+ uint32_t status_flag;
+
+ status_flag = base->S1 | ((uint32_t)(base->S2) << 8);
+
+#if defined(FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS
+ status_flag |= ((uint32_t)(base->ED) << 16);
+#endif
+
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+ status_flag |= ((uint32_t)(base->SFIFO) << 24);
+#endif
+
+ return status_flag;
+}
+
+/*!
+ * brief Clears status flags with the provided mask.
+ *
+ * This function clears UART status flags with a provided mask. An automatically cleared flag
+ * can't be cleared by this function.
+ * These flags can only be cleared or set by hardware.
+ * kUART_TxDataRegEmptyFlag, kUART_TransmissionCompleteFlag, kUART_RxDataRegFullFlag,
+ * kUART_RxActiveFlag, kUART_NoiseErrorInRxDataRegFlag, kUART_ParityErrorInRxDataRegFlag,
+ * kUART_TxFifoEmptyFlag,kUART_RxFifoEmptyFlag
+ * Note that this API should be called when the Tx/Rx is idle. Otherwise it has no effect.
+ *
+ * param base UART peripheral base address.
+ * param mask The status flags to be cleared; it is logical OR value of ref _uart_flags.
+ * retval kStatus_UART_FlagCannotClearManually The flag can't be cleared by this function but
+ * it is cleared automatically by hardware.
+ * retval kStatus_Success Status in the mask is cleared.
+ */
+status_t UART_ClearStatusFlags(UART_Type *base, uint32_t mask)
+{
+ uint8_t reg = base->S2;
+ status_t status;
+
+#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT
+ reg &= ~(UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK);
+#else
+ reg &= ~UART_S2_RXEDGIF_MASK;
+#endif
+
+ base->S2 = reg | (uint8_t)(mask >> 8);
+
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+ base->SFIFO = (uint8_t)(mask >> 24);
+#endif
+
+ if (mask & (kUART_IdleLineFlag | kUART_NoiseErrorFlag | kUART_FramingErrorFlag | kUART_ParityErrorFlag))
+ {
+ /* Read base->D to clear the flags. */
+ (void)base->S1;
+ (void)base->D;
+ }
+
+ if (mask & kUART_RxOverrunFlag)
+ {
+ /* Read base->D to clear the flags and Flush all data in FIFO. */
+ (void)base->S1;
+ (void)base->D;
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+ /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */
+ base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
+#endif
+ }
+
+ /* If some flags still pending. */
+ if (mask & UART_GetStatusFlags(base))
+ {
+ /* Some flags can only clear or set by the hardware itself, these flags are: kUART_TxDataRegEmptyFlag,
+ kUART_TransmissionCompleteFlag, kUART_RxDataRegFullFlag, kUART_RxActiveFlag, kUART_NoiseErrorInRxDataRegFlag,
+ kUART_ParityErrorInRxDataRegFlag, kUART_TxFifoEmptyFlag, kUART_RxFifoEmptyFlag. */
+ status = kStatus_UART_FlagCannotClearManually;
+ }
+ else
+ {
+ status = kStatus_Success;
+ }
+
+ return status;
+}
+
+/*!
+ * brief Writes to the TX register using a blocking method.
+ *
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
+ * to have room and writes data to the TX buffer.
+ *
+ * note This function does not check whether all data is sent out to the bus.
+ * Before disabling the TX, check kUART_TransmissionCompleteFlag to ensure that the TX is
+ * finished.
+ *
+ * param base UART peripheral base address.
+ * param data Start address of the data to write.
+ * param length Size of the data to write.
+ */
+void UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length)
+{
+ /* This API can only ensure that the data is written into the data buffer but can't
+ ensure all data in the data buffer are sent into the transmit shift buffer. */
+ while (length--)
+ {
+ while (!(base->S1 & UART_S1_TDRE_MASK))
+ {
+ }
+ base->D = *(data++);
+ }
+}
+
+static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length)
+{
+ assert(data);
+
+ size_t i;
+
+ /* The Non Blocking write data API assume user have ensured there is enough space in
+ peripheral to write. */
+ for (i = 0; i < length; i++)
+ {
+ base->D = data[i];
+ }
+}
+
+/*!
+ * brief Read RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
+ * have data, and reads data from the TX register.
+ *
+ * param base UART peripheral base address.
+ * param data Start address of the buffer to store the received data.
+ * param length Size of the buffer.
+ * retval kStatus_UART_RxHardwareOverrun Receiver overrun occurred while receiving data.
+ * retval kStatus_UART_NoiseError A noise error occurred while receiving data.
+ * retval kStatus_UART_FramingError A framing error occurred while receiving data.
+ * retval kStatus_UART_ParityError A parity error occurred while receiving data.
+ * retval kStatus_Success Successfully received all data.
+ */
+status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length)
+{
+ assert(data);
+
+ uint32_t statusFlag;
+
+ while (length--)
+ {
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+ while (!base->RCFIFO)
+#else
+ while (!(base->S1 & UART_S1_RDRF_MASK))
+#endif
+ {
+ statusFlag = UART_GetStatusFlags(base);
+
+ if (statusFlag & kUART_RxOverrunFlag)
+ {
+ return kStatus_UART_RxHardwareOverrun;
+ }
+
+ if (statusFlag & kUART_NoiseErrorFlag)
+ {
+ return kStatus_UART_NoiseError;
+ }
+
+ if (statusFlag & kUART_FramingErrorFlag)
+ {
+ return kStatus_UART_FramingError;
+ }
+
+ if (statusFlag & kUART_ParityErrorFlag)
+ {
+ return kStatus_UART_ParityError;
+ }
+ }
+ *(data++) = base->D;
+ }
+
+ return kStatus_Success;
+}
+
+static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length)
+{
+ assert(data);
+
+ size_t i;
+
+ /* The Non Blocking read data API assume user have ensured there is enough space in
+ peripheral to write. */
+ for (i = 0; i < length; i++)
+ {
+ data[i] = base->D;
+ }
+}
+
+/*!
+ * brief Initializes the UART handle.
+ *
+ * This function initializes the UART handle which can be used for other UART
+ * transactional APIs. Usually, for a specified UART instance,
+ * call this API once to get the initialized handle.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * param callback The callback function.
+ * param userData The parameter of the callback function.
+ */
+void UART_TransferCreateHandle(UART_Type *base,
+ uart_handle_t *handle,
+ uart_transfer_callback_t callback,
+ void *userData)
+{
+ assert(handle);
+
+ uint32_t instance;
+
+ /* Zero the handle. */
+ memset(handle, 0, sizeof(*handle));
+
+ /* Set the TX/RX state. */
+ handle->rxState = kUART_RxIdle;
+ handle->txState = kUART_TxIdle;
+
+ /* Set the callback and user data. */
+ handle->callback = callback;
+ handle->userData = userData;
+
+ /* Get instance from peripheral base address. */
+ instance = UART_GetInstance(base);
+
+ /* Save the handle in global variables to support the double weak mechanism. */
+ s_uartHandle[instance] = handle;
+
+ s_uartIsr = UART_TransferHandleIRQ;
+ /* Enable interrupt in NVIC. */
+ EnableIRQ(s_uartIRQ[instance]);
+}
+
+/*!
+ * brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific UART handle.
+ *
+ * When the RX ring buffer is used, data received are stored into the ring buffer even when the
+ * user doesn't call the UART_TransferReceiveNonBlocking() API. If data is already received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * note When using the RX ring buffer, one byte is reserved for internal use. In other
+ * words, if p ringBufferSize is 32, only 31 bytes are used for saving data.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * param ringBufferSize Size of the ring buffer.
+ */
+void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)
+{
+ assert(handle);
+ assert(ringBuffer);
+
+ /* Setup the ringbuffer address */
+ handle->rxRingBuffer = ringBuffer;
+ handle->rxRingBufferSize = ringBufferSize;
+ handle->rxRingBufferHead = 0U;
+ handle->rxRingBufferTail = 0U;
+
+ /* Enable the interrupt to accept the data when user need the ring buffer. */
+ UART_EnableInterrupts(
+ base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable | kUART_FramingErrorInterruptEnable);
+ /* Enable parity error interrupt when parity mode is enable*/
+ if (UART_C1_PE_MASK & base->C1)
+ {
+ UART_EnableInterrupts(base, kUART_ParityErrorInterruptEnable);
+ }
+}
+
+/*!
+ * brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ */
+void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle)
+{
+ assert(handle);
+
+ if (handle->rxState == kUART_RxIdle)
+ {
+ UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
+ kUART_FramingErrorInterruptEnable);
+ /* Disable parity error interrupt when parity mode is enable*/
+ if (UART_C1_PE_MASK & base->C1)
+ {
+ UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable);
+ }
+ }
+
+ handle->rxRingBuffer = NULL;
+ handle->rxRingBufferSize = 0U;
+ handle->rxRingBufferHead = 0U;
+ handle->rxRingBufferTail = 0U;
+}
+
+/*!
+ * brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the ISR, the UART driver calls the callback
+ * function and passes the ref kStatus_UART_TxIdle as status parameter.
+ *
+ * note The kStatus_UART_TxIdle is passed to the upper layer when all data is written
+ * to the TX register. However, it does not ensure that all data is sent out. Before disabling the TX,
+ * check the kUART_TransmissionCompleteFlag to ensure that the TX is finished.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * param xfer UART transfer structure. See #uart_transfer_t.
+ * retval kStatus_Success Successfully start the data transmission.
+ * retval kStatus_UART_TxBusy Previous transmission still not finished; data not all written to TX register yet.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer)
+{
+ assert(handle);
+ assert(xfer);
+ assert(xfer->dataSize);
+ assert(xfer->data);
+
+ status_t status;
+
+ /* Return error if current TX busy. */
+ if (kUART_TxBusy == handle->txState)
+ {
+ status = kStatus_UART_TxBusy;
+ }
+ else
+ {
+ handle->txData = xfer->data;
+ handle->txDataSize = xfer->dataSize;
+ handle->txDataSizeAll = xfer->dataSize;
+ handle->txState = kUART_TxBusy;
+
+ /* Enable transmitter interrupt. */
+ UART_EnableInterrupts(base, kUART_TxDataRegEmptyInterruptEnable);
+
+ status = kStatus_Success;
+ }
+
+ return status;
+}
+
+/*!
+ * brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
+ * how many bytes are not sent out.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ */
+void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle)
+{
+ assert(handle);
+
+ UART_DisableInterrupts(base, kUART_TxDataRegEmptyInterruptEnable | kUART_TransmissionCompleteInterruptEnable);
+
+ handle->txDataSize = 0;
+ handle->txState = kUART_TxIdle;
+}
+
+/*!
+ * brief Gets the number of bytes written to the UART TX register.
+ *
+ * This function gets the number of bytes written to the UART TX
+ * register by using the interrupt method.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * param count Send bytes count.
+ * retval kStatus_NoTransferInProgress No send in progress.
+ * retval kStatus_InvalidArgument The parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count)
+{
+ assert(handle);
+ assert(count);
+
+ if (kUART_TxIdle == handle->txState)
+ {
+ return kStatus_NoTransferInProgress;
+ }
+
+ *count = handle->txDataSizeAll - handle->txDataSize;
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ * returns without waiting for all data to be received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough to read, the receive
+ * request is saved by the UART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the UART driver notifies the upper layer
+ * through a callback function and passes the status parameter ref kStatus_UART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer.
+ * The 5 bytes are copied to the xfer->data and this function returns with the
+ * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is
+ * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to the xfer->data. When all data is received, the upper layer is notified.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * param xfer UART transfer structure, see #uart_transfer_t.
+ * param receivedBytes Bytes received from the ring buffer directly.
+ * retval kStatus_Success Successfully queue the transfer into transmit queue.
+ * retval kStatus_UART_RxBusy Previous receive request is not finished.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t UART_TransferReceiveNonBlocking(UART_Type *base,
+ uart_handle_t *handle,
+ uart_transfer_t *xfer,
+ size_t *receivedBytes)
+{
+ assert(handle);
+ assert(xfer);
+ assert(xfer->data);
+ assert(xfer->dataSize);
+
+ uint32_t i;
+ status_t status;
+ /* How many bytes to copy from ring buffer to user memory. */
+ size_t bytesToCopy = 0U;
+ /* How many bytes to receive. */
+ size_t bytesToReceive;
+ /* How many bytes currently have received. */
+ size_t bytesCurrentReceived;
+
+ /* How to get data:
+ 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
+ to uart handle, enable interrupt to store received data to xfer->data. When
+ all data received, trigger callback.
+ 2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
+ If there are enough data in ring buffer, copy them to xfer->data and return.
+ If there are not enough data in ring buffer, copy all of them to xfer->data,
+ save the xfer->data remained empty space to uart handle, receive data
+ to this empty space and trigger callback when finished. */
+
+ if (kUART_RxBusy == handle->rxState)
+ {
+ status = kStatus_UART_RxBusy;
+ }
+ else
+ {
+ bytesToReceive = xfer->dataSize;
+ bytesCurrentReceived = 0U;
+
+ /* If RX ring buffer is used. */
+ if (handle->rxRingBuffer)
+ {
+ /* Disable UART RX IRQ, protect ring buffer. */
+ UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable);
+
+ /* How many bytes in RX ring buffer currently. */
+ bytesToCopy = UART_TransferGetRxRingBufferLength(handle);
+
+ if (bytesToCopy)
+ {
+ bytesToCopy = MIN(bytesToReceive, bytesToCopy);
+
+ bytesToReceive -= bytesToCopy;
+
+ /* Copy data from ring buffer to user memory. */
+ for (i = 0U; i < bytesToCopy; i++)
+ {
+ xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
+
+ /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
+ if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+ {
+ handle->rxRingBufferTail = 0U;
+ }
+ else
+ {
+ handle->rxRingBufferTail++;
+ }
+ }
+ }
+
+ /* If ring buffer does not have enough data, still need to read more data. */
+ if (bytesToReceive)
+ {
+ /* No data in ring buffer, save the request to UART handle. */
+ handle->rxData = xfer->data + bytesCurrentReceived;
+ handle->rxDataSize = bytesToReceive;
+ handle->rxDataSizeAll = bytesToReceive;
+ handle->rxState = kUART_RxBusy;
+ }
+
+ /* Enable UART RX IRQ if previously enabled. */
+ UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable);
+
+ /* Call user callback since all data are received. */
+ if (0 == bytesToReceive)
+ {
+ if (handle->callback)
+ {
+ handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData);
+ }
+ }
+ }
+ /* Ring buffer not used. */
+ else
+ {
+ handle->rxData = xfer->data + bytesCurrentReceived;
+ handle->rxDataSize = bytesToReceive;
+ handle->rxDataSizeAll = bytesToReceive;
+ handle->rxState = kUART_RxBusy;
+
+ /* Enable RX/Rx overrun/framing error/idle line interrupt. */
+ UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
+ kUART_FramingErrorInterruptEnable | kUART_IdleLineInterruptEnable);
+ /* Enable parity error interrupt when parity mode is enable*/
+ if (UART_C1_PE_MASK & base->C1)
+ {
+ UART_EnableInterrupts(base, kUART_ParityErrorInterruptEnable);
+ }
+ }
+
+ /* Return the how many bytes have read. */
+ if (receivedBytes)
+ {
+ *receivedBytes = bytesCurrentReceived;
+ }
+
+ status = kStatus_Success;
+ }
+
+ return status;
+}
+
+/*!
+ * brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
+ * how many bytes are not received yet.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ */
+void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle)
+{
+ assert(handle);
+
+ /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
+ if (!handle->rxRingBuffer)
+ {
+ /* Disable RX interrupt. */
+ UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
+ kUART_FramingErrorInterruptEnable | kUART_IdleLineInterruptEnable);
+ /* Disable parity error interrupt when parity mode is enable*/
+ if (UART_C1_PE_MASK & base->C1)
+ {
+ UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable);
+ }
+ }
+
+ handle->rxDataSize = 0U;
+ handle->rxState = kUART_RxIdle;
+}
+
+/*!
+ * brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * param count Receive bytes count.
+ * retval kStatus_NoTransferInProgress No receive in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count)
+{
+ assert(handle);
+ assert(count);
+
+ if (kUART_RxIdle == handle->rxState)
+ {
+ return kStatus_NoTransferInProgress;
+ }
+
+ if (!count)
+ {
+ return kStatus_InvalidArgument;
+ }
+
+ *count = handle->rxDataSizeAll - handle->rxDataSize;
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief UART IRQ handle function.
+ *
+ * This function handles the UART transmit and receive IRQ request.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ */
+void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle)
+{
+ assert(handle);
+
+ uint8_t count;
+ uint8_t tempCount;
+ uint32_t status = UART_GetStatusFlags(base);
+
+ /* If RX framing error */
+ if (kUART_FramingErrorFlag & status)
+ {
+ /* Read base->D to clear framing error flag, otherwise the RX does not work. */
+ while (base->S1 & UART_S1_RDRF_MASK)
+ {
+ (void)base->D;
+ }
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+ /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */
+ base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
+#endif
+
+ handle->rxState = kUART_RxFramingError;
+ handle->rxDataSize = 0U;
+ /* Trigger callback. */
+ if (handle->callback)
+ {
+ handle->callback(base, handle, kStatus_UART_FramingError, handle->userData);
+ }
+ }
+
+ /* If RX parity error */
+ if (kUART_ParityErrorFlag & status)
+ {
+ /* Read base->D to clear parity error flag, otherwise the RX does not work. */
+ while (base->S1 & UART_S1_RDRF_MASK)
+ {
+ (void)base->D;
+ }
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+ /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */
+ base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
+#endif
+
+ handle->rxState = kUART_RxParityError;
+ handle->rxDataSize = 0U;
+ /* Trigger callback. */
+ if (handle->callback)
+ {
+ handle->callback(base, handle, kStatus_UART_ParityError, handle->userData);
+ }
+ }
+
+ /* If RX overrun. */
+ if (kUART_RxOverrunFlag & status)
+ {
+ /* Read base->D to clear overrun flag, otherwise the RX does not work. */
+ while (base->S1 & UART_S1_RDRF_MASK)
+ {
+ (void)base->D;
+ }
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+ /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */
+ base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
+#endif
+ /* Trigger callback. */
+ if (handle->callback)
+ {
+ handle->callback(base, handle, kStatus_UART_RxHardwareOverrun, handle->userData);
+ }
+ }
+
+ /* If IDLE line was detected. */
+ if ((kUART_IdleLineFlag & status) && (UART_C2_ILIE_MASK & base->C2))
+ {
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+ /* If still some data in the FIFO, read out these data to user data buffer. */
+ count = base->RCFIFO;
+ /* If handle->rxDataSize is not 0, first save data to handle->rxData. */
+ while ((count) && (handle->rxDataSize))
+ {
+ tempCount = MIN(handle->rxDataSize, count);
+
+ /* Using non block API to read the data from the registers. */
+ UART_ReadNonBlocking(base, handle->rxData, tempCount);
+ handle->rxData += tempCount;
+ handle->rxDataSize -= tempCount;
+ count -= tempCount;
+
+ /* If all the data required for upper layer is ready, trigger callback. */
+ if (!handle->rxDataSize)
+ {
+ handle->rxState = kUART_RxIdle;
+
+ /* Disable RX interrupt/overrun interrupt/fram error/idle line detected interrupt */
+ UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
+ kUART_FramingErrorInterruptEnable);
+
+ /* Disable parity error interrupt when parity mode is enable*/
+ if (UART_C1_PE_MASK & base->C1)
+ {
+ UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable);
+ }
+
+ if (handle->callback)
+ {
+ handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData);
+ }
+ }
+ }
+#endif
+ /* To clear IDLE, read UART status S1 with IDLE set and then read D.*/
+ while (UART_S1_IDLE_MASK & base->S1)
+ {
+ (void)base->D;
+ }
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+ /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */
+ base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
+#endif
+ /* If rxDataSize is 0, disable idle line interrupt.*/
+ if (!(handle->rxDataSize))
+ {
+ UART_DisableInterrupts(base, kUART_IdleLineInterruptEnable);
+ }
+ /* If callback is not NULL and rxDataSize is not 0. */
+ if ((handle->callback) && (handle->rxDataSize))
+ {
+ handle->callback(base, handle, kStatus_UART_IdleLineDetected, handle->userData);
+ }
+ }
+ /* Receive data register full */
+ if ((kUART_RxDataRegFullFlag & status) && (UART_C2_RIE_MASK & base->C2))
+ {
+/* Get the size that can be stored into buffer for this interrupt. */
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+ count = base->RCFIFO;
+#else
+ count = 1;
+#endif
+
+ /* If handle->rxDataSize is not 0, first save data to handle->rxData. */
+ while ((count) && (handle->rxDataSize))
+ {
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+ tempCount = MIN(handle->rxDataSize, count);
+#else
+ tempCount = 1;
+#endif
+
+ /* Using non block API to read the data from the registers. */
+ UART_ReadNonBlocking(base, handle->rxData, tempCount);
+ handle->rxData += tempCount;
+ handle->rxDataSize -= tempCount;
+ count -= tempCount;
+
+ /* If all the data required for upper layer is ready, trigger callback. */
+ if (!handle->rxDataSize)
+ {
+ handle->rxState = kUART_RxIdle;
+
+ if (handle->callback)
+ {
+ handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData);
+ }
+ }
+ }
+
+ /* If use RX ring buffer, receive data to ring buffer. */
+ if (handle->rxRingBuffer)
+ {
+ while (count--)
+ {
+ /* If RX ring buffer is full, trigger callback to notify over run. */
+ if (UART_TransferIsRxRingBufferFull(handle))
+ {
+ if (handle->callback)
+ {
+ handle->callback(base, handle, kStatus_UART_RxRingBufferOverrun, handle->userData);
+ }
+ }
+
+ /* If ring buffer is still full after callback function, the oldest data is overrided. */
+ if (UART_TransferIsRxRingBufferFull(handle))
+ {
+ /* Increase handle->rxRingBufferTail to make room for new data. */
+ if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+ {
+ handle->rxRingBufferTail = 0U;
+ }
+ else
+ {
+ handle->rxRingBufferTail++;
+ }
+ }
+
+ /* Read data. */
+ handle->rxRingBuffer[handle->rxRingBufferHead] = base->D;
+
+ /* Increase handle->rxRingBufferHead. */
+ if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
+ {
+ handle->rxRingBufferHead = 0U;
+ }
+ else
+ {
+ handle->rxRingBufferHead++;
+ }
+ }
+ }
+
+ else if (!handle->rxDataSize)
+ {
+ /* Disable RX interrupt/overrun interrupt/fram error/idle line detected interrupt */
+ UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
+ kUART_FramingErrorInterruptEnable);
+
+ /* Disable parity error interrupt when parity mode is enable*/
+ if (UART_C1_PE_MASK & base->C1)
+ {
+ UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable);
+ }
+ }
+ else
+ {
+ }
+ }
+
+ /* If framing error or parity error happened, stop the RX interrupt when ues no ring buffer */
+ if (((handle->rxState == kUART_RxFramingError) || (handle->rxState == kUART_RxParityError)) &&
+ (!handle->rxRingBuffer))
+ {
+ UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
+ kUART_FramingErrorInterruptEnable | kUART_IdleLineInterruptEnable);
+
+ /* Disable parity error interrupt when parity mode is enable*/
+ if (UART_C1_PE_MASK & base->C1)
+ {
+ UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable);
+ }
+ }
+
+ /* Send data register empty and the interrupt is enabled. */
+ if ((kUART_TxDataRegEmptyFlag & status) && (base->C2 & UART_C2_TIE_MASK))
+ {
+/* Get the bytes that available at this moment. */
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+ count = FSL_FEATURE_UART_FIFO_SIZEn(base) - base->TCFIFO;
+#else
+ count = 1;
+#endif
+
+ while ((count) && (handle->txDataSize))
+ {
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+ tempCount = MIN(handle->txDataSize, count);
+#else
+ tempCount = 1;
+#endif
+
+ /* Using non block API to write the data to the registers. */
+ UART_WriteNonBlocking(base, handle->txData, tempCount);
+ handle->txData += tempCount;
+ handle->txDataSize -= tempCount;
+ count -= tempCount;
+
+ /* If all the data are written to data register, TX finished. */
+ if (!handle->txDataSize)
+ {
+ handle->txState = kUART_TxIdle;
+
+ /* Disable TX register empty interrupt. */
+ base->C2 = (base->C2 & ~UART_C2_TIE_MASK);
+
+ /* Trigger callback. */
+ if (handle->callback)
+ {
+ handle->callback(base, handle, kStatus_UART_TxIdle, handle->userData);
+ }
+ }
+ }
+ }
+}
+
+/*!
+ * brief UART Error IRQ handle function.
+ *
+ * This function handles the UART error IRQ request.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ */
+void UART_TransferHandleErrorIRQ(UART_Type *base, uart_handle_t *handle)
+{
+ /* To be implemented by User. */
+}
+
+#if defined(UART0)
+#if ((!(defined(FSL_FEATURE_SOC_LPSCI_COUNT))) || \
+ ((defined(FSL_FEATURE_SOC_LPSCI_COUNT)) && (FSL_FEATURE_SOC_LPSCI_COUNT == 0)))
+void UART0_DriverIRQHandler(void)
+{
+ s_uartIsr(UART0, s_uartHandle[0]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void UART0_RX_TX_DriverIRQHandler(void)
+{
+ UART0_DriverIRQHandler();
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif
+#endif
+
+#if defined(UART1)
+void UART1_DriverIRQHandler(void)
+{
+ s_uartIsr(UART1, s_uartHandle[1]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void UART1_RX_TX_DriverIRQHandler(void)
+{
+ UART1_DriverIRQHandler();
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif
+
+#if defined(UART2)
+void UART2_DriverIRQHandler(void)
+{
+ s_uartIsr(UART2, s_uartHandle[2]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void UART2_RX_TX_DriverIRQHandler(void)
+{
+ UART2_DriverIRQHandler();
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif
+
+#if defined(UART3)
+void UART3_DriverIRQHandler(void)
+{
+ s_uartIsr(UART3, s_uartHandle[3]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void UART3_RX_TX_DriverIRQHandler(void)
+{
+ UART3_DriverIRQHandler();
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif
+
+#if defined(UART4)
+void UART4_DriverIRQHandler(void)
+{
+ s_uartIsr(UART4, s_uartHandle[4]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void UART4_RX_TX_DriverIRQHandler(void)
+{
+ UART4_DriverIRQHandler();
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif
+
+#if defined(UART5)
+void UART5_DriverIRQHandler(void)
+{
+ s_uartIsr(UART5, s_uartHandle[5]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+
+void UART5_RX_TX_DriverIRQHandler(void)
+{
+ UART5_DriverIRQHandler();
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+}
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/fsl_uart.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/fsl_uart.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,782 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_UART_H_
+#define _FSL_UART_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup uart_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief UART driver version 2.1.6. */
+#define FSL_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 6))
+/*@}*/
+
+/*! @brief Error codes for the UART driver. */
+enum _uart_status
+{
+ kStatus_UART_TxBusy = MAKE_STATUS(kStatusGroup_UART, 0), /*!< Transmitter is busy. */
+ kStatus_UART_RxBusy = MAKE_STATUS(kStatusGroup_UART, 1), /*!< Receiver is busy. */
+ kStatus_UART_TxIdle = MAKE_STATUS(kStatusGroup_UART, 2), /*!< UART transmitter is idle. */
+ kStatus_UART_RxIdle = MAKE_STATUS(kStatusGroup_UART, 3), /*!< UART receiver is idle. */
+ kStatus_UART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_UART, 4), /*!< TX FIFO watermark too large */
+ kStatus_UART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_UART, 5), /*!< RX FIFO watermark too large */
+ kStatus_UART_FlagCannotClearManually =
+ MAKE_STATUS(kStatusGroup_UART, 6), /*!< UART flag can't be manually cleared. */
+ kStatus_UART_Error = MAKE_STATUS(kStatusGroup_UART, 7), /*!< Error happens on UART. */
+ kStatus_UART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_UART, 8), /*!< UART RX software ring buffer overrun. */
+ kStatus_UART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_UART, 9), /*!< UART RX receiver overrun. */
+ kStatus_UART_NoiseError = MAKE_STATUS(kStatusGroup_UART, 10), /*!< UART noise error. */
+ kStatus_UART_FramingError = MAKE_STATUS(kStatusGroup_UART, 11), /*!< UART framing error. */
+ kStatus_UART_ParityError = MAKE_STATUS(kStatusGroup_UART, 12), /*!< UART parity error. */
+ kStatus_UART_BaudrateNotSupport =
+ MAKE_STATUS(kStatusGroup_UART, 13), /*!< Baudrate is not support in current clock source */
+ kStatus_UART_IdleLineDetected = MAKE_STATUS(kStatusGroup_UART, 14), /*!< UART IDLE line detected. */
+};
+
+/*! @brief UART parity mode. */
+typedef enum _uart_parity_mode
+{
+ kUART_ParityDisabled = 0x0U, /*!< Parity disabled */
+ kUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */
+ kUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */
+} uart_parity_mode_t;
+
+/*! @brief UART stop bit count. */
+typedef enum _uart_stop_bit_count
+{
+ kUART_OneStopBit = 0U, /*!< One stop bit */
+ kUART_TwoStopBit = 1U, /*!< Two stop bits */
+} uart_stop_bit_count_t;
+
+/*! @brief UART idle type select. */
+typedef enum _uart_idle_type_select
+{
+ kUART_IdleTypeStartBit = 0U, /*!< Start counting after a valid start bit. */
+ kUART_IdleTypeStopBit = 1U, /*!< Start counting after a stop bit. */
+} uart_idle_type_select_t;
+
+/*!
+ * @brief UART interrupt configuration structure, default settings all disabled.
+ *
+ * This structure contains the settings for all of the UART interrupt configurations.
+ */
+enum _uart_interrupt_enable
+{
+#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT
+ kUART_LinBreakInterruptEnable = (UART_BDH_LBKDIE_MASK), /*!< LIN break detect interrupt. */
+#endif
+ kUART_RxActiveEdgeInterruptEnable = (UART_BDH_RXEDGIE_MASK), /*!< RX active edge interrupt. */
+ kUART_TxDataRegEmptyInterruptEnable = (UART_C2_TIE_MASK << 8), /*!< Transmit data register empty interrupt. */
+ kUART_TransmissionCompleteInterruptEnable = (UART_C2_TCIE_MASK << 8), /*!< Transmission complete interrupt. */
+ kUART_RxDataRegFullInterruptEnable = (UART_C2_RIE_MASK << 8), /*!< Receiver data register full interrupt. */
+ kUART_IdleLineInterruptEnable = (UART_C2_ILIE_MASK << 8), /*!< Idle line interrupt. */
+ kUART_RxOverrunInterruptEnable = (UART_C3_ORIE_MASK << 16), /*!< Receiver overrun interrupt. */
+ kUART_NoiseErrorInterruptEnable = (UART_C3_NEIE_MASK << 16), /*!< Noise error flag interrupt. */
+ kUART_FramingErrorInterruptEnable = (UART_C3_FEIE_MASK << 16), /*!< Framing error flag interrupt. */
+ kUART_ParityErrorInterruptEnable = (UART_C3_PEIE_MASK << 16), /*!< Parity error flag interrupt. */
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+ kUART_RxFifoOverflowInterruptEnable = (UART_CFIFO_RXOFE_MASK << 24), /*!< RX FIFO overflow interrupt. */
+ kUART_TxFifoOverflowInterruptEnable = (UART_CFIFO_TXOFE_MASK << 24), /*!< TX FIFO overflow interrupt. */
+ kUART_RxFifoUnderflowInterruptEnable = (UART_CFIFO_RXUFE_MASK << 24), /*!< RX FIFO underflow interrupt. */
+#endif
+ kUART_AllInterruptsEnable =
+#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT
+ kUART_LinBreakInterruptEnable |
+#endif
+ kUART_RxActiveEdgeInterruptEnable | kUART_TxDataRegEmptyInterruptEnable |
+ kUART_TransmissionCompleteInterruptEnable | kUART_RxDataRegFullInterruptEnable | kUART_IdleLineInterruptEnable |
+ kUART_RxOverrunInterruptEnable | kUART_NoiseErrorInterruptEnable | kUART_FramingErrorInterruptEnable |
+ kUART_ParityErrorInterruptEnable
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+ |
+ kUART_RxFifoOverflowInterruptEnable | kUART_TxFifoOverflowInterruptEnable | kUART_RxFifoUnderflowInterruptEnable
+#endif
+ ,
+};
+
+/*!
+ * @brief UART status flags.
+ *
+ * This provides constants for the UART status flags for use in the UART functions.
+ */
+enum _uart_flags
+{
+ kUART_TxDataRegEmptyFlag = (UART_S1_TDRE_MASK), /*!< TX data register empty flag. */
+ kUART_TransmissionCompleteFlag = (UART_S1_TC_MASK), /*!< Transmission complete flag. */
+ kUART_RxDataRegFullFlag = (UART_S1_RDRF_MASK), /*!< RX data register full flag. */
+ kUART_IdleLineFlag = (UART_S1_IDLE_MASK), /*!< Idle line detect flag. */
+ kUART_RxOverrunFlag = (UART_S1_OR_MASK), /*!< RX overrun flag. */
+ kUART_NoiseErrorFlag = (UART_S1_NF_MASK), /*!< RX takes 3 samples of each received bit.
+ If any of these samples differ, noise flag sets */
+ kUART_FramingErrorFlag = (UART_S1_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected
+ where stop bit expected */
+ kUART_ParityErrorFlag = (UART_S1_PF_MASK), /*!< If parity enabled, sets upon parity error detection */
+#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT
+ kUART_LinBreakFlag =
+ (UART_S2_LBKDIF_MASK
+ << 8), /*!< LIN break detect interrupt flag, sets when LIN break char detected and LIN circuit enabled */
+#endif
+ kUART_RxActiveEdgeFlag =
+ (UART_S2_RXEDGIF_MASK << 8), /*!< RX pin active edge interrupt flag,sets when active edge detected */
+ kUART_RxActiveFlag =
+ (UART_S2_RAF_MASK << 8), /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */
+#if defined(FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS
+ kUART_NoiseErrorInRxDataRegFlag = (UART_ED_NOISY_MASK << 16), /*!< Noisy bit, sets if noise detected. */
+ kUART_ParityErrorInRxDataRegFlag = (UART_ED_PARITYE_MASK << 16), /*!< Parity bit, sets if parity error detected. */
+#endif
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+ kUART_TxFifoEmptyFlag = (int)(UART_SFIFO_TXEMPT_MASK << 24), /*!< TXEMPT bit, sets if TX buffer is empty */
+ kUART_RxFifoEmptyFlag = (UART_SFIFO_RXEMPT_MASK << 24), /*!< RXEMPT bit, sets if RX buffer is empty */
+ kUART_TxFifoOverflowFlag = (UART_SFIFO_TXOF_MASK << 24), /*!< TXOF bit, sets if TX buffer overflow occurred */
+ kUART_RxFifoOverflowFlag = (UART_SFIFO_RXOF_MASK << 24), /*!< RXOF bit, sets if receive buffer overflow */
+ kUART_RxFifoUnderflowFlag = (UART_SFIFO_RXUF_MASK << 24), /*!< RXUF bit, sets if receive buffer underflow */
+#endif
+};
+
+/*! @brief UART configuration structure. */
+typedef struct _uart_config
+{
+ uint32_t baudRate_Bps; /*!< UART baud rate */
+ uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
+#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT
+ uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
+#endif
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+ uint8_t txFifoWatermark; /*!< TX FIFO watermark */
+ uint8_t rxFifoWatermark; /*!< RX FIFO watermark */
+#endif
+#if defined(FSL_FEATURE_UART_HAS_MODEM_SUPPORT) && FSL_FEATURE_UART_HAS_MODEM_SUPPORT
+ bool enableRxRTS; /*!< RX RTS enable */
+ bool enableTxCTS; /*!< TX CTS enable */
+#endif
+ uart_idle_type_select_t idleType; /*!< IDLE type select. */
+ bool enableTx; /*!< Enable TX */
+ bool enableRx; /*!< Enable RX */
+} uart_config_t;
+
+/*! @brief UART transfer structure. */
+typedef struct _uart_transfer
+{
+ uint8_t *data; /*!< The buffer of data to be transfer.*/
+ size_t dataSize; /*!< The byte count to be transfer. */
+} uart_transfer_t;
+
+/* Forward declaration of the handle typedef. */
+typedef struct _uart_handle uart_handle_t;
+
+/*! @brief UART transfer callback function. */
+typedef void (*uart_transfer_callback_t)(UART_Type *base, uart_handle_t *handle, status_t status, void *userData);
+
+/*! @brief UART handle structure. */
+struct _uart_handle
+{
+ uint8_t *volatile txData; /*!< Address of remaining data to send. */
+ volatile size_t txDataSize; /*!< Size of the remaining data to send. */
+ size_t txDataSizeAll; /*!< Size of the data to send out. */
+ uint8_t *volatile rxData; /*!< Address of remaining data to receive. */
+ volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */
+ size_t rxDataSizeAll; /*!< Size of the data to receive. */
+
+ uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */
+ size_t rxRingBufferSize; /*!< Size of the ring buffer. */
+ volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
+ volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
+
+ uart_transfer_callback_t callback; /*!< Callback function. */
+ void *userData; /*!< UART callback function parameter.*/
+
+ volatile uint8_t txState; /*!< TX transfer state. */
+ volatile uint8_t rxState; /*!< RX transfer state */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @brief Get the UART instance from peripheral base address.
+ *
+ * @param base UART peripheral base address.
+ * @return UART instance.
+ */
+uint32_t UART_GetInstance(UART_Type *base);
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes a UART instance with a user configuration structure and peripheral clock.
+ *
+ * This function configures the UART module with the user-defined settings. The user can configure the configuration
+ * structure and also get the default configuration by using the UART_GetDefaultConfig() function.
+ * The example below shows how to use this API to configure UART.
+ * @code
+ * uart_config_t uartConfig;
+ * uartConfig.baudRate_Bps = 115200U;
+ * uartConfig.parityMode = kUART_ParityDisabled;
+ * uartConfig.stopBitCount = kUART_OneStopBit;
+ * uartConfig.txFifoWatermark = 0;
+ * uartConfig.rxFifoWatermark = 1;
+ * UART_Init(UART1, &uartConfig, 20000000U);
+ * @endcode
+ *
+ * @param base UART peripheral base address.
+ * @param config Pointer to the user-defined configuration structure.
+ * @param srcClock_Hz UART clock source frequency in HZ.
+ * @retval kStatus_UART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_Success Status UART initialize succeed
+ */
+status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Deinitializes a UART instance.
+ *
+ * This function waits for TX complete, disables TX and RX, and disables the UART clock.
+ *
+ * @param base UART peripheral base address.
+ */
+void UART_Deinit(UART_Type *base);
+
+/*!
+ * @brief Gets the default configuration structure.
+ *
+ * This function initializes the UART configuration structure to a default value. The default
+ * values are as follows.
+ * uartConfig->baudRate_Bps = 115200U;
+ * uartConfig->bitCountPerChar = kUART_8BitsPerChar;
+ * uartConfig->parityMode = kUART_ParityDisabled;
+ * uartConfig->stopBitCount = kUART_OneStopBit;
+ * uartConfig->txFifoWatermark = 0;
+ * uartConfig->rxFifoWatermark = 1;
+ * uartConfig->idleType = kUART_IdleTypeStartBit;
+ * uartConfig->enableTx = false;
+ * uartConfig->enableRx = false;
+ *
+ * @param config Pointer to configuration structure.
+ */
+void UART_GetDefaultConfig(uart_config_t *config);
+
+/*!
+ * @brief Sets the UART instance baud rate.
+ *
+ * This function configures the UART module baud rate. This function is used to update
+ * the UART module baud rate after the UART module is initialized by the UART_Init.
+ * @code
+ * UART_SetBaudRate(UART1, 115200U, 20000000U);
+ * @endcode
+ *
+ * @param base UART peripheral base address.
+ * @param baudRate_Bps UART baudrate to be set.
+ * @param srcClock_Hz UART clock source freqency in Hz.
+ * @retval kStatus_UART_BaudrateNotSupport Baudrate is not support in the current clock source.
+ * @retval kStatus_Success Set baudrate succeeded.
+ */
+status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
+
+/* @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets UART status flags.
+ *
+ * This function gets all UART status flags. The flags are returned as the logical
+ * OR value of the enumerators @ref _uart_flags. To check a specific status,
+ * compare the return value with enumerators in @ref _uart_flags.
+ * For example, to check whether the TX is empty, do the following.
+ * @code
+ * if (kUART_TxDataRegEmptyFlag & UART_GetStatusFlags(UART1))
+ * {
+ * ...
+ * }
+ * @endcode
+ *
+ * @param base UART peripheral base address.
+ * @return UART status flags which are ORed by the enumerators in the _uart_flags.
+ */
+uint32_t UART_GetStatusFlags(UART_Type *base);
+
+/*!
+ * @brief Clears status flags with the provided mask.
+ *
+ * This function clears UART status flags with a provided mask. An automatically cleared flag
+ * can't be cleared by this function.
+ * These flags can only be cleared or set by hardware.
+ * kUART_TxDataRegEmptyFlag, kUART_TransmissionCompleteFlag, kUART_RxDataRegFullFlag,
+ * kUART_RxActiveFlag, kUART_NoiseErrorInRxDataRegFlag, kUART_ParityErrorInRxDataRegFlag,
+ * kUART_TxFifoEmptyFlag,kUART_RxFifoEmptyFlag
+ * Note that this API should be called when the Tx/Rx is idle. Otherwise it has no effect.
+ *
+ * @param base UART peripheral base address.
+ * @param mask The status flags to be cleared; it is logical OR value of @ref _uart_flags.
+ * @retval kStatus_UART_FlagCannotClearManually The flag can't be cleared by this function but
+ * it is cleared automatically by hardware.
+ * @retval kStatus_Success Status in the mask is cleared.
+ */
+status_t UART_ClearStatusFlags(UART_Type *base, uint32_t mask);
+
+/* @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables UART interrupts according to the provided mask.
+ *
+ * This function enables the UART interrupts according to the provided mask. The mask
+ * is a logical OR of enumeration members. See @ref _uart_interrupt_enable.
+ * For example, to enable TX empty interrupt and RX full interrupt, do the following.
+ * @code
+ * UART_EnableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable);
+ * @endcode
+ *
+ * @param base UART peripheral base address.
+ * @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable.
+ */
+void UART_EnableInterrupts(UART_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables the UART interrupts according to the provided mask.
+ *
+ * This function disables the UART interrupts according to the provided mask. The mask
+ * is a logical OR of enumeration members. See @ref _uart_interrupt_enable.
+ * For example, to disable TX empty interrupt and RX full interrupt do the following.
+ * @code
+ * UART_DisableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable);
+ * @endcode
+ *
+ * @param base UART peripheral base address.
+ * @param mask The interrupts to disable. Logical OR of @ref _uart_interrupt_enable.
+ */
+void UART_DisableInterrupts(UART_Type *base, uint32_t mask);
+
+/*!
+ * @brief Gets the enabled UART interrupts.
+ *
+ * This function gets the enabled UART interrupts. The enabled interrupts are returned
+ * as the logical OR value of the enumerators @ref _uart_interrupt_enable. To check
+ * a specific interrupts enable status, compare the return value with enumerators
+ * in @ref _uart_interrupt_enable.
+ * For example, to check whether TX empty interrupt is enabled, do the following.
+ * @code
+ * uint32_t enabledInterrupts = UART_GetEnabledInterrupts(UART1);
+ *
+ * if (kUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)
+ * {
+ * ...
+ * }
+ * @endcode
+ *
+ * @param base UART peripheral base address.
+ * @return UART interrupt flags which are logical OR of the enumerators in @ref _uart_interrupt_enable.
+ */
+uint32_t UART_GetEnabledInterrupts(UART_Type *base);
+
+/* @} */
+
+#if defined(FSL_FEATURE_UART_HAS_DMA_SELECT) && FSL_FEATURE_UART_HAS_DMA_SELECT
+/*!
+ * @name DMA Control
+ * @{
+ */
+
+/*!
+ * @brief Gets the UART data register address.
+ *
+ * This function returns the UART data register address, which is mainly used by DMA/eDMA.
+ *
+ * @param base UART peripheral base address.
+ * @return UART data register addresses which are used both by the transmitter and the receiver.
+ */
+static inline uint32_t UART_GetDataRegisterAddress(UART_Type *base)
+{
+ return (uint32_t) & (base->D);
+}
+
+/*!
+ * @brief Enables or disables the UART transmitter DMA request.
+ *
+ * This function enables or disables the transmit data register empty flag, S1[TDRE], to generate the DMA requests.
+ *
+ * @param base UART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void UART_EnableTxDMA(UART_Type *base, bool enable)
+{
+ if (enable)
+ {
+#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI)
+ base->C4 |= UART_C4_TDMAS_MASK;
+#else
+ base->C5 |= UART_C5_TDMAS_MASK;
+#endif
+ base->C2 |= UART_C2_TIE_MASK;
+ }
+ else
+ {
+#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI)
+ base->C4 &= ~UART_C4_TDMAS_MASK;
+#else
+ base->C5 &= ~UART_C5_TDMAS_MASK;
+#endif
+ base->C2 &= ~UART_C2_TIE_MASK;
+ }
+}
+
+/*!
+ * @brief Enables or disables the UART receiver DMA.
+ *
+ * This function enables or disables the receiver data register full flag, S1[RDRF], to generate DMA requests.
+ *
+ * @param base UART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void UART_EnableRxDMA(UART_Type *base, bool enable)
+{
+ if (enable)
+ {
+#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI)
+ base->C4 |= UART_C4_RDMAS_MASK;
+#else
+ base->C5 |= UART_C5_RDMAS_MASK;
+#endif
+ base->C2 |= UART_C2_RIE_MASK;
+ }
+ else
+ {
+#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI)
+ base->C4 &= ~UART_C4_RDMAS_MASK;
+#else
+ base->C5 &= ~UART_C5_RDMAS_MASK;
+#endif
+ base->C2 &= ~UART_C2_RIE_MASK;
+ }
+}
+
+/* @} */
+#endif /* FSL_FEATURE_UART_HAS_DMA_SELECT */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Enables or disables the UART transmitter.
+ *
+ * This function enables or disables the UART transmitter.
+ *
+ * @param base UART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void UART_EnableTx(UART_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->C2 |= UART_C2_TE_MASK;
+ }
+ else
+ {
+ base->C2 &= ~UART_C2_TE_MASK;
+ }
+}
+
+/*!
+ * @brief Enables or disables the UART receiver.
+ *
+ * This function enables or disables the UART receiver.
+ *
+ * @param base UART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void UART_EnableRx(UART_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->C2 |= UART_C2_RE_MASK;
+ }
+ else
+ {
+ base->C2 &= ~UART_C2_RE_MASK;
+ }
+}
+
+/*!
+ * @brief Writes to the TX register.
+ *
+ * This function writes data to the TX register directly. The upper layer must ensure
+ * that the TX register is empty or TX FIFO has empty room before calling this function.
+ *
+ * @param base UART peripheral base address.
+ * @param data The byte to write.
+ */
+static inline void UART_WriteByte(UART_Type *base, uint8_t data)
+{
+ base->D = data;
+}
+
+/*!
+ * @brief Reads the RX register directly.
+ *
+ * This function reads data from the RX register directly. The upper layer must
+ * ensure that the RX register is full or that the TX FIFO has data before calling this function.
+ *
+ * @param base UART peripheral base address.
+ * @return The byte read from UART data register.
+ */
+static inline uint8_t UART_ReadByte(UART_Type *base)
+{
+ return base->D;
+}
+
+/*!
+ * @brief Writes to the TX register using a blocking method.
+ *
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
+ * to have room and writes data to the TX buffer.
+ *
+ * @note This function does not check whether all data is sent out to the bus.
+ * Before disabling the TX, check kUART_TransmissionCompleteFlag to ensure that the TX is
+ * finished.
+ *
+ * @param base UART peripheral base address.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ */
+void UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length);
+
+/*!
+ * @brief Read RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
+ * have data, and reads data from the TX register.
+ *
+ * @param base UART peripheral base address.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ * @retval kStatus_UART_RxHardwareOverrun Receiver overrun occurred while receiving data.
+ * @retval kStatus_UART_NoiseError A noise error occurred while receiving data.
+ * @retval kStatus_UART_FramingError A framing error occurred while receiving data.
+ * @retval kStatus_UART_ParityError A parity error occurred while receiving data.
+ * @retval kStatus_Success Successfully received all data.
+ */
+status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length);
+
+/* @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the UART handle.
+ *
+ * This function initializes the UART handle which can be used for other UART
+ * transactional APIs. Usually, for a specified UART instance,
+ * call this API once to get the initialized handle.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @param callback The callback function.
+ * @param userData The parameter of the callback function.
+ */
+void UART_TransferCreateHandle(UART_Type *base,
+ uart_handle_t *handle,
+ uart_transfer_callback_t callback,
+ void *userData);
+
+/*!
+ * @brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific UART handle.
+ *
+ * When the RX ring buffer is used, data received are stored into the ring buffer even when the
+ * user doesn't call the UART_TransferReceiveNonBlocking() API. If data is already received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * @note When using the RX ring buffer, one byte is reserved for internal use. In other
+ * words, if @p ringBufferSize is 32, only 31 bytes are used for saving data.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * @param ringBufferSize Size of the ring buffer.
+ */
+void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize);
+
+/*!
+ * @brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ */
+void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle);
+
+/*!
+ * @brief Get the length of received data in RX ring buffer.
+ *
+ * @param handle UART handle pointer.
+ * @return Length of received data in RX ring buffer.
+ */
+size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the ISR, the UART driver calls the callback
+ * function and passes the @ref kStatus_UART_TxIdle as status parameter.
+ *
+ * @note The kStatus_UART_TxIdle is passed to the upper layer when all data is written
+ * to the TX register. However, it does not ensure that all data is sent out. Before disabling the TX,
+ * check the kUART_TransmissionCompleteFlag to ensure that the TX is finished.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @param xfer UART transfer structure. See #uart_transfer_t.
+ * @retval kStatus_Success Successfully start the data transmission.
+ * @retval kStatus_UART_TxBusy Previous transmission still not finished; data not all written to TX register yet.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
+ * how many bytes are not sent out.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ */
+void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle);
+
+/*!
+ * @brief Gets the number of bytes written to the UART TX register.
+ *
+ * This function gets the number of bytes written to the UART TX
+ * register by using the interrupt method.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_NoTransferInProgress No send in progress.
+ * @retval kStatus_InvalidArgument The parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ * returns without waiting for all data to be received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough to read, the receive
+ * request is saved by the UART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the UART driver notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer.
+ * The 5 bytes are copied to the xfer->data and this function returns with the
+ * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is
+ * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to the xfer->data. When all data is received, the upper layer is notified.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @param xfer UART transfer structure, see #uart_transfer_t.
+ * @param receivedBytes Bytes received from the ring buffer directly.
+ * @retval kStatus_Success Successfully queue the transfer into transmit queue.
+ * @retval kStatus_UART_RxBusy Previous receive request is not finished.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t UART_TransferReceiveNonBlocking(UART_Type *base,
+ uart_handle_t *handle,
+ uart_transfer_t *xfer,
+ size_t *receivedBytes);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
+ * how many bytes are not received yet.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ */
+void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle);
+
+/*!
+ * @brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief UART IRQ handle function.
+ *
+ * This function handles the UART transmit and receive IRQ request.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ */
+void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle);
+
+/*!
+ * @brief UART Error IRQ handle function.
+ *
+ * This function handles the UART error IRQ request.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ */
+void UART_TransferHandleErrorIRQ(UART_Type *base, uart_handle_t *handle);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_UART_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/fsl_uart_cmsis.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/fsl_uart_cmsis.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,2849 @@
+/*
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
+ * Copyright 2016-2017 NXP. Not a Contribution.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "fsl_uart_cmsis.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.uart_cmsis"
+#endif
+
+#if ((RTE_USART0 && defined(UART0)) || (RTE_USART1 && defined(UART1)) || (RTE_USART2 && defined(UART2)) || \
+ (RTE_USART3 && defined(UART3)) || (RTE_USART4 && defined(UART4)) || (RTE_USART5 && defined(UART5)))
+
+#define ARM_UART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0)
+
+/*
+ * ARMCC does not support split the data section automatically, so the driver
+ * needs to split the data to separate sections explicitly, to reduce codesize.
+ */
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+#define ARMCC_SECTION(section_name) __attribute__((section(section_name)))
+#endif
+
+typedef const struct _cmsis_uart_resource
+{
+ UART_Type *base; /*!< uart peripheral base address. */
+ uint32_t (*GetFreq)(void); /*!< Function to get the clock frequency. */
+} cmsis_uart_resource_t;
+
+typedef struct _cmsis_uart_interrupt_driver_state
+{
+ cmsis_uart_resource_t *resource; /*!< Basic uart resource. */
+ uart_handle_t *handle; /*!< Interupt transfer handle. */
+ ARM_USART_SignalEvent_t cb_event; /*!< Callback function. */
+ uint8_t flags; /*!< Control and state flags. */
+} cmsis_uart_interrupt_driver_state_t;
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+typedef const struct _cmsis_uart_dma_resource
+{
+ DMA_Type *txDmaBase; /*!< DMA peripheral base address for TX. */
+ uint32_t txDmaChannel; /*!< DMA channel for uart TX. */
+ DMAMUX_Type *txDmamuxBase; /*!< DMAMUX peripheral base address for TX. */
+ uint8_t txDmaRequest; /*!< TX DMA request source. */
+
+ DMA_Type *rxDmaBase; /*!< DMA peripheral base address for RX. */
+ uint32_t rxDmaChannel; /*!< DMA channel for uart RX. */
+ DMAMUX_Type *rxDmamuxBase; /*!< DMAMUX peripheral base address for RX. */
+ uint8_t rxDmaRequest; /*!< RX DMA request source. */
+} cmsis_uart_dma_resource_t;
+
+typedef struct _cmsis_uart_dma_driver_state
+{
+ cmsis_uart_resource_t *resource; /*!< uart basic resource. */
+ cmsis_uart_dma_resource_t *dmaResource; /*!< uart DMA resource. */
+ uart_dma_handle_t *handle; /*!< uart DMA transfer handle. */
+ dma_handle_t *rxHandle; /*!< DMA RX handle. */
+ dma_handle_t *txHandle; /*!< DMA TX handle. */
+ ARM_USART_SignalEvent_t cb_event; /*!< Callback function. */
+ uint8_t flags; /*!< Control and state flags. */
+} cmsis_uart_dma_driver_state_t;
+#endif
+
+#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
+typedef const struct _cmsis_uart_edma_resource
+{
+ DMA_Type *txEdmaBase; /*!< EDMA peripheral base address for TX. */
+ uint32_t txEdmaChannel; /*!< EDMA channel for uart TX. */
+ DMAMUX_Type *txDmamuxBase; /*!< DMAMUX peripheral base address for TX. */
+ uint8_t txDmaRequest; /*!< TX EDMA request source. */
+
+ DMA_Type *rxEdmaBase; /*!< EDMA peripheral base address for RX. */
+ uint32_t rxEdmaChannel; /*!< EDMA channel for uart RX. */
+ DMAMUX_Type *rxDmamuxBase; /*!< DMAMUX peripheral base address for RX. */
+ uint8_t rxDmaRequest; /*!< RX EDMA request source. */
+} cmsis_uart_edma_resource_t;
+
+typedef struct _cmsis_uart_edma_driver_state
+{
+ cmsis_uart_resource_t *resource; /*!< uart basic resource. */
+ cmsis_uart_edma_resource_t *dmaResource; /*!< uart EDMA resource. */
+ uart_edma_handle_t *handle; /*!< uart EDMA transfer handle. */
+ edma_handle_t *rxHandle; /*!< EDMA RX handle. */
+ edma_handle_t *txHandle; /*!< EDMA TX handle. */
+ ARM_USART_SignalEvent_t cb_event; /*!< Callback function. */
+ uint8_t flags; /*!< Control and state flags. */
+} cmsis_uart_edma_driver_state_t;
+#endif
+
+enum _uart_transfer_states
+{
+ kuart_TxIdle, /*!< TX idle. */
+ kuart_TxBusy, /*!< TX busy. */
+ kuart_RxIdle, /*!< RX idle. */
+ kuart_RxBusy /*!< RX busy. */
+};
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION s_uartDriverVersion = {ARM_USART_API_VERSION, ARM_UART_DRV_VERSION};
+
+static const ARM_USART_CAPABILITIES s_uartDriverCapabilities = {
+ 1, /* supports uart (Asynchronous) mode */
+ 0, /* supports Synchronous Master mode */
+ 0, /* supports Synchronous Slave mode */
+ 0, /* supports uart Single-wire mode */
+ 0, /* supports uart IrDA mode */
+ 0, /* supports uart Smart Card mode */
+ 0, /* Smart Card Clock generator */
+ 0, /* RTS Flow Control available */
+ 0, /* CTS Flow Control available */
+ 0, /* Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE */
+ 0, /* Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT */
+ 0, /* RTS Line: 0=not available, 1=available */
+ 0, /* CTS Line: 0=not available, 1=available */
+ 0, /* DTR Line: 0=not available, 1=available */
+ 0, /* DSR Line: 0=not available, 1=available */
+ 0, /* DCD Line: 0=not available, 1=available */
+ 0, /* RI Line: 0=not available, 1=available */
+ 0, /* Signal CTS change event: \ref ARM_USART_EVENT_CTS */
+ 0, /* Signal DSR change event: \ref ARM_USART_EVENT_DSR */
+ 0, /* Signal DCD change event: \ref ARM_USART_EVENT_DCD */
+ 0, /* Signal RI change event: \ref ARM_USART_EVENT_RI */
+};
+
+/*
+ * Common control function used by uart_NonBlockingControl/uart_DmaControl/uart_EdmaControl
+ */
+static int32_t UART_CommonControl(uint32_t control,
+ uint32_t arg,
+ cmsis_uart_resource_t *resource,
+ uint8_t *isConfigured)
+{
+ uart_config_t config;
+
+ UART_GetDefaultConfig(&config);
+
+ switch (control & ARM_USART_CONTROL_Msk)
+ {
+ case ARM_USART_MODE_ASYNCHRONOUS:
+ /* USART Baudrate */
+ config.baudRate_Bps = arg;
+ break;
+
+ /* TX/RX IO is controlled in application layer. */
+ case ARM_USART_CONTROL_TX:
+ if (arg)
+ {
+ UART_EnableTx(resource->base, true);
+ }
+ else
+ {
+ UART_EnableTx(resource->base, false);
+ }
+ return ARM_DRIVER_OK;
+
+ case ARM_USART_CONTROL_RX:
+ if (arg)
+ {
+ UART_EnableRx(resource->base, true);
+ }
+ else
+ {
+ UART_EnableRx(resource->base, false);
+ }
+
+ return ARM_DRIVER_OK;
+
+ default:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+
+ switch (control & ARM_USART_PARITY_Msk)
+ {
+ case ARM_USART_PARITY_NONE:
+ config.parityMode = kUART_ParityDisabled;
+ break;
+ case ARM_USART_PARITY_EVEN:
+ config.parityMode = kUART_ParityEven;
+ break;
+ case ARM_USART_PARITY_ODD:
+ config.parityMode = kUART_ParityOdd;
+ break;
+ default:
+ return ARM_USART_ERROR_PARITY;
+ }
+
+ switch (control & ARM_USART_STOP_BITS_Msk)
+ {
+ case ARM_USART_STOP_BITS_1:
+ /* The GetDefaultConfig has already set for this case. */
+ break;
+#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT
+ case ARM_USART_STOP_BITS_2:
+ config.stopBitCount = kUART_TwoStopBit;
+ break;
+#endif
+ default:
+ return ARM_USART_ERROR_STOP_BITS;
+ }
+
+ /* If uart is already configured, deinit it first. */
+ if ((*isConfigured) & USART_FLAG_CONFIGURED)
+ {
+ UART_Deinit(resource->base);
+ *isConfigured &= ~USART_FLAG_CONFIGURED;
+ }
+
+ config.enableTx = true;
+ config.enableRx = true;
+
+ if (kStatus_UART_BaudrateNotSupport == UART_Init(resource->base, &config, resource->GetFreq()))
+ {
+ return ARM_USART_ERROR_BAUDRATE;
+ }
+
+ *isConfigured |= USART_FLAG_CONFIGURED;
+
+ return ARM_DRIVER_OK;
+}
+
+static ARM_DRIVER_VERSION UARTx_GetVersion(void)
+{
+ return s_uartDriverVersion;
+}
+
+static ARM_USART_CAPABILITIES UARTx_GetCapabilities(void)
+{
+ return s_uartDriverCapabilities;
+}
+
+static int32_t UARTx_SetModemControl(ARM_USART_MODEM_CONTROL control)
+{
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static ARM_USART_MODEM_STATUS UARTx_GetModemStatus(void)
+{
+ ARM_USART_MODEM_STATUS modem_status;
+
+ modem_status.cts = 0U;
+ modem_status.dsr = 0U;
+ modem_status.ri = 0U;
+ modem_status.dcd = 0U;
+ modem_status.reserved = 0U;
+
+ return modem_status;
+}
+
+#endif
+
+#if ((RTE_USART0_DMA_EN && defined(UART0)) || (RTE_USART1_DMA_EN && defined(UART1)) || \
+ (RTE_USART2_DMA_EN && defined(UART2)) || (RTE_USART3_DMA_EN && defined(UART3)) || \
+ (RTE_USART4_DMA_EN && defined(UART4)) || (RTE_USART5_DMA_EN && defined(UART5)))
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+void KSDK_UART_DmaCallback(UART_Type *base, uart_dma_handle_t *handle, status_t status, void *userData)
+{
+ uint32_t event = 0U;
+
+ if (kStatus_UART_TxIdle == status)
+ {
+ event = ARM_USART_EVENT_SEND_COMPLETE;
+ }
+ else if (kStatus_UART_RxIdle == status)
+ {
+ event = ARM_USART_EVENT_RECEIVE_COMPLETE;
+ }
+
+ /* User data is actually CMSIS driver callback. */
+ if ((0U != event) && (userData))
+ {
+ ((ARM_USART_SignalEvent_t)userData)(event);
+ }
+}
+
+static int32_t UART_DmaInitialize(ARM_USART_SignalEvent_t cb_event, cmsis_uart_dma_driver_state_t *uart)
+{
+ if (!(uart->flags & USART_FLAG_INIT))
+ {
+ uart->cb_event = cb_event;
+ uart->flags = USART_FLAG_INIT;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t UART_DmaUninitialize(cmsis_uart_dma_driver_state_t *uart)
+{
+ uart->flags = USART_FLAG_UNINIT;
+ return ARM_DRIVER_OK;
+}
+
+static int32_t UART_DmaPowerControl(ARM_POWER_STATE state, cmsis_uart_dma_driver_state_t *uart)
+{
+ uart_config_t config;
+ cmsis_uart_dma_resource_t *dmaResource;
+
+ switch (state)
+ {
+ case ARM_POWER_OFF:
+ if (uart->flags & USART_FLAG_POWER)
+ {
+ UART_Deinit(uart->resource->base);
+ DMAMUX_DisableChannel(uart->dmaResource->rxDmamuxBase, uart->dmaResource->rxDmaChannel);
+ DMAMUX_DisableChannel(uart->dmaResource->txDmamuxBase, uart->dmaResource->txDmaChannel);
+ uart->flags = USART_FLAG_INIT;
+ }
+ break;
+ case ARM_POWER_LOW:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ case ARM_POWER_FULL:
+ /* Must be initialized first. */
+ if (uart->flags == USART_FLAG_UNINIT)
+ {
+ return ARM_DRIVER_ERROR;
+ }
+
+ if (uart->flags & USART_FLAG_POWER)
+ {
+ /* Driver already powered */
+ break;
+ }
+
+ UART_GetDefaultConfig(&config);
+ config.enableTx = true;
+ config.enableRx = true;
+
+ dmaResource = uart->dmaResource;
+
+ /* Set up DMA setting. */
+ DMA_CreateHandle(uart->rxHandle, dmaResource->rxDmaBase, dmaResource->rxDmaChannel);
+ DMAMUX_SetSource(dmaResource->rxDmamuxBase, dmaResource->rxDmaChannel, dmaResource->rxDmaRequest);
+ DMAMUX_EnableChannel(dmaResource->rxDmamuxBase, dmaResource->rxDmaChannel);
+
+ DMA_CreateHandle(uart->txHandle, dmaResource->txDmaBase, dmaResource->txDmaChannel);
+ DMAMUX_SetSource(dmaResource->txDmamuxBase, dmaResource->txDmaChannel, dmaResource->txDmaRequest);
+ DMAMUX_EnableChannel(dmaResource->txDmamuxBase, dmaResource->txDmaChannel);
+
+ /* Setup the uart. */
+ UART_Init(uart->resource->base, &config, uart->resource->GetFreq());
+ UART_TransferCreateHandleDMA(uart->resource->base, uart->handle, KSDK_UART_DmaCallback,
+ (void *)uart->cb_event, uart->txHandle, uart->rxHandle);
+
+ uart->flags |= (USART_FLAG_POWER | USART_FLAG_CONFIGURED);
+ break;
+ default:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t UART_DmaSend(const void *data, uint32_t num, cmsis_uart_dma_driver_state_t *uart)
+{
+ int32_t ret;
+ status_t status;
+ uart_transfer_t xfer;
+
+ xfer.data = (uint8_t *)data;
+ xfer.dataSize = num;
+
+ status = UART_TransferSendDMA(uart->resource->base, uart->handle, &xfer);
+
+ switch (status)
+ {
+ case kStatus_Success:
+ ret = ARM_DRIVER_OK;
+ break;
+ case kStatus_InvalidArgument:
+ ret = ARM_DRIVER_ERROR_PARAMETER;
+ break;
+ case kStatus_UART_RxBusy:
+ ret = ARM_DRIVER_ERROR_BUSY;
+ break;
+ default:
+ ret = ARM_DRIVER_ERROR;
+ break;
+ }
+
+ return ret;
+}
+
+static int32_t UART_DmaReceive(void *data, uint32_t num, cmsis_uart_dma_driver_state_t *uart)
+{
+ int32_t ret;
+ status_t status;
+ uart_transfer_t xfer;
+
+ xfer.data = data;
+ xfer.dataSize = num;
+
+ status = UART_TransferReceiveDMA(uart->resource->base, uart->handle, &xfer);
+
+ switch (status)
+ {
+ case kStatus_Success:
+ ret = ARM_DRIVER_OK;
+ break;
+ case kStatus_InvalidArgument:
+ ret = ARM_DRIVER_ERROR_PARAMETER;
+ break;
+ case kStatus_UART_TxBusy:
+ ret = ARM_DRIVER_ERROR_BUSY;
+ break;
+ default:
+ ret = ARM_DRIVER_ERROR;
+ break;
+ }
+
+ return ret;
+}
+
+static int32_t UART_DmaTransfer(const void *data_out, void *data_in, uint32_t num, cmsis_uart_dma_driver_state_t *uart)
+{
+ /* Only in synchronous mode */
+ return ARM_DRIVER_ERROR;
+}
+
+static uint32_t UART_DmaGetTxCount(cmsis_uart_dma_driver_state_t *uart)
+{
+ uint32_t cnt;
+
+ /* If TX not in progress, then the TX count is txDataSizeAll saved in handle. */
+ if (kStatus_NoTransferInProgress == UART_TransferGetSendCountDMA(uart->resource->base, uart->handle, &cnt))
+ {
+ cnt = uart->handle->txDataSizeAll;
+ }
+
+ return cnt;
+}
+
+static uint32_t UART_DmaGetRxCount(cmsis_uart_dma_driver_state_t *uart)
+{
+ uint32_t cnt;
+
+ if (kStatus_NoTransferInProgress == UART_TransferGetReceiveCountDMA(uart->resource->base, uart->handle, &cnt))
+ {
+ cnt = uart->handle->rxDataSizeAll;
+ }
+
+ return cnt;
+}
+
+static int32_t UART_DmaControl(uint32_t control, uint32_t arg, cmsis_uart_dma_driver_state_t *uart)
+{
+ /* Must be power on. */
+ if (uart->flags & USART_FLAG_POWER)
+ {
+ return ARM_DRIVER_ERROR;
+ }
+
+ /* Does not support these features. */
+ if (control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk))
+ {
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+
+ switch (control & ARM_USART_CONTROL_Msk)
+ {
+ /* Abort Send */
+ case ARM_USART_ABORT_SEND:
+ UART_TransferAbortSendDMA(uart->resource->base, uart->handle);
+ return ARM_DRIVER_OK;
+
+ /* Abort receive */
+ case ARM_USART_ABORT_RECEIVE:
+ UART_TransferAbortReceiveDMA(uart->resource->base, uart->handle);
+ return ARM_DRIVER_OK;
+
+ default:
+ break;
+ }
+
+ return UART_CommonControl(control, arg, uart->resource, &uart->flags);
+}
+
+static ARM_USART_STATUS UART_DmaGetStatus(cmsis_uart_dma_driver_state_t *uart)
+{
+ ARM_USART_STATUS stat;
+ uint32_t ksdk_uart_status = UART_GetStatusFlags(uart->resource->base);
+
+ stat.tx_busy = ((kuart_TxBusy == uart->handle->txState) ? (1U) : (0U));
+ stat.rx_busy = ((kuart_RxBusy == uart->handle->rxState) ? (1U) : (0U));
+
+ stat.tx_underflow = 0U;
+ stat.rx_overflow = (!(!(ksdk_uart_status & kUART_RxOverrunFlag)));
+#if defined(FSL_FEATURE_uart_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_uart_HAS_LIN_BREAK_DETECT
+ stat.rx_break = (!(!(ksdk_uart_status & kuart_LinBreakFlag)));
+#else
+ stat.rx_break = 0U;
+#endif
+ stat.rx_framing_error = (!(!(ksdk_uart_status & kUART_FramingErrorFlag)));
+ stat.rx_parity_error = (!(!(ksdk_uart_status & kUART_ParityErrorFlag)));
+ stat.reserved = 0U;
+
+ return stat;
+}
+#endif
+
+#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
+void KSDK_UART_EdmaCallback(UART_Type *base, uart_edma_handle_t *handle, status_t status, void *userData)
+{
+ uint32_t event = 0U;
+
+ if (kStatus_UART_TxIdle == status)
+ {
+ event = ARM_USART_EVENT_SEND_COMPLETE;
+ }
+ if (kStatus_UART_RxIdle == status)
+ {
+ event = ARM_USART_EVENT_RECEIVE_COMPLETE;
+ }
+
+ /* User data is actually CMSIS driver callback. */
+ if ((0U != event) && (userData))
+ {
+ ((ARM_USART_SignalEvent_t)userData)(event);
+ }
+}
+
+static int32_t UART_EdmaInitialize(ARM_USART_SignalEvent_t cb_event, cmsis_uart_edma_driver_state_t *uart)
+{
+ if (!(uart->flags & USART_FLAG_INIT))
+ {
+ uart->cb_event = cb_event;
+ uart->flags = USART_FLAG_INIT;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t UART_EdmaUninitialize(cmsis_uart_edma_driver_state_t *uart)
+{
+ uart->flags = USART_FLAG_UNINIT;
+ return ARM_DRIVER_OK;
+}
+
+static int32_t UART_EdmaPowerControl(ARM_POWER_STATE state, cmsis_uart_edma_driver_state_t *uart)
+{
+ uart_config_t config;
+ cmsis_uart_edma_resource_t *dmaResource;
+
+ switch (state)
+ {
+ case ARM_POWER_OFF:
+ if (uart->flags & USART_FLAG_POWER)
+ {
+ UART_Deinit(uart->resource->base);
+ DMAMUX_DisableChannel(uart->dmaResource->rxDmamuxBase, uart->dmaResource->rxEdmaChannel);
+ DMAMUX_DisableChannel(uart->dmaResource->txDmamuxBase, uart->dmaResource->txEdmaChannel);
+ uart->flags = USART_FLAG_INIT;
+ }
+ break;
+ case ARM_POWER_LOW:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ case ARM_POWER_FULL:
+ if (uart->flags == USART_FLAG_UNINIT)
+ {
+ return ARM_DRIVER_ERROR;
+ }
+
+ if (uart->flags & USART_FLAG_POWER)
+ {
+ /* Driver already powered */
+ break;
+ }
+
+ UART_GetDefaultConfig(&config);
+ config.enableTx = true;
+ config.enableRx = true;
+
+ dmaResource = uart->dmaResource;
+
+ /* Set up EDMA setting. */
+ EDMA_CreateHandle(uart->rxHandle, dmaResource->rxEdmaBase, dmaResource->rxEdmaChannel);
+ DMAMUX_SetSource(dmaResource->rxDmamuxBase, dmaResource->rxEdmaChannel, dmaResource->rxDmaRequest);
+ DMAMUX_EnableChannel(dmaResource->rxDmamuxBase, dmaResource->rxEdmaChannel);
+
+ EDMA_CreateHandle(uart->txHandle, dmaResource->txEdmaBase, dmaResource->txEdmaChannel);
+ DMAMUX_SetSource(dmaResource->txDmamuxBase, dmaResource->txEdmaChannel, dmaResource->txDmaRequest);
+ DMAMUX_EnableChannel(dmaResource->txDmamuxBase, dmaResource->txEdmaChannel);
+
+ /* Setup the uart. */
+ UART_Init(uart->resource->base, &config, uart->resource->GetFreq());
+ UART_TransferCreateHandleEDMA(uart->resource->base, uart->handle, KSDK_UART_EdmaCallback,
+ (void *)uart->cb_event, uart->txHandle, uart->rxHandle);
+
+ uart->flags |= (USART_FLAG_CONFIGURED | USART_FLAG_POWER);
+ break;
+ default:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t UART_EdmaSend(const void *data, uint32_t num, cmsis_uart_edma_driver_state_t *uart)
+{
+ int32_t ret;
+ status_t status;
+ uart_transfer_t xfer;
+
+ xfer.data = (uint8_t *)data;
+ xfer.dataSize = num;
+
+ status = UART_SendEDMA(uart->resource->base, uart->handle, &xfer);
+
+ switch (status)
+ {
+ case kStatus_Success:
+ ret = ARM_DRIVER_OK;
+ break;
+ case kStatus_InvalidArgument:
+ ret = ARM_DRIVER_ERROR_PARAMETER;
+ break;
+ case kStatus_UART_RxBusy:
+ ret = ARM_DRIVER_ERROR_BUSY;
+ break;
+ default:
+ ret = ARM_DRIVER_ERROR;
+ break;
+ }
+
+ return ret;
+}
+
+static int32_t UART_EdmaReceive(void *data, uint32_t num, cmsis_uart_edma_driver_state_t *uart)
+{
+ int32_t ret;
+ status_t status;
+ uart_transfer_t xfer;
+
+ xfer.data = data;
+ xfer.dataSize = num;
+
+ status = UART_ReceiveEDMA(uart->resource->base, uart->handle, &xfer);
+
+ switch (status)
+ {
+ case kStatus_Success:
+ ret = ARM_DRIVER_OK;
+ break;
+ case kStatus_InvalidArgument:
+ ret = ARM_DRIVER_ERROR_PARAMETER;
+ break;
+ case kStatus_UART_RxBusy:
+ ret = ARM_DRIVER_ERROR_BUSY;
+ break;
+ default:
+ ret = ARM_DRIVER_ERROR;
+ break;
+ }
+
+ return ret;
+}
+
+static int32_t UART_EdmaTransfer(const void *data_out,
+ void *data_in,
+ uint32_t num,
+ cmsis_uart_edma_driver_state_t *uart)
+{
+ /* Only in synchronous mode */
+ return ARM_DRIVER_ERROR;
+}
+
+static uint32_t UART_EdmaGetTxCount(cmsis_uart_edma_driver_state_t *uart)
+{
+ uint32_t cnt;
+
+ if (kStatus_NoTransferInProgress == UART_TransferGetSendCountEDMA(uart->resource->base, uart->handle, &cnt))
+ {
+ cnt = uart->handle->txDataSizeAll;
+ }
+
+ return cnt;
+}
+
+static uint32_t UART_EdmaGetRxCount(cmsis_uart_edma_driver_state_t *uart)
+{
+ uint32_t cnt;
+
+ if (kStatus_NoTransferInProgress == UART_TransferGetReceiveCountEDMA(uart->resource->base, uart->handle, &cnt))
+ {
+ cnt = uart->handle->rxDataSizeAll;
+ }
+
+ return cnt;
+}
+
+static int32_t UART_EdmaControl(uint32_t control, uint32_t arg, cmsis_uart_edma_driver_state_t *uart)
+{
+ /* Must be power on. */
+ if (!(uart->flags & USART_FLAG_POWER))
+ {
+ return ARM_DRIVER_ERROR;
+ }
+
+ /* Does not support these features. */
+ if (control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk))
+ {
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+
+ switch (control & ARM_USART_CONTROL_Msk)
+ {
+ /* Abort Send */
+ case ARM_USART_ABORT_SEND:
+ UART_TransferAbortSendEDMA(uart->resource->base, uart->handle);
+ return ARM_DRIVER_OK;
+
+ /* Abort receive */
+ case ARM_USART_ABORT_RECEIVE:
+ UART_TransferAbortReceiveEDMA(uart->resource->base, uart->handle);
+ return ARM_DRIVER_OK;
+
+ default:
+ break;
+ }
+
+ return UART_CommonControl(control, arg, uart->resource, &uart->flags);
+}
+
+static ARM_USART_STATUS UART_EdmaGetStatus(cmsis_uart_edma_driver_state_t *uart)
+{
+ ARM_USART_STATUS stat;
+ uint32_t ksdk_uart_status = UART_GetStatusFlags(uart->resource->base);
+
+ stat.tx_busy = ((kuart_TxBusy == uart->handle->txState) ? (1U) : (0U));
+ stat.rx_busy = ((kuart_RxBusy == uart->handle->rxState) ? (1U) : (0U));
+
+ stat.tx_underflow = 0U;
+ stat.rx_overflow = (!(!(ksdk_uart_status & kUART_RxOverrunFlag)));
+#if defined(FSL_FEATURE_uart_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_uart_HAS_LIN_BREAK_DETECT
+ stat.rx_break = (!(!(ksdk_uart_status & kUART_LinBreakFlag)));
+#else
+ stat.rx_break = 0U;
+#endif
+ stat.rx_framing_error = (!(!(ksdk_uart_status & kUART_FramingErrorFlag)));
+ stat.rx_parity_error = (!(!(ksdk_uart_status & kUART_ParityErrorFlag)));
+ stat.reserved = 0U;
+
+ return stat;
+}
+#endif
+
+#endif
+
+#if (((RTE_USART0 && !RTE_USART0_DMA_EN) && defined(UART0)) || \
+ ((RTE_USART1 && !RTE_USART1_DMA_EN) && defined(UART1)) || \
+ ((RTE_USART2 && !RTE_USART2_DMA_EN) && defined(UART2)) || \
+ ((RTE_USART3 && !RTE_USART3_DMA_EN) && defined(UART3)) || \
+ ((RTE_USART4 && !RTE_USART4_DMA_EN) && defined(UART4)) || ((RTE_USART5 && !RTE_USART5_DMA_EN) && defined(UART5)))
+
+void KSDK_UART_NonBlockingCallback(UART_Type *base, uart_handle_t *handle, status_t status, void *userData)
+{
+ uint32_t event = 0U;
+
+ switch (status)
+ {
+ case kStatus_UART_TxIdle:
+ event = ARM_USART_EVENT_SEND_COMPLETE;
+ break;
+
+ case kStatus_UART_RxIdle:
+ event = ARM_USART_EVENT_RECEIVE_COMPLETE;
+ break;
+
+ case kStatus_UART_RxHardwareOverrun:
+ event = ARM_USART_EVENT_RX_OVERFLOW;
+ break;
+
+ case kStatus_UART_FramingError:
+ event = ARM_USART_EVENT_RX_FRAMING_ERROR;
+ break;
+
+ case kStatus_UART_ParityError:
+ event = ARM_USART_EVENT_RX_PARITY_ERROR;
+ break;
+
+ default:
+ event = 0U;
+ break;
+ }
+
+ /* User data is actually CMSIS driver callback. */
+ if ((0U != event) && (userData))
+ {
+ ((ARM_USART_SignalEvent_t)userData)(event);
+ }
+}
+
+static int32_t UART_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event, cmsis_uart_interrupt_driver_state_t *uart)
+{
+ if (!(uart->flags & USART_FLAG_INIT))
+ {
+ uart->cb_event = cb_event;
+ uart->flags = USART_FLAG_INIT;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t UART_NonBlockingUninitialize(cmsis_uart_interrupt_driver_state_t *uart)
+{
+ uart->flags = USART_FLAG_UNINIT;
+ return ARM_DRIVER_OK;
+}
+
+static int32_t UART_NonBlockingPowerControl(ARM_POWER_STATE state, cmsis_uart_interrupt_driver_state_t *uart)
+{
+ uart_config_t config;
+
+ switch (state)
+ {
+ case ARM_POWER_OFF:
+ if (uart->flags & USART_FLAG_POWER)
+ {
+ UART_Deinit(uart->resource->base);
+ uart->flags = USART_FLAG_INIT;
+ }
+ break;
+ case ARM_POWER_LOW:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ case ARM_POWER_FULL:
+ /* Must be initialized first. */
+ if (uart->flags == USART_FLAG_UNINIT)
+ {
+ return ARM_DRIVER_ERROR;
+ }
+
+ if (uart->flags & USART_FLAG_POWER)
+ {
+ /* Driver already powered */
+ break;
+ }
+
+ UART_GetDefaultConfig(&config);
+ config.enableTx = true;
+ config.enableRx = true;
+
+ UART_Init(uart->resource->base, &config, uart->resource->GetFreq());
+ UART_TransferCreateHandle(uart->resource->base, uart->handle, KSDK_UART_NonBlockingCallback,
+ (void *)uart->cb_event);
+ uart->flags |= (USART_FLAG_POWER | USART_FLAG_CONFIGURED);
+
+ break;
+ default:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t UART_NonBlockingSend(const void *data, uint32_t num, cmsis_uart_interrupt_driver_state_t *uart)
+{
+ int32_t ret;
+ status_t status;
+ uart_transfer_t xfer;
+
+ xfer.data = (uint8_t *)data;
+ xfer.dataSize = num;
+
+ status = UART_TransferSendNonBlocking(uart->resource->base, uart->handle, &xfer);
+
+ switch (status)
+ {
+ case kStatus_Success:
+ ret = ARM_DRIVER_OK;
+ break;
+ case kStatus_InvalidArgument:
+ ret = ARM_DRIVER_ERROR_PARAMETER;
+ break;
+ case kStatus_UART_TxBusy:
+ ret = ARM_DRIVER_ERROR_BUSY;
+ break;
+ default:
+ ret = ARM_DRIVER_ERROR;
+ break;
+ }
+
+ return ret;
+}
+
+static int32_t UART_NonBlockingReceive(void *data, uint32_t num, cmsis_uart_interrupt_driver_state_t *uart)
+{
+ int32_t ret;
+ status_t status;
+ uart_transfer_t xfer;
+
+ xfer.data = data;
+ xfer.dataSize = num;
+
+ status = UART_TransferReceiveNonBlocking(uart->resource->base, uart->handle, &xfer, NULL);
+
+ switch (status)
+ {
+ case kStatus_Success:
+ ret = ARM_DRIVER_OK;
+ break;
+ case kStatus_InvalidArgument:
+ ret = ARM_DRIVER_ERROR_PARAMETER;
+ break;
+ case kStatus_UART_RxBusy:
+ ret = ARM_DRIVER_ERROR_BUSY;
+ break;
+ default:
+ ret = ARM_DRIVER_ERROR;
+ break;
+ }
+
+ return ret;
+}
+
+static int32_t UART_NonBlockingTransfer(const void *data_out,
+ void *data_in,
+ uint32_t num,
+ cmsis_uart_interrupt_driver_state_t *uart)
+{
+ /* Only in synchronous mode */
+ return ARM_DRIVER_ERROR;
+}
+
+static uint32_t UART_NonBlockingGetTxCount(cmsis_uart_interrupt_driver_state_t *uart)
+{
+ uint32_t cnt;
+
+ /* If TX not in progress, then the TX count is txDataSizeAll saved in handle. */
+ if (kStatus_NoTransferInProgress == UART_TransferGetSendCount(uart->resource->base, uart->handle, &cnt))
+ {
+ cnt = uart->handle->txDataSizeAll;
+ }
+
+ return cnt;
+}
+
+static uint32_t UART_NonBlockingGetRxCount(cmsis_uart_interrupt_driver_state_t *uart)
+{
+ uint32_t cnt;
+
+ if (kStatus_NoTransferInProgress == UART_TransferGetReceiveCount(uart->resource->base, uart->handle, &cnt))
+ {
+ cnt = uart->handle->rxDataSizeAll;
+ }
+
+ return cnt;
+}
+
+static int32_t UART_NonBlockingControl(uint32_t control, uint32_t arg, cmsis_uart_interrupt_driver_state_t *uart)
+{
+ /* Must be power on. */
+ if (!(uart->flags & USART_FLAG_POWER))
+ {
+ return ARM_DRIVER_ERROR;
+ }
+
+ /* Does not support these features. */
+ if (control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk))
+ {
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+
+ switch (control & ARM_USART_CONTROL_Msk)
+ {
+ /* Abort Send */
+ case ARM_USART_ABORT_SEND:
+ UART_TransferAbortSend(uart->resource->base, uart->handle);
+ return ARM_DRIVER_OK;
+
+ /* Abort receive */
+ case ARM_USART_ABORT_RECEIVE:
+ UART_TransferAbortReceive(uart->resource->base, uart->handle);
+ return ARM_DRIVER_OK;
+
+ default:
+ break;
+ }
+
+ return UART_CommonControl(control, arg, uart->resource, &uart->flags);
+}
+
+static ARM_USART_STATUS UART_NonBlockingGetStatus(cmsis_uart_interrupt_driver_state_t *uart)
+{
+ ARM_USART_STATUS stat;
+ uint32_t ksdk_uart_status = UART_GetStatusFlags(uart->resource->base);
+
+ stat.tx_busy = ((kuart_TxBusy == uart->handle->txState) ? (1U) : (0U));
+ stat.rx_busy = ((kuart_RxBusy == uart->handle->rxState) ? (1U) : (0U));
+
+ stat.tx_underflow = 0U;
+ stat.rx_overflow = (!(!(ksdk_uart_status & kUART_RxOverrunFlag)));
+#if defined(FSL_FEATURE_uart_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_uart_HAS_LIN_BREAK_DETECT
+ stat.rx_break = (!(!(ksdk_uart_status & kuart_LinBreakFlag)));
+#else
+ stat.rx_break = 0U;
+#endif
+ stat.rx_framing_error = (!(!(ksdk_uart_status & kUART_FramingErrorFlag)));
+ stat.rx_parity_error = (!(!(ksdk_uart_status & kUART_ParityErrorFlag)));
+ stat.reserved = 0U;
+
+ return stat;
+}
+
+#endif
+
+#if (FSL_FEATURE_SOC_LPSCI_COUNT == 0) && (FSL_FEATURE_SOC_LPUART_COUNT != 2)
+
+#if defined(UART0) && RTE_USART0
+
+/* User needs to provide the implementation for UART0_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t UART0_GetFreq(void);
+extern void UART0_InitPins(void);
+extern void UART0_DeinitPins(void);
+
+cmsis_uart_resource_t uart0_Resource = {UART0, UART0_GetFreq};
+
+#if RTE_USART0_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+cmsis_uart_dma_resource_t uart0_DmaResource = {
+ RTE_USART0_DMA_TX_DMA_BASE, RTE_USART0_DMA_TX_CH, RTE_USART0_DMA_TX_DMAMUX_BASE, RTE_USART0_DMA_TX_PERI_SEL,
+
+ RTE_USART0_DMA_RX_DMA_BASE, RTE_USART0_DMA_RX_CH, RTE_USART0_DMA_RX_DMAMUX_BASE, RTE_USART0_DMA_RX_PERI_SEL,
+};
+
+uart_dma_handle_t UART0_DmaHandle;
+dma_handle_t UART0_DmaRxHandle;
+dma_handle_t UART0_DmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("uart0_dma_driver_state")
+cmsis_uart_dma_driver_state_t uart0_DmaDriverState = {
+#else
+cmsis_uart_dma_driver_state_t uart0_DmaDriverState = {
+#endif
+ &uart0_Resource, &uart0_DmaResource, &UART0_DmaHandle, &UART0_DmaRxHandle, &UART0_DmaTxHandle,
+};
+
+static int32_t UART0_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+ UART0_InitPins();
+ return UART_DmaInitialize(cb_event, &uart0_DmaDriverState);
+}
+
+static int32_t UART0_DmaUninitialize(void)
+{
+ UART0_DeinitPins();
+ return UART_DmaUninitialize(&uart0_DmaDriverState);
+}
+
+static int32_t UART0_DmaPowerControl(ARM_POWER_STATE state)
+{
+ return UART_DmaPowerControl(state, &uart0_DmaDriverState);
+}
+
+static int32_t UART0_DmaSend(const void *data, uint32_t num)
+{
+ return UART_DmaSend(data, num, &uart0_DmaDriverState);
+}
+
+static int32_t UART0_DmaReceive(void *data, uint32_t num)
+{
+ return UART_DmaReceive(data, num, &uart0_DmaDriverState);
+}
+
+static int32_t UART0_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+ return UART_DmaTransfer(data_out, data_in, num, &uart0_DmaDriverState);
+}
+
+static uint32_t UART0_DmaGetTxCount(void)
+{
+ return UART_DmaGetTxCount(&uart0_DmaDriverState);
+}
+
+static uint32_t UART0_DmaGetRxCount(void)
+{
+ return UART_DmaGetRxCount(&uart0_DmaDriverState);
+}
+
+static int32_t UART0_DmaControl(uint32_t control, uint32_t arg)
+{
+ return UART_DmaControl(control, arg, &uart0_DmaDriverState);
+}
+
+static ARM_USART_STATUS UART0_DmaGetStatus(void)
+{
+ return UART_DmaGetStatus(&uart0_DmaDriverState);
+}
+
+#endif
+
+#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
+
+cmsis_uart_edma_resource_t uart0_EdmaResource = {
+ RTE_USART0_DMA_TX_DMA_BASE, RTE_USART0_DMA_TX_CH, RTE_USART0_DMA_TX_DMAMUX_BASE, RTE_USART0_DMA_TX_PERI_SEL,
+
+ RTE_USART0_DMA_RX_DMA_BASE, RTE_USART0_DMA_RX_CH, RTE_USART0_DMA_RX_DMAMUX_BASE, RTE_USART0_DMA_RX_PERI_SEL,
+};
+
+uart_edma_handle_t UART0_EdmaHandle;
+edma_handle_t UART0_EdmaRxHandle;
+edma_handle_t UART0_EdmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("uart0_edma_driver_state")
+cmsis_uart_edma_driver_state_t uart0_EdmaDriverState = {
+#else
+cmsis_uart_edma_driver_state_t uart0_EdmaDriverState = {
+#endif
+ &uart0_Resource, &uart0_EdmaResource, &UART0_EdmaHandle, &UART0_EdmaRxHandle, &UART0_EdmaTxHandle,
+};
+
+static int32_t UART0_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+ UART0_InitPins();
+ return UART_EdmaInitialize(cb_event, &uart0_EdmaDriverState);
+}
+
+static int32_t UART0_EdmaUninitialize(void)
+{
+ UART0_DeinitPins();
+ return UART_EdmaUninitialize(&uart0_EdmaDriverState);
+}
+
+static int32_t UART0_EdmaPowerControl(ARM_POWER_STATE state)
+{
+ return UART_EdmaPowerControl(state, &uart0_EdmaDriverState);
+}
+
+static int32_t UART0_EdmaSend(const void *data, uint32_t num)
+{
+ return UART_EdmaSend(data, num, &uart0_EdmaDriverState);
+}
+
+static int32_t UART0_EdmaReceive(void *data, uint32_t num)
+{
+ return UART_EdmaReceive(data, num, &uart0_EdmaDriverState);
+}
+
+static int32_t UART0_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+ return UART_EdmaTransfer(data_out, data_in, num, &uart0_EdmaDriverState);
+}
+
+static uint32_t UART0_EdmaGetTxCount(void)
+{
+ return UART_EdmaGetTxCount(&uart0_EdmaDriverState);
+}
+
+static uint32_t UART0_EdmaGetRxCount(void)
+{
+ return UART_EdmaGetRxCount(&uart0_EdmaDriverState);
+}
+
+static int32_t UART0_EdmaControl(uint32_t control, uint32_t arg)
+{
+ return UART_EdmaControl(control, arg, &uart0_EdmaDriverState);
+}
+
+static ARM_USART_STATUS UART0_EdmaGetStatus(void)
+{
+ return UART_EdmaGetStatus(&uart0_EdmaDriverState);
+}
+
+#endif
+
+#else
+
+uart_handle_t UART0_Handle;
+
+#if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1)
+static uint8_t uart0_rxRingBuffer[USART_RX_BUFFER_LEN];
+#endif
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("uart0_non_blocking_driver_state")
+cmsis_uart_interrupt_driver_state_t uart0_NonBlockingDriverState = {
+#else
+cmsis_uart_interrupt_driver_state_t uart0_NonBlockingDriverState = {
+#endif
+ &uart0_Resource, &UART0_Handle,
+};
+
+static int32_t UART0_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+ UART0_InitPins();
+ return UART_NonBlockingInitialize(cb_event, &uart0_NonBlockingDriverState);
+}
+
+static int32_t UART0_NonBlockingUninitialize(void)
+{
+ UART0_DeinitPins();
+ return UART_NonBlockingUninitialize(&uart0_NonBlockingDriverState);
+}
+
+static int32_t UART0_NonBlockingPowerControl(ARM_POWER_STATE state)
+{
+ uint32_t result;
+
+ result = UART_NonBlockingPowerControl(state, &uart0_NonBlockingDriverState);
+
+#if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1)
+ if ((state == ARM_POWER_FULL) && (uart0_NonBlockingDriverState.handle->rxRingBuffer == NULL))
+ {
+ UART_TransferStartRingBuffer(uart0_NonBlockingDriverState.resource->base, uart0_NonBlockingDriverState.handle,
+ uart0_rxRingBuffer, USART_RX_BUFFER_LEN);
+ }
+#endif
+
+ return result;
+}
+
+static int32_t UART0_NonBlockingSend(const void *data, uint32_t num)
+{
+ return UART_NonBlockingSend(data, num, &uart0_NonBlockingDriverState);
+}
+
+static int32_t UART0_NonBlockingReceive(void *data, uint32_t num)
+{
+ return UART_NonBlockingReceive(data, num, &uart0_NonBlockingDriverState);
+}
+
+static int32_t UART0_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+ return UART_NonBlockingTransfer(data_out, data_in, num, &uart0_NonBlockingDriverState);
+}
+
+static uint32_t UART0_NonBlockingGetTxCount(void)
+{
+ return UART_NonBlockingGetTxCount(&uart0_NonBlockingDriverState);
+}
+
+static uint32_t UART0_NonBlockingGetRxCount(void)
+{
+ return UART_NonBlockingGetRxCount(&uart0_NonBlockingDriverState);
+}
+
+static int32_t UART0_NonBlockingControl(uint32_t control, uint32_t arg)
+{
+ int32_t result;
+
+ result = UART_NonBlockingControl(control, arg, &uart0_NonBlockingDriverState);
+ if (ARM_DRIVER_OK != result)
+ {
+ return result;
+ }
+ if (uart0_NonBlockingDriverState.handle->rxRingBuffer != NULL)
+ {
+ /* Enable the interrupt to accept the data when user need the ring buffer. */
+ UART_EnableInterrupts(uart0_NonBlockingDriverState.resource->base, kUART_RxDataRegFullInterruptEnable |
+ kUART_RxOverrunInterruptEnable |
+ kUART_FramingErrorInterruptEnable);
+ /* Enable parity error interrupt when parity mode is enable*/
+ if (UART_C1_PE_MASK & uart0_NonBlockingDriverState.resource->base->C1)
+ {
+ UART_EnableInterrupts(uart0_NonBlockingDriverState.resource->base, kUART_ParityErrorInterruptEnable);
+ }
+ }
+ return ARM_DRIVER_OK;
+}
+
+static ARM_USART_STATUS UART0_NonBlockingGetStatus(void)
+{
+ return UART_NonBlockingGetStatus(&uart0_NonBlockingDriverState);
+}
+
+#endif
+
+ARM_DRIVER_USART Driver_USART0 = {
+ UARTx_GetVersion, UARTx_GetCapabilities,
+#if RTE_USART0_DMA_EN
+#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
+ UART0_EdmaInitialize, UART0_EdmaUninitialize, UART0_EdmaPowerControl, UART0_EdmaSend, UART0_EdmaReceive,
+ UART0_EdmaTransfer, UART0_EdmaGetTxCount, UART0_EdmaGetRxCount, UART0_EdmaControl, UART0_EdmaGetStatus,
+#else
+ UART0_DmaInitialize, UART0_DmaUninitialize, UART0_DmaPowerControl, UART0_DmaSend, UART0_DmaReceive,
+ UART0_DmaTransfer, UART0_DmaGetTxCount, UART0_DmaGetRxCount, UART0_DmaControl, UART0_DmaGetStatus,
+#endif
+#else
+ UART0_NonBlockingInitialize,
+ UART0_NonBlockingUninitialize,
+ UART0_NonBlockingPowerControl,
+ UART0_NonBlockingSend,
+ UART0_NonBlockingReceive,
+ UART0_NonBlockingTransfer,
+ UART0_NonBlockingGetTxCount,
+ UART0_NonBlockingGetRxCount,
+ UART0_NonBlockingControl,
+ UART0_NonBlockingGetStatus,
+#endif
+ UARTx_SetModemControl, UARTx_GetModemStatus};
+
+#endif /* uart0 */
+
+#endif
+
+#if (FSL_FEATURE_SOC_LPUART_COUNT != 2)
+
+#if defined(UART1) && RTE_USART1
+
+/* User needs to provide the implementation for UART1_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t UART1_GetFreq(void);
+extern void UART1_InitPins(void);
+extern void UART1_DeinitPins(void);
+
+cmsis_uart_resource_t uart1_Resource = {UART1, UART1_GetFreq};
+
+#if RTE_USART1_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+cmsis_uart_dma_resource_t uart1_DmaResource = {
+ RTE_USART1_DMA_TX_DMA_BASE, RTE_USART1_DMA_TX_CH, RTE_USART1_DMA_TX_DMAMUX_BASE, RTE_USART1_DMA_TX_PERI_SEL,
+
+ RTE_USART1_DMA_RX_DMA_BASE, RTE_USART1_DMA_RX_CH, RTE_USART1_DMA_RX_DMAMUX_BASE, RTE_USART1_DMA_RX_PERI_SEL,
+};
+
+uart_dma_handle_t UART1_DmaHandle;
+dma_handle_t UART1_DmaRxHandle;
+dma_handle_t UART1_DmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("uart1_dma_driver_state")
+cmsis_uart_dma_driver_state_t uart1_DmaDriverState = {
+#else
+cmsis_uart_dma_driver_state_t uart1_DmaDriverState = {
+#endif
+ &uart1_Resource, &uart1_DmaResource, &UART1_DmaHandle, &UART1_DmaRxHandle, &UART1_DmaTxHandle,
+};
+
+static int32_t UART1_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+ UART1_InitPins();
+ return UART_DmaInitialize(cb_event, &uart1_DmaDriverState);
+}
+
+static int32_t UART1_DmaUninitialize(void)
+{
+ UART1_DeinitPins();
+ return UART_DmaUninitialize(&uart1_DmaDriverState);
+}
+
+static int32_t UART1_DmaPowerControl(ARM_POWER_STATE state)
+{
+ return UART_DmaPowerControl(state, &uart1_DmaDriverState);
+}
+
+static int32_t UART1_DmaSend(const void *data, uint32_t num)
+{
+ return UART_DmaSend(data, num, &uart1_DmaDriverState);
+}
+
+static int32_t UART1_DmaReceive(void *data, uint32_t num)
+{
+ return UART_DmaReceive(data, num, &uart1_DmaDriverState);
+}
+
+static int32_t UART1_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+ return UART_DmaTransfer(data_out, data_in, num, &uart1_DmaDriverState);
+}
+
+static uint32_t UART1_DmaGetTxCount(void)
+{
+ return UART_DmaGetTxCount(&uart1_DmaDriverState);
+}
+
+static uint32_t UART1_DmaGetRxCount(void)
+{
+ return UART_DmaGetRxCount(&uart1_DmaDriverState);
+}
+
+static int32_t UART1_DmaControl(uint32_t control, uint32_t arg)
+{
+ return UART_DmaControl(control, arg, &uart1_DmaDriverState);
+}
+
+static ARM_USART_STATUS UART1_DmaGetStatus(void)
+{
+ return UART_DmaGetStatus(&uart1_DmaDriverState);
+}
+
+#endif
+
+#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
+
+cmsis_uart_edma_resource_t uart1_EdmaResource = {
+ RTE_USART1_DMA_TX_DMA_BASE, RTE_USART1_DMA_TX_CH, RTE_USART1_DMA_TX_DMAMUX_BASE, RTE_USART1_DMA_TX_PERI_SEL,
+
+ RTE_USART1_DMA_RX_DMA_BASE, RTE_USART1_DMA_RX_CH, RTE_USART1_DMA_RX_DMAMUX_BASE, RTE_USART1_DMA_RX_PERI_SEL,
+};
+
+uart_edma_handle_t UART1_EdmaHandle;
+edma_handle_t UART1_EdmaRxHandle;
+edma_handle_t UART1_EdmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("uart1_edma_driver_state")
+cmsis_uart_edma_driver_state_t uart1_EdmaDriverState = {
+#else
+cmsis_uart_edma_driver_state_t uart1_EdmaDriverState = {
+#endif
+ &uart1_Resource, &uart1_EdmaResource, &UART1_EdmaHandle, &UART1_EdmaRxHandle, &UART1_EdmaTxHandle,
+};
+
+static int32_t UART1_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+ UART1_InitPins();
+ return UART_EdmaInitialize(cb_event, &uart1_EdmaDriverState);
+}
+
+static int32_t UART1_EdmaUninitialize(void)
+{
+ UART1_DeinitPins();
+ return UART_EdmaUninitialize(&uart1_EdmaDriverState);
+}
+
+static int32_t UART1_EdmaPowerControl(ARM_POWER_STATE state)
+{
+ return UART_EdmaPowerControl(state, &uart1_EdmaDriverState);
+}
+
+static int32_t UART1_EdmaSend(const void *data, uint32_t num)
+{
+ return UART_EdmaSend(data, num, &uart1_EdmaDriverState);
+}
+
+static int32_t UART1_EdmaReceive(void *data, uint32_t num)
+{
+ return UART_EdmaReceive(data, num, &uart1_EdmaDriverState);
+}
+
+static int32_t UART1_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+ return UART_EdmaTransfer(data_out, data_in, num, &uart1_EdmaDriverState);
+}
+
+static uint32_t UART1_EdmaGetTxCount(void)
+{
+ return UART_EdmaGetTxCount(&uart1_EdmaDriverState);
+}
+
+static uint32_t UART1_EdmaGetRxCount(void)
+{
+ return UART_EdmaGetRxCount(&uart1_EdmaDriverState);
+}
+
+static int32_t UART1_EdmaControl(uint32_t control, uint32_t arg)
+{
+ return UART_EdmaControl(control, arg, &uart1_EdmaDriverState);
+}
+
+static ARM_USART_STATUS UART1_EdmaGetStatus(void)
+{
+ return UART_EdmaGetStatus(&uart1_EdmaDriverState);
+}
+
+#endif
+
+#else
+
+uart_handle_t UART1_Handle;
+
+#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1)
+static uint8_t uart1_rxRingBuffer[USART_RX_BUFFER_LEN];
+#endif
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("uart1_non_blocking_driver_state")
+cmsis_uart_interrupt_driver_state_t uart1_NonBlockingDriverState = {
+#else
+cmsis_uart_interrupt_driver_state_t uart1_NonBlockingDriverState = {
+#endif
+ &uart1_Resource, &UART1_Handle,
+};
+
+static int32_t UART1_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+ UART1_InitPins();
+ return UART_NonBlockingInitialize(cb_event, &uart1_NonBlockingDriverState);
+}
+
+static int32_t UART1_NonBlockingUninitialize(void)
+{
+ UART1_DeinitPins();
+ return UART_NonBlockingUninitialize(&uart1_NonBlockingDriverState);
+}
+
+static int32_t UART1_NonBlockingPowerControl(ARM_POWER_STATE state)
+{
+ uint32_t result;
+
+ result = UART_NonBlockingPowerControl(state, &uart1_NonBlockingDriverState);
+
+#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1)
+ if ((state == ARM_POWER_FULL) && (uart1_NonBlockingDriverState.handle->rxRingBuffer == NULL))
+ {
+ UART_TransferStartRingBuffer(uart1_NonBlockingDriverState.resource->base, uart1_NonBlockingDriverState.handle,
+ uart1_rxRingBuffer, USART_RX_BUFFER_LEN);
+ }
+#endif
+
+ return result;
+}
+
+static int32_t UART1_NonBlockingSend(const void *data, uint32_t num)
+{
+ return UART_NonBlockingSend(data, num, &uart1_NonBlockingDriverState);
+}
+
+static int32_t UART1_NonBlockingReceive(void *data, uint32_t num)
+{
+ return UART_NonBlockingReceive(data, num, &uart1_NonBlockingDriverState);
+}
+
+static int32_t UART1_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+ return UART_NonBlockingTransfer(data_out, data_in, num, &uart1_NonBlockingDriverState);
+}
+
+static uint32_t UART1_NonBlockingGetTxCount(void)
+{
+ return UART_NonBlockingGetTxCount(&uart1_NonBlockingDriverState);
+}
+
+static uint32_t UART1_NonBlockingGetRxCount(void)
+{
+ return UART_NonBlockingGetRxCount(&uart1_NonBlockingDriverState);
+}
+
+static int32_t UART1_NonBlockingControl(uint32_t control, uint32_t arg)
+{
+ int32_t result;
+
+ result = UART_NonBlockingControl(control, arg, &uart1_NonBlockingDriverState);
+ if (ARM_DRIVER_OK != result)
+ {
+ return result;
+ }
+ if (uart1_NonBlockingDriverState.handle->rxRingBuffer != NULL)
+ {
+ /* Enable the interrupt to accept the data when user need the ring buffer. */
+ UART_EnableInterrupts(uart1_NonBlockingDriverState.resource->base, kUART_RxDataRegFullInterruptEnable |
+ kUART_RxOverrunInterruptEnable |
+ kUART_FramingErrorInterruptEnable);
+ /* Enable parity error interrupt when parity mode is enable*/
+ if (UART_C1_PE_MASK & uart1_NonBlockingDriverState.resource->base->C1)
+ {
+ UART_EnableInterrupts(uart1_NonBlockingDriverState.resource->base, kUART_ParityErrorInterruptEnable);
+ }
+ }
+ return ARM_DRIVER_OK;
+}
+
+static ARM_USART_STATUS UART1_NonBlockingGetStatus(void)
+{
+ return UART_NonBlockingGetStatus(&uart1_NonBlockingDriverState);
+}
+
+#endif
+
+ARM_DRIVER_USART Driver_USART1 = {
+ UARTx_GetVersion, UARTx_GetCapabilities,
+#if RTE_USART1_DMA_EN
+#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
+ UART1_EdmaInitialize, UART1_EdmaUninitialize, UART1_EdmaPowerControl, UART1_EdmaSend, UART1_EdmaReceive,
+ UART1_EdmaTransfer, UART1_EdmaGetTxCount, UART1_EdmaGetRxCount, UART1_EdmaControl, UART1_EdmaGetStatus,
+#else
+ UART1_DmaInitialize, UART1_DmaUninitialize, UART1_DmaPowerControl, UART1_DmaSend, UART1_DmaReceive,
+ UART1_DmaTransfer, UART1_DmaGetTxCount, UART1_DmaGetRxCount, UART1_DmaControl, UART1_DmaGetStatus,
+#endif
+#else
+ UART1_NonBlockingInitialize,
+ UART1_NonBlockingUninitialize,
+ UART1_NonBlockingPowerControl,
+ UART1_NonBlockingSend,
+ UART1_NonBlockingReceive,
+ UART1_NonBlockingTransfer,
+ UART1_NonBlockingGetTxCount,
+ UART1_NonBlockingGetRxCount,
+ UART1_NonBlockingControl,
+ UART1_NonBlockingGetStatus,
+#endif
+ UARTx_SetModemControl, UARTx_GetModemStatus};
+
+#endif /* uart1 */
+
+#endif
+
+#if defined(UART2) && RTE_USART2
+
+/* User needs to provide the implementation for UART2_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t UART2_GetFreq(void);
+extern void UART2_InitPins(void);
+extern void UART2_DeinitPins(void);
+
+cmsis_uart_resource_t uart2_Resource = {UART2, UART2_GetFreq};
+
+#if RTE_USART2_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+cmsis_uart_dma_resource_t uart2_DmaResource = {
+ RTE_USART2_DMA_TX_DMA_BASE, RTE_USART2_DMA_TX_CH, RTE_USART2_DMA_TX_DMAMUX_BASE, RTE_USART2_DMA_TX_PERI_SEL,
+
+ RTE_USART2_DMA_RX_DMA_BASE, RTE_USART2_DMA_RX_CH, RTE_USART2_DMA_RX_DMAMUX_BASE, RTE_USART2_DMA_RX_PERI_SEL,
+};
+
+uart_dma_handle_t UART2_DmaHandle;
+dma_handle_t UART2_DmaRxHandle;
+dma_handle_t UART2_DmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("uart2_dma_driver_state")
+cmsis_uart_dma_driver_state_t uart2_DmaDriverState = {
+#else
+cmsis_uart_dma_driver_state_t uart2_DmaDriverState = {
+#endif
+ &uart2_Resource, &uart2_DmaResource, &UART2_DmaHandle, &UART2_DmaRxHandle, &UART2_DmaTxHandle,
+};
+
+static int32_t UART2_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+ UART2_InitPins();
+ return UART_DmaInitialize(cb_event, &uart2_DmaDriverState);
+}
+
+static int32_t UART2_DmaUninitialize(void)
+{
+ UART2_DeinitPins();
+ return UART_DmaUninitialize(&uart2_DmaDriverState);
+}
+
+static int32_t UART2_DmaPowerControl(ARM_POWER_STATE state)
+{
+ return UART_DmaPowerControl(state, &uart2_DmaDriverState);
+}
+
+static int32_t UART2_DmaSend(const void *data, uint32_t num)
+{
+ return UART_DmaSend(data, num, &uart2_DmaDriverState);
+}
+
+static int32_t UART2_DmaReceive(void *data, uint32_t num)
+{
+ return UART_DmaReceive(data, num, &uart2_DmaDriverState);
+}
+
+static int32_t UART2_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+ return UART_DmaTransfer(data_out, data_in, num, &uart2_DmaDriverState);
+}
+
+static uint32_t UART2_DmaGetTxCount(void)
+{
+ return UART_DmaGetTxCount(&uart2_DmaDriverState);
+}
+
+static uint32_t UART2_DmaGetRxCount(void)
+{
+ return UART_DmaGetRxCount(&uart2_DmaDriverState);
+}
+
+static int32_t UART2_DmaControl(uint32_t control, uint32_t arg)
+{
+ return UART_DmaControl(control, arg, &uart2_DmaDriverState);
+}
+
+static ARM_USART_STATUS UART2_DmaGetStatus(void)
+{
+ return UART_DmaGetStatus(&uart2_DmaDriverState);
+}
+
+#endif
+
+#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
+
+cmsis_uart_edma_resource_t uart2_EdmaResource = {
+ RTE_USART2_DMA_TX_DMA_BASE, RTE_USART2_DMA_TX_CH, RTE_USART2_DMA_TX_DMAMUX_BASE, RTE_USART2_DMA_TX_PERI_SEL,
+
+ RTE_USART2_DMA_RX_DMA_BASE, RTE_USART2_DMA_RX_CH, RTE_USART2_DMA_RX_DMAMUX_BASE, RTE_USART2_DMA_RX_PERI_SEL,
+};
+
+uart_edma_handle_t UART2_EdmaHandle;
+edma_handle_t UART2_EdmaRxHandle;
+edma_handle_t UART2_EdmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("uart2_edma_driver_state")
+cmsis_uart_edma_driver_state_t uart2_EdmaDriverState = {
+#else
+cmsis_uart_edma_driver_state_t uart2_EdmaDriverState = {
+#endif
+ &uart2_Resource, &uart2_EdmaResource, &UART2_EdmaHandle, &UART2_EdmaRxHandle, &UART2_EdmaTxHandle,
+};
+
+static int32_t UART2_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+ UART2_InitPins();
+ return UART_EdmaInitialize(cb_event, &uart2_EdmaDriverState);
+}
+
+static int32_t UART2_EdmaUninitialize(void)
+{
+ UART2_DeinitPins();
+ return UART_EdmaUninitialize(&uart2_EdmaDriverState);
+}
+
+static int32_t UART2_EdmaPowerControl(ARM_POWER_STATE state)
+{
+ return UART_EdmaPowerControl(state, &uart2_EdmaDriverState);
+}
+
+static int32_t UART2_EdmaSend(const void *data, uint32_t num)
+{
+ return UART_EdmaSend(data, num, &uart2_EdmaDriverState);
+}
+
+static int32_t UART2_EdmaReceive(void *data, uint32_t num)
+{
+ return UART_EdmaReceive(data, num, &uart2_EdmaDriverState);
+}
+
+static int32_t UART2_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+ return UART_EdmaTransfer(data_out, data_in, num, &uart2_EdmaDriverState);
+}
+
+static uint32_t UART2_EdmaGetTxCount(void)
+{
+ return UART_EdmaGetTxCount(&uart2_EdmaDriverState);
+}
+
+static uint32_t UART2_EdmaGetRxCount(void)
+{
+ return UART_EdmaGetRxCount(&uart2_EdmaDriverState);
+}
+
+static int32_t UART2_EdmaControl(uint32_t control, uint32_t arg)
+{
+ return UART_EdmaControl(control, arg, &uart2_EdmaDriverState);
+}
+
+static ARM_USART_STATUS UART2_EdmaGetStatus(void)
+{
+ return UART_EdmaGetStatus(&uart2_EdmaDriverState);
+}
+
+#endif
+
+#else
+
+uart_handle_t UART2_Handle;
+
+#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1)
+static uint8_t uart2_rxRingBuffer[USART_RX_BUFFER_LEN];
+#endif
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("uart2_non_blocking_driver_state")
+cmsis_uart_interrupt_driver_state_t uart2_NonBlockingDriverState = {
+#else
+cmsis_uart_interrupt_driver_state_t uart2_NonBlockingDriverState = {
+#endif
+ &uart2_Resource, &UART2_Handle,
+};
+
+static int32_t UART2_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+ UART2_InitPins();
+ return UART_NonBlockingInitialize(cb_event, &uart2_NonBlockingDriverState);
+}
+
+static int32_t UART2_NonBlockingUninitialize(void)
+{
+ UART2_DeinitPins();
+ return UART_NonBlockingUninitialize(&uart2_NonBlockingDriverState);
+}
+
+static int32_t UART2_NonBlockingPowerControl(ARM_POWER_STATE state)
+{
+ uint32_t result;
+
+ result = UART_NonBlockingPowerControl(state, &uart2_NonBlockingDriverState);
+#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1)
+ if ((state == ARM_POWER_FULL) && (uart2_NonBlockingDriverState.handle->rxRingBuffer == NULL))
+ {
+ UART_TransferStartRingBuffer(uart2_NonBlockingDriverState.resource->base, uart2_NonBlockingDriverState.handle,
+ uart2_rxRingBuffer, USART_RX_BUFFER_LEN);
+ }
+#endif
+
+ return result;
+}
+
+static int32_t UART2_NonBlockingSend(const void *data, uint32_t num)
+{
+ return UART_NonBlockingSend(data, num, &uart2_NonBlockingDriverState);
+}
+
+static int32_t UART2_NonBlockingReceive(void *data, uint32_t num)
+{
+ return UART_NonBlockingReceive(data, num, &uart2_NonBlockingDriverState);
+}
+
+static int32_t UART2_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+ return UART_NonBlockingTransfer(data_out, data_in, num, &uart2_NonBlockingDriverState);
+}
+
+static uint32_t UART2_NonBlockingGetTxCount(void)
+{
+ return UART_NonBlockingGetTxCount(&uart2_NonBlockingDriverState);
+}
+
+static uint32_t UART2_NonBlockingGetRxCount(void)
+{
+ return UART_NonBlockingGetRxCount(&uart2_NonBlockingDriverState);
+}
+
+static int32_t UART2_NonBlockingControl(uint32_t control, uint32_t arg)
+{
+ int32_t result;
+
+ result = UART_NonBlockingControl(control, arg, &uart2_NonBlockingDriverState);
+ if (ARM_DRIVER_OK != result)
+ {
+ return result;
+ }
+ if (uart2_NonBlockingDriverState.handle->rxRingBuffer != NULL)
+ {
+ /* Enable the interrupt to accept the data when user need the ring buffer. */
+ UART_EnableInterrupts(uart2_NonBlockingDriverState.resource->base, kUART_RxDataRegFullInterruptEnable |
+ kUART_RxOverrunInterruptEnable |
+ kUART_FramingErrorInterruptEnable);
+ /* Enable parity error interrupt when parity mode is enable*/
+ if (UART_C1_PE_MASK & uart2_NonBlockingDriverState.resource->base->C1)
+ {
+ UART_EnableInterrupts(uart2_NonBlockingDriverState.resource->base, kUART_ParityErrorInterruptEnable);
+ }
+ }
+ return ARM_DRIVER_OK;
+}
+
+static ARM_USART_STATUS UART2_NonBlockingGetStatus(void)
+{
+ return UART_NonBlockingGetStatus(&uart2_NonBlockingDriverState);
+}
+
+#endif
+
+ARM_DRIVER_USART Driver_USART2 = {
+ UARTx_GetVersion, UARTx_GetCapabilities,
+#if RTE_USART2_DMA_EN
+#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
+ UART2_EdmaInitialize, UART2_EdmaUninitialize, UART2_EdmaPowerControl, UART2_EdmaSend, UART2_EdmaReceive,
+ UART2_EdmaTransfer, UART2_EdmaGetTxCount, UART2_EdmaGetRxCount, UART2_EdmaControl, UART2_EdmaGetStatus,
+#else
+ UART2_DmaInitialize, UART2_DmaUninitialize, UART2_DmaPowerControl, UART2_DmaSend, UART2_DmaReceive,
+ UART2_DmaTransfer, UART2_DmaGetTxCount, UART2_DmaGetRxCount, UART2_DmaControl, UART2_DmaGetStatus,
+#endif
+#else
+ UART2_NonBlockingInitialize,
+ UART2_NonBlockingUninitialize,
+ UART2_NonBlockingPowerControl,
+ UART2_NonBlockingSend,
+ UART2_NonBlockingReceive,
+ UART2_NonBlockingTransfer,
+ UART2_NonBlockingGetTxCount,
+ UART2_NonBlockingGetRxCount,
+ UART2_NonBlockingControl,
+ UART2_NonBlockingGetStatus,
+#endif
+ UARTx_SetModemControl, UARTx_GetModemStatus};
+
+#endif /* uart2 */
+
+#if defined(UART3) && RTE_USART3
+
+/* User needs to provide the implementation for UART3_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t UART3_GetFreq(void);
+extern void UART3_InitPins(void);
+extern void UART3_DeinitPins(void);
+
+cmsis_uart_resource_t uart3_Resource = {UART3, UART3_GetFreq};
+
+#if RTE_USART3_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+cmsis_uart_dma_resource_t uart3_DmaResource = {
+ RTE_USART3_DMA_TX_DMA_BASE, RTE_USART3_DMA_TX_CH, RTE_USART3_DMA_TX_DMAMUX_BASE, RTE_USART3_DMA_TX_PERI_SEL,
+
+ RTE_USART3_DMA_RX_DMA_BASE, RTE_USART3_DMA_RX_CH, RTE_USART3_DMA_RX_DMAMUX_BASE, RTE_USART3_DMA_RX_PERI_SEL,
+};
+
+uart_dma_handle_t UART3_DmaHandle;
+dma_handle_t UART3_DmaRxHandle;
+dma_handle_t UART3_DmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("uart3_dma_driver_state")
+cmsis_uart_dma_driver_state_t uart3_DmaDriverState = {
+#else
+cmsis_uart_dma_driver_state_t uart3_DmaDriverState = {
+#endif
+ &uart3_Resource, &uart3_DmaResource, &UART3_DmaHandle, &UART3_DmaRxHandle, &UART3_DmaTxHandle};
+
+static int32_t UART3_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+ UART3_InitPins();
+ return UART_DmaInitialize(cb_event, &uart3_DmaDriverState);
+}
+
+static int32_t UART3_DmaUninitialize(void)
+{
+ UART3_DeinitPins();
+ return UART_DmaUninitialize(&uart3_DmaDriverState);
+}
+
+static int32_t UART3_DmaPowerControl(ARM_POWER_STATE state)
+{
+ return UART_DmaPowerControl(state, &uart3_DmaDriverState);
+
+ static int32_t UART3_DmaSend(const void *data, uint32_t num)
+ {
+ return UART_DmaSend(data, num, &uart3_DmaDriverState);
+ }
+
+ static int32_t UART3_DmaReceive(void *data, uint32_t num)
+ {
+ return UART_DmaReceive(data, num, &uart3_DmaDriverState);
+ }
+
+ static int32_t UART3_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
+ {
+ return UART_DmaTransfer(data_out, data_in, num, &uart3_DmaDriverState);
+ }
+
+ static uint32_t UART3_DmaGetTxCount(void)
+ {
+ return UART_DmaGetTxCount(&uart3_DmaDriverState);
+ }
+
+ static uint32_t UART3_DmaGetRxCount(void)
+ {
+ return UART_DmaGetRxCount(&uart3_DmaDriverState);
+ }
+
+ static int32_t UART3_DmaControl(uint32_t control, uint32_t arg)
+ {
+ return UART_DmaControl(control, arg, &uart3_DmaDriverState);
+ }
+
+ static ARM_USART_STATUS UART3_DmaGetStatus(void)
+ {
+ return UART_DmaGetStatus(&uart3_DmaDriverState);
+ }
+
+#endif
+
+#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
+
+ cmsis_uart_edma_resource_t uart3_EdmaResource = {
+ RTE_USART3_DMA_TX_DMA_BASE, RTE_USART3_DMA_TX_CH, RTE_USART3_DMA_TX_DMAMUX_BASE, RTE_USART3_DMA_TX_PERI_SEL,
+
+ RTE_USART3_DMA_RX_DMA_BASE, RTE_USART3_DMA_RX_CH, RTE_USART3_DMA_RX_DMAMUX_BASE, RTE_USART3_DMA_RX_PERI_SEL,
+ };
+
+ uart_edma_handle_t UART3_EdmaHandle;
+ edma_handle_t UART3_EdmaRxHandle;
+ edma_handle_t UART3_EdmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ ARMCC_SECTION("uart3_edma_driver_state")
+ cmsis_uart_edma_driver_state_t uart3_EdmaDriverState =
+ {
+#else
+ cmsis_uart_edma_driver_state_t uart3_EdmaDriverState = {
+#endif
+ &uart3_Resource,
+ &uart3_EdmaResource,
+ &UART3_EdmaHandle,
+ &UART3_EdmaRxHandle,
+ &UART3_EdmaTxHandle,
+ };
+
+ static int32_t UART3_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
+ {
+ UART3_InitPins();
+ return UART_EdmaInitialize(cb_event, &uart3_EdmaDriverState);
+ }
+
+ static int32_t UART3_EdmaUninitialize(void)
+ {
+ UART3_DeinitPins();
+ return UART_EdmaUninitialize(&uart3_EdmaDriverState);
+ }
+
+ static int32_t UART3_EdmaPowerControl(ARM_POWER_STATE state)
+ {
+ return UART_EdmaPowerControl(state, &uart3_EdmaDriverState);
+ }
+
+ static int32_t UART3_EdmaSend(const void *data, uint32_t num)
+ {
+ return UART_EdmaSend(data, num, &uart3_EdmaDriverState);
+ }
+
+ static int32_t UART3_EdmaReceive(void *data, uint32_t num)
+ {
+ return UART_EdmaReceive(data, num, &uart3_EdmaDriverState);
+ }
+
+ static int32_t UART3_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
+ {
+ return UART_EdmaTransfer(data_out, data_in, num, &uart3_EdmaDriverState);
+ }
+
+ static uint32_t UART3_EdmaGetTxCount(void)
+ {
+ return UART_EdmaGetTxCount(&uart3_EdmaDriverState);
+ }
+
+ static uint32_t UART3_EdmaGetRxCount(void)
+ {
+ return UART_EdmaGetRxCount(&uart3_EdmaDriverState);
+ }
+
+ static int32_t UART3_EdmaControl(uint32_t control, uint32_t arg)
+ {
+ return UART_EdmaControl(control, arg, &uart3_EdmaDriverState);
+ }
+
+ static ARM_USART_STATUS UART3_EdmaGetStatus(void)
+ {
+ return UART_EdmaGetStatus(&uart3_EdmaDriverState);
+ }
+
+#endif
+
+#else
+
+uart_handle_t UART3_Handle;
+
+#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1)
+static uint8_t uart3_rxRingBuffer[USART_RX_BUFFER_LEN];
+#endif
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("uart3_non_blocking_driver_state")
+cmsis_uart_interrupt_driver_state_t uart3_NonBlockingDriverState =
+{
+#else
+cmsis_uart_interrupt_driver_state_t uart3_NonBlockingDriverState = {
+#endif
+ &uart3_Resource,
+ &UART3_Handle,
+};
+
+static int32_t UART3_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+ UART3_InitPins();
+ return UART_NonBlockingInitialize(cb_event, &uart3_NonBlockingDriverState);
+}
+
+static int32_t UART3_NonBlockingUninitialize(void)
+{
+ UART3_DeinitPins();
+ return UART_NonBlockingUninitialize(&uart3_NonBlockingDriverState);
+}
+
+static int32_t UART3_NonBlockingPowerControl(ARM_POWER_STATE state)
+{
+ uint32_t result;
+
+ result = UART_NonBlockingPowerControl(state, &uart3_NonBlockingDriverState);
+#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1)
+ if ((state == ARM_POWER_FULL) && (uart3_NonBlockingDriverState.handle->rxRingBuffer == NULL))
+ {
+ UART_TransferStartRingBuffer(uart3_NonBlockingDriverState.resource->base, uart3_NonBlockingDriverState.handle,
+ uart3_rxRingBuffer, USART_RX_BUFFER_LEN);
+ }
+#endif
+
+ return result;
+}
+
+static int32_t UART3_NonBlockingSend(const void *data, uint32_t num)
+{
+ return UART_NonBlockingSend(data, num, &uart3_NonBlockingDriverState);
+}
+
+static int32_t UART3_NonBlockingReceive(void *data, uint32_t num)
+{
+ return UART_NonBlockingReceive(data, num, &uart3_NonBlockingDriverState);
+}
+
+static int32_t UART3_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+ return UART_NonBlockingTransfer(data_out, data_in, num, &uart3_NonBlockingDriverState);
+}
+
+static uint32_t UART3_NonBlockingGetTxCount(void)
+{
+ return UART_NonBlockingGetTxCount(&uart3_NonBlockingDriverState);
+}
+
+static uint32_t UART3_NonBlockingGetRxCount(void)
+{
+ return UART_NonBlockingGetRxCount(&uart3_NonBlockingDriverState);
+}
+
+static int32_t UART3_NonBlockingControl(uint32_t control, uint32_t arg)
+{
+ int32_t result;
+
+ result = UART_NonBlockingControl(control, arg, &uart3_NonBlockingDriverState);
+ if (ARM_DRIVER_OK != result)
+ {
+ return result;
+ }
+ if (uart3_NonBlockingDriverState.handle->rxRingBuffer != NULL)
+ {
+ /* Enable the interrupt to accept the data when user need the ring buffer. */
+ UART_EnableInterrupts(uart3_NonBlockingDriverState.resource->base, kUART_RxDataRegFullInterruptEnable |
+ kUART_RxOverrunInterruptEnable |
+ kUART_FramingErrorInterruptEnable);
+ /* Enable parity error interrupt when parity mode is enable*/
+ if (UART_C1_PE_MASK & uart3_NonBlockingDriverState.resource->base->C1)
+ {
+ UART_EnableInterrupts(uart3_NonBlockingDriverState.resource->base, kUART_ParityErrorInterruptEnable);
+ }
+ }
+ return ARM_DRIVER_OK;
+}
+
+static ARM_USART_STATUS UART3_NonBlockingGetStatus(void)
+{
+ return UART_NonBlockingGetStatus(&uart3_NonBlockingDriverState);
+}
+
+#endif
+
+ ARM_DRIVER_USART Driver_USART3 =
+ {
+ UARTx_GetVersion,
+ UARTx_GetCapabilities,
+#if RTE_USART3_DMA_EN
+#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
+ UART3_EdmaInitialize,
+ UART3_EdmaUninitialize,
+ UART3_EdmaPowerControl,
+ UART3_EdmaSend,
+ UART3_EdmaReceive,
+ UART3_EdmaTransfer,
+ UART3_EdmaGetTxCount,
+ UART3_EdmaGetRxCount,
+ UART3_EdmaControl,
+ UART3_EdmaGetStatus,
+#else
+ UART3_DmaInitialize,
+ UART3_DmaUninitialize,
+ UART3_DmaPowerControl,
+ UART3_DmaSend,
+ UART3_DmaReceive,
+ UART3_DmaTransfer,
+ UART3_DmaGetTxCount,
+ UART3_DmaGetRxCount,
+ UART3_DmaControl,
+ UART3_DmaGetStatus,
+#endif
+#else
+ UART3_NonBlockingInitialize,
+ UART3_NonBlockingUninitialize,
+ UART3_NonBlockingPowerControl,
+ UART3_NonBlockingSend,
+ UART3_NonBlockingReceive,
+ UART3_NonBlockingTransfer,
+ UART3_NonBlockingGetTxCount,
+ UART3_NonBlockingGetRxCount,
+ UART3_NonBlockingControl,
+ UART3_NonBlockingGetStatus,
+#endif
+ UARTx_SetModemControl,
+ UARTx_GetModemStatus
+ };
+
+#endif /* uart3 */
+
+#if defined(UART4) && RTE_USART4
+
+ extern uint32_t UART4_GetFreq(void);
+ extern void UART4_InitPins(void);
+ extern void UART4_DeinitPins(void);
+
+ cmsis_uart_resource_t uart4_Resource = {UART4, UART4_GetFreq};
+
+#if RTE_USART4_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+ cmsis_uart_dma_resource_t uart4_DmaResource = {
+ RTE_USART4_DMA_TX_DMA_BASE, RTE_USART4_DMA_TX_CH, RTE_USART4_DMA_TX_DMAMUX_BASE, RTE_USART4_DMA_TX_PERI_SEL,
+
+ RTE_USART4_DMA_RX_DMA_BASE, RTE_USART4_DMA_RX_CH, RTE_USART4_DMA_RX_DMAMUX_BASE, RTE_USART4_DMA_RX_PERI_SEL,
+ };
+
+ uart_dma_handle_t UART4_DmaHandle;
+ dma_handle_t UART4_DmaRxHandle;
+ dma_handle_t UART4_DmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ ARMCC_SECTION("uart4_dma_driver_state")
+ cmsis_uart_dma_driver_state_t uart4_DmaDriverState =
+ {
+#else
+ cmsis_uart_dma_driver_state_t uart4_DmaDriverState = {
+#endif
+ &uart4_Resource,
+ &uart4_DmaResource,
+ &UART4_DmaHandle,
+ &UART4_DmaRxHandle,
+ &UART4_DmaTxHandle,
+ };
+
+ static int32_t UART4_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
+ {
+ UART4_InitPins();
+ return UART_DmaInitialize(cb_event, &uart4_DmaDriverState);
+ }
+
+ static int32_t UART4_DmaUninitialize(void)
+ {
+ UART4_DeinitPins();
+ return UART_DmaUninitialize(&uart4_DmaDriverState);
+ }
+
+ static int32_t UART4_DmaPowerControl(ARM_POWER_STATE state)
+ {
+ return UART_DmaPowerControl(state, &uart4_DmaDriverState);
+ }
+
+ static int32_t UART4_DmaSend(const void *data, uint32_t num)
+ {
+ return UART_DmaSend(data, num, &uart4_DmaDriverState);
+ }
+
+ static int32_t UART4_DmaReceive(void *data, uint32_t num)
+ {
+ return UART_DmaReceive(data, num, &uart4_DmaDriverState);
+ }
+
+ static int32_t UART4_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
+ {
+ return UART_DmaTransfer(data_out, data_in, num, &uart4_DmaDriverState);
+ }
+
+ static uint32_t UART4_DmaGetTxCount(void)
+ {
+ return UART_DmaGetTxCount(&uart4_DmaDriverState);
+ }
+
+ static uint32_t UART4_DmaGetRxCount(void)
+ {
+ return UART_DmaGetRxCount(&uart4_DmaDriverState);
+ }
+
+ static int32_t UART4_DmaControl(uint32_t control, uint32_t arg)
+ {
+ return UART_DmaControl(control, arg, &uart4_DmaDriverState);
+ }
+
+ static ARM_USART_STATUS UART4_DmaGetStatus(void)
+ {
+ return UART_DmaGetStatus(&uart4_DmaDriverState);
+ }
+
+#endif
+
+#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
+
+ cmsis_uart_edma_resource_t uart4_EdmaResource = {
+ RTE_USART4_DMA_TX_DMA_BASE, RTE_USART4_DMA_TX_CH, RTE_USART4_DMA_TX_DMAMUX_BASE, RTE_USART4_DMA_TX_PERI_SEL,
+
+ RTE_USART4_DMA_RX_DMA_BASE, RTE_USART4_DMA_RX_CH, RTE_USART4_DMA_RX_DMAMUX_BASE, RTE_USART4_DMA_RX_PERI_SEL,
+ };
+
+ uart_edma_handle_t UART4_EdmaHandle;
+ edma_handle_t UART4_EdmaRxHandle;
+ edma_handle_t UART4_EdmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ ARMCC_SECTION("uart4_edma_driver_state")
+ cmsis_uart_edma_driver_state_t uart4_EdmaDriverState =
+ {
+#else
+ cmsis_uart_edma_driver_state_t uart4_EdmaDriverState = {
+#endif
+ &uart4_Resource,
+ &uart4_EdmaResource,
+ &UART4_EdmaHandle,
+ &UART4_EdmaRxHandle,
+ &UART4_EdmaTxHandle,
+ };
+
+ static int32_t UART4_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
+ {
+ UART4_InitPins();
+ return UART_EdmaInitialize(cb_event, &uart4_EdmaDriverState);
+ }
+
+ static int32_t UART4_EdmaUninitialize(void)
+ {
+ UART4_DeinitPins();
+ return UART_EdmaUninitialize(&uart4_EdmaDriverState);
+ }
+
+ static int32_t UART4_EdmaPowerControl(ARM_POWER_STATE state)
+ {
+ return UART_EdmaPowerControl(state, &uart4_EdmaDriverState);
+ }
+
+ static int32_t UART4_EdmaSend(const void *data, uint32_t num)
+ {
+ return UART_EdmaSend(data, num, &uart4_EdmaDriverState);
+ }
+
+ static int32_t UART4_EdmaReceive(void *data, uint32_t num)
+ {
+ return UART_EdmaReceive(data, num, &uart4_EdmaDriverState);
+ }
+
+ static int32_t UART4_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
+ {
+ return UART_EdmaTransfer(data_out, data_in, num, &uart4_EdmaDriverState);
+ }
+
+ static uint32_t UART4_EdmaGetTxCount(void)
+ {
+ return UART_EdmaGetTxCount(&uart4_EdmaDriverState);
+ }
+
+ static uint32_t UART4_EdmaGetRxCount(void)
+ {
+ return UART_EdmaGetRxCount(&uart4_EdmaDriverState);
+ }
+
+ static int32_t UART4_EdmaControl(uint32_t control, uint32_t arg)
+ {
+ return UART_EdmaControl(control, arg, &uart4_EdmaDriverState);
+ }
+
+ static ARM_USART_STATUS UART4_EdmaGetStatus(void)
+ {
+ return UART_EdmaGetStatus(&uart4_EdmaDriverState);
+ }
+
+#endif
+
+#else
+
+uart_handle_t UART4_Handle;
+
+#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1)
+static uint8_t uart4_rxRingBuffer[USART_RX_BUFFER_LEN];
+#endif
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("uart4_non_blocking_driver_state")
+cmsis_uart_interrupt_driver_state_t uart4_NonBlockingDriverState =
+{
+#else
+cmsis_uart_interrupt_driver_state_t uart4_NonBlockingDriverState = {
+#endif
+ &uart4_Resource,
+ &UART4_Handle,
+};
+
+static int32_t UART4_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+ UART4_InitPins();
+ return UART_NonBlockingInitialize(cb_event, &uart4_NonBlockingDriverState);
+}
+
+static int32_t UART4_NonBlockingUninitialize(void)
+{
+ UART4_DeinitPins();
+ return UART_NonBlockingUninitialize(&uart4_NonBlockingDriverState);
+}
+
+static int32_t UART4_NonBlockingPowerControl(ARM_POWER_STATE state)
+{
+ uint32_t result;
+
+ result = UART_NonBlockingPowerControl(state, &uart4_NonBlockingDriverState);
+#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1)
+ if ((state == ARM_POWER_FULL) && (uart4_NonBlockingDriverState.handle->rxRingBuffer == NULL))
+ {
+ UART_TransferStartRingBuffer(uart4_NonBlockingDriverState.resource->base, uart4_NonBlockingDriverState.handle,
+ uart4_rxRingBuffer, USART_RX_BUFFER_LEN);
+ }
+#endif
+
+ return result;
+}
+
+static int32_t UART4_NonBlockingSend(const void *data, uint32_t num)
+{
+ return UART_NonBlockingSend(data, num, &uart4_NonBlockingDriverState);
+}
+
+static int32_t UART4_NonBlockingReceive(void *data, uint32_t num)
+{
+ return UART_NonBlockingReceive(data, num, &uart4_NonBlockingDriverState);
+}
+
+static int32_t UART4_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+ return UART_NonBlockingTransfer(data_out, data_in, num, &uart4_NonBlockingDriverState);
+}
+
+static uint32_t UART4_NonBlockingGetTxCount(void)
+{
+ return UART_NonBlockingGetTxCount(&uart4_NonBlockingDriverState);
+}
+
+static uint32_t UART4_NonBlockingGetRxCount(void)
+{
+ return UART_NonBlockingGetRxCount(&uart4_NonBlockingDriverState);
+}
+
+static int32_t UART4_NonBlockingControl(uint32_t control, uint32_t arg)
+{
+ int32_t result;
+
+ result = UART_NonBlockingControl(control, arg, &uart4_NonBlockingDriverState);
+ if (ARM_DRIVER_OK != result)
+ {
+ return result;
+ }
+ if (uart4_NonBlockingDriverState.handle->rxRingBuffer != NULL)
+ {
+ /* Enable the interrupt to accept the data when user need the ring buffer. */
+ UART_EnableInterrupts(uart4_NonBlockingDriverState.resource->base, kUART_RxDataRegFullInterruptEnable |
+ kUART_RxOverrunInterruptEnable |
+ kUART_FramingErrorInterruptEnable);
+ /* Enable parity error interrupt when parity mode is enable*/
+ if (UART_C1_PE_MASK & uart4_NonBlockingDriverState.resource->base->C1)
+ {
+ UART_EnableInterrupts(uart4_NonBlockingDriverState.resource->base, kUART_ParityErrorInterruptEnable);
+ }
+ }
+ return ARM_DRIVER_OK;
+}
+
+static ARM_USART_STATUS UART4_NonBlockingGetStatus(void)
+{
+ return UART_NonBlockingGetStatus(&uart4_NonBlockingDriverState);
+}
+
+#endif
+
+ ARM_DRIVER_USART Driver_USART4 =
+ {
+ UARTx_GetVersion,
+ UARTx_GetCapabilities,
+#if RTE_USART4_DMA_EN
+#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
+ UART4_EdmaInitialize,
+ UART4_EdmaUninitialize,
+ UART4_EdmaPowerControl,
+ UART4_EdmaSend,
+ UART4_EdmaReceive,
+ UART4_EdmaTransfer,
+ UART4_EdmaGetTxCount,
+ UART4_EdmaGetRxCount,
+ UART4_EdmaControl,
+ UART4_EdmaGetStatus,
+#else
+ UART4_DmaInitialize,
+ UART4_DmaUninitialize,
+ UART4_DmaPowerControl,
+ UART4_DmaSend,
+ UART4_DmaReceive,
+ UART4_DmaTransfer,
+ UART4_DmaGetTxCount,
+ UART4_DmaGetRxCount,
+ UART4_DmaControl,
+ UART4_DmaGetStatus,
+#endif
+#else
+ UART4_NonBlockingInitialize,
+ UART4_NonBlockingUninitialize,
+ UART4_NonBlockingPowerControl,
+ UART4_NonBlockingSend,
+ UART4_NonBlockingReceive,
+ UART4_NonBlockingTransfer,
+ UART4_NonBlockingGetTxCount,
+ UART4_NonBlockingGetRxCount,
+ UART4_NonBlockingControl,
+ UART4_NonBlockingGetStatus,
+#endif
+ UARTx_SetModemControl,
+ UARTx_GetModemStatus
+ };
+
+#endif /* uart4 */
+
+#if defined(UART5) && RTE_USART5
+
+ extern uint32_t UART5_GetFreq(void);
+ extern void UART5_InitPins(void);
+ extern void UART5_DeinitPins(void);
+
+ cmsis_uart_resource_t uart5_Resource = {UART5, UART5_GetFreq};
+
+#if RTE_USART5_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+ cmsis_uart_dma_resource_t uart5_DmaResource = {
+ RTE_USART5_DMA_TX_DMA_BASE, RTE_USART5_DMA_TX_CH, RTE_USART5_DMA_TX_DMAMUX_BASE, RTE_USART5_DMA_TX_PERI_SEL,
+
+ RTE_USART5_DMA_RX_DMA_BASE, RTE_USART5_DMA_RX_CH, RTE_USART5_DMA_RX_DMAMUX_BASE, RTE_USART5_DMA_RX_PERI_SEL,
+ };
+
+ uart_dma_handle_t UART5_DmaHandle;
+ dma_handle_t UART5_DmaRxHandle;
+ dma_handle_t UART5_DmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ ARMCC_SECTION("uart5_dma_driver_state")
+ cmsis_uart_dma_driver_state_t uart5_DmaDriverState =
+ {
+#else
+ cmsis_uart_dma_driver_state_t uart5_DmaDriverState = {
+#endif
+ &uart5_Resource,
+ &uart5_DmaResource,
+ &UART5_DmaHandle,
+ &UART5_DmaRxHandle,
+ UART5_DmaTxHandle,
+ };
+
+ static int32_t UART5_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
+ {
+ UART5_InitPins();
+ return UART_DmaInitialize(cb_event, &uart5_DmaDriverState);
+ }
+
+ static int32_t UART5_DmaUninitialize(void)
+ {
+ UART5_DeinitPins();
+ return UART_DmaUninitialize(&uart5_DmaDriverState);
+ }
+
+ static int32_t UART5_DmaPowerControl(ARM_POWER_STATE state)
+ {
+ return UART_DmaPowerControl(state, &uart5_DmaDriverState);
+ }
+
+ static int32_t UART5_DmaSend(const void *data, uint32_t num)
+ {
+ return UART_DmaSend(data, num, &uart5_DmaDriverState);
+ }
+
+ static int32_t UART5_DmaReceive(void *data, uint32_t num)
+ {
+ return UART_DmaReceive(data, num, &uart5_DmaDriverState);
+ }
+
+ static int32_t UART5_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
+ {
+ return UART_DmaTransfer(data_out, data_in, num, &uart5_DmaDriverState);
+ }
+
+ static uint32_t UART5_DmaGetTxCount(void)
+ {
+ return UART_DmaGetTxCount(&uart5_DmaDriverState);
+ }
+
+ static uint32_t UART5_DmaGetRxCount(void)
+ {
+ return UART_DmaGetRxCount(&uart5_DmaDriverState);
+ }
+
+ static int32_t UART5_DmaControl(uint32_t control, uint32_t arg)
+ {
+ return UART_DmaControl(control, arg, &uart5_DmaDriverState);
+ }
+
+ static ARM_USART_STATUS UART5_DmaGetStatus(void)
+ {
+ return UART_DmaGetStatus(&uart5_DmaDriverState);
+ }
+
+#endif
+
+#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
+
+ cmsis_uart_edma_resource_t uart5_EdmaResource = {
+ RTE_USART5_DMA_TX_DMA_BASE, RTE_USART5_DMA_TX_CH, RTE_USART5_DMA_TX_DMAMUX_BASE, RTE_USART5_DMA_TX_PERI_SEL,
+
+ RTE_USART5_DMA_RX_DMA_BASE, RTE_USART5_DMA_RX_CH, RTE_USART5_DMA_RX_DMAMUX_BASE, RTE_USART5_DMA_RX_PERI_SEL,
+ };
+
+ uart_edma_handle_t UART5_EdmaHandle;
+ edma_handle_t UART5_EdmaRxHandle;
+ edma_handle_t UART5_EdmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ ARMCC_SECTION("uart5_edma_driver_state")
+ cmsis_uart_edma_driver_state_t uart5_EdmaDriverState =
+ {
+#else
+ cmsis_uart_edma_driver_state_t uart5_EdmaDriverState = {
+#endif
+ &uart5_Resource,
+ &uart5_EdmaResource,
+ &UART5_EdmaHandle,
+ &UART5_EdmaRxHandle,
+ &UART5_EdmaTxHandle,
+ };
+
+ static int32_t UART5_EdmaInitialize(ARM_USART_SignalEvent_t cb_event)
+ {
+ UART5_InitPins();
+ return UART_EdmaInitialize(cb_event, &uart5_EdmaDriverState);
+ }
+
+ static int32_t UART5_EdmaUninitialize(void)
+ {
+ UART5_DeinitPins();
+ return UART_EdmaUninitialize(&uart5_EdmaDriverState);
+ }
+
+ static int32_t UART5_EdmaPowerControl(ARM_POWER_STATE state)
+ {
+ return UART_EdmaPowerControl(state, &uart5_EdmaDriverState);
+ }
+
+ static int32_t UART5_EdmaSend(const void *data, uint32_t num)
+ {
+ return UART_EdmaSend(data, num, &uart5_EdmaDriverState);
+ }
+
+ static int32_t UART5_EdmaReceive(void *data, uint32_t num)
+ {
+ return UART_EdmaReceive(data, num, &uart5_EdmaDriverState);
+ }
+
+ static int32_t UART5_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
+ {
+ return UART_EdmaTransfer(data_out, data_in, num, &uart5_EdmaDriverState);
+ }
+
+ static uint32_t UART5_EdmaGetTxCount(void)
+ {
+ return UART_EdmaGetTxCount(&uart5_EdmaDriverState);
+ }
+
+ static uint32_t UART5_EdmaGetRxCount(void)
+ {
+ return UART_EdmaGetRxCount(&uart5_EdmaDriverState);
+ }
+
+ static int32_t UART5_EdmaControl(uint32_t control, uint32_t arg)
+ {
+ return UART_EdmaControl(control, arg, &uart5_EdmaDriverState);
+ }
+
+ static ARM_USART_STATUS UART5_EdmaGetStatus(void)
+ {
+ return UART_EdmaGetStatus(&uart5_EdmaDriverState);
+ }
+
+#endif
+
+#else
+
+uart_handle_t UART5_Handle;
+
+#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1)
+static uint8_t uart5_rxRingBuffer[USART_RX_BUFFER_LEN];
+#endif
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("uart5_non_blocking_driver_state")
+cmsis_uart_interrupt_driver_state_t uart5_NonBlockingDriverState =
+{
+#else
+cmsis_uart_interrupt_driver_state_t uart5_NonBlockingDriverState = {
+#endif
+ &uart5_Resource,
+ &UART5_Handle,
+};
+
+static int32_t UART5_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+ UART5_InitPins();
+ return UART_NonBlockingInitialize(cb_event, &uart5_NonBlockingDriverState);
+}
+
+static int32_t UART5_NonBlockingUninitialize(void)
+{
+ UART5_DeinitPins();
+ return UART_NonBlockingUninitialize(&uart5_NonBlockingDriverState);
+}
+
+static int32_t UART5_NonBlockingPowerControl(ARM_POWER_STATE state)
+{
+ uint32_t result;
+
+ result = UART_NonBlockingPowerControl(state, &uart5_NonBlockingDriverState);
+#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1)
+ if ((state == ARM_POWER_FULL) && (uart5_NonBlockingDriverState.handle->rxRingBuffer == NULL))
+ {
+ UART_TransferStartRingBuffer(uart5_NonBlockingDriverState.resource->base, uart5_NonBlockingDriverState.handle,
+ uart5_rxRingBuffer, USART_RX_BUFFER_LEN);
+ }
+#endif
+
+ return result;
+}
+
+static int32_t UART5_NonBlockingSend(const void *data, uint32_t num)
+{
+ return UART_NonBlockingSend(data, num, &uart5_NonBlockingDriverState);
+}
+
+static int32_t UART5_NonBlockingReceive(void *data, uint32_t num)
+{
+ return UART_NonBlockingReceive(data, num, &uart5_NonBlockingDriverState);
+}
+
+static int32_t UART5_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+ return UART_NonBlockingTransfer(data_out, data_in, num, &uart5_NonBlockingDriverState);
+}
+
+static uint32_t UART5_NonBlockingGetTxCount(void)
+{
+ return UART_NonBlockingGetTxCount(&uart5_NonBlockingDriverState);
+}
+
+static uint32_t UART5_NonBlockingGetRxCount(void)
+{
+ return UART_NonBlockingGetRxCount(&uart5_NonBlockingDriverState);
+}
+
+static int32_t UART5_NonBlockingControl(uint32_t control, uint32_t arg)
+{
+ int32_t result;
+
+ result = UART_NonBlockingControl(control, arg, &uart5_NonBlockingDriverState);
+ if (ARM_DRIVER_OK != result)
+ {
+ return result;
+ }
+ if (uart5_NonBlockingDriverState.handle->rxRingBuffer != NULL)
+ {
+ /* Enable the interrupt to accept the data when user need the ring buffer. */
+ UART_EnableInterrupts(uart5_NonBlockingDriverState.resource->base, kUART_RxDataRegFullInterruptEnable |
+ kUART_RxOverrunInterruptEnable |
+ kUART_FramingErrorInterruptEnable);
+ /* Enable parity error interrupt when parity mode is enable*/
+ if (UART_C1_PE_MASK & uart5_NonBlockingDriverState.resource->base->C1)
+ {
+ UART_EnableInterrupts(uart5_NonBlockingDriverState.resource->base, kUART_ParityErrorInterruptEnable);
+ }
+ }
+ return ARM_DRIVER_OK;
+}
+
+static ARM_USART_STATUS UART5_NonBlockingGetStatus(void)
+{
+ return UART_NonBlockingGetStatus(&uart5_NonBlockingDriverState);
+}
+
+#endif
+
+ ARM_DRIVER_USART Driver_USART5 =
+ {
+ UARTx_GetVersion,
+ UARTx_GetCapabilities,
+#if RTE_USART5_DMA_EN
+#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
+ UART5_EdmaInitialize,
+ UART5_EdmaUninitialize,
+ UART5_EdmaPowerControl,
+ UART5_EdmaSend,
+ UART5_EdmaReceive,
+ UART5_EdmaTransfer,
+ UART5_EdmaGetTxCount,
+ UART5_EdmaGetRxCount,
+ UART5_EdmaControl,
+ UART5_EdmaGetStatus,
+#else
+ UART5_DmaInitialize,
+ UART5_DmaUninitialize,
+ UART5_DmaPowerControl,
+ UART5_DmaSend,
+ UART5_DmaReceive,
+ UART5_DmaTransfer,
+ UART5_DmaGetTxCount,
+ UART5_DmaGetRxCount,
+ UART5_DmaControl,
+ UART5_DmaGetStatus,
+#endif
+#else
+ UART5_NonBlockingInitialize,
+ UART5_NonBlockingUninitialize,
+ UART5_NonBlockingPowerControl,
+ UART5_NonBlockingSend,
+ UART5_NonBlockingReceive,
+ UART5_NonBlockingTransfer,
+ UART5_NonBlockingGetTxCount,
+ UART5_NonBlockingGetRxCount,
+ UART5_NonBlockingControl,
+ UART5_NonBlockingGetStatus,
+#endif
+ UARTx_SetModemControl,
+ UARTx_GetModemStatus
+ };
+
+#endif /* uart5 */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/fsl_uart_cmsis.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/freescale/k26f/fsl_uart_cmsis.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2017 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _FSL_UART_CMSIS_H_ +#define _FSL_UART_CMSIS_H_ + +#include "fsl_common.h" +#include "Driver_USART.h" +#include "RTE_Device.h" +#include "fsl_uart.h" +#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) +#include "fsl_dmamux.h" +#endif +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) +#include "fsl_uart_dma.h" +#endif +#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT) +#include "fsl_uart_edma.h" +#endif + +#if defined(UART0) +extern ARM_DRIVER_USART Driver_USART0; +#endif /* UART0 */ + +#if defined(UART1) +extern ARM_DRIVER_USART Driver_USART1; +#endif /* UART1 */ + +#if defined(UART2) +extern ARM_DRIVER_USART Driver_USART2; +#endif /* UART2 */ + +#if defined(UART3) +extern ARM_DRIVER_USART Driver_USART3; +#endif /* UART3 */ + +#if defined(UART4) +extern ARM_DRIVER_USART Driver_USART4; +#endif /* UART4 */ + +#if defined(UART5) +extern ARM_DRIVER_USART Driver_USART5; +#endif /* UART5 */ + +/* USART Driver state flags */ +#define USART_FLAG_UNINIT (0) +#define USART_FLAG_INIT (1 << 0) +#define USART_FLAG_POWER (1 << 1) +#define USART_FLAG_CONFIGURED (1 << 2) + +#endif /* _FSL_UART_CMSIS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/fsl_uart_edma.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/fsl_uart_edma.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,419 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_uart_edma.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.uart_edma"
+#endif
+
+/* Array of UART handle. */
+#if (defined(UART5))
+#define UART_HANDLE_ARRAY_SIZE 6
+#else /* UART5 */
+#if (defined(UART4))
+#define UART_HANDLE_ARRAY_SIZE 5
+#else /* UART4 */
+#if (defined(UART3))
+#define UART_HANDLE_ARRAY_SIZE 4
+#else /* UART3 */
+#if (defined(UART2))
+#define UART_HANDLE_ARRAY_SIZE 3
+#else /* UART2 */
+#if (defined(UART1))
+#define UART_HANDLE_ARRAY_SIZE 2
+#else /* UART1 */
+#if (defined(UART0))
+#define UART_HANDLE_ARRAY_SIZE 1
+#else /* UART0 */
+#error No UART instance.
+#endif /* UART 0 */
+#endif /* UART 1 */
+#endif /* UART 2 */
+#endif /* UART 3 */
+#endif /* UART 4 */
+#endif /* UART 5 */
+
+/*<! Structure definition for uart_edma_private_handle_t. The structure is private. */
+typedef struct _uart_edma_private_handle
+{
+ UART_Type *base;
+ uart_edma_handle_t *handle;
+} uart_edma_private_handle_t;
+
+/* UART EDMA transfer handle. */
+enum _uart_edma_tansfer_states
+{
+ kUART_TxIdle, /* TX idle. */
+ kUART_TxBusy, /* TX busy. */
+ kUART_RxIdle, /* RX idle. */
+ kUART_RxBusy /* RX busy. */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*<! Private handle only used for internally. */
+static uart_edma_private_handle_t s_edmaPrivateHandle[UART_HANDLE_ARRAY_SIZE];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief UART EDMA send finished callback function.
+ *
+ * This function is called when UART EDMA send finished. It disables the UART
+ * TX EDMA request and sends @ref kStatus_UART_TxIdle to UART callback.
+ *
+ * @param handle The EDMA handle.
+ * @param param Callback function parameter.
+ */
+static void UART_SendEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds);
+
+/*!
+ * @brief UART EDMA receive finished callback function.
+ *
+ * This function is called when UART EDMA receive finished. It disables the UART
+ * RX EDMA request and sends @ref kStatus_UART_RxIdle to UART callback.
+ *
+ * @param handle The EDMA handle.
+ * @param param Callback function parameter.
+ */
+static void UART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static void UART_SendEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
+{
+ assert(param);
+
+ uart_edma_private_handle_t *uartPrivateHandle = (uart_edma_private_handle_t *)param;
+
+ /* Avoid the warning for unused variables. */
+ handle = handle;
+ tcds = tcds;
+
+ if (transferDone)
+ {
+ UART_TransferAbortSendEDMA(uartPrivateHandle->base, uartPrivateHandle->handle);
+
+ if (uartPrivateHandle->handle->callback)
+ {
+ uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, kStatus_UART_TxIdle,
+ uartPrivateHandle->handle->userData);
+ }
+ }
+}
+
+static void UART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
+{
+ assert(param);
+
+ uart_edma_private_handle_t *uartPrivateHandle = (uart_edma_private_handle_t *)param;
+
+ /* Avoid warning for unused parameters. */
+ handle = handle;
+ tcds = tcds;
+
+ if (transferDone)
+ {
+ /* Disable transfer. */
+ UART_TransferAbortReceiveEDMA(uartPrivateHandle->base, uartPrivateHandle->handle);
+
+ if (uartPrivateHandle->handle->callback)
+ {
+ uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, kStatus_UART_RxIdle,
+ uartPrivateHandle->handle->userData);
+ }
+ }
+}
+
+/*!
+ * brief Initializes the UART handle which is used in transactional functions.
+ * param base UART peripheral base address.
+ * param handle Pointer to the uart_edma_handle_t structure.
+ * param callback UART callback, NULL means no callback.
+ * param userData User callback function data.
+ * param rxEdmaHandle User-requested DMA handle for RX DMA transfer.
+ * param txEdmaHandle User-requested DMA handle for TX DMA transfer.
+ */
+void UART_TransferCreateHandleEDMA(UART_Type *base,
+ uart_edma_handle_t *handle,
+ uart_edma_transfer_callback_t callback,
+ void *userData,
+ edma_handle_t *txEdmaHandle,
+ edma_handle_t *rxEdmaHandle)
+{
+ assert(handle);
+
+ uint32_t instance = UART_GetInstance(base);
+
+ s_edmaPrivateHandle[instance].base = base;
+ s_edmaPrivateHandle[instance].handle = handle;
+
+ memset(handle, 0, sizeof(*handle));
+
+ handle->rxState = kUART_RxIdle;
+ handle->txState = kUART_TxIdle;
+
+ handle->rxEdmaHandle = rxEdmaHandle;
+ handle->txEdmaHandle = txEdmaHandle;
+
+ handle->callback = callback;
+ handle->userData = userData;
+
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+ /* Note:
+ Take care of the RX FIFO, EDMA request only assert when received bytes
+ equal or more than RX water mark, there is potential issue if RX water
+ mark larger than 1.
+ For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and
+ 5 bytes are received. the last byte will be saved in FIFO but not trigger
+ EDMA transfer because the water mark is 2.
+ */
+ if (rxEdmaHandle)
+ {
+ base->RWFIFO = 1U;
+ }
+#endif
+
+ /* Configure TX. */
+ if (txEdmaHandle)
+ {
+ EDMA_SetCallback(handle->txEdmaHandle, UART_SendEDMACallback, &s_edmaPrivateHandle[instance]);
+ }
+
+ /* Configure RX. */
+ if (rxEdmaHandle)
+ {
+ EDMA_SetCallback(handle->rxEdmaHandle, UART_ReceiveEDMACallback, &s_edmaPrivateHandle[instance]);
+ }
+}
+
+/*!
+ * brief Sends data using eDMA.
+ *
+ * This function sends data using eDMA. This is a non-blocking function, which returns
+ * right away. When all data is sent, the send callback function is called.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * param xfer UART eDMA transfer structure. See #uart_transfer_t.
+ * retval kStatus_Success if succeeded; otherwise failed.
+ * retval kStatus_UART_TxBusy Previous transfer ongoing.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t UART_SendEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer)
+{
+ assert(handle);
+ assert(handle->txEdmaHandle);
+ assert(xfer);
+ assert(xfer->data);
+ assert(xfer->dataSize);
+
+ edma_transfer_config_t xferConfig;
+ status_t status;
+
+ /* If previous TX not finished. */
+ if (kUART_TxBusy == handle->txState)
+ {
+ status = kStatus_UART_TxBusy;
+ }
+ else
+ {
+ handle->txState = kUART_TxBusy;
+ handle->txDataSizeAll = xfer->dataSize;
+
+ /* Prepare transfer. */
+ EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (void *)UART_GetDataRegisterAddress(base),
+ sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_MemoryToPeripheral);
+
+ /* Store the initially configured eDMA minor byte transfer count into the UART handle */
+ handle->nbytes = sizeof(uint8_t);
+
+ /* Submit transfer. */
+ EDMA_SubmitTransfer(handle->txEdmaHandle, &xferConfig);
+ EDMA_StartTransfer(handle->txEdmaHandle);
+
+ /* Enable UART TX EDMA. */
+ UART_EnableTxDMA(base, true);
+
+ status = kStatus_Success;
+ }
+
+ return status;
+}
+
+/*!
+ * brief Receives data using eDMA.
+ *
+ * This function receives data using eDMA. This is a non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * param base UART peripheral base address.
+ * param handle Pointer to the uart_edma_handle_t structure.
+ * param xfer UART eDMA transfer structure. See #uart_transfer_t.
+ * retval kStatus_Success if succeeded; otherwise failed.
+ * retval kStatus_UART_RxBusy Previous transfer ongoing.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t UART_ReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer)
+{
+ assert(handle);
+ assert(handle->rxEdmaHandle);
+ assert(xfer);
+ assert(xfer->data);
+ assert(xfer->dataSize);
+
+ edma_transfer_config_t xferConfig;
+ status_t status;
+
+ /* If previous RX not finished. */
+ if (kUART_RxBusy == handle->rxState)
+ {
+ status = kStatus_UART_RxBusy;
+ }
+ else
+ {
+ handle->rxState = kUART_RxBusy;
+ handle->rxDataSizeAll = xfer->dataSize;
+
+ /* Prepare transfer. */
+ EDMA_PrepareTransfer(&xferConfig, (void *)UART_GetDataRegisterAddress(base), sizeof(uint8_t), xfer->data,
+ sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory);
+
+ /* Store the initially configured eDMA minor byte transfer count into the UART handle */
+ handle->nbytes = sizeof(uint8_t);
+
+ /* Submit transfer. */
+ EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig);
+ EDMA_StartTransfer(handle->rxEdmaHandle);
+
+ /* Enable UART RX EDMA. */
+ UART_EnableRxDMA(base, true);
+
+ status = kStatus_Success;
+ }
+
+ return status;
+}
+
+/*!
+ * brief Aborts the sent data using eDMA.
+ *
+ * This function aborts sent data using eDMA.
+ *
+ * param base UART peripheral base address.
+ * param handle Pointer to the uart_edma_handle_t structure.
+ */
+void UART_TransferAbortSendEDMA(UART_Type *base, uart_edma_handle_t *handle)
+{
+ assert(handle);
+ assert(handle->txEdmaHandle);
+
+ /* Disable UART TX EDMA. */
+ UART_EnableTxDMA(base, false);
+
+ /* Stop transfer. */
+ EDMA_AbortTransfer(handle->txEdmaHandle);
+
+ handle->txState = kUART_TxIdle;
+}
+
+/*!
+ * brief Aborts the receive data using eDMA.
+ *
+ * This function aborts receive data using eDMA.
+ *
+ * param base UART peripheral base address.
+ * param handle Pointer to the uart_edma_handle_t structure.
+ */
+void UART_TransferAbortReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle)
+{
+ assert(handle);
+ assert(handle->rxEdmaHandle);
+
+ /* Disable UART RX EDMA. */
+ UART_EnableRxDMA(base, false);
+
+ /* Stop transfer. */
+ EDMA_AbortTransfer(handle->rxEdmaHandle);
+
+ handle->rxState = kUART_RxIdle;
+}
+
+/*!
+ * brief Gets the number of received bytes.
+ *
+ * This function gets the number of received bytes.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * param count Receive bytes count.
+ * retval kStatus_NoTransferInProgress No receive in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t UART_TransferGetReceiveCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count)
+{
+ assert(handle);
+ assert(handle->rxEdmaHandle);
+ assert(count);
+
+ if (kUART_RxIdle == handle->rxState)
+ {
+ return kStatus_NoTransferInProgress;
+ }
+
+ *count = handle->rxDataSizeAll -
+ (uint32_t)handle->nbytes *
+ EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel);
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Gets the number of bytes that have been written to UART TX register.
+ *
+ * This function gets the number of bytes that have been written to UART TX
+ * register by DMA.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * param count Send bytes count.
+ * retval kStatus_NoTransferInProgress No send in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t UART_TransferGetSendCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count)
+{
+ assert(handle);
+ assert(handle->txEdmaHandle);
+ assert(count);
+
+ if (kUART_TxIdle == handle->txState)
+ {
+ return kStatus_NoTransferInProgress;
+ }
+
+ *count = handle->txDataSizeAll -
+ (uint32_t)handle->nbytes *
+ EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel);
+
+ return kStatus_Success;
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/fsl_uart_edma.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/fsl_uart_edma.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_UART_EDMA_H_
+#define _FSL_UART_EDMA_H_
+
+#include "fsl_uart.h"
+#include "fsl_edma.h"
+
+/*!
+ * @addtogroup uart_edma_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief UART EDMA driver version 2.1.6. */
+#define FSL_UART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 6))
+/*@}*/
+
+/* Forward declaration of the handle typedef. */
+typedef struct _uart_edma_handle uart_edma_handle_t;
+
+/*! @brief UART transfer callback function. */
+typedef void (*uart_edma_transfer_callback_t)(UART_Type *base,
+ uart_edma_handle_t *handle,
+ status_t status,
+ void *userData);
+
+/*!
+* @brief UART eDMA handle
+*/
+struct _uart_edma_handle
+{
+ uart_edma_transfer_callback_t callback; /*!< Callback function. */
+ void *userData; /*!< UART callback function parameter.*/
+ size_t rxDataSizeAll; /*!< Size of the data to receive. */
+ size_t txDataSizeAll; /*!< Size of the data to send out. */
+
+ edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */
+ edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */
+
+ uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */
+
+ volatile uint8_t txState; /*!< TX transfer state. */
+ volatile uint8_t rxState; /*!< RX transfer state */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name eDMA transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the UART handle which is used in transactional functions.
+ * @param base UART peripheral base address.
+ * @param handle Pointer to the uart_edma_handle_t structure.
+ * @param callback UART callback, NULL means no callback.
+ * @param userData User callback function data.
+ * @param rxEdmaHandle User-requested DMA handle for RX DMA transfer.
+ * @param txEdmaHandle User-requested DMA handle for TX DMA transfer.
+ */
+void UART_TransferCreateHandleEDMA(UART_Type *base,
+ uart_edma_handle_t *handle,
+ uart_edma_transfer_callback_t callback,
+ void *userData,
+ edma_handle_t *txEdmaHandle,
+ edma_handle_t *rxEdmaHandle);
+
+/*!
+ * @brief Sends data using eDMA.
+ *
+ * This function sends data using eDMA. This is a non-blocking function, which returns
+ * right away. When all data is sent, the send callback function is called.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @param xfer UART eDMA transfer structure. See #uart_transfer_t.
+ * @retval kStatus_Success if succeeded; otherwise failed.
+ * @retval kStatus_UART_TxBusy Previous transfer ongoing.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t UART_SendEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer);
+
+/*!
+ * @brief Receives data using eDMA.
+ *
+ * This function receives data using eDMA. This is a non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * @param base UART peripheral base address.
+ * @param handle Pointer to the uart_edma_handle_t structure.
+ * @param xfer UART eDMA transfer structure. See #uart_transfer_t.
+ * @retval kStatus_Success if succeeded; otherwise failed.
+ * @retval kStatus_UART_RxBusy Previous transfer ongoing.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t UART_ReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the sent data using eDMA.
+ *
+ * This function aborts sent data using eDMA.
+ *
+ * @param base UART peripheral base address.
+ * @param handle Pointer to the uart_edma_handle_t structure.
+ */
+void UART_TransferAbortSendEDMA(UART_Type *base, uart_edma_handle_t *handle);
+
+/*!
+ * @brief Aborts the receive data using eDMA.
+ *
+ * This function aborts receive data using eDMA.
+ *
+ * @param base UART peripheral base address.
+ * @param handle Pointer to the uart_edma_handle_t structure.
+ */
+void UART_TransferAbortReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle);
+
+/*!
+ * @brief Gets the number of bytes that have been written to UART TX register.
+ *
+ * This function gets the number of bytes that have been written to UART TX
+ * register by DMA.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_NoTransferInProgress No send in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t UART_TransferGetSendCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief Gets the number of received bytes.
+ *
+ * This function gets the number of received bytes.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t UART_TransferGetReceiveCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_UART_EDMA_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/fsl_usb.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/fsl_usb.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_USB_H__
+#define __FSL_USB_H__
+
+#include <stdint.h>
+#include <stdio.h>
+// #include "usb_osa.h"
+// #include "usb_misc.h"
+// #include "usb_spec.h"
+
+/*!
+ * @addtogroup usb_drv
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Defines USB stack major version */
+#define USB_STACK_VERSION_MAJOR (0x01U)
+/*! @brief Defines USB stack minor version */
+#define USB_STACK_VERSION_MINOR (0x00U)
+/*! @brief Defines USB stack bugfix version */
+#define USB_STACK_VERSION_BUGFIX (0x00U)
+
+/*! @brief USB stack version definition */
+#define USB_MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
+
+/*! @brief USB error code */
+typedef enum _usb_status
+{
+ kStatus_USB_Success = 0x00U, /*!< Success */
+ kStatus_USB_Error, /*!< Failed */
+
+ kStatus_USB_Busy, /*!< Busy */
+ kStatus_USB_InvalidHandle, /*!< Invalid handle */
+ kStatus_USB_InvalidParameter, /*!< Invalid parameter */
+ kStatus_USB_InvalidRequest, /*!< Invalid request */
+ kStatus_USB_ControllerNotFound, /*!< Controller cannot be found */
+ kStatus_USB_InvalidControllerInterface, /*!< Invalid controller interface */
+
+ kStatus_USB_NotSupported, /*!< Configuration is not supported */
+ kStatus_USB_Retry, /*!< Enumeration get configuration retry */
+ kStatus_USB_TransferStall, /*!< Transfer stalled */
+ kStatus_USB_TransferFailed, /*!< Transfer failed */
+ kStatus_USB_AllocFail, /*!< Allocation failed */
+ kStatus_USB_LackSwapBuffer, /*!< Insufficient swap buffer for KHCI */
+ kStatus_USB_TransferCancel, /*!< The transfer cancelled */
+ kStatus_USB_BandwidthFail, /*!< Allocate bandwidth failed */
+ kStatus_USB_MSDStatusFail, /*!< For MSD, the CSW status means fail */
+} usb_status_t;
+
+/*! @brief USB host handle type define */
+typedef void *usb_host_handle;
+
+/*! @brief USB device handle type define. For device stack it is the whole device handle; for host stack it is the
+ * attached device instance handle*/
+typedef void *usb_device_handle;
+
+/*! @brief USB OTG handle type define */
+typedef void *usb_otg_handle;
+
+/*! @brief USB controller ID */
+typedef enum _usb_controller_index
+{
+ kUSB_ControllerKhci0 = 0U, /*!< KHCI 0U */
+ kUSB_ControllerKhci1, /*!< KHCI 1U, Currently, there are no platforms which have two KHCI IPs, this is reserved
+ to be used in the future. */
+ kUSB_ControllerEhci0, /*!< EHCI 0U */
+ kUSB_ControllerEhci1, /*!< EHCI 1U, Currently, there are no platforms which have two KHCI IPs, this is reserved
+ to be used in the future. */
+} usb_controller_index_t;
+
+/**
+* @brief USB stack version fields
+*/
+typedef struct _usb_version
+{
+ uint8_t major; /*!< Major */
+ uint8_t minor; /*!< Minor */
+ uint8_t bugfix; /*!< Bug fix */
+} usb_version_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*! @} */
+
+#endif /* __FSL_USB_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/gpio.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/gpio.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,149 @@
+/**
+ * @file gpio.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * Copyright (c) 2016-2017 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "fsl_device_registers.h"
+#include "DAP_config.h"
+#include "gpio.h"
+#include "daplink.h"
+#include "hic_init.h"
+#include "fsl_clock.h"
+
+static void busy_wait(uint32_t cycles)
+{
+ volatile uint32_t i = cycles;
+ while (i > 0) {
+ i--;
+ }
+}
+
+void gpio_init(void)
+{
+ // Enable hardfault on unaligned access for the interface only.
+ // If this is done in the bootloader than then it might (will) break
+ // older application firmware or firmware from 3rd party vendors.
+#if defined(DAPLINK_IF)
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+ // enable clock to ports
+ SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK;
+ SIM->SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
+ // configure pin as GPIO
+ LED_CONNECTED_PORT->PCR[LED_CONNECTED_BIT] = PORT_PCR_MUX(1);
+ // led off - enable output
+ LED_CONNECTED_GPIO->PDOR = 1UL << LED_CONNECTED_BIT;
+ LED_CONNECTED_GPIO->PDDR = 1UL << LED_CONNECTED_BIT;
+ // led on
+ LED_CONNECTED_GPIO->PCOR = 1UL << LED_CONNECTED_BIT;
+ // reset button configured as gpio input
+ PIN_nRESET_GPIO->PDDR &= ~PIN_nRESET;
+ PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_MUX(1);
+ /* Enable LVLRST_EN */
+ PIN_nRESET_EN_PORT->PCR[PIN_nRESET_EN_BIT] = PORT_PCR_MUX(1) | /* GPIO */
+ PORT_PCR_ODE_MASK; /* Open-drain */
+ PIN_nRESET_EN_GPIO->PSOR = PIN_nRESET_EN;
+ PIN_nRESET_EN_GPIO->PDDR |= PIN_nRESET_EN;
+ // Configure SWO UART RX.
+ PIN_SWO_RX_PORT->PCR[PIN_SWO_RX_BIT] = PORT_PCR_MUX(3); // UART1
+ PIN_SWO_RX_GPIO->PDDR &= ~(1 << PIN_SWO_RX_BIT); // Input
+
+ // Enable pulldowns on power monitor control signals to reduce power consumption.
+ PIN_CTRL0_PORT->PCR[PIN_CTRL0_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);
+ PIN_CTRL1_PORT->PCR[PIN_CTRL1_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);
+ PIN_CTRL2_PORT->PCR[PIN_CTRL2_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);
+ PIN_CTRL3_PORT->PCR[PIN_CTRL3_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);
+
+ // Enable pulldown on GPIO0_B to prevent it floating.
+ PIN_GPIO0_B_PORT->PCR[PIN_GPIO0_B_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);
+
+ // configure power enable pin as GPIO
+ PIN_POWER_EN_PORT->PCR[PIN_POWER_EN_BIT] = PORT_PCR_MUX(1);
+ // set output to 0
+ PIN_POWER_EN_GPIO->PCOR = PIN_POWER_EN;
+ // switch gpio to output
+ PIN_POWER_EN_GPIO->PDDR |= PIN_POWER_EN;
+
+ // Let the voltage rails stabilize. This is especailly important
+ // during software resets, since the target's 3.3v rail can take
+ // 20-50ms to drain. During this time the target could be driving
+ // the reset pin low, causing the bootloader to think the reset
+ // button is pressed.
+ // Note: With optimization set to -O2 the value 1000000 delays for ~85ms
+ busy_wait(1000000);
+}
+
+void gpio_set_board_power(bool powerEnabled)
+{
+ if (powerEnabled) {
+ // enable power switch
+ PIN_POWER_EN_GPIO->PSOR = PIN_POWER_EN;
+ }
+ else {
+ // disable power switch
+ PIN_POWER_EN_GPIO->PCOR = PIN_POWER_EN;
+ }
+}
+
+uint32_t UART1_GetFreq(void)
+{
+ return CLOCK_GetCoreSysClkFreq();
+}
+
+void UART1_InitPins(void)
+{
+ // RX pin inited in gpio_init();
+ // TX not used.
+}
+
+void UART1_DeinitPins(void)
+{
+ // No need to deinit the RX pin.
+ // TX not used.
+}
+
+void gpio_set_hid_led(gpio_led_state_t state)
+{
+ if (state) {
+ LED_CONNECTED_GPIO->PCOR = LED_CONNECTED; // LED on
+ } else {
+ LED_CONNECTED_GPIO->PSOR = LED_CONNECTED; // LED off
+ }
+}
+
+void gpio_set_cdc_led(gpio_led_state_t state)
+{
+ gpio_set_hid_led(state);
+}
+
+void gpio_set_msc_led(gpio_led_state_t state)
+{
+ gpio_set_hid_led(state);
+}
+
+uint8_t gpio_get_reset_btn_no_fwrd(void)
+{
+ return (PIN_nRESET_GPIO->PDIR & PIN_nRESET) ? 0 : 1;
+}
+
+uint8_t gpio_get_reset_btn_fwrd(void)
+{
+ return 0;
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/hic_init.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/hic_init.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,156 @@
+/**
+ * @file hic_init.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * Copyright (c) 2016-2017 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "hic_init.h"
+#include "gpio.h"
+#include "fsl_clock.h"
+#include "usb_phy.h"
+#include "util.h"
+
+static void busy_wait(uint32_t cycles)
+{
+ volatile uint32_t i;
+ i = cycles;
+
+ while (i > 0) {
+ i--;
+ }
+}
+
+static void fll_delay(void)
+{
+ // ~2.5ms at 16MHz core clock
+ busy_wait(10000);
+}
+
+// This IRQ handler will be invoked if VDD falls below the trip point.
+void LVD_LVW_IRQHandler(void)
+{
+ if (PMC->LVDSC1 & PMC_LVDSC1_LVDF_MASK)
+ {
+ util_assert(false && "low voltage detect tripped");
+ PMC->LVDSC1 |= PMC_LVDSC1_LVDACK_MASK;
+ }
+ if (PMC->LVDSC2 & PMC_LVDSC2_LVWF_MASK)
+ {
+ util_assert(false && "low voltage warning tripped");
+ PMC->LVDSC2 |= PMC_LVDSC2_LVWACK_MASK;
+ }
+}
+
+//! - MPU is disabled and gated.
+//! - 8kB cache is enabled. SRAM is not cached, so no flushing is required for normal operation.
+//! - Enable low voltage warning interrupt.
+//! - Disable USB current limiter so the voltage doesn't drop as we enable high speed clocks.
+void sdk_init(void)
+{
+ CLOCK_SetXtal0Freq(16000000U); // 16 MHz crystal
+ CLOCK_SetXtal32Freq(0);
+
+ // Disable the MPU if it's enabled.
+ if (SIM->SCGC7 & SIM_SCGC7_MPU_MASK)
+ {
+ SYSMPU->CESR = 0;
+ SIM->SCGC7 &= ~SIM_SCGC7_MPU_MASK;
+ }
+
+ // Invalidate and enable code cache.
+ LMEM->PCCCR = LMEM_PCCCR_GO_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_ENCACHE_MASK;
+
+ // Enable LVD/LVW IRQ.
+ PMC->LVDSC1 |= PMC_LVDSC1_LVDACK_MASK;
+ PMC->LVDSC1 = PMC_LVDSC1_LVDIE_MASK | PMC_LVDSC1_LVDV(0); // low trip point
+ PMC->LVDSC2 |= PMC_LVDSC2_LVWACK_MASK;
+ PMC->LVDSC2 = PMC_LVDSC2_LVWIE_MASK | PMC_LVDSC2_LVWV(0); // low trip point
+// NVIC_EnableIRQ(LVD_LVW_IRQn);
+
+ // Disable USB inrush current limiter.
+ SIM->USBPHYCTL |= SIM_USBPHYCTL_USBDISILIM_MASK;
+}
+
+//! - Turn on 16MHz crystal oscillator.
+//! - Turn on 32kHz IRC.
+//! - Switch core clock to System PLL at 120 MHz, bus clock at 60 MHz, flash clock at 24 MHz.
+//! - Enable the 480MHz USB PHY PLL.
+//! - Ungate USBPHY and USBHS.
+//! - Configure the USB PHY.
+void hic_enable_usb_clocks(void)
+{
+ // Enable external oscillator and 32kHz IRC.
+ MCG->C1 |= MCG_C1_IRCLKEN_MASK; // Select 32k IR.
+ // Delay at least 100µs for 32kHz IRQ to stabilize.
+ fll_delay();
+ // Configure OSC for very high freq, low power mode.
+ MCG->C2 = (MCG->C2 & ~(MCG_C2_RANGE_MASK | MCG_C2_HGO_MASK)) | MCG_C2_RANGE(2);
+ OSC0->CR |= OSC_CR_ERCLKEN_MASK; // Enable OSC.
+ MCG->C2 |= MCG_C2_EREFS_MASK; // Select OSC as ext ref.
+
+ // Wait for the oscillator to stabilize.
+ while (!(MCG->S & MCG_S_OSCINIT0_MASK))
+ {
+ }
+
+ // Divide 16MHz xtal by 512 = 31.25kHz
+ CLOCK_SetFbeMode(4, kMCG_Dmx32Default, kMCG_DrsMid, fll_delay);
+
+ // Set dividers before switching to SYSPLL.
+ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) // System/core /1 = 120MHz
+ | SIM_CLKDIV1_OUTDIV2(1) // Bus /2 = 60Mhz
+ | SIM_CLKDIV1_OUTDIV3(4) // FlexBus /5 = 24Mhz
+ | SIM_CLKDIV1_OUTDIV4(4); // Flash /5 = 24MHz
+
+ // 120MHz SYSPLL
+ mcg_pll_config_t pllConfig;
+ pllConfig.enableMode = 0;
+ pllConfig.prdiv = 2 - 1;
+ pllConfig.vdiv = 30 - 16;
+ CLOCK_SetPbeMode(kMCG_PllClkSelPll0, &pllConfig);
+ CLOCK_SetPeeMode();
+
+ // Enable USB clock source and init phy. This turns on the 480MHz PLL.
+ CLOCK_EnableUsbhs0Clock(kCLOCK_UsbSrcPll0, CLOCK_GetFreq(kCLOCK_PllFllSelClk));
+ USB_EhciPhyInit(0, CPU_XTAL_CLK_HZ);
+
+ SystemCoreClockUpdate();
+}
+
+void hic_power_target(void)
+{
+ // Keep powered off in bootloader mode
+ // to prevent the target from effecting the state
+ // of the reset line / reset button
+ if (!daplink_is_bootloader()) {
+ // configure pin as GPIO
+ PIN_POWER_EN_PORT->PCR[PIN_POWER_EN_BIT] = PORT_PCR_MUX(1);
+ // force always on logic 1
+ PIN_POWER_EN_GPIO->PSOR = 1UL << PIN_POWER_EN_BIT;
+ PIN_POWER_EN_GPIO->PDDR |= 1UL << PIN_POWER_EN_BIT;
+
+ // Let the voltage rails stabilize. This is especailly important
+ // during software resets, since the target's 3.3v rail can take
+ // 20-50ms to drain. During this time the target could be driving
+ // the reset pin low, causing the bootloader to think the reset
+ // button is pressed.
+ // Note: With optimization set to -O2 the value 5115 delays for ~1ms @ 20.9Mhz core
+ busy_wait(5115 * 50);
+ }
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/hic_init.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/hic_init.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,35 @@
+/**
+ * @file hic_init.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * Copyright (c) 2016-2017 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+//! @brief Set some system-wide hardware settings.
+void hic_init(void);
+
+//! @brief Enable clocks required for USB operation.
+void hic_enable_usb_clocks(void);
+
+#if defined(__cplusplus)
+}
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/read_uid.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/read_uid.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,31 @@
+/**
+ * @file read_uid.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "fsl_device_registers.h"
+#include "read_uid.h"
+
+void read_unique_id(uint32_t *id)
+{
+ id[0] = SIM->UIDL;
+ id[1] = SIM->UIDML;
+ id[2] = SIM->UIDMH;
+ id[3] = SIM->UIDH;
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/uart.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/uart.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,242 @@
+/**
+ * @file uart.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * Copyright (c) 2016-2017 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "string.h"
+#include "fsl_device_registers.h"
+#include "uart.h"
+#include "util.h"
+#include "cortex_m.h"
+#include "circ_buf.h"
+#include "settings.h" // for config_get_overflow_detect
+
+#define UART_INSTANCE (UART0)
+#define UART_IRQ (UART0_RX_TX_IRQn)
+
+extern uint32_t SystemCoreClock;
+
+static void clear_buffers(void);
+
+#define RX_OVRF_MSG "<DAPLink:Overflow>\n"
+#define RX_OVRF_MSG_SIZE (sizeof(RX_OVRF_MSG) - 1)
+#define BUFFER_SIZE (512)
+
+
+circ_buf_t write_buffer;
+uint8_t write_buffer_data[BUFFER_SIZE];
+circ_buf_t read_buffer;
+uint8_t read_buffer_data[BUFFER_SIZE];
+
+void clear_buffers(void)
+{
+ util_assert(!(UART_INSTANCE->C2 & UART_C2_TIE_MASK));
+ circ_buf_init(&write_buffer, write_buffer_data, sizeof(write_buffer_data));
+ circ_buf_init(&read_buffer, read_buffer_data, sizeof(read_buffer_data));
+}
+
+int32_t uart_initialize(void)
+{
+ NVIC_DisableIRQ(UART_IRQ);
+ // enable clk PORTC
+ SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK;
+ // enable clk uart
+ SIM->SCGC4 |= SIM_SCGC4_UART0_MASK;
+
+ // disable interrupt
+ NVIC_DisableIRQ(UART_IRQ);
+ // transmitter and receiver disabled
+ UART_INSTANCE->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);
+ // disable interrupt
+ UART_INSTANCE->C2 &= ~(UART_C2_RIE_MASK | UART_C2_TIE_MASK);
+
+ clear_buffers();
+
+ // Enable receiver and transmitter
+ UART_INSTANCE->C2 |= UART_C2_RE_MASK | UART_C2_TE_MASK;
+
+ // alternate 3: UART0
+ PORTB->PCR[16] = PORT_PCR_MUX(3);
+ PORTB->PCR[17] = PORT_PCR_MUX(3);
+
+ // Enable receive interrupt
+ UART_INSTANCE->C2 |= UART_C2_RIE_MASK;
+ NVIC_ClearPendingIRQ(UART_IRQ);
+ NVIC_EnableIRQ(UART_IRQ);
+
+ return 1;
+}
+
+int32_t uart_uninitialize(void)
+{
+ // transmitter and receiver disabled
+ UART_INSTANCE->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);
+ // disable interrupt
+ UART_INSTANCE->C2 &= ~(UART_C2_RIE_MASK | UART_C2_TIE_MASK);
+ clear_buffers();
+ return 1;
+}
+
+int32_t uart_reset(void)
+{
+ // disable interrupt
+ NVIC_DisableIRQ(UART_IRQ);
+ // disable TIE interrupt
+ UART_INSTANCE->C2 &= ~(UART_C2_TIE_MASK);
+ clear_buffers();
+ // enable interrupt
+ NVIC_EnableIRQ(UART_IRQ);
+ return 1;
+}
+
+int32_t uart_set_configuration(UART_Configuration *config)
+{
+ uint8_t data_bits = 8;
+ uint8_t parity_enable = 0;
+ uint8_t parity_type = 0;
+ uint32_t dll;
+ // disable interrupt
+ NVIC_DisableIRQ(UART_IRQ);
+ UART_INSTANCE->C2 &= ~(UART_C2_RIE_MASK | UART_C2_TIE_MASK);
+ // Disable receiver and transmitter while updating
+ UART_INSTANCE->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);
+ clear_buffers();
+
+ // set data bits, stop bits, parity
+ if ((config->DataBits < 8) || (config->DataBits > 9)) {
+ data_bits = 8;
+ }
+
+ data_bits -= 8;
+
+ if (config->Parity == 1) {
+ parity_enable = 1;
+ parity_type = 1;
+ data_bits++;
+ } else if (config->Parity == 2) {
+ parity_enable = 1;
+ parity_type = 0;
+ data_bits++;
+ }
+
+ // does not support 10 bit data comm
+ if (data_bits == 2) {
+ data_bits = 0;
+ parity_enable = 0;
+ parity_type = 0;
+ }
+
+ // data bits, parity and parity mode
+ UART_INSTANCE->C1 = data_bits << UART_C1_M_SHIFT
+ | parity_enable << UART_C1_PE_SHIFT
+ | parity_type << UART_C1_PT_SHIFT;
+ dll = SystemCoreClock / (16 * config->Baudrate);
+ // set baudrate
+ UART_INSTANCE->BDH = (UART_INSTANCE->BDH & ~(UART_BDH_SBR_MASK)) | ((dll >> 8) & UART_BDH_SBR_MASK);
+ UART_INSTANCE->BDL = (UART_INSTANCE->BDL & ~(UART_BDL_SBR_MASK)) | (dll & UART_BDL_SBR_MASK);
+ // Enable transmitter and receiver
+ UART_INSTANCE->C2 |= UART_C2_RE_MASK | UART_C2_TE_MASK;
+ // Enable UART interrupt
+ NVIC_ClearPendingIRQ(UART_IRQ);
+ NVIC_EnableIRQ(UART_IRQ);
+ UART_INSTANCE->C2 |= UART_C2_RIE_MASK;
+ return 1;
+}
+
+int32_t uart_get_configuration(UART_Configuration *config)
+{
+ return 1;
+}
+
+int32_t uart_write_free(void)
+{
+ return circ_buf_count_free(&write_buffer);
+}
+
+int32_t uart_write_data(uint8_t *data, uint16_t size)
+{
+ cortex_int_state_t state;
+ uint32_t cnt;
+
+ cnt = circ_buf_write(&write_buffer, data, size);
+
+ // Atomically enable TX
+ state = cortex_int_get_and_disable();
+ if (circ_buf_count_used(&write_buffer)) {
+ UART_INSTANCE->C2 |= UART_C2_TIE_MASK;
+ }
+ cortex_int_restore(state);
+
+ return cnt;
+}
+
+int32_t uart_read_data(uint8_t *data, uint16_t size)
+{
+ return circ_buf_read(&read_buffer, data, size);
+}
+
+void UART0_RX_TX_IRQHandler(void)
+{
+ uint32_t s1;
+ volatile uint8_t errorData;
+ // read interrupt status
+ s1 = UART_INSTANCE->S1;
+ // mask off interrupts that are not enabled
+ if (!(UART_INSTANCE->C2 & UART_C2_RIE_MASK)) {
+ s1 &= ~UART_S1_RDRF_MASK;
+ }
+ if (!(UART_INSTANCE->C2 & UART_C2_TIE_MASK)) {
+ s1 &= ~UART_S1_TDRE_MASK;
+ }
+
+ // handle character to transmit
+ if (s1 & UART_S1_TDRE_MASK) {
+ // Assert that there is data in the buffer
+ util_assert(circ_buf_count_used(&write_buffer) > 0);
+
+ // Send out data
+ UART_INSTANCE->D = circ_buf_pop(&write_buffer);
+ // Turn off the transmitter if that was the last byte
+ if (circ_buf_count_used(&write_buffer) == 0) {
+ // disable TIE interrupt
+ UART_INSTANCE->C2 &= ~(UART_C2_TIE_MASK);
+ }
+ }
+
+ // handle received character
+ if (s1 & UART_S1_RDRF_MASK) {
+ if ((s1 & UART_S1_NF_MASK) || (s1 & UART_S1_FE_MASK)) {
+ errorData = UART_INSTANCE->D;
+ } else {
+ uint32_t free;
+ uint8_t data;
+
+ data = UART_INSTANCE->D;
+ free = circ_buf_count_free(&read_buffer);
+ if (free > RX_OVRF_MSG_SIZE) {
+ circ_buf_push(&read_buffer, data);
+ } else if ((RX_OVRF_MSG_SIZE == free) && config_get_overflow_detect()) {
+ circ_buf_write(&read_buffer, (uint8_t*)RX_OVRF_MSG, RX_OVRF_MSG_SIZE);
+ } else {
+ // Drop character
+ }
+ }
+ }
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/usb_buf.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/freescale/k26f/usb_buf.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,29 @@ +/** + * @file usb_buf.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef USB_BUF_H +#define USB_BUF_H + +#include "stdint.h" + +uint32_t usb_buffer[512 / 4]; + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/usb_config.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/freescale/k26f/usb_config.c Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,561 @@ +/** + * @file usb_config.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "util.h" + +//*** <<< Use Configuration Wizard in Context Menu >>> *** + +// **** +// NOTE: The high speed packet sizes are set to the same size as full speed in this +// USB configuration in order to increase the number of devices that can +// simultaneously be connected to a single USB controller. With the maximium +// high speed packet sizes, only 1 or 2 devices can be connected. +// **** + +// <e> USB Device +// <i> Enable the USB Device functionality +#define USBD_ENABLE 1 +#define USBD_RTX_CORE_STACK 0 +#define USBD_RTX_DEVICE_STACK 0 +#define USBD_RTX_ENDPOINT0_STACK 0 + +// <o0.0> High-speed +// <i> Enable high-speed functionality (if device supports it) +#define USBD_HS_ENABLE 1 +#if (defined(WEBUSB_INTERFACE) || defined(WINUSB_INTERFACE) || defined(BULK_ENDPOINT)) +#define USBD_BOS_ENABLE 1 +#else +#define USBD_BOS_ENABLE 0 +#endif +// <h> Device Settings +// <i> These settings affect Device Descriptor +// <o0> Power +// <i> Default Power Setting +// <0=> Bus-powered +// <1=> Self-powered +// <o1> Max Endpoint 0 Packet Size +// <i> Maximum packet size for endpoint zero (bMaxPacketSize0) +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes +// <o2.0..15> Vendor ID <0x0000-0xFFFF> +// <i> Vendor ID assigned by the USB-IF (idVendor) +// <o3.0..15> Product ID <0x0000-0xFFFF> +// <i> Product ID assigned by the manufacturer (idProduct) +// <o4.0..15> Device Release Number <0x0000-0xFFFF> +// <i> Device release number in binary-coded decimal (bcdDevice) +// </h> +#define USBD_POWER 0 +#define USBD_MAX_PACKET0 64 +#define USBD_DEVDESC_IDVENDOR 0x0D28 +#define USBD_DEVDESC_IDPRODUCT 0x0204 +#define USBD_DEVDESC_BCDDEVICE 0x1000 //was 0x0100 + +// <h> Configuration Settings +// <i> These settings affect Configuration Descriptor +// <o0.5> Remote Wakeup +// <i> Configuration support for remote wakeup (D5: of bmAttributes) +// <o1.0..7> Maximum Power Consumption (in mA) <0-510><#/2> +// <i> Maximum power consumption of the USB device +// <i> from the bus in this specific configuration +// <i> when the device is fully operational (bMaxPower) +// </h> +#define USBD_CFGDESC_BMATTRIBUTES 0x80 +#define USBD_CFGDESC_BMAXPOWER 0xFA + +// <h> String Settings +// <i> These settings affect String Descriptor +// <o0.0..15> Language ID <0x0000-0xFCFF> +// <i> English (United States) = 0x0409 +// <s0.126> Manufacturer String +// <i> String descriptor describing manufacturer +// <s1.126> Product String +// <i> String descriptor describing product +// <e1.0> Serial Number +// <i> Enable serial number string +// <i> If disabled serial number string will not be assigned to the USB Device +// <s2.126> Serial Number String +// <i> String descriptor describing device's serial number +// </e> +// </h> +#define USBD_STRDESC_LANGID 0x0409 +#define USBD_STRDESC_MAN L"ARM" +#ifndef USB_PROD_STR +#define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" +#else +#define _TOWIDE(x) L ## #x +#define TOWIDE(x) _TOWIDE(x) +#define USBD_STRDESC_PROD TOWIDE(USB_PROD_STR) +#endif +#define USBD_STRDESC_SER_ENABLE 1 +#define USBD_STRDESC_SER L"0001A0000000" + +// <e0> Class Support +// <i> Enables USB Device Class specific Requests +#define USBD_CLASS_ENABLE 1 + +// <e0.0> Human Interface Device (HID) +// <i> Enable class support for Human Interface Device (HID) +// <h> Interrupt Endpoint Settings +// <o1.0..4> Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o2.0..4> Interrupt Out Endpoint Number <0=> Not used <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <i> If interrupt out endpoint is not used select "Not used" +// <h> Endpoint Settings +// <o3.0..7> Maximum Endpoint Packet Size (in bytes) <0-64> +// <o4.0..7> Endpoint polling Interval (in ms) <1-255> +// <e5> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o6.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o6.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// <o7.0..7> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// </e> +// </h> +// </h> +// <h> Human Interface Device Settings +// <i> Device specific settings +// <s0.126> HID Interface String +// <o8.0..4> Number of Input Reports <1-32> +// <o9.0..4> Number of Output Reports <1-32> +// <o10.0..15> Maximum Input Report Size (in bytes) <1-65535> +// <o11.0..15> Maximum Output Report Size (in bytes) <1-65535> +// <o12.0..15> Maximum Feature Report Size (in bytes) <1-65535> +// </h> +// </e> +#ifndef HID_ENDPOINT +#define HID_ENDPOINT 0 +#else +#define HID_ENDPOINT 1 +#endif + +#ifndef WEBUSB_INTERFACE +#define WEBUSB_INTERFACE 0 +#else +#define WEBUSB_INTERFACE 1 +#endif + +#define USBD_HID_ENABLE HID_ENDPOINT +#define USBD_HID_EP_INTIN 1 +#define USBD_HID_EP_INTOUT 1 + +#define USBD_HID_EP_INTIN_STACK 0 +#define USBD_HID_WMAXPACKETSIZE 64 +#define USBD_HID_BINTERVAL 1 +#define USBD_HID_HS_ENABLE 1 +#define USBD_HID_HS_WMAXPACKETSIZE 64 //| (2<<11) +#define USBD_HID_HS_BINTERVAL 1 +#define USBD_HID_STRDESC L"CMSIS-DAP v1" +#define USBD_WEBUSB_STRDESC L"WebUSB: CMSIS-DAP" +#define USBD_HID_INREPORT_NUM 1 +#define USBD_HID_OUTREPORT_NUM 1 +#define USBD_HID_INREPORT_MAX_SZ 64 +#define USBD_HID_OUTREPORT_MAX_SZ 64 +#define USBD_HID_FEATREPORT_MAX_SZ 1 + +// <e0.0> Mass Storage Device (MSC) +// <i> Enable class support for Mass Storage Device (MSC) +// <h> Bulk Endpoint Settings +// <o1.0..4> Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o2.0..4> Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o3> Maximum Packet Size <1-1024> +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5> Maximum Packet Size <1-1024> +// <o6> Maximum NAK Rate <0-255> +// </e> +// </h> +// </h> +// <h> Mass Storage Device Settings +// <i> Device specific settings +// <s0.126> MSC Interface String +// <h> Inquiry Data +// <s1.8> Vendor Identification +// <s2.16> Product Identification +// <s3.4> Product Revision Level +// </h> +// </h> +// </e> +#ifndef MSC_ENDPOINT +#define MSC_ENDPOINT 0 +#else +#define MSC_ENDPOINT 1 +#endif +#define USBD_MSC_ENABLE MSC_ENDPOINT +#define USBD_MSC_EP_BULKIN 2 +#define USBD_MSC_EP_BULKOUT 2 +#define USBD_MSC_EP_BULKIN_STACK 0 +#define USBD_MSC_WMAXPACKETSIZE 64 +#define USBD_MSC_HS_ENABLE 1 +#define USBD_MSC_HS_WMAXPACKETSIZE 512 +#define USBD_MSC_HS_BINTERVAL 0 +#define USBD_MSC_STRDESC L"USB_MSC" +// Make sure changes to USBD_MSC_INQUIRY_DATA are coordinated with mbed-ls +// since this is used to detect DAPLink drives +#define USBD_MSC_INQUIRY_DATA "MBED " \ + "VFS " \ + "0.1" + +// <e0.0> Audio Device (ADC) +// <i> Enable class support for Audio Device (ADC) +// <h> Isochronous Endpoint Settings +// <o1.0..4> Isochronous Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o2.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o3.0..10> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o5.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// </e> +// </h> +// </h> +// <h> Audio Device Settings +// <i> Device specific settings +// <s0.126> Audio Control Interface String +// <s1.126> Audio Streaming (Zero Bandwidth) Interface String +// <s2.126> Audio Streaming (Operational) Interface String +// <o6.0..7> Audio Subframe Size (in bytes) <0-255> +// <o7.0..7> Sample Resolution (in bits) <0-255> +// <o8.0..23> Sample Frequency (in Hz) <0-16777215> +// <o9> Packet Size (in bytes) <1-256> +// <o10> Packet Count <1-16> +// </h> +// </e> +#define USBD_ADC_ENABLE 0 +#define USBD_ADC_EP_ISOOUT 3 +#define USBD_ADC_WMAXPACKETSIZE 64 +#define USBD_ADC_BINTERVAL 1 +#define USBD_ADC_HS_ENABLE 0 +#define USBD_ADC_HS_WMAXPACKETSIZE 64 +#define USBD_ADC_CIF_STRDESC L"USB_ADC" +#define USBD_ADC_SIF1_STRDESC L"USB_ADC1" +#define USBD_ADC_SIF2_STRDESC L"USB_ADC2" +#define USBD_ADC_BSUBFRAMESIZE 2 +#define USBD_ADC_BBITRESOLUTION 16 +#define USBD_ADC_TSAMFREQ 32000 +#define USBD_ADC_CFG_P_S 32 +#define USBD_ADC_CFG_P_C 1 + +// <e0> Communication Device (CDC) - Abstract Control Model (ACM) +// <i> Enable class support for Communication Device (CDC) - Abstract Control Model (ACM) +// <h> Interrupt Endpoint Settings +// <o1.0..4> Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o2.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o3.0..10> Endpoint polling Interval (in ms) <0-255> +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o5.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// <o6.0..10> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// </e4> +// </h> +// </h> +// <h> Bulk Endpoint Settings +// <o7.0..4> Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o8.0..4> Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o9> Maximum Packet Size <1-1024> +// <e10> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o11> Maximum Packet Size <1-1024> +// <o12> Maximum NAK Rate <0-255> +// </e10> +// </h> +// </h> +// <h> Communication Device Settings +// <i> Device specific settings +// <s0.126> Communication Class Interface String +// <s1.126> Data Class Interface String +// <o13> Maximum Communication Device Send Buffer Size +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// <o14> Maximum Communication Device Receive Buffer Size +// <i> Minimum size must be as big as maximum packet size for Bulk Out Endpoint +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// </h> +// </e> + +#ifndef CDC_ENDPOINT +#define CDC_ENDPOINT 0 +#else +#define CDC_ENDPOINT 1 +#endif +#define USBD_CDC_ACM_ENABLE CDC_ENDPOINT +#define USBD_CDC_ACM_EP_INTIN 3 +#define USBD_CDC_ACM_EP_INTIN_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE 16 +#define USBD_CDC_ACM_BINTERVAL 32 +#define USBD_CDC_ACM_HS_ENABLE 1 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE 64 +#define USBD_CDC_ACM_HS_BINTERVAL 2 +#define USBD_CDC_ACM_EP_BULKIN 4 +#define USBD_CDC_ACM_EP_BULKOUT 4 +#define USBD_CDC_ACM_EP_BULKIN_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE1 64 +#define USBD_CDC_ACM_HS_ENABLE1 1 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE1 512 +#define USBD_CDC_ACM_HS_BINTERVAL1 1 +#define USBD_CDC_ACM_CIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_DIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_SENDBUF_SIZE USBD_CDC_ACM_HS_WMAXPACKETSIZE1 +#define USBD_CDC_ACM_RECEIVEBUF_SIZE USBD_CDC_ACM_HS_WMAXPACKETSIZE1 +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Send Buffer size must be larger or equal to Bulk In maximum packet size!" +#endif +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Receive Buffer size must be larger or equal to Bulk Out maximum packet size!" +#endif + +// <e0> Custom Class Device +// <i> Enables USB Custom Class Requests +// <i> Class IDs: +// <i> 0x00 - Class Reserved ID +// <i> 0x01 - Class Audio ID +// <i> 0x02 - Class Communications ID +// <i> 0x03 - Class Human Interface ID +// <i> 0x04 - Class Monitor ID +// <i> 0x05 - Class Physical Interface ID +// <i> 0x06 - Class Power ID +// <i> 0x07 - Class Printer ID +// <i> 0x08 - Class Storage ID +// <i> 0x09 - Class HUB ID +// <i> 0xEF - Class Miscellaneous ID +// <i> 0xFF - Class Vendor Specific ID +// </e> +#define USBD_CLS_ENABLE 0 + +// WebUSB support +#define USBD_WEBUSB_ENABLE WEBUSB_INTERFACE +#define USBD_WEBUSB_VENDOR_CODE 0x21 +#define USBD_WEBUSB_LANDING_URL "os.mbed.com/webusb/landing-page/?bid=" +#define USBD_WEBUSB_ORIGIN_URL "os.mbed.com/" + +// Microsoft OS Descriptors 2.0 (WinUSB) support +#define USBD_WINUSB_ENABLE WINUSB_INTERFACE +#define USBD_WINUSB_VENDOR_CODE 0x20 +// </e> +// </e> + +#ifndef BULK_ENDPOINT +#define BULK_ENDPOINT 0 +#else +#define BULK_ENDPOINT 1 +#endif +#define USBD_BULK_ENABLE BULK_ENDPOINT +#define USBD_BULK_EP_BULKIN 5 +#define USBD_BULK_EP_BULKOUT 5 +#define USBD_BULK_WMAXPACKETSIZE 64 +#define USBD_BULK_HS_ENABLE 1 +#define USBD_BULK_HS_WMAXPACKETSIZE 512 +#define USBD_BULK_STRDESC L"CMSIS-DAP v2" + + +/* USB Device Calculations ---------------------------------------------------*/ + +#define USBD_IF_NUM_MAX (USBD_BULK_ENABLE+USBD_WEBUSB_ENABLE+USBD_HID_ENABLE+USBD_MSC_ENABLE+(USBD_ADC_ENABLE*2)+(USBD_CDC_ACM_ENABLE*2)+USBD_CLS_ENABLE) +#define USBD_MULTI_IF (USBD_CDC_ACM_ENABLE*(USBD_HID_ENABLE|USBD_MSC_ENABLE|USBD_ADC_ENABLE|USBD_CLS_ENABLE|USBD_WEBUSB_ENABLE|USBD_BULK_ENABLE)) +// #define MAX(x, y) (((x) < (y)) ? (y) : (x)) +#define USBD_EP_NUM_CALC0 MAX((USBD_HID_ENABLE *(USBD_HID_EP_INTIN )), (USBD_HID_ENABLE *(USBD_HID_EP_INTOUT!=0)*(USBD_HID_EP_INTOUT))) +#define USBD_EP_NUM_CALC1 MAX((USBD_MSC_ENABLE *(USBD_MSC_EP_BULKIN )), (USBD_MSC_ENABLE *(USBD_MSC_EP_BULKOUT))) +#define USBD_EP_NUM_CALC2 MAX((USBD_ADC_ENABLE *(USBD_ADC_EP_ISOOUT )), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_INTIN))) +#define USBD_EP_NUM_CALC3 MAX((USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKIN)), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKOUT))) +#define USBD_EP_NUM_CALC4 MAX(USBD_EP_NUM_CALC0, USBD_EP_NUM_CALC1) +#define USBD_EP_NUM_CALC5 MAX(USBD_EP_NUM_CALC2, USBD_EP_NUM_CALC3) +#define USBD_EP_NUM_CALC6 MAX(USBD_EP_NUM_CALC4, USBD_EP_NUM_CALC5) +#define USBD_EP_NUM_CALC7 MAX((USBD_BULK_ENABLE*(USBD_BULK_EP_BULKIN)), (USBD_BULK_ENABLE*(USBD_BULK_EP_BULKOUT))) +#define USBD_EP_NUM MAX(USBD_EP_NUM_CALC6, USBD_EP_NUM_CALC7) + +#if (USBD_HID_ENABLE) +#if (USBD_MSC_ENABLE) +#if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_MSC_EP_BULKOUT))) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKOUT))) +#error "HID and Mass Storage Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_ADC_ENABLE) +#if ((USBD_HID_EP_INTIN == USBD_ADC_EP_ISOOUT) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_ADC_EP_ISOOUT))) +#error "HID and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (((USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKOUT))|| \ + ((USBD_HID_EP_INTOUT != 0) && \ + ((USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKOUT)))) +#error "HID and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_MSC_ENABLE) +#if (USBD_ADC_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_ADC_EP_ISOOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_ADC_EP_ISOOUT)) +#error "Mass Storage Device and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Mass Storage Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_ADC_ENABLE) +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Audio Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#define USBD_ADC_CIF_NUM (0) +#define USBD_ADC_SIF1_NUM (1) +#define USBD_ADC_SIF2_NUM (2) + +#define USBD_ADC_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+0) +#define USBD_ADC_SIF1_STR_NUM (3+USBD_STRDESC_SER_ENABLE+1) +#define USBD_ADC_SIF2_STR_NUM (3+USBD_STRDESC_SER_ENABLE+2) +#define USBD_CDC_ACM_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+0) +#define USBD_CDC_ACM_DIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+1) +#define USBD_HID_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2) +#define USBD_WEBUSB_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) +#define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) +#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) + +#if (USBD_HID_ENABLE) +#if (USBD_HID_HS_ENABLE) +#define USBD_HID_MAX_PACKET ((USBD_HID_HS_WMAXPACKETSIZE > USBD_HID_WMAXPACKETSIZE) ? USBD_HID_HS_WMAXPACKETSIZE : USBD_HID_WMAXPACKETSIZE) +#else +#define USBD_HID_MAX_PACKET (USBD_HID_WMAXPACKETSIZE) +#endif +#else +#define USBD_HID_MAX_PACKET (0) +#endif +#if (USBD_MSC_ENABLE) +#if (USBD_MSC_HS_ENABLE) +#define USBD_MSC_MAX_PACKET ((USBD_MSC_HS_WMAXPACKETSIZE > USBD_MSC_WMAXPACKETSIZE) ? USBD_MSC_HS_WMAXPACKETSIZE : USBD_MSC_WMAXPACKETSIZE) +#else +#define USBD_MSC_MAX_PACKET (USBD_MSC_WMAXPACKETSIZE) +#endif +#else +#define USBD_MSC_MAX_PACKET (0) +#endif +#if (USBD_ADC_ENABLE) +#if (USBD_ADC_HS_ENABLE) +#define USBD_ADC_MAX_PACKET ((USBD_ADC_HS_WMAXPACKETSIZE > USBD_ADC_WMAXPACKETSIZE) ? USBD_ADC_HS_WMAXPACKETSIZE : USBD_ADC_WMAXPACKETSIZE) +#else +#define USBD_ADC_MAX_PACKET (USBD_ADC_WMAXPACKETSIZE) +#endif +#else +#define USBD_ADC_MAX_PACKET (0) +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (USBD_CDC_ACM_HS_ENABLE) +#define USBD_CDC_ACM_MAX_PACKET ((USBD_CDC_ACM_HS_WMAXPACKETSIZE > USBD_CDC_ACM_WMAXPACKETSIZE) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE : USBD_CDC_ACM_WMAXPACKETSIZE) +#else +#define USBD_CDC_ACM_MAX_PACKET (USBD_CDC_ACM_WMAXPACKETSIZE) +#endif +#if (USBD_CDC_ACM_HS_ENABLE1) +#define USBD_CDC_ACM_MAX_PACKET1 ((USBD_CDC_ACM_HS_WMAXPACKETSIZE1 > USBD_CDC_ACM_WMAXPACKETSIZE1) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE1 : USBD_CDC_ACM_WMAXPACKETSIZE1) +#else +#define USBD_CDC_ACM_MAX_PACKET1 (USBD_CDC_ACM_WMAXPACKETSIZE1) +#endif +#else +#define USBD_CDC_ACM_MAX_PACKET (0) +#define USBD_CDC_ACM_MAX_PACKET1 (0) +#endif +#if (USBD_BULK_ENABLE) +#if (USBD_BULK_HS_ENABLE) +#define USBD_BULK_MAX_PACKET ((USBD_BULK_HS_WMAXPACKETSIZE > USBD_BULK_WMAXPACKETSIZE) ? USBD_BULK_HS_WMAXPACKETSIZE : USBD_BULK_WMAXPACKETSIZE) +#else +#define USBD_BULK_MAX_PACKET (USBD_BULK_WMAXPACKETSIZE) +#endif +#else +#define USBD_BULK_MAX_PACKET (0) +#endif +#define USBD_MAX_PACKET_CALC0 ((USBD_HID_MAX_PACKET > USBD_HID_MAX_PACKET ) ? (USBD_HID_MAX_PACKET ) : (USBD_HID_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC1 ((USBD_ADC_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET ) ? (USBD_ADC_MAX_PACKET ) : (USBD_CDC_ACM_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC2 ((USBD_MAX_PACKET_CALC0 > USBD_MAX_PACKET_CALC1 ) ? (USBD_MAX_PACKET_CALC0) : (USBD_MAX_PACKET_CALC1 )) +#define USBD_MAX_PACKET_CALC3 ((USBD_BULK_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET1 ) ? (USBD_BULK_MAX_PACKET) : (USBD_CDC_ACM_MAX_PACKET1 )) +#define USBD_MAX_PACKET ((USBD_MAX_PACKET_CALC3 > USBD_MAX_PACKET_CALC2 ) ? (USBD_MAX_PACKET_CALC3) : (USBD_MAX_PACKET_CALC2 )) + + +/*------------------------------------------------------------------------------ + * USB Config Functions + *----------------------------------------------------------------------------*/ + +#ifndef __USB_CONFIG___ +#define __USB_CONFIG__ + +#ifndef __NO_USB_LIB_C +#include "usb_lib.c" +#endif + +#endif /* __USB_CONFIG__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/usb_phy.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/usb_phy.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_usb.h"
+#include "fsl_device_registers.h"
+
+/*!
+ * @brief ehci phy initialization.
+ *
+ * This function initialize ehci phy IP.
+ *
+ * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
+ * @param[in] freq the external input clock.
+ * for example: if the external input clock is 16M, the parameter freq should be 16000000.
+ *
+ * @retval kStatus_USB_Success cancel successfully.
+ * @retval kStatus_USB_Error the freq value is incorrect.
+ */
+uint32_t USB_EhciPhyInit(uint8_t controllerId, uint32_t freq)
+{
+#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
+ USBPHY->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */
+ USBPHY->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */
+ USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_POWER_MASK; /* power up PLL */
+ if (freq == 24000000U)
+ {
+ USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_DIV_SEL(0U);
+ }
+ else if (freq == 16000000U)
+ {
+ USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_DIV_SEL(1U);
+ }
+ else if (freq == 12000000U)
+ {
+ USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_DIV_SEL(2U);
+ }
+ else
+ {
+ return kStatus_USB_Error; /* error */
+ }
+ USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_BYPASS_MASK; /* clear bypass bit */
+ USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* enable USB clock output from USB PHY PLL */
+ USBPHY->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; /* Clear to 0U to run clocks */
+
+ USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */
+ USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */
+ /* PWD register provides overall control of the PHY power state */
+ USBPHY->PWD = 0U;
+
+ while (!(USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK))
+ {
+ }
+
+ /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */
+ USBPHY->TX = ((USBPHY->TX & (~USBPHY_TX_D_CAL_MASK)) | USBPHY_TX_D_CAL(0xcU));
+#endif
+
+ return kStatus_USB_Success;
+}
+
+/*!
+ * @brief ehci phy initialization for suspend and resume.
+ *
+ * This function initialize ehci phy IP for suspend and resume.
+ *
+ * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
+ * @param[in] freq the external input clock.
+ * for example: if the external input clock is 16M, the parameter freq should be 16000000.
+ *
+ * @retval kStatus_USB_Success cancel successfully.
+ * @retval kStatus_USB_Error the freq value is incorrect.
+ */
+uint32_t USB_EhciLowPowerPhyInit(uint8_t controllerId, uint32_t freq)
+{
+#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
+ USBPHY->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */
+ USBPHY->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */
+ USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_POWER_MASK; /* power up PLL */
+ if (freq == 24000000U)
+ {
+ USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_DIV_SEL(0U);
+ }
+ else if (freq == 16000000U)
+ {
+ USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_DIV_SEL(1U);
+ }
+ else if (freq == 12000000U)
+ {
+ USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_DIV_SEL(2U);
+ }
+ else
+ {
+ return kStatus_USB_Error; /* error */
+ }
+ USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_BYPASS_MASK; /* clear bypass bit */
+ USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* enable USB clock output from USB PHY PLL */
+ USBPHY->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; /* Clear to 0U to run clocks */
+ USBPHY->CTRL |=
+ USBPHY_CTRL_AUTORESUME_EN_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK;
+ USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */
+ USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */
+ /* PWD register provides overall control of the PHY power state */
+ USBPHY->PWD = 0U;
+
+ while (!(USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK))
+ {
+ }
+
+ /* now the 480MHz USB clock is up, then configure fractional divider after PLL with PFD
+ * pfd clock = 480MHz*18/N, where N=18~35
+ * Please note that USB1PFDCLK has to be less than 180MHz for RUN or HSRUN mode
+ */
+ USBPHY->ANACTRL |= USBPHY_ANACTRL_PFD_FRAC(24); /* N=24 */
+ USBPHY->ANACTRL |= USBPHY_ANACTRL_PFD_CLK_SEL(4); /* div by 4 */
+
+ USBPHY->ANACTRL &= ~USBPHY_ANACTRL_DEV_PULLDOWN_MASK;
+ USBPHY->ANACTRL &= ~USBPHY_ANACTRL_PFD_CLKGATE_MASK;
+ while (!(USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_STABLE_MASK))
+ {
+ }
+
+ /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */
+ USBPHY->TX = ((USBPHY->TX & (~USBPHY_TX_D_CAL_MASK)) | USBPHY_TX_D_CAL(0xcU));
+#endif
+
+ return kStatus_USB_Success;
+}
+
+/*!
+ * @brief ehci phy de-initialization.
+ *
+ * This function de-initialize ehci phy IP.
+ *
+ * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
+ */
+void USB_EhciPhyDeinit(uint8_t controllerId)
+{
+#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
+ USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_POWER_MASK; /* power down PLL */
+ USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* disable USB clock output from USB PHY PLL */
+ USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* set to 1U to gate clocks */
+#endif
+}
+
+/*!
+ * @brief ehci phy disconnect detection enable or disable.
+ *
+ * This function enable/disable host ehci disconnect detection.
+ *
+ * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
+ * @param[in] enable
+ * 1U - enable;
+ * 0U - disable;
+ */
+void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable)
+{
+#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
+ if (enable)
+ {
+ USBPHY->CTRL |= USBPHY_CTRL_ENHOSTDISCONDETECT_MASK;
+ }
+ else
+ {
+ USBPHY->CTRL &= (~USBPHY_CTRL_ENHOSTDISCONDETECT_MASK);
+ }
+#endif
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/usb_phy.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/freescale/k26f/usb_phy.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __USB_PHY_H__ +#define __USB_PHY_H__ + +/*! + * @brief EHCI PHY initialization. + * + * This function initializes the EHCI PHY IP. + * + * @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t. + * @param[in] freq The external input clock. + * + * @retval kStatus_USB_Success Cancel successfully. + * @retval kStatus_USB_Error The freq value is incorrect. + */ +extern uint32_t USB_EhciPhyInit(uint8_t controllerId, uint32_t freq); + +/*! + * @brief ehci phy initialization for suspend and resume. + * + * This function initialize ehci phy IP for suspend and resume. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + * @param[in] freq the external input clock. + * for example: if the external input clock is 16M, the parameter freq should be 16000000. + * + * @retval kStatus_USB_Success cancel successfully. + * @retval kStatus_USB_Error the freq value is incorrect. + */ +extern uint32_t USB_EhciLowPowerPhyInit(uint8_t controllerId, uint32_t freq); + +/*! + * @brief EHCI PHY deinitialization. + * + * This function deinitializes the EHCI PHY IP. + * + * @param[in] controllerId EHCI controller ID; See #usb_controller_index_t. + */ +extern void USB_EhciPhyDeinit(uint8_t controllerId); + +/*! + * @brief EHCI PHY disconnect detection enable or disable. + * + * This function enable/disable the host EHCI disconnect detection. + * + * @param[in] controllerId EHCI controller ID; See #usb_controller_index_t. + * @param[in] enable + * 1U - enable; + * 0U - disable; + */ +extern void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable); + +#endif /* __USB_PHY_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/k26f/usbd_MK26F.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/k26f/usbd_MK26F.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,892 @@
+/**
+ * @file usbd_LPC43xx_USBD0.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "rl_usb.h"
+#include "usb.h"
+#include "fsl_device_registers.h"
+#include "hic_init.h"
+
+#define __NO_USB_LIB_C
+#include "usb_config.c"
+
+/* Endpoint queue head */
+typedef struct __EPQH {
+ uint32_t cap;
+ uint32_t curr_dTD;
+ uint32_t next_dTD;
+ uint32_t dTD_token;
+ uint32_t buf[5];
+ uint32_t reserved;
+ uint32_t setup[2];
+ uint32_t reserved1[4];
+} EPQH;
+
+/* Endpoint transfer descriptor */
+typedef struct __dTD {
+ uint32_t next_dTD;
+ uint32_t dTD_token;
+ uint32_t buf[5];
+ uint32_t reserved;
+} dTD;
+
+/* Endpoint */
+typedef struct __EP {
+ uint8_t *buf;
+ uint32_t maxPacket;
+} EP;
+
+EPQH __align(2048) EPQHx[(USBD_EP_NUM + 1) * 2];
+dTD __align(32) dTDx[(USBD_EP_NUM + 1) * 2];
+
+EP Ep[(USBD_EP_NUM + 1) * 2];
+uint32_t BufUsed;
+uint32_t IsoEp;
+uint32_t cmpl_pnd;
+
+#define ENDPTCTRL(EPNum) *(volatile uint32_t *)((uint32_t)(&USBHS->EPCR0) + 4 * EPNum)
+#define EP_OUT_IDX(EPNum) (EPNum * 2 )
+#define EP_IN_IDX(EPNum) (EPNum * 2 + 1)
+#define HS(en) (USBD_HS_ENABLE * en)
+
+/* reserve RAM for endpoint buffers */
+#if USBD_VENDOR_ENABLE
+/* custom class: user defined buffer size */
+#define EP_BUF_POOL_SIZE 0x1000
+uint8_t __align(4096) EPBufPool[EP_BUF_POOL_SIZE]
+#else
+/* supported classes are used */
+uint8_t __align(4096) EPBufPool[
+ USBD_MAX_PACKET0 * 2 +
+ USBD_HID_ENABLE * (HS(USBD_HID_HS_ENABLE) ? USBD_HID_HS_WMAXPACKETSIZE : USBD_HID_WMAXPACKETSIZE) * 2 +
+ USBD_MSC_ENABLE * (HS(USBD_MSC_HS_ENABLE) ? USBD_MSC_HS_WMAXPACKETSIZE : USBD_MSC_WMAXPACKETSIZE) * 2 +
+ USBD_ADC_ENABLE * (HS(USBD_ADC_HS_ENABLE) ? USBD_ADC_HS_WMAXPACKETSIZE : USBD_ADC_WMAXPACKETSIZE) +
+ USBD_CDC_ACM_ENABLE * ((HS(USBD_CDC_ACM_HS_ENABLE) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE : USBD_CDC_ACM_WMAXPACKETSIZE) +
+ (HS(USBD_CDC_ACM_HS_ENABLE) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE1 : USBD_CDC_ACM_WMAXPACKETSIZE1) * 2) +
+ USBD_BULK_ENABLE * (HS(USBD_BULK_HS_ENABLE) ? USBD_BULK_HS_WMAXPACKETSIZE : USBD_BULK_WMAXPACKETSIZE) * 2
+];
+#endif
+
+void USBD_PrimeEp(uint32_t EPNum, uint32_t cnt);
+
+/*
+ * Usb interrupt enable/disable
+ * Parameters: ena: enable/disable
+ * 0: disable interrupt
+ * 1: enable interrupt
+ */
+
+#ifdef __RTX
+void __svc(1) USBD_Intr(int ena);
+void __SVC_1(int ena)
+{
+#else
+void USBD_Intr(int ena)
+{
+#endif
+
+ if (ena) {
+ NVIC_EnableIRQ(USBHS_IRQn); /* Enable USB interrupt */
+ } else {
+ NVIC_DisableIRQ(USBHS_IRQn); /* Disable USB interrupt */
+ }
+}
+
+
+/*
+ * USB Device Initialize Function
+ * Called by the User to initialize USB Device
+ * Return Value: None
+ */
+
+void USBD_Init(void)
+{
+ USBD_Intr(0);
+
+ hic_enable_usb_clocks();
+
+ USBHS->USBCMD |= (1UL << 1); /* usb reset */
+
+ while (USBHS->USBCMD & (1UL << 1));
+
+ USBHS->USBMODE = 2 | (1UL << 3);/* device mode */
+#if USBD_HS_ENABLE
+ USBHS->PORTSC1 &= ~(1UL << 24);
+#else
+ USBHS->PORTSC1 |= (1UL << 24);
+#endif
+ USBHS->OTGSC = 1 | (1UL << 3);
+ Ep[EP_OUT_IDX(0)].maxPacket = USBD_MAX_PACKET0;
+ USBHS->USBINTR = (1UL << 0) | /* usb int enable */
+ (1UL << 2) | /* port change detect int enable */
+ (1UL << 8) | /* suspend int enable */
+ (1UL << 16) | /* nak int enable */
+ (1UL << 6) | /* reset int enable */
+#ifdef __RTX
+ ((USBD_RTX_DevTask != 0) ? (1UL << 7) : 0) | /* SOF */
+ ((USBD_RTX_DevTask != 0) ? (1UL << 1) : 0) ; /* Error */
+#else
+ ((USBD_P_SOF_Event != 0) ? (1UL << 7) : 0) | /* SOF */
+ ((USBD_P_Error_Event != 0) ? (1UL << 1) : 0) ; /* Error */
+#endif
+ USBD_Reset();
+ USBD_Intr(1);
+}
+
+
+/*
+ * USB Device Connect Function
+ * Called by the User to Connect/Disconnect USB Device
+ * Parameters: con: Connect/Disconnect
+ * Return Value: None
+ */
+
+void USBD_Connect(uint32_t con)
+{
+ if (con) {
+ USBHS->USBCMD |= 1; /* run */
+ } else {
+ USBHS->USBCMD &= ~1; /* stop */
+ }
+}
+
+
+/*
+ * USB Device Reset Function
+ * Called automatically on USB Device Reset
+ * Return Value: None
+ */
+
+void USBD_Reset(void)
+{
+ uint32_t i;
+ uint8_t *ptr;
+ cmpl_pnd = 0;
+
+ for (i = 1; i < USBD_EP_NUM + 1; i++) {
+ ENDPTCTRL(i) &= ~((1UL << 7) | (1UL << 23));
+ }
+
+ /* clear interrupts */
+ USBHS->ENDPTNAK = 0xFFFFFFFF;
+ USBHS->ENDPTNAKEN = 0;
+ USBHS->USBSTS = 0xFFFFFFFF;
+ USBHS->EPSETUPSR = USBHS->EPSETUPSR;
+ USBHS->EPCOMPLETE = USBHS->EPCOMPLETE;
+
+ while (USBHS->EPPRIME);
+
+ USBHS->EPFLUSH = 0xFFFFFFFF;
+
+ while (USBHS->EPFLUSH);
+
+ USBHS->USBCMD &= ~0x00FF0000; /* immediate intrrupt treshold */
+ /* clear endpoint queue heads */
+ ptr = (uint8_t *)EPQHx;
+
+ for (i = 0; i < sizeof(EPQHx); i++) {
+ ptr[i] = 0;
+ }
+
+ /* clear endpoint transfer descriptors */
+ ptr = (uint8_t *)dTDx;
+
+ for (i = 0; i < sizeof(dTDx); i++) {
+ ptr[i] = 0;
+ }
+
+ Ep[EP_OUT_IDX(0)].maxPacket = USBD_MAX_PACKET0;
+ Ep[EP_OUT_IDX(0)].buf = EPBufPool;
+ BufUsed = USBD_MAX_PACKET0;
+ Ep[EP_IN_IDX(0)].maxPacket = USBD_MAX_PACKET0;
+ Ep[EP_IN_IDX(0)].buf = &(EPBufPool[BufUsed]);
+ BufUsed += USBD_MAX_PACKET0;
+ dTDx[EP_OUT_IDX(0)].next_dTD = 1;
+ dTDx[EP_IN_IDX(0)].next_dTD = 1;
+ dTDx[EP_OUT_IDX(0)].dTD_token = (USBD_MAX_PACKET0 << 16) | /* total bytes */
+ (1UL << 15); /* int on compl */
+ dTDx[EP_IN_IDX(0)].dTD_token = (USBD_MAX_PACKET0 << 16) | /* total bytes */
+ (1UL << 15); /* int on compl */
+ EPQHx[EP_OUT_IDX(0)].next_dTD = (uint32_t) &dTDx[EP_OUT_IDX(0)];
+ EPQHx[EP_IN_IDX(0)].next_dTD = (uint32_t) &dTDx[EP_IN_IDX(0)];
+ EPQHx[EP_OUT_IDX(0)].cap = ((USBD_MAX_PACKET0 & 0x0EFF) << 16) |
+ (1UL << 29) |
+ (1UL << 15); /* int on setup */
+ EPQHx[EP_IN_IDX(0)].cap = (USBD_MAX_PACKET0 << 16) |
+ (1UL << 29) |
+ (1UL << 15); /* int on setup */
+ USBHS->EPLISTADDR = (uint32_t)EPQHx;
+ USBHS->USBMODE |= (1UL << 3); /* Setup lockouts off */
+ USBHS->EPCR0 = 0x00C000C0;
+ USBD_PrimeEp(0, Ep[EP_OUT_IDX(0)].maxPacket);
+}
+
+
+/*
+ * USB Device Suspend Function
+ * Called automatically on USB Device Suspend
+ * Return Value: None
+ */
+
+void USBD_Suspend(void)
+{
+ /* Performed by Hardware */
+}
+
+
+/*
+ * USB Device Resume Function
+ * Called automatically on USB Device Resume
+ * Return Value: None
+ */
+
+void USBD_Resume(void)
+{
+ /* Performed by Hardware */
+}
+
+
+/*
+ * USB Device Remote Wakeup Function
+ * Called automatically on USB Device Remote Wakeup
+ * Return Value: None
+ */
+
+void USBD_WakeUp(void)
+{
+ USBHS->PORTSC1 |= (1UL << 6);
+}
+
+
+/*
+ * USB Device Remote Wakeup Configuration Function
+ * Parameters: cfg: Device Enable/Disable
+ * Return Value: None
+ */
+
+void USBD_WakeUpCfg(uint32_t cfg)
+{
+ /* Not needed */
+}
+
+
+/*
+ * USB Device Set Address Function
+ * Parameters: adr: USB Device Address
+ * Return Value: None
+ */
+
+void USBD_SetAddress(uint32_t adr, uint32_t setup)
+{
+ if (setup == 0) {
+ USBHS->DEVICEADDR = (adr << 25);
+ USBHS->DEVICEADDR |= (1UL << 24);
+ }
+}
+
+
+/*
+ * USB Device Configure Function
+ * Parameters: cfg: Device Configure/Deconfigure
+ * Return Value: None
+ */
+
+void USBD_Configure(uint32_t cfg)
+{
+ uint32_t i;
+
+ if (!cfg) {
+ for (i = 2; i < (2 * (USBD_EP_NUM + 1)); i++) {
+ Ep[i].buf = 0;
+ Ep[i].maxPacket = 0;
+ }
+
+ BufUsed = 2 * USBD_MAX_PACKET0;
+ }
+}
+
+
+/*
+ * Configure USB Device Endpoint according to Descriptor
+ * Parameters: pEPD: Pointer to Device Endpoint Descriptor
+ * Return Value: None
+ */
+
+void USBD_ConfigEP(USB_ENDPOINT_DESCRIPTOR *pEPD)
+{
+ uint32_t num, val, type, idx;
+
+ if ((pEPD->bEndpointAddress & USB_ENDPOINT_DIRECTION_MASK)) {
+ val = 16;
+ num = pEPD->bEndpointAddress & ~0x80;
+ idx = EP_IN_IDX(num);
+
+ } else {
+ val = 0;
+ num = pEPD->bEndpointAddress;
+ idx = EP_OUT_IDX(num);
+ }
+
+ type = pEPD->bmAttributes & USB_ENDPOINT_TYPE_MASK;
+
+ if (!(Ep[idx].buf)) {
+ Ep[idx].buf = &(EPBufPool[BufUsed]);
+ Ep[idx].maxPacket = pEPD->wMaxPacketSize;
+ BufUsed += pEPD->wMaxPacketSize;
+
+ /* Isochronous endpoint */
+ if (type == USB_ENDPOINT_TYPE_ISOCHRONOUS) {
+ IsoEp |= (1UL << (num + val));
+ }
+ }
+
+ dTDx[idx].buf[0] = (uint32_t)(Ep[idx].buf);
+ dTDx[idx].next_dTD = 1;
+ EPQHx[idx].cap = (Ep[idx].maxPacket << 16) |
+ (1UL << 29);
+ ENDPTCTRL(num) &= ~(0xFFFF << val);
+ ENDPTCTRL(num) |= ((type << 2) << val) |
+ ((1UL << 6) << val); /* Data toogle reset */
+}
+
+
+/*
+ * Set Direction for USB Device Control Endpoint
+ * Parameters: dir: Out (dir == 0), In (dir <> 0)
+ * Return Value: None
+ */
+
+void USBD_DirCtrlEP(uint32_t dir)
+{
+ /* Not needed */
+}
+
+
+/*
+ * Enable USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_EnableEP(uint32_t EPNum)
+{
+ if (EPNum & 0x80) {
+ EPNum &= 0x7F;
+ ENDPTCTRL(EPNum) |= (1UL << 23); /* EP enabled */
+ } else {
+ ENDPTCTRL(EPNum) |= (1UL << 7); /* EP enabled */
+ }
+}
+
+
+/*
+ * Disable USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_DisableEP(uint32_t EPNum)
+{
+ if (EPNum & 0x80) {
+ EPNum &= 0x7F;
+ ENDPTCTRL(EPNum) &= ~(1UL << 23); /* EP disabled */
+ } else {
+ ENDPTCTRL(EPNum) &= ~(1UL << 7); /* EP disabled */
+ }
+}
+
+
+/*
+ * Reset USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_ResetEP(uint32_t EPNum)
+{
+ if (EPNum & 0x80) {
+ EPNum &= 0x7F;
+ EPQHx[EP_IN_IDX(EPNum)].dTD_token &= 0xC0;
+ USBHS->EPFLUSH = (1UL << (EPNum + 16)); /* flush endpoint */
+
+ while (USBHS->EPFLUSH & (1UL << (EPNum + 16)));
+
+ ENDPTCTRL(EPNum) |= (1UL << 22); /* data toggle reset */
+
+ } else {
+ EPQHx[EP_OUT_IDX(EPNum)].dTD_token &= 0xC0;
+ USBHS->EPFLUSH = (1UL << EPNum); /* flush endpoint */
+
+ while (USBHS->EPFLUSH & (1UL << EPNum));
+
+ ENDPTCTRL(EPNum) |= (1UL << 6); /* data toggle reset */
+ USBD_PrimeEp(EPNum, Ep[EP_OUT_IDX(EPNum)].maxPacket);
+ }
+}
+
+
+/*
+ * Set Stall for USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_SetStallEP(uint32_t EPNum)
+{
+ if (EPNum & 0x80) {
+ EPNum &= 0x7F;
+ ENDPTCTRL(EPNum) |= (1UL << 16); /* IN endpoint stall */
+ } else {
+ ENDPTCTRL(EPNum) |= (1UL << 0); /* OUT endpoint stall */
+ }
+}
+
+
+/*
+ * Clear Stall for USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_ClrStallEP(uint32_t EPNum)
+{
+ if (EPNum & 0x80) {
+ EPNum &= 0x7F;
+ ENDPTCTRL(EPNum) &= ~(1UL << 16); /* clear stall */
+ ENDPTCTRL(EPNum) |= (1UL << 22); /* data toggle reset */
+
+ while (ENDPTCTRL(EPNum) & (1UL << 16));
+
+ USBD_ResetEP(EPNum | 0x80);
+
+ } else {
+ ENDPTCTRL(EPNum) &= ~(1UL << 0); /* clear stall */
+ ENDPTCTRL(EPNum) |= (1UL << 6); /* data toggle reset */
+ }
+}
+
+
+/*
+ * Clear USB Device Endpoint Buffer
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_ClearEPBuf(uint32_t EPNum)
+{
+}
+
+
+/*
+ * USB Device Prime endpoint function
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * cnt: Bytes to transfer/receive
+ * Return Value: None
+ */
+
+void USBD_PrimeEp(uint32_t EPNum, uint32_t cnt)
+{
+ uint32_t idx, val;
+
+ /* IN endpoint */
+ if (EPNum & 0x80) {
+ EPNum &= 0x7F;
+ idx = EP_IN_IDX(EPNum);
+ val = (1UL << (EPNum + 16));
+ }
+
+ /* OUT endpoint */
+ else {
+ val = (1UL << EPNum);
+ idx = EP_OUT_IDX(EPNum);
+ }
+
+ dTDx[idx].buf[0] = (uint32_t)(Ep[idx].buf);
+ dTDx[idx].next_dTD = 1;
+
+ if (IsoEp & val) {
+ if (Ep[idx].maxPacket <= cnt) {
+ dTDx[idx].dTD_token = (1 << 10); /* MultO = 1 */
+
+ } else if ((Ep[idx].maxPacket * 2) <= cnt) {
+ dTDx[idx].dTD_token = (2 << 10); /* MultO = 2 */
+
+ } else {
+ dTDx[idx].dTD_token = (3 << 10); /* MultO = 3 */
+ }
+
+ } else {
+ dTDx[idx].dTD_token = 0;
+ }
+
+ dTDx[idx].dTD_token |= (cnt << 16) | /* bytes to transfer */
+ (1UL << 15) | /* int on complete */
+ 0x80; /* status - active */
+ EPQHx[idx].next_dTD = (uint32_t)(&dTDx[idx]);
+ EPQHx[idx].dTD_token &= ~0xC0;
+ USBHS->EPPRIME = (val);
+
+ while ((USBHS->EPPRIME & val));
+}
+
+
+/*
+ * Read USB Device Endpoint Data
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * pData: Pointer to Data Buffer
+ * Return Value: Number of bytes read
+ */
+
+uint32_t USBD_ReadEP(uint32_t EPNum, uint8_t *pData, uint32_t size)
+{
+ uint32_t cnt = 0;
+ uint32_t i;
+
+ /* Setup packet */
+ if ((USBHS->EPSETUPSR & 1) && (!EPNum)) {
+ USBHS->EPSETUPSR = 1;
+
+ while (USBHS->EPSETUPSR & 1);
+
+ do {
+ *((__packed uint32_t *) pData) = EPQHx[EP_OUT_IDX(0)].setup[0];
+ *((__packed uint32_t *)(pData + 4)) = EPQHx[EP_OUT_IDX(0)].setup[1];
+ cnt = 8;
+ USBHS->USBCMD |= (1UL << 13);
+ } while (!(USBHS->USBCMD & (1UL << 13)));
+
+ USBHS->USBCMD &= (~(1UL << 13));
+ USBHS->EPFLUSH = (1UL << EPNum) | (1UL << (EPNum + 16));
+
+ while (USBHS->EPFLUSH & ((1UL << (EPNum + 16)) | (1UL << EPNum)));
+
+ while (USBHS->EPSETUPSR & 1);
+
+ USBD_PrimeEp(EPNum, Ep[EP_OUT_IDX(EPNum)].maxPacket);
+ }
+
+ /* OUT Packet */
+ else {
+ if (Ep[EP_OUT_IDX(EPNum)].buf) {
+ cnt = Ep[EP_OUT_IDX(EPNum)].maxPacket -
+ ((dTDx[EP_OUT_IDX(EPNum)].dTD_token >> 16) & 0x7FFF);
+
+ for (i = 0; i < cnt; i++) {
+ pData[i] = Ep[EP_OUT_IDX(EPNum)].buf[i];
+ }
+ }
+
+ USBHS->EPCOMPLETE = (1UL << EPNum);
+ cmpl_pnd &= ~(1UL << EPNum);
+ USBD_PrimeEp(EPNum, Ep[EP_OUT_IDX(EPNum)].maxPacket);
+ }
+
+ return (cnt);
+}
+
+
+/*
+ * Write USB Device Endpoint Data
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * pData: Pointer to Data Buffer
+ * cnt: Number of bytes to write
+ * Return Value: Number of bytes written
+ */
+
+uint32_t USBD_WriteEP(uint32_t EPNum, uint8_t *pData, uint32_t cnt)
+{
+ uint32_t i;
+ EPNum &= 0x7f;
+
+ for (i = 0; i < cnt; i++) {
+ Ep[EP_IN_IDX(EPNum)].buf[i] = pData[i];
+ }
+
+ USBD_PrimeEp(EPNum | 0x80, cnt);
+ return (cnt);
+}
+
+
+/*
+ * Get USB Device Last Frame Number
+ * Parameters: None
+ * Return Value: Frame Number
+ */
+
+uint32_t USBD_GetFrame(void)
+{
+ return ((USBHS->FRINDEX >> 3) & 0x0FFF);
+}
+
+
+#ifdef __RTX
+uint32_t LastError; /* Last Error */
+
+/*
+ * Get USB Device Last Error Code
+ * Parameters: None
+ * Return Value: Error Code
+ */
+
+uint32_t USBD_GetError(void)
+{
+ return (LastError);
+}
+#endif
+
+
+/*
+ * USB Device Interrupt Service Routine
+ */
+void USBHS_IRQHandler(void)
+{
+ NVIC_DisableIRQ(USBHS_IRQn);
+ USBD_SignalHandler();
+}
+
+/*
+ * USB Device Interrupt Service Routine
+ */
+
+void USBD_Handler(void)
+{
+ uint32_t sts, cmpl, num;
+ sts = USBHS->USBSTS & USBHS->USBINTR;
+ cmpl = USBHS->EPCOMPLETE;
+ USBHS->USBSTS = sts; /* clear interupt flags */
+
+ /* reset interrupt */
+ if (sts & (1UL << 6)) {
+ USBD_Reset();
+ usbd_reset_core();
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_RESET, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Reset_Event) {
+ USBD_P_Reset_Event();
+ }
+
+#endif
+ }
+
+ /* suspend interrupt */
+ if (sts & (1UL << 8)) {
+ USBD_Suspend();
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_SUSPEND, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Suspend_Event) {
+ USBD_P_Suspend_Event();
+ }
+
+#endif
+ }
+
+ /* SOF interrupt */
+ if (sts & (1UL << 7)) {
+ if (IsoEp) {
+ for (num = 0; num < USBD_EP_NUM + 1; num++) {
+ if (IsoEp & (1UL << num)) {
+ USBD_PrimeEp(num, Ep[EP_OUT_IDX(num)].maxPacket);
+ }
+ }
+
+ } else {
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_SOF, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_SOF_Event) {
+ USBD_P_SOF_Event();
+ }
+
+#endif
+ }
+ }
+
+ /* port change detect interrupt */
+ if (sts & (1UL << 2)) {
+ if (((USBHS->PORTSC1 >> 26) & 0x03) == 2) {
+ USBD_HighSpeed = __TRUE;
+ }
+
+ USBD_Resume();
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_RESUME, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Resume_Event) {
+ USBD_P_Resume_Event();
+ }
+
+#endif
+ }
+
+ /* USB interrupt - completed transfer */
+ if (sts & 1) {
+ /* Setup Packet */
+ if (USBHS->EPSETUPSR) {
+#ifdef __RTX
+
+ if (USBD_RTX_EPTask[0]) {
+ isr_evt_set(USBD_EVT_SETUP, USBD_RTX_EPTask[0]);
+ }
+
+#else
+
+ if (USBD_P_EP[0]) {
+ USBD_P_EP[0](USBD_EVT_SETUP);
+ }
+
+#endif
+ }
+
+ /* IN Packet */
+ if (cmpl & (0x3F << 16)) {
+ for (num = 0; num < USBD_EP_NUM + 1; num++) {
+ if (((cmpl >> 16) & 0x3F) & (1UL << num)) {
+ USBHS->EPCOMPLETE = (1UL << (num + 16)); /* Clear completed */
+#ifdef __RTX
+
+ if (USBD_RTX_EPTask[num]) {
+ isr_evt_set(USBD_EVT_IN, USBD_RTX_EPTask[num]);
+ }
+
+#else
+
+ if (USBD_P_EP[num]) {
+ USBD_P_EP[num](USBD_EVT_IN);
+ }
+
+#endif
+ }
+ }
+ }
+
+ /* OUT Packet */
+ if (cmpl & 0x3F) {
+ for (num = 0; num < USBD_EP_NUM + 1; num++) {
+ if ((cmpl ^ cmpl_pnd) & cmpl & (1UL << num)) {
+ cmpl_pnd |= 1UL << num;
+#ifdef __RTX
+
+ if (USBD_RTX_EPTask[num]) {
+ isr_evt_set(USBD_EVT_OUT, USBD_RTX_EPTask[num]);
+
+ } else if (IsoEp & (1UL << num)) {
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_SOF, USBD_RTX_DevTask);
+ }
+ }
+
+#else
+
+ if (USBD_P_EP[num]) {
+ USBD_P_EP[num](USBD_EVT_OUT);
+
+ } else if (IsoEp & (1UL << num)) {
+ if (USBD_P_SOF_Event) {
+ USBD_P_SOF_Event();
+ }
+ }
+
+#endif
+ }
+ }
+ }
+ }
+
+ /* error interrupt */
+ if (sts & (1UL << 1)) {
+ for (num = 0; num < USBD_EP_NUM + 1; num++) {
+ if (cmpl & (1UL << num)) {
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ LastError = dTDx[EP_OUT_IDX(num)].dTD_token & 0xE8;
+ isr_evt_set(USBD_EVT_ERROR, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Error_Event) {
+ USBD_P_Error_Event(dTDx[EP_OUT_IDX(num)].dTD_token & 0xE8);
+ }
+
+#endif
+ }
+
+ if (cmpl & (1UL << (num + 16))) {
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ LastError = dTDx[EP_IN_IDX(num)].dTD_token & 0xE8;
+ isr_evt_set(USBD_EVT_ERROR, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Error_Event) {
+ USBD_P_Error_Event(dTDx[EP_IN_IDX(num)].dTD_token & 0xE8);
+ }
+
+#endif
+ }
+ }
+ }
+
+ NVIC_EnableIRQ(USBHS_IRQn);
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/kl26z/DAP_config.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/kl26z/DAP_config.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,475 @@
+/**
+ * @file DAP_config.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef __DAP_CONFIG_H__
+#define __DAP_CONFIG_H__
+
+#include "IO_Config.h"
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
+\ingroup DAP_ConfigIO_gr
+@{
+Provides definitions about:
+ - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
+ - Debug Unit communication packet size.
+ - Debug Access Port communication mode (JTAG or SWD).
+ - Optional information about a connected Target Device (for Evaluation Boards).
+*/
+
+/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
+/// This value is used to calculate the SWD/JTAG clock speed.
+#define CPU_CLOCK SystemCoreClock ///< Specifies the CPU Clock in Hz
+
+/// Number of processor cycles for I/O Port write operations.
+/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
+/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
+/// requrie 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
+/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
+/// requrired.
+#define IO_PORT_WRITE_CYCLES 1 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
+
+/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available
+
+/// Indicate that JTAG communication mode is available at the Debug Port.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available.
+
+/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
+/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
+#define DAP_JTAG_DEV_CNT 0 ///< Maximum number of JTAG devices on scan chain
+
+/// Default communication mode on the Debug Access Port.
+/// Used for the command \ref DAP_Connect when Port Default mode is selected.
+#define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
+
+/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
+/// Used to initialize the default SWD/JTAG clock frequency.
+/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
+#define DAP_DEFAULT_SWJ_CLOCK 5000000 ///< Default SWD/JTAG clock frequency in Hz.
+
+/// Maximum Package Size for Command and Response data.
+/// This configuration settings is used to optimized the communication performance with the
+/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
+#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed.
+
+/// Maximum Package Buffers for Command and Response data.
+/// This configuration settings is used to optimized the communication performance with the
+/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
+/// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
+#define DAP_PACKET_COUNT 5 ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
+
+/// Indicate that UART Serial Wire Output (SWO) trace is available.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available
+
+/// Maximum SWO UART Baudrate
+#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz
+
+/// Indicate that Manchester Serial Wire Output (SWO) trace is available.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available
+
+/// SWO Trace Buffer Size.
+#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n)
+
+/// SWO Streaming Trace.
+#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available.
+
+/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
+#define TIMESTAMP_CLOCK 0U ///< Timestamp clock in Hz (0 = timestamps not supported).
+
+
+/// Debug Unit is connected to fixed Target Device.
+/// The Debug Unit may be part of an evaluation board and always connected to a fixed
+/// known device. In this case a Device Vendor and Device Name string is stored which
+/// may be used by the debugger or IDE to configure device parameters.
+#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
+
+#if TARGET_DEVICE_FIXED
+#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor
+#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device
+#endif
+
+///@}
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
+\ingroup DAP_ConfigIO_gr
+@{
+
+Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
+and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
+interface of a device. The following I/O Pins are provided:
+
+JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
+---------------------------- | -------------------- | ---------------------------------------------
+TCK: Test Clock | SWCLK: Clock | Output Push/Pull
+TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
+TDI: Test Data Input | | Output Push/Pull
+TDO: Test Data Output | | Input
+nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
+nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
+
+
+DAP Hardware I/O Pin Access Functions
+-------------------------------------
+The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
+these I/O Pins.
+
+For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
+This functions are provided to achieve faster I/O that is possible with some advanced GPIO
+peripherals that can independently write/read a single I/O pin without affecting any other pins
+of the same I/O port. The following SWDIO I/O Pin functions are provided:
+ - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
+ - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
+ - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
+ - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
+*/
+
+
+// Configure DAP I/O pins ------------------------------
+
+/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
+Configures the DAP Hardware I/O pins for JTAG mode:
+ - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
+ - TDO to input mode.
+*/
+__STATIC_INLINE void PORT_JTAG_SETUP(void) {}
+
+/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
+Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
+ - SWCLK, SWDIO, nRESET to output mode and set to default high level.
+ - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
+*/
+__STATIC_INLINE void PORT_SWD_SETUP(void)
+{
+ PIN_SWCLK_GPIO->PSOR = PIN_SWCLK;
+ PIN_SWDIO_GPIO->PSOR = PIN_SWDIO;
+ PIN_nRESET_GPIO->PSOR = PIN_nRESET;
+ PIN_SWCLK_GPIO->PDDR |= (PIN_SWCLK);
+ PIN_SWDIO_GPIO->PDDR |= (PIN_SWDIO);
+ PIN_nRESET_GPIO->PDDR |= (PIN_nRESET);
+}
+
+/** Disable JTAG/SWD I/O Pins.
+Disables the DAP Hardware I/O pins which configures:
+ - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
+*/
+__STATIC_INLINE void PORT_OFF(void)
+{
+ PIN_SWCLK_GPIO->PDDR &= ~(PIN_SWCLK);
+ PIN_SWDIO_GPIO->PDDR &= ~(PIN_SWDIO);
+ PIN_nRESET_GPIO->PDDR &= ~(PIN_nRESET);
+}
+
+
+// SWCLK/TCK I/O pin -------------------------------------
+
+/** SWCLK/TCK I/O pin: Get Input.
+\return Current status of the SWCLK/TCK DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void)
+{
+ return (PIN_SWCLK_GPIO->PDIR & PIN_SWCLK) ? 1 : 0;
+}
+
+/** SWCLK/TCK I/O pin: Set Output to High.
+Set the SWCLK/TCK DAP hardware I/O pin to high level.
+*/
+__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET(void)
+{
+ PIN_SWCLK_GPIO->PSOR = PIN_SWCLK;
+}
+
+/** SWCLK/TCK I/O pin: Set Output to Low.
+Set the SWCLK/TCK DAP hardware I/O pin to low level.
+*/
+__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void)
+{
+ PIN_SWCLK_GPIO->PCOR = PIN_SWCLK;
+}
+
+
+// SWDIO/TMS Pin I/O --------------------------------------
+
+/** SWDIO/TMS I/O pin: Get Input.
+\return Current status of the SWDIO/TMS DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void)
+{
+ return (PIN_SWDIO_GPIO->PDIR & PIN_SWDIO) ? 1 : 0;
+}
+
+/** SWDIO/TMS I/O pin: Set Output to High.
+Set the SWDIO/TMS DAP hardware I/O pin to high level.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET(void)
+{
+ PIN_SWDIO_GPIO->PSOR = PIN_SWDIO;
+}
+
+/** SWDIO/TMS I/O pin: Set Output to Low.
+Set the SWDIO/TMS DAP hardware I/O pin to low level.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void)
+{
+ PIN_SWDIO_GPIO->PCOR = PIN_SWDIO;
+}
+
+/** SWDIO I/O pin: Get Input (used in SWD mode only).
+\return Current status of the SWDIO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
+{
+ return (PIN_SWDIO_GPIO->PDIR & PIN_SWDIO) ? 1 : 0;
+}
+
+/** SWDIO I/O pin: Set Output (used in SWD mode only).
+\param bit Output value for the SWDIO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT(uint32_t bit)
+{
+ if (bit & 0x1) {
+ PIN_SWDIO_GPIO->PSOR = PIN_SWDIO;
+ } else {
+ PIN_SWDIO_GPIO->PCOR = PIN_SWDIO;
+ }
+}
+
+/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
+Configure the SWDIO DAP hardware I/O pin to output mode. This function is
+called prior \ref PIN_SWDIO_OUT function calls.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void)
+{
+ PIN_SWDIO_GPIO->PDDR |= PIN_SWDIO;
+}
+
+/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
+Configure the SWDIO DAP hardware I/O pin to input mode. This function is
+called prior \ref PIN_SWDIO_IN function calls.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void)
+{
+ PIN_SWDIO_GPIO->PDDR &= ~(PIN_SWDIO);
+}
+
+
+// TDI Pin I/O ---------------------------------------------
+
+/** TDI I/O pin: Get Input.
+\return Current status of the TDI DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void)
+{
+ return (0); // Not available
+}
+
+/** TDI I/O pin: Set Output.
+\param bit Output value for the TDI DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE void PIN_TDI_OUT(uint32_t bit)
+{
+ ; // Not available
+}
+
+
+// TDO Pin I/O ---------------------------------------------
+
+/** TDO I/O pin: Get Input.
+\return Current status of the TDO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void)
+{
+ return (0); // Not available
+}
+
+
+// nTRST Pin I/O -------------------------------------------
+
+/** nTRST I/O pin: Get Input.
+\return Current status of the nTRST DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void)
+{
+ return (0); // Not available
+}
+
+/** nTRST I/O pin: Set Output.
+\param bit JTAG TRST Test Reset pin status:
+ - 0: issue a JTAG TRST Test Reset.
+ - 1: release JTAG TRST Test Reset.
+*/
+__STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit)
+{
+ ; // Not available
+}
+
+// nRESET Pin I/O------------------------------------------
+
+/** nRESET I/O pin: Get Input.
+\return Current status of the nRESET DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void)
+{
+ return (PIN_nRESET_GPIO->PDIR & PIN_nRESET) ? 1 : 0;
+}
+
+/** nRESET I/O pin: Set Output.
+\param bit target device hardware reset pin status:
+ - 0: issue a device hardware reset.
+ - 1: release device hardware reset.
+*/
+__STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit)
+{
+ if (bit & 0x1) {
+ PIN_nRESET_GPIO->PSOR = PIN_nRESET;
+ } else {
+ PIN_nRESET_GPIO->PCOR = PIN_nRESET;
+ }
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
+\ingroup DAP_ConfigIO_gr
+@{
+
+CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
+
+It is recommended to provide the following LEDs for status indication:
+ - Connect LED: is active when the DAP hardware is connected to a debugger.
+ - Running LED: is active when the debugger has put the target device into running state.
+*/
+
+/** Debug Unit: Set status of Connected LED.
+\param bit status of the Connect LED.
+ - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
+ - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
+*/
+__STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit)
+{
+ ; // Not available
+}
+
+/** Debug Unit: Set status Target Running LED.
+\param bit status of the Target Running LED.
+ - 1: Target Running LED ON: program execution in target started.
+ - 0: Target Running LED OFF: program execution in target stopped.
+*/
+__STATIC_INLINE void LED_RUNNING_OUT(uint32_t bit)
+{
+ ; // Not available
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
+\ingroup DAP_ConfigIO_gr
+@{
+Access function for Test Domain Timer.
+
+The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
+default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
+
+*/
+
+/** Get timestamp of Test Domain Timer.
+\return Current timestamp value.
+*/
+__STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
+ return 0;
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
+\ingroup DAP_ConfigIO_gr
+@{
+
+CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
+*/
+
+/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
+This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
+Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
+ - I/O clock system enabled.
+ - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
+ - for nTRST, nRESET a weak pull-up (if available) is enabled.
+ - LED output pins are enabled and LEDs are turned off.
+*/
+__STATIC_INLINE void DAP_SETUP(void)
+{
+ SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK | /* Enable Port A Clock */
+ SIM_SCGC5_PORTB_MASK | /* Enable Port B Clock */
+ SIM_SCGC5_PORTC_MASK | /* Enable Port C Clock */
+ SIM_SCGC5_PORTD_MASK | /* Enable Port D Clock */
+ SIM_SCGC5_PORTE_MASK; /* Enable Port E Clock */
+ /* Configure I/O pin SWCLK */
+ PIN_SWCLK_PORT->PCR[PIN_SWCLK_BIT] = PORT_PCR_MUX(1) | /* GPIO */
+ PORT_PCR_PE_MASK; /* Pull (Down) enable */
+ PIN_SWCLK_GPIO->PSOR = PIN_SWCLK; /* High level */
+ PIN_SWCLK_GPIO->PDDR |= PIN_SWCLK; /* Output */
+ /* Configure I/O pin SWDIO */
+ PIN_SWDIO_PORT->PCR[PIN_SWDIO_BIT] = PORT_PCR_MUX(1) | /* GPIO */
+ PORT_PCR_PE_MASK | /* Pull enable */
+ PORT_PCR_PS_MASK; /* Pull-up */
+ PIN_SWDIO_GPIO->PSOR = PIN_SWDIO; /* High level */
+ PIN_SWDIO_GPIO->PDDR &= ~(PIN_SWDIO); /* Input */
+ /* Configure I/O pin nRESET */
+ PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_MUX(1) | /* GPIO */
+ PORT_PCR_PE_MASK | /* Pull enable */
+ PORT_PCR_PS_MASK; /* Pull-up */
+ PIN_nRESET_GPIO->PSOR = PIN_nRESET; /* High level */
+ PIN_nRESET_GPIO->PDDR |= PIN_nRESET; /* Output */
+}
+
+/** Reset Target Device with custom specific I/O pin or command sequence.
+This function allows the optional implementation of a device specific reset sequence.
+It is called when the command \ref DAP_ResetTarget and is for example required
+when a device needs a time-critical unlock sequence that enables the debug port.
+\return 0 = no device specific reset sequence is implemented.\n
+ 1 = a device specific reset sequence is implemented.
+*/
+__STATIC_INLINE uint32_t RESET_TARGET(void)
+{
+ return (0); // change to '1' when a device reset sequence is implemented
+}
+
+///@}
+
+
+#endif /* __DAP_CONFIG_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/kl26z/IO_Config.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/freescale/kl26z/IO_Config.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,127 @@ +/** + * @file IO_Config.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +// Override all defines if IO_CONFIG_OVERRIDE is defined +#ifdef IO_CONFIG_OVERRIDE +#include "IO_Config_Override.h" +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ +#endif +#endif + +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ + +#include "MKL26Z4.h" +#include "compiler.h" +#include "daplink.h" + +// This GPIO configuration is only valid for the KL26 HIC +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_KL26); + + +// Debug Port I/O Pins + +// SWCLK Pin PTC5(C5) +#define PIN_SWCLK_PORT PORTC +#define PIN_SWCLK_GPIO PTC +#define PIN_SWCLK_BIT (5) +#define PIN_SWCLK (1<<PIN_SWCLK_BIT) + +// SWDIO Pin PTC6(C6) +#define PIN_SWDIO_PORT PORTC +#define PIN_SWDIO_GPIO PTC +#define PIN_SWDIO_BIT (6) +#define PIN_SWDIO (1<<PIN_SWDIO_BIT) + +// nRESET Pin PTC8(C8) +#define PIN_nRESET_PORT PORTC +#define PIN_nRESET_GPIO PTC +#define PIN_nRESET_BIT (8) +#define PIN_nRESET (1<<PIN_nRESET_BIT) + +// PWR_REG_EN PTD2 - Not connected +#define PIN_POWER_EN_PORT PORTD +#define PIN_POWER_EN_GPIO PTD +#define PIN_POWER_EN_BIT (2) +#define PIN_POWER_EN (1<<PIN_POWER_EN_BIT) + +// VTRG_FAULT_B PTD3 - Not connected +#define PIN_VTRG_FAULT_B_PORT PORTD +#define PIN_VTRG_FAULT_B_GPIO PTD +#define PIN_VTRG_FAULT_B_BIT (7) +#define PIN_VTRG_FAULT_B_EN (1<<PIN_VTRG_FAULT_B_BIT) + +// Debug Unit LEDs + +// HID_LED PTD4 +#define PIN_HID_LED_PORT PORTD +#define PIN_HID_LED_GPIO PTD +#define PIN_HID_LED_BIT (4) +#define PIN_HID_LED (1<<PIN_HID_LED_BIT) + +// MSC_LED PTD5 +#define PIN_MSC_LED_PORT PORTD +#define PIN_MSC_LED_GPIO PTD +#define PIN_MSC_LED_BIT (4) +#define PIN_MSC_LED (1<<PIN_MSC_LED_BIT) + +// CDC_LED PTD6 +#define PIN_CDC_LED_PORT PORTD +#define PIN_CDC_LED_GPIO PTD +#define PIN_CDC_LED_BIT (4) +#define PIN_CDC_LED (1<<PIN_CDC_LED_BIT) + +// SW RESET BUTTON PTB1 +#define PIN_SW_RESET_PORT PORTB +#define PIN_SW_RESET_GPIO PTB +#define PIN_SW_RESET_BIT (1) +#define PIN_SW_RESET (1<<PIN_SW_RESET_BIT) + +// BOARD TYPE +#define PIN_BOARD_TYPE_PORT PORTB +#define PIN_BOARD_TYPE_GPIO PTB +#define PIN_BOARD_TYPE_BIT (0) +#define PIN_BOARD_TYPE (1<<PIN_BOARD_TYPE_BIT) + +// Connected LED Not available + +// Target Running LED Not available + +// UART +#define UART_PORT PORTC +#define UART_NUM (1) +// RX PTC3 +#define PIN_UART_RX_GPIO PTC +#define PIN_UART_RX_BIT (3) +#define PIN_UART_RX (1<<PIN_UART_RX_BIT) +#define PIN_UART_RX_MUX_ALT (3) +// TX PTC4 +#define PIN_UART_TX_GPIO PTC +#define PIN_UART_TX_BIT (4) +#define PIN_UART_TX (1<<PIN_UART_TX_BIT) +#define PIN_UART_TX_MUX_ALT (3) + +#define UART UART1 +#define UART_RX_TX_IRQn UART1_IRQn +#define UART_RX_TX_IRQHandler UART1_IRQHandler + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/kl26z/MKL26Z4/MKL26Z4.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/kl26z/MKL26Z4/MKL26Z4.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,5910 @@
+/*
+** ###################################################################
+** Processors: MKL26Z128CAL4
+** MKL26Z128VFM4
+** MKL26Z128VFT4
+** MKL26Z128VLH4
+** MKL26Z128VLL4
+** MKL26Z128VMC4
+** MKL26Z256VLH4
+** MKL26Z256VLL4
+** MKL26Z256VMC4
+** MKL26Z256VMP4
+** MKL26Z32VFM4
+** MKL26Z32VFT4
+** MKL26Z32VLH4
+** MKL26Z64VFM4
+** MKL26Z64VFT4
+** MKL26Z64VLH4
+**
+** Compilers: Keil ARM C/C++ Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manuals: KL26P121M48SF4RM Rev. 3.2, October 2013
+** KL26P121M48SF4RM, Rev.2, Dec 2012
+**
+** Version: rev. 1.8, 2015-07-29
+** Build: b160126
+**
+** Abstract:
+** CMSIS Peripheral Access Layer for MKL26Z4
+**
+** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2012-12-12)
+** Initial version.
+** - rev. 1.1 (2013-04-05)
+** Changed start of doxygen comment.
+** - rev. 1.2 (2013-04-12)
+** SystemInit function fixed for clock configuration 1.
+** Name of the interrupt num. 31 updated to reflect proper function.
+** - rev. 1.3 (2014-05-27)
+** Updated to Kinetis SDK support standard.
+** MCG OSC clock select supported (MCG_C7[OSCSEL]).
+** - rev. 1.4 (2014-07-25)
+** System initialization updated:
+** - Prefix added to the system initialization parameterization constants to avoid name conflicts..
+** - VLLSx wake-up recovery added.
+** - Delay of 1 ms added to SystemInit() to ensure stable FLL output in FEI and FEE MCG modes.
+** - rev. 1.5 (2014-08-28)
+** Update of system files - default clock configuration changed, fix of OSC initialization.
+** Update of startup files - possibility to override DefaultISR added.
+** - rev. 1.6 (2014-10-14)
+** Renamed interrupt vector LPTimer to LPTMR0
+** - rev. 1.7 (2015-02-18)
+** Renamed interrupt vector LLW to LLWU
+** - rev. 1.8 (2015-07-29)
+** Correction of backward compatibility.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL26Z4.h
+ * @version 1.8
+ * @date 2015-07-29
+ * @brief CMSIS Peripheral Access Layer for MKL26Z4
+ *
+ * CMSIS Peripheral Access Layer for MKL26Z4
+ */
+
+#ifndef _MKL26Z4_H_
+#define _MKL26Z4_H_ /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0008U
+
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+ /* Auxiliary constants */
+ NotAvail_IRQn = -128, /**< Not available device specific interrupt */
+
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ DMA0_IRQn = 0, /**< DMA channel 0 transfer complete and error interrupt */
+ DMA1_IRQn = 1, /**< DMA channel 1 transfer complete and error interrupt */
+ DMA2_IRQn = 2, /**< DMA channel 2 transfer complete and error interrupt */
+ DMA3_IRQn = 3, /**< DMA channel 3 transfer complete and error interrupt */
+ Reserved20_IRQn = 4, /**< Reserved interrupt */
+ FTFA_IRQn = 5, /**< FTFA command complete and read collision */
+ LVD_LVW_IRQn = 6, /**< Low-voltage detect, low-voltage warning */
+ LLWU_IRQn = 7, /**< Low Leakage Wakeup */
+ I2C0_IRQn = 8, /**< I2C0 interrupt */
+ I2C1_IRQn = 9, /**< I2C1 interrupt */
+ SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */
+ SPI1_IRQn = 11, /**< SPI1 single interrupt vector for all sources */
+ UART0_IRQn = 12, /**< UART0 status and error */
+ UART1_IRQn = 13, /**< UART1 status and error */
+ UART2_IRQn = 14, /**< UART2 status and error */
+ ADC0_IRQn = 15, /**< ADC0 interrupt */
+ CMP0_IRQn = 16, /**< CMP0 interrupt */
+ TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */
+ TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */
+ TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */
+ RTC_IRQn = 20, /**< RTC alarm interrupt */
+ RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */
+ PIT_IRQn = 22, /**< PIT single interrupt vector for all channels */
+ I2S0_IRQn = 23, /**< I2S0 Single interrupt vector for all sources */
+ USB0_IRQn = 24, /**< USB0 OTG */
+ DAC0_IRQn = 25, /**< DAC0 interrupt */
+ TSI0_IRQn = 26, /**< TSI0 interrupt */
+ MCG_IRQn = 27, /**< MCG interrupt */
+ LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */
+ Reserved45_IRQn = 29, /**< Reserved interrupt */
+ PORTA_IRQn = 30, /**< PORTA pin detect */
+ PORTC_PORTD_IRQn = 31 /**< Single interrupt vector for PORTC and PORTD pin detect */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M0 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
+ * @{
+ */
+
+#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
+#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
+#define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */
+#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+
+#include "core_cm0plus.h" /* Core Peripheral Access Layer */
+#include "system_MKL26Z4.h" /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Mapping Information
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup edma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according to the to SoC.
+ */
+typedef enum _dma_request_source
+{
+ kDmaRequestMux0Disable = 0|0x100U, /**< Disable */
+ kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */
+ kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 receive complete */
+ kDmaRequestMux0LPSCI0Rx = 2|0x100U, /**< UART0 receive complete */
+ kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 transmit complete */
+ kDmaRequestMux0LPSCI0Tx = 3|0x100U, /**< UART0 transmit complete */
+ kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 receive complete */
+ kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 transmit complete */
+ kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 receive complete */
+ kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 transmit complete */
+ kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */
+ kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */
+ kDmaRequestMux0Reserved10 = 10|0x100U, /**< Reserved10 */
+ kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */
+ kDmaRequestMux0Reserved12 = 12|0x100U, /**< Reserved12 */
+ kDmaRequestMux0Reserved13 = 13|0x100U, /**< Reserved13 */
+ kDmaRequestMux0I2S0Rx = 14|0x100U, /**< I2S0 receive complete */
+ kDmaRequestMux0I2S0Tx = 15|0x100U, /**< I2S0 transmit complete */
+ kDmaRequestMux0SPI0Rx = 16|0x100U, /**< SPI0 receive complete */
+ kDmaRequestMux0SPI0Tx = 17|0x100U, /**< SPI0 transmit complete */
+ kDmaRequestMux0SPI1Rx = 18|0x100U, /**< SPI1 receive complete */
+ kDmaRequestMux0SPI1Tx = 19|0x100U, /**< SPI1 transmit complete */
+ kDmaRequestMux0Reserved20 = 20|0x100U, /**< Reserved20 */
+ kDmaRequestMux0Reserved21 = 21|0x100U, /**< Reserved21 */
+ kDmaRequestMux0I2C0 = 22|0x100U, /**< I2C0 transmission complete */
+ kDmaRequestMux0I2C1 = 23|0x100U, /**< I2C1 transmission complete */
+ kDmaRequestMux0TPM0Channel0 = 24|0x100U, /**< TPM0 channel 0 event (CMP or CAP) */
+ kDmaRequestMux0TPM0Channel1 = 25|0x100U, /**< TPM0 channel 1 event (CMP or CAP) */
+ kDmaRequestMux0TPM0Channel2 = 26|0x100U, /**< TPM0 channel 2 event (CMP or CAP) */
+ kDmaRequestMux0TPM0Channel3 = 27|0x100U, /**< TPM0 channel 3 event (CMP or CAP) */
+ kDmaRequestMux0TPM0Channel4 = 28|0x100U, /**< TPM0 channel 4 event (CMP or CAP) */
+ kDmaRequestMux0TPM0Channel5 = 29|0x100U, /**< TPM0 channel 5 event (CMP or CAP) */
+ kDmaRequestMux0Reserved30 = 30|0x100U, /**< Reserved30 */
+ kDmaRequestMux0Reserved31 = 31|0x100U, /**< Reserved31 */
+ kDmaRequestMux0TPM1Channel0 = 32|0x100U, /**< TPM1 channel 0 event (CMP or CAP) */
+ kDmaRequestMux0TPM1Channel1 = 33|0x100U, /**< TPM1 channel 1 event (CMP or CAP) */
+ kDmaRequestMux0TPM2Channel0 = 34|0x100U, /**< TPM2 channel 0 event (CMP or CAP) */
+ kDmaRequestMux0TPM2Channel1 = 35|0x100U, /**< TPM2 channel 1 event (CMP or CAP) */
+ kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */
+ kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */
+ kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */
+ kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */
+ kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0 conversion complete */
+ kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */
+ kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0 Output */
+ kDmaRequestMux0Reserved43 = 43|0x100U, /**< Reserved43 */
+ kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */
+ kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0 buffer pointer reaches upper or lower limit */
+ kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */
+ kDmaRequestMux0Reserved47 = 47|0x100U, /**< Reserved47 */
+ kDmaRequestMux0Reserved48 = 48|0x100U, /**< Reserved48 */
+ kDmaRequestMux0PortA = 49|0x100U, /**< PORTA rising, falling or both edges */
+ kDmaRequestMux0Reserved50 = 50|0x100U, /**< Reserved50 */
+ kDmaRequestMux0PortC = 51|0x100U, /**< PORTC rising, falling or both edges */
+ kDmaRequestMux0PortD = 52|0x100U, /**< PORTD rising, falling or both edges */
+ kDmaRequestMux0Reserved53 = 53|0x100U, /**< Reserved53 */
+ kDmaRequestMux0TPM0Overflow = 54|0x100U, /**< TPM0 overflow */
+ kDmaRequestMux0TPM1Overflow = 55|0x100U, /**< TPM1 overflow */
+ kDmaRequestMux0TPM2Overflow = 56|0x100U, /**< TPM2 overflow */
+ kDmaRequestMux0TSI = 57|0x100U, /**< TSI0 event */
+ kDmaRequestMux0Reserved58 = 58|0x100U, /**< Reserved58 */
+ kDmaRequestMux0Reserved59 = 59|0x100U, /**< Reserved59 */
+ kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< Always enabled 60 */
+ kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< Always enabled 61 */
+ kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< Always enabled 62 */
+ kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< Always enabled 63 */
+} dma_request_source_t;
+
+/* @} */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+ __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
+ __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
+ __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
+ __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
+ __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
+ __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
+ __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
+ __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
+ __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
+ __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+ __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+ __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+ __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+ __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+ __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+ __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+ __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+ __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+ __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+ __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+ __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+ __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name SC1 - ADC Status and Control Registers 1 */
+#define ADC_SC1_ADCH_MASK (0x1FU)
+#define ADC_SC1_ADCH_SHIFT (0U)
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK (0x20U)
+#define ADC_SC1_DIFF_SHIFT (5U)
+#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
+#define ADC_SC1_AIEN_MASK (0x40U)
+#define ADC_SC1_AIEN_SHIFT (6U)
+#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
+#define ADC_SC1_COCO_MASK (0x80U)
+#define ADC_SC1_COCO_SHIFT (7U)
+#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
+
+/* The count of ADC_SC1 */
+#define ADC_SC1_COUNT (2U)
+
+/*! @name CFG1 - ADC Configuration Register 1 */
+#define ADC_CFG1_ADICLK_MASK (0x3U)
+#define ADC_CFG1_ADICLK_SHIFT (0U)
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK (0xCU)
+#define ADC_CFG1_MODE_SHIFT (2U)
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK (0x10U)
+#define ADC_CFG1_ADLSMP_SHIFT (4U)
+#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
+#define ADC_CFG1_ADIV_MASK (0x60U)
+#define ADC_CFG1_ADIV_SHIFT (5U)
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK (0x80U)
+#define ADC_CFG1_ADLPC_SHIFT (7U)
+#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
+
+/*! @name CFG2 - ADC Configuration Register 2 */
+#define ADC_CFG2_ADLSTS_MASK (0x3U)
+#define ADC_CFG2_ADLSTS_SHIFT (0U)
+#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK (0x4U)
+#define ADC_CFG2_ADHSC_SHIFT (2U)
+#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
+#define ADC_CFG2_ADACKEN_MASK (0x8U)
+#define ADC_CFG2_ADACKEN_SHIFT (3U)
+#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
+#define ADC_CFG2_MUXSEL_MASK (0x10U)
+#define ADC_CFG2_MUXSEL_SHIFT (4U)
+#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
+
+/*! @name R - ADC Data Result Register */
+#define ADC_R_D_MASK (0xFFFFU)
+#define ADC_R_D_SHIFT (0U)
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
+
+/* The count of ADC_R */
+#define ADC_R_COUNT (2U)
+
+/*! @name CV1 - Compare Value Registers */
+#define ADC_CV1_CV_MASK (0xFFFFU)
+#define ADC_CV1_CV_SHIFT (0U)
+#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
+
+/*! @name CV2 - Compare Value Registers */
+#define ADC_CV2_CV_MASK (0xFFFFU)
+#define ADC_CV2_CV_SHIFT (0U)
+#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
+
+/*! @name SC2 - Status and Control Register 2 */
+#define ADC_SC2_REFSEL_MASK (0x3U)
+#define ADC_SC2_REFSEL_SHIFT (0U)
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK (0x4U)
+#define ADC_SC2_DMAEN_SHIFT (2U)
+#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
+#define ADC_SC2_ACREN_MASK (0x8U)
+#define ADC_SC2_ACREN_SHIFT (3U)
+#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
+#define ADC_SC2_ACFGT_MASK (0x10U)
+#define ADC_SC2_ACFGT_SHIFT (4U)
+#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
+#define ADC_SC2_ACFE_MASK (0x20U)
+#define ADC_SC2_ACFE_SHIFT (5U)
+#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
+#define ADC_SC2_ADTRG_MASK (0x40U)
+#define ADC_SC2_ADTRG_SHIFT (6U)
+#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
+#define ADC_SC2_ADACT_MASK (0x80U)
+#define ADC_SC2_ADACT_SHIFT (7U)
+#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
+
+/*! @name SC3 - Status and Control Register 3 */
+#define ADC_SC3_AVGS_MASK (0x3U)
+#define ADC_SC3_AVGS_SHIFT (0U)
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK (0x4U)
+#define ADC_SC3_AVGE_SHIFT (2U)
+#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
+#define ADC_SC3_ADCO_MASK (0x8U)
+#define ADC_SC3_ADCO_SHIFT (3U)
+#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
+#define ADC_SC3_CALF_MASK (0x40U)
+#define ADC_SC3_CALF_SHIFT (6U)
+#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
+#define ADC_SC3_CAL_MASK (0x80U)
+#define ADC_SC3_CAL_SHIFT (7U)
+#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
+
+/*! @name OFS - ADC Offset Correction Register */
+#define ADC_OFS_OFS_MASK (0xFFFFU)
+#define ADC_OFS_OFS_SHIFT (0U)
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
+
+/*! @name PG - ADC Plus-Side Gain Register */
+#define ADC_PG_PG_MASK (0xFFFFU)
+#define ADC_PG_PG_SHIFT (0U)
+#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
+
+/*! @name MG - ADC Minus-Side Gain Register */
+#define ADC_MG_MG_MASK (0xFFFFU)
+#define ADC_MG_MG_SHIFT (0U)
+#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
+
+/*! @name CLPD - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLPD_CLPD_MASK (0x3FU)
+#define ADC_CLPD_CLPD_SHIFT (0U)
+#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
+
+/*! @name CLPS - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLPS_CLPS_MASK (0x3FU)
+#define ADC_CLPS_CLPS_SHIFT (0U)
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
+
+/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP4_CLP4_MASK (0x3FFU)
+#define ADC_CLP4_CLP4_SHIFT (0U)
+#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
+
+/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP3_CLP3_MASK (0x1FFU)
+#define ADC_CLP3_CLP3_SHIFT (0U)
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
+
+/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP2_CLP2_MASK (0xFFU)
+#define ADC_CLP2_CLP2_SHIFT (0U)
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
+
+/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP1_CLP1_MASK (0x7FU)
+#define ADC_CLP1_CLP1_SHIFT (0U)
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
+
+/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP0_CLP0_MASK (0x3FU)
+#define ADC_CLP0_CLP0_SHIFT (0U)
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
+
+/*! @name CLMD - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLMD_CLMD_MASK (0x3FU)
+#define ADC_CLMD_CLMD_SHIFT (0U)
+#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
+
+/*! @name CLMS - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLMS_CLMS_MASK (0x3FU)
+#define ADC_CLMS_CLMS_SHIFT (0U)
+#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
+
+/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM4_CLM4_MASK (0x3FFU)
+#define ADC_CLM4_CLM4_SHIFT (0U)
+#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
+
+/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM3_CLM3_MASK (0x1FFU)
+#define ADC_CLM3_CLM3_SHIFT (0U)
+#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
+
+/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM2_CLM2_MASK (0xFFU)
+#define ADC_CLM2_CLM2_SHIFT (0U)
+#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
+
+/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM1_CLM1_MASK (0x7FU)
+#define ADC_CLM1_CLM1_SHIFT (0U)
+#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
+
+/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM0_CLM0_MASK (0x3FU)
+#define ADC_CLM0_CLM0_SHIFT (0U)
+#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0 ((ADC_Type *)ADC0_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS { ADC0_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS { ADC0 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS { ADC0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
+ __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
+ __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
+ __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
+ __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
+ __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
+} CMP_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/*! @name CR0 - CMP Control Register 0 */
+#define CMP_CR0_HYSTCTR_MASK (0x3U)
+#define CMP_CR0_HYSTCTR_SHIFT (0U)
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK (0x70U)
+#define CMP_CR0_FILTER_CNT_SHIFT (4U)
+#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
+
+/*! @name CR1 - CMP Control Register 1 */
+#define CMP_CR1_EN_MASK (0x1U)
+#define CMP_CR1_EN_SHIFT (0U)
+#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
+#define CMP_CR1_OPE_MASK (0x2U)
+#define CMP_CR1_OPE_SHIFT (1U)
+#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
+#define CMP_CR1_COS_MASK (0x4U)
+#define CMP_CR1_COS_SHIFT (2U)
+#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
+#define CMP_CR1_INV_MASK (0x8U)
+#define CMP_CR1_INV_SHIFT (3U)
+#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
+#define CMP_CR1_PMODE_MASK (0x10U)
+#define CMP_CR1_PMODE_SHIFT (4U)
+#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
+#define CMP_CR1_TRIGM_MASK (0x20U)
+#define CMP_CR1_TRIGM_SHIFT (5U)
+#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
+#define CMP_CR1_WE_MASK (0x40U)
+#define CMP_CR1_WE_SHIFT (6U)
+#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
+#define CMP_CR1_SE_MASK (0x80U)
+#define CMP_CR1_SE_SHIFT (7U)
+#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
+
+/*! @name FPR - CMP Filter Period Register */
+#define CMP_FPR_FILT_PER_MASK (0xFFU)
+#define CMP_FPR_FILT_PER_SHIFT (0U)
+#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
+
+/*! @name SCR - CMP Status and Control Register */
+#define CMP_SCR_COUT_MASK (0x1U)
+#define CMP_SCR_COUT_SHIFT (0U)
+#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
+#define CMP_SCR_CFF_MASK (0x2U)
+#define CMP_SCR_CFF_SHIFT (1U)
+#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
+#define CMP_SCR_CFR_MASK (0x4U)
+#define CMP_SCR_CFR_SHIFT (2U)
+#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
+#define CMP_SCR_IEF_MASK (0x8U)
+#define CMP_SCR_IEF_SHIFT (3U)
+#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
+#define CMP_SCR_IER_MASK (0x10U)
+#define CMP_SCR_IER_SHIFT (4U)
+#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
+#define CMP_SCR_DMAEN_MASK (0x40U)
+#define CMP_SCR_DMAEN_SHIFT (6U)
+#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
+
+/*! @name DACCR - DAC Control Register */
+#define CMP_DACCR_VOSEL_MASK (0x3FU)
+#define CMP_DACCR_VOSEL_SHIFT (0U)
+#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK (0x40U)
+#define CMP_DACCR_VRSEL_SHIFT (6U)
+#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
+#define CMP_DACCR_DACEN_MASK (0x80U)
+#define CMP_DACCR_DACEN_SHIFT (7U)
+#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
+
+/*! @name MUXCR - MUX Control Register */
+#define CMP_MUXCR_MSEL_MASK (0x7U)
+#define CMP_MUXCR_MSEL_SHIFT (0U)
+#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK (0x38U)
+#define CMP_MUXCR_PSEL_SHIFT (3U)
+#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK (0x80U)
+#define CMP_MUXCR_PSTM_SHIFT (7U)
+#define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0 ((CMP_Type *)CMP0_BASE)
+/** Array initializer of CMP peripheral base addresses */
+#define CMP_BASE_ADDRS { CMP0_BASE }
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASE_PTRS { CMP0 }
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS { CMP0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+ } DAT[2];
+ uint8_t RESERVED_0[28];
+ __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
+ __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
+ __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
+ __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DAC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/*! @name DATL - DAC Data Low Register */
+#define DAC_DATL_DATA0_MASK (0xFFU)
+#define DAC_DATL_DATA0_SHIFT (0U)
+#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
+
+/* The count of DAC_DATL */
+#define DAC_DATL_COUNT (2U)
+
+/*! @name DATH - DAC Data High Register */
+#define DAC_DATH_DATA1_MASK (0xFU)
+#define DAC_DATH_DATA1_SHIFT (0U)
+#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
+
+/* The count of DAC_DATH */
+#define DAC_DATH_COUNT (2U)
+
+/*! @name SR - DAC Status Register */
+#define DAC_SR_DACBFRPBF_MASK (0x1U)
+#define DAC_SR_DACBFRPBF_SHIFT (0U)
+#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
+#define DAC_SR_DACBFRPTF_MASK (0x2U)
+#define DAC_SR_DACBFRPTF_SHIFT (1U)
+#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
+
+/*! @name C0 - DAC Control Register */
+#define DAC_C0_DACBBIEN_MASK (0x1U)
+#define DAC_C0_DACBBIEN_SHIFT (0U)
+#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
+#define DAC_C0_DACBTIEN_MASK (0x2U)
+#define DAC_C0_DACBTIEN_SHIFT (1U)
+#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
+#define DAC_C0_LPEN_MASK (0x8U)
+#define DAC_C0_LPEN_SHIFT (3U)
+#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
+#define DAC_C0_DACSWTRG_MASK (0x10U)
+#define DAC_C0_DACSWTRG_SHIFT (4U)
+#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
+#define DAC_C0_DACTRGSEL_MASK (0x20U)
+#define DAC_C0_DACTRGSEL_SHIFT (5U)
+#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
+#define DAC_C0_DACRFS_MASK (0x40U)
+#define DAC_C0_DACRFS_SHIFT (6U)
+#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
+#define DAC_C0_DACEN_MASK (0x80U)
+#define DAC_C0_DACEN_SHIFT (7U)
+#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
+
+/*! @name C1 - DAC Control Register 1 */
+#define DAC_C1_DACBFEN_MASK (0x1U)
+#define DAC_C1_DACBFEN_SHIFT (0U)
+#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
+#define DAC_C1_DACBFMD_MASK (0x4U)
+#define DAC_C1_DACBFMD_SHIFT (2U)
+#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DMAEN_MASK (0x80U)
+#define DAC_C1_DMAEN_SHIFT (7U)
+#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
+
+/*! @name C2 - DAC Control Register 2 */
+#define DAC_C2_DACBFUP_MASK (0x1U)
+#define DAC_C2_DACBFUP_SHIFT (0U)
+#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFRP_MASK (0x10U)
+#define DAC_C2_DACBFRP_SHIFT (4U)
+#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE (0x4003F000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0 ((DAC_Type *)DAC0_BASE)
+/** Array initializer of DAC peripheral base addresses */
+#define DAC_BASE_ADDRS { DAC0_BASE }
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASE_PTRS { DAC0 }
+/** Interrupt vectors for the DAC peripheral type */
+#define DAC_IRQS { DAC0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[256];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
+ __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
+ union { /* offset: 0x108, array step: 0x10 */
+ __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
+ struct { /* offset: 0x108, array step: 0x10 */
+ uint8_t RESERVED_0[3];
+ __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
+ } DMA_DSR_ACCESS8BIT;
+ };
+ __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
+ } DMA[4];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/*! @name SAR - Source Address Register */
+#define DMA_SAR_SAR_MASK (0xFFFFFFFFU)
+#define DMA_SAR_SAR_SHIFT (0U)
+#define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SAR_SAR_SHIFT)) & DMA_SAR_SAR_MASK)
+
+/* The count of DMA_SAR */
+#define DMA_SAR_COUNT (4U)
+
+/*! @name DAR - Destination Address Register */
+#define DMA_DAR_DAR_MASK (0xFFFFFFFFU)
+#define DMA_DAR_DAR_SHIFT (0U)
+#define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DAR_DAR_SHIFT)) & DMA_DAR_DAR_MASK)
+
+/* The count of DMA_DAR */
+#define DMA_DAR_COUNT (4U)
+
+/*! @name DSR_BCR - DMA Status Register / Byte Count Register */
+#define DMA_DSR_BCR_BCR_MASK (0xFFFFFFU)
+#define DMA_DSR_BCR_BCR_SHIFT (0U)
+#define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BCR_SHIFT)) & DMA_DSR_BCR_BCR_MASK)
+#define DMA_DSR_BCR_DONE_MASK (0x1000000U)
+#define DMA_DSR_BCR_DONE_SHIFT (24U)
+#define DMA_DSR_BCR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_DONE_SHIFT)) & DMA_DSR_BCR_DONE_MASK)
+#define DMA_DSR_BCR_BSY_MASK (0x2000000U)
+#define DMA_DSR_BCR_BSY_SHIFT (25U)
+#define DMA_DSR_BCR_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BSY_SHIFT)) & DMA_DSR_BCR_BSY_MASK)
+#define DMA_DSR_BCR_REQ_MASK (0x4000000U)
+#define DMA_DSR_BCR_REQ_SHIFT (26U)
+#define DMA_DSR_BCR_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_REQ_SHIFT)) & DMA_DSR_BCR_REQ_MASK)
+#define DMA_DSR_BCR_BED_MASK (0x10000000U)
+#define DMA_DSR_BCR_BED_SHIFT (28U)
+#define DMA_DSR_BCR_BED(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BED_SHIFT)) & DMA_DSR_BCR_BED_MASK)
+#define DMA_DSR_BCR_BES_MASK (0x20000000U)
+#define DMA_DSR_BCR_BES_SHIFT (29U)
+#define DMA_DSR_BCR_BES(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BES_SHIFT)) & DMA_DSR_BCR_BES_MASK)
+#define DMA_DSR_BCR_CE_MASK (0x40000000U)
+#define DMA_DSR_BCR_CE_SHIFT (30U)
+#define DMA_DSR_BCR_CE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_CE_SHIFT)) & DMA_DSR_BCR_CE_MASK)
+
+/* The count of DMA_DSR_BCR */
+#define DMA_DSR_BCR_COUNT (4U)
+
+/* The count of DMA_DSR */
+#define DMA_DSR_COUNT (4U)
+
+/*! @name DCR - DMA Control Register */
+#define DMA_DCR_LCH2_MASK (0x3U)
+#define DMA_DCR_LCH2_SHIFT (0U)
+#define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH2_SHIFT)) & DMA_DCR_LCH2_MASK)
+#define DMA_DCR_LCH1_MASK (0xCU)
+#define DMA_DCR_LCH1_SHIFT (2U)
+#define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH1_SHIFT)) & DMA_DCR_LCH1_MASK)
+#define DMA_DCR_LINKCC_MASK (0x30U)
+#define DMA_DCR_LINKCC_SHIFT (4U)
+#define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LINKCC_SHIFT)) & DMA_DCR_LINKCC_MASK)
+#define DMA_DCR_D_REQ_MASK (0x80U)
+#define DMA_DCR_D_REQ_SHIFT (7U)
+#define DMA_DCR_D_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_D_REQ_SHIFT)) & DMA_DCR_D_REQ_MASK)
+#define DMA_DCR_DMOD_MASK (0xF00U)
+#define DMA_DCR_DMOD_SHIFT (8U)
+#define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DMOD_SHIFT)) & DMA_DCR_DMOD_MASK)
+#define DMA_DCR_SMOD_MASK (0xF000U)
+#define DMA_DCR_SMOD_SHIFT (12U)
+#define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SMOD_SHIFT)) & DMA_DCR_SMOD_MASK)
+#define DMA_DCR_START_MASK (0x10000U)
+#define DMA_DCR_START_SHIFT (16U)
+#define DMA_DCR_START(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_START_SHIFT)) & DMA_DCR_START_MASK)
+#define DMA_DCR_DSIZE_MASK (0x60000U)
+#define DMA_DCR_DSIZE_SHIFT (17U)
+#define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DSIZE_SHIFT)) & DMA_DCR_DSIZE_MASK)
+#define DMA_DCR_DINC_MASK (0x80000U)
+#define DMA_DCR_DINC_SHIFT (19U)
+#define DMA_DCR_DINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DINC_SHIFT)) & DMA_DCR_DINC_MASK)
+#define DMA_DCR_SSIZE_MASK (0x300000U)
+#define DMA_DCR_SSIZE_SHIFT (20U)
+#define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SSIZE_SHIFT)) & DMA_DCR_SSIZE_MASK)
+#define DMA_DCR_SINC_MASK (0x400000U)
+#define DMA_DCR_SINC_SHIFT (22U)
+#define DMA_DCR_SINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SINC_SHIFT)) & DMA_DCR_SINC_MASK)
+#define DMA_DCR_EADREQ_MASK (0x800000U)
+#define DMA_DCR_EADREQ_SHIFT (23U)
+#define DMA_DCR_EADREQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EADREQ_SHIFT)) & DMA_DCR_EADREQ_MASK)
+#define DMA_DCR_AA_MASK (0x10000000U)
+#define DMA_DCR_AA_SHIFT (28U)
+#define DMA_DCR_AA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_AA_SHIFT)) & DMA_DCR_AA_MASK)
+#define DMA_DCR_CS_MASK (0x20000000U)
+#define DMA_DCR_CS_SHIFT (29U)
+#define DMA_DCR_CS(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_CS_SHIFT)) & DMA_DCR_CS_MASK)
+#define DMA_DCR_ERQ_MASK (0x40000000U)
+#define DMA_DCR_ERQ_SHIFT (30U)
+#define DMA_DCR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_ERQ_SHIFT)) & DMA_DCR_ERQ_MASK)
+#define DMA_DCR_EINT_MASK (0x80000000U)
+#define DMA_DCR_EINT_SHIFT (31U)
+#define DMA_DCR_EINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EINT_SHIFT)) & DMA_DCR_EINT_MASK)
+
+/* The count of DMA_DCR */
+#define DMA_DCR_COUNT (4U)
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0 ((DMA_Type *)DMA_BASE)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS { DMA_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/*! @name CHCFG - Channel Configuration register */
+#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
+#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK (0x40U)
+#define DMAMUX_CHCFG_TRIG_SHIFT (6U)
+#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
+#define DMAMUX_CHCFG_ENBL_MASK (0x80U)
+#define DMAMUX_CHCFG_ENBL_SHIFT (7U)
+#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
+
+/* The count of DMAMUX_CHCFG */
+#define DMAMUX_CHCFG_COUNT (4U)
+
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX0 base address */
+#define DMAMUX0_BASE (0x40021000u)
+/** Peripheral DMAMUX0 base pointer */
+#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
+/** Array initializer of DMAMUX peripheral base addresses */
+#define DMAMUX_BASE_ADDRS { DMAMUX0_BASE }
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASE_PTRS { DMAMUX0 }
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FGPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
+ * @{
+ */
+
+/** FGPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} FGPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FGPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
+ * @{
+ */
+
+/*! @name PDOR - Port Data Output Register */
+#define FGPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
+#define FGPIO_PDOR_PDO_SHIFT (0U)
+#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK)
+
+/*! @name PSOR - Port Set Output Register */
+#define FGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
+#define FGPIO_PSOR_PTSO_SHIFT (0U)
+#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK)
+
+/*! @name PCOR - Port Clear Output Register */
+#define FGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
+#define FGPIO_PCOR_PTCO_SHIFT (0U)
+#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK)
+
+/*! @name PTOR - Port Toggle Output Register */
+#define FGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
+#define FGPIO_PTOR_PTTO_SHIFT (0U)
+#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK)
+
+/*! @name PDIR - Port Data Input Register */
+#define FGPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
+#define FGPIO_PDIR_PDI_SHIFT (0U)
+#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK)
+
+/*! @name PDDR - Port Data Direction Register */
+#define FGPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
+#define FGPIO_PDDR_PDD_SHIFT (0U)
+#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group FGPIO_Register_Masks */
+
+
+/* FGPIO - Peripheral instance base addresses */
+/** Peripheral FGPIOA base address */
+#define FGPIOA_BASE (0xF8000000u)
+/** Peripheral FGPIOA base pointer */
+#define FGPIOA ((FGPIO_Type *)FGPIOA_BASE)
+/** Peripheral FGPIOB base address */
+#define FGPIOB_BASE (0xF8000040u)
+/** Peripheral FGPIOB base pointer */
+#define FGPIOB ((FGPIO_Type *)FGPIOB_BASE)
+/** Peripheral FGPIOC base address */
+#define FGPIOC_BASE (0xF8000080u)
+/** Peripheral FGPIOC base pointer */
+#define FGPIOC ((FGPIO_Type *)FGPIOC_BASE)
+/** Peripheral FGPIOD base address */
+#define FGPIOD_BASE (0xF80000C0u)
+/** Peripheral FGPIOD base pointer */
+#define FGPIOD ((FGPIO_Type *)FGPIOD_BASE)
+/** Peripheral FGPIOE base address */
+#define FGPIOE_BASE (0xF8000100u)
+/** Peripheral FGPIOE base pointer */
+#define FGPIOE ((FGPIO_Type *)FGPIOE_BASE)
+/** Array initializer of FGPIO peripheral base addresses */
+#define FGPIO_BASE_ADDRS { FGPIOA_BASE, FGPIOB_BASE, FGPIOC_BASE, FGPIOD_BASE, FGPIOE_BASE }
+/** Array initializer of FGPIO peripheral base pointers */
+#define FGPIO_BASE_PTRS { FGPIOA, FGPIOB, FGPIOC, FGPIOD, FGPIOE }
+
+/*!
+ * @}
+ */ /* end of group FGPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
+ * @{
+ */
+
+/** FTFA - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
+ __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
+ __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
+ __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
+ __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
+ __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
+ __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
+ __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
+ __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
+ __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
+ __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
+ __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
+ __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
+ __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
+ __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
+ __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
+ __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
+ __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
+ __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
+ __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
+} FTFA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Register_Masks FTFA Register Masks
+ * @{
+ */
+
+/*! @name FSTAT - Flash Status Register */
+#define FTFA_FSTAT_MGSTAT0_MASK (0x1U)
+#define FTFA_FSTAT_MGSTAT0_SHIFT (0U)
+#define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK)
+#define FTFA_FSTAT_FPVIOL_MASK (0x10U)
+#define FTFA_FSTAT_FPVIOL_SHIFT (4U)
+#define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK)
+#define FTFA_FSTAT_ACCERR_MASK (0x20U)
+#define FTFA_FSTAT_ACCERR_SHIFT (5U)
+#define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK)
+#define FTFA_FSTAT_RDCOLERR_MASK (0x40U)
+#define FTFA_FSTAT_RDCOLERR_SHIFT (6U)
+#define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK)
+#define FTFA_FSTAT_CCIF_MASK (0x80U)
+#define FTFA_FSTAT_CCIF_SHIFT (7U)
+#define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK)
+
+/*! @name FCNFG - Flash Configuration Register */
+#define FTFA_FCNFG_ERSSUSP_MASK (0x10U)
+#define FTFA_FCNFG_ERSSUSP_SHIFT (4U)
+#define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK)
+#define FTFA_FCNFG_ERSAREQ_MASK (0x20U)
+#define FTFA_FCNFG_ERSAREQ_SHIFT (5U)
+#define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK)
+#define FTFA_FCNFG_RDCOLLIE_MASK (0x40U)
+#define FTFA_FCNFG_RDCOLLIE_SHIFT (6U)
+#define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK)
+#define FTFA_FCNFG_CCIE_MASK (0x80U)
+#define FTFA_FCNFG_CCIE_SHIFT (7U)
+#define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK)
+
+/*! @name FSEC - Flash Security Register */
+#define FTFA_FSEC_SEC_MASK (0x3U)
+#define FTFA_FSEC_SEC_SHIFT (0U)
+#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK)
+#define FTFA_FSEC_FSLACC_MASK (0xCU)
+#define FTFA_FSEC_FSLACC_SHIFT (2U)
+#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK)
+#define FTFA_FSEC_MEEN_MASK (0x30U)
+#define FTFA_FSEC_MEEN_SHIFT (4U)
+#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK)
+#define FTFA_FSEC_KEYEN_MASK (0xC0U)
+#define FTFA_FSEC_KEYEN_SHIFT (6U)
+#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK)
+
+/*! @name FOPT - Flash Option Register */
+#define FTFA_FOPT_OPT_MASK (0xFFU)
+#define FTFA_FOPT_OPT_SHIFT (0U)
+#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK)
+
+/*! @name FCCOB3 - Flash Common Command Object Registers */
+#define FTFA_FCCOB3_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB3_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK)
+
+/*! @name FCCOB2 - Flash Common Command Object Registers */
+#define FTFA_FCCOB2_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB2_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK)
+
+/*! @name FCCOB1 - Flash Common Command Object Registers */
+#define FTFA_FCCOB1_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB1_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK)
+
+/*! @name FCCOB0 - Flash Common Command Object Registers */
+#define FTFA_FCCOB0_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB0_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK)
+
+/*! @name FCCOB7 - Flash Common Command Object Registers */
+#define FTFA_FCCOB7_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB7_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK)
+
+/*! @name FCCOB6 - Flash Common Command Object Registers */
+#define FTFA_FCCOB6_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB6_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK)
+
+/*! @name FCCOB5 - Flash Common Command Object Registers */
+#define FTFA_FCCOB5_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB5_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK)
+
+/*! @name FCCOB4 - Flash Common Command Object Registers */
+#define FTFA_FCCOB4_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB4_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK)
+
+/*! @name FCCOBB - Flash Common Command Object Registers */
+#define FTFA_FCCOBB_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOBB_CCOBn_SHIFT (0U)
+#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK)
+
+/*! @name FCCOBA - Flash Common Command Object Registers */
+#define FTFA_FCCOBA_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOBA_CCOBn_SHIFT (0U)
+#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK)
+
+/*! @name FCCOB9 - Flash Common Command Object Registers */
+#define FTFA_FCCOB9_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB9_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK)
+
+/*! @name FCCOB8 - Flash Common Command Object Registers */
+#define FTFA_FCCOB8_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB8_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK)
+
+/*! @name FPROT3 - Program Flash Protection Registers */
+#define FTFA_FPROT3_PROT_MASK (0xFFU)
+#define FTFA_FPROT3_PROT_SHIFT (0U)
+#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK)
+
+/*! @name FPROT2 - Program Flash Protection Registers */
+#define FTFA_FPROT2_PROT_MASK (0xFFU)
+#define FTFA_FPROT2_PROT_SHIFT (0U)
+#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK)
+
+/*! @name FPROT1 - Program Flash Protection Registers */
+#define FTFA_FPROT1_PROT_MASK (0xFFU)
+#define FTFA_FPROT1_PROT_SHIFT (0U)
+#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK)
+
+/*! @name FPROT0 - Program Flash Protection Registers */
+#define FTFA_FPROT0_PROT_MASK (0xFFU)
+#define FTFA_FPROT0_PROT_SHIFT (0U)
+#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group FTFA_Register_Masks */
+
+
+/* FTFA - Peripheral instance base addresses */
+/** Peripheral FTFA base address */
+#define FTFA_BASE (0x40020000u)
+/** Peripheral FTFA base pointer */
+#define FTFA ((FTFA_Type *)FTFA_BASE)
+/** Array initializer of FTFA peripheral base addresses */
+#define FTFA_BASE_ADDRS { FTFA_BASE }
+/** Array initializer of FTFA peripheral base pointers */
+#define FTFA_BASE_PTRS { FTFA }
+/** Interrupt vectors for the FTFA peripheral type */
+#define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FTFA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/*! @name PDOR - Port Data Output Register */
+#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
+#define GPIO_PDOR_PDO_SHIFT (0U)
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
+
+/*! @name PSOR - Port Set Output Register */
+#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
+#define GPIO_PSOR_PTSO_SHIFT (0U)
+#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
+
+/*! @name PCOR - Port Clear Output Register */
+#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
+#define GPIO_PCOR_PTCO_SHIFT (0U)
+#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
+
+/*! @name PTOR - Port Toggle Output Register */
+#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
+#define GPIO_PTOR_PTTO_SHIFT (0U)
+#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
+
+/*! @name PDIR - Port Data Input Register */
+#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
+#define GPIO_PDIR_PDI_SHIFT (0U)
+#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
+
+/*! @name PDDR - Port Data Direction Register */
+#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
+#define GPIO_PDDR_PDD_SHIFT (0U)
+#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral GPIOA base address */
+#define GPIOA_BASE (0x400FF000u)
+/** Peripheral GPIOA base pointer */
+#define GPIOA ((GPIO_Type *)GPIOA_BASE)
+/** Peripheral GPIOB base address */
+#define GPIOB_BASE (0x400FF040u)
+/** Peripheral GPIOB base pointer */
+#define GPIOB ((GPIO_Type *)GPIOB_BASE)
+/** Peripheral GPIOC base address */
+#define GPIOC_BASE (0x400FF080u)
+/** Peripheral GPIOC base pointer */
+#define GPIOC ((GPIO_Type *)GPIOC_BASE)
+/** Peripheral GPIOD base address */
+#define GPIOD_BASE (0x400FF0C0u)
+/** Peripheral GPIOD base pointer */
+#define GPIOD ((GPIO_Type *)GPIOD_BASE)
+/** Peripheral GPIOE base address */
+#define GPIOE_BASE (0x400FF100u)
+/** Peripheral GPIOE base pointer */
+#define GPIOE ((GPIO_Type *)GPIOE_BASE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
+ __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
+ __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
+ __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
+ __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
+ __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
+ __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+ __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
+ __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
+ __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
+ __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
+ __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/*! @name A1 - I2C Address Register 1 */
+#define I2C_A1_AD_MASK (0xFEU)
+#define I2C_A1_AD_SHIFT (1U)
+#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
+
+/*! @name F - I2C Frequency Divider register */
+#define I2C_F_ICR_MASK (0x3FU)
+#define I2C_F_ICR_SHIFT (0U)
+#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK (0xC0U)
+#define I2C_F_MULT_SHIFT (6U)
+#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
+
+/*! @name C1 - I2C Control Register 1 */
+#define I2C_C1_DMAEN_MASK (0x1U)
+#define I2C_C1_DMAEN_SHIFT (0U)
+#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
+#define I2C_C1_WUEN_MASK (0x2U)
+#define I2C_C1_WUEN_SHIFT (1U)
+#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
+#define I2C_C1_RSTA_MASK (0x4U)
+#define I2C_C1_RSTA_SHIFT (2U)
+#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
+#define I2C_C1_TXAK_MASK (0x8U)
+#define I2C_C1_TXAK_SHIFT (3U)
+#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
+#define I2C_C1_TX_MASK (0x10U)
+#define I2C_C1_TX_SHIFT (4U)
+#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
+#define I2C_C1_MST_MASK (0x20U)
+#define I2C_C1_MST_SHIFT (5U)
+#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
+#define I2C_C1_IICIE_MASK (0x40U)
+#define I2C_C1_IICIE_SHIFT (6U)
+#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
+#define I2C_C1_IICEN_MASK (0x80U)
+#define I2C_C1_IICEN_SHIFT (7U)
+#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
+
+/*! @name S - I2C Status register */
+#define I2C_S_RXAK_MASK (0x1U)
+#define I2C_S_RXAK_SHIFT (0U)
+#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
+#define I2C_S_IICIF_MASK (0x2U)
+#define I2C_S_IICIF_SHIFT (1U)
+#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
+#define I2C_S_SRW_MASK (0x4U)
+#define I2C_S_SRW_SHIFT (2U)
+#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
+#define I2C_S_RAM_MASK (0x8U)
+#define I2C_S_RAM_SHIFT (3U)
+#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
+#define I2C_S_ARBL_MASK (0x10U)
+#define I2C_S_ARBL_SHIFT (4U)
+#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
+#define I2C_S_BUSY_MASK (0x20U)
+#define I2C_S_BUSY_SHIFT (5U)
+#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
+#define I2C_S_IAAS_MASK (0x40U)
+#define I2C_S_IAAS_SHIFT (6U)
+#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
+#define I2C_S_TCF_MASK (0x80U)
+#define I2C_S_TCF_SHIFT (7U)
+#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
+
+/*! @name D - I2C Data I/O register */
+#define I2C_D_DATA_MASK (0xFFU)
+#define I2C_D_DATA_SHIFT (0U)
+#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
+
+/*! @name C2 - I2C Control Register 2 */
+#define I2C_C2_AD_MASK (0x7U)
+#define I2C_C2_AD_SHIFT (0U)
+#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK (0x8U)
+#define I2C_C2_RMEN_SHIFT (3U)
+#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
+#define I2C_C2_SBRC_MASK (0x10U)
+#define I2C_C2_SBRC_SHIFT (4U)
+#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
+#define I2C_C2_HDRS_MASK (0x20U)
+#define I2C_C2_HDRS_SHIFT (5U)
+#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
+#define I2C_C2_ADEXT_MASK (0x40U)
+#define I2C_C2_ADEXT_SHIFT (6U)
+#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
+#define I2C_C2_GCAEN_MASK (0x80U)
+#define I2C_C2_GCAEN_SHIFT (7U)
+#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
+
+/*! @name FLT - I2C Programmable Input Glitch Filter register */
+#define I2C_FLT_FLT_MASK (0xFU)
+#define I2C_FLT_FLT_SHIFT (0U)
+#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
+#define I2C_FLT_STARTF_MASK (0x10U)
+#define I2C_FLT_STARTF_SHIFT (4U)
+#define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
+#define I2C_FLT_SSIE_MASK (0x20U)
+#define I2C_FLT_SSIE_SHIFT (5U)
+#define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
+#define I2C_FLT_STOPF_MASK (0x40U)
+#define I2C_FLT_STOPF_SHIFT (6U)
+#define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
+#define I2C_FLT_SHEN_MASK (0x80U)
+#define I2C_FLT_SHEN_SHIFT (7U)
+#define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
+
+/*! @name RA - I2C Range Address register */
+#define I2C_RA_RAD_MASK (0xFEU)
+#define I2C_RA_RAD_SHIFT (1U)
+#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
+
+/*! @name SMB - I2C SMBus Control and Status register */
+#define I2C_SMB_SHTF2IE_MASK (0x1U)
+#define I2C_SMB_SHTF2IE_SHIFT (0U)
+#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
+#define I2C_SMB_SHTF2_MASK (0x2U)
+#define I2C_SMB_SHTF2_SHIFT (1U)
+#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
+#define I2C_SMB_SHTF1_MASK (0x4U)
+#define I2C_SMB_SHTF1_SHIFT (2U)
+#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
+#define I2C_SMB_SLTF_MASK (0x8U)
+#define I2C_SMB_SLTF_SHIFT (3U)
+#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
+#define I2C_SMB_TCKSEL_MASK (0x10U)
+#define I2C_SMB_TCKSEL_SHIFT (4U)
+#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
+#define I2C_SMB_SIICAEN_MASK (0x20U)
+#define I2C_SMB_SIICAEN_SHIFT (5U)
+#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
+#define I2C_SMB_ALERTEN_MASK (0x40U)
+#define I2C_SMB_ALERTEN_SHIFT (6U)
+#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
+#define I2C_SMB_FACK_MASK (0x80U)
+#define I2C_SMB_FACK_SHIFT (7U)
+#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
+
+/*! @name A2 - I2C Address Register 2 */
+#define I2C_A2_SAD_MASK (0xFEU)
+#define I2C_A2_SAD_SHIFT (1U)
+#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
+
+/*! @name SLTH - I2C SCL Low Timeout Register High */
+#define I2C_SLTH_SSLT_MASK (0xFFU)
+#define I2C_SLTH_SSLT_SHIFT (0U)
+#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
+
+/*! @name SLTL - I2C SCL Low Timeout Register Low */
+#define I2C_SLTL_SSLT_MASK (0xFFU)
+#define I2C_SLTL_SSLT_SHIFT (0U)
+#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0 ((I2C_Type *)I2C0_BASE)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1 ((I2C_Type *)I2C1_BASE)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS { I2C0, I2C1 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+ __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+ __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+ __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+ uint8_t RESERVED_1[8];
+ __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+ uint8_t RESERVED_2[60];
+ __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
+ uint8_t RESERVED_3[28];
+ __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
+ uint8_t RESERVED_4[4];
+ __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+ __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+ __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+ __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+ uint8_t RESERVED_5[8];
+ __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+ uint8_t RESERVED_6[60];
+ __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
+ uint8_t RESERVED_7[28];
+ __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
+ __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
+} I2S_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2S Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/*! @name TCSR - SAI Transmit Control Register */
+#define I2S_TCSR_FWDE_MASK (0x2U)
+#define I2S_TCSR_FWDE_SHIFT (1U)
+#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
+#define I2S_TCSR_FWIE_MASK (0x200U)
+#define I2S_TCSR_FWIE_SHIFT (9U)
+#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
+#define I2S_TCSR_FEIE_MASK (0x400U)
+#define I2S_TCSR_FEIE_SHIFT (10U)
+#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
+#define I2S_TCSR_SEIE_MASK (0x800U)
+#define I2S_TCSR_SEIE_SHIFT (11U)
+#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
+#define I2S_TCSR_WSIE_MASK (0x1000U)
+#define I2S_TCSR_WSIE_SHIFT (12U)
+#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
+#define I2S_TCSR_FWF_MASK (0x20000U)
+#define I2S_TCSR_FWF_SHIFT (17U)
+#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
+#define I2S_TCSR_FEF_MASK (0x40000U)
+#define I2S_TCSR_FEF_SHIFT (18U)
+#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
+#define I2S_TCSR_SEF_MASK (0x80000U)
+#define I2S_TCSR_SEF_SHIFT (19U)
+#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
+#define I2S_TCSR_WSF_MASK (0x100000U)
+#define I2S_TCSR_WSF_SHIFT (20U)
+#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
+#define I2S_TCSR_SR_MASK (0x1000000U)
+#define I2S_TCSR_SR_SHIFT (24U)
+#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
+#define I2S_TCSR_FR_MASK (0x2000000U)
+#define I2S_TCSR_FR_SHIFT (25U)
+#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
+#define I2S_TCSR_BCE_MASK (0x10000000U)
+#define I2S_TCSR_BCE_SHIFT (28U)
+#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
+#define I2S_TCSR_DBGE_MASK (0x20000000U)
+#define I2S_TCSR_DBGE_SHIFT (29U)
+#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
+#define I2S_TCSR_STOPE_MASK (0x40000000U)
+#define I2S_TCSR_STOPE_SHIFT (30U)
+#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
+#define I2S_TCSR_TE_MASK (0x80000000U)
+#define I2S_TCSR_TE_SHIFT (31U)
+#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
+
+/*! @name TCR2 - SAI Transmit Configuration 2 Register */
+#define I2S_TCR2_DIV_MASK (0xFFU)
+#define I2S_TCR2_DIV_SHIFT (0U)
+#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK (0x1000000U)
+#define I2S_TCR2_BCD_SHIFT (24U)
+#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
+#define I2S_TCR2_BCP_MASK (0x2000000U)
+#define I2S_TCR2_BCP_SHIFT (25U)
+#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
+#define I2S_TCR2_MSEL_MASK (0xC000000U)
+#define I2S_TCR2_MSEL_SHIFT (26U)
+#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK (0x10000000U)
+#define I2S_TCR2_BCI_SHIFT (28U)
+#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
+#define I2S_TCR2_BCS_MASK (0x20000000U)
+#define I2S_TCR2_BCS_SHIFT (29U)
+#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
+#define I2S_TCR2_SYNC_MASK (0xC0000000U)
+#define I2S_TCR2_SYNC_SHIFT (30U)
+#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
+
+/*! @name TCR3 - SAI Transmit Configuration 3 Register */
+#define I2S_TCR3_WDFL_MASK (0x1U)
+#define I2S_TCR3_WDFL_SHIFT (0U)
+#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK (0x10000U)
+#define I2S_TCR3_TCE_SHIFT (16U)
+#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
+
+/*! @name TCR4 - SAI Transmit Configuration 4 Register */
+#define I2S_TCR4_FSD_MASK (0x1U)
+#define I2S_TCR4_FSD_SHIFT (0U)
+#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
+#define I2S_TCR4_FSP_MASK (0x2U)
+#define I2S_TCR4_FSP_SHIFT (1U)
+#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
+#define I2S_TCR4_FSE_MASK (0x8U)
+#define I2S_TCR4_FSE_SHIFT (3U)
+#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
+#define I2S_TCR4_MF_MASK (0x10U)
+#define I2S_TCR4_MF_SHIFT (4U)
+#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
+#define I2S_TCR4_SYWD_MASK (0x1F00U)
+#define I2S_TCR4_SYWD_SHIFT (8U)
+#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK (0x10000U)
+#define I2S_TCR4_FRSZ_SHIFT (16U)
+#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
+
+/*! @name TCR5 - SAI Transmit Configuration 5 Register */
+#define I2S_TCR5_FBT_MASK (0x1F00U)
+#define I2S_TCR5_FBT_SHIFT (8U)
+#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK (0x1F0000U)
+#define I2S_TCR5_W0W_SHIFT (16U)
+#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK (0x1F000000U)
+#define I2S_TCR5_WNW_SHIFT (24U)
+#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
+
+/*! @name TDR - SAI Transmit Data Register */
+#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
+#define I2S_TDR_TDR_SHIFT (0U)
+#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
+
+/* The count of I2S_TDR */
+#define I2S_TDR_COUNT (1U)
+
+/*! @name TMR - SAI Transmit Mask Register */
+#define I2S_TMR_TWM_MASK (0x3U)
+#define I2S_TMR_TWM_SHIFT (0U)
+#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
+
+/*! @name RCSR - SAI Receive Control Register */
+#define I2S_RCSR_FWDE_MASK (0x2U)
+#define I2S_RCSR_FWDE_SHIFT (1U)
+#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
+#define I2S_RCSR_FWIE_MASK (0x200U)
+#define I2S_RCSR_FWIE_SHIFT (9U)
+#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
+#define I2S_RCSR_FEIE_MASK (0x400U)
+#define I2S_RCSR_FEIE_SHIFT (10U)
+#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
+#define I2S_RCSR_SEIE_MASK (0x800U)
+#define I2S_RCSR_SEIE_SHIFT (11U)
+#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
+#define I2S_RCSR_WSIE_MASK (0x1000U)
+#define I2S_RCSR_WSIE_SHIFT (12U)
+#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
+#define I2S_RCSR_FWF_MASK (0x20000U)
+#define I2S_RCSR_FWF_SHIFT (17U)
+#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
+#define I2S_RCSR_FEF_MASK (0x40000U)
+#define I2S_RCSR_FEF_SHIFT (18U)
+#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
+#define I2S_RCSR_SEF_MASK (0x80000U)
+#define I2S_RCSR_SEF_SHIFT (19U)
+#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
+#define I2S_RCSR_WSF_MASK (0x100000U)
+#define I2S_RCSR_WSF_SHIFT (20U)
+#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
+#define I2S_RCSR_SR_MASK (0x1000000U)
+#define I2S_RCSR_SR_SHIFT (24U)
+#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
+#define I2S_RCSR_FR_MASK (0x2000000U)
+#define I2S_RCSR_FR_SHIFT (25U)
+#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
+#define I2S_RCSR_BCE_MASK (0x10000000U)
+#define I2S_RCSR_BCE_SHIFT (28U)
+#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
+#define I2S_RCSR_DBGE_MASK (0x20000000U)
+#define I2S_RCSR_DBGE_SHIFT (29U)
+#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
+#define I2S_RCSR_STOPE_MASK (0x40000000U)
+#define I2S_RCSR_STOPE_SHIFT (30U)
+#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
+#define I2S_RCSR_RE_MASK (0x80000000U)
+#define I2S_RCSR_RE_SHIFT (31U)
+#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
+
+/*! @name RCR2 - SAI Receive Configuration 2 Register */
+#define I2S_RCR2_DIV_MASK (0xFFU)
+#define I2S_RCR2_DIV_SHIFT (0U)
+#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK (0x1000000U)
+#define I2S_RCR2_BCD_SHIFT (24U)
+#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
+#define I2S_RCR2_BCP_MASK (0x2000000U)
+#define I2S_RCR2_BCP_SHIFT (25U)
+#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
+#define I2S_RCR2_MSEL_MASK (0xC000000U)
+#define I2S_RCR2_MSEL_SHIFT (26U)
+#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK (0x10000000U)
+#define I2S_RCR2_BCI_SHIFT (28U)
+#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
+#define I2S_RCR2_BCS_MASK (0x20000000U)
+#define I2S_RCR2_BCS_SHIFT (29U)
+#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
+#define I2S_RCR2_SYNC_MASK (0xC0000000U)
+#define I2S_RCR2_SYNC_SHIFT (30U)
+#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
+
+/*! @name RCR3 - SAI Receive Configuration 3 Register */
+#define I2S_RCR3_WDFL_MASK (0x1U)
+#define I2S_RCR3_WDFL_SHIFT (0U)
+#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK (0x10000U)
+#define I2S_RCR3_RCE_SHIFT (16U)
+#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
+
+/*! @name RCR4 - SAI Receive Configuration 4 Register */
+#define I2S_RCR4_FSD_MASK (0x1U)
+#define I2S_RCR4_FSD_SHIFT (0U)
+#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
+#define I2S_RCR4_FSP_MASK (0x2U)
+#define I2S_RCR4_FSP_SHIFT (1U)
+#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
+#define I2S_RCR4_FSE_MASK (0x8U)
+#define I2S_RCR4_FSE_SHIFT (3U)
+#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
+#define I2S_RCR4_MF_MASK (0x10U)
+#define I2S_RCR4_MF_SHIFT (4U)
+#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
+#define I2S_RCR4_SYWD_MASK (0x1F00U)
+#define I2S_RCR4_SYWD_SHIFT (8U)
+#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK (0x10000U)
+#define I2S_RCR4_FRSZ_SHIFT (16U)
+#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
+
+/*! @name RCR5 - SAI Receive Configuration 5 Register */
+#define I2S_RCR5_FBT_MASK (0x1F00U)
+#define I2S_RCR5_FBT_SHIFT (8U)
+#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK (0x1F0000U)
+#define I2S_RCR5_W0W_SHIFT (16U)
+#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK (0x1F000000U)
+#define I2S_RCR5_WNW_SHIFT (24U)
+#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
+
+/*! @name RDR - SAI Receive Data Register */
+#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
+#define I2S_RDR_RDR_SHIFT (0U)
+#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
+
+/* The count of I2S_RDR */
+#define I2S_RDR_COUNT (1U)
+
+/*! @name RMR - SAI Receive Mask Register */
+#define I2S_RMR_RWM_MASK (0x3U)
+#define I2S_RMR_RWM_SHIFT (0U)
+#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
+
+/*! @name MCR - SAI MCLK Control Register */
+#define I2S_MCR_MICS_MASK (0x3000000U)
+#define I2S_MCR_MICS_SHIFT (24U)
+#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK (0x40000000U)
+#define I2S_MCR_MOE_SHIFT (30U)
+#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
+#define I2S_MCR_DUF_MASK (0x80000000U)
+#define I2S_MCR_DUF_SHIFT (31U)
+#define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
+
+/*! @name MDR - SAI MCLK Divide Register */
+#define I2S_MDR_DIVIDE_MASK (0xFFFU)
+#define I2S_MDR_DIVIDE_SHIFT (0U)
+#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK (0xFF000U)
+#define I2S_MDR_FRACT_SHIFT (12U)
+#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0 ((I2S_Type *)I2S0_BASE)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS { I2S0_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS { I2S0 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_RX_IRQS { I2S0_IRQn }
+#define I2S_TX_IRQS { I2S0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
+ __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
+ __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
+ __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
+ __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
+ __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
+ __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
+ __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
+ __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
+ __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
+} LLWU_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/*! @name PE1 - LLWU Pin Enable 1 register */
+#define LLWU_PE1_WUPE0_MASK (0x3U)
+#define LLWU_PE1_WUPE0_SHIFT (0U)
+#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK (0xCU)
+#define LLWU_PE1_WUPE1_SHIFT (2U)
+#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK (0x30U)
+#define LLWU_PE1_WUPE2_SHIFT (4U)
+#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK (0xC0U)
+#define LLWU_PE1_WUPE3_SHIFT (6U)
+#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
+
+/*! @name PE2 - LLWU Pin Enable 2 register */
+#define LLWU_PE2_WUPE4_MASK (0x3U)
+#define LLWU_PE2_WUPE4_SHIFT (0U)
+#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK (0xCU)
+#define LLWU_PE2_WUPE5_SHIFT (2U)
+#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK (0x30U)
+#define LLWU_PE2_WUPE6_SHIFT (4U)
+#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK (0xC0U)
+#define LLWU_PE2_WUPE7_SHIFT (6U)
+#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
+
+/*! @name PE3 - LLWU Pin Enable 3 register */
+#define LLWU_PE3_WUPE8_MASK (0x3U)
+#define LLWU_PE3_WUPE8_SHIFT (0U)
+#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK (0xCU)
+#define LLWU_PE3_WUPE9_SHIFT (2U)
+#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK (0x30U)
+#define LLWU_PE3_WUPE10_SHIFT (4U)
+#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK (0xC0U)
+#define LLWU_PE3_WUPE11_SHIFT (6U)
+#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
+
+/*! @name PE4 - LLWU Pin Enable 4 register */
+#define LLWU_PE4_WUPE12_MASK (0x3U)
+#define LLWU_PE4_WUPE12_SHIFT (0U)
+#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK (0xCU)
+#define LLWU_PE4_WUPE13_SHIFT (2U)
+#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK (0x30U)
+#define LLWU_PE4_WUPE14_SHIFT (4U)
+#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK (0xC0U)
+#define LLWU_PE4_WUPE15_SHIFT (6U)
+#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
+
+/*! @name ME - LLWU Module Enable register */
+#define LLWU_ME_WUME0_MASK (0x1U)
+#define LLWU_ME_WUME0_SHIFT (0U)
+#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
+#define LLWU_ME_WUME1_MASK (0x2U)
+#define LLWU_ME_WUME1_SHIFT (1U)
+#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
+#define LLWU_ME_WUME2_MASK (0x4U)
+#define LLWU_ME_WUME2_SHIFT (2U)
+#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
+#define LLWU_ME_WUME3_MASK (0x8U)
+#define LLWU_ME_WUME3_SHIFT (3U)
+#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
+#define LLWU_ME_WUME4_MASK (0x10U)
+#define LLWU_ME_WUME4_SHIFT (4U)
+#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
+#define LLWU_ME_WUME5_MASK (0x20U)
+#define LLWU_ME_WUME5_SHIFT (5U)
+#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
+#define LLWU_ME_WUME6_MASK (0x40U)
+#define LLWU_ME_WUME6_SHIFT (6U)
+#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
+#define LLWU_ME_WUME7_MASK (0x80U)
+#define LLWU_ME_WUME7_SHIFT (7U)
+#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
+
+/*! @name F1 - LLWU Flag 1 register */
+#define LLWU_F1_WUF0_MASK (0x1U)
+#define LLWU_F1_WUF0_SHIFT (0U)
+#define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
+#define LLWU_F1_WUF1_MASK (0x2U)
+#define LLWU_F1_WUF1_SHIFT (1U)
+#define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
+#define LLWU_F1_WUF2_MASK (0x4U)
+#define LLWU_F1_WUF2_SHIFT (2U)
+#define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
+#define LLWU_F1_WUF3_MASK (0x8U)
+#define LLWU_F1_WUF3_SHIFT (3U)
+#define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
+#define LLWU_F1_WUF4_MASK (0x10U)
+#define LLWU_F1_WUF4_SHIFT (4U)
+#define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
+#define LLWU_F1_WUF5_MASK (0x20U)
+#define LLWU_F1_WUF5_SHIFT (5U)
+#define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
+#define LLWU_F1_WUF6_MASK (0x40U)
+#define LLWU_F1_WUF6_SHIFT (6U)
+#define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
+#define LLWU_F1_WUF7_MASK (0x80U)
+#define LLWU_F1_WUF7_SHIFT (7U)
+#define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
+
+/*! @name F2 - LLWU Flag 2 register */
+#define LLWU_F2_WUF8_MASK (0x1U)
+#define LLWU_F2_WUF8_SHIFT (0U)
+#define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
+#define LLWU_F2_WUF9_MASK (0x2U)
+#define LLWU_F2_WUF9_SHIFT (1U)
+#define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
+#define LLWU_F2_WUF10_MASK (0x4U)
+#define LLWU_F2_WUF10_SHIFT (2U)
+#define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
+#define LLWU_F2_WUF11_MASK (0x8U)
+#define LLWU_F2_WUF11_SHIFT (3U)
+#define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
+#define LLWU_F2_WUF12_MASK (0x10U)
+#define LLWU_F2_WUF12_SHIFT (4U)
+#define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
+#define LLWU_F2_WUF13_MASK (0x20U)
+#define LLWU_F2_WUF13_SHIFT (5U)
+#define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
+#define LLWU_F2_WUF14_MASK (0x40U)
+#define LLWU_F2_WUF14_SHIFT (6U)
+#define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
+#define LLWU_F2_WUF15_MASK (0x80U)
+#define LLWU_F2_WUF15_SHIFT (7U)
+#define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
+
+/*! @name F3 - LLWU Flag 3 register */
+#define LLWU_F3_MWUF0_MASK (0x1U)
+#define LLWU_F3_MWUF0_SHIFT (0U)
+#define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
+#define LLWU_F3_MWUF1_MASK (0x2U)
+#define LLWU_F3_MWUF1_SHIFT (1U)
+#define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
+#define LLWU_F3_MWUF2_MASK (0x4U)
+#define LLWU_F3_MWUF2_SHIFT (2U)
+#define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
+#define LLWU_F3_MWUF3_MASK (0x8U)
+#define LLWU_F3_MWUF3_SHIFT (3U)
+#define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
+#define LLWU_F3_MWUF4_MASK (0x10U)
+#define LLWU_F3_MWUF4_SHIFT (4U)
+#define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
+#define LLWU_F3_MWUF5_MASK (0x20U)
+#define LLWU_F3_MWUF5_SHIFT (5U)
+#define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
+#define LLWU_F3_MWUF6_MASK (0x40U)
+#define LLWU_F3_MWUF6_SHIFT (6U)
+#define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
+#define LLWU_F3_MWUF7_MASK (0x80U)
+#define LLWU_F3_MWUF7_SHIFT (7U)
+#define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
+
+/*! @name FILT1 - LLWU Pin Filter 1 register */
+#define LLWU_FILT1_FILTSEL_MASK (0xFU)
+#define LLWU_FILT1_FILTSEL_SHIFT (0U)
+#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK (0x60U)
+#define LLWU_FILT1_FILTE_SHIFT (5U)
+#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK (0x80U)
+#define LLWU_FILT1_FILTF_SHIFT (7U)
+#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
+
+/*! @name FILT2 - LLWU Pin Filter 2 register */
+#define LLWU_FILT2_FILTSEL_MASK (0xFU)
+#define LLWU_FILT2_FILTSEL_SHIFT (0U)
+#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK (0x60U)
+#define LLWU_FILT2_FILTE_SHIFT (5U)
+#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK (0x80U)
+#define LLWU_FILT2_FILTF_SHIFT (7U)
+#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU ((LLWU_Type *)LLWU_BASE)
+/** Array initializer of LLWU peripheral base addresses */
+#define LLWU_BASE_ADDRS { LLWU_BASE }
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASE_PTRS { LLWU }
+/** Interrupt vectors for the LLWU peripheral type */
+#define LLWU_IRQS { LLWU_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
+ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
+ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
+ __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/*! @name CSR - Low Power Timer Control Status Register */
+#define LPTMR_CSR_TEN_MASK (0x1U)
+#define LPTMR_CSR_TEN_SHIFT (0U)
+#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
+#define LPTMR_CSR_TMS_MASK (0x2U)
+#define LPTMR_CSR_TMS_SHIFT (1U)
+#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
+#define LPTMR_CSR_TFC_MASK (0x4U)
+#define LPTMR_CSR_TFC_SHIFT (2U)
+#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
+#define LPTMR_CSR_TPP_MASK (0x8U)
+#define LPTMR_CSR_TPP_SHIFT (3U)
+#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
+#define LPTMR_CSR_TPS_MASK (0x30U)
+#define LPTMR_CSR_TPS_SHIFT (4U)
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK (0x40U)
+#define LPTMR_CSR_TIE_SHIFT (6U)
+#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
+#define LPTMR_CSR_TCF_MASK (0x80U)
+#define LPTMR_CSR_TCF_SHIFT (7U)
+#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
+
+/*! @name PSR - Low Power Timer Prescale Register */
+#define LPTMR_PSR_PCS_MASK (0x3U)
+#define LPTMR_PSR_PCS_SHIFT (0U)
+#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK (0x4U)
+#define LPTMR_PSR_PBYP_SHIFT (2U)
+#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
+#define LPTMR_PSR_PRESCALE_MASK (0x78U)
+#define LPTMR_PSR_PRESCALE_SHIFT (3U)
+#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
+
+/*! @name CMR - Low Power Timer Compare Register */
+#define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
+#define LPTMR_CMR_COMPARE_SHIFT (0U)
+#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
+
+/*! @name CNR - Low Power Timer Counter Register */
+#define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
+#define LPTMR_CNR_COUNTER_SHIFT (0U)
+#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
+/** Array initializer of LPTMR peripheral base addresses */
+#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASE_PTRS { LPTMR0 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS { LPTMR0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
+ __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
+ __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
+ __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
+ __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
+ __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
+ __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+ __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+ __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
+ __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
+ __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
+ __I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */
+} MCG_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MCG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/*! @name C1 - MCG Control 1 Register */
+#define MCG_C1_IREFSTEN_MASK (0x1U)
+#define MCG_C1_IREFSTEN_SHIFT (0U)
+#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
+#define MCG_C1_IRCLKEN_MASK (0x2U)
+#define MCG_C1_IRCLKEN_SHIFT (1U)
+#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
+#define MCG_C1_IREFS_MASK (0x4U)
+#define MCG_C1_IREFS_SHIFT (2U)
+#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
+#define MCG_C1_FRDIV_MASK (0x38U)
+#define MCG_C1_FRDIV_SHIFT (3U)
+#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK (0xC0U)
+#define MCG_C1_CLKS_SHIFT (6U)
+#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
+
+/*! @name C2 - MCG Control 2 Register */
+#define MCG_C2_IRCS_MASK (0x1U)
+#define MCG_C2_IRCS_SHIFT (0U)
+#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
+#define MCG_C2_LP_MASK (0x2U)
+#define MCG_C2_LP_SHIFT (1U)
+#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
+#define MCG_C2_EREFS0_MASK (0x4U)
+#define MCG_C2_EREFS0_SHIFT (2U)
+#define MCG_C2_EREFS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS0_SHIFT)) & MCG_C2_EREFS0_MASK)
+#define MCG_C2_HGO0_MASK (0x8U)
+#define MCG_C2_HGO0_SHIFT (3U)
+#define MCG_C2_HGO0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO0_SHIFT)) & MCG_C2_HGO0_MASK)
+#define MCG_C2_RANGE0_MASK (0x30U)
+#define MCG_C2_RANGE0_SHIFT (4U)
+#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE0_SHIFT)) & MCG_C2_RANGE0_MASK)
+#define MCG_C2_FCFTRIM_MASK (0x40U)
+#define MCG_C2_FCFTRIM_SHIFT (6U)
+#define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
+#define MCG_C2_LOCRE0_MASK (0x80U)
+#define MCG_C2_LOCRE0_SHIFT (7U)
+#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
+
+/*! @name C3 - MCG Control 3 Register */
+#define MCG_C3_SCTRIM_MASK (0xFFU)
+#define MCG_C3_SCTRIM_SHIFT (0U)
+#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
+
+/*! @name C4 - MCG Control 4 Register */
+#define MCG_C4_SCFTRIM_MASK (0x1U)
+#define MCG_C4_SCFTRIM_SHIFT (0U)
+#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
+#define MCG_C4_FCTRIM_MASK (0x1EU)
+#define MCG_C4_FCTRIM_SHIFT (1U)
+#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK (0x60U)
+#define MCG_C4_DRST_DRS_SHIFT (5U)
+#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK (0x80U)
+#define MCG_C4_DMX32_SHIFT (7U)
+#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
+
+/*! @name C5 - MCG Control 5 Register */
+#define MCG_C5_PRDIV0_MASK (0x1FU)
+#define MCG_C5_PRDIV0_SHIFT (0U)
+#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK (0x20U)
+#define MCG_C5_PLLSTEN0_SHIFT (5U)
+#define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)
+#define MCG_C5_PLLCLKEN0_MASK (0x40U)
+#define MCG_C5_PLLCLKEN0_SHIFT (6U)
+#define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)
+
+/*! @name C6 - MCG Control 6 Register */
+#define MCG_C6_VDIV0_MASK (0x1FU)
+#define MCG_C6_VDIV0_SHIFT (0U)
+#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK (0x20U)
+#define MCG_C6_CME0_SHIFT (5U)
+#define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
+#define MCG_C6_PLLS_MASK (0x40U)
+#define MCG_C6_PLLS_SHIFT (6U)
+#define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
+#define MCG_C6_LOLIE0_MASK (0x80U)
+#define MCG_C6_LOLIE0_SHIFT (7U)
+#define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
+
+/*! @name S - MCG Status Register */
+#define MCG_S_IRCST_MASK (0x1U)
+#define MCG_S_IRCST_SHIFT (0U)
+#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
+#define MCG_S_OSCINIT0_MASK (0x2U)
+#define MCG_S_OSCINIT0_SHIFT (1U)
+#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
+#define MCG_S_CLKST_MASK (0xCU)
+#define MCG_S_CLKST_SHIFT (2U)
+#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK (0x10U)
+#define MCG_S_IREFST_SHIFT (4U)
+#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
+#define MCG_S_PLLST_MASK (0x20U)
+#define MCG_S_PLLST_SHIFT (5U)
+#define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
+#define MCG_S_LOCK0_MASK (0x40U)
+#define MCG_S_LOCK0_SHIFT (6U)
+#define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
+#define MCG_S_LOLS0_MASK (0x80U)
+#define MCG_S_LOLS0_SHIFT (7U)
+#define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
+
+/*! @name SC - MCG Status and Control Register */
+#define MCG_SC_LOCS0_MASK (0x1U)
+#define MCG_SC_LOCS0_SHIFT (0U)
+#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
+#define MCG_SC_FCRDIV_MASK (0xEU)
+#define MCG_SC_FCRDIV_SHIFT (1U)
+#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK (0x10U)
+#define MCG_SC_FLTPRSRV_SHIFT (4U)
+#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
+#define MCG_SC_ATMF_MASK (0x20U)
+#define MCG_SC_ATMF_SHIFT (5U)
+#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
+#define MCG_SC_ATMS_MASK (0x40U)
+#define MCG_SC_ATMS_SHIFT (6U)
+#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
+#define MCG_SC_ATME_MASK (0x80U)
+#define MCG_SC_ATME_SHIFT (7U)
+#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
+
+/*! @name ATCVH - MCG Auto Trim Compare Value High Register */
+#define MCG_ATCVH_ATCVH_MASK (0xFFU)
+#define MCG_ATCVH_ATCVH_SHIFT (0U)
+#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
+
+/*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
+#define MCG_ATCVL_ATCVL_MASK (0xFFU)
+#define MCG_ATCVL_ATCVL_SHIFT (0U)
+#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
+
+/*! @name C7 - MCG Control 7 Register */
+#define MCG_C7_OSCSEL_MASK (0x1U)
+#define MCG_C7_OSCSEL_SHIFT (0U)
+#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
+
+/*! @name C8 - MCG Control 8 Register */
+#define MCG_C8_LOLRE_MASK (0x40U)
+#define MCG_C8_LOLRE_SHIFT (6U)
+#define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG ((MCG_Type *)MCG_BASE)
+/** Array initializer of MCG peripheral base addresses */
+#define MCG_BASE_ADDRS { MCG_BASE }
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASE_PTRS { MCG }
+/** Interrupt vectors for the MCG peripheral type */
+#define MCG_IRQS { MCG_IRQn }
+/* MCG C2[EREFS] backward compatibility */
+#define MCG_C2_EREFS_MASK (MCG_C2_EREFS0_MASK)
+#define MCG_C2_EREFS_SHIFT (MCG_C2_EREFS0_SHIFT)
+#define MCG_C2_EREFS_WIDTH (MCG_C2_EREFS0_WIDTH)
+#define MCG_C2_EREFS(x) (MCG_C2_EREFS0(x))
+
+/* MCG C2[HGO] backward compatibility */
+#define MCG_C2_HGO_MASK (MCG_C2_HGO0_MASK)
+#define MCG_C2_HGO_SHIFT (MCG_C2_HGO0_SHIFT)
+#define MCG_C2_HGO_WIDTH (MCG_C2_HGO0_WIDTH)
+#define MCG_C2_HGO(x) (MCG_C2_HGO0(x))
+
+/* MCG C2[RANGE] backward compatibility */
+#define MCG_C2_RANGE_MASK (MCG_C2_RANGE0_MASK)
+#define MCG_C2_RANGE_SHIFT (MCG_C2_RANGE0_SHIFT)
+#define MCG_C2_RANGE_WIDTH (MCG_C2_RANGE0_WIDTH)
+#define MCG_C2_RANGE(x) (MCG_C2_RANGE0(x))
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[8];
+ __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+ __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+ __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
+ uint8_t RESERVED_1[48];
+ __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
+} MCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
+#define MCM_PLASC_ASC_MASK (0xFFU)
+#define MCM_PLASC_ASC_SHIFT (0U)
+#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
+
+/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
+#define MCM_PLAMC_AMC_MASK (0xFFU)
+#define MCM_PLAMC_AMC_SHIFT (0U)
+#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
+
+/*! @name PLACR - Platform Control Register */
+#define MCM_PLACR_ARB_MASK (0x200U)
+#define MCM_PLACR_ARB_SHIFT (9U)
+#define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK)
+#define MCM_PLACR_CFCC_MASK (0x400U)
+#define MCM_PLACR_CFCC_SHIFT (10U)
+#define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK)
+#define MCM_PLACR_DFCDA_MASK (0x800U)
+#define MCM_PLACR_DFCDA_SHIFT (11U)
+#define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK)
+#define MCM_PLACR_DFCIC_MASK (0x1000U)
+#define MCM_PLACR_DFCIC_SHIFT (12U)
+#define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK)
+#define MCM_PLACR_DFCC_MASK (0x2000U)
+#define MCM_PLACR_DFCC_SHIFT (13U)
+#define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK)
+#define MCM_PLACR_EFDS_MASK (0x4000U)
+#define MCM_PLACR_EFDS_SHIFT (14U)
+#define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK)
+#define MCM_PLACR_DFCS_MASK (0x8000U)
+#define MCM_PLACR_DFCS_SHIFT (15U)
+#define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK)
+#define MCM_PLACR_ESFC_MASK (0x10000U)
+#define MCM_PLACR_ESFC_SHIFT (16U)
+#define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK)
+
+/*! @name CPO - Compute Operation Control Register */
+#define MCM_CPO_CPOREQ_MASK (0x1U)
+#define MCM_CPO_CPOREQ_SHIFT (0U)
+#define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
+#define MCM_CPO_CPOACK_MASK (0x2U)
+#define MCM_CPO_CPOACK_SHIFT (1U)
+#define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
+#define MCM_CPO_CPOWOI_MASK (0x4U)
+#define MCM_CPO_CPOWOI_SHIFT (2U)
+#define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE (0xF0003000u)
+/** Peripheral MCM base pointer */
+#define MCM ((MCM_Type *)MCM_BASE)
+/** Array initializer of MCM peripheral base addresses */
+#define MCM_BASE_ADDRS { MCM_BASE }
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASE_PTRS { MCM }
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
+ * @{
+ */
+
+/** MTB - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
+ __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
+ __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
+ __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
+ uint8_t RESERVED_0[3824];
+ __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
+ uint8_t RESERVED_1[156];
+ __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
+ __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
+ uint8_t RESERVED_2[8];
+ __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
+ __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
+ __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
+ __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
+ uint8_t RESERVED_3[8];
+ __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
+ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
+ __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
+ __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
+ __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
+ __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
+ __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
+ __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
+ __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
+ __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MTB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Register_Masks MTB Register Masks
+ * @{
+ */
+
+/*! @name POSITION - MTB Position Register */
+#define MTB_POSITION_WRAP_MASK (0x4U)
+#define MTB_POSITION_WRAP_SHIFT (2U)
+#define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK)
+#define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U)
+#define MTB_POSITION_POINTER_SHIFT (3U)
+#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK)
+
+/*! @name MASTER - MTB Master Register */
+#define MTB_MASTER_MASK_MASK (0x1FU)
+#define MTB_MASTER_MASK_SHIFT (0U)
+#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK)
+#define MTB_MASTER_TSTARTEN_MASK (0x20U)
+#define MTB_MASTER_TSTARTEN_SHIFT (5U)
+#define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK)
+#define MTB_MASTER_TSTOPEN_MASK (0x40U)
+#define MTB_MASTER_TSTOPEN_SHIFT (6U)
+#define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK)
+#define MTB_MASTER_SFRWPRIV_MASK (0x80U)
+#define MTB_MASTER_SFRWPRIV_SHIFT (7U)
+#define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK)
+#define MTB_MASTER_RAMPRIV_MASK (0x100U)
+#define MTB_MASTER_RAMPRIV_SHIFT (8U)
+#define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK)
+#define MTB_MASTER_HALTREQ_MASK (0x200U)
+#define MTB_MASTER_HALTREQ_SHIFT (9U)
+#define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK)
+#define MTB_MASTER_EN_MASK (0x80000000U)
+#define MTB_MASTER_EN_SHIFT (31U)
+#define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK)
+
+/*! @name FLOW - MTB Flow Register */
+#define MTB_FLOW_AUTOSTOP_MASK (0x1U)
+#define MTB_FLOW_AUTOSTOP_SHIFT (0U)
+#define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK)
+#define MTB_FLOW_AUTOHALT_MASK (0x2U)
+#define MTB_FLOW_AUTOHALT_SHIFT (1U)
+#define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK)
+#define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U)
+#define MTB_FLOW_WATERMARK_SHIFT (3U)
+#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK)
+
+/*! @name BASE - MTB Base Register */
+#define MTB_BASE_BASEADDR_MASK (0xFFFFFFFFU)
+#define MTB_BASE_BASEADDR_SHIFT (0U)
+#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK)
+
+/*! @name MODECTRL - Integration Mode Control Register */
+#define MTB_MODECTRL_MODECTRL_MASK (0xFFFFFFFFU)
+#define MTB_MODECTRL_MODECTRL_SHIFT (0U)
+#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK)
+
+/*! @name TAGSET - Claim TAG Set Register */
+#define MTB_TAGSET_TAGSET_MASK (0xFFFFFFFFU)
+#define MTB_TAGSET_TAGSET_SHIFT (0U)
+#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK)
+
+/*! @name TAGCLEAR - Claim TAG Clear Register */
+#define MTB_TAGCLEAR_TAGCLEAR_MASK (0xFFFFFFFFU)
+#define MTB_TAGCLEAR_TAGCLEAR_SHIFT (0U)
+#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK)
+
+/*! @name LOCKACCESS - Lock Access Register */
+#define MTB_LOCKACCESS_LOCKACCESS_MASK (0xFFFFFFFFU)
+#define MTB_LOCKACCESS_LOCKACCESS_SHIFT (0U)
+#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK)
+
+/*! @name LOCKSTAT - Lock Status Register */
+#define MTB_LOCKSTAT_LOCKSTAT_MASK (0xFFFFFFFFU)
+#define MTB_LOCKSTAT_LOCKSTAT_SHIFT (0U)
+#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK)
+
+/*! @name AUTHSTAT - Authentication Status Register */
+#define MTB_AUTHSTAT_BIT0_MASK (0x1U)
+#define MTB_AUTHSTAT_BIT0_SHIFT (0U)
+#define MTB_AUTHSTAT_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK)
+#define MTB_AUTHSTAT_BIT1_MASK (0x2U)
+#define MTB_AUTHSTAT_BIT1_SHIFT (1U)
+#define MTB_AUTHSTAT_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT1_SHIFT)) & MTB_AUTHSTAT_BIT1_MASK)
+#define MTB_AUTHSTAT_BIT2_MASK (0x4U)
+#define MTB_AUTHSTAT_BIT2_SHIFT (2U)
+#define MTB_AUTHSTAT_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK)
+#define MTB_AUTHSTAT_BIT3_MASK (0x8U)
+#define MTB_AUTHSTAT_BIT3_SHIFT (3U)
+#define MTB_AUTHSTAT_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT3_SHIFT)) & MTB_AUTHSTAT_BIT3_MASK)
+
+/*! @name DEVICEARCH - Device Architecture Register */
+#define MTB_DEVICEARCH_DEVICEARCH_MASK (0xFFFFFFFFU)
+#define MTB_DEVICEARCH_DEVICEARCH_SHIFT (0U)
+#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK)
+
+/*! @name DEVICECFG - Device Configuration Register */
+#define MTB_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU)
+#define MTB_DEVICECFG_DEVICECFG_SHIFT (0U)
+#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK)
+
+/*! @name DEVICETYPID - Device Type Identifier Register */
+#define MTB_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU)
+#define MTB_DEVICETYPID_DEVICETYPID_SHIFT (0U)
+#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK)
+
+/*! @name PERIPHID4 - Peripheral ID Register */
+#define MTB_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTB_PERIPHID4_PERIPHID_SHIFT (0U)
+#define MTB_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID4_PERIPHID_SHIFT)) & MTB_PERIPHID4_PERIPHID_MASK)
+
+/*! @name PERIPHID5 - Peripheral ID Register */
+#define MTB_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTB_PERIPHID5_PERIPHID_SHIFT (0U)
+#define MTB_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID5_PERIPHID_SHIFT)) & MTB_PERIPHID5_PERIPHID_MASK)
+
+/*! @name PERIPHID6 - Peripheral ID Register */
+#define MTB_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTB_PERIPHID6_PERIPHID_SHIFT (0U)
+#define MTB_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID6_PERIPHID_SHIFT)) & MTB_PERIPHID6_PERIPHID_MASK)
+
+/*! @name PERIPHID7 - Peripheral ID Register */
+#define MTB_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTB_PERIPHID7_PERIPHID_SHIFT (0U)
+#define MTB_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID7_PERIPHID_SHIFT)) & MTB_PERIPHID7_PERIPHID_MASK)
+
+/*! @name PERIPHID0 - Peripheral ID Register */
+#define MTB_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTB_PERIPHID0_PERIPHID_SHIFT (0U)
+#define MTB_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID0_PERIPHID_SHIFT)) & MTB_PERIPHID0_PERIPHID_MASK)
+
+/*! @name PERIPHID1 - Peripheral ID Register */
+#define MTB_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTB_PERIPHID1_PERIPHID_SHIFT (0U)
+#define MTB_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID1_PERIPHID_SHIFT)) & MTB_PERIPHID1_PERIPHID_MASK)
+
+/*! @name PERIPHID2 - Peripheral ID Register */
+#define MTB_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTB_PERIPHID2_PERIPHID_SHIFT (0U)
+#define MTB_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID2_PERIPHID_SHIFT)) & MTB_PERIPHID2_PERIPHID_MASK)
+
+/*! @name PERIPHID3 - Peripheral ID Register */
+#define MTB_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTB_PERIPHID3_PERIPHID_SHIFT (0U)
+#define MTB_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID3_PERIPHID_SHIFT)) & MTB_PERIPHID3_PERIPHID_MASK)
+
+/*! @name COMPID - Component ID Register */
+#define MTB_COMPID_COMPID_MASK (0xFFFFFFFFU)
+#define MTB_COMPID_COMPID_SHIFT (0U)
+#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK)
+
+/* The count of MTB_COMPID */
+#define MTB_COMPID_COUNT (4U)
+
+
+/*!
+ * @}
+ */ /* end of group MTB_Register_Masks */
+
+
+/* MTB - Peripheral instance base addresses */
+/** Peripheral MTB base address */
+#define MTB_BASE (0xF0000000u)
+/** Peripheral MTB base pointer */
+#define MTB ((MTB_Type *)MTB_BASE)
+/** Array initializer of MTB peripheral base addresses */
+#define MTB_BASE_ADDRS { MTB_BASE }
+/** Array initializer of MTB peripheral base pointers */
+#define MTB_BASE_PTRS { MTB }
+
+/*!
+ * @}
+ */ /* end of group MTB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
+ * @{
+ */
+
+/** MTBDWT - Register Layout Typedef */
+typedef struct {
+ __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[28];
+ struct { /* offset: 0x20, array step: 0x10 */
+ __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
+ __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
+ __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
+ uint8_t RESERVED_0[4];
+ } COMPARATOR[2];
+ uint8_t RESERVED_1[448];
+ __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
+ uint8_t RESERVED_2[3524];
+ __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
+ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
+ __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
+ __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
+ __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
+ __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
+ __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
+ __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
+ __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
+ __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTBDWT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
+ * @{
+ */
+
+/*! @name CTRL - MTB DWT Control Register */
+#define MTBDWT_CTRL_DWTCFGCTRL_MASK (0xFFFFFFFU)
+#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT (0U)
+#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_DWTCFGCTRL_SHIFT)) & MTBDWT_CTRL_DWTCFGCTRL_MASK)
+#define MTBDWT_CTRL_NUMCMP_MASK (0xF0000000U)
+#define MTBDWT_CTRL_NUMCMP_SHIFT (28U)
+#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_NUMCMP_SHIFT)) & MTBDWT_CTRL_NUMCMP_MASK)
+
+/*! @name COMP - MTB_DWT Comparator Register */
+#define MTBDWT_COMP_COMP_MASK (0xFFFFFFFFU)
+#define MTBDWT_COMP_COMP_SHIFT (0U)
+#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMP_COMP_SHIFT)) & MTBDWT_COMP_COMP_MASK)
+
+/* The count of MTBDWT_COMP */
+#define MTBDWT_COMP_COUNT (2U)
+
+/*! @name MASK - MTB_DWT Comparator Mask Register */
+#define MTBDWT_MASK_MASK_MASK (0x1FU)
+#define MTBDWT_MASK_MASK_SHIFT (0U)
+#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_MASK_MASK_SHIFT)) & MTBDWT_MASK_MASK_MASK)
+
+/* The count of MTBDWT_MASK */
+#define MTBDWT_MASK_COUNT (2U)
+
+/*! @name FCT - MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1 */
+#define MTBDWT_FCT_FUNCTION_MASK (0xFU)
+#define MTBDWT_FCT_FUNCTION_SHIFT (0U)
+#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_FUNCTION_SHIFT)) & MTBDWT_FCT_FUNCTION_MASK)
+#define MTBDWT_FCT_DATAVMATCH_MASK (0x100U)
+#define MTBDWT_FCT_DATAVMATCH_SHIFT (8U)
+#define MTBDWT_FCT_DATAVMATCH(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVMATCH_SHIFT)) & MTBDWT_FCT_DATAVMATCH_MASK)
+#define MTBDWT_FCT_DATAVSIZE_MASK (0xC00U)
+#define MTBDWT_FCT_DATAVSIZE_SHIFT (10U)
+#define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVSIZE_SHIFT)) & MTBDWT_FCT_DATAVSIZE_MASK)
+#define MTBDWT_FCT_DATAVADDR0_MASK (0xF000U)
+#define MTBDWT_FCT_DATAVADDR0_SHIFT (12U)
+#define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVADDR0_SHIFT)) & MTBDWT_FCT_DATAVADDR0_MASK)
+#define MTBDWT_FCT_MATCHED_MASK (0x1000000U)
+#define MTBDWT_FCT_MATCHED_SHIFT (24U)
+#define MTBDWT_FCT_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_MATCHED_SHIFT)) & MTBDWT_FCT_MATCHED_MASK)
+
+/* The count of MTBDWT_FCT */
+#define MTBDWT_FCT_COUNT (2U)
+
+/*! @name TBCTRL - MTB_DWT Trace Buffer Control Register */
+#define MTBDWT_TBCTRL_ACOMP0_MASK (0x1U)
+#define MTBDWT_TBCTRL_ACOMP0_SHIFT (0U)
+#define MTBDWT_TBCTRL_ACOMP0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP0_SHIFT)) & MTBDWT_TBCTRL_ACOMP0_MASK)
+#define MTBDWT_TBCTRL_ACOMP1_MASK (0x2U)
+#define MTBDWT_TBCTRL_ACOMP1_SHIFT (1U)
+#define MTBDWT_TBCTRL_ACOMP1(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP1_SHIFT)) & MTBDWT_TBCTRL_ACOMP1_MASK)
+#define MTBDWT_TBCTRL_NUMCOMP_MASK (0xF0000000U)
+#define MTBDWT_TBCTRL_NUMCOMP_SHIFT (28U)
+#define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_NUMCOMP_SHIFT)) & MTBDWT_TBCTRL_NUMCOMP_MASK)
+
+/*! @name DEVICECFG - Device Configuration Register */
+#define MTBDWT_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU)
+#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT (0U)
+#define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICECFG_DEVICECFG_SHIFT)) & MTBDWT_DEVICECFG_DEVICECFG_MASK)
+
+/*! @name DEVICETYPID - Device Type Identifier Register */
+#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU)
+#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT (0U)
+#define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
+
+/*! @name PERIPHID4 - Peripheral ID Register */
+#define MTBDWT_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID4_PERIPHID_SHIFT (0U)
+#define MTBDWT_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID4_PERIPHID_SHIFT)) & MTBDWT_PERIPHID4_PERIPHID_MASK)
+
+/*! @name PERIPHID5 - Peripheral ID Register */
+#define MTBDWT_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID5_PERIPHID_SHIFT (0U)
+#define MTBDWT_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID5_PERIPHID_SHIFT)) & MTBDWT_PERIPHID5_PERIPHID_MASK)
+
+/*! @name PERIPHID6 - Peripheral ID Register */
+#define MTBDWT_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID6_PERIPHID_SHIFT (0U)
+#define MTBDWT_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID6_PERIPHID_SHIFT)) & MTBDWT_PERIPHID6_PERIPHID_MASK)
+
+/*! @name PERIPHID7 - Peripheral ID Register */
+#define MTBDWT_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID7_PERIPHID_SHIFT (0U)
+#define MTBDWT_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID7_PERIPHID_SHIFT)) & MTBDWT_PERIPHID7_PERIPHID_MASK)
+
+/*! @name PERIPHID0 - Peripheral ID Register */
+#define MTBDWT_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID0_PERIPHID_SHIFT (0U)
+#define MTBDWT_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID0_PERIPHID_SHIFT)) & MTBDWT_PERIPHID0_PERIPHID_MASK)
+
+/*! @name PERIPHID1 - Peripheral ID Register */
+#define MTBDWT_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID1_PERIPHID_SHIFT (0U)
+#define MTBDWT_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID1_PERIPHID_SHIFT)) & MTBDWT_PERIPHID1_PERIPHID_MASK)
+
+/*! @name PERIPHID2 - Peripheral ID Register */
+#define MTBDWT_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID2_PERIPHID_SHIFT (0U)
+#define MTBDWT_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID2_PERIPHID_SHIFT)) & MTBDWT_PERIPHID2_PERIPHID_MASK)
+
+/*! @name PERIPHID3 - Peripheral ID Register */
+#define MTBDWT_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID3_PERIPHID_SHIFT (0U)
+#define MTBDWT_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID3_PERIPHID_SHIFT)) & MTBDWT_PERIPHID3_PERIPHID_MASK)
+
+/*! @name COMPID - Component ID Register */
+#define MTBDWT_COMPID_COMPID_MASK (0xFFFFFFFFU)
+#define MTBDWT_COMPID_COMPID_SHIFT (0U)
+#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMPID_COMPID_SHIFT)) & MTBDWT_COMPID_COMPID_MASK)
+
+/* The count of MTBDWT_COMPID */
+#define MTBDWT_COMPID_COUNT (4U)
+
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Register_Masks */
+
+
+/* MTBDWT - Peripheral instance base addresses */
+/** Peripheral MTBDWT base address */
+#define MTBDWT_BASE (0xF0001000u)
+/** Peripheral MTBDWT base pointer */
+#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
+/** Array initializer of MTBDWT peripheral base addresses */
+#define MTBDWT_BASE_ADDRS { MTBDWT_BASE }
+/** Array initializer of MTBDWT peripheral base pointers */
+#define MTBDWT_BASE_PTRS { MTBDWT }
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+ __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
+ __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
+ __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
+ __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
+ __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
+ __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
+ __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
+ __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
+ __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+ __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+ __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+ __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+ __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
+ __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
+} NV_Type;
+
+/* ----------------------------------------------------------------------------
+ -- NV Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/*! @name BACKKEY3 - Backdoor Comparison Key 3. */
+#define NV_BACKKEY3_KEY_MASK (0xFFU)
+#define NV_BACKKEY3_KEY_SHIFT (0U)
+#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
+
+/*! @name BACKKEY2 - Backdoor Comparison Key 2. */
+#define NV_BACKKEY2_KEY_MASK (0xFFU)
+#define NV_BACKKEY2_KEY_SHIFT (0U)
+#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
+
+/*! @name BACKKEY1 - Backdoor Comparison Key 1. */
+#define NV_BACKKEY1_KEY_MASK (0xFFU)
+#define NV_BACKKEY1_KEY_SHIFT (0U)
+#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
+
+/*! @name BACKKEY0 - Backdoor Comparison Key 0. */
+#define NV_BACKKEY0_KEY_MASK (0xFFU)
+#define NV_BACKKEY0_KEY_SHIFT (0U)
+#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
+
+/*! @name BACKKEY7 - Backdoor Comparison Key 7. */
+#define NV_BACKKEY7_KEY_MASK (0xFFU)
+#define NV_BACKKEY7_KEY_SHIFT (0U)
+#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
+
+/*! @name BACKKEY6 - Backdoor Comparison Key 6. */
+#define NV_BACKKEY6_KEY_MASK (0xFFU)
+#define NV_BACKKEY6_KEY_SHIFT (0U)
+#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
+
+/*! @name BACKKEY5 - Backdoor Comparison Key 5. */
+#define NV_BACKKEY5_KEY_MASK (0xFFU)
+#define NV_BACKKEY5_KEY_SHIFT (0U)
+#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
+
+/*! @name BACKKEY4 - Backdoor Comparison Key 4. */
+#define NV_BACKKEY4_KEY_MASK (0xFFU)
+#define NV_BACKKEY4_KEY_SHIFT (0U)
+#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
+
+/*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
+#define NV_FPROT3_PROT_MASK (0xFFU)
+#define NV_FPROT3_PROT_SHIFT (0U)
+#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
+
+/*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
+#define NV_FPROT2_PROT_MASK (0xFFU)
+#define NV_FPROT2_PROT_SHIFT (0U)
+#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
+
+/*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
+#define NV_FPROT1_PROT_MASK (0xFFU)
+#define NV_FPROT1_PROT_SHIFT (0U)
+#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
+
+/*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
+#define NV_FPROT0_PROT_MASK (0xFFU)
+#define NV_FPROT0_PROT_SHIFT (0U)
+#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
+
+/*! @name FSEC - Non-volatile Flash Security Register */
+#define NV_FSEC_SEC_MASK (0x3U)
+#define NV_FSEC_SEC_SHIFT (0U)
+#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK (0xCU)
+#define NV_FSEC_FSLACC_SHIFT (2U)
+#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK (0x30U)
+#define NV_FSEC_MEEN_SHIFT (4U)
+#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK (0xC0U)
+#define NV_FSEC_KEYEN_SHIFT (6U)
+#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
+
+/*! @name FOPT - Non-volatile Flash Option Register */
+#define NV_FOPT_LPBOOT0_MASK (0x1U)
+#define NV_FOPT_LPBOOT0_SHIFT (0U)
+#define NV_FOPT_LPBOOT0(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT0_SHIFT)) & NV_FOPT_LPBOOT0_MASK)
+#define NV_FOPT_NMI_DIS_MASK (0x4U)
+#define NV_FOPT_NMI_DIS_SHIFT (2U)
+#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
+#define NV_FOPT_RESET_PIN_CFG_MASK (0x8U)
+#define NV_FOPT_RESET_PIN_CFG_SHIFT (3U)
+#define NV_FOPT_RESET_PIN_CFG(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_RESET_PIN_CFG_SHIFT)) & NV_FOPT_RESET_PIN_CFG_MASK)
+#define NV_FOPT_LPBOOT1_MASK (0x10U)
+#define NV_FOPT_LPBOOT1_SHIFT (4U)
+#define NV_FOPT_LPBOOT1(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT1_SHIFT)) & NV_FOPT_LPBOOT1_MASK)
+#define NV_FOPT_FAST_INIT_MASK (0x20U)
+#define NV_FOPT_FAST_INIT_SHIFT (5U)
+#define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFA_FlashConfig base address */
+#define FTFA_FlashConfig_BASE (0x400u)
+/** Peripheral FTFA_FlashConfig base pointer */
+#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
+/** Array initializer of NV peripheral base addresses */
+#define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASE_PTRS { FTFA_FlashConfig }
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
+} OSC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- OSC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/*! @name CR - OSC Control Register */
+#define OSC_CR_SC16P_MASK (0x1U)
+#define OSC_CR_SC16P_SHIFT (0U)
+#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
+#define OSC_CR_SC8P_MASK (0x2U)
+#define OSC_CR_SC8P_SHIFT (1U)
+#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
+#define OSC_CR_SC4P_MASK (0x4U)
+#define OSC_CR_SC4P_SHIFT (2U)
+#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
+#define OSC_CR_SC2P_MASK (0x8U)
+#define OSC_CR_SC2P_SHIFT (3U)
+#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
+#define OSC_CR_EREFSTEN_MASK (0x20U)
+#define OSC_CR_EREFSTEN_SHIFT (5U)
+#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
+#define OSC_CR_ERCLKEN_MASK (0x80U)
+#define OSC_CR_ERCLKEN_SHIFT (7U)
+#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC0 base address */
+#define OSC0_BASE (0x40065000u)
+/** Peripheral OSC0 base pointer */
+#define OSC0 ((OSC_Type *)OSC0_BASE)
+/** Array initializer of OSC peripheral base addresses */
+#define OSC_BASE_ADDRS { OSC0_BASE }
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASE_PTRS { OSC0 }
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[220];
+ __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
+ __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
+ uint8_t RESERVED_1[24];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+ __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+ __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+ } CHANNEL[2];
+} PIT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PIT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/*! @name MCR - PIT Module Control Register */
+#define PIT_MCR_FRZ_MASK (0x1U)
+#define PIT_MCR_FRZ_SHIFT (0U)
+#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
+#define PIT_MCR_MDIS_MASK (0x2U)
+#define PIT_MCR_MDIS_SHIFT (1U)
+#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
+
+/*! @name LTMR64H - PIT Upper Lifetime Timer Register */
+#define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)
+#define PIT_LTMR64H_LTH_SHIFT (0U)
+#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
+
+/*! @name LTMR64L - PIT Lower Lifetime Timer Register */
+#define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)
+#define PIT_LTMR64L_LTL_SHIFT (0U)
+#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
+
+/*! @name LDVAL - Timer Load Value Register */
+#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
+#define PIT_LDVAL_TSV_SHIFT (0U)
+#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
+
+/* The count of PIT_LDVAL */
+#define PIT_LDVAL_COUNT (2U)
+
+/*! @name CVAL - Current Timer Value Register */
+#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
+#define PIT_CVAL_TVL_SHIFT (0U)
+#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
+
+/* The count of PIT_CVAL */
+#define PIT_CVAL_COUNT (2U)
+
+/*! @name TCTRL - Timer Control Register */
+#define PIT_TCTRL_TEN_MASK (0x1U)
+#define PIT_TCTRL_TEN_SHIFT (0U)
+#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
+#define PIT_TCTRL_TIE_MASK (0x2U)
+#define PIT_TCTRL_TIE_SHIFT (1U)
+#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
+#define PIT_TCTRL_CHN_MASK (0x4U)
+#define PIT_TCTRL_CHN_SHIFT (2U)
+#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
+
+/* The count of PIT_TCTRL */
+#define PIT_TCTRL_COUNT (2U)
+
+/*! @name TFLG - Timer Flag Register */
+#define PIT_TFLG_TIF_MASK (0x1U)
+#define PIT_TFLG_TIF_SHIFT (0U)
+#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
+
+/* The count of PIT_TFLG */
+#define PIT_TFLG_COUNT (2U)
+
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT ((PIT_Type *)PIT_BASE)
+/** Array initializer of PIT peripheral base addresses */
+#define PIT_BASE_ADDRS { PIT_BASE }
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASE_PTRS { PIT }
+/** Interrupt vectors for the PIT peripheral type */
+#define PIT_IRQS { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+ __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+ __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
+#define PMC_LVDSC1_LVDV_MASK (0x3U)
+#define PMC_LVDSC1_LVDV_SHIFT (0U)
+#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK (0x10U)
+#define PMC_LVDSC1_LVDRE_SHIFT (4U)
+#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
+#define PMC_LVDSC1_LVDIE_MASK (0x20U)
+#define PMC_LVDSC1_LVDIE_SHIFT (5U)
+#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
+#define PMC_LVDSC1_LVDACK_MASK (0x40U)
+#define PMC_LVDSC1_LVDACK_SHIFT (6U)
+#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
+#define PMC_LVDSC1_LVDF_MASK (0x80U)
+#define PMC_LVDSC1_LVDF_SHIFT (7U)
+#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
+
+/*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
+#define PMC_LVDSC2_LVWV_MASK (0x3U)
+#define PMC_LVDSC2_LVWV_SHIFT (0U)
+#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK (0x20U)
+#define PMC_LVDSC2_LVWIE_SHIFT (5U)
+#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
+#define PMC_LVDSC2_LVWACK_MASK (0x40U)
+#define PMC_LVDSC2_LVWACK_SHIFT (6U)
+#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
+#define PMC_LVDSC2_LVWF_MASK (0x80U)
+#define PMC_LVDSC2_LVWF_SHIFT (7U)
+#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
+
+/*! @name REGSC - Regulator Status And Control register */
+#define PMC_REGSC_BGBE_MASK (0x1U)
+#define PMC_REGSC_BGBE_SHIFT (0U)
+#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
+#define PMC_REGSC_REGONS_MASK (0x4U)
+#define PMC_REGSC_REGONS_SHIFT (2U)
+#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
+#define PMC_REGSC_ACKISO_MASK (0x8U)
+#define PMC_REGSC_ACKISO_SHIFT (3U)
+#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
+#define PMC_REGSC_BGEN_MASK (0x10U)
+#define PMC_REGSC_BGEN_SHIFT (4U)
+#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC ((PMC_Type *)PMC_BASE)
+/** Array initializer of PMC peripheral base addresses */
+#define PMC_BASE_ADDRS { PMC_BASE }
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASE_PTRS { PMC }
+/** Interrupt vectors for the PMC peripheral type */
+#define PMC_IRQS { LVD_LVW_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
+ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
+ uint8_t RESERVED_0[24];
+ __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
+} PORT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PORT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/*! @name PCR - Pin Control Register n */
+#define PORT_PCR_PS_MASK (0x1U)
+#define PORT_PCR_PS_SHIFT (0U)
+#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
+#define PORT_PCR_PE_MASK (0x2U)
+#define PORT_PCR_PE_SHIFT (1U)
+#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
+#define PORT_PCR_SRE_MASK (0x4U)
+#define PORT_PCR_SRE_SHIFT (2U)
+#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
+#define PORT_PCR_PFE_MASK (0x10U)
+#define PORT_PCR_PFE_SHIFT (4U)
+#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
+#define PORT_PCR_DSE_MASK (0x40U)
+#define PORT_PCR_DSE_SHIFT (6U)
+#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
+#define PORT_PCR_MUX_MASK (0x700U)
+#define PORT_PCR_MUX_SHIFT (8U)
+#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
+#define PORT_PCR_IRQC_MASK (0xF0000U)
+#define PORT_PCR_IRQC_SHIFT (16U)
+#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK (0x1000000U)
+#define PORT_PCR_ISF_SHIFT (24U)
+#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
+
+/* The count of PORT_PCR */
+#define PORT_PCR_COUNT (32U)
+
+/*! @name GPCLR - Global Pin Control Low Register */
+#define PORT_GPCLR_GPWD_MASK (0xFFFFU)
+#define PORT_GPCLR_GPWD_SHIFT (0U)
+#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
+#define PORT_GPCLR_GPWE_SHIFT (16U)
+#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
+
+/*! @name GPCHR - Global Pin Control High Register */
+#define PORT_GPCHR_GPWD_MASK (0xFFFFU)
+#define PORT_GPCHR_GPWD_SHIFT (0U)
+#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
+#define PORT_GPCHR_GPWE_SHIFT (16U)
+#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
+
+/*! @name ISFR - Interrupt Status Flag Register */
+#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
+#define PORT_ISFR_ISF_SHIFT (0U)
+#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA ((PORT_Type *)PORTA_BASE)
+/** Peripheral PORTB base address */
+#define PORTB_BASE (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB ((PORT_Type *)PORTB_BASE)
+/** Peripheral PORTC base address */
+#define PORTC_BASE (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC ((PORT_Type *)PORTC_BASE)
+/** Peripheral PORTD base address */
+#define PORTD_BASE (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD ((PORT_Type *)PORTD_BASE)
+/** Peripheral PORTE base address */
+#define PORTE_BASE (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE ((PORT_Type *)PORTE_BASE)
+/** Array initializer of PORT peripheral base addresses */
+#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
+/** Interrupt vectors for the PORT peripheral type */
+#define PORT_IRQS { PORTA_IRQn, NotAvail_IRQn, PORTC_PORTD_IRQn, PORTC_PORTD_IRQn, NotAvail_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+ __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
+ __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
+ __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
+} RCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/*! @name SRS0 - System Reset Status Register 0 */
+#define RCM_SRS0_WAKEUP_MASK (0x1U)
+#define RCM_SRS0_WAKEUP_SHIFT (0U)
+#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
+#define RCM_SRS0_LVD_MASK (0x2U)
+#define RCM_SRS0_LVD_SHIFT (1U)
+#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
+#define RCM_SRS0_LOC_MASK (0x4U)
+#define RCM_SRS0_LOC_SHIFT (2U)
+#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
+#define RCM_SRS0_LOL_MASK (0x8U)
+#define RCM_SRS0_LOL_SHIFT (3U)
+#define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
+#define RCM_SRS0_WDOG_MASK (0x20U)
+#define RCM_SRS0_WDOG_SHIFT (5U)
+#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
+#define RCM_SRS0_PIN_MASK (0x40U)
+#define RCM_SRS0_PIN_SHIFT (6U)
+#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
+#define RCM_SRS0_POR_MASK (0x80U)
+#define RCM_SRS0_POR_SHIFT (7U)
+#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
+
+/*! @name SRS1 - System Reset Status Register 1 */
+#define RCM_SRS1_LOCKUP_MASK (0x2U)
+#define RCM_SRS1_LOCKUP_SHIFT (1U)
+#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
+#define RCM_SRS1_SW_MASK (0x4U)
+#define RCM_SRS1_SW_SHIFT (2U)
+#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
+#define RCM_SRS1_MDM_AP_MASK (0x8U)
+#define RCM_SRS1_MDM_AP_SHIFT (3U)
+#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
+#define RCM_SRS1_SACKERR_MASK (0x20U)
+#define RCM_SRS1_SACKERR_SHIFT (5U)
+#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
+
+/*! @name RPFC - Reset Pin Filter Control register */
+#define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
+#define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
+#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK (0x4U)
+#define RCM_RPFC_RSTFLTSS_SHIFT (2U)
+#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
+
+/*! @name RPFW - Reset Pin Filter Width register */
+#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
+#define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
+#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM ((RCM_Type *)RCM_BASE)
+/** Array initializer of RCM peripheral base addresses */
+#define RCM_BASE_ADDRS { RCM_BASE }
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASE_PTRS { RCM }
+
+/*!
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- ROM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
+ * @{
+ */
+
+/** ROM - Register Layout Typedef */
+typedef struct {
+ __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
+ __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
+ uint8_t RESERVED_0[4028];
+ __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
+ __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
+ __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
+ __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
+ __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
+ __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
+ __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
+ __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
+ __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} ROM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ROM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Register_Masks ROM Register Masks
+ * @{
+ */
+
+/*! @name ENTRY - Entry */
+#define ROM_ENTRY_ENTRY_MASK (0xFFFFFFFFU)
+#define ROM_ENTRY_ENTRY_SHIFT (0U)
+#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK)
+
+/* The count of ROM_ENTRY */
+#define ROM_ENTRY_COUNT (3U)
+
+/*! @name TABLEMARK - End of Table Marker Register */
+#define ROM_TABLEMARK_MARK_MASK (0xFFFFFFFFU)
+#define ROM_TABLEMARK_MARK_SHIFT (0U)
+#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK)
+
+/*! @name SYSACCESS - System Access Register */
+#define ROM_SYSACCESS_SYSACCESS_MASK (0xFFFFFFFFU)
+#define ROM_SYSACCESS_SYSACCESS_SHIFT (0U)
+#define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK)
+
+/*! @name PERIPHID4 - Peripheral ID Register */
+#define ROM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
+#define ROM_PERIPHID4_PERIPHID_SHIFT (0U)
+#define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK)
+
+/*! @name PERIPHID5 - Peripheral ID Register */
+#define ROM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
+#define ROM_PERIPHID5_PERIPHID_SHIFT (0U)
+#define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK)
+
+/*! @name PERIPHID6 - Peripheral ID Register */
+#define ROM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
+#define ROM_PERIPHID6_PERIPHID_SHIFT (0U)
+#define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK)
+
+/*! @name PERIPHID7 - Peripheral ID Register */
+#define ROM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
+#define ROM_PERIPHID7_PERIPHID_SHIFT (0U)
+#define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK)
+
+/*! @name PERIPHID0 - Peripheral ID Register */
+#define ROM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
+#define ROM_PERIPHID0_PERIPHID_SHIFT (0U)
+#define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK)
+
+/*! @name PERIPHID1 - Peripheral ID Register */
+#define ROM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
+#define ROM_PERIPHID1_PERIPHID_SHIFT (0U)
+#define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK)
+
+/*! @name PERIPHID2 - Peripheral ID Register */
+#define ROM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
+#define ROM_PERIPHID2_PERIPHID_SHIFT (0U)
+#define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK)
+
+/*! @name PERIPHID3 - Peripheral ID Register */
+#define ROM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
+#define ROM_PERIPHID3_PERIPHID_SHIFT (0U)
+#define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK)
+
+/*! @name COMPID - Component ID Register */
+#define ROM_COMPID_COMPID_MASK (0xFFFFFFFFU)
+#define ROM_COMPID_COMPID_SHIFT (0U)
+#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK)
+
+/* The count of ROM_COMPID */
+#define ROM_COMPID_COUNT (4U)
+
+
+/*!
+ * @}
+ */ /* end of group ROM_Register_Masks */
+
+
+/* ROM - Peripheral instance base addresses */
+/** Peripheral ROM base address */
+#define ROM_BASE (0xF0002000u)
+/** Peripheral ROM base pointer */
+#define ROM ((ROM_Type *)ROM_BASE)
+/** Array initializer of ROM peripheral base addresses */
+#define ROM_BASE_ADDRS { ROM_BASE }
+/** Array initializer of ROM peripheral base pointers */
+#define ROM_BASE_PTRS { ROM }
+
+/*!
+ * @}
+ */ /* end of group ROM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
+ __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
+ __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
+ __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
+ __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
+ __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
+ __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
+ __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/*! @name TSR - RTC Time Seconds Register */
+#define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
+#define RTC_TSR_TSR_SHIFT (0U)
+#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
+
+/*! @name TPR - RTC Time Prescaler Register */
+#define RTC_TPR_TPR_MASK (0xFFFFU)
+#define RTC_TPR_TPR_SHIFT (0U)
+#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
+
+/*! @name TAR - RTC Time Alarm Register */
+#define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
+#define RTC_TAR_TAR_SHIFT (0U)
+#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
+
+/*! @name TCR - RTC Time Compensation Register */
+#define RTC_TCR_TCR_MASK (0xFFU)
+#define RTC_TCR_TCR_SHIFT (0U)
+#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK (0xFF00U)
+#define RTC_TCR_CIR_SHIFT (8U)
+#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK (0xFF0000U)
+#define RTC_TCR_TCV_SHIFT (16U)
+#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK (0xFF000000U)
+#define RTC_TCR_CIC_SHIFT (24U)
+#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
+
+/*! @name CR - RTC Control Register */
+#define RTC_CR_SWR_MASK (0x1U)
+#define RTC_CR_SWR_SHIFT (0U)
+#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
+#define RTC_CR_WPE_MASK (0x2U)
+#define RTC_CR_WPE_SHIFT (1U)
+#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
+#define RTC_CR_SUP_MASK (0x4U)
+#define RTC_CR_SUP_SHIFT (2U)
+#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
+#define RTC_CR_UM_MASK (0x8U)
+#define RTC_CR_UM_SHIFT (3U)
+#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
+#define RTC_CR_WPS_MASK (0x10U)
+#define RTC_CR_WPS_SHIFT (4U)
+#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
+#define RTC_CR_OSCE_MASK (0x100U)
+#define RTC_CR_OSCE_SHIFT (8U)
+#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
+#define RTC_CR_CLKO_MASK (0x200U)
+#define RTC_CR_CLKO_SHIFT (9U)
+#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
+#define RTC_CR_SC16P_MASK (0x400U)
+#define RTC_CR_SC16P_SHIFT (10U)
+#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
+#define RTC_CR_SC8P_MASK (0x800U)
+#define RTC_CR_SC8P_SHIFT (11U)
+#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
+#define RTC_CR_SC4P_MASK (0x1000U)
+#define RTC_CR_SC4P_SHIFT (12U)
+#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
+#define RTC_CR_SC2P_MASK (0x2000U)
+#define RTC_CR_SC2P_SHIFT (13U)
+#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
+
+/*! @name SR - RTC Status Register */
+#define RTC_SR_TIF_MASK (0x1U)
+#define RTC_SR_TIF_SHIFT (0U)
+#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
+#define RTC_SR_TOF_MASK (0x2U)
+#define RTC_SR_TOF_SHIFT (1U)
+#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
+#define RTC_SR_TAF_MASK (0x4U)
+#define RTC_SR_TAF_SHIFT (2U)
+#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
+#define RTC_SR_TCE_MASK (0x10U)
+#define RTC_SR_TCE_SHIFT (4U)
+#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
+
+/*! @name LR - RTC Lock Register */
+#define RTC_LR_TCL_MASK (0x8U)
+#define RTC_LR_TCL_SHIFT (3U)
+#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
+#define RTC_LR_CRL_MASK (0x10U)
+#define RTC_LR_CRL_SHIFT (4U)
+#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
+#define RTC_LR_SRL_MASK (0x20U)
+#define RTC_LR_SRL_SHIFT (5U)
+#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
+#define RTC_LR_LRL_MASK (0x40U)
+#define RTC_LR_LRL_SHIFT (6U)
+#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
+
+/*! @name IER - RTC Interrupt Enable Register */
+#define RTC_IER_TIIE_MASK (0x1U)
+#define RTC_IER_TIIE_SHIFT (0U)
+#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
+#define RTC_IER_TOIE_MASK (0x2U)
+#define RTC_IER_TOIE_SHIFT (1U)
+#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
+#define RTC_IER_TAIE_MASK (0x4U)
+#define RTC_IER_TAIE_SHIFT (2U)
+#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
+#define RTC_IER_TSIE_MASK (0x10U)
+#define RTC_IER_TSIE_SHIFT (4U)
+#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
+#define RTC_IER_WPON_MASK (0x80U)
+#define RTC_IER_WPON_SHIFT (7U)
+#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS { RTC_IRQn }
+#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
+ __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
+ uint8_t RESERVED_0[4092];
+ __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
+ __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
+ uint8_t RESERVED_3[8];
+ __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
+ uint8_t RESERVED_4[12];
+ __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
+ __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
+ __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
+ __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
+ __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
+ uint8_t RESERVED_5[4];
+ __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
+ __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
+ uint8_t RESERVED_6[4];
+ __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
+ __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
+ __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
+ uint8_t RESERVED_7[156];
+ __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
+ __O uint32_t SRVCOP; /**< Service COP, offset: 0x1104 */
+} SIM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SIM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/*! @name SOPT1 - System Options Register 1 */
+#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
+#define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
+#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK (0x20000000U)
+#define SIM_SOPT1_USBVSTBY_SHIFT (29U)
+#define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
+#define SIM_SOPT1_USBSSTBY_MASK (0x40000000U)
+#define SIM_SOPT1_USBSSTBY_SHIFT (30U)
+#define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
+#define SIM_SOPT1_USBREGEN_MASK (0x80000000U)
+#define SIM_SOPT1_USBREGEN_SHIFT (31U)
+#define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
+
+/*! @name SOPT1CFG - SOPT1 Configuration Register */
+#define SIM_SOPT1CFG_URWE_MASK (0x1000000U)
+#define SIM_SOPT1CFG_URWE_SHIFT (24U)
+#define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
+#define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U)
+#define SIM_SOPT1CFG_UVSWE_SHIFT (25U)
+#define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
+#define SIM_SOPT1CFG_USSWE_MASK (0x4000000U)
+#define SIM_SOPT1CFG_USSWE_SHIFT (26U)
+#define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
+
+/*! @name SOPT2 - System Options Register 2 */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
+#define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
+#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
+#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
+#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_PLLFLLSEL_MASK (0x10000U)
+#define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
+#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
+#define SIM_SOPT2_USBSRC_MASK (0x40000U)
+#define SIM_SOPT2_USBSRC_SHIFT (18U)
+#define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
+#define SIM_SOPT2_TPMSRC_MASK (0x3000000U)
+#define SIM_SOPT2_TPMSRC_SHIFT (24U)
+#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)
+#define SIM_SOPT2_UART0SRC_MASK (0xC000000U)
+#define SIM_SOPT2_UART0SRC_SHIFT (26U)
+#define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_UART0SRC_SHIFT)) & SIM_SOPT2_UART0SRC_MASK)
+
+/*! @name SOPT4 - System Options Register 4 */
+#define SIM_SOPT4_TPM1CH0SRC_MASK (0xC0000U)
+#define SIM_SOPT4_TPM1CH0SRC_SHIFT (18U)
+#define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CH0SRC_SHIFT)) & SIM_SOPT4_TPM1CH0SRC_MASK)
+#define SIM_SOPT4_TPM2CH0SRC_MASK (0x100000U)
+#define SIM_SOPT4_TPM2CH0SRC_SHIFT (20U)
+#define SIM_SOPT4_TPM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CH0SRC_SHIFT)) & SIM_SOPT4_TPM2CH0SRC_MASK)
+#define SIM_SOPT4_TPM0CLKSEL_MASK (0x1000000U)
+#define SIM_SOPT4_TPM0CLKSEL_SHIFT (24U)
+#define SIM_SOPT4_TPM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM0CLKSEL_SHIFT)) & SIM_SOPT4_TPM0CLKSEL_MASK)
+#define SIM_SOPT4_TPM1CLKSEL_MASK (0x2000000U)
+#define SIM_SOPT4_TPM1CLKSEL_SHIFT (25U)
+#define SIM_SOPT4_TPM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CLKSEL_SHIFT)) & SIM_SOPT4_TPM1CLKSEL_MASK)
+#define SIM_SOPT4_TPM2CLKSEL_MASK (0x4000000U)
+#define SIM_SOPT4_TPM2CLKSEL_SHIFT (26U)
+#define SIM_SOPT4_TPM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CLKSEL_SHIFT)) & SIM_SOPT4_TPM2CLKSEL_MASK)
+
+/*! @name SOPT5 - System Options Register 5 */
+#define SIM_SOPT5_UART0TXSRC_MASK (0x3U)
+#define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
+#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK (0x4U)
+#define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
+#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_MASK (0x30U)
+#define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
+#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK (0x40U)
+#define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
+#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
+#define SIM_SOPT5_UART0ODE_MASK (0x10000U)
+#define SIM_SOPT5_UART0ODE_SHIFT (16U)
+#define SIM_SOPT5_UART0ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0ODE_SHIFT)) & SIM_SOPT5_UART0ODE_MASK)
+#define SIM_SOPT5_UART1ODE_MASK (0x20000U)
+#define SIM_SOPT5_UART1ODE_SHIFT (17U)
+#define SIM_SOPT5_UART1ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1ODE_SHIFT)) & SIM_SOPT5_UART1ODE_MASK)
+#define SIM_SOPT5_UART2ODE_MASK (0x40000U)
+#define SIM_SOPT5_UART2ODE_SHIFT (18U)
+#define SIM_SOPT5_UART2ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART2ODE_SHIFT)) & SIM_SOPT5_UART2ODE_MASK)
+
+/*! @name SOPT7 - System Options Register 7 */
+#define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
+#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
+#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
+#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
+
+/*! @name SDID - System Device Identification Register */
+#define SIM_SDID_PINID_MASK (0xFU)
+#define SIM_SDID_PINID_SHIFT (0U)
+#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
+#define SIM_SDID_DIEID_MASK (0xF80U)
+#define SIM_SDID_DIEID_SHIFT (7U)
+#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK (0xF000U)
+#define SIM_SDID_REVID_SHIFT (12U)
+#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
+#define SIM_SDID_SRAMSIZE_MASK (0xF0000U)
+#define SIM_SDID_SRAMSIZE_SHIFT (16U)
+#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SRAMSIZE_SHIFT)) & SIM_SDID_SRAMSIZE_MASK)
+#define SIM_SDID_SERIESID_MASK (0xF00000U)
+#define SIM_SDID_SERIESID_SHIFT (20U)
+#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK (0xF000000U)
+#define SIM_SDID_SUBFAMID_SHIFT (24U)
+#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMID_MASK (0xF0000000U)
+#define SIM_SDID_FAMID_SHIFT (28U)
+#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
+
+/*! @name SCGC4 - System Clock Gating Control Register 4 */
+#define SIM_SCGC4_I2C0_MASK (0x40U)
+#define SIM_SCGC4_I2C0_SHIFT (6U)
+#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
+#define SIM_SCGC4_I2C1_MASK (0x80U)
+#define SIM_SCGC4_I2C1_SHIFT (7U)
+#define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
+#define SIM_SCGC4_UART0_MASK (0x400U)
+#define SIM_SCGC4_UART0_SHIFT (10U)
+#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
+#define SIM_SCGC4_UART1_MASK (0x800U)
+#define SIM_SCGC4_UART1_SHIFT (11U)
+#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
+#define SIM_SCGC4_UART2_MASK (0x1000U)
+#define SIM_SCGC4_UART2_SHIFT (12U)
+#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
+#define SIM_SCGC4_USBOTG_MASK (0x40000U)
+#define SIM_SCGC4_USBOTG_SHIFT (18U)
+#define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
+#define SIM_SCGC4_CMP_MASK (0x80000U)
+#define SIM_SCGC4_CMP_SHIFT (19U)
+#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
+#define SIM_SCGC4_SPI0_MASK (0x400000U)
+#define SIM_SCGC4_SPI0_SHIFT (22U)
+#define SIM_SCGC4_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI0_SHIFT)) & SIM_SCGC4_SPI0_MASK)
+#define SIM_SCGC4_SPI1_MASK (0x800000U)
+#define SIM_SCGC4_SPI1_SHIFT (23U)
+#define SIM_SCGC4_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI1_SHIFT)) & SIM_SCGC4_SPI1_MASK)
+
+/*! @name SCGC5 - System Clock Gating Control Register 5 */
+#define SIM_SCGC5_LPTMR_MASK (0x1U)
+#define SIM_SCGC5_LPTMR_SHIFT (0U)
+#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
+#define SIM_SCGC5_TSI_MASK (0x20U)
+#define SIM_SCGC5_TSI_SHIFT (5U)
+#define SIM_SCGC5_TSI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
+#define SIM_SCGC5_PORTA_MASK (0x200U)
+#define SIM_SCGC5_PORTA_SHIFT (9U)
+#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
+#define SIM_SCGC5_PORTB_MASK (0x400U)
+#define SIM_SCGC5_PORTB_SHIFT (10U)
+#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
+#define SIM_SCGC5_PORTC_MASK (0x800U)
+#define SIM_SCGC5_PORTC_SHIFT (11U)
+#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
+#define SIM_SCGC5_PORTD_MASK (0x1000U)
+#define SIM_SCGC5_PORTD_SHIFT (12U)
+#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
+#define SIM_SCGC5_PORTE_MASK (0x2000U)
+#define SIM_SCGC5_PORTE_SHIFT (13U)
+#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
+
+/*! @name SCGC6 - System Clock Gating Control Register 6 */
+#define SIM_SCGC6_FTF_MASK (0x1U)
+#define SIM_SCGC6_FTF_SHIFT (0U)
+#define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
+#define SIM_SCGC6_DMAMUX_MASK (0x2U)
+#define SIM_SCGC6_DMAMUX_SHIFT (1U)
+#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
+#define SIM_SCGC6_I2S_MASK (0x8000U)
+#define SIM_SCGC6_I2S_SHIFT (15U)
+#define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
+#define SIM_SCGC6_PIT_MASK (0x800000U)
+#define SIM_SCGC6_PIT_SHIFT (23U)
+#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
+#define SIM_SCGC6_TPM0_MASK (0x1000000U)
+#define SIM_SCGC6_TPM0_SHIFT (24U)
+#define SIM_SCGC6_TPM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM0_SHIFT)) & SIM_SCGC6_TPM0_MASK)
+#define SIM_SCGC6_TPM1_MASK (0x2000000U)
+#define SIM_SCGC6_TPM1_SHIFT (25U)
+#define SIM_SCGC6_TPM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM1_SHIFT)) & SIM_SCGC6_TPM1_MASK)
+#define SIM_SCGC6_TPM2_MASK (0x4000000U)
+#define SIM_SCGC6_TPM2_SHIFT (26U)
+#define SIM_SCGC6_TPM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM2_SHIFT)) & SIM_SCGC6_TPM2_MASK)
+#define SIM_SCGC6_ADC0_MASK (0x8000000U)
+#define SIM_SCGC6_ADC0_SHIFT (27U)
+#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
+#define SIM_SCGC6_RTC_MASK (0x20000000U)
+#define SIM_SCGC6_RTC_SHIFT (29U)
+#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
+#define SIM_SCGC6_DAC0_MASK (0x80000000U)
+#define SIM_SCGC6_DAC0_SHIFT (31U)
+#define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
+
+/*! @name SCGC7 - System Clock Gating Control Register 7 */
+#define SIM_SCGC7_DMA_MASK (0x100U)
+#define SIM_SCGC7_DMA_SHIFT (8U)
+#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
+
+/*! @name CLKDIV1 - System Clock Divider Register 1 */
+#define SIM_CLKDIV1_OUTDIV4_MASK (0x70000U)
+#define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
+#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
+#define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
+#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
+
+/*! @name FCFG1 - Flash Configuration Register 1 */
+#define SIM_FCFG1_FLASHDIS_MASK (0x1U)
+#define SIM_FCFG1_FLASHDIS_SHIFT (0U)
+#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
+#define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
+#define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
+#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
+#define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
+#define SIM_FCFG1_PFSIZE_SHIFT (24U)
+#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
+
+/*! @name FCFG2 - Flash Configuration Register 2 */
+#define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
+#define SIM_FCFG2_MAXADDR1_SHIFT (16U)
+#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
+#define SIM_FCFG2_MAXADDR0_SHIFT (24U)
+#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
+
+/*! @name UIDMH - Unique Identification Register Mid-High */
+#define SIM_UIDMH_UID_MASK (0xFFFFU)
+#define SIM_UIDMH_UID_SHIFT (0U)
+#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
+
+/*! @name UIDML - Unique Identification Register Mid Low */
+#define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
+#define SIM_UIDML_UID_SHIFT (0U)
+#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
+
+/*! @name UIDL - Unique Identification Register Low */
+#define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
+#define SIM_UIDL_UID_SHIFT (0U)
+#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
+
+/*! @name COPC - COP Control Register */
+#define SIM_COPC_COPW_MASK (0x1U)
+#define SIM_COPC_COPW_SHIFT (0U)
+#define SIM_COPC_COPW(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPW_SHIFT)) & SIM_COPC_COPW_MASK)
+#define SIM_COPC_COPCLKS_MASK (0x2U)
+#define SIM_COPC_COPCLKS_SHIFT (1U)
+#define SIM_COPC_COPCLKS(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKS_SHIFT)) & SIM_COPC_COPCLKS_MASK)
+#define SIM_COPC_COPT_MASK (0xCU)
+#define SIM_COPC_COPT_SHIFT (2U)
+#define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPT_SHIFT)) & SIM_COPC_COPT_MASK)
+
+/*! @name SRVCOP - Service COP */
+#define SIM_SRVCOP_SRVCOP_MASK (0xFFU)
+#define SIM_SRVCOP_SRVCOP_SHIFT (0U)
+#define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRVCOP_SRVCOP_SHIFT)) & SIM_SRVCOP_SRVCOP_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM ((SIM_Type *)SIM_BASE)
+/** Array initializer of SIM peripheral base addresses */
+#define SIM_BASE_ADDRS { SIM_BASE }
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASE_PTRS { SIM }
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
+ __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
+ __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
+ __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/*! @name PMPROT - Power Mode Protection register */
+#define SMC_PMPROT_AVLLS_MASK (0x2U)
+#define SMC_PMPROT_AVLLS_SHIFT (1U)
+#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
+#define SMC_PMPROT_ALLS_MASK (0x8U)
+#define SMC_PMPROT_ALLS_SHIFT (3U)
+#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
+#define SMC_PMPROT_AVLP_MASK (0x20U)
+#define SMC_PMPROT_AVLP_SHIFT (5U)
+#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
+
+/*! @name PMCTRL - Power Mode Control register */
+#define SMC_PMCTRL_STOPM_MASK (0x7U)
+#define SMC_PMCTRL_STOPM_SHIFT (0U)
+#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK (0x8U)
+#define SMC_PMCTRL_STOPA_SHIFT (3U)
+#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
+#define SMC_PMCTRL_RUNM_MASK (0x60U)
+#define SMC_PMCTRL_RUNM_SHIFT (5U)
+#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
+
+/*! @name STOPCTRL - Stop Control Register */
+#define SMC_STOPCTRL_VLLSM_MASK (0x7U)
+#define SMC_STOPCTRL_VLLSM_SHIFT (0U)
+#define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_VLLSM_SHIFT)) & SMC_STOPCTRL_VLLSM_MASK)
+#define SMC_STOPCTRL_PORPO_MASK (0x20U)
+#define SMC_STOPCTRL_PORPO_SHIFT (5U)
+#define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
+#define SMC_STOPCTRL_PSTOPO_MASK (0xC0U)
+#define SMC_STOPCTRL_PSTOPO_SHIFT (6U)
+#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
+
+/*! @name PMSTAT - Power Mode Status register */
+#define SMC_PMSTAT_PMSTAT_MASK (0x7FU)
+#define SMC_PMSTAT_PMSTAT_SHIFT (0U)
+#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC ((SMC_Type *)SMC_BASE)
+/** Array initializer of SMC peripheral base addresses */
+#define SMC_BASE_ADDRS { SMC_BASE }
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASE_PTRS { SMC }
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t S; /**< SPI Status Register, offset: 0x0 */
+ __IO uint8_t BR; /**< SPI Baud Rate Register, offset: 0x1 */
+ __IO uint8_t C2; /**< SPI Control Register 2, offset: 0x2 */
+ __IO uint8_t C1; /**< SPI Control Register 1, offset: 0x3 */
+ __IO uint8_t ML; /**< SPI Match Register low, offset: 0x4 */
+ __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */
+ __IO uint8_t DL; /**< SPI Data Register low, offset: 0x6 */
+ __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */
+ __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/*! @name S - SPI Status Register */
+#define SPI_S_RFIFOEF_MASK (0x1U)
+#define SPI_S_RFIFOEF_SHIFT (0U)
+#define SPI_S_RFIFOEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_RFIFOEF_SHIFT)) & SPI_S_RFIFOEF_MASK)
+#define SPI_S_TXFULLF_MASK (0x2U)
+#define SPI_S_TXFULLF_SHIFT (1U)
+#define SPI_S_TXFULLF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_TXFULLF_SHIFT)) & SPI_S_TXFULLF_MASK)
+#define SPI_S_TNEAREF_MASK (0x4U)
+#define SPI_S_TNEAREF_SHIFT (2U)
+#define SPI_S_TNEAREF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_TNEAREF_SHIFT)) & SPI_S_TNEAREF_MASK)
+#define SPI_S_RNFULLF_MASK (0x8U)
+#define SPI_S_RNFULLF_SHIFT (3U)
+#define SPI_S_RNFULLF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_RNFULLF_SHIFT)) & SPI_S_RNFULLF_MASK)
+#define SPI_S_MODF_MASK (0x10U)
+#define SPI_S_MODF_SHIFT (4U)
+#define SPI_S_MODF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_MODF_SHIFT)) & SPI_S_MODF_MASK)
+#define SPI_S_SPTEF_MASK (0x20U)
+#define SPI_S_SPTEF_SHIFT (5U)
+#define SPI_S_SPTEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPTEF_SHIFT)) & SPI_S_SPTEF_MASK)
+#define SPI_S_SPMF_MASK (0x40U)
+#define SPI_S_SPMF_SHIFT (6U)
+#define SPI_S_SPMF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPMF_SHIFT)) & SPI_S_SPMF_MASK)
+#define SPI_S_SPRF_MASK (0x80U)
+#define SPI_S_SPRF_SHIFT (7U)
+#define SPI_S_SPRF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPRF_SHIFT)) & SPI_S_SPRF_MASK)
+
+/*! @name BR - SPI Baud Rate Register */
+#define SPI_BR_SPR_MASK (0xFU)
+#define SPI_BR_SPR_SHIFT (0U)
+#define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPR_SHIFT)) & SPI_BR_SPR_MASK)
+#define SPI_BR_SPPR_MASK (0x70U)
+#define SPI_BR_SPPR_SHIFT (4U)
+#define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPPR_SHIFT)) & SPI_BR_SPPR_MASK)
+
+/*! @name C2 - SPI Control Register 2 */
+#define SPI_C2_SPC0_MASK (0x1U)
+#define SPI_C2_SPC0_SHIFT (0U)
+#define SPI_C2_SPC0(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPC0_SHIFT)) & SPI_C2_SPC0_MASK)
+#define SPI_C2_SPISWAI_MASK (0x2U)
+#define SPI_C2_SPISWAI_SHIFT (1U)
+#define SPI_C2_SPISWAI(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPISWAI_SHIFT)) & SPI_C2_SPISWAI_MASK)
+#define SPI_C2_RXDMAE_MASK (0x4U)
+#define SPI_C2_RXDMAE_SHIFT (2U)
+#define SPI_C2_RXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_RXDMAE_SHIFT)) & SPI_C2_RXDMAE_MASK)
+#define SPI_C2_BIDIROE_MASK (0x8U)
+#define SPI_C2_BIDIROE_SHIFT (3U)
+#define SPI_C2_BIDIROE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_BIDIROE_SHIFT)) & SPI_C2_BIDIROE_MASK)
+#define SPI_C2_MODFEN_MASK (0x10U)
+#define SPI_C2_MODFEN_SHIFT (4U)
+#define SPI_C2_MODFEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_MODFEN_SHIFT)) & SPI_C2_MODFEN_MASK)
+#define SPI_C2_TXDMAE_MASK (0x20U)
+#define SPI_C2_TXDMAE_SHIFT (5U)
+#define SPI_C2_TXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_TXDMAE_SHIFT)) & SPI_C2_TXDMAE_MASK)
+#define SPI_C2_SPIMODE_MASK (0x40U)
+#define SPI_C2_SPIMODE_SHIFT (6U)
+#define SPI_C2_SPIMODE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPIMODE_SHIFT)) & SPI_C2_SPIMODE_MASK)
+#define SPI_C2_SPMIE_MASK (0x80U)
+#define SPI_C2_SPMIE_SHIFT (7U)
+#define SPI_C2_SPMIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPMIE_SHIFT)) & SPI_C2_SPMIE_MASK)
+
+/*! @name C1 - SPI Control Register 1 */
+#define SPI_C1_LSBFE_MASK (0x1U)
+#define SPI_C1_LSBFE_SHIFT (0U)
+#define SPI_C1_LSBFE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_LSBFE_SHIFT)) & SPI_C1_LSBFE_MASK)
+#define SPI_C1_SSOE_MASK (0x2U)
+#define SPI_C1_SSOE_SHIFT (1U)
+#define SPI_C1_SSOE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SSOE_SHIFT)) & SPI_C1_SSOE_MASK)
+#define SPI_C1_CPHA_MASK (0x4U)
+#define SPI_C1_CPHA_SHIFT (2U)
+#define SPI_C1_CPHA(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPHA_SHIFT)) & SPI_C1_CPHA_MASK)
+#define SPI_C1_CPOL_MASK (0x8U)
+#define SPI_C1_CPOL_SHIFT (3U)
+#define SPI_C1_CPOL(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPOL_SHIFT)) & SPI_C1_CPOL_MASK)
+#define SPI_C1_MSTR_MASK (0x10U)
+#define SPI_C1_MSTR_SHIFT (4U)
+#define SPI_C1_MSTR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_MSTR_SHIFT)) & SPI_C1_MSTR_MASK)
+#define SPI_C1_SPTIE_MASK (0x20U)
+#define SPI_C1_SPTIE_SHIFT (5U)
+#define SPI_C1_SPTIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPTIE_SHIFT)) & SPI_C1_SPTIE_MASK)
+#define SPI_C1_SPE_MASK (0x40U)
+#define SPI_C1_SPE_SHIFT (6U)
+#define SPI_C1_SPE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPE_SHIFT)) & SPI_C1_SPE_MASK)
+#define SPI_C1_SPIE_MASK (0x80U)
+#define SPI_C1_SPIE_SHIFT (7U)
+#define SPI_C1_SPIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPIE_SHIFT)) & SPI_C1_SPIE_MASK)
+
+/*! @name ML - SPI Match Register low */
+#define SPI_ML_Bits_MASK (0xFFU)
+#define SPI_ML_Bits_SHIFT (0U)
+#define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_ML_Bits_SHIFT)) & SPI_ML_Bits_MASK)
+
+/*! @name MH - SPI match register high */
+#define SPI_MH_Bits_MASK (0xFFU)
+#define SPI_MH_Bits_SHIFT (0U)
+#define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_MH_Bits_SHIFT)) & SPI_MH_Bits_MASK)
+
+/*! @name DL - SPI Data Register low */
+#define SPI_DL_Bits_MASK (0xFFU)
+#define SPI_DL_Bits_SHIFT (0U)
+#define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_DL_Bits_SHIFT)) & SPI_DL_Bits_MASK)
+
+/*! @name DH - SPI data register high */
+#define SPI_DH_Bits_MASK (0xFFU)
+#define SPI_DH_Bits_SHIFT (0U)
+#define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_DH_Bits_SHIFT)) & SPI_DH_Bits_MASK)
+
+/*! @name CI - SPI clear interrupt register */
+#define SPI_CI_SPRFCI_MASK (0x1U)
+#define SPI_CI_SPRFCI_SHIFT (0U)
+#define SPI_CI_SPRFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_SPRFCI_SHIFT)) & SPI_CI_SPRFCI_MASK)
+#define SPI_CI_SPTEFCI_MASK (0x2U)
+#define SPI_CI_SPTEFCI_SHIFT (1U)
+#define SPI_CI_SPTEFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_SPTEFCI_SHIFT)) & SPI_CI_SPTEFCI_MASK)
+#define SPI_CI_RNFULLFCI_MASK (0x4U)
+#define SPI_CI_RNFULLFCI_SHIFT (2U)
+#define SPI_CI_RNFULLFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RNFULLFCI_SHIFT)) & SPI_CI_RNFULLFCI_MASK)
+#define SPI_CI_TNEAREFCI_MASK (0x8U)
+#define SPI_CI_TNEAREFCI_SHIFT (3U)
+#define SPI_CI_TNEAREFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TNEAREFCI_SHIFT)) & SPI_CI_TNEAREFCI_MASK)
+#define SPI_CI_RXFOF_MASK (0x10U)
+#define SPI_CI_RXFOF_SHIFT (4U)
+#define SPI_CI_RXFOF(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RXFOF_SHIFT)) & SPI_CI_RXFOF_MASK)
+#define SPI_CI_TXFOF_MASK (0x20U)
+#define SPI_CI_TXFOF_SHIFT (5U)
+#define SPI_CI_TXFOF(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TXFOF_SHIFT)) & SPI_CI_TXFOF_MASK)
+#define SPI_CI_RXFERR_MASK (0x40U)
+#define SPI_CI_RXFERR_SHIFT (6U)
+#define SPI_CI_RXFERR(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RXFERR_SHIFT)) & SPI_CI_RXFERR_MASK)
+#define SPI_CI_TXFERR_MASK (0x80U)
+#define SPI_CI_TXFERR_SHIFT (7U)
+#define SPI_CI_TXFERR(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TXFERR_SHIFT)) & SPI_CI_TXFERR_MASK)
+
+/*! @name C3 - SPI control register 3 */
+#define SPI_C3_FIFOMODE_MASK (0x1U)
+#define SPI_C3_FIFOMODE_SHIFT (0U)
+#define SPI_C3_FIFOMODE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_FIFOMODE_SHIFT)) & SPI_C3_FIFOMODE_MASK)
+#define SPI_C3_RNFULLIEN_MASK (0x2U)
+#define SPI_C3_RNFULLIEN_SHIFT (1U)
+#define SPI_C3_RNFULLIEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_RNFULLIEN_SHIFT)) & SPI_C3_RNFULLIEN_MASK)
+#define SPI_C3_TNEARIEN_MASK (0x4U)
+#define SPI_C3_TNEARIEN_SHIFT (2U)
+#define SPI_C3_TNEARIEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_TNEARIEN_SHIFT)) & SPI_C3_TNEARIEN_MASK)
+#define SPI_C3_INTCLR_MASK (0x8U)
+#define SPI_C3_INTCLR_SHIFT (3U)
+#define SPI_C3_INTCLR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_INTCLR_SHIFT)) & SPI_C3_INTCLR_MASK)
+#define SPI_C3_RNFULLF_MARK_MASK (0x10U)
+#define SPI_C3_RNFULLF_MARK_SHIFT (4U)
+#define SPI_C3_RNFULLF_MARK(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_RNFULLF_MARK_SHIFT)) & SPI_C3_RNFULLF_MARK_MASK)
+#define SPI_C3_TNEAREF_MARK_MASK (0x20U)
+#define SPI_C3_TNEAREF_MARK_SHIFT (5U)
+#define SPI_C3_TNEAREF_MARK(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_TNEAREF_MARK_SHIFT)) & SPI_C3_TNEAREF_MARK_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE (0x40076000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0 ((SPI_Type *)SPI0_BASE)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE (0x40077000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1 ((SPI_Type *)SPI1_BASE)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS { SPI0, SPI1 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TPM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
+ * @{
+ */
+
+/** TPM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
+ __IO uint32_t CNT; /**< Counter, offset: 0x4 */
+ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
+ struct { /* offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+ } CONTROLS[6];
+ uint8_t RESERVED_0[20];
+ __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
+ uint8_t RESERVED_1[48];
+ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
+} TPM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TPM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Register_Masks TPM Register Masks
+ * @{
+ */
+
+/*! @name SC - Status and Control */
+#define TPM_SC_PS_MASK (0x7U)
+#define TPM_SC_PS_SHIFT (0U)
+#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
+#define TPM_SC_CMOD_MASK (0x18U)
+#define TPM_SC_CMOD_SHIFT (3U)
+#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
+#define TPM_SC_CPWMS_MASK (0x20U)
+#define TPM_SC_CPWMS_SHIFT (5U)
+#define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
+#define TPM_SC_TOIE_MASK (0x40U)
+#define TPM_SC_TOIE_SHIFT (6U)
+#define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
+#define TPM_SC_TOF_MASK (0x80U)
+#define TPM_SC_TOF_SHIFT (7U)
+#define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
+#define TPM_SC_DMA_MASK (0x100U)
+#define TPM_SC_DMA_SHIFT (8U)
+#define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
+
+/*! @name CNT - Counter */
+#define TPM_CNT_COUNT_MASK (0xFFFFU)
+#define TPM_CNT_COUNT_SHIFT (0U)
+#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
+
+/*! @name MOD - Modulo */
+#define TPM_MOD_MOD_MASK (0xFFFFU)
+#define TPM_MOD_MOD_SHIFT (0U)
+#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
+
+/*! @name CnSC - Channel (n) Status and Control */
+#define TPM_CnSC_DMA_MASK (0x1U)
+#define TPM_CnSC_DMA_SHIFT (0U)
+#define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
+#define TPM_CnSC_ELSA_MASK (0x4U)
+#define TPM_CnSC_ELSA_SHIFT (2U)
+#define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
+#define TPM_CnSC_ELSB_MASK (0x8U)
+#define TPM_CnSC_ELSB_SHIFT (3U)
+#define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
+#define TPM_CnSC_MSA_MASK (0x10U)
+#define TPM_CnSC_MSA_SHIFT (4U)
+#define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
+#define TPM_CnSC_MSB_MASK (0x20U)
+#define TPM_CnSC_MSB_SHIFT (5U)
+#define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
+#define TPM_CnSC_CHIE_MASK (0x40U)
+#define TPM_CnSC_CHIE_SHIFT (6U)
+#define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
+#define TPM_CnSC_CHF_MASK (0x80U)
+#define TPM_CnSC_CHF_SHIFT (7U)
+#define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
+
+/* The count of TPM_CnSC */
+#define TPM_CnSC_COUNT (6U)
+
+/*! @name CnV - Channel (n) Value */
+#define TPM_CnV_VAL_MASK (0xFFFFU)
+#define TPM_CnV_VAL_SHIFT (0U)
+#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
+
+/* The count of TPM_CnV */
+#define TPM_CnV_COUNT (6U)
+
+/*! @name STATUS - Capture and Compare Status */
+#define TPM_STATUS_CH0F_MASK (0x1U)
+#define TPM_STATUS_CH0F_SHIFT (0U)
+#define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
+#define TPM_STATUS_CH1F_MASK (0x2U)
+#define TPM_STATUS_CH1F_SHIFT (1U)
+#define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
+#define TPM_STATUS_CH2F_MASK (0x4U)
+#define TPM_STATUS_CH2F_SHIFT (2U)
+#define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK)
+#define TPM_STATUS_CH3F_MASK (0x8U)
+#define TPM_STATUS_CH3F_SHIFT (3U)
+#define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK)
+#define TPM_STATUS_CH4F_MASK (0x10U)
+#define TPM_STATUS_CH4F_SHIFT (4U)
+#define TPM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK)
+#define TPM_STATUS_CH5F_MASK (0x20U)
+#define TPM_STATUS_CH5F_SHIFT (5U)
+#define TPM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK)
+#define TPM_STATUS_TOF_MASK (0x100U)
+#define TPM_STATUS_TOF_SHIFT (8U)
+#define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
+
+/*! @name CONF - Configuration */
+#define TPM_CONF_DOZEEN_MASK (0x20U)
+#define TPM_CONF_DOZEEN_SHIFT (5U)
+#define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
+#define TPM_CONF_DBGMODE_MASK (0xC0U)
+#define TPM_CONF_DBGMODE_SHIFT (6U)
+#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
+#define TPM_CONF_GTBEEN_MASK (0x200U)
+#define TPM_CONF_GTBEEN_SHIFT (9U)
+#define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
+#define TPM_CONF_CSOT_MASK (0x10000U)
+#define TPM_CONF_CSOT_SHIFT (16U)
+#define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
+#define TPM_CONF_CSOO_MASK (0x20000U)
+#define TPM_CONF_CSOO_SHIFT (17U)
+#define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
+#define TPM_CONF_CROT_MASK (0x40000U)
+#define TPM_CONF_CROT_SHIFT (18U)
+#define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
+#define TPM_CONF_TRGSEL_MASK (0xF000000U)
+#define TPM_CONF_TRGSEL_SHIFT (24U)
+#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group TPM_Register_Masks */
+
+
+/* TPM - Peripheral instance base addresses */
+/** Peripheral TPM0 base address */
+#define TPM0_BASE (0x40038000u)
+/** Peripheral TPM0 base pointer */
+#define TPM0 ((TPM_Type *)TPM0_BASE)
+/** Peripheral TPM1 base address */
+#define TPM1_BASE (0x40039000u)
+/** Peripheral TPM1 base pointer */
+#define TPM1 ((TPM_Type *)TPM1_BASE)
+/** Peripheral TPM2 base address */
+#define TPM2_BASE (0x4003A000u)
+/** Peripheral TPM2 base pointer */
+#define TPM2 ((TPM_Type *)TPM2_BASE)
+/** Array initializer of TPM peripheral base addresses */
+#define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE }
+/** Array initializer of TPM peripheral base pointers */
+#define TPM_BASE_PTRS { TPM0, TPM1, TPM2 }
+/** Interrupt vectors for the TPM peripheral type */
+#define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn }
+
+/*!
+ * @}
+ */ /* end of group TPM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TSI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
+ * @{
+ */
+
+/** TSI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
+ __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
+ __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
+} TSI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TSI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TSI_Register_Masks TSI Register Masks
+ * @{
+ */
+
+/*! @name GENCS - TSI General Control and Status Register */
+#define TSI_GENCS_CURSW_MASK (0x2U)
+#define TSI_GENCS_CURSW_SHIFT (1U)
+#define TSI_GENCS_CURSW(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK)
+#define TSI_GENCS_EOSF_MASK (0x4U)
+#define TSI_GENCS_EOSF_SHIFT (2U)
+#define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
+#define TSI_GENCS_SCNIP_MASK (0x8U)
+#define TSI_GENCS_SCNIP_SHIFT (3U)
+#define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
+#define TSI_GENCS_STM_MASK (0x10U)
+#define TSI_GENCS_STM_SHIFT (4U)
+#define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
+#define TSI_GENCS_STPE_MASK (0x20U)
+#define TSI_GENCS_STPE_SHIFT (5U)
+#define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
+#define TSI_GENCS_TSIIEN_MASK (0x40U)
+#define TSI_GENCS_TSIIEN_SHIFT (6U)
+#define TSI_GENCS_TSIIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK)
+#define TSI_GENCS_TSIEN_MASK (0x80U)
+#define TSI_GENCS_TSIEN_SHIFT (7U)
+#define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
+#define TSI_GENCS_NSCN_MASK (0x1F00U)
+#define TSI_GENCS_NSCN_SHIFT (8U)
+#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
+#define TSI_GENCS_PS_MASK (0xE000U)
+#define TSI_GENCS_PS_SHIFT (13U)
+#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
+#define TSI_GENCS_EXTCHRG_MASK (0x70000U)
+#define TSI_GENCS_EXTCHRG_SHIFT (16U)
+#define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK)
+#define TSI_GENCS_DVOLT_MASK (0x180000U)
+#define TSI_GENCS_DVOLT_SHIFT (19U)
+#define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK)
+#define TSI_GENCS_REFCHRG_MASK (0xE00000U)
+#define TSI_GENCS_REFCHRG_SHIFT (21U)
+#define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK)
+#define TSI_GENCS_MODE_MASK (0xF000000U)
+#define TSI_GENCS_MODE_SHIFT (24U)
+#define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK)
+#define TSI_GENCS_ESOR_MASK (0x10000000U)
+#define TSI_GENCS_ESOR_SHIFT (28U)
+#define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
+#define TSI_GENCS_OUTRGF_MASK (0x80000000U)
+#define TSI_GENCS_OUTRGF_SHIFT (31U)
+#define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
+
+/*! @name DATA - TSI DATA Register */
+#define TSI_DATA_TSICNT_MASK (0xFFFFU)
+#define TSI_DATA_TSICNT_SHIFT (0U)
+#define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK)
+#define TSI_DATA_SWTS_MASK (0x400000U)
+#define TSI_DATA_SWTS_SHIFT (22U)
+#define TSI_DATA_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK)
+#define TSI_DATA_DMAEN_MASK (0x800000U)
+#define TSI_DATA_DMAEN_SHIFT (23U)
+#define TSI_DATA_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK)
+#define TSI_DATA_TSICH_MASK (0xF0000000U)
+#define TSI_DATA_TSICH_SHIFT (28U)
+#define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK)
+
+/*! @name TSHD - TSI Threshold Register */
+#define TSI_TSHD_THRESL_MASK (0xFFFFU)
+#define TSI_TSHD_THRESL_SHIFT (0U)
+#define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK)
+#define TSI_TSHD_THRESH_MASK (0xFFFF0000U)
+#define TSI_TSHD_THRESH_SHIFT (16U)
+#define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group TSI_Register_Masks */
+
+
+/* TSI - Peripheral instance base addresses */
+/** Peripheral TSI0 base address */
+#define TSI0_BASE (0x40045000u)
+/** Peripheral TSI0 base pointer */
+#define TSI0 ((TSI_Type *)TSI0_BASE)
+/** Array initializer of TSI peripheral base addresses */
+#define TSI_BASE_ADDRS { TSI0_BASE }
+/** Array initializer of TSI peripheral base pointers */
+#define TSI_BASE_PTRS { TSI0 }
+/** Interrupt vectors for the TSI peripheral type */
+#define TSI_IRQS { TSI0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group TSI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0x8 */
+} UART_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/*! @name BDH - UART Baud Rate Register: High */
+#define UART_BDH_SBR_MASK (0x1FU)
+#define UART_BDH_SBR_SHIFT (0U)
+#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
+#define UART_BDH_SBNS_MASK (0x20U)
+#define UART_BDH_SBNS_SHIFT (5U)
+#define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK)
+#define UART_BDH_RXEDGIE_MASK (0x40U)
+#define UART_BDH_RXEDGIE_SHIFT (6U)
+#define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
+#define UART_BDH_LBKDIE_MASK (0x80U)
+#define UART_BDH_LBKDIE_SHIFT (7U)
+#define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
+
+/*! @name BDL - UART Baud Rate Register: Low */
+#define UART_BDL_SBR_MASK (0xFFU)
+#define UART_BDL_SBR_SHIFT (0U)
+#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
+
+/*! @name C1 - UART Control Register 1 */
+#define UART_C1_PT_MASK (0x1U)
+#define UART_C1_PT_SHIFT (0U)
+#define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
+#define UART_C1_PE_MASK (0x2U)
+#define UART_C1_PE_SHIFT (1U)
+#define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
+#define UART_C1_ILT_MASK (0x4U)
+#define UART_C1_ILT_SHIFT (2U)
+#define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
+#define UART_C1_WAKE_MASK (0x8U)
+#define UART_C1_WAKE_SHIFT (3U)
+#define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
+#define UART_C1_M_MASK (0x10U)
+#define UART_C1_M_SHIFT (4U)
+#define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
+#define UART_C1_RSRC_MASK (0x20U)
+#define UART_C1_RSRC_SHIFT (5U)
+#define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
+#define UART_C1_UARTSWAI_MASK (0x40U)
+#define UART_C1_UARTSWAI_SHIFT (6U)
+#define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
+#define UART_C1_LOOPS_MASK (0x80U)
+#define UART_C1_LOOPS_SHIFT (7U)
+#define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
+
+/*! @name C2 - UART Control Register 2 */
+#define UART_C2_SBK_MASK (0x1U)
+#define UART_C2_SBK_SHIFT (0U)
+#define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
+#define UART_C2_RWU_MASK (0x2U)
+#define UART_C2_RWU_SHIFT (1U)
+#define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
+#define UART_C2_RE_MASK (0x4U)
+#define UART_C2_RE_SHIFT (2U)
+#define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
+#define UART_C2_TE_MASK (0x8U)
+#define UART_C2_TE_SHIFT (3U)
+#define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
+#define UART_C2_ILIE_MASK (0x10U)
+#define UART_C2_ILIE_SHIFT (4U)
+#define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
+#define UART_C2_RIE_MASK (0x20U)
+#define UART_C2_RIE_SHIFT (5U)
+#define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
+#define UART_C2_TCIE_MASK (0x40U)
+#define UART_C2_TCIE_SHIFT (6U)
+#define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
+#define UART_C2_TIE_MASK (0x80U)
+#define UART_C2_TIE_SHIFT (7U)
+#define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
+
+/*! @name S1 - UART Status Register 1 */
+#define UART_S1_PF_MASK (0x1U)
+#define UART_S1_PF_SHIFT (0U)
+#define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
+#define UART_S1_FE_MASK (0x2U)
+#define UART_S1_FE_SHIFT (1U)
+#define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
+#define UART_S1_NF_MASK (0x4U)
+#define UART_S1_NF_SHIFT (2U)
+#define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
+#define UART_S1_OR_MASK (0x8U)
+#define UART_S1_OR_SHIFT (3U)
+#define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
+#define UART_S1_IDLE_MASK (0x10U)
+#define UART_S1_IDLE_SHIFT (4U)
+#define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
+#define UART_S1_RDRF_MASK (0x20U)
+#define UART_S1_RDRF_SHIFT (5U)
+#define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
+#define UART_S1_TC_MASK (0x40U)
+#define UART_S1_TC_SHIFT (6U)
+#define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
+#define UART_S1_TDRE_MASK (0x80U)
+#define UART_S1_TDRE_SHIFT (7U)
+#define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
+
+/*! @name S2 - UART Status Register 2 */
+#define UART_S2_RAF_MASK (0x1U)
+#define UART_S2_RAF_SHIFT (0U)
+#define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
+#define UART_S2_LBKDE_MASK (0x2U)
+#define UART_S2_LBKDE_SHIFT (1U)
+#define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
+#define UART_S2_BRK13_MASK (0x4U)
+#define UART_S2_BRK13_SHIFT (2U)
+#define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
+#define UART_S2_RWUID_MASK (0x8U)
+#define UART_S2_RWUID_SHIFT (3U)
+#define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
+#define UART_S2_RXINV_MASK (0x10U)
+#define UART_S2_RXINV_SHIFT (4U)
+#define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
+#define UART_S2_RXEDGIF_MASK (0x40U)
+#define UART_S2_RXEDGIF_SHIFT (6U)
+#define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
+#define UART_S2_LBKDIF_MASK (0x80U)
+#define UART_S2_LBKDIF_SHIFT (7U)
+#define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
+
+/*! @name C3 - UART Control Register 3 */
+#define UART_C3_PEIE_MASK (0x1U)
+#define UART_C3_PEIE_SHIFT (0U)
+#define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
+#define UART_C3_FEIE_MASK (0x2U)
+#define UART_C3_FEIE_SHIFT (1U)
+#define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
+#define UART_C3_NEIE_MASK (0x4U)
+#define UART_C3_NEIE_SHIFT (2U)
+#define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
+#define UART_C3_ORIE_MASK (0x8U)
+#define UART_C3_ORIE_SHIFT (3U)
+#define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
+#define UART_C3_TXINV_MASK (0x10U)
+#define UART_C3_TXINV_SHIFT (4U)
+#define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
+#define UART_C3_TXDIR_MASK (0x20U)
+#define UART_C3_TXDIR_SHIFT (5U)
+#define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
+#define UART_C3_T8_MASK (0x40U)
+#define UART_C3_T8_SHIFT (6U)
+#define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
+#define UART_C3_R8_MASK (0x80U)
+#define UART_C3_R8_SHIFT (7U)
+#define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
+
+/*! @name D - UART Data Register */
+#define UART_D_R0T0_MASK (0x1U)
+#define UART_D_R0T0_SHIFT (0U)
+#define UART_D_R0T0(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R0T0_SHIFT)) & UART_D_R0T0_MASK)
+#define UART_D_R1T1_MASK (0x2U)
+#define UART_D_R1T1_SHIFT (1U)
+#define UART_D_R1T1(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R1T1_SHIFT)) & UART_D_R1T1_MASK)
+#define UART_D_R2T2_MASK (0x4U)
+#define UART_D_R2T2_SHIFT (2U)
+#define UART_D_R2T2(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R2T2_SHIFT)) & UART_D_R2T2_MASK)
+#define UART_D_R3T3_MASK (0x8U)
+#define UART_D_R3T3_SHIFT (3U)
+#define UART_D_R3T3(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R3T3_SHIFT)) & UART_D_R3T3_MASK)
+#define UART_D_R4T4_MASK (0x10U)
+#define UART_D_R4T4_SHIFT (4U)
+#define UART_D_R4T4(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R4T4_SHIFT)) & UART_D_R4T4_MASK)
+#define UART_D_R5T5_MASK (0x20U)
+#define UART_D_R5T5_SHIFT (5U)
+#define UART_D_R5T5(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R5T5_SHIFT)) & UART_D_R5T5_MASK)
+#define UART_D_R6T6_MASK (0x40U)
+#define UART_D_R6T6_SHIFT (6U)
+#define UART_D_R6T6(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R6T6_SHIFT)) & UART_D_R6T6_MASK)
+#define UART_D_R7T7_MASK (0x80U)
+#define UART_D_R7T7_SHIFT (7U)
+#define UART_D_R7T7(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R7T7_SHIFT)) & UART_D_R7T7_MASK)
+
+/*! @name C4 - UART Control Register 4 */
+#define UART_C4_RDMAS_MASK (0x20U)
+#define UART_C4_RDMAS_SHIFT (5U)
+#define UART_C4_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_RDMAS_SHIFT)) & UART_C4_RDMAS_MASK)
+#define UART_C4_TDMAS_MASK (0x80U)
+#define UART_C4_TDMAS_SHIFT (7U)
+#define UART_C4_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_TDMAS_SHIFT)) & UART_C4_TDMAS_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART1 base address */
+#define UART1_BASE (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1 ((UART_Type *)UART1_BASE)
+/** Peripheral UART2 base address */
+#define UART2_BASE (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2 ((UART_Type *)UART2_BASE)
+/** Array initializer of UART peripheral base addresses */
+#define UART_BASE_ADDRS { 0u, UART1_BASE, UART2_BASE }
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASE_PTRS { (UART_Type *)0u, UART1, UART2 }
+/** Interrupt vectors for the UART peripheral type */
+#define UART_RX_TX_IRQS { NotAvail_IRQn, UART1_IRQn, UART2_IRQn }
+#define UART_ERR_IRQS { NotAvail_IRQn, UART1_IRQn, UART2_IRQn }
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART0 Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
+ * @{
+ */
+
+/** UART0 - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
+ __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
+ __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
+} UART0_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UART0 Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART0_Register_Masks UART0 Register Masks
+ * @{
+ */
+
+/*! @name BDH - UART Baud Rate Register High */
+#define UART0_BDH_SBR_MASK (0x1FU)
+#define UART0_BDH_SBR_SHIFT (0U)
+#define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_SBR_SHIFT)) & UART0_BDH_SBR_MASK)
+#define UART0_BDH_SBNS_MASK (0x20U)
+#define UART0_BDH_SBNS_SHIFT (5U)
+#define UART0_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_SBNS_SHIFT)) & UART0_BDH_SBNS_MASK)
+#define UART0_BDH_RXEDGIE_MASK (0x40U)
+#define UART0_BDH_RXEDGIE_SHIFT (6U)
+#define UART0_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_RXEDGIE_SHIFT)) & UART0_BDH_RXEDGIE_MASK)
+#define UART0_BDH_LBKDIE_MASK (0x80U)
+#define UART0_BDH_LBKDIE_SHIFT (7U)
+#define UART0_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_LBKDIE_SHIFT)) & UART0_BDH_LBKDIE_MASK)
+
+/*! @name BDL - UART Baud Rate Register Low */
+#define UART0_BDL_SBR_MASK (0xFFU)
+#define UART0_BDL_SBR_SHIFT (0U)
+#define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDL_SBR_SHIFT)) & UART0_BDL_SBR_MASK)
+
+/*! @name C1 - UART Control Register 1 */
+#define UART0_C1_PT_MASK (0x1U)
+#define UART0_C1_PT_SHIFT (0U)
+#define UART0_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_PT_SHIFT)) & UART0_C1_PT_MASK)
+#define UART0_C1_PE_MASK (0x2U)
+#define UART0_C1_PE_SHIFT (1U)
+#define UART0_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_PE_SHIFT)) & UART0_C1_PE_MASK)
+#define UART0_C1_ILT_MASK (0x4U)
+#define UART0_C1_ILT_SHIFT (2U)
+#define UART0_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_ILT_SHIFT)) & UART0_C1_ILT_MASK)
+#define UART0_C1_WAKE_MASK (0x8U)
+#define UART0_C1_WAKE_SHIFT (3U)
+#define UART0_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_WAKE_SHIFT)) & UART0_C1_WAKE_MASK)
+#define UART0_C1_M_MASK (0x10U)
+#define UART0_C1_M_SHIFT (4U)
+#define UART0_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_M_SHIFT)) & UART0_C1_M_MASK)
+#define UART0_C1_RSRC_MASK (0x20U)
+#define UART0_C1_RSRC_SHIFT (5U)
+#define UART0_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_RSRC_SHIFT)) & UART0_C1_RSRC_MASK)
+#define UART0_C1_DOZEEN_MASK (0x40U)
+#define UART0_C1_DOZEEN_SHIFT (6U)
+#define UART0_C1_DOZEEN(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_DOZEEN_SHIFT)) & UART0_C1_DOZEEN_MASK)
+#define UART0_C1_LOOPS_MASK (0x80U)
+#define UART0_C1_LOOPS_SHIFT (7U)
+#define UART0_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_LOOPS_SHIFT)) & UART0_C1_LOOPS_MASK)
+
+/*! @name C2 - UART Control Register 2 */
+#define UART0_C2_SBK_MASK (0x1U)
+#define UART0_C2_SBK_SHIFT (0U)
+#define UART0_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_SBK_SHIFT)) & UART0_C2_SBK_MASK)
+#define UART0_C2_RWU_MASK (0x2U)
+#define UART0_C2_RWU_SHIFT (1U)
+#define UART0_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_RWU_SHIFT)) & UART0_C2_RWU_MASK)
+#define UART0_C2_RE_MASK (0x4U)
+#define UART0_C2_RE_SHIFT (2U)
+#define UART0_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_RE_SHIFT)) & UART0_C2_RE_MASK)
+#define UART0_C2_TE_MASK (0x8U)
+#define UART0_C2_TE_SHIFT (3U)
+#define UART0_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_TE_SHIFT)) & UART0_C2_TE_MASK)
+#define UART0_C2_ILIE_MASK (0x10U)
+#define UART0_C2_ILIE_SHIFT (4U)
+#define UART0_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_ILIE_SHIFT)) & UART0_C2_ILIE_MASK)
+#define UART0_C2_RIE_MASK (0x20U)
+#define UART0_C2_RIE_SHIFT (5U)
+#define UART0_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_RIE_SHIFT)) & UART0_C2_RIE_MASK)
+#define UART0_C2_TCIE_MASK (0x40U)
+#define UART0_C2_TCIE_SHIFT (6U)
+#define UART0_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_TCIE_SHIFT)) & UART0_C2_TCIE_MASK)
+#define UART0_C2_TIE_MASK (0x80U)
+#define UART0_C2_TIE_SHIFT (7U)
+#define UART0_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_TIE_SHIFT)) & UART0_C2_TIE_MASK)
+
+/*! @name S1 - UART Status Register 1 */
+#define UART0_S1_PF_MASK (0x1U)
+#define UART0_S1_PF_SHIFT (0U)
+#define UART0_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_PF_SHIFT)) & UART0_S1_PF_MASK)
+#define UART0_S1_FE_MASK (0x2U)
+#define UART0_S1_FE_SHIFT (1U)
+#define UART0_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_FE_SHIFT)) & UART0_S1_FE_MASK)
+#define UART0_S1_NF_MASK (0x4U)
+#define UART0_S1_NF_SHIFT (2U)
+#define UART0_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_NF_SHIFT)) & UART0_S1_NF_MASK)
+#define UART0_S1_OR_MASK (0x8U)
+#define UART0_S1_OR_SHIFT (3U)
+#define UART0_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_OR_SHIFT)) & UART0_S1_OR_MASK)
+#define UART0_S1_IDLE_MASK (0x10U)
+#define UART0_S1_IDLE_SHIFT (4U)
+#define UART0_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_IDLE_SHIFT)) & UART0_S1_IDLE_MASK)
+#define UART0_S1_RDRF_MASK (0x20U)
+#define UART0_S1_RDRF_SHIFT (5U)
+#define UART0_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_RDRF_SHIFT)) & UART0_S1_RDRF_MASK)
+#define UART0_S1_TC_MASK (0x40U)
+#define UART0_S1_TC_SHIFT (6U)
+#define UART0_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_TC_SHIFT)) & UART0_S1_TC_MASK)
+#define UART0_S1_TDRE_MASK (0x80U)
+#define UART0_S1_TDRE_SHIFT (7U)
+#define UART0_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_TDRE_SHIFT)) & UART0_S1_TDRE_MASK)
+
+/*! @name S2 - UART Status Register 2 */
+#define UART0_S2_RAF_MASK (0x1U)
+#define UART0_S2_RAF_SHIFT (0U)
+#define UART0_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RAF_SHIFT)) & UART0_S2_RAF_MASK)
+#define UART0_S2_LBKDE_MASK (0x2U)
+#define UART0_S2_LBKDE_SHIFT (1U)
+#define UART0_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_LBKDE_SHIFT)) & UART0_S2_LBKDE_MASK)
+#define UART0_S2_BRK13_MASK (0x4U)
+#define UART0_S2_BRK13_SHIFT (2U)
+#define UART0_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_BRK13_SHIFT)) & UART0_S2_BRK13_MASK)
+#define UART0_S2_RWUID_MASK (0x8U)
+#define UART0_S2_RWUID_SHIFT (3U)
+#define UART0_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RWUID_SHIFT)) & UART0_S2_RWUID_MASK)
+#define UART0_S2_RXINV_MASK (0x10U)
+#define UART0_S2_RXINV_SHIFT (4U)
+#define UART0_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RXINV_SHIFT)) & UART0_S2_RXINV_MASK)
+#define UART0_S2_MSBF_MASK (0x20U)
+#define UART0_S2_MSBF_SHIFT (5U)
+#define UART0_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_MSBF_SHIFT)) & UART0_S2_MSBF_MASK)
+#define UART0_S2_RXEDGIF_MASK (0x40U)
+#define UART0_S2_RXEDGIF_SHIFT (6U)
+#define UART0_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RXEDGIF_SHIFT)) & UART0_S2_RXEDGIF_MASK)
+#define UART0_S2_LBKDIF_MASK (0x80U)
+#define UART0_S2_LBKDIF_SHIFT (7U)
+#define UART0_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_LBKDIF_SHIFT)) & UART0_S2_LBKDIF_MASK)
+
+/*! @name C3 - UART Control Register 3 */
+#define UART0_C3_PEIE_MASK (0x1U)
+#define UART0_C3_PEIE_SHIFT (0U)
+#define UART0_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_PEIE_SHIFT)) & UART0_C3_PEIE_MASK)
+#define UART0_C3_FEIE_MASK (0x2U)
+#define UART0_C3_FEIE_SHIFT (1U)
+#define UART0_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_FEIE_SHIFT)) & UART0_C3_FEIE_MASK)
+#define UART0_C3_NEIE_MASK (0x4U)
+#define UART0_C3_NEIE_SHIFT (2U)
+#define UART0_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_NEIE_SHIFT)) & UART0_C3_NEIE_MASK)
+#define UART0_C3_ORIE_MASK (0x8U)
+#define UART0_C3_ORIE_SHIFT (3U)
+#define UART0_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_ORIE_SHIFT)) & UART0_C3_ORIE_MASK)
+#define UART0_C3_TXINV_MASK (0x10U)
+#define UART0_C3_TXINV_SHIFT (4U)
+#define UART0_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_TXINV_SHIFT)) & UART0_C3_TXINV_MASK)
+#define UART0_C3_TXDIR_MASK (0x20U)
+#define UART0_C3_TXDIR_SHIFT (5U)
+#define UART0_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_TXDIR_SHIFT)) & UART0_C3_TXDIR_MASK)
+#define UART0_C3_R9T8_MASK (0x40U)
+#define UART0_C3_R9T8_SHIFT (6U)
+#define UART0_C3_R9T8(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_R9T8_SHIFT)) & UART0_C3_R9T8_MASK)
+#define UART0_C3_R8T9_MASK (0x80U)
+#define UART0_C3_R8T9_SHIFT (7U)
+#define UART0_C3_R8T9(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_R8T9_SHIFT)) & UART0_C3_R8T9_MASK)
+
+/*! @name D - UART Data Register */
+#define UART0_D_R0T0_MASK (0x1U)
+#define UART0_D_R0T0_SHIFT (0U)
+#define UART0_D_R0T0(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R0T0_SHIFT)) & UART0_D_R0T0_MASK)
+#define UART0_D_R1T1_MASK (0x2U)
+#define UART0_D_R1T1_SHIFT (1U)
+#define UART0_D_R1T1(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R1T1_SHIFT)) & UART0_D_R1T1_MASK)
+#define UART0_D_R2T2_MASK (0x4U)
+#define UART0_D_R2T2_SHIFT (2U)
+#define UART0_D_R2T2(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R2T2_SHIFT)) & UART0_D_R2T2_MASK)
+#define UART0_D_R3T3_MASK (0x8U)
+#define UART0_D_R3T3_SHIFT (3U)
+#define UART0_D_R3T3(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R3T3_SHIFT)) & UART0_D_R3T3_MASK)
+#define UART0_D_R4T4_MASK (0x10U)
+#define UART0_D_R4T4_SHIFT (4U)
+#define UART0_D_R4T4(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R4T4_SHIFT)) & UART0_D_R4T4_MASK)
+#define UART0_D_R5T5_MASK (0x20U)
+#define UART0_D_R5T5_SHIFT (5U)
+#define UART0_D_R5T5(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R5T5_SHIFT)) & UART0_D_R5T5_MASK)
+#define UART0_D_R6T6_MASK (0x40U)
+#define UART0_D_R6T6_SHIFT (6U)
+#define UART0_D_R6T6(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R6T6_SHIFT)) & UART0_D_R6T6_MASK)
+#define UART0_D_R7T7_MASK (0x80U)
+#define UART0_D_R7T7_SHIFT (7U)
+#define UART0_D_R7T7(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R7T7_SHIFT)) & UART0_D_R7T7_MASK)
+
+/*! @name MA1 - UART Match Address Registers 1 */
+#define UART0_MA1_MA_MASK (0xFFU)
+#define UART0_MA1_MA_SHIFT (0U)
+#define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART0_MA1_MA_SHIFT)) & UART0_MA1_MA_MASK)
+
+/*! @name MA2 - UART Match Address Registers 2 */
+#define UART0_MA2_MA_MASK (0xFFU)
+#define UART0_MA2_MA_SHIFT (0U)
+#define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART0_MA2_MA_SHIFT)) & UART0_MA2_MA_MASK)
+
+/*! @name C4 - UART Control Register 4 */
+#define UART0_C4_OSR_MASK (0x1FU)
+#define UART0_C4_OSR_SHIFT (0U)
+#define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_OSR_SHIFT)) & UART0_C4_OSR_MASK)
+#define UART0_C4_M10_MASK (0x20U)
+#define UART0_C4_M10_SHIFT (5U)
+#define UART0_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_M10_SHIFT)) & UART0_C4_M10_MASK)
+#define UART0_C4_MAEN2_MASK (0x40U)
+#define UART0_C4_MAEN2_SHIFT (6U)
+#define UART0_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_MAEN2_SHIFT)) & UART0_C4_MAEN2_MASK)
+#define UART0_C4_MAEN1_MASK (0x80U)
+#define UART0_C4_MAEN1_SHIFT (7U)
+#define UART0_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_MAEN1_SHIFT)) & UART0_C4_MAEN1_MASK)
+
+/*! @name C5 - UART Control Register 5 */
+#define UART0_C5_RESYNCDIS_MASK (0x1U)
+#define UART0_C5_RESYNCDIS_SHIFT (0U)
+#define UART0_C5_RESYNCDIS(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_RESYNCDIS_SHIFT)) & UART0_C5_RESYNCDIS_MASK)
+#define UART0_C5_BOTHEDGE_MASK (0x2U)
+#define UART0_C5_BOTHEDGE_SHIFT (1U)
+#define UART0_C5_BOTHEDGE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_BOTHEDGE_SHIFT)) & UART0_C5_BOTHEDGE_MASK)
+#define UART0_C5_RDMAE_MASK (0x20U)
+#define UART0_C5_RDMAE_SHIFT (5U)
+#define UART0_C5_RDMAE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_RDMAE_SHIFT)) & UART0_C5_RDMAE_MASK)
+#define UART0_C5_TDMAE_MASK (0x80U)
+#define UART0_C5_TDMAE_SHIFT (7U)
+#define UART0_C5_TDMAE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_TDMAE_SHIFT)) & UART0_C5_TDMAE_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group UART0_Register_Masks */
+
+
+/* UART0 - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0 ((UART0_Type *)UART0_BASE)
+/** Array initializer of UART0 peripheral base addresses */
+#define UART0_BASE_ADDRS { UART0_BASE }
+/** Array initializer of UART0 peripheral base pointers */
+#define UART0_BASE_PTRS { UART0 }
+/** Interrupt vectors for the UART0 peripheral type */
+#define UART0_RX_TX_IRQS { UART0_IRQn }
+#define UART0_ERR_IRQS { UART0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group UART0_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+ __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
+ uint8_t RESERVED_0[3];
+ __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
+ uint8_t RESERVED_1[3];
+ __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
+ uint8_t RESERVED_2[3];
+ __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
+ uint8_t RESERVED_3[3];
+ __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
+ uint8_t RESERVED_4[3];
+ __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
+ uint8_t RESERVED_5[3];
+ __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
+ uint8_t RESERVED_6[3];
+ __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
+ uint8_t RESERVED_7[99];
+ __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
+ uint8_t RESERVED_8[3];
+ __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
+ uint8_t RESERVED_9[3];
+ __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
+ uint8_t RESERVED_10[3];
+ __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
+ uint8_t RESERVED_11[3];
+ __I uint8_t STAT; /**< Status register, offset: 0x90 */
+ uint8_t RESERVED_12[3];
+ __IO uint8_t CTL; /**< Control register, offset: 0x94 */
+ uint8_t RESERVED_13[3];
+ __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
+ uint8_t RESERVED_14[3];
+ __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
+ uint8_t RESERVED_15[3];
+ __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
+ uint8_t RESERVED_16[3];
+ __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
+ uint8_t RESERVED_17[3];
+ __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
+ uint8_t RESERVED_18[3];
+ __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
+ uint8_t RESERVED_19[3];
+ __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
+ uint8_t RESERVED_20[3];
+ __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
+ uint8_t RESERVED_21[11];
+ struct { /* offset: 0xC0, array step: 0x4 */
+ __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_0[3];
+ } ENDPOINT[16];
+ __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
+ uint8_t RESERVED_22[3];
+ __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
+ uint8_t RESERVED_23[3];
+ __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
+ uint8_t RESERVED_24[3];
+ __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
+ uint8_t RESERVED_25[7];
+ __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
+} USB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/*! @name PERID - Peripheral ID register */
+#define USB_PERID_ID_MASK (0x3FU)
+#define USB_PERID_ID_SHIFT (0U)
+#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
+
+/*! @name IDCOMP - Peripheral ID Complement register */
+#define USB_IDCOMP_NID_MASK (0x3FU)
+#define USB_IDCOMP_NID_SHIFT (0U)
+#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
+
+/*! @name REV - Peripheral Revision register */
+#define USB_REV_REV_MASK (0xFFU)
+#define USB_REV_REV_SHIFT (0U)
+#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
+
+/*! @name ADDINFO - Peripheral Additional Info register */
+#define USB_ADDINFO_IEHOST_MASK (0x1U)
+#define USB_ADDINFO_IEHOST_SHIFT (0U)
+#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
+#define USB_ADDINFO_IRQNUM_MASK (0xF8U)
+#define USB_ADDINFO_IRQNUM_SHIFT (3U)
+#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IRQNUM_SHIFT)) & USB_ADDINFO_IRQNUM_MASK)
+
+/*! @name OTGISTAT - OTG Interrupt Status register */
+#define USB_OTGISTAT_AVBUSCHG_MASK (0x1U)
+#define USB_OTGISTAT_AVBUSCHG_SHIFT (0U)
+#define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK)
+#define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U)
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U)
+#define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK)
+#define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U)
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U)
+#define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK)
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
+#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
+#define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
+#define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
+#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
+#define USB_OTGISTAT_IDCHG_MASK (0x80U)
+#define USB_OTGISTAT_IDCHG_SHIFT (7U)
+#define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK)
+
+/*! @name OTGICR - OTG Interrupt Control register */
+#define USB_OTGICR_AVBUSEN_MASK (0x1U)
+#define USB_OTGICR_AVBUSEN_SHIFT (0U)
+#define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK)
+#define USB_OTGICR_BSESSEN_MASK (0x4U)
+#define USB_OTGICR_BSESSEN_SHIFT (2U)
+#define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK)
+#define USB_OTGICR_SESSVLDEN_MASK (0x8U)
+#define USB_OTGICR_SESSVLDEN_SHIFT (3U)
+#define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK)
+#define USB_OTGICR_LINESTATEEN_MASK (0x20U)
+#define USB_OTGICR_LINESTATEEN_SHIFT (5U)
+#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
+#define USB_OTGICR_ONEMSECEN_MASK (0x40U)
+#define USB_OTGICR_ONEMSECEN_SHIFT (6U)
+#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
+#define USB_OTGICR_IDEN_MASK (0x80U)
+#define USB_OTGICR_IDEN_SHIFT (7U)
+#define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK)
+
+/*! @name OTGSTAT - OTG Status register */
+#define USB_OTGSTAT_AVBUSVLD_MASK (0x1U)
+#define USB_OTGSTAT_AVBUSVLD_SHIFT (0U)
+#define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK)
+#define USB_OTGSTAT_BSESSEND_MASK (0x4U)
+#define USB_OTGSTAT_BSESSEND_SHIFT (2U)
+#define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK)
+#define USB_OTGSTAT_SESS_VLD_MASK (0x8U)
+#define USB_OTGSTAT_SESS_VLD_SHIFT (3U)
+#define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK)
+#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
+#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
+#define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
+#define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
+#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
+#define USB_OTGSTAT_ID_MASK (0x80U)
+#define USB_OTGSTAT_ID_SHIFT (7U)
+#define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK)
+
+/*! @name OTGCTL - OTG Control register */
+#define USB_OTGCTL_OTGEN_MASK (0x4U)
+#define USB_OTGCTL_OTGEN_SHIFT (2U)
+#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
+#define USB_OTGCTL_DMLOW_MASK (0x10U)
+#define USB_OTGCTL_DMLOW_SHIFT (4U)
+#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
+#define USB_OTGCTL_DPLOW_MASK (0x20U)
+#define USB_OTGCTL_DPLOW_SHIFT (5U)
+#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
+#define USB_OTGCTL_DPHIGH_MASK (0x80U)
+#define USB_OTGCTL_DPHIGH_SHIFT (7U)
+#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
+
+/*! @name ISTAT - Interrupt Status register */
+#define USB_ISTAT_USBRST_MASK (0x1U)
+#define USB_ISTAT_USBRST_SHIFT (0U)
+#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
+#define USB_ISTAT_ERROR_MASK (0x2U)
+#define USB_ISTAT_ERROR_SHIFT (1U)
+#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
+#define USB_ISTAT_SOFTOK_MASK (0x4U)
+#define USB_ISTAT_SOFTOK_SHIFT (2U)
+#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
+#define USB_ISTAT_TOKDNE_MASK (0x8U)
+#define USB_ISTAT_TOKDNE_SHIFT (3U)
+#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
+#define USB_ISTAT_SLEEP_MASK (0x10U)
+#define USB_ISTAT_SLEEP_SHIFT (4U)
+#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
+#define USB_ISTAT_RESUME_MASK (0x20U)
+#define USB_ISTAT_RESUME_SHIFT (5U)
+#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
+#define USB_ISTAT_ATTACH_MASK (0x40U)
+#define USB_ISTAT_ATTACH_SHIFT (6U)
+#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
+#define USB_ISTAT_STALL_MASK (0x80U)
+#define USB_ISTAT_STALL_SHIFT (7U)
+#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
+
+/*! @name INTEN - Interrupt Enable register */
+#define USB_INTEN_USBRSTEN_MASK (0x1U)
+#define USB_INTEN_USBRSTEN_SHIFT (0U)
+#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
+#define USB_INTEN_ERROREN_MASK (0x2U)
+#define USB_INTEN_ERROREN_SHIFT (1U)
+#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
+#define USB_INTEN_SOFTOKEN_MASK (0x4U)
+#define USB_INTEN_SOFTOKEN_SHIFT (2U)
+#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
+#define USB_INTEN_TOKDNEEN_MASK (0x8U)
+#define USB_INTEN_TOKDNEEN_SHIFT (3U)
+#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
+#define USB_INTEN_SLEEPEN_MASK (0x10U)
+#define USB_INTEN_SLEEPEN_SHIFT (4U)
+#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
+#define USB_INTEN_RESUMEEN_MASK (0x20U)
+#define USB_INTEN_RESUMEEN_SHIFT (5U)
+#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
+#define USB_INTEN_ATTACHEN_MASK (0x40U)
+#define USB_INTEN_ATTACHEN_SHIFT (6U)
+#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
+#define USB_INTEN_STALLEN_MASK (0x80U)
+#define USB_INTEN_STALLEN_SHIFT (7U)
+#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
+
+/*! @name ERRSTAT - Error Interrupt Status register */
+#define USB_ERRSTAT_PIDERR_MASK (0x1U)
+#define USB_ERRSTAT_PIDERR_SHIFT (0U)
+#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
+#define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
+#define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
+#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
+#define USB_ERRSTAT_CRC16_MASK (0x4U)
+#define USB_ERRSTAT_CRC16_SHIFT (2U)
+#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
+#define USB_ERRSTAT_DFN8_MASK (0x8U)
+#define USB_ERRSTAT_DFN8_SHIFT (3U)
+#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
+#define USB_ERRSTAT_BTOERR_MASK (0x10U)
+#define USB_ERRSTAT_BTOERR_SHIFT (4U)
+#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
+#define USB_ERRSTAT_DMAERR_MASK (0x20U)
+#define USB_ERRSTAT_DMAERR_SHIFT (5U)
+#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
+#define USB_ERRSTAT_BTSERR_MASK (0x80U)
+#define USB_ERRSTAT_BTSERR_SHIFT (7U)
+#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
+
+/*! @name ERREN - Error Interrupt Enable register */
+#define USB_ERREN_PIDERREN_MASK (0x1U)
+#define USB_ERREN_PIDERREN_SHIFT (0U)
+#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
+#define USB_ERREN_CRC5EOFEN_MASK (0x2U)
+#define USB_ERREN_CRC5EOFEN_SHIFT (1U)
+#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
+#define USB_ERREN_CRC16EN_MASK (0x4U)
+#define USB_ERREN_CRC16EN_SHIFT (2U)
+#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
+#define USB_ERREN_DFN8EN_MASK (0x8U)
+#define USB_ERREN_DFN8EN_SHIFT (3U)
+#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
+#define USB_ERREN_BTOERREN_MASK (0x10U)
+#define USB_ERREN_BTOERREN_SHIFT (4U)
+#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
+#define USB_ERREN_DMAERREN_MASK (0x20U)
+#define USB_ERREN_DMAERREN_SHIFT (5U)
+#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
+#define USB_ERREN_BTSERREN_MASK (0x80U)
+#define USB_ERREN_BTSERREN_SHIFT (7U)
+#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
+
+/*! @name STAT - Status register */
+#define USB_STAT_ODD_MASK (0x4U)
+#define USB_STAT_ODD_SHIFT (2U)
+#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
+#define USB_STAT_TX_MASK (0x8U)
+#define USB_STAT_TX_SHIFT (3U)
+#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
+#define USB_STAT_ENDP_MASK (0xF0U)
+#define USB_STAT_ENDP_SHIFT (4U)
+#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
+
+/*! @name CTL - Control register */
+#define USB_CTL_USBENSOFEN_MASK (0x1U)
+#define USB_CTL_USBENSOFEN_SHIFT (0U)
+#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
+#define USB_CTL_ODDRST_MASK (0x2U)
+#define USB_CTL_ODDRST_SHIFT (1U)
+#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
+#define USB_CTL_RESUME_MASK (0x4U)
+#define USB_CTL_RESUME_SHIFT (2U)
+#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
+#define USB_CTL_HOSTMODEEN_MASK (0x8U)
+#define USB_CTL_HOSTMODEEN_SHIFT (3U)
+#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
+#define USB_CTL_RESET_MASK (0x10U)
+#define USB_CTL_RESET_SHIFT (4U)
+#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
+#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
+#define USB_CTL_SE0_MASK (0x40U)
+#define USB_CTL_SE0_SHIFT (6U)
+#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
+#define USB_CTL_JSTATE_MASK (0x80U)
+#define USB_CTL_JSTATE_SHIFT (7U)
+#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
+
+/*! @name ADDR - Address register */
+#define USB_ADDR_ADDR_MASK (0x7FU)
+#define USB_ADDR_ADDR_SHIFT (0U)
+#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK (0x80U)
+#define USB_ADDR_LSEN_SHIFT (7U)
+#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
+
+/*! @name BDTPAGE1 - BDT Page register 1 */
+#define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
+#define USB_BDTPAGE1_BDTBA_SHIFT (1U)
+#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
+
+/*! @name FRMNUML - Frame Number register Low */
+#define USB_FRMNUML_FRM_MASK (0xFFU)
+#define USB_FRMNUML_FRM_SHIFT (0U)
+#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
+
+/*! @name FRMNUMH - Frame Number register High */
+#define USB_FRMNUMH_FRM_MASK (0x7U)
+#define USB_FRMNUMH_FRM_SHIFT (0U)
+#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
+
+/*! @name TOKEN - Token register */
+#define USB_TOKEN_TOKENENDPT_MASK (0xFU)
+#define USB_TOKEN_TOKENENDPT_SHIFT (0U)
+#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK (0xF0U)
+#define USB_TOKEN_TOKENPID_SHIFT (4U)
+#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
+
+/*! @name SOFTHLD - SOF Threshold register */
+#define USB_SOFTHLD_CNT_MASK (0xFFU)
+#define USB_SOFTHLD_CNT_SHIFT (0U)
+#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
+
+/*! @name BDTPAGE2 - BDT Page Register 2 */
+#define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
+#define USB_BDTPAGE2_BDTBA_SHIFT (0U)
+#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
+
+/*! @name BDTPAGE3 - BDT Page Register 3 */
+#define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
+#define USB_BDTPAGE3_BDTBA_SHIFT (0U)
+#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
+
+/*! @name ENDPT - Endpoint Control register */
+#define USB_ENDPT_EPHSHK_MASK (0x1U)
+#define USB_ENDPT_EPHSHK_SHIFT (0U)
+#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
+#define USB_ENDPT_EPSTALL_MASK (0x2U)
+#define USB_ENDPT_EPSTALL_SHIFT (1U)
+#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
+#define USB_ENDPT_EPTXEN_MASK (0x4U)
+#define USB_ENDPT_EPTXEN_SHIFT (2U)
+#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
+#define USB_ENDPT_EPRXEN_MASK (0x8U)
+#define USB_ENDPT_EPRXEN_SHIFT (3U)
+#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
+#define USB_ENDPT_EPCTLDIS_MASK (0x10U)
+#define USB_ENDPT_EPCTLDIS_SHIFT (4U)
+#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
+#define USB_ENDPT_RETRYDIS_MASK (0x40U)
+#define USB_ENDPT_RETRYDIS_SHIFT (6U)
+#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
+#define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
+#define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
+#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
+
+/* The count of USB_ENDPT */
+#define USB_ENDPT_COUNT (16U)
+
+/*! @name USBCTRL - USB Control register */
+#define USB_USBCTRL_PDE_MASK (0x40U)
+#define USB_USBCTRL_PDE_SHIFT (6U)
+#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
+#define USB_USBCTRL_SUSP_MASK (0x80U)
+#define USB_USBCTRL_SUSP_SHIFT (7U)
+#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
+
+/*! @name OBSERVE - USB OTG Observe register */
+#define USB_OBSERVE_DMPD_MASK (0x10U)
+#define USB_OBSERVE_DMPD_SHIFT (4U)
+#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
+#define USB_OBSERVE_DPPD_MASK (0x40U)
+#define USB_OBSERVE_DPPD_SHIFT (6U)
+#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
+#define USB_OBSERVE_DPPU_MASK (0x80U)
+#define USB_OBSERVE_DPPU_SHIFT (7U)
+#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
+
+/*! @name CONTROL - USB OTG Control register */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
+#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
+
+/*! @name USBTRC0 - USB Transceiver Control register 0 */
+#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
+#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
+#define USB_USBTRC0_SYNC_DET_MASK (0x2U)
+#define USB_USBTRC0_SYNC_DET_SHIFT (1U)
+#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
+#define USB_USBTRC0_USBRESMEN_MASK (0x20U)
+#define USB_USBTRC0_USBRESMEN_SHIFT (5U)
+#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
+#define USB_USBTRC0_USBRESET_MASK (0x80U)
+#define USB_USBTRC0_USBRESET_SHIFT (7U)
+#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
+
+/*! @name USBFRMADJUST - Frame Adjust Register */
+#define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
+#define USB_USBFRMADJUST_ADJ_SHIFT (0U)
+#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0 ((USB_Type *)USB0_BASE)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS { USB0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma pop
+#elif defined(__CWCC__)
+ #pragma pop
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=default
+#else
+ #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SDK Compatibility
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
+ * @{
+ */
+
+#define FPTA_BASE FGPIOA_BASE
+#define FPTA FGPIOA
+#define FPTB_BASE FGPIOB_BASE
+#define FPTB FGPIOB
+#define FPTC_BASE FGPIOC_BASE
+#define FPTC FGPIOC
+#define FPTD_BASE FGPIOD_BASE
+#define FPTD FGPIOD
+#define FPTE_BASE FGPIOE_BASE
+#define FPTE FGPIOE
+#define PTA_BASE GPIOA_BASE
+#define PTA GPIOA
+#define PTB_BASE GPIOB_BASE
+#define PTB GPIOB
+#define PTC_BASE GPIOC_BASE
+#define PTC GPIOC
+#define PTD_BASE GPIOD_BASE
+#define PTD GPIOD
+#define PTE_BASE GPIOE_BASE
+#define PTE GPIOE
+#define I2C_FLT_STOPIE_MASK This_symbol_has_been_deprecated
+#define I2C_FLT_STOPIE_SHIFT This_symbol_has_been_deprecated
+#define I2S_RCR2_CLKMODE_MASK I2S_RCR2_MSEL_MASK
+#define I2S_RCR2_CLKMODE_SHIFT I2S_RCR2_MSEL_SHIFT
+#define I2S_RCR2_CLKMODE(x) I2S_RCR2_MSEL(x)
+#define I2S_TCR2_CLKMODE_MASK I2S_TCR2_MSEL_MASK
+#define I2S_TCR2_CLKMODE_SHIFT I2S_TCR2_MSEL_SHIFT
+#define I2S_TCR2_CLKMODE(x) I2S_TCR2_MSEL(x)
+#define MCG_S_LOLS_MASK MCG_S_LOLS0_MASK
+#define MCG_S_LOLS_SHIFT MCG_S_LOLS0_SHIFT
+#define NVIC_ISPR_SETPEND(x) (((uint32_t)(((uint32_t)(x))<<NVIC_ISPR_SETPEND_SHIFT))&NVIC_ISPR_SETPEND_MASK)
+#define LPTimer_IRQn LPTMR0_IRQn
+#define LPTimer_IRQHandler LPTMR0_IRQHandler
+#define LLW_IRQn LLWU_IRQn
+#define LLW_IRQHandler LLWU_IRQHandler
+
+/*!
+ * @}
+ */ /* end of group SDK_Compatibility_Symbols */
+
+
+#endif /* _MKL26Z4_H_ */
+
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/kl26z/MKL26Z4/MKL26Z4_features.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/freescale/kl26z/MKL26Z4/MKL26Z4_features.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,2368 @@ +/* +** ################################################################### +** Version: rev. 1.11, 2015-05-27 +** Build: b160217 +** +** Abstract: +** Chip specific module features. +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2012-12-12) +** Initial version. +** - rev. 1.1 (2013-04-12) +** SystemInit function fixed for clock configuration 1. +** Name of the interrupt num. 31 updated to reflect proper function. +** - rev. 1.2 (2014-01-30) +** Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum. +** - rev. 1.3 (2014-05-27) +** Updated to Kinetis SDK support standard. +** MCG OSC clock select supported (MCG_C7[OSCSEL]). +** - rev. 1.4 (2014-07-25) +** System initialization updated: +** - Prefix added to the system initialization parameterization constants to avoid name conflicts.. +** - VLLSx wake-up recovery added. +** - Delay of 1 ms added to SystemInit() to ensure stable FLL output in FEI and FEE MCG modes. +** - rev. 1.5 (2014-08-28) +** Update of system files - default clock configuration changed, fix of OSC initialization. +** Update of startup files - possibility to override DefaultISR added. +** - rev. 1.6 (2014-10-14) +** Renamed interrupt vector LPTimer to LPTMR0 +** - rev. 1.7 (2015-01-21) +** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances +** - rev. 1.8 (2015-02-18) +** Renamed interrupt vector LLW to LLWU +** - rev. 1.9 (2015-05-19) +** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT. +** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC. +** Added features for PORT. +** - rev. 1.10 (2015-05-25) +** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS +** - rev. 1.11 (2015-05-27) +** Several USB features added. +** +** ################################################################### +*/ + +#ifndef _MKL26Z4_FEATURES_H_ +#define _MKL26Z4_FEATURES_H_ + +/* SOC module features */ + +/* @brief ACMP availability on the SoC. */ +#define FSL_FEATURE_SOC_ACMP_COUNT (0) +/* @brief ADC16 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC16_COUNT (1) +/* @brief ADC12 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC12_COUNT (0) +/* @brief AFE availability on the SoC. */ +#define FSL_FEATURE_SOC_AFE_COUNT (0) +/* @brief AIPS availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPS_COUNT (0) +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (0) +/* @brief AXBS availability on the SoC. */ +#define FSL_FEATURE_SOC_AXBS_COUNT (0) +/* @brief ASMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ASMC_COUNT (0) +/* @brief CADC availability on the SoC. */ +#define FSL_FEATURE_SOC_CADC_COUNT (0) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) +/* @brief MMCAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMCAU_COUNT (0) +/* @brief CMP availability on the SoC. */ +#define FSL_FEATURE_SOC_CMP_COUNT (1) +/* @brief CMT availability on the SoC. */ +#define FSL_FEATURE_SOC_CMT_COUNT (0) +/* @brief CNC availability on the SoC. */ +#define FSL_FEATURE_SOC_CNC_COUNT (0) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (0) +/* @brief DAC availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC_COUNT (1) +/* @brief DAC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC32_COUNT (0) +/* @brief DCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_DCDC_COUNT (0) +/* @brief DDR availability on the SoC. */ +#define FSL_FEATURE_SOC_DDR_COUNT (0) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (1) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (0) +/* @brief DMAMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_DMAMUX_COUNT (1) +/* @brief DRY availability on the SoC. */ +#define FSL_FEATURE_SOC_DRY_COUNT (0) +/* @brief DSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_DSPI_COUNT (0) +/* @brief EMVSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EMVSIM_COUNT (0) +/* @brief ENC availability on the SoC. */ +#define FSL_FEATURE_SOC_ENC_COUNT (0) +/* @brief ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_ENET_COUNT (0) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (0) +/* @brief FB availability on the SoC. */ +#define FSL_FEATURE_SOC_FB_COUNT (0) +/* @brief FGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FGPIO_COUNT (5) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (0) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (0) +/* @brief FSKDT availability on the SoC. */ +#define FSL_FEATURE_SOC_FSKDT_COUNT (0) +/* @brief FTFA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFA_COUNT (1) +/* @brief FTFE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFE_COUNT (0) +/* @brief FTFL availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFL_COUNT (0) +/* @brief FTM availability on the SoC. */ +#define FSL_FEATURE_SOC_FTM_COUNT (0) +/* @brief FTMRA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRA_COUNT (0) +/* @brief FTMRE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRE_COUNT (0) +/* @brief FTMRH availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRH_COUNT (0) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (5) +/* @brief HSADC availability on the SoC. */ +#define FSL_FEATURE_SOC_HSADC_COUNT (0) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (1) +/* @brief ICS availability on the SoC. */ +#define FSL_FEATURE_SOC_ICS_COUNT (0) +/* @brief INTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INTMUX_COUNT (0) +/* @brief IRQ availability on the SoC. */ +#define FSL_FEATURE_SOC_IRQ_COUNT (0) +/* @brief KBI availability on the SoC. */ +#define FSL_FEATURE_SOC_KBI_COUNT (0) +/* @brief SLCD availability on the SoC. */ +#define FSL_FEATURE_SOC_SLCD_COUNT (0) +/* @brief LCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDC_COUNT (0) +/* @brief LDO availability on the SoC. */ +#define FSL_FEATURE_SOC_LDO_COUNT (0) +/* @brief LLWU availability on the SoC. */ +#define FSL_FEATURE_SOC_LLWU_COUNT (1) +/* @brief LMEM availability on the SoC. */ +#define FSL_FEATURE_SOC_LMEM_COUNT (0) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (0) +/* @brief LPIT availability on the SoC. */ +#define FSL_FEATURE_SOC_LPIT_COUNT (0) +/* @brief LPSCI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSCI_COUNT (1) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (0) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (1) +/* @brief LPTPM availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTPM_COUNT (0) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (0) +/* @brief LTC availability on the SoC. */ +#define FSL_FEATURE_SOC_LTC_COUNT (0) +/* @brief MC availability on the SoC. */ +#define FSL_FEATURE_SOC_MC_COUNT (0) +/* @brief MCG availability on the SoC. */ +#define FSL_FEATURE_SOC_MCG_COUNT (1) +/* @brief MCGLITE availability on the SoC. */ +#define FSL_FEATURE_SOC_MCGLITE_COUNT (0) +/* @brief MCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MCM_COUNT (1) +/* @brief MMAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMAU_COUNT (0) +/* @brief MMDVSQ availability on the SoC. */ +#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (0) +/* @brief MSCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCAN_COUNT (0) +/* @brief MSCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCM_COUNT (0) +/* @brief MTB availability on the SoC. */ +#define FSL_FEATURE_SOC_MTB_COUNT (1) +/* @brief MTBDWT availability on the SoC. */ +#define FSL_FEATURE_SOC_MTBDWT_COUNT (1) +/* @brief MU availability on the SoC. */ +#define FSL_FEATURE_SOC_MU_COUNT (0) +/* @brief NFC availability on the SoC. */ +#define FSL_FEATURE_SOC_NFC_COUNT (0) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (0) +/* @brief OSC availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC_COUNT (1) +/* @brief OSC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC32_COUNT (0) +/* @brief OTFAD availability on the SoC. */ +#define FSL_FEATURE_SOC_OTFAD_COUNT (0) +/* @brief PDB availability on the SoC. */ +#define FSL_FEATURE_SOC_PDB_COUNT (0) +/* @brief PCC availability on the SoC. */ +#define FSL_FEATURE_SOC_PCC_COUNT (0) +/* @brief PGA availability on the SoC. */ +#define FSL_FEATURE_SOC_PGA_COUNT (0) +/* @brief PIT availability on the SoC. */ +#define FSL_FEATURE_SOC_PIT_COUNT (1) +/* @brief PMC availability on the SoC. */ +#define FSL_FEATURE_SOC_PMC_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (5) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (0) +/* @brief PWT availability on the SoC. */ +#define FSL_FEATURE_SOC_PWT_COUNT (0) +/* @brief QuadSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_QuadSPI_COUNT (0) +/* @brief RCM availability on the SoC. */ +#define FSL_FEATURE_SOC_RCM_COUNT (1) +/* @brief RFSYS availability on the SoC. */ +#define FSL_FEATURE_SOC_RFSYS_COUNT (0) +/* @brief RFVBAT availability on the SoC. */ +#define FSL_FEATURE_SOC_RFVBAT_COUNT (0) +/* @brief RNG availability on the SoC. */ +#define FSL_FEATURE_SOC_RNG_COUNT (0) +/* @brief RNGB availability on the SoC. */ +#define FSL_FEATURE_SOC_RNGB_COUNT (0) +/* @brief ROM availability on the SoC. */ +#define FSL_FEATURE_SOC_ROM_COUNT (1) +/* @brief RSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_RSIM_COUNT (0) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (0) +/* @brief SCI availability on the SoC. */ +#define FSL_FEATURE_SOC_SCI_COUNT (0) +/* @brief SDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_SDHC_COUNT (0) +/* @brief SDRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_SDRAM_COUNT (0) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (0) +/* @brief SIM availability on the SoC. */ +#define FSL_FEATURE_SOC_SIM_COUNT (1) +/* @brief SMC availability on the SoC. */ +#define FSL_FEATURE_SOC_SMC_COUNT (1) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (2) +/* @brief TMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TMR_COUNT (0) +/* @brief TPM availability on the SoC. */ +#define FSL_FEATURE_SOC_TPM_COUNT (3) +/* @brief TRGMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_TRGMUX_COUNT (0) +/* @brief TRIAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_TRIAMP_COUNT (0) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (0) +/* @brief TSI availability on the SoC. */ +#define FSL_FEATURE_SOC_TSI_COUNT (1) +/* @brief TSTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TSTMR_COUNT (0) +/* @brief UART availability on the SoC. */ +#define FSL_FEATURE_SOC_UART_COUNT (2) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief USBDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBDCD_COUNT (0) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (0) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (0) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (0) +/* @brief XBAR availability on the SoC. */ +#define FSL_FEATURE_SOC_XBAR_COUNT (0) +/* @brief XBARA availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARA_COUNT (0) +/* @brief XBARB availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARB_COUNT (0) +/* @brief XCVR availability on the SoC. */ +#define FSL_FEATURE_SOC_XCVR_COUNT (0) +/* @brief XRDC availability on the SoC. */ +#define FSL_FEATURE_SOC_XRDC_COUNT (0) +/* @brief ZLL availability on the SoC. */ +#define FSL_FEATURE_SOC_ZLL_COUNT (0) + +/* ADC16 module features */ + +/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ +#define FSL_FEATURE_ADC16_HAS_PGA (0) +/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ +#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) +/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ +#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) +/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ +#define FSL_FEATURE_ADC16_HAS_DMA (1) +/* @brief Has differential mode (bitfield SC1x[DIFF]). */ +#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) +/* @brief Has FIFO (bit SC4[AFDEP]). */ +#define FSL_FEATURE_ADC16_HAS_FIFO (0) +/* @brief FIFO size if available (bitfield SC4[AFDEP]). */ +#define FSL_FEATURE_ADC16_FIFO_SIZE (0) +/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ +#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) +/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ +#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) +/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ +#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) +/* @brief Has HW averaging (bit SC3[AVGE]). */ +#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) +/* @brief Has offset correction (register OFS). */ +#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) +/* @brief Maximum ADC resolution. */ +#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) +/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ +#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) + +/* CMP module features */ + +/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ +#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) +/* @brief Has Window mode in CMP (register bit field CR1[WE]). */ +#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) +/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ +#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) +/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ +#define FSL_FEATURE_CMP_HAS_DMA (1) +/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ +#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1) +/* @brief Has DAC Test function in CMP (register DACTEST). */ +#define FSL_FEATURE_CMP_HAS_DAC_TEST (0) + +/* COP module features */ + +/* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */ +#define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (0) +/* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */ +#define FSL_FEATURE_COP_HAS_STOP_ENABLE (0) +/* @brief Has more clock sources like MCGIRC */ +#define FSL_FEATURE_COP_HAS_MORE_CLKSRC (0) +/* @brief Has the timeout long and short mode bit (COPC[COPCLKSEL] and COPC[COPCLKS]) */ +#define FSL_FEATURE_COP_HAS_LONGTIME_MODE (0) + +/* DAC module features */ + +/* @brief Define the size of hardware buffer */ +#define FSL_FEATURE_DAC_BUFFER_SIZE (2) +/* @brief Define whether the buffer supports watermark event detection or not. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (0) +/* @brief Define whether the buffer supports watermark selection detection or not. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (0) +/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (0) +/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (0) +/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (0) +/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (0) +/* @brief Define whether FIFO buffer mode is available or not. */ +#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0) +/* @brief Define whether swing buffer mode is available or not.. */ +#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0) + +/* DMA module features */ + +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_DMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMA_COUNT * 4) + +/* DMAMUX module features */ + +/* @brief Number of DMA channels (related to number of register CHCFGn). */ +#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 4) +/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ +#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) + +/* FLASH module features */ + +#if defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z128VLH4) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (1) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (0) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (0) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) + /* @brief Has flash cache control in MSCM module. */ + #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x49 Erase All Blocks Unsecure command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) + /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) + /* @brief Has 0x4B Erase All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) +#elif defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z128VMC4) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (1) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (0) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (0) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) + /* @brief Has flash cache control in MSCM module. */ + #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (65536) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x49 Erase All Blocks Unsecure command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) + /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) + /* @brief Has 0x4B Erase All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) +#elif defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL26Z256VMP4) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (1) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (0) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (0) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) + /* @brief Has flash cache control in MSCM module. */ + #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x49 Erase All Blocks Unsecure command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) + /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) + /* @brief Has 0x4B Erase All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) +#elif defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z32VLH4) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (1) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (0) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (0) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) + /* @brief Has flash cache control in MSCM module. */ + #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (32768) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x49 Erase All Blocks Unsecure command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) + /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) + /* @brief Has 0x4B Erase All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) +#elif defined(CPU_MKL26Z64VFM4) || defined(CPU_MKL26Z64VFT4) || defined(CPU_MKL26Z64VLH4) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (1) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (0) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (0) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) + /* @brief Has flash cache control in MSCM module. */ + #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (65536) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x49 Erase All Blocks Unsecure command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) + /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) + /* @brief Has 0x4B Erase All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) +#endif /* defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z128VLH4) */ + +/* GPIO module features */ + +/* @brief Has fast (single cycle) access capability via a dedicated memory region. */ +#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1) +/* @brief Has port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) + +/* I2C module features */ + +/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ +#define FSL_FEATURE_I2C_HAS_SMBUS (1) +/* @brief Maximum supported baud rate in kilobit per second. */ +#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (100) +/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ +#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (1) +/* @brief Has DMA support (register bit C1[DMAEN]). */ +#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) +/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) +/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) +/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ +#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) +/* @brief Maximum width of the glitch filter in number of bus clocks. */ +#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) +/* @brief Has control of the drive capability of the I2C pins. */ +#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) +/* @brief Has double buffering support (register S2). */ +#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) +/* @brief Has double buffer enable. */ +#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0) + +/* SAI module features */ + +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +#define FSL_FEATURE_SAI_FIFO_COUNT (1) +/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ +#define FSL_FEATURE_SAI_CHANNEL_COUNT (1) +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ +#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (2) +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0) +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0) +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0) +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ +#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) +/* @brief Ihe interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) +/* @brief Has register of MCR. */ +#define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has register of MDR */ +#define FSL_FEATURE_SAI_HAS_MDR (1) + +/* LLWU module features */ + +/* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) +/* @brief Has pins 8-15 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) +/* @brief Maximum number of internal modules connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) +/* @brief Number of digital filters. */ +#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) +/* @brief Has MF register. */ +#define FSL_FEATURE_LLWU_HAS_MF (0) +/* @brief Has PF register. */ +#define FSL_FEATURE_LLWU_HAS_PF (0) +/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ +#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) +/* @brief Has external pin 0 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0) +/* @brief Has external pin 1 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0) +/* @brief Has external pin 2 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0) +/* @brief Has external pin 3 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (0) +/* @brief Has external pin 4 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0) +/* @brief Has external pin 5 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) +/* @brief Has external pin 6 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) +/* @brief Has external pin 7 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) +/* @brief Has external pin 8 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) +/* @brief Has external pin 9 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) +/* @brief Has external pin 10 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) +/* @brief Has external pin 11 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0) +/* @brief Has external pin 12 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) +/* @brief Has external pin 13 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (0) +/* @brief Has external pin 14 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) +/* @brief Has external pin 15 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) +/* @brief Has external pin 16 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) +/* @brief Has external pin 17 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) +/* @brief Has external pin 18 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) +/* @brief Has external pin 19 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) +/* @brief Has external pin 20 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) +/* @brief Has external pin 21 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) +/* @brief Has external pin 22 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) +/* @brief Has external pin 23 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) +/* @brief Has external pin 24 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) +/* @brief Has external pin 25 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) +/* @brief Has external pin 26 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) +/* @brief Has external pin 27 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) +/* @brief Has external pin 28 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) +/* @brief Has external pin 29 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) +/* @brief Has external pin 30 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) +/* @brief Has external pin 31 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) +/* @brief Has internal module 0 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) +/* @brief Has internal module 1 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) +/* @brief Has internal module 2 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (0) +/* @brief Has internal module 3 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) +/* @brief Has internal module 4 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) +/* @brief Has internal module 5 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) +/* @brief Has internal module 6 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) +/* @brief Has internal module 7 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) +/* @brief Has Version ID Register (LLWU_VERID). */ +#define FSL_FEATURE_LLWU_HAS_VERID (0) +/* @brief Has Parameter Register (LLWU_PARAM). */ +#define FSL_FEATURE_LLWU_HAS_PARAM (0) +/* @brief Width of registers of the LLWU. */ +#define FSL_FEATURE_LLWU_REG_BITWIDTH (8) +/* @brief Has DMA Enable register (LLWU_DE). */ +#define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) + +/* MCG module features */ + +/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ +#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1) +/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ +#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24) +/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ +#define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) +/* @brief PLL reference clock low range. OSCCLK/PLL_R. */ +#define FSL_FEATURE_MCG_PLL_REF_MIN (2000000) +/* @brief PLL reference clock high range. OSCCLK/PLL_R. */ +#define FSL_FEATURE_MCG_PLL_REF_MAX (4000000) +/* @brief The PLL clock is divided by 2 before VCO divider. */ +#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) +/* @brief FRDIV supports 1280. */ +#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) +/* @brief FRDIV supports 1536. */ +#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) +/* @brief MCGFFCLK divider. */ +#define FSL_FEATURE_MCG_FFCLK_DIV (1) +/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ +#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) +/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ +#define FSL_FEATURE_MCG_HAS_RTC_32K (0) +/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ +#define FSL_FEATURE_MCG_HAS_PLL1 (0) +/* @brief Has 48MHz internal oscillator. */ +#define FSL_FEATURE_MCG_HAS_IRC_48M (0) +/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ +#define FSL_FEATURE_MCG_HAS_OSC1 (0) +/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ +#define FSL_FEATURE_MCG_HAS_FCFTRIM (1) +/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ +#define FSL_FEATURE_MCG_HAS_LOLRE (1) +/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ +#define FSL_FEATURE_MCG_USE_OSCSEL (1) +/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ +#define FSL_FEATURE_MCG_USE_PLLREFSEL (0) +/* @brief TBD */ +#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) +/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ +#define FSL_FEATURE_MCG_HAS_PLL (1) +/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ +#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1) +/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ +#define FSL_FEATURE_MCG_HAS_PLL_VDIV (1) +/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ +#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) +/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ +#define FSL_FEATURE_MCG_HAS_FLL (1) +/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ +#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) +/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ +#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) +/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ +#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) +/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ +#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) +/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ +#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) +/* @brief Has external clock monitor (register bit C6[CME]). */ +#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) +/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ +#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) +/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ +#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) +/* @brief Has PEI mode or PBI mode. */ +#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) +/* @brief Reset clock mode is BLPI. */ +#define FSL_FEATURE_MCG_RESET_IS_BLPI (0) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) + +/* OSC module features */ + +/* @brief Has OSC1 external oscillator. */ +#define FSL_FEATURE_OSC_HAS_OSC1 (0) +/* @brief Has OSC0 external oscillator. */ +#define FSL_FEATURE_OSC_HAS_OSC0 (1) +/* @brief Has OSC external oscillator (without index). */ +#define FSL_FEATURE_OSC_HAS_OSC (0) +/* @brief Number of OSC external oscillators. */ +#define FSL_FEATURE_OSC_OSC_COUNT (1) +/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ +#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) + +/* PIT module features */ + +/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ +#define FSL_FEATURE_PIT_TIMER_COUNT (2) +/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ +#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) +/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ +#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) +/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ +#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) + +/* PMC module features */ + +/* @brief Has Bandgap Enable In VLPx Operation support. */ +#define FSL_FEATURE_PMC_HAS_BGEN (1) +/* @brief Has Bandgap Buffer Enable. */ +#define FSL_FEATURE_PMC_HAS_BGBE (1) +/* @brief Has Bandgap Buffer Drive Select. */ +#define FSL_FEATURE_PMC_HAS_BGBDS (0) +/* @brief Has Low-Voltage Detect Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVDV (1) +/* @brief Has Low-Voltage Warning Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVWV (1) +/* @brief Has LPO. */ +#define FSL_FEATURE_PMC_HAS_LPO (0) +/* @brief Has VLPx option PMC_REGSC[VLPO]. */ +#define FSL_FEATURE_PMC_HAS_VLPO (0) +/* @brief Has acknowledge isolation support. */ +#define FSL_FEATURE_PMC_HAS_ACKISO (1) +/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ +#define FSL_FEATURE_PMC_HAS_REGFPM (0) +/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ +#define FSL_FEATURE_PMC_HAS_REGONS (1) +/* @brief Has PMC_HVDSC1. */ +#define FSL_FEATURE_PMC_HAS_HVDSC1 (0) +/* @brief Has PMC_PARAM. */ +#define FSL_FEATURE_PMC_HAS_PARAM (0) +/* @brief Has PMC_VERID. */ +#define FSL_FEATURE_PMC_HAS_VERID (0) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Has separate drive strength register (HDRVE). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) +/* @brief Has glitch filter (register IOFLT). */ +#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* RCM module features */ + +/* @brief Has Loss-of-Lock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOL (1) +/* @brief Has Loss-of-Clock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOC (1) +/* @brief Has JTAG generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_JTAG (0) +/* @brief Has EzPort generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_EZPORT (0) +/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ +#define FSL_FEATURE_RCM_HAS_EZPMS (0) +/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ +#define FSL_FEATURE_RCM_HAS_BOOTROM (0) +/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ +#define FSL_FEATURE_RCM_HAS_SSRS (0) +/* @brief Has Version ID Register (RCM_VERID). */ +#define FSL_FEATURE_RCM_HAS_VERID (0) +/* @brief Has Parameter Register (RCM_PARAM). */ +#define FSL_FEATURE_RCM_HAS_PARAM (0) +/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ +#define FSL_FEATURE_RCM_HAS_SRIE (0) +/* @brief Width of registers of the RCM. */ +#define FSL_FEATURE_RCM_REG_WIDTH (8) +/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ +#define FSL_FEATURE_RCM_HAS_CORE1 (0) +/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ +#define FSL_FEATURE_RCM_HAS_MDM_AP (1) +/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ +#define FSL_FEATURE_RCM_HAS_WAKEUP (1) + +/* RTC module features */ + +#if defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z128VLH4) || \ + defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VFM4) || \ + defined(CPU_MKL26Z64VFT4) || defined(CPU_MKL26Z64VLH4) + /* @brief Has wakeup pin. */ + #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) + /* @brief Has wakeup pin selection (bit field CR[WPS]). */ + #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) + /* @brief Has low power features (registers MER, MCLR and MCHR). */ + #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) + /* @brief Has read/write access control (registers WAR and RAR). */ + #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) + /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ + #define FSL_FEATURE_RTC_HAS_SECURITY (0) + /* @brief Has RTC_CLKIN available. */ + #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (1) + /* @brief Has prescaler adjust for LPO. */ + #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) + /* @brief Has Clock Pin Enable field. */ + #define FSL_FEATURE_RTC_HAS_CPE (0) + /* @brief Has Timer Seconds Interrupt Configuration field. */ + #define FSL_FEATURE_RTC_HAS_TSIC (0) + /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ + #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) +#elif defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z256VLL4) || \ + defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL26Z256VMP4) + /* @brief Has wakeup pin. */ + #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) + /* @brief Has wakeup pin selection (bit field CR[WPS]). */ + #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) + /* @brief Has low power features (registers MER, MCLR and MCHR). */ + #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) + /* @brief Has read/write access control (registers WAR and RAR). */ + #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) + /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ + #define FSL_FEATURE_RTC_HAS_SECURITY (0) + /* @brief Has RTC_CLKIN available. */ + #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (1) + /* @brief Has prescaler adjust for LPO. */ + #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) + /* @brief Has Clock Pin Enable field. */ + #define FSL_FEATURE_RTC_HAS_CPE (0) + /* @brief Has Timer Seconds Interrupt Configuration field. */ + #define FSL_FEATURE_RTC_HAS_TSIC (0) + /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ + #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) +#endif /* defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z128VLH4) || \ + defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VFM4) || \ + defined(CPU_MKL26Z64VFT4) || defined(CPU_MKL26Z64VLH4) */ + +/* SIM module features */ + +/* @brief Has USB FS divider. */ +#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) +/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ +#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (1) +/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) +/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ +#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) +/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) +/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ +#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) +/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) +/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) +/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) +/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) +/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) +/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PCR (0) +/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_MCC (0) +/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ +#define FSL_FEATURE_SIM_OPT_HAS_ODE (1) +/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ +#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0) +/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ +#define FSL_FEATURE_SIM_OPT_UART_COUNT (3) +/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (1) +/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (1) +/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (1) +/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) +/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) +/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ +#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) +/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) +/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) +/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) +/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) +/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) +/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) +/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) +/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (1) +/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) +/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) +/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (1) +/* @brief Has FTM module(s) configuration. */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM (0) +/* @brief Number of FTM modules. */ +#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) +/* @brief Number of FTM triggers with selectable source. */ +#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) +/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) +/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) +/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) +/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) +/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) +/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) +/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) +/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) +/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) +/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) +/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) +/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) +/* @brief Has TPM module(s) configuration. */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM (1) +/* @brief The highest TPM module index. */ +#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) +/* @brief Has TPM module with index 0. */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) +/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1) +/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1) +/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) +/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1) +/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (2) +/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) +/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) +/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) +/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ +#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) +/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) +/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) +/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) +/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) +/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) +/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) +/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) +/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) +/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) +/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) +/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) +/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) +/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) +/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (1) +/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) +/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) +/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) +/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) +/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) +/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) +/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) +/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) +/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) +/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) +/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) +/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) +/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) +/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) +/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) +/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) +/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ +#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) +/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) +/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) +/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) +/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) +/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) +/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) +/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) +/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) +/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) +/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) +/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) +/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) +/* @brief Has device die ID (register bit field SDID[DIEID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) +/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) +/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) +/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) +/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) +/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) +/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) +/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) +/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) +/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) +/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) +/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) +/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) +/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) +/* @brief Has miscellanious control register (register MCR). */ +#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) +/* @brief Has COP watchdog (registers COPC and SRVCOP). */ +#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) +/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ +#define FSL_FEATURE_SIM_HAS_COP_STOP (0) +/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ +#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) + +/* SMC module features */ + +/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ +#define FSL_FEATURE_SMC_HAS_PSTOPO (1) +/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ +#define FSL_FEATURE_SMC_HAS_LPOPO (0) +/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ +#define FSL_FEATURE_SMC_HAS_PORPO (1) +/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ +#define FSL_FEATURE_SMC_HAS_LPWUI (0) +/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ +#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) +/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) +/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1) +/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ +#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) +/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ +#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) +/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ +#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ +#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has stop submode. */ +#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) +/* @brief Has stop submode 0(VLLS0). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) +/* @brief Has stop submode 2(VLLS2). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (0) +/* @brief Has SMC_PARAM. */ +#define FSL_FEATURE_SMC_HAS_PARAM (0) +/* @brief Has SMC_VERID. */ +#define FSL_FEATURE_SMC_HAS_VERID (0) + +/* SPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_SPI_HAS_FIFO (1) +/* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). */ +#define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_SPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) +/* @brief Receive/transmit FIFO size in number of 16-bit communication items. */ +#define FSL_FEATURE_SPI_FIFO_SIZEn(x) \ + ((x) == SPI0 ? (0) : \ + ((x) == SPI1 ? (4) : (-1))) +/* @brief Maximum transfer data width in bits. */ +#define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16) +/* @brief The data register name has postfix (L as low and H as high). */ +#define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1) +/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ +#define FSL_FEATURE_SPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) +/* @brief Has 16-bit data transfer support. */ +#define FSL_FEATURE_SPI_16BIT_TRANSFERS (1) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) + +/* TPM module features */ + +/* @brief Bus clock is the source clock for the module. */ +#define FSL_FEATURE_TPM_BUS_CLOCK (0) +/* @brief Number of channels. */ +#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ + ((x) == TPM0 ? (6) : \ + ((x) == TPM1 ? (2) : \ + ((x) == TPM2 ? (2) : (-1)))) +/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ +#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) +/* @brief Has TPM_PARAM. */ +#define FSL_FEATURE_TPM_HAS_PARAM (0) +/* @brief Has TPM_VERID. */ +#define FSL_FEATURE_TPM_HAS_VERID (0) +/* @brief Has TPM_GLOBAL. */ +#define FSL_FEATURE_TPM_HAS_GLOBAL (0) +/* @brief Has TPM_TRIG. */ +#define FSL_FEATURE_TPM_HAS_TRIG (0) +/* @brief Has counter pause on trigger. */ +#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (0) +/* @brief Has external trigger selection. */ +#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (0) +/* @brief Has TPM_COMBINE. */ +#define FSL_FEATURE_TPM_HAS_COMBINE (0) +/* @brief Has TPM_POL. */ +#define FSL_FEATURE_TPM_HAS_POL (0) +/* @brief Has TPM_FILTER. */ +#define FSL_FEATURE_TPM_HAS_FILTER (0) +/* @brief Has TPM_QDCTRL. */ +#define FSL_FEATURE_TPM_HAS_QDCTRL (0) + +/* TSI module features */ + +/* @brief TSI module version. */ +#define FSL_FEATURE_TSI_VERSION (4) +/* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */ +#define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0) +/* @brief Number of TSI channels. */ +#define FSL_FEATURE_TSI_CHANNEL_COUNT (16) + +/* LPSCI module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPSCI_HAS_IRQ_EXTENDED_FUNCTIONS (1) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPSCI_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPSCI_HAS_EXTENDED_DATA_REGISTER_FLAGS (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPSCI_HAS_FIFO (0) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPSCI_HAS_MODEM_SUPPORT (0) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPSCI_HAS_IR_SUPPORT (0) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPSCI_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPSCI_HAS_10BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPSCI_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPSCI_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPSCI_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPSCI_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPSCI_IS_SCI (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPSCI_FIFO_SIZE (0) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_LPSCI_MAX_DATA_WIDTH_WITH_NO_PARITY (10) +/* @brief Maximal data width with parity bit. */ +#define FSL_FEATURE_LPSCI_MAX_DATA_WIDTH_WITH_PARITY (9) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPSCI_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPSCI_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPSCI_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPSCI_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPSCI_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPSCI_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPSCI_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPSCI_HAS_32BIT_REGISTERS (0) +/* @brief Lin break detect available (has bit BDH[LBKDIE]). */ +#define FSL_FEATURE_LPSCI_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPSCI_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSCI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) + +/* UART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_UART_HAS_FIFO (0) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (0) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_UART_HAS_IR_SUPPORT (0) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_UART_IS_SCI (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_UART_FIFO_SIZE (0) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) +/* @brief Maximal data width with parity bit. */ +#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (8) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (0) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_UART_HAS_DMA_SELECT (1) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (0) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) +/* @brief Lin break detect available (has bit BDH[LBKDIE]). */ +#define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) + +/* USB module features */ + +/* @brief HOST mode enabled */ +#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) +/* @brief OTG mode enabled */ +#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM (0) +/* @brief Has KEEP_ALIVE_CTRL register */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) +/* @brief Has the Dynamic SOF threshold compare support */ +#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0) +/* @brief Has the VBUS detect support */ +#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) +/* @brief Has the IRC48M module clock support */ +#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (0) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USB_ENDPT_COUNT (16) + +#endif /* _MKL26Z4_FEATURES_H_ */ +
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/kl26z/MKL26Z4/fsl_device_registers.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/freescale/kl26z/MKL26Z4/fsl_device_registers.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z64VFM4) || \ + defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z64VFT4) || \ + defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VLH4) || \ + defined(CPU_MKL26Z128VLH4) || defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z128VLL4) || \ + defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \ + defined(CPU_MKL26Z256VMP4)) + +#define KL26Z4_SERIES + +/* CMSIS-style register definitions */ +#include "MKL26Z4.h" +/* CPU specific feature definitions */ +#include "MKL26Z4_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/kl26z/MKL26Z4/system_MKL26Z4.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/kl26z/MKL26Z4/system_MKL26Z4.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,250 @@
+/*
+** ###################################################################
+** Processor: MKL26Z128VLK4
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL26RM, Rev.1, Jun 2012
+** Version: rev. 1.1, 2012-06-21
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2012-06-13)
+** Initial version.
+** - rev. 1.1 (2012-06-21)
+** Update according to reference manual rev. 1.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MKL25Z4
+ * @version 1.1
+ * @date 2012-06-21
+ * @brief Device specific configuration file for MKL25Z4 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include "stdint.h"
+#include "MKL26Z4.h"
+
+#define DISABLE_WDOG 1
+
+#define CLOCK_SETUP 1
+/* Predefined clock setups
+ 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
+ Reference clock source for MCG module is the slow internal clock source 32.768kHz
+ Core clock = 41.94MHz, BusClock = 13.98MHz
+ 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
+ Reference clock source for MCG module is an external crystal 8MHz
+ Core clock = 48MHz, BusClock = 24MHz
+ 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
+ Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
+ Core clock = 8MHz, BusClock = 8MHz
+*/
+
+/*----------------------------------------------------------------------------
+ Define clock source values
+ *----------------------------------------------------------------------------*/
+#if (CLOCK_SETUP == 0)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
+#elif (CLOCK_SETUP == 1)
+ #define CPU_XTAL_CLK_HZ 16000000u/* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
+#elif (CLOCK_SETUP == 2)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
+#endif /* (CLOCK_SETUP == 2) */
+
+
+/* ----------------------------------------------------------------------------
+ -- Core clock
+ ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+ -- SystemInit()
+ ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if (DISABLE_WDOG)
+ /* Disable the WDOG module */
+ /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
+ SIM->COPC = (uint32_t)0x00u;
+#endif /* (DISABLE_WDOG) */
+#if (CLOCK_SETUP == 0)
+ SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
+ /* Switch to FEI Mode */
+ /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x06U;
+ MCG->C2 = (uint8_t)0x00U;
+ /* MCG->C4: DMX32=0,DRST_DRS=1 */
+ MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
+ OSC0->CR = (uint8_t)0x80U;
+ MCG->C5 = (uint8_t)0x00U;
+ /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00U;
+ while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
+ }
+ while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
+ }
+#elif (CLOCK_SETUP == 1)
+ /* SIM->SCGC5: PORTA=1 */
+ SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
+ SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
+ /* PORTA->PCR18: ISF=0,MUX=0 */
+ PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
+ /* PORTA->PCR19: ISF=0,MUX=0 */
+ PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
+ /* Switch to FBE Mode */
+ OSC0->CR = (uint8_t)0x80U; // was 0x89U for 8Mhz
+ MCG->C2 = (uint8_t)0x24U;
+ /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0xA2U; //was 0x9AU; for 8Mhz
+ /* MCG->C4: DMX32=0,DRST_DRS=0 */
+ MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
+ MCG->C5 = (uint8_t)0x03U; //was 0x01U; for 8Mhz
+ /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00U;
+ while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
+ }
+ while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+ }
+ /* Switch to PBE Mode */
+ /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x40U;
+ while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+ }
+ while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
+ }
+ /* Switch to PEE Mode */
+ /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x1AU;
+ while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
+ }
+#elif (CLOCK_SETUP == 2)
+ /* SIM->SCGC5: PORTA=1 */
+ SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
+ SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */
+ /* PORTA->PCR18: ISF=0,MUX=0 */
+ PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
+ /* PORTA->PCR19: ISF=0,MUX=0 */
+ PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
+ /* Switch to FBE Mode */
+ OSC0->CR = (uint8_t)0x89U;
+ MCG->C2 = (uint8_t)0x24U;
+ /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x9AU;
+ /* MCG->C4: DMX32=0,DRST_DRS=0 */
+ MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
+ MCG->C5 = (uint8_t)0x00U;
+ /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00U;
+ while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
+ }
+ while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+ }
+ /* Switch to BLPE Mode */
+ MCG->C2 = (uint8_t)0x26U;
+ while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+ }
+#endif /* (CLOCK_SETUP == 2) */
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemCoreClockUpdate()
+ ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+ uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+ uint8_t Divider;
+
+ if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
+ /* Output of FLL or PLL is selected */
+ if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
+ /* FLL is selected */
+ if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
+ /* External reference clock is selected */
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+ MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+ if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
+ MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
+ } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
+ } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+ } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+ /* Select correct multiplier to calculate the MCG output clock */
+ switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+ case 0x0u:
+ MCGOUTClock *= 640u;
+ break;
+ case 0x20u:
+ MCGOUTClock *= 1280u;
+ break;
+ case 0x40u:
+ MCGOUTClock *= 1920u;
+ break;
+ case 0x60u:
+ MCGOUTClock *= 2560u;
+ break;
+ case 0x80u:
+ MCGOUTClock *= 732u;
+ break;
+ case 0xA0u:
+ MCGOUTClock *= 1464u;
+ break;
+ case 0xC0u:
+ MCGOUTClock *= 2197u;
+ break;
+ case 0xE0u:
+ MCGOUTClock *= 2929u;
+ break;
+ default:
+ break;
+ }
+ } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+ /* PLL is selected */
+ Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
+ MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+ Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
+ MCGOUTClock *= Divider; /* Calculate the MCG output clock */
+ } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
+ /* Internal reference clock is selected */
+ if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+ } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
+ } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
+ /* External reference clock is selected */
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+ /* Reserved value */
+ return;
+ } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+ SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/kl26z/MKL26Z4/system_MKL26Z4.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/kl26z/MKL26Z4/system_MKL26Z4.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,84 @@
+/*
+** ###################################################################
+** Processor: MKL25Z128VLK4
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL25RM, Rev.1, Jun 2012
+** Version: rev. 1.1, 2012-06-21
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2012-06-13)
+** Initial version.
+** - rev. 1.1 (2012-06-21)
+** Update according to reference manual rev. 1.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MKL25Z4
+ * @version 1.1
+ * @date 2012-06-21
+ * @brief Device specific configuration file for MKL25Z4 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MKL25Z4_H_
+#define SYSTEM_MKL25Z4_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if !defined(SYSTEM_MKL25Z4_H_) */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/kl26z/armcc/startup_MKL26Z4.s --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/freescale/kl26z/armcc/startup_MKL26Z4.s Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,379 @@ +;/** +; * @file startup_MKL26Z.s +; * @brief +; * +; * DAPLink Interface Firmware +; * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000100 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000100 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT g_board_info +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DAPLINK_BUILD_KEY ; Build type - BL/IF + DCD DAPLINK_HIC_ID ; Compatibility + DCD DAPLINK_VERSION ; Version + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD g_board_info ; Ptr to Board info, family info other target details + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt + DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt + DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt + DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt + DCD Reserved20_IRQHandler ; Reserved interrupt 20 + DCD FTFA_IRQHandler ; FTFA interrupt + DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning + DCD LLW_IRQHandler ; Low Leakage Wakeup + DCD I2C0_IRQHandler ; I2C0 interrupt + DCD I2C1_IRQHandler ; I2C0 interrupt 25 + DCD SPI0_IRQHandler ; SPI0 interrupt + DCD SPI1_IRQHandler ; SPI1 interrupt + DCD UART0_IRQHandler ; UART0 status/error interrupt + DCD UART1_IRQHandler ; UART1 status/error interrupt + DCD UART2_IRQHandler ; UART2 status/error interrupt + DCD ADC0_IRQHandler ; ADC0 interrupt + DCD CMP0_IRQHandler ; CMP0 interrupt + DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt + DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt + DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt + DCD RTC_IRQHandler ; RTC interrupt + DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt + DCD PIT_IRQHandler ; PIT timer interrupt + DCD Reserved39_IRQHandler ; Reserved interrupt 39 + DCD USB0_IRQHandler ; USB0 interrupt + DCD DAC0_IRQHandler ; DAC interrupt + DCD TSI0_IRQHandler ; TSI0 interrupt + DCD MCG_IRQHandler ; MCG interrupt + DCD LPTimer_IRQHandler ; LPTimer interrupt + DCD Reserved45_IRQHandler ; Reserved interrupt 45 + DCD PORTA_IRQHandler ; Port A interrupt + DCD PORTD_IRQHandler ; Port D interrupt +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +; <h> Flash Configuration +; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset) +; <i> and security information that allows the MCU to restrict acces to the FTFL module. +; <h> Backdoor Comparison Key +; <o0> Backdoor Key 0 <0x0-0xFF:2> +; <o1> Backdoor Key 1 <0x0-0xFF:2> +; <o2> Backdoor Key 2 <0x0-0xFF:2> +; <o3> Backdoor Key 3 <0x0-0xFF:2> +; <o4> Backdoor Key 4 <0x0-0xFF:2> +; <o5> Backdoor Key 5 <0x0-0xFF:2> +; <o6> Backdoor Key 6 <0x0-0xFF:2> +; <o7> Backdoor Key 7 <0x0-0xFF:2> +BackDoorK0 EQU 0xFF +BackDoorK1 EQU 0xFF +BackDoorK2 EQU 0xFF +BackDoorK3 EQU 0xFF +BackDoorK4 EQU 0xFF +BackDoorK5 EQU 0xFF +BackDoorK6 EQU 0xFF +BackDoorK7 EQU 0xFF +; </h> +; <h> Program flash protection bytes (FPROT) +; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit. +; <i> Each bit protects a 1/32 region of the program flash memory. +; <h> FPROT0 +; <i> Program flash protection bytes +; <i> 1/32 - 8/32 region +; <o.0> FPROT0.0 +; <o.1> FPROT0.1 +; <o.2> FPROT0.2 +; <o.3> FPROT0.3 +; <o.4> FPROT0.4 +; <o.5> FPROT0.5 +; <o.6> FPROT0.6 +; <o.7> FPROT0.7 +nFPROT0 EQU 0x00 +FPROT0 EQU nFPROT0:EOR:0xFF +; </h> +; <h> FPROT1 +; <i> Program Flash Region Protect Register 1 +; <i> 9/32 - 16/32 region +; <o.0> FPROT1.0 +; <o.1> FPROT1.1 +; <o.2> FPROT1.2 +; <o.3> FPROT1.3 +; <o.4> FPROT1.4 +; <o.5> FPROT1.5 +; <o.6> FPROT1.6 +; <o.7> FPROT1.7 +nFPROT1 EQU 0x00 +FPROT1 EQU nFPROT1:EOR:0xFF +; </h> +; <h> FPROT2 +; <i> Program Flash Region Protect Register 2 +; <i> 17/32 - 24/32 region +; <o.0> FPROT2.0 +; <o.1> FPROT2.1 +; <o.2> FPROT2.2 +; <o.3> FPROT2.3 +; <o.4> FPROT2.4 +; <o.5> FPROT2.5 +; <o.6> FPROT2.6 +; <o.7> FPROT2.7 +nFPROT2 EQU 0x00 +FPROT2 EQU nFPROT2:EOR:0xFF +; </h> +; <h> FPROT3 +; <i> Program Flash Region Protect Register 3 +; <i> 25/32 - 32/32 region +; <o.0> FPROT3.0 +; <o.1> FPROT3.1 +; <o.2> FPROT3.2 +; <o.3> FPROT3.3 +; <o.4> FPROT3.4 +; <o.5> FPROT3.5 +; <o.6> FPROT3.6 +; <o.7> FPROT3.7 +nFPROT3 EQU 0x00 +FPROT3 EQU nFPROT3:EOR:0xFF +; </h> +; </h> +; </h> +; <h> Flash nonvolatile option byte (FOPT) +; <i> Allows the user to customize the operation of the MCU at boot time. +; <o.0> LPBOOT0 +; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4) +; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1) +; <o.4> LPBOOT1 +; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2) +; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1) +; <o.2> NMI_DIS +; <0=> NMI interrupts are always blocked +; <1=> NMI pin/interrupts reset default to enabled +; <o.3> RESET_PIN_CFG +; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function +; <1=> RESET pin is dedicated +; <o.3> FAST_INIT +; <0=> Slower initialization +; <1=> Fast Initialization +FOPT EQU 0xFF +; </h> +; <h> Flash security byte (FSEC) +; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", +; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! +; <o.0..1> SEC +; <2=> MCU security status is unsecure +; <3=> MCU security status is secure +; <i> Flash Security +; <i> This bits define the security state of the MCU. +; <o.2..3> FSLACC +; <2=> Freescale factory access denied +; <3=> Freescale factory access granted +; <i> Freescale Failure Analysis Access Code +; <i> This bits define the security state of the MCU. +; <o.4..5> MEEN +; <2=> Mass erase is disabled +; <3=> Mass erase is enabled +; <i> Mass Erase Enable Bits +; <i> Enables and disables mass erase capability of the FTFL module +; <o.6..7> KEYEN +; <2=> Backdoor key access enabled +; <3=> Backdoor key access disabled +; <i> Backdoor key Security Enable +; <i> These bits enable and disable backdoor key access to the FTFL module. +FSEC EQU 0xFE +; </h> + + #if defined(DAPLINK_IF) + AREA |.ARM.__at_0x8400|, CODE, READONLY + #else + AREA |.ARM.__at_0x400 |, CODE, READONLY + #endif + + DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 + DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 + DCB FPROT0, FPROT1, FPROT2, FPROT3 + DCB FSEC, FOPT, 0xFF, 0xFF + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DMA0_IRQHandler [WEAK] + EXPORT DMA1_IRQHandler [WEAK] + EXPORT DMA2_IRQHandler [WEAK] + EXPORT DMA3_IRQHandler [WEAK] + EXPORT Reserved20_IRQHandler [WEAK] + EXPORT FTFA_IRQHandler [WEAK] + EXPORT LVD_LVW_IRQHandler [WEAK] + EXPORT LLW_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT TPM0_IRQHandler [WEAK] + EXPORT TPM1_IRQHandler [WEAK] + EXPORT TPM2_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT RTC_Seconds_IRQHandler [WEAK] + EXPORT PIT_IRQHandler [WEAK] + EXPORT Reserved39_IRQHandler [WEAK] + EXPORT USB0_IRQHandler [WEAK] + EXPORT DAC0_IRQHandler [WEAK] + EXPORT TSI0_IRQHandler [WEAK] + EXPORT MCG_IRQHandler [WEAK] + EXPORT LPTimer_IRQHandler [WEAK] + EXPORT Reserved45_IRQHandler [WEAK] + EXPORT PORTA_IRQHandler [WEAK] + EXPORT PORTD_IRQHandler [WEAK] + EXPORT DefaultISR [WEAK] + +DMA0_IRQHandler +DMA1_IRQHandler +DMA2_IRQHandler +DMA3_IRQHandler +Reserved20_IRQHandler +FTFA_IRQHandler +LVD_LVW_IRQHandler +LLW_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +TPM0_IRQHandler +TPM1_IRQHandler +TPM2_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT_IRQHandler +Reserved39_IRQHandler +USB0_IRQHandler +DAC0_IRQHandler +TSI0_IRQHandler +MCG_IRQHandler +LPTimer_IRQHandler +Reserved45_IRQHandler +PORTA_IRQHandler +PORTD_IRQHandler +DefaultISR + + B . + ENDP + ALIGN +; User Initial Stack & Heap + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ALIGN + + ENDIF + + END
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/kl26z/daplink_addr.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/freescale/kl26z/daplink_addr.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,83 @@ +/** + * @file daplink_addr.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef DAPLINK_ADDR_H +#define DAPLINK_ADDR_H + +/* Device sizes */ + +#define DAPLINK_ROM_START 0x00000000 +#define DAPLINK_ROM_SIZE 0x00020000 + +#define DAPLINK_RAM_START 0x1FFFF000 +#define DAPLINK_RAM_SIZE 0x00004000 + +/* ROM sizes */ + +#define DAPLINK_ROM_BL_START 0x00000000 +#define DAPLINK_ROM_BL_SIZE 0x00008000 + +#define DAPLINK_ROM_CONFIG_ADMIN_START 0x00008000 +#define DAPLINK_ROM_CONFIG_ADMIN_SIZE 0x00000000 + +#define DAPLINK_ROM_IF_START 0x00008000 +#define DAPLINK_ROM_IF_SIZE 0x00017C00 + +#define DAPLINK_ROM_CONFIG_USER_START 0x0001FC00 +#define DAPLINK_ROM_CONFIG_USER_SIZE 0x00000400 + +/* RAM sizes */ + +#define DAPLINK_RAM_APP_START 0x1FFFF000 +#define DAPLINK_RAM_APP_SIZE 0x00003F00 + +#define DAPLINK_RAM_SHARED_START 0x20002F00 +#define DAPLINK_RAM_SHARED_SIZE 0x00000100 + +/* Flash Programming Info */ + +#define DAPLINK_SECTOR_SIZE 0x00000400 +#define DAPLINK_MIN_WRITE_SIZE 0x00000100 + +/* Current build */ + +#if defined(DAPLINK_BL) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_BL_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_IF_SIZE + +#elif defined(DAPLINK_IF) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_IF_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_BL_SIZE + +#else + +#error "Build must be either bootloader or interface" + +#endif + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/kl26z/gpio.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/kl26z/gpio.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,93 @@
+/**
+ * @file gpio.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "gpio.h"
+
+static void busy_wait(uint32_t cycles)
+{
+ volatile uint32_t i;
+ i = cycles;
+
+ while (i > 0) {
+ i--;
+ }
+}
+
+void gpio_init(void)
+{
+ SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK;
+ // configure pin as GPIO
+ PIN_HID_LED_PORT->PCR[PIN_HID_LED_BIT] = PORT_PCR_MUX(1);
+ PIN_MSC_LED_PORT->PCR[PIN_MSC_LED_BIT] = PORT_PCR_MUX(1);
+ PIN_CDC_LED_PORT->PCR[PIN_CDC_LED_BIT] = PORT_PCR_MUX(1);
+ PIN_SW_RESET_PORT->PCR[PIN_SW_RESET_BIT] = PORT_PCR_MUX(1);
+ PIN_POWER_EN_PORT->PCR[PIN_POWER_EN_BIT] = PORT_PCR_MUX(1);
+ // led off
+ gpio_set_hid_led(GPIO_LED_OFF);
+ gpio_set_cdc_led(GPIO_LED_OFF);
+ gpio_set_msc_led(GPIO_LED_OFF);
+ // power regulator on
+ PIN_POWER_EN_GPIO->PDOR |= PIN_POWER_EN;
+ // set as output
+ PIN_HID_LED_GPIO->PDDR |= PIN_HID_LED;
+ PIN_MSC_LED_GPIO->PDDR |= PIN_MSC_LED;
+ PIN_CDC_LED_GPIO->PDDR |= PIN_CDC_LED;
+ PIN_POWER_EN_GPIO->PDDR |= PIN_POWER_EN;
+ // set as input
+ PIN_SW_RESET_GPIO->PDDR &= ~PIN_SW_RESET;
+
+ // Let the voltage rails stabilize. This is especailly important
+ // during software resets, since the target's 3.3v rail can take
+ // 20-50ms to drain. During this time the target could be driving
+ // the reset pin low, causing the bootloader to think the reset
+ // button is pressed.
+ // Note: With optimization set to -O2 the value 1000000 delays for ~85ms
+ busy_wait(1000000);
+}
+
+void gpio_set_hid_led(gpio_led_state_t state)
+{
+ (GPIO_LED_ON == state) ? (PIN_HID_LED_GPIO->PCOR = PIN_HID_LED) : (PIN_HID_LED_GPIO->PSOR = PIN_HID_LED);
+}
+
+void gpio_set_cdc_led(gpio_led_state_t state)
+{
+ (GPIO_LED_ON == state) ? (PIN_CDC_LED_GPIO->PCOR = PIN_CDC_LED) : (PIN_CDC_LED_GPIO->PSOR = PIN_CDC_LED);
+}
+
+void gpio_set_msc_led(gpio_led_state_t state)
+{
+ (GPIO_LED_ON == state) ? (PIN_MSC_LED_GPIO->PCOR = PIN_MSC_LED) : (PIN_MSC_LED_GPIO->PSOR = PIN_MSC_LED);
+}
+
+uint8_t gpio_get_reset_btn_no_fwrd(void)
+{
+ return 0;
+}
+
+uint8_t gpio_get_reset_btn_fwrd(void)
+{
+ return (PIN_SW_RESET_GPIO->PDIR & PIN_SW_RESET) ? 0 : 1;
+}
+
+void gpio_set_board_power(bool powerEnabled)
+{
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/kl26z/read_uid.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/kl26z/read_uid.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,31 @@
+/**
+ * @file read_uid.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "DAP_config.h"
+#include "read_uid.h"
+
+void read_unique_id(uint32_t *id)
+{
+ id[0] = SIM->UIDL;
+ id[1] = SIM->UIDML;
+ id[2] = SIM->UIDMH;
+ id[3] = 0;
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/kl26z/uart.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/kl26z/uart.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,266 @@
+/**
+ * @file uart.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "string.h"
+
+#include "uart.h"
+#include "util.h"
+#include "cortex_m.h"
+#include "IO_Config.h"
+#include "circ_buf.h"
+#include "settings.h" // for config_get_overflow_detect
+
+#define RX_OVRF_MSG "<DAPLink:Overflow>\n"
+#define RX_OVRF_MSG_SIZE (sizeof(RX_OVRF_MSG) - 1)
+#define BUFFER_SIZE (512)
+
+circ_buf_t write_buffer;
+uint8_t write_buffer_data[BUFFER_SIZE];
+circ_buf_t read_buffer;
+uint8_t read_buffer_data[BUFFER_SIZE];
+
+void clear_buffers(void)
+{
+ util_assert(!(UART->C2 & UART_C2_TIE_MASK));
+ circ_buf_init(&write_buffer, write_buffer_data, sizeof(write_buffer_data));
+ circ_buf_init(&read_buffer, read_buffer_data, sizeof(read_buffer_data));
+}
+
+int32_t uart_initialize(void)
+{
+ NVIC_DisableIRQ(UART_RX_TX_IRQn);
+
+ // enable clk port
+ if (UART_PORT == PORTA) {
+ SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
+ }
+
+ if (UART_PORT == PORTC) {
+ SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
+ }
+
+ if (UART_PORT == PORTD) {
+ SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK;
+ }
+
+ if (UART_PORT == PORTE) {
+ SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK;
+ }
+
+ // enable clk uart
+ if (1 == UART_NUM) {
+ SIM->SCGC4 |= SIM_SCGC4_UART1_MASK;
+ }
+
+ if (2 == UART_NUM) {
+ SIM->SCGC4 |= SIM_SCGC4_UART2_MASK;
+ }
+
+ // transmitter and receiver disabled
+ UART->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);
+ // disable interrupt
+ UART->C2 &= ~(UART_C2_RIE_MASK | UART_C2_TIE_MASK);
+
+ clear_buffers();
+
+ // alternate setting
+ UART_PORT->PCR[PIN_UART_RX_BIT] = PORT_PCR_MUX(PIN_UART_RX_MUX_ALT) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
+ UART_PORT->PCR[PIN_UART_TX_BIT] = PORT_PCR_MUX(PIN_UART_TX_MUX_ALT);
+ // transmitter and receiver enabled
+ UART->C2 |= UART_C2_RE_MASK | UART_C2_TE_MASK;
+ // Enable receive interrupt
+ UART->C2 |= UART_C2_RIE_MASK;
+ NVIC_ClearPendingIRQ(UART_RX_TX_IRQn);
+ NVIC_EnableIRQ(UART_RX_TX_IRQn);
+ return 1;
+}
+
+int32_t uart_uninitialize(void)
+{
+ // transmitter and receiver disabled
+ UART->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);
+ // disable interrupt
+ UART->C2 &= ~(UART_C2_RIE_MASK | UART_C2_TIE_MASK);
+ clear_buffers();
+ return 1;
+}
+
+int32_t uart_reset(void)
+{
+ // disable interrupt
+ NVIC_DisableIRQ(UART_RX_TX_IRQn);
+ // disable TIE interrupt
+ UART->C2 &= ~(UART_C2_TIE_MASK);
+ clear_buffers();
+ // enable interrupt
+ NVIC_EnableIRQ(UART_RX_TX_IRQn);
+ return 1;
+}
+
+int32_t uart_set_configuration(UART_Configuration *config)
+{
+ uint8_t data_bits = 8;
+ uint8_t parity_enable = 0;
+ uint8_t parity_type = 0;
+ uint32_t dll;
+ // disable interrupt
+ NVIC_DisableIRQ(UART_RX_TX_IRQn);
+ UART->C2 &= ~(UART_C2_RIE_MASK | UART_C2_TIE_MASK);
+ // Disable receiver and transmitter while updating
+ UART->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);
+ clear_buffers();
+
+ // set data bits, stop bits, parity
+ if ((config->DataBits < 8) || (config->DataBits > 9)) {
+ data_bits = 8;
+ }
+
+ data_bits -= 8;
+
+ if (config->Parity == 1) {
+ parity_enable = 1;
+ parity_type = 1;
+ data_bits++;
+ } else if (config->Parity == 2) {
+ parity_enable = 1;
+ parity_type = 0;
+ data_bits++;
+ }
+
+ // does not support 10 bit data comm
+ if (data_bits == 2) {
+ data_bits = 0;
+ parity_enable = 0;
+ parity_type = 0;
+ }
+
+ // data bits, parity and parity mode
+ UART->C1 = data_bits << UART_C1_M_SHIFT |
+ parity_enable << UART_C1_PE_SHIFT |
+ parity_type << UART_C1_PT_SHIFT;
+ dll = SystemCoreClock / (16 * config->Baudrate);
+
+ if (1 == UART_NUM || 2 == UART_NUM) {
+ dll /= 2; //TODO <<= 1
+ }
+
+ // set baudrate
+ UART->BDH = (UART->BDH & ~(UART_BDH_SBR_MASK)) | ((dll >> 8) & UART_BDH_SBR_MASK);
+ UART->BDL = (UART->BDL & ~(UART_BDL_SBR_MASK)) | (dll & UART_BDL_SBR_MASK);
+ // Enable transmitter and receiver
+ UART->C2 |= UART_C2_RE_MASK | UART_C2_TE_MASK;
+ // Enable UART interrupt
+ NVIC_ClearPendingIRQ(UART_RX_TX_IRQn);
+ NVIC_EnableIRQ(UART_RX_TX_IRQn);
+ UART->C2 |= UART_C2_RIE_MASK;
+ return 1;
+}
+
+int32_t uart_get_configuration(UART_Configuration *config)
+{
+ return 1;
+}
+
+int32_t uart_write_free(void)
+{
+ return circ_buf_count_free(&write_buffer);
+}
+
+int32_t uart_write_data(uint8_t *data, uint16_t size)
+{
+ cortex_int_state_t state;
+ uint32_t cnt;
+
+ cnt = circ_buf_write(&write_buffer, data, size);
+
+ // Atomically enable TX
+ state = cortex_int_get_and_disable();
+ if (circ_buf_count_used(&write_buffer)) {
+ UART->C2 |= UART_C2_TIE_MASK;
+ }
+ cortex_int_restore(state);
+
+ return cnt;
+}
+
+int32_t uart_read_data(uint8_t *data, uint16_t size)
+{
+ return circ_buf_read(&read_buffer, data, size);
+}
+
+void uart_enable_flow_control(bool enabled)
+{
+ // Flow control not implemented for this platform
+}
+
+void UART_RX_TX_IRQHandler(void)
+{
+ uint32_t s1;
+ volatile uint8_t errorData;
+ // read interrupt status
+ s1 = UART->S1;
+ // mask off interrupts that are not enabled
+ if (!(UART->C2 & UART_C2_RIE_MASK)) {
+ s1 &= ~UART_S1_RDRF_MASK;
+ }
+ if (!(UART->C2 & UART_C2_TIE_MASK)) {
+ s1 &= ~UART_S1_TDRE_MASK;
+ }
+
+ // handle character to transmit
+ if (s1 & UART_S1_TDRE_MASK) {
+ // Assert that there is data in the buffer
+ util_assert(circ_buf_count_used(&write_buffer) > 0);
+ // Send out data
+ UART1->D = circ_buf_pop(&write_buffer);
+ // Turn off the transmitter if that was the last byte
+ if (circ_buf_count_used(&write_buffer) == 0) {
+ // disable TIE interrupt
+ UART->C2 &= ~(UART_C2_TIE_MASK);
+ }
+ }
+
+ // handle received character
+ if (s1 & UART_S1_RDRF_MASK) {
+ if ((s1 & UART_S1_NF_MASK) || (s1 & UART_S1_FE_MASK)) {
+ errorData = UART->D;
+ } else {
+ uint32_t free;
+ uint8_t data;
+
+ data = UART1->D;
+ free = circ_buf_count_free(&read_buffer);
+ if (free > RX_OVRF_MSG_SIZE) {
+ circ_buf_push(&read_buffer, data);
+ } else if (config_get_overflow_detect()) {
+ if (RX_OVRF_MSG_SIZE == free) {
+ circ_buf_write(&read_buffer, (uint8_t*)RX_OVRF_MSG, RX_OVRF_MSG_SIZE);
+ } else {
+ // Drop newest
+ }
+ } else {
+ // Drop oldest
+ circ_buf_pop(&read_buffer);
+ circ_buf_push(&read_buffer, data);
+ }
+ }
+ }
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/kl26z/usb_config.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/freescale/kl26z/usb_config.c Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,556 @@ +/** + * @file usb_config.c + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "util.h" + +// <e> USB Device +// <i> Enable the USB Device functionality +#define USBD_ENABLE 1 +#define USBD_RTX_CORE_STACK 0 +#define USBD_RTX_DEVICE_STACK 0 +#define USBD_RTX_ENDPOINT0_STACK 0 + +// <o0.0> High-speed +// <i> Enable high-speed functionality (if device supports it) +#define USBD_HS_ENABLE 0 +#if (defined(WEBUSB_INTERFACE) || defined(WINUSB_INTERFACE) || defined(WINUSB_INTERFACE)) +#define USBD_BOS_ENABLE 1 +#else +#define USBD_BOS_ENABLE 0 +#endif +// <h> Device Settings +// <i> These settings affect Device Descriptor +// <o0> Power +// <i> Default Power Setting +// <0=> Bus-powered +// <1=> Self-powered +// <o1> Max Endpoint 0 Packet Size +// <i> Maximum packet size for endpoint zero (bMaxPacketSize0) +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes +// <o2.0..15> Vendor ID <0x0000-0xFFFF> +// <i> Vendor ID assigned by the USB-IF (idVendor) +// <o3.0..15> Product ID <0x0000-0xFFFF> +// <i> Product ID assigned by the manufacturer (idProduct) +// <o4.0..15> Device Release Number <0x0000-0xFFFF> +// <i> Device release number in binary-coded decimal (bcdDevice) +// </h> +#define USBD_POWER 0 +#define USBD_MAX_PACKET0 64 +#define USBD_DEVDESC_IDVENDOR 0x0D28 +#define USBD_DEVDESC_IDPRODUCT 0x0204 +#define USBD_DEVDESC_BCDDEVICE 0x1000 //was 0x0100 + +// <h> Configuration Settings +// <i> These settings affect Configuration Descriptor +// <o0.5> Remote Wakeup +// <i> Configuration support for remote wakeup (D5: of bmAttributes) +// <o1.0..7> Maximum Power Consumption (in mA) <0-510><#/2> +// <i> Maximum power consumption of the USB device +// <i> from the bus in this specific configuration +// <i> when the device is fully operational (bMaxPower) +// </h> +#define USBD_CFGDESC_BMATTRIBUTES 0x80 +#define USBD_CFGDESC_BMAXPOWER 0xFA + +// <h> String Settings +// <i> These settings affect String Descriptor +// <o0.0..15> Language ID <0x0000-0xFCFF> +// <i> English (United States) = 0x0409 +// <s0.126> Manufacturer String +// <i> String descriptor describing manufacturer +// <s1.126> Product String +// <i> String descriptor describing product +// <e1.0> Serial Number +// <i> Enable serial number string +// <i> If disabled serial number string will not be assigned to the USB Device +// <s2.126> Serial Number String +// <i> String descriptor describing device's serial number +// </e> +// </h> +#define USBD_STRDESC_LANGID 0x0409 +#define USBD_STRDESC_MAN L"ARM" +#ifndef USB_PROD_STR +#define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" +#else +#define _TOWIDE(x) L ## #x +#define TOWIDE(x) _TOWIDE(x) +#define USBD_STRDESC_PROD TOWIDE(USB_PROD_STR) +#endif +#define USBD_STRDESC_SER_ENABLE 1 +#define USBD_STRDESC_SER L"0001A0000000" + +// <e0> Class Support +// <i> Enables USB Device Class specific Requests +#define USBD_CLASS_ENABLE 1 + +// <e0.0> Human Interface Device (HID) +// <i> Enable class support for Human Interface Device (HID) +// <h> Interrupt Endpoint Settings +// <o1.0..4> Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o2.0..4> Interrupt Out Endpoint Number <0=> Not used <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <i> If interrupt out endpoint is not used select "Not used" +// <h> Endpoint Settings +// <o3.0..7> Maximum Endpoint Packet Size (in bytes) <0-64> +// <o4.0..7> Endpoint polling Interval (in ms) <1-255> +// <e5> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o6.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o6.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// <o7.0..7> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// </e> +// </h> +// </h> +// <h> Human Interface Device Settings +// <i> Device specific settings +// <s0.126> HID Interface String +// <o8.0..4> Number of Input Reports <1-32> +// <o9.0..4> Number of Output Reports <1-32> +// <o10.0..15> Maximum Input Report Size (in bytes) <1-65535> +// <o11.0..15> Maximum Output Report Size (in bytes) <1-65535> +// <o12.0..15> Maximum Feature Report Size (in bytes) <1-65535> +// </h> +// </e> +#ifndef HID_ENDPOINT +#define HID_ENDPOINT 0 +#else +#define HID_ENDPOINT 1 +#endif + +#ifndef WEBUSB_INTERFACE +#define WEBUSB_INTERFACE 0 +#else +#define WEBUSB_INTERFACE 1 +#endif + +#define USBD_HID_ENABLE HID_ENDPOINT +#define USBD_HID_EP_INTIN 1 +#define USBD_HID_EP_INTOUT 1 + +#define USBD_HID_EP_INTIN_STACK 0 +#define USBD_HID_WMAXPACKETSIZE 64 +#define USBD_HID_BINTERVAL 1 +#define USBD_HID_HS_ENABLE 0 +#define USBD_HID_HS_WMAXPACKETSIZE 64 +#define USBD_HID_HS_BINTERVAL 6 +#define USBD_HID_STRDESC L"CMSIS-DAP v1" +#define USBD_WEBUSB_STRDESC L"WebUSB: CMSIS-DAP" +#define USBD_HID_INREPORT_NUM 1 +#define USBD_HID_OUTREPORT_NUM 1 +#define USBD_HID_INREPORT_MAX_SZ 64 +#define USBD_HID_OUTREPORT_MAX_SZ 64 +#define USBD_HID_FEATREPORT_MAX_SZ 1 + +// <e0.0> Mass Storage Device (MSC) +// <i> Enable class support for Mass Storage Device (MSC) +// <h> Bulk Endpoint Settings +// <o1.0..4> Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o2.0..4> Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o3> Maximum Packet Size <1-1024> +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5> Maximum Packet Size <1-1024> +// <o6> Maximum NAK Rate <0-255> +// </e> +// </h> +// </h> +// <h> Mass Storage Device Settings +// <i> Device specific settings +// <s0.126> MSC Interface String +// <h> Inquiry Data +// <s1.8> Vendor Identification +// <s2.16> Product Identification +// <s3.4> Product Revision Level +// </h> +// </h> +// </e> +#ifndef MSC_ENDPOINT +#define MSC_ENDPOINT 0 +#else +#define MSC_ENDPOINT 1 +#endif +#define USBD_MSC_ENABLE MSC_ENDPOINT +#define USBD_MSC_EP_BULKIN 2 +#define USBD_MSC_EP_BULKOUT 2 +#define USBD_MSC_EP_BULKIN_STACK 0 +#define USBD_MSC_WMAXPACKETSIZE 64 +#define USBD_MSC_HS_ENABLE 0 +#define USBD_MSC_HS_WMAXPACKETSIZE 512 +#define USBD_MSC_HS_BINTERVAL 0 +#define USBD_MSC_STRDESC L"USB_MSC" +// Make sure changes to USBD_MSC_INQUIRY_DATA are coordinated with mbed-ls +// since this is used to detect DAPLink drives +#define USBD_MSC_INQUIRY_DATA "MBED " \ + "VFS " \ + "0.1" + +// <e0.0> Audio Device (ADC) +// <i> Enable class support for Audio Device (ADC) +// <h> Isochronous Endpoint Settings +// <o1.0..4> Isochronous Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o2.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o3.0..10> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o5.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// </e> +// </h> +// </h> +// <h> Audio Device Settings +// <i> Device specific settings +// <s0.126> Audio Control Interface String +// <s1.126> Audio Streaming (Zero Bandwidth) Interface String +// <s2.126> Audio Streaming (Operational) Interface String +// <o6.0..7> Audio Subframe Size (in bytes) <0-255> +// <o7.0..7> Sample Resolution (in bits) <0-255> +// <o8.0..23> Sample Frequency (in Hz) <0-16777215> +// <o9> Packet Size (in bytes) <1-256> +// <o10> Packet Count <1-16> +// </h> +// </e> +#define USBD_ADC_ENABLE 0 +#define USBD_ADC_EP_ISOOUT 3 +#define USBD_ADC_WMAXPACKETSIZE 64 +#define USBD_ADC_BINTERVAL 1 +#define USBD_ADC_HS_ENABLE 0 +#define USBD_ADC_HS_WMAXPACKETSIZE 64 +#define USBD_ADC_CIF_STRDESC L"USB_ADC" +#define USBD_ADC_SIF1_STRDESC L"USB_ADC1" +#define USBD_ADC_SIF2_STRDESC L"USB_ADC2" +#define USBD_ADC_BSUBFRAMESIZE 2 +#define USBD_ADC_BBITRESOLUTION 16 +#define USBD_ADC_TSAMFREQ 32000 +#define USBD_ADC_CFG_P_S 32 +#define USBD_ADC_CFG_P_C 1 + +// <e0> Communication Device (CDC) - Abstract Control Model (ACM) +// <i> Enable class support for Communication Device (CDC) - Abstract Control Model (ACM) +// <h> Interrupt Endpoint Settings +// <o1.0..4> Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o2.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o3.0..10> Endpoint polling Interval (in ms) <0-255> +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o5.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// <o6.0..10> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// </e4> +// </h> +// </h> +// <h> Bulk Endpoint Settings +// <o7.0..4> Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o8.0..4> Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o9> Maximum Packet Size <1-1024> +// <e10> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o11> Maximum Packet Size <1-1024> +// <o12> Maximum NAK Rate <0-255> +// </e10> +// </h> +// </h> +// <h> Communication Device Settings +// <i> Device specific settings +// <s0.126> Communication Class Interface String +// <s1.126> Data Class Interface String +// <o13> Maximum Communication Device Send Buffer Size +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// <o14> Maximum Communication Device Receive Buffer Size +// <i> Minimum size must be as big as maximum packet size for Bulk Out Endpoint +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// </h> +// </e> + +#ifndef CDC_ENDPOINT +#define CDC_ENDPOINT 0 +#else +#define CDC_ENDPOINT 1 +#endif +#define USBD_CDC_ACM_ENABLE CDC_ENDPOINT +#define USBD_CDC_ACM_EP_INTIN 3 +#define USBD_CDC_ACM_EP_INTIN_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE 16 +#define USBD_CDC_ACM_BINTERVAL 32 +#define USBD_CDC_ACM_HS_ENABLE 0 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE 16 +#define USBD_CDC_ACM_HS_BINTERVAL 2 +#define USBD_CDC_ACM_EP_BULKIN 4 +#define USBD_CDC_ACM_EP_BULKOUT 4 +#define USBD_CDC_ACM_EP_BULKIN_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE1 64 +#define USBD_CDC_ACM_HS_ENABLE1 0 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE1 64 +#define USBD_CDC_ACM_HS_BINTERVAL1 0 +#define USBD_CDC_ACM_CIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_DIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_SENDBUF_SIZE 64 +#define USBD_CDC_ACM_RECEIVEBUF_SIZE 64 +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Send Buffer size must be larger or equal to Bulk In maximum packet size!" +#endif +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Receive Buffer size must be larger or equal to Bulk Out maximum packet size!" +#endif + +// <e0> Custom Class Device +// <i> Enables USB Custom Class Requests +// <i> Class IDs: +// <i> 0x00 - Class Reserved ID +// <i> 0x01 - Class Audio ID +// <i> 0x02 - Class Communications ID +// <i> 0x03 - Class Human Interface ID +// <i> 0x04 - Class Monitor ID +// <i> 0x05 - Class Physical Interface ID +// <i> 0x06 - Class Power ID +// <i> 0x07 - Class Printer ID +// <i> 0x08 - Class Storage ID +// <i> 0x09 - Class HUB ID +// <i> 0xEF - Class Miscellaneous ID +// <i> 0xFF - Class Vendor Specific ID +// </e> +#define USBD_CLS_ENABLE 0 + +// WebUSB support +#define USBD_WEBUSB_ENABLE WEBUSB_INTERFACE +#define USBD_WEBUSB_VENDOR_CODE 0x21 +#define USBD_WEBUSB_LANDING_URL "os.mbed.com/webusb/landing-page/?bid=" +#define USBD_WEBUSB_ORIGIN_URL "os.mbed.com/" + +// Microsoft OS Descriptors 2.0 (WinUSB) support +#define USBD_WINUSB_ENABLE WINUSB_INTERFACE +#define USBD_WINUSB_VENDOR_CODE 0x20 +// </e> +// </e> + +#ifndef BULK_ENDPOINT +#define BULK_ENDPOINT 0 +#else +#define BULK_ENDPOINT 1 +#endif +#define USBD_BULK_ENABLE BULK_ENDPOINT +#define USBD_BULK_EP_BULKIN 5 +#define USBD_BULK_EP_BULKOUT 5 +#define USBD_BULK_WMAXPACKETSIZE 64 +#define USBD_BULK_HS_ENABLE 0 +#define USBD_BULK_HS_WMAXPACKETSIZE 512 +#define USBD_BULK_STRDESC L"CMSIS-DAP v2" + + +/* USB Device Calculations ---------------------------------------------------*/ + +#define USBD_IF_NUM_MAX (USBD_BULK_ENABLE+USBD_WEBUSB_ENABLE+USBD_HID_ENABLE+USBD_MSC_ENABLE+(USBD_ADC_ENABLE*2)+(USBD_CDC_ACM_ENABLE*2)+USBD_CLS_ENABLE) +#define USBD_MULTI_IF (USBD_CDC_ACM_ENABLE*(USBD_HID_ENABLE|USBD_MSC_ENABLE|USBD_ADC_ENABLE|USBD_CLS_ENABLE|USBD_WEBUSB_ENABLE|USBD_BULK_ENABLE)) +// #define MAX(x, y) (((x) < (y)) ? (y) : (x)) +#define USBD_EP_NUM_CALC0 MAX((USBD_HID_ENABLE *(USBD_HID_EP_INTIN )), (USBD_HID_ENABLE *(USBD_HID_EP_INTOUT!=0)*(USBD_HID_EP_INTOUT))) +#define USBD_EP_NUM_CALC1 MAX((USBD_MSC_ENABLE *(USBD_MSC_EP_BULKIN )), (USBD_MSC_ENABLE *(USBD_MSC_EP_BULKOUT))) +#define USBD_EP_NUM_CALC2 MAX((USBD_ADC_ENABLE *(USBD_ADC_EP_ISOOUT )), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_INTIN))) +#define USBD_EP_NUM_CALC3 MAX((USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKIN)), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKOUT))) +#define USBD_EP_NUM_CALC4 MAX(USBD_EP_NUM_CALC0, USBD_EP_NUM_CALC1) +#define USBD_EP_NUM_CALC5 MAX(USBD_EP_NUM_CALC2, USBD_EP_NUM_CALC3) +#define USBD_EP_NUM_CALC6 MAX(USBD_EP_NUM_CALC4, USBD_EP_NUM_CALC5) +#define USBD_EP_NUM_CALC7 MAX((USBD_BULK_ENABLE*(USBD_BULK_EP_BULKIN)), (USBD_BULK_ENABLE*(USBD_BULK_EP_BULKOUT))) +#define USBD_EP_NUM MAX(USBD_EP_NUM_CALC6, USBD_EP_NUM_CALC7) + + +#if (USBD_HID_ENABLE) +#if (USBD_MSC_ENABLE) +#if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_MSC_EP_BULKOUT))) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKOUT))) +#error "HID and Mass Storage Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_ADC_ENABLE) +#if ((USBD_HID_EP_INTIN == USBD_ADC_EP_ISOOUT) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_ADC_EP_ISOOUT))) +#error "HID and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (((USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKOUT))|| \ + ((USBD_HID_EP_INTOUT != 0) && \ + ((USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKOUT)))) +#error "HID and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_MSC_ENABLE) +#if (USBD_ADC_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_ADC_EP_ISOOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_ADC_EP_ISOOUT)) +#error "Mass Storage Device and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Mass Storage Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_ADC_ENABLE) +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Audio Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#define USBD_ADC_CIF_NUM (0) +#define USBD_ADC_SIF1_NUM (1) +#define USBD_ADC_SIF2_NUM (2) + + +#define USBD_ADC_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+0) +#define USBD_ADC_SIF1_STR_NUM (3+USBD_STRDESC_SER_ENABLE+1) +#define USBD_ADC_SIF2_STR_NUM (3+USBD_STRDESC_SER_ENABLE+2) +#define USBD_CDC_ACM_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+0) +#define USBD_CDC_ACM_DIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+1) +#define USBD_HID_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2) +#define USBD_WEBUSB_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) +#define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) +#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) + + +#if (USBD_HID_ENABLE) +#if (USBD_HID_HS_ENABLE) +#define USBD_HID_MAX_PACKET ((USBD_HID_HS_WMAXPACKETSIZE > USBD_HID_WMAXPACKETSIZE) ? USBD_HID_HS_WMAXPACKETSIZE : USBD_HID_WMAXPACKETSIZE) +#else +#define USBD_HID_MAX_PACKET (USBD_HID_WMAXPACKETSIZE) +#endif +#else +#define USBD_HID_MAX_PACKET (0) +#endif +#if (USBD_MSC_ENABLE) +#if (USBD_MSC_HS_ENABLE) +#define USBD_MSC_MAX_PACKET ((USBD_MSC_HS_WMAXPACKETSIZE > USBD_MSC_WMAXPACKETSIZE) ? USBD_MSC_HS_WMAXPACKETSIZE : USBD_MSC_WMAXPACKETSIZE) +#else +#define USBD_MSC_MAX_PACKET (USBD_MSC_WMAXPACKETSIZE) +#endif +#else +#define USBD_MSC_MAX_PACKET (0) +#endif +#if (USBD_ADC_ENABLE) +#if (USBD_ADC_HS_ENABLE) +#define USBD_ADC_MAX_PACKET ((USBD_ADC_HS_WMAXPACKETSIZE > USBD_ADC_WMAXPACKETSIZE) ? USBD_ADC_HS_WMAXPACKETSIZE : USBD_ADC_WMAXPACKETSIZE) +#else +#define USBD_ADC_MAX_PACKET (USBD_ADC_WMAXPACKETSIZE) +#endif +#else +#define USBD_ADC_MAX_PACKET (0) +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (USBD_CDC_ACM_HS_ENABLE) +#define USBD_CDC_ACM_MAX_PACKET ((USBD_CDC_ACM_HS_WMAXPACKETSIZE > USBD_CDC_ACM_WMAXPACKETSIZE) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE : USBD_CDC_ACM_WMAXPACKETSIZE) +#else +#define USBD_CDC_ACM_MAX_PACKET (USBD_CDC_ACM_WMAXPACKETSIZE) +#endif +#if (USBD_CDC_ACM_HS_ENABLE1) +#define USBD_CDC_ACM_MAX_PACKET1 ((USBD_CDC_ACM_HS_WMAXPACKETSIZE1 > USBD_CDC_ACM_WMAXPACKETSIZE1) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE1 : USBD_CDC_ACM_WMAXPACKETSIZE1) +#else +#define USBD_CDC_ACM_MAX_PACKET1 (USBD_CDC_ACM_WMAXPACKETSIZE1) +#endif +#else +#define USBD_CDC_ACM_MAX_PACKET (0) +#define USBD_CDC_ACM_MAX_PACKET1 (0) +#endif + +#if (USBD_BULK_ENABLE) +#if (USBD_BULK_HS_ENABLE) +#define USBD_BULK_MAX_PACKET ((USBD_BULK_HS_WMAXPACKETSIZE > USBD_BULK_WMAXPACKETSIZE) ? USBD_BULK_HS_WMAXPACKETSIZE : USBD_BULK_WMAXPACKETSIZE) +#else +#define USBD_BULK_MAX_PACKET (USBD_BULK_WMAXPACKETSIZE) +#endif +#else +#define USBD_BULK_MAX_PACKET (0) +#endif + +#define USBD_MAX_PACKET_CALC0 ((USBD_HID_MAX_PACKET > USBD_HID_MAX_PACKET ) ? (USBD_HID_MAX_PACKET ) : (USBD_HID_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC1 ((USBD_ADC_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET ) ? (USBD_ADC_MAX_PACKET ) : (USBD_CDC_ACM_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC2 ((USBD_MAX_PACKET_CALC0 > USBD_MAX_PACKET_CALC1 ) ? (USBD_MAX_PACKET_CALC0) : (USBD_MAX_PACKET_CALC1 )) +#define USBD_MAX_PACKET_CALC3 ((USBD_BULK_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET1 ) ? (USBD_BULK_MAX_PACKET) : (USBD_CDC_ACM_MAX_PACKET1 )) +#define USBD_MAX_PACKET ((USBD_MAX_PACKET_CALC3 > USBD_MAX_PACKET_CALC2 ) ? (USBD_MAX_PACKET_CALC3) : (USBD_MAX_PACKET_CALC2 )) + +/*------------------------------------------------------------------------------ + * USB Config Functions + *----------------------------------------------------------------------------*/ + +#ifndef __USB_CONFIG___ +#define __USB_CONFIG__ + +#ifndef __NO_USB_LIB_C +#include "usb_lib.c" +#endif + +#endif /* __USB_CONFIG__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/freescale/usbd_kinetis.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/freescale/usbd_kinetis.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,819 @@
+/**
+ * @file usbd_kinetis.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "rl_usb.h"
+#include "fsl_device_registers.h"
+#include "cortex_m.h"
+#include "util.h"
+#include "string.h"
+
+#define __NO_USB_LIB_C
+#include "usb_config.c"
+
+typedef struct __BUF_DESC {
+ uint8_t stat;
+ uint8_t reserved;
+ uint16_t bc;
+ uint32_t buf_addr;
+} BUF_DESC;
+
+BUF_DESC __align(512) BD[(USBD_EP_NUM + 1) * 2 * 2];
+uint8_t EPBuf[(USBD_EP_NUM + 1) * 2 * 2][64];
+uint8_t OutEpSize[USBD_EP_NUM + 1];
+uint8_t StatQueue[(USBD_EP_NUM + 1) * 2 * 2 + 1];
+uint32_t StatQueueHead = 0;
+uint32_t StatQueueTail = 0;
+uint32_t LastIstat = 0;
+uint8_t UsbSuspended = 0;
+uint8_t Ep0ZlpOut = 0;
+
+uint32_t Data1 = 0x55555555;
+
+#define BD_OWN_MASK 0x80
+#define BD_DATA01_MASK 0x40
+#define BD_KEEP_MASK 0x20
+#define BD_NINC_MASK 0x10
+#define BD_DTS_MASK 0x08
+#define BD_STALL_MASK 0x04
+
+#define TX 1
+#define RX 0
+#define ODD 0
+#define EVEN 1
+#define IDX(Ep, dir, Ev_Odd) ((((Ep & 0x0F) * 4) + (2 * dir) + (1 * Ev_Odd)))
+
+#define SETUP_TOKEN 0x0D
+#define IN_TOKEN 0x09
+#define OUT_TOKEN 0x01
+#define TOK_PID(idx) ((BD[idx].stat >> 2) & 0x0F)
+
+inline static void protected_and(uint32_t *addr, uint32_t val)
+{
+ cortex_int_state_t state;
+ state = cortex_int_get_and_disable();
+ *addr = *addr & val;
+ cortex_int_restore(state);
+}
+inline static void protected_or(uint32_t *addr, uint32_t val)
+{
+ cortex_int_state_t state;
+ state = cortex_int_get_and_disable();
+ *addr = *addr | val;
+ cortex_int_restore(state);
+}
+inline static void protected_xor(uint32_t *addr, uint32_t val)
+{
+ cortex_int_state_t state;
+ state = cortex_int_get_and_disable();
+ *addr = *addr ^ val;
+ cortex_int_restore(state);
+}
+
+inline static void stat_enque(uint32_t stat)
+{
+ cortex_int_state_t state;
+ state = cortex_int_get_and_disable();
+ StatQueue[StatQueueTail] = stat;
+ StatQueueTail = (StatQueueTail + 1) % sizeof(StatQueue);
+ cortex_int_restore(state);
+}
+
+inline static uint32_t stat_deque()
+{
+ cortex_int_state_t state;
+ uint32_t stat;
+ state = cortex_int_get_and_disable();
+ stat = StatQueue[StatQueueHead];
+ StatQueueHead = (StatQueueHead + 1) % sizeof(StatQueue);
+ cortex_int_restore(state);
+
+ return stat;
+}
+
+inline static uint32_t stat_is_empty()
+{
+ cortex_int_state_t state;
+ uint32_t empty;
+ state = cortex_int_get_and_disable();
+ empty = StatQueueHead == StatQueueTail;
+ cortex_int_restore(state);
+ return empty;
+}
+
+/*
+ * USB Device Interrupt enable
+ * Called by USBD_Init to enable the USB Interrupt
+ * Return Value: None
+ */
+
+void USBD_IntrEna(void)
+{
+ NVIC_EnableIRQ(USB0_IRQn); /* Enable OTG interrupt */
+}
+
+
+/*
+ * USB Device Initialize Function
+ * Called by the User to initialize USB
+ * Return Value: None
+ */
+
+void USBD_Init(void)
+{
+ OutEpSize[0] = USBD_MAX_PACKET0;
+ /* Enable all clocks needed for USB to function */
+ /* Set USB clock to 48 MHz */
+ SIM->SOPT2 |= SIM_SOPT2_USBSRC_MASK | /* MCGPLLCLK used as src */
+ SIM_SOPT2_PLLFLLSEL_MASK ; /* Select MCGPLLCLK as clock */
+#if defined(TARGET_MK20D5)
+ SIM->CLKDIV2 &= ~(SIM_CLKDIV2_USBFRAC_MASK | /* Clear CLKDIV2 FS values */
+ SIM_CLKDIV2_USBDIV_MASK);
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) ; /* USB clk = (PLL*1/2) */
+ /* = ( 48*1/1)=48 */
+#endif // TARGET_MK20D5
+ SIM->SCGC4 |= SIM_SCGC4_USBOTG_MASK; /* Enable USBOTG clock */
+ USBD_IntrEna();
+ USB0->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
+
+ while (USB0->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
+
+ USB0->BDTPAGE1 = (uint8_t)((uint32_t) BD >> 8);
+ USB0->BDTPAGE2 = (uint8_t)((uint32_t) BD >> 16);
+ USB0->BDTPAGE3 = (uint8_t)((uint32_t) BD >> 24);
+ USB0->ISTAT = 0xFF; /* clear interrupt flags */
+ /* enable interrupts */
+ USB0->INTEN = USB_INTEN_USBRSTEN_MASK |
+ USB_INTEN_TOKDNEEN_MASK |
+ USB_INTEN_SLEEPEN_MASK |
+#ifdef __RTX
+ ((USBD_RTX_DevTask != 0) ? USB_INTEN_SOFTOKEN_MASK : 0) |
+ ((USBD_RTX_DevTask != 0) ? USB_INTEN_ERROREN_MASK : 0) ;
+#else
+ ((USBD_P_SOF_Event != 0) ? USB_INTEN_SOFTOKEN_MASK : 0) |
+ ((USBD_P_Error_Event != 0) ? USB_INTEN_ERROREN_MASK : 0) ;
+#endif
+ USB0->USBCTRL = USB_USBCTRL_PDE_MASK;/* pull dawn on D+ and D- */
+ USB0->USBTRC0 |= (1 << 6); /* bit 6 must be set to 1 */
+}
+
+
+/*
+ * USB Device Connect Function
+ * Called by the User to Connect/Disconnect USB Device
+ * Parameters: con: Connect/Disconnect
+ * Return Value: None
+ */
+
+void USBD_Connect(uint32_t con)
+{
+ if (con) {
+ USB0->CTL |= USB_CTL_USBENSOFEN_MASK; /* enable USB */
+ USB0->CONTROL = USB_CONTROL_DPPULLUPNONOTG_MASK; /* pull up on D+ */
+ } else {
+ USB0->CTL &= ~USB_CTL_USBENSOFEN_MASK; /* disable USB */
+ USB0->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK;/* pull down on D+ */
+ }
+}
+
+
+/*
+ * USB Device Reset Function
+ * Called automatically on USB Device Reset
+ * Return Value: None
+ */
+
+void USBD_Reset(void)
+{
+ uint32_t i;
+
+ NVIC_DisableIRQ(USB0_IRQn);
+
+ for (i = 1; i < 16; i++) {
+ USB0->ENDPOINT[i].ENDPT = 0x00;
+ }
+
+ memset(StatQueue, 0, sizeof(StatQueue));
+ StatQueueHead = 0;
+ StatQueueTail = 0;
+ LastIstat = 0;
+ UsbSuspended = 0;
+ Ep0ZlpOut = 0;
+
+ /* EP0 control endpoint */
+ BD[IDX(0, RX, ODD)].bc = USBD_MAX_PACKET0;
+ BD[IDX(0, RX, ODD)].buf_addr = (uint32_t) & (EPBuf[IDX(0, RX, ODD)][0]);
+ BD[IDX(0, RX, ODD)].stat = BD_OWN_MASK | BD_DTS_MASK | BD_DATA01_MASK;
+ BD[IDX(0, RX, EVEN)].stat = 0;
+ BD[IDX(0, TX, ODD)].buf_addr = (uint32_t) & (EPBuf[IDX(0, TX, ODD)][0]);
+ BD[IDX(0, TX, EVEN)].buf_addr = 0;
+ USB0->ENDPOINT[0].ENDPT = USB_ENDPT_EPHSHK_MASK | /* enable ep handshaking */
+ USB_ENDPT_EPTXEN_MASK | /* enable TX (IN) tran. */
+ USB_ENDPT_EPRXEN_MASK; /* enable RX (OUT) tran. */
+ Data1 = 0x55555555;
+ USB0->CTL |= USB_CTL_ODDRST_MASK;
+ USB0->ISTAT = 0xFF; /* clear all interrupt status flags */
+ USB0->ERRSTAT = 0xFF; /* clear all error flags */
+ USB0->ERREN = 0xFF; /* enable error interrupt sources */
+ USB0->ADDR = 0x00; /* set default address */
+
+ NVIC_EnableIRQ(USB0_IRQn);
+}
+
+
+/*
+ * USB Device Suspend Function
+ * Called automatically on USB Device Suspend
+ * Return Value: None
+ */
+
+void USBD_Suspend(void)
+{
+ USB0->INTEN |= USB_INTEN_RESUMEEN_MASK;
+}
+
+
+/*
+ * USB Device Resume Function
+ * Called automatically on USB Device Resume
+ * Return Value: None
+ */
+
+void USBD_Resume(void)
+{
+ USB0->INTEN &= ~USB_INTEN_RESUMEEN_MASK;
+}
+
+
+/*
+ * USB Device Remote Wakeup Function
+ * Called automatically on USB Device Remote Wakeup
+ * Return Value: None
+ */
+
+void USBD_WakeUp(void)
+{
+ uint32_t i = 50000;
+
+ if (USBD_DeviceStatus & USB_GETSTATUS_REMOTE_WAKEUP) {
+ USB0->CTL |= USB_CTL_RESUME_MASK;
+
+ while (i--) {
+ __nop();
+ }
+
+ USB0->CTL &= ~USB_CTL_RESUME_MASK;
+ }
+}
+
+
+/*
+ * USB Device Remote Wakeup Configuration Function
+ * Parameters: cfg: Device Enable/Disable
+ * Return Value: None
+ */
+
+void USBD_WakeUpCfg(uint32_t cfg)
+{
+ /* Not needed */
+}
+
+
+/*
+ * USB Device Set Address Function
+ * Parameters: adr: USB Device Address
+ * Return Value: None
+ */
+
+void USBD_SetAddress(uint32_t adr, uint32_t setup)
+{
+ if (!setup) {
+ USB0->ADDR = adr & 0x7F;
+ }
+}
+
+
+/*
+ * USB Device Configure Function
+ * Parameters: cfg: Device Configure/Deconfigure
+ * Return Value: None
+ */
+
+void USBD_Configure(uint32_t cfg)
+{
+}
+
+
+/*
+ * Configure USB Device Endpoint according to Descriptor
+ * Parameters: pEPD: Pointer to Device Endpoint Descriptor
+ * Return Value: None
+ */
+
+void USBD_ConfigEP(USB_ENDPOINT_DESCRIPTOR *pEPD)
+{
+ uint32_t num, val;
+ num = pEPD->bEndpointAddress;
+ val = pEPD->wMaxPacketSize;
+
+ if (!(pEPD->bEndpointAddress & 0x80)) {
+ OutEpSize[num] = val;
+ }
+
+ USBD_ResetEP(num);
+}
+
+
+/*
+ * Set Direction for USB Device Control Endpoint
+ * Parameters: dir: Out (dir == 0), In (dir <> 0)
+ * Return Value: None
+ */
+
+void USBD_DirCtrlEP(uint32_t dir)
+{
+ /* Not needed */
+}
+
+
+/*
+ * Enable USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_EnableEP(uint32_t EPNum)
+{
+ if (EPNum & 0x80) {
+ EPNum &= 0x0F;
+ USB0->ENDPOINT[EPNum].ENDPT |= USB_ENDPT_EPHSHK_MASK | /*en ep handshaking*/
+ USB_ENDPT_EPTXEN_MASK; /*en TX (IN) tran */
+ } else {
+ USB0->ENDPOINT[EPNum].ENDPT |= USB_ENDPT_EPHSHK_MASK | /*en ep handshaking*/
+ USB_ENDPT_EPRXEN_MASK; /*en RX (OUT) tran.*/
+ }
+}
+
+
+/*
+ * Disable USB Endpoint
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_DisableEP(uint32_t EPNum)
+{
+ if (EPNum & 0x80) {
+ EPNum &= 0x0F;
+ USB0->ENDPOINT[EPNum].ENDPT &= ~(USB_ENDPT_EPHSHK_MASK |/*dis handshaking */
+ USB_ENDPT_EPTXEN_MASK);/*dis TX(IN) tran */
+ } else {
+ USB0->ENDPOINT[EPNum].ENDPT &= ~(USB_ENDPT_EPHSHK_MASK |/*dis handshaking */
+ USB_ENDPT_EPRXEN_MASK);/*dis RX(OUT) tran*/
+ }
+}
+
+
+/*
+ * Reset USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_ResetEP(uint32_t EPNum)
+{
+ if (EPNum & 0x80) {
+ EPNum &= 0x0F;
+ protected_or(&Data1, (1 << ((EPNum * 2) + 1)));
+ BD[IDX(EPNum, TX, ODD)].buf_addr = (uint32_t) & (EPBuf[IDX(EPNum, TX, ODD)][0]);
+ BD[IDX(EPNum, TX, EVEN)].buf_addr = 0;
+ } else {
+ protected_and(&Data1, ~(1 << (EPNum * 2)));
+ BD[IDX(EPNum, RX, ODD)].bc = OutEpSize[EPNum];
+ BD[IDX(EPNum, RX, ODD)].buf_addr = (uint32_t) & (EPBuf[IDX(EPNum, RX, ODD)][0]);
+ BD[IDX(EPNum, RX, ODD)].stat = BD_OWN_MASK | BD_DTS_MASK;
+ BD[IDX(EPNum, RX, EVEN)].stat = 0;
+ }
+}
+
+/*
+ * Set Stall for USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_SetStallEP(uint32_t EPNum)
+{
+ EPNum &= 0x0F;
+ USB0->ENDPOINT[EPNum].ENDPT |= USB_ENDPT_EPSTALL_MASK;
+}
+
+
+/*
+ * Clear Stall for USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_ClrStallEP(uint32_t EPNum)
+{
+ USB0->ENDPOINT[EPNum & 0x0F].ENDPT &= ~USB_ENDPT_EPSTALL_MASK;
+ USBD_ResetEP(EPNum);
+}
+
+
+/*
+ * Clear USB Device Endpoint Buffer
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_ClearEPBuf(uint32_t EPNum)
+{
+}
+
+
+/*
+ * Read USB Device Endpoint Data
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * pData: Pointer to Data Buffer
+ * Return Value: Number of bytes read
+ */
+
+uint32_t USBD_ReadEP(uint32_t EPNum, uint8_t *pData, uint32_t size)
+{
+ uint32_t n, sz, idx, setup = 0;
+ idx = IDX(EPNum, RX, 0);
+ sz = BD[idx].bc;
+
+ if ((EPNum == 0) && Ep0ZlpOut) {
+ // This packet was a zero length data out packet. It has already
+ // been processed by USB0_IRQHandler. Only toggle the DATAx bit
+ // and return a size of 0.
+ protected_xor(&Data1, (1 << (idx / 2)));
+ return 0;
+ }
+
+ if ((EPNum == 0) && (TOK_PID(idx) == SETUP_TOKEN)) {
+ setup = 1;
+ }
+
+ if (size < sz) {
+ util_assert(0);
+ sz = size;
+ }
+
+ for (n = 0; n < sz; n++) {
+ pData[n] = EPBuf[idx][n];
+ }
+
+ BD[idx].bc = OutEpSize[EPNum];
+
+ if ((Data1 >> (idx / 2) & 1) == ((BD[idx].stat >> 6) & 1)) {
+ uint32_t xfer_size = (pData[7] << 8) | (pData[6] << 0);
+ if (setup && (0 == xfer_size)) { /* if no setup data stage, */
+ protected_and(&Data1, ~1); /* set DATA0 */
+ } else {
+ protected_xor(&Data1, (1 << (idx / 2)));
+ }
+ }
+
+ if ((Data1 >> (idx / 2)) & 1) {
+ BD[idx].stat = BD_DTS_MASK | BD_DATA01_MASK;
+ BD[idx].stat |= BD_OWN_MASK;
+ } else {
+ BD[idx].stat = BD_DTS_MASK;
+ BD[idx].stat |= BD_OWN_MASK;
+ }
+
+ return (sz);
+}
+
+
+/*
+ * Write USB Device Endpoint Data
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * pData: Pointer to Data Buffer
+ * cnt: Number of bytes to write
+ * Return Value: Number of bytes written
+ */
+
+uint32_t USBD_WriteEP(uint32_t EPNum, uint8_t *pData, uint32_t cnt)
+{
+ uint32_t idx, n;
+ EPNum &= 0x0F;
+ idx = IDX(EPNum, TX, 0);
+ BD[idx].bc = cnt;
+
+ for (n = 0; n < cnt; n++) {
+ EPBuf[idx][n] = pData[n];
+ }
+
+ if ((Data1 >> (idx / 2)) & 1) {
+ BD[idx].stat = BD_OWN_MASK | BD_DTS_MASK;
+ } else {
+ BD[idx].stat = BD_OWN_MASK | BD_DTS_MASK | BD_DATA01_MASK;
+ }
+
+ protected_xor(&Data1, (1 << (idx / 2)));
+ return (cnt);
+}
+
+/*
+ * Get USB Device Last Frame Number
+ * Parameters: None
+ * Return Value: Frame Number
+ */
+
+uint32_t USBD_GetFrame(void)
+{
+ return ((USB0->FRMNUML | (USB0->FRMNUMH << 8) & 0x07FF));
+}
+
+#ifdef __RTX
+U32 LastError; /* Last Error */
+
+/*
+ * Get USB Device Last Error Code
+ * Parameters: None
+ * Return Value: Error Code
+ */
+
+U32 USBD_GetError(void)
+{
+ return (LastError);
+}
+#endif
+
+
+/*
+ * USB Device Interrupt Service Routine
+ */
+void USB0_IRQHandler(void)
+{
+ uint32_t istat, num, dir, ev_odd;
+ uint32_t new_istat;
+ uint8_t suspended = 0;
+
+ new_istat = istat = USB0->ISTAT;
+
+ // Read all tokens
+ if (istat & USB_ISTAT_TOKDNE_MASK) {
+ while (istat & USB_ISTAT_TOKDNE_MASK) {
+ uint8_t stat = USB0->STAT;
+ num = (stat >> 4) & 0x0F;
+ dir = (stat >> 3) & 0x01;
+ ev_odd = (stat >> 2) & 0x01;
+
+ // Consume all zero length OUT packets on endpoint 0 to prevent
+ // a subsequent SETUP packet from being dropped
+ if ((0 == num) && (RX == dir)) {
+ uint32_t idx;
+ idx = IDX(num, dir, ev_odd);
+ if ((TOK_PID(idx) == OUT_TOKEN) && (BD[idx].bc == 0)) {
+ BD[idx].bc = OutEpSize[num];
+ if (BD[idx].stat & BD_DATA01_MASK) {
+ BD[idx].stat = BD_OWN_MASK | BD_DTS_MASK;
+ } else {
+ BD[idx].stat = BD_OWN_MASK | BD_DTS_MASK | BD_DATA01_MASK;
+ }
+ stat |= 1 << 0;
+ }
+ }
+
+ stat_enque(stat);
+ USB0->ISTAT = USB_ISTAT_TOKDNE_MASK;
+
+ // Check if USB is suspending before checking istat
+ suspended = suspended || USB0->CTL & USB_CTL_TXSUSPENDTOKENBUSY_MASK;
+ istat = USB0->ISTAT;
+ }
+ }
+
+ // Set global istat and suspended flags
+ new_istat |= istat;
+ protected_or(&LastIstat, new_istat);
+ UsbSuspended |= suspended ? 1 : 0;
+ USB0->ISTAT = istat;
+
+ USBD_SignalHandler();
+}
+
+/*
+ * USB Device Service Routine
+ */
+
+void USBD_Handler(void)
+{
+ uint32_t istr, num, dir, ev_odd;
+ cortex_int_state_t state;
+ uint8_t suspended = 0;
+
+ // Get ISTAT
+ state = cortex_int_get_and_disable();
+ istr = LastIstat;
+ LastIstat = 0;
+ suspended = UsbSuspended;
+ UsbSuspended = 0;
+ cortex_int_restore(state);
+
+
+ /* reset interrupt */
+ if (istr & USB_ISTAT_USBRST_MASK) {
+ USBD_Reset();
+ usbd_reset_core();
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_RESET, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Reset_Event) {
+ USBD_P_Reset_Event();
+ }
+
+#endif
+ }
+
+ /* suspend interrupt */
+ if (istr & USB_ISTAT_SLEEP_MASK) {
+ USBD_Suspend();
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_SUSPEND, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Suspend_Event) {
+ USBD_P_Suspend_Event();
+ }
+
+#endif
+ }
+
+ /* resume interrupt */
+ if (istr & USB_ISTAT_RESUME_MASK) {
+ USBD_Resume();
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_RESUME, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Resume_Event) {
+ USBD_P_Resume_Event();
+ }
+
+#endif
+ }
+
+ /* Start Of Frame */
+ if (istr & USB_ISTAT_SOFTOK_MASK) {
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_SOF, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_SOF_Event) {
+ USBD_P_SOF_Event();
+ }
+
+#endif
+ }
+
+ /* Error interrupt */
+ if (istr == USB_ISTAT_ERROR_MASK) {
+#ifdef __RTX
+ LastError = USB0->ERRSTAT;
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_ERROR, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Error_Event) {
+ USBD_P_Error_Event(USB0->ERRSTAT);
+ }
+
+#endif
+ USB0->ERRSTAT = 0xFF;
+ }
+
+ /* token interrupt */
+ if (istr & USB_ISTAT_TOKDNE_MASK) {
+ while (!stat_is_empty()) {
+ uint32_t stat;
+
+ stat = stat_deque();
+ num = (stat >> 4) & 0x0F;
+ dir = (stat >> 3) & 0x01;
+ ev_odd = (stat >> 2) & 0x01;
+
+ /* setup packet */
+ if ((num == 0) && (TOK_PID((IDX(num, dir, ev_odd))) == SETUP_TOKEN)) {
+ Data1 &= ~0x02;
+ BD[IDX(0, TX, EVEN)].stat &= ~BD_OWN_MASK;
+ BD[IDX(0, TX, ODD)].stat &= ~BD_OWN_MASK;
+ Ep0ZlpOut = 0;
+#ifdef __RTX
+
+ if (USBD_RTX_EPTask[num]) {
+ isr_evt_set(USBD_EVT_SETUP, USBD_RTX_EPTask[num]);
+ }
+
+#else
+
+ if (USBD_P_EP[num]) {
+ USBD_P_EP[num](USBD_EVT_SETUP);
+ }
+
+#endif
+
+ } else {
+ /* OUT packet */
+ if (TOK_PID((IDX(num, dir, ev_odd))) == OUT_TOKEN) {
+ if (0 == num) {
+ Ep0ZlpOut = stat & (1 << 0);
+ }
+#ifdef __RTX
+
+ if (USBD_RTX_EPTask[num]) {
+ isr_evt_set(USBD_EVT_OUT, USBD_RTX_EPTask[num]);
+ }
+
+#else
+
+ if (USBD_P_EP[num]) {
+ USBD_P_EP[num](USBD_EVT_OUT);
+ }
+
+#endif
+ }
+
+ /* IN packet */
+ if (TOK_PID((IDX(num, dir, ev_odd))) == IN_TOKEN) {
+#ifdef __RTX
+
+ if (USBD_RTX_EPTask[num]) {
+ isr_evt_set(USBD_EVT_IN, USBD_RTX_EPTask[num]);
+ }
+
+#else
+
+ if (USBD_P_EP[num]) {
+ USBD_P_EP[num](USBD_EVT_IN);
+ }
+
+#endif
+ }
+ }
+ }
+ }
+
+ if (suspended) {
+ USB0->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
+ }
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/gpio.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/gpio.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,58 @@
+/**
+ * @file gpio.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef GPIO_H
+#define GPIO_H
+
+#include <stdbool.h>
+#include "IO_Config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// wiring on PCB is unknown so implementations may vary
+typedef enum led_state {
+ GPIO_LED_OFF = 0,
+ GPIO_LED_ON
+} gpio_led_state_t;
+
+void gpio_init(void);
+void gpio_set_board_power(bool powerEnabled);
+void gpio_set_hid_led(gpio_led_state_t state);
+void gpio_set_cdc_led(gpio_led_state_t state);
+void gpio_set_msc_led(gpio_led_state_t state);
+uint8_t gpio_get_reset_btn_no_fwrd(void);
+uint8_t gpio_get_reset_btn_fwrd(void);
+#ifdef PBON_BUTTON
+uint8_t gpio_get_pbon_btn(void);
+#endif
+
+static inline uint8_t gpio_get_reset_btn(void)
+{
+ return gpio_get_reset_btn_no_fwrd() || gpio_get_reset_btn_fwrd();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/DAP_config.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32620/DAP_config.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,514 @@
+#ifndef __DAP_CONFIG_H__
+#define __DAP_CONFIG_H__
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
+\ingroup DAP_ConfigIO_gr
+@{
+Provides definitions about:
+ - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
+ - Debug Unit communication packet size.
+ - Debug Access Port communication mode (JTAG or SWD).
+ - Optional information about a connected Target Device (for Evaluation Boards).
+*/
+
+#include <stdio.h>
+#include "max32620.h" // Debug Unit Cortex-M Processor Header File
+#include "clkman_regs.h"
+#include "gpio_regs.h"
+#include "IO_Config.h"
+
+/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
+/// This value is used to calculate the SWD/JTAG clock speed.
+#define CPU_CLOCK SystemCoreClock ///< Specifies the CPU Clock in Hz
+
+/// Number of processor cycles for I/O Port write operations.
+/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
+/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
+/// requrie 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
+/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
+/// required.
+#define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles
+
+/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available
+
+/// Indicate that JTAG communication mode is available at the Debug Port.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define DAP_JTAG 0 ///< JTAG Mode: 1 = available
+
+/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
+/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
+#define DAP_JTAG_DEV_CNT 8 ///< Maximum number of JTAG devices on scan chain
+
+/// Default communication mode on the Debug Access Port.
+/// Used for the command \ref DAP_Connect when Port Default mode is selected.
+#define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
+
+/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
+/// Used to initialize the default SWD/JTAG clock frequency.
+/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
+#define DAP_DEFAULT_SWJ_CLOCK 3000000 ///< Default SWD/JTAG clock frequency in Hz.
+
+/// Maximum Package Size for Command and Response data.
+/// This configuration settings is used to optimized the communication performance with the
+/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
+#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed.
+
+/// Maximum Package Buffers for Command and Response data.
+/// This configuration settings is used to optimized the communication performance with the
+/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
+/// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
+#define DAP_PACKET_COUNT 1 ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
+
+/// Indicate that UART Serial Wire Output (SWO) trace is available.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available
+
+/// Maximum SWO UART Baudrate
+#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz
+
+/// Indicate that Manchester Serial Wire Output (SWO) trace is available.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available
+
+/// SWO Trace Buffer Size.
+#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n)
+
+/// SWO Streaming Trace.
+#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available.
+
+/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
+#define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported).
+
+/// Debug Unit is connected to fixed Target Device.
+/// The Debug Unit may be part of an evaluation board and always connected to a fixed
+/// known device. In this case a Device Vendor and Device Name string is stored which
+/// may be used by the debugger or IDE to configure device parameters.
+#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
+
+#if TARGET_DEVICE_FIXED
+#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor
+#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device
+#endif
+
+///@}
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
+\ingroup DAP_ConfigIO_gr
+@{
+
+Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
+and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
+interface of a device. The following I/O Pins are provided:
+
+JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
+---------------------------- | -------------------- | ---------------------------------------------
+TCK: Test Clock | SWCLK: Clock | Output Push/Pull
+TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
+TDI: Test Data Input | | Output Push/Pull
+TDO: Test Data Output | | Input
+nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
+nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
+
+
+DAP Hardware I/O Pin Access Functions
+-------------------------------------
+The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
+these I/O Pins.
+
+For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
+This functions are provided to achieve faster I/O that is possible with some advanced GPIO
+peripherals that can independently write/read a single I/O pin without affecting any other pins
+of the same I/O port. The following SWDIO I/O Pin functions are provided:
+ - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
+ - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
+ - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
+ - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
+*/
+
+
+// Configure DAP I/O pins ------------------------------
+
+/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
+Configures the DAP Hardware I/O pins for JTAG mode:
+ - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
+ - TDO to input mode.
+*/
+__STATIC_INLINE void PORT_JTAG_SETUP (void) {
+
+ uint32_t out_mode;
+
+ /* Ensure that the GPIO clock is enabled */
+ if (MXC_CLKMAN->sys_clk_ctrl_6_gpio == MXC_V_CLKMAN_CLK_SCALE_DISABLED) {
+ MXC_CLKMAN->sys_clk_ctrl_6_gpio = MXC_V_CLKMAN_CLK_SCALE_DIV_1;
+ }
+
+ // Setup the JTAG/SWD pins
+ MXC_GPIO->out_val[TRGT_PORT] = 0xFF; // set all pins high
+
+ out_mode = MXC_GPIO->out_mode[TRGT_PORT];
+ out_mode &= ~(0xF << (4 * SRST_PIN));
+ out_mode &= ~(0xF << (4 * RSTN_PIN));
+ out_mode &= ~(0xF << (4 * TDI_PIN));
+ out_mode &= ~(0xF << (4 * TCK_PIN));
+ out_mode &= ~(0xF << (4 * TMS_PIN));
+ out_mode &= ~(0xF << (4 * TDO_PIN));
+
+ out_mode |= (MXC_E_GPIO_OUT_MODE_OPEN_DRAIN_W_PULLUP << (4 * RSTN_PIN));
+ out_mode |= (MXC_E_GPIO_OUT_MODE_OPEN_DRAIN_W_PULLUP << (4 * SRST_PIN));
+ out_mode |= (MXC_E_GPIO_OUT_MODE_NORMAL << (4 * TCK_PIN));
+ out_mode |= (MXC_E_GPIO_OUT_MODE_NORMAL << (4 * TMS_PIN));
+ out_mode |= (MXC_E_GPIO_OUT_MODE_NORMAL << (4 * TDI_PIN));
+ MXC_GPIO->out_mode[TRGT_PORT] = out_mode;
+
+ // Setup the BUFFEN pin
+ MXC_GPIO->out_val[BUFFEN_PORT] = 0xFF; // set all pins high
+
+ out_mode = MXC_GPIO->out_mode[BUFFEN_PORT];
+ out_mode &= ~(0xF << (4 * BUFFEN_PIN));
+
+ out_mode |= (MXC_E_GPIO_OUT_MODE_NORMAL << (4 * BUFFEN_PIN));
+ MXC_GPIO->out_mode[BUFFEN_PIN] = out_mode;
+
+}
+
+/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
+Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
+ - SWCLK, SWDIO, nRESET to output mode and set to default high level.
+ - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
+*/
+__STATIC_INLINE void PORT_SWD_SETUP (void) {
+
+ uint32_t out_mode;
+
+ /* Ensure that the GPIO clock is enabled */
+ if (MXC_CLKMAN->sys_clk_ctrl_6_gpio == MXC_V_CLKMAN_CLK_SCALE_DISABLED) {
+ MXC_CLKMAN->sys_clk_ctrl_6_gpio = MXC_V_CLKMAN_CLK_SCALE_DIV_1;
+ }
+
+ // Setup the JTAG/SWD pins
+ MXC_GPIO->out_val[TRGT_PORT] = 0xFF; // set all pins high
+
+ out_mode = MXC_GPIO->out_mode[TRGT_PORT];
+ out_mode &= ~(0xF << (4 * SRST_PIN));
+ out_mode &= ~(0xF << (4 * SWCLK_PIN));
+ out_mode &= ~(0xF << (4 * SWDIO_PIN));
+
+ out_mode |= (MXC_E_GPIO_OUT_MODE_OPEN_DRAIN_W_PULLUP << (4 * SRST_PIN));
+ out_mode |= (MXC_E_GPIO_OUT_MODE_NORMAL << (4 * SWCLK_PIN));
+ out_mode |= (MXC_E_GPIO_OUT_MODE_NORMAL << (4 * SWDIO_PIN));
+ MXC_GPIO->out_mode[TRGT_PORT] = out_mode;
+
+ // Setup the BUFFEN pin
+ MXC_GPIO->out_val[BUFFEN_PORT] = 0xFF; // set all pins high
+
+ out_mode = MXC_GPIO->out_mode[BUFFEN_PORT];
+ out_mode &= ~(0xF << (4 * BUFFEN_PIN));
+
+ out_mode |= (MXC_E_GPIO_OUT_MODE_NORMAL << (4 * BUFFEN_PIN));
+ MXC_GPIO->out_mode[BUFFEN_PORT] = out_mode;
+}
+
+/** Disable JTAG/SWD I/O Pins.
+Disables the DAP Hardware I/O pins which configures:
+ - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
+*/
+__STATIC_INLINE void PORT_OFF (void) {
+
+ uint32_t out_mode;
+ out_mode = MXC_GPIO->out_mode[TRGT_PORT];
+ out_mode &= ~(0xF << (4 * SRST_PIN));
+ out_mode &= ~(0xF << (4 * RSTN_PIN));
+ out_mode &= ~(0xF << (4 * TDI_PIN));
+ out_mode &= ~(0xF << (4 * TCK_PIN));
+ out_mode &= ~(0xF << (4 * TMS_PIN));
+ out_mode &= ~(0xF << (4 * TDO_PIN));
+
+ out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * SRST_PIN));
+ out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * RSTN_PIN));
+ out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * TDI_PIN));
+ out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * TCK_PIN));
+ out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * TMS_PIN));
+ out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * TDO_PIN));
+
+ MXC_GPIO->out_mode[TRGT_PORT] = out_mode;
+}
+
+
+// SWCLK/TCK I/O pin -------------------------------------
+
+/** SWCLK/TCK I/O pin: Get Input.
+\return Current status of the SWCLK/TCK DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void) {
+ return MXC_GETBIT(&MXC_GPIO->in_val[TRGT_PORT], TCK_PIN);
+}
+
+/** SWCLK/TCK I/O pin: Set Output to High.
+Set the SWCLK/TCK DAP hardware I/O pin to high level.
+*/
+__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET (void) {
+ MXC_SETBIT(&MXC_GPIO->out_val[TRGT_PORT], TCK_PIN);
+}
+
+/** SWCLK/TCK I/O pin: Set Output to Low.
+Set the SWCLK/TCK DAP hardware I/O pin to low level.
+*/
+__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) {
+ MXC_CLRBIT(&MXC_GPIO->out_val[TRGT_PORT], TCK_PIN);
+}
+
+
+// SWDIO/TMS Pin I/O --------------------------------------
+
+/** SWDIO/TMS I/O pin: Get Input.
+\return Current status of the SWDIO/TMS DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN (void) {
+ return MXC_GETBIT(&MXC_GPIO->in_val[TRGT_PORT], TMS_PIN);
+}
+
+/** SWDIO/TMS I/O pin: Set Output to High.
+Set the SWDIO/TMS DAP hardware I/O pin to high level.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET (void) {
+ MXC_SETBIT(&MXC_GPIO->out_val[TRGT_PORT], TMS_PIN);
+}
+
+/** SWDIO/TMS I/O pin: Set Output to Low.
+Set the SWDIO/TMS DAP hardware I/O pin to low level.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR (void) {
+ MXC_CLRBIT(&MXC_GPIO->out_val[TRGT_PORT], TMS_PIN);
+}
+
+/** SWDIO I/O pin: Get Input (used in SWD mode only).
+\return Current status of the SWDIO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN (void) {
+ return MXC_GETBIT(&MXC_GPIO->in_val[TRGT_PORT], SWDIO_PIN);
+}
+
+/** SWDIO I/O pin: Set Output (used in SWD mode only).
+\param bit Output value for the SWDIO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT (uint32_t bit){
+ if (bit & 1) {
+ MXC_SETBIT(&MXC_GPIO->out_val[TRGT_PORT], SWDIO_PIN);
+ } else {
+ MXC_CLRBIT(&MXC_GPIO->out_val[TRGT_PORT], SWDIO_PIN);
+ }
+}
+
+/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
+Configure the SWDIO DAP hardware I/O pin to output mode. This function is
+called prior \ref PIN_SWDIO_OUT function calls.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void) {
+ uint32_t out_mode;
+
+ out_mode = MXC_GPIO->out_mode[TRGT_PORT];
+ out_mode &= ~(0xF << (4 * SWDIO_PIN));
+ out_mode |= (MXC_E_GPIO_OUT_MODE_NORMAL << (4 * SWDIO_PIN));
+
+ MXC_GPIO->out_mode[TRGT_PORT] = out_mode;
+}
+
+/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
+Configure the SWDIO DAP hardware I/O pin to input mode. This function is
+called prior \ref PIN_SWDIO_IN function calls.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE (void) {
+ uint32_t out_mode;
+
+ out_mode = MXC_GPIO->out_mode[TRGT_PORT];
+ out_mode &= ~(0xF << (4 * SWDIO_PIN));
+
+ MXC_GPIO->out_mode[TRGT_PORT] = out_mode;
+}
+
+
+// TDI Pin I/O ---------------------------------------------
+
+/** TDI I/O pin: Get Input.
+\return Current status of the TDI DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_TDI_IN (void) {
+ return MXC_GETBIT(&MXC_GPIO->in_val[TRGT_PORT], TDI_PIN);
+}
+
+/** TDI I/O pin: Set Output.
+\param bit Output value for the TDI DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE void PIN_TDI_OUT (uint32_t bit) {
+ if (bit & 1) {
+ MXC_SETBIT(&MXC_GPIO->out_val[TRGT_PORT], TDI_PIN);
+ } else {
+ MXC_CLRBIT(&MXC_GPIO->out_val[TRGT_PORT], TDI_PIN);
+ }
+}
+
+
+// TDO Pin I/O ---------------------------------------------
+
+/** TDO I/O pin: Get Input.
+\return Current status of the TDO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_TDO_IN (void) {
+ return MXC_GETBIT(&MXC_GPIO->in_val[TRGT_PORT], TDO_PIN);
+}
+
+
+// nTRST Pin I/O -------------------------------------------
+
+/** nTRST I/O pin: Get Input.
+\return Current status of the nTRST DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN (void) {
+ return 0;
+}
+
+/** nTRST I/O pin: Set Output.
+\param bit JTAG TRST Test Reset pin status:
+ - 0: issue a JTAG TRST Test Reset.
+ - 1: release JTAG TRST Test Reset.
+*/
+__STATIC_FORCEINLINE void PIN_nTRST_OUT (uint32_t bit) {
+}
+
+// nRESET Pin I/O------------------------------------------
+
+/** nRESET I/O pin: Get Input.
+\return Current status of the nRESET DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN (void) {
+ return MXC_GETBIT(&MXC_GPIO->in_val[TRGT_PORT], SRST_PIN);
+}
+
+/** nRESET I/O pin: Set Output.
+\param bit target device hardware reset pin status:
+ - 0: issue a device hardware reset.
+ - 1: release device hardware reset.
+*/
+__STATIC_FORCEINLINE void PIN_nRESET_OUT (uint32_t bit) {
+ if (bit) {
+ MXC_SETBIT(&MXC_GPIO->out_val[TRGT_PORT], SRST_PIN);
+ } else {
+ MXC_CLRBIT(&MXC_GPIO->out_val[TRGT_PORT], SRST_PIN);
+ }
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
+\ingroup DAP_ConfigIO_gr
+@{
+
+CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
+
+It is recommended to provide the following LEDs for status indication:
+ - Connect LED: is active when the DAP hardware is connected to a debugger.
+ - Running LED: is active when the debugger has put the target device into running state.
+*/
+
+/** Debug Unit: Set status of Connected LED.
+\param bit status of the Connect LED.
+ - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
+ - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
+*/
+__STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) {
+}
+
+/** Debug Unit: Set status Target Running LED.
+\param bit status of the Target Running LED.
+ - 1: Target Running LED ON: program execution in target started.
+ - 0: Target Running LED OFF: program execution in target stopped.
+*/
+__STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
+\ingroup DAP_ConfigIO_gr
+@{
+Access function for Test Domain Timer.
+
+The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
+default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
+
+*/
+
+/** Get timestamp of Test Domain Timer.
+\return Current timestamp value.
+*/
+__STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
+ return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK);
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
+\ingroup DAP_ConfigIO_gr
+@{
+
+CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
+*/
+
+/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
+This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
+Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
+ - I/O clock system enabled.
+ - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
+ - for nTRST, nRESET a weak pull-up (if available) is enabled.
+ - LED output pins are enabled and LEDs are turned off.
+*/
+__STATIC_INLINE void DAP_SETUP (void) {
+ uint32_t out_mode;
+ out_mode = MXC_GPIO->out_mode[TRGT_PORT];
+ out_mode &= ~(0xF << (4 * SRST_PIN));
+ out_mode &= ~(0xF << (4 * RSTN_PIN));
+ out_mode &= ~(0xF << (4 * TDI_PIN));
+ out_mode &= ~(0xF << (4 * TCK_PIN));
+ out_mode &= ~(0xF << (4 * TMS_PIN));
+ out_mode &= ~(0xF << (4 * TDO_PIN));
+
+ out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * SRST_PIN));
+ out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * RSTN_PIN));
+ out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * TDI_PIN));
+ out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * TCK_PIN));
+ out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * TMS_PIN));
+ out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * TDO_PIN));
+
+ MXC_GPIO->out_mode[TRGT_PORT] = out_mode;
+}
+
+/** Reset Target Device with custom specific I/O pin or command sequence.
+This function allows the optional implementation of a device specific reset sequence.
+It is called when the command \ref DAP_ResetTarget and is for example required
+when a device needs a time-critical unlock sequence that enables the debug port.
+\return 0 = no device specific reset sequence is implemented.\n
+ 1 = a device specific reset sequence is implemented.
+*/
+__STATIC_INLINE uint32_t RESET_TARGET (void) {
+ return (0); // change to '1' when a device reset sequence is implemented
+}
+
+///@}
+
+
+#endif /* __DAP_CONFIG_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/FlashPrg.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32620/FlashPrg.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,208 @@
+/* CMSIS-DAP Interface Firmware
+ * Copyright (c) 2009-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "FlashOS.h"
+#include "max32620.h"
+#include "flc_regs.h"
+
+/******************************************************************************/
+static inline int FLC_Busy(void)
+{
+ return (MXC_FLC->ctrl & (MXC_F_FLC_CTRL_WRITE | MXC_F_FLC_CTRL_MASS_ERASE | MXC_F_FLC_CTRL_PAGE_ERASE));
+}
+
+/******************************************************************************/
+uint32_t Init(uint32_t adr, uint32_t clk, uint32_t fnc)
+{
+ /* Check if the flash controller is busy */
+ if (FLC_Busy()) {
+ return 1;
+ }
+
+ /* Enable automatic calculation of the clock divider to generate a 1MHz clock from the APB clock */
+ MXC_FLC->perform |= MXC_F_FLC_PERFORM_AUTO_CLKDIV;
+
+ /* The flash controller will stall any reads while flash operations are in
+ * progress. Disable the legacy failure detection logic that would flag reads
+ * during flash operations as errors.
+ */
+ MXC_FLC->perform |= MXC_F_FLC_PERFORM_EN_PREVENT_FAIL;
+
+ return 0;
+}
+
+/******************************************************************************/
+uint32_t UnInit(uint32_t fnc)
+{
+ /* Lock flash */
+ MXC_FLC->ctrl &= ~MXC_F_FLC_CTRL_FLSH_UNLOCK;
+
+ return 0; // Finished without Errors
+}
+
+/******************************************************************************/
+/*
+ * Erase complete Flash Memory
+ * Return Value: 0 - OK, 1 - Failed
+ */
+int EraseChip(void)
+{
+ /* Check if the flash controller is busy */
+ if (FLC_Busy()) {
+ return 1;
+ }
+
+ /* Clear stale errors. Interrupt flags can only be written to zero, so this is safe */
+ MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
+
+ /* Unlock flash */
+ MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_FLSH_UNLOCK) | (MXC_V_FLC_FLSH_UNLOCK_KEY << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS);
+
+ /* Write the Erase Code */
+ MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_ERASE_CODE) | (MXC_V_FLC_ERASE_CODE_MASS_ERASE << MXC_F_FLC_CTRL_ERASE_CODE_POS);
+
+ /* Start the mass erase */
+ MXC_FLC->ctrl |= MXC_F_FLC_CTRL_MASS_ERASE;
+
+ /* Wait until flash operation is complete */
+ while (FLC_Busy());
+
+ /* Lock flash */
+ MXC_FLC->ctrl &= ~(MXC_F_FLC_CTRL_FLSH_UNLOCK | MXC_F_FLC_CTRL_ERASE_CODE);
+
+ /* Check for failures */
+ if (MXC_FLC->intr & MXC_F_FLC_INTR_FAILED_IF) {
+ /* Interrupt flags can only be written to zero, so this is safe */
+ MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
+ return 1;
+ }
+
+ return 0;
+}
+
+/******************************************************************************/
+/*
+ * Erase Sector in Flash Memory
+ * Parameter: address: Sector Address
+ * Return Value: 0 - OK, 1 - Failed
+ */
+int EraseSector(unsigned long address)
+{
+ /* Wait until flash operation is complete */
+ while (FLC_Busy());
+
+ /* Clear stale errors. Interrupt flags can only be written to zero, so this is safe */
+ MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
+
+ /* Unlock flash */
+ MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_FLSH_UNLOCK) | (MXC_V_FLC_FLSH_UNLOCK_KEY << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS);
+
+ /* Write page erase code */
+ MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_ERASE_CODE) | (MXC_V_FLC_ERASE_CODE_PAGE_ERASE << MXC_F_FLC_CTRL_ERASE_CODE_POS);
+
+ /* Erase the request page */
+ MXC_FLC->faddr = address;
+ MXC_FLC->ctrl |= MXC_F_FLC_CTRL_PAGE_ERASE;
+
+ /* Wait until flash operation is complete */
+ while (FLC_Busy());
+
+ /* Lock flash */
+ MXC_FLC->ctrl &= ~(MXC_F_FLC_CTRL_FLSH_UNLOCK | MXC_F_FLC_CTRL_ERASE_CODE);
+
+ /* Check for failures */
+ if (MXC_FLC->intr & MXC_F_FLC_INTR_FAILED_IF) {
+ /* Interrupt flags can only be written to zero, so this is safe */
+ MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
+ return 1;
+ }
+
+ return 0;
+}
+
+/******************************************************************************/
+/*
+ * Program Page in Flash Memory
+ * Parameter: address: Page Start Address
+ * size: Page Size
+ * buffer: Page Data
+ * Return Value: 0 - OK, 1 - Failed
+ */
+int ProgramPage(unsigned long address, unsigned long size, unsigned char *buffer8)
+{
+ unsigned long remaining = size;
+ unsigned long *buffer = (unsigned long *)buffer8;
+
+ // Only accept 32-bit aligned pointers
+ if ((unsigned long)buffer8 & 0x3) {
+ return 1;
+ }
+ buffer = (unsigned long *)buffer8;
+
+ /* Check if the flash controller is busy */
+ if (FLC_Busy()) {
+ return 1;
+ }
+
+ /* Unlock flash */
+ MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_FLSH_UNLOCK) | (MXC_V_FLC_FLSH_UNLOCK_KEY << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS);
+
+ while (remaining >= 4) {
+ MXC_FLC->faddr = address;
+ MXC_FLC->fdata = *buffer++;
+ MXC_FLC->ctrl |= MXC_F_FLC_CTRL_WRITE_ENABLE;
+ MXC_FLC->ctrl |= MXC_F_FLC_CTRL_WRITE;
+
+ /* Wait until flash operation is complete */
+ while (FLC_Busy());
+
+ address += 4;
+ remaining -= 4;
+ }
+
+ if (remaining > 0) {
+ uint32_t last_word;
+ uint32_t mask;
+
+ last_word = 0xffffffff;
+ mask = 0xff;
+
+ while (remaining > 0) {
+ last_word &= (*buffer | ~mask);
+ mask <<= 8;
+ remaining--;
+ }
+
+ MXC_FLC->faddr = address;
+ MXC_FLC->fdata = last_word;
+ MXC_FLC->ctrl |= MXC_F_FLC_CTRL_WRITE_ENABLE;
+
+ /* Wait until flash operation is complete */
+ while (FLC_Busy());
+ }
+
+ /* Lock flash */
+ MXC_FLC->ctrl &= ~MXC_F_FLC_CTRL_FLSH_UNLOCK;
+
+ /* Check for failures */
+ if (MXC_FLC->intr & MXC_F_FLC_INTR_FAILED_IF) {
+ /* Interrupt flags can only be written to zero, so this is safe */
+ MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
+ return 1;
+ }
+
+ return 0;
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/IO_Config.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/maxim/max32620/IO_Config.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,62 @@ +/** + * @file IO_Config.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "max32620.h" + +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ + +// DAP LED +#define PIN_DAP_LED_PORT 4 +#define PIN_DAP_LED_PIN 2 + +// MSD LED +#define PIN_MSD_LED_PORT 4 +#define PIN_MSD_LED_PIN 0 + +// CDC LED +#define PIN_CDC_LED_PORT 4 +#define PIN_CDC_LED_PIN 1 + +// Non-Forwarded Reset In Pin +#define PIN_RESET_IN_NO_FWRD_PORT 5 +#define PIN_RESET_IN_NO_FWRD_PIN 0 + +#define TRGT_PORT 1 +#define SRST_PIN 0 +#define RSTN_PIN 1 +#define TDI_PIN 2 +#define TCK_PIN 3 +#define TMS_PIN 4 +#define TDO_PIN 5 +#define VDDIO_PIN 6 + +#define BUFFEN_PORT 6 +#define BUFFEN_PIN 0 + +#define SWCLK_PIN TCK_PIN +#define SWDIO_PIN TMS_PIN + +#define MXC_E_GPIO_OUT_MODE_TRISTATE 0 +#define MXC_E_GPIO_OUT_MODE_OPEN_DRAIN_W_PULLUP 2 +#define MXC_E_GPIO_OUT_MODE_NORMAL 5 + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/adc_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32620/adc_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,273 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_ADC_REGS_H_
+#define _MXC_ADC_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __IO uint32_t ctrl; /* 0x0000 ADC Control */
+ __IO uint32_t status; /* 0x0004 ADC Status */
+ __IO uint32_t data; /* 0x0008 ADC Output Data */
+ __IO uint32_t intr; /* 0x000C ADC Interrupt Control Register */
+ __IO uint32_t limit[4]; /* 0x0010-0x001C ADC Limit 0..3 */
+ __IO uint32_t afe_ctrl; /* 0x0020 AFE Control Register */
+ __IO uint32_t ro_cal0; /* 0x0024 RO Trim Calibration Register 0 */
+ __IO uint32_t ro_cal1; /* 0x0028 RO Trim Calibration Register 1 */
+ __IO uint32_t ro_cal2; /* 0x002C RO Trim Calibration Register 2 */
+} mxc_adc_regs_t;
+
+
+/*
+ Register offsets for module ADC.
+*/
+
+#define MXC_R_ADC_OFFS_CTRL ((uint32_t)0x00000000UL)
+#define MXC_R_ADC_OFFS_STATUS ((uint32_t)0x00000004UL)
+#define MXC_R_ADC_OFFS_DATA ((uint32_t)0x00000008UL)
+#define MXC_R_ADC_OFFS_INTR ((uint32_t)0x0000000CUL)
+#define MXC_R_ADC_OFFS_LIMIT0 ((uint32_t)0x00000010UL)
+#define MXC_R_ADC_OFFS_LIMIT1 ((uint32_t)0x00000014UL)
+#define MXC_R_ADC_OFFS_LIMIT2 ((uint32_t)0x00000018UL)
+#define MXC_R_ADC_OFFS_LIMIT3 ((uint32_t)0x0000001CUL)
+#define MXC_R_ADC_OFFS_AFE_CTRL ((uint32_t)0x00000020UL)
+#define MXC_R_ADC_OFFS_RO_CAL0 ((uint32_t)0x00000024UL)
+#define MXC_R_ADC_OFFS_RO_CAL1 ((uint32_t)0x00000028UL)
+#define MXC_R_ADC_OFFS_RO_CAL2 ((uint32_t)0x0000002CUL)
+
+
+/*
+ Field positions and masks for module ADC.
+*/
+
+#define MXC_F_ADC_CTRL_CPU_ADC_START_POS 0
+#define MXC_F_ADC_CTRL_CPU_ADC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_CPU_ADC_START_POS))
+#define MXC_F_ADC_CTRL_ADC_PU_POS 1
+#define MXC_F_ADC_CTRL_ADC_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_PU_POS))
+#define MXC_F_ADC_CTRL_BUF_PU_POS 2
+#define MXC_F_ADC_CTRL_BUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PU_POS))
+#define MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS 3
+#define MXC_F_ADC_CTRL_ADC_REFBUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS))
+#define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS 4
+#define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS))
+#define MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS 5
+#define MXC_F_ADC_CTRL_BUF_CHOP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS))
+#define MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS 6
+#define MXC_F_ADC_CTRL_BUF_PUMP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS))
+#define MXC_F_ADC_CTRL_BUF_BYPASS_POS 7
+#define MXC_F_ADC_CTRL_BUF_BYPASS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_BYPASS_POS))
+#define MXC_F_ADC_CTRL_ADC_REFSCL_POS 8
+#define MXC_F_ADC_CTRL_ADC_REFSCL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSCL_POS))
+#define MXC_F_ADC_CTRL_ADC_SCALE_POS 9
+#define MXC_F_ADC_CTRL_ADC_SCALE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_SCALE_POS))
+#define MXC_F_ADC_CTRL_ADC_REFSEL_POS 10
+#define MXC_F_ADC_CTRL_ADC_REFSEL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSEL_POS))
+#define MXC_F_ADC_CTRL_ADC_CLK_EN_POS 11
+#define MXC_F_ADC_CTRL_ADC_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CLK_EN_POS))
+#define MXC_F_ADC_CTRL_ADC_CHSEL_POS 12
+#define MXC_F_ADC_CTRL_ADC_CHSEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL_ADC_CHSEL_POS))
+
+#if (MXC_ADC_REV == 0)
+#define MXC_F_ADC_CTRL_ADC_XREF_POS 16
+#define MXC_F_ADC_CTRL_ADC_XREF ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_XREF_POS))
+#endif
+
+#define MXC_F_ADC_CTRL_ADC_DATAALIGN_POS 17
+#define MXC_F_ADC_CTRL_ADC_DATAALIGN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_DATAALIGN_POS))
+#define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS 24
+#define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY ((uint32_t)(0x000000FFUL << MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS))
+
+#define MXC_F_ADC_STATUS_ADC_ACTIVE_POS 0
+#define MXC_F_ADC_STATUS_ADC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_ACTIVE_POS))
+#define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS 1
+#define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS))
+#define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS 2
+#define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS))
+#define MXC_F_ADC_STATUS_ADC_OVERFLOW_POS 3
+#define MXC_F_ADC_STATUS_ADC_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_OVERFLOW_POS))
+
+#define MXC_F_ADC_DATA_ADC_DATA_POS 0
+#define MXC_F_ADC_DATA_ADC_DATA ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_DATA_ADC_DATA_POS))
+
+#define MXC_F_ADC_INTR_ADC_DONE_IE_POS 0
+#define MXC_F_ADC_INTR_ADC_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IE_POS))
+#define MXC_F_ADC_INTR_ADC_REF_READY_IE_POS 1
+#define MXC_F_ADC_INTR_ADC_REF_READY_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IE_POS))
+#define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS 2
+#define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS))
+#define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS 3
+#define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS))
+#define MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS 4
+#define MXC_F_ADC_INTR_ADC_OVERFLOW_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS))
+#define MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS 5
+#define MXC_F_ADC_INTR_RO_CAL_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS))
+#define MXC_F_ADC_INTR_ADC_DONE_IF_POS 16
+#define MXC_F_ADC_INTR_ADC_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IF_POS))
+#define MXC_F_ADC_INTR_ADC_REF_READY_IF_POS 17
+#define MXC_F_ADC_INTR_ADC_REF_READY_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IF_POS))
+#define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS 18
+#define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS))
+#define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS 19
+#define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS))
+#define MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS 20
+#define MXC_F_ADC_INTR_ADC_OVERFLOW_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS))
+#define MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS 21
+#define MXC_F_ADC_INTR_RO_CAL_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS))
+#define MXC_F_ADC_INTR_ADC_INT_PENDING_POS 22
+#define MXC_F_ADC_INTR_ADC_INT_PENDING ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_INT_PENDING_POS))
+
+#define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS 0
+#define MXC_F_ADC_LIMIT0_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS))
+#define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS 12
+#define MXC_F_ADC_LIMIT0_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS))
+#define MXC_F_ADC_LIMIT0_CH_SEL_POS 24
+#define MXC_F_ADC_LIMIT0_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT0_CH_SEL_POS))
+#define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS 28
+#define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS))
+#define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS 29
+#define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS))
+
+#define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS 0
+#define MXC_F_ADC_LIMIT1_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS))
+#define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS 12
+#define MXC_F_ADC_LIMIT1_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS))
+#define MXC_F_ADC_LIMIT1_CH_SEL_POS 24
+#define MXC_F_ADC_LIMIT1_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT1_CH_SEL_POS))
+#define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS 28
+#define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS))
+#define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS 29
+#define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS))
+
+#define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS 0
+#define MXC_F_ADC_LIMIT2_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS))
+#define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS 12
+#define MXC_F_ADC_LIMIT2_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS))
+#define MXC_F_ADC_LIMIT2_CH_SEL_POS 24
+#define MXC_F_ADC_LIMIT2_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT2_CH_SEL_POS))
+#define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS 28
+#define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS))
+#define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS 29
+#define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS))
+
+#define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS 0
+#define MXC_F_ADC_LIMIT3_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS))
+#define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS 12
+#define MXC_F_ADC_LIMIT3_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS))
+#define MXC_F_ADC_LIMIT3_CH_SEL_POS 24
+#define MXC_F_ADC_LIMIT3_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT3_CH_SEL_POS))
+#define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS 28
+#define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS))
+#define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS 29
+#define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS))
+
+#define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS 8
+#define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS))
+#define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS 9
+#define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS))
+
+#define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS 0
+#define MXC_F_ADC_RO_CAL0_RO_CAL_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS))
+#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS 1
+#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS))
+#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS 2
+#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS))
+#define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS 4
+#define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS))
+#define MXC_F_ADC_RO_CAL0_DUMMY_POS 5
+#define MXC_F_ADC_RO_CAL0_DUMMY ((uint32_t)(0x00000007UL << MXC_F_ADC_RO_CAL0_DUMMY_POS))
+#define MXC_F_ADC_RO_CAL0_TRM_MU_POS 8
+#define MXC_F_ADC_RO_CAL0_TRM_MU ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS))
+#define MXC_F_ADC_RO_CAL0_RO_TRM_POS 23
+#define MXC_F_ADC_RO_CAL0_RO_TRM ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS))
+
+#define MXC_F_ADC_RO_CAL1_TRM_INIT_POS 0
+#define MXC_F_ADC_RO_CAL1_TRM_INIT ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS))
+#define MXC_F_ADC_RO_CAL1_TRM_MIN_POS 10
+#define MXC_F_ADC_RO_CAL1_TRM_MIN ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS))
+#define MXC_F_ADC_RO_CAL1_TRM_MAX_POS 20
+#define MXC_F_ADC_RO_CAL1_TRM_MAX ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS))
+
+#define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS 0
+#define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT ((uint32_t)(0x000000FFUL << MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS))
+
+#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN0 ((uint32_t)(0x00000000UL))
+#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN1 ((uint32_t)(0x00000001UL))
+#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN2 ((uint32_t)(0x00000002UL))
+#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN3 ((uint32_t)(0x00000003UL))
+#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN0_DIV_5 ((uint32_t)(0x00000004UL))
+#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN1_DIV_5 ((uint32_t)(0x00000005UL))
+#define MXC_V_ADC_CTRL_ADC_CHSEL_VDDB_DIV_4 ((uint32_t)(0x00000006UL))
+#define MXC_V_ADC_CTRL_ADC_CHSEL_VDD18 ((uint32_t)(0x00000007UL))
+#define MXC_V_ADC_CTRL_ADC_CHSEL_VDD12 ((uint32_t)(0x00000008UL))
+#define MXC_V_ADC_CTRL_ADC_CHSEL_VRTC_DIV_2 ((uint32_t)(0x00000009UL))
+#define MXC_V_ADC_CTRL_ADC_CHSEL_TMON ((uint32_t)(0x0000000AUL))
+
+#if(MXC_ADC_REV > 0)
+#define MXC_V_ADC_CTRL_ADC_CHSEL_VDDIO_DIV_4 ((uint32_t)(0x0000000BUL))
+#define MXC_V_ADC_CTRL_ADC_CHSEL_VDDIOH_DIV_4 ((uint32_t)(0x0000000CUL))
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_ADC_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/armcc/startup_MAX32620.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/maxim/max32620/armcc/startup_MAX32620.S Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,328 @@ +;******************************************************************************* +; Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. +; +; Permission is hereby granted, free of charge, to any person obtaining a +; copy of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice shall be included +; in all copies or substantial portions of the Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES +; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +; OTHER DEALINGS IN THE SOFTWARE. +; +; Except as contained in this notice, the name of Maxim Integrated +; Products, Inc. shall not be used except as stated in the Maxim Integrated +; Products, Inc. Branding Policy. +; +; The mere transfer of this software does not imply any licenses +; of trade secrets, proprietary technology, copyrights, patents, +; trademarks, maskwork rights, or any other form of intellectual +; property whatsoever. Maxim Integrated Products, Inc. retains all +; ownership rights. +;******************************************************************************* + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __initial_sp + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT g_board_info +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD DAPLINK_BUILD_KEY ; Reserved + DCD DAPLINK_HIC_ID ; Reserved + DCD DAPLINK_VERSION ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD g_board_info ; Ptr to Board info, family info other target details + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Maxim 32620 Externals interrupts + DCD CLKMAN_IRQHandler /* 16:01 CLKMAN */ + DCD PWRMAN_IRQHandler /* 17:02 PWRMAN */ + DCD FLC_IRQHandler /* 18:03 Flash Controller */ + DCD RTC0_IRQHandler /* 19:04 RTC INT0 */ + DCD RTC1_IRQHandler /* 20:05 RTC INT1 */ + DCD RTC2_IRQHandler /* 21:06 RTC INT2 */ + DCD RTC3_IRQHandler /* 22:07 RTC INT3 */ + DCD PMU_IRQHandler /* 23:08 PMU */ + DCD USB_IRQHandler /* 24:09 USB */ + DCD AES_IRQHandler /* 25:10 AES */ + DCD MAA_IRQHandler /* 26:11 MAA */ + DCD WDT0_IRQHandler /* 27:12 WATCHDOG0 */ + DCD WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */ + DCD WDT1_IRQHandler /* 29:14 WATCHDOG1 */ + DCD WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */ + DCD GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */ + DCD GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */ + DCD GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */ + DCD GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */ + DCD GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */ + DCD GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */ + DCD GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */ + DCD TMR0_IRQHandler /* 38:23 Timer32-0 */ + DCD TMR16_0_IRQHandler /* 39:24 Timer16-s0 */ + DCD TMR1_IRQHandler /* 40:25 Timer32-1 */ + DCD TMR16_1_IRQHandler /* 41:26 Timer16-s1 */ + DCD TMR2_IRQHandler /* 42:27 Timer32-2 */ + DCD TMR16_2_IRQHandler /* 43:28 Timer16-s2 */ + DCD TMR3_IRQHandler /* 44:29 Timer32-3 */ + DCD TMR16_3_IRQHandler /* 45:30 Timer16-s3 */ + DCD TMR4_IRQHandler /* 46:31 Timer32-4 */ + DCD TMR16_4_IRQHandler /* 47:32 Timer16-s4 */ + DCD TMR5_IRQHandler /* 48:33 Timer32-5 */ + DCD TMR16_5_IRQHandler /* 49:34 Timer16-s5 */ + DCD UART0_IRQHandler /* 50:35 UART0 */ + DCD UART1_IRQHandler /* 51:36 UART1 */ + DCD UART2_IRQHandler /* 52:37 UART0 */ + DCD UART3_IRQHandler /* 53:38 UART1 */ + DCD PT_IRQHandler /* 54:39 PT */ + DCD I2CM0_IRQHandler /* 55:40 I2C Master 0 */ + DCD I2CM1_IRQHandler /* 56:41 I2C Master 1 */ + DCD I2CM2_IRQHandler /* 57:42 I2C Master 2 */ + DCD I2CS_IRQHandler /* 58:43 I2C Slave */ + DCD SPI0_IRQHandler /* 59:44 SPI0 */ + DCD SPI1_IRQHandler /* 60:45 SPI1 */ + DCD SPI2_IRQHandler /* 61:46 SPI2 */ + DCD SPIB_IRQHandler /* 62:47 SPI Bridge */ + DCD OWM_IRQHandler /* 63:48 1-Wire Master */ + DCD AFE_IRQHandler /* 64:49 AFE */ + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT PreInit + IMPORT SystemInit + IMPORT __main + LDR R0, =PreInit + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +DefaultIRQ_Handler PROC + EXPORT CLKMAN_IRQHandler [WEAK] + EXPORT PWRMAN_IRQHandler [WEAK] + EXPORT FLC_IRQHandler [WEAK] + EXPORT RTC0_IRQHandler [WEAK] + EXPORT RTC1_IRQHandler [WEAK] + EXPORT RTC2_IRQHandler [WEAK] + EXPORT RTC3_IRQHandler [WEAK] + EXPORT PMU_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT MAA_IRQHandler [WEAK] + EXPORT WDT0_IRQHandler [WEAK] + EXPORT WDT0_P_IRQHandler [WEAK] + EXPORT WDT1_IRQHandler [WEAK] + EXPORT WDT1_P_IRQHandler [WEAK] + EXPORT GPIO_P0_IRQHandler [WEAK] + EXPORT GPIO_P1_IRQHandler [WEAK] + EXPORT GPIO_P2_IRQHandler [WEAK] + EXPORT GPIO_P3_IRQHandler [WEAK] + EXPORT GPIO_P4_IRQHandler [WEAK] + EXPORT GPIO_P5_IRQHandler [WEAK] + EXPORT GPIO_P6_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR16_0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR16_1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR16_2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT TMR16_3_IRQHandler [WEAK] + EXPORT TMR4_IRQHandler [WEAK] + EXPORT TMR16_4_IRQHandler [WEAK] + EXPORT TMR5_IRQHandler [WEAK] + EXPORT TMR16_5_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT PT_IRQHandler [WEAK] + EXPORT I2CM0_IRQHandler [WEAK] + EXPORT I2CM1_IRQHandler [WEAK] + EXPORT I2CM2_IRQHandler [WEAK] + EXPORT I2CS_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPIB_IRQHandler [WEAK] + EXPORT OWM_IRQHandler [WEAK] + EXPORT AFE_IRQHandler [WEAK] + +CLKMAN_IRQHandler +PWRMAN_IRQHandler +FLC_IRQHandler +RTC0_IRQHandler +RTC1_IRQHandler +RTC2_IRQHandler +RTC3_IRQHandler +PMU_IRQHandler +USB_IRQHandler +AES_IRQHandler +MAA_IRQHandler +WDT0_IRQHandler +WDT0_P_IRQHandler +WDT1_IRQHandler +WDT1_P_IRQHandler +GPIO_P0_IRQHandler +GPIO_P1_IRQHandler +GPIO_P2_IRQHandler +GPIO_P3_IRQHandler +GPIO_P4_IRQHandler +GPIO_P5_IRQHandler +GPIO_P6_IRQHandler +TMR0_IRQHandler +TMR16_0_IRQHandler +TMR1_IRQHandler +TMR16_1_IRQHandler +TMR2_IRQHandler +TMR16_2_IRQHandler +TMR3_IRQHandler +TMR16_3_IRQHandler +TMR4_IRQHandler +TMR16_4_IRQHandler +TMR5_IRQHandler +TMR16_5_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +PT_IRQHandler +I2CM0_IRQHandler +I2CM1_IRQHandler +I2CM2_IRQHandler +I2CS_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +SPIB_IRQHandler +OWM_IRQHandler +AFE_IRQHandler + + B . + ENDP + ALIGN + + ; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + END
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/clkman_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32620/clkman_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,448 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_CLKMAN_REGS_H_
+#define _MXC_CLKMAN_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __IO uint32_t clk_config; /* 0x0000 System Clock Configuration */
+ __IO uint32_t clk_ctrl; /* 0x0004 System Clock Controls */
+ __IO uint32_t intfl; /* 0x0008 Interrupt Flags */
+ __IO uint32_t inten; /* 0x000C Interrupt Enable/Disable Controls */
+ __IO uint32_t trim_calc; /* 0x0010 Trim Calculation Controls */
+ __IO uint32_t i2c_timer_ctrl; /* 0x0014 I2C Timer Control */
+ __IO uint32_t cm4_start_clk_en0; /* 0x0018 CM4 Start Clock on Interrupt Enable 0 */
+ __IO uint32_t cm4_start_clk_en1; /* 0x001C CM4 Start Clock on Interrupt Enable 1 */
+ __IO uint32_t cm4_start_clk_en2; /* 0x0020 CM4 Start Clock on Interrupt Enable 2 */
+ __R uint32_t rsv024[7]; /* 0x0024-0x003C */
+ __IO uint32_t sys_clk_ctrl_0_cm4; /* 0x0040 Control Settings for CLK0 - Cortex M4 Clock */
+ __IO uint32_t sys_clk_ctrl_1_sync; /* 0x0044 Control Settings for CLK1 - Synchronizer Clock */
+ __IO uint32_t sys_clk_ctrl_2_spix; /* 0x0048 Control Settings for CLK2 - SPI XIP Clock */
+ __IO uint32_t sys_clk_ctrl_3_prng; /* 0x004C Control Settings for CLK3 - PRNG Clock */
+ __IO uint32_t sys_clk_ctrl_4_wdt0; /* 0x0050 Control Settings for CLK4 - Watchdog Timer 0 */
+ __IO uint32_t sys_clk_ctrl_5_wdt1; /* 0x0054 Control Settings for CLK5 - Watchdog Timer 1 */
+ __IO uint32_t sys_clk_ctrl_6_gpio; /* 0x0058 Control Settings for CLK6 - Clock for GPIO Ports */
+ __IO uint32_t sys_clk_ctrl_7_pt; /* 0x005C Control Settings for CLK7 - Source Clock for All Pulse Trains */
+ __IO uint32_t sys_clk_ctrl_8_uart; /* 0x0060 Control Settings for CLK8 - Source Clock for All UARTs */
+ __IO uint32_t sys_clk_ctrl_9_i2cm; /* 0x0064 Control Settings for CLK9 - Source Clock for All I2C Masters */
+ __IO uint32_t sys_clk_ctrl_10_i2cs; /* 0x0068 Control Settings for CLK10 - Source Clock for I2C Slave */
+ __IO uint32_t sys_clk_ctrl_11_spi0; /* 0x006C Control Settings for CLK11 - SPI Master 0 */
+ __IO uint32_t sys_clk_ctrl_12_spi1; /* 0x0070 Control Settings for CLK12 - SPI Master 1 */
+ __IO uint32_t sys_clk_ctrl_13_spi2; /* 0x0074 Control Settings for CLK13 - SPI Master 2 */
+ __IO uint32_t sys_clk_ctrl_14_spib; /* 0x0078 Control Settings for CLK14 - SPI Bridge Clock */
+ __IO uint32_t sys_clk_ctrl_15_owm; /* 0x007C Control Settings for CLK15 - 1-Wire Master Clock */
+ __IO uint32_t sys_clk_ctrl_16_spis; /* 0x0080 Control Settings for CLK16 - SPI Slave Clock */
+ __R uint32_t rsv084[31]; /* 0x0084-0x00FC */
+ __IO uint32_t crypt_clk_ctrl_0_aes; /* 0x0100 Control Settings for Crypto Clock 0 - AES */
+ __IO uint32_t crypt_clk_ctrl_1_maa; /* 0x0104 Control Settings for Crypto Clock 1 - MAA */
+ __IO uint32_t crypt_clk_ctrl_2_prng; /* 0x0108 Control Settings for Crypto Clock 2 - PRNG */
+ __R uint32_t rsv10C[13]; /* 0x010C-0x013C */
+ __IO uint32_t clk_gate_ctrl0; /* 0x0140 Dynamic Clock Gating Control Register 0 */
+ __IO uint32_t clk_gate_ctrl1; /* 0x0144 Dynamic Clock Gating Control Register 1 */
+ __IO uint32_t clk_gate_ctrl2; /* 0x0148 Dynamic Clock Gating Control Register 2 */
+} mxc_clkman_regs_t;
+
+
+/*
+ Register offsets for module CLKMAN.
+*/
+
+#define MXC_R_CLKMAN_OFFS_CLK_CONFIG ((uint32_t)0x00000000UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL ((uint32_t)0x00000004UL)
+#define MXC_R_CLKMAN_OFFS_INTFL ((uint32_t)0x00000008UL)
+#define MXC_R_CLKMAN_OFFS_INTEN ((uint32_t)0x0000000CUL)
+#define MXC_R_CLKMAN_OFFS_TRIM_CALC ((uint32_t)0x00000010UL)
+#define MXC_R_CLKMAN_OFFS_I2C_TIMER_CTRL ((uint32_t)0x00000014UL)
+#define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN0 ((uint32_t)0x00000018UL)
+#define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN1 ((uint32_t)0x0000001CUL)
+#define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN2 ((uint32_t)0x00000020UL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_0_CM4 ((uint32_t)0x00000040UL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_1_SYNC ((uint32_t)0x00000044UL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_2_SPIX ((uint32_t)0x00000048UL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_3_PRNG ((uint32_t)0x0000004CUL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_4_WDT0 ((uint32_t)0x00000050UL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_5_WDT1 ((uint32_t)0x00000054UL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_6_GPIO ((uint32_t)0x00000058UL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_7_PT ((uint32_t)0x0000005CUL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_8_UART ((uint32_t)0x00000060UL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_9_I2CM ((uint32_t)0x00000064UL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_10_I2CS ((uint32_t)0x00000068UL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_11_SPI0 ((uint32_t)0x0000006CUL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_12_SPI1 ((uint32_t)0x00000070UL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_13_SPI2 ((uint32_t)0x00000074UL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_14_SPIB ((uint32_t)0x00000078UL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_15_OWM ((uint32_t)0x0000007CUL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_16_SPIS ((uint32_t)0x00000080UL)
+#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_0_AES ((uint32_t)0x00000100UL)
+#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_1_MAA ((uint32_t)0x00000104UL)
+#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_2_PRNG ((uint32_t)0x00000108UL)
+#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL0 ((uint32_t)0x00000140UL)
+#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL1 ((uint32_t)0x00000144UL)
+#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL2 ((uint32_t)0x00000148UL)
+
+
+/*
+ Field positions and masks for module CLKMAN.
+*/
+
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS 0
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS 4
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE_POS 4
+#define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT_POS 5
+#define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE_POS 8
+#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS 12
+#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK_POS 13
+#define MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE_POS 16
+#define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS 17
+#define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE_POS 20
+#define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS 21
+#define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE_POS 24
+#define MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE_POS))
+
+#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS 0
+#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS))
+#define MXC_F_CLKMAN_INTFL_SYS_RO_STABLE_POS 1
+#define MXC_F_CLKMAN_INTFL_SYS_RO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_SYS_RO_STABLE_POS))
+
+#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS 0
+#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS))
+#define MXC_F_CLKMAN_INTEN_SYS_RO_STABLE_POS 1
+#define MXC_F_CLKMAN_INTEN_SYS_RO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_SYS_RO_STABLE_POS))
+
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS 0
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS 1
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS 2
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS 3
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_LENGTH_POS 4
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_LENGTH ((uint32_t)(0x00000FFFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_LENGTH_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS 16
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS ((uint32_t)(0x00003FFFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS))
+
+#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS 0
+#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS))
+
+#define MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS_POS 0
+#define MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS_POS))
+
+#define MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS_POS 0
+#define MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS_POS))
+
+#define MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS_POS 0
+#define MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER_POS 0
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER_POS 2
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS 4
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS 6
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS 8
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS 10
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS 12
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER_POS 14
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER_POS 16
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER_POS 18
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER_POS 20
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER_POS 22
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS 24
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER_POS 26
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER_POS 28
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS 30
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS))
+
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER_POS 0
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS 2
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER_POS 4
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER_POS 6
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER_POS 8
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER_POS 10
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER_POS 12
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER_POS 14
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS 16
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER_POS 18
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER_POS 20
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER_POS 22
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER_POS 24
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS 26
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS 28
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER_POS 30
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER_POS))
+
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER_POS 0
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER_POS 2
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER_POS 4
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER_POS 6
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER_POS 8
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER_POS 10
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER_POS 12
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER_POS 14
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER_POS))
+
+
+
+/*
+ Field values and shifted values for module CLKMAN.
+*/
+
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS ((uint32_t)(0x00000000UL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS ((uint32_t)(0x00000001UL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS ((uint32_t)(0x00000002UL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS ((uint32_t)(0x00000003UL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS ((uint32_t)(0x00000004UL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS ((uint32_t)(0x00000005UL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS ((uint32_t)(0x00000006UL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS ((uint32_t)(0x00000007UL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS ((uint32_t)(0x00000008UL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS ((uint32_t)(0x00000009UL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS ((uint32_t)(0x0000000AUL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS ((uint32_t)(0x0000000BUL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS ((uint32_t)(0x0000000CUL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS ((uint32_t)(0x0000000DUL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS ((uint32_t)(0x0000000EUL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS ((uint32_t)(0x0000000FUL))
+
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+
+#define MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 ((uint32_t)(0x00000000UL))
+#define MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO ((uint32_t)(0x00000001UL))
+
+#define MXC_S_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 ((uint32_t)(MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS))
+#define MXC_S_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO ((uint32_t)(MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS))
+
+#define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 ((uint32_t)(0x00000000UL))
+#define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(0x00000001UL))
+#define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(0x00000002UL))
+#define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(0x00000003UL))
+
+#define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
+#define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
+#define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
+#define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
+
+#define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 ((uint32_t)(0x00000000UL))
+#define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(0x00000001UL))
+#define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(0x00000002UL))
+#define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(0x00000003UL))
+
+#define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
+#define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
+#define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
+#define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
+
+#define MXC_V_CLKMAN_CLK_SCALE_DISABLED ((uint32_t)(0x00000000UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_1 ((uint32_t)(0x00000001UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_2 ((uint32_t)(0x00000002UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_4 ((uint32_t)(0x00000003UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_8 ((uint32_t)(0x00000004UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_16 ((uint32_t)(0x00000005UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_32 ((uint32_t)(0x00000006UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_64 ((uint32_t)(0x00000007UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_128 ((uint32_t)(0x00000008UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_256 ((uint32_t)(0x00000009UL))
+
+#define MXC_S_CLKMAN_CLK_SCALE_DISABLED ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DISABLED << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_1 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_1 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_2 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_2 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_4 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_4 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_8 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_8 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_16 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_16 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_32 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_32 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_64 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_64 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_128 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_128 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_256 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_256 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_CLKMAN_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/daplink_addr.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/maxim/max32620/daplink_addr.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,82 @@ +/** + * @file daplink_addr.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef DAPLINK_ADDR_H +#define DAPLINK_ADDR_H + +/* Device sizes */ + +#define DAPLINK_ROM_START 0x00000000 +#define DAPLINK_ROM_SIZE 0x00080000 + +#define DAPLINK_RAM_START 0x20000000 +#define DAPLINK_RAM_SIZE 0x00040000 + +/* ROM sizes */ + +#define DAPLINK_ROM_BL_START 0x00000000 +#define DAPLINK_ROM_BL_SIZE 0x0000E000 + +#define DAPLINK_ROM_CONFIG_ADMIN_START 0x0000E000 +#define DAPLINK_ROM_CONFIG_ADMIN_SIZE 0x00002000 + +#define DAPLINK_ROM_IF_START 0x00010000 +#define DAPLINK_ROM_IF_SIZE 0x0006E000 + +#define DAPLINK_ROM_CONFIG_USER_START 0x0007E000 +#define DAPLINK_ROM_CONFIG_USER_SIZE 0x00002000 + +/* RAM sizes */ + +#define DAPLINK_RAM_APP_START 0x20000000 +#define DAPLINK_RAM_APP_SIZE 0x00030000 + +#define DAPLINK_RAM_SHARED_START 0x20030000 +#define DAPLINK_RAM_SHARED_SIZE 0x00010000 + +/* Flash Programming Info */ + +#define DAPLINK_SECTOR_SIZE 0x00002000 +#define DAPLINK_MIN_WRITE_SIZE 0x00000020 + +/* Current build */ + +#if defined(DAPLINK_BL) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_BL_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_IF_SIZE + +#elif defined(DAPLINK_IF) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_IF_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_BL_SIZE + +#else + +#error "Build must be either bootloader or interface" + +#endif + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/flc_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32620/flc_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,300 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_FLC_REGS_H_
+#define _MXC_FLC_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+
+
+#define MXC_V_FLC_ERASE_CODE_PAGE_ERASE ((uint8_t)0x55)
+#define MXC_V_FLC_ERASE_CODE_MASS_ERASE ((uint8_t)0xAA)
+#define MXC_V_FLC_FLSH_UNLOCK_KEY ((uint8_t)0x2)
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __IO uint32_t faddr; /* 0x0000 Flash Operation Address */
+ __IO uint32_t fckdiv; /* 0x0004 Flash Clock Pulse Divisor */
+ __IO uint32_t ctrl; /* 0x0008 Flash Control Register */
+ __R uint32_t rsv00C[6]; /* 0x000C-0x0020 */
+ __IO uint32_t intr; /* 0x0024 Flash Controller Interrupt Flags and Enable/Disable 0 */
+ __R uint32_t rsv028[2]; /* 0x0028-0x002C */
+ __IO uint32_t fdata; /* 0x0030 Flash Operation Data Register */
+ __R uint32_t rsv034[7]; /* 0x0034-0x004C */
+ __IO uint32_t perform; /* 0x0050 Flash Performance Settings */
+ __IO uint32_t tacc; /* 0x0054 Flash Read Cycle Config */
+ __IO uint32_t tprog; /* 0x0058 Flash Write Cycle Config */
+ __R uint32_t rsv05C[9]; /* 0x005C-0x007C */
+ __IO uint32_t status; /* 0x0080 Security Status Flags */
+ __R uint32_t rsv084; /* 0x0084 */
+ __IO uint32_t security; /* 0x0088 Flash Controller Security Settings */
+ __R uint32_t rsv08C[4]; /* 0x008C-0x0098 */
+ __IO uint32_t bypass; /* 0x009C Status Flags for DSB Operations */
+ __R uint32_t rsv0A0[24]; /* 0x00A0-0x00FC */
+ __IO uint32_t user_option; /* 0x0100 Used to set DSB Access code and Auto-Lock in info block */
+ __R uint32_t rsv104[15]; /* 0x0104-0x013C */
+ __IO uint32_t ctrl2; /* 0x0140 Flash Control Register 2 */
+ __IO uint32_t intfl1; /* 0x0144 Interrupt Flags Register 1 */
+ __IO uint32_t inten1; /* 0x0148 Interrupt Enable/Disable Register 1 */
+ __R uint32_t rsv14C[9]; /* 0x014C-0x016C */
+ __IO uint32_t bl_ctrl; /* 0x0170 Bootloader Control Register */
+ __IO uint32_t twk; /* 0x0174 PDM33 Register */
+ __R uint32_t rsv178; /* 0x0178 */
+ __IO uint32_t slm; /* 0x017C Sleep Mode Register */
+ __R uint32_t rsv180[32]; /* 0x0180-0x01FC */
+ __IO uint32_t disable_xr0; /* 0x0200 Disable Flash Page Exec/Read Register 0 */
+ __IO uint32_t disable_xr1; /* 0x0204 Disable Flash Page Exec/Read Register 1 */
+ __IO uint32_t disable_xr2; /* 0x0208 Disable Flash Page Exec/Read Register 2 */
+ __IO uint32_t disable_xr3; /* 0x020C Disable Flash Page Exec/Read Register 3 */
+ __IO uint32_t disable_xr4; /* 0x0210 Disable Flash Page Exec/Read Register 4 */
+ __IO uint32_t disable_xr5; /* 0x0214 Disable Flash Page Exec/Read Register 5 */
+ __IO uint32_t disable_xr6; /* 0x0218 Disable Flash Page Exec/Read Register 6 */
+ __IO uint32_t disable_xr7; /* 0x021C Disable Flash Page Exec/Read Register 7 */
+ __R uint32_t rsv220[56]; /* 0x0220-0x02FC */
+ __IO uint32_t disable_we0; /* 0x0300 Disable Flash Page Write/Erase Register 0 */
+ __IO uint32_t disable_we1; /* 0x0304 Disable Flash Page Write/Erase Register 1 */
+ __IO uint32_t disable_we2; /* 0x0308 Disable Flash Page Write/Erase Register 2 */
+ __IO uint32_t disable_we3; /* 0x030C Disable Flash Page Write/Erase Register 3 */
+ __IO uint32_t disable_we4; /* 0x0310 Disable Flash Page Write/Erase Register 4 */
+ __IO uint32_t disable_we5; /* 0x0314 Disable Flash Page Write/Erase Register 5 */
+ __IO uint32_t disable_we6; /* 0x0318 Disable Flash Page Write/Erase Register 6 */
+ __IO uint32_t disable_we7; /* 0x031C Disable Flash Page Write/Erase Register 7 */
+} mxc_flc_regs_t;
+
+
+/*
+ Register offsets for module FLC.
+*/
+
+#define MXC_R_FLC_OFFS_FADDR ((uint32_t)0x00000000UL)
+#define MXC_R_FLC_OFFS_FCKDIV ((uint32_t)0x00000004UL)
+#define MXC_R_FLC_OFFS_CTRL ((uint32_t)0x00000008UL)
+#define MXC_R_FLC_OFFS_INTR ((uint32_t)0x00000024UL)
+#define MXC_R_FLC_OFFS_FDATA ((uint32_t)0x00000030UL)
+#define MXC_R_FLC_OFFS_PERFORM ((uint32_t)0x00000050UL)
+#define MXC_R_FLC_OFFS_TACC ((uint32_t)0x00000054UL)
+#define MXC_R_FLC_OFFS_TPROG ((uint32_t)0x00000058UL)
+#define MXC_R_FLC_OFFS_STATUS ((uint32_t)0x00000080UL)
+#define MXC_R_FLC_OFFS_SECURITY ((uint32_t)0x00000088UL)
+#define MXC_R_FLC_OFFS_BYPASS ((uint32_t)0x0000009CUL)
+#define MXC_R_FLC_OFFS_USER_OPTION ((uint32_t)0x00000100UL)
+#define MXC_R_FLC_OFFS_CTRL2 ((uint32_t)0x00000140UL)
+#define MXC_R_FLC_OFFS_INTFL1 ((uint32_t)0x00000144UL)
+#define MXC_R_FLC_OFFS_INTEN1 ((uint32_t)0x00000148UL)
+#define MXC_R_FLC_OFFS_BL_CTRL ((uint32_t)0x00000170UL)
+#define MXC_R_FLC_OFFS_TWK ((uint32_t)0x00000174UL)
+#define MXC_R_FLC_OFFS_SLM ((uint32_t)0x0000017CUL)
+#define MXC_R_FLC_OFFS_DISABLE_XR0 ((uint32_t)0x00000200UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR1 ((uint32_t)0x00000204UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR2 ((uint32_t)0x00000208UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR3 ((uint32_t)0x0000020CUL)
+#define MXC_R_FLC_OFFS_DISABLE_XR4 ((uint32_t)0x00000210UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR5 ((uint32_t)0x00000214UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR6 ((uint32_t)0x00000218UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR7 ((uint32_t)0x0000021CUL)
+#define MXC_R_FLC_OFFS_DISABLE_WE0 ((uint32_t)0x00000300UL)
+#define MXC_R_FLC_OFFS_DISABLE_WE1 ((uint32_t)0x00000304UL)
+#define MXC_R_FLC_OFFS_DISABLE_WE2 ((uint32_t)0x00000308UL)
+#define MXC_R_FLC_OFFS_DISABLE_WE3 ((uint32_t)0x0000030CUL)
+#define MXC_R_FLC_OFFS_DISABLE_WE4 ((uint32_t)0x00000310UL)
+#define MXC_R_FLC_OFFS_DISABLE_WE5 ((uint32_t)0x00000314UL)
+#define MXC_R_FLC_OFFS_DISABLE_WE6 ((uint32_t)0x00000318UL)
+#define MXC_R_FLC_OFFS_DISABLE_WE7 ((uint32_t)0x0000031CUL)
+
+
+/*
+ Field positions and masks for module FLC.
+*/
+
+#define MXC_F_FLC_FADDR_FADDR_POS 0
+#define MXC_F_FLC_FADDR_FADDR ((uint32_t)(0x003FFFFFUL << MXC_F_FLC_FADDR_FADDR_POS))
+
+#define MXC_F_FLC_FCKDIV_FCKDIV_POS 0
+#define MXC_F_FLC_FCKDIV_FCKDIV ((uint32_t)(0x0000007FUL << MXC_F_FLC_FCKDIV_FCKDIV_POS))
+#define MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT_POS 16
+#define MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT ((uint32_t)(0x0000FFFFUL << MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT_POS))
+
+#define MXC_F_FLC_CTRL_WRITE_POS 0
+#define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_POS))
+#define MXC_F_FLC_CTRL_MASS_ERASE_POS 1
+#define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_MASS_ERASE_POS))
+#define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2
+#define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS))
+#define MXC_F_FLC_CTRL_ERASE_CODE_POS 8
+#define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS))
+#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS 16
+#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS))
+#define MXC_F_FLC_CTRL_WRITE_ENABLE_POS 17
+#define MXC_F_FLC_CTRL_WRITE_ENABLE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_ENABLE_POS))
+#define MXC_F_FLC_CTRL_PENDING_POS 24
+#define MXC_F_FLC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PENDING_POS))
+#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS 25
+#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS))
+#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS 27
+#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS))
+#define MXC_F_FLC_CTRL_FLSH_UNLOCK_POS 28
+#define MXC_F_FLC_CTRL_FLSH_UNLOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS))
+
+#define MXC_F_FLC_INTR_FINISHED_IF_POS 0
+#define MXC_F_FLC_INTR_FINISHED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FINISHED_IF_POS))
+#define MXC_F_FLC_INTR_FAILED_IF_POS 1
+#define MXC_F_FLC_INTR_FAILED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IF_POS))
+#define MXC_F_FLC_INTR_FINISHED_IE_POS 8
+#define MXC_F_FLC_INTR_FINISHED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FINISHED_IE_POS))
+#define MXC_F_FLC_INTR_FAILED_IE_POS 9
+#define MXC_F_FLC_INTR_FAILED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IE_POS))
+#define MXC_F_FLC_INTR_FAIL_FLAGS_POS 16
+#define MXC_F_FLC_INTR_FAIL_FLAGS ((uint32_t)(0x0000FFFFUL << MXC_F_FLC_INTR_FAIL_FLAGS_POS))
+
+#define MXC_F_FLC_PERFORM_DELAY_SE_EN_POS 0
+#define MXC_F_FLC_PERFORM_DELAY_SE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_DELAY_SE_EN_POS))
+#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS 8
+#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS))
+#define MXC_F_FLC_PERFORM_EN_PREVENT_FAIL_POS 12
+#define MXC_F_FLC_PERFORM_EN_PREVENT_FAIL ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_PREVENT_FAIL_POS))
+#define MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS_POS 16
+#define MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS_POS))
+#define MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS_POS 20
+#define MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS_POS))
+#define MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT_POS 24
+#define MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT_POS))
+#define MXC_F_FLC_PERFORM_AUTO_TACC_POS 28
+#define MXC_F_FLC_PERFORM_AUTO_TACC ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_AUTO_TACC_POS))
+#define MXC_F_FLC_PERFORM_AUTO_CLKDIV_POS 29
+#define MXC_F_FLC_PERFORM_AUTO_CLKDIV ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_AUTO_CLKDIV_POS))
+
+#define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS 0
+#define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS))
+#define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS 1
+#define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS))
+#define MXC_F_FLC_STATUS_AUTO_LOCK_POS 3
+#define MXC_F_FLC_STATUS_AUTO_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_AUTO_LOCK_POS))
+#define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS 29
+#define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS))
+#define MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS 30
+#define MXC_F_FLC_STATUS_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS))
+
+#define MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS 0
+#define MXC_F_FLC_SECURITY_DEBUG_DISABLE ((uint32_t)(0x000000FFUL << MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS))
+#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS 8
+#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS))
+#define MXC_F_FLC_SECURITY_DISABLE_AHB_WR_POS 16
+#define MXC_F_FLC_SECURITY_DISABLE_AHB_WR ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_DISABLE_AHB_WR_POS))
+#define MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK_POS 24
+#define MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK_POS))
+#define MXC_F_FLC_SECURITY_SECURITY_LOCK_POS 28
+#define MXC_F_FLC_SECURITY_SECURITY_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_SECURITY_LOCK_POS))
+
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS 0
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS))
+#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS 1
+#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS))
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS 2
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS))
+#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS 3
+#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS))
+
+#define MXC_F_FLC_CTRL2_FLASH_LVE_POS 0
+#define MXC_F_FLC_CTRL2_FLASH_LVE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FLASH_LVE_POS))
+#define MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS 1
+#define MXC_F_FLC_CTRL2_FRC_FCLK1_ON ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS))
+#define MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES_POS 3
+#define MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES_POS))
+#define MXC_F_FLC_CTRL2_EN_CHANGE_POS 4
+#define MXC_F_FLC_CTRL2_EN_CHANGE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_EN_CHANGE_POS))
+#define MXC_F_FLC_CTRL2_SLOW_CLK_POS 5
+#define MXC_F_FLC_CTRL2_SLOW_CLK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_SLOW_CLK_POS))
+#define MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP_POS 6
+#define MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP_POS))
+#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS 8
+#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS))
+
+#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS 0
+#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS))
+#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS 1
+#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS))
+#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS 2
+#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS))
+#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS 3
+#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS))
+#define MXC_F_FLC_INTFL1_FLC_STATE_DONE_POS 4
+#define MXC_F_FLC_INTFL1_FLC_STATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLC_STATE_DONE_POS))
+#define MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE_POS 5
+#define MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE_POS))
+
+#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS 0
+#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS))
+#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS 1
+#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS))
+#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS 2
+#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS))
+#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS 3
+#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS))
+#define MXC_F_FLC_INTEN1_FLC_STATE_DONE_POS 4
+#define MXC_F_FLC_INTEN1_FLC_STATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLC_STATE_DONE_POS))
+#define MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE_POS 5
+#define MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE_POS))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_FLC_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/gpio.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32620/gpio.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,113 @@
+/* CMSIS-DAP Interface Firmware
+ * Copyright (c) 2009-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "max32620.h"
+#include "clkman_regs.h"
+#include "gpio_regs.h"
+#include "IO_Config.h"
+#include "gpio.h"
+
+/******************************************************************************/
+void gpio_init(void)
+{
+ int i;
+ uint32_t out_mode;
+
+ // Ensure that the GPIO clock is enabled
+ if (MXC_CLKMAN->sys_clk_ctrl_6_gpio == MXC_S_CLKMAN_CLK_SCALE_DISABLED) {
+ MXC_CLKMAN->sys_clk_ctrl_6_gpio = MXC_S_CLKMAN_CLK_SCALE_DIV_1;
+ }
+
+ // All inputs readable
+ for (i = 0; i < MXC_GPIO_NUM_PORTS; i++) {
+ MXC_GPIO->in_mode[i] = 0x00000000;
+ }
+
+ // LED initial state off
+ MXC_GPIO->out_val[PIN_DAP_LED_PORT] |= (1 << PIN_DAP_LED_PIN);
+ MXC_GPIO->out_val[PIN_MSD_LED_PORT] |= (1 << PIN_MSD_LED_PIN);
+ MXC_GPIO->out_val[PIN_CDC_LED_PORT] |= (1 << PIN_CDC_LED_PIN);
+
+ // LED outputs
+ out_mode = MXC_GPIO->out_mode[PIN_DAP_LED_PORT];
+ out_mode &= ~(0xFU << (4 * PIN_DAP_LED_PIN));
+ out_mode |= (MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << (4 * PIN_DAP_LED_PIN));
+ MXC_GPIO->out_mode[PIN_DAP_LED_PORT] = out_mode;
+
+ out_mode = MXC_GPIO->out_mode[PIN_MSD_LED_PORT];
+ out_mode &= ~(0xFU << (4 * PIN_MSD_LED_PIN));
+ out_mode |= (MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << (4 * PIN_MSD_LED_PIN));
+ MXC_GPIO->out_mode[PIN_MSD_LED_PORT] = out_mode;
+
+ out_mode = MXC_GPIO->out_mode[PIN_CDC_LED_PORT];
+ out_mode &= ~(0xFU << (4 * PIN_CDC_LED_PIN));
+ out_mode |= (MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << (4 * PIN_CDC_LED_PIN));
+ MXC_GPIO->out_mode[PIN_CDC_LED_PORT] = out_mode;
+
+ // Button input
+ out_mode = MXC_GPIO->out_mode[PIN_RESET_IN_NO_FWRD_PORT];
+ out_mode &= ~(0xFU << (4 * PIN_RESET_IN_NO_FWRD_PIN));
+ out_mode |= (MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << (4 * PIN_RESET_IN_NO_FWRD_PIN));
+ MXC_GPIO->out_mode[PIN_RESET_IN_NO_FWRD_PORT] = out_mode;
+ MXC_GPIO->out_val[PIN_RESET_IN_NO_FWRD_PORT] |= (0x1 << PIN_RESET_IN_NO_FWRD_PIN);
+}
+
+/******************************************************************************/
+void gpio_set_hid_led(gpio_led_state_t state)
+{
+ if (state == GPIO_LED_ON) {
+ MXC_CLRBIT(&MXC_GPIO->out_val[PIN_DAP_LED_PORT], PIN_DAP_LED_PIN);
+ } else {
+ MXC_SETBIT(&MXC_GPIO->out_val[PIN_DAP_LED_PORT], PIN_DAP_LED_PIN);
+ }
+}
+
+/******************************************************************************/
+void gpio_set_msc_led(gpio_led_state_t state)
+{
+ if (state == GPIO_LED_ON) {
+ MXC_CLRBIT(&MXC_GPIO->out_val[PIN_MSD_LED_PORT], PIN_MSD_LED_PIN);
+ } else {
+ MXC_SETBIT(&MXC_GPIO->out_val[PIN_MSD_LED_PORT], PIN_MSD_LED_PIN);
+ }
+}
+
+/******************************************************************************/
+void gpio_set_cdc_led(gpio_led_state_t state)
+{
+ if (state == GPIO_LED_ON) {
+ MXC_CLRBIT(&MXC_GPIO->out_val[PIN_CDC_LED_PORT], PIN_CDC_LED_PIN);
+ } else {
+ MXC_SETBIT(&MXC_GPIO->out_val[PIN_CDC_LED_PORT], PIN_CDC_LED_PIN);
+ }
+}
+
+/******************************************************************************/
+uint8_t gpio_get_reset_btn_no_fwrd(void)
+{
+ return !MXC_GETBIT(&MXC_GPIO->in_val[PIN_RESET_IN_NO_FWRD_PORT], PIN_RESET_IN_NO_FWRD_PIN);
+}
+
+/******************************************************************************/
+uint8_t gpio_get_reset_btn_fwrd(void)
+{
+ return 0;
+}
+
+/******************************************************************************/
+void gpio_set_board_power(bool powerEnabled)
+{
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/gpio_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32620/gpio_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,472 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_GPIO_REGS_H_
+#define _MXC_GPIO_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __IO uint32_t rst_mode[16]; /* 0x0000-0x003C Port P[0..15] Default (Power-On Reset) Output Drive Mode */
+ __IO uint32_t free[16]; /* 0x0040-0x007C Port P[0..15] Free for GPIO Operation Flags */
+ __IO uint32_t out_mode[16]; /* 0x0080-0x00BC Port P[0..15] Output Drive Mode */
+ __IO uint32_t out_val[16]; /* 0x00C0-0x00FC Port P[0..15] GPIO Output Value */
+ __IO uint32_t func_sel[16]; /* 0x0100-0x013C Port P[0..15] GPIO Function Select */
+ __IO uint32_t in_mode[16]; /* 0x0140-0x017C Port P[0..15] GPIO Input Monitoring Mode */
+ __IO uint32_t in_val[16]; /* 0x0180-0x01BC Port P[0..15] GPIO Input Value */
+ __IO uint32_t int_mode[16]; /* 0x01C0-0x01FC Port P[0..15] Interrupt Detection Mode */
+ __IO uint32_t intfl[16]; /* 0x0200-0x023C Port P[0..15] Interrupt Flags */
+ __IO uint32_t inten[16]; /* 0x0240-0x027C Port P[0..15] Interrupt Enables */
+} mxc_gpio_regs_t;
+
+
+/*
+ Register offsets for module GPIO.
+*/
+
+#define MXC_R_GPIO_OFFS_RST_MODE_P0 ((uint32_t)0x00000000UL)
+#define MXC_R_GPIO_OFFS_RST_MODE_P1 ((uint32_t)0x00000004UL)
+#define MXC_R_GPIO_OFFS_RST_MODE_P2 ((uint32_t)0x00000008UL)
+#define MXC_R_GPIO_OFFS_RST_MODE_P3 ((uint32_t)0x0000000CUL)
+#define MXC_R_GPIO_OFFS_RST_MODE_P4 ((uint32_t)0x00000010UL)
+#define MXC_R_GPIO_OFFS_RST_MODE_P5 ((uint32_t)0x00000014UL)
+#define MXC_R_GPIO_OFFS_RST_MODE_P6 ((uint32_t)0x00000018UL)
+#define MXC_R_GPIO_OFFS_RST_MODE_P7 ((uint32_t)0x0000001CUL)
+#define MXC_R_GPIO_OFFS_RST_MODE_P8 ((uint32_t)0x00000020UL)
+#define MXC_R_GPIO_OFFS_RST_MODE_P9 ((uint32_t)0x00000024UL)
+#define MXC_R_GPIO_OFFS_RST_MODE_P10 ((uint32_t)0x00000028UL)
+#define MXC_R_GPIO_OFFS_RST_MODE_P11 ((uint32_t)0x0000002CUL)
+#define MXC_R_GPIO_OFFS_RST_MODE_P12 ((uint32_t)0x00000030UL)
+#define MXC_R_GPIO_OFFS_RST_MODE_P13 ((uint32_t)0x00000034UL)
+#define MXC_R_GPIO_OFFS_RST_MODE_P14 ((uint32_t)0x00000038UL)
+#define MXC_R_GPIO_OFFS_RST_MODE_P15 ((uint32_t)0x0000003CUL)
+#define MXC_R_GPIO_OFFS_FREE_P0 ((uint32_t)0x00000040UL)
+#define MXC_R_GPIO_OFFS_FREE_P1 ((uint32_t)0x00000044UL)
+#define MXC_R_GPIO_OFFS_FREE_P2 ((uint32_t)0x00000048UL)
+#define MXC_R_GPIO_OFFS_FREE_P3 ((uint32_t)0x0000004CUL)
+#define MXC_R_GPIO_OFFS_FREE_P4 ((uint32_t)0x00000050UL)
+#define MXC_R_GPIO_OFFS_FREE_P5 ((uint32_t)0x00000054UL)
+#define MXC_R_GPIO_OFFS_FREE_P6 ((uint32_t)0x00000058UL)
+#define MXC_R_GPIO_OFFS_FREE_P7 ((uint32_t)0x0000005CUL)
+#define MXC_R_GPIO_OFFS_FREE_P8 ((uint32_t)0x00000060UL)
+#define MXC_R_GPIO_OFFS_FREE_P9 ((uint32_t)0x00000064UL)
+#define MXC_R_GPIO_OFFS_FREE_P10 ((uint32_t)0x00000068UL)
+#define MXC_R_GPIO_OFFS_FREE_P11 ((uint32_t)0x0000006CUL)
+#define MXC_R_GPIO_OFFS_FREE_P12 ((uint32_t)0x00000070UL)
+#define MXC_R_GPIO_OFFS_FREE_P13 ((uint32_t)0x00000074UL)
+#define MXC_R_GPIO_OFFS_FREE_P14 ((uint32_t)0x00000078UL)
+#define MXC_R_GPIO_OFFS_FREE_P15 ((uint32_t)0x0000007CUL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P0 ((uint32_t)0x00000080UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P1 ((uint32_t)0x00000084UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P2 ((uint32_t)0x00000088UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P3 ((uint32_t)0x0000008CUL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P4 ((uint32_t)0x00000090UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P5 ((uint32_t)0x00000094UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P6 ((uint32_t)0x00000098UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P7 ((uint32_t)0x0000009CUL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P8 ((uint32_t)0x000000A0UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P9 ((uint32_t)0x000000A4UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P10 ((uint32_t)0x000000A8UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P11 ((uint32_t)0x000000ACUL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P12 ((uint32_t)0x000000B0UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P13 ((uint32_t)0x000000B4UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P14 ((uint32_t)0x000000B8UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P15 ((uint32_t)0x000000BCUL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P0 ((uint32_t)0x000000C0UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P1 ((uint32_t)0x000000C4UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P2 ((uint32_t)0x000000C8UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P3 ((uint32_t)0x000000CCUL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P4 ((uint32_t)0x000000D0UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P5 ((uint32_t)0x000000D4UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P6 ((uint32_t)0x000000D8UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P7 ((uint32_t)0x000000DCUL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P8 ((uint32_t)0x000000E0UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P9 ((uint32_t)0x000000E4UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P10 ((uint32_t)0x000000E8UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P11 ((uint32_t)0x000000ECUL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P12 ((uint32_t)0x000000F0UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P13 ((uint32_t)0x000000F4UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P14 ((uint32_t)0x000000F8UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P15 ((uint32_t)0x000000FCUL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P0 ((uint32_t)0x00000100UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P1 ((uint32_t)0x00000104UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P2 ((uint32_t)0x00000108UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P3 ((uint32_t)0x0000010CUL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P4 ((uint32_t)0x00000110UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P5 ((uint32_t)0x00000114UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P6 ((uint32_t)0x00000118UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P7 ((uint32_t)0x0000011CUL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P8 ((uint32_t)0x00000120UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P9 ((uint32_t)0x00000124UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P10 ((uint32_t)0x00000128UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P11 ((uint32_t)0x0000012CUL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P12 ((uint32_t)0x00000130UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P13 ((uint32_t)0x00000134UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P14 ((uint32_t)0x00000138UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P15 ((uint32_t)0x0000013CUL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P0 ((uint32_t)0x00000140UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P1 ((uint32_t)0x00000144UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P2 ((uint32_t)0x00000148UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P3 ((uint32_t)0x0000014CUL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P4 ((uint32_t)0x00000150UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P5 ((uint32_t)0x00000154UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P6 ((uint32_t)0x00000158UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P7 ((uint32_t)0x0000015CUL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P8 ((uint32_t)0x00000160UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P9 ((uint32_t)0x00000164UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P10 ((uint32_t)0x00000168UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P11 ((uint32_t)0x0000016CUL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P12 ((uint32_t)0x00000170UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P13 ((uint32_t)0x00000174UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P14 ((uint32_t)0x00000178UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P15 ((uint32_t)0x0000017CUL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P0 ((uint32_t)0x00000180UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P1 ((uint32_t)0x00000184UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P2 ((uint32_t)0x00000188UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P3 ((uint32_t)0x0000018CUL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P4 ((uint32_t)0x00000190UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P5 ((uint32_t)0x00000194UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P6 ((uint32_t)0x00000198UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P7 ((uint32_t)0x0000019CUL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P8 ((uint32_t)0x000001A0UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P9 ((uint32_t)0x000001A4UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P10 ((uint32_t)0x000001A8UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P11 ((uint32_t)0x000001ACUL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P12 ((uint32_t)0x000001B0UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P13 ((uint32_t)0x000001B4UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P14 ((uint32_t)0x000001B8UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P15 ((uint32_t)0x000001BCUL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P0 ((uint32_t)0x000001C0UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P1 ((uint32_t)0x000001C4UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P2 ((uint32_t)0x000001C8UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P3 ((uint32_t)0x000001CCUL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P4 ((uint32_t)0x000001D0UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P5 ((uint32_t)0x000001D4UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P6 ((uint32_t)0x000001D8UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P7 ((uint32_t)0x000001DCUL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P8 ((uint32_t)0x000001E0UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P9 ((uint32_t)0x000001E4UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P10 ((uint32_t)0x000001E8UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P11 ((uint32_t)0x000001ECUL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P12 ((uint32_t)0x000001F0UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P13 ((uint32_t)0x000001F4UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P14 ((uint32_t)0x000001F8UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P15 ((uint32_t)0x000001FCUL)
+#define MXC_R_GPIO_OFFS_INTFL_P0 ((uint32_t)0x00000200UL)
+#define MXC_R_GPIO_OFFS_INTFL_P1 ((uint32_t)0x00000204UL)
+#define MXC_R_GPIO_OFFS_INTFL_P2 ((uint32_t)0x00000208UL)
+#define MXC_R_GPIO_OFFS_INTFL_P3 ((uint32_t)0x0000020CUL)
+#define MXC_R_GPIO_OFFS_INTFL_P4 ((uint32_t)0x00000210UL)
+#define MXC_R_GPIO_OFFS_INTFL_P5 ((uint32_t)0x00000214UL)
+#define MXC_R_GPIO_OFFS_INTFL_P6 ((uint32_t)0x00000218UL)
+#define MXC_R_GPIO_OFFS_INTFL_P7 ((uint32_t)0x0000021CUL)
+#define MXC_R_GPIO_OFFS_INTFL_P8 ((uint32_t)0x00000220UL)
+#define MXC_R_GPIO_OFFS_INTFL_P9 ((uint32_t)0x00000224UL)
+#define MXC_R_GPIO_OFFS_INTFL_P10 ((uint32_t)0x00000228UL)
+#define MXC_R_GPIO_OFFS_INTFL_P11 ((uint32_t)0x0000022CUL)
+#define MXC_R_GPIO_OFFS_INTFL_P12 ((uint32_t)0x00000230UL)
+#define MXC_R_GPIO_OFFS_INTFL_P13 ((uint32_t)0x00000234UL)
+#define MXC_R_GPIO_OFFS_INTFL_P14 ((uint32_t)0x00000238UL)
+#define MXC_R_GPIO_OFFS_INTFL_P15 ((uint32_t)0x0000023CUL)
+#define MXC_R_GPIO_OFFS_INTEN_P0 ((uint32_t)0x00000240UL)
+#define MXC_R_GPIO_OFFS_INTEN_P1 ((uint32_t)0x00000244UL)
+#define MXC_R_GPIO_OFFS_INTEN_P2 ((uint32_t)0x00000248UL)
+#define MXC_R_GPIO_OFFS_INTEN_P3 ((uint32_t)0x0000024CUL)
+#define MXC_R_GPIO_OFFS_INTEN_P4 ((uint32_t)0x00000250UL)
+#define MXC_R_GPIO_OFFS_INTEN_P5 ((uint32_t)0x00000254UL)
+#define MXC_R_GPIO_OFFS_INTEN_P6 ((uint32_t)0x00000258UL)
+#define MXC_R_GPIO_OFFS_INTEN_P7 ((uint32_t)0x0000025CUL)
+#define MXC_R_GPIO_OFFS_INTEN_P8 ((uint32_t)0x00000260UL)
+#define MXC_R_GPIO_OFFS_INTEN_P9 ((uint32_t)0x00000264UL)
+#define MXC_R_GPIO_OFFS_INTEN_P10 ((uint32_t)0x00000268UL)
+#define MXC_R_GPIO_OFFS_INTEN_P11 ((uint32_t)0x0000026CUL)
+#define MXC_R_GPIO_OFFS_INTEN_P12 ((uint32_t)0x00000270UL)
+#define MXC_R_GPIO_OFFS_INTEN_P13 ((uint32_t)0x00000274UL)
+#define MXC_R_GPIO_OFFS_INTEN_P14 ((uint32_t)0x00000278UL)
+#define MXC_R_GPIO_OFFS_INTEN_P15 ((uint32_t)0x0000027CUL)
+
+
+/*
+ Field positions and masks for module GPIO.
+*/
+
+#define MXC_F_GPIO_RST_MODE_PIN0_POS 0
+#define MXC_F_GPIO_RST_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN0_POS))
+#define MXC_F_GPIO_RST_MODE_PIN1_POS 4
+#define MXC_F_GPIO_RST_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN1_POS))
+#define MXC_F_GPIO_RST_MODE_PIN2_POS 8
+#define MXC_F_GPIO_RST_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN2_POS))
+#define MXC_F_GPIO_RST_MODE_PIN3_POS 12
+#define MXC_F_GPIO_RST_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN3_POS))
+#define MXC_F_GPIO_RST_MODE_PIN4_POS 16
+#define MXC_F_GPIO_RST_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN4_POS))
+#define MXC_F_GPIO_RST_MODE_PIN5_POS 20
+#define MXC_F_GPIO_RST_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN5_POS))
+#define MXC_F_GPIO_RST_MODE_PIN6_POS 24
+#define MXC_F_GPIO_RST_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN6_POS))
+#define MXC_F_GPIO_RST_MODE_PIN7_POS 28
+#define MXC_F_GPIO_RST_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN7_POS))
+
+#define MXC_F_GPIO_FREE_PIN0_POS 0
+#define MXC_F_GPIO_FREE_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN0_POS))
+#define MXC_F_GPIO_FREE_PIN1_POS 1
+#define MXC_F_GPIO_FREE_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN1_POS))
+#define MXC_F_GPIO_FREE_PIN2_POS 2
+#define MXC_F_GPIO_FREE_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN2_POS))
+#define MXC_F_GPIO_FREE_PIN3_POS 3
+#define MXC_F_GPIO_FREE_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN3_POS))
+#define MXC_F_GPIO_FREE_PIN4_POS 4
+#define MXC_F_GPIO_FREE_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN4_POS))
+#define MXC_F_GPIO_FREE_PIN5_POS 5
+#define MXC_F_GPIO_FREE_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN5_POS))
+#define MXC_F_GPIO_FREE_PIN6_POS 6
+#define MXC_F_GPIO_FREE_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN6_POS))
+#define MXC_F_GPIO_FREE_PIN7_POS 7
+#define MXC_F_GPIO_FREE_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN7_POS))
+
+#define MXC_F_GPIO_OUT_MODE_PIN0_POS 0
+#define MXC_F_GPIO_OUT_MODE_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN1_POS 4
+#define MXC_F_GPIO_OUT_MODE_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN2_POS 8
+#define MXC_F_GPIO_OUT_MODE_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN3_POS 12
+#define MXC_F_GPIO_OUT_MODE_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN4_POS 16
+#define MXC_F_GPIO_OUT_MODE_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN5_POS 20
+#define MXC_F_GPIO_OUT_MODE_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN6_POS 24
+#define MXC_F_GPIO_OUT_MODE_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN7_POS 28
+#define MXC_F_GPIO_OUT_MODE_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+
+#define MXC_F_GPIO_OUT_VAL_PIN0_POS 0
+#define MXC_F_GPIO_OUT_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN0_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN1_POS 1
+#define MXC_F_GPIO_OUT_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN1_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN2_POS 2
+#define MXC_F_GPIO_OUT_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN2_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN3_POS 3
+#define MXC_F_GPIO_OUT_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN3_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN4_POS 4
+#define MXC_F_GPIO_OUT_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN4_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN5_POS 5
+#define MXC_F_GPIO_OUT_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN5_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN6_POS 6
+#define MXC_F_GPIO_OUT_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN6_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN7_POS 7
+#define MXC_F_GPIO_OUT_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN7_POS))
+
+#define MXC_F_GPIO_FUNC_SEL_PIN0_POS 0
+#define MXC_F_GPIO_FUNC_SEL_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN0_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN1_POS 4
+#define MXC_F_GPIO_FUNC_SEL_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN1_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN2_POS 8
+#define MXC_F_GPIO_FUNC_SEL_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN2_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN3_POS 12
+#define MXC_F_GPIO_FUNC_SEL_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN3_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN4_POS 16
+#define MXC_F_GPIO_FUNC_SEL_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN4_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN5_POS 20
+#define MXC_F_GPIO_FUNC_SEL_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN5_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN6_POS 24
+#define MXC_F_GPIO_FUNC_SEL_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN6_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN7_POS 28
+#define MXC_F_GPIO_FUNC_SEL_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN7_POS))
+
+#define MXC_F_GPIO_IN_MODE_PIN0_POS 0
+#define MXC_F_GPIO_IN_MODE_PIN0 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN0_POS))
+#define MXC_F_GPIO_IN_MODE_PIN1_POS 4
+#define MXC_F_GPIO_IN_MODE_PIN1 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN1_POS))
+#define MXC_F_GPIO_IN_MODE_PIN2_POS 8
+#define MXC_F_GPIO_IN_MODE_PIN2 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN2_POS))
+#define MXC_F_GPIO_IN_MODE_PIN3_POS 12
+#define MXC_F_GPIO_IN_MODE_PIN3 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN3_POS))
+#define MXC_F_GPIO_IN_MODE_PIN4_POS 16
+#define MXC_F_GPIO_IN_MODE_PIN4 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN4_POS))
+#define MXC_F_GPIO_IN_MODE_PIN5_POS 20
+#define MXC_F_GPIO_IN_MODE_PIN5 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN5_POS))
+#define MXC_F_GPIO_IN_MODE_PIN6_POS 24
+#define MXC_F_GPIO_IN_MODE_PIN6 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN6_POS))
+#define MXC_F_GPIO_IN_MODE_PIN7_POS 28
+#define MXC_F_GPIO_IN_MODE_PIN7 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN7_POS))
+
+#define MXC_F_GPIO_IN_VAL_PIN0_POS 0
+#define MXC_F_GPIO_IN_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN0_POS))
+#define MXC_F_GPIO_IN_VAL_PIN1_POS 1
+#define MXC_F_GPIO_IN_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN1_POS))
+#define MXC_F_GPIO_IN_VAL_PIN2_POS 2
+#define MXC_F_GPIO_IN_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN2_POS))
+#define MXC_F_GPIO_IN_VAL_PIN3_POS 3
+#define MXC_F_GPIO_IN_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN3_POS))
+#define MXC_F_GPIO_IN_VAL_PIN4_POS 4
+#define MXC_F_GPIO_IN_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN4_POS))
+#define MXC_F_GPIO_IN_VAL_PIN5_POS 5
+#define MXC_F_GPIO_IN_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN5_POS))
+#define MXC_F_GPIO_IN_VAL_PIN6_POS 6
+#define MXC_F_GPIO_IN_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN6_POS))
+#define MXC_F_GPIO_IN_VAL_PIN7_POS 7
+#define MXC_F_GPIO_IN_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN7_POS))
+
+#define MXC_F_GPIO_INT_MODE_PIN0_POS 0
+#define MXC_F_GPIO_INT_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN0_POS))
+#define MXC_F_GPIO_INT_MODE_PIN1_POS 4
+#define MXC_F_GPIO_INT_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN1_POS))
+#define MXC_F_GPIO_INT_MODE_PIN2_POS 8
+#define MXC_F_GPIO_INT_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN2_POS))
+#define MXC_F_GPIO_INT_MODE_PIN3_POS 12
+#define MXC_F_GPIO_INT_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN3_POS))
+#define MXC_F_GPIO_INT_MODE_PIN4_POS 16
+#define MXC_F_GPIO_INT_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN4_POS))
+#define MXC_F_GPIO_INT_MODE_PIN5_POS 20
+#define MXC_F_GPIO_INT_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN5_POS))
+#define MXC_F_GPIO_INT_MODE_PIN6_POS 24
+#define MXC_F_GPIO_INT_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN6_POS))
+#define MXC_F_GPIO_INT_MODE_PIN7_POS 28
+#define MXC_F_GPIO_INT_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN7_POS))
+
+#define MXC_F_GPIO_INTFL_PIN0_POS 0
+#define MXC_F_GPIO_INTFL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN0_POS))
+#define MXC_F_GPIO_INTFL_PIN1_POS 1
+#define MXC_F_GPIO_INTFL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN1_POS))
+#define MXC_F_GPIO_INTFL_PIN2_POS 2
+#define MXC_F_GPIO_INTFL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN2_POS))
+#define MXC_F_GPIO_INTFL_PIN3_POS 3
+#define MXC_F_GPIO_INTFL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN3_POS))
+#define MXC_F_GPIO_INTFL_PIN4_POS 4
+#define MXC_F_GPIO_INTFL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN4_POS))
+#define MXC_F_GPIO_INTFL_PIN5_POS 5
+#define MXC_F_GPIO_INTFL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN5_POS))
+#define MXC_F_GPIO_INTFL_PIN6_POS 6
+#define MXC_F_GPIO_INTFL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN6_POS))
+#define MXC_F_GPIO_INTFL_PIN7_POS 7
+#define MXC_F_GPIO_INTFL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN7_POS))
+
+#define MXC_F_GPIO_INTEN_PIN0_POS 0
+#define MXC_F_GPIO_INTEN_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN0_POS))
+#define MXC_F_GPIO_INTEN_PIN1_POS 1
+#define MXC_F_GPIO_INTEN_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN1_POS))
+#define MXC_F_GPIO_INTEN_PIN2_POS 2
+#define MXC_F_GPIO_INTEN_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN2_POS))
+#define MXC_F_GPIO_INTEN_PIN3_POS 3
+#define MXC_F_GPIO_INTEN_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN3_POS))
+#define MXC_F_GPIO_INTEN_PIN4_POS 4
+#define MXC_F_GPIO_INTEN_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN4_POS))
+#define MXC_F_GPIO_INTEN_PIN5_POS 5
+#define MXC_F_GPIO_INTEN_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN5_POS))
+#define MXC_F_GPIO_INTEN_PIN6_POS 6
+#define MXC_F_GPIO_INTEN_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN6_POS))
+#define MXC_F_GPIO_INTEN_PIN7_POS 7
+#define MXC_F_GPIO_INTEN_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN7_POS))
+
+
+
+/*
+ Field values and shifted values for module GPIO.
+*/
+
+#define MXC_V_GPIO_RST_MODE_DRIVE_0 ((uint32_t)(0x00000000UL))
+#define MXC_V_GPIO_RST_MODE_WEAK_PULLDOWN ((uint32_t)(0x00000001UL))
+#define MXC_V_GPIO_RST_MODE_WEAK_PULLUP ((uint32_t)(0x00000002UL))
+#define MXC_V_GPIO_RST_MODE_DRIVE_1 ((uint32_t)(0x00000003UL))
+#define MXC_V_GPIO_RST_MODE_HIGH_Z ((uint32_t)(0x00000004UL))
+
+#define MXC_V_GPIO_FREE_NOT_AVAILABLE ((uint32_t)(0x00000000UL))
+#define MXC_V_GPIO_FREE_AVAILABLE ((uint32_t)(0x00000001UL))
+
+#define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP ((uint32_t)(0x00000000UL))
+#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN ((uint32_t)(0x00000001UL))
+#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(0x00000002UL))
+#define MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z ((uint32_t)(0x00000004UL))
+#define MXC_V_GPIO_OUT_MODE_NORMAL ((uint32_t)(0x00000005UL))
+#define MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z ((uint32_t)(0x00000006UL))
+#define MXC_V_GPIO_OUT_MODE_SLOW_DRIVE ((uint32_t)(0x00000007UL))
+#define MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z ((uint32_t)(0x00000008UL))
+#define MXC_V_GPIO_OUT_MODE_FAST_DRIVE ((uint32_t)(0x00000009UL))
+#define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN ((uint32_t)(0x0000000AUL))
+#define MXC_V_GPIO_OUT_MODE_OPEN_SOURCE ((uint32_t)(0x0000000BUL))
+#define MXC_V_GPIO_OUT_MODE_OPEN_SOURCE_WEAK_PULLDOWN ((uint32_t)(0x0000000CUL))
+#define MXC_V_GPIO_OUT_MODE_HIGH_Z_INPUT_DISABLED ((uint32_t)(0x0000000FUL))
+
+#define MXC_V_GPIO_FUNC_SEL_MODE_GPIO ((uint32_t)(0x00000000UL))
+#define MXC_V_GPIO_FUNC_SEL_MODE_PT ((uint32_t)(0x00000001UL))
+#define MXC_V_GPIO_FUNC_SEL_MODE_TMR ((uint32_t)(0x00000002UL))
+
+#define MXC_V_GPIO_IN_MODE_NORMAL ((uint32_t)(0x00000000UL))
+#define MXC_V_GPIO_IN_MODE_INVERTED ((uint32_t)(0x00000001UL))
+#define MXC_V_GPIO_IN_MODE_ALWAYS_ZERO ((uint32_t)(0x00000002UL))
+#define MXC_V_GPIO_IN_MODE_ALWAYS_ONE ((uint32_t)(0x00000003UL))
+
+#define MXC_V_GPIO_INT_MODE_DISABLE ((uint32_t)(0x00000000UL))
+#define MXC_V_GPIO_INT_MODE_FALLING_EDGE ((uint32_t)(0x00000001UL))
+#define MXC_V_GPIO_INT_MODE_RISING_EDGE ((uint32_t)(0x00000002UL))
+#define MXC_V_GPIO_INT_MODE_ANY_EDGE ((uint32_t)(0x00000003UL))
+#define MXC_V_GPIO_INT_MODE_LOW_LVL ((uint32_t)(0x00000004UL))
+#define MXC_V_GPIO_INT_MODE_HIGH_LVL ((uint32_t)(0x00000005UL))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_GPIO_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/icc_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32620/icc_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,114 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_ICC_REGS_H_
+#define _MXC_ICC_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __IO uint32_t id; /* 0x0000 Cache ID Register (INTERNAL USE ONLY) */
+ __IO uint32_t mem_cfg; /* 0x0004 Memory Configuration Register */
+ __R uint32_t rsv008[62]; /* 0x0008-0x00FC */
+ __IO uint32_t ctrl_stat; /* 0x0100 Control and Status */
+ __R uint32_t rsv104[383]; /* 0x0104-0x06FC */
+ __IO uint32_t invdt_all; /* 0x0700 Invalidate (Clear) Cache Control */
+} mxc_icc_regs_t;
+
+
+/*
+ Register offsets for module ICC.
+*/
+
+#define MXC_R_ICC_OFFS_ID ((uint32_t)0x00000000UL)
+#define MXC_R_ICC_OFFS_MEM_CFG ((uint32_t)0x00000004UL)
+#define MXC_R_ICC_OFFS_CTRL_STAT ((uint32_t)0x00000100UL)
+#define MXC_R_ICC_OFFS_INVDT_ALL ((uint32_t)0x00000700UL)
+
+
+/*
+ Field positions and masks for module ICC.
+*/
+
+#define MXC_F_ICC_ID_RTL_VERSION_POS 0
+#define MXC_F_ICC_ID_RTL_VERSION ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_RTL_VERSION_POS))
+#define MXC_F_ICC_ID_PART_NUM_POS 6
+#define MXC_F_ICC_ID_PART_NUM ((uint32_t)(0x0000000FUL << MXC_F_ICC_ID_PART_NUM_POS))
+#define MXC_F_ICC_ID_CACHE_ID_POS 10
+#define MXC_F_ICC_ID_CACHE_ID ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_CACHE_ID_POS))
+
+#define MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS 0
+#define MXC_F_ICC_MEM_CFG_CACHE_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS))
+#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS 16
+#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS))
+
+#define MXC_F_ICC_CTRL_STAT_ENABLE_POS 0
+#define MXC_F_ICC_CTRL_STAT_ENABLE ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_ENABLE_POS))
+#define MXC_F_ICC_CTRL_STAT_READY_POS 16
+#define MXC_F_ICC_CTRL_STAT_READY ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_READY_POS))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_ICC_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/ioman_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32620/ioman_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,995 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_IOMAN_REGS_H_
+#define _MXC_IOMAN_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+
+
+/*
+ Bitfield structs for registers in this module
+*/
+
+typedef struct {
+ uint32_t wud_req_p0 : 8;
+ uint32_t wud_req_p1 : 8;
+ uint32_t wud_req_p2 : 8;
+ uint32_t wud_req_p3 : 8;
+} mxc_ioman_wud_req0_t;
+
+typedef struct {
+ uint32_t wud_req_p4 : 8;
+ uint32_t wud_req_p5 : 8;
+ uint32_t wud_req_p6 : 8;
+ uint32_t wud_req_p7 : 8;
+} mxc_ioman_wud_req1_t;
+
+typedef struct {
+ uint32_t wud_ack_p0 : 8;
+ uint32_t wud_ack_p1 : 8;
+ uint32_t wud_ack_p2 : 8;
+ uint32_t wud_ack_p3 : 8;
+} mxc_ioman_wud_ack0_t;
+
+typedef struct {
+ uint32_t wud_ack_p4 : 8;
+ uint32_t wud_ack_p5 : 8;
+ uint32_t wud_ack_p6 : 8;
+ uint32_t wud_ack_p7 : 8;
+} mxc_ioman_wud_ack1_t;
+
+typedef struct {
+ uint32_t ali_req_p0 : 8;
+ uint32_t ali_req_p1 : 8;
+ uint32_t ali_req_p2 : 8;
+ uint32_t ali_req_p3 : 8;
+} mxc_ioman_ali_req0_t;
+
+typedef struct {
+ uint32_t ali_req_p4 : 8;
+ uint32_t ali_req_p5 : 8;
+ uint32_t ali_req_p6 : 8;
+ uint32_t ali_req_p7 : 8;
+} mxc_ioman_ali_req1_t;
+
+typedef struct {
+ uint32_t ali_ack_p0 : 8;
+ uint32_t ali_ack_p1 : 8;
+ uint32_t ali_ack_p2 : 8;
+ uint32_t ali_ack_p3 : 8;
+} mxc_ioman_ali_ack0_t;
+
+typedef struct {
+ uint32_t ali_ack_p4 : 8;
+ uint32_t ali_ack_p5 : 8;
+ uint32_t ali_ack_p6 : 8;
+ uint32_t ali_ack_p7 : 8;
+} mxc_ioman_ali_ack1_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t core_io_req : 1;
+ uint32_t : 3;
+ uint32_t ss0_io_req : 1;
+ uint32_t ss1_io_req : 1;
+ uint32_t ss2_io_req : 1;
+ uint32_t : 1;
+ uint32_t quad_io_req : 1;
+ uint32_t : 3;
+ uint32_t fast_mode : 1;
+ uint32_t : 15;
+} mxc_ioman_spix_req_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t core_io_ack : 1;
+ uint32_t : 3;
+ uint32_t ss0_io_ack : 1;
+ uint32_t ss1_io_ack : 1;
+ uint32_t ss2_io_ack : 1;
+ uint32_t : 1;
+ uint32_t quad_io_ack : 1;
+ uint32_t : 3;
+ uint32_t fast_mode : 1;
+ uint32_t : 15;
+} mxc_ioman_spix_ack_t;
+
+typedef struct {
+ uint32_t io_map : 1;
+ uint32_t cts_map : 1;
+ uint32_t rts_map : 1;
+ uint32_t : 1;
+ uint32_t io_req : 1;
+ uint32_t cts_io_req : 1;
+ uint32_t rts_io_req : 1;
+ uint32_t : 25;
+} mxc_ioman_uart0_req_t;
+
+typedef struct {
+ uint32_t io_map : 1;
+ uint32_t cts_map : 1;
+ uint32_t rts_map : 1;
+ uint32_t : 1;
+ uint32_t io_ack : 1;
+ uint32_t cts_io_ack : 1;
+ uint32_t rts_io_ack : 1;
+ uint32_t : 25;
+} mxc_ioman_uart0_ack_t;
+
+typedef struct {
+ uint32_t io_map : 1;
+ uint32_t cts_map : 1;
+ uint32_t rts_map : 1;
+ uint32_t : 1;
+ uint32_t io_req : 1;
+ uint32_t cts_io_req : 1;
+ uint32_t rts_io_req : 1;
+ uint32_t : 25;
+} mxc_ioman_uart1_req_t;
+
+typedef struct {
+ uint32_t io_map : 1;
+ uint32_t cts_map : 1;
+ uint32_t rts_map : 1;
+ uint32_t : 1;
+ uint32_t io_ack : 1;
+ uint32_t cts_io_ack : 1;
+ uint32_t rts_io_ack : 1;
+ uint32_t : 25;
+} mxc_ioman_uart1_ack_t;
+
+typedef struct {
+ uint32_t io_map : 1;
+ uint32_t cts_map : 1;
+ uint32_t rts_map : 1;
+ uint32_t : 1;
+ uint32_t io_req : 1;
+ uint32_t cts_io_req : 1;
+ uint32_t rts_io_req : 1;
+ uint32_t : 25;
+} mxc_ioman_uart2_req_t;
+
+typedef struct {
+ uint32_t io_map : 1;
+ uint32_t cts_map : 1;
+ uint32_t rts_map : 1;
+ uint32_t : 1;
+ uint32_t io_ack : 1;
+ uint32_t cts_io_ack : 1;
+ uint32_t rts_io_ack : 1;
+ uint32_t : 25;
+} mxc_ioman_uart2_ack_t;
+
+typedef struct {
+ uint32_t io_map : 1;
+ uint32_t cts_map : 1;
+ uint32_t rts_map : 1;
+ uint32_t : 1;
+ uint32_t io_req : 1;
+ uint32_t cts_io_req : 1;
+ uint32_t rts_io_req : 1;
+ uint32_t : 25;
+} mxc_ioman_uart3_req_t;
+
+typedef struct {
+ uint32_t io_map : 1;
+ uint32_t cts_map : 1;
+ uint32_t rts_map : 1;
+ uint32_t : 1;
+ uint32_t io_ack : 1;
+ uint32_t cts_io_ack : 1;
+ uint32_t rts_io_ack : 1;
+ uint32_t : 25;
+} mxc_ioman_uart3_ack_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t core_io_req : 1;
+ uint32_t push_pull : 1;
+ uint32_t : 26;
+} mxc_ioman_i2cm0_req_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t core_io_ack : 1;
+ uint32_t : 27;
+} mxc_ioman_i2cm0_ack_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t core_io_req : 1;
+ uint32_t push_pull : 1;
+ uint32_t : 26;
+} mxc_ioman_i2cm1_req_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t core_io_ack : 1;
+ uint32_t : 27;
+} mxc_ioman_i2cm1_ack_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t core_io_req : 1;
+ uint32_t push_pull : 1;
+ uint32_t : 26;
+} mxc_ioman_i2cm2_req_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t core_io_ack : 1;
+ uint32_t : 27;
+} mxc_ioman_i2cm2_ack_t;
+
+typedef struct {
+ uint32_t mapping_req : 2;
+ uint32_t : 2;
+ uint32_t core_io_req : 1;
+ uint32_t : 27;
+} mxc_ioman_i2cs_req_t;
+
+typedef struct {
+ uint32_t mapping_ack : 2;
+ uint32_t : 2;
+ uint32_t core_io_ack : 1;
+ uint32_t : 27;
+} mxc_ioman_i2cs_acl_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t core_io_req : 1;
+ uint32_t : 3;
+ uint32_t ss0_io_req : 1;
+ uint32_t ss1_io_req : 1;
+ uint32_t ss2_io_req : 1;
+ uint32_t ss3_io_req : 1;
+ uint32_t ss4_io_req : 1;
+ uint32_t : 7;
+ uint32_t quad_io_req : 1;
+ uint32_t : 3;
+ uint32_t fast_mode : 1;
+ uint32_t : 7;
+} mxc_ioman_spim0_req_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t core_io_ack : 1;
+ uint32_t : 3;
+ uint32_t ss0_io_ack : 1;
+ uint32_t ss1_io_ack : 1;
+ uint32_t ss2_io_ack : 1;
+ uint32_t ss3_io_ack : 1;
+ uint32_t ss4_io_ack : 1;
+ uint32_t : 7;
+ uint32_t quad_io_ack : 1;
+ uint32_t : 3;
+ uint32_t fast_mode : 1;
+ uint32_t : 7;
+} mxc_ioman_spim0_ack_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t core_io_req : 1;
+ uint32_t : 3;
+ uint32_t ss0_io_req : 1;
+ uint32_t ss1_io_req : 1;
+ uint32_t ss2_io_req : 1;
+ uint32_t : 9;
+ uint32_t quad_io_req : 1;
+ uint32_t : 3;
+ uint32_t fast_mode : 1;
+ uint32_t : 7;
+} mxc_ioman_spim1_req_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t core_io_ack : 1;
+ uint32_t : 3;
+ uint32_t ss0_io_ack : 1;
+ uint32_t ss1_io_ack : 1;
+ uint32_t ss2_io_ack : 1;
+ uint32_t : 9;
+ uint32_t quad_io_ack : 1;
+ uint32_t : 3;
+ uint32_t fast_mode : 1;
+ uint32_t : 7;
+} mxc_ioman_spim1_ack_t;
+
+typedef struct {
+ uint32_t mapping_req : 2;
+ uint32_t : 2;
+ uint32_t core_io_req : 1;
+ uint32_t : 3;
+ uint32_t ss0_io_req : 1;
+ uint32_t ss1_io_req : 1;
+ uint32_t ss2_io_req : 1;
+ uint32_t : 5;
+ uint32_t sr0_io_req : 1;
+ uint32_t sr1_io_req : 1;
+ uint32_t : 2;
+ uint32_t quad_io_req : 1;
+ uint32_t : 3;
+ uint32_t fast_mode : 1;
+ uint32_t : 7;
+} mxc_ioman_spim2_req_t;
+
+typedef struct {
+ uint32_t mapping_ack : 2;
+ uint32_t : 2;
+ uint32_t core_io_ack : 1;
+ uint32_t : 3;
+ uint32_t ss0_io_ack : 1;
+ uint32_t ss1_io_ack : 1;
+ uint32_t ss2_io_ack : 1;
+ uint32_t : 5;
+ uint32_t sr0_io_req : 1;
+ uint32_t sr1_io_req : 1;
+ uint32_t : 2;
+ uint32_t quad_io_ack : 1;
+ uint32_t : 3;
+ uint32_t fast_mode : 1;
+ uint32_t : 7;
+} mxc_ioman_spim2_ack_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t core_io_req : 1;
+ uint32_t : 3;
+ uint32_t quad_io_req : 1;
+ uint32_t : 3;
+ uint32_t fast_mode : 1;
+ uint32_t : 19;
+} mxc_ioman_spib_req_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t core_io_ack : 1;
+ uint32_t : 3;
+ uint32_t quad_io_ack : 1;
+ uint32_t : 3;
+ uint32_t fast_mode : 1;
+ uint32_t : 19;
+} mxc_ioman_spib_ack_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t mapping_req : 1;
+ uint32_t epu_io_req : 1;
+ uint32_t : 26;
+} mxc_ioman_owm_req_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t mapping_ack : 1;
+ uint32_t epu_io_ack : 1;
+ uint32_t : 26;
+} mxc_ioman_owm_ack_t;
+
+typedef struct {
+ uint32_t mapping_req : 2;
+ uint32_t : 2;
+ uint32_t core_io_req : 1;
+ uint32_t : 3;
+ uint32_t quad_io_req : 1;
+ uint32_t : 3;
+ uint32_t fast_mode : 1;
+ uint32_t : 19;
+} mxc_ioman_spis_req_t;
+
+typedef struct {
+ uint32_t mapping_ack : 2;
+ uint32_t : 2;
+ uint32_t core_io_ack : 1;
+ uint32_t : 3;
+ uint32_t quad_io_ack : 1;
+ uint32_t : 3;
+ uint32_t fast_mode : 1;
+ uint32_t : 19;
+} mxc_ioman_spis_ack_t;
+
+typedef struct {
+ uint32_t slow_mode : 1;
+ uint32_t alt_rcvr_mode : 1;
+ uint32_t : 30;
+} mxc_ioman_pad_mode_t;
+
+typedef struct {
+ uint32_t wud_req_p8 : 2;
+ uint32_t : 30;
+} mxc_ioman_wud_req2_t;
+
+typedef struct {
+ uint32_t wud_ack_p8 : 2;
+ uint32_t : 30;
+} mxc_ioman_wud_ack2_t;
+
+typedef struct {
+ uint32_t ali_req_p8 : 2;
+ uint32_t : 30;
+} mxc_ioman_ali_req2_t;
+
+typedef struct {
+ uint32_t ali_ack_p8 : 2;
+ uint32_t : 30;
+} mxc_ioman_ali_ack2_t;
+
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __IO uint32_t wud_req0; /* 0x0000 Wakeup Detect Mode Request Register 0 (P0/P1/P2/P3) */
+ __IO uint32_t wud_req1; /* 0x0004 Wakeup Detect Mode Request Register 1 (P4/P5/P6/P7) */
+ __IO uint32_t wud_ack0; /* 0x0008 Wakeup Detect Mode Acknowledge Register 0 (P0/P1/P2/P3) */
+ __IO uint32_t wud_ack1; /* 0x000C Wakeup Detect Mode Acknowledge Register 1 (P4/P5/P6/P7) */
+ __IO uint32_t ali_req0; /* 0x0010 Analog Input Request Register 0 (P0/P1/P2/P3) */
+ __IO uint32_t ali_req1; /* 0x0014 Analog Input Request Register 1 (P4/P5/P6/P7) */
+ __IO uint32_t ali_ack0; /* 0x0018 Analog Input Acknowledge Register 0 (P0/P1/P2/P3) */
+ __IO uint32_t ali_ack1; /* 0x001C Analog Input Acknowledge Register 1 (P4/P5/P6/P7) */
+ __IO uint32_t ali_connect0; /* 0x0020 Analog I/O Connection Control Register 0 */
+ __IO uint32_t ali_connect1; /* 0x0024 Analog I/O Connection Control Register 1 */
+ __IO uint32_t spix_req; /* 0x0028 SPIX I/O Mode Request */
+ __IO uint32_t spix_ack; /* 0x002C SPIX I/O Mode Acknowledge */
+ __IO uint32_t uart0_req; /* 0x0030 UART0 I/O Mode Request */
+ __IO uint32_t uart0_ack; /* 0x0034 UART0 I/O Mode Acknowledge */
+ __IO uint32_t uart1_req; /* 0x0038 UART1 I/O Mode Request */
+ __IO uint32_t uart1_ack; /* 0x003C UART1 I/O Mode Acknowledge */
+ __IO uint32_t uart2_req; /* 0x0040 UART2 I/O Mode Request */
+ __IO uint32_t uart2_ack; /* 0x0044 UART2 I/O Mode Acknowledge */
+ __IO uint32_t uart3_req; /* 0x0048 UART3 I/O Mode Request */
+ __IO uint32_t uart3_ack; /* 0x004C UART3 I/O Mode Acknowledge */
+ __IO uint32_t i2cm0_req; /* 0x0050 I2C Master 0 I/O Request */
+ __IO uint32_t i2cm0_ack; /* 0x0054 I2C Master 0 I/O Acknowledge */
+ __IO uint32_t i2cm1_req; /* 0x0058 I2C Master 1 I/O Request */
+ __IO uint32_t i2cm1_ack; /* 0x005C I2C Master 1 I/O Acknowledge */
+ __IO uint32_t i2cm2_req; /* 0x0060 I2C Master 2 I/O Request */
+ __IO uint32_t i2cm2_ack; /* 0x0064 I2C Master 2 I/O Acknowledge */
+ __IO uint32_t i2cs_req; /* 0x0068 I2C Slave I/O Request */
+ __IO uint32_t i2cs_ack; /* 0x006C I2C Slave I/O Acknowledge */
+ __IO uint32_t spim0_req; /* 0x0070 SPI Master 0 I/O Mode Request */
+ __IO uint32_t spim0_ack; /* 0x0074 SPI Master 0 I/O Mode Acknowledge */
+ __IO uint32_t spim1_req; /* 0x0078 SPI Master 1 I/O Mode Request */
+ __IO uint32_t spim1_ack; /* 0x007C SPI Master 1 I/O Mode Acknowledge */
+ __IO uint32_t spim2_req; /* 0x0080 SPI Master 2 I/O Mode Request */
+ __IO uint32_t spim2_ack; /* 0x0084 SPI Master 2 I/O Mode Acknowledge */
+ __IO uint32_t spib_req; /* 0x0088 SPI Bridge I/O Mode Request */
+ __IO uint32_t spib_ack; /* 0x008C SPI Bridge I/O Mode Acknowledge */
+ __IO uint32_t owm_req; /* 0x0090 1-Wire Master I/O Mode Request */
+ __IO uint32_t owm_ack; /* 0x0094 1-Wire Master I/O Mode Acknowledge */
+ __IO uint32_t spis_req; /* 0x0098 SPI Slave I/O Mode Request */
+ __IO uint32_t spis_ack; /* 0x009C SPI Slave I/O Mode Acknowledge */
+ __R uint32_t rsv0A0[24]; /* 0x00A0-0x00FC */
+ __IO uint32_t use_vddioh_0; /* 0x0100 Enable VDDIOH Register 0 */
+ __IO uint32_t use_vddioh_1; /* 0x0104 Enable VDDIOH Register 1 */
+ __IO uint32_t use_vddioh_2; /* 0x0108 Enable VDDIOH Register 2 */
+ __R uint32_t rsv10C; /* 0x010C */
+ __IO uint32_t pad_mode; /* 0x0110 Pad Mode Control Register */
+ __R uint32_t rsv114[27]; /* 0x0114-0x017C */
+ __IO uint32_t wud_req2; /* 0x0180 Wakeup Detect Mode Request Register 2 (P8) */
+ __R uint32_t rsv184; /* 0x0184 */
+ __IO uint32_t wud_ack2; /* 0x0188 Wakeup Detect Mode Acknowledge Register 2 (P8) */
+ __R uint32_t rsv18C; /* 0x018C */
+ __IO uint32_t ali_req2; /* 0x0190 Analog Input Request Register 2 (P8) */
+ __R uint32_t rsv194; /* 0x0194 */
+ __IO uint32_t ali_ack2; /* 0x0198 Analog Input Acknowledge Register 2 (P8) */
+ __R uint32_t rsv19C; /* 0x019C */
+ __IO uint32_t ali_connect2; /* 0x01A0 Analog I/O Connection Control Register 2 */
+} mxc_ioman_regs_t;
+
+
+/*
+ Register offsets for module IOMAN.
+*/
+
+#define MXC_R_IOMAN_OFFS_WUD_REQ0 ((uint32_t)0x00000000UL)
+#define MXC_R_IOMAN_OFFS_WUD_REQ1 ((uint32_t)0x00000004UL)
+#define MXC_R_IOMAN_OFFS_WUD_ACK0 ((uint32_t)0x00000008UL)
+#define MXC_R_IOMAN_OFFS_WUD_ACK1 ((uint32_t)0x0000000CUL)
+#define MXC_R_IOMAN_OFFS_ALI_REQ0 ((uint32_t)0x00000010UL)
+#define MXC_R_IOMAN_OFFS_ALI_REQ1 ((uint32_t)0x00000014UL)
+#define MXC_R_IOMAN_OFFS_ALI_ACK0 ((uint32_t)0x00000018UL)
+#define MXC_R_IOMAN_OFFS_ALI_ACK1 ((uint32_t)0x0000001CUL)
+#define MXC_R_IOMAN_OFFS_ALI_CONNECT0 ((uint32_t)0x00000020UL)
+#define MXC_R_IOMAN_OFFS_ALI_CONNECT1 ((uint32_t)0x00000024UL)
+#define MXC_R_IOMAN_OFFS_SPIX_REQ ((uint32_t)0x00000028UL)
+#define MXC_R_IOMAN_OFFS_SPIX_ACK ((uint32_t)0x0000002CUL)
+#define MXC_R_IOMAN_OFFS_UART0_REQ ((uint32_t)0x00000030UL)
+#define MXC_R_IOMAN_OFFS_UART0_ACK ((uint32_t)0x00000034UL)
+#define MXC_R_IOMAN_OFFS_UART1_REQ ((uint32_t)0x00000038UL)
+#define MXC_R_IOMAN_OFFS_UART1_ACK ((uint32_t)0x0000003CUL)
+#define MXC_R_IOMAN_OFFS_UART2_REQ ((uint32_t)0x00000040UL)
+#define MXC_R_IOMAN_OFFS_UART2_ACK ((uint32_t)0x00000044UL)
+#define MXC_R_IOMAN_OFFS_UART3_REQ ((uint32_t)0x00000048UL)
+#define MXC_R_IOMAN_OFFS_UART3_ACK ((uint32_t)0x0000004CUL)
+#define MXC_R_IOMAN_OFFS_I2CM0_REQ ((uint32_t)0x00000050UL)
+#define MXC_R_IOMAN_OFFS_I2CM0_ACK ((uint32_t)0x00000054UL)
+#define MXC_R_IOMAN_OFFS_I2CM1_REQ ((uint32_t)0x00000058UL)
+#define MXC_R_IOMAN_OFFS_I2CM1_ACK ((uint32_t)0x0000005CUL)
+#define MXC_R_IOMAN_OFFS_I2CM2_REQ ((uint32_t)0x00000060UL)
+#define MXC_R_IOMAN_OFFS_I2CM2_ACK ((uint32_t)0x00000064UL)
+#define MXC_R_IOMAN_OFFS_I2CS_REQ ((uint32_t)0x00000068UL)
+#define MXC_R_IOMAN_OFFS_I2CS_ACK ((uint32_t)0x0000006CUL)
+#define MXC_R_IOMAN_OFFS_SPIM0_REQ ((uint32_t)0x00000070UL)
+#define MXC_R_IOMAN_OFFS_SPIM0_ACK ((uint32_t)0x00000074UL)
+#define MXC_R_IOMAN_OFFS_SPIM1_REQ ((uint32_t)0x00000078UL)
+#define MXC_R_IOMAN_OFFS_SPIM1_ACK ((uint32_t)0x0000007CUL)
+#define MXC_R_IOMAN_OFFS_SPIM2_REQ ((uint32_t)0x00000080UL)
+#define MXC_R_IOMAN_OFFS_SPIM2_ACK ((uint32_t)0x00000084UL)
+#define MXC_R_IOMAN_OFFS_SPIB_REQ ((uint32_t)0x00000088UL)
+#define MXC_R_IOMAN_OFFS_SPIB_ACK ((uint32_t)0x0000008CUL)
+#define MXC_R_IOMAN_OFFS_OWM_REQ ((uint32_t)0x00000090UL)
+#define MXC_R_IOMAN_OFFS_OWM_ACK ((uint32_t)0x00000094UL)
+#define MXC_R_IOMAN_OFFS_SPIS_REQ ((uint32_t)0x00000098UL)
+#define MXC_R_IOMAN_OFFS_SPIS_ACK ((uint32_t)0x0000009CUL)
+#define MXC_R_IOMAN_OFFS_USE_VDDIOH_0 ((uint32_t)0x00000100UL)
+#define MXC_R_IOMAN_OFFS_USE_VDDIOH_1 ((uint32_t)0x00000104UL)
+#define MXC_R_IOMAN_OFFS_USE_VDDIOH_2 ((uint32_t)0x00000108UL)
+#define MXC_R_IOMAN_OFFS_PAD_MODE ((uint32_t)0x00000110UL)
+#define MXC_R_IOMAN_OFFS_WUD_REQ2 ((uint32_t)0x00000180UL)
+#define MXC_R_IOMAN_OFFS_WUD_ACK2 ((uint32_t)0x00000188UL)
+#define MXC_R_IOMAN_OFFS_ALI_REQ2 ((uint32_t)0x00000190UL)
+#define MXC_R_IOMAN_OFFS_ALI_ACK2 ((uint32_t)0x00000198UL)
+#define MXC_R_IOMAN_OFFS_ALI_CONNECT2 ((uint32_t)0x000001A0UL)
+
+
+/*
+ Field positions and masks for module IOMAN.
+*/
+
+#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0_POS 0
+#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0_POS))
+#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1_POS 8
+#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1_POS))
+#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2_POS 16
+#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2_POS))
+#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3_POS 24
+#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3_POS))
+
+#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4_POS 0
+#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4_POS))
+#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P5_POS 8
+#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P5_POS))
+#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P6_POS 16
+#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P6_POS))
+#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P7_POS 24
+#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P7_POS))
+
+#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0_POS 0
+#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0_POS))
+#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1_POS 8
+#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1_POS))
+#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2_POS 16
+#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2_POS))
+#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3_POS 24
+#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3_POS))
+
+#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4_POS 0
+#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4_POS))
+#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P5_POS 8
+#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P5_POS))
+#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P6_POS 16
+#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P6_POS))
+#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P7_POS 24
+#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P7_POS))
+
+#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0_POS 0
+#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0_POS))
+#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1_POS 8
+#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1_POS))
+#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2_POS 16
+#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2_POS))
+#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3_POS 24
+#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3_POS))
+
+#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4_POS 0
+#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4_POS))
+#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P5_POS 8
+#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P5_POS))
+#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P6_POS 16
+#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P6_POS))
+#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P7_POS 24
+#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P7_POS))
+
+#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0_POS 0
+#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0_POS))
+#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1_POS 8
+#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1_POS))
+#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2_POS 16
+#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2_POS))
+#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3_POS 24
+#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3_POS))
+
+#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4_POS 0
+#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4_POS))
+#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P5_POS 8
+#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P5_POS))
+#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P6_POS 16
+#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P6_POS))
+#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P7_POS 24
+#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P7_POS))
+
+#define MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ_POS 4
+#define MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ_POS 8
+#define MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ_POS 9
+#define MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ_POS 10
+#define MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ_POS 12
+#define MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIX_REQ_FAST_MODE_POS 16
+#define MXC_F_IOMAN_SPIX_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK_POS 4
+#define MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK_POS 8
+#define MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK_POS 9
+#define MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK_POS 10
+#define MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK_POS 12
+#define MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIX_ACK_FAST_MODE_POS 16
+#define MXC_F_IOMAN_SPIX_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_UART0_REQ_IO_MAP_POS 0
+#define MXC_F_IOMAN_UART0_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_MAP_POS))
+#define MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS 1
+#define MXC_F_IOMAN_UART0_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS))
+#define MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS 2
+#define MXC_F_IOMAN_UART0_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS))
+#define MXC_F_IOMAN_UART0_REQ_IO_REQ_POS 4
+#define MXC_F_IOMAN_UART0_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_REQ_POS))
+#define MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ_POS 5
+#define MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ_POS))
+#define MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ_POS 6
+#define MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ_POS))
+
+#define MXC_F_IOMAN_UART0_ACK_IO_MAP_POS 0
+#define MXC_F_IOMAN_UART0_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_MAP_POS))
+#define MXC_F_IOMAN_UART0_ACK_CTS_MAP_POS 1
+#define MXC_F_IOMAN_UART0_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_MAP_POS))
+#define MXC_F_IOMAN_UART0_ACK_RTS_MAP_POS 2
+#define MXC_F_IOMAN_UART0_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_MAP_POS))
+#define MXC_F_IOMAN_UART0_ACK_IO_ACK_POS 4
+#define MXC_F_IOMAN_UART0_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_ACK_POS))
+#define MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK_POS 5
+#define MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK_POS))
+#define MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK_POS 6
+#define MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK_POS))
+
+#define MXC_F_IOMAN_UART1_REQ_IO_MAP_POS 0
+#define MXC_F_IOMAN_UART1_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_IO_MAP_POS))
+#define MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS 1
+#define MXC_F_IOMAN_UART1_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS))
+#define MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS 2
+#define MXC_F_IOMAN_UART1_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS))
+#define MXC_F_IOMAN_UART1_REQ_IO_REQ_POS 4
+#define MXC_F_IOMAN_UART1_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_IO_REQ_POS))
+#define MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ_POS 5
+#define MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ_POS))
+#define MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ_POS 6
+#define MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ_POS))
+
+#define MXC_F_IOMAN_UART1_ACK_IO_MAP_POS 0
+#define MXC_F_IOMAN_UART1_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_IO_MAP_POS))
+#define MXC_F_IOMAN_UART1_ACK_CTS_MAP_POS 1
+#define MXC_F_IOMAN_UART1_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_CTS_MAP_POS))
+#define MXC_F_IOMAN_UART1_ACK_RTS_MAP_POS 2
+#define MXC_F_IOMAN_UART1_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_RTS_MAP_POS))
+#define MXC_F_IOMAN_UART1_ACK_IO_ACK_POS 4
+#define MXC_F_IOMAN_UART1_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_IO_ACK_POS))
+#define MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK_POS 5
+#define MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK_POS))
+#define MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK_POS 6
+#define MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK_POS))
+
+#define MXC_F_IOMAN_UART2_REQ_IO_MAP_POS 0
+#define MXC_F_IOMAN_UART2_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_IO_MAP_POS))
+#define MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS 1
+#define MXC_F_IOMAN_UART2_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS))
+#define MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS 2
+#define MXC_F_IOMAN_UART2_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS))
+#define MXC_F_IOMAN_UART2_REQ_IO_REQ_POS 4
+#define MXC_F_IOMAN_UART2_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_IO_REQ_POS))
+#define MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ_POS 5
+#define MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ_POS))
+#define MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ_POS 6
+#define MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ_POS))
+
+#define MXC_F_IOMAN_UART2_ACK_IO_MAP_POS 0
+#define MXC_F_IOMAN_UART2_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_IO_MAP_POS))
+#define MXC_F_IOMAN_UART2_ACK_CTS_MAP_POS 1
+#define MXC_F_IOMAN_UART2_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_CTS_MAP_POS))
+#define MXC_F_IOMAN_UART2_ACK_RTS_MAP_POS 2
+#define MXC_F_IOMAN_UART2_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_RTS_MAP_POS))
+#define MXC_F_IOMAN_UART2_ACK_IO_ACK_POS 4
+#define MXC_F_IOMAN_UART2_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_IO_ACK_POS))
+#define MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK_POS 5
+#define MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK_POS))
+#define MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK_POS 6
+#define MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK_POS))
+
+#define MXC_F_IOMAN_UART3_REQ_IO_MAP_POS 0
+#define MXC_F_IOMAN_UART3_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_IO_MAP_POS))
+#define MXC_F_IOMAN_UART3_REQ_CTS_MAP_POS 1
+#define MXC_F_IOMAN_UART3_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_CTS_MAP_POS))
+#define MXC_F_IOMAN_UART3_REQ_RTS_MAP_POS 2
+#define MXC_F_IOMAN_UART3_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_RTS_MAP_POS))
+#define MXC_F_IOMAN_UART3_REQ_IO_REQ_POS 4
+#define MXC_F_IOMAN_UART3_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_IO_REQ_POS))
+#define MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ_POS 5
+#define MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ_POS))
+#define MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ_POS 6
+#define MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ_POS))
+
+#define MXC_F_IOMAN_UART3_ACK_IO_MAP_POS 0
+#define MXC_F_IOMAN_UART3_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_IO_MAP_POS))
+#define MXC_F_IOMAN_UART3_ACK_CTS_MAP_POS 1
+#define MXC_F_IOMAN_UART3_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_CTS_MAP_POS))
+#define MXC_F_IOMAN_UART3_ACK_RTS_MAP_POS 2
+#define MXC_F_IOMAN_UART3_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_RTS_MAP_POS))
+#define MXC_F_IOMAN_UART3_ACK_IO_ACK_POS 4
+#define MXC_F_IOMAN_UART3_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_IO_ACK_POS))
+#define MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK_POS 5
+#define MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK_POS))
+#define MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK_POS 6
+#define MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK_POS))
+
+#define MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ_POS 4
+#define MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ_POS))
+
+#define MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK_POS 4
+#define MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK_POS))
+
+#define MXC_F_IOMAN_I2CM1_REQ_IO_SEL_POS 0
+#define MXC_F_IOMAN_I2CM1_REQ_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM1_REQ_IO_SEL_POS))
+#define MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ_POS 4
+#define MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ_POS))
+
+#define MXC_F_IOMAN_I2CM1_ACK_IO_SEL_POS 0
+#define MXC_F_IOMAN_I2CM1_ACK_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM1_ACK_IO_SEL_POS))
+#define MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK_POS 4
+#define MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK_POS))
+
+#define MXC_F_IOMAN_I2CM2_REQ_IO_SEL_POS 0
+#define MXC_F_IOMAN_I2CM2_REQ_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM2_REQ_IO_SEL_POS))
+#define MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ_POS 4
+#define MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ_POS))
+
+#define MXC_F_IOMAN_I2CM2_ACK_IO_SEL_POS 0
+#define MXC_F_IOMAN_I2CM2_ACK_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM2_ACK_IO_SEL_POS))
+#define MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK_POS 4
+#define MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK_POS))
+
+#define MXC_F_IOMAN_I2CS_REQ_IO_SEL_POS 0
+#define MXC_F_IOMAN_I2CS_REQ_IO_SEL ((uint32_t)(0x00000007UL << MXC_F_IOMAN_I2CS_REQ_IO_SEL_POS))
+#define MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ_POS 4
+#define MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ_POS))
+
+#define MXC_F_IOMAN_I2CS_ACK_IO_SEL_POS 0
+#define MXC_F_IOMAN_I2CS_ACK_IO_SEL ((uint32_t)(0x00000007UL << MXC_F_IOMAN_I2CS_ACK_IO_SEL_POS))
+#define MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK_POS 4
+#define MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK_POS))
+
+#define MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ_POS 4
+#define MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ_POS 8
+#define MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ_POS 9
+#define MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ_POS 10
+#define MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ_POS 11
+#define MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ_POS 12
+#define MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ_POS 20
+#define MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM0_REQ_FAST_MODE_POS 24
+#define MXC_F_IOMAN_SPIM0_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK_POS 4
+#define MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK_POS 8
+#define MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK_POS 9
+#define MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK_POS 10
+#define MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK_POS 11
+#define MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK_POS 12
+#define MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK_POS 20
+#define MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM0_ACK_FAST_MODE_POS 24
+#define MXC_F_IOMAN_SPIM0_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ_POS 4
+#define MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ_POS 8
+#define MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ_POS 9
+#define MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ_POS 10
+#define MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ_POS 20
+#define MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM1_REQ_FAST_MODE_POS 24
+#define MXC_F_IOMAN_SPIM1_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK_POS 4
+#define MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK_POS 8
+#define MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK_POS 9
+#define MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK_POS 10
+#define MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK_POS 20
+#define MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM1_ACK_FAST_MODE_POS 24
+#define MXC_F_IOMAN_SPIM1_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ_POS 0
+#define MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ_POS 4
+#define MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ_POS 8
+#define MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ_POS 9
+#define MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ_POS 10
+#define MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ_POS 16
+#define MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ_POS 17
+#define MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_REQ_QUAD_IO_REQ_POS 20
+#define MXC_F_IOMAN_SPIM2_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_QUAD_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_REQ_FAST_MODE_POS 24
+#define MXC_F_IOMAN_SPIM2_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK_POS 0
+#define MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK_POS))
+#define MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK_POS 4
+#define MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK_POS 8
+#define MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK_POS 9
+#define MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK_POS 10
+#define MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM2_ACK_SR0_IO_REQ_POS 16
+#define MXC_F_IOMAN_SPIM2_ACK_SR0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SR0_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_ACK_SR1_IO_REQ_POS 17
+#define MXC_F_IOMAN_SPIM2_ACK_SR1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SR1_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_ACK_QUAD_IO_ACK_POS 20
+#define MXC_F_IOMAN_SPIM2_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_QUAD_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM2_ACK_FAST_MODE_POS 24
+#define MXC_F_IOMAN_SPIM2_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_SPIB_REQ_CORE_IO_REQ_POS 4
+#define MXC_F_IOMAN_SPIB_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_REQ_CORE_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIB_REQ_QUAD_IO_REQ_POS 8
+#define MXC_F_IOMAN_SPIB_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_REQ_QUAD_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIB_REQ_FAST_MODE_POS 12
+#define MXC_F_IOMAN_SPIB_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_REQ_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_SPIB_ACK_CORE_IO_ACK_POS 4
+#define MXC_F_IOMAN_SPIB_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_ACK_CORE_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIB_ACK_QUAD_IO_ACK_POS 8
+#define MXC_F_IOMAN_SPIB_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_ACK_QUAD_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIB_ACK_FAST_MODE_POS 12
+#define MXC_F_IOMAN_SPIB_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_ACK_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_OWM_REQ_MAPPING_REQ_POS 4
+#define MXC_F_IOMAN_OWM_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_REQ_MAPPING_REQ_POS))
+#define MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ_POS 5
+#define MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ_POS))
+
+#define MXC_F_IOMAN_OWM_ACK_MAPPING_ACK_POS 4
+#define MXC_F_IOMAN_OWM_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_ACK_MAPPING_ACK_POS))
+#define MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK_POS 5
+#define MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK_POS))
+
+#define MXC_F_IOMAN_SPIS_REQ_MAPPING_REQ_POS 0
+#define MXC_F_IOMAN_SPIS_REQ_MAPPING_REQ ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIS_REQ_MAPPING_REQ_POS))
+#define MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ_POS 4
+#define MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ_POS 8
+#define MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIS_REQ_FAST_MODE_POS 12
+#define MXC_F_IOMAN_SPIS_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_SPIS_ACK_MAPPING_ACK_POS 0
+#define MXC_F_IOMAN_SPIS_ACK_MAPPING_ACK ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIS_ACK_MAPPING_ACK_POS))
+#define MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK_POS 4
+#define MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK_POS 8
+#define MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIS_ACK_FAST_MODE_POS 12
+#define MXC_F_IOMAN_SPIS_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_PAD_MODE_SLOW_MODE_POS 0
+#define MXC_F_IOMAN_PAD_MODE_SLOW_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PAD_MODE_SLOW_MODE_POS))
+#define MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE_POS 1
+#define MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE_POS))
+
+#define MXC_F_IOMAN_WUD_REQ2_WUD_REQ_P8_POS 0
+#define MXC_F_IOMAN_WUD_REQ2_WUD_REQ_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_WUD_REQ2_WUD_REQ_P8_POS))
+
+#define MXC_F_IOMAN_WUD_ACK2_WUD_ACK_P8_POS 0
+#define MXC_F_IOMAN_WUD_ACK2_WUD_ACK_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_WUD_ACK2_WUD_ACK_P8_POS))
+
+#define MXC_F_IOMAN_ALI_REQ2_ALI_REQ_P8_POS 0
+#define MXC_F_IOMAN_ALI_REQ2_ALI_REQ_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_ALI_REQ2_ALI_REQ_P8_POS))
+
+#define MXC_F_IOMAN_ALI_ACK2_ALI_ACK_P8_POS 0
+#define MXC_F_IOMAN_ALI_ACK2_ALI_ACK_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_ALI_ACK2_ALI_ACK_P8_POS))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_IOMAN_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/max32620.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32620/max32620.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,836 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#ifndef _MAX32620_H_
+#define _MAX32620_H_
+
+#include <stdint.h>
+
+#ifndef FALSE
+#define FALSE (0)
+#endif
+
+#ifndef TRUE
+#define TRUE (1)
+#endif
+
+#if !defined (__GNUC__)
+#define CMSIS_VECTAB_VIRTUAL
+#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "nvic_table.h"
+#endif /* !__GNUC__ */
+
+/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
+#if defined ( __GNUC__ )
+#define __weak __attribute__((weak))
+
+#elif defined ( __CC_ARM)
+
+#define inline __inline
+#pragma anon_unions
+
+#endif
+
+typedef enum {
+ NonMaskableInt_IRQn = -14,
+ HardFault_IRQn = -13,
+ MemoryManagement_IRQn = -12,
+ BusFault_IRQn = -11,
+ UsageFault_IRQn = -10,
+ SVCall_IRQn = -5,
+ DebugMonitor_IRQn = -4,
+ PendSV_IRQn = -2,
+ SysTick_IRQn = -1,
+
+ /* Device-specific interrupt sources (external to ARM core) */
+ /* table entry number */
+ /* |||| */
+ /* |||| table offset address */
+ /* vvvv vvvvvv */
+
+ CLKMAN_IRQn = 0, /* 0x10 0x0040 CLKMAN */
+ PWRMAN_IRQn, /* 0x11 0x0044 PWRMAN */
+ FLC_IRQn, /* 0x12 0x0048 Flash Controller */
+ RTC0_IRQn, /* 0x13 0x004C RTC Counter match with Compare 0 */
+ RTC1_IRQn, /* 0x14 0x0050 RTC Counter match with Compare 1 */
+ RTC2_IRQn, /* 0x15 0x0054 RTC Prescaler interval compare match */
+ RTC3_IRQn, /* 0x16 0x0058 RTC Overflow */
+ PMU_IRQn, /* 0x17 0x005C Peripheral Management Unit (PMU/DMA) */
+ USB_IRQn, /* 0x18 0x0060 USB */
+ AES_IRQn, /* 0x19 0x0064 AES */
+ MAA_IRQn, /* 0x1A 0x0068 MAA */
+ WDT0_IRQn, /* 0x1B 0x006C Watchdog 0 timeout */
+ WDT0_P_IRQn, /* 0x1C 0x0070 Watchdog 0 pre-window (fed too early) */
+ WDT1_IRQn, /* 0x1D 0x0074 Watchdog 1 timeout */
+ WDT1_P_IRQn, /* 0x1E 0x0078 Watchdog 1 pre-window (fed too early) */
+ GPIO_P0_IRQn, /* 0x1F 0x007C GPIO Port 0 */
+ GPIO_P1_IRQn, /* 0x20 0x0080 GPIO Port 1 */
+ GPIO_P2_IRQn, /* 0x21 0x0084 GPIO Port 2 */
+ GPIO_P3_IRQn, /* 0x22 0x0088 GPIO Port 3 */
+ GPIO_P4_IRQn, /* 0x23 0x008C GPIO Port 4 */
+ GPIO_P5_IRQn, /* 0x24 0x0090 GPIO Port 5 */
+ GPIO_P6_IRQn, /* 0x25 0x0094 GPIO Port 6 */
+ TMR0_0_IRQn, /* 0x26 0x0098 Timer 0 (32-bit, 16-bit #0) */
+ TMR0_1_IRQn, /* 0x27 0x009C Timer 0 (16-bit #1) */
+ TMR1_0_IRQn, /* 0x28 0x00A0 Timer 1 (32-bit, 16-bit #0) */
+ TMR1_1_IRQn, /* 0x29 0x00A4 Timer 1 (16-bit #1) */
+ TMR2_0_IRQn, /* 0x2A 0x00A8 Timer 2 (32-bit, 16-bit #0) */
+ TMR2_1_IRQn, /* 0x2B 0x00AC Timer 2 (16-bit #1) */
+ TMR3_0_IRQn, /* 0x2C 0x00B0 Timer 3 (32-bit, 16-bit #0) */
+ TMR3_1_IRQn, /* 0x2D 0x00B4 Timer 3 (16-bit #1) */
+ TMR4_0_IRQn, /* 0x2E 0x00B8 Timer 4 (32-bit, 16-bit #0) */
+ TMR4_1_IRQn, /* 0x2F 0x00BC Timer 4 (16-bit #1) */
+ TMR5_0_IRQn, /* 0x30 0x00C0 Timer 5 (32-bit, 16-bit #0) */
+ TMR5_1_IRQn, /* 0x31 0x00C4 Timer 5 (16-bit #1) */
+ UART0_IRQn, /* 0x32 0x00C8 UART 0 */
+ UART1_IRQn, /* 0x33 0x00CC UART 1 */
+ UART2_IRQn, /* 0x34 0x00D0 UART 2 */
+ UART3_IRQn, /* 0x35 0x00D4 UART 3 */
+ PT_IRQn, /* 0x36 0x00D8 Pulse Trains */
+ I2CM0_IRQn, /* 0x37 0x00DC I2C Master 0 */
+ I2CM1_IRQn, /* 0x38 0x00E0 I2C Master 1 */
+ I2CM2_IRQn, /* 0x39 0x00E4 I2C Master 2 */
+ I2CS_IRQn, /* 0x3A 0x00E8 I2C Slave */
+ SPIM0_IRQn, /* 0x3B 0x00EC SPI Master 0 */
+ SPIM1_IRQn, /* 0x3C 0x00F0 SPI Master 1 */
+ SPIM2_IRQn, /* 0x3D 0x00F4 SPI Master 2 */
+ SPIB_IRQn, /* 0x3E 0x00F8 SPI Bridge */
+ OWM_IRQn, /* 0x3F 0x00FC 1-Wire Master */
+ AFE_IRQn, /* 0x40 0x0100 Analog Front End, ADC */
+ SPIS_IRQn, /* 0x41 0x0104 SPI Slave */
+ GPIO_P7_IRQn, /* 0x42 0x0108 GPIO Port 7 */
+ GPIO_P8_IRQn, /* 0x43 0x010C GPIO Port 8 */
+ MXC_IRQ_EXT_COUNT,
+} IRQn_Type;
+
+#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
+
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+/* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */
+#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< FPU present or not */
+
+#include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */
+#include "system_max32620.h" /*!< System Header */
+
+
+/* ================================================================================ */
+/* ================== Device Specific Memory Section ================== */
+/* ================================================================================ */
+
+#define MXC_FLASH_MEM_BASE 0x00000000UL
+#define MXC_FLASH_PAGE_SIZE 0x00002000UL
+#define MXC_FLASH_FULL_MEM_SIZE 0x00200000UL
+#define MXC_SYS_MEM_BASE 0x20000000UL
+#define MXC_SRAM_FULL_MEM_SIZE 0x00040000UL
+#define MXC_EXT_FLASH_MEM_BASE 0x10000000UL
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+
+
+/*
+ Base addresses and configuration settings for all MAX32620 peripheral modules.
+*/
+
+
+/*******************************************************************************/
+/* System Manager Settings */
+
+#define MXC_BASE_SYSMAN ((uint32_t)0x40000000UL)
+#define MXC_SYSMAN ((mxc_sysman_regs_t *)MXC_BASE_SYSMAN)
+
+
+
+/*******************************************************************************/
+/* System Clock Manager */
+
+#define MXC_BASE_CLKMAN ((uint32_t)0x40000400UL)
+#define MXC_CLKMAN ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN)
+
+
+
+/*******************************************************************************/
+/* System Power Manager */
+
+#define MXC_BASE_PWRMAN ((uint32_t)0x40000800UL)
+#define MXC_PWRMAN ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN)
+
+
+
+/*******************************************************************************/
+/* Real Time Clock */
+
+#define MXC_BASE_RTCTMR ((uint32_t)0x40000A00UL)
+#define MXC_RTCTMR ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR)
+#define MXC_BASE_RTCCFG ((uint32_t)0x40000A70UL)
+#define MXC_RTCCFG ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG)
+
+#define MXC_RTCTMR_GET_IRQ(i) (IRQn_Type)(i == 0 ? RTC0_IRQn : \
+ i == 1 ? RTC1_IRQn : \
+ i == 2 ? RTC2_IRQn : \
+ i == 3 ? RTC3_IRQn : 0)
+
+
+
+/*******************************************************************************/
+/* Power Sequencer */
+
+#define MXC_BASE_PWRSEQ ((uint32_t)0x40000A30UL)
+#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
+
+
+
+/*******************************************************************************/
+/* System I/O Manager */
+
+#define MXC_BASE_IOMAN ((uint32_t)0x40000C00UL)
+#define MXC_IOMAN ((mxc_ioman_regs_t *)MXC_BASE_IOMAN)
+
+
+
+/*******************************************************************************/
+/* Shadow Trim Registers */
+
+#define MXC_BASE_TRIM ((uint32_t)0x40001000UL)
+#define MXC_TRIM ((mxc_trim_regs_t *)MXC_BASE_TRIM)
+
+
+
+/*******************************************************************************/
+/* Flash Controller */
+
+#define MXC_BASE_FLC ((uint32_t)0x40002000UL)
+#define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC)
+
+#define MXC_FLC_PAGE_SIZE_SHIFT (13)
+#define MXC_FLC_PAGE_SIZE (1 << MXC_FLC_PAGE_SIZE_SHIFT)
+#define MXC_FLC_PAGE_ERASE_MSK ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT
+
+
+
+/*******************************************************************************/
+/* Instruction Cache */
+
+#define MXC_BASE_ICC ((uint32_t)0x40003000UL)
+#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC)
+
+
+
+/*******************************************************************************/
+/* SPI XIP Interface */
+
+#define MXC_BASE_SPIX ((uint32_t)0x40004000UL)
+#define MXC_SPIX ((mxc_spix_regs_t *)MXC_BASE_SPIX)
+
+
+
+/*******************************************************************************/
+/* Peripheral Management Unit */
+
+#define MXC_CFG_PMU_CHANNELS (6)
+
+#define MXC_BASE_PMU0 ((uint32_t)0x40005000UL)
+#define MXC_PMU0 ((mxc_pmu_regs_t *)MXC_BASE_PMU0)
+#define MXC_BASE_PMU1 ((uint32_t)0x40005020UL)
+#define MXC_PMU1 ((mxc_pmu_regs_t *)MXC_BASE_PMU1)
+#define MXC_BASE_PMU2 ((uint32_t)0x40005040UL)
+#define MXC_PMU2 ((mxc_pmu_regs_t *)MXC_BASE_PMU2)
+#define MXC_BASE_PMU3 ((uint32_t)0x40005060UL)
+#define MXC_PMU3 ((mxc_pmu_regs_t *)MXC_BASE_PMU3)
+#define MXC_BASE_PMU4 ((uint32_t)0x40005080UL)
+#define MXC_PMU4 ((mxc_pmu_regs_t *)MXC_BASE_PMU4)
+#define MXC_BASE_PMU5 ((uint32_t)0x400050A0UL)
+#define MXC_PMU5 ((mxc_pmu_regs_t *)MXC_BASE_PMU5)
+
+#define MXC_PMU_GET_BASE(i) ((i) == 0 ? MXC_BASE_PMU0 : \
+ (i) == 1 ? MXC_BASE_PMU1 : \
+ (i) == 2 ? MXC_BASE_PMU2 : \
+ (i) == 3 ? MXC_BASE_PMU3 : \
+ (i) == 4 ? MXC_BASE_PMU4 : \
+ (i) == 5 ? MXC_BASE_PMU5 : 0)
+
+#define MXC_PMU_GET_PMU(i) ((i) == 0 ? MXC_PMU0 : \
+ (i) == 1 ? MXC_PMU1 : \
+ (i) == 2 ? MXC_PMU2 : \
+ (i) == 3 ? MXC_PMU3 : \
+ (i) == 4 ? MXC_PMU4 : \
+ (i) == 5 ? MXC_PMU5 : 0)
+
+#define MXC_PMU_GET_IDX(p) ((p) == MXC_PMU0 ? 0 : \
+ (p) == MXC_PMU1 ? 1 : \
+ (p) == MXC_PMU2 ? 2 : \
+ (p) == MXC_PMU3 ? 3 : \
+ (p) == MXC_PMU4 ? 4 : \
+ (p) == MXC_PMU5 ? 5 : -1)
+
+/*******************************************************************************/
+/* USB Device Controller */
+
+#define MXC_BASE_USB ((uint32_t)0x40100000UL)
+#define MXC_USB ((mxc_usb_regs_t *)MXC_BASE_USB)
+
+#define MXC_USB_MAX_PACKET (64)
+#define MXC_USB_NUM_EP (8)
+
+
+
+/*******************************************************************************/
+/* CRC-16/CRC-32 Engine */
+
+#define MXC_BASE_CRC ((uint32_t)0x40006000UL)
+#define MXC_CRC ((mxc_crc_regs_t *)MXC_BASE_CRC)
+#define MXC_BASE_CRC_DATA ((uint32_t)0x40101000UL)
+#define MXC_CRC_DATA ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA)
+
+/*******************************************************************************/
+/* Pseudo-random number generator (PRNG) */
+
+#define MXC_BASE_PRNG ((uint32_t)0x40007000UL)
+#define MXC_PRNG ((mxc_prng_regs_t *)MXC_BASE_PRNG)
+
+/*******************************************************************************/
+/* AES Cryptographic Engine */
+
+#define MXC_BASE_AES ((uint32_t)0x40007400UL)
+#define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES)
+#define MXC_BASE_AES_MEM ((uint32_t)0x40102000UL)
+#define MXC_AES_MEM ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM)
+
+/*******************************************************************************/
+/* MAA Cryptographic Engine */
+
+#define MXC_BASE_MAA ((uint32_t)0x40007800UL)
+#define MXC_MAA ((mxc_maa_regs_t *)MXC_BASE_MAA)
+#define MXC_BASE_MAA_MEM ((uint32_t)0x40102800UL)
+#define MXC_MAA_MEM ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM)
+
+/*******************************************************************************/
+/* Trust Protection Unit (TPU) */
+
+#define MXC_BASE_TPU ((uint32_t)0x40007000UL)
+#define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU)
+#define MXC_BASE_TPU_TSR ((uint32_t)0x40007C00UL)
+#define MXC_TPU_TSR ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR)
+
+/*******************************************************************************/
+/* Watchdog Timers */
+
+#define MXC_CFG_WDT_INSTANCES (2)
+
+#define MXC_BASE_WDT0 ((uint32_t)0x40008000UL)
+#define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
+#define MXC_BASE_WDT1 ((uint32_t)0x40009000UL)
+#define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
+
+#define MXC_WDT_GET_IRQ(i) (IRQn_Type)((i) == 0 ? WDT0_IRQn : \
+ (i) == 1 ? WDT1_IRQn : 0)
+
+#define MXC_WDT_GET_IRQ_P(i) (IRQn_Type)((i) == 0 ? WDT0_P_IRQn : \
+ (i) == 1 ? WDT1_P_IRQn : 0)
+
+#define MXC_WDT_GET_BASE(i) ((i) == 0 ? MXC_BASE_WDT0 : \
+ (i) == 1 ? MXC_BASE_WDT1 : 0)
+
+#define MXC_WDT_GET_WDT(i) ((i) == 0 ? MXC_WDT0 : \
+ (i) == 1 ? MXC_WDT1 : 0)
+
+#define MXC_WDT_GET_IDX(i) ((i) == MXC_WDT0 ? 0: \
+ (i) == MXC_WDT1 ? 1: -1)
+
+
+/*******************************************************************************/
+/* Always-On Watchdog Timer */
+
+#define MXC_BASE_WDT2 ((uint32_t)0x40007C60UL)
+#define MXC_WDT2 ((mxc_wdt2_regs_t *)MXC_BASE_WDT2)
+
+
+
+/*******************************************************************************/
+/* General Purpose I/O Ports (GPIO) */
+
+#define MXC_GPIO_NUM_PORTS (7)
+#define MXC_GPIO_MAX_PINS_PER_PORT (8)
+
+#define MXC_BASE_GPIO ((uint32_t)0x4000A000UL)
+#define MXC_GPIO ((mxc_gpio_regs_t *)MXC_BASE_GPIO)
+
+#define MXC_GPIO_GET_IRQ(i) (IRQn_Type)((i) == 0 ? GPIO_P0_IRQn : \
+ (i) == 1 ? GPIO_P1_IRQn : \
+ (i) == 2 ? GPIO_P2_IRQn : \
+ (i) == 3 ? GPIO_P3_IRQn : \
+ (i) == 4 ? GPIO_P4_IRQn : \
+ (i) == 5 ? GPIO_P5_IRQn : \
+ (i) == 6 ? GPIO_P6_IRQn : \
+ (i) == 7 ? GPIO_P7_IRQn : \
+ (i) == 8 ? GPIO_P8_IRQn : 0)
+
+
+
+/*******************************************************************************/
+/* 16/32 bit Timer/Counters */
+
+#define MXC_CFG_TMR_INSTANCES (6)
+
+#define MXC_BASE_TMR0 ((uint32_t)0x4000B000UL)
+#define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0)
+#define MXC_BASE_TMR1 ((uint32_t)0x4000C000UL)
+#define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1)
+#define MXC_BASE_TMR2 ((uint32_t)0x4000D000UL)
+#define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2)
+#define MXC_BASE_TMR3 ((uint32_t)0x4000E000UL)
+#define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3)
+#define MXC_BASE_TMR4 ((uint32_t)0x4000F000UL)
+#define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4)
+#define MXC_BASE_TMR5 ((uint32_t)0x40010000UL)
+#define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5)
+
+#define MXC_TMR_GET_IRQ_32(i) (IRQn_Type)((i) == 0 ? TMR0_0_IRQn : \
+ (i) == 1 ? TMR1_0_IRQn : \
+ (i) == 2 ? TMR2_0_IRQn : \
+ (i) == 3 ? TMR3_0_IRQn : \
+ (i) == 4 ? TMR4_0_IRQn : \
+ (i) == 5 ? TMR5_0_IRQn : 0)
+
+#define MXC_TMR_GET_IRQ_16(i) (IRQn_Type)((i) == 0 ? TMR0_0_IRQn : \
+ (i) == 1 ? TMR1_0_IRQn : \
+ (i) == 2 ? TMR2_0_IRQn : \
+ (i) == 3 ? TMR3_0_IRQn : \
+ (i) == 4 ? TMR4_0_IRQn : \
+ (i) == 5 ? TMR5_0_IRQn : \
+ (i) == 6 ? TMR0_1_IRQn : \
+ (i) == 7 ? TMR1_1_IRQn : \
+ (i) == 8 ? TMR2_1_IRQn : \
+ (i) == 9 ? TMR3_1_IRQn : \
+ (i) == 10 ? TMR4_1_IRQn : \
+ (i) == 11 ? TMR5_1_IRQn : 0)
+
+#define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
+ (i) == 1 ? MXC_BASE_TMR1 : \
+ (i) == 2 ? MXC_BASE_TMR2 : \
+ (i) == 3 ? MXC_BASE_TMR3 : \
+ (i) == 4 ? MXC_BASE_TMR4 : \
+ (i) == 5 ? MXC_BASE_TMR5 : 0)
+
+#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
+ (i) == 1 ? MXC_TMR1 : \
+ (i) == 2 ? MXC_TMR2 : \
+ (i) == 3 ? MXC_TMR3 : \
+ (i) == 4 ? MXC_TMR4 : \
+ (i) == 5 ? MXC_TMR5 : 0)
+
+#define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \
+ (p) == MXC_TMR1 ? 1 : \
+ (p) == MXC_TMR2 ? 2 : \
+ (p) == MXC_TMR3 ? 3 : \
+ (p) == MXC_TMR4 ? 4 : \
+ (p) == MXC_TMR5 ? 5 : -1)
+
+
+
+
+/*******************************************************************************/
+/* Pulse Train Generation */
+
+#define MXC_CFG_PT_INSTANCES (16)
+
+#define MXC_BASE_PTG ((uint32_t)0x40011000UL)
+#define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG)
+#define MXC_BASE_PT0 ((uint32_t)0x40011020UL)
+#define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0)
+#define MXC_BASE_PT1 ((uint32_t)0x40011040UL)
+#define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1)
+#define MXC_BASE_PT2 ((uint32_t)0x40011060UL)
+#define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2)
+#define MXC_BASE_PT3 ((uint32_t)0x40011080UL)
+#define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3)
+#define MXC_BASE_PT4 ((uint32_t)0x400110A0UL)
+#define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4)
+#define MXC_BASE_PT5 ((uint32_t)0x400110C0UL)
+#define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5)
+#define MXC_BASE_PT6 ((uint32_t)0x400110E0UL)
+#define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6)
+#define MXC_BASE_PT7 ((uint32_t)0x40011100UL)
+#define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7)
+#define MXC_BASE_PT8 ((uint32_t)0x40011120UL)
+#define MXC_PT8 ((mxc_pt_regs_t *)MXC_BASE_PT8)
+#define MXC_BASE_PT9 ((uint32_t)0x40011140UL)
+#define MXC_PT9 ((mxc_pt_regs_t *)MXC_BASE_PT9)
+#define MXC_BASE_PT10 ((uint32_t)0x40011160UL)
+#define MXC_PT10 ((mxc_pt_regs_t *)MXC_BASE_PT10)
+#define MXC_BASE_PT11 ((uint32_t)0x40011180UL)
+#define MXC_PT11 ((mxc_pt_regs_t *)MXC_BASE_PT11)
+#define MXC_BASE_PT12 ((uint32_t)0x400111A0UL)
+#define MXC_PT12 ((mxc_pt_regs_t *)MXC_BASE_PT12)
+#define MXC_BASE_PT13 ((uint32_t)0x400111C0UL)
+#define MXC_PT13 ((mxc_pt_regs_t *)MXC_BASE_PT13)
+#define MXC_BASE_PT14 ((uint32_t)0x400111E0UL)
+#define MXC_PT14 ((mxc_pt_regs_t *)MXC_BASE_PT14)
+#define MXC_BASE_PT15 ((uint32_t)0x40011200UL)
+#define MXC_PT15 ((mxc_pt_regs_t *)MXC_BASE_PT15)
+
+#define MXC_PT_GET_BASE(i) ((i) == 0 ? MXC_BASE_PT0 : \
+ (i) == 1 ? MXC_BASE_PT1 : \
+ (i) == 2 ? MXC_BASE_PT2 : \
+ (i) == 3 ? MXC_BASE_PT3 : \
+ (i) == 4 ? MXC_BASE_PT4 : \
+ (i) == 5 ? MXC_BASE_PT5 : \
+ (i) == 6 ? MXC_BASE_PT6 : \
+ (i) == 7 ? MXC_BASE_PT7 : \
+ (i) == 8 ? MXC_BASE_PT8 : \
+ (i) == 9 ? MXC_BASE_PT9 : \
+ (i) == 10 ? MXC_BASE_PT10 : \
+ (i) == 11 ? MXC_BASE_PT11 : \
+ (i) == 12 ? MXC_BASE_PT12 : \
+ (i) == 13 ? MXC_BASE_PT13 : \
+ (i) == 14 ? MXC_BASE_PT14 : \
+ (i) == 15 ? MXC_BASE_PT15 : 0)
+
+#define MXC_PT_GET_PT(i) ((i) == 0 ? MXC_PT0 : \
+ (i) == 1 ? MXC_PT1 : \
+ (i) == 2 ? MXC_PT2 : \
+ (i) == 3 ? MXC_PT3 : \
+ (i) == 4 ? MXC_PT4 : \
+ (i) == 5 ? MXC_PT5 : \
+ (i) == 6 ? MXC_PT6 : \
+ (i) == 7 ? MXC_PT7 : \
+ (i) == 8 ? MXC_PT8 : \
+ (i) == 9 ? MXC_PT9 : \
+ (i) == 10 ? MXC_PT10 : \
+ (i) == 11 ? MXC_PT11 : \
+ (i) == 12 ? MXC_PT12 : \
+ (i) == 13 ? MXC_PT13 : \
+ (i) == 14 ? MXC_PT14 : \
+ (i) == 15 ? MXC_PT15 : 0)
+
+#define MXC_PT_GET_IDX(p) ((p) == MXC_PT0 ? 0 : \
+ (p) == MXC_PT1 ? 1 : \
+ (p) == MXC_PT2 ? 2 : \
+ (p) == MXC_PT3 ? 3 : \
+ (p) == MXC_PT4 ? 4 : \
+ (p) == MXC_PT5 ? 5 : \
+ (p) == MXC_PT6 ? 6 : \
+ (p) == MXC_PT7 ? 7 : \
+ (p) == MXC_PT8 ? 8 : \
+ (p) == MXC_PT9 ? 9 : \
+ (p) == MXC_PT10 ? 10 : \
+ (p) == MXC_PT11 ? 11 : \
+ (p) == MXC_PT12 ? 12 : \
+ (p) == MXC_PT13 ? 13 : \
+ (p) == MXC_PT14 ? 14 : \
+ (p) == MXC_PT15 ? 15 : -1)
+
+
+
+/*******************************************************************************/
+/* UART / Serial Port Interface */
+
+#define MXC_CFG_UART_INSTANCES (4)
+#define MXC_UART_FIFO_DEPTH (32)
+
+#define MXC_BASE_UART0 ((uint32_t)0x40012000UL)
+#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
+#define MXC_BASE_UART1 ((uint32_t)0x40013000UL)
+#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1)
+#define MXC_BASE_UART2 ((uint32_t)0x40014000UL)
+#define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2)
+#define MXC_BASE_UART3 ((uint32_t)0x40015000UL)
+#define MXC_UART3 ((mxc_uart_regs_t *)MXC_BASE_UART3)
+#define MXC_BASE_UART0_FIFO ((uint32_t)0x40103000UL)
+#define MXC_UART0_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART0_FIFO)
+#define MXC_BASE_UART1_FIFO ((uint32_t)0x40104000UL)
+#define MXC_UART1_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART1_FIFO)
+#define MXC_BASE_UART2_FIFO ((uint32_t)0x40105000UL)
+#define MXC_UART2_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART2_FIFO)
+#define MXC_BASE_UART3_FIFO ((uint32_t)0x40106000UL)
+#define MXC_UART3_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART3_FIFO)
+
+#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \
+ (i) == 1 ? UART1_IRQn : \
+ (i) == 2 ? UART2_IRQn : \
+ (i) == 3 ? UART3_IRQn : 0)
+
+#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
+ (i) == 1 ? MXC_BASE_UART1 : \
+ (i) == 2 ? MXC_BASE_UART2 : \
+ (i) == 3 ? MXC_BASE_UART3 : 0)
+
+#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
+ (i) == 1 ? MXC_UART1 : \
+ (i) == 2 ? MXC_UART2 : \
+ (i) == 3 ? MXC_UART3 : 0)
+
+#define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \
+ (p) == MXC_UART1 ? 1 : \
+ (p) == MXC_UART2 ? 2 : \
+ (p) == MXC_UART3 ? 3 : -1)
+
+#define MXC_UART_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_UART0_FIFO : \
+ (i) == 1 ? MXC_BASE_UART1_FIFO : \
+ (i) == 2 ? MXC_BASE_UART2_FIFO : \
+ (i) == 3 ? MXC_BASE_UART3_FIFO : 0)
+
+#define MXC_UART_GET_FIFO(i) ((i) == 0 ? MXC_UART0_FIFO : \
+ (i) == 1 ? MXC_UART1_FIFO : \
+ (i) == 2 ? MXC_UART2_FIFO : \
+ (i) == 3 ? MXC_UART3_FIFO : 0)
+
+
+
+/*******************************************************************************/
+/* I2C Master Interface */
+
+#define MXC_CFG_I2CM_INSTANCES (3)
+#define MXC_I2CM_FIFO_DEPTH (8)
+
+#define MXC_BASE_I2CM0 ((uint32_t)0x40016000UL)
+#define MXC_I2CM0 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0)
+#define MXC_BASE_I2CM1 ((uint32_t)0x40017000UL)
+#define MXC_I2CM1 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1)
+#define MXC_BASE_I2CM2 ((uint32_t)0x40018000UL)
+#define MXC_I2CM2 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM2)
+#define MXC_BASE_I2CM0_FIFO ((uint32_t)0x40107000UL)
+#define MXC_I2CM0_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM0_FIFO)
+#define MXC_BASE_I2CM1_FIFO ((uint32_t)0x40108000UL)
+#define MXC_I2CM1_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM1_FIFO)
+#define MXC_BASE_I2CM2_FIFO ((uint32_t)0x40109000UL)
+#define MXC_I2CM2_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM2_FIFO)
+
+#define MXC_I2CM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2CM0_IRQn : \
+ (i) == 1 ? I2CM1_IRQn : \
+ (i) == 2 ? I2CM2_IRQn : 0)
+
+#define MXC_I2CM_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CM0 : \
+ (i) == 1 ? MXC_BASE_I2CM1 : \
+ (i) == 2 ? MXC_BASE_I2CM2 : 0)
+
+#define MXC_I2CM_GET_I2CM(i) ((i) == 0 ? MXC_I2CM0 : \
+ (i) == 1 ? MXC_I2CM1 : \
+ (i) == 2 ? MXC_I2CM2 : 0)
+
+#define MXC_I2CM_GET_IDX(p) ((p) == MXC_I2CM0 ? 0 : \
+ (p) == MXC_I2CM1 ? 1 : \
+ (p) == MXC_I2CM2 ? 2 : -1)
+
+#define MXC_I2CM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_FIFO : \
+ (i) == 1 ? MXC_BASE_I2CM1_FIFO : \
+ (i) == 2 ? MXC_BASE_I2CM2_FIFO : 0)
+
+#define MXC_I2CM_GET_FIFO(i) ((i) == 0 ? MXC_I2CM0_FIFO : \
+ (i) == 1 ? MXC_I2CM1_FIFO : \
+ (i) == 2 ? MXC_I2CM2_FIFO : 0)
+
+
+
+/*******************************************************************************/
+/* I2C Slave Interface (Mailbox type) */
+
+#define MXC_CFG_I2CS_INSTANCES (1)
+#define MXC_CFG_I2CS_BUFFER_SIZE (32)
+
+#define MXC_BASE_I2CS ((uint32_t)0x40019000UL)
+#define MXC_I2CS ((mxc_i2cs_regs_t *)MXC_BASE_I2CS)
+
+#define MXC_I2CS_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2CS_IRQn : 0)
+
+#define MXC_I2CS_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CS : 0)
+
+#define MXC_I2CS_GET_I2CS(i) ((i) == 0 ? MXC_I2CS : 0)
+
+#define MXC_I2CS_GET_IDX(p) ((p) == MXC_I2CS ? 0 : -1)
+
+/*******************************************************************************/
+/* SPI Master Interface */
+
+#define MXC_CFG_SPIM_INSTANCES (3)
+#define MXC_CFG_SPIM_FIFO_DEPTH (16)
+
+#define MXC_BASE_SPIM0 ((uint32_t)0x4001A000UL)
+#define MXC_SPIM0 ((mxc_spim_regs_t *)MXC_BASE_SPIM0)
+#define MXC_BASE_SPIM1 ((uint32_t)0x4001B000UL)
+#define MXC_SPIM1 ((mxc_spim_regs_t *)MXC_BASE_SPIM1)
+#define MXC_BASE_SPIM2 ((uint32_t)0x4001C000UL)
+#define MXC_SPIM2 ((mxc_spim_regs_t *)MXC_BASE_SPIM2)
+#define MXC_BASE_SPIM0_FIFO ((uint32_t)0x4010A000UL)
+#define MXC_SPIM0_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM0_FIFO)
+#define MXC_BASE_SPIM1_FIFO ((uint32_t)0x4010B000UL)
+#define MXC_SPIM1_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM1_FIFO)
+#define MXC_BASE_SPIM2_FIFO ((uint32_t)0x4010C000UL)
+#define MXC_SPIM2_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM2_FIFO)
+
+#define MXC_SPIM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPIM0_IRQn : \
+ (i) == 1 ? SPIM1_IRQn : \
+ (i) == 2 ? SPIM2_IRQn : 0)
+
+#define MXC_SPIM_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPIM0 : \
+ (i) == 1 ? MXC_BASE_SPIM1 : \
+ (i) == 2 ? MXC_BASE_SPIM2 : 0)
+
+#define MXC_SPIM_GET_SPIM(i) ((i) == 0 ? MXC_SPIM0 : \
+ (i) == 1 ? MXC_SPIM1 : \
+ (i) == 2 ? MXC_SPIM2 : 0)
+
+#define MXC_SPIM_GET_IDX(p) ((p) == MXC_SPIM0 ? 0 : \
+ (p) == MXC_SPIM1 ? 1 : \
+ (p) == MXC_SPIM2 ? 2 : -1)
+
+#define MXC_SPIM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_SPIM0_FIFO : \
+ (i) == 1 ? MXC_BASE_SPIM1_FIFO : \
+ (i) == 2 ? MXC_BASE_SPIM2_FIFO : 0)
+
+#define MXC_SPIM_GET_SPIM_FIFO(i) ((i) == 0 ? MXC_SPIM0_FIFO : \
+ (i) == 1 ? MXC_SPIM1_FIFO : \
+ (i) == 2 ? MXC_SPIM2_FIFO : 0)
+
+
+
+/*******************************************************************************/
+/* 1-Wire Master Interface */
+
+#define MXC_CFG_OWM_INSTANCES (1)
+
+#define MXC_BASE_OWM ((uint32_t)0x4001E000UL)
+#define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM)
+
+#define MXC_OWM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? OWM_IRQn : 0)
+
+#define MXC_OWM_GET_BASE(i) ((i) == 0 ? MXC_BASE_OWM : 0)
+
+#define MXC_OWM_GET_OWM(i) ((i) == 0 ? MXC_OWM : 0)
+
+#define MXC_OWM_GET_IDX(p) ((p) == MXC_OWM ? 0 : -1)
+
+
+/*******************************************************************************/
+/* ADC / AFE */
+
+#define MXC_CFG_ADC_FIFO_DEPTH (32)
+
+#define MXC_BASE_ADC ((uint32_t)0x4001F000UL)
+#define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC)
+
+
+
+/*******************************************************************************/
+/* SPIB AHB-to-SPI Bridge */
+
+#define MXC_BASE_SPIB ((uint32_t)0x4000D000UL)
+#define MXC_SPIB ((mxc_spib_regs_t *)MXC_BASE_SPIB)
+
+
+
+/*******************************************************************************/
+/* SPI Slave Interface */
+#define MXC_CFG_SPIS_INSTANCES (1)
+#define MXC_CFG_SPIS_FIFO_DEPTH (32)
+
+#define MXC_BASE_SPIS ((uint32_t)0x40020000UL)
+#define MXC_SPIS ((mxc_spis_regs_t *)MXC_BASE_SPIS)
+#define MXC_BASE_SPIS_FIFO ((uint32_t)0x4010E000UL)
+#define MXC_SPIS_FIFO ((mxc_spis_fifo_regs_t *)MXC_BASE_SPIS_FIFO)
+
+#define MXC_SPIS_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPIS_IRQn : 0)
+
+#define MXC_SPIS_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPIS : 0)
+
+#define MXC_SPIS_GET_SPIS(i) ((i) == 0 ? MXC_SPIS : 0)
+
+#define MXC_SPIS_GET_IDX(p) ((p) == MXC_SPIS ? 0 : -1)
+
+#define MXC_SPIS_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_SPIS_FIFO : 0)
+
+#define MXC_SPIS_GET_SPIS_FIFO(i) ((i) == 0 ? MXC_SPIS_FIFO :0)
+
+/*******************************************************************************/
+/* Bit Shifting */
+
+#define MXC_F_BIT_0 (1 << 0)
+#define MXC_F_BIT_1 (1 << 1)
+#define MXC_F_BIT_2 (1 << 2)
+#define MXC_F_BIT_3 (1 << 3)
+#define MXC_F_BIT_4 (1 << 4)
+#define MXC_F_BIT_5 (1 << 5)
+#define MXC_F_BIT_6 (1 << 6)
+#define MXC_F_BIT_7 (1 << 7)
+#define MXC_F_BIT_8 (1 << 8)
+#define MXC_F_BIT_9 (1 << 9)
+#define MXC_F_BIT_10 (1 << 10)
+#define MXC_F_BIT_11 (1 << 11)
+#define MXC_F_BIT_12 (1 << 12)
+#define MXC_F_BIT_13 (1 << 13)
+#define MXC_F_BIT_14 (1 << 14)
+#define MXC_F_BIT_15 (1 << 15)
+#define MXC_F_BIT_16 (1 << 16)
+#define MXC_F_BIT_17 (1 << 17)
+#define MXC_F_BIT_18 (1 << 18)
+#define MXC_F_BIT_19 (1 << 19)
+#define MXC_F_BIT_20 (1 << 20)
+#define MXC_F_BIT_21 (1 << 21)
+#define MXC_F_BIT_22 (1 << 22)
+#define MXC_F_BIT_23 (1 << 23)
+#define MXC_F_BIT_24 (1 << 24)
+#define MXC_F_BIT_25 (1 << 25)
+#define MXC_F_BIT_26 (1 << 26)
+#define MXC_F_BIT_27 (1 << 27)
+#define MXC_F_BIT_28 (1 << 28)
+#define MXC_F_BIT_29 (1 << 29)
+#define MXC_F_BIT_30 (1 << 30)
+#define MXC_F_BIT_31 (1 << 31)
+
+
+/*******************************************************************************/
+
+#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
+#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
+#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
+#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
+
+
+/*******************************************************************************/
+
+/* SCB CPACR Register Definitions */
+/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
+#define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */
+#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */
+#define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */
+#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */
+
+#endif /* _MAX32620_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/pwrman_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32620/pwrman_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,394 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_PWRMAN_REGS_H_
+#define _MXC_PWRMAN_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+
+
+/**
+ * @brief Defines PAD Modes for Wake Up Detection.
+ */
+typedef enum {
+ /** WUD Mode for Selected PAD = Clear/Activate */
+ MXC_E_PWRMAN_PAD_MODE_CLEAR_SET,
+ /** WUD Mode for Selected PAD = Set WUD Act Hi/Set WUD Act Lo */
+ MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO,
+ /** WUD Mode for Selected PAD = Set Weak Hi/ Set Weak Lo */
+ MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO,
+ /** WUD Mode for Selected PAD = No pad state change */
+ MXC_E_PWRMAN_PAD_MODE_NONE
+}
+mxc_pwrman_pad_mode_t;
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __IO uint32_t pwr_rst_ctrl; /* 0x0000 Power Reset Control and Status */
+ __IO uint32_t intfl; /* 0x0004 Interrupt Flags */
+ __IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */
+ __IO uint32_t svm_events; /* 0x000C SVM Event Status Flags (read-only) */
+ __IO uint32_t wud_ctrl; /* 0x0010 Wake-Up Detect Control */
+ __IO uint32_t wud_pulse0; /* 0x0014 WUD Pulse To Mode Bit 0 */
+ __IO uint32_t wud_pulse1; /* 0x0018 WUD Pulse To Mode Bit 1 */
+ __IO uint32_t wud_seen0; /* 0x001C Wake-up Detect Status for P0/P1/P2/P3 */
+ __IO uint32_t wud_seen1; /* 0x0020 Wake-up Detect Status for P4/P5/P6/P7 */
+ __R uint32_t rsv024[3]; /* 0x0024-0x002C */
+ __IO uint32_t pt_regmap_ctrl; /* 0x0030 PT Register Mapping Control */
+ __R uint32_t rsv034; /* 0x0034 */
+ __IO uint32_t die_type; /* 0x0038 Die Type ID Register */
+ __IO uint32_t base_part_num; /* 0x003C Base Part Number */
+ __IO uint32_t mask_id0; /* 0x0040 Mask ID Register 0 */
+ __IO uint32_t mask_id1; /* 0x0044 Mask ID Register 1 */
+ __IO uint32_t peripheral_reset; /* 0x0048 Peripheral Reset Control Register */
+} mxc_pwrman_regs_t;
+
+
+/*
+ Register offsets for module PWRMAN.
+*/
+
+#define MXC_R_PWRMAN_OFFS_PWR_RST_CTRL ((uint32_t)0x00000000UL)
+#define MXC_R_PWRMAN_OFFS_INTFL ((uint32_t)0x00000004UL)
+#define MXC_R_PWRMAN_OFFS_INTEN ((uint32_t)0x00000008UL)
+#define MXC_R_PWRMAN_OFFS_SVM_EVENTS ((uint32_t)0x0000000CUL)
+#define MXC_R_PWRMAN_OFFS_WUD_CTRL ((uint32_t)0x00000010UL)
+#define MXC_R_PWRMAN_OFFS_WUD_PULSE0 ((uint32_t)0x00000014UL)
+#define MXC_R_PWRMAN_OFFS_WUD_PULSE1 ((uint32_t)0x00000018UL)
+#define MXC_R_PWRMAN_OFFS_WUD_SEEN0 ((uint32_t)0x0000001CUL)
+#define MXC_R_PWRMAN_OFFS_WUD_SEEN1 ((uint32_t)0x00000020UL)
+#define MXC_R_PWRMAN_OFFS_PT_REGMAP_CTRL ((uint32_t)0x00000030UL)
+#define MXC_R_PWRMAN_OFFS_DIE_TYPE ((uint32_t)0x00000038UL)
+#define MXC_R_PWRMAN_OFFS_BASE_PART_NUM ((uint32_t)0x0000003CUL)
+#define MXC_R_PWRMAN_OFFS_MASK_ID0 ((uint32_t)0x00000040UL)
+#define MXC_R_PWRMAN_OFFS_MASK_ID1 ((uint32_t)0x00000044UL)
+#define MXC_R_PWRMAN_OFFS_PERIPHERAL_RESET ((uint32_t)0x00000048UL)
+
+
+/*
+ Field positions and masks for module PWRMAN.
+*/
+
+#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS 2
+#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS 3
+#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS 4
+#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS 5
+#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS 8
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS 9
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS 16
+#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS 17
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS 18
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS 19
+#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS 20
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS 21
+#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS 22
+#define MXC_F_PWRMAN_PWR_RST_CTRL_POR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS 31
+#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS))
+
+#define MXC_F_PWRMAN_INTFL_V1_2_WARNING_POS 0
+#define MXC_F_PWRMAN_INTFL_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_2_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS 1
+#define MXC_F_PWRMAN_INTFL_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_RTC_WARNING_POS 2
+#define MXC_F_PWRMAN_INTFL_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_RTC_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS 3
+#define MXC_F_PWRMAN_INTFL_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_VDDB_WARNING_POS 4
+#define MXC_F_PWRMAN_INTFL_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDB_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_VDDIO_WARNING_POS 5
+#define MXC_F_PWRMAN_INTFL_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDIO_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_VDDIOH_WARNING_POS 6
+#define MXC_F_PWRMAN_INTFL_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDIOH_WARNING_POS))
+
+#define MXC_F_PWRMAN_INTEN_V1_2_WARNING_POS 0
+#define MXC_F_PWRMAN_INTEN_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_2_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS 1
+#define MXC_F_PWRMAN_INTEN_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_RTC_WARNING_POS 2
+#define MXC_F_PWRMAN_INTEN_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_RTC_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS 3
+#define MXC_F_PWRMAN_INTEN_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_VDDB_WARNING_POS 4
+#define MXC_F_PWRMAN_INTEN_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDB_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_VDDIO_WARNING_POS 5
+#define MXC_F_PWRMAN_INTEN_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDIO_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_VDDIOH_WARNING_POS 6
+#define MXC_F_PWRMAN_INTEN_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDIOH_WARNING_POS))
+
+#define MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING_POS 0
+#define MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS 1
+#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS 2
+#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS 3
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING_POS 4
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING_POS 5
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING_POS 6
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING_POS))
+
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS 0
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT ((uint32_t)(0x0000003FUL << MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS))
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS 8
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE ((uint32_t)(0x00000003UL << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS))
+#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS 12
+#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS))
+#define MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE_POS 16
+#define MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE_POS))
+
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS 0
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS 1
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS 2
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS 3
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS 4
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS 5
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS 6
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS 7
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS 8
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS 9
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS 10
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS 11
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS 12
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS 13
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS 14
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS 15
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS 16
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS 17
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS 18
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS 19
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS 20
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS 21
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS 22
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS 23
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS 24
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS 25
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS 26
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS 27
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS 28
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS 29
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS 30
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS 31
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS))
+
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS 0
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS 1
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS 2
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS 3
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS 4
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS 5
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS 6
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS 7
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS 8
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO40 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS 9
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO41 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS 10
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO42 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS 11
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO43 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS 12
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO44 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS 13
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO45 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS 14
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO46 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS 15
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO47 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS 16
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO48 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS))
+
+#define MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE_POS 0
+#define MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE_POS))
+
+#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS 0
+#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER ((uint32_t)(0x0000FFFFUL << MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS))
+
+#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS 0
+#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID ((uint32_t)(0x0000000FUL << MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS))
+#define MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS 4
+#define MXC_F_PWRMAN_MASK_ID0_MASK_ID ((uint32_t)(0x0FFFFFFFUL << MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS))
+
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS 0
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS))
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS 31
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS))
+
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS 0
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX_POS 1
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_PMU_POS 2
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_PMU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PMU_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS 3
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS 4
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS 5
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS 6
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS 7
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS 8
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS 9
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS 10
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS 11
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4_POS 12
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5_POS 13
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS 14
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS 15
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS 16
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART2_POS 17
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART2_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART3_POS 18
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART3_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS 19
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS 20
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2_POS 21
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS 22
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0_POS 23
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1_POS 24
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2_POS 25
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB_POS 26
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_OWM_POS 27
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_OWM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_OWM_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS 28
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS_POS 29
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS_POS))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_PWRMAN_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/pwrseq_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32620/pwrseq_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,427 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_PWRSEQ_REGS_H_
+#define _MXC_PWRSEQ_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __IO uint32_t reg0; /* 0x0000 Power Sequencer Control Register 0 */
+ __IO uint32_t reg1; /* 0x0004 Power Sequencer Control Register 1 */
+ __IO uint32_t reg2; /* 0x0008 Power Sequencer Control Register 2 */
+ __IO uint32_t reg3; /* 0x000C Power Sequencer Control Register 3 */
+ __IO uint32_t reg4; /* 0x0010 Power Sequencer Control Register 4 (Internal Test Only) */
+ __IO uint32_t reg5; /* 0x0014 Power Sequencer Control Register 5 (Trim 0) */
+ __IO uint32_t reg6; /* 0x0018 Power Sequencer Control Register 6 (Trim 1) */
+ __IO uint32_t reg7; /* 0x001C Power Sequencer Control Register 7 (Trim 2) */
+ __IO uint32_t flags; /* 0x0020 Power Sequencer Flags */
+ __IO uint32_t msk_flags; /* 0x0024 Power Sequencer Flags Mask Register */
+ __R uint32_t rsv028; /* 0x0028 */
+ __IO uint32_t wr_protect; /* 0x002C Critical Setting Write Protect Register */
+ __IO uint32_t retn_ctrl0; /* 0x0030 Retention Control Register 0 */
+ __IO uint32_t retn_ctrl1; /* 0x0034 Retention Control Register 1 */
+ __IO uint32_t pwr_misc; /* 0x0038 Power Misc Controls */
+ __IO uint32_t rtc_ctrl2; /* 0x003C RTC Misc Controls */
+} mxc_pwrseq_regs_t;
+
+
+/*
+ Register offsets for module PWRSEQ.
+*/
+
+#define MXC_R_PWRSEQ_OFFS_REG0 ((uint32_t)0x00000000UL)
+#define MXC_R_PWRSEQ_OFFS_REG1 ((uint32_t)0x00000004UL)
+#define MXC_R_PWRSEQ_OFFS_REG2 ((uint32_t)0x00000008UL)
+#define MXC_R_PWRSEQ_OFFS_REG3 ((uint32_t)0x0000000CUL)
+#define MXC_R_PWRSEQ_OFFS_REG4 ((uint32_t)0x00000010UL)
+#define MXC_R_PWRSEQ_OFFS_REG5 ((uint32_t)0x00000014UL)
+#define MXC_R_PWRSEQ_OFFS_REG6 ((uint32_t)0x00000018UL)
+#define MXC_R_PWRSEQ_OFFS_REG7 ((uint32_t)0x0000001CUL)
+#define MXC_R_PWRSEQ_OFFS_FLAGS ((uint32_t)0x00000020UL)
+#define MXC_R_PWRSEQ_OFFS_MSK_FLAGS ((uint32_t)0x00000024UL)
+#define MXC_R_PWRSEQ_OFFS_WR_PROTECT ((uint32_t)0x0000002CUL)
+#define MXC_R_PWRSEQ_OFFS_RETN_CTRL0 ((uint32_t)0x00000030UL)
+#define MXC_R_PWRSEQ_OFFS_RETN_CTRL1 ((uint32_t)0x00000034UL)
+#define MXC_R_PWRSEQ_OFFS_PWR_MISC ((uint32_t)0x00000038UL)
+#define MXC_R_PWRSEQ_OFFS_RTC_CTRL2 ((uint32_t)0x0000003CUL)
+
+
+/*
+ Field positions and masks for module PWRSEQ.
+*/
+
+#define MXC_F_PWRSEQ_REG0_PWR_LP1_POS 0
+#define MXC_F_PWRSEQ_REG0_PWR_LP1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS 1
+#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS 2
+#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS 3
+#define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS 4
+#define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS 5
+#define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS 6
+#define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS 7
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS 8
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS 9
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS 10
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS 11
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS 12
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS 13
+#define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS 15
+#define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS 17
+#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS 19
+#define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS 21
+#define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS 23
+#define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS 24
+#define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS 25
+#define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS 26
+#define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS 27
+#define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS 28
+#define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN_POS 29
+#define MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP_POS 30
+#define MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT_POS 31
+#define MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT_POS))
+
+#define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS 0
+#define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS 1
+#define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS 2
+#define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS 3
+#define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS 4
+#define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW_POS 5
+#define MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE_POS 6
+#define MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN_POS 8
+#define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN_POS 10
+#define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12_POS 12
+#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC_POS 13
+#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18_POS 14
+#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR_POS 16
+#define MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR_POS 17
+#define MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN_POS 18
+#define MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN_POS 19
+#define MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN_POS))
+
+#define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS 0
+#define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS 2
+#define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS 4
+#define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS 6
+#define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS 8
+#define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST_POS 10
+#define MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST_POS 12
+#define MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST_POS))
+
+#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS 0
+#define MXC_F_PWRSEQ_REG3_PWR_ROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS 3
+#define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS 6
+#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS 8
+#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS 10
+#define MXC_F_PWRSEQ_REG3_PWR_FAILSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS 16
+#define MXC_F_PWRSEQ_REG3_PWR_RO_DIV ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS 20
+#define MXC_F_PWRSEQ_REG3_PWR_RC_DIV ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS))
+
+#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS 0
+#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS 1
+#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS 3
+#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS 4
+#define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS 5
+#define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS 6
+#define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS 7
+#define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_RTC_MUX_POS 8
+#define MXC_F_PWRSEQ_REG4_PWR_RTC_MUX ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RTC_MUX_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN_POS 9
+#define MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN_POS 10
+#define MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN_POS))
+
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS 0
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS))
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS 9
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS))
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0_POS 15
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0 ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0_POS))
+#define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS 21
+#define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS))
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6_POS 25
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6 ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6_POS))
+
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS 0
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS))
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS 3
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS))
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS 7
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS))
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS 11
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS))
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS 20
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS))
+
+#define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS 0
+#define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS))
+#define MXC_F_PWRSEQ_REG7_PWR_TRIM_RC_POS 16
+#define MXC_F_PWRSEQ_REG7_PWR_TRIM_RC ((uint32_t)(0x0000FFFFUL << MXC_F_PWRSEQ_REG7_PWR_TRIM_RC_POS))
+
+#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS 0
+#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS 1
+#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS 2
+#define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS 3
+#define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS 4
+#define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS 5
+#define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS 6
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS 7
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS 8
+#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS 9
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS 10
+#define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS 11
+#define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS 12
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS 13
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS 14
+#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS 15
+#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS 16
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 17
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS 18
+#define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD_POS 19
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD_POS 20
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS 21
+#define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS 22
+#define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS 23
+#define MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS 24
+#define MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS))
+
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS 1
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS 2
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS 3
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS 4
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS 5
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS 6
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS 7
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS 8
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS 9
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS 10
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS 11
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS 12
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS 13
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS 14
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS 15
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS 16
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 17
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS 18
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD_POS 19
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD_POS 20
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS 21
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS 22
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS 23
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS 24
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS))
+
+#define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ_POS 0
+#define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ_POS))
+#define MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ_POS 8
+#define MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ_POS))
+#define MXC_F_PWRSEQ_WR_PROTECT_RTC_POS 28
+#define MXC_F_PWRSEQ_WR_PROTECT_RTC ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_RTC_POS))
+#define MXC_F_PWRSEQ_WR_PROTECT_INFO_POS 29
+#define MXC_F_PWRSEQ_WR_PROTECT_INFO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_INFO_POS))
+#define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_POS 30
+#define MXC_F_PWRSEQ_WR_PROTECT_BYPASS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_BYPASS_POS))
+#define MXC_F_PWRSEQ_WR_PROTECT_WP_POS 31
+#define MXC_F_PWRSEQ_WR_PROTECT_WP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_WP_POS))
+
+#define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS 0
+#define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS))
+#define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS 1
+#define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS))
+#define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS 2
+#define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS))
+#define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS 3
+#define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS))
+#define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS 4
+#define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS))
+
+#define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS 0
+#define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS))
+#define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS 4
+#define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS))
+
+#define MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS_POS 0
+#define MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS_POS))
+
+#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD_POS 0
+#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD_POS))
+#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR_POS 1
+#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR_POS))
+#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE_POS 2
+#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE_POS))
+#define MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE_POS 3
+#define MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE_POS))
+#define MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK_POS 24
+#define MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK_POS))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_PWRSEQ_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/read_uid.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32620/read_uid.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,23 @@
+/* CMSIS-DAP Interface Firmware
+ * Copyright (c) 2009-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "read_uid.h"
+
+#define UID_BASE 0x40001018
+
+void read_unique_id(uint32_t * id) {
+ uint32_t *uid_ptr = (uint32_t*)UID_BASE;
+ *id = uid_ptr[0] ^ uid_ptr[1] ^ uid_ptr[2] ^ uid_ptr[3];
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/rtc_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32620/rtc_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,270 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_RTC_REGS_H_
+#define _MXC_RTC_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __IO uint32_t ctrl; /* 0x0000 RTC Timer Control */
+ __IO uint32_t timer; /* 0x0004 RTC Timer Count Value */
+ __IO uint32_t comp[2]; /* 0x0008-0x000C RTC Time of Day Alarm [0..1] Compare Register */
+ __IO uint32_t flags; /* 0x0010 CPU Interrupt and RTC Domain Flags */
+ __IO uint32_t snz_val; /* 0x0014 RTC Timer Alarm Snooze Value */
+ __IO uint32_t inten; /* 0x0018 Interrupt Enable Controls */
+ __IO uint32_t prescale; /* 0x001C RTC Timer Prescale Setting */
+ __R uint32_t rsv020; /* 0x0020 */
+ __IO uint32_t prescale_mask; /* 0x0024 RTC Timer Prescale Compare Mask */
+ __IO uint32_t trim_ctrl; /* 0x0028 RTC Timer Trim Controls */
+ __IO uint32_t trim_value; /* 0x002C RTC Timer Trim Adjustment Interval */
+} mxc_rtctmr_regs_t;
+
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __IO uint32_t nano_cntr; /* 0x0000 Nano Oscillator Counter Read Register */
+ __IO uint32_t clk_ctrl; /* 0x0004 RTC Clock Control Settings */
+ __R uint32_t rsv008; /* 0x0008 */
+ __IO uint32_t osc_ctrl; /* 0x000C RTC Oscillator Control */
+} mxc_rtccfg_regs_t;
+
+
+/*
+ Register offsets for module RTC.
+*/
+
+#define MXC_R_RTCTMR_OFFS_CTRL ((uint32_t)0x00000000UL)
+#define MXC_R_RTCTMR_OFFS_TIMER ((uint32_t)0x00000004UL)
+#define MXC_R_RTCTMR_OFFS_COMP0 ((uint32_t)0x00000008UL)
+#define MXC_R_RTCTMR_OFFS_COMP1 ((uint32_t)0x0000000CUL)
+#define MXC_R_RTCTMR_OFFS_FLAGS ((uint32_t)0x00000010UL)
+#define MXC_R_RTCTMR_OFFS_SNZ_VAL ((uint32_t)0x00000014UL)
+#define MXC_R_RTCTMR_OFFS_INTEN ((uint32_t)0x00000018UL)
+#define MXC_R_RTCTMR_OFFS_PRESCALE ((uint32_t)0x0000001CUL)
+#define MXC_R_RTCTMR_OFFS_PRESCALE_MASK ((uint32_t)0x00000024UL)
+#define MXC_R_RTCTMR_OFFS_TRIM_CTRL ((uint32_t)0x00000028UL)
+#define MXC_R_RTCTMR_OFFS_TRIM_VALUE ((uint32_t)0x0000002CUL)
+#define MXC_R_RTCCFG_OFFS_NANO_CNTR ((uint32_t)0x00000000UL)
+#define MXC_R_RTCCFG_OFFS_CLK_CTRL ((uint32_t)0x00000004UL)
+#define MXC_R_RTCCFG_OFFS_OSC_CTRL ((uint32_t)0x0000000CUL)
+
+
+/*
+ Field positions and masks for module RTC.
+*/
+
+#define MXC_F_RTC_CTRL_ENABLE_POS 0
+#define MXC_F_RTC_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ENABLE_POS))
+#define MXC_F_RTC_CTRL_CLEAR_POS 1
+#define MXC_F_RTC_CTRL_CLEAR ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLEAR_POS))
+#define MXC_F_RTC_CTRL_PENDING_POS 2
+#define MXC_F_RTC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PENDING_POS))
+#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS 3
+#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS))
+#define MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS 4
+#define MXC_F_RTC_CTRL_AGGRESSIVE_RST ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS))
+#define MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE_POS 5
+#define MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE_POS))
+#define MXC_F_RTC_CTRL_SNOOZE_ENABLE_POS 6
+#define MXC_F_RTC_CTRL_SNOOZE_ENABLE ((uint32_t)(0x00000003UL << MXC_F_RTC_CTRL_SNOOZE_ENABLE_POS))
+#define MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE_POS 16
+#define MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS 17
+#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS 18
+#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS 19
+#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_RTC_SET_ACTIVE_POS 20
+#define MXC_F_RTC_CTRL_RTC_SET_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_SET_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_RTC_CLR_ACTIVE_POS 21
+#define MXC_F_RTC_CTRL_RTC_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_CLR_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS 22
+#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS 23
+#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS 24
+#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS 25
+#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS 26
+#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE_POS 27
+#define MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE_POS 28
+#define MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE_POS 29
+#define MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_ACTIVE_TRANS_0_POS 30
+#define MXC_F_RTC_CTRL_ACTIVE_TRANS_0 ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ACTIVE_TRANS_0_POS))
+
+#define MXC_F_RTC_FLAGS_COMP0_POS 0
+#define MXC_F_RTC_FLAGS_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_POS))
+#define MXC_F_RTC_FLAGS_COMP1_POS 1
+#define MXC_F_RTC_FLAGS_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_POS))
+#define MXC_F_RTC_FLAGS_PRESCALE_COMP_POS 2
+#define MXC_F_RTC_FLAGS_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCALE_COMP_POS))
+#define MXC_F_RTC_FLAGS_OVERFLOW_POS 3
+#define MXC_F_RTC_FLAGS_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_POS))
+#define MXC_F_RTC_FLAGS_TRIM_POS 4
+#define MXC_F_RTC_FLAGS_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_POS))
+#define MXC_F_RTC_FLAGS_SNOOZE_POS 5
+#define MXC_F_RTC_FLAGS_SNOOZE ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_POS))
+#define MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS 8
+#define MXC_F_RTC_FLAGS_COMP0_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS))
+#define MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS 9
+#define MXC_F_RTC_FLAGS_COMP1_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS))
+#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS 10
+#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS))
+#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS 11
+#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS))
+#define MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS 12
+#define MXC_F_RTC_FLAGS_TRIM_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS))
+#define MXC_F_RTC_FLAGS_SNOOZE_A_POS 28
+#define MXC_F_RTC_FLAGS_SNOOZE_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_A_POS))
+#define MXC_F_RTC_FLAGS_SNOOZE_B_POS 29
+#define MXC_F_RTC_FLAGS_SNOOZE_B ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_B_POS))
+#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS 31
+#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS))
+
+#define MXC_F_RTC_SNZ_VAL_VALUE_POS 0
+#define MXC_F_RTC_SNZ_VAL_VALUE ((uint32_t)(0x000003FFUL << MXC_F_RTC_SNZ_VAL_VALUE_POS))
+
+#define MXC_F_RTC_INTEN_COMP0_POS 0
+#define MXC_F_RTC_INTEN_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP0_POS))
+#define MXC_F_RTC_INTEN_COMP1_POS 1
+#define MXC_F_RTC_INTEN_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP1_POS))
+#define MXC_F_RTC_INTEN_PRESCALE_COMP_POS 2
+#define MXC_F_RTC_INTEN_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_PRESCALE_COMP_POS))
+#define MXC_F_RTC_INTEN_OVERFLOW_POS 3
+#define MXC_F_RTC_INTEN_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_OVERFLOW_POS))
+#define MXC_F_RTC_INTEN_TRIM_POS 4
+#define MXC_F_RTC_INTEN_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_TRIM_POS))
+
+#define MXC_F_RTC_PRESCALE_PRESCALE_POS 0
+#define MXC_F_RTC_PRESCALE_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_PRESCALE_POS))
+
+#define MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK_POS 0
+#define MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK_POS))
+
+#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS 0
+#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS))
+#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS 1
+#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS))
+#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS 2
+#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS))
+
+#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS 0
+#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE ((uint32_t)(0x0003FFFFUL << MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS))
+#define MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL_POS 18
+#define MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL_POS))
+
+#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS 0
+#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER ((uint32_t)(0x0000FFFFUL << MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS))
+
+#define MXC_F_RTC_CLK_CTRL_OSC1_EN_POS 0
+#define MXC_F_RTC_CLK_CTRL_OSC1_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC1_EN_POS))
+#define MXC_F_RTC_CLK_CTRL_OSC2_EN_POS 1
+#define MXC_F_RTC_CLK_CTRL_OSC2_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC2_EN_POS))
+#define MXC_F_RTC_CLK_CTRL_NANO_EN_POS 2
+#define MXC_F_RTC_CLK_CTRL_NANO_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_NANO_EN_POS))
+
+#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS 0
+#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS))
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS 1
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS))
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS 2
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS))
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS 3
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS))
+#define MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE_POS 14
+#define MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE_POS))
+
+/*
+ Field values
+*/
+
+#define MXC_V_RTC_CTRL_SNOOZE_DISABLE ((uint32_t)(0x00000000UL))
+#define MXC_V_RTC_CTRL_SNOOZE_MODE_A ((uint32_t)(0x00000001UL))
+#define MXC_V_RTC_CTRL_SNOOZE_MODE_B ((uint32_t)(0x00000002UL))
+
+#define MXC_V_RTC_PRESCALE_DIV_2_0 ((uint32_t)(0x00000000UL))
+#define MXC_V_RTC_PRESCALE_DIV_2_1 ((uint32_t)(0x00000001UL))
+#define MXC_V_RTC_PRESCALE_DIV_2_2 ((uint32_t)(0x00000002UL))
+#define MXC_V_RTC_PRESCALE_DIV_2_3 ((uint32_t)(0x00000003UL))
+#define MXC_V_RTC_PRESCALE_DIV_2_4 ((uint32_t)(0x00000004UL))
+#define MXC_V_RTC_PRESCALE_DIV_2_5 ((uint32_t)(0x00000005UL))
+#define MXC_V_RTC_PRESCALE_DIV_2_6 ((uint32_t)(0x00000006UL))
+#define MXC_V_RTC_PRESCALE_DIV_2_7 ((uint32_t)(0x00000007UL))
+#define MXC_V_RTC_PRESCALE_DIV_2_8 ((uint32_t)(0x00000008UL))
+#define MXC_V_RTC_PRESCALE_DIV_2_9 ((uint32_t)(0x00000009UL))
+#define MXC_V_RTC_PRESCALE_DIV_2_10 ((uint32_t)(0x0000000AUL))
+#define MXC_V_RTC_PRESCALE_DIV_2_11 ((uint32_t)(0x0000000BUL))
+#define MXC_V_RTC_PRESCALE_DIV_2_12 ((uint32_t)(0x0000000CUL))
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_RTC_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/system_max32620.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32620/system_max32620.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,296 @@
+/*******************************************************************************
+ * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#include <string.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include "max32620.h"
+#include "clkman_regs.h"
+#include "adc_regs.h"
+#include "pwrseq_regs.h"
+#include "pwrman_regs.h"
+#include "icc_regs.h"
+#include "flc_regs.h"
+#include "rtc_regs.h"
+#include "trim_regs.h"
+
+#ifndef RO_FREQ
+#define RO_FREQ 96000000
+#endif
+
+#ifndef LP0_POST_HOOK
+#define LP0_POST_HOOK
+#endif
+
+extern void (* const __isr_vector[])(void);
+/*
+* Note: When compiling on ARM Keil Toolchain only.
+* If the SystemCoreClock is left uninitialized, post Scatter load
+* the clock will default to system reset value(48MHz)
+*/
+uint32_t SystemCoreClock = RO_FREQ;
+
+void SystemCoreClockUpdate(void)
+{
+ if(MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN) {
+ /* 4 MHz source */
+ if(MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RC_DIV) {
+ SystemCoreClock = (4000000 / (0x1 << ((MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RC_DIV) >>
+ MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS)));
+ } else {
+ SystemCoreClock = 4000000;
+ }
+ } else {
+ /* 96 MHz source */
+ if(MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RO_DIV) {
+ SystemCoreClock = (RO_FREQ / (0x1 << ((MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RO_DIV) >>
+ MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS)));
+ } else {
+ SystemCoreClock = RO_FREQ;
+ }
+ }
+}
+
+void CLKMAN_TrimRO(void)
+{
+ uint32_t running;
+ uint32_t trim;
+
+ /* Step 1: enable 32KHz RTC */
+ running = MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
+ MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
+
+ /* Wait for RTC warm-up */
+ while(MXC_RTCCFG->osc_ctrl & MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE) {}
+
+ /* Step 2: enable RO calibration complete interrupt */
+ MXC_ADC->intr |= MXC_F_ADC_INTR_RO_CAL_DONE_IE;
+
+ /* Step 3: clear RO calibration complete interrupt */
+ MXC_ADC->intr |= MXC_F_ADC_INTR_RO_CAL_DONE_IF;
+
+ /* Step 4: -- NO LONGER NEEDED / HANDLED BY STARTUP CODE -- */
+
+ /* Step 5: write initial trim to frequency calibration initial condition register */
+ trim = (MXC_PWRSEQ->reg6 & MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF) >> MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS;
+ MXC_ADC->ro_cal1 = (MXC_ADC->ro_cal1 & ~MXC_F_ADC_RO_CAL1_TRM_INIT) |
+ ((trim << MXC_F_ADC_RO_CAL1_TRM_INIT_POS) & MXC_F_ADC_RO_CAL1_TRM_INIT);
+
+ /* Step 6: load initial trim to active frequency trim register */
+ MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_LOAD;
+
+ /* Step 7: enable frequency loop to control RO trim */
+ MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_EN;
+
+ /* Step 8: run frequency calibration in atomic mode */
+ MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC;
+
+ /* Step 9: waiting for ro_cal_done flag */
+ while(!(MXC_ADC->intr & MXC_F_ADC_INTR_RO_CAL_DONE_IF));
+
+ /* Step 10: stop frequency calibration */
+ MXC_ADC->ro_cal0 &= ~MXC_F_ADC_RO_CAL0_RO_CAL_RUN;
+
+ /* Step 11: disable RO calibration complete interrupt */
+ MXC_ADC->intr &= ~MXC_F_ADC_INTR_RO_CAL_DONE_IE;
+
+ /* Step 12: read final frequency trim value */
+ trim = (MXC_ADC->ro_cal0 & MXC_F_ADC_RO_CAL0_RO_TRM) >> MXC_F_ADC_RO_CAL0_RO_TRM_POS;
+
+ /* Step 13: write final trim to RO flash trim shadow register */
+ MXC_PWRSEQ->reg6 = (MXC_PWRSEQ->reg6 & ~MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF) |
+ ((trim << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS) & MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF);
+
+ /* Step 14: restore RTC status */
+ if (!running) {
+ MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
+ }
+
+ /* Step 15: disable frequency loop to control RO trim */
+ MXC_ADC->ro_cal0 &= ~MXC_F_ADC_RO_CAL0_RO_CAL_EN;
+}
+
+static void ICC_Enable(void)
+{
+ /* Invalidate cache and wait until ready */
+ MXC_ICC->invdt_all = 1;
+ while (!(MXC_ICC->ctrl_stat & MXC_F_ICC_CTRL_STAT_READY));
+
+ /* Enable cache */
+ MXC_ICC->ctrl_stat |= MXC_F_ICC_CTRL_STAT_ENABLE;
+
+ /* Must invalidate a second time for proper use */
+ MXC_ICC->invdt_all = 1;
+}
+
+/* This function is called before C runtime initialization and can be
+ * implemented by the application for early initializations. If a value other
+ * than '0' is returned, the C runtime initialization will be skipped.
+ *
+ * You may over-ride this function in your program by defining a custom
+ * PreInit(), but care should be taken to reproduce the initilization steps
+ * or a non-functional system may result.
+ */
+__weak int PreInit(void)
+{
+ /* Increase system clock to 96 MHz */
+ MXC_CLKMAN->clk_ctrl = MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO;
+
+ /* Performance-measurement hook, may be defined as nothing */
+ LP0_POST_HOOK;
+
+ /* Enable cache here to reduce boot time */
+ ICC_Enable();
+
+ return 0;
+}
+
+/*
+* Note: When compiling on ARM Keil Toolchain only.
+* If the SystemCoreClock is modified in this function, post Scatter load
+* the clock will default to system reset value(48MHz)
+*/
+/* This function can be implemented by the application to initialize the board */
+__weak int Board_Init(void)
+{
+ /* Do nothing */
+ return 0;
+}
+
+/* This function is called just before control is transferred to main().
+ *
+ * You may over-ride this function in your program by defining a custom
+ * SystemInit(), but care should be taken to reproduce the initialization
+ * steps or a non-functional system may result.
+ */
+__weak void SystemInit(void)
+{
+ /* Configure the interrupt controller to use the application vector table in */
+ /* the application space */
+#if defined ( __GNUC__)
+ /* IAR sets the VTOR pointer prior to SystemInit and causes stack corruption to change it here. */
+ __disable_irq(); /* Disable interrupts */
+ // SCB->VTOR = (uint32_t)__isr_vector; /* set the Vector Table to point at our ISR table */
+ __DSB(); /* bus sync */
+ __enable_irq(); /* enable interrupts */
+#endif /* __GNUC__ */
+
+ /* Copy trim information from shadow registers into power manager registers */
+ /* NOTE: Checks have been added to prevent bad/missing trim values from being loaded */
+ if ((MXC_FLC->ctrl & MXC_F_FLC_CTRL_INFO_BLOCK_VALID) &&
+ (MXC_TRIM->for_pwr_reg5 != 0xffffffff) &&
+ (MXC_TRIM->for_pwr_reg6 != 0xffffffff)) {
+ MXC_PWRSEQ->reg5 = MXC_TRIM->for_pwr_reg5;
+ MXC_PWRSEQ->reg6 = MXC_TRIM->for_pwr_reg6;
+ } else {
+ /* No valid info block, use some reasonable defaults */
+ MXC_PWRSEQ->reg6 &= ~MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF;
+ MXC_PWRSEQ->reg6 |= (0x1e0 << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS);
+ }
+
+ /* Improve flash access timing */
+ MXC_FLC->perform |= (/*MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS | */
+ MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT |
+ MXC_F_FLC_PERFORM_AUTO_TACC |
+ MXC_F_FLC_PERFORM_AUTO_CLKDIV);
+
+ /* First, eliminate the unnecessary RTC handshake between clock domains. Must be set as a pair. */
+ MXC_RTCTMR->ctrl |= (MXC_F_RTC_CTRL_USE_ASYNC_FLAGS |
+ MXC_F_RTC_CTRL_AGGRESSIVE_RST);
+ /* Enable fast read of the RTC timer value, and fast write of all other RTC registers */
+ MXC_PWRSEQ->rtc_ctrl2 |= (MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE |
+ MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR);
+ MXC_PWRSEQ->rtc_ctrl2 &= ~(MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD);
+
+ /* Clear the GPIO WUD event if not waking up from LP0 */
+ /* this is necessary because WUD flops come up in undetermined state out of POR or SRST*/
+ if(MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ||
+ !(MXC_PWRMAN->pwr_rst_ctrl & MXC_F_PWRMAN_PWR_RST_CTRL_POR)) {
+ /* Clear GPIO WUD event and configuration registers, globally */
+ MXC_PWRSEQ->reg1 |= (MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH |
+ MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
+ MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH |
+ MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
+ } else {
+ /* Unfreeze the GPIO by clearing MBUS_GATE, when returning from LP0 */
+ MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE);
+ /* LP0 wake-up: Turn off special switch to eliminate ~50nA of leakage on VDD12 */
+ MXC_PWRSEQ->reg1 &= ~MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW;
+ }
+
+ /* Turn on retention regulator */
+ MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN |
+ MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP);
+
+ /* Turn on Auto GPIO Freeze/UnFreeze in sleep modes */
+ MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE;
+
+ /* Adjust settings in the retention controller for fastest wake-up time */
+ MXC_PWRSEQ->retn_ctrl0 |= (MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY |
+ MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH);
+ MXC_PWRSEQ->retn_ctrl0 &= ~(MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK);
+
+
+ /* Set retention controller TWake cycle count to 1us to minimize the wake-up time */
+ /* NOTE: flash polling (...PWRSEQ_RETN_CTRL0_RC_POLL_FLASH) must be enabled before changing POR default! */
+ MXC_PWRSEQ->retn_ctrl1 = (MXC_PWRSEQ->retn_ctrl1 & ~MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK) |
+ (1 << MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS);
+
+ /* Improve wake-up time by changing ROSEL to 140ns */
+ MXC_PWRSEQ->reg3 = (1 << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS) |
+ (1 << MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS) |
+ (MXC_PWRSEQ->reg3 & ~(MXC_F_PWRSEQ_REG3_PWR_ROSEL |
+ MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL));
+
+ /* Enable RTOS Mode: Enable 32kHz clock synchronizer to SysTick external clock input */
+ MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE;
+
+ /* Set this so all bits of PWR_MSK_FLAGS are active low to mask the corresponding flags */
+ MXC_PWRSEQ->pwr_misc |= MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS;
+
+ /* Clear this bit to get the latest PT */
+ MXC_PWRMAN->pt_regmap_ctrl &= ~MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE;
+
+ /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */
+ /* Grant full access, per "Table B3-24 CPACR bit assignments". */
+ /* DDI0403D "ARMv7-M Architecture Reference Manual" */
+ SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
+ __DSB();
+ __ISB();
+
+ /* Perform an initial trim of the internal ring oscillator */
+ CLKMAN_TrimRO();
+
+ SystemCoreClockUpdate();
+ Board_Init();
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/system_max32620.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32620/system_max32620.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,76 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#ifndef _SYSTEM_MAX32620_H_
+#define _SYSTEM_MAX32620_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#ifndef HFXIN_FREQ
+#define HFXIN_FREQ 8000000
+#endif
+
+#ifndef RO_FREQ
+#define RO_FREQ 96000000
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/*
+ * Initialize the system
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit(void);
+
+/*
+ * Update SystemCoreClock variable
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_MAX32620_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/tmr_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32620/tmr_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,205 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_TMR_REGS_H_
+#define _MXC_TMR_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __IO uint32_t ctrl; /* 0x0000 Timer Control Register */
+ __IO uint32_t count32; /* 0x0004 Timer [32 bit] Current Count Value */
+ __IO uint32_t term_cnt32; /* 0x0008 Timer [32 bit] Terminal Count Setting */
+ __IO uint32_t pwm_cap32; /* 0x000C Timer [32 bit] PWM Compare Setting or Capture/Measure Value */
+ __IO uint32_t count16_0; /* 0x0010 Timer [16 bit] Current Count Value, 16-bit Timer 0 */
+ __IO uint32_t term_cnt16_0; /* 0x0014 Timer [16 bit] Terminal Count Setting, 16-bit Timer 0 */
+ __IO uint32_t count16_1; /* 0x0018 Timer [16 bit] Current Count Value, 16-bit Timer 1 */
+ __IO uint32_t term_cnt16_1; /* 0x001C Timer [16 bit] Terminal Count Setting, 16-bit Timer 1 */
+ __IO uint32_t intfl; /* 0x0020 Timer Interrupt Flags */
+ __IO uint32_t inten; /* 0x0024 Timer Interrupt Enable/Disable Settings */
+} mxc_tmr_regs_t;
+
+
+/*
+ Register offsets for module TMR.
+*/
+
+#define MXC_R_TMR_OFFS_CTRL ((uint32_t)0x00000000UL)
+#define MXC_R_TMR_OFFS_COUNT32 ((uint32_t)0x00000004UL)
+#define MXC_R_TMR_OFFS_TERM_CNT32 ((uint32_t)0x00000008UL)
+#define MXC_R_TMR_OFFS_PWM_CAP32 ((uint32_t)0x0000000CUL)
+#define MXC_R_TMR_OFFS_COUNT16_0 ((uint32_t)0x00000010UL)
+#define MXC_R_TMR_OFFS_TERM_CNT16_0 ((uint32_t)0x00000014UL)
+#define MXC_R_TMR_OFFS_COUNT16_1 ((uint32_t)0x00000018UL)
+#define MXC_R_TMR_OFFS_TERM_CNT16_1 ((uint32_t)0x0000001CUL)
+#define MXC_R_TMR_OFFS_INTFL ((uint32_t)0x00000020UL)
+#define MXC_R_TMR_OFFS_INTEN ((uint32_t)0x00000024UL)
+
+
+/*
+ Field positions and masks for module TMR.
+*/
+
+#define MXC_F_TMR_CTRL_MODE_POS 0
+#define MXC_F_TMR_CTRL_MODE ((uint32_t)(0x00000007UL << MXC_F_TMR_CTRL_MODE_POS))
+#define MXC_F_TMR_CTRL_TMR2X16_POS 3
+#define MXC_F_TMR_CTRL_TMR2X16 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_TMR2X16_POS))
+#define MXC_F_TMR_CTRL_PRESCALE_POS 4
+#define MXC_F_TMR_CTRL_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_TMR_CTRL_PRESCALE_POS))
+#define MXC_F_TMR_CTRL_POLARITY_POS 8
+#define MXC_F_TMR_CTRL_POLARITY ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_POLARITY_POS))
+#define MXC_F_TMR_CTRL_ENABLE0_POS 12
+#define MXC_F_TMR_CTRL_ENABLE0 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE0_POS))
+#define MXC_F_TMR_CTRL_ENABLE1_POS 13
+#define MXC_F_TMR_CTRL_ENABLE1 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE1_POS))
+
+#define MXC_F_TMR_COUNT16_0_VALUE_POS 0
+#define MXC_F_TMR_COUNT16_0_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_0_VALUE_POS))
+
+#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS 0
+#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS))
+
+#define MXC_F_TMR_COUNT16_1_VALUE_POS 0
+#define MXC_F_TMR_COUNT16_1_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_1_VALUE_POS))
+
+#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS 0
+#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS))
+
+#define MXC_F_TMR_INTFL_TIMER0_POS 0
+#define MXC_F_TMR_INTFL_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER0_POS))
+#define MXC_F_TMR_INTFL_TIMER1_POS 1
+#define MXC_F_TMR_INTFL_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER1_POS))
+
+#define MXC_F_TMR_INTEN_TIMER0_POS 0
+#define MXC_F_TMR_INTEN_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER0_POS))
+#define MXC_F_TMR_INTEN_TIMER1_POS 1
+#define MXC_F_TMR_INTEN_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER1_POS))
+
+
+
+/*
+ Field values and shifted values for module TMR.
+*/
+
+#define MXC_V_TMR_CTRL_MODE_ONE_SHOT ((uint32_t)(0x00000000UL))
+#define MXC_V_TMR_CTRL_MODE_CONTINUOUS ((uint32_t)(0x00000001UL))
+#define MXC_V_TMR_CTRL_MODE_COUNTER ((uint32_t)(0x00000002UL))
+#define MXC_V_TMR_CTRL_MODE_PWM ((uint32_t)(0x00000003UL))
+#define MXC_V_TMR_CTRL_MODE_CAPTURE ((uint32_t)(0x00000004UL))
+#define MXC_V_TMR_CTRL_MODE_COMPARE ((uint32_t)(0x00000005UL))
+#define MXC_V_TMR_CTRL_MODE_GATED ((uint32_t)(0x00000006UL))
+#define MXC_V_TMR_CTRL_MODE_MEASURE ((uint32_t)(0x00000007UL))
+
+#define MXC_S_TMR_CTRL_MODE_ONE_SHOT ((uint32_t)(MXC_V_TMR_CTRL_MODE_ONE_SHOT << MXC_F_TMR_CTRL_MODE_POS))
+#define MXC_S_TMR_CTRL_MODE_CONTINUOUS ((uint32_t)(MXC_V_TMR_CTRL_MODE_CONTINUOUS << MXC_F_TMR_CTRL_MODE_POS))
+#define MXC_S_TMR_CTRL_MODE_COUNTER ((uint32_t)(MXC_V_TMR_CTRL_MODE_COUNTER << MXC_F_TMR_CTRL_MODE_POS))
+#define MXC_S_TMR_CTRL_MODE_PWM ((uint32_t)(MXC_V_TMR_CTRL_MODE_PWM << MXC_F_TMR_CTRL_MODE_POS))
+#define MXC_S_TMR_CTRL_MODE_CAPTURE ((uint32_t)(MXC_V_TMR_CTRL_MODE_CAPTURE << MXC_F_TMR_CTRL_MODE_POS))
+#define MXC_S_TMR_CTRL_MODE_COMPARE ((uint32_t)(MXC_V_TMR_CTRL_MODE_COMPARE << MXC_F_TMR_CTRL_MODE_POS))
+#define MXC_S_TMR_CTRL_MODE_GATED ((uint32_t)(MXC_V_TMR_CTRL_MODE_GATED << MXC_F_TMR_CTRL_MODE_POS))
+#define MXC_S_TMR_CTRL_MODE_MEASURE ((uint32_t)(MXC_V_TMR_CTRL_MODE_MEASURE << MXC_F_TMR_CTRL_MODE_POS))
+
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1 ((uint32_t)(0x00000000UL))
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2 ((uint32_t)(0x00000001UL))
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4 ((uint32_t)(0x00000002UL))
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_8 ((uint32_t)(0x00000003UL))
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_16 ((uint32_t)(0x00000004UL))
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_32 ((uint32_t)(0x00000005UL))
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_64 ((uint32_t)(0x00000006UL))
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_128 ((uint32_t)(0x00000007UL))
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_256 ((uint32_t)(0x00000008UL))
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_512 ((uint32_t)(0x00000009UL))
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 ((uint32_t)(0x0000000AUL))
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 ((uint32_t)(0x0000000BUL))
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 ((uint32_t)(0x0000000CUL))
+
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_1 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1 << MXC_F_TMR_CTRL_PRESCALE_POS))
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_2 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2 << MXC_F_TMR_CTRL_PRESCALE_POS))
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_4 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4 << MXC_F_TMR_CTRL_PRESCALE_POS))
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_8 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_8 << MXC_F_TMR_CTRL_PRESCALE_POS))
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_16 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_16 << MXC_F_TMR_CTRL_PRESCALE_POS))
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_32 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_32 << MXC_F_TMR_CTRL_PRESCALE_POS))
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_64 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_64 << MXC_F_TMR_CTRL_PRESCALE_POS))
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_128 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_128 << MXC_F_TMR_CTRL_PRESCALE_POS))
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_256 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_256 << MXC_F_TMR_CTRL_PRESCALE_POS))
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_512 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_512 << MXC_F_TMR_CTRL_PRESCALE_POS))
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 << MXC_F_TMR_CTRL_PRESCALE_POS))
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 << MXC_F_TMR_CTRL_PRESCALE_POS))
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 << MXC_F_TMR_CTRL_PRESCALE_POS))
+
+
+/*
+ * These two 1-bit fields replace the standard 3-bit mode field when the associated TMR module
+ * is in dual 16-bit timer mode.
+ */
+
+#define MXC_F_TMR_CTRL_MODE_16_0_POS 0
+#define MXC_F_TMR_CTRL_MODE_16_0 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_MODE_16_0_POS))
+
+#define MXC_F_TMR_CTRL_MODE_16_1_POS 1
+#define MXC_F_TMR_CTRL_MODE_16_1 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_MODE_16_1_POS))
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_TMR_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/trim_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32620/trim_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,127 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_TRIM_REGS_H_
+#define _MXC_TRIM_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __R uint32_t rsv000[10]; /* 0x0000-0x0024 */
+ __IO uint32_t reg10_mem_size; /* 0x0028 Shadow Trim for Flash and SRAM Memory Size */
+ __IO uint32_t reg11_adc_trim0; /* 0x002C Shadow Trim for ADC R0 */
+ __IO uint32_t reg12_adc_trim1; /* 0x0030 Shadow Trim for ADC R1 */
+ __IO uint32_t for_pwr_reg5; /* 0x0034 Shadow Trim for PWRSEQ Register REG5 */
+ __IO uint32_t for_pwr_reg6; /* 0x0038 Shadow Trim for PWRSEQ Register REG6 */
+ __IO uint32_t for_pwr_reg7; /* 0x003C Shadow Trim for PWRSEQ Register REG7 */
+} mxc_trim_regs_t;
+
+
+/*
+ Register offsets for module TRIM.
+*/
+
+#define MXC_R_TRIM_OFFS_REG10_MEM_SIZE ((uint32_t)0x00000028UL)
+#define MXC_R_TRIM_OFFS_REG11_ADC_TRIM0 ((uint32_t)0x0000002CUL)
+#define MXC_R_TRIM_OFFS_REG12_ADC_TRIM1 ((uint32_t)0x00000030UL)
+#define MXC_R_TRIM_OFFS_FOR_PWR_REG5 ((uint32_t)0x00000034UL)
+#define MXC_R_TRIM_OFFS_FOR_PWR_REG6 ((uint32_t)0x00000038UL)
+#define MXC_R_TRIM_OFFS_FOR_PWR_REG7 ((uint32_t)0x0000003CUL)
+
+
+/*
+ Field positions and masks for module TRIM.
+*/
+
+#define MXC_F_TRIM_REG10_MEM_SIZE_SRAM_POS 0
+#define MXC_F_TRIM_REG10_MEM_SIZE_SRAM ((uint32_t)(0x00000003UL << MXC_F_TRIM_REG10_MEM_SIZE_SRAM_POS))
+#define MXC_F_TRIM_REG10_MEM_SIZE_FLASH_POS 2
+#define MXC_F_TRIM_REG10_MEM_SIZE_FLASH ((uint32_t)(0x00000007UL << MXC_F_TRIM_REG10_MEM_SIZE_FLASH_POS))
+
+#define MXC_V_TRIM_REG10_MEM_SRAM_FULL_SIZE ((uint32_t)(0x00000000UL))
+#define MXC_V_TRIM_REG10_MEM_SRAM_THREE_FOURTHS_SIZE ((uint32_t)(0x00000001UL))
+#define MXC_V_TRIM_REG10_MEM_SRAM_HALF_SIZE ((uint32_t)(0x00000002UL))
+
+#define MXC_V_TRIM_REG10_MEM_FLASH_FULL_SIZE ((uint32_t)(0x00000000UL))
+#define MXC_V_TRIM_REG10_MEM_FLASH_THREE_FOURTHS_SIZE ((uint32_t)(0x00000001UL))
+#define MXC_V_TRIM_REG10_MEM_FLASH_HALF_SIZE ((uint32_t)(0x00000002UL))
+#define MXC_V_TRIM_REG10_MEM_FLASH_THREE_EIGHTHS_SIZE ((uint32_t)(0x00000003UL))
+#define MXC_V_TRIM_REG10_MEM_FLASH_FOURTH_SIZE ((uint32_t)(0x00000004UL))
+
+#define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0_POS 0
+#define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0_POS))
+#define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0_POS 16
+#define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0_POS))
+
+#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1_POS 0
+#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1_POS))
+#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1_POS 16
+#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1_POS))
+#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC_POS 28
+#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC ((uint32_t)(0x0000000FUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC_POS))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_TRIM_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/uart.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32620/uart.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,316 @@
+/* CMSIS-DAP Interface Firmware
+ * Copyright (c) 2009-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+#include "max32620.h"
+#include "clkman_regs.h"
+#include "ioman_regs.h"
+#include "gpio_regs.h"
+#include "uart_regs.h"
+#include "uart.h"
+
+// Size must be 2^n
+#define BUFFER_SIZE (4096)
+
+#define UART_ERRORS (MXC_F_UART_INTFL_RX_FRAMING_ERR | \
+ MXC_F_UART_INTFL_RX_PARITY_ERR | \
+ MXC_F_UART_INTFL_RX_FIFO_OVERFLOW)
+
+
+// Track bit rate to avoid calculation from bus clock, clock scaler and baud divisor values
+static uint32_t baudrate;
+
+static mxc_uart_regs_t *CdcAcmUart = MXC_UART0;
+static mxc_uart_fifo_regs_t *CdcAcmUartFifo = MXC_UART0_FIFO;
+static const IRQn_Type CdcAcmUartIrqNumber = UART0_IRQn;
+
+
+static struct {
+ uint8_t data[BUFFER_SIZE];
+ volatile uint16_t idx_in;
+ volatile uint16_t idx_out;
+ volatile int16_t cnt_in;
+ volatile int16_t cnt_out;
+} write_buffer, read_buffer;
+
+/******************************************************************************/
+static void set_bitrate(uint32_t bps)
+{
+ uint32_t baud_divisor;
+
+ baud_divisor = SystemCoreClock / (1 << (MXC_CLKMAN->sys_clk_ctrl_8_uart - 1));
+ baud_divisor /= (bps * 16);
+ CdcAcmUart->baud = baud_divisor;
+
+ baudrate = bps;
+}
+
+/******************************************************************************/
+int32_t uart_initialize(void)
+{
+ if (MXC_CLKMAN->sys_clk_ctrl_8_uart != MXC_S_CLKMAN_CLK_SCALE_DIV_4) {
+ MXC_CLKMAN->sys_clk_ctrl_8_uart = MXC_S_CLKMAN_CLK_SCALE_DIV_4;
+ }
+ // Configure GPIO for UART
+ MXC_IOMAN->uart0_req = ((0 << MXC_F_IOMAN_UART0_REQ_IO_MAP_POS) | MXC_F_IOMAN_UART0_REQ_IO_REQ);
+ while (MXC_IOMAN->uart0_ack != ((0 << MXC_F_IOMAN_UART0_REQ_IO_MAP_POS) | MXC_F_IOMAN_UART0_REQ_IO_REQ));
+
+ // Disable TX and RX fifos
+ CdcAcmUart->ctrl &= ~(MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN);
+
+ // Disable interrupts
+ CdcAcmUart->inten = 0;
+ CdcAcmUart->intfl = CdcAcmUart->intfl;
+
+ // Set the parity, size, stop and flow configuration
+ CdcAcmUart->ctrl |= (MXC_S_UART_CTRL_DATA_SIZE_8_BITS | MXC_S_UART_CTRL_PARITY_DISABLE);
+
+ // Set receive fifo threshold to 0
+ CdcAcmUart->rx_fifo_ctrl &= ~MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL;
+ CdcAcmUart->rx_fifo_ctrl |= (0 << MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS);
+
+ // Enable TX and RX fifos
+ CdcAcmUart->ctrl |= (MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN);
+
+ NVIC_EnableIRQ(CdcAcmUartIrqNumber);
+
+ // Set transmit almost empty level to three-quarters of the fifo size
+ CdcAcmUart->tx_fifo_ctrl &= ~MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL;
+ CdcAcmUart->tx_fifo_ctrl |= (MXC_UART_FIFO_DEPTH - (MXC_UART_FIFO_DEPTH >> 2)) << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS;
+
+ // Enable TX and RX interrupts
+ CdcAcmUart->inten = (MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY | MXC_F_UART_INTFL_RX_FIFO_OVERFLOW | MXC_F_UART_INTEN_TX_FIFO_AE);
+
+ // Enable UART
+ CdcAcmUart->ctrl |= MXC_F_UART_CTRL_UART_EN;
+
+ return 1;
+}
+
+/******************************************************************************/
+int32_t uart_uninitialize(void)
+{
+ // Disable UART
+ CdcAcmUart->ctrl &= ~MXC_F_UART_CTRL_UART_EN;
+
+ // Disable interrupts
+ CdcAcmUart->inten = 0;
+ NVIC_DisableIRQ(CdcAcmUartIrqNumber);
+
+ // Clear buffers
+ memset(&write_buffer, 0, sizeof(write_buffer));
+ memset(&read_buffer, 0, sizeof(read_buffer));
+
+ return 1;
+}
+
+/******************************************************************************/
+void uart_set_control_line_state(uint16_t ctrl_bmp)
+{
+}
+
+/******************************************************************************/
+int32_t uart_reset(void)
+{
+ // Clear buffers
+ memset(&write_buffer, 0, sizeof(write_buffer));
+ memset(&read_buffer, 0, sizeof(read_buffer));
+
+ return 1;
+}
+
+/******************************************************************************/
+int32_t uart_set_configuration(UART_Configuration *config)
+{
+ uint32_t ctrl;
+
+ // Get current configuration; clearing parameters that may be configured here
+ ctrl = CdcAcmUart->ctrl & ~(MXC_F_UART_CTRL_PARITY |
+ MXC_F_UART_CTRL_DATA_SIZE |
+ MXC_F_UART_CTRL_EXTRA_STOP |
+ MXC_F_UART_CTRL_CTS_EN |
+ MXC_F_UART_CTRL_RTS_EN);
+
+ switch (config->Parity) {
+ case UART_PARITY_NONE: break;
+ case UART_PARITY_ODD: ctrl |= MXC_S_UART_CTRL_PARITY_ODD;
+ case UART_PARITY_EVEN: ctrl |= MXC_S_UART_CTRL_PARITY_EVEN;
+ case UART_PARITY_MARK: return 0;
+ case UART_PARITY_SPACE: return 0;
+ }
+
+ switch (config->DataBits) {
+ case UART_DATA_BITS_5: ctrl |= MXC_S_UART_CTRL_DATA_SIZE_5_BITS; break;
+ case UART_DATA_BITS_6: ctrl |= MXC_S_UART_CTRL_DATA_SIZE_6_BITS; break;
+ case UART_DATA_BITS_7: ctrl |= MXC_S_UART_CTRL_DATA_SIZE_7_BITS; break;
+ case UART_DATA_BITS_8: ctrl |= MXC_S_UART_CTRL_DATA_SIZE_8_BITS; break;
+ case UART_DATA_BITS_16: return 0;
+ }
+
+ switch (config->StopBits) {
+ case UART_STOP_BITS_1: break;
+ case UART_STOP_BITS_1_5:
+ case UART_STOP_BITS_2: ctrl |= MXC_F_UART_CTRL_EXTRA_STOP; break;
+ }
+
+ switch (config->FlowControl) {
+ case UART_FLOW_CONTROL_NONE: break;
+ case UART_FLOW_CONTROL_RTS_CTS: return 0;
+ case UART_FLOW_CONTROL_XON_XOFF: return 0;
+ }
+
+ set_bitrate(config->Baudrate);
+
+ // Set the new configuration
+ CdcAcmUart->ctrl = ctrl;
+
+ return 1;
+}
+
+/******************************************************************************/
+int32_t uart_get_configuration(UART_Configuration *config)
+{
+ uint32_t ctrl;
+
+ // Capture current configuration
+ ctrl = CdcAcmUart->ctrl;
+
+ if (!(ctrl & MXC_S_UART_CTRL_PARITY_DISABLE)) {
+ config->Parity = UART_PARITY_NONE;
+ } else if (ctrl & MXC_S_UART_CTRL_PARITY_ODD) {
+ config->Parity = UART_PARITY_ODD;
+ } else {
+ // Note both EVEN and MARK parity are captured here
+ config->Parity = UART_PARITY_EVEN;
+ }
+
+ switch (ctrl & MXC_F_UART_CTRL_DATA_SIZE) {
+ case MXC_S_UART_CTRL_DATA_SIZE_5_BITS: config->DataBits = UART_DATA_BITS_5; break;
+ case MXC_S_UART_CTRL_DATA_SIZE_6_BITS: config->DataBits = UART_DATA_BITS_6; break;
+ case MXC_S_UART_CTRL_DATA_SIZE_7_BITS: config->DataBits = UART_DATA_BITS_7; break;
+ case MXC_S_UART_CTRL_DATA_SIZE_8_BITS: config->DataBits = UART_DATA_BITS_8; break;
+ }
+
+ if (!(ctrl & MXC_F_UART_CTRL_EXTRA_STOP)) {
+ config->StopBits = UART_STOP_BITS_1;
+ } else {
+ config->StopBits = UART_STOP_BITS_2;
+ }
+
+ if ((ctrl & (MXC_F_UART_CTRL_CTS_EN | MXC_F_UART_CTRL_RTS_EN)) == (MXC_F_UART_CTRL_CTS_EN | MXC_F_UART_CTRL_RTS_EN)) {
+ config->FlowControl = UART_FLOW_CONTROL_RTS_CTS;
+ } else {
+ // Not true if only one of ...CST_EN and ...RTS_EN are asserted
+ config->FlowControl = UART_FLOW_CONTROL_NONE;
+ }
+
+ config->Baudrate = baudrate;
+
+ return 1;
+}
+
+/******************************************************************************/
+int32_t uart_write_free(void)
+{
+ return BUFFER_SIZE - (write_buffer.cnt_in - write_buffer.cnt_out);
+}
+
+/******************************************************************************/
+int32_t uart_write_data(uint8_t *data, uint16_t size)
+{
+ uint16_t xfer_count = size;
+
+ NVIC_DisableIRQ(CdcAcmUartIrqNumber);
+ if (write_buffer.cnt_in == write_buffer.cnt_out) {
+ while ((((CdcAcmUart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) < MXC_UART_FIFO_DEPTH) &&
+ (xfer_count > 0)) {
+ CdcAcmUart->intfl = MXC_F_UART_INTFL_TX_FIFO_AE;
+ CdcAcmUartFifo->tx = *data++;
+ xfer_count--;
+ }
+ }
+ NVIC_EnableIRQ(CdcAcmUartIrqNumber);
+
+ while (xfer_count > 0) {
+ if ((write_buffer.cnt_in - write_buffer.cnt_out) < BUFFER_SIZE) {
+ write_buffer.data[write_buffer.idx_in++] = *data++;
+ write_buffer.idx_in &= (BUFFER_SIZE - 1);
+ write_buffer.cnt_in++;
+ xfer_count--;
+ } else {
+ break;
+ }
+ }
+ return size - xfer_count;
+}
+
+/******************************************************************************/
+int32_t uart_read_data(uint8_t *data, uint16_t size)
+{
+ int32_t cnt;
+
+ for (cnt = 0; (cnt < size) && (read_buffer.cnt_in != read_buffer.cnt_out); cnt++) {
+ *data++ = read_buffer.data[read_buffer.idx_out++];
+ read_buffer.idx_out &= (BUFFER_SIZE - 1);
+ read_buffer.cnt_out++;
+ }
+
+ return cnt;
+}
+
+/******************************************************************************/
+void UART0_IRQHandler(void)
+{
+ /* Capture interrupt flag state at entry */
+ uint32_t intfl = CdcAcmUart->intfl;
+ /* Clear interrupts that will be serviced */
+ CdcAcmUart->intfl = intfl;
+
+ if (intfl & MXC_F_UART_INTFL_RX_FIFO_OVERFLOW) {
+ read_buffer.data[read_buffer.idx_in++] = '*';
+ read_buffer.idx_in &= (BUFFER_SIZE - 1);
+ read_buffer.cnt_in++;
+ }
+
+ if (intfl & (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS)) {
+ while ((CdcAcmUart->rx_fifo_ctrl & MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY) &&
+ ((read_buffer.cnt_in - read_buffer.cnt_out) < BUFFER_SIZE)) {
+ read_buffer.data[read_buffer.idx_in++] = CdcAcmUartFifo->rx;
+ CdcAcmUart->intfl = MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY;
+ read_buffer.idx_in &= (BUFFER_SIZE - 1);
+ read_buffer.cnt_in++;
+ }
+ if (((read_buffer.cnt_in - read_buffer.cnt_out) >= BUFFER_SIZE)) {
+ read_buffer.data[read_buffer.idx_in++] = '%';
+ read_buffer.idx_in &= (BUFFER_SIZE - 1);
+ read_buffer.cnt_in++;
+ }
+ }
+
+ if (intfl & MXC_F_UART_INTFL_TX_FIFO_AE) {
+ /*
+ Transfer data from write buffer to transmit fifo if
+ a) write buffer contains data and
+ b) transmit fifo is not full
+ */
+ while ((write_buffer.cnt_out != write_buffer.cnt_in) &&
+ (((CdcAcmUart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) < MXC_UART_FIFO_DEPTH)) {
+ CdcAcmUartFifo->tx = write_buffer.data[write_buffer.idx_out++];
+ write_buffer.idx_out &= (BUFFER_SIZE - 1);
+ write_buffer.cnt_out++;
+ }
+ }
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/uart_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32620/uart_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,242 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_UART_REGS_H_
+#define _MXC_UART_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __IO uint32_t ctrl; /* 0x0000 UART Control Register */
+ __IO uint32_t baud; /* 0x0004 UART Baud Control Register */
+ __IO uint32_t tx_fifo_ctrl; /* 0x0008 UART TX FIFO Control Register */
+ __IO uint32_t rx_fifo_ctrl; /* 0x000C UART RX FIFO Control Register */
+ __IO uint32_t md_ctrl; /* 0x0010 UART Multidrop Control Register */
+ __IO uint32_t intfl; /* 0x0014 UART Interrupt Flags */
+ __IO uint32_t inten; /* 0x0018 UART Interrupt Enable/Disable Controls */
+#if (MXC_UART_REV > 0)
+ __R uint32_t idle; /* 0x001C UART Idle Status */
+#endif
+} mxc_uart_regs_t;
+
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ union { /* 0x0000-0x07FC FIFO Write Point for Data to Transmit */
+ __IO uint8_t tx;
+ __IO uint8_t tx_8[2048];
+ __IO uint16_t tx_16[1024];
+ __IO uint32_t tx_32[512];
+ };
+ union { /* 0x0800-0x0FFC FIFO Read Point for Received Data */
+ __IO uint8_t rx;
+ __IO uint8_t rx_8[2048];
+ __IO uint16_t rx_16[1024];
+ __IO uint32_t rx_32[512];
+ };
+} mxc_uart_fifo_regs_t;
+
+
+/*
+ Register offsets for module UART.
+*/
+
+#define MXC_R_UART_OFFS_CTRL ((uint32_t)0x00000000UL)
+#define MXC_R_UART_OFFS_BAUD ((uint32_t)0x00000004UL)
+#define MXC_R_UART_OFFS_TX_FIFO_CTRL ((uint32_t)0x00000008UL)
+#define MXC_R_UART_OFFS_RX_FIFO_CTRL ((uint32_t)0x0000000CUL)
+#define MXC_R_UART_OFFS_MD_CTRL ((uint32_t)0x00000010UL)
+#define MXC_R_UART_OFFS_INTFL ((uint32_t)0x00000014UL)
+#define MXC_R_UART_OFFS_INTEN ((uint32_t)0x00000018UL)
+#define MXC_R_UART_FIFO_OFFS_TX ((uint32_t)0x00000000UL)
+#define MXC_R_UART_FIFO_OFFS_RX ((uint32_t)0x00000800UL)
+
+
+/*
+ Field positions and masks for module UART.
+*/
+
+#define MXC_F_UART_CTRL_UART_EN_POS 0
+#define MXC_F_UART_CTRL_UART_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_UART_EN_POS))
+#define MXC_F_UART_CTRL_RX_FIFO_EN_POS 1
+#define MXC_F_UART_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RX_FIFO_EN_POS))
+#define MXC_F_UART_CTRL_TX_FIFO_EN_POS 2
+#define MXC_F_UART_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_TX_FIFO_EN_POS))
+#define MXC_F_UART_CTRL_DATA_SIZE_POS 4
+#define MXC_F_UART_CTRL_DATA_SIZE ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_DATA_SIZE_POS))
+#define MXC_F_UART_CTRL_EXTRA_STOP_POS 8
+#define MXC_F_UART_CTRL_EXTRA_STOP ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_EXTRA_STOP_POS))
+#define MXC_F_UART_CTRL_PARITY_POS 12
+#define MXC_F_UART_CTRL_PARITY ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_PARITY_POS))
+#define MXC_F_UART_CTRL_CTS_EN_POS 16
+#define MXC_F_UART_CTRL_CTS_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_CTS_EN_POS))
+#define MXC_F_UART_CTRL_CTS_POLARITY_POS 17
+#define MXC_F_UART_CTRL_CTS_POLARITY ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_CTS_POLARITY_POS))
+#define MXC_F_UART_CTRL_RTS_EN_POS 18
+#define MXC_F_UART_CTRL_RTS_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RTS_EN_POS))
+#define MXC_F_UART_CTRL_RTS_POLARITY_POS 19
+#define MXC_F_UART_CTRL_RTS_POLARITY ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RTS_POLARITY_POS))
+#define MXC_F_UART_CTRL_RTS_LEVEL_POS 20
+#define MXC_F_UART_CTRL_RTS_LEVEL ((uint32_t)(0x0000003FUL << MXC_F_UART_CTRL_RTS_LEVEL_POS))
+
+#define MXC_F_UART_BAUD_BAUD_DIVISOR_POS 0
+#define MXC_F_UART_BAUD_BAUD_DIVISOR ((uint32_t)(0x000000FFUL << MXC_F_UART_BAUD_BAUD_DIVISOR_POS))
+#define MXC_F_UART_BAUD_BAUD_MODE_POS 8
+#define MXC_F_UART_BAUD_BAUD_MODE ((uint32_t)(0x00000003UL << MXC_F_UART_BAUD_BAUD_MODE_POS))
+
+#define MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS 0
+#define MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY ((uint32_t)(0x0000003FUL << MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS))
+#define MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS 16
+#define MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL ((uint32_t)(0x0000001FUL << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS))
+
+#define MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY_POS 0
+#define MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY ((uint32_t)(0x0000003FUL << MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY_POS))
+#define MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS 16
+#define MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS))
+
+#define MXC_F_UART_MD_CTRL_SLAVE_ADDR_POS 0
+#define MXC_F_UART_MD_CTRL_SLAVE_ADDR ((uint32_t)(0x000000FFUL << MXC_F_UART_MD_CTRL_SLAVE_ADDR_POS))
+#define MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK_POS 8
+#define MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK ((uint32_t)(0x000000FFUL << MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK_POS))
+#define MXC_F_UART_MD_CTRL_MD_MSTR_POS 16
+#define MXC_F_UART_MD_CTRL_MD_MSTR ((uint32_t)(0x00000001UL << MXC_F_UART_MD_CTRL_MD_MSTR_POS))
+#define MXC_F_UART_MD_CTRL_TX_ADDR_MARK_POS 17
+#define MXC_F_UART_MD_CTRL_TX_ADDR_MARK ((uint32_t)(0x00000001UL << MXC_F_UART_MD_CTRL_TX_ADDR_MARK_POS))
+
+#define MXC_F_UART_INTFL_TX_DONE_POS 0
+#define MXC_F_UART_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_DONE_POS))
+#define MXC_F_UART_INTFL_TX_UNSTALLED_POS 1
+#define MXC_F_UART_INTFL_TX_UNSTALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_UNSTALLED_POS))
+#define MXC_F_UART_INTFL_TX_FIFO_AE_POS 2
+#define MXC_F_UART_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_FIFO_AE_POS))
+#define MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY_POS 3
+#define MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY_POS))
+#define MXC_F_UART_INTFL_RX_STALLED_POS 4
+#define MXC_F_UART_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_STALLED_POS))
+#define MXC_F_UART_INTFL_RX_FIFO_AF_POS 5
+#define MXC_F_UART_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_AF_POS))
+#define MXC_F_UART_INTFL_RX_FIFO_OVERFLOW_POS 6
+#define MXC_F_UART_INTFL_RX_FIFO_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_OVERFLOW_POS))
+#define MXC_F_UART_INTFL_RX_FRAMING_ERR_POS 7
+#define MXC_F_UART_INTFL_RX_FRAMING_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FRAMING_ERR_POS))
+#define MXC_F_UART_INTFL_RX_PARITY_ERR_POS 8
+#define MXC_F_UART_INTFL_RX_PARITY_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_PARITY_ERR_POS))
+
+#define MXC_F_UART_INTEN_TX_DONE_POS 0
+#define MXC_F_UART_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_DONE_POS))
+#define MXC_F_UART_INTEN_TX_UNSTALLED_POS 1
+#define MXC_F_UART_INTEN_TX_UNSTALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_UNSTALLED_POS))
+#define MXC_F_UART_INTEN_TX_FIFO_AE_POS 2
+#define MXC_F_UART_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_FIFO_AE_POS))
+#define MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY_POS 3
+#define MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY_POS))
+#define MXC_F_UART_INTEN_RX_STALLED_POS 4
+#define MXC_F_UART_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_STALLED_POS))
+#define MXC_F_UART_INTEN_RX_FIFO_AF_POS 5
+#define MXC_F_UART_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_AF_POS))
+#define MXC_F_UART_INTEN_RX_FIFO_OVERFLOW_POS 6
+#define MXC_F_UART_INTEN_RX_FIFO_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_OVERFLOW_POS))
+#define MXC_F_UART_INTEN_RX_FRAMING_ERR_POS 7
+#define MXC_F_UART_INTEN_RX_FRAMING_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FRAMING_ERR_POS))
+#define MXC_F_UART_INTEN_RX_PARITY_ERR_POS 8
+#define MXC_F_UART_INTEN_RX_PARITY_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_PARITY_ERR_POS))
+
+#if (MXC_UART_REV > 0)
+#define MXC_F_UART_IDLE_TX_RX_IDLE_POS 0
+#define MXC_F_UART_IDLE_TX_RX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_TX_RX_IDLE_POS))
+#define MXC_F_UART_IDLE_TX_IDLE_POS 1
+#define MXC_F_UART_IDLE_TX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_TX_IDLE_POS))
+#define MXC_F_UART_IDLE_RX_IDLE_POS 2
+#define MXC_F_UART_IDLE_RX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_RX_IDLE_POS))
+#endif
+
+/*
+ Field values and shifted values for module UART.
+*/
+
+#define MXC_V_UART_CTRL_DATA_SIZE_5_BITS ((uint32_t)(0x00000000UL))
+#define MXC_V_UART_CTRL_DATA_SIZE_6_BITS ((uint32_t)(0x00000001UL))
+#define MXC_V_UART_CTRL_DATA_SIZE_7_BITS ((uint32_t)(0x00000002UL))
+#define MXC_V_UART_CTRL_DATA_SIZE_8_BITS ((uint32_t)(0x00000003UL))
+
+#define MXC_S_UART_CTRL_DATA_SIZE_5_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_5_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
+#define MXC_S_UART_CTRL_DATA_SIZE_6_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_6_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
+#define MXC_S_UART_CTRL_DATA_SIZE_7_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_7_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
+#define MXC_S_UART_CTRL_DATA_SIZE_8_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_8_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
+
+#define MXC_V_UART_CTRL_PARITY_DISABLE ((uint32_t)(0x00000000UL))
+#define MXC_V_UART_CTRL_PARITY_ODD ((uint32_t)(0x00000001UL))
+#define MXC_V_UART_CTRL_PARITY_EVEN ((uint32_t)(0x00000002UL))
+#define MXC_V_UART_CTRL_PARITY_MARK ((uint32_t)(0x00000003UL))
+
+#define MXC_S_UART_CTRL_PARITY_DISABLE ((uint32_t)(MXC_V_UART_CTRL_PARITY_DISABLE << MXC_F_UART_CTRL_PARITY_POS))
+#define MXC_S_UART_CTRL_PARITY_ODD ((uint32_t)(MXC_V_UART_CTRL_PARITY_ODD << MXC_F_UART_CTRL_PARITY_POS))
+#define MXC_S_UART_CTRL_PARITY_EVEN ((uint32_t)(MXC_V_UART_CTRL_PARITY_EVEN << MXC_F_UART_CTRL_PARITY_POS))
+#define MXC_S_UART_CTRL_PARITY_MARK ((uint32_t)(MXC_V_UART_CTRL_PARITY_MARK << MXC_F_UART_CTRL_PARITY_POS))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_UART_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/usb_buf.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/maxim/max32620/usb_buf.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,28 @@ +/* CMSIS-DAP Interface Firmware + * Copyright (c) 2009-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef USB_BUF_H +#define USB_BUF_H + +//#include <absacc.h> +#include <stdint.h> + +//#define USB_MSC_BUF_SIZE (2048) +#define USB_MSC_BUF_SIZE (512) + +__attribute__ ((aligned (64))) +uint32_t usb_buffer[USB_MSC_BUF_SIZE/4]; + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/usb_config.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/maxim/max32620/usb_config.c Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,557 @@ +/* CMSIS-DAP Interface Firmware + * Copyright (c) 2009-2019 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "util.h" + +/*------------------------------------------------------------------------------ + * USB Device Configuration + *----------------------------------------------------------------------------*/ + +// <e> USB Device +// <i> Enable the USB Device functionality +#define USBD_ENABLE 1 +#define USBD_RTX_CORE_STACK 0 +#define USBD_RTX_DEVICE_STACK 0 +#define USBD_RTX_ENDPOINT0_STACK 0 + +// <o0.0> High-speed +// <i> Enable high-speed functionality (if device supports it) +#define USBD_HS_ENABLE 0 +#if (defined(WEBUSB_INTERFACE) || defined(WINUSB_INTERFACE) || defined(BULK_ENDPOINT)) +#define USBD_BOS_ENABLE 1 +#else +#define USBD_BOS_ENABLE 0 +#endif +// <h> Device Settings +// <i> These settings affect Device Descriptor +// <o0> Power +// <i> Default Power Setting +// <0=> Bus-powered +// <1=> Self-powered +// <o1> Max Endpoint 0 Packet Size +// <i> Maximum packet size for endpoint zero (bMaxPacketSize0) +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes +// <o2.0..15> Vendor ID <0x0000-0xFFFF> +// <i> Vendor ID assigned by the USB-IF (idVendor) +// <o3.0..15> Product ID <0x0000-0xFFFF> +// <i> Product ID assigned by the manufacturer (idProduct) +// <o4.0..15> Device Release Number <0x0000-0xFFFF> +// <i> Device release number in binary-coded decimal (bcdDevice) +// </h> +#define USBD_POWER 0 +#define USBD_MAX_PACKET0 64 +#define USBD_DEVDESC_IDVENDOR 0x0D28 +#define USBD_DEVDESC_IDPRODUCT 0x0204 +#define USBD_DEVDESC_BCDDEVICE 0x1000 //was 0x0100 + +// <h> Configuration Settings +// <i> These settings affect Configuration Descriptor +// <o0.5> Remote Wakeup +// <i> Configuration support for remote wakeup (D5: of bmAttributes) +// <o1.0..7> Maximum Power Consumption (in mA) <0-510><#/2> +// <i> Maximum power consumption of the USB device +// <i> from the bus in this specific configuration +// <i> when the device is fully operational (bMaxPower) +// </h> +#define USBD_CFGDESC_BMATTRIBUTES 0x80 +#define USBD_CFGDESC_BMAXPOWER 0xFA + +// <h> String Settings +// <i> These settings affect String Descriptor +// <o0.0..15> Language ID <0x0000-0xFCFF> +// <i> English (United States) = 0x0409 +// <s0.126> Manufacturer String +// <i> String descriptor describing manufacturer +// <s1.126> Product String +// <i> String descriptor describing product +// <e1.0> Serial Number +// <i> Enable serial number string +// <i> If disabled serial number string will not be assigned to the USB Device +// <s2.126> Serial Number String +// <i> String descriptor describing device's serial number +// </e> +// </h> +#define USBD_STRDESC_LANGID 0x0409 +#define USBD_STRDESC_MAN L"ARM" +#ifndef USB_PROD_STR +#define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" +#else +#define _TOWIDE(x) L ## #x +#define TOWIDE(x) _TOWIDE(x) +#define USBD_STRDESC_PROD TOWIDE(USB_PROD_STR) +#endif +#define USBD_STRDESC_SER_ENABLE 1 +#define USBD_STRDESC_SER L"0001A0000000" + +// <e0> Class Support +// <i> Enables USB Device Class specific Requests +#define USBD_CLASS_ENABLE 1 + +// <e0.0> Human Interface Device (HID) +// <i> Enable class support for Human Interface Device (HID) +// <h> Interrupt Endpoint Settings +// <o1.0..4> Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o2.0..4> Interrupt Out Endpoint Number <0=> Not used <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <i> If interrupt out endpoint is not used select "Not used" +// <h> Endpoint Settings +// <o3.0..7> Maximum Endpoint Packet Size (in bytes) <0-64> +// <o4.0..7> Endpoint polling Interval (in ms) <1-255> +// <e5> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o6.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o6.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// <o7.0..7> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// </e> +// </h> +// </h> +// <h> Human Interface Device Settings +// <i> Device specific settings +// <s0.126> HID Interface String +// <o8.0..4> Number of Input Reports <1-32> +// <o9.0..4> Number of Output Reports <1-32> +// <o10.0..15> Maximum Input Report Size (in bytes) <1-65535> +// <o11.0..15> Maximum Output Report Size (in bytes) <1-65535> +// <o12.0..15> Maximum Feature Report Size (in bytes) <1-65535> +// </h> +// </e> +#ifndef HID_ENDPOINT +#define HID_ENDPOINT 0 +#else +#define HID_ENDPOINT 1 +#endif + +#ifndef WEBUSB_INTERFACE +#define WEBUSB_INTERFACE 0 +#else +#define WEBUSB_INTERFACE 1 +#endif + +#define USBD_HID_ENABLE HID_ENDPOINT +#ifndef BULK_ENDPOINT //check if bulk endpoint is not enabled +#define USBD_HID_EP_INTIN 1 +#define USBD_HID_EP_INTOUT 2 +#else //if bulk endpoint is enabled remove interrupt endpoints from the hid +#define USBD_HID_EP_INTIN 0 +#define USBD_HID_EP_INTOUT 0 +#endif +#define USBD_HID_EP_INTIN_STACK 0 +#define USBD_HID_WMAXPACKETSIZE 64 +#define USBD_HID_BINTERVAL 1 +#define USBD_HID_HS_ENABLE 0 +#define USBD_HID_HS_WMAXPACKETSIZE 64 +#define USBD_HID_HS_BINTERVAL 6 +#define USBD_HID_STRDESC L"CMSIS-DAP v1" +#define USBD_WEBUSB_STRDESC L"WebUSB: CMSIS-DAP" +#define USBD_HID_INREPORT_NUM 1 +#define USBD_HID_OUTREPORT_NUM 1 +#define USBD_HID_INREPORT_MAX_SZ 64 +#define USBD_HID_OUTREPORT_MAX_SZ 64 +#define USBD_HID_FEATREPORT_MAX_SZ 1 + +// <e0.0> Mass Storage Device (MSC) +// <i> Enable class support for Mass Storage Device (MSC) +// <h> Bulk Endpoint Settings +// <o1.0..4> Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o2.0..4> Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o3> Maximum Packet Size <1-1024> +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5> Maximum Packet Size <1-1024> +// <o6> Maximum NAK Rate <0-255> +// </e> +// </h> +// </h> +// <h> Mass Storage Device Settings +// <i> Device specific settings +// <s0.126> MSC Interface String +// <h> Inquiry Data +// <s1.8> Vendor Identification +// <s2.16> Product Identification +// <s3.4> Product Revision Level +// </h> +// </h> +// </e> +#ifndef MSC_ENDPOINT +#define MSC_ENDPOINT 0 +#else +#define MSC_ENDPOINT 1 +#endif +#define USBD_MSC_ENABLE MSC_ENDPOINT +#define USBD_MSC_EP_BULKIN 3 +#define USBD_MSC_EP_BULKOUT 4 +#define USBD_MSC_EP_BULKIN_STACK 0 +#define USBD_MSC_WMAXPACKETSIZE 64 +#define USBD_MSC_HS_ENABLE 0 +#define USBD_MSC_HS_WMAXPACKETSIZE 512 +#define USBD_MSC_HS_BINTERVAL 0 +#define USBD_MSC_STRDESC L"USB_MSC" +#define USBD_MSC_INQUIRY_DATA "MBED " \ + "VFS " \ + "0.1" + +// <e0.0> Audio Device (ADC) +// <i> Enable class support for Audio Device (ADC) +// <h> Isochronous Endpoint Settings +// <o1.0..4> Isochronous Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o2.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o3.0..10> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o5.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// </e> +// </h> +// </h> +// <h> Audio Device Settings +// <i> Device specific settings +// <s0.126> Audio Control Interface String +// <s1.126> Audio Streaming (Zero Bandwidth) Interface String +// <s2.126> Audio Streaming (Operational) Interface String +// <o6.0..7> Audio Subframe Size (in bytes) <0-255> +// <o7.0..7> Sample Resolution (in bits) <0-255> +// <o8.0..23> Sample Frequency (in Hz) <0-16777215> +// <o9> Packet Size (in bytes) <1-256> +// <o10> Packet Count <1-16> +// </h> +// </e> +#define USBD_ADC_ENABLE 0 +#define USBD_ADC_EP_ISOOUT 3 +#define USBD_ADC_WMAXPACKETSIZE 64 +#define USBD_ADC_BINTERVAL 1 +#define USBD_ADC_HS_ENABLE 0 +#define USBD_ADC_HS_WMAXPACKETSIZE 64 +#define USBD_ADC_CIF_STRDESC L"USB_ADC" +#define USBD_ADC_SIF1_STRDESC L"USB_ADC1" +#define USBD_ADC_SIF2_STRDESC L"USB_ADC2" +#define USBD_ADC_BSUBFRAMESIZE 2 +#define USBD_ADC_BBITRESOLUTION 16 +#define USBD_ADC_TSAMFREQ 32000 +#define USBD_ADC_CFG_P_S 32 +#define USBD_ADC_CFG_P_C 1 + +// <e0> Communication Device (CDC) - Abstract Control Model (ACM) +// <i> Enable class support for Communication Device (CDC) - Abstract Control Model (ACM) +// <h> Interrupt Endpoint Settings +// <o1.0..4> Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o2.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o3.0..10> Endpoint polling Interval (in ms) <0-255> +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o5.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// <o6.0..10> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// </e4> +// </h> +// </h> +// <h> Bulk Endpoint Settings +// <o7.0..4> Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o8.0..4> Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o9> Maximum Packet Size <1-1024> +// <e10> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o11> Maximum Packet Size <1-1024> +// <o12> Maximum NAK Rate <0-255> +// </e10> +// </h> +// </h> +// <h> Communication Device Settings +// <i> Device specific settings +// <s0.126> Communication Class Interface String +// <s1.126> Data Class Interface String +// <o13> Maximum Communication Device Send Buffer Size +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// <o14> Maximum Communication Device Receive Buffer Size +// <i> Minimum size must be as big as maximum packet size for Bulk Out Endpoint +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// </h> +// </e> +#ifndef CDC_ENDPOINT +#define CDC_ENDPOINT 0 +#else +#define CDC_ENDPOINT 1 +#endif +#define USBD_CDC_ACM_ENABLE CDC_ENDPOINT +#define USBD_CDC_ACM_EP_INTIN 5 +#define USBD_CDC_ACM_EP_INTIN_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE 16 +#define USBD_CDC_ACM_BINTERVAL 32 +#define USBD_CDC_ACM_HS_ENABLE 0 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE 16 +#define USBD_CDC_ACM_HS_BINTERVAL 2 +#define USBD_CDC_ACM_EP_BULKIN 6 +#define USBD_CDC_ACM_EP_BULKOUT 7 +#define USBD_CDC_ACM_EP_BULKIN_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE1 64 +#define USBD_CDC_ACM_HS_ENABLE1 0 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE1 64 +#define USBD_CDC_ACM_HS_BINTERVAL1 0 +#define USBD_CDC_ACM_CIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_DIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_SENDBUF_SIZE 64 +#define USBD_CDC_ACM_RECEIVEBUF_SIZE 64 +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Send Buffer size must be larger or equal to Bulk In maximum packet size!" +#endif +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Receive Buffer size must be larger or equal to Bulk Out maximum packet size!" +#endif + +// <e0> Custom Class Device +// <i> Enables USB Custom Class Requests +// <i> Class IDs: +// <i> 0x00 - Class Reserved ID +// <i> 0x01 - Class Audio ID +// <i> 0x02 - Class Communications ID +// <i> 0x03 - Class Human Interface ID +// <i> 0x04 - Class Monitor ID +// <i> 0x05 - Class Physical Interface ID +// <i> 0x06 - Class Power ID +// <i> 0x07 - Class Printer ID +// <i> 0x08 - Class Storage ID +// <i> 0x09 - Class HUB ID +// <i> 0xEF - Class Miscellaneous ID +// <i> 0xFF - Class Vendor Specific ID +// </e> +#define USBD_CLS_ENABLE 0 + +// WebUSB support +#define USBD_WEBUSB_ENABLE WEBUSB_INTERFACE +#define USBD_WEBUSB_VENDOR_CODE 0x21 +#define USBD_WEBUSB_LANDING_URL "os.mbed.com/webusb/landing-page/?bid=" +#define USBD_WEBUSB_ORIGIN_URL "os.mbed.com/" + +// Microsoft OS Descriptors 2.0 (WinUSB) support +#define USBD_WINUSB_ENABLE WINUSB_INTERFACE +#define USBD_WINUSB_VENDOR_CODE 0x20 +// </e> +// </e> + +#ifndef BULK_ENDPOINT +#define BULK_ENDPOINT 0 +#else +#define BULK_ENDPOINT 1 +#endif +#define USBD_BULK_ENABLE BULK_ENDPOINT +#define USBD_BULK_EP_BULKIN 1 +#define USBD_BULK_EP_BULKOUT 2 +#define USBD_BULK_EP_BULKIN_SWO 10 +#define USBD_BULK_WMAXPACKETSIZE 64 +#define USBD_BULK_HS_ENABLE 0 +#define USBD_BULK_HS_WMAXPACKETSIZE 512 +#define USBD_BULK_STRDESC L"CMSIS-DAP v2" + +/* USB Device Calculations ---------------------------------------------------*/ + +#define USBD_IF_NUM_MAX (USBD_BULK_ENABLE+USBD_WEBUSB_ENABLE+USBD_HID_ENABLE+USBD_MSC_ENABLE+(USBD_ADC_ENABLE*2)+(USBD_CDC_ACM_ENABLE*2)+USBD_CLS_ENABLE) +#define USBD_MULTI_IF (USBD_CDC_ACM_ENABLE*(USBD_HID_ENABLE|USBD_MSC_ENABLE|USBD_ADC_ENABLE|USBD_CLS_ENABLE|USBD_WEBUSB_ENABLE|USBD_BULK_ENABLE)) +// #define MAX(x, y) (((x) < (y)) ? (y) : (x)) +#define USBD_EP_NUM_CALC0 MAX((USBD_HID_ENABLE *(USBD_HID_EP_INTIN )), (USBD_HID_ENABLE *(USBD_HID_EP_INTOUT!=0)*(USBD_HID_EP_INTOUT))) +#define USBD_EP_NUM_CALC1 MAX((USBD_MSC_ENABLE *(USBD_MSC_EP_BULKIN )), (USBD_MSC_ENABLE *(USBD_MSC_EP_BULKOUT))) +#define USBD_EP_NUM_CALC2 MAX((USBD_ADC_ENABLE *(USBD_ADC_EP_ISOOUT )), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_INTIN))) +#define USBD_EP_NUM_CALC3 MAX((USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKIN)), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKOUT))) +#define USBD_EP_NUM_CALC4 MAX(USBD_EP_NUM_CALC0, USBD_EP_NUM_CALC1) +#define USBD_EP_NUM_CALC5 MAX(USBD_EP_NUM_CALC2, USBD_EP_NUM_CALC3) +#define USBD_EP_NUM_CALC6 MAX(USBD_EP_NUM_CALC4, USBD_EP_NUM_CALC5) +#define USBD_EP_NUM_CALC7 MAX((USBD_BULK_ENABLE*(USBD_BULK_EP_BULKIN)), (USBD_BULK_ENABLE*(USBD_BULK_EP_BULKOUT))) +#define USBD_EP_NUM MAX(USBD_EP_NUM_CALC6, USBD_EP_NUM_CALC7) + +#if (USBD_EP_NUM > 7) +#error "Max32620 only have 8 individual endpoints including EP0!" +#endif + +#if (USBD_HID_ENABLE) +#if (USBD_MSC_ENABLE) +#if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_MSC_EP_BULKOUT))) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKOUT))) +#error "HID and Mass Storage Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_ADC_ENABLE) +#if ((USBD_HID_EP_INTIN == USBD_ADC_EP_ISOOUT) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_ADC_EP_ISOOUT))) +#error "HID and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (((USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKOUT))|| \ + ((USBD_HID_EP_INTOUT != 0) && \ + ((USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKOUT)))) +#error "HID and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_MSC_ENABLE) +#if (USBD_ADC_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_ADC_EP_ISOOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_ADC_EP_ISOOUT)) +#error "Mass Storage Device and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Mass Storage Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_ADC_ENABLE) +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Audio Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif +#define USBD_ADC_CIF_NUM (0) +#define USBD_ADC_SIF1_NUM (1) +#define USBD_ADC_SIF2_NUM (2) + + +#define USBD_ADC_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+0) +#define USBD_ADC_SIF1_STR_NUM (3+USBD_STRDESC_SER_ENABLE+1) +#define USBD_ADC_SIF2_STR_NUM (3+USBD_STRDESC_SER_ENABLE+2) +#define USBD_CDC_ACM_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+0) +#define USBD_CDC_ACM_DIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+1) +#define USBD_HID_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2) +#define USBD_WEBUSB_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) +#define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) +#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) + +#if (USBD_HID_ENABLE) +#if (USBD_HID_HS_ENABLE) +#define USBD_HID_MAX_PACKET ((USBD_HID_HS_WMAXPACKETSIZE > USBD_HID_WMAXPACKETSIZE) ? USBD_HID_HS_WMAXPACKETSIZE : USBD_HID_WMAXPACKETSIZE) +#else +#define USBD_HID_MAX_PACKET (USBD_HID_WMAXPACKETSIZE) +#endif +#else +#define USBD_HID_MAX_PACKET (0) +#endif +#if (USBD_MSC_ENABLE) +#if (USBD_MSC_HS_ENABLE) +#define USBD_MSC_MAX_PACKET ((USBD_MSC_HS_WMAXPACKETSIZE > USBD_MSC_WMAXPACKETSIZE) ? USBD_MSC_HS_WMAXPACKETSIZE : USBD_MSC_WMAXPACKETSIZE) +#else +#define USBD_MSC_MAX_PACKET (USBD_MSC_WMAXPACKETSIZE) +#endif +#else +#define USBD_MSC_MAX_PACKET (0) +#endif +#if (USBD_ADC_ENABLE) +#if (USBD_ADC_HS_ENABLE) +#define USBD_ADC_MAX_PACKET ((USBD_ADC_HS_WMAXPACKETSIZE > USBD_ADC_WMAXPACKETSIZE) ? USBD_ADC_HS_WMAXPACKETSIZE : USBD_ADC_WMAXPACKETSIZE) +#else +#define USBD_ADC_MAX_PACKET (USBD_ADC_WMAXPACKETSIZE) +#endif +#else +#define USBD_ADC_MAX_PACKET (0) +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (USBD_CDC_ACM_HS_ENABLE) +#define USBD_CDC_ACM_MAX_PACKET ((USBD_CDC_ACM_HS_WMAXPACKETSIZE > USBD_CDC_ACM_WMAXPACKETSIZE) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE : USBD_CDC_ACM_WMAXPACKETSIZE) +#else +#define USBD_CDC_ACM_MAX_PACKET (USBD_CDC_ACM_WMAXPACKETSIZE) +#endif +#if (USBD_CDC_ACM_HS_ENABLE1) +#define USBD_CDC_ACM_MAX_PACKET1 ((USBD_CDC_ACM_HS_WMAXPACKETSIZE1 > USBD_CDC_ACM_WMAXPACKETSIZE1) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE1 : USBD_CDC_ACM_WMAXPACKETSIZE1) +#else +#define USBD_CDC_ACM_MAX_PACKET1 (USBD_CDC_ACM_WMAXPACKETSIZE1) +#endif +#else +#define USBD_CDC_ACM_MAX_PACKET (0) +#define USBD_CDC_ACM_MAX_PACKET1 (0) +#endif + +#if (USBD_BULK_ENABLE) +#if (USBD_BULK_HS_ENABLE) +#define USBD_BULK_MAX_PACKET ((USBD_BULK_HS_WMAXPACKETSIZE > USBD_BULK_WMAXPACKETSIZE) ? USBD_BULK_HS_WMAXPACKETSIZE : USBD_BULK_WMAXPACKETSIZE) +#else +#define USBD_BULK_MAX_PACKET (USBD_BULK_WMAXPACKETSIZE) +#endif +#else +#define USBD_BULK_MAX_PACKET (0) +#endif + +#define USBD_MAX_PACKET_CALC0 ((USBD_HID_MAX_PACKET > USBD_HID_MAX_PACKET ) ? (USBD_HID_MAX_PACKET ) : (USBD_HID_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC1 ((USBD_ADC_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET ) ? (USBD_ADC_MAX_PACKET ) : (USBD_CDC_ACM_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC2 ((USBD_MAX_PACKET_CALC0 > USBD_MAX_PACKET_CALC1 ) ? (USBD_MAX_PACKET_CALC0) : (USBD_MAX_PACKET_CALC1 )) +#define USBD_MAX_PACKET_CALC3 ((USBD_BULK_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET1 ) ? (USBD_BULK_MAX_PACKET) : (USBD_CDC_ACM_MAX_PACKET1 )) +#define USBD_MAX_PACKET ((USBD_MAX_PACKET_CALC3 > USBD_MAX_PACKET_CALC2 ) ? (USBD_MAX_PACKET_CALC3) : (USBD_MAX_PACKET_CALC2 )) + +/*------------------------------------------------------------------------------ + * USB Config Functions + *----------------------------------------------------------------------------*/ + +#ifndef __USB_CONFIG___ +#define __USB_CONFIG__ + +#ifndef __NO_USB_LIB_C +#include "usb_lib.c" +#endif + +#endif /* __USB_CONFIG__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/usb_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32620/usb_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,295 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_USB_REGS_H_
+#define _MXC_USB_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+
+
+#define MXC_V_USB_EP_DIR_DISABLE ((uint32_t)0x00000000UL)
+#define MXC_V_USB_EP_DIR_OUT ((uint32_t)0x00000001UL)
+#define MXC_V_USB_EP_DIR_IN ((uint32_t)0x00000002UL)
+#define MXC_V_USB_EP_DIR_CONTROL ((uint32_t)0x00000003UL)
+
+#define MXC_S_USB_EP_DIR_DISABLE (MXC_V_USB_EP_DIR_DISABLE << MXC_F_USB_EP_DIR_POS)
+#define MXC_S_USB_EP_DIR_OUT (MXC_V_USB_EP_DIR_OUT << MXC_F_USB_EP_DIR_POS)
+#define MXC_S_USB_EP_DIR_IN (MXC_V_USB_EP_DIR_IN << MXC_F_USB_EP_DIR_POS)
+#define MXC_S_USB_EP_DIR_CONTROL (MXC_V_USB_EP_DIR_CONTROL << MXC_F_USB_EP_DIR_POS)
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __IO uint32_t cn; /* 0x0000 USB Control Register */
+ __R uint32_t rsv004[127]; /* 0x0004-0x01FC */
+ __IO uint32_t dev_addr; /* 0x0200 USB Device Address Register */
+ __IO uint32_t dev_cn; /* 0x0204 USB Device Control Register */
+ __IO uint32_t dev_intfl; /* 0x0208 USB Device Interrupt */
+ __IO uint32_t dev_inten; /* 0x020C USB Device Interrupt Enable */
+ __R uint32_t rsv210[4]; /* 0x0210-0x021C */
+ __IO uint32_t ep_base; /* 0x0220 USB Endpoint Descriptor Table Base Address */
+ __IO uint32_t cur_buf; /* 0x0224 USB Current Endpoint Buffer Register */
+ __IO uint32_t in_owner; /* 0x0228 USB IN Endpoint Buffer Owner Register */
+ __IO uint32_t out_owner; /* 0x022C USB OUT Endpoint Buffer Owner Register */
+ __IO uint32_t in_int; /* 0x0230 USB IN Endpoint Buffer Available Interrupt */
+ __IO uint32_t out_int; /* 0x0234 USB OUT Endpoint Data Available Interrupt */
+ __IO uint32_t nak_int; /* 0x0238 USB IN Endpoint NAK Interrupt */
+ __IO uint32_t dma_err_int; /* 0x023C USB DMA Error Interrupt */
+ __IO uint32_t buf_ovr_int; /* 0x0240 USB Buffer Overflow Interrupt */
+ __R uint32_t rsv244[7]; /* 0x0244-0x025C */
+ __IO uint32_t setup0; /* 0x0260 USB SETUP Packet Bytes 0 to 3 */
+ __IO uint32_t setup1; /* 0x0264 USB SETUP Packet Bytes 4 to 7 */
+ __R uint32_t rsv268[6]; /* 0x0268-0x027C */
+ __IO uint32_t ep[8]; /* 0x0280-0x029C USB Endpoint[n] Control Register */
+} mxc_usb_regs_t;
+
+
+/*
+ Register offsets for module USB.
+*/
+
+#define MXC_R_USB_OFFS_CN ((uint32_t)0x00000000UL)
+#define MXC_R_USB_OFFS_DEV_ADDR ((uint32_t)0x00000200UL)
+#define MXC_R_USB_OFFS_DEV_CN ((uint32_t)0x00000204UL)
+#define MXC_R_USB_OFFS_DEV_INTFL ((uint32_t)0x00000208UL)
+#define MXC_R_USB_OFFS_DEV_INTEN ((uint32_t)0x0000020CUL)
+#define MXC_R_USB_OFFS_EP_BASE ((uint32_t)0x00000220UL)
+#define MXC_R_USB_OFFS_CUR_BUF ((uint32_t)0x00000224UL)
+#define MXC_R_USB_OFFS_IN_OWNER ((uint32_t)0x00000228UL)
+#define MXC_R_USB_OFFS_OUT_OWNER ((uint32_t)0x0000022CUL)
+#define MXC_R_USB_OFFS_IN_INT ((uint32_t)0x00000230UL)
+#define MXC_R_USB_OFFS_OUT_INT ((uint32_t)0x00000234UL)
+#define MXC_R_USB_OFFS_NAK_INT ((uint32_t)0x00000238UL)
+#define MXC_R_USB_OFFS_DMA_ERR_INT ((uint32_t)0x0000023CUL)
+#define MXC_R_USB_OFFS_BUF_OVR_INT ((uint32_t)0x00000240UL)
+#define MXC_R_USB_OFFS_SETUP0 ((uint32_t)0x00000260UL)
+#define MXC_R_USB_OFFS_SETUP1 ((uint32_t)0x00000264UL)
+#define MXC_R_USB_OFFS_EP0 ((uint32_t)0x00000280UL)
+#define MXC_R_USB_OFFS_EP1 ((uint32_t)0x00000284UL)
+#define MXC_R_USB_OFFS_EP2 ((uint32_t)0x00000288UL)
+#define MXC_R_USB_OFFS_EP3 ((uint32_t)0x0000028CUL)
+#define MXC_R_USB_OFFS_EP4 ((uint32_t)0x00000290UL)
+#define MXC_R_USB_OFFS_EP5 ((uint32_t)0x00000294UL)
+#define MXC_R_USB_OFFS_EP6 ((uint32_t)0x00000298UL)
+#define MXC_R_USB_OFFS_EP7 ((uint32_t)0x0000029CUL)
+
+
+/*
+ Field positions and masks for module USB.
+*/
+
+#define MXC_F_USB_CN_USB_EN_POS 0
+#define MXC_F_USB_CN_USB_EN ((uint32_t)(0x00000001UL << MXC_F_USB_CN_USB_EN_POS))
+#define MXC_F_USB_CN_HOST_POS 1
+#define MXC_F_USB_CN_HOST ((uint32_t)(0x00000001UL << MXC_F_USB_CN_HOST_POS))
+
+#define MXC_F_USB_DEV_ADDR_DEV_ADDR_POS 0
+#define MXC_F_USB_DEV_ADDR_DEV_ADDR ((uint32_t)(0x0000007FUL << MXC_F_USB_DEV_ADDR_DEV_ADDR_POS))
+
+#define MXC_F_USB_DEV_CN_SIGRWU_POS 2
+#define MXC_F_USB_DEV_CN_SIGRWU ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_SIGRWU_POS))
+#define MXC_F_USB_DEV_CN_CONNECT_POS 3
+#define MXC_F_USB_DEV_CN_CONNECT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_CONNECT_POS))
+#define MXC_F_USB_DEV_CN_ULPM_POS 4
+#define MXC_F_USB_DEV_CN_ULPM ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_ULPM_POS))
+#define MXC_F_USB_DEV_CN_URST_POS 5
+#define MXC_F_USB_DEV_CN_URST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_URST_POS))
+#define MXC_F_USB_DEV_CN_VBGATE_POS 6
+#define MXC_F_USB_DEV_CN_VBGATE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_VBGATE_POS))
+#define MXC_F_USB_DEV_CN_OSCEN_POS 7
+#define MXC_F_USB_DEV_CN_OSCEN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_OSCEN_POS))
+#define MXC_F_USB_DEV_CN_BACT_OE_POS 8
+#define MXC_F_USB_DEV_CN_BACT_OE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_BACT_OE_POS))
+#define MXC_F_USB_DEV_CN_FIFO_MODE_POS 9
+#define MXC_F_USB_DEV_CN_FIFO_MODE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_FIFO_MODE_POS))
+
+#define MXC_F_USB_DEV_INTFL_DPACT_POS 0
+#define MXC_F_USB_DEV_INTFL_DPACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DPACT_POS))
+#define MXC_F_USB_DEV_INTFL_RWU_DN_POS 1
+#define MXC_F_USB_DEV_INTFL_RWU_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_RWU_DN_POS))
+#define MXC_F_USB_DEV_INTFL_BACT_POS 2
+#define MXC_F_USB_DEV_INTFL_BACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BACT_POS))
+#define MXC_F_USB_DEV_INTFL_BRST_POS 3
+#define MXC_F_USB_DEV_INTFL_BRST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_POS))
+#define MXC_F_USB_DEV_INTFL_SUSP_POS 4
+#define MXC_F_USB_DEV_INTFL_SUSP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SUSP_POS))
+#define MXC_F_USB_DEV_INTFL_NO_VBUS_POS 5
+#define MXC_F_USB_DEV_INTFL_NO_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_NO_VBUS_POS))
+#define MXC_F_USB_DEV_INTFL_VBUS_POS 6
+#define MXC_F_USB_DEV_INTFL_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_POS))
+#define MXC_F_USB_DEV_INTFL_BRST_DN_POS 7
+#define MXC_F_USB_DEV_INTFL_BRST_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_DN_POS))
+#define MXC_F_USB_DEV_INTFL_SETUP_POS 8
+#define MXC_F_USB_DEV_INTFL_SETUP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SETUP_POS))
+#define MXC_F_USB_DEV_INTFL_EP_IN_POS 9
+#define MXC_F_USB_DEV_INTFL_EP_IN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_IN_POS))
+#define MXC_F_USB_DEV_INTFL_EP_OUT_POS 10
+#define MXC_F_USB_DEV_INTFL_EP_OUT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_OUT_POS))
+#define MXC_F_USB_DEV_INTFL_EP_NAK_POS 11
+#define MXC_F_USB_DEV_INTFL_EP_NAK ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_NAK_POS))
+#define MXC_F_USB_DEV_INTFL_DMA_ERR_POS 12
+#define MXC_F_USB_DEV_INTFL_DMA_ERR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DMA_ERR_POS))
+#define MXC_F_USB_DEV_INTFL_BUF_OVR_POS 13
+#define MXC_F_USB_DEV_INTFL_BUF_OVR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BUF_OVR_POS))
+#define MXC_F_USB_DEV_INTFL_VBUS_ST_POS 16
+#define MXC_F_USB_DEV_INTFL_VBUS_ST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_ST_POS))
+
+#define MXC_F_USB_DEV_INTEN_DPACT_POS 0
+#define MXC_F_USB_DEV_INTEN_DPACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DPACT_POS))
+#define MXC_F_USB_DEV_INTEN_RWU_DN_POS 1
+#define MXC_F_USB_DEV_INTEN_RWU_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_RWU_DN_POS))
+#define MXC_F_USB_DEV_INTEN_BACT_POS 2
+#define MXC_F_USB_DEV_INTEN_BACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BACT_POS))
+#define MXC_F_USB_DEV_INTEN_BRST_POS 3
+#define MXC_F_USB_DEV_INTEN_BRST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_POS))
+#define MXC_F_USB_DEV_INTEN_SUSP_POS 4
+#define MXC_F_USB_DEV_INTEN_SUSP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SUSP_POS))
+#define MXC_F_USB_DEV_INTEN_NO_VBUS_POS 5
+#define MXC_F_USB_DEV_INTEN_NO_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_NO_VBUS_POS))
+#define MXC_F_USB_DEV_INTEN_VBUS_POS 6
+#define MXC_F_USB_DEV_INTEN_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_VBUS_POS))
+#define MXC_F_USB_DEV_INTEN_BRST_DN_POS 7
+#define MXC_F_USB_DEV_INTEN_BRST_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_DN_POS))
+#define MXC_F_USB_DEV_INTEN_SETUP_POS 8
+#define MXC_F_USB_DEV_INTEN_SETUP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SETUP_POS))
+#define MXC_F_USB_DEV_INTEN_EP_IN_POS 9
+#define MXC_F_USB_DEV_INTEN_EP_IN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_IN_POS))
+#define MXC_F_USB_DEV_INTEN_EP_OUT_POS 10
+#define MXC_F_USB_DEV_INTEN_EP_OUT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_OUT_POS))
+#define MXC_F_USB_DEV_INTEN_EP_NAK_POS 11
+#define MXC_F_USB_DEV_INTEN_EP_NAK ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_NAK_POS))
+#define MXC_F_USB_DEV_INTEN_DMA_ERR_POS 12
+#define MXC_F_USB_DEV_INTEN_DMA_ERR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DMA_ERR_POS))
+#define MXC_F_USB_DEV_INTEN_BUF_OVR_POS 13
+#define MXC_F_USB_DEV_INTEN_BUF_OVR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BUF_OVR_POS))
+
+#define MXC_F_USB_EP_BASE_EP_BASE_POS 9
+#define MXC_F_USB_EP_BASE_EP_BASE ((uint32_t)(0x007FFFFFUL << MXC_F_USB_EP_BASE_EP_BASE_POS))
+
+#define MXC_F_USB_CUR_BUF_OUT_BUF_POS 0
+#define MXC_F_USB_CUR_BUF_OUT_BUF ((uint32_t)(0x0000FFFFUL << MXC_F_USB_CUR_BUF_OUT_BUF_POS))
+#define MXC_F_USB_CUR_BUF_IN_BUF_POS 16
+#define MXC_F_USB_CUR_BUF_IN_BUF ((uint32_t)(0x0000FFFFUL << MXC_F_USB_CUR_BUF_IN_BUF_POS))
+
+#define MXC_F_USB_IN_OWNER_BUF0_OWNER_POS 0
+#define MXC_F_USB_IN_OWNER_BUF0_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_IN_OWNER_BUF0_OWNER_POS))
+#define MXC_F_USB_IN_OWNER_BUF1_OWNER_POS 16
+#define MXC_F_USB_IN_OWNER_BUF1_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_IN_OWNER_BUF1_OWNER_POS))
+
+#define MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS 0
+#define MXC_F_USB_OUT_OWNER_BUF0_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS))
+#define MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS 16
+#define MXC_F_USB_OUT_OWNER_BUF1_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS))
+
+#define MXC_F_USB_IN_INT_INBAV_POS 0
+#define MXC_F_USB_IN_INT_INBAV ((uint32_t)(0x000000FFUL << MXC_F_USB_IN_INT_INBAV_POS))
+
+#define MXC_F_USB_OUT_INT_OUTDAV_POS 0
+#define MXC_F_USB_OUT_INT_OUTDAV ((uint32_t)(0x000000FFUL << MXC_F_USB_OUT_INT_OUTDAV_POS))
+
+#define MXC_F_USB_NAK_INT_NAK_POS 0
+#define MXC_F_USB_NAK_INT_NAK ((uint32_t)(0x000000FFUL << MXC_F_USB_NAK_INT_NAK_POS))
+
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR_POS 0
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR ((uint32_t)(0x000000FFUL << MXC_F_USB_DMA_ERR_INT_DMA_ERR_POS))
+
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR_POS 0
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR ((uint32_t)(0x000000FFUL << MXC_F_USB_BUF_OVR_INT_BUF_OVR_POS))
+
+#define MXC_F_USB_SETUP0_BYTE0_POS 0
+#define MXC_F_USB_SETUP0_BYTE0 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE0_POS))
+#define MXC_F_USB_SETUP0_BYTE1_POS 8
+#define MXC_F_USB_SETUP0_BYTE1 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE1_POS))
+#define MXC_F_USB_SETUP0_BYTE2_POS 16
+#define MXC_F_USB_SETUP0_BYTE2 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE2_POS))
+#define MXC_F_USB_SETUP0_BYTE3_POS 24
+#define MXC_F_USB_SETUP0_BYTE3 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE3_POS))
+
+#define MXC_F_USB_SETUP1_BYTE0_POS 0
+#define MXC_F_USB_SETUP1_BYTE0 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE0_POS))
+#define MXC_F_USB_SETUP1_BYTE1_POS 8
+#define MXC_F_USB_SETUP1_BYTE1 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE1_POS))
+#define MXC_F_USB_SETUP1_BYTE2_POS 16
+#define MXC_F_USB_SETUP1_BYTE2 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE2_POS))
+#define MXC_F_USB_SETUP1_BYTE3_POS 24
+#define MXC_F_USB_SETUP1_BYTE3 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE3_POS))
+
+#define MXC_F_USB_EP_DIR_POS 0
+#define MXC_F_USB_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP_DIR_POS))
+#define MXC_F_USB_EP_BUF2_POS 3
+#define MXC_F_USB_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP_BUF2_POS))
+#define MXC_F_USB_EP_INT_EN_POS 4
+#define MXC_F_USB_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP_INT_EN_POS))
+#define MXC_F_USB_EP_NAK_EN_POS 5
+#define MXC_F_USB_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP_NAK_EN_POS))
+#define MXC_F_USB_EP_DT_POS 6
+#define MXC_F_USB_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP_DT_POS))
+#define MXC_F_USB_EP_STALL_POS 8
+#define MXC_F_USB_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP_STALL_POS))
+#define MXC_F_USB_EP_ST_STALL_POS 9
+#define MXC_F_USB_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP_ST_STALL_POS))
+#define MXC_F_USB_EP_ST_ACK_POS 10
+#define MXC_F_USB_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP_ST_ACK_POS))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_USB_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32620/usbd_max32620.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32620/usbd_max32620.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,622 @@
+/* CMSIS-DAP Interface Firmware
+ * Copyright (c) 2009-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+#include "rl_usb.h"
+#include "util.h"
+
+#include "max32620.h"
+#include "usb_regs.h"
+#include "clkman_regs.h"
+#include "pwrman_regs.h"
+#include "tmr_regs.h"
+
+#define __NO_USB_LIB_C
+#include "usb_config.c"
+
+#define EPNUM_MASK (~USB_ENDPOINT_DIRECTION_MASK)
+
+#define INIT_INTS (MXC_F_USB_DEV_INTEN_BRST | MXC_F_USB_DEV_INTFL_BRST_DN | MXC_F_USB_DEV_INTEN_VBUS | MXC_F_USB_DEV_INTFL_NO_VBUS)
+#define CONNECT_INTS (MXC_F_USB_DEV_INTEN_SETUP | MXC_F_USB_DEV_INTEN_EP_IN | MXC_F_USB_DEV_INTEN_EP_OUT | MXC_F_USB_DEV_INTEN_DMA_ERR)
+
+typedef struct {
+ volatile uint32_t buf0_desc;
+ volatile uint32_t buf0_address;
+ volatile uint32_t buf1_desc;
+ volatile uint32_t buf1_address;
+} ep_buffer_t;
+
+typedef struct {
+ ep_buffer_t out_buffer;
+ ep_buffer_t in_buffer;
+} ep0_buffer_t;
+
+typedef struct {
+ ep0_buffer_t ep0;
+ ep_buffer_t ep[MXC_USB_NUM_EP - 1];
+} ep_buffer_descriptor_t;
+
+typedef struct {
+ U8 type;
+ U16 len;
+} ep_info_t;
+
+/* static storage for endpoint buffer descriptor table, must be 512 byte aligned for DMA */
+__attribute__ ((aligned (512)))
+ep_buffer_descriptor_t ep_buffer_descriptor;
+
+static uint32_t ep_buffer[MXC_USB_NUM_EP][MXC_USB_MAX_PACKET / sizeof(uint32_t)];
+static ep_info_t ep_info[MXC_USB_NUM_EP];
+static volatile int suspended;
+static volatile int setup_waiting;
+static volatile int ep0_expect_zlp;
+
+#if CDC_ENDPOINT
+/* CDC-ACM class processes FIFOs in the SOF interrupt. The USB Device interface
+ * of Maxim's microcontrollers does not provide and SOF interrupt. A periodic
+ * timer interrupt is used instead.
+ */
+/******************************************************************************/
+void TMR0_IRQHandler(void)
+{
+ MXC_TMR0->intfl = MXC_TMR0->intfl;
+
+ if (usbd_configured()) {
+ USBD_CDC_ACM_SOF_Event();
+ }
+}
+#endif
+
+/******************************************************************************/
+static ep_buffer_t *get_desc(U32 EPNum)
+{
+ ep_buffer_t *desc;
+
+ if (EPNum == 0x80) {
+ desc = &ep_buffer_descriptor.ep0.in_buffer;
+ } else if (EPNum == 0x00) {
+ desc = &ep_buffer_descriptor.ep0.out_buffer;
+ } else {
+ desc = &ep_buffer_descriptor.ep[(EPNum & EPNUM_MASK) - 1];
+ }
+
+ return desc;
+}
+
+/*
+ * USB Device Interrupt enable
+ * Called by USBD_Init to enable the USB Interrupt
+ * Return Value: None
+ */
+
+void USBD_IntrEna(void)
+{
+ NVIC_EnableIRQ(USB_IRQn); /* Enable OTG interrupt */
+}
+
+/******************************************************************************/
+/*
+ * Usb interrupt enable/disable
+ * Parameters: ena: enable/disable
+ * 0: disable interrupt
+ * 1: enable interrupt
+ */
+#ifdef __RTX
+void __svc(1) USBD_Intr (int ena);
+void __SVC_1 (int ena)
+{
+ if (ena) {
+ NVIC_EnableIRQ(USB_IRQn); /* Enable USB interrupt */
+ } else {
+ NVIC_DisableIRQ(USB_IRQn); /* Disable USB interrupt */
+ }
+}
+#endif
+
+/******************************************************************************/
+static void reset_state(void)
+{
+ unsigned int ep;
+
+ suspended = 0;
+ setup_waiting = 0;
+ ep0_expect_zlp = 0;
+ memset(ep_info, 0, sizeof(ep_info));
+
+ MXC_USB->ep[0] |= (MXC_S_USB_EP_DIR_CONTROL | MXC_F_USB_EP_INT_EN | MXC_F_USB_EP_DT);
+ for (ep = 1; ep < MXC_USB_NUM_EP; ep++) {
+ MXC_USB->ep[ep] = MXC_F_USB_EP_DT;
+ }
+}
+
+/*
+ * USB Device Initialize Function
+ * Called by the User to initialize USB Device
+ * Return Value: None
+ */
+void USBD_Init (void)
+{
+ uint32_t reg;
+
+ /* Enable USB power domain */
+ MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED;
+ /* Setup the USB clocking, select */
+ MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE;
+ /* Force USB clock gater */
+ reg = MXC_CLKMAN->clk_gate_ctrl0;
+ reg &= ~MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER;
+ reg |= (0x2 << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS);
+ MXC_CLKMAN->clk_gate_ctrl0 = reg;
+
+ MXC_USB->cn = 0;
+ MXC_USB->cn = MXC_F_USB_CN_USB_EN;
+ MXC_USB->dev_inten = 0;
+ MXC_USB->dev_intfl = 0xFFFF; // clear interrupts
+ MXC_USB->dev_cn = 0;
+ MXC_USB->dev_cn |= MXC_F_USB_DEV_CN_URST;
+ MXC_USB->dev_cn = 0;
+
+ reset_state();
+
+ /* set the descriptor location */
+ MXC_USB->ep_base = (uint32_t)&ep_buffer_descriptor;
+
+ /* enable some interrupts */
+ MXC_USB->dev_inten = INIT_INTS;
+ NVIC_EnableIRQ(USB_IRQn);
+}
+
+/*
+ * USB Device Connect Function
+ * Called by the User to Connect/Disconnect USB Device
+ * Parameters: con: Connect/Disconnect
+ * Return Value: None
+ */
+void USBD_Connect (BOOL con)
+{
+ if (con) {
+ MXC_USB->dev_intfl = 0xFFFF; // clear interrupts
+ MXC_USB->dev_inten |= CONNECT_INTS;
+ MXC_USB->ep[0] |= MXC_F_USB_EP_INT_EN;
+ MXC_USB->dev_cn |= (MXC_F_USB_DEV_CN_CONNECT | MXC_F_USB_DEV_CN_FIFO_MODE);
+ } else {
+ MXC_USB->dev_inten &= ~CONNECT_INTS;
+ MXC_USB->ep[0] &= ~MXC_F_USB_EP_INT_EN;
+ MXC_USB->dev_cn &= ~MXC_F_USB_DEV_CN_CONNECT;
+ }
+}
+
+/*
+ * USB Device Remote Wakeup Configuration Function
+ * Parameters: cfg: Device Enable/Disable
+ * Return Value: None
+ */
+void USBD_WakeUpCfg (BOOL cfg)
+{
+}
+
+/*
+ * USB Device Set Address Function
+ * Parameters: adr: USB Device Address
+ * Return Value: None
+ */
+void USBD_SetAddress (U32 adr, U32 setup)
+{
+ /* Performed by Hardware */
+}
+
+/*
+ * USB Device Configure Function
+ * Parameters: cfg: Device Configure/Deconfigure
+ * Return Value: None
+ */
+void USBD_Configure (BOOL cfg)
+{
+#if CDC_ENDPOINT
+ /* CDC-ACM class processes FIFOs in the SOF interrupt. The USB Device interface
+ * of Maxim's microcontrollers does not provide and SOF interrupt. A periodic
+ * timer interrupt is used instead.
+ */
+
+ #define SOF_INT_US 1000
+
+ if (cfg) {
+ // Setup timer interrupt for SOF
+ MXC_TMR0->ctrl = MXC_S_TMR_CTRL_MODE_CONTINUOUS;
+ MXC_TMR0->count32 = 0;
+ MXC_TMR0->term_cnt32 = (SystemCoreClock / 1000000) * SOF_INT_US;
+
+ // Enable the interrupt
+ MXC_TMR0->intfl = MXC_TMR0->intfl;
+ NVIC_EnableIRQ(TMR0_0_IRQn);
+ MXC_TMR0->inten = MXC_F_TMR_INTEN_TIMER0;
+
+ // Start the timer
+ MXC_TMR0->ctrl |= MXC_F_TMR_CTRL_ENABLE0;
+
+ } else {
+ // Disable tmr
+ MXC_TMR0->ctrl &= ~(MXC_F_TMR_CTRL_ENABLE0);
+ }
+#endif
+}
+
+/*
+ * Configure USB Device Endpoint according to Descriptor
+ * Parameters: pEPD: Pointer to Device Endpoint Descriptor
+ * Return Value: None
+ */
+void USBD_ConfigEP (USB_ENDPOINT_DESCRIPTOR *pEPD)
+{
+ U32 EPNum;
+
+ EPNum = pEPD->bEndpointAddress & EPNUM_MASK;
+
+ if (EPNum < MXC_USB_NUM_EP) {
+
+ // Clear existing configurations
+ MXC_USB->ep[EPNum] = MXC_F_USB_EP_DT;
+
+ if (pEPD->bEndpointAddress & USB_ENDPOINT_DIRECTION_MASK) {
+ ep_info[EPNum].type = MXC_S_USB_EP_DIR_IN;
+ } else {
+ ep_info[EPNum].type = MXC_S_USB_EP_DIR_OUT;
+ }
+
+ ep_info[EPNum].len = pEPD->wMaxPacketSize;
+ }
+}
+
+/*
+ * Set Direction for USB Device Control Endpoint
+ * Parameters: dir: Out (dir == 0), In (dir <> 0)
+ * Return Value: None
+ */
+void USBD_DirCtrlEP (U32 dir)
+{
+ /* Not needed */
+}
+
+/*
+ * Enable USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+void USBD_EnableEP (U32 EPNum)
+{
+ ep_buffer_t *desc = get_desc(EPNum);
+
+ EPNum &= EPNUM_MASK;
+ MXC_USB->ep[EPNum] |= (MXC_F_USB_EP_INT_EN | ep_info[EPNum].type | MXC_F_USB_EP_DT);
+
+ if (ep_info[EPNum].type == MXC_S_USB_EP_DIR_OUT) {
+ // This is an OUT endpoint. Go ahead and register a request.
+ desc = get_desc(EPNum);
+ desc->buf0_address = (uint32_t)ep_buffer[EPNum];
+ desc->buf0_desc = sizeof(ep_buffer[EPNum]);
+ MXC_USB->out_owner = (1 << EPNum);
+ }
+}
+
+/*
+ * Disable USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+void USBD_DisableEP (U32 EPNum)
+{
+ EPNum &= EPNUM_MASK;
+ MXC_USB->ep[EPNum] = 0;
+}
+
+/*
+ * Reset USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+void USBD_ResetEP (U32 EPNum)
+{
+ ep_buffer_t *desc = get_desc(EPNum);
+
+ EPNum &= EPNUM_MASK;
+ MXC_USB->ep[EPNum] |= MXC_F_USB_EP_DT;
+
+ if (ep_info[EPNum].type == MXC_S_USB_EP_DIR_OUT) {
+ // This is an OUT endpoint. Go ahead and register a request.
+ desc = get_desc(EPNum);
+ desc->buf0_address = (uint32_t)ep_buffer[EPNum];
+ desc->buf0_desc = sizeof(ep_buffer[EPNum]);
+ MXC_USB->out_owner = (1 << EPNum);
+ }
+}
+
+/*
+ * Set Stall for USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+void USBD_SetStallEP (U32 EPNum)
+{
+ EPNum &= EPNUM_MASK;
+
+ if (EPNum == 0) {
+ MXC_USB->ep[0] |= (MXC_F_USB_EP_ST_STALL | MXC_F_USB_EP_STALL);
+ } else {
+ MXC_USB->ep[EPNum] |= MXC_F_USB_EP_STALL;
+ }
+}
+
+/*
+ * Clear Stall for USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+void USBD_ClrStallEP (U32 EPNum)
+{
+ USBD_ResetEP(EPNum);
+ MXC_USB->ep[EPNum & EPNUM_MASK] &= ~MXC_F_USB_EP_STALL;
+}
+
+/*
+ * Read USB Device Endpoint Data
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * pData: Pointer to Data Buffer
+ * Return Value: Number of bytes read
+ */
+U32 USBD_ReadEP (U32 EPNum, U8 *pData, U32 size)
+{
+ U32 cnt;
+ ep_buffer_t *desc = get_desc(EPNum);
+ USB_SETUP_PACKET *sup;
+
+ EPNum &= EPNUM_MASK;
+
+ if ((EPNum == 0) && setup_waiting) {
+ cnt = USBD_MAX_PACKET0;
+
+ if (size < cnt) {
+ cnt = size;
+ }
+ setup_waiting = 0;
+ memcpy(pData, (void*)&MXC_USB->setup0, cnt);
+ sup = (USB_SETUP_PACKET*)pData;
+
+ if ( (sup->bmRequestType.Dir == REQUEST_HOST_TO_DEVICE) && (sup->wLength > 0) ) {
+ // There is an OUT stage for this setup packet. Register a request.
+ if (!(MXC_USB->out_owner & 1)) {
+ desc = &ep_buffer_descriptor.ep0.out_buffer;
+ desc->buf0_address = (uint32_t)ep_buffer[0];
+ desc->buf0_desc = sup->wLength;
+ MXC_USB->out_owner = 1;
+ }
+ }
+ } else {
+ cnt = desc->buf0_desc;
+
+ if (size < cnt) {
+ cnt = size;
+ }
+ memcpy(pData, ep_buffer[EPNum], cnt);
+
+ // Register the next request.
+ desc->buf0_address = (uint32_t)ep_buffer[EPNum];
+ desc->buf0_desc = sizeof(ep_buffer[EPNum]);
+ MXC_USB->out_owner = (1 << EPNum);
+ }
+
+ return cnt;
+}
+
+/*
+ * Write USB Device Endpoint Data
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * pData: Pointer to Data Buffer
+ * cnt: Number of bytes to write
+ * Return Value: Number of bytes written
+ */
+U32 USBD_WriteEP (U32 EPNum, U8 *pData, U32 cnt)
+{
+ ep_buffer_t *desc = get_desc(EPNum);
+ uint32_t mask;
+
+ EPNum &= EPNUM_MASK;
+ mask = (1 << EPNum);
+
+ if (MXC_USB->in_owner & mask) {
+ return 0;
+ }
+
+ if (EPNum == 0) {
+ // Prepare to ACK the status stage.
+ MXC_USB->ep[0] |= MXC_F_USB_EP_ST_ACK;
+
+ if ((cnt == 0) && !ep0_expect_zlp) {
+ // This is a status stage ACK. Handled in hardware.
+ return 0;
+ } else if (cnt == USBD_MAX_PACKET0) {
+ ep0_expect_zlp = 1;
+ } else {
+ ep0_expect_zlp = 0;
+ }
+ }
+
+ if (cnt > MXC_USB_MAX_PACKET) {
+ cnt = MXC_USB_MAX_PACKET;
+ }
+
+ /* prepare data to be sent */
+ memcpy(ep_buffer[EPNum], pData, cnt);
+ desc->buf0_address = (uint32_t)ep_buffer[EPNum];
+ desc->buf0_desc = cnt;
+
+ /* start the transaction */
+ MXC_USB->in_owner = mask;
+
+ return cnt;
+}
+
+/*
+ * USB Device Interrupt Service Routine
+ */
+void USB_IRQHandler (void)
+{
+ NVIC_DisableIRQ(USB_IRQn);
+ USBD_SignalHandler();
+}
+
+void USBD_Handler(void)
+{
+
+#ifdef __RTX
+ while(1) {}
+#else
+
+#endif
+
+ uint32_t irq_flags;
+ unsigned int ep;
+ uint32_t ep_int, mask;
+
+ // Read and clear interrupts
+ irq_flags = MXC_USB->dev_intfl;
+ MXC_USB->dev_intfl = irq_flags;
+
+ /* reset interrupt */
+ if (irq_flags & MXC_F_USB_DEV_INTFL_BRST) {
+ if (suspended) {
+ suspended = 0;
+#ifdef __RTX
+ if (USBD_RTX_DevTask) { isr_evt_set(USBD_EVT_RESUME, USBD_RTX_DevTask); }
+#else
+ if (USBD_P_Resume_Event) { USBD_P_Resume_Event(); }
+#endif
+ }
+
+ reset_state();
+ usbd_reset_core();
+
+#ifdef __RTX
+ if (USBD_RTX_DevTask) { isr_evt_set(USBD_EVT_RESET, USBD_RTX_DevTask); }
+#else
+ if (USBD_P_Reset_Event) { USBD_P_Reset_Event(); }
+#endif
+
+ }
+
+ /* reset done interrupt */
+ if (irq_flags & MXC_F_USB_DEV_INTFL_BRST_DN) {
+ reset_state();
+ }
+
+ /* suspend interrupt */
+ if (irq_flags & MXC_F_USB_DEV_INTFL_SUSP) {
+ suspended = 1;
+#ifdef __RTX
+ if (USBD_RTX_DevTask) { isr_evt_set(USBD_EVT_SUSPEND, USBD_RTX_DevTask); }
+#else
+ if (USBD_P_Suspend_Event) { USBD_P_Suspend_Event(); }
+#endif
+ }
+
+ if (irq_flags & MXC_F_USB_DEV_INTFL_VBUS) {
+#ifdef __RTX
+ if (USBD_RTX_DevTask) { isr_evt_set(USBD_EVT_POWER_ON, USBD_RTX_DevTask); }
+#else
+ if (USBD_P_Power_Event) { USBD_P_Power_Event(1); }
+#endif
+ }
+
+ if (irq_flags & MXC_F_USB_DEV_INTFL_NO_VBUS) {
+#ifdef __RTX
+ if (USBD_RTX_DevTask) { isr_evt_set(USBD_EVT_POWER_OFF, USBD_RTX_DevTask); }
+#else
+ if (USBD_P_Power_Event) { USBD_P_Power_Event(0); }
+#endif
+ }
+
+ if (irq_flags & MXC_F_USB_DEV_INTFL_SETUP) {
+ setup_waiting = 1;
+#ifdef __RTX
+ if (USBD_RTX_EPTask[0]) { isr_evt_set(USBD_EVT_SETUP, USBD_RTX_EPTask[0]); }
+#else
+ if (USBD_P_EP[0]) { USBD_P_EP[0](USBD_EVT_SETUP); }
+#endif
+ }
+
+ if (irq_flags & MXC_F_USB_DEV_INTFL_EP_IN) {
+
+ // Read and clear endpoint interrupts
+ ep_int = MXC_USB->in_int;
+ MXC_USB->in_int = ep_int;
+
+ mask = 1;
+ for (ep = 0; ep < MXC_USB_NUM_EP; ep++) {
+ if (ep_int & mask) {
+#ifdef __RTX
+ if (USBD_RTX_EPTask[ep]) { isr_evt_set(USBD_EVT_IN, USBD_RTX_EPTask[ep]); }
+#else
+ if (USBD_P_EP[ep]) { USBD_P_EP[ep](USBD_EVT_IN); }
+#endif
+ }
+
+ mask <<= 1;
+ }
+ }
+
+ if (irq_flags & MXC_F_USB_DEV_INTFL_EP_OUT) {
+
+ // Read and clear endpoint interrupts
+ ep_int = MXC_USB->out_int;
+ MXC_USB->out_int = ep_int;
+
+ mask = 1;
+ for (ep = 0; ep < MXC_USB_NUM_EP; ep++) {
+ if (ep_int & mask) {
+#ifdef __RTX
+ if (USBD_RTX_EPTask[ep]) { isr_evt_set(USBD_EVT_OUT, USBD_RTX_EPTask[ep]); }
+#else
+ if (USBD_P_EP[ep]) { USBD_P_EP[ep](USBD_EVT_OUT); }
+#endif
+ }
+
+ mask <<= 1;
+ }
+ }
+
+ if (irq_flags & MXC_F_USB_DEV_INTFL_DMA_ERR) {
+ // Read and clear endpoint interrupts
+ ep_int = MXC_USB->dma_err_int;
+ MXC_USB->dma_err_int = ep_int;
+ while(1); // not recoverable
+ }
+
+ NVIC_EnableIRQ(USB_IRQn);
+
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/DAP_config.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32625/DAP_config.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,531 @@
+/**
+ * @file DAP_config.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __DAP_CONFIG_H__
+#define __DAP_CONFIG_H__
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
+\ingroup DAP_ConfigIO_gr
+@{
+Provides definitions about:
+ - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
+ - Debug Unit communication packet size.
+ - Debug Access Port communication mode (JTAG or SWD).
+ - Optional information about a connected Target Device (for Evaluation Boards).
+*/
+
+#include <stdio.h>
+#include "max32625.h"
+#include "clkman_regs.h"
+#include "gpio_regs.h"
+#include "IO_Config.h"
+
+/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
+/// This value is used to calculate the SWD/JTAG clock speed.
+#define CPU_CLOCK SystemCoreClock ///< Specifies the CPU Clock in Hz
+
+/// Number of processor cycles for I/O Port write operations.
+/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
+/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
+/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
+/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
+/// required.
+#define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
+
+/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available
+
+/// Indicate that JTAG communication mode is available at the Debug Port.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available.
+
+/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
+/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
+#define DAP_JTAG_DEV_CNT 0 ///< Maximum number of JTAG devices on scan chain
+
+/// Default communication mode on the Debug Access Port.
+/// Used for the command \ref DAP_Connect when Port Default mode is selected.
+#define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
+
+/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
+/// Used to initialize the default SWD/JTAG clock frequency.
+/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
+#define DAP_DEFAULT_SWJ_CLOCK 5000000 ///< Default SWD/JTAG clock frequency in Hz.
+
+/// Maximum Package Size for Command and Response data.
+/// This configuration settings is used to optimized the communication performance with the
+/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
+#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed.
+
+/// Maximum Package Buffers for Command and Response data.
+/// This configuration settings is used to optimized the communication performance with the
+/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
+/// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
+#define DAP_PACKET_COUNT 4 ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
+
+/// Indicate that UART Serial Wire Output (SWO) trace is available.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available
+
+/// Maximum SWO UART Baudrate
+#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz
+
+/// Indicate that Manchester Serial Wire Output (SWO) trace is available.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available
+
+/// SWO Trace Buffer Size.
+#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n)
+
+/// SWO Streaming Trace.
+#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available.
+
+/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
+#define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported).
+
+/// Debug Unit is connected to fixed Target Device.
+/// The Debug Unit may be part of an evaluation board and always connected to a fixed
+/// known device. In this case a Device Vendor and Device Name string is stored which
+/// may be used by the debugger or IDE to configure device parameters.
+#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
+
+#if TARGET_DEVICE_FIXED
+#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor
+#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device
+#endif
+
+///@}
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
+\ingroup DAP_ConfigIO_gr
+@{
+
+Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
+and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
+interface of a device. The following I/O Pins are provided:
+
+JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
+---------------------------- | -------------------- | ---------------------------------------------
+TCK: Test Clock | SWCLK: Clock | Output Push/Pull
+TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
+TDI: Test Data Input | | Output Push/Pull
+TDO: Test Data Output | | Input
+nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
+nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
+
+
+DAP Hardware I/O Pin Access Functions
+-------------------------------------
+The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
+these I/O Pins.
+
+For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
+This functions are provided to achieve faster I/O that is possible with some advanced GPIO
+peripherals that can independently write/read a single I/O pin without affecting any other pins
+of the same I/O port. The following SWDIO I/O Pin functions are provided:
+ - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
+ - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
+ - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
+ - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
+*/
+
+extern volatile uint32_t *tck_in;
+extern volatile uint32_t *tck_out;
+extern volatile uint32_t *tms_in;
+extern volatile uint32_t *tms_out;
+extern volatile uint32_t *rst_in;
+extern volatile uint32_t *rst_out;
+
+extern uint32_t swdio_port;
+extern uint32_t swdio_pin;
+extern uint32_t swclk_port;
+extern uint32_t swclk_pin;
+extern uint32_t nreset_port;
+extern uint32_t nreset_pin;
+
+// Configure DAP I/O pins ------------------------------
+
+/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
+Configures the DAP Hardware I/O pins for JTAG mode:
+ - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
+ - TDO to input mode.
+*/
+__STATIC_INLINE void PORT_JTAG_SETUP (void)
+{
+}
+
+/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
+Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
+ - SWCLK, SWDIO, nRESET to output mode and set to default high level.
+ - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
+*/
+__STATIC_INLINE void PORT_SWD_SETUP (void)
+{
+ uint32_t out_mode;
+
+ // Ensure that the GPIO clock is enabled
+ if (MXC_CLKMAN->sys_clk_ctrl_6_gpio == MXC_V_CLKMAN_CLK_SCALE_DISABLED) {
+ MXC_CLKMAN->sys_clk_ctrl_6_gpio = MXC_V_CLKMAN_CLK_SCALE_DIV_1;
+ }
+
+ // Initial state
+ MXC_GPIO->out_val[swclk_port] |= (1 << swclk_pin);
+ MXC_GPIO->out_val[swdio_port] |= (1 << swdio_pin);
+ MXC_GPIO->out_val[nreset_port] |= (1 << nreset_pin);
+
+ // Output mode
+ out_mode = MXC_GPIO->out_mode[swclk_port];
+ out_mode &= ~(0xFU << (4 * swclk_pin));
+ out_mode |= (MXC_V_GPIO_OUT_MODE_NORMAL << (4 * swclk_pin));
+ MXC_GPIO->out_mode[swclk_port] = out_mode;
+
+ out_mode = MXC_GPIO->out_mode[swdio_port];
+ out_mode &= ~(0xFU << (4 * swdio_pin));
+ out_mode |= (MXC_V_GPIO_OUT_MODE_NORMAL << (4 * swdio_pin));
+ MXC_GPIO->out_mode[swdio_port] = out_mode;
+
+ out_mode = MXC_GPIO->out_mode[nreset_port];
+ out_mode &= ~(0xFU << (4 * nreset_pin));
+ out_mode |= (MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << (4 * nreset_pin));
+ MXC_GPIO->out_mode[nreset_port] = out_mode;
+
+ tck_in = (volatile uint32_t *)BITBAND(&MXC_GPIO->in_val[swclk_port], swclk_pin);
+ tck_out = (volatile uint32_t *)BITBAND(&MXC_GPIO->out_val[swclk_port], swclk_pin);
+ tms_in = (volatile uint32_t *)BITBAND(&MXC_GPIO->in_val[swdio_port], swdio_pin);
+ tms_out = (volatile uint32_t *)BITBAND(&MXC_GPIO->out_val[swdio_port], swdio_pin);
+ rst_in = (volatile uint32_t *)BITBAND(&MXC_GPIO->in_val[nreset_port], nreset_pin);
+ rst_out = (volatile uint32_t *)BITBAND(&MXC_GPIO->out_val[nreset_port], nreset_pin);
+}
+
+/** Disable JTAG/SWD I/O Pins.
+Disables the DAP Hardware I/O pins which configures:
+ - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
+*/
+__STATIC_INLINE void PORT_OFF (void)
+{
+ uint32_t out_mode;
+
+ // Disable weak pullup in high-z output mode
+ MXC_GPIO->out_val[swclk_port] &= ~(1 << swclk_pin);
+ MXC_GPIO->out_val[swdio_port] &= ~(1 << swdio_pin);
+ MXC_GPIO->out_val[nreset_port] &= ~(1 << nreset_pin);
+
+ // High-z output mode
+ out_mode = MXC_GPIO->out_mode[swclk_port];
+ out_mode &= ~(0xFU << (4 * swclk_pin));
+ out_mode |= (MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << (4 * swclk_pin));
+ MXC_GPIO->out_mode[swclk_port] = out_mode;
+
+ out_mode = MXC_GPIO->out_mode[swdio_port];
+ out_mode &= ~(0xFU << (4 * swdio_pin));
+ out_mode |= (MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << (4 * swdio_pin));
+ MXC_GPIO->out_mode[swdio_port] = out_mode;
+
+ out_mode = MXC_GPIO->out_mode[nreset_port];
+ out_mode &= ~(0xFU << (4 * nreset_pin));
+ out_mode |= (MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << (4 * nreset_pin));
+ MXC_GPIO->out_mode[nreset_port] = out_mode;
+}
+
+// SWCLK/TCK I/O pin -------------------------------------
+
+/** SWCLK/TCK I/O pin: Get Input.
+\return Current status of the SWCLK/TCK DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void)
+{
+ return *tck_in;
+}
+
+/** SWCLK/TCK I/O pin: Set Output to High.
+Set the SWCLK/TCK DAP hardware I/O pin to high level.
+*/
+__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET (void)
+{
+ *tck_out = 1;
+}
+
+/** SWCLK/TCK I/O pin: Set Output to Low.
+Set the SWCLK/TCK DAP hardware I/O pin to low level.
+*/
+__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void)
+{
+ *tck_out = 0;
+}
+
+// SWDIO/TMS Pin I/O --------------------------------------
+
+/** SWDIO/TMS I/O pin: Get Input.
+\return Current status of the SWDIO/TMS DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN (void)
+{
+ return *tms_in;
+}
+
+/** SWDIO/TMS I/O pin: Set Output to High.
+Set the SWDIO/TMS DAP hardware I/O pin to high level.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET (void)
+{
+ *tms_out = 1;
+}
+
+/** SWDIO/TMS I/O pin: Set Output to Low.
+Set the SWDIO/TMS DAP hardware I/O pin to low level.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR (void)
+{
+ *tms_out = 0;
+}
+
+/** SWDIO I/O pin: Get Input (used in SWD mode only).
+\return Current status of the SWDIO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN (void)
+{
+ return *tms_in;
+}
+
+/** SWDIO I/O pin: Set Output (used in SWD mode only).
+\param bit Output value for the SWDIO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT (uint32_t bit)
+{
+ *tms_out = bit & 1;
+}
+
+/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
+Configure the SWDIO DAP hardware I/O pin to output mode. This function is
+called prior \ref PIN_SWDIO_OUT function calls.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void)
+{
+ uint32_t out_mode;
+
+ out_mode = MXC_GPIO->out_mode[swdio_port];
+ out_mode &= ~(0xFU << (4 * swdio_pin));
+ out_mode |= (MXC_V_GPIO_OUT_MODE_NORMAL << (4 * swdio_pin));
+ MXC_GPIO->out_mode[swdio_port] = out_mode;
+}
+
+/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
+Configure the SWDIO DAP hardware I/O pin to input mode. This function is
+called prior \ref PIN_SWDIO_IN function calls.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE (void)
+{
+ uint32_t out_mode;
+
+ out_mode = MXC_GPIO->out_mode[swdio_port];
+ out_mode &= ~(0xFU << (4 * swdio_pin));
+ MXC_GPIO->out_mode[swdio_port] = out_mode;
+ MXC_GPIO->out_val[swdio_port] &= ~(1 << swdio_pin);
+}
+
+// TDI Pin I/O ---------------------------------------------
+
+/** TDI I/O pin: Get Input.
+\return Current status of the TDI DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_TDI_IN (void)
+{
+ return 0;
+}
+
+/** TDI I/O pin: Set Output.
+\param bit Output value for the TDI DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE void PIN_TDI_OUT (uint32_t bit)
+{
+}
+
+// TDO Pin I/O ---------------------------------------------
+
+/** TDO I/O pin: Get Input.
+\return Current status of the TDO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_TDO_IN (void)
+{
+ return 0;
+}
+
+// nTRST Pin I/O -------------------------------------------
+
+/** nTRST I/O pin: Get Input.
+\return Current status of the nTRST DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN (void)
+{
+ return 0;
+}
+
+/** nTRST I/O pin: Set Output.
+\param bit JTAG TRST Test Reset pin status:
+ - 0: issue a JTAG TRST Test Reset.
+ - 1: release JTAG TRST Test Reset.
+*/
+__STATIC_FORCEINLINE void PIN_nTRST_OUT (uint32_t bit)
+{
+}
+
+// nRESET Pin I/O------------------------------------------
+
+/** nRESET I/O pin: Get Input.
+\return Current status of the nRESET DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN (void)
+{
+ return *rst_in;
+}
+
+/** nRESET I/O pin: Set Output.
+\param bit target device hardware reset pin status:
+ - 0: issue a device hardware reset.
+ - 1: release device hardware reset.
+*/
+__STATIC_FORCEINLINE void PIN_nRESET_OUT (uint32_t bit)
+{
+ *rst_out = bit & 1;
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
+\ingroup DAP_ConfigIO_gr
+@{
+
+CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
+
+It is recommended to provide the following LEDs for status indication:
+ - Connect LED: is active when the DAP hardware is connected to a debugger.
+ - Running LED: is active when the debugger has put the target device into running state.
+*/
+
+/** Debug Unit: Set status of Connected LED.
+\param bit status of the Connect LED.
+ - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
+ - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
+*/
+__STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit)
+{
+}
+
+/** Debug Unit: Set status Target Running LED.
+\param bit status of the Target Running LED.
+ - 1: Target Running LED ON: program execution in target started.
+ - 0: Target Running LED OFF: program execution in target stopped.
+*/
+__STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit)
+{
+}
+
+///@}
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
+\ingroup DAP_ConfigIO_gr
+@{
+Access function for Test Domain Timer.
+
+The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
+default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
+
+*/
+
+/** Get timestamp of Test Domain Timer.
+\return Current timestamp value.
+*/
+__STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
+ return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK);
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
+\ingroup DAP_ConfigIO_gr
+@{
+
+CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
+*/
+
+/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
+This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
+Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
+ - I/O clock system enabled.
+ - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
+ - for nTRST, nRESET a weak pull-up (if available) is enabled.
+ - LED output pins are enabled and LEDs are turned off.
+*/
+__STATIC_INLINE void DAP_SETUP (void)
+{
+ uint32_t out_mode;
+
+ // Weak pull-up disabled
+ MXC_GPIO->out_val[swclk_port] &= ~(1 << swclk_pin);
+ MXC_GPIO->out_val[swdio_port] &= ~(1 << swdio_pin);
+ // Weak pull-up enabled
+ MXC_GPIO->out_val[nreset_port] |= (1 << nreset_pin);
+
+ // High-Z output mode
+ out_mode = MXC_GPIO->out_mode[swclk_port];
+ out_mode &= ~(0xFU << (4 * swclk_pin));
+ out_mode |= (MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << (4 * swclk_pin));
+ MXC_GPIO->out_mode[swclk_port] = out_mode;
+
+ out_mode = MXC_GPIO->out_mode[swdio_port];
+ out_mode &= ~(0xFU << (4 * swdio_pin));
+ out_mode |= (MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << (4 * swdio_pin));
+ MXC_GPIO->out_mode[swdio_port] = out_mode;
+
+ out_mode = MXC_GPIO->out_mode[nreset_port];
+ out_mode &= ~(0xFU << (4 * nreset_pin));
+ out_mode |= (MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << (4 * nreset_pin));
+ MXC_GPIO->out_mode[nreset_port] = out_mode;
+}
+
+/** Reset Target Device with custom specific I/O pin or command sequence.
+This function allows the optional implementation of a device specific reset sequence.
+It is called when the command \ref DAP_ResetTarget and is for example required
+when a device needs a time-critical unlock sequence that enables the debug port.
+\return 0 = no device specific reset sequence is implemented.\n
+ 1 = a device specific reset sequence is implemented.
+*/
+__STATIC_INLINE uint32_t RESET_TARGET (void)
+{
+ return (0); // change to '1' when a device reset sequence is implemented
+}
+
+///@}
+
+#endif /* __DAP_CONFIG_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/FlashPrg.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32625/FlashPrg.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,208 @@
+/* CMSIS-DAP Interface Firmware
+ * Copyright (c) 2009-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "FlashOS.h"
+#include "max32625.h"
+#include "flc_regs.h"
+
+/******************************************************************************/
+static inline int FLC_Busy(void)
+{
+ return (MXC_FLC->ctrl & (MXC_F_FLC_CTRL_WRITE | MXC_F_FLC_CTRL_MASS_ERASE | MXC_F_FLC_CTRL_PAGE_ERASE));
+}
+
+/******************************************************************************/
+uint32_t Init(uint32_t adr, uint32_t clk, uint32_t fnc)
+{
+ /* Check if the flash controller is busy */
+ if (FLC_Busy()) {
+ return 1;
+ }
+
+ /* Enable automatic calculation of the clock divider to generate a 1MHz clock from the APB clock */
+ MXC_FLC->perform |= MXC_F_FLC_PERFORM_AUTO_CLKDIV;
+
+ /* The flash controller will stall any reads while flash operations are in
+ * progress. Disable the legacy failure detection logic that would flag reads
+ * during flash operations as errors.
+ */
+ MXC_FLC->perform |= MXC_F_FLC_PERFORM_EN_PREVENT_FAIL;
+
+ return 0;
+}
+
+/******************************************************************************/
+uint32_t UnInit(uint32_t fnc)
+{
+ /* Lock flash */
+ MXC_FLC->ctrl &= ~MXC_F_FLC_CTRL_FLSH_UNLOCK;
+
+ return 0; // Finished without Errors
+}
+
+/******************************************************************************/
+/*
+ * Erase complete Flash Memory
+ * Return Value: 0 - OK, 1 - Failed
+ */
+int EraseChip(void)
+{
+ /* Check if the flash controller is busy */
+ if (FLC_Busy()) {
+ return 1;
+ }
+
+ /* Clear stale errors. Interrupt flags can only be written to zero, so this is safe */
+ MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
+
+ /* Unlock flash */
+ MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_FLSH_UNLOCK) | (MXC_V_FLC_FLSH_UNLOCK_KEY << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS);
+
+ /* Write the Erase Code */
+ MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_ERASE_CODE) | (MXC_V_FLC_ERASE_CODE_MASS_ERASE << MXC_F_FLC_CTRL_ERASE_CODE_POS);
+
+ /* Start the mass erase */
+ MXC_FLC->ctrl |= MXC_F_FLC_CTRL_MASS_ERASE;
+
+ /* Wait until flash operation is complete */
+ while (FLC_Busy());
+
+ /* Lock flash */
+ MXC_FLC->ctrl &= ~(MXC_F_FLC_CTRL_FLSH_UNLOCK | MXC_F_FLC_CTRL_ERASE_CODE);
+
+ /* Check for failures */
+ if (MXC_FLC->intr & MXC_F_FLC_INTR_FAILED_IF) {
+ /* Interrupt flags can only be written to zero, so this is safe */
+ MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
+ return 1;
+ }
+
+ return 0;
+}
+
+/******************************************************************************/
+/*
+ * Erase Sector in Flash Memory
+ * Parameter: address: Sector Address
+ * Return Value: 0 - OK, 1 - Failed
+ */
+int EraseSector(unsigned long address)
+{
+ /* Wait until flash operation is complete */
+ while (FLC_Busy());
+
+ /* Clear stale errors. Interrupt flags can only be written to zero, so this is safe */
+ MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
+
+ /* Unlock flash */
+ MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_FLSH_UNLOCK) | (MXC_V_FLC_FLSH_UNLOCK_KEY << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS);
+
+ /* Write page erase code */
+ MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_ERASE_CODE) | (MXC_V_FLC_ERASE_CODE_PAGE_ERASE << MXC_F_FLC_CTRL_ERASE_CODE_POS);
+
+ /* Erase the request page */
+ MXC_FLC->faddr = address;
+ MXC_FLC->ctrl |= MXC_F_FLC_CTRL_PAGE_ERASE;
+
+ /* Wait until flash operation is complete */
+ while (FLC_Busy());
+
+ /* Lock flash */
+ MXC_FLC->ctrl &= ~(MXC_F_FLC_CTRL_FLSH_UNLOCK | MXC_F_FLC_CTRL_ERASE_CODE);
+
+ /* Check for failures */
+ if (MXC_FLC->intr & MXC_F_FLC_INTR_FAILED_IF) {
+ /* Interrupt flags can only be written to zero, so this is safe */
+ MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
+ return 1;
+ }
+
+ return 0;
+}
+
+/******************************************************************************/
+/*
+ * Program Page in Flash Memory
+ * Parameter: address: Page Start Address
+ * size: Page Size
+ * buffer: Page Data
+ * Return Value: 0 - OK, 1 - Failed
+ */
+int ProgramPage(unsigned long address, unsigned long size, unsigned char *buffer8)
+{
+ unsigned long remaining = size;
+ unsigned long *buffer = (unsigned long *)buffer8;
+
+ // Only accept 32-bit aligned pointers
+ if ((unsigned long)buffer8 & 0x3) {
+ return 1;
+ }
+ buffer = (unsigned long *)buffer8;
+
+ /* Check if the flash controller is busy */
+ if (FLC_Busy()) {
+ return 1;
+ }
+
+ /* Unlock flash */
+ MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_FLSH_UNLOCK) | (MXC_V_FLC_FLSH_UNLOCK_KEY << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS);
+
+ while (remaining >= 4) {
+ MXC_FLC->faddr = address;
+ MXC_FLC->fdata = *buffer++;
+ MXC_FLC->ctrl |= MXC_F_FLC_CTRL_WRITE_ENABLE;
+ MXC_FLC->ctrl |= MXC_F_FLC_CTRL_WRITE;
+
+ /* Wait until flash operation is complete */
+ while (FLC_Busy());
+
+ address += 4;
+ remaining -= 4;
+ }
+
+ if (remaining > 0) {
+ uint32_t last_word;
+ uint32_t mask;
+
+ last_word = 0xffffffff;
+ mask = 0xff;
+
+ while (remaining > 0) {
+ last_word &= (*buffer | ~mask);
+ mask <<= 8;
+ remaining--;
+ }
+
+ MXC_FLC->faddr = address;
+ MXC_FLC->fdata = last_word;
+ MXC_FLC->ctrl |= MXC_F_FLC_CTRL_WRITE_ENABLE;
+
+ /* Wait until flash operation is complete */
+ while (FLC_Busy());
+ }
+
+ /* Lock flash */
+ MXC_FLC->ctrl &= ~MXC_F_FLC_CTRL_FLSH_UNLOCK;
+
+ /* Check for failures */
+ if (MXC_FLC->intr & MXC_F_FLC_INTR_FAILED_IF) {
+ /* Interrupt flags can only be written to zero, so this is safe */
+ MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
+ return 1;
+ }
+
+ return 0;
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/IO_Config.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32625/IO_Config.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,105 @@
+/**
+ * @file IO_Config.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __IO_CONFIG_H__
+#define __IO_CONFIG_H__
+
+#include "max32625.h"
+
+#define EN_VDDIOH_PORT 3
+#define EN_VDDIOH_PIN 6
+
+// The MAX14689 is powered with this pin
+#define IOH_OW_EN_PORT 2
+#define IOH_OW_EN_PIN 2
+
+// Low selects NC pins HDR_OW and HDR_VIO
+// High selcts NO pins SWD_OW and SWD_VIO
+#define SWD_DIP_SEL_PORT 2
+#define SWD_DIP_SEL_PIN 3
+
+// UART Tx
+#define PIN_TX_PORT 2
+#define PIN_TX_PIN 0
+#define PIN_DIP_TX_PORT 0
+#define PIN_DIP_TX_PIN 0
+
+// UART Rx
+#define PIN_RX_PORT 2
+#define PIN_RX_PIN 1
+#define PIN_DIP_RX_PORT 0
+#define PIN_DIP_RX_PIN 1
+
+// DAP LED
+#define PIN_DAP_LED_PORT 2
+#define PIN_DAP_LED_PIN 5
+
+// MSD LED
+#define PIN_MSD_LED_PORT 2
+#define PIN_MSD_LED_PIN 4
+
+// CDC LED
+#define PIN_CDC_LED_PORT 2
+#define PIN_CDC_LED_PIN 6
+
+// Non-Forwarded Reset In Pin
+#define PIN_RESET_IN_NO_FWRD_PORT 2
+#define PIN_RESET_IN_NO_FWRD_PIN 7
+
+// nRESET
+#define PIN_nRESET_PORT 3
+#define PIN_nRESET_PIN 7
+#define PIN_DIP_nRESET_PORT 0
+#define PIN_DIP_nRESET_PIN 4
+
+// SWCLK
+#define PIN_SWCLK_PORT 3
+#define PIN_SWCLK_PIN 2
+#define PIN_DIP_SWCLK_PORT 0
+#define PIN_DIP_SWCLK_PIN 2
+
+// SWDIO
+#define PIN_SWDIO_PORT 3
+#define PIN_SWDIO_PIN 3
+#define PIN_DIP_SWDIO_PORT 0
+#define PIN_DIP_SWDIO_PIN 3
+
+// 1-Wire master I/O
+#define OWM_PORT 4
+#define OWM_PIN 0
+#define OWM_SUP_PORT 4
+#define OWM_SUP_PIN 1
+
+// ADC channels for target detection
+#define SWD_VIO_CH 5
+#define HDR_VIO_CH 4
+#define SWD_GNDDET_CH 3
+#define HDR_GNDDET_CH 2
+
+typedef enum {
+ IO_SWD_EXT,
+ IO_DIP_EXT
+} TARGET_INTERFACE;
+
+#define CDC_ACM_UART_SWD 2
+#define CDC_ACM_UART_DIP 0
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/adc_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32625/adc_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,383 @@
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_ADC_REGS_H_
+#define _MXC_ADC_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/// @cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @defgroup adc_registers Registers
+ * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module.
+ * @ingroup adc
+ * @{
+ */
+
+/**
+ * Structure type to access the ADC Registers.
+ */
+typedef struct {
+ __IO uint32_t ctrl; /**< <tt>\b 0x000:</tt> ADC CTRL Register */
+ __IO uint32_t status; /**< <tt>\b 0x004:</tt> ADC STATUS Register */
+ __IO uint32_t data; /**< <tt>\b 0x008:</tt> ADC DATA Register */
+ __IO uint32_t intr; /**< <tt>\b 0x00C:</tt> ADC INTR Register */
+ __IO uint32_t limit[4]; /**< <tt>\b 0x010:</tt> ADC LIMIT0, LIMIT1, LIMIT2, LIMIT3 Register */
+ __IO uint32_t afe_ctrl; /**< <tt>\b 0x020:</tt> ADC AFE_CTRL Register */
+ __IO uint32_t ro_cal0; /**< <tt>\b 0x024:</tt> ADC RO_CAL0 Register */
+ __IO uint32_t ro_cal1; /**< <tt>\b 0x028:</tt> ADC RO_CAL1 Register */
+ __IO uint32_t ro_cal2; /**< <tt>\b 0x02C:</tt> ADC RO_CAL2 Register */
+} mxc_adc_regs_t;
+/**@} end of group adc_registers */
+
+
+/* Register offsets for module ADC. */
+/**
+ * @defgroup ADC_Register_Offsets Register Offsets
+ * @ingroup adc_registers
+ * @brief ADC Peripheral Register Offsets from the ADC Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_ADC_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from ADC Base Address: <tt>\b 0x000</tt> */
+#define MXC_R_ADC_OFFS_STATUS ((uint32_t)0x00000004UL) /**< Offset from ADC Base Address: <tt>\b 0x004</tt> */
+#define MXC_R_ADC_OFFS_DATA ((uint32_t)0x00000008UL) /**< Offset from ADC Base Address: <tt>\b 0x008</tt> */
+#define MXC_R_ADC_OFFS_INTR ((uint32_t)0x0000000CUL) /**< Offset from ADC Base Address: <tt>\b 0x00C</tt> */
+#define MXC_R_ADC_OFFS_LIMIT0 ((uint32_t)0x00000010UL) /**< Offset from ADC Base Address: <tt>\b 0x010</tt> */
+#define MXC_R_ADC_OFFS_LIMIT1 ((uint32_t)0x00000014UL) /**< Offset from ADC Base Address: <tt>\b 0x014</tt> */
+#define MXC_R_ADC_OFFS_LIMIT2 ((uint32_t)0x00000018UL) /**< Offset from ADC Base Address: <tt>\b 0x018</tt> */
+#define MXC_R_ADC_OFFS_LIMIT3 ((uint32_t)0x0000001CUL) /**< Offset from ADC Base Address: <tt>\b 0x01C</tt> */
+#define MXC_R_ADC_OFFS_AFE_CTRL ((uint32_t)0x00000020UL) /**< Offset from ADC Base Address: <tt>\b 0x020</tt> */
+#define MXC_R_ADC_OFFS_RO_CAL0 ((uint32_t)0x00000024UL) /**< Offset from ADC Base Address: <tt>\b 0x024</tt> */
+#define MXC_R_ADC_OFFS_RO_CAL1 ((uint32_t)0x00000028UL) /**< Offset from ADC Base Address: <tt>\b 0x028</tt> */
+#define MXC_R_ADC_OFFS_RO_CAL2 ((uint32_t)0x0000002CUL) /**< Offset from ADC Base Address: <tt>\b 0x02C</tt> */
+/**@} end of group adc_registers */
+
+/**
+ * @defgroup ADC_CTRL_Register ADC_CTRL
+ * @brief Field Positions and Bit Masks for the ADC_CTRL register
+ * @ingroup adc_registers
+ * @{
+ */
+#define MXC_F_ADC_CTRL_CPU_ADC_START_POS 0 /**< CPU_ADC_START Position */
+#define MXC_F_ADC_CTRL_CPU_ADC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_CPU_ADC_START_POS)) /**< CPU_ADC_START Mask */
+#define MXC_F_ADC_CTRL_ADC_PU_POS 1 /**< ADC_PU Position */
+#define MXC_F_ADC_CTRL_ADC_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_PU_POS)) /**< ADC_PU Mask */
+#define MXC_F_ADC_CTRL_BUF_PU_POS 2 /**< BUF_PU Position */
+#define MXC_F_ADC_CTRL_BUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PU_POS)) /**< BUF_PU Mask */
+#define MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS 3 /**< REFBUF_PU Position */
+#define MXC_F_ADC_CTRL_ADC_REFBUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS)) /**< REFBUF_PU Mask */
+#define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS 4 /**< CHGPUMP_PU Position */
+#define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS)) /**< CHGPUMP_PU Mask */
+#define MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS 5 /**< BUF_CHOP_DIS Position */
+#define MXC_F_ADC_CTRL_BUF_CHOP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS)) /**< BUF_CHOP_DIS Mask */
+#define MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS 6 /**< BUF_PUMP_DIS Position */
+#define MXC_F_ADC_CTRL_BUF_PUMP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS)) /**< BUF_PUMP_DIS Mask */
+#define MXC_F_ADC_CTRL_BUF_BYPASS_POS 7 /**< BUF_BYPASS Position */
+#define MXC_F_ADC_CTRL_BUF_BYPASS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_BYPASS_POS)) /**< BUF_BYPASS Mask */
+#define MXC_F_ADC_CTRL_ADC_REFSCL_POS 8 /**< ADC_REFSCL Position */
+#define MXC_F_ADC_CTRL_ADC_REFSCL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSCL_POS)) /**< ADC_REFSCL Mask */
+#define MXC_F_ADC_CTRL_ADC_SCALE_POS 9 /**< ADC_SCALE Position */
+#define MXC_F_ADC_CTRL_ADC_SCALE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_SCALE_POS)) /**< ADC_SCALE Mask */
+#define MXC_F_ADC_CTRL_ADC_REFSEL_POS 10 /**< ADC_REFSEL Position */
+#define MXC_F_ADC_CTRL_ADC_REFSEL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSEL_POS)) /**< ADC_REFSEL Mask */
+#define MXC_F_ADC_CTRL_ADC_CLK_EN_POS 11 /**< ADC_CLK_EN Position */
+#define MXC_F_ADC_CTRL_ADC_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CLK_EN_POS)) /**< ADC_CLK_EN Mask */
+#define MXC_F_ADC_CTRL_ADC_CHSEL_POS 12 /**< ADC_CHSEL Position */
+#define MXC_F_ADC_CTRL_ADC_CHSEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL_ADC_CHSEL_POS)) /**< ADC_CHSEL Mask */
+#define MXC_F_ADC_CTRL_ADC_XREF_POS 16 /**< ADC_XREF Position */
+#define MXC_F_ADC_CTRL_ADC_XREF ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_XREF_POS)) /**< ADC_XREF Mask */
+#define MXC_F_ADC_CTRL_ADC_DATAALIGN_POS 17 /**< ADC_DATAALIGN Position */
+#define MXC_F_ADC_CTRL_ADC_DATAALIGN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_DATAALIGN_POS)) /**< ADC_DATAALIGN Mask */
+#define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS 24 /**< AFE_PWR_UP_DLY Position */
+#define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY ((uint32_t)(0x000000FFUL << MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS)) /**< AFE_PWR_UP_DLY Mask */
+
+/**@} end of group adc_ctrl_register */
+
+/**
+ * @defgroup ADC_STATUS_Register ADC_STATUS
+ * @brief Field Positions and Bit Masks for the ADC_STATUS register
+ * @ingroup adc_registers
+ * @{
+ */
+#define MXC_F_ADC_STATUS_ADC_ACTIVE_POS 0 /**< ADC_ACTIVE Position */
+#define MXC_F_ADC_STATUS_ADC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_ACTIVE_POS)) /**< ADC_ACTIVE Mask */
+#define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS 1 /**< RO_CAL_ATOMIC_ACTIVE Position */
+#define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS)) /**< RO_CAL_ATOMIC_ACTIVE Mask */
+#define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS 2 /**< AFE_PWR_UP_ACTIVE Position */
+#define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS)) /**< AFE_PWR_UP_ACTIVE Mask */
+#define MXC_F_ADC_STATUS_ADC_OVERFLOW_POS 3 /**< ADC_OVERFLOW Position */
+#define MXC_F_ADC_STATUS_ADC_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_OVERFLOW_POS)) /**< ADC_OVERFLOW Mask */
+/**@} end of group ADC_STATUS_register */
+
+/**
+ * @defgroup ADC_DATA_Register ADC_DATA
+ * @ingroup adc_registers
+ * @brief Field Positions and Bit Masks for the ADC_DATA register
+ * @{
+ */
+#define MXC_F_ADC_DATA_ADC_DATA_POS 0 /**< ADC_DATA Position */
+#define MXC_F_ADC_DATA_ADC_DATA ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_DATA_ADC_DATA_POS)) /**< ADC_DATA Mask */
+/**@} end of group ADC_DATA_register */
+
+/**
+ * @defgroup ADC_INTR_Register ADC_INTR Register
+ * @ingroup adc_registers
+ * @brief Interrupt Enable and Interrupt Flag Field Positions and Bit Masks
+ * @{
+ */
+/**
+ * @defgroup ADC_INTR_IE_Register Interrupt Enable Bits
+ * @ingroup ADC_INTR_Register
+ * @brief Interrupt Enable Bit Positions and Masks
+ * @{
+ */
+#define MXC_F_ADC_INTR_ADC_DONE_IE_POS 0 /**< ADC_DONE_IE Position */
+#define MXC_F_ADC_INTR_ADC_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IE_POS)) /**< ADC_DONE_IE Mask */
+#define MXC_F_ADC_INTR_ADC_REF_READY_IE_POS 1 /**< ADC_REF_READY_IE Position */
+#define MXC_F_ADC_INTR_ADC_REF_READY_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IE_POS)) /**< ADC_REF_READY_IE Mask */
+#define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS 2 /**< ADC_HI_LIMIT_IE Position */
+#define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS)) /**< ADC_HI_LIMIT_IE Mask */
+#define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS 3 /**< ADC_LO_LIMIT_IE Position */
+#define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS)) /**< ADC_LO_LIMIT_IE Mask */
+#define MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS 4 /**< ADC_OVERFLOW_IE Position */
+#define MXC_F_ADC_INTR_ADC_OVERFLOW_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS)) /**< ADC_OVERFLOW_IE Mask */
+#define MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS 5 /**< RO_CAL_DONE_IE Position */
+#define MXC_F_ADC_INTR_RO_CAL_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS)) /**< RO_CAL_DONE_IE Mask */
+/**@} end of group ADC_INTR_IE_Register */
+
+
+/**
+ * @defgroup ADC_INTR_IF_Register Interrupt Flag Bits
+ * @ingroup ADC_INTR_Register
+ * @brief Interrupt Flag Bit Positions and Masks
+ * @{
+ */
+#define MXC_F_ADC_INTR_ADC_DONE_IF_POS 16 /**< ADC_DONE_IF Position */
+#define MXC_F_ADC_INTR_ADC_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IF_POS)) /**< ADC_DONE_IF Mask */
+#define MXC_F_ADC_INTR_ADC_REF_READY_IF_POS 17 /**< ADC_REF_READY_IF Position */
+#define MXC_F_ADC_INTR_ADC_REF_READY_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IF_POS)) /**< ADC_REF_READY_IF Mask */
+#define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS 18 /**< ADC_HI_LIMIT_IF Position */
+#define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS)) /**< ADC_HI_LIMIT_IF Mask */
+#define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS 19 /**< ADC_LO_LIMIT_IF Position */
+#define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS)) /**< ADC_LO_LIMIT_IF Mask */
+#define MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS 20 /**< ADC_OVERFLOW_IF Position */
+#define MXC_F_ADC_INTR_ADC_OVERFLOW_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS)) /**< ADC_OVERFLOW_IF Mask */
+#define MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS 21 /**< RO_CAL_DONE_IF Position */
+#define MXC_F_ADC_INTR_RO_CAL_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS)) /**< RO_CAL_DONE_IF Mask */
+#define MXC_F_ADC_INTR_ADC_INT_PENDING_POS 22 /**< ADC_INT_PENDING Position */
+#define MXC_F_ADC_INTR_ADC_INT_PENDING ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_INT_PENDING_POS)) /**< ADC_INT_PENDING Mask */
+/**@} end of group ADC_INTR_IF_Register */
+/**@} end of group ADC_INTR_Register */
+
+/**
+ * @defgroup ADC_LIMIT0_Register ADC_LIMIT0
+ * @ingroup adc_registers
+ * @brief Field Positions and Bit Masks for the ADC_LIMIT0 register
+ * @{
+ */
+#define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */
+#define MXC_F_ADC_LIMIT0_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */
+#define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */
+#define MXC_F_ADC_LIMIT0_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */
+#define MXC_F_ADC_LIMIT0_CH_SEL_POS 24 /**< CH_SEL Position */
+#define MXC_F_ADC_LIMIT0_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT0_CH_SEL_POS)) /**< CH_SEL Mask */
+#define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */
+#define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */
+#define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */
+#define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */
+/**@} end of group ADC_LIMIT0_register */
+
+/**
+ * @defgroup ADC_LIMIT1_Register ADC_LIMIT1
+ * @ingroup adc_registers
+ * @brief Field Positions and Bit Masks for the ADC_LIMIT1 register
+ * @{
+ */
+#define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */
+#define MXC_F_ADC_LIMIT1_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */
+#define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */
+#define MXC_F_ADC_LIMIT1_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */
+#define MXC_F_ADC_LIMIT1_CH_SEL_POS 24 /**< CH_SEL Position */
+#define MXC_F_ADC_LIMIT1_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT1_CH_SEL_POS)) /**< CH_SEL Mask */
+#define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */
+#define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */
+#define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */
+#define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */
+/**@} end of group ADC_LIMIT1_register */
+
+/**
+ * @defgroup ADC_LIMIT2_Register ADC_LIMIT2
+ * @ingroup adc_registers
+ * @brief Field Positions and Bit Masks for the ADC_LIMIT2 register
+ * @{
+ */
+#define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */
+#define MXC_F_ADC_LIMIT2_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */
+#define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */
+#define MXC_F_ADC_LIMIT2_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */
+#define MXC_F_ADC_LIMIT2_CH_SEL_POS 24 /**< CH_SEL Position */
+#define MXC_F_ADC_LIMIT2_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT2_CH_SEL_POS)) /**< CH_SEL Mask */
+#define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */
+#define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */
+#define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */
+#define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */
+/**@} end of group ADC_LIMIT2_register */
+
+/**
+ * @defgroup ADC_LIMIT3_Register ADC_LIMIT3
+ * @ingroup adc_registers
+ * @brief Field Positions and Bit Masks for the ADC_LIMIT3 register
+ * @{
+ */
+#define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */
+#define MXC_F_ADC_LIMIT3_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */
+#define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */
+#define MXC_F_ADC_LIMIT3_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */
+#define MXC_F_ADC_LIMIT3_CH_SEL_POS 24 /**< CH_SEL Position */
+#define MXC_F_ADC_LIMIT3_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT3_CH_SEL_POS)) /**< CH_SEL Mask */
+#define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */
+#define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */
+#define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */
+#define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */
+/**@} end of group ADC_LIMIT3_register */
+
+/**
+ * @defgroup ADC_AFE_CTRL_Register ADC_AFE_CTRL
+ * @ingroup adc_registers
+ * @brief Field Positions and Bit Masks for the ADC_AFE_CTRL register
+ * @{
+ */
+#define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS 8 /**< TMON_INTBIAS_EN Position */
+#define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS)) /**< TMON_INTBIAS_EN Mask */
+#define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS 9 /**< TMON_EXTBIAS_EN Position */
+#define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS)) /**< TMON_EXTBIAS_EN Mask */
+/**@} end of group ADC_AFE_CTRL_register */
+
+/**
+ * @defgroup ADC_RO_CAL0_Register ADC_RO_CAL0
+ * @ingroup adc_registers
+ * @brief Field Positions and Bit Masks for the ADC_RO_CAL0 register
+ * @{
+ */
+#define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS 0 /**< RO_CAL_EN Position */
+#define MXC_F_ADC_RO_CAL0_RO_CAL_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS)) /**< RO_CAL_EN Mask */
+#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS 1 /**< RO_CAL_RUN Position */
+#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS)) /**< RO_CAL_RUN Mask */
+#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS 2 /**< RO_CAL_LOAD Position */
+#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS)) /**< RO_CAL_LOAD Mask */
+#define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS 4 /**< RO_CAL_ATOMIC Position */
+#define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS)) /**< RO_CAL_ATOMIC Mask */
+#define MXC_F_ADC_RO_CAL0_DUMMY_POS 5 /**< DUMMY Position */
+#define MXC_F_ADC_RO_CAL0_DUMMY ((uint32_t)(0x00000007UL << MXC_F_ADC_RO_CAL0_DUMMY_POS)) /**< DUMMY Mask */
+#define MXC_F_ADC_RO_CAL0_TRM_MU_POS 8 /**< TRM_MU Position */
+#define MXC_F_ADC_RO_CAL0_TRM_MU ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS)) /**< TRM_MU Mask */
+#define MXC_F_ADC_RO_CAL0_RO_TRM_POS 23 /**< RO_TRM Position */
+#define MXC_F_ADC_RO_CAL0_RO_TRM ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS)) /**< RO_TRM Mask */
+/**@} end of group ADC_RO_CAL0_register */
+
+/**
+ * @defgroup ADC_RO_CAL1_Register ADC_RO_CAL1
+ * @ingroup adc_registers
+ * @brief Field Positions and Bit Masks for the ADC_RO_CAL1 register
+ * @{
+ */
+#define MXC_F_ADC_RO_CAL1_TRM_INIT_POS 0 /**< TRM_INIT Position */
+#define MXC_F_ADC_RO_CAL1_TRM_INIT ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS)) /**< TRM_INIT Mask */
+#define MXC_F_ADC_RO_CAL1_TRM_MIN_POS 10 /**< TRM_MIN Position */
+#define MXC_F_ADC_RO_CAL1_TRM_MIN ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS)) /**< TRM_MIN Mask */
+#define MXC_F_ADC_RO_CAL1_TRM_MAX_POS 20 /**< TRM_MAX Position */
+#define MXC_F_ADC_RO_CAL1_TRM_MAX ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS)) /**< TRM_MAX Mask */
+/**@} end of group RO_CAL1_register */
+
+/**
+ * @defgroup ADC_RO_CAL2_Register ADC_RO_CAL2
+ * @ingroup adc_registers
+ * @brief Field Positions and Bit Masks for the ADC_RO_CAL2 register
+ * @{
+ */
+#define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS 0 /**< AUTO_CAL_DONE_CNT Position */
+#define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT ((uint32_t)(0x000000FFUL << MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS)) /**< AUTO_CAL_DONE_CNT Mask */
+/**@} end of group RO_CAL2_register */
+
+/**
+ * @defgroup ADC_CHSEL_values ADC Channel Select Values
+ * @ingroup ADC_CTRL_Register
+ * @brief Channel Select Values
+ * @{
+ */
+#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN0 ((uint32_t)(0x00000000UL)) /**< Channel 0 Select */
+#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN1 ((uint32_t)(0x00000001UL)) /**< Channel 1 Select */
+#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN2 ((uint32_t)(0x00000002UL)) /**< Channel 2 Select */
+#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN3 ((uint32_t)(0x00000003UL)) /**< Channel 3 Select */
+#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN0_DIV_5 ((uint32_t)(0x00000004UL)) /**< Channel 0 divided by 5 */
+#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN1_DIV_5 ((uint32_t)(0x00000005UL)) /**< Channel 1 divided by 5 */
+#define MXC_V_ADC_CTRL_ADC_CHSEL_VDDB_DIV_4 ((uint32_t)(0x00000006UL)) /**< VDDB divided by 4 */
+#define MXC_V_ADC_CTRL_ADC_CHSEL_VDD18 ((uint32_t)(0x00000007UL)) /**< VDD18 input select */
+#define MXC_V_ADC_CTRL_ADC_CHSEL_VDD12 ((uint32_t)(0x00000008UL)) /**< VDD12 input select */
+#define MXC_V_ADC_CTRL_ADC_CHSEL_VRTC_DIV_2 ((uint32_t)(0x00000009UL)) /**< VRTC divided by 2 */
+#define MXC_V_ADC_CTRL_ADC_CHSEL_TMON ((uint32_t)(0x0000000AUL)) /**< TMON input select */
+#define MXC_V_ADC_CTRL_ADC_CHSEL_VDDIO_DIV_4 ((uint32_t)(0x0000000BUL)) /**< VDDIO divided by 4 select */
+#define MXC_V_ADC_CTRL_ADC_CHSEL_VDDIOH_DIV_4 ((uint32_t)(0x0000000CUL)) /**< VDDIOH divided by 4 select */
+
+/**@} end of group ADC_CHSEL_values */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_ADC_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/armcc/startup_MAX32625.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/maxim/max32625/armcc/startup_MAX32625.S Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,335 @@ +;******************************************************************************* +; Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. +; +; Permission is hereby granted, free of charge, to any person obtaining a +; copy of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice shall be included +; in all copies or substantial portions of the Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES +; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +; OTHER DEALINGS IN THE SOFTWARE. +; +; Except as contained in this notice, the name of Maxim Integrated +; Products, Inc. shall not be used except as stated in the Maxim Integrated +; Products, Inc. Branding Policy. +; +; The mere transfer of this software does not imply any licenses +; of trade secrets, proprietary technology, copyrights, patents, +; trademarks, maskwork rights, or any other form of intellectual +; property whatsoever. Maxim Integrated Products, Inc. retains all +; ownership rights. +;******************************************************************************* + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __initial_sp + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT g_board_info +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD DAPLINK_BUILD_KEY ; Reserved + DCD DAPLINK_HIC_ID ; Reserved + DCD DAPLINK_VERSION ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD g_board_info ; Ptr to Board info, family info other target details + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Maxim 32625 Externals interrupts + DCD CLKMAN_IRQHandler /* 16:01 CLKMAN */ + DCD PWRMAN_IRQHandler /* 17:02 PWRMAN */ + DCD FLC_IRQHandler /* 18:03 Flash Controller */ + DCD RTC0_IRQHandler /* 19:04 RTC INT0 */ + DCD RTC1_IRQHandler /* 20:05 RTC INT1 */ + DCD RTC2_IRQHandler /* 21:06 RTC INT2 */ + DCD RTC3_IRQHandler /* 22:07 RTC INT3 */ + DCD PMU_IRQHandler /* 23:08 PMU */ + DCD USB_IRQHandler /* 24:09 USB */ + DCD AES_IRQHandler /* 25:10 AES */ + DCD MAA_IRQHandler /* 26:11 MAA */ + DCD WDT0_IRQHandler /* 27:12 WATCHDOG0 */ + DCD WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */ + DCD WDT1_IRQHandler /* 29:14 WATCHDOG1 */ + DCD WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */ + DCD GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */ + DCD GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */ + DCD GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */ + DCD GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */ + DCD GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */ + DCD GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */ + DCD GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */ + DCD TMR0_IRQHandler /* 38:23 Timer32-0 */ + DCD TMR16_0_IRQHandler /* 39:24 Timer16-s0 */ + DCD TMR1_IRQHandler /* 40:25 Timer32-1 */ + DCD TMR16_1_IRQHandler /* 41:26 Timer16-s1 */ + DCD TMR2_IRQHandler /* 42:27 Timer32-2 */ + DCD TMR16_2_IRQHandler /* 43:28 Timer16-s2 */ + DCD TMR3_IRQHandler /* 44:29 Timer32-3 */ + DCD TMR16_3_IRQHandler /* 45:30 Timer16-s3 */ + DCD TMR4_IRQHandler /* 46:31 Timer32-4 */ + DCD TMR16_4_IRQHandler /* 47:32 Timer16-s4 */ + DCD TMR5_IRQHandler /* 48:33 Timer32-5 */ + DCD TMR16_5_IRQHandler /* 49:34 Timer16-s5 */ + DCD UART0_IRQHandler /* 50:35 UART0 */ + DCD UART1_IRQHandler /* 51:36 UART1 */ + DCD UART2_IRQHandler /* 52:37 UART0 */ + DCD UART3_IRQHandler /* 53:38 UART1 */ + DCD PT_IRQHandler /* 54:39 PT */ + DCD I2CM0_IRQHandler /* 55:40 I2C Master 0 */ + DCD I2CM1_IRQHandler /* 56:41 I2C Master 1 */ + DCD I2CM2_IRQHandler /* 57:42 I2C Master 2 */ + DCD I2CS_IRQHandler /* 58:43 I2C Slave */ + DCD SPI0_IRQHandler /* 59:44 SPI0 */ + DCD SPI1_IRQHandler /* 60:45 SPI1 */ + DCD SPI2_IRQHandler /* 61:46 SPI2 */ + DCD SPIB_IRQHandler /* 62:47 SPI Bridge */ + DCD OWM_IRQHandler /* 63:48 1-Wire Master */ + DCD AFE_IRQHandler /* 64:49 AFE */ + DCD SPIS_IRQHandler ; 65:50 SPI Slave + DCD GPIO_P7_IRQHandler ; 66:51 GPIO Port 7 + DCD GPIO_P8_IRQHandler ; 67:52 GPIO Port 8 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT PreInit + IMPORT SystemInit + IMPORT __main + LDR R0, =PreInit + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +DefaultIRQ_Handler PROC + EXPORT CLKMAN_IRQHandler [WEAK] + EXPORT PWRMAN_IRQHandler [WEAK] + EXPORT FLC_IRQHandler [WEAK] + EXPORT RTC0_IRQHandler [WEAK] + EXPORT RTC1_IRQHandler [WEAK] + EXPORT RTC2_IRQHandler [WEAK] + EXPORT RTC3_IRQHandler [WEAK] + EXPORT PMU_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT MAA_IRQHandler [WEAK] + EXPORT WDT0_IRQHandler [WEAK] + EXPORT WDT0_P_IRQHandler [WEAK] + EXPORT WDT1_IRQHandler [WEAK] + EXPORT WDT1_P_IRQHandler [WEAK] + EXPORT GPIO_P0_IRQHandler [WEAK] + EXPORT GPIO_P1_IRQHandler [WEAK] + EXPORT GPIO_P2_IRQHandler [WEAK] + EXPORT GPIO_P3_IRQHandler [WEAK] + EXPORT GPIO_P4_IRQHandler [WEAK] + EXPORT GPIO_P5_IRQHandler [WEAK] + EXPORT GPIO_P6_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR16_0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR16_1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR16_2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT TMR16_3_IRQHandler [WEAK] + EXPORT TMR4_IRQHandler [WEAK] + EXPORT TMR16_4_IRQHandler [WEAK] + EXPORT TMR5_IRQHandler [WEAK] + EXPORT TMR16_5_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT PT_IRQHandler [WEAK] + EXPORT I2CM0_IRQHandler [WEAK] + EXPORT I2CM1_IRQHandler [WEAK] + EXPORT I2CM2_IRQHandler [WEAK] + EXPORT I2CS_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPIB_IRQHandler [WEAK] + EXPORT OWM_IRQHandler [WEAK] + EXPORT AFE_IRQHandler [WEAK] + EXPORT SPIS_IRQHandler [WEAK] + EXPORT GPIO_P7_IRQHandler [WEAK] + EXPORT GPIO_P8_IRQHandler [WEAK] +CLKMAN_IRQHandler +PWRMAN_IRQHandler +FLC_IRQHandler +RTC0_IRQHandler +RTC1_IRQHandler +RTC2_IRQHandler +RTC3_IRQHandler +PMU_IRQHandler +USB_IRQHandler +AES_IRQHandler +MAA_IRQHandler +WDT0_IRQHandler +WDT0_P_IRQHandler +WDT1_IRQHandler +WDT1_P_IRQHandler +GPIO_P0_IRQHandler +GPIO_P1_IRQHandler +GPIO_P2_IRQHandler +GPIO_P3_IRQHandler +GPIO_P4_IRQHandler +GPIO_P5_IRQHandler +GPIO_P6_IRQHandler +TMR0_IRQHandler +TMR16_0_IRQHandler +TMR1_IRQHandler +TMR16_1_IRQHandler +TMR2_IRQHandler +TMR16_2_IRQHandler +TMR3_IRQHandler +TMR16_3_IRQHandler +TMR4_IRQHandler +TMR16_4_IRQHandler +TMR5_IRQHandler +TMR16_5_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +PT_IRQHandler +I2CM0_IRQHandler +I2CM1_IRQHandler +I2CM2_IRQHandler +I2CS_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +SPIB_IRQHandler +OWM_IRQHandler +AFE_IRQHandler +SPIS_IRQHandler +GPIO_P7_IRQHandler +GPIO_P8_IRQHandler + + B . + ENDP + ALIGN + + ; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + END
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/clkman_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32625/clkman_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,438 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_CLKMAN_REGS_H_
+#define _MXC_CLKMAN_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __IO uint32_t clk_config; /* 0x0000 System Clock Configuration */
+ __IO uint32_t clk_ctrl; /* 0x0004 System Clock Controls */
+ __IO uint32_t intfl; /* 0x0008 Interrupt Flags */
+ __IO uint32_t inten; /* 0x000C Interrupt Enable/Disable Controls */
+ __IO uint32_t trim_calc; /* 0x0010 Trim Calculation Controls */
+ __IO uint32_t i2c_timer_ctrl; /* 0x0014 I2C Timer Control */
+ __IO uint32_t cm4_start_clk_en0; /* 0x0018 CM4 Start Clock on Interrupt Enable 0 */
+ __IO uint32_t cm4_start_clk_en1; /* 0x001C CM4 Start Clock on Interrupt Enable 1 */
+ __IO uint32_t cm4_start_clk_en2; /* 0x0020 CM4 Start Clock on Interrupt Enable 2 */
+ __R uint32_t rsv024[7]; /* 0x0024-0x003C */
+ __IO uint32_t sys_clk_ctrl_0_cm4; /* 0x0040 Control Settings for CLK0 - Cortex M4 Clock */
+ __IO uint32_t sys_clk_ctrl_1_sync; /* 0x0044 Control Settings for CLK1 - Synchronizer Clock */
+ __IO uint32_t sys_clk_ctrl_2_spix; /* 0x0048 Control Settings for CLK2 - SPI XIP Clock */
+ __IO uint32_t sys_clk_ctrl_3_prng; /* 0x004C Control Settings for CLK3 - PRNG Clock */
+ __IO uint32_t sys_clk_ctrl_4_wdt0; /* 0x0050 Control Settings for CLK4 - Watchdog Timer 0 */
+ __IO uint32_t sys_clk_ctrl_5_wdt1; /* 0x0054 Control Settings for CLK5 - Watchdog Timer 1 */
+ __IO uint32_t sys_clk_ctrl_6_gpio; /* 0x0058 Control Settings for CLK6 - Clock for GPIO Ports */
+ __IO uint32_t sys_clk_ctrl_7_pt; /* 0x005C Control Settings for CLK7 - Source Clock for All Pulse Trains */
+ __IO uint32_t sys_clk_ctrl_8_uart; /* 0x0060 Control Settings for CLK8 - Source Clock for All UARTs */
+ __IO uint32_t sys_clk_ctrl_9_i2cm; /* 0x0064 Control Settings for CLK9 - Source Clock for All I2C Masters */
+ __IO uint32_t sys_clk_ctrl_10_i2cs; /* 0x0068 Control Settings for CLK10 - Source Clock for I2C Slave */
+ __IO uint32_t sys_clk_ctrl_11_spi0; /* 0x006C Control Settings for CLK11 - SPI Master 0 */
+ __IO uint32_t sys_clk_ctrl_12_spi1; /* 0x0070 Control Settings for CLK12 - SPI Master 1 */
+ __IO uint32_t sys_clk_ctrl_13_spi2; /* 0x0074 Control Settings for CLK13 - SPI Master 2 */
+ __R uint32_t rsv078; /* 0x0078 */
+ __IO uint32_t sys_clk_ctrl_15_owm; /* 0x007C Control Settings for CLK15 - 1-Wire Master Clock */
+ __IO uint32_t sys_clk_ctrl_16_spis; /* 0x0080 Control Settings for CLK16 - SPI Slave Clock */
+ __R uint32_t rsv084[31]; /* 0x0084-0x00FC */
+ __IO uint32_t crypt_clk_ctrl_0_aes; /* 0x0100 Control Settings for Crypto Clock 0 - AES */
+ __IO uint32_t crypt_clk_ctrl_1_maa; /* 0x0104 Control Settings for Crypto Clock 1 - MAA */
+ __IO uint32_t crypt_clk_ctrl_2_prng; /* 0x0108 Control Settings for Crypto Clock 2 - PRNG */
+ __R uint32_t rsv10C[13]; /* 0x010C-0x013C */
+ __IO uint32_t clk_gate_ctrl0; /* 0x0140 Dynamic Clock Gating Control Register 0 */
+ __IO uint32_t clk_gate_ctrl1; /* 0x0144 Dynamic Clock Gating Control Register 1 */
+ __IO uint32_t clk_gate_ctrl2; /* 0x0148 Dynamic Clock Gating Control Register 2 */
+} mxc_clkman_regs_t;
+
+
+/*
+ Register offsets for module CLKMAN.
+*/
+
+#define MXC_R_CLKMAN_OFFS_CLK_CONFIG ((uint32_t)0x00000000UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL ((uint32_t)0x00000004UL)
+#define MXC_R_CLKMAN_OFFS_INTFL ((uint32_t)0x00000008UL)
+#define MXC_R_CLKMAN_OFFS_INTEN ((uint32_t)0x0000000CUL)
+#define MXC_R_CLKMAN_OFFS_TRIM_CALC ((uint32_t)0x00000010UL)
+#define MXC_R_CLKMAN_OFFS_I2C_TIMER_CTRL ((uint32_t)0x00000014UL)
+#define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN0 ((uint32_t)0x00000018UL)
+#define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN1 ((uint32_t)0x0000001CUL)
+#define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN2 ((uint32_t)0x00000020UL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_0_CM4 ((uint32_t)0x00000040UL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_1_SYNC ((uint32_t)0x00000044UL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_2_SPIX ((uint32_t)0x00000048UL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_3_PRNG ((uint32_t)0x0000004CUL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_4_WDT0 ((uint32_t)0x00000050UL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_5_WDT1 ((uint32_t)0x00000054UL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_6_GPIO ((uint32_t)0x00000058UL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_7_PT ((uint32_t)0x0000005CUL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_8_UART ((uint32_t)0x00000060UL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_9_I2CM ((uint32_t)0x00000064UL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_10_I2CS ((uint32_t)0x00000068UL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_11_SPI0 ((uint32_t)0x0000006CUL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_12_SPI1 ((uint32_t)0x00000070UL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_13_SPI2 ((uint32_t)0x00000074UL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_15_OWM ((uint32_t)0x0000007CUL)
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_16_SPIS ((uint32_t)0x00000080UL)
+#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_0_AES ((uint32_t)0x00000100UL)
+#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_1_MAA ((uint32_t)0x00000104UL)
+#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_2_PRNG ((uint32_t)0x00000108UL)
+#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL0 ((uint32_t)0x00000140UL)
+#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL1 ((uint32_t)0x00000144UL)
+#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL2 ((uint32_t)0x00000148UL)
+
+
+/*
+ Field positions and masks for module CLKMAN.
+*/
+
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS 0
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS 4
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE_POS 4
+#define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT_POS 5
+#define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE_POS 8
+#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS 12
+#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK_POS 13
+#define MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE_POS 16
+#define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS 17
+#define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE_POS 20
+#define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS 21
+#define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE_POS 24
+#define MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE_POS))
+
+#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS 0
+#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS))
+#define MXC_F_CLKMAN_INTFL_SYS_RO_STABLE_POS 1
+#define MXC_F_CLKMAN_INTFL_SYS_RO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_SYS_RO_STABLE_POS))
+
+#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS 0
+#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS))
+#define MXC_F_CLKMAN_INTEN_SYS_RO_STABLE_POS 1
+#define MXC_F_CLKMAN_INTEN_SYS_RO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_SYS_RO_STABLE_POS))
+
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS 0
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS 1
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS 2
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS 3
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_LENGTH_POS 4
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_LENGTH ((uint32_t)(0x00000FFFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_LENGTH_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS 16
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS ((uint32_t)(0x00003FFFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS))
+
+#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS 0
+#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS))
+
+#define MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS_POS 0
+#define MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS_POS))
+
+#define MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS_POS 0
+#define MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS_POS))
+
+#define MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS_POS 0
+#define MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER_POS 0
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER_POS 2
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS 4
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS 6
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS 8
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS 10
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS 12
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER_POS 14
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER_POS 16
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER_POS 18
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER_POS 20
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER_POS 22
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS 24
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER_POS 26
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER_POS 28
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS 30
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS))
+
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER_POS 0
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS 2
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER_POS 4
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER_POS 6
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER_POS 8
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER_POS 10
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER_POS 12
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER_POS 14
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS 16
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER_POS 18
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER_POS 20
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER_POS 22
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS 26
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS 28
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS))
+
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER_POS 0
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER_POS 2
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER_POS 4
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER_POS 6
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER_POS 10
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER_POS 12
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER_POS 14
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER_POS))
+
+
+
+/*
+ Field values and shifted values for module CLKMAN.
+*/
+
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS ((uint32_t)(0x00000000UL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS ((uint32_t)(0x00000001UL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS ((uint32_t)(0x00000002UL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS ((uint32_t)(0x00000003UL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS ((uint32_t)(0x00000004UL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS ((uint32_t)(0x00000005UL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS ((uint32_t)(0x00000006UL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS ((uint32_t)(0x00000007UL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS ((uint32_t)(0x00000008UL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS ((uint32_t)(0x00000009UL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS ((uint32_t)(0x0000000AUL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS ((uint32_t)(0x0000000BUL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS ((uint32_t)(0x0000000CUL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS ((uint32_t)(0x0000000DUL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS ((uint32_t)(0x0000000EUL))
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS ((uint32_t)(0x0000000FUL))
+
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+
+#define MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 ((uint32_t)(0x00000000UL))
+#define MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO ((uint32_t)(0x00000001UL))
+
+#define MXC_S_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 ((uint32_t)(MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS))
+#define MXC_S_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO ((uint32_t)(MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS))
+
+#define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 ((uint32_t)(0x00000000UL))
+#define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(0x00000001UL))
+#define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(0x00000002UL))
+#define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(0x00000003UL))
+
+#define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
+#define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
+#define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
+#define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
+
+#define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 ((uint32_t)(0x00000000UL))
+#define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(0x00000001UL))
+#define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(0x00000002UL))
+#define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(0x00000003UL))
+
+#define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
+#define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
+#define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
+#define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
+
+#define MXC_V_CLKMAN_CLK_SCALE_DISABLED ((uint32_t)(0x00000000UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_1 ((uint32_t)(0x00000001UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_2 ((uint32_t)(0x00000002UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_4 ((uint32_t)(0x00000003UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_8 ((uint32_t)(0x00000004UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_16 ((uint32_t)(0x00000005UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_32 ((uint32_t)(0x00000006UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_64 ((uint32_t)(0x00000007UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_128 ((uint32_t)(0x00000008UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_256 ((uint32_t)(0x00000009UL))
+
+#define MXC_S_CLKMAN_CLK_SCALE_DISABLED ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DISABLED << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_1 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_1 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_2 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_2 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_4 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_4 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_8 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_8 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_16 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_16 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_32 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_32 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_64 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_64 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_128 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_128 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_256 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_256 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_CLKMAN_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/daplink_addr.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/maxim/max32625/daplink_addr.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,82 @@ +/** + * @file daplink_addr.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef DAPLINK_ADDR_H +#define DAPLINK_ADDR_H + +/* Device sizes */ + +#define DAPLINK_ROM_START 0x00000000 +#define DAPLINK_ROM_SIZE 0x00080000 + +#define DAPLINK_RAM_START 0x20000000 +#define DAPLINK_RAM_SIZE 0x00028000 + +/* ROM sizes */ + +#define DAPLINK_ROM_BL_START 0x00000000 +#define DAPLINK_ROM_BL_SIZE 0x0000E000 + +#define DAPLINK_ROM_CONFIG_ADMIN_START 0x0000E000 +#define DAPLINK_ROM_CONFIG_ADMIN_SIZE 0x00002000 + +#define DAPLINK_ROM_IF_START 0x00010000 +#define DAPLINK_ROM_IF_SIZE 0x0006E000 + +#define DAPLINK_ROM_CONFIG_USER_START 0x0007E000 +#define DAPLINK_ROM_CONFIG_USER_SIZE 0x00002000 + +/* RAM sizes */ + +#define DAPLINK_RAM_APP_START 0x20000000 +#define DAPLINK_RAM_APP_SIZE 0x00020000 + +#define DAPLINK_RAM_SHARED_START 0x20020000 +#define DAPLINK_RAM_SHARED_SIZE 0x00008000 + +/* Flash Programming Info */ + +#define DAPLINK_SECTOR_SIZE 0x00002000 +#define DAPLINK_MIN_WRITE_SIZE 0x00000020 + +/* Current build */ + +#if defined(DAPLINK_BL) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_BL_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_IF_SIZE + +#elif defined(DAPLINK_IF) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_IF_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_BL_SIZE + +#else + +#error "Build must be either bootloader or interface" + +#endif + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/flc_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32625/flc_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,387 @@
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, Maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_FLC_REGS_H_
+#define _MXC_FLC_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/// @cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+/**
+ * @defgroup flc_special_codes Flash Controller Codes/Keys.
+ * @brief Required values to pass to the flash controller to perform restricted
+ * operations.
+ * @ingroup flc_registers
+ * @{
+ */
+#define MXC_V_FLC_ERASE_CODE_PAGE_ERASE ((uint8_t)0x55) /**< Page Erase Code required to perform a page erase operation */
+#define MXC_V_FLC_ERASE_CODE_MASS_ERASE ((uint8_t)0xAA) /**< Mass Erase Code required to perform a page erase operation */
+#define MXC_V_FLC_FLSH_UNLOCK_KEY ((uint8_t)0x2) /**< Unlock Code required to unlock the flash for erase and write functions */
+/**@} end of flc_special_codes */
+
+/**
+ * @defgroup flc_registers Registers
+ * @brief Registers, Bit Masks, Bit Positions and Values for the FLC Peripheral Module.
+ * @ingroup flc
+ * @{
+ */
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/**
+ * Structure type to access the Flash Controller registers with direct 32-bit
+ access to each.
+ */
+typedef struct {
+ __IO uint32_t faddr; /**< <tt>\b 0x0000: </tt> FLC_FADDR Register - Flash Operation Address */
+ __IO uint32_t fckdiv; /**< <tt>\b 0x0004: </tt> FLC_FCKDIV Register - Flash Clock Pulse Divisor */
+ __IO uint32_t ctrl; /**< <tt>\b 0x0008: </tt> FLC_CTRL Register - Flash Control Register */
+ __R uint32_t rsv00C[6]; /**< <tt>\b 0x000C-0x0020:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
+ __IO uint32_t intr; /**< <tt>\b 0x0024: </tt> FLC_INTR Register - Flash Controller Interrupt Flags and Enable/Disable 0 */
+ __R uint32_t rsv028[2]; /**< <tt>\b 0x0028-0x002C:</tt> RESERVED */
+ __IO uint32_t fdata; /**< <tt>\b 0x0030: </tt> FLC_FDATA Register - Flash Operation Data Register */
+ __R uint32_t rsv034[7]; /**< <tt>\b 0x0034-0x004C:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
+ __IO uint32_t perform; /**< <tt>\b 0x0050: </tt> FLC_PERFORM Register - Flash Performance Settings */
+ __IO uint32_t tacc; /**< <tt>\b 0x0054: </tt> FLC_TACC Register - Flash Read Cycle Config */
+ __IO uint32_t tprog; /**< <tt>\b 0x0058: </tt> FLC_TPROG Register - Flash Write Cycle Config */
+ __R uint32_t rsv05C[9]; /**< <tt>\b 0x005C-0x007C:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
+ __IO uint32_t status; /**< <tt>\b 0x0080: </tt> FLC_STATUS Register - Security Status Flags */
+ __R uint32_t rsv084; /**< <tt>\b 0x0084: </tt> RESERVED \warning Do Not Modify Reserved Locations! */
+ __IO uint32_t security; /**< <tt>\b 0x0088: </tt> FLC_SECURITY Register - Flash Controller Security Settings */
+ __R uint32_t rsv08C[4]; /**< <tt>\b 0x008C-0x0098:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
+ __IO uint32_t bypass; /**< <tt>\b 0x009C: </tt> FLC_BYPASS Register - Status Flags for DSB Operations */
+ __R uint32_t rsv0A0[24]; /**< <tt>\b 0x00A0-0x00FC:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
+ __IO uint32_t user_option; /**< <tt>\b 0x0100: </tt> FLC_USER_OPTION Register - Used to set DSB Access code and Auto-Lock in info block */
+ __R uint32_t rsv104[15]; /**< <tt>\b 0x0104-0x013C:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
+ __IO uint32_t ctrl2; /**< <tt>\b 0x0140: </tt> FLC_CTRL2 Register - Flash Control Register 2 */
+ __IO uint32_t intfl1; /**< <tt>\b 0x0144: </tt> FLC_INTFL1 Register - Interrupt Flags Register 1 */
+ __IO uint32_t inten1; /**< <tt>\b 0x0148: </tt> FLC_INTEN1 Register - Interrupt Enable/Disable Register 1 */
+ __R uint32_t rsv14C[9]; /**< <tt>\b 0x014C-0x016C:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
+ __IO uint32_t bl_ctrl; /**< <tt>\b 0x0170: </tt> FLC_BL_CTRL Register - Bootloader Control Register */
+ __IO uint32_t twk; /**< <tt>\b 0x0174: </tt> FLC_TWK Register - PDM33 Register */
+ __R uint32_t rsv178; /**< <tt>\b 0x0178: </tt> RESERVED \warning Do Not Modify Reserved Locations! */
+ __IO uint32_t slm; /**< <tt>\b 0x017C: </tt> FLC_SLM Register - Sleep Mode Register */
+ __R uint32_t rsv180[32]; /**< <tt>\b 0x0180-0x01FC:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
+ __IO uint32_t disable_xr0; /**< <tt>\b 0x0200: </tt> FLC_DISABLE_XR0 Register - Disable Flash Page Exec/Read Register 0 */
+ __IO uint32_t disable_xr1; /**< <tt>\b 0x0204: </tt> FLC_DISABLE_XR1 Register - Disable Flash Page Exec/Read Register 1 */
+ __IO uint32_t disable_xr2; /**< <tt>\b 0x0208: </tt> FLC_DISABLE_XR2 Register - Disable Flash Page Exec/Read Register 2 */
+ __IO uint32_t disable_xr3; /**< <tt>\b 0x020C: </tt> FLC_DISABLE_XR3 Register - Disable Flash Page Exec/Read Register 3 */
+ __IO uint32_t disable_xr4; /**< <tt>\b 0x0210: </tt> FLC_DISABLE_XR4 Register - Disable Flash Page Exec/Read Register 4 */
+ __IO uint32_t disable_xr5; /**< <tt>\b 0x0214: </tt> FLC_DISABLE_XR5 Register - Disable Flash Page Exec/Read Register 5 */
+ __IO uint32_t disable_xr6; /**< <tt>\b 0x0218: </tt> FLC_DISABLE_XR6 Register - Disable Flash Page Exec/Read Register 6 */
+ __IO uint32_t disable_xr7; /**< <tt>\b 0x021C: </tt> FLC_DISABLE_XR7 Register - Disable Flash Page Exec/Read Register 7 */
+ __R uint32_t rsv220[56]; /**< <tt>\b 0x0220-0x02FC:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
+ __IO uint32_t disable_we0; /**< <tt>\b 0x0300: </tt> FLC_DISABLE_WE0 Register - Disable Flash Page Write/Erase Register 0 */
+ __IO uint32_t disable_we1; /**< <tt>\b 0x0304: </tt> FLC_DISABLE_WE1 Register - Disable Flash Page Write/Erase Register 1 */
+ __IO uint32_t disable_we2; /**< <tt>\b 0x0308: </tt> FLC_DISABLE_WE2 Register - Disable Flash Page Write/Erase Register 2 */
+ __IO uint32_t disable_we3; /**< <tt>\b 0x030C: </tt> FLC_DISABLE_WE3 Register - Disable Flash Page Write/Erase Register 3 */
+ __IO uint32_t disable_we4; /**< <tt>\b 0x0310: </tt> FLC_DISABLE_WE4 Register - Disable Flash Page Write/Erase Register 4 */
+ __IO uint32_t disable_we5; /**< <tt>\b 0x0314: </tt> FLC_DISABLE_WE5 Register - Disable Flash Page Write/Erase Register 5 */
+ __IO uint32_t disable_we6; /**< <tt>\b 0x0318: </tt> FLC_DISABLE_WE6 Register - Disable Flash Page Write/Erase Register 6 */
+ __IO uint32_t disable_we7; /**< <tt>\b 0x031C: </tt> FLC_DISABLE_WE7 Register - Disable Flash Page Write/Erase Register 7 */
+} mxc_flc_regs_t;
+/**@} end of group flc_registers */
+/*
+ Register offsets for module FLC.
+*/
+/**
+ * @defgroup FLC_Register_Offsets Register Offsets
+ * @ingroup flc_registers
+ * @brief Flash Controller Register Offsets from the FLC Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_FLC_OFFS_FADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt>\b 0x0000</tt> */
+#define MXC_R_FLC_OFFS_FCKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt>\b 0x0004</tt> */
+#define MXC_R_FLC_OFFS_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt>\b 0x0008</tt> */
+#define MXC_R_FLC_OFFS_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt>\b 0x0024</tt> */
+#define MXC_R_FLC_OFFS_FDATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt>\b 0x0030</tt> */
+#define MXC_R_FLC_OFFS_PERFORM ((uint32_t)0x00000050UL) /**< Offset from FLC Base Address: <tt>\b 0x0050</tt> */
+#define MXC_R_FLC_OFFS_TACC ((uint32_t)0x00000054UL) /**< Offset from FLC Base Address: <tt>\b 0x0054</tt> */
+#define MXC_R_FLC_OFFS_TPROG ((uint32_t)0x00000058UL) /**< Offset from FLC Base Address: <tt>\b 0x0058</tt> */
+#define MXC_R_FLC_OFFS_STATUS ((uint32_t)0x00000080UL) /**< Offset from FLC Base Address: <tt>\b 0x0080</tt> */
+#define MXC_R_FLC_OFFS_SECURITY ((uint32_t)0x00000088UL) /**< Offset from FLC Base Address: <tt>\b 0x0088</tt> */
+#define MXC_R_FLC_OFFS_BYPASS ((uint32_t)0x0000009CUL) /**< Offset from FLC Base Address: <tt>\b 0x009C</tt> */
+#define MXC_R_FLC_OFFS_USER_OPTION ((uint32_t)0x00000100UL) /**< Offset from FLC Base Address: <tt>\b 0x0100</tt> */
+#define MXC_R_FLC_OFFS_CTRL2 ((uint32_t)0x00000140UL) /**< Offset from FLC Base Address: <tt>\b 0x0140</tt> */
+#define MXC_R_FLC_OFFS_INTFL1 ((uint32_t)0x00000144UL) /**< Offset from FLC Base Address: <tt>\b 0x0144</tt> */
+#define MXC_R_FLC_OFFS_INTEN1 ((uint32_t)0x00000148UL) /**< Offset from FLC Base Address: <tt>\b 0x0148</tt> */
+#define MXC_R_FLC_OFFS_BL_CTRL ((uint32_t)0x00000170UL) /**< Offset from FLC Base Address: <tt>\b 0x0170</tt> */
+#define MXC_R_FLC_OFFS_TWK ((uint32_t)0x00000174UL) /**< Offset from FLC Base Address: <tt>\b 0x0174</tt> */
+#define MXC_R_FLC_OFFS_SLM ((uint32_t)0x0000017CUL) /**< Offset from FLC Base Address: <tt>\b 0x017C</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_XR0 ((uint32_t)0x00000200UL) /**< Offset from FLC Base Address: <tt>\b 0x0200</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_XR1 ((uint32_t)0x00000204UL) /**< Offset from FLC Base Address: <tt>\b 0x0204</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_XR2 ((uint32_t)0x00000208UL) /**< Offset from FLC Base Address: <tt>\b 0x0208</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_XR3 ((uint32_t)0x0000020CUL) /**< Offset from FLC Base Address: <tt>\b 0x020C</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_XR4 ((uint32_t)0x00000210UL) /**< Offset from FLC Base Address: <tt>\b 0x0210</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_XR5 ((uint32_t)0x00000214UL) /**< Offset from FLC Base Address: <tt>\b 0x0214</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_XR6 ((uint32_t)0x00000218UL) /**< Offset from FLC Base Address: <tt>\b 0x0218</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_XR7 ((uint32_t)0x0000021CUL) /**< Offset from FLC Base Address: <tt>\b 0x021C</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_WE0 ((uint32_t)0x00000300UL) /**< Offset from FLC Base Address: <tt>\b 0x0300</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_WE1 ((uint32_t)0x00000304UL) /**< Offset from FLC Base Address: <tt>\b 0x0304</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_WE2 ((uint32_t)0x00000308UL) /**< Offset from FLC Base Address: <tt>\b 0x0308</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_WE3 ((uint32_t)0x0000030CUL) /**< Offset from FLC Base Address: <tt>\b 0x030C</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_WE4 ((uint32_t)0x00000310UL) /**< Offset from FLC Base Address: <tt>\b 0x0310</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_WE5 ((uint32_t)0x00000314UL) /**< Offset from FLC Base Address: <tt>\b 0x0314</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_WE6 ((uint32_t)0x00000318UL) /**< Offset from FLC Base Address: <tt>\b 0x0318</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_WE7 ((uint32_t)0x0000031CUL) /**< Offset from FLC Base Address: <tt>\b 0x031C</tt> */
+/**@} end of group FLC_Register_Offsets */
+/*
+ Field positions and Masks for module FLC.
+*/
+/**
+ * @defgroup FLC_FADDR_Register FLC_FADDR
+ * @ingroup flc_registers
+ * @brief Field Positions and Bit Masks for the FLC_FADDR register.
+ * @{
+ */
+#define MXC_F_FLC_FADDR_FADDR_POS 0 /**< FADDR Position */
+#define MXC_F_FLC_FADDR_FADDR ((uint32_t)(0x003FFFFFUL << MXC_F_FLC_FADDR_FADDR_POS)) /**< FADDR Mask */
+/**@} end of group FLC_FADDR */
+/**
+ * @defgroup FLC_FCKDIV_Register FLC_FCKDIV
+ * @ingroup flc_registers
+ * @brief Field Positions and Bit Masks for the FLC_FCKDIV register.
+ * @{
+ */
+#define MXC_F_FLC_FCKDIV_FCKDIV_POS /**< FCKDIV Position */
+#define MXC_F_FLC_FCKDIV_FCKDIV ((uint32_t)(0x0000007FUL << MXC_F_FLC_FCKDIV_FCKDIV_POS)) /**< FCKDIV Mask */
+#define MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT_POS 16 /**< AUTO_FCKDIV_RESULT Position */
+#define MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT ((uint32_t)(0x0000FFFFUL << MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT_POS)) /**< AUTO_FCKDIV_RESULT Mask */
+/**@} end of group FLC_FCKDIV */
+/**
+ * @defgroup FLC_CTRL_Register FLC_CTRL
+ * @ingroup flc_registers
+ * @brief Field Positions and Bit Masks for the FLC_CTRL register.
+ * @{
+ */
+#define MXC_F_FLC_CTRL_WRITE_POS 0 /**< WRITE Position */
+#define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_POS)) /**< WRITE Mask */
+#define MXC_F_FLC_CTRL_MASS_ERASE_POS 1 /**< MASS_ERASE Position */
+#define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_MASS_ERASE_POS)) /**< MASS_ERASE Mask */
+#define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2 /**< PAGE_ERASE Position */
+#define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS)) /**< PAGE_ERASE Mask */
+#define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< ERASE_CODE Position */
+#define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< ERASE_CODE Mask */
+#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS 16 /**< INFO_BLOCK_UNLOCK Position */
+#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS)) /**< INFO_BLOCK_UNLOCK Mask */
+#define MXC_F_FLC_CTRL_WRITE_ENABLE_POS 17 /**< WRITE_ENABLE Position */
+#define MXC_F_FLC_CTRL_WRITE_ENABLE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_ENABLE_POS)) /**< WRITE_ENABLE Mask */
+#define MXC_F_FLC_CTRL_PENDING_POS 24 /**< PENDING Position */
+#define MXC_F_FLC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PENDING_POS)) /**< PENDING Mask */
+#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS 25 /**< INFO_BLOCK_VALID Position */
+#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS)) /**< INFO_BLOCK_VALID Mask */
+#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS 27 /**< AUTO_INCRE_MODE Position */
+#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS)) /**< AUTO_INCRE_MODE Mask */
+#define MXC_F_FLC_CTRL_FLSH_UNLOCK_POS 28 /**< FLSH_UNLOCK Position */
+#define MXC_F_FLC_CTRL_FLSH_UNLOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS)) /**< FLSH_UNLOCK Mask */
+/**@} end of group FLC_CTRL */
+/**
+ * @defgroup FLC_INTR_Register FLC_INTR
+ * @ingroup flc_registers
+ * @brief Field Positions and Bit Masks for the FLC_INTR register.
+ * @{
+ */
+#define MXC_F_FLC_INTR_FINISHED_IF_POS 0 /**< FINISHED_IF Position */
+#define MXC_F_FLC_INTR_FINISHED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FINISHED_IF_POS)) /**< FINISHED_IF Mask */
+#define MXC_F_FLC_INTR_FAILED_IF_POS 1 /**< FAILED_IF Position */
+#define MXC_F_FLC_INTR_FAILED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IF_POS)) /**< FAILED_IF Mask */
+#define MXC_F_FLC_INTR_FINISHED_IE_POS 8 /**< FINISHED_IE Position */
+#define MXC_F_FLC_INTR_FINISHED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FINISHED_IE_POS)) /**< FINISHED_IE Mask */
+#define MXC_F_FLC_INTR_FAILED_IE_POS 9 /**< FAILED_IE Position */
+#define MXC_F_FLC_INTR_FAILED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IE_POS)) /**< FAILED_IE Mask */
+#define MXC_F_FLC_INTR_FAIL_FLAGS_POS 16 /**< FAIL_FLAGS Position */
+#define MXC_F_FLC_INTR_FAIL_FLAGS ((uint32_t)(0x0000FFFFUL << MXC_F_FLC_INTR_FAIL_FLAGS_POS)) /**< FAIL_FLAGS Mask */
+/**@} end of group FLC_INTR */
+/**
+ * @defgroup FLC_PERFORM_Register FLC_PERFORM
+ * @ingroup flc_registers
+ * @brief Field Positions and Bit Masks for the FLC_PERFORM register.
+ * @{
+ */
+#define MXC_F_FLC_PERFORM_DELAY_SE_EN_POS 0 /**< DELAY_SE_EN Position */
+#define MXC_F_FLC_PERFORM_DELAY_SE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_DELAY_SE_EN_POS)) /**< DELAY_SE_EN Mask */
+#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS 8 /**< FAST_READ_MODE_EN Position */
+#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS)) /**< FAST_READ_MODE_EN Mask */
+#define MXC_F_FLC_PERFORM_EN_PREVENT_FAIL_POS 12 /**< EN_PREVENT_FAIL Position */
+#define MXC_F_FLC_PERFORM_EN_PREVENT_FAIL ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_PREVENT_FAIL_POS)) /**< EN_PREVENT_FAIL Mask */
+#define MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS_POS 16 /**< EN_BACK2BACK_RDS Position */
+#define MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS_POS)) /**< EN_BACK2BACK_RDS Mask */
+#define MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS_POS 20 /**< EN_BACK2BACK_WRS Position */
+#define MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS_POS)) /**< EN_BACK2BACK_WRS Mask */
+#define MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT_POS 24 /**< EN_MERGE_GRAB_GNT Position */
+#define MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT_POS)) /**< EN_MERGE_GRAB_GNT Mask */
+#define MXC_F_FLC_PERFORM_AUTO_TACC_POS 28 /**< AUTO_TACC Position */
+#define MXC_F_FLC_PERFORM_AUTO_TACC ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_AUTO_TACC_POS)) /**< AUTO_TACC Mask */
+#define MXC_F_FLC_PERFORM_AUTO_CLKDIV_POS 29 /**< AUTO_CLKDIV Position */
+#define MXC_F_FLC_PERFORM_AUTO_CLKDIV ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_AUTO_CLKDIV_POS)) /**< AUTO_CLKDIV Mask */
+/**@} end of group FLC_PERFORM */
+/**
+ * @defgroup FLC_STATUS_Register FLC_STATUS
+ * @ingroup flc_registers
+ * @brief Field Positions and Bit Masks for the FLC_STATUS register.
+ * @{
+ */
+#define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS 0 /**< JTAG_LOCK_WINDOW Position */
+#define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS)) /**< JTAG_LOCK_WINDOW Mask */
+#define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS 1 /**< JTAG_LOCK_STATIC Position */
+#define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS)) /**< JTAG_LOCK_STATIC Mask */
+#define MXC_F_FLC_STATUS_AUTO_LOCK_POS 3 /**< AUTO_LOCK Position */
+#define MXC_F_FLC_STATUS_AUTO_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_AUTO_LOCK_POS)) /**< AUTO_LOCK Mask */
+#define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS 29 /**< TRIM_UPDATE_DONE Position */
+#define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS)) /**< TRIM_UPDATE_DONE Mask */
+#define MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS 30 /**< INFO_BLOCK_VALID Position */
+#define MXC_F_FLC_STATUS_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS)) /**< INFO_BLOCK_VALID Mask */
+/**@} end of group FLC_STATUS*/
+/**
+ * @defgroup FLC_SECURITY_Register FLC_SECURITY
+ * @ingroup flc_registers
+ * @brief Field Positions and Bit Masks for the FLC_SECURITY register.
+ * @{
+ */
+#define MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS 0 /**< DEBUG_DISABLE Position */
+#define MXC_F_FLC_SECURITY_DEBUG_DISABLE ((uint32_t)(0x000000FFUL << MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS)) /**< DEBUG_DISABLE Mask */
+#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS 8 /**< MASS_ERASE_LOCK Position */
+#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS)) /**< MASS_ERASE_LOCK Mask */
+#define MXC_F_FLC_SECURITY_DISABLE_AHB_WR_POS 16 /**< DISABLE_AHB_WR Position */
+#define MXC_F_FLC_SECURITY_DISABLE_AHB_WR ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_DISABLE_AHB_WR_POS)) /**< DISABLE_AHB_WR Mask */
+#define MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK_POS 24 /**< FLC_SETTINGS_LOCK Position */
+#define MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK_POS)) /**< FLC_SETTINGS_LOCK Mask */
+#define MXC_F_FLC_SECURITY_SECURITY_LOCK_POS 28 /**< SECURITY_LOCK Position */
+#define MXC_F_FLC_SECURITY_SECURITY_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_SECURITY_LOCK_POS)) /**< SECURITY_LOCK Mask */
+/**@} end of group FLC_SECURITY */
+/**
+ * @defgroup FLC_BYPASS_Register FLC_BYPASS
+ * @ingroup flc_registers
+ * @brief Field Positions and Bit Masks for the FLC_BYPASS register.
+ * @{
+ */
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS 0 /**< DESTRUCT_BYPASS_ERASE Position */
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS)) /**< DESTRUCT_BYPASS_ERASE Mask */
+#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS 1 /**< SUPERWIPE_ERASE Position */
+#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS)) /**< SUPERWIPE_ERASE Mask */
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS 2 /**< DESTRUCT_BYPASS_COMPLETE Position */
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS)) /**< DESTRUCT_BYPASS_COMPLETE Mask */
+#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS 3 /**< SUPERWIPE_COMPLETE Position */
+#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS)) /**< SUPERWIPE_COMPLETE Mask */
+/**@} end of group FLC_BYPASS*/
+/**
+ * @defgroup FLC_CTRL2_Register FLC_CTRL2
+ * @ingroup flc_registers
+ * @brief Field Positions and Bit Masks for the FLC_CTRL2 register.
+ * @{
+ */
+#define MXC_F_FLC_CTRL2_FLASH_LVE_POS 0 /**< FLASH_LVE Position */
+#define MXC_F_FLC_CTRL2_FLASH_LVE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FLASH_LVE_POS)) /**< FLASH_LVE Mask */
+#define MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS 1 /**< FRC_FCLK1_ON Position */
+#define MXC_F_FLC_CTRL2_FRC_FCLK1_ON ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS)) /**< FRC_FCLK1_ON Mask */
+#define MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES_POS 3 /**< EN_WRITE_ALL_ZEROES Position */
+#define MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES_POS)) /**< EN_WRITE_ALL_ZEROES Mask */
+#define MXC_F_FLC_CTRL2_EN_CHANGE_POS 4 /**< EN_CHANGE Position */
+#define MXC_F_FLC_CTRL2_EN_CHANGE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_EN_CHANGE_POS)) /**< EN_CHANGE Mask */
+#define MXC_F_FLC_CTRL2_SLOW_CLK_POS 5 /**< SLOW_CLK Position */
+#define MXC_F_FLC_CTRL2_SLOW_CLK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_SLOW_CLK_POS)) /**< SLOW_CLK Mask */
+#define MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP_POS 6 /**< ENABLE_RAM_HRESP Position */
+#define MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP_POS)) /**< ENABLE_RAM_HRESP Mask */
+#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS 8 /**< BYPASS_AHB_FAIL Position */
+#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS)) /**< BYPASS_AHB_FAIL Mask */
+/**@} end of group FLC_CTRL2*/
+ /**
+ * @defgroup FLC_INTFL1_Register FLC_INTFL1
+ * @ingroup flc_registers
+ * @brief Field Positions and Bit Masks for the FLC_INTFL1 register.
+ * @{
+ */
+#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS 0 /**< SRAM_ADDR_WRAPPED Position */
+#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS)) /**< SRAM_ADDR_WRAPPED Mask */
+#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS 1 /**< INVALID_FLASH_ADDR Position */
+#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS)) /**< INVALID_FLASH_ADDR Mask */
+#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS 2 /**< FLASH_READ_LOCKED Position */
+#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS)) /**< FLASH_READ_LOCKED Mask */
+#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS 3 /**< TRIM_UPDATE_DONE Position */
+#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS)) /**< TRIM_UPDATE_DONE Mask */
+#define MXC_F_FLC_INTFL1_FLC_STATE_DONE_POS 4 /**< FLC_STATE_DONE Position */
+#define MXC_F_FLC_INTFL1_FLC_STATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLC_STATE_DONE_POS)) /**< FLC_STATE_DONE Mask */
+#define MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE_POS 5 /**< FLC_PROG_COMPLETE Position */
+#define MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE_POS)) /**< FLC_PROG_COMPLETE Mask */
+/**@} end of group FLC_INTFL1 */
+/**
+ * @defgroup FLC_INTEN1_Register FLC_INTEN1
+ * @ingroup flc_registers
+ * @brief Field Positions and Bit Masks for the FLC_INTEN1 register.
+ * @{
+ */
+#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS 0 /**< SRAM_ADDR_WRAPPED Position */
+#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS)) /**< SRAM_ADDR_WRAPPED Mask */
+#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS 1 /**< INVALID_FLASH_ADDR Position */
+#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS)) /**< INVALID_FLASH_ADDR Mask */
+#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS 2 /**< FLASH_READ_LOCKED Position */
+#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS)) /**< FLASH_READ_LOCKED Mask */
+#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS 3 /**< TRIM_UPDATE_DONE Position */
+#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS)) /**< TRIM_UPDATE_DONE Mask */
+#define MXC_F_FLC_INTEN1_FLC_STATE_DONE_POS 4 /**< FLC_STATE_DONE Position */
+#define MXC_F_FLC_INTEN1_FLC_STATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLC_STATE_DONE_POS)) /**< FLC_STATE_DONE Mask */
+#define MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE_POS 5 /**< FLC_PROG_COMPLETE Position */
+#define MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE_POS)) /**< FLC_PROG_COMPLETE Mask */
+/**@} end of group FLC_INTEN1*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_FLC_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/gpio.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32625/gpio.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,288 @@
+/* CMSIS-DAP Interface Firmware
+ * Copyright (c) 2009-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "max32625.h"
+#include "clkman_regs.h"
+#include "gpio_regs.h"
+#include "IO_Config.h"
+#include "gpio.h"
+#include "adc_regs.h"
+#include "pwrman_regs.h"
+#include "ioman_regs.h"
+
+// For channels 4 and 5; the target VIO inputs
+// 1.6V is the lowest VIO can operate at,
+// so set this as minimum acceptable voltage.
+// round(AIN/(5 * 1.2)*(2^10-1))
+#define VIO_ADC_MIN 273
+
+// Bitband pointers
+volatile uint32_t *tck_in;
+volatile uint32_t *tck_out;
+volatile uint32_t *tms_in;
+volatile uint32_t *tms_out;
+volatile uint32_t *rst_in;
+volatile uint32_t *rst_out;
+
+uint32_t swdio_port;
+uint32_t swdio_pin;
+uint32_t swclk_port;
+uint32_t swclk_pin;
+uint32_t nreset_port;
+uint32_t nreset_pin;
+
+int32_t uart_set_instance(uint32_t inst);
+
+/******************************************************************************/
+static inline void use_vddioh(int port, int pin)
+{
+ if (port > 3) {
+ MXC_IOMAN->use_vddioh_1 |= 1U << (((port - 4) * 8) + pin);
+ } else {
+ MXC_IOMAN->use_vddioh_0 |= 1U << ((port * 8) + pin);
+ }
+}
+
+/******************************************************************************/
+static uint16_t readADC(uint8_t ch)
+{
+ uint32_t ctrl_tmp;
+
+ // Select channel
+ ctrl_tmp = MXC_ADC->ctrl;
+ ctrl_tmp &= ~MXC_F_ADC_CTRL_ADC_CHSEL;
+ ctrl_tmp |= ((ch << MXC_F_ADC_CTRL_ADC_CHSEL_POS) & MXC_F_ADC_CTRL_ADC_CHSEL);
+
+ // Clear channel configuration
+ ctrl_tmp &= ~(MXC_F_ADC_CTRL_ADC_REFSCL | MXC_F_ADC_CTRL_ADC_SCALE | MXC_F_ADC_CTRL_BUF_BYPASS);
+
+ // ADC reference scaling
+ ctrl_tmp |= MXC_F_ADC_CTRL_ADC_REFSCL;
+
+ if ((ch == SWD_VIO_CH) || (ch == HDR_VIO_CH)) {
+ ctrl_tmp |= MXC_F_ADC_CTRL_ADC_SCALE;
+ }
+
+ // Do not bypass buffer, except when measuring near ground.
+ // This may be the case for measuring 1-Wire ground detect on channels 2 and 3.
+ if ((ch == SWD_GNDDET_CH) || (ch == HDR_GNDDET_CH)) {
+ ctrl_tmp |= MXC_F_ADC_CTRL_BUF_BYPASS;
+ }
+
+ // Write this configuration
+ MXC_ADC->ctrl = ctrl_tmp;
+
+ // Clear conversion done interrupt flag
+ MXC_ADC->intr = MXC_F_ADC_INTR_ADC_DONE_IF;
+
+ // Start conversion
+ MXC_ADC->ctrl |= MXC_F_ADC_CTRL_CPU_ADC_START;
+
+ while (!(MXC_ADC->intr & MXC_F_ADC_INTR_ADC_DONE_IF));
+
+ return (uint16_t)(MXC_ADC->data);
+}
+
+/******************************************************************************/
+void target_set_interface(TARGET_INTERFACE mode)
+{
+ switch (mode) {
+ case IO_SWD_EXT:
+ swdio_port = PIN_SWDIO_PORT;
+ swdio_pin = PIN_SWDIO_PIN;
+ swclk_port = PIN_SWCLK_PORT;
+ swclk_pin = PIN_SWCLK_PIN;
+ nreset_port = PIN_nRESET_PORT;
+ nreset_pin = PIN_nRESET_PIN;
+
+ MXC_CLRBIT(&MXC_GPIO->out_val[EN_VDDIOH_PORT], EN_VDDIOH_PIN); // Low to disable SWOUT
+ MXC_SETBIT(&MXC_GPIO->out_val[IOH_OW_EN_PORT], IOH_OW_EN_PIN); // High to power MAX14689
+ MXC_SETBIT(&MXC_GPIO->out_val[SWD_DIP_SEL_PORT], SWD_DIP_SEL_PIN); // High to connect Bn <-> Cn
+ uart_set_instance(CDC_ACM_UART_SWD);
+ break;
+ case IO_DIP_EXT:
+ swdio_port = PIN_DIP_SWDIO_PORT;
+ swdio_pin = PIN_DIP_SWDIO_PIN;
+ swclk_port = PIN_DIP_SWCLK_PORT;
+ swclk_pin = PIN_DIP_SWCLK_PIN;
+ nreset_port = PIN_DIP_nRESET_PORT;
+ nreset_pin = PIN_DIP_nRESET_PIN;
+
+ MXC_CLRBIT(&MXC_GPIO->out_val[EN_VDDIOH_PORT], EN_VDDIOH_PIN); // Low to disable SWOUT
+ MXC_SETBIT(&MXC_GPIO->out_val[IOH_OW_EN_PORT], IOH_OW_EN_PIN); // High to power MAX14689
+ MXC_CLRBIT(&MXC_GPIO->out_val[SWD_DIP_SEL_PORT], SWD_DIP_SEL_PIN); // Low to connect Bn <-> An
+ uart_set_instance(CDC_ACM_UART_DIP);
+ break;
+ }
+}
+
+/******************************************************************************/
+void gpio_init(void)
+{
+ int i;
+ uint32_t out_mode;
+
+ // Ensure that the GPIO clock is enabled
+ if (MXC_CLKMAN->sys_clk_ctrl_6_gpio == MXC_S_CLKMAN_CLK_SCALE_DISABLED) {
+ MXC_CLKMAN->sys_clk_ctrl_6_gpio = MXC_S_CLKMAN_CLK_SCALE_DIV_1;
+ }
+
+ // Make all GPIO pins readable
+ for (i = 0; i < MXC_GPIO_NUM_PORTS; i++) {
+ MXC_GPIO->in_mode[i] = 0x00000000;
+ }
+
+ // Set to enable the board to power VDDIOH and in turn the target micro
+ // Clear to disable the board from powering VDDIOH
+ MXC_CLRBIT(&MXC_GPIO->out_val[EN_VDDIOH_PORT], EN_VDDIOH_PIN);
+ out_mode = MXC_GPIO->out_mode[EN_VDDIOH_PORT];
+ out_mode &= ~(0xFU << (4 * EN_VDDIOH_PIN));
+ out_mode |= (MXC_V_GPIO_OUT_MODE_NORMAL << (4 * EN_VDDIOH_PIN));
+ MXC_GPIO->out_mode[EN_VDDIOH_PORT] = out_mode;
+
+ // LED initial state off
+ MXC_GPIO->out_val[PIN_DAP_LED_PORT] |= (1 << PIN_DAP_LED_PIN);
+ MXC_GPIO->out_val[PIN_MSD_LED_PORT] |= (1 << PIN_MSD_LED_PIN);
+ MXC_GPIO->out_val[PIN_CDC_LED_PORT] |= (1 << PIN_CDC_LED_PIN);
+
+ // LED outputs
+ out_mode = MXC_GPIO->out_mode[PIN_DAP_LED_PORT];
+ out_mode &= ~(0xFU << (4 * PIN_DAP_LED_PIN));
+ out_mode |= (MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << (4 * PIN_DAP_LED_PIN));
+ MXC_GPIO->out_mode[PIN_DAP_LED_PORT] = out_mode;
+
+ out_mode = MXC_GPIO->out_mode[PIN_MSD_LED_PORT];
+ out_mode &= ~(0xFU << (4 * PIN_MSD_LED_PIN));
+ out_mode |= (MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << (4 * PIN_MSD_LED_PIN));
+ MXC_GPIO->out_mode[PIN_MSD_LED_PORT] = out_mode;
+
+ out_mode = MXC_GPIO->out_mode[PIN_CDC_LED_PORT];
+ out_mode &= ~(0xFU << (4 * PIN_CDC_LED_PIN));
+ out_mode |= (MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << (4 * PIN_CDC_LED_PIN));
+ MXC_GPIO->out_mode[PIN_CDC_LED_PORT] = out_mode;
+
+ // Button Input
+ out_mode = MXC_GPIO->out_mode[PIN_RESET_IN_NO_FWRD_PORT];
+ out_mode &= ~(0xFU << (4 * PIN_RESET_IN_NO_FWRD_PIN));
+ out_mode |= (MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << (4 * PIN_RESET_IN_NO_FWRD_PIN));
+ MXC_GPIO->out_mode[PIN_RESET_IN_NO_FWRD_PORT] = out_mode;
+ MXC_GPIO->out_val[PIN_RESET_IN_NO_FWRD_PORT] |= (0x1U << PIN_RESET_IN_NO_FWRD_PIN);
+
+ // IOH_1W_EN (must be configured for strong drive)
+ MXC_SETBIT(&MXC_GPIO->out_val[IOH_OW_EN_PORT], IOH_OW_EN_PIN);
+ out_mode = MXC_GPIO->out_mode[IOH_OW_EN_PORT];
+ out_mode &= ~(0xFU << (4 * IOH_OW_EN_PIN));
+ out_mode |= (MXC_V_GPIO_OUT_MODE_FAST_DRIVE << (4 * IOH_OW_EN_PIN));
+ MXC_GPIO->out_mode[IOH_OW_EN_PORT] = out_mode;
+
+ // SWD_DIP_SEL (must be configured for strong drive)
+ MXC_CLRBIT(&MXC_GPIO->out_val[SWD_DIP_SEL_PORT], SWD_DIP_SEL_PIN);
+ out_mode = MXC_GPIO->out_mode[SWD_DIP_SEL_PORT];
+ out_mode &= ~(0xFU << (4 * SWD_DIP_SEL_PIN));
+ out_mode |= (MXC_V_GPIO_OUT_MODE_FAST_DRIVE << (4 * SWD_DIP_SEL_PIN));
+ MXC_GPIO->out_mode[SWD_DIP_SEL_PORT] = out_mode;
+
+ // Strong pull-up disable
+ MXC_SETBIT(&MXC_GPIO->out_val[OWM_SUP_PORT], OWM_SUP_PIN);
+ out_mode = MXC_GPIO->out_mode[OWM_SUP_PORT];
+ out_mode &= ~(0xFU << (4 * OWM_SUP_PIN));
+ out_mode |= (MXC_V_GPIO_OUT_MODE_NORMAL << (4 * OWM_SUP_PIN));
+ MXC_GPIO->out_mode[OWM_SUP_PORT] = out_mode;
+
+ // VDDIOH driver isn't strong enough with the strong pull-up
+ MXC_IOMAN->use_vddioh_1 &= ~(1U << (((OWM_PORT - 4) * 8) + OWM_PIN));
+ // 1V8 VDDIO is not high enough to turn off the FET if VDDIOH is 3V3
+ MXC_IOMAN->use_vddioh_1 |= (1U << (((OWM_PORT - 4) * 8) + OWM_SUP_PIN));
+
+ use_vddioh(PIN_nRESET_PORT, PIN_nRESET_PIN);
+ use_vddioh(PIN_DIP_nRESET_PORT, PIN_DIP_nRESET_PIN);
+ use_vddioh(PIN_SWCLK_PORT, PIN_SWCLK_PIN);
+ use_vddioh(PIN_DIP_SWCLK_PORT, PIN_DIP_SWCLK_PIN);
+ use_vddioh(PIN_SWDIO_PORT, PIN_SWDIO_PIN);
+ use_vddioh(PIN_DIP_SWDIO_PORT, PIN_DIP_SWDIO_PIN);
+ use_vddioh(PIN_TX_PORT, PIN_TX_PIN);
+ use_vddioh(PIN_RX_PORT, PIN_RX_PIN);
+ use_vddioh(PIN_DIP_TX_PORT, PIN_DIP_TX_PIN);
+ use_vddioh(PIN_DIP_RX_PORT, PIN_DIP_RX_PIN);
+
+ // Setup the ADC; read the ADC to set IO interface
+ MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED;
+ MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE;
+
+ MXC_ADC->ctrl = (MXC_F_ADC_CTRL_ADC_PU |
+ MXC_F_ADC_CTRL_ADC_CLK_EN |
+ MXC_F_ADC_CTRL_BUF_PU |
+ MXC_F_ADC_CTRL_ADC_REFBUF_PU |
+ MXC_F_ADC_CTRL_ADC_CHGPUMP_PU);
+
+ // Set IO interface
+ if (readADC(SWD_VIO_CH) > VIO_ADC_MIN) {
+ target_set_interface(IO_SWD_EXT);
+ } else if (readADC(HDR_VIO_CH) > VIO_ADC_MIN) {
+ target_set_interface(IO_DIP_EXT);
+ } else {
+ // Default to SWD interface
+ target_set_interface(IO_SWD_EXT);
+ }
+
+}
+
+/******************************************************************************/
+void gpio_set_hid_led(gpio_led_state_t state)
+{
+ if (state == GPIO_LED_ON) {
+ MXC_CLRBIT(&MXC_GPIO->out_val[PIN_DAP_LED_PORT], PIN_DAP_LED_PIN);
+ } else {
+ MXC_SETBIT(&MXC_GPIO->out_val[PIN_DAP_LED_PORT], PIN_DAP_LED_PIN);
+ }
+}
+
+/******************************************************************************/
+void gpio_set_msc_led(gpio_led_state_t state)
+{
+ if (state == GPIO_LED_ON) {
+ MXC_CLRBIT(&MXC_GPIO->out_val[PIN_MSD_LED_PORT], PIN_MSD_LED_PIN);
+ } else {
+ MXC_SETBIT(&MXC_GPIO->out_val[PIN_MSD_LED_PORT], PIN_MSD_LED_PIN);
+ }
+}
+
+/******************************************************************************/
+void gpio_set_cdc_led(gpio_led_state_t state)
+{
+ if (state == GPIO_LED_ON) {
+ MXC_CLRBIT(&MXC_GPIO->out_val[PIN_CDC_LED_PORT], PIN_CDC_LED_PIN);
+ } else {
+ MXC_SETBIT(&MXC_GPIO->out_val[PIN_CDC_LED_PORT], PIN_CDC_LED_PIN);
+ }
+}
+
+/******************************************************************************/
+uint8_t gpio_get_reset_btn_no_fwrd(void)
+{
+ return !MXC_GETBIT(&MXC_GPIO->in_val[PIN_RESET_IN_NO_FWRD_PORT], PIN_RESET_IN_NO_FWRD_PIN);
+}
+
+/******************************************************************************/
+uint8_t gpio_get_reset_btn_fwrd(void)
+{
+ return 0;
+}
+
+/******************************************************************************/
+void gpio_set_board_power(bool powerEnabled)
+{
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/gpio_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32625/gpio_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,659 @@
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+*************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_GPIO_REGS_H_
+#define _MXC_GPIO_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+///@cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+///@endcond
+
+/* **** Definitions **** */
+
+/**
+ * @defgroup gpio_registers Registers
+ * @ingroup gpio
+ * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
+ * @{
+ */
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/**
+ * Structure type to access the GPIO Registers
+ */
+typedef struct {
+ __IO uint32_t rst_mode[16]; /**< <tt>\b 0x0000-0x003C</tt> GPIO_RST_MODE_P[0..15] Registers - Power-On Reset Output Drive Mode */
+ __IO uint32_t free[16]; /**< <tt>\b 0x0040-0x007C</tt> GPIO_FREE_P[0..15] Registers - Free for GPIO Operation Flags */
+ __IO uint32_t out_mode[16]; /**< <tt>\b 0x0080-0x00BC</tt> GPIO_OUT_MODE_P[0..15] Registers - Output Drive Mode */
+ __IO uint32_t out_val[16]; /**< <tt>\b 0x00C0-0x00FC</tt> GPIO_OUT_VAL_P[0..15] Registers - GPIO Output Value */
+ __IO uint32_t func_sel[16]; /**< <tt>\b 0x0100-0x013C</tt> GPIO_FUNC_SEL_P[0..15] Registers - GPIO Function Select */
+ __IO uint32_t in_mode[16]; /**< <tt>\b 0x0140-0x017C</tt> GPIO_IN_MODE_P[0..15] Registers - GPIO Input Monitoring Mode */
+ __IO uint32_t in_val[16]; /**< <tt>\b 0x0180-0x01BC</tt> GPIO_IN_VAL_P[0..15] Registers - GPIO Input Value */
+ __IO uint32_t int_mode[16]; /**< <tt>\b 0x01C0-0x01FC</tt> GPIO_INT_MODE_P[0..15] Registers - Interrupt Detection Mode */
+ __IO uint32_t intfl[16]; /**< <tt>\b 0x0200-0x023C</tt> GPIO_INTFL_P[0..15] Registers - Interrupt Flags */
+ __IO uint32_t inten[16]; /**< <tt>\b 0x0240-0x027C</tt> GPIO_INTEN_P[0..15] Registers - Interrupt Enables */
+} mxc_gpio_regs_t;
+/**@} end of gpio_registers group */
+
+/*
+ Register offsets for module GPIO.
+*/
+/**
+ * @defgroup GPIO_Register_Offsets Register Offsets
+ * @ingroup gpio_registers
+ * @brief GPIO Register Offsets from the GPIO Base Address.
+ * @{
+ */
+/**
+ * @defgroup gpio_rst_mode_offsets Registers GPIO_RST_MODE_P[0..15] Offsets
+ * @ingroup GPIO_Register_Offsets
+ * @brief GPIO_RST_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_GPIO_OFFS_RST_MODE_P0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt>\b 0x0000</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P1 ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt>\b 0x0004</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P2 ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt>\b 0x0008</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P3 ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt>\b 0x000C</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P4 ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt>\b 0x0010</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P5 ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt>\b 0x0014</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P6 ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt>\b 0x0018</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P7 ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt>\b 0x001C</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P8 ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt>\b 0x0020</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P9 ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt>\b 0x0024</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P10 ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt>\b 0x0028</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P11 ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt>\b 0x002C</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P12 ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: <tt>\b 0x0030</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P13 ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt>\b 0x0034</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P14 ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt>\b 0x0038</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P15 ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt>\b 0x003C</tt> */
+/**@} end of gpio_rst_mode group */
+/**
+ * @defgroup gpio_free_offsets Registers GPIO_FREE_P[0..15] Offsets
+ * @ingroup GPIO_Register_Offsets
+ * @brief GPIO_FREE_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_GPIO_OFFS_FREE_P0 ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt>\b 0x0040</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P1 ((uint32_t)0x00000044UL) /**< Offset from GPIO Base Address: <tt>\b 0x0044</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P2 ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt>\b 0x0048</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P3 ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt>\b 0x004C</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P4 ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt>\b 0x0050</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P5 ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt>\b 0x0054</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P6 ((uint32_t)0x00000058UL) /**< Offset from GPIO Base Address: <tt>\b 0x0058</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P7 ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt>\b 0x005C</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P8 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt>\b 0x0060</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P9 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt>\b 0x0064</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P10 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt>\b 0x0068</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P11 ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt>\b 0x006C</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P12 ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt>\b 0x0070</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P13 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt>\b 0x0074</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P14 ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt>\b 0x0078</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P15 ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt>\b 0x007C</tt> */
+/**@} end of gpio_free group */
+/**
+ * @defgroup gpio_out_mode_offsets GPIO_OUT_MODE_P[0..15] Registers
+ * @ingroup GPIO_Register_Offsets
+ * @brief GPIO_OUT_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P0 ((uint32_t)0x00000080UL) /**< Offset from GPIO Base Address: <tt>\b 0x0080</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P1 ((uint32_t)0x00000084UL) /**< Offset from GPIO Base Address: <tt>\b 0x0084</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P2 ((uint32_t)0x00000088UL) /**< Offset from GPIO Base Address: <tt>\b 0x0088</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P3 ((uint32_t)0x0000008CUL) /**< Offset from GPIO Base Address: <tt>\b 0x008C</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P4 ((uint32_t)0x00000090UL) /**< Offset from GPIO Base Address: <tt>\b 0x0090</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P5 ((uint32_t)0x00000094UL) /**< Offset from GPIO Base Address: <tt>\b 0x0094</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P6 ((uint32_t)0x00000098UL) /**< Offset from GPIO Base Address: <tt>\b 0x0098</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P7 ((uint32_t)0x0000009CUL) /**< Offset from GPIO Base Address: <tt>\b 0x009C</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P8 ((uint32_t)0x000000A0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00A0</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P9 ((uint32_t)0x000000A4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00A4</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P10 ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00A8</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P11 ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt>\b 0x00AC</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P12 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00B0</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P13 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00B4</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P14 ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00B8</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P15 ((uint32_t)0x000000BCUL) /**< Offset from GPIO Base Address: <tt>\b 0x00BC</tt> */
+/**@} end of gpio_out_mode group */
+/**
+ * @defgroup gpio_out_val_offsets GPIO_OUT_VAL_P[0..15] Registers
+ * @ingroup GPIO_Register_Offsets
+ * @brief GPIO_OUT_VAL_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P0 ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00C0</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P1 ((uint32_t)0x000000C4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00C4</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P2 ((uint32_t)0x000000C8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00C8</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P3 ((uint32_t)0x000000CCUL) /**< Offset from GPIO Base Address: <tt>\b 0x00CC</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P4 ((uint32_t)0x000000D0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00D0</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P5 ((uint32_t)0x000000D4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00D4</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P6 ((uint32_t)0x000000D8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00D8</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P7 ((uint32_t)0x000000DCUL) /**< Offset from GPIO Base Address: <tt>\b 0x00DC</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P8 ((uint32_t)0x000000E0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00E0</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P9 ((uint32_t)0x000000E4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00E4</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P10 ((uint32_t)0x000000E8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00E8</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P11 ((uint32_t)0x000000ECUL) /**< Offset from GPIO Base Address: <tt>\b 0x00EC</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P12 ((uint32_t)0x000000F0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00F0</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P13 ((uint32_t)0x000000F4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00F4</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P14 ((uint32_t)0x000000F8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00F8</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P15 ((uint32_t)0x000000FCUL) /**< Offset from GPIO Base Address: <tt>\b 0x00FC</tt> */
+/**@} end of gpio_out_val group */
+/**
+ * @defgroup gpio_func_sel_offsets GPIO_FUNC_SEL_P[0..15] Registers
+ * @ingroup GPIO_Register_Offsets
+ * @brief GPIO_FUNC_SEL_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P0 ((uint32_t)0x00000100UL) /**< Offset from GPIO Base Address: <tt>\b 0x0100</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P1 ((uint32_t)0x00000104UL) /**< Offset from GPIO Base Address: <tt>\b 0x0104</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P2 ((uint32_t)0x00000108UL) /**< Offset from GPIO Base Address: <tt>\b 0x0108</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P3 ((uint32_t)0x0000010CUL) /**< Offset from GPIO Base Address: <tt>\b 0x010C</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P4 ((uint32_t)0x00000110UL) /**< Offset from GPIO Base Address: <tt>\b 0x0110</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P5 ((uint32_t)0x00000114UL) /**< Offset from GPIO Base Address: <tt>\b 0x0114</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P6 ((uint32_t)0x00000118UL) /**< Offset from GPIO Base Address: <tt>\b 0x0118</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P7 ((uint32_t)0x0000011CUL) /**< Offset from GPIO Base Address: <tt>\b 0x011C</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P8 ((uint32_t)0x00000120UL) /**< Offset from GPIO Base Address: <tt>\b 0x0120</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P9 ((uint32_t)0x00000124UL) /**< Offset from GPIO Base Address: <tt>\b 0x0124</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P10 ((uint32_t)0x00000128UL) /**< Offset from GPIO Base Address: <tt>\b 0x0128</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P11 ((uint32_t)0x0000012CUL) /**< Offset from GPIO Base Address: <tt>\b 0x012C</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P12 ((uint32_t)0x00000130UL) /**< Offset from GPIO Base Address: <tt>\b 0x0130</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P13 ((uint32_t)0x00000134UL) /**< Offset from GPIO Base Address: <tt>\b 0x0134</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P14 ((uint32_t)0x00000138UL) /**< Offset from GPIO Base Address: <tt>\b 0x0138</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P15 ((uint32_t)0x0000013CUL) /**< Offset from GPIO Base Address: <tt>\b 0x013C</tt> */
+/**@} end of gpio_func_sel */
+/**
+ * @defgroup gpio_in_mode_offsets GPIO_IN_MODE_P[0..15] Registers
+ * @ingroup GPIO_Register_Offsets
+ * @brief GPIO_IN_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_GPIO_OFFS_IN_MODE_P0 ((uint32_t)0x00000140UL) /**< Offset from GPIO Base Address: <tt>\b 0x0140</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P1 ((uint32_t)0x00000144UL) /**< Offset from GPIO Base Address: <tt>\b 0x0144</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P2 ((uint32_t)0x00000148UL) /**< Offset from GPIO Base Address: <tt>\b 0x0148</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P3 ((uint32_t)0x0000014CUL) /**< Offset from GPIO Base Address: <tt>\b 0x014C</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P4 ((uint32_t)0x00000150UL) /**< Offset from GPIO Base Address: <tt>\b 0x0150</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P5 ((uint32_t)0x00000154UL) /**< Offset from GPIO Base Address: <tt>\b 0x0154</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P6 ((uint32_t)0x00000158UL) /**< Offset from GPIO Base Address: <tt>\b 0x0158</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P7 ((uint32_t)0x0000015CUL) /**< Offset from GPIO Base Address: <tt>\b 0x015C</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P8 ((uint32_t)0x00000160UL) /**< Offset from GPIO Base Address: <tt>\b 0x0160</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P9 ((uint32_t)0x00000164UL) /**< Offset from GPIO Base Address: <tt>\b 0x0164</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P10 ((uint32_t)0x00000168UL) /**< Offset from GPIO Base Address: <tt>\b 0x0168</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P11 ((uint32_t)0x0000016CUL) /**< Offset from GPIO Base Address: <tt>\b 0x016C</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P12 ((uint32_t)0x00000170UL) /**< Offset from GPIO Base Address: <tt>\b 0x0170</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P13 ((uint32_t)0x00000174UL) /**< Offset from GPIO Base Address: <tt>\b 0x0174</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P14 ((uint32_t)0x00000178UL) /**< Offset from GPIO Base Address: <tt>\b 0x0178</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P15 ((uint32_t)0x0000017CUL) /**< Offset from GPIO Base Address: <tt>\b 0x017C</tt> */
+/**@} end of gpio_in_mode group */
+/**
+ * @defgroup gpio_in_val_offsets GPIO_IN_VAL_P[0..15] Registers
+ * @ingroup GPIO_Register_Offsets
+ * @brief GPIO_IN_VAL_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_GPIO_OFFS_IN_VAL_P0 ((uint32_t)0x00000180UL) /**< Offset from GPIO Base Address: <tt>\b 0x0180</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P1 ((uint32_t)0x00000184UL) /**< Offset from GPIO Base Address: <tt>\b 0x0184</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P2 ((uint32_t)0x00000188UL) /**< Offset from GPIO Base Address: <tt>\b 0x0188</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P3 ((uint32_t)0x0000018CUL) /**< Offset from GPIO Base Address: <tt>\b 0x018C</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P4 ((uint32_t)0x00000190UL) /**< Offset from GPIO Base Address: <tt>\b 0x0190</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P5 ((uint32_t)0x00000194UL) /**< Offset from GPIO Base Address: <tt>\b 0x0194</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P6 ((uint32_t)0x00000198UL) /**< Offset from GPIO Base Address: <tt>\b 0x0198</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P7 ((uint32_t)0x0000019CUL) /**< Offset from GPIO Base Address: <tt>\b 0x019C</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P8 ((uint32_t)0x000001A0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01A0</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P9 ((uint32_t)0x000001A4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01A4</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P10 ((uint32_t)0x000001A8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01A8</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P11 ((uint32_t)0x000001ACUL) /**< Offset from GPIO Base Address: <tt>\b 0x01AC</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P12 ((uint32_t)0x000001B0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01B0</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P13 ((uint32_t)0x000001B4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01B4</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P14 ((uint32_t)0x000001B8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01B8</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P15 ((uint32_t)0x000001BCUL) /**< Offset from GPIO Base Address: <tt>\b 0x01BC</tt> */
+/**@} end of gpio_in_val group */
+/**
+ * @defgroup gpio_int_mode_offsets GPIO_INT_MODE_P[0..15] Registers
+ * @ingroup GPIO_Register_Offsets
+ * @brief GPIO_INT_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_GPIO_OFFS_INT_MODE_P0 ((uint32_t)0x000001C0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01C0</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P1 ((uint32_t)0x000001C4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01C4</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P2 ((uint32_t)0x000001C8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01C8</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P3 ((uint32_t)0x000001CCUL) /**< Offset from GPIO Base Address: <tt>\b 0x01CC</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P4 ((uint32_t)0x000001D0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01D0</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P5 ((uint32_t)0x000001D4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01D4</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P6 ((uint32_t)0x000001D8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01D8</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P7 ((uint32_t)0x000001DCUL) /**< Offset from GPIO Base Address: <tt>\b 0x01DC</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P8 ((uint32_t)0x000001E0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01E0</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P9 ((uint32_t)0x000001E4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01E4</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P10 ((uint32_t)0x000001E8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01E8</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P11 ((uint32_t)0x000001ECUL) /**< Offset from GPIO Base Address: <tt>\b 0x01EC</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P12 ((uint32_t)0x000001F0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01F0</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P13 ((uint32_t)0x000001F4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01F4</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P14 ((uint32_t)0x000001F8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01F8</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P15 ((uint32_t)0x000001FCUL) /**< Offset from GPIO Base Address: <tt>\b 0x01FC</tt> */
+/**@} end of gpio_int_mode group */
+/**
+ * @defgroup gpio_int_flag_offsets GPIO_INTFL_P[0..15] Registers
+ * @ingroup GPIO_Register_Offsets
+ * @brief GPIO_INTFL_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_GPIO_OFFS_INTFL_P0 ((uint32_t)0x00000200UL) /**< Offset from GPIO Base Address: <tt>\b 0x0200</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P1 ((uint32_t)0x00000204UL) /**< Offset from GPIO Base Address: <tt>\b 0x0204</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P2 ((uint32_t)0x00000208UL) /**< Offset from GPIO Base Address: <tt>\b 0x0208</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P3 ((uint32_t)0x0000020CUL) /**< Offset from GPIO Base Address: <tt>\b 0x020C</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P4 ((uint32_t)0x00000210UL) /**< Offset from GPIO Base Address: <tt>\b 0x0210</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P5 ((uint32_t)0x00000214UL) /**< Offset from GPIO Base Address: <tt>\b 0x0214</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P6 ((uint32_t)0x00000218UL) /**< Offset from GPIO Base Address: <tt>\b 0x0218</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P7 ((uint32_t)0x0000021CUL) /**< Offset from GPIO Base Address: <tt>\b 0x021C</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P8 ((uint32_t)0x00000220UL) /**< Offset from GPIO Base Address: <tt>\b 0x0220</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P9 ((uint32_t)0x00000224UL) /**< Offset from GPIO Base Address: <tt>\b 0x0224</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P10 ((uint32_t)0x00000228UL) /**< Offset from GPIO Base Address: <tt>\b 0x0228</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P11 ((uint32_t)0x0000022CUL) /**< Offset from GPIO Base Address: <tt>\b 0x022C</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P12 ((uint32_t)0x00000230UL) /**< Offset from GPIO Base Address: <tt>\b 0x0230</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P13 ((uint32_t)0x00000234UL) /**< Offset from GPIO Base Address: <tt>\b 0x0234</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P14 ((uint32_t)0x00000238UL) /**< Offset from GPIO Base Address: <tt>\b 0x0238</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P15 ((uint32_t)0x0000023CUL) /**< Offset from GPIO Base Address: <tt>\b 0x023C</tt> */
+/**@} end of gpio_int_flag group */
+/**
+ * @defgroup gpio_int_enable_offsets GPIO_INTEN_P[0..15] Registers
+ * @ingroup GPIO_Register_Offsets
+ * @brief GPIO_INTEN_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_GPIO_OFFS_INTEN_P0 ((uint32_t)0x00000240UL) /**< Offset from GPIO Base Address: <tt>\b 0x0240</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P1 ((uint32_t)0x00000244UL) /**< Offset from GPIO Base Address: <tt>\b 0x0244</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P2 ((uint32_t)0x00000248UL) /**< Offset from GPIO Base Address: <tt>\b 0x0248</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P3 ((uint32_t)0x0000024CUL) /**< Offset from GPIO Base Address: <tt>\b 0x024C</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P4 ((uint32_t)0x00000250UL) /**< Offset from GPIO Base Address: <tt>\b 0x0250</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P5 ((uint32_t)0x00000254UL) /**< Offset from GPIO Base Address: <tt>\b 0x0254</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P6 ((uint32_t)0x00000258UL) /**< Offset from GPIO Base Address: <tt>\b 0x0258</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P7 ((uint32_t)0x0000025CUL) /**< Offset from GPIO Base Address: <tt>\b 0x025C</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P8 ((uint32_t)0x00000260UL) /**< Offset from GPIO Base Address: <tt>\b 0x0260</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P9 ((uint32_t)0x00000264UL) /**< Offset from GPIO Base Address: <tt>\b 0x0264</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P10 ((uint32_t)0x00000268UL) /**< Offset from GPIO Base Address: <tt>\b 0x0268</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P11 ((uint32_t)0x0000026CUL) /**< Offset from GPIO Base Address: <tt>\b 0x026C</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P12 ((uint32_t)0x00000270UL) /**< Offset from GPIO Base Address: <tt>\b 0x0270</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P13 ((uint32_t)0x00000274UL) /**< Offset from GPIO Base Address: <tt>\b 0x0274</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P14 ((uint32_t)0x00000278UL) /**< Offset from GPIO Base Address: <tt>\b 0x0278</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P15 ((uint32_t)0x0000027CUL) /**< Offset from GPIO Base Address: <tt>\b 0x027C</tt> */
+/**@}*/
+/**@} end of GPIO_Register_Offsets */
+
+/*
+ Field positions and masks for module GPIO.
+*/
+ /**
+ * @defgroup GPIO_RST_MODE_Register GPIO_RST_MODE
+ * @ingroup gpio_registers
+ * @brief Field Positions and Bit Masks for the GPIO_RST_MODE register.
+ * @{
+ */
+#define MXC_F_GPIO_RST_MODE_PIN0_POS 0 /**< PIN0 Position */
+#define MXC_F_GPIO_RST_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN0_POS)) /**< PIN0 Mask */
+#define MXC_F_GPIO_RST_MODE_PIN1_POS 4 /**< PIN1 Position */
+#define MXC_F_GPIO_RST_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN1_POS)) /**< PIN1 Mask */
+#define MXC_F_GPIO_RST_MODE_PIN2_POS 8 /**< PIN2 Position */
+#define MXC_F_GPIO_RST_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN2_POS)) /**< PIN2 Mask */
+#define MXC_F_GPIO_RST_MODE_PIN3_POS 12 /**< PIN3 Position */
+#define MXC_F_GPIO_RST_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN3_POS)) /**< PIN3 Mask */
+#define MXC_F_GPIO_RST_MODE_PIN4_POS 16 /**< PIN4 Position */
+#define MXC_F_GPIO_RST_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN4_POS)) /**< PIN4 Mask */
+#define MXC_F_GPIO_RST_MODE_PIN5_POS 20 /**< PIN5 Position */
+#define MXC_F_GPIO_RST_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN5_POS)) /**< PIN5 Mask */
+#define MXC_F_GPIO_RST_MODE_PIN6_POS 24 /**< PIN6 Position */
+#define MXC_F_GPIO_RST_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN6_POS)) /**< PIN6 Mask */
+#define MXC_F_GPIO_RST_MODE_PIN7_POS 28 /**< PIN7 Position */
+#define MXC_F_GPIO_RST_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN7_POS)) /**< PIN7 Mask */
+/**@} end of group GPIO_FREE */
+/**
+ * @defgroup GPIO_FREE_Register GPIO_FREE
+ * @ingroup gpio_registers
+ * @brief Field Positions and Bit Masks for the GPIO_FREE register.
+ * @{
+ */
+#define MXC_F_GPIO_FREE_PIN0_POS 0 /**< PIN0 Position */
+#define MXC_F_GPIO_FREE_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN0_POS)) /**< PIN0 Mask */
+#define MXC_F_GPIO_FREE_PIN1_POS 1 /**< PIN1 Position */
+#define MXC_F_GPIO_FREE_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN1_POS)) /**< PIN1 Mask */
+#define MXC_F_GPIO_FREE_PIN2_POS 2 /**< PIN2 Position */
+#define MXC_F_GPIO_FREE_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN2_POS)) /**< PIN2 Mask */
+#define MXC_F_GPIO_FREE_PIN3_POS 3 /**< PIN3 Position */
+#define MXC_F_GPIO_FREE_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN3_POS)) /**< PIN3 Mask */
+#define MXC_F_GPIO_FREE_PIN4_POS 4 /**< PIN4 Position */
+#define MXC_F_GPIO_FREE_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN4_POS)) /**< PIN4 Mask */
+#define MXC_F_GPIO_FREE_PIN5_POS 5 /**< PIN5 Position */
+#define MXC_F_GPIO_FREE_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN5_POS)) /**< PIN5 Mask */
+#define MXC_F_GPIO_FREE_PIN6_POS 6 /**< PIN6 Position */
+#define MXC_F_GPIO_FREE_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN6_POS)) /**< PIN6 Mask */
+#define MXC_F_GPIO_FREE_PIN7_POS 7 /**< PIN7 Position */
+#define MXC_F_GPIO_FREE_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN7_POS)) /**< PIN7 Mask */
+/**@} end of group GPIO_FREE */
+/**
+ * @defgroup GPIO_OUT_MODE_Register GPIO_OUT_MODE
+ * @ingroup gpio_registers
+ * @brief Field Positions and Bit Masks for the GPIO_OUT_MODE register.
+ * @{
+ */
+#define MXC_F_GPIO_OUT_MODE_PIN0_POS 0 /**< PIN0 Position */
+#define MXC_F_GPIO_OUT_MODE_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN0_POS)) /**< PIN0 Mask */
+#define MXC_F_GPIO_OUT_MODE_PIN1_POS 4 /**< PIN1 Position */
+#define MXC_F_GPIO_OUT_MODE_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN1_POS)) /**< PIN1 Mask */
+#define MXC_F_GPIO_OUT_MODE_PIN2_POS 8 /**< PIN2 Position */
+#define MXC_F_GPIO_OUT_MODE_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN2_POS)) /**< PIN2 Mask */
+#define MXC_F_GPIO_OUT_MODE_PIN3_POS 12 /**< PIN3 Position */
+#define MXC_F_GPIO_OUT_MODE_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN3_POS)) /**< PIN3 Mask */
+#define MXC_F_GPIO_OUT_MODE_PIN4_POS 16 /**< PIN4 Position */
+#define MXC_F_GPIO_OUT_MODE_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN4_POS)) /**< PIN4 Mask */
+#define MXC_F_GPIO_OUT_MODE_PIN5_POS 20 /**< PIN5 Position */
+#define MXC_F_GPIO_OUT_MODE_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN5_POS)) /**< PIN5 Mask */
+#define MXC_F_GPIO_OUT_MODE_PIN6_POS 24 /**< PIN6 Position */
+#define MXC_F_GPIO_OUT_MODE_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN6_POS)) /**< PIN6 Mask */
+#define MXC_F_GPIO_OUT_MODE_PIN7_POS 28 /**< PIN7 Position */
+#define MXC_F_GPIO_OUT_MODE_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN7_POS)) /**< PIN7 Mask */
+/**@} end of group GPIO_OUT_MODE */
+/**
+ * @defgroup GPIO_OUT_VAL_Register GPIO_OUT_VAL
+ * @ingroup gpio_registers
+ * @brief Field Positions and Bit Masks for the GPIO_OUT_VAL register.
+ * @{
+ */
+#define MXC_F_GPIO_OUT_VAL_PIN0_POS 0 /**< PIN0 Position */
+#define MXC_F_GPIO_OUT_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN0_POS)) /**< PIN0 Mask */
+#define MXC_F_GPIO_OUT_VAL_PIN1_POS 1 /**< PIN1 Position */
+#define MXC_F_GPIO_OUT_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN1_POS)) /**< PIN1 Mask */
+#define MXC_F_GPIO_OUT_VAL_PIN2_POS 2 /**< PIN2 Position */
+#define MXC_F_GPIO_OUT_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN2_POS)) /**< PIN2 Mask */
+#define MXC_F_GPIO_OUT_VAL_PIN3_POS 3 /**< PIN3 Position */
+#define MXC_F_GPIO_OUT_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN3_POS)) /**< PIN3 Mask */
+#define MXC_F_GPIO_OUT_VAL_PIN4_POS 4 /**< PIN4 Position */
+#define MXC_F_GPIO_OUT_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN4_POS)) /**< PIN4 Mask */
+#define MXC_F_GPIO_OUT_VAL_PIN5_POS 5 /**< PIN5 Position */
+#define MXC_F_GPIO_OUT_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN5_POS)) /**< PIN5 Mask */
+#define MXC_F_GPIO_OUT_VAL_PIN6_POS 6 /**< PIN6 Position */
+#define MXC_F_GPIO_OUT_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN6_POS)) /**< PIN6 Mask */
+#define MXC_F_GPIO_OUT_VAL_PIN7_POS 7 /**< PIN7 Position */
+#define MXC_F_GPIO_OUT_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN7_POS)) /**< PIN7 Mask */
+/**@} end of group GPIO_OUT_VAL */
+/**
+ * @defgroup GPIO_FUNC_SEL_Register GPIO_FUNC_SEL
+ * @ingroup gpio_registers
+ * @brief Field Positions and Bit Masks for the GPIO_FUNC_SEL register.
+ * @{
+ */
+#define MXC_F_GPIO_FUNC_SEL_PIN0_POS 0 /**< PIN0 Position */
+#define MXC_F_GPIO_FUNC_SEL_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN0_POS)) /**< PIN0 Mask */
+#define MXC_F_GPIO_FUNC_SEL_PIN1_POS 4 /**< PIN1 Position */
+#define MXC_F_GPIO_FUNC_SEL_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN1_POS)) /**< PIN1 Mask */
+#define MXC_F_GPIO_FUNC_SEL_PIN2_POS 8 /**< PIN2 Position */
+#define MXC_F_GPIO_FUNC_SEL_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN2_POS)) /**< PIN2 Mask */
+#define MXC_F_GPIO_FUNC_SEL_PIN3_POS 12 /**< PIN3 Position */
+#define MXC_F_GPIO_FUNC_SEL_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN3_POS)) /**< PIN3 Mask */
+#define MXC_F_GPIO_FUNC_SEL_PIN4_POS 16 /**< PIN4 Position */
+#define MXC_F_GPIO_FUNC_SEL_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN4_POS)) /**< PIN4 Mask */
+#define MXC_F_GPIO_FUNC_SEL_PIN5_POS 20 /**< PIN5 Position */
+#define MXC_F_GPIO_FUNC_SEL_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN5_POS)) /**< PIN5 Mask */
+#define MXC_F_GPIO_FUNC_SEL_PIN6_POS 24 /**< PIN6 Position */
+#define MXC_F_GPIO_FUNC_SEL_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN6_POS)) /**< PIN6 Mask */
+#define MXC_F_GPIO_FUNC_SEL_PIN7_POS 28 /**< PIN7 Position */
+#define MXC_F_GPIO_FUNC_SEL_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN7_POS)) /**< PIN7 Mask */
+/**@} end of group GPIO_FUNC_SEL */
+/**
+ * @defgroup GPIO_IN_MODE_Register GPIO_IN_MODE
+ * @ingroup gpio_registers
+ * @brief Field Positions and Bit Masks for the GPIO_IN_MODE register.
+ * @{
+ */
+#define MXC_F_GPIO_IN_MODE_PIN0_POS 0 /**< PIN0 Position */
+#define MXC_F_GPIO_IN_MODE_PIN0 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN0_POS)) /**< PIN0 Mask */
+#define MXC_F_GPIO_IN_MODE_PIN1_POS 4 /**< PIN1 Position */
+#define MXC_F_GPIO_IN_MODE_PIN1 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN1_POS)) /**< PIN1 Mask */
+#define MXC_F_GPIO_IN_MODE_PIN2_POS 8 /**< PIN2 Position */
+#define MXC_F_GPIO_IN_MODE_PIN2 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN2_POS)) /**< PIN2 Mask */
+#define MXC_F_GPIO_IN_MODE_PIN3_POS 12 /**< PIN3 Position */
+#define MXC_F_GPIO_IN_MODE_PIN3 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN3_POS)) /**< PIN3 Mask */
+#define MXC_F_GPIO_IN_MODE_PIN4_POS 16 /**< PIN4 Position */
+#define MXC_F_GPIO_IN_MODE_PIN4 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN4_POS)) /**< PIN4 Mask */
+#define MXC_F_GPIO_IN_MODE_PIN5_POS 20 /**< PIN5 Position */
+#define MXC_F_GPIO_IN_MODE_PIN5 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN5_POS)) /**< PIN5 Mask */
+#define MXC_F_GPIO_IN_MODE_PIN6_POS 24 /**< PIN6 Position */
+#define MXC_F_GPIO_IN_MODE_PIN6 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN6_POS)) /**< PIN6 Mask */
+#define MXC_F_GPIO_IN_MODE_PIN7_POS 28 /**< PIN7 Position */
+#define MXC_F_GPIO_IN_MODE_PIN7 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN7_POS)) /**< PIN7 Mask */
+/**@} end of group GPIO_IN_MODE */
+/**
+ * @defgroup GPIO_IN_VAL_Register GPIO_IN_VAL
+ * @ingroup gpio_registers
+ * @brief Field Positions and Bit Masks for the GPIO_IN_VAL register.
+ * @{
+ */
+#define MXC_F_GPIO_IN_VAL_PIN0_POS 0 /**< PIN0 Position */
+#define MXC_F_GPIO_IN_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN0_POS)) /**< PIN0 Mask */
+#define MXC_F_GPIO_IN_VAL_PIN1_POS 1 /**< PIN1 Position */
+#define MXC_F_GPIO_IN_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN1_POS)) /**< PIN1 Mask */
+#define MXC_F_GPIO_IN_VAL_PIN2_POS 2 /**< PIN2 Position */
+#define MXC_F_GPIO_IN_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN2_POS)) /**< PIN2 Mask */
+#define MXC_F_GPIO_IN_VAL_PIN3_POS 3 /**< PIN3 Position */
+#define MXC_F_GPIO_IN_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN3_POS)) /**< PIN3 Mask */
+#define MXC_F_GPIO_IN_VAL_PIN4_POS 4 /**< PIN4 Position */
+#define MXC_F_GPIO_IN_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN4_POS)) /**< PIN4 Mask */
+#define MXC_F_GPIO_IN_VAL_PIN5_POS 5 /**< PIN5 Position */
+#define MXC_F_GPIO_IN_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN5_POS)) /**< PIN5 Mask */
+#define MXC_F_GPIO_IN_VAL_PIN6_POS 6 /**< PIN6 Position */
+#define MXC_F_GPIO_IN_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN6_POS)) /**< PIN6 Mask */
+#define MXC_F_GPIO_IN_VAL_PIN7_POS 7 /**< PIN7 Position */
+#define MXC_F_GPIO_IN_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN7_POS)) /**< PIN7 Mask */
+/**@} end of group GPIO_IN_VAL */
+/**
+ * @defgroup GPIO_INT_MODE_Register GPIO_INT_MODE
+ * @ingroup gpio_registers
+ * @brief Field Positions and Bit Masks for the GPIO_INT_MODE register.
+ * @{
+ */
+#define MXC_F_GPIO_INT_MODE_PIN0_POS 0 /**< PIN0 Position */
+#define MXC_F_GPIO_INT_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN0_POS)) /**< PIN0 Mask */
+#define MXC_F_GPIO_INT_MODE_PIN1_POS 4 /**< PIN1 Position */
+#define MXC_F_GPIO_INT_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN1_POS)) /**< PIN1 Mask */
+#define MXC_F_GPIO_INT_MODE_PIN2_POS 8 /**< PIN2 Position */
+#define MXC_F_GPIO_INT_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN2_POS)) /**< PIN2 Mask */
+#define MXC_F_GPIO_INT_MODE_PIN3_POS 12 /**< PIN3 Position */
+#define MXC_F_GPIO_INT_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN3_POS)) /**< PIN3 Mask */
+#define MXC_F_GPIO_INT_MODE_PIN4_POS 16 /**< PIN4 Position */
+#define MXC_F_GPIO_INT_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN4_POS)) /**< PIN4 Mask */
+#define MXC_F_GPIO_INT_MODE_PIN5_POS 20 /**< PIN5 Position */
+#define MXC_F_GPIO_INT_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN5_POS)) /**< PIN5 Mask */
+#define MXC_F_GPIO_INT_MODE_PIN6_POS 24 /**< PIN6 Position */
+#define MXC_F_GPIO_INT_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN6_POS)) /**< PIN6 Mask */
+#define MXC_F_GPIO_INT_MODE_PIN7_POS 28 /**< PIN7 Position */
+#define MXC_F_GPIO_INT_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN7_POS)) /**< PIN7 Mask */
+/**@} end of group GPIO_INT_MODE */
+/**
+ * @defgroup GPIO_INTFL_Register GPIO_INTFL
+ * @ingroup gpio_registers
+ * @brief Field Positions and Bit Masks for the GPIO_INTFL register.
+ * @{
+ */
+#define MXC_F_GPIO_INTFL_PIN0_POS 0 /**< PIN0 Position */
+#define MXC_F_GPIO_INTFL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN0_POS)) /**< PIN0 Mask */
+#define MXC_F_GPIO_INTFL_PIN1_POS 1 /**< PIN1 Position */
+#define MXC_F_GPIO_INTFL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN1_POS)) /**< PIN1 Mask */
+#define MXC_F_GPIO_INTFL_PIN2_POS 2 /**< PIN2 Position */
+#define MXC_F_GPIO_INTFL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN2_POS)) /**< PIN2 Mask */
+#define MXC_F_GPIO_INTFL_PIN3_POS 3 /**< PIN3 Position */
+#define MXC_F_GPIO_INTFL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN3_POS)) /**< PIN3 Mask */
+#define MXC_F_GPIO_INTFL_PIN4_POS 4 /**< PIN4 Position */
+#define MXC_F_GPIO_INTFL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN4_POS)) /**< PIN4 Mask */
+#define MXC_F_GPIO_INTFL_PIN5_POS 5 /**< PIN5 Position */
+#define MXC_F_GPIO_INTFL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN5_POS)) /**< PIN5 Mask */
+#define MXC_F_GPIO_INTFL_PIN6_POS 6 /**< PIN6 Position */
+#define MXC_F_GPIO_INTFL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN6_POS)) /**< PIN6 Mask */
+#define MXC_F_GPIO_INTFL_PIN7_POS 7 /**< PIN7 Position */
+#define MXC_F_GPIO_INTFL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN7_POS)) /**< PIN7 Mask */
+/**@} end of group GPIO_INTFL */
+/**
+ * @defgroup GPIO_INTEN_Register GPIO_INTEN
+ * @ingroup gpio_registers
+ * @brief Field Positions and Bit Masks for the GPIO_INTEN register.
+ * @{
+ */
+#define MXC_F_GPIO_INTEN_PIN0_POS 0 /**< PIN0 Position */
+#define MXC_F_GPIO_INTEN_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN0_POS)) /**< PIN0 Mask */
+#define MXC_F_GPIO_INTEN_PIN1_POS 1 /**< PIN1 Position */
+#define MXC_F_GPIO_INTEN_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN1_POS)) /**< PIN1 Mask */
+#define MXC_F_GPIO_INTEN_PIN2_POS 2 /**< PIN2 Position */
+#define MXC_F_GPIO_INTEN_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN2_POS)) /**< PIN2 Mask */
+#define MXC_F_GPIO_INTEN_PIN3_POS 3 /**< PIN3 Position */
+#define MXC_F_GPIO_INTEN_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN3_POS)) /**< PIN3 Mask */
+#define MXC_F_GPIO_INTEN_PIN4_POS 4 /**< PIN4 Position */
+#define MXC_F_GPIO_INTEN_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN4_POS)) /**< PIN4 Mask */
+#define MXC_F_GPIO_INTEN_PIN5_POS 5 /**< PIN5 Position */
+#define MXC_F_GPIO_INTEN_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN5_POS)) /**< PIN5 Mask */
+#define MXC_F_GPIO_INTEN_PIN6_POS 6 /**< PIN6 Position */
+#define MXC_F_GPIO_INTEN_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN6_POS)) /**< PIN6 Mask */
+#define MXC_F_GPIO_INTEN_PIN7_POS 7 /**< PIN7 Position */
+#define MXC_F_GPIO_INTEN_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN7_POS)) /**< PIN7 Mask */
+/**@} end group GPIO_INTEN_Register */
+
+
+/*
+ Field values and shifted values for module GPIO.
+*/
+/**
+ * @defgroup GPIO_RST_MODE_Values Reset Mode Values
+ * @ingroup GPIO_RST_MODE_Register
+ * @brief Mode Values for setting the GPIO_RST_MODE Field for different pad modes
+ * @{
+ */
+#define MXC_V_GPIO_RST_MODE_DRIVE_0 ((uint32_t)(0x00000000UL)) /**< DRIVE_0 */
+#define MXC_V_GPIO_RST_MODE_WEAK_PULLDOWN ((uint32_t)(0x00000001UL)) /**< WEAK_PULLDOWN */
+#define MXC_V_GPIO_RST_MODE_WEAK_PULLUP ((uint32_t)(0x00000002UL)) /**< WEAK_PULLUP */
+#define MXC_V_GPIO_RST_MODE_DRIVE_1 ((uint32_t)(0x00000003UL)) /**< DRIVE_1 */
+#define MXC_V_GPIO_RST_MODE_HIGH_Z ((uint32_t)(0x00000004UL)) /**< HIGH_Z */
+/**@}*/
+
+/**
+ * @defgroup GPIO_FREE_Values Reset Mode Values
+ * @ingroup GPIO_FREE_Register
+ * @brief Mode Values for setting the GPIO_FREE to Available or Unavailable
+ * @{
+ */
+#define MXC_V_GPIO_FREE_NOT_AVAILABLE ((uint32_t)(0x00000000UL)) /**< GPIO Pin is Unavailable */
+#define MXC_V_GPIO_FREE_AVAILABLE ((uint32_t)(0x00000001UL)) /**< GPIO Pin is Available */
+/**@}*/
+
+/**
+ * @defgroup GPIO_OUT_MODE_Values Output Mode Values
+ * @ingroup GPIO_FREE_Register
+ * @brief GPIO_OUT_MODE values for setting the different port pin output modes
+ * @{
+ */
+#define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP ((uint32_t)(0x00000000UL)) /**< See \MXIM_Device User Guide for details: HIGH_Z_WEAK_PULLUP */
+#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN ((uint32_t)(0x00000001UL)) /**< See \MXIM_Device User Guide for details: OPEN_DRAIN */
+#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(0x00000002UL)) /**< See \MXIM_Device User Guide for details: OPEN_DRAIN_WEAK_PULLUP */
+#define MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z ((uint32_t)(0x00000004UL)) /**< See \MXIM_Device User Guide for details: NORMAL_HIGH_Z */
+#define MXC_V_GPIO_OUT_MODE_NORMAL ((uint32_t)(0x00000005UL)) /**< See \MXIM_Device User Guide for details: NORMAL */
+#define MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z ((uint32_t)(0x00000006UL)) /**< See \MXIM_Device User Guide for details: SLOW_HIGH_Z */
+#define MXC_V_GPIO_OUT_MODE_SLOW_DRIVE ((uint32_t)(0x00000007UL)) /**< See \MXIM_Device User Guide for details: SLOW_DRIVE */
+#define MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z ((uint32_t)(0x00000008UL)) /**< See \MXIM_Device User Guide for details: FAST_HIGH_Z */
+#define MXC_V_GPIO_OUT_MODE_FAST_DRIVE ((uint32_t)(0x00000009UL)) /**< See \MXIM_Device User Guide for details: FAST_DRIVE */
+#define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN ((uint32_t)(0x0000000AUL)) /**< See \MXIM_Device User Guide for details: HIGH_Z_WEAK_PULLDOWN */
+#define MXC_V_GPIO_OUT_MODE_OPEN_SOURCE ((uint32_t)(0x0000000BUL)) /**< See \MXIM_Device User Guide for details: OPEN_SOURCE */
+#define MXC_V_GPIO_OUT_MODE_OPEN_SOURCE_WEAK_PULLDOWN ((uint32_t)(0x0000000CUL)) /**< See \MXIM_Device User Guide for details: OPEN_SOURCE_WEAK_PULLDOWN */
+#define MXC_V_GPIO_OUT_MODE_HIGH_Z_INPUT_DISABLED ((uint32_t)(0x0000000FUL)) /**< See \MXIM_Device User Guide for details: HIGH_Z_INPUT_DISABLED */
+/**@}*/
+
+/**
+ * @defgroup GPIO_FUNC_SEL_Values Function type selection values
+ * @ingroup GPIO_FUNC_SEL_Register
+ * @brief Function selection values for the GPIO_FUNC_SEL Register.
+ * @{
+ */
+#define MXC_V_GPIO_FUNC_SEL_MODE_GPIO ((uint32_t)(0x00000000UL)) /**< Standard GPIO Mode */
+#define MXC_V_GPIO_FUNC_SEL_MODE_PT ((uint32_t)(0x00000001UL)) /**< Pulse Train Mode */
+#define MXC_V_GPIO_FUNC_SEL_MODE_TMR ((uint32_t)(0x00000002UL)) /**< Timer Mode */
+/**@}*/
+
+/**
+ * @defgroup GPIO_IN_MODE_Values Input mode selection values
+ * @ingroup GPIO_IN_MODE_Register
+ * @brief Input mode values for selecting the GPIO input mode.
+ * @{
+ */
+#define MXC_V_GPIO_IN_MODE_NORMAL ((uint32_t)(0x00000000UL)) /**< Normal Input Mode */
+#define MXC_V_GPIO_IN_MODE_INVERTED ((uint32_t)(0x00000001UL)) /**< Inverted Input Mode */
+#define MXC_V_GPIO_IN_MODE_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) /**< Always reads 0 */
+#define MXC_V_GPIO_IN_MODE_ALWAYS_ONE ((uint32_t)(0x00000003UL)) /**< Always reads 1 */
+/**@}*/
+
+/**
+ * @defgroup GPIO_INT_MODE_Values Interrupt mode selection values
+ * @ingroup GPIO_INT_MODE_Register
+ * @brief Values for setting the interrupt mode of a GPIO input pin.
+ * @{
+ */
+#define MXC_V_GPIO_INT_MODE_DISABLE ((uint32_t)(0x00000000UL)) /**< Disable Interrupt for a given port pin */
+#define MXC_V_GPIO_INT_MODE_FALLING_EDGE ((uint32_t)(0x00000001UL)) /**< Interrupt on falling edge */
+#define MXC_V_GPIO_INT_MODE_RISING_EDGE ((uint32_t)(0x00000002UL)) /**< Interrupt on rising edge */
+#define MXC_V_GPIO_INT_MODE_ANY_EDGE ((uint32_t)(0x00000003UL)) /**< Interrupt on rising or falling edge */
+#define MXC_V_GPIO_INT_MODE_LOW_LVL ((uint32_t)(0x00000004UL)) /**< Interrupt on Low Level */
+#define MXC_V_GPIO_INT_MODE_HIGH_LVL ((uint32_t)(0x00000005UL)) /**< Interrupt on High Level */
+/**@}*/
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_GPIO_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/icc_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32625/icc_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,143 @@
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_ICC_REGS_H_
+#define _MXC_ICC_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/// @cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+///@endcond
+
+/* **** Definitions **** */
+
+/**
+ * @defgroup icc_registers Registers
+ * @brief Registers, Bit Masks and Bit Positions for the ICC.
+ * @ingroup icc
+ * @{
+ */
+
+/**
+ * Structure type to access the ICC Registers.
+ */
+typedef struct {
+ __IO uint32_t id; /**< <tt>\b 0x0000: </tt> ICC_ID Register \warning INTERNAL USE ONLY, DO NOT MODIFY */
+ __IO uint32_t mem_cfg; /**< <tt>\b 0x0004: </tt> ICC_MEM_CFG Register */
+ __R uint32_t rsv008[62]; /**< <tt>\b 0x0008-0x00FC: </tt> RESERVED */
+ __IO uint32_t ctrl_stat; /**< <tt>\b 0x0100: </tt> ICC_CTRL_STAT Register */
+ __R uint32_t rsv104[383]; /**< <tt>\b 0x0104-0x06FC: </tt> RESERVED */
+ __IO uint32_t invdt_all; /**< <tt>\b 0x0700: </tt> ICC_INVDT_ALL Register */
+} mxc_icc_regs_t;
+/**@} end of group icc_registers*/
+
+/*
+ Register offsets for module ICC.
+*/
+/**
+ * @defgroup ICC_Register_Offsets Register Offsets
+ * @ingroup icc_registers
+ * @brief Instruction Cache Controller Register Offsets from the ICC Base Address.
+ * @{
+ */
+#define MXC_R_ICC_OFFS_ID ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: <tt>\b 0x0000</tt> */
+#define MXC_R_ICC_OFFS_MEM_CFG ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: <tt>\b 0x0004</tt> */
+#define MXC_R_ICC_OFFS_CTRL_STAT ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: <tt>\b 0x0100</tt> */
+#define MXC_R_ICC_OFFS_INVDT_ALL ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: <tt>\b 0x0700</tt> */
+/**@} end of group icc_registers */
+
+/*
+ Field positions and masks for module ICC.
+*/
+/**
+ * @defgroup ICC_ID_Register ICC_ID
+ * @brief Field Positions and Bit Masks for the ICC_ID register
+ * @ingroup icc_registers
+ * @{
+ */
+#define MXC_F_ICC_ID_RTL_VERSION_POS 0 /**< RTL_VERSION Position */
+#define MXC_F_ICC_ID_RTL_VERSION ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_RTL_VERSION_POS)) /**< RTL_VERSION Mask */
+#define MXC_F_ICC_ID_PART_NUM_POS 6 /**< PART_NUM Position */
+#define MXC_F_ICC_ID_PART_NUM ((uint32_t)(0x0000000FUL << MXC_F_ICC_ID_PART_NUM_POS)) /**< PART_NUM Mask */
+#define MXC_F_ICC_ID_CACHE_ID_POS 10 /**< CACHE_ID Position */
+#define MXC_F_ICC_ID_CACHE_ID ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_CACHE_ID_POS)) /**< CACHE_ID Mask */
+/**@} end of group ICC_ID_register */
+/**
+ * @defgroup ICC_MEM_CFG_Register ICC_MEM_CFG
+ * @brief Field Positions and Bit Masks for the ICC_MEM_CFG register
+ * @ingroup icc_registers
+ * @{
+ */
+#define MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS 0 /**< CACHE_SIZE Position */
+#define MXC_F_ICC_MEM_CFG_CACHE_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS)) /**< CACHE_SIZE Mask */
+#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS 16 /**< MAIN_MEMORY_SIZE Position */
+#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS)) /**< MAIN_MEMORY_SIZE Mask */
+/**@} end of group ICC_MEM_CFG_register */
+/**
+ * @defgroup ICC_CTRL_STAT_Register ICC_CTRL_STAT
+ * @brief Field Positions and Bit Masks for the ICC_CTRL_STAT register
+ * @ingroup icc_registers
+ * @{
+ */
+#define MXC_F_ICC_CTRL_STAT_ENABLE_POS 0 /**< ENABLE Position */
+#define MXC_F_ICC_CTRL_STAT_ENABLE ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_ENABLE_POS)) /**< ENABLE Mask */
+#define MXC_F_ICC_CTRL_STAT_READY_POS 16 /**< READY Position */
+#define MXC_F_ICC_CTRL_STAT_READY ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_READY_POS)) /**< READY Mask */
+/**@} end of group ICC_CTRL_STAT_register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_ICC_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/ioman_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32625/ioman_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,796 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_IOMAN_REGS_H_
+#define _MXC_IOMAN_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+
+
+/*
+ Bitfield structs for registers in this module
+*/
+
+typedef struct {
+ uint32_t wud_req_p0 : 8;
+ uint32_t wud_req_p1 : 8;
+ uint32_t wud_req_p2 : 8;
+ uint32_t wud_req_p3 : 8;
+} mxc_ioman_wud_req0_t;
+
+typedef struct {
+ uint32_t wud_req_p4 : 8;
+ uint32_t : 24;
+} mxc_ioman_wud_req1_t;
+
+typedef struct {
+ uint32_t wud_ack_p0 : 8;
+ uint32_t wud_ack_p1 : 8;
+ uint32_t wud_ack_p2 : 8;
+ uint32_t wud_ack_p3 : 8;
+} mxc_ioman_wud_ack0_t;
+
+typedef struct {
+ uint32_t wud_ack_p4 : 8;
+ uint32_t : 24;
+} mxc_ioman_wud_ack1_t;
+
+typedef struct {
+ uint32_t ali_req_p0 : 8;
+ uint32_t ali_req_p1 : 8;
+ uint32_t ali_req_p2 : 8;
+ uint32_t ali_req_p3 : 8;
+} mxc_ioman_ali_req0_t;
+
+typedef struct {
+ uint32_t ali_req_p4 : 8;
+ uint32_t : 24;
+} mxc_ioman_ali_req1_t;
+
+typedef struct {
+ uint32_t ali_ack_p0 : 8;
+ uint32_t ali_ack_p1 : 8;
+ uint32_t ali_ack_p2 : 8;
+ uint32_t ali_ack_p3 : 8;
+} mxc_ioman_ali_ack0_t;
+
+typedef struct {
+ uint32_t ali_ack_p4 : 8;
+ uint32_t : 24;
+} mxc_ioman_ali_ack1_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t core_io_req : 1;
+ uint32_t : 3;
+ uint32_t ss0_io_req : 1;
+ uint32_t ss1_io_req : 1;
+ uint32_t ss2_io_req : 1;
+ uint32_t : 1;
+ uint32_t quad_io_req : 1;
+ uint32_t : 3;
+ uint32_t fast_mode : 1;
+ uint32_t : 15;
+} mxc_ioman_spix_req_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t core_io_ack : 1;
+ uint32_t : 3;
+ uint32_t ss0_io_ack : 1;
+ uint32_t ss1_io_ack : 1;
+ uint32_t ss2_io_ack : 1;
+ uint32_t : 1;
+ uint32_t quad_io_ack : 1;
+ uint32_t : 3;
+ uint32_t fast_mode : 1;
+ uint32_t : 15;
+} mxc_ioman_spix_ack_t;
+
+typedef struct {
+ uint32_t io_map : 1;
+ uint32_t cts_map : 1;
+ uint32_t rts_map : 1;
+ uint32_t : 1;
+ uint32_t io_req : 1;
+ uint32_t cts_io_req : 1;
+ uint32_t rts_io_req : 1;
+ uint32_t : 25;
+} mxc_ioman_uart0_req_t;
+
+typedef struct {
+ uint32_t io_map : 1;
+ uint32_t cts_map : 1;
+ uint32_t rts_map : 1;
+ uint32_t : 1;
+ uint32_t io_ack : 1;
+ uint32_t cts_io_ack : 1;
+ uint32_t rts_io_ack : 1;
+ uint32_t : 25;
+} mxc_ioman_uart0_ack_t;
+
+typedef struct {
+ uint32_t io_map : 1;
+ uint32_t cts_map : 1;
+ uint32_t rts_map : 1;
+ uint32_t : 1;
+ uint32_t io_req : 1;
+ uint32_t cts_io_req : 1;
+ uint32_t rts_io_req : 1;
+ uint32_t : 25;
+} mxc_ioman_uart1_req_t;
+
+typedef struct {
+ uint32_t io_map : 1;
+ uint32_t cts_map : 1;
+ uint32_t rts_map : 1;
+ uint32_t : 1;
+ uint32_t io_ack : 1;
+ uint32_t cts_io_ack : 1;
+ uint32_t rts_io_ack : 1;
+ uint32_t : 25;
+} mxc_ioman_uart1_ack_t;
+
+typedef struct {
+ uint32_t io_map : 1;
+ uint32_t cts_map : 1;
+ uint32_t rts_map : 1;
+ uint32_t : 1;
+ uint32_t io_req : 1;
+ uint32_t cts_io_req : 1;
+ uint32_t rts_io_req : 1;
+ uint32_t : 25;
+} mxc_ioman_uart2_req_t;
+
+typedef struct {
+ uint32_t io_map : 1;
+ uint32_t cts_map : 1;
+ uint32_t rts_map : 1;
+ uint32_t : 1;
+ uint32_t io_ack : 1;
+ uint32_t cts_io_ack : 1;
+ uint32_t rts_io_ack : 1;
+ uint32_t : 25;
+} mxc_ioman_uart2_ack_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t mapping_req : 1;
+ uint32_t scl_push_pull : 1;
+ uint32_t : 26;
+} mxc_ioman_i2cm0_req_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t mapping_ack : 1;
+ uint32_t : 27;
+} mxc_ioman_i2cm0_ack_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t mapping_req : 1;
+ uint32_t scl_push_pull : 1;
+ uint32_t : 26;
+} mxc_ioman_i2cm1_req_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t mapping_ack : 1;
+ uint32_t : 27;
+} mxc_ioman_i2cm1_ack_t;
+
+typedef struct {
+ uint32_t io_sel : 2;
+ uint32_t : 2;
+ uint32_t mapping_req : 1;
+ uint32_t : 27;
+} mxc_ioman_i2cs_req_t;
+
+typedef struct {
+ uint32_t io_sel : 2;
+ uint32_t : 2;
+ uint32_t mapping_ack : 1;
+ uint32_t : 27;
+} mxc_ioman_i2cs_ack_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t core_io_req : 1;
+ uint32_t : 3;
+ uint32_t ss0_io_req : 1;
+ uint32_t ss1_io_req : 1;
+ uint32_t ss2_io_req : 1;
+ uint32_t ss3_io_req : 1;
+ uint32_t ss4_io_req : 1;
+ uint32_t : 7;
+ uint32_t quad_io_req : 1;
+ uint32_t : 3;
+ uint32_t fast_mode : 1;
+ uint32_t : 7;
+} mxc_ioman_spim0_req_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t core_io_ack : 1;
+ uint32_t : 3;
+ uint32_t ss0_io_ack : 1;
+ uint32_t ss1_io_ack : 1;
+ uint32_t ss2_io_ack : 1;
+ uint32_t ss3_io_ack : 1;
+ uint32_t ss4_io_ack : 1;
+ uint32_t : 7;
+ uint32_t quad_io_ack : 1;
+ uint32_t : 3;
+ uint32_t fast_mode : 1;
+ uint32_t : 7;
+} mxc_ioman_spim0_ack_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t core_io_req : 1;
+ uint32_t : 3;
+ uint32_t ss0_io_req : 1;
+ uint32_t ss1_io_req : 1;
+ uint32_t ss2_io_req : 1;
+ uint32_t : 9;
+ uint32_t quad_io_req : 1;
+ uint32_t : 3;
+ uint32_t fast_mode : 1;
+ uint32_t : 7;
+} mxc_ioman_spim1_req_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t core_io_ack : 1;
+ uint32_t : 3;
+ uint32_t ss0_io_ack : 1;
+ uint32_t ss1_io_ack : 1;
+ uint32_t ss2_io_ack : 1;
+ uint32_t : 9;
+ uint32_t quad_io_ack : 1;
+ uint32_t : 3;
+ uint32_t fast_mode : 1;
+ uint32_t : 7;
+} mxc_ioman_spim1_ack_t;
+
+typedef struct {
+ uint32_t mapping_req : 1;
+ uint32_t : 3;
+ uint32_t core_io_req : 1;
+ uint32_t : 3;
+ uint32_t ss0_io_req : 1;
+ uint32_t ss1_io_req : 1;
+ uint32_t ss2_io_req : 1;
+ uint32_t : 5;
+ uint32_t sr0_io_req : 1;
+ uint32_t sr1_io_req : 1;
+ uint32_t : 2;
+ uint32_t quad_io_req : 1;
+ uint32_t : 3;
+ uint32_t fast_mode : 1;
+ uint32_t : 7;
+} mxc_ioman_spim2_req_t;
+
+typedef struct {
+ uint32_t mapping_ack : 1;
+ uint32_t : 3;
+ uint32_t core_io_ack : 1;
+ uint32_t : 3;
+ uint32_t ss0_io_ack : 1;
+ uint32_t ss1_io_ack : 1;
+ uint32_t ss2_io_ack : 1;
+ uint32_t : 5;
+ uint32_t sr0_io_ack : 1;
+ uint32_t sr1_io_ack : 1;
+ uint32_t : 2;
+ uint32_t quad_io_ack : 1;
+ uint32_t : 3;
+ uint32_t fast_mode : 1;
+ uint32_t : 7;
+} mxc_ioman_spim2_ack_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t mapping_req : 1;
+ uint32_t epu_io_req : 1;
+ uint32_t : 26;
+} mxc_ioman_owm_req_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t mapping_ack : 1;
+ uint32_t epu_io_ack : 1;
+ uint32_t : 26;
+} mxc_ioman_owm_ack_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t core_io_req : 1;
+ uint32_t : 3;
+ uint32_t quad_io_req : 1;
+ uint32_t : 3;
+ uint32_t fast_mode : 1;
+ uint32_t : 19;
+} mxc_ioman_spis_req_t;
+
+typedef struct {
+ uint32_t : 4;
+ uint32_t core_io_ack : 1;
+ uint32_t : 3;
+ uint32_t quad_io_ack : 1;
+ uint32_t : 3;
+ uint32_t fast_mode : 1;
+ uint32_t : 19;
+} mxc_ioman_spis_ack_t;
+
+typedef struct {
+ uint32_t slow_mode : 1;
+ uint32_t alt_rcvr_mode : 1;
+ uint32_t : 30;
+} mxc_ioman_pad_mode_t;
+
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __IO uint32_t wud_req0; /* 0x0000 Wakeup Detect Mode Request Register 0 (P0/P1/P2/P3) */
+ __IO uint32_t wud_req1; /* 0x0004 Wakeup Detect Mode Request Register 1 (P4) */
+ __IO uint32_t wud_ack0; /* 0x0008 Wakeup Detect Mode Acknowledge Register 0 (P0/P1/P2/P3) */
+ __IO uint32_t wud_ack1; /* 0x000C Wakeup Detect Mode Acknowledge Register 1 (P4) */
+ __IO uint32_t ali_req0; /* 0x0010 Analog Input Request Register 0 (P0/P1/P2/P3) */
+ __IO uint32_t ali_req1; /* 0x0014 Analog Input Request Register 1 (P4) */
+ __IO uint32_t ali_ack0; /* 0x0018 Analog Input Acknowledge Register 0 (P0/P1/P2/P3) */
+ __IO uint32_t ali_ack1; /* 0x001C Analog Input Acknowledge Register 1 (P4) */
+ __IO uint32_t ali_connect0; /* 0x0020 Analog I/O Connection Control Register 0 */
+ __IO uint32_t ali_connect1; /* 0x0024 Analog I/O Connection Control Register 1 */
+ __IO uint32_t spix_req; /* 0x0028 SPIX I/O Mode Request */
+ __IO uint32_t spix_ack; /* 0x002C SPIX I/O Mode Acknowledge */
+ __IO uint32_t uart0_req; /* 0x0030 UART0 I/O Mode Request */
+ __IO uint32_t uart0_ack; /* 0x0034 UART0 I/O Mode Acknowledge */
+ __IO uint32_t uart1_req; /* 0x0038 UART1 I/O Mode Request */
+ __IO uint32_t uart1_ack; /* 0x003C UART1 I/O Mode Acknowledge */
+ __IO uint32_t uart2_req; /* 0x0040 UART2 I/O Mode Request */
+ __IO uint32_t uart2_ack; /* 0x0044 UART2 I/O Mode Acknowledge */
+ __R uint32_t rsv048[2]; /* 0x0048-0x004C */
+ __IO uint32_t i2cm0_req; /* 0x0050 I2C Master 0 I/O Request */
+ __IO uint32_t i2cm0_ack; /* 0x0054 I2C Master 0 I/O Acknowledge */
+ __IO uint32_t i2cm1_req; /* 0x0058 I2C Master 1 I/O Request */
+ __IO uint32_t i2cm1_ack; /* 0x005C I2C Master 1 I/O Acknowledge */
+ __R uint32_t rsv060[2]; /* 0x0060-0x0064 */
+ __IO uint32_t i2cs_req; /* 0x0068 I2C Slave I/O Request */
+ __IO uint32_t i2cs_ack; /* 0x006C I2C Slave I/O Acknowledge */
+ __IO uint32_t spim0_req; /* 0x0070 SPI Master 0 I/O Mode Request */
+ __IO uint32_t spim0_ack; /* 0x0074 SPI Master 0 I/O Mode Acknowledge */
+ __IO uint32_t spim1_req; /* 0x0078 SPI Master 1 I/O Mode Request */
+ __IO uint32_t spim1_ack; /* 0x007C SPI Master 1 I/O Mode Acknowledge */
+ __IO uint32_t spim2_req; /* 0x0080 SPI Master 2 I/O Mode Request */
+ __IO uint32_t spim2_ack; /* 0x0084 SPI Master 2 I/O Mode Acknowledge */
+ __R uint32_t rsv088[2]; /* 0x0088-0x008C */
+ __IO uint32_t owm_req; /* 0x0090 1-Wire Master I/O Mode Request */
+ __IO uint32_t owm_ack; /* 0x0094 1-Wire Master I/O Mode Acknowledge */
+ __IO uint32_t spis_req; /* 0x0098 SPI Slave I/O Mode Request */
+ __IO uint32_t spis_ack; /* 0x009C SPI Slave I/O Mode Acknowledge */
+ __R uint32_t rsv0A0[24]; /* 0x00A0-0x00FC */
+ __IO uint32_t use_vddioh_0; /* 0x0100 Enable VDDIOH Register 0 */
+ __IO uint32_t use_vddioh_1; /* 0x0104 Enable VDDIOH Register 1 */
+ __R uint32_t rsv108[2]; /* 0x0108-0x010C */
+ __IO uint32_t pad_mode; /* 0x0110 Pad Mode Control Register */
+} mxc_ioman_regs_t;
+
+
+/*
+ Register offsets for module IOMAN.
+*/
+
+#define MXC_R_IOMAN_OFFS_WUD_REQ0 ((uint32_t)0x00000000UL)
+#define MXC_R_IOMAN_OFFS_WUD_REQ1 ((uint32_t)0x00000004UL)
+#define MXC_R_IOMAN_OFFS_WUD_ACK0 ((uint32_t)0x00000008UL)
+#define MXC_R_IOMAN_OFFS_WUD_ACK1 ((uint32_t)0x0000000CUL)
+#define MXC_R_IOMAN_OFFS_ALI_REQ0 ((uint32_t)0x00000010UL)
+#define MXC_R_IOMAN_OFFS_ALI_REQ1 ((uint32_t)0x00000014UL)
+#define MXC_R_IOMAN_OFFS_ALI_ACK0 ((uint32_t)0x00000018UL)
+#define MXC_R_IOMAN_OFFS_ALI_ACK1 ((uint32_t)0x0000001CUL)
+#define MXC_R_IOMAN_OFFS_ALI_CONNECT0 ((uint32_t)0x00000020UL)
+#define MXC_R_IOMAN_OFFS_ALI_CONNECT1 ((uint32_t)0x00000024UL)
+#define MXC_R_IOMAN_OFFS_SPIX_REQ ((uint32_t)0x00000028UL)
+#define MXC_R_IOMAN_OFFS_SPIX_ACK ((uint32_t)0x0000002CUL)
+#define MXC_R_IOMAN_OFFS_UART0_REQ ((uint32_t)0x00000030UL)
+#define MXC_R_IOMAN_OFFS_UART0_ACK ((uint32_t)0x00000034UL)
+#define MXC_R_IOMAN_OFFS_UART1_REQ ((uint32_t)0x00000038UL)
+#define MXC_R_IOMAN_OFFS_UART1_ACK ((uint32_t)0x0000003CUL)
+#define MXC_R_IOMAN_OFFS_UART2_REQ ((uint32_t)0x00000040UL)
+#define MXC_R_IOMAN_OFFS_UART2_ACK ((uint32_t)0x00000044UL)
+#define MXC_R_IOMAN_OFFS_I2CM0_REQ ((uint32_t)0x00000050UL)
+#define MXC_R_IOMAN_OFFS_I2CM0_ACK ((uint32_t)0x00000054UL)
+#define MXC_R_IOMAN_OFFS_I2CM1_REQ ((uint32_t)0x00000058UL)
+#define MXC_R_IOMAN_OFFS_I2CM1_ACK ((uint32_t)0x0000005CUL)
+#define MXC_R_IOMAN_OFFS_I2CS_REQ ((uint32_t)0x00000068UL)
+#define MXC_R_IOMAN_OFFS_I2CS_ACK ((uint32_t)0x0000006CUL)
+#define MXC_R_IOMAN_OFFS_SPIM0_REQ ((uint32_t)0x00000070UL)
+#define MXC_R_IOMAN_OFFS_SPIM0_ACK ((uint32_t)0x00000074UL)
+#define MXC_R_IOMAN_OFFS_SPIM1_REQ ((uint32_t)0x00000078UL)
+#define MXC_R_IOMAN_OFFS_SPIM1_ACK ((uint32_t)0x0000007CUL)
+#define MXC_R_IOMAN_OFFS_SPIM2_REQ ((uint32_t)0x00000080UL)
+#define MXC_R_IOMAN_OFFS_SPIM2_ACK ((uint32_t)0x00000084UL)
+#define MXC_R_IOMAN_OFFS_OWM_REQ ((uint32_t)0x00000090UL)
+#define MXC_R_IOMAN_OFFS_OWM_ACK ((uint32_t)0x00000094UL)
+#define MXC_R_IOMAN_OFFS_SPIS_REQ ((uint32_t)0x00000098UL)
+#define MXC_R_IOMAN_OFFS_SPIS_ACK ((uint32_t)0x0000009CUL)
+#define MXC_R_IOMAN_OFFS_USE_VDDIOH_0 ((uint32_t)0x00000100UL)
+#define MXC_R_IOMAN_OFFS_USE_VDDIOH_1 ((uint32_t)0x00000104UL)
+#define MXC_R_IOMAN_OFFS_PAD_MODE ((uint32_t)0x00000110UL)
+
+
+/*
+ Field positions and masks for module IOMAN.
+*/
+
+#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0_POS 0
+#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0_POS))
+#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1_POS 8
+#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1_POS))
+#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2_POS 16
+#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2_POS))
+#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3_POS 24
+#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3_POS))
+
+#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4_POS 0
+#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4_POS))
+
+#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0_POS 0
+#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0_POS))
+#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1_POS 8
+#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1_POS))
+#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2_POS 16
+#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2_POS))
+#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3_POS 24
+#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3_POS))
+
+#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4_POS 0
+#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4_POS))
+
+#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0_POS 0
+#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0_POS))
+#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1_POS 8
+#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1_POS))
+#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2_POS 16
+#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2_POS))
+#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3_POS 24
+#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3_POS))
+
+#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4_POS 0
+#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4_POS))
+
+#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0_POS 0
+#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0_POS))
+#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1_POS 8
+#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1_POS))
+#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2_POS 16
+#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2_POS))
+#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3_POS 24
+#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3_POS))
+
+#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4_POS 0
+#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4_POS))
+
+#define MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ_POS 4
+#define MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ_POS 8
+#define MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ_POS 9
+#define MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ_POS 10
+#define MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ_POS 12
+#define MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIX_REQ_FAST_MODE_POS 16
+#define MXC_F_IOMAN_SPIX_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK_POS 4
+#define MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK_POS 8
+#define MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK_POS 9
+#define MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK_POS 10
+#define MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK_POS 12
+#define MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIX_ACK_FAST_MODE_POS 16
+#define MXC_F_IOMAN_SPIX_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_UART0_REQ_IO_MAP_POS 0
+#define MXC_F_IOMAN_UART0_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_MAP_POS))
+#define MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS 1
+#define MXC_F_IOMAN_UART0_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS))
+#define MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS 2
+#define MXC_F_IOMAN_UART0_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS))
+#define MXC_F_IOMAN_UART0_REQ_IO_REQ_POS 4
+#define MXC_F_IOMAN_UART0_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_REQ_POS))
+#define MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ_POS 5
+#define MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ_POS))
+#define MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ_POS 6
+#define MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ_POS))
+
+#define MXC_F_IOMAN_UART0_ACK_IO_MAP_POS 0
+#define MXC_F_IOMAN_UART0_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_MAP_POS))
+#define MXC_F_IOMAN_UART0_ACK_CTS_MAP_POS 1
+#define MXC_F_IOMAN_UART0_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_MAP_POS))
+#define MXC_F_IOMAN_UART0_ACK_RTS_MAP_POS 2
+#define MXC_F_IOMAN_UART0_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_MAP_POS))
+#define MXC_F_IOMAN_UART0_ACK_IO_ACK_POS 4
+#define MXC_F_IOMAN_UART0_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_ACK_POS))
+#define MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK_POS 5
+#define MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK_POS))
+#define MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK_POS 6
+#define MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK_POS))
+
+#define MXC_F_IOMAN_UART1_REQ_IO_MAP_POS 0
+#define MXC_F_IOMAN_UART1_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_IO_MAP_POS))
+#define MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS 1
+#define MXC_F_IOMAN_UART1_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS))
+#define MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS 2
+#define MXC_F_IOMAN_UART1_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS))
+#define MXC_F_IOMAN_UART1_REQ_IO_REQ_POS 4
+#define MXC_F_IOMAN_UART1_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_IO_REQ_POS))
+#define MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ_POS 5
+#define MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ_POS))
+#define MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ_POS 6
+#define MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ_POS))
+
+#define MXC_F_IOMAN_UART1_ACK_IO_MAP_POS 0
+#define MXC_F_IOMAN_UART1_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_IO_MAP_POS))
+#define MXC_F_IOMAN_UART1_ACK_CTS_MAP_POS 1
+#define MXC_F_IOMAN_UART1_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_CTS_MAP_POS))
+#define MXC_F_IOMAN_UART1_ACK_RTS_MAP_POS 2
+#define MXC_F_IOMAN_UART1_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_RTS_MAP_POS))
+#define MXC_F_IOMAN_UART1_ACK_IO_ACK_POS 4
+#define MXC_F_IOMAN_UART1_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_IO_ACK_POS))
+#define MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK_POS 5
+#define MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK_POS))
+#define MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK_POS 6
+#define MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK_POS))
+
+#define MXC_F_IOMAN_UART2_REQ_IO_MAP_POS 0
+#define MXC_F_IOMAN_UART2_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_IO_MAP_POS))
+#define MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS 1
+#define MXC_F_IOMAN_UART2_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS))
+#define MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS 2
+#define MXC_F_IOMAN_UART2_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS))
+#define MXC_F_IOMAN_UART2_REQ_IO_REQ_POS 4
+#define MXC_F_IOMAN_UART2_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_IO_REQ_POS))
+#define MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ_POS 5
+#define MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ_POS))
+#define MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ_POS 6
+#define MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ_POS))
+
+#define MXC_F_IOMAN_UART2_ACK_IO_MAP_POS 0
+#define MXC_F_IOMAN_UART2_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_IO_MAP_POS))
+#define MXC_F_IOMAN_UART2_ACK_CTS_MAP_POS 1
+#define MXC_F_IOMAN_UART2_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_CTS_MAP_POS))
+#define MXC_F_IOMAN_UART2_ACK_RTS_MAP_POS 2
+#define MXC_F_IOMAN_UART2_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_RTS_MAP_POS))
+#define MXC_F_IOMAN_UART2_ACK_IO_ACK_POS 4
+#define MXC_F_IOMAN_UART2_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_IO_ACK_POS))
+#define MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK_POS 5
+#define MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK_POS))
+#define MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK_POS 6
+#define MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK_POS))
+
+#define MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ_POS 4
+#define MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ_POS))
+#define MXC_F_IOMAN_I2CM0_REQ_SCL_PUSH_PULL_POS 5
+#define MXC_F_IOMAN_I2CM0_REQ_SCL_PUSH_PULL ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_REQ_SCL_PUSH_PULL_POS))
+
+#define MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK_POS 4
+#define MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK_POS))
+
+#define MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ_POS 4
+#define MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ_POS))
+#define MXC_F_IOMAN_I2CM1_REQ_SCL_PUSH_PULL_POS 5
+#define MXC_F_IOMAN_I2CM1_REQ_SCL_PUSH_PULL ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM1_REQ_SCL_PUSH_PULL_POS))
+
+#define MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK_POS 4
+#define MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK_POS))
+
+#define MXC_F_IOMAN_I2CS_REQ_IO_SEL_POS 0
+#define MXC_F_IOMAN_I2CS_REQ_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CS_REQ_IO_SEL_POS))
+#define MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ_POS 4
+#define MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ_POS))
+
+#define MXC_F_IOMAN_I2CS_ACK_IO_SEL_POS 0
+#define MXC_F_IOMAN_I2CS_ACK_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CS_ACK_IO_SEL_POS))
+#define MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK_POS 4
+#define MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK_POS))
+
+#define MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ_POS 4
+#define MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ_POS 8
+#define MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ_POS 9
+#define MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ_POS 10
+#define MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ_POS 11
+#define MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ_POS 12
+#define MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ_POS 20
+#define MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM0_REQ_FAST_MODE_POS 24
+#define MXC_F_IOMAN_SPIM0_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK_POS 4
+#define MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK_POS 8
+#define MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK_POS 9
+#define MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK_POS 10
+#define MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK_POS 11
+#define MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK_POS 12
+#define MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK_POS 20
+#define MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM0_ACK_FAST_MODE_POS 24
+#define MXC_F_IOMAN_SPIM0_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ_POS 4
+#define MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ_POS 8
+#define MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ_POS 9
+#define MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ_POS 10
+#define MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ_POS 20
+#define MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM1_REQ_FAST_MODE_POS 24
+#define MXC_F_IOMAN_SPIM1_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK_POS 4
+#define MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK_POS 8
+#define MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK_POS 9
+#define MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK_POS 10
+#define MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK_POS 20
+#define MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM1_ACK_FAST_MODE_POS 24
+#define MXC_F_IOMAN_SPIM1_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ_POS 0
+#define MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ_POS 4
+#define MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ_POS 8
+#define MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ_POS 9
+#define MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ_POS 10
+#define MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ_POS 16
+#define MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ_POS 17
+#define MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_REQ_FAST_MODE_POS 24
+#define MXC_F_IOMAN_SPIM2_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK_POS 0
+#define MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK_POS))
+#define MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK_POS 4
+#define MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK_POS 8
+#define MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK_POS 9
+#define MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK_POS 10
+#define MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM2_ACK_SR0_IO_REQ_POS 16
+#define MXC_F_IOMAN_SPIM2_ACK_SR0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SR0_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_ACK_SR1_IO_REQ_POS 17
+#define MXC_F_IOMAN_SPIM2_ACK_SR1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SR1_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_ACK_FAST_MODE_POS 24
+#define MXC_F_IOMAN_SPIM2_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_OWM_REQ_MAPPING_REQ_POS 4
+#define MXC_F_IOMAN_OWM_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_REQ_MAPPING_REQ_POS))
+#define MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ_POS 5
+#define MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ_POS))
+
+#define MXC_F_IOMAN_OWM_ACK_MAPPING_ACK_POS 4
+#define MXC_F_IOMAN_OWM_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_ACK_MAPPING_ACK_POS))
+#define MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK_POS 5
+#define MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK_POS))
+
+#define MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ_POS 4
+#define MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ_POS 8
+#define MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIS_REQ_FAST_MODE_POS 12
+#define MXC_F_IOMAN_SPIS_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK_POS 4
+#define MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK_POS 8
+#define MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIS_ACK_FAST_MODE_POS 12
+#define MXC_F_IOMAN_SPIS_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_PAD_MODE_SLOW_MODE_POS 0
+#define MXC_F_IOMAN_PAD_MODE_SLOW_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PAD_MODE_SLOW_MODE_POS))
+#define MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE_POS 1
+#define MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE_POS))
+
+#define MXC_V_IOMAN_MAP_A ((uint32_t)0x00000000UL)
+#define MXC_V_IOMAN_MAP_B ((uint32_t)0x00000001UL)
+#define MXC_V_IOMAN_MAP_C ((uint32_t)0x00000002UL)
+#define MXC_V_IOMAN_MAP_D ((uint32_t)0x00000003UL)
+#define MXC_V_IOMAN_MAP_E ((uint32_t)0x00000004UL)
+#define MXC_V_IOMAN_MAP_F ((uint32_t)0x00000005UL)
+#define MXC_V_IOMAN_MAP_G ((uint32_t)0x00000006UL)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_IOMAN_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/max32625.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32625/max32625.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,796 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#ifndef _MAX32625_H_
+#define _MAX32625_H_
+
+#include <stdint.h>
+
+#ifndef FALSE
+#define FALSE (0)
+#endif
+
+#ifndef TRUE
+#define TRUE (1)
+#endif
+
+/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
+#if defined ( __GNUC__ )
+#define __weak __attribute__((weak))
+
+#elif defined ( __CC_ARM)
+
+#define inline __inline
+#pragma anon_unions
+
+#endif
+
+typedef enum {
+ NonMaskableInt_IRQn = -14,
+ HardFault_IRQn = -13,
+ MemoryManagement_IRQn = -12,
+ BusFault_IRQn = -11,
+ UsageFault_IRQn = -10,
+ SVCall_IRQn = -5,
+ DebugMonitor_IRQn = -4,
+ PendSV_IRQn = -2,
+ SysTick_IRQn = -1,
+
+ /* Device-specific interrupt sources (external to ARM core) */
+ /* table entry number */
+ /* |||| */
+ /* |||| table offset address */
+ /* vvvv vvvvvv */
+
+ CLKMAN_IRQn = 0, /* 0x10 0x0040,CLKMAN */
+ PWRMAN_IRQn = 1, /* 0x11 0x0044 PWRMAN */
+ FLC_IRQn = 2, /* 0x12 0x0048 Flash Controller */
+ RTC0_IRQn = 3, /* 0x13 0x004C RTC Counter match with Compare 0 */
+ RTC1_IRQn = 4, /* 0x14 0x0050 RTC Counter match with Compare 1 */
+ RTC2_IRQn = 5, /* 0x15 0x0054 RTC Prescaler interval compare match */
+ RTC3_IRQn = 6, /* 0x16 0x0058 RTC Overflow */
+ PMU_IRQn = 7, /* 0x17 0x005C Peripheral Management Unit (PMU/DMA) */
+ USB_IRQn = 8, /* 0x18 0x0060 USB */
+ AES_IRQn = 9, /* 0x19 0x0064 AES */
+ MAA_IRQn = 10, /* 0x1A 0x0068 MAA */
+ WDT0_IRQn = 11, /* 0x1B 0x006C Watchdog 0 timeout */
+ WDT0_P_IRQn = 12, /* 0x1C 0x0070 Watchdog 0 pre-window (fed too early) */
+ WDT1_IRQn = 13, /* 0x1D 0x0074 Watchdog 1 timeout */
+ WDT1_P_IRQn = 14, /* 0x1E 0x0078 Watchdog 1 pre-window (fed too early) */
+ GPIO_P0_IRQn = 15, /* 0x1F 0x007C GPIO Port 0 */
+ GPIO_P1_IRQn = 16, /* 0x20 0x0080 GPIO Port 1 */
+ GPIO_P2_IRQn = 17, /* 0x21 0x0084 GPIO Port 2 */
+ GPIO_P3_IRQn = 18, /* 0x22 0x0088 GPIO Port 3 */
+ GPIO_P4_IRQn = 19, /* 0x23 0x008C GPIO Port 4 */
+ // Reserved = 20, /* 0x24 0x0090 Reserved */
+ // Reserved = 21, /* 0x25 0x0094 Reserved */
+ TMR0_0_IRQn = 22, /* 0x26 0x0098 Timer 0 (32-bit, 16-bit #0) */
+ TMR0_1_IRQn = 23, /* 0x27 0x009C Timer 0 (16-bit #1) */
+ TMR1_0_IRQn = 24, /* 0x28 0x00A0 Timer 1 (32-bit, 16-bit #0) */
+ TMR1_1_IRQn = 25, /* 0x29 0x00A4 Timer 1 (16-bit #1) */
+ TMR2_0_IRQn = 26, /* 0x2A 0x00A8 Timer 2 (32-bit, 16-bit #0) */
+ TMR2_1_IRQn = 27, /* 0x2B 0x00AC Timer 2 (16-bit #1) */
+ TMR3_0_IRQn = 28, /* 0x2C 0x00B0 Timer 3 (32-bit, 16-bit #0) */
+ TMR3_1_IRQn = 29, /* 0x2D 0x00B4 Timer 3 (16-bit #1) */
+ TMR4_0_IRQn = 30, /* 0x2E 0x00B8 Timer 4 (32-bit, 16-bit #0) */
+ TMR4_1_IRQn = 31, /* 0x2F 0x00BC Timer 4 (16-bit #1) */
+ TMR5_0_IRQn = 32, /* 0x30 0x00C0 Timer 5 (32-bit, 16-bit #0) */
+ TMR5_1_IRQn = 33, /* 0x31 0x00C4 Timer 5 (16-bit #1) */
+ UART0_IRQn = 34, /* 0x32 0x00C8 UART 0 */
+ UART1_IRQn = 35, /* 0x33 0x00CC UART 1 */
+ UART2_IRQn = 36, /* 0x34 0x00D0 UART 2 */
+ UART3_IRQn = 37, /* 0x35 0x00D4 UART 3 (Unused) */
+ PT_IRQn = 38, /* 0x36 0x00D8 Pulse Trains */
+ I2CM0_IRQn = 39, /* 0x37 0x00DC I2C Master 0 */
+ I2CM1_IRQn = 40, /* 0x38 0x00E0 I2C Master 1 */
+ I2CM2_IRQn = 41, /* 0x39 0x00E4 I2C Master 2 (Unused) */
+ I2CS_IRQn = 42, /* 0x3A 0x00E8 I2C Slave */
+ SPIM0_IRQn = 43, /* 0x3B 0x00EC SPI Master 0 */
+ SPIM1_IRQn = 44, /* 0x3C 0x00F0 SPI Master 1 */
+ SPIM2_IRQn = 45, /* 0x3D 0x00F4 SPI Master 2 */
+ SPIB_IRQn = 46, /* 0x3E 0x00F8 SPI Bridge (Unused) */
+ OWM_IRQn = 47, /* 0x3F 0x00FC 1-Wire Master */
+ AFE_IRQn = 48, /* 0x40 0x0100 Analog Front End, ADC */
+ SPIS_IRQn = 49, /* 0x41 0x0104 SPI Slave */
+ MXC_IRQ_EXT_COUNT,
+} IRQn_Type;
+
+#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
+
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+/* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */
+#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< FPU present or not */
+
+#include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */
+#include "system_max32625.h" /*!< System Header */
+
+
+/* ================================================================================ */
+/* ================== Device Specific Memory Section ================== */
+/* ================================================================================ */
+
+#define MXC_FLASH_MEM_BASE 0x00000000UL
+#define MXC_FLASH_PAGE_SIZE 0x00002000UL
+#define MXC_FLASH_FULL_MEM_SIZE 0x00080000UL
+#define MXC_SYS_MEM_BASE 0x20000000UL
+#define MXC_SRAM_FULL_MEM_SIZE 0x00028000UL
+#define MXC_EXT_FLASH_MEM_BASE 0x10000000UL
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+
+
+/*
+ Base addresses and configuration settings for all MAX32625 peripheral modules.
+*/
+
+
+/*******************************************************************************/
+/* System Manager Settings */
+
+#define MXC_BASE_SYSMAN ((uint32_t)0x40000000UL)
+#define MXC_SYSMAN ((mxc_sysman_regs_t *)MXC_BASE_SYSMAN)
+
+
+
+/*******************************************************************************/
+/* System Clock Manager */
+
+#define MXC_BASE_CLKMAN ((uint32_t)0x40000400UL)
+#define MXC_CLKMAN ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN)
+
+
+
+/*******************************************************************************/
+/* System Power Manager */
+
+#define MXC_BASE_PWRMAN ((uint32_t)0x40000800UL)
+#define MXC_PWRMAN ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN)
+
+
+
+/*******************************************************************************/
+/* Real Time Clock */
+
+#define MXC_BASE_RTCTMR ((uint32_t)0x40000A00UL)
+#define MXC_RTCTMR ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR)
+#define MXC_BASE_RTCCFG ((uint32_t)0x40000A70UL)
+#define MXC_RTCCFG ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG)
+
+#define MXC_RTCTMR_GET_IRQ(i) (IRQn_Type)((i) == 0 ? RTC0_IRQn : \
+ (i) == 1 ? RTC1_IRQn : \
+ (i) == 2 ? RTC2_IRQn : \
+ (i) == 3 ? RTC3_IRQn : 0)
+
+
+
+/*******************************************************************************/
+/* Power Sequencer */
+
+#define MXC_BASE_PWRSEQ ((uint32_t)0x40000A30UL)
+#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
+
+
+
+/*******************************************************************************/
+/* System I/O Manager */
+
+#define MXC_BASE_IOMAN ((uint32_t)0x40000C00UL)
+#define MXC_IOMAN ((mxc_ioman_regs_t *)MXC_BASE_IOMAN)
+
+
+
+/*******************************************************************************/
+/* Shadow Trim Registers */
+
+#define MXC_BASE_TRIM ((uint32_t)0x40001000UL)
+#define MXC_TRIM ((mxc_trim_regs_t *)MXC_BASE_TRIM)
+
+
+
+/*******************************************************************************/
+/* Flash Controller */
+
+#define MXC_BASE_FLC ((uint32_t)0x40002000UL)
+#define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC)
+
+#define MXC_FLC_PAGE_SIZE_SHIFT (13)
+#define MXC_FLC_PAGE_SIZE (1 << MXC_FLC_PAGE_SIZE_SHIFT)
+#define MXC_FLC_PAGE_ERASE_MSK ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT
+
+
+
+/*******************************************************************************/
+/* Instruction Cache */
+
+#define MXC_BASE_ICC ((uint32_t)0x40003000UL)
+#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC)
+
+
+
+/*******************************************************************************/
+/* SPI XIP Interface */
+
+#define MXC_BASE_SPIX ((uint32_t)0x40004000UL)
+#define MXC_SPIX ((mxc_spix_regs_t *)MXC_BASE_SPIX)
+
+
+
+/*******************************************************************************/
+/* Peripheral Management Unit */
+
+#define MXC_CFG_PMU_CHANNELS (6)
+
+#define MXC_BASE_PMU0 ((uint32_t)0x40005000UL)
+#define MXC_PMU0 ((mxc_pmu_regs_t *)MXC_BASE_PMU0)
+#define MXC_BASE_PMU1 ((uint32_t)0x40005020UL)
+#define MXC_PMU1 ((mxc_pmu_regs_t *)MXC_BASE_PMU1)
+#define MXC_BASE_PMU2 ((uint32_t)0x40005040UL)
+#define MXC_PMU2 ((mxc_pmu_regs_t *)MXC_BASE_PMU2)
+#define MXC_BASE_PMU3 ((uint32_t)0x40005060UL)
+#define MXC_PMU3 ((mxc_pmu_regs_t *)MXC_BASE_PMU3)
+#define MXC_BASE_PMU4 ((uint32_t)0x40005080UL)
+#define MXC_PMU4 ((mxc_pmu_regs_t *)MXC_BASE_PMU4)
+#define MXC_BASE_PMU5 ((uint32_t)0x400050A0UL)
+#define MXC_PMU5 ((mxc_pmu_regs_t *)MXC_BASE_PMU5)
+
+#define MXC_PMU_GET_BASE(i) ((i) == 0 ? MXC_BASE_PMU0 : \
+ (i) == 1 ? MXC_BASE_PMU1 : \
+ (i) == 2 ? MXC_BASE_PMU2 : \
+ (i) == 3 ? MXC_BASE_PMU3 : \
+ (i) == 4 ? MXC_BASE_PMU4 : \
+ (i) == 5 ? MXC_BASE_PMU5 : 0)
+
+#define MXC_PMU_GET_PMU(i) ((i) == 0 ? MXC_PMU0 : \
+ (i) == 1 ? MXC_PMU1 : \
+ (i) == 2 ? MXC_PMU2 : \
+ (i) == 3 ? MXC_PMU3 : \
+ (i) == 4 ? MXC_PMU4 : \
+ (i) == 5 ? MXC_PMU5 : 0)
+
+#define MXC_PMU_GET_IDX(p) ((p) == MXC_PMU0 ? 0 : \
+ (p) == MXC_PMU1 ? 1 : \
+ (p) == MXC_PMU2 ? 2 : \
+ (p) == MXC_PMU3 ? 3 : \
+ (p) == MXC_PMU4 ? 4 : \
+ (p) == MXC_PMU5 ? 5 : -1)
+
+/*******************************************************************************/
+/* USB Device Controller */
+
+#define MXC_BASE_USB ((uint32_t)0x40100000UL)
+#define MXC_USB ((mxc_usb_regs_t *)MXC_BASE_USB)
+
+#define MXC_USB_MAX_PACKET (64)
+#define MXC_USB_NUM_EP (8)
+
+
+
+/*******************************************************************************/
+/* CRC-16/CRC-32 Engine */
+
+#define MXC_BASE_CRC ((uint32_t)0x40006000UL)
+#define MXC_CRC ((mxc_crc_regs_t *)MXC_BASE_CRC)
+#define MXC_BASE_CRC_DATA ((uint32_t)0x40101000UL)
+#define MXC_CRC_DATA ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA)
+
+/*******************************************************************************/
+/* Pseudo-random number generator (PRNG) */
+
+#define MXC_BASE_PRNG ((uint32_t)0x40007000UL)
+#define MXC_PRNG ((mxc_prng_regs_t *)MXC_BASE_PRNG)
+
+/*******************************************************************************/
+/* AES Cryptographic Engine */
+
+#define MXC_BASE_AES ((uint32_t)0x40007400UL)
+#define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES)
+#define MXC_BASE_AES_MEM ((uint32_t)0x40102000UL)
+#define MXC_AES_MEM ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM)
+
+/*******************************************************************************/
+/* MAA Cryptographic Engine */
+
+#define MXC_BASE_MAA ((uint32_t)0x40007800UL)
+#define MXC_MAA ((mxc_maa_regs_t *)MXC_BASE_MAA)
+#define MXC_BASE_MAA_MEM ((uint32_t)0x40102800UL)
+#define MXC_MAA_MEM ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM)
+
+/*******************************************************************************/
+/* Trust Protection Unit (TPU) */
+
+#define MXC_BASE_TPU ((uint32_t)0x40007000UL)
+#define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU)
+#define MXC_BASE_TPU_TSR ((uint32_t)0x40007C00UL)
+#define MXC_TPU_TSR ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR)
+
+/*******************************************************************************/
+/* Watchdog Timers */
+
+#define MXC_CFG_WDT_INSTANCES (2)
+
+#define MXC_BASE_WDT0 ((uint32_t)0x40008000UL)
+#define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
+#define MXC_BASE_WDT1 ((uint32_t)0x40009000UL)
+#define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
+
+#define MXC_WDT_GET_IRQ(i) (IRQn_Type)((i) == 0 ? WDT0_IRQn : \
+ (i) == 1 ? WDT1_IRQn : 0)
+
+#define MXC_WDT_GET_IRQ_P(i) (IRQn_Type)((i) == 0 ? WDT0_P_IRQn : \
+ (i) == 1 ? WDT1_P_IRQn : 0)
+
+#define MXC_WDT_GET_BASE(i) ((i) == 0 ? MXC_BASE_WDT0 : \
+ (i) == 1 ? MXC_BASE_WDT1 : 0)
+
+#define MXC_WDT_GET_WDT(i) ((i) == 0 ? MXC_WDT0 : \
+ (i) == 1 ? MXC_WDT1 : 0)
+
+#define MXC_WDT_GET_IDX(i) ((i) == MXC_WDT0 ? 0: \
+ (i) == MXC_WDT1 ? 1: -1)
+
+
+/*******************************************************************************/
+/* Low-Level Watchdog Timer */
+
+#define MXC_BASE_WDT2 ((uint32_t)0x40007C60UL)
+#define MXC_WDT2 ((mxc_wdt2_regs_t *)MXC_BASE_WDT2)
+
+
+
+/*******************************************************************************/
+/* General Purpose I/O Ports (GPIO) */
+
+#define MXC_GPIO_NUM_PORTS (5)
+#define MXC_GPIO_MAX_PINS_PER_PORT (8)
+
+#define MXC_BASE_GPIO ((uint32_t)0x4000A000UL)
+#define MXC_GPIO ((mxc_gpio_regs_t *)MXC_BASE_GPIO)
+
+#define MXC_GPIO_GET_IRQ(i) (IRQn_Type)((i) == 0 ? GPIO_P0_IRQn : \
+ (i) == 1 ? GPIO_P1_IRQn : \
+ (i) == 2 ? GPIO_P2_IRQn : \
+ (i) == 3 ? GPIO_P3_IRQn : \
+ (i) == 4 ? GPIO_P4_IRQn : 0)
+
+
+
+/*******************************************************************************/
+/* 16/32 bit Timer/Counters */
+
+#define MXC_CFG_TMR_INSTANCES (6)
+
+#define MXC_BASE_TMR0 ((uint32_t)0x4000B000UL)
+#define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0)
+#define MXC_BASE_TMR1 ((uint32_t)0x4000C000UL)
+#define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1)
+#define MXC_BASE_TMR2 ((uint32_t)0x4000D000UL)
+#define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2)
+#define MXC_BASE_TMR3 ((uint32_t)0x4000E000UL)
+#define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3)
+#define MXC_BASE_TMR4 ((uint32_t)0x4000F000UL)
+#define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4)
+#define MXC_BASE_TMR5 ((uint32_t)0x40010000UL)
+#define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5)
+
+#define MXC_TMR_GET_IRQ_32(i) (IRQn_Type)((i) == 0 ? TMR0_0_IRQn : \
+ (i) == 1 ? TMR1_0_IRQn : \
+ (i) == 2 ? TMR2_0_IRQn : \
+ (i) == 3 ? TMR3_0_IRQn : \
+ (i) == 4 ? TMR4_0_IRQn : \
+ (i) == 5 ? TMR5_0_IRQn : 0)
+
+#define MXC_TMR_GET_IRQ_16(i) (IRQn_Type)((i) == 0 ? TMR0_0_IRQn : \
+ (i) == 1 ? TMR1_0_IRQn : \
+ (i) == 2 ? TMR2_0_IRQn : \
+ (i) == 3 ? TMR3_0_IRQn : \
+ (i) == 4 ? TMR4_0_IRQn : \
+ (i) == 5 ? TMR5_0_IRQn : \
+ (i) == 6 ? TMR0_1_IRQn : \
+ (i) == 7 ? TMR1_1_IRQn : \
+ (i) == 8 ? TMR2_1_IRQn : \
+ (i) == 9 ? TMR3_1_IRQn : \
+ (i) == 10 ? TMR4_1_IRQn : \
+ (i) == 11 ? TMR5_1_IRQn : 0)
+
+#define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
+ (i) == 1 ? MXC_BASE_TMR1 : \
+ (i) == 2 ? MXC_BASE_TMR2 : \
+ (i) == 3 ? MXC_BASE_TMR3 : \
+ (i) == 4 ? MXC_BASE_TMR4 : \
+ (i) == 5 ? MXC_BASE_TMR5 : 0)
+
+#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
+ (i) == 1 ? MXC_TMR1 : \
+ (i) == 2 ? MXC_TMR2 : \
+ (i) == 3 ? MXC_TMR3 : \
+ (i) == 4 ? MXC_TMR4 : \
+ (i) == 5 ? MXC_TMR5 : 0)
+
+#define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \
+ (p) == MXC_TMR1 ? 1 : \
+ (p) == MXC_TMR2 ? 2 : \
+ (p) == MXC_TMR3 ? 3 : \
+ (p) == MXC_TMR4 ? 4 : \
+ (p) == MXC_TMR5 ? 5 : -1)
+
+
+
+
+/*******************************************************************************/
+/* Pulse Train Generation */
+
+#define MXC_CFG_PT_INSTANCES (16)
+
+#define MXC_BASE_PTG ((uint32_t)0x40011000UL)
+#define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG)
+#define MXC_BASE_PT0 ((uint32_t)0x40011020UL)
+#define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0)
+#define MXC_BASE_PT1 ((uint32_t)0x40011040UL)
+#define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1)
+#define MXC_BASE_PT2 ((uint32_t)0x40011060UL)
+#define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2)
+#define MXC_BASE_PT3 ((uint32_t)0x40011080UL)
+#define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3)
+#define MXC_BASE_PT4 ((uint32_t)0x400110A0UL)
+#define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4)
+#define MXC_BASE_PT5 ((uint32_t)0x400110C0UL)
+#define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5)
+#define MXC_BASE_PT6 ((uint32_t)0x400110E0UL)
+#define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6)
+#define MXC_BASE_PT7 ((uint32_t)0x40011100UL)
+#define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7)
+#define MXC_BASE_PT8 ((uint32_t)0x40011120UL)
+#define MXC_PT8 ((mxc_pt_regs_t *)MXC_BASE_PT8)
+#define MXC_BASE_PT9 ((uint32_t)0x40011140UL)
+#define MXC_PT9 ((mxc_pt_regs_t *)MXC_BASE_PT9)
+#define MXC_BASE_PT10 ((uint32_t)0x40011160UL)
+#define MXC_PT10 ((mxc_pt_regs_t *)MXC_BASE_PT10)
+#define MXC_BASE_PT11 ((uint32_t)0x40011180UL)
+#define MXC_PT11 ((mxc_pt_regs_t *)MXC_BASE_PT11)
+#define MXC_BASE_PT12 ((uint32_t)0x400111A0UL)
+#define MXC_PT12 ((mxc_pt_regs_t *)MXC_BASE_PT12)
+#define MXC_BASE_PT13 ((uint32_t)0x400111C0UL)
+#define MXC_PT13 ((mxc_pt_regs_t *)MXC_BASE_PT13)
+#define MXC_BASE_PT14 ((uint32_t)0x400111E0UL)
+#define MXC_PT14 ((mxc_pt_regs_t *)MXC_BASE_PT14)
+#define MXC_BASE_PT15 ((uint32_t)0x40011200UL)
+#define MXC_PT15 ((mxc_pt_regs_t *)MXC_BASE_PT15)
+
+#define MXC_PT_GET_BASE(i) ((i) == 0 ? MXC_BASE_PT0 : \
+ (i) == 1 ? MXC_BASE_PT1 : \
+ (i) == 2 ? MXC_BASE_PT2 : \
+ (i) == 3 ? MXC_BASE_PT3 : \
+ (i) == 4 ? MXC_BASE_PT4 : \
+ (i) == 5 ? MXC_BASE_PT5 : \
+ (i) == 6 ? MXC_BASE_PT6 : \
+ (i) == 7 ? MXC_BASE_PT7 : \
+ (i) == 8 ? MXC_BASE_PT8 : \
+ (i) == 9 ? MXC_BASE_PT9 : \
+ (i) == 10 ? MXC_BASE_PT10 : \
+ (i) == 11 ? MXC_BASE_PT11 : \
+ (i) == 12 ? MXC_BASE_PT12 : \
+ (i) == 13 ? MXC_BASE_PT13 : \
+ (i) == 14 ? MXC_BASE_PT14 : \
+ (i) == 15 ? MXC_BASE_PT15 : 0)
+
+#define MXC_PT_GET_PT(i) ((i) == 0 ? MXC_PT0 : \
+ (i) == 1 ? MXC_PT1 : \
+ (i) == 2 ? MXC_PT2 : \
+ (i) == 3 ? MXC_PT3 : \
+ (i) == 4 ? MXC_PT4 : \
+ (i) == 5 ? MXC_PT5 : \
+ (i) == 6 ? MXC_PT6 : \
+ (i) == 7 ? MXC_PT7 : \
+ (i) == 8 ? MXC_PT8 : \
+ (i) == 9 ? MXC_PT9 : \
+ (i) == 10 ? MXC_PT10 : \
+ (i) == 11 ? MXC_PT11 : \
+ (i) == 12 ? MXC_PT12 : \
+ (i) == 13 ? MXC_PT13 : \
+ (i) == 14 ? MXC_PT14 : \
+ (i) == 15 ? MXC_PT15 : 0)
+
+#define MXC_PT_GET_IDX(p) ((p) == MXC_PT0 ? 0 : \
+ (p) == MXC_PT1 ? 1 : \
+ (p) == MXC_PT2 ? 2 : \
+ (p) == MXC_PT3 ? 3 : \
+ (p) == MXC_PT4 ? 4 : \
+ (p) == MXC_PT5 ? 5 : \
+ (p) == MXC_PT6 ? 6 : \
+ (p) == MXC_PT7 ? 7 : \
+ (p) == MXC_PT8 ? 8 : \
+ (p) == MXC_PT9 ? 9 : \
+ (p) == MXC_PT10 ? 10 : \
+ (p) == MXC_PT11 ? 11 : \
+ (p) == MXC_PT12 ? 12 : \
+ (p) == MXC_PT13 ? 13 : \
+ (p) == MXC_PT14 ? 14 : \
+ (p) == MXC_PT15 ? 15 : -1)
+
+
+
+/*******************************************************************************/
+/* UART / Serial Port Interface */
+
+#define MXC_CFG_UART_INSTANCES (3)
+#define MXC_UART_FIFO_DEPTH (32)
+
+#define MXC_BASE_UART0 ((uint32_t)0x40012000UL)
+#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
+#define MXC_BASE_UART1 ((uint32_t)0x40013000UL)
+#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1)
+#define MXC_BASE_UART2 ((uint32_t)0x40014000UL)
+#define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2)
+#define MXC_BASE_UART0_FIFO ((uint32_t)0x40103000UL)
+#define MXC_UART0_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART0_FIFO)
+#define MXC_BASE_UART1_FIFO ((uint32_t)0x40104000UL)
+#define MXC_UART1_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART1_FIFO)
+#define MXC_BASE_UART2_FIFO ((uint32_t)0x40105000UL)
+#define MXC_UART2_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART2_FIFO)
+
+#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \
+ (i) == 1 ? UART1_IRQn : \
+ (i) == 2 ? UART2_IRQn : 0)
+
+#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
+ (i) == 1 ? MXC_BASE_UART1 : \
+ (i) == 2 ? MXC_BASE_UART2 : 0)
+
+#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
+ (i) == 1 ? MXC_UART1 : \
+ (i) == 2 ? MXC_UART2 : 0)
+
+#define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \
+ (p) == MXC_UART1 ? 1 : \
+ (p) == MXC_UART2 ? 2 : -1)
+
+#define MXC_UART_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_UART0_FIFO : \
+ (i) == 1 ? MXC_BASE_UART1_FIFO : \
+ (i) == 2 ? MXC_BASE_UART2_FIFO : 0)
+
+#define MXC_UART_GET_FIFO(i) ((i) == 0 ? MXC_UART0_FIFO : \
+ (i) == 1 ? MXC_UART1_FIFO : \
+ (i) == 2 ? MXC_UART2_FIFO : 0)
+
+
+
+/*******************************************************************************/
+/* I2C Master Interface */
+
+#define MXC_CFG_I2CM_INSTANCES (2)
+#define MXC_I2CM_FIFO_DEPTH (8)
+
+#define MXC_BASE_I2CM0 ((uint32_t)0x40016000UL)
+#define MXC_I2CM0 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0)
+#define MXC_BASE_I2CM1 ((uint32_t)0x40017000UL)
+#define MXC_I2CM1 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1)
+#define MXC_BASE_I2CM0_FIFO ((uint32_t)0x40107000UL)
+#define MXC_I2CM0_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM0_FIFO)
+#define MXC_BASE_I2CM1_FIFO ((uint32_t)0x40108000UL)
+#define MXC_I2CM1_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM1_FIFO)
+
+#define MXC_I2CM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2CM0_IRQn : \
+ (i) == 1 ? I2CM1_IRQn : 0)
+
+#define MXC_I2CM_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CM0 : \
+ (i) == 1 ? MXC_BASE_I2CM1 : 0)
+
+#define MXC_I2CM_GET_I2CM(i) ((i) == 0 ? MXC_I2CM0 : \
+ (i) == 1 ? MXC_I2CM1 : 0)
+
+#define MXC_I2CM_GET_IDX(p) ((p) == MXC_I2CM0 ? 0 : \
+ (p) == MXC_I2CM1 ? 1 : -1)
+
+#define MXC_I2CM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_FIFO : \
+ (i) == 1 ? MXC_BASE_I2CM1_FIFO : 0)
+
+#define MXC_I2CM_GET_FIFO(i) ((i) == 0 ? MXC_I2CM0_FIFO : \
+ (i) == 1 ? MXC_I2CM1_FIFO : 0)
+
+
+
+/*******************************************************************************/
+/* I2C Slave Interface (Mailbox type) */
+
+#define MXC_CFG_I2CS_INSTANCES (1)
+#define MXC_CFG_I2CS_BUFFER_SIZE (32)
+
+#define MXC_BASE_I2CS ((uint32_t)0x40019000UL)
+#define MXC_I2CS ((mxc_i2cs_regs_t *)MXC_BASE_I2CS)
+
+#define MXC_I2CS_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2CS_IRQn : 0)
+
+#define MXC_I2CS_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CS : 0)
+
+#define MXC_I2CS_GET_I2CS(i) ((i) == 0 ? MXC_I2CS : 0)
+
+#define MXC_I2CS_GET_IDX(p) ((p) == MXC_I2CS ? 0 : -1)
+
+/*******************************************************************************/
+/* SPI Master Interface */
+
+#define MXC_CFG_SPIM_INSTANCES (3)
+#define MXC_CFG_SPIM_FIFO_DEPTH (16)
+
+#define MXC_BASE_SPIM0 ((uint32_t)0x4001A000UL)
+#define MXC_SPIM0 ((mxc_spim_regs_t *)MXC_BASE_SPIM0)
+#define MXC_BASE_SPIM1 ((uint32_t)0x4001B000UL)
+#define MXC_SPIM1 ((mxc_spim_regs_t *)MXC_BASE_SPIM1)
+#define MXC_BASE_SPIM2 ((uint32_t)0x4001C000UL)
+#define MXC_SPIM2 ((mxc_spim_regs_t *)MXC_BASE_SPIM2)
+#define MXC_BASE_SPIM0_FIFO ((uint32_t)0x4010A000UL)
+#define MXC_SPIM0_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM0_FIFO)
+#define MXC_BASE_SPIM1_FIFO ((uint32_t)0x4010B000UL)
+#define MXC_SPIM1_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM1_FIFO)
+#define MXC_BASE_SPIM2_FIFO ((uint32_t)0x4010C000UL)
+#define MXC_SPIM2_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM2_FIFO)
+
+#define MXC_SPIM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPIM0_IRQn : \
+ (i) == 1 ? SPIM1_IRQn : \
+ (i) == 2 ? SPIM2_IRQn : 0)
+
+#define MXC_SPIM_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPIM0 : \
+ (i) == 1 ? MXC_BASE_SPIM1 : \
+ (i) == 2 ? MXC_BASE_SPIM2 : 0)
+
+#define MXC_SPIM_GET_SPIM(i) ((i) == 0 ? MXC_SPIM0 : \
+ (i) == 1 ? MXC_SPIM1 : \
+ (i) == 2 ? MXC_SPIM2 : 0)
+
+#define MXC_SPIM_GET_IDX(p) ((p) == MXC_SPIM0 ? 0 : \
+ (p) == MXC_SPIM1 ? 1 : \
+ (p) == MXC_SPIM2 ? 2 : -1)
+
+#define MXC_SPIM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_SPIM0_FIFO : \
+ (i) == 1 ? MXC_BASE_SPIM1_FIFO : \
+ (i) == 2 ? MXC_BASE_SPIM2_FIFO : 0)
+
+#define MXC_SPIM_GET_SPIM_FIFO(i) ((i) == 0 ? MXC_SPIM0_FIFO : \
+ (i) == 1 ? MXC_SPIM1_FIFO : \
+ (i) == 2 ? MXC_SPIM2_FIFO : 0)
+
+
+
+/*******************************************************************************/
+/* 1-Wire Master Interface */
+
+#define MXC_CFG_OWM_INSTANCES (1)
+
+#define MXC_BASE_OWM ((uint32_t)0x4001E000UL)
+#define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM)
+
+#define MXC_OWM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? OWM_IRQn : 0)
+
+#define MXC_OWM_GET_BASE(i) ((i) == 0 ? MXC_BASE_OWM : 0)
+
+#define MXC_OWM_GET_OWM(i) ((i) == 0 ? MXC_OWM : 0)
+
+#define MXC_OWM_GET_IDX(p) ((p) == MXC_OWM ? 0 : -1)
+
+/*******************************************************************************/
+/* ADC / AFE */
+
+#define MXC_CFG_ADC_FIFO_DEPTH (32)
+
+#define MXC_BASE_ADC ((uint32_t)0x4001F000UL)
+#define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC)
+
+
+
+/*******************************************************************************/
+/* SPI Slave Interface */
+#define MXC_CFG_SPIS_INSTANCES (1)
+#define MXC_CFG_SPIS_FIFO_DEPTH (32)
+
+#define MXC_BASE_SPIS ((uint32_t)0x40020000UL)
+#define MXC_SPIS ((mxc_spis_regs_t *)MXC_BASE_SPIS)
+#define MXC_BASE_SPIS_FIFO ((uint32_t)0x4010E000UL)
+#define MXC_SPIS_FIFO ((mxc_spis_fifo_regs_t *)MXC_BASE_SPIS_FIFO)
+
+#define MXC_SPIS_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPIS_IRQn : 0)
+
+#define MXC_SPIS_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPIS : 0)
+
+#define MXC_SPIS_GET_SPIS(i) ((i) == 0 ? MXC_SPIS : 0)
+
+#define MXC_SPIS_GET_IDX(p) ((p) == MXC_SPIS ? 0 : -1)
+
+#define MXC_SPIS_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_SPIS_FIFO : 0)
+
+#define MXC_SPIS_GET_SPIS_FIFO(i) ((i) == 0 ? MXC_SPIS_FIFO :0)
+
+/*******************************************************************************/
+/* Bit Shifting */
+
+#define MXC_F_BIT_0 (1 << 0)
+#define MXC_F_BIT_1 (1 << 1)
+#define MXC_F_BIT_2 (1 << 2)
+#define MXC_F_BIT_3 (1 << 3)
+#define MXC_F_BIT_4 (1 << 4)
+#define MXC_F_BIT_5 (1 << 5)
+#define MXC_F_BIT_6 (1 << 6)
+#define MXC_F_BIT_7 (1 << 7)
+#define MXC_F_BIT_8 (1 << 8)
+#define MXC_F_BIT_9 (1 << 9)
+#define MXC_F_BIT_10 (1 << 10)
+#define MXC_F_BIT_11 (1 << 11)
+#define MXC_F_BIT_12 (1 << 12)
+#define MXC_F_BIT_13 (1 << 13)
+#define MXC_F_BIT_14 (1 << 14)
+#define MXC_F_BIT_15 (1 << 15)
+#define MXC_F_BIT_16 (1 << 16)
+#define MXC_F_BIT_17 (1 << 17)
+#define MXC_F_BIT_18 (1 << 18)
+#define MXC_F_BIT_19 (1 << 19)
+#define MXC_F_BIT_20 (1 << 20)
+#define MXC_F_BIT_21 (1 << 21)
+#define MXC_F_BIT_22 (1 << 22)
+#define MXC_F_BIT_23 (1 << 23)
+#define MXC_F_BIT_24 (1 << 24)
+#define MXC_F_BIT_25 (1 << 25)
+#define MXC_F_BIT_26 (1 << 26)
+#define MXC_F_BIT_27 (1 << 27)
+#define MXC_F_BIT_28 (1 << 28)
+#define MXC_F_BIT_29 (1 << 29)
+#define MXC_F_BIT_30 (1 << 30)
+#define MXC_F_BIT_31 (1 << 31)
+
+
+/*******************************************************************************/
+
+#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
+#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
+#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
+#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
+
+
+/*******************************************************************************/
+
+/* SCB CPACR Register Definitions */
+/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
+#define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */
+#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */
+#define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */
+#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */
+
+#endif /* _MAX32625_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/owm_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32625/owm_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,211 @@
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ **************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_OWM_REGS_H_
+#define _MXC_OWM_REGS_H_
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+///@cond
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+///@endcond
+
+
+/**
+ * @defgroup owm_registers Registers
+ * @brief Registers, Bit Masks and Bit Positions
+ * @ingroup owm
+ * @{
+ */
+/**
+ * Structure type for the 1-Wire Master module registers allowing direct 32-bit access to each register.
+ */
+typedef struct {
+ __IO uint32_t cfg; /**< <tt>\b 0x0000:</tt> OWM_CFG Register - 1-Wire Master Configuration */
+ __IO uint32_t clk_div_1us; /**< <tt>\b 0x0004:</tt> OWM_CLK_DIV_1US Register - 1-Wire Master Clock Divisor */
+ __IO uint32_t ctrl_stat; /**< <tt>\b 0x0008:</tt> OWM_CTRL_STAT Register - 1-Wire Master Control/Status */
+ __IO uint32_t data; /**< <tt>\b 0x000C:</tt> OWM_DATA Register - 1-Wire Master Data Buffer */
+ __IO uint32_t intfl; /**< <tt>\b 0x0010:</tt> OWM_INTFL Register - 1-Wire Master Interrupt Flags */
+ __IO uint32_t inten; /**< <tt>\b 0x0014:</tt> OWM_INTEN Register - 1-Wire Master Interrupt Enables */
+} mxc_owm_regs_t;
+/**@} end of group owm_registers */
+
+/**
+ * @defgroup OWM_Register_Offsets Register Offsets
+ * @ingroup owm_registers
+ * @brief 1-Wire Master register offsets from the 1-Wire Master Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_OWM_OFFS_CFG ((uint32_t)0x00000000UL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x0000:</tt>*/
+#define MXC_R_OWM_OFFS_CLK_DIV_1US ((uint32_t)0x00000004UL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x0004:</tt>*/
+#define MXC_R_OWM_OFFS_CTRL_STAT ((uint32_t)0x00000008UL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x0008:</tt>*/
+#define MXC_R_OWM_OFFS_DATA ((uint32_t)0x0000000CUL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x000C:</tt>*/
+#define MXC_R_OWM_OFFS_INTFL ((uint32_t)0x00000010UL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x0010:</tt>*/
+#define MXC_R_OWM_OFFS_INTEN ((uint32_t)0x00000014UL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x0014:</tt>*/
+/**@} end of group OWM_Register_Offsets */
+
+/*
+ Field positions and masks for module OWM.
+*/
+/**
+ * @defgroup owm_cfg OWM_CFG
+ * @ingroup owm_registers
+ * @brief Field Positions and Masks
+ */
+#define MXC_F_OWM_CFG_LONG_LINE_MODE_POS 0 /**< LONG_LINE_MODE Position */
+#define MXC_F_OWM_CFG_LONG_LINE_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_LONG_LINE_MODE_POS)) /**< LONG_LINE_MODE Mask */
+#define MXC_F_OWM_CFG_FORCE_PRES_DET_POS 1 /**< FORCE_PRES_DET Position */
+#define MXC_F_OWM_CFG_FORCE_PRES_DET ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_FORCE_PRES_DET_POS)) /**< FORCE_PRES_DET Mask */
+#define MXC_F_OWM_CFG_BIT_BANG_EN_POS 2 /**< BIT_BANG_EN Position */
+#define MXC_F_OWM_CFG_BIT_BANG_EN ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_BIT_BANG_EN_POS)) /**< BIT_BANG_EN Mask */
+#define MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS 3 /**< EXT_PULLUP_MODE Position */
+#define MXC_F_OWM_CFG_EXT_PULLUP_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS)) /**< EXT_PULLUP_MODE Mask */
+#define MXC_F_OWM_CFG_EXT_PULLUP_ENABLE_POS 4 /**< EXT_PULLUP_ENABLE Position */
+#define MXC_F_OWM_CFG_EXT_PULLUP_ENABLE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_EXT_PULLUP_ENABLE_POS)) /**< EXT_PULLUP_ENABLE Mask */
+#define MXC_F_OWM_CFG_SINGLE_BIT_MODE_POS 5 /**< SINGLE_BIT_MODE Position */
+#define MXC_F_OWM_CFG_SINGLE_BIT_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_SINGLE_BIT_MODE_POS)) /**< SINGLE_BIT_MODE Mask */
+#define MXC_F_OWM_CFG_OVERDRIVE_POS 6 /**< OVERDRIVE Position */
+#define MXC_F_OWM_CFG_OVERDRIVE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_OVERDRIVE_POS)) /**< OVERDRIVE Mask */
+#define MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS 7 /**< INT_PULLUP_ENABLE Position */
+#define MXC_F_OWM_CFG_INT_PULLUP_ENABLE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS)) /**< INT_PULLUP_ENABLE Mask */
+/**@} end of group owm_cfg*/
+/**
+ * @defgroup owm_clk_div OWM_CLK_DIV
+ * @ingroup owm_registers
+ * @brief Field Positions and Masks
+ */
+#define MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS 0 /**< 1US_DIVISOR Position */
+#define MXC_F_OWM_CLK_DIV_1US_DIVISOR ((uint32_t)(0x000000FFUL << MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS)) /**< 1US_DIVISOR Mask */
+/**@} end of group owm_clk_cfg*/
+/**
+ * @defgroup owm_ctrl_stat OWM_CTRL_STAT
+ * @ingroup owm_registers
+ * @brief Field Positions and Masks
+ */
+#define MXC_F_OWM_CTRL_STAT_START_OW_RESET_POS 0 /**< START_OW_RESET Position */
+#define MXC_F_OWM_CTRL_STAT_START_OW_RESET ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_START_OW_RESET_POS)) /**< START_OW_RESET Mask */
+#define MXC_F_OWM_CTRL_STAT_SRA_MODE_POS 1 /**< SRA_MODE Position */
+#define MXC_F_OWM_CTRL_STAT_SRA_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_SRA_MODE_POS)) /**< SRA_MODE Mask */
+#define MXC_F_OWM_CTRL_STAT_BIT_BANG_OE_POS 2 /**< BIT_BANG_OE Position */
+#define MXC_F_OWM_CTRL_STAT_BIT_BANG_OE ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_BIT_BANG_OE_POS)) /**< BIT_BANG_OE Mask */
+#define MXC_F_OWM_CTRL_STAT_OW_INPUT_POS 3 /**< OW_INPUT Position */
+#define MXC_F_OWM_CTRL_STAT_OW_INPUT ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_OW_INPUT_POS)) /**< OW_INPUT Mask */
+#define MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE_POS 4 /**< OD_SPEC_MODE Position */
+#define MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE_POS)) /**< OD_SPEC_MODE Mask */
+#define MXC_F_OWM_CTRL_STAT_EXT_PULLUP_POL_POS 5 /**< EXT_PULLUP_POL Position */
+#define MXC_F_OWM_CTRL_STAT_EXT_PULLUP_POL ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_EXT_PULLUP_POL_POS)) /**< EXT_PULLUP_POL Mask */
+#define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS 7 /**< PRESENCE_DETECT Position */
+#define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS)) /**< PRESENCE_DETECT Mask */
+/**@} end of group owm_ctrl*/
+/**
+ * @defgroup owm_data OWM_DATA
+ * @ingroup owm_registers
+ * @brief Field Positions and Masks
+ */
+#define MXC_F_OWM_DATA_TX_RX_POS 0 /**< TX_RX Position */
+#define MXC_F_OWM_DATA_TX_RX ((uint32_t)(0x000000FFUL << MXC_F_OWM_DATA_TX_RX_POS)) /**< TX_RX Mask */
+/**@} end of group owm_data*/
+/**
+ * @defgroup owm_intfl OWM_INTFL
+ * @ingroup owm_registers
+ * @brief Field Positions and Masks
+ */
+#define MXC_F_OWM_INTFL_OW_RESET_DONE_POS 0 /**< OW_RESET_DONE Position */
+#define MXC_F_OWM_INTFL_OW_RESET_DONE ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_OW_RESET_DONE_POS)) /**< OW_RESET_DONE Mask */
+#define MXC_F_OWM_INTFL_TX_DATA_EMPTY_POS 1 /**< TX_DATA_EMPTY Position */
+#define MXC_F_OWM_INTFL_TX_DATA_EMPTY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_TX_DATA_EMPTY_POS)) /**< TX_DATA_EMPTY Mask */
+#define MXC_F_OWM_INTFL_RX_DATA_READY_POS 2 /**< RX_DATA_READY Position */
+#define MXC_F_OWM_INTFL_RX_DATA_READY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_RX_DATA_READY_POS)) /**< RX_DATA_READY Mask */
+#define MXC_F_OWM_INTFL_LINE_SHORT_POS 3 /**< LINE_SHORT Position */
+#define MXC_F_OWM_INTFL_LINE_SHORT ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_LINE_SHORT_POS)) /**< LINE_SHORT Mask */
+#define MXC_F_OWM_INTFL_LINE_LOW_POS 4 /**< LINE_LOW Position */
+#define MXC_F_OWM_INTFL_LINE_LOW ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_LINE_LOW_POS)) /**< LINE_LOW Mask */
+/**@} end of group owm_intfl*/
+/**
+ * @defgroup owm_inten OWM_INTEN
+ * @ingroup owm_registers
+ * @brief Field Positions and Masks
+ */
+#define MXC_F_OWM_INTEN_OW_RESET_DONE_POS 0 /**< OW_RESET_DONE Position */
+#define MXC_F_OWM_INTEN_OW_RESET_DONE ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_OW_RESET_DONE_POS)) /**< OW_RESET_DONE Mask */
+#define MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS 1 /**< TX_DATA_EMPTY Position */
+#define MXC_F_OWM_INTEN_TX_DATA_EMPTY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS)) /**< TX_DATA_EMPTY Mask */
+#define MXC_F_OWM_INTEN_RX_DATA_READY_POS 2 /**< RX_DATA_READY Position */
+#define MXC_F_OWM_INTEN_RX_DATA_READY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_RX_DATA_READY_POS)) /**< RX_DATA_READY Mask */
+#define MXC_F_OWM_INTEN_LINE_SHORT_POS 3 /**< LINE_SHORT Position */
+#define MXC_F_OWM_INTEN_LINE_SHORT ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_LINE_SHORT_POS)) /**< LINE_SHORT Mask */
+#define MXC_F_OWM_INTEN_LINE_LOW_POS 4 /**< LINE_LOW Position */
+#define MXC_F_OWM_INTEN_LINE_LOW ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_LINE_LOW_POS)) /**< LINE_LOW Mask */
+/**@} end of group owm_inten*/
+/**
+ * @ingroup owm_cfg
+ * @{
+ */
+#define MXC_V_OWM_CFG_EXT_PULLUP_MODE_UNUSED ((uint32_t)(0x00000000UL)) /**< External Pullup Mode Value: Unused */
+#define MXC_V_OWM_CFG_EXT_PULLUP_MODE_USED ((uint32_t)(0x00000001UL)) /**< External Pullup Mode Value: Used */
+/**@}*/
+/**
+ * @ingroup owm_ctrl_stat
+ * @{
+ */
+#define MXC_V_OWM_CTRL_STAT_OD_SPEC_MODE_12US ((uint32_t)(0x00000000UL)) /**< Overdrive speed setting 12us. */
+#define MXC_V_OWM_CTRL_STAT_OD_SPEC_MODE_10US ((uint32_t)(0x00000001UL)) /**< Overdrive speed setting 10us. */
+
+#define MXC_V_OWM_CTRL_STAT_EXT_PULLUP_POL_ACT_HIGH ((uint32_t)(0x00000000UL)) /**< External Pullup Pin Polarity Active High */
+#define MXC_V_OWM_CTRL_STAT_EXT_PULLUP_POL_ACT_LOW ((uint32_t)(0x00000001UL)) /**< External Pullup Pin Polarity Active Low */
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_OWM_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/pwrman_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32625/pwrman_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,367 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_PWRMAN_REGS_H_
+#define _MXC_PWRMAN_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+
+
+/**
+ * @brief Defines PAD Modes for Wake Up Detection.
+ */
+typedef enum {
+ /** WUD Mode for Selected PAD = Clear/Activate */
+ MXC_E_PWRMAN_PAD_MODE_CLEAR_SET,
+ /** WUD Mode for Selected PAD = Set WUD Act Hi/Set WUD Act Lo */
+ MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO,
+ /** WUD Mode for Selected PAD = Set Weak Hi/ Set Weak Lo */
+ MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO,
+ /** WUD Mode for Selected PAD = No pad state change */
+ MXC_E_PWRMAN_PAD_MODE_NONE
+} mxc_pwrman_pad_mode_t;
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __IO uint32_t pwr_rst_ctrl; /* 0x0000 Power Reset Control and Status */
+ __IO uint32_t intfl; /* 0x0004 Interrupt Flags */
+ __IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */
+ __IO uint32_t svm_events; /* 0x000C SVM Event Status Flags (read-only) */
+ __IO uint32_t wud_ctrl; /* 0x0010 Wake-Up Detect Control */
+ __IO uint32_t wud_pulse0; /* 0x0014 WUD Pulse To Mode Bit 0 */
+ __IO uint32_t wud_pulse1; /* 0x0018 WUD Pulse To Mode Bit 1 */
+ __IO uint32_t wud_seen0; /* 0x001C Wake-up Detect Status for P0/P1/P2/P3 */
+ __IO uint32_t wud_seen1; /* 0x0020 Wake-up Detect Status for P4/P5/P6/P7 */
+ __R uint32_t rsv024[3]; /* 0x0024-0x002C */
+ __IO uint32_t pt_regmap_ctrl; /* 0x0030 PT Register Mapping Control */
+ __R uint32_t rsv034; /* 0x0034 */
+ __IO uint32_t die_type; /* 0x0038 Die Type ID Register */
+ __IO uint32_t base_part_num; /* 0x003C Base Part Number */
+ __IO uint32_t mask_id0; /* 0x0040 Mask ID Register 0 */
+ __IO uint32_t mask_id1; /* 0x0044 Mask ID Register 1 */
+ __IO uint32_t peripheral_reset; /* 0x0048 Peripheral Reset Control Register */
+} mxc_pwrman_regs_t;
+
+
+/*
+ Register offsets for module PWRMAN.
+*/
+
+#define MXC_R_PWRMAN_OFFS_PWR_RST_CTRL ((uint32_t)0x00000000UL)
+#define MXC_R_PWRMAN_OFFS_INTFL ((uint32_t)0x00000004UL)
+#define MXC_R_PWRMAN_OFFS_INTEN ((uint32_t)0x00000008UL)
+#define MXC_R_PWRMAN_OFFS_SVM_EVENTS ((uint32_t)0x0000000CUL)
+#define MXC_R_PWRMAN_OFFS_WUD_CTRL ((uint32_t)0x00000010UL)
+#define MXC_R_PWRMAN_OFFS_WUD_PULSE0 ((uint32_t)0x00000014UL)
+#define MXC_R_PWRMAN_OFFS_WUD_PULSE1 ((uint32_t)0x00000018UL)
+#define MXC_R_PWRMAN_OFFS_WUD_SEEN0 ((uint32_t)0x0000001CUL)
+#define MXC_R_PWRMAN_OFFS_WUD_SEEN1 ((uint32_t)0x00000020UL)
+#define MXC_R_PWRMAN_OFFS_PT_REGMAP_CTRL ((uint32_t)0x00000030UL)
+#define MXC_R_PWRMAN_OFFS_DIE_TYPE ((uint32_t)0x00000038UL)
+#define MXC_R_PWRMAN_OFFS_BASE_PART_NUM ((uint32_t)0x0000003CUL)
+#define MXC_R_PWRMAN_OFFS_MASK_ID0 ((uint32_t)0x00000040UL)
+#define MXC_R_PWRMAN_OFFS_MASK_ID1 ((uint32_t)0x00000044UL)
+#define MXC_R_PWRMAN_OFFS_PERIPHERAL_RESET ((uint32_t)0x00000048UL)
+
+
+/*
+ Field positions and masks for module PWRMAN.
+*/
+
+#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS 2
+#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS 3
+#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS 4
+#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS 5
+#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS 8
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS 9
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS 16
+#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS 17
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS 18
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS 19
+#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS 20
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS 21
+#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS 22
+#define MXC_F_PWRMAN_PWR_RST_CTRL_POR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS 31
+#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS))
+
+#define MXC_F_PWRMAN_INTFL_V1_2_WARNING_POS 0
+#define MXC_F_PWRMAN_INTFL_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_2_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS 1
+#define MXC_F_PWRMAN_INTFL_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_RTC_WARNING_POS 2
+#define MXC_F_PWRMAN_INTFL_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_RTC_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS 3
+#define MXC_F_PWRMAN_INTFL_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_VDDB_WARNING_POS 4
+#define MXC_F_PWRMAN_INTFL_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDB_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_VDDIO_WARNING_POS 5
+#define MXC_F_PWRMAN_INTFL_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDIO_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_VDDIOH_WARNING_POS 6
+#define MXC_F_PWRMAN_INTFL_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDIOH_WARNING_POS))
+
+#define MXC_F_PWRMAN_INTEN_V1_2_WARNING_POS 0
+#define MXC_F_PWRMAN_INTEN_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_2_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS 1
+#define MXC_F_PWRMAN_INTEN_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_RTC_WARNING_POS 2
+#define MXC_F_PWRMAN_INTEN_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_RTC_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS 3
+#define MXC_F_PWRMAN_INTEN_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_VDDB_WARNING_POS 4
+#define MXC_F_PWRMAN_INTEN_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDB_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_VDDIO_WARNING_POS 5
+#define MXC_F_PWRMAN_INTEN_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDIO_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_VDDIOH_WARNING_POS 6
+#define MXC_F_PWRMAN_INTEN_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDIOH_WARNING_POS))
+
+#define MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING_POS 0
+#define MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS 1
+#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS 2
+#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS 3
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING_POS 4
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING_POS 5
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING_POS 6
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING_POS))
+
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS 0
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT ((uint32_t)(0x0000003FUL << MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS))
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS 8
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE ((uint32_t)(0x00000003UL << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS))
+#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS 12
+#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS))
+#define MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE_POS 16
+#define MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE_POS))
+
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS 0
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS 1
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS 2
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS 3
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS 4
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS 5
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS 6
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS 7
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS 8
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS 9
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS 10
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS 11
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS 12
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS 13
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS 14
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS 15
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS 16
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS 17
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS 18
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS 19
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS 20
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS 21
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS 22
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS 23
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS 24
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS 25
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS 26
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS 27
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS 28
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS 29
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS 30
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS 31
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS))
+
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS 0
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS 1
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS 2
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS 3
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS 4
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS 5
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS 6
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS 7
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS))
+
+#define MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE_POS 0
+#define MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE_POS))
+
+#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS 0
+#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER ((uint32_t)(0x0000FFFFUL << MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS))
+
+#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS 0
+#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID ((uint32_t)(0x0000000FUL << MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS))
+#define MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS 4
+#define MXC_F_PWRMAN_MASK_ID0_MASK_ID ((uint32_t)(0x0FFFFFFFUL << MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS))
+
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS 0
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS))
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS 31
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS))
+
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS 0
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX_POS 1
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_PMU_POS 2
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_PMU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PMU_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS 3
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS 4
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS 5
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS 6
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS 7
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS 8
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS 9
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS 10
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS 11
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4_POS 12
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5_POS 13
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS 14
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS 15
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS 16
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART2_POS 17
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART2_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS 19
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS 20
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS 22
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0_POS 23
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1_POS 24
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2_POS 25
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_OWM_POS 27
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_OWM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_OWM_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS 28
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS_POS 29
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_PWRMAN_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/pwrseq_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32625/pwrseq_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,425 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_PWRSEQ_REGS_H_
+#define _MXC_PWRSEQ_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __IO uint32_t reg0; /* 0x0000 Power Sequencer Control Register 0 */
+ __IO uint32_t reg1; /* 0x0004 Power Sequencer Control Register 1 */
+ __IO uint32_t reg2; /* 0x0008 Power Sequencer Control Register 2 */
+ __IO uint32_t reg3; /* 0x000C Power Sequencer Control Register 3 */
+ __IO uint32_t reg4; /* 0x0010 Power Sequencer Control Register 4 (Internal Test Only) */
+ __IO uint32_t reg5; /* 0x0014 Power Sequencer Control Register 5 (Trim 0) */
+ __IO uint32_t reg6; /* 0x0018 Power Sequencer Control Register 6 (Trim 1) */
+ __IO uint32_t reg7; /* 0x001C Power Sequencer Control Register 7 (Trim 2) */
+ __IO uint32_t flags; /* 0x0020 Power Sequencer Flags */
+ __IO uint32_t msk_flags; /* 0x0024 Power Sequencer Flags Mask Register */
+ __R uint32_t rsv028; /* 0x0028 */
+ __IO uint32_t wr_protect; /* 0x002C Critical Setting Write Protect Register */
+ __IO uint32_t retn_ctrl0; /* 0x0030 Retention Control Register 0 */
+ __IO uint32_t retn_ctrl1; /* 0x0034 Retention Control Register 1 */
+ __IO uint32_t pwr_misc; /* 0x0038 Power Misc Controls */
+ __IO uint32_t rtc_ctrl2; /* 0x003C RTC Misc Controls */
+} mxc_pwrseq_regs_t;
+
+
+/*
+ Register offsets for module PWRSEQ.
+*/
+
+#define MXC_R_PWRSEQ_OFFS_REG0 ((uint32_t)0x00000000UL)
+#define MXC_R_PWRSEQ_OFFS_REG1 ((uint32_t)0x00000004UL)
+#define MXC_R_PWRSEQ_OFFS_REG2 ((uint32_t)0x00000008UL)
+#define MXC_R_PWRSEQ_OFFS_REG3 ((uint32_t)0x0000000CUL)
+#define MXC_R_PWRSEQ_OFFS_REG4 ((uint32_t)0x00000010UL)
+#define MXC_R_PWRSEQ_OFFS_REG5 ((uint32_t)0x00000014UL)
+#define MXC_R_PWRSEQ_OFFS_REG6 ((uint32_t)0x00000018UL)
+#define MXC_R_PWRSEQ_OFFS_REG7 ((uint32_t)0x0000001CUL)
+#define MXC_R_PWRSEQ_OFFS_FLAGS ((uint32_t)0x00000020UL)
+#define MXC_R_PWRSEQ_OFFS_MSK_FLAGS ((uint32_t)0x00000024UL)
+#define MXC_R_PWRSEQ_OFFS_WR_PROTECT ((uint32_t)0x0000002CUL)
+#define MXC_R_PWRSEQ_OFFS_RETN_CTRL0 ((uint32_t)0x00000030UL)
+#define MXC_R_PWRSEQ_OFFS_RETN_CTRL1 ((uint32_t)0x00000034UL)
+#define MXC_R_PWRSEQ_OFFS_PWR_MISC ((uint32_t)0x00000038UL)
+#define MXC_R_PWRSEQ_OFFS_RTC_CTRL2 ((uint32_t)0x0000003CUL)
+
+
+/*
+ Field positions and masks for module PWRSEQ.
+*/
+
+#define MXC_F_PWRSEQ_REG0_PWR_LP1_POS 0
+#define MXC_F_PWRSEQ_REG0_PWR_LP1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS 1
+#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS 2
+#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS 3
+#define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS 4
+#define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS 5
+#define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS 6
+#define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS 7
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS 8
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS 9
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS 10
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS 11
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS 12
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS 13
+#define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS 15
+#define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS 17
+#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS 19
+#define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS 21
+#define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS 23
+#define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS 24
+#define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS 25
+#define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS 26
+#define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS 27
+#define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS 28
+#define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN_POS 29
+#define MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP_POS 30
+#define MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT_POS 31
+#define MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT_POS))
+
+#define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS 0
+#define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS 1
+#define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS 2
+#define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS 3
+#define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS 4
+#define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW_POS 5
+#define MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE_POS 6
+#define MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN_POS 8
+#define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN_POS 10
+#define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12_POS 12
+#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC_POS 13
+#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18_POS 14
+#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR_POS 16
+#define MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR_POS 17
+#define MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN_POS 18
+#define MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN_POS 19
+#define MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN_POS))
+
+#define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS 0
+#define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS 2
+#define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS 4
+#define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS 6
+#define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS 8
+#define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST_POS 10
+#define MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST_POS 12
+#define MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST_POS))
+
+#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS 0
+#define MXC_F_PWRSEQ_REG3_PWR_ROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS 3
+#define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS 6
+#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS 8
+#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS 10
+#define MXC_F_PWRSEQ_REG3_PWR_FAILSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS 16
+#define MXC_F_PWRSEQ_REG3_PWR_RO_DIV ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS 20
+#define MXC_F_PWRSEQ_REG3_PWR_RC_DIV ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS))
+
+#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS 0
+#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS 1
+#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS 3
+#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS 4
+#define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS 5
+#define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS 6
+#define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS 7
+#define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_RTC_MUX_POS 8
+#define MXC_F_PWRSEQ_REG4_PWR_RTC_MUX ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RTC_MUX_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN_POS 9
+#define MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN_POS 10
+#define MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN_POS))
+
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS 0
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS))
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS 9
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS))
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0_POS 15
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0 ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0_POS))
+#define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS 21
+#define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS))
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6_POS 25
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6 ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6_POS))
+
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS 0
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS))
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS 3
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS))
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS 7
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS))
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS 11
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS))
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS 20
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS))
+
+#define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS 0
+#define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS))
+#define MXC_F_PWRSEQ_REG7_PWR_TRIM_RC_POS 16
+#define MXC_F_PWRSEQ_REG7_PWR_TRIM_RC ((uint32_t)(0x0000FFFFUL << MXC_F_PWRSEQ_REG7_PWR_TRIM_RC_POS))
+
+#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS 0
+#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS 1
+#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS 2
+#define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS 3
+#define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS 4
+#define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS 5
+#define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS 6
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS 7
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS 8
+#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS 9
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS 10
+#define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS 11
+#define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS 12
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS 13
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS 14
+#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS 15
+#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS 16
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 17
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS 18
+#define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD_POS 19
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD_POS 20
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS 21
+#define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS 22
+#define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS 23
+#define MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS 24
+#define MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS))
+
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS 1
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS 2
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS 3
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS 4
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS 5
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS 6
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS 7
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS 8
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS 9
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS 10
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS 11
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS 12
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS 13
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS 14
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS 15
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS 16
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 17
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS 18
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD_POS 19
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD_POS 20
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS 21
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS 22
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS 23
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS 24
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS))
+
+#define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ_POS 0
+#define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ_POS))
+#define MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ_POS 8
+#define MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ_POS))
+#define MXC_F_PWRSEQ_WR_PROTECT_RTC_POS 28
+#define MXC_F_PWRSEQ_WR_PROTECT_RTC ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_RTC_POS))
+#define MXC_F_PWRSEQ_WR_PROTECT_INFO_POS 29
+#define MXC_F_PWRSEQ_WR_PROTECT_INFO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_INFO_POS))
+#define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_POS 30
+#define MXC_F_PWRSEQ_WR_PROTECT_BYPASS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_BYPASS_POS))
+#define MXC_F_PWRSEQ_WR_PROTECT_WP_POS 31
+#define MXC_F_PWRSEQ_WR_PROTECT_WP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_WP_POS))
+
+#define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS 0
+#define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS))
+#define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS 1
+#define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS))
+#define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS 2
+#define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS))
+#define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS 3
+#define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS))
+#define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS 4
+#define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS))
+
+#define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS 0
+#define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS))
+#define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS 4
+#define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS))
+
+#define MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS_POS 0
+#define MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS_POS))
+
+#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD_POS 0
+#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD_POS))
+#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR_POS 1
+#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR_POS))
+#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE_POS 2
+#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE_POS))
+#define MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE_POS 3
+#define MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE_POS))
+#define MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK_POS 24
+#define MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_PWRSEQ_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/read_uid.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32625/read_uid.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,24 @@
+/* CMSIS-DAP Interface Firmware
+ * Copyright (c) 2009-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "read_uid.h"
+
+#define UID_BASE 0x40001018
+
+void read_unique_id(uint32_t * id)
+{
+ uint32_t *uid_ptr = (uint32_t*)UID_BASE;
+ *id = uid_ptr[0] ^ uid_ptr[1] ^ uid_ptr[2] ^ uid_ptr[3];
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/rtc_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32625/rtc_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,353 @@
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ **************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_RTC_REGS_H_
+#define _MXC_RTC_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+/// @cond
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+/// @endcond
+
+/**
+ * @defgroup rtc_registers RTC Registers
+ * @brief Registers, Bit Masks and Bit Positions
+ * @ingroup rtc
+ * @{
+ */
+
+/**
+ * Structure type for the Real-Time Clock module registers allowing direct 32-bit access to each register.
+ */
+ typedef struct {
+ __IO uint32_t ctrl; /**< <tt>\b 0x0000: </tt> RTC_CTRL Register - RTC Timer Control */
+ __IO uint32_t timer; /**< <tt>\b 0x0004: </tt> RTC_TIMER Register - RTC Timer Count Value */
+ __IO uint32_t comp[2]; /**< <tt>\b 0x0008-0x000C: </tt> RTC_COMP0/RTC_COMP1 Registers - RTC Time of Day Alarm [0..1] Compare Register */
+ __IO uint32_t flags; /**< <tt>\b 0x0010: </tt> RTC_FLAGS Register - CPU Interrupt and RTC Domain Flags */
+ __IO uint32_t snz_val; /**< <tt>\b 0x0014: </tt> RTC_SNZ_VAL Register - RTC Timer Alarm Snooze Value */
+ __IO uint32_t inten; /**< <tt>\b 0x0018: </tt> RTC_INTEN Register - Interrupt Enable Controls */
+ __IO uint32_t prescale; /**< <tt>\b 0x001C: </tt> RTC_PRESCALE Register - RTC Timer Prescale Setting */
+ __R uint32_t rsv020; /**< <tt>\b 0x0020: </tt> RESERVED */
+ __IO uint32_t prescale_mask; /**< <tt>\b 0x0024: </tt> RTC_PRESCALE_MASK Register - RTC Timer Prescale Compare Mask */
+ __IO uint32_t trim_ctrl; /**< <tt>\b 0x0028: </tt> RTC_TRIM_CTRL Register - RTC Timer Trim Controls */
+ __IO uint32_t trim_value; /**< <tt>\b 0x002C: </tt> RTC_TRIM_VALUE Register - RTC Timer Trim Adjustment Interval */
+} mxc_rtctmr_regs_t;
+
+
+/**
+ * Structure type for access to the RTC CFG hardware.
+ */
+typedef struct {
+ __IO uint32_t nano_cntr; /**< <tt>\b 0x0000: </tt> - RTCCFG_NANO_CNTR - Nano Oscillator Counter Read Register */
+ __IO uint32_t clk_ctrl; /**< <tt>\b 0x0004: </tt> - RTCCFG_CLK_CTRL - RTC Clock Control Settings */
+ __R uint32_t rsv008; /**< <tt>\b 0x0008: </tt> - RESERVED */
+ __IO uint32_t osc_ctrl; /**< <tt>\b 0x000C: </tt> - RTCCFG_OSC_CTRL - RTC Oscillator Control */
+} mxc_rtccfg_regs_t;
+/**@} end of group rtc_registers.*/
+
+/*
+ Register offsets for module RTC.
+*/
+/**
+ * @defgroup RTC_Register_Offsets Register Offsets
+ * @ingroup rtc_registers
+ * @brief Real-Time Clock Register Offsets from the RTC Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_RTCTMR_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0000</tt> */
+#define MXC_R_RTCTMR_OFFS_TIMER ((uint32_t)0x00000004UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0004</tt> */
+#define MXC_R_RTCTMR_OFFS_COMP0 ((uint32_t)0x00000008UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0008</tt> */
+#define MXC_R_RTCTMR_OFFS_COMP1 ((uint32_t)0x0000000CUL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x000C</tt> */
+#define MXC_R_RTCTMR_OFFS_FLAGS ((uint32_t)0x00000010UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0010</tt> */
+#define MXC_R_RTCTMR_OFFS_SNZ_VAL ((uint32_t)0x00000014UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0014</tt> */
+#define MXC_R_RTCTMR_OFFS_INTEN ((uint32_t)0x00000018UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0018</tt> */
+#define MXC_R_RTCTMR_OFFS_PRESCALE ((uint32_t)0x0000001CUL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x001C</tt> */
+#define MXC_R_RTCTMR_OFFS_PRESCALE_MASK ((uint32_t)0x00000024UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0024</tt> */
+#define MXC_R_RTCTMR_OFFS_TRIM_CTRL ((uint32_t)0x00000028UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0028</tt> */
+#define MXC_R_RTCTMR_OFFS_TRIM_VALUE ((uint32_t)0x0000002CUL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x002C</tt> */
+/**@} end of group RTC_Register_Offsets */
+/**
+ * @defgroup RTCCFG_Register_Offsets RTCCFG Register Offsets
+ * @ingroup rtc_registers
+ * @brief Real-Time Clock CFG Register Offsets from the RTCCFG Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_RTCCFG_OFFS_NANO_CNTR ((uint32_t)0x00000000UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0000</tt> */
+#define MXC_R_RTCCFG_OFFS_CLK_CTRL ((uint32_t)0x00000004UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0004</tt> */
+#define MXC_R_RTCCFG_OFFS_OSC_CTRL ((uint32_t)0x0000000CUL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x000C</tt> */
+/**@} end of group RTCCFG_Register_Offsets */
+
+/*
+ Field positions and masks for module RTC.
+*/
+/**
+ * @defgroup RTC_CTRL_Register RTC_CTRL
+ * @ingroup rtc_registers
+ * @{
+ */
+#define MXC_F_RTC_CTRL_ENABLE_POS 0 /**< ENABLE Position */
+#define MXC_F_RTC_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ENABLE_POS)) /**< ENABLE Mask */
+#define MXC_F_RTC_CTRL_CLEAR_POS 1 /**< CLEAR Position */
+#define MXC_F_RTC_CTRL_CLEAR ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLEAR_POS)) /**< CLEAR Mask */
+#define MXC_F_RTC_CTRL_PENDING_POS 2 /**< PENDING Position */
+#define MXC_F_RTC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PENDING_POS)) /**< PENDING Mask */
+#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS 3 /**< USE_ASYNC_FLAGS Position */
+#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS)) /**< USE_ASYNC_FLAGS Mask */
+#define MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS 4 /**< AGGRESSIVE_RST Position */
+#define MXC_F_RTC_CTRL_AGGRESSIVE_RST ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS)) /**< AGGRESSIVE_RST Mask */
+#define MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE_POS 5 /**< AUTO_UPDATE_DISABLE Position */
+#define MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE_POS)) /**< AUTO_UPDATE_DISABLE Mask */
+#define MXC_F_RTC_CTRL_SNOOZE_ENABLE_POS 6 /**< SNOOZE_ENABLE Position */
+#define MXC_F_RTC_CTRL_SNOOZE_ENABLE ((uint32_t)(0x00000003UL << MXC_F_RTC_CTRL_SNOOZE_ENABLE_POS)) /**< SNOOZE_ENABLE Mask */
+#define MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE_POS 16 /**< RTC_ENABLE_ACTIVE Position */
+#define MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE_POS)) /**< RTC_ENABLE_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS 17 /**< OSC_GOTO_LOW_ACTIVE Position */
+#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS)) /**< OSC_GOTO_LOW_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS 18 /**< OSC_FRCE_SM_EN_ACTIVE Position */
+#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS)) /**< OSC_FRCE_SM_EN_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS 19 /**< OSC_FRCE_ST_ACTIVE Position */
+#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS)) /**< OSC_FRCE_ST_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_RTC_SET_ACTIVE_POS 20 /**< RTC_SET_ACTIVE Position */
+#define MXC_F_RTC_CTRL_RTC_SET_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_SET_ACTIVE_POS)) /**< RTC_SET_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_RTC_CLR_ACTIVE_POS 21 /**< RTC_CLR_ACTIVE Position */
+#define MXC_F_RTC_CTRL_RTC_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_CLR_ACTIVE_POS)) /**< RTC_CLR_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS 22 /**< ROLLOVER_CLR_ACTIVE Position */
+#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS)) /**< ROLLOVER_CLR_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS 23 /**< PRESCALE_CMPR0_ACTIVE Position */
+#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS)) /**< PRESCALE_CMPR0_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS 24 /**< PRESCALE_UPDATE_ACTIVE Position */
+#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS)) /**< PRESCALE_UPDATE_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS 25 /**< CMPR1_CLR_ACTIVE Position */
+#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS)) /**< CMPR1_CLR_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS 26 /**< CMPR0_CLR_ACTIVE Position */
+#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS)) /**< CMPR0_CLR_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE_POS 27 /**< TRIM_ENABLE_ACTIVE Position */
+#define MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE_POS)) /**< TRIM_ENABLE_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE_POS 28 /**< TRIM_SLOWER_ACTIVE Position */
+#define MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE_POS)) /**< TRIM_SLOWER_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE_POS 29 /**< TRIM_CLR_ACTIVE Position */
+#define MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE_POS)) /**< TRIM_CLR_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_ACTIVE_TRANS_0_POS 30 /**< ACTIVE_TRANS_0 Position */
+#define MXC_F_RTC_CTRL_ACTIVE_TRANS_0 ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ACTIVE_TRANS_0_POS)) /**< ACTIVE_TRANS_0 Mask */
+/**@} end of group RTC_CTRL*/
+/**
+ * @defgroup RTC_FLAGS_Register RTC_FLAGS
+ * @ingroup rtc_registers
+ * @{
+ */
+#define MXC_F_RTC_FLAGS_COMP0_POS 0 /**< COMP0 Position */
+#define MXC_F_RTC_FLAGS_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_POS)) /**< COMP0 Mask */
+#define MXC_F_RTC_FLAGS_COMP1_POS 1 /**< COMP1 Position */
+#define MXC_F_RTC_FLAGS_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_POS)) /**< COMP1 Mask */
+#define MXC_F_RTC_FLAGS_PRESCALE_COMP_POS 2 /**< PRESCALE_COMP Position */
+#define MXC_F_RTC_FLAGS_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCALE_COMP_POS)) /**< PRESCALE_COMP Mask */
+#define MXC_F_RTC_FLAGS_OVERFLOW_POS 3 /**< OVERFLOW Position */
+#define MXC_F_RTC_FLAGS_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_POS)) /**< OVERFLOW Mask */
+#define MXC_F_RTC_FLAGS_TRIM_POS 4 /**< TRIM Position */
+#define MXC_F_RTC_FLAGS_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_POS)) /**< TRIM Mask */
+#define MXC_F_RTC_FLAGS_SNOOZE_POS 5 /**< SNOOZE Position */
+#define MXC_F_RTC_FLAGS_SNOOZE ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_POS)) /**< SNOOZE Mask */
+#define MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS 8 /**< COMP0_FLAG_A Position */
+#define MXC_F_RTC_FLAGS_COMP0_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS)) /**< COMP0_FLAG_A Mask */
+#define MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS 9 /**< COMP1_FLAG_A Position */
+#define MXC_F_RTC_FLAGS_COMP1_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS)) /**< COMP1_FLAG_A Mask */
+#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS 10 /**< PRESCL_FLAG_A Position */
+#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS)) /**< PRESCL_FLAG_A Mask */
+#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS 11 /**< OVERFLOW_FLAG_A Position */
+#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS)) /**< OVERFLOW_FLAG_A Mask */
+#define MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS 12 /**< TRIM_FLAG_A Position */
+#define MXC_F_RTC_FLAGS_TRIM_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS)) /**< TRIM_FLAG_A Mask */
+#define MXC_F_RTC_FLAGS_SNOOZE_A_POS 28 /**< SNOOZE_A Position */
+#define MXC_F_RTC_FLAGS_SNOOZE_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_A_POS)) /**< SNOOZE_A Mask */
+#define MXC_F_RTC_FLAGS_SNOOZE_B_POS 29 /**< SNOOZE_B Position */
+#define MXC_F_RTC_FLAGS_SNOOZE_B ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_B_POS)) /**< SNOOZE_B Mask */
+#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS 31 /**< ASYNC_CLR_FLAGS Position */
+#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS)) /**< ASYNC_CLR_FLAGS Mask */
+/**@} end of group RTC_FLAGS_Register */
+/**
+ * @defgroup RTC_SNZ_VAL_Register RTC_SNZ_VAL.
+ * @ingroup rtc_registers
+ * @{
+ */
+#define MXC_F_RTC_SNZ_VAL_VALUE_POS 0 /**< VALUE Position */
+#define MXC_F_RTC_SNZ_VAL_VALUE ((uint32_t)(0x000003FFUL << MXC_F_RTC_SNZ_VAL_VALUE_POS)) /**< VALUE Mask */
+/**@} end of group RTC_SNZ_VAL_Register */
+/**
+ * @defgroup RTC_INTEN_Register RTC_INTEN.
+ * @ingroup rtc_registers
+ * @{
+ */
+#define MXC_F_RTC_INTEN_COMP0_POS 0 /**< COMP0 Position */
+#define MXC_F_RTC_INTEN_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP0_POS)) /**< COMP0 Mask */
+#define MXC_F_RTC_INTEN_COMP1_POS 1 /**< COMP1 Position */
+#define MXC_F_RTC_INTEN_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP1_POS)) /**< COMP1 Mask */
+#define MXC_F_RTC_INTEN_PRESCALE_COMP_POS 2 /**< PRESCALE_COMP Position */
+#define MXC_F_RTC_INTEN_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_PRESCALE_COMP_POS)) /**< PRESCALE_COMP Mask */
+#define MXC_F_RTC_INTEN_OVERFLOW_POS 3 /**< OVERFLOW Position */
+#define MXC_F_RTC_INTEN_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_OVERFLOW_POS)) /**< OVERFLOW Mask */
+#define MXC_F_RTC_INTEN_TRIM_POS 4 /**< TRIM Position */
+#define MXC_F_RTC_INTEN_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_TRIM_POS)) /**< TRIM Mask */
+/**@} end of group RTC_INTEN_Register */
+/**
+ * @defgroup RTC_PRESCALE_Register RTC_PRESCALE.
+ * @ingroup rtc_registers
+ * @{
+ */
+#define MXC_F_RTC_PRESCALE_PRESCALE_POS 0 /**< PRESCALE Position */
+#define MXC_F_RTC_PRESCALE_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_PRESCALE_POS)) /**< PRESCALE Mask */
+/**@} end of group RTC_INTEN_Register */
+/**
+ * @defgroup RTC_PRESCALE_MASK_Register RTC_PRESCALE_MASK.
+ * @ingroup rtc_registers
+ * @{
+ */
+#define MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK_POS 0 /**< PRESCALE_MASK Position */
+#define MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK_POS)) /**< PRESCALE_MASK Mask */
+/**@} end of group RTC_PRESCALE_MASK_Register */
+/**
+ * @defgroup RTC_TRIM_CTRL_Register RTC_TRIM_CTRL.
+ * @ingroup rtc_registers
+ * @{
+ */
+#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS 0 /**< TRIM_ENABLE_R Position */
+#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS)) /**< TRIM_ENABLE_R Mask */
+#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS 1 /**< TRIM_FASTER_OVR_R Position */
+#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS)) /**< TRIM_FASTER_OVR_R Mask */
+#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS 2 /**< TRIM_SLOWER_R Position */
+#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS)) /**< TRIM_SLOWER_R Mask */
+/**@} end of group RTC_TRIM_CTRL_Register */
+/**
+ * @defgroup RTC_TRIM_VALUE_Register RTC_TRIM_VALUE.
+ * @ingroup rtc_registers
+ * @{
+ */
+#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS 0 /**< TRIM_VALUE Position */
+#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE ((uint32_t)(0x0003FFFFUL << MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS)) /**< TRIM_VALUE Mask */
+#define MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL_POS 18 /**< TRIM_SLOWER_CONTROL Position */
+#define MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL_POS)) /**< TRIM_SLOWER_CONTROL Mask */
+/**@} end of group RTC_TRIM_VALUE_Register */
+/**
+ * @defgroup RTC_NANO_CNTR_Register RTC_NANO_CNTR.
+ * @ingroup rtc_registers
+ * @{
+ */
+#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS 0 /**< NANORING_COUNTER Position */
+#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER ((uint32_t)(0x0000FFFFUL << MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS)) /**< NANORING_COUNTER Mask */
+/**@} end of group RTC_NANO_CNTR_Register */
+/**
+ * @defgroup RTC_CLK_CTRL_Register RTC_CLK_CTRL.
+ * @ingroup rtc_registers
+ * @{
+ */
+#define MXC_F_RTC_CLK_CTRL_OSC1_EN_POS 0 /**< OSC1_EN Position */
+#define MXC_F_RTC_CLK_CTRL_OSC1_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC1_EN_POS)) /**< OSC1_EN Mask */
+#define MXC_F_RTC_CLK_CTRL_OSC2_EN_POS 1 /**< OSC2_EN Position */
+#define MXC_F_RTC_CLK_CTRL_OSC2_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC2_EN_POS)) /**< OSC2_EN Mask */
+#define MXC_F_RTC_CLK_CTRL_NANO_EN_POS 2 /**< NANO_EN Position */
+#define MXC_F_RTC_CLK_CTRL_NANO_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_NANO_EN_POS)) /**< NANO_EN Mask */
+/**@} end of group RTC_CLK_CTRL_Register */
+/**
+ * @defgroup RTC_OSC_CTRL_Register RTC_OSC_CTRL.
+ * @ingroup rtc_registers
+ * @{
+ */
+#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS 0 /**< OSC_BYPASS Position */
+#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS)) /**< OSC_BYPASS Mask */
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS 1 /**< OSC_DISABLE_R Position */
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS)) /**< OSC_DISABLE_R Mask */
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS 2 /**< OSC_DISABLE_SEL Position */
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS)) /**< OSC_DISABLE_SEL Mask */
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS 3 /**< OSC_DISABLE_O Position */
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS)) /**< OSC_DISABLE_O Mask */
+#define MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE_POS 14 /**< OSC_WARMUP_ENABLE Position */
+#define MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE_POS)) /**< OSC_WARMUP_ENABLE Mask */
+/**@} end of group RTC_OSC_CTRL_Register */
+
+/*
+ Field values
+*/
+/**
+ * @defgroup rtc_snz_mode_values RTC SNOOZE MODE Values
+ * @ingroup RTC_CTRL_Register
+ * @{
+ */
+#define MXC_V_RTC_CTRL_SNOOZE_DISABLE ((uint32_t)(0x00000000UL)) /**< SNOOZE Mode Disable */
+#define MXC_V_RTC_CTRL_SNOOZE_MODE_A ((uint32_t)(0x00000001UL)) /**< SNOOZE Mode A */
+#define MXC_V_RTC_CTRL_SNOOZE_MODE_B ((uint32_t)(0x00000002UL)) /**< SNOOZE Mode B */
+/**@} end of group rtc_snz_mode_values */
+/**
+ * @defgroup rtc_prescale_values RTC Prescale Values
+ * @ingroup RTC_PRESCALE_Register
+ * @{
+ */
+#define MXC_V_RTC_PRESCALE_DIV_2_0 ((uint32_t)(0x00000000UL)) /**< RTC Prescale Divide by \f$ 2^{0} \f$.*/
+#define MXC_V_RTC_PRESCALE_DIV_2_1 ((uint32_t)(0x00000001UL)) /**< RTC Prescale Divide by \f$ 2^{1} \f$.*/
+#define MXC_V_RTC_PRESCALE_DIV_2_2 ((uint32_t)(0x00000002UL)) /**< RTC Prescale Divide by \f$ 2^{2} \f$.*/
+#define MXC_V_RTC_PRESCALE_DIV_2_3 ((uint32_t)(0x00000003UL)) /**< RTC Prescale Divide by \f$ 2^{3} \f$.*/
+#define MXC_V_RTC_PRESCALE_DIV_2_4 ((uint32_t)(0x00000004UL)) /**< RTC Prescale Divide by \f$ 2^{4} \f$.*/
+#define MXC_V_RTC_PRESCALE_DIV_2_5 ((uint32_t)(0x00000005UL)) /**< RTC Prescale Divide by \f$ 2^{5} \f$.*/
+#define MXC_V_RTC_PRESCALE_DIV_2_6 ((uint32_t)(0x00000006UL)) /**< RTC Prescale Divide by \f$ 2^{6} \f$.*/
+#define MXC_V_RTC_PRESCALE_DIV_2_7 ((uint32_t)(0x00000007UL)) /**< RTC Prescale Divide by \f$ 2^{7} \f$.*/
+#define MXC_V_RTC_PRESCALE_DIV_2_8 ((uint32_t)(0x00000008UL)) /**< RTC Prescale Divide by \f$ 2^{8} \f$.*/
+#define MXC_V_RTC_PRESCALE_DIV_2_9 ((uint32_t)(0x00000009UL)) /**< RTC Prescale Divide by \f$ 2^{9} \f$.*/
+#define MXC_V_RTC_PRESCALE_DIV_2_10 ((uint32_t)(0x0000000AUL)) /**< RTC Prescale Divide by \f$ 2^{10} \f$.*/
+#define MXC_V_RTC_PRESCALE_DIV_2_11 ((uint32_t)(0x0000000BUL)) /**< RTC Prescale Divide by \f$ 2^{11} \f$.*/
+#define MXC_V_RTC_PRESCALE_DIV_2_12 ((uint32_t)(0x0000000CUL)) /**< RTC Prescale Divide by \f$ 2^{12} \f$.*/
+/**@} end of group rtc_prescale_values*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_RTC_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/system_max32625.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32625/system_max32625.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,281 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#include <string.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include "max32625.h"
+#include "clkman_regs.h"
+#include "adc_regs.h"
+#include "pwrseq_regs.h"
+#include "pwrman_regs.h"
+#include "icc_regs.h"
+#include "flc_regs.h"
+#include "rtc_regs.h"
+#include "trim_regs.h"
+
+#ifndef RO_FREQ
+#define RO_FREQ 96000000
+#endif
+
+#ifndef LP0_POST_HOOK
+#define LP0_POST_HOOK
+#endif
+
+/*
+* Note: When compiling on ARM Keil Toolchain only.
+* If the SystemCoreClock is left uninitialized, post Scatter load
+* the clock will default to system reset value(48MHz)
+*/
+uint32_t SystemCoreClock = RO_FREQ;
+
+void SystemCoreClockUpdate(void)
+{
+ if (MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN) {
+ /* 4 MHz source */
+ if (MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RC_DIV) {
+ SystemCoreClock = (4000000 / (0x1 << ((MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RC_DIV) >>
+ MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS)));
+ } else {
+ SystemCoreClock = 4000000;
+ }
+ } else {
+ /* 96 MHz source */
+ if (MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RO_DIV) {
+ SystemCoreClock = (RO_FREQ / (0x1 << ((MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RO_DIV) >>
+ MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS)));
+ } else {
+ SystemCoreClock = RO_FREQ;
+ }
+ }
+}
+
+void CLKMAN_TrimRO(void)
+{
+ uint32_t running;
+ uint32_t trim;
+
+ /* Step 1: enable 32KHz RTC */
+ running = MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
+ MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
+
+ /* Wait for RTC warm-up */
+ while(MXC_RTCCFG->osc_ctrl & MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE) {}
+
+ /* Step 2: enable RO calibration complete interrupt */
+ MXC_ADC->intr |= MXC_F_ADC_INTR_RO_CAL_DONE_IE;
+
+ /* Step 3: clear RO calibration complete interrupt */
+ MXC_ADC->intr |= MXC_F_ADC_INTR_RO_CAL_DONE_IF;
+
+ /* Step 4: -- NO LONGER NEEDED / HANDLED BY STARTUP CODE -- */
+
+ /* Step 5: write initial trim to frequency calibration initial condition register */
+ trim = (MXC_PWRSEQ->reg6 & MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF) >> MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS;
+ MXC_ADC->ro_cal1 = (MXC_ADC->ro_cal1 & ~MXC_F_ADC_RO_CAL1_TRM_INIT) |
+ ((trim << MXC_F_ADC_RO_CAL1_TRM_INIT_POS) & MXC_F_ADC_RO_CAL1_TRM_INIT);
+
+ /* Step 6: load initial trim to active frequency trim register */
+ MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_LOAD;
+
+ /* Step 7: enable frequency loop to control RO trim */
+ MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_EN;
+
+ /* Step 8: run frequency calibration in atomic mode */
+ MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC;
+
+ /* Step 9: waiting for ro_cal_done flag */
+ while(!(MXC_ADC->intr & MXC_F_ADC_INTR_RO_CAL_DONE_IF));
+
+ /* Step 10: stop frequency calibration */
+ MXC_ADC->ro_cal0 &= ~MXC_F_ADC_RO_CAL0_RO_CAL_RUN;
+
+ /* Step 11: disable RO calibration complete interrupt */
+ MXC_ADC->intr &= ~MXC_F_ADC_INTR_RO_CAL_DONE_IE;
+
+ /* Step 12: read final frequency trim value */
+ trim = (MXC_ADC->ro_cal0 & MXC_F_ADC_RO_CAL0_RO_TRM) >> MXC_F_ADC_RO_CAL0_RO_TRM_POS;
+
+ /* Step 13: write final trim to RO flash trim shadow register */
+ MXC_PWRSEQ->reg6 = (MXC_PWRSEQ->reg6 & ~MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF) |
+ ((trim << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS) & MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF);
+
+ /* Step 14: restore RTC status */
+ if (!running) {
+ MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
+ }
+
+ /* Step 15: disable frequency loop to control RO trim */
+ MXC_ADC->ro_cal0 &= ~MXC_F_ADC_RO_CAL0_RO_CAL_EN;
+}
+
+static void ICC_Enable(void)
+{
+ /* Invalidate cache and wait until ready */
+ MXC_ICC->invdt_all = 1;
+ while (!(MXC_ICC->ctrl_stat & MXC_F_ICC_CTRL_STAT_READY));
+
+ /* Enable cache */
+ MXC_ICC->ctrl_stat |= MXC_F_ICC_CTRL_STAT_ENABLE;
+
+ /* Must invalidate a second time for proper use */
+ MXC_ICC->invdt_all = 1;
+}
+
+/* This function is called before C runtime initialization and can be
+ * implemented by the application for early initializations. If a value other
+ * than '0' is returned, the C runtime initialization will be skipped.
+ *
+ * You may over-ride this function in your program by defining a custom
+ * PreInit(), but care should be taken to reproduce the initilization steps
+ * or a non-functional system may result.
+ */
+__weak int PreInit(void)
+{
+ /* Increase system clock to 96 MHz */
+ MXC_CLKMAN->clk_ctrl = MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO;
+
+ /* Performance-measurement hook, may be defined as nothing */
+ LP0_POST_HOOK;
+
+ /* Enable cache here to reduce boot time */
+ ICC_Enable();
+
+ return 0;
+}
+
+/*
+* Note: When compiling on ARM Keil Toolchain only.
+* If any global variable is modified in this function, post Scatter load
+* it will default to its original value(E.g.: SystemCoreClock)
+*/
+/* This function can be implemented by the application to initialize the board */
+__weak int Board_Init(void)
+{
+ /* Do nothing */
+ return 0;
+}
+
+/* This function is called just before control is transferred to main().
+ *
+ * You may over-ride this function in your program by defining a custom
+ * SystemInit(), but care should be taken to reproduce the initialization
+ * steps or a non-functional system may result.
+ */
+__weak void SystemInit(void)
+{
+ /* Copy trim information from shadow registers into power manager registers */
+ /* NOTE: Checks have been added to prevent bad/missing trim values from being loaded */
+ if ((MXC_FLC->ctrl & MXC_F_FLC_CTRL_INFO_BLOCK_VALID) &&
+ (MXC_TRIM->for_pwr_reg5 != 0xffffffff) &&
+ (MXC_TRIM->for_pwr_reg6 != 0xffffffff)) {
+ MXC_PWRSEQ->reg5 = MXC_TRIM->for_pwr_reg5;
+ MXC_PWRSEQ->reg6 = MXC_TRIM->for_pwr_reg6;
+ } else {
+ /* No valid info block, use some reasonable defaults */
+ MXC_PWRSEQ->reg6 &= ~MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF;
+ MXC_PWRSEQ->reg6 |= (0x1e0 << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS);
+ }
+
+ /* Improve flash access timing */
+ MXC_FLC->perform |= (MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS |
+ MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT |
+ MXC_F_FLC_PERFORM_AUTO_TACC |
+ MXC_F_FLC_PERFORM_AUTO_CLKDIV);
+
+ /* First, eliminate the unnecessary RTC handshake between clock domains. Must be set as a pair. */
+ MXC_RTCTMR->ctrl |= (MXC_F_RTC_CTRL_USE_ASYNC_FLAGS |
+ MXC_F_RTC_CTRL_AGGRESSIVE_RST);
+ /* Enable fast read of the RTC timer value, and fast write of all other RTC registers */
+ MXC_PWRSEQ->rtc_ctrl2 |= (MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE |
+ MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR);
+
+ MXC_PWRSEQ->rtc_ctrl2 &= ~(MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD);
+
+ /* Clear the GPIO WUD event if not waking up from LP0 */
+ /* this is necessary because WUD flops come up in undetermined state out of POR or SRST*/
+ if(MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ||
+ !(MXC_PWRMAN->pwr_rst_ctrl & MXC_F_PWRMAN_PWR_RST_CTRL_POR)) {
+ /* Clear GPIO WUD event and configuration registers, globally */
+ MXC_PWRSEQ->reg1 |= (MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH |
+ MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
+ MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH |
+ MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
+ } else {
+ /* Unfreeze the GPIO by clearing MBUS_GATE, when returning from LP0 */
+ MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE);
+ /* LP0 wake-up: Turn off special switch to eliminate ~50nA of leakage on VDD12 */
+ MXC_PWRSEQ->reg1 &= ~MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW;
+ }
+
+ /* Turn on retention regulator */
+ MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN |
+ MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP);
+
+ /* Adjust settings in the retention controller for fastest wake-up time */
+ MXC_PWRSEQ->retn_ctrl0 |= (MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY |
+ MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH);
+ MXC_PWRSEQ->retn_ctrl0 &= ~(MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK);
+
+
+ /* Set retention controller TWake cycle count to 1us to minimize the wake-up time */
+ /* NOTE: flash polling (...PWRSEQ_RETN_CTRL0_RC_POLL_FLASH) must be enabled before changing POR default! */
+ MXC_PWRSEQ->retn_ctrl1 = (MXC_PWRSEQ->retn_ctrl1 & ~MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK) |
+ (1 << MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS);
+
+ /* Improve wake-up time by changing ROSEL to 140ns */
+ MXC_PWRSEQ->reg3 = (1 << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS) |
+ (1 << MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS) |
+ (MXC_PWRSEQ->reg3 & ~(MXC_F_PWRSEQ_REG3_PWR_ROSEL |
+ MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL));
+
+ /* Enable RTOS Mode: Enable 32kHz clock synchronizer to SysTick external clock input */
+ MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE;
+
+ /* Set this so all bits of PWR_MSK_FLAGS are active low to mask the corresponding flags */
+ MXC_PWRSEQ->pwr_misc |= MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS;
+
+ /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */
+ /* Grant full access, per "Table B3-24 CPACR bit assignments". */
+ /* DDI0403D "ARMv7-M Architecture Reference Manual" */
+ SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
+ __DSB();
+ __ISB();
+
+ /* Perform an initial trim of the internal ring oscillator */
+ CLKMAN_TrimRO();
+
+ SystemCoreClockUpdate();
+ Board_Init();
+
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/system_max32625.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32625/system_max32625.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,76 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#ifndef _SYSTEM_MAX32625_H_
+#define _SYSTEM_MAX32625_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#ifndef HFXIN_FREQ
+#define HFXIN_FREQ 8000000
+#endif
+
+#ifndef RO_FREQ
+#define RO_FREQ 96000000
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/*
+ * Initialize the system
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit(void);
+
+/*
+ * Update SystemCoreClock variable
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_MAX32625_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/tmr_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32625/tmr_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,296 @@
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_TMR_REGS_H_
+#define _MXC_TMR_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+///@cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+///@endcond
+
+/**
+ * @defgroup tmr_registers Timer Registers
+ * @ingroup tmr
+ * @brief Hardware interface definitions for the Timer Peripheral.
+ * @details Definitions for the Hardware Access Layer of the Timer
+ * Peripherals. Includes:
+ * - Registers
+ * - Fields
+ * - Positions
+ * - Values
+ * - Masks
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/**
+ * Structure type to access the Timer Registers, see #MXC_TMR_GET_TMR(i) to get a pointer to the Timer[i] register structure.
+ */
+typedef struct {
+ __IO uint32_t ctrl; /**< <tt>\b 0x0000</tt> - TMR_CTRL Register - Timer Control Register */
+ __IO uint32_t count32; /**< <tt>\b 0x0004</tt> - TMR_COUNT32 Register - Timer [32 bit] Current Count Value */
+ __IO uint32_t term_cnt32; /**< <tt>\b 0x0008</tt> - TMR_TERM_CNT32 Register - Timer [32 bit] Terminal Count Setting */
+ __IO uint32_t pwm_cap32; /**< <tt>\b 0x000C</tt> - TMR_PWM_CAP32 Register - Timer [32 bit] PWM Compare Setting or Capture/Measure Value */
+ __IO uint32_t count16_0; /**< <tt>\b 0x0010</tt> - TMR_COUNT16_0 Register - Timer [16 bit] Current Count Value, 16-bit Timer 0 */
+ __IO uint32_t term_cnt16_0; /**< <tt>\b 0x0014</tt> - TMR_TERM_CNT16_0 Register - Timer [16 bit] Terminal Count Setting, 16-bit Timer 0 */
+ __IO uint32_t count16_1; /**< <tt>\b 0x0018</tt> - TMR_COUNT16_1 Register - Timer [16 bit] Current Count Value, 16-bit Timer 1 */
+ __IO uint32_t term_cnt16_1; /**< <tt>\b 0x001C</tt> - TMR_TERM_CNT16_1 Register - Timer [16 bit] Terminal Count Setting, 16-bit Timer 1 */
+ __IO uint32_t intfl; /**< <tt>\b 0x0020</tt> - TMR_INTFL Register - Timer Interrupt Flags */
+ __IO uint32_t inten; /**< <tt>\b 0x0024</tt> - TMR_INTEN Register - Timer Interrupt Enable/Disable Settings */
+} mxc_tmr_regs_t;
+/**@} end of group tmr_registers. */
+
+
+/*
+ Register offsets for module TMR.
+*/
+/**
+ * @defgroup TMR_Register_Offsets Register Offsets
+ * @ingroup tmr_registers
+ * @brief Timer Register Offsets from the Timer[n] Base Peripheral Address, where n is between 0 and #MXC_CFG_TMR_INSTANCES for the \MXIM_Device. Use #MXC_TMR_GET_BASE(i) to get the base address for a specific timer number.
+ * @{
+ */
+#define MXC_R_TMR_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from TMR[n] Base Address: TMR_CTRL : <tt>\b 0x0x0000 </tt> */
+#define MXC_R_TMR_OFFS_COUNT32 ((uint32_t)0x00000004UL) /**< Offset from TMR[n] Base Address: TMR_COUNT32 : <tt>\b 0x0x0004 </tt> */
+#define MXC_R_TMR_OFFS_TERM_CNT32 ((uint32_t)0x00000008UL) /**< Offset from TMR[n] Base Address: TMR_TERM_CNT32 : <tt>\b 0x0x0008 </tt> */
+#define MXC_R_TMR_OFFS_PWM_CAP32 ((uint32_t)0x0000000CUL) /**< Offset from TMR[n] Base Address: TMR_PWM_CAP32 : <tt>\b 0x0x000C </tt> */
+#define MXC_R_TMR_OFFS_COUNT16_0 ((uint32_t)0x00000010UL) /**< Offset from TMR[n] Base Address: TMR_COUNT16_0 : <tt>\b 0x0x0010 </tt> */
+#define MXC_R_TMR_OFFS_TERM_CNT16_0 ((uint32_t)0x00000014UL) /**< Offset from TMR[n] Base Address: TMR_TERM_CNT16_0 : <tt>\b 0x0x0014 </tt> */
+#define MXC_R_TMR_OFFS_COUNT16_1 ((uint32_t)0x00000018UL) /**< Offset from TMR[n] Base Address: TMR_COUNT16_1 : <tt>\b 0x0x0018 </tt> */
+#define MXC_R_TMR_OFFS_TERM_CNT16_1 ((uint32_t)0x0000001CUL) /**< Offset from TMR[n] Base Address: TMR_TERM_CNT16_1 : <tt>\b 0x0x001C </tt> */
+#define MXC_R_TMR_OFFS_INTFL ((uint32_t)0x00000020UL) /**< Offset from TMR[n] Base Address: TMR_INTFL : <tt>\b 0x0x0020 </tt> */
+#define MXC_R_TMR_OFFS_INTEN ((uint32_t)0x00000024UL) /**< Offset from TMR[n] Base Address: TMR_INTEN : <tt>\b 0x0x0024 </tt> */
+/**@} end of group TMR_Register_Offsets */
+
+/**
+ * @defgroup TMR_CTRL_Register TMR_CTRL Register
+ * @ingroup tmr_registers
+ * @brief Field Positions and Bit Masks for the TMR_CTRL register
+ * @{
+ */
+#define MXC_F_TMR_CTRL_MODE_POS 0 /**< MODE Field Position for 32-bit timer if TMR2X16 Field is 0 (Default) */
+#define MXC_F_TMR_CTRL_MODE ((uint32_t)(0x00000007UL << MXC_F_TMR_CTRL_MODE_POS)) /**< MODE Field Shifted Position for 32-bit timer if TMR2X16 Field is 0 (Default) */
+#define MXC_F_TMR_CTRL_TMR2X16_POS 3 /**< TMR2X16 Field Position */
+#define MXC_F_TMR_CTRL_TMR2X16 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_TMR2X16_POS)) /**< TMR2X16 Field Shifted Position */
+#define MXC_F_TMR_CTRL_PRESCALE_POS 4 /**< PRESCALE Field Position */
+#define MXC_F_TMR_CTRL_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< PRESCALE Field Shifted Position */
+#define MXC_F_TMR_CTRL_POLARITY_POS 8 /**< POLARITY Field Position */
+#define MXC_F_TMR_CTRL_POLARITY ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_POLARITY_POS)) /**< POLARITY Field Shifted Position */
+#define MXC_F_TMR_CTRL_ENABLE0_POS 12 /**< ENABLE0 Field Position */
+#define MXC_F_TMR_CTRL_ENABLE0 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE0_POS)) /**< ENABLE0 Field Shifted Position */
+#define MXC_F_TMR_CTRL_ENABLE1_POS 13 /**< ENABLE1 Field Position */
+#define MXC_F_TMR_CTRL_ENABLE1 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE1_POS)) /**< ENABLE1 Field Shifted Position */
+/**@} end of group TMR_CTRL */
+
+/**
+ * @defgroup TMR_COUNT16_0_Register TMR_COUNT16_0 Register
+ * @ingroup tmr_registers
+ * @brief Field Positions and Bit Masks for the TMR_COUNT16_0 register. This field indicates the current count value of the <b> 16-bit Timer 0 </b> instance.
+ * @{
+ */
+#define MXC_F_TMR_COUNT16_0_VALUE_POS 0 /**< VALUE Field Position for the 16-bit timer 0 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
+#define MXC_F_TMR_COUNT16_0_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_0_VALUE_POS)) /**< VALUE Field Mask for the 16-bit timer 0 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
+/**@} end of group TMR_COUNT16_0 */
+
+/**
+ * @defgroup TMR_TERM_CNT16_0_Register TMR_TERM_CNT16_0 Register
+ * @ingroup tmr_registers
+ * @brief Field Positions and Bit Masks for the TMR_TERM_CNT16_0 register. This field indicates the termination count value for the <b> 16-bit Timer 0 </b> instance if the Timer is set to 2 16-bit Timers.
+ * @{
+ */
+#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS 0 /**< TERM_COUNT Field Position for the 16-bit timer 0 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
+#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS)) /**< TERM_COUNT Field Mask for the 16-bit timer 0 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
+/**@} end of group TMR_TERM_CNT16_0 */
+
+/**
+ * @defgroup TMR_COUNT16_1__Register _TMR_COUNT16_1_ Register
+ * @ingroup tmr_registers
+ * @brief Field Positions and Bit Masks for the _TMR_COUNT16_1_ register. This field indicates the current count value of the <b> 16-bit Timer 0 </b> instance.
+ * @{
+ */
+#define MXC_F_TMR_COUNT16_1_VALUE_POS 0 /**< VALUE Field Position for the 16-bit timer 1 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
+#define MXC_F_TMR_COUNT16_1_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_1_VALUE_POS)) /**< VALUE Field Mask for the 16-bit timer 1 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
+/**@} end of group TMR_COUNT16_1 */
+
+/**
+ * @defgroup TMR_TERM_CNT16_1_Register TMR_TERM_CNT16_1 Register
+ * @ingroup tmr_registers
+ * @brief Field Positions and Bit Masks for the TMR_TERM_CNT16_1 register. This field indicates the termination count value for the <b> 16-bit Timer 1 </b> instance if the Timer is set to 2 16-bit Timers.
+ * @{
+ */
+#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS 0 /**< TERM_COUNT Field Position for the 16-bit timer 1 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
+#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS)) /**< TERM_COUNT Field Mask for the 16-bit timer 1 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
+/**@} end of group TMR_TERM_CNT16_1 */
+
+/**
+ * @defgroup TMR_INTFL_Register TMR_INTFL Register
+ * @ingroup tmr_registers
+ * @brief Field Positions and Bit Masks for the TMR_INTFL register. This register includes the interrupt flags for both <b> 16-bit Timer 0 and 16-bit Timer 1</b>.
+ * @{
+ */
+#define MXC_F_TMR_INTFL_TIMER0_POS 0 /**< TIMER0 Interrupt Flag Field Position */
+#define MXC_F_TMR_INTFL_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER0_POS)) /**< TIMER0 Interrupt Flag Shifted Field */
+#define MXC_F_TMR_INTFL_TIMER1_POS 1 /**< TIMER1 Interrupt Flag Field Position */
+#define MXC_F_TMR_INTFL_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER1_POS)) /**< TIMER1 Interrupt Flag Shifted Field */
+/**@} end of group TMR_INTFL */
+
+/**
+ * @defgroup TMR_INTEN_Register TMR_INTEN Register
+ * @ingroup tmr_registers
+ * @brief Field Positions and Bit Masks for the TMR_INTEN register. This register includes the interrupt enable bits for both <b> 16-bit Timer 0 and 16-bit Timer 1</b>.
+ * @{
+ */
+#define MXC_F_TMR_INTEN_TIMER0_POS 0 /**< TIMER0 Interrupt Enable Field Position */
+#define MXC_F_TMR_INTEN_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER0_POS)) /**< TIMER0 Interrupt Enable Shifted Field */
+#define MXC_F_TMR_INTEN_TIMER1_POS 1 /**< TIMER1 Interrupt Enable Field Position */
+#define MXC_F_TMR_INTEN_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER1_POS)) /**< TIMER1 Interrupt Enable Shifted Field */
+/**@} end of group TMR_INTEN */
+
+
+
+/*
+ Field values and shifted values for module TMR.
+*/
+/**
+ * @defgroup TMR_CTRL_field_values TMR_CTRL Field and Shifted Field Values
+ * @ingroup TMR_CTRL_Register
+ * @brief Field values and Shifted Field values for the TMR_CTRL register. Shifted field values are field values shifted to the loacation of the field in the register.
+ */
+/**
+ * @defgroup TMR_CTRL_MODE_Field Mode Field for 32-bit Timer Operation.
+ * @ingroup TMR_CTRL_field_values
+ * @brief This field is used to select the timer mode for a 32-bit timer.
+ * @details The mode field is used to set the 32-bit timer instance to one of the supported modes, e.g. 1-Shot, Continuous, etc.
+ * @note If the 32-bit timer is set to operate as 2 16-bit timers, see @ref TMR_CTRL_MODE_16_Field.
+ * @{
+ */
+#define MXC_V_TMR_CTRL_MODE_ONE_SHOT ((uint32_t)(0x00000000UL)) /**< Field value to set a 32-bit Timer to 1-Shot Timer mode. */
+#define MXC_V_TMR_CTRL_MODE_CONTINUOUS ((uint32_t)(0x00000001UL)) /**< Field value to set a 32-bit Timer to continuous mode. */
+#define MXC_V_TMR_CTRL_MODE_COUNTER ((uint32_t)(0x00000002UL)) /**< Field value to set a 32-bit Timer to counter mode. */
+#define MXC_V_TMR_CTRL_MODE_PWM ((uint32_t)(0x00000003UL)) /**< Field value to set a 32-bit Timer to pulse-width mode. */
+#define MXC_V_TMR_CTRL_MODE_CAPTURE ((uint32_t)(0x00000004UL)) /**< Field value to set a 32-bit Timer to capture mode. */
+#define MXC_V_TMR_CTRL_MODE_COMPARE ((uint32_t)(0x00000005UL)) /**< Field value to set a 32-bit Timer to compare mode. */
+#define MXC_V_TMR_CTRL_MODE_GATED ((uint32_t)(0x00000006UL)) /**< Field value to set a 32-bit Timer to gated mode. */
+#define MXC_V_TMR_CTRL_MODE_MEASURE ((uint32_t)(0x00000007UL)) /**< Field value to set a 32-bit Timer to measurement mode. */
+
+#define MXC_S_TMR_CTRL_MODE_ONE_SHOT ((uint32_t)(MXC_V_TMR_CTRL_MODE_ONE_SHOT << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to 1-Shot Timer mode. */
+#define MXC_S_TMR_CTRL_MODE_CONTINUOUS ((uint32_t)(MXC_V_TMR_CTRL_MODE_CONTINUOUS << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to continuous mode. */
+#define MXC_S_TMR_CTRL_MODE_COUNTER ((uint32_t)(MXC_V_TMR_CTRL_MODE_COUNTER << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to counter mode. */
+#define MXC_S_TMR_CTRL_MODE_PWM ((uint32_t)(MXC_V_TMR_CTRL_MODE_PWM << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to pulse-width mode. */
+#define MXC_S_TMR_CTRL_MODE_CAPTURE ((uint32_t)(MXC_V_TMR_CTRL_MODE_CAPTURE << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to capture mode. */
+#define MXC_S_TMR_CTRL_MODE_COMPARE ((uint32_t)(MXC_V_TMR_CTRL_MODE_COMPARE << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to compare mode. */
+#define MXC_S_TMR_CTRL_MODE_GATED ((uint32_t)(MXC_V_TMR_CTRL_MODE_GATED << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to gated mode. */
+#define MXC_S_TMR_CTRL_MODE_MEASURE ((uint32_t)(MXC_V_TMR_CTRL_MODE_MEASURE << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to measurement mode. */
+/**@} end of group TMR_CTRL_MODE_Field */
+/**
+ * @defgroup TMR_CTRL_MODE_16_Field 16-bit Timer Mode Field and Shifted Field Values.
+ * @ingroup TMR_CTRL_field_values
+ * @brief This field is used to select the timer mode when the timer is set to a dual 16-bit timer. The mode field is used to set the 16-bit timer instance to one of the supported modes, e.g. 1-Shot, Continuous, etc.
+ * @{
+ */
+#define MXC_F_TMR_CTRL_MODE_16_0_POS 0
+#define MXC_F_TMR_CTRL_MODE_16_0 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_MODE_16_0_POS))
+
+#define MXC_F_TMR_CTRL_MODE_16_1_POS 1
+#define MXC_F_TMR_CTRL_MODE_16_1 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_MODE_16_1_POS))
+/**@} end of group TMR_CTRL_MODE_16_Field */
+
+/**
+ * @defgroup TMR_CTRL_PRESCALE_Field Prescale Divide Selection Field and Shifted Field Values.
+ * @ingroup TMR_CTRL_field_values
+ * @brief Timer Clock Prescaler divide values and shifted values. The Prescale Divide field is used to scale the timer instance peripheral clock by the specified value.
+ * @{
+ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1 ((uint32_t)(0x00000000UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{0}= 1 \f$ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2 ((uint32_t)(0x00000001UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{1}= 2 \f$ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4 ((uint32_t)(0x00000002UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{2}= 4 \f$ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_8 ((uint32_t)(0x00000003UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{3}= 8 \f$ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_16 ((uint32_t)(0x00000004UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{4}= 16\f$ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_32 ((uint32_t)(0x00000005UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{5}= 32 \f$ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_64 ((uint32_t)(0x00000006UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{6}= 64 \f$ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_128 ((uint32_t)(0x00000007UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{7}= 128 \f$ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_256 ((uint32_t)(0x00000008UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{8}= 256 \f$ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_512 ((uint32_t)(0x00000009UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{9}= 512 \f$ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 ((uint32_t)(0x0000000AUL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{10} = 1024 \f$ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 ((uint32_t)(0x0000000BUL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{11} = 2048 \f$ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 ((uint32_t)(0x0000000CUL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{12} = 4096 \f$ */
+
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_1 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{0}= 1 \f$ */
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_2 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{1}= 2 \f$ */
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_4 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{2}= 4 \f$ */
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_8 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_8 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{3}= 8 \f$ */
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_16 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_16 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{4}= 16 \f$ */
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_32 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_32 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{5}= 32 \f$ */
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_64 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_64 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{6}= 64 \f$ */
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_128 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_128 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{7}= 128 \f$ */
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_256 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_256 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{8}= 256 \f$ */
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_512 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_512 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{9}= 512 \f$ */
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{10} = 1024 \f$ */
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{11} = 2048 \f$ */
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{12} = 4096 \f$ */
+/**@} end of group TMR_CTRL_PRESCALE_Field */
+
+
+/*
+ * These two 1-bit fields replace the standard 3-bit mode field when the associated TMR module
+ * is in dual 16-bit timer mode.
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_TMR_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/trim_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32625/trim_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,125 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_TRIM_REGS_H_
+#define _MXC_TRIM_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __R uint32_t rsv000[10]; /* 0x0000-0x0024 */
+ __IO uint32_t reg10_mem_size; /* 0x0028 Shadow Trim for Flash and SRAM Memory Size */
+ __IO uint32_t reg11_adc_trim0; /* 0x002C Shadow Trim for ADC R0 */
+ __IO uint32_t reg12_adc_trim1; /* 0x0030 Shadow Trim for ADC R1 */
+ __IO uint32_t for_pwr_reg5; /* 0x0034 Shadow Trim for PWRSEQ Register REG5 */
+ __IO uint32_t for_pwr_reg6; /* 0x0038 Shadow Trim for PWRSEQ Register REG6 */
+ __IO uint32_t for_pwr_reg7; /* 0x003C Shadow Trim for PWRSEQ Register REG7 */
+} mxc_trim_regs_t;
+
+
+/*
+ Register offsets for module TRIM.
+*/
+
+#define MXC_R_TRIM_OFFS_REG10_MEM_SIZE ((uint32_t)0x00000028UL)
+#define MXC_R_TRIM_OFFS_REG11_ADC_TRIM0 ((uint32_t)0x0000002CUL)
+#define MXC_R_TRIM_OFFS_REG12_ADC_TRIM1 ((uint32_t)0x00000030UL)
+#define MXC_R_TRIM_OFFS_FOR_PWR_REG5 ((uint32_t)0x00000034UL)
+#define MXC_R_TRIM_OFFS_FOR_PWR_REG6 ((uint32_t)0x00000038UL)
+#define MXC_R_TRIM_OFFS_FOR_PWR_REG7 ((uint32_t)0x0000003CUL)
+
+
+/*
+ Field positions and masks for module TRIM.
+*/
+
+#define MXC_F_TRIM_REG10_MEM_SIZE_SRAM_POS 0
+#define MXC_F_TRIM_REG10_MEM_SIZE_SRAM ((uint32_t)(0x00000003UL << MXC_F_TRIM_REG10_MEM_SIZE_SRAM_POS))
+#define MXC_F_TRIM_REG10_MEM_SIZE_FLASH_POS 2
+#define MXC_F_TRIM_REG10_MEM_SIZE_FLASH ((uint32_t)(0x00000007UL << MXC_F_TRIM_REG10_MEM_SIZE_FLASH_POS))
+
+#define MXC_V_TRIM_REG10_MEM_SRAM_FULL_SIZE ((uint32_t)(0x00000000UL))
+#define MXC_V_TRIM_REG10_MEM_SRAM_THREE_FOURTHS_SIZE ((uint32_t)(0x00000001UL))
+#define MXC_V_TRIM_REG10_MEM_SRAM_HALF_SIZE ((uint32_t)(0x00000002UL))
+
+#define MXC_V_TRIM_REG10_MEM_FLASH_FULL_SIZE ((uint32_t)(0x00000000UL))
+#define MXC_V_TRIM_REG10_MEM_FLASH_THREE_FOURTHS_SIZE ((uint32_t)(0x00000001UL))
+#define MXC_V_TRIM_REG10_MEM_FLASH_HALF_SIZE ((uint32_t)(0x00000002UL))
+#define MXC_V_TRIM_REG10_MEM_FLASH_THREE_EIGHTHS_SIZE ((uint32_t)(0x00000003UL))
+#define MXC_V_TRIM_REG10_MEM_FLASH_FOURTH_SIZE ((uint32_t)(0x00000004UL))
+
+#define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0_POS 0
+#define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0_POS))
+#define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0_POS 16
+#define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0_POS))
+
+#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1_POS 0
+#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1_POS))
+#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1_POS 16
+#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1_POS))
+#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC_POS 28
+#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC ((uint32_t)(0x0000000FUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_TRIM_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/uart.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32625/uart.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,380 @@
+/* CMSIS-DAP Interface Firmware
+ * Copyright (c) 2009-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+#include "max32625.h"
+#include "IO_Config.h"
+#include "clkman_regs.h"
+#include "ioman_regs.h"
+#include "gpio_regs.h"
+#include "uart_regs.h"
+#include "pwrman_regs.h"
+#include "uart.h"
+
+// Size must be 2^n
+#define BUFFER_SIZE (4096)
+
+#define UART_ERRORS (MXC_F_UART_INTFL_RX_FRAMING_ERR | \
+ MXC_F_UART_INTFL_RX_PARITY_ERR | \
+ MXC_F_UART_INTFL_RX_FIFO_OVERFLOW)
+
+
+// Track bit rate to avoid calculation from bus clock, clock scaler and baud divisor values
+static uint32_t baudrate;
+
+static mxc_uart_regs_t *CdcAcmUart = NULL;
+static mxc_uart_fifo_regs_t *CdcAcmUartFifo = NULL;
+static IRQn_Type CdcAcmUartIrqNumber = MXC_IRQ_EXT_COUNT;
+
+static struct {
+ uint8_t data[BUFFER_SIZE];
+ volatile uint16_t idx_in;
+ volatile uint16_t idx_out;
+ volatile int16_t cnt_in;
+ volatile int16_t cnt_out;
+} write_buffer, read_buffer;
+
+/******************************************************************************/
+static void set_bitrate(uint32_t bps)
+{
+ uint32_t baud_divisor;
+
+ baud_divisor = SystemCoreClock / (1 << (MXC_CLKMAN->sys_clk_ctrl_8_uart - 1));
+ baud_divisor /= (bps * 16);
+ CdcAcmUart->baud = baud_divisor;
+
+ baudrate = bps;
+}
+
+/******************************************************************************/
+int32_t uart_set_instance(uint32_t inst)
+{
+ if (inst == 0) {
+ CdcAcmUart = MXC_UART0;
+ CdcAcmUartFifo = MXC_UART0_FIFO;
+ CdcAcmUartIrqNumber = UART0_IRQn;
+ } else if (inst == 2) {
+ CdcAcmUart = MXC_UART2;
+ CdcAcmUartFifo = MXC_UART2_FIFO;
+ CdcAcmUartIrqNumber = UART2_IRQn;
+ } else {
+ return 0;
+ }
+ return 1;
+}
+
+/******************************************************************************/
+int32_t uart_initialize(void)
+{
+ int idx;
+
+ if (CdcAcmUart == MXC_UART0) {
+ MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER;
+ if (MXC_CLKMAN->sys_clk_ctrl_8_uart != MXC_S_CLKMAN_CLK_SCALE_DIV_4) {
+ MXC_CLKMAN->sys_clk_ctrl_8_uart = MXC_S_CLKMAN_CLK_SCALE_DIV_4;
+ }
+
+ // Configure GPIO for UART
+ MXC_IOMAN->uart0_req = ((MXC_V_IOMAN_MAP_A << MXC_F_IOMAN_UART0_REQ_IO_MAP_POS) | MXC_F_IOMAN_UART0_REQ_IO_REQ);
+ while (MXC_IOMAN->uart0_ack != ((MXC_V_IOMAN_MAP_A << MXC_F_IOMAN_UART0_REQ_IO_MAP_POS) | MXC_F_IOMAN_UART0_REQ_IO_REQ));
+
+ } else if (CdcAcmUart == MXC_UART2) {
+ MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER;
+ if (MXC_CLKMAN->sys_clk_ctrl_8_uart != MXC_S_CLKMAN_CLK_SCALE_DIV_4) {
+ MXC_CLKMAN->sys_clk_ctrl_8_uart = MXC_S_CLKMAN_CLK_SCALE_DIV_4;
+ }
+
+ // Configure GPIO for UART
+ MXC_IOMAN->uart2_req = ((MXC_V_IOMAN_MAP_A << MXC_F_IOMAN_UART2_REQ_IO_MAP_POS) | MXC_F_IOMAN_UART2_REQ_IO_REQ);
+ while (MXC_IOMAN->uart2_ack != ((MXC_V_IOMAN_MAP_A << MXC_F_IOMAN_UART2_REQ_IO_MAP_POS) | MXC_F_IOMAN_UART2_REQ_IO_REQ));
+ } else {
+ return 0;
+ }
+
+ idx = MXC_UART_GET_IDX(CdcAcmUart);
+ MXC_PWRMAN->peripheral_reset |= (MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 << idx);
+ MXC_PWRMAN->peripheral_reset &= ~((MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 << idx));
+
+ // Flush RX and TX FIFOS
+ CdcAcmUart->ctrl &= ~(MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN);
+
+ // Disable interrupts
+ CdcAcmUart->inten = 0;
+ CdcAcmUart->intfl = CdcAcmUart->intfl;
+
+ // Set the parity, size, stop and flow configuration
+ CdcAcmUart->ctrl |= (MXC_S_UART_CTRL_DATA_SIZE_8_BITS | MXC_S_UART_CTRL_PARITY_DISABLE);
+
+ // Set receive fifo threshold to 0
+ CdcAcmUart->rx_fifo_ctrl &= ~MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL;
+ CdcAcmUart->rx_fifo_ctrl |= (0 << MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS);
+
+ // Enable receive and transmit fifos
+ CdcAcmUart->ctrl |= (MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN);
+
+ NVIC_EnableIRQ(CdcAcmUartIrqNumber);
+
+ // Set transmit almost empty level to three-quarters of the fifo size
+ CdcAcmUart->tx_fifo_ctrl &= ~MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL;
+ CdcAcmUart->tx_fifo_ctrl |= (MXC_UART_FIFO_DEPTH - (MXC_UART_FIFO_DEPTH >> 2)) << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS;
+
+ // Enable RX and TX interrupts
+ CdcAcmUart->inten = (MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY | MXC_F_UART_INTFL_RX_FIFO_OVERFLOW | MXC_F_UART_INTEN_TX_FIFO_AE);
+
+ // Enable UART
+ CdcAcmUart->ctrl |= MXC_F_UART_CTRL_UART_EN;
+
+ return 1;
+}
+
+/******************************************************************************/
+int32_t uart_uninitialize(void)
+{
+ // Disable UART
+ CdcAcmUart->ctrl &= ~MXC_F_UART_CTRL_UART_EN;
+
+ // Disable interrupts
+ CdcAcmUart->inten = 0;
+ NVIC_DisableIRQ(CdcAcmUartIrqNumber);
+
+ // Clear buffers
+ memset(&write_buffer, 0, sizeof(write_buffer));
+ memset(&read_buffer, 0, sizeof(read_buffer));
+
+ return 1;
+}
+
+/******************************************************************************/
+void uart_set_control_line_state(uint16_t ctrl_bmp)
+{
+}
+
+/******************************************************************************/
+int32_t uart_reset(void)
+{
+ // Clear buffers
+ memset(&write_buffer, 0, sizeof(write_buffer));
+ memset(&read_buffer, 0, sizeof(read_buffer));
+
+ return 1;
+}
+
+/******************************************************************************/
+int32_t uart_set_configuration(UART_Configuration *config)
+{
+ uint32_t ctrl;
+
+ // Get current configuration; clearing parameters that may be configured here
+ ctrl = CdcAcmUart->ctrl & ~(MXC_F_UART_CTRL_PARITY |
+ MXC_F_UART_CTRL_DATA_SIZE |
+ MXC_F_UART_CTRL_EXTRA_STOP |
+ MXC_F_UART_CTRL_CTS_EN |
+ MXC_F_UART_CTRL_RTS_EN);
+
+ switch (config->Parity) {
+ case UART_PARITY_NONE: break;
+ case UART_PARITY_ODD: ctrl |= MXC_S_UART_CTRL_PARITY_ODD;
+ case UART_PARITY_EVEN: ctrl |= MXC_S_UART_CTRL_PARITY_EVEN;
+ case UART_PARITY_MARK: return 0;
+ case UART_PARITY_SPACE: return 0;
+ }
+
+ switch (config->DataBits) {
+ case UART_DATA_BITS_5: ctrl |= MXC_S_UART_CTRL_DATA_SIZE_5_BITS; break;
+ case UART_DATA_BITS_6: ctrl |= MXC_S_UART_CTRL_DATA_SIZE_6_BITS; break;
+ case UART_DATA_BITS_7: ctrl |= MXC_S_UART_CTRL_DATA_SIZE_7_BITS; break;
+ case UART_DATA_BITS_8: ctrl |= MXC_S_UART_CTRL_DATA_SIZE_8_BITS; break;
+ case UART_DATA_BITS_16: return 0;
+ }
+
+ switch (config->StopBits) {
+ case UART_STOP_BITS_1: break;
+ case UART_STOP_BITS_1_5:
+ case UART_STOP_BITS_2: ctrl |= MXC_F_UART_CTRL_EXTRA_STOP; break;
+ }
+
+ switch (config->FlowControl) {
+ case UART_FLOW_CONTROL_NONE: break;
+ case UART_FLOW_CONTROL_RTS_CTS: return 0;
+ case UART_FLOW_CONTROL_XON_XOFF: return 0;
+ }
+
+ set_bitrate(config->Baudrate);
+
+ // Set the new configuration
+ CdcAcmUart->ctrl = ctrl;
+
+ return 1;
+}
+
+/******************************************************************************/
+int32_t uart_get_configuration(UART_Configuration *config)
+{
+ uint32_t ctrl;
+
+ // Capture current configuration
+ ctrl = CdcAcmUart->ctrl;
+
+ if (!(ctrl & MXC_S_UART_CTRL_PARITY_DISABLE)) {
+ config->Parity = UART_PARITY_NONE;
+ } else if (ctrl & MXC_S_UART_CTRL_PARITY_ODD) {
+ config->Parity = UART_PARITY_ODD;
+ } else {
+ // Note both EVEN and MARK parity are captured here
+ config->Parity = UART_PARITY_EVEN;
+ }
+
+ switch (ctrl & MXC_F_UART_CTRL_DATA_SIZE) {
+ case MXC_S_UART_CTRL_DATA_SIZE_5_BITS: config->DataBits = UART_DATA_BITS_5; break;
+ case MXC_S_UART_CTRL_DATA_SIZE_6_BITS: config->DataBits = UART_DATA_BITS_6; break;
+ case MXC_S_UART_CTRL_DATA_SIZE_7_BITS: config->DataBits = UART_DATA_BITS_7; break;
+ case MXC_S_UART_CTRL_DATA_SIZE_8_BITS: config->DataBits = UART_DATA_BITS_8; break;
+ }
+
+ if (!(ctrl & MXC_F_UART_CTRL_EXTRA_STOP)) {
+ config->StopBits = UART_STOP_BITS_1;
+ } else {
+ config->StopBits = UART_STOP_BITS_2;
+ }
+
+ if ((ctrl & (MXC_F_UART_CTRL_CTS_EN | MXC_F_UART_CTRL_RTS_EN)) == (MXC_F_UART_CTRL_CTS_EN | MXC_F_UART_CTRL_RTS_EN)) {
+ config->FlowControl = UART_FLOW_CONTROL_RTS_CTS;
+ } else {
+ // Not true if only one of ...CST_EN and ...RTS_EN are asserted
+ config->FlowControl = UART_FLOW_CONTROL_NONE;
+ }
+
+ config->Baudrate = baudrate;
+
+ return 1;
+}
+
+/******************************************************************************/
+int32_t uart_write_free(void)
+{
+ return BUFFER_SIZE - (write_buffer.cnt_in - write_buffer.cnt_out);
+}
+
+/******************************************************************************/
+int32_t uart_write_data(uint8_t *data, uint16_t size)
+{
+ uint16_t xfer_count = size;
+
+ if (write_buffer.cnt_in == write_buffer.cnt_out) {
+ while ((((CdcAcmUart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) < MXC_UART_FIFO_DEPTH) &&
+ (xfer_count > 0)) {
+
+ NVIC_DisableIRQ(CdcAcmUartIrqNumber);
+ CdcAcmUart->intfl = MXC_F_UART_INTFL_TX_FIFO_AE;
+ CdcAcmUartFifo->tx = *data++;
+ xfer_count--;
+ NVIC_EnableIRQ(CdcAcmUartIrqNumber);
+
+ }
+ }
+
+ while (xfer_count > 0) {
+ if ((write_buffer.cnt_in - write_buffer.cnt_out) < BUFFER_SIZE) {
+
+ NVIC_DisableIRQ(CdcAcmUartIrqNumber);
+ write_buffer.data[write_buffer.idx_in++] = *data++;
+ write_buffer.idx_in &= (BUFFER_SIZE - 1);
+ write_buffer.cnt_in++;
+ xfer_count--;
+ NVIC_EnableIRQ(CdcAcmUartIrqNumber);
+
+ } else {
+ break;
+ }
+ }
+ return size - xfer_count;
+}
+
+/******************************************************************************/
+int32_t uart_read_data(uint8_t *data, uint16_t size)
+{
+ int32_t cnt;
+
+ for (cnt = 0; (cnt < size) && (read_buffer.cnt_in != read_buffer.cnt_out); cnt++) {
+ *data++ = read_buffer.data[read_buffer.idx_out++];
+ read_buffer.idx_out &= (BUFFER_SIZE - 1);
+ read_buffer.cnt_out++;
+ }
+
+ return cnt;
+}
+
+/******************************************************************************/
+void UART_IRQHandler(void)
+{
+ // Capture interrupt flag state at entry
+ uint32_t intfl = CdcAcmUart->intfl;
+ // Clear interrupts that will be serviced
+ CdcAcmUart->intfl = intfl;
+
+ if (intfl & MXC_F_UART_INTFL_RX_FIFO_OVERFLOW) {
+ read_buffer.data[read_buffer.idx_in++] = '*';
+ read_buffer.idx_in &= (BUFFER_SIZE - 1);
+ read_buffer.cnt_in++;
+ }
+
+ if (intfl & (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS)) {
+ while ((CdcAcmUart->rx_fifo_ctrl & MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY) &&
+ ((read_buffer.cnt_in - read_buffer.cnt_out) < BUFFER_SIZE)) {
+ read_buffer.data[read_buffer.idx_in++] = CdcAcmUartFifo->rx;
+ CdcAcmUart->intfl = MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY;
+ read_buffer.idx_in &= (BUFFER_SIZE - 1);
+ read_buffer.cnt_in++;
+ }
+ if (((read_buffer.cnt_in - read_buffer.cnt_out) >= BUFFER_SIZE)) {
+ read_buffer.data[read_buffer.idx_in++] = '%';
+ read_buffer.idx_in &= (BUFFER_SIZE - 1);
+ read_buffer.cnt_in++;
+ }
+ }
+
+ if (intfl & MXC_F_UART_INTFL_TX_FIFO_AE) {
+ /*
+ Transfer data from write buffer to transmit FIFO if
+ a) write buffer contains data and
+ b) transmit FIFO is not full
+ */
+ while ((write_buffer.cnt_out != write_buffer.cnt_in) &&
+ (((CdcAcmUart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) < MXC_UART_FIFO_DEPTH)) {
+ CdcAcmUartFifo->tx = write_buffer.data[write_buffer.idx_out++];
+ write_buffer.idx_out &= (BUFFER_SIZE - 1);
+ write_buffer.cnt_out++;
+ }
+ }
+}
+
+/******************************************************************************/
+void UART0_IRQHandler(void)
+{
+ UART_IRQHandler();
+}
+
+/******************************************************************************/
+void UART1_IRQHandler(void)
+{
+ UART_IRQHandler();
+}
+
+/******************************************************************************/
+void UART2_IRQHandler(void)
+{
+ UART_IRQHandler();
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/uart_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32625/uart_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,259 @@
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_UART_REGS_H_
+#define _MXC_UART_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+///@cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+///@endcond
+
+/**
+ * @defgroup uart_registers UART Registers
+ * @brief Registers, Bit Masks and Bit Positions
+ * @ingroup uart_comm
+ * @{
+ */
+
+/**
+ * Structure type for the UART peripheral registers allowing direct 32-bit access to each register.
+ */
+typedef struct {
+ __IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> UART_CTRL Register - UART Control Register. */
+ __IO uint32_t baud; /**< <tt>\b 0x0004:</tt> UART_BAUD Register - UART Baud Control Register. */
+ __IO uint32_t tx_fifo_ctrl; /**< <tt>\b 0x0008:</tt> UART_TX_FIFO_CTRL Register - UART TX FIFO Control Register. */
+ __IO uint32_t rx_fifo_ctrl; /**< <tt>\b 0x000C:</tt> UART_RX_FIFO_CTRL Register - UART RX FIFO Control Register. */
+ __IO uint32_t md_ctrl; /**< <tt>\b 0x0010:</tt> UART_MD_CTRL Register - UART Multidrop Control Register. */
+ __IO uint32_t intfl; /**< <tt>\b 0x0014:</tt> UART_INTFL Register - UART Interrupt Flags. */
+ __IO uint32_t inten; /**< <tt>\b 0x0018:</tt> UART_INTEN Register - UART Interrupt Enable/Disable Control. */
+#if (MXC_UART_REV > 0)
+ __R uint32_t idle; /**< <tt>\b 0x001C:</tt> UART_IDLE Register - UART Idle Status */
+#endif
+} mxc_uart_regs_t;
+/**@} end of group uart_registers */
+
+/**
+ * @defgroup uart_fifos UART TX and RX FIFOs
+ * @brief TX and RX FIFO access for reads and writes using 8-bit, 16-bit and 32-bit data types.
+ * @ingroup uart_registers
+ * @{
+ */
+/**
+ * Structure type for accessing the UART Transmit and Receive FIFOs.
+ */
+typedef struct {
+ union {
+ __IO uint8_t tx; /**< TX FIFO write point for data to transmit. */
+ __IO uint8_t tx_8[2048]; /**< 8-bit access to TX FIFO. */
+ __IO uint16_t tx_16[1024]; /**< 16-bit access to TX FIFO. */
+ __IO uint32_t tx_32[512]; /**< 32-bit access to TX FIFO. */
+ };
+ union {
+ __IO uint8_t rx; /**< RX FIFO read point for received data. */
+ __IO uint8_t rx_8[2048]; /**< 8-bit access to RX FIFO. */
+ __IO uint16_t rx_16[1024]; /**< 16-bit access to RX FIFO. */
+ __IO uint32_t rx_32[512]; /**< 32-bit access to RX FIFO. */
+ };
+} mxc_uart_fifo_regs_t;
+/**@} end of group uart_fifos */
+
+/*
+ Register offsets for module UART.
+*/
+
+#define MXC_R_UART_OFFS_CTRL ((uint32_t)0x00000000UL)
+#define MXC_R_UART_OFFS_BAUD ((uint32_t)0x00000004UL)
+#define MXC_R_UART_OFFS_TX_FIFO_CTRL ((uint32_t)0x00000008UL)
+#define MXC_R_UART_OFFS_RX_FIFO_CTRL ((uint32_t)0x0000000CUL)
+#define MXC_R_UART_OFFS_MD_CTRL ((uint32_t)0x00000010UL)
+#define MXC_R_UART_OFFS_INTFL ((uint32_t)0x00000014UL)
+#define MXC_R_UART_OFFS_INTEN ((uint32_t)0x00000018UL)
+#define MXC_R_UART_FIFO_OFFS_TX ((uint32_t)0x00000000UL)
+#define MXC_R_UART_FIFO_OFFS_RX ((uint32_t)0x00000800UL)
+
+
+/*
+ Field positions and masks for module UART.
+*/
+
+#define MXC_F_UART_CTRL_UART_EN_POS 0
+#define MXC_F_UART_CTRL_UART_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_UART_EN_POS))
+#define MXC_F_UART_CTRL_RX_FIFO_EN_POS 1
+#define MXC_F_UART_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RX_FIFO_EN_POS))
+#define MXC_F_UART_CTRL_TX_FIFO_EN_POS 2
+#define MXC_F_UART_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_TX_FIFO_EN_POS))
+#define MXC_F_UART_CTRL_DATA_SIZE_POS 4
+#define MXC_F_UART_CTRL_DATA_SIZE ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_DATA_SIZE_POS))
+#define MXC_F_UART_CTRL_EXTRA_STOP_POS 8
+#define MXC_F_UART_CTRL_EXTRA_STOP ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_EXTRA_STOP_POS))
+#define MXC_F_UART_CTRL_PARITY_POS 12
+#define MXC_F_UART_CTRL_PARITY ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_PARITY_POS))
+#define MXC_F_UART_CTRL_CTS_EN_POS 16
+#define MXC_F_UART_CTRL_CTS_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_CTS_EN_POS))
+#define MXC_F_UART_CTRL_CTS_POLARITY_POS 17
+#define MXC_F_UART_CTRL_CTS_POLARITY ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_CTS_POLARITY_POS))
+#define MXC_F_UART_CTRL_RTS_EN_POS 18
+#define MXC_F_UART_CTRL_RTS_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RTS_EN_POS))
+#define MXC_F_UART_CTRL_RTS_POLARITY_POS 19
+#define MXC_F_UART_CTRL_RTS_POLARITY ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RTS_POLARITY_POS))
+#define MXC_F_UART_CTRL_RTS_LEVEL_POS 20
+#define MXC_F_UART_CTRL_RTS_LEVEL ((uint32_t)(0x0000003FUL << MXC_F_UART_CTRL_RTS_LEVEL_POS))
+
+#define MXC_F_UART_BAUD_BAUD_DIVISOR_POS 0
+#define MXC_F_UART_BAUD_BAUD_DIVISOR ((uint32_t)(0x000000FFUL << MXC_F_UART_BAUD_BAUD_DIVISOR_POS))
+#define MXC_F_UART_BAUD_BAUD_MODE_POS 8
+#define MXC_F_UART_BAUD_BAUD_MODE ((uint32_t)(0x00000003UL << MXC_F_UART_BAUD_BAUD_MODE_POS))
+
+#define MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS 0
+#define MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY ((uint32_t)(0x0000001FUL << MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS))
+#define MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS 16
+#define MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL ((uint32_t)(0x0000001FUL << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS))
+
+#define MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY_POS 0
+#define MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY ((uint32_t)(0x0000001FUL << MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY_POS))
+#define MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS 16
+#define MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS))
+
+#define MXC_F_UART_MD_CTRL_SLAVE_ADDR_POS 0
+#define MXC_F_UART_MD_CTRL_SLAVE_ADDR ((uint32_t)(0x000000FFUL << MXC_F_UART_MD_CTRL_SLAVE_ADDR_POS))
+#define MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK_POS 8
+#define MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK ((uint32_t)(0x000000FFUL << MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK_POS))
+#define MXC_F_UART_MD_CTRL_MD_MSTR_POS 16
+#define MXC_F_UART_MD_CTRL_MD_MSTR ((uint32_t)(0x00000001UL << MXC_F_UART_MD_CTRL_MD_MSTR_POS))
+#define MXC_F_UART_MD_CTRL_TX_ADDR_MARK_POS 17
+#define MXC_F_UART_MD_CTRL_TX_ADDR_MARK ((uint32_t)(0x00000001UL << MXC_F_UART_MD_CTRL_TX_ADDR_MARK_POS))
+
+/**
+ * @defgroup UART_INTFL_Register UART_INTFL
+ * @ingroup uart_registers
+ * @{
+ */
+#define MXC_F_UART_INTFL_TX_DONE_POS 0
+#define MXC_F_UART_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_DONE_POS))
+#define MXC_F_UART_INTFL_TX_UNSTALLED_POS 1
+#define MXC_F_UART_INTFL_TX_UNSTALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_UNSTALLED_POS))
+#define MXC_F_UART_INTFL_TX_FIFO_AE_POS 2
+#define MXC_F_UART_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_FIFO_AE_POS))
+#define MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY_POS 3
+#define MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY_POS))
+#define MXC_F_UART_INTFL_RX_STALLED_POS 4
+#define MXC_F_UART_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_STALLED_POS))
+#define MXC_F_UART_INTFL_RX_FIFO_AF_POS 5
+#define MXC_F_UART_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_AF_POS))
+#define MXC_F_UART_INTFL_RX_FIFO_OVERFLOW_POS 6
+#define MXC_F_UART_INTFL_RX_FIFO_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_OVERFLOW_POS))
+#define MXC_F_UART_INTFL_RX_FRAMING_ERR_POS 7
+#define MXC_F_UART_INTFL_RX_FRAMING_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FRAMING_ERR_POS))
+#define MXC_F_UART_INTFL_RX_PARITY_ERR_POS 8
+#define MXC_F_UART_INTFL_RX_PARITY_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_PARITY_ERR_POS))
+/**@} end of group UART_INTFL_Register */
+
+#define MXC_F_UART_INTEN_TX_DONE_POS 0
+#define MXC_F_UART_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_DONE_POS))
+#define MXC_F_UART_INTEN_TX_UNSTALLED_POS 1
+#define MXC_F_UART_INTEN_TX_UNSTALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_UNSTALLED_POS))
+#define MXC_F_UART_INTEN_TX_FIFO_AE_POS 2
+#define MXC_F_UART_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_FIFO_AE_POS))
+#define MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY_POS 3
+#define MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY_POS))
+#define MXC_F_UART_INTEN_RX_STALLED_POS 4
+#define MXC_F_UART_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_STALLED_POS))
+#define MXC_F_UART_INTEN_RX_FIFO_AF_POS 5
+#define MXC_F_UART_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_AF_POS))
+#define MXC_F_UART_INTEN_RX_FIFO_OVERFLOW_POS 6
+#define MXC_F_UART_INTEN_RX_FIFO_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_OVERFLOW_POS))
+#define MXC_F_UART_INTEN_RX_FRAMING_ERR_POS 7
+#define MXC_F_UART_INTEN_RX_FRAMING_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FRAMING_ERR_POS))
+#define MXC_F_UART_INTEN_RX_PARITY_ERR_POS 8
+#define MXC_F_UART_INTEN_RX_PARITY_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_PARITY_ERR_POS))
+
+#if (MXC_UART_REV > 0)
+#define MXC_F_UART_IDLE_TX_RX_IDLE_POS 0
+#define MXC_F_UART_IDLE_TX_RX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_TX_RX_IDLE_POS))
+#define MXC_F_UART_IDLE_TX_IDLE_POS 1
+#define MXC_F_UART_IDLE_TX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_TX_IDLE_POS))
+#define MXC_F_UART_IDLE_RX_IDLE_POS 2
+#define MXC_F_UART_IDLE_RX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_RX_IDLE_POS))
+#endif
+
+/*
+ Field values and shifted values for module UART.
+*/
+
+#define MXC_V_UART_CTRL_DATA_SIZE_5_BITS ((uint32_t)(0x00000000UL))
+#define MXC_V_UART_CTRL_DATA_SIZE_6_BITS ((uint32_t)(0x00000001UL))
+#define MXC_V_UART_CTRL_DATA_SIZE_7_BITS ((uint32_t)(0x00000002UL))
+#define MXC_V_UART_CTRL_DATA_SIZE_8_BITS ((uint32_t)(0x00000003UL))
+
+#define MXC_S_UART_CTRL_DATA_SIZE_5_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_5_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
+#define MXC_S_UART_CTRL_DATA_SIZE_6_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_6_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
+#define MXC_S_UART_CTRL_DATA_SIZE_7_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_7_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
+#define MXC_S_UART_CTRL_DATA_SIZE_8_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_8_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
+
+#define MXC_V_UART_CTRL_PARITY_DISABLE ((uint32_t)(0x00000000UL))
+#define MXC_V_UART_CTRL_PARITY_ODD ((uint32_t)(0x00000001UL))
+#define MXC_V_UART_CTRL_PARITY_EVEN ((uint32_t)(0x00000002UL))
+#define MXC_V_UART_CTRL_PARITY_MARK ((uint32_t)(0x00000003UL))
+
+#define MXC_S_UART_CTRL_PARITY_DISABLE ((uint32_t)(MXC_V_UART_CTRL_PARITY_DISABLE << MXC_F_UART_CTRL_PARITY_POS))
+#define MXC_S_UART_CTRL_PARITY_ODD ((uint32_t)(MXC_V_UART_CTRL_PARITY_ODD << MXC_F_UART_CTRL_PARITY_POS))
+#define MXC_S_UART_CTRL_PARITY_EVEN ((uint32_t)(MXC_V_UART_CTRL_PARITY_EVEN << MXC_F_UART_CTRL_PARITY_POS))
+#define MXC_S_UART_CTRL_PARITY_MARK ((uint32_t)(MXC_V_UART_CTRL_PARITY_MARK << MXC_F_UART_CTRL_PARITY_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_UART_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/usb_buf.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/maxim/max32625/usb_buf.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,26 @@ +/* CMSIS-DAP Interface Firmware + * Copyright (c) 2009-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef USB_BUF_H +#define USB_BUF_H + +#include <stdint.h> + +#define USB_MSC_BUF_SIZE (512) + +__attribute__ ((aligned (64))) +uint32_t usb_buffer[USB_MSC_BUF_SIZE/4]; + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/usb_config.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/maxim/max32625/usb_config.c Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,558 @@ +/* CMSIS-DAP Interface Firmware + * Copyright (c) 2009-2019 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "util.h" + +/*------------------------------------------------------------------------------ + * USB Device Configuration + *----------------------------------------------------------------------------*/ + +// <e> USB Device +// <i> Enable the USB Device functionality +#define USBD_ENABLE 1 +#define USBD_RTX_CORE_STACK 0 +#define USBD_RTX_DEVICE_STACK 0 +#define USBD_RTX_ENDPOINT0_STACK 0 + +// <o0.0> High-speed +// <i> Enable high-speed functionality (if device supports it) +#define USBD_HS_ENABLE 0 +#if (defined(WEBUSB_INTERFACE) || defined(WINUSB_INTERFACE) || defined(BULK_ENDPOINT)) +#define USBD_BOS_ENABLE 1 +#else +#define USBD_BOS_ENABLE 0 +#endif +// <h> Device Settings +// <i> These settings affect Device Descriptor +// <o0> Power +// <i> Default Power Setting +// <0=> Bus-powered +// <1=> Self-powered +// <o1> Max Endpoint 0 Packet Size +// <i> Maximum packet size for endpoint zero (bMaxPacketSize0) +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes +// <o2.0..15> Vendor ID <0x0000-0xFFFF> +// <i> Vendor ID assigned by the USB-IF (idVendor) +// <o3.0..15> Product ID <0x0000-0xFFFF> +// <i> Product ID assigned by the manufacturer (idProduct) +// <o4.0..15> Device Release Number <0x0000-0xFFFF> +// <i> Device release number in binary-coded decimal (bcdDevice) +// </h> +#define USBD_POWER 0 +#define USBD_MAX_PACKET0 64 +#define USBD_DEVDESC_IDVENDOR 0x0D28 +#define USBD_DEVDESC_IDPRODUCT 0x0204 +#define USBD_DEVDESC_BCDDEVICE 0x1000 //was 0x0100 + +// <h> Configuration Settings +// <i> These settings affect Configuration Descriptor +// <o0.5> Remote Wakeup +// <i> Configuration support for remote wakeup (D5: of bmAttributes) +// <o1.0..7> Maximum Power Consumption (in mA) <0-510><#/2> +// <i> Maximum power consumption of the USB device +// <i> from the bus in this specific configuration +// <i> when the device is fully operational (bMaxPower) +// </h> +#define USBD_CFGDESC_BMATTRIBUTES 0x80 +#define USBD_CFGDESC_BMAXPOWER 0xFA + +// <h> String Settings +// <i> These settings affect String Descriptor +// <o0.0..15> Language ID <0x0000-0xFCFF> +// <i> English (United States) = 0x0409 +// <s0.126> Manufacturer String +// <i> String descriptor describing manufacturer +// <s1.126> Product String +// <i> String descriptor describing product +// <e1.0> Serial Number +// <i> Enable serial number string +// <i> If disabled serial number string will not be assigned to the USB Device +// <s2.126> Serial Number String +// <i> String descriptor describing device's serial number +// </e> +// </h> +#define USBD_STRDESC_LANGID 0x0409 +#define USBD_STRDESC_MAN L"ARM" +#ifndef USB_PROD_STR +#define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" +#else +#define _TOWIDE(x) L ## #x +#define TOWIDE(x) _TOWIDE(x) +#define USBD_STRDESC_PROD TOWIDE(USB_PROD_STR) +#endif +#define USBD_STRDESC_SER_ENABLE 1 +#define USBD_STRDESC_SER L"0001A0000000" + +// <e0> Class Support +// <i> Enables USB Device Class specific Requests +#define USBD_CLASS_ENABLE 1 + +// <e0.0> Human Interface Device (HID) +// <i> Enable class support for Human Interface Device (HID) +// <h> Interrupt Endpoint Settings +// <o1.0..4> Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o2.0..4> Interrupt Out Endpoint Number <0=> Not used <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <i> If interrupt out endpoint is not used select "Not used" +// <h> Endpoint Settings +// <o3.0..7> Maximum Endpoint Packet Size (in bytes) <0-64> +// <o4.0..7> Endpoint polling Interval (in ms) <1-255> +// <e5> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o6.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o6.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// <o7.0..7> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// </e> +// </h> +// </h> +// <h> Human Interface Device Settings +// <i> Device specific settings +// <s0.126> HID Interface String +// <o8.0..4> Number of Input Reports <1-32> +// <o9.0..4> Number of Output Reports <1-32> +// <o10.0..15> Maximum Input Report Size (in bytes) <1-65535> +// <o11.0..15> Maximum Output Report Size (in bytes) <1-65535> +// <o12.0..15> Maximum Feature Report Size (in bytes) <1-65535> +// </h> +// </e> +#ifndef HID_ENDPOINT +#define HID_ENDPOINT 0 +#else +#define HID_ENDPOINT 1 +#endif + +#ifndef WEBUSB_INTERFACE +#define WEBUSB_INTERFACE 0 +#else +#define WEBUSB_INTERFACE 1 +#endif + +#define USBD_HID_ENABLE HID_ENDPOINT +#ifndef BULK_ENDPOINT //check if bulk endpoint is not enabled +#define USBD_HID_EP_INTIN 1 +#define USBD_HID_EP_INTOUT 2 +#else //if bulk endpoint is enabled remove interrupt endpoints from the hid +#define USBD_HID_EP_INTIN 0 +#define USBD_HID_EP_INTOUT 0 +#endif +#define USBD_HID_EP_INTIN_STACK 0 +#define USBD_HID_WMAXPACKETSIZE 64 +#define USBD_HID_BINTERVAL 1 +#define USBD_HID_HS_ENABLE 0 +#define USBD_HID_HS_WMAXPACKETSIZE 64 +#define USBD_HID_HS_BINTERVAL 6 +#define USBD_HID_STRDESC L"CMSIS-DAP v1" +#define USBD_WEBUSB_STRDESC L"WebUSB: CMSIS-DAP" +#define USBD_HID_INREPORT_NUM 1 +#define USBD_HID_OUTREPORT_NUM 1 +#define USBD_HID_INREPORT_MAX_SZ 64 +#define USBD_HID_OUTREPORT_MAX_SZ 64 +#define USBD_HID_FEATREPORT_MAX_SZ 1 + +// <e0.0> Mass Storage Device (MSC) +// <i> Enable class support for Mass Storage Device (MSC) +// <h> Bulk Endpoint Settings +// <o1.0..4> Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o2.0..4> Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o3> Maximum Packet Size <1-1024> +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5> Maximum Packet Size <1-1024> +// <o6> Maximum NAK Rate <0-255> +// </e> +// </h> +// </h> +// <h> Mass Storage Device Settings +// <i> Device specific settings +// <s0.126> MSC Interface String +// <h> Inquiry Data +// <s1.8> Vendor Identification +// <s2.16> Product Identification +// <s3.4> Product Revision Level +// </h> +// </h> +// </e> +#ifndef MSC_ENDPOINT +#define MSC_ENDPOINT 0 +#else +#define MSC_ENDPOINT 1 +#endif +#define USBD_MSC_ENABLE MSC_ENDPOINT +#define USBD_MSC_EP_BULKIN 3 +#define USBD_MSC_EP_BULKOUT 4 +#define USBD_MSC_EP_BULKIN_STACK 0 +#define USBD_MSC_WMAXPACKETSIZE 64 +#define USBD_MSC_HS_ENABLE 0 +#define USBD_MSC_HS_WMAXPACKETSIZE 512 +#define USBD_MSC_HS_BINTERVAL 0 +#define USBD_MSC_STRDESC L"USB_MSC" +#define USBD_MSC_INQUIRY_DATA "MBED " \ + "VFS " \ + "0.1" + +// <e0.0> Audio Device (ADC) +// <i> Enable class support for Audio Device (ADC) +// <h> Isochronous Endpoint Settings +// <o1.0..4> Isochronous Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o2.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o3.0..10> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o5.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// </e> +// </h> +// </h> +// <h> Audio Device Settings +// <i> Device specific settings +// <s0.126> Audio Control Interface String +// <s1.126> Audio Streaming (Zero Bandwidth) Interface String +// <s2.126> Audio Streaming (Operational) Interface String +// <o6.0..7> Audio Subframe Size (in bytes) <0-255> +// <o7.0..7> Sample Resolution (in bits) <0-255> +// <o8.0..23> Sample Frequency (in Hz) <0-16777215> +// <o9> Packet Size (in bytes) <1-256> +// <o10> Packet Count <1-16> +// </h> +// </e> +#define USBD_ADC_ENABLE 0 +#define USBD_ADC_EP_ISOOUT 3 +#define USBD_ADC_WMAXPACKETSIZE 64 +#define USBD_ADC_BINTERVAL 1 +#define USBD_ADC_HS_ENABLE 0 +#define USBD_ADC_HS_WMAXPACKETSIZE 64 +#define USBD_ADC_CIF_STRDESC L"USB_ADC" +#define USBD_ADC_SIF1_STRDESC L"USB_ADC1" +#define USBD_ADC_SIF2_STRDESC L"USB_ADC2" +#define USBD_ADC_BSUBFRAMESIZE 2 +#define USBD_ADC_BBITRESOLUTION 16 +#define USBD_ADC_TSAMFREQ 32000 +#define USBD_ADC_CFG_P_S 32 +#define USBD_ADC_CFG_P_C 1 + +// <e0> Communication Device (CDC) - Abstract Control Model (ACM) +// <i> Enable class support for Communication Device (CDC) - Abstract Control Model (ACM) +// <h> Interrupt Endpoint Settings +// <o1.0..4> Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o2.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o3.0..10> Endpoint polling Interval (in ms) <0-255> +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o5.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// <o6.0..10> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// </e4> +// </h> +// </h> +// <h> Bulk Endpoint Settings +// <o7.0..4> Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o8.0..4> Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o9> Maximum Packet Size <1-1024> +// <e10> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o11> Maximum Packet Size <1-1024> +// <o12> Maximum NAK Rate <0-255> +// </e10> +// </h> +// </h> +// <h> Communication Device Settings +// <i> Device specific settings +// <s0.126> Communication Class Interface String +// <s1.126> Data Class Interface String +// <o13> Maximum Communication Device Send Buffer Size +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// <o14> Maximum Communication Device Receive Buffer Size +// <i> Minimum size must be as big as maximum packet size for Bulk Out Endpoint +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// </h> +// </e> +#ifndef CDC_ENDPOINT +#define CDC_ENDPOINT 0 +#else +#define CDC_ENDPOINT 1 +#endif +#define USBD_CDC_ACM_ENABLE CDC_ENDPOINT +#define USBD_CDC_ACM_EP_INTIN 5 +#define USBD_CDC_ACM_EP_INTIN_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE 16 +#define USBD_CDC_ACM_BINTERVAL 32 +#define USBD_CDC_ACM_HS_ENABLE 0 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE 16 +#define USBD_CDC_ACM_HS_BINTERVAL 2 +#define USBD_CDC_ACM_EP_BULKIN 6 +#define USBD_CDC_ACM_EP_BULKOUT 7 +#define USBD_CDC_ACM_EP_BULKIN_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE1 64 +#define USBD_CDC_ACM_HS_ENABLE1 0 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE1 64 +#define USBD_CDC_ACM_HS_BINTERVAL1 0 +#define USBD_CDC_ACM_CIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_DIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_SENDBUF_SIZE 64 +#define USBD_CDC_ACM_RECEIVEBUF_SIZE 64 +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Send Buffer size must be larger or equal to Bulk In maximum packet size!" +#endif +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Receive Buffer size must be larger or equal to Bulk Out maximum packet size!" +#endif + +// <e0> Custom Class Device +// <i> Enables USB Custom Class Requests +// <i> Class IDs: +// <i> 0x00 - Class Reserved ID +// <i> 0x01 - Class Audio ID +// <i> 0x02 - Class Communications ID +// <i> 0x03 - Class Human Interface ID +// <i> 0x04 - Class Monitor ID +// <i> 0x05 - Class Physical Interface ID +// <i> 0x06 - Class Power ID +// <i> 0x07 - Class Printer ID +// <i> 0x08 - Class Storage ID +// <i> 0x09 - Class HUB ID +// <i> 0xEF - Class Miscellaneous ID +// <i> 0xFF - Class Vendor Specific ID +// </e> +#define USBD_CLS_ENABLE 0 + +// WebUSB support +#define USBD_WEBUSB_ENABLE WEBUSB_INTERFACE +#define USBD_WEBUSB_VENDOR_CODE 0x21 +#define USBD_WEBUSB_LANDING_URL "os.mbed.com/webusb/landing-page/?bid=" +#define USBD_WEBUSB_ORIGIN_URL "os.mbed.com/" + +// Microsoft OS Descriptors 2.0 (WinUSB) support +#define USBD_WINUSB_ENABLE WINUSB_INTERFACE +#define USBD_WINUSB_VENDOR_CODE 0x20 +// </e> +// </e> + +#ifndef BULK_ENDPOINT +#define BULK_ENDPOINT 0 +#else +#define BULK_ENDPOINT 1 +#endif +#define USBD_BULK_ENABLE BULK_ENDPOINT +#define USBD_BULK_EP_BULKIN 1 +#define USBD_BULK_EP_BULKOUT 2 +#define USBD_BULK_EP_BULKIN_SWO 10 +#define USBD_BULK_WMAXPACKETSIZE 64 +#define USBD_BULK_HS_ENABLE 0 +#define USBD_BULK_HS_WMAXPACKETSIZE 512 +#define USBD_BULK_STRDESC L"CMSIS-DAP v2" + +/* USB Device Calculations ---------------------------------------------------*/ + +#define USBD_IF_NUM_MAX (USBD_BULK_ENABLE+USBD_WEBUSB_ENABLE+USBD_HID_ENABLE+USBD_MSC_ENABLE+(USBD_ADC_ENABLE*2)+(USBD_CDC_ACM_ENABLE*2)+USBD_CLS_ENABLE) +#define USBD_MULTI_IF (USBD_CDC_ACM_ENABLE*(USBD_HID_ENABLE|USBD_MSC_ENABLE|USBD_ADC_ENABLE|USBD_CLS_ENABLE|USBD_WEBUSB_ENABLE|USBD_BULK_ENABLE)) +// #define MAX(x, y) (((x) < (y)) ? (y) : (x)) +#define USBD_EP_NUM_CALC0 MAX((USBD_HID_ENABLE *(USBD_HID_EP_INTIN )), (USBD_HID_ENABLE *(USBD_HID_EP_INTOUT!=0)*(USBD_HID_EP_INTOUT))) +#define USBD_EP_NUM_CALC1 MAX((USBD_MSC_ENABLE *(USBD_MSC_EP_BULKIN )), (USBD_MSC_ENABLE *(USBD_MSC_EP_BULKOUT))) +#define USBD_EP_NUM_CALC2 MAX((USBD_ADC_ENABLE *(USBD_ADC_EP_ISOOUT )), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_INTIN))) +#define USBD_EP_NUM_CALC3 MAX((USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKIN)), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKOUT))) +#define USBD_EP_NUM_CALC4 MAX(USBD_EP_NUM_CALC0, USBD_EP_NUM_CALC1) +#define USBD_EP_NUM_CALC5 MAX(USBD_EP_NUM_CALC2, USBD_EP_NUM_CALC3) +#define USBD_EP_NUM_CALC6 MAX(USBD_EP_NUM_CALC4, USBD_EP_NUM_CALC5) +#define USBD_EP_NUM_CALC7 MAX((USBD_BULK_ENABLE*(USBD_BULK_EP_BULKIN)), (USBD_BULK_ENABLE*(USBD_BULK_EP_BULKOUT))) +#define USBD_EP_NUM MAX(USBD_EP_NUM_CALC6, USBD_EP_NUM_CALC7) + +#if (USBD_EP_NUM > 7) +#error "Max32620 only have 8 individual endpoints including EP0!" +#endif + +#if (USBD_HID_ENABLE) +#if (USBD_MSC_ENABLE) +#if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_MSC_EP_BULKOUT))) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKOUT))) +#error "HID and Mass Storage Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_ADC_ENABLE) +#if ((USBD_HID_EP_INTIN == USBD_ADC_EP_ISOOUT) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_ADC_EP_ISOOUT))) +#error "HID and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (((USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKOUT))|| \ + ((USBD_HID_EP_INTOUT != 0) && \ + ((USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKOUT)))) +#error "HID and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_MSC_ENABLE) +#if (USBD_ADC_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_ADC_EP_ISOOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_ADC_EP_ISOOUT)) +#error "Mass Storage Device and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Mass Storage Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_ADC_ENABLE) +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Audio Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif +#define USBD_ADC_CIF_NUM (0) +#define USBD_ADC_SIF1_NUM (1) +#define USBD_ADC_SIF2_NUM (2) + + +#define USBD_ADC_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+0) +#define USBD_ADC_SIF1_STR_NUM (3+USBD_STRDESC_SER_ENABLE+1) +#define USBD_ADC_SIF2_STR_NUM (3+USBD_STRDESC_SER_ENABLE+2) +#define USBD_CDC_ACM_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+0) +#define USBD_CDC_ACM_DIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+1) +#define USBD_HID_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2) +#define USBD_WEBUSB_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) +#define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) +#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) + +#if (USBD_HID_ENABLE) +#if (USBD_HID_HS_ENABLE) +#define USBD_HID_MAX_PACKET ((USBD_HID_HS_WMAXPACKETSIZE > USBD_HID_WMAXPACKETSIZE) ? USBD_HID_HS_WMAXPACKETSIZE : USBD_HID_WMAXPACKETSIZE) +#else +#define USBD_HID_MAX_PACKET (USBD_HID_WMAXPACKETSIZE) +#endif +#else +#define USBD_HID_MAX_PACKET (0) +#endif +#if (USBD_MSC_ENABLE) +#if (USBD_MSC_HS_ENABLE) +#define USBD_MSC_MAX_PACKET ((USBD_MSC_HS_WMAXPACKETSIZE > USBD_MSC_WMAXPACKETSIZE) ? USBD_MSC_HS_WMAXPACKETSIZE : USBD_MSC_WMAXPACKETSIZE) +#else +#define USBD_MSC_MAX_PACKET (USBD_MSC_WMAXPACKETSIZE) +#endif +#else +#define USBD_MSC_MAX_PACKET (0) +#endif +#if (USBD_ADC_ENABLE) +#if (USBD_ADC_HS_ENABLE) +#define USBD_ADC_MAX_PACKET ((USBD_ADC_HS_WMAXPACKETSIZE > USBD_ADC_WMAXPACKETSIZE) ? USBD_ADC_HS_WMAXPACKETSIZE : USBD_ADC_WMAXPACKETSIZE) +#else +#define USBD_ADC_MAX_PACKET (USBD_ADC_WMAXPACKETSIZE) +#endif +#else +#define USBD_ADC_MAX_PACKET (0) +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (USBD_CDC_ACM_HS_ENABLE) +#define USBD_CDC_ACM_MAX_PACKET ((USBD_CDC_ACM_HS_WMAXPACKETSIZE > USBD_CDC_ACM_WMAXPACKETSIZE) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE : USBD_CDC_ACM_WMAXPACKETSIZE) +#else +#define USBD_CDC_ACM_MAX_PACKET (USBD_CDC_ACM_WMAXPACKETSIZE) +#endif +#if (USBD_CDC_ACM_HS_ENABLE1) +#define USBD_CDC_ACM_MAX_PACKET1 ((USBD_CDC_ACM_HS_WMAXPACKETSIZE1 > USBD_CDC_ACM_WMAXPACKETSIZE1) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE1 : USBD_CDC_ACM_WMAXPACKETSIZE1) +#else +#define USBD_CDC_ACM_MAX_PACKET1 (USBD_CDC_ACM_WMAXPACKETSIZE1) +#endif +#else +#define USBD_CDC_ACM_MAX_PACKET (0) +#define USBD_CDC_ACM_MAX_PACKET1 (0) +#endif + +#if (USBD_BULK_ENABLE) +#if (USBD_BULK_HS_ENABLE) +#define USBD_BULK_MAX_PACKET ((USBD_BULK_HS_WMAXPACKETSIZE > USBD_BULK_WMAXPACKETSIZE) ? USBD_BULK_HS_WMAXPACKETSIZE : USBD_BULK_WMAXPACKETSIZE) +#else +#define USBD_BULK_MAX_PACKET (USBD_BULK_WMAXPACKETSIZE) +#endif +#else +#define USBD_BULK_MAX_PACKET (0) +#endif + +#define USBD_MAX_PACKET_CALC0 ((USBD_HID_MAX_PACKET > USBD_HID_MAX_PACKET ) ? (USBD_HID_MAX_PACKET ) : (USBD_HID_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC1 ((USBD_ADC_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET ) ? (USBD_ADC_MAX_PACKET ) : (USBD_CDC_ACM_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC2 ((USBD_MAX_PACKET_CALC0 > USBD_MAX_PACKET_CALC1 ) ? (USBD_MAX_PACKET_CALC0) : (USBD_MAX_PACKET_CALC1 )) +#define USBD_MAX_PACKET_CALC3 ((USBD_BULK_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET1 ) ? (USBD_BULK_MAX_PACKET) : (USBD_CDC_ACM_MAX_PACKET1 )) +#define USBD_MAX_PACKET ((USBD_MAX_PACKET_CALC3 > USBD_MAX_PACKET_CALC2 ) ? (USBD_MAX_PACKET_CALC3) : (USBD_MAX_PACKET_CALC2 )) + + +/*------------------------------------------------------------------------------ + * USB Config Functions + *----------------------------------------------------------------------------*/ + +#ifndef __USB_CONFIG___ +#define __USB_CONFIG__ + +#ifndef __NO_USB_LIB_C +#include "usb_lib.c" +#endif + +#endif /* __USB_CONFIG__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/usb_regs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32625/usb_regs.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,293 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_USB_REGS_H_
+#define _MXC_USB_REGS_H_
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+
+
+#define MXC_V_USB_EP_DIR_DISABLE ((uint32_t)0x00000000UL)
+#define MXC_V_USB_EP_DIR_OUT ((uint32_t)0x00000001UL)
+#define MXC_V_USB_EP_DIR_IN ((uint32_t)0x00000002UL)
+#define MXC_V_USB_EP_DIR_CONTROL ((uint32_t)0x00000003UL)
+
+#define MXC_S_USB_EP_DIR_DISABLE (MXC_V_USB_EP_DIR_DISABLE << MXC_F_USB_EP_DIR_POS)
+#define MXC_S_USB_EP_DIR_OUT (MXC_V_USB_EP_DIR_OUT << MXC_F_USB_EP_DIR_POS)
+#define MXC_S_USB_EP_DIR_IN (MXC_V_USB_EP_DIR_IN << MXC_F_USB_EP_DIR_POS)
+#define MXC_S_USB_EP_DIR_CONTROL (MXC_V_USB_EP_DIR_CONTROL << MXC_F_USB_EP_DIR_POS)
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __IO uint32_t cn; /* 0x0000 USB Control Register */
+ __R uint32_t rsv004[127]; /* 0x0004-0x01FC */
+ __IO uint32_t dev_addr; /* 0x0200 USB Device Address Register */
+ __IO uint32_t dev_cn; /* 0x0204 USB Device Control Register */
+ __IO uint32_t dev_intfl; /* 0x0208 USB Device Interrupt */
+ __IO uint32_t dev_inten; /* 0x020C USB Device Interrupt Enable */
+ __R uint32_t rsv210[4]; /* 0x0210-0x021C */
+ __IO uint32_t ep_base; /* 0x0220 USB Endpoint Descriptor Table Base Address */
+ __IO uint32_t cur_buf; /* 0x0224 USB Current Endpoint Buffer Register */
+ __IO uint32_t in_owner; /* 0x0228 USB IN Endpoint Buffer Owner Register */
+ __IO uint32_t out_owner; /* 0x022C USB OUT Endpoint Buffer Owner Register */
+ __IO uint32_t in_int; /* 0x0230 USB IN Endpoint Buffer Available Interrupt */
+ __IO uint32_t out_int; /* 0x0234 USB OUT Endpoint Data Available Interrupt */
+ __IO uint32_t nak_int; /* 0x0238 USB IN Endpoint NAK Interrupt */
+ __IO uint32_t dma_err_int; /* 0x023C USB DMA Error Interrupt */
+ __IO uint32_t buf_ovr_int; /* 0x0240 USB Buffer Overflow Interrupt */
+ __R uint32_t rsv244[7]; /* 0x0244-0x025C */
+ __IO uint32_t setup0; /* 0x0260 USB SETUP Packet Bytes 0 to 3 */
+ __IO uint32_t setup1; /* 0x0264 USB SETUP Packet Bytes 4 to 7 */
+ __R uint32_t rsv268[6]; /* 0x0268-0x027C */
+ __IO uint32_t ep[8]; /* 0x0280-0x029C USB Endpoint[n] Control Register */
+} mxc_usb_regs_t;
+
+
+/*
+ Register offsets for module USB.
+*/
+
+#define MXC_R_USB_OFFS_CN ((uint32_t)0x00000000UL)
+#define MXC_R_USB_OFFS_DEV_ADDR ((uint32_t)0x00000200UL)
+#define MXC_R_USB_OFFS_DEV_CN ((uint32_t)0x00000204UL)
+#define MXC_R_USB_OFFS_DEV_INTFL ((uint32_t)0x00000208UL)
+#define MXC_R_USB_OFFS_DEV_INTEN ((uint32_t)0x0000020CUL)
+#define MXC_R_USB_OFFS_EP_BASE ((uint32_t)0x00000220UL)
+#define MXC_R_USB_OFFS_CUR_BUF ((uint32_t)0x00000224UL)
+#define MXC_R_USB_OFFS_IN_OWNER ((uint32_t)0x00000228UL)
+#define MXC_R_USB_OFFS_OUT_OWNER ((uint32_t)0x0000022CUL)
+#define MXC_R_USB_OFFS_IN_INT ((uint32_t)0x00000230UL)
+#define MXC_R_USB_OFFS_OUT_INT ((uint32_t)0x00000234UL)
+#define MXC_R_USB_OFFS_NAK_INT ((uint32_t)0x00000238UL)
+#define MXC_R_USB_OFFS_DMA_ERR_INT ((uint32_t)0x0000023CUL)
+#define MXC_R_USB_OFFS_BUF_OVR_INT ((uint32_t)0x00000240UL)
+#define MXC_R_USB_OFFS_SETUP0 ((uint32_t)0x00000260UL)
+#define MXC_R_USB_OFFS_SETUP1 ((uint32_t)0x00000264UL)
+#define MXC_R_USB_OFFS_EP0 ((uint32_t)0x00000280UL)
+#define MXC_R_USB_OFFS_EP1 ((uint32_t)0x00000284UL)
+#define MXC_R_USB_OFFS_EP2 ((uint32_t)0x00000288UL)
+#define MXC_R_USB_OFFS_EP3 ((uint32_t)0x0000028CUL)
+#define MXC_R_USB_OFFS_EP4 ((uint32_t)0x00000290UL)
+#define MXC_R_USB_OFFS_EP5 ((uint32_t)0x00000294UL)
+#define MXC_R_USB_OFFS_EP6 ((uint32_t)0x00000298UL)
+#define MXC_R_USB_OFFS_EP7 ((uint32_t)0x0000029CUL)
+
+
+/*
+ Field positions and masks for module USB.
+*/
+
+#define MXC_F_USB_CN_USB_EN_POS 0
+#define MXC_F_USB_CN_USB_EN ((uint32_t)(0x00000001UL << MXC_F_USB_CN_USB_EN_POS))
+#define MXC_F_USB_CN_HOST_POS 1
+#define MXC_F_USB_CN_HOST ((uint32_t)(0x00000001UL << MXC_F_USB_CN_HOST_POS))
+
+#define MXC_F_USB_DEV_ADDR_DEV_ADDR_POS 0
+#define MXC_F_USB_DEV_ADDR_DEV_ADDR ((uint32_t)(0x0000007FUL << MXC_F_USB_DEV_ADDR_DEV_ADDR_POS))
+
+#define MXC_F_USB_DEV_CN_SIGRWU_POS 2
+#define MXC_F_USB_DEV_CN_SIGRWU ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_SIGRWU_POS))
+#define MXC_F_USB_DEV_CN_CONNECT_POS 3
+#define MXC_F_USB_DEV_CN_CONNECT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_CONNECT_POS))
+#define MXC_F_USB_DEV_CN_ULPM_POS 4
+#define MXC_F_USB_DEV_CN_ULPM ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_ULPM_POS))
+#define MXC_F_USB_DEV_CN_URST_POS 5
+#define MXC_F_USB_DEV_CN_URST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_URST_POS))
+#define MXC_F_USB_DEV_CN_VBGATE_POS 6
+#define MXC_F_USB_DEV_CN_VBGATE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_VBGATE_POS))
+#define MXC_F_USB_DEV_CN_OSCEN_POS 7
+#define MXC_F_USB_DEV_CN_OSCEN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_OSCEN_POS))
+#define MXC_F_USB_DEV_CN_BACT_OE_POS 8
+#define MXC_F_USB_DEV_CN_BACT_OE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_BACT_OE_POS))
+#define MXC_F_USB_DEV_CN_FIFO_MODE_POS 9
+#define MXC_F_USB_DEV_CN_FIFO_MODE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_FIFO_MODE_POS))
+
+#define MXC_F_USB_DEV_INTFL_DPACT_POS 0
+#define MXC_F_USB_DEV_INTFL_DPACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DPACT_POS))
+#define MXC_F_USB_DEV_INTFL_RWU_DN_POS 1
+#define MXC_F_USB_DEV_INTFL_RWU_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_RWU_DN_POS))
+#define MXC_F_USB_DEV_INTFL_BACT_POS 2
+#define MXC_F_USB_DEV_INTFL_BACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BACT_POS))
+#define MXC_F_USB_DEV_INTFL_BRST_POS 3
+#define MXC_F_USB_DEV_INTFL_BRST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_POS))
+#define MXC_F_USB_DEV_INTFL_SUSP_POS 4
+#define MXC_F_USB_DEV_INTFL_SUSP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SUSP_POS))
+#define MXC_F_USB_DEV_INTFL_NO_VBUS_POS 5
+#define MXC_F_USB_DEV_INTFL_NO_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_NO_VBUS_POS))
+#define MXC_F_USB_DEV_INTFL_VBUS_POS 6
+#define MXC_F_USB_DEV_INTFL_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_POS))
+#define MXC_F_USB_DEV_INTFL_BRST_DN_POS 7
+#define MXC_F_USB_DEV_INTFL_BRST_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_DN_POS))
+#define MXC_F_USB_DEV_INTFL_SETUP_POS 8
+#define MXC_F_USB_DEV_INTFL_SETUP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SETUP_POS))
+#define MXC_F_USB_DEV_INTFL_EP_IN_POS 9
+#define MXC_F_USB_DEV_INTFL_EP_IN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_IN_POS))
+#define MXC_F_USB_DEV_INTFL_EP_OUT_POS 10
+#define MXC_F_USB_DEV_INTFL_EP_OUT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_OUT_POS))
+#define MXC_F_USB_DEV_INTFL_EP_NAK_POS 11
+#define MXC_F_USB_DEV_INTFL_EP_NAK ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_NAK_POS))
+#define MXC_F_USB_DEV_INTFL_DMA_ERR_POS 12
+#define MXC_F_USB_DEV_INTFL_DMA_ERR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DMA_ERR_POS))
+#define MXC_F_USB_DEV_INTFL_BUF_OVR_POS 13
+#define MXC_F_USB_DEV_INTFL_BUF_OVR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BUF_OVR_POS))
+#define MXC_F_USB_DEV_INTFL_VBUS_ST_POS 16
+#define MXC_F_USB_DEV_INTFL_VBUS_ST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_ST_POS))
+
+#define MXC_F_USB_DEV_INTEN_DPACT_POS 0
+#define MXC_F_USB_DEV_INTEN_DPACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DPACT_POS))
+#define MXC_F_USB_DEV_INTEN_RWU_DN_POS 1
+#define MXC_F_USB_DEV_INTEN_RWU_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_RWU_DN_POS))
+#define MXC_F_USB_DEV_INTEN_BACT_POS 2
+#define MXC_F_USB_DEV_INTEN_BACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BACT_POS))
+#define MXC_F_USB_DEV_INTEN_BRST_POS 3
+#define MXC_F_USB_DEV_INTEN_BRST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_POS))
+#define MXC_F_USB_DEV_INTEN_SUSP_POS 4
+#define MXC_F_USB_DEV_INTEN_SUSP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SUSP_POS))
+#define MXC_F_USB_DEV_INTEN_NO_VBUS_POS 5
+#define MXC_F_USB_DEV_INTEN_NO_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_NO_VBUS_POS))
+#define MXC_F_USB_DEV_INTEN_VBUS_POS 6
+#define MXC_F_USB_DEV_INTEN_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_VBUS_POS))
+#define MXC_F_USB_DEV_INTEN_BRST_DN_POS 7
+#define MXC_F_USB_DEV_INTEN_BRST_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_DN_POS))
+#define MXC_F_USB_DEV_INTEN_SETUP_POS 8
+#define MXC_F_USB_DEV_INTEN_SETUP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SETUP_POS))
+#define MXC_F_USB_DEV_INTEN_EP_IN_POS 9
+#define MXC_F_USB_DEV_INTEN_EP_IN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_IN_POS))
+#define MXC_F_USB_DEV_INTEN_EP_OUT_POS 10
+#define MXC_F_USB_DEV_INTEN_EP_OUT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_OUT_POS))
+#define MXC_F_USB_DEV_INTEN_EP_NAK_POS 11
+#define MXC_F_USB_DEV_INTEN_EP_NAK ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_NAK_POS))
+#define MXC_F_USB_DEV_INTEN_DMA_ERR_POS 12
+#define MXC_F_USB_DEV_INTEN_DMA_ERR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DMA_ERR_POS))
+#define MXC_F_USB_DEV_INTEN_BUF_OVR_POS 13
+#define MXC_F_USB_DEV_INTEN_BUF_OVR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BUF_OVR_POS))
+
+#define MXC_F_USB_EP_BASE_EP_BASE_POS 9
+#define MXC_F_USB_EP_BASE_EP_BASE ((uint32_t)(0x007FFFFFUL << MXC_F_USB_EP_BASE_EP_BASE_POS))
+
+#define MXC_F_USB_CUR_BUF_OUT_BUF_POS 0
+#define MXC_F_USB_CUR_BUF_OUT_BUF ((uint32_t)(0x0000FFFFUL << MXC_F_USB_CUR_BUF_OUT_BUF_POS))
+#define MXC_F_USB_CUR_BUF_IN_BUF_POS 16
+#define MXC_F_USB_CUR_BUF_IN_BUF ((uint32_t)(0x0000FFFFUL << MXC_F_USB_CUR_BUF_IN_BUF_POS))
+
+#define MXC_F_USB_IN_OWNER_BUF0_OWNER_POS 0
+#define MXC_F_USB_IN_OWNER_BUF0_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_IN_OWNER_BUF0_OWNER_POS))
+#define MXC_F_USB_IN_OWNER_BUF1_OWNER_POS 16
+#define MXC_F_USB_IN_OWNER_BUF1_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_IN_OWNER_BUF1_OWNER_POS))
+
+#define MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS 0
+#define MXC_F_USB_OUT_OWNER_BUF0_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS))
+#define MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS 16
+#define MXC_F_USB_OUT_OWNER_BUF1_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS))
+
+#define MXC_F_USB_IN_INT_INBAV_POS 0
+#define MXC_F_USB_IN_INT_INBAV ((uint32_t)(0x000000FFUL << MXC_F_USB_IN_INT_INBAV_POS))
+
+#define MXC_F_USB_OUT_INT_OUTDAV_POS 0
+#define MXC_F_USB_OUT_INT_OUTDAV ((uint32_t)(0x000000FFUL << MXC_F_USB_OUT_INT_OUTDAV_POS))
+
+#define MXC_F_USB_NAK_INT_NAK_POS 0
+#define MXC_F_USB_NAK_INT_NAK ((uint32_t)(0x000000FFUL << MXC_F_USB_NAK_INT_NAK_POS))
+
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR_POS 0
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR ((uint32_t)(0x000000FFUL << MXC_F_USB_DMA_ERR_INT_DMA_ERR_POS))
+
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR_POS 0
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR ((uint32_t)(0x000000FFUL << MXC_F_USB_BUF_OVR_INT_BUF_OVR_POS))
+
+#define MXC_F_USB_SETUP0_BYTE0_POS 0
+#define MXC_F_USB_SETUP0_BYTE0 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE0_POS))
+#define MXC_F_USB_SETUP0_BYTE1_POS 8
+#define MXC_F_USB_SETUP0_BYTE1 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE1_POS))
+#define MXC_F_USB_SETUP0_BYTE2_POS 16
+#define MXC_F_USB_SETUP0_BYTE2 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE2_POS))
+#define MXC_F_USB_SETUP0_BYTE3_POS 24
+#define MXC_F_USB_SETUP0_BYTE3 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE3_POS))
+
+#define MXC_F_USB_SETUP1_BYTE0_POS 0
+#define MXC_F_USB_SETUP1_BYTE0 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE0_POS))
+#define MXC_F_USB_SETUP1_BYTE1_POS 8
+#define MXC_F_USB_SETUP1_BYTE1 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE1_POS))
+#define MXC_F_USB_SETUP1_BYTE2_POS 16
+#define MXC_F_USB_SETUP1_BYTE2 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE2_POS))
+#define MXC_F_USB_SETUP1_BYTE3_POS 24
+#define MXC_F_USB_SETUP1_BYTE3 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE3_POS))
+
+#define MXC_F_USB_EP_DIR_POS 0
+#define MXC_F_USB_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP_DIR_POS))
+#define MXC_F_USB_EP_BUF2_POS 3
+#define MXC_F_USB_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP_BUF2_POS))
+#define MXC_F_USB_EP_INT_EN_POS 4
+#define MXC_F_USB_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP_INT_EN_POS))
+#define MXC_F_USB_EP_NAK_EN_POS 5
+#define MXC_F_USB_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP_NAK_EN_POS))
+#define MXC_F_USB_EP_DT_POS 6
+#define MXC_F_USB_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP_DT_POS))
+#define MXC_F_USB_EP_STALL_POS 8
+#define MXC_F_USB_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP_STALL_POS))
+#define MXC_F_USB_EP_ST_STALL_POS 9
+#define MXC_F_USB_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP_ST_STALL_POS))
+#define MXC_F_USB_EP_ST_ACK_POS 10
+#define MXC_F_USB_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP_ST_ACK_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_USB_REGS_H_ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/maxim/max32625/usbd_max32625.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/maxim/max32625/usbd_max32625.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,647 @@
+/* CMSIS-DAP Interface Firmware
+ * Copyright (c) 2009-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+#include "rl_usb.h"
+#include "util.h"
+
+#include "max32625.h"
+#include "usb_regs.h"
+#include "clkman_regs.h"
+#include "pwrman_regs.h"
+#include "tmr_regs.h"
+
+#define __NO_USB_LIB_C
+#include "usb_config.c"
+
+#define EPNUM_MASK (~USB_ENDPOINT_DIRECTION_MASK)
+
+#define INIT_INTS (MXC_F_USB_DEV_INTEN_BRST | MXC_F_USB_DEV_INTFL_BRST_DN | MXC_F_USB_DEV_INTEN_VBUS | MXC_F_USB_DEV_INTFL_NO_VBUS)
+#define CONNECT_INTS (MXC_F_USB_DEV_INTEN_SETUP | MXC_F_USB_DEV_INTEN_EP_IN | MXC_F_USB_DEV_INTEN_EP_OUT | MXC_F_USB_DEV_INTEN_DMA_ERR)
+
+typedef struct {
+ volatile uint32_t buf0_desc;
+ volatile uint32_t buf0_address;
+ volatile uint32_t buf1_desc;
+ volatile uint32_t buf1_address;
+} ep_buffer_t;
+
+typedef struct {
+ ep_buffer_t out_buffer;
+ ep_buffer_t in_buffer;
+} ep0_buffer_t;
+
+typedef struct {
+ ep0_buffer_t ep0;
+ ep_buffer_t ep[MXC_USB_NUM_EP - 1];
+} ep_buffer_descriptor_t;
+
+typedef struct {
+ U8 type;
+ U16 len;
+} ep_info_t;
+
+/* static storage for endpoint buffer descriptor table, must be 512 byte aligned for DMA */
+__attribute__ ((aligned (512)))
+ep_buffer_descriptor_t ep_buffer_descriptor;
+
+static uint32_t ep_buffer[MXC_USB_NUM_EP][MXC_USB_MAX_PACKET / sizeof(uint32_t)];
+static ep_info_t ep_info[MXC_USB_NUM_EP];
+static volatile int suspended;
+static volatile int setup_waiting;
+static volatile int ep0_expect_zlp;
+
+#if CDC_ENDPOINT
+/* CDC-ACM class processes FIFOs in the SOF interrupt. The USB Device interface
+ * of Maxim's microcontrollers does not provide and SOF interrupt. A periodic
+ * timer interrupt is used instead.
+ */
+/******************************************************************************/
+void TMR0_IRQHandler(void)
+{
+ MXC_TMR0->intfl = MXC_TMR0->intfl;
+
+ if (usbd_configured()) {
+ USBD_CDC_ACM_SOF_Event();
+ }
+}
+#endif
+
+/******************************************************************************/
+static ep_buffer_t *get_desc(U32 EPNum)
+{
+ ep_buffer_t *desc;
+
+ if (EPNum == 0x80) {
+ desc = &ep_buffer_descriptor.ep0.in_buffer;
+ } else if (EPNum == 0x00) {
+ desc = &ep_buffer_descriptor.ep0.out_buffer;
+ } else {
+ desc = &ep_buffer_descriptor.ep[(EPNum & EPNUM_MASK) - 1];
+ }
+
+ return desc;
+}
+
+/*
+ * USB Device Interrupt enable
+ * Called by USBD_Init to enable the USB Interrupt
+ * Return Value: None
+ */
+
+void USBD_IntrEna(void)
+{
+ NVIC_EnableIRQ(USB_IRQn); /* Enable OTG interrupt */
+}
+
+/******************************************************************************/
+/*
+ * Usb interrupt enable/disable
+ * Parameters: ena: enable/disable
+ * 0: disable interrupt
+ * 1: enable interrupt
+ */
+#ifdef __RTX
+void __svc(1) USBD_Intr (int ena);
+void __SVC_1 (int ena)
+{
+ if (ena) {
+ NVIC_EnableIRQ(USB_IRQn); /* Enable USB interrupt */
+ } else {
+ NVIC_DisableIRQ(USB_IRQn); /* Disable USB interrupt */
+ }
+}
+#endif
+
+/******************************************************************************/
+static void reset_state(void)
+{
+ unsigned int ep;
+
+ suspended = 0;
+ setup_waiting = 0;
+ ep0_expect_zlp = 0;
+ memset(ep_info, 0, sizeof(ep_info));
+
+ MXC_USB->ep[0] |= (MXC_S_USB_EP_DIR_CONTROL | MXC_F_USB_EP_INT_EN | MXC_F_USB_EP_DT);
+ for (ep = 1; ep < MXC_USB_NUM_EP; ep++) {
+ MXC_USB->ep[ep] = MXC_F_USB_EP_DT;
+ }
+}
+
+/*
+ * USB Device Initialize Function
+ * Called by the User to initialize USB Device
+ * Return Value: None
+ */
+void USBD_Init (void)
+{
+ uint32_t reg;
+
+ /* Enable USB power domain */
+ MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED;
+ /* Setup the USB clocking, select */
+ MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE;
+ /* Force USB clock gater */
+ reg = MXC_CLKMAN->clk_gate_ctrl0;
+ reg &= ~MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER;
+ reg |= (0x2 << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS);
+ MXC_CLKMAN->clk_gate_ctrl0 = reg;
+
+ MXC_USB->cn = 0;
+ MXC_USB->cn = MXC_F_USB_CN_USB_EN;
+ MXC_USB->dev_inten = 0;
+ MXC_USB->dev_intfl = 0xFFFF; // clear interrupts
+ MXC_USB->dev_cn = 0;
+ MXC_USB->dev_cn |= MXC_F_USB_DEV_CN_URST;
+ MXC_USB->dev_cn = 0;
+
+ reset_state();
+
+ /* set the descriptor location */
+ MXC_USB->ep_base = (uint32_t)&ep_buffer_descriptor;
+
+ /* enable some interrupts */
+ MXC_USB->dev_inten = INIT_INTS;
+ NVIC_EnableIRQ(USB_IRQn);
+}
+
+/*
+ * USB Device Connect Function
+ * Called by the User to Connect/Disconnect USB Device
+ * Parameters: con: Connect/Disconnect
+ * Return Value: None
+ */
+void USBD_Connect (BOOL con)
+{
+ if (con) {
+ MXC_USB->dev_intfl = 0xFFFF; // clear interrupts
+ MXC_USB->dev_inten |= CONNECT_INTS;
+ MXC_USB->ep[0] |= MXC_F_USB_EP_INT_EN;
+ MXC_USB->dev_cn |= (MXC_F_USB_DEV_CN_CONNECT | MXC_F_USB_DEV_CN_FIFO_MODE);
+ } else {
+ MXC_USB->dev_inten &= ~CONNECT_INTS;
+ MXC_USB->ep[0] &= ~MXC_F_USB_EP_INT_EN;
+ MXC_USB->dev_cn &= ~MXC_F_USB_DEV_CN_CONNECT;
+ }
+}
+
+/*
+ * USB Device Remote Wakeup Configuration Function
+ * Parameters: cfg: Device Enable/Disable
+ * Return Value: None
+ */
+void USBD_WakeUpCfg (BOOL cfg)
+{
+}
+
+/*
+ * USB Device Set Address Function
+ * Parameters: adr: USB Device Address
+ * Return Value: None
+ */
+void USBD_SetAddress (U32 adr, U32 setup)
+{
+ /* Performed by Hardware */
+}
+
+/*
+ * USB Device Configure Function
+ * Parameters: cfg: Device Configure/Deconfigure
+ * Return Value: None
+ */
+void USBD_Configure (BOOL cfg)
+{
+#if CDC_ENDPOINT
+ /* CDC-ACM class processes FIFOs in the SOF interrupt. The USB Device interface
+ * of Maxim's microcontrollers does not provide and SOF interrupt. A periodic
+ * timer interrupt is used instead.
+ */
+
+ #define SOF_INT_US 1000
+
+ if (cfg) {
+ // Setup timer interrupt for SOF
+ MXC_TMR0->ctrl = MXC_S_TMR_CTRL_MODE_CONTINUOUS;
+ MXC_TMR0->count32 = 0;
+ MXC_TMR0->term_cnt32 = (SystemCoreClock / 1000000) * SOF_INT_US;
+
+ // Enable the interrupt
+ MXC_TMR0->intfl = MXC_TMR0->intfl;
+ NVIC_EnableIRQ(TMR0_0_IRQn);
+ MXC_TMR0->inten = MXC_F_TMR_INTEN_TIMER0;
+
+ // Start the timer
+ MXC_TMR0->ctrl |= MXC_F_TMR_CTRL_ENABLE0;
+
+ } else {
+ // Disable tmr
+ MXC_TMR0->ctrl &= ~(MXC_F_TMR_CTRL_ENABLE0);
+ }
+#endif
+}
+
+/*
+ * Configure USB Device Endpoint according to Descriptor
+ * Parameters: pEPD: Pointer to Device Endpoint Descriptor
+ * Return Value: None
+ */
+void USBD_ConfigEP (USB_ENDPOINT_DESCRIPTOR *pEPD)
+{
+ U32 EPNum;
+
+ EPNum = pEPD->bEndpointAddress & EPNUM_MASK;
+
+ if (EPNum < MXC_USB_NUM_EP) {
+
+ // Clear existing configurations
+ MXC_USB->ep[EPNum] = MXC_F_USB_EP_DT;
+
+ if (pEPD->bEndpointAddress & USB_ENDPOINT_DIRECTION_MASK) {
+ ep_info[EPNum].type = MXC_S_USB_EP_DIR_IN;
+ } else {
+ ep_info[EPNum].type = MXC_S_USB_EP_DIR_OUT;
+ }
+
+ ep_info[EPNum].len = pEPD->wMaxPacketSize;
+ }
+}
+
+/*
+ * Set Direction for USB Device Control Endpoint
+ * Parameters: dir: Out (dir == 0), In (dir <> 0)
+ * Return Value: None
+ */
+void USBD_DirCtrlEP (U32 dir)
+{
+ /* Not needed */
+}
+
+/*
+ * Enable USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+void USBD_EnableEP (U32 EPNum)
+{
+ ep_buffer_t *desc = get_desc(EPNum);
+
+ EPNum &= EPNUM_MASK;
+ MXC_USB->ep[EPNum] |= (MXC_F_USB_EP_INT_EN | ep_info[EPNum].type | MXC_F_USB_EP_DT);
+
+ if (ep_info[EPNum].type == MXC_S_USB_EP_DIR_OUT) {
+ // This is an OUT endpoint. Go ahead and register a request.
+ desc = get_desc(EPNum);
+ desc->buf0_address = (uint32_t)ep_buffer[EPNum];
+ desc->buf0_desc = sizeof(ep_buffer[EPNum]);
+ MXC_USB->out_owner = (1 << EPNum);
+ }
+}
+
+/*
+ * Disable USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+void USBD_DisableEP (U32 EPNum)
+{
+ EPNum &= EPNUM_MASK;
+ MXC_USB->ep[EPNum] = 0;
+}
+
+/*
+ * Reset USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+void USBD_ResetEP (U32 EPNum)
+{
+ ep_buffer_t *desc = get_desc(EPNum);
+
+ EPNum &= EPNUM_MASK;
+ MXC_USB->ep[EPNum] |= MXC_F_USB_EP_DT;
+
+ if (ep_info[EPNum].type == MXC_S_USB_EP_DIR_OUT) {
+ // This is an OUT endpoint. Go ahead and register a request.
+ desc = get_desc(EPNum);
+ desc->buf0_address = (uint32_t)ep_buffer[EPNum];
+ desc->buf0_desc = sizeof(ep_buffer[EPNum]);
+ MXC_USB->out_owner = (1 << EPNum);
+ }
+}
+
+/*
+ * Set Stall for USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+void USBD_SetStallEP (U32 EPNum)
+{
+ EPNum &= EPNUM_MASK;
+
+ if (EPNum == 0) {
+ MXC_USB->ep[0] |= (MXC_F_USB_EP_ST_STALL | MXC_F_USB_EP_STALL);
+ } else {
+ MXC_USB->ep[EPNum] |= MXC_F_USB_EP_STALL;
+ }
+}
+
+/*
+ * Clear Stall for USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+void USBD_ClrStallEP (U32 EPNum)
+{
+ USBD_ResetEP(EPNum);
+ MXC_USB->ep[EPNum & EPNUM_MASK] &= ~MXC_F_USB_EP_STALL;
+}
+
+/*
+ * Read USB Device Endpoint Data
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * pData: Pointer to Data Buffer
+ * Return Value: Number of bytes read
+ */
+U32 USBD_ReadEP (U32 EPNum, U8 *pData, U32 size)
+{
+ U32 cnt;
+ ep_buffer_t *desc = get_desc(EPNum);
+ USB_SETUP_PACKET *sup;
+
+ EPNum &= EPNUM_MASK;
+
+ if ((EPNum == 0) && setup_waiting) {
+ cnt = USBD_MAX_PACKET0;
+
+ if (size < cnt) {
+ cnt = size;
+ }
+ setup_waiting = 0;
+ memcpy(pData, (void*)&MXC_USB->setup0, cnt);
+ sup = (USB_SETUP_PACKET*)pData;
+
+ if ( (sup->bmRequestType.Dir == REQUEST_HOST_TO_DEVICE) && (sup->wLength > 0) ) {
+ // There is an OUT stage for this setup packet. Register a request.
+ if (!(MXC_USB->out_owner & 1)) {
+ desc = &ep_buffer_descriptor.ep0.out_buffer;
+ desc->buf0_address = (uint32_t)ep_buffer[0];
+ desc->buf0_desc = sup->wLength;
+ MXC_USB->out_owner = 1;
+ }
+ }
+ } else {
+ cnt = desc->buf0_desc;
+
+ if (size < cnt) {
+ cnt = size;
+ }
+ memcpy(pData, ep_buffer[EPNum], cnt);
+
+ // Register the next request.
+ desc->buf0_address = (uint32_t)ep_buffer[EPNum];
+ desc->buf0_desc = sizeof(ep_buffer[EPNum]);
+ MXC_USB->out_owner = (1 << EPNum);
+ }
+
+ return cnt;
+}
+
+/*
+ * Write USB Device Endpoint Data
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * pData: Pointer to Data Buffer
+ * cnt: Number of bytes to write
+ * Return Value: Number of bytes written
+ */
+U32 USBD_WriteEP (U32 EPNum, U8 *pData, U32 cnt)
+{
+ ep_buffer_t *desc = get_desc(EPNum);
+ uint32_t mask;
+
+ EPNum &= EPNUM_MASK;
+ mask = (1 << EPNum);
+
+ if (MXC_USB->in_owner & mask) {
+ return 0;
+ }
+
+ if (EPNum == 0) {
+ // Prepare to ACK the status stage.
+ MXC_USB->ep[0] |= MXC_F_USB_EP_ST_ACK;
+
+ if ((cnt == 0) && !ep0_expect_zlp) {
+ // This is a status stage ACK. Handled in hardware.
+ return 0;
+ } else if (cnt == USBD_MAX_PACKET0) {
+ ep0_expect_zlp = 1;
+ } else {
+ ep0_expect_zlp = 0;
+ }
+ }
+
+ if (cnt > MXC_USB_MAX_PACKET) {
+ cnt = MXC_USB_MAX_PACKET;
+ }
+
+ /* prepare data to be sent */
+ memcpy(ep_buffer[EPNum], pData, cnt);
+ desc->buf0_address = (uint32_t)ep_buffer[EPNum];
+ desc->buf0_desc = cnt;
+
+ /* start the transaction */
+ MXC_USB->in_owner = mask;
+
+ return cnt;
+}
+
+/*
+ * USB Device Interrupt Service Routine
+ */
+void USB_IRQHandler (void)
+{
+ NVIC_DisableIRQ(USB_IRQn);
+ USBD_SignalHandler();
+}
+
+void USBD_Handler(void)
+{
+ uint32_t irq_flags;
+ unsigned int ep;
+ uint32_t ep_int, mask;
+
+ // Read and clear interrupts
+ irq_flags = MXC_USB->dev_intfl;
+ MXC_USB->dev_intfl = irq_flags;
+
+ /* reset interrupt */
+ if (irq_flags & MXC_F_USB_DEV_INTFL_BRST) {
+ if (suspended) {
+ suspended = 0;
+#ifdef __RTX
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_RESUME, USBD_RTX_DevTask);
+ }
+#else
+ if (USBD_P_Resume_Event) {
+ USBD_P_Resume_Event();
+ }
+#endif
+ }
+
+ reset_state();
+ usbd_reset_core();
+
+#ifdef __RTX
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_RESET, USBD_RTX_DevTask);
+ }
+#else
+ if (USBD_P_Reset_Event) {
+ USBD_P_Reset_Event();
+ }
+#endif
+
+ }
+
+ /* reset done interrupt */
+ if (irq_flags & MXC_F_USB_DEV_INTFL_BRST_DN) {
+ reset_state();
+ }
+
+ /* suspend interrupt */
+ if (irq_flags & MXC_F_USB_DEV_INTFL_SUSP) {
+ suspended = 1;
+#ifdef __RTX
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_SUSPEND, USBD_RTX_DevTask);
+ }
+#else
+ if (USBD_P_Suspend_Event) {
+ USBD_P_Suspend_Event();
+ }
+#endif
+ }
+
+ if (irq_flags & MXC_F_USB_DEV_INTFL_VBUS) {
+#ifdef __RTX
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_POWER_ON, USBD_RTX_DevTask);
+ }
+#else
+ if (USBD_P_Power_Event) {
+ USBD_P_Power_Event(1);
+ }
+#endif
+ }
+
+ if (irq_flags & MXC_F_USB_DEV_INTFL_NO_VBUS) {
+#ifdef __RTX
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_POWER_OFF, USBD_RTX_DevTask);
+ }
+#else
+ if (USBD_P_Power_Event) {
+ USBD_P_Power_Event(0);
+ }
+#endif
+ }
+
+ if (irq_flags & MXC_F_USB_DEV_INTFL_SETUP) {
+ setup_waiting = 1;
+#ifdef __RTX
+ if (USBD_RTX_EPTask[0]) {
+ isr_evt_set(USBD_EVT_SETUP, USBD_RTX_EPTask[0]);
+ }
+#else
+ if (USBD_P_EP[0]) {
+ USBD_P_EP[0](USBD_EVT_SETUP);
+ }
+#endif
+ }
+
+ if (irq_flags & MXC_F_USB_DEV_INTFL_EP_IN) {
+
+ // Read and clear endpoint interrupts
+ ep_int = MXC_USB->in_int;
+ MXC_USB->in_int = ep_int;
+
+ mask = 1;
+ for (ep = 0; ep < MXC_USB_NUM_EP; ep++) {
+ if (ep_int & mask) {
+#ifdef __RTX
+ if (USBD_RTX_EPTask[ep]) {
+ isr_evt_set(USBD_EVT_IN, USBD_RTX_EPTask[ep]);
+ }
+#else
+ if (USBD_P_EP[ep]) {
+ USBD_P_EP[ep](USBD_EVT_IN);
+ }
+#endif
+ }
+
+ mask <<= 1;
+ }
+ }
+
+ if (irq_flags & MXC_F_USB_DEV_INTFL_EP_OUT) {
+
+ // Read and clear endpoint interrupts
+ ep_int = MXC_USB->out_int;
+ MXC_USB->out_int = ep_int;
+
+ mask = 1;
+ for (ep = 0; ep < MXC_USB_NUM_EP; ep++) {
+ if (ep_int & mask) {
+#ifdef __RTX
+ if (USBD_RTX_EPTask[ep]) {
+ isr_evt_set(USBD_EVT_OUT, USBD_RTX_EPTask[ep]);
+ }
+#else
+ if (USBD_P_EP[ep]) {
+ USBD_P_EP[ep](USBD_EVT_OUT);
+ }
+#endif
+ }
+
+ mask <<= 1;
+ }
+ }
+
+ if (irq_flags & MXC_F_USB_DEV_INTFL_DMA_ERR) {
+ // Read and clear endpoint interrupts
+ ep_int = MXC_USB->dma_err_int;
+ MXC_USB->dma_err_int = ep_int;
+ while(1); // not recoverable
+ }
+
+ NVIC_EnableIRQ(USB_IRQn);
+
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/DAP_config.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/DAP_config.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,454 @@
+/**
+ * @file DAP_config.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __DAP_CONFIG_H__
+#define __DAP_CONFIG_H__
+
+#include "stdint.h"
+#include "cmsis_os2.h"
+#include "IO_Config.h"
+#include "uart.h"
+//#include "debug_cm.h"
+//#include "swd_host.h"
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
+\ingroup DAP_ConfigIO_gr
+@{
+Provides definitions about:
+ - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
+ - Debug Unit communication packet size.
+ - Debug Access Port communication mode (JTAG or SWD).
+ - Optional information about a connected Target Device (for Evaluation Boards).
+*/
+
+/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
+/// This value is used to calculate the SWD/JTAG clock speed.
+#define CPU_CLOCK SystemCoreClock ///< Specifies the CPU Clock in Hz
+
+/// Number of processor cycles for I/O Port write operations.
+/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
+/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
+/// requrie 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
+/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
+/// requrired.
+#define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
+
+/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available
+
+/// Indicate that JTAG communication mode is available at the Debug Port.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available.
+
+/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
+/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
+#define DAP_JTAG_DEV_CNT 0 ///< Maximum number of JTAG devices on scan chain
+
+/// Default communication mode on the Debug Access Port.
+/// Used for the command \ref DAP_Connect when Port Default mode is selected.
+#define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
+
+/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
+/// Used to initialize the default SWD/JTAG clock frequency.
+/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
+#define DAP_DEFAULT_SWJ_CLOCK 5000000 ///< Default SWD/JTAG clock frequency in Hz.
+
+/// Maximum Package Size for Command and Response data.
+/// This configuration settings is used to optimized the communication performance with the
+/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
+#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed.
+
+/// Maximum Package Buffers for Command and Response data.
+/// This configuration settings is used to optimized the communication performance with the
+/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
+/// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
+#define DAP_PACKET_COUNT 64 ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
+
+/// Indicate that UART Serial Wire Output (SWO) trace is available.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available
+
+/// Maximum SWO UART Baudrate
+#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz
+
+/// Indicate that Manchester Serial Wire Output (SWO) trace is available.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available
+
+/// SWO Trace Buffer Size.
+#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n)
+
+/// SWO Streaming Trace.
+#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available.
+
+/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
+#define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported).
+
+/// Debug Unit is connected to fixed Target Device.
+/// The Debug Unit may be part of an evaluation board and always connected to a fixed
+/// known device. In this case a Device Vendor and Device Name string is stored which
+/// may be used by the debugger or IDE to configure device parameters.
+#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
+
+#if TARGET_DEVICE_FIXED
+#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor
+#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device
+#endif
+
+///@}
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
+\ingroup DAP_ConfigIO_gr
+@{
+
+Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
+and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
+interface of a device. The following I/O Pins are provided:
+
+JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
+---------------------------- | -------------------- | ---------------------------------------------
+TCK: Test Clock | SWCLK: Clock | Output Push/Pull
+TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
+TDI: Test Data Input | | Output Push/Pull
+TDO: Test Data Output | | Input
+nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
+nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
+
+
+DAP Hardware I/O Pin Access Functions
+-------------------------------------
+The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
+these I/O Pins.
+
+For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
+This functions are provided to achieve faster I/O that is possible with some advanced GPIO
+peripherals that can independently write/read a single I/O pin without affecting any other pins
+of the same I/O port. The following SWDIO I/O Pin functions are provided:
+ - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
+ - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
+ - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
+ - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
+*/
+
+
+// Configure DAP I/O pins ------------------------------
+
+/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
+Configures the DAP Hardware I/O pins for JTAG mode:
+ - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
+ - TDO to input mode.
+*/
+__STATIC_INLINE void PORT_JTAG_SETUP(void)
+{
+#if (DAP_JTAG != 0)
+#endif
+}
+
+/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
+Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
+ - SWCLK, SWDIO, nRESET to output mode and set to default high level.
+ - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
+*/
+__STATIC_INLINE void PORT_SWD_SETUP(void)
+{
+ SWD_DAT_IO = 1;
+ SWD_CLK_IO = 1;
+ DBG_RST_IO = 1;
+ GPIO_SetMode(SWD_DAT_GRP, (1 << SWD_DAT_BIT), GPIO_MODE_OUTPUT);
+ GPIO_SetMode(SWD_CLK_GRP, (1 << SWD_CLK_BIT), GPIO_MODE_OUTPUT);
+ GPIO_SetMode(DBG_RST_GRP, (1 << DBG_RST_BIT), GPIO_MODE_OUTPUT);
+}
+
+/** Disable JTAG/SWD I/O Pins.
+Disables the DAP Hardware I/O pins which configures:
+ - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
+*/
+__STATIC_INLINE void PORT_OFF(void)
+{
+ GPIO_SetMode(SWD_DAT_GRP, (1 << SWD_DAT_BIT), GPIO_MODE_INPUT);
+ GPIO_SetMode(SWD_CLK_GRP, (1 << SWD_CLK_BIT), GPIO_MODE_INPUT);
+ GPIO_SetMode(DBG_RST_GRP, (1 << DBG_RST_BIT), GPIO_MODE_INPUT);
+}
+
+// SWCLK/TCK I/O pin -------------------------------------
+
+/** SWCLK/TCK I/O pin: Get Input.
+\return Current status of the SWCLK/TCK DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void)
+{
+ return SWD_CLK_IO;
+}
+
+/** SWCLK/TCK I/O pin: Set Output to High.
+Set the SWCLK/TCK DAP hardware I/O pin to high level.
+*/
+__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET(void)
+{
+ SWD_CLK_IO = 1;
+}
+
+/** SWCLK/TCK I/O pin: Set Output to Low.
+Set the SWCLK/TCK DAP hardware I/O pin to low level.
+*/
+__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void)
+{
+ SWD_CLK_IO = 0;
+}
+
+// SWDIO/TMS Pin I/O --------------------------------------
+
+/** SWDIO/TMS I/O pin: Get Input.
+\return Current status of the SWDIO/TMS DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void)
+{
+ return SWD_DAT_IO;
+}
+
+/** SWDIO/TMS I/O pin: Set Output to High.
+Set the SWDIO/TMS DAP hardware I/O pin to high level.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET(void)
+{
+ SWD_DAT_IO = 1;
+}
+
+/** SWDIO/TMS I/O pin: Set Output to Low.
+Set the SWDIO/TMS DAP hardware I/O pin to low level.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void)
+{
+ SWD_DAT_IO = 0;
+}
+
+/** SWDIO I/O pin: Get Input (used in SWD mode only).
+\return Current status of the SWDIO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
+{
+ return SWD_DAT_IO;
+}
+
+/** SWDIO I/O pin: Set Output (used in SWD mode only).
+\param bit Output value for the SWDIO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT(uint32_t bit)
+{
+ SWD_DAT_IO = bit;
+}
+
+/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
+Configure the SWDIO DAP hardware I/O pin to output mode. This function is
+called prior \ref PIN_SWDIO_OUT function calls.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void)
+{
+ GPIO_SetMode(SWD_DAT_GRP, (1 << SWD_DAT_BIT), GPIO_MODE_OUTPUT);
+}
+
+/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
+Configure the SWDIO DAP hardware I/O pin to input mode. This function is
+called prior \ref PIN_SWDIO_IN function calls.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void)
+{
+ GPIO_SetMode(SWD_DAT_GRP, (1 << SWD_DAT_BIT), GPIO_MODE_INPUT);
+}
+
+
+// TDI Pin I/O ---------------------------------------------
+
+/** TDI I/O pin: Get Input.
+\return Current status of the TDI DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void)
+{
+ return (0); // Not available
+}
+
+/** TDI I/O pin: Set Output.
+\param bit Output value for the TDI DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE void PIN_TDI_OUT(uint32_t bit)
+{
+ ; // Not available
+}
+
+
+// TDO Pin I/O ---------------------------------------------
+
+/** TDO I/O pin: Get Input.
+\return Current status of the TDO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void)
+{
+ return (0); // Not available
+}
+
+
+// nTRST Pin I/O -------------------------------------------
+
+/** nTRST I/O pin: Get Input.
+\return Current status of the nTRST DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void)
+{
+ return (0); // Not available
+}
+
+/** nTRST I/O pin: Set Output.
+\param bit JTAG TRST Test Reset pin status:
+ - 0: issue a JTAG TRST Test Reset.
+ - 1: release JTAG TRST Test Reset.
+*/
+__STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit)
+{
+ ; // Not available
+}
+
+// nRESET Pin I/O------------------------------------------
+
+/** nRESET I/O pin: Get Input.
+\return Current status of the nRESET DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void)
+{
+ return DBG_RST_IO;
+}
+
+/** nRESET I/O pin: Set Output.
+\param bit target device hardware reset pin status:
+ - 0: issue a device hardware reset.
+ - 1: release device hardware reset.
+*/
+// TODO - sw specific implementation should be created
+
+__STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit)
+{
+ DBG_RST_IO = bit;
+}
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
+\ingroup DAP_ConfigIO_gr
+@{
+
+CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
+
+It is recommended to provide the following LEDs for status indication:
+ - Connect LED: is active when the DAP hardware is connected to a debugger.
+ - Running LED: is active when the debugger has put the target device into running state.
+*/
+
+/** Debug Unit: Set status of Connected LED.
+\param bit status of the Connect LED.
+ - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
+ - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
+*/
+__STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit)
+{
+ LED_ISP_IO = bit ? 0 : 1;
+}
+
+/** Debug Unit: Set status Target Running LED.
+\param bit status of the Target Running LED.
+ - 1: Target Running LED ON: program execution in target started.
+ - 0: Target Running LED OFF: program execution in target stopped.
+*/
+__STATIC_INLINE void LED_RUNNING_OUT(uint32_t bit)
+{
+ LED_GRE_IO = bit ? 0 : 1;
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
+\ingroup DAP_ConfigIO_gr
+@{
+Access function for Test Domain Timer.
+
+The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
+default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
+
+*/
+
+/** Get timestamp of Test Domain Timer.
+\return Current timestamp value.
+*/
+__STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
+ return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK);
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
+\ingroup DAP_ConfigIO_gr
+@{
+
+CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
+*/
+
+/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
+This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
+Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
+ - I/O clock system enabled.
+ - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
+ - for nTRST, nRESET a weak pull-up (if available) is enabled.
+ - LED output pins are enabled and LEDs are turned off.
+*/
+__STATIC_INLINE void DAP_SETUP(void)
+{
+ GPIO_SetMode(LED_ICE_GRP, (1 << LED_ICE_BIT), GPIO_MODE_OUTPUT);
+ GPIO_SetMode(LED_ISP_GRP, (1 << LED_ISP_BIT), GPIO_MODE_OUTPUT);
+ GPIO_SetMode(LED_GRE_GRP, (1 << LED_GRE_BIT), GPIO_MODE_OUTPUT);
+ LED_ICE_IO = 0;
+ LED_ISP_IO = 1;
+ LED_GRE_IO = 1;
+}
+
+/** Reset Target Device with custom specific I/O pin or command sequence.
+This function allows the optional implementation of a device specific reset sequence.
+It is called when the command \ref DAP_ResetTarget and is for example required
+when a device needs a time-critical unlock sequence that enables the debug port.
+\return 0 = no device specific reset sequence is implemented.\n
+ 1 = a device specific reset sequence is implemented.
+*/
+__STATIC_INLINE uint32_t RESET_TARGET(void)
+{
+ return (0); // change to '1' when a device reset sequence is implemented
+}
+
+///@}
+
+
+#endif /* __DAP_CONFIG_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Include/M480.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Include/M480.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,638 @@
+/**************************************************************************//**
+ * @file M480.h
+ * @version V1.00
+ * @brief M480 peripheral access layer header file.
+ * This file contains all the peripheral register's definitions,
+ * bits definitions and memory mapping for NuMicro M480 MCU.
+ *
+ * @copyright (C) 2017-2018 Nuvoton Technology Corp. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/
+/**
+ \mainpage NuMicro M480 Driver Reference Guide
+ *
+ * <b>Introduction</b>
+ *
+ * This user manual describes the usage of M480 Series MCU device driver
+ *
+ * <b>Disclaimer</b>
+ *
+ * The Software is furnished "AS IS", without warranty as to performance or results, and
+ * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
+ * warranties, express, implied or otherwise, with regard to the Software, its use, or
+ * operation, including without limitation any and all warranties of merchantability, fitness
+ * for a particular purpose, and non-infringement of intellectual property rights.
+ *
+ * <b>Important Notice</b>
+ *
+ * Nuvoton Products are neither intended nor warranted for usage in systems or equipment,
+ * any malfunction or failure of which may cause loss of human life, bodily injury or severe
+ * property damage. Such applications are deemed, "Insecure Usage".
+ *
+ * Insecure usage includes, but is not limited to: equipment for surgical implementation,
+ * atomic energy control instruments, airplane or spaceship instruments, the control or
+ * operation of dynamic, brake or safety systems designed for vehicular use, traffic signal
+ * instruments, all types of safety devices, and other applications intended to support or
+ * sustain life.
+ *
+ * All Insecure Usage shall be made at customer's risk, and in the event that third parties
+ * lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify
+ * the damages and liabilities thus incurred by Nuvoton.
+ *
+ * Please note that all data and specifications are subject to change without notice. All the
+ * trademarks of products and companies mentioned in this datasheet belong to their respective
+ * owners.
+ *
+ * <b>Copyright Notice</b>
+ *
+ * Copyright (C) 2017-2018 Nuvoton Technology Corp. All rights reserved.
+ */
+#ifndef __M480_H__
+#define __M480_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************/
+/* Processor and Core Peripherals */
+/******************************************************************************/
+/** @addtogroup CMSIS_Device Device CMSIS Definitions
+ Configuration of the Cortex-M4 Processor and Core Peripherals
+ @{
+*/
+
+/**
+ * @details Interrupt Number Definition.
+ */
+typedef enum IRQn {
+ /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
+
+ /****** M480 Specific Interrupt Numbers ********************************************************/
+
+ BOD_IRQn = 0, /*!< Brown Out detection Interrupt */
+ IRC_IRQn = 1, /*!< Internal RC Interrupt */
+ PWRWU_IRQn = 2, /*!< Power Down Wake Up Interrupt */
+ RAMPE_IRQn = 3, /*!< SRAM parity check failed Interrupt */
+ CKFAIL_IRQn = 4, /*!< Clock failed Interrupt */
+ RTC_IRQn = 6, /*!< Real Time Clock Interrupt */
+ TAMPER_IRQn = 7, /*!< Tamper detection Interrupt */
+ WDT_IRQn = 8, /*!< Watchdog timer Interrupt */
+ WWDT_IRQn = 9, /*!< Window Watchdog timer Interrupt */
+ EINT0_IRQn = 10, /*!< External Input 0 Interrupt */
+ EINT1_IRQn = 11, /*!< External Input 1 Interrupt */
+ EINT2_IRQn = 12, /*!< External Input 2 Interrupt */
+ EINT3_IRQn = 13, /*!< External Input 3 Interrupt */
+ EINT4_IRQn = 14, /*!< External Input 4 Interrupt */
+ EINT5_IRQn = 15, /*!< External Input 5 Interrupt */
+ GPA_IRQn = 16, /*!< GPIO Port A Interrupt */
+ GPB_IRQn = 17, /*!< GPIO Port B Interrupt */
+ GPC_IRQn = 18, /*!< GPIO Port C Interrupt */
+ GPD_IRQn = 19, /*!< GPIO Port D Interrupt */
+ GPE_IRQn = 20, /*!< GPIO Port E Interrupt */
+ GPF_IRQn = 21, /*!< GPIO Port F Interrupt */
+ QSPI0_IRQn = 22, /*!< QSPI0 Interrupt */
+ SPI0_IRQn = 23, /*!< SPI0 Interrupt */
+ BRAKE0_IRQn = 24, /*!< BRAKE0 Interrupt */
+ EPWM0P0_IRQn = 25, /*!< EPWM0P0 Interrupt */
+ EPWM0P1_IRQn = 26, /*!< EPWM0P1 Interrupt */
+ EPWM0P2_IRQn = 27, /*!< EPWM0P2 Interrupt */
+ BRAKE1_IRQn = 28, /*!< BRAKE1 Interrupt */
+ EPWM1P0_IRQn = 29, /*!< EPWM1P0 Interrupt */
+ EPWM1P1_IRQn = 30, /*!< EPWM1P1 Interrupt */
+ EPWM1P2_IRQn = 31, /*!< EPWM1P2 Interrupt */
+ TMR0_IRQn = 32, /*!< Timer 0 Interrupt */
+ TMR1_IRQn = 33, /*!< Timer 1 Interrupt */
+ TMR2_IRQn = 34, /*!< Timer 2 Interrupt */
+ TMR3_IRQn = 35, /*!< Timer 3 Interrupt */
+ UART0_IRQn = 36, /*!< UART 0 Interrupt */
+ UART1_IRQn = 37, /*!< UART 1 Interrupt */
+ I2C0_IRQn = 38, /*!< I2C 0 Interrupt */
+ I2C1_IRQn = 39, /*!< I2C 1 Interrupt */
+ PDMA_IRQn = 40, /*!< Peripheral DMA Interrupt */
+ DAC_IRQn = 41, /*!< DAC Interrupt */
+ ADC0_IRQn = 42, /*!< ADC0 Interrupt */
+ ADC1_IRQn = 43, /*!< ADC1 Interrupt */
+ ACMP01_IRQn = 44, /*!< Analog Comparator 0 and 1 Interrupt */
+ ADC2_IRQn = 46, /*!< ADC2 Interrupt */
+ ADC3_IRQn = 47, /*!< ADC3 Interrupt */
+ UART2_IRQn = 48, /*!< UART2 Interrupt */
+ UART3_IRQn = 49, /*!< UART3 Interrupt */
+ SPI1_IRQn = 51, /*!< SPI1 Interrupt */
+ SPI2_IRQn = 52, /*!< SPI2 Interrupt */
+ USBD_IRQn = 53, /*!< USB device Interrupt */
+ USBH_IRQn = 54, /*!< USB host Interrupt */
+ USBOTG_IRQn = 55, /*!< USB OTG Interrupt */
+ CAN0_IRQn = 56, /*!< CAN0 Interrupt */
+ CAN1_IRQn = 57, /*!< CAN1 Interrupt */
+ SC0_IRQn = 58, /*!< Smart Card 0 Interrupt */
+ SC1_IRQn = 59, /*!< Smart Card 1 Interrupt */
+ SC2_IRQn = 60, /*!< Smart Card 2 Interrupt */
+ SPI3_IRQn = 62, /*!< SPI3 Interrupt */
+ EMAC_TX_IRQn = 66, /*!< Ethernet MAC TX Interrupt */
+ EMAC_RX_IRQn = 67, /*!< Ethernet MAC RX Interrupt */
+ SDH0_IRQn = 64, /*!< Secure Digital Host Controller 0 Interrupt */
+ USBD20_IRQn = 65, /*!< High Speed USB device Interrupt */
+ I2S0_IRQn = 68, /*!< I2S0 Interrupt */
+ OPA_IRQn = 70, /*!< OPA Interrupt */
+ CRPT_IRQn = 71, /*!< CRPT Interrupt */
+ GPG_IRQn = 72, /*!< GPIO Port G Interrupt */
+ EINT6_IRQn = 73, /*!< External Input 6 Interrupt */
+ UART4_IRQn = 74, /*!< UART4 Interrupt */
+ UART5_IRQn = 75, /*!< UART5 Interrupt */
+ USCI0_IRQn = 76, /*!< USCI0 Interrupt */
+ USCI1_IRQn = 77, /*!< USCI1 Interrupt */
+ BPWM0_IRQn = 78, /*!< BPWM0 Interrupt */
+ BPWM1_IRQn = 79, /*!< BPWM1 Interrupt */
+ SPIM_IRQn = 80, /*!< SPIM Interrupt */
+ I2C2_IRQn = 82, /*!< I2C2 Interrupt */
+ QEI0_IRQn = 84, /*!< QEI0 Interrupt */
+ QEI1_IRQn = 85, /*!< QEI1 Interrupt */
+ ECAP0_IRQn = 86, /*!< ECAP0 Interrupt */
+ ECAP1_IRQn = 87, /*!< ECAP1 Interrupt */
+ GPH_IRQn = 88, /*!< GPIO Port H Interrupt */
+ EINT7_IRQn = 89, /*!< External Input 7 Interrupt */
+ SDH1_IRQn = 90, /*!< Secure Digital Host Controller 1 Interrupt */
+ HSUSBH_IRQn = 92, /*!< High speed USB host Interrupt */
+ USBOTG20_IRQn = 93, /*!< High speed USB OTG Interrupt */
+}
+IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M4 Processor and Core Peripherals */
+#define __CM4_REV 0x0201UL /*!< Core Revision r2p1 */
+#define __NVIC_PRIO_BITS 4UL /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0UL /*!< Set to 1 if different SysTick Config is used */
+#define __MPU_PRESENT 1UL /*!< MPU present or not */
+#ifdef __FPU_PRESENT
+#undef __FPU_PRESENT
+#define __FPU_PRESENT 1UL /*!< FPU present or not */
+#else
+#define __FPU_PRESENT 1UL /*!< FPU present or not */
+#endif
+
+/*@}*/ /* end of group CMSIS_Device */
+
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_M480.h" /* System include file */
+#include <stdint.h>
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/******************************************************************************/
+/* Register definitions */
+/******************************************************************************/
+
+#include "m480_sys_reg.h"
+#include "m480_clk_reg.h"
+#include "m480_fmc_reg.h"
+#include "m480_gpio_reg.h"
+#include "m480_rtc_reg.h"
+#include "m480_uart_reg.h"
+#include "m480_hsusbd_reg.h"
+
+
+/** @addtogroup PERIPHERAL_MEM_MAP Peripheral Memory Base
+ Memory Mapped Structure for Peripherals
+ @{
+ */
+/* Peripheral and SRAM base address */
+#define FLASH_BASE ((uint32_t)0x00000000) /*!< Flash base address */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM Base Address */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral Base Address */
+#define AHBPERIPH_BASE PERIPH_BASE /*!< AHB Base Address */
+#define APBPERIPH_BASE (PERIPH_BASE + (uint32_t)0x00040000) /*!< APB Base Address */
+
+/*!< AHB peripherals */
+#define SYS_BASE (AHBPERIPH_BASE + 0x00000UL)
+#define CLK_BASE (AHBPERIPH_BASE + 0x00200UL)
+#define NMI_BASE (AHBPERIPH_BASE + 0x00300UL)
+#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000UL)
+#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040UL)
+#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080UL)
+#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0UL)
+#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100UL)
+#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140UL)
+#define GPIOG_BASE (AHBPERIPH_BASE + 0x04180UL)
+#define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0UL)
+#define GPIOI_BASE (AHBPERIPH_BASE + 0x04200UL)
+#define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440UL)
+#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800UL)
+#define PDMA_BASE (AHBPERIPH_BASE + 0x08000UL)
+#define USBH_BASE (AHBPERIPH_BASE + 0x09000UL)
+#define HSUSBH_BASE (AHBPERIPH_BASE + 0x1A000UL)
+#define EMAC_BASE (AHBPERIPH_BASE + 0x0B000UL)
+#define FMC_BASE (AHBPERIPH_BASE + 0x0C000UL)
+#define SDH0_BASE (AHBPERIPH_BASE + 0x0D000UL)
+#define SDH1_BASE (AHBPERIPH_BASE + 0x0E000UL)
+#define EBI_BASE (AHBPERIPH_BASE + 0x10000UL)
+#define HSUSBD_BASE (AHBPERIPH_BASE + 0x19000UL)
+#define CRC_BASE (AHBPERIPH_BASE + 0x31000UL)
+#define TAMPER_BASE (AHBPERIPH_BASE + 0xE1000UL)
+
+/*!< APB2 peripherals */
+#define WDT_BASE (APBPERIPH_BASE + 0x00000UL)
+#define WWDT_BASE (APBPERIPH_BASE + 0x00100UL)
+#define OPA_BASE (APBPERIPH_BASE + 0x06000UL)
+#define I2S_BASE (APBPERIPH_BASE + 0x08000UL)
+#define TIMER0_BASE (APBPERIPH_BASE + 0x10000UL)
+#define TIMER1_BASE (APBPERIPH_BASE + 0x10100UL)
+#define EPWM0_BASE (APBPERIPH_BASE + 0x18000UL)
+#define BPWM0_BASE (APBPERIPH_BASE + 0x1A000UL)
+#define QSPI0_BASE (APBPERIPH_BASE + 0x20000UL)
+#define SPI1_BASE (APBPERIPH_BASE + 0x22000UL)
+#define SPI3_BASE (APBPERIPH_BASE + 0x24000UL)
+#define UART0_BASE (APBPERIPH_BASE + 0x30000UL)
+#define UART2_BASE (APBPERIPH_BASE + 0x32000UL)
+#define UART4_BASE (APBPERIPH_BASE + 0x34000UL)
+#define I2C0_BASE (APBPERIPH_BASE + 0x40000UL)
+#define I2C2_BASE (APBPERIPH_BASE + 0x42000UL)
+#define CAN0_BASE (APBPERIPH_BASE + 0x60000UL)
+#define QEI0_BASE (APBPERIPH_BASE + 0x70000UL)
+#define ECAP0_BASE (APBPERIPH_BASE + 0x74000UL)
+#define USCI0_BASE (APBPERIPH_BASE + 0x90000UL)
+
+
+/*!< APB1 peripherals */
+#define RTC_BASE (APBPERIPH_BASE + 0x01000UL)
+#define EADC_BASE (APBPERIPH_BASE + 0x03000UL)
+#define ACMP01_BASE (APBPERIPH_BASE + 0x05000UL)
+#define USBD_BASE (APBPERIPH_BASE + 0x80000UL)
+#define OTG_BASE (APBPERIPH_BASE + 0x0D000UL)
+#define HSOTG_BASE (APBPERIPH_BASE + 0x0F000UL)
+#define TIMER2_BASE (APBPERIPH_BASE + 0x11000UL)
+#define TIMER3_BASE (APBPERIPH_BASE + 0x11100UL)
+#define EPWM1_BASE (APBPERIPH_BASE + 0x19000UL)
+#define BPWM1_BASE (APBPERIPH_BASE + 0x1B000UL)
+#define SPI0_BASE (APBPERIPH_BASE + 0x21000UL)
+#define SPI2_BASE (APBPERIPH_BASE + 0x23000UL)
+#define UART1_BASE (APBPERIPH_BASE + 0x31000UL)
+#define UART3_BASE (APBPERIPH_BASE + 0x33000UL)
+#define UART5_BASE (APBPERIPH_BASE + 0x35000UL)
+#define I2C1_BASE (APBPERIPH_BASE + 0x41000UL)
+#define CAN1_BASE (APBPERIPH_BASE + 0x61000UL)
+#define QEI1_BASE (APBPERIPH_BASE + 0x71000UL)
+#define ECAP1_BASE (APBPERIPH_BASE + 0x75000UL)
+#define USCI1_BASE (APBPERIPH_BASE + 0x91000UL)
+#define CRPT_BASE (0x50080000UL)
+#define SPIM_BASE (0x40007000UL)
+
+#define SC0_BASE (APBPERIPH_BASE + 0x50000UL)
+#define SC1_BASE (APBPERIPH_BASE + 0x51000UL)
+#define SC2_BASE (APBPERIPH_BASE + 0x52000UL)
+#define DAC0_BASE (APBPERIPH_BASE + 0x07000UL)
+#define DAC1_BASE (APBPERIPH_BASE + 0x07040UL)
+#define DACDBG_BASE (APBPERIPH_BASE + 0x07FECUL)
+#define OPA0_BASE (APBPERIPH_BASE + 0x06000UL)
+
+/*@}*/ /* end of group PERIPHERAL_MEM_MAP */
+
+
+/** @addtogroup PERIPHERAL_DECLARATION Peripheral Pointer
+ The Declaration of Peripherals
+ @{
+ */
+
+#define SYS ((SYS_T *) SYS_BASE)
+#define CLK ((CLK_T *) CLK_BASE)
+#define NMI ((NMI_T *) NMI_BASE)
+#define PA ((GPIO_T *) GPIOA_BASE)
+#define PB ((GPIO_T *) GPIOB_BASE)
+#define PC ((GPIO_T *) GPIOC_BASE)
+#define PD ((GPIO_T *) GPIOD_BASE)
+#define PE ((GPIO_T *) GPIOE_BASE)
+#define PF ((GPIO_T *) GPIOF_BASE)
+#define PG ((GPIO_T *) GPIOG_BASE)
+#define PH ((GPIO_T *) GPIOH_BASE)
+#define GPA ((GPIO_T *) GPIOA_BASE)
+#define GPB ((GPIO_T *) GPIOB_BASE)
+#define GPC ((GPIO_T *) GPIOC_BASE)
+#define GPD ((GPIO_T *) GPIOD_BASE)
+#define GPE ((GPIO_T *) GPIOE_BASE)
+#define GPF ((GPIO_T *) GPIOF_BASE)
+#define GPG ((GPIO_T *) GPIOG_BASE)
+#define GPH ((GPIO_T *) GPIOH_BASE)
+#define GPIO ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE)
+#define PDMA ((PDMA_T *) PDMA_BASE)
+#define USBH ((USBH_T *) USBH_BASE)
+#define HSUSBH ((HSUSBH_T *) HSUSBH_BASE)
+#define EMAC ((EMAC_T *) EMAC_BASE)
+#define FMC ((FMC_T *) FMC_BASE)
+#define SDH0 ((SDH_T *) SDH0_BASE)
+#define SDH1 ((SDH_T *) SDH1_BASE)
+#define EBI ((EBI_T *) EBI_BASE)
+#define CRC ((CRC_T *) CRC_BASE)
+#define TAMPER ((TAMPER_T *) TAMPER_BASE)
+
+#define WDT ((WDT_T *) WDT_BASE)
+#define WWDT ((WWDT_T *) WWDT_BASE)
+#define RTC ((RTC_T *) RTC_BASE)
+#define EADC ((EADC_T *) EADC_BASE)
+#define ACMP01 ((ACMP_T *) ACMP01_BASE)
+
+#define I2S0 ((I2S_T *) I2S_BASE)
+#define USBD ((USBD_T *) USBD_BASE)
+#define OTG ((OTG_T *) OTG_BASE)
+#define HSUSBD ((HSUSBD_T *)HSUSBD_BASE)
+#define HSOTG ((HSOTG_T *) HSOTG_BASE)
+#define TIMER0 ((TIMER_T *) TIMER0_BASE)
+#define TIMER1 ((TIMER_T *) TIMER1_BASE)
+#define TIMER2 ((TIMER_T *) TIMER2_BASE)
+#define TIMER3 ((TIMER_T *) TIMER3_BASE)
+#define EPWM0 ((EPWM_T *) EPWM0_BASE)
+#define EPWM1 ((EPWM_T *) EPWM1_BASE)
+#define BPWM0 ((BPWM_T *) BPWM0_BASE)
+#define BPWM1 ((BPWM_T *) BPWM1_BASE)
+#define ECAP0 ((ECAP_T *) ECAP0_BASE)
+#define ECAP1 ((ECAP_T *) ECAP1_BASE)
+#define QEI0 ((QEI_T *) QEI0_BASE)
+#define QEI1 ((QEI_T *) QEI1_BASE)
+#define QSPI0 ((QSPI_T *) QSPI0_BASE)
+#define SPI0 ((SPI_T *) SPI0_BASE)
+#define SPI1 ((SPI_T *) SPI1_BASE)
+#define SPI2 ((SPI_T *) SPI2_BASE)
+#define SPI3 ((SPI_T *) SPI3_BASE)
+#define UART0 ((UART_T *) UART0_BASE)
+#define UART1 ((UART_T *) UART1_BASE)
+#define UART2 ((UART_T *) UART2_BASE)
+#define UART3 ((UART_T *) UART3_BASE)
+#define UART4 ((UART_T *) UART4_BASE)
+#define UART5 ((UART_T *) UART5_BASE)
+#define I2C0 ((I2C_T *) I2C0_BASE)
+#define I2C1 ((I2C_T *) I2C1_BASE)
+#define I2C2 ((I2C_T *) I2C2_BASE)
+#define SC0 ((SC_T *) SC0_BASE)
+#define SC1 ((SC_T *) SC1_BASE)
+#define SC2 ((SC_T *) SC2_BASE)
+#define CAN0 ((CAN_T *) CAN0_BASE)
+#define CAN1 ((CAN_T *) CAN1_BASE)
+#define CRPT ((CRPT_T *) CRPT_BASE)
+#define SPIM ((volatile SPIM_T *) SPIM_BASE)
+#define DAC0 ((DAC_T *) DAC0_BASE)
+#define DAC1 ((DAC_T *) DAC1_BASE)
+#define USPI0 ((USPI_T *) USCI0_BASE) /*!< USPI0 Configuration Struct */
+#define USPI1 ((USPI_T *) USCI1_BASE) /*!< USPI1 Configuration Struct */
+#define OPA ((OPA_T *) OPA_BASE)
+#define UI2C0 ((UI2C_T *) USCI0_BASE) /*!< UI2C0 Configuration Struct */
+#define UI2C1 ((UI2C_T *) USCI1_BASE) /*!< UI2C1 Configuration Struct */
+#define UUART0 ((UUART_T *) USCI0_BASE) /*!< UUART0 Configuration Struct */
+#define UUART1 ((UUART_T *) USCI1_BASE) /*!< UUART1 Configuration Struct */
+
+/*@}*/ /* end of group ERIPHERAL_DECLARATION */
+
+/** @addtogroup IO_ROUTINE I/O Routines
+ The Declaration of I/O Routines
+ @{
+ */
+
+typedef volatile unsigned char vu8; ///< Define 8-bit unsigned volatile data type
+typedef volatile unsigned short vu16; ///< Define 16-bit unsigned volatile data type
+typedef volatile unsigned long vu32; ///< Define 32-bit unsigned volatile data type
+
+/**
+ * @brief Get a 8-bit unsigned value from specified address
+ * @param[in] addr Address to get 8-bit data from
+ * @return 8-bit unsigned value stored in specified address
+ */
+#define M8(addr) (*((vu8 *) (addr)))
+
+/**
+ * @brief Get a 16-bit unsigned value from specified address
+ * @param[in] addr Address to get 16-bit data from
+ * @return 16-bit unsigned value stored in specified address
+ * @note The input address must be 16-bit aligned
+ */
+#define M16(addr) (*((vu16 *) (addr)))
+
+/**
+ * @brief Get a 32-bit unsigned value from specified address
+ * @param[in] addr Address to get 32-bit data from
+ * @return 32-bit unsigned value stored in specified address
+ * @note The input address must be 32-bit aligned
+ */
+#define M32(addr) (*((vu32 *) (addr)))
+
+/**
+ * @brief Set a 32-bit unsigned value to specified I/O port
+ * @param[in] port Port address to set 32-bit data
+ * @param[in] value Value to write to I/O port
+ * @return None
+ * @note The output port must be 32-bit aligned
+ */
+#define outpw(port,value) *((volatile unsigned int *)(port)) = (value)
+
+/**
+ * @brief Get a 32-bit unsigned value from specified I/O port
+ * @param[in] port Port address to get 32-bit data from
+ * @return 32-bit unsigned value stored in specified I/O port
+ * @note The input port must be 32-bit aligned
+ */
+#define inpw(port) (*((volatile unsigned int *)(port)))
+
+/**
+ * @brief Set a 16-bit unsigned value to specified I/O port
+ * @param[in] port Port address to set 16-bit data
+ * @param[in] value Value to write to I/O port
+ * @return None
+ * @note The output port must be 16-bit aligned
+ */
+#define outps(port,value) *((volatile unsigned short *)(port)) = (value)
+
+/**
+ * @brief Get a 16-bit unsigned value from specified I/O port
+ * @param[in] port Port address to get 16-bit data from
+ * @return 16-bit unsigned value stored in specified I/O port
+ * @note The input port must be 16-bit aligned
+ */
+#define inps(port) (*((volatile unsigned short *)(port)))
+
+/**
+ * @brief Set a 8-bit unsigned value to specified I/O port
+ * @param[in] port Port address to set 8-bit data
+ * @param[in] value Value to write to I/O port
+ * @return None
+ */
+#define outpb(port,value) *((volatile unsigned char *)(port)) = (value)
+
+/**
+ * @brief Get a 8-bit unsigned value from specified I/O port
+ * @param[in] port Port address to get 8-bit data from
+ * @return 8-bit unsigned value stored in specified I/O port
+ */
+#define inpb(port) (*((volatile unsigned char *)(port)))
+
+/**
+ * @brief Set a 32-bit unsigned value to specified I/O port
+ * @param[in] port Port address to set 32-bit data
+ * @param[in] value Value to write to I/O port
+ * @return None
+ * @note The output port must be 32-bit aligned
+ */
+#define outp32(port,value) *((volatile unsigned int *)(port)) = (value)
+
+/**
+ * @brief Get a 32-bit unsigned value from specified I/O port
+ * @param[in] port Port address to get 32-bit data from
+ * @return 32-bit unsigned value stored in specified I/O port
+ * @note The input port must be 32-bit aligned
+ */
+#define inp32(port) (*((volatile unsigned int *)(port)))
+
+/**
+ * @brief Set a 16-bit unsigned value to specified I/O port
+ * @param[in] port Port address to set 16-bit data
+ * @param[in] value Value to write to I/O port
+ * @return None
+ * @note The output port must be 16-bit aligned
+ */
+#define outp16(port,value) *((volatile unsigned short *)(port)) = (value)
+
+/**
+ * @brief Get a 16-bit unsigned value from specified I/O port
+ * @param[in] port Port address to get 16-bit data from
+ * @return 16-bit unsigned value stored in specified I/O port
+ * @note The input port must be 16-bit aligned
+ */
+#define inp16(port) (*((volatile unsigned short *)(port)))
+
+/**
+ * @brief Set a 8-bit unsigned value to specified I/O port
+ * @param[in] port Port address to set 8-bit data
+ * @param[in] value Value to write to I/O port
+ * @return None
+ */
+#define outp8(port,value) *((volatile unsigned char *)(port)) = (value)
+
+/**
+ * @brief Get a 8-bit unsigned value from specified I/O port
+ * @param[in] port Port address to get 8-bit data from
+ * @return 8-bit unsigned value stored in specified I/O port
+ */
+#define inp8(port) (*((volatile unsigned char *)(port)))
+
+
+/*@}*/ /* end of group IO_ROUTINE */
+
+/******************************************************************************/
+/* Legacy Constants */
+/******************************************************************************/
+/** @addtogroup Legacy_Constants Legacy Constants
+ Legacy Constants
+ @{
+*/
+
+#ifndef NULL
+#define NULL (0) ///< NULL pointer
+#endif
+
+#define TRUE (1UL) ///< Boolean true, define to use in API parameters or return value
+#define FALSE (0UL) ///< Boolean false, define to use in API parameters or return value
+
+#define ENABLE (1UL) ///< Enable, define to use in API parameters
+#define DISABLE (0UL) ///< Disable, define to use in API parameters
+
+/* Define one bit mask */
+#define BIT0 (0x00000001UL) ///< Bit 0 mask of an 32 bit integer
+#define BIT1 (0x00000002UL) ///< Bit 1 mask of an 32 bit integer
+#define BIT2 (0x00000004UL) ///< Bit 2 mask of an 32 bit integer
+#define BIT3 (0x00000008UL) ///< Bit 3 mask of an 32 bit integer
+#define BIT4 (0x00000010UL) ///< Bit 4 mask of an 32 bit integer
+#define BIT5 (0x00000020UL) ///< Bit 5 mask of an 32 bit integer
+#define BIT6 (0x00000040UL) ///< Bit 6 mask of an 32 bit integer
+#define BIT7 (0x00000080UL) ///< Bit 7 mask of an 32 bit integer
+#define BIT8 (0x00000100UL) ///< Bit 8 mask of an 32 bit integer
+#define BIT9 (0x00000200UL) ///< Bit 9 mask of an 32 bit integer
+#define BIT10 (0x00000400UL) ///< Bit 10 mask of an 32 bit integer
+#define BIT11 (0x00000800UL) ///< Bit 11 mask of an 32 bit integer
+#define BIT12 (0x00001000UL) ///< Bit 12 mask of an 32 bit integer
+#define BIT13 (0x00002000UL) ///< Bit 13 mask of an 32 bit integer
+#define BIT14 (0x00004000UL) ///< Bit 14 mask of an 32 bit integer
+#define BIT15 (0x00008000UL) ///< Bit 15 mask of an 32 bit integer
+#define BIT16 (0x00010000UL) ///< Bit 16 mask of an 32 bit integer
+#define BIT17 (0x00020000UL) ///< Bit 17 mask of an 32 bit integer
+#define BIT18 (0x00040000UL) ///< Bit 18 mask of an 32 bit integer
+#define BIT19 (0x00080000UL) ///< Bit 19 mask of an 32 bit integer
+#define BIT20 (0x00100000UL) ///< Bit 20 mask of an 32 bit integer
+#define BIT21 (0x00200000UL) ///< Bit 21 mask of an 32 bit integer
+#define BIT22 (0x00400000UL) ///< Bit 22 mask of an 32 bit integer
+#define BIT23 (0x00800000UL) ///< Bit 23 mask of an 32 bit integer
+#define BIT24 (0x01000000UL) ///< Bit 24 mask of an 32 bit integer
+#define BIT25 (0x02000000UL) ///< Bit 25 mask of an 32 bit integer
+#define BIT26 (0x04000000UL) ///< Bit 26 mask of an 32 bit integer
+#define BIT27 (0x08000000UL) ///< Bit 27 mask of an 32 bit integer
+#define BIT28 (0x10000000UL) ///< Bit 28 mask of an 32 bit integer
+#define BIT29 (0x20000000UL) ///< Bit 29 mask of an 32 bit integer
+#define BIT30 (0x40000000UL) ///< Bit 30 mask of an 32 bit integer
+#define BIT31 (0x80000000UL) ///< Bit 31 mask of an 32 bit integer
+
+/* Byte Mask Definitions */
+#define BYTE0_Msk (0x000000FFUL) ///< Mask to get bit0~bit7 from a 32 bit integer
+#define BYTE1_Msk (0x0000FF00UL) ///< Mask to get bit8~bit15 from a 32 bit integer
+#define BYTE2_Msk (0x00FF0000UL) ///< Mask to get bit16~bit23 from a 32 bit integer
+#define BYTE3_Msk (0xFF000000UL) ///< Mask to get bit24~bit31 from a 32 bit integer
+
+#define GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */
+#define GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */
+#define GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
+#define GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
+
+/*@}*/ /* end of group Legacy_Constants */
+
+
+/******************************************************************************/
+/* Peripheral header files */
+/******************************************************************************/
+#include "m480_sys.h"
+#include "m480_clk.h"
+#include "m480_uart.h"
+#include "m480_gpio.h"
+#include "m480_fmc.h"
+#include "m480_rtc.h"
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __M480_H__ */
+
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Include/NuMicro.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Include/NuMicro.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,37 @@ +/**************************************************************************//** + * @file NuMicro.h + * @version V1.00 + * @brief NuMicro peripheral access layer header file. + * + * @copyright (C) 2017-2018 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *****************************************************************************/ +#ifndef __NUMICRO_H__ +#define __NUMICRO_H__ + +#include "M480.h" + +#endif /* __NUMICRO_H__ */ + +
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Include/m480_clk_reg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Include/m480_clk_reg.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1616 @@
+/**************************************************************************//**
+ * @file clk_reg.h
+ * @version V1.00
+ * @brief CLK register definition header file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/
+#ifndef __CLK_REG_H__
+#define __CLK_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup CLK System Clock Controller(CLK)
+ Memory Mapped Structure for CLK Controller
+@{ */
+
+typedef struct {
+
+
+ /**
+ * @var CLK_T::PWRCTL
+ * Offset: 0x00 System Power-down Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |HXTEN |HXT Enable Bit (Write Protect)
+ * | | |The bit default value is set by flash controller user configuration register CONFIG0 [26]
+ * | | |When the default clock source is from HXT, this bit is set to 1 automatically.
+ * | | |0 = 4~24 MHz external high speed crystal (HXT) Disabled.
+ * | | |1 = 4~24 MHz external high speed crystal (HXT) Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[1] |LXTEN |LXT Enable Bit (Write Protect)
+ * | | |0 = 32.768 kHz external low speed crystal (LXT) Disabled.
+ * | | |1 = 32.768 kHz external low speed crystal (LXT) Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[2] |HIRCEN |HIRC Enable Bit (Write Protect)
+ * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) Disabled.
+ * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[3] |LIRCEN |LIRC Enable Bit (Write Protect)
+ * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled.
+ * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[4] |PDWKDLY |Enable the Wake-up Delay Counter (Write Protect)
+ * | | |When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
+ * | | |The delayed clock cycle is 4096 clock cycles when chip works at 4~24 MHz external high speed crystal oscillator (HXT), and 256 clock cycles when chip works at 12 MHz internal high speed RC oscillator (HIRC).
+ * | | |0 = Clock cycles delay Disabled.
+ * | | |1 = Clock cycles delay Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[5] |PDWKIEN |Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)
+ * | | |0 = Power-down mode wake-up interrupt Disabled.
+ * | | |1 = Power-down mode wake-up interrupt Enabled.
+ * | | |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high.
+ * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status
+ * | | |Set by "Power-down wake-up event", it indicates that resume from Power-down mode.
+ * | | |The flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter.
+ * | | |Note1: Write 1 to clear the bit to 0.
+ * | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
+ * |[7] |PDEN |System Power-down Enable (Write Protect)
+ * | | |When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.
+ * | | |When chip wakes up from Power-down mode, this bit is auto cleared
+ * | | |Users need to set this bit again for next Power-down.
+ * | | |In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode.
+ * | | |In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection
+ * | | |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC.
+ * | | |0 = Chip will not enter Power-down mode after CPU sleep command WFI.
+ * | | |1 = Chip enters Power-down mode after CPU sleep command WFI.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[11:10] |HXTGAIN |HXT Gain Control Bit (Write Protect)
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |Gain control is used to enlarge the gain of crystal to make sure crystal work normally
+ * | | |If gain control is enabled, crystal will consume more power than gain control off.
+ * | | |00 = HXT frequency is lower than from 8 MHz.
+ * | | |01 = HXT frequency is from 8 MHz to 12 MHz.
+ * | | |10 = HXT frequency is from 12 MHz to 16 MHz.
+ * | | |11 = HXT frequency is higher than 16 MHz.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[12] |HXTSELTYP |HXT Crystal Type Select Bit (Write Protect)
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = Select INV type.
+ * | | |1 = Select GM type.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[13] |HXTTBEN |HXT Crystal TURBO Mode (Write Protect)
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = HXT Crystal TURBO mode disabled.
+ * | | |1 = HXT Crystal TURBO mode enabled.
+ * |[17:16] |HIRCSTBS |HIRC Stable Count Select (Write Protect)
+ * | | |00 = HIRC stable count is 64 clocks.
+ * | | |01 = HIRC stable count is 24 clocks.
+ * | | |others = Reserved.
+ * @var CLK_T::AHBCLK
+ * Offset: 0x04 AHB Devices Clock Enable Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |PDMACKEN |PDMA Controller Clock Enable Bit
+ * | | |0 = PDMA peripheral clock Disabled.
+ * | | |1 = PDMA peripheral clock Enabled.
+ * |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit
+ * | | |0 = Flash ISP peripheral clock Disabled.
+ * | | |1 = Flash ISP peripheral clock Enabled.
+ * |[3] |EBICKEN |EBI Controller Clock Enable Bit
+ * | | |0 = EBI peripheral clock Disabled.
+ * | | |1 = EBI peripheral clock Enabled.
+ * |[5] |EMACCKEN |Ethernet Controller Clock Enable Bit
+ * | | |0 = Ethernet Controller engine clock Disabled.
+ * | | |1 = Ethernet Controller engine clock Enabled.
+ * |[6] |SDH0CKEN |SD0 Controller Clock Enable Bit
+ * | | |0 = SD0 engine clock Disabled.
+ * | | |1 = SD0 engine clock Enabled.
+ * |[7] |CRCCKEN |CRC Generator Controller Clock Enable Bit
+ * | | |0 = CRC peripheral clock Disabled.
+ * | | |1 = CRC peripheral clock Enabled.
+ * |[10] |HSUSBDCKEN|HSUSB Device Clock Enable Bit
+ * | | |0 = HSUSB device controller's clock Disabled.
+ * | | |1 = HSUSB device controller's clock Enabled.
+ * |[12] |CRPTCKEN |Cryptographic Accelerator Clock Enable Bit
+ * | | |0 = Cryptographic Accelerator clock Disabled.
+ * | | |1 = Cryptographic Accelerator clock Enabled.
+ * |[14] |SPIMCKEN |SPIM Controller Clock Enable Bit
+ * | | |0 = SPIM controller clock Disabled.
+ * | | |1 = SPIM controller clock Enabled.
+ * |[15] |FMCIDLE |Flash Memory Controller Clock Enable Bit in IDLE Mode
+ * | | |0 = FMC clock Disabled when chip is under IDLE mode.
+ * | | |1 = FMC clock Enabled when chip is under IDLE mode.
+ * |[16] |USBHCKEN |USB HOST Controller Clock Enable Bit
+ * | | |0 = USB HOST peripheral clock Disabled.
+ * | | |1 = USB HOST peripheral clock Enabled.
+ * |[17] |SDH1CKEN |SD1 Controller Clock Enable Bit
+ * | | |0 = SD1 engine clock Disabled.
+ * | | |1 = SD1 engine clock Enabled.
+ * @var CLK_T::APBCLK0
+ * Offset: 0x08 APB Devices Clock Enable Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WDTCKEN |Watchdog Timer Clock Enable Bit (Write Protect)
+ * | | |0 = Watchdog timer clock Disabled.
+ * | | |1 = Watchdog timer clock Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[1] |RTCCKEN |Real-time-clock APB Interface Clock Enable Bit
+ * | | |This bit is used to control the RTC APB clock only
+ * | | |The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8])
+ * | | |It can be selected to 32.768 kHz external low speed crystal or 10 kHz internal low speed RC oscillator (LIRC).
+ * | | |0 = RTC clock Disabled.
+ * | | |1 = RTC clock Enabled.
+ * |[2] |TMR0CKEN |Timer0 Clock Enable Bit
+ * | | |0 = Timer0 clock Disabled.
+ * | | |1 = Timer0 clock Enabled.
+ * |[3] |TMR1CKEN |Timer1 Clock Enable Bit
+ * | | |0 = Timer1 clock Disabled.
+ * | | |1 = Timer1 clock Enabled.
+ * |[4] |TMR2CKEN |Timer2 Clock Enable Bit
+ * | | |0 = Timer2 clock Disabled.
+ * | | |1 = Timer2 clock Enabled.
+ * |[5] |TMR3CKEN |Timer3 Clock Enable Bit
+ * | | |0 = Timer3 clock Disabled.
+ * | | |1 = Timer3 clock Enabled.
+ * |[6] |CLKOCKEN |CLKO Clock Enable Bit
+ * | | |0 = CLKO clock Disabled.
+ * | | |1 = CLKO clock Enabled.
+ * |[7] |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit
+ * | | |0 = Analog comparator 0/1 clock Disabled.
+ * | | |1 = Analog comparator 0/1 clock Enabled.
+ * |[8] |I2C0CKEN |I2C0 Clock Enable Bit
+ * | | |0 = I2C0 clock Disabled.
+ * | | |1 = I2C0 clock Enabled.
+ * |[9] |I2C1CKEN |I2C1 Clock Enable Bit
+ * | | |0 = I2C1 clock Disabled.
+ * | | |1 = I2C1 clock Enabled.
+ * |[10] |I2C2CKEN |I2C2 Clock Enable Bit
+ * | | |0 = I2C2 clock Disabled.
+ * | | |1 = I2C2 clock Enabled.
+ * |[12] |QSPI0CKEN |QSPI0 Clock Enable Bit
+ * | | |0 = QSPI0 clock Disabled.
+ * | | |1 = QSPI0 clock Enabled.
+ * |[13] |SPI0CKEN |SPI0 Clock Enable Bit
+ * | | |0 = SPI0 clock Disabled.
+ * | | |1 = SPI0 clock Enabled.
+ * |[14] |SPI1CKEN |SPI1 Clock Enable Bit
+ * | | |0 = SPI1 clock Disabled.
+ * | | |1 = SPI1 clock Enabled.
+ * |[15] |SPI2CKEN |SPI2 Clock Enable Bit
+ * | | |0 = SPI2 clock Disabled.
+ * | | |1 = SPI2 clock Enabled.
+ * |[16] |UART0CKEN |UART0 Clock Enable Bit
+ * | | |0 = UART0 clock Disabled.
+ * | | |1 = UART0 clock Enabled.
+ * |[17] |UART1CKEN |UART1 Clock Enable Bit
+ * | | |0 = UART1 clock Disabled.
+ * | | |1 = UART1 clock Enabled.
+ * |[18] |UART2CKEN |UART2 Clock Enable Bit
+ * | | |0 = UART2 clock Disabled.
+ * | | |1 = UART2 clock Enabled.
+ * |[19] |UART3CKEN |UART3 Clock Enable Bit
+ * | | |0 = UART3 clock Disabled.
+ * | | |1 = UART3 clock Enabled.
+ * |[20] |UART4CKEN |UART4 Clock Enable Bit
+ * | | |0 = UART4 clock Disabled.
+ * | | |1 = UART4 clock Enabled.
+ * |[21] |UART5CKEN |UART5 Clock Enable Bit
+ * | | |0 = UART5 clock Disabled.
+ * | | |1 = UART5 clock Enabled.
+ * |[24] |CAN0CKEN |CAN0 Clock Enable Bit
+ * | | |0 = CAN0 clock Disabled.
+ * | | |1 = CAN0 clock Enabled.
+ * |[25] |CAN1CKEN |CAN1 Clock Enable Bit
+ * | | |0 = CAN1 clock Disabled.
+ * | | |1 = CAN1 clock Enabled.
+ * |[26] |OTGCKEN |USB OTG Clock Enable Bit
+ * | | |0 = USB OTG clock Disabled.
+ * | | |1 = USB OTG clock Enabled.
+ * |[27] |USBDCKEN |USB Device Clock Enable Bit
+ * | | |0 = USB Device clock Disabled.
+ * | | |1 = USB Device clock Enabled.
+ * |[28] |EADCCKEN |Enhanced Analog-digital-converter (EADC) Clock Enable Bit
+ * | | |0 = EADC clock Disabled.
+ * | | |1 = EADC clock Enabled.
+ * |[29] |I2S0CKEN |I2S0 Clock Enable Bit
+ * | | |0 = I2S0 Clock Disabled.
+ * | | |1 = I2S0 Clock Enabled.
+ * |[30] |HSOTGCKEN |HSUSB OTG Clock Enable Bit
+ * | | |0 = HSUSB OTG clock Disabled.
+ * | | |1 = HSUSB OTG clock Enabled.
+ * @var CLK_T::APBCLK1
+ * Offset: 0x0C APB Devices Clock Enable Control Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SC0CKEN |SC0 Clock Enable Bit
+ * | | |0 = SC0 clock Disabled.
+ * | | |1 = SC0 clock Enabled.
+ * |[1] |SC1CKEN |SC1 Clock Enable Bit
+ * | | |0 = SC1 clock Disabled.
+ * | | |1 = SC1 clock Enabled.
+ * |[2] |SC2CKEN |SC2 Clock Enable Bit
+ * | | |0 = SC2 clock Disabled.
+ * | | |1 = SC2 clock Enabled.
+ * |[6] |SPI3CKEN |SPI3 Clock Enable Bit
+ * | | |0 = SPI3 clock Disabled.
+ * | | |1 = SPI3 clock Enabled.
+ * |[8] |USCI0CKEN |USCI0 Clock Enable Bit
+ * | | |0 = USCI0 clock Disabled.
+ * | | |1 = USCI0 clock Enabled.
+ * |[9] |USCI1CKEN |USCI1 Clock Enable Bit
+ * | | |0 = USCI1 clock Disabled.
+ * | | |1 = USCI1 clock Enabled.
+ * |[12] |DACCKEN |DAC Clock Enable Bit
+ * | | |0 = DAC clock Disabled.
+ * | | |1 = DAC clock Enabled.
+ * |[16] |EPWM0CKEN |EPWM0 Clock Enable Bit
+ * | | |0 = EPWM0 clock Disabled.
+ * | | |1 = EPWM0 clock Enabled.
+ * |[17] |EPWM1CKEN |EPWM1 Clock Enable Bit
+ * | | |0 = EPWM1 clock Disabled.
+ * | | |1 = EPWM1 clock Enabled.
+ * |[18] |BPWM0CKEN |BPWM0 Clock Enable Bit
+ * | | |0 = BPWM0 clock Disabled.
+ * | | |1 = BPWM0 clock Enabled.
+ * |[19] |BPWM1CKEN |BPWM1 Clock Enable Bit
+ * | | |0 = BPWM1 clock Disabled.
+ * | | |1 = BPWM1 clock Enabled.
+ * |[22] |QEI0CKEN |QEI0 Clock Enable Bit
+ * | | |0 = QEI0 clock Disabled.
+ * | | |1 = QEI0 clock Enabled.
+ * |[23] |QEI1CKEN |QEI1 Clock Enable Bit
+ * | | |0 = QEI1 clock Disabled.
+ * | | |1 = QEI1 clock Enabled.
+ * |[26] |ECAP0CKEN |ECAP0 Clock Enable Bit
+ * | | |0 = ECAP0 clock Disabled.
+ * | | |1 = ECAP0 clock Enabled.
+ * |[27] |ECAP1CKEN |ECAP1 Clock Enable Bit
+ * | | |0 = ECAP1 clock Disabled.
+ * | | |1 = ECAP1 clock Enabled.
+ * |[30] |OPACKEN |OP Amplifier (OPA) Clock Enable Bit
+ * | | |0 = OPA clock Disabled.
+ * | | |1 = OPA clock Enabled.
+ * @var CLK_T::CLKSEL0
+ * Offset: 0x10 Clock Source Select Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |HCLKSEL |HCLK Clock Source Selection (Write Protect)
+ * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on.
+ * | | |The default value is reloaded from the value of CFOSC (CONFIG0[26]) in user configuration register of Flash controller by any reset
+ * | | |Therefore the default value is either 000b or 111b.
+ * | | |000 = Clock source from HXT.
+ * | | |001 = Clock source from LXT.
+ * | | |010 = Clock source from PLL.
+ * | | |011 = Clock source from LIRC.
+ * | | |111 = Clock source from HIRC.
+ * | | |Other = Reserved.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[5:3] |STCLKSEL |Cortex-M4 SysTick Clock Source Selection (Write Protect)
+ * | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below.
+ * | | |000 = Clock source from HXT.
+ * | | |001 = Clock source from LXT.
+ * | | |010 = Clock source from HXT/2.
+ * | | |011 = Clock source from HCLK/2.
+ * | | |111 = Clock source from HIRC/2.
+ * | | |Note: if SysTick clock source is not from HCLK (i.e
+ * | | |SYST_CTRL[2] = 0), SysTick clock source must less than or equal to HCLK/2.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[21:20] |SDH0SEL |SD0 Engine Clock Source Selection (Write Protect)
+ * | | |00 = Clock source from HXT clock.
+ * | | |01 = Clock source from PLL clock.
+ * | | |10 = Clock source from HCLK.
+ * | | |11 = Clock source from HIRC clock.
+ * |[23:22] |SDH1SEL |SD1 Engine Clock Source Selection (Write Protect)
+ * | | |00 = Clock source from HXT clock.
+ * | | |01 = Clock source from PLL clock.
+ * | | |10 = Clock source from HCLK.
+ * | | |11 = Clock source from HIRC clock.
+ * @var CLK_T::CLKSEL1
+ * Offset: 0x14 Clock Source Select Control Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect)
+ * | | |00 = Reserved.
+ * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |10 = Clock source from HCLK/2048.
+ * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[10:8] |TMR0SEL |TIMER0 Clock Source Selection
+ * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |010 = Clock source from PCLK0.
+ * | | |011 = Clock source from external clock TM0 pin.
+ * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+ * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * | | |Others = Reserved.
+ * |[14:12] |TMR1SEL |TIMER1 Clock Source Selection
+ * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |010 = Clock source from PCLK0.
+ * | | |011 = Clock source from external clock TM1 pin.
+ * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+ * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * | | |Others = Reserved.
+ * |[18:16] |TMR2SEL |TIMER2 Clock Source Selection
+ * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |010 = Clock source from PCLK1.
+ * | | |011 = Clock source from external clock TM2 pin.
+ * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+ * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * | | |Others = Reserved.
+ * |[22:20] |TMR3SEL |TIMER3 Clock Source Selection
+ * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |010 = Clock source from PCLK1.
+ * | | |011 = Clock source from external clock TM3 pin.
+ * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+ * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * | | |Others = Reserved.
+ * |[25:24] |UART0SEL |UART0 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[27:26] |UART1SEL |UART1 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[29:28] |CLKOSEL |Clock Divider Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |10 = Clock source from HCLK.
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[31:30] |WWDTSEL |Window Watchdog Timer Clock Source Selection
+ * | | |10 = Clock source from HCLK/2048.
+ * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+ * | | |Others = Reserved.
+ * @var CLK_T::CLKSEL2
+ * Offset: 0x18 Clock Source Select Control Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |EPWM0SEL |EPWM0 Clock Source Selection
+ * | | |The peripheral clock source of EPWM0 is defined by EPWM0SEL.
+ * | | |0 = Clock source from PLL.
+ * | | |1 = Clock source from PCLK0.
+ * |[1] |EPWM1SEL |EPWM1 Clock Source Selection
+ * | | |The peripheral clock source of EPWM1 is defined by EPWM1SEL.
+ * | | |0 = Clock source from PLL.
+ * | | |1 = Clock source from PCLK1.
+ * |[3:2] |QSPI0SEL |QSPI0 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from PCLK0.
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[5:4] |SPI0SEL |SPI0 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from PCLK1.
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[7:6] |SPI1SEL |SPI1 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from PCLK0.
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[8] |BPWM0SEL |BPWM0 Clock Source Selection
+ * | | |The peripheral clock source of BPWM0 is defined by BPWM0SEL.
+ * | | |0 = Clock source from PLL.
+ * | | |1 = Clock source from PCLK0.
+ * |[9] |BPWM1SEL |BPWM1 Clock Source Selection
+ * | | |The peripheral clock source of BPWM1 is defined by BPWM1SEL.
+ * | | |0 = Clock source from PLL.
+ * | | |1 = Clock source from PCLK1.
+ * |[11:10] |SPI2SEL |SPI2 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from PCLK1.
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[13:12] |SPI3SEL |SPI3 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from PCLK0.
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * @var CLK_T::CLKSEL3
+ * Offset: 0x1C Clock Source Select Control Register 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |SC0SEL |SC0 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from PCLK0.
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[3:2] |SC1SEL |SC0 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from PCLK1.
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[5:4] |SC2SEL |SC2 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from PCLK0.
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[8] |RTCSEL |RTC Clock Source Selection
+ * | | |0 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |1 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+ * |[17:16] |I2S0SEL |I2S0 Clock Source Selection
+ * | | |00 = Clock source from HXT clock.
+ * | | |01 = Clock source from PLL clock.
+ * | | |10 = Clock source from PCLK.
+ * | | |11 = Clock source from HIRC clock.
+ * |[25:24] |UART2SEL |UART2 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[27:26] |UART3SEL |UART3 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[29:28] |UART4SEL |UART4 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * |[31:30] |UART5SEL |UART5 Clock Source Selection
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+ * | | |01 = Clock source from PLL.
+ * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+ * @var CLK_T::CLKDIV0
+ * Offset: 0x20 Clock Divider Number Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |HCLKDIV |HCLK Clock Divide Number From HCLK Clock Source
+ * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1).
+ * |[7:4] |USBDIV |USB Clock Divide Number From PLL Clock
+ * | | |USB clock frequency = (PLL frequency) / (USBDIV + 1).
+ * |[11:8] |UART0DIV |UART0 Clock Divide Number From UART0 Clock Source
+ * | | |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1).
+ * |[15:12] |UART1DIV |UART1 Clock Divide Number From UART1 Clock Source
+ * | | |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1).
+ * |[23:16] |EADCDIV |EADC Clock Divide Number From EADC Clock Source
+ * | | |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1).
+ * |[31:24] |SDH0DIV |SD0 Clock Divide Number From SD0 Clock Source
+ * | | |SD0 clock frequency = (SD0 clock source frequency) / (SDH0DIV + 1).
+ * @var CLK_T::CLKDIV1
+ * Offset: 0x24 Clock Divider Number Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |SC0DIV |SC0 Clock Divide Number From SC0 Clock Source
+ * | | |SC0 clock frequency = (SC0 clock source frequency ) / (SC0DIV + 1).
+ * |[15:8] |SC1DIV |SC1 Clock Divide Number From SC1 Clock Source
+ * | | |SC1 clock frequency = (SC1 clock source frequency ) / (SC1DIV + 1).
+ * |[23:16] |SC2DIV |SC2 Clock Divide Number From SC2 Clock Source
+ * | | |SC2 clock frequency = (SC2 clock source frequency ) / (SC2DIV + 1).
+ * @var CLK_T::CLKDIV3
+ * Offset: 0x2C Clock Divider Number Register 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |EMACDIV |Ethernet Clock Divide Number Form HCLK
+ * | | |EMAC MDCLK clock frequency = (HCLK) / (EMACDIV + 1).
+ * |[31:24] |SDH1DIV |SD1 Clock Divide Number From SD1 Clock Source
+ * | | |SD1 clock frequency = (SD1 clock source frequency) / (SDH1DIV + 1).
+ * @var CLK_T::CLKDIV4
+ * Offset: 0x30 Clock Divider Number Register 4
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |UART2DIV |UART2 Clock Divide Number From UART2 Clock Source
+ * | | |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1).
+ * |[7:4] |UART3DIV |UART3 Clock Divide Number From UART3 Clock Source
+ * | | |UART3 clock frequency = (UART3 clock source frequency) / (UART3DIV + 1).
+ * |[11:8] |UART4DIV |UART4 Clock Divide Number From UART4 Clock Source
+ * | | |UART4 clock frequency = (UART4 clock source frequency) / (UART4DIV + 1).
+ * |[15:12] |UART5DIV |UART5 Clock Divide Number From UART5 Clock Source
+ * | | |UART5 clock frequency = (UART5 clock source frequency) / (UART5DIV + 1).
+ * @var CLK_T::PCLKDIV
+ * Offset: 0x34 APB Clock Divider Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |APB0DIV |APB0 Clock Divider
+ * | | |APB0 clock can be divided from HCLK
+ * | | |000: PCLK0 = HCLK.
+ * | | |001: PCLK0 = 1/2 HCLK.
+ * | | |010: PCLK0 = 1/4 HCLK.
+ * | | |011: PCLK0 = 1/8 HCLK.
+ * | | |100: PCLK0 = 1/16 HCLK.
+ * | | |Others: Reserved.
+ * |[6:4] |APB1DIV |APB1 Clock Divider
+ * | | |APB1 clock can be divided from HCLK
+ * | | |000: PCLK1 = HCLK.
+ * | | |001: PCLK1 = 1/2 HCLK.
+ * | | |010: PCLK1 = 1/4 HCLK.
+ * | | |011: PCLK1 = 1/8 HCLK.
+ * | | |100: PCLK1 = 1/16 HCLK.
+ * | | |Others: Reserved.
+ * @var CLK_T::PLLCTL
+ * Offset: 0x40 PLL Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8:0] |FBDIV |PLL Feedback Divider Control (Write Protect)
+ * | | |Refer to the formulas below the table.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[13:9] |INDIV |PLL Input Divider Control (Write Protect)
+ * | | |Refer to the formulas below the table.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[15:14] |OUTDIV |PLL Output Divider Control (Write Protect)
+ * | | |Refer to the formulas below the table.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[16] |PD |Power-down Mode (Write Protect)
+ * | | |If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.
+ * | | |0 = PLL is in normal mode.
+ * | | |1 = PLL is in Power-down mode (default).
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[17] |BP |PLL Bypass Control (Write Protect)
+ * | | |0 = PLL is in normal mode (default).
+ * | | |1 = PLL clock output is same as PLL input clock FIN.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[18] |OE |PLL OE (FOUT Enable) Pin Control (Write Protect)
+ * | | |0 = PLL FOUT Enabled.
+ * | | |1 = PLL FOUT is fixed low.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[19] |PLLSRC |PLL Source Clock Selection (Write Protect)
+ * | | |0 = PLL source clock from 4~24 MHz external high-speed crystal oscillator (HXT).
+ * | | |1 = PLL source clock from 12 MHz internal high-speed oscillator (HIRC).
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[23] |STBSEL |PLL Stable Counter Selection (Write Protect)
+ * | | |0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12 MHz).
+ * | | |1 = PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12 MHz).
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[28] |BANDSEL |PLL Stable Counter Selection (Write Protect)
+ * | | |0 = PLL low band frequency select. (FVCO range is 200MHz ~ 400MHZ)
+ * | | |1 = PLL high band frequency select. (FVCO range is 400MHz ~ 500MHZ)
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var CLK_T::STATUS
+ * Offset: 0x50 Clock Status Monitor Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |HXTSTB |HXT Clock Source Stable Flag (Read Only)
+ * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled.
+ * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled.
+ * |[1] |LXTSTB |LXT Clock Source Stable Flag (Read Only)
+ * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled.
+ * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled.
+ * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only)
+ * | | |0 = Internal PLL clock is not stable or disabled.
+ * | | |1 = Internal PLL clock is stable and enabled.
+ * |[3] |LIRCSTB |LIRC Clock Source Stable Flag (Read Only)
+ * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled.
+ * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled.
+ * |[4] |HIRCSTB |HIRC Clock Source Stable Flag (Read Only)
+ * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled.
+ * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled.
+ * | | |Note: This bit is read only.
+ * |[7] |CLKSFAIL |Clock Switching Fail Flag (Read Only)
+ * | | |This bit is updated when software switches system clock source
+ * | | |If switch target clock is stable, this bit will be set to 0
+ * | | |If switch target clock is not stable, this bit will be set to 1.
+ * | | |0 = Clock switching success.
+ * | | |1 = Clock switching failure.
+ * | | |Note: Write 1 to clear the bit to 0.
+ * @var CLK_T::CLKOCTL
+ * Offset: 0x60 Clock Output Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |FREQSEL |Clock Output Frequency Selection
+ * | | |The formula of output frequency is
+ * | | |Fout = Fin/2(N+1).
+ * | | |Fin is the input clock frequency.
+ * | | |Fout is the frequency of divider output clock.
+ * | | |N is the 4-bit value of FREQSEL[3:0].
+ * |[4] |CLKOEN |Clock Output Enable Bit
+ * | | |0 = Clock Output function Disabled.
+ * | | |1 = Clock Output function Enabled.
+ * |[5] |DIV1EN |Clock Output Divide One Enable Bit
+ * | | |0 = Clock Output will output clock with source frequency divided by FREQSEL.
+ * | | |1 = Clock Output will output clock with source frequency.
+ * |[6] |CLK1HZEN |Clock Output 1Hz Enable Bit
+ * | | |0 = 1 Hz clock output for 32.768 kHz frequency compensation Disabled.
+ * | | |1 = 1 Hz clock output for 32.768 kHz frequency compensation Enabled.
+ * @var CLK_T::CLKDCTL
+ * Offset: 0x70 Clock Fail Detector Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit
+ * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled.
+ * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled.
+ * |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit
+ * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled.
+ * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled.
+ * |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit
+ * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled.
+ * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled.
+ * |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit
+ * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled.
+ * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled.
+ * |[16] |HXTFQDEN |HXT Clock Frequency Range Detector Enable Bit
+ * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Disabled.
+ * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Enabled.
+ * |[17] |HXTFQIEN |HXT Clock Frequency Range Detector Interrupt Enable Bit
+ * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled.
+ * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled.
+ * @var CLK_T::CLKDSTS
+ * Offset: 0x74 Clock Fail Detector Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |HXTFIF |HXT Clock Fail Interrupt Flag
+ * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal.
+ * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock stops.
+ * | | |Note: Write 1 to clear the bit to 0.
+ * |[1] |LXTFIF |LXT Clock Fail Interrupt Flag
+ * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal.
+ * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) stops.
+ * | | |Note: Write 1 to clear the bit to 0.
+ * |[8] |HXTFQIF |HXT Clock Frequency Range Detector Interrupt Flag
+ * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is normal.
+ * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal.
+ * | | |Note: Write 1 to clear the bit to 0.
+ * @var CLK_T::CDUPB
+ * Offset: 0x78 Clock Frequency Range Detector Upper Boundary Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[9:0] |UPERBD |HXT Clock Frequency Range Detector Upper Boundary Value
+ * | | |The bits define the maximum value of frequency range detector window.
+ * | | |When HXT frequency higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1.
+ * @var CLK_T::CDLOWB
+ * Offset: 0x7C Clock Frequency Range Detector Lower Boundary Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[9:0] |LOWERBD |HXT Clock Frequency Range Detector Lower Boundary Value
+ * | | |The bits define the minimum value of frequency range detector window.
+ * | | |When HXT frequency lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1.
+ * @var CLK_T::PMUCTL
+ * Offset: 0x90 Power Manager Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |PDMSEL |Power-down Mode Selection (Write Protect)
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |These bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction.
+ * | | |000 = Power-down mode is selected. (PD)
+ * | | |001 = Low leakage Power-down mode is selected (LLPD).
+ * | | |010 =Fast wake-up Power-down mode is selected (FWPD).
+ * | | |011 = Reserved.
+ * | | |100 = Standby Power-down mode 0 is selected (SPD0) (SRAM retention).
+ * | | |101 = Standby Power-down mode 1 is selected (SPD1).
+ * | | |110 = Deep Power-down mode is selected (DPD).
+ * | | |111 = Reserved.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[8] |WKTMREN |Wake-up Timer Enable (Write Protect)
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = Wake-up timer disable at DPD/SPD mode.
+ * | | |1 = Wake-up timer enabled at DPD/SPD mode.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[11:9] |WKTMRIS |Wake-up Timer Time-out Interval Select (Write Protect)
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |These bits control wake-up timer time-out interval when chip at DPD/SPD mode.
+ * | | |000 = Time-out interval is 128 OSC10K clocks (12.8 ms).
+ * | | |001 = Time-out interval is 256 OSC10K clocks (25.6 ms).
+ * | | |010 = Time-out interval is 512 OSC10K clocks (51.2 ms).
+ * | | |011 = Time-out interval is 1024 OSC10K clocks (102.4ms).
+ * | | |100 = Time-out interval is 4096 OSC10K clocks (409.6ms).
+ * | | |101 = Time-out interval is 8192 OSC10K clocks (819.2ms).
+ * | | |110 = Time-out interval is 16384 OSC10K clocks (1638.4ms).
+ * | | |111 = Time-out interval is 65536 OSC10K clocks (6553.6ms).
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[17:16] |WKPINEN |Wake-up Pin Enable (Write Protect)
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |00 = Wake-up pin disable at Deep Power-down mode.
+ * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode.
+ * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode.
+ * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[18] |ACMPSPWK |ACMP Standby Power-down Mode Wake-up Enable (Write Protect)
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = ACMP wake-up disable at Standby Power-down mode.
+ * | | |1 = ACMP wake-up enabled at Standby Power-down mode.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[23] |RTCWKEN |RTC Wake-up Enable (Write Protect)
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = RTC wake-up disable at Deep Power-down mode or Standby Power-down mode.
+ * | | |1 = RTC wake-up enabled at Deep Power-down mode or Standby Power-down mode.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var CLK_T::PMUSTS
+ * Offset: 0x94 Power Manager Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PINWK |Pin Wake-up Flag (Read Only)
+ * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPC.0)
+ * | | |This flag is cleared when DPD mode is entered.
+ * |[1] |TMRWK |Timer Wake-up Flag (Read Only)
+ * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out
+ * | | |This flag is cleared when DPD or SPD mode is entered.
+ * |[2] |RTCWK |RTC Wake-up Flag (Read Only)
+ * | | |This flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RTC alarm, tick time or tamper happened
+ * | | |This flag is cleared when DPD or SPD mode is entered.
+ * |[8] |GPAWK |GPA Wake-up Flag (Read Only)
+ * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPA group pins
+ * | | |This flag is cleared when SPD mode is entered.
+ * |[9] |GPBWK |GPB Wake-up Flag (Read Only)
+ * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPB group pins
+ * | | |This flag is cleared when SPD mode is entered.
+ * |[10] |GPCWK |GPC Wake-up Flag (Read Only)
+ * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPC group pins
+ * | | |This flag is cleared when SPD mode is entered.
+ * |[11] |GPDWK |GPD Wake-up Flag (Read Only)
+ * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPD group pins
+ * | | |This flag is cleared when SPD mode is entered.
+ * |[12] |LVRWK |LVR Wake-up Flag (Read Only)
+ * | | |This flag indicates that wakeup of device from Standby Power-down mode was requested with a LVR happened
+ * | | |This flag is cleared when SPD mode is entered.
+ * |[13] |BODWK |BOD Wake-up Flag (Read Only)
+ * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a BOD happened
+ * | | |This flag is cleared when SPD mode is entered.
+ * |[14] |ACMPWK |ACMP Wake-up Flag (Read Only)
+ * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a ACMP transition
+ * | | |This flag is cleared when SPD mode is entered.
+ * |[31] |CLRWK |Clear Wake-up Flag
+ * | | |0 = No clear.
+ * | | |1 = Clear all wake-up flag.
+ * @var CLK_T::LDOCTL
+ * Offset: 0x98 LDO Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[18] |PDBIASEN |Power-down Bias Enable Bit
+ * | | |0 = Reserved.
+ * | | |1 = Power-down bias enabled.
+ * | | |Note: This bit should set to 1 before chip enter power-down mode.
+ * @var CLK_T::SWKDBCTL
+ * Offset: 0x9C Standby Power-down Wake-up De-bounce Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |SWKDBCLKSEL|Standby Power-down Wake-up De-bounce Sampling Cycle Selection
+ * | | |0000 = Sample wake-up input once per 1 clocks.
+ * | | |0001 = Sample wake-up input once per 2 clocks.
+ * | | |0010 = Sample wake-up input once per 4 clocks.
+ * | | |0011 = Sample wake-up input once per 8 clocks.
+ * | | |0100 = Sample wake-up input once per 16 clocks.
+ * | | |0101 = Sample wake-up input once per 32 clocks.
+ * | | |0110 = Sample wake-up input once per 64 clocks.
+ * | | |0111 = Sample wake-up input once per 128 clocks.
+ * | | |1000 = Sample wake-up input once per 256 clocks.
+ * | | |1001 = Sample wake-up input once per 2*256 clocks.
+ * | | |1010 = Sample wake-up input once per 4*256 clocks.
+ * | | |1011 = Sample wake-up input once per 8*256 clocks.
+ * | | |1100 = Sample wake-up input once per 16*256 clocks.
+ * | | |1101 = Sample wake-up input once per 32*256 clocks.
+ * | | |1110 = Sample wake-up input once per 64*256 clocks.
+ * | | |1111 = Sample wake-up input once per 128*256 clocks.
+ * | | |Note: De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC).
+ * @var CLK_T::PASWKCTL
+ * Offset: 0xA0 GPA Standby Power-down Wake-up Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit
+ * | | |0 = GPA group pin wake-up function disabled.
+ * | | |1 = GPA group pin wake-up function enabled.
+ * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit
+ * | | |0 = GPA group pin rising edge wake-up function disabled.
+ * | | |1 = GPA group pin rising edge wake-up function enabled.
+ * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit
+ * | | |0 = GPA group pin falling edge wake-up function disabled.
+ * | | |1 = GPA group pin falling edge wake-up function enabled.
+ * |[7:4] |WKPSEL |GPA Standby Power-down Wake-up Pin Select
+ * | | |0000 = GPA.0 wake-up function enabled.
+ * | | |0001 = GPA.1 wake-up function enabled.
+ * | | |0010 = GPA.2 wake-up function enabled.
+ * | | |0011 = GPA.3 wake-up function enabled.
+ * | | |0100 = GPA.4 wake-up function enabled.
+ * | | |0101 = GPA.5 wake-up function enabled.
+ * | | |0110 = GPA.6 wake-up function enabled.
+ * | | |0111 = GPA.7 wake-up function enabled.
+ * | | |1000 = GPA.8 wake-up function enabled.
+ * | | |1001 = GPA.9 wake-up function enabled.
+ * | | |1010 = GPA.10 wake-up function enabled.
+ * | | |1011 = GPA.11 wake-up function enabled.
+ * | | |1100 = GPA.12 wake-up function enabled.
+ * | | |1101 = GPA.13 wake-up function enabled.
+ * | | |1110 = GPA.14 wake-up function enabled.
+ * | | |1111 = GPA.15 wake-up function enabled.
+ * |[8] |DBEN |GPA Input Signal De-bounce Enable Bit
+ * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO
+ * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up
+ * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator.
+ * | | |0 = Standby power-down wake-up pin De-bounce function disable.
+ * | | |1 = Standby power-down wake-up pin De-bounce function enable.
+ * | | |The de-bounce function is valid only for edge triggered.
+ * @var CLK_T::PBSWKCTL
+ * Offset: 0xA4 GPB Standby Power-down Wake-up Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit
+ * | | |0 = GPB group pin wake-up function disabled.
+ * | | |1 = GPB group pin wake-up function enabled.
+ * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit
+ * | | |0 = GPB group pin rising edge wake-up function disabled.
+ * | | |1 = GPB group pin rising edge wake-up function enabled.
+ * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit
+ * | | |0 = GPB group pin falling edge wake-up function disabled.
+ * | | |1 = GPB group pin falling edge wake-up function enabled.
+ * |[7:4] |WKPSEL |GPB Standby Power-down Wake-up Pin Select
+ * | | |0000 = GPB.0 wake-up function enabled.
+ * | | |0001 = GPB.1 wake-up function enabled.
+ * | | |0010 = GPB.2 wake-up function enabled.
+ * | | |0011 = GPB.3 wake-up function enabled.
+ * | | |0100 = GPB.4 wake-up function enabled.
+ * | | |0101 = GPB.5 wake-up function enabled.
+ * | | |0110 = GPB.6 wake-up function enabled.
+ * | | |0111 = GPB.7 wake-up function enabled.
+ * | | |1000 = GPB.8 wake-up function enabled.
+ * | | |1001 = GPB.9 wake-up function enabled.
+ * | | |1010 = GPB.10 wake-up function enabled.
+ * | | |1011 = GPB.11 wake-up function enabled.
+ * | | |1100 = GPB.12 wake-up function enabled.
+ * | | |1101 = GPB.13 wake-up function enabled.
+ * | | |1110 = GPB.14 wake-up function enabled.
+ * | | |1111 = GPB.15 wake-up function enabled.
+ * |[8] |DBEN |GPB Input Signal De-bounce Enable Bit
+ * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO
+ * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up
+ * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator.
+ * | | |0 = Standby power-down wake-up pin De-bounce function disable.
+ * | | |1 = Standby power-down wake-up pin De-bounce function enable.
+ * | | |The de-bounce function is valid only for edge triggered.
+ * @var CLK_T::PCSWKCTL
+ * Offset: 0xA8 GPC Standby Power-down Wake-up Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit
+ * | | |0 = GPC group pin wake-up function disabled.
+ * | | |1 = GPC group pin wake-up function enabled.
+ * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit
+ * | | |0 = GPC group pin rising edge wake-up function disabled.
+ * | | |1 = GPC group pin rising edge wake-up function enabled.
+ * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit
+ * | | |0 = GPC group pin falling edge wake-up function disabled.
+ * | | |1 = GPC group pin falling edge wake-up function enabled.
+ * |[7:4] |WKPSEL |GPC Standby Power-down Wake-up Pin Select
+ * | | |0000 = GPC.0 wake-up function enabled.
+ * | | |0001 = GPC.1 wake-up function enabled.
+ * | | |0010 = GPC.2 wake-up function enabled.
+ * | | |0011 = GPC.3 wake-up function enabled.
+ * | | |0100 = GPC.4 wake-up function enabled.
+ * | | |0101 = GPC.5 wake-up function enabled.
+ * | | |0110 = GPC.6 wake-up function enabled.
+ * | | |0111 = GPC.7 wake-up function enabled.
+ * | | |1000 = GPC.8 wake-up function enabled.
+ * | | |1001 = GPC.9 wake-up function enabled.
+ * | | |1010 = GPC.10 wake-up function enabled.
+ * | | |1011 = GPC.11 wake-up function enabled.
+ * | | |1100 = GPC.12 wake-up function enabled.
+ * | | |1101 = GPC.13 wake-up function enabled.
+ * | | |1110 = GPC.14 wake-up function enabled.
+ * | | |1111 = GPC.15 wake-up function enabled.
+ * |[8] |DBEN |GPC Input Signal De-bounce Enable Bit
+ * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO
+ * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up
+ * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator.
+ * | | |0 = Standby power-down wake-up pin De-bounce function disable.
+ * | | |1 = Standby power-down wake-up pin De-bounce function enable.
+ * | | |The de-bounce function is valid only for edge triggered.
+ * @var CLK_T::PDSWKCTL
+ * Offset: 0xAC GPD Standby Power-down Wake-up Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit
+ * | | |0 = GPD group pin wake-up function disabled.
+ * | | |1 = GPD group pin wake-up function enabled.
+ * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit
+ * | | |0 = GPD group pin rising edge wake-up function disabled.
+ * | | |1 = GPD group pin rising edge wake-up function enabled.
+ * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit
+ * | | |0 = GPD group pin falling edge wake-up function disabled.
+ * | | |1 = GPD group pin falling edge wake-up function enabled.
+ * |[7:4] |WKPSEL |GPD Standby Power-down Wake-up Pin Select
+ * | | |0000 = GPD.0 wake-up function enabled.
+ * | | |0001 = GPD.1 wake-up function enabled.
+ * | | |0010 = GPD.2 wake-up function enabled.
+ * | | |0011 = GPD.3 wake-up function enabled.
+ * | | |0100 = GPD.4 wake-up function enabled.
+ * | | |0101 = GPD.5 wake-up function enabled.
+ * | | |0110 = GPD.6 wake-up function enabled.
+ * | | |0111 = GPD.7 wake-up function enabled.
+ * | | |1000 = GPD.8 wake-up function enabled.
+ * | | |1001 = GPD.9 wake-up function enabled.
+ * | | |1010 = GPD.10 wake-up function enabled.
+ * | | |1011 = GPD.11 wake-up function enabled.
+ * | | |1100 = GPD.12 wake-up function enabled.
+ * | | |1101 = GPD.13 wake-up function enabled.
+ * | | |1110 = GPD.14 wake-up function enabled.
+ * | | |1111 = GPD.15 wake-up function enabled.
+ * |[8] |DBEN |GPD Input Signal De-bounce Enable Bit
+ * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO
+ * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up
+ * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator.
+ * | | |0 = Standby power-down wake-up pin De-bounce function disable.
+ * | | |1 = Standby power-down wake-up pin De-bounce function enable.
+ * | | |The de-bounce function is valid only for edge triggered.
+ * @var CLK_T::IOPDCTL
+ * Offset: 0xB0 GPIO Standby Power-down Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |IOHR |GPIO Hold Release
+ * | | |When GPIO enter standby power-down mode, all I/O status are hold to keep normal operating status
+ * | | |After chip was waked up from standby power-down mode, the I/O are still keep hold status until user set this bit to release I/O hold status.
+ * | | |This bit is auto cleared by hardware.
+ */
+ __IO uint32_t PWRCTL; /*!< [0x0000] System Power-down Control Register */
+ __IO uint32_t AHBCLK; /*!< [0x0004] AHB Devices Clock Enable Control Register */
+ __IO uint32_t APBCLK0; /*!< [0x0008] APB Devices Clock Enable Control Register 0 */
+ __IO uint32_t APBCLK1; /*!< [0x000c] APB Devices Clock Enable Control Register 1 */
+ __IO uint32_t CLKSEL0; /*!< [0x0010] Clock Source Select Control Register 0 */
+ __IO uint32_t CLKSEL1; /*!< [0x0014] Clock Source Select Control Register 1 */
+ __IO uint32_t CLKSEL2; /*!< [0x0018] Clock Source Select Control Register 2 */
+ __IO uint32_t CLKSEL3; /*!< [0x001c] Clock Source Select Control Register 3 */
+ __IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 */
+ __IO uint32_t CLKDIV1; /*!< [0x0024] Clock Divider Number Register 1 */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE0[1];
+ /** @endcond */
+ __IO uint32_t CLKDIV3; /*!< [0x002c] Clock Divider Number Register 3 */
+ __IO uint32_t CLKDIV4; /*!< [0x0030] Clock Divider Number Register 4 */
+ __IO uint32_t PCLKDIV; /*!< [0x0034] APB Clock Divider Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE1[2];
+ /** @endcond */
+ __IO uint32_t PLLCTL; /*!< [0x0040] PLL Control Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE2[3];
+ /** @endcond */
+ __I uint32_t STATUS; /*!< [0x0050] Clock Status Monitor Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE3[3];
+ /** @endcond */
+ __IO uint32_t CLKOCTL; /*!< [0x0060] Clock Output Control Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE4[3];
+ /** @endcond */
+ __IO uint32_t CLKDCTL; /*!< [0x0070] Clock Fail Detector Control Register */
+ __IO uint32_t CLKDSTS; /*!< [0x0074] Clock Fail Detector Status Register */
+ __IO uint32_t CDUPB; /*!< [0x0078] Clock Frequency Range Detector Upper Boundary Register */
+ __IO uint32_t CDLOWB; /*!< [0x007c] Clock Frequency Range Detector Lower Boundary Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE5[4];
+ /** @endcond */
+ __IO uint32_t PMUCTL; /*!< [0x0090] Power Manager Control Register */
+ __IO uint32_t PMUSTS; /*!< [0x0094] Power Manager Status Register */
+ __IO uint32_t LDOCTL; /*!< [0x0098] LDO Control Register */
+ __IO uint32_t SWKDBCTL; /*!< [0x009c] Standby Power-down Wake-up De-bounce Control Register */
+ __IO uint32_t PASWKCTL; /*!< [0x00a0] GPA Standby Power-down Wake-up Control Register */
+ __IO uint32_t PBSWKCTL; /*!< [0x00a4] GPB Standby Power-down Wake-up Control Register */
+ __IO uint32_t PCSWKCTL; /*!< [0x00a8] GPC Standby Power-down Wake-up Control Register */
+ __IO uint32_t PDSWKCTL; /*!< [0x00ac] GPD Standby Power-down Wake-up Control Register */
+ __IO uint32_t IOPDCTL; /*!< [0x00b0] GPIO Standby Power-down Control Register */
+
+} CLK_T;
+
+/**
+ @addtogroup CLK_CONST CLK Bit Field Definition
+ Constant Definitions for CLK Controller
+@{ */
+
+#define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */
+#define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */
+
+#define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */
+#define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */
+
+#define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */
+#define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */
+
+#define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */
+#define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */
+
+#define CLK_PWRCTL_PDWKDLY_Pos (4) /*!< CLK_T::PWRCTL: PDWKDLY Position */
+#define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) /*!< CLK_T::PWRCTL: PDWKDLY Mask */
+
+#define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK_T::PWRCTL: PDWKIEN Position */
+#define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK_T::PWRCTL: PDWKIEN Mask */
+
+#define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK_T::PWRCTL: PDWKIF Position */
+#define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK_T::PWRCTL: PDWKIF Mask */
+
+#define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK_T::PWRCTL: PDEN Position */
+#define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK_T::PWRCTL: PDEN Mask */
+
+#define CLK_PWRCTL_HXTGAIN_Pos (10) /*!< CLK_T::PWRCTL: HXTGAIN Position */
+#define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos) /*!< CLK_T::PWRCTL: HXTGAIN Mask */
+
+#define CLK_PWRCTL_HXTSELTYP_Pos (12) /*!< CLK_T::PWRCTL: HXTSELTYP Position */
+#define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos) /*!< CLK_T::PWRCTL: HXTSELTYP Mask */
+
+#define CLK_PWRCTL_HXTTBEN_Pos (13) /*!< CLK_T::PWRCTL: HXTTBEN Position */
+#define CLK_PWRCTL_HXTTBEN_Msk (0x1ul << CLK_PWRCTL_HXTTBEN_Pos) /*!< CLK_T::PWRCTL: HXTTBEN Mask */
+
+#define CLK_PWRCTL_HIRCSTBS_Pos (16) /*!< CLK_T::PWRCTL: HIRCSTBS Position */
+#define CLK_PWRCTL_HIRCSTBS_Msk (0x3ul << CLK_PWRCTL_HIRCSTBS_Pos) /*!< CLK_T::PWRCTL: HIRCSTBS Mask */
+
+#define CLK_AHBCLK_PDMACKEN_Pos (1) /*!< CLK_T::AHBCLK: PDMACKEN Position */
+#define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos) /*!< CLK_T::AHBCLK: PDMACKEN Mask */
+
+#define CLK_AHBCLK_ISPCKEN_Pos (2) /*!< CLK_T::AHBCLK: ISPCKEN Position */
+#define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) /*!< CLK_T::AHBCLK: ISPCKEN Mask */
+
+#define CLK_AHBCLK_EBICKEN_Pos (3) /*!< CLK_T::AHBCLK: EBICKEN Position */
+#define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) /*!< CLK_T::AHBCLK: EBICKEN Mask */
+
+#define CLK_AHBCLK_EMACCKEN_Pos (5) /*!< CLK_T::AHBCLK: EMACCKEN Position */
+#define CLK_AHBCLK_EMACCKEN_Msk (0x1ul << CLK_AHBCLK_EMACCKEN_Pos) /*!< CLK_T::AHBCLK: EMACCKEN Mask */
+
+#define CLK_AHBCLK_SDH0CKEN_Pos (6) /*!< CLK_T::AHBCLK: SDH0CKEN Position */
+#define CLK_AHBCLK_SDH0CKEN_Msk (0x1ul << CLK_AHBCLK_SDH0CKEN_Pos) /*!< CLK_T::AHBCLK: SDH0CKEN Mask */
+
+#define CLK_AHBCLK_CRCCKEN_Pos (7) /*!< CLK_T::AHBCLK: CRCCKEN Position */
+#define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) /*!< CLK_T::AHBCLK: CRCCKEN Mask */
+
+#define CLK_AHBCLK_HSUSBDCKEN_Pos (10) /*!< CLK_T::AHBCLK: HSUSBDCKEN Position */
+#define CLK_AHBCLK_HSUSBDCKEN_Msk (0x1ul << CLK_AHBCLK_HSUSBDCKEN_Pos) /*!< CLK_T::AHBCLK: HSUSBDCKEN Mask */
+
+#define CLK_AHBCLK_CRPTCKEN_Pos (12) /*!< CLK_T::AHBCLK: CRPTCKEN Position */
+#define CLK_AHBCLK_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos) /*!< CLK_T::AHBCLK: CRPTCKEN Mask */
+
+#define CLK_AHBCLK_SPIMCKEN_Pos (14) /*!< CLK_T::AHBCLK: SPIMCKEN Position */
+#define CLK_AHBCLK_SPIMCKEN_Msk (0x1ul << CLK_AHBCLK_SPIMCKEN_Pos) /*!< CLK_T::AHBCLK: SPIMCKEN Mask */
+
+#define CLK_AHBCLK_FMCIDLE_Pos (15) /*!< CLK_T::AHBCLK: FMCIDLE Position */
+#define CLK_AHBCLK_FMCIDLE_Msk (0x1ul << CLK_AHBCLK_FMCIDLE_Pos) /*!< CLK_T::AHBCLK: FMCIDLE Mask */
+
+#define CLK_AHBCLK_USBHCKEN_Pos (16) /*!< CLK_T::AHBCLK: USBHCKEN Position */
+#define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) /*!< CLK_T::AHBCLK: USBHCKEN Mask */
+
+#define CLK_AHBCLK_SDH1CKEN_Pos (17) /*!< CLK_T::AHBCLK: SDH1CKEN Position */
+#define CLK_AHBCLK_SDH1CKEN_Msk (0x1ul << CLK_AHBCLK_SDH1CKEN_Pos) /*!< CLK_T::AHBCLK: SDH1CKEN Mask */
+
+#define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK_T::APBCLK0: WDTCKEN Position */
+#define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK_T::APBCLK0: WDTCKEN Mask */
+
+#define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK_T::APBCLK0: RTCCKEN Position */
+#define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */
+
+#define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR0CKEN Position */
+#define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */
+
+#define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR1CKEN Position */
+#define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */
+
+#define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR2CKEN Position */
+#define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */
+
+#define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR3CKEN Position */
+#define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */
+
+#define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK_T::APBCLK0: CLKOCKEN Position */
+#define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK_T::APBCLK0: CLKOCKEN Mask */
+
+#define CLK_APBCLK0_ACMP01CKEN_Pos (7) /*!< CLK_T::APBCLK0: ACMP01CKEN Position */
+#define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) /*!< CLK_T::APBCLK0: ACMP01CKEN Mask */
+
+#define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK_T::APBCLK0: I2C0CKEN Position */
+#define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK_T::APBCLK0: I2C0CKEN Mask */
+
+#define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK_T::APBCLK0: I2C1CKEN Position */
+#define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK_T::APBCLK0: I2C1CKEN Mask */
+
+#define CLK_APBCLK0_I2C2CKEN_Pos (10) /*!< CLK_T::APBCLK0: I2C2CKEN Position */
+#define CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos) /*!< CLK_T::APBCLK0: I2C2CKEN Mask */
+
+#define CLK_APBCLK0_QSPI0CKEN_Pos (12) /*!< CLK_T::APBCLK0: QSPI0CKEN Position */
+#define CLK_APBCLK0_QSPI0CKEN_Msk (0x1ul << CLK_APBCLK0_QSPI0CKEN_Pos) /*!< CLK_T::APBCLK0: QSPI0CKEN Mask */
+
+#define CLK_APBCLK0_SPI0CKEN_Pos (13) /*!< CLK_T::APBCLK0: SPI0CKEN Position */
+#define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK_T::APBCLK0: SPI0CKEN Mask */
+
+#define CLK_APBCLK0_SPI1CKEN_Pos (14) /*!< CLK_T::APBCLK0: SPI1CKEN Position */
+#define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /*!< CLK_T::APBCLK0: SPI1CKEN Mask */
+
+#define CLK_APBCLK0_SPI2CKEN_Pos (15) /*!< CLK_T::APBCLK0: SPI2CKEN Position */
+#define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /*!< CLK_T::APBCLK0: SPI2CKEN Mask */
+
+#define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART0CKEN Position */
+#define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */
+
+#define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART1CKEN Position */
+#define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */
+
+#define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART2CKEN Position */
+#define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */
+
+#define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK_T::APBCLK0: UART3CKEN Position */
+#define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK_T::APBCLK0: UART3CKEN Mask */
+
+#define CLK_APBCLK0_UART4CKEN_Pos (20) /*!< CLK_T::APBCLK0: UART4CKEN Position */
+#define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) /*!< CLK_T::APBCLK0: UART4CKEN Mask */
+
+#define CLK_APBCLK0_UART5CKEN_Pos (21) /*!< CLK_T::APBCLK0: UART5CKEN Position */
+#define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) /*!< CLK_T::APBCLK0: UART5CKEN Mask */
+
+#define CLK_APBCLK0_CAN0CKEN_Pos (24) /*!< CLK_T::APBCLK0: CAN0CKEN Position */
+#define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) /*!< CLK_T::APBCLK0: CAN0CKEN Mask */
+
+#define CLK_APBCLK0_CAN1CKEN_Pos (25) /*!< CLK_T::APBCLK0: CAN1CKEN Position */
+#define CLK_APBCLK0_CAN1CKEN_Msk (0x1ul << CLK_APBCLK0_CAN1CKEN_Pos) /*!< CLK_T::APBCLK0: CAN1CKEN Mask */
+
+#define CLK_APBCLK0_OTGCKEN_Pos (26) /*!< CLK_T::APBCLK0: OTGCKEN Position */
+#define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /*!< CLK_T::APBCLK0: OTGCKEN Mask */
+
+#define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */
+#define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */
+
+#define CLK_APBCLK0_EADCCKEN_Pos (28) /*!< CLK_T::APBCLK0: EADCCKEN Position */
+#define CLK_APBCLK0_EADCCKEN_Msk (0x1ul << CLK_APBCLK0_EADCCKEN_Pos) /*!< CLK_T::APBCLK0: EADCCKEN Mask */
+
+#define CLK_APBCLK0_I2S0CKEN_Pos (29) /*!< CLK_T::APBCLK0: I2S0CKEN Position */
+#define CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos) /*!< CLK_T::APBCLK0: I2S0CKEN Mask */
+
+#define CLK_APBCLK0_HSOTGCKEN_Pos (30) /*!< CLK_T::APBCLK0: HSOTGCKEN Position */
+#define CLK_APBCLK0_HSOTGCKEN_Msk (0x1ul << CLK_APBCLK0_HSOTGCKEN_Pos) /*!< CLK_T::APBCLK0: HSOTGCKEN Mask */
+
+#define CLK_APBCLK1_SC0CKEN_Pos (0) /*!< CLK_T::APBCLK1: SC0CKEN Position */
+#define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK_T::APBCLK1: SC0CKEN Mask */
+
+#define CLK_APBCLK1_SC1CKEN_Pos (1) /*!< CLK_T::APBCLK1: SC1CKEN Position */
+#define CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos) /*!< CLK_T::APBCLK1: SC1CKEN Mask */
+
+#define CLK_APBCLK1_SC2CKEN_Pos (2) /*!< CLK_T::APBCLK1: SC2CKEN Position */
+#define CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos) /*!< CLK_T::APBCLK1: SC2CKEN Mask */
+
+#define CLK_APBCLK1_SPI3CKEN_Pos (6) /*!< CLK_T::APBCLK1: SPI3CKEN Position */
+#define CLK_APBCLK1_SPI3CKEN_Msk (0x1ul << CLK_APBCLK1_SPI3CKEN_Pos) /*!< CLK_T::APBCLK1: SPI3CKEN Mask */
+
+#define CLK_APBCLK1_USCI0CKEN_Pos (8) /*!< CLK_T::APBCLK1: USCI0CKEN Position */
+#define CLK_APBCLK1_USCI0CKEN_Msk (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos) /*!< CLK_T::APBCLK1: USCI0CKEN Mask */
+
+#define CLK_APBCLK1_USCI1CKEN_Pos (9) /*!< CLK_T::APBCLK1: USCI1CKEN Position */
+#define CLK_APBCLK1_USCI1CKEN_Msk (0x1ul << CLK_APBCLK1_USCI1CKEN_Pos) /*!< CLK_T::APBCLK1: USCI1CKEN Mask */
+
+#define CLK_APBCLK1_DACCKEN_Pos (12) /*!< CLK_T::APBCLK1: DACCKEN Position */
+#define CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos) /*!< CLK_T::APBCLK1: DACCKEN Mask */
+
+#define CLK_APBCLK1_EPWM0CKEN_Pos (16) /*!< CLK_T::APBCLK1: EPWM0CKEN Position */
+#define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM0CKEN Mask */
+
+#define CLK_APBCLK1_EPWM1CKEN_Pos (17) /*!< CLK_T::APBCLK1: EPWM1CKEN Position */
+#define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM1CKEN Mask */
+
+#define CLK_APBCLK1_BPWM0CKEN_Pos (18) /*!< CLK_T::APBCLK1: BPWM0CKEN Position */
+#define CLK_APBCLK1_BPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM0CKEN Mask */
+
+#define CLK_APBCLK1_BPWM1CKEN_Pos (19) /*!< CLK_T::APBCLK1: BPWM1CKEN Position */
+#define CLK_APBCLK1_BPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM1CKEN Mask */
+
+#define CLK_APBCLK1_QEI0CKEN_Pos (22) /*!< CLK_T::APBCLK1: QEI0CKEN Position */
+#define CLK_APBCLK1_QEI0CKEN_Msk (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos) /*!< CLK_T::APBCLK1: QEI0CKEN Mask */
+
+#define CLK_APBCLK1_QEI1CKEN_Pos (23) /*!< CLK_T::APBCLK1: QEI1CKEN Position */
+#define CLK_APBCLK1_QEI1CKEN_Msk (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos) /*!< CLK_T::APBCLK1: QEI1CKEN Mask */
+
+#define CLK_APBCLK1_ECAP0CKEN_Pos (26) /*!< CLK_T::APBCLK1: ECAP0CKEN Position */
+#define CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP0CKEN Mask */
+
+#define CLK_APBCLK1_ECAP1CKEN_Pos (27) /*!< CLK_T::APBCLK1: ECAP1CKEN Position */
+#define CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP1CKEN Mask */
+
+#define CLK_APBCLK1_OPACKEN_Pos (30) /*!< CLK_T::APBCLK1: OPACKEN Position */
+#define CLK_APBCLK1_OPACKEN_Msk (0x1ul << CLK_APBCLK1_OPACKEN_Pos) /*!< CLK_T::APBCLK1: OPACKEN Mask */
+
+#define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK_T::CLKSEL0: HCLKSEL Position */
+#define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK_T::CLKSEL0: HCLKSEL Mask */
+
+#define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK_T::CLKSEL0: STCLKSEL Position */
+#define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK_T::CLKSEL0: STCLKSEL Mask */
+
+#define CLK_CLKSEL0_SDH0SEL_Pos (20) /*!< CLK_T::CLKSEL0: SDH0SEL Position */
+#define CLK_CLKSEL0_SDH0SEL_Msk (0x3ul << CLK_CLKSEL0_SDH0SEL_Pos) /*!< CLK_T::CLKSEL0: SDH0SEL Mask */
+
+#define CLK_CLKSEL0_SDH1SEL_Pos (22) /*!< CLK_T::CLKSEL0: SDH1SEL Position */
+#define CLK_CLKSEL0_SDH1SEL_Msk (0x3ul << CLK_CLKSEL0_SDH1SEL_Pos) /*!< CLK_T::CLKSEL0: SDH1SEL Mask */
+
+#define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */
+#define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */
+
+#define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */
+#define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */
+
+#define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR1SEL Position */
+#define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */
+
+#define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR2SEL Position */
+#define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */
+
+#define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR3SEL Position */
+#define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */
+
+#define CLK_CLKSEL1_UART0SEL_Pos (24) /*!< CLK_T::CLKSEL1: UART0SEL Position */
+#define CLK_CLKSEL1_UART0SEL_Msk (0x3ul << CLK_CLKSEL1_UART0SEL_Pos) /*!< CLK_T::CLKSEL1: UART0SEL Mask */
+
+#define CLK_CLKSEL1_UART1SEL_Pos (26) /*!< CLK_T::CLKSEL1: UART1SEL Position */
+#define CLK_CLKSEL1_UART1SEL_Msk (0x3ul << CLK_CLKSEL1_UART1SEL_Pos) /*!< CLK_T::CLKSEL1: UART1SEL Mask */
+
+#define CLK_CLKSEL1_CLKOSEL_Pos (28) /*!< CLK_T::CLKSEL1: CLKOSEL Position */
+#define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK_T::CLKSEL1: CLKOSEL Mask */
+
+#define CLK_CLKSEL1_WWDTSEL_Pos (30) /*!< CLK_T::CLKSEL1: WWDTSEL Position */
+#define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK_T::CLKSEL1: WWDTSEL Mask */
+
+#define CLK_CLKSEL2_EPWM0SEL_Pos (0) /*!< CLK_T::CLKSEL2: EPWM0SEL Position */
+#define CLK_CLKSEL2_EPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM0SEL Mask */
+
+#define CLK_CLKSEL2_EPWM1SEL_Pos (1) /*!< CLK_T::CLKSEL2: EPWM1SEL Position */
+#define CLK_CLKSEL2_EPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM1SEL Mask */
+
+#define CLK_CLKSEL2_QSPI0SEL_Pos (2) /*!< CLK_T::CLKSEL2: QSPI0SEL Position */
+#define CLK_CLKSEL2_QSPI0SEL_Msk (0x3ul << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< CLK_T::CLKSEL2: QSPI0SEL Mask */
+
+#define CLK_CLKSEL2_SPI0SEL_Pos (4) /*!< CLK_T::CLKSEL2: SPI0SEL Position */
+#define CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos) /*!< CLK_T::CLKSEL2: SPI0SEL Mask */
+
+#define CLK_CLKSEL2_SPI1SEL_Pos (6) /*!< CLK_T::CLKSEL2: SPI1SEL Position */
+#define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos) /*!< CLK_T::CLKSEL2: SPI1SEL Mask */
+
+#define CLK_CLKSEL2_BPWM0SEL_Pos (8) /*!< CLK_T::CLKSEL2: BPWM0SEL Position */
+#define CLK_CLKSEL2_BPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM0SEL Mask */
+
+#define CLK_CLKSEL2_BPWM1SEL_Pos (9) /*!< CLK_T::CLKSEL2: BPWM1SEL Position */
+#define CLK_CLKSEL2_BPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM1SEL Mask */
+
+#define CLK_CLKSEL2_SPI2SEL_Pos (10) /*!< CLK_T::CLKSEL2: SPI2SEL Position */
+#define CLK_CLKSEL2_SPI2SEL_Msk (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos) /*!< CLK_T::CLKSEL2: SPI2SEL Mask */
+
+#define CLK_CLKSEL2_SPI3SEL_Pos (12) /*!< CLK_T::CLKSEL2: SPI3SEL Position */
+#define CLK_CLKSEL2_SPI3SEL_Msk (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos) /*!< CLK_T::CLKSEL2: SPI3SEL Mask */
+
+#define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK_T::CLKSEL3: SC0SEL Position */
+#define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK_T::CLKSEL3: SC0SEL Mask */
+
+#define CLK_CLKSEL3_SC1SEL_Pos (2) /*!< CLK_T::CLKSEL3: SC1SEL Position */
+#define CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos) /*!< CLK_T::CLKSEL3: SC1SEL Mask */
+
+#define CLK_CLKSEL3_SC2SEL_Pos (4) /*!< CLK_T::CLKSEL3: SC2SEL Position */
+#define CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos) /*!< CLK_T::CLKSEL3: SC2SEL Mask */
+
+#define CLK_CLKSEL3_RTCSEL_Pos (8) /*!< CLK_T::CLKSEL3: RTCSEL Position */
+#define CLK_CLKSEL3_RTCSEL_Msk (0x1ul << CLK_CLKSEL3_RTCSEL_Pos) /*!< CLK_T::CLKSEL3: RTCSEL Mask */
+
+#define CLK_CLKSEL3_I2S0SEL_Pos (16) /*!< CLK_T::CLKSEL3: I2S0SEL Position */
+#define CLK_CLKSEL3_I2S0SEL_Msk (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos) /*!< CLK_T::CLKSEL3: I2S0SEL Mask */
+
+#define CLK_CLKSEL3_UART2SEL_Pos (24) /*!< CLK_T::CLKSEL3: UART2SEL Position */
+#define CLK_CLKSEL3_UART2SEL_Msk (0x3ul << CLK_CLKSEL3_UART2SEL_Pos) /*!< CLK_T::CLKSEL3: UART2SEL Mask */
+
+#define CLK_CLKSEL3_UART3SEL_Pos (26) /*!< CLK_T::CLKSEL3: UART3SEL Position */
+#define CLK_CLKSEL3_UART3SEL_Msk (0x3ul << CLK_CLKSEL3_UART3SEL_Pos) /*!< CLK_T::CLKSEL3: UART3SEL Mask */
+
+#define CLK_CLKSEL3_UART4SEL_Pos (28) /*!< CLK_T::CLKSEL3: UART4SEL Position */
+#define CLK_CLKSEL3_UART4SEL_Msk (0x3ul << CLK_CLKSEL3_UART4SEL_Pos) /*!< CLK_T::CLKSEL3: UART4SEL Mask */
+
+#define CLK_CLKSEL3_UART5SEL_Pos (30) /*!< CLK_T::CLKSEL3: UART5SEL Position */
+#define CLK_CLKSEL3_UART5SEL_Msk (0x3ul << CLK_CLKSEL3_UART5SEL_Pos) /*!< CLK_T::CLKSEL3: UART5SEL Mask */
+
+#define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK_T::CLKDIV0: HCLKDIV Position */
+#define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK_T::CLKDIV0: HCLKDIV Mask */
+
+#define CLK_CLKDIV0_USBDIV_Pos (4) /*!< CLK_T::CLKDIV0: USBDIV Position */
+#define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) /*!< CLK_T::CLKDIV0: USBDIV Mask */
+
+#define CLK_CLKDIV0_UART0DIV_Pos (8) /*!< CLK_T::CLKDIV0: UART0DIV Position */
+#define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLK_T::CLKDIV0: UART0DIV Mask */
+
+#define CLK_CLKDIV0_UART1DIV_Pos (12) /*!< CLK_T::CLKDIV0: UART1DIV Position */
+#define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLK_T::CLKDIV0: UART1DIV Mask */
+
+#define CLK_CLKDIV0_EADCDIV_Pos (16) /*!< CLK_T::CLKDIV0: EADCDIV Position */
+#define CLK_CLKDIV0_EADCDIV_Msk (0xfful << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLK_T::CLKDIV0: EADCDIV Mask */
+
+#define CLK_CLKDIV0_SDH0DIV_Pos (24) /*!< CLK_T::CLKDIV0: SDH0DIV Position */
+#define CLK_CLKDIV0_SDH0DIV_Msk (0xfful << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLK_T::CLKDIV0: SDH0DIV Mask */
+
+#define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK_T::CLKDIV1: SC0DIV Position */
+#define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK_T::CLKDIV1: SC0DIV Mask */
+
+#define CLK_CLKDIV1_SC1DIV_Pos (8) /*!< CLK_T::CLKDIV1: SC1DIV Position */
+#define CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLK_T::CLKDIV1: SC1DIV Mask */
+
+#define CLK_CLKDIV1_SC2DIV_Pos (16) /*!< CLK_T::CLKDIV1: SC2DIV Position */
+#define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLK_T::CLKDIV1: SC2DIV Mask */
+
+#define CLK_CLKDIV3_EMACDIV_Pos (16) /*!< CLK_T::CLKDIV3: EMACDIV Position */
+#define CLK_CLKDIV3_EMACDIV_Msk (0xfful << CLK_CLKDIV3_EMACDIV_Pos) /*!< CLK_T::CLKDIV3: EMACDIV Mask */
+
+#define CLK_CLKDIV3_SDH1DIV_Pos (24) /*!< CLK_T::CLKDIV3: SDH1DIV Position */
+#define CLK_CLKDIV3_SDH1DIV_Msk (0xfful << CLK_CLKDIV3_SDH1DIV_Pos) /*!< CLK_T::CLKDIV3: SDH1DIV Mask */
+
+#define CLK_CLKDIV4_UART2DIV_Pos (0) /*!< CLK_T::CLKDIV4: UART2DIV Position */
+#define CLK_CLKDIV4_UART2DIV_Msk (0xful << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLK_T::CLKDIV4: UART2DIV Mask */
+
+#define CLK_CLKDIV4_UART3DIV_Pos (4) /*!< CLK_T::CLKDIV4: UART3DIV Position */
+#define CLK_CLKDIV4_UART3DIV_Msk (0xful << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLK_T::CLKDIV4: UART3DIV Mask */
+
+#define CLK_CLKDIV4_UART4DIV_Pos (8) /*!< CLK_T::CLKDIV4: UART4DIV Position */
+#define CLK_CLKDIV4_UART4DIV_Msk (0xful << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLK_T::CLKDIV4: UART4DIV Mask */
+
+#define CLK_CLKDIV4_UART5DIV_Pos (12) /*!< CLK_T::CLKDIV4: UART5DIV Position */
+#define CLK_CLKDIV4_UART5DIV_Msk (0xful << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLK_T::CLKDIV4: UART5DIV Mask */
+
+#define CLK_PCLKDIV_APB0DIV_Pos (0) /*!< CLK_T::PCLKDIV: APB0DIV Position */
+#define CLK_PCLKDIV_APB0DIV_Msk (0x7ul << CLK_PCLKDIV_APB0DIV_Pos) /*!< CLK_T::PCLKDIV: APB0DIV Mask */
+
+#define CLK_PCLKDIV_APB1DIV_Pos (4) /*!< CLK_T::PCLKDIV: APB1DIV Position */
+#define CLK_PCLKDIV_APB1DIV_Msk (0x7ul << CLK_PCLKDIV_APB1DIV_Pos) /*!< CLK_T::PCLKDIV: APB1DIV Mask */
+
+#define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK_T::PLLCTL: FBDIV Position */
+#define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK_T::PLLCTL: FBDIV Mask */
+
+#define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK_T::PLLCTL: INDIV Position */
+#define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /*!< CLK_T::PLLCTL: INDIV Mask */
+
+#define CLK_PLLCTL_OUTDIV_Pos (14) /*!< CLK_T::PLLCTL: OUTDIV Position */
+#define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) /*!< CLK_T::PLLCTL: OUTDIV Mask */
+
+#define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */
+#define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */
+
+#define CLK_PLLCTL_BP_Pos (17) /*!< CLK_T::PLLCTL: BP Position */
+#define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK_T::PLLCTL: BP Mask */
+
+#define CLK_PLLCTL_OE_Pos (18) /*!< CLK_T::PLLCTL: OE Position */
+#define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) /*!< CLK_T::PLLCTL: OE Mask */
+
+#define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK_T::PLLCTL: PLLSRC Position */
+#define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK_T::PLLCTL: PLLSRC Mask */
+
+#define CLK_PLLCTL_STBSEL_Pos (23) /*!< CLK_T::PLLCTL: STBSEL Position */
+#define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) /*!< CLK_T::PLLCTL: STBSEL Mask */
+
+#define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */
+#define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */
+
+#define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */
+#define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */
+
+#define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK_T::STATUS: PLLSTB Position */
+#define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK_T::STATUS: PLLSTB Mask */
+
+#define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */
+#define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */
+
+#define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */
+#define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */
+
+#define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK_T::STATUS: CLKSFAIL Position */
+#define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK_T::STATUS: CLKSFAIL Mask */
+
+#define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */
+#define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */
+
+#define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */
+#define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */
+
+#define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */
+#define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */
+
+#define CLK_CLKOCTL_CLK1HZEN_Pos (6) /*!< CLK_T::CLKOCTL: CLK1HZEN Position */
+#define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) /*!< CLK_T::CLKOCTL: CLK1HZEN Mask */
+
+#define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */
+#define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */
+
+#define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */
+#define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */
+
+#define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */
+#define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */
+
+#define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */
+#define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */
+
+#define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */
+#define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */
+
+#define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */
+#define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */
+
+#define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */
+#define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */
+
+#define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */
+#define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */
+
+#define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */
+#define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */
+
+#define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */
+#define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */
+
+#define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */
+#define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */
+
+#define CLK_PMUCTL_PDMSEL_Pos (0) /*!< CLK_T::PMUCTL: PDMSEL Position */
+#define CLK_PMUCTL_PDMSEL_Msk (0x7ul << CLK_PMUCTL_PDMSEL_Pos) /*!< CLK_T::PMUCTL: PDMSEL Mask */
+
+#define CLK_PMUCTL_WKTMREN_Pos (8) /*!< CLK_T::PMUCTL: WKTMREN Position */
+#define CLK_PMUCTL_WKTMREN_Msk (0x1ul << CLK_PMUCTL_WKTMREN_Pos) /*!< CLK_T::PMUCTL: WKTMREN Mask */
+
+#define CLK_PMUCTL_WKTMRIS_Pos (9) /*!< CLK_T::PMUCTL: WKTMRIS Position */
+#define CLK_PMUCTL_WKTMRIS_Msk (0x7ul << CLK_PMUCTL_WKTMRIS_Pos) /*!< CLK_T::PMUCTL: WKTMRIS Mask */
+
+#define CLK_PMUCTL_WKPINEN_Pos (16) /*!< CLK_T::PMUCTL: WKPINEN Position */
+#define CLK_PMUCTL_WKPINEN_Msk (0x3ul << CLK_PMUCTL_WKPINEN_Pos) /*!< CLK_T::PMUCTL: WKPINEN Mask */
+
+#define CLK_PMUCTL_ACMPSPWK_Pos (18) /*!< CLK_T::PMUCTL: ACMPSPWK Position */
+#define CLK_PMUCTL_ACMPSPWK_Msk (0x1ul << CLK_PMUCTL_ACMPSPWK_Pos) /*!< CLK_T::PMUCTL: ACMPSPWK Mask */
+
+#define CLK_PMUCTL_RTCWKEN_Pos (23) /*!< CLK_T::PMUCTL: RTCWKEN Position */
+#define CLK_PMUCTL_RTCWKEN_Msk (0x1ul << CLK_PMUCTL_RTCWKEN_Pos) /*!< CLK_T::PMUCTL: RTCWKEN Mask */
+
+#define CLK_PMUSTS_PINWK_Pos (0) /*!< CLK_T::PMUSTS: PINWK Position */
+#define CLK_PMUSTS_PINWK_Msk (0x1ul << CLK_PMUSTS_PINWK_Pos) /*!< CLK_T::PMUSTS: PINWK Mask */
+
+#define CLK_PMUSTS_TMRWK_Pos (1) /*!< CLK_T::PMUSTS: TMRWK Position */
+#define CLK_PMUSTS_TMRWK_Msk (0x1ul << CLK_PMUSTS_TMRWK_Pos) /*!< CLK_T::PMUSTS: TMRWK Mask */
+
+#define CLK_PMUSTS_RTCWK_Pos (2) /*!< CLK_T::PMUSTS: RTCWK Position */
+#define CLK_PMUSTS_RTCWK_Msk (0x1ul << CLK_PMUSTS_RTCWK_Pos) /*!< CLK_T::PMUSTS: RTCWK Mask */
+
+#define CLK_PMUSTS_GPAWK_Pos (8) /*!< CLK_T::PMUSTS: GPAWK Position */
+#define CLK_PMUSTS_GPAWK_Msk (0x1ul << CLK_PMUSTS_GPAWK_Pos) /*!< CLK_T::PMUSTS: GPAWK Mask */
+
+#define CLK_PMUSTS_GPBWK_Pos (9) /*!< CLK_T::PMUSTS: GPBWK Position */
+#define CLK_PMUSTS_GPBWK_Msk (0x1ul << CLK_PMUSTS_GPBWK_Pos) /*!< CLK_T::PMUSTS: GPBWK Mask */
+
+#define CLK_PMUSTS_GPCWK_Pos (10) /*!< CLK_T::PMUSTS: GPCWK Position */
+#define CLK_PMUSTS_GPCWK_Msk (0x1ul << CLK_PMUSTS_GPCWK_Pos) /*!< CLK_T::PMUSTS: GPCWK Mask */
+
+#define CLK_PMUSTS_GPDWK_Pos (11) /*!< CLK_T::PMUSTS: GPDWK Position */
+#define CLK_PMUSTS_GPDWK_Msk (0x1ul << CLK_PMUSTS_GPDWK_Pos) /*!< CLK_T::PMUSTS: GPDWK Mask */
+
+#define CLK_PMUSTS_LVRWK_Pos (12) /*!< CLK_T::PMUSTS: LVRWK Position */
+#define CLK_PMUSTS_LVRWK_Msk (0x1ul << CLK_PMUSTS_LVRWK_Pos) /*!< CLK_T::PMUSTS: LVRWK Mask */
+
+#define CLK_PMUSTS_BODWK_Pos (13) /*!< CLK_T::PMUSTS: BODWK Position */
+#define CLK_PMUSTS_BODWK_Msk (0x1ul << CLK_PMUSTS_BODWK_Pos) /*!< CLK_T::PMUSTS: BODWK Mask */
+
+#define CLK_PMUSTS_ACMPWK_Pos (14) /*!< CLK_T::PMUSTS: ACMPWK Position */
+#define CLK_PMUSTS_ACMPWK_Msk (0x1ul << CLK_PMUSTS_ACMPWK_Pos) /*!< CLK_T::PMUSTS: ACMPWK Mask */
+
+#define CLK_PMUSTS_CLRWK_Pos (31) /*!< CLK_T::PMUSTS: CLRWK Position */
+#define CLK_PMUSTS_CLRWK_Msk (0x1ul << CLK_PMUSTS_CLRWK_Pos) /*!< CLK_T::PMUSTS: CLRWK Mask */
+
+#define CLK_LDOCTL_PDBIASEN_Pos (18) /*!< CLK_T::LDOCTL: PDBIASEN Position */
+#define CLK_LDOCTL_PDBIASEN_Msk (0x1ul << CLK_LDOCTL_PDBIASEN_Pos) /*!< CLK_T::LDOCTL: PDBIASEN Mask */
+
+#define CLK_SWKDBCTL_SWKDBCLKSEL_Pos (0) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Position */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_Msk (0xful << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Mask */
+
+#define CLK_PASWKCTL_WKEN_Pos (0) /*!< CLK_T::PASWKCTL: WKEN Position */
+#define CLK_PASWKCTL_WKEN_Msk (0x1ul << CLK_PASWKCTL_WKEN_Pos) /*!< CLK_T::PASWKCTL: WKEN Mask */
+
+#define CLK_PASWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PASWKCTL: PRWKEN Position */
+#define CLK_PASWKCTL_PRWKEN_Msk (0x1ul << CLK_PASWKCTL_PRWKEN_Pos) /*!< CLK_T::PASWKCTL: PRWKEN Mask */
+
+#define CLK_PASWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PASWKCTL: PFWKEN Position */
+#define CLK_PASWKCTL_PFWKEN_Msk (0x1ul << CLK_PASWKCTL_PFWKEN_Pos) /*!< CLK_T::PASWKCTL: PFWKEN Mask */
+
+#define CLK_PASWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PASWKCTL: WKPSEL Position */
+#define CLK_PASWKCTL_WKPSEL_Msk (0xful << CLK_PASWKCTL_WKPSEL_Pos) /*!< CLK_T::PASWKCTL: WKPSEL Mask */
+
+#define CLK_PASWKCTL_DBEN_Pos (8) /*!< CLK_T::PASWKCTL: DBEN Position */
+#define CLK_PASWKCTL_DBEN_Msk (0x1ul << CLK_PASWKCTL_DBEN_Pos) /*!< CLK_T::PASWKCTL: DBEN Mask */
+
+#define CLK_PBSWKCTL_WKEN_Pos (0) /*!< CLK_T::PBSWKCTL: WKEN Position */
+#define CLK_PBSWKCTL_WKEN_Msk (0x1ul << CLK_PBSWKCTL_WKEN_Pos) /*!< CLK_T::PBSWKCTL: WKEN Mask */
+
+#define CLK_PBSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PBSWKCTL: PRWKEN Position */
+#define CLK_PBSWKCTL_PRWKEN_Msk (0x1ul << CLK_PBSWKCTL_PRWKEN_Pos) /*!< CLK_T::PBSWKCTL: PRWKEN Mask */
+
+#define CLK_PBSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PBSWKCTL: PFWKEN Position */
+#define CLK_PBSWKCTL_PFWKEN_Msk (0x1ul << CLK_PBSWKCTL_PFWKEN_Pos) /*!< CLK_T::PBSWKCTL: PFWKEN Mask */
+
+#define CLK_PBSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PBSWKCTL: WKPSEL Position */
+#define CLK_PBSWKCTL_WKPSEL_Msk (0xful << CLK_PBSWKCTL_WKPSEL_Pos) /*!< CLK_T::PBSWKCTL: WKPSEL Mask */
+
+#define CLK_PBSWKCTL_DBEN_Pos (8) /*!< CLK_T::PBSWKCTL: DBEN Position */
+#define CLK_PBSWKCTL_DBEN_Msk (0x1ul << CLK_PBSWKCTL_DBEN_Pos) /*!< CLK_T::PBSWKCTL: DBEN Mask */
+
+#define CLK_PCSWKCTL_WKEN_Pos (0) /*!< CLK_T::PCSWKCTL: WKEN Position */
+#define CLK_PCSWKCTL_WKEN_Msk (0x1ul << CLK_PCSWKCTL_WKEN_Pos) /*!< CLK_T::PCSWKCTL: WKEN Mask */
+
+#define CLK_PCSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PCSWKCTL: PRWKEN Position */
+#define CLK_PCSWKCTL_PRWKEN_Msk (0x1ul << CLK_PCSWKCTL_PRWKEN_Pos) /*!< CLK_T::PCSWKCTL: PRWKEN Mask */
+
+#define CLK_PCSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PCSWKCTL: PFWKEN Position */
+#define CLK_PCSWKCTL_PFWKEN_Msk (0x1ul << CLK_PCSWKCTL_PFWKEN_Pos) /*!< CLK_T::PCSWKCTL: PFWKEN Mask */
+
+#define CLK_PCSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PCSWKCTL: WKPSEL Position */
+#define CLK_PCSWKCTL_WKPSEL_Msk (0xful << CLK_PCSWKCTL_WKPSEL_Pos) /*!< CLK_T::PCSWKCTL: WKPSEL Mask */
+
+#define CLK_PCSWKCTL_DBEN_Pos (8) /*!< CLK_T::PCSWKCTL: DBEN Position */
+#define CLK_PCSWKCTL_DBEN_Msk (0x1ul << CLK_PCSWKCTL_DBEN_Pos) /*!< CLK_T::PCSWKCTL: DBEN Mask */
+
+#define CLK_PDSWKCTL_WKEN_Pos (0) /*!< CLK_T::PDSWKCTL: WKEN Position */
+#define CLK_PDSWKCTL_WKEN_Msk (0x1ul << CLK_PDSWKCTL_WKEN_Pos) /*!< CLK_T::PDSWKCTL: WKEN Mask */
+
+#define CLK_PDSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PDSWKCTL: PRWKEN Position */
+#define CLK_PDSWKCTL_PRWKEN_Msk (0x1ul << CLK_PDSWKCTL_PRWKEN_Pos) /*!< CLK_T::PDSWKCTL: PRWKEN Mask */
+
+#define CLK_PDSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PDSWKCTL: PFWKEN Position */
+#define CLK_PDSWKCTL_PFWKEN_Msk (0x1ul << CLK_PDSWKCTL_PFWKEN_Pos) /*!< CLK_T::PDSWKCTL: PFWKEN Mask */
+
+#define CLK_PDSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PDSWKCTL: WKPSEL Position */
+#define CLK_PDSWKCTL_WKPSEL_Msk (0xful << CLK_PDSWKCTL_WKPSEL_Pos) /*!< CLK_T::PDSWKCTL: WKPSEL Mask */
+
+#define CLK_PDSWKCTL_DBEN_Pos (8) /*!< CLK_T::PDSWKCTL: DBEN Position */
+#define CLK_PDSWKCTL_DBEN_Msk (0x1ul << CLK_PDSWKCTL_DBEN_Pos) /*!< CLK_T::PDSWKCTL: DBEN Mask */
+
+#define CLK_IOPDCTL_IOHR_Pos (0) /*!< CLK_T::IOPDCTL: IOHR Position */
+#define CLK_IOPDCTL_IOHR_Msk (0x1ul << CLK_IOPDCTL_IOHR_Pos) /*!< CLK_T::IOPDCTL: IOHR Mask */
+
+/**@}*/ /* CLK_CONST */
+/**@}*/ /* end of CLK register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __CLK_REG_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Include/m480_fmc_reg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Include/m480_fmc_reg.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,661 @@
+/**************************************************************************//**
+ * @file fmc_reg.h
+ * @version V1.00
+ * @brief FMC register definition header file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/
+#ifndef __FMC_REG_H__
+#define __FMC_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup FMC Flash Memory Controller(FMC)
+ Memory Mapped Structure for FMC Controller
+@{ */
+
+typedef struct {
+ /**
+ * @var FMC_T::ISPCTL
+ * Offset: 0x00 ISP Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ISPEN |ISP Enable Bit (Write Protect)
+ * | | |ISP function enable bit. Set this bit to enable ISP function.
+ * | | |0 = ISP function Disabled.
+ * | | |1 = ISP function Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[1] |BS |Boot Select (Write Protect)
+ * | | |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively
+ * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from
+ * | | |This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
+ * | | |0 = Booting from APROM when MBS (CONFIG0[5]) is 1.
+ * | | |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[2] |SPUEN |SPROM Update Enable Bit (Write Protect)
+ * | | |0 = SPROM cannot be updated.
+ * | | |1 = SPROM can be updated.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[3] |APUEN |APROM Update Enable Bit (Write Protect)
+ * | | |0 = APROM cannot be updated when the chip runs in APROM.
+ * | | |1 = APROM can be updated when the chip runs in APROM.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect)
+ * | | |0 = CONFIG cannot be updated.
+ * | | |1 = CONFIG can be updated.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[5] |LDUEN |LDROM Update Enable Bit (Write Protect)
+ * | | |LDROM update enable bit.
+ * | | |0 = LDROM cannot be updated.
+ * | | |1 = LDROM can be updated.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[6] |ISPFF |ISP Fail Flag (Write Protect)
+ * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
+ * | | |This bit needs to be cleared by writing 1 to it.
+ * | | |(1) APROM writes to itself if APUEN is set to 0.
+ * | | |(2) LDROM writes to itself if LDUEN is set to 0.
+ * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
+ * | | |(4) SPROM is erased/programmed if SPUEN is set to 0
+ * | | |(5) SPROM is programmed at SPROM secured mode.
+ * | | |(6) Page Erase command at LOCK mode with ICE connection
+ * | | |(7) Erase or Program command at brown-out detected
+ * | | |(8) Destination address is illegal, such as over an available range.
+ * | | |(9) Invalid ISP commands
+ * | | |(10) Vector address is mapping to SPROM region
+ * | | |(11) KPROM is erased/programmed if KEYLOCK is set to 1
+ * | | |(12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1
+ * | | |(13) LDROM is erased/programmed if KEYLOCK is set to 1
+ * | | |(14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1.
+ * | | |(15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1
+ * | | |(16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A
+ * | | |(17) Read any content of boot loader with ICE connection
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[16] |BL |Boot Loader Booting (Write Protect)
+ * | | |This bit is initiated with the inversed value of MBS (CONFIG0[5])
+ * | | |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded
+ * | | |This bit is used to check chip boot from Boot Loader or not
+ * | | |User should keep original value of this bit when updating FMC_ISPCTL register.
+ * | | |0 = Booting from APROM or LDROM.
+ * | | |1 = Booting from Boot Loader.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var FMC_T::ISPADDR
+ * Offset: 0x04 ISP Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ISPADDR |ISP Address
+ * | | |The NuMicro M480 series is equipped with embedded flash
+ * | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation
+ * | | |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.
+ * | | |For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 4 Kbytes alignment is necessary for CRC32 checksum calculation.
+ * | | |For FLASH 32-bit Program, ISP address needs word alignment (4-byte)
+ * | | |For FLASH 64-bit Program, ISP address needs double word alignment (8-byte).
+ * @var FMC_T::ISPDAT
+ * Offset: 0x08 ISP Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ISPDAT |ISP Data
+ * | | |Write data to this register before ISP program operation.
+ * | | |Read data from this register after ISP read operation.
+ * | | |When ISPFF (FMC_ISPCTL[6]) is 1, ISPDAT = 0xffff_ffff
+ * | | |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 4 Kbytes alignment
+ * | | |For ISP Read CRC32 Checksum command, ISPDAT is the checksum result
+ * | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect
+ * @var FMC_T::ISPCMD
+ * Offset: 0x0C ISP Command Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[6:0] |CMD |ISP Command
+ * | | |ISP command table is shown below:
+ * | | |0x00= FLASH Read.
+ * | | |0x04= Read Unique ID.
+ * | | |0x08= Read Flash All-One Result.
+ * | | |0x0B= Read Company ID.
+ * | | |0x0C= Read Device ID.
+ * | | |0x0D= Read Checksum.
+ * | | |0x21= FLASH 32-bit Program.
+ * | | |0x22= FLASH Page Erase. Erase any page in two banks, except for OTP.
+ * | | |0x23= FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1.
+ * | | |0x25= FLASH Block Erase. Erase four pages alignment of APROM in BANK0 or BANK1..
+ * | | |0x27= FLASH Multi-Word Program.
+ * | | |0x28= Run Flash All-One Verification.
+ * | | |0x2D= Run Checksum Calculation.
+ * | | |0x2E= Vector Remap.
+ * | | |0x40= FLASH 64-bit Read.
+ * | | |0x61= FLASH 64-bit Program.
+ * | | |The other commands are invalid.
+ * @var FMC_T::ISPTRG
+ * Offset: 0x10 ISP Trigger Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ISPGO |ISP Start Trigger (Write Protect)
+ * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
+ * | | |0 = ISP operation is finished.
+ * | | |1 = ISP is progressed.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var FMC_T::DFBA
+ * Offset: 0x14 Data Flash Base Address
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DFBA |Data Flash Base Address
+ * | | |This register indicates Data Flash start address. It is a read only register.
+ * | | |The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1
+ * | | |This register is valid when DFEN (CONFIG0[0]) =0 .
+ * @var FMC_T::ISPSTS
+ * Offset: 0x40 ISP Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ISPBUSY |ISP Busy Flag (Read Only)
+ * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
+ * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
+ * | | |0 = ISP operation is finished.
+ * | | |1 = ISP is progressed.
+ * |[2:1] |CBS |Boot Selection of CONFIG (Read Only)
+ * | | |This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
+ * | | |The following function is valid when MBS (FMC_ISPSTS[3])= 1.
+ * | | |00 = LDROM with IAP mode.
+ * | | |01 = LDROM without IAP mode.
+ * | | |10 = APROM with IAP mode.
+ * | | |11 = APROM without IAP mode.
+ * |[3] |MBS |Boot From Boot Loader Selection Flag (Read Only)
+ * | | |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
+ * | | |0 = Booting from Boot Loader.
+ * | | |1 = Booting from LDROM/APROM.(.see CBS bit setting)
+ * |[4] |FCYCDIS |Flash Access Cycle Auto-tuning Disabled Flag (Read Only)
+ * | | |This bit is set if flash access cycle auto-tuning function is disabled
+ * | | |The auto-tunning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready.
+ * | | |0 = Flash access cycle auto-tuning is enabled.
+ * | | |1 = Flash access cycle auto-tuning is disabled.
+ * |[5] |PGFF |Flash Program with Fast Verification Flag (Read Only)
+ * | | |This bit is set if data is mismatched at ISP programming verification
+ * | | |This bit is clear by performing ISP flash erase or ISP read CID operation
+ * | | |0 = Flash Program is success.
+ * | | |1 = Flash Program is fail. Program data is different with data in the flash memory
+ * |[6] |ISPFF |ISP Fail Flag (Write Protect)
+ * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]
+ * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
+ * | | |(1) APROM writes to itself if APUEN is set to 0.
+ * | | |(2) LDROM writes to itself if LDUEN is set to 0.
+ * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
+ * | | |(4) SPROM is erased/programmed if SPUEN is set to 0
+ * | | |(5) SPROM is programmed at SPROM secured mode.
+ * | | |(6) Page Erase command at LOCK mode with ICE connection
+ * | | |(7) Erase or Program command at brown-out detected
+ * | | |(8) Destination address is illegal, such as over an available range.
+ * | | |(9) Invalid ISP commands
+ * | | |(10) Vector address is mapping to SPROM region.
+ * | | |(11) KPROM is erased/programmed if KEYLOCK is set to 1
+ * | | |(12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1
+ * | | |(13) LDROM is erased/programmed if KEYLOCK is set to 1
+ * | | |(14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1.
+ * | | |(15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1.
+ * | | |(16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A
+ * | | |(17) Read any content of boot loader with ICE connection
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[7] |ALLONE |Flash All-one Verification Flag
+ * | | |This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after "Run Flash All-One Verification" complete; this bit also can be clear by writing 1
+ * | | |0 = All of flash bits are 1 after "Run Flash All-One Verification" complete.
+ * | | |1 = Flash bits are not all 1 after "Run Flash All-One Verification" complete.
+ * |[23:9] |VECMAP |Vector Page Mapping Address (Read Only)
+ * | | |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9u2019h000} ~ {VECMAP[14:0], 9u2019h1FF}
+ * |[31] |SCODE |Security Code Active Flag
+ * | | |This bit is set by hardware when detecting SPROM secured code is active at flash initiation, or software writes 1 to this bit to make secured code active; this bit is clear by SPROM page erase operation.
+ * | | |0 = Secured code is inactive.
+ * | | |1 = Secured code is active.
+ * @var FMC_T::CYCCTL
+ * Offset: 0x4C Flash Access Cycle Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |CYCLE |Flash Access Cycle Control (Write Protect)
+ * | | |0001 = CPU access with one wait cycle if cache miss; flash access cycle is 1;.
+ * | | |The HCLK working frequency range range is<27MHz
+ * | | |0010 = CPU access with two wait cycles if cache miss; flash access cycle is 2;.
+ * | | | The optimized HCLK working frequency range is 27~54 MHz
+ * | | |0011 = CPU access with three wait cycles if cache miss; flash access cycle is 3;.
+ * | | |The optimized HCLK working frequency range is 54~81MHz
+ * | | |0100 = CPU access with four wait cycles if cache miss; flash access cycle is 4;.
+ * | | | The optimized HCLK working frequency range is81~108MHz
+ * | | |0101 = CPU access with five wait cycles if cache miss; flash access cycle is 5;.
+ * | | |The optimized HCLK working frequency range is 108~135MHz
+ * | | |0110 = CPU access with six wait cycles if cache miss; flash access cycle is 6;.
+ * | | | The optimized HCLK working frequency range is 135~162MHz
+ * | | |0111 = CPU access with seven wait cycles if cache miss; flash access cycle is 7;.
+ * | | | The optimized HCLK working frequency range is 162~192MHz
+ * | | |1000 = CPU access with eight wait cycles if cache miss; flash access cycle is 8;.
+ * | | |The optimized HCLK working frequency range is >192MHz
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var FMC_T::KPKEY0
+ * Offset: 0x50 KPROM KEY0 Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KPKEY0 |KPROM KEY0 Data (Write Only)
+ * | | |Write KPKEY0 data to this register before KEY Comparison operation.
+ * @var FMC_T::KPKEY1
+ * Offset: 0x54 KPROM KEY1 Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KPKEY1 |KPROM KEY1 Data (Write Only)
+ * | | |Write KPKEY1 data to this register before KEY Comparison operation.
+ * @var FMC_T::KPKEY2
+ * Offset: 0x58 KPROM KEY2 Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |KPKEY2 |KPROM KEY2 Data (Write Only)
+ * | | |Write KPKEY2 data to this register before KEY Comparison operation.
+ * @var FMC_T::KPKEYTRG
+ * Offset: 0x5C KPROM KEY Comparison Trigger Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |KPKEYGO |KPROM KEY Comparison Start Trigger (Write Protection)
+ * | | |Write 1 to start KEY comparison operation and this bit will be cleared to 0 by hardware automatically when KEY comparison operation is finished
+ * | | |This trigger operation is valid while FORBID (FMC_KPKEYSTS [3]) is 0.
+ * | | |0 = KEY comparison operation is finished.
+ * | | |1 = KEY comparison is progressed.
+ * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
+ * |[1] |TCEN |Timeout Counting Enable (Write Protection)
+ * | | |0 = Timeout counting is disabled.
+ * | | |1 = Timeout counting is enabled if input key is matched after key comparison finish.
+ * | | |10 minutes is at least for timeout, and average is about 20 minutes.
+ * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
+ * @var FMC_T::KPKEYSTS
+ * Offset: 0x60 KPROM KEY Comparison Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |KEYBUSY |KEY Comparison Busy (Read Only)
+ * | | |0 = KEY comparison is finished.
+ * | | |1 = KEY comparison is busy.
+ * |[1] |KEYLOCK |KEY LOCK Flag
+ * | | |This bit is set to 1 if KEYMATCH (FMC_KPKEYSTS [2]) is 0 and cleared to 0 if KEYMATCH is 1 in Security Key protection
+ * | | |After Mass Erase operation, users must reset or power on /off to clear this bit to 0
+ * | | |This bit also can be set to 1 while
+ * | | | - CPU write 1 to KEYLOCK(FMC_KPKEYSTS[1]) or
+ * | | | - KEYFLAG(FMC_KPKEYSTS[4]) is 1 at power-on or reset or
+ * | | | - KEYENROM is programmed a non-0xFF value or
+ * | | | - Timeout event or
+ * | | | - FORBID(FMC_KPKEYSTS[3]) is 1
+ * | | |0 = KPROM, LDROM and APROM (not include Data Flash) is not in write protection.
+ * | | |1 = KPROM, LDROM and APROM (not include Data Flash) is in write protection.
+ * | | |SPROM write protect is depended on SPFLAG.
+ * | | |CONFIG write protect is depended on CFGFLAG
+ * |[2] |KEYMATCH |KEY Match Flag (Read Only)
+ * | | |This bit is set to 1 after KEY comparison complete if the KEY0, KEY1 and KEY2 are matched with the 96-bit security keys in KPROM; and cleared to 0 if KEYs are unmatched
+ * | | |This bit is also cleared to 0 while
+ * | | | - CPU writing 1 to KEYLOCK(FMC_KPKEYSTS[1]) or
+ * | | | - Timeout event or
+ * | | | - KPROM is erased or
+ * | | | - KEYENROM is programmed to a non-0xFF value.
+ * | | | - Chip is in power down mode.
+ * | | |0 = KEY0, KEY1, and KEY2 are unmatched with the KPROM setting.
+ * | | |1 = KEY0, KEY1, and KEY2 are matched with the KPROM setting.
+ * |[3] |FORBID |KEY Comparison Forbidden Flag (Read Only)
+ * | | |This bit is set to 1 when KPKECNT(FMC_KPKEY0[4:0]) is more than KPKEMAX (FMC_KPKEY0[12:8]) or KPCNT (FMC_KPCNT [2:0]) is more than KPMAX (FMC_KPCNT [10:8]).
+ * | | |0 = KEY comparison is not forbidden.
+ * | | |1 = KEY comparison is forbidden, KEYGO (FMC_KEYTRG [0]) cannot trigger.
+ * |[4] |KEYFLAG |KEY Protection Enabled Flag (Read Only)
+ * | | |This bit is set while the KEYENROM [7:0] is not 0xFF at power-on or reset
+ * | | |This bit is cleared to 0 by hardware while KPROM is erased
+ * | | |This bit is set to 1 by hardware while KEYENROM is programmed to a non-0xFF value.
+ * | | |0 = Security Key protection is disabled.
+ * | | |1 = Security Key protection is enabled.
+ * |[5] |CFGFLAG |CONFIG Write-protection Enabled Flag (Read Only)
+ * | | |This bit is set while the KEYENROM [0] is 0 at power-on or reset
+ * | | |This bit is cleared to 0 by hardware while KPROM is erased
+ * | | |This bit is set to 1 by hardware while KEYENROM[0] is programmed to 0.
+ * | | |0 = CONFIG write-protection is disabled.
+ * | | |1 = CONFIG write-protection is enabled.
+ * |[6] |SPFLAG |SPROM Write-protection Enabled Flag (Read Only)
+ * | | |This bit is set while the KEYENROM [1] is 0 at power-on or reset
+ * | | |This bit is cleared to 0 by hardware while KPROM is erased
+ * | | |This bit is set to 1 by hardware while KEYENROM[1] is programmed to 0.
+ * | | |0 = SPROM write-protection is disabled.
+ * | | |1 = SPROM write-protection is enabled.
+ * @var FMC_T::KPKEYCNT
+ * Offset: 0x64 KPROM KEY-Unmatched Counting Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |KPKECNT |Error Key Entry Counter at Each Power-on (Read Only)
+ * | | |KPKECNT is increased when entry keys is wrong in Security Key protection
+ * | | |KPKECNT is cleared to 0 if key comparison is matched or system power-on.
+ * |[13:8] |KPKEMAX |Maximum Number for Error Key Entry at Each Power-on (Read Only)
+ * | | |KPKEMAX is the maximum error key entry number at each power-on
+ * | | |When KPKEMAXROM of KPROM is erased or programmed, KPKEMAX will also be updated
+ * | | |KPKEMAX is used to limit KPKECNT(FMC_KPKEY0[5:0]) maximum counting
+ * | | |The FORBID (FMC_KPKEYSTS [3]) will be set to 1 when KPKECNT is more than KPKEMAX.
+ * @var FMC_T::KPCNT
+ * Offset: 0x68 KPROM KEY-Unmatched Power-On Counting Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |KPCNT |Power-on Counter for Error Key Entry(Read Only)
+ * | | |KPCNT is the power-on counting for error key entry in Security Key protection
+ * | | |KPCNT is cleared to 0 if key comparison is matched.
+ * |[11:8] |KPMAX |Power-on Maximum Number for Error Key Entry (Read Only)
+ * | | |KPMAX is the power-on maximum number for error key entry
+ * | | |When KPMAXROM of KPROM is erased or programmed, KPMAX will also be updated
+ * | | |KPMAX is used to limit KPCNT (FMC_KPCNT [3:0]) maximum counting
+ * | | |The FORBID(FMC_KPKEYSTS[3]) will be set to 1 when KPCNT is more than KPMAX
+ * @var FMC_T::MPDAT0
+ * Offset: 0x80 ISP Data0 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ISPDAT0 |ISP Data 0
+ * | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data
+ * @var FMC_T::MPDAT1
+ * Offset: 0x84 ISP Data1 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ISPDAT1 |ISP Data 1
+ * | | |This register is the second 32-bit data for 64-bit/multi-word programming.
+ * @var FMC_T::MPDAT2
+ * Offset: 0x88 ISP Data2 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ISPDAT2 |ISP Data 2
+ * | | |This register is the third 32-bit data for multi-word programming.
+ * @var FMC_T::MPDAT3
+ * Offset: 0x8C ISP Data3 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ISPDAT3 |ISP Data 3
+ * | | |This register is the fourth 32-bit data for multi-word programming.
+ * @var FMC_T::MPSTS
+ * Offset: 0xC0 ISP Multi-Program Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MPBUSY |ISP Multi-word Program Busy Flag (Read Only)
+ * | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.
+ * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
+ * | | |0 = ISP Multi-Word program operation is finished.
+ * | | |1 = ISP Multi-Word program operation is progressed.
+ * |[1] |PPGO |ISP Multi-program Status (Read Only)
+ * | | |0 = ISP multi-word program operation is not active.
+ * | | |1 = ISP multi-word program operation is in progress.
+ * |[2] |ISPFF |ISP Fail Flag (Read Only)
+ * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]
+ * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
+ * | | |(1) APROM writes to itself if APUEN is set to 0.
+ * | | |(2) LDROM writes to itself if LDUEN is set to 0.
+ * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
+ * | | |(4) SPROM is erased/programmed if SPUEN is set to 0
+ * | | |(5) SPROM is programmed at SPROM secured mode.
+ * | | |(6) Page Erase command at LOCK mode with ICE connection
+ * | | |(7) Erase or Program command at brown-out detected
+ * | | |(8) Destination address is illegal, such as over an available range.
+ * | | |(9) Invalid ISP commands
+ * | | |(10) Vector address is mapping to SPROM region.
+ * |[4] |D0 |ISP DATA 0 Flag (Read Only)
+ * | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete.
+ * | | |0 = FMC_MPDAT0 register is empty, or program to flash complete.
+ * | | |1 = FMC_MPDAT0 register has been written, and not program to flash complete.
+ * |[5] |D1 |ISP DATA 1 Flag (Read Only)
+ * | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete.
+ * | | |0 = FMC_MPDAT1 register is empty, or program to flash complete.
+ * | | |1 = FMC_MPDAT1 register has been written, and not program to flash complete.
+ * |[6] |D2 |ISP DATA 2 Flag (Read Only)
+ * | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete.
+ * | | |0 = FMC_MPDAT2 register is empty, or program to flash complete.
+ * | | |1 = FMC_MPDAT2 register has been written, and not program to flash complete.
+ * |[7] |D3 |ISP DATA 3 Flag (Read Only)
+ * | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete.
+ * | | |0 = FMC_MPDAT3 register is empty, or program to flash complete.
+ * | | |1 = FMC_MPDAT3 register has been written, and not program to flash complete.
+ * @var FMC_T::MPADDR
+ * Offset: 0xC4 ISP Multi-Program Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |MPADDR |ISP Multi-word Program Address
+ * | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.
+ * | | |MPADDR will keep the final ISP address when ISP multi-word program is complete.
+ */
+ __IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */
+ __IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */
+ __IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */
+ __IO uint32_t ISPCMD; /*!< [0x000c] ISP Command Register */
+ __IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */
+ __I uint32_t DFBA; /*!< [0x0014] Data Flash Base Address */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[10];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE1[2];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t CYCCTL; /*!< [0x004c] Flash Access Cycle Control Register */
+ __O uint32_t KPKEY0; /*!< [0x0050] KPROM KEY0 Data Register */
+ __O uint32_t KPKEY1; /*!< [0x0054] KPROM KEY1 Data Register */
+ __O uint32_t KPKEY2; /*!< [0x0058] KPROM KEY2 Data Register */
+ __IO uint32_t KPKEYTRG; /*!< [0x005c] KPROM KEY Comparison Trigger Control Register */
+ __IO uint32_t KPKEYSTS; /*!< [0x0060] KPROM KEY Comparison Status Register */
+ __I uint32_t KPKEYCNT; /*!< [0x0064] KPROM KEY-Unmatched Counting Register */
+ __I uint32_t KPCNT; /*!< [0x0068] KPROM KEY-Unmatched Power-On Counting Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE2[5];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */
+ __IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */
+ __IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */
+ __IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE3[12];
+ /// @endcond //HIDDEN_SYMBOLS
+ __I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-Program Status Register */
+ __I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-Program Address Register */
+
+} FMC_T;
+
+/**
+ @addtogroup FMC_CONST FMC Bit Field Definition
+ Constant Definitions for FMC Controller
+@{ */
+
+#define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */
+#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */
+
+#define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */
+#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */
+
+#define FMC_ISPCTL_SPUEN_Pos (2) /*!< FMC_T::ISPCTL: SPUEN Position */
+#define FMC_ISPCTL_SPUEN_Msk (0x1ul << FMC_ISPCTL_SPUEN_Pos) /*!< FMC_T::ISPCTL: SPUEN Mask */
+
+#define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */
+#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */
+
+#define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */
+#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */
+
+#define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */
+#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */
+
+#define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */
+#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */
+
+#define FMC_ISPCTL_BL_Pos (16) /*!< FMC_T::ISPCTL: BL Position */
+#define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) /*!< FMC_T::ISPCTL: BL Mask */
+
+#define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */
+#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */
+
+#define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */
+#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */
+
+#define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */
+#define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */
+
+#define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */
+#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */
+
+#define FMC_DFBA_DFBA_Pos (0) /*!< FMC_T::DFBA: DFBA Position */
+#define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) /*!< FMC_T::DFBA: DFBA Mask */
+
+#define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */
+#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */
+
+#define FMC_ISPSTS_CBS_Pos (1) /*!< FMC_T::ISPSTS: CBS Position */
+#define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */
+
+#define FMC_ISPSTS_MBS_Pos (3) /*!< FMC_T::ISPSTS: MBS Position */
+#define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) /*!< FMC_T::ISPSTS: MBS Mask */
+
+#define FMC_ISPSTS_FCYCDIS_Pos (4) /*!< FMC_T::ISPSTS: FCYCDIS Position */
+#define FMC_ISPSTS_FCYCDIS_Msk (0x1ul << FMC_ISPSTS_FCYCDIS_Pos) /*!< FMC_T::ISPSTS: FCYCDIS Mask */
+
+#define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */
+#define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */
+
+#define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */
+#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */
+
+#define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ALLONE Position */
+#define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) /*!< FMC_T::ISPSTS: ALLONE Mask */
+
+#define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */
+#define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */
+
+#define FMC_ISPSTS_SCODE_Pos (31) /*!< FMC_T::ISPSTS: SCODE Position */
+#define FMC_ISPSTS_SCODE_Msk (0x1ul << FMC_ISPSTS_SCODE_Pos) /*!< FMC_T::ISPSTS: SCODE Mask */
+
+#define FMC_CYCCTL_CYCLE_Pos (0) /*!< FMC_T::CYCCTL: CYCLE Position */
+#define FMC_CYCCTL_CYCLE_Msk (0xful << FMC_CYCCTL_CYCLE_Pos) /*!< FMC_T::CYCCTL: CYCLE Mask */
+
+#define FMC_KPKEY0_KPKEY0_Pos (0) /*!< FMC_T::KPKEY0: KPKEY0 Position */
+#define FMC_KPKEY0_KPKEY0_Msk (0xfffffffful << FMC_KPKEY0_KPKEY0_Pos) /*!< FMC_T::KPKEY0: KPKEY0 Mask */
+
+#define FMC_KPKEY1_KPKEY1_Pos (0) /*!< FMC_T::KPKEY1: KPKEY1 Position */
+#define FMC_KPKEY1_KPKEY1_Msk (0xfffffffful << FMC_KPKEY1_KPKEY1_Pos) /*!< FMC_T::KPKEY1: KPKEY1 Mask */
+
+#define FMC_KPKEY2_KPKEY2_Pos (0) /*!< FMC_T::KPKEY2: KPKEY2 Position */
+#define FMC_KPKEY2_KPKEY2_Msk (0xfffffffful << FMC_KPKEY2_KPKEY2_Pos) /*!< FMC_T::KPKEY2: KPKEY2 Mask */
+
+#define FMC_KPKEYTRG_KPKEYGO_Pos (0) /*!< FMC_T::KPKEYTRG: KPKEYGO Position */
+#define FMC_KPKEYTRG_KPKEYGO_Msk (0x1ul << FMC_KPKEYTRG_KPKEYGO_Pos) /*!< FMC_T::KPKEYTRG: KPKEYGO Mask */
+
+#define FMC_KPKEYTRG_TCEN_Pos (1) /*!< FMC_T::KPKEYTRG: TCEN Position */
+#define FMC_KPKEYTRG_TCEN_Msk (0x1ul << FMC_KPKEYTRG_TCEN_Pos) /*!< FMC_T::KPKEYTRG: TCEN Mask */
+
+#define FMC_KPKEYSTS_KEYBUSY_Pos (0) /*!< FMC_T::KPKEYSTS: KEYBUSY Position */
+#define FMC_KPKEYSTS_KEYBUSY_Msk (0x1ul << FMC_KPKEYSTS_KEYBUSY_Pos) /*!< FMC_T::KPKEYSTS: KEYBUSY Mask */
+
+#define FMC_KPKEYSTS_KEYLOCK_Pos (1) /*!< FMC_T::KPKEYSTS: KEYLOCK Position */
+#define FMC_KPKEYSTS_KEYLOCK_Msk (0x1ul << FMC_KPKEYSTS_KEYLOCK_Pos) /*!< FMC_T::KPKEYSTS: KEYLOCK Mask */
+
+#define FMC_KPKEYSTS_KEYMATCH_Pos (2) /*!< FMC_T::KPKEYSTS: KEYMATCH Position */
+#define FMC_KPKEYSTS_KEYMATCH_Msk (0x1ul << FMC_KPKEYSTS_KEYMATCH_Pos) /*!< FMC_T::KPKEYSTS: KEYMATCH Mask */
+
+#define FMC_KPKEYSTS_FORBID_Pos (3) /*!< FMC_T::KPKEYSTS: FORBID Position */
+#define FMC_KPKEYSTS_FORBID_Msk (0x1ul << FMC_KPKEYSTS_FORBID_Pos) /*!< FMC_T::KPKEYSTS: FORBID Mask */
+
+#define FMC_KPKEYSTS_KEYFLAG_Pos (4) /*!< FMC_T::KPKEYSTS: KEYFLAG Position */
+#define FMC_KPKEYSTS_KEYFLAG_Msk (0x1ul << FMC_KPKEYSTS_KEYFLAG_Pos) /*!< FMC_T::KPKEYSTS: KEYFLAG Mask */
+
+#define FMC_KPKEYSTS_CFGFLAG_Pos (5) /*!< FMC_T::KPKEYSTS: CFGFLAG Position */
+#define FMC_KPKEYSTS_CFGFLAG_Msk (0x1ul << FMC_KPKEYSTS_CFGFLAG_Pos) /*!< FMC_T::KPKEYSTS: CFGFLAG Mask */
+
+#define FMC_KPKEYSTS_SPFLAG_Pos (6) /*!< FMC_T::KPKEYSTS: SPFLAG Position */
+#define FMC_KPKEYSTS_SPFLAG_Msk (0x1ul << FMC_KPKEYSTS_SPFLAG_Pos) /*!< FMC_T::KPKEYSTS: SPFLAG Mask */
+
+#define FMC_KPKEYCNT_KPKECNT_Pos (0) /*!< FMC_T::KPKEYCNT: KPKECNT Position */
+#define FMC_KPKEYCNT_KPKECNT_Msk (0x3ful << FMC_KPKEYCNT_KPKECNT_Pos) /*!< FMC_T::KPKEYCNT: KPKECNT Mask */
+
+#define FMC_KPKEYCNT_KPKEMAX_Pos (8) /*!< FMC_T::KPKEYCNT: KPKEMAX Position */
+#define FMC_KPKEYCNT_KPKEMAX_Msk (0x3ful << FMC_KPKEYCNT_KPKEMAX_Pos) /*!< FMC_T::KPKEYCNT: KPKEMAX Mask */
+
+#define FMC_KPCNT_KPCNT_Pos (0) /*!< FMC_T::KPCNT: KPCNT Position */
+#define FMC_KPCNT_KPCNT_Msk (0xful << FMC_KPCNT_KPCNT_Pos) /*!< FMC_T::KPCNT: KPCNT Mask */
+
+#define FMC_KPCNT_KPMAX_Pos (8) /*!< FMC_T::KPCNT: KPMAX Position */
+#define FMC_KPCNT_KPMAX_Msk (0xful << FMC_KPCNT_KPMAX_Pos) /*!< FMC_T::KPCNT: KPMAX Mask */
+
+#define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */
+#define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */
+
+#define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */
+#define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */
+
+#define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */
+#define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */
+
+#define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */
+#define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */
+
+#define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */
+#define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */
+
+#define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */
+#define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */
+
+#define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */
+#define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */
+
+#define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */
+#define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */
+
+#define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */
+#define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */
+
+#define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */
+#define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */
+
+#define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */
+#define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */
+
+#define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */
+#define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */
+
+/**@}*/ /* FMC_CONST */
+/**@}*/ /* end of FMC register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __FMC_REG_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Include/m480_gpio_reg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Include/m480_gpio_reg.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,955 @@
+/**************************************************************************//**
+ * @file gpio_reg.h
+ * @version V1.00
+ * @brief GPIO register definition header file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/
+#ifndef __GPIO_REG_H__
+#define __GPIO_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup GPIO General Purpose Input/Output Controller(GPIO)
+ Memory Mapped Structure for GPIO Controller
+@{ */
+
+
+typedef struct {
+
+ /**
+ * @var GPIO_T::MODE
+ * Offset: 0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0 Port A-H I/O Mode Control
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2n+1:2n]|MODEn |Port A-H I/O Pin[n] Mode Control
+ * | | |Determine each I/O mode of Px.n pins.
+ * | | |00 = Px.n is in Input mode.
+ * | | |01 = Px.n is in Push-pull Output mode.
+ * | | |10 = Px.n is in Open-drain Output mode.
+ * | | |11 = Px.n is in Quasi-bidirectional mode.
+ * | | |Note1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).
+ * | | |If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.
+ * | | |If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
+ * | | |Note2:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var GPIO_T::DINOFF
+ * Offset: 0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4 Port A-H Digital Input Path Disable Control
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n+16] |DINOFFn |Port A-H Pin[n] Digital Input Path Disable Control
+ * | | |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled.
+ * | | |If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
+ * | | |0 = Px.n digital input path Enabled.
+ * | | |1 = Px.n digital input path Disabled (digital input tied to low).
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var GPIO_T::DOUT
+ * Offset: 0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8 Port A-H Data Output Value
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |DOUTn |Port A-H Pin[n] Output Value
+ * | | |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
+ * | | |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
+ * | | |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var GPIO_T::DATMSK
+ * Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC Port A-H Data Output Write Mask
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |DATMSKn |Port A-H Pin[n] Data Output Write Mask
+ * | | |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit.
+ * | | |When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected.
+ * | | |If the write signal is masked, writing data to the protect bit is ignored.
+ * | | |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
+ * | | |1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
+ * | | |Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[n]) bit.
+ * | | |Note2:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var GPIO_T::PIN
+ * Offset: 0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0 Port A-H Pin Value
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |PINn |Port A-H Pin[n] Pin Value
+ * | | |Each bit of the register reflects the actual status of the respective Px.n pin.
+ * | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var GPIO_T::DBEN
+ * Offset: 0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4 Port A-H De-Bounce Enable Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |DBENn |Port A-H Pin[n] Input Signal De-Bounce Enable Bit
+ * | | |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.
+ * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt.
+ * | | |The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
+ * | | |0 = Px.n de-bounce function Disabled.
+ * | | |1 = Px.n de-bounce function Enabled.
+ * | | |The de-bounce function is valid only for edge triggered interrupt.
+ * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var GPIO_T::INTTYPE
+ * Offset: 0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8 Port A-H Interrupt Trigger Type Control
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |TYPEn |Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control
+ * | | |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger.
+ * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
+ * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
+ * | | |0 = Edge trigger interrupt.
+ * | | |1 = Level trigger interrupt.
+ * | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]).
+ * | | |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
+ * | | |The de-bounce function is valid only for edge triggered interrupt.
+ * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var GPIO_T::INTEN
+ * Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC Port A-H Interrupt Enable Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |FLIENn |Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
+ * | | |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
+ * | | |Set bit to 1 also enable the pin wake-up function.
+ * | | |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
+ * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
+ * | | |If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
+ * | | |0 = Px.n level low or high to low interrupt Disabled.
+ * | | |1 = Px.n level low or high to low interrupt Enabled.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[n+16] |RHIENn |Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
+ * | | |The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
+ * | | |Set bit to 1 also enable the pin wake-up function.
+ * | | |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
+ * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
+ * | | |If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
+ * | | |0 = Px.n level high or low to high interrupt Disabled.
+ * | | |1 = Px.n level high or low to high interrupt Enabled.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var GPIO_T::INTSRC
+ * Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0 Port A-H Interrupt Source Flag
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |INTSRCn |Port A-H Pin[n] Interrupt Source Flag
+ * | | |Write Operation :
+ * | | |0 = No action.
+ * | | |1 = Clear the corresponding pending interrupt.
+ * | | |Read Operation :
+ * | | |0 = No interrupt at Px.n.
+ * | | |1 = Px.n generates an interrupt.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var GPIO_T::SMTEN
+ * Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4 Port A-H Input Schmitt Trigger Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |SMTENn |Port A-H Pin[n] Input Schmitt Trigger Enable Bit
+ * | | |0 = Px.n input Schmitt trigger function Disabled.
+ * | | |1 = Px.n input Schmitt trigger function Enabled.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var GPIO_T::SLEWCTL
+ * Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8 Port A-H High Slew Rate Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2n+1:2n]|HSRENn |Port A-H Pin[n] High Slew Rate Control
+ * | | |00 = Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V).
+ * | | |01 = Px.n output with high slew rate mode (maximum 80 MHz at 2.7V).
+ * | | |10 = Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V.
+ * | | |11 = Reserved.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var GPIO_T::PUSEL
+ * Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0 Port A-H Pull-up and Pull-down Selection Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2n+1:2n]|PUSELn |Port A-H Pin[n] Pull-up and Pull-down Enable Register
+ * | | |Determine each I/O Pull-up/pull-down of Px.n pins.
+ * | | |00 = Px.n pull-up and pull-up disable.
+ * | | |01 = Px.n pull-up enable.
+ * | | |10 = Px.n pull-down enable.
+ * | | |11 = Reserved.
+ * | | |Note1:
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation
+ * | | |The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode
+ * | | |The independent pull-down control register only valid when MODEn set as tri-state mode
+ * | | |When both pull-up pull-down is set as 1 at tri-state mode, keep I/O in tri-state mode
+ * | | |Note2:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ */
+
+ __IO uint32_t MODE; /* Offset: 0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0 Port A-H I/O Mode Control */
+ __IO uint32_t DINOFF; /* Offset: 0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4 Port A-H Digital Input Path Disable Control */
+ __IO uint32_t DOUT; /* Offset: 0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8 Port A-H Data Output Value */
+ __IO uint32_t DATMSK; /* Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC Port A-H Data Output Write Mask */
+ __I uint32_t PIN; /* Offset: 0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0 Port A-H Pin Value */
+ __IO uint32_t DBEN; /* Offset: 0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4 Port A-H De-Bounce Enable Control Register */
+ __IO uint32_t INTTYPE; /* Offset: 0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8 Port A-H Interrupt Trigger Type Control */
+ __IO uint32_t INTEN; /* Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC Port A-H Interrupt Enable Control Register */
+ __IO uint32_t INTSRC; /* Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0 Port A-H Interrupt Source Flag */
+ __IO uint32_t SMTEN; /* Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4 Port A-H Input Schmitt Trigger Enable Register */
+ __IO uint32_t SLEWCTL; /* Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8 Port A-H High Slew Rate Control Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t PUSEL; /* Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0 Port A-H Pull-up and Pull-down Enable Register */
+
+} GPIO_T;
+
+typedef struct {
+
+ /**
+ * @var GPIO_DBCTL_T::DBCTL
+ * Offset: 0x440 Interrupt De-bounce Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |DBCLKSEL |De-Bounce Sampling Cycle Selection
+ * | | |0000 = Sample interrupt input once per 1 clocks.
+ * | | |0001 = Sample interrupt input once per 2 clocks.
+ * | | |0010 = Sample interrupt input once per 4 clocks.
+ * | | |0011 = Sample interrupt input once per 8 clocks.
+ * | | |0100 = Sample interrupt input once per 16 clocks.
+ * | | |0101 = Sample interrupt input once per 32 clocks.
+ * | | |0110 = Sample interrupt input once per 64 clocks.
+ * | | |0111 = Sample interrupt input once per 128 clocks.
+ * | | |1000 = Sample interrupt input once per 256 clocks.
+ * | | |1001 = Sample interrupt input once per 2*256 clocks.
+ * | | |1010 = Sample interrupt input once per 4*256 clocks.
+ * | | |1011 = Sample interrupt input once per 8*256 clocks.
+ * | | |1100 = Sample interrupt input once per 16*256 clocks.
+ * | | |1101 = Sample interrupt input once per 32*256 clocks.
+ * | | |1110 = Sample interrupt input once per 64*256 clocks.
+ * | | |1111 = Sample interrupt input once per 128*256 clocks.
+ * |[4] |DBCLKSRC |De-Bounce Counter Clock Source Selection
+ * | | |0 = De-bounce counter clock source is the HCLK.
+ * | | |1 = De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC).
+ * |[5] |ICLKON |Interrupt Clock On Mode
+ * | | |0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1.
+ * | | |1 = All I/O pins edge detection circuit is always active after reset.
+ * | | |Note: It is recommended to disable this bit to save system power if no special application concern.
+ */
+
+ __IO uint32_t DBCTL; /* Offset: 0x440 Interrupt De-bounce Control Register */
+
+} GPIO_DBCTL_T;
+
+/**
+ @addtogroup GPIO_CONST GPIO Bit Field Definition
+ Constant Definitions for GPIO Controller
+@{ */
+
+#define GPIO_MODE_MODE0_Pos (0) /*!< GPIO_T::MODE: MODE0 Position */
+#define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) /*!< GPIO_T::MODE: MODE0 Mask */
+
+#define GPIO_MODE_MODE1_Pos (2) /*!< GPIO_T::MODE: MODE1 Position */
+#define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) /*!< GPIO_T::MODE: MODE1 Mask */
+
+#define GPIO_MODE_MODE2_Pos (4) /*!< GPIO_T::MODE: MODE2 Position */
+#define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) /*!< GPIO_T::MODE: MODE2 Mask */
+
+#define GPIO_MODE_MODE3_Pos (6) /*!< GPIO_T::MODE: MODE3 Position */
+#define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) /*!< GPIO_T::MODE: MODE3 Mask */
+
+#define GPIO_MODE_MODE4_Pos (8) /*!< GPIO_T::MODE: MODE4 Position */
+#define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) /*!< GPIO_T::MODE: MODE4 Mask */
+
+#define GPIO_MODE_MODE5_Pos (10) /*!< GPIO_T::MODE: MODE5 Position */
+#define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) /*!< GPIO_T::MODE: MODE5 Mask */
+
+#define GPIO_MODE_MODE6_Pos (12) /*!< GPIO_T::MODE: MODE6 Position */
+#define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) /*!< GPIO_T::MODE: MODE6 Mask */
+
+#define GPIO_MODE_MODE7_Pos (14) /*!< GPIO_T::MODE: MODE7 Position */
+#define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) /*!< GPIO_T::MODE: MODE7 Mask */
+
+#define GPIO_MODE_MODE8_Pos (16) /*!< GPIO_T::MODE: MODE8 Position */
+#define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) /*!< GPIO_T::MODE: MODE8 Mask */
+
+#define GPIO_MODE_MODE9_Pos (18) /*!< GPIO_T::MODE: MODE9 Position */
+#define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) /*!< GPIO_T::MODE: MODE9 Mask */
+
+#define GPIO_MODE_MODE10_Pos (20) /*!< GPIO_T::MODE: MODE10 Position */
+#define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) /*!< GPIO_T::MODE: MODE10 Mask */
+
+#define GPIO_MODE_MODE11_Pos (22) /*!< GPIO_T::MODE: MODE11 Position */
+#define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) /*!< GPIO_T::MODE: MODE11 Mask */
+
+#define GPIO_MODE_MODE12_Pos (24) /*!< GPIO_T::MODE: MODE12 Position */
+#define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) /*!< GPIO_T::MODE: MODE12 Mask */
+
+#define GPIO_MODE_MODE13_Pos (26) /*!< GPIO_T::MODE: MODE13 Position */
+#define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) /*!< GPIO_T::MODE: MODE13 Mask */
+
+#define GPIO_MODE_MODE14_Pos (28) /*!< GPIO_T::MODE: MODE14 Position */
+#define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) /*!< GPIO_T::MODE: MODE14 Mask */
+
+#define GPIO_MODE_MODE15_Pos (30) /*!< GPIO_T::MODE: MODE15 Position */
+#define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) /*!< GPIO_T::MODE: MODE15 Mask */
+
+#define GPIO_DINOFF_DINOFF0_Pos (16) /*!< GPIO_T::DINOFF: DINOFF0 Position */
+#define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) /*!< GPIO_T::DINOFF: DINOFF0 Mask */
+
+#define GPIO_DINOFF_DINOFF1_Pos (17) /*!< GPIO_T::DINOFF: DINOFF1 Position */
+#define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) /*!< GPIO_T::DINOFF: DINOFF1 Mask */
+
+#define GPIO_DINOFF_DINOFF2_Pos (18) /*!< GPIO_T::DINOFF: DINOFF2 Position */
+#define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) /*!< GPIO_T::DINOFF: DINOFF2 Mask */
+
+#define GPIO_DINOFF_DINOFF3_Pos (19) /*!< GPIO_T::DINOFF: DINOFF3 Position */
+#define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) /*!< GPIO_T::DINOFF: DINOFF3 Mask */
+
+#define GPIO_DINOFF_DINOFF4_Pos (20) /*!< GPIO_T::DINOFF: DINOFF4 Position */
+#define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) /*!< GPIO_T::DINOFF: DINOFF4 Mask */
+
+#define GPIO_DINOFF_DINOFF5_Pos (21) /*!< GPIO_T::DINOFF: DINOFF5 Position */
+#define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) /*!< GPIO_T::DINOFF: DINOFF5 Mask */
+
+#define GPIO_DINOFF_DINOFF6_Pos (22) /*!< GPIO_T::DINOFF: DINOFF6 Position */
+#define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) /*!< GPIO_T::DINOFF: DINOFF6 Mask */
+
+#define GPIO_DINOFF_DINOFF7_Pos (23) /*!< GPIO_T::DINOFF: DINOFF7 Position */
+#define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) /*!< GPIO_T::DINOFF: DINOFF7 Mask */
+
+#define GPIO_DINOFF_DINOFF8_Pos (24) /*!< GPIO_T::DINOFF: DINOFF8 Position */
+#define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) /*!< GPIO_T::DINOFF: DINOFF8 Mask */
+
+#define GPIO_DINOFF_DINOFF9_Pos (25) /*!< GPIO_T::DINOFF: DINOFF9 Position */
+#define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) /*!< GPIO_T::DINOFF: DINOFF9 Mask */
+
+#define GPIO_DINOFF_DINOFF10_Pos (26) /*!< GPIO_T::DINOFF: DINOFF10 Position */
+#define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) /*!< GPIO_T::DINOFF: DINOFF10 Mask */
+
+#define GPIO_DINOFF_DINOFF11_Pos (27) /*!< GPIO_T::DINOFF: DINOFF11 Position */
+#define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) /*!< GPIO_T::DINOFF: DINOFF11 Mask */
+
+#define GPIO_DINOFF_DINOFF12_Pos (28) /*!< GPIO_T::DINOFF: DINOFF12 Position */
+#define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) /*!< GPIO_T::DINOFF: DINOFF12 Mask */
+
+#define GPIO_DINOFF_DINOFF13_Pos (29) /*!< GPIO_T::DINOFF: DINOFF13 Position */
+#define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) /*!< GPIO_T::DINOFF: DINOFF13 Mask */
+
+#define GPIO_DINOFF_DINOFF14_Pos (30) /*!< GPIO_T::DINOFF: DINOFF14 Position */
+#define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) /*!< GPIO_T::DINOFF: DINOFF14 Mask */
+
+#define GPIO_DINOFF_DINOFF15_Pos (31) /*!< GPIO_T::DINOFF: DINOFF15 Position */
+#define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) /*!< GPIO_T::DINOFF: DINOFF15 Mask */
+
+#define GPIO_DOUT_DOUT0_Pos (0) /*!< GPIO_T::DOUT: DOUT0 Position */
+#define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) /*!< GPIO_T::DOUT: DOUT0 Mask */
+
+#define GPIO_DOUT_DOUT1_Pos (1) /*!< GPIO_T::DOUT: DOUT1 Position */
+#define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) /*!< GPIO_T::DOUT: DOUT1 Mask */
+
+#define GPIO_DOUT_DOUT2_Pos (2) /*!< GPIO_T::DOUT: DOUT2 Position */
+#define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) /*!< GPIO_T::DOUT: DOUT2 Mask */
+
+#define GPIO_DOUT_DOUT3_Pos (3) /*!< GPIO_T::DOUT: DOUT3 Position */
+#define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) /*!< GPIO_T::DOUT: DOUT3 Mask */
+
+#define GPIO_DOUT_DOUT4_Pos (4) /*!< GPIO_T::DOUT: DOUT4 Position */
+#define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) /*!< GPIO_T::DOUT: DOUT4 Mask */
+
+#define GPIO_DOUT_DOUT5_Pos (5) /*!< GPIO_T::DOUT: DOUT5 Position */
+#define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) /*!< GPIO_T::DOUT: DOUT5 Mask */
+
+#define GPIO_DOUT_DOUT6_Pos (6) /*!< GPIO_T::DOUT: DOUT6 Position */
+#define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) /*!< GPIO_T::DOUT: DOUT6 Mask */
+
+#define GPIO_DOUT_DOUT7_Pos (7) /*!< GPIO_T::DOUT: DOUT7 Position */
+#define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) /*!< GPIO_T::DOUT: DOUT7 Mask */
+
+#define GPIO_DOUT_DOUT8_Pos (8) /*!< GPIO_T::DOUT: DOUT8 Position */
+#define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) /*!< GPIO_T::DOUT: DOUT8 Mask */
+
+#define GPIO_DOUT_DOUT9_Pos (9) /*!< GPIO_T::DOUT: DOUT9 Position */
+#define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) /*!< GPIO_T::DOUT: DOUT9 Mask */
+
+#define GPIO_DOUT_DOUT10_Pos (10) /*!< GPIO_T::DOUT: DOUT10 Position */
+#define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) /*!< GPIO_T::DOUT: DOUT10 Mask */
+
+#define GPIO_DOUT_DOUT11_Pos (11) /*!< GPIO_T::DOUT: DOUT11 Position */
+#define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) /*!< GPIO_T::DOUT: DOUT11 Mask */
+
+#define GPIO_DOUT_DOUT12_Pos (12) /*!< GPIO_T::DOUT: DOUT12 Position */
+#define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) /*!< GPIO_T::DOUT: DOUT12 Mask */
+
+#define GPIO_DOUT_DOUT13_Pos (13) /*!< GPIO_T::DOUT: DOUT13 Position */
+#define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) /*!< GPIO_T::DOUT: DOUT13 Mask */
+
+#define GPIO_DOUT_DOUT14_Pos (14) /*!< GPIO_T::DOUT: DOUT14 Position */
+#define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) /*!< GPIO_T::DOUT: DOUT14 Mask */
+
+#define GPIO_DOUT_DOUT15_Pos (15) /*!< GPIO_T::DOUT: DOUT15 Position */
+#define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) /*!< GPIO_T::DOUT: DOUT15 Mask */
+
+#define GPIO_DATMSK_DATMSK0_Pos (0) /*!< GPIO_T::DATMSK: DATMSK0 Position */
+#define GPIO_DATMSK_DATMSK0_Msk (0x1ul << GPIO_DATMSK_DATMSK0_Pos) /*!< GPIO_T::DATMSK: DATMSK0 Mask */
+
+#define GPIO_DATMSK_DATMSK1_Pos (1) /*!< GPIO_T::DATMSK: DATMSK1 Position */
+#define GPIO_DATMSK_DATMSK1_Msk (0x1ul << GPIO_DATMSK_DATMSK1_Pos) /*!< GPIO_T::DATMSK: DATMSK1 Mask */
+
+#define GPIO_DATMSK_DATMSK2_Pos (2) /*!< GPIO_T::DATMSK: DATMSK2 Position */
+#define GPIO_DATMSK_DATMSK2_Msk (0x1ul << GPIO_DATMSK_DATMSK2_Pos) /*!< GPIO_T::DATMSK: DATMSK2 Mask */
+
+#define GPIO_DATMSK_DATMSK3_Pos (3) /*!< GPIO_T::DATMSK: DATMSK3 Position */
+#define GPIO_DATMSK_DATMSK3_Msk (0x1ul << GPIO_DATMSK_DATMSK3_Pos) /*!< GPIO_T::DATMSK: DATMSK3 Mask */
+
+#define GPIO_DATMSK_DATMSK4_Pos (4) /*!< GPIO_T::DATMSK: DATMSK4 Position */
+#define GPIO_DATMSK_DATMSK4_Msk (0x1ul << GPIO_DATMSK_DATMSK4_Pos) /*!< GPIO_T::DATMSK: DATMSK4 Mask */
+
+#define GPIO_DATMSK_DATMSK5_Pos (5) /*!< GPIO_T::DATMSK: DATMSK5 Position */
+#define GPIO_DATMSK_DATMSK5_Msk (0x1ul << GPIO_DATMSK_DATMSK5_Pos) /*!< GPIO_T::DATMSK: DATMSK5 Mask */
+
+#define GPIO_DATMSK_DATMSK6_Pos (6) /*!< GPIO_T::DATMSK: DATMSK6 Position */
+#define GPIO_DATMSK_DATMSK6_Msk (0x1ul << GPIO_DATMSK_DATMSK6_Pos) /*!< GPIO_T::DATMSK: DATMSK6 Mask */
+
+#define GPIO_DATMSK_DATMSK7_Pos (7) /*!< GPIO_T::DATMSK: DATMSK7 Position */
+#define GPIO_DATMSK_DATMSK7_Msk (0x1ul << GPIO_DATMSK_DATMSK7_Pos) /*!< GPIO_T::DATMSK: DATMSK7 Mask */
+
+#define GPIO_DATMSK_DATMSK8_Pos (8) /*!< GPIO_T::DATMSK: DATMSK8 Position */
+#define GPIO_DATMSK_DATMSK8_Msk (0x1ul << GPIO_DATMSK_DATMSK8_Pos) /*!< GPIO_T::DATMSK: DATMSK8 Mask */
+
+#define GPIO_DATMSK_DATMSK9_Pos (9) /*!< GPIO_T::DATMSK: DATMSK9 Position */
+#define GPIO_DATMSK_DATMSK9_Msk (0x1ul << GPIO_DATMSK_DATMSK9_Pos) /*!< GPIO_T::DATMSK: DATMSK9 Mask */
+
+#define GPIO_DATMSK_DATMSK10_Pos (10) /*!< GPIO_T::DATMSK: DATMSK10 Position */
+#define GPIO_DATMSK_DATMSK10_Msk (0x1ul << GPIO_DATMSK_DATMSK10_Pos) /*!< GPIO_T::DATMSK: DATMSK10 Mask */
+
+#define GPIO_DATMSK_DATMSK11_Pos (11) /*!< GPIO_T::DATMSK: DATMSK11 Position */
+#define GPIO_DATMSK_DATMSK11_Msk (0x1ul << GPIO_DATMSK_DATMSK11_Pos) /*!< GPIO_T::DATMSK: DATMSK11 Mask */
+
+#define GPIO_DATMSK_DATMSK12_Pos (12) /*!< GPIO_T::DATMSK: DATMSK12 Position */
+#define GPIO_DATMSK_DATMSK12_Msk (0x1ul << GPIO_DATMSK_DATMSK12_Pos) /*!< GPIO_T::DATMSK: DATMSK12 Mask */
+
+#define GPIO_DATMSK_DATMSK13_Pos (13) /*!< GPIO_T::DATMSK: DATMSK13 Position */
+#define GPIO_DATMSK_DATMSK13_Msk (0x1ul << GPIO_DATMSK_DATMSK13_Pos) /*!< GPIO_T::DATMSK: DATMSK13 Mask */
+
+#define GPIO_DATMSK_DATMSK14_Pos (14) /*!< GPIO_T::DATMSK: DATMSK14 Position */
+#define GPIO_DATMSK_DATMSK14_Msk (0x1ul << GPIO_DATMSK_DATMSK14_Pos) /*!< GPIO_T::DATMSK: DATMSK14 Mask */
+
+#define GPIO_DATMSK_DATMSK15_Pos (15) /*!< GPIO_T::DATMSK: DATMSK15 Position */
+#define GPIO_DATMSK_DATMSK15_Msk (0x1ul << GPIO_DATMSK_DATMSK15_Pos) /*!< GPIO_T::DATMSK: DATMSK15 Mask */
+
+#define GPIO_PIN_PIN0_Pos (0) /*!< GPIO_T::PIN: PIN0 Position */
+#define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) /*!< GPIO_T::PIN: PIN0 Mask */
+
+#define GPIO_PIN_PIN1_Pos (1) /*!< GPIO_T::PIN: PIN1 Position */
+#define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) /*!< GPIO_T::PIN: PIN1 Mask */
+
+#define GPIO_PIN_PIN2_Pos (2) /*!< GPIO_T::PIN: PIN2 Position */
+#define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) /*!< GPIO_T::PIN: PIN2 Mask */
+
+#define GPIO_PIN_PIN3_Pos (3) /*!< GPIO_T::PIN: PIN3 Position */
+#define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) /*!< GPIO_T::PIN: PIN3 Mask */
+
+#define GPIO_PIN_PIN4_Pos (4) /*!< GPIO_T::PIN: PIN4 Position */
+#define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) /*!< GPIO_T::PIN: PIN4 Mask */
+
+#define GPIO_PIN_PIN5_Pos (5) /*!< GPIO_T::PIN: PIN5 Position */
+#define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) /*!< GPIO_T::PIN: PIN5 Mask */
+
+#define GPIO_PIN_PIN6_Pos (6) /*!< GPIO_T::PIN: PIN6 Position */
+#define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) /*!< GPIO_T::PIN: PIN6 Mask */
+
+#define GPIO_PIN_PIN7_Pos (7) /*!< GPIO_T::PIN: PIN7 Position */
+#define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) /*!< GPIO_T::PIN: PIN7 Mask */
+
+#define GPIO_PIN_PIN8_Pos (8) /*!< GPIO_T::PIN: PIN8 Position */
+#define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) /*!< GPIO_T::PIN: PIN8 Mask */
+
+#define GPIO_PIN_PIN9_Pos (9) /*!< GPIO_T::PIN: PIN9 Position */
+#define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) /*!< GPIO_T::PIN: PIN9 Mask */
+
+#define GPIO_PIN_PIN10_Pos (10) /*!< GPIO_T::PIN: PIN10 Position */
+#define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) /*!< GPIO_T::PIN: PIN10 Mask */
+
+#define GPIO_PIN_PIN11_Pos (11) /*!< GPIO_T::PIN: PIN11 Position */
+#define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) /*!< GPIO_T::PIN: PIN11 Mask */
+
+#define GPIO_PIN_PIN12_Pos (12) /*!< GPIO_T::PIN: PIN12 Position */
+#define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) /*!< GPIO_T::PIN: PIN12 Mask */
+
+#define GPIO_PIN_PIN13_Pos (13) /*!< GPIO_T::PIN: PIN13 Position */
+#define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) /*!< GPIO_T::PIN: PIN13 Mask */
+
+#define GPIO_PIN_PIN14_Pos (14) /*!< GPIO_T::PIN: PIN14 Position */
+#define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) /*!< GPIO_T::PIN: PIN14 Mask */
+
+#define GPIO_PIN_PIN15_Pos (15) /*!< GPIO_T::PIN: PIN15 Position */
+#define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) /*!< GPIO_T::PIN: PIN15 Mask */
+
+#define GPIO_DBEN_DBEN0_Pos (0) /*!< GPIO_T::DBEN: DBEN0 Position */
+#define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) /*!< GPIO_T::DBEN: DBEN0 Mask */
+
+#define GPIO_DBEN_DBEN1_Pos (1) /*!< GPIO_T::DBEN: DBEN1 Position */
+#define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) /*!< GPIO_T::DBEN: DBEN1 Mask */
+
+#define GPIO_DBEN_DBEN2_Pos (2) /*!< GPIO_T::DBEN: DBEN2 Position */
+#define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) /*!< GPIO_T::DBEN: DBEN2 Mask */
+
+#define GPIO_DBEN_DBEN3_Pos (3) /*!< GPIO_T::DBEN: DBEN3 Position */
+#define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) /*!< GPIO_T::DBEN: DBEN3 Mask */
+
+#define GPIO_DBEN_DBEN4_Pos (4) /*!< GPIO_T::DBEN: DBEN4 Position */
+#define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) /*!< GPIO_T::DBEN: DBEN4 Mask */
+
+#define GPIO_DBEN_DBEN5_Pos (5) /*!< GPIO_T::DBEN: DBEN5 Position */
+#define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) /*!< GPIO_T::DBEN: DBEN5 Mask */
+
+#define GPIO_DBEN_DBEN6_Pos (6) /*!< GPIO_T::DBEN: DBEN6 Position */
+#define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) /*!< GPIO_T::DBEN: DBEN6 Mask */
+
+#define GPIO_DBEN_DBEN7_Pos (7) /*!< GPIO_T::DBEN: DBEN7 Position */
+#define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) /*!< GPIO_T::DBEN: DBEN7 Mask */
+
+#define GPIO_DBEN_DBEN8_Pos (8) /*!< GPIO_T::DBEN: DBEN8 Position */
+#define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) /*!< GPIO_T::DBEN: DBEN8 Mask */
+
+#define GPIO_DBEN_DBEN9_Pos (9) /*!< GPIO_T::DBEN: DBEN9 Position */
+#define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) /*!< GPIO_T::DBEN: DBEN9 Mask */
+
+#define GPIO_DBEN_DBEN10_Pos (10) /*!< GPIO_T::DBEN: DBEN10 Position */
+#define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) /*!< GPIO_T::DBEN: DBEN10 Mask */
+
+#define GPIO_DBEN_DBEN11_Pos (11) /*!< GPIO_T::DBEN: DBEN11 Position */
+#define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) /*!< GPIO_T::DBEN: DBEN11 Mask */
+
+#define GPIO_DBEN_DBEN12_Pos (12) /*!< GPIO_T::DBEN: DBEN12 Position */
+#define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) /*!< GPIO_T::DBEN: DBEN12 Mask */
+
+#define GPIO_DBEN_DBEN13_Pos (13) /*!< GPIO_T::DBEN: DBEN13 Position */
+#define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) /*!< GPIO_T::DBEN: DBEN13 Mask */
+
+#define GPIO_DBEN_DBEN14_Pos (14) /*!< GPIO_T::DBEN: DBEN14 Position */
+#define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) /*!< GPIO_T::DBEN: DBEN14 Mask */
+
+#define GPIO_DBEN_DBEN15_Pos (15) /*!< GPIO_T::DBEN: DBEN15 Position */
+#define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) /*!< GPIO_T::DBEN: DBEN15 Mask */
+
+#define GPIO_INTTYPE_TYPE0_Pos (0) /*!< GPIO_T::INTTYPE: TYPE0 Position */
+#define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) /*!< GPIO_T::INTTYPE: TYPE0 Mask */
+
+#define GPIO_INTTYPE_TYPE1_Pos (1) /*!< GPIO_T::INTTYPE: TYPE1 Position */
+#define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) /*!< GPIO_T::INTTYPE: TYPE1 Mask */
+
+#define GPIO_INTTYPE_TYPE2_Pos (2) /*!< GPIO_T::INTTYPE: TYPE2 Position */
+#define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) /*!< GPIO_T::INTTYPE: TYPE2 Mask */
+
+#define GPIO_INTTYPE_TYPE3_Pos (3) /*!< GPIO_T::INTTYPE: TYPE3 Position */
+#define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) /*!< GPIO_T::INTTYPE: TYPE3 Mask */
+
+#define GPIO_INTTYPE_TYPE4_Pos (4) /*!< GPIO_T::INTTYPE: TYPE4 Position */
+#define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) /*!< GPIO_T::INTTYPE: TYPE4 Mask */
+
+#define GPIO_INTTYPE_TYPE5_Pos (5) /*!< GPIO_T::INTTYPE: TYPE5 Position */
+#define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) /*!< GPIO_T::INTTYPE: TYPE5 Mask */
+
+#define GPIO_INTTYPE_TYPE6_Pos (6) /*!< GPIO_T::INTTYPE: TYPE6 Position */
+#define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) /*!< GPIO_T::INTTYPE: TYPE6 Mask */
+
+#define GPIO_INTTYPE_TYPE7_Pos (7) /*!< GPIO_T::INTTYPE: TYPE7 Position */
+#define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) /*!< GPIO_T::INTTYPE: TYPE7 Mask */
+
+#define GPIO_INTTYPE_TYPE8_Pos (8) /*!< GPIO_T::INTTYPE: TYPE8 Position */
+#define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) /*!< GPIO_T::INTTYPE: TYPE8 Mask */
+
+#define GPIO_INTTYPE_TYPE9_Pos (9) /*!< GPIO_T::INTTYPE: TYPE9 Position */
+#define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) /*!< GPIO_T::INTTYPE: TYPE9 Mask */
+
+#define GPIO_INTTYPE_TYPE10_Pos (10) /*!< GPIO_T::INTTYPE: TYPE10 Position */
+#define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) /*!< GPIO_T::INTTYPE: TYPE10 Mask */
+
+#define GPIO_INTTYPE_TYPE11_Pos (11) /*!< GPIO_T::INTTYPE: TYPE11 Position */
+#define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) /*!< GPIO_T::INTTYPE: TYPE11 Mask */
+
+#define GPIO_INTTYPE_TYPE12_Pos (12) /*!< GPIO_T::INTTYPE: TYPE12 Position */
+#define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) /*!< GPIO_T::INTTYPE: TYPE12 Mask */
+
+#define GPIO_INTTYPE_TYPE13_Pos (13) /*!< GPIO_T::INTTYPE: TYPE13 Position */
+#define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) /*!< GPIO_T::INTTYPE: TYPE13 Mask */
+
+#define GPIO_INTTYPE_TYPE14_Pos (14) /*!< GPIO_T::INTTYPE: TYPE14 Position */
+#define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) /*!< GPIO_T::INTTYPE: TYPE14 Mask */
+
+#define GPIO_INTTYPE_TYPE15_Pos (15) /*!< GPIO_T::INTTYPE: TYPE15 Position */
+#define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) /*!< GPIO_T::INTTYPE: TYPE15 Mask */
+
+#define GPIO_INTEN_FLIEN0_Pos (0) /*!< GPIO_T::INTEN: FLIEN0 Position */
+#define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) /*!< GPIO_T::INTEN: FLIEN0 Mask */
+
+#define GPIO_INTEN_FLIEN1_Pos (1) /*!< GPIO_T::INTEN: FLIEN1 Position */
+#define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) /*!< GPIO_T::INTEN: FLIEN1 Mask */
+
+#define GPIO_INTEN_FLIEN2_Pos (2) /*!< GPIO_T::INTEN: FLIEN2 Position */
+#define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) /*!< GPIO_T::INTEN: FLIEN2 Mask */
+
+#define GPIO_INTEN_FLIEN3_Pos (3) /*!< GPIO_T::INTEN: FLIEN3 Position */
+#define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) /*!< GPIO_T::INTEN: FLIEN3 Mask */
+
+#define GPIO_INTEN_FLIEN4_Pos (4) /*!< GPIO_T::INTEN: FLIEN4 Position */
+#define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) /*!< GPIO_T::INTEN: FLIEN4 Mask */
+
+#define GPIO_INTEN_FLIEN5_Pos (5) /*!< GPIO_T::INTEN: FLIEN5 Position */
+#define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) /*!< GPIO_T::INTEN: FLIEN5 Mask */
+
+#define GPIO_INTEN_FLIEN6_Pos (6) /*!< GPIO_T::INTEN: FLIEN6 Position */
+#define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) /*!< GPIO_T::INTEN: FLIEN6 Mask */
+
+#define GPIO_INTEN_FLIEN7_Pos (7) /*!< GPIO_T::INTEN: FLIEN7 Position */
+#define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) /*!< GPIO_T::INTEN: FLIEN7 Mask */
+
+#define GPIO_INTEN_FLIEN8_Pos (8) /*!< GPIO_T::INTEN: FLIEN8 Position */
+#define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) /*!< GPIO_T::INTEN: FLIEN8 Mask */
+
+#define GPIO_INTEN_FLIEN9_Pos (9) /*!< GPIO_T::INTEN: FLIEN9 Position */
+#define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) /*!< GPIO_T::INTEN: FLIEN9 Mask */
+
+#define GPIO_INTEN_FLIEN10_Pos (10) /*!< GPIO_T::INTEN: FLIEN10 Position */
+#define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) /*!< GPIO_T::INTEN: FLIEN10 Mask */
+
+#define GPIO_INTEN_FLIEN11_Pos (11) /*!< GPIO_T::INTEN: FLIEN11 Position */
+#define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) /*!< GPIO_T::INTEN: FLIEN11 Mask */
+
+#define GPIO_INTEN_FLIEN12_Pos (12) /*!< GPIO_T::INTEN: FLIEN12 Position */
+#define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) /*!< GPIO_T::INTEN: FLIEN12 Mask */
+
+#define GPIO_INTEN_FLIEN13_Pos (13) /*!< GPIO_T::INTEN: FLIEN13 Position */
+#define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) /*!< GPIO_T::INTEN: FLIEN13 Mask */
+
+#define GPIO_INTEN_FLIEN14_Pos (14) /*!< GPIO_T::INTEN: FLIEN14 Position */
+#define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) /*!< GPIO_T::INTEN: FLIEN14 Mask */
+
+#define GPIO_INTEN_FLIEN15_Pos (15) /*!< GPIO_T::INTEN: FLIEN15 Position */
+#define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) /*!< GPIO_T::INTEN: FLIEN15 Mask */
+
+#define GPIO_INTEN_RHIEN0_Pos (16) /*!< GPIO_T::INTEN: RHIEN0 Position */
+#define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) /*!< GPIO_T::INTEN: RHIEN0 Mask */
+
+#define GPIO_INTEN_RHIEN1_Pos (17) /*!< GPIO_T::INTEN: RHIEN1 Position */
+#define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) /*!< GPIO_T::INTEN: RHIEN1 Mask */
+
+#define GPIO_INTEN_RHIEN2_Pos (18) /*!< GPIO_T::INTEN: RHIEN2 Position */
+#define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) /*!< GPIO_T::INTEN: RHIEN2 Mask */
+
+#define GPIO_INTEN_RHIEN3_Pos (19) /*!< GPIO_T::INTEN: RHIEN3 Position */
+#define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) /*!< GPIO_T::INTEN: RHIEN3 Mask */
+
+#define GPIO_INTEN_RHIEN4_Pos (20) /*!< GPIO_T::INTEN: RHIEN4 Position */
+#define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) /*!< GPIO_T::INTEN: RHIEN4 Mask */
+
+#define GPIO_INTEN_RHIEN5_Pos (21) /*!< GPIO_T::INTEN: RHIEN5 Position */
+#define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) /*!< GPIO_T::INTEN: RHIEN5 Mask */
+
+#define GPIO_INTEN_RHIEN6_Pos (22) /*!< GPIO_T::INTEN: RHIEN6 Position */
+#define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) /*!< GPIO_T::INTEN: RHIEN6 Mask */
+
+#define GPIO_INTEN_RHIEN7_Pos (23) /*!< GPIO_T::INTEN: RHIEN7 Position */
+#define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) /*!< GPIO_T::INTEN: RHIEN7 Mask */
+
+#define GPIO_INTEN_RHIEN8_Pos (24) /*!< GPIO_T::INTEN: RHIEN8 Position */
+#define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) /*!< GPIO_T::INTEN: RHIEN8 Mask */
+
+#define GPIO_INTEN_RHIEN9_Pos (25) /*!< GPIO_T::INTEN: RHIEN9 Position */
+#define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) /*!< GPIO_T::INTEN: RHIEN9 Mask */
+
+#define GPIO_INTEN_RHIEN10_Pos (26) /*!< GPIO_T::INTEN: RHIEN10 Position */
+#define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) /*!< GPIO_T::INTEN: RHIEN10 Mask */
+
+#define GPIO_INTEN_RHIEN11_Pos (27) /*!< GPIO_T::INTEN: RHIEN11 Position */
+#define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) /*!< GPIO_T::INTEN: RHIEN11 Mask */
+
+#define GPIO_INTEN_RHIEN12_Pos (28) /*!< GPIO_T::INTEN: RHIEN12 Position */
+#define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) /*!< GPIO_T::INTEN: RHIEN12 Mask */
+
+#define GPIO_INTEN_RHIEN13_Pos (29) /*!< GPIO_T::INTEN: RHIEN13 Position */
+#define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) /*!< GPIO_T::INTEN: RHIEN13 Mask */
+
+#define GPIO_INTEN_RHIEN14_Pos (30) /*!< GPIO_T::INTEN: RHIEN14 Position */
+#define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) /*!< GPIO_T::INTEN: RHIEN14 Mask */
+
+#define GPIO_INTEN_RHIEN15_Pos (31) /*!< GPIO_T::INTEN: RHIEN15 Position */
+#define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) /*!< GPIO_T::INTEN: RHIEN15 Mask */
+
+#define GPIO_INTSRC_INTSRC0_Pos (0) /*!< GPIO_T::INTSRC: INTSRC0 Position */
+#define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) /*!< GPIO_T::INTSRC: INTSRC0 Mask */
+
+#define GPIO_INTSRC_INTSRC1_Pos (1) /*!< GPIO_T::INTSRC: INTSRC1 Position */
+#define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) /*!< GPIO_T::INTSRC: INTSRC1 Mask */
+
+#define GPIO_INTSRC_INTSRC2_Pos (2) /*!< GPIO_T::INTSRC: INTSRC2 Position */
+#define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) /*!< GPIO_T::INTSRC: INTSRC2 Mask */
+
+#define GPIO_INTSRC_INTSRC3_Pos (3) /*!< GPIO_T::INTSRC: INTSRC3 Position */
+#define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) /*!< GPIO_T::INTSRC: INTSRC3 Mask */
+
+#define GPIO_INTSRC_INTSRC4_Pos (4) /*!< GPIO_T::INTSRC: INTSRC4 Position */
+#define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) /*!< GPIO_T::INTSRC: INTSRC4 Mask */
+
+#define GPIO_INTSRC_INTSRC5_Pos (5) /*!< GPIO_T::INTSRC: INTSRC5 Position */
+#define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) /*!< GPIO_T::INTSRC: INTSRC5 Mask */
+
+#define GPIO_INTSRC_INTSRC6_Pos (6) /*!< GPIO_T::INTSRC: INTSRC6 Position */
+#define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) /*!< GPIO_T::INTSRC: INTSRC6 Mask */
+
+#define GPIO_INTSRC_INTSRC7_Pos (7) /*!< GPIO_T::INTSRC: INTSRC7 Position */
+#define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) /*!< GPIO_T::INTSRC: INTSRC7 Mask */
+
+#define GPIO_INTSRC_INTSRC8_Pos (8) /*!< GPIO_T::INTSRC: INTSRC8 Position */
+#define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) /*!< GPIO_T::INTSRC: INTSRC8 Mask */
+
+#define GPIO_INTSRC_INTSRC9_Pos (9) /*!< GPIO_T::INTSRC: INTSRC9 Position */
+#define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) /*!< GPIO_T::INTSRC: INTSRC9 Mask */
+
+#define GPIO_INTSRC_INTSRC10_Pos (10) /*!< GPIO_T::INTSRC: INTSRC10 Position */
+#define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) /*!< GPIO_T::INTSRC: INTSRC10 Mask */
+
+#define GPIO_INTSRC_INTSRC11_Pos (11) /*!< GPIO_T::INTSRC: INTSRC11 Position */
+#define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) /*!< GPIO_T::INTSRC: INTSRC11 Mask */
+
+#define GPIO_INTSRC_INTSRC12_Pos (12) /*!< GPIO_T::INTSRC: INTSRC12 Position */
+#define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) /*!< GPIO_T::INTSRC: INTSRC12 Mask */
+
+#define GPIO_INTSRC_INTSRC13_Pos (13) /*!< GPIO_T::INTSRC: INTSRC13 Position */
+#define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) /*!< GPIO_T::INTSRC: INTSRC13 Mask */
+
+#define GPIO_INTSRC_INTSRC14_Pos (14) /*!< GPIO_T::INTSRC: INTSRC14 Position */
+#define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) /*!< GPIO_T::INTSRC: INTSRC14 Mask */
+
+#define GPIO_INTSRC_INTSRC15_Pos (15) /*!< GPIO_T::INTSRC: INTSRC15 Position */
+#define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) /*!< GPIO_T::INTSRC: INTSRC15 Mask */
+
+#define GPIO_SMTEN_SMTEN0_Pos (0) /*!< GPIO_T::SMTEN: SMTEN0 Position */
+#define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) /*!< GPIO_T::SMTEN: SMTEN0 Mask */
+
+#define GPIO_SMTEN_SMTEN1_Pos (1) /*!< GPIO_T::SMTEN: SMTEN1 Position */
+#define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) /*!< GPIO_T::SMTEN: SMTEN1 Mask */
+
+#define GPIO_SMTEN_SMTEN2_Pos (2) /*!< GPIO_T::SMTEN: SMTEN2 Position */
+#define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) /*!< GPIO_T::SMTEN: SMTEN2 Mask */
+
+#define GPIO_SMTEN_SMTEN3_Pos (3) /*!< GPIO_T::SMTEN: SMTEN3 Position */
+#define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) /*!< GPIO_T::SMTEN: SMTEN3 Mask */
+
+#define GPIO_SMTEN_SMTEN4_Pos (4) /*!< GPIO_T::SMTEN: SMTEN4 Position */
+#define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) /*!< GPIO_T::SMTEN: SMTEN4 Mask */
+
+#define GPIO_SMTEN_SMTEN5_Pos (5) /*!< GPIO_T::SMTEN: SMTEN5 Position */
+#define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) /*!< GPIO_T::SMTEN: SMTEN5 Mask */
+
+#define GPIO_SMTEN_SMTEN6_Pos (6) /*!< GPIO_T::SMTEN: SMTEN6 Position */
+#define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) /*!< GPIO_T::SMTEN: SMTEN6 Mask */
+
+#define GPIO_SMTEN_SMTEN7_Pos (7) /*!< GPIO_T::SMTEN: SMTEN7 Position */
+#define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) /*!< GPIO_T::SMTEN: SMTEN7 Mask */
+
+#define GPIO_SMTEN_SMTEN8_Pos (8) /*!< GPIO_T::SMTEN: SMTEN8 Position */
+#define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) /*!< GPIO_T::SMTEN: SMTEN8 Mask */
+
+#define GPIO_SMTEN_SMTEN9_Pos (9) /*!< GPIO_T::SMTEN: SMTEN9 Position */
+#define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) /*!< GPIO_T::SMTEN: SMTEN9 Mask */
+
+#define GPIO_SMTEN_SMTEN10_Pos (10) /*!< GPIO_T::SMTEN: SMTEN10 Position */
+#define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) /*!< GPIO_T::SMTEN: SMTEN10 Mask */
+
+#define GPIO_SMTEN_SMTEN11_Pos (11) /*!< GPIO_T::SMTEN: SMTEN11 Position */
+#define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) /*!< GPIO_T::SMTEN: SMTEN11 Mask */
+
+#define GPIO_SMTEN_SMTEN12_Pos (12) /*!< GPIO_T::SMTEN: SMTEN12 Position */
+#define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) /*!< GPIO_T::SMTEN: SMTEN12 Mask */
+
+#define GPIO_SMTEN_SMTEN13_Pos (13) /*!< GPIO_T::SMTEN: SMTEN13 Position */
+#define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) /*!< GPIO_T::SMTEN: SMTEN13 Mask */
+
+#define GPIO_SMTEN_SMTEN14_Pos (14) /*!< GPIO_T::SMTEN: SMTEN14 Position */
+#define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) /*!< GPIO_T::SMTEN: SMTEN14 Mask */
+
+#define GPIO_SMTEN_SMTEN15_Pos (15) /*!< GPIO_T::SMTEN: SMTEN15 Position */
+#define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) /*!< GPIO_T::SMTEN: SMTEN15 Mask */
+
+#define GPIO_SLEWCTL_HSREN0_Pos (0) /*!< GPIO_T::SLEWCTL: HSREN0 Position */
+#define GPIO_SLEWCTL_HSREN0_Msk (0x3ul << GPIO_SLEWCTL_HSREN0_Pos) /*!< GPIO_T::SLEWCTL: HSREN0 Mask */
+
+#define GPIO_SLEWCTL_HSREN1_Pos (2) /*!< GPIO_T::SLEWCTL: HSREN1 Position */
+#define GPIO_SLEWCTL_HSREN1_Msk (0x3ul << GPIO_SLEWCTL_HSREN1_Pos) /*!< GPIO_T::SLEWCTL: HSREN1 Mask */
+
+#define GPIO_SLEWCTL_HSREN2_Pos (4) /*!< GPIO_T::SLEWCTL: HSREN2 Position */
+#define GPIO_SLEWCTL_HSREN2_Msk (0x3ul << GPIO_SLEWCTL_HSREN2_Pos) /*!< GPIO_T::SLEWCTL: HSREN2 Mask */
+
+#define GPIO_SLEWCTL_HSREN3_Pos (6) /*!< GPIO_T::SLEWCTL: HSREN3 Position */
+#define GPIO_SLEWCTL_HSREN3_Msk (0x3ul << GPIO_SLEWCTL_HSREN3_Pos) /*!< GPIO_T::SLEWCTL: HSREN3 Mask */
+
+#define GPIO_SLEWCTL_HSREN4_Pos (8) /*!< GPIO_T::SLEWCTL: HSREN4 Position */
+#define GPIO_SLEWCTL_HSREN4_Msk (0x3ul << GPIO_SLEWCTL_HSREN4_Pos) /*!< GPIO_T::SLEWCTL: HSREN4 Mask */
+
+#define GPIO_SLEWCTL_HSREN5_Pos (10) /*!< GPIO_T::SLEWCTL: HSREN5 Position */
+#define GPIO_SLEWCTL_HSREN5_Msk (0x3ul << GPIO_SLEWCTL_HSREN5_Pos) /*!< GPIO_T::SLEWCTL: HSREN5 Mask */
+
+#define GPIO_SLEWCTL_HSREN6_Pos (12) /*!< GPIO_T::SLEWCTL: HSREN6 Position */
+#define GPIO_SLEWCTL_HSREN6_Msk (0x3ul << GPIO_SLEWCTL_HSREN6_Pos) /*!< GPIO_T::SLEWCTL: HSREN6 Mask */
+
+#define GPIO_SLEWCTL_HSREN7_Pos (14) /*!< GPIO_T::SLEWCTL: HSREN7 Position */
+#define GPIO_SLEWCTL_HSREN7_Msk (0x3ul << GPIO_SLEWCTL_HSREN7_Pos) /*!< GPIO_T::SLEWCTL: HSREN7 Mask */
+
+#define GPIO_SLEWCTL_HSREN8_Pos (16) /*!< GPIO_T::SLEWCTL: HSREN8 Position */
+#define GPIO_SLEWCTL_HSREN8_Msk (0x3ul << GPIO_SLEWCTL_HSREN8_Pos) /*!< GPIO_T::SLEWCTL: HSREN8 Mask */
+
+#define GPIO_SLEWCTL_HSREN9_Pos (18) /*!< GPIO_T::SLEWCTL: HSREN9 Position */
+#define GPIO_SLEWCTL_HSREN9_Msk (0x3ul << GPIO_SLEWCTL_HSREN9_Pos) /*!< GPIO_T::SLEWCTL: HSREN9 Mask */
+
+#define GPIO_SLEWCTL_HSREN10_Pos (20) /*!< GPIO_T::SLEWCTL: HSREN10 Position */
+#define GPIO_SLEWCTL_HSREN10_Msk (0x3ul << GPIO_SLEWCTL_HSREN10_Pos) /*!< GPIO_T::SLEWCTL: HSREN10 Mask */
+
+#define GPIO_SLEWCTL_HSREN11_Pos (22) /*!< GPIO_T::SLEWCTL: HSREN11 Position */
+#define GPIO_SLEWCTL_HSREN11_Msk (0x3ul << GPIO_SLEWCTL_HSREN11_Pos) /*!< GPIO_T::SLEWCTL: HSREN11 Mask */
+
+#define GPIO_SLEWCTL_HSREN12_Pos (24) /*!< GPIO_T::SLEWCTL: HSREN12 Position */
+#define GPIO_SLEWCTL_HSREN12_Msk (0x3ul << GPIO_SLEWCTL_HSREN12_Pos) /*!< GPIO_T::SLEWCTL: HSREN12 Mask */
+
+#define GPIO_SLEWCTL_HSREN13_Pos (26) /*!< GPIO_T::SLEWCTL: HSREN13 Position */
+#define GPIO_SLEWCTL_HSREN13_Msk (0x3ul << GPIO_SLEWCTL_HSREN13_Pos) /*!< GPIO_T::SLEWCTL: HSREN13 Mask */
+
+#define GPIO_SLEWCTL_HSREN14_Pos (28) /*!< GPIO_T::SLEWCTL: HSREN14 Position */
+#define GPIO_SLEWCTL_HSREN14_Msk (0x3ul << GPIO_SLEWCTL_HSREN14_Pos) /*!< GPIO_T::SLEWCTL: HSREN14 Mask */
+
+#define GPIO_SLEWCTL_HSREN15_Pos (30) /*!< GPIO_T::SLEWCTL: HSREN15 Position */
+#define GPIO_SLEWCTL_HSREN15_Msk (0x3ul << GPIO_SLEWCTL_HSREN15_Pos) /*!< GPIO_T::SLEWCTL: HSREN15 Mask */
+
+#define GPIO_PUSEL_PUSEL0_Pos (0) /*!< GPIO_T::PUSEL: PUSEL0 Position */
+#define GPIO_PUSEL_PUSEL0_Msk (0x3ul << GPIO_PUSEL_PUSEL0_Pos) /*!< GPIO_T::PUSEL: PUSEL0 Mask */
+
+#define GPIO_PUSEL_PUSEL1_Pos (2) /*!< GPIO_T::PUSEL: PUSEL1 Position */
+#define GPIO_PUSEL_PUSEL1_Msk (0x3ul << GPIO_PUSEL_PUSEL1_Pos) /*!< GPIO_T::PUSEL: PUSEL1 Mask */
+
+#define GPIO_PUSEL_PUSEL2_Pos (4) /*!< GPIO_T::PUSEL: PUSEL2 Position */
+#define GPIO_PUSEL_PUSEL2_Msk (0x3ul << GPIO_PUSEL_PUSEL2_Pos) /*!< GPIO_T::PUSEL: PUSEL2 Mask */
+
+#define GPIO_PUSEL_PUSEL3_Pos (6) /*!< GPIO_T::PUSEL: PUSEL3 Position */
+#define GPIO_PUSEL_PUSEL3_Msk (0x3ul << GPIO_PUSEL_PUSEL3_Pos) /*!< GPIO_T::PUSEL: PUSEL3 Mask */
+
+#define GPIO_PUSEL_PUSEL4_Pos (8) /*!< GPIO_T::PUSEL: PUSEL4 Position */
+#define GPIO_PUSEL_PUSEL4_Msk (0x3ul << GPIO_PUSEL_PUSEL4_Pos) /*!< GPIO_T::PUSEL: PUSEL4 Mask */
+
+#define GPIO_PUSEL_PUSEL5_Pos (10) /*!< GPIO_T::PUSEL: PUSEL5 Position */
+#define GPIO_PUSEL_PUSEL5_Msk (0x3ul << GPIO_PUSEL_PUSEL5_Pos) /*!< GPIO_T::PUSEL: PUSEL5 Mask */
+
+#define GPIO_PUSEL_PUSEL6_Pos (12) /*!< GPIO_T::PUSEL: PUSEL6 Position */
+#define GPIO_PUSEL_PUSEL6_Msk (0x3ul << GPIO_PUSEL_PUSEL6_Pos) /*!< GPIO_T::PUSEL: PUSEL6 Mask */
+
+#define GPIO_PUSEL_PUSEL7_Pos (14) /*!< GPIO_T::PUSEL: PUSEL7 Position */
+#define GPIO_PUSEL_PUSEL7_Msk (0x3ul << GPIO_PUSEL_PUSEL7_Pos) /*!< GPIO_T::PUSEL: PUSEL7 Mask */
+
+#define GPIO_PUSEL_PUSEL8_Pos (16) /*!< GPIO_T::PUSEL: PUSEL8 Position */
+#define GPIO_PUSEL_PUSEL8_Msk (0x3ul << GPIO_PUSEL_PUSEL8_Pos) /*!< GPIO_T::PUSEL: PUSEL8 Mask */
+
+#define GPIO_PUSEL_PUSEL9_Pos (18) /*!< GPIO_T::PUSEL: PUSEL9 Position */
+#define GPIO_PUSEL_PUSEL9_Msk (0x3ul << GPIO_PUSEL_PUSEL9_Pos) /*!< GPIO_T::PUSEL: PUSEL9 Mask */
+
+#define GPIO_PUSEL_PUSEL10_Pos (20) /*!< GPIO_T::PUSEL: PUSEL10 Position */
+#define GPIO_PUSEL_PUSEL10_Msk (0x3ul << GPIO_PUSEL_PUSEL10_Pos) /*!< GPIO_T::PUSEL: PUSEL10 Mask */
+
+#define GPIO_PUSEL_PUSEL11_Pos (22) /*!< GPIO_T::PUSEL: PUSEL11 Position */
+#define GPIO_PUSEL_PUSEL11_Msk (0x3ul << GPIO_PUSEL_PUSEL11_Pos) /*!< GPIO_T::PUSEL: PUSEL11 Mask */
+
+#define GPIO_PUSEL_PUSEL12_Pos (24) /*!< GPIO_T::PUSEL: PUSEL12 Position */
+#define GPIO_PUSEL_PUSEL12_Msk (0x3ul << GPIO_PUSEL_PUSEL12_Pos) /*!< GPIO_T::PUSEL: PUSEL12 Mask */
+
+#define GPIO_PUSEL_PUSEL13_Pos (26) /*!< GPIO_T::PUSEL: PUSEL13 Position */
+#define GPIO_PUSEL_PUSEL13_Msk (0x3ul << GPIO_PUSEL_PUSEL13_Pos) /*!< GPIO_T::PUSEL: PUSEL13 Mask */
+
+#define GPIO_PUSEL_PUSEL14_Pos (28) /*!< GPIO_T::PUSEL: PUSEL14 Position */
+#define GPIO_PUSEL_PUSEL14_Msk (0x3ul << GPIO_PUSEL_PUSEL14_Pos) /*!< GPIO_T::PUSEL: PUSEL14 Mask */
+
+#define GPIO_PUSEL_PUSEL15_Pos (30) /*!< GPIO_T::PUSEL: PUSEL15 Position */
+#define GPIO_PUSEL_PUSEL15_Msk (0x3ul << GPIO_PUSEL_PUSEL15_Pos) /*!< GPIO_T::PUSEL: PUSEL15 Mask */
+
+#define GPIO_DBCTL_DBCLKSEL_Pos (0) /*!< GPIO_T::DBCTL: DBCLKSEL Position */
+#define GPIO_DBCTL_DBCLKSEL_Msk (0xFul << GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_T::DBCTL: DBCLKSEL Mask */
+
+#define GPIO_DBCTL_DBCLKSRC_Pos (4) /*!< GPIO_T::DBCTL: DBCLKSRC Position */
+#define GPIO_DBCTL_DBCLKSRC_Msk (1ul << GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO_T::DBCTL: DBCLKSRC Mask */
+
+#define GPIO_DBCTL_ICLKON_Pos (5) /*!< GPIO_T::DBCTL: ICLKON Position */
+#define GPIO_DBCTL_ICLKON_Msk (1ul << GPIO_DBCTL_ICLKON_Pos) /*!< GPIO_T::DBCTL: ICLKON Mask */
+
+/**@}*/ /* GPIO_CONST */
+/**@}*/ /* end of GPIO register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __GPIO_REG_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Include/m480_hsusbd_reg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Include/m480_hsusbd_reg.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1398 @@
+/**************************************************************************//**
+ * @file hsusbd_reg.h
+ * @version V1.00
+ * @brief HSUSBD register definition header file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/
+#ifndef __HSUSBD_REG_H__
+#define __HSUSBD_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup HSUSBD USB 2.0 Device Controller(HSUSBD)
+ Memory Mapped Structure for HSUSBD Controller
+@{ */
+
+typedef struct {
+
+ /**
+ * @var HSUSBD_EP_T::EPDAT
+ * Offset: 0x00 Endpoint n Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |EPDAT |Endpoint A~L Data Register
+ * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
+ * | | |Note: Only word access is supported.
+ * @var HSUSBD_EP_T::EPDAT_BYTE
+ * Offset: 0x00 Endpoint n Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |EPDAT |Endpoint A~L Data Register
+ * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
+ * | | |Note: Only byte access is supported.
+ * @var HSUSBD_EP_T::EPINTSTS
+ * Offset: 0x04 Endpoint n Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BUFFULLIF |Buffer Full
+ * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write)
+ * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
+ * | | |0 = The endpoint packet buffer is not full.
+ * | | |1 = The endpoint packet buffer is full.
+ * | | |Note: This bit is read-only.
+ * |[1] |BUFEMPTYIF|Buffer Empty
+ * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
+ * | | |0 = The endpoint buffer is not empty.
+ * | | |1 = The endpoint buffer is empty.
+ * | | |For an OUT endpoint:
+ * | | |0 = The currently selected buffer has not a count of 0.
+ * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
+ * | | |Note: This bit is read-only.
+ * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
+ * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
+ * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[3] |TXPKIF |Data Packet Transmitted Interrupt
+ * | | |0 = Not a data packet is transmitted from the endpoint to the host.
+ * | | |1 = A data packet is transmitted from the endpoint to the host.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[4] |RXPKIF |Data Packet Received Interrupt
+ * | | |0 = No data packet is received from the host by the endpoint.
+ * | | |1 = A data packet is received from the host by the endpoint.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[5] |OUTTKIF |Data OUT Token Interrupt
+ * | | |0 = A Data OUT token has not been received from the host.
+ * | | |1 = A Data OUT token has been received from the host
+ * | | |This bit also set by PING token (in high-speed only).
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[6] |INTKIF |Data IN Token Interrupt
+ * | | |0 = Not Data IN token has been received from the host.
+ * | | |1 = A Data IN token has been received from the host.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[7] |PINGIF |PING Token Interrupt
+ * | | |0 = A Data PING token has not been received from the host.
+ * | | |1 = A Data PING token has been received from the host.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[8] |NAKIF |USB NAK Sent
+ * | | |0 = The last USB IN packet could be provided, and was acknowledged with an ACK.
+ * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[9] |STALLIF |USB STALL Sent
+ * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
+ * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[10] |NYETIF |NYET Sent
+ * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
+ * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[11] |ERRIF |ERR Sent
+ * | | |0 = No any error in the transaction.
+ * | | |1 = There occurs any error in the transaction.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[12] |SHORTRXIF |Bulk Out Short Packet Received
+ * | | |0 = No bulk out short packet is received.
+ * | | |1 = Received bulk out short packet (including zero length packet).
+ * | | |Note: Write 1 to clear this bit to 0.
+ * @var HSUSBD_EP_T::EPINTEN
+ * Offset: 0x08 Endpoint n Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BUFFULLIEN|Buffer Full Interrupt
+ * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
+ * | | |0 = Buffer full interrupt Disabled.
+ * | | |1 = Buffer full interrupt Enabled.
+ * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
+ * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
+ * | | |0 = Buffer empty interrupt Disabled.
+ * | | |1 = Buffer empty interrupt Enabled.
+ * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
+ * | | |0 = Short data packet interrupt Disabled.
+ * | | |1 = Short data packet interrupt Enabled.
+ * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
+ * | | |0 = Data packet has been received from the host interrupt Disabled.
+ * | | |1 = Data packet has been received from the host interrupt Enabled.
+ * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
+ * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
+ * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
+ * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
+ * | | |0 = Data OUT token interrupt Disabled.
+ * | | |1 = Data OUT token interrupt Enabled.
+ * |[6] |INTKIEN |Data IN Token Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
+ * | | |0 = Data IN token interrupt Disabled.
+ * | | |1 = Data IN token interrupt Enabled.
+ * |[7] |PINGIEN |PING Token Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
+ * | | |0 = PING token interrupt Disabled.
+ * | | |1 = PING token interrupt Enabled.
+ * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
+ * | | |0 = NAK token interrupt Disabled.
+ * | | |1 = NAK token interrupt Enabled.
+ * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
+ * | | |0 = STALL token interrupt Disabled.
+ * | | |1 = STALL token interrupt Enabled.
+ * |[10] |NYETIEN |NYET Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
+ * | | |0 = NYET condition interrupt Disabled.
+ * | | |1 = NYET condition interrupt Enabled.
+ * |[11] |ERRIEN |ERR Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
+ * | | |0 = Error event interrupt Disabled.
+ * | | |1 = Error event interrupt Enabled.
+ * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
+ * | | |0 = Bulk out interrupt Disabled.
+ * | | |1 = Bulk out interrupt Enabled.
+ * @var HSUSBD_EP_T::EPDATCNT
+ * Offset: 0x0C Endpoint n Data Available Count Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |DATCNT |Data Count
+ * | | |For an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.), this register returns the number of valid bytes in the IN endpoint packet buffer.
+ * | | |For an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.), this register returns the number of received valid bytes in the Host OUT transfer.
+ * |[30:16] |DMALOOP |DMA Loop
+ * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
+ * @var HSUSBD_EP_T::EPRSPCTL
+ * Offset: 0x10 Endpoint n Response Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |FLUSH |Buffer Flush
+ * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared
+ * | | |This bit is self-clearing
+ * | | |This bit should always be written after an configuration event.
+ * | | |0 = The packet buffer is not flushed.
+ * | | |1 = The packet buffer is flushed by user.
+ * |[2:1] |MODE |Mode Control
+ * | | |The two bits decide the operation mode of the in-endpoint.
+ * | | |00: Auto-Validate Mode
+ * | | |01: Manual-Validate Mode
+ * | | |10: Fly Mode
+ * | | |11: Reserved
+ * | | |These bits are not valid for an out-endpoint
+ * | | |The auto validate mode will be activated when the reserved mode is selected
+ * |[3] |TOGGLE |Endpoint Toggle
+ * | | |This bit is used to clear the endpoint data toggle bit
+ * | | |Reading this bit returns the current state of the endpoint data toggle bit.
+ * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host
+ * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
+ * | | |0 = Not clear the endpoint data toggle bit.
+ * | | |1 = Clear the endpoint data toggle bit.
+ * |[4] |HALT |Endpoint Halt
+ * | | |This bit is used to send a STALL handshake as response to the token from the host
+ * | | |When an Endpoint Set Feature (ep_halt) is detected by the local CPU, it must write a '1' to this bit.
+ * | | |0 = Not send a STALL handshake as response to the token from the host.
+ * | | |1 = Send a STALL handshake as response to the token from the host.
+ * |[5] |ZEROLEN |Zero Length
+ * | | |This bit is used to send a zero-length packet response to an IN-token
+ * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token
+ * | | |This bit gets cleared once the zero length data packet is sent.
+ * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
+ * | | |1 = A zero packet is sent to the host on reception of an IN-token.
+ * |[6] |SHORTTXEN |Short Packet Transfer Enable
+ * | | |This bit is applicable only in case of Auto-Validate Method
+ * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer
+ * | | |This bit gets cleared once the data packet is sent.
+ * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
+ * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
+ * |[7] |DISBUF |Buffer Disable Bit
+ * | | |This bit is used to receive unknown size OUT short packet
+ * | | |The received packet size is reference USBD_EPxDATCNT register.
+ * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
+ * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
+ * @var HSUSBD_EP_T::EPMPS
+ * Offset: 0x14 Endpoint n Maximum Packet Size Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[10:0] |EPMPS |Endpoint Maximum Packet Size
+ * | | |This field determines the Maximum Packet Size of the Endpoint.
+ * @var HSUSBD_EP_T::EPTXCNT
+ * Offset: 0x18 Endpoint n Transfer Count Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[10:0] |TXCNT |Endpoint Transfer Count
+ * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
+ * | | |For OUT endpoints, this field has no effect.
+ * @var HSUSBD_EP_T::EPCFG
+ * Offset: 0x1C Endpoint n Configuration Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |EPEN |Endpoint Valid
+ * | | |When set, this bit enables this endpoint
+ * | | |This bit has no effect on Endpoint 0, which is always enabled.
+ * | | |0 = The endpoint Disabled.
+ * | | |1 = The endpoint Enabled.
+ * |[2:1] |EPTYPE |Endpoint Type
+ * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
+ * | | |00 = Reserved.
+ * | | |01 = Bulk.
+ * | | |10 = Interrupt.
+ * | | |11 = Isochronous.
+ * |[3] |EPDIR |Endpoint Direction
+ * | | |0 = out-endpoint (Host OUT to Device).
+ * | | |1 = in-endpoint (Host IN to Device).
+ * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
+ * |[7:4] |EPNUM |Endpoint Number
+ * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
+ * | | |Note: Do not support two endpoints have same endpoint number.
+ * @var HSUSBD_EP_T::EPBUFST
+ * Offset: 0x20 Endpoint n RAM Start Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |SADDR |Endpoint Start Address
+ * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
+ * @var HSUSBD_EP_T::EPBUFEND
+ * Offset: 0x24 Endpoint n RAM End Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |EADDR |Endpoint End Address
+ * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
+ */
+
+ union {
+ __IO uint32_t EPDAT;
+ __IO uint8_t EPDAT_BYTE;
+
+ }; /*!< [0x0000] Endpoint n Data Register */
+
+ __IO uint32_t EPINTSTS; /*!< [0x0004] Endpoint n Interrupt Status Register */
+ __IO uint32_t EPINTEN; /*!< [0x0008] Endpoint n Interrupt Enable Register */
+ __I uint32_t EPDATCNT; /*!< [0x000c] Endpoint n Data Available Count Register */
+ __IO uint32_t EPRSPCTL; /*!< [0x0010] Endpoint n Response Control Register */
+ __IO uint32_t EPMPS; /*!< [0x0014] Endpoint n Maximum Packet Size Register */
+ __IO uint32_t EPTXCNT; /*!< [0x0018] Endpoint n Transfer Count Register */
+ __IO uint32_t EPCFG; /*!< [0x001c] Endpoint n Configuration Register */
+ __IO uint32_t EPBUFST; /*!< [0x0020] Endpoint n RAM Start Address Register */
+ __IO uint32_t EPBUFEND; /*!< [0x0024] Endpoint n RAM End Address Register */
+
+} HSUSBD_EP_T;
+
+typedef struct {
+
+ /**
+ * @var HSUSBD_T::GINTSTS
+ * Offset: 0x00 Global Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |USBIF |USB Interrupt
+ * | | |This bit conveys the interrupt status for USB specific events endpoint
+ * | | |When set, USB interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[1] |CEPIF |Control Endpoint Interrupt
+ * | | |This bit conveys the interrupt status for control endpoint
+ * | | |When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[2] |EPAIF |Endpoint a Interrupt
+ * | | |When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[3] |EPBIF |Endpoint B Interrupt
+ * | | |When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[4] |EPCIF |Endpoint C Interrupt
+ * | | |When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[5] |EPDIF |Endpoint D Interrupt
+ * | | |When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[6] |EPEIF |Endpoint E Interrupt
+ * | | |When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[7] |EPFIF |Endpoint F Interrupt
+ * | | |When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[8] |EPGIF |Endpoint G Interrupt
+ * | | |When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[9] |EPHIF |Endpoint H Interrupt
+ * | | |When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[10] |EPIIF |Endpoint I Interrupt
+ * | | |When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[11] |EPJIF |Endpoint J Interrupt
+ * | | |When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[12] |EPKIF |Endpoint K Interrupt
+ * | | |When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * |[13] |EPLIF |Endpoint L Interrupt
+ * | | |When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt.
+ * | | |0 = No interrupt event occurred.
+ * | | |1 = The related interrupt event is occurred.
+ * @var HSUSBD_T::GINTEN
+ * Offset: 0x08 Global Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |USBIEN |USB Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be generated when a USB event occurs on the bus.
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[1] |CEPIEN |Control Endpoint Interrupt Enable Bit
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the control endpoint.
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[2] |EPAIEN |Interrupt Enable Control for Endpoint a
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint A.
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[3] |EPBIEN |Interrupt Enable Control for Endpoint B
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint B
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[4] |EPCIEN |Interrupt Enable Control for Endpoint C
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint C
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[5] |EPDIEN |Interrupt Enable Control for Endpoint D
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint D
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[6] |EPEIEN |Interrupt Enable Control for Endpoint E
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint E
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[7] |EPFIEN |Interrupt Enable Control for Endpoint F
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint F
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[8] |EPGIEN |Interrupt Enable Control for Endpoint G
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint G
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[9] |EPHIEN |Interrupt Enable Control for Endpoint H
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint H
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[10] |EPIIEN |Interrupt Enable Control for Endpoint I
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint I
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[11] |EPJIEN |Interrupt Enable Control for Endpoint J
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint J
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[12] |EPKIEN |Interrupt Enable Control for Endpoint K
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint K
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * |[13] |EPLIEN |Interrupt Enable Control for Endpoint L
+ * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint L
+ * | | |0 = The related interrupt Disabled.
+ * | | |1 = The related interrupt Enabled.
+ * @var HSUSBD_T::BUSINTSTS
+ * Offset: 0x10 USB Bus Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SOFIF |SOF Receive Control
+ * | | |This bit indicates when a start-of-frame packet has been received.
+ * | | |0 = No start-of-frame packet has been received.
+ * | | |1 = Start-of-frame packet has been received.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[1] |RSTIF |Reset Status
+ * | | |When set, this bit indicates that either the USB root port reset is end.
+ * | | |0 = No USB root port reset is end.
+ * | | |1 = USB root port reset is end.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[2] |RESUMEIF |Resume
+ * | | |When set, this bit indicates that a device resume has occurred.
+ * | | |0 = No device resume has occurred.
+ * | | |1 = Device resume has occurred.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[3] |SUSPENDIF |Suspend Request
+ * | | |This bit is set as default and it has to be cleared by writing '1' before the USB reset
+ * | | |This bit is also set when a USB Suspend request is detected from the host.
+ * | | |0 = No USB Suspend request is detected from the host.
+ * | | |1= USB Suspend request is detected from the host.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[4] |HISPDIF |High-speed Settle
+ * | | |0 = No valid high-speed reset protocol is detected.
+ * | | |1 = Valid high-speed reset protocol is over and the device has settled in high-speed.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[5] |DMADONEIF |DMA Completion Interrupt
+ * | | |0 = No DMA transfer over.
+ * | | |1 = DMA transfer is over.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[6] |PHYCLKVLDIF|Usable Clock Interrupt
+ * | | |0 = Usable clock is not available.
+ * | | |1 = Usable clock is available from the transceiver.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[8] |VBUSDETIF |VBUS Detection Interrupt Status
+ * | | |0 = No VBUS is plug-in.
+ * | | |1 = VBUS is plug-in.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * @var HSUSBD_T::BUSINTEN
+ * Offset: 0x14 USB Bus Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SOFIEN |SOF Interrupt
+ * | | |This bit enables the SOF interrupt.
+ * | | |0 = SOF interrupt Disabled.
+ * | | |1 = SOF interrupt Enabled.
+ * |[1] |RSTIEN |Reset Status
+ * | | |This bit enables the USB-Reset interrupt.
+ * | | |0 = USB-Reset interrupt Disabled.
+ * | | |1 = USB-Reset interrupt Enabled.
+ * |[2] |RESUMEIEN |Resume
+ * | | |This bit enables the Resume interrupt.
+ * | | |0 = Resume interrupt Disabled.
+ * | | |1 = Resume interrupt Enabled.
+ * |[3] |SUSPENDIEN|Suspend Request
+ * | | |This bit enables the Suspend interrupt.
+ * | | |0 = Suspend interrupt Disabled.
+ * | | |1 = Suspend interrupt Enabled.
+ * |[4] |HISPDIEN |High-speed Settle
+ * | | |This bit enables the high-speed settle interrupt.
+ * | | |0 = High-speed settle interrupt Disabled.
+ * | | |1 = High-speed settle interrupt Enabled.
+ * |[5] |DMADONEIEN|DMA Completion Interrupt
+ * | | |This bit enables the DMA completion interrupt
+ * | | |0 = DMA completion interrupt Disabled.
+ * | | |1 = DMA completion interrupt Enabled.
+ * |[6] |PHYCLKVLDIEN|Usable Clock Interrupt
+ * | | |This bit enables the usable clock interrupt.
+ * | | |0 = Usable clock interrupt Disabled.
+ * | | |1 = Usable clock interrupt Enabled.
+ * |[8] |VBUSDETIEN|VBUS Detection Interrupt Enable Bit
+ * | | |This bit enables the VBUS floating detection interrupt.
+ * | | |0 = VBUS floating detection interrupt Disabled.
+ * | | |1 = VBUS floating detection interrupt Enabled.
+ * @var HSUSBD_T::OPER
+ * Offset: 0x18 USB Operational Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RESUMEEN |Generate Resume
+ * | | |0 = No Resume sequence to be initiated to the host.
+ * | | |1 = A Resume sequence to be initiated to the host if device remote wakeup is enabled
+ * | | |This bit is self-clearing.
+ * |[1] |HISPDEN |USB High-speed
+ * | | |0 = The USB device controller to suppress the chirp-sequence during reset protocol, thereby allowing the USB device controller to settle in full-speed, even though it is connected to a USB2.0 Host.
+ * | | |1 = The USB device controller to initiate a chirp-sequence during reset protocol.
+ * |[2] |CURSPD |USB Current Speed
+ * | | |0 = The device has settled in Full Speed.
+ * | | |1 = The USB device controller has settled in High-speed.
+ * @var HSUSBD_T::FRAMECNT
+ * Offset: 0x1C USB Frame Count Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |MFRAMECNT |Micro-frame Counter
+ * | | |This field contains the micro-frame number for the frame number in the frame counter field.
+ * |[13:3] |FRAMECNT |Frame Counter
+ * | | |This field contains the frame count from the most recent start-of-frame packet.
+ * @var HSUSBD_T::FADDR
+ * Offset: 0x20 USB Function Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[6:0] |FADDR |USB Function Address
+ * | | |This field contains the current USB address of the device
+ * | | |This field is cleared when a root port reset is detected
+ * @var HSUSBD_T::TEST
+ * Offset: 0x24 USB Test Mode Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |TESTMODE |Test Mode Selection
+ * | | |000 = Normal Operation.
+ * | | |001 = Test_J.
+ * | | |010 = Test_K.
+ * | | |011 = Test_SE0_NAK.
+ * | | |100 = Test_Packet.
+ * | | |101 = Test_Force_Enable.
+ * | | |110 = Reserved.
+ * | | |111 = Reserved.
+ * | | |Note: This field is cleared when root port reset is detected.
+ * @var HSUSBD_T::CEPDAT
+ * Offset: 0x28 Control-Endpoint Data Buffer
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DAT |Control-endpoint Data Buffer
+ * | | |Control endpoint data buffer for the buffer transaction (read or write).
+ * | | |Note: Only word access is supported.
+ * @var HSUSBD_T::CEPDAT_BYTE
+ * Offset: 0x28 Control-Endpoint Data Buffer
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |DAT |Control-endpoint Data Buffer
+ * | | |Control endpoint data buffer for the buffer transaction (read or write).
+ * | | |Note: Only byte access is supported.
+ * @var HSUSBD_T::CEPCTL
+ * Offset: 0x2C Control-Endpoint Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |NAKCLR |No Acknowledge Control
+ * | | |This bit plays a crucial role in any control transfer.
+ * | | |0 = The bit is being cleared by the local CPU by writing zero, the USB device controller will be responding with NAKs for the subsequent status phase
+ * | | |This mechanism holds the host from moving to the next request, until the local CPU is also ready to process the next request.
+ * | | |1 = This bit is set to one by the USB device controller, whenever a setup token is received
+ * | | |The local CPU can take its own time to finish off any house-keeping work based on the request and then clear this bit.
+ * | | |Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated.
+ * |[1] |STALLEN |Stall Enable Bit
+ * | | |When this stall bit is set, the control endpoint sends a stall handshake in response to any in or out token thereafter
+ * | | |This is typically used for response to invalid/unsupported requests
+ * | | |When this bit is being set the NAK clear bit has to be cleared at the same time since the NAK clear bit has highest priority than STALL
+ * | | |It is automatically cleared on receipt of a next setup-token
+ * | | |So, the local CPU need not write again to clear this bit.
+ * | | |0 = No sends a stall handshake in response to any in or out token thereafter.
+ * | | |1 = The control endpoint sends a stall handshake in response to any in or out token thereafter.
+ * | | |Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated.
+ * |[2] |ZEROLEN |Zero Packet Length
+ * | | |This bit is valid for Auto Validation mode only.
+ * | | |0 = No zero length packet to the host during Data stage to an IN token.
+ * | | |1 = USB device controller can send a zero length packet to the host during Data stage to an IN token
+ * | | |This bit gets cleared once the zero length data packet is sent
+ * | | |So, the local CPU need not write again to clear this bit.
+ * |[3] |FLUSH |CEP-flush Bit
+ * | | |0 = No the packet buffer and its corresponding USBD_CEPDATCNT register to be cleared.
+ * | | |1 = The packet buffer and its corresponding USBD_CEPDATCNT register to be cleared
+ * | | |This bit is self-cleaning.
+ * @var HSUSBD_T::CEPINTEN
+ * Offset: 0x30 Control-Endpoint Interrupt Enable
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SETUPTKIEN|Setup Token Interrupt Enable Bit
+ * | | |0 = The SETUP token interrupt in Control Endpoint Disabled.
+ * | | |1 = The SETUP token interrupt in Control Endpoint Enabled.
+ * |[1] |SETUPPKIEN|Setup Packet Interrupt
+ * | | |0 = The SETUP packet interrupt in Control Endpoint Disabled.
+ * | | |1 = The SETUP packet interrupt in Control Endpoint Enabled.
+ * |[2] |OUTTKIEN |Out Token Interrupt
+ * | | |0 = The OUT token interrupt in Control Endpoint Disabled.
+ * | | |1 = The OUT token interrupt in Control Endpoint Enabled.
+ * |[3] |INTKIEN |In Token Interrupt
+ * | | |0 = The IN token interrupt in Control Endpoint Disabled.
+ * | | |1 = The IN token interrupt in Control Endpoint Enabled.
+ * |[4] |PINGIEN |Ping Token Interrupt
+ * | | |0 = The ping token interrupt in Control Endpoint Disabled.
+ * | | |1 = The ping token interrupt Control Endpoint Enabled.
+ * |[5] |TXPKIEN |Data Packet Transmitted Interrupt
+ * | | |0 = The data packet transmitted interrupt in Control Endpoint Disabled.
+ * | | |1 = The data packet transmitted interrupt in Control Endpoint Enabled.
+ * |[6] |RXPKIEN |Data Packet Received Interrupt
+ * | | |0 = The data received interrupt in Control Endpoint Disabled.
+ * | | |1 = The data received interrupt in Control Endpoint Enabled.
+ * |[7] |NAKIEN |NAK Sent Interrupt
+ * | | |0 = The NAK sent interrupt in Control Endpoint Disabled.
+ * | | |1 = The NAK sent interrupt in Control Endpoint Enabled.
+ * |[8] |STALLIEN |STALL Sent Interrupt
+ * | | |0 = The STALL sent interrupt in Control Endpoint Disabled.
+ * | | |1 = The STALL sent interrupt in Control Endpoint Enabled.
+ * |[9] |ERRIEN |USB Error Interrupt
+ * | | |0 = The USB Error interrupt in Control Endpoint Disabled.
+ * | | |1 = The USB Error interrupt in Control Endpoint Enabled.
+ * |[10] |STSDONEIEN|Status Completion Interrupt
+ * | | |0 = The Status Completion interrupt in Control Endpoint Disabled.
+ * | | |1 = The Status Completion interrupt in Control Endpoint Enabled.
+ * |[11] |BUFFULLIEN|Buffer Full Interrupt
+ * | | |0 = The buffer full interrupt in Control Endpoint Disabled.
+ * | | |1 = The buffer full interrupt in Control Endpoint Enabled.
+ * |[12] |BUFEMPTYIEN|Buffer Empty Interrupt
+ * | | |0 = The buffer empty interrupt in Control Endpoint Disabled.
+ * | | |1= The buffer empty interrupt in Control Endpoint Enabled.
+ * @var HSUSBD_T::CEPINTSTS
+ * Offset: 0x34 Control-Endpoint Interrupt Status
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SETUPTKIF |Setup Token Interrupt
+ * | | |0 = Not a Setup token is received.
+ * | | |1 = A Setup token is received. Writing 1 clears this status bit
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[1] |SETUPPKIF |Setup Packet Interrupt
+ * | | |This bit must be cleared (by writing 1) before the next setup packet can be received
+ * | | |If the bit is not cleared, then the successive setup packets will be overwritten in the setup packet buffer.
+ * | | |0 = Not a Setup packet has been received from the host.
+ * | | |1 = A Setup packet has been received from the host.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[2] |OUTTKIF |Out Token Interrupt
+ * | | |0 = The control-endpoint does not received an OUT token from the host.
+ * | | |1 = The control-endpoint receives an OUT token from the host.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[3] |INTKIF |in Token Interrupt
+ * | | |0 = The control-endpoint does not received an IN token from the host.
+ * | | |1 = The control-endpoint receives an IN token from the host.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[4] |PINGIF |Ping Token Interrupt
+ * | | |0 = The control-endpoint does not received a ping token from the host.
+ * | | |1 = The control-endpoint receives a ping token from the host.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[5] |TXPKIF |Data Packet Transmitted Interrupt
+ * | | |0 = Not a data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same.
+ * | | |1 = A data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[6] |RXPKIF |Data Packet Received Interrupt
+ * | | |0 = Not a data packet is successfully received from the host for an OUT-token and an ACK is sent to the host.
+ * | | |1 = A data packet is successfully received from the host for an OUT-token and an ACK is sent to the host.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[7] |NAKIF |NAK Sent Interrupt
+ * | | |0 = Not a NAK-token is sent in response to an IN/OUT token.
+ * | | |1 = A NAK-token is sent in response to an IN/OUT token.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[8] |STALLIF |STALL Sent Interrupt
+ * | | |0 = Not a stall-token is sent in response to an IN/OUT token.
+ * | | |1 = A stall-token is sent in response to an IN/OUT token.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[9] |ERRIF |USB Error Interrupt
+ * | | |0 = No error had occurred during the transaction.
+ * | | |1 = An error had occurred during the transaction.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[10] |STSDONEIF |Status Completion Interrupt
+ * | | |0 = Not a USB transaction has completed successfully.
+ * | | |1 = The status stage of a USB transaction has completed successfully.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[11] |BUFFULLIF |Buffer Full Interrupt
+ * | | |0 = The control-endpoint buffer is not full.
+ * | | |1 = The control-endpoint buffer is full.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[12] |BUFEMPTYIF|Buffer Empty Interrupt
+ * | | |0 = The control-endpoint buffer is not empty.
+ * | | |1 = The control-endpoint buffer is empty.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * @var HSUSBD_T::CEPTXCNT
+ * Offset: 0x38 Control-Endpoint In-transfer Data Count
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |TXCNT |In-transfer Data Count
+ * | | |There is no mode selection for the control endpoint (but it operates like manual mode).The local-CPU has to fill the control-endpoint buffer with the data to be sent for an in-token and to write the count of bytes in this register
+ * | | |When zero is written into this field, a zero length packet is sent to the host
+ * | | |When the count written in the register is more than the MPS, the data sent will be of only MPS.
+ * @var HSUSBD_T::CEPRXCNT
+ * Offset: 0x3C Control-Endpoint Out-transfer Data Count
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |RXCNT |Out-transfer Data Count
+ * | | |The USB device controller maintains the count of the data received in case of an out transfer, during the control transfer.
+ * @var HSUSBD_T::CEPDATCNT
+ * Offset: 0x40 Control-Endpoint data count
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |DATCNT |Control-endpoint Data Count
+ * | | |The USB device controller maintains the count of the data of control-endpoint.
+ * @var HSUSBD_T::SETUP1_0
+ * Offset: 0x44 Setup1 & Setup0 bytes
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |SETUP0 |Setup Byte 0[7:0]
+ * | | |This register provides byte 0 of the last setup packet received
+ * | | |For a Standard Device Request, the following bmRequestType information is returned.
+ * | | |Bit 7(Direction):
+ * | | | 0: Host to device
+ * | | | 1: Device to host
+ * | | |Bit 6-5 (Type):
+ * | | | 00: Standard
+ * | | | 01: Class
+ * | | | 10: Vendor
+ * | | | 11: Reserved
+ * | | |Bit 4-0 (Recipient)
+ * | | | 00000: Device
+ * | | | 00001: Interface
+ * | | | 00010: Endpoint
+ * | | | 00011: Other
+ * | | | Others: Reserved
+ * |[15:8] |SETUP1 |Setup Byte 1[15:8]
+ * | | |This register provides byte 1 of the last setup packet received
+ * | | |For a Standard Device Request, the following bRequest Code information is returned.
+ * | | |00000000 = Get Status.
+ * | | |00000001 = Clear Feature.
+ * | | |00000010 = Reserved.
+ * | | |00000011 = Set Feature.
+ * | | |00000100 = Reserved.
+ * | | |00000101 = Set Address.
+ * | | |00000110 = Get Descriptor.
+ * | | |00000111 = Set Descriptor.
+ * | | |00001000 = Get Configuration.
+ * | | |00001001 = Set Configuration.
+ * | | |00001010 = Get Interface.
+ * | | |00001011 = Set Interface.
+ * | | |00001100 = Sync Frame.
+ * @var HSUSBD_T::SETUP3_2
+ * Offset: 0x48 Setup3 & Setup2 Bytes
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |SETUP2 |Setup Byte 2 [7:0]
+ * | | |This register provides byte 2 of the last setup packet received
+ * | | |For a Standard Device Request, the least significant byte of the wValue field is returned
+ * |[15:8] |SETUP3 |Setup Byte 3 [15:8]
+ * | | |This register provides byte 3 of the last setup packet received
+ * | | |For a Standard Device Request, the most significant byte of the wValue field is returned.
+ * @var HSUSBD_T::SETUP5_4
+ * Offset: 0x4C Setup5 & Setup4 Bytes
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |SETUP4 |Setup Byte 4[7:0]
+ * | | |This register provides byte 4 of the last setup packet received
+ * | | |For a Standard Device Request, the least significant byte of the wIndex is returned.
+ * |[15:8] |SETUP5 |Setup Byte 5[15:8]
+ * | | |This register provides byte 5 of the last setup packet received
+ * | | |For a Standard Device Request, the most significant byte of the wIndex field is returned.
+ * @var HSUSBD_T::SETUP7_6
+ * Offset: 0x50 Setup7 & Setup6 Bytes
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |SETUP6 |Setup Byte 6[7:0]
+ * | | |This register provides byte 6 of the last setup packet received
+ * | | |For a Standard Device Request, the least significant byte of the wLength field is returned.
+ * |[15:8] |SETUP7 |Setup Byte 7[15:8]
+ * | | |This register provides byte 7 of the last setup packet received
+ * | | |For a Standard Device Request, the most significant byte of the wLength field is returned.
+ * @var HSUSBD_T::CEPBUFST
+ * Offset: 0x54 Control Endpoint RAM Start Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |SADDR |Control-endpoint Start Address
+ * | | |This is the start-address of the RAM space allocated for the control-endpoint.
+ * @var HSUSBD_T::CEPBUFEND
+ * Offset: 0x58 Control Endpoint RAM End Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |EADDR |Control-endpoint End Address
+ * | | |This is the end-address of the RAM space allocated for the control-endpoint.
+ * @var HSUSBD_T::DMACTL
+ * Offset: 0x5C DMA Control Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |EPNUM |DMA Endpoint Address Bits
+ * | | |Used to define the Endpoint Address
+ * |[4] |DMARD |DMA Operation
+ * | | |0 : The operation is a DMA write (read from USB buffer)
+ * | | |DMA will check endpoint data available count (USBD_EPxDATCNT) according to EPNM setting before to perform DMA write operation.
+ * | | |1 : The operation is a DMA read (write to USB buffer).
+ * |[5] |DMAEN |DMA Enable Bit
+ * | | |0 : DMA function Disabled.
+ * | | |1 : DMA function Enabled.
+ * |[6] |SGEN |Scatter Gather Function Enable Bit
+ * | | |0 : Scatter gather function Disabled.
+ * | | |1 : Scatter gather function Enabled.
+ * |[7] |DMARST |Reset DMA State Machine
+ * | | |0 : No reset the DMA state machine.
+ * | | |1 : Reset the DMA state machine.
+ * |[8] |SVINEP |Serve IN Endpoint
+ * | | |This bit is used to specify DMA serving endpoint-IN endpoint or OUT endpoint.
+ * | | |0: DMA serves OUT endpoint
+ * | | |1: DMA serves IN endpoint
+ * @var HSUSBD_T::DMACNT
+ * Offset: 0x60 DMA Count Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[19:0] |DMACNT |DMA Transfer Count
+ * | | |The transfer count of the DMA operation to be performed is written to this register.
+ * @var HSUSBD_T::DMAADDR
+ * Offset: 0x700 AHB DMA Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DMAADDR |DMAADDR
+ * | | |The register specifies the address from which the DMA has to read / write
+ * | | |The address must WORD (32-bit) aligned.
+ * @var HSUSBD_T::PHYCTL
+ * Offset: 0x704 USB PHY Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8] |DPPUEN |DP Pull-up
+ * | | |0 = Pull-up resistor on D+ Disabled.
+ * | | |1 = Pull-up resistor on D+ Enabled.
+ * |[9] |PHYEN |PHY Suspend Enable Bit
+ * | | |0 = The USB PHY is suspend.
+ * | | |1 = The USB PHY is not suspend.
+ * |[24] |WKEN |Wake-up Enable Bit
+ * | | |0 = The wake-up function Disabled.
+ * | | |1 = The wake-up function Enabled.
+ * |[31] |VBUSDET |VBUS Status
+ * | | |0 = The VBUS is not detected yet.
+ * | | |1 = The VBUS is detected.
+ */
+
+ __I uint32_t GINTSTS; /*!< [0x0000] Global Interrupt Status Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t GINTEN; /*!< [0x0008] Global Interrupt Enable Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE1[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t BUSINTSTS; /*!< [0x0010] USB Bus Interrupt Status Register */
+ __IO uint32_t BUSINTEN; /*!< [0x0014] USB Bus Interrupt Enable Register */
+ __IO uint32_t OPER; /*!< [0x0018] USB Operational Register */
+ __I uint32_t FRAMECNT; /*!< [0x001c] USB Frame Count Register */
+ __IO uint32_t FADDR; /*!< [0x0020] USB Function Address Register */
+ __IO uint32_t TEST; /*!< [0x0024] USB Test Mode Register */
+
+ union {
+ __IO uint32_t CEPDAT;
+ __IO uint8_t CEPDAT_BYTE;
+
+ }; /*!< [0x0028] Control-Endpoint Data Buffer */
+
+ __IO uint32_t CEPCTL; /*!< [0x002c] Control-Endpoint Control Register */
+ __IO uint32_t CEPINTEN; /*!< [0x0030] Control-Endpoint Interrupt Enable */
+ __IO uint32_t CEPINTSTS; /*!< [0x0034] Control-Endpoint Interrupt Status */
+ __IO uint32_t CEPTXCNT; /*!< [0x0038] Control-Endpoint In-transfer Data Count */
+ __I uint32_t CEPRXCNT; /*!< [0x003c] Control-Endpoint Out-transfer Data Count */
+ __I uint32_t CEPDATCNT; /*!< [0x0040] Control-Endpoint data count */
+ __I uint32_t SETUP1_0; /*!< [0x0044] Setup1 & Setup0 bytes */
+ __I uint32_t SETUP3_2; /*!< [0x0048] Setup3 & Setup2 Bytes */
+ __I uint32_t SETUP5_4; /*!< [0x004c] Setup5 & Setup4 Bytes */
+ __I uint32_t SETUP7_6; /*!< [0x0050] Setup7 & Setup6 Bytes */
+ __IO uint32_t CEPBUFST; /*!< [0x0054] Control Endpoint RAM Start Address Register */
+ __IO uint32_t CEPBUFEND; /*!< [0x0058] Control Endpoint RAM End Address Register */
+ __IO uint32_t DMACTL; /*!< [0x005c] DMA Control Status Register */
+ __IO uint32_t DMACNT; /*!< [0x0060] DMA Count Register */
+
+ HSUSBD_EP_T EP[12];
+
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE2[303];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t DMAADDR; /*!< [0x0700] AHB DMA Address Register */
+ __IO uint32_t PHYCTL; /*!< [0x0704] USB PHY Control Register */
+
+} HSUSBD_T;
+
+/**
+ @addtogroup HSUSBD_CONST HSUSBD Bit Field Definition
+ Constant Definitions for HSUSBD Controller
+@{ */
+
+#define HSUSBD_GINTSTS_USBIF_Pos (0) /*!< HSUSBD_T::GINTSTS: USBIF Position */
+#define HSUSBD_GINTSTS_USBIF_Msk (0x1ul << HSUSBD_GINTSTS_USBIF_Pos) /*!< HSUSBD_T::GINTSTS: USBIF Mask */
+
+#define HSUSBD_GINTSTS_CEPIF_Pos (1) /*!< HSUSBD_T::GINTSTS: CEPIF Position */
+#define HSUSBD_GINTSTS_CEPIF_Msk (0x1ul << HSUSBD_GINTSTS_CEPIF_Pos) /*!< HSUSBD_T::GINTSTS: CEPIF Mask */
+
+#define HSUSBD_GINTSTS_EPAIF_Pos (2) /*!< HSUSBD_T::GINTSTS: EPAIF Position */
+#define HSUSBD_GINTSTS_EPAIF_Msk (0x1ul << HSUSBD_GINTSTS_EPAIF_Pos) /*!< HSUSBD_T::GINTSTS: EPAIF Mask */
+
+#define HSUSBD_GINTSTS_EPBIF_Pos (3) /*!< HSUSBD_T::GINTSTS: EPBIF Position */
+#define HSUSBD_GINTSTS_EPBIF_Msk (0x1ul << HSUSBD_GINTSTS_EPBIF_Pos) /*!< HSUSBD_T::GINTSTS: EPBIF Mask */
+
+#define HSUSBD_GINTSTS_EPCIF_Pos (4) /*!< HSUSBD_T::GINTSTS: EPCIF Position */
+#define HSUSBD_GINTSTS_EPCIF_Msk (0x1ul << HSUSBD_GINTSTS_EPCIF_Pos) /*!< HSUSBD_T::GINTSTS: EPCIF Mask */
+
+#define HSUSBD_GINTSTS_EPDIF_Pos (5) /*!< HSUSBD_T::GINTSTS: EPDIF Position */
+#define HSUSBD_GINTSTS_EPDIF_Msk (0x1ul << HSUSBD_GINTSTS_EPDIF_Pos) /*!< HSUSBD_T::GINTSTS: EPDIF Mask */
+
+#define HSUSBD_GINTSTS_EPEIF_Pos (6) /*!< HSUSBD_T::GINTSTS: EPEIF Position */
+#define HSUSBD_GINTSTS_EPEIF_Msk (0x1ul << HSUSBD_GINTSTS_EPEIF_Pos) /*!< HSUSBD_T::GINTSTS: EPEIF Mask */
+
+#define HSUSBD_GINTSTS_EPFIF_Pos (7) /*!< HSUSBD_T::GINTSTS: EPFIF Position */
+#define HSUSBD_GINTSTS_EPFIF_Msk (0x1ul << HSUSBD_GINTSTS_EPFIF_Pos) /*!< HSUSBD_T::GINTSTS: EPFIF Mask */
+
+#define HSUSBD_GINTSTS_EPGIF_Pos (8) /*!< HSUSBD_T::GINTSTS: EPGIF Position */
+#define HSUSBD_GINTSTS_EPGIF_Msk (0x1ul << HSUSBD_GINTSTS_EPGIF_Pos) /*!< HSUSBD_T::GINTSTS: EPGIF Mask */
+
+#define HSUSBD_GINTSTS_EPHIF_Pos (9) /*!< HSUSBD_T::GINTSTS: EPHIF Position */
+#define HSUSBD_GINTSTS_EPHIF_Msk (0x1ul << HSUSBD_GINTSTS_EPHIF_Pos) /*!< HSUSBD_T::GINTSTS: EPHIF Mask */
+
+#define HSUSBD_GINTSTS_EPIIF_Pos (10) /*!< HSUSBD_T::GINTSTS: EPIIF Position */
+#define HSUSBD_GINTSTS_EPIIF_Msk (0x1ul << HSUSBD_GINTSTS_EPIIF_Pos) /*!< HSUSBD_T::GINTSTS: EPIIF Mask */
+
+#define HSUSBD_GINTSTS_EPJIF_Pos (11) /*!< HSUSBD_T::GINTSTS: EPJIF Position */
+#define HSUSBD_GINTSTS_EPJIF_Msk (0x1ul << HSUSBD_GINTSTS_EPJIF_Pos) /*!< HSUSBD_T::GINTSTS: EPJIF Mask */
+
+#define HSUSBD_GINTSTS_EPKIF_Pos (12) /*!< HSUSBD_T::GINTSTS: EPKIF Position */
+#define HSUSBD_GINTSTS_EPKIF_Msk (0x1ul << HSUSBD_GINTSTS_EPKIF_Pos) /*!< HSUSBD_T::GINTSTS: EPKIF Mask */
+
+#define HSUSBD_GINTSTS_EPLIF_Pos (13) /*!< HSUSBD_T::GINTSTS: EPLIF Position */
+#define HSUSBD_GINTSTS_EPLIF_Msk (0x1ul << HSUSBD_GINTSTS_EPLIF_Pos) /*!< HSUSBD_T::GINTSTS: EPLIF Mask */
+
+#define HSUSBD_GINTEN_USBIEN_Pos (0) /*!< HSUSBD_T::GINTEN: USBIEN Position */
+#define HSUSBD_GINTEN_USBIEN_Msk (0x1ul << HSUSBD_GINTEN_USBIEN_Pos) /*!< HSUSBD_T::GINTEN: USBIEN Mask */
+
+#define HSUSBD_GINTEN_CEPIEN_Pos (1) /*!< HSUSBD_T::GINTEN: CEPIEN Position */
+#define HSUSBD_GINTEN_CEPIEN_Msk (0x1ul << HSUSBD_GINTEN_CEPIEN_Pos) /*!< HSUSBD_T::GINTEN: CEPIEN Mask */
+
+#define HSUSBD_GINTEN_EPAIEN_Pos (2) /*!< HSUSBD_T::GINTEN: EPAIEN Position */
+#define HSUSBD_GINTEN_EPAIEN_Msk (0x1ul << HSUSBD_GINTEN_EPAIEN_Pos) /*!< HSUSBD_T::GINTEN: EPAIEN Mask */
+
+#define HSUSBD_GINTEN_EPBIEN_Pos (3) /*!< HSUSBD_T::GINTEN: EPBIEN Position */
+#define HSUSBD_GINTEN_EPBIEN_Msk (0x1ul << HSUSBD_GINTEN_EPBIEN_Pos) /*!< HSUSBD_T::GINTEN: EPBIEN Mask */
+
+#define HSUSBD_GINTEN_EPCIEN_Pos (4) /*!< HSUSBD_T::GINTEN: EPCIEN Position */
+#define HSUSBD_GINTEN_EPCIEN_Msk (0x1ul << HSUSBD_GINTEN_EPCIEN_Pos) /*!< HSUSBD_T::GINTEN: EPCIEN Mask */
+
+#define HSUSBD_GINTEN_EPDIEN_Pos (5) /*!< HSUSBD_T::GINTEN: EPDIEN Position */
+#define HSUSBD_GINTEN_EPDIEN_Msk (0x1ul << HSUSBD_GINTEN_EPDIEN_Pos) /*!< HSUSBD_T::GINTEN: EPDIEN Mask */
+
+#define HSUSBD_GINTEN_EPEIEN_Pos (6) /*!< HSUSBD_T::GINTEN: EPEIEN Position */
+#define HSUSBD_GINTEN_EPEIEN_Msk (0x1ul << HSUSBD_GINTEN_EPEIEN_Pos) /*!< HSUSBD_T::GINTEN: EPEIEN Mask */
+
+#define HSUSBD_GINTEN_EPFIEN_Pos (7) /*!< HSUSBD_T::GINTEN: EPFIEN Position */
+#define HSUSBD_GINTEN_EPFIEN_Msk (0x1ul << HSUSBD_GINTEN_EPFIEN_Pos) /*!< HSUSBD_T::GINTEN: EPFIEN Mask */
+
+#define HSUSBD_GINTEN_EPGIEN_Pos (8) /*!< HSUSBD_T::GINTEN: EPGIEN Position */
+#define HSUSBD_GINTEN_EPGIEN_Msk (0x1ul << HSUSBD_GINTEN_EPGIEN_Pos) /*!< HSUSBD_T::GINTEN: EPGIEN Mask */
+
+#define HSUSBD_GINTEN_EPHIEN_Pos (9) /*!< HSUSBD_T::GINTEN: EPHIEN Position */
+#define HSUSBD_GINTEN_EPHIEN_Msk (0x1ul << HSUSBD_GINTEN_EPHIEN_Pos) /*!< HSUSBD_T::GINTEN: EPHIEN Mask */
+
+#define HSUSBD_GINTEN_EPIIEN_Pos (10) /*!< HSUSBD_T::GINTEN: EPIIEN Position */
+#define HSUSBD_GINTEN_EPIIEN_Msk (0x1ul << HSUSBD_GINTEN_EPIIEN_Pos) /*!< HSUSBD_T::GINTEN: EPIIEN Mask */
+
+#define HSUSBD_GINTEN_EPJIEN_Pos (11) /*!< HSUSBD_T::GINTEN: EPJIEN Position */
+#define HSUSBD_GINTEN_EPJIEN_Msk (0x1ul << HSUSBD_GINTEN_EPJIEN_Pos) /*!< HSUSBD_T::GINTEN: EPJIEN Mask */
+
+#define HSUSBD_GINTEN_EPKIEN_Pos (12) /*!< HSUSBD_T::GINTEN: EPKIEN Position */
+#define HSUSBD_GINTEN_EPKIEN_Msk (0x1ul << HSUSBD_GINTEN_EPKIEN_Pos) /*!< HSUSBD_T::GINTEN: EPKIEN Mask */
+
+#define HSUSBD_GINTEN_EPLIEN_Pos (13) /*!< HSUSBD_T::GINTEN: EPLIEN Position */
+#define HSUSBD_GINTEN_EPLIEN_Msk (0x1ul << HSUSBD_GINTEN_EPLIEN_Pos) /*!< HSUSBD_T::GINTEN: EPLIEN Mask */
+
+#define HSUSBD_BUSINTSTS_SOFIF_Pos (0) /*!< HSUSBD_T::BUSINTSTS: SOFIF Position */
+#define HSUSBD_BUSINTSTS_SOFIF_Msk (0x1ul << HSUSBD_BUSINTSTS_SOFIF_Pos) /*!< HSUSBD_T::BUSINTSTS: SOFIF Mask */
+
+#define HSUSBD_BUSINTSTS_RSTIF_Pos (1) /*!< HSUSBD_T::BUSINTSTS: RSTIF Position */
+#define HSUSBD_BUSINTSTS_RSTIF_Msk (0x1ul << HSUSBD_BUSINTSTS_RSTIF_Pos) /*!< HSUSBD_T::BUSINTSTS: RSTIF Mask */
+
+#define HSUSBD_BUSINTSTS_RESUMEIF_Pos (2) /*!< HSUSBD_T::BUSINTSTS: RESUMEIF Position */
+#define HSUSBD_BUSINTSTS_RESUMEIF_Msk (0x1ul << HSUSBD_BUSINTSTS_RESUMEIF_Pos) /*!< HSUSBD_T::BUSINTSTS: RESUMEIF Mask */
+
+#define HSUSBD_BUSINTSTS_SUSPENDIF_Pos (3) /*!< HSUSBD_T::BUSINTSTS: SUSPENDIF Position*/
+#define HSUSBD_BUSINTSTS_SUSPENDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_SUSPENDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: SUSPENDIF Mask */
+
+#define HSUSBD_BUSINTSTS_HISPDIF_Pos (4) /*!< HSUSBD_T::BUSINTSTS: HISPDIF Position */
+#define HSUSBD_BUSINTSTS_HISPDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_HISPDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: HISPDIF Mask */
+
+#define HSUSBD_BUSINTSTS_DMADONEIF_Pos (5) /*!< HSUSBD_T::BUSINTSTS: DMADONEIF Position*/
+#define HSUSBD_BUSINTSTS_DMADONEIF_Msk (0x1ul << HSUSBD_BUSINTSTS_DMADONEIF_Pos) /*!< HSUSBD_T::BUSINTSTS: DMADONEIF Mask */
+
+#define HSUSBD_BUSINTSTS_PHYCLKVLDIF_Pos (6) /*!< HSUSBD_T::BUSINTSTS: PHYCLKVLDIF Position*/
+#define HSUSBD_BUSINTSTS_PHYCLKVLDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_PHYCLKVLDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: PHYCLKVLDIF Mask */
+
+#define HSUSBD_BUSINTSTS_VBUSDETIF_Pos (8) /*!< HSUSBD_T::BUSINTSTS: VBUSDETIF Position*/
+#define HSUSBD_BUSINTSTS_VBUSDETIF_Msk (0x1ul << HSUSBD_BUSINTSTS_VBUSDETIF_Pos) /*!< HSUSBD_T::BUSINTSTS: VBUSDETIF Mask */
+
+#define HSUSBD_BUSINTEN_SOFIEN_Pos (0) /*!< HSUSBD_T::BUSINTEN: SOFIEN Position */
+#define HSUSBD_BUSINTEN_SOFIEN_Msk (0x1ul << HSUSBD_BUSINTEN_SOFIEN_Pos) /*!< HSUSBD_T::BUSINTEN: SOFIEN Mask */
+
+#define HSUSBD_BUSINTEN_RSTIEN_Pos (1) /*!< HSUSBD_T::BUSINTEN: RSTIEN Position */
+#define HSUSBD_BUSINTEN_RSTIEN_Msk (0x1ul << HSUSBD_BUSINTEN_RSTIEN_Pos) /*!< HSUSBD_T::BUSINTEN: RSTIEN Mask */
+
+#define HSUSBD_BUSINTEN_RESUMEIEN_Pos (2) /*!< HSUSBD_T::BUSINTEN: RESUMEIEN Position */
+#define HSUSBD_BUSINTEN_RESUMEIEN_Msk (0x1ul << HSUSBD_BUSINTEN_RESUMEIEN_Pos) /*!< HSUSBD_T::BUSINTEN: RESUMEIEN Mask */
+
+#define HSUSBD_BUSINTEN_SUSPENDIEN_Pos (3) /*!< HSUSBD_T::BUSINTEN: SUSPENDIEN Position*/
+#define HSUSBD_BUSINTEN_SUSPENDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_SUSPENDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: SUSPENDIEN Mask */
+
+#define HSUSBD_BUSINTEN_HISPDIEN_Pos (4) /*!< HSUSBD_T::BUSINTEN: HISPDIEN Position */
+#define HSUSBD_BUSINTEN_HISPDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_HISPDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: HISPDIEN Mask */
+
+#define HSUSBD_BUSINTEN_DMADONEIEN_Pos (5) /*!< HSUSBD_T::BUSINTEN: DMADONEIEN Position*/
+#define HSUSBD_BUSINTEN_DMADONEIEN_Msk (0x1ul << HSUSBD_BUSINTEN_DMADONEIEN_Pos) /*!< HSUSBD_T::BUSINTEN: DMADONEIEN Mask */
+
+#define HSUSBD_BUSINTEN_PHYCLKVLDIEN_Pos (6) /*!< HSUSBD_T::BUSINTEN: PHYCLKVLDIEN Position*/
+#define HSUSBD_BUSINTEN_PHYCLKVLDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_PHYCLKVLDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: PHYCLKVLDIEN Mask */
+
+#define HSUSBD_BUSINTEN_VBUSDETIEN_Pos (8) /*!< HSUSBD_T::BUSINTEN: VBUSDETIEN Position*/
+#define HSUSBD_BUSINTEN_VBUSDETIEN_Msk (0x1ul << HSUSBD_BUSINTEN_VBUSDETIEN_Pos) /*!< HSUSBD_T::BUSINTEN: VBUSDETIEN Mask */
+
+#define HSUSBD_OPER_RESUMEEN_Pos (0) /*!< HSUSBD_T::OPER: RESUMEEN Position */
+#define HSUSBD_OPER_RESUMEEN_Msk (0x1ul << HSUSBD_OPER_RESUMEEN_Pos) /*!< HSUSBD_T::OPER: RESUMEEN Mask */
+
+#define HSUSBD_OPER_HISPDEN_Pos (1) /*!< HSUSBD_T::OPER: HISPDEN Position */
+#define HSUSBD_OPER_HISPDEN_Msk (0x1ul << HSUSBD_OPER_HISPDEN_Pos) /*!< HSUSBD_T::OPER: HISPDEN Mask */
+
+#define HSUSBD_OPER_CURSPD_Pos (2) /*!< HSUSBD_T::OPER: CURSPD Position */
+#define HSUSBD_OPER_CURSPD_Msk (0x1ul << HSUSBD_OPER_CURSPD_Pos) /*!< HSUSBD_T::OPER: CURSPD Mask */
+
+#define HSUSBD_FRAMECNT_MFRAMECNT_Pos (0) /*!< HSUSBD_T::FRAMECNT: MFRAMECNT Position */
+#define HSUSBD_FRAMECNT_MFRAMECNT_Msk (0x7ul << HSUSBD_FRAMECNT_MFRAMECNT_Pos) /*!< HSUSBD_T::FRAMECNT: MFRAMECNT Mask */
+
+#define HSUSBD_FRAMECNT_FRAMECNT_Pos (3) /*!< HSUSBD_T::FRAMECNT: FRAMECNT Position */
+#define HSUSBD_FRAMECNT_FRAMECNT_Msk (0x7fful << HSUSBD_FRAMECNT_FRAMECNT_Pos) /*!< HSUSBD_T::FRAMECNT: FRAMECNT Mask */
+
+#define HSUSBD_FADDR_FADDR_Pos (0) /*!< HSUSBD_T::FADDR: FADDR Position */
+#define HSUSBD_FADDR_FADDR_Msk (0x7ful << HSUSBD_FADDR_FADDR_Pos) /*!< HSUSBD_T::FADDR: FADDR Mask */
+
+#define HSUSBD_TEST_TESTMODE_Pos (0) /*!< HSUSBD_T::TEST: TESTMODE Position */
+#define HSUSBD_TEST_TESTMODE_Msk (0x7ul << HSUSBD_TEST_TESTMODE_Pos) /*!< HSUSBD_T::TEST: TESTMODE Mask */
+
+#define HSUSBD_CEPDAT_DAT_Pos (0) /*!< HSUSBD_T::CEPDAT: DAT Position */
+#define HSUSBD_CEPDAT_DAT_Msk (0xfffffffful << HSUSBD_CEPDAT_DAT_Pos) /*!< HSUSBD_T::CEPDAT: DAT Mask */
+
+#define HSUSBD_CEPCTL_NAKCLR_Pos (0) /*!< HSUSBD_T::CEPCTL: NAKCLR Position */
+#define HSUSBD_CEPCTL_NAKCLR_Msk (0x1ul << HSUSBD_CEPCTL_NAKCLR_Pos) /*!< HSUSBD_T::CEPCTL: NAKCLR Mask */
+
+#define HSUSBD_CEPCTL_STALLEN_Pos (1) /*!< HSUSBD_T::CEPCTL: STALLEN Position */
+#define HSUSBD_CEPCTL_STALLEN_Msk (0x1ul << HSUSBD_CEPCTL_STALLEN_Pos) /*!< HSUSBD_T::CEPCTL: STALLEN Mask */
+
+#define HSUSBD_CEPCTL_ZEROLEN_Pos (2) /*!< HSUSBD_T::CEPCTL: ZEROLEN Position */
+#define HSUSBD_CEPCTL_ZEROLEN_Msk (0x1ul << HSUSBD_CEPCTL_ZEROLEN_Pos) /*!< HSUSBD_T::CEPCTL: ZEROLEN Mask */
+
+#define HSUSBD_CEPCTL_FLUSH_Pos (3) /*!< HSUSBD_T::CEPCTL: FLUSH Position */
+#define HSUSBD_CEPCTL_FLUSH_Msk (0x1ul << HSUSBD_CEPCTL_FLUSH_Pos) /*!< HSUSBD_T::CEPCTL: FLUSH Mask */
+
+#define HSUSBD_CEPINTEN_SETUPTKIEN_Pos (0) /*!< HSUSBD_T::CEPINTEN: SETUPTKIEN Position*/
+#define HSUSBD_CEPINTEN_SETUPTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_SETUPTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: SETUPTKIEN Mask */
+
+#define HSUSBD_CEPINTEN_SETUPPKIEN_Pos (1) /*!< HSUSBD_T::CEPINTEN: SETUPPKIEN Position*/
+#define HSUSBD_CEPINTEN_SETUPPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_SETUPPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: SETUPPKIEN Mask */
+
+#define HSUSBD_CEPINTEN_OUTTKIEN_Pos (2) /*!< HSUSBD_T::CEPINTEN: OUTTKIEN Position */
+#define HSUSBD_CEPINTEN_OUTTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_OUTTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: OUTTKIEN Mask */
+
+#define HSUSBD_CEPINTEN_INTKIEN_Pos (3) /*!< HSUSBD_T::CEPINTEN: INTKIEN Position */
+#define HSUSBD_CEPINTEN_INTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_INTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: INTKIEN Mask */
+
+#define HSUSBD_CEPINTEN_PINGIEN_Pos (4) /*!< HSUSBD_T::CEPINTEN: PINGIEN Position */
+#define HSUSBD_CEPINTEN_PINGIEN_Msk (0x1ul << HSUSBD_CEPINTEN_PINGIEN_Pos) /*!< HSUSBD_T::CEPINTEN: PINGIEN Mask */
+
+#define HSUSBD_CEPINTEN_TXPKIEN_Pos (5) /*!< HSUSBD_T::CEPINTEN: TXPKIEN Position */
+#define HSUSBD_CEPINTEN_TXPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_TXPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: TXPKIEN Mask */
+
+#define HSUSBD_CEPINTEN_RXPKIEN_Pos (6) /*!< HSUSBD_T::CEPINTEN: RXPKIEN Position */
+#define HSUSBD_CEPINTEN_RXPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_RXPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: RXPKIEN Mask */
+
+#define HSUSBD_CEPINTEN_NAKIEN_Pos (7) /*!< HSUSBD_T::CEPINTEN: NAKIEN Position */
+#define HSUSBD_CEPINTEN_NAKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_NAKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: NAKIEN Mask */
+
+#define HSUSBD_CEPINTEN_STALLIEN_Pos (8) /*!< HSUSBD_T::CEPINTEN: STALLIEN Position */
+#define HSUSBD_CEPINTEN_STALLIEN_Msk (0x1ul << HSUSBD_CEPINTEN_STALLIEN_Pos) /*!< HSUSBD_T::CEPINTEN: STALLIEN Mask */
+
+#define HSUSBD_CEPINTEN_ERRIEN_Pos (9) /*!< HSUSBD_T::CEPINTEN: ERRIEN Position */
+#define HSUSBD_CEPINTEN_ERRIEN_Msk (0x1ul << HSUSBD_CEPINTEN_ERRIEN_Pos) /*!< HSUSBD_T::CEPINTEN: ERRIEN Mask */
+
+#define HSUSBD_CEPINTEN_STSDONEIEN_Pos (10) /*!< HSUSBD_T::CEPINTEN: STSDONEIEN Position*/
+#define HSUSBD_CEPINTEN_STSDONEIEN_Msk (0x1ul << HSUSBD_CEPINTEN_STSDONEIEN_Pos) /*!< HSUSBD_T::CEPINTEN: STSDONEIEN Mask */
+
+#define HSUSBD_CEPINTEN_BUFFULLIEN_Pos (11) /*!< HSUSBD_T::CEPINTEN: BUFFULLIEN Position*/
+#define HSUSBD_CEPINTEN_BUFFULLIEN_Msk (0x1ul << HSUSBD_CEPINTEN_BUFFULLIEN_Pos) /*!< HSUSBD_T::CEPINTEN: BUFFULLIEN Mask */
+
+#define HSUSBD_CEPINTEN_BUFEMPTYIEN_Pos (12) /*!< HSUSBD_T::CEPINTEN: BUFEMPTYIEN Position*/
+#define HSUSBD_CEPINTEN_BUFEMPTYIEN_Msk (0x1ul << HSUSBD_CEPINTEN_BUFEMPTYIEN_Pos) /*!< HSUSBD_T::CEPINTEN: BUFEMPTYIEN Mask */
+
+#define HSUSBD_CEPINTSTS_SETUPTKIF_Pos (0) /*!< HSUSBD_T::CEPINTSTS: SETUPTKIF Position*/
+#define HSUSBD_CEPINTSTS_SETUPTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_SETUPTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: SETUPTKIF Mask */
+
+#define HSUSBD_CEPINTSTS_SETUPPKIF_Pos (1) /*!< HSUSBD_T::CEPINTSTS: SETUPPKIF Position*/
+#define HSUSBD_CEPINTSTS_SETUPPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_SETUPPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: SETUPPKIF Mask */
+
+#define HSUSBD_CEPINTSTS_OUTTKIF_Pos (2) /*!< HSUSBD_T::CEPINTSTS: OUTTKIF Position */
+#define HSUSBD_CEPINTSTS_OUTTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_OUTTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: OUTTKIF Mask */
+
+#define HSUSBD_CEPINTSTS_INTKIF_Pos (3) /*!< HSUSBD_T::CEPINTSTS: INTKIF Position */
+#define HSUSBD_CEPINTSTS_INTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_INTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: INTKIF Mask */
+
+#define HSUSBD_CEPINTSTS_PINGIF_Pos (4) /*!< HSUSBD_T::CEPINTSTS: PINGIF Position */
+#define HSUSBD_CEPINTSTS_PINGIF_Msk (0x1ul << HSUSBD_CEPINTSTS_PINGIF_Pos) /*!< HSUSBD_T::CEPINTSTS: PINGIF Mask */
+
+#define HSUSBD_CEPINTSTS_TXPKIF_Pos (5) /*!< HSUSBD_T::CEPINTSTS: TXPKIF Position */
+#define HSUSBD_CEPINTSTS_TXPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_TXPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: TXPKIF Mask */
+
+#define HSUSBD_CEPINTSTS_RXPKIF_Pos (6) /*!< HSUSBD_T::CEPINTSTS: RXPKIF Position */
+#define HSUSBD_CEPINTSTS_RXPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_RXPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: RXPKIF Mask */
+
+#define HSUSBD_CEPINTSTS_NAKIF_Pos (7) /*!< HSUSBD_T::CEPINTSTS: NAKIF Position */
+#define HSUSBD_CEPINTSTS_NAKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_NAKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: NAKIF Mask */
+
+#define HSUSBD_CEPINTSTS_STALLIF_Pos (8) /*!< HSUSBD_T::CEPINTSTS: STALLIF Position */
+#define HSUSBD_CEPINTSTS_STALLIF_Msk (0x1ul << HSUSBD_CEPINTSTS_STALLIF_Pos) /*!< HSUSBD_T::CEPINTSTS: STALLIF Mask */
+
+#define HSUSBD_CEPINTSTS_ERRIF_Pos (9) /*!< HSUSBD_T::CEPINTSTS: ERRIF Position */
+#define HSUSBD_CEPINTSTS_ERRIF_Msk (0x1ul << HSUSBD_CEPINTSTS_ERRIF_Pos) /*!< HSUSBD_T::CEPINTSTS: ERRIF Mask */
+
+#define HSUSBD_CEPINTSTS_STSDONEIF_Pos (10) /*!< HSUSBD_T::CEPINTSTS: STSDONEIF Position*/
+#define HSUSBD_CEPINTSTS_STSDONEIF_Msk (0x1ul << HSUSBD_CEPINTSTS_STSDONEIF_Pos) /*!< HSUSBD_T::CEPINTSTS: STSDONEIF Mask */
+
+#define HSUSBD_CEPINTSTS_BUFFULLIF_Pos (11) /*!< HSUSBD_T::CEPINTSTS: BUFFULLIF Position*/
+#define HSUSBD_CEPINTSTS_BUFFULLIF_Msk (0x1ul << HSUSBD_CEPINTSTS_BUFFULLIF_Pos) /*!< HSUSBD_T::CEPINTSTS: BUFFULLIF Mask */
+
+#define HSUSBD_CEPINTSTS_BUFEMPTYIF_Pos (12) /*!< HSUSBD_T::CEPINTSTS: BUFEMPTYIF Position*/
+#define HSUSBD_CEPINTSTS_BUFEMPTYIF_Msk (0x1ul << HSUSBD_CEPINTSTS_BUFEMPTYIF_Pos) /*!< HSUSBD_T::CEPINTSTS: BUFEMPTYIF Mask */
+
+#define HSUSBD_CEPTXCNT_TXCNT_Pos (0) /*!< HSUSBD_T::CEPTXCNT: TXCNT Position */
+#define HSUSBD_CEPTXCNT_TXCNT_Msk (0xfful << HSUSBD_CEPTXCNT_TXCNT_Pos) /*!< HSUSBD_T::CEPTXCNT: TXCNT Mask */
+
+#define HSUSBD_CEPRXCNT_RXCNT_Pos (0) /*!< HSUSBD_T::CEPRXCNT: RXCNT Position */
+#define HSUSBD_CEPRXCNT_RXCNT_Msk (0xfful << HSUSBD_CEPRXCNT_RXCNT_Pos) /*!< HSUSBD_T::CEPRXCNT: RXCNT Mask */
+
+#define HSUSBD_CEPDATCNT_DATCNT_Pos (0) /*!< HSUSBD_T::CEPDATCNT: DATCNT Position */
+#define HSUSBD_CEPDATCNT_DATCNT_Msk (0xfffful << HSUSBD_CEPDATCNT_DATCNT_Pos) /*!< HSUSBD_T::CEPDATCNT: DATCNT Mask */
+
+#define HSUSBD_SETUP1_0_SETUP0_Pos (0) /*!< HSUSBD_T::SETUP1_0: SETUP0 Position */
+#define HSUSBD_SETUP1_0_SETUP0_Msk (0xfful << HSUSBD_SETUP1_0_SETUP0_Pos) /*!< HSUSBD_T::SETUP1_0: SETUP0 Mask */
+
+#define HSUSBD_SETUP1_0_SETUP1_Pos (8) /*!< HSUSBD_T::SETUP1_0: SETUP1 Position */
+#define HSUSBD_SETUP1_0_SETUP1_Msk (0xfful << HSUSBD_SETUP1_0_SETUP1_Pos) /*!< HSUSBD_T::SETUP1_0: SETUP1 Mask */
+
+#define HSUSBD_SETUP3_2_SETUP2_Pos (0) /*!< HSUSBD_T::SETUP3_2: SETUP2 Position */
+#define HSUSBD_SETUP3_2_SETUP2_Msk (0xfful << HSUSBD_SETUP3_2_SETUP2_Pos) /*!< HSUSBD_T::SETUP3_2: SETUP2 Mask */
+
+#define HSUSBD_SETUP3_2_SETUP3_Pos (8) /*!< HSUSBD_T::SETUP3_2: SETUP3 Position */
+#define HSUSBD_SETUP3_2_SETUP3_Msk (0xfful << HSUSBD_SETUP3_2_SETUP3_Pos) /*!< HSUSBD_T::SETUP3_2: SETUP3 Mask */
+
+#define HSUSBD_SETUP5_4_SETUP4_Pos (0) /*!< HSUSBD_T::SETUP5_4: SETUP4 Position */
+#define HSUSBD_SETUP5_4_SETUP4_Msk (0xfful << HSUSBD_SETUP5_4_SETUP4_Pos) /*!< HSUSBD_T::SETUP5_4: SETUP4 Mask */
+
+#define HSUSBD_SETUP5_4_SETUP5_Pos (8) /*!< HSUSBD_T::SETUP5_4: SETUP5 Position */
+#define HSUSBD_SETUP5_4_SETUP5_Msk (0xfful << HSUSBD_SETUP5_4_SETUP5_Pos) /*!< HSUSBD_T::SETUP5_4: SETUP5 Mask */
+
+#define HSUSBD_SETUP7_6_SETUP6_Pos (0) /*!< HSUSBD_T::SETUP7_6: SETUP6 Position */
+#define HSUSBD_SETUP7_6_SETUP6_Msk (0xfful << HSUSBD_SETUP7_6_SETUP6_Pos) /*!< HSUSBD_T::SETUP7_6: SETUP6 Mask */
+
+#define HSUSBD_SETUP7_6_SETUP7_Pos (8) /*!< HSUSBD_T::SETUP7_6: SETUP7 Position */
+#define HSUSBD_SETUP7_6_SETUP7_Msk (0xfful << HSUSBD_SETUP7_6_SETUP7_Pos) /*!< HSUSBD_T::SETUP7_6: SETUP7 Mask */
+
+#define HSUSBD_CEPBUFST_SADDR_Pos (0) /*!< HSUSBD_T::CEPBUFST: SADDR Position */
+#define HSUSBD_CEPBUFST_SADDR_Msk (0xffful << HSUSBD_CEPBUFST_SADDR_Pos) /*!< HSUSBD_T::CEPBUFST: SADDR Mask */
+
+#define HSUSBD_CEPBUFEND_EADDR_Pos (0) /*!< HSUSBD_T::CEPBUFEND: EADDR Position */
+#define HSUSBD_CEPBUFEND_EADDR_Msk (0xffful << HSUSBD_CEPBUFEND_EADDR_Pos) /*!< HSUSBD_T::CEPBUFEND: EADDR Mask */
+
+#define HSUSBD_DMACTL_EPNUM_Pos (0) /*!< HSUSBD_T::DMACTL: EPNUM Position */
+#define HSUSBD_DMACTL_EPNUM_Msk (0xful << HSUSBD_DMACTL_EPNUM_Pos) /*!< HSUSBD_T::DMACTL: EPNUM Mask */
+
+#define HSUSBD_DMACTL_DMARD_Pos (4) /*!< HSUSBD_T::DMACTL: DMARD Position */
+#define HSUSBD_DMACTL_DMARD_Msk (0x1ul << HSUSBD_DMACTL_DMARD_Pos) /*!< HSUSBD_T::DMACTL: DMARD Mask */
+
+#define HSUSBD_DMACTL_DMAEN_Pos (5) /*!< HSUSBD_T::DMACTL: DMAEN Position */
+#define HSUSBD_DMACTL_DMAEN_Msk (0x1ul << HSUSBD_DMACTL_DMAEN_Pos) /*!< HSUSBD_T::DMACTL: DMAEN Mask */
+
+#define HSUSBD_DMACTL_SGEN_Pos (6) /*!< HSUSBD_T::DMACTL: SGEN Position */
+#define HSUSBD_DMACTL_SGEN_Msk (0x1ul << HSUSBD_DMACTL_SGEN_Pos) /*!< HSUSBD_T::DMACTL: SGEN Mask */
+
+#define HSUSBD_DMACTL_DMARST_Pos (7) /*!< HSUSBD_T::DMACTL: DMARST Position */
+#define HSUSBD_DMACTL_DMARST_Msk (0x1ul << HSUSBD_DMACTL_DMARST_Pos) /*!< HSUSBD_T::DMACTL: DMARST Mask */
+
+#define HSUSBD_DMACTL_SVINEP_Pos (8) /*!< HSUSBD_T::DMACTL: SVINEP Position */
+#define HSUSBD_DMACTL_SVINEP_Msk (0x1ul << HSUSBD_DMACTL_SVINEP_Pos) /*!< HSUSBD_T::DMACTL: SVINEP Mask */
+
+#define HSUSBD_DMACNT_DMACNT_Pos (0) /*!< HSUSBD_T::DMACNT: DMACNT Position */
+#define HSUSBD_DMACNT_DMACNT_Msk (0xffffful << HSUSBD_DMACNT_DMACNT_Pos) /*!< HSUSBD_T::DMACNT: DMACNT Mask */
+
+#define HSUSBD_EPDAT_EPDAT_Pos (0) /*!< HSUSBD_T::EPDAT: EPDAT Position */
+#define HSUSBD_EPDAT_EPDAT_Msk (0xfffffffful << HSUSBD_EPDAT_EPDAT_Pos) /*!< HSUSBD_T::EPDAT: EPDAT Mask */
+
+#define HSUSBD_EPINTSTS_BUFFULLIF_Pos (0) /*!< HSUSBD_T::EPINTSTS: BUFFULLIF Position */
+#define HSUSBD_EPINTSTS_BUFFULLIF_Msk (0x1ul << HSUSBD_EPINTSTS_BUFFULLIF_Pos) /*!< HSUSBD_T::EPINTSTS: BUFFULLIF Mask */
+
+#define HSUSBD_EPINTSTS_BUFEMPTYIF_Pos (1) /*!< HSUSBD_T::EPINTSTS: BUFEMPTYIF Position*/
+#define HSUSBD_EPINTSTS_BUFEMPTYIF_Msk (0x1ul << HSUSBD_EPINTSTS_BUFEMPTYIF_Pos) /*!< HSUSBD_T::EPINTSTS: BUFEMPTYIF Mask */
+
+#define HSUSBD_EPINTSTS_SHORTTXIF_Pos (2) /*!< HSUSBD_T::EPINTSTS: SHORTTXIF Position */
+#define HSUSBD_EPINTSTS_SHORTTXIF_Msk (0x1ul << HSUSBD_EPINTSTS_SHORTTXIF_Pos) /*!< HSUSBD_T::EPINTSTS: SHORTTXIF Mask */
+
+#define HSUSBD_EPINTSTS_TXPKIF_Pos (3) /*!< HSUSBD_T::EPINTSTS: TXPKIF Position */
+#define HSUSBD_EPINTSTS_TXPKIF_Msk (0x1ul << HSUSBD_EPINTSTS_TXPKIF_Pos) /*!< HSUSBD_T::EPINTSTS: TXPKIF Mask */
+
+#define HSUSBD_EPINTSTS_RXPKIF_Pos (4) /*!< HSUSBD_T::EPINTSTS: RXPKIF Position */
+#define HSUSBD_EPINTSTS_RXPKIF_Msk (0x1ul << HSUSBD_EPINTSTS_RXPKIF_Pos) /*!< HSUSBD_T::EPINTSTS: RXPKIF Mask */
+
+#define HSUSBD_EPINTSTS_OUTTKIF_Pos (5) /*!< HSUSBD_T::EPINTSTS: OUTTKIF Position */
+#define HSUSBD_EPINTSTS_OUTTKIF_Msk (0x1ul << HSUSBD_EPINTSTS_OUTTKIF_Pos) /*!< HSUSBD_T::EPINTSTS: OUTTKIF Mask */
+
+#define HSUSBD_EPINTSTS_INTKIF_Pos (6) /*!< HSUSBD_T::EPINTSTS: INTKIF Position */
+#define HSUSBD_EPINTSTS_INTKIF_Msk (0x1ul << HSUSBD_EPINTSTS_INTKIF_Pos) /*!< HSUSBD_T::EPINTSTS: INTKIF Mask */
+
+#define HSUSBD_EPINTSTS_PINGIF_Pos (7) /*!< HSUSBD_T::EPINTSTS: PINGIF Position */
+#define HSUSBD_EPINTSTS_PINGIF_Msk (0x1ul << HSUSBD_EPINTSTS_PINGIF_Pos) /*!< HSUSBD_T::EPINTSTS: PINGIF Mask */
+
+#define HSUSBD_EPINTSTS_NAKIF_Pos (8) /*!< HSUSBD_T::EPINTSTS: NAKIF Position */
+#define HSUSBD_EPINTSTS_NAKIF_Msk (0x1ul << HSUSBD_EPINTSTS_NAKIF_Pos) /*!< HSUSBD_T::EPINTSTS: NAKIF Mask */
+
+#define HSUSBD_EPINTSTS_STALLIF_Pos (9) /*!< HSUSBD_T::EPINTSTS: STALLIF Position */
+#define HSUSBD_EPINTSTS_STALLIF_Msk (0x1ul << HSUSBD_EPINTSTS_STALLIF_Pos) /*!< HSUSBD_T::EPINTSTS: STALLIF Mask */
+
+#define HSUSBD_EPINTSTS_NYETIF_Pos (10) /*!< HSUSBD_T::EPINTSTS: NYETIF Position */
+#define HSUSBD_EPINTSTS_NYETIF_Msk (0x1ul << HSUSBD_EPINTSTS_NYETIF_Pos) /*!< HSUSBD_T::EPINTSTS: NYETIF Mask */
+
+#define HSUSBD_EPINTSTS_ERRIF_Pos (11) /*!< HSUSBD_T::EPINTSTS: ERRIF Position */
+#define HSUSBD_EPINTSTS_ERRIF_Msk (0x1ul << HSUSBD_EPINTSTS_ERRIF_Pos) /*!< HSUSBD_T::EPINTSTS: ERRIF Mask */
+
+#define HSUSBD_EPINTSTS_SHORTRXIF_Pos (12) /*!< HSUSBD_T::EPINTSTS: SHORTRXIF Position */
+#define HSUSBD_EPINTSTS_SHORTRXIF_Msk (0x1ul << HSUSBD_EPINTSTS_SHORTRXIF_Pos) /*!< HSUSBD_T::EPINTSTS: SHORTRXIF Mask */
+
+#define HSUSBD_EPINTEN_BUFFULLIEN_Pos (0) /*!< HSUSBD_T::EPINTEN: BUFFULLIEN Position */
+#define HSUSBD_EPINTEN_BUFFULLIEN_Msk (0x1ul << HSUSBD_EPINTEN_BUFFULLIEN_Pos) /*!< HSUSBD_T::EPINTEN: BUFFULLIEN Mask */
+
+#define HSUSBD_EPINTEN_BUFEMPTYIEN_Pos (1) /*!< HSUSBD_T::EPINTEN: BUFEMPTYIEN Position*/
+#define HSUSBD_EPINTEN_BUFEMPTYIEN_Msk (0x1ul << HSUSBD_EPINTEN_BUFEMPTYIEN_Pos) /*!< HSUSBD_T::EPINTEN: BUFEMPTYIEN Mask */
+
+#define HSUSBD_EPINTEN_SHORTTXIEN_Pos (2) /*!< HSUSBD_T::EPINTEN: SHORTTXIEN Position */
+#define HSUSBD_EPINTEN_SHORTTXIEN_Msk (0x1ul << HSUSBD_EPINTEN_SHORTTXIEN_Pos) /*!< HSUSBD_T::EPINTEN: SHORTTXIEN Mask */
+
+#define HSUSBD_EPINTEN_TXPKIEN_Pos (3) /*!< HSUSBD_T::EPINTEN: TXPKIEN Position */
+#define HSUSBD_EPINTEN_TXPKIEN_Msk (0x1ul << HSUSBD_EPINTEN_TXPKIEN_Pos) /*!< HSUSBD_T::EPINTEN: TXPKIEN Mask */
+
+#define HSUSBD_EPINTEN_RXPKIEN_Pos (4) /*!< HSUSBD_T::EPINTEN: RXPKIEN Position */
+#define HSUSBD_EPINTEN_RXPKIEN_Msk (0x1ul << HSUSBD_EPINTEN_RXPKIEN_Pos) /*!< HSUSBD_T::EPINTEN: RXPKIEN Mask */
+
+#define HSUSBD_EPINTEN_OUTTKIEN_Pos (5) /*!< HSUSBD_T::EPINTEN: OUTTKIEN Position */
+#define HSUSBD_EPINTEN_OUTTKIEN_Msk (0x1ul << HSUSBD_EPINTEN_OUTTKIEN_Pos) /*!< HSUSBD_T::EPINTEN: OUTTKIEN Mask */
+
+#define HSUSBD_EPINTEN_INTKIEN_Pos (6) /*!< HSUSBD_T::EPINTEN: INTKIEN Position */
+#define HSUSBD_EPINTEN_INTKIEN_Msk (0x1ul << HSUSBD_EPINTEN_INTKIEN_Pos) /*!< HSUSBD_T::EPINTEN: INTKIEN Mask */
+
+#define HSUSBD_EPINTEN_PINGIEN_Pos (7) /*!< HSUSBD_T::EPINTEN: PINGIEN Position */
+#define HSUSBD_EPINTEN_PINGIEN_Msk (0x1ul << HSUSBD_EPINTEN_PINGIEN_Pos) /*!< HSUSBD_T::EPINTEN: PINGIEN Mask */
+
+#define HSUSBD_EPINTEN_NAKIEN_Pos (8) /*!< HSUSBD_T::EPINTEN: NAKIEN Position */
+#define HSUSBD_EPINTEN_NAKIEN_Msk (0x1ul << HSUSBD_EPINTEN_NAKIEN_Pos) /*!< HSUSBD_T::EPINTEN: NAKIEN Mask */
+
+#define HSUSBD_EPINTEN_STALLIEN_Pos (9) /*!< HSUSBD_T::EPINTEN: STALLIEN Position */
+#define HSUSBD_EPINTEN_STALLIEN_Msk (0x1ul << HSUSBD_EPINTEN_STALLIEN_Pos) /*!< HSUSBD_T::EPINTEN: STALLIEN Mask */
+
+#define HSUSBD_EPINTEN_NYETIEN_Pos (10) /*!< HSUSBD_T::EPINTEN: NYETIEN Position */
+#define HSUSBD_EPINTEN_NYETIEN_Msk (0x1ul << HSUSBD_EPINTEN_NYETIEN_Pos) /*!< HSUSBD_T::EPINTEN: NYETIEN Mask */
+
+#define HSUSBD_EPINTEN_ERRIEN_Pos (11) /*!< HSUSBD_T::EPINTEN: ERRIEN Position */
+#define HSUSBD_EPINTEN_ERRIEN_Msk (0x1ul << HSUSBD_EPINTEN_ERRIEN_Pos) /*!< HSUSBD_T::EPINTEN: ERRIEN Mask */
+
+#define HSUSBD_EPINTEN_SHORTRXIEN_Pos (12) /*!< HSUSBD_T::EPINTEN: SHORTRXIEN Position */
+#define HSUSBD_EPINTEN_SHORTRXIEN_Msk (0x1ul << HSUSBD_EPINTEN_SHORTRXIEN_Pos) /*!< HSUSBD_T::EPINTEN: SHORTRXIEN Mask */
+
+#define HSUSBD_EPDATCNT_DATCNT_Pos (0) /*!< HSUSBD_T::EPDATCNT: DATCNT Position */
+#define HSUSBD_EPDATCNT_DATCNT_Msk (0xfffful << HSUSBD_EPDATCNT_DATCNT_Pos) /*!< HSUSBD_T::EPDATCNT: DATCNT Mask */
+
+#define HSUSBD_EPDATCNT_DMALOOP_Pos (16) /*!< HSUSBD_T::EPDATCNT: DMALOOP Position */
+#define HSUSBD_EPDATCNT_DMALOOP_Msk (0x7ffful << HSUSBD_EPDATCNT_DMALOOP_Pos) /*!< HSUSBD_T::EPDATCNT: DMALOOP Mask */
+
+#define HSUSBD_EPRSPCTL_FLUSH_Pos (0) /*!< HSUSBD_T::EPRSPCTL: FLUSH Position */
+#define HSUSBD_EPRSPCTL_FLUSH_Msk (0x1ul << HSUSBD_EPRSPCTL_FLUSH_Pos) /*!< HSUSBD_T::EPRSPCTL: FLUSH Mask */
+
+#define HSUSBD_EPRSPCTL_MODE_Pos (1) /*!< HSUSBD_T::EPRSPCTL: MODE Position */
+#define HSUSBD_EPRSPCTL_MODE_Msk (0x3ul << HSUSBD_EPRSPCTL_MODE_Pos) /*!< HSUSBD_T::EPRSPCTL: MODE Mask */
+
+#define HSUSBD_EPRSPCTL_TOGGLE_Pos (3) /*!< HSUSBD_T::EPRSPCTL: TOGGLE Position */
+#define HSUSBD_EPRSPCTL_TOGGLE_Msk (0x1ul << HSUSBD_EPRSPCTL_TOGGLE_Pos) /*!< HSUSBD_T::EPRSPCTL: TOGGLE Mask */
+
+#define HSUSBD_EPRSPCTL_HALT_Pos (4) /*!< HSUSBD_T::EPRSPCTL: HALT Position */
+#define HSUSBD_EPRSPCTL_HALT_Msk (0x1ul << HSUSBD_EPRSPCTL_HALT_Pos) /*!< HSUSBD_T::EPRSPCTL: HALT Mask */
+
+#define HSUSBD_EPRSPCTL_ZEROLEN_Pos (5) /*!< HSUSBD_T::EPRSPCTL: ZEROLEN Position */
+#define HSUSBD_EPRSPCTL_ZEROLEN_Msk (0x1ul << HSUSBD_EPRSPCTL_ZEROLEN_Pos) /*!< HSUSBD_T::EPRSPCTL: ZEROLEN Mask */
+
+#define HSUSBD_EPRSPCTL_SHORTTXEN_Pos (6) /*!< HSUSBD_T::EPRSPCTL: SHORTTXEN Position */
+#define HSUSBD_EPRSPCTL_SHORTTXEN_Msk (0x1ul << HSUSBD_EPRSPCTL_SHORTTXEN_Pos) /*!< HSUSBD_T::EPRSPCTL: SHORTTXEN Mask */
+
+#define HSUSBD_EPRSPCTL_DISBUF_Pos (7) /*!< HSUSBD_T::EPRSPCTL: DISBUF Position */
+#define HSUSBD_EPRSPCTL_DISBUF_Msk (0x1ul << HSUSBD_EPRSPCTL_DISBUF_Pos) /*!< HSUSBD_T::EPRSPCTL: DISBUF Mask */
+
+#define HSUSBD_EPMPS_EPMPS_Pos (0) /*!< HSUSBD_T::EPMPS: EPMPS Position */
+#define HSUSBD_EPMPS_EPMPS_Msk (0x7fful << HSUSBD_EPMPS_EPMPS_Pos) /*!< HSUSBD_T::EPMPS: EPMPS Mask */
+
+#define HSUSBD_EPTXCNT_TXCNT_Pos (0) /*!< HSUSBD_T::EPTXCNT: TXCNT Position */
+#define HSUSBD_EPTXCNT_TXCNT_Msk (0x7fful << HSUSBD_EPTXCNT_TXCNT_Pos) /*!< HSUSBD_T::EPTXCNT: TXCNT Mask */
+
+#define HSUSBD_EPCFG_EPEN_Pos (0) /*!< HSUSBD_T::EPCFG: EPEN Position */
+#define HSUSBD_EPCFG_EPEN_Msk (0x1ul << HSUSBD_EPCFG_EPEN_Pos) /*!< HSUSBD_T::EPCFG: EPEN Mask */
+
+#define HSUSBD_EPCFG_EPTYPE_Pos (1) /*!< HSUSBD_T::EPCFG: EPTYPE Position */
+#define HSUSBD_EPCFG_EPTYPE_Msk (0x3ul << HSUSBD_EPCFG_EPTYPE_Pos) /*!< HSUSBD_T::EPCFG: EPTYPE Mask */
+
+#define HSUSBD_EPCFG_EPDIR_Pos (3) /*!< HSUSBD_T::EPCFG: EPDIR Position */
+#define HSUSBD_EPCFG_EPDIR_Msk (0x1ul << HSUSBD_EPCFG_EPDIR_Pos) /*!< HSUSBD_T::EPCFG: EPDIR Mask */
+
+#define HSUSBD_EPCFG_EPNUM_Pos (4) /*!< HSUSBD_T::EPCFG: EPNUM Position */
+#define HSUSBD_EPCFG_EPNUM_Msk (0xful << HSUSBD_EPCFG_EPNUM_Pos) /*!< HSUSBD_T::EPCFG: EPNUM Mask */
+
+#define HSUSBD_EPBUFST_SADDR_Pos (0) /*!< HSUSBD_T::EPBUFST: SADDR Position */
+#define HSUSBD_EPBUFST_SADDR_Msk (0xffful << HSUSBD_EPBUFST_SADDR_Pos) /*!< HSUSBD_T::EPBUFST: SADDR Mask */
+
+#define HSUSBD_EPBUFEND_EADDR_Pos (0) /*!< HSUSBD_T::EPBUFEND: EADDR Position */
+#define HSUSBD_EPBUFEND_EADDR_Msk (0xffful << HSUSBD_EPBUFEND_EADDR_Pos) /*!< HSUSBD_T::EPBUFEND: EADDR Mask */
+
+#define HSUSBD_DMAADDR_DMAADDR_Pos (0) /*!< HSUSBD_T::DMAADDR: DMAADDR Position */
+#define HSUSBD_DMAADDR_DMAADDR_Msk (0xfffffffful << HSUSBD_DMAADDR_DMAADDR_Pos) /*!< HSUSBD_T::DMAADDR: DMAADDR Mask */
+
+#define HSUSBD_PHYCTL_DPPUEN_Pos (8) /*!< HSUSBD_T::PHYCTL: DPPUEN Position */
+#define HSUSBD_PHYCTL_DPPUEN_Msk (0x1ul << HSUSBD_PHYCTL_DPPUEN_Pos) /*!< HSUSBD_T::PHYCTL: DPPUEN Mask */
+
+#define HSUSBD_PHYCTL_PHYEN_Pos (9) /*!< HSUSBD_T::PHYCTL: PHYEN Position */
+#define HSUSBD_PHYCTL_PHYEN_Msk (0x1ul << HSUSBD_PHYCTL_PHYEN_Pos) /*!< HSUSBD_T::PHYCTL: PHYEN Mask */
+
+#define HSUSBD_PHYCTL_WKEN_Pos (24) /*!< HSUSBD_T::PHYCTL: WKEN Position */
+#define HSUSBD_PHYCTL_WKEN_Msk (0x1ul << HSUSBD_PHYCTL_WKEN_Pos) /*!< HSUSBD_T::PHYCTL: WKEN Mask */
+
+#define HSUSBD_PHYCTL_VBUSDET_Pos (31) /*!< HSUSBD_T::PHYCTL: VBUSDET Position */
+#define HSUSBD_PHYCTL_VBUSDET_Msk (0x1ul << HSUSBD_PHYCTL_VBUSDET_Pos) /*!< HSUSBD_T::PHYCTL: VBUSDET Mask */
+
+/**@}*/ /* HSUSBD_CONST */
+/**@}*/ /* end of HSUSBD register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __HSUSBD_REG_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Include/m480_rtc_reg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Include/m480_rtc_reg.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1245 @@
+/**************************************************************************//**
+ * @file rtc_reg.h
+ * @version V1.00
+ * @brief RTC register definition header file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/
+#ifndef __RTC_REG_H__
+#define __RTC_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup RTC Real Time Clock Controller(RTC)
+ Memory Mapped Structure for RTC Controller
+@{ */
+
+typedef struct {
+
+
+ /**
+ * @var RTC_T::INIT
+ * Offset: 0x00 RTC Initiation Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |INIT_ACTIVE|RTC Active Status (Read Only)
+ * | | |0 = RTC is at reset state.
+ * | | |1 = RTC is at normal active state.
+ * |[31:1] |INIT |RTC Initiation (Write Only)
+ * | | |When RTC block is powered on, RTC is at reset state
+ * | | |User has to write a number (0xa5eb1357) to INIT to make RTC leaving reset state
+ * | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
+ * | | |The INIT is a write-only field and read value will be always 0.
+ * @var RTC_T::RWEN
+ * Offset: 0x04 RTC Access Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[16] |RWENF |RTC Register Access Enable Flag (Read Only)
+ * | | |0 = RTC register read/write Disabled.
+ * | | |1 = RTC register read/write Enabled.
+ * | | |Note: RWENF will be mask to 0 during RTCBUSY is 1, and first turn on RTCCKEN (CLK_APBCLK[1]) also.
+ * |[24] |RTCBUSY |RTC Write Busy Flag
+ * | | |This bit indicates RTC registers are writable or not.
+ * | | |0: RTC registers are writable.
+ * | | |1: RTC registers can't write, RTC under Busy Status.
+ * | | |Note: RTCBUSY flag will be set when execute write RTC register command exceed 6 times within 1120 PCLK cycles.
+ * @var RTC_T::FREQADJ
+ * Offset: 0x08 RTC Frequency Compensation Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[21:0] |FREQADJ |Frequency Compensation Register
+ * | | |User must to get actual LXT frequency for RTC application.
+ * | | |FCR = 0x200000 * (32768 / LXT frequency).
+ * | | |Note: This formula is suitable only when RTC clock source is from LXT, RTCSEL (CLK_CLKSEL3[8]) is 0.
+ * @var RTC_T::TIME
+ * Offset: 0x0C RTC Time Loading Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |SEC |1-Sec Time Digit (0~9)
+ * |[6:4] |TENSEC |10-Sec Time Digit (0~5)
+ * |[11:8] |MIN |1-Min Time Digit (0~9)
+ * |[14:12] |TENMIN |10-Min Time Digit (0~5)
+ * |[19:16] |HR |1-Hour Time Digit (0~9)
+ * |[21:20] |TENHR |10-Hour Time Digit (0~2)
+ * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication
+ * | | |(If RTC_TIME[21] is 1, it indicates PM time message).
+ * @var RTC_T::CAL
+ * Offset: 0x10 RTC Calendar Loading Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |DAY |1-Day Calendar Digit (0~9)
+ * |[5:4] |TENDAY |10-Day Calendar Digit (0~3)
+ * |[11:8] |MON |1-Month Calendar Digit (0~9)
+ * |[12] |TENMON |10-Month Calendar Digit (0~1)
+ * |[19:16] |YEAR |1-Year Calendar Digit (0~9)
+ * |[23:20] |TENYEAR |10-Year Calendar Digit (0~9)
+ * @var RTC_T::CLKFMT
+ * Offset: 0x14 RTC Time Scale Selection Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |24HEN |24-hour / 12-hour Time Scale Selection
+ * | | |Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale
+ * | | |0 = 12-hour time scale with AM and PM indication selected.
+ * | | |1 = 24-hour time scale selected.
+ * @var RTC_T::WEEKDAY
+ * Offset: 0x18 RTC Day of the Week Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |WEEKDAY |Day of the Week Register
+ * | | |000 = Sunday.
+ * | | |001 = Monday.
+ * | | |010 = Tuesday.
+ * | | |011 = Wednesday.
+ * | | |100 = Thursday.
+ * | | |101 = Friday.
+ * | | |110 = Saturday.
+ * | | |111 = Reserved.
+ * @var RTC_T::TALM
+ * Offset: 0x1C RTC Time Alarm Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |SEC |1-Sec Time Digit of Alarm Setting (0~9)
+ * |[6:4] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5)
+ * |[11:8] |MIN |1-Min Time Digit of Alarm Setting (0~9)
+ * |[14:12] |TENMIN |10-Min Time Digit of Alarm Setting (0~5)
+ * |[19:16] |HR |1-Hour Time Digit of Alarm Setting (0~9)
+ * |[21:20] |TENHR |10-Hour Time Digit of Alarm Setting (0~2)
+ * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication
+ * | | |(If RTC_TIME[21] is 1, it indicates PM time message).
+ * @var RTC_T::CALM
+ * Offset: 0x20 RTC Calendar Alarm Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |DAY |1-Day Calendar Digit of Alarm Setting (0~9)
+ * |[5:4] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3)
+ * |[11:8] |MON |1-Month Calendar Digit of Alarm Setting (0~9)
+ * |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1)
+ * |[19:16] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9)
+ * |[23:20] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9)
+ * @var RTC_T::LEAPYEAR
+ * Offset: 0x24 RTC Leap Year Indicator Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |LEAPYEAR |Leap Year Indication Register (Read Only)
+ * | | |0 = This year is not a leap year.
+ * | | |1 = This year is leap year.
+ * @var RTC_T::INTEN
+ * Offset: 0x28 RTC Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ALMIEN |Alarm Interrupt Enable Bit
+ * | | |Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated.
+ * | | |0 = RTC Alarm interrupt Disabled.
+ * | | |1 = RTC Alarm interrupt Enabled.
+ * |[1] |TICKIEN |Time Tick Interrupt Enable Bit
+ * | | |Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated.
+ * | | |0 = RTC Time Tick interrupt Disabled.
+ * | | |1 = RTC Time Tick interrupt Enabled.
+ * |[8] |TAMP0IEN |Tamper 0 Interrupt Enable Bit
+ * | | |Set TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated.
+ * | | |0 = Tamper 0 interrupt Disabled.
+ * | | |1 = Tamper 0 interrupt Enabled.
+ * |[9] |TAMP1IEN |Tamper 1 or Pair 0 Interrupt Enable Bit
+ * | | |Set TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated.
+ * | | |0 = Tamper 1 or Pair 0 interrupt Disabled.
+ * | | |1 = Tamper 1 or Pair 0 interrupt Enabled.
+ * |[10] |TAMP2IEN |Tamper 2 Interrupt Enable Bit
+ * | | |Set TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated.
+ * | | |0 = Tamper 2 interrupt Disabled.
+ * | | |1 = Tamper 2 interrupt Enabled.
+ * |[11] |TAMP3IEN |Tamper 3 or Pair 1 Interrupt Enable Bit
+ * | | |Set TAMP3IEN to 1 can also enable chip wake-up function when tamper 3 interrupt event is generated.
+ * | | |0 = Tamper 3 or Pair 1 interrupt Disabled.
+ * | | |1 = Tamper 3 or Pair 1 interrupt Enabled.
+ * |[12] |TAMP4IEN |Tamper 4 Interrupt Enable Bit
+ * | | |Set TAMP4IEN to 1 can also enable chip wake-up function when tamper 4 interrupt event is generated.
+ * | | |0 = Tamper 4 interrupt Disabled.
+ * | | |1 = Tamper 4 interrupt Enabled.
+ * |[13] |TAMP5IEN |Tamper 5 or Pair 2 Interrupt Enable Bit
+ * | | |Set TAMP5IEN to 1 can also enable chip wake-up function when tamper 5 interrupt event is generated.
+ * | | |0 = Tamper 5 or Pair 2 interrupt Disabled.
+ * | | |1 = Tamper 5 or Pair 2 interrupt Enabled.
+ * @var RTC_T::INTSTS
+ * Offset: 0x2C RTC Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ALMIF |RTC Alarm Interrupt Flag
+ * | | |0 = Alarm condition is not matched.
+ * | | |1 = Alarm condition is matched.
+ * | | |Note: Write 1 to clear this bit.
+ * |[1] |TICKIF |RTC Time Tick Interrupt Flag
+ * | | |0 = Tick condition does not occur.
+ * | | |1 = Tick condition occur.
+ * | | |Note: Write 1 to clear this bit.
+ * |[8] |TAMP0IF |Tamper 0 Interrupt Flag
+ * | | |This bit is set when TAMP0_PIN detected level non-equal TAMP0LV (RTC_TAMPCTL[9]).
+ * | | |0 = No Tamper 0 interrupt flag is generated.
+ * | | |1 = Tamper 0 interrupt flag is generated.
+ * | | |Note1: Write 1 to clear this bit.
+ * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
+ * |[9] |TAMP1IF |Tamper 1 or Pair 0 Interrupt Flag
+ * | | |This bit is set when TAMP1_PIN detected level non-equal TAMP1LV (RTC_TAMPCTL[13])
+ * | | |or TAMP0_PIN and TAMP1_PIN disconnected during DYNPR0EN (RTC_TAMPCTL[15]) is activated.
+ * | | |0 = No Tamper 1 or Pair 0 interrupt flag is generated.
+ * | | |1 = Tamper 1 or Pair 0 interrupt flag is generated.
+ * | | |Note1: Write 1 to clear this bit.
+ * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
+ * |[10] |TAMP2IF |Tamper 2 Interrupt Flag
+ * | | |This bit is set when TAMP2_PIN detected level non-equal TAMP2LV (RTC_TAMPCTL[17]).
+ * | | |0 = No Tamper 2 interrupt flag is generated.
+ * | | |1 = Tamper 2 interrupt flag is generated.
+ * | | |Note1: Write 1 to clear this bit.
+ * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
+ * |[11] |TAMP3IF |Tamper 3 or Pair 1 Interrupt Flag
+ * | | |This bit is set when TAMP3_PIN detected level non-equal TAMP3LV (RTC_TAMPCTL[21])
+ * | | |or TAMP2_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) is activated
+ * | | |or TAMP0_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) and DYN1ISS (RTC_TAMPCTL[0]) are activated.
+ * | | |0 = No Tamper 3 or Pair 1 interrupt flag is generated.
+ * | | |1 = Tamper 3 or Pair 1 interrupt flag is generated.
+ * | | |Note1: Write 1 to clear this bit.
+ * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
+ * |[12] |TAMP4IF |Tamper 4 Interrupt Flag
+ * | | |This bit is set when TAMP4_PIN detected level non-equal TAMP4LV (RTC_TAMPCTL[25]).
+ * | | |0 = No Tamper 4 interrupt flag is generated.
+ * | | |1 = Tamper 4 interrupt flag is generated.
+ * | | |Note1: Write 1 to clear this bit.
+ * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
+ * |[13] |TAMP5IF |Tamper 5 or Pair 2 Interrupt Flag
+ * | | |This bit is set when TAMP5_PIN detected level non-equal TAMP5LV (RTC_TAMPCTL[29])
+ * | | |or TAMP4_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) is activated
+ * | | |or TAMP0_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) and DYN2ISS (RTC_TAMPCTL[1]) are activated.
+ * | | |0 = No Tamper 5 or Pair 2 interrupt flag is generated.
+ * | | |1 = Tamper 5 or Pair 2 interrupt flag is generated.
+ * | | |Note1: Write 1 to clear this bit.
+ * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
+ * @var RTC_T::TICK
+ * Offset: 0x30 RTC Time Tick Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |TICK |Time Tick Register
+ * | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request.
+ * | | |000 = Time tick is 1 second.
+ * | | |001 = Time tick is 1/2 second.
+ * | | |010 = Time tick is 1/4 second.
+ * | | |011 = Time tick is 1/8 second.
+ * | | |100 = Time tick is 1/16 second.
+ * | | |101 = Time tick is 1/32 second.
+ * | | |110 = Time tick is 1/64 second.
+ * | | |111 = Time tick is 1/128 second.
+ * | | |Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active.
+ * @var RTC_T::TAMSK
+ * Offset: 0x34 RTC Time Alarm Mask Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9)
+ * |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5)
+ * |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9)
+ * |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5)
+ * |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9)
+ * |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2)
+ * @var RTC_T::CAMSK
+ * Offset: 0x38 RTC Calendar Alarm Mask Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9)
+ * |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3)
+ * |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9)
+ * |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1)
+ * |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9)
+ * |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9)
+ * @var RTC_T::SPRCTL
+ * Offset: 0x3C RTC Spare Functional Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2] |SPRRWEN |Spare Register Enable Bit
+ * | | |0 = Spare register is Disabled.
+ * | | |1 = Spare register is Enabled.
+ * | | |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed.
+ * |[5] |SPRCSTS |SPR Clear Flag
+ * | | |This bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify tamper event is detected.
+ * | | |0 = Spare register content is not cleared.
+ * | | |1 = Spare register content is cleared.
+ * | | |Writes 1 to clear this bit.
+ * | | |Note: This bit keep 1 when RTC_INTSTS[13:8] not equal zero.
+ * @var RTC_T::SPR[20]
+ * Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SPARE |Spare Register
+ * | | |This field is used to store back-up information defined by user.
+ * | | |This field will be cleared by hardware automatically once a tamper pin event is detected.
+ * | | |Before storing back-up information in to RTC_SPRx register,
+ * | | |user should check REWNF (RTC_RWEN[16]) is enabled.
+ * @var RTC_T::LXTCTL
+ * Offset: 0x100 RTC 32.768 kHz Oscillator Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:1] |GAIN |Oscillator Gain Option
+ * | | |User can select oscillator gain according to crystal external loading and operating temperature range
+ * | | |The larger gain value corresponding to stronger driving capability and higher power consumption.
+ * | | |00 = L0 mode.
+ * | | |01 = L1 mode.
+ * | | |10 = L2 mode.
+ * | | |11 = L3 mode.
+ * @var RTC_T::GPIOCTL0
+ * Offset: 0x104 RTC GPIO Control 0 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |OPMODE0 |IO Operation Mode
+ * | | |00 = PF.4 is input only mode, without pull-up resistor.
+ * | | |01 = PF.4 is output push pull mode.
+ * | | |10 = PF.4 is open drain mode.
+ * | | |11 = PF.4 is quasi-bidirectional mode with internal pull up.
+ * |[2] |DOUT0 |IO Output Data
+ * | | |0 = PF.4 output low.
+ * | | |1 = PF.4 output high.
+ * |[3] |CTLSEL0 |IO Pin State Backup Selection
+ * | | |When low speed 32 kHz oscillator is disabled, PF.4 pin (X32KO pin) can be used as GPIO function
+ * | | |User can program CTLSEL0 to decide PF.4 I/O function is controlled by system power domain GPIO module or
+ * | | |VBAT power domain RTC_GPIOCTL0 control register.
+ * | | |0 = PF.4 pin I/O function is controlled by GPIO module.
+ * | | |Hardware auto becomes CTLSEL0 = 1 when system power is turned off.
+ * | | |1 = PF.4 pin I/O function is controlled by VBAT power domain.
+ * | | |PF.4 pin function and I/O status are controlled by OPMODE0[1:0] and DOUT0 after CTLSEL0 is set to 1.
+ * | | |Note: CTLSEL0 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
+ * |[5:4] |PUSEL0 |IO Pull-up and Pull-down Enable
+ * | | |Determine PF.4 I/O pull-up or pull-down.
+ * | | |00 = PF.4 pull-up and pull-up disable.
+ * | | |01 = PF.4 pull-down enable.
+ * | | |10 = PF.4 pull-up enable.
+ * | | |11 = PF.4 pull-up and pull-up disable.
+ * | | |Note:
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation.
+ * | | |The independent pull-up control register only valid when OPMODE0 set as input tri-state and open-drain mode.
+ * | | |The independent pull-down control register only valid when OPMODE0 set as input tri-state mode.
+ * |[9:8] |OPMODE1 |IO Operation Mode
+ * | | |00 = PF.5 is input only mode, without pull-up resistor.
+ * | | |01 = PF.5 is output push pull mode.
+ * | | |10 = PF.5 is open drain mode.
+ * | | |11 = PF.5 is quasi-bidirectional mode with internal pull up.
+ * |[10] |DOUT1 |IO Output Data
+ * | | |0 = PF.5 output low.
+ * | | |1 = PF.5 output high.
+ * |[11] |CTLSEL1 |IO Pin State Backup Selection
+ * | | |When low speed 32 kHz oscillator is disabled, PF.5 pin (X32KI pin) can be used as GPIO function
+ * | | |User can program CTLSEL1 to decide PF.5 I/O function is controlled by system power domain GPIO module or
+ * | | |VBAT power domain RTC_GPIOCTL0 control register.
+ * | | |0 = PF.5 pin I/O function is controlled by GPIO module.
+ * | | |Hardware auto becomes CTLSEL1 = 1 when system power is turned off.
+ * | | |1 = PF.5 pin I/O function is controlled by VBAT power domain.
+ * | | |PF.5 pin function and I/O status are controlled by OPMODE1[1:0] and DOUT1 after CTLSEL1 is set to 1.
+ * | | |Note: CTLSEL1 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
+ * |[13:12] |PUSEL1 |IO Pull-up and Pull-down Enable
+ * | | |Determine PF.5 I/O pull-up or pull-down.
+ * | | |00 = PF.5 pull-up and pull-up disable.
+ * | | |01 = PF.5 pull-down enable.
+ * | | |10 = PF.5 pull-up enable.
+ * | | |11 = PF.5 pull-up and pull-up disable.
+ * | | |Note:
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation.
+ * | | |The independent pull-up control register only valid when OPMODE1 set as input tri-state and open-drain mode.
+ * | | |The independent pull-down control register only valid when OPMODE1 set as input tri-state mode.
+ * |[17:16] |OPMODE2 |IO Operation Mode
+ * | | |00 = PF.6 is input only mode, without pull-up resistor.
+ * | | |01 = PF.6 is output push pull mode.
+ * | | |10 = PF.6 is open drain mode.
+ * | | |11 = PF.6 is quasi-bidirectional mode with internal pull up.
+ * |[18] |DOUT2 |IO Output Data
+ * | | |0 = PF.6 output low.
+ * | | |1 = PF.6 output high.
+ * |[19] |CTLSEL2 |IO Pin State Backup Selection
+ * | | |When TAMP0EN is disabled, PF.6 pin (TAMPER0 pin) can be used as GPIO function
+ * | | |User can program CTLSEL2 to decide PF.6 I/O function is controlled by system power domain GPIO module or
+ * | | |VBAT power domain RTC_GPIOCTL0 control register.
+ * | | |0 = PF.6 pin I/O function is controlled by GPIO module.
+ * | | |Hardware auto becomes CTLSEL2 = 1 when system power is turned off.
+ * | | |1 = PF.6 pin I/O function is controlled by VBAT power domain.
+ * | | |PF.6 pin function and I/O status are controlled by OPMODE2[1:0] and DOUT2 after CTLSEL2 is set to 1.
+ * | | |Note: CTLSEL2 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
+ * |[21:20] |PUSEL2 |IO Pull-up and Pull-down Enable
+ * | | |Determine PF.6 I/O pull-up or pull-down.
+ * | | |00 = PF.6 pull-up and pull-up disable.
+ * | | |01 = PF.6 pull-down enable.
+ * | | |10 = PF.6 pull-up enable.
+ * | | |11 = PF.6 pull-up and pull-up disable.
+ * | | |Note1:
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation.
+ * | | |The independent pull-up control register only valid when OPMODE2 set as input tri-state and open-drain mode.
+ * | | |The independent pull-down control register only valid when OPMODE2 set as input tri-state mode.
+ * |[25:24] |OPMODE3 |IO Operation Mode
+ * | | |00 = PF.7 is input only mode, without pull-up resistor.
+ * | | |01 = PF.7 is output push pull mode.
+ * | | |10 = PF.7 is open drain mode.
+ * | | |11 = PF.7 is quasi-bidirectional mode.
+ * |[26] |DOUT3 |IO Output Data
+ * | | |0 = PF.7 output low.
+ * | | |1 = PF.7 output high.
+ * |[27] |CTLSEL3 |IO Pin State Backup Selection
+ * | | |When TAMP1EN is disabled, PF.7 pin (TAMPER1 pin) can be used as GPIO function
+ * | | |User can program CTLSEL3 to decide PF.7 I/O function is controlled by system power domain GPIO module or
+ * | | |VBAT power domain RTC_GPIOCTL0 control register.
+ * | | |0 = PF.7 pin I/O function is controlled by GPIO module.
+ * | | |Hardware auto becomes CTLSEL3 = 1 when system power is turned off.
+ * | | |1 = PF.7 pin I/O function is controlled by VBAT power domain.
+ * | | |PF.7 pin function and I/O status are controlled by OPMODE3[1:0] and DOUT3 after CTLSEL3 is set to 1.
+ * | | |Note: CTLSEL3 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.
+ * |[29:28] |PUSEL3 |IO Pull-up and Pull-down Enable
+ * | | |Determine PF.7 I/O pull-up or pull-down.
+ * | | |00 = PF.7 pull-up and pull-down disable.
+ * | | |01 = PF.7 pull-down enable.
+ * | | |10 = PF.7 pull-up enable.
+ * | | |11 = PF.7 pull-up and pull-down disable.
+ * | | |Note:
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation.
+ * | | |The independent pull-up control register only valid when OPMODE3 set as input tri-state and open-drain mode.
+ * | | |The independent pull-down control register only valid when OPMODE3 set as input tri-state mode.
+ * @var RTC_T::GPIOCTL1
+ * Offset: 0x108 RTC GPIO Control 1 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |OPMODE4 |IO Operation Mode
+ * | | |00 = PF.8 is input only mode, without pull-up resistor.
+ * | | |01 = PF.8 is output push pull mode.
+ * | | |10 = PF.8 is open drain mode.
+ * | | |11 = PF.8 is quasi-bidirectional mode.
+ * |[2] |DOUT4 |IO Output Data
+ * | | |0 = PF.8 output low.
+ * | | |1 = PF.8 output high.
+ * |[3] |CTLSEL4 |IO Pin State Backup Selection
+ * | | |When TAMP2EN is disabled, PF.8 pin (TAMPER2 pin) can be used as GPIO function
+ * | | |User can program CTLSEL4 to decide PF.8 I/O function is controlled by system power domain GPIO module or
+ * | | |VBAT power domain RTC_GPIOCTL1 control register.
+ * | | |0 = PF.8 pin I/O function is controlled by GPIO module.
+ * | | |Hardware auto becomes CTLSEL4 = 1 when system power is turned off.
+ * | | |1 = PF.8 pin I/O function is controlled by VBAT power domain.
+ * | | |PF.8 pin function and I/O status are controlled by OPMODE4[1:0] and DOUT4 after CTLSEL4 is set to 1.
+ * | | |Note: CTLSEL4 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.
+ * |[5:4] |PUSEL4 |IO Pull-up and Pull-down Enable
+ * | | |Determine PF.8 I/O pull-up or pull-down.
+ * | | |00 = PF.8 pull-up and pull-down disable.
+ * | | |01 = PF.8 pull-down enable.
+ * | | |10 = PF.8 pull-up enable.
+ * | | |11 = PF.8 pull-up and pull-down disable.
+ * | | |Note:
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation.
+ * | | |The independent pull-up control register only valid when OPMODE4 set as input tri-state and open-drain mode.
+ * | | |The independent pull-down control register only valid when OPMODE4 set as input tri-state mode.
+ * |[9:8] |OPMODE5 |IO Operation Mode
+ * | | |00 = PF.9 is input only mode, without pull-up resistor.
+ * | | |01 = PF.9 is output push pull mode.
+ * | | |10 = PF.9 is open drain mode.
+ * | | |11 = PF.9 is quasi-bidirectional mode.
+ * |[10] |DOUT5 |IO Output Data
+ * | | |0 = PF.9 output low.
+ * | | |1 = PF.9 output high.
+ * |[11] |CTLSEL5 |IO Pin State Backup Selection
+ * | | |When TAMP3EN is disabled, PF.9 pin (TAMPER3 pin) can be used as GPIO function
+ * | | |User can program CTLSEL5 to decide PF.9 I/O function is controlled by system power domain GPIO module or
+ * | | |VBAT power domain RTC_GPIOCTL1 control register.
+ * | | |0 = PF.9 pin I/O function is controlled by GPIO module.
+ * | | |Hardware auto becomes CTLSEL5 = 1 when system power is turned off.
+ * | | |1 = PF.9 pin I/O function is controlled by VBAT power domain.
+ * | | |PF.9 pin function and I/O status are controlled by OPMODE5[1:0] and DOUT5 after CTLSEL5 is set to 1.
+ * | | |Note: CTLSEL5 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
+ * |[13:12] |PUSEL5 |IO Pull-up and Pull-down Enable
+ * | | |Determine PF.9 I/O pull-up or pull-down.
+ * | | |00 = PF.9 pull-up and pull-down disable.
+ * | | |01 = PF.9 pull-down enable.
+ * | | |10 = PF.9 pull-up enable.
+ * | | |11 = PF.9 pull-up and pull-down disable.
+ * | | |Note:
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation.
+ * | | |The independent pull-up control register only valid when OPMODE5 set as input tri-state and open-drain mode.
+ * | | |The independent pull-down control register only valid when OPMODE5 set as input tri-state mode.
+ * |[17:16] |OPMODE6 |IO Operation Mode
+ * | | |00 = PF.10 is input only mode, without pull-up resistor.
+ * | | |01 = PF.10 is output push pull mode.
+ * | | |10 = PF.10 is open drain mode.
+ * | | |11 = PF.10 is quasi-bidirectional mode.
+ * |[18] |DOUT6 |IO Output Data
+ * | | |0 = PF.10 output low.
+ * | | |1 = PF.10 output high.
+ * |[19] |CTLSEL6 |IO Pin State Backup Selection
+ * | | |When TAMP4EN is disabled, PF.10 pin (TAMPER4 pin) can be used as GPIO function
+ * | | |User can program CTLSEL6 to decide PF.10 I/O function is controlled by system power domain GPIO module or
+ * | | |VBAT power domain RTC_GPIOCTL1 control register.
+ * | | |0 = PF.10 pin I/O function is controlled by GPIO module.
+ * | | |Hardware auto becomes CTLSEL6 = 1 when system power is turned off.
+ * | | |1 = PF.10 pin I/O function is controlled by VBAT power domain.
+ * | | |PF.10 pin function and I/O status are controlled by OPMODE6[1:0] and DOUT6 after CTLSEL6 is set to 1.
+ * | | |Note: CTLSEL6 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
+ * |[21:20] |PUSEL6 |IO Pull-up and Pull-down Enable
+ * | | |Determine PF.10 I/O pull-up or pull-down.
+ * | | |00 = PF.10 pull-up and pull-down disable.
+ * | | |01 = PF.10 pull-down enable.
+ * | | |10 = PF.10 pull-up enable.
+ * | | |11 = PF.10 pull-up and pull-down disable.
+ * | | |Note:
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation.
+ * | | |The independent pull-up control register only valid when OPMODE6 set as input tri-state and open-drain mode.
+ * | | |The independent pull-down control register only valid when OPMODE6 set as input tri-state mode.
+ * |[25:24] |OPMODE7 |IO Operation Mode
+ * | | |00 = PF.11 is input only mode, without pull-up resistor.
+ * | | |01 = PF.11 is output push pull mode.
+ * | | |10 = PF.11 is open drain mode.
+ * | | |11 = PF.11 is quasi-bidirectional mode.
+ * |[26] |DOUT7 |IO Output Data
+ * | | |0 = PF.11 output low.
+ * | | |1 = PF.11 output high.
+ * |[27] |CTLSEL7 |IO Pin State Backup Selection
+ * | | |When TAMP5EN is disabled, PF.11 pin (TAMPER5 pin) can be used as GPIO function
+ * | | |User can program CTLSEL7 to decide PF.11 I/O function is controlled by system power domain GPIO module or
+ * | | |VBAT power domain RTC_GPIOCTL1 control register.
+ * | | |0 = PF.11 pin I/O function is controlled by GPIO module.
+ * | | |Hardware auto becomes CTLSEL7 = 1 when system power is turned off.
+ * | | |1 = PF.11 pin I/O function is controlled by VBAT power domain.
+ * | | |PF.11 pin function and I/O status are controlled by OPMODE7[1:0] and DOUT7 after CTLSEL7 is set to 1.
+ * | | |Note: CTLSEL7 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
+ * |[29:28] |PUSEL7 |IO Pull-up and Pull-down Enable
+ * | | |Determine PF.11 I/O pull-up or pull-down.
+ * | | |00 = PF.11 pull-up and pull-down disable.
+ * | | |01 = PF.11 pull-down enable.
+ * | | |10 = PF.11 pull-up enable.
+ * | | |11 = PF.11 pull-up and pull-down disable.
+ * | | |Note:
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation.
+ * | | |The independent pull-up control register only valid when OPMODE7 set as input tri-state and open-drain mode.
+ * | | |The independent pull-down control register only valid when OPMODE7 set as input tri-state mode.
+ * @var RTC_T::DSTCTL
+ * Offset: 0x110 RTC Daylight Saving Time Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ADDHR |Add 1 Hour
+ * | | |0 = No effect.
+ * | | |1 = Indicates RTC hour digit has been added one hour for summer time change.
+ * |[1] |SUBHR |Subtract 1 Hour
+ * | | |0 = No effect.
+ * | | |1 = Indicates RTC hour digit has been subtracted one hour for winter time change.
+ * |[2] |DSBAK |Daylight Saving Back
+ * | | |0= Normal mode.
+ * | | |1= Daylight saving mode.
+ * @var RTC_T::TAMPCTL
+ * Offset: 0x120 RTC Tamper Pin Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |DYN1ISS |Dynamic Pair 1 Input Source Select
+ * | | |This bit determine Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode.
+ * | | |0 = Tamper input is from Tamper 2.
+ * | | |1 = Tamper input is from Tamper 0.
+ * | | |Note: This bit has effect only when DYNPR1EN (RTC_TAMPCTL[16]) and DYNPR0EN (RTC_TAMPCTL[15]) are set
+ * |[1] |DYN2ISS |Dynamic Pair 2 Input Source Select
+ * | | |This bit determine Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode.
+ * | | |0 = Tamper input is from Tamper 4.
+ * | | |1 = Tamper input is from Tamper 0.
+ * | | |Note: This bit has effect only when DYNPR2EN (RTC_TAMPCTL[24]) and DYNPR0EN (RTC_TAMPCTL[15]) are set
+ * |[3:2] |DYNSRC |Dynamic Reference Pattern
+ * | | |This fields determine the new reference pattern when current pattern run out in dynamic pair mode.
+ * | | |00 or 10 = The new reference pattern is generated by random number generator when the reference pattern run out.
+ * | | |01 = The new reference pattern is repeated previous random value when the reference pattern run out.
+ * | | |11 = The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out.
+ * | | |Note: After revise this bit, the SEEDRLD (RTC_TAMPCTL[4]) should be set.
+ * |[4] |SEEDRLD |Reload New Seed for PRNG Engine
+ * | | |Setting this bit, the tamper configuration will be reload.
+ * | | |0 = Generating key based on the current seed.
+ * | | |1 = Reload new seed.
+ * | | |Note: Before set this bit, the tamper configuration should be set to complete.
+ * |[7:5] |DYNRATE |Dynamic Change Rate
+ * | | |This item is choice the dynamic tamper output change rate.
+ * | | |000 = 210 * RTC_CLK.
+ * | | |001 = 211 * RTC_CLK.
+ * | | |010 = 212 * RTC_CLK.
+ * | | |011 = 213 * RTC_CLK.
+ * | | |100 = 214 * RTC_CLK.
+ * | | |101 = 215 * RTC_CLK.
+ * | | |110 = 216 * RTC_CLK.
+ * | | |111 = 217 * RTC_CLK.
+ * | | |Note: After revise this field, set SEEDRLD (RTC_TAMPCTL[4]) can reload change rate immediately.
+ * |[8] |TAMP0EN |Tamper0 Detect Enable Bit
+ * | | |0 = Tamper 0 detect Disabled.
+ * | | |1 = Tamper 0 detect Enabled.
+ * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
+ * |[9] |TAMP0LV |Tamper 0 Level
+ * | | |This bit depend on level attribute of tamper pin for static tamper detection.
+ * | | |0 = Detect voltage level is low.
+ * | | |1 = Detect voltage level is high.
+ * |[10] |TAMP0DBEN |Tamper 0 De-bounce Enable Bit
+ * | | |0 = Tamper 0 de-bounce Disabled.
+ * | | |1 = Tamper 0 de-bounce Enabled.
+ * |[12] |TAMP1EN |Tamper 1 Detect Enable Bit
+ * | | |0 = Tamper 1 detect Disabled.
+ * | | |1 = Tamper 1 detect Enabled.
+ * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
+ * |[13] |TAMP1LV |Tamper 1 Level
+ * | | |This bit depend on level attribute of tamper pin for static tamper detection.
+ * | | |0 = Detect voltage level is low.
+ * | | |1 = Detect voltage level is high.
+ * |[14] |TAMP1DBEN |Tamper 1 De-bounce Enable Bit
+ * | | |0 = Tamper 1 de-bounce Disabled.
+ * | | |1 = Tamper 1 de-bounce Enabled.
+ * |[15] |DYNPR0EN |Dynamic Pair 0 Enable Bit
+ * | | |0 = Static detect.
+ * | | |1 = Dynamic detect.
+ * |[16] |TAMP2EN |Tamper 2 Detect Enable Bit
+ * | | |0 = Tamper 2 detect Disabled.
+ * | | |1 = Tamper 2 detect Enabled.
+ * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
+ * |[17] |TAMP2LV |Tamper 2 Level
+ * | | |This bit depend on level attribute of tamper pin for static tamper detection.
+ * | | |0 = Detect voltage level is low.
+ * | | |1 = Detect voltage level is high.
+ * |[18] |TAMP2DBEN |Tamper 2 De-bounce Enable Bit
+ * | | |0 = Tamper 2 de-bounce Disabled.
+ * | | |1 = Tamper 2 de-bounce Enabled.
+ * |[20] |TAMP3EN |Tamper 3 Detect Enable Bit
+ * | | |0 = Tamper 3 detect Disabled.
+ * | | |1 = Tamper 3 detect Enabled.
+ * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
+ * |[21] |TAMP3LV |Tamper 3 Level
+ * | | |This bit depend on level attribute of tamper pin for static tamper detection.
+ * | | |0 = Detect voltage level is low.
+ * | | |1 = Detect voltage level is high.
+ * |[22] |TAMP3DBEN |Tamper 3 De-bounce Enable Bit
+ * | | |0 = Tamper 3 de-bounce Disabled.
+ * | | |1 = Tamper 3 de-bounce Enabled.
+ * |[23] |DYNPR1EN |Dynamic Pair 1 Enable Bit
+ * | | |0 = Static detect.
+ * | | |1 = Dynamic detect.
+ * |[24] |TAMP4EN |Tamper4 Detect Enable Bit
+ * | | |0 = Tamper 4 detect Disabled.
+ * | | |1 = Tamper 4 detect Enabled.
+ * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
+ * |[25] |TAMP4LV |Tamper 4 Level
+ * | | |This bit depends on level attribute of tamper pin for static tamper detection.
+ * | | |0 = Detect voltage level is low.
+ * | | |1 = Detect voltage level is high.
+ * |[26] |TAMP4DBEN |Tamper 4 De-bounce Enable Bit
+ * | | |0 = Tamper 4 de-bounce Disabled.
+ * | | |1 = Tamper 4 de-bounce Enabled.
+ * |[28] |TAMP5EN |Tamper 5 Detect Enable Bit
+ * | | |0 = Tamper 5 detect Disabled.
+ * | | |1 = Tamper 5 detect Enabled.
+ * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
+ * |[29] |TAMP5LV |Tamper 5 Level
+ * | | |This bit depend on level attribute of tamper pin for static tamper detection.
+ * | | |0 = Detect voltage level is low.
+ * | | |1 = Detect voltage level is high.
+ * |[30] |TAMP5DBEN |Tamper 5 De-bounce Enable Bit
+ * | | |0 = Tamper 5 de-bounce Disabled.
+ * | | |1 = Tamper 5 de-bounce Enabled.
+ * |[31] |DYNPR2EN |Dynamic Pair 2 Enable Bit
+ * | | |0 = Static detect.
+ * | | |1 = Dynamic detect.
+ * @var RTC_T::TAMPSEED
+ * Offset: 0x128 RTC Tamper Dynamic Seed Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SEED |Seed Value
+ * @var RTC_T::TAMPTIME
+ * Offset: 0x130 RTC Tamper Time Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |SEC |1-Sec Time Digit of TAMPER Time (0~9)
+ * |[6:4] |TENSEC |10-Sec Time Digit of TAMPER Time (0~5)
+ * |[11:8] |MIN |1-Min Time Digit of TAMPER Time (0~9)
+ * |[14:12] |TENMIN |10-Min Time Digit of TAMPER Time (0~5)
+ * |[19:16] |HR |1-Hour Time Digit of TAMPER Time (0~9)
+ * |[21:20] |TENHR |10-Hour Time Digit of TAMPER Time (0~2)
+ * | | |Note: 24-hour time scale only.
+ * @var RTC_T::TAMPCAL
+ * Offset: 0x134 RTC Tamper Calendar Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |DAY |1-Day Calendar Digit of TAMPER Calendar (0~9)
+ * |[5:4] |TENDAY |10-Day Calendar Digit of TAMPER Calendar (0~3)
+ * |[11:8] |MON |1-Month Calendar Digit of TAMPER Calendar (0~9)
+ * |[12] |TENMON |10-Month Calendar Digit of TAMPER Calendar (0~1)
+ * |[19:16] |YEAR |1-Year Calendar Digit of TAMPER Calendar (0~9)
+ * |[23:20] |TENYEAR |10-Year Calendar Digit of TAMPER Calendar (0~9)
+ */
+ __IO uint32_t INIT; /*!< [0x0000] RTC Initiation Register */
+ __IO uint32_t RWEN; /*!< [0x0004] RTC Access Enable Register */
+ __IO uint32_t FREQADJ; /*!< [0x0008] RTC Frequency Compensation Register */
+ __IO uint32_t TIME; /*!< [0x000c] RTC Time Loading Register */
+ __IO uint32_t CAL; /*!< [0x0010] RTC Calendar Loading Register */
+ __IO uint32_t CLKFMT; /*!< [0x0014] RTC Time Scale Selection Register */
+ __IO uint32_t WEEKDAY; /*!< [0x0018] RTC Day of the Week Register */
+ __IO uint32_t TALM; /*!< [0x001c] RTC Time Alarm Register */
+ __IO uint32_t CALM; /*!< [0x0020] RTC Calendar Alarm Register */
+ __I uint32_t LEAPYEAR; /*!< [0x0024] RTC Leap Year Indicator Register */
+ __IO uint32_t INTEN; /*!< [0x0028] RTC Interrupt Enable Register */
+ __IO uint32_t INTSTS; /*!< [0x002c] RTC Interrupt Status Register */
+ __IO uint32_t TICK; /*!< [0x0030] RTC Time Tick Register */
+ __IO uint32_t TAMSK; /*!< [0x0034] RTC Time Alarm Mask Register */
+ __IO uint32_t CAMSK; /*!< [0x0038] RTC Calendar Alarm Mask Register */
+ __IO uint32_t SPRCTL; /*!< [0x003c] RTC Spare Functional Control Register */
+ __IO uint32_t SPR[20]; /*!< [0x0040] ~ [0x008c] RTC Spare Register 0 ~ 19 */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE0[28];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t LXTCTL; /*!< [0x0100] RTC 32.768 kHz Oscillator Control Register */
+ __IO uint32_t GPIOCTL0; /*!< [0x0104] RTC GPIO Control 0 Register */
+ __IO uint32_t GPIOCTL1; /*!< [0x0108] RTC GPIO Control 1 Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE1[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t DSTCTL; /*!< [0x0110] RTC Daylight Saving Time Control Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE2[3];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t TAMPCTL; /*!< [0x0120] RTC Tamper Pin Control Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE3[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __IO uint32_t TAMPSEED; /*!< [0x0128] RTC Tamper Dynamic Seed Register */
+ /// @cond HIDDEN_SYMBOLS
+ __I uint32_t RESERVE4[1];
+ /// @endcond //HIDDEN_SYMBOLS
+ __I uint32_t TAMPTIME; /*!< [0x0130] RTC Tamper Time Register */
+ __I uint32_t TAMPCAL; /*!< [0x0134] RTC Tamper Calendar Register */
+
+} RTC_T;
+
+/**
+ @addtogroup RTC_CONST RTC Bit Field Definition
+ Constant Definitions for RTC Controller
+@{ */
+
+#define RTC_INIT_ACTIVE_Pos (0) /*!< RTC_T::INIT: INIT_ACTIVE Position */
+#define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) /*!< RTC_T::INIT: INIT_ACTIVE Mask */
+
+#define RTC_INIT_INIT_Pos (1) /*!< RTC_T::INIT: INIT Position */
+#define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) /*!< RTC_T::INIT: INIT Mask */
+
+#define RTC_RWEN_RWENF_Pos (16) /*!< RTC_T::RWEN: RWENF Position */
+#define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos) /*!< RTC_T::RWEN: RWENF Mask */
+
+#define RTC_RWEN_RTCBUSY_Pos (24) /*!< RTC_T::RWEN: RTCBUSY Position */
+#define RTC_RWEN_RTCBUSY_Msk (0x1ul << RTC_RWEN_RTCBUSY_Pos) /*!< RTC_T::RWEN: RTCBUSY Mask */
+
+#define RTC_FREQADJ_FREQADJ_Pos (0) /*!< RTC_T::FREQADJ: FREQADJ Position */
+#define RTC_FREQADJ_FREQADJ_Msk (0x3ffffful << RTC_FREQADJ_FREQADJ_Pos) /*!< RTC_T::FREQADJ: FREQADJ Mask */
+
+#define RTC_TIME_SEC_Pos (0) /*!< RTC_T::TIME: SEC Position */
+#define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC_T::TIME: SEC Mask */
+
+#define RTC_TIME_TENSEC_Pos (4) /*!< RTC_T::TIME: TENSEC Position */
+#define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC_T::TIME: TENSEC Mask */
+
+#define RTC_TIME_MIN_Pos (8) /*!< RTC_T::TIME: MIN Position */
+#define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC_T::TIME: MIN Mask */
+
+#define RTC_TIME_TENMIN_Pos (12) /*!< RTC_T::TIME: TENMIN Position */
+#define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC_T::TIME: TENMIN Mask */
+
+#define RTC_TIME_HR_Pos (16) /*!< RTC_T::TIME: HR Position */
+#define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC_T::TIME: HR Mask */
+
+#define RTC_TIME_TENHR_Pos (20) /*!< RTC_T::TIME: TENHR Position */
+#define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC_T::TIME: TENHR Mask */
+
+#define RTC_CAL_DAY_Pos (0) /*!< RTC_T::CAL: DAY Position */
+#define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC_T::CAL: DAY Mask */
+
+#define RTC_CAL_TENDAY_Pos (4) /*!< RTC_T::CAL: TENDAY Position */
+#define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC_T::CAL: TENDAY Mask */
+
+#define RTC_CAL_MON_Pos (8) /*!< RTC_T::CAL: MON Position */
+#define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC_T::CAL: MON Mask */
+
+#define RTC_CAL_TENMON_Pos (12) /*!< RTC_T::CAL: TENMON Position */
+#define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC_T::CAL: TENMON Mask */
+
+#define RTC_CAL_YEAR_Pos (16) /*!< RTC_T::CAL: YEAR Position */
+#define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC_T::CAL: YEAR Mask */
+
+#define RTC_CAL_TENYEAR_Pos (20) /*!< RTC_T::CAL: TENYEAR Position */
+#define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC_T::CAL: TENYEAR Mask */
+
+#define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC_T::CLKFMT: 24HEN Position */
+#define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC_T::CLKFMT: 24HEN Mask */
+
+#define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC_T::WEEKDAY: WEEKDAY Position */
+#define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC_T::WEEKDAY: WEEKDAY Mask */
+
+#define RTC_TALM_SEC_Pos (0) /*!< RTC_T::TALM: SEC Position */
+#define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC_T::TALM: SEC Mask */
+
+#define RTC_TALM_TENSEC_Pos (4) /*!< RTC_T::TALM: TENSEC Position */
+#define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC_T::TALM: TENSEC Mask */
+
+#define RTC_TALM_MIN_Pos (8) /*!< RTC_T::TALM: MIN Position */
+#define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC_T::TALM: MIN Mask */
+
+#define RTC_TALM_TENMIN_Pos (12) /*!< RTC_T::TALM: TENMIN Position */
+#define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC_T::TALM: TENMIN Mask */
+
+#define RTC_TALM_HR_Pos (16) /*!< RTC_T::TALM: HR Position */
+#define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC_T::TALM: HR Mask */
+
+#define RTC_TALM_TENHR_Pos (20) /*!< RTC_T::TALM: TENHR Position */
+#define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC_T::TALM: TENHR Mask */
+
+#define RTC_CALM_DAY_Pos (0) /*!< RTC_T::CALM: DAY Position */
+#define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC_T::CALM: DAY Mask */
+
+#define RTC_CALM_TENDAY_Pos (4) /*!< RTC_T::CALM: TENDAY Position */
+#define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC_T::CALM: TENDAY Mask */
+
+#define RTC_CALM_MON_Pos (8) /*!< RTC_T::CALM: MON Position */
+#define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC_T::CALM: MON Mask */
+
+#define RTC_CALM_TENMON_Pos (12) /*!< RTC_T::CALM: TENMON Position */
+#define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC_T::CALM: TENMON Mask */
+
+#define RTC_CALM_YEAR_Pos (16) /*!< RTC_T::CALM: YEAR Position */
+#define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC_T::CALM: YEAR Mask */
+
+#define RTC_CALM_TENYEAR_Pos (20) /*!< RTC_T::CALM: TENYEAR Position */
+#define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC_T::CALM: TENYEAR Mask */
+
+#define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC_T::LEAPYEAR: LEAPYEAR Position */
+#define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask */
+
+#define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC_T::INTEN: ALMIEN Position */
+#define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC_T::INTEN: ALMIEN Mask */
+
+#define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC_T::INTEN: TICKIEN Position */
+#define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC_T::INTEN: TICKIEN Mask */
+
+#define RTC_INTEN_TAMP0IEN_Pos (8) /*!< RTC_T::INTEN: TAMP0IEN Position */
+#define RTC_INTEN_TAMP0IEN_Msk (0x1ul << RTC_INTEN_TAMP0IEN_Pos) /*!< RTC_T::INTEN: TAMP0IEN Mask */
+
+#define RTC_INTEN_TAMP1IEN_Pos (9) /*!< RTC_T::INTEN: TAMP1IEN Position */
+#define RTC_INTEN_TAMP1IEN_Msk (0x1ul << RTC_INTEN_TAMP1IEN_Pos) /*!< RTC_T::INTEN: TAMP1IEN Mask */
+
+#define RTC_INTEN_TAMP2IEN_Pos (10) /*!< RTC_T::INTEN: TAMP2IEN Position */
+#define RTC_INTEN_TAMP2IEN_Msk (0x1ul << RTC_INTEN_TAMP2IEN_Pos) /*!< RTC_T::INTEN: TAMP2IEN Mask */
+
+#define RTC_INTEN_TAMP3IEN_Pos (11) /*!< RTC_T::INTEN: TAMP3IEN Position */
+#define RTC_INTEN_TAMP3IEN_Msk (0x1ul << RTC_INTEN_TAMP3IEN_Pos) /*!< RTC_T::INTEN: TAMP3IEN Mask */
+
+#define RTC_INTEN_TAMP4IEN_Pos (12) /*!< RTC_T::INTEN: TAMP4IEN Position */
+#define RTC_INTEN_TAMP4IEN_Msk (0x1ul << RTC_INTEN_TAMP4IEN_Pos) /*!< RTC_T::INTEN: TAMP4IEN Mask */
+
+#define RTC_INTEN_TAMP5IEN_Pos (13) /*!< RTC_T::INTEN: TAMP5IEN Position */
+#define RTC_INTEN_TAMP5IEN_Msk (0x1ul << RTC_INTEN_TAMP5IEN_Pos) /*!< RTC_T::INTEN: TAMP5IEN Mask */
+
+#define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC_T::INTSTS: ALMIF Position */
+#define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC_T::INTSTS: ALMIF Mask */
+
+#define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC_T::INTSTS: TICKIF Position */
+#define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC_T::INTSTS: TICKIF Mask */
+
+#define RTC_INTSTS_TAMP0IF_Pos (8) /*!< RTC_T::INTSTS: TAMP0IF Position */
+#define RTC_INTSTS_TAMP0IF_Msk (0x1ul << RTC_INTSTS_TAMP0IF_Pos) /*!< RTC_T::INTSTS: TAMP0IF Mask */
+
+#define RTC_INTSTS_TAMP1IF_Pos (9) /*!< RTC_T::INTSTS: TAMP1IF Position */
+#define RTC_INTSTS_TAMP1IF_Msk (0x1ul << RTC_INTSTS_TAMP1IF_Pos) /*!< RTC_T::INTSTS: TAMP1IF Mask */
+
+#define RTC_INTSTS_TAMP2IF_Pos (10) /*!< RTC_T::INTSTS: TAMP2IF Position */
+#define RTC_INTSTS_TAMP2IF_Msk (0x1ul << RTC_INTSTS_TAMP2IF_Pos) /*!< RTC_T::INTSTS: TAMP2IF Mask */
+
+#define RTC_INTSTS_TAMP3IF_Pos (11) /*!< RTC_T::INTSTS: TAMP3IF Position */
+#define RTC_INTSTS_TAMP3IF_Msk (0x1ul << RTC_INTSTS_TAMP3IF_Pos) /*!< RTC_T::INTSTS: TAMP3IF Mask */
+
+#define RTC_INTSTS_TAMP4IF_Pos (12) /*!< RTC_T::INTSTS: TAMP4IF Position */
+#define RTC_INTSTS_TAMP4IF_Msk (0x1ul << RTC_INTSTS_TAMP4IF_Pos) /*!< RTC_T::INTSTS: TAMP4IF Mask */
+
+#define RTC_INTSTS_TAMP5IF_Pos (13) /*!< RTC_T::INTSTS: TAMP5IF Position */
+#define RTC_INTSTS_TAMP5IF_Msk (0x1ul << RTC_INTSTS_TAMP5IF_Pos) /*!< RTC_T::INTSTS: TAMP5IF Mask */
+
+#define RTC_TICK_TICK_Pos (0) /*!< RTC_T::TICK: TICK Position */
+#define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) /*!< RTC_T::TICK: TICK Mask */
+
+#define RTC_TAMSK_MSEC_Pos (0) /*!< RTC_T::TAMSK: MSEC Position */
+#define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC_T::TAMSK: MSEC Mask */
+
+#define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC_T::TAMSK: MTENSEC Position */
+#define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC_T::TAMSK: MTENSEC Mask */
+
+#define RTC_TAMSK_MMIN_Pos (2) /*!< RTC_T::TAMSK: MMIN Position */
+#define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC_T::TAMSK: MMIN Mask */
+
+#define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC_T::TAMSK: MTENMIN Position */
+#define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC_T::TAMSK: MTENMIN Mask */
+
+#define RTC_TAMSK_MHR_Pos (4) /*!< RTC_T::TAMSK: MHR Position */
+#define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC_T::TAMSK: MHR Mask */
+
+#define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC_T::TAMSK: MTENHR Position */
+#define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC_T::TAMSK: MTENHR Mask */
+
+#define RTC_CAMSK_MDAY_Pos (0) /*!< RTC_T::CAMSK: MDAY Position */
+#define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC_T::CAMSK: MDAY Mask */
+
+#define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC_T::CAMSK: MTENDAY Position */
+#define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC_T::CAMSK: MTENDAY Mask */
+
+#define RTC_CAMSK_MMON_Pos (2) /*!< RTC_T::CAMSK: MMON Position */
+#define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC_T::CAMSK: MMON Mask */
+
+#define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC_T::CAMSK: MTENMON Position */
+#define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC_T::CAMSK: MTENMON Mask */
+
+#define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC_T::CAMSK: MYEAR Position */
+#define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC_T::CAMSK: MYEAR Mask */
+
+#define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC_T::CAMSK: MTENYEAR Position */
+#define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC_T::CAMSK: MTENYEAR Mask */
+
+#define RTC_SPRCTL_SPRRWEN_Pos (2) /*!< RTC_T::SPRCTL: SPRRWEN Position */
+#define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /*!< RTC_T::SPRCTL: SPRRWEN Mask */
+
+#define RTC_SPRCTL_SPRCSTS_Pos (5) /*!< RTC_T::SPRCTL: SPRCSTS Position */
+#define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) /*!< RTC_T::SPRCTL: SPRCSTS Mask */
+
+#define RTC_SPR0_SPARE_Pos (0) /*!< RTC_T::SPR0: SPARE Position */
+#define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos) /*!< RTC_T::SPR0: SPARE Mask */
+
+#define RTC_SPR1_SPARE_Pos (0) /*!< RTC_T::SPR1: SPARE Position */
+#define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos) /*!< RTC_T::SPR1: SPARE Mask */
+
+#define RTC_SPR2_SPARE_Pos (0) /*!< RTC_T::SPR2: SPARE Position */
+#define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos) /*!< RTC_T::SPR2: SPARE Mask */
+
+#define RTC_SPR3_SPARE_Pos (0) /*!< RTC_T::SPR3: SPARE Position */
+#define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos) /*!< RTC_T::SPR3: SPARE Mask */
+
+#define RTC_SPR4_SPARE_Pos (0) /*!< RTC_T::SPR4: SPARE Position */
+#define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos) /*!< RTC_T::SPR4: SPARE Mask */
+
+#define RTC_SPR5_SPARE_Pos (0) /*!< RTC_T::SPR5: SPARE Position */
+#define RTC_SPR5_SPARE_Msk (0xfffffffful << RTC_SPR5_SPARE_Pos) /*!< RTC_T::SPR5: SPARE Mask */
+
+#define RTC_SPR6_SPARE_Pos (0) /*!< RTC_T::SPR6: SPARE Position */
+#define RTC_SPR6_SPARE_Msk (0xfffffffful << RTC_SPR6_SPARE_Pos) /*!< RTC_T::SPR6: SPARE Mask */
+
+#define RTC_SPR7_SPARE_Pos (0) /*!< RTC_T::SPR7: SPARE Position */
+#define RTC_SPR7_SPARE_Msk (0xfffffffful << RTC_SPR7_SPARE_Pos) /*!< RTC_T::SPR7: SPARE Mask */
+
+#define RTC_SPR8_SPARE_Pos (0) /*!< RTC_T::SPR8: SPARE Position */
+#define RTC_SPR8_SPARE_Msk (0xfffffffful << RTC_SPR8_SPARE_Pos) /*!< RTC_T::SPR8: SPARE Mask */
+
+#define RTC_SPR9_SPARE_Pos (0) /*!< RTC_T::SPR9: SPARE Position */
+#define RTC_SPR9_SPARE_Msk (0xfffffffful << RTC_SPR9_SPARE_Pos) /*!< RTC_T::SPR9: SPARE Mask */
+
+#define RTC_SPR10_SPARE_Pos (0) /*!< RTC_T::SPR10: SPARE Position */
+#define RTC_SPR10_SPARE_Msk (0xfffffffful << RTC_SPR10_SPARE_Pos) /*!< RTC_T::SPR10: SPARE Mask */
+
+#define RTC_SPR11_SPARE_Pos (0) /*!< RTC_T::SPR11: SPARE Position */
+#define RTC_SPR11_SPARE_Msk (0xfffffffful << RTC_SPR11_SPARE_Pos) /*!< RTC_T::SPR11: SPARE Mask */
+
+#define RTC_SPR12_SPARE_Pos (0) /*!< RTC_T::SPR12: SPARE Position */
+#define RTC_SPR12_SPARE_Msk (0xfffffffful << RTC_SPR12_SPARE_Pos) /*!< RTC_T::SPR12: SPARE Mask */
+
+#define RTC_SPR13_SPARE_Pos (0) /*!< RTC_T::SPR13: SPARE Position */
+#define RTC_SPR13_SPARE_Msk (0xfffffffful << RTC_SPR13_SPARE_Pos) /*!< RTC_T::SPR13: SPARE Mask */
+
+#define RTC_SPR14_SPARE_Pos (0) /*!< RTC_T::SPR14: SPARE Position */
+#define RTC_SPR14_SPARE_Msk (0xfffffffful << RTC_SPR14_SPARE_Pos) /*!< RTC_T::SPR14: SPARE Mask */
+
+#define RTC_SPR15_SPARE_Pos (0) /*!< RTC_T::SPR15: SPARE Position */
+#define RTC_SPR15_SPARE_Msk (0xfffffffful << RTC_SPR15_SPARE_Pos) /*!< RTC_T::SPR15: SPARE Mask */
+
+#define RTC_SPR16_SPARE_Pos (0) /*!< RTC_T::SPR16: SPARE Position */
+#define RTC_SPR16_SPARE_Msk (0xfffffffful << RTC_SPR16_SPARE_Pos) /*!< RTC_T::SPR16: SPARE Mask */
+
+#define RTC_SPR17_SPARE_Pos (0) /*!< RTC_T::SPR17: SPARE Position */
+#define RTC_SPR17_SPARE_Msk (0xfffffffful << RTC_SPR17_SPARE_Pos) /*!< RTC_T::SPR17: SPARE Mask */
+
+#define RTC_SPR18_SPARE_Pos (0) /*!< RTC_T::SPR18: SPARE Position */
+#define RTC_SPR18_SPARE_Msk (0xfffffffful << RTC_SPR18_SPARE_Pos) /*!< RTC_T::SPR18: SPARE Mask */
+
+#define RTC_SPR19_SPARE_Pos (0) /*!< RTC_T::SPR19: SPARE Position */
+#define RTC_SPR19_SPARE_Msk (0xfffffffful << RTC_SPR19_SPARE_Pos) /*!< RTC_T::SPR19: SPARE Mask */
+
+#define RTC_LXTCTL_GAIN_Pos (1) /*!< RTC_T::LXTCTL: GAIN Position */
+#define RTC_LXTCTL_GAIN_Msk (0x3ul << RTC_LXTCTL_GAIN_Pos) /*!< RTC_T::LXTCTL: GAIN Mask */
+
+#define RTC_GPIOCTL0_OPMODE0_Pos (0) /*!< RTC_T::GPIOCTL0: OPMODE0 Position */
+#define RTC_GPIOCTL0_OPMODE0_Msk (0x3ul << RTC_GPIOCTL0_OPMODE0_Pos) /*!< RTC_T::GPIOCTL0: OPMODE0 Mask */
+
+#define RTC_GPIOCTL0_DOUT0_Pos (2) /*!< RTC_T::GPIOCTL0: DOUT0 Position */
+#define RTC_GPIOCTL0_DOUT0_Msk (0x1ul << RTC_GPIOCTL0_DOUT0_Pos) /*!< RTC_T::GPIOCTL0: DOUT0 Mask */
+
+#define RTC_GPIOCTL0_CTLSEL0_Pos (3) /*!< RTC_T::GPIOCTL0: CTLSEL0 Position */
+#define RTC_GPIOCTL0_CTLSEL0_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL0_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL0 Mask */
+
+#define RTC_GPIOCTL0_PUSEL0_Pos (4) /*!< RTC_T::GPIOCTL0: PUSEL0 Position */
+#define RTC_GPIOCTL0_PUSEL0_Msk (0x3ul << RTC_GPIOCTL0_PUSEL0_Pos) /*!< RTC_T::GPIOCTL0: PUSEL0 Mask */
+
+#define RTC_GPIOCTL0_OPMODE1_Pos (8) /*!< RTC_T::GPIOCTL0: OPMODE1 Position */
+#define RTC_GPIOCTL0_OPMODE1_Msk (0x3ul << RTC_GPIOCTL0_OPMODE1_Pos) /*!< RTC_T::GPIOCTL0: OPMODE1 Mask */
+
+#define RTC_GPIOCTL0_DOUT1_Pos (10) /*!< RTC_T::GPIOCTL0: DOUT1 Position */
+#define RTC_GPIOCTL0_DOUT1_Msk (0x1ul << RTC_GPIOCTL0_DOUT1_Pos) /*!< RTC_T::GPIOCTL0: DOUT1 Mask */
+
+#define RTC_GPIOCTL0_CTLSEL1_Pos (11) /*!< RTC_T::GPIOCTL0: CTLSEL1 Position */
+#define RTC_GPIOCTL0_CTLSEL1_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL1_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL1 Mask */
+
+#define RTC_GPIOCTL0_PUSEL1_Pos (12) /*!< RTC_T::GPIOCTL0: PUSEL1 Position */
+#define RTC_GPIOCTL0_PUSEL1_Msk (0x3ul << RTC_GPIOCTL0_PUSEL1_Pos) /*!< RTC_T::GPIOCTL0: PUSEL1 Mask */
+
+#define RTC_GPIOCTL0_OPMODE2_Pos (16) /*!< RTC_T::GPIOCTL0: OPMODE2 Position */
+#define RTC_GPIOCTL0_OPMODE2_Msk (0x3ul << RTC_GPIOCTL0_OPMODE2_Pos) /*!< RTC_T::GPIOCTL0: OPMODE2 Mask */
+
+#define RTC_GPIOCTL0_DOUT2_Pos (18) /*!< RTC_T::GPIOCTL0: DOUT2 Position */
+#define RTC_GPIOCTL0_DOUT2_Msk (0x1ul << RTC_GPIOCTL0_DOUT2_Pos) /*!< RTC_T::GPIOCTL0: DOUT2 Mask */
+
+#define RTC_GPIOCTL0_CTLSEL2_Pos (19) /*!< RTC_T::GPIOCTL0: CTLSEL2 Position */
+#define RTC_GPIOCTL0_CTLSEL2_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL2_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL2 Mask */
+
+#define RTC_GPIOCTL0_PUSEL2_Pos (20) /*!< RTC_T::GPIOCTL0: PUSEL2 Position */
+#define RTC_GPIOCTL0_PUSEL2_Msk (0x3ul << RTC_GPIOCTL0_PUSEL2_Pos) /*!< RTC_T::GPIOCTL0: PUSEL2 Mask */
+
+#define RTC_GPIOCTL0_OPMODE3_Pos (24) /*!< RTC_T::GPIOCTL0: OPMODE3 Position */
+#define RTC_GPIOCTL0_OPMODE3_Msk (0x3ul << RTC_GPIOCTL0_OPMODE3_Pos) /*!< RTC_T::GPIOCTL0: OPMODE3 Mask */
+
+#define RTC_GPIOCTL0_DOUT3_Pos (26) /*!< RTC_T::GPIOCTL0: DOUT3 Position */
+#define RTC_GPIOCTL0_DOUT3_Msk (0x1ul << RTC_GPIOCTL0_DOUT3_Pos) /*!< RTC_T::GPIOCTL0: DOUT3 Mask */
+
+#define RTC_GPIOCTL0_CTLSEL3_Pos (27) /*!< RTC_T::GPIOCTL0: CTLSEL3 Position */
+#define RTC_GPIOCTL0_CTLSEL3_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL3_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL3 Mask */
+
+#define RTC_GPIOCTL0_PUSEL3_Pos (28) /*!< RTC_T::GPIOCTL0: PUSEL3 Position */
+#define RTC_GPIOCTL0_PUSEL3_Msk (0x3ul << RTC_GPIOCTL0_PUSEL3_Pos) /*!< RTC_T::GPIOCTL0: PUSEL3 Mask */
+
+#define RTC_GPIOCTL1_OPMODE4_Pos (0) /*!< RTC_T::GPIOCTL1: OPMODE4 Position */
+#define RTC_GPIOCTL1_OPMODE4_Msk (0x3ul << RTC_GPIOCTL1_OPMODE4_Pos) /*!< RTC_T::GPIOCTL1: OPMODE4 Mask */
+
+#define RTC_GPIOCTL1_DOUT4_Pos (2) /*!< RTC_T::GPIOCTL1: DOUT4 Position */
+#define RTC_GPIOCTL1_DOUT4_Msk (0x1ul << RTC_GPIOCTL1_DOUT4_Pos) /*!< RTC_T::GPIOCTL1: DOUT4 Mask */
+
+#define RTC_GPIOCTL1_CTLSEL4_Pos (3) /*!< RTC_T::GPIOCTL1: CTLSEL4 Position */
+#define RTC_GPIOCTL1_CTLSEL4_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL4_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL4 Mask */
+
+#define RTC_GPIOCTL1_PUSEL4_Pos (4) /*!< RTC_T::GPIOCTL1: PUSEL4 Position */
+#define RTC_GPIOCTL1_PUSEL4_Msk (0x3ul << RTC_GPIOCTL1_PUSEL4_Pos) /*!< RTC_T::GPIOCTL1: PUSEL4 Mask */
+
+#define RTC_GPIOCTL1_OPMODE5_Pos (8) /*!< RTC_T::GPIOCTL1: OPMODE5 Position */
+#define RTC_GPIOCTL1_OPMODE5_Msk (0x3ul << RTC_GPIOCTL1_OPMODE5_Pos) /*!< RTC_T::GPIOCTL1: OPMODE5 Mask */
+
+#define RTC_GPIOCTL1_DOUT5_Pos (10) /*!< RTC_T::GPIOCTL1: DOUT5 Position */
+#define RTC_GPIOCTL1_DOUT5_Msk (0x1ul << RTC_GPIOCTL1_DOUT5_Pos) /*!< RTC_T::GPIOCTL1: DOUT5 Mask */
+
+#define RTC_GPIOCTL1_CTLSEL5_Pos (11) /*!< RTC_T::GPIOCTL1: CTLSEL5 Position */
+#define RTC_GPIOCTL1_CTLSEL5_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL5_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL5 Mask */
+
+#define RTC_GPIOCTL1_PUSEL5_Pos (12) /*!< RTC_T::GPIOCTL1: PUSEL5 Position */
+#define RTC_GPIOCTL1_PUSEL5_Msk (0x3ul << RTC_GPIOCTL1_PUSEL5_Pos) /*!< RTC_T::GPIOCTL1: PUSEL5 Mask */
+
+#define RTC_GPIOCTL1_OPMODE6_Pos (16) /*!< RTC_T::GPIOCTL1: OPMODE6 Position */
+#define RTC_GPIOCTL1_OPMODE6_Msk (0x3ul << RTC_GPIOCTL1_OPMODE6_Pos) /*!< RTC_T::GPIOCTL1: OPMODE6 Mask */
+
+#define RTC_GPIOCTL1_DOUT6_Pos (18) /*!< RTC_T::GPIOCTL1: DOUT6 Position */
+#define RTC_GPIOCTL1_DOUT6_Msk (0x1ul << RTC_GPIOCTL1_DOUT6_Pos) /*!< RTC_T::GPIOCTL1: DOUT6 Mask */
+
+#define RTC_GPIOCTL1_CTLSEL6_Pos (19) /*!< RTC_T::GPIOCTL1: CTLSEL6 Position */
+#define RTC_GPIOCTL1_CTLSEL6_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL6_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL6 Mask */
+
+#define RTC_GPIOCTL1_PUSEL6_Pos (20) /*!< RTC_T::GPIOCTL1: PUSEL6 Position */
+#define RTC_GPIOCTL1_PUSEL6_Msk (0x3ul << RTC_GPIOCTL1_PUSEL6_Pos) /*!< RTC_T::GPIOCTL1: PUSEL6 Mask */
+
+#define RTC_GPIOCTL1_OPMODE7_Pos (24) /*!< RTC_T::GPIOCTL1: OPMODE7 Position */
+#define RTC_GPIOCTL1_OPMODE7_Msk (0x3ul << RTC_GPIOCTL1_OPMODE7_Pos) /*!< RTC_T::GPIOCTL1: OPMODE7 Mask */
+
+#define RTC_GPIOCTL1_DOUT7_Pos (26) /*!< RTC_T::GPIOCTL1: DOUT7 Position */
+#define RTC_GPIOCTL1_DOUT7_Msk (0x1ul << RTC_GPIOCTL1_DOUT7_Pos) /*!< RTC_T::GPIOCTL1: DOUT7 Mask */
+
+#define RTC_GPIOCTL1_CTLSEL7_Pos (27) /*!< RTC_T::GPIOCTL1: CTLSEL7 Position */
+#define RTC_GPIOCTL1_CTLSEL7_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL7_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL7 Mask */
+
+#define RTC_GPIOCTL1_PUSEL7_Pos (28) /*!< RTC_T::GPIOCTL1: PUSEL7 Position */
+#define RTC_GPIOCTL1_PUSEL7_Msk (0x3ul << RTC_GPIOCTL1_PUSEL7_Pos) /*!< RTC_T::GPIOCTL1: PUSEL7 Mask */
+
+#define RTC_DSTCTL_ADDHR_Pos (0) /*!< RTC_T::DSTCTL: ADDHR Position */
+#define RTC_DSTCTL_ADDHR_Msk (0x1ul << RTC_DSTCTL_ADDHR_Pos) /*!< RTC_T::DSTCTL: ADDHR Mask */
+
+#define RTC_DSTCTL_SUBHR_Pos (1) /*!< RTC_T::DSTCTL: SUBHR Position */
+#define RTC_DSTCTL_SUBHR_Msk (0x1ul << RTC_DSTCTL_SUBHR_Pos) /*!< RTC_T::DSTCTL: SUBHR Mask */
+
+#define RTC_DSTCTL_DSBAK_Pos (2) /*!< RTC_T::DSTCTL: DSBAK Position */
+#define RTC_DSTCTL_DSBAK_Msk (0x1ul << RTC_DSTCTL_DSBAK_Pos) /*!< RTC_T::DSTCTL: DSBAK Mask */
+
+#define RTC_TAMPCTL_DYN1ISS_Pos (0) /*!< RTC_T::TAMPCTL: DYN1ISS Position */
+#define RTC_TAMPCTL_DYN1ISS_Msk (0x1ul << RTC_TAMPCTL_DYN1ISS_Pos) /*!< RTC_T::TAMPCTL: DYN1ISS Mask */
+
+#define RTC_TAMPCTL_DYN2ISS_Pos (1) /*!< RTC_T::TAMPCTL: DYN2ISS Position */
+#define RTC_TAMPCTL_DYN2ISS_Msk (0x1ul << RTC_TAMPCTL_DYN2ISS_Pos) /*!< RTC_T::TAMPCTL: DYN2ISS Mask */
+
+#define RTC_TAMPCTL_DYNSRC_Pos (2) /*!< RTC_T::TAMPCTL: DYNSRC Position */
+#define RTC_TAMPCTL_DYNSRC_Msk (0x3ul << RTC_TAMPCTL_DYNSRC_Pos) /*!< RTC_T::TAMPCTL: DYNSRC Mask */
+
+#define RTC_TAMPCTL_SEEDRLD_Pos (4) /*!< RTC_T::TAMPCTL: SEEDRLD Position */
+#define RTC_TAMPCTL_SEEDRLD_Msk (0x1ul << RTC_TAMPCTL_SEEDRLD_Pos) /*!< RTC_T::TAMPCTL: SEEDRLD Mask */
+
+#define RTC_TAMPCTL_DYNRATE_Pos (5) /*!< RTC_T::TAMPCTL: DYNRATE Position */
+#define RTC_TAMPCTL_DYNRATE_Msk (0x7ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< RTC_T::TAMPCTL: DYNRATE Mask */
+
+#define RTC_TAMPCTL_TAMP0EN_Pos (8) /*!< RTC_T::TAMPCTL: TAMP0EN Position */
+#define RTC_TAMPCTL_TAMP0EN_Msk (0x1ul << RTC_TAMPCTL_TAMP0EN_Pos) /*!< RTC_T::TAMPCTL: TAMP0EN Mask */
+
+#define RTC_TAMPCTL_TAMP0LV_Pos (9) /*!< RTC_T::TAMPCTL: TAMP0LV Position */
+#define RTC_TAMPCTL_TAMP0LV_Msk (0x1ul << RTC_TAMPCTL_TAMP0LV_Pos) /*!< RTC_T::TAMPCTL: TAMP0LV Mask */
+
+#define RTC_TAMPCTL_TAMP0DBEN_Pos (10) /*!< RTC_T::TAMPCTL: TAMP0DBEN Position */
+#define RTC_TAMPCTL_TAMP0DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP0DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP0DBEN Mask */
+
+#define RTC_TAMPCTL_TAMP1EN_Pos (12) /*!< RTC_T::TAMPCTL: TAMP1EN Position */
+#define RTC_TAMPCTL_TAMP1EN_Msk (0x1ul << RTC_TAMPCTL_TAMP1EN_Pos) /*!< RTC_T::TAMPCTL: TAMP1EN Mask */
+
+#define RTC_TAMPCTL_TAMP1LV_Pos (13) /*!< RTC_T::TAMPCTL: TAMP1LV Position */
+#define RTC_TAMPCTL_TAMP1LV_Msk (0x1ul << RTC_TAMPCTL_TAMP1LV_Pos) /*!< RTC_T::TAMPCTL: TAMP1LV Mask */
+
+#define RTC_TAMPCTL_TAMP1DBEN_Pos (14) /*!< RTC_T::TAMPCTL: TAMP1DBEN Position */
+#define RTC_TAMPCTL_TAMP1DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP1DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP1DBEN Mask */
+
+#define RTC_TAMPCTL_DYNPR0EN_Pos (15) /*!< RTC_T::TAMPCTL: DYNPR0EN Position */
+#define RTC_TAMPCTL_DYNPR0EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR0EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR0EN Mask */
+
+#define RTC_TAMPCTL_TAMP2EN_Pos (16) /*!< RTC_T::TAMPCTL: TAMP2EN Position */
+#define RTC_TAMPCTL_TAMP2EN_Msk (0x1ul << RTC_TAMPCTL_TAMP2EN_Pos) /*!< RTC_T::TAMPCTL: TAMP2EN Mask */
+
+#define RTC_TAMPCTL_TAMP2LV_Pos (17) /*!< RTC_T::TAMPCTL: TAMP2LV Position */
+#define RTC_TAMPCTL_TAMP2LV_Msk (0x1ul << RTC_TAMPCTL_TAMP2LV_Pos) /*!< RTC_T::TAMPCTL: TAMP2LV Mask */
+
+#define RTC_TAMPCTL_TAMP2DBEN_Pos (18) /*!< RTC_T::TAMPCTL: TAMP2DBEN Position */
+#define RTC_TAMPCTL_TAMP2DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP2DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP2DBEN Mask */
+
+#define RTC_TAMPCTL_TAMP3EN_Pos (20) /*!< RTC_T::TAMPCTL: TAMP3EN Position */
+#define RTC_TAMPCTL_TAMP3EN_Msk (0x1ul << RTC_TAMPCTL_TAMP3EN_Pos) /*!< RTC_T::TAMPCTL: TAMP3EN Mask */
+
+#define RTC_TAMPCTL_TAMP3LV_Pos (21) /*!< RTC_T::TAMPCTL: TAMP3LV Position */
+#define RTC_TAMPCTL_TAMP3LV_Msk (0x1ul << RTC_TAMPCTL_TAMP3LV_Pos) /*!< RTC_T::TAMPCTL: TAMP3LV Mask */
+
+#define RTC_TAMPCTL_TAMP3DBEN_Pos (22) /*!< RTC_T::TAMPCTL: TAMP3DBEN Position */
+#define RTC_TAMPCTL_TAMP3DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP3DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP3DBEN Mask */
+
+#define RTC_TAMPCTL_DYNPR1EN_Pos (23) /*!< RTC_T::TAMPCTL: DYNPR1EN Position */
+#define RTC_TAMPCTL_DYNPR1EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR1EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR1EN Mask */
+
+#define RTC_TAMPCTL_TAMP4EN_Pos (24) /*!< RTC_T::TAMPCTL: TAMP4EN Position */
+#define RTC_TAMPCTL_TAMP4EN_Msk (0x1ul << RTC_TAMPCTL_TAMP4EN_Pos) /*!< RTC_T::TAMPCTL: TAMP4EN Mask */
+
+#define RTC_TAMPCTL_TAMP4LV_Pos (25) /*!< RTC_T::TAMPCTL: TAMP4LV Position */
+#define RTC_TAMPCTL_TAMP4LV_Msk (0x1ul << RTC_TAMPCTL_TAMP4LV_Pos) /*!< RTC_T::TAMPCTL: TAMP4LV Mask */
+
+#define RTC_TAMPCTL_TAMP4DBEN_Pos (26) /*!< RTC_T::TAMPCTL: TAMP4DBEN Position */
+#define RTC_TAMPCTL_TAMP4DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP4DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP4DBEN Mask */
+
+#define RTC_TAMPCTL_TAMP5EN_Pos (28) /*!< RTC_T::TAMPCTL: TAMP5EN Position */
+#define RTC_TAMPCTL_TAMP5EN_Msk (0x1ul << RTC_TAMPCTL_TAMP5EN_Pos) /*!< RTC_T::TAMPCTL: TAMP5EN Mask */
+
+#define RTC_TAMPCTL_TAMP5LV_Pos (29) /*!< RTC_T::TAMPCTL: TAMP5LV Position */
+#define RTC_TAMPCTL_TAMP5LV_Msk (0x1ul << RTC_TAMPCTL_TAMP5LV_Pos) /*!< RTC_T::TAMPCTL: TAMP5LV Mask */
+
+#define RTC_TAMPCTL_TAMP5DBEN_Pos (30) /*!< RTC_T::TAMPCTL: TAMP5DBEN Position */
+#define RTC_TAMPCTL_TAMP5DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP5DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP5DBEN Mask */
+
+#define RTC_TAMPCTL_DYNPR2EN_Pos (31) /*!< RTC_T::TAMPCTL: DYNPR2EN Position */
+#define RTC_TAMPCTL_DYNPR2EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR2EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR2EN Mask */
+
+#define RTC_TAMPSEED_SEED_Pos (0) /*!< RTC_T::TAMPSEED: SEED Position */
+#define RTC_TAMPSEED_SEED_Msk (0xfffffffful << RTC_TAMPSEED_SEED_Pos) /*!< RTC_T::TAMPSEED: SEED Mask */
+
+#define RTC_TAMPTIME_SEC_Pos (0) /*!< RTC_T::TAMPTIME: SEC Position */
+#define RTC_TAMPTIME_SEC_Msk (0xful << RTC_TAMPTIME_SEC_Pos) /*!< RTC_T::TAMPTIME: SEC Mask */
+
+#define RTC_TAMPTIME_TENSEC_Pos (4) /*!< RTC_T::TAMPTIME: TENSEC Position */
+#define RTC_TAMPTIME_TENSEC_Msk (0x7ul << RTC_TAMPTIME_TENSEC_Pos) /*!< RTC_T::TAMPTIME: TENSEC Mask */
+
+#define RTC_TAMPTIME_MIN_Pos (8) /*!< RTC_T::TAMPTIME: MIN Position */
+#define RTC_TAMPTIME_MIN_Msk (0xful << RTC_TAMPTIME_MIN_Pos) /*!< RTC_T::TAMPTIME: MIN Mask */
+
+#define RTC_TAMPTIME_TENMIN_Pos (12) /*!< RTC_T::TAMPTIME: TENMIN Position */
+#define RTC_TAMPTIME_TENMIN_Msk (0x7ul << RTC_TAMPTIME_TENMIN_Pos) /*!< RTC_T::TAMPTIME: TENMIN Mask */
+
+#define RTC_TAMPTIME_HR_Pos (16) /*!< RTC_T::TAMPTIME: HR Position */
+#define RTC_TAMPTIME_HR_Msk (0xful << RTC_TAMPTIME_HR_Pos) /*!< RTC_T::TAMPTIME: HR Mask */
+
+#define RTC_TAMPTIME_TENHR_Pos (20) /*!< RTC_T::TAMPTIME: TENHR Position */
+#define RTC_TAMPTIME_TENHR_Msk (0x3ul << RTC_TAMPTIME_TENHR_Pos) /*!< RTC_T::TAMPTIME: TENHR Mask */
+
+#define RTC_TAMPCAL_DAY_Pos (0) /*!< RTC_T::TAMPCAL: DAY Position */
+#define RTC_TAMPCAL_DAY_Msk (0xful << RTC_TAMPCAL_DAY_Pos) /*!< RTC_T::TAMPCAL: DAY Mask */
+
+#define RTC_TAMPCAL_TENDAY_Pos (4) /*!< RTC_T::TAMPCAL: TENDAY Position */
+#define RTC_TAMPCAL_TENDAY_Msk (0x3ul << RTC_TAMPCAL_TENDAY_Pos) /*!< RTC_T::TAMPCAL: TENDAY Mask */
+
+#define RTC_TAMPCAL_MON_Pos (8) /*!< RTC_T::TAMPCAL: MON Position */
+#define RTC_TAMPCAL_MON_Msk (0xful << RTC_TAMPCAL_MON_Pos) /*!< RTC_T::TAMPCAL: MON Mask */
+
+#define RTC_TAMPCAL_TENMON_Pos (12) /*!< RTC_T::TAMPCAL: TENMON Position */
+#define RTC_TAMPCAL_TENMON_Msk (0x1ul << RTC_TAMPCAL_TENMON_Pos) /*!< RTC_T::TAMPCAL: TENMON Mask */
+
+#define RTC_TAMPCAL_YEAR_Pos (16) /*!< RTC_T::TAMPCAL: YEAR Position */
+#define RTC_TAMPCAL_YEAR_Msk (0xful << RTC_TAMPCAL_YEAR_Pos) /*!< RTC_T::TAMPCAL: YEAR Mask */
+
+#define RTC_TAMPCAL_TENYEAR_Pos (20) /*!< RTC_T::TAMPCAL: TENYEAR Position */
+#define RTC_TAMPCAL_TENYEAR_Msk (0xful << RTC_TAMPCAL_TENYEAR_Pos) /*!< RTC_T::TAMPCAL: TENYEAR Mask */
+
+
+/**@}*/ /* RTC_CONST */
+/**@}*/ /* end of RTC register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __RTC_REG_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Include/m480_sys_reg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Include/m480_sys_reg.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,3495 @@
+/**************************************************************************//**
+ * @file sys_reg.h
+ * @version V1.00
+ * @brief SYS register definition header file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/
+#ifndef __SYS_REG_H__
+#define __SYS_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup SYS System Manger Controller(SYS)
+ Memory Mapped Structure for SYS Controller
+@{ */
+
+typedef struct {
+
+
+ /**
+ * @var SYS_T::PDID
+ * Offset: 0x00 Part Device Identification Number Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |PDID |Part Device Identification Number (Read Only)
+ * | | |This register reflects device part number code
+ * | | |Software can read this register to identify which device is used.
+ * @var SYS_T::RSTSTS
+ * Offset: 0x04 System Reset Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PORF |POR Reset Flag
+ * | | |The POR reset flag is set by the "Reset Signal" from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.
+ * | | |0 = No reset from POR or CHIPRST.
+ * | | |1 = Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[1] |PINRF |NRESET Pin Reset Flag
+ * | | |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source.
+ * | | |0 = No reset from nRESET pin.
+ * | | |1 = Pin nRESET had issued the reset signal to reset the system.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[2] |WDTRF |WDT Reset Flag
+ * | | |The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.
+ * | | |0 = No reset from watchdog timer or window watchdog timer.
+ * | | |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system.
+ * | | |Note1: Write 1 to clear this bit to 0.
+ * | | |Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset
+ * | | |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
+ * |[3] |LVRF |LVR Reset Flag
+ * | | |The LVR reset flag is set by the "Reset Signal" from the Low Voltage Reset Controller to indicate the previous reset source.
+ * | | |0 = No reset from LVR.
+ * | | |1 = LVR controller had issued the reset signal to reset the system.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[4] |BODRF |BOD Reset Flag
+ * | | |The BOD reset flag is set by the "Reset Signal" from the Brown-Out Detector to indicate the previous reset source.
+ * | | |0 = No reset from BOD.
+ * | | |1 = The BOD had issued the reset signal to reset the system.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[5] |SYSRF |System Reset Flag
+ * | | |The system reset flag is set by the "Reset Signal" from the Cortex-M4 Core to indicate the previous reset source.
+ * | | |0 = No reset from Cortex-M4.
+ * | | |1 = The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[7] |CPURF |CPU Reset Flag
+ * | | |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC).
+ * | | |0 = No reset from CPU.
+ * | | |1 = The Cortex-M4 Core and FMC are reset by software setting CPURST to 1.
+ * | | |Note: Write to clear this bit to 0.
+ * |[8] |CPULKRF |CPU Lock-up Reset Flag
+ * | | |0 = No reset from CPU lock-up happened.
+ * | | |1 = The Cortex-M4 lock-up happened and chip is reset.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * | | |Note2: When CPU lock-up happened under ICE is connected, This flag will set to 1 but chip will not reset.
+ * @var SYS_T::IPRST0
+ * Offset: 0x08 Peripheral Reset Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CHIPRST |Chip One-shot Reset (Write Protect)
+ * | | |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
+ * | | |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.
+ * | | |About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2
+ * | | |0 = Chip normal operation.
+ * | | |1 = Chip one-shot reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[1] |CPURST |Processor Core One-shot Reset (Write Protect)
+ * | | |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.
+ * | | |0 = Processor core normal operation.
+ * | | |1 = Processor core one-shot reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[2] |PDMARST |PDMA Controller Reset (Write Protect)
+ * | | |Setting this bit to 1 will generate a reset signal to the PDMA
+ * | | |User needs to set this bit to 0 to release from reset state.
+ * | | |0 = PDMA controller normal operation.
+ * | | |1 = PDMA controller reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[3] |EBIRST |EBI Controller Reset (Write Protect)
+ * | | |Set this bit to 1 will generate a reset signal to the EBI
+ * | | |User needs to set this bit to 0 to release from the reset state.
+ * | | |0 = EBI controller normal operation.
+ * | | |1 = EBI controller reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[5] |EMACRST |EMAC Controller Reset (Write Protect)
+ * | | |Setting this bit to 1 will generate a reset signal to the EMAC controller
+ * | | |User needs to set this bit to 0 to release from the reset state.
+ * | | |0 = EMAC controller normal operation.
+ * | | |1 = EMAC controller reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[6] |SDH0RST |SDHOST0 Controller Reset (Write Protect)
+ * | | |Setting this bit to 1 will generate a reset signal to the SDHOST0 controller
+ * | | |User needs to set this bit to 0 to release from the reset state.
+ * | | |0 = SDHOST0 controller normal operation.
+ * | | |1 = SDHOST0 controller reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[7] |CRCRST |CRC Calculation Controller Reset (Write Protect)
+ * | | |Set this bit to 1 will generate a reset signal to the CRC calculation controller
+ * | | |User needs to set this bit to 0 to release from the reset state.
+ * | | |0 = CRC calculation controller normal operation.
+ * | | |1 = CRC calculation controller reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[10] |HSUSBDRST |HSUSBD Controller Reset (Write Protect)
+ * | | |Setting this bit to 1 will generate a reset signal to the HSUSBD controller
+ * | | |User needs to set this bit to 0 to release from the reset state.
+ * | | |0 = HSUSBD controller normal operation.
+ * | | |1 = HSUSBD controller reset.
+ * |[12] |CRPTRST |CRYPTO Controller Reset (Write Protect)
+ * | | |Setting this bit to 1 will generate a reset signal to the CRYPTO controller
+ * | | |User needs to set this bit to 0 to release from the reset state.
+ * | | |0 = CRYPTO controller normal operation.
+ * | | |1 = CRYPTO controller reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[14] |SPIMRST |SPIM Controller Reset
+ * | | |Setting this bit to 1 will generate a reset signal to the SPIM controller
+ * | | |User needs to set this bit to 0 to release from the reset state.
+ * | | |0 = SPIM controller normal operation.
+ * | | |1 = SPIM controller reset.
+ * |[16] |USBHRST |USBH Controller Reset (Write Protect)
+ * | | |Set this bit to 1 will generate a reset signal to the USBH controller
+ * | | |User needs to set this bit to 0 to release from the reset state.
+ * | | |0 = USBH controller normal operation.
+ * | | |1 = USBH controller reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[17] |SDH1RST |SDHOST1 Controller Reset (Write Protect)
+ * | | |Setting this bit to 1 will generate a reset signal to the SDHOST1 controller
+ * | | |User needs to set this bit to 0 to release from the reset state.
+ * | | |0 = SDHOST1 controller normal operation.
+ * | | |1 = SDHOST1 controller reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var SYS_T::IPRST1
+ * Offset: 0x0C Peripheral Reset Control Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |GPIORST |GPIO Controller Reset
+ * | | |0 = GPIO controller normal operation.
+ * | | |1 = GPIO controller reset.
+ * |[2] |TMR0RST |Timer0 Controller Reset
+ * | | |0 = Timer0 controller normal operation.
+ * | | |1 = Timer0 controller reset.
+ * |[3] |TMR1RST |Timer1 Controller Reset
+ * | | |0 = Timer1 controller normal operation.
+ * | | |1 = Timer1 controller reset.
+ * |[4] |TMR2RST |Timer2 Controller Reset
+ * | | |0 = Timer2 controller normal operation.
+ * | | |1 = Timer2 controller reset.
+ * |[5] |TMR3RST |Timer3 Controller Reset
+ * | | |0 = Timer3 controller normal operation.
+ * | | |1 = Timer3 controller reset.
+ * |[7] |ACMP01RST |Analog Comparator 0/1 Controller Reset
+ * | | |0 = Analog Comparator 0/1 controller normal operation.
+ * | | |1 = Analog Comparator 0/1 controller reset.
+ * |[8] |I2C0RST |I2C0 Controller Reset
+ * | | |0 = I2C0 controller normal operation.
+ * | | |1 = I2C0 controller reset.
+ * |[9] |I2C1RST |I2C1 Controller Reset
+ * | | |0 = I2C1 controller normal operation.
+ * | | |1 = I2C1 controller reset.
+ * |[10] |I2C2RST |I2C2 Controller Reset
+ * | | |0 = I2C2 controller normal operation.
+ * | | |1 = I2C2 controller reset.
+ * |[12] |QSPI0RST |QSPI0 Controller Reset
+ * | | |0 = QSPI0 controller normal operation.
+ * | | |1 = QSPI0 controller reset.
+ * |[13] |SPI0RST |SPI0 Controller Reset
+ * | | |0 = SPI0 controller normal operation.
+ * | | |1 = SPI0 controller reset.
+ * |[14] |SPI1RST |SPI1 Controller Reset
+ * | | |0 = SPI1 controller normal operation.
+ * | | |1 = SPI1 controller reset.
+ * |[15] |SPI2RST |SPI2 Controller Reset
+ * | | |0 = SPI2 controller normal operation.
+ * | | |1 = SPI2 controller reset.
+ * |[16] |UART0RST |UART0 Controller Reset
+ * | | |0 = UART0 controller normal operation.
+ * | | |1 = UART0 controller reset.
+ * |[17] |UART1RST |UART1 Controller Reset
+ * | | |0 = UART1 controller normal operation.
+ * | | |1 = UART1 controller reset.
+ * |[18] |UART2RST |UART2 Controller Reset
+ * | | |0 = UART2 controller normal operation.
+ * | | |1 = UART2 controller reset.
+ * |[19] |UART3RST |UART3 Controller Reset
+ * | | |0 = UART3 controller normal operation.
+ * | | |1 = UART3 controller reset.
+ * |[20] |UART4RST |UART4 Controller Reset
+ * | | |0 = UART4 controller normal operation.
+ * | | |1 = UART4 controller reset.
+ * |[21] |UART5RST |UART5 Controller Reset
+ * | | |0 = UART5 controller normal operation.
+ * | | |1 = UART5 controller reset.
+ * |[24] |CAN0RST |CAN0 Controller Reset
+ * | | |0 = CAN0 controller normal operation.
+ * | | |1 = CAN0 controller reset.
+ * |[25] |CAN1RST |CAN1 Controller Reset
+ * | | |0 = CAN1 controller normal operation.
+ * | | |1 = CAN1 controller reset.
+ * |[27] |USBDRST |USBD Controller Reset
+ * | | |0 = USBD controller normal operation.
+ * | | |1 = USBD controller reset.
+ * |[28] |EADCRST |EADC Controller Reset
+ * | | |0 = EADC controller normal operation.
+ * | | |1 = EADC controller reset.
+ * |[29] |I2S0RST |I2S0 Controller Reset
+ * | | |0 = I2S0 controller normal operation.
+ * | | |1 = I2S0 controller reset.
+ * @var SYS_T::IPRST2
+ * Offset: 0x10 Peripheral Reset Control Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SC0RST |SC0 Controller Reset
+ * | | |0 = SC0 controller normal operation.
+ * | | |1 = SC0 controller reset.
+ * |[1] |SC1RST |SC1 Controller Reset
+ * | | |0 = SC1 controller normal operation.
+ * | | |1 = SC1 controller reset.
+ * |[2] |SC2RST |SC2 Controller Reset
+ * | | |0 = SC2 controller normal operation.
+ * | | |1 = SC2 controller reset.
+ * |[6] |SPI3RST |SPI3 Controller Reset
+ * | | |0 = SPI3 controller normal operation.
+ * | | |1 = SPI3 controller reset.
+ * |[8] |USCI0RST |USCI0 Controller Reset
+ * | | |0 = USCI0 controller normal operation.
+ * | | |1 = USCI0 controller reset.
+ * |[9] |USCI1RST |USCI1 Controller Reset
+ * | | |0 = USCI1 controller normal operation.
+ * | | |1 = USCI1 controller reset.
+ * |[12] |DACRST |DAC Controller Reset
+ * | | |0 = DAC controller normal operation.
+ * | | |1 = DAC controller reset.
+ * |[16] |EPWM0RST |EPWM0 Controller Reset
+ * | | |0 = EPWM0 controller normal operation.
+ * | | |1 = EPWM0 controller reset.
+ * |[17] |EPWM1RST |EPWM1 Controller Reset
+ * | | |0 = EPWM1 controller normal operation.
+ * | | |1 = EPWM1 controller reset.
+ * |[18] |BPWM0RST |BPWM0 Controller Reset
+ * | | |0 = BPWM0 controller normal operation.
+ * | | |1 = BPWM0 controller reset.
+ * |[19] |BPWM1RST |BPWM1 Controller Reset
+ * | | |0 = BPWM1 controller normal operation.
+ * | | |1 = BPWM1 controller reset.
+ * |[22] |QEI0RST |QEI0 Controller Reset
+ * | | |0 = QEI0 controller normal operation.
+ * | | |1 = QEI0 controller reset.
+ * |[23] |QEI1RST |QEI1 Controller Reset
+ * | | |0 = QEI1 controller normal operation.
+ * | | |1 = QEI1 controller reset.
+ * |[26] |ECAP0RST |ECAP0 Controller Reset
+ * | | |0 = ECAP0 controller normal operation.
+ * | | |1 = ECAP0 controller reset.
+ * |[27] |ECAP1RST |ECAP1 Controller Reset
+ * | | |0 = ECAP1 controller normal operation.
+ * | | |1 = ECAP1 controller reset.
+ * |[30] |OPARST |OP Amplifier (OPA) Controller Reset
+ * | | |0 = OPA controller normal operation.
+ * | | |1 = OPA controller reset.
+ * @var SYS_T::BODCTL
+ * Offset: 0x18 Brown-Out Detector Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BODEN |Brown-out Detector Enable Bit (Write Protect)
+ * | | |The default value is set by flash controller user configuration register CBODEN(CONFIG0 [19]).
+ * | | |0 = Brown-out Detector function Disabled.
+ * | | |1 = Brown-out Detector function Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[3] |BODRSTEN |Brown-out Reset Enable Bit (Write Protect)
+ * | | |The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit .
+ * | | |0 = Brown-out INTERRUPT function Enabled.
+ * | | |1 = Brown-out RESET function Enabled.
+ * | | |Note1:
+ * | | |While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).
+ * | | |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high
+ * | | |BOD interrupt will keep till to the BODEN set to 0
+ * | | |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).
+ * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[4] |BODIF |Brown-out Detector Interrupt Flag
+ * | | |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting.
+ * | | |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[5] |BODLPM |Brown-out Detector Low Power Mode (Write Protect)
+ * | | |0 = BOD operate in normal mode (default).
+ * | | |1 = BOD Low Power mode Enabled.
+ * | | |Note1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
+ * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[6] |BODOUT |Brown-out Detector Output Status
+ * | | |0 = Brown-out Detector output status is 0.
+ * | | |It means the detected voltage is higher than BODVL setting or BODEN is 0.
+ * | | |1 = Brown-out Detector output status is 1.
+ * | | |It means the detected voltage is lower than BODVL setting
+ * | | |If the BODEN is 0, BOD function disabled , this bit always responds 0000.
+ * |[7] |LVREN |Low Voltage Reset Enable Bit (Write Protect)
+ * | | |The LVR function resets the chip when the input power voltage is lower than LVR circuit setting
+ * | | |LVR function is enabled by default.
+ * | | |0 = Low Voltage Reset function Disabled.
+ * | | |1 = Low Voltage Reset function Enabled.
+ * | | |Note1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default).
+ * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[10:8] |BODDGSEL |Brown-out Detector Output De-glitch Time Select (Write Protect)
+ * | | |000 = BOD output is sampled by RC10K clock.
+ * | | |001 = 4 system clock (HCLK).
+ * | | |010 = 8 system clock (HCLK).
+ * | | |011 = 16 system clock (HCLK).
+ * | | |100 = 32 system clock (HCLK).
+ * | | |101 = 64 system clock (HCLK).
+ * | | |110 = 128 system clock (HCLK).
+ * | | |111 = 256 system clock (HCLK).
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+ * |[14:12] |LVRDGSEL |LVR Output De-glitch Time Select (Write Protect)
+ * | | |000 = Without de-glitch function.
+ * | | |001 = 4 system clock (HCLK).
+ * | | |010 = 8 system clock (HCLK).
+ * | | |011 = 16 system clock (HCLK).
+ * | | |100 = 32 system clock (HCLK).
+ * | | |101 = 64 system clock (HCLK).
+ * | | |110 = 128 system clock (HCLK).
+ * | | |111 = 256 system clock (HCLK).
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+ * |[18:16] |BODVL |Brown-out Detector Threshold Voltage Selection (Write Protect)
+ * | | |The default value is set by flash controller user configuration register CBOV (CONFIG0 [23:21]).
+ * | | |000 = Brown-Out Detector threshold voltage is 1.6V.
+ * | | |001 = Brown-Out Detector threshold voltage is 1.8V.
+ * | | |010 = Brown-Out Detector threshold voltage is 2.0V.
+ * | | |011 = Brown-Out Detector threshold voltage is 2.2V.
+ * | | |100 = Brown-Out Detector threshold voltage is 2.4V.
+ * | | |101 = Brown-Out Detector threshold voltage is 2.6V.
+ * | | |110 = Brown-Out Detector threshold voltage is 2.8V.
+ * | | |111 = Brown-Out Detector threshold voltage is 3.0V.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var SYS_T::IVSCTL
+ * Offset: 0x1C Internal Voltage Source Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |VTEMPEN |Temperature Sensor Enable Bit
+ * | | |This bit is used to enable/disable temperature sensor function.
+ * | | |0 = Temperature sensor function Disabled (default).
+ * | | |1 = Temperature sensor function Enabled.
+ * | | |Note: After this bit is set to 1, the value of temperature sensor output can be obtained through GPC.9.
+ * |[1] |VBATUGEN |VBAT Unity Gain Buffer Enable Bit
+ * | | |This bit is used to enable/disable VBAT unity gain buffer function.
+ * | | |0 = VBAT unity gain buffer function Disabled (default).
+ * | | |1 = VBAT unity gain buffer function Enabled.
+ * | | |Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result
+ * @var SYS_T::PORCTL
+ * Offset: 0x24 Power-On-Reset Controller Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |POROFF |Power-on Reset Enable Bit (Write Protect)
+ * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again
+ * | | |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
+ * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
+ * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var SYS_T::VREFCTL
+ * Offset: 0x28 VREF Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[4:0] |VREFCTL |VREF Control Bits (Write Protect)
+ * | | |00000 = VREF is from external pin.
+ * | | |00011 = VREF is internal 1.6V.
+ * | | |00111 = VREF is internal 2.0V.
+ * | | |01011 = VREF is internal 2.5V.
+ * | | |01111 = VREF is internal 3.0V.
+ * | | |Others = Reserved.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[7:6] |PRELOAD_SEL|Pre-load Timing Selection.
+ * | | |00 = pre-load time is 60us for 0.1uF Capacitor.
+ * | | |01 = pre-load time is 310us for 1uF Capacitor.
+ * | | |10 = pre-load time is 1270us for 4.7uF Capacitor.
+ * | | |11 = pre-load time is 2650us for 10uF Capacitor.
+ * @var SYS_T::USBPHY
+ * Offset: 0x2C USB PHY Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |USBROLE |USB Role Option (Write Protect)
+ * | | |These two bits are used to select the role of USB.
+ * | | |00 = Standard USB Device mode.
+ * | | |01 = Standard USB Host mode.
+ * | | |10 = ID dependent mode.
+ * | | |11 = Reserved.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[2] |SBO |Note: This bit must always be kept 1. If set to 0, the result is unpredictable
+ * |[8] |USBEN |USB PHY Enable (Write Protect)
+ * | | |This bit is used to enable/disable USB PHY.
+ * | | |0 = USB PHY Disabled.
+ * | | |1 = USB PHY Enabled.
+ * |[17:16] |HSUSBROLE |HSUSB Role Option (Write Protect)
+ * | | |These two bits are used to select the role of HSUSB
+ * | | |00 = Standard HSUSB Device mode.
+ * | | |01 = Standard HSUSB Host mode.
+ * | | |10 = ID dependent mode.
+ * | | |11 = Reserved.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[24] |HSUSBEN |HSUSB PHY Enable (Write Protect)
+ * | | |This bit is used to enable/disable HSUSB PHY.
+ * | | |0 = HSUSB PHY Disabled.
+ * | | |1 = HSUSB PHY Enabled.
+ * |[25] |HSUSBACT |HSUSB PHY Active Control
+ * | | |This bit is used to control HSUSB PHY at reset state or active state.
+ * | | |0 = HSUSB PHY at reset state.
+ * | | |1 = HSUSB PHY at active state.
+ * | | |Note: After set HSUSBEN (SYS_USBPHY[24]) to enable HSUSB PHY, user should keep HSUSB PHY at reset mode at lease 10uS before changing to active mode.
+ * @var SYS_T::GPA_MFPL
+ * Offset: 0x30 GPIOA Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PA0MFP |PA.0 Multi-function Pin Selection
+ * |[7:4] |PA1MFP |PA.1 Multi-function Pin Selection
+ * |[11:8] |PA2MFP |PA.2 Multi-function Pin Selection
+ * |[15:12] |PA3MFP |PA.3 Multi-function Pin Selection
+ * |[19:16] |PA4MFP |PA.4 Multi-function Pin Selection
+ * |[23:20] |PA5MFP |PA.5 Multi-function Pin Selection
+ * |[27:24] |PA6MFP |PA.6 Multi-function Pin Selection
+ * |[31:28] |PA7MFP |PA.7 Multi-function Pin Selection
+ * @var SYS_T::GPA_MFPH
+ * Offset: 0x34 GPIOA High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PA8MFP |PA.8 Multi-function Pin Selection
+ * |[7:4] |PA9MFP |PA.9 Multi-function Pin Selection
+ * |[11:8] |PA10MFP |PA.10 Multi-function Pin Selection
+ * |[15:12] |PA11MFP |PA.11 Multi-function Pin Selection
+ * |[19:16] |PA12MFP |PA.12 Multi-function Pin Selection
+ * |[23:20] |PA13MFP |PA.13 Multi-function Pin Selection
+ * |[27:24] |PA14MFP |PA.14 Multi-function Pin Selection
+ * |[31:28] |PA15MFP |PA.15 Multi-function Pin Selection
+ * @var SYS_T::GPB_MFPL
+ * Offset: 0x38 GPIOB Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PB0MFP |PB.0 Multi-function Pin Selection
+ * |[7:4] |PB1MFP |PB.1 Multi-function Pin Selection
+ * |[11:8] |PB2MFP |PB.2 Multi-function Pin Selection
+ * |[15:12] |PB3MFP |PB.3 Multi-function Pin Selection
+ * |[19:16] |PB4MFP |PB.4 Multi-function Pin Selection
+ * |[23:20] |PB5MFP |PB.5 Multi-function Pin Selection
+ * |[27:24] |PB6MFP |PB.6 Multi-function Pin Selection
+ * |[31:28] |PB7MFP |PB.7 Multi-function Pin Selection
+ * @var SYS_T::GPB_MFPH
+ * Offset: 0x3C GPIOB High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PB8MFP |PB.8 Multi-function Pin Selection
+ * |[7:4] |PB9MFP |PB.9 Multi-function Pin Selection
+ * |[11:8] |PB10MFP |PB.10 Multi-function Pin Selection
+ * |[15:12] |PB11MFP |PB.11 Multi-function Pin Selection
+ * |[19:16] |PB12MFP |PB.12 Multi-function Pin Selection
+ * |[23:20] |PB13MFP |PB.13 Multi-function Pin Selection
+ * |[27:24] |PB14MFP |PB.14 Multi-function Pin Selection
+ * |[31:28] |PB15MFP |PB.15 Multi-function Pin Selection
+ * @var SYS_T::GPC_MFPL
+ * Offset: 0x40 GPIOC Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PC0MFP |PC.0 Multi-function Pin Selection
+ * |[7:4] |PC1MFP |PC.1 Multi-function Pin Selection
+ * |[11:8] |PC2MFP |PC.2 Multi-function Pin Selection
+ * |[15:12] |PC3MFP |PC.3 Multi-function Pin Selection
+ * |[19:16] |PC4MFP |PC.4 Multi-function Pin Selection
+ * |[23:20] |PC5MFP |PC.5 Multi-function Pin Selection
+ * |[27:24] |PC6MFP |PC.6 Multi-function Pin Selection
+ * |[31:28] |PC7MFP |PC.7 Multi-function Pin Selection
+ * @var SYS_T::GPC_MFPH
+ * Offset: 0x44 GPIOC High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PC8MFP |PC.8 Multi-function Pin Selection
+ * |[7:4] |PC9MFP |PC.9 Multi-function Pin Selection
+ * |[11:8] |PC10MFP |PC.10 Multi-function Pin Selection
+ * |[15:12] |PC11MFP |PC.11 Multi-function Pin Selection
+ * |[19:16] |PC12MFP |PC.12 Multi-function Pin Selection
+ * |[23:20] |PC13MFP |PC.13 Multi-function Pin Selection
+ * |[27:24] |PC14MFP |PC.14 Multi-function Pin Selection
+ * |[31:28] |PC15MFP |PC.15 Multi-function Pin Selection
+ * @var SYS_T::GPD_MFPL
+ * Offset: 0x48 GPIOD Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PD0MFP |PD.0 Multi-function Pin Selection
+ * |[7:4] |PD1MFP |PD.1 Multi-function Pin Selection
+ * |[11:8] |PD2MFP |PD.2 Multi-function Pin Selection
+ * |[15:12] |PD3MFP |PD.3 Multi-function Pin Selection
+ * |[19:16] |PD4MFP |PD.4 Multi-function Pin Selection
+ * |[23:20] |PD5MFP |PD.5 Multi-function Pin Selection
+ * |[27:24] |PD6MFP |PD.6 Multi-function Pin Selection
+ * |[31:28] |PD7MFP |PD.7 Multi-function Pin Selection
+ * @var SYS_T::GPD_MFPH
+ * Offset: 0x4C GPIOD High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PD8MFP |PD.8 Multi-function Pin Selection
+ * |[7:4] |PD9MFP |PD.9 Multi-function Pin Selection
+ * |[11:8] |PD10MFP |PD.10 Multi-function Pin Selection
+ * |[15:12] |PD11MFP |PD.11 Multi-function Pin Selection
+ * |[19:16] |PD12MFP |PD.12 Multi-function Pin Selection
+ * |[23:20] |PD13MFP |PD.13 Multi-function Pin Selection
+ * |[27:24] |PD14MFP |PD.14 Multi-function Pin Selection
+ * |[31:28] |PD15MFP |PD.15 Multi-function Pin Selection
+ * @var SYS_T::GPE_MFPL
+ * Offset: 0x50 GPIOE Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PE0MFP |PE.0 Multi-function Pin Selection
+ * |[7:4] |PE1MFP |PE.1 Multi-function Pin Selection
+ * |[11:8] |PE2MFP |PE.2 Multi-function Pin Selection
+ * |[15:12] |PE3MFP |PE.3 Multi-function Pin Selection
+ * |[19:16] |PE4MFP |PE.4 Multi-function Pin Selection
+ * |[23:20] |PE5MFP |PE.5 Multi-function Pin Selection
+ * |[27:24] |PE6MFP |PE.6 Multi-function Pin Selection
+ * |[31:28] |PE7MFP |PE.7 Multi-function Pin Selection
+ * @var SYS_T::GPE_MFPH
+ * Offset: 0x54 GPIOE High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PE8MFP |PE.8 Multi-function Pin Selection
+ * |[7:4] |PE9MFP |PE.9 Multi-function Pin Selection
+ * |[11:8] |PE10MFP |PE.10 Multi-function Pin Selection
+ * |[15:12] |PE11MFP |PE.11 Multi-function Pin Selection
+ * |[19:16] |PE12MFP |PE.12 Multi-function Pin Selection
+ * |[23:20] |PE13MFP |PE.13 Multi-function Pin Selection
+ * |[27:24] |PE14MFP |PE.14 Multi-function Pin Selection
+ * |[31:28] |PE15MFP |PE.15 Multi-function Pin Selection
+ * @var SYS_T::GPF_MFPL
+ * Offset: 0x58 GPIOF Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PF0MFP |PF.0 Multi-function Pin Selection
+ * |[7:4] |PF1MFP |PF.1 Multi-function Pin Selection
+ * |[11:8] |PF2MFP |PF.2 Multi-function Pin Selection
+ * |[15:12] |PF3MFP |PF.3 Multi-function Pin Selection
+ * |[19:16] |PF4MFP |PF.4 Multi-function Pin Selection
+ * |[23:20] |PF5MFP |PF.5 Multi-function Pin Selection
+ * |[27:24] |PF6MFP |PF.6 Multi-function Pin Selection
+ * |[31:28] |PF7MFP |PF.7 Multi-function Pin Selection
+ * @var SYS_T::GPF_MFPH
+ * Offset: 0x5C GPIOF High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PF8MFP |PF.8 Multi-function Pin Selection
+ * |[7:4] |PF9MFP |PF.9 Multi-function Pin Selection
+ * |[11:8] |PF10MFP |PF.10 Multi-function Pin Selection
+ * |[15:12] |PF11MFP |PF.11 Multi-function Pin Selection
+ * |[19:16] |PF12MFP |PF.12 Multi-function Pin Selection
+ * |[23:20] |PF13MFP |PF.13 Multi-function Pin Selection
+ * |[27:24] |PF14MFP |PF.14 Multi-function Pin Selection
+ * |[31:28] |PF15MFP |PF.15 Multi-function Pin Selection
+ * @var SYS_T::GPG_MFPL
+ * Offset: 0x60 GPIOG Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PG0MFP |PG.0 Multi-function Pin Selection
+ * |[7:4] |PG1MFP |PG.1 Multi-function Pin Selection
+ * |[11:8] |PG2MFP |PG.2 Multi-function Pin Selection
+ * |[15:12] |PG3MFP |PG.3 Multi-function Pin Selection
+ * |[19:16] |PG4MFP |PG.4 Multi-function Pin Selection
+ * |[23:20] |PG5MFP |PG.5 Multi-function Pin Selection
+ * |[27:24] |PG6MFP |PG.6 Multi-function Pin Selection
+ * |[31:28] |PG7MFP |PG.7 Multi-function Pin Selection
+ * @var SYS_T::GPG_MFPH
+ * Offset: 0x64 GPIOG High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PG8MFP |PG.8 Multi-function Pin Selection
+ * |[7:4] |PG9MFP |PG.9 Multi-function Pin Selection
+ * |[11:8] |PG10MFP |PG.10 Multi-function Pin Selection
+ * |[15:12] |PG11MFP |PG.11 Multi-function Pin Selection
+ * |[19:16] |PG12MFP |PG.12 Multi-function Pin Selection
+ * |[23:20] |PG13MFP |PG.13 Multi-function Pin Selection
+ * |[27:24] |PG14MFP |PG.14 Multi-function Pin Selection
+ * |[31:28] |PG15MFP |PG.15 Multi-function Pin Selection
+ * @var SYS_T::GPH_MFPL
+ * Offset: 0x68 GPIOH Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PH0MFP |PH.0 Multi-function Pin Selection
+ * |[7:4] |PH1MFP |PH.1 Multi-function Pin Selection
+ * |[11:8] |PH2MFP |PH.2 Multi-function Pin Selection
+ * |[15:12] |PH3MFP |PH.3 Multi-function Pin Selection
+ * |[19:16] |PH4MFP |PH.4 Multi-function Pin Selection
+ * |[23:20] |PH5MFP |PH.5 Multi-function Pin Selection
+ * |[27:24] |PH6MFP |PH.6 Multi-function Pin Selection
+ * |[31:28] |PH7MFP |PH.7 Multi-function Pin Selection
+ * @var SYS_T::GPH_MFPH
+ * Offset: 0x6C GPIOH High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PH8MFP |PH.8 Multi-function Pin Selection
+ * |[7:4] |PH9MFP |PH.9 Multi-function Pin Selection
+ * |[11:8] |PH10MFP |PH.10 Multi-function Pin Selection
+ * |[15:12] |PH11MFP |PH.11 Multi-function Pin Selection
+ * |[19:16] |PH12MFP |PH.12 Multi-function Pin Selection
+ * |[23:20] |PH13MFP |PH.13 Multi-function Pin Selection
+ * |[27:24] |PH14MFP |PH.14 Multi-function Pin Selection
+ * |[31:28] |PH15MFP |PH.15 Multi-function Pin Selection
+ * @var SYS_T::GPA_MFOS
+ * Offset: 0x80 GPIOA Multiple Function Output Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var SYS_T::GPB_MFOS
+ * Offset: 0x84 GPIOB Multiple Function Output Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var SYS_T::GPC_MFOS
+ * Offset: 0x88 GPIOC Multiple Function Output Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var SYS_T::GPD_MFOS
+ * Offset: 0x8C GPIOD Multiple Function Output Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var SYS_T::GPE_MFOS
+ * Offset: 0x90 GPIOE Multiple Function Output Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var SYS_T::GPF_MFOS
+ * Offset: 0x94 GPIOF Multiple Function Output Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var SYS_T::GPG_MFOS
+ * Offset: 0x98 GPIOG Multiple Function Output Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var SYS_T::GPH_MFOS
+ * Offset: 0x9C GPIOH Multiple Function Output Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.
+ * | | |Note:
+ * | | |Max. n=15 for port A/B/E/G.
+ * | | |Max. n=14 for port C/D.
+ * | | |Max. n=11 for port F/H.
+ * @var SYS_T::SRAM_INTCTL
+ * Offset: 0xC0 System SRAM Interrupt Enable Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PERRIEN |SRAM Parity Check Error Interrupt Enable Bit
+ * | | |0 = SRAM parity check error interrupt Disabled.
+ * | | |1 = SRAM parity check error interrupt Enabled.
+ * @var SYS_T::SRAM_STATUS
+ * Offset: 0xC4 System SRAM Parity Error Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PERRIF |SRAM Parity Check Error Flag
+ * | | |This bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0.
+ * | | |0 = No System SRAM parity error.
+ * | | |1 = System SRAM parity error occur.
+ * @var SYS_T::SRAM_ERRADDR
+ * Offset: 0xC8 System SRAM Parity Check Error Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ERRADDR |System SRAM Parity Error Address
+ * | | |This register shows system SRAM parity error byte address.
+ * @var SYS_T::SRAM_BISTCTL
+ * Offset: 0xD0 System SRAM BIST Test Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SRBIST0 |SRAM Bank0 BIST Enable Bit (Write Protect)
+ * | | |This bit enables BIST test for SRAM bank0.
+ * | | |0 = system SRAM bank0 BIST Disabled.
+ * | | |1 = system SRAM bank0 BIST Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[1] |SRBIST1 |SRAM Bank1 BIST Enable Bit (Write Protect)
+ * | | |This bit enables BIST test for SRAM bank1.
+ * | | |0 = system SRAM bank1 BIST Disabled.
+ * | | |1 = system SRAM bank1 BIST Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[2] |CRBIST |CACHE BIST Enable Bit (Write Protect)
+ * | | |This bit enables BIST test for CACHE RAM
+ * | | |0 = system CACHE BIST Disabled.
+ * | | |1 = system CACHE BIST Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[3] |CANBIST |CAN BIST Enable Bit (Write Protect)
+ * | | |This bit enables BIST test for CAN RAM
+ * | | |0 = system CAN BIST Disabled.
+ * | | |1 = system CAN BIST Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[4] |USBBIST |USB BIST Enable Bit (Write Protect)
+ * | | |This bit enables BIST test for USB RAM
+ * | | |0 = system USB BIST Disabled.
+ * | | |1 = system USB BIST Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[5] |SPIMBIST |SPIM BIST Enable Bit (Write Protect)
+ * | | |This bit enables BIST test for SPIM RAM
+ * | | |0 = system SPIM BIST Disabled.
+ * | | |1 = system SPIM BIST Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[6] |EMCBIST |EMC BIST Enable Bit (Write Protect)
+ * | | |This bit enables BIST test for EMC RAM
+ * | | |0 = system EMC BIST Disabled.
+ * | | |1 = system EMC BIST Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[7] |PDMABIST |PDMA BIST Enable Bit (Write Protect)
+ * | | |This bit enables BIST test for PDMA RAM
+ * | | |0 = system PDMA BIST Disabled.
+ * | | |1 = system PDMA BIST Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[8] |HSUSBDBIST|HSUSBD BIST Enable Bit (Write Protect)
+ * | | |This bit enables BIST test for HSUSBD RAM
+ * | | |0 = system HSUSBD BIST Disabled.
+ * | | |1 = system HSUSBD BIST Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[9] |HSUSBHBIST|HSUSBH BIST Enable Bit (Write Protect)
+ * | | |This bit enables BIST test for HSUSBH RAM
+ * | | |0 = system HSUSBH BIST Disabled.
+ * | | |1 = system HSUSBH BIST Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[16] |SRB0S0 |SRAM Bank0 Section 0 BIST Select (Write Protect)
+ * | | |This bit define if the first 16KB section of SRAM bank0 is selected or not when doing bist test.
+ * | | |0 = SRAM bank0 section 0 is deselected when doing bist test.
+ * | | |1 = SRAM bank0 section 0 is selected when doing bist test.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note: At least one section of SRAM bank0 should be selected when doing SRAM bank0 bist test.
+ * |[17] |SRB0S1 |SRAM Bank0 Section 1 BIST Select (Write Protect)
+ * | | |This bit define if the second 16KB section of SRAM bank0 is selected or not when doing bist test.
+ * | | |0 = SRAM bank0 section 1 is deselected when doing bist test.
+ * | | |1 = SRAM bank0 section 1 is selected when doing bist test.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note: At least one section of SRAM bank0 should be selected when doing SRAM bank0 bist test.
+ * |[18] |SRB1S0 |SRAM Bank1 Section 0 BIST Select (Write Protect)
+ * | | |This bit define if the first 16KB section of SRAM bank1 is selected or not when doing bist test.
+ * | | |0 = SRAM bank1 first 16KB section is deselected when doing bist test.
+ * | | |1 = SRAM bank1 first 16KB section is selected when doing bist test.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
+ * |[19] |SRB1S1 |SRAM Bank1 Section 1 BIST Select (Write Protect)
+ * | | |This bit define if the second 16KB section of SRAM bank1 is selected or not when doing bist test.
+ * | | |0 = SRAM bank1 second 16KB section is deselected when doing bist test.
+ * | | |1 = SRAM bank1 second 16KB section is selected when doing bist test.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
+ * |[20] |SRB1S2 |SRAM Bank1 Section 0 BIST Select (Write Protect)
+ * | | |This bit define if the third 16KB section of SRAM bank1 is selected or not when doing bist test.
+ * | | |0 = SRAM bank1 third 16KB section is deselected when doing bist test.
+ * | | |1 = SRAM bank1 third 16KB section is selected when doing bist test.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
+ * |[21] |SRB1S3 |SRAM Bank1 Section 1 BIST Select (Write Protect)
+ * | | |This bit define if the fourth 16KB section of SRAM bank1 is selected or not when doing bist test.
+ * | | |0 = SRAM bank1 fourth 16KB section is deselected when doing bist test.
+ * | | |1 = SRAM bank1 fourth 16KB section is selected when doing bist test.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
+ * |[22] |SRB1S4 |SRAM Bank1 Section 0 BIST Select (Write Protect)
+ * | | |This bit define if the fifth 16KB section of SRAM bank1 is selected or not when doing bist test.
+ * | | |0 = SRAM bank1 fifth 16KB section is deselected when doing bist test.
+ * | | |1 = SRAM bank1 fifth 16KB section is selected when doing bist test.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
+ * |[23] |SRB1S5 |SRAM Bank1 Section 1 BIST Select (Write Protect)
+ * | | |This bit define if the sixth 16KB section of SRAM bank1 is selected or not when doing bist test.
+ * | | |0 = SRAM bank1 sixth 16KB section is deselected when doing bist test.
+ * | | |1 = SRAM bank1 sixth 16KB section is selected when doing bist test.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
+ * @var SYS_T::SRAM_BISTSTS
+ * Offset: 0xD4 System SRAM BIST Test Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SRBISTEF0 |1st System SRAM BIST Fail Flag
+ * | | |0 = 1st system SRAM BIST test pass.
+ * | | |1 = 1st system SRAM BIST test fail.
+ * |[1] |SRBISTEF1 |2nd System SRAM BIST Fail Flag
+ * | | |0 = 2nd system SRAM BIST test pass.
+ * | | |1 = 2nd system SRAM BIST test fail.
+ * |[2] |CRBISTEF |CACHE SRAM BIST Fail Flag
+ * | | |0 = System CACHE RAM BIST test pass.
+ * | | |1 = System CACHE RAM BIST test fail.
+ * |[3] |CANBEF |CAN SRAM BIST Fail Flag
+ * | | |0 = CAN SRAM BIST test pass.
+ * | | |1 = CAN SRAM BIST test fail.
+ * |[4] |USBBEF |USB SRAM BIST Fail Flag
+ * | | |0 = USB SRAM BIST test pass.
+ * | | |1 = USB SRAM BIST test fail.
+ * |[16] |SRBEND0 |1st SRAM BIST Test Finish
+ * | | |0 = 1st system SRAM BIST active.
+ * | | |1 =1st system SRAM BIST finish.
+ * |[17] |SRBEND1 |2nd SRAM BIST Test Finish
+ * | | |0 = 2nd system SRAM BIST is active.
+ * | | |1 = 2nd system SRAM BIST finish.
+ * |[18] |CRBEND |CACHE SRAM BIST Test Finish
+ * | | |0 = System CACHE RAM BIST is active.
+ * | | |1 = System CACHE RAM BIST test finish.
+ * |[19] |CANBEND |CAN SRAM BIST Test Finish
+ * | | |0 = CAN SRAM BIST is active.
+ * | | |1 = CAN SRAM BIST test finish.
+ * |[20] |USBBEND |USB SRAM BIST Test Finish
+ * | | |0 = USB SRAM BIST is active.
+ * | | |1 = USB SRAM BIST test finish.
+ * @var SYS_T::IRCTCTL
+ * Offset: 0xF0 HIRC Trim Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |FREQSEL |Trim Frequency Selection
+ * | | |This field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC) auto trim.
+ * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
+ * | | |00 = Disable HIRC auto trim function.
+ * | | |01 = Enable HIRC auto trim function and trim HIRC to 12 MHz.
+ * | | |10 = Reserved..
+ * | | |11 = Reserved.
+ * |[5:4] |LOOPSEL |Trim Calculation Loop Selection
+ * | | |This field defines that trim value calculation is based on how many reference clocks.
+ * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock.
+ * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock.
+ * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock.
+ * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock.
+ * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
+ * |[7:6] |RETRYCNT |Trim Value Update Limitation Count
+ * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
+ * | | |Once the HIRC locked, the internal trim value update counter will be reset.
+ * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
+ * | | |00 = Trim retry count limitation is 64 loops.
+ * | | |01 = Trim retry count limitation is 128 loops.
+ * | | |10 = Trim retry count limitation is 256 loops.
+ * | | |11 = Trim retry count limitation is 512 loops.
+ * |[8] |CESTOPEN |Clock Error Stop Enable Bit
+ * | | |0 = The trim operation is keep going if clock is inaccuracy.
+ * | | |1 = The trim operation is stopped if clock is inaccuracy.
+ * |[10] |REFCKSEL |Reference Clock Selection
+ * | | |0 = HIRC trim reference from external 32.768 kHz crystal oscillator.
+ * | | |1 = HIRC trim reference from internal USB synchronous mode.
+ * | | |Note: HIRC trim reference clock is 20Khz in test mode.
+ * @var SYS_T::IRCTIEN
+ * Offset: 0xF4 HIRC Trim Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit
+ * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).
+ * | | |If this bit is high and TFAILIF(SYS_IRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
+ * | | |0 = Disable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU.
+ * | | |1 = Enable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU.
+ * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit
+ * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.
+ * | | |If this bit is set to1, and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
+ * | | |0 = Disable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU.
+ * | | |1 = Enable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU.
+ * @var SYS_T::IRCTISTS
+ * Offset: 0xF8 HIRC Trim Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |FREQLOCK |HIRC Frequency Lock Status
+ * | | |This bit indicates the HIRC frequency is locked.
+ * | | |This is a status bit and doesn't trigger any interrupt
+ * | | |Write 1 to clear this to 0
+ * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled.
+ * | | |0 = The internal high-speed oscillator frequency doesn't lock at 12 MHz yet.
+ * | | |1 = The internal high-speed oscillator frequency locked at 12 MHz.
+ * |[1] |TFAILIF |Trim Failure Interrupt Status
+ * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked
+ * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRCTCTL[1:0]) will be cleared to 00 by hardware automatically.
+ * | | |If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached
+ * | | |Write 1 to clear this to 0.
+ * | | |0 = Trim value update limitation count does not reach.
+ * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked.
+ * |[2] |CLKERRIF |Clock Error Interrupt Status
+ * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 12MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy.
+ * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1.
+ * | | |If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy.
+ * | | |Write 1 to clear this to 0.
+ * | | |0 = Clock frequency is accuracy.
+ * | | |1 = Clock frequency is inaccuracy.
+ * @var SYS_T::REGLCTL
+ * Offset: 0x100 Register Lock Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |REGLCTL |Register Lock Control Code
+ * | | |Some registers have write-protection function
+ * | | |Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field.
+ * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
+ * | | |Register Lock Control Code
+ * | | |0 = Write-protection Enabled for writing protected registers
+ * | | |Any write to the protected register is ignored.
+ * | | |1 = Write-protection Disabled for writing protected registers.
+ * @var SYS_T::PLCTL
+ * Offset: 0x1F8 Power Level Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |PLSEL |Power Level Select(Write Protect)
+ * | | |00 = Power level is PL0.
+ * | | |01 = Power level is PL1.
+ * | | |Others = Reserved.
+ * |[21:16] |LVSSTEP |LDO Voltage Scaling Step(Write Protect)
+ * | | |The LVSSTEP value is LDO voltage rising step.
+ * | | |Core voltage scaling voltage step = (LVSSTEP + 1) * 10mV.
+ * |[31:24] |LVSPRD |LDO Voltage Scaling Period(Write Protect)
+ * | | |The LVSPRD value is the period of each LDO voltage rising step.
+ * | | |LDO voltage scaling period = (LVSPRD + 1) * 1us.
+ * @var SYS_T::PLSTS
+ * Offset: 0x1FC Power Level Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PLCBUSY |Power Level Change Busy Bit (Read Only)
+ * | | |This bit is set by hardware when core voltage is changing
+ * | | |After core voltage change is completed, this bit will be cleared automatically by hardware.
+ * | | |0 = Core voltage change is completed.
+ * | | |1 = Core voltage change is ongoing.
+ * |[9:8] |PLSTATUS |Power Level Status (Read Only)
+ * | | |00 = Power level is PL0.
+ * | | |01 = Power level is PL1.
+ * | | |Others = Reserved.
+ * @var SYS_T::AHBMCTL
+ * Offset: 0x400 AHB Bus Matrix Priority Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |INTACTEN |Highest AHB Bus Priority of Cortex M4 Core Enable Bit (Write Protect)
+ * | | |Enable Cortex-M4 Core With Highest AHB Bus Priority In AHB Bus Matrix
+ * | | |0 = Run robin mode.
+ * | | |1 = Cortex-M4 CPU with highest bus priority when interrupt occurred.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ */
+ __I uint32_t PDID; /*!< [0x0000] Part Device Identification Number Register */
+ __IO uint32_t RSTSTS; /*!< [0x0004] System Reset Status Register */
+ __IO uint32_t IPRST0; /*!< [0x0008] Peripheral Reset Control Register 0 */
+ __IO uint32_t IPRST1; /*!< [0x000c] Peripheral Reset Control Register 1 */
+ __IO uint32_t IPRST2; /*!< [0x0010] Peripheral Reset Control Register 2 */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE0[1];
+ /** @endcond */
+ __IO uint32_t BODCTL; /*!< [0x0018] Brown-Out Detector Control Register */
+ __IO uint32_t IVSCTL; /*!< [0x001c] Internal Voltage Source Control Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE1[1];
+ /** @endcond */
+ __IO uint32_t PORCTL; /*!< [0x0024] Power-On-Reset Controller Register */
+ __IO uint32_t VREFCTL; /*!< [0x0028] VREF Control Register */
+ __IO uint32_t USBPHY; /*!< [0x002c] USB PHY Control Register */
+ __IO uint32_t GPA_MFPL; /*!< [0x0030] GPIOA Low Byte Multiple Function Control Register */
+ __IO uint32_t GPA_MFPH; /*!< [0x0034] GPIOA High Byte Multiple Function Control Register */
+ __IO uint32_t GPB_MFPL; /*!< [0x0038] GPIOB Low Byte Multiple Function Control Register */
+ __IO uint32_t GPB_MFPH; /*!< [0x003c] GPIOB High Byte Multiple Function Control Register */
+ __IO uint32_t GPC_MFPL; /*!< [0x0040] GPIOC Low Byte Multiple Function Control Register */
+ __IO uint32_t GPC_MFPH; /*!< [0x0044] GPIOC High Byte Multiple Function Control Register */
+ __IO uint32_t GPD_MFPL; /*!< [0x0048] GPIOD Low Byte Multiple Function Control Register */
+ __IO uint32_t GPD_MFPH; /*!< [0x004c] GPIOD High Byte Multiple Function Control Register */
+ __IO uint32_t GPE_MFPL; /*!< [0x0050] GPIOE Low Byte Multiple Function Control Register */
+ __IO uint32_t GPE_MFPH; /*!< [0x0054] GPIOE High Byte Multiple Function Control Register */
+ __IO uint32_t GPF_MFPL; /*!< [0x0058] GPIOF Low Byte Multiple Function Control Register */
+ __IO uint32_t GPF_MFPH; /*!< [0x005c] GPIOF High Byte Multiple Function Control Register */
+ __IO uint32_t GPG_MFPL; /*!< [0x0060] GPIOG Low Byte Multiple Function Control Register */
+ __IO uint32_t GPG_MFPH; /*!< [0x0064] GPIOG High Byte Multiple Function Control Register */
+ __IO uint32_t GPH_MFPL; /*!< [0x0068] GPIOH Low Byte Multiple Function Control Register */
+ __IO uint32_t GPH_MFPH; /*!< [0x006c] GPIOH High Byte Multiple Function Control Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE2[4];
+ /** @endcond */
+ __IO uint32_t GPA_MFOS; /*!< [0x0080] GPIOA Multiple Function Output Select Register */
+ __IO uint32_t GPB_MFOS; /*!< [0x0084] GPIOB Multiple Function Output Select Register */
+ __IO uint32_t GPC_MFOS; /*!< [0x0088] GPIOC Multiple Function Output Select Register */
+ __IO uint32_t GPD_MFOS; /*!< [0x008c] GPIOD Multiple Function Output Select Register */
+ __IO uint32_t GPE_MFOS; /*!< [0x0090] GPIOE Multiple Function Output Select Register */
+ __IO uint32_t GPF_MFOS; /*!< [0x0094] GPIOF Multiple Function Output Select Register */
+ __IO uint32_t GPG_MFOS; /*!< [0x0098] GPIOG Multiple Function Output Select Register */
+ __IO uint32_t GPH_MFOS; /*!< [0x009c] GPIOH Multiple Function Output Select Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE3[8];
+ /** @endcond */
+ __IO uint32_t SRAM_INTCTL; /*!< [0x00c0] System SRAM Interrupt Enable Control Register */
+ __IO uint32_t SRAM_STATUS; /*!< [0x00c4] System SRAM Parity Error Status Register */
+ __I uint32_t SRAM_ERRADDR; /*!< [0x00c8] System SRAM Parity Check Error Address Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE4[1];
+ /** @endcond */
+ __IO uint32_t SRAM_BISTCTL; /*!< [0x00d0] System SRAM BIST Test Control Register */
+ __I uint32_t SRAM_BISTSTS; /*!< [0x00d4] System SRAM BIST Test Status Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE5[6];
+ /** @endcond */
+ __IO uint32_t IRCTCTL; /*!< [0x00f0] HIRC Trim Control Register */
+ __IO uint32_t IRCTIEN; /*!< [0x00f4] HIRC Trim Interrupt Enable Register */
+ __IO uint32_t IRCTISTS; /*!< [0x00f8] HIRC Trim Interrupt Status Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE6[1];
+ /** @endcond */
+ __IO uint32_t REGLCTL; /*!< [0x0100] Register Lock Control Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE7[61];
+ /** @endcond */
+ __IO uint32_t PLCTL; /*!< [0x01f8] Power Level Control Register */
+ __I uint32_t PLSTS; /*!< [0x01fc] Power Level Status Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE8[128];
+ /** @endcond */
+ __IO uint32_t AHBMCTL; /*!< [0x0400] AHB Bus Matrix Priority Control Register */
+
+} SYS_T;
+
+/**
+ @addtogroup SYS_CONST SYS Bit Field Definition
+ Constant Definitions for SYS Controller
+@{ */
+
+#define SYS_PDID_PDID_Pos (0) /*!< SYS_T::PDID: PDID Position */
+#define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) /*!< SYS_T::PDID: PDID Mask */
+
+#define SYS_RSTSTS_PORF_Pos (0) /*!< SYS_T::RSTSTS: PORF Position */
+#define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /*!< SYS_T::RSTSTS: PORF Mask */
+
+#define SYS_RSTSTS_PINRF_Pos (1) /*!< SYS_T::RSTSTS: PINRF Position */
+#define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /*!< SYS_T::RSTSTS: PINRF Mask */
+
+#define SYS_RSTSTS_WDTRF_Pos (2) /*!< SYS_T::RSTSTS: WDTRF Position */
+#define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) /*!< SYS_T::RSTSTS: WDTRF Mask */
+
+#define SYS_RSTSTS_LVRF_Pos (3) /*!< SYS_T::RSTSTS: LVRF Position */
+#define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /*!< SYS_T::RSTSTS: LVRF Mask */
+
+#define SYS_RSTSTS_BODRF_Pos (4) /*!< SYS_T::RSTSTS: BODRF Position */
+#define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) /*!< SYS_T::RSTSTS: BODRF Mask */
+
+#define SYS_RSTSTS_SYSRF_Pos (5) /*!< SYS_T::RSTSTS: SYSRF Position */
+#define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) /*!< SYS_T::RSTSTS: SYSRF Mask */
+
+#define SYS_RSTSTS_CPURF_Pos (7) /*!< SYS_T::RSTSTS: CPURF Position */
+#define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) /*!< SYS_T::RSTSTS: CPURF Mask */
+
+#define SYS_RSTSTS_CPULKRF_Pos (8) /*!< SYS_T::RSTSTS: CPULKRF Position */
+#define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos) /*!< SYS_T::RSTSTS: CPULKRF Mask */
+
+#define SYS_IPRST0_CHIPRST_Pos (0) /*!< SYS_T::IPRST0: CHIPRST Position */
+#define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /*!< SYS_T::IPRST0: CHIPRST Mask */
+
+#define SYS_IPRST0_CPURST_Pos (1) /*!< SYS_T::IPRST0: CPURST Position */
+#define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) /*!< SYS_T::IPRST0: CPURST Mask */
+
+#define SYS_IPRST0_PDMARST_Pos (2) /*!< SYS_T::IPRST0: PDMARST Position */
+#define SYS_IPRST0_PDMARST_Msk (0x1ul << SYS_IPRST0_PDMARST_Pos) /*!< SYS_T::IPRST0: PDMARST Mask */
+
+#define SYS_IPRST0_EBIRST_Pos (3) /*!< SYS_T::IPRST0: EBIRST Position */
+#define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /*!< SYS_T::IPRST0: EBIRST Mask */
+
+#define SYS_IPRST0_EMACRST_Pos (5) /*!< SYS_T::IPRST0: EMACRST Position */
+#define SYS_IPRST0_EMACRST_Msk (0x1ul << SYS_IPRST0_EMACRST_Pos) /*!< SYS_T::IPRST0: EMACRST Mask */
+
+#define SYS_IPRST0_SDH0RST_Pos (6) /*!< SYS_T::IPRST0: SDH0RST Position */
+#define SYS_IPRST0_SDH0RST_Msk (0x1ul << SYS_IPRST0_SDH0RST_Pos) /*!< SYS_T::IPRST0: SDH0RST Mask */
+
+#define SYS_IPRST0_CRCRST_Pos (7) /*!< SYS_T::IPRST0: CRCRST Position */
+#define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) /*!< SYS_T::IPRST0: CRCRST Mask */
+
+#define SYS_IPRST0_HSUSBDRST_Pos (10) /*!< SYS_T::IPRST0: HSUSBDRST Position */
+#define SYS_IPRST0_HSUSBDRST_Msk (0x1ul << SYS_IPRST0_HSUSBDRST_Pos) /*!< SYS_T::IPRST0: HSUSBDRST Mask */
+
+#define SYS_IPRST0_CRPTRST_Pos (12) /*!< SYS_T::IPRST0: CRPTRST Position */
+#define SYS_IPRST0_CRPTRST_Msk (0x1ul << SYS_IPRST0_CRPTRST_Pos) /*!< SYS_T::IPRST0: CRPTRST Mask */
+
+#define SYS_IPRST0_SPIMRST_Pos (14) /*!< SYS_T::IPRST0: SPIMRST Position */
+#define SYS_IPRST0_SPIMRST_Msk (0x1ul << SYS_IPRST0_SPIMRST_Pos) /*!< SYS_T::IPRST0: SPIMRST Mask */
+
+#define SYS_IPRST0_USBHRST_Pos (16) /*!< SYS_T::IPRST0: USBHRST Position */
+#define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) /*!< SYS_T::IPRST0: USBHRST Mask */
+
+#define SYS_IPRST0_SDH1RST_Pos (17) /*!< SYS_T::IPRST0: SDH1RST Position */
+#define SYS_IPRST0_SDH1RST_Msk (0x1ul << SYS_IPRST0_SDH1RST_Pos) /*!< SYS_T::IPRST0: SDH1RST Mask */
+
+#define SYS_IPRST1_GPIORST_Pos (1) /*!< SYS_T::IPRST1: GPIORST Position */
+#define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) /*!< SYS_T::IPRST1: GPIORST Mask */
+
+#define SYS_IPRST1_TMR0RST_Pos (2) /*!< SYS_T::IPRST1: TMR0RST Position */
+#define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /*!< SYS_T::IPRST1: TMR0RST Mask */
+
+#define SYS_IPRST1_TMR1RST_Pos (3) /*!< SYS_T::IPRST1: TMR1RST Position */
+#define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /*!< SYS_T::IPRST1: TMR1RST Mask */
+
+#define SYS_IPRST1_TMR2RST_Pos (4) /*!< SYS_T::IPRST1: TMR2RST Position */
+#define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /*!< SYS_T::IPRST1: TMR2RST Mask */
+
+#define SYS_IPRST1_TMR3RST_Pos (5) /*!< SYS_T::IPRST1: TMR3RST Position */
+#define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /*!< SYS_T::IPRST1: TMR3RST Mask */
+
+#define SYS_IPRST1_ACMP01RST_Pos (7) /*!< SYS_T::IPRST1: ACMP01RST Position */
+#define SYS_IPRST1_ACMP01RST_Msk (0x1ul << SYS_IPRST1_ACMP01RST_Pos) /*!< SYS_T::IPRST1: ACMP01RST Mask */
+
+#define SYS_IPRST1_I2C0RST_Pos (8) /*!< SYS_T::IPRST1: I2C0RST Position */
+#define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /*!< SYS_T::IPRST1: I2C0RST Mask */
+
+#define SYS_IPRST1_I2C1RST_Pos (9) /*!< SYS_T::IPRST1: I2C1RST Position */
+#define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /*!< SYS_T::IPRST1: I2C1RST Mask */
+
+#define SYS_IPRST1_I2C2RST_Pos (10) /*!< SYS_T::IPRST1: I2C2RST Position */
+#define SYS_IPRST1_I2C2RST_Msk (0x1ul << SYS_IPRST1_I2C2RST_Pos) /*!< SYS_T::IPRST1: I2C2RST Mask */
+
+#define SYS_IPRST1_QSPI0RST_Pos (12) /*!< SYS_T::IPRST1: QSPI0RST Position */
+#define SYS_IPRST1_QSPI0RST_Msk (0x1ul << SYS_IPRST1_QSPI0RST_Pos) /*!< SYS_T::IPRST1: QSPI0RST Mask */
+
+#define SYS_IPRST1_SPI0RST_Pos (13) /*!< SYS_T::IPRST1: SPI0RST Position */
+#define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /*!< SYS_T::IPRST1: SPI0RST Mask */
+
+#define SYS_IPRST1_SPI1RST_Pos (14) /*!< SYS_T::IPRST1: SPI1RST Position */
+#define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) /*!< SYS_T::IPRST1: SPI1RST Mask */
+
+#define SYS_IPRST1_SPI2RST_Pos (15) /*!< SYS_T::IPRST1: SPI2RST Position */
+#define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) /*!< SYS_T::IPRST1: SPI2RST Mask */
+
+#define SYS_IPRST1_UART0RST_Pos (16) /*!< SYS_T::IPRST1: UART0RST Position */
+#define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /*!< SYS_T::IPRST1: UART0RST Mask */
+
+#define SYS_IPRST1_UART1RST_Pos (17) /*!< SYS_T::IPRST1: UART1RST Position */
+#define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /*!< SYS_T::IPRST1: UART1RST Mask */
+
+#define SYS_IPRST1_UART2RST_Pos (18) /*!< SYS_T::IPRST1: UART2RST Position */
+#define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /*!< SYS_T::IPRST1: UART2RST Mask */
+
+#define SYS_IPRST1_UART3RST_Pos (19) /*!< SYS_T::IPRST1: UART3RST Position */
+#define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) /*!< SYS_T::IPRST1: UART3RST Mask */
+
+#define SYS_IPRST1_UART4RST_Pos (20) /*!< SYS_T::IPRST1: UART4RST Position */
+#define SYS_IPRST1_UART4RST_Msk (0x1ul << SYS_IPRST1_UART4RST_Pos) /*!< SYS_T::IPRST1: UART4RST Mask */
+
+#define SYS_IPRST1_UART5RST_Pos (21) /*!< SYS_T::IPRST1: UART5RST Position */
+#define SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos) /*!< SYS_T::IPRST1: UART5RST Mask */
+
+#define SYS_IPRST1_CAN0RST_Pos (24) /*!< SYS_T::IPRST1: CAN0RST Position */
+#define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) /*!< SYS_T::IPRST1: CAN0RST Mask */
+
+#define SYS_IPRST1_CAN1RST_Pos (25) /*!< SYS_T::IPRST1: CAN1RST Position */
+#define SYS_IPRST1_CAN1RST_Msk (0x1ul << SYS_IPRST1_CAN1RST_Pos) /*!< SYS_T::IPRST1: CAN1RST Mask */
+
+#define SYS_IPRST1_USBDRST_Pos (27) /*!< SYS_T::IPRST1: USBDRST Position */
+#define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) /*!< SYS_T::IPRST1: USBDRST Mask */
+
+#define SYS_IPRST1_EADCRST_Pos (28) /*!< SYS_T::IPRST1: EADCRST Position */
+#define SYS_IPRST1_EADCRST_Msk (0x1ul << SYS_IPRST1_EADCRST_Pos) /*!< SYS_T::IPRST1: EADCRST Mask */
+
+#define SYS_IPRST1_I2S0RST_Pos (29) /*!< SYS_T::IPRST1: I2S0RST Position */
+#define SYS_IPRST1_I2S0RST_Msk (0x1ul << SYS_IPRST1_I2S0RST_Pos) /*!< SYS_T::IPRST1: I2S0RST Mask */
+
+#define SYS_IPRST2_SC0RST_Pos (0) /*!< SYS_T::IPRST2: SC0RST Position */
+#define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) /*!< SYS_T::IPRST2: SC0RST Mask */
+
+#define SYS_IPRST2_SC1RST_Pos (1) /*!< SYS_T::IPRST2: SC1RST Position */
+#define SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) /*!< SYS_T::IPRST2: SC1RST Mask */
+
+#define SYS_IPRST2_SC2RST_Pos (2) /*!< SYS_T::IPRST2: SC2RST Position */
+#define SYS_IPRST2_SC2RST_Msk (0x1ul << SYS_IPRST2_SC2RST_Pos) /*!< SYS_T::IPRST2: SC2RST Mask */
+
+#define SYS_IPRST2_SPI3RST_Pos (6) /*!< SYS_T::IPRST2: SPI3RST Position */
+#define SYS_IPRST2_SPI3RST_Msk (0x1ul << SYS_IPRST2_SPI3RST_Pos) /*!< SYS_T::IPRST2: SPI3RST Mask */
+
+#define SYS_IPRST2_USCI0RST_Pos (8) /*!< SYS_T::IPRST2: USCI0RST Position */
+#define SYS_IPRST2_USCI0RST_Msk (0x1ul << SYS_IPRST2_USCI0RST_Pos) /*!< SYS_T::IPRST2: USCI0RST Mask */
+
+#define SYS_IPRST2_USCI1RST_Pos (9) /*!< SYS_T::IPRST2: USCI1RST Position */
+#define SYS_IPRST2_USCI1RST_Msk (0x1ul << SYS_IPRST2_USCI1RST_Pos) /*!< SYS_T::IPRST2: USCI1RST Mask */
+
+#define SYS_IPRST2_DACRST_Pos (12) /*!< SYS_T::IPRST2: DACRST Position */
+#define SYS_IPRST2_DACRST_Msk (0x1ul << SYS_IPRST2_DACRST_Pos) /*!< SYS_T::IPRST2: DACRST Mask */
+
+#define SYS_IPRST2_EPWM0RST_Pos (16) /*!< SYS_T::IPRST2: EPWM0RST Position */
+#define SYS_IPRST2_EPWM0RST_Msk (0x1ul << SYS_IPRST2_EPWM0RST_Pos) /*!< SYS_T::IPRST2: EPWM0RST Mask */
+
+#define SYS_IPRST2_EPWM1RST_Pos (17) /*!< SYS_T::IPRST2: EPWM1RST Position */
+#define SYS_IPRST2_EPWM1RST_Msk (0x1ul << SYS_IPRST2_EPWM1RST_Pos) /*!< SYS_T::IPRST2: EPWM1RST Mask */
+
+#define SYS_IPRST2_BPWM0RST_Pos (18) /*!< SYS_T::IPRST2: BPWM0RST Position */
+#define SYS_IPRST2_BPWM0RST_Msk (0x1ul << SYS_IPRST2_BPWM0RST_Pos) /*!< SYS_T::IPRST2: BPWM0RST Mask */
+
+#define SYS_IPRST2_BPWM1RST_Pos (19) /*!< SYS_T::IPRST2: BPWM1RST Position */
+#define SYS_IPRST2_BPWM1RST_Msk (0x1ul << SYS_IPRST2_BPWM1RST_Pos) /*!< SYS_T::IPRST2: BPWM1RST Mask */
+
+#define SYS_IPRST2_QEI0RST_Pos (22) /*!< SYS_T::IPRST2: QEI0RST Position */
+#define SYS_IPRST2_QEI0RST_Msk (0x1ul << SYS_IPRST2_QEI0RST_Pos) /*!< SYS_T::IPRST2: QEI0RST Mask */
+
+#define SYS_IPRST2_QEI1RST_Pos (23) /*!< SYS_T::IPRST2: QEI1RST Position */
+#define SYS_IPRST2_QEI1RST_Msk (0x1ul << SYS_IPRST2_QEI1RST_Pos) /*!< SYS_T::IPRST2: QEI1RST Mask */
+
+#define SYS_IPRST2_ECAP0RST_Pos (26) /*!< SYS_T::IPRST2: ECAP0RST Position */
+#define SYS_IPRST2_ECAP0RST_Msk (0x1ul << SYS_IPRST2_ECAP0RST_Pos) /*!< SYS_T::IPRST2: ECAP0RST Mask */
+
+#define SYS_IPRST2_ECAP1RST_Pos (27) /*!< SYS_T::IPRST2: ECAP1RST Position */
+#define SYS_IPRST2_ECAP1RST_Msk (0x1ul << SYS_IPRST2_ECAP1RST_Pos) /*!< SYS_T::IPRST2: ECAP1RST Mask */
+
+#define SYS_IPRST2_OPARST_Pos (30) /*!< SYS_T::IPRST2: OPARST Position */
+#define SYS_IPRST2_OPARST_Msk (0x1ul << SYS_IPRST2_OPARST_Pos) /*!< SYS_T::IPRST2: OPARST Mask */
+
+#define SYS_BODCTL_BODEN_Pos (0) /*!< SYS_T::BODCTL: BODEN Position */
+#define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) /*!< SYS_T::BODCTL: BODEN Mask */
+
+#define SYS_BODCTL_BODRSTEN_Pos (3) /*!< SYS_T::BODCTL: BODRSTEN Position */
+#define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) /*!< SYS_T::BODCTL: BODRSTEN Mask */
+
+#define SYS_BODCTL_BODIF_Pos (4) /*!< SYS_T::BODCTL: BODIF Position */
+#define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) /*!< SYS_T::BODCTL: BODIF Mask */
+
+#define SYS_BODCTL_BODLPM_Pos (5) /*!< SYS_T::BODCTL: BODLPM Position */
+#define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) /*!< SYS_T::BODCTL: BODLPM Mask */
+
+#define SYS_BODCTL_BODOUT_Pos (6) /*!< SYS_T::BODCTL: BODOUT Position */
+#define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) /*!< SYS_T::BODCTL: BODOUT Mask */
+
+#define SYS_BODCTL_LVREN_Pos (7) /*!< SYS_T::BODCTL: LVREN Position */
+#define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) /*!< SYS_T::BODCTL: LVREN Mask */
+
+#define SYS_BODCTL_BODDGSEL_Pos (8) /*!< SYS_T::BODCTL: BODDGSEL Position */
+#define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) /*!< SYS_T::BODCTL: BODDGSEL Mask */
+
+#define SYS_BODCTL_LVRDGSEL_Pos (12) /*!< SYS_T::BODCTL: LVRDGSEL Position */
+#define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) /*!< SYS_T::BODCTL: LVRDGSEL Mask */
+
+#define SYS_BODCTL_BODVL_Pos (16) /*!< SYS_T::BODCTL: BODVL Position */
+#define SYS_BODCTL_BODVL_Msk (0x7ul << SYS_BODCTL_BODVL_Pos) /*!< SYS_T::BODCTL: BODVL Mask */
+
+#define SYS_IVSCTL_VTEMPEN_Pos (0) /*!< SYS_T::IVSCTL: VTEMPEN Position */
+#define SYS_IVSCTL_VTEMPEN_Msk (0x1ul << SYS_IVSCTL_VTEMPEN_Pos) /*!< SYS_T::IVSCTL: VTEMPEN Mask */
+
+#define SYS_IVSCTL_VBATUGEN_Pos (1) /*!< SYS_T::IVSCTL: VBATUGEN Position */
+#define SYS_IVSCTL_VBATUGEN_Msk (0x1ul << SYS_IVSCTL_VBATUGEN_Pos) /*!< SYS_T::IVSCTL: VBATUGEN Mask */
+
+#define SYS_PORCTL_POROFF_Pos (0) /*!< SYS_T::PORCTL: POROFF Position */
+#define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) /*!< SYS_T::PORCTL: POROFF Mask */
+
+#define SYS_VREFCTL_VREFCTL_Pos (0) /*!< SYS_T::VREFCTL: VREFCTL Position */
+#define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) /*!< SYS_T::VREFCTL: VREFCTL Mask */
+
+#define SYS_VREFCTL_PRELOAD_SEL_Pos (6) /*!< SYS_T::VREFCTL: PRELOAD_SEL Position */
+#define SYS_VREFCTL_PRELOAD_SEL_Msk (0x3ul << SYS_VREFCTL_PRELOAD_SEL_Pos) /*!< SYS_T::VREFCTL: PRELOAD_SEL Mask */
+
+#define SYS_USBPHY_USBROLE_Pos (0) /*!< SYS_T::USBPHY: USBROLE Position */
+#define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) /*!< SYS_T::USBPHY: USBROLE Mask */
+
+#define SYS_USBPHY_SBO_Pos (2) /*!< SYS_T::USBPHY: SBO Position */
+#define SYS_USBPHY_SBO_Msk (0x1ul << SYS_USBPHY_SBO_Pos) /*!< SYS_T::USBPHY: SBO Mask */
+
+#define SYS_USBPHY_USBEN_Pos (8) /*!< SYS_T::USBPHY: USBEN Position */
+#define SYS_USBPHY_USBEN_Msk (0x1ul << SYS_USBPHY_USBEN_Pos) /*!< SYS_T::USBPHY: USBEN Mask */
+
+#define SYS_USBPHY_HSUSBROLE_Pos (16) /*!< SYS_T::USBPHY: HSUSBROLE Position */
+#define SYS_USBPHY_HSUSBROLE_Msk (0x3ul << SYS_USBPHY_HSUSBROLE_Pos) /*!< SYS_T::USBPHY: HSUSBROLE Mask */
+
+#define SYS_USBPHY_HSUSBEN_Pos (24) /*!< SYS_T::USBPHY: HSUSBEN Position */
+#define SYS_USBPHY_HSUSBEN_Msk (0x1ul << SYS_USBPHY_HSUSBEN_Pos) /*!< SYS_T::USBPHY: HSUSBEN Mask */
+
+#define SYS_USBPHY_HSUSBACT_Pos (25) /*!< SYS_T::USBPHY: HSUSBACT Position */
+#define SYS_USBPHY_HSUSBACT_Msk (0x1ul << SYS_USBPHY_HSUSBACT_Pos) /*!< SYS_T::USBPHY: HSUSBACT Mask */
+
+#define SYS_GPA_MFPL_PA0MFP_Pos (0) /*!< SYS_T::GPA_MFPL: PA0MFP Position */
+#define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) /*!< SYS_T::GPA_MFPL: PA0MFP Mask */
+
+#define SYS_GPA_MFPL_PA1MFP_Pos (4) /*!< SYS_T::GPA_MFPL: PA1MFP Position */
+#define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) /*!< SYS_T::GPA_MFPL: PA1MFP Mask */
+
+#define SYS_GPA_MFPL_PA2MFP_Pos (8) /*!< SYS_T::GPA_MFPL: PA2MFP Position */
+#define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) /*!< SYS_T::GPA_MFPL: PA2MFP Mask */
+
+#define SYS_GPA_MFPL_PA3MFP_Pos (12) /*!< SYS_T::GPA_MFPL: PA3MFP Position */
+#define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) /*!< SYS_T::GPA_MFPL: PA3MFP Mask */
+
+#define SYS_GPA_MFPL_PA4MFP_Pos (16) /*!< SYS_T::GPA_MFPL: PA4MFP Position */
+#define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) /*!< SYS_T::GPA_MFPL: PA4MFP Mask */
+
+#define SYS_GPA_MFPL_PA5MFP_Pos (20) /*!< SYS_T::GPA_MFPL: PA5MFP Position */
+#define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) /*!< SYS_T::GPA_MFPL: PA5MFP Mask */
+
+#define SYS_GPA_MFPL_PA6MFP_Pos (24) /*!< SYS_T::GPA_MFPL: PA6MFP Position */
+#define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) /*!< SYS_T::GPA_MFPL: PA6MFP Mask */
+
+#define SYS_GPA_MFPL_PA7MFP_Pos (28) /*!< SYS_T::GPA_MFPL: PA7MFP Position */
+#define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) /*!< SYS_T::GPA_MFPL: PA7MFP Mask */
+
+#define SYS_GPA_MFPH_PA8MFP_Pos (0) /*!< SYS_T::GPA_MFPH: PA8MFP Position */
+#define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) /*!< SYS_T::GPA_MFPH: PA8MFP Mask */
+
+#define SYS_GPA_MFPH_PA9MFP_Pos (4) /*!< SYS_T::GPA_MFPH: PA9MFP Position */
+#define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) /*!< SYS_T::GPA_MFPH: PA9MFP Mask */
+
+#define SYS_GPA_MFPH_PA10MFP_Pos (8) /*!< SYS_T::GPA_MFPH: PA10MFP Position */
+#define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) /*!< SYS_T::GPA_MFPH: PA10MFP Mask */
+
+#define SYS_GPA_MFPH_PA11MFP_Pos (12) /*!< SYS_T::GPA_MFPH: PA11MFP Position */
+#define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) /*!< SYS_T::GPA_MFPH: PA11MFP Mask */
+
+#define SYS_GPA_MFPH_PA12MFP_Pos (16) /*!< SYS_T::GPA_MFPH: PA12MFP Position */
+#define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) /*!< SYS_T::GPA_MFPH: PA12MFP Mask */
+
+#define SYS_GPA_MFPH_PA13MFP_Pos (20) /*!< SYS_T::GPA_MFPH: PA13MFP Position */
+#define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) /*!< SYS_T::GPA_MFPH: PA13MFP Mask */
+
+#define SYS_GPA_MFPH_PA14MFP_Pos (24) /*!< SYS_T::GPA_MFPH: PA14MFP Position */
+#define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) /*!< SYS_T::GPA_MFPH: PA14MFP Mask */
+
+#define SYS_GPA_MFPH_PA15MFP_Pos (28) /*!< SYS_T::GPA_MFPH: PA15MFP Position */
+#define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) /*!< SYS_T::GPA_MFPH: PA15MFP Mask */
+
+#define SYS_GPB_MFPL_PB0MFP_Pos (0) /*!< SYS_T::GPB_MFPL: PB0MFP Position */
+#define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) /*!< SYS_T::GPB_MFPL: PB0MFP Mask */
+
+#define SYS_GPB_MFPL_PB1MFP_Pos (4) /*!< SYS_T::GPB_MFPL: PB1MFP Position */
+#define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) /*!< SYS_T::GPB_MFPL: PB1MFP Mask */
+
+#define SYS_GPB_MFPL_PB2MFP_Pos (8) /*!< SYS_T::GPB_MFPL: PB2MFP Position */
+#define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) /*!< SYS_T::GPB_MFPL: PB2MFP Mask */
+
+#define SYS_GPB_MFPL_PB3MFP_Pos (12) /*!< SYS_T::GPB_MFPL: PB3MFP Position */
+#define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) /*!< SYS_T::GPB_MFPL: PB3MFP Mask */
+
+#define SYS_GPB_MFPL_PB4MFP_Pos (16) /*!< SYS_T::GPB_MFPL: PB4MFP Position */
+#define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) /*!< SYS_T::GPB_MFPL: PB4MFP Mask */
+
+#define SYS_GPB_MFPL_PB5MFP_Pos (20) /*!< SYS_T::GPB_MFPL: PB5MFP Position */
+#define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) /*!< SYS_T::GPB_MFPL: PB5MFP Mask */
+
+#define SYS_GPB_MFPL_PB6MFP_Pos (24) /*!< SYS_T::GPB_MFPL: PB6MFP Position */
+#define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) /*!< SYS_T::GPB_MFPL: PB6MFP Mask */
+
+#define SYS_GPB_MFPL_PB7MFP_Pos (28) /*!< SYS_T::GPB_MFPL: PB7MFP Position */
+#define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) /*!< SYS_T::GPB_MFPL: PB7MFP Mask */
+
+#define SYS_GPB_MFPH_PB8MFP_Pos (0) /*!< SYS_T::GPB_MFPH: PB8MFP Position */
+#define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) /*!< SYS_T::GPB_MFPH: PB8MFP Mask */
+
+#define SYS_GPB_MFPH_PB9MFP_Pos (4) /*!< SYS_T::GPB_MFPH: PB9MFP Position */
+#define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) /*!< SYS_T::GPB_MFPH: PB9MFP Mask */
+
+#define SYS_GPB_MFPH_PB10MFP_Pos (8) /*!< SYS_T::GPB_MFPH: PB10MFP Position */
+#define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) /*!< SYS_T::GPB_MFPH: PB10MFP Mask */
+
+#define SYS_GPB_MFPH_PB11MFP_Pos (12) /*!< SYS_T::GPB_MFPH: PB11MFP Position */
+#define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) /*!< SYS_T::GPB_MFPH: PB11MFP Mask */
+
+#define SYS_GPB_MFPH_PB12MFP_Pos (16) /*!< SYS_T::GPB_MFPH: PB12MFP Position */
+#define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) /*!< SYS_T::GPB_MFPH: PB12MFP Mask */
+
+#define SYS_GPB_MFPH_PB13MFP_Pos (20) /*!< SYS_T::GPB_MFPH: PB13MFP Position */
+#define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) /*!< SYS_T::GPB_MFPH: PB13MFP Mask */
+
+#define SYS_GPB_MFPH_PB14MFP_Pos (24) /*!< SYS_T::GPB_MFPH: PB14MFP Position */
+#define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) /*!< SYS_T::GPB_MFPH: PB14MFP Mask */
+
+#define SYS_GPB_MFPH_PB15MFP_Pos (28) /*!< SYS_T::GPB_MFPH: PB15MFP Position */
+#define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) /*!< SYS_T::GPB_MFPH: PB15MFP Mask */
+
+#define SYS_GPC_MFPL_PC0MFP_Pos (0) /*!< SYS_T::GPC_MFPL: PC0MFP Position */
+#define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) /*!< SYS_T::GPC_MFPL: PC0MFP Mask */
+
+#define SYS_GPC_MFPL_PC1MFP_Pos (4) /*!< SYS_T::GPC_MFPL: PC1MFP Position */
+#define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) /*!< SYS_T::GPC_MFPL: PC1MFP Mask */
+
+#define SYS_GPC_MFPL_PC2MFP_Pos (8) /*!< SYS_T::GPC_MFPL: PC2MFP Position */
+#define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) /*!< SYS_T::GPC_MFPL: PC2MFP Mask */
+
+#define SYS_GPC_MFPL_PC3MFP_Pos (12) /*!< SYS_T::GPC_MFPL: PC3MFP Position */
+#define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) /*!< SYS_T::GPC_MFPL: PC3MFP Mask */
+
+#define SYS_GPC_MFPL_PC4MFP_Pos (16) /*!< SYS_T::GPC_MFPL: PC4MFP Position */
+#define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) /*!< SYS_T::GPC_MFPL: PC4MFP Mask */
+
+#define SYS_GPC_MFPL_PC5MFP_Pos (20) /*!< SYS_T::GPC_MFPL: PC5MFP Position */
+#define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) /*!< SYS_T::GPC_MFPL: PC5MFP Mask */
+
+#define SYS_GPC_MFPL_PC6MFP_Pos (24) /*!< SYS_T::GPC_MFPL: PC6MFP Position */
+#define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) /*!< SYS_T::GPC_MFPL: PC6MFP Mask */
+
+#define SYS_GPC_MFPL_PC7MFP_Pos (28) /*!< SYS_T::GPC_MFPL: PC7MFP Position */
+#define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) /*!< SYS_T::GPC_MFPL: PC7MFP Mask */
+
+#define SYS_GPC_MFPH_PC8MFP_Pos (0) /*!< SYS_T::GPC_MFPH: PC8MFP Position */
+#define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) /*!< SYS_T::GPC_MFPH: PC8MFP Mask */
+
+#define SYS_GPC_MFPH_PC9MFP_Pos (4) /*!< SYS_T::GPC_MFPH: PC9MFP Position */
+#define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) /*!< SYS_T::GPC_MFPH: PC9MFP Mask */
+
+#define SYS_GPC_MFPH_PC10MFP_Pos (8) /*!< SYS_T::GPC_MFPH: PC10MFP Position */
+#define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) /*!< SYS_T::GPC_MFPH: PC10MFP Mask */
+
+#define SYS_GPC_MFPH_PC11MFP_Pos (12) /*!< SYS_T::GPC_MFPH: PC11MFP Position */
+#define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) /*!< SYS_T::GPC_MFPH: PC11MFP Mask */
+
+#define SYS_GPC_MFPH_PC12MFP_Pos (16) /*!< SYS_T::GPC_MFPH: PC12MFP Position */
+#define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) /*!< SYS_T::GPC_MFPH: PC12MFP Mask */
+
+#define SYS_GPC_MFPH_PC13MFP_Pos (20) /*!< SYS_T::GPC_MFPH: PC13MFP Position */
+#define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) /*!< SYS_T::GPC_MFPH: PC13MFP Mask */
+
+#define SYS_GPC_MFPH_PC14MFP_Pos (24) /*!< SYS_T::GPC_MFPH: PC14MFP Position */
+#define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) /*!< SYS_T::GPC_MFPH: PC14MFP Mask */
+
+#define SYS_GPC_MFPH_PC15MFP_Pos (28) /*!< SYS_T::GPC_MFPH: PC15MFP Position */
+#define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) /*!< SYS_T::GPC_MFPH: PC15MFP Mask */
+
+#define SYS_GPD_MFPL_PD0MFP_Pos (0) /*!< SYS_T::GPD_MFPL: PD0MFP Position */
+#define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) /*!< SYS_T::GPD_MFPL: PD0MFP Mask */
+
+#define SYS_GPD_MFPL_PD1MFP_Pos (4) /*!< SYS_T::GPD_MFPL: PD1MFP Position */
+#define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) /*!< SYS_T::GPD_MFPL: PD1MFP Mask */
+
+#define SYS_GPD_MFPL_PD2MFP_Pos (8) /*!< SYS_T::GPD_MFPL: PD2MFP Position */
+#define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) /*!< SYS_T::GPD_MFPL: PD2MFP Mask */
+
+#define SYS_GPD_MFPL_PD3MFP_Pos (12) /*!< SYS_T::GPD_MFPL: PD3MFP Position */
+#define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) /*!< SYS_T::GPD_MFPL: PD3MFP Mask */
+
+#define SYS_GPD_MFPL_PD4MFP_Pos (16) /*!< SYS_T::GPD_MFPL: PD4MFP Position */
+#define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) /*!< SYS_T::GPD_MFPL: PD4MFP Mask */
+
+#define SYS_GPD_MFPL_PD5MFP_Pos (20) /*!< SYS_T::GPD_MFPL: PD5MFP Position */
+#define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) /*!< SYS_T::GPD_MFPL: PD5MFP Mask */
+
+#define SYS_GPD_MFPL_PD6MFP_Pos (24) /*!< SYS_T::GPD_MFPL: PD6MFP Position */
+#define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) /*!< SYS_T::GPD_MFPL: PD6MFP Mask */
+
+#define SYS_GPD_MFPL_PD7MFP_Pos (28) /*!< SYS_T::GPD_MFPL: PD7MFP Position */
+#define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) /*!< SYS_T::GPD_MFPL: PD7MFP Mask */
+
+#define SYS_GPD_MFPH_PD8MFP_Pos (0) /*!< SYS_T::GPD_MFPH: PD8MFP Position */
+#define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) /*!< SYS_T::GPD_MFPH: PD8MFP Mask */
+
+#define SYS_GPD_MFPH_PD9MFP_Pos (4) /*!< SYS_T::GPD_MFPH: PD9MFP Position */
+#define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) /*!< SYS_T::GPD_MFPH: PD9MFP Mask */
+
+#define SYS_GPD_MFPH_PD10MFP_Pos (8) /*!< SYS_T::GPD_MFPH: PD10MFP Position */
+#define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) /*!< SYS_T::GPD_MFPH: PD10MFP Mask */
+
+#define SYS_GPD_MFPH_PD11MFP_Pos (12) /*!< SYS_T::GPD_MFPH: PD11MFP Position */
+#define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) /*!< SYS_T::GPD_MFPH: PD11MFP Mask */
+
+#define SYS_GPD_MFPH_PD12MFP_Pos (16) /*!< SYS_T::GPD_MFPH: PD12MFP Position */
+#define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) /*!< SYS_T::GPD_MFPH: PD12MFP Mask */
+
+#define SYS_GPD_MFPH_PD13MFP_Pos (20) /*!< SYS_T::GPD_MFPH: PD13MFP Position */
+#define SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos) /*!< SYS_T::GPD_MFPH: PD13MFP Mask */
+
+#define SYS_GPD_MFPH_PD14MFP_Pos (24) /*!< SYS_T::GPD_MFPH: PD14MFP Position */
+#define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) /*!< SYS_T::GPD_MFPH: PD14MFP Mask */
+
+#define SYS_GPD_MFPH_PD15MFP_Pos (28) /*!< SYS_T::GPD_MFPH: PD15MFP Position */
+#define SYS_GPD_MFPH_PD15MFP_Msk (0xful << SYS_GPD_MFPH_PD15MFP_Pos) /*!< SYS_T::GPD_MFPH: PD15MFP Mask */
+
+#define SYS_GPE_MFPL_PE0MFP_Pos (0) /*!< SYS_T::GPE_MFPL: PE0MFP Position */
+#define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) /*!< SYS_T::GPE_MFPL: PE0MFP Mask */
+
+#define SYS_GPE_MFPL_PE1MFP_Pos (4) /*!< SYS_T::GPE_MFPL: PE1MFP Position */
+#define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) /*!< SYS_T::GPE_MFPL: PE1MFP Mask */
+
+#define SYS_GPE_MFPL_PE2MFP_Pos (8) /*!< SYS_T::GPE_MFPL: PE2MFP Position */
+#define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) /*!< SYS_T::GPE_MFPL: PE2MFP Mask */
+
+#define SYS_GPE_MFPL_PE3MFP_Pos (12) /*!< SYS_T::GPE_MFPL: PE3MFP Position */
+#define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) /*!< SYS_T::GPE_MFPL: PE3MFP Mask */
+
+#define SYS_GPE_MFPL_PE4MFP_Pos (16) /*!< SYS_T::GPE_MFPL: PE4MFP Position */
+#define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) /*!< SYS_T::GPE_MFPL: PE4MFP Mask */
+
+#define SYS_GPE_MFPL_PE5MFP_Pos (20) /*!< SYS_T::GPE_MFPL: PE5MFP Position */
+#define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) /*!< SYS_T::GPE_MFPL: PE5MFP Mask */
+
+#define SYS_GPE_MFPL_PE6MFP_Pos (24) /*!< SYS_T::GPE_MFPL: PE6MFP Position */
+#define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) /*!< SYS_T::GPE_MFPL: PE6MFP Mask */
+
+#define SYS_GPE_MFPL_PE7MFP_Pos (28) /*!< SYS_T::GPE_MFPL: PE7MFP Position */
+#define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) /*!< SYS_T::GPE_MFPL: PE7MFP Mask */
+
+#define SYS_GPE_MFPH_PE8MFP_Pos (0) /*!< SYS_T::GPE_MFPH: PE8MFP Position */
+#define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) /*!< SYS_T::GPE_MFPH: PE8MFP Mask */
+
+#define SYS_GPE_MFPH_PE9MFP_Pos (4) /*!< SYS_T::GPE_MFPH: PE9MFP Position */
+#define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) /*!< SYS_T::GPE_MFPH: PE9MFP Mask */
+
+#define SYS_GPE_MFPH_PE10MFP_Pos (8) /*!< SYS_T::GPE_MFPH: PE10MFP Position */
+#define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) /*!< SYS_T::GPE_MFPH: PE10MFP Mask */
+
+#define SYS_GPE_MFPH_PE11MFP_Pos (12) /*!< SYS_T::GPE_MFPH: PE11MFP Position */
+#define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) /*!< SYS_T::GPE_MFPH: PE11MFP Mask */
+
+#define SYS_GPE_MFPH_PE12MFP_Pos (16) /*!< SYS_T::GPE_MFPH: PE12MFP Position */
+#define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) /*!< SYS_T::GPE_MFPH: PE12MFP Mask */
+
+#define SYS_GPE_MFPH_PE13MFP_Pos (20) /*!< SYS_T::GPE_MFPH: PE13MFP Position */
+#define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) /*!< SYS_T::GPE_MFPH: PE13MFP Mask */
+
+#define SYS_GPE_MFPH_PE14MFP_Pos (24) /*!< SYS_T::GPE_MFPH: PE14MFP Position */
+#define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) /*!< SYS_T::GPE_MFPH: PE14MFP Mask */
+
+#define SYS_GPE_MFPH_PE15MFP_Pos (28) /*!< SYS_T::GPE_MFPH: PE15MFP Position */
+#define SYS_GPE_MFPH_PE15MFP_Msk (0xful << SYS_GPE_MFPH_PE15MFP_Pos) /*!< SYS_T::GPE_MFPH: PE15MFP Mask */
+
+#define SYS_GPF_MFPL_PF0MFP_Pos (0) /*!< SYS_T::GPF_MFPL: PF0MFP Position */
+#define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) /*!< SYS_T::GPF_MFPL: PF0MFP Mask */
+
+#define SYS_GPF_MFPL_PF1MFP_Pos (4) /*!< SYS_T::GPF_MFPL: PF1MFP Position */
+#define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) /*!< SYS_T::GPF_MFPL: PF1MFP Mask */
+
+#define SYS_GPF_MFPL_PF2MFP_Pos (8) /*!< SYS_T::GPF_MFPL: PF2MFP Position */
+#define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) /*!< SYS_T::GPF_MFPL: PF2MFP Mask */
+
+#define SYS_GPF_MFPL_PF3MFP_Pos (12) /*!< SYS_T::GPF_MFPL: PF3MFP Position */
+#define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) /*!< SYS_T::GPF_MFPL: PF3MFP Mask */
+
+#define SYS_GPF_MFPL_PF4MFP_Pos (16) /*!< SYS_T::GPF_MFPL: PF4MFP Position */
+#define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) /*!< SYS_T::GPF_MFPL: PF4MFP Mask */
+
+#define SYS_GPF_MFPL_PF5MFP_Pos (20) /*!< SYS_T::GPF_MFPL: PF5MFP Position */
+#define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) /*!< SYS_T::GPF_MFPL: PF5MFP Mask */
+
+#define SYS_GPF_MFPL_PF6MFP_Pos (24) /*!< SYS_T::GPF_MFPL: PF6MFP Position */
+#define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) /*!< SYS_T::GPF_MFPL: PF6MFP Mask */
+
+#define SYS_GPF_MFPL_PF7MFP_Pos (28) /*!< SYS_T::GPF_MFPL: PF7MFP Position */
+#define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) /*!< SYS_T::GPF_MFPL: PF7MFP Mask */
+
+#define SYS_GPF_MFPH_PF8MFP_Pos (0) /*!< SYS_T::GPF_MFPH: PF8MFP Position */
+#define SYS_GPF_MFPH_PF8MFP_Msk (0xful << SYS_GPF_MFPH_PF8MFP_Pos) /*!< SYS_T::GPF_MFPH: PF8MFP Mask */
+
+#define SYS_GPF_MFPH_PF9MFP_Pos (4) /*!< SYS_T::GPF_MFPH: PF9MFP Position */
+#define SYS_GPF_MFPH_PF9MFP_Msk (0xful << SYS_GPF_MFPH_PF9MFP_Pos) /*!< SYS_T::GPF_MFPH: PF9MFP Mask */
+
+#define SYS_GPF_MFPH_PF10MFP_Pos (8) /*!< SYS_T::GPF_MFPH: PF10MFP Position */
+#define SYS_GPF_MFPH_PF10MFP_Msk (0xful << SYS_GPF_MFPH_PF10MFP_Pos) /*!< SYS_T::GPF_MFPH: PF10MFP Mask */
+
+#define SYS_GPF_MFPH_PF11MFP_Pos (12) /*!< SYS_T::GPF_MFPH: PF11MFP Position */
+#define SYS_GPF_MFPH_PF11MFP_Msk (0xful << SYS_GPF_MFPH_PF11MFP_Pos) /*!< SYS_T::GPF_MFPH: PF11MFP Mask */
+
+#define SYS_GPF_MFPH_PF12MFP_Pos (16) /*!< SYS_T::GPF_MFPH: PF12MFP Position */
+#define SYS_GPF_MFPH_PF12MFP_Msk (0xful << SYS_GPF_MFPH_PF12MFP_Pos) /*!< SYS_T::GPF_MFPH: PF12MFP Mask */
+
+#define SYS_GPF_MFPH_PF13MFP_Pos (20) /*!< SYS_T::GPF_MFPH: PF13MFP Position */
+#define SYS_GPF_MFPH_PF13MFP_Msk (0xful << SYS_GPF_MFPH_PF13MFP_Pos) /*!< SYS_T::GPF_MFPH: PF13MFP Mask */
+
+#define SYS_GPF_MFPH_PF14MFP_Pos (24) /*!< SYS_T::GPF_MFPH: PF14MFP Position */
+#define SYS_GPF_MFPH_PF14MFP_Msk (0xful << SYS_GPF_MFPH_PF14MFP_Pos) /*!< SYS_T::GPF_MFPH: PF14MFP Mask */
+
+#define SYS_GPF_MFPH_PF15MFP_Pos (28) /*!< SYS_T::GPF_MFPH: PF15MFP Position */
+#define SYS_GPF_MFPH_PF15MFP_Msk (0xful << SYS_GPF_MFPH_PF15MFP_Pos) /*!< SYS_T::GPF_MFPH: PF15MFP Mask */
+
+#define SYS_GPG_MFPL_PG0MFP_Pos (0) /*!< SYS_T::GPG_MFPL: PG0MFP Position */
+#define SYS_GPG_MFPL_PG0MFP_Msk (0xful << SYS_GPG_MFPL_PG0MFP_Pos) /*!< SYS_T::GPG_MFPL: PG0MFP Mask */
+
+#define SYS_GPG_MFPL_PG1MFP_Pos (4) /*!< SYS_T::GPG_MFPL: PG1MFP Position */
+#define SYS_GPG_MFPL_PG1MFP_Msk (0xful << SYS_GPG_MFPL_PG1MFP_Pos) /*!< SYS_T::GPG_MFPL: PG1MFP Mask */
+
+#define SYS_GPG_MFPL_PG2MFP_Pos (8) /*!< SYS_T::GPG_MFPL: PG2MFP Position */
+#define SYS_GPG_MFPL_PG2MFP_Msk (0xful << SYS_GPG_MFPL_PG2MFP_Pos) /*!< SYS_T::GPG_MFPL: PG2MFP Mask */
+
+#define SYS_GPG_MFPL_PG3MFP_Pos (12) /*!< SYS_T::GPG_MFPL: PG3MFP Position */
+#define SYS_GPG_MFPL_PG3MFP_Msk (0xful << SYS_GPG_MFPL_PG3MFP_Pos) /*!< SYS_T::GPG_MFPL: PG3MFP Mask */
+
+#define SYS_GPG_MFPL_PG4MFP_Pos (16) /*!< SYS_T::GPG_MFPL: PG4MFP Position */
+#define SYS_GPG_MFPL_PG4MFP_Msk (0xful << SYS_GPG_MFPL_PG4MFP_Pos) /*!< SYS_T::GPG_MFPL: PG4MFP Mask */
+
+#define SYS_GPG_MFPL_PG5MFP_Pos (20) /*!< SYS_T::GPG_MFPL: PG5MFP Position */
+#define SYS_GPG_MFPL_PG5MFP_Msk (0xful << SYS_GPG_MFPL_PG5MFP_Pos) /*!< SYS_T::GPG_MFPL: PG5MFP Mask */
+
+#define SYS_GPG_MFPL_PG6MFP_Pos (24) /*!< SYS_T::GPG_MFPL: PG6MFP Position */
+#define SYS_GPG_MFPL_PG6MFP_Msk (0xful << SYS_GPG_MFPL_PG6MFP_Pos) /*!< SYS_T::GPG_MFPL: PG6MFP Mask */
+
+#define SYS_GPG_MFPL_PG7MFP_Pos (28) /*!< SYS_T::GPG_MFPL: PG7MFP Position */
+#define SYS_GPG_MFPL_PG7MFP_Msk (0xful << SYS_GPG_MFPL_PG7MFP_Pos) /*!< SYS_T::GPG_MFPL: PG7MFP Mask */
+
+#define SYS_GPG_MFPH_PG8MFP_Pos (0) /*!< SYS_T::GPG_MFPH: PG8MFP Position */
+#define SYS_GPG_MFPH_PG8MFP_Msk (0xful << SYS_GPG_MFPH_PG8MFP_Pos) /*!< SYS_T::GPG_MFPH: PG8MFP Mask */
+
+#define SYS_GPG_MFPH_PG9MFP_Pos (4) /*!< SYS_T::GPG_MFPH: PG9MFP Position */
+#define SYS_GPG_MFPH_PG9MFP_Msk (0xful << SYS_GPG_MFPH_PG9MFP_Pos) /*!< SYS_T::GPG_MFPH: PG9MFP Mask */
+
+#define SYS_GPG_MFPH_PG10MFP_Pos (8) /*!< SYS_T::GPG_MFPH: PG10MFP Position */
+#define SYS_GPG_MFPH_PG10MFP_Msk (0xful << SYS_GPG_MFPH_PG10MFP_Pos) /*!< SYS_T::GPG_MFPH: PG10MFP Mask */
+
+#define SYS_GPG_MFPH_PG11MFP_Pos (12) /*!< SYS_T::GPG_MFPH: PG11MFP Position */
+#define SYS_GPG_MFPH_PG11MFP_Msk (0xful << SYS_GPG_MFPH_PG11MFP_Pos) /*!< SYS_T::GPG_MFPH: PG11MFP Mask */
+
+#define SYS_GPG_MFPH_PG12MFP_Pos (16) /*!< SYS_T::GPG_MFPH: PG12MFP Position */
+#define SYS_GPG_MFPH_PG12MFP_Msk (0xful << SYS_GPG_MFPH_PG12MFP_Pos) /*!< SYS_T::GPG_MFPH: PG12MFP Mask */
+
+#define SYS_GPG_MFPH_PG13MFP_Pos (20) /*!< SYS_T::GPG_MFPH: PG13MFP Position */
+#define SYS_GPG_MFPH_PG13MFP_Msk (0xful << SYS_GPG_MFPH_PG13MFP_Pos) /*!< SYS_T::GPG_MFPH: PG13MFP Mask */
+
+#define SYS_GPG_MFPH_PG14MFP_Pos (24) /*!< SYS_T::GPG_MFPH: PG14MFP Position */
+#define SYS_GPG_MFPH_PG14MFP_Msk (0xful << SYS_GPG_MFPH_PG14MFP_Pos) /*!< SYS_T::GPG_MFPH: PG14MFP Mask */
+
+#define SYS_GPG_MFPH_PG15MFP_Pos (28) /*!< SYS_T::GPG_MFPH: PG15MFP Position */
+#define SYS_GPG_MFPH_PG15MFP_Msk (0xful << SYS_GPG_MFPH_PG15MFP_Pos) /*!< SYS_T::GPG_MFPH: PG15MFP Mask */
+
+#define SYS_GPH_MFPL_PH0MFP_Pos (0) /*!< SYS_T::GPH_MFPL: PH0MFP Position */
+#define SYS_GPH_MFPL_PH0MFP_Msk (0xful << SYS_GPH_MFPL_PH0MFP_Pos) /*!< SYS_T::GPH_MFPL: PH0MFP Mask */
+
+#define SYS_GPH_MFPL_PH1MFP_Pos (4) /*!< SYS_T::GPH_MFPL: PH1MFP Position */
+#define SYS_GPH_MFPL_PH1MFP_Msk (0xful << SYS_GPH_MFPL_PH1MFP_Pos) /*!< SYS_T::GPH_MFPL: PH1MFP Mask */
+
+#define SYS_GPH_MFPL_PH2MFP_Pos (8) /*!< SYS_T::GPH_MFPL: PH2MFP Position */
+#define SYS_GPH_MFPL_PH2MFP_Msk (0xful << SYS_GPH_MFPL_PH2MFP_Pos) /*!< SYS_T::GPH_MFPL: PH2MFP Mask */
+
+#define SYS_GPH_MFPL_PH3MFP_Pos (12) /*!< SYS_T::GPH_MFPL: PH3MFP Position */
+#define SYS_GPH_MFPL_PH3MFP_Msk (0xful << SYS_GPH_MFPL_PH3MFP_Pos) /*!< SYS_T::GPH_MFPL: PH3MFP Mask */
+
+#define SYS_GPH_MFPL_PH4MFP_Pos (16) /*!< SYS_T::GPH_MFPL: PH4MFP Position */
+#define SYS_GPH_MFPL_PH4MFP_Msk (0xful << SYS_GPH_MFPL_PH4MFP_Pos) /*!< SYS_T::GPH_MFPL: PH4MFP Mask */
+
+#define SYS_GPH_MFPL_PH5MFP_Pos (20) /*!< SYS_T::GPH_MFPL: PH5MFP Position */
+#define SYS_GPH_MFPL_PH5MFP_Msk (0xful << SYS_GPH_MFPL_PH5MFP_Pos) /*!< SYS_T::GPH_MFPL: PH5MFP Mask */
+
+#define SYS_GPH_MFPL_PH6MFP_Pos (24) /*!< SYS_T::GPH_MFPL: PH6MFP Position */
+#define SYS_GPH_MFPL_PH6MFP_Msk (0xful << SYS_GPH_MFPL_PH6MFP_Pos) /*!< SYS_T::GPH_MFPL: PH6MFP Mask */
+
+#define SYS_GPH_MFPL_PH7MFP_Pos (28) /*!< SYS_T::GPH_MFPL: PH7MFP Position */
+#define SYS_GPH_MFPL_PH7MFP_Msk (0xful << SYS_GPH_MFPL_PH7MFP_Pos) /*!< SYS_T::GPH_MFPL: PH7MFP Mask */
+
+#define SYS_GPH_MFPH_PH8MFP_Pos (0) /*!< SYS_T::GPH_MFPH: PH8MFP Position */
+#define SYS_GPH_MFPH_PH8MFP_Msk (0xful << SYS_GPH_MFPH_PH8MFP_Pos) /*!< SYS_T::GPH_MFPH: PH8MFP Mask */
+
+#define SYS_GPH_MFPH_PH9MFP_Pos (4) /*!< SYS_T::GPH_MFPH: PH9MFP Position */
+#define SYS_GPH_MFPH_PH9MFP_Msk (0xful << SYS_GPH_MFPH_PH9MFP_Pos) /*!< SYS_T::GPH_MFPH: PH9MFP Mask */
+
+#define SYS_GPH_MFPH_PH10MFP_Pos (8) /*!< SYS_T::GPH_MFPH: PH10MFP Position */
+#define SYS_GPH_MFPH_PH10MFP_Msk (0xful << SYS_GPH_MFPH_PH10MFP_Pos) /*!< SYS_T::GPH_MFPH: PH10MFP Mask */
+
+#define SYS_GPH_MFPH_PH11MFP_Pos (12) /*!< SYS_T::GPH_MFPH: PH11MFP Position */
+#define SYS_GPH_MFPH_PH11MFP_Msk (0xful << SYS_GPH_MFPH_PH11MFP_Pos) /*!< SYS_T::GPH_MFPH: PH11MFP Mask */
+
+#define SYS_GPH_MFPH_PH12MFP_Pos (16) /*!< SYS_T::GPH_MFPH: PH12MFP Position */
+#define SYS_GPH_MFPH_PH12MFP_Msk (0xful << SYS_GPH_MFPH_PH12MFP_Pos) /*!< SYS_T::GPH_MFPH: PH12MFP Mask */
+
+#define SYS_GPH_MFPH_PH13MFP_Pos (20) /*!< SYS_T::GPH_MFPH: PH13MFP Position */
+#define SYS_GPH_MFPH_PH13MFP_Msk (0xful << SYS_GPH_MFPH_PH13MFP_Pos) /*!< SYS_T::GPH_MFPH: PH13MFP Mask */
+
+#define SYS_GPH_MFPH_PH14MFP_Pos (24) /*!< SYS_T::GPH_MFPH: PH14MFP Position */
+#define SYS_GPH_MFPH_PH14MFP_Msk (0xful << SYS_GPH_MFPH_PH14MFP_Pos) /*!< SYS_T::GPH_MFPH: PH14MFP Mask */
+
+#define SYS_GPH_MFPH_PH15MFP_Pos (28) /*!< SYS_T::GPH_MFPH: PH15MFP Position */
+#define SYS_GPH_MFPH_PH15MFP_Msk (0xful << SYS_GPH_MFPH_PH15MFP_Pos) /*!< SYS_T::GPH_MFPH: PH15MFP Mask */
+
+#define SYS_GPA_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPA_MFOS: MFOS0 Position */
+#define SYS_GPA_MFOS_MFOS0_Msk (0x1ul << SYS_GPA_MFOS_MFOS0_Pos) /*!< SYS_T::GPA_MFOS: MFOS0 Mask */
+
+#define SYS_GPA_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPA_MFOS: MFOS1 Position */
+#define SYS_GPA_MFOS_MFOS1_Msk (0x1ul << SYS_GPA_MFOS_MFOS1_Pos) /*!< SYS_T::GPA_MFOS: MFOS1 Mask */
+
+#define SYS_GPA_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPA_MFOS: MFOS2 Position */
+#define SYS_GPA_MFOS_MFOS2_Msk (0x1ul << SYS_GPA_MFOS_MFOS2_Pos) /*!< SYS_T::GPA_MFOS: MFOS2 Mask */
+
+#define SYS_GPA_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPA_MFOS: MFOS3 Position */
+#define SYS_GPA_MFOS_MFOS3_Msk (0x1ul << SYS_GPA_MFOS_MFOS3_Pos) /*!< SYS_T::GPA_MFOS: MFOS3 Mask */
+
+#define SYS_GPA_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPA_MFOS: MFOS4 Position */
+#define SYS_GPA_MFOS_MFOS4_Msk (0x1ul << SYS_GPA_MFOS_MFOS4_Pos) /*!< SYS_T::GPA_MFOS: MFOS4 Mask */
+
+#define SYS_GPA_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPA_MFOS: MFOS5 Position */
+#define SYS_GPA_MFOS_MFOS5_Msk (0x1ul << SYS_GPA_MFOS_MFOS5_Pos) /*!< SYS_T::GPA_MFOS: MFOS5 Mask */
+
+#define SYS_GPA_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPA_MFOS: MFOS6 Position */
+#define SYS_GPA_MFOS_MFOS6_Msk (0x1ul << SYS_GPA_MFOS_MFOS6_Pos) /*!< SYS_T::GPA_MFOS: MFOS6 Mask */
+
+#define SYS_GPA_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPA_MFOS: MFOS7 Position */
+#define SYS_GPA_MFOS_MFOS7_Msk (0x1ul << SYS_GPA_MFOS_MFOS7_Pos) /*!< SYS_T::GPA_MFOS: MFOS7 Mask */
+
+#define SYS_GPA_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPA_MFOS: MFOS8 Position */
+#define SYS_GPA_MFOS_MFOS8_Msk (0x1ul << SYS_GPA_MFOS_MFOS8_Pos) /*!< SYS_T::GPA_MFOS: MFOS8 Mask */
+
+#define SYS_GPA_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPA_MFOS: MFOS9 Position */
+#define SYS_GPA_MFOS_MFOS9_Msk (0x1ul << SYS_GPA_MFOS_MFOS9_Pos) /*!< SYS_T::GPA_MFOS: MFOS9 Mask */
+
+#define SYS_GPA_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPA_MFOS: MFOS10 Position */
+#define SYS_GPA_MFOS_MFOS10_Msk (0x1ul << SYS_GPA_MFOS_MFOS10_Pos) /*!< SYS_T::GPA_MFOS: MFOS10 Mask */
+
+#define SYS_GPA_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPA_MFOS: MFOS11 Position */
+#define SYS_GPA_MFOS_MFOS11_Msk (0x1ul << SYS_GPA_MFOS_MFOS11_Pos) /*!< SYS_T::GPA_MFOS: MFOS11 Mask */
+
+#define SYS_GPA_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPA_MFOS: MFOS12 Position */
+#define SYS_GPA_MFOS_MFOS12_Msk (0x1ul << SYS_GPA_MFOS_MFOS12_Pos) /*!< SYS_T::GPA_MFOS: MFOS12 Mask */
+
+#define SYS_GPA_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPA_MFOS: MFOS13 Position */
+#define SYS_GPA_MFOS_MFOS13_Msk (0x1ul << SYS_GPA_MFOS_MFOS13_Pos) /*!< SYS_T::GPA_MFOS: MFOS13 Mask */
+
+#define SYS_GPA_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPA_MFOS: MFOS14 Position */
+#define SYS_GPA_MFOS_MFOS14_Msk (0x1ul << SYS_GPA_MFOS_MFOS14_Pos) /*!< SYS_T::GPA_MFOS: MFOS14 Mask */
+
+#define SYS_GPA_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPA_MFOS: MFOS15 Position */
+#define SYS_GPA_MFOS_MFOS15_Msk (0x1ul << SYS_GPA_MFOS_MFOS15_Pos) /*!< SYS_T::GPA_MFOS: MFOS15 Mask */
+
+#define SYS_GPB_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPB_MFOS: MFOS0 Position */
+#define SYS_GPB_MFOS_MFOS0_Msk (0x1ul << SYS_GPB_MFOS_MFOS0_Pos) /*!< SYS_T::GPB_MFOS: MFOS0 Mask */
+
+#define SYS_GPB_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPB_MFOS: MFOS1 Position */
+#define SYS_GPB_MFOS_MFOS1_Msk (0x1ul << SYS_GPB_MFOS_MFOS1_Pos) /*!< SYS_T::GPB_MFOS: MFOS1 Mask */
+
+#define SYS_GPB_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPB_MFOS: MFOS2 Position */
+#define SYS_GPB_MFOS_MFOS2_Msk (0x1ul << SYS_GPB_MFOS_MFOS2_Pos) /*!< SYS_T::GPB_MFOS: MFOS2 Mask */
+
+#define SYS_GPB_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPB_MFOS: MFOS3 Position */
+#define SYS_GPB_MFOS_MFOS3_Msk (0x1ul << SYS_GPB_MFOS_MFOS3_Pos) /*!< SYS_T::GPB_MFOS: MFOS3 Mask */
+
+#define SYS_GPB_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPB_MFOS: MFOS4 Position */
+#define SYS_GPB_MFOS_MFOS4_Msk (0x1ul << SYS_GPB_MFOS_MFOS4_Pos) /*!< SYS_T::GPB_MFOS: MFOS4 Mask */
+
+#define SYS_GPB_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPB_MFOS: MFOS5 Position */
+#define SYS_GPB_MFOS_MFOS5_Msk (0x1ul << SYS_GPB_MFOS_MFOS5_Pos) /*!< SYS_T::GPB_MFOS: MFOS5 Mask */
+
+#define SYS_GPB_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPB_MFOS: MFOS6 Position */
+#define SYS_GPB_MFOS_MFOS6_Msk (0x1ul << SYS_GPB_MFOS_MFOS6_Pos) /*!< SYS_T::GPB_MFOS: MFOS6 Mask */
+
+#define SYS_GPB_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPB_MFOS: MFOS7 Position */
+#define SYS_GPB_MFOS_MFOS7_Msk (0x1ul << SYS_GPB_MFOS_MFOS7_Pos) /*!< SYS_T::GPB_MFOS: MFOS7 Mask */
+
+#define SYS_GPB_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPB_MFOS: MFOS8 Position */
+#define SYS_GPB_MFOS_MFOS8_Msk (0x1ul << SYS_GPB_MFOS_MFOS8_Pos) /*!< SYS_T::GPB_MFOS: MFOS8 Mask */
+
+#define SYS_GPB_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPB_MFOS: MFOS9 Position */
+#define SYS_GPB_MFOS_MFOS9_Msk (0x1ul << SYS_GPB_MFOS_MFOS9_Pos) /*!< SYS_T::GPB_MFOS: MFOS9 Mask */
+
+#define SYS_GPB_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPB_MFOS: MFOS10 Position */
+#define SYS_GPB_MFOS_MFOS10_Msk (0x1ul << SYS_GPB_MFOS_MFOS10_Pos) /*!< SYS_T::GPB_MFOS: MFOS10 Mask */
+
+#define SYS_GPB_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPB_MFOS: MFOS11 Position */
+#define SYS_GPB_MFOS_MFOS11_Msk (0x1ul << SYS_GPB_MFOS_MFOS11_Pos) /*!< SYS_T::GPB_MFOS: MFOS11 Mask */
+
+#define SYS_GPB_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPB_MFOS: MFOS12 Position */
+#define SYS_GPB_MFOS_MFOS12_Msk (0x1ul << SYS_GPB_MFOS_MFOS12_Pos) /*!< SYS_T::GPB_MFOS: MFOS12 Mask */
+
+#define SYS_GPB_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPB_MFOS: MFOS13 Position */
+#define SYS_GPB_MFOS_MFOS13_Msk (0x1ul << SYS_GPB_MFOS_MFOS13_Pos) /*!< SYS_T::GPB_MFOS: MFOS13 Mask */
+
+#define SYS_GPB_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPB_MFOS: MFOS14 Position */
+#define SYS_GPB_MFOS_MFOS14_Msk (0x1ul << SYS_GPB_MFOS_MFOS14_Pos) /*!< SYS_T::GPB_MFOS: MFOS14 Mask */
+
+#define SYS_GPB_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPB_MFOS: MFOS15 Position */
+#define SYS_GPB_MFOS_MFOS15_Msk (0x1ul << SYS_GPB_MFOS_MFOS15_Pos) /*!< SYS_T::GPB_MFOS: MFOS15 Mask */
+
+#define SYS_GPC_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPC_MFOS: MFOS0 Position */
+#define SYS_GPC_MFOS_MFOS0_Msk (0x1ul << SYS_GPC_MFOS_MFOS0_Pos) /*!< SYS_T::GPC_MFOS: MFOS0 Mask */
+
+#define SYS_GPC_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPC_MFOS: MFOS1 Position */
+#define SYS_GPC_MFOS_MFOS1_Msk (0x1ul << SYS_GPC_MFOS_MFOS1_Pos) /*!< SYS_T::GPC_MFOS: MFOS1 Mask */
+
+#define SYS_GPC_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPC_MFOS: MFOS2 Position */
+#define SYS_GPC_MFOS_MFOS2_Msk (0x1ul << SYS_GPC_MFOS_MFOS2_Pos) /*!< SYS_T::GPC_MFOS: MFOS2 Mask */
+
+#define SYS_GPC_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPC_MFOS: MFOS3 Position */
+#define SYS_GPC_MFOS_MFOS3_Msk (0x1ul << SYS_GPC_MFOS_MFOS3_Pos) /*!< SYS_T::GPC_MFOS: MFOS3 Mask */
+
+#define SYS_GPC_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPC_MFOS: MFOS4 Position */
+#define SYS_GPC_MFOS_MFOS4_Msk (0x1ul << SYS_GPC_MFOS_MFOS4_Pos) /*!< SYS_T::GPC_MFOS: MFOS4 Mask */
+
+#define SYS_GPC_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPC_MFOS: MFOS5 Position */
+#define SYS_GPC_MFOS_MFOS5_Msk (0x1ul << SYS_GPC_MFOS_MFOS5_Pos) /*!< SYS_T::GPC_MFOS: MFOS5 Mask */
+
+#define SYS_GPC_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPC_MFOS: MFOS6 Position */
+#define SYS_GPC_MFOS_MFOS6_Msk (0x1ul << SYS_GPC_MFOS_MFOS6_Pos) /*!< SYS_T::GPC_MFOS: MFOS6 Mask */
+
+#define SYS_GPC_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPC_MFOS: MFOS7 Position */
+#define SYS_GPC_MFOS_MFOS7_Msk (0x1ul << SYS_GPC_MFOS_MFOS7_Pos) /*!< SYS_T::GPC_MFOS: MFOS7 Mask */
+
+#define SYS_GPC_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPC_MFOS: MFOS8 Position */
+#define SYS_GPC_MFOS_MFOS8_Msk (0x1ul << SYS_GPC_MFOS_MFOS8_Pos) /*!< SYS_T::GPC_MFOS: MFOS8 Mask */
+
+#define SYS_GPC_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPC_MFOS: MFOS9 Position */
+#define SYS_GPC_MFOS_MFOS9_Msk (0x1ul << SYS_GPC_MFOS_MFOS9_Pos) /*!< SYS_T::GPC_MFOS: MFOS9 Mask */
+
+#define SYS_GPC_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPC_MFOS: MFOS10 Position */
+#define SYS_GPC_MFOS_MFOS10_Msk (0x1ul << SYS_GPC_MFOS_MFOS10_Pos) /*!< SYS_T::GPC_MFOS: MFOS10 Mask */
+
+#define SYS_GPC_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPC_MFOS: MFOS11 Position */
+#define SYS_GPC_MFOS_MFOS11_Msk (0x1ul << SYS_GPC_MFOS_MFOS11_Pos) /*!< SYS_T::GPC_MFOS: MFOS11 Mask */
+
+#define SYS_GPC_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPC_MFOS: MFOS12 Position */
+#define SYS_GPC_MFOS_MFOS12_Msk (0x1ul << SYS_GPC_MFOS_MFOS12_Pos) /*!< SYS_T::GPC_MFOS: MFOS12 Mask */
+
+#define SYS_GPC_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPC_MFOS: MFOS13 Position */
+#define SYS_GPC_MFOS_MFOS13_Msk (0x1ul << SYS_GPC_MFOS_MFOS13_Pos) /*!< SYS_T::GPC_MFOS: MFOS13 Mask */
+
+#define SYS_GPC_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPC_MFOS: MFOS14 Position */
+#define SYS_GPC_MFOS_MFOS14_Msk (0x1ul << SYS_GPC_MFOS_MFOS14_Pos) /*!< SYS_T::GPC_MFOS: MFOS14 Mask */
+
+#define SYS_GPC_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPC_MFOS: MFOS15 Position */
+#define SYS_GPC_MFOS_MFOS15_Msk (0x1ul << SYS_GPC_MFOS_MFOS15_Pos) /*!< SYS_T::GPC_MFOS: MFOS15 Mask */
+
+#define SYS_GPD_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPD_MFOS: MFOS0 Position */
+#define SYS_GPD_MFOS_MFOS0_Msk (0x1ul << SYS_GPD_MFOS_MFOS0_Pos) /*!< SYS_T::GPD_MFOS: MFOS0 Mask */
+
+#define SYS_GPD_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPD_MFOS: MFOS1 Position */
+#define SYS_GPD_MFOS_MFOS1_Msk (0x1ul << SYS_GPD_MFOS_MFOS1_Pos) /*!< SYS_T::GPD_MFOS: MFOS1 Mask */
+
+#define SYS_GPD_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPD_MFOS: MFOS2 Position */
+#define SYS_GPD_MFOS_MFOS2_Msk (0x1ul << SYS_GPD_MFOS_MFOS2_Pos) /*!< SYS_T::GPD_MFOS: MFOS2 Mask */
+
+#define SYS_GPD_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPD_MFOS: MFOS3 Position */
+#define SYS_GPD_MFOS_MFOS3_Msk (0x1ul << SYS_GPD_MFOS_MFOS3_Pos) /*!< SYS_T::GPD_MFOS: MFOS3 Mask */
+
+#define SYS_GPD_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPD_MFOS: MFOS4 Position */
+#define SYS_GPD_MFOS_MFOS4_Msk (0x1ul << SYS_GPD_MFOS_MFOS4_Pos) /*!< SYS_T::GPD_MFOS: MFOS4 Mask */
+
+#define SYS_GPD_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPD_MFOS: MFOS5 Position */
+#define SYS_GPD_MFOS_MFOS5_Msk (0x1ul << SYS_GPD_MFOS_MFOS5_Pos) /*!< SYS_T::GPD_MFOS: MFOS5 Mask */
+
+#define SYS_GPD_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPD_MFOS: MFOS6 Position */
+#define SYS_GPD_MFOS_MFOS6_Msk (0x1ul << SYS_GPD_MFOS_MFOS6_Pos) /*!< SYS_T::GPD_MFOS: MFOS6 Mask */
+
+#define SYS_GPD_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPD_MFOS: MFOS7 Position */
+#define SYS_GPD_MFOS_MFOS7_Msk (0x1ul << SYS_GPD_MFOS_MFOS7_Pos) /*!< SYS_T::GPD_MFOS: MFOS7 Mask */
+
+#define SYS_GPD_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPD_MFOS: MFOS8 Position */
+#define SYS_GPD_MFOS_MFOS8_Msk (0x1ul << SYS_GPD_MFOS_MFOS8_Pos) /*!< SYS_T::GPD_MFOS: MFOS8 Mask */
+
+#define SYS_GPD_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPD_MFOS: MFOS9 Position */
+#define SYS_GPD_MFOS_MFOS9_Msk (0x1ul << SYS_GPD_MFOS_MFOS9_Pos) /*!< SYS_T::GPD_MFOS: MFOS9 Mask */
+
+#define SYS_GPD_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPD_MFOS: MFOS10 Position */
+#define SYS_GPD_MFOS_MFOS10_Msk (0x1ul << SYS_GPD_MFOS_MFOS10_Pos) /*!< SYS_T::GPD_MFOS: MFOS10 Mask */
+
+#define SYS_GPD_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPD_MFOS: MFOS11 Position */
+#define SYS_GPD_MFOS_MFOS11_Msk (0x1ul << SYS_GPD_MFOS_MFOS11_Pos) /*!< SYS_T::GPD_MFOS: MFOS11 Mask */
+
+#define SYS_GPD_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPD_MFOS: MFOS12 Position */
+#define SYS_GPD_MFOS_MFOS12_Msk (0x1ul << SYS_GPD_MFOS_MFOS12_Pos) /*!< SYS_T::GPD_MFOS: MFOS12 Mask */
+
+#define SYS_GPD_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPD_MFOS: MFOS13 Position */
+#define SYS_GPD_MFOS_MFOS13_Msk (0x1ul << SYS_GPD_MFOS_MFOS13_Pos) /*!< SYS_T::GPD_MFOS: MFOS13 Mask */
+
+#define SYS_GPD_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPD_MFOS: MFOS14 Position */
+#define SYS_GPD_MFOS_MFOS14_Msk (0x1ul << SYS_GPD_MFOS_MFOS14_Pos) /*!< SYS_T::GPD_MFOS: MFOS14 Mask */
+
+#define SYS_GPD_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPD_MFOS: MFOS15 Position */
+#define SYS_GPD_MFOS_MFOS15_Msk (0x1ul << SYS_GPD_MFOS_MFOS15_Pos) /*!< SYS_T::GPD_MFOS: MFOS15 Mask */
+
+#define SYS_GPE_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPE_MFOS: MFOS0 Position */
+#define SYS_GPE_MFOS_MFOS0_Msk (0x1ul << SYS_GPE_MFOS_MFOS0_Pos) /*!< SYS_T::GPE_MFOS: MFOS0 Mask */
+
+#define SYS_GPE_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPE_MFOS: MFOS1 Position */
+#define SYS_GPE_MFOS_MFOS1_Msk (0x1ul << SYS_GPE_MFOS_MFOS1_Pos) /*!< SYS_T::GPE_MFOS: MFOS1 Mask */
+
+#define SYS_GPE_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPE_MFOS: MFOS2 Position */
+#define SYS_GPE_MFOS_MFOS2_Msk (0x1ul << SYS_GPE_MFOS_MFOS2_Pos) /*!< SYS_T::GPE_MFOS: MFOS2 Mask */
+
+#define SYS_GPE_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPE_MFOS: MFOS3 Position */
+#define SYS_GPE_MFOS_MFOS3_Msk (0x1ul << SYS_GPE_MFOS_MFOS3_Pos) /*!< SYS_T::GPE_MFOS: MFOS3 Mask */
+
+#define SYS_GPE_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPE_MFOS: MFOS4 Position */
+#define SYS_GPE_MFOS_MFOS4_Msk (0x1ul << SYS_GPE_MFOS_MFOS4_Pos) /*!< SYS_T::GPE_MFOS: MFOS4 Mask */
+
+#define SYS_GPE_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPE_MFOS: MFOS5 Position */
+#define SYS_GPE_MFOS_MFOS5_Msk (0x1ul << SYS_GPE_MFOS_MFOS5_Pos) /*!< SYS_T::GPE_MFOS: MFOS5 Mask */
+
+#define SYS_GPE_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPE_MFOS: MFOS6 Position */
+#define SYS_GPE_MFOS_MFOS6_Msk (0x1ul << SYS_GPE_MFOS_MFOS6_Pos) /*!< SYS_T::GPE_MFOS: MFOS6 Mask */
+
+#define SYS_GPE_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPE_MFOS: MFOS7 Position */
+#define SYS_GPE_MFOS_MFOS7_Msk (0x1ul << SYS_GPE_MFOS_MFOS7_Pos) /*!< SYS_T::GPE_MFOS: MFOS7 Mask */
+
+#define SYS_GPE_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPE_MFOS: MFOS8 Position */
+#define SYS_GPE_MFOS_MFOS8_Msk (0x1ul << SYS_GPE_MFOS_MFOS8_Pos) /*!< SYS_T::GPE_MFOS: MFOS8 Mask */
+
+#define SYS_GPE_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPE_MFOS: MFOS9 Position */
+#define SYS_GPE_MFOS_MFOS9_Msk (0x1ul << SYS_GPE_MFOS_MFOS9_Pos) /*!< SYS_T::GPE_MFOS: MFOS9 Mask */
+
+#define SYS_GPE_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPE_MFOS: MFOS10 Position */
+#define SYS_GPE_MFOS_MFOS10_Msk (0x1ul << SYS_GPE_MFOS_MFOS10_Pos) /*!< SYS_T::GPE_MFOS: MFOS10 Mask */
+
+#define SYS_GPE_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPE_MFOS: MFOS11 Position */
+#define SYS_GPE_MFOS_MFOS11_Msk (0x1ul << SYS_GPE_MFOS_MFOS11_Pos) /*!< SYS_T::GPE_MFOS: MFOS11 Mask */
+
+#define SYS_GPE_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPE_MFOS: MFOS12 Position */
+#define SYS_GPE_MFOS_MFOS12_Msk (0x1ul << SYS_GPE_MFOS_MFOS12_Pos) /*!< SYS_T::GPE_MFOS: MFOS12 Mask */
+
+#define SYS_GPE_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPE_MFOS: MFOS13 Position */
+#define SYS_GPE_MFOS_MFOS13_Msk (0x1ul << SYS_GPE_MFOS_MFOS13_Pos) /*!< SYS_T::GPE_MFOS: MFOS13 Mask */
+
+#define SYS_GPE_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPE_MFOS: MFOS14 Position */
+#define SYS_GPE_MFOS_MFOS14_Msk (0x1ul << SYS_GPE_MFOS_MFOS14_Pos) /*!< SYS_T::GPE_MFOS: MFOS14 Mask */
+
+#define SYS_GPE_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPE_MFOS: MFOS15 Position */
+#define SYS_GPE_MFOS_MFOS15_Msk (0x1ul << SYS_GPE_MFOS_MFOS15_Pos) /*!< SYS_T::GPE_MFOS: MFOS15 Mask */
+
+#define SYS_GPF_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPF_MFOS: MFOS0 Position */
+#define SYS_GPF_MFOS_MFOS0_Msk (0x1ul << SYS_GPF_MFOS_MFOS0_Pos) /*!< SYS_T::GPF_MFOS: MFOS0 Mask */
+
+#define SYS_GPF_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPF_MFOS: MFOS1 Position */
+#define SYS_GPF_MFOS_MFOS1_Msk (0x1ul << SYS_GPF_MFOS_MFOS1_Pos) /*!< SYS_T::GPF_MFOS: MFOS1 Mask */
+
+#define SYS_GPF_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPF_MFOS: MFOS2 Position */
+#define SYS_GPF_MFOS_MFOS2_Msk (0x1ul << SYS_GPF_MFOS_MFOS2_Pos) /*!< SYS_T::GPF_MFOS: MFOS2 Mask */
+
+#define SYS_GPF_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPF_MFOS: MFOS3 Position */
+#define SYS_GPF_MFOS_MFOS3_Msk (0x1ul << SYS_GPF_MFOS_MFOS3_Pos) /*!< SYS_T::GPF_MFOS: MFOS3 Mask */
+
+#define SYS_GPF_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPF_MFOS: MFOS4 Position */
+#define SYS_GPF_MFOS_MFOS4_Msk (0x1ul << SYS_GPF_MFOS_MFOS4_Pos) /*!< SYS_T::GPF_MFOS: MFOS4 Mask */
+
+#define SYS_GPF_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPF_MFOS: MFOS5 Position */
+#define SYS_GPF_MFOS_MFOS5_Msk (0x1ul << SYS_GPF_MFOS_MFOS5_Pos) /*!< SYS_T::GPF_MFOS: MFOS5 Mask */
+
+#define SYS_GPF_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPF_MFOS: MFOS6 Position */
+#define SYS_GPF_MFOS_MFOS6_Msk (0x1ul << SYS_GPF_MFOS_MFOS6_Pos) /*!< SYS_T::GPF_MFOS: MFOS6 Mask */
+
+#define SYS_GPF_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPF_MFOS: MFOS7 Position */
+#define SYS_GPF_MFOS_MFOS7_Msk (0x1ul << SYS_GPF_MFOS_MFOS7_Pos) /*!< SYS_T::GPF_MFOS: MFOS7 Mask */
+
+#define SYS_GPF_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPF_MFOS: MFOS8 Position */
+#define SYS_GPF_MFOS_MFOS8_Msk (0x1ul << SYS_GPF_MFOS_MFOS8_Pos) /*!< SYS_T::GPF_MFOS: MFOS8 Mask */
+
+#define SYS_GPF_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPF_MFOS: MFOS9 Position */
+#define SYS_GPF_MFOS_MFOS9_Msk (0x1ul << SYS_GPF_MFOS_MFOS9_Pos) /*!< SYS_T::GPF_MFOS: MFOS9 Mask */
+
+#define SYS_GPF_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPF_MFOS: MFOS10 Position */
+#define SYS_GPF_MFOS_MFOS10_Msk (0x1ul << SYS_GPF_MFOS_MFOS10_Pos) /*!< SYS_T::GPF_MFOS: MFOS10 Mask */
+
+#define SYS_GPF_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPF_MFOS: MFOS11 Position */
+#define SYS_GPF_MFOS_MFOS11_Msk (0x1ul << SYS_GPF_MFOS_MFOS11_Pos) /*!< SYS_T::GPF_MFOS: MFOS11 Mask */
+
+#define SYS_GPF_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPF_MFOS: MFOS12 Position */
+#define SYS_GPF_MFOS_MFOS12_Msk (0x1ul << SYS_GPF_MFOS_MFOS12_Pos) /*!< SYS_T::GPF_MFOS: MFOS12 Mask */
+
+#define SYS_GPF_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPF_MFOS: MFOS13 Position */
+#define SYS_GPF_MFOS_MFOS13_Msk (0x1ul << SYS_GPF_MFOS_MFOS13_Pos) /*!< SYS_T::GPF_MFOS: MFOS13 Mask */
+
+#define SYS_GPF_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPF_MFOS: MFOS14 Position */
+#define SYS_GPF_MFOS_MFOS14_Msk (0x1ul << SYS_GPF_MFOS_MFOS14_Pos) /*!< SYS_T::GPF_MFOS: MFOS14 Mask */
+
+#define SYS_GPF_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPF_MFOS: MFOS15 Position */
+#define SYS_GPF_MFOS_MFOS15_Msk (0x1ul << SYS_GPF_MFOS_MFOS15_Pos) /*!< SYS_T::GPF_MFOS: MFOS15 Mask */
+
+#define SYS_GPG_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPG_MFOS: MFOS0 Position */
+#define SYS_GPG_MFOS_MFOS0_Msk (0x1ul << SYS_GPG_MFOS_MFOS0_Pos) /*!< SYS_T::GPG_MFOS: MFOS0 Mask */
+
+#define SYS_GPG_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPG_MFOS: MFOS1 Position */
+#define SYS_GPG_MFOS_MFOS1_Msk (0x1ul << SYS_GPG_MFOS_MFOS1_Pos) /*!< SYS_T::GPG_MFOS: MFOS1 Mask */
+
+#define SYS_GPG_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPG_MFOS: MFOS2 Position */
+#define SYS_GPG_MFOS_MFOS2_Msk (0x1ul << SYS_GPG_MFOS_MFOS2_Pos) /*!< SYS_T::GPG_MFOS: MFOS2 Mask */
+
+#define SYS_GPG_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPG_MFOS: MFOS3 Position */
+#define SYS_GPG_MFOS_MFOS3_Msk (0x1ul << SYS_GPG_MFOS_MFOS3_Pos) /*!< SYS_T::GPG_MFOS: MFOS3 Mask */
+
+#define SYS_GPG_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPG_MFOS: MFOS4 Position */
+#define SYS_GPG_MFOS_MFOS4_Msk (0x1ul << SYS_GPG_MFOS_MFOS4_Pos) /*!< SYS_T::GPG_MFOS: MFOS4 Mask */
+
+#define SYS_GPG_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPG_MFOS: MFOS5 Position */
+#define SYS_GPG_MFOS_MFOS5_Msk (0x1ul << SYS_GPG_MFOS_MFOS5_Pos) /*!< SYS_T::GPG_MFOS: MFOS5 Mask */
+
+#define SYS_GPG_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPG_MFOS: MFOS6 Position */
+#define SYS_GPG_MFOS_MFOS6_Msk (0x1ul << SYS_GPG_MFOS_MFOS6_Pos) /*!< SYS_T::GPG_MFOS: MFOS6 Mask */
+
+#define SYS_GPG_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPG_MFOS: MFOS7 Position */
+#define SYS_GPG_MFOS_MFOS7_Msk (0x1ul << SYS_GPG_MFOS_MFOS7_Pos) /*!< SYS_T::GPG_MFOS: MFOS7 Mask */
+
+#define SYS_GPG_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPG_MFOS: MFOS8 Position */
+#define SYS_GPG_MFOS_MFOS8_Msk (0x1ul << SYS_GPG_MFOS_MFOS8_Pos) /*!< SYS_T::GPG_MFOS: MFOS8 Mask */
+
+#define SYS_GPG_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPG_MFOS: MFOS9 Position */
+#define SYS_GPG_MFOS_MFOS9_Msk (0x1ul << SYS_GPG_MFOS_MFOS9_Pos) /*!< SYS_T::GPG_MFOS: MFOS9 Mask */
+
+#define SYS_GPG_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPG_MFOS: MFOS10 Position */
+#define SYS_GPG_MFOS_MFOS10_Msk (0x1ul << SYS_GPG_MFOS_MFOS10_Pos) /*!< SYS_T::GPG_MFOS: MFOS10 Mask */
+
+#define SYS_GPG_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPG_MFOS: MFOS11 Position */
+#define SYS_GPG_MFOS_MFOS11_Msk (0x1ul << SYS_GPG_MFOS_MFOS11_Pos) /*!< SYS_T::GPG_MFOS: MFOS11 Mask */
+
+#define SYS_GPG_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPG_MFOS: MFOS12 Position */
+#define SYS_GPG_MFOS_MFOS12_Msk (0x1ul << SYS_GPG_MFOS_MFOS12_Pos) /*!< SYS_T::GPG_MFOS: MFOS12 Mask */
+
+#define SYS_GPG_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPG_MFOS: MFOS13 Position */
+#define SYS_GPG_MFOS_MFOS13_Msk (0x1ul << SYS_GPG_MFOS_MFOS13_Pos) /*!< SYS_T::GPG_MFOS: MFOS13 Mask */
+
+#define SYS_GPG_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPG_MFOS: MFOS14 Position */
+#define SYS_GPG_MFOS_MFOS14_Msk (0x1ul << SYS_GPG_MFOS_MFOS14_Pos) /*!< SYS_T::GPG_MFOS: MFOS14 Mask */
+
+#define SYS_GPG_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPG_MFOS: MFOS15 Position */
+#define SYS_GPG_MFOS_MFOS15_Msk (0x1ul << SYS_GPG_MFOS_MFOS15_Pos) /*!< SYS_T::GPG_MFOS: MFOS15 Mask */
+
+#define SYS_GPH_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPH_MFOS: MFOS0 Position */
+#define SYS_GPH_MFOS_MFOS0_Msk (0x1ul << SYS_GPH_MFOS_MFOS0_Pos) /*!< SYS_T::GPH_MFOS: MFOS0 Mask */
+
+#define SYS_GPH_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPH_MFOS: MFOS1 Position */
+#define SYS_GPH_MFOS_MFOS1_Msk (0x1ul << SYS_GPH_MFOS_MFOS1_Pos) /*!< SYS_T::GPH_MFOS: MFOS1 Mask */
+
+#define SYS_GPH_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPH_MFOS: MFOS2 Position */
+#define SYS_GPH_MFOS_MFOS2_Msk (0x1ul << SYS_GPH_MFOS_MFOS2_Pos) /*!< SYS_T::GPH_MFOS: MFOS2 Mask */
+
+#define SYS_GPH_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPH_MFOS: MFOS3 Position */
+#define SYS_GPH_MFOS_MFOS3_Msk (0x1ul << SYS_GPH_MFOS_MFOS3_Pos) /*!< SYS_T::GPH_MFOS: MFOS3 Mask */
+
+#define SYS_GPH_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPH_MFOS: MFOS4 Position */
+#define SYS_GPH_MFOS_MFOS4_Msk (0x1ul << SYS_GPH_MFOS_MFOS4_Pos) /*!< SYS_T::GPH_MFOS: MFOS4 Mask */
+
+#define SYS_GPH_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPH_MFOS: MFOS5 Position */
+#define SYS_GPH_MFOS_MFOS5_Msk (0x1ul << SYS_GPH_MFOS_MFOS5_Pos) /*!< SYS_T::GPH_MFOS: MFOS5 Mask */
+
+#define SYS_GPH_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPH_MFOS: MFOS6 Position */
+#define SYS_GPH_MFOS_MFOS6_Msk (0x1ul << SYS_GPH_MFOS_MFOS6_Pos) /*!< SYS_T::GPH_MFOS: MFOS6 Mask */
+
+#define SYS_GPH_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPH_MFOS: MFOS7 Position */
+#define SYS_GPH_MFOS_MFOS7_Msk (0x1ul << SYS_GPH_MFOS_MFOS7_Pos) /*!< SYS_T::GPH_MFOS: MFOS7 Mask */
+
+#define SYS_GPH_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPH_MFOS: MFOS8 Position */
+#define SYS_GPH_MFOS_MFOS8_Msk (0x1ul << SYS_GPH_MFOS_MFOS8_Pos) /*!< SYS_T::GPH_MFOS: MFOS8 Mask */
+
+#define SYS_GPH_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPH_MFOS: MFOS9 Position */
+#define SYS_GPH_MFOS_MFOS9_Msk (0x1ul << SYS_GPH_MFOS_MFOS9_Pos) /*!< SYS_T::GPH_MFOS: MFOS9 Mask */
+
+#define SYS_GPH_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPH_MFOS: MFOS10 Position */
+#define SYS_GPH_MFOS_MFOS10_Msk (0x1ul << SYS_GPH_MFOS_MFOS10_Pos) /*!< SYS_T::GPH_MFOS: MFOS10 Mask */
+
+#define SYS_GPH_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPH_MFOS: MFOS11 Position */
+#define SYS_GPH_MFOS_MFOS11_Msk (0x1ul << SYS_GPH_MFOS_MFOS11_Pos) /*!< SYS_T::GPH_MFOS: MFOS11 Mask */
+
+#define SYS_GPH_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPH_MFOS: MFOS12 Position */
+#define SYS_GPH_MFOS_MFOS12_Msk (0x1ul << SYS_GPH_MFOS_MFOS12_Pos) /*!< SYS_T::GPH_MFOS: MFOS12 Mask */
+
+#define SYS_GPH_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPH_MFOS: MFOS13 Position */
+#define SYS_GPH_MFOS_MFOS13_Msk (0x1ul << SYS_GPH_MFOS_MFOS13_Pos) /*!< SYS_T::GPH_MFOS: MFOS13 Mask */
+
+#define SYS_GPH_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPH_MFOS: MFOS14 Position */
+#define SYS_GPH_MFOS_MFOS14_Msk (0x1ul << SYS_GPH_MFOS_MFOS14_Pos) /*!< SYS_T::GPH_MFOS: MFOS14 Mask */
+
+#define SYS_GPH_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPH_MFOS: MFOS15 Position */
+#define SYS_GPH_MFOS_MFOS15_Msk (0x1ul << SYS_GPH_MFOS_MFOS15_Pos) /*!< SYS_T::GPH_MFOS: MFOS15 Mask */
+
+#define SYS_SRAM_INTCTL_PERRIEN_Pos (0) /*!< SYS_T::SRAM_INTCTL: PERRIEN Position */
+#define SYS_SRAM_INTCTL_PERRIEN_Msk (0x1ul << SYS_SRAM_INTCTL_PERRIEN_Pos) /*!< SYS_T::SRAM_INTCTL: PERRIEN Mask */
+
+#define SYS_SRAM_STATUS_PERRIF_Pos (0) /*!< SYS_T::SRAM_STATUS: PERRIF Position */
+#define SYS_SRAM_STATUS_PERRIF_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF_Pos) /*!< SYS_T::SRAM_STATUS: PERRIF Mask */
+
+#define SYS_SRAM_ERRADDR_ERRADDR_Pos (0) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Position */
+#define SYS_SRAM_ERRADDR_ERRADDR_Msk (0xfffffffful << SYS_SRAM_ERRADDR_ERRADDR_Pos) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Mask */
+
+#define SYS_SRAM_BISTCTL_SRBIST0_Pos (0) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Position */
+#define SYS_SRAM_BISTCTL_SRBIST0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Mask */
+
+#define SYS_SRAM_BISTCTL_SRBIST1_Pos (1) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Position */
+#define SYS_SRAM_BISTCTL_SRBIST1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Mask */
+
+#define SYS_SRAM_BISTCTL_CRBIST_Pos (2) /*!< SYS_T::SRAM_BISTCTL: CRBIST Position */
+#define SYS_SRAM_BISTCTL_CRBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CRBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CRBIST Mask */
+
+#define SYS_SRAM_BISTCTL_CANBIST_Pos (3) /*!< SYS_T::SRAM_BISTCTL: CANBIST Position */
+#define SYS_SRAM_BISTCTL_CANBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CANBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CANBIST Mask */
+
+#define SYS_SRAM_BISTCTL_USBBIST_Pos (4) /*!< SYS_T::SRAM_BISTCTL: USBBIST Position */
+#define SYS_SRAM_BISTCTL_USBBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_USBBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: USBBIST Mask */
+
+#define SYS_SRAM_BISTCTL_SPIMBIST_Pos (5) /*!< SYS_T::SRAM_BISTCTL: SPIMBIST Position */
+#define SYS_SRAM_BISTCTL_SPIMBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_SPIMBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: SPIMBIST Mask */
+
+#define SYS_SRAM_BISTCTL_EMCBIST_Pos (6) /*!< SYS_T::SRAM_BISTCTL: EMCBIST Position */
+#define SYS_SRAM_BISTCTL_EMCBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_EMCBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: EMCBIST Mask */
+
+#define SYS_SRAM_BISTCTL_PDMABIST_Pos (7) /*!< SYS_T::SRAM_BISTCTL: PDMABIST Position */
+#define SYS_SRAM_BISTCTL_PDMABIST_Msk (0x1ul << SYS_SRAM_BISTCTL_PDMABIST_Pos) /*!< SYS_T::SRAM_BISTCTL: PDMABIST Mask */
+
+#define SYS_SRAM_BISTCTL_HSUSBDBIST_Pos (8) /*!< SYS_T::SRAM_BISTCTL: HSUSBDBIST Position*/
+#define SYS_SRAM_BISTCTL_HSUSBDBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_HSUSBDBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: HSUSBDBIST Mask */
+
+#define SYS_SRAM_BISTCTL_HSUSBHBIST_Pos (9) /*!< SYS_T::SRAM_BISTCTL: HSUSBHBIST Position*/
+#define SYS_SRAM_BISTCTL_HSUSBHBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_HSUSBHBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: HSUSBHBIST Mask */
+
+#define SYS_SRAM_BISTCTL_SRB0S0_Pos (16) /*!< SYS_T::SRAM_BISTCTL: SRB0S0 Position */
+#define SYS_SRAM_BISTCTL_SRB0S0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB0S0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB0S0 Mask */
+
+#define SYS_SRAM_BISTCTL_SRB0S1_Pos (17) /*!< SYS_T::SRAM_BISTCTL: SRB0S1 Position */
+#define SYS_SRAM_BISTCTL_SRB0S1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB0S1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB0S1 Mask */
+
+#define SYS_SRAM_BISTCTL_SRB1S0_Pos (18) /*!< SYS_T::SRAM_BISTCTL: SRB1S0 Position */
+#define SYS_SRAM_BISTCTL_SRB1S0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S0 Mask */
+
+#define SYS_SRAM_BISTCTL_SRB1S1_Pos (19) /*!< SYS_T::SRAM_BISTCTL: SRB1S1 Position */
+#define SYS_SRAM_BISTCTL_SRB1S1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S1 Mask */
+
+#define SYS_SRAM_BISTCTL_SRB1S2_Pos (20) /*!< SYS_T::SRAM_BISTCTL: SRB1S2 Position */
+#define SYS_SRAM_BISTCTL_SRB1S2_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S2_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S2 Mask */
+
+#define SYS_SRAM_BISTCTL_SRB1S3_Pos (21) /*!< SYS_T::SRAM_BISTCTL: SRB1S3 Position */
+#define SYS_SRAM_BISTCTL_SRB1S3_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S3_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S3 Mask */
+
+#define SYS_SRAM_BISTCTL_SRB1S4_Pos (22) /*!< SYS_T::SRAM_BISTCTL: SRB1S4 Position */
+#define SYS_SRAM_BISTCTL_SRB1S4_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S4_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S4 Mask */
+
+#define SYS_SRAM_BISTCTL_SRB1S5_Pos (23) /*!< SYS_T::SRAM_BISTCTL: SRB1S5 Position */
+#define SYS_SRAM_BISTCTL_SRB1S5_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S5_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S5 Mask */
+
+#define SYS_SRAM_BISTSTS_SRBISTEF0_Pos (0) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Position*/
+#define SYS_SRAM_BISTSTS_SRBISTEF0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Mask */
+
+#define SYS_SRAM_BISTSTS_SRBISTEF1_Pos (1) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Position*/
+#define SYS_SRAM_BISTSTS_SRBISTEF1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Mask */
+
+#define SYS_SRAM_BISTSTS_CRBISTEF_Pos (2) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Position */
+#define SYS_SRAM_BISTSTS_CRBISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBISTEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Mask */
+
+#define SYS_SRAM_BISTSTS_CANBEF_Pos (3) /*!< SYS_T::SRAM_BISTSTS: CANBEF Position */
+#define SYS_SRAM_BISTSTS_CANBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEF Mask */
+
+#define SYS_SRAM_BISTSTS_USBBEF_Pos (4) /*!< SYS_T::SRAM_BISTSTS: USBBEF Position */
+#define SYS_SRAM_BISTSTS_USBBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEF Mask */
+
+#define SYS_SRAM_BISTSTS_SRBEND0_Pos (16) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Position */
+#define SYS_SRAM_BISTSTS_SRBEND0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Mask */
+
+#define SYS_SRAM_BISTSTS_SRBEND1_Pos (17) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Position */
+#define SYS_SRAM_BISTSTS_SRBEND1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Mask */
+
+#define SYS_SRAM_BISTSTS_CRBEND_Pos (18) /*!< SYS_T::SRAM_BISTSTS: CRBEND Position */
+#define SYS_SRAM_BISTSTS_CRBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBEND Mask */
+
+#define SYS_SRAM_BISTSTS_CANBEND_Pos (19) /*!< SYS_T::SRAM_BISTSTS: CANBEND Position */
+#define SYS_SRAM_BISTSTS_CANBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEND Mask */
+
+#define SYS_SRAM_BISTSTS_USBBEND_Pos (20) /*!< SYS_T::SRAM_BISTSTS: USBBEND Position */
+#define SYS_SRAM_BISTSTS_USBBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEND Mask */
+
+#define SYS_IRCTCTL_FREQSEL_Pos (0) /*!< SYS_T::IRCTCTL: FREQSEL Position */
+#define SYS_IRCTCTL_FREQSEL_Msk (0x3ul << SYS_IRCTCTL_FREQSEL_Pos) /*!< SYS_T::IRCTCTL: FREQSEL Mask */
+
+#define SYS_IRCTCTL_LOOPSEL_Pos (4) /*!< SYS_T::IRCTCTL: LOOPSEL Position */
+#define SYS_IRCTCTL_LOOPSEL_Msk (0x3ul << SYS_IRCTCTL_LOOPSEL_Pos) /*!< SYS_T::IRCTCTL: LOOPSEL Mask */
+
+#define SYS_IRCTCTL_RETRYCNT_Pos (6) /*!< SYS_T::IRCTCTL: RETRYCNT Position */
+#define SYS_IRCTCTL_RETRYCNT_Msk (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos) /*!< SYS_T::IRCTCTL: RETRYCNT Mask */
+
+#define SYS_IRCTCTL_CESTOPEN_Pos (8) /*!< SYS_T::IRCTCTL: CESTOPEN Position */
+#define SYS_IRCTCTL_CESTOPEN_Msk (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos) /*!< SYS_T::IRCTCTL: CESTOPEN Mask */
+
+#define SYS_IRCTCTL_REFCKSEL_Pos (10) /*!< SYS_T::IRCTCTL: REFCKSEL Position */
+#define SYS_IRCTCTL_REFCKSEL_Msk (0x1ul << SYS_IRCTCTL_REFCKSEL_Pos) /*!< SYS_T::IRCTCTL: REFCKSEL Mask */
+
+#define SYS_IRCTIEN_TFAILIEN_Pos (1) /*!< SYS_T::IRCTIEN: TFAILIEN Position */
+#define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos) /*!< SYS_T::IRCTIEN: TFAILIEN Mask */
+
+#define SYS_IRCTIEN_CLKEIEN_Pos (2) /*!< SYS_T::IRCTIEN: CLKEIEN Position */
+#define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos) /*!< SYS_T::IRCTIEN: CLKEIEN Mask */
+
+#define SYS_IRCTISTS_FREQLOCK_Pos (0) /*!< SYS_T::IRCTISTS: FREQLOCK Position */
+#define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos) /*!< SYS_T::IRCTISTS: FREQLOCK Mask */
+
+#define SYS_IRCTISTS_TFAILIF_Pos (1) /*!< SYS_T::IRCTISTS: TFAILIF Position */
+#define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos) /*!< SYS_T::IRCTISTS: TFAILIF Mask */
+
+#define SYS_IRCTISTS_CLKERRIF_Pos (2) /*!< SYS_T::IRCTISTS: CLKERRIF Position */
+#define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos) /*!< SYS_T::IRCTISTS: CLKERRIF Mask */
+
+#define SYS_REGLCTL_REGLCTL_Pos (0) /*!< SYS_T::REGLCTL: REGLCTL Position */
+#define SYS_REGLCTL_REGLCTL_Msk (0x1ul << SYS_REGLCTL_REGLCTL_Pos) /*!< SYS_T::REGLCTL: REGLCTL Mask */
+
+#define SYS_PLCTL_PLSEL_Pos (0) /*!< SYS_T::PLCTL: PLSEL Position */
+#define SYS_PLCTL_PLSEL_Msk (0x3ul << SYS_PLCTL_PLSEL_Pos) /*!< SYS_T::PLCTL: PLSEL Mask */
+
+#define SYS_PLCTL_LVSSTEP_Pos (16) /*!< SYS_T::PLCTL: LVSSTEP Position */
+#define SYS_PLCTL_LVSSTEP_Msk (0x3ful << SYS_PLCTL_LVSSTEP_Pos) /*!< SYS_T::PLCTL: LVSSTEP Mask */
+
+#define SYS_PLCTL_LVSPRD_Pos (24) /*!< SYS_T::PLCTL: LVSPRD Position */
+#define SYS_PLCTL_LVSPRD_Msk (0xfful << SYS_PLCTL_LVSPRD_Pos) /*!< SYS_T::PLCTL: LVSPRD Mask */
+
+#define SYS_PLSTS_PLCBUSY_Pos (0) /*!< SYS_T::PLSTS: PLCBUSY Position */
+#define SYS_PLSTS_PLCBUSY_Msk (0x1ul << SYS_PLSTS_PLCBUSY_Pos) /*!< SYS_T::PLSTS: PLCBUSY Mask */
+
+#define SYS_PLSTS_PLSTATUS_Pos (8) /*!< SYS_T::PLSTS: PLSTATUS Position */
+#define SYS_PLSTS_PLSTATUS_Msk (0x3ul << SYS_PLSTS_PLSTATUS_Pos) /*!< SYS_T::PLSTS: PLSTATUS Mask */
+
+#define SYS_AHBMCTL_INTACTEN_Pos (0) /*!< SYS_T::AHBMCTL: INTACTEN Position */
+#define SYS_AHBMCTL_INTACTEN_Msk (0x1ul << SYS_AHBMCTL_INTACTEN_Pos) /*!< SYS_T::AHBMCTL: INTACTEN Mask */
+
+/**@}*/ /* SYS_CONST */
+/**@}*/ /* end of SYS register group */
+
+/**
+ @addtogroup NMI NMI Controller (NMI)
+ Memory Mapped Structure for NMI Controller
+@{ */
+
+typedef struct {
+
+
+ /**
+ * @var NMI_T::NMIEN
+ * Offset: 0x00 NMI Source Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BODOUT |BOD NMI Source Enable (Write Protect)
+ * | | |0 = BOD NMI source Disabled.
+ * | | |1 = BOD NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[1] |IRC_INT |IRC TRIM NMI Source Enable (Write Protect)
+ * | | |0 = IRC TRIM NMI source Disabled.
+ * | | |1 = IRC TRIM NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[2] |PWRWU_INT |Power-down Mode Wake-up NMI Source Enable (Write Protect)
+ * | | |0 = Power-down mode wake-up NMI source Disabled.
+ * | | |1 = Power-down mode wake-up NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[3] |SRAM_PERR |SRAM Parity Check NMI Source Enable (Write Protect)
+ * | | |0 = SRAM parity check error NMI source Disabled.
+ * | | |1 = SRAM parity check error NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[4] |CLKFAIL |Clock Fail Detected and IRC Auto Trim Interrupt NMI Source Enable (Write Protect)
+ * | | |0 = Clock fail detected and IRC Auto Trim interrupt NMI source Disabled.
+ * | | |1 = Clock fail detected and IRC Auto Trim interrupt NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[6] |RTC_INT |RTC NMI Source Enable (Write Protect)
+ * | | |0 = RTC NMI source Disabled.
+ * | | |1 = RTC NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[7] |TAMPER_INT|TAMPER_INT NMI Source Enable (Write Protect)
+ * | | |0 = Backup register tamper detected NMI source Disabled.
+ * | | |1 = Backup register tamper detected NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[8] |EINT0 |External Interrupt From PA.6 or PB.5 Pin NMI Source Enable (Write Protect)
+ * | | |0 = External interrupt from PA.6 or PB.5 pin NMI source Disabled.
+ * | | |1 = External interrupt from PA.6 or PB.5 pin NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[9] |EINT1 |External Interrupt From PA.7, PB.4 or PD.15 Pin NMI Source Enable (Write Protect)
+ * | | |0 = External interrupt from PA.7, PB.4 or PD.15 pin NMI source Disabled.
+ * | | |1 = External interrupt from PA.7, PB.4 or PD.15 pin NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[10] |EINT2 |External Interrupt From PB.3 or PC.6 Pin NMI Source Enable (Write Protect)
+ * | | |0 = External interrupt from PB.3 or PC.6 pin NMI source Disabled.
+ * | | |1 = External interrupt from PB.3 or PC.6 pin NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[11] |EINT3 |External Interrupt From PB.2 or PC.7 Pin NMI Source Enable (Write Protect)
+ * | | |0 = External interrupt from PB.2 or PC.7 pin NMI source Disabled.
+ * | | |1 = External interrupt from PB.2 or PC.7 pin NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[12] |EINT4 |External Interrupt From PA.8, PB.6 or PF.15 Pin NMI Source Enable (Write Protect)
+ * | | |0 = External interrupt from PA.8, PB.6 or PF.15 pin NMI source Disabled.
+ * | | |1 = External interrupt from PA.8, PB.6 or PF.15 pin NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[13] |EINT5 |External Interrupt From PB.7 or PF.14 Pin NMI Source Enable (Write Protect)
+ * | | |0 = External interrupt from PB.7 or PF.14 pin NMI source Disabled.
+ * | | |1 = External interrupt from PB.7 or PF.14 pin NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[14] |UART0_INT |UART0 NMI Source Enable (Write Protect)
+ * | | |0 = UART0 NMI source Disabled.
+ * | | |1 = UART0 NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[15] |UART1_INT |UART1 NMI Source Enable (Write Protect)
+ * | | |0 = UART1 NMI source Disabled.
+ * | | |1 = UART1 NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var NMI_T::NMISTS
+ * Offset: 0x04 NMI Source Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BODOUT |BOD Interrupt Flag (Read Only)
+ * | | |0 = BOD interrupt is deasserted.
+ * | | |1 = BOD interrupt is asserted.
+ * |[1] |IRC_INT |IRC TRIM Interrupt Flag (Read Only)
+ * | | |0 = HIRC TRIM interrupt is deasserted.
+ * | | |1 = HIRC TRIM interrupt is asserted.
+ * |[2] |PWRWU_INT |Power-down Mode Wake-up Interrupt Flag (Read Only)
+ * | | |0 = Power-down mode wake-up interrupt is deasserted.
+ * | | |1 = Power-down mode wake-up interrupt is asserted.
+ * |[3] |SRAM_PERR |SRAM ParityCheck Error Interrupt Flag (Read Only)
+ * | | |0 = SRAM parity check error interrupt is deasserted.
+ * | | |1 = SRAM parity check error interrupt is asserted.
+ * |[4] |CLKFAIL |Clock Fail Detected or IRC Auto Trim Interrupt Flag (Read Only)
+ * | | |0 = Clock fail detected or IRC Auto Trim interrupt is deasserted.
+ * | | |1 = Clock fail detected or IRC Auto Trim interrupt is asserted.
+ * |[6] |RTC_INT |RTC Interrupt Flag (Read Only)
+ * | | |0 = RTC interrupt is deasserted.
+ * | | |1 = RTC interrupt is asserted.
+ * |[7] |TAMPER_INT|TAMPER_INT Interrupt Flag (Read Only)
+ * | | |0 = Backup register tamper detected interrupt is deasserted.
+ * | | |1 = Backup register tamper detected interrupt is asserted.
+ * |[8] |EINT0 |External Interrupt From PA.6 or PB.5 Pin Interrupt Flag (Read Only)
+ * | | |0 = External Interrupt from PA.6 or PB.5 interrupt is deasserted.
+ * | | |1 = External Interrupt from PA.6 or PB.5 interrupt is asserted.
+ * |[9] |EINT1 |External Interrupt From PA.7, PB.4 or PD.15 Pin Interrupt Flag (Read Only)
+ * | | |0 = External Interrupt from PA.7, PB.4 or PD.15 interrupt is deasserted.
+ * | | |1 = External Interrupt from PA.7, PB.4 or PD.15 interrupt is asserted.
+ * |[10] |EINT2 |External Interrupt From PB.3 or PC.6 Pin Interrupt Flag (Read Only)
+ * | | |0 = External Interrupt from PB.3 or PC.6 interrupt is deasserted.
+ * | | |1 = External Interrupt from PB.3 or PC.6 interrupt is asserted.
+ * |[11] |EINT3 |External Interrupt From PB.2 or PC.7 Pin Interrupt Flag (Read Only)
+ * | | |0 = External Interrupt from PB.2 or PC.7 interrupt is deasserted.
+ * | | |1 = External Interrupt from PB.2 or PC.7 interrupt is asserted.
+ * |[12] |EINT4 |External Interrupt From PA.8, PB.6 or PF.15 Pin Interrupt Flag (Read Only)
+ * | | |0 = External Interrupt from PA.8, PB.6 or PF.15 interrupt is deasserted.
+ * | | |1 = External Interrupt from PA.8, PB.6 or PF.15 interrupt is asserted.
+ * |[13] |EINT5 |External Interrupt From PB.7 or PF.14 Pin Interrupt Flag (Read Only)
+ * | | |0 = External Interrupt from PB.7 or PF.14 interrupt is deasserted.
+ * | | |1 = External Interrupt from PB.7 or PF.14 interrupt is asserted.
+ * |[14] |UART0_INT |UART0 Interrupt Flag (Read Only)
+ * | | |0 = UART1 interrupt is deasserted.
+ * | | |1 = UART1 interrupt is asserted.
+ * |[15] |UART1_INT |UART1 Interrupt Flag (Read Only)
+ * | | |0 = UART1 interrupt is deasserted.
+ * | | |1 = UART1 interrupt is asserted.
+ */
+ __IO uint32_t NMIEN; /*!< [0x0000] NMI Source Interrupt Enable Register */
+ __I uint32_t NMISTS; /*!< [0x0004] NMI Source Interrupt Status Register */
+
+} NMI_T;
+
+/**
+ @addtogroup NMI_CONST NMI Bit Field Definition
+ Constant Definitions for NMI Controller
+@{ */
+
+#define NMI_NMIEN_BODOUT_Pos (0) /*!< NMI_T::NMIEN: BODOUT Position */
+#define NMI_NMIEN_BODOUT_Msk (0x1ul << NMI_NMIEN_BODOUT_Pos) /*!< NMI_T::NMIEN: BODOUT Mask */
+
+#define NMI_NMIEN_IRC_INT_Pos (1) /*!< NMI_T::NMIEN: IRC_INT Position */
+#define NMI_NMIEN_IRC_INT_Msk (0x1ul << NMI_NMIEN_IRC_INT_Pos) /*!< NMI_T::NMIEN: IRC_INT Mask */
+
+#define NMI_NMIEN_PWRWU_INT_Pos (2) /*!< NMI_T::NMIEN: PWRWU_INT Position */
+#define NMI_NMIEN_PWRWU_INT_Msk (0x1ul << NMI_NMIEN_PWRWU_INT_Pos) /*!< NMI_T::NMIEN: PWRWU_INT Mask */
+
+#define NMI_NMIEN_SRAM_PERR_Pos (3) /*!< NMI_T::NMIEN: SRAM_PERR Position */
+#define NMI_NMIEN_SRAM_PERR_Msk (0x1ul << NMI_NMIEN_SRAM_PERR_Pos) /*!< NMI_T::NMIEN: SRAM_PERR Mask */
+
+#define NMI_NMIEN_CLKFAIL_Pos (4) /*!< NMI_T::NMIEN: CLKFAIL Position */
+#define NMI_NMIEN_CLKFAIL_Msk (0x1ul << NMI_NMIEN_CLKFAIL_Pos) /*!< NMI_T::NMIEN: CLKFAIL Mask */
+
+#define NMI_NMIEN_RTC_INT_Pos (6) /*!< NMI_T::NMIEN: RTC_INT Position */
+#define NMI_NMIEN_RTC_INT_Msk (0x1ul << NMI_NMIEN_RTC_INT_Pos) /*!< NMI_T::NMIEN: RTC_INT Mask */
+
+#define NMI_NMIEN_TAMPER_INT_Pos (7) /*!< NMI_T::NMIEN: TAMPER_INT Position */
+#define NMI_NMIEN_TAMPER_INT_Msk (0x1ul << NMI_NMIEN_TAMPER_INT_Pos) /*!< NMI_T::NMIEN: TAMPER_INT Mask */
+
+#define NMI_NMIEN_EINT0_Pos (8) /*!< NMI_T::NMIEN: EINT0 Position */
+#define NMI_NMIEN_EINT0_Msk (0x1ul << NMI_NMIEN_EINT0_Pos) /*!< NMI_T::NMIEN: EINT0 Mask */
+
+#define NMI_NMIEN_EINT1_Pos (9) /*!< NMI_T::NMIEN: EINT1 Position */
+#define NMI_NMIEN_EINT1_Msk (0x1ul << NMI_NMIEN_EINT1_Pos) /*!< NMI_T::NMIEN: EINT1 Mask */
+
+#define NMI_NMIEN_EINT2_Pos (10) /*!< NMI_T::NMIEN: EINT2 Position */
+#define NMI_NMIEN_EINT2_Msk (0x1ul << NMI_NMIEN_EINT2_Pos) /*!< NMI_T::NMIEN: EINT2 Mask */
+
+#define NMI_NMIEN_EINT3_Pos (11) /*!< NMI_T::NMIEN: EINT3 Position */
+#define NMI_NMIEN_EINT3_Msk (0x1ul << NMI_NMIEN_EINT3_Pos) /*!< NMI_T::NMIEN: EINT3 Mask */
+
+#define NMI_NMIEN_EINT4_Pos (12) /*!< NMI_T::NMIEN: EINT4 Position */
+#define NMI_NMIEN_EINT4_Msk (0x1ul << NMI_NMIEN_EINT4_Pos) /*!< NMI_T::NMIEN: EINT4 Mask */
+
+#define NMI_NMIEN_EINT5_Pos (13) /*!< NMI_T::NMIEN: EINT5 Position */
+#define NMI_NMIEN_EINT5_Msk (0x1ul << NMI_NMIEN_EINT5_Pos) /*!< NMI_T::NMIEN: EINT5 Mask */
+
+#define NMI_NMIEN_UART0_INT_Pos (14) /*!< NMI_T::NMIEN: UART0_INT Position */
+#define NMI_NMIEN_UART0_INT_Msk (0x1ul << NMI_NMIEN_UART0_INT_Pos) /*!< NMI_T::NMIEN: UART0_INT Mask */
+
+#define NMI_NMIEN_UART1_INT_Pos (15) /*!< NMI_T::NMIEN: UART1_INT Position */
+#define NMI_NMIEN_UART1_INT_Msk (0x1ul << NMI_NMIEN_UART1_INT_Pos) /*!< NMI_T::NMIEN: UART1_INT Mask */
+
+#define NMI_NMISTS_BODOUT_Pos (0) /*!< NMI_T::NMISTS: BODOUT Position */
+#define NMI_NMISTS_BODOUT_Msk (0x1ul << NMI_NMISTS_BODOUT_Pos) /*!< NMI_T::NMISTS: BODOUT Mask */
+
+#define NMI_NMISTS_IRC_INT_Pos (1) /*!< NMI_T::NMISTS: IRC_INT Position */
+#define NMI_NMISTS_IRC_INT_Msk (0x1ul << NMI_NMISTS_IRC_INT_Pos) /*!< NMI_T::NMISTS: IRC_INT Mask */
+
+#define NMI_NMISTS_PWRWU_INT_Pos (2) /*!< NMI_T::NMISTS: PWRWU_INT Position */
+#define NMI_NMISTS_PWRWU_INT_Msk (0x1ul << NMI_NMISTS_PWRWU_INT_Pos) /*!< NMI_T::NMISTS: PWRWU_INT Mask */
+
+#define NMI_NMISTS_SRAM_PERR_Pos (3) /*!< NMI_T::NMISTS: SRAM_PERR Position */
+#define NMI_NMISTS_SRAM_PERR_Msk (0x1ul << NMI_NMISTS_SRAM_PERR_Pos) /*!< NMI_T::NMISTS: SRAM_PERR Mask */
+
+#define NMI_NMISTS_CLKFAIL_Pos (4) /*!< NMI_T::NMISTS: CLKFAIL Position */
+#define NMI_NMISTS_CLKFAIL_Msk (0x1ul << NMI_NMISTS_CLKFAIL_Pos) /*!< NMI_T::NMISTS: CLKFAIL Mask */
+
+#define NMI_NMISTS_RTC_INT_Pos (6) /*!< NMI_T::NMISTS: RTC_INT Position */
+#define NMI_NMISTS_RTC_INT_Msk (0x1ul << NMI_NMISTS_RTC_INT_Pos) /*!< NMI_T::NMISTS: RTC_INT Mask */
+
+#define NMI_NMISTS_TAMPER_INT_Pos (7) /*!< NMI_T::NMISTS: TAMPER_INT Position */
+#define NMI_NMISTS_TAMPER_INT_Msk (0x1ul << NMI_NMISTS_TAMPER_INT_Pos) /*!< NMI_T::NMISTS: TAMPER_INT Mask */
+
+#define NMI_NMISTS_EINT0_Pos (8) /*!< NMI_T::NMISTS: EINT0 Position */
+#define NMI_NMISTS_EINT0_Msk (0x1ul << NMI_NMISTS_EINT0_Pos) /*!< NMI_T::NMISTS: EINT0 Mask */
+
+#define NMI_NMISTS_EINT1_Pos (9) /*!< NMI_T::NMISTS: EINT1 Position */
+#define NMI_NMISTS_EINT1_Msk (0x1ul << NMI_NMISTS_EINT1_Pos) /*!< NMI_T::NMISTS: EINT1 Mask */
+
+#define NMI_NMISTS_EINT2_Pos (10) /*!< NMI_T::NMISTS: EINT2 Position */
+#define NMI_NMISTS_EINT2_Msk (0x1ul << NMI_NMISTS_EINT2_Pos) /*!< NMI_T::NMISTS: EINT2 Mask */
+
+#define NMI_NMISTS_EINT3_Pos (11) /*!< NMI_T::NMISTS: EINT3 Position */
+#define NMI_NMISTS_EINT3_Msk (0x1ul << NMI_NMISTS_EINT3_Pos) /*!< NMI_T::NMISTS: EINT3 Mask */
+
+#define NMI_NMISTS_EINT4_Pos (12) /*!< NMI_T::NMISTS: EINT4 Position */
+#define NMI_NMISTS_EINT4_Msk (0x1ul << NMI_NMISTS_EINT4_Pos) /*!< NMI_T::NMISTS: EINT4 Mask */
+
+#define NMI_NMISTS_EINT5_Pos (13) /*!< NMI_T::NMISTS: EINT5 Position */
+#define NMI_NMISTS_EINT5_Msk (0x1ul << NMI_NMISTS_EINT5_Pos) /*!< NMI_T::NMISTS: EINT5 Mask */
+
+#define NMI_NMISTS_UART0_INT_Pos (14) /*!< NMI_T::NMISTS: UART0_INT Position */
+#define NMI_NMISTS_UART0_INT_Msk (0x1ul << NMI_NMISTS_UART0_INT_Pos) /*!< NMI_T::NMISTS: UART0_INT Mask */
+
+#define NMI_NMISTS_UART1_INT_Pos (15) /*!< NMI_T::NMISTS: UART1_INT Position */
+#define NMI_NMISTS_UART1_INT_Msk (0x1ul << NMI_NMISTS_UART1_INT_Pos) /*!< NMI_T::NMISTS: UART1_INT Mask */
+
+/**@}*/ /* NMI_CONST */
+/**@}*/ /* end of NMI register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __SYS_REG_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Include/m480_uart_reg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Include/m480_uart_reg.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1293 @@
+/**************************************************************************//**
+ * @file uart_reg.h
+ * @version V1.00
+ * @brief UART register definition header file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/
+#ifndef __UART_REG_H__
+#define __UART_REG_H__
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART)
+ Memory Mapped Structure for UART Controller
+@{ */
+
+typedef struct {
+
+
+ /**
+ * @var UART_T::DAT
+ * Offset: 0x00 UART Receive/Transmit Buffer Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |DAT |Data Receive/Transmit Buffer
+ * | | |Write Operation:
+ * | | |By writing one byte to this register, the data byte will be stored in transmitter FIFO
+ * | | |The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.
+ * | | |Read Operation:
+ * | | |By reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
+ * |[8] |PARITY |Parity Bit Receive/Transmit Buffer
+ * | | |Write Operation:
+ * | | |By writing to this bit, the parity bit will be stored in transmitter FIFO
+ * | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set,
+ * | | |the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.
+ * | | |Read Operation:
+ * | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.
+ * | | |Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
+ * @var UART_T::INTEN
+ * Offset: 0x04 UART Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RDAIEN |Receive Data Available Interrupt Enable Bit
+ * | | |0 = Receive data available interrupt Disabled.
+ * | | |1 = Receive data available interrupt Enabled.
+ * |[1] |THREIEN |Transmit Holding Register Empty Interrupt Enable Bit
+ * | | |0 = Transmit holding register empty interrupt Disabled.
+ * | | |1 = Transmit holding register empty interrupt Enabled.
+ * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit
+ * | | |0 = Receive Line Status interrupt Disabled.
+ * | | |1 = Receive Line Status interrupt Enabled.
+ * |[3] |MODEMIEN |Modem Status Interrupt Enable Bit
+ * | | |0 = Modem status interrupt Disabled.
+ * | | |1 = Modem status interrupt Enabled.
+ * |[4] |RXTOIEN |RX Time-out Interrupt Enable Bit
+ * | | |0 = RX time-out interrupt Disabled.
+ * | | |1 = RX time-out interrupt Enabled.
+ * |[5] |BUFERRIEN |Buffer Error Interrupt Enable Bit
+ * | | |0 = Buffer error interrupt Disabled.
+ * | | |1 = Buffer error interrupt Enabled.
+ * |[6] |WKIEN |Wake-up Interrupt Enable Bit
+ * | | |0 = Wake-up Interrupt Disabled.
+ * | | |1 = Wake-up Interrupt Enabled.
+ * |[8] |LINIEN |LIN Bus Interrupt Enable Bit
+ * | | |0 = LIN bus interrupt Disabled.
+ * | | |1 = LIN bus interrupt Enabled.
+ * | | |Note: This bit is used for LIN function mode.
+ * |[11] |TOCNTEN |Receive Buffer Time-out Counter Enable Bit
+ * | | |0 = Receive Buffer Time-out counter Disabled.
+ * | | |1 = Receive Buffer Time-out counter Enabled.
+ * |[12] |ATORTSEN |nRTS Auto-flow Control Enable Bit
+ * | | |0 = nRTS auto-flow control Disabled.
+ * | | |1 = nRTS auto-flow control Enabled.
+ * | | |Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
+ * |[13] |ATOCTSEN |nCTS Auto-flow Control Enable Bit
+ * | | |0 = nCTS auto-flow control Disabled.
+ * | | |1 = nCTS auto-flow control Enabled.
+ * | | |Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
+ * |[14] |TXPDMAEN |TX PDMA Enable Bit
+ * | | |This bit can enable or disable TX PDMA service.
+ * | | |0 = TX PDMA Disabled.
+ * | | |1 = TX PDMA Enabled.
+ * | | |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused
+ * | | |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA transmit request operation is stop
+ * | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue.
+ * |[15] |RXPDMAEN |RX PDMA Enable Bit
+ * | | |This bit can enable or disable RX PDMA service.
+ * | | |0 = RX PDMA Disabled.
+ * | | |1 = RX PDMA Enabled.
+ * | | |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused
+ * | | |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA receive request operation is stop
+ * | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
+ * |[18] |ABRIEN |Auto-baud Rate Interrupt Enable Bit
+ * | | |0 = Auto-baud rate interrupt Disabled.
+ * | | |1 = Auto-baud rate interrupt Enabled.
+ * |[22] |TXENDIEN |Transmitter Empty Interrupt Enable Bit
+ * | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
+ * | | |0 = Transmitter empty interrupt Disabled.
+ * | | |1 = Transmitter empty interrupt Enabled.
+ * @var UART_T::FIFO
+ * Offset: 0x08 UART FIFO Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |RXRST |RX Field Software Reset
+ * | | |When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
+ * | | |0 = No effect.
+ * | | |1 = Reset the RX internal state machine and pointers.
+ * | | |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles.
+ * | | |Note2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
+ * |[2] |TXRST |TX Field Software Reset
+ * | | |When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
+ * | | |0 = No effect.
+ * | | |1 = Reset the TX internal state machine and pointers.
+ * | | |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles.
+ * | | |Note2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
+ * |[7:4] |RFITL |RX FIFO Interrupt Trigger Level
+ * | | |When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
+ * | | |0000 = RX FIFO Interrupt Trigger Level is 1 byte.
+ * | | |0001 = RX FIFO Interrupt Trigger Level is 4 bytes.
+ * | | |0010 = RX FIFO Interrupt Trigger Level is 8 bytes.
+ * | | |0011 = RX FIFO Interrupt Trigger Level is 14 bytes.
+ * | | |Others = Reserved.
+ * |[8] |RXOFF |Receiver Disable Bit
+ * | | |The receiver is disabled or not (set 1 to disable receiver).
+ * | | |0 = Receiver Enabled.
+ * | | |1 = Receiver Disabled.
+ * | | |Note: This bit is used for RS-485 Normal Multi-drop mode
+ * | | |It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
+ * |[19:16] |RTSTRGLV |nRTS Trigger Level for Auto-flow Control Use
+ * | | |0000 = nRTS Trigger Level is 1 byte.
+ * | | |0001 = nRTS Trigger Level is 4 bytes.
+ * | | |0010 = nRTS Trigger Level is 8 bytes.
+ * | | |0011 = nRTS Trigger Level is 14 bytes.
+ * | | |Others = Reserved.
+ * | | |Note: This field is used for auto nRTS flow control.
+ * @var UART_T::LINE
+ * Offset: 0x0C UART Line Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |WLS |Word Length Selection
+ * | | |This field sets UART word length.
+ * | | |00 = 5 bits.
+ * | | |01 = 6 bits.
+ * | | |10 = 7 bits.
+ * | | |11 = 8 bits.
+ * |[2] |NSB |Number of 'STOP Bit'
+ * | | |0 = One 'STOP bit' is generated in the transmitted data.
+ * | | |1 = When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data
+ * | | |When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data.
+ * |[3] |PBE |Parity Bit Enable Bit
+ * | | |0 = Parity bit generated Disabled.
+ * | | |1 = Parity bit generated Enabled.
+ * | | |Note: Parity bit is generated on each outgoing character and is checked on each incoming data.
+ * |[4] |EPE |Even Parity Enable Bit
+ * | | |0 = Odd number of logic '1's is transmitted and checked in each word.
+ * | | |1 = Even number of logic '1's is transmitted and checked in each word.
+ * | | |Note: This bit has effect only when PBE (UART_LINE[3]) is set.
+ * |[5] |SPE |Stick Parity Enable Bit
+ * | | |0 = Stick parity Disabled.
+ * | | |1 = Stick parity Enabled.
+ * | | |Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0
+ * | | |If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
+ * |[6] |BCB |Break Control Bit
+ * | | |0 = Break Control Disabled.
+ * | | |1 = Break Control Enabled.
+ * | | |Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0)
+ * | | |This bit acts only on TX line and has no effect on the transmitter logic.
+ * |[7] |PSS |Parity Bit Source Selection
+ * | | |The parity bit can be selected to be generated and checked automatically or by software.
+ * | | |0 = Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically.
+ * | | |1 = Parity bit generated and checked by software.
+ * | | |Note1: This bit has effect only when PBE (UART_LINE[3]) is set.
+ * | | |Note2: If PSS is 0, the parity bit is transmitted and checked automatically
+ * | | |If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]).
+ * |[8] |TXDINV |TX Data Inverted
+ * | | |0 = Transmitted data signal inverted Disabled.
+ * | | |1 = Transmitted data signal inverted Enabled.
+ * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared
+ * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
+ * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
+ * |[9] |RXDINV |RX Data Inverted
+ * | | |0 = Received data signal inverted Disabled.
+ * | | |1 = Received data signal inverted Enabled.
+ * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared
+ * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
+ * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
+ * @var UART_T::MODEM
+ * Offset: 0x10 UART Modem Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |RTS |nRTS (Request-to-send) Signal Control
+ * | | |This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.
+ * | | |0 = nRTS signal is active.
+ * | | |1 = nRTS signal is inactive.
+ * | | |Note1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.
+ * | | |Note2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
+ * |[9] |RTSACTLV |nRTS Pin Active Level
+ * | | |This bit defines the active level state of nRTS pin output.
+ * | | |0 = nRTS pin output is high level active.
+ * | | |1 = nRTS pin output is low level active. (Default)
+ * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared
+ * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
+ * |[13] |RTSSTS |nRTS Pin Status (Read Only)
+ * | | |This bit mirror from nRTS pin output of voltage logic status.
+ * | | |0 = nRTS pin output is low level voltage logic state.
+ * | | |1 = nRTS pin output is high level voltage logic state.
+ * @var UART_T::MODEMSTS
+ * Offset: 0x14 UART Modem Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CTSDETF |Detect nCTS State Change Flag
+ * | | |This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
+ * | | |0 = nCTS input has not change state.
+ * | | |1 = nCTS input has change state.
+ * | | |Note: This bit can be cleared by writing '1' to it.
+ * |[4] |CTSSTS |nCTS Pin Status (Read Only)
+ * | | |This bit mirror from nCTS pin input of voltage logic status.
+ * | | |0 = nCTS pin input is low level voltage logic state.
+ * | | |1 = nCTS pin input is high level voltage logic state.
+ * | | |Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
+ * |[8] |CTSACTLV |nCTS Pin Active Level
+ * | | |This bit defines the active level state of nCTS pin input.
+ * | | |0 = nCTS pin input is high level active.
+ * | | |1 = nCTS pin input is low level active. (Default)
+ * | | |Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared
+ * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
+ * @var UART_T::FIFOSTS
+ * Offset: 0x18 UART FIFO Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RXOVIF |RX Overflow Error Interrupt Flag
+ * | | |This bit is set when RX FIFO overflow.
+ * | | |If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.
+ * | | |0 = RX FIFO is not overflow.
+ * | | |1 = RX FIFO is overflow.
+ * | | |Note: This bit can be cleared by writing '1' to it.
+ * |[1] |ABRDIF |Auto-baud Rate Detect Interrupt Flag
+ * | | |This bit is set to logic '1' when auto-baud rate detect function is finished.
+ * | | |0 = Auto-baud rate detect function is not finished.
+ * | | |1 = Auto-baud rate detect function is finished.
+ * | | |Note: This bit can be cleared by writing '1' to it.
+ * |[2] |ABRDTOIF |Auto-baud Rate Detect Time-out Interrupt Flag
+ * | | |This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.
+ * | | |0 = Auto-baud rate counter is underflow.
+ * | | |1 = Auto-baud rate counter is overflow.
+ * | | |Note: This bit can be cleared by writing '1' to it.
+ * |[3] |ADDRDETF |RS-485 Address Byte Detect Flag
+ * | | |0 = Receiver detects a data that is not an address bit (bit 9 ='0').
+ * | | |1 = Receiver detects a data that is an address bit (bit 9 ='1').
+ * | | |Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.
+ * | | |Note2: This bit can be cleared by writing '1' to it.
+ * |[4] |PEF |Parity Error Flag
+ * | | |This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.
+ * | | |0 = No parity error is generated.
+ * | | |1 = Parity error is generated.
+ * | | |Note: This bit can be cleared by writing '1' to it.
+ * |[5] |FEF |Framing Error Flag
+ * | | |This bit is set to logic 1 whenever the received character does not have a valid 'stop bit'
+ * | | |(that is, the stop bit following the last data bit or parity bit is detected as logic 0).
+ * | | |0 = No framing error is generated.
+ * | | |1 = Framing error is generated.
+ * | | |Note: This bit can be cleared by writing '1' to it.
+ * |[6] |BIF |Break Interrupt Flag
+ * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0)
+ * | | |for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits).
+ * | | |0 = No Break interrupt is generated.
+ * | | |1 = Break interrupt is generated.
+ * | | |Note: This bit can be cleared by writing '1' to it.
+ * |[13:8] |RXPTR |RX FIFO Pointer (Read Only)
+ * | | |This field indicates the RX FIFO Buffer Pointer
+ * | | |When UART receives one byte from external device, RXPTR increases one
+ * | | |When one byte of RX FIFO is read by CPU, RXPTR decreases one.
+ * | | |The Maximum value shown in RXPTR is 15
+ * | | |When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0
+ * | | |As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15
+ * |[14] |RXEMPTY |Receiver FIFO Empty (Read Only)
+ * | | |This bit initiate RX FIFO empty or not.
+ * | | |0 = RX FIFO is not empty.
+ * | | |1 = RX FIFO is empty.
+ * | | |Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high
+ * | | |It will be cleared when UART receives any new data.
+ * |[15] |RXFULL |Receiver FIFO Full (Read Only)
+ * | | |This bit initiates RX FIFO full or not.
+ * | | |0 = RX FIFO is not full.
+ * | | |1 = RX FIFO is full.
+ * | | |Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
+ * |[21:16] |TXPTR |TX FIFO Pointer (Read Only)
+ * | | |This field indicates the TX FIFO Buffer Pointer
+ * | | |When CPU writes one byte into UART_DAT, TXPTR increases one
+ * | | |When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
+ * | | |The Maximum value shown in TXPTR is 15
+ * | | |When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0
+ * | | |As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15
+ * |[22] |TXEMPTY |Transmitter FIFO Empty (Read Only)
+ * | | |This bit indicates TX FIFO empty or not.
+ * | | |0 = TX FIFO is not empty.
+ * | | |1 = TX FIFO is empty.
+ * | | |Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high
+ * | | |It will be cleared when writing data into UART_DAT (TX FIFO not empty).
+ * |[23] |TXFULL |Transmitter FIFO Full (Read Only)
+ * | | |This bit indicates TX FIFO full or not.
+ * | | |0 = TX FIFO is not full.
+ * | | |1 = TX FIFO is full.
+ * | | |Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
+ * |[24] |TXOVIF |TX Overflow Error Interrupt Flag
+ * | | |If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.
+ * | | |0 = TX FIFO is not overflow.
+ * | | |1 = TX FIFO is overflow.
+ * | | |Note: This bit can be cleared by writing '1' to it.
+ * |[28] |TXEMPTYF |Transmitter Empty Flag (Read Only)
+ * | | |This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
+ * | | |0 = TX FIFO is not empty or the STOP bit of the last byte has been not transmitted.
+ * | | |1 = TX FIFO is empty and the STOP bit of the last byte has been transmitted.
+ * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
+ * |[29] |RXIDLE |RX Idle Status (Read Only)
+ * | | |This bit is set by hardware when RX is idle.
+ * | | |0 = RX is busy.
+ * | | |1 = RX is idle. (Default)
+ * |[31] |TXRXACT |TX and RX Active Status (Read Only)
+ * | | |This bit indicates TX and RX are active or inactive.
+ * | | |0 = TX and RX are inactive.
+ * | | |1 = TX and RX are active. (Default)
+ * | | |Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared
+ * | | |The UART controller can not transmit or receive data at this moment
+ * | | |Otherwise this bit is set.
+ * @var UART_T::INTSTS
+ * Offset: 0x1C UART Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RDAIF |Receive Data Available Interrupt Flag
+ * | | |When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set
+ * | | |If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.
+ * | | |0 = No RDA interrupt flag is generated.
+ * | | |1 = RDA interrupt flag is generated.
+ * | | |Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
+ * |[1] |THREIF |Transmit Holding Register Empty Interrupt Flag
+ * | | |This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register
+ * | | |If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.
+ * | | |0 = No THRE interrupt flag is generated.
+ * | | |1 = THRE interrupt flag is generated.
+ * | | |Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
+ * |[2] |RLSIF |Receive Line Interrupt Flag (Read Only)
+ * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set)
+ * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
+ * | | |0 = No RLS interrupt flag is generated.
+ * | | |1 = RLS interrupt flag is generated.
+ * | | |Note1: In RS-485 function mode, this field is set include "receiver detect and received address byte character (bit9 = '1') bit"
+ * | | |At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set.
+ * | | |Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
+ * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
+ * |[3] |MODEMIF |MODEM Interrupt Flag (Read Only)
+ * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1)
+ * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.
+ * | | |0 = No Modem interrupt flag is generated.
+ * | | |1 = Modem interrupt flag is generated.
+ * | | |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
+ * |[4] |RXTOIF |RX Time-out Interrupt Flag (Read Only)
+ * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])
+ * | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.
+ * | | |0 = No RX time-out interrupt flag is generated.
+ * | | |1 = RX time-out interrupt flag is generated.
+ * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
+ * |[5] |BUFERRIF |Buffer Error Interrupt Flag (Read Only)
+ * | | |This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)
+ * | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct
+ * | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
+ * | | |0 = No buffer error interrupt flag is generated.
+ * | | |1 = Buffer error interrupt flag is generated.
+ * | | |Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
+ * |[6] |WKIF |UART Wake-up Interrupt Flag (Read Only)
+ * | | |This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.
+ * | | |0 = No UART wake-up interrupt flag is generated.
+ * | | |1 = UART wake-up interrupt flag is generated.
+ * | | |Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
+ * |[7] |LINIF |LIN Bus Interrupt Flag
+ * | | |This bit is set when LIN slave header detect (SLVHDETF (UART_LINSTS[0] = 1)), LIN break detect (BRKDETF(UART_LINSTS[8]=1)), bit error detect (BITEF(UART_LINSTS[9]=1)), LIN slave ID parity error (SLVIDPEF(UART_LINSTS[2] = 1)) or LIN slave header error detect (SLVHEF (UART_LINSTS[1]))
+ * | | |If LINIEN (UART_INTEN [8]) is enabled the LIN interrupt will be generated.
+ * | | |0 = None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
+ * | | |1 = At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
+ * | | |Note: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7]).
+ * |[8] |RDAINT |Receive Data Available Interrupt Indicator (Read Only)
+ * | | |This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
+ * | | |0 = No RDA interrupt is generated.
+ * | | |1 = RDA interrupt is generated.
+ * |[9] |THREINT |Transmit Holding Register Empty Interrupt Indicator (Read Only)
+ * | | |This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
+ * | | |0 = No THRE interrupt is generated.
+ * | | |1 = THRE interrupt is generated.
+ * |[10] |RLSINT |Receive Line Status Interrupt Indicator (Read Only)
+ * | | |This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
+ * | | |0 = No RLS interrupt is generated.
+ * | | |1 = RLS interrupt is generated.
+ * |[11] |MODEMINT |MODEM Status Interrupt Indicator (Read Only)
+ * | | |This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
+ * | | |0 = No Modem interrupt is generated.
+ * | | |1 = Modem interrupt is generated.
+ * |[12] |RXTOINT |RX Time-out Interrupt Indicator (Read Only)
+ * | | |This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
+ * | | |0 = No RX time-out interrupt is generated.
+ * | | |1 = RX time-out interrupt is generated.
+ * |[13] |BUFERRINT |Buffer Error Interrupt Indicator (Read Only)
+ * | | |This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
+ * | | |0 = No buffer error interrupt is generated.
+ * | | |1 = Buffer error interrupt is generated.
+ * |[14] |WKINT |UART Wake-up Interrupt Indicator (Read Only)
+ * | | |This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
+ * | | |0 = No UART wake-up interrupt is generated.
+ * | | |1 = UART wake-up interrupt is generated.
+ * |[15] |LININT |LIN Bus Interrupt Indicator (Read Only)
+ * | | |This bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1.
+ * | | |0 = No LIN Bus interrupt is generated.
+ * | | |1 = The LIN Bus interrupt is generated.
+ * |[18] |HWRLSIF |PDMA Mode Receive Line Status Flag (Read Only)
+ * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)
+ * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
+ * | | |0 = No RLS interrupt flag is generated in PDMA mode.
+ * | | |1 = RLS interrupt flag is generated in PDMA mode.
+ * | | |Note1: In RS-485 function mode, this field include "receiver detect any address byte received address byte character (bit9 = '1') bit".
+ * | | |Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
+ * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared
+ * |[19] |HWMODIF |PDMA Mode MODEM Interrupt Flag (Read Only)
+ * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS [0] =1))
+ * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.
+ * | | |0 = No Modem interrupt flag is generated in PDMA mode.
+ * | | |1 = Modem interrupt flag is generated in PDMA mode.
+ * | | |Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).
+ * |[20] |HWTOIF |PDMA Mode RX Time-out Interrupt Flag (Read Only)
+ * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])
+ * | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated .
+ * | | |0 = No RX time-out interrupt flag is generated in PDMA mode.
+ * | | |1 = RX time-out interrupt flag is generated in PDMA mode.
+ * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
+ * |[21] |HWBUFEIF |PDMA Mode Buffer Error Interrupt Flag (Read Only)
+ * | | |This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)
+ * | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct
+ * | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
+ * | | |0 = No buffer error interrupt flag is generated in PDMA mode.
+ * | | |1 = Buffer error interrupt flag is generated in PDMA mode.
+ * | | |Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
+ * |[22] |TXENDIF |Transmitter Empty Interrupt Flag
+ * | | |This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)
+ * | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.
+ * | | |0 = No transmitter empty interrupt flag is generated.
+ * | | |1 = Transmitter empty interrupt flag is generated.
+ * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
+ * |[26] |HWRLSINT |PDMA Mode Receive Line Status Interrupt Indicator (Read Only)
+ * | | |This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
+ * | | |0 = No RLS interrupt is generated in PDMA mode.
+ * | | |1 = RLS interrupt is generated in PDMA mode.
+ * |[27] |HWMODINT |PDMA Mode MODEM Status Interrupt Indicator (Read Only)
+ * | | |This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
+ * | | |0 = No Modem interrupt is generated in PDMA mode.
+ * | | |1 = Modem interrupt is generated in PDMA mode.
+ * |[28] |HWTOINT |PDMA Mode RX Time-out Interrupt Indicator (Read Only)
+ * | | |This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
+ * | | |0 = No RX time-out interrupt is generated in PDMA mode.
+ * | | |1 = RX time-out interrupt is generated in PDMA mode.
+ * |[29] |HWBUFEINT |PDMA Mode Buffer Error Interrupt Indicator (Read Only)
+ * | | |This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
+ * | | |0 = No buffer error interrupt is generated in PDMA mode.
+ * | | |1 = Buffer error interrupt is generated in PDMA mode.
+ * |[30] |TXENDINT |Transmitter Empty Interrupt Indicator (Read Only)
+ * | | |This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
+ * | | |0 = No Transmitter Empty interrupt is generated.
+ * | | |1 = Transmitter Empty interrupt is generated.
+ * |[31] |ABRINT |Auto-baud Rate Interrupt Indicator (Read Only)
+ * | | |This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
+ * | | |0 = No Auto-baud Rate interrupt is generated.
+ * | | |1 = The Auto-baud Rate interrupt is generated.
+ * @var UART_T::TOUT
+ * Offset: 0x20 UART Time-out Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |TOIC |Time-out Interrupt Comparator
+ * | | |The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word if time out counter is enabled by setting TOCNTEN (UART_INTEN[11])
+ * | | |Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TOUT[7:0])), a receiver time-out interrupt (RXTOINT(UART_INTSTS[12])) is generated if RXTOIEN (UART_INTEN [4]) enabled
+ * | | |A new incoming data word or RX FIFO empty will clear RXTOIF (UART_INTSTS[4])
+ * | | |In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255
+ * | | |So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer.
+ * |[15:8] |DLY |TX Delay Time Value
+ * | | |This field is used to programming the transfer delay time between the last stop bit and next start bit
+ * | | |The unit is bit time.
+ * @var UART_T::BAUD
+ * Offset: 0x24 UART Baud Rate Divider Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |BRD |Baud Rate Divider
+ * | | |The field indicates the baud rate divider
+ * | | |This filed is used in baud rate calculation
+ * | | |The detail description is shown in Table 7.15-4.
+ * |[27:24] |EDIVM1 |Extra Divider for BAUD Rate Mode 1
+ * | | |This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2
+ * | | |The detail description is shown in Table 7.15-4
+ * |[28] |BAUDM0 |BAUD Rate Mode Selection Bit 0
+ * | | |This bit is baud rate mode selection bit 0
+ * | | |UART provides three baud rate calculation modes
+ * | | |This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode
+ * | | |The detail description is shown in Table 7.15-4.
+ * |[29] |BAUDM1 |BAUD Rate Mode Selection Bit 1
+ * | | |This bit is baud rate mode selection bit 1
+ * | | |UART provides three baud rate calculation modes
+ * | | |This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode
+ * | | |The detail description is shown in Table 7.15-4.
+ * | | |Note: In IrDA mode must be operated in mode 0.
+ * @var UART_T::IRDA
+ * Offset: 0x28 UART IrDA Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |TXEN |IrDA Receiver/Transmitter Selection Enable Bit
+ * | | |0 = IrDA Transmitter Disabled and Receiver Enabled. (Default)
+ * | | |1 = IrDA Transmitter Enabled and Receiver Disabled.
+ * |[5] |TXINV |IrDA Inverse Transmitting Output Signal
+ * | | |0 = None inverse transmitting signal. (Default).
+ * | | |1 = Inverse transmitting output signal.
+ * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared
+ * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
+ * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
+ * |[6] |RXINV |IrDA Inverse Receive Input Signal
+ * | | |0 = None inverse receiving input signal.
+ * | | |1 = Inverse receiving input signal. (Default)
+ * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared
+ * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
+ * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
+ * @var UART_T::ALTCTL
+ * Offset: 0x2C UART Alternate Control/Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |BRKFL |UART LIN Break Field Length
+ * | | |This field indicates a 4-bit LIN TX break field count.
+ * | | |Note1: This break field length is BRKFL + 1.
+ * | | |Note2: According to LIN spec, the reset value is 0xC (break field length = 13).
+ * |[6] |LINRXEN |LIN RX Enable Bit
+ * | | |0 = LIN RX mode Disabled.
+ * | | |1 = LIN RX mode Enabled.
+ * |[7] |LINTXEN |LIN TX Break Mode Enable Bit
+ * | | |0 = LIN TX Break mode Disabled.
+ * | | |1 = LIN TX Break mode Enabled.
+ * | | |Note: When TX break field transfer operation finished, this bit will be cleared automatically.
+ * |[8] |RS485NMM |RS-485 Normal Multi-drop Operation Mode (NMM)
+ * | | |0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled.
+ * | | |1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled.
+ * | | |Note: It cannot be active with RS-485_AAD operation mode.
+ * |[9] |RS485AAD |RS-485 Auto Address Detection Operation Mode (AAD)
+ * | | |0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled.
+ * | | |1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled.
+ * | | |Note: It cannot be active with RS-485_NMM operation mode.
+ * |[10] |RS485AUD |RS-485 Auto Direction Function (AUD)
+ * | | |0 = RS-485 Auto Direction Operation function (AUD) Disabled.
+ * | | |1 = RS-485 Auto Direction Operation function (AUD) Enabled.
+ * | | |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
+ * |[15] |ADDRDEN |RS-485 Address Detection Enable Bit
+ * | | |This bit is used to enable RS-485 Address Detection mode.
+ * | | |0 = Address detection mode Disabled.
+ * | | |1 = Address detection mode Enabled.
+ * | | |Note: This bit is used for RS-485 any operation mode.
+ * |[17] |ABRIF |Auto-baud Rate Interrupt Flag (Read Only)
+ * | | |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
+ * | | |0 = No auto-baud rate interrupt flag is generated.
+ * | | |1 = Auto-baud rate interrupt flag is generated.
+ * | | |Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1])
+ * |[18] |ABRDEN |Auto-baud Rate Detect Enable Bit
+ * | | |0 = Auto-baud rate detect function Disabled.
+ * | | |1 = Auto-baud rate detect function Enabled.
+ * | | |Note : This bit is cleared automatically after auto-baud detection is finished.
+ * |[20:19] |ABRDBITS |Auto-baud Rate Detect Bit Length
+ * | | |00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01.
+ * | | |01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02.
+ * | | |10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08.
+ * | | |11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80.
+ * | | |Note : The calculation of bit number includes the START bit.
+ * |[31:24] |ADDRMV |Address Match Value
+ * | | |This field contains the RS-485 address match values.
+ * | | |Note: This field is used for RS-485 auto address detection mode.
+ * @var UART_T::FUNCSEL
+ * Offset: 0x30 UART Function Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |FUNCSEL |Function Select
+ * | | |00 = UART function.
+ * | | |01 = LIN function.
+ * | | |10 = IrDA function.
+ * | | |11 = RS-485 function.
+ * |[3] |TXRXDIS |TX and RX Disable Bit
+ * | | |Setting this bit can disable TX and RX.
+ * | | |0 = TX and RX Enabled.
+ * | | |1 = TX and RX Disabled.
+ * | | |Note: The TX and RX will not disable immediately when this bit is set
+ * | | |The TX and RX complete current task before disable TX and RX
+ * | | |When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared.
+ * @var UART_T::LINCTL
+ * Offset: 0x34 UART LIN Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SLVEN |LIN Slave Mode Enable Bit
+ * | | |0 = LIN slave mode Disabled.
+ * | | |1 = LIN slave mode Enabled.
+ * |[1] |SLVHDEN |LIN Slave Header Detection Enable Bit
+ * | | |0 = LIN slave header detection Disabled.
+ * | | |1 = LIN slave header detection Enabled.
+ * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
+ * | | |Note2: In LIN function mode, when detect header field (break + sync + frame ID), SLVHDETF (UART_LINSTS [0]) flag will be asserted
+ * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
+ * |[2] |SLVAREN |LIN Slave Automatic Resynchronization Mode Enable Bit
+ * | | |0 = LIN automatic resynchronization Disabled.
+ * | | |1 = LIN automatic resynchronization Enabled.
+ * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
+ * | | |Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).
+ * | | |Note3: The control and interactions of this field are explained in 7.15.5.9 (Slave mode with automatic resynchronization).
+ * |[3] |SLVDUEN |LIN Slave Divider Update Method Enable Bit
+ * | | |0 = UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time).
+ * | | |1 = UART_BAUD is updated at the next received character
+ * | | |User must set the bit before checksum reception.
+ * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
+ * | | |Note2: This bit used for LIN Slave Automatic Resynchronization mode
+ * | | |(for Non-Automatic Resynchronization mode, this bit should be kept cleared)
+ * | | |Note3: The control and interactions of this field are explained in 7.15.5.9 (Slave mode with automatic resynchronization).
+ * |[4] |MUTE |LIN Mute Mode Enable Bit
+ * | | |0 = LIN mute mode Disabled.
+ * | | |1 = LIN mute mode Enabled.
+ * | | |Note: The exit from mute mode condition and each control and interactions of this field are explained in 7.15.5.9 (LIN slave mode).
+ * |[8] |SENDH |LIN TX Send Header Enable Bit
+ * | | |The LIN TX header can be break field or 'break and sync field' or 'break, sync and frame ID field', it is depend on setting HSEL (UART_LINCTL[23:22]).
+ * | | |0 = Send LIN TX header Disabled.
+ * | | |1 = Send LIN TX header Enabled.
+ * | | |Note1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]); user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]).
+ * | | |Note2: When transmitter header field (it may be 'break' or 'break + sync' or 'break + sync + frame ID' selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically.
+ * |[9] |IDPEN |LIN ID Parity Enable Bit
+ * | | |0 = LIN frame ID parity Disabled.
+ * | | |1 = LIN frame ID parity Enabled.
+ * | | |Note1: This bit can be used for LIN master to sending header field (SENDH (UART_LINCTL[8])) = 1 and HSEL (UART_LINCTL[23:22]) = 10 or be used for enable LIN slave received frame ID parity checked.
+ * | | |Note2: This bit is only used when the operation header transmitter is in HSEL (UART_LINCTL[23:22]) = 10
+ * |[10] |BRKDETEN |LIN Break Detection Enable Bit
+ * | | |When detect consecutive dominant greater than 11 bits, and are followed by a delimiter character, the BRKDETF (UART_LINSTS[8]) flag is set at the end of break field
+ * | | |If the LINIEN (UART_INTEN [8])=1, an interrupt will be generated.
+ * | | |0 = LIN break detection Disabled .
+ * | | |1 = LIN break detection Enabled.
+ * |[11] |LINRXOFF |LIN Receiver Disable Bit
+ * | | |If the receiver is enabled (LINRXOFF (UART_LINCTL[11] ) = 0), all received byte data will be accepted and stored in the RX FIFO, and if the receiver is disabled (LINRXOFF (UART_LINCTL[11] = 1), all received byte data will be ignore.
+ * | | |0 = LIN receiver Enabled.
+ * | | |1 = LIN receiver Disabled.
+ * | | |Note: This bit is only valid when operating in LIN function mode (FUNCSEL (UART_FUNCSEL[1:0]) = 01).
+ * |[12] |BITERREN |Bit Error Detect Enable Bit
+ * | | |0 = Bit error detection function Disabled.
+ * | | |1 = Bit error detection function Enabled.
+ * | | |Note: In LIN function mode, when occur bit error, the BITEF (UART_LINSTS[9]) flag will be asserted
+ * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
+ * |[19:16] |BRKFL |LIN Break Field Length
+ * | | |This field indicates a 4-bit LIN TX break field count.
+ * | | |Note1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]), User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).
+ * | | |Note2: This break field length is BRKFL + 1.
+ * | | |Note3: According to LIN spec, the reset value is 12 (break field length = 13).
+ * |[21:20] |BSL |LIN Break/Sync Delimiter Length
+ * | | |00 = The LIN break/sync delimiter length is 1-bit time.
+ * | | |01 = The LIN break/sync delimiter length is 2-bit time.
+ * | | |10 = The LIN break/sync delimiter length is 3-bit time.
+ * | | |11 = The LIN break/sync delimiter length is 4-bit time.
+ * | | |Note: This bit used for LIN master to sending header field.
+ * |[23:22] |HSEL |LIN Header Select
+ * | | |00 = The LIN header includes 'break field'.
+ * | | |01 = The LIN header includes 'break field' and 'sync field'.
+ * | | |10 = The LIN header includes 'break field', 'sync field' and 'frame ID field'.
+ * | | |11 = Reserved.
+ * | | |Note: This bit is used to master mode for LIN to send header field (SENDH (UART_LINCTL [8]) = 1) or used to slave to indicates exit from mute mode condition (MUTE (UART_LINCTL[4] = 1).
+ * |[31:24] |PID |LIN PID Bits
+ * | | |This field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on IDPEN (UART_LINCTL[9]) = 1.
+ * | | |If the parity generated by hardware, user fill ID0~ID5 (PID [29:24] ), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field.
+ * | | |Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).
+ * | | |Note2: This field can be used for LIN master mode or slave mode.
+ * @var UART_T::LINSTS
+ * Offset: 0x38 UART LIN Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SLVHDETF |LIN Slave Header Detection Flag
+ * | | |This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.
+ * | | |0 = LIN header not detected.
+ * | | |1 = LIN header detected (break + sync + frame ID).
+ * | | |Note1: This bit can be cleared by writing 1 to it.
+ * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN slave header detection function (SLVHDEN (UART_LINCTL [1])).
+ * | | |Note3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ('break + sync + frame ID'), the SLVHDETF will be set whether the frame ID correct or not.
+ * |[1] |SLVHEF |LIN Slave Header Error Flag
+ * | | |This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it
+ * | | |The header errors include 'break delimiter is too short (less than 0.5 bit time)', 'frame error in sync field or Identifier field',
+ * | | |'sync field data is not 0x55 in Non-Automatic Resynchronization mode', 'sync field deviation error with Automatic Resynchronization mode',
+ * | | |'sync field measure time-out with Automatic Resynchronization mode' and 'LIN header reception time-out'.
+ * | | |0 = LIN header error not detected.
+ * | | |1 = LIN header error detected.
+ * | | |Note1: This bit can be cleared by writing 1 to it.
+ * | | |Note2: This bit is only valid when UART is operated in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and
+ * | | |enables LIN slave header detection function (SLVHDEN (UART_LINCTL [1])).
+ * |[2] |SLVIDPEF |LIN Slave ID Parity Error Flag
+ * | | |This bit is set by hardware when receipted frame ID parity is not correct.
+ * | | |0 = No active.
+ * | | |1 = Receipted frame ID parity is not correct.
+ * | | |Note1: This bit can be cleared by writing 1 to it.
+ * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0])= 1) and enable LIN frame ID parity check function IDPEN (UART_LINCTL [9]).
+ * |[3] |SLVSYNCF |LIN Slave Sync Field
+ * | | |This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode
+ * | | |When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.
+ * | | |0 = The current character is not at LIN sync state.
+ * | | |1 = The current character is at LIN sync state.
+ * | | |Note1: This bit is only valid when in LIN Slave mode (SLVEN(UART_LINCTL[0]) = 1).
+ * | | |Note2: This bit can be cleared by writing 1 to it.
+ * | | |Note3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header.
+ * |[8] |BRKDETF |LIN Break Detection Flag
+ * | | |This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.
+ * | | |0 = LIN break not detected.
+ * | | |1 = LIN break detected.
+ * | | |Note1: This bit can be cleared by writing 1 to it.
+ * | | |Note2: This bit is only valid when LIN break detection function is enabled (BRKDETEN (UART_LINCTL[10]) =1).
+ * |[9] |BITEF |Bit Error Detect Status Flag
+ * | | |At TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set.
+ * | | |When occur bit error, if the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
+ * | | |0 = Bit error not detected.
+ * | | |1 = Bit error detected.
+ * | | |Note1: This bit can be cleared by writing 1 to it.
+ * | | |Note2: This bit is only valid when enable bit error detection function (BITERREN (UART_LINCTL [12]) = 1).
+ * @var UART_T::BRCOMP
+ * Offset: 0x3C UART Baud Rate Compensation Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8:0] |BRCOMP |Baud Rate Compensation Patten
+ * | | |These 9-bits are used to define the relative bit is compensated or not.
+ * | | |BRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit.
+ * |[31] |BRCOMPDEC |Baud Rate Compensation Decrease
+ * | | |0 = Positive (increase one module clock) compensation for each compensated bit.
+ * | | |1 = Negative (decrease one module clock) compensation for each compensated bit.
+ * @var UART_T::WKCTL
+ * Offset: 0x40 UART Wake-up Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WKCTSEN |nCTS Wake-up Enable Bit
+ * | | |0 = nCTS Wake-up system function Disabled.
+ * | | |1 = nCTS Wake-up system function Enabled, when the system is in Power-down mode, an external.
+ * | | |nCTS change will wake-up system from Power-down mode.
+ * |[1] |WKDATEN |Incoming Data Wake-up Enable Bit
+ * | | |0 = Incoming data wake-up system function Disabled.
+ * | | |1 = Incoming data wake-up system function Enabled, when the system is in Power-down mode,.
+ * | | |incoming data will wake-up system from Power-down mode.
+ * |[2] |WKRFRTEN |Received Data FIFO Reached Threshold Wake-up Enable Bit
+ * | | |0 = Received Data FIFO reached threshold wake-up system function Disabled.
+ * | | |1 = Received Data FIFO reached threshold wake-up system function Enabled, when the system is.
+ * | | |in Power-down mode, Received Data FIFO reached threshold will wake-up system from
+ * | | |Power-down mode.
+ * |[3] |WKRS485EN |RS-485 Address Match (AAD Mode) Wake-up Enable Bit
+ * | | |0 = RS-485 Address Match (AAD mode) wake-up system function Disabled.
+ * | | |1 = RS-485 Address Match (AAD mode) wake-up system function Enabled, when the system is in.
+ * | | |Power-down mode, RS-485 Address Match will wake-up system from Power-down mode.
+ * | | |Note: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode
+ * | | |and ADDRDEN (UART_ALTCTL[15]) is set to 1.
+ * |[4] |WKTOUTEN |Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit
+ * | | |0 = Received Data FIFO reached threshold time-out wake-up system function Disabled.
+ * | | |1 = Received Data FIFO reached threshold time-out wake-up system function Enabled, when the.
+ * | | |system is in Power-down mode, Received Data FIFO reached threshold time-out will wake-up
+ * | | |system from Power-down mode.
+ * | | |Note: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.
+ * @var UART_T::WKSTS
+ * Offset: 0x44 UART Wake-up Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CTSWKF |nCTS Wake-up Flag
+ * | | |This bit is set if chip wake-up from power-down state by nCTS wake-up.
+ * | | |0 = Chip stays in power-down state.
+ * | | |1 = Chip wake-up from power-down state by nCTS wake-up.
+ * | | |Note1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.
+ * | | |Note2: This bit can be cleared by writing '1' to it.
+ * |[1] |DATWKF |Incoming Data Wake-up Flag
+ * | | |This bit is set if chip wake-up from power-down state by data wake-up.
+ * | | |0 = Chip stays in power-down state.
+ * | | |1 = Chip wake-up from power-down state by Incoming Data wake-up.
+ * | | |Note1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.
+ * | | |Note2: This bit can be cleared by writing '1' to it.
+ * |[2] |RFRTWKF |Received Data FIFO Reached Threshold Wake-up Flag
+ * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold
+ * | | |wake-up .
+ * | | |0 = Chip stays in power-down state.
+ * | | |1 = Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up.
+ * | | |Note1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.
+ * | | |Note2: This bit can be cleared by writing '1' to it.
+ * |[3] |RS485WKF |RS-485 Address Match (AAD Mode) Wake-up Flag
+ * | | |This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).
+ * | | |0 = Chip stays in power-down state.
+ * | | |1 = Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up.
+ * | | |Note1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.
+ * | | |Note2: This bit can be cleared by writing '1' to it.
+ * |[4] |TOUTWKF |Received Data FIFO Threshold Time-out Wake-up Flag
+ * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out
+ * | | |wake-up.
+ * | | |0 = Chip stays in power-down state.
+ * | | |1 = Chip wake-up from power-down state by Received Data FIFO reached threshold time-out.
+ * | | |wake-up.
+ * | | |Note1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.
+ * | | |Note2: This bit can be cleared by writing '1' to it.
+ * @var UART_T::DWKCOMP
+ * Offset: 0x48 UART Incoming Data Wake-up Compensation Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |STCOMP |Start Bit Compensation Value
+ * | | |These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode.
+ * | | |Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
+ */
+ __IO uint32_t DAT; /*!< [0x0000] UART Receive/Transmit Buffer Register */
+ __IO uint32_t INTEN; /*!< [0x0004] UART Interrupt Enable Register */
+ __IO uint32_t FIFO; /*!< [0x0008] UART FIFO Control Register */
+ __IO uint32_t LINE; /*!< [0x000c] UART Line Control Register */
+ __IO uint32_t MODEM; /*!< [0x0010] UART Modem Control Register */
+ __IO uint32_t MODEMSTS; /*!< [0x0014] UART Modem Status Register */
+ __IO uint32_t FIFOSTS; /*!< [0x0018] UART FIFO Status Register */
+ __IO uint32_t INTSTS; /*!< [0x001c] UART Interrupt Status Register */
+ __IO uint32_t TOUT; /*!< [0x0020] UART Time-out Register */
+ __IO uint32_t BAUD; /*!< [0x0024] UART Baud Rate Divider Register */
+ __IO uint32_t IRDA; /*!< [0x0028] UART IrDA Control Register */
+ __IO uint32_t ALTCTL; /*!< [0x002c] UART Alternate Control/Status Register */
+ __IO uint32_t FUNCSEL; /*!< [0x0030] UART Function Select Register */
+ __IO uint32_t LINCTL; /*!< [0x0034] UART LIN Control Register */
+ __IO uint32_t LINSTS; /*!< [0x0038] UART LIN Status Register */
+ __IO uint32_t BRCOMP; /*!< [0x003c] UART Baud Rate Compensation Register */
+ __IO uint32_t WKCTL; /*!< [0x0040] UART Wake-up Control Register */
+ __IO uint32_t WKSTS; /*!< [0x0044] UART Wake-up Status Register */
+ __IO uint32_t DWKCOMP; /*!< [0x0048] UART Incoming Data Wake-up Compensation Register */
+
+} UART_T;
+
+/**
+ @addtogroup UART_CONST UART Bit Field Definition
+ Constant Definitions for UART Controller
+@{ */
+
+#define UART_DAT_DAT_Pos (0) /*!< UART_T::DAT: DAT Position */
+#define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) /*!< UART_T::DAT: DAT Mask */
+
+#define UART_DAT_PARITY_Pos (8) /*!< UART_T::DAT: PARITY Position */
+#define UART_DAT_PARITY_Msk (0x1ul << UART_DAT_PARITY_Pos) /*!< UART_T::DAT: PARITY Mask */
+
+#define UART_INTEN_RDAIEN_Pos (0) /*!< UART_T::INTEN: RDAIEN Position */
+#define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) /*!< UART_T::INTEN: RDAIEN Mask */
+
+#define UART_INTEN_THREIEN_Pos (1) /*!< UART_T::INTEN: THREIEN Position */
+#define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) /*!< UART_T::INTEN: THREIEN Mask */
+
+#define UART_INTEN_RLSIEN_Pos (2) /*!< UART_T::INTEN: RLSIEN Position */
+#define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) /*!< UART_T::INTEN: RLSIEN Mask */
+
+#define UART_INTEN_MODEMIEN_Pos (3) /*!< UART_T::INTEN: MODEMIEN Position */
+#define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) /*!< UART_T::INTEN: MODEMIEN Mask */
+
+#define UART_INTEN_RXTOIEN_Pos (4) /*!< UART_T::INTEN: RXTOIEN Position */
+#define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) /*!< UART_T::INTEN: RXTOIEN Mask */
+
+#define UART_INTEN_BUFERRIEN_Pos (5) /*!< UART_T::INTEN: BUFERRIEN Position */
+#define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) /*!< UART_T::INTEN: BUFERRIEN Mask */
+
+#define UART_INTEN_WKIEN_Pos (6) /*!< UART_T::INTEN: WKIEN Position */
+#define UART_INTEN_WKIEN_Msk (0x1ul << UART_INTEN_WKIEN_Pos) /*!< UART_T::INTEN: WKIEN Mask */
+
+#define UART_INTEN_LINIEN_Pos (8) /*!< UART_T::INTEN: LINIEN Position */
+#define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) /*!< UART_T::INTEN: LINIEN Mask */
+
+#define UART_INTEN_TOCNTEN_Pos (11) /*!< UART_T::INTEN: TOCNTEN Position */
+#define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) /*!< UART_T::INTEN: TOCNTEN Mask */
+
+#define UART_INTEN_ATORTSEN_Pos (12) /*!< UART_T::INTEN: ATORTSEN Position */
+#define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) /*!< UART_T::INTEN: ATORTSEN Mask */
+
+#define UART_INTEN_ATOCTSEN_Pos (13) /*!< UART_T::INTEN: ATOCTSEN Position */
+#define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) /*!< UART_T::INTEN: ATOCTSEN Mask */
+
+#define UART_INTEN_TXPDMAEN_Pos (14) /*!< UART_T::INTEN: TXPDMAEN Position */
+#define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) /*!< UART_T::INTEN: TXPDMAEN Mask */
+
+#define UART_INTEN_RXPDMAEN_Pos (15) /*!< UART_T::INTEN: RXPDMAEN Position */
+#define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) /*!< UART_T::INTEN: RXPDMAEN Mask */
+
+#define UART_INTEN_ABRIEN_Pos (18) /*!< UART_T::INTEN: ABRIEN Position */
+#define UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos) /*!< UART_T::INTEN: ABRIEN Mask */
+
+#define UART_INTEN_TXENDIEN_Pos (22) /*!< UART_T::INTEN: TXENDIEN Position */
+#define UART_INTEN_TXENDIEN_Msk (0x1ul << UART_INTEN_TXENDIEN_Pos) /*!< UART_T::INTEN: TXENDIEN Mask */
+
+#define UART_FIFO_RXRST_Pos (1) /*!< UART_T::FIFO: RXRST Position */
+#define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) /*!< UART_T::FIFO: RXRST Mask */
+
+#define UART_FIFO_TXRST_Pos (2) /*!< UART_T::FIFO: TXRST Position */
+#define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) /*!< UART_T::FIFO: TXRST Mask */
+
+#define UART_FIFO_RFITL_Pos (4) /*!< UART_T::FIFO: RFITL Position */
+#define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) /*!< UART_T::FIFO: RFITL Mask */
+
+#define UART_FIFO_RXOFF_Pos (8) /*!< UART_T::FIFO: RXOFF Position */
+#define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) /*!< UART_T::FIFO: RXOFF Mask */
+
+#define UART_FIFO_RTSTRGLV_Pos (16) /*!< UART_T::FIFO: RTSTRGLV Position */
+#define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) /*!< UART_T::FIFO: RTSTRGLV Mask */
+
+#define UART_LINE_WLS_Pos (0) /*!< UART_T::LINE: WLS Position */
+#define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) /*!< UART_T::LINE: WLS Mask */
+
+#define UART_LINE_NSB_Pos (2) /*!< UART_T::LINE: NSB Position */
+#define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) /*!< UART_T::LINE: NSB Mask */
+
+#define UART_LINE_PBE_Pos (3) /*!< UART_T::LINE: PBE Position */
+#define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) /*!< UART_T::LINE: PBE Mask */
+
+#define UART_LINE_EPE_Pos (4) /*!< UART_T::LINE: EPE Position */
+#define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) /*!< UART_T::LINE: EPE Mask */
+
+#define UART_LINE_SPE_Pos (5) /*!< UART_T::LINE: SPE Position */
+#define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) /*!< UART_T::LINE: SPE Mask */
+
+#define UART_LINE_BCB_Pos (6) /*!< UART_T::LINE: BCB Position */
+#define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) /*!< UART_T::LINE: BCB Mask */
+
+#define UART_LINE_PSS_Pos (7) /*!< UART_T::LINE: PSS Position */
+#define UART_LINE_PSS_Msk (0x1ul << UART_LINE_PSS_Pos) /*!< UART_T::LINE: PSS Mask */
+
+#define UART_LINE_TXDINV_Pos (8) /*!< UART_T::LINE: TXDINV Position */
+#define UART_LINE_TXDINV_Msk (0x1ul << UART_LINE_TXDINV_Pos) /*!< UART_T::LINE: TXDINV Mask */
+
+#define UART_LINE_RXDINV_Pos (9) /*!< UART_T::LINE: RXDINV Position */
+#define UART_LINE_RXDINV_Msk (0x1ul << UART_LINE_RXDINV_Pos) /*!< UART_T::LINE: RXDINV Mask */
+
+#define UART_MODEM_RTS_Pos (1) /*!< UART_T::MODEM: RTS Position */
+#define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) /*!< UART_T::MODEM: RTS Mask */
+
+#define UART_MODEM_RTSACTLV_Pos (9) /*!< UART_T::MODEM: RTSACTLV Position */
+#define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< UART_T::MODEM: RTSACTLV Mask */
+
+#define UART_MODEM_RTSSTS_Pos (13) /*!< UART_T::MODEM: RTSSTS Position */
+#define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) /*!< UART_T::MODEM: RTSSTS Mask */
+
+#define UART_MODEMSTS_CTSDETF_Pos (0) /*!< UART_T::MODEMSTS: CTSDETF Position */
+#define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) /*!< UART_T::MODEMSTS: CTSDETF Mask */
+
+#define UART_MODEMSTS_CTSSTS_Pos (4) /*!< UART_T::MODEMSTS: CTSSTS Position */
+#define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) /*!< UART_T::MODEMSTS: CTSSTS Mask */
+
+#define UART_MODEMSTS_CTSACTLV_Pos (8) /*!< UART_T::MODEMSTS: CTSACTLV Position */
+#define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) /*!< UART_T::MODEMSTS: CTSACTLV Mask */
+
+#define UART_FIFOSTS_RXOVIF_Pos (0) /*!< UART_T::FIFOSTS: RXOVIF Position */
+#define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) /*!< UART_T::FIFOSTS: RXOVIF Mask */
+
+#define UART_FIFOSTS_ABRDIF_Pos (1) /*!< UART_T::FIFOSTS: ABRDIF Position */
+#define UART_FIFOSTS_ABRDIF_Msk (0x1ul << UART_FIFOSTS_ABRDIF_Pos) /*!< UART_T::FIFOSTS: ABRDIF Mask */
+
+#define UART_FIFOSTS_ABRDTOIF_Pos (2) /*!< UART_T::FIFOSTS: ABRDTOIF Position */
+#define UART_FIFOSTS_ABRDTOIF_Msk (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos) /*!< UART_T::FIFOSTS: ABRDTOIF Mask */
+
+#define UART_FIFOSTS_ADDRDETF_Pos (3) /*!< UART_T::FIFOSTS: ADDRDETF Position */
+#define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) /*!< UART_T::FIFOSTS: ADDRDETF Mask */
+
+#define UART_FIFOSTS_PEF_Pos (4) /*!< UART_T::FIFOSTS: PEF Position */
+#define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) /*!< UART_T::FIFOSTS: PEF Mask */
+
+#define UART_FIFOSTS_FEF_Pos (5) /*!< UART_T::FIFOSTS: FEF Position */
+#define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) /*!< UART_T::FIFOSTS: FEF Mask */
+
+#define UART_FIFOSTS_BIF_Pos (6) /*!< UART_T::FIFOSTS: BIF Position */
+#define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) /*!< UART_T::FIFOSTS: BIF Mask */
+
+#define UART_FIFOSTS_RXPTR_Pos (8) /*!< UART_T::FIFOSTS: RXPTR Position */
+#define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) /*!< UART_T::FIFOSTS: RXPTR Mask */
+
+#define UART_FIFOSTS_RXEMPTY_Pos (14) /*!< UART_T::FIFOSTS: RXEMPTY Position */
+#define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) /*!< UART_T::FIFOSTS: RXEMPTY Mask */
+
+#define UART_FIFOSTS_RXFULL_Pos (15) /*!< UART_T::FIFOSTS: RXFULL Position */
+#define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) /*!< UART_T::FIFOSTS: RXFULL Mask */
+
+#define UART_FIFOSTS_TXPTR_Pos (16) /*!< UART_T::FIFOSTS: TXPTR Position */
+#define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) /*!< UART_T::FIFOSTS: TXPTR Mask */
+
+#define UART_FIFOSTS_TXEMPTY_Pos (22) /*!< UART_T::FIFOSTS: TXEMPTY Position */
+#define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) /*!< UART_T::FIFOSTS: TXEMPTY Mask */
+
+#define UART_FIFOSTS_TXFULL_Pos (23) /*!< UART_T::FIFOSTS: TXFULL Position */
+#define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) /*!< UART_T::FIFOSTS: TXFULL Mask */
+
+#define UART_FIFOSTS_TXOVIF_Pos (24) /*!< UART_T::FIFOSTS: TXOVIF Position */
+#define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) /*!< UART_T::FIFOSTS: TXOVIF Mask */
+
+#define UART_FIFOSTS_TXEMPTYF_Pos (28) /*!< UART_T::FIFOSTS: TXEMPTYF Position */
+#define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) /*!< UART_T::FIFOSTS: TXEMPTYF Mask */
+
+#define UART_FIFOSTS_RXIDLE_Pos (29) /*!< UART_T::FIFOSTS: RXIDLE Position */
+#define UART_FIFOSTS_RXIDLE_Msk (0x1ul << UART_FIFOSTS_RXIDLE_Pos) /*!< UART_T::FIFOSTS: RXIDLE Mask */
+
+#define UART_FIFOSTS_TXRXACT_Pos (31) /*!< UART_T::FIFOSTS: TXRXACT Position */
+#define UART_FIFOSTS_TXRXACT_Msk (0x1ul << UART_FIFOSTS_TXRXACT_Pos) /*!< UART_T::FIFOSTS: TXRXACT Mask */
+
+#define UART_INTSTS_RDAIF_Pos (0) /*!< UART_T::INTSTS: RDAIF Position */
+#define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) /*!< UART_T::INTSTS: RDAIF Mask */
+
+#define UART_INTSTS_THREIF_Pos (1) /*!< UART_T::INTSTS: THREIF Position */
+#define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) /*!< UART_T::INTSTS: THREIF Mask */
+
+#define UART_INTSTS_RLSIF_Pos (2) /*!< UART_T::INTSTS: RLSIF Position */
+#define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) /*!< UART_T::INTSTS: RLSIF Mask */
+
+#define UART_INTSTS_MODEMIF_Pos (3) /*!< UART_T::INTSTS: MODEMIF Position */
+#define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos) /*!< UART_T::INTSTS: MODEMIF Mask */
+
+#define UART_INTSTS_RXTOIF_Pos (4) /*!< UART_T::INTSTS: RXTOIF Position */
+#define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) /*!< UART_T::INTSTS: RXTOIF Mask */
+
+#define UART_INTSTS_BUFERRIF_Pos (5) /*!< UART_T::INTSTS: BUFERRIF Position */
+#define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) /*!< UART_T::INTSTS: BUFERRIF Mask */
+
+#define UART_INTSTS_WKIF_Pos (6) /*!< UART_T::INTSTS: WKIF Position */
+#define UART_INTSTS_WKIF_Msk (0x1ul << UART_INTSTS_WKIF_Pos) /*!< UART_T::INTSTS: WKIF Mask */
+
+#define UART_INTSTS_LINIF_Pos (7) /*!< UART_T::INTSTS: LINIF Position */
+#define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) /*!< UART_T::INTSTS: LINIF Mask */
+
+#define UART_INTSTS_RDAINT_Pos (8) /*!< UART_T::INTSTS: RDAINT Position */
+#define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) /*!< UART_T::INTSTS: RDAINT Mask */
+
+#define UART_INTSTS_THREINT_Pos (9) /*!< UART_T::INTSTS: THREINT Position */
+#define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) /*!< UART_T::INTSTS: THREINT Mask */
+
+#define UART_INTSTS_RLSINT_Pos (10) /*!< UART_T::INTSTS: RLSINT Position */
+#define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) /*!< UART_T::INTSTS: RLSINT Mask */
+
+#define UART_INTSTS_MODEMINT_Pos (11) /*!< UART_T::INTSTS: MODEMINT Position */
+#define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) /*!< UART_T::INTSTS: MODEMINT Mask */
+
+#define UART_INTSTS_RXTOINT_Pos (12) /*!< UART_T::INTSTS: RXTOINT Position */
+#define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) /*!< UART_T::INTSTS: RXTOINT Mask */
+
+#define UART_INTSTS_BUFERRINT_Pos (13) /*!< UART_T::INTSTS: BUFERRINT Position */
+#define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos) /*!< UART_T::INTSTS: BUFERRINT Mask */
+
+#define UART_INTSTS_WKINT_Pos (14) /*!< UART_T::INTSTS: WKINT Position */
+#define UART_INTSTS_WKINT_Msk (0x1ul << UART_INTSTS_WKINT_Pos) /*!< UART_T::INTSTS: WKINT Mask */
+
+#define UART_INTSTS_LININT_Pos (15) /*!< UART_T::INTSTS: LININT Position */
+#define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos) /*!< UART_T::INTSTS: LININT Mask */
+
+#define UART_INTSTS_HWRLSIF_Pos (18) /*!< UART_T::INTSTS: HWRLSIF Position */
+#define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos) /*!< UART_T::INTSTS: HWRLSIF Mask */
+
+#define UART_INTSTS_HWMODIF_Pos (19) /*!< UART_T::INTSTS: HWMODIF Position */
+#define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos) /*!< UART_T::INTSTS: HWMODIF Mask */
+
+#define UART_INTSTS_HWTOIF_Pos (20) /*!< UART_T::INTSTS: HWTOIF Position */
+#define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos) /*!< UART_T::INTSTS: HWTOIF Mask */
+
+#define UART_INTSTS_HWBUFEIF_Pos (21) /*!< UART_T::INTSTS: HWBUFEIF Position */
+#define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos) /*!< UART_T::INTSTS: HWBUFEIF Mask */
+
+#define UART_INTSTS_TXENDIF_Pos (22) /*!< UART_T::INTSTS: TXENDIF Position */
+#define UART_INTSTS_TXENDIF_Msk (0x1ul << UART_INTSTS_TXENDIF_Pos) /*!< UART_T::INTSTS: TXENDIF Mask */
+
+#define UART_INTSTS_HWRLSINT_Pos (26) /*!< UART_T::INTSTS: HWRLSINT Position */
+#define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos) /*!< UART_T::INTSTS: HWRLSINT Mask */
+
+#define UART_INTSTS_HWMODINT_Pos (27) /*!< UART_T::INTSTS: HWMODINT Position */
+#define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos) /*!< UART_T::INTSTS: HWMODINT Mask */
+
+#define UART_INTSTS_HWTOINT_Pos (28) /*!< UART_T::INTSTS: HWTOINT Position */
+#define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos) /*!< UART_T::INTSTS: HWTOINT Mask */
+
+#define UART_INTSTS_HWBUFEINT_Pos (29) /*!< UART_T::INTSTS: HWBUFEINT Position */
+#define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos) /*!< UART_T::INTSTS: HWBUFEINT Mask */
+
+#define UART_INTSTS_TXENDINT_Pos (30) /*!< UART_T::INTSTS: TXENDINT Position */
+#define UART_INTSTS_TXENDINT_Msk (0x1ul << UART_INTSTS_TXENDINT_Pos) /*!< UART_T::INTSTS: TXENDINT Mask */
+
+#define UART_INTSTS_ABRINT_Pos (31) /*!< UART_T::INTSTS: ABRINT Position */
+#define UART_INTSTS_ABRINT_Msk (0x1ul << UART_INTSTS_ABRINT_Pos) /*!< UART_T::INTSTS: ABRINT Mask */
+
+#define UART_TOUT_TOIC_Pos (0) /*!< UART_T::TOUT: TOIC Position */
+#define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) /*!< UART_T::TOUT: TOIC Mask */
+
+#define UART_TOUT_DLY_Pos (8) /*!< UART_T::TOUT: DLY Position */
+#define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) /*!< UART_T::TOUT: DLY Mask */
+
+#define UART_BAUD_BRD_Pos (0) /*!< UART_T::BAUD: BRD Position */
+#define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) /*!< UART_T::BAUD: BRD Mask */
+
+#define UART_BAUD_EDIVM1_Pos (24) /*!< UART_T::BAUD: EDIVM1 Position */
+#define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) /*!< UART_T::BAUD: EDIVM1 Mask */
+
+#define UART_BAUD_BAUDM0_Pos (28) /*!< UART_T::BAUD: BAUDM0 Position */
+#define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) /*!< UART_T::BAUD: BAUDM0 Mask */
+
+#define UART_BAUD_BAUDM1_Pos (29) /*!< UART_T::BAUD: BAUDM1 Position */
+#define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) /*!< UART_T::BAUD: BAUDM1 Mask */
+
+#define UART_IRDA_TXEN_Pos (1) /*!< UART_T::IRDA: TXEN Position */
+#define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) /*!< UART_T::IRDA: TXEN Mask */
+
+#define UART_IRDA_TXINV_Pos (5) /*!< UART_T::IRDA: TXINV Position */
+#define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) /*!< UART_T::IRDA: TXINV Mask */
+
+#define UART_IRDA_RXINV_Pos (6) /*!< UART_T::IRDA: RXINV Position */
+#define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) /*!< UART_T::IRDA: RXINV Mask */
+
+#define UART_ALTCTL_BRKFL_Pos (0) /*!< UART_T::ALTCTL: BRKFL Position */
+#define UART_ALTCTL_BRKFL_Msk (0xful << UART_ALTCTL_BRKFL_Pos) /*!< UART_T::ALTCTL: BRKFL Mask */
+
+#define UART_ALTCTL_LINRXEN_Pos (6) /*!< UART_T::ALTCTL: LINRXEN Position */
+#define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) /*!< UART_T::ALTCTL: LINRXEN Mask */
+
+#define UART_ALTCTL_LINTXEN_Pos (7) /*!< UART_T::ALTCTL: LINTXEN Position */
+#define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) /*!< UART_T::ALTCTL: LINTXEN Mask */
+
+#define UART_ALTCTL_RS485NMM_Pos (8) /*!< UART_T::ALTCTL: RS485NMM Position */
+#define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) /*!< UART_T::ALTCTL: RS485NMM Mask */
+
+#define UART_ALTCTL_RS485AAD_Pos (9) /*!< UART_T::ALTCTL: RS485AAD Position */
+#define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) /*!< UART_T::ALTCTL: RS485AAD Mask */
+
+#define UART_ALTCTL_RS485AUD_Pos (10) /*!< UART_T::ALTCTL: RS485AUD Position */
+#define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) /*!< UART_T::ALTCTL: RS485AUD Mask */
+
+#define UART_ALTCTL_ADDRDEN_Pos (15) /*!< UART_T::ALTCTL: ADDRDEN Position */
+#define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) /*!< UART_T::ALTCTL: ADDRDEN Mask */
+
+#define UART_ALTCTL_ABRIF_Pos (17) /*!< UART_T::ALTCTL: ABRIF Position */
+#define UART_ALTCTL_ABRIF_Msk (0x1ul << UART_ALTCTL_ABRIF_Pos) /*!< UART_T::ALTCTL: ABRIF Mask */
+
+#define UART_ALTCTL_ABRDEN_Pos (18) /*!< UART_T::ALTCTL: ABRDEN Position */
+#define UART_ALTCTL_ABRDEN_Msk (0x1ul << UART_ALTCTL_ABRDEN_Pos) /*!< UART_T::ALTCTL: ABRDEN Mask */
+
+#define UART_ALTCTL_ABRDBITS_Pos (19) /*!< UART_T::ALTCTL: ABRDBITS Position */
+#define UART_ALTCTL_ABRDBITS_Msk (0x3ul << UART_ALTCTL_ABRDBITS_Pos) /*!< UART_T::ALTCTL: ABRDBITS Mask */
+
+#define UART_ALTCTL_ADDRMV_Pos (24) /*!< UART_T::ALTCTL: ADDRMV Position */
+#define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) /*!< UART_T::ALTCTL: ADDRMV Mask */
+
+#define UART_FUNCSEL_FUNCSEL_Pos (0) /*!< UART_T::FUNCSEL: FUNCSEL Position */
+#define UART_FUNCSEL_FUNCSEL_Msk (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_T::FUNCSEL: FUNCSEL Mask */
+
+#define UART_FUNCSEL_TXRXDIS_Pos (3) /*!< UART_T::FUNCSEL: TXRXDIS Position */
+#define UART_FUNCSEL_TXRXDIS_Msk (0x1ul << UART_FUNCSEL_TXRXDIS_Pos) /*!< UART_T::FUNCSEL: TXRXDIS Mask */
+
+#define UART_LINCTL_SLVEN_Pos (0) /*!< UART_T::LINCTL: SLVEN Position */
+#define UART_LINCTL_SLVEN_Msk (0x1ul << UART_LINCTL_SLVEN_Pos) /*!< UART_T::LINCTL: SLVEN Mask */
+
+#define UART_LINCTL_SLVHDEN_Pos (1) /*!< UART_T::LINCTL: SLVHDEN Position */
+#define UART_LINCTL_SLVHDEN_Msk (0x1ul << UART_LINCTL_SLVHDEN_Pos) /*!< UART_T::LINCTL: SLVHDEN Mask */
+
+#define UART_LINCTL_SLVAREN_Pos (2) /*!< UART_T::LINCTL: SLVAREN Position */
+#define UART_LINCTL_SLVAREN_Msk (0x1ul << UART_LINCTL_SLVAREN_Pos) /*!< UART_T::LINCTL: SLVAREN Mask */
+
+#define UART_LINCTL_SLVDUEN_Pos (3) /*!< UART_T::LINCTL: SLVDUEN Position */
+#define UART_LINCTL_SLVDUEN_Msk (0x1ul << UART_LINCTL_SLVDUEN_Pos) /*!< UART_T::LINCTL: SLVDUEN Mask */
+
+#define UART_LINCTL_MUTE_Pos (4) /*!< UART_T::LINCTL: MUTE Position */
+#define UART_LINCTL_MUTE_Msk (0x1ul << UART_LINCTL_MUTE_Pos) /*!< UART_T::LINCTL: MUTE Mask */
+
+#define UART_LINCTL_SENDH_Pos (8) /*!< UART_T::LINCTL: SENDH Position */
+#define UART_LINCTL_SENDH_Msk (0x1ul << UART_LINCTL_SENDH_Pos) /*!< UART_T::LINCTL: SENDH Mask */
+
+#define UART_LINCTL_IDPEN_Pos (9) /*!< UART_T::LINCTL: IDPEN Position */
+#define UART_LINCTL_IDPEN_Msk (0x1ul << UART_LINCTL_IDPEN_Pos) /*!< UART_T::LINCTL: IDPEN Mask */
+
+#define UART_LINCTL_BRKDETEN_Pos (10) /*!< UART_T::LINCTL: BRKDETEN Position */
+#define UART_LINCTL_BRKDETEN_Msk (0x1ul << UART_LINCTL_BRKDETEN_Pos) /*!< UART_T::LINCTL: BRKDETEN Mask */
+
+#define UART_LINCTL_LINRXOFF_Pos (11) /*!< UART_T::LINCTL: LINRXOFF Position */
+#define UART_LINCTL_LINRXOFF_Msk (0x1ul << UART_LINCTL_LINRXOFF_Pos) /*!< UART_T::LINCTL: LINRXOFF Mask */
+
+#define UART_LINCTL_BITERREN_Pos (12) /*!< UART_T::LINCTL: BITERREN Position */
+#define UART_LINCTL_BITERREN_Msk (0x1ul << UART_LINCTL_BITERREN_Pos) /*!< UART_T::LINCTL: BITERREN Mask */
+
+#define UART_LINCTL_BRKFL_Pos (16) /*!< UART_T::LINCTL: BRKFL Position */
+#define UART_LINCTL_BRKFL_Msk (0xful << UART_LINCTL_BRKFL_Pos) /*!< UART_T::LINCTL: BRKFL Mask */
+
+#define UART_LINCTL_BSL_Pos (20) /*!< UART_T::LINCTL: BSL Position */
+#define UART_LINCTL_BSL_Msk (0x3ul << UART_LINCTL_BSL_Pos) /*!< UART_T::LINCTL: BSL Mask */
+
+#define UART_LINCTL_HSEL_Pos (22) /*!< UART_T::LINCTL: HSEL Position */
+#define UART_LINCTL_HSEL_Msk (0x3ul << UART_LINCTL_HSEL_Pos) /*!< UART_T::LINCTL: HSEL Mask */
+
+#define UART_LINCTL_PID_Pos (24) /*!< UART_T::LINCTL: PID Position */
+#define UART_LINCTL_PID_Msk (0xfful << UART_LINCTL_PID_Pos) /*!< UART_T::LINCTL: PID Mask */
+
+#define UART_LINSTS_SLVHDETF_Pos (0) /*!< UART_T::LINSTS: SLVHDETF Position */
+#define UART_LINSTS_SLVHDETF_Msk (0x1ul << UART_LINSTS_SLVHDETF_Pos) /*!< UART_T::LINSTS: SLVHDETF Mask */
+
+#define UART_LINSTS_SLVHEF_Pos (1) /*!< UART_T::LINSTS: SLVHEF Position */
+#define UART_LINSTS_SLVHEF_Msk (0x1ul << UART_LINSTS_SLVHEF_Pos) /*!< UART_T::LINSTS: SLVHEF Mask */
+
+#define UART_LINSTS_SLVIDPEF_Pos (2) /*!< UART_T::LINSTS: SLVIDPEF Position */
+#define UART_LINSTS_SLVIDPEF_Msk (0x1ul << UART_LINSTS_SLVIDPEF_Pos) /*!< UART_T::LINSTS: SLVIDPEF Mask */
+
+#define UART_LINSTS_SLVSYNCF_Pos (3) /*!< UART_T::LINSTS: SLVSYNCF Position */
+#define UART_LINSTS_SLVSYNCF_Msk (0x1ul << UART_LINSTS_SLVSYNCF_Pos) /*!< UART_T::LINSTS: SLVSYNCF Mask */
+
+#define UART_LINSTS_BRKDETF_Pos (8) /*!< UART_T::LINSTS: BRKDETF Position */
+#define UART_LINSTS_BRKDETF_Msk (0x1ul << UART_LINSTS_BRKDETF_Pos) /*!< UART_T::LINSTS: BRKDETF Mask */
+
+#define UART_LINSTS_BITEF_Pos (9) /*!< UART_T::LINSTS: BITEF Position */
+#define UART_LINSTS_BITEF_Msk (0x1ul << UART_LINSTS_BITEF_Pos) /*!< UART_T::LINSTS: BITEF Mask */
+
+#define UART_BRCOMP_BRCOMP_Pos (0) /*!< UART_T::BRCOMP: BRCOMP Position */
+#define UART_BRCOMP_BRCOMP_Msk (0x1fful << UART_BRCOMP_BRCOMP_Pos) /*!< UART_T::BRCOMP: BRCOMP Mask */
+
+#define UART_BRCOMP_BRCOMPDEC_Pos (31) /*!< UART_T::BRCOMP: BRCOMPDEC Position */
+#define UART_BRCOMP_BRCOMPDEC_Msk (0x1ul << UART_BRCOMP_BRCOMPDEC_Pos) /*!< UART_T::BRCOMP: BRCOMPDEC Mask */
+
+#define UART_WKCTL_WKCTSEN_Pos (0) /*!< UART_T::WKCTL: WKCTSEN Position */
+#define UART_WKCTL_WKCTSEN_Msk (0x1ul << UART_WKCTL_WKCTSEN_Pos) /*!< UART_T::WKCTL: WKCTSEN Mask */
+
+#define UART_WKCTL_WKDATEN_Pos (1) /*!< UART_T::WKCTL: WKDATEN Position */
+#define UART_WKCTL_WKDATEN_Msk (0x1ul << UART_WKCTL_WKDATEN_Pos) /*!< UART_T::WKCTL: WKDATEN Mask */
+
+#define UART_WKCTL_WKRFRTEN_Pos (2) /*!< UART_T::WKCTL: WKRFRTEN Position */
+#define UART_WKCTL_WKRFRTEN_Msk (0x1ul << UART_WKCTL_WKRFRTEN_Pos) /*!< UART_T::WKCTL: WKRFRTEN Mask */
+
+#define UART_WKCTL_WKRS485EN_Pos (3) /*!< UART_T::WKCTL: WKRS485EN Position */
+#define UART_WKCTL_WKRS485EN_Msk (0x1ul << UART_WKCTL_WKRS485EN_Pos) /*!< UART_T::WKCTL: WKRS485EN Mask */
+
+#define UART_WKCTL_WKTOUTEN_Pos (4) /*!< UART_T::WKCTL: WKTOUTEN Position */
+#define UART_WKCTL_WKTOUTEN_Msk (0x1ul << UART_WKCTL_WKTOUTEN_Pos) /*!< UART_T::WKCTL: WKTOUTEN Mask */
+
+#define UART_WKSTS_CTSWKF_Pos (0) /*!< UART_T::WKSTS: CTSWKF Position */
+#define UART_WKSTS_CTSWKF_Msk (0x1ul << UART_WKSTS_CTSWKF_Pos) /*!< UART_T::WKSTS: CTSWKF Mask */
+
+#define UART_WKSTS_DATWKF_Pos (1) /*!< UART_T::WKSTS: DATWKF Position */
+#define UART_WKSTS_DATWKF_Msk (0x1ul << UART_WKSTS_DATWKF_Pos) /*!< UART_T::WKSTS: DATWKF Mask */
+
+#define UART_WKSTS_RFRTWKF_Pos (2) /*!< UART_T::WKSTS: RFRTWKF Position */
+#define UART_WKSTS_RFRTWKF_Msk (0x1ul << UART_WKSTS_RFRTWKF_Pos) /*!< UART_T::WKSTS: RFRTWKF Mask */
+
+#define UART_WKSTS_RS485WKF_Pos (3) /*!< UART_T::WKSTS: RS485WKF Position */
+#define UART_WKSTS_RS485WKF_Msk (0x1ul << UART_WKSTS_RS485WKF_Pos) /*!< UART_T::WKSTS: RS485WKF Mask */
+
+#define UART_WKSTS_TOUTWKF_Pos (4) /*!< UART_T::WKSTS: TOUTWKF Position */
+#define UART_WKSTS_TOUTWKF_Msk (0x1ul << UART_WKSTS_TOUTWKF_Pos) /*!< UART_T::WKSTS: TOUTWKF Mask */
+
+#define UART_DWKCOMP_STCOMP_Pos (0) /*!< UART_T::DWKCOMP: STCOMP Position */
+#define UART_DWKCOMP_STCOMP_Msk (0xfffful << UART_DWKCOMP_STCOMP_Pos) /*!< UART_T::DWKCOMP: STCOMP Mask */
+
+/**@}*/ /* UART_CONST */
+/**@}*/ /* end of UART register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+#endif /* __UART_REG_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Include/system_M480.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Include/system_M480.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,88 @@
+/**************************************************************************//**
+ * @file system_M480.h
+ * @version V1.00
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for M480
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************/
+
+#ifndef __SYSTEM_M480_H__
+#define __SYSTEM_M480_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+
+#define __HSI (12000000UL) /*!< PLL default output is 50MHz */
+#define __HXT (12000000UL) /*!< External Crystal Clock Frequency */
+#define __LXT (32768UL) /*!< External Crystal Clock Frequency 32.768KHz */
+#define __HIRC (12000000UL) /*!< Internal 12M RC Oscillator Frequency */
+#define __LIRC (10000UL) /*!< Internal 10K RC Oscillator Frequency */
+#define __SYS_OSC_CLK ( ___HSI) /* Main oscillator frequency */
+
+
+#define __SYSTEM_CLOCK (1UL*__HXT)
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+extern uint32_t CyclesPerUs; /*!< Cycles per micro second */
+extern uint32_t PllClock; /*!< PLL Output Clock Frequency */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the micro controller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit(void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_M480_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Source/ARM/startup_M480.s --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Source/ARM/startup_M480.s Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,501 @@ +;/****************************************************************************** +; * @file startup_M480.s +; * @version V1.00 +; * @brief CMSIS Cortex-M4 Core Device Startup File for M480 +; * +; * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +; * +; * Redistribution and use in source and binary forms, with or without modification, +; * are permitted provided that the following conditions are met: +; * 1. Redistributions of source code must retain the above copyright notice, +; * this list of conditions and the following disclaimer. +; * 2. Redistributions in binary form must reproduce the above copyright notice, +; * this list of conditions and the following disclaimer in the documentation +; * and/or other materials provided with the distribution. +; * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors +; * may be used to endorse or promote products derived from this software +; * without specific prior written permission. +; * +; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;*****************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + + IF :LNOT: :DEF: Stack_Size +Stack_Size EQU 0x00006000 + ENDIF + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + + IF :LNOT: :DEF: Heap_Size +Heap_Size EQU 0x00000100 + ENDIF + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD DAPLINK_BUILD_KEY ; Build type - BL/IF + DCD DAPLINK_HIC_ID ; Compatibility + DCD DAPLINK_VERSION ; Version + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD BOD_IRQHandler ; 0: Brown Out detection + DCD IRC_IRQHandler ; 1: Internal RC + DCD PWRWU_IRQHandler ; 2: Power down wake up + DCD RAMPE_IRQHandler ; 3: RAM parity error + DCD CKFAIL_IRQHandler ; 4: Clock detection fail + DCD Default_Handler ; 5: Reserved + DCD RTC_IRQHandler ; 6: Real Time Clock + DCD TAMPER_IRQHandler ; 7: Tamper detection + DCD WDT_IRQHandler ; 8: Watchdog timer + DCD WWDT_IRQHandler ; 9: Window watchdog timer + DCD EINT0_IRQHandler ; 10: External Input 0 + DCD EINT1_IRQHandler ; 11: External Input 1 + DCD EINT2_IRQHandler ; 12: External Input 2 + DCD EINT3_IRQHandler ; 13: External Input 3 + DCD EINT4_IRQHandler ; 14: External Input 4 + DCD EINT5_IRQHandler ; 15: External Input 5 + DCD GPA_IRQHandler ; 16: GPIO Port A + DCD GPB_IRQHandler ; 17: GPIO Port B + DCD GPC_IRQHandler ; 18: GPIO Port C + DCD GPD_IRQHandler ; 19: GPIO Port D + DCD GPE_IRQHandler ; 20: GPIO Port E + DCD GPF_IRQHandler ; 21: GPIO Port F + DCD QSPI0_IRQHandler ; 22: QSPI0 + DCD SPI0_IRQHandler ; 23: SPI0 + DCD BRAKE0_IRQHandler ; 24: + DCD EPWM0P0_IRQHandler ; 25: + DCD EPWM0P1_IRQHandler ; 26: + DCD EPWM0P2_IRQHandler ; 27: + DCD BRAKE1_IRQHandler ; 28: + DCD EPWM1P0_IRQHandler ; 29: + DCD EPWM1P1_IRQHandler ; 30: + DCD EPWM1P2_IRQHandler ; 31: + DCD TMR0_IRQHandler ; 32: Timer 0 + DCD TMR1_IRQHandler ; 33: Timer 1 + DCD TMR2_IRQHandler ; 34: Timer 2 + DCD TMR3_IRQHandler ; 35: Timer 3 + DCD UART0_IRQHandler ; 36: UART0 + DCD UART1_IRQHandler ; 37: UART1 + DCD I2C0_IRQHandler ; 38: I2C0 + DCD I2C1_IRQHandler ; 39: I2C1 + DCD PDMA_IRQHandler ; 40: Peripheral DMA + DCD DAC_IRQHandler ; 41: DAC + DCD ADC00_IRQHandler ; 42: ADC0 interrupt source 0 + DCD ADC01_IRQHandler ; 43: ADC0 interrupt source 1 + DCD ACMP01_IRQHandler ; 44: ACMP0 and ACMP1 + DCD Default_Handler ; 45: Reserved + DCD ADC02_IRQHandler ; 46: ADC0 interrupt source 2 + DCD ADC03_IRQHandler ; 47: ADC0 interrupt source 3 + DCD UART2_IRQHandler ; 48: UART2 + DCD UART3_IRQHandler ; 49: UART3 + DCD Default_Handler ; 50: Reserved + DCD SPI1_IRQHandler ; 51: SPI1 + DCD SPI2_IRQHandler ; 52: SPI2 + DCD USBD_IRQHandler ; 53: USB device + DCD OHCI_IRQHandler ; 54: OHCI + DCD USBOTG_IRQHandler ; 55: USB OTG + DCD CAN0_IRQHandler ; 56: CAN0 + DCD CAN1_IRQHandler ; 57: CAN1 + DCD SC0_IRQHandler ; 58: + DCD SC1_IRQHandler ; 59: + DCD SC2_IRQHandler ; 60: + DCD Default_Handler ; 61: + DCD SPI3_IRQHandler ; 62: SPI3 + DCD Default_Handler ; 63: + DCD SDH0_IRQHandler ; 64: SDH0 + DCD USBD20_IRQHandler ; 65: USBD20 + DCD EMAC_TX_IRQHandler ; 66: EMAC_TX + DCD EMAC_RX_IRQHandler ; 67: EMAX_RX + DCD I2S0_IRQHandler ; 68: I2S0 + DCD Default_Handler ; 69: ToDo: Add description to this Interrupt + DCD OPA0_IRQHandler ; 70: OPA0 + DCD CRYPTO_IRQHandler ; 71: CRYPTO + DCD GPG_IRQHandler ; 72: + DCD EINT6_IRQHandler ; 73: + DCD UART4_IRQHandler ; 74: UART4 + DCD UART5_IRQHandler ; 75: UART5 + DCD USCI0_IRQHandler ; 76: USCI0 + DCD USCI1_IRQHandler ; 77: USCI1 + DCD BPWM0_IRQHandler ; 78: BPWM0 + DCD BPWM1_IRQHandler ; 79: BPWM1 + DCD SPIM_IRQHandler ; 80: SPIM + DCD Default_Handler ; 81: ToDo: Add description to this Interrupt + DCD I2C2_IRQHandler ; 82: I2C2 + DCD Default_Handler ; 83: + DCD QEI0_IRQHandler ; 84: QEI0 + DCD QEI1_IRQHandler ; 85: QEI1 + DCD ECAP0_IRQHandler ; 86: ECAP0 + DCD ECAP1_IRQHandler ; 87: ECAP1 + DCD GPH_IRQHandler ; 88: + DCD EINT7_IRQHandler ; 89: + DCD SDH1_IRQHandler ; 90: SDH1 + DCD Default_Handler ; 91: + DCD EHCI_IRQHandler ; 92: EHCI + DCD USBOTG20_IRQHandler ; 93: + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + ; Unlock Register + LDR R0, =0x40000100 + LDR R1, =0x59 + STR R1, [R0] + LDR R1, =0x16 + STR R1, [R0] + LDR R1, =0x88 + STR R1, [R0] + + IF :LNOT: :DEF: ENABLE_SPIM_CACHE + LDR R0, =0x40000200 ; R0 = Clock Controller Register Base Address + LDR R1, [R0,#0x4] ; R1 = 0x40000204 (AHBCLK) + ORR R1, R1, #0x4000 + STR R1, [R0,#0x4] ; CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk; + + LDR R0, =0x40007000 ; R0 = SPIM Register Base Address + LDR R1, [R0,#4] ; R1 = SPIM->CTL1 + ORR R1, R1,#2 ; R1 |= SPIM_CTL1_CACHEOFF_Msk + STR R1, [R0,#4] ; _SPIM_DISABLE_CACHE() + LDR R1, [R0,#4] ; R1 = SPIM->CTL1 + ORR R1, R1, #4 ; R1 |= SPIM_CTL1_CCMEN_Msk + STR R1, [R0,#4] ; _SPIM_ENABLE_CCM() + ENDIF + + LDR R0, =SystemInit + BLX R0 + + ; Init POR + ; LDR R2, =0x40000024 + ; LDR R1, =0x00005AA5 + ; STR R1, [R2] + + ; Lock + LDR R0, =0x40000100 + LDR R1, =0 + STR R1, [R0] + + LDR R0, =__main + BX R0 + + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT BOD_IRQHandler [WEAK] + EXPORT IRC_IRQHandler [WEAK] + EXPORT PWRWU_IRQHandler [WEAK] + EXPORT RAMPE_IRQHandler [WEAK] + EXPORT CKFAIL_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT WWDT_IRQHandler [WEAK] + EXPORT EINT0_IRQHandler [WEAK] + EXPORT EINT1_IRQHandler [WEAK] + EXPORT EINT2_IRQHandler [WEAK] + EXPORT EINT3_IRQHandler [WEAK] + EXPORT EINT4_IRQHandler [WEAK] + EXPORT EINT5_IRQHandler [WEAK] + EXPORT GPA_IRQHandler [WEAK] + EXPORT GPB_IRQHandler [WEAK] + EXPORT GPC_IRQHandler [WEAK] + EXPORT GPD_IRQHandler [WEAK] + EXPORT GPE_IRQHandler [WEAK] + EXPORT GPF_IRQHandler [WEAK] + EXPORT QSPI0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT BRAKE0_IRQHandler [WEAK] + EXPORT EPWM0P0_IRQHandler [WEAK] + EXPORT EPWM0P1_IRQHandler [WEAK] + EXPORT EPWM0P2_IRQHandler [WEAK] + EXPORT BRAKE1_IRQHandler [WEAK] + EXPORT EPWM1P0_IRQHandler [WEAK] + EXPORT EPWM1P1_IRQHandler [WEAK] + EXPORT EPWM1P2_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT PDMA_IRQHandler [WEAK] + EXPORT DAC_IRQHandler [WEAK] + EXPORT ADC00_IRQHandler [WEAK] + EXPORT ADC01_IRQHandler [WEAK] + EXPORT ACMP01_IRQHandler [WEAK] + EXPORT ADC02_IRQHandler [WEAK] + EXPORT ADC03_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USBD_IRQHandler [WEAK] + EXPORT OHCI_IRQHandler [WEAK] + EXPORT USBOTG_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT CAN1_IRQHandler [WEAK] + EXPORT SC0_IRQHandler [WEAK] + EXPORT SC1_IRQHandler [WEAK] + EXPORT SC2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT SDH0_IRQHandler [WEAK] + EXPORT USBD20_IRQHandler [WEAK] + EXPORT EMAC_TX_IRQHandler [WEAK] + EXPORT EMAC_RX_IRQHandler [WEAK] + EXPORT I2S0_IRQHandler [WEAK] + EXPORT OPA0_IRQHandler [WEAK] + EXPORT CRYPTO_IRQHandler [WEAK] + EXPORT GPG_IRQHandler [WEAK] + EXPORT EINT6_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT USCI0_IRQHandler [WEAK] + EXPORT USCI1_IRQHandler [WEAK] + EXPORT BPWM0_IRQHandler [WEAK] + EXPORT BPWM1_IRQHandler [WEAK] + EXPORT SPIM_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT QEI0_IRQHandler [WEAK] + EXPORT QEI1_IRQHandler [WEAK] + EXPORT ECAP0_IRQHandler [WEAK] + EXPORT ECAP1_IRQHandler [WEAK] + EXPORT GPH_IRQHandler [WEAK] + EXPORT EINT7_IRQHandler [WEAK] + EXPORT SDH1_IRQHandler [WEAK] + EXPORT EHCI_IRQHandler [WEAK] + EXPORT USBOTG20_IRQHandler [WEAK] + +Default__IRQHandler +BOD_IRQHandler +IRC_IRQHandler +PWRWU_IRQHandler +RAMPE_IRQHandler +CKFAIL_IRQHandler +RTC_IRQHandler +TAMPER_IRQHandler +WDT_IRQHandler +WWDT_IRQHandler +EINT0_IRQHandler +EINT1_IRQHandler +EINT2_IRQHandler +EINT3_IRQHandler +EINT4_IRQHandler +EINT5_IRQHandler +GPA_IRQHandler +GPB_IRQHandler +GPC_IRQHandler +GPD_IRQHandler +GPE_IRQHandler +GPF_IRQHandler +QSPI0_IRQHandler +SPI0_IRQHandler +BRAKE0_IRQHandler +EPWM0P0_IRQHandler +EPWM0P1_IRQHandler +EPWM0P2_IRQHandler +BRAKE1_IRQHandler +EPWM1P0_IRQHandler +EPWM1P1_IRQHandler +EPWM1P2_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +PDMA_IRQHandler +DAC_IRQHandler +ADC00_IRQHandler +ADC01_IRQHandler +ACMP01_IRQHandler +ADC02_IRQHandler +ADC03_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USBD_IRQHandler +OHCI_IRQHandler +USBOTG_IRQHandler +CAN0_IRQHandler +CAN1_IRQHandler +SC0_IRQHandler +SC1_IRQHandler +SC2_IRQHandler +SPI3_IRQHandler +SDH0_IRQHandler +USBD20_IRQHandler +EMAC_TX_IRQHandler +EMAC_RX_IRQHandler +I2S0_IRQHandler +OPA0_IRQHandler +CRYPTO_IRQHandler +GPG_IRQHandler +EINT6_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +USCI0_IRQHandler +USCI1_IRQHandler +BPWM0_IRQHandler +BPWM1_IRQHandler +SPIM_IRQHandler +I2C2_IRQHandler +QEI0_IRQHandler +QEI1_IRQHandler +ECAP0_IRQHandler +ECAP1_IRQHandler +GPH_IRQHandler +EINT7_IRQHandler +SDH1_IRQHandler +EHCI_IRQHandler +USBOTG20_IRQHandler + + + + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END +;/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Source/system_M480.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Source/system_M480.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,117 @@
+/**************************************************************************//**
+ * @file system_M480.c
+ * @version V1.000
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for M480
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************/
+
+#include "NuMicro.h"
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
+uint32_t CyclesPerUs = (__HSI / 1000000UL); /* Cycles per micro second */
+uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */
+uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0UL, __LIRC, 0UL, 0UL, 0UL, __HIRC};
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
+{
+ uint32_t u32Freq, u32ClkSrc;
+ uint32_t u32HclkDiv;
+ /* Update PLL Clock */
+ PllClock = CLK_GetPLLClockFreq();
+ u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
+
+ if (u32ClkSrc == CLK_CLKSEL0_HCLKSEL_PLL) {
+ /* Use PLL clock */
+ u32Freq = PllClock;
+ } else {
+ /* Use the clock sources directly */
+ u32Freq = gau32ClkSrcTbl[u32ClkSrc];
+ }
+
+ u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1UL;
+ /* Update System Core Clock */
+ SystemCoreClock = u32Freq / u32HclkDiv;
+ //if(SystemCoreClock == 0)
+ // __BKPT(0);
+ CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL;
+}
+
+/**
+ * @brief Set PF.2 and PF.3 to input mode
+ * @param None
+ * @return None
+ * @details GPIO default state could be configured as input or quasi through user config.
+ * To use HXT, PF.2 and PF.3 must not set as quasi mode. This function changes
+ * PF.2 and PF.3 to input mode no matter which mode they are working at.
+ */
+static __INLINE void HXTInit(void)
+{
+ PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk);
+}
+
+/**
+ * @brief Initialize the System
+ *
+ * @param none
+ * @return none
+ */
+void SystemInit(void)
+{
+ /* Add your system initialize code here.
+ Do not use global variables because this function is called before
+ reaching pre-main. RW section maybe overwritten afterwards. */
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ SCB->CPACR |= ((3UL << 10 * 2) | /* set CP10 Full Access */
+ (3UL << 11 * 2)); /* set CP11 Full Access */
+#endif
+ /* Set access cycle for CPU @ 192MHz */
+ FMC->CYCCTL = (FMC->CYCCTL & ~FMC_CYCCTL_CYCLE_Msk) | (8 << FMC_CYCCTL_CYCLE_Pos);
+ /* Configure power down bias, must set 1 before entering power down mode.
+ So set it at the very beginning */
+ CLK->LDOCTL |= CLK_LDOCTL_PDBIASEN_Msk;
+ /* Hand over the control of PF.4~11 I/O function from RTC module to GPIO module */
+ CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk;
+ RTC->GPIOCTL0 &= ~(RTC_GPIOCTL0_CTLSEL0_Msk | RTC_GPIOCTL0_CTLSEL1_Msk |
+ RTC_GPIOCTL0_CTLSEL2_Msk | RTC_GPIOCTL0_CTLSEL3_Msk);
+ RTC->GPIOCTL1 &= ~(RTC_GPIOCTL1_CTLSEL4_Msk | RTC_GPIOCTL1_CTLSEL5_Msk |
+ RTC_GPIOCTL1_CTLSEL6_Msk | RTC_GPIOCTL1_CTLSEL7_Msk);
+ CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk;
+ HXTInit();
+}
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/IO_Config.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/nuvoton/m48ssidae/IO_Config.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,66 @@ +/** + * @file IO_Config.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ + +#include "NuMicro.h" +#include "compiler.h" +#include "daplink.h" + +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_M48SSIDAE); + +// SWD +#define SWD_DAT_IO PA9 +#define SWD_DAT_GRP PA +#define SWD_DAT_BIT 9 + +#define SWD_CLK_IO PA10 +#define SWD_CLK_GRP PA +#define SWD_CLK_BIT 10 + +#define DBG_RST_IO PF5 +#define DBG_RST_GRP PF +#define DBG_RST_BIT 5 + +// LED +#define LED_ICE_IO PF4 +#define LED_ICE_GRP PF +#define LED_ICE_BIT 4 + +#define LED_ISP_IO PC6 +#define LED_ISP_GRP PC +#define LED_ISP_BIT 6 + +#define LED_RED_IO PB9 +#define LED_RED_GRP PB +#define LED_RED_BIT 9 + +#define LED_GRE_IO PB8 +#define LED_GRE_GRP PB +#define LED_GRE_BIT 8 + +// Other +#define OFF_BTN_IO PC7 +#define OFF_BTN_GRP PC +#define OFF_BTN_BIT 7 + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/StdDriver/inc/m480_clk.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/StdDriver/inc/m480_clk.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,628 @@
+/**************************************************************************//**
+ * @file CLK.h
+ * @version V1.0
+ * @brief M480 Series CLK Driver Header File
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+#ifndef __CLK_H__
+#define __CLK_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup CLK_Driver CLK Driver
+ @{
+*/
+
+/** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants
+ @{
+*/
+
+
+#define FREQ_25MHZ 25000000UL /*!< 25 MHz \hideinitializer */
+#define FREQ_50MHZ 50000000UL /*!< 50 MHz \hideinitializer */
+#define FREQ_72MHZ 72000000UL /*!< 72 MHz \hideinitializer */
+#define FREQ_80MHZ 80000000UL /*!< 80 MHz \hideinitializer */
+#define FREQ_100MHZ 100000000UL /*!< 100 MHz \hideinitializer */
+#define FREQ_125MHZ 125000000UL /*!< 125 MHz \hideinitializer */
+#define FREQ_160MHZ 160000000UL /*!< 160 MHz \hideinitializer */
+#define FREQ_192MHZ 192000000UL /*!< 192 MHz \hideinitializer */
+#define FREQ_200MHZ 200000000UL /*!< 200 MHz \hideinitializer */
+#define FREQ_250MHZ 250000000UL /*!< 250 MHz \hideinitializer */
+#define FREQ_500MHZ 500000000UL /*!< 500 MHz \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CLKSEL0 constant definitions. (Write-protection) */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKSEL0_HCLKSEL_HXT (0x0UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL0_HCLKSEL_LXT (0x1UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL0_HCLKSEL_PLL (0x2UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from PLL \hideinitializer */
+#define CLK_CLKSEL0_HCLKSEL_LIRC (0x3UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from low speed oscillator \hideinitializer */
+#define CLK_CLKSEL0_HCLKSEL_HIRC (0x7UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from high speed oscillator \hideinitializer */
+
+#define CLK_CLKSEL0_STCLKSEL_HXT (0x0UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL0_STCLKSEL_LXT (0x1UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL0_STCLKSEL_HXT_DIV2 (0x2UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HXT/2 \hideinitializer */
+#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x3UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HCLK/2 \hideinitializer */
+#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x7UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HIRC/2 \hideinitializer */
+#define CLK_CLKSEL0_STCLKSEL_HCLK (0x01UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< Select SysTick clock source from HCLK \hideinitializer */
+
+#if(0)
+#define CLK_CLKSEL0_PCLK0DIV1 (0x0UL << CLK_CLKSEL0_PCLK0SEL_Pos) /*!< Select PCLK0 clock source from HCLK \hideinitializer */
+#define CLK_CLKSEL0_PCLK0DIV2 (0x1UL << CLK_CLKSEL0_PCLK0SEL_Pos) /*!< Select PCLK0 clock source from 1/2 HCLK \hideinitializer */
+
+#define CLK_CLKSEL0_PCLK1DIV1 (0x0UL << CLK_CLKSEL0_PCLK1SEL_Pos) /*!< Select PCLK1 clock source from HCLK \hideinitializer */
+#define CLK_CLKSEL0_PCLK1DIV2 (0x1UL << CLK_CLKSEL0_PCLK1SEL_Pos) /*!< Select PCLK1 clock source from 1/2 HCLK \hideinitializer */
+#endif
+
+#define CLK_CLKSEL0_SDH0SEL_HXT (0x0UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL0_SDH0SEL_PLL (0x1UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL0_SDH0SEL_HIRC (0x3UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL0_SDH0SEL_HCLK (0x2UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from HCLK \hideinitializer */
+
+#define CLK_CLKSEL0_SDH1SEL_HXT (0x0UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL0_SDH1SEL_PLL (0x1UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL0_SDH1SEL_HIRC (0x3UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL0_SDH1SEL_HCLK (0x2UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from HCLK \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CLKSEL1 constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKSEL1_WDTSEL_LXT (0x1UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from low speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 (0x2UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from HCLK/2048 \hideinitializer */
+
+#define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from low speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from PCLK0 \hideinitializer */
+#define CLK_CLKSEL1_TMR0SEL_EXT (0x3UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from external trigger \hideinitializer */
+
+#define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL1_TMR1SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from low speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_TMR1SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_TMR1SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from PCLK0 \hideinitializer */
+#define CLK_CLKSEL1_TMR1SEL_EXT (0x3UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from external trigger \hideinitializer */
+
+#define CLK_CLKSEL1_TMR2SEL_HXT (0x0UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL1_TMR2SEL_LXT (0x1UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL1_TMR2SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from low speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_TMR2SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_TMR2SEL_PCLK1 (0x2UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from PCLK1 \hideinitializer */
+#define CLK_CLKSEL1_TMR2SEL_EXT (0x3UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from external trigger \hideinitializer */
+
+#define CLK_CLKSEL1_TMR3SEL_HXT (0x0UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL1_TMR3SEL_LXT (0x1UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL1_TMR3SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from low speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_TMR3SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_TMR3SEL_PCLK1 (0x2UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from PCLK1 \hideinitializer */
+#define CLK_CLKSEL1_TMR3SEL_EXT (0x3UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from external trigger \hideinitializer */
+
+#define CLK_CLKSEL1_UART0SEL_HXT (0x0UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL1_UART0SEL_LXT (0x2UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL1_UART0SEL_PLL (0x1UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL1_UART0SEL_HIRC (0x3UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from high speed oscillator \hideinitializer */
+
+#define CLK_CLKSEL1_UART1SEL_HXT (0x0UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL1_UART1SEL_LXT (0x2UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL1_UART1SEL_PLL (0x1UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL1_UART1SEL_HIRC (0x3UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from high speed oscillator \hideinitializer */
+
+#define CLK_CLKSEL1_CLKOSEL_HXT (0x0UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL1_CLKOSEL_LXT (0x1UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL1_CLKOSEL_HIRC (0x3UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_CLKOSEL_HCLK (0x2UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from HCLK \hideinitializer */
+
+#define CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL << CLK_CLKSEL1_WWDTSEL_Pos) /*!< Select WWDT clock source from low speed oscillator \hideinitializer */
+#define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 (0x2UL << CLK_CLKSEL1_WWDTSEL_Pos) /*!< Select WWDT clock source from HCLK/2048 \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CLKSEL2 constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKSEL2_QSPI0SEL_HXT (0x0UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL2_QSPI0SEL_PLL (0x1UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_QSPI0SEL_HIRC (0x3UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL2_QSPI0SEL_PCLK0 (0x2UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from PCLK0 \hideinitializer */
+
+#define CLK_CLKSEL2_SPI0SEL_HXT (0x0UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL2_SPI0SEL_PLL (0x1UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_SPI0SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL2_SPI0SEL_PCLK1 (0x2UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from PCLK1 \hideinitializer */
+
+#define CLK_CLKSEL2_SPI1SEL_HXT (0x0UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL2_SPI1SEL_PLL (0x1UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_SPI1SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL2_SPI1SEL_PCLK0 (0x2UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from PCLK0 \hideinitializer */
+
+#define CLK_CLKSEL2_EPWM0SEL_PLL (0x0UL << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< Select EPWM0 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_EPWM0SEL_PCLK0 (0x1UL << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< Select EPWM0 clock source from PCLK0 \hideinitializer */
+
+#define CLK_CLKSEL2_EPWM1SEL_PLL (0x0UL << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< Select EPWM1 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_EPWM1SEL_PCLK1 (0x1UL << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< Select EPWM1 clock source from PCLK1 \hideinitializer */
+
+#define CLK_CLKSEL2_BPWM0SEL_PLL (0x0UL << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< Select BPWM0 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_BPWM0SEL_PCLK0 (0x1UL << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< Select BPWM0 clock source from PCLK0 \hideinitializer */
+
+#define CLK_CLKSEL2_BPWM1SEL_PLL (0x0UL << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< Select BPWM1 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_BPWM1SEL_PCLK1 (0x1UL << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< Select BPWM1 clock source from PCLK1 \hideinitializer */
+
+#define CLK_CLKSEL2_SPI2SEL_HXT (0x0UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL2_SPI2SEL_PLL (0x1UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_SPI2SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL2_SPI2SEL_PCLK1 (0x2UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from PCLK1 \hideinitializer */
+
+#define CLK_CLKSEL2_SPI3SEL_HXT (0x0UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL2_SPI3SEL_PLL (0x1UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL2_SPI3SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL2_SPI3SEL_PCLK0 (0x2UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from PCLK0 \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CLKSEL3 constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKSEL3_SC0SEL_HXT (0x0UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_SC0SEL_PLL (0x1UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_SC0SEL_HIRC (0x3UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL3_SC0SEL_PCLK0 (0x2UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from PCLK0 \hideinitializer */
+
+#define CLK_CLKSEL3_SC1SEL_HXT (0x0UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_SC1SEL_PLL (0x1UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_SC1SEL_HIRC (0x3UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL3_SC1SEL_PCLK1 (0x2UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from PCLK1 \hideinitializer */
+
+#define CLK_CLKSEL3_SC2SEL_HXT (0x0UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_SC2SEL_PLL (0x1UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_SC2SEL_HIRC (0x3UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL3_SC2SEL_PCLK0 (0x2UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from PCLK0 \hideinitializer */
+
+#define CLK_CLKSEL3_RTCSEL_LXT (0x0UL << CLK_CLKSEL3_RTCSEL_Pos) /*!< Select RTC clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL3_RTCSEL_LIRC (0x1UL << CLK_CLKSEL3_RTCSEL_Pos) /*!< Select RTC clock source from low speed oscillator \hideinitializer */
+
+#define CLK_CLKSEL3_I2S0SEL_HXT (0x0UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_I2S0SEL_PLL (0x1UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_I2S0SEL_HIRC (0x3UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from high speed oscillator \hideinitializer */
+#define CLK_CLKSEL3_I2S0SEL_PCLK0 (0x2UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from PCLK0 \hideinitializer */
+
+#define CLK_CLKSEL3_UART2SEL_HXT (0x0UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART2SEL_LXT (0x2UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART2SEL_PLL (0x1UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_UART2SEL_HIRC (0x3UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from high speed oscillator \hideinitializer */
+
+#define CLK_CLKSEL3_UART3SEL_HXT (0x0UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART3SEL_LXT (0x2UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART3SEL_PLL (0x1UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_UART3SEL_HIRC (0x3UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from high speed oscillator \hideinitializer */
+
+#define CLK_CLKSEL3_UART4SEL_HXT (0x0UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART4SEL_LXT (0x2UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART4SEL_PLL (0x1UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_UART4SEL_HIRC (0x3UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from high speed oscillator \hideinitializer */
+
+#define CLK_CLKSEL3_UART5SEL_HXT (0x0UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from high speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART5SEL_LXT (0x2UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from low speed crystal \hideinitializer */
+#define CLK_CLKSEL3_UART5SEL_PLL (0x1UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from PLL \hideinitializer */
+#define CLK_CLKSEL3_UART5SEL_HIRC (0x3UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from high speed oscillator \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CLKDIV0 constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKDIV0_HCLK(x) (((x) - 1UL) << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLKDIV0 Setting for HCLK clock divider. It could be 1~16 \hideinitializer */
+#define CLK_CLKDIV0_USB(x) (((x) - 1UL) << CLK_CLKDIV0_USBDIV_Pos) /*!< CLKDIV0 Setting for USB clock divider. It could be 1~16 \hideinitializer */
+#define CLK_CLKDIV0_SDH0(x) (((x) - 1UL) << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLKDIV0 Setting for SDH0 clock divider. It could be 1~256 \hideinitializer */
+#define CLK_CLKDIV0_UART0(x) (((x) - 1UL) << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLKDIV0 Setting for UART0 clock divider. It could be 1~16 \hideinitializer */
+#define CLK_CLKDIV0_UART1(x) (((x) - 1UL) << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLKDIV0 Setting for UART1 clock divider. It could be 1~16 \hideinitializer */
+#define CLK_CLKDIV0_EADC(x) (((x) - 1UL) << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLKDIV0 Setting for EADC clock divider. It could be 1~256 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CLKDIV1 constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKDIV1_SC0(x) (((x) - 1UL) << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLKDIV1 Setting for SC0 clock divider. It could be 1~256 \hideinitializer */
+#define CLK_CLKDIV1_SC1(x) (((x) - 1UL) << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLKDIV1 Setting for SC1 clock divider. It could be 1~256 \hideinitializer */
+#define CLK_CLKDIV1_SC2(x) (((x) - 1UL) << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLKDIV1 Setting for SC2 clock divider. It could be 1~256 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CLKDIV3 constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKDIV3_EMAC(x) (((x) - 1UL) << CLK_CLKDIV3_EMACDIV_Pos) /*!< CLKDIV3 Setting for EMAC clock divider. It could be 1~256 \hideinitializer */
+#define CLK_CLKDIV3_SDH1(x) (((x) - 1UL) << CLK_CLKDIV3_SDH1DIV_Pos) /*!< CLKDIV3 Setting for SDH1 clock divider. It could be 1~256 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CLKDIV4 constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKDIV4_UART2(x) (((x) - 1UL) << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLKDIV4 Setting for UART2 clock divider. It could be 1~16 \hideinitializer */
+#define CLK_CLKDIV4_UART3(x) (((x) - 1UL) << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLKDIV4 Setting for UART3 clock divider. It could be 1~16 \hideinitializer */
+#define CLK_CLKDIV4_UART4(x) (((x) - 1UL) << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLKDIV4 Setting for UART4 clock divider. It could be 1~16 \hideinitializer */
+#define CLK_CLKDIV4_UART5(x) (((x) - 1UL) << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLKDIV4 Setting for UART5 clock divider. It could be 1~16 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* PCLKDIV constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#if(1)
+#define CLK_PCLKDIV_PCLK0DIV1 (0x0UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK0DIV2 (0x1UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/2 HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK0DIV4 (0x2UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/4 HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK0DIV8 (0x3UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/8 HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK0DIV16 (0x4UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/16 HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK1DIV1 (0x0UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK1DIV2 (0x1UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/2 HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK1DIV4 (0x2UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/4 HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK1DIV8 (0x3UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/8 HCLK \hideinitializer */
+#define CLK_PCLKDIV_PCLK1DIV16 (0x4UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/16 HCLK \hideinitializer */
+#endif
+/*---------------------------------------------------------------------------------------------------------*/
+/* PLLCTL constant definitions. PLL = FIN * 2 * NF / NR / NO */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_PLLCTL_PLLSRC_HXT 0x00000000UL /*!< For PLL clock source is HXT. 4MHz < FIN/NR < 8MHz \hideinitializer */
+#define CLK_PLLCTL_PLLSRC_HIRC 0x00080000UL /*!< For PLL clock source is HIRC. 4MHz < FIN/NR < 8MHz \hideinitializer */
+
+#define CLK_PLLCTL_NF(x) (((x)-2UL)) /*!< x must be constant and 2 <= x <= 513. 200MHz < FIN*2*NF/NR < 500MHz. \hideinitializer */
+#define CLK_PLLCTL_NR(x) (((x)-1UL)<<9) /*!< x must be constant and 1 <= x <= 32. 4MHz < FIN/NR < 8MHz \hideinitializer */
+
+#define CLK_PLLCTL_NO_1 0x0000UL /*!< For output divider is 1 \hideinitializer */
+#define CLK_PLLCTL_NO_2 0x4000UL /*!< For output divider is 2 \hideinitializer */
+#define CLK_PLLCTL_NO_4 0xC000UL /*!< For output divider is 4 \hideinitializer */
+
+#define CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 36UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
+#define CLK_PLLCTL_80MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 80MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
+#define CLK_PLLCTL_144MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 24UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
+#define CLK_PLLCTL_160MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 160MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
+#define CLK_PLLCTL_192MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 32UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 192MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
+
+#define CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 36UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
+#define CLK_PLLCTL_80MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 80MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
+#define CLK_PLLCTL_144MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 24UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
+#define CLK_PLLCTL_160MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 160MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
+#define CLK_PLLCTL_192MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 32UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 192MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* MODULE constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+
+/* APBCLK(31:30)|CLKSEL(29:28)|CLKSEL_Msk(27:25) |CLKSEL_Pos(24:20)|CLKDIV(19:18)|CLKDIV_Msk(17:10)|CLKDIV_Pos(9:5)|IP_EN_Pos(4:0) */
+
+#define MODULE_APBCLK(x) (((x) >>30) & 0x3UL) /*!< Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 \hideinitializer */
+#define MODULE_CLKSEL(x) (((x) >>28) & 0x3UL) /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 \hideinitializer */
+#define MODULE_CLKSEL_Msk(x) (((x) >>25) & 0x7UL) /*!< Calculate CLKSEL mask offset on MODULE index \hideinitializer */
+#define MODULE_CLKSEL_Pos(x) (((x) >>20) & 0x1fUL) /*!< Calculate CLKSEL position offset on MODULE index \hideinitializer */
+#define MODULE_CLKDIV(x) (((x) >>18) & 0x3UL) /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4 \hideinitializer */
+#define MODULE_CLKDIV_Msk(x) (((x) >>10) & 0xffUL) /*!< Calculate CLKDIV mask offset on MODULE index \hideinitializer */
+#define MODULE_CLKDIV_Pos(x) (((x) >>5 ) & 0x1fUL) /*!< Calculate CLKDIV position offset on MODULE index \hideinitializer */
+#define MODULE_IP_EN_Pos(x) (((x) >>0 ) & 0x1fUL) /*!< Calculate APBCLK offset on MODULE index \hideinitializer */
+#define MODULE_NoMsk 0x0UL /*!< Not mask on MODULE index \hideinitializer */
+#define NA MODULE_NoMsk /*!< Not Available \hideinitializer */
+
+#define MODULE_APBCLK_ENC(x) (((x) & 0x03UL) << 30) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 \hideinitializer */
+#define MODULE_CLKSEL_ENC(x) (((x) & 0x03UL) << 28) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 \hideinitializer */
+#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07UL) << 25) /*!< CLKSEL mask offset on MODULE index \hideinitializer */
+#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1fUL) << 20) /*!< CLKSEL position offset on MODULE index \hideinitializer */
+#define MODULE_CLKDIV_ENC(x) (((x) & 0x03UL) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4 \hideinitializer */
+#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xffUL) << 10) /*!< CLKDIV mask offset on MODULE index \hideinitializer */
+#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1fUL) << 5) /*!< CLKDIV position offset on MODULE index \hideinitializer */
+#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1fUL) << 0) /*!< AHBCLK/APBCLK offset on MODULE index \hideinitializer */
+
+#define PDMA_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< PDMA Module \hideinitializer */
+#define ISP_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< ISP Module \hideinitializer */
+#define EBI_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< EBI Module \hideinitializer */
+#define USBH_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(16UL<<0)) /*!< USBH Module \hideinitializer */
+#define EMAC_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(2UL<<18) |(0xFFUL<<10) |(16UL<<5) |(5UL<<0)) /*!< EMAC Module \hideinitializer */
+#define SDH0_MODULE ((0UL<<30)|(0UL<<28) |(0x3UL<<25) |(20UL<<20) |(0UL<<18) |(0xFFUL<<10) |(24UL<<5) |(6UL<<0)) /*!< SDH0 Module \hideinitializer */
+#define CRC_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0)) /*!< CRC Module \hideinitializer */
+#define HSUSBD_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(10UL<<0)) /*!< HSUSBD Module \hideinitializer */
+#define CRPT_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< CRPT Module \hideinitializer */
+#define SPIM_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(14UL<<0)) /*!< SPIM Module \hideinitializer */
+#define FMCIDLE_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(15UL<<0)) /*!< FMCIDLE Module \hideinitializer */
+#define SDH1_MODULE ((0UL<<30)|(0UL<<28) |(0x3UL<<25) |(22UL<<20) |(2UL<<18) |(0xFFUL<<10) |(24UL<<5) |(17UL<<0)) /*!< SDH1 Module \hideinitializer */
+#define WDT_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(0UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0)) /*!< WDT Module \hideinitializer */
+#define RTC_MODULE ((1UL<<30)|(3UL<<28) |(0x1UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< RTC Module \hideinitializer */
+#define TMR0_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< TMR0 Module \hideinitializer */
+#define TMR1_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(12UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< TMR1 Module \hideinitializer */
+#define TMR2_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(16UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0)) /*!< TMR2 Module \hideinitializer */
+#define TMR3_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(20UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(5UL<<0)) /*!< TMR3 Module \hideinitializer */
+#define CLKO_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(28UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< CLKO Module \hideinitializer */
+#define WWDT_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(30UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0)) /*!< WWDT Module \hideinitializer */
+#define ACMP01_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0)) /*!< ACMP01 Module \hideinitializer */
+#define I2C0_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0)) /*!< I2C0 Module \hideinitializer */
+#define I2C1_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0)) /*!< I2C1 Module \hideinitializer */
+#define I2C2_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(10UL<<0)) /*!< I2C2 Module \hideinitializer */
+#define QSPI0_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(2UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< QSPI0 Module \hideinitializer */
+#define SPI0_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(4UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(13UL<<0)) /*!< SPI0 Module \hideinitializer */
+#define SPI1_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(6UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(14UL<<0)) /*!< SPI1 Module \hideinitializer */
+#define SPI2_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(10UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(15UL<<0)) /*!< SPI2 Module \hideinitializer */
+#define UART0_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(24UL<<20) |(0UL<<18) |(0xFUL<<10) |(8UL<<5) |(16UL<<0)) /*!< UART0 Module \hideinitializer */
+#define UART1_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(26UL<<20) |(0UL<<18) |(0xFUL<<10) |(12UL<<5) |(17UL<<0)) /*!< UART1 Module \hideinitializer */
+#define UART2_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(24UL<<20) |(3UL<<18) |(0xFUL<<10) |(0UL<<5) |(18UL<<0)) /*!< UART2 Module \hideinitializer */
+#define UART3_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(26UL<<20) |(3UL<<18) |(0xFUL<<10) |(4UL<<5) |(19UL<<0)) /*!< UART3 Module \hideinitializer */
+#define UART4_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(28UL<<20) |(3UL<<18) |(0xFUL<<10) |(8UL<<5) |(20UL<<0)) /*!< UART4 Module \hideinitializer */
+#define UART5_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(30UL<<20) |(3UL<<18) |(0xFUL<<10) |(12UL<<5) |(21UL<<0)) /*!< UART5 Module \hideinitializer */
+#define CAN0_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(24UL<<0)) /*!< CAN0 Module \hideinitializer */
+#define CAN1_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(25UL<<0)) /*!< CAN1 Module \hideinitializer */
+#define OTG_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0)) /*!< OTG Module \hideinitializer */
+#define USBD_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(27UL<<0)) /*!< USBD Module \hideinitializer */
+#define EADC_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(0UL<<18) |(0xFFUL<<10) |(16UL<<5) |(28UL<<0)) /*!< EADC Module \hideinitializer */
+#define I2S0_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(16UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(29UL<<0)) /*!< I2S0 Module \hideinitializer */
+#define HSOTG_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(30UL<<0)) /*!< HSOTG Module \hideinitializer */
+#define SC0_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(0UL<<20) |(1UL<<18) |(0xFFUL<<10) |(0UL<<5) |(0UL<<0)) /*!< SC0 Module \hideinitializer */
+#define SC1_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(2UL<<20) |(1UL<<18) |(0xFFUL<<10) |(8UL<<5) |(1UL<<0)) /*!< SC1 Module \hideinitializer */
+#define SC2_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(4UL<<20) |(1UL<<18) |(0xFFUL<<10) |(16UL<<5) |(2UL<<0)) /*!< SC2 Module \hideinitializer */
+#define SPI3_MODULE ((2UL<<30)|(2UL<<28) |(0x3UL<<25) |(12UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< SPI3 Module \hideinitializer */
+#define USCI0_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0)) /*!< USCI0 Module \hideinitializer */
+#define USCI1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0)) /*!< USCI1 Module \hideinitializer */
+#define DAC_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< DAC Module \hideinitializer */
+#define EPWM0_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(0UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(16UL<<0)) /*!< EPWM0 Module \hideinitializer */
+#define EPWM1_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(1UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(17UL<<0)) /*!< EPWM1 Module \hideinitializer */
+#define BPWM0_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(18UL<<0)) /*!< BPWM0 Module \hideinitializer */
+#define BPWM1_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(9UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(19UL<<0)) /*!< BPWM1 Module \hideinitializer */
+#define QEI0_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(22UL<<0)) /*!< QEI0 Module \hideinitializer */
+#define QEI1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(23UL<<0)) /*!< QEI1 Module \hideinitializer */
+#define ECAP0_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0)) /*!< ECAP0 Module \hideinitializer */
+#define ECAP1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(27UL<<0)) /*!< ECAP1 Module \hideinitializer */
+#define OPA_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(30UL<<0)) /*!< OPA Module \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* PDMSEL constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_PMUCTL_PDMSEL_PD (0x0UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Power-down mode \hideinitializer */
+#define CLK_PMUCTL_PDMSEL_LLPD (0x1UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Low leakage Power-down mode \hideinitializer */
+#define CLK_PMUCTL_PDMSEL_FWPD (0x2UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Fast wake-up Power-down mode \hideinitializer */
+#define CLK_PMUCTL_PDMSEL_SPD0 (0x4UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Standby Power-down mode 0 \hideinitializer */
+#define CLK_PMUCTL_PDMSEL_SPD1 (0x5UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Standby Power-down mode 1 \hideinitializer */
+#define CLK_PMUCTL_PDMSEL_DPD (0x6UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Deep Power-down mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* WKTMRIS constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_PMUCTL_WKTMRIS_128 (0x0UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 128 OSC10K clocks (12.8 ms) \hideinitializer */
+#define CLK_PMUCTL_WKTMRIS_256 (0x1UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 256 OSC10K clocks (25.6 ms) \hideinitializer */
+#define CLK_PMUCTL_WKTMRIS_512 (0x2UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 512 OSC10K clocks (51.2 ms) \hideinitializer */
+#define CLK_PMUCTL_WKTMRIS_1024 (0x3UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 1024 OSC10K clocks (102.4ms) \hideinitializer */
+#define CLK_PMUCTL_WKTMRIS_4096 (0x4UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 4096 OSC10K clocks (409.6ms) \hideinitializer */
+#define CLK_PMUCTL_WKTMRIS_8192 (0x5UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 8192 OSC10K clocks (819.2ms) \hideinitializer */
+#define CLK_PMUCTL_WKTMRIS_16384 (0x6UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 16384 OSC10K clocks (1638.4ms) \hideinitializer */
+#define CLK_PMUCTL_WKTMRIS_65536 (0x7UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 65536 OSC10K clocks (6553.6ms) \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* SWKDBCLKSEL constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_SWKDBCTL_SWKDBCLKSEL_1 (0x0UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 1 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_2 (0x1UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_4 (0x2UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_8 (0x3UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_16 (0x4UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_32 (0x5UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_64 (0x6UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_128 (0x7UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_256 (0x8UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 256 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_2x256 (0x9UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2x256 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_4x256 (0xaUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4x256 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_8x256 (0xbUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8x256 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_16x256 (0xcUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16x256 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_32x256 (0xdUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32x256 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_64x256 (0xeUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64x256 clocks \hideinitializer */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_128x256 (0xfUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128x256 clocks \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* DPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_DPDWKPIN_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Disable Wake-up pin at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN_RISING (0x1UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin rising edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN_FALLING (0x2UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin falling edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin both edge at Deep Power-down mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* SPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_SPDWKPIN_ENABLE (0x1UL << 0) /*!< Enable Standby Power-down Pin Wake-up \hideinitializer */
+#define CLK_SPDWKPIN_RISING (0x1UL << 1) /*!< Standby Power-down Wake-up on Standby Power-down Pin rising edge \hideinitializer */
+#define CLK_SPDWKPIN_FALLING (0x1UL << 2) /*!< Standby Power-down Wake-up on Standby Power-down Pin falling edge \hideinitializer */
+#define CLK_SPDWKPIN_DEBOUNCEEN (0x1UL << 8) /*!< Enable Standby power-down pin De-bounce function \hideinitializer */
+#define CLK_SPDWKPIN_DEBOUNCEDIS (0x0UL << 8) /*!< Disable Standby power-down pin De-bounce function \hideinitializer */
+
+#define CLK_DISABLE_WKTMR(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKTMREN_Msk) /*!< Disable Wake-up timer at Standby or Deep Power-down mode \hideinitializer */
+#define CLK_ENABLE_WKTMR(void) (CLK->PMUCTL |= CLK_PMUCTL_WKTMREN_Msk) /*!< Enable Wake-up timer at Standby or Deep Power-down mode \hideinitializer */
+#define CLK_DISABLE_DPDWKPIN(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN_Msk) /*!< Disable Wake-up pin at Deep Power-down mode \hideinitializer */
+#define CLK_DISABLE_SPDACMP(void) (CLK->PMUCTL &= ~CLK_PMUCTL_ACMPSPWK_Msk) /*!< Disable ACMP wake-up at Standby Power-down mode \hideinitializer */
+#define CLK_ENABLE_SPDACMP(void) (CLK->PMUCTL |= CLK_PMUCTL_ACMPSPWK_Msk) /*!< Enable ACMP wake-up at Standby Power-down mode \hideinitializer */
+#define CLK_DISABLE_RTCWK(void) (CLK->PMUCTL &= ~CLK_PMUCTL_RTCWKEN_Msk) /*!< Disable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */
+#define CLK_ENABLE_RTCWK(void) (CLK->PMUCTL |= CLK_PMUCTL_RTCWKEN_Msk) /*!< Enable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */
+
+/*@}*/ /* end of group CLK_EXPORTED_CONSTANTS */
+
+/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions
+ @{
+*/
+
+/**
+ * @brief Set Wake-up Timer Time-out Interval
+ *
+ * @param[in] u32Interval The Wake-up Timer Time-out Interval selection. It could be
+ * - \ref CLK_PMUCTL_WKTMRIS_128
+ * - \ref CLK_PMUCTL_WKTMRIS_256
+ * - \ref CLK_PMUCTL_WKTMRIS_512
+ * - \ref CLK_PMUCTL_WKTMRIS_1024
+ * - \ref CLK_PMUCTL_WKTMRIS_4096
+ * - \ref CLK_PMUCTL_WKTMRIS_8192
+ * - \ref CLK_PMUCTL_WKTMRIS_16384
+ * - \ref CLK_PMUCTL_WKTMRIS_65536
+ *
+ * @return None
+ *
+ * @details This function set Wake-up Timer Time-out Interval.
+ *
+ * \hideinitializer
+ */
+#define CLK_SET_WKTMR_INTERVAL(u32Interval) (CLK->PMUCTL |= (u32Interval))
+
+/**
+ * @brief Set De-bounce Sampling Cycle Time
+ *
+ * @param[in] u32CycleSel The de-bounce sampling cycle selection. It could be
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_1
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_256
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2x256
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4x256
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8x256
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16x256
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32x256
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64x256
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128x256
+ *
+ * @return None
+ *
+ * @details This function set Set De-bounce Sampling Cycle Time.
+ *
+ * \hideinitializer
+ */
+#define CLK_SET_SPDDEBOUNCETIME(u32CycleSel) (CLK->SWKDBCTL = (u32CycleSel))
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* static inline functions */
+/*---------------------------------------------------------------------------------------------------------*/
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+__STATIC_INLINE void CLK_SysTickDelay(uint32_t us);
+__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us);
+
+/**
+ * @brief This function execute delay function.
+ * @param[in] us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex:
+ * 72MHz => 233016us, 50MHz => 335544us,
+ * 48MHz => 349525us, 28MHz => 699050us ...
+ * @return None
+ * @details Use the SysTick to generate the delay time and the unit is in us.
+ * The SysTick clock source is from HCLK, i.e the same as system core clock.
+ */
+__STATIC_INLINE void CLK_SysTickDelay(uint32_t us)
+{
+ SysTick->LOAD = us * CyclesPerUs;
+ SysTick->VAL = 0x0UL;
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
+
+ /* Waiting for down-count to zero */
+ while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL) {
+ }
+
+ /* Disable SysTick counter */
+ SysTick->CTRL = 0UL;
+}
+
+/**
+ * @brief This function execute long delay function.
+ * @param[in] us Delay time.
+ * @return None
+ * @details Use the SysTick to generate the long delay time and the UNIT is in us.
+ * The SysTick clock source is from HCLK, i.e the same as system core clock.
+ * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.
+ */
+__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us)
+{
+ uint32_t delay;
+ /* It should <= 349525us for each delay loop */
+ delay = 349525UL;
+
+ do {
+ if (us > delay) {
+ us -= delay;
+ } else {
+ delay = us;
+ us = 0UL;
+ }
+
+ SysTick->LOAD = delay * CyclesPerUs;
+ SysTick->VAL = (0x0UL);
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
+
+ /* Waiting for down-count to zero */
+ while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL);
+
+ /* Disable SysTick counter */
+ SysTick->CTRL = 0UL;
+ } while (us > 0UL);
+}
+
+
+void CLK_DisableCKO(void);
+void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
+void CLK_PowerDown(void);
+void CLK_Idle(void);
+uint32_t CLK_GetHXTFreq(void);
+uint32_t CLK_GetLXTFreq(void);
+uint32_t CLK_GetHCLKFreq(void);
+uint32_t CLK_GetPCLK0Freq(void);
+uint32_t CLK_GetPCLK1Freq(void);
+uint32_t CLK_GetCPUFreq(void);
+uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
+void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
+void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
+void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
+void CLK_EnableXtalRC(uint32_t u32ClkMask);
+void CLK_DisableXtalRC(uint32_t u32ClkMask);
+void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
+void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
+uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
+void CLK_DisablePLL(void);
+uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
+void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
+void CLK_DisableSysTick(void);
+void CLK_SetPowerDownMode(uint32_t u32PDMode);
+void CLK_EnableDPDWKPin(uint32_t u32TriggerType);
+uint32_t CLK_GetPMUWKSrc(void);
+void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn);
+uint32_t CLK_GetPLLClockFreq(void);
+uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx);
+uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx);
+
+/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CLK_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CLK_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/StdDriver/inc/m480_fmc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/StdDriver/inc/m480_fmc.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,310 @@
+/**************************************************************************//**
+ * @file fmc.h
+ * @version V1.00
+ * @brief M480 Series Flash Memory Controller Driver Header File
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+#ifndef __FMC_H__
+#define __FMC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup FMC_Driver FMC Driver
+ @{
+*/
+
+
+/** @addtogroup FMC_EXPORTED_CONSTANTS FMC Exported Constants
+ @{
+*/
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define Base Address */
+/*---------------------------------------------------------------------------------------------------------*/
+#define FMC_APROM_BASE 0x00000000UL /*!< APROM base address \hideinitializer */
+#define FMC_APROM_END 0x00080000UL /*!< APROM end address \hideinitializer */
+#define FMC_APROM_BANK0_END (FMC_APROM_END/2UL) /*!< APROM bank0 end address \hideinitializer */
+#define FMC_LDROM_BASE 0x00100000UL /*!< LDROM base address \hideinitializer */
+#define FMC_LDROM_END 0x00101000UL /*!< LDROM end address \hideinitializer */
+#define FMC_SPROM_BASE 0x00200000UL /*!< SPROM base address \hideinitializer */
+#define FMC_SPROM_END 0x00201000UL /*!< SPROM end address \hideinitializer */
+#define FMC_CONFIG_BASE 0x00300000UL /*!< User Configuration address \hideinitializer */
+#define FMC_USER_CONFIG_0 0x00300000UL /*!< User Config 0 address \hideinitializer */
+#define FMC_USER_CONFIG_1 0x00300004UL /*!< User Config 1 address \hideinitializer */
+#define FMC_USER_CONFIG_2 0x00300008UL /*!< User Config 2 address \hideinitializer */
+#define FMC_KPROM_BASE 0x00301000UL /*!< Security ROM base address \hideinitializer */
+#define FMC_OTP_BASE 0x00310000UL /*!< OTP flash base address \hideinitializer */
+
+#define FMC_FLASH_PAGE_SIZE 0x1000UL /*!< Flash Page Size (4K bytes) \hideinitializer */
+#define FMC_PAGE_ADDR_MASK 0xFFFFF000UL /*!< Flash page address mask \hideinitializer */
+#define FMC_MULTI_WORD_PROG_LEN 512 /*!< The maximum length of a multi-word program. */
+
+#define FMC_APROM_SIZE FMC_APROM_END /*!< APROM Size \hideinitializer */
+#define FMC_BANK_SIZE (FMC_APROM_SIZE/2UL) /*!< APROM Bank Size \hideinitializer */
+#define FMC_LDROM_SIZE 0x1000UL /*!< LDROM Size (4 Kbytes) \hideinitializer */
+#define FMC_SPROM_SIZE 0x1000UL /*!< SPROM Size (4 Kbytes) \hideinitializer */
+#define FMC_OTP_ENTRY_CNT 256UL /*!< OTP entry number \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ISPCMD constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define FMC_ISPCMD_READ 0x00UL /*!< ISP Command: Read flash word \hideinitializer */
+#define FMC_ISPCMD_READ_UID 0x04UL /*!< ISP Command: Read Unique ID \hideinitializer */
+#define FMC_ISPCMD_READ_ALL1 0x08UL /*!< ISP Command: Read all-one result \hideinitializer */
+#define FMC_ISPCMD_READ_CID 0x0BUL /*!< ISP Command: Read Company ID \hideinitializer */
+#define FMC_ISPCMD_READ_DID 0x0CUL /*!< ISP Command: Read Device ID \hideinitializer */
+#define FMC_ISPCMD_READ_CKS 0x0DUL /*!< ISP Command: Read checksum \hideinitializer */
+#define FMC_ISPCMD_PROGRAM 0x21UL /*!< ISP Command: Write flash word \hideinitializer */
+#define FMC_ISPCMD_PAGE_ERASE 0x22UL /*!< ISP Command: Page Erase Flash \hideinitializer */
+#define FMC_ISPCMD_BANK_ERASE 0x23UL /*!< ISP Command: Erase Flash bank 0 or 1 \hideinitializer */
+#define FMC_ISPCMD_BLOCK_ERASE 0x25UL /*!< ISP Command: Erase 4 pages alignment of APROM in bank 0 or 1 \hideinitializer */
+#define FMC_ISPCMD_PROGRAM_MUL 0x27UL /*!< ISP Command: Multuple word program \hideinitializer */
+#define FMC_ISPCMD_RUN_ALL1 0x28UL /*!< ISP Command: Run all-one verification \hideinitializer */
+#define FMC_ISPCMD_RUN_CKS 0x2DUL /*!< ISP Command: Run checksum calculation \hideinitializer */
+#define FMC_ISPCMD_VECMAP 0x2EUL /*!< ISP Command: Vector Page Remap \hideinitializer */
+#define FMC_ISPCMD_READ_64 0x40UL /*!< ISP Command: Read double flash word \hideinitializer */
+#define FMC_ISPCMD_PROGRAM_64 0x61UL /*!< ISP Command: Write double flash word \hideinitializer */
+
+#define IS_BOOT_FROM_APROM 0UL /*!< Is booting from APROM \hideinitializer */
+#define IS_BOOT_FROM_LDROM 1UL /*!< Is booting from LDROM \hideinitializer */
+
+#define READ_ALLONE_YES 0xA11FFFFFUL /*!< Check-all-one result is all one. \hideinitializer */
+#define READ_ALLONE_NOT 0xA1100000UL /*!< Check-all-one result is not all one. \hideinitializer */
+#define READ_ALLONE_CMD_FAIL 0xFFFFFFFFUL /*!< Check-all-one command failed. \hideinitializer */
+
+
+/*@}*/ /* end of group FMC_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup FMC_EXPORTED_MACROS FMC Exported Macros
+ @{
+*/
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Macros */
+/*---------------------------------------------------------------------------------------------------------*/
+
+#define FMC_SET_APROM_BOOT() (FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk) /*!< Select booting from APROM \hideinitializer */
+#define FMC_SET_LDROM_BOOT() (FMC->ISPCTL |= FMC_ISPCTL_BS_Msk) /*!< Select booting from LDROM \hideinitializer */
+#define FMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk) /*!< Enable APROM update \hideinitializer */
+#define FMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk) /*!< Disable APROM update \hideinitializer */
+#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk) /*!< Enable User Config update \hideinitializer */
+#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk) /*!< Disable User Config update \hideinitializer */
+#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk) /*!< Enable LDROM update \hideinitializer */
+#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk) /*!< Disable LDROM update \hideinitializer */
+#define FMC_ENABLE_SP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_SPUEN_Msk) /*!< Enable SPROM update \hideinitializer */
+#define FMC_DISABLE_SP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_SPUEN_Msk) /*!< Disable SPROM update \hideinitializer */
+#define FMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk) /*!< Disable ISP function \hideinitializer */
+#define FMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk) /*!< Enable ISP function \hideinitializer */
+#define FMC_GET_FAIL_FLAG() ((FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1UL : 0UL) /*!< Get ISP fail flag \hideinitializer */
+#define FMC_CLR_FAIL_FLAG() (FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk) /*!< Clear ISP fail flag \hideinitializer */
+
+/*@}*/ /* end of group FMC_EXPORTED_MACROS */
+
+
+/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* inline functions */
+/*---------------------------------------------------------------------------------------------------------*/
+
+__STATIC_INLINE uint32_t FMC_ReadCID(void);
+__STATIC_INLINE uint32_t FMC_ReadPID(void);
+__STATIC_INLINE uint32_t FMC_ReadUID(uint8_t u8Index);
+__STATIC_INLINE uint32_t FMC_ReadUCID(uint32_t u32Index);
+__STATIC_INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr);
+__STATIC_INLINE uint32_t FMC_GetVECMAP(void);
+
+/**
+ * @brief Get current vector mapping address.
+ * @param None
+ * @return The current vector mapping address.
+ * @details To get VECMAP value which is the page address for remapping to vector page (0x0).
+ * @note
+ * VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b)
+ */
+__STATIC_INLINE uint32_t FMC_GetVECMAP(void)
+{
+ return (FMC->ISPSTS & FMC_ISPSTS_VECMAP_Msk);
+}
+
+/**
+ * @brief Read company ID
+ * @param None
+ * @return The company ID (32-bit)
+ * @details The company ID of Nuvoton is fixed to be 0xDA
+ */
+__STATIC_INLINE uint32_t FMC_ReadCID(void)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ_CID; /* Set ISP Command Code */
+ FMC->ISPADDR = 0x0u; /* Must keep 0x0 when read CID */
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
+#if ISBEN
+ __ISB();
+#endif /* To make sure ISP/CPU be Synchronized */
+
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */
+
+ return FMC->ISPDAT;
+}
+
+/**
+ * @brief Read product ID
+ * @param None
+ * @return The product ID (32-bit)
+ * @details This function is used to read product ID.
+ */
+__STATIC_INLINE uint32_t FMC_ReadPID(void)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ_DID; /* Set ISP Command Code */
+ FMC->ISPADDR = 0x04u; /* Must keep 0x4 when read PID */
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
+#if ISBEN
+ __ISB();
+#endif /* To make sure ISP/CPU be Synchronized */
+
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */
+
+ return FMC->ISPDAT;
+}
+
+/**
+ * @brief Read Unique ID
+ * @param[in] u8Index UID index. 0 = UID[31:0], 1 = UID[63:32], 2 = UID[95:64]
+ * @return The 32-bit unique ID data of specified UID index.
+ * @details To read out 96-bit Unique ID.
+ */
+__STATIC_INLINE uint32_t FMC_ReadUID(uint8_t u8Index)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ_UID;
+ FMC->ISPADDR = ((uint32_t)u8Index << 2u);
+ FMC->ISPDAT = 0u;
+ FMC->ISPTRG = 0x1u;
+#if ISBEN
+ __ISB();
+#endif
+
+ while (FMC->ISPTRG) {}
+
+ return FMC->ISPDAT;
+}
+
+/**
+ * @brief To read UCID
+ * @param[in] u32Index Index of the UCID to read. u32Index must be 0, 1, 2, or 3.
+ * @return The UCID of specified index
+ * @details This function is used to read unique chip ID (UCID).
+ */
+__STATIC_INLINE uint32_t FMC_ReadUCID(uint32_t u32Index)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */
+ FMC->ISPADDR = (0x04u * u32Index) + 0x10u; /* The UCID is at offset 0x10 with word alignment. */
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
+#if ISBEN
+ __ISB();
+#endif /* To make sure ISP/CPU be Synchronized */
+
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */
+
+ return FMC->ISPDAT;
+}
+
+/**
+ * @brief Set vector mapping address
+ * @param[in] u32PageAddr The page address to remap to address 0x0. The address must be page alignment.
+ * @return To set VECMAP to remap specified page address to 0x0.
+ * @details This function is used to set VECMAP to map specified page to vector page (0x0).
+ * @note
+ * VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b)
+ */
+__STATIC_INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr)
+{
+ FMC->ISPCMD = FMC_ISPCMD_VECMAP; /* Set ISP Command Code */
+ FMC->ISPADDR = u32PageAddr; /* The address of specified page which will be map to address 0x0. It must be page alignment. */
+ FMC->ISPTRG = 0x1u; /* Trigger to start ISP procedure */
+#if ISBEN
+ __ISB();
+#endif /* To make sure ISP/CPU be Synchronized */
+
+ while (FMC->ISPTRG) {} /* Waiting for ISP Done */
+}
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Functions */
+/*---------------------------------------------------------------------------------------------------------*/
+
+extern void FMC_Close(void);
+extern int32_t FMC_Erase(uint32_t u32PageAddr);
+extern int32_t FMC_Erase_SPROM(void);
+extern int32_t FMC_Erase_Block(uint32_t u32BlockAddr);
+extern int32_t FMC_Erase_Bank(uint32_t u32BankAddr);
+extern int32_t FMC_GetBootSource(void);
+extern void FMC_Open(void);
+extern uint32_t FMC_Read(uint32_t u32Addr);
+extern int32_t FMC_Read_64(uint32_t u32addr, uint32_t *u32data0, uint32_t *u32data1);
+extern uint32_t FMC_ReadDataFlashBaseAddr(void);
+extern void FMC_SetBootSource(int32_t i32BootSrc);
+extern void FMC_Write(uint32_t u32Addr, uint32_t u32Data);
+extern int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1);
+extern int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len);
+extern int32_t FMC_Write_OTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word);
+extern int32_t FMC_Read_OTP(uint32_t otp_num, uint32_t *low_word, uint32_t *high_word);
+extern int32_t FMC_Lock_OTP(uint32_t otp_num);
+extern int32_t FMC_Is_OTP_Locked(uint32_t otp_num);
+extern int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count);
+extern int32_t FMC_WriteConfig(uint32_t u32Config[], uint32_t u32Count);
+extern uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count);
+extern uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count);
+extern int32_t FMC_SetSPKey(uint32_t key[3], uint32_t kpmax, uint32_t kemax, const int32_t lock_CONFIG, const int32_t lock_SPROM);
+extern int32_t FMC_CompareSPKey(uint32_t key[3]);
+
+
+/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group FMC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FMC_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/StdDriver/inc/m480_gpio.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/StdDriver/inc/m480_gpio.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,518 @@
+/**************************************************************************//**
+ * @file GPIO.h
+ * @version V3.00
+ * @brief M480 series GPIO driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+#ifndef __GPIO_H__
+#define __GPIO_H__
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup GPIO_Driver GPIO Driver
+ @{
+*/
+
+/** @addtogroup GPIO_EXPORTED_CONSTANTS GPIO Exported Constants
+ @{
+*/
+
+
+#define GPIO_PIN_MAX 16UL /*!< Specify Maximum Pins of Each GPIO Port \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* GPIO_MODE Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_MODE_INPUT 0x0UL /*!< Input Mode \hideinitializer */
+#define GPIO_MODE_OUTPUT 0x1UL /*!< Output Mode \hideinitializer */
+#define GPIO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode \hideinitializer */
+#define GPIO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* GPIO Interrupt Type Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge \hideinitializer */
+#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge \hideinitializer */
+#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge \hideinitializer */
+#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High \hideinitializer */
+#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* GPIO_INTTYPE Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_INTTYPE_EDGE 0UL /*!< GPIO_INTTYPE Setting for Edge Trigger Mode \hideinitializer */
+#define GPIO_INTTYPE_LEVEL 1UL /*!< GPIO_INTTYPE Setting for Edge Level Mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* GPIO Slew Rate Type Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_SLEWCTL_NORMAL 0x0UL /*!< GPIO slew setting for normal Mode \hideinitializer */
+#define GPIO_SLEWCTL_HIGH 0x1UL /*!< GPIO slew setting for high Mode \hideinitializer */
+#define GPIO_SLEWCTL_FAST 0x2UL /*!< GPIO slew setting for fast Mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* GPIO Pull-up And Pull-down Type Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_PUSEL_DISABLE 0x0UL /*!< GPIO PUSEL setting for Disable Mode \hideinitializer */
+#define GPIO_PUSEL_PULL_UP 0x1UL /*!< GPIO PUSEL setting for Pull-up Mode \hideinitializer */
+#define GPIO_PUSEL_PULL_DOWN 0x2UL /*!< GPIO PUSEL setting for Pull-down Mode \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* GPIO_DBCTL Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_DBCTL_ICLK_ON 0x00000020UL /*!< GPIO_DBCTL setting for all IO pins edge detection circuit is always active after reset \hideinitializer */
+#define GPIO_DBCTL_ICLK_OFF 0x00000000UL /*!< GPIO_DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 \hideinitializer */
+
+#define GPIO_DBCTL_DBCLKSRC_LIRC 0x00000010UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the internal 10 kHz \hideinitializer */
+#define GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the HCLK \hideinitializer */
+
+#define GPIO_DBCTL_DBCLKSEL_1 0x00000000UL /*!< GPIO_DBCTL setting for sampling cycle = 1 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_2 0x00000001UL /*!< GPIO_DBCTL setting for sampling cycle = 2 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_4 0x00000002UL /*!< GPIO_DBCTL setting for sampling cycle = 4 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_8 0x00000003UL /*!< GPIO_DBCTL setting for sampling cycle = 8 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_16 0x00000004UL /*!< GPIO_DBCTL setting for sampling cycle = 16 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_32 0x00000005UL /*!< GPIO_DBCTL setting for sampling cycle = 32 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_64 0x00000006UL /*!< GPIO_DBCTL setting for sampling cycle = 64 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_128 0x00000007UL /*!< GPIO_DBCTL setting for sampling cycle = 128 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_256 0x00000008UL /*!< GPIO_DBCTL setting for sampling cycle = 256 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_512 0x00000009UL /*!< GPIO_DBCTL setting for sampling cycle = 512 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL /*!< GPIO_DBCTL setting for sampling cycle = 1024 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL /*!< GPIO_DBCTL setting for sampling cycle = 2048 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL /*!< GPIO_DBCTL setting for sampling cycle = 4096 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL /*!< GPIO_DBCTL setting for sampling cycle = 8192 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL /*!< GPIO_DBCTL setting for sampling cycle = 16384 clocks \hideinitializer */
+#define GPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL /*!< GPIO_DBCTL setting for sampling cycle = 32768 clocks \hideinitializer */
+
+
+/* Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping.
+ Example 1:
+
+ PA0 = 1;
+
+ It is used to set GPIO PA.0 to high;
+
+ Example 2:
+
+ if (PA0)
+ PA0 = 0;
+
+ If GPIO PA.0 pin status is high, then set GPIO PA.0 data output to low.
+ */
+#define GPIO_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2)))) /*!< Pin Data Input/Output \hideinitializer */
+#define PA0 GPIO_PIN_DATA(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output \hideinitializer */
+#define PA1 GPIO_PIN_DATA(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output \hideinitializer */
+#define PA2 GPIO_PIN_DATA(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output \hideinitializer */
+#define PA3 GPIO_PIN_DATA(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output \hideinitializer */
+#define PA4 GPIO_PIN_DATA(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output \hideinitializer */
+#define PA5 GPIO_PIN_DATA(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output \hideinitializer */
+#define PA6 GPIO_PIN_DATA(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output \hideinitializer */
+#define PA7 GPIO_PIN_DATA(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output \hideinitializer */
+#define PA8 GPIO_PIN_DATA(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output \hideinitializer */
+#define PA9 GPIO_PIN_DATA(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output \hideinitializer */
+#define PA10 GPIO_PIN_DATA(0, 10) /*!< Specify PA.10 Pin Data Input/Output \hideinitializer */
+#define PA11 GPIO_PIN_DATA(0, 11) /*!< Specify PA.11 Pin Data Input/Output \hideinitializer */
+#define PA12 GPIO_PIN_DATA(0, 12) /*!< Specify PA.12 Pin Data Input/Output \hideinitializer */
+#define PA13 GPIO_PIN_DATA(0, 13) /*!< Specify PA.13 Pin Data Input/Output \hideinitializer */
+#define PA14 GPIO_PIN_DATA(0, 14) /*!< Specify PA.14 Pin Data Input/Output \hideinitializer */
+#define PA15 GPIO_PIN_DATA(0, 15) /*!< Specify PA.15 Pin Data Input/Output \hideinitializer */
+#define PB0 GPIO_PIN_DATA(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output \hideinitializer */
+#define PB1 GPIO_PIN_DATA(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output \hideinitializer */
+#define PB2 GPIO_PIN_DATA(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output \hideinitializer */
+#define PB3 GPIO_PIN_DATA(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output \hideinitializer */
+#define PB4 GPIO_PIN_DATA(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output \hideinitializer */
+#define PB5 GPIO_PIN_DATA(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output \hideinitializer */
+#define PB6 GPIO_PIN_DATA(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output \hideinitializer */
+#define PB7 GPIO_PIN_DATA(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output \hideinitializer */
+#define PB8 GPIO_PIN_DATA(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output \hideinitializer */
+#define PB9 GPIO_PIN_DATA(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output \hideinitializer */
+#define PB10 GPIO_PIN_DATA(1, 10) /*!< Specify PB.10 Pin Data Input/Output \hideinitializer */
+#define PB11 GPIO_PIN_DATA(1, 11) /*!< Specify PB.11 Pin Data Input/Output \hideinitializer */
+#define PB12 GPIO_PIN_DATA(1, 12) /*!< Specify PB.12 Pin Data Input/Output \hideinitializer */
+#define PB13 GPIO_PIN_DATA(1, 13) /*!< Specify PB.13 Pin Data Input/Output \hideinitializer */
+#define PB14 GPIO_PIN_DATA(1, 14) /*!< Specify PB.14 Pin Data Input/Output \hideinitializer */
+#define PB15 GPIO_PIN_DATA(1, 15) /*!< Specify PB.15 Pin Data Input/Output \hideinitializer */
+#define PC0 GPIO_PIN_DATA(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output \hideinitializer */
+#define PC1 GPIO_PIN_DATA(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output \hideinitializer */
+#define PC2 GPIO_PIN_DATA(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output \hideinitializer */
+#define PC3 GPIO_PIN_DATA(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output \hideinitializer */
+#define PC4 GPIO_PIN_DATA(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output \hideinitializer */
+#define PC5 GPIO_PIN_DATA(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output \hideinitializer */
+#define PC6 GPIO_PIN_DATA(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output \hideinitializer */
+#define PC7 GPIO_PIN_DATA(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output \hideinitializer */
+#define PC8 GPIO_PIN_DATA(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output \hideinitializer */
+#define PC9 GPIO_PIN_DATA(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output \hideinitializer */
+#define PC10 GPIO_PIN_DATA(2, 10) /*!< Specify PC.10 Pin Data Input/Output \hideinitializer */
+#define PC11 GPIO_PIN_DATA(2, 11) /*!< Specify PC.11 Pin Data Input/Output \hideinitializer */
+#define PC12 GPIO_PIN_DATA(2, 12) /*!< Specify PC.12 Pin Data Input/Output \hideinitializer */
+#define PC13 GPIO_PIN_DATA(2, 13) /*!< Specify PC.13 Pin Data Input/Output \hideinitializer */
+#define PC14 GPIO_PIN_DATA(2, 14) /*!< Specify PC.14 Pin Data Input/Output \hideinitializer */
+#define PD0 GPIO_PIN_DATA(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output \hideinitializer */
+#define PD1 GPIO_PIN_DATA(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output \hideinitializer */
+#define PD2 GPIO_PIN_DATA(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output \hideinitializer */
+#define PD3 GPIO_PIN_DATA(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output \hideinitializer */
+#define PD4 GPIO_PIN_DATA(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output \hideinitializer */
+#define PD5 GPIO_PIN_DATA(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output \hideinitializer */
+#define PD6 GPIO_PIN_DATA(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output \hideinitializer */
+#define PD7 GPIO_PIN_DATA(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output \hideinitializer */
+#define PD8 GPIO_PIN_DATA(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output \hideinitializer */
+#define PD9 GPIO_PIN_DATA(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output \hideinitializer */
+#define PD10 GPIO_PIN_DATA(3, 10) /*!< Specify PD.10 Pin Data Input/Output \hideinitializer */
+#define PD11 GPIO_PIN_DATA(3, 11) /*!< Specify PD.11 Pin Data Input/Output \hideinitializer */
+#define PD12 GPIO_PIN_DATA(3, 12) /*!< Specify PD.12 Pin Data Input/Output \hideinitializer */
+#define PD13 GPIO_PIN_DATA(3, 13) /*!< Specify PD.13 Pin Data Input/Output \hideinitializer */
+#define PD14 GPIO_PIN_DATA(3, 14) /*!< Specify PD.14 Pin Data Input/Output \hideinitializer */
+#define PE0 GPIO_PIN_DATA(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output \hideinitializer */
+#define PE1 GPIO_PIN_DATA(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output \hideinitializer */
+#define PE2 GPIO_PIN_DATA(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output \hideinitializer */
+#define PE3 GPIO_PIN_DATA(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output \hideinitializer */
+#define PE4 GPIO_PIN_DATA(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output \hideinitializer */
+#define PE5 GPIO_PIN_DATA(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output \hideinitializer */
+#define PE6 GPIO_PIN_DATA(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output \hideinitializer */
+#define PE7 GPIO_PIN_DATA(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output \hideinitializer */
+#define PE8 GPIO_PIN_DATA(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output \hideinitializer */
+#define PE9 GPIO_PIN_DATA(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output \hideinitializer */
+#define PE10 GPIO_PIN_DATA(4, 10) /*!< Specify PE.10 Pin Data Input/Output \hideinitializer */
+#define PE11 GPIO_PIN_DATA(4, 11) /*!< Specify PE.11 Pin Data Input/Output \hideinitializer */
+#define PE12 GPIO_PIN_DATA(4, 12) /*!< Specify PE.12 Pin Data Input/Output \hideinitializer */
+#define PE13 GPIO_PIN_DATA(4, 13) /*!< Specify PE.13 Pin Data Input/Output \hideinitializer */
+#define PE14 GPIO_PIN_DATA(4, 14) /*!< Specify PE.14 Pin Data Input/Output \hideinitializer */
+#define PE15 GPIO_PIN_DATA(4, 15) /*!< Specify PE.15 Pin Data Input/Output \hideinitializer */
+#define PF0 GPIO_PIN_DATA(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output \hideinitializer */
+#define PF1 GPIO_PIN_DATA(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output \hideinitializer */
+#define PF2 GPIO_PIN_DATA(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output \hideinitializer */
+#define PF3 GPIO_PIN_DATA(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output \hideinitializer */
+#define PF4 GPIO_PIN_DATA(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output \hideinitializer */
+#define PF5 GPIO_PIN_DATA(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output \hideinitializer */
+#define PF6 GPIO_PIN_DATA(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output \hideinitializer */
+#define PF7 GPIO_PIN_DATA(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output \hideinitializer */
+#define PF8 GPIO_PIN_DATA(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output \hideinitializer */
+#define PF9 GPIO_PIN_DATA(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output \hideinitializer */
+#define PF10 GPIO_PIN_DATA(5, 10) /*!< Specify PF.10 Pin Data Input/Output \hideinitializer */
+#define PF11 GPIO_PIN_DATA(5, 11) /*!< Specify PF.11 Pin Data Input/Output \hideinitializer */
+#define PG0 GPIO_PIN_DATA(6, 0 ) /*!< Specify PG.0 Pin Data Input/Output \hideinitializer */
+#define PG1 GPIO_PIN_DATA(6, 1 ) /*!< Specify PG.1 Pin Data Input/Output \hideinitializer */
+#define PG2 GPIO_PIN_DATA(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output \hideinitializer */
+#define PG3 GPIO_PIN_DATA(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output \hideinitializer */
+#define PG4 GPIO_PIN_DATA(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output \hideinitializer */
+#define PG5 GPIO_PIN_DATA(6, 5 ) /*!< Specify PG.5 Pin Data Input/Output \hideinitializer */
+#define PG6 GPIO_PIN_DATA(6, 6 ) /*!< Specify PG.6 Pin Data Input/Output \hideinitializer */
+#define PG7 GPIO_PIN_DATA(6, 7 ) /*!< Specify PG.7 Pin Data Input/Output \hideinitializer */
+#define PG8 GPIO_PIN_DATA(6, 8 ) /*!< Specify PG.8 Pin Data Input/Output \hideinitializer */
+#define PG9 GPIO_PIN_DATA(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output \hideinitializer */
+#define PG10 GPIO_PIN_DATA(6, 10) /*!< Specify PG.10 Pin Data Input/Output \hideinitializer */
+#define PG11 GPIO_PIN_DATA(6, 11) /*!< Specify PG.11 Pin Data Input/Output \hideinitializer */
+#define PG12 GPIO_PIN_DATA(6, 12) /*!< Specify PG.12 Pin Data Input/Output \hideinitializer */
+#define PG13 GPIO_PIN_DATA(6, 13) /*!< Specify PG.13 Pin Data Input/Output \hideinitializer */
+#define PG14 GPIO_PIN_DATA(6, 14) /*!< Specify PG.14 Pin Data Input/Output \hideinitializer */
+#define PG15 GPIO_PIN_DATA(6, 15) /*!< Specify PG.15 Pin Data Input/Output \hideinitializer */
+#define PH0 GPIO_PIN_DATA(7, 0 ) /*!< Specify PH.0 Pin Data Input/Output \hideinitializer */
+#define PH1 GPIO_PIN_DATA(7, 1 ) /*!< Specify PH.1 Pin Data Input/Output \hideinitializer */
+#define PH2 GPIO_PIN_DATA(7, 2 ) /*!< Specify PH.2 Pin Data Input/Output \hideinitializer */
+#define PH3 GPIO_PIN_DATA(7, 3 ) /*!< Specify PH.3 Pin Data Input/Output \hideinitializer */
+#define PH4 GPIO_PIN_DATA(7, 4 ) /*!< Specify PH.4 Pin Data Input/Output \hideinitializer */
+#define PH5 GPIO_PIN_DATA(7, 5 ) /*!< Specify PH.5 Pin Data Input/Output \hideinitializer */
+#define PH6 GPIO_PIN_DATA(7, 6 ) /*!< Specify PH.6 Pin Data Input/Output \hideinitializer */
+#define PH7 GPIO_PIN_DATA(7, 7 ) /*!< Specify PH.7 Pin Data Input/Output \hideinitializer */
+#define PH8 GPIO_PIN_DATA(7, 8 ) /*!< Specify PH.8 Pin Data Input/Output \hideinitializer */
+#define PH9 GPIO_PIN_DATA(7, 9 ) /*!< Specify PH.9 Pin Data Input/Output \hideinitializer */
+#define PH10 GPIO_PIN_DATA(7, 10) /*!< Specify PH.10 Pin Data Input/Output \hideinitializer */
+#define PH11 GPIO_PIN_DATA(7, 11) /*!< Specify PH.11 Pin Data Input/Output \hideinitializer */
+
+
+/*@}*/ /* end of group GPIO_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
+ @{
+*/
+
+/**
+ * @brief Clear GPIO Pin Interrupt Flag
+ *
+ * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ * It could be BIT0 ~ BIT13 for PE GPIO port.
+ * It could be BIT0 ~ BIT11 for PG GPIO port.
+ *
+ * @return None
+ *
+ * @details Clear the interrupt status of specified GPIO pin.
+ * \hideinitializer
+ */
+#define GPIO_CLR_INT_FLAG(port, u32PinMask) ((port)->INTSRC = (u32PinMask))
+
+/**
+ * @brief Disable Pin De-bounce Function
+ *
+ * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ * It could be BIT0 ~ BIT13 for PE GPIO port.
+ * It could be BIT0 ~ BIT11 for PG GPIO port.
+ *
+ * @return None
+ *
+ * @details Disable the interrupt de-bounce function of specified GPIO pin.
+ * \hideinitializer
+ */
+#define GPIO_DISABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN &= ~(u32PinMask))
+
+/**
+ * @brief Enable Pin De-bounce Function
+ *
+ * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ * It could be BIT0 ~ BIT13 for PE GPIO port.
+ * It could be BIT0 ~ BIT11 for PG GPIO port.
+ * @return None
+ *
+ * @details Enable the interrupt de-bounce function of specified GPIO pin.
+ * \hideinitializer
+ */
+#define GPIO_ENABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN |= (u32PinMask))
+
+/**
+ * @brief Disable I/O Digital Input Path
+ *
+ * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ * It could be BIT0 ~ BIT13 for PE GPIO port.
+ * It could be BIT0 ~ BIT11 for PG GPIO port.
+ *
+ * @return None
+ *
+ * @details Disable I/O digital input path of specified GPIO pin.
+ * \hideinitializer
+ */
+#define GPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF |= ((u32PinMask)<<16))
+
+/**
+ * @brief Enable I/O Digital Input Path
+ *
+ * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ * It could be BIT0 ~ BIT13 for PE GPIO port.
+ * It could be BIT0 ~ BIT11 for PG GPIO port.
+ *
+ * @return None
+ *
+ * @details Enable I/O digital input path of specified GPIO pin.
+ * \hideinitializer
+ */
+#define GPIO_ENABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF &= ~((u32PinMask)<<16))
+
+/**
+ * @brief Disable I/O DOUT mask
+ *
+ * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ * It could be BIT0 ~ BIT13 for PE GPIO port.
+ * It could be BIT0 ~ BIT11 for PG GPIO port.
+ *
+ * @return None
+ *
+ * @details Disable I/O DOUT mask of specified GPIO pin.
+ * \hideinitializer
+ */
+#define GPIO_DISABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK &= ~(u32PinMask))
+
+/**
+ * @brief Enable I/O DOUT mask
+ *
+ * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ * It could be BIT0 ~ BIT13 for PE GPIO port.
+ * It could be BIT0 ~ BIT11 for PG GPIO port.
+ *
+ * @return None
+ *
+ * @details Enable I/O DOUT mask of specified GPIO pin.
+ * \hideinitializer
+ */
+#define GPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK |= (u32PinMask))
+
+/**
+ * @brief Get GPIO Pin Interrupt Flag
+ *
+ * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ * It could be BIT0 ~ BIT13 for PE GPIO port.
+ * It could be BIT0 ~ BIT11 for PG GPIO port.
+ *
+ * @retval 0 No interrupt at specified GPIO pin
+ * @retval 1 The specified GPIO pin generate an interrupt
+ *
+ * @details Get the interrupt status of specified GPIO pin.
+ * \hideinitializer
+ */
+#define GPIO_GET_INT_FLAG(port, u32PinMask) ((port)->INTSRC & (u32PinMask))
+
+/**
+ * @brief Set De-bounce Sampling Cycle Time
+ *
+ * @param[in] u32ClkSrc The de-bounce counter clock source. It could be GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC.
+ * @param[in] u32ClkSel The de-bounce sampling cycle selection. It could be
+ * - \ref GPIO_DBCTL_DBCLKSEL_1
+ * - \ref GPIO_DBCTL_DBCLKSEL_2
+ * - \ref GPIO_DBCTL_DBCLKSEL_4
+ * - \ref GPIO_DBCTL_DBCLKSEL_8
+ * - \ref GPIO_DBCTL_DBCLKSEL_16
+ * - \ref GPIO_DBCTL_DBCLKSEL_32
+ * - \ref GPIO_DBCTL_DBCLKSEL_64
+ * - \ref GPIO_DBCTL_DBCLKSEL_128
+ * - \ref GPIO_DBCTL_DBCLKSEL_256
+ * - \ref GPIO_DBCTL_DBCLKSEL_512
+ * - \ref GPIO_DBCTL_DBCLKSEL_1024
+ * - \ref GPIO_DBCTL_DBCLKSEL_2048
+ * - \ref GPIO_DBCTL_DBCLKSEL_4096
+ * - \ref GPIO_DBCTL_DBCLKSEL_8192
+ * - \ref GPIO_DBCTL_DBCLKSEL_16384
+ * - \ref GPIO_DBCTL_DBCLKSEL_32768
+ *
+ * @return None
+ *
+ * @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n
+ * Example: _GPIO_SET_DEBOUNCE_TIME(GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_4). \n
+ * It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n
+ * Then the target de-bounce sampling cycle time is (4)*(1/(10*1000)) s = 4*0.0001 s = 400 us,
+ * and system will sampling interrupt input once per 00 us.
+ * \hideinitializer
+ */
+#define GPIO_SET_DEBOUNCE_TIME(u32ClkSrc, u32ClkSel) (GPIO->DBCTL = (GPIO_DBCTL_ICLKON_Msk | (u32ClkSrc) | (u32ClkSel)))
+
+/**
+ * @brief Get GPIO Port IN Data
+ *
+* @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ *
+ * @return The specified port data
+ *
+ * @details Get the PIN register of specified GPIO port.
+ * \hideinitializer
+ */
+#define GPIO_GET_IN_DATA(port) ((port)->PIN)
+
+/**
+ * @brief Set GPIO Port OUT Data
+ *
+ * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32Data GPIO port data.
+ *
+ * @return None
+ *
+ * @details Set the Data into specified GPIO port.
+ * \hideinitializer
+ */
+#define GPIO_SET_OUT_DATA(port, u32Data) ((port)->DOUT = (u32Data))
+
+/**
+ * @brief Toggle Specified GPIO pin
+ *
+ * @param[in] u32Pin Pxy
+ *
+ * @return None
+ *
+ * @details Toggle the specified GPIO pint.
+ * \hideinitializer
+ */
+#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
+
+
+/**
+ * @brief Enable External GPIO interrupt
+ *
+ * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32Pin The pin of specified GPIO port.
+ * It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port.
+ * It could be 0 ~ 13 for PE GPIO port.
+ * It could be 0 ~ 11 for PG GPIO port.
+ * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
+ * GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW.
+ *
+ * @return None
+ *
+ * @details This function is used to enable specified GPIO pin interrupt.
+ * \hideinitializer
+ */
+#define GPIO_EnableEINT GPIO_EnableInt
+
+/**
+ * @brief Disable External GPIO interrupt
+ *
+ * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32Pin The pin of specified GPIO port.
+ * It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port.
+ * It could be 0 ~ 13 for PE GPIO port.
+ * It could be 0 ~ 11 for PG GPIO port.
+ *
+ * @return None
+ *
+ * @details This function is used to enable specified GPIO pin interrupt.
+ * \hideinitializer
+ */
+#define GPIO_DisableEINT GPIO_DisableInt
+
+
+void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
+void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs);
+void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin);
+void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
+void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
+
+
+/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group GPIO_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GPIO_H__ */
+
+/*** (C) COPYRIGHT 2013~2016 Nuvoton Technology Corp. ***/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/StdDriver/inc/m480_rtc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/StdDriver/inc/m480_rtc.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,355 @@
+/**************************************************************************//**
+ * @file rtc.h
+ * @version V3.00
+ * @brief M480 series RTC driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/
+#ifndef __RTC_H__
+#define __RTC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup RTC_Driver RTC Driver
+ @{
+*/
+
+/** @addtogroup RTC_EXPORTED_CONSTANTS RTC Exported Constants
+ @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* RTC Initial Keyword Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_INIT_KEY 0xA5EB1357UL /*!< RTC Initiation Key to make RTC leaving reset state \hideinitializer */
+#define RTC_WRITE_KEY 0x0000A965UL /*!< RTC Register Access Enable Key to enable RTC read/write accessible and kept 1024 RTC clock \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* RTC Time Attribute Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_CLOCK_12 0UL /*!< RTC as 12-hour time scale with AM and PM indication \hideinitializer */
+#define RTC_CLOCK_24 1UL /*!< RTC as 24-hour time scale \hideinitializer */
+#define RTC_AM 1UL /*!< RTC as AM indication \hideinitializer */
+#define RTC_PM 2UL /*!< RTC as PM indication \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* RTC Tick Period Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_TICK_1_SEC 0x0UL /*!< RTC time tick period is 1 second \hideinitializer */
+#define RTC_TICK_1_2_SEC 0x1UL /*!< RTC time tick period is 1/2 second \hideinitializer */
+#define RTC_TICK_1_4_SEC 0x2UL /*!< RTC time tick period is 1/4 second \hideinitializer */
+#define RTC_TICK_1_8_SEC 0x3UL /*!< RTC time tick period is 1/8 second \hideinitializer */
+#define RTC_TICK_1_16_SEC 0x4UL /*!< RTC time tick period is 1/16 second \hideinitializer */
+#define RTC_TICK_1_32_SEC 0x5UL /*!< RTC time tick period is 1/32 second \hideinitializer */
+#define RTC_TICK_1_64_SEC 0x6UL /*!< RTC time tick period is 1/64 second \hideinitializer */
+#define RTC_TICK_1_128_SEC 0x7UL /*!< RTC time tick period is 1/128 second \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* RTC Day of Week Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_SUNDAY 0x0UL /*!< Day of the Week is Sunday \hideinitializer */
+#define RTC_MONDAY 0x1UL /*!< Day of the Week is Monday \hideinitializer */
+#define RTC_TUESDAY 0x2UL /*!< Day of the Week is Tuesday \hideinitializer */
+#define RTC_WEDNESDAY 0x3UL /*!< Day of the Week is Wednesday \hideinitializer */
+#define RTC_THURSDAY 0x4UL /*!< Day of the Week is Thursday \hideinitializer */
+#define RTC_FRIDAY 0x5UL /*!< Day of the Week is Friday \hideinitializer */
+#define RTC_SATURDAY 0x6UL /*!< Day of the Week is Saturday \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* RTC Miscellaneous Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_WAIT_COUNT 0xFFFFFFFFUL /*!< Initial Time-out Value \hideinitializer */
+#define RTC_YEAR2000 2000UL /*!< RTC Reference for compute year data \hideinitializer */
+#define RTC_FCR_REFERENCE 32761UL /*!< RTC Reference for frequency compensation \hideinitializer */
+
+
+#define RTC_TAMPER0_SELECT (0x1ul << 0) /*!< Select Tamper 0 \hideinitializer */
+#define RTC_TAMPER1_SELECT (0x1ul << 1) /*!< Select Tamper 1 \hideinitializer */
+#define RTC_TAMPER2_SELECT (0x1ul << 2) /*!< Select Tamper 2 \hideinitializer */
+#define RTC_TAMPER3_SELECT (0x1ul << 3) /*!< Select Tamper 3 \hideinitializer */
+#define RTC_TAMPER4_SELECT (0x1ul << 4) /*!< Select Tamper 4 \hideinitializer */
+#define RTC_TAMPER5_SELECT (0x1ul << 5) /*!< Select Tamper 5 \hideinitializer */
+#define MAX_TAMPER_PIN_NUM 6ul /*!< Tamper Pin number \hideinitializer */
+
+#define RTC_TAMPER_HIGH_LEVEL_DETECT 1ul /*!< Tamper pin detect voltage level is high \hideinitializer */
+#define RTC_TAMPER_LOW_LEVEL_DETECT 0ul /*!< Tamper pin detect voltage level is low \hideinitializer */
+
+#define RTC_TAMPER_DEBOUNCE_ENABLE 1ul /*!< Enable RTC tamper pin de-bounce function \hideinitializer */
+#define RTC_TAMPER_DEBOUNCE_DISABLE 0ul /*!< Disable RTC tamper pin de-bounce function \hideinitializer */
+
+#define RTC_PAIR0_SELECT (0x1ul << 0) /*!< Select Pair 0 \hideinitializer */
+#define RTC_PAIR1_SELECT (0x1ul << 1) /*!< Select Pair 1 \hideinitializer */
+#define RTC_PAIR2_SELECT (0x1ul << 2) /*!< Select Pair 2 \hideinitializer */
+#define MAX_PAIR_NUM 3ul /*!< Pair number \hideinitializer */
+
+#define RTC_2POW10_CLK (0x0 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 RTC clock cycles \hideinitializer */
+#define RTC_2POW11_CLK (0x1 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 2 RTC clock cycles \hideinitializer */
+#define RTC_2POW12_CLK (0x2 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 4 RTC clock cycles \hideinitializer */
+#define RTC_2POW13_CLK (0x3 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 6 RTC clock cycles \hideinitializer */
+#define RTC_2POW14_CLK (0x4 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 8 RTC clock cycles \hideinitializer */
+#define RTC_2POW15_CLK (0x5 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 16 RTC clock cycles \hideinitializer */
+#define RTC_2POW16_CLK (0x6 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 32 RTC clock cycles \hideinitializer */
+#define RTC_2POW17_CLK (0x7 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 64 RTC clock cycles \hideinitializer */
+
+#define REF_RANDOM_PATTERN 0x0 /*!< The new reference pattern is generated by random number generator when the reference pattern run out \hideinitializer */
+#define REF_PREVIOUS_PATTERN 0x1 /*!< The new reference pattern is repeated previous random value when the reference pattern run out \hideinitializer */
+#define REF_SEED 0x3 /*!< The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out \hideinitializer */
+
+/*@}*/ /* end of group RTC_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup RTC_EXPORTED_STRUCTS RTC Exported Structs
+ @{
+*/
+/**
+ * @details RTC define Time Data Struct
+ */
+typedef struct {
+ uint32_t u32Year; /*!< Year value */
+ uint32_t u32Month; /*!< Month value */
+ uint32_t u32Day; /*!< Day value */
+ uint32_t u32DayOfWeek; /*!< Day of week value */
+ uint32_t u32Hour; /*!< Hour value */
+ uint32_t u32Minute; /*!< Minute value */
+ uint32_t u32Second; /*!< Second value */
+ uint32_t u32TimeScale; /*!< 12-Hour, 24-Hour */
+ uint32_t u32AmPm; /*!< Only Time Scale select 12-hr used */
+} S_RTC_TIME_DATA_T;
+
+/*@}*/ /* end of group RTC_EXPORTED_STRUCTS */
+
+
+/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions
+ @{
+*/
+
+/**
+ * @brief Indicate is Leap Year or not
+ *
+ * @param None
+ *
+ * @retval 0 This year is not a leap year
+ * @retval 1 This year is a leap year
+ *
+ * @details According to current date, return this year is leap year or not.
+ * \hideinitializer
+ */
+#define RTC_IS_LEAP_YEAR() (RTC->LEAPYEAR & RTC_LEAPYEAR_LEAPYEAR_Msk ? 1:0)
+
+/**
+ * @brief Clear RTC Alarm Interrupt Flag
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This macro is used to clear RTC alarm interrupt flag.
+ * \hideinitializer
+ */
+#define RTC_CLEAR_ALARM_INT_FLAG() (RTC->INTSTS = RTC_INTSTS_ALMIF_Msk)
+
+/**
+ * @brief Clear RTC Tick Interrupt Flag
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This macro is used to clear RTC tick interrupt flag.
+ * \hideinitializer
+ */
+#define RTC_CLEAR_TICK_INT_FLAG() (RTC->INTSTS = RTC_INTSTS_TICKIF_Msk)
+
+/**
+ * @brief Clear RTC Tamper Interrupt Flag
+ *
+ * @param u32TamperFlag Tamper interrupt flag. It consists of: \n
+ * - \ref RTC_INTSTS_TAMP0IF_Msk \n
+ * - \ref RTC_INTSTS_TAMP1IF_Msk \n
+ * - \ref RTC_INTSTS_TAMP2IF_Msk \n
+ * - \ref RTC_INTSTS_TAMP3IF_Msk \n
+ * - \ref RTC_INTSTS_TAMP4IF_Msk \n
+ * - \ref RTC_INTSTS_TAMP5IF_Msk
+ *
+ * @return None
+ *
+ * @details This macro is used to clear RTC snooper pin interrupt flag.
+ * \hideinitializer
+ */
+#define RTC_CLEAR_TAMPER_INT_FLAG(u32TamperFlag) (RTC->INTSTS = (u32TamperFlag))
+
+/**
+ * @brief Get RTC Alarm Interrupt Flag
+ *
+ * @param None
+ *
+ * @retval 0 RTC alarm interrupt did not occur
+ * @retval 1 RTC alarm interrupt occurred
+ *
+ * @details This macro indicates RTC alarm interrupt occurred or not.
+ * \hideinitializer
+ */
+#define RTC_GET_ALARM_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_ALMIF_Msk)? 1:0)
+
+/**
+ * @brief Get RTC Time Tick Interrupt Flag
+ *
+ * @param None
+ *
+ * @retval 0 RTC time tick interrupt did not occur
+ * @retval 1 RTC time tick interrupt occurred
+ *
+ * @details This macro indicates RTC time tick interrupt occurred or not.
+ * \hideinitializer
+ */
+#define RTC_GET_TICK_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_TICKIF_Msk)? 1:0)
+
+/**
+ * @brief Get RTC Tamper Interrupt Flag
+ *
+ * @param None
+ *
+ * @retval 0 RTC snooper pin interrupt did not occur
+ * @retval 1 RTC snooper pin interrupt occurred
+ *
+ * @details This macro indicates RTC snooper pin interrupt occurred or not.
+ * \hideinitializer
+ */
+#define RTC_GET_TAMPER_INT_FLAG() ((RTC->INTSTS & (0x3F00))? 1:0)
+
+/**
+ * @brief Get RTC TAMPER Interrupt Status
+ *
+ * @param None
+ *
+ * @retval RTC_INTSTS_TAMP0IF_Msk Tamper 0 interrupt flag is generated
+ * @retval RTC_INTSTS_TAMP1IF_Msk Tamper 1 interrupt flag is generated
+ * @retval RTC_INTSTS_TAMP2IF_Msk Tamper 2 interrupt flag is generated
+ * @retval RTC_INTSTS_TAMP3IF_Msk Tamper 3 interrupt flag is generated
+ * @retval RTC_INTSTS_TAMP4IF_Msk Tamper 4 interrupt flag is generated
+ * @retval RTC_INTSTS_TAMP5IF_Msk Tamper 5 interrupt flag is generated
+ *
+ * @details This macro indicates RTC snooper pin interrupt occurred or not.
+ * \hideinitializer
+ */
+#define RTC_GET_TAMPER_INT_STATUS() ((RTC->INTSTS & (0x3F00)))
+
+/**
+ * @brief Read Spare Register
+ *
+ * @param[in] u32RegNum The spare register number, 0~19.
+ *
+ * @return Spare register content
+ *
+ * @details Read the specify spare register content.
+ * @note The returned value is valid only when SPRRDY(SPRCTL[7] SPR Register Ready) bit is set. \n
+ * And its controlled by RTC Access Enable Register.
+ * \hideinitializer
+ */
+#define RTC_READ_SPARE_REGISTER(u32RegNum) (RTC->SPR[(u32RegNum)])
+
+/**
+ * @brief Write Spare Register
+ *
+ * @param[in] u32RegNum The spare register number, 0~19.
+ * @param[in] u32RegValue The spare register value.
+ *
+ * @return None
+ *
+ * @details Write specify data to spare register.
+ * @note This macro is effect only when SPRRDY(SPRCTL[7] SPR Register Ready) bit is set. \n
+ * And its controlled by RTC Access Enable Register(RTC_RWEN).
+ * \hideinitializer
+ */
+#define RTC_WRITE_SPARE_REGISTER(u32RegNum, u32RegValue) (RTC->SPR[(u32RegNum)] = (u32RegValue))
+
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+__STATIC_INLINE void RTC_WaitAccessEnable(void);
+
+/**
+ * @brief Wait RTC Access Enable
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function is used to enable the maximum RTC read/write accessible time.
+ */
+__STATIC_INLINE void RTC_WaitAccessEnable(void)
+{
+ while ((RTC->RWEN & RTC_RWEN_RTCBUSY_Msk) == RTC_RWEN_RTCBUSY_Msk) {
+ }
+
+ /* To wait RWENF bit is cleared and enable RWENF bit (Access Enable bit) again */
+ RTC->RWEN = RTC_WRITE_KEY;
+
+ /* To wait RWENF bit is set and user can access the protected-register of RTC from now on */
+ while ((RTC->RWEN & RTC_RWEN_RWENF_Msk) == (uint32_t)0x0) {
+ }
+}
+
+void RTC_Open(S_RTC_TIME_DATA_T *sPt);
+void RTC_Close(void);
+void RTC_32KCalibration(int32_t i32FrequencyX10000);
+void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek);
+void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
+void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day);
+void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
+uint32_t RTC_GetDayOfWeek(void);
+void RTC_SetTickPeriod(uint32_t u32TickSelection);
+void RTC_EnableInt(uint32_t u32IntFlagMask);
+void RTC_DisableInt(uint32_t u32IntFlagMask);
+void RTC_EnableSpareAccess(void);
+void RTC_DisableSpareRegister(void);
+void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn);
+void RTC_StaticTamperDisable(uint32_t u32TamperSelect);
+void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source);
+void RTC_DynamicTamperDisable(uint32_t u32PairSel);
+void RTC_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed);
+
+/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group RTC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __RTC_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/StdDriver/inc/m480_sys.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/StdDriver/inc/m480_sys.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1520 @@
+/**************************************************************************//**
+ * @file SYS.h
+ * @version V3.0
+ * @brief M480 Series SYS Driver Header File
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#ifndef __SYS_H__
+#define __SYS_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup SYS_Driver SYS Driver
+ @{
+*/
+
+/** @addtogroup SYS_EXPORTED_CONSTANTS SYS Exported Constants
+ @{
+*/
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Module Reset Control Resister constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PDMA_RST ((0UL<<24) | SYS_IPRST0_PDMARST_Pos) /*!< Reset PDMA \hideinitializer*/
+#define EBI_RST ((0UL<<24) | SYS_IPRST0_EBIRST_Pos) /*!< Reset EBI \hideinitializer*/
+#define EMAC_RST ((0UL<<24) | SYS_IPRST0_EMACRST_Pos) /*!< Reset EMAC \hideinitializer */
+#define SDH0_RST ((0UL<<24) | SYS_IPRST0_SDH0RST_Pos) /*!< Reset SDH0 \hideinitializer */
+#define CRC_RST ((0UL<<24) | SYS_IPRST0_CRCRST_Pos) /*!< Reset CRC \hideinitializer */
+#define HSUSBD_RST ((0UL<<24) | SYS_IPRST0_HSUSBDRST_Pos) /*!< Reset HSUSBD \hideinitializer */
+#define CRPT_RST ((0UL<<24) | SYS_IPRST0_CRPTRST_Pos) /*!< Reset CRPT \hideinitializer */
+#define SPIM_RST ((0UL<<24) | SYS_IPRST0_SPIMRST_Pos) /*!< Reset SPIM \hideinitializer */
+#define USBH_RST ((0UL<<24) | SYS_IPRST0_USBHRST_Pos) /*!< Reset USBH \hideinitializer */
+#define SDH1_RST ((0UL<<24) | SYS_IPRST0_SDH1RST_Pos) /*!< Reset SDH1 \hideinitializer */
+
+#define GPIO_RST ((4UL<<24) | SYS_IPRST1_GPIORST_Pos) /*!< Reset GPIO \hideinitializer */
+#define TMR0_RST ((4UL<<24) | SYS_IPRST1_TMR0RST_Pos) /*!< Reset TMR0 \hideinitializer */
+#define TMR1_RST ((4UL<<24) | SYS_IPRST1_TMR1RST_Pos) /*!< Reset TMR1 \hideinitializer */
+#define TMR2_RST ((4UL<<24) | SYS_IPRST1_TMR2RST_Pos) /*!< Reset TMR2 \hideinitializer */
+#define TMR3_RST ((4UL<<24) | SYS_IPRST1_TMR3RST_Pos) /*!< Reset TMR3 \hideinitializer */
+#define ACMP01_RST ((4UL<<24) | SYS_IPRST1_ACMP01RST_Pos) /*!< Reset ACMP01 \hideinitializer */
+#define I2C0_RST ((4UL<<24) | SYS_IPRST1_I2C0RST_Pos) /*!< Reset I2C0 \hideinitializer */
+#define I2C1_RST ((4UL<<24) | SYS_IPRST1_I2C1RST_Pos) /*!< Reset I2C1 \hideinitializer */
+#define I2C2_RST ((4UL<<24) | SYS_IPRST1_I2C2RST_Pos) /*!< Reset I2C2 \hideinitializer */
+#define QSPI0_RST ((4UL<<24) | SYS_IPRST1_QSPI0RST_Pos) /*!< Reset QSPI0 \hideinitializer */
+#define SPI0_RST ((4UL<<24) | SYS_IPRST1_SPI0RST_Pos) /*!< Reset SPI0 \hideinitializer */
+#define SPI1_RST ((4UL<<24) | SYS_IPRST1_SPI1RST_Pos) /*!< Reset SPI1 \hideinitializer */
+#define SPI2_RST ((4UL<<24) | SYS_IPRST1_SPI2RST_Pos) /*!< Reset SPI2 \hideinitializer */
+#define UART0_RST ((4UL<<24) | SYS_IPRST1_UART0RST_Pos) /*!< Reset UART0 \hideinitializer */
+#define UART1_RST ((4UL<<24) | SYS_IPRST1_UART1RST_Pos) /*!< Reset UART1 \hideinitializer */
+#define UART2_RST ((4UL<<24) | SYS_IPRST1_UART2RST_Pos) /*!< Reset UART2 \hideinitializer */
+#define UART3_RST ((4UL<<24) | SYS_IPRST1_UART3RST_Pos) /*!< Reset UART3 \hideinitializer */
+#define UART4_RST ((4UL<<24) | SYS_IPRST1_UART4RST_Pos) /*!< Reset UART4 \hideinitializer */
+#define UART5_RST ((4UL<<24) | SYS_IPRST1_UART5RST_Pos) /*!< Reset UART5 \hideinitializer */
+#define CAN0_RST ((4UL<<24) | SYS_IPRST1_CAN0RST_Pos) /*!< Reset CAN0 \hideinitializer */
+#define CAN1_RST ((4UL<<24) | SYS_IPRST1_CAN1RST_Pos) /*!< Reset CAN1 \hideinitializer */
+#define USBD_RST ((4UL<<24) | SYS_IPRST1_USBDRST_Pos) /*!< Reset USBD \hideinitializer */
+#define EADC_RST ((4UL<<24) | SYS_IPRST1_EADCRST_Pos) /*!< Reset EADC \hideinitializer */
+#define I2S0_RST ((4UL<<24) | SYS_IPRST1_I2S0RST_Pos) /*!< Reset I2S0 \hideinitializer */
+
+#define SC0_RST ((8UL<<24) | SYS_IPRST2_SC0RST_Pos) /*!< Reset SC0 \hideinitializer */
+#define SC1_RST ((8UL<<24) | SYS_IPRST2_SC1RST_Pos) /*!< Reset SC1 \hideinitializer */
+#define SC2_RST ((8UL<<24) | SYS_IPRST2_SC2RST_Pos) /*!< Reset SC2 \hideinitializer */
+#define SPI3_RST ((8UL<<24) | SYS_IPRST2_SPI3RST_Pos) /*!< Reset SPI3 \hideinitializer */
+#define USCI0_RST ((8UL<<24) | SYS_IPRST2_USCI0RST_Pos) /*!< Reset USCI0 \hideinitializer */
+#define USCI1_RST ((8UL<<24) | SYS_IPRST2_USCI1RST_Pos) /*!< Reset USCI1 \hideinitializer */
+#define DAC_RST ((8UL<<24) | SYS_IPRST2_DACRST_Pos) /*!< Reset DAC \hideinitializer */
+#define EPWM0_RST ((8UL<<24) | SYS_IPRST2_EPWM0RST_Pos) /*!< Reset EPWM0 \hideinitializer */
+#define EPWM1_RST ((8UL<<24) | SYS_IPRST2_EPWM1RST_Pos) /*!< Reset EPWM1 \hideinitializer */
+#define BPWM0_RST ((8UL<<24) | SYS_IPRST2_BPWM0RST_Pos) /*!< Reset BPWM0 \hideinitializer */
+#define BPWM1_RST ((8UL<<24) | SYS_IPRST2_BPWM1RST_Pos) /*!< Reset BPWM1 \hideinitializer */
+#define QEI0_RST ((8UL<<24) | SYS_IPRST2_QEI0RST_Pos) /*!< Reset QEI0 \hideinitializer */
+#define QEI1_RST ((8UL<<24) | SYS_IPRST2_QEI1RST_Pos) /*!< Reset QEI1 \hideinitializer */
+#define ECAP0_RST ((8UL<<24) | SYS_IPRST2_ECAP0RST_Pos) /*!< Reset ECAP0 \hideinitializer */
+#define ECAP1_RST ((8UL<<24) | SYS_IPRST2_ECAP1RST_Pos) /*!< Reset ECAP1 \hideinitializer */
+#define OPA_RST ((8UL<<24) | SYS_IPRST2_OPARST_Pos) /*!< Reset OPA \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Brown Out Detector Threshold Voltage Selection constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define SYS_BODCTL_BOD_RST_EN (1UL << SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Reset Enable \hideinitializer */
+#define SYS_BODCTL_BOD_INTERRUPT_EN (0UL << SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Interrupt Enable \hideinitializer */
+#define SYS_BODCTL_BODVL_3_0V (7UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 3.0V \hideinitializer */
+#define SYS_BODCTL_BODVL_2_8V (6UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.8V \hideinitializer */
+#define SYS_BODCTL_BODVL_2_6V (5UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.6V \hideinitializer */
+#define SYS_BODCTL_BODVL_2_4V (4UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.4V \hideinitializer */
+#define SYS_BODCTL_BODVL_2_2V (3UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.2V \hideinitializer */
+#define SYS_BODCTL_BODVL_2_0V (2UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.0V \hideinitializer */
+#define SYS_BODCTL_BODVL_1_8V (1UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 1.8V \hideinitializer */
+#define SYS_BODCTL_BODVL_1_6V (0UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 1.6V \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* VREFCTL constant definitions. (Write-Protection Register) */
+/*---------------------------------------------------------------------------------------------------------*/
+#define SYS_VREFCTL_VREF_PIN (0x0UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = Vref pin \hideinitializer */
+#define SYS_VREFCTL_VREF_1_6V (0x3UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 1.6V \hideinitializer */
+#define SYS_VREFCTL_VREF_2_0V (0x7UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 2.0V \hideinitializer */
+#define SYS_VREFCTL_VREF_2_5V (0xBUL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 2.5V \hideinitializer */
+#define SYS_VREFCTL_VREF_3_0V (0xFUL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 3.0V \hideinitializer */
+#define SYS_VREFCTL_VREF_AVDD (0x10UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = AVDD \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* USBPHY constant definitions. (Write-Protection Register) */
+/*---------------------------------------------------------------------------------------------------------*/
+#define SYS_USBPHY_USBROLE_STD_USBD (0x0UL << SYS_USBPHY_USBROLE_Pos) /*!< Standard USB device \hideinitializer */
+#define SYS_USBPHY_USBROLE_STD_USBH (0x1UL << SYS_USBPHY_USBROLE_Pos) /*!< Standard USB host \hideinitializer */
+#define SYS_USBPHY_USBROLE_ID_DEPH (0x2UL << SYS_USBPHY_USBROLE_Pos) /*!< ID dependent device \hideinitializer */
+#define SYS_USBPHY_USBROLE_ON_THE_GO (0x3UL << SYS_USBPHY_USBROLE_Pos) /*!< On-The-Go device \hideinitializer */
+#define SYS_USBPHY_HSUSBROLE_STD_USBD (0x0UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< Standard HSUSB device \hideinitializer */
+#define SYS_USBPHY_HSUSBROLE_STD_USBH (0x1UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< Standard HSUSB host \hideinitializer */
+#define SYS_USBPHY_HSUSBROLE_ID_DEPH (0x2UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< ID dependent device \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* PLCTL constant definitions. (Write-Protection Register) */
+/*---------------------------------------------------------------------------------------------------------*/
+#define SYS_PLCTL_PLSEL_PL0 (0x0UL<<SYS_PLCTL_PLSEL_Pos) /*!< Set power level to power level 0 */
+#define SYS_PLCTL_PLSEL_PL1 (0x1UL<<SYS_PLCTL_PLSEL_Pos) /*!< Set power level to power level 1 */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Multi-Function constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+/* How to use below #define?
+Example 1: If user want to set PA.0 as SC0_CLK in initial function,
+ user can issue following command to achieve it.
+
+ SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0_MFP_SC0_CLK ;
+
+*/
+/********************* Bit definition of GPA_MFPL register **********************/
+#define SYS_GPA_MFPL_PA0MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA0MFP_SPIM_MOSI (0x02UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< 1st SPIM MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA0MFP_QSPI0_MOSI0 (0x03UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< 1st QSPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA0MFP_SPI0_MOSI (0x04UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< 1st SPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA0MFP_SD1_DAT0 (0x05UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< SD/SDIO 1 data line bit 0. \hideinitializer */
+#define SYS_GPA_MFPL_PA0MFP_SC0_CLK (0x06UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< SmartCard0 clock pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA0MFP_UART0_RXD (0x07UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
+#define SYS_GPA_MFPL_PA0MFP_UART1_nRTS (0x08UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< Request to Send output pin for UART1. \hideinitializer */
+#define SYS_GPA_MFPL_PA0MFP_I2C2_SDA (0x09UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA0MFP_BPWM0_CH0 (0x0CUL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< BPWM0 channel0 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA0MFP_EPWM0_CH5 (0x0DUL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< EPWM0 channel5 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA0MFP_DAC0_ST (0x0FUL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< DAC0 external trigger input. \hideinitializer */
+#define SYS_GPA_MFPL_PA1MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA1MFP_SPIM_MISO (0x02UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< 1st SPIM MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA1MFP_QSPI0_MISO0 (0x03UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< 1st QSPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA1MFP_SPI0_MISO (0x04UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< 1st SPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA1MFP_SD1_DAT1 (0x05UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< SD/SDIO 1 data line bit 1. \hideinitializer */
+#define SYS_GPA_MFPL_PA1MFP_SC0_DAT (0x06UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< SmartCard0 data pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA1MFP_UART0_TXD (0x07UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
+#define SYS_GPA_MFPL_PA1MFP_UART1_nCTS (0x08UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< Clear to Send input pin for UART1. \hideinitializer */
+#define SYS_GPA_MFPL_PA1MFP_I2C2_SCL (0x09UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA1MFP_BPWM0_CH1 (0x0CUL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< BPWM0 channel1 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA1MFP_EPWM0_CH4 (0x0DUL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< EPWM0 channel4 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA1MFP_DAC1_ST (0x0FUL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< DAC1 external trigger input. \hideinitializer */
+#define SYS_GPA_MFPL_PA2MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA2MFP_SPIM_CLK (0x02UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< SPIM serial clock pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA2MFP_QSPI0_CLK (0x03UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< QSPI0 serial clock pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA2MFP_SPI0_CLK (0x04UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< SPI0 serial clock pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA2MFP_SD1_DAT2 (0x05UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< SD/SDIO 1 data line bit 2. \hideinitializer */
+#define SYS_GPA_MFPL_PA2MFP_SC0_RST (0x06UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< SmartCard0 reset pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA2MFP_UART4_RXD (0x07UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */
+#define SYS_GPA_MFPL_PA2MFP_UART1_RXD (0x08UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */
+#define SYS_GPA_MFPL_PA2MFP_I2C1_SDA (0x09UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA2MFP_BPWM0_CH2 (0x0CUL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< BPWM0 channel2 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA2MFP_EPWM0_CH3 (0x0DUL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< EPWM0 channel3 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_SPIM_SS (0x02UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< 1st SPIM slave select pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_QSPI0_SS (0x03UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< 1st QSPI0 slave select pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_SPI0_SS (0x04UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< 1st SPI0 slave select pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_SD1_DAT3 (0x05UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< SD/SDIO 1 data line bit 3. \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_SC0_PWR (0x06UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< SmartCard0 power pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_UART4_TXD (0x07UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_UART1_TXD (0x08UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_I2C1_SCL (0x09UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_BPWM0_CH3 (0x0CUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< BPWM0 channel3 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_EPWM0_CH2 (0x0DUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< EPWM0 channel2 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_QEI0_B (0x0EUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< Quadrature encoder phase B input of QEI Unit 0. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_SPIM_D3 (0x02UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< SPIM data 3 pin for Quad Mode I/O. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_QSPI0_MOSI1 (0x03UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< 2nd QSPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_SPI0_I2SMCLK (0x04UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< SPI0 I2S master clock output pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_SD1_CLK (0x05UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< SD/SDIO 1 clock. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_SC0_nCD (0x06UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< SmartCard0 card detect pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_UART0_nRTS (0x07UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< Request to Send output pin for UART0. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_UART5_RXD (0x08UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< Data receiver input pin for UART5. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_I2C0_SDA (0x09UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_CAN0_RXD (0x0AUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_BPWM0_CH4 (0x0CUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< BPWM0 channel4 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_EPWM0_CH1 (0x0DUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< EPWM0 channel1 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA4MFP_QEI0_A (0x0EUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< Quadrature encoder phase A input of QEI Unit 0. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_SPIM_D2 (0x02UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< SPIM data 2 pin for Quad Mode I/O. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_QSPI0_MISO1 (0x03UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< 2nd QSPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_SPI1_I2SMCLK (0x04UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< SPI1 I2S master clock output pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_SD1_CMD (0x05UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< SD/SDIO 1 command/response. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_SC2_nCD (0x06UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< SmartCard2 card detect pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_UART0_nCTS (0x07UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< Clear to Send input pin for UART0. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_UART5_TXD (0x08UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< Data transmitter output pin for UART5. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_I2C0_SCL (0x09UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_CAN0_TXD (0x0AUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_BPWM0_CH5 (0x0CUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< BPWM0 channel5 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_EPWM0_CH0 (0x0DUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< EPWM0 channel0 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_QEI0_INDEX (0x0EUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< Quadrature encoder index input of QEI Unit 0. \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_EBI_AD6 (0x02UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< EBI address/data bus bit6. \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_EMAC_RMII_RXERR (0x03UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< RMII Receive Data error. \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_SPI1_SS (0x04UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< 1st SPI1 slave select pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_SD1_nCD (0x05UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< SD/SDIO 1 card detect \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_SC2_CLK (0x06UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< SmartCard2 clock pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_UART0_RXD (0x07UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_I2C1_SDA (0x08UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_EPWM1_CH5 (0x0BUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< EPWM1 channel5 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_BPWM1_CH3 (0x0CUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< BPWM1 channel3 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_ACMP1_WLAT (0x0DUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< Analog comparator1 window latch input pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_TM3 (0x0EUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< Timer3 event counter input / toggle output \hideinitializer */
+#define SYS_GPA_MFPL_PA6MFP_INT0 (0x0FUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< External interrupt0 input pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA7MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA7MFP_EBI_AD7 (0x02UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< EBI address/data bus bit7. \hideinitializer */
+#define SYS_GPA_MFPL_PA7MFP_EMAC_RMII_CRSDV (0x03UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< MII Receive Data Valid / RMII CRS_DV input. \hideinitializer */
+#define SYS_GPA_MFPL_PA7MFP_SPI1_CLK (0x04UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< SPI1 serial clock pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA7MFP_SC2_DAT (0x06UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< SmartCard2 data pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA7MFP_UART0_TXD (0x07UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
+#define SYS_GPA_MFPL_PA7MFP_I2C1_SCL (0x08UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA7MFP_EPWM1_CH4 (0x0BUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< EPWM1 channel4 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA7MFP_BPWM1_CH2 (0x0CUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< BPWM1 channel2 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPL_PA7MFP_ACMP0_WLAT (0x0DUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< Analog comparator0 window latch input pin. \hideinitializer */
+#define SYS_GPA_MFPL_PA7MFP_TM2 (0x0EUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< Timer2 event counter input / toggle output \hideinitializer */
+#define SYS_GPA_MFPL_PA7MFP_INT1 (0x0FUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< External interrupt1 input pin. \hideinitializer */
+/********************* Bit definition of GPA_MFPH register **********************/
+#define SYS_GPA_MFPH_PA8MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA8MFP_OPA1_P (0x01UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< Operational amplifier positive input pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA8MFP_EBI_ALE (0x02UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< EBI address latch enable output pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA8MFP_SC2_CLK (0x03UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< SmartCard2 clock pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA8MFP_SPI2_MOSI (0x04UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< 1st SPI2 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA8MFP_SD1_DAT0 (0x05UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< SD/SDIO 1 data line bit 0. \hideinitializer */
+#define SYS_GPA_MFPH_PA8MFP_USCI0_CTL1 (0x06UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< USCI0 control1 pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA8MFP_UART1_RXD (0x07UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */
+#define SYS_GPA_MFPH_PA8MFP_BPWM0_CH3 (0x09UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< BPWM0 channel3 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPH_PA8MFP_QEI1_B (0x0AUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< Quadrature encoder phase B input of QEI Unit 1. \hideinitializer */
+#define SYS_GPA_MFPH_PA8MFP_ECAP0_IC2 (0x0BUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< Input 0 of enhanced capture unit 2. \hideinitializer */
+#define SYS_GPA_MFPH_PA8MFP_TM3_EXT (0x0DUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< Timer3 event counter input / toggle output \hideinitializer */
+#define SYS_GPA_MFPH_PA8MFP_INT4 (0x0FUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< External interrupt4 input pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_OPA1_N (0x01UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< Operational amplifier negative input pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_EBI_MCLK (0x02UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< EBI external clock output pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_SC2_DAT (0x03UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< SmartCard2 data pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_SPI2_MISO (0x04UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< 1st SPI2 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_SD1_DAT1 (0x05UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< SD/SDIO 1 data line bit 1. \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_USCI0_DAT1 (0x06UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< USCI0 data1 pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_UART1_TXD (0x07UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_BPWM0_CH2 (0x09UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< BPWM0 channel2 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_QEI1_A (0x0AUL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< Quadrature encoder phase A input of QEI Unit 1. \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_ECAP0_IC1 (0x0BUL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< Input 1 of enhanced capture unit 0. \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_TM2_EXT (0x0DUL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< Timer2 event counter input / toggle output \hideinitializer */
+#define SYS_GPA_MFPH_PA9MFP_SWDH_DAT (0x0FUL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< SWD Host interface input/output bus bit. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_ACMP1_P0 (0x01UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Analog comparator1 positive input pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_OPA1_O (0x01UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Operational amplifier output pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_EBI_nWR (0x02UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< EBI write enable output pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_SC2_RST (0x03UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< SmartCard2 reset pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_SPI2_CLK (0x04UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< SPI2 serial clock pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_SD1_DAT2 (0x05UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< SD/SDIO 1 data line bit 2. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_USCI0_DAT0 (0x06UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< USCI0 data0 pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_I2C2_SDA (0x07UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_BPWM0_CH1 (0x09UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< BPWM0 channel1 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_QEI1_INDEX (0x0AUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Quadrature encoder index input of QEI Unit 1. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_ECAP0_IC0 (0x0BUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Input 0 of enhanced capture unit 0. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_TM1_EXT (0x0DUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Timer1 event counter input / toggle output \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_DAC0_ST (0x0EUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< DAC0 external trigger input. \hideinitializer */
+#define SYS_GPA_MFPH_PA10MFP_SWDH_CLK (0x0FUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< SWD Host interface clock output pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA11MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA11MFP_ACMP0_P0 (0x01UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< Analog comparator0 positive input pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA11MFP_EBI_nRD (0x02UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< EBI read enable output pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA11MFP_SC2_PWR (0x03UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< SmartCard2 power pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA11MFP_SPI2_SS (0x04UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< 1st SPI2 slave select pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA11MFP_SD1_DAT3 (0x05UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< SD/SDIO 1 data line bit 3. \hideinitializer */
+#define SYS_GPA_MFPH_PA11MFP_USCI0_CLK (0x06UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< USCI0 clock pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA11MFP_I2C2_SCL (0x07UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA11MFP_BPWM0_CH0 (0x09UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< BPWM0 channel0 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPH_PA11MFP_EPWM0_SYNC_OUT (0x0AUL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< EPWM0 counter synchronous trigger output pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA11MFP_TM0_EXT (0x0DUL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< Timer0 event counter input / toggle output \hideinitializer */
+#define SYS_GPA_MFPH_PA11MFP_DAC1_ST (0x0EUL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< DAC1 external trigger input. \hideinitializer */
+#define SYS_GPA_MFPH_PA12MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA12MFP_I2S0_BCLK (0x02UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< I2S0 bit clock pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA12MFP_UART4_TXD (0x03UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */
+#define SYS_GPA_MFPH_PA12MFP_I2C1_SCL (0x04UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA12MFP_SPI2_SS (0x05UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< 1st SPI2 slave select pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA12MFP_CAN0_TXD (0x06UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */
+#define SYS_GPA_MFPH_PA12MFP_SC2_PWR (0x07UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< SmartCard2 power pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA12MFP_BPWM1_CH2 (0x0BUL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< BPWM1 channel2 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPH_PA12MFP_QEI1_INDEX (0x0CUL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< Quadrature encoder index input of QEI Unit 1. \hideinitializer */
+#define SYS_GPA_MFPH_PA12MFP_USB_VBUS (0x0EUL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< Power supply from USB Full speed host or HUB. \hideinitializer */
+#define SYS_GPA_MFPH_PA13MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA13MFP_I2S0_MCLK (0x02UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< I2S0 master clock output pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA13MFP_UART4_RXD (0x03UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */
+#define SYS_GPA_MFPH_PA13MFP_I2C1_SDA (0x04UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA13MFP_SPI2_CLK (0x05UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< SPI2 serial clock pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA13MFP_CAN0_RXD (0x06UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */
+#define SYS_GPA_MFPH_PA13MFP_SC2_RST (0x07UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< SmartCard2 reset pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA13MFP_BPWM1_CH3 (0x0BUL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< BPWM1 channel3 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPH_PA13MFP_QEI1_A (0x0CUL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< Quadrature encoder phase A input of QEI Unit 1. \hideinitializer */
+#define SYS_GPA_MFPH_PA13MFP_USB_D_N (0x0EUL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< USB Full speed differential signal D-. \hideinitializer */
+#define SYS_GPA_MFPH_PA14MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA14MFP_I2S0_DI (0x02UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< I2S0 data input. \hideinitializer */
+#define SYS_GPA_MFPH_PA14MFP_UART0_TXD (0x03UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
+#define SYS_GPA_MFPH_PA14MFP_SPI2_MISO (0x05UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< 1st SPI2 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA14MFP_I2C2_SCL (0x06UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA14MFP_SC2_DAT (0x07UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< SmartCard2 data pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA14MFP_BPWM1_CH4 (0x0BUL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< BPWM1 channel4 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPH_PA14MFP_QEI1_B (0x0CUL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< Quadrature encoder phase B input of QEI Unit 1. \hideinitializer */
+#define SYS_GPA_MFPH_PA14MFP_USB_D_P (0x0EUL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< USB Full speed differential signal D+. \hideinitializer */
+#define SYS_GPA_MFPH_PA15MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA15MFP_I2S0_DO (0x02UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< I2S0 data output. \hideinitializer */
+#define SYS_GPA_MFPH_PA15MFP_UART0_RXD (0x03UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
+#define SYS_GPA_MFPH_PA15MFP_SPI2_MOSI (0x05UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< 1st SPI2 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA15MFP_I2C2_SDA (0x06UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA15MFP_SC2_CLK (0x07UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< SmartCard2 clock pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA15MFP_BPWM1_CH5 (0x0BUL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< BPWM1 channel5 output/capture input. \hideinitializer */
+#define SYS_GPA_MFPH_PA15MFP_EPWM0_SYNC_IN (0x0CUL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< EPWM0 counter synchronous trigger input pin. \hideinitializer */
+#define SYS_GPA_MFPH_PA15MFP_USB_OTG_ID (0x0EUL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< USB Full speed identification. \hideinitializer */
+/********************* Bit definition of GPB_MFPL register **********************/
+#define SYS_GPB_MFPL_PB0MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB0MFP_EADC0_CH0 (0x01UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< EADC0 channel0 analog input. \hideinitializer */
+#define SYS_GPB_MFPL_PB0MFP_OPA0_P (0x01UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< Operational amplifier positive input pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB0MFP_EBI_ADR9 (0x02UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPB_MFPL_PB0MFP_SD0_CMD (0x03UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< SD/SDIO 0 command/response. \hideinitializer */
+#define SYS_GPB_MFPL_PB0MFP_UART2_RXD (0x07UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */
+#define SYS_GPB_MFPL_PB0MFP_SPI0_I2SMCLK (0x08UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< SPI0 I2S master clock output pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB0MFP_I2C1_SDA (0x09UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB0MFP_EPWM0_CH5 (0x0BUL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< EPWM0 channel5 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPL_PB0MFP_EPWM1_CH5 (0x0CUL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< EPWM1 channel5 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPL_PB0MFP_EPWM0_BRAKE1 (0x0DUL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< Brake input pin 1 of EPWM0. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_EADC0_CH1 (0x01UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_OPA0_N (0x01UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< Operational amplifier negative input pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_EBI_ADR8 (0x02UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_SD0_CLK (0x03UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< SD/SDIO 0 clock. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_EMAC_RMII_RXERR (0x04UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< RMII Receive Data error. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_SPI1_I2SMCLK (0x05UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< SPI1 I2S master clock output pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_SPI3_I2SMCLK (0x06UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< SPI3 I2S master clock output pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_UART2_TXD (0x07UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_USCI1_CLK (0x08UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< USCI1 clock pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_I2C1_SCL (0x09UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_I2S0_LRCK (0x0AUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< I2S0 left right channel clock. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_EPWM0_CH4 (0x0BUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< EPWM0 channel4 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_EPWM1_CH4 (0x0CUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< EPWM1 channel4 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPL_PB1MFP_EPWM0_BRAKE0 (0x0DUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< Brake input pin 0 of EPWM0. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_ACMP0_P1 (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< Analog comparator0 positive input pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_EADC0_CH2 (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< EADC0 channel2 analog input. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_OPA0_O (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< Operational amplifier output pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_EBI_ADR3 (0x02UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_SD0_DAT0 (0x03UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< SD/SDIO 0 data line bit 0. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_EMAC_RMII_CRSDV (0x04UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< MII Receive Data Valid / RMII CRS_DV input. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_SPI1_SS (0x05UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< 1st SPI1 slave select pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_UART1_RXD (0x06UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_UART5_nCTS (0x07UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< Clear to Send input pin for UART5. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_USCI1_DAT0 (0x08UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< USCI1 data0 pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_SC0_PWR (0x09UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< SmartCard0 power pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_I2S0_DO (0x0AUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< I2S0 data output. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_EPWM0_CH3 (0x0BUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< EPWM0 channel3 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_TM3 (0x0EUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< Timer3 event counter input / toggle output \hideinitializer */
+#define SYS_GPB_MFPL_PB2MFP_INT3 (0x0FUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< External interrupt3 input pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_ACMP0_N (0x01UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< Analog comparator0 negative input pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_EADC0_CH3 (0x01UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< EADC0 channel3 analog input. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_EBI_ADR2 (0x02UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_SD0_DAT1 (0x03UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< SD/SDIO 0 data line bit 1. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_EMAC_RMII_RXD1 (0x04UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< RMII Receive Data bus bit 1. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_SPI1_CLK (0x05UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< SPI1 serial clock pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_UART1_TXD (0x06UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_UART5_nRTS (0x07UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< Request to Send output pin for UART5. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_USCI1_DAT1 (0x08UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< USCI1 data1 pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_SC0_RST (0x09UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< SmartCard0 reset pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_I2S0_DI (0x0AUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< I2S0 data input. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_EPWM0_CH2 (0x0BUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< EPWM0 channel2 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_TM2 (0x0EUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< Timer2 event counter input / toggle output \hideinitializer */
+#define SYS_GPB_MFPL_PB3MFP_INT2 (0x0FUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< External interrupt2 input pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_ACMP1_P1 (0x01UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< Analog comparator1 positive input pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_EADC0_CH4 (0x01UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< EADC0 channel4 analog input. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_EBI_ADR1 (0x02UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_SD0_DAT2 (0x03UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< SD/SDIO 0 data line bit 2. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_EMAC_RMII_RXD0 (0x04UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< RMII Receive Data bus bit 0. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_SPI1_MOSI (0x05UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_I2C0_SDA (0x06UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_UART5_RXD (0x07UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< Data receiver input pin for UART5. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_USCI1_CTL1 (0x08UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< USCI1 control1 pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_SC0_DAT (0x09UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< SmartCard0 data pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_I2S0_MCLK (0x0AUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< I2S0 master clock output pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_EPWM0_CH1 (0x0BUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< EPWM0 channel1 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_TM1 (0x0EUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< Timer1 event counter input / toggle output \hideinitializer */
+#define SYS_GPB_MFPL_PB4MFP_INT1 (0x0FUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< External interrupt1 input pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_ACMP1_N (0x01UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< Analog comparator1 negative input pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_EADC0_CH5 (0x01UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< EADC0 channel5 analog input. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_EBI_ADR0 (0x02UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_SD0_DAT3 (0x03UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< SD/SDIO 0 data line bit 3. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_EMAC_RMII_REFCLK (0x04UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< EMAC mode clock input. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_SPI1_MISO (0x05UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_I2C0_SCL (0x06UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_UART5_TXD (0x07UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< Data transmitter output pin for UART5. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_USCI1_CTL0 (0x08UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< USCI1 control0 pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_SC0_CLK (0x09UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< SmartCard0 clock pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_I2S0_BCLK (0x0AUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< I2S0 bit clock pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_EPWM0_CH0 (0x0BUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< EPWM0 channel0 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_TM0 (0x0EUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< Timer0 event counter input / toggle output \hideinitializer */
+#define SYS_GPB_MFPL_PB5MFP_INT0 (0x0FUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< External interrupt0 input pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_EADC0_CH6 (0x01UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< EADC0 channel6 analog input. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_EBI_nWRH (0x02UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< EBI write enable output pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_EMAC_PPS (0x03UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< EMAC Pulse Per Second output \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_USCI1_DAT1 (0x04UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< USCI1 data1 pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_CAN1_RXD (0x05UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< CAN1 bus receiver input. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_UART1_RXD (0x06UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_SD1_CLK (0x07UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< SD/SDIO 1 clock. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_EBI_nCS1 (0x08UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_BPWM1_CH5 (0x0AUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< BPWM1 channel5 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_EPWM1_BRAKE1 (0x0BUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< Brake input pin 1 of EPWM1. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_EPWM1_CH5 (0x0CUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< EPWM1 channel5 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_INT4 (0x0DUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< External interrupt4 input pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_USB_VBUS_EN (0x0EUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< Power supply from USB Full speed host or HUB. \hideinitializer */
+#define SYS_GPB_MFPL_PB6MFP_ACMP1_O (0x0FUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< Analog comparator1 output. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_EADC0_CH7 (0x01UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< EADC0 channel7 analog input. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_EBI_nWRL (0x02UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< EBI write enable output pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_EMAC_RMII_TXEN (0x03UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< RMII? Transmit Enable. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_USCI1_DAT0 (0x04UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< USCI1 data0 pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_CAN1_TXD (0x05UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< CAN1 bus transmitter output. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_UART1_TXD (0x06UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_SD1_CMD (0x07UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< SD/SDIO 1 command/response. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_EBI_nCS0 (0x08UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_BPWM1_CH4 (0x0AUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< BPWM1 channel4 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_EPWM1_BRAKE0 (0x0BUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< Brake input pin 0 of EPWM1. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_EPWM1_CH4 (0x0CUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< EPWM1 channel4 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_INT5 (0x0DUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< External interrupt5 input pin. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_USB_VBUS_ST (0x0EUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< Power supply from USB Full speed host or HUB. \hideinitializer */
+#define SYS_GPB_MFPL_PB7MFP_ACMP0_O (0x0FUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< Analog comparator0 output. \hideinitializer */
+/********************* Bit definition of GPB_MFPH register **********************/
+#define SYS_GPB_MFPH_PB8MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB8MFP_EADC0_CH8 (0x01UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< EADC0 channel8 analog input. \hideinitializer */
+#define SYS_GPB_MFPH_PB8MFP_EBI_ADR19 (0x02UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPB_MFPH_PB8MFP_EMAC_RMII_TXD1 (0x03UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< RMII Transmit Data bus bit 1. \hideinitializer */
+#define SYS_GPB_MFPH_PB8MFP_USCI1_CLK (0x04UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< USCI1 clock pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB8MFP_UART0_RXD (0x05UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
+#define SYS_GPB_MFPH_PB8MFP_UART1_nRTS (0x06UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< Request to Send output pin for UART1. \hideinitializer */
+#define SYS_GPB_MFPH_PB8MFP_I2C1_SMBSUS (0x07UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin) \hideinitializer */
+#define SYS_GPB_MFPH_PB8MFP_BPWM1_CH3 (0x0AUL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< BPWM1 channel3 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPH_PB8MFP_SPI3_MOSI (0x0BUL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< 1st SPI3 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB8MFP_INT6 (0x0DUL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< External interrupt6 input pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB9MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB9MFP_EADC0_CH9 (0x01UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< EADC0 channel9 analog input. \hideinitializer */
+#define SYS_GPB_MFPH_PB9MFP_EBI_ADR18 (0x02UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPB_MFPH_PB9MFP_EMAC_RMII_TXD0 (0x03UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< RMII Transmit Data bus bit 0. \hideinitializer */
+#define SYS_GPB_MFPH_PB9MFP_USCI1_CTL1 (0x04UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< USCI1 control1 pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB9MFP_UART0_TXD (0x05UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
+#define SYS_GPB_MFPH_PB9MFP_UART1_nCTS (0x06UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< Clear to Send input pin for UART1. \hideinitializer */
+#define SYS_GPB_MFPH_PB9MFP_I2C1_SMBAL (0x07UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< I2C1 SMBus SMBALTER# pin \hideinitializer */
+#define SYS_GPB_MFPH_PB9MFP_BPWM1_CH2 (0x0AUL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< BPWM1 channel2 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPH_PB9MFP_SPI3_MISO (0x0BUL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< 1st SPI3 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB9MFP_INT7 (0x0DUL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< External interrupt7 input pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB10MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB10MFP_EADC0_CH10 (0x01UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
+#define SYS_GPB_MFPH_PB10MFP_EBI_ADR17 (0x02UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPB_MFPH_PB10MFP_EMAC_RMII_MDIO (0x03UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< RMII Management Data I/O. \hideinitializer */
+#define SYS_GPB_MFPH_PB10MFP_USCI1_CTL0 (0x04UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< USCI1 control0 pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB10MFP_UART0_nRTS (0x05UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< Request to Send output pin for UART0. \hideinitializer */
+#define SYS_GPB_MFPH_PB10MFP_UART4_RXD (0x06UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */
+#define SYS_GPB_MFPH_PB10MFP_I2C1_SDA (0x07UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB10MFP_CAN0_RXD (0x08UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */
+#define SYS_GPB_MFPH_PB10MFP_BPWM1_CH1 (0x0AUL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< BPWM1 channel1 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPH_PB10MFP_SPI3_SS (0x0BUL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< 1st SPI3 slave select pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB10MFP_HSUSB_VBUS_EN (0x0EUL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< Power supply from USB High speed host or HUB. \hideinitializer */
+#define SYS_GPB_MFPH_PB11MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB11MFP_EADC0_CH11 (0x01UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
+#define SYS_GPB_MFPH_PB11MFP_EBI_ADR16 (0x02UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPB_MFPH_PB11MFP_EMAC_RMII_MDC (0x03UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< RMII Management Data Clock. \hideinitializer */
+#define SYS_GPB_MFPH_PB11MFP_UART0_nCTS (0x05UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< Clear to Send input pin for UART0. \hideinitializer */
+#define SYS_GPB_MFPH_PB11MFP_UART4_TXD (0x06UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */
+#define SYS_GPB_MFPH_PB11MFP_I2C1_SCL (0x07UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB11MFP_CAN0_TXD (0x08UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */
+#define SYS_GPB_MFPH_PB11MFP_SPI0_I2SMCLK (0x09UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< SPI0 I2S master clock output pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB11MFP_BPWM1_CH0 (0x0AUL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< BPWM1 channel0 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPH_PB11MFP_SPI3_CLK (0x0BUL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< SPI3 serial clock pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB11MFP_HSUSB_VBUS_ST (0x0EUL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< Power supply from USB High speed host or HUB. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_ACMP0_P2 (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Analog comparator0 positive input pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_ACMP1_P2 (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Analog comparator1 positive input pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_DAC0_OUT (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< DAC0 channel analog output. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_EADC0_CH12 (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_EBI_AD15 (0x02UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_SC1_CLK (0x03UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< SmartCard1 clock pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_SPI0_MOSI (0x04UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< 1st SPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_USCI0_CLK (0x05UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< USCI0 clock pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_UART0_RXD (0x06UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_UART3_nCTS (0x07UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Clear to Send input pin for UART3. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_I2C2_SDA (0x08UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_SD0_nCD (0x09UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< SD/SDIO 0 card detect \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_EPWM1_CH3 (0x0BUL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< EPWM1 channel3 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_ETM_TRACE_DATA3 (0x0CUL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< ETM Rx input bus bit3. \hideinitializer */
+#define SYS_GPB_MFPH_PB12MFP_TM3_EXT (0x0DUL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Timer3 event counter input / toggle output \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_ACMP0_P3 (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Analog comparator0 positive input pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_ACMP1_P3 (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Analog comparator1 positive input pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_DAC1_OUT (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< DAC1 channel analog output. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_EADC0_CH13 (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_EBI_AD14 (0x02UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_SC1_DAT (0x03UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< SmartCard1 data pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_SPI0_MISO (0x04UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< 1st SPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_USCI0_DAT0 (0x05UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< USCI0 data0 pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_UART0_TXD (0x06UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_UART3_nRTS (0x07UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Request to Send output pin for UART3. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_I2C2_SCL (0x08UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_EPWM1_CH2 (0x0BUL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< EPWM1 channel2 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_ETM_TRACE_DATA2 (0x0CUL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< ETM Rx input bus bit2. \hideinitializer */
+#define SYS_GPB_MFPH_PB13MFP_TM2_EXT (0x0DUL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Timer2 event counter input / toggle output \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_EADC0_CH14 (0x01UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_EBI_AD13 (0x02UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_SC1_RST (0x03UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< SmartCard1 reset pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_SPI0_CLK (0x04UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< SPI0 serial clock pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_USCI0_DAT1 (0x05UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< USCI0 data1 pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_UART0_nRTS (0x06UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< Request to Send output pin for UART0. \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_UART3_RXD (0x07UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< Data receiver input pin for UART3. \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_I2C2_SMBSUS (0x08UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< I2C2 SMBus SMBSUS# pin (PMBus CONTROL pin) \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_EPWM1_CH1 (0x0BUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< EPWM1 channel1 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_ETM_TRACE_DATA1 (0x0CUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< ETM Rx input bus bit1. \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_TM1_EXT (0x0DUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< Timer1 event counter input / toggle output \hideinitializer */
+#define SYS_GPB_MFPH_PB14MFP_CLKO (0x0EUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< Clock Output pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_EADC0_CH15 (0x01UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_EBI_AD12 (0x02UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_SC1_PWR (0x03UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< SmartCard1 power pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_SPI0_SS (0x04UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< 1st SPI0 slave select pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_USCI0_CTL1 (0x05UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< USCI0 control1 pin. \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_UART0_nCTS (0x06UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Clear to Send input pin for UART0. \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_UART3_TXD (0x07UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Data transmitter output pin for UART3. \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_I2C2_SMBAL (0x08UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< I2C2 SMBus SMBALTER# pin \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_EPWM1_CH0 (0x0BUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< EPWM1 channel0 output/capture input. \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_ETM_TRACE_DATA0 (0x0CUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< ETM Rx input bus bit0. \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_TM0_EXT (0x0DUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Timer0 event counter input / toggle output \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_USB_VBUS_EN (0x0EUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Power supply from USB Full speed host or HUB. \hideinitializer */
+#define SYS_GPB_MFPH_PB15MFP_HSUSB_VBUS_EN (0x0FUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Power supply from USB High speed host or HUB. \hideinitializer */
+/********************* Bit definition of GPC_MFPL register **********************/
+#define SYS_GPC_MFPL_PC0MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC0MFP_EBI_AD0 (0x02UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< EBI address/data bus bit0. \hideinitializer */
+#define SYS_GPC_MFPL_PC0MFP_SPIM_MOSI (0x03UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< 1st SPIM MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC0MFP_QSPI0_MOSI0 (0x04UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< 1st QSPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC0MFP_SC1_CLK (0x05UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< SmartCard1 clock pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC0MFP_I2S0_LRCK (0x06UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< I2S0 left right channel clock. \hideinitializer */
+#define SYS_GPC_MFPL_PC0MFP_SPI1_SS (0x07UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< 1st SPI1 slave select pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC0MFP_UART2_RXD (0x08UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */
+#define SYS_GPC_MFPL_PC0MFP_I2C0_SDA (0x09UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC0MFP_EPWM1_CH5 (0x0CUL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< EPWM1 channel5 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPL_PC0MFP_ACMP1_O (0x0EUL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< Analog comparator1 output. \hideinitializer */
+#define SYS_GPC_MFPL_PC1MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC1MFP_EBI_AD1 (0x02UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPC_MFPL_PC1MFP_SPIM_MISO (0x03UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< 1st SPIM MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC1MFP_QSPI0_MISO0 (0x04UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< 1st QSPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC1MFP_SC1_DAT (0x05UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< SmartCard1 data pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC1MFP_I2S0_DO (0x06UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< I2S0 data output. \hideinitializer */
+#define SYS_GPC_MFPL_PC1MFP_SPI1_CLK (0x07UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< SPI1 serial clock pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC1MFP_UART2_TXD (0x08UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */
+#define SYS_GPC_MFPL_PC1MFP_I2C0_SCL (0x09UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC1MFP_EPWM1_CH4 (0x0CUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< EPWM1 channel4 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPL_PC1MFP_ACMP0_O (0x0EUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< Analog comparator0 output. \hideinitializer */
+#define SYS_GPC_MFPL_PC2MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC2MFP_EBI_AD2 (0x02UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< EBI address/data bus bit2. \hideinitializer */
+#define SYS_GPC_MFPL_PC2MFP_SPIM_CLK (0x03UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< SPIM serial clock pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC2MFP_QSPI0_CLK (0x04UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< QSPI0 serial clock pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC2MFP_SC1_RST (0x05UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< SmartCard1 reset pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC2MFP_I2S0_DI (0x06UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< I2S0 data input. \hideinitializer */
+#define SYS_GPC_MFPL_PC2MFP_SPI1_MOSI (0x07UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC2MFP_UART2_nCTS (0x08UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< Clear to Send input pin for UART2. \hideinitializer */
+#define SYS_GPC_MFPL_PC2MFP_I2C0_SMBSUS (0x09UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin) \hideinitializer */
+#define SYS_GPC_MFPL_PC2MFP_CAN1_RXD (0x0AUL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< CAN1 bus receiver input. \hideinitializer */
+#define SYS_GPC_MFPL_PC2MFP_UART3_RXD (0x0BUL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< Data receiver input pin for UART3. \hideinitializer */
+#define SYS_GPC_MFPL_PC2MFP_EPWM1_CH3 (0x0CUL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< EPWM1 channel3 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPL_PC3MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC3MFP_EBI_AD3 (0x02UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< EBI address/data bus bit3. \hideinitializer */
+#define SYS_GPC_MFPL_PC3MFP_SPIM_SS (0x03UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< 1st SPIM slave select pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC3MFP_QSPI0_SS (0x04UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< 1st QSPI0 slave select pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC3MFP_SC1_PWR (0x05UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< SmartCard1 power pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC3MFP_I2S0_MCLK (0x06UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< I2S0 master clock output pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC3MFP_SPI1_MISO (0x07UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC3MFP_UART2_nRTS (0x08UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< Request to Send output pin for UART2. \hideinitializer */
+#define SYS_GPC_MFPL_PC3MFP_I2C0_SMBAL (0x09UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< I2C0 SMBus SMBALTER# pin \hideinitializer */
+#define SYS_GPC_MFPL_PC3MFP_CAN1_TXD (0x0AUL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< CAN1 bus transmitter output. \hideinitializer */
+#define SYS_GPC_MFPL_PC3MFP_UART3_TXD (0x0BUL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< Data transmitter output pin for UART3. \hideinitializer */
+#define SYS_GPC_MFPL_PC3MFP_EPWM1_CH2 (0x0CUL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< EPWM1 channel2 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPL_PC4MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC4MFP_EBI_AD4 (0x02UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< EBI address/data bus bit4. \hideinitializer */
+#define SYS_GPC_MFPL_PC4MFP_SPIM_D3 (0x03UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< SPIM data 3 pin for Quad Mode I/O. \hideinitializer */
+#define SYS_GPC_MFPL_PC4MFP_QSPI0_MOSI1 (0x04UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< 2nd QSPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC4MFP_SC1_nCD (0x05UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< SmartCard1 card detect pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC4MFP_I2S0_BCLK (0x06UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< I2S0 bit clock pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC4MFP_SPI1_I2SMCLK (0x07UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< SPI1 I2S master clock output pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC4MFP_UART2_RXD (0x08UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */
+#define SYS_GPC_MFPL_PC4MFP_I2C1_SDA (0x09UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC4MFP_CAN0_RXD (0x0AUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */
+#define SYS_GPC_MFPL_PC4MFP_UART4_RXD (0x0BUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */
+#define SYS_GPC_MFPL_PC4MFP_EPWM1_CH1 (0x0CUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< EPWM1 channel1 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPL_PC5MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC5MFP_EBI_AD5 (0x02UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< EBI address/data bus bit5. \hideinitializer */
+#define SYS_GPC_MFPL_PC5MFP_SPIM_D2 (0x03UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< SPIM data 2 pin for Quad Mode I/O. \hideinitializer */
+#define SYS_GPC_MFPL_PC5MFP_QSPI0_MISO1 (0x04UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< 2nd QSPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC5MFP_UART2_TXD (0x08UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */
+#define SYS_GPC_MFPL_PC5MFP_I2C1_SCL (0x09UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC5MFP_CAN0_TXD (0x0AUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */
+#define SYS_GPC_MFPL_PC5MFP_UART4_TXD (0x0BUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */
+#define SYS_GPC_MFPL_PC5MFP_EPWM1_CH0 (0x0CUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< EPWM1 channel0 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPL_PC6MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC6MFP_EBI_AD8 (0x02UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< EBI address/data bus bit8. \hideinitializer */
+#define SYS_GPC_MFPL_PC6MFP_EMAC_RMII_RXD1 (0x03UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< RMII Receive Data bus bit 1. \hideinitializer */
+#define SYS_GPC_MFPL_PC6MFP_SPI1_MOSI (0x04UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC6MFP_UART4_RXD (0x05UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */
+#define SYS_GPC_MFPL_PC6MFP_SC2_RST (0x06UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< SmartCard2 reset pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC6MFP_UART0_nRTS (0x07UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< Request to Send output pin for UART0. \hideinitializer */
+#define SYS_GPC_MFPL_PC6MFP_I2C1_SMBSUS (0x08UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin) \hideinitializer */
+#define SYS_GPC_MFPL_PC6MFP_EPWM1_CH3 (0x0BUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< EPWM1 channel3 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPL_PC6MFP_BPWM1_CH1 (0x0CUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< BPWM1 channel1 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPL_PC6MFP_TM1 (0x0EUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< Timer1 event counter input / toggle output \hideinitializer */
+#define SYS_GPC_MFPL_PC6MFP_INT2 (0x0FUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< External interrupt2 input pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC7MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC7MFP_EBI_AD9 (0x02UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< EBI address/data bus bit9. \hideinitializer */
+#define SYS_GPC_MFPL_PC7MFP_EMAC_RMII_RXD0 (0x03UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< RMII Receive Data bus bit 0. \hideinitializer */
+#define SYS_GPC_MFPL_PC7MFP_SPI1_MISO (0x04UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC7MFP_UART4_TXD (0x05UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */
+#define SYS_GPC_MFPL_PC7MFP_SC2_PWR (0x06UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< SmartCard2 power pin. \hideinitializer */
+#define SYS_GPC_MFPL_PC7MFP_UART0_nCTS (0x07UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< Clear to Send input pin for UART0. \hideinitializer */
+#define SYS_GPC_MFPL_PC7MFP_I2C1_SMBAL (0x08UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< I2C1 SMBus SMBALTER# pin \hideinitializer */
+#define SYS_GPC_MFPL_PC7MFP_EPWM1_CH2 (0x0BUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< EPWM1 channel2 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPL_PC7MFP_BPWM1_CH0 (0x0CUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< BPWM1 channel0 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPL_PC7MFP_TM0 (0x0EUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< Timer0 event counter input / toggle output \hideinitializer */
+#define SYS_GPC_MFPL_PC7MFP_INT3 (0x0FUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< External interrupt3 input pin. \hideinitializer */
+/********************* Bit definition of GPC_MFPH register **********************/
+#define SYS_GPC_MFPH_PC8MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC8MFP_EBI_ADR16 (0x02UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPC_MFPH_PC8MFP_EMAC_RMII_REFCLK (0x03UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< EMAC mode clock input. \hideinitializer */
+#define SYS_GPC_MFPH_PC8MFP_I2C0_SDA (0x04UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC8MFP_UART4_nCTS (0x05UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< Clear to Send input pin for UART4. \hideinitializer */
+#define SYS_GPC_MFPH_PC8MFP_UART1_RXD (0x08UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */
+#define SYS_GPC_MFPH_PC8MFP_EPWM1_CH1 (0x0BUL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< EPWM1 channel1 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPH_PC8MFP_BPWM1_CH4 (0x0CUL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< BPWM1 channel4 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPH_PC9MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC9MFP_EBI_ADR7 (0x02UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPC_MFPH_PC9MFP_SPI3_SS (0x06UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< 1st SPI3 slave select pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC9MFP_UART3_RXD (0x07UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< Data receiver input pin for UART3. \hideinitializer */
+#define SYS_GPC_MFPH_PC9MFP_CAN1_RXD (0x09UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< CAN1 bus receiver input. \hideinitializer */
+#define SYS_GPC_MFPH_PC9MFP_EPWM1_CH3 (0x0CUL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< EPWM1 channel3 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPH_PC10MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC10MFP_EBI_ADR6 (0x02UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPC_MFPH_PC10MFP_SPI3_CLK (0x06UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< SPI3 serial clock pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC10MFP_UART3_TXD (0x07UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< Data transmitter output pin for UART3. \hideinitializer */
+#define SYS_GPC_MFPH_PC10MFP_CAN1_TXD (0x09UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< CAN1 bus transmitter output. \hideinitializer */
+#define SYS_GPC_MFPH_PC10MFP_ECAP1_IC0 (0x0BUL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< Input 0 of enhanced capture unit 1. \hideinitializer */
+#define SYS_GPC_MFPH_PC10MFP_EPWM1_CH2 (0x0CUL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< EPWM1 channel2 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPH_PC11MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC11MFP_EBI_ADR5 (0x02UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPC_MFPH_PC11MFP_UART0_RXD (0x03UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
+#define SYS_GPC_MFPH_PC11MFP_I2C0_SDA (0x04UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC11MFP_SPI3_MOSI (0x06UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< 1st SPI3 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC11MFP_ECAP1_IC1 (0x0BUL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< Input 1 of enhanced capture unit 1. \hideinitializer */
+#define SYS_GPC_MFPH_PC11MFP_EPWM1_CH1 (0x0CUL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< EPWM1 channel1 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPH_PC11MFP_ACMP1_O (0x0EUL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< Analog comparator1 output. \hideinitializer */
+#define SYS_GPC_MFPH_PC12MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC12MFP_EBI_ADR4 (0x02UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPC_MFPH_PC12MFP_UART0_TXD (0x03UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
+#define SYS_GPC_MFPH_PC12MFP_I2C0_SCL (0x04UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC12MFP_SPI3_MISO (0x06UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< 1st SPI3 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC12MFP_SC0_nCD (0x09UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< SmartCard0 card detect pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC12MFP_ECAP1_IC2 (0x0BUL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< Input 1 of enhanced capture unit 2. \hideinitializer */
+#define SYS_GPC_MFPH_PC12MFP_EPWM1_CH0 (0x0CUL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< EPWM1 channel0 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPH_PC12MFP_ACMP0_O (0x0EUL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< Analog comparator0 output. \hideinitializer */
+#define SYS_GPC_MFPH_PC13MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC13MFP_EBI_ADR10 (0x02UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPC_MFPH_PC13MFP_SC2_nCD (0x03UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< SmartCard2 card detect pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC13MFP_SPI2_I2SMCLK (0x04UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< SPI2 I2S master clock output pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC13MFP_CAN1_TXD (0x05UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< CAN1 bus transmitter output. \hideinitializer */
+#define SYS_GPC_MFPH_PC13MFP_USCI0_CTL0 (0x06UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< USCI0 control0 pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC13MFP_UART2_TXD (0x07UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */
+#define SYS_GPC_MFPH_PC13MFP_BPWM0_CH4 (0x09UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< BPWM0 channel4 output/capture input. \hideinitializer */
+#define SYS_GPC_MFPH_PC13MFP_CLKO (0x0DUL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< Clock Output pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC13MFP_EADC0_ST (0x0EUL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< EADC external trigger input. \hideinitializer */
+#define SYS_GPC_MFPH_PC14MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC14MFP_EBI_AD11 (0x02UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPC_MFPH_PC14MFP_SC1_nCD (0x03UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< SmartCard1 card detect pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC14MFP_SPI0_I2SMCLK (0x04UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< SPI0 I2S master clock output pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC14MFP_USCI0_CTL0 (0x05UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< USCI0 control0 pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC14MFP_QSPI0_CLK (0x06UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< QSPI0 serial clock pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC14MFP_EPWM0_SYNC_IN (0x0BUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< EPWM0 counter synchronous trigger input pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC14MFP_ETM_TRACE_CLK (0x0CUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< ETM Rx clock input pin. \hideinitializer */
+#define SYS_GPC_MFPH_PC14MFP_TM1 (0x0DUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< Timer1 event counter input / toggle output \hideinitializer */
+#define SYS_GPC_MFPH_PC14MFP_USB_VBUS_ST (0x0EUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< Power supply from USB Full speed host or HUB. \hideinitializer */
+#define SYS_GPC_MFPH_PC14MFP_HSUSB_VBUS_ST (0x0FUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< Power supply from USB High speed host or HUB. \hideinitializer */
+/********************* Bit definition of GPD_MFPL register **********************/
+#define SYS_GPD_MFPL_PD0MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD0MFP_EBI_AD13 (0x02UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPD_MFPL_PD0MFP_USCI0_CLK (0x03UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< USCI0 clock pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD0MFP_SPI0_MOSI (0x04UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< 1st SPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD0MFP_UART3_RXD (0x05UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< Data receiver input pin for UART3. \hideinitializer */
+#define SYS_GPD_MFPL_PD0MFP_I2C2_SDA (0x06UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD0MFP_SC2_CLK (0x07UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< SmartCard2 clock pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD0MFP_TM2 (0x0EUL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< Timer2 event counter input / toggle output \hideinitializer */
+#define SYS_GPD_MFPL_PD1MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD1MFP_EBI_AD12 (0x02UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPD_MFPL_PD1MFP_USCI0_DAT0 (0x03UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< USCI0 data0 pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD1MFP_SPI0_MISO (0x04UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< 1st SPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD1MFP_UART3_TXD (0x05UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< Data transmitter output pin for UART3. \hideinitializer */
+#define SYS_GPD_MFPL_PD1MFP_I2C2_SCL (0x06UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD1MFP_SC2_DAT (0x07UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< SmartCard2 data pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD2MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD2MFP_EBI_AD11 (0x02UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPD_MFPL_PD2MFP_USCI0_DAT1 (0x03UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< USCI0 data1 pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD2MFP_SPI0_CLK (0x04UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< SPI0 serial clock pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD2MFP_UART3_nCTS (0x05UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< Clear to Send input pin for UART3. \hideinitializer */
+#define SYS_GPD_MFPL_PD2MFP_SC2_RST (0x07UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< SmartCard2 reset pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD2MFP_UART0_RXD (0x09UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
+#define SYS_GPD_MFPL_PD3MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD3MFP_EBI_AD10 (0x02UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPD_MFPL_PD3MFP_USCI0_CTL1 (0x03UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< USCI0 control1 pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD3MFP_SPI0_SS (0x04UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< 1st SPI0 slave select pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD3MFP_UART3_nRTS (0x05UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< Request to Send output pin for UART3. \hideinitializer */
+#define SYS_GPD_MFPL_PD3MFP_USCI1_CTL0 (0x06UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< USCI1 control0 pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD3MFP_SC2_PWR (0x07UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< SmartCard2 power pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD3MFP_SC1_nCD (0x08UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< SmartCard1 card detect pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD3MFP_UART0_TXD (0x09UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
+#define SYS_GPD_MFPL_PD4MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD4MFP_USCI0_CTL0 (0x03UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< USCI0 control0 pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD4MFP_I2C1_SDA (0x04UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD4MFP_SPI1_SS (0x05UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< 1st SPI1 slave select pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD4MFP_USCI1_CTL1 (0x06UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< USCI1 control1 pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD4MFP_SC1_CLK (0x08UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< SmartCard1 clock pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD4MFP_USB_VBUS_ST (0x0EUL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< Power supply from USB Full speed host or HUB. \hideinitializer */
+#define SYS_GPD_MFPL_PD5MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD5MFP_I2C1_SCL (0x04UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD5MFP_SPI1_CLK (0x05UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< SPI1 serial clock pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD5MFP_USCI1_DAT0 (0x06UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< USCI1 data0 pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD5MFP_SC1_DAT (0x08UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< SmartCard1 data pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD6MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD6MFP_UART1_RXD (0x03UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */
+#define SYS_GPD_MFPL_PD6MFP_I2C0_SDA (0x04UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD6MFP_SPI1_MOSI (0x05UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD6MFP_USCI1_DAT1 (0x06UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< USCI1 data1 pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD6MFP_SC1_RST (0x08UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< SmartCard1 reset pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD7MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD7MFP_UART1_TXD (0x03UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */
+#define SYS_GPD_MFPL_PD7MFP_I2C0_SCL (0x04UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD7MFP_SPI1_MISO (0x05UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD7MFP_USCI1_CLK (0x06UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< USCI1 clock pin. \hideinitializer */
+#define SYS_GPD_MFPL_PD7MFP_SC1_PWR (0x08UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< SmartCard1 power pin. \hideinitializer */
+/********************* Bit definition of GPD_MFPH register **********************/
+#define SYS_GPD_MFPH_PD8MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD8MFP_EBI_AD6 (0x02UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< EBI address/data bus bit6. \hideinitializer */
+#define SYS_GPD_MFPH_PD8MFP_I2C2_SDA (0x03UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD8MFP_UART2_nRTS (0x04UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< Request to Send output pin for UART2. \hideinitializer */
+#define SYS_GPD_MFPH_PD9MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD9MFP_EBI_AD7 (0x02UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< EBI address/data bus bit7. \hideinitializer */
+#define SYS_GPD_MFPH_PD9MFP_I2C2_SCL (0x03UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD9MFP_UART2_nCTS (0x04UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< Clear to Send input pin for UART2. \hideinitializer */
+#define SYS_GPD_MFPH_PD10MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD10MFP_OPA2_P (0x01UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< Operational amplifier positive input pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD10MFP_EBI_nCS2 (0x02UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD10MFP_UART1_RXD (0x03UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */
+#define SYS_GPD_MFPH_PD10MFP_CAN0_RXD (0x04UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */
+#define SYS_GPD_MFPH_PD10MFP_QEI0_B (0x0AUL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< Quadrature encoder phase B input of QEI Unit 0. \hideinitializer */
+#define SYS_GPD_MFPH_PD10MFP_INT7 (0x0FUL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< External interrupt7 input pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD11MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD11MFP_OPA2_N (0x01UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< Operational amplifier negative input pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD11MFP_EBI_nCS1 (0x02UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD11MFP_UART1_TXD (0x03UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */
+#define SYS_GPD_MFPH_PD11MFP_CAN0_TXD (0x04UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */
+#define SYS_GPD_MFPH_PD11MFP_QEI0_A (0x0AUL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< Quadrature encoder phase A input of QEI Unit 0. \hideinitializer */
+#define SYS_GPD_MFPH_PD11MFP_INT6 (0x0FUL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< External interrupt6 input pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD12MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD12MFP_OPA2_O (0x01UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< Operational amplifier output pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD12MFP_EBI_nCS0 (0x02UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD12MFP_CAN1_RXD (0x05UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< CAN1 bus receiver input. \hideinitializer */
+#define SYS_GPD_MFPH_PD12MFP_UART2_RXD (0x07UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */
+#define SYS_GPD_MFPH_PD12MFP_BPWM0_CH5 (0x09UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< BPWM0 channel5 output/capture input. \hideinitializer */
+#define SYS_GPD_MFPH_PD12MFP_QEI0_INDEX (0x0AUL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< Quadrature encoder index input of QEI Unit 0. \hideinitializer */
+#define SYS_GPD_MFPH_PD12MFP_CLKO (0x0DUL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< Clock Output pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD12MFP_EADC0_ST (0x0EUL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< EADC external trigger input. \hideinitializer */
+#define SYS_GPD_MFPH_PD12MFP_INT5 (0x0FUL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< External interrupt5 input pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD13MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD13MFP_EBI_AD10 (0x02UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPD_MFPH_PD13MFP_SD0_nCD (0x03UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< SD/SDIO 0 card detect \hideinitializer */
+#define SYS_GPD_MFPH_PD13MFP_SPI0_I2SMCLK (0x04UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< SPI0 I2S master clock output pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD13MFP_SPI1_I2SMCLK (0x05UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< SPI1 I2S master clock output pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD13MFP_SC2_nCD (0x07UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< SmartCard2 card detect pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD14MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD14MFP_EBI_nCS0 (0x02UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD14MFP_SPI3_I2SMCLK (0x03UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< SPI3 I2S master clock output pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD14MFP_SC1_nCD (0x04UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< SmartCard1 card detect pin. \hideinitializer */
+#define SYS_GPD_MFPH_PD14MFP_EPWM0_CH4 (0x0BUL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< EPWM0 channel4 output/capture input. \hideinitializer */
+/********************* Bit definition of GPE_MFPL register **********************/
+#define SYS_GPE_MFPL_PE0MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE0MFP_EBI_AD11 (0x02UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPE_MFPL_PE0MFP_QSPI0_MOSI0 (0x03UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< 1st QSPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE0MFP_SC2_CLK (0x04UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< SmartCard2 clock pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE0MFP_I2S0_MCLK (0x05UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< I2S0 master clock output pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE0MFP_SPI1_MOSI (0x06UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE0MFP_UART3_RXD (0x07UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< Data receiver input pin for UART3. \hideinitializer */
+#define SYS_GPE_MFPL_PE0MFP_I2C1_SDA (0x08UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE0MFP_UART4_nRTS (0x09UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< Request to Send output pin for UART4. \hideinitializer */
+#define SYS_GPE_MFPL_PE1MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE1MFP_EBI_AD10 (0x02UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPE_MFPL_PE1MFP_QSPI0_MISO0 (0x03UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< 1st QSPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE1MFP_SC2_DAT (0x04UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< SmartCard2 data pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE1MFP_I2S0_BCLK (0x05UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< I2S0 bit clock pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE1MFP_SPI1_MISO (0x06UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE1MFP_UART3_TXD (0x07UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< Data transmitter output pin for UART3. \hideinitializer */
+#define SYS_GPE_MFPL_PE1MFP_I2C1_SCL (0x08UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE1MFP_UART4_nCTS (0x09UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< Clear to Send input pin for UART4. \hideinitializer */
+#define SYS_GPE_MFPL_PE2MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE2MFP_EBI_ALE (0x02UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< EBI address latch enable output pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE2MFP_SD0_DAT0 (0x03UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< SD/SDIO 0 data line bit 0. \hideinitializer */
+#define SYS_GPE_MFPL_PE2MFP_SPIM_MOSI (0x04UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< 1st SPIM MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE2MFP_SPI3_MOSI (0x05UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< 1st SPI3 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE2MFP_SC0_CLK (0x06UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< SmartCard0 clock pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE2MFP_USCI0_CLK (0x07UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< USCI0 clock pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE2MFP_QEI0_B (0x0BUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< Quadrature encoder phase B input of QEI Unit 0. \hideinitializer */
+#define SYS_GPE_MFPL_PE2MFP_EPWM0_CH5 (0x0CUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< EPWM0 channel5 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPL_PE2MFP_BPWM0_CH0 (0x0DUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< BPWM0 channel0 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPL_PE3MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE3MFP_EBI_MCLK (0x02UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< EBI external clock output pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE3MFP_SD0_DAT1 (0x03UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< SD/SDIO 0 data line bit 1. \hideinitializer */
+#define SYS_GPE_MFPL_PE3MFP_SPIM_MISO (0x04UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< 1st SPIM MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE3MFP_SPI3_MISO (0x05UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< 1st SPI3 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE3MFP_SC0_DAT (0x06UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< SmartCard0 data pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE3MFP_USCI0_DAT0 (0x07UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< USCI0 data0 pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE3MFP_QEI0_A (0x0BUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< Quadrature encoder phase A input of QEI Unit 0. \hideinitializer */
+#define SYS_GPE_MFPL_PE3MFP_EPWM0_CH4 (0x0CUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< EPWM0 channel4 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPL_PE3MFP_BPWM0_CH1 (0x0DUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< BPWM0 channel1 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPL_PE4MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE4MFP_EBI_nWR (0x02UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< EBI write enable output pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE4MFP_SD0_DAT2 (0x03UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< SD/SDIO 0 data line bit 2. \hideinitializer */
+#define SYS_GPE_MFPL_PE4MFP_SPIM_CLK (0x04UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< SPIM serial clock pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE4MFP_SPI3_CLK (0x05UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< SPI3 serial clock pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE4MFP_SC0_RST (0x06UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< SmartCard0 reset pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE4MFP_USCI0_DAT1 (0x07UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< USCI0 data1 pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE4MFP_QEI0_INDEX (0x0BUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< Quadrature encoder index input of QEI Unit 0. \hideinitializer */
+#define SYS_GPE_MFPL_PE4MFP_EPWM0_CH3 (0x0CUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< EPWM0 channel3 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPL_PE4MFP_BPWM0_CH2 (0x0DUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< BPWM0 channel2 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPL_PE5MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE5MFP_EBI_nRD (0x02UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< EBI read enable output pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE5MFP_SD0_DAT3 (0x03UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< SD/SDIO 0 data line bit 3. \hideinitializer */
+#define SYS_GPE_MFPL_PE5MFP_SPIM_SS (0x04UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< 1st SPIM slave select pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE5MFP_SPI3_SS (0x05UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< 1st SPI3 slave select pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE5MFP_SC0_PWR (0x06UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< SmartCard0 power pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE5MFP_USCI0_CTL1 (0x07UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< USCI0 control1 pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE5MFP_QEI1_B (0x0BUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< Quadrature encoder phase B input of QEI Unit 1. \hideinitializer */
+#define SYS_GPE_MFPL_PE5MFP_EPWM0_CH2 (0x0CUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< EPWM0 channel2 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPL_PE5MFP_BPWM0_CH3 (0x0DUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< BPWM0 channel3 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPL_PE6MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE6MFP_SD0_CLK (0x03UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< SD/SDIO 0 clock. \hideinitializer */
+#define SYS_GPE_MFPL_PE6MFP_SPIM_D3 (0x04UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< SPIM data 3 pin for Quad Mode I/O. \hideinitializer */
+#define SYS_GPE_MFPL_PE6MFP_SPI3_I2SMCLK (0x05UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< SPI3 I2S master clock output pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE6MFP_SC0_nCD (0x06UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< SmartCard0 card detect pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE6MFP_USCI0_CTL0 (0x07UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< USCI0 control0 pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE6MFP_UART5_RXD (0x08UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< Data receiver input pin for UART5. \hideinitializer */
+#define SYS_GPE_MFPL_PE6MFP_CAN1_RXD (0x09UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< CAN1 bus receiver input. \hideinitializer */
+#define SYS_GPE_MFPL_PE6MFP_QEI1_A (0x0BUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< Quadrature encoder phase A input of QEI Unit 1. \hideinitializer */
+#define SYS_GPE_MFPL_PE6MFP_EPWM0_CH1 (0x0CUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< EPWM0 channel1 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPL_PE6MFP_BPWM0_CH4 (0x0DUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< BPWM0 channel4 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPL_PE7MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPL_PE7MFP_SD0_CMD (0x03UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< SD/SDIO 0 command/response. \hideinitializer */
+#define SYS_GPE_MFPL_PE7MFP_SPIM_D2 (0x04UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< SPIM data 2 pin for Quad Mode I/O. \hideinitializer */
+#define SYS_GPE_MFPL_PE7MFP_UART5_TXD (0x08UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< Data transmitter output pin for UART5. \hideinitializer */
+#define SYS_GPE_MFPL_PE7MFP_CAN1_TXD (0x09UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< CAN1 bus transmitter output. \hideinitializer */
+#define SYS_GPE_MFPL_PE7MFP_QEI1_INDEX (0x0BUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< Quadrature encoder index input of QEI Unit 1. \hideinitializer */
+#define SYS_GPE_MFPL_PE7MFP_EPWM0_CH0 (0x0CUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< EPWM0 channel0 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPL_PE7MFP_BPWM0_CH5 (0x0DUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< BPWM0 channel5 output/capture input. \hideinitializer */
+/********************* Bit definition of GPE_MFPH register **********************/
+#define SYS_GPE_MFPH_PE8MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE8MFP_EBI_ADR10 (0x02UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPE_MFPH_PE8MFP_EMAC_RMII_MDC (0x03UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< RMII Management Data Clock. \hideinitializer */
+#define SYS_GPE_MFPH_PE8MFP_I2S0_BCLK (0x04UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< I2S0 bit clock pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE8MFP_SPI2_CLK (0x05UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< SPI2 serial clock pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE8MFP_USCI1_CTL1 (0x06UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< USCI1 control1 pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE8MFP_UART2_TXD (0x07UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */
+#define SYS_GPE_MFPH_PE8MFP_EPWM0_CH0 (0x0AUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< EPWM0 channel0 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPH_PE8MFP_EPWM0_BRAKE0 (0x0BUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< Brake input pin 0 of EPWM0. \hideinitializer */
+#define SYS_GPE_MFPH_PE8MFP_ECAP0_IC0 (0x0CUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< Input 0 of enhanced capture unit 0. \hideinitializer */
+#define SYS_GPE_MFPH_PE8MFP_TRACE_DATA3 (0x0EUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< ETM Rx input bus bit3. \hideinitializer */
+#define SYS_GPE_MFPH_PE9MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE9MFP_EBI_ADR11 (0x02UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPE_MFPH_PE9MFP_EMAC_RMII_MDIO (0x03UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< RMII Management Data I/O. \hideinitializer */
+#define SYS_GPE_MFPH_PE9MFP_I2S0_MCLK (0x04UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< I2S0 master clock output pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE9MFP_SPI2_MISO (0x05UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< 1st SPI2 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE9MFP_USCI1_CTL0 (0x06UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< USCI1 control0 pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE9MFP_UART2_RXD (0x07UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */
+#define SYS_GPE_MFPH_PE9MFP_EPWM0_CH1 (0x0AUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< EPWM0 channel1 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPH_PE9MFP_EPWM0_BRAKE1 (0x0BUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< Brake input pin 1 of EPWM0. \hideinitializer */
+#define SYS_GPE_MFPH_PE9MFP_ECAP0_IC1 (0x0CUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< Input 1 of enhanced capture unit 0. \hideinitializer */
+#define SYS_GPE_MFPH_PE9MFP_TRACE_DATA2 (0x0EUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< ETM Rx input bus bit2. \hideinitializer */
+#define SYS_GPE_MFPH_PE10MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE10MFP_EBI_ADR12 (0x02UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPE_MFPH_PE10MFP_EMAC_RMII_TXD0 (0x03UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< RMII Transmit Data bus bit 0. \hideinitializer */
+#define SYS_GPE_MFPH_PE10MFP_I2S0_DI (0x04UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< I2S0 data input. \hideinitializer */
+#define SYS_GPE_MFPH_PE10MFP_SPI2_MOSI (0x05UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< 1st SPI2 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE10MFP_USCI1_DAT0 (0x06UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< USCI1 data0 pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE10MFP_UART3_TXD (0x07UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< Data transmitter output pin for UART3. \hideinitializer */
+#define SYS_GPE_MFPH_PE10MFP_EPWM0_CH2 (0x0AUL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< EPWM0 channel2 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPH_PE10MFP_EPWM1_BRAKE0 (0x0BUL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< Brake input pin 0 of EPWM1. \hideinitializer */
+#define SYS_GPE_MFPH_PE10MFP_ECAP0_IC2 (0x0CUL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< Input 0 of enhanced capture unit 2. \hideinitializer */
+#define SYS_GPE_MFPH_PE10MFP_TRACE_DATA1 (0x0EUL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< ETM Rx input bus bit1. \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_EBI_ADR13 (0x02UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_EMAC_RMII_TXD1 (0x03UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< RMII Transmit Data bus bit 1. \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_I2S0_DO (0x04UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< I2S0 data output. \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_SPI2_SS (0x05UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< 1st SPI2 slave select pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_USCI1_DAT1 (0x06UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< USCI1 data1 pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_UART3_RXD (0x07UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< Data receiver input pin for UART3. \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_UART1_nCTS (0x08UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< Clear to Send input pin for UART1. \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_EPWM0_CH3 (0x0AUL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< EPWM0 channel3 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_EPWM1_BRAKE1 (0x0BUL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< Brake input pin 1 of EPWM1. \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_ECAP1_IC2 (0x0DUL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< Input 1 of enhanced capture unit 2. \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_TRACE_DATA0 (0x0EUL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< ETM Rx input bus bit0. \hideinitializer */
+#define SYS_GPE_MFPH_PE12MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE12MFP_EBI_ADR14 (0x02UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPE_MFPH_PE12MFP_EMAC_RMII_TXEN (0x03UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< RMII? Transmit Enable. \hideinitializer */
+#define SYS_GPE_MFPH_PE12MFP_I2S0_LRCK (0x04UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< I2S0 left right channel clock. \hideinitializer */
+#define SYS_GPE_MFPH_PE12MFP_SPI2_I2SMCLK (0x05UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< SPI2 I2S master clock output pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE12MFP_USCI1_CLK (0x06UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< USCI1 clock pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE12MFP_UART1_nRTS (0x08UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< Request to Send output pin for UART1. \hideinitializer */
+#define SYS_GPE_MFPH_PE12MFP_EPWM0_CH4 (0x0AUL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< EPWM0 channel4 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPH_PE12MFP_ECAP1_IC1 (0x0DUL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< Input 1 of enhanced capture unit 1. \hideinitializer */
+#define SYS_GPE_MFPH_PE12MFP_TRACE_CLK (0x0EUL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< ETM Rx clock input pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE13MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE13MFP_EBI_ADR15 (0x02UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPE_MFPH_PE13MFP_EMAC_PPS (0x03UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< EMAC Pulse Per Second output \hideinitializer */
+#define SYS_GPE_MFPH_PE13MFP_I2C0_SCL (0x04UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE13MFP_UART4_nRTS (0x05UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< Request to Send output pin for UART4. \hideinitializer */
+#define SYS_GPE_MFPH_PE13MFP_UART1_TXD (0x08UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */
+#define SYS_GPE_MFPH_PE13MFP_EPWM0_CH5 (0x0AUL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< EPWM0 channel5 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPH_PE13MFP_EPWM1_CH0 (0x0BUL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< EPWM1 channel0 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPH_PE13MFP_BPWM1_CH5 (0x0CUL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< BPWM1 channel5 output/capture input. \hideinitializer */
+#define SYS_GPE_MFPH_PE13MFP_ECAP1_IC0 (0x0DUL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< Input 0 of enhanced capture unit 1. \hideinitializer */
+#define SYS_GPE_MFPH_PE14MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE14MFP_EBI_AD8 (0x02UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< EBI address/data bus bit8. \hideinitializer */
+#define SYS_GPE_MFPH_PE14MFP_UART2_TXD (0x03UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */
+#define SYS_GPE_MFPH_PE14MFP_CAN0_TXD (0x04UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */
+#define SYS_GPE_MFPH_PE14MFP_SD1_nCD (0x05UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< SD/SDIO 1 card detect \hideinitializer */
+#define SYS_GPE_MFPH_PE15MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPE_MFPH_PE15MFP_EBI_AD9 (0x02UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< EBI address/data bus bit9. \hideinitializer */
+#define SYS_GPE_MFPH_PE15MFP_UART2_RXD (0x03UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */
+#define SYS_GPE_MFPH_PE15MFP_CAN0_RXD (0x04UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */
+/********************* Bit definition of GPF_MFPL register **********************/
+#define SYS_GPF_MFPL_PF0MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF0MFP_UART1_TXD (0x02UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */
+#define SYS_GPF_MFPL_PF0MFP_I2C1_SCL (0x03UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF0MFP_BPWM1_CH0 (0x0CUL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< BPWM1 channel0 output/capture input. \hideinitializer */
+#define SYS_GPF_MFPL_PF0MFP_ICE_DAT (0x0EUL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< Serial wired debugger data pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF1MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF1MFP_UART1_RXD (0x02UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */
+#define SYS_GPF_MFPL_PF1MFP_I2C1_SDA (0x03UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF1MFP_BPWM1_CH1 (0x0CUL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< BPWM1 channel1 output/capture input. \hideinitializer */
+#define SYS_GPF_MFPL_PF1MFP_ICE_CLK (0x0EUL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< Serial wired debugger clock pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF2MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF2MFP_EBI_nCS1 (0x02UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF2MFP_UART0_RXD (0x03UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
+#define SYS_GPF_MFPL_PF2MFP_I2C0_SDA (0x04UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF2MFP_QSPI0_CLK (0x05UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< QSPI0 serial clock pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF2MFP_XT1_OUT (0x0AUL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< External 4~24 MHz (high speed) crystal output pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF2MFP_BPWM1_CH1 (0x0BUL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< BPWM1 channel1 output/capture input. \hideinitializer */
+#define SYS_GPF_MFPL_PF3MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF3MFP_EBI_nCS0 (0x02UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF3MFP_UART0_TXD (0x03UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
+#define SYS_GPF_MFPL_PF3MFP_I2C0_SCL (0x04UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF3MFP_XT1_IN (0x0AUL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< External 4~24 MHz (high speed) crystal input pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF3MFP_BPWM1_CH0 (0x0BUL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< BPWM1 channel0 output/capture input. \hideinitializer */
+#define SYS_GPF_MFPL_PF4MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF4MFP_UART2_TXD (0x02UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */
+#define SYS_GPF_MFPL_PF4MFP_UART2_nRTS (0x04UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< Request to Send output pin for UART2. \hideinitializer */
+#define SYS_GPF_MFPL_PF4MFP_BPWM0_CH5 (0x08UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< BPWM0 channel5 output/capture input. \hideinitializer */
+#define SYS_GPF_MFPL_PF4MFP_X32_OUT (0x0AUL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< External 32.768 kHz (low speed) crystal output pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF5MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF5MFP_UART2_RXD (0x02UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */
+#define SYS_GPF_MFPL_PF5MFP_UART2_nCTS (0x04UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< Clear to Send input pin for UART2. \hideinitializer */
+#define SYS_GPF_MFPL_PF5MFP_BPWM0_CH4 (0x08UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< BPWM0 channel4 output/capture input. \hideinitializer */
+#define SYS_GPF_MFPL_PF5MFP_EPWM0_SYNC_OUT (0x09UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< EPWM0 counter synchronous trigger output pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF5MFP_X32_IN (0x0AUL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< External 32.768 kHz (low speed) crystal input pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF5MFP_EADC0_ST (0x0BUL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< EADC external trigger input. \hideinitializer */
+#define SYS_GPF_MFPL_PF6MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF6MFP_EBI_ADR19 (0x02UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPF_MFPL_PF6MFP_SC0_CLK (0x03UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< SmartCard0 clock pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF6MFP_I2S0_LRCK (0x04UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< I2S0 left right channel clock. \hideinitializer */
+#define SYS_GPF_MFPL_PF6MFP_SPI0_MOSI (0x05UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< 1st SPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF6MFP_UART4_RXD (0x06UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */
+#define SYS_GPF_MFPL_PF6MFP_EBI_nCS0 (0x07UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF6MFP_TAMPER0 (0x0AUL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< TAMPER detector loop pin0. \hideinitializer */
+#define SYS_GPF_MFPL_PF7MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF7MFP_EBI_ADR18 (0x02UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPF_MFPL_PF7MFP_SC0_DAT (0x03UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< SmartCard0 data pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF7MFP_I2S0_DO (0x04UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< I2S0 data output. \hideinitializer */
+#define SYS_GPF_MFPL_PF7MFP_SPI0_MISO (0x05UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< 1st SPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPF_MFPL_PF7MFP_UART4_TXD (0x06UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */
+#define SYS_GPF_MFPL_PF7MFP_TAMPER1 (0x0AUL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< TAMPER detector loop pin1. \hideinitializer */
+/********************* Bit definition of GPF_MFPH register **********************/
+#define SYS_GPF_MFPH_PF8MFP_GPIO (0x00UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF8MFP_EBI_ADR17 (0x02UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPF_MFPH_PF8MFP_SC0_RST (0x03UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< SmartCard0 reset pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF8MFP_I2S0_DI (0x04UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< I2S0 data input. \hideinitializer */
+#define SYS_GPF_MFPH_PF8MFP_SPI0_CLK (0x05UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< SPI0 serial clock pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF8MFP_TAMPER2 (0x0AUL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< TAMPER detector loop pin2. \hideinitializer */
+#define SYS_GPF_MFPH_PF9MFP_GPIO (0x00UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF9MFP_EBI_ADR16 (0x02UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPF_MFPH_PF9MFP_SC0_PWR (0x03UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< SmartCard0 power pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF9MFP_I2S0_MCLK (0x04UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< I2S0 master clock output pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF9MFP_SPI0_SS (0x05UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< 1st SPI0 slave select pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF9MFP_TAMPER3 (0x0AUL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< TAMPER detector loop pin3. \hideinitializer */
+#define SYS_GPF_MFPH_PF10MFP_GPIO (0x00UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF10MFP_EBI_ADR15 (0x02UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPF_MFPH_PF10MFP_SC0_nCD (0x03UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< SmartCard0 card detect pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF10MFP_I2S0_BCLK (0x04UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< I2S0 bit clock pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF10MFP_SPI0_I2SMCLK (0x05UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< SPI0 I2S master clock output pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF10MFP_TAMPER4 (0x0AUL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< TAMPER detector loop pin4. \hideinitializer */
+#define SYS_GPF_MFPH_PF11MFP_GPIO (0x00UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF11MFP_EBI_ADR14 (0x02UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPF_MFPH_PF11MFP_SPI2_MOSI (0x03UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< 1st SPI2 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPF_MFPH_PF11MFP_TAMPER5 (0x0AUL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< TAMPER detector loop pin5. \hideinitializer */
+#define SYS_GPF_MFPH_PF11MFP_TM3 (0x0DUL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< Timer3 event counter input / toggle output \hideinitializer */
+/********************* Bit definition of GPG_MFPL register **********************/
+#define SYS_GPG_MFPL_PG0MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG0MFP_EBI_ADR8 (0x02UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPG_MFPL_PG0MFP_I2C0_SCL (0x04UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG0MFP_I2C1_SMBAL (0x05UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< I2C1 SMBus SMBALTER# pin \hideinitializer */
+#define SYS_GPG_MFPL_PG0MFP_UART2_RXD (0x06UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */
+#define SYS_GPG_MFPL_PG0MFP_CAN1_TXD (0x07UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< CAN1 bus transmitter output. \hideinitializer */
+#define SYS_GPG_MFPL_PG0MFP_UART1_TXD (0x08UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */
+#define SYS_GPG_MFPL_PG1MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG1MFP_EBI_ADR9 (0x02UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPG_MFPL_PG1MFP_SPI2_I2SMCLK (0x03UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< SPI2 I2S master clock output pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG1MFP_I2C0_SDA (0x04UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG1MFP_I2C1_SMBSUS (0x05UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin) \hideinitializer */
+#define SYS_GPG_MFPL_PG1MFP_UART2_TXD (0x06UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */
+#define SYS_GPG_MFPL_PG1MFP_CAN1_RXD (0x07UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< CAN1 bus receiver input. \hideinitializer */
+#define SYS_GPG_MFPL_PG1MFP_UART1_RXD (0x08UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */
+#define SYS_GPG_MFPL_PG2MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG2MFP_EBI_ADR11 (0x02UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPG_MFPL_PG2MFP_SPI2_SS (0x03UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< 1st SPI2 slave select pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG2MFP_I2C0_SMBAL (0x04UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< I2C0 SMBus SMBALTER# pin \hideinitializer */
+#define SYS_GPG_MFPL_PG2MFP_I2C1_SCL (0x05UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG2MFP_TM0 (0x0DUL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< Timer0 event counter input / toggle output \hideinitializer */
+#define SYS_GPG_MFPL_PG3MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG3MFP_EBI_ADR12 (0x02UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPG_MFPL_PG3MFP_SPI2_CLK (0x03UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< SPI2 serial clock pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG3MFP_I2C0_SMBSUS (0x04UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin) \hideinitializer */
+#define SYS_GPG_MFPL_PG3MFP_I2C1_SDA (0x05UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG3MFP_TM1 (0x0DUL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< Timer1 event counter input / toggle output \hideinitializer */
+#define SYS_GPG_MFPL_PG4MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG4MFP_EBI_ADR13 (0x02UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPG_MFPL_PG4MFP_SPI2_MISO (0x03UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< 1st SPI2 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG4MFP_TM2 (0x0DUL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< Timer2 event counter input / toggle output \hideinitializer */
+#define SYS_GPG_MFPL_PG5MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG5MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG5MFP_EBI_nCS1 (0x02UL<<SYS_GPG_MFPL_PG5MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG5MFP_SPI3_SS (0x03UL<<SYS_GPG_MFPL_PG5MFP_Pos) /*!< 1st SPI3 slave select pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG5MFP_SC1_PWR (0x04UL<<SYS_GPG_MFPL_PG5MFP_Pos) /*!< SmartCard1 power pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG5MFP_EPWM0_CH3 (0x0BUL<<SYS_GPG_MFPL_PG5MFP_Pos) /*!< EPWM0 channel3 output/capture input. \hideinitializer */
+#define SYS_GPG_MFPL_PG6MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG6MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG6MFP_EBI_nCS2 (0x02UL<<SYS_GPG_MFPL_PG6MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG6MFP_SPI3_CLK (0x03UL<<SYS_GPG_MFPL_PG6MFP_Pos) /*!< SPI3 serial clock pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG6MFP_SC1_RST (0x04UL<<SYS_GPG_MFPL_PG6MFP_Pos) /*!< SmartCard1 reset pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG6MFP_EPWM0_CH2 (0x0BUL<<SYS_GPG_MFPL_PG6MFP_Pos) /*!< EPWM0 channel2 output/capture input. \hideinitializer */
+#define SYS_GPG_MFPL_PG7MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG7MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG7MFP_EBI_nWRL (0x02UL<<SYS_GPG_MFPL_PG7MFP_Pos) /*!< EBI write enable output pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG7MFP_SPI3_MISO (0x03UL<<SYS_GPG_MFPL_PG7MFP_Pos) /*!< 1st SPI3 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG7MFP_SC1_DAT (0x04UL<<SYS_GPG_MFPL_PG7MFP_Pos) /*!< SmartCard1 data pin. \hideinitializer */
+#define SYS_GPG_MFPL_PG7MFP_EPWM0_CH1 (0x0BUL<<SYS_GPG_MFPL_PG7MFP_Pos) /*!< EPWM0 channel1 output/capture input. \hideinitializer */
+/********************* Bit definition of GPG_MFPH register **********************/
+#define SYS_GPG_MFPH_PG8MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG8MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG8MFP_EBI_nWRH (0x02UL<<SYS_GPG_MFPH_PG8MFP_Pos) /*!< EBI write enable output pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG8MFP_SPI3_MOSI (0x03UL<<SYS_GPG_MFPH_PG8MFP_Pos) /*!< 1st SPI3 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG8MFP_SC1_CLK (0x04UL<<SYS_GPG_MFPH_PG8MFP_Pos) /*!< SmartCard1 clock pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG8MFP_EPWM0_CH0 (0x0BUL<<SYS_GPG_MFPH_PG8MFP_Pos) /*!< EPWM0 channel0 output/capture input. \hideinitializer */
+#define SYS_GPG_MFPH_PG9MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG9MFP_EBI_AD0 (0x02UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< EBI address/data bus bit0. \hideinitializer */
+#define SYS_GPG_MFPH_PG9MFP_SD1_DAT3 (0x03UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< SD/SDIO 1 data line bit 3. \hideinitializer */
+#define SYS_GPG_MFPH_PG9MFP_SPIM_D2 (0x04UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< SPIM data 2 pin for Quad Mode I/O. \hideinitializer */
+#define SYS_GPG_MFPH_PG9MFP_BPWM0_CH5 (0x0CUL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< BPWM0 channel5 output/capture input. \hideinitializer */
+#define SYS_GPG_MFPH_PG10MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG10MFP_EBI_AD1 (0x02UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPG_MFPH_PG10MFP_SD1_DAT2 (0x03UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< SD/SDIO 1 data line bit 2. \hideinitializer */
+#define SYS_GPG_MFPH_PG10MFP_SPIM_D3 (0x04UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< SPIM data 3 pin for Quad Mode I/O. \hideinitializer */
+#define SYS_GPG_MFPH_PG10MFP_BPWM0_CH4 (0x0CUL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< BPWM0 channel4 output/capture input. \hideinitializer */
+#define SYS_GPG_MFPH_PG11MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG11MFP_EBI_AD2 (0x02UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< EBI address/data bus bit2. \hideinitializer */
+#define SYS_GPG_MFPH_PG11MFP_SD1_DAT1 (0x03UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< SD/SDIO 1 data line bit 1. \hideinitializer */
+#define SYS_GPG_MFPH_PG11MFP_SPIM_SS (0x04UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< 1st SPIM slave select pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG11MFP_BPWM0_CH3 (0x0CUL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< BPWM0 channel3 output/capture input. \hideinitializer */
+#define SYS_GPG_MFPH_PG12MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG12MFP_EBI_AD3 (0x02UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< EBI address/data bus bit3. \hideinitializer */
+#define SYS_GPG_MFPH_PG12MFP_SD1_DAT0 (0x03UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< SD/SDIO 1 data line bit 0. \hideinitializer */
+#define SYS_GPG_MFPH_PG12MFP_SPIM_CLK (0x04UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< SPIM serial clock pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG12MFP_BPWM0_CH2 (0x0CUL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< BPWM0 channel2 output/capture input. \hideinitializer */
+#define SYS_GPG_MFPH_PG13MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG13MFP_EBI_AD4 (0x02UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< EBI address/data bus bit4. \hideinitializer */
+#define SYS_GPG_MFPH_PG13MFP_SD1_CMD (0x03UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< SD/SDIO 1 command/response. \hideinitializer */
+#define SYS_GPG_MFPH_PG13MFP_SPIM_MISO (0x04UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< 1st SPIM MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG13MFP_BPWM0_CH1 (0x0CUL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< BPWM0 channel1 output/capture input. \hideinitializer */
+#define SYS_GPG_MFPH_PG14MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG14MFP_EBI_AD5 (0x02UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< EBI address/data bus bit5. \hideinitializer */
+#define SYS_GPG_MFPH_PG14MFP_SD1_CLK (0x03UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< SD/SDIO 1 clock. \hideinitializer */
+#define SYS_GPG_MFPH_PG14MFP_SPIM_MOSI (0x04UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< 1st SPIM MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG14MFP_BPWM0_CH0 (0x0CUL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< BPWM0 channel0 output/capture input. \hideinitializer */
+#define SYS_GPG_MFPH_PG15MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG15MFP_SD1_nCD (0x03UL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< SD/SDIO 1 card detect \hideinitializer */
+#define SYS_GPG_MFPH_PG15MFP_CLKO (0x0EUL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< Clock Output pin. \hideinitializer */
+#define SYS_GPG_MFPH_PG15MFP_EADC0_ST (0x0FUL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< EADC external trigger input. \hideinitializer */
+/********************* Bit definition of GPH_MFPL register **********************/
+#define SYS_GPH_MFPL_PH0MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH0MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH0MFP_EBI_ADR7 (0x02UL<<SYS_GPH_MFPL_PH0MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPH_MFPL_PH0MFP_UART5_TXD (0x04UL<<SYS_GPH_MFPL_PH0MFP_Pos) /*!< Data transmitter output pin for UART5. \hideinitializer */
+#define SYS_GPH_MFPL_PH0MFP_TM0_EXT (0x0DUL<<SYS_GPH_MFPL_PH0MFP_Pos) /*!< Timer0 event counter input / toggle output \hideinitializer */
+#define SYS_GPH_MFPL_PH1MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH1MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH1MFP_EBI_ADR6 (0x02UL<<SYS_GPH_MFPL_PH1MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPH_MFPL_PH1MFP_UART5_RXD (0x04UL<<SYS_GPH_MFPL_PH1MFP_Pos) /*!< Data receiver input pin for UART5. \hideinitializer */
+#define SYS_GPH_MFPL_PH1MFP_TM1_EXT (0x0DUL<<SYS_GPH_MFPL_PH1MFP_Pos) /*!< Timer1 event counter input / toggle output \hideinitializer */
+#define SYS_GPH_MFPL_PH2MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH2MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH2MFP_EBI_ADR5 (0x02UL<<SYS_GPH_MFPL_PH2MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPH_MFPL_PH2MFP_UART5_nRTS (0x04UL<<SYS_GPH_MFPL_PH2MFP_Pos) /*!< Request to Send output pin for UART5. \hideinitializer */
+#define SYS_GPH_MFPL_PH2MFP_UART4_TXD (0x05UL<<SYS_GPH_MFPL_PH2MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */
+#define SYS_GPH_MFPL_PH2MFP_I2C0_SCL (0x06UL<<SYS_GPH_MFPL_PH2MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH2MFP_TM2_EXT (0x0DUL<<SYS_GPH_MFPL_PH2MFP_Pos) /*!< Timer2 event counter input / toggle output \hideinitializer */
+#define SYS_GPH_MFPL_PH3MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH3MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH3MFP_EBI_ADR4 (0x02UL<<SYS_GPH_MFPL_PH3MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPH_MFPL_PH3MFP_SPI1_I2SMCLK (0x03UL<<SYS_GPH_MFPL_PH3MFP_Pos) /*!< SPI1 I2S master clock output pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH3MFP_UART5_nCTS (0x04UL<<SYS_GPH_MFPL_PH3MFP_Pos) /*!< Clear to Send input pin for UART5. \hideinitializer */
+#define SYS_GPH_MFPL_PH3MFP_UART4_RXD (0x05UL<<SYS_GPH_MFPL_PH3MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */
+#define SYS_GPH_MFPL_PH3MFP_I2C0_SDA (0x06UL<<SYS_GPH_MFPL_PH3MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH3MFP_TM3_EXT (0x0DUL<<SYS_GPH_MFPL_PH3MFP_Pos) /*!< Timer3 event counter input / toggle output \hideinitializer */
+#define SYS_GPH_MFPL_PH4MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH4MFP_EBI_ADR3 (0x02UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPH_MFPL_PH4MFP_SPI1_MISO (0x03UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH5MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH5MFP_EBI_ADR2 (0x02UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPH_MFPL_PH5MFP_SPI1_MOSI (0x03UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH6MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH6MFP_EBI_ADR1 (0x02UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPH_MFPL_PH6MFP_SPI1_CLK (0x03UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< SPI1 serial clock pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH7MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPH_MFPL_PH7MFP_EBI_ADR0 (0x02UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
+#define SYS_GPH_MFPL_PH7MFP_SPI1_SS (0x03UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< 1st SPI1 slave select pin. \hideinitializer */
+/********************* Bit definition of GPH_MFPH register **********************/
+#define SYS_GPH_MFPH_PH8MFP_GPIO (0x00UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH8MFP_EBI_AD12 (0x02UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPH_MFPH_PH8MFP_QSPI0_CLK (0x03UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< QSPI0 serial clock pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH8MFP_SC2_PWR (0x04UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< SmartCard2 power pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH8MFP_I2S0_DI (0x05UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< I2S0 data input. \hideinitializer */
+#define SYS_GPH_MFPH_PH8MFP_SPI1_CLK (0x06UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< SPI1 serial clock pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH8MFP_UART3_nRTS (0x07UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< Request to Send output pin for UART3. \hideinitializer */
+#define SYS_GPH_MFPH_PH8MFP_I2C1_SMBAL (0x08UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< I2C1 SMBus SMBALTER# pin \hideinitializer */
+#define SYS_GPH_MFPH_PH8MFP_I2C2_SCL (0x09UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH8MFP_UART1_TXD (0x0AUL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */
+#define SYS_GPH_MFPH_PH9MFP_GPIO (0x00UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH9MFP_EBI_AD13 (0x02UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPH_MFPH_PH9MFP_QSPI0_SS (0x03UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< 1st QSPI0 slave select pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH9MFP_SC2_RST (0x04UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< SmartCard2 reset pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH9MFP_I2S0_DO (0x05UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< I2S0 data output. \hideinitializer */
+#define SYS_GPH_MFPH_PH9MFP_SPI1_SS (0x06UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< 1st SPI1 slave select pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH9MFP_UART3_nCTS (0x07UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< Clear to Send input pin for UART3. \hideinitializer */
+#define SYS_GPH_MFPH_PH9MFP_I2C1_SMBSUS (0x08UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin) \hideinitializer */
+#define SYS_GPH_MFPH_PH9MFP_I2C2_SDA (0x09UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH9MFP_UART1_RXD (0x0AUL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */
+#define SYS_GPH_MFPH_PH10MFP_GPIO (0x00UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH10MFP_EBI_AD14 (0x02UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPH_MFPH_PH10MFP_QSPI0_MISO1 (0x03UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< 2nd QSPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH10MFP_SC2_nCD (0x04UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< SmartCard2 card detect pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH10MFP_I2S0_LRCK (0x05UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< I2S0 left right channel clock. \hideinitializer */
+#define SYS_GPH_MFPH_PH10MFP_SPI1_I2SMCLK (0x06UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< SPI1 I2S master clock output pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH10MFP_UART4_TXD (0x07UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */
+#define SYS_GPH_MFPH_PH10MFP_UART0_TXD (0x08UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
+#define SYS_GPH_MFPH_PH11MFP_GPIO (0x00UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH11MFP_EBI_AD15 (0x02UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
+#define SYS_GPH_MFPH_PH11MFP_QSPI0_MOSI1 (0x03UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< 2nd QSPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
+#define SYS_GPH_MFPH_PH11MFP_UART4_RXD (0x07UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */
+#define SYS_GPH_MFPH_PH11MFP_UART0_RXD (0x08UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
+#define SYS_GPH_MFPH_PH11MFP_EPWM0_CH5 (0x0BUL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< EPWM0 channel5 output/capture input. \hideinitializer */
+
+/*@}*/ /* end of group SYS_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions
+ @{
+*/
+
+
+/**
+ * @brief Clear Brown-out detector interrupt flag
+ * @param None
+ * @return None
+ * @details This macro clear Brown-out detector interrupt flag.
+ * \hideinitializer
+ */
+#define SYS_CLEAR_BOD_INT_FLAG() (SYS->BODCTL |= SYS_BODCTL_BODIF_Msk)
+
+/**
+ * @brief Set Brown-out detector function to normal mode
+ * @param None
+ * @return None
+ * @details This macro set Brown-out detector to normal mode.
+ * The register write-protection function should be disabled before using this macro.
+ * \hideinitializer
+ */
+#define SYS_CLEAR_BOD_LPM() (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk)
+
+/**
+ * @brief Disable Brown-out detector function
+ * @param None
+ * @return None
+ * @details This macro disable Brown-out detector function.
+ * The register write-protection function should be disabled before using this macro.
+ * \hideinitializer
+ */
+#define SYS_DISABLE_BOD() (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk)
+
+/**
+ * @brief Enable Brown-out detector function
+ * @param None
+ * @return None
+ * @details This macro enable Brown-out detector function.
+ * The register write-protection function should be disabled before using this macro.
+ * \hideinitializer
+ */
+#define SYS_ENABLE_BOD() (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk)
+
+/**
+ * @brief Get Brown-out detector interrupt flag
+ * @param None
+ * @retval 0 Brown-out detect interrupt flag is not set.
+ * @retval >=1 Brown-out detect interrupt flag is set.
+ * @details This macro get Brown-out detector interrupt flag.
+ * \hideinitializer
+ */
+#define SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODIF_Msk)
+
+/**
+ * @brief Get Brown-out detector status
+ * @param None
+ * @retval 0 System voltage is higher than BOD threshold voltage setting or BOD function is disabled.
+ * @retval >=1 System voltage is lower than BOD threshold voltage setting.
+ * @details This macro get Brown-out detector output status.
+ * If the BOD function is disabled, this function always return 0.
+ * \hideinitializer
+ */
+#define SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk)
+
+/**
+ * @brief Enable Brown-out detector interrupt function
+ * @param None
+ * @return None
+ * @details This macro enable Brown-out detector interrupt function.
+ * The register write-protection function should be disabled before using this macro.
+ * \hideinitializer
+ */
+#define SYS_DISABLE_BOD_RST() (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk)
+
+/**
+ * @brief Enable Brown-out detector reset function
+ * @param None
+ * @return None
+ * @details This macro enable Brown-out detect reset function.
+ * The register write-protection function should be disabled before using this macro.
+ * \hideinitializer
+ */
+#define SYS_ENABLE_BOD_RST() (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk)
+
+/**
+ * @brief Set Brown-out detector function low power mode
+ * @param None
+ * @return None
+ * @details This macro set Brown-out detector to low power mode.
+ * The register write-protection function should be disabled before using this macro.
+ * \hideinitializer
+ */
+#define SYS_SET_BOD_LPM() (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk)
+
+/**
+ * @brief Set Brown-out detector voltage level
+ * @param[in] u32Level is Brown-out voltage level. Including :
+ * - \ref SYS_BODCTL_BODVL_3_0V
+ * - \ref SYS_BODCTL_BODVL_2_8V
+ * - \ref SYS_BODCTL_BODVL_2_6V
+ * - \ref SYS_BODCTL_BODVL_2_4V
+ * - \ref SYS_BODCTL_BODVL_2_2V
+ * - \ref SYS_BODCTL_BODVL_2_0V
+ * - \ref SYS_BODCTL_BODVL_1_8V
+ * - \ref SYS_BODCTL_BODVL_1_6V
+ * @return None
+ * @details This macro set Brown-out detector voltage level.
+ * The write-protection function should be disabled before using this macro.
+ * \hideinitializer
+ */
+#define SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level))
+
+/**
+ * @brief Get reset source is from Brown-out detector reset
+ * @param None
+ * @retval 0 Previous reset source is not from Brown-out detector reset
+ * @retval >=1 Previous reset source is from Brown-out detector reset
+ * @details This macro get previous reset source is from Brown-out detect reset or not.
+ * \hideinitializer
+ */
+#define SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk)
+
+/**
+ * @brief Get reset source is from CPU reset
+ * @param None
+ * @retval 0 Previous reset source is not from CPU reset
+ * @retval >=1 Previous reset source is from CPU reset
+ * @details This macro get previous reset source is from CPU reset.
+ * \hideinitializer
+ */
+#define SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk)
+
+/**
+ * @brief Get reset source is from LVR Reset
+ * @param None
+ * @retval 0 Previous reset source is not from Low-Voltage-Reset
+ * @retval >=1 Previous reset source is from Low-Voltage-Reset
+ * @details This macro get previous reset source is from Low-Voltage-Reset.
+ * \hideinitializer
+ */
+#define SYS_IS_LVR_RST() (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk)
+
+/**
+ * @brief Get reset source is from Power-on Reset
+ * @param None
+ * @retval 0 Previous reset source is not from Power-on Reset
+ * @retval >=1 Previous reset source is from Power-on Reset
+ * @details This macro get previous reset source is from Power-on Reset.
+ * \hideinitializer
+ */
+#define SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk)
+
+/**
+ * @brief Get reset source is from reset pin reset
+ * @param None
+ * @retval 0 Previous reset source is not from reset pin reset
+ * @retval >=1 Previous reset source is from reset pin reset
+ * @details This macro get previous reset source is from reset pin reset.
+ * \hideinitializer
+ */
+#define SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk)
+
+/**
+ * @brief Get reset source is from system reset
+ * @param None
+ * @retval 0 Previous reset source is not from system reset
+ * @retval >=1 Previous reset source is from system reset
+ * @details This macro get previous reset source is from system reset.
+ * \hideinitializer
+ */
+#define SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk)
+
+/**
+ * @brief Get reset source is from window watch dog reset
+ * @param None
+ * @retval 0 Previous reset source is not from window watch dog reset
+ * @retval >=1 Previous reset source is from window watch dog reset
+ * @details This macro get previous reset source is from window watch dog reset.
+ * \hideinitializer
+ */
+#define SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk)
+
+/**
+ * @brief Disable Low-Voltage-Reset function
+ * @param None
+ * @return None
+ * @details This macro disable Low-Voltage-Reset function.
+ * The register write-protection function should be disabled before using this macro.
+ * \hideinitializer
+ */
+#define SYS_DISABLE_LVR() (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk)
+
+/**
+ * @brief Enable Low-Voltage-Reset function
+ * @param None
+ * @return None
+ * @details This macro enable Low-Voltage-Reset function.
+ * The register write-protection function should be disabled before using this macro.
+ * \hideinitializer
+ */
+#define SYS_ENABLE_LVR() (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk)
+
+/**
+ * @brief Disable Power-on Reset function
+ * @param None
+ * @return None
+ * @details This macro disable Power-on Reset function.
+ * The register write-protection function should be disabled before using this macro.
+ * \hideinitializer
+ */
+#define SYS_DISABLE_POR() (SYS->PORCTL = 0x5AA5)
+
+/**
+ * @brief Enable Power-on Reset function
+ * @param None
+ * @return None
+ * @details This macro enable Power-on Reset function.
+ * The register write-protection function should be disabled before using this macro.
+ * \hideinitializer
+ */
+#define SYS_ENABLE_POR() (SYS->PORCTL = 0)
+
+/**
+ * @brief Clear reset source flag
+ * @param[in] u32RstSrc is reset source. Including :
+ * - \ref SYS_RSTSTS_PORF_Msk
+ * - \ref SYS_RSTSTS_PINRF_Msk
+ * - \ref SYS_RSTSTS_WDTRF_Msk
+ * - \ref SYS_RSTSTS_LVRF_Msk
+ * - \ref SYS_RSTSTS_BODRF_Msk
+ * - \ref SYS_RSTSTS_SYSRF_Msk
+ * - \ref SYS_RSTSTS_CPURF_Msk
+ * - \ref SYS_RSTSTS_CPULKRF_Msk
+ * @return None
+ * @details This macro clear reset source flag.
+ * \hideinitializer
+ */
+#define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) )
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* static inline functions */
+/*---------------------------------------------------------------------------------------------------------*/
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+__STATIC_INLINE void SYS_UnlockReg(void);
+__STATIC_INLINE void SYS_LockReg(void);
+
+/**
+ * @brief Disable register write-protection function
+ * @param None
+ * @return None
+ * @details This function disable register write-protection function.
+ * To unlock the protected register to allow write access.
+ */
+__STATIC_INLINE void SYS_UnlockReg(void)
+{
+ do {
+ SYS->REGLCTL = 0x59UL;
+ SYS->REGLCTL = 0x16UL;
+ SYS->REGLCTL = 0x88UL;
+ } while (SYS->REGLCTL == 0UL);
+}
+
+/**
+ * @brief Enable register write-protection function
+ * @param None
+ * @return None
+ * @details This function is used to enable register write-protection function.
+ * To lock the protected register to forbid write access.
+ */
+__STATIC_INLINE void SYS_LockReg(void)
+{
+ SYS->REGLCTL = 0UL;
+}
+
+
+void SYS_ClearResetSrc(uint32_t u32Src);
+uint32_t SYS_GetBODStatus(void);
+uint32_t SYS_GetResetSrc(void);
+uint32_t SYS_IsRegLocked(void);
+uint32_t SYS_ReadPDID(void);
+void SYS_ResetChip(void);
+void SYS_ResetCPU(void);
+void SYS_ResetModule(uint32_t u32ModuleIndex);
+void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel);
+void SYS_DisableBOD(void);
+void SYS_SetPowerLevel(uint32_t u32PowerLevel);
+
+
+/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SYS_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYS_H__ */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/StdDriver/inc/m480_uart.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/StdDriver/inc/m480_uart.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,501 @@
+/**************************************************************************//**
+ * @file uart.h
+ * @version V3.00
+ * @brief M480 series UART driver header file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************/
+#ifndef __UART_H__
+#define __UART_H__
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup UART_Driver UART Driver
+ @{
+*/
+
+/** @addtogroup UART_EXPORTED_CONSTANTS UART Exported Constants
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART FIFO size constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+
+#define UART0_FIFO_SIZE 16ul /*!< UART0 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */
+#define UART1_FIFO_SIZE 16ul /*!< UART1 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */
+#define UART2_FIFO_SIZE 16ul /*!< UART2 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */
+#define UART3_FIFO_SIZE 16ul /*!< UART3 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */
+#define UART4_FIFO_SIZE 16ul /*!< UART3 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */
+#define UART5_FIFO_SIZE 16ul /*!< UART3 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART_FIFO constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+
+#define UART_FIFO_RFITL_1BYTE (0x0ul << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 1 byte \hideinitializer */
+#define UART_FIFO_RFITL_4BYTES (0x1ul << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 4 bytes \hideinitializer */
+#define UART_FIFO_RFITL_8BYTES (0x2ul << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 8 bytes \hideinitializer */
+#define UART_FIFO_RFITL_14BYTES (0x3ul << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 14 bytes \hideinitializer */
+
+#define UART_FIFO_RTSTRGLV_1BYTE (0x0ul << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 1 byte \hideinitializer */
+#define UART_FIFO_RTSTRGLV_4BYTES (0x1ul << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 4 bytes \hideinitializer */
+#define UART_FIFO_RTSTRGLV_8BYTES (0x2ul << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 8 bytes \hideinitializer */
+#define UART_FIFO_RTSTRGLV_14BYTES (0x3ul << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 14 bytes \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART_LINE constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_WORD_LEN_5 (0ul) /*!< UART_LINE setting to set UART word length to 5 bits \hideinitializer */
+#define UART_WORD_LEN_6 (1ul) /*!< UART_LINE setting to set UART word length to 6 bits \hideinitializer */
+#define UART_WORD_LEN_7 (2ul) /*!< UART_LINE setting to set UART word length to 7 bits \hideinitializer */
+#define UART_WORD_LEN_8 (3ul) /*!< UART_LINE setting to set UART word length to 8 bits \hideinitializer */
+
+#define _UART_PARITY_NONE (0x0ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as no parity \hideinitializer */
+#define _UART_PARITY_ODD (0x1ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as odd parity \hideinitializer */
+#define _UART_PARITY_EVEN (0x3ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as even parity \hideinitializer */
+#define _UART_PARITY_MARK (0x5ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '1' \hideinitializer */
+#define _UART_PARITY_SPACE (0x7ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '0' \hideinitializer */
+
+#define UART_STOP_BIT_1 (0x0ul << UART_LINE_NSB_Pos) /*!< UART_LINE setting for one stop bit \hideinitializer */
+#define UART_STOP_BIT_1_5 (0x1ul << UART_LINE_NSB_Pos) /*!< UART_LINE setting for 1.5 stop bit when 5-bit word length \hideinitializer */
+#define UART_STOP_BIT_2 (0x1ul << UART_LINE_NSB_Pos) /*!< UART_LINE setting for two stop bit when 6, 7, 8-bit word length \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART RTS ACTIVE LEVEL constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_RTS_IS_LOW_LEV_ACTIVE (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is Low Level Active \hideinitializer */
+#define UART_RTS_IS_HIGH_LEV_ACTIVE (0x0ul << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is High Level Active \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART_IRDA constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_IRDA_TXEN (0x1ul << UART_IRDA_TXEN_Pos) /*!< Set IrDA function Tx mode \hideinitializer */
+#define UART_IRDA_RXEN (0x0ul << UART_IRDA_TXEN_Pos) /*!< Set IrDA function Rx mode \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART_FUNCSEL constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_FUNCSEL_UART (0x0ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set UART Function (Default) \hideinitializer */
+#define UART_FUNCSEL_LIN (0x1ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set LIN Function \hideinitializer */
+#define UART_FUNCSEL_IrDA (0x2ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set IrDA Function \hideinitializer */
+#define UART_FUNCSEL_RS485 (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set RS485 Function \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART_LINCTL constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_LINCTL_BRKFL(x) (((x)-1) << UART_LINCTL_BRKFL_Pos) /*!< UART_LINCTL setting to set LIN Break Field Length, x = 10 ~ 15, default value is 12 \hideinitializer */
+#define UART_LINCTL_BSL(x) (((x)-1) << UART_LINCTL_BSL_Pos) /*!< UART_LINCTL setting to set LIN Break/Sync Delimiter Length, x = 1 ~ 4 \hideinitializer */
+#define UART_LINCTL_HSEL_BREAK (0x0UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field \hideinitializer */
+#define UART_LINCTL_HSEL_BREAK_SYNC (0x1UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field and sync field \hideinitializer */
+#define UART_LINCTL_HSEL_BREAK_SYNC_ID (0x2UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field, sync field and ID field \hideinitializer */
+#define UART_LINCTL_PID(x) ((x) << UART_LINCTL_PID_Pos) /*!< UART_LINCTL setting to set LIN PID value \hideinitializer */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART BAUDRATE MODE constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_BAUD_MODE0 (0ul) /*!< Set UART Baudrate Mode is Mode0 \hideinitializer */
+#define UART_BAUD_MODE2 (UART_BAUD_BAUDM1_Msk | UART_BAUD_BAUDM0_Msk) /*!< Set UART Baudrate Mode is Mode2 \hideinitializer */
+
+
+/*@}*/ /* end of group UART_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions
+ @{
+*/
+
+
+/**
+ * @brief Calculate UART baudrate mode0 divider
+ *
+ * @param[in] u32SrcFreq UART clock frequency
+ * @param[in] u32BaudRate Baudrate of UART module
+ *
+ * @return UART baudrate mode0 divider
+ *
+ * @details This macro calculate UART baudrate mode0 divider.
+ * \hideinitializer
+ */
+#define UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)*8ul)) / (u32BaudRate) >> 4ul)-2ul)
+
+
+/**
+ * @brief Calculate UART baudrate mode2 divider
+ *
+ * @param[in] u32SrcFreq UART clock frequency
+ * @param[in] u32BaudRate Baudrate of UART module
+ *
+ * @return UART baudrate mode2 divider
+ *
+ * @details This macro calculate UART baudrate mode2 divider.
+ * \hideinitializer
+ */
+#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)/2ul)) / (u32BaudRate))-2ul)
+
+
+/**
+ * @brief Write UART data
+ *
+ * @param[in] uart The pointer of the specified UART module
+ * @param[in] u8Data Data byte to transmit.
+ *
+ * @return None
+ *
+ * @details This macro write Data to Tx data register.
+ * \hideinitializer
+ */
+#define UART_WRITE(uart, u8Data) ((uart)->DAT = (u8Data))
+
+
+/**
+ * @brief Read UART data
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @return The oldest data byte in RX FIFO.
+ *
+ * @details This macro read Rx data register.
+ * \hideinitializer
+ */
+#define UART_READ(uart) ((uart)->DAT)
+
+
+/**
+ * @brief Get Tx empty
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 0 Tx FIFO is not empty
+ * @retval >=1 Tx FIFO is empty
+ *
+ * @details This macro get Transmitter FIFO empty register value.
+ * \hideinitializer
+ */
+#define UART_GET_TX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTY_Msk)
+
+
+/**
+ * @brief Get Rx empty
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 0 Rx FIFO is not empty
+ * @retval >=1 Rx FIFO is empty
+ *
+ * @details This macro get Receiver FIFO empty register value.
+ * \hideinitializer
+ */
+#define UART_GET_RX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)
+
+
+/**
+ * @brief Check specified UART port transmission is over.
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 0 Tx transmission is not over
+ * @retval 1 Tx transmission is over
+ *
+ * @details This macro return Transmitter Empty Flag register bit value.
+ * It indicates if specified UART port transmission is over nor not.
+ * \hideinitializer
+ */
+#define UART_IS_TX_EMPTY(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)
+
+
+/**
+ * @brief Wait specified UART port transmission is over
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @return None
+ *
+ * @details This macro wait specified UART port transmission is over.
+ * \hideinitializer
+ */
+#define UART_WAIT_TX_EMPTY(uart) while(!((((uart)->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos))
+
+
+/**
+ * @brief Check RX is ready or not
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 0 The number of bytes in the RX FIFO is less than the RFITL
+ * @retval 1 The number of bytes in the RX FIFO equals or larger than RFITL
+ *
+ * @details This macro check receive data available interrupt flag is set or not.
+ * \hideinitializer
+ */
+#define UART_IS_RX_READY(uart) (((uart)->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos)
+
+
+/**
+ * @brief Check TX FIFO is full or not
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 1 TX FIFO is full
+ * @retval 0 TX FIFO is not full
+ *
+ * @details This macro check TX FIFO is full or not.
+ * \hideinitializer
+ */
+#define UART_IS_TX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos)
+
+
+/**
+ * @brief Check RX FIFO is full or not
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 1 RX FIFO is full
+ * @retval 0 RX FIFO is not full
+ *
+ * @details This macro check RX FIFO is full or not.
+ * \hideinitializer
+ */
+#define UART_IS_RX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos)
+
+
+/**
+ * @brief Get Tx full register value
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 0 Tx FIFO is not full.
+ * @retval >=1 Tx FIFO is full.
+ *
+ * @details This macro get Tx full register value.
+ * \hideinitializer
+ */
+#define UART_GET_TX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)
+
+
+/**
+ * @brief Get Rx full register value
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 0 Rx FIFO is not full.
+ * @retval >=1 Rx FIFO is full.
+ *
+ * @details This macro get Rx full register value.
+ * \hideinitializer
+ */
+#define UART_GET_RX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)
+
+
+/**
+ * @brief Enable specified UART interrupt
+ *
+ * @param[in] uart The pointer of the specified UART module
+ * @param[in] u32eIntSel Interrupt type select
+ * - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt
+ * - \ref UART_INTEN_WKIEN_Msk : Wakeup interrupt
+ * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt
+ * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
+ * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
+ * - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt
+ * - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt
+ * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
+ * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
+ *
+ * @return None
+ *
+ * @details This macro enable specified UART interrupt.
+ * \hideinitializer
+ */
+#define UART_ENABLE_INT(uart, u32eIntSel) ((uart)->INTEN |= (u32eIntSel))
+
+
+/**
+ * @brief Disable specified UART interrupt
+ *
+ * @param[in] uart The pointer of the specified UART module
+ * @param[in] u32eIntSel Interrupt type select
+ * - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt
+ * - \ref UART_INTEN_WKIEN_Msk : Wakeup interrupt
+ * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt
+ * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
+ * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
+ * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt
+ * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt
+ * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
+ * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
+ *
+ * @return None
+ *
+ * @details This macro enable specified UART interrupt.
+ * \hideinitializer
+ */
+#define UART_DISABLE_INT(uart, u32eIntSel) ((uart)->INTEN &= ~ (u32eIntSel))
+
+
+/**
+ * @brief Get specified interrupt flag/status
+ *
+ * @param[in] uart The pointer of the specified UART module
+ * @param[in] u32eIntTypeFlag Interrupt Type Flag, should be
+ * - \ref UART_INTSTS_HWBUFEINT_Msk : In DMA Mode, Buffer Error Interrupt Indicator
+ * - \ref UART_INTSTS_HWTOINT_Msk : In DMA Mode, Time-out Interrupt Indicator
+ * - \ref UART_INTSTS_HWMODINT_Msk : In DMA Mode, MODEM Status Interrupt Indicator
+ * - \ref UART_INTSTS_HWRLSINT_Msk : In DMA Mode, Receive Line Status Interrupt Indicator
+ * - \ref UART_INTSTS_HWBUFEIF_Msk : In DMA Mode, Buffer Error Interrupt Flag
+ * - \ref UART_INTSTS_HWTOIF_Msk : In DMA Mode, Time-out Interrupt Flag
+ * - \ref UART_INTSTS_HWMODIF_Msk : In DMA Mode, MODEM Interrupt Flag
+ * - \ref UART_INTSTS_HWRLSIF_Msk : In DMA Mode, Receive Line Status Flag
+ * - \ref UART_INTSTS_LININT_Msk : LIN Bus Interrupt Indicator
+ * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error Interrupt Indicator
+ * - \ref UART_INTSTS_RXTOINT_Msk : Time-out Interrupt Indicator
+ * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status Interrupt Indicator
+ * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status Interrupt Indicator
+ * - \ref UART_INTSTS_THREINT_Msk : Transmit Holding Register Empty Interrupt Indicator
+ * - \ref UART_INTSTS_RDAINT_Msk : Receive Data Available Interrupt Indicator
+ * - \ref UART_INTSTS_LINIF_Msk : LIN Bus Flag
+ * - \ref UART_INTSTS_BUFERRIF_Msk : Buffer Error Interrupt Flag
+ * - \ref UART_INTSTS_RXTOIF_Msk : Rx Time-out Interrupt Flag
+ * - \ref UART_INTSTS_MODEMIF_Msk : Modem Interrupt Flag
+ * - \ref UART_INTSTS_RLSIF_Msk : Receive Line Status Interrupt Flag
+ * - \ref UART_INTSTS_THREIF_Msk : Tx Empty Interrupt Flag
+ * - \ref UART_INTSTS_RDAIF_Msk : Rx Ready Interrupt Flag
+ *
+ * @retval 0 The specified interrupt is not happened.
+ * 1 The specified interrupt is happened.
+ *
+ * @details This macro get specified interrupt flag or interrupt indicator status.
+ * \hideinitializer
+ */
+#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) (((uart)->INTSTS & (u32eIntTypeFlag))?1:0)
+
+
+/**
+ * @brief Clear RS-485 Address Byte Detection Flag
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @return None
+ *
+ * @details This macro clear RS-485 address byte detection flag.
+ * \hideinitializer
+ */
+#define UART_RS485_CLEAR_ADDR_FLAG(uart) ((uart)->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk)
+
+
+/**
+ * @brief Get RS-485 Address Byte Detection Flag
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 0 Receiver detects a data that is not an address bit.
+ * @retval 1 Receiver detects a data that is an address bit.
+ *
+ * @details This macro get RS-485 address byte detection flag.
+ * \hideinitializer
+ */
+#define UART_RS485_GET_ADDR_FLAG(uart) (((uart)->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos)
+
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+__STATIC_INLINE void UART_CLEAR_RTS(UART_T *uart);
+__STATIC_INLINE void UART_SET_RTS(UART_T *uart);
+
+
+/**
+ * @brief Set RTS pin to low
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @return None
+ *
+ * @details This macro set RTS pin to low.
+ */
+__STATIC_INLINE void UART_CLEAR_RTS(UART_T *uart)
+{
+ uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
+ uart->MODEM &= ~UART_MODEM_RTS_Msk;
+}
+
+
+/**
+ * @brief Set RTS pin to high
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @return None
+ *
+ * @details This macro set RTS pin to high.
+ */
+__STATIC_INLINE void UART_SET_RTS(UART_T *uart)
+{
+ uart->MODEM |= UART_MODEM_RTSACTLV_Msk | UART_MODEM_RTS_Msk;
+}
+
+
+void UART_ClearIntFlag(UART_T *uart, uint32_t u32InterruptFlag);
+void UART_Close(UART_T *uart);
+void UART_DisableFlowCtrl(UART_T *uart);
+void UART_DisableInt(UART_T *uart, uint32_t u32InterruptFlag);
+void UART_EnableFlowCtrl(UART_T *uart);
+void UART_EnableInt(UART_T *uart, uint32_t u32InterruptFlag);
+void UART_Open(UART_T *uart, uint32_t u32baudrate);
+uint32_t UART_Read(UART_T *uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes);
+void UART_SetLineConfig(UART_T *uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits);
+void UART_SetTimeoutCnt(UART_T *uart, uint32_t u32TOC);
+void UART_SelectIrDAMode(UART_T *uart, uint32_t u32Buadrate, uint32_t u32Direction);
+void UART_SelectRS485Mode(UART_T *uart, uint32_t u32Mode, uint32_t u32Addr);
+void UART_SelectLINMode(UART_T *uart, uint32_t u32Mode, uint32_t u32BreakLength);
+uint32_t UART_Write(UART_T *uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes);
+
+
+
+
+/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group UART_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__UART_H__*/
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/StdDriver/src/m480_clk.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/StdDriver/src/m480_clk.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1114 @@
+/**************************************************************************//**
+ * @file clk.c
+ * @version V3.00
+ * @brief M480 series CLK driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/
+
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup CLK_Driver CLK Driver
+ @{
+*/
+
+/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions
+ @{
+*/
+
+/**
+ * @brief Disable clock divider output function
+ * @param None
+ * @return None
+ * @details This function disable clock divider output function.
+ */
+void CLK_DisableCKO(void)
+{
+ /* Disable CKO clock source */
+ CLK_DisableModuleClock(CLKO_MODULE);
+}
+
+/**
+ * @brief This function enable clock divider output module clock,
+ * enable clock divider output function and set frequency selection.
+ * @param[in] u32ClkSrc is frequency divider function clock source. Including :
+ * - \ref CLK_CLKSEL1_CLKOSEL_HXT
+ * - \ref CLK_CLKSEL1_CLKOSEL_LXT
+ * - \ref CLK_CLKSEL1_CLKOSEL_HCLK
+ * - \ref CLK_CLKSEL1_CLKOSEL_HIRC
+ * @param[in] u32ClkDiv is divider output frequency selection. It could be 0~15.
+ * @param[in] u32ClkDivBy1En is clock divided by one enabled.
+ * @return None
+ * @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. \n
+ * The formula is: \n
+ * CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) \n
+ * This function is just used to set CKO clock.
+ * User must enable I/O for CKO clock output pin by themselves. \n
+ */
+void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
+{
+ /* CKO = clock source / 2^(u32ClkDiv + 1) */
+ CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | (u32ClkDiv) | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos);
+ /* Enable CKO clock source */
+ CLK_EnableModuleClock(CLKO_MODULE);
+ /* Select CKO clock source */
+ CLK_SetModuleClock(CLKO_MODULE, u32ClkSrc, 0UL);
+}
+
+/**
+ * @brief Enter to Power-down mode
+ * @param None
+ * @return None
+ * @details This function is used to let system enter to Power-down mode. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+void CLK_PowerDown(void)
+{
+ uint32_t u32HIRCTRIMCTL;
+ /* Set the processor uses deep sleep as its low power mode */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+ /* Set system Power-down enabled */
+ CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk);
+ /* Store HIRC control register */
+ u32HIRCTRIMCTL = SYS->IRCTCTL;
+ /* Disable HIRC auto trim */
+ SYS->IRCTCTL &= (~SYS_IRCTCTL_FREQSEL_Msk);
+ /* Chip enter Power-down mode after CPU run WFI instruction */
+ __WFI();
+ /* Restore HIRC control register */
+ SYS->IRCTCTL = u32HIRCTRIMCTL;
+}
+
+/**
+ * @brief Enter to Idle mode
+ * @param None
+ * @return None
+ * @details This function let system enter to Idle mode. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+void CLK_Idle(void)
+{
+ /* Set the processor uses sleep as its low power mode */
+ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+ /* Set chip in idle mode because of WFI command */
+ CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk;
+ /* Chip enter idle mode after CPU run WFI instruction */
+ __WFI();
+}
+
+/**
+ * @brief Get external high speed crystal clock frequency
+ * @param None
+ * @return External high frequency crystal frequency
+ * @details This function get external high frequency crystal frequency. The frequency unit is Hz.
+ */
+uint32_t CLK_GetHXTFreq(void)
+{
+ uint32_t u32Freq;
+
+ if ((CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) == CLK_PWRCTL_HXTEN_Msk) {
+ u32Freq = __HXT;
+ } else {
+ u32Freq = 0UL;
+ }
+
+ return u32Freq;
+}
+
+
+/**
+ * @brief Get external low speed crystal clock frequency
+ * @param None
+ * @return External low speed crystal clock frequency
+ * @details This function get external low frequency crystal frequency. The frequency unit is Hz.
+ */
+uint32_t CLK_GetLXTFreq(void)
+{
+ uint32_t u32Freq;
+
+ if ((CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk) == CLK_PWRCTL_LXTEN_Msk) {
+ u32Freq = __LXT;
+ } else {
+ u32Freq = 0UL;
+ }
+
+ return u32Freq;
+}
+
+/**
+ * @brief Get PCLK0 frequency
+ * @param None
+ * @return PCLK0 frequency
+ * @details This function get PCLK0 frequency. The frequency unit is Hz.
+ */
+uint32_t CLK_GetPCLK0Freq(void)
+{
+ uint32_t u32Freq;
+ SystemCoreClockUpdate();
+
+ if ((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_PCLK0DIV1) {
+ u32Freq = SystemCoreClock;
+ } else if ((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_PCLK0DIV2) {
+ u32Freq = SystemCoreClock / 2UL;
+ } else if ((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_PCLK0DIV4) {
+ u32Freq = SystemCoreClock / 4UL;
+ } else if ((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_PCLK0DIV8) {
+ u32Freq = SystemCoreClock / 8UL;
+ } else if ((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_PCLK0DIV16) {
+ u32Freq = SystemCoreClock / 16UL;
+ } else {
+ u32Freq = SystemCoreClock;
+ }
+
+ return u32Freq;
+}
+
+
+/**
+ * @brief Get PCLK1 frequency
+ * @param None
+ * @return PCLK1 frequency
+ * @details This function get PCLK1 frequency. The frequency unit is Hz.
+ */
+uint32_t CLK_GetPCLK1Freq(void)
+{
+ uint32_t u32Freq;
+ SystemCoreClockUpdate();
+
+ if ((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_PCLK1DIV1) {
+ u32Freq = SystemCoreClock;
+ } else if ((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_PCLK1DIV2) {
+ u32Freq = SystemCoreClock / 2UL;
+ } else if ((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_PCLK1DIV4) {
+ u32Freq = SystemCoreClock / 4UL;
+ } else if ((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_PCLK1DIV8) {
+ u32Freq = SystemCoreClock / 8UL;
+ } else if ((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_PCLK1DIV16) {
+ u32Freq = SystemCoreClock / 16UL;
+ } else {
+ u32Freq = SystemCoreClock;
+ }
+
+ return u32Freq;
+}
+
+
+/**
+ * @brief Get HCLK frequency
+ * @param None
+ * @return HCLK frequency
+ * @details This function get HCLK frequency. The frequency unit is Hz.
+ */
+uint32_t CLK_GetHCLKFreq(void)
+{
+ SystemCoreClockUpdate();
+ return SystemCoreClock;
+}
+
+
+/**
+ * @brief Get CPU frequency
+ * @param None
+ * @return CPU frequency
+ * @details This function get CPU frequency. The frequency unit is Hz.
+ */
+uint32_t CLK_GetCPUFreq(void)
+{
+ SystemCoreClockUpdate();
+ return SystemCoreClock;
+}
+
+
+/**
+ * @brief Set HCLK frequency
+ * @param[in] u32Hclk is HCLK frequency. The range of u32Hclk is running up to 192MHz.
+ * @return HCLK frequency
+ * @details This function is used to set HCLK frequency. The frequency unit is Hz. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
+{
+ uint32_t u32HIRCSTB;
+ /* Read HIRC clock source stable flag */
+ u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
+
+ /* The range of u32Hclk is running up to 192 MHz */
+ if (u32Hclk > FREQ_192MHZ) {
+ u32Hclk = FREQ_192MHZ;
+ }
+
+ /* Switch HCLK clock source to HIRC clock for safe */
+ CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
+ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
+ CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk;
+ CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk);
+
+ /* Configure PLL setting if HXT clock is enabled */
+ if ((CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) == CLK_PWRCTL_HXTEN_Msk) {
+ u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, u32Hclk);
+ }
+ /* Configure PLL setting if HXT clock is not enabled */
+ else {
+ u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HIRC, u32Hclk);
+ /* Read HIRC clock source stable flag */
+ u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
+ }
+
+ /* Select HCLK clock source to PLL,
+ and update system core clock
+ */
+ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(1UL));
+
+ /* Disable HIRC if HIRC is disabled before setting core clock */
+ if (u32HIRCSTB == 0UL) {
+ CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
+ }
+
+ /* Return actually HCLK frequency is PLL frequency divide 1 */
+ return u32Hclk;
+}
+
+/**
+ * @brief This function set HCLK clock source and HCLK clock divider
+ * @param[in] u32ClkSrc is HCLK clock source. Including :
+ * - \ref CLK_CLKSEL0_HCLKSEL_HXT
+ * - \ref CLK_CLKSEL0_HCLKSEL_LXT
+ * - \ref CLK_CLKSEL0_HCLKSEL_PLL
+ * - \ref CLK_CLKSEL0_HCLKSEL_LIRC
+ * - \ref CLK_CLKSEL0_HCLKSEL_HIRC
+ * @param[in] u32ClkDiv is HCLK clock divider. Including :
+ * - \ref CLK_CLKDIV0_HCLK(x)
+ * @return None
+ * @details This function set HCLK clock source and HCLK clock divider. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
+{
+ uint32_t u32HIRCSTB;
+ /* Read HIRC clock source stable flag */
+ u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
+ /* Switch to HIRC for Safe. Avoid HCLK too high when applying new divider. */
+ CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
+ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
+ CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_HIRC;
+ /* Apply new Divider */
+ CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv;
+ /* Switch HCLK to new HCLK source */
+ CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc;
+ /* Update System Core Clock */
+ SystemCoreClockUpdate();
+
+ /* Disable HIRC if HIRC is disabled before switching HCLK source */
+ if (u32HIRCSTB == 0UL) {
+ CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
+ }
+}
+
+/**
+ * @brief This function set selected module clock source and module clock divider
+ * @param[in] u32ModuleIdx is module index.
+ * @param[in] u32ClkSrc is module clock source.
+ * @param[in] u32ClkDiv is module clock divider.
+ * @return None
+ * @details Valid parameter combinations listed in following table:
+ *
+ * |Module index |Clock source |Divider |
+ * | :---------------- | :----------------------------------- | :-------------------------- |
+ * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HXT |\ref CLK_CLKDIV0_SDH0(x) |
+ * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_PLL |\ref CLK_CLKDIV0_SDH0(x) |
+ * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HIRC |\ref CLK_CLKDIV0_SDH0(x) |
+ * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HCLK |\ref CLK_CLKDIV0_SDH0(x) |
+ * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_HXT |\ref CLK_CLKDIV3_SDH1(x) |
+ * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_PLL |\ref CLK_CLKDIV3_SDH1(x) |
+ * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_HIRC |\ref CLK_CLKDIV3_SDH1(x) |
+ * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_HCLK |\ref CLK_CLKDIV3_SDH1(x) |
+ * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LXT | x |
+ * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LIRC | x |
+ * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HXT | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LXT | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LIRC | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HIRC | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_PCLK0 | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_EXT | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HXT | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LXT | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LIRC | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HIRC | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_PCLK0 | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_EXT | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HXT | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LXT | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LIRC | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HIRC | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_PCLK1 | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_EXT | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HXT | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LXT | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LIRC | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HIRC | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_PCLK1 | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_EXT | x |
+ * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_HXT |\ref CLK_CLKDIV0_UART0(x) |
+ * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_LXT |\ref CLK_CLKDIV0_UART0(x) |
+ * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_PLL |\ref CLK_CLKDIV0_UART0(x) |
+ * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_HIRC |\ref CLK_CLKDIV0_UART0(x) |
+ * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_HXT |\ref CLK_CLKDIV0_UART1(x) |
+ * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_LXT |\ref CLK_CLKDIV0_UART1(x) |
+ * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_PLL |\ref CLK_CLKDIV0_UART1(x) |
+ * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_HIRC |\ref CLK_CLKDIV0_UART1(x) |
+ * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HXT | x |
+ * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LXT | x |
+ * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HIRC | x |
+ * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HCLK | x |
+ * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_LIRC | x |
+ * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 | x |
+ * |\ref EPWM0_MODULE |\ref CLK_CLKSEL2_EPWM0SEL_PLL | x |
+ * |\ref EPWM0_MODULE |\ref CLK_CLKSEL2_EPWM0SEL_PCLK0 | x |
+ * |\ref EPWM1_MODULE |\ref CLK_CLKSEL2_EPWM1SEL_PLL | x |
+ * |\ref EPWM1_MODULE |\ref CLK_CLKSEL2_EPWM1SEL_PCLK1 | x |
+ * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HXT | x |
+ * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PLL | x |
+ * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HIRC | x |
+ * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PCLK0 | x |
+ * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HXT | x |
+ * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PLL | x |
+ * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HIRC | x |
+ * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PCLK1 | x |
+ * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HXT | x |
+ * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PLL | x |
+ * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HIRC | x |
+ * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PCLK0 | x |
+ * |\ref BPWM0_MODULE |\ref CLK_CLKSEL2_BPWM0SEL_PLL | x |
+ * |\ref BPWM0_MODULE |\ref CLK_CLKSEL2_BPWM0SEL_PCLK0 | x |
+ * |\ref BPWM1_MODULE |\ref CLK_CLKSEL2_BPWM1SEL_PLL | x |
+ * |\ref BPWM1_MODULE |\ref CLK_CLKSEL2_BPWM1SEL_PCLK1 | x |
+ * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HXT | x |
+ * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PLL | x |
+ * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HIRC | x |
+ * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PCLK1 | x |
+ * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_HXT | x |
+ * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_PLL | x |
+ * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_HIRC | x |
+ * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_PCLK0 | x |
+ * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HXT |\ref CLK_CLKDIV1_SC0(x) |
+ * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PLL |\ref CLK_CLKDIV1_SC0(x) |
+ * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HIRC |\ref CLK_CLKDIV1_SC0(x) |
+ * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PCLK0 |\ref CLK_CLKDIV1_SC0(x) |
+ * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HXT |\ref CLK_CLKDIV1_SC1(x) |
+ * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PLL |\ref CLK_CLKDIV1_SC1(x) |
+ * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HIRC |\ref CLK_CLKDIV1_SC1(x) |
+ * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PCLK1 |\ref CLK_CLKDIV1_SC1(x) |
+ * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HXT |\ref CLK_CLKDIV1_SC2(x) |
+ * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PLL |\ref CLK_CLKDIV1_SC2(x) |
+ * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HIRC |\ref CLK_CLKDIV1_SC2(x) |
+ * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PCLK0 |\ref CLK_CLKDIV1_SC2(x) |
+ * |\ref RTC_MODULE |\ref CLK_CLKSEL3_RTCSEL_LXT | x |
+ * |\ref RTC_MODULE |\ref CLK_CLKSEL3_RTCSEL_LIRC | x |
+ * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HXT | x |
+ * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PLL | x |
+ * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HIRC | x |
+ * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_HXT |\ref CLK_CLKDIV4_UART2(x) |
+ * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_LXT |\ref CLK_CLKDIV4_UART2(x) |
+ * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_PLL |\ref CLK_CLKDIV4_UART2(x) |
+ * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_HIRC |\ref CLK_CLKDIV4_UART2(x) |
+ * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_HXT |\ref CLK_CLKDIV4_UART3(x) |
+ * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_LXT |\ref CLK_CLKDIV4_UART3(x) |
+ * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_PLL |\ref CLK_CLKDIV4_UART3(x) |
+ * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_HIRC |\ref CLK_CLKDIV4_UART3(x) |
+ * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HXT |\ref CLK_CLKDIV4_UART4(x) |
+ * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_LXT |\ref CLK_CLKDIV4_UART4(x) |
+ * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_PLL |\ref CLK_CLKDIV4_UART4(x) |
+ * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HIRC |\ref CLK_CLKDIV4_UART4(x) |
+ * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HXT |\ref CLK_CLKDIV4_UART5(x) |
+ * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_LXT |\ref CLK_CLKDIV4_UART5(x) |
+ * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_PLL |\ref CLK_CLKDIV4_UART5(x) |
+ * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HIRC |\ref CLK_CLKDIV4_UART5(x) |
+ * |\ref EADC_MODULE | x |\ref CLK_CLKDIV0_EADC(x) |
+ * |\ref EMAC_MODULE | x |\ref CLK_CLKDIV3_EMAC(x) |
+ *
+ */
+void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
+{
+ uint32_t u32sel = 0U, u32div = 0U;
+
+ if (MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk) {
+ /* Get clock divider control register address */
+ if (MODULE_CLKDIV(u32ModuleIdx) == 2U) {
+ u32div = (uint32_t)&CLK->CLKDIV3;
+ } else if (MODULE_CLKDIV(u32ModuleIdx) == 3U) {
+ u32div = (uint32_t)&CLK->CLKDIV4;
+ } else {
+ u32div = (uint32_t)&CLK->CLKDIV0 + ((MODULE_CLKDIV(u32ModuleIdx)) * 4U);
+ }
+
+ /* Apply new divider */
+ M32(u32div) = (M32(u32div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv;
+ }
+
+ if (MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk) {
+ /* Get clock select control register address */
+ u32sel = (uint32_t)&CLK->CLKSEL0 + ((MODULE_CLKSEL(u32ModuleIdx)) * 4U);
+ /* Set new clock selection setting */
+ M32(u32sel) = (M32(u32sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc;
+ }
+}
+
+/**
+ * @brief Set SysTick clock source
+ * @param[in] u32ClkSrc is module clock source. Including:
+ * - \ref CLK_CLKSEL0_STCLKSEL_HXT
+ * - \ref CLK_CLKSEL0_STCLKSEL_LXT
+ * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
+ * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
+ * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
+ * @return None
+ * @details This function set SysTick clock source. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
+{
+ CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
+}
+
+/**
+ * @brief Enable clock source
+ * @param[in] u32ClkMask is clock source mask. Including :
+ * - \ref CLK_PWRCTL_HXTEN_Msk
+ * - \ref CLK_PWRCTL_LXTEN_Msk
+ * - \ref CLK_PWRCTL_HIRCEN_Msk
+ * - \ref CLK_PWRCTL_LIRCEN_Msk
+ * @return None
+ * @details This function enable clock source. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+void CLK_EnableXtalRC(uint32_t u32ClkMask)
+{
+ CLK->PWRCTL |= u32ClkMask;
+}
+
+/**
+ * @brief Disable clock source
+ * @param[in] u32ClkMask is clock source mask. Including :
+ * - \ref CLK_PWRCTL_HXTEN_Msk
+ * - \ref CLK_PWRCTL_LXTEN_Msk
+ * - \ref CLK_PWRCTL_HIRCEN_Msk
+ * - \ref CLK_PWRCTL_LIRCEN_Msk
+ * @return None
+ * @details This function disable clock source. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+void CLK_DisableXtalRC(uint32_t u32ClkMask)
+{
+ CLK->PWRCTL &= ~u32ClkMask;
+}
+
+/**
+ * @brief Enable module clock
+ * @param[in] u32ModuleIdx is module index. Including :
+ * - \ref PDMA_MODULE
+ * - \ref ISP_MODULE
+ * - \ref EBI_MODULE
+ * - \ref EMAC_MODULE
+ * - \ref SDH0_MODULE
+ * - \ref CRC_MODULE
+ * - \ref HSUSBD_MODULE
+ * - \ref CRPT_MODULE
+ * - \ref SPIM_MODULE
+ * - \ref FMCIDLE_MODULE
+ * - \ref USBH_MODULE
+ * - \ref SDH1_MODULE
+ * - \ref WDT_MODULE
+ * - \ref RTC_MODULE
+ * - \ref TMR0_MODULE
+ * - \ref TMR1_MODULE
+ * - \ref TMR2_MODULE
+ * - \ref TMR3_MODULE
+ * - \ref CLKO_MODULE
+ * - \ref WWDT_MODULE
+ * - \ref ACMP01_MODULE
+ * - \ref I2C0_MODULE
+ * - \ref I2C1_MODULE
+ * - \ref I2C2_MODULE
+ * - \ref QSPI0_MODULE
+ * - \ref SPI0_MODULE
+ * - \ref SPI1_MODULE
+ * - \ref SPI2_MODULE
+ * - \ref UART0_MODULE
+ * - \ref UART1_MODULE
+ * - \ref UART2_MODULE
+ * - \ref UART3_MODULE
+ * - \ref UART4_MODULE
+ * - \ref UART5_MODULE
+ * - \ref CAN0_MODULE
+ * - \ref CAN1_MODULE
+ * - \ref OTG_MODULE
+ * - \ref USBD_MODULE
+ * - \ref EADC_MODULE
+ * - \ref I2S0_MODULE
+ * - \ref HSOTG_MODULE
+ * - \ref SC0_MODULE
+ * - \ref SC1_MODULE
+ * - \ref SC2_MODULE
+ * - \ref SPI3_MODULE
+ * - \ref USCI0_MODULE
+ * - \ref USCI1_MODULE
+ * - \ref DAC_MODULE
+ * - \ref EPWM0_MODULE
+ * - \ref EPWM1_MODULE
+ * - \ref BPWM0_MODULE
+ * - \ref BPWM1_MODULE
+ * - \ref QEI0_MODULE
+ * - \ref QEI1_MODULE
+ * - \ref ECAP0_MODULE
+ * - \ref ECAP1_MODULE
+ * - \ref OPA_MODULE
+ * @return None
+ * @details This function is used to enable module clock.
+ */
+void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
+{
+ uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL;
+ u32tmpVal = (1UL << MODULE_IP_EN_Pos(u32ModuleIdx));
+ u32tmpAddr = (uint32_t)&CLK->AHBCLK;
+ u32tmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL));
+ *(volatile uint32_t *)u32tmpAddr |= u32tmpVal;
+}
+
+/**
+ * @brief Disable module clock
+ * @param[in] u32ModuleIdx is module index. Including :
+ * - \ref PDMA_MODULE
+ * - \ref ISP_MODULE
+ * - \ref EBI_MODULE
+ * - \ref EMAC_MODULE
+ * - \ref SDH0_MODULE
+ * - \ref CRC_MODULE
+ * - \ref HSUSBD_MODULE
+ * - \ref CRPT_MODULE
+ * - \ref SPIM_MODULE
+ * - \ref FMCIDLE_MODULE
+ * - \ref USBH_MODULE
+ * - \ref SDH1_MODULE
+ * - \ref WDT_MODULE
+ * - \ref RTC_MODULE
+ * - \ref TMR0_MODULE
+ * - \ref TMR1_MODULE
+ * - \ref TMR2_MODULE
+ * - \ref TMR3_MODULE
+ * - \ref CLKO_MODULE
+ * - \ref WWDT_MODULE
+ * - \ref ACMP01_MODULE
+ * - \ref I2C0_MODULE
+ * - \ref I2C1_MODULE
+ * - \ref I2C2_MODULE
+ * - \ref QSPI0_MODULE
+ * - \ref SPI0_MODULE
+ * - \ref SPI1_MODULE
+ * - \ref SPI2_MODULE
+ * - \ref UART0_MODULE
+ * - \ref UART1_MODULE
+ * - \ref UART2_MODULE
+ * - \ref UART3_MODULE
+ * - \ref UART4_MODULE
+ * - \ref UART5_MODULE
+ * - \ref CAN0_MODULE
+ * - \ref CAN1_MODULE
+ * - \ref OTG_MODULE
+ * - \ref USBD_MODULE
+ * - \ref EADC_MODULE
+ * - \ref I2S0_MODULE
+ * - \ref HSOTG_MODULE
+ * - \ref SC0_MODULE
+ * - \ref SC1_MODULE
+ * - \ref SC2_MODULE
+ * - \ref SPI3_MODULE
+ * - \ref USCI0_MODULE
+ * - \ref USCI1_MODULE
+ * - \ref DAC_MODULE
+ * - \ref EPWM0_MODULE
+ * - \ref EPWM1_MODULE
+ * - \ref BPWM0_MODULE
+ * - \ref BPWM1_MODULE
+ * - \ref QEI0_MODULE
+ * - \ref QEI1_MODULE
+ * - \ref ECAP0_MODULE
+ * - \ref ECAP1_MODULE
+ * - \ref OPA_MODULE
+ * @return None
+ * @details This function is used to disable module clock.
+ */
+void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
+{
+ uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL;
+ u32tmpVal = ~(1UL << MODULE_IP_EN_Pos(u32ModuleIdx));
+ u32tmpAddr = (uint32_t)&CLK->AHBCLK;
+ u32tmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL));
+ *(uint32_t *)u32tmpAddr &= u32tmpVal;
+}
+
+
+/**
+ * @brief Set PLL frequency
+ * @param[in] u32PllClkSrc is PLL clock source. Including :
+ * - \ref CLK_PLLCTL_PLLSRC_HXT
+ * - \ref CLK_PLLCTL_PLLSRC_HIRC
+ * @param[in] u32PllFreq is PLL frequency.
+ * @return PLL frequency
+ * @details This function is used to configure PLLCTL register to set specified PLL frequency. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
+{
+ uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32CLK_SRC, u32PllClk;
+ uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR, u32MinNO, u32basFreq;
+ /* Disable PLL first to avoid unstable when setting PLL */
+ CLK_DisablePLL();
+
+ /* PLL source clock is from HXT */
+ if (u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) {
+ /* Enable HXT clock */
+ CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk;
+ /* Wait for HXT clock ready */
+ CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
+ /* Select PLL source clock from HXT */
+ u32CLK_SRC = CLK_PLLCTL_PLLSRC_HXT;
+ u32PllSrcClk = __HXT;
+ /* u32NR start from 2 */
+ u32NR = 2UL;
+ }
+ /* PLL source clock is from HIRC */
+ else {
+ /* Enable HIRC clock */
+ CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
+ /* Wait for HIRC clock ready */
+ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
+ /* Select PLL source clock from HIRC */
+ u32CLK_SRC = CLK_PLLCTL_PLLSRC_HIRC;
+ u32PllSrcClk = __HIRC;
+ /* u32NR start from 4 when FIN = 22.1184MHz to avoid calculation overflow */
+ u32NR = 4UL;
+ }
+
+ if ((u32PllFreq <= FREQ_500MHZ) && (u32PllFreq >= FREQ_50MHZ)) {
+ /* Find best solution */
+ u32Min = (uint32_t) - 1;
+ u32MinNR = 0UL;
+ u32MinNF = 0UL;
+ u32MinNO = 0UL;
+ u32basFreq = u32PllFreq;
+
+ for (u32NO = 1UL; u32NO <= 4UL; u32NO++) {
+ /* Break when get good results */
+ if (u32Min == 0UL) {
+ break;
+ }
+
+ if (u32NO != 3UL) {
+ if (u32NO == 4UL) {
+ u32PllFreq = u32basFreq << 2;
+ } else if (u32NO == 2UL) {
+ u32PllFreq = u32basFreq << 1;
+ } else {
+ }
+
+ for (u32NR = 2UL; u32NR <= 32UL; u32NR++) {
+ /* Break when get good results */
+ if (u32Min == 0UL) {
+ break;
+ }
+
+ u32Tmp = u32PllSrcClk / u32NR;
+
+ if ((u32Tmp >= 4000000UL) && (u32Tmp <= 8000000UL)) {
+ for (u32NF = 2UL; u32NF <= 513UL; u32NF++) {
+ /* u32Tmp2 is shifted 2 bits to avoid overflow */
+ u32Tmp2 = (((u32Tmp * 2UL) >> 2) * u32NF);
+
+ if ((u32Tmp2 >= FREQ_50MHZ) && (u32Tmp2 <= FREQ_125MHZ)) {
+ u32Tmp3 = (u32Tmp2 > (u32PllFreq >> 2)) ? u32Tmp2 - (u32PllFreq >> 2) : (u32PllFreq >> 2) - u32Tmp2;
+
+ if (u32Tmp3 < u32Min) {
+ u32Min = u32Tmp3;
+ u32MinNR = u32NR;
+ u32MinNF = u32NF;
+ u32MinNO = u32NO;
+
+ /* Break when get good results */
+ if (u32Min == 0UL) {
+ break;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ /* Enable and apply new PLL setting. */
+ CLK->PLLCTL = u32CLK_SRC | ((u32MinNO - 1UL) << 14) | ((u32MinNR - 1UL) << 9) | (u32MinNF - 2UL);
+ /* Wait for PLL clock stable */
+ CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
+ /* Actual PLL output clock frequency */
+ u32PllClk = u32PllSrcClk / (u32MinNO * (u32MinNR)) * (u32MinNF) * 2UL;
+ } else {
+ /* Wrong frequency request. Just return default setting. */
+ /* Apply default PLL setting and return */
+ if (u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) {
+ CLK->PLLCTL = CLK_PLLCTL_192MHz_HXT;
+ } else {
+ CLK->PLLCTL = CLK_PLLCTL_192MHz_HIRC;
+ }
+
+ /* Wait for PLL clock stable */
+ CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
+ /* Actual PLL output clock frequency */
+ u32PllClk = CLK_GetPLLClockFreq();
+ }
+
+ return u32PllClk;
+}
+
+/**
+ * @brief Disable PLL
+ * @param None
+ * @return None
+ * @details This function set PLL in Power-down mode. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+void CLK_DisablePLL(void)
+{
+ CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
+}
+
+
+/**
+ * @brief This function check selected clock source status
+ * @param[in] u32ClkMask is selected clock source. Including :
+ * - \ref CLK_STATUS_HXTSTB_Msk
+ * - \ref CLK_STATUS_LXTSTB_Msk
+ * - \ref CLK_STATUS_HIRCSTB_Msk
+ * - \ref CLK_STATUS_LIRCSTB_Msk
+ * - \ref CLK_STATUS_PLLSTB_Msk
+ * @retval 0 clock is not stable
+ * @retval 1 clock is stable
+ * @details To wait for clock ready by specified clock source stable flag or timeout (~300ms)
+ */
+uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
+{
+ int32_t i32TimeOutCnt = 2160000;
+ uint32_t u32Ret = 1U;
+
+ while ((CLK->STATUS & u32ClkMask) != u32ClkMask) {
+ if (i32TimeOutCnt-- <= 0) {
+ u32Ret = 0U;
+ break;
+ }
+ }
+
+ return u32Ret;
+}
+
+/**
+ * @brief Enable System Tick counter
+ * @param[in] u32ClkSrc is System Tick clock source. Including:
+ * - \ref CLK_CLKSEL0_STCLKSEL_HXT
+ * - \ref CLK_CLKSEL0_STCLKSEL_LXT
+ * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
+ * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
+ * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
+ * - \ref CLK_CLKSEL0_STCLKSEL_HCLK
+ * @param[in] u32Count is System Tick reload value. It could be 0~0xFFFFFF.
+ * @return None
+ * @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
+{
+ /* Set System Tick counter disabled */
+ SysTick->CTRL = 0UL;
+
+ /* Set System Tick clock source */
+ if (u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK) {
+ SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
+ } else {
+ CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
+ }
+
+ /* Set System Tick reload value */
+ SysTick->LOAD = u32Count;
+ /* Clear System Tick current value and counter flag */
+ SysTick->VAL = 0UL;
+ /* Set System Tick interrupt enabled and counter enabled */
+ SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
+}
+
+/**
+ * @brief Disable System Tick counter
+ * @param None
+ * @return None
+ * @details This function disable System Tick counter.
+ */
+void CLK_DisableSysTick(void)
+{
+ /* Set System Tick counter disabled */
+ SysTick->CTRL = 0UL;
+}
+
+
+/**
+ * @brief Power-down mode selected
+ * @param[in] u32PDMode is power down mode index. Including :
+ * - \ref CLK_PMUCTL_PDMSEL_PD
+ * - \ref CLK_PMUCTL_PDMSEL_LLPD
+ * - \ref CLK_PMUCTL_PDMSEL_FWPD
+ * - \ref CLK_PMUCTL_PDMSEL_SPD0
+ * - \ref CLK_PMUCTL_PDMSEL_SPD1
+ * - \ref CLK_PMUCTL_PDMSEL_DPD
+ * @return None
+ * @details This function is used to set power-down mode.
+ * @note Must enable LIRC clock before entering to Standby Power-down Mode
+ */
+
+void CLK_SetPowerDownMode(uint32_t u32PDMode)
+{
+ /* Enable LIRC clock before entering to Standby Power-down Mode */
+ if ((u32PDMode == CLK_PMUCTL_PDMSEL_SPD0) || (u32PDMode == CLK_PMUCTL_PDMSEL_SPD1)) {
+ /* Enable LIRC clock */
+ CLK->PWRCTL |= CLK_PWRCTL_LIRCEN_Msk;
+ /* Wait for LIRC clock stable */
+ CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
+ }
+
+ CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_PDMSEL_Msk)) | u32PDMode;
+}
+
+/**
+ * @brief Set Wake-up pin trigger type at Deep Power down mode
+ *
+ * @param[in] u32TriggerType
+ * - \ref CLK_DPDWKPIN_RISING
+ * - \ref CLK_DPDWKPIN_FALLING
+ * - \ref CLK_DPDWKPIN_BOTHEDGE
+ * @return None
+ *
+ * @details This function is used to enable Wake-up pin trigger type.
+ */
+
+void CLK_EnableDPDWKPin(uint32_t u32TriggerType)
+{
+ CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN_Msk)) | u32TriggerType;
+}
+
+/**
+ * @brief Get power manager wake up source
+ *
+ * @param[in] None
+ * @return None
+ *
+ * @details This function get power manager wake up source.
+ */
+
+uint32_t CLK_GetPMUWKSrc(void)
+{
+ return (CLK->PMUSTS);
+}
+
+/**
+ * @brief Set specified GPIO as wake up source at Stand-by Power down mode
+ *
+ * @param[in] u32Port GPIO port. It could be 0~3.
+ * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15.
+ * @param[in] u32TriggerType
+ * - \ref CLK_SPDWKPIN_RISING
+ * - \ref CLK_SPDWKPIN_FALLING
+ * @param[in] u32DebounceEn
+ * - \ref CLK_SPDWKPIN_DEBOUNCEEN
+ * - \ref CLK_SPDWKPIN_DEBOUNCEDIS
+ * @return None
+ *
+ * @details This function is used to set specified GPIO as wake up source
+ * at Stand-by Power down mode.
+ */
+void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn)
+{
+ uint32_t u32tmpAddr = 0UL;
+ uint32_t u32tmpVal = 0UL;
+ /* GPx Stand-by Power-down Wake-up Pin Select */
+ u32tmpAddr = (uint32_t)&CLK->PASWKCTL;
+ u32tmpAddr += (0x4UL * u32Port);
+ u32tmpVal = inpw((uint32_t *)u32tmpAddr);
+ u32tmpVal = (u32tmpVal & ~(CLK_PASWKCTL_WKPSEL_Msk | CLK_PASWKCTL_PRWKEN_Msk | CLK_PASWKCTL_PFWKEN_Msk | CLK_PASWKCTL_DBEN_Msk | CLK_PASWKCTL_WKEN_Msk)) |
+ (u32Pin << CLK_PASWKCTL_WKPSEL_Pos) | u32TriggerType | u32DebounceEn | CLK_SPDWKPIN_ENABLE;
+ outpw((uint32_t *)u32tmpAddr, u32tmpVal);
+}
+
+/**
+ * @brief Get PLL clock frequency
+ * @param None
+ * @return PLL frequency
+ * @details This function get PLL frequency. The frequency unit is Hz.
+ */
+uint32_t CLK_GetPLLClockFreq(void)
+{
+ uint32_t u32PllFreq = 0UL, u32PllReg;
+ uint32_t u32FIN, u32NF, u32NR, u32NO;
+ uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U};
+ u32PllReg = CLK->PLLCTL;
+
+ if (u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk)) {
+ u32PllFreq = 0UL; /* PLL is in power down mode or fix low */
+ } else if ((u32PllReg & CLK_PLLCTL_BP_Msk) == CLK_PLLCTL_BP_Msk) {
+ if ((u32PllReg & CLK_PLLCTL_PLLSRC_HIRC) == CLK_PLLCTL_PLLSRC_HIRC) {
+ u32FIN = __HIRC; /* PLL source clock from HIRC */
+ } else {
+ u32FIN = __HXT; /* PLL source clock from HXT */
+ }
+
+ u32PllFreq = u32FIN;
+ } else {
+ if ((u32PllReg & CLK_PLLCTL_PLLSRC_HIRC) == CLK_PLLCTL_PLLSRC_HIRC) {
+ u32FIN = __HIRC; /* PLL source clock from HIRC */
+ } else {
+ u32FIN = __HXT; /* PLL source clock from HXT */
+ }
+
+ /* PLL is output enabled in normal work mode */
+ u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)];
+ u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2UL;
+ u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 1UL;
+ /* u32FIN is shifted 2 bits to avoid overflow */
+ u32PllFreq = (((u32FIN >> 2) * u32NF) / (u32NR * u32NO) << 2) * 2UL;
+ }
+
+ return u32PllFreq;
+}
+
+/**
+ * @brief Get selected module clock source
+ * @param[in] u32ModuleIdx is module index.
+ * - \ref SDH0_MODULE
+ * - \ref SDH1_MODULE
+ * - \ref WDT_MODULE
+ * - \ref UART0_MODULE
+ * - \ref UART1_MODULE
+ * - \ref CLKO_MODULE
+ * - \ref WWDT_MODULE
+ * - \ref TMR0_MODULE
+ * - \ref TMR1_MODULE
+ * - \ref TMR2_MODULE
+ * - \ref TMR3_MODULE
+ * - \ref EPWM0_MODULE
+ * - \ref EPWM1_MODULE
+ * - \ref BPWM0_MODULE
+ * - \ref BPWM1_MODULE
+ * - \ref QSPI0_MODULE
+ * - \ref SPI0_MODULE
+ * - \ref SPI1_MODULE
+ * - \ref SPI2_MODULE
+ * - \ref SPI3_MODULE
+ * - \ref SC0_MODULE
+ * - \ref SC1_MODULE
+ * - \ref SC2_MODULE
+ * - \ref RTC_MODULE
+ * - \ref I2S0_MODULE
+ * - \ref UART2_MODULE
+ * - \ref UART3_MODULE
+ * - \ref UART4_MODULE
+ * - \ref UART5_MODULE
+ * @return Selected module clock source setting
+ * @details This function get selected module clock source.
+ */
+uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx)
+{
+ uint32_t u32sel = 0;
+ uint32_t u32SelTbl[4] = {0x0, 0x4, 0x8, 0xC};
+
+ /* Get clock source selection setting */
+ if (u32ModuleIdx == EPWM0_MODULE) {
+ return ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk) >> CLK_CLKSEL2_EPWM0SEL_Pos);
+ } else if (u32ModuleIdx == EPWM1_MODULE) {
+ return ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk) >> CLK_CLKSEL2_EPWM1SEL_Pos);
+ } else if (u32ModuleIdx == BPWM0_MODULE) {
+ return ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk) >> CLK_CLKSEL2_BPWM0SEL_Pos);
+ } else if (u32ModuleIdx == BPWM1_MODULE) {
+ return ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk) >> CLK_CLKSEL2_BPWM1SEL_Pos);
+ } else if (MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk) {
+ /* Get clock select control register address */
+ u32sel = (uint32_t)&CLK->CLKSEL0 + (u32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]);
+ /* Get clock source selection setting */
+ return ((M32(u32sel) & (MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx))) >> MODULE_CLKSEL_Pos(u32ModuleIdx));
+ } else {
+ return 0;
+ }
+}
+
+/**
+ * @brief Get selected module clock divider number
+ * @param[in] u32ModuleIdx is module index.
+ * - \ref UART0_MODULE
+ * - \ref UART1_MODULE
+ * - \ref EADC_MODULE
+ * - \ref SDH0_MODULE
+ * - \ref SC0_MODULE
+ * - \ref SC1_MODULE
+ * - \ref SC2_MODULE
+ * - \ref EMAC_MODULE
+ * - \ref SDH1_MODULE
+ * - \ref UART2_MODULE
+ * - \ref UART3_MODULE
+ * - \ref UART4_MODULE
+ * - \ref UART5_MODULE
+ * @return Selected module clock divider number setting
+ * @details This function get selected module clock divider number.
+ */
+uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx)
+{
+ uint32_t u32div = 0;
+ uint32_t u32DivTbl[4] = {0x0, 0x4, 0x8, 0x10};
+
+ if (MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk) {
+ /* Get clock divider control register address */
+ u32div = (uint32_t)&CLK->CLKDIV0 + (u32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]);
+ /* Get clock divider number setting */
+ return ((M32(u32div) & (MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx))) >> MODULE_CLKDIV_Pos(u32ModuleIdx));
+ } else {
+ return 0;
+ }
+}
+
+
+/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CLK_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/StdDriver/src/m480_fmc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/StdDriver/src/m480_fmc.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,809 @@
+/**************************************************************************//**
+ * @file fmc.c
+ * @version V1.00
+ * @brief M480 series FMC driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************/
+
+#include <stdio.h>
+
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup FMC_Driver FMC Driver
+ @{
+*/
+
+
+/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions
+ @{
+*/
+
+
+/**
+ * @brief Disable FMC ISP function.
+ * @return None
+ */
+void FMC_Close(void)
+{
+ FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk;
+}
+
+
+/**
+ * @brief Execute FMC_ISPCMD_PAGE_ERASE command to erase a flash page. The page size is 4096 bytes.
+ * @param[in] u32PageAddr Address of the flash page to be erased.
+ * It must be a 4096 bytes aligned address.
+ * @return ISP page erase success or not.
+ * @retval 0 Success
+ * @retval -1 Erase failed
+ */
+int32_t FMC_Erase(uint32_t u32PageAddr)
+{
+ int32_t ret = 0;
+
+ if (u32PageAddr == FMC_SPROM_BASE) {
+ ret = FMC_Erase_SPROM();
+ }
+
+ if (ret == 0) {
+ FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE;
+ FMC->ISPADDR = u32PageAddr;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+ if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) {
+ FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
+ ret = -1;
+ }
+ }
+
+ return ret;
+}
+
+
+/**
+ * @brief Execute FMC_ISPCMD_PAGE_ERASE command to erase SPROM. The page size is 4096 bytes.
+ * @return SPROM page erase success or not.
+ * @retval 0 Success
+ * @retval -1 Erase failed
+ */
+int32_t FMC_Erase_SPROM(void)
+{
+ int32_t ret = 0;
+ FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE;
+ FMC->ISPADDR = FMC_SPROM_BASE;
+ FMC->ISPDAT = 0x0055AA03UL;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+ if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) {
+ FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Execute FMC_ISPCMD_BLOCK_ERASE command to erase a flash block. The block size is 4 pages.
+ * @param[in] u32BlockAddr Address of the flash block to be erased.
+ * It must be a 4 pages aligned address.
+ * @return ISP page erase success or not.
+ * @retval 0 Success
+ * @retval -1 Erase failed
+ */
+int32_t FMC_Erase_Block(uint32_t u32BlockAddr)
+{
+ int32_t ret = 0;
+ FMC->ISPCMD = FMC_ISPCMD_BLOCK_ERASE;
+ FMC->ISPADDR = u32BlockAddr;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+ if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) {
+ FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Execute FMC_ISPCMD_BANK_ERASE command to erase a flash block.
+ * @param[in] u32BankAddr Base address of the flash bank to be erased.
+ * @return ISP page erase success or not.
+ * @retval 0 Success
+ * @retval -1 Erase failed
+ */
+int32_t FMC_Erase_Bank(uint32_t u32BankAddr)
+{
+ int32_t ret = 0;
+ FMC->ISPCMD = FMC_ISPCMD_BANK_ERASE;
+ FMC->ISPADDR = u32BankAddr;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+ if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) {
+ FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Get the current boot source.
+ * @return The current boot source.
+ * @retval 0 Is boot from APROM.
+ * @retval 1 Is boot from LDROM.
+ */
+int32_t FMC_GetBootSource(void)
+{
+ int32_t ret = 0;
+
+ if (FMC->ISPCTL & FMC_ISPCTL_BS_Msk) {
+ ret = 1;
+ }
+
+ return ret;
+}
+
+
+/**
+ * @brief Enable FMC ISP function
+ * @return None
+ */
+void FMC_Open(void)
+{
+ FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk;
+}
+
+
+/**
+ * @brief Execute FMC_ISPCMD_READ command to read a word from flash.
+ * @param[in] u32Addr Address of the flash location to be read.
+ * It must be a word aligned address.
+ * @return The word data read from specified flash address.
+ */
+uint32_t FMC_Read(uint32_t u32Addr)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ;
+ FMC->ISPADDR = u32Addr;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+ return FMC->ISPDAT;
+}
+
+
+/**
+ * @brief Execute FMC_ISPCMD_READ_64 command to read a double-word from flash.
+ * @param[in] u32addr Address of the flash location to be read.
+ * It must be a double-word aligned address.
+ * @param[out] u32data0 Place holder of word 0 read from flash address u32addr.
+ * @param[out] u32data1 Place holder of word 0 read from flash address u32addr+4.
+ * @return 0 Success
+ * @return -1 Failed
+ */
+int32_t FMC_Read_64(uint32_t u32addr, uint32_t *u32data0, uint32_t *u32data1)
+{
+ int32_t ret = 0;
+ FMC->ISPCMD = FMC_ISPCMD_READ_64;
+ FMC->ISPADDR = u32addr;
+ FMC->ISPDAT = 0x0UL;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+
+ if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) {
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+ ret = -1;
+ } else {
+ *u32data0 = FMC->MPDAT0;
+ *u32data1 = FMC->MPDAT1;
+ }
+
+ return ret;
+}
+
+
+/**
+ * @brief Get the base address of Data Flash if enabled.
+ * @retval The base address of Data Flash
+ */
+uint32_t FMC_ReadDataFlashBaseAddr(void)
+{
+ return FMC->DFBA;
+}
+
+/**
+ * @brief Set boot source from LDROM or APROM after next software reset
+ * @param[in] i32BootSrc
+ * 1: Boot from LDROM
+ * 0: Boot from APROM
+ * @return None
+ * @details This function is used to switch APROM boot or LDROM boot. User need to call
+ * FMC_SetBootSource to select boot source first, then use CPU reset or
+ * System Reset Request to reset system.
+ */
+void FMC_SetBootSource(int32_t i32BootSrc)
+{
+ if (i32BootSrc) {
+ FMC->ISPCTL |= FMC_ISPCTL_BS_Msk; /* Boot from LDROM */
+ } else {
+ FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk;/* Boot from APROM */
+ }
+}
+
+/**
+ * @brief Execute ISP FMC_ISPCMD_PROGRAM to program a word to flash.
+ * @param[in] u32Addr Address of the flash location to be programmed.
+ * It must be a word aligned address.
+ * @param[in] u32Data The word data to be programmed.
+ * @return None
+ */
+void FMC_Write(uint32_t u32Addr, uint32_t u32Data)
+{
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
+ FMC->ISPADDR = u32Addr;
+ FMC->ISPDAT = u32Data;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+}
+
+/**
+ * @brief Execute ISP FMC_ISPCMD_PROGRAM_64 to program a double-word to flash.
+ * @param[in] u32addr Address of the flash location to be programmed.
+ * It must be a double-word aligned address.
+ * @param[in] u32data0 The word data to be programmed to flash address u32addr.
+ * @param[in] u32data1 The word data to be programmed to flash address u32addr+4.
+ * @return 0 Success
+ * @return -1 Failed
+ */
+int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1)
+{
+ int32_t ret = 0;
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM_64;
+ FMC->ISPADDR = u32addr;
+ FMC->MPDAT0 = u32data0;
+ FMC->MPDAT1 = u32data1;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+
+ if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) {
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+ ret = -1;
+ }
+
+ return ret;
+}
+
+
+/**
+ * @brief Program Multi-Word data into specified address of flash.
+ * @param[in] u32Addr Start flash address in APROM where the data chunk to be programmed into.
+ * This address must be 8-bytes aligned to flash address.
+ * @param[in] pu32Buf Buffer that carry the data chunk.
+ * @param[in] u32Len Length of the data chunk in bytes.
+ * @retval >=0 Number of data bytes were programmed.
+ * @return -1 Invalid address.
+ */
+int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len)
+{
+ int i, idx, retval = 0;
+
+ if ((u32Addr >= FMC_APROM_END) || ((u32Addr % 8) != 0)) {
+ return -1;
+ }
+
+ u32Len = u32Len - (u32Len % 8); /* u32Len must be multiple of 8. */
+ idx = 0;
+
+ while (u32Len >= 8) {
+ FMC->ISPADDR = u32Addr;
+ FMC->MPDAT0 = pu32Buf[idx++];
+ FMC->MPDAT1 = pu32Buf[idx++];
+ FMC->MPDAT2 = pu32Buf[idx++];
+ FMC->MPDAT3 = pu32Buf[idx++];
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM_MUL;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ for (i = 16; i < FMC_MULTI_WORD_PROG_LEN;) {
+ while (FMC->MPSTS & (FMC_MPSTS_D0_Msk | FMC_MPSTS_D1_Msk))
+ ;
+
+ retval += 8;
+ u32Len -= 8;
+
+ if (u32Len < 8) {
+ return retval;
+ }
+
+ if (!(FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk)) {
+ /* printf(" [WARNING] busy cleared after D0D1 cleared!\n"); */
+ i += 8;
+ break;
+ }
+
+ FMC->MPDAT0 = pu32Buf[idx++];
+ FMC->MPDAT1 = pu32Buf[idx++];
+
+ if (i == FMC_MULTI_WORD_PROG_LEN / 4) {
+ break; // done
+ }
+
+ while (FMC->MPSTS & (FMC_MPSTS_D2_Msk | FMC_MPSTS_D3_Msk))
+ ;
+
+ retval += 8;
+ u32Len -= 8;
+
+ if (u32Len < 8) {
+ return retval;
+ }
+
+ if (!(FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk)) {
+ /* printf(" [WARNING] busy cleared after D2D3 cleared!\n"); */
+ i += 8;
+ break;
+ }
+
+ FMC->MPDAT2 = pu32Buf[idx++];
+ FMC->MPDAT3 = pu32Buf[idx++];
+ }
+
+ if (i != FMC_MULTI_WORD_PROG_LEN) {
+ /* printf(" [WARNING] Multi-word program interrupted at 0x%x !!\n", i); */
+ return retval;
+ }
+
+ while (FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) ;
+
+ u32Addr += FMC_MULTI_WORD_PROG_LEN;
+ }
+
+ return retval;
+}
+
+
+/**
+ * @brief Program a 64-bits data to the specified OTP.
+ * @param[in] otp_num The OTP number.
+ * @param[in] low_word Low word of the 64-bits data.
+ * @param[in] high_word Low word of the 64-bits data.
+ * @retval 0 Success
+ * @retval -1 Program failed.
+ * @retval -2 Invalid OTP number.
+ */
+int32_t FMC_Write_OTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word)
+{
+ int32_t ret = 0;
+
+ if (otp_num > 255UL) {
+ ret = -2;
+ }
+
+ if (ret == 0) {
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
+ FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL;
+ FMC->ISPDAT = low_word;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+ if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) {
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+ ret = -1;
+ }
+ }
+
+ if (ret == 0) {
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
+ FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL + 4UL;
+ FMC->ISPDAT = high_word;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+ if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) {
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+ ret = -1;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Read the 64-bits data from the specified OTP.
+ * @param[in] otp_num The OTP number.
+ * @param[in] low_word Low word of the 64-bits data.
+ * @param[in] high_word Low word of the 64-bits data.
+ * @retval 0 Success
+ * @retval -1 Read failed.
+ * @retval -2 Invalid OTP number.
+ */
+int32_t FMC_Read_OTP(uint32_t otp_num, uint32_t *low_word, uint32_t *high_word)
+{
+ int32_t ret = 0;
+
+ if (otp_num > 255UL) {
+ ret = -2;
+ }
+
+ if (ret == 0) {
+ FMC->ISPCMD = FMC_ISPCMD_READ_64;
+ FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL ;
+ FMC->ISPDAT = 0x0UL;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+
+ if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) {
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+ ret = -1;
+ } else {
+ *low_word = FMC->MPDAT0;
+ *high_word = FMC->MPDAT1;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Lock the specified OTP.
+ * @param[in] otp_num The OTP number.
+ * @retval 0 Success
+ * @retval -1 Failed to write OTP lock bits.
+ * @retval -2 Invalid OTP number.
+ */
+int32_t FMC_Lock_OTP(uint32_t otp_num)
+{
+ int32_t ret = 0;
+
+ if (otp_num > 255UL) {
+ ret = -2;
+ }
+
+ if (ret == 0) {
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
+ FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + otp_num * 4UL;
+ FMC->ISPDAT = 0UL;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+ if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) {
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+ ret = -1;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Check the OTP is locked or not.
+ * @param[in] otp_num The OTP number.
+ * @retval 1 OTP is locked.
+ * @retval 0 OTP is not locked.
+ * @retval -1 Failed to read OTP lock bits.
+ * @retval -2 Invalid OTP number.
+ */
+int32_t FMC_Is_OTP_Locked(uint32_t otp_num)
+{
+ int32_t ret = 0;
+
+ if (otp_num > 255UL) {
+ ret = -2;
+ }
+
+ if (ret == 0) {
+ FMC->ISPCMD = FMC_ISPCMD_READ;
+ FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + otp_num * 4UL;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+ if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) {
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+ ret = -1;
+ } else {
+ if (FMC->ISPDAT != 0xFFFFFFFFUL) {
+ ret = 1; /* Lock work was progrmmed. OTP was locked. */
+ }
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Execute FMC_ISPCMD_READ command to read User Configuration.
+ * @param[out] u32Config A two-word array.
+ * u32Config[0] holds CONFIG0, while u32Config[1] holds CONFIG1.
+ * @param[in] u32Count Available word count in u32Config.
+ * @return Success or not.
+ * @retval 0 Success.
+ * @retval -1 Invalid parameter.
+ */
+int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count)
+{
+ int32_t ret = 0;
+ u32Config[0] = FMC_Read(FMC_CONFIG_BASE);
+
+ if (u32Count < 2UL) {
+ ret = -1;
+ } else {
+ u32Config[1] = FMC_Read(FMC_CONFIG_BASE + 4UL);
+ }
+
+ return ret;
+}
+
+
+/**
+ * @brief Execute ISP commands to erase then write User Configuration.
+ * @param[in] u32Config A two-word array.
+ * u32Config[0] holds CONFIG0, while u32Config[1] holds CONFIG1.
+ * @param[in] u32Count Always be 2 in this BSP.
+ * @return Success or not.
+ * @retval 0 Success.
+ * @retval -1 Invalid parameter.
+ */
+int32_t FMC_WriteConfig(uint32_t u32Config[], uint32_t u32Count)
+{
+ FMC_ENABLE_CFG_UPDATE();
+ FMC_Erase(FMC_CONFIG_BASE);
+ FMC_Write(FMC_CONFIG_BASE, u32Config[0]);
+ FMC_Write(FMC_CONFIG_BASE + 4UL, u32Config[1]);
+ FMC_DISABLE_CFG_UPDATE();
+ return 0;
+}
+
+
+/**
+ * @brief Run CRC32 checksum calculation and get result.
+ * @param[in] u32addr Starting flash address. It must be a page aligned address.
+ * @param[in] u32count Byte count of flash to be calculated. It must be multiple of 512 bytes.
+ * @return Success or not.
+ * @retval 0 Success.
+ * @retval 0xFFFFFFFF Invalid parameter.
+ */
+uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count)
+{
+ uint32_t ret;
+
+ if ((u32addr % 512UL) || (u32count % 512UL)) {
+ ret = 0xFFFFFFFF;
+ } else {
+ FMC->ISPCMD = FMC_ISPCMD_RUN_CKS;
+ FMC->ISPADDR = u32addr;
+ FMC->ISPDAT = u32count;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+
+ FMC->ISPCMD = FMC_ISPCMD_READ_CKS;
+ FMC->ISPADDR = u32addr;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+
+ ret = FMC->ISPDAT;
+ }
+
+ return ret;
+}
+
+
+/**
+ * @brief Run flash all one verification and get result.
+ * @param[in] u32addr Starting flash address. It must be a page aligned address.
+ * @param[in] u32count Byte count of flash to be calculated. It must be multiple of 512 bytes.
+ * @retval READ_ALLONE_YES The contents of verified flash area are 0xFFFFFFFF.
+ * @retval READ_ALLONE_NOT Some contents of verified flash area are not 0xFFFFFFFF.
+ * @retval READ_ALLONE_CMD_FAIL Unexpected error occurred.
+ */
+uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count)
+{
+ uint32_t ret = READ_ALLONE_CMD_FAIL;
+ FMC->ISPSTS = 0x80UL; /* clear check all one bit */
+ FMC->ISPCMD = FMC_ISPCMD_RUN_ALL1;
+ FMC->ISPADDR = u32addr;
+ FMC->ISPDAT = u32count;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+
+ do {
+ FMC->ISPCMD = FMC_ISPCMD_READ_ALL1;
+ FMC->ISPADDR = u32addr;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+ while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+ } while (FMC->ISPDAT == 0UL);
+
+ if (FMC->ISPDAT == READ_ALLONE_YES) {
+ ret = FMC->ISPDAT;
+ }
+
+ if (FMC->ISPDAT == READ_ALLONE_NOT) {
+ ret = FMC->ISPDAT;
+ }
+
+ return ret;
+}
+
+
+/**
+ * @brief Setup security key.
+ * @param[in] key Key 0~2 to be setup.
+ * @param[in] kpmax Maximum unmatched power-on counting number.
+ * @param[in] kemax Maximum unmatched counting number.
+ * @param[in] lock_CONFIG 1: Security key lock CONFIG to write-protect. 0: Don't lock CONFIG.
+ * @param[in] lock_SPROM 1: Security key lock SPROM to write-protect. 0: Don't lock SPROM.
+ * @retval 0 Success.
+ * @retval -1 Key is locked. Cannot overwrite the current key.
+ * @retval -2 Failed to erase flash.
+ * @retval -3 Failed to program key.
+ * @retval -4 Key lock function failed.
+ * @retval -5 CONFIG lock function failed.
+ * @retval -6 SPROM lock function failed.
+ * @retval -7 KPMAX function failed.
+ * @retval -8 KEMAX function failed.
+ */
+int32_t FMC_SetSPKey(uint32_t key[3], uint32_t kpmax, uint32_t kemax,
+ const int32_t lock_CONFIG, const int32_t lock_SPROM)
+{
+ uint32_t lock_ctrl = 0UL;
+ uint32_t u32KeySts;
+ int32_t ret = 0;
+
+ if (FMC->KPKEYSTS != 0x200UL) {
+ ret = -1;
+ }
+
+ if (FMC_Erase(FMC_KPROM_BASE)) {
+ ret = -2;
+ }
+
+ if (FMC_Erase(FMC_KPROM_BASE + 0x200UL)) {
+ ret = -3;
+ }
+
+ if (!lock_CONFIG) {
+ lock_ctrl |= 0x1UL;
+ }
+
+ if (!lock_SPROM) {
+ lock_ctrl |= 0x2UL;
+ }
+
+ if (ret == 0) {
+ FMC_Write(FMC_KPROM_BASE, key[0]);
+ FMC_Write(FMC_KPROM_BASE + 0x4UL, key[1]);
+ FMC_Write(FMC_KPROM_BASE + 0x8UL, key[2]);
+ FMC_Write(FMC_KPROM_BASE + 0xCUL, kpmax);
+ FMC_Write(FMC_KPROM_BASE + 0x10UL, kemax);
+ FMC_Write(FMC_KPROM_BASE + 0x14UL, lock_ctrl);
+
+ while (FMC->KPKEYSTS & FMC_KPKEYSTS_KEYBUSY_Msk) { }
+
+ u32KeySts = FMC->KPKEYSTS;
+
+ if (!(u32KeySts & FMC_KPKEYSTS_KEYLOCK_Msk)) {
+ /* Security key lock failed! */
+ ret = -4;
+ } else if ((lock_CONFIG && (!(u32KeySts & FMC_KPKEYSTS_CFGFLAG_Msk))) ||
+ ((!lock_CONFIG) && (u32KeySts & FMC_KPKEYSTS_CFGFLAG_Msk))) {
+ /* CONFIG lock failed! */
+ ret = -5;
+ } else if ((lock_SPROM && (!(u32KeySts & FMC_KPKEYSTS_SPFLAG_Msk))) ||
+ ((!lock_SPROM) && (u32KeySts & FMC_KPKEYSTS_SPFLAG_Msk))) {
+ /* CONFIG lock failed! */
+ ret = -6;
+ } else if (((FMC->KPCNT & FMC_KPCNT_KPMAX_Msk) >> FMC_KPCNT_KPMAX_Pos) != kpmax) {
+ /* KPMAX failed! */
+ ret = -7;
+ } else if (((FMC->KPKEYCNT & FMC_KPKEYCNT_KPKEMAX_Msk) >> FMC_KPKEYCNT_KPKEMAX_Pos) != kemax) {
+ /* KEMAX failed! */
+ ret = -8;
+ }
+ }
+
+ return ret;
+}
+
+
+/**
+ * @brief Execute security key comparison.
+ * @param[in] key Key 0~2 to be compared.
+ * @retval 0 Key matched.
+ * @retval -1 Forbidden. Times of key comparison mismatch reach the maximum count.
+ * @retval -2 Key mismatched.
+ * @retval -3 No security key lock. Key comparison is not required.
+ */
+int32_t FMC_CompareSPKey(uint32_t key[3])
+{
+ uint32_t u32KeySts;
+ int32_t ret = 0;
+
+ if (FMC->KPKEYSTS & FMC_KPKEYSTS_FORBID_Msk) {
+ /* FMC_CompareSPKey - FORBID! */
+ ret = -1;
+ }
+
+ if (!(FMC->KPKEYSTS & FMC_KPKEYSTS_KEYLOCK_Msk)) {
+ /* FMC_CompareSPKey - key is not locked! */
+ ret = -3;
+ }
+
+ if (ret == 0) {
+ FMC->KPKEY0 = key[0];
+ FMC->KPKEY1 = key[1];
+ FMC->KPKEY2 = key[2];
+ FMC->KPKEYTRG = FMC_KPKEYTRG_KPKEYGO_Msk | FMC_KPKEYTRG_TCEN_Msk;
+
+ while (FMC->KPKEYSTS & FMC_KPKEYSTS_KEYBUSY_Msk) { }
+
+ u32KeySts = FMC->KPKEYSTS;
+
+ if (!(u32KeySts & FMC_KPKEYSTS_KEYMATCH_Msk)) {
+ /* Key mismatched! */
+ ret = -2;
+ } else if (u32KeySts & FMC_KPKEYSTS_KEYLOCK_Msk) {
+ /* Key matched, but still be locked! */
+ ret = -2;
+ }
+ }
+
+ return ret;
+}
+
+
+/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group FMC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
+
+
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/StdDriver/src/m480_gpio.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/StdDriver/src/m480_gpio.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,168 @@
+/**************************************************************************//**
+ * @file gpio.c
+ * @version V3.00
+ * @brief M480 series GPIO driver source file
+ *
+ * @copyright (C) 2011~2016 Nuvoton Technology Corp. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************/
+
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup GPIO_Driver GPIO Driver
+ @{
+*/
+
+/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
+ @{
+*/
+
+/**
+ * @brief Set GPIO operation mode
+ *
+ * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
+ * It could be BIT0 ~ BIT13 for PE GPIO port.
+ * It could be BIT0 ~ BIT11 for PG GPIO port.
+ * @param[in] u32Mode Operation mode. It could be \n
+ * GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_OPEN_DRAIN, GPIO_MODE_QUASI.
+ *
+ * @return None
+ *
+ * @details This function is used to set specified GPIO operation mode.
+ */
+void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
+{
+ uint32_t i;
+
+ for (i = 0ul; i < GPIO_PIN_MAX; i++) {
+ if ((u32PinMask & (1ul << i)) == (1ul << i)) {
+ port->MODE = (port->MODE & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1));
+ }
+ }
+}
+
+/**
+ * @brief Enable GPIO interrupt
+ *
+ * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32Pin The pin of specified GPIO port.
+ * It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port.
+ * It could be 0 ~ 13 for PE GPIO port.
+ * It could be 0 ~ 11 for PG GPIO port.
+ * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
+ * GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW.
+ *
+ * @return None
+ *
+ * @details This function is used to enable specified GPIO pin interrupt.
+ */
+void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs)
+{
+ port->INTTYPE = (port->INTTYPE & ~(1ul << u32Pin)) | (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin);
+ port->INTEN = (port->INTEN & ~(0x00010001ul << u32Pin)) | ((u32IntAttribs & 0xFFFFFFUL) << u32Pin);
+}
+
+
+/**
+ * @brief Disable GPIO interrupt
+ *
+ * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32Pin The pin of specified GPIO port.
+ * It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port.
+ * It could be 0 ~ 13 for PE GPIO port.
+ * It could be 0 ~ 11 for PG GPIO port.
+ *
+ * @return None
+ *
+ * @details This function is used to disable specified GPIO pin interrupt.
+ */
+void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin)
+{
+ port->INTTYPE &= ~(1UL << u32Pin);
+ port->INTEN &= ~((0x00010001UL) << u32Pin);
+}
+
+/**
+ * @brief Set GPIO slew rate control
+ *
+ * @param[in] port GPIO port. It could be \ref PA, \ref PB, ... or \ref GPH
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * @param[in] u32Mode Slew rate mode. \ref GPIO_SLEWCTL_NORMAL (maximum 40 MHz at 2.7V)
+ * \ref GPIO_SLEWCTL_HIGH (maximum 80 MHz at 2.7V)
+ * \ref GPIO_SLEWCTL_FAST (maximum 100 MHz at 2.7V)
+ *
+ * @return None
+ *
+ * @details This function is used to set specified GPIO operation mode.
+ */
+void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
+{
+ uint32_t i;
+
+ for (i = 0ul; i < GPIO_PIN_MAX; i++) {
+ if (u32PinMask & (1ul << i)) {
+ port->SLEWCTL = (port->SLEWCTL & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1));
+ }
+ }
+}
+
+/**
+ * @brief Set GPIO Pull-up and Pull-down control
+ *
+ * @param[in] port GPIO port. It could be \ref PA, \ref PB, ... or \ref GPH
+ * @param[in] u32PinMask The pin of specified GPIO port. It could be 0 ~ 15.
+ * @param[in] u32Mode The pin mode of specified GPIO pin. It could be
+ * \ref GPIO_PUSEL_DISABLE
+ * \ref GPIO_PUSEL_PULL_UP
+ * \ref GPIO_PUSEL_PULL_DOWN
+ *
+ * @return None
+ *
+ * @details Set the pin mode of specified GPIO pin.
+ */
+void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
+{
+ uint32_t i;
+
+ for (i = 0ul; i < GPIO_PIN_MAX; i++) {
+ if (u32PinMask & (1ul << i)) {
+ port->PUSEL = (port->PUSEL & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1));
+ }
+ }
+}
+
+
+/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group GPIO_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2011~2016 Nuvoton Technology Corp. ***/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/StdDriver/src/m480_rtc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/StdDriver/src/m480_rtc.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,991 @@
+/**************************************************************************//**
+ * @file rtc.c
+ * @version V3.00
+ * @brief M480 series RTC driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************/
+#include "NuMicro.h"
+
+
+/** @cond HIDDEN_SYMBOLS */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Macro, type and constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_GLOBALS
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Global file scope (static) variables */
+/*---------------------------------------------------------------------------------------------------------*/
+static volatile uint32_t g_u32hiYear, g_u32loYear, g_u32hiMonth, g_u32loMonth, g_u32hiDay, g_u32loDay;
+static volatile uint32_t g_u32hiHour, g_u32loHour, g_u32hiMin, g_u32loMin, g_u32hiSec, g_u32loSec;
+
+/** @endcond HIDDEN_SYMBOLS */
+
+
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup RTC_Driver RTC Driver
+ @{
+*/
+
+/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions
+ @{
+*/
+
+/**
+ * @brief Initialize RTC module and start counting
+ *
+ * @param[in] sPt Specify the time property and current date and time. It includes: \n
+ * u32Year: Year value, range between 2000 ~ 2099. \n
+ * u32Month: Month value, range between 1 ~ 12. \n
+ * u32Day: Day value, range between 1 ~ 31. \n
+ * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
+ * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
+ * RTC_SATURDAY] \n
+ * u32Hour: Hour value, range between 0 ~ 23. \n
+ * u32Minute: Minute value, range between 0 ~ 59. \n
+ * u32Second: Second value, range between 0 ~ 59. \n
+ * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
+ * u8AmPm: [RTC_AM / RTC_PM] \n
+ *
+ * @return None
+ *
+ * @details This function is used to: \n
+ * 1. Write initial key to let RTC start count. \n
+ * 2. Input parameter indicates start date/time. \n
+ * 3. User has to make sure that parameters of RTC date/time are reasonable. \n
+ * @note Null pointer for using default starting date/time.
+ */
+void RTC_Open(S_RTC_TIME_DATA_T *sPt)
+{
+ RTC->INIT = RTC_INIT_KEY;
+
+ if (RTC->INIT != RTC_INIT_ACTIVE_Msk) {
+ RTC->INIT = RTC_INIT_KEY;
+
+ while (RTC->INIT != RTC_INIT_ACTIVE_Msk) {
+ }
+ }
+
+ if (sPt == 0) {
+ } else {
+ /* Set RTC date and time */
+ RTC_SetDateAndTime(sPt);
+ }
+}
+
+/**
+ * @brief Disable RTC Clock
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This API will disable RTC peripheral clock and stops RTC counting.
+ */
+void RTC_Close(void)
+{
+ CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk;
+}
+
+/**
+ * @brief Set Frequency Compensation Data
+ *
+ * @param[in] i32FrequencyX10000 Specify the RTC clock X10000, ex: 327736512 means 32773.6512.
+ *
+ * @return None
+ *
+ */
+void RTC_32KCalibration(int32_t i32FrequencyX10000)
+{
+ uint64_t u64Compensate;
+ u64Compensate = (uint64_t)(0x2710000000000);
+ u64Compensate = (uint64_t)(u64Compensate / (uint64_t)i32FrequencyX10000);
+
+ if (u64Compensate >= (uint64_t)0x400000) {
+ u64Compensate = (uint64_t)0x3FFFFF;
+ }
+
+ RTC_WaitAccessEnable();
+ RTC->FREQADJ = (uint32_t)u64Compensate;
+}
+
+/**
+ * @brief Get Current RTC Date and Time
+ *
+ * @param[out] sPt The returned pointer is specified the current RTC value. It includes: \n
+ * u32Year: Year value \n
+ * u32Month: Month value \n
+ * u32Day: Day value \n
+ * u32DayOfWeek: Day of week \n
+ * u32Hour: Hour value \n
+ * u32Minute: Minute value \n
+ * u32Second: Second value \n
+ * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
+ * u8AmPm: [RTC_AM / RTC_PM] \n
+ *
+ * @return None
+ *
+ * @details This API is used to get the current RTC date and time value.
+ */
+void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+ uint32_t u32Tmp;
+ sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */
+ sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */
+ /* Get [Date digit] data */
+ g_u32hiYear = (RTC->CAL & RTC_CAL_TENYEAR_Msk) >> RTC_CAL_TENYEAR_Pos;
+ g_u32loYear = (RTC->CAL & RTC_CAL_YEAR_Msk) >> RTC_CAL_YEAR_Pos;
+ g_u32hiMonth = (RTC->CAL & RTC_CAL_TENMON_Msk) >> RTC_CAL_TENMON_Pos;
+ g_u32loMonth = (RTC->CAL & RTC_CAL_MON_Msk) >> RTC_CAL_MON_Pos;
+ g_u32hiDay = (RTC->CAL & RTC_CAL_TENDAY_Msk) >> RTC_CAL_TENDAY_Pos;
+ g_u32loDay = (RTC->CAL & RTC_CAL_DAY_Msk) >> RTC_CAL_DAY_Pos;
+ /* Get [Time digit] data */
+ g_u32hiHour = (RTC->TIME & RTC_TIME_TENHR_Msk) >> RTC_TIME_TENHR_Pos;
+ g_u32loHour = (RTC->TIME & RTC_TIME_HR_Msk) >> RTC_TIME_HR_Pos;
+ g_u32hiMin = (RTC->TIME & RTC_TIME_TENMIN_Msk) >> RTC_TIME_TENMIN_Pos;
+ g_u32loMin = (RTC->TIME & RTC_TIME_MIN_Msk) >> RTC_TIME_MIN_Pos;
+ g_u32hiSec = (RTC->TIME & RTC_TIME_TENSEC_Msk) >> RTC_TIME_TENSEC_Pos;
+ g_u32loSec = (RTC->TIME & RTC_TIME_SEC_Msk) >> RTC_TIME_SEC_Pos;
+ /* Compute to 20XX year */
+ u32Tmp = (g_u32hiYear * 10ul);
+ u32Tmp += g_u32loYear;
+ sPt->u32Year = u32Tmp + RTC_YEAR2000;
+ /* Compute 0~12 month */
+ u32Tmp = (g_u32hiMonth * 10ul);
+ sPt->u32Month = u32Tmp + g_u32loMonth;
+ /* Compute 0~31 day */
+ u32Tmp = (g_u32hiDay * 10ul);
+ sPt->u32Day = u32Tmp + g_u32loDay;
+
+ /* Compute 12/24 hour */
+ if (sPt->u32TimeScale == RTC_CLOCK_12) {
+ u32Tmp = (g_u32hiHour * 10ul);
+ u32Tmp += g_u32loHour;
+ sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */
+
+ if (sPt->u32Hour >= 21ul) {
+ sPt->u32AmPm = RTC_PM;
+ sPt->u32Hour -= 20ul;
+ } else {
+ sPt->u32AmPm = RTC_AM;
+ }
+
+ u32Tmp = (g_u32hiMin * 10ul);
+ u32Tmp += g_u32loMin;
+ sPt->u32Minute = u32Tmp;
+ u32Tmp = (g_u32hiSec * 10ul);
+ u32Tmp += g_u32loSec;
+ sPt->u32Second = u32Tmp;
+ } else {
+ u32Tmp = (g_u32hiHour * 10ul);
+ u32Tmp += g_u32loHour;
+ sPt->u32Hour = u32Tmp;
+ u32Tmp = (g_u32hiMin * 10ul);
+ u32Tmp += g_u32loMin;
+ sPt->u32Minute = u32Tmp;
+ u32Tmp = (g_u32hiSec * 10ul);
+ u32Tmp += g_u32loSec;
+ sPt->u32Second = u32Tmp;
+ }
+}
+
+/**
+ * @brief Get RTC Alarm Date and Time
+ *
+ * @param[out] sPt The returned pointer is specified the RTC alarm value. It includes: \n
+ * u32Year: Year value \n
+ * u32Month: Month value \n
+ * u32Day: Day value \n
+ * u32DayOfWeek: Day of week \n
+ * u32Hour: Hour value \n
+ * u32Minute: Minute value \n
+ * u32Second: Second value \n
+ * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
+ * u8AmPm: [RTC_AM / RTC_PM] \n
+ *
+ * @return None
+ *
+ * @details This API is used to get the RTC alarm date and time setting.
+ */
+void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+ uint32_t u32Tmp;
+ sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */
+ sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */
+ /* Get alarm [Date digit] data */
+ RTC_WaitAccessEnable();
+ g_u32hiYear = (RTC->CALM & RTC_CALM_TENYEAR_Msk) >> RTC_CALM_TENYEAR_Pos;
+ g_u32loYear = (RTC->CALM & RTC_CALM_YEAR_Msk) >> RTC_CALM_YEAR_Pos;
+ g_u32hiMonth = (RTC->CALM & RTC_CALM_TENMON_Msk) >> RTC_CALM_TENMON_Pos;
+ g_u32loMonth = (RTC->CALM & RTC_CALM_MON_Msk) >> RTC_CALM_MON_Pos;
+ g_u32hiDay = (RTC->CALM & RTC_CALM_TENDAY_Msk) >> RTC_CALM_TENDAY_Pos;
+ g_u32loDay = (RTC->CALM & RTC_CALM_DAY_Msk) >> RTC_CALM_DAY_Pos;
+ /* Get alarm [Time digit] data */
+ RTC_WaitAccessEnable();
+ g_u32hiHour = (RTC->TALM & RTC_TALM_TENHR_Msk) >> RTC_TALM_TENHR_Pos;
+ g_u32loHour = (RTC->TALM & RTC_TALM_HR_Msk) >> RTC_TALM_HR_Pos;
+ g_u32hiMin = (RTC->TALM & RTC_TALM_TENMIN_Msk) >> RTC_TALM_TENMIN_Pos;
+ g_u32loMin = (RTC->TALM & RTC_TALM_MIN_Msk) >> RTC_TALM_MIN_Pos;
+ g_u32hiSec = (RTC->TALM & RTC_TALM_TENSEC_Msk) >> RTC_TALM_TENSEC_Pos;
+ g_u32loSec = (RTC->TALM & RTC_TALM_SEC_Msk) >> RTC_TALM_SEC_Pos;
+ /* Compute to 20XX year */
+ u32Tmp = (g_u32hiYear * 10ul);
+ u32Tmp += g_u32loYear;
+ sPt->u32Year = u32Tmp + RTC_YEAR2000;
+ /* Compute 0~12 month */
+ u32Tmp = (g_u32hiMonth * 10ul);
+ sPt->u32Month = u32Tmp + g_u32loMonth;
+ /* Compute 0~31 day */
+ u32Tmp = (g_u32hiDay * 10ul);
+ sPt->u32Day = u32Tmp + g_u32loDay;
+
+ /* Compute 12/24 hour */
+ if (sPt->u32TimeScale == RTC_CLOCK_12) {
+ u32Tmp = (g_u32hiHour * 10ul);
+ u32Tmp += g_u32loHour;
+ sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */
+
+ if (sPt->u32Hour >= 21ul) {
+ sPt->u32AmPm = RTC_PM;
+ sPt->u32Hour -= 20ul;
+ } else {
+ sPt->u32AmPm = RTC_AM;
+ }
+
+ u32Tmp = (g_u32hiMin * 10ul);
+ u32Tmp += g_u32loMin;
+ sPt->u32Minute = u32Tmp;
+ u32Tmp = (g_u32hiSec * 10ul);
+ u32Tmp += g_u32loSec;
+ sPt->u32Second = u32Tmp;
+ } else {
+ u32Tmp = (g_u32hiHour * 10ul);
+ u32Tmp += g_u32loHour;
+ sPt->u32Hour = u32Tmp;
+ u32Tmp = (g_u32hiMin * 10ul);
+ u32Tmp += g_u32loMin;
+ sPt->u32Minute = u32Tmp;
+ u32Tmp = (g_u32hiSec * 10ul);
+ u32Tmp += g_u32loSec;
+ sPt->u32Second = u32Tmp;
+ }
+}
+
+/**
+ * @brief Update Current RTC Date and Time
+ *
+ * @param[in] sPt Specify the time property and current date and time. It includes: \n
+ * u32Year: Year value, range between 2000 ~ 2099. \n
+ * u32Month: Month value, range between 1 ~ 12. \n
+ * u32Day: Day value, range between 1 ~ 31. \n
+ * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
+ * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
+ * RTC_SATURDAY] \n
+ * u32Hour: Hour value, range between 0 ~ 23. \n
+ * u32Minute: Minute value, range between 0 ~ 59. \n
+ * u32Second: Second value, range between 0 ~ 59. \n
+ * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
+ * u8AmPm: [RTC_AM / RTC_PM] \n
+ *
+ * @return None
+ *
+ * @details This API is used to update current date and time to RTC.
+ */
+void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+ uint32_t u32RegCAL, u32RegTIME;
+
+ if (sPt == 0ul) {
+ } else {
+ /*-----------------------------------------------------------------------------------------------------*/
+ /* Set RTC 24/12 hour setting and Day of the Week */
+ /*-----------------------------------------------------------------------------------------------------*/
+ RTC_WaitAccessEnable();
+
+ if (sPt->u32TimeScale == RTC_CLOCK_12) {
+ RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
+
+ /*-------------------------------------------------------------------------------------------------*/
+ /* Important, range of 12-hour PM mode is 21 up to 32 */
+ /*-------------------------------------------------------------------------------------------------*/
+ if (sPt->u32AmPm == RTC_PM) {
+ sPt->u32Hour += 20ul;
+ }
+ } else {
+ RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
+ }
+
+ /* Set Day of the Week */
+ RTC_WaitAccessEnable();
+ RTC->WEEKDAY = sPt->u32DayOfWeek;
+ /*-----------------------------------------------------------------------------------------------------*/
+ /* Set RTC Current Date and Time */
+ /*-----------------------------------------------------------------------------------------------------*/
+ u32RegCAL = ((sPt->u32Year - RTC_YEAR2000) / 10ul) << 20;
+ u32RegCAL |= (((sPt->u32Year - RTC_YEAR2000) % 10ul) << 16);
+ u32RegCAL |= ((sPt->u32Month / 10ul) << 12);
+ u32RegCAL |= ((sPt->u32Month % 10ul) << 8);
+ u32RegCAL |= ((sPt->u32Day / 10ul) << 4);
+ u32RegCAL |= (sPt->u32Day % 10ul);
+ u32RegTIME = ((sPt->u32Hour / 10ul) << 20);
+ u32RegTIME |= ((sPt->u32Hour % 10ul) << 16);
+ u32RegTIME |= ((sPt->u32Minute / 10ul) << 12);
+ u32RegTIME |= ((sPt->u32Minute % 10ul) << 8);
+ u32RegTIME |= ((sPt->u32Second / 10ul) << 4);
+ u32RegTIME |= (sPt->u32Second % 10ul);
+ /*-----------------------------------------------------------------------------------------------------*/
+ /* Set RTC Calender and Time Loading */
+ /*-----------------------------------------------------------------------------------------------------*/
+ RTC_WaitAccessEnable();
+ RTC->CAL = (uint32_t)u32RegCAL;
+ RTC_WaitAccessEnable();
+ RTC->TIME = (uint32_t)u32RegTIME;
+ }
+}
+
+/**
+ * @brief Update RTC Alarm Date and Time
+ *
+ * @param[in] sPt Specify the time property and alarm date and time. It includes: \n
+ * u32Year: Year value, range between 2000 ~ 2099. \n
+ * u32Month: Month value, range between 1 ~ 12. \n
+ * u32Day: Day value, range between 1 ~ 31. \n
+ * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
+ * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
+ * RTC_SATURDAY] \n
+ * u32Hour: Hour value, range between 0 ~ 23. \n
+ * u32Minute: Minute value, range between 0 ~ 59. \n
+ * u32Second: Second value, range between 0 ~ 59. \n
+ * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
+ * u8AmPm: [RTC_AM / RTC_PM] \n
+ *
+ * @return None
+ *
+ * @details This API is used to update alarm date and time setting to RTC.
+ */
+void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+ uint32_t u32RegCALM, u32RegTALM;
+
+ if (sPt == 0) {
+ } else {
+ /*-----------------------------------------------------------------------------------------------------*/
+ /* Set RTC 24/12 hour setting and Day of the Week */
+ /*-----------------------------------------------------------------------------------------------------*/
+ RTC_WaitAccessEnable();
+
+ if (sPt->u32TimeScale == RTC_CLOCK_12) {
+ RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
+
+ /*-------------------------------------------------------------------------------------------------*/
+ /* Important, range of 12-hour PM mode is 21 up to 32 */
+ /*-------------------------------------------------------------------------------------------------*/
+ if (sPt->u32AmPm == RTC_PM) {
+ sPt->u32Hour += 20ul;
+ }
+ } else {
+ RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
+ }
+
+ /*-----------------------------------------------------------------------------------------------------*/
+ /* Set RTC Alarm Date and Time */
+ /*-----------------------------------------------------------------------------------------------------*/
+ u32RegCALM = ((sPt->u32Year - RTC_YEAR2000) / 10ul) << 20;
+ u32RegCALM |= (((sPt->u32Year - RTC_YEAR2000) % 10ul) << 16);
+ u32RegCALM |= ((sPt->u32Month / 10ul) << 12);
+ u32RegCALM |= ((sPt->u32Month % 10ul) << 8);
+ u32RegCALM |= ((sPt->u32Day / 10ul) << 4);
+ u32RegCALM |= (sPt->u32Day % 10ul);
+ u32RegTALM = ((sPt->u32Hour / 10ul) << 20);
+ u32RegTALM |= ((sPt->u32Hour % 10ul) << 16);
+ u32RegTALM |= ((sPt->u32Minute / 10ul) << 12);
+ u32RegTALM |= ((sPt->u32Minute % 10ul) << 8);
+ u32RegTALM |= ((sPt->u32Second / 10ul) << 4);
+ u32RegTALM |= (sPt->u32Second % 10ul);
+ RTC_WaitAccessEnable();
+ RTC->CALM = (uint32_t)u32RegCALM;
+ RTC_WaitAccessEnable();
+ RTC->TALM = (uint32_t)u32RegTALM;
+ }
+}
+
+/**
+ * @brief Update RTC Current Date
+ *
+ * @param[in] u32Year The year calendar digit of current RTC setting.
+ * @param[in] u32Month The month calendar digit of current RTC setting.
+ * @param[in] u32Day The day calendar digit of current RTC setting.
+ * @param[in] u32DayOfWeek The Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
+ * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
+ * RTC_SATURDAY]
+ *
+ * @return None
+ *
+ * @details This API is used to update current date to RTC.
+ */
+void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek)
+{
+ uint32_t u32RegCAL;
+ u32RegCAL = ((u32Year - RTC_YEAR2000) / 10ul) << 20;
+ u32RegCAL |= (((u32Year - RTC_YEAR2000) % 10ul) << 16);
+ u32RegCAL |= ((u32Month / 10ul) << 12);
+ u32RegCAL |= ((u32Month % 10ul) << 8);
+ u32RegCAL |= ((u32Day / 10ul) << 4);
+ u32RegCAL |= (u32Day % 10ul);
+ /* Set Day of the Week */
+ RTC_WaitAccessEnable();
+ RTC->WEEKDAY = u32DayOfWeek & RTC_WEEKDAY_WEEKDAY_Msk;
+ /* Set RTC Calender Loading */
+ RTC_WaitAccessEnable();
+ RTC->CAL = (uint32_t)u32RegCAL;
+}
+
+/**
+ * @brief Update RTC Current Time
+ *
+ * @param[in] u32Hour The hour time digit of current RTC setting.
+ * @param[in] u32Minute The minute time digit of current RTC setting.
+ * @param[in] u32Second The second time digit of current RTC setting.
+ * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24]
+ * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM]
+ *
+ * @return None
+ *
+ * @details This API is used to update current time to RTC.
+ */
+void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm)
+{
+ uint32_t u32RegTIME;
+
+ /* Important, range of 12-hour PM mode is 21 up to 32 */
+ if ((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM)) {
+ u32Hour += 20ul;
+ }
+
+ u32RegTIME = ((u32Hour / 10ul) << 20);
+ u32RegTIME |= ((u32Hour % 10ul) << 16);
+ u32RegTIME |= ((u32Minute / 10ul) << 12);
+ u32RegTIME |= ((u32Minute % 10ul) << 8);
+ u32RegTIME |= ((u32Second / 10ul) << 4);
+ u32RegTIME |= (u32Second % 10ul);
+ /*-----------------------------------------------------------------------------------------------------*/
+ /* Set RTC 24/12 hour setting and Day of the Week */
+ /*-----------------------------------------------------------------------------------------------------*/
+ RTC_WaitAccessEnable();
+
+ if (u32TimeMode == RTC_CLOCK_12) {
+ RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
+ } else {
+ RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
+ }
+
+ RTC_WaitAccessEnable();
+ RTC->TIME = (uint32_t)u32RegTIME;
+}
+
+/**
+ * @brief Update RTC Alarm Date
+ *
+ * @param[in] u32Year The year calendar digit of RTC alarm setting.
+ * @param[in] u32Month The month calendar digit of RTC alarm setting.
+ * @param[in] u32Day The day calendar digit of RTC alarm setting.
+ *
+ * @return None
+ *
+ * @details This API is used to update alarm date setting to RTC.
+ */
+void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day)
+{
+ uint32_t u32RegCALM;
+ u32RegCALM = ((u32Year - RTC_YEAR2000) / 10ul) << 20;
+ u32RegCALM |= (((u32Year - RTC_YEAR2000) % 10ul) << 16);
+ u32RegCALM |= ((u32Month / 10ul) << 12);
+ u32RegCALM |= ((u32Month % 10ul) << 8);
+ u32RegCALM |= ((u32Day / 10ul) << 4);
+ u32RegCALM |= (u32Day % 10ul);
+ RTC_WaitAccessEnable();
+ /* Set RTC Alarm Date */
+ RTC->CALM = (uint32_t)u32RegCALM;
+}
+
+/**
+ * @brief Update RTC Alarm Time
+ *
+ * @param[in] u32Hour The hour time digit of RTC alarm setting.
+ * @param[in] u32Minute The minute time digit of RTC alarm setting.
+ * @param[in] u32Second The second time digit of RTC alarm setting.
+ * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24]
+ * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM]
+ *
+ * @return None
+ *
+ * @details This API is used to update alarm time setting to RTC.
+ */
+void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm)
+{
+ uint32_t u32RegTALM;
+
+ /* Important, range of 12-hour PM mode is 21 up to 32 */
+ if ((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM)) {
+ u32Hour += 20ul;
+ }
+
+ u32RegTALM = ((u32Hour / 10ul) << 20);
+ u32RegTALM |= ((u32Hour % 10ul) << 16);
+ u32RegTALM |= ((u32Minute / 10ul) << 12);
+ u32RegTALM |= ((u32Minute % 10ul) << 8);
+ u32RegTALM |= ((u32Second / 10ul) << 4);
+ u32RegTALM |= (u32Second % 10ul);
+ /*-----------------------------------------------------------------------------------------------------*/
+ /* Set RTC 24/12 hour setting and Day of the Week */
+ /*-----------------------------------------------------------------------------------------------------*/
+ RTC_WaitAccessEnable();
+
+ if (u32TimeMode == RTC_CLOCK_12) {
+ RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
+ } else {
+ RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
+ }
+
+ /* Set RTC Alarm Time */
+ RTC_WaitAccessEnable();
+ RTC->TALM = (uint32_t)u32RegTALM;
+}
+
+/**
+ * @brief Set RTC Alarm Date Mask Function
+ *
+ * @param[in] u8IsTenYMsk 1: enable 10-Year digit alarm mask; 0: disabled.
+ * @param[in] u8IsYMsk 1: enable 1-Year digit alarm mask; 0: disabled.
+ * @param[in] u8IsTenMMsk 1: enable 10-Mon digit alarm mask; 0: disabled.
+ * @param[in] u8IsMMsk 1: enable 1-Mon digit alarm mask; 0: disabled.
+ * @param[in] u8IsTenDMsk 1: enable 10-Day digit alarm mask; 0: disabled.
+ * @param[in] u8IsDMsk 1: enable 1-Day digit alarm mask; 0: disabled.
+ *
+ * @return None
+ *
+ * @details This API is used to enable or disable RTC alarm date mask function.
+ */
+void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk)
+{
+ RTC_WaitAccessEnable();
+ RTC->CAMSK = ((uint32_t)u8IsTenYMsk << RTC_CAMSK_MTENYEAR_Pos) |
+ ((uint32_t)u8IsYMsk << RTC_CAMSK_MYEAR_Pos) |
+ ((uint32_t)u8IsTenMMsk << RTC_CAMSK_MTENMON_Pos) |
+ ((uint32_t)u8IsMMsk << RTC_CAMSK_MMON_Pos) |
+ ((uint32_t)u8IsTenDMsk << RTC_CAMSK_MTENDAY_Pos) |
+ ((uint32_t)u8IsDMsk << RTC_CAMSK_MDAY_Pos);
+}
+
+/**
+ * @brief Set RTC Alarm Time Mask Function
+ *
+ * @param[in] u8IsTenHMsk 1: enable 10-Hour digit alarm mask; 0: disabled.
+ * @param[in] u8IsHMsk 1: enable 1-Hour digit alarm mask; 0: disabled.
+ * @param[in] u8IsTenMMsk 1: enable 10-Min digit alarm mask; 0: disabled.
+ * @param[in] u8IsMMsk 1: enable 1-Min digit alarm mask; 0: disabled.
+ * @param[in] u8IsTenSMsk 1: enable 10-Sec digit alarm mask; 0: disabled.
+ * @param[in] u8IsSMsk 1: enable 1-Sec digit alarm mask; 0: disabled.
+ *
+ * @return None
+ *
+ * @details This API is used to enable or disable RTC alarm time mask function.
+ */
+void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk)
+{
+ RTC_WaitAccessEnable();
+ RTC->TAMSK = ((uint32_t)u8IsTenHMsk << RTC_TAMSK_MTENHR_Pos) |
+ ((uint32_t)u8IsHMsk << RTC_TAMSK_MHR_Pos) |
+ ((uint32_t)u8IsTenMMsk << RTC_TAMSK_MTENMIN_Pos) |
+ ((uint32_t)u8IsMMsk << RTC_TAMSK_MMIN_Pos) |
+ ((uint32_t)u8IsTenSMsk << RTC_TAMSK_MTENSEC_Pos) |
+ ((uint32_t)u8IsSMsk << RTC_TAMSK_MSEC_Pos);
+}
+
+/**
+ * @brief Get Day of the Week
+ *
+ * @param None
+ *
+ * @retval 0 Sunday
+ * @retval 1 Monday
+ * @retval 2 Tuesday
+ * @retval 3 Wednesday
+ * @retval 4 Thursday
+ * @retval 5 Friday
+ * @retval 6 Saturday
+ *
+ * @details This API is used to get day of the week of current RTC date.
+ */
+uint32_t RTC_GetDayOfWeek(void)
+{
+ return (RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk);
+}
+
+/**
+ * @brief Set RTC Tick Period Time
+ *
+ * @param[in] u32TickSelection It is used to set the RTC tick period time for Periodic Time Tick request. \n
+ * It consists of:
+ * - \ref RTC_TICK_1_SEC : Time tick is 1 second
+ * - \ref RTC_TICK_1_2_SEC : Time tick is 1/2 second
+ * - \ref RTC_TICK_1_4_SEC : Time tick is 1/4 second
+ * - \ref RTC_TICK_1_8_SEC : Time tick is 1/8 second
+ * - \ref RTC_TICK_1_16_SEC : Time tick is 1/16 second
+ * - \ref RTC_TICK_1_32_SEC : Time tick is 1/32 second
+ * - \ref RTC_TICK_1_64_SEC : Time tick is 1/64 second
+ * - \ref RTC_TICK_1_128_SEC : Time tick is 1/128 second
+ *
+ * @return None
+ *
+ * @details This API is used to set RTC tick period time for each tick interrupt.
+ */
+void RTC_SetTickPeriod(uint32_t u32TickSelection)
+{
+ RTC_WaitAccessEnable();
+ RTC->TICK = (RTC->TICK & ~RTC_TICK_TICK_Msk) | u32TickSelection;
+}
+
+/**
+ * @brief Enable RTC Interrupt
+ *
+ * @param[in] u32IntFlagMask Specify the interrupt source. It consists of:
+ * - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt
+ * - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt
+ * - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt
+ * - \ref RTC_INTEN_TAMP1IEN_Msk : Tamper 1 Pin Event Detection interrupt
+ * - \ref RTC_INTEN_TAMP2IEN_Msk : Tamper 2 Pin Event Detection interrupt
+ * - \ref RTC_INTEN_TAMP3IEN_Msk : Tamper 3 Pin Event Detection interrupt
+ * - \ref RTC_INTEN_TAMP4IEN_Msk : Tamper 4 Pin Event Detection interrupt
+ * - \ref RTC_INTEN_TAMP5IEN_Msk : Tamper 5 Pin Event Detection interrupt
+ *
+ * @return None
+ *
+ * @details This API is used to enable the specify RTC interrupt function.
+ */
+void RTC_EnableInt(uint32_t u32IntFlagMask)
+{
+ RTC_WaitAccessEnable();
+ RTC->INTEN |= u32IntFlagMask;
+}
+
+/**
+ * @brief Disable RTC Interrupt
+ *
+ * @param[in] u32IntFlagMask Specify the interrupt source. It consists of:
+ * - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt
+ * - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt
+ * - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt
+ * - \ref RTC_INTEN_TAMP1IEN_Msk : Tamper 1 Pin Event Detection interrupt
+ * - \ref RTC_INTEN_TAMP2IEN_Msk : Tamper 2 Pin Event Detection interrupt
+ * - \ref RTC_INTEN_TAMP3IEN_Msk : Tamper 3 Pin Event Detection interrupt
+ * - \ref RTC_INTEN_TAMP4IEN_Msk : Tamper 4 Pin Event Detection interrupt
+ * - \ref RTC_INTEN_TAMP5IEN_Msk : Tamper 5 Pin Event Detection interrupt
+ *
+ * @return None
+ *
+ * @details This API is used to disable the specify RTC interrupt function.
+ */
+void RTC_DisableInt(uint32_t u32IntFlagMask)
+{
+ RTC_WaitAccessEnable();
+ RTC->INTEN &= ~u32IntFlagMask;
+ RTC_WaitAccessEnable();
+ RTC->INTSTS = u32IntFlagMask;
+}
+
+/**
+ * @brief Enable Spare Registers Access
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This API is used to enable the spare registers 0~19 can be accessed.
+ */
+void RTC_EnableSpareAccess(void)
+{
+ RTC_WaitAccessEnable();
+ RTC->SPRCTL |= RTC_SPRCTL_SPRRWEN_Msk;
+}
+
+/**
+ * @brief Disable Spare Register
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This API is used to disable the spare register 0~19 cannot be accessed.
+ */
+void RTC_DisableSpareRegister(void)
+{
+ RTC_WaitAccessEnable();
+ RTC->SPRCTL &= ~RTC_SPRCTL_SPRRWEN_Msk;
+}
+
+/**
+ * @brief Static Tamper Detect
+ *
+ * @param[in] u32TamperSelect Tamper pin select. Possible options are
+ * - \ref RTC_TAMPER5_SELECT
+ * - \ref RTC_TAMPER4_SELECT
+ * - \ref RTC_TAMPER3_SELECT
+ * - \ref RTC_TAMPER2_SELECT
+ * - \ref RTC_TAMPER1_SELECT
+ * - \ref RTC_TAMPER0_SELECT
+ *
+ * @param[in] u32DetecLevel Tamper pin detection level select. Possible options are
+ * - \ref RTC_TAMPER_HIGH_LEVEL_DETECT
+ * - \ref RTC_TAMPER_LOW_LEVEL_DETECT
+ *
+ * @param[in] u32DebounceEn Tamper pin de-bounce enable
+ * - \ref RTC_TAMPER_DEBOUNCE_ENABLE
+ * - \ref RTC_TAMPER_DEBOUNCE_DISABLE
+ *
+ * @return None
+ *
+ * @details This API is used to enable the tamper pin detect function with specify trigger condition.
+ */
+void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn)
+{
+ uint32_t i;
+ uint32_t u32Reg;
+ uint32_t u32TmpReg;
+ RTC_WaitAccessEnable();
+ u32Reg = RTC->TAMPCTL;
+ u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | (u32DetecLevel << RTC_TAMPCTL_TAMP0LV_Pos) |
+ (u32DebounceEn << RTC_TAMPCTL_TAMP0DBEN_Pos));
+
+ for (i = 0ul; i < MAX_TAMPER_PIN_NUM; i++) {
+ if (u32TamperSelect & (0x1ul << i)) {
+ u32Reg &= ~((RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP0LV_Msk | RTC_TAMPCTL_TAMP0DBEN_Msk) << (i * 4ul));
+ u32Reg |= (u32TmpReg << (i * 4ul));
+ }
+ }
+
+ RTC_WaitAccessEnable();
+ RTC->TAMPCTL = u32Reg;
+}
+
+/**
+ * @brief Static Tamper Disable
+ *
+ * @param[in] u32TamperSelect Tamper pin select. Possible options are
+ * - \ref RTC_TAMPER5_SELECT
+ * - \ref RTC_TAMPER4_SELECT
+ * - \ref RTC_TAMPER3_SELECT
+ * - \ref RTC_TAMPER2_SELECT
+ * - \ref RTC_TAMPER1_SELECT
+ * - \ref RTC_TAMPER0_SELECT
+ *
+ * @return None
+ *
+ * @details This API is used to disable the static tamper pin detect.
+ */
+void RTC_StaticTamperDisable(uint32_t u32TamperSelect)
+{
+ uint32_t i;
+ uint32_t u32Reg;
+ uint32_t u32TmpReg;
+ RTC_WaitAccessEnable();
+ u32Reg = RTC->TAMPCTL;
+ u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk);
+
+ for (i = 0ul; i < MAX_TAMPER_PIN_NUM; i++) {
+ if (u32TamperSelect & (0x1ul << i)) {
+ u32Reg &= ~(u32TmpReg << (i * 4ul));
+ }
+ }
+
+ RTC_WaitAccessEnable();
+ RTC->TAMPCTL = u32Reg;
+}
+
+/**
+ * @brief Dynamic Tamper Detect
+ *
+ * @param[in] u32PairSel Tamper pin detection enable. Possible options are
+ * - \ref RTC_PAIR0_SELECT
+ * - \ref RTC_PAIR1_SELECT
+ * - \ref RTC_PAIR2_SELECT
+ *
+ * @param[in] u32DebounceEn Tamper pin de-bounce enable
+ * - \ref RTC_TAMPER_DEBOUNCE_ENABLE
+ * - \ref RTC_TAMPER_DEBOUNCE_DISABLE
+ *
+ * @param[in] u32Pair1Source Dynamic Pair 1 Input Source Select
+ * 0: Pair 1 source select tamper 2
+ * 1: Pair 1 source select tamper 0
+ *
+ * @param[in] u32Pair2Source Dynamic Pair 2 Input Source Select
+ * 0: Pair 2 source select tamper 4
+ * 1: Pair 2 source select tamper 0
+ *
+ * @return None
+ *
+ * @details This API is used to enable the dynamic tamper.
+ */
+void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source)
+{
+ uint32_t i;
+ uint32_t u32Reg;
+ uint32_t u32TmpReg;
+ uint32_t u32Tamper2Debounce, u32Tamper4Debounce;
+ RTC_WaitAccessEnable();
+ u32Reg = RTC->TAMPCTL;
+ u32Tamper2Debounce = u32Reg & RTC_TAMPCTL_TAMP2DBEN_Msk;
+ u32Tamper4Debounce = u32Reg & RTC_TAMPCTL_TAMP4DBEN_Msk;
+ u32Reg &= ~(RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_TAMP2EN_Msk |
+ RTC_TAMPCTL_TAMP3EN_Msk | RTC_TAMPCTL_TAMP4EN_Msk | RTC_TAMPCTL_TAMP5EN_Msk);
+ u32Reg &= ~(RTC_TAMPCTL_DYN1ISS_Msk | RTC_TAMPCTL_DYN2ISS_Msk);
+ u32Reg |= ((u32Pair1Source & 0x1ul) << RTC_TAMPCTL_DYN1ISS_Pos) | ((u32Pair2Source & 0x1ul) << RTC_TAMPCTL_DYN2ISS_Pos);
+
+ if (u32DebounceEn) {
+ u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk |
+ RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk);
+ } else {
+ u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk);
+ }
+
+ for (i = 0ul; i < MAX_PAIR_NUM; i++) {
+ if (u32PairSel & (0x1ul << i)) {
+ u32Reg &= ~((RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk) << (i * 8ul));
+ u32Reg |= (u32TmpReg << (i * 8ul));
+ }
+ }
+
+ if ((u32Pair1Source) && (u32PairSel & RTC_PAIR1_SELECT)) {
+ u32Reg &= ~RTC_TAMPCTL_TAMP2EN_Msk;
+ u32Reg |= u32Tamper2Debounce;
+ }
+
+ if ((u32Pair2Source) && (u32PairSel & RTC_PAIR2_SELECT)) {
+ u32Reg &= ~RTC_TAMPCTL_TAMP4EN_Msk;
+ u32Reg |= u32Tamper4Debounce;
+ }
+
+ RTC_WaitAccessEnable();
+ RTC->TAMPCTL = u32Reg;
+}
+
+/**
+ * @brief Dynamic Tamper Disable
+ *
+ * @param[in] u32PairSel Tamper pin detection enable. Possible options are
+ * - \ref RTC_PAIR0_SELECT
+ * - \ref RTC_PAIR1_SELECT
+ * - \ref RTC_PAIR2_SELECT
+ *
+ * @return None
+ *
+ * @details This API is used to disable the dynamic tamper.
+ */
+void RTC_DynamicTamperDisable(uint32_t u32PairSel)
+{
+ uint32_t i;
+ uint32_t u32Reg;
+ uint32_t u32TmpReg;
+ uint32_t u32Tamper2En = 0ul, u32Tamper4En = 0ul;
+ RTC_WaitAccessEnable();
+ u32Reg = RTC->TAMPCTL;
+
+ if ((u32Reg & RTC_TAMPCTL_DYN1ISS_Msk) && (u32PairSel & RTC_PAIR1_SELECT)) {
+ u32Tamper2En = u32Reg & RTC_TAMPCTL_TAMP2EN_Msk;
+ }
+
+ if ((u32Reg & RTC_TAMPCTL_DYN2ISS_Msk) && (u32PairSel & RTC_PAIR2_SELECT)) {
+ u32Tamper4En = u32Reg & RTC_TAMPCTL_TAMP4EN_Msk;
+ }
+
+ u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk);
+
+ for (i = 0ul; i < MAX_PAIR_NUM; i++) {
+ if (u32PairSel & (0x1ul << i)) {
+ u32Reg &= ~(u32TmpReg << ((i * 8ul)));
+ }
+ }
+
+ u32Reg |= (u32Tamper2En | u32Tamper4En);
+ RTC_WaitAccessEnable();
+ RTC->TAMPCTL = u32Reg;
+}
+
+/**
+ * @brief Config dynamic tamper
+ *
+ * @param[in] u32ChangeRate The dynamic tamper output change rate
+ * - \ref RTC_2POW10_CLK
+ * - \ref RTC_2POW11_CLK
+ * - \ref RTC_2POW12_CLK
+ * - \ref RTC_2POW13_CLK
+ * - \ref RTC_2POW14_CLK
+ * - \ref RTC_2POW15_CLK
+ * - \ref RTC_2POW16_CLK
+ * - \ref RTC_2POW17_CLK
+ *
+ * @param[in] u32SeedReload Reload new seed or not
+ * 0: not reload new seed
+ * 1: reload new seed
+ *
+ * @param[in] u32RefPattern Reference pattern
+ * - \ref REF_RANDOM_PATTERN
+ * - \ref REF_PREVIOUS_PATTERN
+ * - \ref REF_SEED
+ *
+ * @param[in] u32Seed Seed Value (0x0 ~ 0xFFFFFFFF)
+ *
+ * @return None
+ *
+ * @details This API is used to config dynamic tamper setting.
+ */
+void RTC_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed)
+{
+ uint32_t u32Reg;
+ RTC_WaitAccessEnable();
+ u32Reg = RTC->TAMPCTL;
+ u32Reg &= ~(RTC_TAMPCTL_DYNSRC_Msk | RTC_TAMPCTL_SEEDRLD_Msk | RTC_TAMPCTL_DYNRATE_Msk);
+ u32Reg |= (u32ChangeRate) | ((u32SeedReload & 0x1ul) << RTC_TAMPCTL_SEEDRLD_Pos) |
+ ((u32RefPattern & 0x3ul) << RTC_TAMPCTL_DYNSRC_Pos);
+ RTC_WaitAccessEnable();
+ RTC->TAMPSEED = u32Seed; /* need set seed value before re-load seed */
+ RTC_WaitAccessEnable();
+ RTC->TAMPCTL = u32Reg;
+}
+
+/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group RTC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/StdDriver/src/m480_sys.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/StdDriver/src/m480_sys.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,273 @@
+/**************************************************************************//**
+ * @file sys.c
+ * @version V1.00
+ * @brief M480 series SYS driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************/
+
+#include "NuMicro.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup SYS_Driver SYS Driver
+ @{
+*/
+
+
+/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions
+ @{
+*/
+
+/**
+ * @brief Clear reset source
+ * @param[in] u32Src is system reset source. Including :
+ * - \ref SYS_RSTSTS_CPULKRF_Msk
+ * - \ref SYS_RSTSTS_CPURF_Msk
+ * - \ref SYS_RSTSTS_SYSRF_Msk
+ * - \ref SYS_RSTSTS_BODRF_Msk
+ * - \ref SYS_RSTSTS_LVRF_Msk
+ * - \ref SYS_RSTSTS_WDTRF_Msk
+ * - \ref SYS_RSTSTS_PINRF_Msk
+ * - \ref SYS_RSTSTS_PORF_Msk
+ * @return None
+ * @details This function clear the selected system reset source.
+ */
+void SYS_ClearResetSrc(uint32_t u32Src)
+{
+ SYS->RSTSTS |= u32Src;
+}
+
+/**
+ * @brief Get Brown-out detector output status
+ * @param None
+ * @retval 0 System voltage is higher than BODVL setting or BODEN is 0.
+ * @retval 1 System voltage is lower than BODVL setting.
+ * @details This function get Brown-out detector output status.
+ */
+uint32_t SYS_GetBODStatus(void)
+{
+ return ((SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) >> SYS_BODCTL_BODOUT_Pos);
+}
+
+/**
+ * @brief Get reset status register value
+ * @param None
+ * @return Reset source
+ * @details This function get the system reset status register value.
+ */
+uint32_t SYS_GetResetSrc(void)
+{
+ return (SYS->RSTSTS);
+}
+
+/**
+ * @brief Check if register is locked nor not
+ * @param None
+ * @retval 0 Write-protection function is disabled.
+ * 1 Write-protection function is enabled.
+ * @details This function check register write-protection bit setting.
+ */
+uint32_t SYS_IsRegLocked(void)
+{
+ return SYS->REGLCTL & 1UL ? 0UL : 1UL;
+}
+
+/**
+ * @brief Get product ID
+ * @param None
+ * @return Product ID
+ * @details This function get product ID.
+ */
+uint32_t SYS_ReadPDID(void)
+{
+ return SYS->PDID;
+}
+
+/**
+ * @brief Reset chip with chip reset
+ * @param None
+ * @return None
+ * @details This function reset chip with chip reset.
+ * The register write-protection function should be disabled before using this function.
+ */
+void SYS_ResetChip(void)
+{
+ SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk;
+}
+
+/**
+ * @brief Reset chip with CPU reset
+ * @param None
+ * @return None
+ * @details This function reset CPU with CPU reset.
+ * The register write-protection function should be disabled before using this function.
+ */
+void SYS_ResetCPU(void)
+{
+ SYS->IPRST0 |= SYS_IPRST0_CPURST_Msk;
+}
+
+/**
+ * @brief Reset selected module
+ * @param[in] u32ModuleIndex is module index. Including :
+ * - \ref PDMA_RST
+ * - \ref EBI_RST
+ * - \ref EMAC_RST
+ * - \ref SDH0_RST
+ * - \ref CRC_RST
+ * - \ref HSUSBD_RST
+ * - \ref CRPT_RST
+ * - \ref SPIM_RST
+ * - \ref USBH_RST
+ * - \ref SDH1_RST
+ * - \ref GPIO_RST
+ * - \ref TMR0_RST
+ * - \ref TMR1_RST
+ * - \ref TMR2_RST
+ * - \ref TMR3_RST
+ * - \ref ACMP01_RST
+ * - \ref I2C0_RST
+ * - \ref I2C1_RST
+ * - \ref I2C2_RST
+ * - \ref QSPI0_RST
+ * - \ref SPI0_RST
+ * - \ref SPI1_RST
+ * - \ref SPI2_RST
+ * - \ref UART0_RST
+ * - \ref UART1_RST
+ * - \ref UART2_RST
+ * - \ref UART3_RST
+ * - \ref UART4_RST
+ * - \ref UART5_RST
+ * - \ref CAN0_RST
+ * - \ref CAN1_RST
+ * - \ref USBD_RST
+ * - \ref EADC_RST
+ * - \ref I2S0_RST
+ * - \ref SC0_RST
+ * - \ref SC1_RST
+ * - \ref SC2_RST
+ * - \ref SPI3_RST
+ * - \ref USCI0_RST
+ * - \ref USCI1_RST
+ * - \ref DAC_RST
+ * - \ref EPWM0_RST
+ * - \ref EPWM1_RST
+ * - \ref BPWM0_RST
+ * - \ref BPWM1_RST
+ * - \ref QEI0_RST
+ * - \ref QEI1_RST
+ * - \ref ECAP0_RST
+ * - \ref ECAP1_RST
+ * - \ref OPA_RST
+ * @return None
+ * @details This function reset selected module.
+ */
+void SYS_ResetModule(uint32_t u32ModuleIndex)
+{
+ uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL;
+ /* Generate reset signal to the corresponding module */
+ u32tmpVal = (1UL << (u32ModuleIndex & 0x00ffffffUL));
+ u32tmpAddr = (uint32_t)&SYS->IPRST0 + ((u32ModuleIndex >> 24UL));
+ *(uint32_t *)u32tmpAddr |= u32tmpVal;
+ /* Release corresponding module from reset state */
+ u32tmpVal = ~(1UL << (u32ModuleIndex & 0x00ffffffUL));
+ *(uint32_t *)u32tmpAddr &= u32tmpVal;
+}
+
+/**
+ * @brief Enable and configure Brown-out detector function
+ * @param[in] i32Mode is reset or interrupt mode. Including :
+ * - \ref SYS_BODCTL_BOD_RST_EN
+ * - \ref SYS_BODCTL_BOD_INTERRUPT_EN
+ * @param[in] u32BODLevel is Brown-out voltage level. Including :
+ * - \ref SYS_BODCTL_BODVL_3_0V
+ * - \ref SYS_BODCTL_BODVL_2_8V
+ * - \ref SYS_BODCTL_BODVL_2_6V
+ * - \ref SYS_BODCTL_BODVL_2_4V
+ * - \ref SYS_BODCTL_BODVL_2_2V
+ * - \ref SYS_BODCTL_BODVL_2_0V
+ * - \ref SYS_BODCTL_BODVL_1_8V
+ * - \ref SYS_BODCTL_BODVL_1_6V
+ * @return None
+ * @details This function configure Brown-out detector reset or interrupt mode, enable Brown-out function and set Brown-out voltage level.
+ * The register write-protection function should be disabled before using this function.
+ */
+void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel)
+{
+ /* Enable Brown-out Detector function */
+ SYS->BODCTL |= SYS_BODCTL_BODEN_Msk;
+ /* Enable Brown-out interrupt or reset function */
+ SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODRSTEN_Msk) | (uint32_t)i32Mode;
+ /* Select Brown-out Detector threshold voltage */
+ SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | u32BODLevel;
+}
+
+/**
+ * @brief Disable Brown-out detector function
+ * @param None
+ * @return None
+ * @details This function disable Brown-out detector function.
+ * The register write-protection function should be disabled before using this function.
+ */
+void SYS_DisableBOD(void)
+{
+ SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk;
+}
+
+/**
+ * @brief Set Power Level
+ * @param[in] u32PowerLevel is power level setting. Including :
+ * - \ref SYS_PLCTL_PLSEL_PL0
+ * - \ref SYS_PLCTL_PLSEL_PL1
+ * @return None
+ * @details This function select power level.
+ * The register write-protection function should be disabled before using this function.
+ */
+void SYS_SetPowerLevel(uint32_t u32PowerLevel)
+{
+ /* Set power voltage level */
+ SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | (u32PowerLevel);
+}
+
+/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SYS_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/StdDriver/src/m480_uart.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/StdDriver/src/m480_uart.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,587 @@
+/**************************************************************************//**
+ * @file uart.c
+ * @version V3.00
+ * @brief M480 series UART driver source file
+ *
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************/
+
+#include <stdio.h>
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup UART_Driver UART Driver
+ @{
+*/
+
+/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions
+ @{
+*/
+
+/**
+ * @brief Clear UART specified interrupt flag
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32InterruptFlag The specified interrupt of UART module.
+ * - \ref UART_INTSTS_LININT_Msk : LIN bus interrupt
+ * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt
+ * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error interrupt
+ * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status interrupt
+ * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status interrupt
+ *
+ * @return None
+ *
+ * @details The function is used to clear UART specified interrupt flag.
+ */
+
+void UART_ClearIntFlag(UART_T *uart, uint32_t u32InterruptFlag)
+{
+ if (u32InterruptFlag & UART_INTSTS_RLSINT_Msk) { /* Clear Receive Line Status Interrupt */
+ uart->FIFOSTS = UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_PEF_Msk;
+ uart->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk;
+ }
+
+ if (u32InterruptFlag & UART_INTSTS_MODEMINT_Msk) { /* Clear Modem Status Interrupt */
+ uart->MODEMSTS |= UART_MODEMSTS_CTSDETF_Msk;
+ } else {
+ }
+
+ if (u32InterruptFlag & UART_INTSTS_BUFERRINT_Msk) { /* Clear Buffer Error Interrupt */
+ uart->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk | UART_FIFOSTS_TXOVIF_Msk;
+ }
+
+ if (u32InterruptFlag & UART_INTSTS_WKINT_Msk) { /* Clear Wake-up Interrupt */
+ uart->WKSTS = UART_WKSTS_CTSWKF_Msk | UART_WKSTS_DATWKF_Msk |
+ UART_WKSTS_RFRTWKF_Msk | UART_WKSTS_RS485WKF_Msk |
+ UART_WKSTS_TOUTWKF_Msk;
+ }
+
+ if (u32InterruptFlag & UART_INTSTS_LININT_Msk) { /* Clear LIN Bus Interrupt */
+ uart->INTSTS = UART_INTSTS_LINIF_Msk;
+ uart->LINSTS = UART_LINSTS_BITEF_Msk | UART_LINSTS_BRKDETF_Msk |
+ UART_LINSTS_SLVSYNCF_Msk | UART_LINSTS_SLVIDPEF_Msk |
+ UART_LINSTS_SLVHEF_Msk | UART_LINSTS_SLVHDETF_Msk ;
+ }
+}
+
+
+/**
+ * @brief Disable UART interrupt
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ *
+ * @return None
+ *
+ * @details The function is used to disable UART interrupt.
+ */
+void UART_Close(UART_T *uart)
+{
+ uart->INTEN = 0ul;
+}
+
+
+/**
+ * @brief Disable UART auto flow control function
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ *
+ * @return None
+ *
+ * @details The function is used to disable UART auto flow control.
+ */
+void UART_DisableFlowCtrl(UART_T *uart)
+{
+ uart->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
+}
+
+
+/**
+ * @brief Disable UART specified interrupt
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32InterruptFlag The specified interrupt of UART module.
+ * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt
+ * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt
+ * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
+ * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
+ * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt
+ * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt
+ * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
+ * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt *
+ *
+ * @return None
+ *
+ * @details The function is used to disable UART specified interrupt and disable NVIC UART IRQ.
+ */
+void UART_DisableInt(UART_T *uart, uint32_t u32InterruptFlag)
+{
+ /* Disable UART specified interrupt */
+ UART_DISABLE_INT(uart, u32InterruptFlag);
+}
+
+
+/**
+ * @brief Enable UART auto flow control function
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ *
+ * @return None
+ *
+ * @details The function is used to Enable UART auto flow control.
+ */
+void UART_EnableFlowCtrl(UART_T *uart)
+{
+ /* Set RTS pin output is low level active */
+ uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
+ /* Set CTS pin input is low level active */
+ uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
+ /* Set RTS and CTS auto flow control enable */
+ uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk;
+}
+
+
+/**
+ * @brief The function is used to enable UART specified interrupt and enable NVIC UART IRQ.
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32InterruptFlag The specified interrupt of UART module:
+ * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt
+ * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt
+ * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
+ * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
+ * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt
+ * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt
+ * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
+ * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt *
+ *
+ * @return None
+ *
+ * @details The function is used to enable UART specified interrupt and enable NVIC UART IRQ.
+ */
+void UART_EnableInt(UART_T *uart, uint32_t u32InterruptFlag)
+{
+ /* Enable UART specified interrupt */
+ UART_ENABLE_INT(uart, u32InterruptFlag);
+}
+
+
+/**
+ * @brief Open and set UART function
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32baudrate The baudrate of UART module.
+ *
+ * @return None
+ *
+ * @details This function use to enable UART function and set baud-rate.
+ */
+void UART_Open(UART_T *uart, uint32_t u32baudrate)
+{
+ uint32_t u32UartClkSrcSel = 0ul, u32UartClkDivNum = 0ul;
+ uint32_t u32ClkTbl[4] = {__HXT, 0ul, __LXT, __HIRC};
+ uint32_t u32Baud_Div = 0ul;
+
+ if (uart == (UART_T *)UART0) {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = ((uint32_t)(CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk)) >> CLK_CLKSEL1_UART0SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos;
+ } else if (uart == (UART_T *)UART1) {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos;
+ } else if (uart == (UART_T *)UART2) {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos;
+ } else if (uart == (UART_T *)UART3) {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos;
+ } else if (uart == (UART_T *)UART4) {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos;
+ } else if (uart == (UART_T *)UART5) {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos;
+ }
+
+ /* Select UART function */
+ uart->FUNCSEL = UART_FUNCSEL_UART;
+ /* Set UART line configuration */
+ uart->LINE = UART_WORD_LEN_8 | _UART_PARITY_NONE | UART_STOP_BIT_1;
+ /* Set UART Rx and RTS trigger level */
+ uart->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk);
+
+ /* Get PLL clock frequency if UART clock source selection is PLL */
+ if (u32UartClkSrcSel == 1ul) {
+ u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
+ }
+
+ /* Set UART baud rate */
+ if (u32baudrate != 0ul) {
+ u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate);
+
+ if (u32Baud_Div > 0xFFFFul) {
+ uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate));
+ } else {
+ uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
+ }
+ }
+}
+
+
+/**
+ * @brief Read UART data
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] pu8RxBuf The buffer to receive the data of receive FIFO.
+ * @param[in] u32ReadBytes The the read bytes number of data.
+ *
+ * @return u32Count Receive byte count
+ *
+ * @details The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf.
+ */
+uint32_t UART_Read(UART_T *uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes)
+{
+ uint32_t u32Count, u32delayno;
+ uint32_t u32Exit = 0ul;
+
+ for (u32Count = 0ul; u32Count < u32ReadBytes; u32Count++) {
+ u32delayno = 0ul;
+
+ while (uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) { /* Check RX empty => failed */
+ u32delayno++;
+
+ if (u32delayno >= 0x40000000ul) {
+ u32Exit = 1ul;
+ break;
+ } else {
+ }
+ }
+
+ if (u32Exit == 1ul) {
+ break;
+ } else {
+ pu8RxBuf[u32Count] = (uint8_t)uart->DAT; /* Get Data from UART RX */
+ }
+ }
+
+ return u32Count;
+}
+
+
+/**
+ * @brief Set UART line configuration
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32baudrate The register value of baudrate of UART module.
+ * If u32baudrate = 0, UART baudrate will not change.
+ * @param[in] u32data_width The data length of UART module.
+ * - \ref UART_WORD_LEN_5
+ * - \ref UART_WORD_LEN_6
+ * - \ref UART_WORD_LEN_7
+ * - \ref UART_WORD_LEN_8
+ * @param[in] u32parity The parity setting (none/odd/even/mark/space) of UART module.
+ * - \ref _UART_PARITY_NONE
+ * - \ref _UART_PARITY_ODD
+ * - \ref _UART_PARITY_EVEN
+ * - \ref _UART_PARITY_MARK
+ * - \ref _UART_PARITY_SPACE
+ * @param[in] u32stop_bits The stop bit length (1/1.5/2 bit) of UART module.
+ * - \ref UART_STOP_BIT_1
+ * - \ref UART_STOP_BIT_1_5
+ * - \ref UART_STOP_BIT_2
+ *
+ * @return None
+ *
+ * @details This function use to config UART line setting.
+ */
+void UART_SetLineConfig(UART_T *uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits)
+{
+ uint32_t u32UartClkSrcSel = 0ul, u32UartClkDivNum = 0ul;
+ uint32_t u32ClkTbl[4ul] = {__HXT, 0ul, __LXT, __HIRC};
+ uint32_t u32Baud_Div = 0ul;
+
+ if (uart == (UART_T *)UART0) {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos;
+ } else if (uart == (UART_T *)UART1) {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos;
+ } else if (uart == (UART_T *)UART2) {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos;
+ } else if (uart == (UART_T *)UART3) {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos;
+ } else if (uart == (UART_T *)UART4) {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos;
+ } else if (uart == (UART_T *)UART5) {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos;
+ }
+
+ /* Get PLL clock frequency if UART clock source selection is PLL */
+ if (u32UartClkSrcSel == 1ul) {
+ u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
+ } else {
+ }
+
+ /* Set UART baud rate */
+ if (u32baudrate != 0ul) {
+ u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate);
+
+ if (u32Baud_Div > 0xFFFFul) {
+ uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate));
+ } else {
+ uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
+ }
+ }
+
+ /* Set UART line configuration */
+ uart->LINE = u32data_width | u32parity | u32stop_bits;
+}
+
+
+/**
+ * @brief Set Rx timeout count
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32TOC Rx timeout counter.
+ *
+ * @return None
+ *
+ * @details This function use to set Rx timeout count.
+ */
+void UART_SetTimeoutCnt(UART_T *uart, uint32_t u32TOC)
+{
+ /* Set time-out interrupt comparator */
+ uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk) | (u32TOC);
+ /* Set time-out counter enable */
+ uart->INTEN |= UART_INTEN_TOCNTEN_Msk;
+}
+
+
+/**
+ * @brief Select and configure IrDA function
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32Buadrate The baudrate of UART module.
+ * @param[in] u32Direction The direction of UART module in IrDA mode:
+ * - \ref UART_IRDA_TXEN
+ * - \ref UART_IRDA_RXEN
+ *
+ * @return None
+ *
+ * @details The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate.
+ */
+void UART_SelectIrDAMode(UART_T *uart, uint32_t u32Buadrate, uint32_t u32Direction)
+{
+ uint32_t u32UartClkSrcSel = 0ul, u32UartClkDivNum = 0ul;
+ uint32_t u32ClkTbl[4ul] = {__HXT, 0ul, __LXT, __HIRC};
+ uint32_t u32Baud_Div;
+ /* Select IrDA function mode */
+ uart->FUNCSEL = UART_FUNCSEL_IrDA;
+
+ if (uart == UART0) {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos;
+ } else if (uart == UART1) {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos;
+ } else if (uart == UART2) {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos;
+ } else if (uart == UART3) {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos;
+ } else if (uart == UART4) {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos;
+ } else if (uart == UART5) {
+ /* Get UART clock source selection */
+ u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos;
+ /* Get UART clock divider number */
+ u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos;
+ }
+
+ /* Get PLL clock frequency if UART clock source selection is PLL */
+ if (u32UartClkSrcSel == 1ul) {
+ u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
+ } else {
+ }
+
+ /* Set UART IrDA baud rate in mode 0 */
+ if (u32Buadrate != 0ul) {
+ u32Baud_Div = UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32Buadrate);
+
+ if (u32Baud_Div < 0xFFFFul) {
+ uart->BAUD = (UART_BAUD_MODE0 | u32Baud_Div);
+ } else {
+ }
+ }
+
+ /* Configure IrDA relative settings */
+ if (u32Direction == UART_IRDA_RXEN) {
+ uart->IRDA |= UART_IRDA_RXINV_Msk; /*Rx signal is inverse*/
+ uart->IRDA &= ~UART_IRDA_TXEN_Msk;
+ } else {
+ uart->IRDA &= ~UART_IRDA_TXINV_Msk; /*Tx signal is not inverse*/
+ uart->IRDA |= UART_IRDA_TXEN_Msk;
+ }
+}
+
+
+/**
+ * @brief Select and configure RS485 function
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32Mode The operation mode(NMM/AUD/AAD).
+ * - \ref UART_ALTCTL_RS485NMM_Msk
+ * - \ref UART_ALTCTL_RS485AUD_Msk
+ * - \ref UART_ALTCTL_RS485AAD_Msk
+ * @param[in] u32Addr The RS485 address.
+ *
+ * @return None
+ *
+ * @details The function is used to set RS485 relative setting.
+ */
+void UART_SelectRS485Mode(UART_T *uart, uint32_t u32Mode, uint32_t u32Addr)
+{
+ /* Select UART RS485 function mode */
+ uart->FUNCSEL = UART_FUNCSEL_RS485;
+ /* Set RS585 configuration */
+ uart->ALTCTL &= ~(UART_ALTCTL_RS485NMM_Msk | UART_ALTCTL_RS485AUD_Msk | UART_ALTCTL_RS485AAD_Msk | UART_ALTCTL_ADDRMV_Msk);
+ uart->ALTCTL |= (u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos));
+}
+
+
+/**
+ * @brief Select and configure LIN function
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32Mode The LIN direction :
+ * - \ref UART_ALTCTL_LINTXEN_Msk
+ * - \ref UART_ALTCTL_LINRXEN_Msk
+ * @param[in] u32BreakLength The break field length.
+ *
+ * @return None
+ *
+ * @details The function is used to set LIN relative setting.
+ */
+void UART_SelectLINMode(UART_T *uart, uint32_t u32Mode, uint32_t u32BreakLength)
+{
+ /* Select LIN function mode */
+ uart->FUNCSEL = UART_FUNCSEL_LIN;
+ /* Select LIN function setting : Tx enable, Rx enable and break field length */
+ uart->ALTCTL &= ~(UART_ALTCTL_LINTXEN_Msk | UART_ALTCTL_LINRXEN_Msk | UART_ALTCTL_BRKFL_Msk);
+ uart->ALTCTL |= (u32Mode | (u32BreakLength << UART_ALTCTL_BRKFL_Pos));
+}
+
+
+/**
+ * @brief Write UART data
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] pu8TxBuf The buffer to send the data to UART transmission FIFO.
+ * @param[out] u32WriteBytes The byte number of data.
+ *
+ * @return u32Count transfer byte count
+ *
+ * @details The function is to write data into TX buffer to transmit data by UART.
+ */
+uint32_t UART_Write(UART_T *uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes)
+{
+ uint32_t u32Count, u32delayno;
+ uint32_t u32Exit = 0ul;
+
+ for (u32Count = 0ul; u32Count != u32WriteBytes; u32Count++) {
+ u32delayno = 0ul;
+
+ while (uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) { /* Check Tx Full */
+ u32delayno++;
+
+ if (u32delayno >= 0x40000000ul) {
+ u32Exit = 1ul;
+ break;
+ } else {
+ }
+ }
+
+ if (u32Exit == 1ul) {
+ break;
+ } else {
+ uart->DAT = pu8TxBuf[u32Count]; /* Send UART Data from buffer */
+ }
+ }
+
+ return u32Count;
+}
+
+
+/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group UART_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
+
+
+
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/daplink_addr.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/nuvoton/m48ssidae/daplink_addr.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,84 @@ +/** + * @file daplink_addr.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef DAPLINK_ADDR_H +#define DAPLINK_ADDR_H + +#define KB(size) ((size) * 1024) + +/* Device sizes */ + +#define DAPLINK_ROM_START 0x00000000 +#define DAPLINK_ROM_SIZE KB(256) + +#define DAPLINK_RAM_START 0x20000000 +#define DAPLINK_RAM_SIZE KB(160) + +/* ROM sizes */ + +#define DAPLINK_ROM_BL_START 0x00000000 +#define DAPLINK_ROM_BL_SIZE KB(48) + +#define DAPLINK_ROM_CONFIG_ADMIN_START 0x0000C000 +#define DAPLINK_ROM_CONFIG_ADMIN_SIZE KB(0) + +#define DAPLINK_ROM_IF_START 0x0000C000 +#define DAPLINK_ROM_IF_SIZE KB(204) + +#define DAPLINK_ROM_CONFIG_USER_START 0x0003F000 +#define DAPLINK_ROM_CONFIG_USER_SIZE KB(4) + +/* RAM sizes */ + +#define DAPLINK_RAM_APP_START 0x20000000 +#define DAPLINK_RAM_APP_SIZE KB(156) + +#define DAPLINK_RAM_SHARED_START 0x20027000 +#define DAPLINK_RAM_SHARED_SIZE KB(4) + +/* Flash Programming Info */ + +#define DAPLINK_SECTOR_SIZE KB(4) +#define DAPLINK_MIN_WRITE_SIZE (256) + +/* Current build */ + +#if defined(DAPLINK_BL) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_BL_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_IF_SIZE + +#elif defined(DAPLINK_IF) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_IF_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_BL_SIZE + +#else + +#error "Build must be either bootloader or interface" + +#endif + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/flash.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/flash.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,79 @@
+/**
+ * @file flash.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_hal.h" // FlashOS Structures
+#include "target_config.h" // target_device
+#include "util.h"
+#include "string.h"
+#include "target_board.h"
+#include "NuMicro.h"
+
+uint32_t Init(uint32_t adr, uint32_t clk, uint32_t fnc)
+{
+ SYS_UnlockReg();
+ /* Enable FMC ISP function */
+ FMC_Open();
+ FMC_ENABLE_AP_UPDATE();
+ return 0;
+}
+
+uint32_t UnInit(uint32_t fnc)
+{
+ FMC_DISABLE_AP_UPDATE();
+ /* Disable FMC ISP function */
+ FMC_Close();
+ SYS_LockReg();
+ return 0;
+}
+
+uint32_t EraseChip(void)
+{
+ return 1;
+}
+
+uint32_t EraseSector(uint32_t adr)
+{
+ uint32_t ret = 0;
+
+ if (FMC_Erase(adr) != 0) {
+ ret = 1;
+ }
+
+ return ret;
+}
+
+uint32_t ProgramPage(uint32_t adr, uint32_t sz, uint32_t *buf)
+{
+ uint32_t i;
+ uint32_t ret = 0;
+
+ for (i = 0; i < sz; i += 4) {
+ FMC_Write(adr + i, buf[i / 4]);
+
+ if (FMC_GET_FAIL_FLAG()) {
+ FMC_CLR_FAIL_FLAG();
+ ret = 1;
+ break;
+ }
+ }
+
+ return ret;
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/gpio.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/gpio.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,53 @@
+/**
+ * @file gpio.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "gpio.h"
+
+void gpio_init(void)
+{
+ GPIO_SetMode(OFF_BTN_GRP, (1 << OFF_BTN_BIT), GPIO_MODE_INPUT);
+}
+
+void gpio_set_hid_led(gpio_led_state_t state)
+{
+}
+
+void gpio_set_cdc_led(gpio_led_state_t state)
+{
+}
+
+void gpio_set_msc_led(gpio_led_state_t state)
+{
+}
+
+uint8_t gpio_get_reset_btn_no_fwrd(void)
+{
+ return (OFF_BTN_IO != 0) ? 0 : 1;
+}
+
+uint8_t gpio_get_reset_btn_fwrd(void)
+{
+ return 0;
+}
+
+void gpio_set_board_power(bool powerEnabled)
+{
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/read_uid.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/read_uid.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,38 @@
+/**
+ * @file read_uid.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "read_uid.h"
+#include "NuMicro.h"
+
+void read_unique_id(uint32_t *id)
+{
+ SYS_UnlockReg();
+ /* Enable FMC ISP function */
+ FMC_Open();
+ /* Read Unique ID */
+ id[0] = FMC_ReadUID(0);
+ id[1] = FMC_ReadUID(1);
+ id[2] = FMC_ReadUID(2);
+ id[3] = 0;
+ /* Disable FMC ISP function */
+ FMC_Close();
+ SYS_LockReg();
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/sdk.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/sdk.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,68 @@
+/**
+ * @file sdk.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "NuMicro.h"
+#include "DAP_config.h"
+#include "gpio.h"
+#include "daplink.h"
+#include "util.h"
+#include "cortex_m.h"
+
+void sdk_init()
+{
+ uint32_t volatile i;
+ /* Unlock protected registers */
+ SYS_UnlockReg();
+ /* Set XT1_OUT(PF.2) and XT1_IN(PF.3) to input mode */
+ PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk);
+ /* Enable External XTAL (4~24 MHz) */
+ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
+ /* Waiting for 12MHz clock ready */
+ CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
+ /* Switch HCLK clock source to HXT */
+ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT, CLK_CLKDIV0_HCLK(1));
+ /* Set core clock as PLL_CLOCK from PLL */
+ CLK_SetCoreClock(FREQ_192MHZ);
+ /* Set PCLK0/PCLK1 to HCLK/2 */
+ CLK->PCLKDIV = (CLK_PCLKDIV_PCLK0DIV2 | CLK_PCLKDIV_PCLK1DIV2);
+ /* Select HSUSBD */
+ SYS->USBPHY &= ~SYS_USBPHY_HSUSBROLE_Msk;
+ /* Enable USB PHY */
+ SYS->USBPHY = (SYS->USBPHY & ~(SYS_USBPHY_HSUSBROLE_Msk | SYS_USBPHY_HSUSBACT_Msk)) | SYS_USBPHY_HSUSBEN_Msk;
+
+ for (i = 0; i < 0x1000; i++); // delay > 10 us
+
+ SYS->USBPHY |= SYS_USBPHY_HSUSBACT_Msk;
+ /* Enable HSUSBD clock */
+ CLK_EnableModuleClock(HSUSBD_MODULE);
+ /* Select UART clock source */
+ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART0SEL_HXT, CLK_CLKDIV0_UART0(1));
+ /* Enable UART clock */
+ CLK_EnableModuleClock(UART0_MODULE);
+ /* Set GPA multi-function pins for UART0 RXD and TXD */
+ SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA0MFP_Msk | SYS_GPA_MFPL_PA1MFP_Msk);
+ SYS->GPA_MFPL |= (SYS_GPA_MFPL_PA0MFP_UART0_RXD | SYS_GPA_MFPL_PA1MFP_UART0_TXD);
+ /* Update System Core Clock */
+ /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
+ SystemCoreClockUpdate();
+ /* Lock protected registers */
+ SYS_LockReg();
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/uart.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/uart.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,222 @@
+/**
+ * @file uart.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "string.h"
+#include "uart.h"
+#include "gpio.h"
+#include "util.h"
+#include "circ_buf.h"
+#include "NuMicro.h"
+
+#define RX_OVRF_MSG "<DAPLink:Overflow>\n"
+#define RX_OVRF_MSG_SIZE (sizeof(RX_OVRF_MSG) - 1)
+#define BUFFER_SIZE (512)
+
+#define TX_FIFO_SIZE 16 /* TX Hardware FIFO size */
+
+circ_buf_t write_buffer;
+uint8_t write_buffer_data[BUFFER_SIZE];
+circ_buf_t read_buffer;
+uint8_t read_buffer_data[BUFFER_SIZE];
+
+static UART_Configuration configuration = {
+ .Baudrate = 9600,
+ .DataBits = UART_DATA_BITS_8,
+ .Parity = UART_PARITY_NONE,
+ .StopBits = UART_STOP_BITS_1,
+ .FlowControl = UART_FLOW_CONTROL_NONE,
+};
+
+static void clear_buffers(void)
+{
+ circ_buf_init(&write_buffer, write_buffer_data, sizeof(write_buffer_data));
+ circ_buf_init(&read_buffer, read_buffer_data, sizeof(read_buffer_data));
+}
+
+int32_t uart_initialize(void)
+{
+ clear_buffers();
+ UART_Open(UART0, 115200);
+ UART_ENABLE_INT(UART0, (UART_INTEN_RDAIEN_Msk | UART_INTEN_THREIEN_Msk | UART_INTEN_RXTOIEN_Msk));
+ NVIC_EnableIRQ(UART0_IRQn);
+ return 1;
+}
+
+int32_t uart_uninitialize(void)
+{
+ NVIC_DisableIRQ(UART0_IRQn);
+ UART_Close(UART0);
+ clear_buffers();
+ return 1;
+}
+
+int32_t uart_reset(void)
+{
+ UART_Configuration backup_configuration = configuration;
+ uart_set_configuration(&backup_configuration);
+ return 1;
+}
+
+int32_t uart_set_configuration(UART_Configuration *config)
+{
+ uint32_t u32Reg;
+ uint32_t u32Baud_Div;
+ NVIC_DisableIRQ(UART0_IRQn);
+ /* Reset hardware fifo */
+ UART0->FIFO |= (UART_FIFO_TXRST_Msk | UART_FIFO_RXRST_Msk);
+ /* Reset software fifo */
+ clear_buffers();
+ /* Set parity */
+ configuration.Parity = config->Parity;
+
+ if (config->Parity == UART_PARITY_ODD) {
+ u32Reg = 0x08;
+ } else if (config->Parity == UART_PARITY_EVEN) {
+ u32Reg = 0x18;
+ } else if (config->Parity == UART_PARITY_NONE) {
+ u32Reg = 0;
+ } else {
+ u32Reg = 0;
+ }
+
+ /* Stop bit */
+ configuration.StopBits = config->StopBits;
+
+ if (config->StopBits == UART_STOP_BITS_2) {
+ u32Reg |= 0x4;
+ } else if (config->StopBits == UART_STOP_BITS_1_5) {
+ u32Reg |= 0x4;
+ } else if (config->StopBits == UART_STOP_BITS_1)
+ ;
+
+ /* Bit width */
+ configuration.DataBits = config->DataBits;
+
+ if (config->DataBits == UART_DATA_BITS_5) {
+ u32Reg |= 0;
+ } else if (config->DataBits == UART_DATA_BITS_6) {
+ u32Reg |= 1;
+ } else if (config->DataBits == UART_DATA_BITS_7) {
+ u32Reg |= 2;
+ } else if (config->DataBits == UART_DATA_BITS_8) {
+ u32Reg |= 3;
+ }
+
+ configuration.FlowControl = UART_FLOW_CONTROL_NONE;
+ /* Set baudrate */
+ configuration.Baudrate = config->Baudrate;
+ u32Baud_Div = UART_BAUD_MODE2_DIVIDER(__HXT, configuration.Baudrate);
+
+ if (u32Baud_Div > 0xFFFF) {
+ UART0->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER(__HXT, configuration.Baudrate));
+ } else {
+ UART0->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
+ }
+
+ UART0->LINE = u32Reg;
+ NVIC_EnableIRQ(UART0_IRQn);
+ return 1;
+}
+
+int32_t uart_get_configuration(UART_Configuration *config)
+{
+ config->Baudrate = configuration.Baudrate;
+ config->DataBits = configuration.DataBits;
+ config->Parity = configuration.Parity;
+ config->StopBits = configuration.StopBits;
+ config->FlowControl = UART_FLOW_CONTROL_NONE;
+ return 1;
+}
+
+int32_t uart_write_free(void)
+{
+ return circ_buf_count_free(&write_buffer);
+}
+
+int32_t uart_write_data(uint8_t *data, uint16_t size)
+{
+ uint8_t bInChar;
+ uint32_t u32Size = circ_buf_write(&write_buffer, data, size);
+
+ if (circ_buf_count_used(&write_buffer) > 0) {
+ if ((UART0->INTEN & UART_INTEN_THREIEN_Msk) == 0) {
+ bInChar = circ_buf_pop(&write_buffer);
+ /* Send one bytes out */
+ UART_WRITE(UART0, bInChar);
+ /* Enable Tx Empty Interrupt. (Trigger first one) */
+ UART0->INTEN |= UART_INTEN_THREIEN_Msk;
+ }
+ }
+
+ return u32Size;
+}
+
+int32_t uart_read_data(uint8_t *data, uint16_t size)
+{
+ return circ_buf_read(&read_buffer, data, size);
+}
+
+void UART0_IRQHandler(void)
+{
+ uint8_t bInChar;
+ int32_t u32Size;
+ uint32_t u32IntStatus;
+ u32IntStatus = UART0->INTSTS;
+
+ if ((u32IntStatus & UART_INTSTS_RDAINT_Msk) || (u32IntStatus & UART_INTSTS_RXTOINT_Msk)) {
+ /* Receiver FIFO threshold level is reached or Rx time out */
+ /* Get all the input characters */
+ while ((!UART_GET_RX_EMPTY(UART0))) {
+ /* Get the character from UART Buffer */
+ bInChar = UART_READ(UART0); /* Rx trigger level is 1 byte*/
+ /* Check if buffer full */
+ uint32_t u32Free = circ_buf_count_free(&read_buffer);
+
+ if (u32Free > RX_OVRF_MSG_SIZE) {
+ circ_buf_push(&read_buffer, bInChar);
+ } else if (RX_OVRF_MSG_SIZE == u32Free) {
+ circ_buf_write(&read_buffer, (uint8_t *)RX_OVRF_MSG, RX_OVRF_MSG_SIZE);
+ } else {
+ // Drop character
+ }
+ }
+ }
+
+ if (u32IntStatus & UART_INTSTS_THREINT_Msk) {
+ if (circ_buf_count_used(&write_buffer) > 0) {
+ /* Fill the Tx FIFO */
+ u32Size = circ_buf_count_used(&write_buffer);
+
+ if (u32Size >= TX_FIFO_SIZE) {
+ u32Size = TX_FIFO_SIZE;
+ }
+
+ while (u32Size) {
+ bInChar = circ_buf_pop(&write_buffer);
+ UART_WRITE(UART0, bInChar);
+ u32Size--;
+ }
+ } else {
+ /* No more data, just stop Tx (Stop work) */
+ UART0->INTEN &= ~UART_INTEN_THREIEN_Msk;
+ }
+ }
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/usb_buf.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/nuvoton/m48ssidae/usb_buf.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,31 @@ +/** + * @file usb_buf.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef USB_BUF_H +#define USB_BUF_H + + +#include "stdint.h" + +#define USB_MSC_BUF_SIZE (512) +uint32_t usb_buffer[USB_MSC_BUF_SIZE / sizeof(uint32_t)]; + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/usb_config.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/nuvoton/m48ssidae/usb_config.c Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,554 @@ +/** + * @file usb_config.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "util.h" + +// <e> USB Device +// <i> Enable the USB Device functionality +#define USBD_ENABLE 1 +#define USBD_RTX_CORE_STACK 0 +#define USBD_RTX_DEVICE_STACK 0 +#define USBD_RTX_ENDPOINT0_STACK 0 + +// <o0.0> High-speed +// <i> Enable high-speed functionality (if device supports it) +#define USBD_HS_ENABLE 1 +#if (defined(WEBUSB_INTERFACE) || defined(WINUSB_INTERFACE) || defined(BULK_ENDPOINT)) +#define USBD_BOS_ENABLE 1 +#else +#define USBD_BOS_ENABLE 0 +#endif +// <h> Device Settings +// <i> These settings affect Device Descriptor +// <o0> Power +// <i> Default Power Setting +// <0=> Bus-powered +// <1=> Self-powered +// <o1> Max Endpoint 0 Packet Size +// <i> Maximum packet size for endpoint zero (bMaxPacketSize0) +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes +// <o2.0..15> Vendor ID <0x0000-0xFFFF> +// <i> Vendor ID assigned by the USB-IF (idVendor) +// <o3.0..15> Product ID <0x0000-0xFFFF> +// <i> Product ID assigned by the manufacturer (idProduct) +// <o4.0..15> Device Release Number <0x0000-0xFFFF> +// <i> Device release number in binary-coded decimal (bcdDevice) +// </h> +#define USBD_POWER 0 +#define USBD_MAX_PACKET0 64 +#define USBD_DEVDESC_IDVENDOR 0x0D28 +#define USBD_DEVDESC_IDPRODUCT 0x0204 +#define USBD_DEVDESC_BCDDEVICE 0x0100 //was 0x0100 + +// <h> Configuration Settings +// <i> These settings affect Configuration Descriptor +// <o0.5> Remote Wakeup +// <i> Configuration support for remote wakeup (D5: of bmAttributes) +// <o1.0..7> Maximum Power Consumption (in mA) <0-510><#/2> +// <i> Maximum power consumption of the USB device +// <i> from the bus in this specific configuration +// <i> when the device is fully operational (bMaxPower) +// </h> +#define USBD_CFGDESC_BMATTRIBUTES 0x80 +#define USBD_CFGDESC_BMAXPOWER 0xFA + +// <h> String Settings +// <i> These settings affect String Descriptor +// <o0.0..15> Language ID <0x0000-0xFCFF> +// <i> English (United States) = 0x0409 +// <s0.126> Manufacturer String +// <i> String descriptor describing manufacturer +// <s1.126> Product String +// <i> String descriptor describing product +// <e1.0> Serial Number +// <i> Enable serial number string +// <i> If disabled serial number string will not be assigned to the USB Device +// <s2.126> Serial Number String +// <i> String descriptor describing device's serial number +// </e> +// </h> +#define USBD_STRDESC_LANGID 0x0409 +#define USBD_STRDESC_MAN L"ARM" +#define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" +#define USBD_STRDESC_SER_ENABLE 1 +#define USBD_STRDESC_SER L"0001A0000000" + +// <e0> Class Support +// <i> Enables USB Device Class specific Requests +#define USBD_CLASS_ENABLE 1 + +// <e0.0> Human Interface Device (HID) +// <i> Enable class support for Human Interface Device (HID) +// <h> Interrupt Endpoint Settings +// <o1.0..4> Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o2.0..4> Interrupt Out Endpoint Number <0=> Not used <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <i> If interrupt out endpoint is not used select "Not used" +// <h> Endpoint Settings +// <o3.0..7> Maximum Endpoint Packet Size (in bytes) <0-64> +// <o4.0..7> Endpoint polling Interval (in ms) <1-255> +// <e5> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o6.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o6.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// <o7.0..7> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// </e> +// </h> +// </h> +// <h> Human Interface Device Settings +// <i> Device specific settings +// <s0.126> HID Interface String +// <o8.0..4> Number of Input Reports <1-32> +// <o9.0..4> Number of Output Reports <1-32> +// <o10.0..15> Maximum Input Report Size (in bytes) <1-65535> +// <o11.0..15> Maximum Output Report Size (in bytes) <1-65535> +// <o12.0..15> Maximum Feature Report Size (in bytes) <1-65535> +// </h> +// </e> +#ifndef HID_ENDPOINT +#define HID_ENDPOINT 0 +#else +#define HID_ENDPOINT 1 +#endif + +#ifndef WEBUSB_INTERFACE +#define WEBUSB_INTERFACE 0 +#else +#define WEBUSB_INTERFACE 1 +#endif + +#define USBD_HID_ENABLE HID_ENDPOINT +#ifndef BULK_ENDPOINT //check if bulk endpoint is not enabled +#define USBD_HID_EP_INTIN 1 +#define USBD_HID_EP_INTOUT 2 +#else //if bulk endpoint is enabled remove interrupt endpoints from the hid +#define USBD_HID_EP_INTIN 0 +#define USBD_HID_EP_INTOUT 0 +#endif +#define USBD_HID_EP_INTIN_STACK 0 +#define USBD_HID_WMAXPACKETSIZE 64 +#define USBD_HID_BINTERVAL 1 +#define USBD_HID_HS_ENABLE 1 +#define USBD_HID_HS_WMAXPACKETSIZE 64 +#define USBD_HID_HS_BINTERVAL 4 +#define USBD_HID_STRDESC L"CMSIS-DAP v1" +#define USBD_WEBUSB_STRDESC L"WebUSB: CMSIS-DAP" +#define USBD_HID_INREPORT_NUM 1 +#define USBD_HID_OUTREPORT_NUM 1 +#define USBD_HID_INREPORT_MAX_SZ 64 +#define USBD_HID_OUTREPORT_MAX_SZ 64 +#define USBD_HID_FEATREPORT_MAX_SZ 1 + +// <e0.0> Mass Storage Device (MSC) +// <i> Enable class support for Mass Storage Device (MSC) +// <h> Bulk Endpoint Settings +// <o1.0..4> Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o2.0..4> Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o3> Maximum Packet Size <1-1024> +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5> Maximum Packet Size <1-1024> +// <o6> Maximum NAK Rate <0-255> +// </e> +// </h> +// </h> +// <h> Mass Storage Device Settings +// <i> Device specific settings +// <s0.126> MSC Interface String +// <h> Inquiry Data +// <s1.8> Vendor Identification +// <s2.16> Product Identification +// <s3.4> Product Revision Level +// </h> +// </h> +// </e> +#ifndef MSC_ENDPOINT +#define MSC_ENDPOINT 0 +#else +#define MSC_ENDPOINT 1 +#endif +#define USBD_MSC_ENABLE MSC_ENDPOINT +#define USBD_MSC_EP_BULKIN 6 +#define USBD_MSC_EP_BULKOUT 7 +#define USBD_MSC_EP_BULKIN_STACK 0 +#define USBD_MSC_WMAXPACKETSIZE 64 +#define USBD_MSC_HS_ENABLE 1 +#define USBD_MSC_HS_WMAXPACKETSIZE 512 +#define USBD_MSC_HS_BINTERVAL 0 +#define USBD_MSC_STRDESC L"USB_MSC" +// Make sure changes to USBD_MSC_INQUIRY_DATA are coordinated with mbed-ls +// since this is used to detect DAPLink drives +#define USBD_MSC_INQUIRY_DATA "MBED " \ + "VFS " \ + "0.1" + +// <e0.0> Audio Device (ADC) +// <i> Enable class support for Audio Device (ADC) +// <h> Isochronous Endpoint Settings +// <o1.0..4> Isochronous Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o2.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o3.0..10> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o5.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// </e> +// </h> +// </h> +// <h> Audio Device Settings +// <i> Device specific settings +// <s0.126> Audio Control Interface String +// <s1.126> Audio Streaming (Zero Bandwidth) Interface String +// <s2.126> Audio Streaming (Operational) Interface String +// <o6.0..7> Audio Subframe Size (in bytes) <0-255> +// <o7.0..7> Sample Resolution (in bits) <0-255> +// <o8.0..23> Sample Frequency (in Hz) <0-16777215> +// <o9> Packet Size (in bytes) <1-256> +// <o10> Packet Count <1-16> +// </h> +// </e> +#define USBD_ADC_ENABLE 0 +#define USBD_ADC_EP_ISOOUT 3 +#define USBD_ADC_WMAXPACKETSIZE 64 +#define USBD_ADC_BINTERVAL 1 +#define USBD_ADC_HS_ENABLE 0 +#define USBD_ADC_HS_WMAXPACKETSIZE 64 +#define USBD_ADC_CIF_STRDESC L"USB_ADC" +#define USBD_ADC_SIF1_STRDESC L"USB_ADC1" +#define USBD_ADC_SIF2_STRDESC L"USB_ADC2" +#define USBD_ADC_BSUBFRAMESIZE 2 +#define USBD_ADC_BBITRESOLUTION 16 +#define USBD_ADC_TSAMFREQ 32000 +#define USBD_ADC_CFG_P_S 32 +#define USBD_ADC_CFG_P_C 1 + +// <e0> Communication Device (CDC) - Abstract Control Model (ACM) +// <i> Enable class support for Communication Device (CDC) - Abstract Control Model (ACM) +// <h> Interrupt Endpoint Settings +// <o1.0..4> Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o2.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o3.0..10> Endpoint polling Interval (in ms) <0-255> +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o5.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// <o6.0..10> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// </e4> +// </h> +// </h> +// <h> Bulk Endpoint Settings +// <o7.0..4> Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o8.0..4> Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o9> Maximum Packet Size <1-1024> +// <e10> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o11> Maximum Packet Size <1-1024> +// <o12> Maximum NAK Rate <0-255> +// </e10> +// </h> +// </h> +// <h> Communication Device Settings +// <i> Device specific settings +// <s0.126> Communication Class Interface String +// <s1.126> Data Class Interface String +// <o13> Maximum Communication Device Send Buffer Size +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// <o14> Maximum Communication Device Receive Buffer Size +// <i> Minimum size must be as big as maximum packet size for Bulk Out Endpoint +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// </h> +// </e> + +#ifndef CDC_ENDPOINT +#define CDC_ENDPOINT 0 +#else +#define CDC_ENDPOINT 1 +#endif +#define USBD_CDC_ACM_ENABLE CDC_ENDPOINT +#define USBD_CDC_ACM_EP_INTIN 3 +#define USBD_CDC_ACM_EP_INTIN_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE 64 +#define USBD_CDC_ACM_BINTERVAL 32 +#define USBD_CDC_ACM_HS_ENABLE 1 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE 64 +#define USBD_CDC_ACM_HS_BINTERVAL 2 +#define USBD_CDC_ACM_EP_BULKIN 4 +#define USBD_CDC_ACM_EP_BULKOUT 5 +#define USBD_CDC_ACM_EP_BULKIN_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE1 64 +#define USBD_CDC_ACM_HS_ENABLE1 1 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE1 512 +#define USBD_CDC_ACM_HS_BINTERVAL1 0 +#define USBD_CDC_ACM_CIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_DIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_SENDBUF_SIZE 512 +#define USBD_CDC_ACM_RECEIVEBUF_SIZE 512 +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Send Buffer size must be larger or equal to Bulk In maximum packet size!" +#endif +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Receive Buffer size must be larger or equal to Bulk Out maximum packet size!" +#endif + +// <e0> Custom Class Device +// <i> Enables USB Custom Class Requests +// <i> Class IDs: +// <i> 0x00 - Class Reserved ID +// <i> 0x01 - Class Audio ID +// <i> 0x02 - Class Communications ID +// <i> 0x03 - Class Human Interface ID +// <i> 0x04 - Class Monitor ID +// <i> 0x05 - Class Physical Interface ID +// <i> 0x06 - Class Power ID +// <i> 0x07 - Class Printer ID +// <i> 0x08 - Class Storage ID +// <i> 0x09 - Class HUB ID +// <i> 0xEF - Class Miscellaneous ID +// <i> 0xFF - Class Vendor Specific ID +// </e> +#define USBD_CLS_ENABLE 0 + +// WebUSB support +#define USBD_WEBUSB_ENABLE WEBUSB_INTERFACE +#define USBD_WEBUSB_VENDOR_CODE 0x21 +#define USBD_WEBUSB_LANDING_URL "os.mbed.com/webusb/landing-page/?bid=" +#define USBD_WEBUSB_ORIGIN_URL "os.mbed.com/" + +// Microsoft OS Descriptors 2.0 (WinUSB) support +#define USBD_WINUSB_ENABLE WINUSB_INTERFACE +#define USBD_WINUSB_VENDOR_CODE 0x20 +// </e> +// </e> + +#ifndef BULK_ENDPOINT +#define BULK_ENDPOINT 0 +#else +#define BULK_ENDPOINT 1 +#endif +#define USBD_BULK_ENABLE BULK_ENDPOINT +#define USBD_BULK_EP_BULKIN 1 // fixme: both bulk and hid ep cannot be both enabled in a single build +#define USBD_BULK_EP_BULKOUT 1 +#define USBD_BULK_EP_BULKIN_SWO 6 +#define USBD_BULK_WMAXPACKETSIZE 64 +#define USBD_BULK_HS_ENABLE 0 +#define USBD_BULK_HS_WMAXPACKETSIZE 512 +#define USBD_BULK_STRDESC L"CMSIS-DAP v2" + +/* USB Device Calculations ---------------------------------------------------*/ + +#define USBD_IF_NUM_MAX (USBD_BULK_ENABLE+USBD_WEBUSB_ENABLE+USBD_HID_ENABLE+USBD_MSC_ENABLE+(USBD_ADC_ENABLE*2)+(USBD_CDC_ACM_ENABLE*2)+USBD_CLS_ENABLE) +#define USBD_MULTI_IF (USBD_CDC_ACM_ENABLE*(USBD_HID_ENABLE|USBD_MSC_ENABLE|USBD_ADC_ENABLE|USBD_CLS_ENABLE|USBD_WEBUSB_ENABLE|USBD_BULK_ENABLE)) +// #define MAX(x, y) (((x) < (y)) ? (y) : (x)) +#define USBD_EP_NUM_CALC0 MAX((USBD_HID_ENABLE *(USBD_HID_EP_INTIN )), (USBD_HID_ENABLE *(USBD_HID_EP_INTOUT))) +#define USBD_EP_NUM_CALC1 MAX((USBD_MSC_ENABLE *(USBD_MSC_EP_BULKIN )), (USBD_MSC_ENABLE *(USBD_MSC_EP_BULKOUT))) +#define USBD_EP_NUM_CALC2 MAX((USBD_ADC_ENABLE *(USBD_ADC_EP_ISOOUT )), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_INTIN))) +#define USBD_EP_NUM_CALC3 MAX((USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKIN)), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKOUT))) +#define USBD_EP_NUM_CALC4 MAX(USBD_EP_NUM_CALC0, USBD_EP_NUM_CALC1) +#define USBD_EP_NUM_CALC5 MAX(USBD_EP_NUM_CALC2, USBD_EP_NUM_CALC3) +#define USBD_EP_NUM_CALC6 MAX(USBD_EP_NUM_CALC4, USBD_EP_NUM_CALC5) +#define USBD_EP_NUM_CALC7 MAX((USBD_BULK_ENABLE*(USBD_BULK_EP_BULKIN)), (USBD_BULK_ENABLE*(USBD_BULK_EP_BULKOUT))) +#define USBD_EP_NUM MAX(USBD_EP_NUM_CALC6, USBD_EP_NUM_CALC7) + + +#if (USBD_HID_ENABLE) +#if (USBD_MSC_ENABLE) +#if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN)))|| \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKOUT))) +#error "HID and Mass Storage Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_ADC_ENABLE) +#if ((USBD_HID_EP_INTIN == USBD_ADC_EP_ISOOUT) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_ADC_EP_ISOOUT))) +#error "HID and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (((USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKOUT))|| \ + ((USBD_HID_EP_INTOUT != 0) && \ + ((USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKOUT)))) +#error "HID and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_MSC_ENABLE) +#if (USBD_ADC_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_ADC_EP_ISOOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_ADC_EP_ISOOUT)) +#error "Mass Storage Device and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Mass Storage Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_ADC_ENABLE) +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Audio Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#define USBD_ADC_CIF_NUM (0) +#define USBD_ADC_SIF1_NUM (1) +#define USBD_ADC_SIF2_NUM (2) + + +#define USBD_ADC_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+0) +#define USBD_ADC_SIF1_STR_NUM (3+USBD_STRDESC_SER_ENABLE+1) +#define USBD_ADC_SIF2_STR_NUM (3+USBD_STRDESC_SER_ENABLE+2) +#define USBD_CDC_ACM_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+0) +#define USBD_CDC_ACM_DIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+1) +#define USBD_HID_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2) +#define USBD_WEBUSB_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) +#define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) +#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) + + +#if (USBD_HID_ENABLE) +#if (USBD_HID_HS_ENABLE) +#define USBD_HID_MAX_PACKET ((USBD_HID_HS_WMAXPACKETSIZE > USBD_HID_WMAXPACKETSIZE) ? USBD_HID_HS_WMAXPACKETSIZE : USBD_HID_WMAXPACKETSIZE) +#else +#define USBD_HID_MAX_PACKET (USBD_HID_WMAXPACKETSIZE) +#endif +#else +#define USBD_HID_MAX_PACKET (0) +#endif +#if (USBD_MSC_ENABLE) +#if (USBD_MSC_HS_ENABLE) +#define USBD_MSC_MAX_PACKET ((USBD_MSC_HS_WMAXPACKETSIZE > USBD_MSC_WMAXPACKETSIZE) ? USBD_MSC_HS_WMAXPACKETSIZE : USBD_MSC_WMAXPACKETSIZE) +#else +#define USBD_MSC_MAX_PACKET (USBD_MSC_WMAXPACKETSIZE) +#endif +#else +#define USBD_MSC_MAX_PACKET (0) +#endif +#if (USBD_ADC_ENABLE) +#if (USBD_ADC_HS_ENABLE) +#define USBD_ADC_MAX_PACKET ((USBD_ADC_HS_WMAXPACKETSIZE > USBD_ADC_WMAXPACKETSIZE) ? USBD_ADC_HS_WMAXPACKETSIZE : USBD_ADC_WMAXPACKETSIZE) +#else +#define USBD_ADC_MAX_PACKET (USBD_ADC_WMAXPACKETSIZE) +#endif +#else +#define USBD_ADC_MAX_PACKET (0) +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (USBD_CDC_ACM_HS_ENABLE) +#define USBD_CDC_ACM_MAX_PACKET ((USBD_CDC_ACM_HS_WMAXPACKETSIZE > USBD_CDC_ACM_WMAXPACKETSIZE) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE : USBD_CDC_ACM_WMAXPACKETSIZE) +#else +#define USBD_CDC_ACM_MAX_PACKET (USBD_CDC_ACM_WMAXPACKETSIZE) +#endif +#if (USBD_CDC_ACM_HS_ENABLE1) +#define USBD_CDC_ACM_MAX_PACKET1 ((USBD_CDC_ACM_HS_WMAXPACKETSIZE1 > USBD_CDC_ACM_WMAXPACKETSIZE1) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE1 : USBD_CDC_ACM_WMAXPACKETSIZE1) +#else +#define USBD_CDC_ACM_MAX_PACKET1 (USBD_CDC_ACM_WMAXPACKETSIZE1) +#endif +#else +#define USBD_CDC_ACM_MAX_PACKET (0) +#define USBD_CDC_ACM_MAX_PACKET1 (0) +#endif +#if (USBD_BULK_ENABLE) +#if (USBD_BULK_HS_ENABLE) +#define USBD_BULK_MAX_PACKET ((USBD_BULK_HS_WMAXPACKETSIZE > USBD_BULK_WMAXPACKETSIZE) ? USBD_BULK_HS_WMAXPACKETSIZE : USBD_BULK_WMAXPACKETSIZE) +#else +#define USBD_BULK_MAX_PACKET (USBD_BULK_WMAXPACKETSIZE) +#endif +#else +#define USBD_BULK_MAX_PACKET (0) +#endif + +#define USBD_MAX_PACKET_CALC0 ((USBD_HID_MAX_PACKET > USBD_HID_MAX_PACKET ) ? (USBD_HID_MAX_PACKET ) : (USBD_HID_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC1 ((USBD_ADC_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET ) ? (USBD_ADC_MAX_PACKET ) : (USBD_CDC_ACM_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC2 ((USBD_MAX_PACKET_CALC0 > USBD_MAX_PACKET_CALC1 ) ? (USBD_MAX_PACKET_CALC0) : (USBD_MAX_PACKET_CALC1 )) +#define USBD_MAX_PACKET_CALC3 ((USBD_BULK_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET1 ) ? (USBD_BULK_MAX_PACKET) : (USBD_CDC_ACM_MAX_PACKET1 )) +#define USBD_MAX_PACKET ((USBD_MAX_PACKET_CALC3 > USBD_MAX_PACKET_CALC2 ) ? (USBD_MAX_PACKET_CALC3) : (USBD_MAX_PACKET_CALC2 )) + + +/*------------------------------------------------------------------------------ + * USB Config Functions + *----------------------------------------------------------------------------*/ + +#ifndef __USB_CONFIG___ +#define __USB_CONFIG__ + +#ifndef __NO_USB_LIB_C +#include "usb_lib.c" +#endif + +#endif /* __USB_CONFIG__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nuvoton/m48ssidae/usbd_m480.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/usbd_m480.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,835 @@
+/*
+ * Copyright (c) 2004-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <rl_usb.h>
+#include "NuMicro.h"
+
+#define __NO_USB_LIB_C
+#include "usb_config.c"
+
+/* Bit definition of CEPCTL register */
+#define HSUSBD_CEPCTL_NAKCLR ((uint32_t)0x00000000UL)
+#define HSUSBD_CEPCTL_STALL ((uint32_t)0x00000002UL)
+#define HSUSBD_CEPCTL_ZEROLEN ((uint32_t)0x00000004UL)
+#define HSUSBD_CEPCTL_FLUSH ((uint32_t)0x00000008UL)
+
+/* Bit definition of EPxRSPCTL register */
+#define HSUSBD_EP_RSPCTL_FLUSH ((uint32_t)0x00000001UL)
+#define HSUSBD_EP_RSPCTL_MODE_AUTO ((uint32_t)0x00000000UL)
+#define HSUSBD_EP_RSPCTL_MODE_MANUAL ((uint32_t)0x00000002UL)
+#define HSUSBD_EP_RSPCTL_MODE_FLY ((uint32_t)0x00000004UL)
+#define HSUSBD_EP_RSPCTL_MODE_MASK ((uint32_t)0x00000006UL)
+#define HSUSBD_EP_RSPCTL_TOGGLE ((uint32_t)0x00000008UL)
+#define HSUSBD_EP_RSPCTL_HALT ((uint32_t)0x00000010UL)
+#define HSUSBD_EP_RSPCTL_ZEROLEN ((uint32_t)0x00000020UL)
+#define HSUSBD_EP_RSPCTL_SHORTTXEN ((uint32_t)0x00000040UL)
+#define HSUSBD_EP_RSPCTL_DISBUF ((uint32_t)0x00000080UL)
+
+/* Bit definition of EPxCFG register */
+#define HSUSBD_EP_CFG_VALID ((uint32_t)0x00000001UL)
+#define HSUSBD_EP_CFG_TYPE_BULK ((uint32_t)0x00000002UL)
+#define HSUSBD_EP_CFG_TYPE_INT ((uint32_t)0x00000004UL)
+#define HSUSBD_EP_CFG_TYPE_ISO ((uint32_t)0x00000006UL)
+#define HSUSBD_EP_CFG_TYPE_MASK ((uint32_t)0x00000006UL)
+#define HSUSBD_EP_CFG_DIR_OUT ((uint32_t)0x00000000UL)
+#define HSUSBD_EP_CFG_DIR_IN ((uint32_t)0x00000008UL)
+
+#define HSUSBD_ENABLE_USB() ((uint32_t)(HSUSBD->PHYCTL |= (HSUSBD_PHYCTL_PHYEN_Msk|HSUSBD_PHYCTL_DPPUEN_Msk)))
+#define HSUSBD_DISABLE_USB() ((uint32_t)(HSUSBD->PHYCTL &= ~HSUSBD_PHYCTL_DPPUEN_Msk))
+#define HSUSBD_ENABLE_PHY() ((uint32_t)(HSUSBD->PHYCTL |= HSUSBD_PHYCTL_PHYEN_Msk))
+#define HSUSBD_DISABLE_PHY() ((uint32_t)(HSUSBD->PHYCTL &= ~HSUSBD_PHYCTL_PHYEN_Msk))
+#define HSUSBD_SET_SE0() ((uint32_t)(HSUSBD->PHYCTL &= ~HSUSBD_PHYCTL_DPPUEN_Msk))
+#define HSUSBD_CLR_SE0() ((uint32_t)(HSUSBD->PHYCTL |= HSUSBD_PHYCTL_DPPUEN_Msk))
+#define HSUSBD_SET_ADDR(addr) (HSUSBD->FADDR = (addr))
+#define HSUSBD_GET_ADDR() ((uint32_t)(HSUSBD->FADDR))
+#define HSUSBD_ENABLE_USB_INT(intr) (HSUSBD->GINTEN = (intr))
+#define HSUSBD_ENABLE_BUS_INT(intr) (HSUSBD->BUSINTEN = (intr))
+#define HSUSBD_GET_BUS_INT_FLAG() (HSUSBD->BUSINTSTS)
+#define HSUSBD_CLR_BUS_INT_FLAG(flag) (HSUSBD->BUSINTSTS = (flag))
+#define HSUSBD_ENABLE_CEP_INT(intr) (HSUSBD->CEPINTEN = (intr))
+#define HSUSBD_CLR_CEP_INT_FLAG(flag) (HSUSBD->CEPINTSTS = (flag))
+#define HSUSBD_SET_CEP_STATE(flag) (HSUSBD->CEPCTL = (flag))
+#define HSUSBD_START_CEP_IN(size) (HSUSBD->CEPTXCNT = (size))
+#define HSUSBD_SET_MAX_PAYLOAD(ep, size) (HSUSBD->EP[(ep)].EPMPS = (size))
+#define HSUSBD_ENABLE_EP_INT(ep, intr) (HSUSBD->EP[(ep)].EPINTEN = (intr))
+#define HSUSBD_GET_EP_INT_FLAG(ep) (HSUSBD->EP[(ep)].EPINTSTS)
+#define HSUSBD_CLR_EP_INT_FLAG(ep, flag) (HSUSBD->EP[(ep)].EPINTSTS = (flag))
+#define HSUSBD_SET_DMA_LEN(len) (HSUSBD->DMACNT = (len))
+#define HSUSBD_SET_DMA_ADDR(addr) (HSUSBD->DMAADDR = (addr))
+#define HSUSBD_SET_DMA_READ(epnum) (HSUSBD->DMACTL = (HSUSBD->DMACTL & ~HSUSBD_DMACTL_EPNUM_Msk) | HSUSBD_DMACTL_DMARD_Msk | (epnum) | 0x100)
+#define HSUSBD_SET_DMA_WRITE(epnum) (HSUSBD->DMACTL = (HSUSBD->DMACTL & ~(HSUSBD_DMACTL_EPNUM_Msk | HSUSBD_DMACTL_DMARD_Msk | 0x100)) | (epnum))
+#define HSUSBD_ENABLE_DMA() (HSUSBD->DMACTL |= HSUSBD_DMACTL_DMAEN_Msk)
+#define HSUSBD_IS_ATTACHED() ((uint32_t)(HSUSBD->PHYCTL & HSUSBD_PHYCTL_VBUSDET_Msk))
+
+#define HSUSBD_MAX_EP 12UL
+#define CEP 0xFFUL
+#define EPA 0UL
+#define EPB 1UL
+#define EPC 2UL
+#define EPD 3UL
+#define EPE 4UL
+#define EPF 5UL
+#define EPG 6UL
+#define EPH 7UL
+#define EPI 8UL
+#define EPJ 9UL
+#define EPK 10UL
+#define EPL 11UL
+
+#define USBD_EP_TO_NUM(ep) ((ep == CEP) ? (0) : (1 + (ep - EPA)))
+#define USBD_NUM_TO_EP(num) ((num == 0) ? (CEP) : (EPA + (num - 1)))
+
+#define CEP_BUF_BASE 0
+#define CEP_BUF_LEN USBD_MAX_PACKET0
+
+static uint32_t g_u32FreeBufAddr;
+static uint8_t g_u8StatusIn;
+
+/*
+ * USB Device Interrupt enable
+ * Called by USBD_Init to enable the USB Interrupt
+ * Return Value: None
+ */
+
+#ifdef __RTX
+void __svc(1) USBD_IntrEna(void);
+void __SVC_1(void)
+{
+#else
+void USBD_IntrEna(void)
+{
+#endif
+ NVIC_EnableIRQ(USBD20_IRQn);
+}
+
+
+/*
+ * USB Device Initialize Function
+ * Called by the User to initialize USB
+ * Return Value: None
+ */
+
+void USBD_Init(void)
+{
+ uint32_t volatile i;
+ /* Initial USB engine */
+ HSUSBD_ENABLE_PHY();
+
+ /* wait PHY clock ready */
+ while (1) {
+ HSUSBD->EP[EPA].EPMPS = 0x20UL;
+
+ if (HSUSBD->EP[EPA].EPMPS == 0x20UL) {
+ break;
+ }
+ }
+
+ for (i = 0; i < 0x10000; i++);
+
+ if (HSUSBD->OPER & HSUSBD_OPER_CURSPD_Msk) {
+ USBD_HighSpeed = __TRUE;
+ } else {
+ USBD_HighSpeed = __FALSE;
+ }
+
+ /* Enable USB BUS, CEP global interrupt */
+ HSUSBD_ENABLE_USB_INT(HSUSBD_GINTEN_USBIEN_Msk | HSUSBD_GINTEN_CEPIEN_Msk);
+ /* Enable BUS interrupt */
+ HSUSBD_ENABLE_BUS_INT(HSUSBD_BUSINTEN_RESUMEIEN_Msk | HSUSBD_BUSINTEN_RSTIEN_Msk | HSUSBD_BUSINTEN_VBUSDETIEN_Msk | HSUSBD_BUSINTEN_SOFIEN_Msk);
+ /* Reset Address to 0 */
+ HSUSBD_SET_ADDR(0);
+ /* Control endpoint */
+ HSUSBD->CEPBUFST = CEP_BUF_BASE;
+ HSUSBD->CEPBUFEND = CEP_BUF_BASE + CEP_BUF_LEN - 1UL;
+ HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_SETUPPKIEN_Msk | HSUSBD_CEPINTEN_STSDONEIEN_Msk | HSUSBD_CEPINTEN_RXPKIEN_Msk | HSUSBD_CEPINTEN_TXPKIEN_Msk);
+ USBD_IntrEna();
+}
+
+
+/*
+ * USB Device Connect Function
+ * Called by the User to Connect/Disconnect USB Device
+ * Parameters: con: Connect/Disconnect
+ * Return Value: None
+ */
+
+void USBD_Connect(BOOL con)
+{
+ if (con) {
+ HSUSBD_CLR_SE0();
+ } else {
+ HSUSBD_SET_SE0();
+ }
+}
+
+
+/*
+ * USB Device Reset Function
+ * Called automatically on USB Device Reset
+ * Return Value: None
+ */
+
+void USBD_Reset(void)
+{
+ uint32_t i;
+
+ for (i = 0; i < HSUSBD_MAX_EP; i++) {
+ HSUSBD->EP[EPA + i].EPRSPCTL = HSUSBD_EPRSPCTL_FLUSH_Msk;
+ }
+
+ if (HSUSBD->OPER & HSUSBD_OPER_CURSPD_Msk) {
+ USBD_HighSpeed = __TRUE;
+ } else {
+ USBD_HighSpeed = __FALSE;
+ }
+
+ g_u32FreeBufAddr = CEP_BUF_BASE + CEP_BUF_LEN;
+ g_u8StatusIn = 0;
+ HSUSBD_SET_ADDR(0);
+}
+
+
+/*
+ * USB Device Suspend Function
+ * Called automatically on USB Device Suspend
+ * Return Value: None
+ */
+
+void USBD_Suspend(void)
+{
+}
+
+
+/*
+ * USB Device Resume Function
+ * Called automatically on USB Device Resume
+ * Return Value: None
+ */
+
+void USBD_Resume(void)
+{
+}
+
+
+/*
+ * USB Device Remote Wakeup Function
+ * Called automatically on USB Device Remote Wakeup
+ * Return Value: None
+ */
+
+void USBD_WakeUp(void)
+{
+}
+
+
+/*
+ * USB Device Remote Wakeup Configuration Function
+ * Parameters: cfg: Device Enable/Disable
+ * Return Value: None
+ */
+
+void USBD_WakeUpCfg(BOOL cfg)
+{
+}
+
+
+/*
+ * USB Device Set Address Function
+ * Parameters: adr: USB Device Address
+ * setup: Called in setup stage (!=0), else after status stage
+ * Return Value: None
+ */
+
+void USBD_SetAddress(U32 adr, U32 setup)
+{
+ if (setup) {
+ return;
+ }
+
+ HSUSBD_SET_ADDR(adr);
+}
+
+
+/*
+ * USB Device Configure Function
+ * Parameters: cfg: Device Configure/Deconfigure
+ * Return Value: None
+ */
+
+void USBD_Configure(BOOL cfg)
+{
+ if (cfg == __FALSE) {
+ g_u32FreeBufAddr = CEP_BUF_BASE + CEP_BUF_LEN;
+ }
+}
+
+
+/*
+ * Configure USB Device Endpoint according to Descriptor
+ * Parameters: pEPD: Pointer to Device Endpoint Descriptor
+ * Return Value: None
+ */
+
+void USBD_ConfigEP(USB_ENDPOINT_DESCRIPTOR *pEPD)
+{
+ uint32_t u32Num, u32Ep, u32Size, u32Type, u32Dir;
+ u32Num = pEPD->bEndpointAddress & 0x0F;
+ u32Ep = USBD_NUM_TO_EP(u32Num);
+ u32Size = pEPD->wMaxPacketSize;
+
+ switch (pEPD->bmAttributes & USB_ENDPOINT_TYPE_MASK) {
+ case USB_ENDPOINT_TYPE_ISOCHRONOUS:
+ u32Type = HSUSBD_EP_CFG_TYPE_ISO;
+ break;
+
+ case USB_ENDPOINT_TYPE_BULK:
+ u32Type = HSUSBD_EP_CFG_TYPE_BULK;
+ break;
+
+ case USB_ENDPOINT_TYPE_INTERRUPT:
+ u32Type = HSUSBD_EP_CFG_TYPE_INT;
+ break;
+ }
+
+ if (pEPD->bEndpointAddress & USB_ENDPOINT_DIRECTION_MASK) {
+ u32Dir = HSUSBD_EP_CFG_DIR_IN;
+ } else {
+ u32Dir = HSUSBD_EP_CFG_DIR_OUT;
+ }
+
+ HSUSBD->EP[u32Ep].EPBUFST = g_u32FreeBufAddr;
+ HSUSBD->EP[u32Ep].EPBUFEND = g_u32FreeBufAddr + u32Size - 1UL;
+ HSUSBD_SET_MAX_PAYLOAD(u32Ep, u32Size);
+ HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD_EP_RSPCTL_FLUSH | HSUSBD_EP_RSPCTL_MODE_AUTO);
+ HSUSBD->EP[u32Ep].EPCFG = (u32Type | u32Dir | HSUSBD_EP_CFG_VALID | (u32Num << 4));
+ g_u32FreeBufAddr += u32Size;
+}
+
+
+/*
+ * Set Direction for USB Device Control Endpoint
+ * Parameters: dir: Out (dir == 0), In (dir <> 0)
+ * Return Value: None
+ */
+
+void USBD_DirCtrlEP(U32 dir)
+{
+}
+
+
+/*
+ * Enable USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_EnableEP(U32 EPNum)
+{
+ uint32_t u32Ep, u32Num, u32Intr;
+ u32Num = EPNum & 0x0F;
+ u32Ep = USBD_NUM_TO_EP(u32Num);
+ HSUSBD->GINTEN |= (0x1UL << (HSUSBD_GINTEN_EPAIEN_Pos + (u32Num - USBD_EP_TO_NUM(EPA))));
+
+ if (EPNum & 0x80) {
+ u32Intr = HSUSBD_EPINTEN_TXPKIEN_Msk;
+ } else {
+ u32Intr = HSUSBD_EPINTEN_RXPKIEN_Msk | HSUSBD_EPINTEN_SHORTRXIEN_Msk | HSUSBD_EPINTEN_BUFFULLIEN_Msk;
+ }
+
+ HSUSBD_ENABLE_EP_INT(u32Ep, u32Intr);
+}
+
+
+/*
+ * Disable USB Endpoint
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_DisableEP(U32 EPNum)
+{
+ uint32_t u32Ep, u32Num;
+ u32Num = EPNum & 0x0F;
+ u32Ep = USBD_NUM_TO_EP(u32Num);
+ HSUSBD->GINTEN &= ~(0x1UL << (HSUSBD_GINTEN_EPAIEN_Pos + (u32Num - USBD_EP_TO_NUM(EPA))));
+ HSUSBD_ENABLE_EP_INT(u32Ep, 0);
+}
+
+
+/*
+ * Reset USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_ResetEP(U32 EPNum)
+{
+ uint32_t u32Ep, u32Num;
+ u32Num = EPNum & 0x0F;
+ u32Ep = USBD_NUM_TO_EP(u32Num);
+ HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD->EP[u32Ep].EPRSPCTL & HSUSBD_EP_RSPCTL_MODE_MASK) | HSUSBD_EPRSPCTL_FLUSH_Msk;
+}
+
+
+/*
+ * Set Stall for USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_SetStallEP(U32 EPNum)
+{
+ uint32_t u32Ep, u32Num;
+ u32Num = EPNum & 0x0F;
+ u32Ep = USBD_NUM_TO_EP(u32Num);
+
+ if (u32Ep == CEP) {
+ HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALL);
+ } else {
+ HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD->EP[u32Ep].EPRSPCTL & 0xF7UL) | HSUSBD_EP_RSPCTL_HALT;
+ }
+}
+
+
+/*
+ * Clear Stall for USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_ClrStallEP(U32 EPNum)
+{
+ uint32_t u32Ep, u32Num;
+ u32Num = EPNum & 0x0F;
+ u32Ep = USBD_NUM_TO_EP(u32Num);
+
+ if (u32Ep == CEP) {
+ HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR_Msk);
+ } else {
+ HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD->EP[u32Ep].EPRSPCTL & HSUSBD_EP_RSPCTL_MODE_MASK) | HSUSBD_EP_RSPCTL_TOGGLE;
+ }
+}
+
+
+/*
+ * Clear USB Device Endpoint Buffer
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_ClearEPBuf(U32 EPNum)
+{
+}
+
+
+/*
+ * Read USB Device Endpoint Data
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * pData: Pointer to Data Buffer
+ * Return Value: Number of bytes read
+ */
+
+U32 USBD_ReadEP(U32 EPNum, U8 *pData, U32 bufsz)
+{
+ uint32_t u32Ep, u32Num, u32Len, i;
+ u32Num = EPNum & 0x0F;
+ u32Ep = USBD_NUM_TO_EP(u32Num);
+
+ if (u32Num == 0) {
+ if (pData == (uint8_t *)&USBD_SetupPacket) {
+ *((uint16_t *)(pData + 0)) = (uint16_t)(HSUSBD->SETUP1_0 & 0xFFFFUL);
+ *((uint16_t *)(pData + 2)) = (uint16_t)(HSUSBD->SETUP3_2 & 0xFFFFUL);
+ *((uint16_t *)(pData + 4)) = (uint16_t)(HSUSBD->SETUP5_4 & 0xFFFFUL);
+ *((uint16_t *)(pData + 6)) = (uint16_t)(HSUSBD->SETUP7_6 & 0xFFFFUL);
+ return 8;
+ } else {
+ u32Len = HSUSBD->CEPDATCNT & 0xFFFFUL;
+
+ if (u32Len > bufsz) {
+ u32Len = bufsz;
+ }
+
+ for (i = 0; i < bufsz; i++) {
+ pData[i] = inpb(&HSUSBD->CEPDAT);
+ }
+
+ return u32Len;
+ }
+ } else {
+ u32Len = HSUSBD->EP[u32Ep].EPDATCNT & 0xFFFFUL;
+
+ if (u32Len > bufsz) {
+ u32Len = bufsz;
+ }
+
+ for (i = 0; i < u32Len; i++) {
+ pData[i] = HSUSBD->EP[u32Ep].EPDAT_BYTE;
+ }
+
+ return u32Len;
+ }
+}
+
+
+/*
+ * Write USB Device Endpoint Data
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * pData: Pointer to Data Buffer
+ * cnt: Number of bytes to write
+ * Return Value: Number of bytes written
+ */
+
+U32 USBD_WriteEP(U32 EPNum, U8 *pData, U32 cnt)
+{
+ uint32_t u32Ep, u32Num, i;
+ u32Num = EPNum & 0x0F;
+ u32Ep = USBD_NUM_TO_EP(u32Num);
+
+ if (u32Num == 0) {
+ if (pData != NULL) {
+ if (cnt > 0) {
+ for (i = 0; i < cnt; i++) {
+ HSUSBD->CEPDAT_BYTE = pData[i];
+ }
+
+ HSUSBD_START_CEP_IN(cnt);
+ } else {
+ HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_ZEROLEN);
+ }
+ } else if (cnt == 0) {
+ g_u8StatusIn = 1;
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk);
+ HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR);
+ }
+
+ return cnt;
+ } else {
+ if (cnt > 0) {
+ for (i = 0; i < cnt; i++) {
+ HSUSBD->EP[u32Ep].EPDAT_BYTE = pData[i];
+ }
+
+ HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD->EP[u32Ep].EPRSPCTL & HSUSBD_EP_RSPCTL_HALT) | HSUSBD_EP_RSPCTL_SHORTTXEN;
+ } else {
+ HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD->EP[u32Ep].EPRSPCTL & HSUSBD_EP_RSPCTL_HALT) | HSUSBD_EP_RSPCTL_ZEROLEN;
+ }
+
+ return cnt;
+ }
+}
+
+
+/*
+ * Get USB Device Last Frame Number
+ * Parameters: None
+ * Return Value: Frame Number
+ */
+
+U32 USBD_GetFrame(void)
+{
+ return 0;
+}
+
+
+#ifdef __RTX
+U32 LastError;
+
+/*
+ * Get USB Last Error Code
+ * Parameters: None
+ * Return Value: Error Code
+ */
+
+U32 USBD_GetError(void)
+{
+ return (LastError);
+}
+#endif
+
+
+/*
+ * USB Device Interrupt Service Routine
+ */
+
+void USBD20_IRQHandler(void)
+{
+ NVIC_DisableIRQ(USBD20_IRQn);
+ USBD_SignalHandler();
+}
+
+void USBD_Handler_Main()
+{
+ __IO uint32_t IrqStL, IrqSt;
+ uint32_t u32Ep, u32Num, i;
+ IrqStL = HSUSBD->GINTSTS & HSUSBD->GINTEN;
+
+ if (!IrqStL) {
+ return;
+ }
+
+ if (IrqStL & HSUSBD_GINTSTS_USBIF_Msk) {
+ IrqSt = HSUSBD->BUSINTSTS & HSUSBD->BUSINTEN;
+
+ if (IrqSt & HSUSBD_BUSINTSTS_SOFIF_Msk) {
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_SOF, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_SOF_Event) {
+ USBD_P_SOF_Event();
+ }
+
+#endif
+ HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_SOFIF_Msk);
+ }
+
+ if (IrqSt & HSUSBD_BUSINTSTS_RSTIF_Msk) {
+ USBD_Reset();
+ usbd_reset_core();
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_RESET, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Reset_Event) {
+ USBD_P_Reset_Event();
+ }
+
+#endif
+ HSUSBD_ENABLE_BUS_INT(HSUSBD_BUSINTEN_RSTIEN_Msk | HSUSBD_BUSINTEN_RESUMEIEN_Msk | HSUSBD_BUSINTEN_SUSPENDIEN_Msk | HSUSBD_BUSINTEN_SOFIEN_Msk);
+ HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_RSTIF_Msk);
+ HSUSBD_CLR_CEP_INT_FLAG(0x1FFC);
+ }
+
+ if (IrqSt & HSUSBD_BUSINTSTS_RESUMEIF_Msk) {
+ USBD_WakeUp();
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_RESUME, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Resume_Event) {
+ USBD_P_Resume_Event();
+ }
+
+#endif
+ HSUSBD_ENABLE_BUS_INT(HSUSBD_BUSINTEN_RSTIEN_Msk | HSUSBD_BUSINTEN_SUSPENDIEN_Msk | HSUSBD_BUSINTEN_SOFIEN_Msk);
+ HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_RESUMEIF_Msk);
+ }
+
+ if (IrqSt & HSUSBD_BUSINTSTS_SUSPENDIF_Msk) {
+ USBD_Suspend();
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_SUSPEND, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Suspend_Event) {
+ USBD_P_Suspend_Event();
+ }
+
+#endif
+ HSUSBD_ENABLE_BUS_INT(HSUSBD_BUSINTEN_RSTIEN_Msk | HSUSBD_BUSINTEN_RESUMEIEN_Msk | HSUSBD_BUSINTEN_SOFIEN_Msk);
+ HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_SUSPENDIF_Msk);
+ }
+
+ if (IrqSt & HSUSBD_BUSINTSTS_VBUSDETIF_Msk) {
+ if (HSUSBD_IS_ATTACHED()) {
+ HSUSBD_ENABLE_USB();
+ } else {
+ HSUSBD_DISABLE_USB();
+ }
+
+ HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_VBUSDETIF_Msk);
+ }
+ }
+
+ if (IrqStL & HSUSBD_GINTSTS_CEPIF_Msk) {
+ IrqSt = HSUSBD->CEPINTSTS & HSUSBD->CEPINTEN;
+
+ if (IrqSt & HSUSBD_CEPINTSTS_SETUPPKIF_Msk) {
+#ifdef __RTX
+
+ if (USBD_RTX_EPTask[0]) {
+ isr_evt_set(USBD_EVT_SETUP, USBD_RTX_EPTask[0]);
+ }
+
+#else
+
+ if (USBD_P_EP[0]) {
+ USBD_P_EP[0](USBD_EVT_SETUP);
+ }
+
+#endif
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_SETUPPKIF_Msk);
+ return;
+ }
+
+ if (IrqSt & HSUSBD_CEPINTSTS_TXPKIF_Msk) {
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk);
+ HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR);
+#ifdef __RTX
+
+ if (USBD_RTX_EPTask[0]) {
+ isr_evt_set(USBD_EVT_IN, USBD_RTX_EPTask[0]);
+ }
+
+#else
+
+ if (USBD_P_EP[0]) {
+ USBD_P_EP[0](USBD_EVT_IN);
+ }
+
+#endif
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_TXPKIF_Msk);
+ return;
+ }
+
+ if (IrqSt & HSUSBD_CEPINTSTS_RXPKIF_Msk) {
+#ifdef __RTX
+
+ if (USBD_RTX_EPTask[0]) {
+ isr_evt_set(USBD_EVT_OUT, USBD_RTX_EPTask[0]);
+ }
+
+#else
+
+ if (USBD_P_EP[0]) {
+ USBD_P_EP[0](USBD_EVT_OUT);
+ }
+
+#endif
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_RXPKIF_Msk);
+ return;
+ }
+
+ if (IrqSt & HSUSBD_CEPINTSTS_STSDONEIF_Msk) {
+ if (g_u8StatusIn == 0) {
+#ifdef __RTX
+
+ if (USBD_RTX_EPTask[0]) {
+ isr_evt_set(USBD_EVT_OUT, USBD_RTX_EPTask[0]);
+ }
+
+#else
+
+ if (USBD_P_EP[0]) {
+ USBD_P_EP[0](USBD_EVT_OUT);
+ }
+
+#endif
+ } else {
+#ifdef __RTX
+
+ if (USBD_RTX_EPTask[0]) {
+ isr_evt_set(USBD_EVT_IN, USBD_RTX_EPTask[0]);
+ }
+
+#else
+
+ if (USBD_P_EP[0]) {
+ USBD_P_EP[0](USBD_EVT_IN);
+ }
+
+#endif
+ }
+
+ g_u8StatusIn = 0;
+ HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk);
+ return;
+ }
+ }
+
+ for (i = 0; i < HSUSBD_MAX_EP; i++) {
+ u32Ep = EPA + i;
+ u32Num = USBD_EP_TO_NUM(u32Ep);
+
+ if (IrqStL & (0x1UL << (HSUSBD_GINTSTS_EPAIF_Pos + i))) {
+ IrqSt = HSUSBD->EP[u32Ep].EPINTSTS & HSUSBD->EP[u32Ep].EPINTEN;
+
+ if (IrqSt & HSUSBD_EPINTSTS_TXPKIF_Msk) {
+#ifdef __RTX
+
+ if (USBD_RTX_EPTask[u32Num]) {
+ isr_evt_set(USBD_EVT_IN, USBD_RTX_EPTask[u32Num]);
+ }
+
+#else
+
+ if (USBD_P_EP[u32Num]) {
+ USBD_P_EP[u32Num](USBD_EVT_IN);
+ }
+
+#endif
+ }
+
+ if (IrqSt & (HSUSBD_EPINTSTS_RXPKIF_Msk | HSUSBD_EPINTSTS_SHORTRXIF_Msk | HSUSBD_EPINTEN_BUFFULLIEN_Msk)) {
+#ifdef __RTX
+
+ if (USBD_RTX_EPTask[u32Num]) {
+ isr_evt_set(USBD_EVT_OUT, USBD_RTX_EPTask[u32Num]);
+ }
+
+#else
+
+ if (USBD_P_EP[u32Num]) {
+ USBD_P_EP[u32Num](USBD_EVT_OUT);
+ }
+
+#endif
+ }
+
+ HSUSBD_CLR_EP_INT_FLAG(u32Ep, IrqSt);
+ }
+ }
+}
+
+void USBD_Handler(void)
+{
+ USBD_Handler_Main();
+ NVIC_EnableIRQ(USBD20_IRQn);
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc11u35/DAP_config.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc11u35/DAP_config.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,526 @@
+/**
+ * @file DAP_config.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __DAP_CONFIG_H__
+#define __DAP_CONFIG_H__
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
+\ingroup DAP_ConfigIO_gr
+@{
+Provides definitions about:
+ - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
+ - Debug Unit communication packet size.
+ - Debug Access Port communication mode (JTAG or SWD).
+ - Optional information about a connected Target Device (for Evaluation Boards).
+*/
+
+#include "IO_Config.h"
+
+// Board configuration options
+
+// Configure JTAG option
+#if defined(BOARD_BAMBINO_210) || defined(BOARD_BAMBINO_210E)
+// LPC43xx multicore targets require JTAG to debug slave cores
+#define CONF_JTAG
+#endif
+
+/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
+/// This value is used to calculate the SWD/JTAG clock speed.
+#define CPU_CLOCK 48000000 ///< Specifies the CPU Clock in Hz
+
+/// Number of processor cycles for I/O Port write operations.
+/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
+/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
+/// requrie 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
+/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
+/// required.
+#define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
+
+/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available
+
+/// Indicate that JTAG communication mode is available at the Debug Port.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#if defined(CONF_JTAG)
+#define DAP_JTAG 1 ///< JTAG Mode: 1 = available
+#else
+#define DAP_JTAG 0 ///< JTAG Mode: 0 = not available
+#endif
+
+/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
+/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
+#define DAP_JTAG_DEV_CNT 8 ///< Maximum number of JTAG devices on scan chain
+
+/// Default communication mode on the Debug Access Port.
+/// Used for the command \ref DAP_Connect when Port Default mode is selected.
+#define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
+
+/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
+/// Used to initialize the default SWD/JTAG clock frequency.
+/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
+#define DAP_DEFAULT_SWJ_CLOCK 5000000 ///< Default SWD/JTAG clock frequency in Hz.
+
+/// Maximum Package Size for Command and Response data.
+/// This configuration settings is used to optimized the communication performance with the
+/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
+#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed.
+
+/// Maximum Package Buffers for Command and Response data.
+/// This configuration settings is used to optimized the communication performance with the
+/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
+/// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
+#define DAP_PACKET_COUNT 1 ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
+
+/// Indicate that UART Serial Wire Output (SWO) trace is available.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available
+
+/// Maximum SWO UART Baudrate
+#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz
+
+/// Indicate that Manchester Serial Wire Output (SWO) trace is available.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available
+
+/// SWO Trace Buffer Size.
+#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n)
+
+/// SWO Streaming Trace.
+#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available.
+
+/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
+#define TIMESTAMP_CLOCK 0 //100000000U ///< Timestamp clock in Hz (0 = timestamps not supported).
+
+/// Debug Unit is connected to fixed Target Device.
+/// The Debug Unit may be part of an evaluation board and always connected to a fixed
+/// known device. In this case a Device Vendor and Device Name string is stored which
+/// may be used by the debugger or IDE to configure device parameters.
+#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
+
+#if TARGET_DEVICE_FIXED
+#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor
+#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device
+#endif
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
+\ingroup DAP_ConfigIO_gr
+@{
+
+Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
+and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
+interface of a device. The following I/O Pins are provided:
+
+JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
+---------------------------- | -------------------- | ---------------------------------------------
+TCK: Test Clock | SWCLK: Clock | Output Push/Pull
+TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
+TDI: Test Data Input | | Output Push/Pull
+TDO: Test Data Output | | Input
+nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
+nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
+
+
+DAP Hardware I/O Pin Access Functions
+-------------------------------------
+The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
+these I/O Pins.
+
+For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
+This functions are provided to achieve faster I/O that is possible with some advanced GPIO
+peripherals that can independently write/read a single I/O pin without affecting any other pins
+of the same I/O port. The following SWDIO I/O Pin functions are provided:
+ - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
+ - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
+ - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
+ - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
+*/
+
+
+// Configure DAP I/O pins ------------------------------
+
+/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
+Configures the DAP Hardware I/O pins for JTAG mode:
+ - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
+ - TDO to input mode.
+*/
+__STATIC_INLINE void PORT_JTAG_SETUP(void)
+{
+#if (DAP_JTAG != 0)
+ LPC_GPIO->SET[PIN_TDI_PORT] = PIN_TDI;
+ LPC_GPIO->DIR[PIN_TDI_PORT] |= PIN_TDI;
+ LPC_GPIO->DIR[PIN_TDO_PORT] &= ~PIN_TDO;
+#endif
+}
+
+/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
+Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
+ - SWCLK, SWDIO, nRESET to output mode and set to default high level.
+ - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
+*/
+__STATIC_INLINE void PORT_SWD_SETUP(void)
+{
+ LPC_GPIO->SET[PIN_SWCLK_PORT] = PIN_SWCLK;
+ LPC_GPIO->SET[PIN_SWDIO_PORT] = PIN_SWDIO;
+#if !defined(PIN_nRESET_FET_DRIVE)
+ // open drain logic
+ LPC_GPIO->DIR[PIN_nRESET_PORT] &= ~PIN_nRESET;
+ LPC_GPIO->CLR[PIN_nRESET_PORT] = PIN_nRESET;
+#else
+ // FET drive logic
+ LPC_GPIO->DIR[PIN_nRESET_PORT] |= PIN_nRESET;
+ LPC_GPIO->CLR[PIN_nRESET_PORT] = PIN_nRESET;
+#endif
+ LPC_GPIO->DIR[PIN_SWCLK_PORT] |= PIN_SWCLK;
+ LPC_GPIO->DIR[PIN_SWDIO_PORT] |= PIN_SWDIO;
+}
+
+/** Disable JTAG/SWD I/O Pins.
+Disables the DAP Hardware I/O pins which configures:
+ - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
+*/
+__STATIC_INLINE void PORT_OFF(void)
+{
+#if !defined(PIN_nRESET_FET_DRIVE)
+ // open drain logic
+ LPC_GPIO->DIR[PIN_nRESET_PORT] &= ~PIN_nRESET;
+#else
+ // FET drive logic
+ LPC_GPIO->DIR[PIN_nRESET_PORT] |= PIN_nRESET;
+ LPC_GPIO->CLR[PIN_nRESET_PORT] = PIN_nRESET;
+#endif
+ LPC_GPIO->DIR[PIN_SWCLK_PORT] &= ~PIN_SWCLK;
+ LPC_GPIO->DIR[PIN_SWDIO_PORT] &= ~PIN_SWDIO;
+
+#if defined(TARGET_POWER_HOLD)
+ //Release Target PowerHold
+ LPC_GPIO->CLR[PIN_PWH_PORT] = PIN_PWH;
+#endif
+}
+
+
+// SWCLK/TCK I/O pin -------------------------------------
+
+/** SWCLK/TCK I/O pin: Get Input.
+\return Current status of the SWCLK/TCK DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void)
+{
+ return LPC_GPIO->B[PIN_SWCLK_BIT + PIN_SWCLK_PORT * 32] & 0x1;
+}
+
+/** SWCLK/TCK I/O pin: Set Output to High.
+Set the SWCLK/TCK DAP hardware I/O pin to high level.
+*/
+__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET(void)
+{
+ LPC_GPIO->SET[PIN_SWCLK_PORT] = PIN_SWCLK;
+}
+
+/** SWCLK/TCK I/O pin: Set Output to Low.
+Set the SWCLK/TCK DAP hardware I/O pin to low level.
+*/
+__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void)
+{
+ LPC_GPIO->CLR[PIN_SWCLK_PORT] = PIN_SWCLK;
+}
+
+
+// SWDIO/TMS Pin I/O --------------------------------------
+
+/** SWDIO/TMS I/O pin: Get Input.
+\return Current status of the SWDIO/TMS DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void)
+{
+ return LPC_GPIO->B[PIN_SWDIO_BIT + PIN_SWDIO_PORT * 32] & 0x1;
+}
+
+/** SWDIO/TMS I/O pin: Set Output to High.
+Set the SWDIO/TMS DAP hardware I/O pin to high level.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET(void)
+{
+ LPC_GPIO->SET[PIN_SWDIO_PORT] = PIN_SWDIO;
+}
+
+/** SWDIO/TMS I/O pin: Set Output to Low.
+Set the SWDIO/TMS DAP hardware I/O pin to low level.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void)
+{
+ LPC_GPIO->CLR[PIN_SWDIO_PORT] = PIN_SWDIO;
+}
+
+/** SWDIO I/O pin: Get Input (used in SWD mode only).
+\return Current status of the SWDIO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
+{
+ return LPC_GPIO->B[PIN_SWDIO_BIT + PIN_SWDIO_PORT * 32] & 0x1;
+}
+
+/** SWDIO I/O pin: Set Output (used in SWD mode only).
+\param bit Output value for the SWDIO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT(uint32_t bit)
+{
+ if (bit & 0x1) {
+ LPC_GPIO->SET[PIN_SWDIO_PORT] = PIN_SWDIO;
+ } else {
+ LPC_GPIO->CLR[PIN_SWDIO_PORT] = PIN_SWDIO;
+ }
+}
+
+/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
+Configure the SWDIO DAP hardware I/O pin to output mode. This function is
+called prior \ref PIN_SWDIO_OUT function calls.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void)
+{
+ LPC_GPIO->DIR[PIN_SWDIO_PORT] |= PIN_SWDIO;
+}
+
+/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
+Configure the SWDIO DAP hardware I/O pin to input mode. This function is
+called prior \ref PIN_SWDIO_IN function calls.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void)
+{
+ LPC_GPIO->DIR[PIN_SWDIO_PORT] &= ~(PIN_SWDIO);
+}
+
+
+// TDI Pin I/O ---------------------------------------------
+
+/** TDI I/O pin: Get Input.
+\return Current status of the TDI DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void)
+{
+#if (DAP_JTAG != 0)
+ return LPC_GPIO->B[PIN_TDI_BIT + PIN_TDI_PORT * 32] & 0x1;
+#else
+ return (0); // Not available
+#endif
+}
+
+/** TDI I/O pin: Set Output.
+\param bit Output value for the TDI DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE void PIN_TDI_OUT(uint32_t bit)
+{
+#if (DAP_JTAG != 0)
+
+ if (bit & 0x1) {
+ LPC_GPIO->SET[PIN_TDI_PORT] = PIN_TDI;
+ } else {
+ LPC_GPIO->CLR[PIN_TDI_PORT] = PIN_TDI;
+ }
+
+#else
+ ; // Not available
+#endif
+}
+
+
+// TDO Pin I/O ---------------------------------------------
+
+/** TDO I/O pin: Get Input.
+\return Current status of the TDO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void)
+{
+#if (DAP_JTAG != 0)
+ return LPC_GPIO->B[PIN_TDO_BIT + PIN_TDO_PORT * 32] & 0x1;
+#else
+ return (0); // Not available
+#endif
+}
+
+
+// nTRST Pin I/O -------------------------------------------
+
+/** nTRST I/O pin: Get Input.
+\return Current status of the nTRST DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void)
+{
+ return (0); // Not available
+}
+
+/** nTRST I/O pin: Set Output.
+\param bit JTAG TRST Test Reset pin status:
+ - 0: issue a JTAG TRST Test Reset.
+ - 1: release JTAG TRST Test Reset.
+*/
+__STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit)
+{
+ ; // Not available
+}
+
+// nRESET Pin I/O------------------------------------------
+
+/** nRESET I/O pin: Get Input.
+\return Current status of the nRESET DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void)
+{
+ return LPC_GPIO->B[PIN_nRESET_BIT + PIN_nRESET_PORT * 32] & 0x1;
+}
+
+/** nRESET I/O pin: Set Output.
+\param bit target device hardware reset pin status:
+ - 0: issue a device hardware reset.
+ - 1: release device hardware reset.
+*/
+__STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit)
+{
+#if !defined(PIN_nRESET_FET_DRIVE)
+ // open drain logic
+ if (bit) {
+ LPC_GPIO->DIR[PIN_nRESET_PORT] &= ~PIN_nRESET; // input (pulled high external)
+ } else {
+ LPC_GPIO->DIR[PIN_nRESET_PORT] |= PIN_nRESET; // output (low)
+ }
+#else
+ // FET drive logic
+ if (bit) {
+ LPC_GPIO->CLR[PIN_nRESET_PORT] = (PIN_nRESET);
+ } else {
+ LPC_GPIO->SET[PIN_nRESET_PORT] = (PIN_nRESET);
+ }
+#endif
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
+\ingroup DAP_ConfigIO_gr
+@{
+
+CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
+
+It is recommended to provide the following LEDs for status indication:
+ - Connect LED: is active when the DAP hardware is connected to a debugger.
+ - Running LED: is active when the debugger has put the target device into running state.
+*/
+
+/** Debug Unit: Set status of Connected LED.
+\param bit status of the Connect LED.
+ - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
+ - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
+*/
+__STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit)
+{
+}
+
+/** Debug Unit: Set status Target Running LED.
+\param bit status of the Target Running LED.
+ - 1: Target Running LED ON: program execution in target started.
+ - 0: Target Running LED OFF: program execution in target stopped.
+*/
+__STATIC_INLINE void LED_RUNNING_OUT(uint32_t bit)
+{
+ ; // Not available
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
+\ingroup DAP_ConfigIO_gr
+@{
+Access function for Test Domain Timer.
+
+The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
+default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
+
+*/
+
+/** Get timestamp of Test Domain Timer.
+\return Current timestamp value.
+*/
+__STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
+ return 0; //(DWT->CYCCNT);
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
+\ingroup DAP_ConfigIO_gr
+@{
+
+CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
+*/
+
+/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
+This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
+Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
+ - I/O clock system enabled.
+ - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
+ - for nTRST, nRESET a weak pull-up (if available) is enabled.
+ - LED output pins are enabled and LEDs are turned off.
+*/
+__STATIC_INLINE void DAP_SETUP(void)
+{
+ // Configure I/O pins
+ PIN_SWCLK_TCK_IOCON = PIN_SWCLK_TCK_IOCON_INIT; // SWCLK/TCK
+ PIN_SWDIO_TMS_IOCON = PIN_SWDIO_TMS_IOCON_INIT; // SWDIO/TMS
+ PIN_nRESET_IOCON = PIN_nRESET_IOCON_INIT; // nRESET
+#if (DAP_JTAG != 0)
+ PIN_TDI_IOCON = PIN_TDI_IOCON_INIT; // TDI
+ PIN_TDO_IOCON = PIN_TDO_IOCON_INIT; // TDO
+#endif
+}
+
+/** Reset Target Device with custom specific I/O pin or command sequence.
+This function allows the optional implementation of a device specific reset sequence.
+It is called when the command \ref DAP_ResetTarget and is for example required
+when a device needs a time-critical unlock sequence that enables the debug port.
+\return 0 = no device specific reset sequence is implemented.\n
+ 1 = a device specific reset sequence is implemented.
+*/
+__STATIC_INLINE uint32_t RESET_TARGET(void)
+{
+ return (0); // change to '1' when a device reset sequence is implemented
+}
+
+///@}
+
+
+#endif /* __DAP_CONFIG_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc11u35/IO_Config.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/nxp/lpc11u35/IO_Config.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,118 @@ +/** + * @file IO_Config.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +// Override all defines if IO_CONFIG_OVERRIDE is defined +#ifdef IO_CONFIG_OVERRIDE +#include "IO_Config_Override.h" +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ +#endif +#endif + + +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ + +#include "LPC11Uxx.h" +#include "daplink.h" + +// This GPIO configuration is only valid for the LPC11U35 HIC +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC11U35); + +// Peripheral register bit masks (used for pin inits) +#define FUNC_0 0 +#define FUNC_1 1 +#define PULL_DOWN_ENABLED (1 << 3) +#define PULL_UP_ENABLED (2 << 3) +#define OPENDRAIN (1 << 10) + +// DAP LED PIO0_21 +#define PIN_DAP_LED_PORT 0 +#define PIN_DAP_LED_BIT 21 +#define PIN_DAP_LED (1 << PIN_DAP_LED_BIT) +#define PIN_DAP_LED_IOCON LPC_IOCON->PIO0_21 +#define PIN_DAP_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// MSD LED PIO0_20 +#define PIN_MSD_LED_PORT 0 +#define PIN_MSD_LED_BIT 20 +#define PIN_MSD_LED (1 << PIN_MSD_LED_BIT) +#define PIN_MSD_LED_IOCON LPC_IOCON->PIO0_20 +#define PIN_MSD_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// CDC LED PIO0_11 +#define PIN_CDC_LED_PORT 0 +#define PIN_CDC_LED_BIT 11 +#define PIN_CDC_LED (1 << PIN_CDC_LED_BIT) +#define PIN_CDC_LED_IOCON LPC_IOCON->TDI_PIO0_11 +#define PIN_CDC_LED_IOCON_INIT (FUNC_1 | PULL_UP_ENABLED) + +// Non-Forwarded Reset in PIN PIO0_1 +#define PIN_RESET_IN_PORT 0 +#define PIN_RESET_IN_BIT 1 +#define PIN_RESET_IN (1 << PIN_RESET_IN_BIT) +#define PIN_RESET_IN_IOCON LPC_IOCON->PIO0_1 +#define PIN_RESET_IN_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// Forwarded Reset in PIN PIO1_19 +#define PIN_RESET_IN_FWRD_PORT 1 +#define PIN_RESET_IN_FWRD_BIT 19 +#define PIN_RESET_IN_FWRD (1 << PIN_RESET_IN_FWRD_BIT) +#define PIN_RESET_IN_FWRD_IOCON LPC_IOCON->PIO1_19 +#define PIN_RESET_IN_FWRD_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// nRESET OUT Pin PIO0_2 +#define PIN_nRESET_PORT 0 +#define PIN_nRESET_BIT 2 +#define PIN_nRESET (1 << PIN_nRESET_BIT) +#define PIN_nRESET_IOCON LPC_IOCON->PIO0_2 +#define PIN_nRESET_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) + +// SWCLK/TCK Pin PIO0_7 +#define PIN_SWCLK_PORT 0 +#define PIN_SWCLK_BIT 7 +#define PIN_SWCLK (1 << PIN_SWCLK_BIT) +#define PIN_SWCLK_TCK_IOCON LPC_IOCON->PIO0_7 +#define PIN_SWCLK_TCK_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// SWDIO/TMS In/Out Pin PIO0_8 +#define PIN_SWDIO_PORT 0 +#define PIN_SWDIO_BIT 8 +#define PIN_SWDIO (1 << PIN_SWDIO_BIT) +#define PIN_SWDIO_TMS_IOCON LPC_IOCON->PIO0_8 +#define PIN_SWDIO_TMS_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// TDI Pin PIO0_17 +#define PIN_TDI_PORT 17 +#define PIN_TDI_BIT 17 +#define PIN_TDI (1 << PIN_TDI_BIT) +#define PIN_TDI_IOCON LPC_IOCON->PIO0_17 +#define PIN_TDI_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +// SWO/TDO Pin PIO0_9 +#define PIN_TDO_PORT 9 +#define PIN_TDO_BIT 9 +#define PIN_TDO (1 << PIN_TDO_BIT) +#define PIN_TDO_IOCON LPC_IOCON->PIO0_9 +#define PIN_TDO_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc11u35/LPC11Uxx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc11u35/LPC11Uxx.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,670 @@
+
+/****************************************************************************************************//**
+ * @file LPC11Uxx.h
+ *
+ *
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
+ * default LPC11Uxx Device Series
+ *
+ * @version V0.1
+ * @date 21. March 2011
+ *
+ * @note Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45
+ *
+ * from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1,
+ * created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40
+ *
+ *******************************************************************************************************/
+
+// ################################################################################
+// Minor fix 8 April 2011 - changed LPC_CT32B1_BASE from 0x40014000 to 0x40018000
+// ################################################################################
+
+/** @addtogroup NXP
+ * @{
+ */
+
+/** @addtogroup LPC11Uxx
+ * @{
+ */
+
+#ifndef __LPC11UXX_H__
+#define __LPC11UXX_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined ( __CC_ARM )
+ #pragma anon_unions
+#endif
+
+ /* Interrupt Number Definition */
+
+typedef enum {
+// ------------------------- Cortex-M0 Processor Exceptions Numbers -----------------------------
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */
+// --------------------------- LPC11Uxx Specific Interrupt Numbers ------------------------------
+FLEX_INT0_IRQn = 0, /*!< All I/O pins can be routed to below 8 interrupts. */
+ FLEX_INT1_IRQn = 1,
+ FLEX_INT2_IRQn = 2,
+ FLEX_INT3_IRQn = 3,
+ FLEX_INT4_IRQn = 4,
+ FLEX_INT5_IRQn = 5,
+ FLEX_INT6_IRQn = 6,
+ FLEX_INT7_IRQn = 7,
+ GINT0_IRQn = 8, /*!< Grouped Interrupt 0 */
+ GINT1_IRQn = 9, /*!< Grouped Interrupt 1 */
+ Reserved0_IRQn = 10, /*!< Reserved Interrupt */
+ Reserved1_IRQn = 11,
+ Reserved2_IRQn = 12,
+ Reserved3_IRQn = 13,
+ SSP1_IRQn = 14, /*!< SSP1 Interrupt */
+ I2C_IRQn = 15, /*!< I2C Interrupt */
+ TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
+ TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
+ TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
+ TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
+ SSP0_IRQn = 20, /*!< SSP0 Interrupt */
+ UART_IRQn = 21, /*!< UART Interrupt */
+ USB_IRQn = 22, /*!< USB IRQ Interrupt */
+ USB_FIQn = 23, /*!< USB FIQ Interrupt */
+ ADC_IRQn = 24, /*!< A/D Converter Interrupt */
+ WDT_IRQn = 25, /*!< Watchdog timer Interrupt */
+ BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */
+ FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */
+ Reserved4_IRQn = 28, /*!< Reserved Interrupt */
+ Reserved5_IRQn = 29, /*!< Reserved Interrupt */
+ USBWakeup_IRQn = 30, /*!< USB wakeup Interrupt */
+ Reserved6_IRQn = 31, /*!< Reserved Interrupt */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */
+
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
+#include "system_LPC11Uxx.h" /*!< LPC11Uxx System */
+
+/** @addtogroup Device_Peripheral_Registers
+ * @{
+ */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- I2C -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (I2C)
+ */
+
+typedef struct { /*!< (@ 0x40000000) I2C Structure */
+ __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register */
+ __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register */
+ __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. */
+ __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0 */
+ __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */
+ __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */
+ __IO uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register*/
+ __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register*/
+ __IO uint32_t ADR1; /*!< (@ 0x40000020) I2C Slave Address Register 1*/
+ __IO uint32_t ADR2; /*!< (@ 0x40000024) I2C Slave Address Register 2*/
+ __IO uint32_t ADR3; /*!< (@ 0x40000028) I2C Slave Address Register 3*/
+ __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register */
+union{
+ __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register */
+ struct{
+ __IO uint32_t MASK0;
+ __IO uint32_t MASK1;
+ __IO uint32_t MASK2;
+ __IO uint32_t MASK3;
+ };
+ };
+} LPC_I2C_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- WWDT -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3 (WWDT)
+ */
+
+typedef struct { /*!< (@ 0x40004000) WWDT Structure */
+ __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register*/
+ __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register */
+ __IO uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register */
+ __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register */
+ __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
+ __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
+ __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
+} LPC_WWDT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USART -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3 (USART)
+ */
+
+typedef struct { /*!< (@ 0x40008000) USART Structure */
+
+ union {
+ __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
+ __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
+ __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
+ };
+
+ union {
+ __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
+ __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
+ };
+
+ union {
+ __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
+ __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
+ };
+ __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
+ __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
+ __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
+ __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
+ __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
+ __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
+ __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
+ __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
+ __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
+ __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
+ __I uint32_t RESERVED0[3];
+ __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
+ __I uint32_t RESERVED1;
+ __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
+ __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
+ __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
+ __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
+ __IO uint32_t SYNCCTRL;
+} LPC_USART_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- Timer -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3
+ */
+
+typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
+ __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register */
+ __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register */
+ __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter */
+ __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register */
+ __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter */
+ __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register */
+ union {
+ __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register */
+ struct{
+ __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
+ __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
+ __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
+ __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
+ };
+ };
+ __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register */
+ union{
+ __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register */
+ struct{
+ __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
+ __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
+ __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
+ __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
+ };
+ };
+__IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register */
+ __I uint32_t RESERVED0[12];
+ __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register */
+ __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register */
+} LPC_CTxxBx_Type;
+
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- ADC -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3 (ADC)
+ */
+
+typedef struct { /*!< (@ 0x4001C000) ADC Structure */
+ __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register */
+ __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register */
+ __I uint32_t RESERVED0[1];
+ __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */
+ union{
+ __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
+ struct{
+ __IO uint32_t DR0; /*!< (@ 0x40020010) A/D Channel Data Register 0*/
+ __IO uint32_t DR1; /*!< (@ 0x40020014) A/D Channel Data Register 1*/
+ __IO uint32_t DR2; /*!< (@ 0x40020018) A/D Channel Data Register 2*/
+ __IO uint32_t DR3; /*!< (@ 0x4002001C) A/D Channel Data Register 3*/
+ __IO uint32_t DR4; /*!< (@ 0x40020020) A/D Channel Data Register 4*/
+ __IO uint32_t DR5; /*!< (@ 0x40020024) A/D Channel Data Register 5*/
+ __IO uint32_t DR6; /*!< (@ 0x40020028) A/D Channel Data Register 6*/
+ __IO uint32_t DR7; /*!< (@ 0x4002002C) A/D Channel Data Register 7*/
+ };
+ };
+ __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. */
+} LPC_ADC_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- PMU -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3 (PMU)
+ */
+
+typedef struct { /*!< (@ 0x40038000) PMU Structure */
+ __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
+ union{
+ __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
+ struct{
+ __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
+ __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
+ __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
+ __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
+ };
+ };
+} LPC_PMU_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- FLASHCTRL -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3 (FLASHCTRL)
+ */
+
+typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
+ __I uint32_t RESERVED0[4];
+ __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
+ __I uint32_t RESERVED1[3];
+ __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
+ __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
+ __I uint32_t RESERVED2[1];
+ __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
+ __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
+ __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
+ __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
+ __I uint32_t RESERVED3[1001];
+ __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
+ __I uint32_t RESERVED4[1];
+ __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
+} LPC_FLASHCTRL_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SSP0/1 -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0)
+ */
+
+typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
+ __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
+ __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
+ __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
+ __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
+ __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
+ __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
+ __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
+ __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
+ __IO uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
+} LPC_SSPx_Type;
+
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- IOCONFIG -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
+ */
+
+typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
+ __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
+ __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
+ __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
+ __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
+ __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
+ __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
+ __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
+ __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
+ __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */
+ __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */
+ __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
+ __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
+ __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
+ __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
+ __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
+ __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
+ __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
+ __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
+ __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
+ __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
+ __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
+ __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
+ __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
+ __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
+ __IO uint32_t PIO1_0; /*!< Offset: 0x060 */
+ __IO uint32_t PIO1_1;
+ __IO uint32_t PIO1_2;
+ __IO uint32_t PIO1_3;
+ __IO uint32_t PIO1_4; /*!< Offset: 0x070 */
+ __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
+ __IO uint32_t PIO1_6;
+ __IO uint32_t PIO1_7;
+ __IO uint32_t PIO1_8; /*!< Offset: 0x080 */
+ __IO uint32_t PIO1_9;
+ __IO uint32_t PIO1_10;
+ __IO uint32_t PIO1_11;
+ __IO uint32_t PIO1_12; /*!< Offset: 0x090 */
+ __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */
+ __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */
+ __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
+ __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
+ __IO uint32_t PIO1_17;
+ __IO uint32_t PIO1_18;
+ __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
+ __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
+ __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
+ __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
+ __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
+ __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
+ __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
+ __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
+ __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
+ __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
+ __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
+ __IO uint32_t PIO1_30;
+ __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
+} LPC_IOCON_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SYSCON -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3 (SYSCON)
+ */
+
+typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
+ __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
+ __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
+ __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
+ __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
+ __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
+ __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
+ __I uint32_t RESERVED0[2];
+ __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
+ __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
+ __I uint32_t RESERVED1[2];
+ __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
+ __I uint32_t RESERVED2[3];
+ __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
+ __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */
+ __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
+ __IO uint32_t USBPLLCLKUEN; /*!< (@ 0x4004804C) USB PLL clock source update enable */
+ __I uint32_t RESERVED3[8];
+ __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
+ __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */
+ __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
+ __I uint32_t RESERVED4[1];
+ __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
+ __I uint32_t RESERVED5[4];
+ __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
+ __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
+ __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
+ __I uint32_t RESERVED6[8];
+ __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
+ __IO uint32_t USBCLKUEN; /*!< (@ 0x400480C4) USB clock source update enable */
+ __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
+ __I uint32_t RESERVED7[5];
+ __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
+ __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */
+ __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
+ __I uint32_t RESERVED8[5];
+ __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
+ __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
+ __I uint32_t RESERVED9[18];
+ __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
+ __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
+ __I uint32_t RESERVED10[6];
+ __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay */
+ __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
+ __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
+ __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
+ __I uint32_t RESERVED11[25];
+ __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
+ __I uint32_t RESERVED12[3];
+ __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
+ __I uint32_t RESERVED13[6];
+ __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
+ __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
+ __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
+ __I uint32_t RESERVED14[110];
+ __I uint32_t DEVICE_ID; /*!< (@ 0x400483F4) Device ID */
+} LPC_SYSCON_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_PIN_INT -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PIN_INT)
+ */
+
+typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
+ __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
+ __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
+ __IO uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
+ __IO uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
+ __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
+ __IO uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
+ __IO uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
+ __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
+ __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
+ __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
+} LPC_GPIO_PIN_INT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_GROUP_INT0/1 -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_GROUP_INT0)
+ */
+
+typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
+ __I uint32_t RESERVED0[7];
+ __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
+ __I uint32_t RESERVED1[6];
+ __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
+} LPC_GPIO_GROUP_INTx_Type;
+
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USB -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (USB)
+ */
+
+typedef struct { /*!< (@ 0x40080000) USB Structure */
+ __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40080000) USB Device Command/Status register */
+ __IO uint32_t INFO; /*!< (@ 0x40080004) USB Info register */
+ __IO uint32_t EPLISTSTART; /*!< (@ 0x40080008) USB EP Command/Status List start address */
+ __IO uint32_t DATABUFSTART; /*!< (@ 0x4008000C) USB Data buffer start address */
+ __IO uint32_t LPM; /*!< (@ 0x40080010) Link Power Management register */
+ __IO uint32_t EPSKIP; /*!< (@ 0x40080014) USB Endpoint skip */
+ __IO uint32_t EPINUSE; /*!< (@ 0x40080018) USB Endpoint Buffer in use */
+ __IO uint32_t EPBUFCFG; /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */
+ __IO uint32_t INTSTAT; /*!< (@ 0x40080020) USB interrupt status register */
+ __IO uint32_t INTEN; /*!< (@ 0x40080024) USB interrupt enable register */
+ __IO uint32_t INTSETSTAT; /*!< (@ 0x40080028) USB set interrupt status register */
+ __IO uint32_t INTROUTING; /*!< (@ 0x4008002C) USB interrupt routing register */
+ __I uint32_t RESERVED0[1];
+ __I uint32_t EPTOGGLE; /*!< (@ 0x40080034) USB Endpoint toggle register */
+} LPC_USB_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_PORT -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
+ */
+
+typedef struct {
+ union {
+ struct {
+ __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
+ __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
+ };
+ __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
+ };
+ __I uint32_t RESERVED0[1008];
+ union {
+ struct {
+ __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
+ __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
+ };
+ __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
+ };
+ uint32_t RESERVED1[960];
+ __IO uint32_t DIR[2]; /* 0x2000 */
+ uint32_t RESERVED2[30];
+ __IO uint32_t MASK[2]; /* 0x2080 */
+ uint32_t RESERVED3[30];
+ __IO uint32_t PIN[2]; /* 0x2100 */
+ uint32_t RESERVED4[30];
+ __IO uint32_t MPIN[2]; /* 0x2180 */
+ uint32_t RESERVED5[30];
+ __IO uint32_t SET[2]; /* 0x2200 */
+ uint32_t RESERVED6[30];
+ __O uint32_t CLR[2]; /* 0x2280 */
+ uint32_t RESERVED7[30];
+ __O uint32_t NOT[2]; /* 0x2300 */
+} LPC_GPIO_Type;
+
+
+#if defined ( __CC_ARM )
+ #pragma no_anon_unions
+#endif
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- Peripheral memory map -----
+// ------------------------------------------------------------------------------------------------
+
+#define LPC_I2C_BASE (0x40000000)
+#define LPC_WWDT_BASE (0x40004000)
+#define LPC_USART_BASE (0x40008000)
+#define LPC_CT16B0_BASE (0x4000C000)
+#define LPC_CT16B1_BASE (0x40010000)
+#define LPC_CT32B0_BASE (0x40014000)
+#define LPC_CT32B1_BASE (0x40018000)
+#define LPC_ADC_BASE (0x4001C000)
+#define LPC_PMU_BASE (0x40038000)
+#define LPC_FLASHCTRL_BASE (0x4003C000)
+#define LPC_SSP0_BASE (0x40040000)
+#define LPC_SSP1_BASE (0x40058000)
+#define LPC_IOCON_BASE (0x40044000)
+#define LPC_SYSCON_BASE (0x40048000)
+#define LPC_GPIO_PIN_INT_BASE (0x4004C000)
+#define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
+#define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
+#define LPC_USB_BASE (0x40080000)
+#define LPC_GPIO_BASE (0x50000000)
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- Peripheral declaration -----
+// ------------------------------------------------------------------------------------------------
+
+#define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
+#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
+#define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
+#define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)
+#define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)
+#define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)
+#define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)
+#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
+#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
+#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
+#define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)
+#define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
+#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
+#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
+#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
+#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE)
+#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE)
+#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
+#define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group (null) */
+/** @} */ /* End of group LPC11Uxx */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif // __LPC11UXX_H__
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc11u35/armcc/startup_LPC11Uxx.s --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/nxp/lpc11u35/armcc/startup_LPC11Uxx.s Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,346 @@ +;/** +; * @file startup_LPC11Uxx.s +; * @brief +; * +; * DAPLink Interface Firmware +; * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000100 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + IMPORT g_board_info +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DAPLINK_BUILD_KEY ; Build type - BL/IF + DCD DAPLINK_HIC_ID ; Compatibility + DCD DAPLINK_VERSION ; Version + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD g_board_info ; Ptr to Board info, family info other target details + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx + DCD FLEX_INT1_IRQHandler + DCD FLEX_INT2_IRQHandler + DCD FLEX_INT3_IRQHandler + DCD FLEX_INT4_IRQHandler + DCD FLEX_INT5_IRQHandler + DCD FLEX_INT6_IRQHandler + DCD FLEX_INT7_IRQHandler + DCD GINT0_IRQHandler + DCD GINT1_IRQHandler ; PIO0 (0:7) + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD SSP1_IRQHandler ; SSP1 + DCD I2C_IRQHandler ; I2C + DCD TIMER16_0_IRQHandler ; 16-bit Timer0 + DCD TIMER16_1_IRQHandler ; 16-bit Timer1 + DCD TIMER32_0_IRQHandler ; 32-bit Timer0 + DCD TIMER32_1_IRQHandler ; 32-bit Timer1 + DCD SSP0_IRQHandler ; SSP0 + DCD UART_IRQHandler ; UART + DCD USB_IRQHandler ; USB IRQ + DCD USB_FIQHandler ; USB FIQ + DCD ADC_IRQHandler ; A/D Converter + DCD WDT_IRQHandler ; Watchdog timer + DCD BOD_IRQHandler ; Brown Out Detect + DCD FMC_IRQHandler ; IP2111 Flash Memory Controller + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler ; Reserved + DCD USBWakeup_IRQHandler ; USB wake up + DCD Reserved_IRQHandler ; Reserved + + + IF :DEF:MBED_BOOTLOADER + ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + ENDIF + + IF :LNOT::DEF:NO_CRP + AREA |.ARM.__at_0x02FC|, CODE, READONLY +CRP_Key DCD 0xFFFFFFFF + ENDIF + + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + ; Power on RAM1 and USBRAM area + LDR R0, =0x40048080 ; System clock control + LDR R1, =0x0C00485F ; boot default + RAM1, USBRAM + STR R1, [R0] + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled +; for particular peripheral. +;NMI_Handler PROC +; EXPORT NMI_Handler [WEAK] +; B . +; ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Reserved_IRQHandler PROC + EXPORT Reserved_IRQHandler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT NMI_Handler [WEAK] + EXPORT FLEX_INT0_IRQHandler [WEAK] + EXPORT FLEX_INT1_IRQHandler [WEAK] + EXPORT FLEX_INT2_IRQHandler [WEAK] + EXPORT FLEX_INT3_IRQHandler [WEAK] + EXPORT FLEX_INT4_IRQHandler [WEAK] + EXPORT FLEX_INT5_IRQHandler [WEAK] + EXPORT FLEX_INT6_IRQHandler [WEAK] + EXPORT FLEX_INT7_IRQHandler [WEAK] + EXPORT GINT0_IRQHandler [WEAK] + EXPORT GINT1_IRQHandler [WEAK] + EXPORT SSP1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT TIMER16_0_IRQHandler [WEAK] + EXPORT TIMER16_1_IRQHandler [WEAK] + EXPORT TIMER32_0_IRQHandler [WEAK] + EXPORT TIMER32_1_IRQHandler [WEAK] + EXPORT SSP0_IRQHandler [WEAK] + EXPORT UART_IRQHandler [WEAK] + + EXPORT USB_IRQHandler [WEAK] + EXPORT USB_FIQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT USBWakeup_IRQHandler [WEAK] + +NMI_Handler +FLEX_INT0_IRQHandler +FLEX_INT1_IRQHandler +FLEX_INT2_IRQHandler +FLEX_INT3_IRQHandler +FLEX_INT4_IRQHandler +FLEX_INT5_IRQHandler +FLEX_INT6_IRQHandler +FLEX_INT7_IRQHandler +GINT0_IRQHandler +GINT1_IRQHandler +SSP1_IRQHandler +I2C_IRQHandler +TIMER16_0_IRQHandler +TIMER16_1_IRQHandler +TIMER32_0_IRQHandler +TIMER32_1_IRQHandler +SSP0_IRQHandler +UART_IRQHandler +USB_IRQHandler +USB_FIQHandler +ADC_IRQHandler +WDT_IRQHandler +BOD_IRQHandler +FMC_IRQHandler +USBWakeup_IRQHandler + + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc11u35/daplink_addr.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/nxp/lpc11u35/daplink_addr.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,88 @@ +/** + * @file daplink_addr.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef DAPLINK_ADDR_H +#define DAPLINK_ADDR_H + +/* Device sizes */ + +#define DAPLINK_ROM_START 0x00000000 +#define DAPLINK_ROM_SIZE 0x00010000 + +#define DAPLINK_RAM_START 0x10000000 +#define DAPLINK_RAM_SIZE (0x00002000 - DAPLINK_DEV_IAP_RESERVED) + +// region at the end of RAM1 used by IAP driver +#define DAPLINK_DEV_IAP_RESERVED 0x00000020 + +/* ROM sizes */ + +#define DAPLINK_ROM_BL_START 0x00000000 +#define DAPLINK_ROM_BL_SIZE 0x00000000 + +#define DAPLINK_ROM_CONFIG_ADMIN_START 0x00000000 +#define DAPLINK_ROM_CONFIG_ADMIN_SIZE 0x00000000 + +#define DAPLINK_ROM_IF_START 0x00000000 +#define DAPLINK_ROM_IF_SIZE 0x0000F000 + +#define DAPLINK_ROM_CONFIG_USER_START 0x0000F000 +#define DAPLINK_ROM_CONFIG_USER_SIZE 0x00001000 + +/* RAM sizes */ + +#define DAPLINK_RAM_APP_START 0x10000000 +#define DAPLINK_RAM_APP_SIZE (0x00001F00 - DAPLINK_DEV_IAP_RESERVED) + +#define DAPLINK_RAM_SHARED_START (0x10001F00 - DAPLINK_DEV_IAP_RESERVED) +#define DAPLINK_RAM_SHARED_SIZE 0x00000100 + +#define DAPLINK_RAM_APP2_START 0x20000000 +#define DAPLINK_RAM_APP2_SIZE 0x00000800 + +/* Flash Programming Info */ + +#define DAPLINK_SECTOR_SIZE 0x00000100 +#define DAPLINK_MIN_WRITE_SIZE 0x00000100 + +/* Current build */ + +#if defined(DAPLINK_BL) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_BL_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_IF_SIZE + +#elif defined(DAPLINK_IF) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_IF_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_BL_SIZE + +#else + +#error "Build must be either bootloader or interface" + +#endif + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc11u35/flash.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc11u35/flash.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,120 @@
+/**
+ * @file flash.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+#include "flash_hal.h"
+#include "iap.h"
+#include "util.h"
+#include "LPC11Uxx.h"
+
+// page buffer must be 4 byte algined and must reside in ram bank 1
+static __attribute__((section("RAM1"))) uint32_t page_buf[64];
+
+static uint32_t get_sector_num(uint32_t addr);
+
+uint32_t Init(uint32_t adr, uint32_t clk, uint32_t fnc)
+{
+ return 0; // No init needed
+}
+
+uint32_t UnInit(uint32_t fnc)
+{
+ return 0; // No init needed
+}
+
+uint32_t EraseChip(void)
+{
+ return (1); // IAP not supported
+}
+
+uint32_t EraseSector(uint32_t adr)
+{
+ uint32_t num = get_sector_num(adr);
+
+ iap_lock();
+
+ iap_op.cmd = 50; // Prepare Sector for Erase
+ iap_op.par[0] = num; // Start Sector
+ iap_op.par[1] = num; // End Sector
+ iap_call(&iap_op);
+ if (iap_op.stat != CMD_SUCCESS) {
+ iap_unlock();
+ return (1);
+ }
+
+ iap_op.cmd = 52; // Erase Sector
+ iap_op.par[0] = num; // Start Sector
+ iap_op.par[1] = num; // End Sector
+ iap_op.par[2] = SystemCoreClock / 1000; // Core Clock in kHz
+ iap_call(&iap_op);
+ if (iap_op.stat != CMD_SUCCESS) {
+ iap_unlock();
+ return (1);
+ }
+
+ iap_unlock();
+
+ return 0; // Success
+}
+
+uint32_t ProgramPage(uint32_t adr, uint32_t sz, uint32_t *buf)
+{
+ uint32_t num = get_sector_num(adr);
+
+ iap_lock();
+
+ iap_op.cmd = 50; // Prepare Sector for Program
+ iap_op.par[0] = num; // Start Sector
+ iap_op.par[1] = num; // End Sector
+ iap_call(&iap_op);
+ if (iap_op.stat != CMD_SUCCESS) {
+ iap_unlock();
+ return (1);
+ }
+
+ while (sz > 0) {
+ uint32_t copy_size = MIN(sz, sizeof(page_buf));
+ memset(page_buf, 0xFF, sizeof(page_buf));
+ memcpy(page_buf, buf, copy_size);
+ iap_op.cmd = 51; // Erase Sector
+ iap_op.par[0] = adr; // Destination
+ iap_op.par[1] = (uint32_t)page_buf; // Source
+ iap_op.par[2] = 256; // Write size
+ iap_op.par[3] = SystemCoreClock / 1000; // Core Clock in kHz
+ iap_call(&iap_op);
+ if (iap_op.stat != CMD_SUCCESS) {
+ iap_unlock();
+ return (1);
+ }
+ sz -= copy_size;
+ adr += copy_size;
+ buf += copy_size / 4;
+ }
+
+ iap_unlock();
+
+ return 0; // Success
+}
+
+static uint32_t get_sector_num(uint32_t addr)
+{
+ return addr / 0x1000;
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc11u35/gpio.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc11u35/gpio.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,156 @@
+/**
+ * @file gpio.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "LPC11Uxx.h"
+#include "gpio.h"
+#include "compiler.h"
+#include "IO_Config.h"
+#include "settings.h"
+#include "iap.h"
+
+static void busy_wait(uint32_t cycles)
+{
+ volatile uint32_t i;
+ i = cycles;
+
+ while (i > 0) {
+ i--;
+ }
+}
+
+void gpio_init(void)
+{
+ // enable clock for GPIO port 0
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1UL << 6);
+#if defined(TARGET_POWER_HOLD)
+ // Target PowerHOLD port
+ PIN_PWH_IOCON = PIN_PWH_IOCON_INIT;
+ LPC_GPIO->CLR[PIN_PWH_PORT] = PIN_PWH;
+ LPC_GPIO->DIR[PIN_PWH_PORT] |= PIN_PWH;
+#endif
+ // configure GPIO-LED as output
+#if defined(CONTROLLED_POWER_LED)
+ // Power led (red)
+ PIN_POW_LED_IOCON = PIN_POW_LED_IOCON_INIT;
+ LPC_GPIO->CLR[PIN_POW_LED_PORT] = PIN_POW_LED;
+ LPC_GPIO->DIR[PIN_POW_LED_PORT] |= PIN_POW_LED;
+#endif
+ // DAP led (green)
+ PIN_DAP_LED_IOCON = PIN_DAP_LED_IOCON_INIT;
+ LPC_GPIO->SET[PIN_DAP_LED_PORT] = PIN_DAP_LED;
+ LPC_GPIO->DIR[PIN_DAP_LED_PORT] |= PIN_DAP_LED;
+ // MSD led (red)
+ PIN_MSD_LED_IOCON = PIN_MSD_LED_IOCON_INIT;
+ LPC_GPIO->SET[PIN_MSD_LED_PORT] = PIN_MSD_LED;
+ LPC_GPIO->DIR[PIN_MSD_LED_PORT] |= PIN_MSD_LED;
+ // Serial LED (blue)
+ PIN_CDC_LED_IOCON = PIN_CDC_LED_IOCON_INIT;
+ LPC_GPIO->SET[PIN_CDC_LED_PORT] = PIN_CDC_LED;
+ LPC_GPIO->DIR[PIN_CDC_LED_PORT] |= PIN_CDC_LED;
+ // configure Button(s) as input
+ PIN_RESET_IN_IOCON = PIN_RESET_IN_IOCON_INIT;
+ LPC_GPIO->DIR[PIN_RESET_IN_PORT] &= ~PIN_RESET_IN;
+ PIN_RESET_IN_FWRD_IOCON = PIN_RESET_IN_FWRD_IOCON_INIT;
+ LPC_GPIO->DIR[PIN_RESET_IN_FWRD_PORT] &= ~PIN_RESET_IN_FWRD;
+#if !defined(PIN_nRESET_FET_DRIVE)
+ // open drain logic for reset button
+ PIN_nRESET_IOCON = PIN_nRESET_IOCON_INIT;
+ LPC_GPIO->CLR[PIN_nRESET_PORT] = PIN_nRESET;
+ LPC_GPIO->DIR[PIN_nRESET_PORT] &= ~PIN_nRESET;
+#else
+ // FET drive logic for reset button
+ PIN_nRESET_IOCON = PIN_nRESET_IOCON_INIT;
+ LPC_GPIO->CLR[PIN_nRESET_PORT] = PIN_nRESET;
+ LPC_GPIO->DIR[PIN_nRESET_PORT] |= PIN_nRESET;
+#endif
+ /* Enable AHB clock to the FlexInt, GroupedInt domain. */
+ LPC_SYSCON->SYSAHBCLKCTRL |= ((1 << 19) | (1 << 23) | (1 << 24));
+ // Give the cap on the reset button time to charge
+ busy_wait(10000);
+
+ if (gpio_get_reset_btn() || config_ram_get_initial_hold_in_bl()) {
+ IRQn_Type irq;
+ // Disable SYSTICK timer and interrupt before calling into ISP
+ SysTick->CTRL &= ~(SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_TICKINT_Msk);
+
+ // Disable all nvic interrupts
+ for (irq = (IRQn_Type)0; irq < (IRQn_Type)32; irq++) {
+ NVIC_DisableIRQ(irq);
+ NVIC_ClearPendingIRQ(irq);
+ }
+
+ // If switching to "bootloader" mode then setup the watchdog
+ // so it will exit CRP mode after ~30 seconds
+ if (config_ram_get_initial_hold_in_bl()) {
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 15); // Enable watchdog module
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 6); // Enable watchdog clock (WDOSC)
+ LPC_SYSCON->WDTOSCCTRL = (0xF << 5); // Set max frequency - 2.3MHz
+ LPC_WWDT->CLKSEL = (1 << 0); // Select watchdog clock
+ LPC_WWDT->TC = 0x00FFFFFF; // Set time to reset to ~29s
+ LPC_WWDT->MOD = (1 << 0) | (1 << 1); // Enable watchdog and set reset
+ LPC_WWDT->FEED = 0xAA; // Enable watchdog
+ LPC_WWDT->FEED = 0x55;
+ }
+
+ iap_reinvoke();
+ }
+}
+
+void gpio_set_hid_led(gpio_led_state_t state)
+{
+ if (state) {
+ LPC_GPIO->CLR[PIN_DAP_LED_PORT] = PIN_DAP_LED;
+ } else {
+ LPC_GPIO->SET[PIN_DAP_LED_PORT] = PIN_DAP_LED;
+ }
+}
+
+void gpio_set_cdc_led(gpio_led_state_t state)
+{
+ if (state) {
+ LPC_GPIO->CLR[PIN_CDC_LED_PORT] = PIN_CDC_LED;
+ } else {
+ LPC_GPIO->SET[PIN_CDC_LED_PORT] = PIN_CDC_LED;
+ }
+}
+
+void gpio_set_msc_led(gpio_led_state_t state)
+{
+ if (state) {
+ LPC_GPIO->CLR[PIN_MSD_LED_PORT] = PIN_MSD_LED;
+ } else {
+ LPC_GPIO->SET[PIN_MSD_LED_PORT] = PIN_MSD_LED;
+ }
+}
+
+uint8_t gpio_get_reset_btn_no_fwrd()
+{
+ return LPC_GPIO->PIN[PIN_RESET_IN_PORT] & PIN_RESET_IN ? 0 : 1;
+}
+
+uint8_t gpio_get_reset_btn_fwrd()
+{
+ return LPC_GPIO->PIN[PIN_RESET_IN_FWRD_PORT] & PIN_RESET_IN_FWRD ? 0 : 1;
+}
+
+void gpio_set_board_power(bool powerEnabled)
+{
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc11u35/iap.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc11u35/iap.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,95 @@
+/**
+ * @file iap.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "iap.h"
+#include "cortex_m.h"
+#include "LPC11Uxx.h"
+
+iap_operation_t iap_op;
+static cortex_int_state_t state;
+static uint32_t lock_count;
+
+// taken code from the Nxp App Note AN11305
+/* This data must be global so it is not read from the stack */
+typedef void (*IAP)(uint32_t [], uint32_t []);
+static const IAP iap_entry = (IAP)0x1fff1ff1;
+#define init_msdstate() *((uint32_t *)(0x10000054)) = 0x0
+
+/* This function resets some microcontroller peripherals to reset
+ * hardware configuration to ensure that the USB In-System Programming module
+ * will work properly. It is normally called from reset and assumes some reset
+ * configuration settings for the MCU.
+ * Some of the peripheral configurations may be redundant in your specific
+ * project.
+ */
+void iap_reinvoke(void)
+{
+ /* make sure USB clock is turned on before calling ISP */
+ LPC_SYSCON->SYSAHBCLKCTRL |= 0x04000;
+ /* make sure 32-bit Timer 1 is turned on before calling ISP */
+ LPC_SYSCON->SYSAHBCLKCTRL |= 0x00400;
+ /* make sure GPIO clock is turned on before calling ISP */
+ LPC_SYSCON->SYSAHBCLKCTRL |= 0x00040;
+ /* make sure IO configuration clock is turned on before calling ISP */
+ LPC_SYSCON->SYSAHBCLKCTRL |= 0x10000;
+ /* make sure AHB clock divider is 1:1 */
+ LPC_SYSCON->SYSAHBCLKDIV = 1;
+ /* Send Reinvoke ISP command to ISP entry point*/
+ iap_op.cmd = 57;
+ init_msdstate(); /* Initialize Storage state machine */
+ /* Set stack pointer to ROM value (reset default) This must be the last
+ * piece of code executed before calling ISP, because most C expressions
+ * and function returns will fail after the stack pointer is changed.
+ * In addition ensure the CONTROL register is set to 0 so the MSP is
+ * used rather than the PSP.
+ */
+ __set_MSP(*((volatile uint32_t *)0x00000000));
+ __set_CONTROL(0);
+ /* Enter ISP. We call "iap_entry" to enter ISP because the ISP entry is done
+ * through the same command interface as IAP.
+ */
+ iap_entry(&iap_op.cmd, &iap_op.stat);
+ // Not supposed to come back!
+}
+
+void iap_call(iap_operation_t *operation)
+{
+ iap_entry(&operation->cmd, &operation->stat);
+}
+
+void iap_lock()
+{
+ cortex_int_state_t local_state;
+ local_state = cortex_int_get_and_disable();
+ if (lock_count == 0) {
+ state = local_state;
+ }
+ lock_count++;
+}
+
+void iap_unlock()
+{
+ lock_count--;
+ if (lock_count == 0) {
+ cortex_int_restore(state);
+ }
+
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc11u35/iap.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc11u35/iap.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,44 @@
+/**
+ * @file iap.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef IAP_H
+#define IAP_H
+
+#include<stdint.h>
+
+#define CMD_SUCCESS 0
+
+typedef struct {
+ uint32_t cmd;
+ uint32_t par[4];
+ uint32_t stat;
+ uint32_t res[4];
+} iap_operation_t;
+
+extern iap_operation_t iap_op;
+
+void iap_lock(void);
+void iap_unlock(void);
+void iap_call(iap_operation_t* operation);
+void iap_reinvoke(void);
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc11u35/read_uid.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc11u35/read_uid.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,35 @@
+/**
+ * @file read_uid.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "read_uid.h"
+#include "iap.h"
+
+void read_unique_id(uint32_t *id)
+{
+ iap_lock();
+
+ // readUID IAP call
+ iap_op.cmd = 58;
+ iap_call(&iap_op);
+ *id = iap_op.res[0] ^ iap_op.res[1] ^ iap_op.res[2] ^ iap_op.res[3];
+
+ iap_unlock();
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc11u35/system_LPC11Uxx.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc11u35/system_LPC11Uxx.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,454 @@
+/******************************************************************************
+ * @file system_LPC11Uxx.c
+ * @purpose CMSIS Cortex-M3 Device Peripheral Access Layer Source File
+ * for the NXP LPC13xx Device Series
+ * @version V1.10
+ * @date 24. November 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include "stdint.h"
+#include "LPC11Uxx.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Clock Configuration ----------------------------------
+//
+// <e> Clock Configuration
+// <h> System Oscillator Control Register (SYSOSCCTRL)
+// <o1.0> BYPASS: System Oscillator Bypass Enable
+// <i> If enabled then PLL input (sys_osc_clk) is fed
+// <i> directly from XTALIN and XTALOUT pins.
+// <o1.9> FREQRANGE: System Oscillator Frequency Range
+// <i> Determines frequency range for Low-power oscillator.
+// <0=> 1 - 20 MHz
+// <1=> 15 - 25 MHz
+// </h>
+//
+// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
+// <o2.0..4> DIVSEL: Select Divider for Fclkana
+// <i> wdt_osc_clk = Fclkana/ (2 × (1 + DIVSEL))
+// <0-31>
+// <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
+// <0=> Undefined
+// <1=> 0.5 MHz
+// <2=> 0.8 MHz
+// <3=> 1.1 MHz
+// <4=> 1.4 MHz
+// <5=> 1.6 MHz
+// <6=> 1.8 MHz
+// <7=> 2.0 MHz
+// <8=> 2.2 MHz
+// <9=> 2.4 MHz
+// <10=> 2.6 MHz
+// <11=> 2.7 MHz
+// <12=> 2.9 MHz
+// <13=> 3.1 MHz
+// <14=> 3.2 MHz
+// <15=> 3.4 MHz
+// </h>
+//
+// <h> System PLL Control Register (SYSPLLCTRL)
+// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+// <i> F_clkin must be in the range of 10 MHz to 25 MHz
+// <i> F_CCO must be in the range of 156 MHz to 320 MHz
+// <o3.0..4> MSEL: Feedback Divider Selection
+// <i> M = MSEL + 1
+// <0-31>
+// <o3.5..6> PSEL: Post Divider Selection
+// <0=> P = 1
+// <1=> P = 2
+// <2=> P = 4
+// <3=> P = 8
+// </h>
+//
+// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
+// <o4.0..1> SEL: System PLL Clock Source
+// <0=> IRC Oscillator
+// <1=> System Oscillator
+// <2=> Reserved
+// <3=> Reserved
+// </h>
+//
+// <h> Main Clock Source Select Register (MAINCLKSEL)
+// <o5.0..1> SEL: Clock Source for Main Clock
+// <0=> IRC Oscillator
+// <1=> Input Clock to System PLL
+// <2=> WDT Oscillator
+// <3=> System PLL Clock Out
+// </h>
+//
+// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
+// <o6.0..7> DIV: System AHB Clock Divider
+// <i> Divides main clock to provide system clock to core, memories, and peripherals.
+// <i> 0 = is disabled
+// <0-255>
+// </h>
+//
+// <h> USB PLL Control Register (USBPLLCTRL)
+// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+// <i> F_clkin must be in the range of 10 MHz to 25 MHz
+// <i> F_CCO must be in the range of 156 MHz to 320 MHz
+// <o7.0..4> MSEL: Feedback Divider Selection
+// <i> M = MSEL + 1
+// <0-31>
+// <o7.5..6> PSEL: Post Divider Selection
+// <0=> P = 1
+// <1=> P = 2
+// <2=> P = 4
+// <3=> P = 8
+// </h>
+//
+// <h> USB PLL Clock Source Select Register (USBPLLCLKSEL)
+// <o8.0..1> SEL: USB PLL Clock Source
+// <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
+// <0=> IRC Oscillator
+// <1=> System Oscillator
+// <2=> Reserved
+// <3=> Reserved
+// </h>
+//
+// <h> USB Clock Source Select Register (USBCLKSEL)
+// <o9.0..1> SEL: System PLL Clock Source
+// <0=> USB PLL out
+// <1=> Main clock
+// <2=> Reserved
+// <3=> Reserved
+// </h>
+//
+// <h> USB Clock Divider Register (USBCLKDIV)
+// <o10.0..7> DIV: USB Clock Divider
+// <i> Divides USB clock to 48 MHz.
+// <i> 0 = is disabled
+// <0-255>
+// </h>
+// </e>
+*/
+#define CLOCK_SETUP 1
+#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
+#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
+#define SYSPLLCTRL_Val 0x00000023 // Reset: 0x000
+#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
+#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
+#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
+#define USBPLLCTRL_Val 0x00000023 // Reset: 0x000
+#define USBPLLCLKSEL_Val 0x00000001 // Reset: 0x000
+#define USBCLKSEL_Val 0x00000000 // Reset: 0x000
+#define USBCLKDIV_Val 0x00000001 // Reset: 0x001
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
+ #error "SYSOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
+ #error "WDTOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
+ #error "SYSPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
+ #error "SYSPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
+ #error "MAINCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
+ #error "SYSAHBCLKDIV: Value out of range!"
+#endif
+
+#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
+ #error "USBPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF))
+ #error "USBPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
+ #error "USBCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
+ #error "USBCLKDIV: Value out of range!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL (12000000UL) /* Oscillator frequency */
+#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
+#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
+
+
+#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
+#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
+
+#if (CLOCK_SETUP) /* Clock Setup */
+ #if (__FREQSEL == 0)
+ #define __WDT_OSC_CLK ( 0) /* undefined */
+ #elif (__FREQSEL == 1)
+ #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
+ #elif (__FREQSEL == 2)
+ #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
+ #elif (__FREQSEL == 3)
+ #define __WDT_OSC_CLK (1100000 / __DIVSEL)
+ #elif (__FREQSEL == 4)
+ #define __WDT_OSC_CLK (1400000 / __DIVSEL)
+ #elif (__FREQSEL == 5)
+ #define __WDT_OSC_CLK (1600000 / __DIVSEL)
+ #elif (__FREQSEL == 6)
+ #define __WDT_OSC_CLK (1800000 / __DIVSEL)
+ #elif (__FREQSEL == 7)
+ #define __WDT_OSC_CLK (2000000 / __DIVSEL)
+ #elif (__FREQSEL == 8)
+ #define __WDT_OSC_CLK (2200000 / __DIVSEL)
+ #elif (__FREQSEL == 9)
+ #define __WDT_OSC_CLK (2400000 / __DIVSEL)
+ #elif (__FREQSEL == 10)
+ #define __WDT_OSC_CLK (2600000 / __DIVSEL)
+ #elif (__FREQSEL == 11)
+ #define __WDT_OSC_CLK (2700000 / __DIVSEL)
+ #elif (__FREQSEL == 12)
+ #define __WDT_OSC_CLK (2900000 / __DIVSEL)
+ #elif (__FREQSEL == 13)
+ #define __WDT_OSC_CLK (3100000 / __DIVSEL)
+ #elif (__FREQSEL == 14)
+ #define __WDT_OSC_CLK (3200000 / __DIVSEL)
+ #else
+ #define __WDT_OSC_CLK (3400000 / __DIVSEL)
+ #endif
+
+ /* sys_pllclkin calculation */
+ #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
+ #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
+ #else
+ #define __SYS_PLLCLKIN (0)
+ #endif
+
+ #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
+
+ /* main clock calculation */
+ #if ((MAINCLKSEL_Val & 0x03) == 0)
+ #define __MAIN_CLOCK (__IRC_OSC_CLK)
+ #elif ((MAINCLKSEL_Val & 0x03) == 1)
+ #define __MAIN_CLOCK (__SYS_PLLCLKIN)
+ #elif ((MAINCLKSEL_Val & 0x03) == 2)
+ #if (__FREQSEL == 0)
+ #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
+ #else
+ #define __MAIN_CLOCK (__WDT_OSC_CLK)
+ #endif
+ #elif ((MAINCLKSEL_Val & 0x03) == 3)
+ #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
+ #else
+ #define __MAIN_CLOCK (0)
+ #endif
+
+ #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
+
+#else
+ #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
+#endif // CLOCK_SETUP
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ uint32_t wdt_osc = 0;
+
+ /* Determine clock frequency according to clock register values */
+ switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
+ case 0: wdt_osc = 0; break;
+ case 1: wdt_osc = 500000; break;
+ case 2: wdt_osc = 800000; break;
+ case 3: wdt_osc = 1100000; break;
+ case 4: wdt_osc = 1400000; break;
+ case 5: wdt_osc = 1600000; break;
+ case 6: wdt_osc = 1800000; break;
+ case 7: wdt_osc = 2000000; break;
+ case 8: wdt_osc = 2200000; break;
+ case 9: wdt_osc = 2400000; break;
+ case 10: wdt_osc = 2600000; break;
+ case 11: wdt_osc = 2700000; break;
+ case 12: wdt_osc = 2900000; break;
+ case 13: wdt_osc = 3100000; break;
+ case 14: wdt_osc = 3200000; break;
+ case 15: wdt_osc = 3400000; break;
+ }
+ wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
+
+ switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* Input Clock to System PLL */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* System oscillator */
+ SystemCoreClock = __SYS_OSC_CLK;
+ break;
+ case 2: /* Reserved */
+ case 3: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ }
+ break;
+ case 2: /* WDT Oscillator */
+ SystemCoreClock = wdt_osc;
+ break;
+ case 3: /* System PLL Clock Out */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
+ SystemCoreClock = __IRC_OSC_CLK;
+ } else {
+ SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ }
+ break;
+ case 1: /* System oscillator */
+ if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
+ SystemCoreClock = __SYS_OSC_CLK;
+ } else {
+ SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ }
+ break;
+ case 2: /* Reserved */
+ case 3: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ }
+ break;
+ }
+
+ SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void) {
+ volatile uint32_t i;
+
+ // Enable USBRAM and SRAM1
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 26) | (1 << 27);
+
+#if (CLOCK_SETUP) /* Clock Setup */
+
+#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
+ LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
+ LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
+ LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
+ LPC_SYSCON->SYSPLLCLKUEN = 0x01;
+ while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
+#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
+ LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
+ while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
+#endif
+
+#if (((MAINCLKSEL_Val & 0x03) == 2) )
+ LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
+ LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
+ LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
+ LPC_SYSCON->MAINCLKUEN = 0x01;
+ while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
+
+ LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
+
+#if ((USBCLKDIV_Val & 0x1FF) != 0) /* USB clock is used */
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
+
+#if ((USBCLKSEL_Val & 0x003) == 0) /* USB clock is USB PLL out */
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
+ LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
+ LPC_SYSCON->USBPLLCLKUEN = 0x01; /* Update Clock Source */
+ LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */
+ LPC_SYSCON->USBPLLCLKUEN = 0x01;
+ while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */
+ LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
+ while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
+ LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */
+#endif
+
+ LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
+ LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
+
+#else /* USB clock is not used */
+ LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */
+ LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */
+#endif
+
+#endif
+
+ /* System clock to the IOCON needs to be enabled or
+ most of the I/O related peripherals won't work. */
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
+
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc11u35/system_LPC11Uxx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc11u35/system_LPC11Uxx.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,64 @@
+/**************************************************************************//**
+ * @file system_LPC11Uxx.h
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File
+ * for the NXP LPC11Uxx Device Series
+ * @version V1.10
+ * @date 24. November 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC11Uxx_H
+#define __SYSTEM_LPC11Uxx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "stdint.h"
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC11Uxx_H */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc11u35/uart.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc11u35/uart.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,373 @@
+/**
+ * @file uart.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "LPC11Uxx.h"
+#include "uart.h"
+#include "util.h"
+#include "circ_buf.h"
+#include "settings.h" // for config_get_overflow_detect
+
+static uint32_t baudrate;
+static uint32_t dll;
+static uint32_t tx_in_progress;
+
+extern uint32_t SystemCoreClock;
+
+#define RX_OVRF_MSG "<DAPLink:Overflow>\n"
+#define RX_OVRF_MSG_SIZE (sizeof(RX_OVRF_MSG) - 1)
+#define BUFFER_SIZE (64)
+
+circ_buf_t write_buffer;
+uint8_t write_buffer_data[BUFFER_SIZE];
+circ_buf_t read_buffer;
+uint8_t read_buffer_data[BUFFER_SIZE];
+
+static uint8_t flow_control_enabled = 0;
+
+static int32_t reset(void);
+
+int32_t uart_initialize(void)
+{
+ NVIC_DisableIRQ(UART_IRQn);
+ LPC_SYSCON->SYSAHBCLKCTRL |= ((1UL << 6) | // enable clock for GPIO
+ (1UL << 16)); // enable clock for IOCON
+ // enable clk for usart
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1UL << 12);
+ // usart clk divider = 1
+ LPC_SYSCON->UARTCLKDIV = (1UL << 0);
+ // alternate function USART and PullNone
+ LPC_IOCON->PIO0_18 |= 0x01;
+ LPC_IOCON->PIO0_19 |= 0x01;
+ // enable FIFOs (trigger level 1) and clear them
+ LPC_USART->FCR = 0x87;
+ // Transmit Enable
+ LPC_USART->TER = 0x80;
+ // reset uart
+ reset();
+ // enable rx and tx interrupt
+ LPC_USART->IER |= (1 << 0) | (1 << 1);
+ NVIC_EnableIRQ(UART_IRQn);
+ return 1;
+}
+
+int32_t uart_uninitialize(void)
+{
+ // disable interrupt
+ LPC_USART->IER &= ~(0x7);
+ NVIC_DisableIRQ(UART_IRQn);
+ // reset uart
+ reset();
+ return 1;
+}
+
+int32_t uart_reset(void)
+{
+ // disable interrupt
+ NVIC_DisableIRQ(UART_IRQn);
+ // reset uart
+ reset();
+ // enable interrupt
+ NVIC_EnableIRQ(UART_IRQn);
+ return 1;
+}
+
+int32_t uart_set_configuration(UART_Configuration *config)
+{
+ uint8_t DivAddVal = 0;
+ uint8_t MulVal = 1;
+ uint8_t mv, data_bits = 8, parity, stop_bits = 0;
+ // disable interrupt
+ NVIC_DisableIRQ(UART_IRQn);
+ // reset uart
+ reset();
+ baudrate = config->Baudrate;
+ // Compute baud rate dividers
+ mv = 15;
+ dll = util_div_round_down(SystemCoreClock, 16 * config->Baudrate);
+ DivAddVal = util_div_round(SystemCoreClock * mv, dll * config->Baudrate * 16) - mv;
+ // set LCR[DLAB] to enable writing to divider registers
+ LPC_USART->LCR |= (1 << 7);
+ // set divider values
+ LPC_USART->DLM = (dll >> 8) & 0xFF;
+ LPC_USART->DLL = (dll >> 0) & 0xFF;
+ LPC_USART->FDR = (uint32_t) DivAddVal << 0
+ | (uint32_t) MulVal << 4;
+ // clear LCR[DLAB]
+ LPC_USART->LCR &= ~(1 << 7);
+
+ // set data bits, stop bits, parity
+ if ((config->DataBits < 5) || (config->DataBits > 8)) {
+ data_bits = 8;
+ }
+
+ data_bits -= 5;
+
+ if (config->StopBits != 1 && config->StopBits != 2) {
+ stop_bits = 1;
+ }
+
+ stop_bits -= 1;
+
+ switch (config->Parity) {
+ case UART_PARITY_ODD:
+ parity = 0x01;
+ break; // Parity Odd
+
+ case UART_PARITY_EVEN:
+ parity = 0x03;
+ break; // Parity Even
+
+ case UART_PARITY_MARK:
+ parity = 0x05;
+ break; // Parity Mark
+
+ case UART_PARITY_SPACE:
+ parity = 0x07;
+ break; // Parity Space
+
+ case UART_PARITY_NONE: // Parity None
+ default:
+ parity = 0x00;
+ break;
+ }
+
+ if (flow_control_enabled) {
+ LPC_IOCON->PIO0_17 |= 0x01; // RTS
+ LPC_IOCON->PIO0_7 |= 0x01; // CTS
+ // enable auto RTS and CTS
+ LPC_USART->MCR = (1 << 6) | (1 << 7);
+ } else {
+ LPC_IOCON->PIO0_17 &= ~0x01; // RTS
+ LPC_IOCON->PIO0_7 &= ~0x01; // CTS
+ // disable auto RTS and CTS
+ LPC_USART->MCR = (0 << 6) | (0 << 7);
+ }
+
+ LPC_USART->LCR = (data_bits << 0)
+ | (stop_bits << 2)
+ | (parity << 3);
+ // Enable UART interrupt
+ NVIC_EnableIRQ(UART_IRQn);
+ return 1;
+}
+
+int32_t uart_get_configuration(UART_Configuration *config)
+{
+ float br;
+ uint32_t lcr;
+ // line control parameter
+ lcr = LPC_USART->LCR;
+ // baudrate
+ br = SystemCoreClock / (dll * 16);
+
+ // If inside +/- 2% tolerance
+ if (((br * 100) <= (baudrate * 102)) && ((br * 100) >= (baudrate * 98))) {
+ config->Baudrate = baudrate;
+ } else {
+ config->Baudrate = br;
+ }
+
+ // get data bits
+ switch ((lcr >> 0) & 3) {
+ case 0:
+ config->DataBits = UART_DATA_BITS_5;
+ break;
+
+ case 1:
+ config->DataBits = UART_DATA_BITS_6;
+ break;
+
+ case 2:
+ config->DataBits = UART_DATA_BITS_7;
+ break;
+
+ case 3:
+ config->DataBits = UART_DATA_BITS_8;
+ break;
+
+ default:
+ return 0;
+ }
+
+ // get parity
+ switch ((lcr >> 3) & 7) {
+ case 0:
+ case 2:
+ case 4:
+ case 6:
+ config->Parity = UART_PARITY_NONE;
+ break;
+
+ case 1:
+ config->Parity = UART_PARITY_ODD;
+ break;
+
+ case 3:
+ config->Parity = UART_PARITY_MARK;
+ break;
+
+ case 5:
+ config->Parity = UART_PARITY_EVEN;
+ break;
+
+ case 7:
+ config->Parity = UART_PARITY_SPACE;
+ break;
+
+ default:
+ return 0;
+ }
+
+ // get stop bits
+ switch ((lcr >> 2) & 1) {
+ case 0:
+ config->StopBits = UART_STOP_BITS_1;
+ break;
+
+ case 1:
+ config->StopBits = UART_STOP_BITS_2;
+ break;
+
+ default:
+ return 0;
+ }
+
+ // get flow control
+ if (flow_control_enabled) {
+ config->FlowControl = UART_FLOW_CONTROL_RTS_CTS;
+ }
+ else {
+ config->FlowControl = UART_FLOW_CONTROL_NONE;
+ }
+ return 1;
+}
+
+int32_t uart_write_free(void)
+{
+ return circ_buf_count_free(&write_buffer);
+}
+
+int32_t uart_write_data(uint8_t *data, uint16_t size)
+{
+ uint32_t cnt;
+
+ cnt = circ_buf_write(&write_buffer, data, size);
+
+ // enable THRE interrupt
+ LPC_USART->IER |= (1 << 1);
+
+ if (!tx_in_progress) {
+ // force THRE interrupt to start
+ NVIC_SetPendingIRQ(UART_IRQn);
+ }
+
+ return cnt;
+}
+
+
+int32_t uart_read_data(uint8_t *data, uint16_t size)
+{
+ return circ_buf_read(&read_buffer, data, size);
+}
+
+void uart_enable_flow_control(bool enabled)
+{
+ flow_control_enabled = (uint8_t)enabled;
+}
+
+void UART_IRQHandler(void)
+{
+ uint32_t iir;
+ // read interrupt status
+ iir = LPC_USART->IIR;
+
+ // handle character to transmit
+ if (circ_buf_count_used(&write_buffer) > 0) {
+ // if THR is empty
+ if (LPC_USART->LSR & (1 << 5)) {
+ LPC_USART->THR = circ_buf_pop(&write_buffer);
+ tx_in_progress = 1;
+ }
+
+ } else if (tx_in_progress) {
+ tx_in_progress = 0;
+ // disable THRE interrupt
+ LPC_USART->IER &= ~(1 << 1);
+ }
+
+ // handle received character
+ if (((iir & 0x0E) == 0x04) || // Rx interrupt (RDA)
+ ((iir & 0x0E) == 0x0C)) { // Rx interrupt (CTI)
+ while (LPC_USART->LSR & 0x01) {
+ uint32_t free;
+ uint8_t data;
+
+ data = LPC_USART->RBR;
+ free = circ_buf_count_free(&read_buffer);
+ if (free > RX_OVRF_MSG_SIZE) {
+ circ_buf_push(&read_buffer, data);
+ } else if (config_get_overflow_detect()) {
+ if (RX_OVRF_MSG_SIZE == free) {
+ circ_buf_write(&read_buffer, (uint8_t*)RX_OVRF_MSG, RX_OVRF_MSG_SIZE);
+ } else {
+ // Drop newest
+ }
+ } else {
+ // Drop oldest
+ circ_buf_pop(&read_buffer);
+ circ_buf_push(&read_buffer, data);
+ }
+ }
+ }
+
+ LPC_USART->LSR;
+}
+
+static int32_t reset(void)
+{
+ uint32_t mcr;
+ // Reset FIFOs
+ LPC_USART->FCR = 0x06;
+ baudrate = 0;
+ dll = 0;
+ tx_in_progress = 0;
+
+ circ_buf_init(&write_buffer, write_buffer_data, sizeof(write_buffer_data));
+ circ_buf_init(&read_buffer, read_buffer_data, sizeof(read_buffer_data));
+
+ // Enable loopback mode to drain remaining bytes (even if flow control is on)
+ mcr = LPC_USART->MCR;
+ LPC_USART->MCR = mcr | (1 << 4);
+
+ // Ensure a clean start, no data in either TX or RX FIFO
+ while ((LPC_USART->LSR & ((1 << 5) | (1 << 6))) != ((1 << 5) | (1 << 6))) {
+ LPC_USART->FCR = (1 << 1) | (1 << 2);
+ }
+
+ // Restore previous mode (loopback off)
+ LPC_USART->MCR = mcr;
+
+ while (LPC_USART->LSR & 0x01) {
+ LPC_USART->RBR; // Dump data from RX FIFO
+ }
+
+ return 1;
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc11u35/usb_buf.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/nxp/lpc11u35/usb_buf.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,29 @@ +/** + * @file usb_buf.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef USB_BUF_H +#define USB_BUF_H + +#include "stdint.h" + +uint32_t usb_buffer[512 / 4]; + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc11u35/usb_config.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/nxp/lpc11u35/usb_config.c Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,564 @@ +/** + * @file usb_config.c + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "util.h" + +// <e> USB Device +// <i> Enable the USB Device functionality +#define USBD_ENABLE 1 +#define USBD_RTX_CORE_STACK 0 +#define USBD_RTX_DEVICE_STACK 0 +#define USBD_RTX_ENDPOINT0_STACK 0 +#if (defined(WEBUSB_INTERFACE) || defined(WINUSB_INTERFACE) || defined(BULK_ENDPOINT)) +#define USBD_BOS_ENABLE 1 +#else +#define USBD_BOS_ENABLE 0 +#endif +// <o0.0> High-speed +// <i> Enable high-speed functionality (if device supports it) +#define USBD_HS_ENABLE 0 + +// <h> Device Settings +// <i> These settings affect Device Descriptor +// <o0> Power +// <i> Default Power Setting +// <0=> Bus-powered +// <1=> Self-powered +// <o1> Max Endpoint 0 Packet Size +// <i> Maximum packet size for endpoint zero (bMaxPacketSize0) +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes +// <o2.0..15> Vendor ID <0x0000-0xFFFF> +// <i> Vendor ID assigned by the USB-IF (idVendor) +// <o3.0..15> Product ID <0x0000-0xFFFF> +// <i> Product ID assigned by the manufacturer (idProduct) +// <o4.0..15> Device Release Number <0x0000-0xFFFF> +// <i> Device release number in binary-coded decimal (bcdDevice) +// </h> +#define USBD_POWER 0 +#define USBD_MAX_PACKET0 8 +#define USBD_DEVDESC_IDVENDOR 0x0D28 +#define USBD_DEVDESC_IDPRODUCT 0x0204 +#define USBD_DEVDESC_BCDDEVICE 0x0100 + +// <h> Configuration Settings +// <i> These settings affect Configuration Descriptor +// <o0.5> Remote Wakeup +// <i> Configuration support for remote wakeup (D5: of bmAttributes) +// <o1.0..7> Maximum Power Consumption (in mA) <0-510><#/2> +// <i> Maximum power consumption of the USB device +// <i> from the bus in this specific configuration +// <i> when the device is fully operational (bMaxPower) +// </h> +#define USBD_CFGDESC_BMATTRIBUTES 0x80 +#define USBD_CFGDESC_BMAXPOWER 0xFA + +// <h> String Settings +// <i> These settings affect String Descriptor +// <o0.0..15> Language ID <0x0000-0xFCFF> +// <i> English (United States) = 0x0409 +// <s0.126> Manufacturer String +// <i> String descriptor describing manufacturer +// <s1.126> Product String +// <i> String descriptor describing product +// <e1.0> Serial Number +// <i> Enable serial number string +// <i> If disabled serial number string will not be assigned to the USB Device +// <s2.126> Serial Number String +// <i> String descriptor describing device's serial number +// </e> +// </h> +#define USBD_STRDESC_LANGID 0x0409 +#define USBD_STRDESC_MAN L"ARM" +#ifndef USB_PROD_STR +#define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" +#else +#define _TOWIDE(x) L ## #x +#define TOWIDE(x) _TOWIDE(x) +#define USBD_STRDESC_PROD TOWIDE(USB_PROD_STR) +#endif +#define USBD_STRDESC_SER_ENABLE 1 +#define USBD_STRDESC_SER L"0001A0000000" + +// <e0> Class Support +// <i> Enables USB Device Class specific Requests +#define USBD_CLASS_ENABLE 1 + +// <e0.0> Human Interface Device (HID) +// <i> Enable class support for Human Interface Device (HID) +// <h> Interrupt Endpoint Settings +// <o1.0..4> Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o2.0..4> Interrupt Out Endpoint Number <0=> Not used <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <i> If interrupt out endpoint is not used select "Not used" +// <h> Endpoint Settings +// <o3.0..7> Maximum Endpoint Packet Size (in bytes) <0-64> +// <o4.0..7> Endpoint polling Interval (in ms) <1-255> +// <e5> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o6.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o6.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// <o7.0..7> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// </e> +// </h> +// </h> +// <h> Human Interface Device Settings +// <i> Device specific settings +// <s0.126> HID Interface String +// <o8.0..4> Number of Input Reports <1-32> +// <o9.0..4> Number of Output Reports <1-32> +// <o10.0..15> Maximum Input Report Size (in bytes) <1-65535> +// <o11.0..15> Maximum Output Report Size (in bytes) <1-65535> +// <o12.0..15> Maximum Feature Report Size (in bytes) <1-65535> +// </h> +// </e> +#ifndef HID_ENDPOINT +#define HID_ENDPOINT 0 +#else +#define HID_ENDPOINT 1 +#endif + +#ifndef WEBUSB_INTERFACE +#define WEBUSB_INTERFACE 0 +#else +#define WEBUSB_INTERFACE 1 +#endif + +#define USBD_HID_ENABLE HID_ENDPOINT +#ifndef BULK_ENDPOINT //check if bulk endpoint is not enabled +#define USBD_HID_EP_INTIN 1 +#define USBD_HID_EP_INTOUT 1 +#else //if bulk endpoint is enabled remove interrupt endpoints from the hid +#define USBD_HID_EP_INTIN 0 +#define USBD_HID_EP_INTOUT 0 +#endif +#define USBD_HID_ENABLE HID_ENDPOINT +#define USBD_HID_EP_INTIN_STACK 0 +#define USBD_HID_WMAXPACKETSIZE 64 +#define USBD_HID_BINTERVAL 1 +#define USBD_HID_HS_ENABLE 0 +#define USBD_HID_HS_WMAXPACKETSIZE 64 +#define USBD_HID_HS_BINTERVAL 6 +#define USBD_HID_STRDESC L"CMSIS-DAP v1" +#define USBD_WEBUSB_STRDESC L"WebUSB: CMSIS-DAP" +#define USBD_HID_INREPORT_NUM 1 +#define USBD_HID_OUTREPORT_NUM 1 +#define USBD_HID_INREPORT_MAX_SZ 64 +#define USBD_HID_OUTREPORT_MAX_SZ 64 +#define USBD_HID_FEATREPORT_MAX_SZ 1 + +// <e0.0> Mass Storage Device (MSC) +// <i> Enable class support for Mass Storage Device (MSC) +// <h> Bulk Endpoint Settings +// <o1.0..4> Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o2.0..4> Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o3> Maximum Packet Size <1-1024> +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5> Maximum Packet Size <1-1024> +// <o6> Maximum NAK Rate <0-255> +// </e> +// </h> +// </h> +// <h> Mass Storage Device Settings +// <i> Device specific settings +// <s0.126> MSC Interface String +// <h> Inquiry Data +// <s1.8> Vendor Identification +// <s2.16> Product Identification +// <s3.4> Product Revision Level +// </h> +// </h> +// </e> +#ifndef MSC_ENDPOINT +#define MSC_ENDPOINT 0 +#else +#define MSC_ENDPOINT 1 +#endif +#define USBD_MSC_ENABLE MSC_ENDPOINT +#define USBD_MSC_EP_BULKIN 2 +#define USBD_MSC_EP_BULKOUT 2 +#define USBD_MSC_EP_BULKIN_STACK 0 +#define USBD_MSC_WMAXPACKETSIZE 64 +#define USBD_MSC_HS_ENABLE 0 +#define USBD_MSC_HS_WMAXPACKETSIZE 512 +#define USBD_MSC_HS_BINTERVAL 0 +#define USBD_MSC_STRDESC L"USB_MSC" +// Make sure changes to USBD_MSC_INQUIRY_DATA are coordinated with mbed-ls +// since this is used to detect DAPLink drives +#define USBD_MSC_INQUIRY_DATA "MBED " \ + "VFS " \ + "0.1" + +// <e0.0> Audio Device (ADC) +// <i> Enable class support for Audio Device (ADC) +// <h> Isochronous Endpoint Settings +// <o1.0..4> Isochronous Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o2.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o3.0..10> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o5.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// </e> +// </h> +// </h> +// <h> Audio Device Settings +// <i> Device specific settings +// <s0.126> Audio Control Interface String +// <s1.126> Audio Streaming (Zero Bandwidth) Interface String +// <s2.126> Audio Streaming (Operational) Interface String +// <o6.0..7> Audio Subframe Size (in bytes) <0-255> +// <o7.0..7> Sample Resolution (in bits) <0-255> +// <o8.0..23> Sample Frequency (in Hz) <0-16777215> +// <o9> Packet Size (in bytes) <1-256> +// <o10> Packet Count <1-16> +// </h> +// </e> +#define USBD_ADC_ENABLE 0 +#define USBD_ADC_EP_ISOOUT 3 +#define USBD_ADC_WMAXPACKETSIZE 64 +#define USBD_ADC_BINTERVAL 1 +#define USBD_ADC_HS_ENABLE 0 +#define USBD_ADC_HS_WMAXPACKETSIZE 64 +#define USBD_ADC_CIF_STRDESC L"USB_ADC" +#define USBD_ADC_SIF1_STRDESC L"USB_ADC1" +#define USBD_ADC_SIF2_STRDESC L"USB_ADC2" +#define USBD_ADC_BSUBFRAMESIZE 2 +#define USBD_ADC_BBITRESOLUTION 16 +#define USBD_ADC_TSAMFREQ 32000 +#define USBD_ADC_CFG_P_S 32 +#define USBD_ADC_CFG_P_C 1 + +// <e0> Communication Device (CDC) - Abstract Control Model (ACM) +// <i> Enable class support for Communication Device (CDC) - Abstract Control Model (ACM) +// <h> Interrupt Endpoint Settings +// <o1.0..4> Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o2.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o3.0..10> Endpoint polling Interval (in ms) <0-255> +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o5.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// <o6.0..10> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// </e4> +// </h> +// </h> +// <h> Bulk Endpoint Settings +// <o7.0..4> Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o8.0..4> Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o9> Maximum Packet Size <1-1024> +// <e10> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o11> Maximum Packet Size <1-1024> +// <o12> Maximum NAK Rate <0-255> +// </e10> +// </h> +// </h> +// <h> Communication Device Settings +// <i> Device specific settings +// <s0.126> Communication Class Interface String +// <s1.126> Data Class Interface String +// <o13> Maximum Communication Device Send Buffer Size +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// <o14> Maximum Communication Device Receive Buffer Size +// <i> Minimum size must be as big as maximum packet size for Bulk Out Endpoint +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// </h> +// </e> + +#ifndef CDC_ENDPOINT +#define CDC_ENDPOINT 0 +#else +#define CDC_ENDPOINT 1 +#endif +#define USBD_CDC_ACM_ENABLE CDC_ENDPOINT +#define USBD_CDC_ACM_EP_INTIN 3 +#define USBD_CDC_ACM_EP_INTIN_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE 16 +#define USBD_CDC_ACM_BINTERVAL 32 +#define USBD_CDC_ACM_HS_ENABLE 0 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE 16 +#define USBD_CDC_ACM_HS_BINTERVAL 2 +#define USBD_CDC_ACM_EP_BULKIN 4 +#define USBD_CDC_ACM_EP_BULKOUT 4 +#define USBD_CDC_ACM_EP_BULKIN_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE1 64 +#define USBD_CDC_ACM_HS_ENABLE1 0 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE1 64 +#define USBD_CDC_ACM_HS_BINTERVAL1 0 +#define USBD_CDC_ACM_CIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_DIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_SENDBUF_SIZE 64 +#define USBD_CDC_ACM_RECEIVEBUF_SIZE 64 +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Send Buffer size must be larger or equal to Bulk In maximum packet size!" +#endif +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Receive Buffer size must be larger or equal to Bulk Out maximum packet size!" +#endif + +// <e0> Custom Class Device +// <i> Enables USB Custom Class Requests +// <i> Class IDs: +// <i> 0x00 - Class Reserved ID +// <i> 0x01 - Class Audio ID +// <i> 0x02 - Class Communications ID +// <i> 0x03 - Class Human Interface ID +// <i> 0x04 - Class Monitor ID +// <i> 0x05 - Class Physical Interface ID +// <i> 0x06 - Class Power ID +// <i> 0x07 - Class Printer ID +// <i> 0x08 - Class Storage ID +// <i> 0x09 - Class HUB ID +// <i> 0xEF - Class Miscellaneous ID +// <i> 0xFF - Class Vendor Specific ID +// </e> +#define USBD_CLS_ENABLE 0 + +// WebUSB support +#define USBD_WEBUSB_ENABLE WEBUSB_INTERFACE +#define USBD_WEBUSB_VENDOR_CODE 0x21 +#define USBD_WEBUSB_LANDING_URL "os.mbed.com/webusb/landing-page/?bid=" +#define USBD_WEBUSB_ORIGIN_URL "os.mbed.com/" + +// Microsoft OS Descriptors 2.0 (WinUSB) support +#define USBD_WINUSB_ENABLE WINUSB_INTERFACE +#define USBD_WINUSB_VENDOR_CODE 0x20 +// </e> +// </e> + +#ifndef BULK_ENDPOINT +#define BULK_ENDPOINT 0 +#else +#define BULK_ENDPOINT 1 +#endif +//There are only 5 pyhical endpt so get the hid endpts +#define USBD_BULK_ENABLE BULK_ENDPOINT +#define USBD_BULK_EP_BULKIN 1 +#define USBD_BULK_EP_BULKOUT 1 +#define USBD_BULK_WMAXPACKETSIZE 64 +#define USBD_BULK_HS_ENABLE 0 +#define USBD_BULK_HS_WMAXPACKETSIZE 512 +#define USBD_BULK_STRDESC L"CMSIS-DAP v2" + +/* USB Device Calculations ---------------------------------------------------*/ + +#define USBD_IF_NUM_MAX (USBD_BULK_ENABLE+USBD_WEBUSB_ENABLE+USBD_HID_ENABLE+USBD_MSC_ENABLE+(USBD_ADC_ENABLE*2)+(USBD_CDC_ACM_ENABLE*2)+USBD_CLS_ENABLE) +#define USBD_MULTI_IF (USBD_CDC_ACM_ENABLE*(USBD_HID_ENABLE|USBD_MSC_ENABLE|USBD_ADC_ENABLE|USBD_CLS_ENABLE|USBD_WEBUSB_ENABLE|USBD_BULK_ENABLE)) +// #define MAX(x, y) (((x) < (y)) ? (y) : (x)) +#define USBD_EP_NUM_CALC0 MAX((USBD_HID_ENABLE *(USBD_HID_EP_INTIN )), (USBD_HID_ENABLE *(USBD_HID_EP_INTOUT!=0)*(USBD_HID_EP_INTOUT))) +#define USBD_EP_NUM_CALC1 MAX((USBD_MSC_ENABLE *(USBD_MSC_EP_BULKIN )), (USBD_MSC_ENABLE *(USBD_MSC_EP_BULKOUT))) +#define USBD_EP_NUM_CALC2 MAX((USBD_ADC_ENABLE *(USBD_ADC_EP_ISOOUT )), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_INTIN))) +#define USBD_EP_NUM_CALC3 MAX((USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKIN)), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKOUT))) +#define USBD_EP_NUM_CALC4 MAX(USBD_EP_NUM_CALC0, USBD_EP_NUM_CALC1) +#define USBD_EP_NUM_CALC5 MAX(USBD_EP_NUM_CALC2, USBD_EP_NUM_CALC3) +#define USBD_EP_NUM_CALC6 MAX(USBD_EP_NUM_CALC4, USBD_EP_NUM_CALC5) +#define USBD_EP_NUM_CALC7 MAX((USBD_BULK_ENABLE*(USBD_BULK_EP_BULKIN)), (USBD_BULK_ENABLE*(USBD_BULK_EP_BULKOUT))) +#define USBD_EP_NUM MAX(USBD_EP_NUM_CALC6, USBD_EP_NUM_CALC7) + +#if (USBD_EP_NUM > 5) +#error "Lpc11u35 only have 5 pyhsical endpoints including EP0!" +#endif + +#if (USBD_HID_ENABLE) +#if (USBD_MSC_ENABLE) +#if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_MSC_EP_BULKOUT))) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKOUT))) +#error "HID and Mass Storage Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_ADC_ENABLE) +#if ((USBD_HID_EP_INTIN == USBD_ADC_EP_ISOOUT) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_ADC_EP_ISOOUT))) +#error "HID and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (((USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKOUT))|| \ + ((USBD_HID_EP_INTOUT != 0) && \ + ((USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKOUT)))) +#error "HID and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_MSC_ENABLE) +#if (USBD_ADC_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_ADC_EP_ISOOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_ADC_EP_ISOOUT)) +#error "Mass Storage Device and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Mass Storage Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_ADC_ENABLE) +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Audio Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#define USBD_ADC_CIF_NUM (0) +#define USBD_ADC_SIF1_NUM (1) +#define USBD_ADC_SIF2_NUM (2) + + +#define USBD_ADC_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+0) +#define USBD_ADC_SIF1_STR_NUM (3+USBD_STRDESC_SER_ENABLE+1) +#define USBD_ADC_SIF2_STR_NUM (3+USBD_STRDESC_SER_ENABLE+2) +#define USBD_CDC_ACM_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+0) +#define USBD_CDC_ACM_DIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+1) +#define USBD_HID_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2) +#define USBD_WEBUSB_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) +#define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) +#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) + +#if (USBD_HID_ENABLE) +#if (USBD_HID_HS_ENABLE) +#define USBD_HID_MAX_PACKET ((USBD_HID_HS_WMAXPACKETSIZE > USBD_HID_WMAXPACKETSIZE) ? USBD_HID_HS_WMAXPACKETSIZE : USBD_HID_WMAXPACKETSIZE) +#else +#define USBD_HID_MAX_PACKET (USBD_HID_WMAXPACKETSIZE) +#endif +#else +#define USBD_HID_MAX_PACKET (0) +#endif +#if (USBD_MSC_ENABLE) +#if (USBD_MSC_HS_ENABLE) +#define USBD_MSC_MAX_PACKET ((USBD_MSC_HS_WMAXPACKETSIZE > USBD_MSC_WMAXPACKETSIZE) ? USBD_MSC_HS_WMAXPACKETSIZE : USBD_MSC_WMAXPACKETSIZE) +#else +#define USBD_MSC_MAX_PACKET (USBD_MSC_WMAXPACKETSIZE) +#endif +#else +#define USBD_MSC_MAX_PACKET (0) +#endif +#if (USBD_ADC_ENABLE) +#if (USBD_ADC_HS_ENABLE) +#define USBD_ADC_MAX_PACKET ((USBD_ADC_HS_WMAXPACKETSIZE > USBD_ADC_WMAXPACKETSIZE) ? USBD_ADC_HS_WMAXPACKETSIZE : USBD_ADC_WMAXPACKETSIZE) +#else +#define USBD_ADC_MAX_PACKET (USBD_ADC_WMAXPACKETSIZE) +#endif +#else +#define USBD_ADC_MAX_PACKET (0) +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (USBD_CDC_ACM_HS_ENABLE) +#define USBD_CDC_ACM_MAX_PACKET ((USBD_CDC_ACM_HS_WMAXPACKETSIZE > USBD_CDC_ACM_WMAXPACKETSIZE) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE : USBD_CDC_ACM_WMAXPACKETSIZE) +#else +#define USBD_CDC_ACM_MAX_PACKET (USBD_CDC_ACM_WMAXPACKETSIZE) +#endif +#if (USBD_CDC_ACM_HS_ENABLE1) +#define USBD_CDC_ACM_MAX_PACKET1 ((USBD_CDC_ACM_HS_WMAXPACKETSIZE1 > USBD_CDC_ACM_WMAXPACKETSIZE1) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE1 : USBD_CDC_ACM_WMAXPACKETSIZE1) +#else +#define USBD_CDC_ACM_MAX_PACKET1 (USBD_CDC_ACM_WMAXPACKETSIZE1) +#endif +#else +#define USBD_CDC_ACM_MAX_PACKET (0) +#define USBD_CDC_ACM_MAX_PACKET1 (0) +#endif + +#if (USBD_BULK_ENABLE) +#if (USBD_BULK_HS_ENABLE) +#define USBD_BULK_MAX_PACKET ((USBD_BULK_HS_WMAXPACKETSIZE > USBD_BULK_WMAXPACKETSIZE) ? USBD_BULK_HS_WMAXPACKETSIZE : USBD_BULK_WMAXPACKETSIZE) +#else +#define USBD_BULK_MAX_PACKET (USBD_BULK_WMAXPACKETSIZE) +#endif +#else +#define USBD_BULK_MAX_PACKET (0) +#endif + +#define USBD_MAX_PACKET_CALC0 ((USBD_HID_MAX_PACKET > USBD_HID_MAX_PACKET ) ? (USBD_HID_MAX_PACKET ) : (USBD_HID_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC1 ((USBD_ADC_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET ) ? (USBD_ADC_MAX_PACKET ) : (USBD_CDC_ACM_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC2 ((USBD_MAX_PACKET_CALC0 > USBD_MAX_PACKET_CALC1 ) ? (USBD_MAX_PACKET_CALC0) : (USBD_MAX_PACKET_CALC1 )) +#define USBD_MAX_PACKET_CALC3 ((USBD_BULK_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET1 ) ? (USBD_BULK_MAX_PACKET) : (USBD_CDC_ACM_MAX_PACKET1 )) +#define USBD_MAX_PACKET ((USBD_MAX_PACKET_CALC3 > USBD_MAX_PACKET_CALC2 ) ? (USBD_MAX_PACKET_CALC3) : (USBD_MAX_PACKET_CALC2 )) + + +/*------------------------------------------------------------------------------ + * USB Config Functions + *----------------------------------------------------------------------------*/ + +#ifndef __USB_CONFIG___ +#define __USB_CONFIG__ + +#ifndef __NO_USB_LIB_C +#include "usb_lib.c" +#endif + +#endif /* __USB_CONFIG__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc11u35/usbd_LPC11Uxx.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc11u35/usbd_LPC11Uxx.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,825 @@
+/**
+ * @file usbd_LPC11Uxx.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "rl_usb.h"
+#include "LPC11Uxx.h"
+#include "compiler.h"
+#include "util.h"
+
+#define __NO_USB_LIB_C
+#include "usb_config.c"
+
+
+#define BUF_ACTIVE (1UL << 31)
+#define EP_DISABLED (1UL << 30)
+#define EP_STALL (1UL << 29)
+#define TOOGLE_RESET (1UL << 28)
+#define EP_TYPE (1UL << 26)
+
+#define N_BYTES(n) ((n & 0x3FF) << 16)
+#define BUF_ADDR(addr) (((addr) >> 6) & 0xFFFF)
+
+#define EP_OUT_IDX(EPNum) (EPNum * 2 )
+#define EP_IN_IDX(EPNum) (EPNum * 2 + 1)
+
+#define EP_LIST_BASE 0x20004000
+#define EP_BUF_BASE (U32)(EP_LIST_BASE + 0x100)
+
+typedef struct BUF_INFO {
+ U32 buf_len;
+ U32 buf_ptr;
+} EP_BUF_INFO;
+
+EP_BUF_INFO EPBufInfo[(USBD_EP_NUM + 1) * 2];
+volatile U32 EPList[(USBD_EP_NUM + 1) * 2] __at(EP_LIST_BASE);
+
+static U32 addr = 3 * 64 + EP_BUF_BASE;
+static U32 ctrl_out_next = 0;
+
+/*
+ * Get EP CmdStat pointer
+ * Parameters: EPNum: endpoint number
+ *
+ */
+
+U32 *GetEpCmdStatPtr(U32 EPNum)
+{
+ U32 ptr = 0;
+
+ if (EPNum & 0x80) {
+ EPNum &= ~0x80;
+ ptr = 8;
+ }
+
+ ptr += EP_LIST_BASE + EPNum * 16;
+ return ((U32 *)ptr);
+}
+
+
+/*
+ * Usb interrupt enable/disable
+ * Parameters: ena: enable/disable
+ * 0: disable interrupt
+ * 1: enable interrupt
+ */
+
+#ifdef __RTX
+void __svc(1) USBD_Intr(int ena);
+void __SVC_1(int ena)
+{
+ if (ena) {
+ NVIC_EnableIRQ(USB_IRQn); /* Enable USB interrupt */
+ } else {
+ NVIC_DisableIRQ(USB_IRQn); /* Disable USB interrupt */
+ }
+}
+#endif
+
+
+
+/*
+ * USB Device Initialize Function
+ * Called by the User to initialize USB Device
+ * Return Value: None
+ */
+
+void USBD_Init(void)
+{
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1UL << 6);
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1UL << 14) |
+ (1UL << 27);
+ LPC_USB->DEVCMDSTAT |= (1UL << 9); /* PLL ON */
+ LPC_IOCON->PIO0_3 &= ~(0x1F);
+ LPC_IOCON->PIO0_3 |= (1UL << 0); /* Secondary function VBUS */
+ LPC_IOCON->PIO0_6 &= ~7;
+ LPC_IOCON->PIO0_6 |= (1UL << 0); /* Secondary function USB CON */
+ LPC_SYSCON->PDRUNCFG &= ~((1UL << 8) | /* USB PLL powered */
+ (1UL << 10)); /* USB transceiver powered */
+ LPC_USB->DATABUFSTART = EP_BUF_BASE & 0xFFC00000;
+ LPC_USB->EPLISTSTART = EP_LIST_BASE;
+ NVIC_EnableIRQ(USB_IRQn);
+ USBD_Reset();
+}
+
+
+/*
+ * USB Device Connect Function
+ * Called by the User to Connect/Disconnect USB Device
+ * Parameters: con: Connect/Disconnect
+ * Return Value: None
+ */
+
+void USBD_Connect(BOOL con)
+{
+ if (con) {
+ LPC_USB->DEVCMDSTAT |= (1UL << 16); /* Set device connect status */
+ } else {
+ LPC_USB->DEVCMDSTAT &= ~(1UL << 16); /* Clear device connect status */
+ }
+
+ return;
+}
+
+
+/*
+ * USB Device Reset Function
+ * Called automatically on USB Device Reset
+ * Return Value: None
+ */
+
+void USBD_Reset(void)
+{
+ U32 i;
+ U32 *ptr;
+ addr = 3 * 64 + EP_BUF_BASE;
+
+ for (i = 2; i < (5 * 4); i++) {
+ EPList[i] = (1UL << 30); /* EPs disabled */
+ }
+
+ ctrl_out_next = 0;
+ EPBufInfo[0].buf_len = USBD_MAX_PACKET0;
+ EPBufInfo[0].buf_ptr = EP_BUF_BASE;
+ EPBufInfo[1].buf_len = USBD_MAX_PACKET0;
+ EPBufInfo[1].buf_ptr = EP_BUF_BASE + 2 * 64;
+ ptr = GetEpCmdStatPtr(0);
+ *ptr = N_BYTES(EPBufInfo[0].buf_len) | /* EP0 OUT */
+ BUF_ADDR(EPBufInfo[0].buf_ptr) |
+ BUF_ACTIVE;
+ ptr++;
+ *ptr = BUF_ADDR(EPBufInfo[0].buf_ptr + 64);/* SETUP */
+ LPC_USB->DEVCMDSTAT |= (1UL << 7); /*USB device enable */
+ LPC_USB->INTSTAT = 0x2FC; /* clear EP interrupt flags */
+ LPC_USB->INTEN = ((1UL << 30) | /* SOF intr enable */
+ (1UL << 0) | /* EP0 OUT intr enable */
+ (1UL << 1) | /* EP0 IN intr enable */
+ (1UL << 31)); /* stat change int en */
+}
+
+
+/*
+ * USB Device Suspend Function
+ * Called automatically on USB Device Suspend
+ * Return Value: None
+ */
+
+void USBD_Suspend(void)
+{
+ /* Performed by Hardware */
+}
+
+
+/*
+ * USB Device Resume Function
+ * Called automatically on USB Device Resume
+ * Return Value: None
+ */
+
+void USBD_Resume(void)
+{
+ /* Performed by Hardware */
+}
+
+
+/*
+ * USB Device Remote Wakeup Function
+ * Called automatically on USB Device Remote Wakeup
+ * Return Value: None
+ */
+
+void USBD_WakeUp(void)
+{
+ LPC_SYSCON->USBCLKCTRL = 1;
+ LPC_USB->DEVCMDSTAT &= ~(1UL << 17); /*clear device suspend status */
+
+ while (LPC_USB->DEVCMDSTAT & (1UL << 17));
+
+ LPC_SYSCON->USBCLKCTRL = 0;
+}
+
+
+/*
+ * USB Device Remote Wakeup Configuration Function
+ * Parameters: cfg: Device Enable/Disable
+ * Return Value: None
+ */
+
+void USBD_WakeUpCfg(BOOL cfg)
+{
+ if (cfg == __TRUE) {
+ LPC_USB->DEVCMDSTAT &= ~(1UL << 9); /*PPL_ON=0, in suspend clk is stoped */
+ } else {
+ LPC_USB->DEVCMDSTAT |= (1UL << 9); /*PPL_ON=1, in suspend clk isnt stoped */
+ LPC_SYSCON->USBCLKCTRL = 0;
+ }
+}
+
+
+/*
+ * USB Device Set Address Function
+ * Parameters: adr: USB Device Address
+ * Return Value: None
+ */
+
+void USBD_SetAddress(U32 adr, U32 setup)
+{
+ if (!setup) {
+ LPC_USB->DEVCMDSTAT &= ~0x7F;
+ LPC_USB->DEVCMDSTAT |= adr | (1UL << 7);
+ }
+}
+
+
+
+/*
+ * USB Device Configure Function
+ * Parameters: cfg: Device Configure/Deconfigure
+ * Return Value: None
+ */
+
+void USBD_Configure(BOOL cfg)
+{
+ addr = 3 * 64 + EP_BUF_BASE;
+}
+
+
+/*
+ * Configure USB Device Endpoint according to Descriptor
+ * Parameters: pEPD: Pointer to Device Endpoint Descriptor
+ * Return Value: None
+ */
+
+void USBD_ConfigEP(USB_ENDPOINT_DESCRIPTOR *pEPD)
+{
+ U32 num, val, type;
+ U32 *ptr;
+ num = pEPD->bEndpointAddress;
+ val = pEPD->wMaxPacketSize;
+ type = pEPD->bmAttributes & USB_ENDPOINT_TYPE_MASK;
+
+ /* IN EPs */
+ if (num & 0x80) {
+ num &= ~0x80;
+ EPBufInfo[EP_IN_IDX(num)].buf_len = val;
+ EPBufInfo[EP_IN_IDX(num)].buf_ptr = addr;
+ addr += ((val + 63) >> 6) * 64; /* calc new free buffer address */
+ ptr = GetEpCmdStatPtr(num | 0x80);
+ *ptr = EP_DISABLED;
+
+ if (type == USB_ENDPOINT_TYPE_ISOCHRONOUS) {
+ *ptr |= EP_TYPE;
+ }
+ }
+
+ /* OUT EPs */
+ else {
+ EPBufInfo[EP_OUT_IDX(num)].buf_len = val;
+ EPBufInfo[EP_OUT_IDX(num)].buf_ptr = addr;
+ ptr = GetEpCmdStatPtr(num);
+ *ptr = N_BYTES(EPBufInfo[EP_OUT_IDX(num)].buf_len) |
+ BUF_ADDR(EPBufInfo[EP_OUT_IDX(num)].buf_ptr) |
+ EP_DISABLED;
+
+ if (type == USB_ENDPOINT_TYPE_ISOCHRONOUS) {
+ *ptr |= EP_TYPE;
+ }
+
+ addr += ((val + 63) >> 6) * 64; /* calc new free buffer address */
+ }
+}
+
+
+/*
+ * Set Direction for USB Device Control Endpoint
+ * Parameters: dir: Out (dir == 0), In (dir <> 0)
+ * Return Value: None
+ */
+
+void USBD_DirCtrlEP(U32 dir)
+{
+ /* Not needed */
+}
+
+
+/*
+ * Enable USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_EnableEP(U32 EPNum)
+{
+ U32 *ptr;;
+ ptr = GetEpCmdStatPtr(EPNum);
+
+ /* IN EP */
+ if (EPNum & 0x80) {
+ EPNum &= ~0x80;
+ *ptr &= ~EP_DISABLED;
+ LPC_USB->INTSTAT = (1 << EP_IN_IDX(EPNum));
+ LPC_USB->INTEN |= (1 << EP_IN_IDX(EPNum));
+ }
+
+ /* OUT EP */
+ else {
+ *ptr &= ~EP_DISABLED;
+ *ptr |= BUF_ACTIVE;
+ LPC_USB->INTSTAT = (1 << EP_OUT_IDX(EPNum));
+ LPC_USB->INTEN |= (1 << EP_OUT_IDX(EPNum));
+ }
+}
+
+
+/*
+ * Disable USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_DisableEP(U32 EPNum)
+{
+ U32 *ptr;
+ ptr = GetEpCmdStatPtr(EPNum);
+ *ptr = EP_DISABLED;
+
+ if (EPNum & 0x80) {
+ EPNum &= ~0x80;
+ LPC_USB->INTEN &= ~(1 << EP_IN_IDX(EPNum));
+
+ } else {
+ LPC_USB->INTEN &= ~(1 << EP_OUT_IDX(EPNum));
+ }
+}
+
+
+/*
+ * Reset USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_ResetEP(U32 EPNum)
+{
+ U32 *ptr;
+ ptr = GetEpCmdStatPtr(EPNum);
+ *ptr |= TOOGLE_RESET;
+}
+
+
+/*
+ * Set Stall for USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_SetStallEP(U32 EPNum)
+{
+ U32 *ptr;
+ ptr = GetEpCmdStatPtr(EPNum);
+
+ if (EPNum & 0x7F) {
+ if (*ptr & BUF_ACTIVE) {
+ *ptr &= ~(BUF_ACTIVE);
+ }
+
+ } else {
+ if (EPNum & 0x80) {
+ EPNum &= ~0x80;
+ LPC_USB->EPSKIP |= (1 << EP_IN_IDX(EPNum));
+
+ while (LPC_USB->EPSKIP & (1 << EP_IN_IDX(EPNum)));
+
+ } else {
+ LPC_USB->EPSKIP |= (1 << EP_OUT_IDX(EPNum));
+
+ while (LPC_USB->EPSKIP & (1 << EP_OUT_IDX(EPNum)));
+ }
+ }
+
+ if ((EPNum & 0x7F) == 0) {
+ /* Endpoint is stalled so control out won't be next */
+ ctrl_out_next = 0;
+ }
+
+ *ptr |= EP_STALL;
+}
+
+
+/*
+ * Clear Stall for USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_ClrStallEP(U32 EPNum)
+{
+ U32 *ptr;
+ ptr = GetEpCmdStatPtr(EPNum);
+
+ if (EPNum & 0x80) {
+ *ptr &= ~EP_STALL;
+
+ } else {
+ *ptr &= ~EP_STALL;
+ *ptr |= BUF_ACTIVE;
+ }
+
+ USBD_ResetEP(EPNum);
+}
+
+
+/*
+ * Clear USB Device Endpoint Buffer
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_ClearEPBuf(U32 EPNum)
+{
+ U32 cnt, i;
+ U8 *dataptr;
+
+ if (EPNum & 0x80) {
+ EPNum &= ~0x80;
+ dataptr = (U8 *)EPBufInfo[EP_IN_IDX(EPNum)].buf_ptr;
+ cnt = EPBufInfo[EP_IN_IDX(EPNum)].buf_len;
+
+ for (i = 0; i < cnt; i++) {
+ dataptr[i] = 0;
+ }
+
+ } else {
+ dataptr = (U8 *)EPBufInfo[EP_OUT_IDX(EPNum)].buf_ptr;
+ cnt = EPBufInfo[EP_OUT_IDX(EPNum)].buf_len;
+
+ for (i = 0; i < cnt; i++) {
+ dataptr[i] = 0;
+ }
+ }
+}
+
+
+/*
+ * Read USB Device Endpoint Data
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * pData: Pointer to Data Buffer
+ * Return Value: Number of bytes read
+ */
+
+U32 USBD_ReadEP(U32 EPNum, U8 *pData, U32 size)
+{
+ U32 cnt, i, xfer_size;
+ volatile U32 *ptr;
+ U8 *dataptr;
+ ptr = GetEpCmdStatPtr(EPNum);
+ int timeout = 256;
+
+ /* Setup packet */
+ if ((EPNum == 0) && !ctrl_out_next && (LPC_USB->DEVCMDSTAT & (1UL << 8))) {
+ cnt = USBD_MAX_PACKET0;
+
+ if (size < cnt) {
+ util_assert(0);
+ cnt = size;
+ }
+
+ dataptr = (U8 *)(EPBufInfo[EP_OUT_IDX(EPNum)].buf_ptr + 64);
+
+ for (i = 0; i < cnt; i++) {
+ pData[i] = dataptr[i];
+ }
+
+ xfer_size = (pData[7] << 8) | (pData[6] << 0);
+ if ((xfer_size > 0) && (pData[0] & (1 << 7))) {
+ /* This control transfer has a data IN stage */
+ /* and ends with a zero length data OUT transfer. */
+ /* Ensure the data OUT token is not skipped even if */
+ /* a SETUP token arrives before USBD_ReadEP has */
+ /* been called. */
+ ctrl_out_next = 1;
+ }
+
+ LPC_USB->EPSKIP |= (1 << EP_IN_IDX(EPNum));
+
+ while (LPC_USB->EPSKIP & (1 << EP_IN_IDX(EPNum)));
+
+ if (*(ptr + 2) & EP_STALL) {
+ *(ptr + 2) &= ~(EP_STALL);
+ }
+
+ if (*ptr & EP_STALL) {
+ *ptr &= ~(EP_STALL);
+ }
+
+ LPC_USB->DEVCMDSTAT |= (1UL << 8);
+ }
+
+ /* OUT packet */
+ else {
+ ptr = GetEpCmdStatPtr(EPNum);
+ cnt = EPBufInfo[EP_OUT_IDX(EPNum)].buf_len - ((*ptr >> 16) & 0x3FF);
+ dataptr = (U8 *)EPBufInfo[EP_OUT_IDX(EPNum)].buf_ptr;
+
+ while ((timeout-- > 0) && (*ptr & BUF_ACTIVE)); //spin on the hardware until it's done
+ util_assert(!(*ptr & BUF_ACTIVE)); //check for timeout
+
+ if (size < cnt) {
+ util_assert(0);
+ cnt = size;
+ }
+
+ cnt = cnt < size ? cnt : size;
+
+ for (i = 0; i < cnt; i++) {
+ pData[i] = dataptr[i];
+ }
+
+ *ptr = N_BYTES(EPBufInfo[EP_OUT_IDX(EPNum)].buf_len) |
+ BUF_ADDR(EPBufInfo[EP_OUT_IDX(EPNum)].buf_ptr) |
+ BUF_ACTIVE;
+
+ if (EPNum == 0) {
+ /* If ctrl_out_next is set then this should be a zero length */
+ /* data OUT packet. */
+ util_assert(!ctrl_out_next || (cnt == 0));
+ ctrl_out_next = 0;
+ if (LPC_USB->DEVCMDSTAT & (1UL << 8)) {
+ // A setup packet is still pending so trigger another interrupt
+ LPC_USB->INTSETSTAT |= (1 << 0);
+ }
+ }
+ }
+
+ return (cnt);
+}
+
+
+/*
+ * Write USB Device Endpoint Data
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * pData: Pointer to Data Buffer
+ * cnt: Number of bytes to write
+ * Return Value: Number of bytes written
+ */
+
+U32 USBD_WriteEP(U32 EPNum, U8 *pData, U32 cnt)
+{
+ U32 i;
+ volatile U32 *ptr;
+ U32 *dataptr;
+ ptr = GetEpCmdStatPtr(EPNum);
+ EPNum &= ~0x80;
+
+ while (*ptr & BUF_ACTIVE);
+
+ *ptr &= ~(0x3FFFFFF);
+ *ptr |= BUF_ADDR(EPBufInfo[EP_IN_IDX(EPNum)].buf_ptr) |
+ N_BYTES(cnt);
+ dataptr = (U32 *)EPBufInfo[EP_IN_IDX(EPNum)].buf_ptr;
+
+ for (i = 0; i < (cnt + 3) / 4; i++) {
+ dataptr[i] = * ((__packed U32 *)pData);
+ pData += 4;
+ }
+
+ if (EPNum && (*ptr & EP_STALL)) {
+ return (0);
+ }
+
+ *ptr |= BUF_ACTIVE;
+ return (cnt);
+}
+
+
+/*
+ * Get USB Device Last Frame Number
+ * Parameters: None
+ * Return Value: Frame Number
+ */
+
+U32 USBD_GetFrame(void)
+{
+ return (LPC_USB->INFO & 0x7FF);
+}
+
+
+/*
+ * USB Device Interrupt Service Routine
+ */
+
+void USB_IRQHandler(void)
+{
+ NVIC_DisableIRQ(USB_IRQn);
+ USBD_SignalHandler();
+}
+
+void USBD_Handler(void)
+{
+ U32 sts, val, num, i;
+ sts = LPC_USB->INTSTAT;
+ LPC_USB->INTSTAT = sts;
+
+ /* Device Status Interrupt (Reset, Connect change, Suspend/Resume) */
+ if (sts & (1UL << 31)) {
+ val = LPC_USB->DEVCMDSTAT;
+
+ /* reset interrupt */
+ if (val & (1UL << 26)) {
+ LPC_USB->DEVCMDSTAT |= (1UL << 26);
+ USBD_Reset();
+ usbd_reset_core();
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_RESET, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Reset_Event) {
+ USBD_P_Reset_Event();
+ }
+
+#endif
+ }
+
+ /* connect interrupt */
+ if (val & (1UL << 24)) {
+ LPC_USB->DEVCMDSTAT |= (1UL << 24);
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ if (val & (1UL << 16)) {
+ isr_evt_set(USBD_EVT_POWER_ON, USBD_RTX_DevTask);
+ } else {
+ isr_evt_set(USBD_EVT_POWER_OFF, USBD_RTX_DevTask);
+ }
+ }
+
+#else
+
+ if (USBD_P_Power_Event) {
+ USBD_P_Power_Event((val >> 16) & 1);
+ }
+
+#endif
+ }
+
+ /* suspend/resume interrupt */
+ if (val & (1 << 25)) {
+ LPC_USB->DEVCMDSTAT |= (1UL << 25);
+
+ /* suspend interrupt */
+ if (val & (1UL << 17)) {
+ USBD_Suspend();
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_SUSPEND, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Suspend_Event) {
+ USBD_P_Suspend_Event();
+ }
+
+#endif
+ }
+
+ /* resume interrupt */
+ else {
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_RESUME, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Resume_Event) {
+ USBD_P_Resume_Event();
+ }
+
+#endif
+ }
+ }
+ }
+
+ /* Start of Frame */
+ if (sts & (1UL << 30)) {
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_SOF, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_SOF_Event) {
+ USBD_P_SOF_Event();
+ }
+
+#endif
+ }
+
+ /* EndPoint Interrupt */
+ if (sts & 0x3FF) {
+ const uint32_t endpoint_count = ((USBD_EP_NUM + 1) * 2);
+
+ for (i = 0; i < endpoint_count; i++) {
+ // Iterate through endpoints in the reverse order so IN endpoints
+ // get processed before OUT endpoints if they are both pending.
+ num = endpoint_count - i - 1;
+
+ if (sts & (1UL << num)) {
+ /* Setup */
+ if ((num == 0) && !ctrl_out_next && (LPC_USB->DEVCMDSTAT & (1UL << 8))) {
+#ifdef __RTX
+
+ if (USBD_RTX_EPTask[num / 2]) {
+ isr_evt_set(USBD_EVT_SETUP, USBD_RTX_EPTask[num / 2]);
+ }
+
+#else
+
+ if (USBD_P_EP[num / 2]) {
+ USBD_P_EP[num / 2](USBD_EVT_SETUP);
+ }
+
+#endif
+ }
+
+ /* OUT */
+ else if ((num % 2) == 0) {
+#ifdef __RTX
+
+ if (USBD_RTX_EPTask[num / 2]) {
+ isr_evt_set(USBD_EVT_OUT, USBD_RTX_EPTask[num / 2]);
+ }
+
+#else
+
+ if (USBD_P_EP[num / 2]) {
+ USBD_P_EP[num / 2](USBD_EVT_OUT);
+ }
+
+#endif
+ }
+
+ /* IN */
+ else {
+#ifdef __RTX
+
+ if (USBD_RTX_EPTask[num / 2]) {
+ isr_evt_set(USBD_EVT_IN, USBD_RTX_EPTask[num / 2]);
+ }
+
+#else
+
+ if (USBD_P_EP[num / 2]) {
+ USBD_P_EP[num / 2](USBD_EVT_IN);
+ }
+
+#endif
+ }
+ }
+ }
+ }
+
+ NVIC_EnableIRQ(USB_IRQn);
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc4322/DAP_config.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc4322/DAP_config.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,540 @@
+/**
+ * @file DAP_config.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __DAP_CONFIG_H__
+#define __DAP_CONFIG_H__
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
+\ingroup DAP_ConfigIO_gr
+@{
+Provides definitions about:
+ - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
+ - Debug Unit communication packet size.
+ - Debug Access Port communication mode (JTAG or SWD).
+ - Optional information about a connected Target Device (for Evaluation Boards).
+*/
+
+#include "LPC43xx.h" // Debug Unit Cortex-M Processor Header File
+#include "lpc43xx_scu.h"
+
+typedef unsigned int BOOL;
+
+#ifndef __TRUE
+ #define __TRUE 1
+#endif
+#ifndef __FALSE
+ #define __FALSE 0
+#endif
+
+/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
+/// This value is used to calculate the SWD/JTAG clock speed.
+#define CPU_CLOCK SystemCoreClock ///< Specifies the CPU Clock in Hz
+
+/// Number of processor cycles for I/O Port write operations.
+/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
+/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
+/// requrie 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
+/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
+/// required.
+#define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
+
+/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available
+
+/// Indicate that JTAG communication mode is available at the Debug Port.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available.
+
+/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
+/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
+#define DAP_JTAG_DEV_CNT 0 ///< Maximum number of JTAG devices on scan chain
+
+/// Default communication mode on the Debug Access Port.
+/// Used for the command \ref DAP_Connect when Port Default mode is selected.
+#define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
+
+/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
+/// Used to initialize the default SWD/JTAG clock frequency.
+/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
+#define DAP_DEFAULT_SWJ_CLOCK 5000000 ///< Default SWD/JTAG clock frequency in Hz.
+
+/// Maximum Package Size for Command and Response data.
+/// This configuration settings is used to optimized the communication performance with the
+/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
+#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed.
+
+/// Maximum Package Buffers for Command and Response data.
+/// This configuration settings is used to optimized the communication performance with the
+/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
+/// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
+#define DAP_PACKET_COUNT 1 ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
+
+/// Indicate that UART Serial Wire Output (SWO) trace is available.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available
+
+/// Maximum SWO UART Baudrate
+#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz
+
+/// Indicate that Manchester Serial Wire Output (SWO) trace is available.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available
+
+/// SWO Trace Buffer Size.
+#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n)
+
+/// SWO Streaming Trace.
+#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available.
+
+/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
+#define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported).
+
+
+/// Debug Unit is connected to fixed Target Device.
+/// The Debug Unit may be part of an evaluation board and always connected to a fixed
+/// known device. In this case a Device Vendor and Device Name string is stored which
+/// may be used by the debugger or IDE to configure device parameters.
+#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
+
+#if TARGET_DEVICE_FIXED
+#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor
+#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device
+#endif
+
+///@}
+
+
+// LPC43xx peripheral register bit masks (used by macros)
+#define CCU_CLK_CFG_RUN (1UL << 0)
+#define CCU_CLK_CFG_AUTO (1UL << 1)
+#define CCU_CLK_STAT_RUN (1UL << 0)
+
+// State of Reset Ouput Enable buffer
+extern BOOL gpio_reset_pin_is_input;
+
+// Debug Port I/O Pins
+
+// SWCLK Pin P1_17: GPIO0[12]
+#define PORT_SWCLK 0
+#define PIN_SWCLK_IN_BIT 12
+#define PIN_SWCLK (1<<PIN_SWCLK_IN_BIT)
+
+// SWDIO Pin P1_6: GPIO1[9]
+#define PORT_SWDIO 1
+#define PIN_SWDIO_IN_BIT 9
+#define PIN_SWDIO (1<<PIN_SWDIO_IN_BIT)
+
+// SWDIO Output Enable Pin P1_5: GPIO1[8]
+#define PORT_SWDIO_TXE 1
+#define PIN_SWDIO_TXE_IN_BIT 8
+#define PIN_SWDIO_TXE (1<<PIN_SWDIO_TXE_IN_BIT)
+
+// nRESET Pin P2_5: GPIO5[5] note: HANI_IOT workaround: changing to GPIO0[7]
+#define PORT_nRESET 0
+#define PIN_nRESET_IN_BIT 7
+#define PIN_nRESET (1<<PIN_nRESET_IN_BIT)
+
+// nRESET Output Enable Pin P2_6: GPIO5[6]
+#define PORT_RESET_TXE 5
+#define PIN_RESET_TXE_IN_BIT 6
+#define PIN_RESET_TXE (1<<PIN_RESET_TXE_IN_BIT)
+
+// ISP Control Pin P2_11: GPIO1[11]
+#define ISPCTRL_PORT 1
+#define ISPCTRL_BIT 11
+
+#define X_SET(str) LPC_GPIO_PORT->SET[PORT_##str] = PIN_##str
+#define X_CLR(str) LPC_GPIO_PORT->CLR[PORT_##str] = PIN_##str
+#define X_DIR_OUT(str) LPC_GPIO_PORT->DIR[PORT_##str] |= (PIN_##str)
+#define X_DIR_IN(str) LPC_GPIO_PORT->DIR[PORT_##str] &= ~(PIN_##str)
+#define X_BYTE(str) LPC_GPIO_PORT->B[(PORT_##str << 5) + PIN_##str##_IN_BIT]
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
+\ingroup DAP_ConfigIO_gr
+@{
+
+Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
+and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
+interface of a device. The following I/O Pins are provided:
+
+JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
+---------------------------- | -------------------- | ---------------------------------------------
+TCK: Test Clock | SWCLK: Clock | Output Push/Pull
+TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
+TDI: Test Data Input | | Output Push/Pull
+TDO: Test Data Output | | Input
+nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
+nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
+
+
+DAP Hardware I/O Pin Access Functions
+-------------------------------------
+The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
+these I/O Pins.
+
+For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
+This functions are provided to achieve faster I/O that is possible with some advanced GPIO
+peripherals that can independently write/read a single I/O pin without affecting any other pins
+of the same I/O port. The following SWDIO I/O Pin functions are provided:
+ - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
+ - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
+ - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
+ - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
+*/
+
+
+// Configure DAP I/O pins ------------------------------
+
+/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
+Configures the DAP Hardware I/O pins for JTAG mode:
+ - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
+ - TDO to input mode.
+*/
+__STATIC_INLINE void PORT_JTAG_SETUP(void) {}
+
+/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
+Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
+ - SWCLK, SWDIO, nRESET to output mode and set to default high level.
+ - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
+*/
+__STATIC_INLINE void PORT_SWD_SETUP(void)
+{
+ X_SET(SWCLK);
+ X_SET(SWDIO);
+ X_DIR_OUT(SWCLK);
+ X_DIR_OUT(SWDIO);
+ X_SET(SWDIO_TXE);
+ X_DIR_OUT(SWDIO_TXE);
+}
+
+
+/** Disable JTAG/SWD I/O Pins.
+Disables the DAP Hardware I/O pins which configures:
+ - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
+*/
+__STATIC_INLINE void PORT_OFF(void)
+{
+ X_CLR(SWCLK);
+ X_CLR(SWDIO);
+ X_DIR_OUT(SWCLK);
+ X_DIR_OUT(SWDIO);
+ X_SET(SWDIO_TXE);
+ X_DIR_OUT(SWDIO_TXE);
+}
+
+
+// SWCLK/TCK I/O pin -------------------------------------
+
+/** SWCLK/TCK I/O pin: Get Input.
+\return Current status of the SWCLK/TCK DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void)
+{
+ return (0); // Not available
+}
+
+/** SWCLK/TCK I/O pin: Set Output to High.
+Set the SWCLK/TCK DAP hardware I/O pin to high level.
+*/
+__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET(void)
+{
+ X_SET(SWCLK);
+}
+
+/** SWCLK/TCK I/O pin: Set Output to Low.
+Set the SWCLK/TCK DAP hardware I/O pin to low level.
+*/
+__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void)
+{
+ X_CLR(SWCLK);
+}
+
+
+// SWDIO/TMS Pin I/O --------------------------------------
+
+/** SWDIO/TMS I/O pin: Get Input.
+\return Current status of the SWDIO/TMS DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void)
+{
+ return X_BYTE(SWDIO) & 0x1;
+}
+
+/** SWDIO/TMS I/O pin: Set Output to High.
+Set the SWDIO/TMS DAP hardware I/O pin to high level.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET(void)
+{
+ X_SET(SWDIO);
+}
+
+/** SWDIO/TMS I/O pin: Set Output to Low.
+Set the SWDIO/TMS DAP hardware I/O pin to low level.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void)
+{
+ X_CLR(SWDIO);
+}
+
+/** SWDIO I/O pin: Get Input (used in SWD mode only).
+\return Current status of the SWDIO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
+{
+ return X_BYTE(SWDIO) & 0x1;
+}
+
+/** SWDIO I/O pin: Set Output (used in SWD mode only).
+\param bit Output value for the SWDIO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT(uint32_t bit)
+{
+ if (bit & 0x1) {
+ X_SET(SWDIO);
+ } else {
+ X_CLR(SWDIO);
+ }
+}
+
+/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
+Configure the SWDIO DAP hardware I/O pin to output mode. This function is
+called prior \ref PIN_SWDIO_OUT function calls.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void)
+{
+ X_SET(SWDIO_TXE);
+ X_DIR_OUT(SWDIO);
+}
+
+/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
+Configure the SWDIO DAP hardware I/O pin to input mode. This function is
+called prior \ref PIN_SWDIO_IN function calls.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void)
+{
+ X_DIR_IN(SWDIO);
+ X_CLR(SWDIO_TXE);
+}
+
+
+// TDI Pin I/O ---------------------------------------------
+
+/** TDI I/O pin: Get Input.
+\return Current status of the TDI DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void)
+{
+ return (0); // Not available
+}
+
+/** TDI I/O pin: Set Output.
+\param bit Output value for the TDI DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE void PIN_TDI_OUT(uint32_t bit)
+{
+ ; // Not available
+}
+
+
+// TDO Pin I/O ---------------------------------------------
+
+/** TDO I/O pin: Get Input.
+\return Current status of the TDO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void)
+{
+ return (0); // Not available
+}
+
+
+// nTRST Pin I/O -------------------------------------------
+
+/** nTRST I/O pin: Get Input.
+\return Current status of the nTRST DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void)
+{
+ return (0); // Not available
+}
+
+/** nTRST I/O pin: Set Output.
+\param bit JTAG TRST Test Reset pin status:
+ - 0: issue a JTAG TRST Test Reset.
+ - 1: release JTAG TRST Test Reset.
+*/
+__STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit)
+{
+ ; // Not available
+}
+
+// nRESET Pin I/O------------------------------------------
+
+/** nRESET I/O pin: Get Input.
+\return Current status of the nRESET DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void)
+{
+ if (gpio_reset_pin_is_input) {
+ return X_BYTE(nRESET) & 0x1;
+ } else {
+ return 0; // Always LOW when output
+ }
+}
+
+/** nRESET I/O pin: Set Output.
+\param bit target device hardware reset pin status:
+ - 0: issue a device hardware reset.
+ - 1: release device hardware reset.
+*/
+__STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit)
+{
+ if (bit) {
+ // release device hardware reset. (reset INPUT, reset oe LOW=INPUT)
+ X_DIR_IN(nRESET);
+ X_CLR(RESET_TXE);
+ gpio_reset_pin_is_input = __TRUE;
+ LPC_GPIO_PIN_INT->IST = 0x01; // ACK any pending edge interrupt
+ LPC_GPIO_PIN_INT->SIENF |= 0x1; // Enable falling edge interrupt
+ } else {
+ // issue a device hardware reset. (reset OUTPUT+LOW, reset oe HIGH=OUTPUT)
+ gpio_reset_pin_is_input = __FALSE;
+ LPC_GPIO_PIN_INT->CIENF |= 0x1; // Disable falling edge interrupt
+ LPC_GPIO_PIN_INT->IST = 0x01; // ACK any pending edge interrupt
+ X_SET(RESET_TXE);
+ X_CLR(nRESET);
+ X_DIR_OUT(nRESET);
+ }
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
+\ingroup DAP_ConfigIO_gr
+@{
+
+CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
+
+It is recommended to provide the following LEDs for status indication:
+ - Connect LED: is active when the DAP hardware is connected to a debugger.
+ - Running LED: is active when the debugger has put the target device into running state.
+*/
+
+/** Debug Unit: Set status of Connected LED.
+\param bit status of the Connect LED.
+ - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
+ - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
+*/
+__STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit)
+{
+}
+
+/** Debug Unit: Set status Target Running LED.
+\param bit status of the Target Running LED.
+ - 1: Target Running LED ON: program execution in target started.
+ - 0: Target Running LED OFF: program execution in target stopped.
+*/
+__STATIC_INLINE void LED_RUNNING_OUT(uint32_t bit)
+{
+ ; // Not available
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
+\ingroup DAP_ConfigIO_gr
+@{
+Access function for Test Domain Timer.
+
+The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
+default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
+
+*/
+
+/** Get timestamp of Test Domain Timer.
+\return Current timestamp value.
+*/
+__STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
+ return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK);
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
+\ingroup DAP_ConfigIO_gr
+@{
+
+CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
+*/
+
+/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
+This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
+Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
+ - I/O clock system enabled.
+ - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
+ - for nTRST, nRESET a weak pull-up (if available) is enabled.
+ - LED output pins are enabled and LEDs are turned off.
+*/
+__STATIC_INLINE void DAP_SETUP(void)
+{
+ /* Enable clock and init GPIO outputs */
+ LPC_CCU1->CLK_M4_GPIO_CFG = CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN;
+
+ while (!(LPC_CCU1->CLK_M4_GPIO_STAT & CCU_CLK_STAT_RUN));
+
+ /* Configure I/O pins: function number, input buffer enabled, */
+ /* no pull-up/down */
+ scu_pinmux(1, 17, GPIO_NOPULL, FUNC0); /* SWCLK/TCK: GPIO0[12] */
+ scu_pinmux(1, 6, GPIO_NOPULL, FUNC0); /* SWDIO/TMS: GPIO1[9] */
+ scu_pinmux(1, 5, GPIO_NOPULL, FUNC0); /* SWDIO_OE: GPIO1[8] */
+}
+
+/** Reset Target Device with custom specific I/O pin or command sequence.
+This function allows the optional implementation of a device specific reset sequence.
+It is called when the command \ref DAP_ResetTarget and is for example required
+when a device needs a time-critical unlock sequence that enables the debug port.
+\return 0 = no device specific reset sequence is implemented.\n
+ 1 = a device specific reset sequence is implemented.
+*/
+__STATIC_INLINE uint32_t RESET_TARGET(void)
+{
+ return (0); // change to '1' when a device reset sequence is implemented
+}
+
+///@}
+
+
+#endif /* __DAP_CONFIG_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc4322/IO_Config.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/nxp/lpc4322/IO_Config.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,33 @@ +/** + * @file IO_Config.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +// Override all defines if IO_CONFIG_OVERRIDE is defined +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ + +#include "daplink.h" +#include "LPC43xx.h" + +// This GPIO configuration is only valid for the LPC4322 HIC +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC4322); + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc4322/LPC43xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc4322/LPC43xx.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,34953 @@
+
+/****************************************************************************************************//**
+ * @file LPC43xx.h
+ *
+ * @status RELEASE
+ *
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for
+ * default LPC43xx Device Series
+ *
+ * @version V5
+ * @date 9. December 2011
+ *
+ * @note Generated with SVDConv V2.6 Build 6c on Friday, 09.12.2011 13:56:08
+ *
+ * from CMSIS SVD File 'LPC43xxv5.xml' Version 5,
+ * created on Friday, 09.12.2011 21:56:03, last modified on Friday, 09.12.2011 21:56:04
+ *
+ *******************************************************************************************************/
+
+
+
+/** @addtogroup (null)
+ * @{
+ */
+
+/** @addtogroup LPC43xx
+ * @{
+ */
+
+#ifndef __LPC43XX_H__
+#define __LPC43XX_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+/********************************************
+** Start of section using anonymous unions **
+*********************************************/
+
+#if defined(__ARMCC_VERSION)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma push
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+
+ /* Interrupt Number Definition */
+
+typedef enum {
+// ------------------------- Cortex-M4 Processor Exceptions Numbers -----------------------------
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
+ BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+ UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */
+// --------------------------- LPC43xx Specific Interrupt Numbers -------------------------------
+ DAC_IRQn = 0, /*!< 0 DAC */
+ M0CORE_IRQn = 1, /*!< 1 M0a */
+ DMA_IRQn = 2, /*!< 2 DMA */
+ RESERVED1_IRQn = 3, /*!< 3 EZH/EDM */
+ RESERVED2_IRQn = 4,
+ ETHERNET_IRQn = 5, /*!< 5 ETHERNET */
+ SDIO_IRQn = 6, /*!< 6 SDIO */
+ LCD_IRQn = 7, /*!< 7 LCD */
+ USB0_IRQn = 8, /*!< 8 USB0 */
+ USB1_IRQn = 9, /*!< 9 USB1 */
+ SCT_IRQn = 10, /*!< 10 SCT */
+ RITIMER_IRQn = 11, /*!< 11 RITIMER */
+ TIMER0_IRQn = 12, /*!< 12 TIMER0 */
+ TIMER1_IRQn = 13, /*!< 13 TIMER1 */
+ TIMER2_IRQn = 14, /*!< 14 TIMER2 */
+ TIMER3_IRQn = 15, /*!< 15 TIMER3 */
+ MCPWM_IRQn = 16, /*!< 16 MCPWM */
+ ADC0_IRQn = 17, /*!< 17 ADC0 */
+ I2C0_IRQn = 18, /*!< 18 I2C0 */
+ I2C1_IRQn = 19, /*!< 19 I2C1 */
+ SPI_INT_IRQn = 20, /*!< 20 SPI_INT */
+ ADC1_IRQn = 21, /*!< 21 ADC1 */
+ SSP0_IRQn = 22, /*!< 22 SSP0 */
+ SSP1_IRQn = 23, /*!< 23 SSP1 */
+ USART0_IRQn = 24, /*!< 24 USART0 */
+ UART1_IRQn = 25, /*!< 25 UART1 */
+ USART2_IRQn = 26, /*!< 26 USART2 */
+ USART3_IRQn = 27, /*!< 27 USART3 */
+ I2S0_IRQn = 28, /*!< 28 I2S0 */
+ I2S1_IRQn = 29, /*!< 29 I2S1 */
+ RESERVED4_IRQn = 30,
+ SGPIO_IINT_IRQn = 31, /*!< 31 SGPIO_IINT */
+ PIN_INT0_IRQn = 32, /*!< 32 PIN_INT0 */
+ PIN_INT1_IRQn = 33, /*!< 33 PIN_INT1 */
+ PIN_INT2_IRQn = 34, /*!< 34 PIN_INT2 */
+ PIN_INT3_IRQn = 35, /*!< 35 PIN_INT3 */
+ PIN_INT4_IRQn = 36, /*!< 36 PIN_INT4 */
+ PIN_INT5_IRQn = 37, /*!< 37 PIN_INT5 */
+ PIN_INT6_IRQn = 38, /*!< 38 PIN_INT6 */
+ PIN_INT7_IRQn = 39, /*!< 39 PIN_INT7 */
+ GINT0_IRQn = 40, /*!< 40 GINT0 */
+ GINT1_IRQn = 41, /*!< 41 GINT1 */
+ EVENTROUTER_IRQn = 42, /*!< 42 EVENTROUTER */
+ C_CAN1_IRQn = 43, /*!< 43 C_CAN1 */
+ RESERVED6_IRQn = 44,
+ VADC_IRQn = 45, /*!< 45 VADC */
+ ATIMER_IRQn = 46, /*!< 46 ATIMER */
+ RTC_IRQn = 47, /*!< 47 RTC */
+ RESERVED8_IRQn = 48,
+ WWDT_IRQn = 49, /*!< 49 WWDT */
+ RESERVED9_IRQn = 50,
+ C_CAN0_IRQn = 51, /*!< 51 C_CAN0 */
+ QEI_IRQn = 52, /*!< 52 QEI */
+
+// ------------------------- Cortex-M0 Processor Exceptions Numbers -----------------------------
+ M0_Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
+ M0_NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
+ M0_HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
+ M0_SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
+ M0_DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
+ M0_PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
+ M0_SysTick_IRQn = -1, /*!< 15 System Tick Timer */
+// --------------------------- LPC43xx Specific Interrupt Numbers -------------------------------
+ M0_RTC_IRQn = 0, /*!< 0 RTC */
+ M0_M4CORE_IRQn = 1, /*!< 1 M4 */
+ M0_DMA_IRQn = 2, /*!< 2 DMA */
+ M0_RESERVED0_IRQn = 3,
+ M0_RESERVED1_IRQn = 4,
+ M0_ETHERNET_IRQn = 5, /*!< 5 ETHERNET */
+ M0_SDIO_IRQn = 6, /*!< 6 SDIO */
+ M0_LCD_IRQn = 7, /*!< 7 LCD */
+ M0_USB0_IRQn = 8, /*!< 8 USB0 */
+ M0_USB1_IRQn = 9, /*!< 9 USB1 */
+ M0_SCT_IRQn = 10, /*!< 10 SCT */
+ M0_RITIMER_OR_WWDT_IRQn = 11, /*!< 11 RITIMER_OR_WWDT */
+ M0_TIMER0_IRQn = 12, /*!< 12 TIMER0 */
+ M0_GINT1_IRQn = 13, /*!< 13 GINT1 */
+ M0_TIMER3_IRQn = 15, /*!< 15 TIMER3 */
+ M0_RESERVED2_IRQn = 14,
+ M0_RESERVED3_IRQn = 15,
+ M0_MCPWM_IRQn = 16, /*!< 16 MCPWM */
+ M0_ADC0_IRQn = 17, /*!< 17 ADC0 */
+ M0_I2C0_OR_I2C1_IRQn = 18, /*!< 18 I2C0_OR_I2C1 */
+ M0_SGPIO_IRQn = 19, /*!< 19 SGPIO */
+ M0_SPI_OR_DAC_IRQn = 20, /*!< 20 SPI_OR_DAC */
+ M0_ADC1_IRQn = 21, /*!< 21 ADC1 */
+ M0_SSP0_OR_SSP1_IRQn = 22, /*!< 22 SSP0_OR_SSP1 */
+ M0_EVENTROUTER_IRQn = 23, /*!< 23 EVENTROUTER */
+ M0_USART0_IRQn = 24, /*!< 24 USART0 */
+ M0_UART1_IRQn = 25, /*!< 25 UART1 */
+ M0_USART2_OR_C_CAN1_IRQn = 26, /*!< 26 USART2_OR_C_CAN1 */
+ M0_USART3_IRQn = 27, /*!< 27 USART3 */
+ M0_I2S0_OR_I2S1_OR_QEI_IRQn = 28, /*!< 28 I2S0_OR_I2S1_OR_QEI */
+ M0_C_CAN0_IRQn = 29 /*!< 29 C_CAN0 */
+} IRQn_Type;
+
+ /* Event Router Input (ERI) Number Definitions */
+typedef enum {
+ WAKEUP0_ERIn = 0,
+ WAKEUP1_ERIn = 1,
+ WAKEUP2_ERIn = 2,
+ WAKEUP3_ERIn = 3,
+ ATIMER_ERIn = 4,
+ RTC_ERIn = 5,
+ BOD1_ERIn = 6, /* Bod trip 1 */
+ WWDT_ERIn = 7,
+ ETH_ERIn = 8,
+ USB0_ERIn = 9,
+ USB1_ERIn = 10,
+ SDIO_ERIn = 11,
+ CAN_ERIn = 12, /* CAN0/1 or'ed */
+ TIM2_ERIn = 13,
+ TIM6_ERIn = 14,
+ QEI_ERIn = 15,
+ TIM14_ERIn = 16,
+ RESERVED0_ERIn = 17, /* M0s */
+ RESERVED1_ERIn = 18, /* M3/M4 */
+ RESET_ERIn = 19
+}ERIn_Type;
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M4 Processor and Core Peripherals */
+
+#ifdef CORE_M4
+#define __CM4_REV 0x0000 /*!< Cortex-M4 Core Revision */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< FPU present or not */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */
+#else
+#ifdef CORE_M0
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 0 /*!< FPU present or not */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include <core_cm0.h> /*!< Cortex-M4 processor and core peripherals */
+#else
+#error Please #define CORE_M0 or CORE_M4
+#endif
+#endif
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+#include "system_LPC43xx.h" /*!< LPC43xx System */
+
+/** @addtogroup Device_Peripheral_Registers
+ * @{
+ */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SCT -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7 (SCT)
+ */
+
+#define CONFIG_SCT_nEV (16) /* Number of events */
+#define CONFIG_SCT_nRG (16) /* Number of match/compare registers */
+#define CONFIG_SCT_nOU (16) /* Number of outputs */
+
+typedef struct
+{
+ __IO uint32_t CONFIG; /* 0x000 Configuration Register */
+ union {
+ __IO uint32_t CTRL_U; /* 0x004 Control Register */
+ struct {
+ __IO uint16_t CTRL_L; /* 0x004 low control register */
+ __IO uint16_t CTRL_H; /* 0x006 high control register */
+ };
+ };
+ __IO uint16_t LIMIT_L; /* 0x008 limit register for counter L */
+ __IO uint16_t LIMIT_H; /* 0x00A limit register for counter H */
+ __IO uint16_t HALT_L; /* 0x00C halt register for counter L */
+ __IO uint16_t HALT_H; /* 0x00E halt register for counter H */
+ __IO uint16_t STOP_L; /* 0x010 stop register for counter L */
+ __IO uint16_t STOP_H; /* 0x012 stop register for counter H */
+ __IO uint16_t START_L; /* 0x014 start register for counter L */
+ __IO uint16_t START_H; /* 0x016 start register for counter H */
+ uint32_t RESERVED1[10]; /* 0x018-0x03C reserved */
+ union {
+ __IO uint32_t COUNT_U; /* 0x040 counter register */
+ struct {
+ __IO uint16_t COUNT_L; /* 0x040 counter register for counter L */
+ __IO uint16_t COUNT_H; /* 0x042 counter register for counter H */
+ };
+ };
+ __IO uint16_t STATE_L; /* 0x044 state register for counter L */
+ __IO uint16_t STATE_H; /* 0x046 state register for counter H */
+ __I uint32_t INPUT; /* 0x048 input register */
+ __IO uint16_t REGMODE_L; /* 0x04C match - capture registers mode register L */
+ __IO uint16_t REGMODE_H; /* 0x04E match - capture registers mode register H */
+ __IO uint32_t OUTPUT; /* 0x050 output register */
+ __IO uint32_t OUTPUTDIRCTRL; /* 0x054 Output counter direction Control Register */
+ __IO uint32_t RES; /* 0x058 conflict resolution register */
+ __IO uint32_t DMA0REQUEST; /* 0x05C DMA0 Request Register */
+ __IO uint32_t DMA1REQUEST; /* 0x060 DMA1 Request Register */
+ uint32_t RESERVED2[35]; /* 0x064-0x0EC reserved */
+ __IO uint32_t EVEN; /* 0x0F0 event enable register */
+ __IO uint32_t EVFLAG; /* 0x0F4 event flag register */
+ __IO uint32_t CONEN; /* 0x0F8 conflict enable register */
+ __IO uint32_t CONFLAG; /* 0x0FC conflict flag register */
+
+ union {
+ __IO union { /* 0x100-... Match / Capture value */
+ uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTMATCH[i].L Access to L value */
+ uint16_t H; /* SCTMATCH[i].H Access to H value */
+ };
+ } MATCH[CONFIG_SCT_nRG];
+ __I union {
+ uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTCAP[i].L Access to H value */
+ uint16_t H; /* SCTCAP[i].H Access to H value */
+ };
+ } CAP[CONFIG_SCT_nRG];
+ };
+
+ uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */
+
+ union {
+ __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
+ __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
+ };
+ uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
+ union {
+ __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
+ __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
+ };
+ uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
+
+ union {
+ __IO union { /* 0x200-... Match Reload / Capture Control value */
+ uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTMATCHREL[i].L Access to L value */
+ uint16_t H; /* SCTMATCHREL[i].H Access to H value */
+ };
+ } MATCHREL[CONFIG_SCT_nRG];
+ __IO union {
+ uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTCAPCTRL[i].L Access to H value */
+ uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
+ };
+ } CAPCTRL[CONFIG_SCT_nRG];
+ };
+
+ uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */
+
+ union {
+ __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
+ __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
+ };
+ uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
+ union {
+ __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
+ __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
+ };
+ uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
+
+ __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
+ uint32_t STATE; /* Event State Register */
+ uint32_t CTRL; /* Event Control Register */
+ } EVENT[CONFIG_SCT_nEV];
+
+ uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
+
+ __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
+ uint32_t SET; /* Output n Set Register */
+ uint32_t CLR; /* Output n Clear Register */
+ } OUT[CONFIG_SCT_nOU];
+
+ uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
+
+ __I uint32_t MODULECONTENT; /* 0x7FC Module Content */
+
+} LPC_SCT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPDMA -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx General Purpose DMA (GPDMA) controller Modification date=1/19/2011 Major revision=0 Minor revision=7 (GPDMA)
+ */
+
+typedef struct { /*!< (@ 0x40002000) GPDMA Structure */
+ __I uint32_t INTSTAT; /*!< (@ 0x40002000) DMA Interrupt Status Register */
+ __I uint32_t INTTCSTAT; /*!< (@ 0x40002004) DMA Interrupt Terminal Count Request Status Register */
+ __O uint32_t INTTCCLEAR; /*!< (@ 0x40002008) DMA Interrupt Terminal Count Request Clear Register */
+ __I uint32_t INTERRSTAT; /*!< (@ 0x4000200C) DMA Interrupt Error Status Register */
+ __O uint32_t INTERRCLR; /*!< (@ 0x40002010) DMA Interrupt Error Clear Register */
+ __I uint32_t RAWINTTCSTAT; /*!< (@ 0x40002014) DMA Raw Interrupt Terminal Count Status Register */
+ __I uint32_t RAWINTERRSTAT; /*!< (@ 0x40002018) DMA Raw Error Interrupt Status Register */
+ __I uint32_t ENBLDCHNS; /*!< (@ 0x4000201C) DMA Enabled Channel Register */
+ __IO uint32_t SOFTBREQ; /*!< (@ 0x40002020) DMA Software Burst Request Register */
+ __IO uint32_t SOFTSREQ; /*!< (@ 0x40002024) DMA Software Single Request Register */
+ __IO uint32_t SOFTLBREQ; /*!< (@ 0x40002028) DMA Software Last Burst Request Register */
+ __IO uint32_t SOFTLSREQ; /*!< (@ 0x4000202C) DMA Software Last Single Request Register */
+ __IO uint32_t CONFIG; /*!< (@ 0x40002030) DMA Configuration Register */
+ __IO uint32_t SYNC; /*!< (@ 0x40002034) DMA Synchronization Register */
+ __I uint32_t RESERVED0[50];
+ __IO uint32_t C0SRCADDR; /*!< (@ 0x40002100) DMA Channel Source Address Register */
+ __IO uint32_t C0DESTADDR; /*!< (@ 0x40002104) DMA Channel Destination Address Register */
+ __IO uint32_t C0LLI; /*!< (@ 0x40002108) DMA Channel Linked List Item Register */
+ __IO uint32_t C0CONTROL; /*!< (@ 0x4000210C) DMA Channel Control Register */
+ __IO uint32_t C0CONFIG; /*!< (@ 0x40002110) DMA Channel Configuration Register */
+ __I uint32_t RESERVED1[3];
+ __IO uint32_t C1SRCADDR; /*!< (@ 0x40002120) DMA Channel Source Address Register */
+ __IO uint32_t C1DESTADDR; /*!< (@ 0x40002124) DMA Channel Destination Address Register */
+ __IO uint32_t C1LLI; /*!< (@ 0x40002128) DMA Channel Linked List Item Register */
+ __IO uint32_t C1CONTROL; /*!< (@ 0x4000212C) DMA Channel Control Register */
+ __IO uint32_t C1CONFIG; /*!< (@ 0x40002130) DMA Channel Configuration Register */
+ __I uint32_t RESERVED2[3];
+ __IO uint32_t C2SRCADDR; /*!< (@ 0x40002140) DMA Channel Source Address Register */
+ __IO uint32_t C2DESTADDR; /*!< (@ 0x40002144) DMA Channel Destination Address Register */
+ __IO uint32_t C2LLI; /*!< (@ 0x40002148) DMA Channel Linked List Item Register */
+ __IO uint32_t C2CONTROL; /*!< (@ 0x4000214C) DMA Channel Control Register */
+ __IO uint32_t C2CONFIG; /*!< (@ 0x40002150) DMA Channel Configuration Register */
+ __I uint32_t RESERVED3[3];
+ __IO uint32_t C3SRCADDR; /*!< (@ 0x40002160) DMA Channel Source Address Register */
+ __IO uint32_t C3DESTADDR; /*!< (@ 0x40002164) DMA Channel Destination Address Register */
+ __IO uint32_t C3LLI; /*!< (@ 0x40002168) DMA Channel Linked List Item Register */
+ __IO uint32_t C3CONTROL; /*!< (@ 0x4000216C) DMA Channel Control Register */
+ __IO uint32_t C3CONFIG; /*!< (@ 0x40002170) DMA Channel Configuration Register */
+ __I uint32_t RESERVED4[3];
+ __IO uint32_t C4SRCADDR; /*!< (@ 0x40002180) DMA Channel Source Address Register */
+ __IO uint32_t C4DESTADDR; /*!< (@ 0x40002184) DMA Channel Destination Address Register */
+ __IO uint32_t C4LLI; /*!< (@ 0x40002188) DMA Channel Linked List Item Register */
+ __IO uint32_t C4CONTROL; /*!< (@ 0x4000218C) DMA Channel Control Register */
+ __IO uint32_t C4CONFIG; /*!< (@ 0x40002190) DMA Channel Configuration Register */
+ __I uint32_t RESERVED5[3];
+ __IO uint32_t C5SRCADDR; /*!< (@ 0x400021A0) DMA Channel Source Address Register */
+ __IO uint32_t C5DESTADDR; /*!< (@ 0x400021A4) DMA Channel Destination Address Register */
+ __IO uint32_t C5LLI; /*!< (@ 0x400021A8) DMA Channel Linked List Item Register */
+ __IO uint32_t C5CONTROL; /*!< (@ 0x400021AC) DMA Channel Control Register */
+ __IO uint32_t C5CONFIG; /*!< (@ 0x400021B0) DMA Channel Configuration Register */
+ __I uint32_t RESERVED6[3];
+ __IO uint32_t C6SRCADDR; /*!< (@ 0x400021C0) DMA Channel Source Address Register */
+ __IO uint32_t C6DESTADDR; /*!< (@ 0x400021C4) DMA Channel Destination Address Register */
+ __IO uint32_t C6LLI; /*!< (@ 0x400021C8) DMA Channel Linked List Item Register */
+ __IO uint32_t C6CONTROL; /*!< (@ 0x400021CC) DMA Channel Control Register */
+ __IO uint32_t C6CONFIG; /*!< (@ 0x400021D0) DMA Channel Configuration Register */
+ __I uint32_t RESERVED7[3];
+ __IO uint32_t C7SRCADDR; /*!< (@ 0x400021E0) DMA Channel Source Address Register */
+ __IO uint32_t C7DESTADDR; /*!< (@ 0x400021E4) DMA Channel Destination Address Register */
+ __IO uint32_t C7LLI; /*!< (@ 0x400021E8) DMA Channel Linked List Item Register */
+ __IO uint32_t C7CONTROL; /*!< (@ 0x400021EC) DMA Channel Control Register */
+ __IO uint32_t C7CONFIG; /*!< (@ 0x400021F0) DMA Channel Configuration Register */
+} LPC_GPDMA_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SDMMC -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx SD/MMC Modification date=n/a Major revision=n/a Minor revision=n/a (SDMMC)
+ */
+
+typedef struct { /*!< (@ 0x40004000) SDMMC Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x40004000) Control Register */
+ __IO uint32_t PWREN; /*!< (@ 0x40004004) Power Enable Register */
+ __IO uint32_t CLKDIV; /*!< (@ 0x40004008) Clock Divider Register */
+ __IO uint32_t CLKSRC; /*!< (@ 0x4000400C) SD Clock Source Register */
+ __IO uint32_t CLKENA; /*!< (@ 0x40004010) Clock Enable Register */
+ __IO uint32_t TMOUT; /*!< (@ 0x40004014) Timeout Register */
+ __IO uint32_t CTYPE; /*!< (@ 0x40004018) Card Type Register */
+ __IO uint32_t BLKSIZ; /*!< (@ 0x4000401C) Block Size Register */
+ __IO uint32_t BYTCNT; /*!< (@ 0x40004020) Byte Count Register */
+ __IO uint32_t INTMASK; /*!< (@ 0x40004024) Interrupt Mask Register */
+ __IO uint32_t CMDARG; /*!< (@ 0x40004028) Command Argument Register */
+ __IO uint32_t CMD; /*!< (@ 0x4000402C) Command Register */
+ __I uint32_t RESP0; /*!< (@ 0x40004030) Response Register 0 */
+ __I uint32_t RESP1; /*!< (@ 0x40004034) Response Register 1 */
+ __I uint32_t RESP2; /*!< (@ 0x40004038) Response Register 2 */
+ __I uint32_t RESP3; /*!< (@ 0x4000403C) Response Register 3 */
+ __I uint32_t MINTSTS; /*!< (@ 0x40004040) Masked Interrupt Status Register */
+ __IO uint32_t RINTSTS; /*!< (@ 0x40004044) Raw Interrupt Status Register */
+ __I uint32_t STATUS; /*!< (@ 0x40004048) Status Register */
+ __IO uint32_t FIFOTH; /*!< (@ 0x4000404C) FIFO Threshold Watermark Register */
+ __I uint32_t CDETECT; /*!< (@ 0x40004050) Card Detect Register */
+ __I uint32_t WRTPRT; /*!< (@ 0x40004054) Write Protect Register */
+ __IO uint32_t GPIO; /*!< (@ 0x40004058) General Purpose Input/Output Register */
+ __I uint32_t TCBCNT; /*!< (@ 0x4000405C) Transferred CIU Card Byte Count Register */
+ __I uint32_t TBBCNT; /*!< (@ 0x40004060) Transferred Host to BIU-FIFO Byte Count Register */
+ __IO uint32_t DEBNCE; /*!< (@ 0x40004064) Debounce Count Register */
+ __IO uint32_t USRID; /*!< (@ 0x40004068) User ID Register */
+ __I uint32_t VERID; /*!< (@ 0x4000406C) Version ID Register */
+ __I uint32_t RESERVED0;
+ __IO uint32_t UHS_REG; /*!< (@ 0x40004074) UHS-1 Register */
+ __IO uint32_t RST_N; /*!< (@ 0x40004078) Hardware Reset */
+ __I uint32_t RESERVED1;
+ __IO uint32_t BMOD; /*!< (@ 0x40004080) Bus Mode Register */
+ __O uint32_t PLDMND; /*!< (@ 0x40004084) Poll Demand Register */
+ __IO uint32_t DBADDR; /*!< (@ 0x40004088) Descriptor List Base Address Register */
+ __IO uint32_t IDSTS; /*!< (@ 0x4000408C) Internal DMAC Status Register */
+ __IO uint32_t IDINTEN; /*!< (@ 0x40004090) Internal DMAC Interrupt Enable Register */
+ __I uint32_t DSCADDR; /*!< (@ 0x40004094) Current Host Descriptor Address Register */
+ __I uint32_t BUFADDR; /*!< (@ 0x40004098) Current Buffer Descriptor Address Register */
+} LPC_SDMMC_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- EMC -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx External Memory Controller (EMC) Modification date=1/19/2011 Major revision=0 Minor revision=7 (EMC)
+ */
+
+typedef struct { /*!< (@ 0x40005000) EMC Structure */
+ __IO uint32_t CONTROL; /*!< (@ 0x40005000) Controls operation of the memory controller. */
+ __I uint32_t STATUS; /*!< (@ 0x40005004) Provides EMC status information. */
+ __IO uint32_t CONFIG; /*!< (@ 0x40005008) Configures operation of the memory controller. */
+ __I uint32_t RESERVED0[5];
+ __IO uint32_t DYNAMICCONTROL; /*!< (@ 0x40005020) Controls dynamic memory operation. */
+ __IO uint32_t DYNAMICREFRESH; /*!< (@ 0x40005024) Configures dynamic memory refresh operation. */
+ __IO uint32_t DYNAMICREADCONFIG; /*!< (@ 0x40005028) Configures the dynamic memory read strategy. */
+ __I uint32_t RESERVED1;
+ __IO uint32_t DYNAMICRP; /*!< (@ 0x40005030) Selects the precharge command period. */
+ __IO uint32_t DYNAMICRAS; /*!< (@ 0x40005034) Selects the active to precharge command period. */
+ __IO uint32_t DYNAMICSREX; /*!< (@ 0x40005038) Selects the self-refresh exit time. */
+ __IO uint32_t DYNAMICAPR; /*!< (@ 0x4000503C) Selects the last-data-out to active command time. */
+ __IO uint32_t DYNAMICDAL; /*!< (@ 0x40005040) Selects the data-in to active command time. */
+ __IO uint32_t DYNAMICWR; /*!< (@ 0x40005044) Selects the write recovery time. */
+ __IO uint32_t DYNAMICRC; /*!< (@ 0x40005048) Selects the active to active command period. */
+ __IO uint32_t DYNAMICRFC; /*!< (@ 0x4000504C) Selects the auto-refresh period. */
+ __IO uint32_t DYNAMICXSR; /*!< (@ 0x40005050) Selects the exit self-refresh to active command time. */
+ __IO uint32_t DYNAMICRRD; /*!< (@ 0x40005054) Selects the active bank A to active bank B latency. */
+ __IO uint32_t DYNAMICMRD; /*!< (@ 0x40005058) Selects the load mode register to active command time. */
+ __I uint32_t RESERVED2[9];
+ __IO uint32_t STATICEXTENDEDWAIT; /*!< (@ 0x40005080) Selects time for long static memory read and write transfers. */
+ __I uint32_t RESERVED3[31];
+ __IO uint32_t DYNAMICCONFIG0; /*!< (@ 0x40005100) Selects the configuration information for dynamic memory chip select n. */
+ __IO uint32_t DYNAMICRASCAS0; /*!< (@ 0x40005104) Selects the RAS and CAS latencies for dynamic memory chip select n. */
+ __I uint32_t RESERVED4[6];
+ __IO uint32_t DYNAMICCONFIG1; /*!< (@ 0x40005120) Selects the configuration information for dynamic memory chip select n. */
+ __IO uint32_t DYNAMICRASCAS1; /*!< (@ 0x40005124) Selects the RAS and CAS latencies for dynamic memory chip select n. */
+ __I uint32_t RESERVED5[6];
+ __IO uint32_t DYNAMICCONFIG2; /*!< (@ 0x40005140) Selects the configuration information for dynamic memory chip select n. */
+ __IO uint32_t DYNAMICRASCAS2; /*!< (@ 0x40005144) Selects the RAS and CAS latencies for dynamic memory chip select n. */
+ __I uint32_t RESERVED6[6];
+ __IO uint32_t DYNAMICCONFIG3; /*!< (@ 0x40005160) Selects the configuration information for dynamic memory chip select n. */
+ __IO uint32_t DYNAMICRASCAS3; /*!< (@ 0x40005164) Selects the RAS and CAS latencies for dynamic memory chip select n. */
+ __I uint32_t RESERVED7[38];
+ __IO uint32_t STATICCONFIG0; /*!< (@ 0x40005200) Selects the memory configuration for static chip select n. */
+ __IO uint32_t STATICWAITWEN0; /*!< (@ 0x40005204) Selects the delay from chip select n to write enable. */
+ __IO uint32_t STATICWAITOEN0; /*!< (@ 0x40005208) Selects the delay from chip select n or address change, whichever is later, to output enable. */
+ __IO uint32_t STATICWAITRD0; /*!< (@ 0x4000520C) Selects the delay from chip select n to a read access. */
+ __IO uint32_t STATICWAITPAG0; /*!< (@ 0x40005210) Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+ __IO uint32_t STATICWAITWR0; /*!< (@ 0x40005214) Selects the delay from chip select n to a write access. */
+ __IO uint32_t STATICWAITTURN0; /*!< (@ 0x40005218) Selects bus turnaround cycles */
+ __I uint32_t RESERVED8;
+ __IO uint32_t STATICCONFIG1; /*!< (@ 0x40005220) Selects the memory configuration for static chip select n. */
+ __IO uint32_t STATICWAITWEN1; /*!< (@ 0x40005224) Selects the delay from chip select n to write enable. */
+ __IO uint32_t STATICWAITOEN1; /*!< (@ 0x40005228) Selects the delay from chip select n or address change, whichever is later, to output enable. */
+ __IO uint32_t STATICWAITRD1; /*!< (@ 0x4000522C) Selects the delay from chip select n to a read access. */
+ __IO uint32_t STATICWAITPAG1; /*!< (@ 0x40005230) Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+ __IO uint32_t STATICWAITWR1; /*!< (@ 0x40005234) Selects the delay from chip select n to a write access. */
+ __IO uint32_t STATICWAITTURN1; /*!< (@ 0x40005238) Selects bus turnaround cycles */
+ __I uint32_t RESERVED9;
+ __IO uint32_t STATICCONFIG2; /*!< (@ 0x40005240) Selects the memory configuration for static chip select n. */
+ __IO uint32_t STATICWAITWEN2; /*!< (@ 0x40005244) Selects the delay from chip select n to write enable. */
+ __IO uint32_t STATICWAITOEN2; /*!< (@ 0x40005248) Selects the delay from chip select n or address change, whichever is later, to output enable. */
+ __IO uint32_t STATICWAITRD2; /*!< (@ 0x4000524C) Selects the delay from chip select n to a read access. */
+ __IO uint32_t STATICWAITPAG2; /*!< (@ 0x40005250) Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+ __IO uint32_t STATICWAITWR2; /*!< (@ 0x40005254) Selects the delay from chip select n to a write access. */
+ __IO uint32_t STATICWAITTURN2; /*!< (@ 0x40005258) Selects bus turnaround cycles */
+ __I uint32_t RESERVED10;
+ __IO uint32_t STATICCONFIG3; /*!< (@ 0x40005260) Selects the memory configuration for static chip select n. */
+ __IO uint32_t STATICWAITWEN3; /*!< (@ 0x40005264) Selects the delay from chip select n to write enable. */
+ __IO uint32_t STATICWAITOEN3; /*!< (@ 0x40005268) Selects the delay from chip select n or address change, whichever is later, to output enable. */
+ __IO uint32_t STATICWAITRD3; /*!< (@ 0x4000526C) Selects the delay from chip select n to a read access. */
+ __IO uint32_t STATICWAITPAG3; /*!< (@ 0x40005270) Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+ __IO uint32_t STATICWAITWR3; /*!< (@ 0x40005274) Selects the delay from chip select n to a write access. */
+ __IO uint32_t STATICWAITTURN3; /*!< (@ 0x40005278) Selects bus turnaround cycles */
+} LPC_EMC_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USB0 -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx USB0 Host/Device/OTG controller Modification date=1/19/2011 Major revision=0 Minor revision=7 (USB0)
+ */
+
+typedef struct { /*!< (@ 0x40006000) USB0 Structure */
+ __I uint32_t RESERVED0[64];
+ __I uint32_t CAPLENGTH; /*!< (@ 0x40006100) Capability register length */
+ __I uint32_t HCSPARAMS; /*!< (@ 0x40006104) Host controller structural parameters */
+ __I uint32_t HCCPARAMS; /*!< (@ 0x40006108) Host controller capability parameters */
+ __I uint32_t RESERVED1[5];
+ __I uint32_t DCIVERSION; /*!< (@ 0x40006120) Device interface version number */
+ __I uint32_t RESERVED2[7];
+
+ union {
+ __IO uint32_t USBCMD_H; /*!< (@ 0x40006140) USB command (host mode) */
+ __IO uint32_t USBCMD_D; /*!< (@ 0x40006140) USB command (device mode) */
+ } ;
+
+ union {
+ __IO uint32_t USBSTS_H; /*!< (@ 0x40006144) USB status (host mode) */
+ __IO uint32_t USBSTS_D; /*!< (@ 0x40006144) USB status (device mode) */
+ } ;
+
+ union {
+ __IO uint32_t USBINTR_H; /*!< (@ 0x40006148) USB interrupt enable (host mode) */
+ __IO uint32_t USBINTR_D; /*!< (@ 0x40006148) USB interrupt enable (device mode) */
+ } ;
+
+ union {
+ __IO uint32_t FRINDEX_H; /*!< (@ 0x4000614C) USB frame index (host mode) */
+ __IO uint32_t FRINDEX_D; /*!< (@ 0x4000614C) USB frame index (device mode) */
+ } ;
+ __I uint32_t RESERVED3;
+
+ union {
+ __IO uint32_t PERIODICLISTBASE; /*!< (@ 0x40006154) Frame list base address (host mode) */
+ __IO uint32_t DEVICEADDR; /*!< (@ 0x40006154) USB device address (device mode) */
+ } ;
+
+ union {
+ __IO uint32_t ASYNCLISTADDR; /*!< (@ 0x40006158) Address of endpoint list in memory */
+ __IO uint32_t ENDPOINTLISTADDR; /*!< (@ 0x40006158) Address of endpoint list in memory */
+ } ;
+ __IO uint32_t TTCTRL; /*!< (@ 0x4000615C) Asynchronous buffer status for embedded TT (host mode) */
+ __IO uint32_t BURSTSIZE; /*!< (@ 0x40006160) Programmable burst size */
+ __IO uint32_t TXFILLTUNING; /*!< (@ 0x40006164) Host transmit pre-buffer packet tuning (host mode) */
+ __I uint32_t RESERVED4[3];
+ __IO uint32_t BINTERVAL; /*!< (@ 0x40006174) Length of virtual frame */
+ __IO uint32_t ENDPTNAK; /*!< (@ 0x40006178) Endpoint NAK (device mode) */
+ __IO uint32_t ENDPTNAKEN; /*!< (@ 0x4000617C) Endpoint NAK Enable (device mode) */
+ __I uint32_t RESERVED5;
+
+ union {
+ __IO uint32_t PORTSC1_H; /*!< (@ 0x40006184) Port 1 status/control (host mode) */
+ __IO uint32_t PORTSC1_D; /*!< (@ 0x40006184) Port 1 status/control (device mode) */
+ } ;
+ __I uint32_t RESERVED6[7];
+ __IO uint32_t OTGSC; /*!< (@ 0x400061A4) OTG status and control */
+
+ union {
+ __IO uint32_t USBMODE_H; /*!< (@ 0x400061A8) USB mode (host mode) */
+ __IO uint32_t USBMODE_D; /*!< (@ 0x400061A8) USB device mode (device mode) */
+ } ;
+ __IO uint32_t ENDPTSETUPSTAT; /*!< (@ 0x400061AC) Endpoint setup status */
+ __IO uint32_t ENDPTPRIME; /*!< (@ 0x400061B0) Endpoint initialization */
+ __IO uint32_t ENDPTFLUSH; /*!< (@ 0x400061B4) Endpoint de-initialization */
+ __I uint32_t ENDPTSTAT; /*!< (@ 0x400061B8) Endpoint status */
+ __IO uint32_t ENDPTCOMPLETE; /*!< (@ 0x400061BC) Endpoint complete */
+ __IO uint32_t ENDPTCTRL0; /*!< (@ 0x400061C0) Endpoint control 0 */
+ __IO uint32_t ENDPTCTRL1; /*!< (@ 0x400061C4) Endpoint control */
+ __IO uint32_t ENDPTCTRL2; /*!< (@ 0x400061C8) Endpoint control */
+ __IO uint32_t ENDPTCTRL3; /*!< (@ 0x400061CC) Endpoint control */
+ __IO uint32_t ENDPTCTRL4; /*!< (@ 0x400061D0) Endpoint control */
+ __IO uint32_t ENDPTCTRL5; /*!< (@ 0x400061D4) Endpoint control */
+} LPC_USB0_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USB1 -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx USB1 Host/Device controller Modification date=1/19/2011 Major revision=0 Minor revision=7 (USB1)
+ */
+
+typedef struct { /*!< (@ 0x40007000) USB1 Structure */
+ __I uint32_t RESERVED0[64];
+ __I uint32_t CAPLENGTH; /*!< (@ 0x40007100) Capability register length */
+ __I uint32_t HCSPARAMS; /*!< (@ 0x40007104) Host controller structural parameters */
+ __I uint32_t HCCPARAMS; /*!< (@ 0x40007108) Host controller capability parameters */
+ __I uint32_t RESERVED1[5];
+ __I uint32_t DCIVERSION; /*!< (@ 0x40007120) Device interface version number */
+ __I uint32_t RESERVED2[7];
+
+ union {
+ __IO uint32_t USBCMD_H; /*!< (@ 0x40007140) USB command (host mode) */
+ __IO uint32_t USBCMD_D; /*!< (@ 0x40007140) USB command (device mode) */
+ } ;
+
+ union {
+ __IO uint32_t USBSTS_H; /*!< (@ 0x40007144) USB status (host mode) */
+ __IO uint32_t USBSTS_D; /*!< (@ 0x40007144) USB status (device mode) */
+ } ;
+
+ union {
+ __IO uint32_t USBINTR_H; /*!< (@ 0x40007148) USB interrupt enable (host mode) */
+ __IO uint32_t USBINTR_D; /*!< (@ 0x40007148) USB interrupt enable (device mode) */
+ } ;
+
+ union {
+ __IO uint32_t FRINDEX_H; /*!< (@ 0x4000714C) USB frame index (host mode) */
+ __I uint32_t FRINDEX_D; /*!< (@ 0x4000714C) USB frame index (device mode) */
+ } ;
+ __I uint32_t RESERVED3;
+
+ union {
+ __IO uint32_t PERIODICLISTBASE; /*!< (@ 0x40007154) Frame list base address */
+ __IO uint32_t DEVICEADDR; /*!< (@ 0x40007154) USB device address */
+ } ;
+
+ union {
+ __IO uint32_t ASYNCLISTADDR; /*!< (@ 0x40007158) Address of endpoint list in memory (host mode) */
+ __IO uint32_t ENDPOINTLISTADDR; /*!< (@ 0x40007158) Address of endpoint list in memory (device mode) */
+ } ;
+ __IO uint32_t TTCTRL; /*!< (@ 0x4000715C) Asynchronous buffer status for embedded TT (host mode) */
+ __IO uint32_t BURSTSIZE; /*!< (@ 0x40007160) Programmable burst size */
+ __IO uint32_t TXFILLTUNING; /*!< (@ 0x40007164) Host transmit pre-buffer packet tuning (host mode) */
+ __I uint32_t RESERVED4[2];
+ __IO uint32_t ULPIVIEWPORT; /*!< (@ 0x40007170) ULPI viewport */
+ __IO uint32_t BINTERVAL; /*!< (@ 0x40007174) Length of virtual frame */
+ __IO uint32_t ENDPTNAK; /*!< (@ 0x40007178) Endpoint NAK (device mode) */
+ __IO uint32_t ENDPTNAKEN; /*!< (@ 0x4000717C) Endpoint NAK Enable (device mode) */
+ __I uint32_t RESERVED5;
+
+ union {
+ __IO uint32_t PORTSC1_H; /*!< (@ 0x40007184) Port 1 status/control (host mode) */
+ __IO uint32_t PORTSC1_D; /*!< (@ 0x40007184) Port 1 status/control (device mode) */
+ } ;
+ __I uint32_t RESERVED6[8];
+
+ union {
+ __IO uint32_t USBMODE_H; /*!< (@ 0x400071A8) USB mode (host mode) */
+ __IO uint32_t USBMODE_D; /*!< (@ 0x400071A8) USB mode (device mode) */
+ } ;
+ __IO uint32_t ENDPTSETUPSTAT; /*!< (@ 0x400071AC) Endpoint setup status */
+ __IO uint32_t ENDPTPRIME; /*!< (@ 0x400071B0) Endpoint initialization */
+ __IO uint32_t ENDPTFLUSH; /*!< (@ 0x400071B4) Endpoint de-initialization */
+ __I uint32_t ENDPTSTAT; /*!< (@ 0x400071B8) Endpoint status */
+ __IO uint32_t ENDPTCOMPLETE; /*!< (@ 0x400071BC) Endpoint complete */
+ __IO uint32_t ENDPTCTRL0; /*!< (@ 0x400071C0) Endpoint control 0 */
+ __IO uint32_t ENDPTCTRL1; /*!< (@ 0x400071C4) Endpoint control */
+ __IO uint32_t ENDPTCTRL2; /*!< (@ 0x400071C8) Endpoint control */
+ __IO uint32_t ENDPTCTRL3; /*!< (@ 0x400071CC) Endpoint control */
+} LPC_USB1_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- LCD -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx LCD Modification date=1/19/2011 Major revision=0 Minor revision=7 (LCD)
+ */
+
+typedef struct { /*!< (@ 0x40008000) LCD Structure */
+ __IO uint32_t TIMH; /*!< (@ 0x40008000) Horizontal Timing Control register */
+ __IO uint32_t TIMV; /*!< (@ 0x40008004) Vertical Timing Control register */
+ __IO uint32_t POL; /*!< (@ 0x40008008) Clock and Signal Polarity Control register */
+ __IO uint32_t LE; /*!< (@ 0x4000800C) Line End Control register */
+ __IO uint32_t UPBASE; /*!< (@ 0x40008010) Upper Panel Frame Base Address register */
+ __IO uint32_t LPBASE; /*!< (@ 0x40008014) Lower Panel Frame Base Address register */
+ __IO uint32_t CTRL; /*!< (@ 0x40008018) LCD Control register */
+ __IO uint32_t INTMSK; /*!< (@ 0x4000801C) Interrupt Mask register */
+ __I uint32_t INTRAW; /*!< (@ 0x40008020) Raw Interrupt Status register */
+ __I uint32_t INTSTAT; /*!< (@ 0x40008024) Masked Interrupt Status register */
+ __O uint32_t INTCLR; /*!< (@ 0x40008028) Interrupt Clear register */
+ __I uint32_t UPCURR; /*!< (@ 0x4000802C) Upper Panel Current Address Value register */
+ __I uint32_t LPCURR; /*!< (@ 0x40008030) Lower Panel Current Address Value register */
+ __I uint32_t RESERVED0[115];
+ __IO uint32_t PAL[256]; /*!< (@ 0x40008200) 256x16-bit Color Palette registers */
+ __I uint32_t RESERVED1[128];
+ __IO uint32_t CRSR_IMG[256]; /*!< (@ 0x40008800) Cursor Image registers */
+ __IO uint32_t CRSR_CTRL; /*!< (@ 0x40008C00) Cursor Control register */
+ __IO uint32_t CRSR_CFG; /*!< (@ 0x40008C04) Cursor Configuration register */
+ __IO uint32_t CRSR_PAL0; /*!< (@ 0x40008C08) Cursor Palette register 0 */
+ __IO uint32_t CRSR_PAL1; /*!< (@ 0x40008C0C) Cursor Palette register 1 */
+ __IO uint32_t CRSR_XY; /*!< (@ 0x40008C10) Cursor XY Position register */
+ __IO uint32_t CRSR_CLIP; /*!< (@ 0x40008C14) Cursor Clip Position register */
+ __I uint32_t RESERVED2[2];
+ __IO uint32_t CRSR_INTMSK; /*!< (@ 0x40008C20) Cursor Interrupt Mask register */
+ __O uint32_t CRSR_INTCLR; /*!< (@ 0x40008C24) Cursor Interrupt Clear register */
+ __I uint32_t CRSR_INTRAW; /*!< (@ 0x40008C28) Cursor Raw Interrupt Status register */
+ __I uint32_t CRSR_INTSTAT; /*!< (@ 0x40008C2C) Cursor Masked Interrupt Status register */
+} LPC_LCD_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- ETHERNET -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx Ethernet Modification date=12/9/2011 Major revision=1.1 Minor revision=not available (ETHERNET)
+ */
+
+typedef struct { /*!< (@ 0x40010000) ETHERNET Structure */
+ __IO uint32_t MAC_CONFIG; /*!< (@ 0x40010000) MAC configuration register */
+ __IO uint32_t MAC_FRAME_FILTER; /*!< (@ 0x40010004) MAC frame filter */
+ __IO uint32_t MAC_HASHTABLE_HIGH; /*!< (@ 0x40010008) Hash table high register */
+ __IO uint32_t MAC_HASHTABLE_LOW; /*!< (@ 0x4001000C) Hash table low register */
+ __IO uint32_t MAC_MII_ADDR; /*!< (@ 0x40010010) MII address register */
+ __IO uint32_t MAC_MII_DATA; /*!< (@ 0x40010014) MII data register */
+ __IO uint32_t MAC_FLOW_CTRL; /*!< (@ 0x40010018) Flow control register */
+ __IO uint32_t MAC_VLAN_TAG; /*!< (@ 0x4001001C) VLAN tag register */
+ __I uint32_t RESERVED0;
+ __I uint32_t MAC_DEBUG; /*!< (@ 0x40010024) Debug register */
+ __IO uint32_t MAC_RWAKE_FRFLT; /*!< (@ 0x40010028) Remote wake-up frame filter */
+ __IO uint32_t MAC_PMT_CTRL_STAT; /*!< (@ 0x4001002C) PMT control and status */
+ __I uint32_t RESERVED1[2];
+ __I uint32_t MAC_INTR; /*!< (@ 0x40010038) Interrupt status register */
+ __IO uint32_t MAC_INTR_MASK; /*!< (@ 0x4001003C) Interrupt mask register */
+ __IO uint32_t MAC_ADDR0_HIGH; /*!< (@ 0x40010040) MAC address 0 high register */
+ __IO uint32_t MAC_ADDR0_LOW; /*!< (@ 0x40010044) MAC address 0 low register */
+ __I uint32_t RESERVED2[430];
+ __IO uint32_t MAC_TIMESTP_CTRL; /*!< (@ 0x40010700) Time stamp control register */
+ __IO uint32_t SUBSECOND_INCR; /*!< (@ 0x40010704) Sub-second increment register */
+ __I uint32_t SECONDS; /*!< (@ 0x40010708) System time seconds register */
+ __I uint32_t NANOSECONDS; /*!< (@ 0x4001070C) System time nanoseconds register */
+ __IO uint32_t SECONDSUPDATE; /*!< (@ 0x40010710) System time seconds update register */
+ __IO uint32_t NANOSECONDSUPDATE; /*!< (@ 0x40010714) System time nanoseconds update register */
+ __IO uint32_t ADDEND; /*!< (@ 0x40010718) Time stamp addend register */
+ __IO uint32_t TARGETSECONDS; /*!< (@ 0x4001071C) Target time seconds register */
+ __IO uint32_t TARGETNANOSECONDS; /*!< (@ 0x40010720) Target time nanoseconds register */
+ __IO uint32_t HIGHWORD; /*!< (@ 0x40010724) System time higher word seconds register */
+ __I uint32_t TIMESTAMPSTAT; /*!< (@ 0x40010728) Time stamp status register */
+ __IO uint32_t PPSCTRL; /*!< (@ 0x4001072C) PPS control register */
+ __I uint32_t AUXNANOSECONDS; /*!< (@ 0x40010730) Auxiliary time stamp nanoseconds register */
+ __I uint32_t AUXSECONDS; /*!< (@ 0x40010734) Auxiliary time stamp seconds register */
+ __I uint32_t RESERVED3[562];
+ __IO uint32_t DMA_BUS_MODE; /*!< (@ 0x40011000) Bus Mode Register */
+ __IO uint32_t DMA_TRANS_POLL_DEMAND; /*!< (@ 0x40011004) Transmit poll demand register */
+ __IO uint32_t DMA_REC_POLL_DEMAND; /*!< (@ 0x40011008) Receive poll demand register */
+ __IO uint32_t DMA_REC_DES_ADDR; /*!< (@ 0x4001100C) Receive descriptor list address register */
+ __IO uint32_t DMA_TRANS_DES_ADDR; /*!< (@ 0x40011010) Transmit descriptor list address register */
+ __IO uint32_t DMA_STAT; /*!< (@ 0x40011014) Status register */
+ __IO uint32_t DMA_OP_MODE; /*!< (@ 0x40011018) Operation mode register */
+ __IO uint32_t DMA_INT_EN; /*!< (@ 0x4001101C) Interrupt enable register */
+ __I uint32_t DMA_MFRM_BUFOF; /*!< (@ 0x40011020) Missed frame and buffer overflow register */
+ __IO uint32_t DMA_REC_INT_WDT; /*!< (@ 0x40011024) Receive interrupt watchdog timer register */
+ __I uint32_t RESERVED4[8];
+ __I uint32_t DMA_CURHOST_TRANS_DES; /*!< (@ 0x40011048) Current host transmit descriptor register */
+ __I uint32_t DMA_CURHOST_REC_DES; /*!< (@ 0x4001104C) Current host receive descriptor register */
+ __I uint32_t DMA_CURHOST_TRANS_BUF; /*!< (@ 0x40011050) Current host transmit buffer address register */
+ __I uint32_t DMA_CURHOST_REC_BUF; /*!< (@ 0x40011054) Current host receive buffer address register */
+} LPC_ETHERNET_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- ATIMER -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx Alarm timer Modification date=1/7/2011 Major revision=0 Minor revision=6 (ATIMER)
+ */
+
+typedef struct { /*!< (@ 0x40040000) ATIMER Structure */
+ __IO uint32_t DOWNCOUNTER; /*!< (@ 0x40040000) Downcounter register */
+ __IO uint32_t PRESET; /*!< (@ 0x40040004) Preset value register */
+ __I uint32_t RESERVED0[1012];
+ __O uint32_t CLR_EN; /*!< (@ 0x40040FD8) Interrupt clear enable register */
+ __O uint32_t SET_EN; /*!< (@ 0x40040FDC) Interrupt set enable register */
+ __I uint32_t STATUS; /*!< (@ 0x40040FE0) Status register */
+ __I uint32_t ENABLE; /*!< (@ 0x40040FE4) Enable register */
+ __O uint32_t CLR_STAT; /*!< (@ 0x40040FE8) Clear register */
+ __O uint32_t SET_STAT; /*!< (@ 0x40040FEC) Set register */
+} LPC_ATIMER_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- REGFILE -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx rtc/REGFILE date=1/20/2011 Major revision=0 Minor revision=7 (REGFILE)
+ */
+
+typedef struct { /*!< (@ 0x40041000) REGFILE Structure */
+ __IO uint32_t REGFILE[64]; /*!< (@ 0x40041000) General purpose storage register */
+} LPC_REGFILE_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- PMC -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx Power Management Controller (PMC) Modification date=1/20/2011 Major revision=0 Minor revision=7 (PMC)
+ */
+
+typedef struct { /*!< (@ 0x40042000) PMC Structure */
+ __IO uint32_t PD0_SLEEP0_HW_ENA; /*!< (@ 0x40042000) Hardware sleep event enable register */
+ __I uint32_t RESERVED0[6];
+ __IO uint32_t PD0_SLEEP0_MODE; /*!< (@ 0x4004201C) Sleep power mode register */
+} LPC_PMC_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- CREG -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10503 Chapter title=LPC43xx Configuration Registers (CREG) Modification date=10/7/2011 Major revision=0 Minor revision=3 (CREG)
+ */
+
+typedef struct { /*!< (@ 0x40043000) CREG Structure */
+ __I uint32_t IRCTRM; /*!< (@ 0x40043000) IRC trim register */
+ __IO uint32_t CREG0; /*!< (@ 0x40043004) Chip configuration register 32 kHz oscillator output and BOD control register. */
+ __I uint32_t RESERVED1[62];
+ __IO uint32_t M4MEMMAP; /*!< (@ 0x40043100) ARM Cortex-M4 memory mapping */
+ __I uint32_t RESERVED2[5];
+ __IO uint32_t CREG5; /*!< (@ 0x40043118) Chip configuration register 5. Controls JTAG access. */
+ __IO uint32_t DMAMUX; /*!< (@ 0x4004311C) DMA muxing control */
+ __I uint32_t RESERVED3[2];
+ __IO uint32_t ETBCFG; /*!< (@ 0x40043128) ETB RAM configuration */
+ __IO uint32_t CREG6; /*!< (@ 0x4004312C) Chip configuration register 6. */
+ __IO uint32_t M4TXEVENT; /*!< (@ 0x40043130) Cortex-M4 TXEV event clear */
+ __I uint32_t RESERVED4[51];
+ __I uint32_t CHIPID; /*!< (@ 0x40043200) Part ID */
+ __I uint32_t RESERVED5[127];
+ __IO uint32_t M0TXEVENT; /*!< (@ 0x40043400) Cortex-M0 TXEV event clear */
+ __IO uint32_t M0APPMEMMAP; /*!< (@ 0x40043404) ARM Cortex-M0 memory mapping */
+} LPC_CREG_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- EVENTROUTER -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10503 Chapter title=LPC43xx Event router Modification date=10/7/2011 Major revision=0 Minor revision=3 (EVENTROUTER)
+ */
+
+typedef struct { /*!< (@ 0x40044000) EVENTROUTER Structure */
+ __IO uint32_t HILO; /*!< (@ 0x40044000) Level configuration register */
+ __IO uint32_t EDGE; /*!< (@ 0x40044004) Edge configuration */
+ __I uint32_t RESERVED0[1012];
+ __O uint32_t CLR_EN; /*!< (@ 0x40044FD8) Clear event enable register */
+ __O uint32_t SET_EN; /*!< (@ 0x40044FDC) Set event enable register */
+ __I uint32_t STATUS; /*!< (@ 0x40044FE0) Event Status register */
+ __I uint32_t ENABLE; /*!< (@ 0x40044FE4) Event Enable register */
+ __O uint32_t CLR_STAT; /*!< (@ 0x40044FE8) Clear event status register */
+ __O uint32_t SET_STAT; /*!< (@ 0x40044FEC) Set event status register */
+} LPC_EVENTROUTER_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- RTC -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx Real-Time Clock (RTC) Modification date=1/20/2011 Major revision=0 Minor revision=7 (RTC)
+ */
+
+typedef struct { /*!< (@ 0x40046000) RTC Structure */
+ __O uint32_t ILR; /*!< (@ 0x40046000) Interrupt Location Register */
+ __I uint32_t RESERVED0;
+ __IO uint32_t CCR; /*!< (@ 0x40046008) Clock Control Register */
+ __IO uint32_t CIIR; /*!< (@ 0x4004600C) Counter Increment Interrupt Register */
+ __IO uint32_t AMR; /*!< (@ 0x40046010) Alarm Mask Register */
+ __I uint32_t CTIME0; /*!< (@ 0x40046014) Consolidated Time Register 0 */
+ __I uint32_t CTIME1; /*!< (@ 0x40046018) Consolidated Time Register 1 */
+ __I uint32_t CTIME2; /*!< (@ 0x4004601C) Consolidated Time Register 2 */
+ __IO uint32_t SEC; /*!< (@ 0x40046020) Seconds Register */
+ __IO uint32_t MIN; /*!< (@ 0x40046024) Minutes Register */
+ __IO uint32_t HRS; /*!< (@ 0x40046028) Hours Register */
+ __IO uint32_t DOM; /*!< (@ 0x4004602C) Day of Month Register */
+ __IO uint32_t DOW; /*!< (@ 0x40046030) Day of Week Register */
+ __IO uint32_t DOY; /*!< (@ 0x40046034) Day of Year Register */
+ __IO uint32_t MONTH; /*!< (@ 0x40046038) Months Register */
+ __IO uint32_t YEAR; /*!< (@ 0x4004603C) Years Register */
+ __IO uint32_t CALIBRATION; /*!< (@ 0x40046040) Calibration Value Register */
+ __I uint32_t RESERVED1[7];
+ __IO uint32_t ASEC; /*!< (@ 0x40046060) Alarm value for Seconds */
+ __IO uint32_t AMIN; /*!< (@ 0x40046064) Alarm value for Minutes */
+ __IO uint32_t AHRS; /*!< (@ 0x40046068) Alarm value for Hours */
+ __IO uint32_t ADOM; /*!< (@ 0x4004606C) Alarm value for Day of Month */
+ __IO uint32_t ADOW; /*!< (@ 0x40046070) Alarm value for Day of Week */
+ __IO uint32_t ADOY; /*!< (@ 0x40046074) Alarm value for Day of Year */
+ __IO uint32_t AMON; /*!< (@ 0x40046078) Alarm value for Months */
+ __IO uint32_t AYRS; /*!< (@ 0x4004607C) Alarm value for Year */
+} LPC_RTC_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- CGU -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC18xx Clock Generation Unit (CGU) Modification date=6/1/2011 Major revision=0 Minor revision=1 (CGU)
+ */
+
+typedef struct { /*!< (@ 0x40050000) CGU Structure */
+ __I uint32_t RESERVED0[5];
+ __IO uint32_t FREQ_MON; /*!< (@ 0x40050014) Frequency monitor register */
+ __IO uint32_t XTAL_OSC_CTRL; /*!< (@ 0x40050018) Crystal oscillator control register */
+ __I uint32_t PLL0USB_STAT; /*!< (@ 0x4005001C) PLL0 (USB) status register */
+ __IO uint32_t PLL0USB_CTRL; /*!< (@ 0x40050020) PLL0 (USB) control register */
+ __IO uint32_t PLL0USB_MDIV; /*!< (@ 0x40050024) PLL0 (USB) M-divider register */
+ __IO uint32_t PLL0USB_NP_DIV; /*!< (@ 0x40050028) PLL0 (USB) N/P-divider register */
+ __I uint32_t PLL0AUDIO_STAT; /*!< (@ 0x4005002C) PLL0 (audio) status register */
+ __IO uint32_t PLL0AUDIO_CTRL; /*!< (@ 0x40050030) PLL0 (audio) control register */
+ __IO uint32_t PLL0AUDIO_MDIV; /*!< (@ 0x40050034) PLL0 (audio) M-divider register */
+ __IO uint32_t PLL0AUDIO_NP_DIV; /*!< (@ 0x40050038) PLL0 (audio) N/P-divider register */
+ __IO uint32_t PLL0AUDIO_FRAC; /*!< (@ 0x4005003C) PLL0 (audio) */
+ __I uint32_t PLL1_STAT; /*!< (@ 0x40050040) PLL1 status register */
+ __IO uint32_t PLL1_CTRL; /*!< (@ 0x40050044) PLL1 control register */
+ __IO uint32_t IDIVA_CTRL; /*!< (@ 0x40050048) Integer divider A control register */
+ __IO uint32_t IDIVB_CTRL; /*!< (@ 0x4005004C) Integer divider B control register */
+ __IO uint32_t IDIVC_CTRL; /*!< (@ 0x40050050) Integer divider C control register */
+ __IO uint32_t IDIVD_CTRL; /*!< (@ 0x40050054) Integer divider D control register */
+ __IO uint32_t IDIVE_CTRL; /*!< (@ 0x40050058) Integer divider E control register */
+ __IO uint32_t BASE_SAFE_CLK; /*!< (@ 0x4005005C) Output stage 0 control register for base clock BASE_SAFE_CLK */
+ __IO uint32_t BASE_USB0_CLK; /*!< (@ 0x40050060) Output stage 1 control register for base clock BASE_USB0_CLK */
+ __IO uint32_t BASE_PERIPH_CLK; /*!< (@ 0x40050064) Output stage 2 control register for base clock BASE_PERIPH_CLK */
+ __IO uint32_t BASE_USB1_CLK; /*!< (@ 0x40050068) Output stage 3 control register for base clock BASE_USB1_CLK */
+ __IO uint32_t BASE_M4_CLK; /*!< (@ 0x4005006C) Output stage BASE_M4_CLK control register */
+ __IO uint32_t BASE_SPIFI_CLK; /*!< (@ 0x40050070) Output stage BASE_SPIFI_CLK control register */
+ __IO uint32_t BASE_SPI_CLK; /*!< (@ 0x40050074) Output stage BASE_SPI_CLK control register */
+ __IO uint32_t BASE_PHY_RX_CLK; /*!< (@ 0x40050078) Output stage BASE_PHY_RX_CLK control register */
+ __IO uint32_t BASE_PHY_TX_CLK; /*!< (@ 0x4005007C) Output stage BASE_PHY_TX_CLK control register */
+ __IO uint32_t BASE_APB1_CLK; /*!< (@ 0x40050080) Output stage BASE_APB1_CLK control register */
+ __IO uint32_t BASE_APB3_CLK; /*!< (@ 0x40050084) Output stage BASE_APB3_CLK control register */
+ __IO uint32_t BASE_LCD_CLK; /*!< (@ 0x40050088) Output stage BASE_LCD_CLK control register */
+ __IO uint32_t BASE_VADC_CLK; /*!< (@ 0x4005008C) Output stage BASE_VADC_CLK control register */
+ __IO uint32_t BASE_SDIO_CLK; /*!< (@ 0x40050090) Output stage BASE_SDIO_CLK control register */
+ __IO uint32_t BASE_SSP0_CLK; /*!< (@ 0x40050094) Output stage BASE_SSP0_CLK control register */
+ __IO uint32_t BASE_SSP1_CLK; /*!< (@ 0x40050098) Output stage BASE_SSP1_CLK control register */
+ __IO uint32_t BASE_UART0_CLK; /*!< (@ 0x4005009C) Output stage BASE_UART0_CLK control register */
+ __IO uint32_t BASE_UART1_CLK; /*!< (@ 0x400500A0) Output stage BASE_UART1_CLK control register */
+ __IO uint32_t BASE_UART2_CLK; /*!< (@ 0x400500A4) Output stage BASE_UART2_CLK control register */
+ __IO uint32_t BASE_UART3_CLK; /*!< (@ 0x400500A8) Output stage BASE_UART3_CLK control register */
+ __IO uint32_t BASE_OUT_CLK; /*!< (@ 0x400500AC) Output stage 20 control register for base clock BASE_OUT_CLK */
+ __I uint32_t RESERVED3[4];
+ __IO uint32_t BASE_APLL_CLK; /*!< (@ 0x400500C0) Output stage 25 control register for base clock BASE_APLL_CLK */
+ __IO uint32_t BASE_CGU_OUT0_CLK; /*!< (@ 0x400500C4) Output stage 25 control register for base clock BASE_CGU_OUT0_CLK */
+ __IO uint32_t BASE_CGU_OUT1_CLK; /*!< (@ 0x400500C8) Output stage 25 control register for base clock BASE_CGU_OUT1_CLK */
+} LPC_CGU_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- CCU1 -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC43xx Clock Control Unit (CCU) (CCU1)
+ */
+
+typedef struct { /*!< (@ 0x40051000) CCU1 Structure */
+ __IO uint32_t PM; /*!< (@ 0x40051000) CCU1 power mode register */
+ __I uint32_t BASE_STAT; /*!< (@ 0x40051004) CCU1 base clocks status register */
+ __I uint32_t RESERVED0[62];
+ __IO uint32_t CLK_APB3_BUS_CFG; /*!< (@ 0x40051100) CLK_APB3_BUS clock configuration register */
+ __I uint32_t CLK_APB3_BUS_STAT; /*!< (@ 0x40051104) CLK_APB3_BUS clock status register */
+ __IO uint32_t CLK_APB3_I2C1_CFG; /*!< (@ 0x40051108) CLK_APB3_I2C1 clock configuration register */
+ __I uint32_t CLK_APB3_I2C1_STAT; /*!< (@ 0x4005110C) CLK_APB3_I2C1 clock status register */
+ __IO uint32_t CLK_APB3_DAC_CFG; /*!< (@ 0x40051110) CLK_APB3_DAC clock configuration register */
+ __I uint32_t CLK_APB3_DAC_STAT; /*!< (@ 0x40051114) CLK_APB3_DAC clock status register */
+ __IO uint32_t CLK_APB3_ADC0_CFG; /*!< (@ 0x40051118) CLK_APB3_ADC0 clock configuration register */
+ __I uint32_t CLK_APB3_ADC0_STAT; /*!< (@ 0x4005111C) CLK_APB3_ADC0 clock status register */
+ __IO uint32_t CLK_APB3_ADC1_CFG; /*!< (@ 0x40051120) CLK_APB3_ADC1 clock configuration register */
+ __I uint32_t CLK_APB3_ADC1_STAT; /*!< (@ 0x40051124) CLK_APB3_ADC1 clock status register */
+ __IO uint32_t CLK_APB3_CAN0_CFG; /*!< (@ 0x40051128) CLK_APB3_CAN0 clock configuration register */
+ __I uint32_t CLK_APB3_CAN0_STAT; /*!< (@ 0x4005112C) CLK_APB3_CAN0 clock status register */
+ __I uint32_t RESERVED1[52];
+ __IO uint32_t CLK_APB1_BUS_CFG; /*!< (@ 0x40051200) CLK_APB1_BUS clock configuration register */
+ __I uint32_t CLK_APB1_BUS_STAT; /*!< (@ 0x40051204) CLK_APB1_BUS clock status register */
+ __IO uint32_t CLK_APB1_MOTOCONPWM_CFG; /*!< (@ 0x40051208) CLK_APB1_MOTOCONPWM clock configuration register */
+ __I uint32_t CLK_APB1_MOTOCONPWM_STAT; /*!< (@ 0x4005120C) CLK_APB1_MOTOCONPWM clock status register */
+ __IO uint32_t CLK_ABP1_I2C0_CFG; /*!< (@ 0x40051210) CLK_ABP1_I2C0 clock configuration register */
+ __I uint32_t CLK_APB1_I2C0_STAT; /*!< (@ 0x40051214) CLK_APB1_I2C0 clock status register */
+ __IO uint32_t CLK_APB1_I2S_CFG; /*!< (@ 0x40051218) CLK_APB1_I2S clock configuration register */
+ __I uint32_t CLK_APB1_I2S_STAT; /*!< (@ 0x4005121C) CLK_APB1_I2S clock status register */
+ __IO uint32_t CLK_APB1_CAN1_CFG; /*!< (@ 0x40051220) CLK_APB1_CAN1 clock configuration register */
+ __I uint32_t CLK_APB1_CAN1_STAT; /*!< (@ 0x40051224) CLK_APB1_CAN1 clock status register */
+ __I uint32_t RESERVED2[54];
+ __IO uint32_t CLK_SPIFI_CFG; /*!< (@ 0x40051300) CLK_SPIFI clock configuration register */
+ __I uint32_t CLK_SPIFI_STAT; /*!< (@ 0x40051304) CLK_APB1_SPIFI clock status register */
+ __I uint32_t RESERVED3[62];
+ __IO uint32_t CLK_M4_BUS_CFG; /*!< (@ 0x40051400) CLK_M4_BUS clock configuration register */
+ __I uint32_t CLK_M4_BUS_STAT; /*!< (@ 0x40051404) CLK_M4_BUSclock status register */
+ __IO uint32_t CLK_M4_SPIFI_CFG; /*!< (@ 0x40051408) CLK_M4_SPIFI clock configuration register */
+ __I uint32_t CLK_M4_SPIFI_STAT; /*!< (@ 0x4005140C) CLK_M4_SPIFI clock status register */
+ __IO uint32_t CLK_M4_GPIO_CFG; /*!< (@ 0x40051410) CLK_M4_GPIO clock configuration register */
+ __I uint32_t CLK_M4_GPIO_STAT; /*!< (@ 0x40051414) CLK_M4_GPIO clock status register */
+ __IO uint32_t CLK_M4_LCD_CFG; /*!< (@ 0x40051418) CLK_M4_LCD clock configuration register */
+ __I uint32_t CLK_M4_LCD_STAT; /*!< (@ 0x4005141C) CLK_M4_LCD clock status register */
+ __IO uint32_t CLK_M4_ETHERNET_CFG; /*!< (@ 0x40051420) CLK_M4_ETHERNET clock configuration register */
+ __I uint32_t CLK_M4_ETHERNET_STAT; /*!< (@ 0x40051424) CLK_M4_ETHERNET clock status register */
+ __IO uint32_t CLK_M4_USB0_CFG; /*!< (@ 0x40051428) CLK_M4_USB0 clock configuration register */
+ __I uint32_t CLK_M4_USB0_STAT; /*!< (@ 0x4005142C) CLK_M4_USB0 clock status register */
+ __IO uint32_t CLK_M4_EMC_CFG; /*!< (@ 0x40051430) CLK_M4_EMC clock configuration register */
+ __I uint32_t CLK_M4_EMC_STAT; /*!< (@ 0x40051434) CLK_M4_EMC clock status register */
+ __IO uint32_t CLK_M4_SDIO_CFG; /*!< (@ 0x40051438) CLK_M4_SDIO clock configuration register */
+ __I uint32_t CLK_M4_SDIO_STAT; /*!< (@ 0x4005143C) CLK_M4_SDIO clock status register */
+ __IO uint32_t CLK_M4_DMA_CFG; /*!< (@ 0x40051440) CLK_M4_DMA clock configuration register */
+ __I uint32_t CLK_M4_DMA_STAT; /*!< (@ 0x40051444) CLK_M4_DMA clock status register */
+ __IO uint32_t CLK_M4_M4CORE_CFG; /*!< (@ 0x40051448) CLK_M4_M4CORE clock configuration register */
+ __I uint32_t CLK_M4_M3CORE_STAT; /*!< (@ 0x4005144C) CLK_M4_M3CORE clock status register */
+ __I uint32_t RESERVED4[6];
+ __IO uint32_t CLK_M4_SCT_CFG; /*!< (@ 0x40051468) CLK_M4_SCT clock configuration register */
+ __I uint32_t CLK_M4_SCT_STAT; /*!< (@ 0x4005146C) CLK_M4_SCT clock status register */
+ __IO uint32_t CLK_M4_USB1_CFG; /*!< (@ 0x40051470) CLK_M4_USB1 clock configuration register */
+ __I uint32_t CLK_M4_USB1_STAT; /*!< (@ 0x40051474) CLK_M4_USB1 clock status register */
+ __IO uint32_t CLK_M4_EMCDIV_CFG; /*!< (@ 0x40051478) CLK_M4_EMCDIV clock configuration register */
+ __I uint32_t CLK_M4_EMCDIV_STAT; /*!< (@ 0x4005147C) CLK_M4_EMCDIV clock status register */
+ __I uint32_t RESERVED5[4];
+ __IO uint32_t CLK_M4_M0APP_CFG; /*!< (@ 0x40051490) CLK_M0APP_CFG clock configuration register */
+ __I uint32_t CLK_M4_M0APP_STAT; /*!< (@ 0x40051494) CLK_M4_MOAPP clock status register */
+ __I uint32_t RESERVED6[26];
+ __IO uint32_t CLK_M4_WWDT_CFG; /*!< (@ 0x40051500) CLK_M4_WWDT clock configuration register */
+ __I uint32_t CLK_M4_WWDT_STAT; /*!< (@ 0x40051504) CLK_M4_WWDT clock status register */
+ __IO uint32_t CLK_M4_USART0_CFG; /*!< (@ 0x40051508) CLK_M4_USART0 clock configuration register */
+ __I uint32_t CLK_M4_USART0_STAT; /*!< (@ 0x4005150C) CLK_M4_USART0 clock status register */
+ __IO uint32_t CLK_M4_UART1_CFG; /*!< (@ 0x40051510) CLK_M4_UART1 clock configuration register */
+ __I uint32_t CLK_M4_UART1_STAT; /*!< (@ 0x40051514) CLK_M4_UART1 clock status register */
+ __IO uint32_t CLK_M4_SSP0_CFG; /*!< (@ 0x40051518) CLK_M4_SSP0 clock configuration register */
+ __I uint32_t CLK_M4_SSP0_STAT; /*!< (@ 0x4005151C) CLK_M4_SSP0 clock status register */
+ __IO uint32_t CLK_M4_TIMER0_CFG; /*!< (@ 0x40051520) CLK_M4_TIMER0 clock configuration register */
+ __I uint32_t CLK_M4_TIMER0_STAT; /*!< (@ 0x40051524) CLK_M4_TIMER0 clock status register */
+ __IO uint32_t CLK_M4_TIMER1_CFG; /*!< (@ 0x40051528) CLK_M4_TIMER1clock configuration register */
+ __I uint32_t CLK_M4_TIMER1_STAT; /*!< (@ 0x4005152C) CLK_M4_TIMER1 clock status register */
+ __IO uint32_t CLK_M4_SCU_CFG; /*!< (@ 0x40051530) CLK_M4_SCU clock configuration register */
+ __I uint32_t CLK_M4_SCU_STAT; /*!< (@ 0x40051534) CLK_SCU_XXX clock status register */
+ __IO uint32_t CLK_M4_CREG_CFG; /*!< (@ 0x40051538) CLK_M4_CREGclock configuration register */
+ __I uint32_t CLK_M4_CREG_STAT; /*!< (@ 0x4005153C) CLK_M4_CREG clock status register */
+ __I uint32_t RESERVED7[48];
+ __IO uint32_t CLK_M4_RITIMER_CFG; /*!< (@ 0x40051600) CLK_M4_RITIMER clock configuration register */
+ __I uint32_t CLK_M4_RITIMER_STAT; /*!< (@ 0x40051604) CLK_M4_RITIMER clock status register */
+ __IO uint32_t CLK_M4_USART2_CFG; /*!< (@ 0x40051608) CLK_M4_USART2 clock configuration register */
+ __I uint32_t CLK_M4_USART2_STAT; /*!< (@ 0x4005160C) CLK_M4_USART2 clock status register */
+ __IO uint32_t CLK_M4_USART3_CFG; /*!< (@ 0x40051610) CLK_M4_USART3 clock configuration register */
+ __I uint32_t CLK_M4_USART3_STAT; /*!< (@ 0x40051614) CLK_M4_USART3 clock status register */
+ __IO uint32_t CLK_M4_TIMER2_CFG; /*!< (@ 0x40051618) CLK_M4_TIMER2 clock configuration register */
+ __I uint32_t CLK_M4_TIMER2_STAT; /*!< (@ 0x4005161C) CLK_M4_TIMER2 clock status register */
+ __IO uint32_t CLK_M4_TIMER3_CFG; /*!< (@ 0x40051620) CLK_M4_TIMER3 clock configuration register */
+ __I uint32_t CLK_M4_TIMER3_STAT; /*!< (@ 0x40051624) CLK_M4_TIMER3 clock status register */
+ __IO uint32_t CLK_M4_SSP1_CFG; /*!< (@ 0x40051628) CLK_M4_SSP1 clock configuration register */
+ __I uint32_t CLK_M4_SSP1_STAT; /*!< (@ 0x4005162C) CLK_M4_SSP1 clock status register */
+ __IO uint32_t CLK_M4_QEI_CFG; /*!< (@ 0x40051630) CLK_M4_QEIclock configuration register */
+ __I uint32_t CLK_M4_QEI_STAT; /*!< (@ 0x40051634) CLK_M4_QEI clock status register */
+ __I uint32_t RESERVED8[50];
+ __IO uint32_t CLK_PERIPH_BUS_CFG; /*!< (@ 0x40051700) CLK_PERIPH_BUS_CFG clock configuration register */
+ __I uint32_t CLK_PERIPH_BUS_STAT; /*!< (@ 0x40051704) CLK_PERIPH_BUS_STAT clock status register */
+ __I uint32_t RESERVED9[2];
+ __IO uint32_t CLK_PERIPH_CORE_CFG; /*!< (@ 0x40051710) CLK_PERIPH_CORE_CFG clock configuration register */
+ __I uint32_t CLK_PERIPH_CORE_STAT; /*!< (@ 0x40051714) CLK_CORE_BUS_STAT clock status register */
+ __IO uint32_t CLK_PERIPH_SGPIO_CFG; /*!< (@ 0x40051718) CLK_PERIPH_SGPIO_CFG clock configuration register */
+ __I uint32_t CLK_PERIPH_SGPIO_STAT; /*!< (@ 0x4005171C) CLK_CORE_SGPIO_STAT clock status register */
+ __I uint32_t RESERVED10[56];
+ __IO uint32_t CLK_USB0_CFG; /*!< (@ 0x40051800) CLK_M4_USB0 clock configuration register */
+ __I uint32_t CLK_USB0_STAT; /*!< (@ 0x40051804) CLK_USB0 clock status register */
+ __I uint32_t RESERVED11[62];
+ __IO uint32_t CLK_USB1_CFG; /*!< (@ 0x40051900) CLK_USB1 clock configuration register */
+ __I uint32_t CLK_USB1_STAT; /*!< (@ 0x40051904) CLK_USB1 clock status register */
+ __I uint32_t RESERVED12[62];
+ __IO uint32_t CLK_SPI_CFG; /*!< (@ 0x40051A00) CLK_SPI clock configuration register */
+ __I uint32_t CLK_SPI_STAT; /*!< (@ 0x40051A04) CLK_SPI clock status register */
+ __I uint32_t RESERVED13[62];
+ __IO uint32_t CLK_VADC_CFG; /*!< (@ 0x40051B00) CLK_VADC clock configuration register */
+ __I uint32_t CLK_VADC_STAT; /*!< (@ 0x40051B04) CLK_VADC clock status register */
+} LPC_CCU1_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- CCU2 -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx Clock Control Unit (CCU) Modification date=1/21/2011 Major revision=0 Minor revision=7 (CCU2)
+ */
+
+typedef struct { /*!< (@ 0x40052000) CCU2 Structure */
+ __IO uint32_t PM; /*!< (@ 0x40052000) Power mode register */
+ __I uint32_t BASE_STAT; /*!< (@ 0x40052004) CCU base clocks status register */
+ __I uint32_t RESERVED0[62];
+ __IO uint32_t CLK_APLL_CFG; /*!< (@ 0x40052100) CLK_APLL clock configuration register */
+ __I uint32_t CLK_APLL_STAT; /*!< (@ 0x40052104) CLK_APLL clock status register */
+ __I uint32_t RESERVED1[62];
+ __IO uint32_t CLK_APB2_USART3_CFG; /*!< (@ 0x40052200) CLK_APB2_USART3 clock configuration register */
+ __I uint32_t CLK_APB2_USART3_STAT; /*!< (@ 0x40052204) CLK_APB2_USART3 clock status register */
+ __I uint32_t RESERVED2[62];
+ __IO uint32_t CLK_APB2_USART2_CFG; /*!< (@ 0x40052300) CLK_APB2_USART2 clock configuration register */
+ __I uint32_t CLK_APB2_USART2_STAT; /*!< (@ 0x40052304) CLK_APB2_USART clock status register */
+ __I uint32_t RESERVED3[62];
+ __IO uint32_t CLK_APB0_UART1_CFG; /*!< (@ 0x40052400) CLK_APB2_UART1 clock configuration register */
+ __I uint32_t CLK_APB0_UART1_STAT; /*!< (@ 0x40052404) CLK_APB0_UART1 clock status register */
+ __I uint32_t RESERVED4[62];
+ __IO uint32_t CLK_APB0_USART0_CFG; /*!< (@ 0x40052500) CLK_APB2_USART0 clock configuration register */
+ __I uint32_t CLK_APB0_USART0_STAT; /*!< (@ 0x40052504) CLK_APB0_USART0 clock status register */
+ __I uint32_t RESERVED5[62];
+ __IO uint32_t CLK_APB2_SSP1_CFG; /*!< (@ 0x40052600) CLK_APB2_SSP1 clock configuration register */
+ __I uint32_t CLK_APB2_SSP1_STAT; /*!< (@ 0x40052604) CLK_APB2_SSP1 clock status register */
+ __I uint32_t RESERVED6[62];
+ __IO uint32_t CLK_APB0_SSP0_CFG; /*!< (@ 0x40052700) CLK_APB0_SSP0 clock configuration register */
+ __I uint32_t CLK_APB0_SSP0_STAT; /*!< (@ 0x40052704) CLK_APB0_SSP0 clock status register */
+ __I uint32_t RESERVED7[62];
+ __IO uint32_t CLK_SDIO_CFG; /*!< (@ 0x40052800) CLK_SDIO clock configuration register */
+ __I uint32_t CLK_SDIO_STAT; /*!< (@ 0x40052804) CLK_SDIO clock status register */
+} LPC_CCU2_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- RGU -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10503 Chapter title=LPC43xx Reset GenerationUnit (RGU) Modification date=7/20/2011 Major revision=0 Minor revision=13 (RGU)
+ */
+
+typedef struct { /*!< (@ 0x40053000) RGU Structure */
+ __I uint32_t RESERVED0[64];
+ __O uint32_t RESET_CTRL0; /*!< (@ 0x40053100) Reset control register 0 */
+ __O uint32_t RESET_CTRL1; /*!< (@ 0x40053104) Reset control register 1 */
+ __I uint32_t RESERVED1[2];
+ __IO uint32_t RESET_STATUS0; /*!< (@ 0x40053110) Reset status register 0 */
+ __IO uint32_t RESET_STATUS1; /*!< (@ 0x40053114) Reset status register 1 */
+ __IO uint32_t RESET_STATUS2; /*!< (@ 0x40053118) Reset status register 2 */
+ __IO uint32_t RESET_STATUS3; /*!< (@ 0x4005311C) Reset status register 3 */
+ __I uint32_t RESERVED2[12];
+ __I uint32_t RESET_ACTIVE_STATUS0; /*!< (@ 0x40053150) Reset active status register 0 */
+ __I uint32_t RESET_ACTIVE_STATUS1; /*!< (@ 0x40053154) Reset active status register 1 */
+ __I uint32_t RESERVED3[170];
+ __IO uint32_t RESET_EXT_STAT0; /*!< (@ 0x40053400) Reset external status register 0 for CORE_RST */
+ __IO uint32_t RESET_EXT_STAT1; /*!< (@ 0x40053404) Reset external status register 1 for PERIPH_RST */
+ __IO uint32_t RESET_EXT_STAT2; /*!< (@ 0x40053408) Reset external status register 2 for MASTER_RST */
+ __I uint32_t RESERVED4;
+ __IO uint32_t RESET_EXT_STAT4; /*!< (@ 0x40053410) Reset external status register 4 for WWDT_RST */
+ __IO uint32_t RESET_EXT_STAT5; /*!< (@ 0x40053414) Reset external status register 5 for CREG_RST */
+ __I uint32_t RESERVED5[2];
+ __IO uint32_t RESET_EXT_STAT8; /*!< (@ 0x40053420) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT9; /*!< (@ 0x40053424) Reset external status register */
+ __I uint32_t RESERVED6[3];
+ __IO uint32_t RESET_EXT_STAT13; /*!< (@ 0x40053434) Reset external status register */
+ __I uint32_t RESERVED7[2];
+ __IO uint32_t RESET_EXT_STAT16; /*!< (@ 0x40053440) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT17; /*!< (@ 0x40053444) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT18; /*!< (@ 0x40053448) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT19; /*!< (@ 0x4005344C) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT20; /*!< (@ 0x40053450) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT21; /*!< (@ 0x40053454) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT22; /*!< (@ 0x40053458) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT23; /*!< (@ 0x4005345C) Reset external status register */
+ __I uint32_t RESERVED8[4];
+ __IO uint32_t RESET_EXT_STAT28; /*!< (@ 0x40053470) Reset external status register */
+ __I uint32_t RESERVED9[3];
+ __IO uint32_t RESET_EXT_STAT32; /*!< (@ 0x40053480) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT33; /*!< (@ 0x40053484) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT34; /*!< (@ 0x40053488) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT35; /*!< (@ 0x4005348C) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT36; /*!< (@ 0x40053490) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT37; /*!< (@ 0x40053494) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT38; /*!< (@ 0x40053498) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT39; /*!< (@ 0x4005349C) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT40; /*!< (@ 0x400534A0) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT41; /*!< (@ 0x400534A4) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT42; /*!< (@ 0x400534A8) Reset external status register */
+ __I uint32_t RESERVED10;
+ __IO uint32_t RESET_EXT_STAT44; /*!< (@ 0x400534B0) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT45; /*!< (@ 0x400534B4) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT46; /*!< (@ 0x400534B8) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT47; /*!< (@ 0x400534BC) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT48; /*!< (@ 0x400534C0) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT49; /*!< (@ 0x400534C4) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT50; /*!< (@ 0x400534C8) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT51; /*!< (@ 0x400534CC) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT52; /*!< (@ 0x400534D0) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT53; /*!< (@ 0x400534D4) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT54; /*!< (@ 0x400534D8) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT55; /*!< (@ 0x400534DC) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT56; /*!< (@ 0x400534E0) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT57; /*!< (@ 0x400534E4) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT58; /*!< (@ 0x400534E8) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT59; /*!< (@ 0x400534EC) Reserved */
+ __IO uint32_t RESET_EXT_STAT60; /*!< (@ 0x400534F0) Reset external status register */
+ __IO uint32_t RESET_EXT_STAT61; /*!< (@ 0x400534F4) Reserved */
+ __IO uint32_t RESET_EXT_STAT62; /*!< (@ 0x400534F8) Reserved */
+ __IO uint32_t RESET_EXT_STAT63; /*!< (@ 0x400534FC) Reserved */
+} LPC_RGU_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- WWDT -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx Windowed Watchdog timer (WWDT) Modification date=1/14/2011 Major revision=0 Minor revision=7 (WWDT)
+ */
+
+typedef struct { /*!< (@ 0x40080000) WWDT Structure */
+ __IO uint32_t MOD; /*!< (@ 0x40080000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
+ __IO uint32_t TC; /*!< (@ 0x40080004) Watchdog timer constant register. This register determines the time-out value. */
+ __O uint32_t FEED; /*!< (@ 0x40080008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
+ __I uint32_t TV; /*!< (@ 0x4008000C) Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t WARNINT; /*!< (@ 0x40080014) Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
+ __IO uint32_t WINDOW; /*!< (@ 0x40080018) Watchdog timer window register. This register contains the Watchdog window value. */
+} LPC_WWDT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USARTn -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx USART0_2_3 Modification date=1/14/2011 Major revision=0 Minor revision=7 (USARTn)
+ */
+
+typedef struct { /*!< (@ 0x400xx000) USARTn Structure */
+
+ union {
+ __IO uint32_t DLL; /*!< (@ 0x400xx000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
+ __O uint32_t THR; /*!< (@ 0x400xx000) Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
+ __I uint32_t RBR; /*!< (@ 0x400xx000) Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
+ } ;
+
+ union {
+ __IO uint32_t IER; /*!< (@ 0x400xx004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
+ __IO uint32_t DLM; /*!< (@ 0x400xx004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
+ } ;
+
+ union {
+ __O uint32_t FCR; /*!< (@ 0x400xx008) FIFO Control Register. Controls UART FIFO usage and modes. */
+ __I uint32_t IIR; /*!< (@ 0x400xx008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
+ } ;
+ __IO uint32_t LCR; /*!< (@ 0x400xx00C) Line Control Register. Contains controls for frame formatting and break generation. */
+ __I uint32_t RESERVED0[1];
+ __I uint32_t LSR; /*!< (@ 0x400xx014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
+ __I uint32_t RESERVED1[1];
+ __IO uint32_t SCR; /*!< (@ 0x400xx01C) Scratch Pad Register. Eight-bit temporary storage for software. */
+ __IO uint32_t ACR; /*!< (@ 0x400xx020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
+ __IO uint32_t ICR; /*!< (@ 0x400xx024) IrDA control register (UART3 only) */
+ __IO uint32_t FDR; /*!< (@ 0x400xx028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
+ __IO uint32_t OSR; /*!< (@ 0x400xx02C) Oversampling Register. Controls the degree of oversampling during each bit time. */
+ __I uint32_t RESERVED2[4];
+ __IO uint32_t HDEN; /*!< (@ 0x400xx03C) Half-duplex enable Register */
+ __I uint32_t RESERVED3[1];
+ __IO uint32_t SCICTRL; /*!< (@ 0x400xx048) Smart card interface control register */
+ __IO uint32_t RS485CTRL; /*!< (@ 0x400xx04C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
+ __IO uint32_t RS485ADRMATCH; /*!< (@ 0x400xx050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
+ __IO uint32_t RS485DLY; /*!< (@ 0x400xx054) RS-485/EIA-485 direction control delay. */
+ __IO uint32_t SYNCCTRL; /*!< (@ 0x400xx058) Synchronous mode control register. */
+ __IO uint32_t TER; /*!< (@ 0x400xx05C) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */
+} LPC_USARTn_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- UART1 -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx UART1 Modification date=1/14/2011 Major revision=0 Minor revision=7 (UART1)
+ */
+
+typedef struct { /*!< (@ 0x40082000) UART1 Structure */
+
+ union {
+ __IO uint32_t DLL; /*!< (@ 0x40082000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
+ __O uint32_t THR; /*!< (@ 0x40082000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
+ __I uint32_t RBR; /*!< (@ 0x40082000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
+ } ;
+
+ union {
+ __IO uint32_t IER; /*!< (@ 0x40082004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0) */
+ __IO uint32_t DLM; /*!< (@ 0x40082004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.(DLAB=1) */
+ } ;
+
+ union {
+ __O uint32_t FCR; /*!< (@ 0x40082008) FIFO Control Register. Controls UART1 FIFO usage and modes. */
+ __I uint32_t IIR; /*!< (@ 0x40082008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
+ } ;
+ __IO uint32_t LCR; /*!< (@ 0x4008200C) Line Control Register. Contains controls for frame formatting and break generation. */
+ __IO uint32_t MCR; /*!< (@ 0x40082010) Modem Control Register. Contains controls for flow control handshaking and loopback mode. */
+ __I uint32_t LSR; /*!< (@ 0x40082014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
+ __I uint32_t MSR; /*!< (@ 0x40082018) Modem Status Register. Contains handshake signal status flags. */
+ __IO uint32_t SCR; /*!< (@ 0x4008201C) Scratch Pad Register. 8-bit temporary storage for software. */
+ __IO uint32_t ACR; /*!< (@ 0x40082020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t FDR; /*!< (@ 0x40082028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
+ __I uint32_t RESERVED1;
+ __IO uint32_t TER; /*!< (@ 0x40082030) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */
+ __I uint32_t RESERVED2[6];
+ __IO uint32_t RS485CTRL; /*!< (@ 0x4008204C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
+ __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40082050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
+ __IO uint32_t RS485DLY; /*!< (@ 0x40082054) RS-485/EIA-485 direction control delay. */
+ __I uint32_t FIFOLVL; /*!< (@ 0x40082058) FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
+} LPC_UART1_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SSPn -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx SSP0/1 Modification date=1/14/2011 Major revision=0 Minor revision=7 (SSP0)
+ */
+
+typedef struct { /*!< (@ 0x400xx000) SSPn Structure */
+ __IO uint32_t CR0; /*!< (@ 0x400xx000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
+ __IO uint32_t CR1; /*!< (@ 0x400xx004) Control Register 1. Selects master/slave and other modes. */
+ __IO uint32_t DR; /*!< (@ 0x400xx008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
+ __I uint32_t SR; /*!< (@ 0x400xx00C) Status Register */
+ __IO uint32_t CPSR; /*!< (@ 0x400xx010) Clock Prescale Register */
+ __IO uint32_t IMSC; /*!< (@ 0x400xx014) Interrupt Mask Set and Clear Register */
+ __I uint32_t RIS; /*!< (@ 0x400xx018) Raw Interrupt Status Register */
+ __I uint32_t MIS; /*!< (@ 0x400xx01C) Masked Interrupt Status Register */
+ __O uint32_t ICR; /*!< (@ 0x400xx020) SSPICR Interrupt Clear Register */
+ __IO uint32_t DMACR; /*!< (@ 0x400xx024) SSPn DMA control register */
+} LPC_SSPn_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- TIMERn -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx Timer0/1/2/3 Modification date=1/14/2011 Major revision=0 Minor revision=7 (TIMERn)
+ */
+
+typedef struct { /*!< (@ 0x400xx000) TIMERn Structure */
+ __IO uint32_t IR; /*!< (@ 0x400xx000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+ __IO uint32_t TCR; /*!< (@ 0x400xx004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+ __IO uint32_t TC; /*!< (@ 0x400xx008) Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
+ __IO uint32_t PR; /*!< (@ 0x400xx00C) Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
+ __IO uint32_t PC; /*!< (@ 0x400xx010) Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
+ __IO uint32_t MCR; /*!< (@ 0x400xx014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
+ __IO uint32_t MR[4]; /*!< (@ 0x400xx018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+ __IO uint32_t CCR; /*!< (@ 0x400xx028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+ __IO uint32_t CR[4]; /*!< (@ 0x400xx02C) Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
+ __IO uint32_t EMR; /*!< (@ 0x400xx03C) External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
+ __I uint32_t RESERVED0[12];
+ __IO uint32_t CTCR; /*!< (@ 0x400xx070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+} LPC_TIMERn_Type;
+
+
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SCU -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx System Control Unit (SCU) Modification date=6/8/2011 Major revision=0 Minor revision=10 (SCU)
+ */
+
+typedef struct { /*!< (@ 0x40086000) SCU Structure */
+ __IO uint32_t SFSP0_0; /*!< (@ 0x40086000) Pin configuration register for pins P0 */
+ __IO uint32_t SFSP0_1; /*!< (@ 0x40086004) Pin configuration register for pins P0 */
+ __I uint32_t RESERVED0[30];
+ __IO uint32_t SFSP1_0; /*!< (@ 0x40086080) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_1; /*!< (@ 0x40086084) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_2; /*!< (@ 0x40086088) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_3; /*!< (@ 0x4008608C) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_4; /*!< (@ 0x40086090) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_5; /*!< (@ 0x40086094) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_6; /*!< (@ 0x40086098) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_7; /*!< (@ 0x4008609C) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_8; /*!< (@ 0x400860A0) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_9; /*!< (@ 0x400860A4) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_10; /*!< (@ 0x400860A8) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_11; /*!< (@ 0x400860AC) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_12; /*!< (@ 0x400860B0) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_13; /*!< (@ 0x400860B4) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_14; /*!< (@ 0x400860B8) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_15; /*!< (@ 0x400860BC) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_16; /*!< (@ 0x400860C0) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_17; /*!< (@ 0x400860C4) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_18; /*!< (@ 0x400860C8) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_19; /*!< (@ 0x400860CC) Pin configuration register for pins P1 */
+ __IO uint32_t SFSP1_20; /*!< (@ 0x400860D0) Pin configuration register for pins P1 */
+ __I uint32_t RESERVED1[11];
+ __IO uint32_t SFSP2_0; /*!< (@ 0x40086100) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_1; /*!< (@ 0x40086104) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_2; /*!< (@ 0x40086108) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_3; /*!< (@ 0x4008610C) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_4; /*!< (@ 0x40086110) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_5; /*!< (@ 0x40086114) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_6; /*!< (@ 0x40086118) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_7; /*!< (@ 0x4008611C) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_8; /*!< (@ 0x40086120) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_9; /*!< (@ 0x40086124) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_10; /*!< (@ 0x40086128) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_11; /*!< (@ 0x4008612C) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_12; /*!< (@ 0x40086130) Pin configuration register for pins P2 */
+ __IO uint32_t SFSP2_13; /*!< (@ 0x40086134) Pin configuration register for pins P2 */
+ __I uint32_t RESERVED2[18];
+ __IO uint32_t SFSP3_0; /*!< (@ 0x40086180) Pin configuration register for pins P3 */
+ __IO uint32_t SFSP3_1; /*!< (@ 0x40086184) Pin configuration register for pins P3 */
+ __IO uint32_t SFSP3_2; /*!< (@ 0x40086188) Pin configuration register for pins P3 */
+ __IO uint32_t SFSP3_3; /*!< (@ 0x4008618C) Pin configuration register for pins P3 */
+ __IO uint32_t SFSP3_4; /*!< (@ 0x40086190) Pin configuration register for pins P3 */
+ __IO uint32_t SFSP3_5; /*!< (@ 0x40086194) Pin configuration register for pins P3 */
+ __IO uint32_t SFSP3_6; /*!< (@ 0x40086198) Pin configuration register for pins P3 */
+ __IO uint32_t SFSP3_7; /*!< (@ 0x4008619C) Pin configuration register for pins P3 */
+ __IO uint32_t SFSP3_8; /*!< (@ 0x400861A0) Pin configuration register for pins P3 */
+ __I uint32_t RESERVED3[23];
+ __IO uint32_t SFSP4_0; /*!< (@ 0x40086200) Pin configuration register for pins P4 */
+ __IO uint32_t SFSP4_1; /*!< (@ 0x40086204) Pin configuration register for pins P4 */
+ __IO uint32_t SFSP4_2; /*!< (@ 0x40086208) Pin configuration register for pins P4 */
+ __IO uint32_t SFSP4_3; /*!< (@ 0x4008620C) Pin configuration register for pins P4 */
+ __IO uint32_t SFSP4_4; /*!< (@ 0x40086210) Pin configuration register for pins P4 */
+ __IO uint32_t SFSP4_5; /*!< (@ 0x40086214) Pin configuration register for pins P4 */
+ __IO uint32_t SFSP4_6; /*!< (@ 0x40086218) Pin configuration register for pins P4 */
+ __IO uint32_t SFSP4_7; /*!< (@ 0x4008621C) Pin configuration register for pins P4 */
+ __IO uint32_t SFSP4_8; /*!< (@ 0x40086220) Pin configuration register for pins P4 */
+ __IO uint32_t SFSP4_9; /*!< (@ 0x40086224) Pin configuration register for pins P4 */
+ __IO uint32_t SFSP4_10; /*!< (@ 0x40086228) Pin configuration register for pins P4 */
+ __I uint32_t RESERVED4[21];
+ __IO uint32_t SFSP5_0; /*!< (@ 0x40086280) Pin configuration register for pins P5 */
+ __IO uint32_t SFSP5_1; /*!< (@ 0x40086284) Pin configuration register for pins P5 */
+ __IO uint32_t SFSP5_2; /*!< (@ 0x40086288) Pin configuration register for pins P5 */
+ __IO uint32_t SFSP5_3; /*!< (@ 0x4008628C) Pin configuration register for pins P5 */
+ __IO uint32_t SFSP5_4; /*!< (@ 0x40086290) Pin configuration register for pins P5 */
+ __IO uint32_t SFSP5_5; /*!< (@ 0x40086294) Pin configuration register for pins P5 */
+ __IO uint32_t SFSP5_6; /*!< (@ 0x40086298) Pin configuration register for pins P5 */
+ __IO uint32_t SFSP5_7; /*!< (@ 0x4008629C) Pin configuration register for pins P5 */
+ __I uint32_t RESERVED5[24];
+ __IO uint32_t SFSP6_0; /*!< (@ 0x40086300) Pin configuration register for pins P6 */
+ __IO uint32_t SFSP6_1; /*!< (@ 0x40086304) Pin configuration register for pins P6 */
+ __IO uint32_t SFSP6_2; /*!< (@ 0x40086308) Pin configuration register for pins P6 */
+ __IO uint32_t SFSP6_3; /*!< (@ 0x4008630C) Pin configuration register for pins P6 */
+ __IO uint32_t SFSP6_4; /*!< (@ 0x40086310) Pin configuration register for pins P6 */
+ __IO uint32_t SFSP6_5; /*!< (@ 0x40086314) Pin configuration register for pins P6 */
+ __IO uint32_t SFSP6_6; /*!< (@ 0x40086318) Pin configuration register for pins P6 */
+ __IO uint32_t SFSP6_7; /*!< (@ 0x4008631C) Pin configuration register for pins P6 */
+ __IO uint32_t SFSP6_8; /*!< (@ 0x40086320) Pin configuration register for pins P6 */
+ __IO uint32_t SFSP6_9; /*!< (@ 0x40086324) Pin configuration register for pins P6 */
+ __IO uint32_t SFSP6_10; /*!< (@ 0x40086328) Pin configuration register for pins P6 */
+ __IO uint32_t SFSP6_11; /*!< (@ 0x4008632C) Pin configuration register for pins P6 */
+ __IO uint32_t SFSP6_12; /*!< (@ 0x40086330) Pin configuration register for pins P6 */
+ __I uint32_t RESERVED6[19];
+ __IO uint32_t SFSP7_0; /*!< (@ 0x40086380) Pin configuration register for pins P7 */
+ __IO uint32_t SFSP7_1; /*!< (@ 0x40086384) Pin configuration register for pins P7 */
+ __IO uint32_t SFSP7_2; /*!< (@ 0x40086388) Pin configuration register for pins P7 */
+ __IO uint32_t SFSP7_3; /*!< (@ 0x4008638C) Pin configuration register for pins P7 */
+ __IO uint32_t SFSP7_4; /*!< (@ 0x40086390) Pin configuration register for pins P7 */
+ __IO uint32_t SFSP7_5; /*!< (@ 0x40086394) Pin configuration register for pins P7 */
+ __IO uint32_t SFSP7_6; /*!< (@ 0x40086398) Pin configuration register for pins P7 */
+ __IO uint32_t SFSP7_7; /*!< (@ 0x4008639C) Pin configuration register for pins P7 */
+ __I uint32_t RESERVED7[24];
+ __IO uint32_t SFSP8_0; /*!< (@ 0x40086400) Pin configuration register for pins P8 */
+ __IO uint32_t SFSP8_1; /*!< (@ 0x40086404) Pin configuration register for pins P8 */
+ __IO uint32_t SFSP8_2; /*!< (@ 0x40086408) Pin configuration register for pins P8 */
+ __IO uint32_t SFSP8_3; /*!< (@ 0x4008640C) Pin configuration register for pins P8 */
+ __IO uint32_t SFSP8_4; /*!< (@ 0x40086410) Pin configuration register for pins P8 */
+ __IO uint32_t SFSP8_5; /*!< (@ 0x40086414) Pin configuration register for pins P8 */
+ __IO uint32_t SFSP8_6; /*!< (@ 0x40086418) Pin configuration register for pins P8 */
+ __IO uint32_t SFSP8_7; /*!< (@ 0x4008641C) Pin configuration register for pins P8 */
+ __IO uint32_t SFSP8_8; /*!< (@ 0x40086420) Pin configuration register for pins P8 */
+ __I uint32_t RESERVED8[23];
+ __IO uint32_t SFSP9_0; /*!< (@ 0x40086480) Pin configuration register for pins P9 */
+ __IO uint32_t SFSP9_1; /*!< (@ 0x40086484) Pin configuration register for pins P9 */
+ __IO uint32_t SFSP9_2; /*!< (@ 0x40086488) Pin configuration register for pins P9 */
+ __IO uint32_t SFSP9_3; /*!< (@ 0x4008648C) Pin configuration register for pins P9 */
+ __IO uint32_t SFSP9_4; /*!< (@ 0x40086490) Pin configuration register for pins P9 */
+ __IO uint32_t SFSP9_5; /*!< (@ 0x40086494) Pin configuration register for pins P9 */
+ __IO uint32_t SFSP9_6; /*!< (@ 0x40086498) Pin configuration register for pins P9 */
+ __I uint32_t RESERVED9[25];
+ __IO uint32_t SFSPA_0; /*!< (@ 0x40086500) Pin configuration register for pins PA */
+ __IO uint32_t SFSPA_1; /*!< (@ 0x40086504) Pin configuration register for pins PA */
+ __IO uint32_t SFSPA_2; /*!< (@ 0x40086508) Pin configuration register for pins PA */
+ __IO uint32_t SFSPA_3; /*!< (@ 0x4008650C) Pin configuration register for pins PA */
+ __IO uint32_t SFSPA_4; /*!< (@ 0x40086510) Pin configuration register for pins PA */
+ __I uint32_t RESERVED10[27];
+ __IO uint32_t SFSPB_0; /*!< (@ 0x40086580) Pin configuration register for pins PB */
+ __IO uint32_t SFSPB_1; /*!< (@ 0x40086584) Pin configuration register for pins PB */
+ __IO uint32_t SFSPB_2; /*!< (@ 0x40086588) Pin configuration register for pins PB */
+ __IO uint32_t SFSPB_3; /*!< (@ 0x4008658C) Pin configuration register for pins PB */
+ __IO uint32_t SFSPB_4; /*!< (@ 0x40086590) Pin configuration register for pins PB */
+ __IO uint32_t SFSPB_5; /*!< (@ 0x40086594) Pin configuration register for pins PB */
+ __IO uint32_t SFSPB_6; /*!< (@ 0x40086598) Pin configuration register for pins PB */
+ __I uint32_t RESERVED11[25];
+ __IO uint32_t SFSPC_0; /*!< (@ 0x40086600) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_1; /*!< (@ 0x40086604) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_2; /*!< (@ 0x40086608) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_3; /*!< (@ 0x4008660C) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_4; /*!< (@ 0x40086610) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_5; /*!< (@ 0x40086614) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_6; /*!< (@ 0x40086618) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_7; /*!< (@ 0x4008661C) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_8; /*!< (@ 0x40086620) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_9; /*!< (@ 0x40086624) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_10; /*!< (@ 0x40086628) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_11; /*!< (@ 0x4008662C) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_12; /*!< (@ 0x40086630) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_13; /*!< (@ 0x40086634) Pin configuration register for pins PC */
+ __IO uint32_t SFSPC_14; /*!< (@ 0x40086638) Pin configuration register for pins PC */
+ __I uint32_t RESERVED12[17];
+ __IO uint32_t SFSPD_0; /*!< (@ 0x40086680) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_1; /*!< (@ 0x40086684) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_2; /*!< (@ 0x40086688) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_3; /*!< (@ 0x4008668C) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_4; /*!< (@ 0x40086690) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_5; /*!< (@ 0x40086694) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_6; /*!< (@ 0x40086698) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_7; /*!< (@ 0x4008669C) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_8; /*!< (@ 0x400866A0) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_9; /*!< (@ 0x400866A4) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_10; /*!< (@ 0x400866A8) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_11; /*!< (@ 0x400866AC) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_12; /*!< (@ 0x400866B0) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_13; /*!< (@ 0x400866B4) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_14; /*!< (@ 0x400866B8) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_15; /*!< (@ 0x400866BC) Pin configuration register for pins PD */
+ __IO uint32_t SFSPD_16; /*!< (@ 0x400866C0) Pin configuration register for pins PD */
+ __I uint32_t RESERVED13[15];
+ __IO uint32_t SFSPE_0; /*!< (@ 0x40086700) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_1; /*!< (@ 0x40086704) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_2; /*!< (@ 0x40086708) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_3; /*!< (@ 0x4008670C) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_4; /*!< (@ 0x40086710) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_5; /*!< (@ 0x40086714) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_6; /*!< (@ 0x40086718) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_7; /*!< (@ 0x4008671C) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_8; /*!< (@ 0x40086720) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_9; /*!< (@ 0x40086724) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_10; /*!< (@ 0x40086728) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_11; /*!< (@ 0x4008672C) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_12; /*!< (@ 0x40086730) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_13; /*!< (@ 0x40086734) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_14; /*!< (@ 0x40086738) Pin configuration register for pins PE */
+ __IO uint32_t SFSPE_15; /*!< (@ 0x4008673C) Pin configuration register for pins PE */
+ __I uint32_t RESERVED14[16];
+ __IO uint32_t SFSPF_0; /*!< (@ 0x40086780) Pin configuration register for pins PF */
+ __IO uint32_t SFSPF_1; /*!< (@ 0x40086784) Pin configuration register for pins PF */
+ __IO uint32_t SFSPF_2; /*!< (@ 0x40086788) Pin configuration register for pins PF */
+ __IO uint32_t SFSPF_3; /*!< (@ 0x4008678C) Pin configuration register for pins PF */
+ __IO uint32_t SFSPF_4; /*!< (@ 0x40086790) Pin configuration register for pins PF */
+ __IO uint32_t SFSPF_5; /*!< (@ 0x40086794) Pin configuration register for pins PF */
+ __IO uint32_t SFSPF_6; /*!< (@ 0x40086798) Pin configuration register for pins PF */
+ __IO uint32_t SFSPF_7; /*!< (@ 0x4008679C) Pin configuration register for pins PF */
+ __IO uint32_t SFSPF_8; /*!< (@ 0x400867A0) Pin configuration register for pins PF */
+ __IO uint32_t SFSPF_9; /*!< (@ 0x400867A4) Pin configuration register for pins PF */
+ __IO uint32_t SFSPF_10; /*!< (@ 0x400867A8) Pin configuration register for pins PF */
+ __IO uint32_t SFSPF_11; /*!< (@ 0x400867AC) Pin configuration register for pins PF */
+ __I uint32_t RESERVED15[276];
+ __IO uint32_t SFSCLK_0; /*!< (@ 0x40086C00) Pin configuration register for pin CLK0 */
+ __IO uint32_t SFSCLK_1; /*!< (@ 0x40086C04) Pin configuration register for pin CLK1 */
+ __IO uint32_t SFSCLK_2; /*!< (@ 0x40086C08) Pin configuration register for pin CLK2 */
+ __IO uint32_t SFSCLK_3; /*!< (@ 0x40086C0C) Pin configuration register for pin CLK3 */
+ __I uint32_t RESERVED16[28];
+ __IO uint32_t SFSUSB; /*!< (@ 0x40086C80) Pin configuration register for */
+ __IO uint32_t SFSI2C0; /*!< (@ 0x40086C84) Pin configuration register for I 2C0-bus pins */
+ __IO uint32_t ENAIO0; /*!< (@ 0x40086C88) ADC0 function select register */
+ __IO uint32_t ENAIO1; /*!< (@ 0x40086C8C) ADC1 function select register */
+ __IO uint32_t ENAIO2; /*!< (@ 0x40086C90) Analog function select register */
+ __I uint32_t RESERVED17[27];
+ __IO uint32_t EMCDELAYCLK; /*!< (@ 0x40086D00) EMC clock delay register */
+ __I uint32_t RESERVED18[63];
+ __IO uint32_t PINTSEL0; /*!< (@ 0x40086E00) Pin interrupt select register for pin interrupts 0 to 3. */
+ __IO uint32_t PINTSEL1; /*!< (@ 0x40086E04) Pin interrupt select register for pin interrupts 4 to 7. */
+} LPC_SCU_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_PIN_INT -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief GPIO pin interrupt (GPIO_PIN_INT)
+ */
+
+typedef struct { /*!< (@ 0x40087000) GPIO_PIN_INT Structure */
+ __IO uint32_t ISEL; /*!< (@ 0x40087000) Pin Interrupt Mode register */
+ __IO uint32_t IENR; /*!< (@ 0x40087004) Pin Interrupt Enable (Rising) register */
+ __O uint32_t SIENR; /*!< (@ 0x40087008) Set Pin Interrupt Enable (Rising) register */
+ __O uint32_t CIENR; /*!< (@ 0x4008700C) Clear Pin Interrupt Enable (Rising) register */
+ __IO uint32_t IENF; /*!< (@ 0x40087010) Pin Interrupt Enable Falling Edge / Active Level register */
+ __O uint32_t SIENF; /*!< (@ 0x40087014) Set Pin Interrupt Enable Falling Edge / Active Level register */
+ __O uint32_t CIENF; /*!< (@ 0x40087018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
+ __IO uint32_t RISE; /*!< (@ 0x4008701C) Pin Interrupt Rising Edge register */
+ __IO uint32_t FALL; /*!< (@ 0x40087020) Pin Interrupt Falling Edge register */
+ __IO uint32_t IST; /*!< (@ 0x40087024) Pin Interrupt Status register */
+} LPC_GPIO_PIN_INT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_GROUP_INTn -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief GPIO group interrupt 0 (GPIO_GROUP_INTn)
+ */
+
+typedef struct { /*!< (@ 0x40088000) GPIO_GROUP_INTn Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x40088000) GPIO grouped interrupt control register */
+ __I uint32_t RESERVED0[7];
+ __IO uint32_t PORT_POL0; /*!< (@ 0x40088020) GPIO grouped interrupt port polarity register */
+ __IO uint32_t PORT_POL1; /*!< (@ 0x40088024) GPIO grouped interrupt port polarity register */
+ __IO uint32_t PORT_POL2; /*!< (@ 0x40088028) GPIO grouped interrupt port polarity register */
+ __IO uint32_t PORT_POL3; /*!< (@ 0x4008802C) GPIO grouped interrupt port polarity register */
+ __IO uint32_t PORT_POL4; /*!< (@ 0x40088030) GPIO grouped interrupt port polarity register */
+ __IO uint32_t PORT_POL5; /*!< (@ 0x40088034) GPIO grouped interrupt port polarity register */
+ __IO uint32_t PORT_POL6; /*!< (@ 0x40088038) GPIO grouped interrupt port polarity register */
+ __IO uint32_t PORT_POL7; /*!< (@ 0x4008803C) GPIO grouped interrupt port polarity register */
+ __IO uint32_t PORT_ENA0; /*!< (@ 0x40088040) GPIO grouped interrupt port m enable register */
+ __IO uint32_t PORT_ENA1; /*!< (@ 0x40088044) GPIO grouped interrupt port m enable register */
+ __IO uint32_t PORT_ENA2; /*!< (@ 0x40088048) GPIO grouped interrupt port m enable register */
+ __IO uint32_t PORT_ENA3; /*!< (@ 0x4008804C) GPIO grouped interrupt port m enable register */
+ __IO uint32_t PORT_ENA4; /*!< (@ 0x40088050) GPIO grouped interrupt port m enable register */
+ __IO uint32_t PORT_ENA5; /*!< (@ 0x40088054) GPIO grouped interrupt port m enable register */
+ __IO uint32_t PORT_ENA6; /*!< (@ 0x40088058) GPIO grouped interrupt port m enable register */
+ __IO uint32_t PORT_ENA7; /*!< (@ 0x4008805C) GPIO grouped interrupt port m enable register */
+} LPC_GPIO_GROUP_INTn_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- MCPWM -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx Motor Control PWM (MOTOCONPWM) Modification date=1/14/2011 Major revision=0 Minor revision=7 (MCPWM)
+ */
+
+typedef struct { /*!< (@ 0x400A0000) MCPWM Structure */
+ __I uint32_t CON; /*!< (@ 0x400A0000) PWM Control read address */
+ __O uint32_t CON_SET; /*!< (@ 0x400A0004) PWM Control set address */
+ __O uint32_t CON_CLR; /*!< (@ 0x400A0008) PWM Control clear address */
+ __I uint32_t CAPCON; /*!< (@ 0x400A000C) Capture Control read address */
+ __O uint32_t CAPCON_SET; /*!< (@ 0x400A0010) Capture Control set address */
+ __O uint32_t CAPCON_CLR; /*!< (@ 0x400A0014) Event Control clear address */
+ __IO uint32_t TC[3]; /*!< (@ 0x400A0018) Timer Counter register */
+ __IO uint32_t LIM[3]; /*!< (@ 0x400A0024) Limit register */
+ __IO uint32_t MAT[3]; /*!< (@ 0x400A0030) Match register */
+ __IO uint32_t DT; /*!< (@ 0x400A003C) Dead time register */
+ __IO uint32_t CCP; /*!< (@ 0x400A0040) Communication Pattern register */
+ __I uint32_t CAP[3]; /*!< (@ 0x400A0044) Capture register */
+ __I uint32_t INTEN; /*!< (@ 0x400A0050) Interrupt Enable read address */
+ __O uint32_t INTEN_SET; /*!< (@ 0x400A0054) Interrupt Enable set address */
+ __O uint32_t INTEN_CLR; /*!< (@ 0x400A0058) Interrupt Enable clear address */
+ __I uint32_t CNTCON; /*!< (@ 0x400A005C) Count Control read address */
+ __O uint32_t CNTCON_SET; /*!< (@ 0x400A0060) Count Control set address */
+ __O uint32_t CNTCON_CLR; /*!< (@ 0x400A0064) Count Control clear address */
+ __I uint32_t INTF; /*!< (@ 0x400A0068) Interrupt flags read address */
+ __O uint32_t INTF_SET; /*!< (@ 0x400A006C) Interrupt flags set address */
+ __O uint32_t INTF_CLR; /*!< (@ 0x400A0070) Interrupt flags clear address */
+ __O uint32_t CAP_CLR; /*!< (@ 0x400A0074) Capture clear address */
+} LPC_MCPWM_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- I2C0 -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx I2C-bus interface Modification date=1/14/2011 Major revision=0 Minor revision=7 (I2Cn)
+ */
+
+typedef struct { /*!< (@ 0x400xx000) I2C0 Structure */
+ __IO uint32_t CONSET; /*!< (@ 0x400xx000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
+ __I uint32_t STAT; /*!< (@ 0x400xx004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
+ __IO uint32_t DAT; /*!< (@ 0x400xx008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
+ __IO uint32_t ADR0; /*!< (@ 0x400xx00C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+ __IO uint32_t SCLH; /*!< (@ 0x400xx010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
+ __IO uint32_t SCLL; /*!< (@ 0x400xx014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
+ __O uint32_t CONCLR; /*!< (@ 0x400xx018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
+ __IO uint32_t MMCTRL; /*!< (@ 0x400xx01C) Monitor mode control register. */
+ __IO uint32_t ADR1; /*!< (@ 0x400xx020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+ __IO uint32_t ADR2; /*!< (@ 0x400xx024) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+ __IO uint32_t ADR3; /*!< (@ 0x400xx028) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+ __I uint32_t DATA_BUFFER; /*!< (@ 0x400xx02C) Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
+ __IO uint32_t MASK[4]; /*!< (@ 0x400xx030) I2C Slave address mask register */
+} LPC_I2Cn_Type;
+
+// ------------------------------------------------------------------------------------------------
+// ----- I2Sn -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx I2S interface Modification date=1/14/2011 Major revision=0 Minor revision=7 (I2Sn)
+ 0x400A2000 / 0x400A3000
+ */
+
+typedef struct { /*!< (@ 0x400Ax000) I2S Structure */
+ __IO uint32_t DAO; /*!< (@ 0x400Ax000) I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel. */
+ __IO uint32_t DAI; /*!< (@ 0x400Ax004) I2S Digital Audio Input Register. Contains control bits for the I2S receive channel. */
+ __O uint32_t TXFIFO; /*!< (@ 0x400Ax008) I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO. */
+ __I uint32_t RXFIFO; /*!< (@ 0x400Ax00C) I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO. */
+ __I uint32_t STATE; /*!< (@ 0x400Ax010) I2S Status Feedback Register. Contains status information about the I2S interface. */
+ __IO uint32_t DMA1; /*!< (@ 0x400Ax014) I2S DMA Configuration Register 1. Contains control information for DMA request 1. */
+ __IO uint32_t DMA2; /*!< (@ 0x400Ax018) I2S DMA Configuration Register 2. Contains control information for DMA request 2. */
+ __IO uint32_t IRQ; /*!< (@ 0x400Ax01C) I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated. */
+ __IO uint32_t TXRATE; /*!< (@ 0x400Ax020) I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. */
+ __IO uint32_t RXRATE; /*!< (@ 0x400Ax024) I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. */
+ __IO uint32_t TXBITRATE; /*!< (@ 0x400Ax028) I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock. */
+ __IO uint32_t RXBITRATE; /*!< (@ 0x400Ax02C) I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock. */
+ __IO uint32_t TXMODE; /*!< (@ 0x400Ax030) I2S Transmit mode control. */
+ __IO uint32_t RXMODE; /*!< (@ 0x400Ax034) I2S Receive mode control. */
+} LPC_I2Sn_Type;
+
+// ------------------------------------------------------------------------------------------------
+// ----- C_CANn -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx C_CAN Modification date=1/18/2011 Major revision=0 Minor revision=7 (C_CANn)
+ 0x400A4000 / 0x400E2000
+ */
+
+typedef struct { /*!< (@ 0x400E2000) C_CAN Structure */
+ __IO uint32_t CNTL; /*!< (@ 0x400E2000) CAN control */
+ __IO uint32_t STAT; /*!< (@ 0x400E2004) Status register */
+ __I uint32_t EC; /*!< (@ 0x400E2008) Error counter */
+ __IO uint32_t BT; /*!< (@ 0x400E200C) Bit timing register */
+ __I uint32_t INT; /*!< (@ 0x400E2010) Interrupt register */
+ __IO uint32_t TEST; /*!< (@ 0x400E2014) Test register */
+ __IO uint32_t BRPE; /*!< (@ 0x400E2018) Baud rate prescaler extension register */
+ __I uint32_t RESERVED0;
+ __IO uint32_t IF1_CMDREQ; /*!< (@ 0x400E2020) Message interface command request */
+
+ union {
+ __IO uint32_t IF1_CMDMSK_R; /*!< (@ 0x400E2024) Message interface command mask (read direction) */
+ __IO uint32_t IF1_CMDMSK_W; /*!< (@ 0x400E2024) Message interface command mask (write direction) */
+ } ;
+ __IO uint32_t IF1_MSK1; /*!< (@ 0x400E2028) Message interface mask 1 */
+ __IO uint32_t IF1_MSK2; /*!< (@ 0x400E202C) Message interface 1 mask 2 */
+ __IO uint32_t IF1_ARB1; /*!< (@ 0x400E2030) Message interface 1 arbitration 1 */
+ __IO uint32_t IF1_ARB2; /*!< (@ 0x400E2034) Message interface 1 arbitration 2 */
+ __IO uint32_t IF1_MCTRL; /*!< (@ 0x400E2038) Message interface 1 message control */
+ __IO uint32_t IF1_DA1; /*!< (@ 0x400E203C) Message interface data A1 */
+ __IO uint32_t IF1_DA2; /*!< (@ 0x400E2040) Message interface 1 data A2 */
+ __IO uint32_t IF1_DB1; /*!< (@ 0x400E2044) Message interface 1 data B1 */
+ __IO uint32_t IF1_DB2; /*!< (@ 0x400E2048) Message interface 1 data B2 */
+ __I uint32_t RESERVED1[13];
+ __IO uint32_t IF2_CMDREQ; /*!< (@ 0x400E2080) Message interface command request */
+
+ union {
+ __IO uint32_t IF2_CMDMSK_R; /*!< (@ 0x400E2084) Message interface command mask (read direction) */
+ __IO uint32_t IF2_CMDMSK_W; /*!< (@ 0x400E2084) Message interface command mask (write direction) */
+ } ;
+ __IO uint32_t IF2_MSK1; /*!< (@ 0x400E2088) Message interface mask 1 */
+ __IO uint32_t IF2_MSK2; /*!< (@ 0x400E208C) Message interface 1 mask 2 */
+ __IO uint32_t IF2_ARB1; /*!< (@ 0x400E2090) Message interface 1 arbitration 1 */
+ __IO uint32_t IF2_ARB2; /*!< (@ 0x400E2094) Message interface 1 arbitration 2 */
+ __IO uint32_t IF2_MCTRL; /*!< (@ 0x400E2098) Message interface 1 message control */
+ __IO uint32_t IF2_DA1; /*!< (@ 0x400E209C) Message interface data A1 */
+ __IO uint32_t IF2_DA2; /*!< (@ 0x400E20A0) Message interface 1 data A2 */
+ __IO uint32_t IF2_DB1; /*!< (@ 0x400E20A4) Message interface 1 data B1 */
+ __IO uint32_t IF2_DB2; /*!< (@ 0x400E20A8) Message interface 1 data B2 */
+ __I uint32_t RESERVED2[21];
+ __I uint32_t TXREQ1; /*!< (@ 0x400E2100) Transmission request 1 */
+ __I uint32_t TXREQ2; /*!< (@ 0x400E2104) Transmission request 2 */
+ __I uint32_t RESERVED3[6];
+ __I uint32_t ND1; /*!< (@ 0x400E2120) New data 1 */
+ __I uint32_t ND2; /*!< (@ 0x400E2124) New data 2 */
+ __I uint32_t RESERVED4[6];
+ __I uint32_t IR1; /*!< (@ 0x400E2140) Interrupt pending 1 */
+ __I uint32_t IR2; /*!< (@ 0x400E2144) Interrupt pending 2 */
+ __I uint32_t RESERVED5[6];
+ __I uint32_t MSGV1; /*!< (@ 0x400E2160) Message valid 1 */
+ __I uint32_t MSGV2; /*!< (@ 0x400E2164) Message valid 2 */
+ __I uint32_t RESERVED6[6];
+ __IO uint32_t CLKDIV; /*!< (@ 0x400E2180) CAN clock divider register */
+} LPC_C_CANn_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- RITIMER -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx Repetitive Interrupt Timer (RIT) Modification date=1/14/2011 Major revision=0 Minor revision=7 (RITIMER)
+ */
+
+typedef struct { /*!< (@ 0x400C0000) RITIMER Structure */
+ __IO uint32_t COMPVAL; /*!< (@ 0x400C0000) Compare register */
+ __IO uint32_t MASK; /*!< (@ 0x400C0004) Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
+ __IO uint32_t CTRL; /*!< (@ 0x400C0008) Control register. */
+ __IO uint32_t COUNTER; /*!< (@ 0x400C000C) 32-bit counter */
+} LPC_RITIMER_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- QEI -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx Quadrature Encoder Interface (QEI) Modification date=1/18/2011 Major revision=0 Minor revision=7 (QEI)
+ */
+
+typedef struct { /*!< (@ 0x400C6000) QEI Structure */
+ __O uint32_t CON; /*!< (@ 0x400C6000) Control register */
+ __I uint32_t STAT; /*!< (@ 0x400C6004) Encoder status register */
+ __IO uint32_t CONF; /*!< (@ 0x400C6008) Configuration register */
+ __I uint32_t POS; /*!< (@ 0x400C600C) Position register */
+ __IO uint32_t MAXPOS; /*!< (@ 0x400C6010) Maximum position register */
+ __IO uint32_t CMPOS0; /*!< (@ 0x400C6014) position compare register 0 */
+ __IO uint32_t CMPOS1; /*!< (@ 0x400C6018) position compare register 1 */
+ __IO uint32_t CMPOS2; /*!< (@ 0x400C601C) position compare register 2 */
+ __I uint32_t INXCNT; /*!< (@ 0x400C6020) Index count register */
+ __IO uint32_t INXCMP0; /*!< (@ 0x400C6024) Index compare register 0 */
+ __IO uint32_t LOAD; /*!< (@ 0x400C6028) Velocity timer reload register */
+ __I uint32_t TIME; /*!< (@ 0x400C602C) Velocity timer register */
+ __I uint32_t VEL; /*!< (@ 0x400C6030) Velocity counter register */
+ __I uint32_t CAP; /*!< (@ 0x400C6034) Velocity capture register */
+ __IO uint32_t VELCOMP; /*!< (@ 0x400C6038) Velocity compare register */
+ __IO uint32_t FILTERPHA; /*!< (@ 0x400C603C) Digital filter register on input phase A (QEI_A) */
+ __IO uint32_t FILTERPHB; /*!< (@ 0x400C6040) Digital filter register on input phase B (QEI_B) */
+ __IO uint32_t FILTERINX; /*!< (@ 0x400C6044) Digital filter register on input index (QEI_IDX) */
+ __IO uint32_t WINDOW; /*!< (@ 0x400C6048) Index acceptance window register */
+ __IO uint32_t INXCMP1; /*!< (@ 0x400C604C) Index compare register 1 */
+ __IO uint32_t INXCMP2; /*!< (@ 0x400C6050) Index compare register 2 */
+ __I uint32_t RESERVED0[993];
+ __O uint32_t IEC; /*!< (@ 0x400C6FD8) Interrupt enable clear register */
+ __O uint32_t IES; /*!< (@ 0x400C6FDC) Interrupt enable set register */
+ __I uint32_t INTSTAT; /*!< (@ 0x400C6FE0) Interrupt status register */
+ __I uint32_t IE; /*!< (@ 0x400C6FE4) Interrupt enable register */
+ __O uint32_t CLR; /*!< (@ 0x400C6FE8) Interrupt status clear register */
+ __O uint32_t SET; /*!< (@ 0x400C6FEC) Interrupt status set register */
+} LPC_QEI_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GIMA -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10503 Chapter title=LPC43xx Global Input Multiplexer Array (GIMA) Modification date=10/7/2011 Major revision=0 Minor revision=3 (GIMA)
+ */
+
+typedef struct { /*!< (@ 0x400C7000) GIMA Structure */
+ __IO uint32_t CAP0_0_IN; /*!< (@ 0x400C7000) Timer 0 CAP0_0 capture input multiplexer (GIMA output 0) */
+ __IO uint32_t CAP0_1_IN; /*!< (@ 0x400C7004) Timer 0 CAP0_1 capture input multiplexer (GIMA output 1) */
+ __IO uint32_t CAP0_2_IN; /*!< (@ 0x400C7008) Timer 0 CAP0_2 capture input multiplexer (GIMA output 2) */
+ __IO uint32_t CAP0_3_IN; /*!< (@ 0x400C700C) Timer 0 CAP0_3 capture input multiplexer (GIMA output 3) */
+ __IO uint32_t CAP1_0_IN; /*!< (@ 0x400C7010) Timer 1 CAP1_0 capture input multiplexer (GIMA output 4) */
+ __IO uint32_t CAP1_1_IN; /*!< (@ 0x400C7014) Timer 1 CAP1_1 capture input multiplexer (GIMA output 5) */
+ __IO uint32_t CAP1_2_IN; /*!< (@ 0x400C7018) Timer 1 CAP1_2 capture input multiplexer (GIMA output 6) */
+ __IO uint32_t CAP1_3_IN; /*!< (@ 0x400C701C) Timer 1 CAP1_3 capture input multiplexer (GIMA output 7) */
+ __IO uint32_t CAP2_0_IN; /*!< (@ 0x400C7020) Timer 2 CAP2_0 capture input multiplexer (GIMA output 8) */
+ __IO uint32_t CAP2_1_IN; /*!< (@ 0x400C7024) Timer 2 CAP2_1 capture input multiplexer (GIMA output 9) */
+ __IO uint32_t CAP2_2_IN; /*!< (@ 0x400C7028) Timer 2 CAP2_2 capture input multiplexer (GIMA output 10) */
+ __IO uint32_t CAP2_3_IN; /*!< (@ 0x400C702C) Timer 2 CAP2_3 capture input multiplexer (GIMA output 11) */
+ __IO uint32_t CAP3_0_IN; /*!< (@ 0x400C7030) Timer 3 CAP3_0 capture input multiplexer (GIMA output 12) */
+ __IO uint32_t CAP3_1_IN; /*!< (@ 0x400C7034) Timer 3 CAP3_1 capture input multiplexer (GIMA output 13) */
+ __IO uint32_t CAP3_2_IN; /*!< (@ 0x400C7038) Timer 3 CAP3_2 capture input multiplexer (GIMA output 14) */
+ __IO uint32_t CAP3_3_IN; /*!< (@ 0x400C703C) Timer 3 CAP3_3 capture input multiplexer (GIMA output 15) */
+ __IO uint32_t CTIN_0_IN; /*!< (@ 0x400C7040) SCT CTIN_0 capture input multiplexer (GIMA output 16) */
+ __IO uint32_t CTIN_1_IN; /*!< (@ 0x400C7044) SCT CTIN_1 capture input multiplexer (GIMA output 17) */
+ __IO uint32_t CTIN_2_IN; /*!< (@ 0x400C7048) SCT CTIN_2 capture input multiplexer (GIMA output 18) */
+ __IO uint32_t CTIN_3_IN; /*!< (@ 0x400C704C) SCT CTIN_3 capture input multiplexer (GIMA output 19) */
+ __IO uint32_t CTIN_4_IN; /*!< (@ 0x400C7050) SCT CTIN_4 capture input multiplexer (GIMA output 20) */
+ __IO uint32_t CTIN_5_IN; /*!< (@ 0x400C7054) SCT CTIN_5 capture input multiplexer (GIMA output 21) */
+ __IO uint32_t CTIN_6_IN; /*!< (@ 0x400C7058) SCT CTIN_6 capture input multiplexer (GIMA output 22) */
+ __IO uint32_t CTIN_7_IN; /*!< (@ 0x400C705C) SCT CTIN_7 capture input multiplexer (GIMA output 23) */
+ __IO uint32_t VADC_TRIGGER_IN; /*!< (@ 0x400C7060) VADC trigger input multiplexer (GIMA output 24) */
+ __IO uint32_t EVENTROUTER_13_IN; /*!< (@ 0x400C7064) Event router input 13 multiplexer (GIMA output 25) */
+ __IO uint32_t EVENTROUTER_14_IN; /*!< (@ 0x400C7068) Event router input 14 multiplexer (GIMA output 26) */
+ __IO uint32_t EVENTROUTER_16_IN; /*!< (@ 0x400C706C) Event router input 16 multiplexer (GIMA output 27) */
+ __IO uint32_t ADCSTART0_IN; /*!< (@ 0x400C7070) ADC start0 input multiplexer (GIMA output 28) */
+ __IO uint32_t ADCSTART1_IN; /*!< (@ 0x400C7074) ADC start1 input multiplexer (GIMA output 29) */
+} LPC_GIMA_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- DAC -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx DAC Modification date=1/18/2011 Major revision=0 Minor revision=7 (DAC)
+ */
+
+typedef struct { /*!< (@ 0x400E1000) DAC Structure */
+ __IO uint32_t CR; /*!< (@ 0x400E1000) DAC register. Holds the conversion data. */
+ __IO uint32_t CTRL; /*!< (@ 0x400E1004) DAC control register. */
+ __IO uint32_t CNTVAL; /*!< (@ 0x400E1008) DAC counter value register. */
+} LPC_DAC_Type;
+
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- ADCn -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC18xx 10-bit ADC0/1 Modification date=1/18/2011 Major revision=0 Minor revision=7 (ADCn)
+ 0x400E3000 / 0x400E4000
+ */
+
+typedef struct { /*!< (@ 0x400Ex000) ADCn Structure */
+ __IO uint32_t CR; /*!< (@ 0x400Ex000) A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
+ __I uint32_t GDR; /*!< (@ 0x400Ex004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t INTEN; /*!< (@ 0x400Ex00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
+ __I uint32_t DR[8]; /*!< (@ 0x400Ex010) A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
+ __I uint32_t STAT; /*!< (@ 0x400Ex030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
+} LPC_ADCn_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- VADC -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM????? Chapter title=?????? Modification date=12/11/2012 Major revision=? Minor revision=? (VADC)
+ 0x400F0000
+ */
+
+typedef struct { /*!< (@ 0x400F0000) VADC Structure */
+ __O uint32_t FLUSH; /*!< (@ 0x400F0000) Flushes FIFO */
+ __IO uint32_t DMA_REQ; /*!< (@ 0x400F0004) Set or clear DMA write request */
+ __I uint32_t FIFO_STS; /*!< (@ 0x400F0008) Indicates FIFO fullness status */
+ __IO uint32_t FIFO_CFG; /*!< (@ 0x400F000C) Configures FIFO fullness level that triggers interrupt and packing 1 or 2 samples per word. */
+ __O uint32_t TRIGGER; /*!< (@ 0x400F0010) Enable software trigger to start descriptor processing */
+ __IO uint32_t DSCR_STS; /*!< (@ 0x400F0014) Indicates active descriptor table and descriptor entry */
+ __IO uint32_t POWER_DOWN; /*!< (@ 0x400F0018) Set or clear power down mode */
+ __IO uint32_t CONFIG; /*!< (@ 0x400F001C) Configures external trigger mode, store channel ID in FIFO and wakeup recovery time from power down. */
+ __IO uint32_t THR_A; /*!< (@ 0x400F0020) Configures window comparator A levels. */
+ __IO uint32_t THR_B; /*!< (@ 0x400F0024) Configures window comparator B levels. */
+ __I uint32_t LAST_SAMPLE[6]; /*!< (@ 0x400F0028) Contains last converted sample of input M [M=0..5) and result of window comparator. */
+ __I uint32_t RESERVED0[48];
+ __IO uint32_t ADC_DEBUG; /*!< (@ 0x400F0100) Reserved (ADC Debug pin inputs) */
+ __IO uint32_t ADC_SPEED; /*!< (@ 0x400F0104) ADC speed control */
+ __IO uint32_t POWER_CONTROL; /*!< (@ 0x400F0108) Configures ADC power vs. speed, DC-in biasing, output format and power gating. */
+ __I uint32_t RESERVED1[61];
+ __I uint32_t FIFO_OUTPUT[16]; /*!< (@ 0x400F0200 - 0x400F023C) FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples */
+ __I uint32_t RESERVED2[48];
+ __IO uint32_t DESCRIPTOR_0[8]; /*!< (@ 0x400F0300) Table0 descriptor n, n= 0 to 7 */
+ __IO uint32_t DESCRIPTOR_1[8]; /*!< (@ 0x400F0320) Table1 descriptor n, n= 0 to 7 */
+ __I uint32_t RESERVED3[752];
+ __O uint32_t CLR_EN0; /*!< (@ 0x400F0F00) Interrupt0 clear mask */
+ __O uint32_t SET_EN0; /*!< (@ 0x400F0F04) Interrupt0 set mask */
+ __I uint32_t MASK0; /*!< (@ 0x400F0F08) Interrupt0 mask */
+ __I uint32_t STATUS0; /*!< (@ 0x400F0F0C) Interrupt0 status. Interrupt0 contains FIFO fullness, descriptor status and ADC range under/overflow */
+ __O uint32_t CLR_STAT0; /*!< (@ 0x400F0F10) Interrupt0 clear status */
+ __O uint32_t SET_STAT0; /*!< (@ 0x400F0F14) Interrupt0 set status */
+ __I uint32_t RESERVED4[2];
+ __O uint32_t CLR_EN1; /*!< (@ 0x400F0F20) Interrupt1 mask clear enable. */
+ __O uint32_t SET_EN1; /*!< (@ 0x400F0F24) Interrupt1 mask set enable */
+ __I uint32_t MASK1; /*!< (@ 0x400F0F28) Interrupt1 mask */
+ __I uint32_t STATUS1; /*!< (@ 0x400F0F2C) Interrupt1 status. Interrupt1 contains window comparator results and register last LAST_SAMPLE[M] overrun. */
+ __O uint32_t CLR_STAT1; /*!< (@ 0x400F0F30) Interrupt1 clear status */
+ __O uint32_t SET_STAT1; /*!< (@ 0x400F0F34) Interrupt1 set status */
+} LPC_VADC_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_PORT -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief GPIO port (GPIO_PORT)
+ */
+
+typedef struct { /*!< (@ 0x400F4000) GPIO_PORT Structure */
+ __IO uint8_t B[256]; /*!< (@ 0x400F4000) Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31 */
+ __I uint32_t RESERVED0[960];
+ __IO uint32_t W[256]; /*!< (@ 0x400F5000) Word pin registers port 0 to 5 */
+ __I uint32_t RESERVED1[768];
+ __IO uint32_t DIR[8]; /*!< (@ 0x400F6000) Direction registers port n */
+ __I uint32_t RESERVED2[24];
+ __IO uint32_t MASK[8]; /*!< (@ 0x400F6080) Mask register port n */
+ __I uint32_t RESERVED3[24];
+ __IO uint32_t PIN[8]; /*!< (@ 0x400F6100) Portpin register port n */
+ __I uint32_t RESERVED4[24];
+ __IO uint32_t MPIN[8]; /*!< (@ 0x400F6180) Masked port register port n */
+ __I uint32_t RESERVED5[24];
+ __IO uint32_t SET[8]; /*!< (@ 0x400F6200) Write: Set register for port n Read: output bits for port n */
+ __I uint32_t RESERVED6[24];
+ __O uint32_t CLR[8]; /*!< (@ 0x400F6280) Clear port n */
+ __I uint32_t RESERVED7[24];
+ __O uint32_t NOT[8]; /*!< (@ 0x400F6300) Toggle port n */
+} LPC_GPIO_PORT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SPI -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10503 Chapter title=LPC43xxSPI Modification date=10/7/2011 Major revision=0 Minor revision=3 (SPI)
+ */
+
+typedef struct { /*!< (@ 0x40100000) SPI Structure */
+ __IO uint32_t CR; /*!< (@ 0x40100000) SPI Control Register. This register controls the operation of the SPI. */
+ __I uint32_t SR; /*!< (@ 0x40100004) SPI Status Register. This register shows the status of the SPI. */
+ __IO uint32_t DR; /*!< (@ 0x40100008) SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register. */
+ __IO uint32_t CCR; /*!< (@ 0x4010000C) SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */
+ __IO uint32_t TCR; /*!< (@ 0x40100010) SPI Test Control register. For functional testing only. */
+ __IO uint32_t TSR; /*!< (@ 0x40100014) SPI Test Status register. For functional testing only. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t INT; /*!< (@ 0x4010001C) SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */
+} LPC_SPI_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SGPIO -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10503 Chapter title=LPC43xx SerialGPIO (SGPIO) Modification date=10/7/2011 Major revision=0 Minor revision=3 (SGPIO)
+ */
+
+typedef struct { /*!< (@ 0x40101000) SGPIO Structure */
+ __IO uint32_t OUT_MUX_CFG[16]; /*!< (@ 0x40101000) Pin multiplexer configurationregisters. */
+ __IO uint32_t SGPIO_MUX_CFG[16]; /*!< (@ 0x40101040) SGPIO multiplexer configuration registers. */
+ __IO uint32_t SLICE_MUX_CFG[16]; /*!< (@ 0x40101080) Slice multiplexer configuration registers. */
+ __IO uint32_t REG[16]; /*!< (@ 0x401010C0) Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */
+ __IO uint32_t REG_SS[16]; /*!< (@ 0x40101100) Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */
+ __IO uint32_t PRESET[16]; /*!< (@ 0x40101140) Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */
+ __IO uint32_t COUNT[16]; /*!< (@ 0x40101180) Down counter, counts down each clock cycle. */
+ __IO uint32_t POS[16]; /*!< (@ 0x401011C0) Each time COUNT0 reaches 0x0 */
+ __IO uint32_t MASK_A; /*!< (@ 0x40101200) Mask for pattern match function of slice A */
+ __IO uint32_t MASK_H; /*!< (@ 0x40101204) Mask for pattern match function of slice H */
+ __IO uint32_t MASK_I; /*!< (@ 0x40101208) Mask for pattern match function of slice I */
+ __IO uint32_t MASK_P; /*!< (@ 0x4010120C) Mask for pattern match function of slice P */
+ __I uint32_t GPIO_INREG; /*!< (@ 0x40101210) GPIO input status register */
+ __IO uint32_t GPIO_OUTREG; /*!< (@ 0x40101214) GPIO output control register */
+ __IO uint32_t GPIO_OENREG; /*!< (@ 0x40101218) GPIO OE control register */
+ __IO uint32_t CTRL_ENABLED; /*!< (@ 0x4010121C) Enables the slice COUNT counter */
+ __IO uint32_t CTRL_DISABLED; /*!< (@ 0x40101220) Disables the slice COUNT counter */
+ __I uint32_t RESERVED0[823];
+ __O uint32_t CLR_EN_0; /*!< (@ 0x40101F00) Shift clock interrupt clear mask */
+ __O uint32_t SET_EN_0; /*!< (@ 0x40101F04) Shift clock interrupt set mask */
+ __I uint32_t ENABLE_0; /*!< (@ 0x40101F08) Shift clock interrupt enable */
+ __I uint32_t STATUS_0; /*!< (@ 0x40101F0C) Shift clock interrupt status */
+ __O uint32_t CTR_STATUS_0; /*!< (@ 0x40101F10) Shift clock interrupt clear status */
+ __O uint32_t SET_STATUS_0; /*!< (@ 0x40101F14) Shift clock interrupt set status */
+ __I uint32_t RESERVED1[2];
+ __O uint32_t CLR_EN_1; /*!< (@ 0x40101F20) Capture clock interrupt clear mask */
+ __O uint32_t SET_EN_1; /*!< (@ 0x40101F24) Capture clock interrupt set mask */
+ __I uint32_t ENABLE_1; /*!< (@ 0x40101F28) Capture clock interrupt enable */
+ __I uint32_t STATUS_1; /*!< (@ 0x40101F2C) Capture clock interrupt status */
+ __O uint32_t CTR_STATUS_1; /*!< (@ 0x40101F30) Capture clock interrupt clear status */
+ __O uint32_t SET_STATUS_1; /*!< (@ 0x40101F34) Capture clock interrupt set status */
+ __I uint32_t RESERVED2[2];
+ __O uint32_t CLR_EN_2; /*!< (@ 0x40101F40) Pattern match interrupt clear mask */
+ __O uint32_t SET_EN_2; /*!< (@ 0x40101F44) Pattern match interrupt set mask */
+ __I uint32_t ENABLE_2; /*!< (@ 0x40101F48) Pattern match interrupt enable */
+ __I uint32_t STATUS_2; /*!< (@ 0x40101F4C) Pattern match interrupt status */
+ __O uint32_t CTR_STATUS_2; /*!< (@ 0x40101F50) Pattern match interrupt clear status */
+ __O uint32_t SET_STATUS_2; /*!< (@ 0x40101F54) Pattern match interrupt set status */
+ __I uint32_t RESERVED3[2];
+ __O uint32_t CLR_EN_3; /*!< (@ 0x40101F60) Input interrupt clear mask */
+ __O uint32_t SET_EN_3; /*!< (@ 0x40101F64) Input bit match interrupt set mask */
+ __I uint32_t ENABLE_3; /*!< (@ 0x40101F68) Input bit match interrupt enable */
+ __I uint32_t STATUS_3; /*!< (@ 0x40101F6C) Input bit match interrupt status */
+ __O uint32_t CTR_STATUS_3; /*!< (@ 0x40101F70) Input bit match interrupt clear status */
+ __O uint32_t SET_STATUS_3; /*!< (@ 0x40101F74) Shift clock interrupt set status */
+} LPC_SGPIO_Type;
+
+
+
+/********************************************
+** End of section using anonymous unions **
+*********************************************/
+
+#if defined(__ARMCC_VERSION)
+ #pragma pop
+#elif defined(__CWCC__)
+ #pragma pop
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma pop
+#else
+ #error Not supported compiler type
+#endif
+
+
+#ifdef CMSIS_BITPOSITIONS
+// ------------------------------------------------------------------------------------------------
+// ----- SCT Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------- SCT_CONFIG -------------------------------------------
+#define SCT_CONFIG_UNIFY_Pos 0 /*!< SCT CONFIG: UNIFY Position */
+#define SCT_CONFIG_UNIFY_Msk (0x01UL << SCT_CONFIG_UNIFY_Pos) /*!< SCT CONFIG: UNIFY Mask */
+#define SCT_CONFIG_CLKMODE_Pos 1 /*!< SCT CONFIG: CLKMODE Position */
+#define SCT_CONFIG_CLKMODE_Msk (0x03UL << SCT_CONFIG_CLKMODE_Pos) /*!< SCT CONFIG: CLKMODE Mask */
+#define SCT_CONFIG_CLKSEL_Pos 3 /*!< SCT CONFIG: CLKSEL Position */
+#define SCT_CONFIG_CLKSEL_Msk (0x0fUL << SCT_CONFIG_CLKSEL_Pos) /*!< SCT CONFIG: CLKSEL Mask */
+#define SCT_CONFIG_NORELAODL_NORELOADU_Pos 7 /*!< SCT CONFIG: NORELAODL_NORELOADU Position */
+#define SCT_CONFIG_NORELAODL_NORELOADU_Msk (0x01UL << SCT_CONFIG_NORELAODL_NORELOADU_Pos) /*!< SCT CONFIG: NORELAODL_NORELOADU Mask */
+#define SCT_CONFIG_NORELOADH_Pos 8 /*!< SCT CONFIG: NORELOADH Position */
+#define SCT_CONFIG_NORELOADH_Msk (0x01UL << SCT_CONFIG_NORELOADH_Pos) /*!< SCT CONFIG: NORELOADH Mask */
+#define SCT_CONFIG_INSYNCn_Pos 9 /*!< SCT CONFIG: INSYNCn Position */
+#define SCT_CONFIG_INSYNCn_Msk (0x000000ffUL << SCT_CONFIG_INSYNCn_Pos) /*!< SCT CONFIG: INSYNCn Mask */
+
+// ---------------------------------------- SCT_CTRL --------------------------------------------
+#define SCT_CTRL_DOWN_L_Pos 0 /*!< SCT CTRL: DOWN_L Position */
+#define SCT_CTRL_DOWN_L_Msk (0x01UL << SCT_CTRL_DOWN_L_Pos) /*!< SCT CTRL: DOWN_L Mask */
+#define SCT_CTRL_STOP_L_Pos 1 /*!< SCT CTRL: STOP_L Position */
+#define SCT_CTRL_STOP_L_Msk (0x01UL << SCT_CTRL_STOP_L_Pos) /*!< SCT CTRL: STOP_L Mask */
+#define SCT_CTRL_HALT_L_Pos 2 /*!< SCT CTRL: HALT_L Position */
+#define SCT_CTRL_HALT_L_Msk (0x01UL << SCT_CTRL_HALT_L_Pos) /*!< SCT CTRL: HALT_L Mask */
+#define SCT_CTRL_CLRCTR_L_Pos 3 /*!< SCT CTRL: CLRCTR_L Position */
+#define SCT_CTRL_CLRCTR_L_Msk (0x01UL << SCT_CTRL_CLRCTR_L_Pos) /*!< SCT CTRL: CLRCTR_L Mask */
+#define SCT_CTRL_BIDIR_L_Pos 4 /*!< SCT CTRL: BIDIR_L Position */
+#define SCT_CTRL_BIDIR_L_Msk (0x01UL << SCT_CTRL_BIDIR_L_Pos) /*!< SCT CTRL: BIDIR_L Mask */
+#define SCT_CTRL_PRE_L_Pos 5 /*!< SCT CTRL: PRE_L Position */
+#define SCT_CTRL_PRE_L_Msk (0x000000ffUL << SCT_CTRL_PRE_L_Pos) /*!< SCT CTRL: PRE_L Mask */
+#define SCT_CTRL_DOWN_H_Pos 16 /*!< SCT CTRL: DOWN_H Position */
+#define SCT_CTRL_DOWN_H_Msk (0x01UL << SCT_CTRL_DOWN_H_Pos) /*!< SCT CTRL: DOWN_H Mask */
+#define SCT_CTRL_STOP_H_Pos 17 /*!< SCT CTRL: STOP_H Position */
+#define SCT_CTRL_STOP_H_Msk (0x01UL << SCT_CTRL_STOP_H_Pos) /*!< SCT CTRL: STOP_H Mask */
+#define SCT_CTRL_HALT_H_Pos 18 /*!< SCT CTRL: HALT_H Position */
+#define SCT_CTRL_HALT_H_Msk (0x01UL << SCT_CTRL_HALT_H_Pos) /*!< SCT CTRL: HALT_H Mask */
+#define SCT_CTRL_CLRCTR_H_Pos 19 /*!< SCT CTRL: CLRCTR_H Position */
+#define SCT_CTRL_CLRCTR_H_Msk (0x01UL << SCT_CTRL_CLRCTR_H_Pos) /*!< SCT CTRL: CLRCTR_H Mask */
+#define SCT_CTRL_BIDIR_H_Pos 20 /*!< SCT CTRL: BIDIR_H Position */
+#define SCT_CTRL_BIDIR_H_Msk (0x01UL << SCT_CTRL_BIDIR_H_Pos) /*!< SCT CTRL: BIDIR_H Mask */
+#define SCT_CTRL_PRE_H_Pos 21 /*!< SCT CTRL: PRE_H Position */
+#define SCT_CTRL_PRE_H_Msk (0x000000ffUL << SCT_CTRL_PRE_H_Pos) /*!< SCT CTRL: PRE_H Mask */
+
+// ---------------------------------------- SCT_LIMIT -------------------------------------------
+#define SCT_LIMIT_LIMMSK_L_Pos 0 /*!< SCT LIMIT: LIMMSK_L Position */
+#define SCT_LIMIT_LIMMSK_L_Msk (0x0000ffffUL << SCT_LIMIT_LIMMSK_L_Pos) /*!< SCT LIMIT: LIMMSK_L Mask */
+#define SCT_LIMIT_LIMMSK_H_Pos 16 /*!< SCT LIMIT: LIMMSK_H Position */
+#define SCT_LIMIT_LIMMSK_H_Msk (0x0000ffffUL << SCT_LIMIT_LIMMSK_H_Pos) /*!< SCT LIMIT: LIMMSK_H Mask */
+
+// ---------------------------------------- SCT_HALT --------------------------------------------
+#define SCT_HALT_HALTMSK_L_Pos 0 /*!< SCT HALT: HALTMSK_L Position */
+#define SCT_HALT_HALTMSK_L_Msk (0x0000ffffUL << SCT_HALT_HALTMSK_L_Pos) /*!< SCT HALT: HALTMSK_L Mask */
+#define SCT_HALT_HALTMSK_H_Pos 16 /*!< SCT HALT: HALTMSK_H Position */
+#define SCT_HALT_HALTMSK_H_Msk (0x0000ffffUL << SCT_HALT_HALTMSK_H_Pos) /*!< SCT HALT: HALTMSK_H Mask */
+
+// ---------------------------------------- SCT_STOP --------------------------------------------
+#define SCT_STOP_STOPMSK_L_Pos 0 /*!< SCT STOP: STOPMSK_L Position */
+#define SCT_STOP_STOPMSK_L_Msk (0x0000ffffUL << SCT_STOP_STOPMSK_L_Pos) /*!< SCT STOP: STOPMSK_L Mask */
+#define SCT_STOP_STOPMSK_H_Pos 16 /*!< SCT STOP: STOPMSK_H Position */
+#define SCT_STOP_STOPMSK_H_Msk (0x0000ffffUL << SCT_STOP_STOPMSK_H_Pos) /*!< SCT STOP: STOPMSK_H Mask */
+
+// ---------------------------------------- SCT_START -------------------------------------------
+#define SCT_START_STARTMSK_L_Pos 0 /*!< SCT START: STARTMSK_L Position */
+#define SCT_START_STARTMSK_L_Msk (0x0000ffffUL << SCT_START_STARTMSK_L_Pos) /*!< SCT START: STARTMSK_L Mask */
+#define SCT_START_STARTMSK_H_Pos 16 /*!< SCT START: STARTMSK_H Position */
+#define SCT_START_STARTMSK_H_Msk (0x0000ffffUL << SCT_START_STARTMSK_H_Pos) /*!< SCT START: STARTMSK_H Mask */
+
+// ---------------------------------------- SCT_COUNT -------------------------------------------
+#define SCT_COUNT_CTR_L_Pos 0 /*!< SCT COUNT: CTR_L Position */
+#define SCT_COUNT_CTR_L_Msk (0x0000ffffUL << SCT_COUNT_CTR_L_Pos) /*!< SCT COUNT: CTR_L Mask */
+#define SCT_COUNT_CTR_H_Pos 16 /*!< SCT COUNT: CTR_H Position */
+#define SCT_COUNT_CTR_H_Msk (0x0000ffffUL << SCT_COUNT_CTR_H_Pos) /*!< SCT COUNT: CTR_H Mask */
+
+// ---------------------------------------- SCT_STATE -------------------------------------------
+#define SCT_STATE_STATE_L_Pos 0 /*!< SCT STATE: STATE_L Position */
+#define SCT_STATE_STATE_L_Msk (0x1fUL << SCT_STATE_STATE_L_Pos) /*!< SCT STATE: STATE_L Mask */
+#define SCT_STATE_STATE_H_Pos 16 /*!< SCT STATE: STATE_H Position */
+#define SCT_STATE_STATE_H_Msk (0x1fUL << SCT_STATE_STATE_H_Pos) /*!< SCT STATE: STATE_H Mask */
+
+// ---------------------------------------- SCT_INPUT -------------------------------------------
+#define SCT_INPUT_AIN0_Pos 0 /*!< SCT INPUT: AIN0 Position */
+#define SCT_INPUT_AIN0_Msk (0x01UL << SCT_INPUT_AIN0_Pos) /*!< SCT INPUT: AIN0 Mask */
+#define SCT_INPUT_AIN1_Pos 1 /*!< SCT INPUT: AIN1 Position */
+#define SCT_INPUT_AIN1_Msk (0x01UL << SCT_INPUT_AIN1_Pos) /*!< SCT INPUT: AIN1 Mask */
+#define SCT_INPUT_AIN2_Pos 2 /*!< SCT INPUT: AIN2 Position */
+#define SCT_INPUT_AIN2_Msk (0x01UL << SCT_INPUT_AIN2_Pos) /*!< SCT INPUT: AIN2 Mask */
+#define SCT_INPUT_AIN3_Pos 3 /*!< SCT INPUT: AIN3 Position */
+#define SCT_INPUT_AIN3_Msk (0x01UL << SCT_INPUT_AIN3_Pos) /*!< SCT INPUT: AIN3 Mask */
+#define SCT_INPUT_AIN4_Pos 4 /*!< SCT INPUT: AIN4 Position */
+#define SCT_INPUT_AIN4_Msk (0x01UL << SCT_INPUT_AIN4_Pos) /*!< SCT INPUT: AIN4 Mask */
+#define SCT_INPUT_AIN5_Pos 5 /*!< SCT INPUT: AIN5 Position */
+#define SCT_INPUT_AIN5_Msk (0x01UL << SCT_INPUT_AIN5_Pos) /*!< SCT INPUT: AIN5 Mask */
+#define SCT_INPUT_AIN6_Pos 6 /*!< SCT INPUT: AIN6 Position */
+#define SCT_INPUT_AIN6_Msk (0x01UL << SCT_INPUT_AIN6_Pos) /*!< SCT INPUT: AIN6 Mask */
+#define SCT_INPUT_AIN7_Pos 7 /*!< SCT INPUT: AIN7 Position */
+#define SCT_INPUT_AIN7_Msk (0x01UL << SCT_INPUT_AIN7_Pos) /*!< SCT INPUT: AIN7 Mask */
+#define SCT_INPUT_SIN0_Pos 16 /*!< SCT INPUT: SIN0 Position */
+#define SCT_INPUT_SIN0_Msk (0x01UL << SCT_INPUT_SIN0_Pos) /*!< SCT INPUT: SIN0 Mask */
+#define SCT_INPUT_SIN1_Pos 17 /*!< SCT INPUT: SIN1 Position */
+#define SCT_INPUT_SIN1_Msk (0x01UL << SCT_INPUT_SIN1_Pos) /*!< SCT INPUT: SIN1 Mask */
+#define SCT_INPUT_SIN2_Pos 18 /*!< SCT INPUT: SIN2 Position */
+#define SCT_INPUT_SIN2_Msk (0x01UL << SCT_INPUT_SIN2_Pos) /*!< SCT INPUT: SIN2 Mask */
+#define SCT_INPUT_SIN3_Pos 19 /*!< SCT INPUT: SIN3 Position */
+#define SCT_INPUT_SIN3_Msk (0x01UL << SCT_INPUT_SIN3_Pos) /*!< SCT INPUT: SIN3 Mask */
+#define SCT_INPUT_SIN4_Pos 20 /*!< SCT INPUT: SIN4 Position */
+#define SCT_INPUT_SIN4_Msk (0x01UL << SCT_INPUT_SIN4_Pos) /*!< SCT INPUT: SIN4 Mask */
+#define SCT_INPUT_SIN5_Pos 21 /*!< SCT INPUT: SIN5 Position */
+#define SCT_INPUT_SIN5_Msk (0x01UL << SCT_INPUT_SIN5_Pos) /*!< SCT INPUT: SIN5 Mask */
+#define SCT_INPUT_SIN6_Pos 22 /*!< SCT INPUT: SIN6 Position */
+#define SCT_INPUT_SIN6_Msk (0x01UL << SCT_INPUT_SIN6_Pos) /*!< SCT INPUT: SIN6 Mask */
+#define SCT_INPUT_SIN7_Pos 23 /*!< SCT INPUT: SIN7 Position */
+#define SCT_INPUT_SIN7_Msk (0x01UL << SCT_INPUT_SIN7_Pos) /*!< SCT INPUT: SIN7 Mask */
+
+// --------------------------------------- SCT_REGMODE ------------------------------------------
+#define SCT_REGMODE_REGMOD_L0_Pos 0 /*!< SCT REGMODE: REGMOD_L0 Position */
+#define SCT_REGMODE_REGMOD_L0_Msk (0x01UL << SCT_REGMODE_REGMOD_L0_Pos) /*!< SCT REGMODE: REGMOD_L0 Mask */
+#define SCT_REGMODE_REGMOD_L1_Pos 1 /*!< SCT REGMODE: REGMOD_L1 Position */
+#define SCT_REGMODE_REGMOD_L1_Msk (0x01UL << SCT_REGMODE_REGMOD_L1_Pos) /*!< SCT REGMODE: REGMOD_L1 Mask */
+#define SCT_REGMODE_REGMOD_L2_Pos 2 /*!< SCT REGMODE: REGMOD_L2 Position */
+#define SCT_REGMODE_REGMOD_L2_Msk (0x01UL << SCT_REGMODE_REGMOD_L2_Pos) /*!< SCT REGMODE: REGMOD_L2 Mask */
+#define SCT_REGMODE_REGMOD_L3_Pos 3 /*!< SCT REGMODE: REGMOD_L3 Position */
+#define SCT_REGMODE_REGMOD_L3_Msk (0x01UL << SCT_REGMODE_REGMOD_L3_Pos) /*!< SCT REGMODE: REGMOD_L3 Mask */
+#define SCT_REGMODE_REGMOD_L4_Pos 4 /*!< SCT REGMODE: REGMOD_L4 Position */
+#define SCT_REGMODE_REGMOD_L4_Msk (0x01UL << SCT_REGMODE_REGMOD_L4_Pos) /*!< SCT REGMODE: REGMOD_L4 Mask */
+#define SCT_REGMODE_REGMOD_L5_Pos 5 /*!< SCT REGMODE: REGMOD_L5 Position */
+#define SCT_REGMODE_REGMOD_L5_Msk (0x01UL << SCT_REGMODE_REGMOD_L5_Pos) /*!< SCT REGMODE: REGMOD_L5 Mask */
+#define SCT_REGMODE_REGMOD_L6_Pos 6 /*!< SCT REGMODE: REGMOD_L6 Position */
+#define SCT_REGMODE_REGMOD_L6_Msk (0x01UL << SCT_REGMODE_REGMOD_L6_Pos) /*!< SCT REGMODE: REGMOD_L6 Mask */
+#define SCT_REGMODE_REGMOD_L7_Pos 7 /*!< SCT REGMODE: REGMOD_L7 Position */
+#define SCT_REGMODE_REGMOD_L7_Msk (0x01UL << SCT_REGMODE_REGMOD_L7_Pos) /*!< SCT REGMODE: REGMOD_L7 Mask */
+#define SCT_REGMODE_REGMOD_L8_Pos 8 /*!< SCT REGMODE: REGMOD_L8 Position */
+#define SCT_REGMODE_REGMOD_L8_Msk (0x01UL << SCT_REGMODE_REGMOD_L8_Pos) /*!< SCT REGMODE: REGMOD_L8 Mask */
+#define SCT_REGMODE_REGMOD_L9_Pos 9 /*!< SCT REGMODE: REGMOD_L9 Position */
+#define SCT_REGMODE_REGMOD_L9_Msk (0x01UL << SCT_REGMODE_REGMOD_L9_Pos) /*!< SCT REGMODE: REGMOD_L9 Mask */
+#define SCT_REGMODE_REGMOD_L10_Pos 10 /*!< SCT REGMODE: REGMOD_L10 Position */
+#define SCT_REGMODE_REGMOD_L10_Msk (0x01UL << SCT_REGMODE_REGMOD_L10_Pos) /*!< SCT REGMODE: REGMOD_L10 Mask */
+#define SCT_REGMODE_REGMOD_L11_Pos 11 /*!< SCT REGMODE: REGMOD_L11 Position */
+#define SCT_REGMODE_REGMOD_L11_Msk (0x01UL << SCT_REGMODE_REGMOD_L11_Pos) /*!< SCT REGMODE: REGMOD_L11 Mask */
+#define SCT_REGMODE_REGMOD_L12_Pos 12 /*!< SCT REGMODE: REGMOD_L12 Position */
+#define SCT_REGMODE_REGMOD_L12_Msk (0x01UL << SCT_REGMODE_REGMOD_L12_Pos) /*!< SCT REGMODE: REGMOD_L12 Mask */
+#define SCT_REGMODE_REGMOD_L13_Pos 13 /*!< SCT REGMODE: REGMOD_L13 Position */
+#define SCT_REGMODE_REGMOD_L13_Msk (0x01UL << SCT_REGMODE_REGMOD_L13_Pos) /*!< SCT REGMODE: REGMOD_L13 Mask */
+#define SCT_REGMODE_REGMOD_L14_Pos 14 /*!< SCT REGMODE: REGMOD_L14 Position */
+#define SCT_REGMODE_REGMOD_L14_Msk (0x01UL << SCT_REGMODE_REGMOD_L14_Pos) /*!< SCT REGMODE: REGMOD_L14 Mask */
+#define SCT_REGMODE_REGMOD_L15_Pos 15 /*!< SCT REGMODE: REGMOD_L15 Position */
+#define SCT_REGMODE_REGMOD_L15_Msk (0x01UL << SCT_REGMODE_REGMOD_L15_Pos) /*!< SCT REGMODE: REGMOD_L15 Mask */
+#define SCT_REGMODE_REGMOD_H16_Pos 16 /*!< SCT REGMODE: REGMOD_H16 Position */
+#define SCT_REGMODE_REGMOD_H16_Msk (0x01UL << SCT_REGMODE_REGMOD_H16_Pos) /*!< SCT REGMODE: REGMOD_H16 Mask */
+#define SCT_REGMODE_REGMOD_H17_Pos 17 /*!< SCT REGMODE: REGMOD_H17 Position */
+#define SCT_REGMODE_REGMOD_H17_Msk (0x01UL << SCT_REGMODE_REGMOD_H17_Pos) /*!< SCT REGMODE: REGMOD_H17 Mask */
+#define SCT_REGMODE_REGMOD_H18_Pos 18 /*!< SCT REGMODE: REGMOD_H18 Position */
+#define SCT_REGMODE_REGMOD_H18_Msk (0x01UL << SCT_REGMODE_REGMOD_H18_Pos) /*!< SCT REGMODE: REGMOD_H18 Mask */
+#define SCT_REGMODE_REGMOD_H19_Pos 19 /*!< SCT REGMODE: REGMOD_H19 Position */
+#define SCT_REGMODE_REGMOD_H19_Msk (0x01UL << SCT_REGMODE_REGMOD_H19_Pos) /*!< SCT REGMODE: REGMOD_H19 Mask */
+#define SCT_REGMODE_REGMOD_H20_Pos 20 /*!< SCT REGMODE: REGMOD_H20 Position */
+#define SCT_REGMODE_REGMOD_H20_Msk (0x01UL << SCT_REGMODE_REGMOD_H20_Pos) /*!< SCT REGMODE: REGMOD_H20 Mask */
+#define SCT_REGMODE_REGMOD_H21_Pos 21 /*!< SCT REGMODE: REGMOD_H21 Position */
+#define SCT_REGMODE_REGMOD_H21_Msk (0x01UL << SCT_REGMODE_REGMOD_H21_Pos) /*!< SCT REGMODE: REGMOD_H21 Mask */
+#define SCT_REGMODE_REGMOD_H22_Pos 22 /*!< SCT REGMODE: REGMOD_H22 Position */
+#define SCT_REGMODE_REGMOD_H22_Msk (0x01UL << SCT_REGMODE_REGMOD_H22_Pos) /*!< SCT REGMODE: REGMOD_H22 Mask */
+#define SCT_REGMODE_REGMOD_H23_Pos 23 /*!< SCT REGMODE: REGMOD_H23 Position */
+#define SCT_REGMODE_REGMOD_H23_Msk (0x01UL << SCT_REGMODE_REGMOD_H23_Pos) /*!< SCT REGMODE: REGMOD_H23 Mask */
+#define SCT_REGMODE_REGMOD_H24_Pos 24 /*!< SCT REGMODE: REGMOD_H24 Position */
+#define SCT_REGMODE_REGMOD_H24_Msk (0x01UL << SCT_REGMODE_REGMOD_H24_Pos) /*!< SCT REGMODE: REGMOD_H24 Mask */
+#define SCT_REGMODE_REGMOD_H25_Pos 25 /*!< SCT REGMODE: REGMOD_H25 Position */
+#define SCT_REGMODE_REGMOD_H25_Msk (0x01UL << SCT_REGMODE_REGMOD_H25_Pos) /*!< SCT REGMODE: REGMOD_H25 Mask */
+#define SCT_REGMODE_REGMOD_H26_Pos 26 /*!< SCT REGMODE: REGMOD_H26 Position */
+#define SCT_REGMODE_REGMOD_H26_Msk (0x01UL << SCT_REGMODE_REGMOD_H26_Pos) /*!< SCT REGMODE: REGMOD_H26 Mask */
+#define SCT_REGMODE_REGMOD_H27_Pos 27 /*!< SCT REGMODE: REGMOD_H27 Position */
+#define SCT_REGMODE_REGMOD_H27_Msk (0x01UL << SCT_REGMODE_REGMOD_H27_Pos) /*!< SCT REGMODE: REGMOD_H27 Mask */
+#define SCT_REGMODE_REGMOD_H28_Pos 28 /*!< SCT REGMODE: REGMOD_H28 Position */
+#define SCT_REGMODE_REGMOD_H28_Msk (0x01UL << SCT_REGMODE_REGMOD_H28_Pos) /*!< SCT REGMODE: REGMOD_H28 Mask */
+#define SCT_REGMODE_REGMOD_H29_Pos 29 /*!< SCT REGMODE: REGMOD_H29 Position */
+#define SCT_REGMODE_REGMOD_H29_Msk (0x01UL << SCT_REGMODE_REGMOD_H29_Pos) /*!< SCT REGMODE: REGMOD_H29 Mask */
+#define SCT_REGMODE_REGMOD_H30_Pos 30 /*!< SCT REGMODE: REGMOD_H30 Position */
+#define SCT_REGMODE_REGMOD_H30_Msk (0x01UL << SCT_REGMODE_REGMOD_H30_Pos) /*!< SCT REGMODE: REGMOD_H30 Mask */
+#define SCT_REGMODE_REGMOD_H31_Pos 31 /*!< SCT REGMODE: REGMOD_H31 Position */
+#define SCT_REGMODE_REGMOD_H31_Msk (0x01UL << SCT_REGMODE_REGMOD_H31_Pos) /*!< SCT REGMODE: REGMOD_H31 Mask */
+
+// --------------------------------------- SCT_OUTPUT -------------------------------------------
+#define SCT_OUTPUT_OUT0_Pos 0 /*!< SCT OUTPUT: OUT0 Position */
+#define SCT_OUTPUT_OUT0_Msk (0x01UL << SCT_OUTPUT_OUT0_Pos) /*!< SCT OUTPUT: OUT0 Mask */
+#define SCT_OUTPUT_OUT1_Pos 1 /*!< SCT OUTPUT: OUT1 Position */
+#define SCT_OUTPUT_OUT1_Msk (0x01UL << SCT_OUTPUT_OUT1_Pos) /*!< SCT OUTPUT: OUT1 Mask */
+#define SCT_OUTPUT_OUT2_Pos 2 /*!< SCT OUTPUT: OUT2 Position */
+#define SCT_OUTPUT_OUT2_Msk (0x01UL << SCT_OUTPUT_OUT2_Pos) /*!< SCT OUTPUT: OUT2 Mask */
+#define SCT_OUTPUT_OUT3_Pos 3 /*!< SCT OUTPUT: OUT3 Position */
+#define SCT_OUTPUT_OUT3_Msk (0x01UL << SCT_OUTPUT_OUT3_Pos) /*!< SCT OUTPUT: OUT3 Mask */
+#define SCT_OUTPUT_OUT4_Pos 4 /*!< SCT OUTPUT: OUT4 Position */
+#define SCT_OUTPUT_OUT4_Msk (0x01UL << SCT_OUTPUT_OUT4_Pos) /*!< SCT OUTPUT: OUT4 Mask */
+#define SCT_OUTPUT_OUT5_Pos 5 /*!< SCT OUTPUT: OUT5 Position */
+#define SCT_OUTPUT_OUT5_Msk (0x01UL << SCT_OUTPUT_OUT5_Pos) /*!< SCT OUTPUT: OUT5 Mask */
+#define SCT_OUTPUT_OUT6_Pos 6 /*!< SCT OUTPUT: OUT6 Position */
+#define SCT_OUTPUT_OUT6_Msk (0x01UL << SCT_OUTPUT_OUT6_Pos) /*!< SCT OUTPUT: OUT6 Mask */
+#define SCT_OUTPUT_OUT7_Pos 7 /*!< SCT OUTPUT: OUT7 Position */
+#define SCT_OUTPUT_OUT7_Msk (0x01UL << SCT_OUTPUT_OUT7_Pos) /*!< SCT OUTPUT: OUT7 Mask */
+#define SCT_OUTPUT_OUT8_Pos 8 /*!< SCT OUTPUT: OUT8 Position */
+#define SCT_OUTPUT_OUT8_Msk (0x01UL << SCT_OUTPUT_OUT8_Pos) /*!< SCT OUTPUT: OUT8 Mask */
+#define SCT_OUTPUT_OUT9_Pos 9 /*!< SCT OUTPUT: OUT9 Position */
+#define SCT_OUTPUT_OUT9_Msk (0x01UL << SCT_OUTPUT_OUT9_Pos) /*!< SCT OUTPUT: OUT9 Mask */
+#define SCT_OUTPUT_OUT10_Pos 10 /*!< SCT OUTPUT: OUT10 Position */
+#define SCT_OUTPUT_OUT10_Msk (0x01UL << SCT_OUTPUT_OUT10_Pos) /*!< SCT OUTPUT: OUT10 Mask */
+#define SCT_OUTPUT_OUT11_Pos 11 /*!< SCT OUTPUT: OUT11 Position */
+#define SCT_OUTPUT_OUT11_Msk (0x01UL << SCT_OUTPUT_OUT11_Pos) /*!< SCT OUTPUT: OUT11 Mask */
+#define SCT_OUTPUT_OUT12_Pos 12 /*!< SCT OUTPUT: OUT12 Position */
+#define SCT_OUTPUT_OUT12_Msk (0x01UL << SCT_OUTPUT_OUT12_Pos) /*!< SCT OUTPUT: OUT12 Mask */
+#define SCT_OUTPUT_OUT13_Pos 13 /*!< SCT OUTPUT: OUT13 Position */
+#define SCT_OUTPUT_OUT13_Msk (0x01UL << SCT_OUTPUT_OUT13_Pos) /*!< SCT OUTPUT: OUT13 Mask */
+#define SCT_OUTPUT_OUT14_Pos 14 /*!< SCT OUTPUT: OUT14 Position */
+#define SCT_OUTPUT_OUT14_Msk (0x01UL << SCT_OUTPUT_OUT14_Pos) /*!< SCT OUTPUT: OUT14 Mask */
+#define SCT_OUTPUT_OUT15_Pos 15 /*!< SCT OUTPUT: OUT15 Position */
+#define SCT_OUTPUT_OUT15_Msk (0x01UL << SCT_OUTPUT_OUT15_Pos) /*!< SCT OUTPUT: OUT15 Mask */
+
+// ------------------------------------ SCT_OUTPUTDIRCTRL ---------------------------------------
+#define SCT_OUTPUTDIRCTRL_SETCLR0_Pos 0 /*!< SCT OUTPUTDIRCTRL: SETCLR0 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR0_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR0_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR0 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR1_Pos 2 /*!< SCT OUTPUTDIRCTRL: SETCLR1 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR1_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR1_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR1 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR2_Pos 4 /*!< SCT OUTPUTDIRCTRL: SETCLR2 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR2_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR2_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR2 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR3_Pos 6 /*!< SCT OUTPUTDIRCTRL: SETCLR3 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR3_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR3_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR3 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR4_Pos 8 /*!< SCT OUTPUTDIRCTRL: SETCLR4 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR4_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR4_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR4 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR5_Pos 10 /*!< SCT OUTPUTDIRCTRL: SETCLR5 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR5_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR5_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR5 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR6_Pos 12 /*!< SCT OUTPUTDIRCTRL: SETCLR6 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR6_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR6_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR6 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR7_Pos 14 /*!< SCT OUTPUTDIRCTRL: SETCLR7 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR7_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR7_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR7 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR8_Pos 16 /*!< SCT OUTPUTDIRCTRL: SETCLR8 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR8_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR8_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR8 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR9_Pos 18 /*!< SCT OUTPUTDIRCTRL: SETCLR9 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR9_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR9_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR9 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR10_Pos 20 /*!< SCT OUTPUTDIRCTRL: SETCLR10 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR10_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR10_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR10 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR11_Pos 22 /*!< SCT OUTPUTDIRCTRL: SETCLR11 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR11_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR11_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR11 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR12_Pos 24 /*!< SCT OUTPUTDIRCTRL: SETCLR12 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR12_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR12_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR12 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR13_Pos 26 /*!< SCT OUTPUTDIRCTRL: SETCLR13 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR13_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR13_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR13 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR14_Pos 28 /*!< SCT OUTPUTDIRCTRL: SETCLR14 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR14_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR14_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR14 Mask */
+#define SCT_OUTPUTDIRCTRL_SETCLR15_Pos 30 /*!< SCT OUTPUTDIRCTRL: SETCLR15 Position */
+#define SCT_OUTPUTDIRCTRL_SETCLR15_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR15_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR15 Mask */
+
+// ----------------------------------------- SCT_RES --------------------------------------------
+#define SCT_RES_O0RES_Pos 0 /*!< SCT RES: O0RES Position */
+#define SCT_RES_O0RES_Msk (0x03UL << SCT_RES_O0RES_Pos) /*!< SCT RES: O0RES Mask */
+#define SCT_RES_O1RES_Pos 2 /*!< SCT RES: O1RES Position */
+#define SCT_RES_O1RES_Msk (0x03UL << SCT_RES_O1RES_Pos) /*!< SCT RES: O1RES Mask */
+#define SCT_RES_O2RES_Pos 4 /*!< SCT RES: O2RES Position */
+#define SCT_RES_O2RES_Msk (0x03UL << SCT_RES_O2RES_Pos) /*!< SCT RES: O2RES Mask */
+#define SCT_RES_O3RES_Pos 6 /*!< SCT RES: O3RES Position */
+#define SCT_RES_O3RES_Msk (0x03UL << SCT_RES_O3RES_Pos) /*!< SCT RES: O3RES Mask */
+#define SCT_RES_O4RES_Pos 8 /*!< SCT RES: O4RES Position */
+#define SCT_RES_O4RES_Msk (0x03UL << SCT_RES_O4RES_Pos) /*!< SCT RES: O4RES Mask */
+#define SCT_RES_O5RES_Pos 10 /*!< SCT RES: O5RES Position */
+#define SCT_RES_O5RES_Msk (0x03UL << SCT_RES_O5RES_Pos) /*!< SCT RES: O5RES Mask */
+#define SCT_RES_O6RES_Pos 12 /*!< SCT RES: O6RES Position */
+#define SCT_RES_O6RES_Msk (0x03UL << SCT_RES_O6RES_Pos) /*!< SCT RES: O6RES Mask */
+#define SCT_RES_O7RES_Pos 14 /*!< SCT RES: O7RES Position */
+#define SCT_RES_O7RES_Msk (0x03UL << SCT_RES_O7RES_Pos) /*!< SCT RES: O7RES Mask */
+#define SCT_RES_O8RES_Pos 16 /*!< SCT RES: O8RES Position */
+#define SCT_RES_O8RES_Msk (0x03UL << SCT_RES_O8RES_Pos) /*!< SCT RES: O8RES Mask */
+#define SCT_RES_O9RES_Pos 18 /*!< SCT RES: O9RES Position */
+#define SCT_RES_O9RES_Msk (0x03UL << SCT_RES_O9RES_Pos) /*!< SCT RES: O9RES Mask */
+#define SCT_RES_O10RES_Pos 20 /*!< SCT RES: O10RES Position */
+#define SCT_RES_O10RES_Msk (0x03UL << SCT_RES_O10RES_Pos) /*!< SCT RES: O10RES Mask */
+#define SCT_RES_O11RES_Pos 22 /*!< SCT RES: O11RES Position */
+#define SCT_RES_O11RES_Msk (0x03UL << SCT_RES_O11RES_Pos) /*!< SCT RES: O11RES Mask */
+#define SCT_RES_O12RES_Pos 24 /*!< SCT RES: O12RES Position */
+#define SCT_RES_O12RES_Msk (0x03UL << SCT_RES_O12RES_Pos) /*!< SCT RES: O12RES Mask */
+#define SCT_RES_O13RES_Pos 26 /*!< SCT RES: O13RES Position */
+#define SCT_RES_O13RES_Msk (0x03UL << SCT_RES_O13RES_Pos) /*!< SCT RES: O13RES Mask */
+#define SCT_RES_O14RES_Pos 28 /*!< SCT RES: O14RES Position */
+#define SCT_RES_O14RES_Msk (0x03UL << SCT_RES_O14RES_Pos) /*!< SCT RES: O14RES Mask */
+#define SCT_RES_O15RES_Pos 30 /*!< SCT RES: O15RES Position */
+#define SCT_RES_O15RES_Msk (0x03UL << SCT_RES_O15RES_Pos) /*!< SCT RES: O15RES Mask */
+
+// --------------------------------------- SCT_DMAREQ0 ------------------------------------------
+#define SCT_DMAREQ0_DEV_0_0_Pos 0 /*!< SCT DMAREQ0: DEV_0_0 Position */
+#define SCT_DMAREQ0_DEV_0_0_Msk (0x01UL << SCT_DMAREQ0_DEV_0_0_Pos) /*!< SCT DMAREQ0: DEV_0_0 Mask */
+#define SCT_DMAREQ0_DEV_0_1_Pos 1 /*!< SCT DMAREQ0: DEV_0_1 Position */
+#define SCT_DMAREQ0_DEV_0_1_Msk (0x01UL << SCT_DMAREQ0_DEV_0_1_Pos) /*!< SCT DMAREQ0: DEV_0_1 Mask */
+#define SCT_DMAREQ0_DEV_0_2_Pos 2 /*!< SCT DMAREQ0: DEV_0_2 Position */
+#define SCT_DMAREQ0_DEV_0_2_Msk (0x01UL << SCT_DMAREQ0_DEV_0_2_Pos) /*!< SCT DMAREQ0: DEV_0_2 Mask */
+#define SCT_DMAREQ0_DEV_0_3_Pos 3 /*!< SCT DMAREQ0: DEV_0_3 Position */
+#define SCT_DMAREQ0_DEV_0_3_Msk (0x01UL << SCT_DMAREQ0_DEV_0_3_Pos) /*!< SCT DMAREQ0: DEV_0_3 Mask */
+#define SCT_DMAREQ0_DEV_0_4_Pos 4 /*!< SCT DMAREQ0: DEV_0_4 Position */
+#define SCT_DMAREQ0_DEV_0_4_Msk (0x01UL << SCT_DMAREQ0_DEV_0_4_Pos) /*!< SCT DMAREQ0: DEV_0_4 Mask */
+#define SCT_DMAREQ0_DEV_0_5_Pos 5 /*!< SCT DMAREQ0: DEV_0_5 Position */
+#define SCT_DMAREQ0_DEV_0_5_Msk (0x01UL << SCT_DMAREQ0_DEV_0_5_Pos) /*!< SCT DMAREQ0: DEV_0_5 Mask */
+#define SCT_DMAREQ0_DEV_0_6_Pos 6 /*!< SCT DMAREQ0: DEV_0_6 Position */
+#define SCT_DMAREQ0_DEV_0_6_Msk (0x01UL << SCT_DMAREQ0_DEV_0_6_Pos) /*!< SCT DMAREQ0: DEV_0_6 Mask */
+#define SCT_DMAREQ0_DEV_0_7_Pos 7 /*!< SCT DMAREQ0: DEV_0_7 Position */
+#define SCT_DMAREQ0_DEV_0_7_Msk (0x01UL << SCT_DMAREQ0_DEV_0_7_Pos) /*!< SCT DMAREQ0: DEV_0_7 Mask */
+#define SCT_DMAREQ0_DEV_0_8_Pos 8 /*!< SCT DMAREQ0: DEV_0_8 Position */
+#define SCT_DMAREQ0_DEV_0_8_Msk (0x01UL << SCT_DMAREQ0_DEV_0_8_Pos) /*!< SCT DMAREQ0: DEV_0_8 Mask */
+#define SCT_DMAREQ0_DEV_0_9_Pos 9 /*!< SCT DMAREQ0: DEV_0_9 Position */
+#define SCT_DMAREQ0_DEV_0_9_Msk (0x01UL << SCT_DMAREQ0_DEV_0_9_Pos) /*!< SCT DMAREQ0: DEV_0_9 Mask */
+#define SCT_DMAREQ0_DEV_0_10_Pos 10 /*!< SCT DMAREQ0: DEV_0_10 Position */
+#define SCT_DMAREQ0_DEV_0_10_Msk (0x01UL << SCT_DMAREQ0_DEV_0_10_Pos) /*!< SCT DMAREQ0: DEV_0_10 Mask */
+#define SCT_DMAREQ0_DEV_0_11_Pos 11 /*!< SCT DMAREQ0: DEV_0_11 Position */
+#define SCT_DMAREQ0_DEV_0_11_Msk (0x01UL << SCT_DMAREQ0_DEV_0_11_Pos) /*!< SCT DMAREQ0: DEV_0_11 Mask */
+#define SCT_DMAREQ0_DEV_0_12_Pos 12 /*!< SCT DMAREQ0: DEV_0_12 Position */
+#define SCT_DMAREQ0_DEV_0_12_Msk (0x01UL << SCT_DMAREQ0_DEV_0_12_Pos) /*!< SCT DMAREQ0: DEV_0_12 Mask */
+#define SCT_DMAREQ0_DEV_0_13_Pos 13 /*!< SCT DMAREQ0: DEV_0_13 Position */
+#define SCT_DMAREQ0_DEV_0_13_Msk (0x01UL << SCT_DMAREQ0_DEV_0_13_Pos) /*!< SCT DMAREQ0: DEV_0_13 Mask */
+#define SCT_DMAREQ0_DEV_0_14_Pos 14 /*!< SCT DMAREQ0: DEV_0_14 Position */
+#define SCT_DMAREQ0_DEV_0_14_Msk (0x01UL << SCT_DMAREQ0_DEV_0_14_Pos) /*!< SCT DMAREQ0: DEV_0_14 Mask */
+#define SCT_DMAREQ0_DEV_0_15_Pos 15 /*!< SCT DMAREQ0: DEV_0_15 Position */
+#define SCT_DMAREQ0_DEV_0_15_Msk (0x01UL << SCT_DMAREQ0_DEV_0_15_Pos) /*!< SCT DMAREQ0: DEV_0_15 Mask */
+#define SCT_DMAREQ0_DRL0_Pos 30 /*!< SCT DMAREQ0: DRL0 Position */
+#define SCT_DMAREQ0_DRL0_Msk (0x01UL << SCT_DMAREQ0_DRL0_Pos) /*!< SCT DMAREQ0: DRL0 Mask */
+#define SCT_DMAREQ0_DRQ0_Pos 31 /*!< SCT DMAREQ0: DRQ0 Position */
+#define SCT_DMAREQ0_DRQ0_Msk (0x01UL << SCT_DMAREQ0_DRQ0_Pos) /*!< SCT DMAREQ0: DRQ0 Mask */
+
+// --------------------------------------- SCT_DMAREQ1 ------------------------------------------
+#define SCT_DMAREQ1_DEV_1_0_Pos 0 /*!< SCT DMAREQ1: DEV_1_0 Position */
+#define SCT_DMAREQ1_DEV_1_0_Msk (0x01UL << SCT_DMAREQ1_DEV_1_0_Pos) /*!< SCT DMAREQ1: DEV_1_0 Mask */
+#define SCT_DMAREQ1_DEV_1_1_Pos 1 /*!< SCT DMAREQ1: DEV_1_1 Position */
+#define SCT_DMAREQ1_DEV_1_1_Msk (0x01UL << SCT_DMAREQ1_DEV_1_1_Pos) /*!< SCT DMAREQ1: DEV_1_1 Mask */
+#define SCT_DMAREQ1_DEV_1_2_Pos 2 /*!< SCT DMAREQ1: DEV_1_2 Position */
+#define SCT_DMAREQ1_DEV_1_2_Msk (0x01UL << SCT_DMAREQ1_DEV_1_2_Pos) /*!< SCT DMAREQ1: DEV_1_2 Mask */
+#define SCT_DMAREQ1_DEV_1_3_Pos 3 /*!< SCT DMAREQ1: DEV_1_3 Position */
+#define SCT_DMAREQ1_DEV_1_3_Msk (0x01UL << SCT_DMAREQ1_DEV_1_3_Pos) /*!< SCT DMAREQ1: DEV_1_3 Mask */
+#define SCT_DMAREQ1_DEV_1_4_Pos 4 /*!< SCT DMAREQ1: DEV_1_4 Position */
+#define SCT_DMAREQ1_DEV_1_4_Msk (0x01UL << SCT_DMAREQ1_DEV_1_4_Pos) /*!< SCT DMAREQ1: DEV_1_4 Mask */
+#define SCT_DMAREQ1_DEV_1_5_Pos 5 /*!< SCT DMAREQ1: DEV_1_5 Position */
+#define SCT_DMAREQ1_DEV_1_5_Msk (0x01UL << SCT_DMAREQ1_DEV_1_5_Pos) /*!< SCT DMAREQ1: DEV_1_5 Mask */
+#define SCT_DMAREQ1_DEV_1_6_Pos 6 /*!< SCT DMAREQ1: DEV_1_6 Position */
+#define SCT_DMAREQ1_DEV_1_6_Msk (0x01UL << SCT_DMAREQ1_DEV_1_6_Pos) /*!< SCT DMAREQ1: DEV_1_6 Mask */
+#define SCT_DMAREQ1_DEV_1_7_Pos 7 /*!< SCT DMAREQ1: DEV_1_7 Position */
+#define SCT_DMAREQ1_DEV_1_7_Msk (0x01UL << SCT_DMAREQ1_DEV_1_7_Pos) /*!< SCT DMAREQ1: DEV_1_7 Mask */
+#define SCT_DMAREQ1_DEV_1_8_Pos 8 /*!< SCT DMAREQ1: DEV_1_8 Position */
+#define SCT_DMAREQ1_DEV_1_8_Msk (0x01UL << SCT_DMAREQ1_DEV_1_8_Pos) /*!< SCT DMAREQ1: DEV_1_8 Mask */
+#define SCT_DMAREQ1_DEV_1_9_Pos 9 /*!< SCT DMAREQ1: DEV_1_9 Position */
+#define SCT_DMAREQ1_DEV_1_9_Msk (0x01UL << SCT_DMAREQ1_DEV_1_9_Pos) /*!< SCT DMAREQ1: DEV_1_9 Mask */
+#define SCT_DMAREQ1_DEV_1_10_Pos 10 /*!< SCT DMAREQ1: DEV_1_10 Position */
+#define SCT_DMAREQ1_DEV_1_10_Msk (0x01UL << SCT_DMAREQ1_DEV_1_10_Pos) /*!< SCT DMAREQ1: DEV_1_10 Mask */
+#define SCT_DMAREQ1_DEV_1_11_Pos 11 /*!< SCT DMAREQ1: DEV_1_11 Position */
+#define SCT_DMAREQ1_DEV_1_11_Msk (0x01UL << SCT_DMAREQ1_DEV_1_11_Pos) /*!< SCT DMAREQ1: DEV_1_11 Mask */
+#define SCT_DMAREQ1_DEV_1_12_Pos 12 /*!< SCT DMAREQ1: DEV_1_12 Position */
+#define SCT_DMAREQ1_DEV_1_12_Msk (0x01UL << SCT_DMAREQ1_DEV_1_12_Pos) /*!< SCT DMAREQ1: DEV_1_12 Mask */
+#define SCT_DMAREQ1_DEV_1_13_Pos 13 /*!< SCT DMAREQ1: DEV_1_13 Position */
+#define SCT_DMAREQ1_DEV_1_13_Msk (0x01UL << SCT_DMAREQ1_DEV_1_13_Pos) /*!< SCT DMAREQ1: DEV_1_13 Mask */
+#define SCT_DMAREQ1_DEV_1_14_Pos 14 /*!< SCT DMAREQ1: DEV_1_14 Position */
+#define SCT_DMAREQ1_DEV_1_14_Msk (0x01UL << SCT_DMAREQ1_DEV_1_14_Pos) /*!< SCT DMAREQ1: DEV_1_14 Mask */
+#define SCT_DMAREQ1_DEV_1_15_Pos 15 /*!< SCT DMAREQ1: DEV_1_15 Position */
+#define SCT_DMAREQ1_DEV_1_15_Msk (0x01UL << SCT_DMAREQ1_DEV_1_15_Pos) /*!< SCT DMAREQ1: DEV_1_15 Mask */
+#define SCT_DMAREQ1_DRL1_Pos 30 /*!< SCT DMAREQ1: DRL1 Position */
+#define SCT_DMAREQ1_DRL1_Msk (0x01UL << SCT_DMAREQ1_DRL1_Pos) /*!< SCT DMAREQ1: DRL1 Mask */
+#define SCT_DMAREQ1_DRQ1_Pos 31 /*!< SCT DMAREQ1: DRQ1 Position */
+#define SCT_DMAREQ1_DRQ1_Msk (0x01UL << SCT_DMAREQ1_DRQ1_Pos) /*!< SCT DMAREQ1: DRQ1 Mask */
+
+// ---------------------------------------- SCT_EVEN --------------------------------------------
+#define SCT_EVEN_IEN0_Pos 0 /*!< SCT EVEN: IEN0 Position */
+#define SCT_EVEN_IEN0_Msk (0x01UL << SCT_EVEN_IEN0_Pos) /*!< SCT EVEN: IEN0 Mask */
+#define SCT_EVEN_IEN1_Pos 1 /*!< SCT EVEN: IEN1 Position */
+#define SCT_EVEN_IEN1_Msk (0x01UL << SCT_EVEN_IEN1_Pos) /*!< SCT EVEN: IEN1 Mask */
+#define SCT_EVEN_IEN2_Pos 2 /*!< SCT EVEN: IEN2 Position */
+#define SCT_EVEN_IEN2_Msk (0x01UL << SCT_EVEN_IEN2_Pos) /*!< SCT EVEN: IEN2 Mask */
+#define SCT_EVEN_IEN3_Pos 3 /*!< SCT EVEN: IEN3 Position */
+#define SCT_EVEN_IEN3_Msk (0x01UL << SCT_EVEN_IEN3_Pos) /*!< SCT EVEN: IEN3 Mask */
+#define SCT_EVEN_IEN4_Pos 4 /*!< SCT EVEN: IEN4 Position */
+#define SCT_EVEN_IEN4_Msk (0x01UL << SCT_EVEN_IEN4_Pos) /*!< SCT EVEN: IEN4 Mask */
+#define SCT_EVEN_IEN5_Pos 5 /*!< SCT EVEN: IEN5 Position */
+#define SCT_EVEN_IEN5_Msk (0x01UL << SCT_EVEN_IEN5_Pos) /*!< SCT EVEN: IEN5 Mask */
+#define SCT_EVEN_IEN6_Pos 6 /*!< SCT EVEN: IEN6 Position */
+#define SCT_EVEN_IEN6_Msk (0x01UL << SCT_EVEN_IEN6_Pos) /*!< SCT EVEN: IEN6 Mask */
+#define SCT_EVEN_IEN7_Pos 7 /*!< SCT EVEN: IEN7 Position */
+#define SCT_EVEN_IEN7_Msk (0x01UL << SCT_EVEN_IEN7_Pos) /*!< SCT EVEN: IEN7 Mask */
+#define SCT_EVEN_IEN8_Pos 8 /*!< SCT EVEN: IEN8 Position */
+#define SCT_EVEN_IEN8_Msk (0x01UL << SCT_EVEN_IEN8_Pos) /*!< SCT EVEN: IEN8 Mask */
+#define SCT_EVEN_IEN9_Pos 9 /*!< SCT EVEN: IEN9 Position */
+#define SCT_EVEN_IEN9_Msk (0x01UL << SCT_EVEN_IEN9_Pos) /*!< SCT EVEN: IEN9 Mask */
+#define SCT_EVEN_IEN10_Pos 10 /*!< SCT EVEN: IEN10 Position */
+#define SCT_EVEN_IEN10_Msk (0x01UL << SCT_EVEN_IEN10_Pos) /*!< SCT EVEN: IEN10 Mask */
+#define SCT_EVEN_IEN11_Pos 11 /*!< SCT EVEN: IEN11 Position */
+#define SCT_EVEN_IEN11_Msk (0x01UL << SCT_EVEN_IEN11_Pos) /*!< SCT EVEN: IEN11 Mask */
+#define SCT_EVEN_IEN12_Pos 12 /*!< SCT EVEN: IEN12 Position */
+#define SCT_EVEN_IEN12_Msk (0x01UL << SCT_EVEN_IEN12_Pos) /*!< SCT EVEN: IEN12 Mask */
+#define SCT_EVEN_IEN13_Pos 13 /*!< SCT EVEN: IEN13 Position */
+#define SCT_EVEN_IEN13_Msk (0x01UL << SCT_EVEN_IEN13_Pos) /*!< SCT EVEN: IEN13 Mask */
+#define SCT_EVEN_IEN14_Pos 14 /*!< SCT EVEN: IEN14 Position */
+#define SCT_EVEN_IEN14_Msk (0x01UL << SCT_EVEN_IEN14_Pos) /*!< SCT EVEN: IEN14 Mask */
+#define SCT_EVEN_IEN15_Pos 15 /*!< SCT EVEN: IEN15 Position */
+#define SCT_EVEN_IEN15_Msk (0x01UL << SCT_EVEN_IEN15_Pos) /*!< SCT EVEN: IEN15 Mask */
+
+// --------------------------------------- SCT_EVFLAG -------------------------------------------
+#define SCT_EVFLAG_FLAG0_Pos 0 /*!< SCT EVFLAG: FLAG0 Position */
+#define SCT_EVFLAG_FLAG0_Msk (0x01UL << SCT_EVFLAG_FLAG0_Pos) /*!< SCT EVFLAG: FLAG0 Mask */
+#define SCT_EVFLAG_FLAG1_Pos 1 /*!< SCT EVFLAG: FLAG1 Position */
+#define SCT_EVFLAG_FLAG1_Msk (0x01UL << SCT_EVFLAG_FLAG1_Pos) /*!< SCT EVFLAG: FLAG1 Mask */
+#define SCT_EVFLAG_FLAG2_Pos 2 /*!< SCT EVFLAG: FLAG2 Position */
+#define SCT_EVFLAG_FLAG2_Msk (0x01UL << SCT_EVFLAG_FLAG2_Pos) /*!< SCT EVFLAG: FLAG2 Mask */
+#define SCT_EVFLAG_FLAG3_Pos 3 /*!< SCT EVFLAG: FLAG3 Position */
+#define SCT_EVFLAG_FLAG3_Msk (0x01UL << SCT_EVFLAG_FLAG3_Pos) /*!< SCT EVFLAG: FLAG3 Mask */
+#define SCT_EVFLAG_FLAG4_Pos 4 /*!< SCT EVFLAG: FLAG4 Position */
+#define SCT_EVFLAG_FLAG4_Msk (0x01UL << SCT_EVFLAG_FLAG4_Pos) /*!< SCT EVFLAG: FLAG4 Mask */
+#define SCT_EVFLAG_FLAG5_Pos 5 /*!< SCT EVFLAG: FLAG5 Position */
+#define SCT_EVFLAG_FLAG5_Msk (0x01UL << SCT_EVFLAG_FLAG5_Pos) /*!< SCT EVFLAG: FLAG5 Mask */
+#define SCT_EVFLAG_FLAG6_Pos 6 /*!< SCT EVFLAG: FLAG6 Position */
+#define SCT_EVFLAG_FLAG6_Msk (0x01UL << SCT_EVFLAG_FLAG6_Pos) /*!< SCT EVFLAG: FLAG6 Mask */
+#define SCT_EVFLAG_FLAG7_Pos 7 /*!< SCT EVFLAG: FLAG7 Position */
+#define SCT_EVFLAG_FLAG7_Msk (0x01UL << SCT_EVFLAG_FLAG7_Pos) /*!< SCT EVFLAG: FLAG7 Mask */
+#define SCT_EVFLAG_FLAG8_Pos 8 /*!< SCT EVFLAG: FLAG8 Position */
+#define SCT_EVFLAG_FLAG8_Msk (0x01UL << SCT_EVFLAG_FLAG8_Pos) /*!< SCT EVFLAG: FLAG8 Mask */
+#define SCT_EVFLAG_FLAG9_Pos 9 /*!< SCT EVFLAG: FLAG9 Position */
+#define SCT_EVFLAG_FLAG9_Msk (0x01UL << SCT_EVFLAG_FLAG9_Pos) /*!< SCT EVFLAG: FLAG9 Mask */
+#define SCT_EVFLAG_FLAG10_Pos 10 /*!< SCT EVFLAG: FLAG10 Position */
+#define SCT_EVFLAG_FLAG10_Msk (0x01UL << SCT_EVFLAG_FLAG10_Pos) /*!< SCT EVFLAG: FLAG10 Mask */
+#define SCT_EVFLAG_FLAG11_Pos 11 /*!< SCT EVFLAG: FLAG11 Position */
+#define SCT_EVFLAG_FLAG11_Msk (0x01UL << SCT_EVFLAG_FLAG11_Pos) /*!< SCT EVFLAG: FLAG11 Mask */
+#define SCT_EVFLAG_FLAG12_Pos 12 /*!< SCT EVFLAG: FLAG12 Position */
+#define SCT_EVFLAG_FLAG12_Msk (0x01UL << SCT_EVFLAG_FLAG12_Pos) /*!< SCT EVFLAG: FLAG12 Mask */
+#define SCT_EVFLAG_FLAG13_Pos 13 /*!< SCT EVFLAG: FLAG13 Position */
+#define SCT_EVFLAG_FLAG13_Msk (0x01UL << SCT_EVFLAG_FLAG13_Pos) /*!< SCT EVFLAG: FLAG13 Mask */
+#define SCT_EVFLAG_FLAG14_Pos 14 /*!< SCT EVFLAG: FLAG14 Position */
+#define SCT_EVFLAG_FLAG14_Msk (0x01UL << SCT_EVFLAG_FLAG14_Pos) /*!< SCT EVFLAG: FLAG14 Mask */
+#define SCT_EVFLAG_FLAG15_Pos 15 /*!< SCT EVFLAG: FLAG15 Position */
+#define SCT_EVFLAG_FLAG15_Msk (0x01UL << SCT_EVFLAG_FLAG15_Pos) /*!< SCT EVFLAG: FLAG15 Mask */
+
+// ---------------------------------------- SCT_CONEN -------------------------------------------
+#define SCT_CONEN_NCEN0_Pos 0 /*!< SCT CONEN: NCEN0 Position */
+#define SCT_CONEN_NCEN0_Msk (0x01UL << SCT_CONEN_NCEN0_Pos) /*!< SCT CONEN: NCEN0 Mask */
+#define SCT_CONEN_NCEN1_Pos 1 /*!< SCT CONEN: NCEN1 Position */
+#define SCT_CONEN_NCEN1_Msk (0x01UL << SCT_CONEN_NCEN1_Pos) /*!< SCT CONEN: NCEN1 Mask */
+#define SCT_CONEN_NCEN2_Pos 2 /*!< SCT CONEN: NCEN2 Position */
+#define SCT_CONEN_NCEN2_Msk (0x01UL << SCT_CONEN_NCEN2_Pos) /*!< SCT CONEN: NCEN2 Mask */
+#define SCT_CONEN_NCEN3_Pos 3 /*!< SCT CONEN: NCEN3 Position */
+#define SCT_CONEN_NCEN3_Msk (0x01UL << SCT_CONEN_NCEN3_Pos) /*!< SCT CONEN: NCEN3 Mask */
+#define SCT_CONEN_NCEN4_Pos 4 /*!< SCT CONEN: NCEN4 Position */
+#define SCT_CONEN_NCEN4_Msk (0x01UL << SCT_CONEN_NCEN4_Pos) /*!< SCT CONEN: NCEN4 Mask */
+#define SCT_CONEN_NCEN5_Pos 5 /*!< SCT CONEN: NCEN5 Position */
+#define SCT_CONEN_NCEN5_Msk (0x01UL << SCT_CONEN_NCEN5_Pos) /*!< SCT CONEN: NCEN5 Mask */
+#define SCT_CONEN_NCEN6_Pos 6 /*!< SCT CONEN: NCEN6 Position */
+#define SCT_CONEN_NCEN6_Msk (0x01UL << SCT_CONEN_NCEN6_Pos) /*!< SCT CONEN: NCEN6 Mask */
+#define SCT_CONEN_NCEN7_Pos 7 /*!< SCT CONEN: NCEN7 Position */
+#define SCT_CONEN_NCEN7_Msk (0x01UL << SCT_CONEN_NCEN7_Pos) /*!< SCT CONEN: NCEN7 Mask */
+#define SCT_CONEN_NCEN8_Pos 8 /*!< SCT CONEN: NCEN8 Position */
+#define SCT_CONEN_NCEN8_Msk (0x01UL << SCT_CONEN_NCEN8_Pos) /*!< SCT CONEN: NCEN8 Mask */
+#define SCT_CONEN_NCEN9_Pos 9 /*!< SCT CONEN: NCEN9 Position */
+#define SCT_CONEN_NCEN9_Msk (0x01UL << SCT_CONEN_NCEN9_Pos) /*!< SCT CONEN: NCEN9 Mask */
+#define SCT_CONEN_NCEN10_Pos 10 /*!< SCT CONEN: NCEN10 Position */
+#define SCT_CONEN_NCEN10_Msk (0x01UL << SCT_CONEN_NCEN10_Pos) /*!< SCT CONEN: NCEN10 Mask */
+#define SCT_CONEN_NCEN11_Pos 11 /*!< SCT CONEN: NCEN11 Position */
+#define SCT_CONEN_NCEN11_Msk (0x01UL << SCT_CONEN_NCEN11_Pos) /*!< SCT CONEN: NCEN11 Mask */
+#define SCT_CONEN_NCEN12_Pos 12 /*!< SCT CONEN: NCEN12 Position */
+#define SCT_CONEN_NCEN12_Msk (0x01UL << SCT_CONEN_NCEN12_Pos) /*!< SCT CONEN: NCEN12 Mask */
+#define SCT_CONEN_NCEN13_Pos 13 /*!< SCT CONEN: NCEN13 Position */
+#define SCT_CONEN_NCEN13_Msk (0x01UL << SCT_CONEN_NCEN13_Pos) /*!< SCT CONEN: NCEN13 Mask */
+#define SCT_CONEN_NCEN14_Pos 14 /*!< SCT CONEN: NCEN14 Position */
+#define SCT_CONEN_NCEN14_Msk (0x01UL << SCT_CONEN_NCEN14_Pos) /*!< SCT CONEN: NCEN14 Mask */
+#define SCT_CONEN_NCEN15_Pos 15 /*!< SCT CONEN: NCEN15 Position */
+#define SCT_CONEN_NCEN15_Msk (0x01UL << SCT_CONEN_NCEN15_Pos) /*!< SCT CONEN: NCEN15 Mask */
+
+// --------------------------------------- SCT_CONFLAG ------------------------------------------
+#define SCT_CONFLAG_NCFLAG0_Pos 0 /*!< SCT CONFLAG: NCFLAG0 Position */
+#define SCT_CONFLAG_NCFLAG0_Msk (0x01UL << SCT_CONFLAG_NCFLAG0_Pos) /*!< SCT CONFLAG: NCFLAG0 Mask */
+#define SCT_CONFLAG_NCFLAG1_Pos 1 /*!< SCT CONFLAG: NCFLAG1 Position */
+#define SCT_CONFLAG_NCFLAG1_Msk (0x01UL << SCT_CONFLAG_NCFLAG1_Pos) /*!< SCT CONFLAG: NCFLAG1 Mask */
+#define SCT_CONFLAG_NCFLAG2_Pos 2 /*!< SCT CONFLAG: NCFLAG2 Position */
+#define SCT_CONFLAG_NCFLAG2_Msk (0x01UL << SCT_CONFLAG_NCFLAG2_Pos) /*!< SCT CONFLAG: NCFLAG2 Mask */
+#define SCT_CONFLAG_NCFLAG3_Pos 3 /*!< SCT CONFLAG: NCFLAG3 Position */
+#define SCT_CONFLAG_NCFLAG3_Msk (0x01UL << SCT_CONFLAG_NCFLAG3_Pos) /*!< SCT CONFLAG: NCFLAG3 Mask */
+#define SCT_CONFLAG_NCFLAG4_Pos 4 /*!< SCT CONFLAG: NCFLAG4 Position */
+#define SCT_CONFLAG_NCFLAG4_Msk (0x01UL << SCT_CONFLAG_NCFLAG4_Pos) /*!< SCT CONFLAG: NCFLAG4 Mask */
+#define SCT_CONFLAG_NCFLAG5_Pos 5 /*!< SCT CONFLAG: NCFLAG5 Position */
+#define SCT_CONFLAG_NCFLAG5_Msk (0x01UL << SCT_CONFLAG_NCFLAG5_Pos) /*!< SCT CONFLAG: NCFLAG5 Mask */
+#define SCT_CONFLAG_NCFLAG6_Pos 6 /*!< SCT CONFLAG: NCFLAG6 Position */
+#define SCT_CONFLAG_NCFLAG6_Msk (0x01UL << SCT_CONFLAG_NCFLAG6_Pos) /*!< SCT CONFLAG: NCFLAG6 Mask */
+#define SCT_CONFLAG_NCFLAG7_Pos 7 /*!< SCT CONFLAG: NCFLAG7 Position */
+#define SCT_CONFLAG_NCFLAG7_Msk (0x01UL << SCT_CONFLAG_NCFLAG7_Pos) /*!< SCT CONFLAG: NCFLAG7 Mask */
+#define SCT_CONFLAG_NCFLAG8_Pos 8 /*!< SCT CONFLAG: NCFLAG8 Position */
+#define SCT_CONFLAG_NCFLAG8_Msk (0x01UL << SCT_CONFLAG_NCFLAG8_Pos) /*!< SCT CONFLAG: NCFLAG8 Mask */
+#define SCT_CONFLAG_NCFLAG9_Pos 9 /*!< SCT CONFLAG: NCFLAG9 Position */
+#define SCT_CONFLAG_NCFLAG9_Msk (0x01UL << SCT_CONFLAG_NCFLAG9_Pos) /*!< SCT CONFLAG: NCFLAG9 Mask */
+#define SCT_CONFLAG_NCFLAG10_Pos 10 /*!< SCT CONFLAG: NCFLAG10 Position */
+#define SCT_CONFLAG_NCFLAG10_Msk (0x01UL << SCT_CONFLAG_NCFLAG10_Pos) /*!< SCT CONFLAG: NCFLAG10 Mask */
+#define SCT_CONFLAG_NCFLAG11_Pos 11 /*!< SCT CONFLAG: NCFLAG11 Position */
+#define SCT_CONFLAG_NCFLAG11_Msk (0x01UL << SCT_CONFLAG_NCFLAG11_Pos) /*!< SCT CONFLAG: NCFLAG11 Mask */
+#define SCT_CONFLAG_NCFLAG12_Pos 12 /*!< SCT CONFLAG: NCFLAG12 Position */
+#define SCT_CONFLAG_NCFLAG12_Msk (0x01UL << SCT_CONFLAG_NCFLAG12_Pos) /*!< SCT CONFLAG: NCFLAG12 Mask */
+#define SCT_CONFLAG_NCFLAG13_Pos 13 /*!< SCT CONFLAG: NCFLAG13 Position */
+#define SCT_CONFLAG_NCFLAG13_Msk (0x01UL << SCT_CONFLAG_NCFLAG13_Pos) /*!< SCT CONFLAG: NCFLAG13 Mask */
+#define SCT_CONFLAG_NCFLAG14_Pos 14 /*!< SCT CONFLAG: NCFLAG14 Position */
+#define SCT_CONFLAG_NCFLAG14_Msk (0x01UL << SCT_CONFLAG_NCFLAG14_Pos) /*!< SCT CONFLAG: NCFLAG14 Mask */
+#define SCT_CONFLAG_NCFLAG15_Pos 15 /*!< SCT CONFLAG: NCFLAG15 Position */
+#define SCT_CONFLAG_NCFLAG15_Msk (0x01UL << SCT_CONFLAG_NCFLAG15_Pos) /*!< SCT CONFLAG: NCFLAG15 Mask */
+#define SCT_CONFLAG_BUSERRL_Pos 30 /*!< SCT CONFLAG: BUSERRL Position */
+#define SCT_CONFLAG_BUSERRL_Msk (0x01UL << SCT_CONFLAG_BUSERRL_Pos) /*!< SCT CONFLAG: BUSERRL Mask */
+#define SCT_CONFLAG_BUSERRH_Pos 31 /*!< SCT CONFLAG: BUSERRH Position */
+#define SCT_CONFLAG_BUSERRH_Msk (0x01UL << SCT_CONFLAG_BUSERRH_Pos) /*!< SCT CONFLAG: BUSERRH Mask */
+
+// --------------------------------------- SCT_MATCH0 -------------------------------------------
+#define SCT_MATCH0_MATCHn_L_Pos 0 /*!< SCT MATCH0: MATCHn_L Position */
+#define SCT_MATCH0_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH0_MATCHn_L_Pos) /*!< SCT MATCH0: MATCHn_L Mask */
+#define SCT_MATCH0_MATCHn_H_Pos 16 /*!< SCT MATCH0: MATCHn_H Position */
+#define SCT_MATCH0_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH0_MATCHn_H_Pos) /*!< SCT MATCH0: MATCHn_H Mask */
+
+// ---------------------------------------- SCT_CAP0 --------------------------------------------
+#define SCT_CAP0_CAPn_L_Pos 0 /*!< SCT CAP0: CAPn_L Position */
+#define SCT_CAP0_CAPn_L_Msk (0x0000ffffUL << SCT_CAP0_CAPn_L_Pos) /*!< SCT CAP0: CAPn_L Mask */
+#define SCT_CAP0_CAPn_H_Pos 16 /*!< SCT CAP0: CAPn_H Position */
+#define SCT_CAP0_CAPn_H_Msk (0x0000ffffUL << SCT_CAP0_CAPn_H_Pos) /*!< SCT CAP0: CAPn_H Mask */
+
+// --------------------------------------- SCT_MATCH1 -------------------------------------------
+#define SCT_MATCH1_MATCHn_L_Pos 0 /*!< SCT MATCH1: MATCHn_L Position */
+#define SCT_MATCH1_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH1_MATCHn_L_Pos) /*!< SCT MATCH1: MATCHn_L Mask */
+#define SCT_MATCH1_MATCHn_H_Pos 16 /*!< SCT MATCH1: MATCHn_H Position */
+#define SCT_MATCH1_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH1_MATCHn_H_Pos) /*!< SCT MATCH1: MATCHn_H Mask */
+
+// ---------------------------------------- SCT_CAP1 --------------------------------------------
+#define SCT_CAP1_CAPn_L_Pos 0 /*!< SCT CAP1: CAPn_L Position */
+#define SCT_CAP1_CAPn_L_Msk (0x0000ffffUL << SCT_CAP1_CAPn_L_Pos) /*!< SCT CAP1: CAPn_L Mask */
+#define SCT_CAP1_CAPn_H_Pos 16 /*!< SCT CAP1: CAPn_H Position */
+#define SCT_CAP1_CAPn_H_Msk (0x0000ffffUL << SCT_CAP1_CAPn_H_Pos) /*!< SCT CAP1: CAPn_H Mask */
+
+// --------------------------------------- SCT_MATCH2 -------------------------------------------
+#define SCT_MATCH2_MATCHn_L_Pos 0 /*!< SCT MATCH2: MATCHn_L Position */
+#define SCT_MATCH2_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH2_MATCHn_L_Pos) /*!< SCT MATCH2: MATCHn_L Mask */
+#define SCT_MATCH2_MATCHn_H_Pos 16 /*!< SCT MATCH2: MATCHn_H Position */
+#define SCT_MATCH2_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH2_MATCHn_H_Pos) /*!< SCT MATCH2: MATCHn_H Mask */
+
+// ---------------------------------------- SCT_CAP2 --------------------------------------------
+#define SCT_CAP2_CAPn_L_Pos 0 /*!< SCT CAP2: CAPn_L Position */
+#define SCT_CAP2_CAPn_L_Msk (0x0000ffffUL << SCT_CAP2_CAPn_L_Pos) /*!< SCT CAP2: CAPn_L Mask */
+#define SCT_CAP2_CAPn_H_Pos 16 /*!< SCT CAP2: CAPn_H Position */
+#define SCT_CAP2_CAPn_H_Msk (0x0000ffffUL << SCT_CAP2_CAPn_H_Pos) /*!< SCT CAP2: CAPn_H Mask */
+
+// ---------------------------------------- SCT_CAP3 --------------------------------------------
+#define SCT_CAP3_CAPn_L_Pos 0 /*!< SCT CAP3: CAPn_L Position */
+#define SCT_CAP3_CAPn_L_Msk (0x0000ffffUL << SCT_CAP3_CAPn_L_Pos) /*!< SCT CAP3: CAPn_L Mask */
+#define SCT_CAP3_CAPn_H_Pos 16 /*!< SCT CAP3: CAPn_H Position */
+#define SCT_CAP3_CAPn_H_Msk (0x0000ffffUL << SCT_CAP3_CAPn_H_Pos) /*!< SCT CAP3: CAPn_H Mask */
+
+// --------------------------------------- SCT_MATCH3 -------------------------------------------
+#define SCT_MATCH3_MATCHn_L_Pos 0 /*!< SCT MATCH3: MATCHn_L Position */
+#define SCT_MATCH3_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH3_MATCHn_L_Pos) /*!< SCT MATCH3: MATCHn_L Mask */
+#define SCT_MATCH3_MATCHn_H_Pos 16 /*!< SCT MATCH3: MATCHn_H Position */
+#define SCT_MATCH3_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH3_MATCHn_H_Pos) /*!< SCT MATCH3: MATCHn_H Mask */
+
+// --------------------------------------- SCT_MATCH4 -------------------------------------------
+#define SCT_MATCH4_MATCHn_L_Pos 0 /*!< SCT MATCH4: MATCHn_L Position */
+#define SCT_MATCH4_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH4_MATCHn_L_Pos) /*!< SCT MATCH4: MATCHn_L Mask */
+#define SCT_MATCH4_MATCHn_H_Pos 16 /*!< SCT MATCH4: MATCHn_H Position */
+#define SCT_MATCH4_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH4_MATCHn_H_Pos) /*!< SCT MATCH4: MATCHn_H Mask */
+
+// ---------------------------------------- SCT_CAP4 --------------------------------------------
+#define SCT_CAP4_CAPn_L_Pos 0 /*!< SCT CAP4: CAPn_L Position */
+#define SCT_CAP4_CAPn_L_Msk (0x0000ffffUL << SCT_CAP4_CAPn_L_Pos) /*!< SCT CAP4: CAPn_L Mask */
+#define SCT_CAP4_CAPn_H_Pos 16 /*!< SCT CAP4: CAPn_H Position */
+#define SCT_CAP4_CAPn_H_Msk (0x0000ffffUL << SCT_CAP4_CAPn_H_Pos) /*!< SCT CAP4: CAPn_H Mask */
+
+// --------------------------------------- SCT_MATCH5 -------------------------------------------
+#define SCT_MATCH5_MATCHn_L_Pos 0 /*!< SCT MATCH5: MATCHn_L Position */
+#define SCT_MATCH5_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH5_MATCHn_L_Pos) /*!< SCT MATCH5: MATCHn_L Mask */
+#define SCT_MATCH5_MATCHn_H_Pos 16 /*!< SCT MATCH5: MATCHn_H Position */
+#define SCT_MATCH5_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH5_MATCHn_H_Pos) /*!< SCT MATCH5: MATCHn_H Mask */
+
+// ---------------------------------------- SCT_CAP5 --------------------------------------------
+#define SCT_CAP5_CAPn_L_Pos 0 /*!< SCT CAP5: CAPn_L Position */
+#define SCT_CAP5_CAPn_L_Msk (0x0000ffffUL << SCT_CAP5_CAPn_L_Pos) /*!< SCT CAP5: CAPn_L Mask */
+#define SCT_CAP5_CAPn_H_Pos 16 /*!< SCT CAP5: CAPn_H Position */
+#define SCT_CAP5_CAPn_H_Msk (0x0000ffffUL << SCT_CAP5_CAPn_H_Pos) /*!< SCT CAP5: CAPn_H Mask */
+
+// --------------------------------------- SCT_MATCH6 -------------------------------------------
+#define SCT_MATCH6_MATCHn_L_Pos 0 /*!< SCT MATCH6: MATCHn_L Position */
+#define SCT_MATCH6_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH6_MATCHn_L_Pos) /*!< SCT MATCH6: MATCHn_L Mask */
+#define SCT_MATCH6_MATCHn_H_Pos 16 /*!< SCT MATCH6: MATCHn_H Position */
+#define SCT_MATCH6_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH6_MATCHn_H_Pos) /*!< SCT MATCH6: MATCHn_H Mask */
+
+// ---------------------------------------- SCT_CAP6 --------------------------------------------
+#define SCT_CAP6_CAPn_L_Pos 0 /*!< SCT CAP6: CAPn_L Position */
+#define SCT_CAP6_CAPn_L_Msk (0x0000ffffUL << SCT_CAP6_CAPn_L_Pos) /*!< SCT CAP6: CAPn_L Mask */
+#define SCT_CAP6_CAPn_H_Pos 16 /*!< SCT CAP6: CAPn_H Position */
+#define SCT_CAP6_CAPn_H_Msk (0x0000ffffUL << SCT_CAP6_CAPn_H_Pos) /*!< SCT CAP6: CAPn_H Mask */
+
+// ---------------------------------------- SCT_CAP7 --------------------------------------------
+#define SCT_CAP7_CAPn_L_Pos 0 /*!< SCT CAP7: CAPn_L Position */
+#define SCT_CAP7_CAPn_L_Msk (0x0000ffffUL << SCT_CAP7_CAPn_L_Pos) /*!< SCT CAP7: CAPn_L Mask */
+#define SCT_CAP7_CAPn_H_Pos 16 /*!< SCT CAP7: CAPn_H Position */
+#define SCT_CAP7_CAPn_H_Msk (0x0000ffffUL << SCT_CAP7_CAPn_H_Pos) /*!< SCT CAP7: CAPn_H Mask */
+
+// --------------------------------------- SCT_MATCH7 -------------------------------------------
+#define SCT_MATCH7_MATCHn_L_Pos 0 /*!< SCT MATCH7: MATCHn_L Position */
+#define SCT_MATCH7_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH7_MATCHn_L_Pos) /*!< SCT MATCH7: MATCHn_L Mask */
+#define SCT_MATCH7_MATCHn_H_Pos 16 /*!< SCT MATCH7: MATCHn_H Position */
+#define SCT_MATCH7_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH7_MATCHn_H_Pos) /*!< SCT MATCH7: MATCHn_H Mask */
+
+// ---------------------------------------- SCT_CAP8 --------------------------------------------
+#define SCT_CAP8_CAPn_L_Pos 0 /*!< SCT CAP8: CAPn_L Position */
+#define SCT_CAP8_CAPn_L_Msk (0x0000ffffUL << SCT_CAP8_CAPn_L_Pos) /*!< SCT CAP8: CAPn_L Mask */
+#define SCT_CAP8_CAPn_H_Pos 16 /*!< SCT CAP8: CAPn_H Position */
+#define SCT_CAP8_CAPn_H_Msk (0x0000ffffUL << SCT_CAP8_CAPn_H_Pos) /*!< SCT CAP8: CAPn_H Mask */
+
+// --------------------------------------- SCT_MATCH8 -------------------------------------------
+#define SCT_MATCH8_MATCHn_L_Pos 0 /*!< SCT MATCH8: MATCHn_L Position */
+#define SCT_MATCH8_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH8_MATCHn_L_Pos) /*!< SCT MATCH8: MATCHn_L Mask */
+#define SCT_MATCH8_MATCHn_H_Pos 16 /*!< SCT MATCH8: MATCHn_H Position */
+#define SCT_MATCH8_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH8_MATCHn_H_Pos) /*!< SCT MATCH8: MATCHn_H Mask */
+
+// --------------------------------------- SCT_MATCH9 -------------------------------------------
+#define SCT_MATCH9_MATCHn_L_Pos 0 /*!< SCT MATCH9: MATCHn_L Position */
+#define SCT_MATCH9_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH9_MATCHn_L_Pos) /*!< SCT MATCH9: MATCHn_L Mask */
+#define SCT_MATCH9_MATCHn_H_Pos 16 /*!< SCT MATCH9: MATCHn_H Position */
+#define SCT_MATCH9_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH9_MATCHn_H_Pos) /*!< SCT MATCH9: MATCHn_H Mask */
+
+// ---------------------------------------- SCT_CAP9 --------------------------------------------
+#define SCT_CAP9_CAPn_L_Pos 0 /*!< SCT CAP9: CAPn_L Position */
+#define SCT_CAP9_CAPn_L_Msk (0x0000ffffUL << SCT_CAP9_CAPn_L_Pos) /*!< SCT CAP9: CAPn_L Mask */
+#define SCT_CAP9_CAPn_H_Pos 16 /*!< SCT CAP9: CAPn_H Position */
+#define SCT_CAP9_CAPn_H_Msk (0x0000ffffUL << SCT_CAP9_CAPn_H_Pos) /*!< SCT CAP9: CAPn_H Mask */
+
+// ---------------------------------------- SCT_CAP10 -------------------------------------------
+#define SCT_CAP10_CAPn_L_Pos 0 /*!< SCT CAP10: CAPn_L Position */
+#define SCT_CAP10_CAPn_L_Msk (0x0000ffffUL << SCT_CAP10_CAPn_L_Pos) /*!< SCT CAP10: CAPn_L Mask */
+#define SCT_CAP10_CAPn_H_Pos 16 /*!< SCT CAP10: CAPn_H Position */
+#define SCT_CAP10_CAPn_H_Msk (0x0000ffffUL << SCT_CAP10_CAPn_H_Pos) /*!< SCT CAP10: CAPn_H Mask */
+
+// --------------------------------------- SCT_MATCH10 ------------------------------------------
+#define SCT_MATCH10_MATCHn_L_Pos 0 /*!< SCT MATCH10: MATCHn_L Position */
+#define SCT_MATCH10_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH10_MATCHn_L_Pos) /*!< SCT MATCH10: MATCHn_L Mask */
+#define SCT_MATCH10_MATCHn_H_Pos 16 /*!< SCT MATCH10: MATCHn_H Position */
+#define SCT_MATCH10_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH10_MATCHn_H_Pos) /*!< SCT MATCH10: MATCHn_H Mask */
+
+// ---------------------------------------- SCT_CAP11 -------------------------------------------
+#define SCT_CAP11_CAPn_L_Pos 0 /*!< SCT CAP11: CAPn_L Position */
+#define SCT_CAP11_CAPn_L_Msk (0x0000ffffUL << SCT_CAP11_CAPn_L_Pos) /*!< SCT CAP11: CAPn_L Mask */
+#define SCT_CAP11_CAPn_H_Pos 16 /*!< SCT CAP11: CAPn_H Position */
+#define SCT_CAP11_CAPn_H_Msk (0x0000ffffUL << SCT_CAP11_CAPn_H_Pos) /*!< SCT CAP11: CAPn_H Mask */
+
+// --------------------------------------- SCT_MATCH11 ------------------------------------------
+#define SCT_MATCH11_MATCHn_L_Pos 0 /*!< SCT MATCH11: MATCHn_L Position */
+#define SCT_MATCH11_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH11_MATCHn_L_Pos) /*!< SCT MATCH11: MATCHn_L Mask */
+#define SCT_MATCH11_MATCHn_H_Pos 16 /*!< SCT MATCH11: MATCHn_H Position */
+#define SCT_MATCH11_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH11_MATCHn_H_Pos) /*!< SCT MATCH11: MATCHn_H Mask */
+
+// --------------------------------------- SCT_MATCH12 ------------------------------------------
+#define SCT_MATCH12_MATCHn_L_Pos 0 /*!< SCT MATCH12: MATCHn_L Position */
+#define SCT_MATCH12_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH12_MATCHn_L_Pos) /*!< SCT MATCH12: MATCHn_L Mask */
+#define SCT_MATCH12_MATCHn_H_Pos 16 /*!< SCT MATCH12: MATCHn_H Position */
+#define SCT_MATCH12_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH12_MATCHn_H_Pos) /*!< SCT MATCH12: MATCHn_H Mask */
+
+// ---------------------------------------- SCT_CAP12 -------------------------------------------
+#define SCT_CAP12_CAPn_L_Pos 0 /*!< SCT CAP12: CAPn_L Position */
+#define SCT_CAP12_CAPn_L_Msk (0x0000ffffUL << SCT_CAP12_CAPn_L_Pos) /*!< SCT CAP12: CAPn_L Mask */
+#define SCT_CAP12_CAPn_H_Pos 16 /*!< SCT CAP12: CAPn_H Position */
+#define SCT_CAP12_CAPn_H_Msk (0x0000ffffUL << SCT_CAP12_CAPn_H_Pos) /*!< SCT CAP12: CAPn_H Mask */
+
+// ---------------------------------------- SCT_CAP13 -------------------------------------------
+#define SCT_CAP13_CAPn_L_Pos 0 /*!< SCT CAP13: CAPn_L Position */
+#define SCT_CAP13_CAPn_L_Msk (0x0000ffffUL << SCT_CAP13_CAPn_L_Pos) /*!< SCT CAP13: CAPn_L Mask */
+#define SCT_CAP13_CAPn_H_Pos 16 /*!< SCT CAP13: CAPn_H Position */
+#define SCT_CAP13_CAPn_H_Msk (0x0000ffffUL << SCT_CAP13_CAPn_H_Pos) /*!< SCT CAP13: CAPn_H Mask */
+
+// --------------------------------------- SCT_MATCH13 ------------------------------------------
+#define SCT_MATCH13_MATCHn_L_Pos 0 /*!< SCT MATCH13: MATCHn_L Position */
+#define SCT_MATCH13_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH13_MATCHn_L_Pos) /*!< SCT MATCH13: MATCHn_L Mask */
+#define SCT_MATCH13_MATCHn_H_Pos 16 /*!< SCT MATCH13: MATCHn_H Position */
+#define SCT_MATCH13_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH13_MATCHn_H_Pos) /*!< SCT MATCH13: MATCHn_H Mask */
+
+// --------------------------------------- SCT_MATCH14 ------------------------------------------
+#define SCT_MATCH14_MATCHn_L_Pos 0 /*!< SCT MATCH14: MATCHn_L Position */
+#define SCT_MATCH14_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH14_MATCHn_L_Pos) /*!< SCT MATCH14: MATCHn_L Mask */
+#define SCT_MATCH14_MATCHn_H_Pos 16 /*!< SCT MATCH14: MATCHn_H Position */
+#define SCT_MATCH14_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH14_MATCHn_H_Pos) /*!< SCT MATCH14: MATCHn_H Mask */
+
+// ---------------------------------------- SCT_CAP14 -------------------------------------------
+#define SCT_CAP14_CAPn_L_Pos 0 /*!< SCT CAP14: CAPn_L Position */
+#define SCT_CAP14_CAPn_L_Msk (0x0000ffffUL << SCT_CAP14_CAPn_L_Pos) /*!< SCT CAP14: CAPn_L Mask */
+#define SCT_CAP14_CAPn_H_Pos 16 /*!< SCT CAP14: CAPn_H Position */
+#define SCT_CAP14_CAPn_H_Msk (0x0000ffffUL << SCT_CAP14_CAPn_H_Pos) /*!< SCT CAP14: CAPn_H Mask */
+
+// --------------------------------------- SCT_MATCH15 ------------------------------------------
+#define SCT_MATCH15_MATCHn_L_Pos 0 /*!< SCT MATCH15: MATCHn_L Position */
+#define SCT_MATCH15_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH15_MATCHn_L_Pos) /*!< SCT MATCH15: MATCHn_L Mask */
+#define SCT_MATCH15_MATCHn_H_Pos 16 /*!< SCT MATCH15: MATCHn_H Position */
+#define SCT_MATCH15_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH15_MATCHn_H_Pos) /*!< SCT MATCH15: MATCHn_H Mask */
+
+// ---------------------------------------- SCT_CAP15 -------------------------------------------
+#define SCT_CAP15_CAPn_L_Pos 0 /*!< SCT CAP15: CAPn_L Position */
+#define SCT_CAP15_CAPn_L_Msk (0x0000ffffUL << SCT_CAP15_CAPn_L_Pos) /*!< SCT CAP15: CAPn_L Mask */
+#define SCT_CAP15_CAPn_H_Pos 16 /*!< SCT CAP15: CAPn_H Position */
+#define SCT_CAP15_CAPn_H_Msk (0x0000ffffUL << SCT_CAP15_CAPn_H_Pos) /*!< SCT CAP15: CAPn_H Mask */
+
+// -------------------------------------- SCT_MATCHREL0 -----------------------------------------
+#define SCT_MATCHREL0_RELOADn_L_Pos 0 /*!< SCT MATCHREL0: RELOADn_L Position */
+#define SCT_MATCHREL0_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL0_RELOADn_L_Pos) /*!< SCT MATCHREL0: RELOADn_L Mask */
+#define SCT_MATCHREL0_RELOADn_H_Pos 16 /*!< SCT MATCHREL0: RELOADn_H Position */
+#define SCT_MATCHREL0_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL0_RELOADn_H_Pos) /*!< SCT MATCHREL0: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL0 ------------------------------------------
+#define SCT_CAPCTRL0_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL0: CAPCONn_L0 Position */
+#define SCT_CAPCTRL0_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L0_Pos) /*!< SCT CAPCTRL0: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL0: CAPCONn_L1 Position */
+#define SCT_CAPCTRL0_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L1_Pos) /*!< SCT CAPCTRL0: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL0: CAPCONn_L2 Position */
+#define SCT_CAPCTRL0_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L2_Pos) /*!< SCT CAPCTRL0: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL0: CAPCONn_L3 Position */
+#define SCT_CAPCTRL0_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L3_Pos) /*!< SCT CAPCTRL0: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL0: CAPCONn_L4 Position */
+#define SCT_CAPCTRL0_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L4_Pos) /*!< SCT CAPCTRL0: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL0: CAPCONn_L5 Position */
+#define SCT_CAPCTRL0_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L5_Pos) /*!< SCT CAPCTRL0: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL0: CAPCONn_L6 Position */
+#define SCT_CAPCTRL0_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L6_Pos) /*!< SCT CAPCTRL0: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL0: CAPCONn_L7 Position */
+#define SCT_CAPCTRL0_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L7_Pos) /*!< SCT CAPCTRL0: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL0: CAPCONn_L8 Position */
+#define SCT_CAPCTRL0_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L8_Pos) /*!< SCT CAPCTRL0: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL0: CAPCONn_L9 Position */
+#define SCT_CAPCTRL0_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L9_Pos) /*!< SCT CAPCTRL0: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL0: CAPCONn_L10 Position */
+#define SCT_CAPCTRL0_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L10_Pos) /*!< SCT CAPCTRL0: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL0: CAPCONn_L11 Position */
+#define SCT_CAPCTRL0_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L11_Pos) /*!< SCT CAPCTRL0: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL0: CAPCONn_L12 Position */
+#define SCT_CAPCTRL0_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L12_Pos) /*!< SCT CAPCTRL0: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL0: CAPCONn_L13 Position */
+#define SCT_CAPCTRL0_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L13_Pos) /*!< SCT CAPCTRL0: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL0: CAPCONn_L14 Position */
+#define SCT_CAPCTRL0_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L14_Pos) /*!< SCT CAPCTRL0: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL0_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL0: CAPCONn_L15 Position */
+#define SCT_CAPCTRL0_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L15_Pos) /*!< SCT CAPCTRL0: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL0_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL0: CAPCONn_H Position */
+#define SCT_CAPCTRL0_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL0_CAPCONn_H_Pos) /*!< SCT CAPCTRL0: CAPCONn_H Mask */
+
+// -------------------------------------- SCT_MATCHREL1 -----------------------------------------
+#define SCT_MATCHREL1_RELOADn_L_Pos 0 /*!< SCT MATCHREL1: RELOADn_L Position */
+#define SCT_MATCHREL1_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL1_RELOADn_L_Pos) /*!< SCT MATCHREL1: RELOADn_L Mask */
+#define SCT_MATCHREL1_RELOADn_H_Pos 16 /*!< SCT MATCHREL1: RELOADn_H Position */
+#define SCT_MATCHREL1_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL1_RELOADn_H_Pos) /*!< SCT MATCHREL1: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL1 ------------------------------------------
+#define SCT_CAPCTRL1_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL1: CAPCONn_L0 Position */
+#define SCT_CAPCTRL1_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L0_Pos) /*!< SCT CAPCTRL1: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL1: CAPCONn_L1 Position */
+#define SCT_CAPCTRL1_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L1_Pos) /*!< SCT CAPCTRL1: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL1: CAPCONn_L2 Position */
+#define SCT_CAPCTRL1_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L2_Pos) /*!< SCT CAPCTRL1: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL1: CAPCONn_L3 Position */
+#define SCT_CAPCTRL1_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L3_Pos) /*!< SCT CAPCTRL1: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL1: CAPCONn_L4 Position */
+#define SCT_CAPCTRL1_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L4_Pos) /*!< SCT CAPCTRL1: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL1: CAPCONn_L5 Position */
+#define SCT_CAPCTRL1_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L5_Pos) /*!< SCT CAPCTRL1: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL1: CAPCONn_L6 Position */
+#define SCT_CAPCTRL1_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L6_Pos) /*!< SCT CAPCTRL1: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL1: CAPCONn_L7 Position */
+#define SCT_CAPCTRL1_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L7_Pos) /*!< SCT CAPCTRL1: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL1: CAPCONn_L8 Position */
+#define SCT_CAPCTRL1_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L8_Pos) /*!< SCT CAPCTRL1: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL1: CAPCONn_L9 Position */
+#define SCT_CAPCTRL1_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L9_Pos) /*!< SCT CAPCTRL1: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL1: CAPCONn_L10 Position */
+#define SCT_CAPCTRL1_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L10_Pos) /*!< SCT CAPCTRL1: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL1: CAPCONn_L11 Position */
+#define SCT_CAPCTRL1_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L11_Pos) /*!< SCT CAPCTRL1: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL1: CAPCONn_L12 Position */
+#define SCT_CAPCTRL1_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L12_Pos) /*!< SCT CAPCTRL1: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL1: CAPCONn_L13 Position */
+#define SCT_CAPCTRL1_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L13_Pos) /*!< SCT CAPCTRL1: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL1: CAPCONn_L14 Position */
+#define SCT_CAPCTRL1_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L14_Pos) /*!< SCT CAPCTRL1: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL1_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL1: CAPCONn_L15 Position */
+#define SCT_CAPCTRL1_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L15_Pos) /*!< SCT CAPCTRL1: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL1_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL1: CAPCONn_H Position */
+#define SCT_CAPCTRL1_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL1_CAPCONn_H_Pos) /*!< SCT CAPCTRL1: CAPCONn_H Mask */
+
+// -------------------------------------- SCT_MATCHREL2 -----------------------------------------
+#define SCT_MATCHREL2_RELOADn_L_Pos 0 /*!< SCT MATCHREL2: RELOADn_L Position */
+#define SCT_MATCHREL2_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL2_RELOADn_L_Pos) /*!< SCT MATCHREL2: RELOADn_L Mask */
+#define SCT_MATCHREL2_RELOADn_H_Pos 16 /*!< SCT MATCHREL2: RELOADn_H Position */
+#define SCT_MATCHREL2_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL2_RELOADn_H_Pos) /*!< SCT MATCHREL2: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL2 ------------------------------------------
+#define SCT_CAPCTRL2_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL2: CAPCONn_L0 Position */
+#define SCT_CAPCTRL2_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L0_Pos) /*!< SCT CAPCTRL2: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL2: CAPCONn_L1 Position */
+#define SCT_CAPCTRL2_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L1_Pos) /*!< SCT CAPCTRL2: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL2: CAPCONn_L2 Position */
+#define SCT_CAPCTRL2_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L2_Pos) /*!< SCT CAPCTRL2: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL2: CAPCONn_L3 Position */
+#define SCT_CAPCTRL2_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L3_Pos) /*!< SCT CAPCTRL2: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL2: CAPCONn_L4 Position */
+#define SCT_CAPCTRL2_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L4_Pos) /*!< SCT CAPCTRL2: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL2: CAPCONn_L5 Position */
+#define SCT_CAPCTRL2_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L5_Pos) /*!< SCT CAPCTRL2: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL2: CAPCONn_L6 Position */
+#define SCT_CAPCTRL2_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L6_Pos) /*!< SCT CAPCTRL2: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL2: CAPCONn_L7 Position */
+#define SCT_CAPCTRL2_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L7_Pos) /*!< SCT CAPCTRL2: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL2: CAPCONn_L8 Position */
+#define SCT_CAPCTRL2_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L8_Pos) /*!< SCT CAPCTRL2: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL2: CAPCONn_L9 Position */
+#define SCT_CAPCTRL2_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L9_Pos) /*!< SCT CAPCTRL2: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL2: CAPCONn_L10 Position */
+#define SCT_CAPCTRL2_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L10_Pos) /*!< SCT CAPCTRL2: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL2: CAPCONn_L11 Position */
+#define SCT_CAPCTRL2_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L11_Pos) /*!< SCT CAPCTRL2: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL2: CAPCONn_L12 Position */
+#define SCT_CAPCTRL2_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L12_Pos) /*!< SCT CAPCTRL2: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL2: CAPCONn_L13 Position */
+#define SCT_CAPCTRL2_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L13_Pos) /*!< SCT CAPCTRL2: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL2: CAPCONn_L14 Position */
+#define SCT_CAPCTRL2_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L14_Pos) /*!< SCT CAPCTRL2: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL2_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL2: CAPCONn_L15 Position */
+#define SCT_CAPCTRL2_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L15_Pos) /*!< SCT CAPCTRL2: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL2_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL2: CAPCONn_H Position */
+#define SCT_CAPCTRL2_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL2_CAPCONn_H_Pos) /*!< SCT CAPCTRL2: CAPCONn_H Mask */
+
+// -------------------------------------- SCT_MATCHREL3 -----------------------------------------
+#define SCT_MATCHREL3_RELOADn_L_Pos 0 /*!< SCT MATCHREL3: RELOADn_L Position */
+#define SCT_MATCHREL3_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL3_RELOADn_L_Pos) /*!< SCT MATCHREL3: RELOADn_L Mask */
+#define SCT_MATCHREL3_RELOADn_H_Pos 16 /*!< SCT MATCHREL3: RELOADn_H Position */
+#define SCT_MATCHREL3_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL3_RELOADn_H_Pos) /*!< SCT MATCHREL3: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL3 ------------------------------------------
+#define SCT_CAPCTRL3_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL3: CAPCONn_L0 Position */
+#define SCT_CAPCTRL3_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L0_Pos) /*!< SCT CAPCTRL3: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL3: CAPCONn_L1 Position */
+#define SCT_CAPCTRL3_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L1_Pos) /*!< SCT CAPCTRL3: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL3: CAPCONn_L2 Position */
+#define SCT_CAPCTRL3_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L2_Pos) /*!< SCT CAPCTRL3: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL3: CAPCONn_L3 Position */
+#define SCT_CAPCTRL3_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L3_Pos) /*!< SCT CAPCTRL3: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL3: CAPCONn_L4 Position */
+#define SCT_CAPCTRL3_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L4_Pos) /*!< SCT CAPCTRL3: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL3: CAPCONn_L5 Position */
+#define SCT_CAPCTRL3_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L5_Pos) /*!< SCT CAPCTRL3: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL3: CAPCONn_L6 Position */
+#define SCT_CAPCTRL3_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L6_Pos) /*!< SCT CAPCTRL3: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL3: CAPCONn_L7 Position */
+#define SCT_CAPCTRL3_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L7_Pos) /*!< SCT CAPCTRL3: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL3: CAPCONn_L8 Position */
+#define SCT_CAPCTRL3_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L8_Pos) /*!< SCT CAPCTRL3: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL3: CAPCONn_L9 Position */
+#define SCT_CAPCTRL3_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L9_Pos) /*!< SCT CAPCTRL3: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL3: CAPCONn_L10 Position */
+#define SCT_CAPCTRL3_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L10_Pos) /*!< SCT CAPCTRL3: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL3: CAPCONn_L11 Position */
+#define SCT_CAPCTRL3_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L11_Pos) /*!< SCT CAPCTRL3: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL3: CAPCONn_L12 Position */
+#define SCT_CAPCTRL3_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L12_Pos) /*!< SCT CAPCTRL3: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL3: CAPCONn_L13 Position */
+#define SCT_CAPCTRL3_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L13_Pos) /*!< SCT CAPCTRL3: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL3: CAPCONn_L14 Position */
+#define SCT_CAPCTRL3_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L14_Pos) /*!< SCT CAPCTRL3: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL3_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL3: CAPCONn_L15 Position */
+#define SCT_CAPCTRL3_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L15_Pos) /*!< SCT CAPCTRL3: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL3_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL3: CAPCONn_H Position */
+#define SCT_CAPCTRL3_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL3_CAPCONn_H_Pos) /*!< SCT CAPCTRL3: CAPCONn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL4 ------------------------------------------
+#define SCT_CAPCTRL4_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL4: CAPCONn_L0 Position */
+#define SCT_CAPCTRL4_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L0_Pos) /*!< SCT CAPCTRL4: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL4: CAPCONn_L1 Position */
+#define SCT_CAPCTRL4_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L1_Pos) /*!< SCT CAPCTRL4: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL4: CAPCONn_L2 Position */
+#define SCT_CAPCTRL4_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L2_Pos) /*!< SCT CAPCTRL4: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL4: CAPCONn_L3 Position */
+#define SCT_CAPCTRL4_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L3_Pos) /*!< SCT CAPCTRL4: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL4: CAPCONn_L4 Position */
+#define SCT_CAPCTRL4_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L4_Pos) /*!< SCT CAPCTRL4: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL4: CAPCONn_L5 Position */
+#define SCT_CAPCTRL4_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L5_Pos) /*!< SCT CAPCTRL4: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL4: CAPCONn_L6 Position */
+#define SCT_CAPCTRL4_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L6_Pos) /*!< SCT CAPCTRL4: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL4: CAPCONn_L7 Position */
+#define SCT_CAPCTRL4_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L7_Pos) /*!< SCT CAPCTRL4: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL4: CAPCONn_L8 Position */
+#define SCT_CAPCTRL4_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L8_Pos) /*!< SCT CAPCTRL4: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL4: CAPCONn_L9 Position */
+#define SCT_CAPCTRL4_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L9_Pos) /*!< SCT CAPCTRL4: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL4: CAPCONn_L10 Position */
+#define SCT_CAPCTRL4_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L10_Pos) /*!< SCT CAPCTRL4: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL4: CAPCONn_L11 Position */
+#define SCT_CAPCTRL4_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L11_Pos) /*!< SCT CAPCTRL4: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL4: CAPCONn_L12 Position */
+#define SCT_CAPCTRL4_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L12_Pos) /*!< SCT CAPCTRL4: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL4: CAPCONn_L13 Position */
+#define SCT_CAPCTRL4_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L13_Pos) /*!< SCT CAPCTRL4: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL4: CAPCONn_L14 Position */
+#define SCT_CAPCTRL4_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L14_Pos) /*!< SCT CAPCTRL4: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL4_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL4: CAPCONn_L15 Position */
+#define SCT_CAPCTRL4_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L15_Pos) /*!< SCT CAPCTRL4: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL4_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL4: CAPCONn_H Position */
+#define SCT_CAPCTRL4_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL4_CAPCONn_H_Pos) /*!< SCT CAPCTRL4: CAPCONn_H Mask */
+
+// -------------------------------------- SCT_MATCHREL4 -----------------------------------------
+#define SCT_MATCHREL4_RELOADn_L_Pos 0 /*!< SCT MATCHREL4: RELOADn_L Position */
+#define SCT_MATCHREL4_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL4_RELOADn_L_Pos) /*!< SCT MATCHREL4: RELOADn_L Mask */
+#define SCT_MATCHREL4_RELOADn_H_Pos 16 /*!< SCT MATCHREL4: RELOADn_H Position */
+#define SCT_MATCHREL4_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL4_RELOADn_H_Pos) /*!< SCT MATCHREL4: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL5 ------------------------------------------
+#define SCT_CAPCTRL5_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL5: CAPCONn_L0 Position */
+#define SCT_CAPCTRL5_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L0_Pos) /*!< SCT CAPCTRL5: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL5: CAPCONn_L1 Position */
+#define SCT_CAPCTRL5_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L1_Pos) /*!< SCT CAPCTRL5: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL5: CAPCONn_L2 Position */
+#define SCT_CAPCTRL5_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L2_Pos) /*!< SCT CAPCTRL5: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL5: CAPCONn_L3 Position */
+#define SCT_CAPCTRL5_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L3_Pos) /*!< SCT CAPCTRL5: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL5: CAPCONn_L4 Position */
+#define SCT_CAPCTRL5_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L4_Pos) /*!< SCT CAPCTRL5: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL5: CAPCONn_L5 Position */
+#define SCT_CAPCTRL5_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L5_Pos) /*!< SCT CAPCTRL5: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL5: CAPCONn_L6 Position */
+#define SCT_CAPCTRL5_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L6_Pos) /*!< SCT CAPCTRL5: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL5: CAPCONn_L7 Position */
+#define SCT_CAPCTRL5_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L7_Pos) /*!< SCT CAPCTRL5: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL5: CAPCONn_L8 Position */
+#define SCT_CAPCTRL5_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L8_Pos) /*!< SCT CAPCTRL5: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL5: CAPCONn_L9 Position */
+#define SCT_CAPCTRL5_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L9_Pos) /*!< SCT CAPCTRL5: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL5: CAPCONn_L10 Position */
+#define SCT_CAPCTRL5_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L10_Pos) /*!< SCT CAPCTRL5: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL5: CAPCONn_L11 Position */
+#define SCT_CAPCTRL5_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L11_Pos) /*!< SCT CAPCTRL5: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL5: CAPCONn_L12 Position */
+#define SCT_CAPCTRL5_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L12_Pos) /*!< SCT CAPCTRL5: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL5: CAPCONn_L13 Position */
+#define SCT_CAPCTRL5_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L13_Pos) /*!< SCT CAPCTRL5: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL5: CAPCONn_L14 Position */
+#define SCT_CAPCTRL5_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L14_Pos) /*!< SCT CAPCTRL5: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL5_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL5: CAPCONn_L15 Position */
+#define SCT_CAPCTRL5_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L15_Pos) /*!< SCT CAPCTRL5: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL5_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL5: CAPCONn_H Position */
+#define SCT_CAPCTRL5_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL5_CAPCONn_H_Pos) /*!< SCT CAPCTRL5: CAPCONn_H Mask */
+
+// -------------------------------------- SCT_MATCHREL5 -----------------------------------------
+#define SCT_MATCHREL5_RELOADn_L_Pos 0 /*!< SCT MATCHREL5: RELOADn_L Position */
+#define SCT_MATCHREL5_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL5_RELOADn_L_Pos) /*!< SCT MATCHREL5: RELOADn_L Mask */
+#define SCT_MATCHREL5_RELOADn_H_Pos 16 /*!< SCT MATCHREL5: RELOADn_H Position */
+#define SCT_MATCHREL5_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL5_RELOADn_H_Pos) /*!< SCT MATCHREL5: RELOADn_H Mask */
+
+// -------------------------------------- SCT_MATCHREL6 -----------------------------------------
+#define SCT_MATCHREL6_RELOADn_L_Pos 0 /*!< SCT MATCHREL6: RELOADn_L Position */
+#define SCT_MATCHREL6_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL6_RELOADn_L_Pos) /*!< SCT MATCHREL6: RELOADn_L Mask */
+#define SCT_MATCHREL6_RELOADn_H_Pos 16 /*!< SCT MATCHREL6: RELOADn_H Position */
+#define SCT_MATCHREL6_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL6_RELOADn_H_Pos) /*!< SCT MATCHREL6: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL6 ------------------------------------------
+#define SCT_CAPCTRL6_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL6: CAPCONn_L0 Position */
+#define SCT_CAPCTRL6_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L0_Pos) /*!< SCT CAPCTRL6: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL6: CAPCONn_L1 Position */
+#define SCT_CAPCTRL6_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L1_Pos) /*!< SCT CAPCTRL6: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL6: CAPCONn_L2 Position */
+#define SCT_CAPCTRL6_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L2_Pos) /*!< SCT CAPCTRL6: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL6: CAPCONn_L3 Position */
+#define SCT_CAPCTRL6_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L3_Pos) /*!< SCT CAPCTRL6: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL6: CAPCONn_L4 Position */
+#define SCT_CAPCTRL6_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L4_Pos) /*!< SCT CAPCTRL6: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL6: CAPCONn_L5 Position */
+#define SCT_CAPCTRL6_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L5_Pos) /*!< SCT CAPCTRL6: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL6: CAPCONn_L6 Position */
+#define SCT_CAPCTRL6_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L6_Pos) /*!< SCT CAPCTRL6: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL6: CAPCONn_L7 Position */
+#define SCT_CAPCTRL6_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L7_Pos) /*!< SCT CAPCTRL6: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL6: CAPCONn_L8 Position */
+#define SCT_CAPCTRL6_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L8_Pos) /*!< SCT CAPCTRL6: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL6: CAPCONn_L9 Position */
+#define SCT_CAPCTRL6_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L9_Pos) /*!< SCT CAPCTRL6: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL6: CAPCONn_L10 Position */
+#define SCT_CAPCTRL6_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L10_Pos) /*!< SCT CAPCTRL6: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL6: CAPCONn_L11 Position */
+#define SCT_CAPCTRL6_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L11_Pos) /*!< SCT CAPCTRL6: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL6: CAPCONn_L12 Position */
+#define SCT_CAPCTRL6_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L12_Pos) /*!< SCT CAPCTRL6: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL6: CAPCONn_L13 Position */
+#define SCT_CAPCTRL6_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L13_Pos) /*!< SCT CAPCTRL6: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL6: CAPCONn_L14 Position */
+#define SCT_CAPCTRL6_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L14_Pos) /*!< SCT CAPCTRL6: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL6_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL6: CAPCONn_L15 Position */
+#define SCT_CAPCTRL6_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L15_Pos) /*!< SCT CAPCTRL6: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL6_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL6: CAPCONn_H Position */
+#define SCT_CAPCTRL6_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL6_CAPCONn_H_Pos) /*!< SCT CAPCTRL6: CAPCONn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL7 ------------------------------------------
+#define SCT_CAPCTRL7_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL7: CAPCONn_L0 Position */
+#define SCT_CAPCTRL7_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L0_Pos) /*!< SCT CAPCTRL7: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL7: CAPCONn_L1 Position */
+#define SCT_CAPCTRL7_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L1_Pos) /*!< SCT CAPCTRL7: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL7: CAPCONn_L2 Position */
+#define SCT_CAPCTRL7_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L2_Pos) /*!< SCT CAPCTRL7: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL7: CAPCONn_L3 Position */
+#define SCT_CAPCTRL7_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L3_Pos) /*!< SCT CAPCTRL7: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL7: CAPCONn_L4 Position */
+#define SCT_CAPCTRL7_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L4_Pos) /*!< SCT CAPCTRL7: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL7: CAPCONn_L5 Position */
+#define SCT_CAPCTRL7_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L5_Pos) /*!< SCT CAPCTRL7: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL7: CAPCONn_L6 Position */
+#define SCT_CAPCTRL7_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L6_Pos) /*!< SCT CAPCTRL7: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL7: CAPCONn_L7 Position */
+#define SCT_CAPCTRL7_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L7_Pos) /*!< SCT CAPCTRL7: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL7: CAPCONn_L8 Position */
+#define SCT_CAPCTRL7_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L8_Pos) /*!< SCT CAPCTRL7: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL7: CAPCONn_L9 Position */
+#define SCT_CAPCTRL7_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L9_Pos) /*!< SCT CAPCTRL7: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL7: CAPCONn_L10 Position */
+#define SCT_CAPCTRL7_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L10_Pos) /*!< SCT CAPCTRL7: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL7: CAPCONn_L11 Position */
+#define SCT_CAPCTRL7_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L11_Pos) /*!< SCT CAPCTRL7: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL7: CAPCONn_L12 Position */
+#define SCT_CAPCTRL7_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L12_Pos) /*!< SCT CAPCTRL7: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL7: CAPCONn_L13 Position */
+#define SCT_CAPCTRL7_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L13_Pos) /*!< SCT CAPCTRL7: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL7: CAPCONn_L14 Position */
+#define SCT_CAPCTRL7_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L14_Pos) /*!< SCT CAPCTRL7: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL7_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL7: CAPCONn_L15 Position */
+#define SCT_CAPCTRL7_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L15_Pos) /*!< SCT CAPCTRL7: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL7_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL7: CAPCONn_H Position */
+#define SCT_CAPCTRL7_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL7_CAPCONn_H_Pos) /*!< SCT CAPCTRL7: CAPCONn_H Mask */
+
+// -------------------------------------- SCT_MATCHREL7 -----------------------------------------
+#define SCT_MATCHREL7_RELOADn_L_Pos 0 /*!< SCT MATCHREL7: RELOADn_L Position */
+#define SCT_MATCHREL7_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL7_RELOADn_L_Pos) /*!< SCT MATCHREL7: RELOADn_L Mask */
+#define SCT_MATCHREL7_RELOADn_H_Pos 16 /*!< SCT MATCHREL7: RELOADn_H Position */
+#define SCT_MATCHREL7_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL7_RELOADn_H_Pos) /*!< SCT MATCHREL7: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL8 ------------------------------------------
+#define SCT_CAPCTRL8_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL8: CAPCONn_L0 Position */
+#define SCT_CAPCTRL8_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L0_Pos) /*!< SCT CAPCTRL8: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL8: CAPCONn_L1 Position */
+#define SCT_CAPCTRL8_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L1_Pos) /*!< SCT CAPCTRL8: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL8: CAPCONn_L2 Position */
+#define SCT_CAPCTRL8_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L2_Pos) /*!< SCT CAPCTRL8: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL8: CAPCONn_L3 Position */
+#define SCT_CAPCTRL8_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L3_Pos) /*!< SCT CAPCTRL8: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL8: CAPCONn_L4 Position */
+#define SCT_CAPCTRL8_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L4_Pos) /*!< SCT CAPCTRL8: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL8: CAPCONn_L5 Position */
+#define SCT_CAPCTRL8_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L5_Pos) /*!< SCT CAPCTRL8: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL8: CAPCONn_L6 Position */
+#define SCT_CAPCTRL8_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L6_Pos) /*!< SCT CAPCTRL8: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL8: CAPCONn_L7 Position */
+#define SCT_CAPCTRL8_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L7_Pos) /*!< SCT CAPCTRL8: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL8: CAPCONn_L8 Position */
+#define SCT_CAPCTRL8_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L8_Pos) /*!< SCT CAPCTRL8: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL8: CAPCONn_L9 Position */
+#define SCT_CAPCTRL8_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L9_Pos) /*!< SCT CAPCTRL8: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL8: CAPCONn_L10 Position */
+#define SCT_CAPCTRL8_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L10_Pos) /*!< SCT CAPCTRL8: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL8: CAPCONn_L11 Position */
+#define SCT_CAPCTRL8_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L11_Pos) /*!< SCT CAPCTRL8: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL8: CAPCONn_L12 Position */
+#define SCT_CAPCTRL8_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L12_Pos) /*!< SCT CAPCTRL8: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL8: CAPCONn_L13 Position */
+#define SCT_CAPCTRL8_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L13_Pos) /*!< SCT CAPCTRL8: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL8: CAPCONn_L14 Position */
+#define SCT_CAPCTRL8_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L14_Pos) /*!< SCT CAPCTRL8: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL8_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL8: CAPCONn_L15 Position */
+#define SCT_CAPCTRL8_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L15_Pos) /*!< SCT CAPCTRL8: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL8_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL8: CAPCONn_H Position */
+#define SCT_CAPCTRL8_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL8_CAPCONn_H_Pos) /*!< SCT CAPCTRL8: CAPCONn_H Mask */
+
+// -------------------------------------- SCT_MATCHREL8 -----------------------------------------
+#define SCT_MATCHREL8_RELOADn_L_Pos 0 /*!< SCT MATCHREL8: RELOADn_L Position */
+#define SCT_MATCHREL8_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL8_RELOADn_L_Pos) /*!< SCT MATCHREL8: RELOADn_L Mask */
+#define SCT_MATCHREL8_RELOADn_H_Pos 16 /*!< SCT MATCHREL8: RELOADn_H Position */
+#define SCT_MATCHREL8_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL8_RELOADn_H_Pos) /*!< SCT MATCHREL8: RELOADn_H Mask */
+
+// -------------------------------------- SCT_MATCHREL9 -----------------------------------------
+#define SCT_MATCHREL9_RELOADn_L_Pos 0 /*!< SCT MATCHREL9: RELOADn_L Position */
+#define SCT_MATCHREL9_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL9_RELOADn_L_Pos) /*!< SCT MATCHREL9: RELOADn_L Mask */
+#define SCT_MATCHREL9_RELOADn_H_Pos 16 /*!< SCT MATCHREL9: RELOADn_H Position */
+#define SCT_MATCHREL9_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL9_RELOADn_H_Pos) /*!< SCT MATCHREL9: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL9 ------------------------------------------
+#define SCT_CAPCTRL9_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL9: CAPCONn_L0 Position */
+#define SCT_CAPCTRL9_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L0_Pos) /*!< SCT CAPCTRL9: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL9: CAPCONn_L1 Position */
+#define SCT_CAPCTRL9_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L1_Pos) /*!< SCT CAPCTRL9: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL9: CAPCONn_L2 Position */
+#define SCT_CAPCTRL9_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L2_Pos) /*!< SCT CAPCTRL9: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL9: CAPCONn_L3 Position */
+#define SCT_CAPCTRL9_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L3_Pos) /*!< SCT CAPCTRL9: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL9: CAPCONn_L4 Position */
+#define SCT_CAPCTRL9_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L4_Pos) /*!< SCT CAPCTRL9: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL9: CAPCONn_L5 Position */
+#define SCT_CAPCTRL9_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L5_Pos) /*!< SCT CAPCTRL9: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL9: CAPCONn_L6 Position */
+#define SCT_CAPCTRL9_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L6_Pos) /*!< SCT CAPCTRL9: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL9: CAPCONn_L7 Position */
+#define SCT_CAPCTRL9_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L7_Pos) /*!< SCT CAPCTRL9: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL9: CAPCONn_L8 Position */
+#define SCT_CAPCTRL9_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L8_Pos) /*!< SCT CAPCTRL9: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL9: CAPCONn_L9 Position */
+#define SCT_CAPCTRL9_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L9_Pos) /*!< SCT CAPCTRL9: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL9: CAPCONn_L10 Position */
+#define SCT_CAPCTRL9_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L10_Pos) /*!< SCT CAPCTRL9: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL9: CAPCONn_L11 Position */
+#define SCT_CAPCTRL9_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L11_Pos) /*!< SCT CAPCTRL9: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL9: CAPCONn_L12 Position */
+#define SCT_CAPCTRL9_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L12_Pos) /*!< SCT CAPCTRL9: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL9: CAPCONn_L13 Position */
+#define SCT_CAPCTRL9_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L13_Pos) /*!< SCT CAPCTRL9: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL9: CAPCONn_L14 Position */
+#define SCT_CAPCTRL9_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L14_Pos) /*!< SCT CAPCTRL9: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL9_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL9: CAPCONn_L15 Position */
+#define SCT_CAPCTRL9_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L15_Pos) /*!< SCT CAPCTRL9: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL9_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL9: CAPCONn_H Position */
+#define SCT_CAPCTRL9_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL9_CAPCONn_H_Pos) /*!< SCT CAPCTRL9: CAPCONn_H Mask */
+
+// ------------------------------------- SCT_MATCHREL10 -----------------------------------------
+#define SCT_MATCHREL10_RELOADn_L_Pos 0 /*!< SCT MATCHREL10: RELOADn_L Position */
+#define SCT_MATCHREL10_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL10_RELOADn_L_Pos) /*!< SCT MATCHREL10: RELOADn_L Mask */
+#define SCT_MATCHREL10_RELOADn_H_Pos 16 /*!< SCT MATCHREL10: RELOADn_H Position */
+#define SCT_MATCHREL10_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL10_RELOADn_H_Pos) /*!< SCT MATCHREL10: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL10 -----------------------------------------
+#define SCT_CAPCTRL10_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL10: CAPCONn_L0 Position */
+#define SCT_CAPCTRL10_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L0_Pos) /*!< SCT CAPCTRL10: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL10: CAPCONn_L1 Position */
+#define SCT_CAPCTRL10_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L1_Pos) /*!< SCT CAPCTRL10: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL10: CAPCONn_L2 Position */
+#define SCT_CAPCTRL10_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L2_Pos) /*!< SCT CAPCTRL10: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL10: CAPCONn_L3 Position */
+#define SCT_CAPCTRL10_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L3_Pos) /*!< SCT CAPCTRL10: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL10: CAPCONn_L4 Position */
+#define SCT_CAPCTRL10_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L4_Pos) /*!< SCT CAPCTRL10: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL10: CAPCONn_L5 Position */
+#define SCT_CAPCTRL10_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L5_Pos) /*!< SCT CAPCTRL10: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL10: CAPCONn_L6 Position */
+#define SCT_CAPCTRL10_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L6_Pos) /*!< SCT CAPCTRL10: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL10: CAPCONn_L7 Position */
+#define SCT_CAPCTRL10_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L7_Pos) /*!< SCT CAPCTRL10: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL10: CAPCONn_L8 Position */
+#define SCT_CAPCTRL10_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L8_Pos) /*!< SCT CAPCTRL10: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL10: CAPCONn_L9 Position */
+#define SCT_CAPCTRL10_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L9_Pos) /*!< SCT CAPCTRL10: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL10: CAPCONn_L10 Position */
+#define SCT_CAPCTRL10_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L10_Pos) /*!< SCT CAPCTRL10: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL10: CAPCONn_L11 Position */
+#define SCT_CAPCTRL10_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L11_Pos) /*!< SCT CAPCTRL10: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL10: CAPCONn_L12 Position */
+#define SCT_CAPCTRL10_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L12_Pos) /*!< SCT CAPCTRL10: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL10: CAPCONn_L13 Position */
+#define SCT_CAPCTRL10_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L13_Pos) /*!< SCT CAPCTRL10: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL10: CAPCONn_L14 Position */
+#define SCT_CAPCTRL10_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L14_Pos) /*!< SCT CAPCTRL10: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL10_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL10: CAPCONn_L15 Position */
+#define SCT_CAPCTRL10_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L15_Pos) /*!< SCT CAPCTRL10: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL10_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL10: CAPCONn_H Position */
+#define SCT_CAPCTRL10_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL10_CAPCONn_H_Pos) /*!< SCT CAPCTRL10: CAPCONn_H Mask */
+
+// ------------------------------------- SCT_MATCHREL11 -----------------------------------------
+#define SCT_MATCHREL11_RELOADn_L_Pos 0 /*!< SCT MATCHREL11: RELOADn_L Position */
+#define SCT_MATCHREL11_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL11_RELOADn_L_Pos) /*!< SCT MATCHREL11: RELOADn_L Mask */
+#define SCT_MATCHREL11_RELOADn_H_Pos 16 /*!< SCT MATCHREL11: RELOADn_H Position */
+#define SCT_MATCHREL11_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL11_RELOADn_H_Pos) /*!< SCT MATCHREL11: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL11 -----------------------------------------
+#define SCT_CAPCTRL11_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL11: CAPCONn_L0 Position */
+#define SCT_CAPCTRL11_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L0_Pos) /*!< SCT CAPCTRL11: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL11: CAPCONn_L1 Position */
+#define SCT_CAPCTRL11_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L1_Pos) /*!< SCT CAPCTRL11: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL11: CAPCONn_L2 Position */
+#define SCT_CAPCTRL11_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L2_Pos) /*!< SCT CAPCTRL11: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL11: CAPCONn_L3 Position */
+#define SCT_CAPCTRL11_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L3_Pos) /*!< SCT CAPCTRL11: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL11: CAPCONn_L4 Position */
+#define SCT_CAPCTRL11_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L4_Pos) /*!< SCT CAPCTRL11: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL11: CAPCONn_L5 Position */
+#define SCT_CAPCTRL11_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L5_Pos) /*!< SCT CAPCTRL11: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL11: CAPCONn_L6 Position */
+#define SCT_CAPCTRL11_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L6_Pos) /*!< SCT CAPCTRL11: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL11: CAPCONn_L7 Position */
+#define SCT_CAPCTRL11_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L7_Pos) /*!< SCT CAPCTRL11: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL11: CAPCONn_L8 Position */
+#define SCT_CAPCTRL11_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L8_Pos) /*!< SCT CAPCTRL11: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL11: CAPCONn_L9 Position */
+#define SCT_CAPCTRL11_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L9_Pos) /*!< SCT CAPCTRL11: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL11: CAPCONn_L10 Position */
+#define SCT_CAPCTRL11_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L10_Pos) /*!< SCT CAPCTRL11: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL11: CAPCONn_L11 Position */
+#define SCT_CAPCTRL11_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L11_Pos) /*!< SCT CAPCTRL11: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL11: CAPCONn_L12 Position */
+#define SCT_CAPCTRL11_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L12_Pos) /*!< SCT CAPCTRL11: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL11: CAPCONn_L13 Position */
+#define SCT_CAPCTRL11_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L13_Pos) /*!< SCT CAPCTRL11: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL11: CAPCONn_L14 Position */
+#define SCT_CAPCTRL11_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L14_Pos) /*!< SCT CAPCTRL11: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL11_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL11: CAPCONn_L15 Position */
+#define SCT_CAPCTRL11_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L15_Pos) /*!< SCT CAPCTRL11: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL11_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL11: CAPCONn_H Position */
+#define SCT_CAPCTRL11_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL11_CAPCONn_H_Pos) /*!< SCT CAPCTRL11: CAPCONn_H Mask */
+
+// ------------------------------------- SCT_MATCHREL12 -----------------------------------------
+#define SCT_MATCHREL12_RELOADn_L_Pos 0 /*!< SCT MATCHREL12: RELOADn_L Position */
+#define SCT_MATCHREL12_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL12_RELOADn_L_Pos) /*!< SCT MATCHREL12: RELOADn_L Mask */
+#define SCT_MATCHREL12_RELOADn_H_Pos 16 /*!< SCT MATCHREL12: RELOADn_H Position */
+#define SCT_MATCHREL12_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL12_RELOADn_H_Pos) /*!< SCT MATCHREL12: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL12 -----------------------------------------
+#define SCT_CAPCTRL12_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL12: CAPCONn_L0 Position */
+#define SCT_CAPCTRL12_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L0_Pos) /*!< SCT CAPCTRL12: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL12: CAPCONn_L1 Position */
+#define SCT_CAPCTRL12_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L1_Pos) /*!< SCT CAPCTRL12: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL12: CAPCONn_L2 Position */
+#define SCT_CAPCTRL12_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L2_Pos) /*!< SCT CAPCTRL12: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL12: CAPCONn_L3 Position */
+#define SCT_CAPCTRL12_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L3_Pos) /*!< SCT CAPCTRL12: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL12: CAPCONn_L4 Position */
+#define SCT_CAPCTRL12_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L4_Pos) /*!< SCT CAPCTRL12: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL12: CAPCONn_L5 Position */
+#define SCT_CAPCTRL12_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L5_Pos) /*!< SCT CAPCTRL12: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL12: CAPCONn_L6 Position */
+#define SCT_CAPCTRL12_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L6_Pos) /*!< SCT CAPCTRL12: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL12: CAPCONn_L7 Position */
+#define SCT_CAPCTRL12_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L7_Pos) /*!< SCT CAPCTRL12: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL12: CAPCONn_L8 Position */
+#define SCT_CAPCTRL12_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L8_Pos) /*!< SCT CAPCTRL12: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL12: CAPCONn_L9 Position */
+#define SCT_CAPCTRL12_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L9_Pos) /*!< SCT CAPCTRL12: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL12: CAPCONn_L10 Position */
+#define SCT_CAPCTRL12_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L10_Pos) /*!< SCT CAPCTRL12: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL12: CAPCONn_L11 Position */
+#define SCT_CAPCTRL12_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L11_Pos) /*!< SCT CAPCTRL12: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL12: CAPCONn_L12 Position */
+#define SCT_CAPCTRL12_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L12_Pos) /*!< SCT CAPCTRL12: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL12: CAPCONn_L13 Position */
+#define SCT_CAPCTRL12_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L13_Pos) /*!< SCT CAPCTRL12: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL12: CAPCONn_L14 Position */
+#define SCT_CAPCTRL12_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L14_Pos) /*!< SCT CAPCTRL12: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL12_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL12: CAPCONn_L15 Position */
+#define SCT_CAPCTRL12_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L15_Pos) /*!< SCT CAPCTRL12: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL12_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL12: CAPCONn_H Position */
+#define SCT_CAPCTRL12_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL12_CAPCONn_H_Pos) /*!< SCT CAPCTRL12: CAPCONn_H Mask */
+
+// ------------------------------------- SCT_MATCHREL13 -----------------------------------------
+#define SCT_MATCHREL13_RELOADn_L_Pos 0 /*!< SCT MATCHREL13: RELOADn_L Position */
+#define SCT_MATCHREL13_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL13_RELOADn_L_Pos) /*!< SCT MATCHREL13: RELOADn_L Mask */
+#define SCT_MATCHREL13_RELOADn_H_Pos 16 /*!< SCT MATCHREL13: RELOADn_H Position */
+#define SCT_MATCHREL13_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL13_RELOADn_H_Pos) /*!< SCT MATCHREL13: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL13 -----------------------------------------
+#define SCT_CAPCTRL13_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL13: CAPCONn_L0 Position */
+#define SCT_CAPCTRL13_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L0_Pos) /*!< SCT CAPCTRL13: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL13: CAPCONn_L1 Position */
+#define SCT_CAPCTRL13_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L1_Pos) /*!< SCT CAPCTRL13: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL13: CAPCONn_L2 Position */
+#define SCT_CAPCTRL13_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L2_Pos) /*!< SCT CAPCTRL13: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL13: CAPCONn_L3 Position */
+#define SCT_CAPCTRL13_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L3_Pos) /*!< SCT CAPCTRL13: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL13: CAPCONn_L4 Position */
+#define SCT_CAPCTRL13_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L4_Pos) /*!< SCT CAPCTRL13: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL13: CAPCONn_L5 Position */
+#define SCT_CAPCTRL13_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L5_Pos) /*!< SCT CAPCTRL13: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL13: CAPCONn_L6 Position */
+#define SCT_CAPCTRL13_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L6_Pos) /*!< SCT CAPCTRL13: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL13: CAPCONn_L7 Position */
+#define SCT_CAPCTRL13_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L7_Pos) /*!< SCT CAPCTRL13: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL13: CAPCONn_L8 Position */
+#define SCT_CAPCTRL13_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L8_Pos) /*!< SCT CAPCTRL13: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL13: CAPCONn_L9 Position */
+#define SCT_CAPCTRL13_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L9_Pos) /*!< SCT CAPCTRL13: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL13: CAPCONn_L10 Position */
+#define SCT_CAPCTRL13_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L10_Pos) /*!< SCT CAPCTRL13: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL13: CAPCONn_L11 Position */
+#define SCT_CAPCTRL13_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L11_Pos) /*!< SCT CAPCTRL13: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL13: CAPCONn_L12 Position */
+#define SCT_CAPCTRL13_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L12_Pos) /*!< SCT CAPCTRL13: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL13: CAPCONn_L13 Position */
+#define SCT_CAPCTRL13_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L13_Pos) /*!< SCT CAPCTRL13: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL13: CAPCONn_L14 Position */
+#define SCT_CAPCTRL13_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L14_Pos) /*!< SCT CAPCTRL13: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL13_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL13: CAPCONn_L15 Position */
+#define SCT_CAPCTRL13_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L15_Pos) /*!< SCT CAPCTRL13: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL13_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL13: CAPCONn_H Position */
+#define SCT_CAPCTRL13_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL13_CAPCONn_H_Pos) /*!< SCT CAPCTRL13: CAPCONn_H Mask */
+
+// ------------------------------------- SCT_MATCHREL14 -----------------------------------------
+#define SCT_MATCHREL14_RELOADn_L_Pos 0 /*!< SCT MATCHREL14: RELOADn_L Position */
+#define SCT_MATCHREL14_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL14_RELOADn_L_Pos) /*!< SCT MATCHREL14: RELOADn_L Mask */
+#define SCT_MATCHREL14_RELOADn_H_Pos 16 /*!< SCT MATCHREL14: RELOADn_H Position */
+#define SCT_MATCHREL14_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL14_RELOADn_H_Pos) /*!< SCT MATCHREL14: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL14 -----------------------------------------
+#define SCT_CAPCTRL14_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL14: CAPCONn_L0 Position */
+#define SCT_CAPCTRL14_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L0_Pos) /*!< SCT CAPCTRL14: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL14: CAPCONn_L1 Position */
+#define SCT_CAPCTRL14_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L1_Pos) /*!< SCT CAPCTRL14: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL14: CAPCONn_L2 Position */
+#define SCT_CAPCTRL14_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L2_Pos) /*!< SCT CAPCTRL14: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL14: CAPCONn_L3 Position */
+#define SCT_CAPCTRL14_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L3_Pos) /*!< SCT CAPCTRL14: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL14: CAPCONn_L4 Position */
+#define SCT_CAPCTRL14_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L4_Pos) /*!< SCT CAPCTRL14: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL14: CAPCONn_L5 Position */
+#define SCT_CAPCTRL14_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L5_Pos) /*!< SCT CAPCTRL14: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL14: CAPCONn_L6 Position */
+#define SCT_CAPCTRL14_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L6_Pos) /*!< SCT CAPCTRL14: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL14: CAPCONn_L7 Position */
+#define SCT_CAPCTRL14_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L7_Pos) /*!< SCT CAPCTRL14: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL14: CAPCONn_L8 Position */
+#define SCT_CAPCTRL14_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L8_Pos) /*!< SCT CAPCTRL14: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL14: CAPCONn_L9 Position */
+#define SCT_CAPCTRL14_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L9_Pos) /*!< SCT CAPCTRL14: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL14: CAPCONn_L10 Position */
+#define SCT_CAPCTRL14_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L10_Pos) /*!< SCT CAPCTRL14: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL14: CAPCONn_L11 Position */
+#define SCT_CAPCTRL14_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L11_Pos) /*!< SCT CAPCTRL14: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL14: CAPCONn_L12 Position */
+#define SCT_CAPCTRL14_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L12_Pos) /*!< SCT CAPCTRL14: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL14: CAPCONn_L13 Position */
+#define SCT_CAPCTRL14_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L13_Pos) /*!< SCT CAPCTRL14: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL14: CAPCONn_L14 Position */
+#define SCT_CAPCTRL14_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L14_Pos) /*!< SCT CAPCTRL14: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL14_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL14: CAPCONn_L15 Position */
+#define SCT_CAPCTRL14_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L15_Pos) /*!< SCT CAPCTRL14: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL14_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL14: CAPCONn_H Position */
+#define SCT_CAPCTRL14_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL14_CAPCONn_H_Pos) /*!< SCT CAPCTRL14: CAPCONn_H Mask */
+
+// ------------------------------------- SCT_MATCHREL15 -----------------------------------------
+#define SCT_MATCHREL15_RELOADn_L_Pos 0 /*!< SCT MATCHREL15: RELOADn_L Position */
+#define SCT_MATCHREL15_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL15_RELOADn_L_Pos) /*!< SCT MATCHREL15: RELOADn_L Mask */
+#define SCT_MATCHREL15_RELOADn_H_Pos 16 /*!< SCT MATCHREL15: RELOADn_H Position */
+#define SCT_MATCHREL15_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL15_RELOADn_H_Pos) /*!< SCT MATCHREL15: RELOADn_H Mask */
+
+// -------------------------------------- SCT_CAPCTRL15 -----------------------------------------
+#define SCT_CAPCTRL15_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL15: CAPCONn_L0 Position */
+#define SCT_CAPCTRL15_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L0_Pos) /*!< SCT CAPCTRL15: CAPCONn_L0 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL15: CAPCONn_L1 Position */
+#define SCT_CAPCTRL15_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L1_Pos) /*!< SCT CAPCTRL15: CAPCONn_L1 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL15: CAPCONn_L2 Position */
+#define SCT_CAPCTRL15_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L2_Pos) /*!< SCT CAPCTRL15: CAPCONn_L2 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL15: CAPCONn_L3 Position */
+#define SCT_CAPCTRL15_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L3_Pos) /*!< SCT CAPCTRL15: CAPCONn_L3 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL15: CAPCONn_L4 Position */
+#define SCT_CAPCTRL15_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L4_Pos) /*!< SCT CAPCTRL15: CAPCONn_L4 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL15: CAPCONn_L5 Position */
+#define SCT_CAPCTRL15_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L5_Pos) /*!< SCT CAPCTRL15: CAPCONn_L5 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL15: CAPCONn_L6 Position */
+#define SCT_CAPCTRL15_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L6_Pos) /*!< SCT CAPCTRL15: CAPCONn_L6 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL15: CAPCONn_L7 Position */
+#define SCT_CAPCTRL15_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L7_Pos) /*!< SCT CAPCTRL15: CAPCONn_L7 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL15: CAPCONn_L8 Position */
+#define SCT_CAPCTRL15_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L8_Pos) /*!< SCT CAPCTRL15: CAPCONn_L8 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL15: CAPCONn_L9 Position */
+#define SCT_CAPCTRL15_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L9_Pos) /*!< SCT CAPCTRL15: CAPCONn_L9 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL15: CAPCONn_L10 Position */
+#define SCT_CAPCTRL15_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L10_Pos) /*!< SCT CAPCTRL15: CAPCONn_L10 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL15: CAPCONn_L11 Position */
+#define SCT_CAPCTRL15_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L11_Pos) /*!< SCT CAPCTRL15: CAPCONn_L11 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL15: CAPCONn_L12 Position */
+#define SCT_CAPCTRL15_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L12_Pos) /*!< SCT CAPCTRL15: CAPCONn_L12 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL15: CAPCONn_L13 Position */
+#define SCT_CAPCTRL15_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L13_Pos) /*!< SCT CAPCTRL15: CAPCONn_L13 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL15: CAPCONn_L14 Position */
+#define SCT_CAPCTRL15_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L14_Pos) /*!< SCT CAPCTRL15: CAPCONn_L14 Mask */
+#define SCT_CAPCTRL15_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL15: CAPCONn_L15 Position */
+#define SCT_CAPCTRL15_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L15_Pos) /*!< SCT CAPCTRL15: CAPCONn_L15 Mask */
+#define SCT_CAPCTRL15_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL15: CAPCONn_H Position */
+#define SCT_CAPCTRL15_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL15_CAPCONn_H_Pos) /*!< SCT CAPCTRL15: CAPCONn_H Mask */
+
+// ------------------------------------- SCT_EVSTATEMSK0 ----------------------------------------
+#define SCT_EVSTATEMSK0_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK0: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK0: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK0: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK0: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK0: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK0: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK0: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK0: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK0: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK0: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK0: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK0: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK0: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK0: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK0: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK0: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK0: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK0: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK0: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK0: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK0: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK0: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK0: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK0: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK0: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK0: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK0: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK0: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK0: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK0: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK0: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK0_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK0: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK0_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn31 Mask */
+
+// --------------------------------------- SCT_EVCTRL0 ------------------------------------------
+#define SCT_EVCTRL0_MATCHSEL_Pos 0 /*!< SCT EVCTRL0: MATCHSEL Position */
+#define SCT_EVCTRL0_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL0_MATCHSEL_Pos) /*!< SCT EVCTRL0: MATCHSEL Mask */
+#define SCT_EVCTRL0_HEVENT_Pos 4 /*!< SCT EVCTRL0: HEVENT Position */
+#define SCT_EVCTRL0_HEVENT_Msk (0x01UL << SCT_EVCTRL0_HEVENT_Pos) /*!< SCT EVCTRL0: HEVENT Mask */
+#define SCT_EVCTRL0_OUTSEL_Pos 5 /*!< SCT EVCTRL0: OUTSEL Position */
+#define SCT_EVCTRL0_OUTSEL_Msk (0x01UL << SCT_EVCTRL0_OUTSEL_Pos) /*!< SCT EVCTRL0: OUTSEL Mask */
+#define SCT_EVCTRL0_IOSEL_Pos 6 /*!< SCT EVCTRL0: IOSEL Position */
+#define SCT_EVCTRL0_IOSEL_Msk (0x0fUL << SCT_EVCTRL0_IOSEL_Pos) /*!< SCT EVCTRL0: IOSEL Mask */
+#define SCT_EVCTRL0_IOCOND_Pos 10 /*!< SCT EVCTRL0: IOCOND Position */
+#define SCT_EVCTRL0_IOCOND_Msk (0x03UL << SCT_EVCTRL0_IOCOND_Pos) /*!< SCT EVCTRL0: IOCOND Mask */
+#define SCT_EVCTRL0_COMBMODE_Pos 12 /*!< SCT EVCTRL0: COMBMODE Position */
+#define SCT_EVCTRL0_COMBMODE_Msk (0x03UL << SCT_EVCTRL0_COMBMODE_Pos) /*!< SCT EVCTRL0: COMBMODE Mask */
+#define SCT_EVCTRL0_STATELD_Pos 14 /*!< SCT EVCTRL0: STATELD Position */
+#define SCT_EVCTRL0_STATELD_Msk (0x01UL << SCT_EVCTRL0_STATELD_Pos) /*!< SCT EVCTRL0: STATELD Mask */
+#define SCT_EVCTRL0_STATEV_Pos 15 /*!< SCT EVCTRL0: STATEV Position */
+#define SCT_EVCTRL0_STATEV_Msk (0x1fUL << SCT_EVCTRL0_STATEV_Pos) /*!< SCT EVCTRL0: STATEV Mask */
+
+// ------------------------------------- SCT_EVSTATEMSK1 ----------------------------------------
+#define SCT_EVSTATEMSK1_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK1: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK1: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK1: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK1: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK1: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK1: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK1: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK1: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK1: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK1: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK1: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK1: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK1: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK1: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK1: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK1: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK1: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK1: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK1: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK1: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK1: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK1: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK1: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK1: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK1: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK1: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK1: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK1: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK1: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK1: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK1: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK1_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK1: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK1_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn31 Mask */
+
+// --------------------------------------- SCT_EVCTRL1 ------------------------------------------
+#define SCT_EVCTRL1_MATCHSEL_Pos 0 /*!< SCT EVCTRL1: MATCHSEL Position */
+#define SCT_EVCTRL1_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL1_MATCHSEL_Pos) /*!< SCT EVCTRL1: MATCHSEL Mask */
+#define SCT_EVCTRL1_HEVENT_Pos 4 /*!< SCT EVCTRL1: HEVENT Position */
+#define SCT_EVCTRL1_HEVENT_Msk (0x01UL << SCT_EVCTRL1_HEVENT_Pos) /*!< SCT EVCTRL1: HEVENT Mask */
+#define SCT_EVCTRL1_OUTSEL_Pos 5 /*!< SCT EVCTRL1: OUTSEL Position */
+#define SCT_EVCTRL1_OUTSEL_Msk (0x01UL << SCT_EVCTRL1_OUTSEL_Pos) /*!< SCT EVCTRL1: OUTSEL Mask */
+#define SCT_EVCTRL1_IOSEL_Pos 6 /*!< SCT EVCTRL1: IOSEL Position */
+#define SCT_EVCTRL1_IOSEL_Msk (0x0fUL << SCT_EVCTRL1_IOSEL_Pos) /*!< SCT EVCTRL1: IOSEL Mask */
+#define SCT_EVCTRL1_IOCOND_Pos 10 /*!< SCT EVCTRL1: IOCOND Position */
+#define SCT_EVCTRL1_IOCOND_Msk (0x03UL << SCT_EVCTRL1_IOCOND_Pos) /*!< SCT EVCTRL1: IOCOND Mask */
+#define SCT_EVCTRL1_COMBMODE_Pos 12 /*!< SCT EVCTRL1: COMBMODE Position */
+#define SCT_EVCTRL1_COMBMODE_Msk (0x03UL << SCT_EVCTRL1_COMBMODE_Pos) /*!< SCT EVCTRL1: COMBMODE Mask */
+#define SCT_EVCTRL1_STATELD_Pos 14 /*!< SCT EVCTRL1: STATELD Position */
+#define SCT_EVCTRL1_STATELD_Msk (0x01UL << SCT_EVCTRL1_STATELD_Pos) /*!< SCT EVCTRL1: STATELD Mask */
+#define SCT_EVCTRL1_STATEV_Pos 15 /*!< SCT EVCTRL1: STATEV Position */
+#define SCT_EVCTRL1_STATEV_Msk (0x1fUL << SCT_EVCTRL1_STATEV_Pos) /*!< SCT EVCTRL1: STATEV Mask */
+
+// ------------------------------------- SCT_EVSTATEMSK2 ----------------------------------------
+#define SCT_EVSTATEMSK2_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK2: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK2: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK2: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK2: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK2: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK2: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK2: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK2: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK2: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK2: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK2: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK2: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK2: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK2: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK2: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK2: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK2: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK2: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK2: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK2: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK2: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK2: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK2: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK2: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK2: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK2: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK2: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK2: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK2: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK2: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK2: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK2_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK2: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK2_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn31 Mask */
+
+// --------------------------------------- SCT_EVCTRL2 ------------------------------------------
+#define SCT_EVCTRL2_MATCHSEL_Pos 0 /*!< SCT EVCTRL2: MATCHSEL Position */
+#define SCT_EVCTRL2_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL2_MATCHSEL_Pos) /*!< SCT EVCTRL2: MATCHSEL Mask */
+#define SCT_EVCTRL2_HEVENT_Pos 4 /*!< SCT EVCTRL2: HEVENT Position */
+#define SCT_EVCTRL2_HEVENT_Msk (0x01UL << SCT_EVCTRL2_HEVENT_Pos) /*!< SCT EVCTRL2: HEVENT Mask */
+#define SCT_EVCTRL2_OUTSEL_Pos 5 /*!< SCT EVCTRL2: OUTSEL Position */
+#define SCT_EVCTRL2_OUTSEL_Msk (0x01UL << SCT_EVCTRL2_OUTSEL_Pos) /*!< SCT EVCTRL2: OUTSEL Mask */
+#define SCT_EVCTRL2_IOSEL_Pos 6 /*!< SCT EVCTRL2: IOSEL Position */
+#define SCT_EVCTRL2_IOSEL_Msk (0x0fUL << SCT_EVCTRL2_IOSEL_Pos) /*!< SCT EVCTRL2: IOSEL Mask */
+#define SCT_EVCTRL2_IOCOND_Pos 10 /*!< SCT EVCTRL2: IOCOND Position */
+#define SCT_EVCTRL2_IOCOND_Msk (0x03UL << SCT_EVCTRL2_IOCOND_Pos) /*!< SCT EVCTRL2: IOCOND Mask */
+#define SCT_EVCTRL2_COMBMODE_Pos 12 /*!< SCT EVCTRL2: COMBMODE Position */
+#define SCT_EVCTRL2_COMBMODE_Msk (0x03UL << SCT_EVCTRL2_COMBMODE_Pos) /*!< SCT EVCTRL2: COMBMODE Mask */
+#define SCT_EVCTRL2_STATELD_Pos 14 /*!< SCT EVCTRL2: STATELD Position */
+#define SCT_EVCTRL2_STATELD_Msk (0x01UL << SCT_EVCTRL2_STATELD_Pos) /*!< SCT EVCTRL2: STATELD Mask */
+#define SCT_EVCTRL2_STATEV_Pos 15 /*!< SCT EVCTRL2: STATEV Position */
+#define SCT_EVCTRL2_STATEV_Msk (0x1fUL << SCT_EVCTRL2_STATEV_Pos) /*!< SCT EVCTRL2: STATEV Mask */
+
+// ------------------------------------- SCT_EVSTATEMSK3 ----------------------------------------
+#define SCT_EVSTATEMSK3_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK3: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK3: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK3: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK3: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK3: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK3: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK3: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK3: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK3: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK3: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK3: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK3: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK3: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK3: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK3: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK3: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK3: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK3: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK3: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK3: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK3: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK3: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK3: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK3: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK3: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK3: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK3: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK3: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK3: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK3: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK3: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK3_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK3: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK3_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn31 Mask */
+
+// --------------------------------------- SCT_EVCTRL3 ------------------------------------------
+#define SCT_EVCTRL3_MATCHSEL_Pos 0 /*!< SCT EVCTRL3: MATCHSEL Position */
+#define SCT_EVCTRL3_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL3_MATCHSEL_Pos) /*!< SCT EVCTRL3: MATCHSEL Mask */
+#define SCT_EVCTRL3_HEVENT_Pos 4 /*!< SCT EVCTRL3: HEVENT Position */
+#define SCT_EVCTRL3_HEVENT_Msk (0x01UL << SCT_EVCTRL3_HEVENT_Pos) /*!< SCT EVCTRL3: HEVENT Mask */
+#define SCT_EVCTRL3_OUTSEL_Pos 5 /*!< SCT EVCTRL3: OUTSEL Position */
+#define SCT_EVCTRL3_OUTSEL_Msk (0x01UL << SCT_EVCTRL3_OUTSEL_Pos) /*!< SCT EVCTRL3: OUTSEL Mask */
+#define SCT_EVCTRL3_IOSEL_Pos 6 /*!< SCT EVCTRL3: IOSEL Position */
+#define SCT_EVCTRL3_IOSEL_Msk (0x0fUL << SCT_EVCTRL3_IOSEL_Pos) /*!< SCT EVCTRL3: IOSEL Mask */
+#define SCT_EVCTRL3_IOCOND_Pos 10 /*!< SCT EVCTRL3: IOCOND Position */
+#define SCT_EVCTRL3_IOCOND_Msk (0x03UL << SCT_EVCTRL3_IOCOND_Pos) /*!< SCT EVCTRL3: IOCOND Mask */
+#define SCT_EVCTRL3_COMBMODE_Pos 12 /*!< SCT EVCTRL3: COMBMODE Position */
+#define SCT_EVCTRL3_COMBMODE_Msk (0x03UL << SCT_EVCTRL3_COMBMODE_Pos) /*!< SCT EVCTRL3: COMBMODE Mask */
+#define SCT_EVCTRL3_STATELD_Pos 14 /*!< SCT EVCTRL3: STATELD Position */
+#define SCT_EVCTRL3_STATELD_Msk (0x01UL << SCT_EVCTRL3_STATELD_Pos) /*!< SCT EVCTRL3: STATELD Mask */
+#define SCT_EVCTRL3_STATEV_Pos 15 /*!< SCT EVCTRL3: STATEV Position */
+#define SCT_EVCTRL3_STATEV_Msk (0x1fUL << SCT_EVCTRL3_STATEV_Pos) /*!< SCT EVCTRL3: STATEV Mask */
+
+// ------------------------------------- SCT_EVSTATEMSK4 ----------------------------------------
+#define SCT_EVSTATEMSK4_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK4: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK4: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK4: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK4: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK4: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK4: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK4: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK4: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK4: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK4: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK4: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK4: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK4: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK4: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK4: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK4: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK4: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK4: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK4: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK4: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK4: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK4: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK4: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK4: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK4: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK4: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK4: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK4: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK4: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK4: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK4: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK4_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK4: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK4_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn31 Mask */
+
+// --------------------------------------- SCT_EVCTRL4 ------------------------------------------
+#define SCT_EVCTRL4_MATCHSEL_Pos 0 /*!< SCT EVCTRL4: MATCHSEL Position */
+#define SCT_EVCTRL4_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL4_MATCHSEL_Pos) /*!< SCT EVCTRL4: MATCHSEL Mask */
+#define SCT_EVCTRL4_HEVENT_Pos 4 /*!< SCT EVCTRL4: HEVENT Position */
+#define SCT_EVCTRL4_HEVENT_Msk (0x01UL << SCT_EVCTRL4_HEVENT_Pos) /*!< SCT EVCTRL4: HEVENT Mask */
+#define SCT_EVCTRL4_OUTSEL_Pos 5 /*!< SCT EVCTRL4: OUTSEL Position */
+#define SCT_EVCTRL4_OUTSEL_Msk (0x01UL << SCT_EVCTRL4_OUTSEL_Pos) /*!< SCT EVCTRL4: OUTSEL Mask */
+#define SCT_EVCTRL4_IOSEL_Pos 6 /*!< SCT EVCTRL4: IOSEL Position */
+#define SCT_EVCTRL4_IOSEL_Msk (0x0fUL << SCT_EVCTRL4_IOSEL_Pos) /*!< SCT EVCTRL4: IOSEL Mask */
+#define SCT_EVCTRL4_IOCOND_Pos 10 /*!< SCT EVCTRL4: IOCOND Position */
+#define SCT_EVCTRL4_IOCOND_Msk (0x03UL << SCT_EVCTRL4_IOCOND_Pos) /*!< SCT EVCTRL4: IOCOND Mask */
+#define SCT_EVCTRL4_COMBMODE_Pos 12 /*!< SCT EVCTRL4: COMBMODE Position */
+#define SCT_EVCTRL4_COMBMODE_Msk (0x03UL << SCT_EVCTRL4_COMBMODE_Pos) /*!< SCT EVCTRL4: COMBMODE Mask */
+#define SCT_EVCTRL4_STATELD_Pos 14 /*!< SCT EVCTRL4: STATELD Position */
+#define SCT_EVCTRL4_STATELD_Msk (0x01UL << SCT_EVCTRL4_STATELD_Pos) /*!< SCT EVCTRL4: STATELD Mask */
+#define SCT_EVCTRL4_STATEV_Pos 15 /*!< SCT EVCTRL4: STATEV Position */
+#define SCT_EVCTRL4_STATEV_Msk (0x1fUL << SCT_EVCTRL4_STATEV_Pos) /*!< SCT EVCTRL4: STATEV Mask */
+
+// ------------------------------------- SCT_EVSTATEMSK5 ----------------------------------------
+#define SCT_EVSTATEMSK5_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK5: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK5: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK5: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK5: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK5: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK5: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK5: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK5: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK5: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK5: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK5: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK5: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK5: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK5: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK5: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK5: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK5: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK5: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK5: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK5: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK5: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK5: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK5: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK5: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK5: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK5: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK5: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK5: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK5: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK5: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK5: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK5_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK5: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK5_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn31 Mask */
+
+// --------------------------------------- SCT_EVCTRL5 ------------------------------------------
+#define SCT_EVCTRL5_MATCHSEL_Pos 0 /*!< SCT EVCTRL5: MATCHSEL Position */
+#define SCT_EVCTRL5_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL5_MATCHSEL_Pos) /*!< SCT EVCTRL5: MATCHSEL Mask */
+#define SCT_EVCTRL5_HEVENT_Pos 4 /*!< SCT EVCTRL5: HEVENT Position */
+#define SCT_EVCTRL5_HEVENT_Msk (0x01UL << SCT_EVCTRL5_HEVENT_Pos) /*!< SCT EVCTRL5: HEVENT Mask */
+#define SCT_EVCTRL5_OUTSEL_Pos 5 /*!< SCT EVCTRL5: OUTSEL Position */
+#define SCT_EVCTRL5_OUTSEL_Msk (0x01UL << SCT_EVCTRL5_OUTSEL_Pos) /*!< SCT EVCTRL5: OUTSEL Mask */
+#define SCT_EVCTRL5_IOSEL_Pos 6 /*!< SCT EVCTRL5: IOSEL Position */
+#define SCT_EVCTRL5_IOSEL_Msk (0x0fUL << SCT_EVCTRL5_IOSEL_Pos) /*!< SCT EVCTRL5: IOSEL Mask */
+#define SCT_EVCTRL5_IOCOND_Pos 10 /*!< SCT EVCTRL5: IOCOND Position */
+#define SCT_EVCTRL5_IOCOND_Msk (0x03UL << SCT_EVCTRL5_IOCOND_Pos) /*!< SCT EVCTRL5: IOCOND Mask */
+#define SCT_EVCTRL5_COMBMODE_Pos 12 /*!< SCT EVCTRL5: COMBMODE Position */
+#define SCT_EVCTRL5_COMBMODE_Msk (0x03UL << SCT_EVCTRL5_COMBMODE_Pos) /*!< SCT EVCTRL5: COMBMODE Mask */
+#define SCT_EVCTRL5_STATELD_Pos 14 /*!< SCT EVCTRL5: STATELD Position */
+#define SCT_EVCTRL5_STATELD_Msk (0x01UL << SCT_EVCTRL5_STATELD_Pos) /*!< SCT EVCTRL5: STATELD Mask */
+#define SCT_EVCTRL5_STATEV_Pos 15 /*!< SCT EVCTRL5: STATEV Position */
+#define SCT_EVCTRL5_STATEV_Msk (0x1fUL << SCT_EVCTRL5_STATEV_Pos) /*!< SCT EVCTRL5: STATEV Mask */
+
+// ------------------------------------- SCT_EVSTATEMSK6 ----------------------------------------
+#define SCT_EVSTATEMSK6_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK6: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK6: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK6: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK6: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK6: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK6: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK6: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK6: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK6: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK6: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK6: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK6: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK6: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK6: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK6: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK6: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK6: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK6: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK6: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK6: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK6: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK6: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK6: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK6: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK6: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK6: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK6: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK6: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK6: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK6: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK6: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK6_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK6: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK6_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn31 Mask */
+
+// --------------------------------------- SCT_EVCTRL6 ------------------------------------------
+#define SCT_EVCTRL6_MATCHSEL_Pos 0 /*!< SCT EVCTRL6: MATCHSEL Position */
+#define SCT_EVCTRL6_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL6_MATCHSEL_Pos) /*!< SCT EVCTRL6: MATCHSEL Mask */
+#define SCT_EVCTRL6_HEVENT_Pos 4 /*!< SCT EVCTRL6: HEVENT Position */
+#define SCT_EVCTRL6_HEVENT_Msk (0x01UL << SCT_EVCTRL6_HEVENT_Pos) /*!< SCT EVCTRL6: HEVENT Mask */
+#define SCT_EVCTRL6_OUTSEL_Pos 5 /*!< SCT EVCTRL6: OUTSEL Position */
+#define SCT_EVCTRL6_OUTSEL_Msk (0x01UL << SCT_EVCTRL6_OUTSEL_Pos) /*!< SCT EVCTRL6: OUTSEL Mask */
+#define SCT_EVCTRL6_IOSEL_Pos 6 /*!< SCT EVCTRL6: IOSEL Position */
+#define SCT_EVCTRL6_IOSEL_Msk (0x0fUL << SCT_EVCTRL6_IOSEL_Pos) /*!< SCT EVCTRL6: IOSEL Mask */
+#define SCT_EVCTRL6_IOCOND_Pos 10 /*!< SCT EVCTRL6: IOCOND Position */
+#define SCT_EVCTRL6_IOCOND_Msk (0x03UL << SCT_EVCTRL6_IOCOND_Pos) /*!< SCT EVCTRL6: IOCOND Mask */
+#define SCT_EVCTRL6_COMBMODE_Pos 12 /*!< SCT EVCTRL6: COMBMODE Position */
+#define SCT_EVCTRL6_COMBMODE_Msk (0x03UL << SCT_EVCTRL6_COMBMODE_Pos) /*!< SCT EVCTRL6: COMBMODE Mask */
+#define SCT_EVCTRL6_STATELD_Pos 14 /*!< SCT EVCTRL6: STATELD Position */
+#define SCT_EVCTRL6_STATELD_Msk (0x01UL << SCT_EVCTRL6_STATELD_Pos) /*!< SCT EVCTRL6: STATELD Mask */
+#define SCT_EVCTRL6_STATEV_Pos 15 /*!< SCT EVCTRL6: STATEV Position */
+#define SCT_EVCTRL6_STATEV_Msk (0x1fUL << SCT_EVCTRL6_STATEV_Pos) /*!< SCT EVCTRL6: STATEV Mask */
+
+// ------------------------------------- SCT_EVSTATEMSK7 ----------------------------------------
+#define SCT_EVSTATEMSK7_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK7: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK7: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK7: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK7: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK7: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK7: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK7: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK7: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK7: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK7: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK7: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK7: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK7: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK7: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK7: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK7: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK7: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK7: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK7: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK7: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK7: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK7: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK7: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK7: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK7: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK7: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK7: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK7: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK7: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK7: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK7: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK7_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK7: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK7_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn31 Mask */
+
+// --------------------------------------- SCT_EVCTRL7 ------------------------------------------
+#define SCT_EVCTRL7_MATCHSEL_Pos 0 /*!< SCT EVCTRL7: MATCHSEL Position */
+#define SCT_EVCTRL7_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL7_MATCHSEL_Pos) /*!< SCT EVCTRL7: MATCHSEL Mask */
+#define SCT_EVCTRL7_HEVENT_Pos 4 /*!< SCT EVCTRL7: HEVENT Position */
+#define SCT_EVCTRL7_HEVENT_Msk (0x01UL << SCT_EVCTRL7_HEVENT_Pos) /*!< SCT EVCTRL7: HEVENT Mask */
+#define SCT_EVCTRL7_OUTSEL_Pos 5 /*!< SCT EVCTRL7: OUTSEL Position */
+#define SCT_EVCTRL7_OUTSEL_Msk (0x01UL << SCT_EVCTRL7_OUTSEL_Pos) /*!< SCT EVCTRL7: OUTSEL Mask */
+#define SCT_EVCTRL7_IOSEL_Pos 6 /*!< SCT EVCTRL7: IOSEL Position */
+#define SCT_EVCTRL7_IOSEL_Msk (0x0fUL << SCT_EVCTRL7_IOSEL_Pos) /*!< SCT EVCTRL7: IOSEL Mask */
+#define SCT_EVCTRL7_IOCOND_Pos 10 /*!< SCT EVCTRL7: IOCOND Position */
+#define SCT_EVCTRL7_IOCOND_Msk (0x03UL << SCT_EVCTRL7_IOCOND_Pos) /*!< SCT EVCTRL7: IOCOND Mask */
+#define SCT_EVCTRL7_COMBMODE_Pos 12 /*!< SCT EVCTRL7: COMBMODE Position */
+#define SCT_EVCTRL7_COMBMODE_Msk (0x03UL << SCT_EVCTRL7_COMBMODE_Pos) /*!< SCT EVCTRL7: COMBMODE Mask */
+#define SCT_EVCTRL7_STATELD_Pos 14 /*!< SCT EVCTRL7: STATELD Position */
+#define SCT_EVCTRL7_STATELD_Msk (0x01UL << SCT_EVCTRL7_STATELD_Pos) /*!< SCT EVCTRL7: STATELD Mask */
+#define SCT_EVCTRL7_STATEV_Pos 15 /*!< SCT EVCTRL7: STATEV Position */
+#define SCT_EVCTRL7_STATEV_Msk (0x1fUL << SCT_EVCTRL7_STATEV_Pos) /*!< SCT EVCTRL7: STATEV Mask */
+
+// ------------------------------------- SCT_EVSTATEMSK8 ----------------------------------------
+#define SCT_EVSTATEMSK8_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK8: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK8: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK8: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK8: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK8: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK8: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK8: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK8: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK8: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK8: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK8: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK8: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK8: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK8: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK8: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK8: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK8: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK8: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK8: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK8: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK8: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK8: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK8: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK8: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK8: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK8: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK8: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK8: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK8: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK8: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK8: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK8_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK8: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK8_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn31 Mask */
+
+// --------------------------------------- SCT_EVCTRL8 ------------------------------------------
+#define SCT_EVCTRL8_MATCHSEL_Pos 0 /*!< SCT EVCTRL8: MATCHSEL Position */
+#define SCT_EVCTRL8_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL8_MATCHSEL_Pos) /*!< SCT EVCTRL8: MATCHSEL Mask */
+#define SCT_EVCTRL8_HEVENT_Pos 4 /*!< SCT EVCTRL8: HEVENT Position */
+#define SCT_EVCTRL8_HEVENT_Msk (0x01UL << SCT_EVCTRL8_HEVENT_Pos) /*!< SCT EVCTRL8: HEVENT Mask */
+#define SCT_EVCTRL8_OUTSEL_Pos 5 /*!< SCT EVCTRL8: OUTSEL Position */
+#define SCT_EVCTRL8_OUTSEL_Msk (0x01UL << SCT_EVCTRL8_OUTSEL_Pos) /*!< SCT EVCTRL8: OUTSEL Mask */
+#define SCT_EVCTRL8_IOSEL_Pos 6 /*!< SCT EVCTRL8: IOSEL Position */
+#define SCT_EVCTRL8_IOSEL_Msk (0x0fUL << SCT_EVCTRL8_IOSEL_Pos) /*!< SCT EVCTRL8: IOSEL Mask */
+#define SCT_EVCTRL8_IOCOND_Pos 10 /*!< SCT EVCTRL8: IOCOND Position */
+#define SCT_EVCTRL8_IOCOND_Msk (0x03UL << SCT_EVCTRL8_IOCOND_Pos) /*!< SCT EVCTRL8: IOCOND Mask */
+#define SCT_EVCTRL8_COMBMODE_Pos 12 /*!< SCT EVCTRL8: COMBMODE Position */
+#define SCT_EVCTRL8_COMBMODE_Msk (0x03UL << SCT_EVCTRL8_COMBMODE_Pos) /*!< SCT EVCTRL8: COMBMODE Mask */
+#define SCT_EVCTRL8_STATELD_Pos 14 /*!< SCT EVCTRL8: STATELD Position */
+#define SCT_EVCTRL8_STATELD_Msk (0x01UL << SCT_EVCTRL8_STATELD_Pos) /*!< SCT EVCTRL8: STATELD Mask */
+#define SCT_EVCTRL8_STATEV_Pos 15 /*!< SCT EVCTRL8: STATEV Position */
+#define SCT_EVCTRL8_STATEV_Msk (0x1fUL << SCT_EVCTRL8_STATEV_Pos) /*!< SCT EVCTRL8: STATEV Mask */
+
+// ------------------------------------- SCT_EVSTATEMSK9 ----------------------------------------
+#define SCT_EVSTATEMSK9_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK9: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK9: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK9: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK9: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK9: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK9: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK9: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK9: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK9: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK9: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK9: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK9: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK9: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK9: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK9: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK9: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK9: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK9: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK9: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK9: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK9: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK9: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK9: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK9: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK9: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK9: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK9: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK9: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK9: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK9: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK9: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK9_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK9: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK9_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn31 Mask */
+
+// --------------------------------------- SCT_EVCTRL9 ------------------------------------------
+#define SCT_EVCTRL9_MATCHSEL_Pos 0 /*!< SCT EVCTRL9: MATCHSEL Position */
+#define SCT_EVCTRL9_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL9_MATCHSEL_Pos) /*!< SCT EVCTRL9: MATCHSEL Mask */
+#define SCT_EVCTRL9_HEVENT_Pos 4 /*!< SCT EVCTRL9: HEVENT Position */
+#define SCT_EVCTRL9_HEVENT_Msk (0x01UL << SCT_EVCTRL9_HEVENT_Pos) /*!< SCT EVCTRL9: HEVENT Mask */
+#define SCT_EVCTRL9_OUTSEL_Pos 5 /*!< SCT EVCTRL9: OUTSEL Position */
+#define SCT_EVCTRL9_OUTSEL_Msk (0x01UL << SCT_EVCTRL9_OUTSEL_Pos) /*!< SCT EVCTRL9: OUTSEL Mask */
+#define SCT_EVCTRL9_IOSEL_Pos 6 /*!< SCT EVCTRL9: IOSEL Position */
+#define SCT_EVCTRL9_IOSEL_Msk (0x0fUL << SCT_EVCTRL9_IOSEL_Pos) /*!< SCT EVCTRL9: IOSEL Mask */
+#define SCT_EVCTRL9_IOCOND_Pos 10 /*!< SCT EVCTRL9: IOCOND Position */
+#define SCT_EVCTRL9_IOCOND_Msk (0x03UL << SCT_EVCTRL9_IOCOND_Pos) /*!< SCT EVCTRL9: IOCOND Mask */
+#define SCT_EVCTRL9_COMBMODE_Pos 12 /*!< SCT EVCTRL9: COMBMODE Position */
+#define SCT_EVCTRL9_COMBMODE_Msk (0x03UL << SCT_EVCTRL9_COMBMODE_Pos) /*!< SCT EVCTRL9: COMBMODE Mask */
+#define SCT_EVCTRL9_STATELD_Pos 14 /*!< SCT EVCTRL9: STATELD Position */
+#define SCT_EVCTRL9_STATELD_Msk (0x01UL << SCT_EVCTRL9_STATELD_Pos) /*!< SCT EVCTRL9: STATELD Mask */
+#define SCT_EVCTRL9_STATEV_Pos 15 /*!< SCT EVCTRL9: STATEV Position */
+#define SCT_EVCTRL9_STATEV_Msk (0x1fUL << SCT_EVCTRL9_STATEV_Pos) /*!< SCT EVCTRL9: STATEV Mask */
+
+// ------------------------------------ SCT_EVSTATEMSK10 ----------------------------------------
+#define SCT_EVSTATEMSK10_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK10: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK10: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK10: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK10: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK10: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK10: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK10: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK10: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK10: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK10: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK10: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK10: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK10: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK10: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK10: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK10: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK10: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK10: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK10: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK10: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK10: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK10: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK10: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK10: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK10: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK10: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK10: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK10: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK10: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK10: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK10: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK10_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK10: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK10_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn31 Mask */
+
+// -------------------------------------- SCT_EVCTRL10 ------------------------------------------
+#define SCT_EVCTRL10_MATCHSEL_Pos 0 /*!< SCT EVCTRL10: MATCHSEL Position */
+#define SCT_EVCTRL10_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL10_MATCHSEL_Pos) /*!< SCT EVCTRL10: MATCHSEL Mask */
+#define SCT_EVCTRL10_HEVENT_Pos 4 /*!< SCT EVCTRL10: HEVENT Position */
+#define SCT_EVCTRL10_HEVENT_Msk (0x01UL << SCT_EVCTRL10_HEVENT_Pos) /*!< SCT EVCTRL10: HEVENT Mask */
+#define SCT_EVCTRL10_OUTSEL_Pos 5 /*!< SCT EVCTRL10: OUTSEL Position */
+#define SCT_EVCTRL10_OUTSEL_Msk (0x01UL << SCT_EVCTRL10_OUTSEL_Pos) /*!< SCT EVCTRL10: OUTSEL Mask */
+#define SCT_EVCTRL10_IOSEL_Pos 6 /*!< SCT EVCTRL10: IOSEL Position */
+#define SCT_EVCTRL10_IOSEL_Msk (0x0fUL << SCT_EVCTRL10_IOSEL_Pos) /*!< SCT EVCTRL10: IOSEL Mask */
+#define SCT_EVCTRL10_IOCOND_Pos 10 /*!< SCT EVCTRL10: IOCOND Position */
+#define SCT_EVCTRL10_IOCOND_Msk (0x03UL << SCT_EVCTRL10_IOCOND_Pos) /*!< SCT EVCTRL10: IOCOND Mask */
+#define SCT_EVCTRL10_COMBMODE_Pos 12 /*!< SCT EVCTRL10: COMBMODE Position */
+#define SCT_EVCTRL10_COMBMODE_Msk (0x03UL << SCT_EVCTRL10_COMBMODE_Pos) /*!< SCT EVCTRL10: COMBMODE Mask */
+#define SCT_EVCTRL10_STATELD_Pos 14 /*!< SCT EVCTRL10: STATELD Position */
+#define SCT_EVCTRL10_STATELD_Msk (0x01UL << SCT_EVCTRL10_STATELD_Pos) /*!< SCT EVCTRL10: STATELD Mask */
+#define SCT_EVCTRL10_STATEV_Pos 15 /*!< SCT EVCTRL10: STATEV Position */
+#define SCT_EVCTRL10_STATEV_Msk (0x1fUL << SCT_EVCTRL10_STATEV_Pos) /*!< SCT EVCTRL10: STATEV Mask */
+
+// ------------------------------------ SCT_EVSTATEMSK11 ----------------------------------------
+#define SCT_EVSTATEMSK11_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK11: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK11: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK11: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK11: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK11: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK11: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK11: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK11: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK11: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK11: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK11: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK11: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK11: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK11: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK11: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK11: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK11: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK11: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK11: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK11: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK11: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK11: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK11: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK11: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK11: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK11: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK11: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK11: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK11: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK11: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK11: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK11_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK11: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK11_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn31 Mask */
+
+// -------------------------------------- SCT_EVCTRL11 ------------------------------------------
+#define SCT_EVCTRL11_MATCHSEL_Pos 0 /*!< SCT EVCTRL11: MATCHSEL Position */
+#define SCT_EVCTRL11_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL11_MATCHSEL_Pos) /*!< SCT EVCTRL11: MATCHSEL Mask */
+#define SCT_EVCTRL11_HEVENT_Pos 4 /*!< SCT EVCTRL11: HEVENT Position */
+#define SCT_EVCTRL11_HEVENT_Msk (0x01UL << SCT_EVCTRL11_HEVENT_Pos) /*!< SCT EVCTRL11: HEVENT Mask */
+#define SCT_EVCTRL11_OUTSEL_Pos 5 /*!< SCT EVCTRL11: OUTSEL Position */
+#define SCT_EVCTRL11_OUTSEL_Msk (0x01UL << SCT_EVCTRL11_OUTSEL_Pos) /*!< SCT EVCTRL11: OUTSEL Mask */
+#define SCT_EVCTRL11_IOSEL_Pos 6 /*!< SCT EVCTRL11: IOSEL Position */
+#define SCT_EVCTRL11_IOSEL_Msk (0x0fUL << SCT_EVCTRL11_IOSEL_Pos) /*!< SCT EVCTRL11: IOSEL Mask */
+#define SCT_EVCTRL11_IOCOND_Pos 10 /*!< SCT EVCTRL11: IOCOND Position */
+#define SCT_EVCTRL11_IOCOND_Msk (0x03UL << SCT_EVCTRL11_IOCOND_Pos) /*!< SCT EVCTRL11: IOCOND Mask */
+#define SCT_EVCTRL11_COMBMODE_Pos 12 /*!< SCT EVCTRL11: COMBMODE Position */
+#define SCT_EVCTRL11_COMBMODE_Msk (0x03UL << SCT_EVCTRL11_COMBMODE_Pos) /*!< SCT EVCTRL11: COMBMODE Mask */
+#define SCT_EVCTRL11_STATELD_Pos 14 /*!< SCT EVCTRL11: STATELD Position */
+#define SCT_EVCTRL11_STATELD_Msk (0x01UL << SCT_EVCTRL11_STATELD_Pos) /*!< SCT EVCTRL11: STATELD Mask */
+#define SCT_EVCTRL11_STATEV_Pos 15 /*!< SCT EVCTRL11: STATEV Position */
+#define SCT_EVCTRL11_STATEV_Msk (0x1fUL << SCT_EVCTRL11_STATEV_Pos) /*!< SCT EVCTRL11: STATEV Mask */
+
+// ------------------------------------ SCT_EVSTATEMSK12 ----------------------------------------
+#define SCT_EVSTATEMSK12_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK12: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK12: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK12: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK12: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK12: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK12: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK12: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK12: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK12: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK12: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK12: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK12: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK12: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK12: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK12: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK12: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK12: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK12: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK12: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK12: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK12: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK12: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK12: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK12: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK12: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK12: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK12: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK12: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK12: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK12: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK12: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK12_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK12: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK12_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn31 Mask */
+
+// -------------------------------------- SCT_EVCTRL12 ------------------------------------------
+#define SCT_EVCTRL12_MATCHSEL_Pos 0 /*!< SCT EVCTRL12: MATCHSEL Position */
+#define SCT_EVCTRL12_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL12_MATCHSEL_Pos) /*!< SCT EVCTRL12: MATCHSEL Mask */
+#define SCT_EVCTRL12_HEVENT_Pos 4 /*!< SCT EVCTRL12: HEVENT Position */
+#define SCT_EVCTRL12_HEVENT_Msk (0x01UL << SCT_EVCTRL12_HEVENT_Pos) /*!< SCT EVCTRL12: HEVENT Mask */
+#define SCT_EVCTRL12_OUTSEL_Pos 5 /*!< SCT EVCTRL12: OUTSEL Position */
+#define SCT_EVCTRL12_OUTSEL_Msk (0x01UL << SCT_EVCTRL12_OUTSEL_Pos) /*!< SCT EVCTRL12: OUTSEL Mask */
+#define SCT_EVCTRL12_IOSEL_Pos 6 /*!< SCT EVCTRL12: IOSEL Position */
+#define SCT_EVCTRL12_IOSEL_Msk (0x0fUL << SCT_EVCTRL12_IOSEL_Pos) /*!< SCT EVCTRL12: IOSEL Mask */
+#define SCT_EVCTRL12_IOCOND_Pos 10 /*!< SCT EVCTRL12: IOCOND Position */
+#define SCT_EVCTRL12_IOCOND_Msk (0x03UL << SCT_EVCTRL12_IOCOND_Pos) /*!< SCT EVCTRL12: IOCOND Mask */
+#define SCT_EVCTRL12_COMBMODE_Pos 12 /*!< SCT EVCTRL12: COMBMODE Position */
+#define SCT_EVCTRL12_COMBMODE_Msk (0x03UL << SCT_EVCTRL12_COMBMODE_Pos) /*!< SCT EVCTRL12: COMBMODE Mask */
+#define SCT_EVCTRL12_STATELD_Pos 14 /*!< SCT EVCTRL12: STATELD Position */
+#define SCT_EVCTRL12_STATELD_Msk (0x01UL << SCT_EVCTRL12_STATELD_Pos) /*!< SCT EVCTRL12: STATELD Mask */
+#define SCT_EVCTRL12_STATEV_Pos 15 /*!< SCT EVCTRL12: STATEV Position */
+#define SCT_EVCTRL12_STATEV_Msk (0x1fUL << SCT_EVCTRL12_STATEV_Pos) /*!< SCT EVCTRL12: STATEV Mask */
+
+// ------------------------------------ SCT_EVSTATEMSK13 ----------------------------------------
+#define SCT_EVSTATEMSK13_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK13: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK13: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK13: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK13: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK13: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK13: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK13: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK13: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK13: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK13: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK13: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK13: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK13: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK13: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK13: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK13: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK13: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK13: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK13: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK13: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK13: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK13: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK13: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK13: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK13: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK13: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK13: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK13: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK13: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK13: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK13: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK13_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK13: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK13_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn31 Mask */
+
+// -------------------------------------- SCT_EVCTRL13 ------------------------------------------
+#define SCT_EVCTRL13_MATCHSEL_Pos 0 /*!< SCT EVCTRL13: MATCHSEL Position */
+#define SCT_EVCTRL13_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL13_MATCHSEL_Pos) /*!< SCT EVCTRL13: MATCHSEL Mask */
+#define SCT_EVCTRL13_HEVENT_Pos 4 /*!< SCT EVCTRL13: HEVENT Position */
+#define SCT_EVCTRL13_HEVENT_Msk (0x01UL << SCT_EVCTRL13_HEVENT_Pos) /*!< SCT EVCTRL13: HEVENT Mask */
+#define SCT_EVCTRL13_OUTSEL_Pos 5 /*!< SCT EVCTRL13: OUTSEL Position */
+#define SCT_EVCTRL13_OUTSEL_Msk (0x01UL << SCT_EVCTRL13_OUTSEL_Pos) /*!< SCT EVCTRL13: OUTSEL Mask */
+#define SCT_EVCTRL13_IOSEL_Pos 6 /*!< SCT EVCTRL13: IOSEL Position */
+#define SCT_EVCTRL13_IOSEL_Msk (0x0fUL << SCT_EVCTRL13_IOSEL_Pos) /*!< SCT EVCTRL13: IOSEL Mask */
+#define SCT_EVCTRL13_IOCOND_Pos 10 /*!< SCT EVCTRL13: IOCOND Position */
+#define SCT_EVCTRL13_IOCOND_Msk (0x03UL << SCT_EVCTRL13_IOCOND_Pos) /*!< SCT EVCTRL13: IOCOND Mask */
+#define SCT_EVCTRL13_COMBMODE_Pos 12 /*!< SCT EVCTRL13: COMBMODE Position */
+#define SCT_EVCTRL13_COMBMODE_Msk (0x03UL << SCT_EVCTRL13_COMBMODE_Pos) /*!< SCT EVCTRL13: COMBMODE Mask */
+#define SCT_EVCTRL13_STATELD_Pos 14 /*!< SCT EVCTRL13: STATELD Position */
+#define SCT_EVCTRL13_STATELD_Msk (0x01UL << SCT_EVCTRL13_STATELD_Pos) /*!< SCT EVCTRL13: STATELD Mask */
+#define SCT_EVCTRL13_STATEV_Pos 15 /*!< SCT EVCTRL13: STATEV Position */
+#define SCT_EVCTRL13_STATEV_Msk (0x1fUL << SCT_EVCTRL13_STATEV_Pos) /*!< SCT EVCTRL13: STATEV Mask */
+
+// ------------------------------------ SCT_EVSTATEMSK14 ----------------------------------------
+#define SCT_EVSTATEMSK14_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK14: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK14: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK14: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK14: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK14: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK14: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK14: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK14: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK14: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK14: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK14: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK14: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK14: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK14: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK14: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK14: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK14: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK14: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK14: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK14: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK14: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK14: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK14: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK14: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK14: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK14: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK14: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK14: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK14: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK14: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK14: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK14_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK14: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK14_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn31 Mask */
+
+// -------------------------------------- SCT_EVCTRL14 ------------------------------------------
+#define SCT_EVCTRL14_MATCHSEL_Pos 0 /*!< SCT EVCTRL14: MATCHSEL Position */
+#define SCT_EVCTRL14_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL14_MATCHSEL_Pos) /*!< SCT EVCTRL14: MATCHSEL Mask */
+#define SCT_EVCTRL14_HEVENT_Pos 4 /*!< SCT EVCTRL14: HEVENT Position */
+#define SCT_EVCTRL14_HEVENT_Msk (0x01UL << SCT_EVCTRL14_HEVENT_Pos) /*!< SCT EVCTRL14: HEVENT Mask */
+#define SCT_EVCTRL14_OUTSEL_Pos 5 /*!< SCT EVCTRL14: OUTSEL Position */
+#define SCT_EVCTRL14_OUTSEL_Msk (0x01UL << SCT_EVCTRL14_OUTSEL_Pos) /*!< SCT EVCTRL14: OUTSEL Mask */
+#define SCT_EVCTRL14_IOSEL_Pos 6 /*!< SCT EVCTRL14: IOSEL Position */
+#define SCT_EVCTRL14_IOSEL_Msk (0x0fUL << SCT_EVCTRL14_IOSEL_Pos) /*!< SCT EVCTRL14: IOSEL Mask */
+#define SCT_EVCTRL14_IOCOND_Pos 10 /*!< SCT EVCTRL14: IOCOND Position */
+#define SCT_EVCTRL14_IOCOND_Msk (0x03UL << SCT_EVCTRL14_IOCOND_Pos) /*!< SCT EVCTRL14: IOCOND Mask */
+#define SCT_EVCTRL14_COMBMODE_Pos 12 /*!< SCT EVCTRL14: COMBMODE Position */
+#define SCT_EVCTRL14_COMBMODE_Msk (0x03UL << SCT_EVCTRL14_COMBMODE_Pos) /*!< SCT EVCTRL14: COMBMODE Mask */
+#define SCT_EVCTRL14_STATELD_Pos 14 /*!< SCT EVCTRL14: STATELD Position */
+#define SCT_EVCTRL14_STATELD_Msk (0x01UL << SCT_EVCTRL14_STATELD_Pos) /*!< SCT EVCTRL14: STATELD Mask */
+#define SCT_EVCTRL14_STATEV_Pos 15 /*!< SCT EVCTRL14: STATEV Position */
+#define SCT_EVCTRL14_STATEV_Msk (0x1fUL << SCT_EVCTRL14_STATEV_Pos) /*!< SCT EVCTRL14: STATEV Mask */
+
+// ------------------------------------ SCT_EVSTATEMSK15 ----------------------------------------
+#define SCT_EVSTATEMSK15_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK15: STATEMSKn0 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn0 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK15: STATEMSKn1 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn1 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK15: STATEMSKn2 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn2 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK15: STATEMSKn3 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn3 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK15: STATEMSKn4 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn4 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK15: STATEMSKn5 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn5 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK15: STATEMSKn6 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn6 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK15: STATEMSKn7 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn7 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK15: STATEMSKn8 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn8 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK15: STATEMSKn9 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn9 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK15: STATEMSKn10 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn10 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK15: STATEMSKn11 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn11 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK15: STATEMSKn12 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn12 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK15: STATEMSKn13 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn13 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK15: STATEMSKn14 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn14 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK15: STATEMSKn15 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn15 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK15: STATEMSKn16 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn16 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK15: STATEMSKn17 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn17 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK15: STATEMSKn18 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn18 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK15: STATEMSKn19 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn19 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK15: STATEMSKn20 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn20 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK15: STATEMSKn21 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn21 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK15: STATEMSKn22 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn22 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK15: STATEMSKn23 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn23 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK15: STATEMSKn24 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn24 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK15: STATEMSKn25 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn25 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK15: STATEMSKn26 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn26 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK15: STATEMSKn27 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn27 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK15: STATEMSKn28 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn28 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK15: STATEMSKn29 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn29 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK15: STATEMSKn30 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn30 Mask */
+#define SCT_EVSTATEMSK15_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK15: STATEMSKn31 Position */
+#define SCT_EVSTATEMSK15_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn31 Mask */
+
+// -------------------------------------- SCT_EVCTRL15 ------------------------------------------
+#define SCT_EVCTRL15_MATCHSEL_Pos 0 /*!< SCT EVCTRL15: MATCHSEL Position */
+#define SCT_EVCTRL15_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL15_MATCHSEL_Pos) /*!< SCT EVCTRL15: MATCHSEL Mask */
+#define SCT_EVCTRL15_HEVENT_Pos 4 /*!< SCT EVCTRL15: HEVENT Position */
+#define SCT_EVCTRL15_HEVENT_Msk (0x01UL << SCT_EVCTRL15_HEVENT_Pos) /*!< SCT EVCTRL15: HEVENT Mask */
+#define SCT_EVCTRL15_OUTSEL_Pos 5 /*!< SCT EVCTRL15: OUTSEL Position */
+#define SCT_EVCTRL15_OUTSEL_Msk (0x01UL << SCT_EVCTRL15_OUTSEL_Pos) /*!< SCT EVCTRL15: OUTSEL Mask */
+#define SCT_EVCTRL15_IOSEL_Pos 6 /*!< SCT EVCTRL15: IOSEL Position */
+#define SCT_EVCTRL15_IOSEL_Msk (0x0fUL << SCT_EVCTRL15_IOSEL_Pos) /*!< SCT EVCTRL15: IOSEL Mask */
+#define SCT_EVCTRL15_IOCOND_Pos 10 /*!< SCT EVCTRL15: IOCOND Position */
+#define SCT_EVCTRL15_IOCOND_Msk (0x03UL << SCT_EVCTRL15_IOCOND_Pos) /*!< SCT EVCTRL15: IOCOND Mask */
+#define SCT_EVCTRL15_COMBMODE_Pos 12 /*!< SCT EVCTRL15: COMBMODE Position */
+#define SCT_EVCTRL15_COMBMODE_Msk (0x03UL << SCT_EVCTRL15_COMBMODE_Pos) /*!< SCT EVCTRL15: COMBMODE Mask */
+#define SCT_EVCTRL15_STATELD_Pos 14 /*!< SCT EVCTRL15: STATELD Position */
+#define SCT_EVCTRL15_STATELD_Msk (0x01UL << SCT_EVCTRL15_STATELD_Pos) /*!< SCT EVCTRL15: STATELD Mask */
+#define SCT_EVCTRL15_STATEV_Pos 15 /*!< SCT EVCTRL15: STATEV Position */
+#define SCT_EVCTRL15_STATEV_Msk (0x1fUL << SCT_EVCTRL15_STATEV_Pos) /*!< SCT EVCTRL15: STATEV Mask */
+
+// ------------------------------------- SCT_OUTPUTSET0 -----------------------------------------
+#define SCT_OUTPUTSET0_SETn0_Pos 0 /*!< SCT OUTPUTSET0: SETn0 Position */
+#define SCT_OUTPUTSET0_SETn0_Msk (0x01UL << SCT_OUTPUTSET0_SETn0_Pos) /*!< SCT OUTPUTSET0: SETn0 Mask */
+#define SCT_OUTPUTSET0_SETn1_Pos 1 /*!< SCT OUTPUTSET0: SETn1 Position */
+#define SCT_OUTPUTSET0_SETn1_Msk (0x01UL << SCT_OUTPUTSET0_SETn1_Pos) /*!< SCT OUTPUTSET0: SETn1 Mask */
+#define SCT_OUTPUTSET0_SETn2_Pos 2 /*!< SCT OUTPUTSET0: SETn2 Position */
+#define SCT_OUTPUTSET0_SETn2_Msk (0x01UL << SCT_OUTPUTSET0_SETn2_Pos) /*!< SCT OUTPUTSET0: SETn2 Mask */
+#define SCT_OUTPUTSET0_SETn3_Pos 3 /*!< SCT OUTPUTSET0: SETn3 Position */
+#define SCT_OUTPUTSET0_SETn3_Msk (0x01UL << SCT_OUTPUTSET0_SETn3_Pos) /*!< SCT OUTPUTSET0: SETn3 Mask */
+#define SCT_OUTPUTSET0_SETn4_Pos 4 /*!< SCT OUTPUTSET0: SETn4 Position */
+#define SCT_OUTPUTSET0_SETn4_Msk (0x01UL << SCT_OUTPUTSET0_SETn4_Pos) /*!< SCT OUTPUTSET0: SETn4 Mask */
+#define SCT_OUTPUTSET0_SETn5_Pos 5 /*!< SCT OUTPUTSET0: SETn5 Position */
+#define SCT_OUTPUTSET0_SETn5_Msk (0x01UL << SCT_OUTPUTSET0_SETn5_Pos) /*!< SCT OUTPUTSET0: SETn5 Mask */
+#define SCT_OUTPUTSET0_SETn6_Pos 6 /*!< SCT OUTPUTSET0: SETn6 Position */
+#define SCT_OUTPUTSET0_SETn6_Msk (0x01UL << SCT_OUTPUTSET0_SETn6_Pos) /*!< SCT OUTPUTSET0: SETn6 Mask */
+#define SCT_OUTPUTSET0_SETn7_Pos 7 /*!< SCT OUTPUTSET0: SETn7 Position */
+#define SCT_OUTPUTSET0_SETn7_Msk (0x01UL << SCT_OUTPUTSET0_SETn7_Pos) /*!< SCT OUTPUTSET0: SETn7 Mask */
+#define SCT_OUTPUTSET0_SETn8_Pos 8 /*!< SCT OUTPUTSET0: SETn8 Position */
+#define SCT_OUTPUTSET0_SETn8_Msk (0x01UL << SCT_OUTPUTSET0_SETn8_Pos) /*!< SCT OUTPUTSET0: SETn8 Mask */
+#define SCT_OUTPUTSET0_SETn9_Pos 9 /*!< SCT OUTPUTSET0: SETn9 Position */
+#define SCT_OUTPUTSET0_SETn9_Msk (0x01UL << SCT_OUTPUTSET0_SETn9_Pos) /*!< SCT OUTPUTSET0: SETn9 Mask */
+#define SCT_OUTPUTSET0_SETn10_Pos 10 /*!< SCT OUTPUTSET0: SETn10 Position */
+#define SCT_OUTPUTSET0_SETn10_Msk (0x01UL << SCT_OUTPUTSET0_SETn10_Pos) /*!< SCT OUTPUTSET0: SETn10 Mask */
+#define SCT_OUTPUTSET0_SETn11_Pos 11 /*!< SCT OUTPUTSET0: SETn11 Position */
+#define SCT_OUTPUTSET0_SETn11_Msk (0x01UL << SCT_OUTPUTSET0_SETn11_Pos) /*!< SCT OUTPUTSET0: SETn11 Mask */
+#define SCT_OUTPUTSET0_SETn12_Pos 12 /*!< SCT OUTPUTSET0: SETn12 Position */
+#define SCT_OUTPUTSET0_SETn12_Msk (0x01UL << SCT_OUTPUTSET0_SETn12_Pos) /*!< SCT OUTPUTSET0: SETn12 Mask */
+#define SCT_OUTPUTSET0_SETn13_Pos 13 /*!< SCT OUTPUTSET0: SETn13 Position */
+#define SCT_OUTPUTSET0_SETn13_Msk (0x01UL << SCT_OUTPUTSET0_SETn13_Pos) /*!< SCT OUTPUTSET0: SETn13 Mask */
+#define SCT_OUTPUTSET0_SETn14_Pos 14 /*!< SCT OUTPUTSET0: SETn14 Position */
+#define SCT_OUTPUTSET0_SETn14_Msk (0x01UL << SCT_OUTPUTSET0_SETn14_Pos) /*!< SCT OUTPUTSET0: SETn14 Mask */
+#define SCT_OUTPUTSET0_SETn15_Pos 15 /*!< SCT OUTPUTSET0: SETn15 Position */
+#define SCT_OUTPUTSET0_SETn15_Msk (0x01UL << SCT_OUTPUTSET0_SETn15_Pos) /*!< SCT OUTPUTSET0: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR0 -----------------------------------------
+#define SCT_OUTPUTCLR0_CLRn0_Pos 0 /*!< SCT OUTPUTCLR0: CLRn0 Position */
+#define SCT_OUTPUTCLR0_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn0_Pos) /*!< SCT OUTPUTCLR0: CLRn0 Mask */
+#define SCT_OUTPUTCLR0_CLRn1_Pos 1 /*!< SCT OUTPUTCLR0: CLRn1 Position */
+#define SCT_OUTPUTCLR0_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn1_Pos) /*!< SCT OUTPUTCLR0: CLRn1 Mask */
+#define SCT_OUTPUTCLR0_CLRn2_Pos 2 /*!< SCT OUTPUTCLR0: CLRn2 Position */
+#define SCT_OUTPUTCLR0_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn2_Pos) /*!< SCT OUTPUTCLR0: CLRn2 Mask */
+#define SCT_OUTPUTCLR0_CLRn3_Pos 3 /*!< SCT OUTPUTCLR0: CLRn3 Position */
+#define SCT_OUTPUTCLR0_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn3_Pos) /*!< SCT OUTPUTCLR0: CLRn3 Mask */
+#define SCT_OUTPUTCLR0_CLRn4_Pos 4 /*!< SCT OUTPUTCLR0: CLRn4 Position */
+#define SCT_OUTPUTCLR0_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn4_Pos) /*!< SCT OUTPUTCLR0: CLRn4 Mask */
+#define SCT_OUTPUTCLR0_CLRn5_Pos 5 /*!< SCT OUTPUTCLR0: CLRn5 Position */
+#define SCT_OUTPUTCLR0_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn5_Pos) /*!< SCT OUTPUTCLR0: CLRn5 Mask */
+#define SCT_OUTPUTCLR0_CLRn6_Pos 6 /*!< SCT OUTPUTCLR0: CLRn6 Position */
+#define SCT_OUTPUTCLR0_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn6_Pos) /*!< SCT OUTPUTCLR0: CLRn6 Mask */
+#define SCT_OUTPUTCLR0_CLRn7_Pos 7 /*!< SCT OUTPUTCLR0: CLRn7 Position */
+#define SCT_OUTPUTCLR0_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn7_Pos) /*!< SCT OUTPUTCLR0: CLRn7 Mask */
+#define SCT_OUTPUTCLR0_CLRn8_Pos 8 /*!< SCT OUTPUTCLR0: CLRn8 Position */
+#define SCT_OUTPUTCLR0_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn8_Pos) /*!< SCT OUTPUTCLR0: CLRn8 Mask */
+#define SCT_OUTPUTCLR0_CLRn9_Pos 9 /*!< SCT OUTPUTCLR0: CLRn9 Position */
+#define SCT_OUTPUTCLR0_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn9_Pos) /*!< SCT OUTPUTCLR0: CLRn9 Mask */
+#define SCT_OUTPUTCLR0_CLRn10_Pos 10 /*!< SCT OUTPUTCLR0: CLRn10 Position */
+#define SCT_OUTPUTCLR0_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn10_Pos) /*!< SCT OUTPUTCLR0: CLRn10 Mask */
+#define SCT_OUTPUTCLR0_CLRn11_Pos 11 /*!< SCT OUTPUTCLR0: CLRn11 Position */
+#define SCT_OUTPUTCLR0_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn11_Pos) /*!< SCT OUTPUTCLR0: CLRn11 Mask */
+#define SCT_OUTPUTCLR0_CLRn12_Pos 12 /*!< SCT OUTPUTCLR0: CLRn12 Position */
+#define SCT_OUTPUTCLR0_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn12_Pos) /*!< SCT OUTPUTCLR0: CLRn12 Mask */
+#define SCT_OUTPUTCLR0_CLRn13_Pos 13 /*!< SCT OUTPUTCLR0: CLRn13 Position */
+#define SCT_OUTPUTCLR0_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn13_Pos) /*!< SCT OUTPUTCLR0: CLRn13 Mask */
+#define SCT_OUTPUTCLR0_CLRn14_Pos 14 /*!< SCT OUTPUTCLR0: CLRn14 Position */
+#define SCT_OUTPUTCLR0_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn14_Pos) /*!< SCT OUTPUTCLR0: CLRn14 Mask */
+#define SCT_OUTPUTCLR0_CLRn15_Pos 15 /*!< SCT OUTPUTCLR0: CLRn15 Position */
+#define SCT_OUTPUTCLR0_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn15_Pos) /*!< SCT OUTPUTCLR0: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET1 -----------------------------------------
+#define SCT_OUTPUTSET1_SETn0_Pos 0 /*!< SCT OUTPUTSET1: SETn0 Position */
+#define SCT_OUTPUTSET1_SETn0_Msk (0x01UL << SCT_OUTPUTSET1_SETn0_Pos) /*!< SCT OUTPUTSET1: SETn0 Mask */
+#define SCT_OUTPUTSET1_SETn1_Pos 1 /*!< SCT OUTPUTSET1: SETn1 Position */
+#define SCT_OUTPUTSET1_SETn1_Msk (0x01UL << SCT_OUTPUTSET1_SETn1_Pos) /*!< SCT OUTPUTSET1: SETn1 Mask */
+#define SCT_OUTPUTSET1_SETn2_Pos 2 /*!< SCT OUTPUTSET1: SETn2 Position */
+#define SCT_OUTPUTSET1_SETn2_Msk (0x01UL << SCT_OUTPUTSET1_SETn2_Pos) /*!< SCT OUTPUTSET1: SETn2 Mask */
+#define SCT_OUTPUTSET1_SETn3_Pos 3 /*!< SCT OUTPUTSET1: SETn3 Position */
+#define SCT_OUTPUTSET1_SETn3_Msk (0x01UL << SCT_OUTPUTSET1_SETn3_Pos) /*!< SCT OUTPUTSET1: SETn3 Mask */
+#define SCT_OUTPUTSET1_SETn4_Pos 4 /*!< SCT OUTPUTSET1: SETn4 Position */
+#define SCT_OUTPUTSET1_SETn4_Msk (0x01UL << SCT_OUTPUTSET1_SETn4_Pos) /*!< SCT OUTPUTSET1: SETn4 Mask */
+#define SCT_OUTPUTSET1_SETn5_Pos 5 /*!< SCT OUTPUTSET1: SETn5 Position */
+#define SCT_OUTPUTSET1_SETn5_Msk (0x01UL << SCT_OUTPUTSET1_SETn5_Pos) /*!< SCT OUTPUTSET1: SETn5 Mask */
+#define SCT_OUTPUTSET1_SETn6_Pos 6 /*!< SCT OUTPUTSET1: SETn6 Position */
+#define SCT_OUTPUTSET1_SETn6_Msk (0x01UL << SCT_OUTPUTSET1_SETn6_Pos) /*!< SCT OUTPUTSET1: SETn6 Mask */
+#define SCT_OUTPUTSET1_SETn7_Pos 7 /*!< SCT OUTPUTSET1: SETn7 Position */
+#define SCT_OUTPUTSET1_SETn7_Msk (0x01UL << SCT_OUTPUTSET1_SETn7_Pos) /*!< SCT OUTPUTSET1: SETn7 Mask */
+#define SCT_OUTPUTSET1_SETn8_Pos 8 /*!< SCT OUTPUTSET1: SETn8 Position */
+#define SCT_OUTPUTSET1_SETn8_Msk (0x01UL << SCT_OUTPUTSET1_SETn8_Pos) /*!< SCT OUTPUTSET1: SETn8 Mask */
+#define SCT_OUTPUTSET1_SETn9_Pos 9 /*!< SCT OUTPUTSET1: SETn9 Position */
+#define SCT_OUTPUTSET1_SETn9_Msk (0x01UL << SCT_OUTPUTSET1_SETn9_Pos) /*!< SCT OUTPUTSET1: SETn9 Mask */
+#define SCT_OUTPUTSET1_SETn10_Pos 10 /*!< SCT OUTPUTSET1: SETn10 Position */
+#define SCT_OUTPUTSET1_SETn10_Msk (0x01UL << SCT_OUTPUTSET1_SETn10_Pos) /*!< SCT OUTPUTSET1: SETn10 Mask */
+#define SCT_OUTPUTSET1_SETn11_Pos 11 /*!< SCT OUTPUTSET1: SETn11 Position */
+#define SCT_OUTPUTSET1_SETn11_Msk (0x01UL << SCT_OUTPUTSET1_SETn11_Pos) /*!< SCT OUTPUTSET1: SETn11 Mask */
+#define SCT_OUTPUTSET1_SETn12_Pos 12 /*!< SCT OUTPUTSET1: SETn12 Position */
+#define SCT_OUTPUTSET1_SETn12_Msk (0x01UL << SCT_OUTPUTSET1_SETn12_Pos) /*!< SCT OUTPUTSET1: SETn12 Mask */
+#define SCT_OUTPUTSET1_SETn13_Pos 13 /*!< SCT OUTPUTSET1: SETn13 Position */
+#define SCT_OUTPUTSET1_SETn13_Msk (0x01UL << SCT_OUTPUTSET1_SETn13_Pos) /*!< SCT OUTPUTSET1: SETn13 Mask */
+#define SCT_OUTPUTSET1_SETn14_Pos 14 /*!< SCT OUTPUTSET1: SETn14 Position */
+#define SCT_OUTPUTSET1_SETn14_Msk (0x01UL << SCT_OUTPUTSET1_SETn14_Pos) /*!< SCT OUTPUTSET1: SETn14 Mask */
+#define SCT_OUTPUTSET1_SETn15_Pos 15 /*!< SCT OUTPUTSET1: SETn15 Position */
+#define SCT_OUTPUTSET1_SETn15_Msk (0x01UL << SCT_OUTPUTSET1_SETn15_Pos) /*!< SCT OUTPUTSET1: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR1 -----------------------------------------
+#define SCT_OUTPUTCLR1_CLRn0_Pos 0 /*!< SCT OUTPUTCLR1: CLRn0 Position */
+#define SCT_OUTPUTCLR1_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn0_Pos) /*!< SCT OUTPUTCLR1: CLRn0 Mask */
+#define SCT_OUTPUTCLR1_CLRn1_Pos 1 /*!< SCT OUTPUTCLR1: CLRn1 Position */
+#define SCT_OUTPUTCLR1_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn1_Pos) /*!< SCT OUTPUTCLR1: CLRn1 Mask */
+#define SCT_OUTPUTCLR1_CLRn2_Pos 2 /*!< SCT OUTPUTCLR1: CLRn2 Position */
+#define SCT_OUTPUTCLR1_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn2_Pos) /*!< SCT OUTPUTCLR1: CLRn2 Mask */
+#define SCT_OUTPUTCLR1_CLRn3_Pos 3 /*!< SCT OUTPUTCLR1: CLRn3 Position */
+#define SCT_OUTPUTCLR1_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn3_Pos) /*!< SCT OUTPUTCLR1: CLRn3 Mask */
+#define SCT_OUTPUTCLR1_CLRn4_Pos 4 /*!< SCT OUTPUTCLR1: CLRn4 Position */
+#define SCT_OUTPUTCLR1_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn4_Pos) /*!< SCT OUTPUTCLR1: CLRn4 Mask */
+#define SCT_OUTPUTCLR1_CLRn5_Pos 5 /*!< SCT OUTPUTCLR1: CLRn5 Position */
+#define SCT_OUTPUTCLR1_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn5_Pos) /*!< SCT OUTPUTCLR1: CLRn5 Mask */
+#define SCT_OUTPUTCLR1_CLRn6_Pos 6 /*!< SCT OUTPUTCLR1: CLRn6 Position */
+#define SCT_OUTPUTCLR1_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn6_Pos) /*!< SCT OUTPUTCLR1: CLRn6 Mask */
+#define SCT_OUTPUTCLR1_CLRn7_Pos 7 /*!< SCT OUTPUTCLR1: CLRn7 Position */
+#define SCT_OUTPUTCLR1_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn7_Pos) /*!< SCT OUTPUTCLR1: CLRn7 Mask */
+#define SCT_OUTPUTCLR1_CLRn8_Pos 8 /*!< SCT OUTPUTCLR1: CLRn8 Position */
+#define SCT_OUTPUTCLR1_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn8_Pos) /*!< SCT OUTPUTCLR1: CLRn8 Mask */
+#define SCT_OUTPUTCLR1_CLRn9_Pos 9 /*!< SCT OUTPUTCLR1: CLRn9 Position */
+#define SCT_OUTPUTCLR1_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn9_Pos) /*!< SCT OUTPUTCLR1: CLRn9 Mask */
+#define SCT_OUTPUTCLR1_CLRn10_Pos 10 /*!< SCT OUTPUTCLR1: CLRn10 Position */
+#define SCT_OUTPUTCLR1_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn10_Pos) /*!< SCT OUTPUTCLR1: CLRn10 Mask */
+#define SCT_OUTPUTCLR1_CLRn11_Pos 11 /*!< SCT OUTPUTCLR1: CLRn11 Position */
+#define SCT_OUTPUTCLR1_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn11_Pos) /*!< SCT OUTPUTCLR1: CLRn11 Mask */
+#define SCT_OUTPUTCLR1_CLRn12_Pos 12 /*!< SCT OUTPUTCLR1: CLRn12 Position */
+#define SCT_OUTPUTCLR1_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn12_Pos) /*!< SCT OUTPUTCLR1: CLRn12 Mask */
+#define SCT_OUTPUTCLR1_CLRn13_Pos 13 /*!< SCT OUTPUTCLR1: CLRn13 Position */
+#define SCT_OUTPUTCLR1_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn13_Pos) /*!< SCT OUTPUTCLR1: CLRn13 Mask */
+#define SCT_OUTPUTCLR1_CLRn14_Pos 14 /*!< SCT OUTPUTCLR1: CLRn14 Position */
+#define SCT_OUTPUTCLR1_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn14_Pos) /*!< SCT OUTPUTCLR1: CLRn14 Mask */
+#define SCT_OUTPUTCLR1_CLRn15_Pos 15 /*!< SCT OUTPUTCLR1: CLRn15 Position */
+#define SCT_OUTPUTCLR1_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn15_Pos) /*!< SCT OUTPUTCLR1: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET2 -----------------------------------------
+#define SCT_OUTPUTSET2_SETn0_Pos 0 /*!< SCT OUTPUTSET2: SETn0 Position */
+#define SCT_OUTPUTSET2_SETn0_Msk (0x01UL << SCT_OUTPUTSET2_SETn0_Pos) /*!< SCT OUTPUTSET2: SETn0 Mask */
+#define SCT_OUTPUTSET2_SETn1_Pos 1 /*!< SCT OUTPUTSET2: SETn1 Position */
+#define SCT_OUTPUTSET2_SETn1_Msk (0x01UL << SCT_OUTPUTSET2_SETn1_Pos) /*!< SCT OUTPUTSET2: SETn1 Mask */
+#define SCT_OUTPUTSET2_SETn2_Pos 2 /*!< SCT OUTPUTSET2: SETn2 Position */
+#define SCT_OUTPUTSET2_SETn2_Msk (0x01UL << SCT_OUTPUTSET2_SETn2_Pos) /*!< SCT OUTPUTSET2: SETn2 Mask */
+#define SCT_OUTPUTSET2_SETn3_Pos 3 /*!< SCT OUTPUTSET2: SETn3 Position */
+#define SCT_OUTPUTSET2_SETn3_Msk (0x01UL << SCT_OUTPUTSET2_SETn3_Pos) /*!< SCT OUTPUTSET2: SETn3 Mask */
+#define SCT_OUTPUTSET2_SETn4_Pos 4 /*!< SCT OUTPUTSET2: SETn4 Position */
+#define SCT_OUTPUTSET2_SETn4_Msk (0x01UL << SCT_OUTPUTSET2_SETn4_Pos) /*!< SCT OUTPUTSET2: SETn4 Mask */
+#define SCT_OUTPUTSET2_SETn5_Pos 5 /*!< SCT OUTPUTSET2: SETn5 Position */
+#define SCT_OUTPUTSET2_SETn5_Msk (0x01UL << SCT_OUTPUTSET2_SETn5_Pos) /*!< SCT OUTPUTSET2: SETn5 Mask */
+#define SCT_OUTPUTSET2_SETn6_Pos 6 /*!< SCT OUTPUTSET2: SETn6 Position */
+#define SCT_OUTPUTSET2_SETn6_Msk (0x01UL << SCT_OUTPUTSET2_SETn6_Pos) /*!< SCT OUTPUTSET2: SETn6 Mask */
+#define SCT_OUTPUTSET2_SETn7_Pos 7 /*!< SCT OUTPUTSET2: SETn7 Position */
+#define SCT_OUTPUTSET2_SETn7_Msk (0x01UL << SCT_OUTPUTSET2_SETn7_Pos) /*!< SCT OUTPUTSET2: SETn7 Mask */
+#define SCT_OUTPUTSET2_SETn8_Pos 8 /*!< SCT OUTPUTSET2: SETn8 Position */
+#define SCT_OUTPUTSET2_SETn8_Msk (0x01UL << SCT_OUTPUTSET2_SETn8_Pos) /*!< SCT OUTPUTSET2: SETn8 Mask */
+#define SCT_OUTPUTSET2_SETn9_Pos 9 /*!< SCT OUTPUTSET2: SETn9 Position */
+#define SCT_OUTPUTSET2_SETn9_Msk (0x01UL << SCT_OUTPUTSET2_SETn9_Pos) /*!< SCT OUTPUTSET2: SETn9 Mask */
+#define SCT_OUTPUTSET2_SETn10_Pos 10 /*!< SCT OUTPUTSET2: SETn10 Position */
+#define SCT_OUTPUTSET2_SETn10_Msk (0x01UL << SCT_OUTPUTSET2_SETn10_Pos) /*!< SCT OUTPUTSET2: SETn10 Mask */
+#define SCT_OUTPUTSET2_SETn11_Pos 11 /*!< SCT OUTPUTSET2: SETn11 Position */
+#define SCT_OUTPUTSET2_SETn11_Msk (0x01UL << SCT_OUTPUTSET2_SETn11_Pos) /*!< SCT OUTPUTSET2: SETn11 Mask */
+#define SCT_OUTPUTSET2_SETn12_Pos 12 /*!< SCT OUTPUTSET2: SETn12 Position */
+#define SCT_OUTPUTSET2_SETn12_Msk (0x01UL << SCT_OUTPUTSET2_SETn12_Pos) /*!< SCT OUTPUTSET2: SETn12 Mask */
+#define SCT_OUTPUTSET2_SETn13_Pos 13 /*!< SCT OUTPUTSET2: SETn13 Position */
+#define SCT_OUTPUTSET2_SETn13_Msk (0x01UL << SCT_OUTPUTSET2_SETn13_Pos) /*!< SCT OUTPUTSET2: SETn13 Mask */
+#define SCT_OUTPUTSET2_SETn14_Pos 14 /*!< SCT OUTPUTSET2: SETn14 Position */
+#define SCT_OUTPUTSET2_SETn14_Msk (0x01UL << SCT_OUTPUTSET2_SETn14_Pos) /*!< SCT OUTPUTSET2: SETn14 Mask */
+#define SCT_OUTPUTSET2_SETn15_Pos 15 /*!< SCT OUTPUTSET2: SETn15 Position */
+#define SCT_OUTPUTSET2_SETn15_Msk (0x01UL << SCT_OUTPUTSET2_SETn15_Pos) /*!< SCT OUTPUTSET2: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR2 -----------------------------------------
+#define SCT_OUTPUTCLR2_CLRn0_Pos 0 /*!< SCT OUTPUTCLR2: CLRn0 Position */
+#define SCT_OUTPUTCLR2_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn0_Pos) /*!< SCT OUTPUTCLR2: CLRn0 Mask */
+#define SCT_OUTPUTCLR2_CLRn1_Pos 1 /*!< SCT OUTPUTCLR2: CLRn1 Position */
+#define SCT_OUTPUTCLR2_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn1_Pos) /*!< SCT OUTPUTCLR2: CLRn1 Mask */
+#define SCT_OUTPUTCLR2_CLRn2_Pos 2 /*!< SCT OUTPUTCLR2: CLRn2 Position */
+#define SCT_OUTPUTCLR2_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn2_Pos) /*!< SCT OUTPUTCLR2: CLRn2 Mask */
+#define SCT_OUTPUTCLR2_CLRn3_Pos 3 /*!< SCT OUTPUTCLR2: CLRn3 Position */
+#define SCT_OUTPUTCLR2_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn3_Pos) /*!< SCT OUTPUTCLR2: CLRn3 Mask */
+#define SCT_OUTPUTCLR2_CLRn4_Pos 4 /*!< SCT OUTPUTCLR2: CLRn4 Position */
+#define SCT_OUTPUTCLR2_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn4_Pos) /*!< SCT OUTPUTCLR2: CLRn4 Mask */
+#define SCT_OUTPUTCLR2_CLRn5_Pos 5 /*!< SCT OUTPUTCLR2: CLRn5 Position */
+#define SCT_OUTPUTCLR2_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn5_Pos) /*!< SCT OUTPUTCLR2: CLRn5 Mask */
+#define SCT_OUTPUTCLR2_CLRn6_Pos 6 /*!< SCT OUTPUTCLR2: CLRn6 Position */
+#define SCT_OUTPUTCLR2_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn6_Pos) /*!< SCT OUTPUTCLR2: CLRn6 Mask */
+#define SCT_OUTPUTCLR2_CLRn7_Pos 7 /*!< SCT OUTPUTCLR2: CLRn7 Position */
+#define SCT_OUTPUTCLR2_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn7_Pos) /*!< SCT OUTPUTCLR2: CLRn7 Mask */
+#define SCT_OUTPUTCLR2_CLRn8_Pos 8 /*!< SCT OUTPUTCLR2: CLRn8 Position */
+#define SCT_OUTPUTCLR2_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn8_Pos) /*!< SCT OUTPUTCLR2: CLRn8 Mask */
+#define SCT_OUTPUTCLR2_CLRn9_Pos 9 /*!< SCT OUTPUTCLR2: CLRn9 Position */
+#define SCT_OUTPUTCLR2_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn9_Pos) /*!< SCT OUTPUTCLR2: CLRn9 Mask */
+#define SCT_OUTPUTCLR2_CLRn10_Pos 10 /*!< SCT OUTPUTCLR2: CLRn10 Position */
+#define SCT_OUTPUTCLR2_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn10_Pos) /*!< SCT OUTPUTCLR2: CLRn10 Mask */
+#define SCT_OUTPUTCLR2_CLRn11_Pos 11 /*!< SCT OUTPUTCLR2: CLRn11 Position */
+#define SCT_OUTPUTCLR2_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn11_Pos) /*!< SCT OUTPUTCLR2: CLRn11 Mask */
+#define SCT_OUTPUTCLR2_CLRn12_Pos 12 /*!< SCT OUTPUTCLR2: CLRn12 Position */
+#define SCT_OUTPUTCLR2_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn12_Pos) /*!< SCT OUTPUTCLR2: CLRn12 Mask */
+#define SCT_OUTPUTCLR2_CLRn13_Pos 13 /*!< SCT OUTPUTCLR2: CLRn13 Position */
+#define SCT_OUTPUTCLR2_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn13_Pos) /*!< SCT OUTPUTCLR2: CLRn13 Mask */
+#define SCT_OUTPUTCLR2_CLRn14_Pos 14 /*!< SCT OUTPUTCLR2: CLRn14 Position */
+#define SCT_OUTPUTCLR2_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn14_Pos) /*!< SCT OUTPUTCLR2: CLRn14 Mask */
+#define SCT_OUTPUTCLR2_CLRn15_Pos 15 /*!< SCT OUTPUTCLR2: CLRn15 Position */
+#define SCT_OUTPUTCLR2_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn15_Pos) /*!< SCT OUTPUTCLR2: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET3 -----------------------------------------
+#define SCT_OUTPUTSET3_SETn0_Pos 0 /*!< SCT OUTPUTSET3: SETn0 Position */
+#define SCT_OUTPUTSET3_SETn0_Msk (0x01UL << SCT_OUTPUTSET3_SETn0_Pos) /*!< SCT OUTPUTSET3: SETn0 Mask */
+#define SCT_OUTPUTSET3_SETn1_Pos 1 /*!< SCT OUTPUTSET3: SETn1 Position */
+#define SCT_OUTPUTSET3_SETn1_Msk (0x01UL << SCT_OUTPUTSET3_SETn1_Pos) /*!< SCT OUTPUTSET3: SETn1 Mask */
+#define SCT_OUTPUTSET3_SETn2_Pos 2 /*!< SCT OUTPUTSET3: SETn2 Position */
+#define SCT_OUTPUTSET3_SETn2_Msk (0x01UL << SCT_OUTPUTSET3_SETn2_Pos) /*!< SCT OUTPUTSET3: SETn2 Mask */
+#define SCT_OUTPUTSET3_SETn3_Pos 3 /*!< SCT OUTPUTSET3: SETn3 Position */
+#define SCT_OUTPUTSET3_SETn3_Msk (0x01UL << SCT_OUTPUTSET3_SETn3_Pos) /*!< SCT OUTPUTSET3: SETn3 Mask */
+#define SCT_OUTPUTSET3_SETn4_Pos 4 /*!< SCT OUTPUTSET3: SETn4 Position */
+#define SCT_OUTPUTSET3_SETn4_Msk (0x01UL << SCT_OUTPUTSET3_SETn4_Pos) /*!< SCT OUTPUTSET3: SETn4 Mask */
+#define SCT_OUTPUTSET3_SETn5_Pos 5 /*!< SCT OUTPUTSET3: SETn5 Position */
+#define SCT_OUTPUTSET3_SETn5_Msk (0x01UL << SCT_OUTPUTSET3_SETn5_Pos) /*!< SCT OUTPUTSET3: SETn5 Mask */
+#define SCT_OUTPUTSET3_SETn6_Pos 6 /*!< SCT OUTPUTSET3: SETn6 Position */
+#define SCT_OUTPUTSET3_SETn6_Msk (0x01UL << SCT_OUTPUTSET3_SETn6_Pos) /*!< SCT OUTPUTSET3: SETn6 Mask */
+#define SCT_OUTPUTSET3_SETn7_Pos 7 /*!< SCT OUTPUTSET3: SETn7 Position */
+#define SCT_OUTPUTSET3_SETn7_Msk (0x01UL << SCT_OUTPUTSET3_SETn7_Pos) /*!< SCT OUTPUTSET3: SETn7 Mask */
+#define SCT_OUTPUTSET3_SETn8_Pos 8 /*!< SCT OUTPUTSET3: SETn8 Position */
+#define SCT_OUTPUTSET3_SETn8_Msk (0x01UL << SCT_OUTPUTSET3_SETn8_Pos) /*!< SCT OUTPUTSET3: SETn8 Mask */
+#define SCT_OUTPUTSET3_SETn9_Pos 9 /*!< SCT OUTPUTSET3: SETn9 Position */
+#define SCT_OUTPUTSET3_SETn9_Msk (0x01UL << SCT_OUTPUTSET3_SETn9_Pos) /*!< SCT OUTPUTSET3: SETn9 Mask */
+#define SCT_OUTPUTSET3_SETn10_Pos 10 /*!< SCT OUTPUTSET3: SETn10 Position */
+#define SCT_OUTPUTSET3_SETn10_Msk (0x01UL << SCT_OUTPUTSET3_SETn10_Pos) /*!< SCT OUTPUTSET3: SETn10 Mask */
+#define SCT_OUTPUTSET3_SETn11_Pos 11 /*!< SCT OUTPUTSET3: SETn11 Position */
+#define SCT_OUTPUTSET3_SETn11_Msk (0x01UL << SCT_OUTPUTSET3_SETn11_Pos) /*!< SCT OUTPUTSET3: SETn11 Mask */
+#define SCT_OUTPUTSET3_SETn12_Pos 12 /*!< SCT OUTPUTSET3: SETn12 Position */
+#define SCT_OUTPUTSET3_SETn12_Msk (0x01UL << SCT_OUTPUTSET3_SETn12_Pos) /*!< SCT OUTPUTSET3: SETn12 Mask */
+#define SCT_OUTPUTSET3_SETn13_Pos 13 /*!< SCT OUTPUTSET3: SETn13 Position */
+#define SCT_OUTPUTSET3_SETn13_Msk (0x01UL << SCT_OUTPUTSET3_SETn13_Pos) /*!< SCT OUTPUTSET3: SETn13 Mask */
+#define SCT_OUTPUTSET3_SETn14_Pos 14 /*!< SCT OUTPUTSET3: SETn14 Position */
+#define SCT_OUTPUTSET3_SETn14_Msk (0x01UL << SCT_OUTPUTSET3_SETn14_Pos) /*!< SCT OUTPUTSET3: SETn14 Mask */
+#define SCT_OUTPUTSET3_SETn15_Pos 15 /*!< SCT OUTPUTSET3: SETn15 Position */
+#define SCT_OUTPUTSET3_SETn15_Msk (0x01UL << SCT_OUTPUTSET3_SETn15_Pos) /*!< SCT OUTPUTSET3: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR3 -----------------------------------------
+#define SCT_OUTPUTCLR3_CLRn0_Pos 0 /*!< SCT OUTPUTCLR3: CLRn0 Position */
+#define SCT_OUTPUTCLR3_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn0_Pos) /*!< SCT OUTPUTCLR3: CLRn0 Mask */
+#define SCT_OUTPUTCLR3_CLRn1_Pos 1 /*!< SCT OUTPUTCLR3: CLRn1 Position */
+#define SCT_OUTPUTCLR3_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn1_Pos) /*!< SCT OUTPUTCLR3: CLRn1 Mask */
+#define SCT_OUTPUTCLR3_CLRn2_Pos 2 /*!< SCT OUTPUTCLR3: CLRn2 Position */
+#define SCT_OUTPUTCLR3_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn2_Pos) /*!< SCT OUTPUTCLR3: CLRn2 Mask */
+#define SCT_OUTPUTCLR3_CLRn3_Pos 3 /*!< SCT OUTPUTCLR3: CLRn3 Position */
+#define SCT_OUTPUTCLR3_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn3_Pos) /*!< SCT OUTPUTCLR3: CLRn3 Mask */
+#define SCT_OUTPUTCLR3_CLRn4_Pos 4 /*!< SCT OUTPUTCLR3: CLRn4 Position */
+#define SCT_OUTPUTCLR3_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn4_Pos) /*!< SCT OUTPUTCLR3: CLRn4 Mask */
+#define SCT_OUTPUTCLR3_CLRn5_Pos 5 /*!< SCT OUTPUTCLR3: CLRn5 Position */
+#define SCT_OUTPUTCLR3_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn5_Pos) /*!< SCT OUTPUTCLR3: CLRn5 Mask */
+#define SCT_OUTPUTCLR3_CLRn6_Pos 6 /*!< SCT OUTPUTCLR3: CLRn6 Position */
+#define SCT_OUTPUTCLR3_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn6_Pos) /*!< SCT OUTPUTCLR3: CLRn6 Mask */
+#define SCT_OUTPUTCLR3_CLRn7_Pos 7 /*!< SCT OUTPUTCLR3: CLRn7 Position */
+#define SCT_OUTPUTCLR3_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn7_Pos) /*!< SCT OUTPUTCLR3: CLRn7 Mask */
+#define SCT_OUTPUTCLR3_CLRn8_Pos 8 /*!< SCT OUTPUTCLR3: CLRn8 Position */
+#define SCT_OUTPUTCLR3_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn8_Pos) /*!< SCT OUTPUTCLR3: CLRn8 Mask */
+#define SCT_OUTPUTCLR3_CLRn9_Pos 9 /*!< SCT OUTPUTCLR3: CLRn9 Position */
+#define SCT_OUTPUTCLR3_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn9_Pos) /*!< SCT OUTPUTCLR3: CLRn9 Mask */
+#define SCT_OUTPUTCLR3_CLRn10_Pos 10 /*!< SCT OUTPUTCLR3: CLRn10 Position */
+#define SCT_OUTPUTCLR3_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn10_Pos) /*!< SCT OUTPUTCLR3: CLRn10 Mask */
+#define SCT_OUTPUTCLR3_CLRn11_Pos 11 /*!< SCT OUTPUTCLR3: CLRn11 Position */
+#define SCT_OUTPUTCLR3_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn11_Pos) /*!< SCT OUTPUTCLR3: CLRn11 Mask */
+#define SCT_OUTPUTCLR3_CLRn12_Pos 12 /*!< SCT OUTPUTCLR3: CLRn12 Position */
+#define SCT_OUTPUTCLR3_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn12_Pos) /*!< SCT OUTPUTCLR3: CLRn12 Mask */
+#define SCT_OUTPUTCLR3_CLRn13_Pos 13 /*!< SCT OUTPUTCLR3: CLRn13 Position */
+#define SCT_OUTPUTCLR3_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn13_Pos) /*!< SCT OUTPUTCLR3: CLRn13 Mask */
+#define SCT_OUTPUTCLR3_CLRn14_Pos 14 /*!< SCT OUTPUTCLR3: CLRn14 Position */
+#define SCT_OUTPUTCLR3_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn14_Pos) /*!< SCT OUTPUTCLR3: CLRn14 Mask */
+#define SCT_OUTPUTCLR3_CLRn15_Pos 15 /*!< SCT OUTPUTCLR3: CLRn15 Position */
+#define SCT_OUTPUTCLR3_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn15_Pos) /*!< SCT OUTPUTCLR3: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET4 -----------------------------------------
+#define SCT_OUTPUTSET4_SETn0_Pos 0 /*!< SCT OUTPUTSET4: SETn0 Position */
+#define SCT_OUTPUTSET4_SETn0_Msk (0x01UL << SCT_OUTPUTSET4_SETn0_Pos) /*!< SCT OUTPUTSET4: SETn0 Mask */
+#define SCT_OUTPUTSET4_SETn1_Pos 1 /*!< SCT OUTPUTSET4: SETn1 Position */
+#define SCT_OUTPUTSET4_SETn1_Msk (0x01UL << SCT_OUTPUTSET4_SETn1_Pos) /*!< SCT OUTPUTSET4: SETn1 Mask */
+#define SCT_OUTPUTSET4_SETn2_Pos 2 /*!< SCT OUTPUTSET4: SETn2 Position */
+#define SCT_OUTPUTSET4_SETn2_Msk (0x01UL << SCT_OUTPUTSET4_SETn2_Pos) /*!< SCT OUTPUTSET4: SETn2 Mask */
+#define SCT_OUTPUTSET4_SETn3_Pos 3 /*!< SCT OUTPUTSET4: SETn3 Position */
+#define SCT_OUTPUTSET4_SETn3_Msk (0x01UL << SCT_OUTPUTSET4_SETn3_Pos) /*!< SCT OUTPUTSET4: SETn3 Mask */
+#define SCT_OUTPUTSET4_SETn4_Pos 4 /*!< SCT OUTPUTSET4: SETn4 Position */
+#define SCT_OUTPUTSET4_SETn4_Msk (0x01UL << SCT_OUTPUTSET4_SETn4_Pos) /*!< SCT OUTPUTSET4: SETn4 Mask */
+#define SCT_OUTPUTSET4_SETn5_Pos 5 /*!< SCT OUTPUTSET4: SETn5 Position */
+#define SCT_OUTPUTSET4_SETn5_Msk (0x01UL << SCT_OUTPUTSET4_SETn5_Pos) /*!< SCT OUTPUTSET4: SETn5 Mask */
+#define SCT_OUTPUTSET4_SETn6_Pos 6 /*!< SCT OUTPUTSET4: SETn6 Position */
+#define SCT_OUTPUTSET4_SETn6_Msk (0x01UL << SCT_OUTPUTSET4_SETn6_Pos) /*!< SCT OUTPUTSET4: SETn6 Mask */
+#define SCT_OUTPUTSET4_SETn7_Pos 7 /*!< SCT OUTPUTSET4: SETn7 Position */
+#define SCT_OUTPUTSET4_SETn7_Msk (0x01UL << SCT_OUTPUTSET4_SETn7_Pos) /*!< SCT OUTPUTSET4: SETn7 Mask */
+#define SCT_OUTPUTSET4_SETn8_Pos 8 /*!< SCT OUTPUTSET4: SETn8 Position */
+#define SCT_OUTPUTSET4_SETn8_Msk (0x01UL << SCT_OUTPUTSET4_SETn8_Pos) /*!< SCT OUTPUTSET4: SETn8 Mask */
+#define SCT_OUTPUTSET4_SETn9_Pos 9 /*!< SCT OUTPUTSET4: SETn9 Position */
+#define SCT_OUTPUTSET4_SETn9_Msk (0x01UL << SCT_OUTPUTSET4_SETn9_Pos) /*!< SCT OUTPUTSET4: SETn9 Mask */
+#define SCT_OUTPUTSET4_SETn10_Pos 10 /*!< SCT OUTPUTSET4: SETn10 Position */
+#define SCT_OUTPUTSET4_SETn10_Msk (0x01UL << SCT_OUTPUTSET4_SETn10_Pos) /*!< SCT OUTPUTSET4: SETn10 Mask */
+#define SCT_OUTPUTSET4_SETn11_Pos 11 /*!< SCT OUTPUTSET4: SETn11 Position */
+#define SCT_OUTPUTSET4_SETn11_Msk (0x01UL << SCT_OUTPUTSET4_SETn11_Pos) /*!< SCT OUTPUTSET4: SETn11 Mask */
+#define SCT_OUTPUTSET4_SETn12_Pos 12 /*!< SCT OUTPUTSET4: SETn12 Position */
+#define SCT_OUTPUTSET4_SETn12_Msk (0x01UL << SCT_OUTPUTSET4_SETn12_Pos) /*!< SCT OUTPUTSET4: SETn12 Mask */
+#define SCT_OUTPUTSET4_SETn13_Pos 13 /*!< SCT OUTPUTSET4: SETn13 Position */
+#define SCT_OUTPUTSET4_SETn13_Msk (0x01UL << SCT_OUTPUTSET4_SETn13_Pos) /*!< SCT OUTPUTSET4: SETn13 Mask */
+#define SCT_OUTPUTSET4_SETn14_Pos 14 /*!< SCT OUTPUTSET4: SETn14 Position */
+#define SCT_OUTPUTSET4_SETn14_Msk (0x01UL << SCT_OUTPUTSET4_SETn14_Pos) /*!< SCT OUTPUTSET4: SETn14 Mask */
+#define SCT_OUTPUTSET4_SETn15_Pos 15 /*!< SCT OUTPUTSET4: SETn15 Position */
+#define SCT_OUTPUTSET4_SETn15_Msk (0x01UL << SCT_OUTPUTSET4_SETn15_Pos) /*!< SCT OUTPUTSET4: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR4 -----------------------------------------
+#define SCT_OUTPUTCLR4_CLRn0_Pos 0 /*!< SCT OUTPUTCLR4: CLRn0 Position */
+#define SCT_OUTPUTCLR4_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn0_Pos) /*!< SCT OUTPUTCLR4: CLRn0 Mask */
+#define SCT_OUTPUTCLR4_CLRn1_Pos 1 /*!< SCT OUTPUTCLR4: CLRn1 Position */
+#define SCT_OUTPUTCLR4_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn1_Pos) /*!< SCT OUTPUTCLR4: CLRn1 Mask */
+#define SCT_OUTPUTCLR4_CLRn2_Pos 2 /*!< SCT OUTPUTCLR4: CLRn2 Position */
+#define SCT_OUTPUTCLR4_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn2_Pos) /*!< SCT OUTPUTCLR4: CLRn2 Mask */
+#define SCT_OUTPUTCLR4_CLRn3_Pos 3 /*!< SCT OUTPUTCLR4: CLRn3 Position */
+#define SCT_OUTPUTCLR4_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn3_Pos) /*!< SCT OUTPUTCLR4: CLRn3 Mask */
+#define SCT_OUTPUTCLR4_CLRn4_Pos 4 /*!< SCT OUTPUTCLR4: CLRn4 Position */
+#define SCT_OUTPUTCLR4_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn4_Pos) /*!< SCT OUTPUTCLR4: CLRn4 Mask */
+#define SCT_OUTPUTCLR4_CLRn5_Pos 5 /*!< SCT OUTPUTCLR4: CLRn5 Position */
+#define SCT_OUTPUTCLR4_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn5_Pos) /*!< SCT OUTPUTCLR4: CLRn5 Mask */
+#define SCT_OUTPUTCLR4_CLRn6_Pos 6 /*!< SCT OUTPUTCLR4: CLRn6 Position */
+#define SCT_OUTPUTCLR4_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn6_Pos) /*!< SCT OUTPUTCLR4: CLRn6 Mask */
+#define SCT_OUTPUTCLR4_CLRn7_Pos 7 /*!< SCT OUTPUTCLR4: CLRn7 Position */
+#define SCT_OUTPUTCLR4_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn7_Pos) /*!< SCT OUTPUTCLR4: CLRn7 Mask */
+#define SCT_OUTPUTCLR4_CLRn8_Pos 8 /*!< SCT OUTPUTCLR4: CLRn8 Position */
+#define SCT_OUTPUTCLR4_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn8_Pos) /*!< SCT OUTPUTCLR4: CLRn8 Mask */
+#define SCT_OUTPUTCLR4_CLRn9_Pos 9 /*!< SCT OUTPUTCLR4: CLRn9 Position */
+#define SCT_OUTPUTCLR4_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn9_Pos) /*!< SCT OUTPUTCLR4: CLRn9 Mask */
+#define SCT_OUTPUTCLR4_CLRn10_Pos 10 /*!< SCT OUTPUTCLR4: CLRn10 Position */
+#define SCT_OUTPUTCLR4_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn10_Pos) /*!< SCT OUTPUTCLR4: CLRn10 Mask */
+#define SCT_OUTPUTCLR4_CLRn11_Pos 11 /*!< SCT OUTPUTCLR4: CLRn11 Position */
+#define SCT_OUTPUTCLR4_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn11_Pos) /*!< SCT OUTPUTCLR4: CLRn11 Mask */
+#define SCT_OUTPUTCLR4_CLRn12_Pos 12 /*!< SCT OUTPUTCLR4: CLRn12 Position */
+#define SCT_OUTPUTCLR4_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn12_Pos) /*!< SCT OUTPUTCLR4: CLRn12 Mask */
+#define SCT_OUTPUTCLR4_CLRn13_Pos 13 /*!< SCT OUTPUTCLR4: CLRn13 Position */
+#define SCT_OUTPUTCLR4_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn13_Pos) /*!< SCT OUTPUTCLR4: CLRn13 Mask */
+#define SCT_OUTPUTCLR4_CLRn14_Pos 14 /*!< SCT OUTPUTCLR4: CLRn14 Position */
+#define SCT_OUTPUTCLR4_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn14_Pos) /*!< SCT OUTPUTCLR4: CLRn14 Mask */
+#define SCT_OUTPUTCLR4_CLRn15_Pos 15 /*!< SCT OUTPUTCLR4: CLRn15 Position */
+#define SCT_OUTPUTCLR4_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn15_Pos) /*!< SCT OUTPUTCLR4: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET5 -----------------------------------------
+#define SCT_OUTPUTSET5_SETn0_Pos 0 /*!< SCT OUTPUTSET5: SETn0 Position */
+#define SCT_OUTPUTSET5_SETn0_Msk (0x01UL << SCT_OUTPUTSET5_SETn0_Pos) /*!< SCT OUTPUTSET5: SETn0 Mask */
+#define SCT_OUTPUTSET5_SETn1_Pos 1 /*!< SCT OUTPUTSET5: SETn1 Position */
+#define SCT_OUTPUTSET5_SETn1_Msk (0x01UL << SCT_OUTPUTSET5_SETn1_Pos) /*!< SCT OUTPUTSET5: SETn1 Mask */
+#define SCT_OUTPUTSET5_SETn2_Pos 2 /*!< SCT OUTPUTSET5: SETn2 Position */
+#define SCT_OUTPUTSET5_SETn2_Msk (0x01UL << SCT_OUTPUTSET5_SETn2_Pos) /*!< SCT OUTPUTSET5: SETn2 Mask */
+#define SCT_OUTPUTSET5_SETn3_Pos 3 /*!< SCT OUTPUTSET5: SETn3 Position */
+#define SCT_OUTPUTSET5_SETn3_Msk (0x01UL << SCT_OUTPUTSET5_SETn3_Pos) /*!< SCT OUTPUTSET5: SETn3 Mask */
+#define SCT_OUTPUTSET5_SETn4_Pos 4 /*!< SCT OUTPUTSET5: SETn4 Position */
+#define SCT_OUTPUTSET5_SETn4_Msk (0x01UL << SCT_OUTPUTSET5_SETn4_Pos) /*!< SCT OUTPUTSET5: SETn4 Mask */
+#define SCT_OUTPUTSET5_SETn5_Pos 5 /*!< SCT OUTPUTSET5: SETn5 Position */
+#define SCT_OUTPUTSET5_SETn5_Msk (0x01UL << SCT_OUTPUTSET5_SETn5_Pos) /*!< SCT OUTPUTSET5: SETn5 Mask */
+#define SCT_OUTPUTSET5_SETn6_Pos 6 /*!< SCT OUTPUTSET5: SETn6 Position */
+#define SCT_OUTPUTSET5_SETn6_Msk (0x01UL << SCT_OUTPUTSET5_SETn6_Pos) /*!< SCT OUTPUTSET5: SETn6 Mask */
+#define SCT_OUTPUTSET5_SETn7_Pos 7 /*!< SCT OUTPUTSET5: SETn7 Position */
+#define SCT_OUTPUTSET5_SETn7_Msk (0x01UL << SCT_OUTPUTSET5_SETn7_Pos) /*!< SCT OUTPUTSET5: SETn7 Mask */
+#define SCT_OUTPUTSET5_SETn8_Pos 8 /*!< SCT OUTPUTSET5: SETn8 Position */
+#define SCT_OUTPUTSET5_SETn8_Msk (0x01UL << SCT_OUTPUTSET5_SETn8_Pos) /*!< SCT OUTPUTSET5: SETn8 Mask */
+#define SCT_OUTPUTSET5_SETn9_Pos 9 /*!< SCT OUTPUTSET5: SETn9 Position */
+#define SCT_OUTPUTSET5_SETn9_Msk (0x01UL << SCT_OUTPUTSET5_SETn9_Pos) /*!< SCT OUTPUTSET5: SETn9 Mask */
+#define SCT_OUTPUTSET5_SETn10_Pos 10 /*!< SCT OUTPUTSET5: SETn10 Position */
+#define SCT_OUTPUTSET5_SETn10_Msk (0x01UL << SCT_OUTPUTSET5_SETn10_Pos) /*!< SCT OUTPUTSET5: SETn10 Mask */
+#define SCT_OUTPUTSET5_SETn11_Pos 11 /*!< SCT OUTPUTSET5: SETn11 Position */
+#define SCT_OUTPUTSET5_SETn11_Msk (0x01UL << SCT_OUTPUTSET5_SETn11_Pos) /*!< SCT OUTPUTSET5: SETn11 Mask */
+#define SCT_OUTPUTSET5_SETn12_Pos 12 /*!< SCT OUTPUTSET5: SETn12 Position */
+#define SCT_OUTPUTSET5_SETn12_Msk (0x01UL << SCT_OUTPUTSET5_SETn12_Pos) /*!< SCT OUTPUTSET5: SETn12 Mask */
+#define SCT_OUTPUTSET5_SETn13_Pos 13 /*!< SCT OUTPUTSET5: SETn13 Position */
+#define SCT_OUTPUTSET5_SETn13_Msk (0x01UL << SCT_OUTPUTSET5_SETn13_Pos) /*!< SCT OUTPUTSET5: SETn13 Mask */
+#define SCT_OUTPUTSET5_SETn14_Pos 14 /*!< SCT OUTPUTSET5: SETn14 Position */
+#define SCT_OUTPUTSET5_SETn14_Msk (0x01UL << SCT_OUTPUTSET5_SETn14_Pos) /*!< SCT OUTPUTSET5: SETn14 Mask */
+#define SCT_OUTPUTSET5_SETn15_Pos 15 /*!< SCT OUTPUTSET5: SETn15 Position */
+#define SCT_OUTPUTSET5_SETn15_Msk (0x01UL << SCT_OUTPUTSET5_SETn15_Pos) /*!< SCT OUTPUTSET5: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR5 -----------------------------------------
+#define SCT_OUTPUTCLR5_CLRn0_Pos 0 /*!< SCT OUTPUTCLR5: CLRn0 Position */
+#define SCT_OUTPUTCLR5_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn0_Pos) /*!< SCT OUTPUTCLR5: CLRn0 Mask */
+#define SCT_OUTPUTCLR5_CLRn1_Pos 1 /*!< SCT OUTPUTCLR5: CLRn1 Position */
+#define SCT_OUTPUTCLR5_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn1_Pos) /*!< SCT OUTPUTCLR5: CLRn1 Mask */
+#define SCT_OUTPUTCLR5_CLRn2_Pos 2 /*!< SCT OUTPUTCLR5: CLRn2 Position */
+#define SCT_OUTPUTCLR5_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn2_Pos) /*!< SCT OUTPUTCLR5: CLRn2 Mask */
+#define SCT_OUTPUTCLR5_CLRn3_Pos 3 /*!< SCT OUTPUTCLR5: CLRn3 Position */
+#define SCT_OUTPUTCLR5_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn3_Pos) /*!< SCT OUTPUTCLR5: CLRn3 Mask */
+#define SCT_OUTPUTCLR5_CLRn4_Pos 4 /*!< SCT OUTPUTCLR5: CLRn4 Position */
+#define SCT_OUTPUTCLR5_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn4_Pos) /*!< SCT OUTPUTCLR5: CLRn4 Mask */
+#define SCT_OUTPUTCLR5_CLRn5_Pos 5 /*!< SCT OUTPUTCLR5: CLRn5 Position */
+#define SCT_OUTPUTCLR5_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn5_Pos) /*!< SCT OUTPUTCLR5: CLRn5 Mask */
+#define SCT_OUTPUTCLR5_CLRn6_Pos 6 /*!< SCT OUTPUTCLR5: CLRn6 Position */
+#define SCT_OUTPUTCLR5_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn6_Pos) /*!< SCT OUTPUTCLR5: CLRn6 Mask */
+#define SCT_OUTPUTCLR5_CLRn7_Pos 7 /*!< SCT OUTPUTCLR5: CLRn7 Position */
+#define SCT_OUTPUTCLR5_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn7_Pos) /*!< SCT OUTPUTCLR5: CLRn7 Mask */
+#define SCT_OUTPUTCLR5_CLRn8_Pos 8 /*!< SCT OUTPUTCLR5: CLRn8 Position */
+#define SCT_OUTPUTCLR5_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn8_Pos) /*!< SCT OUTPUTCLR5: CLRn8 Mask */
+#define SCT_OUTPUTCLR5_CLRn9_Pos 9 /*!< SCT OUTPUTCLR5: CLRn9 Position */
+#define SCT_OUTPUTCLR5_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn9_Pos) /*!< SCT OUTPUTCLR5: CLRn9 Mask */
+#define SCT_OUTPUTCLR5_CLRn10_Pos 10 /*!< SCT OUTPUTCLR5: CLRn10 Position */
+#define SCT_OUTPUTCLR5_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn10_Pos) /*!< SCT OUTPUTCLR5: CLRn10 Mask */
+#define SCT_OUTPUTCLR5_CLRn11_Pos 11 /*!< SCT OUTPUTCLR5: CLRn11 Position */
+#define SCT_OUTPUTCLR5_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn11_Pos) /*!< SCT OUTPUTCLR5: CLRn11 Mask */
+#define SCT_OUTPUTCLR5_CLRn12_Pos 12 /*!< SCT OUTPUTCLR5: CLRn12 Position */
+#define SCT_OUTPUTCLR5_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn12_Pos) /*!< SCT OUTPUTCLR5: CLRn12 Mask */
+#define SCT_OUTPUTCLR5_CLRn13_Pos 13 /*!< SCT OUTPUTCLR5: CLRn13 Position */
+#define SCT_OUTPUTCLR5_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn13_Pos) /*!< SCT OUTPUTCLR5: CLRn13 Mask */
+#define SCT_OUTPUTCLR5_CLRn14_Pos 14 /*!< SCT OUTPUTCLR5: CLRn14 Position */
+#define SCT_OUTPUTCLR5_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn14_Pos) /*!< SCT OUTPUTCLR5: CLRn14 Mask */
+#define SCT_OUTPUTCLR5_CLRn15_Pos 15 /*!< SCT OUTPUTCLR5: CLRn15 Position */
+#define SCT_OUTPUTCLR5_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn15_Pos) /*!< SCT OUTPUTCLR5: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET6 -----------------------------------------
+#define SCT_OUTPUTSET6_SETn0_Pos 0 /*!< SCT OUTPUTSET6: SETn0 Position */
+#define SCT_OUTPUTSET6_SETn0_Msk (0x01UL << SCT_OUTPUTSET6_SETn0_Pos) /*!< SCT OUTPUTSET6: SETn0 Mask */
+#define SCT_OUTPUTSET6_SETn1_Pos 1 /*!< SCT OUTPUTSET6: SETn1 Position */
+#define SCT_OUTPUTSET6_SETn1_Msk (0x01UL << SCT_OUTPUTSET6_SETn1_Pos) /*!< SCT OUTPUTSET6: SETn1 Mask */
+#define SCT_OUTPUTSET6_SETn2_Pos 2 /*!< SCT OUTPUTSET6: SETn2 Position */
+#define SCT_OUTPUTSET6_SETn2_Msk (0x01UL << SCT_OUTPUTSET6_SETn2_Pos) /*!< SCT OUTPUTSET6: SETn2 Mask */
+#define SCT_OUTPUTSET6_SETn3_Pos 3 /*!< SCT OUTPUTSET6: SETn3 Position */
+#define SCT_OUTPUTSET6_SETn3_Msk (0x01UL << SCT_OUTPUTSET6_SETn3_Pos) /*!< SCT OUTPUTSET6: SETn3 Mask */
+#define SCT_OUTPUTSET6_SETn4_Pos 4 /*!< SCT OUTPUTSET6: SETn4 Position */
+#define SCT_OUTPUTSET6_SETn4_Msk (0x01UL << SCT_OUTPUTSET6_SETn4_Pos) /*!< SCT OUTPUTSET6: SETn4 Mask */
+#define SCT_OUTPUTSET6_SETn5_Pos 5 /*!< SCT OUTPUTSET6: SETn5 Position */
+#define SCT_OUTPUTSET6_SETn5_Msk (0x01UL << SCT_OUTPUTSET6_SETn5_Pos) /*!< SCT OUTPUTSET6: SETn5 Mask */
+#define SCT_OUTPUTSET6_SETn6_Pos 6 /*!< SCT OUTPUTSET6: SETn6 Position */
+#define SCT_OUTPUTSET6_SETn6_Msk (0x01UL << SCT_OUTPUTSET6_SETn6_Pos) /*!< SCT OUTPUTSET6: SETn6 Mask */
+#define SCT_OUTPUTSET6_SETn7_Pos 7 /*!< SCT OUTPUTSET6: SETn7 Position */
+#define SCT_OUTPUTSET6_SETn7_Msk (0x01UL << SCT_OUTPUTSET6_SETn7_Pos) /*!< SCT OUTPUTSET6: SETn7 Mask */
+#define SCT_OUTPUTSET6_SETn8_Pos 8 /*!< SCT OUTPUTSET6: SETn8 Position */
+#define SCT_OUTPUTSET6_SETn8_Msk (0x01UL << SCT_OUTPUTSET6_SETn8_Pos) /*!< SCT OUTPUTSET6: SETn8 Mask */
+#define SCT_OUTPUTSET6_SETn9_Pos 9 /*!< SCT OUTPUTSET6: SETn9 Position */
+#define SCT_OUTPUTSET6_SETn9_Msk (0x01UL << SCT_OUTPUTSET6_SETn9_Pos) /*!< SCT OUTPUTSET6: SETn9 Mask */
+#define SCT_OUTPUTSET6_SETn10_Pos 10 /*!< SCT OUTPUTSET6: SETn10 Position */
+#define SCT_OUTPUTSET6_SETn10_Msk (0x01UL << SCT_OUTPUTSET6_SETn10_Pos) /*!< SCT OUTPUTSET6: SETn10 Mask */
+#define SCT_OUTPUTSET6_SETn11_Pos 11 /*!< SCT OUTPUTSET6: SETn11 Position */
+#define SCT_OUTPUTSET6_SETn11_Msk (0x01UL << SCT_OUTPUTSET6_SETn11_Pos) /*!< SCT OUTPUTSET6: SETn11 Mask */
+#define SCT_OUTPUTSET6_SETn12_Pos 12 /*!< SCT OUTPUTSET6: SETn12 Position */
+#define SCT_OUTPUTSET6_SETn12_Msk (0x01UL << SCT_OUTPUTSET6_SETn12_Pos) /*!< SCT OUTPUTSET6: SETn12 Mask */
+#define SCT_OUTPUTSET6_SETn13_Pos 13 /*!< SCT OUTPUTSET6: SETn13 Position */
+#define SCT_OUTPUTSET6_SETn13_Msk (0x01UL << SCT_OUTPUTSET6_SETn13_Pos) /*!< SCT OUTPUTSET6: SETn13 Mask */
+#define SCT_OUTPUTSET6_SETn14_Pos 14 /*!< SCT OUTPUTSET6: SETn14 Position */
+#define SCT_OUTPUTSET6_SETn14_Msk (0x01UL << SCT_OUTPUTSET6_SETn14_Pos) /*!< SCT OUTPUTSET6: SETn14 Mask */
+#define SCT_OUTPUTSET6_SETn15_Pos 15 /*!< SCT OUTPUTSET6: SETn15 Position */
+#define SCT_OUTPUTSET6_SETn15_Msk (0x01UL << SCT_OUTPUTSET6_SETn15_Pos) /*!< SCT OUTPUTSET6: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR6 -----------------------------------------
+#define SCT_OUTPUTCLR6_CLRn0_Pos 0 /*!< SCT OUTPUTCLR6: CLRn0 Position */
+#define SCT_OUTPUTCLR6_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn0_Pos) /*!< SCT OUTPUTCLR6: CLRn0 Mask */
+#define SCT_OUTPUTCLR6_CLRn1_Pos 1 /*!< SCT OUTPUTCLR6: CLRn1 Position */
+#define SCT_OUTPUTCLR6_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn1_Pos) /*!< SCT OUTPUTCLR6: CLRn1 Mask */
+#define SCT_OUTPUTCLR6_CLRn2_Pos 2 /*!< SCT OUTPUTCLR6: CLRn2 Position */
+#define SCT_OUTPUTCLR6_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn2_Pos) /*!< SCT OUTPUTCLR6: CLRn2 Mask */
+#define SCT_OUTPUTCLR6_CLRn3_Pos 3 /*!< SCT OUTPUTCLR6: CLRn3 Position */
+#define SCT_OUTPUTCLR6_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn3_Pos) /*!< SCT OUTPUTCLR6: CLRn3 Mask */
+#define SCT_OUTPUTCLR6_CLRn4_Pos 4 /*!< SCT OUTPUTCLR6: CLRn4 Position */
+#define SCT_OUTPUTCLR6_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn4_Pos) /*!< SCT OUTPUTCLR6: CLRn4 Mask */
+#define SCT_OUTPUTCLR6_CLRn5_Pos 5 /*!< SCT OUTPUTCLR6: CLRn5 Position */
+#define SCT_OUTPUTCLR6_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn5_Pos) /*!< SCT OUTPUTCLR6: CLRn5 Mask */
+#define SCT_OUTPUTCLR6_CLRn6_Pos 6 /*!< SCT OUTPUTCLR6: CLRn6 Position */
+#define SCT_OUTPUTCLR6_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn6_Pos) /*!< SCT OUTPUTCLR6: CLRn6 Mask */
+#define SCT_OUTPUTCLR6_CLRn7_Pos 7 /*!< SCT OUTPUTCLR6: CLRn7 Position */
+#define SCT_OUTPUTCLR6_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn7_Pos) /*!< SCT OUTPUTCLR6: CLRn7 Mask */
+#define SCT_OUTPUTCLR6_CLRn8_Pos 8 /*!< SCT OUTPUTCLR6: CLRn8 Position */
+#define SCT_OUTPUTCLR6_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn8_Pos) /*!< SCT OUTPUTCLR6: CLRn8 Mask */
+#define SCT_OUTPUTCLR6_CLRn9_Pos 9 /*!< SCT OUTPUTCLR6: CLRn9 Position */
+#define SCT_OUTPUTCLR6_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn9_Pos) /*!< SCT OUTPUTCLR6: CLRn9 Mask */
+#define SCT_OUTPUTCLR6_CLRn10_Pos 10 /*!< SCT OUTPUTCLR6: CLRn10 Position */
+#define SCT_OUTPUTCLR6_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn10_Pos) /*!< SCT OUTPUTCLR6: CLRn10 Mask */
+#define SCT_OUTPUTCLR6_CLRn11_Pos 11 /*!< SCT OUTPUTCLR6: CLRn11 Position */
+#define SCT_OUTPUTCLR6_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn11_Pos) /*!< SCT OUTPUTCLR6: CLRn11 Mask */
+#define SCT_OUTPUTCLR6_CLRn12_Pos 12 /*!< SCT OUTPUTCLR6: CLRn12 Position */
+#define SCT_OUTPUTCLR6_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn12_Pos) /*!< SCT OUTPUTCLR6: CLRn12 Mask */
+#define SCT_OUTPUTCLR6_CLRn13_Pos 13 /*!< SCT OUTPUTCLR6: CLRn13 Position */
+#define SCT_OUTPUTCLR6_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn13_Pos) /*!< SCT OUTPUTCLR6: CLRn13 Mask */
+#define SCT_OUTPUTCLR6_CLRn14_Pos 14 /*!< SCT OUTPUTCLR6: CLRn14 Position */
+#define SCT_OUTPUTCLR6_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn14_Pos) /*!< SCT OUTPUTCLR6: CLRn14 Mask */
+#define SCT_OUTPUTCLR6_CLRn15_Pos 15 /*!< SCT OUTPUTCLR6: CLRn15 Position */
+#define SCT_OUTPUTCLR6_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn15_Pos) /*!< SCT OUTPUTCLR6: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET7 -----------------------------------------
+#define SCT_OUTPUTSET7_SETn0_Pos 0 /*!< SCT OUTPUTSET7: SETn0 Position */
+#define SCT_OUTPUTSET7_SETn0_Msk (0x01UL << SCT_OUTPUTSET7_SETn0_Pos) /*!< SCT OUTPUTSET7: SETn0 Mask */
+#define SCT_OUTPUTSET7_SETn1_Pos 1 /*!< SCT OUTPUTSET7: SETn1 Position */
+#define SCT_OUTPUTSET7_SETn1_Msk (0x01UL << SCT_OUTPUTSET7_SETn1_Pos) /*!< SCT OUTPUTSET7: SETn1 Mask */
+#define SCT_OUTPUTSET7_SETn2_Pos 2 /*!< SCT OUTPUTSET7: SETn2 Position */
+#define SCT_OUTPUTSET7_SETn2_Msk (0x01UL << SCT_OUTPUTSET7_SETn2_Pos) /*!< SCT OUTPUTSET7: SETn2 Mask */
+#define SCT_OUTPUTSET7_SETn3_Pos 3 /*!< SCT OUTPUTSET7: SETn3 Position */
+#define SCT_OUTPUTSET7_SETn3_Msk (0x01UL << SCT_OUTPUTSET7_SETn3_Pos) /*!< SCT OUTPUTSET7: SETn3 Mask */
+#define SCT_OUTPUTSET7_SETn4_Pos 4 /*!< SCT OUTPUTSET7: SETn4 Position */
+#define SCT_OUTPUTSET7_SETn4_Msk (0x01UL << SCT_OUTPUTSET7_SETn4_Pos) /*!< SCT OUTPUTSET7: SETn4 Mask */
+#define SCT_OUTPUTSET7_SETn5_Pos 5 /*!< SCT OUTPUTSET7: SETn5 Position */
+#define SCT_OUTPUTSET7_SETn5_Msk (0x01UL << SCT_OUTPUTSET7_SETn5_Pos) /*!< SCT OUTPUTSET7: SETn5 Mask */
+#define SCT_OUTPUTSET7_SETn6_Pos 6 /*!< SCT OUTPUTSET7: SETn6 Position */
+#define SCT_OUTPUTSET7_SETn6_Msk (0x01UL << SCT_OUTPUTSET7_SETn6_Pos) /*!< SCT OUTPUTSET7: SETn6 Mask */
+#define SCT_OUTPUTSET7_SETn7_Pos 7 /*!< SCT OUTPUTSET7: SETn7 Position */
+#define SCT_OUTPUTSET7_SETn7_Msk (0x01UL << SCT_OUTPUTSET7_SETn7_Pos) /*!< SCT OUTPUTSET7: SETn7 Mask */
+#define SCT_OUTPUTSET7_SETn8_Pos 8 /*!< SCT OUTPUTSET7: SETn8 Position */
+#define SCT_OUTPUTSET7_SETn8_Msk (0x01UL << SCT_OUTPUTSET7_SETn8_Pos) /*!< SCT OUTPUTSET7: SETn8 Mask */
+#define SCT_OUTPUTSET7_SETn9_Pos 9 /*!< SCT OUTPUTSET7: SETn9 Position */
+#define SCT_OUTPUTSET7_SETn9_Msk (0x01UL << SCT_OUTPUTSET7_SETn9_Pos) /*!< SCT OUTPUTSET7: SETn9 Mask */
+#define SCT_OUTPUTSET7_SETn10_Pos 10 /*!< SCT OUTPUTSET7: SETn10 Position */
+#define SCT_OUTPUTSET7_SETn10_Msk (0x01UL << SCT_OUTPUTSET7_SETn10_Pos) /*!< SCT OUTPUTSET7: SETn10 Mask */
+#define SCT_OUTPUTSET7_SETn11_Pos 11 /*!< SCT OUTPUTSET7: SETn11 Position */
+#define SCT_OUTPUTSET7_SETn11_Msk (0x01UL << SCT_OUTPUTSET7_SETn11_Pos) /*!< SCT OUTPUTSET7: SETn11 Mask */
+#define SCT_OUTPUTSET7_SETn12_Pos 12 /*!< SCT OUTPUTSET7: SETn12 Position */
+#define SCT_OUTPUTSET7_SETn12_Msk (0x01UL << SCT_OUTPUTSET7_SETn12_Pos) /*!< SCT OUTPUTSET7: SETn12 Mask */
+#define SCT_OUTPUTSET7_SETn13_Pos 13 /*!< SCT OUTPUTSET7: SETn13 Position */
+#define SCT_OUTPUTSET7_SETn13_Msk (0x01UL << SCT_OUTPUTSET7_SETn13_Pos) /*!< SCT OUTPUTSET7: SETn13 Mask */
+#define SCT_OUTPUTSET7_SETn14_Pos 14 /*!< SCT OUTPUTSET7: SETn14 Position */
+#define SCT_OUTPUTSET7_SETn14_Msk (0x01UL << SCT_OUTPUTSET7_SETn14_Pos) /*!< SCT OUTPUTSET7: SETn14 Mask */
+#define SCT_OUTPUTSET7_SETn15_Pos 15 /*!< SCT OUTPUTSET7: SETn15 Position */
+#define SCT_OUTPUTSET7_SETn15_Msk (0x01UL << SCT_OUTPUTSET7_SETn15_Pos) /*!< SCT OUTPUTSET7: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR7 -----------------------------------------
+#define SCT_OUTPUTCLR7_CLRn0_Pos 0 /*!< SCT OUTPUTCLR7: CLRn0 Position */
+#define SCT_OUTPUTCLR7_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn0_Pos) /*!< SCT OUTPUTCLR7: CLRn0 Mask */
+#define SCT_OUTPUTCLR7_CLRn1_Pos 1 /*!< SCT OUTPUTCLR7: CLRn1 Position */
+#define SCT_OUTPUTCLR7_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn1_Pos) /*!< SCT OUTPUTCLR7: CLRn1 Mask */
+#define SCT_OUTPUTCLR7_CLRn2_Pos 2 /*!< SCT OUTPUTCLR7: CLRn2 Position */
+#define SCT_OUTPUTCLR7_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn2_Pos) /*!< SCT OUTPUTCLR7: CLRn2 Mask */
+#define SCT_OUTPUTCLR7_CLRn3_Pos 3 /*!< SCT OUTPUTCLR7: CLRn3 Position */
+#define SCT_OUTPUTCLR7_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn3_Pos) /*!< SCT OUTPUTCLR7: CLRn3 Mask */
+#define SCT_OUTPUTCLR7_CLRn4_Pos 4 /*!< SCT OUTPUTCLR7: CLRn4 Position */
+#define SCT_OUTPUTCLR7_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn4_Pos) /*!< SCT OUTPUTCLR7: CLRn4 Mask */
+#define SCT_OUTPUTCLR7_CLRn5_Pos 5 /*!< SCT OUTPUTCLR7: CLRn5 Position */
+#define SCT_OUTPUTCLR7_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn5_Pos) /*!< SCT OUTPUTCLR7: CLRn5 Mask */
+#define SCT_OUTPUTCLR7_CLRn6_Pos 6 /*!< SCT OUTPUTCLR7: CLRn6 Position */
+#define SCT_OUTPUTCLR7_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn6_Pos) /*!< SCT OUTPUTCLR7: CLRn6 Mask */
+#define SCT_OUTPUTCLR7_CLRn7_Pos 7 /*!< SCT OUTPUTCLR7: CLRn7 Position */
+#define SCT_OUTPUTCLR7_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn7_Pos) /*!< SCT OUTPUTCLR7: CLRn7 Mask */
+#define SCT_OUTPUTCLR7_CLRn8_Pos 8 /*!< SCT OUTPUTCLR7: CLRn8 Position */
+#define SCT_OUTPUTCLR7_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn8_Pos) /*!< SCT OUTPUTCLR7: CLRn8 Mask */
+#define SCT_OUTPUTCLR7_CLRn9_Pos 9 /*!< SCT OUTPUTCLR7: CLRn9 Position */
+#define SCT_OUTPUTCLR7_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn9_Pos) /*!< SCT OUTPUTCLR7: CLRn9 Mask */
+#define SCT_OUTPUTCLR7_CLRn10_Pos 10 /*!< SCT OUTPUTCLR7: CLRn10 Position */
+#define SCT_OUTPUTCLR7_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn10_Pos) /*!< SCT OUTPUTCLR7: CLRn10 Mask */
+#define SCT_OUTPUTCLR7_CLRn11_Pos 11 /*!< SCT OUTPUTCLR7: CLRn11 Position */
+#define SCT_OUTPUTCLR7_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn11_Pos) /*!< SCT OUTPUTCLR7: CLRn11 Mask */
+#define SCT_OUTPUTCLR7_CLRn12_Pos 12 /*!< SCT OUTPUTCLR7: CLRn12 Position */
+#define SCT_OUTPUTCLR7_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn12_Pos) /*!< SCT OUTPUTCLR7: CLRn12 Mask */
+#define SCT_OUTPUTCLR7_CLRn13_Pos 13 /*!< SCT OUTPUTCLR7: CLRn13 Position */
+#define SCT_OUTPUTCLR7_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn13_Pos) /*!< SCT OUTPUTCLR7: CLRn13 Mask */
+#define SCT_OUTPUTCLR7_CLRn14_Pos 14 /*!< SCT OUTPUTCLR7: CLRn14 Position */
+#define SCT_OUTPUTCLR7_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn14_Pos) /*!< SCT OUTPUTCLR7: CLRn14 Mask */
+#define SCT_OUTPUTCLR7_CLRn15_Pos 15 /*!< SCT OUTPUTCLR7: CLRn15 Position */
+#define SCT_OUTPUTCLR7_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn15_Pos) /*!< SCT OUTPUTCLR7: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET8 -----------------------------------------
+#define SCT_OUTPUTSET8_SETn0_Pos 0 /*!< SCT OUTPUTSET8: SETn0 Position */
+#define SCT_OUTPUTSET8_SETn0_Msk (0x01UL << SCT_OUTPUTSET8_SETn0_Pos) /*!< SCT OUTPUTSET8: SETn0 Mask */
+#define SCT_OUTPUTSET8_SETn1_Pos 1 /*!< SCT OUTPUTSET8: SETn1 Position */
+#define SCT_OUTPUTSET8_SETn1_Msk (0x01UL << SCT_OUTPUTSET8_SETn1_Pos) /*!< SCT OUTPUTSET8: SETn1 Mask */
+#define SCT_OUTPUTSET8_SETn2_Pos 2 /*!< SCT OUTPUTSET8: SETn2 Position */
+#define SCT_OUTPUTSET8_SETn2_Msk (0x01UL << SCT_OUTPUTSET8_SETn2_Pos) /*!< SCT OUTPUTSET8: SETn2 Mask */
+#define SCT_OUTPUTSET8_SETn3_Pos 3 /*!< SCT OUTPUTSET8: SETn3 Position */
+#define SCT_OUTPUTSET8_SETn3_Msk (0x01UL << SCT_OUTPUTSET8_SETn3_Pos) /*!< SCT OUTPUTSET8: SETn3 Mask */
+#define SCT_OUTPUTSET8_SETn4_Pos 4 /*!< SCT OUTPUTSET8: SETn4 Position */
+#define SCT_OUTPUTSET8_SETn4_Msk (0x01UL << SCT_OUTPUTSET8_SETn4_Pos) /*!< SCT OUTPUTSET8: SETn4 Mask */
+#define SCT_OUTPUTSET8_SETn5_Pos 5 /*!< SCT OUTPUTSET8: SETn5 Position */
+#define SCT_OUTPUTSET8_SETn5_Msk (0x01UL << SCT_OUTPUTSET8_SETn5_Pos) /*!< SCT OUTPUTSET8: SETn5 Mask */
+#define SCT_OUTPUTSET8_SETn6_Pos 6 /*!< SCT OUTPUTSET8: SETn6 Position */
+#define SCT_OUTPUTSET8_SETn6_Msk (0x01UL << SCT_OUTPUTSET8_SETn6_Pos) /*!< SCT OUTPUTSET8: SETn6 Mask */
+#define SCT_OUTPUTSET8_SETn7_Pos 7 /*!< SCT OUTPUTSET8: SETn7 Position */
+#define SCT_OUTPUTSET8_SETn7_Msk (0x01UL << SCT_OUTPUTSET8_SETn7_Pos) /*!< SCT OUTPUTSET8: SETn7 Mask */
+#define SCT_OUTPUTSET8_SETn8_Pos 8 /*!< SCT OUTPUTSET8: SETn8 Position */
+#define SCT_OUTPUTSET8_SETn8_Msk (0x01UL << SCT_OUTPUTSET8_SETn8_Pos) /*!< SCT OUTPUTSET8: SETn8 Mask */
+#define SCT_OUTPUTSET8_SETn9_Pos 9 /*!< SCT OUTPUTSET8: SETn9 Position */
+#define SCT_OUTPUTSET8_SETn9_Msk (0x01UL << SCT_OUTPUTSET8_SETn9_Pos) /*!< SCT OUTPUTSET8: SETn9 Mask */
+#define SCT_OUTPUTSET8_SETn10_Pos 10 /*!< SCT OUTPUTSET8: SETn10 Position */
+#define SCT_OUTPUTSET8_SETn10_Msk (0x01UL << SCT_OUTPUTSET8_SETn10_Pos) /*!< SCT OUTPUTSET8: SETn10 Mask */
+#define SCT_OUTPUTSET8_SETn11_Pos 11 /*!< SCT OUTPUTSET8: SETn11 Position */
+#define SCT_OUTPUTSET8_SETn11_Msk (0x01UL << SCT_OUTPUTSET8_SETn11_Pos) /*!< SCT OUTPUTSET8: SETn11 Mask */
+#define SCT_OUTPUTSET8_SETn12_Pos 12 /*!< SCT OUTPUTSET8: SETn12 Position */
+#define SCT_OUTPUTSET8_SETn12_Msk (0x01UL << SCT_OUTPUTSET8_SETn12_Pos) /*!< SCT OUTPUTSET8: SETn12 Mask */
+#define SCT_OUTPUTSET8_SETn13_Pos 13 /*!< SCT OUTPUTSET8: SETn13 Position */
+#define SCT_OUTPUTSET8_SETn13_Msk (0x01UL << SCT_OUTPUTSET8_SETn13_Pos) /*!< SCT OUTPUTSET8: SETn13 Mask */
+#define SCT_OUTPUTSET8_SETn14_Pos 14 /*!< SCT OUTPUTSET8: SETn14 Position */
+#define SCT_OUTPUTSET8_SETn14_Msk (0x01UL << SCT_OUTPUTSET8_SETn14_Pos) /*!< SCT OUTPUTSET8: SETn14 Mask */
+#define SCT_OUTPUTSET8_SETn15_Pos 15 /*!< SCT OUTPUTSET8: SETn15 Position */
+#define SCT_OUTPUTSET8_SETn15_Msk (0x01UL << SCT_OUTPUTSET8_SETn15_Pos) /*!< SCT OUTPUTSET8: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR8 -----------------------------------------
+#define SCT_OUTPUTCLR8_CLRn0_Pos 0 /*!< SCT OUTPUTCLR8: CLRn0 Position */
+#define SCT_OUTPUTCLR8_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn0_Pos) /*!< SCT OUTPUTCLR8: CLRn0 Mask */
+#define SCT_OUTPUTCLR8_CLRn1_Pos 1 /*!< SCT OUTPUTCLR8: CLRn1 Position */
+#define SCT_OUTPUTCLR8_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn1_Pos) /*!< SCT OUTPUTCLR8: CLRn1 Mask */
+#define SCT_OUTPUTCLR8_CLRn2_Pos 2 /*!< SCT OUTPUTCLR8: CLRn2 Position */
+#define SCT_OUTPUTCLR8_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn2_Pos) /*!< SCT OUTPUTCLR8: CLRn2 Mask */
+#define SCT_OUTPUTCLR8_CLRn3_Pos 3 /*!< SCT OUTPUTCLR8: CLRn3 Position */
+#define SCT_OUTPUTCLR8_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn3_Pos) /*!< SCT OUTPUTCLR8: CLRn3 Mask */
+#define SCT_OUTPUTCLR8_CLRn4_Pos 4 /*!< SCT OUTPUTCLR8: CLRn4 Position */
+#define SCT_OUTPUTCLR8_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn4_Pos) /*!< SCT OUTPUTCLR8: CLRn4 Mask */
+#define SCT_OUTPUTCLR8_CLRn5_Pos 5 /*!< SCT OUTPUTCLR8: CLRn5 Position */
+#define SCT_OUTPUTCLR8_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn5_Pos) /*!< SCT OUTPUTCLR8: CLRn5 Mask */
+#define SCT_OUTPUTCLR8_CLRn6_Pos 6 /*!< SCT OUTPUTCLR8: CLRn6 Position */
+#define SCT_OUTPUTCLR8_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn6_Pos) /*!< SCT OUTPUTCLR8: CLRn6 Mask */
+#define SCT_OUTPUTCLR8_CLRn7_Pos 7 /*!< SCT OUTPUTCLR8: CLRn7 Position */
+#define SCT_OUTPUTCLR8_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn7_Pos) /*!< SCT OUTPUTCLR8: CLRn7 Mask */
+#define SCT_OUTPUTCLR8_CLRn8_Pos 8 /*!< SCT OUTPUTCLR8: CLRn8 Position */
+#define SCT_OUTPUTCLR8_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn8_Pos) /*!< SCT OUTPUTCLR8: CLRn8 Mask */
+#define SCT_OUTPUTCLR8_CLRn9_Pos 9 /*!< SCT OUTPUTCLR8: CLRn9 Position */
+#define SCT_OUTPUTCLR8_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn9_Pos) /*!< SCT OUTPUTCLR8: CLRn9 Mask */
+#define SCT_OUTPUTCLR8_CLRn10_Pos 10 /*!< SCT OUTPUTCLR8: CLRn10 Position */
+#define SCT_OUTPUTCLR8_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn10_Pos) /*!< SCT OUTPUTCLR8: CLRn10 Mask */
+#define SCT_OUTPUTCLR8_CLRn11_Pos 11 /*!< SCT OUTPUTCLR8: CLRn11 Position */
+#define SCT_OUTPUTCLR8_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn11_Pos) /*!< SCT OUTPUTCLR8: CLRn11 Mask */
+#define SCT_OUTPUTCLR8_CLRn12_Pos 12 /*!< SCT OUTPUTCLR8: CLRn12 Position */
+#define SCT_OUTPUTCLR8_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn12_Pos) /*!< SCT OUTPUTCLR8: CLRn12 Mask */
+#define SCT_OUTPUTCLR8_CLRn13_Pos 13 /*!< SCT OUTPUTCLR8: CLRn13 Position */
+#define SCT_OUTPUTCLR8_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn13_Pos) /*!< SCT OUTPUTCLR8: CLRn13 Mask */
+#define SCT_OUTPUTCLR8_CLRn14_Pos 14 /*!< SCT OUTPUTCLR8: CLRn14 Position */
+#define SCT_OUTPUTCLR8_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn14_Pos) /*!< SCT OUTPUTCLR8: CLRn14 Mask */
+#define SCT_OUTPUTCLR8_CLRn15_Pos 15 /*!< SCT OUTPUTCLR8: CLRn15 Position */
+#define SCT_OUTPUTCLR8_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn15_Pos) /*!< SCT OUTPUTCLR8: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET9 -----------------------------------------
+#define SCT_OUTPUTSET9_SETn0_Pos 0 /*!< SCT OUTPUTSET9: SETn0 Position */
+#define SCT_OUTPUTSET9_SETn0_Msk (0x01UL << SCT_OUTPUTSET9_SETn0_Pos) /*!< SCT OUTPUTSET9: SETn0 Mask */
+#define SCT_OUTPUTSET9_SETn1_Pos 1 /*!< SCT OUTPUTSET9: SETn1 Position */
+#define SCT_OUTPUTSET9_SETn1_Msk (0x01UL << SCT_OUTPUTSET9_SETn1_Pos) /*!< SCT OUTPUTSET9: SETn1 Mask */
+#define SCT_OUTPUTSET9_SETn2_Pos 2 /*!< SCT OUTPUTSET9: SETn2 Position */
+#define SCT_OUTPUTSET9_SETn2_Msk (0x01UL << SCT_OUTPUTSET9_SETn2_Pos) /*!< SCT OUTPUTSET9: SETn2 Mask */
+#define SCT_OUTPUTSET9_SETn3_Pos 3 /*!< SCT OUTPUTSET9: SETn3 Position */
+#define SCT_OUTPUTSET9_SETn3_Msk (0x01UL << SCT_OUTPUTSET9_SETn3_Pos) /*!< SCT OUTPUTSET9: SETn3 Mask */
+#define SCT_OUTPUTSET9_SETn4_Pos 4 /*!< SCT OUTPUTSET9: SETn4 Position */
+#define SCT_OUTPUTSET9_SETn4_Msk (0x01UL << SCT_OUTPUTSET9_SETn4_Pos) /*!< SCT OUTPUTSET9: SETn4 Mask */
+#define SCT_OUTPUTSET9_SETn5_Pos 5 /*!< SCT OUTPUTSET9: SETn5 Position */
+#define SCT_OUTPUTSET9_SETn5_Msk (0x01UL << SCT_OUTPUTSET9_SETn5_Pos) /*!< SCT OUTPUTSET9: SETn5 Mask */
+#define SCT_OUTPUTSET9_SETn6_Pos 6 /*!< SCT OUTPUTSET9: SETn6 Position */
+#define SCT_OUTPUTSET9_SETn6_Msk (0x01UL << SCT_OUTPUTSET9_SETn6_Pos) /*!< SCT OUTPUTSET9: SETn6 Mask */
+#define SCT_OUTPUTSET9_SETn7_Pos 7 /*!< SCT OUTPUTSET9: SETn7 Position */
+#define SCT_OUTPUTSET9_SETn7_Msk (0x01UL << SCT_OUTPUTSET9_SETn7_Pos) /*!< SCT OUTPUTSET9: SETn7 Mask */
+#define SCT_OUTPUTSET9_SETn8_Pos 8 /*!< SCT OUTPUTSET9: SETn8 Position */
+#define SCT_OUTPUTSET9_SETn8_Msk (0x01UL << SCT_OUTPUTSET9_SETn8_Pos) /*!< SCT OUTPUTSET9: SETn8 Mask */
+#define SCT_OUTPUTSET9_SETn9_Pos 9 /*!< SCT OUTPUTSET9: SETn9 Position */
+#define SCT_OUTPUTSET9_SETn9_Msk (0x01UL << SCT_OUTPUTSET9_SETn9_Pos) /*!< SCT OUTPUTSET9: SETn9 Mask */
+#define SCT_OUTPUTSET9_SETn10_Pos 10 /*!< SCT OUTPUTSET9: SETn10 Position */
+#define SCT_OUTPUTSET9_SETn10_Msk (0x01UL << SCT_OUTPUTSET9_SETn10_Pos) /*!< SCT OUTPUTSET9: SETn10 Mask */
+#define SCT_OUTPUTSET9_SETn11_Pos 11 /*!< SCT OUTPUTSET9: SETn11 Position */
+#define SCT_OUTPUTSET9_SETn11_Msk (0x01UL << SCT_OUTPUTSET9_SETn11_Pos) /*!< SCT OUTPUTSET9: SETn11 Mask */
+#define SCT_OUTPUTSET9_SETn12_Pos 12 /*!< SCT OUTPUTSET9: SETn12 Position */
+#define SCT_OUTPUTSET9_SETn12_Msk (0x01UL << SCT_OUTPUTSET9_SETn12_Pos) /*!< SCT OUTPUTSET9: SETn12 Mask */
+#define SCT_OUTPUTSET9_SETn13_Pos 13 /*!< SCT OUTPUTSET9: SETn13 Position */
+#define SCT_OUTPUTSET9_SETn13_Msk (0x01UL << SCT_OUTPUTSET9_SETn13_Pos) /*!< SCT OUTPUTSET9: SETn13 Mask */
+#define SCT_OUTPUTSET9_SETn14_Pos 14 /*!< SCT OUTPUTSET9: SETn14 Position */
+#define SCT_OUTPUTSET9_SETn14_Msk (0x01UL << SCT_OUTPUTSET9_SETn14_Pos) /*!< SCT OUTPUTSET9: SETn14 Mask */
+#define SCT_OUTPUTSET9_SETn15_Pos 15 /*!< SCT OUTPUTSET9: SETn15 Position */
+#define SCT_OUTPUTSET9_SETn15_Msk (0x01UL << SCT_OUTPUTSET9_SETn15_Pos) /*!< SCT OUTPUTSET9: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR9 -----------------------------------------
+#define SCT_OUTPUTCLR9_CLRn0_Pos 0 /*!< SCT OUTPUTCLR9: CLRn0 Position */
+#define SCT_OUTPUTCLR9_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn0_Pos) /*!< SCT OUTPUTCLR9: CLRn0 Mask */
+#define SCT_OUTPUTCLR9_CLRn1_Pos 1 /*!< SCT OUTPUTCLR9: CLRn1 Position */
+#define SCT_OUTPUTCLR9_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn1_Pos) /*!< SCT OUTPUTCLR9: CLRn1 Mask */
+#define SCT_OUTPUTCLR9_CLRn2_Pos 2 /*!< SCT OUTPUTCLR9: CLRn2 Position */
+#define SCT_OUTPUTCLR9_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn2_Pos) /*!< SCT OUTPUTCLR9: CLRn2 Mask */
+#define SCT_OUTPUTCLR9_CLRn3_Pos 3 /*!< SCT OUTPUTCLR9: CLRn3 Position */
+#define SCT_OUTPUTCLR9_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn3_Pos) /*!< SCT OUTPUTCLR9: CLRn3 Mask */
+#define SCT_OUTPUTCLR9_CLRn4_Pos 4 /*!< SCT OUTPUTCLR9: CLRn4 Position */
+#define SCT_OUTPUTCLR9_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn4_Pos) /*!< SCT OUTPUTCLR9: CLRn4 Mask */
+#define SCT_OUTPUTCLR9_CLRn5_Pos 5 /*!< SCT OUTPUTCLR9: CLRn5 Position */
+#define SCT_OUTPUTCLR9_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn5_Pos) /*!< SCT OUTPUTCLR9: CLRn5 Mask */
+#define SCT_OUTPUTCLR9_CLRn6_Pos 6 /*!< SCT OUTPUTCLR9: CLRn6 Position */
+#define SCT_OUTPUTCLR9_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn6_Pos) /*!< SCT OUTPUTCLR9: CLRn6 Mask */
+#define SCT_OUTPUTCLR9_CLRn7_Pos 7 /*!< SCT OUTPUTCLR9: CLRn7 Position */
+#define SCT_OUTPUTCLR9_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn7_Pos) /*!< SCT OUTPUTCLR9: CLRn7 Mask */
+#define SCT_OUTPUTCLR9_CLRn8_Pos 8 /*!< SCT OUTPUTCLR9: CLRn8 Position */
+#define SCT_OUTPUTCLR9_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn8_Pos) /*!< SCT OUTPUTCLR9: CLRn8 Mask */
+#define SCT_OUTPUTCLR9_CLRn9_Pos 9 /*!< SCT OUTPUTCLR9: CLRn9 Position */
+#define SCT_OUTPUTCLR9_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn9_Pos) /*!< SCT OUTPUTCLR9: CLRn9 Mask */
+#define SCT_OUTPUTCLR9_CLRn10_Pos 10 /*!< SCT OUTPUTCLR9: CLRn10 Position */
+#define SCT_OUTPUTCLR9_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn10_Pos) /*!< SCT OUTPUTCLR9: CLRn10 Mask */
+#define SCT_OUTPUTCLR9_CLRn11_Pos 11 /*!< SCT OUTPUTCLR9: CLRn11 Position */
+#define SCT_OUTPUTCLR9_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn11_Pos) /*!< SCT OUTPUTCLR9: CLRn11 Mask */
+#define SCT_OUTPUTCLR9_CLRn12_Pos 12 /*!< SCT OUTPUTCLR9: CLRn12 Position */
+#define SCT_OUTPUTCLR9_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn12_Pos) /*!< SCT OUTPUTCLR9: CLRn12 Mask */
+#define SCT_OUTPUTCLR9_CLRn13_Pos 13 /*!< SCT OUTPUTCLR9: CLRn13 Position */
+#define SCT_OUTPUTCLR9_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn13_Pos) /*!< SCT OUTPUTCLR9: CLRn13 Mask */
+#define SCT_OUTPUTCLR9_CLRn14_Pos 14 /*!< SCT OUTPUTCLR9: CLRn14 Position */
+#define SCT_OUTPUTCLR9_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn14_Pos) /*!< SCT OUTPUTCLR9: CLRn14 Mask */
+#define SCT_OUTPUTCLR9_CLRn15_Pos 15 /*!< SCT OUTPUTCLR9: CLRn15 Position */
+#define SCT_OUTPUTCLR9_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn15_Pos) /*!< SCT OUTPUTCLR9: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET10 ----------------------------------------
+#define SCT_OUTPUTSET10_SETn0_Pos 0 /*!< SCT OUTPUTSET10: SETn0 Position */
+#define SCT_OUTPUTSET10_SETn0_Msk (0x01UL << SCT_OUTPUTSET10_SETn0_Pos) /*!< SCT OUTPUTSET10: SETn0 Mask */
+#define SCT_OUTPUTSET10_SETn1_Pos 1 /*!< SCT OUTPUTSET10: SETn1 Position */
+#define SCT_OUTPUTSET10_SETn1_Msk (0x01UL << SCT_OUTPUTSET10_SETn1_Pos) /*!< SCT OUTPUTSET10: SETn1 Mask */
+#define SCT_OUTPUTSET10_SETn2_Pos 2 /*!< SCT OUTPUTSET10: SETn2 Position */
+#define SCT_OUTPUTSET10_SETn2_Msk (0x01UL << SCT_OUTPUTSET10_SETn2_Pos) /*!< SCT OUTPUTSET10: SETn2 Mask */
+#define SCT_OUTPUTSET10_SETn3_Pos 3 /*!< SCT OUTPUTSET10: SETn3 Position */
+#define SCT_OUTPUTSET10_SETn3_Msk (0x01UL << SCT_OUTPUTSET10_SETn3_Pos) /*!< SCT OUTPUTSET10: SETn3 Mask */
+#define SCT_OUTPUTSET10_SETn4_Pos 4 /*!< SCT OUTPUTSET10: SETn4 Position */
+#define SCT_OUTPUTSET10_SETn4_Msk (0x01UL << SCT_OUTPUTSET10_SETn4_Pos) /*!< SCT OUTPUTSET10: SETn4 Mask */
+#define SCT_OUTPUTSET10_SETn5_Pos 5 /*!< SCT OUTPUTSET10: SETn5 Position */
+#define SCT_OUTPUTSET10_SETn5_Msk (0x01UL << SCT_OUTPUTSET10_SETn5_Pos) /*!< SCT OUTPUTSET10: SETn5 Mask */
+#define SCT_OUTPUTSET10_SETn6_Pos 6 /*!< SCT OUTPUTSET10: SETn6 Position */
+#define SCT_OUTPUTSET10_SETn6_Msk (0x01UL << SCT_OUTPUTSET10_SETn6_Pos) /*!< SCT OUTPUTSET10: SETn6 Mask */
+#define SCT_OUTPUTSET10_SETn7_Pos 7 /*!< SCT OUTPUTSET10: SETn7 Position */
+#define SCT_OUTPUTSET10_SETn7_Msk (0x01UL << SCT_OUTPUTSET10_SETn7_Pos) /*!< SCT OUTPUTSET10: SETn7 Mask */
+#define SCT_OUTPUTSET10_SETn8_Pos 8 /*!< SCT OUTPUTSET10: SETn8 Position */
+#define SCT_OUTPUTSET10_SETn8_Msk (0x01UL << SCT_OUTPUTSET10_SETn8_Pos) /*!< SCT OUTPUTSET10: SETn8 Mask */
+#define SCT_OUTPUTSET10_SETn9_Pos 9 /*!< SCT OUTPUTSET10: SETn9 Position */
+#define SCT_OUTPUTSET10_SETn9_Msk (0x01UL << SCT_OUTPUTSET10_SETn9_Pos) /*!< SCT OUTPUTSET10: SETn9 Mask */
+#define SCT_OUTPUTSET10_SETn10_Pos 10 /*!< SCT OUTPUTSET10: SETn10 Position */
+#define SCT_OUTPUTSET10_SETn10_Msk (0x01UL << SCT_OUTPUTSET10_SETn10_Pos) /*!< SCT OUTPUTSET10: SETn10 Mask */
+#define SCT_OUTPUTSET10_SETn11_Pos 11 /*!< SCT OUTPUTSET10: SETn11 Position */
+#define SCT_OUTPUTSET10_SETn11_Msk (0x01UL << SCT_OUTPUTSET10_SETn11_Pos) /*!< SCT OUTPUTSET10: SETn11 Mask */
+#define SCT_OUTPUTSET10_SETn12_Pos 12 /*!< SCT OUTPUTSET10: SETn12 Position */
+#define SCT_OUTPUTSET10_SETn12_Msk (0x01UL << SCT_OUTPUTSET10_SETn12_Pos) /*!< SCT OUTPUTSET10: SETn12 Mask */
+#define SCT_OUTPUTSET10_SETn13_Pos 13 /*!< SCT OUTPUTSET10: SETn13 Position */
+#define SCT_OUTPUTSET10_SETn13_Msk (0x01UL << SCT_OUTPUTSET10_SETn13_Pos) /*!< SCT OUTPUTSET10: SETn13 Mask */
+#define SCT_OUTPUTSET10_SETn14_Pos 14 /*!< SCT OUTPUTSET10: SETn14 Position */
+#define SCT_OUTPUTSET10_SETn14_Msk (0x01UL << SCT_OUTPUTSET10_SETn14_Pos) /*!< SCT OUTPUTSET10: SETn14 Mask */
+#define SCT_OUTPUTSET10_SETn15_Pos 15 /*!< SCT OUTPUTSET10: SETn15 Position */
+#define SCT_OUTPUTSET10_SETn15_Msk (0x01UL << SCT_OUTPUTSET10_SETn15_Pos) /*!< SCT OUTPUTSET10: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR10 ----------------------------------------
+#define SCT_OUTPUTCLR10_CLRn0_Pos 0 /*!< SCT OUTPUTCLR10: CLRn0 Position */
+#define SCT_OUTPUTCLR10_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn0_Pos) /*!< SCT OUTPUTCLR10: CLRn0 Mask */
+#define SCT_OUTPUTCLR10_CLRn1_Pos 1 /*!< SCT OUTPUTCLR10: CLRn1 Position */
+#define SCT_OUTPUTCLR10_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn1_Pos) /*!< SCT OUTPUTCLR10: CLRn1 Mask */
+#define SCT_OUTPUTCLR10_CLRn2_Pos 2 /*!< SCT OUTPUTCLR10: CLRn2 Position */
+#define SCT_OUTPUTCLR10_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn2_Pos) /*!< SCT OUTPUTCLR10: CLRn2 Mask */
+#define SCT_OUTPUTCLR10_CLRn3_Pos 3 /*!< SCT OUTPUTCLR10: CLRn3 Position */
+#define SCT_OUTPUTCLR10_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn3_Pos) /*!< SCT OUTPUTCLR10: CLRn3 Mask */
+#define SCT_OUTPUTCLR10_CLRn4_Pos 4 /*!< SCT OUTPUTCLR10: CLRn4 Position */
+#define SCT_OUTPUTCLR10_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn4_Pos) /*!< SCT OUTPUTCLR10: CLRn4 Mask */
+#define SCT_OUTPUTCLR10_CLRn5_Pos 5 /*!< SCT OUTPUTCLR10: CLRn5 Position */
+#define SCT_OUTPUTCLR10_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn5_Pos) /*!< SCT OUTPUTCLR10: CLRn5 Mask */
+#define SCT_OUTPUTCLR10_CLRn6_Pos 6 /*!< SCT OUTPUTCLR10: CLRn6 Position */
+#define SCT_OUTPUTCLR10_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn6_Pos) /*!< SCT OUTPUTCLR10: CLRn6 Mask */
+#define SCT_OUTPUTCLR10_CLRn7_Pos 7 /*!< SCT OUTPUTCLR10: CLRn7 Position */
+#define SCT_OUTPUTCLR10_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn7_Pos) /*!< SCT OUTPUTCLR10: CLRn7 Mask */
+#define SCT_OUTPUTCLR10_CLRn8_Pos 8 /*!< SCT OUTPUTCLR10: CLRn8 Position */
+#define SCT_OUTPUTCLR10_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn8_Pos) /*!< SCT OUTPUTCLR10: CLRn8 Mask */
+#define SCT_OUTPUTCLR10_CLRn9_Pos 9 /*!< SCT OUTPUTCLR10: CLRn9 Position */
+#define SCT_OUTPUTCLR10_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn9_Pos) /*!< SCT OUTPUTCLR10: CLRn9 Mask */
+#define SCT_OUTPUTCLR10_CLRn10_Pos 10 /*!< SCT OUTPUTCLR10: CLRn10 Position */
+#define SCT_OUTPUTCLR10_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn10_Pos) /*!< SCT OUTPUTCLR10: CLRn10 Mask */
+#define SCT_OUTPUTCLR10_CLRn11_Pos 11 /*!< SCT OUTPUTCLR10: CLRn11 Position */
+#define SCT_OUTPUTCLR10_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn11_Pos) /*!< SCT OUTPUTCLR10: CLRn11 Mask */
+#define SCT_OUTPUTCLR10_CLRn12_Pos 12 /*!< SCT OUTPUTCLR10: CLRn12 Position */
+#define SCT_OUTPUTCLR10_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn12_Pos) /*!< SCT OUTPUTCLR10: CLRn12 Mask */
+#define SCT_OUTPUTCLR10_CLRn13_Pos 13 /*!< SCT OUTPUTCLR10: CLRn13 Position */
+#define SCT_OUTPUTCLR10_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn13_Pos) /*!< SCT OUTPUTCLR10: CLRn13 Mask */
+#define SCT_OUTPUTCLR10_CLRn14_Pos 14 /*!< SCT OUTPUTCLR10: CLRn14 Position */
+#define SCT_OUTPUTCLR10_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn14_Pos) /*!< SCT OUTPUTCLR10: CLRn14 Mask */
+#define SCT_OUTPUTCLR10_CLRn15_Pos 15 /*!< SCT OUTPUTCLR10: CLRn15 Position */
+#define SCT_OUTPUTCLR10_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn15_Pos) /*!< SCT OUTPUTCLR10: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET11 ----------------------------------------
+#define SCT_OUTPUTSET11_SETn0_Pos 0 /*!< SCT OUTPUTSET11: SETn0 Position */
+#define SCT_OUTPUTSET11_SETn0_Msk (0x01UL << SCT_OUTPUTSET11_SETn0_Pos) /*!< SCT OUTPUTSET11: SETn0 Mask */
+#define SCT_OUTPUTSET11_SETn1_Pos 1 /*!< SCT OUTPUTSET11: SETn1 Position */
+#define SCT_OUTPUTSET11_SETn1_Msk (0x01UL << SCT_OUTPUTSET11_SETn1_Pos) /*!< SCT OUTPUTSET11: SETn1 Mask */
+#define SCT_OUTPUTSET11_SETn2_Pos 2 /*!< SCT OUTPUTSET11: SETn2 Position */
+#define SCT_OUTPUTSET11_SETn2_Msk (0x01UL << SCT_OUTPUTSET11_SETn2_Pos) /*!< SCT OUTPUTSET11: SETn2 Mask */
+#define SCT_OUTPUTSET11_SETn3_Pos 3 /*!< SCT OUTPUTSET11: SETn3 Position */
+#define SCT_OUTPUTSET11_SETn3_Msk (0x01UL << SCT_OUTPUTSET11_SETn3_Pos) /*!< SCT OUTPUTSET11: SETn3 Mask */
+#define SCT_OUTPUTSET11_SETn4_Pos 4 /*!< SCT OUTPUTSET11: SETn4 Position */
+#define SCT_OUTPUTSET11_SETn4_Msk (0x01UL << SCT_OUTPUTSET11_SETn4_Pos) /*!< SCT OUTPUTSET11: SETn4 Mask */
+#define SCT_OUTPUTSET11_SETn5_Pos 5 /*!< SCT OUTPUTSET11: SETn5 Position */
+#define SCT_OUTPUTSET11_SETn5_Msk (0x01UL << SCT_OUTPUTSET11_SETn5_Pos) /*!< SCT OUTPUTSET11: SETn5 Mask */
+#define SCT_OUTPUTSET11_SETn6_Pos 6 /*!< SCT OUTPUTSET11: SETn6 Position */
+#define SCT_OUTPUTSET11_SETn6_Msk (0x01UL << SCT_OUTPUTSET11_SETn6_Pos) /*!< SCT OUTPUTSET11: SETn6 Mask */
+#define SCT_OUTPUTSET11_SETn7_Pos 7 /*!< SCT OUTPUTSET11: SETn7 Position */
+#define SCT_OUTPUTSET11_SETn7_Msk (0x01UL << SCT_OUTPUTSET11_SETn7_Pos) /*!< SCT OUTPUTSET11: SETn7 Mask */
+#define SCT_OUTPUTSET11_SETn8_Pos 8 /*!< SCT OUTPUTSET11: SETn8 Position */
+#define SCT_OUTPUTSET11_SETn8_Msk (0x01UL << SCT_OUTPUTSET11_SETn8_Pos) /*!< SCT OUTPUTSET11: SETn8 Mask */
+#define SCT_OUTPUTSET11_SETn9_Pos 9 /*!< SCT OUTPUTSET11: SETn9 Position */
+#define SCT_OUTPUTSET11_SETn9_Msk (0x01UL << SCT_OUTPUTSET11_SETn9_Pos) /*!< SCT OUTPUTSET11: SETn9 Mask */
+#define SCT_OUTPUTSET11_SETn10_Pos 10 /*!< SCT OUTPUTSET11: SETn10 Position */
+#define SCT_OUTPUTSET11_SETn10_Msk (0x01UL << SCT_OUTPUTSET11_SETn10_Pos) /*!< SCT OUTPUTSET11: SETn10 Mask */
+#define SCT_OUTPUTSET11_SETn11_Pos 11 /*!< SCT OUTPUTSET11: SETn11 Position */
+#define SCT_OUTPUTSET11_SETn11_Msk (0x01UL << SCT_OUTPUTSET11_SETn11_Pos) /*!< SCT OUTPUTSET11: SETn11 Mask */
+#define SCT_OUTPUTSET11_SETn12_Pos 12 /*!< SCT OUTPUTSET11: SETn12 Position */
+#define SCT_OUTPUTSET11_SETn12_Msk (0x01UL << SCT_OUTPUTSET11_SETn12_Pos) /*!< SCT OUTPUTSET11: SETn12 Mask */
+#define SCT_OUTPUTSET11_SETn13_Pos 13 /*!< SCT OUTPUTSET11: SETn13 Position */
+#define SCT_OUTPUTSET11_SETn13_Msk (0x01UL << SCT_OUTPUTSET11_SETn13_Pos) /*!< SCT OUTPUTSET11: SETn13 Mask */
+#define SCT_OUTPUTSET11_SETn14_Pos 14 /*!< SCT OUTPUTSET11: SETn14 Position */
+#define SCT_OUTPUTSET11_SETn14_Msk (0x01UL << SCT_OUTPUTSET11_SETn14_Pos) /*!< SCT OUTPUTSET11: SETn14 Mask */
+#define SCT_OUTPUTSET11_SETn15_Pos 15 /*!< SCT OUTPUTSET11: SETn15 Position */
+#define SCT_OUTPUTSET11_SETn15_Msk (0x01UL << SCT_OUTPUTSET11_SETn15_Pos) /*!< SCT OUTPUTSET11: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR11 ----------------------------------------
+#define SCT_OUTPUTCLR11_CLRn0_Pos 0 /*!< SCT OUTPUTCLR11: CLRn0 Position */
+#define SCT_OUTPUTCLR11_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn0_Pos) /*!< SCT OUTPUTCLR11: CLRn0 Mask */
+#define SCT_OUTPUTCLR11_CLRn1_Pos 1 /*!< SCT OUTPUTCLR11: CLRn1 Position */
+#define SCT_OUTPUTCLR11_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn1_Pos) /*!< SCT OUTPUTCLR11: CLRn1 Mask */
+#define SCT_OUTPUTCLR11_CLRn2_Pos 2 /*!< SCT OUTPUTCLR11: CLRn2 Position */
+#define SCT_OUTPUTCLR11_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn2_Pos) /*!< SCT OUTPUTCLR11: CLRn2 Mask */
+#define SCT_OUTPUTCLR11_CLRn3_Pos 3 /*!< SCT OUTPUTCLR11: CLRn3 Position */
+#define SCT_OUTPUTCLR11_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn3_Pos) /*!< SCT OUTPUTCLR11: CLRn3 Mask */
+#define SCT_OUTPUTCLR11_CLRn4_Pos 4 /*!< SCT OUTPUTCLR11: CLRn4 Position */
+#define SCT_OUTPUTCLR11_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn4_Pos) /*!< SCT OUTPUTCLR11: CLRn4 Mask */
+#define SCT_OUTPUTCLR11_CLRn5_Pos 5 /*!< SCT OUTPUTCLR11: CLRn5 Position */
+#define SCT_OUTPUTCLR11_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn5_Pos) /*!< SCT OUTPUTCLR11: CLRn5 Mask */
+#define SCT_OUTPUTCLR11_CLRn6_Pos 6 /*!< SCT OUTPUTCLR11: CLRn6 Position */
+#define SCT_OUTPUTCLR11_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn6_Pos) /*!< SCT OUTPUTCLR11: CLRn6 Mask */
+#define SCT_OUTPUTCLR11_CLRn7_Pos 7 /*!< SCT OUTPUTCLR11: CLRn7 Position */
+#define SCT_OUTPUTCLR11_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn7_Pos) /*!< SCT OUTPUTCLR11: CLRn7 Mask */
+#define SCT_OUTPUTCLR11_CLRn8_Pos 8 /*!< SCT OUTPUTCLR11: CLRn8 Position */
+#define SCT_OUTPUTCLR11_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn8_Pos) /*!< SCT OUTPUTCLR11: CLRn8 Mask */
+#define SCT_OUTPUTCLR11_CLRn9_Pos 9 /*!< SCT OUTPUTCLR11: CLRn9 Position */
+#define SCT_OUTPUTCLR11_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn9_Pos) /*!< SCT OUTPUTCLR11: CLRn9 Mask */
+#define SCT_OUTPUTCLR11_CLRn10_Pos 10 /*!< SCT OUTPUTCLR11: CLRn10 Position */
+#define SCT_OUTPUTCLR11_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn10_Pos) /*!< SCT OUTPUTCLR11: CLRn10 Mask */
+#define SCT_OUTPUTCLR11_CLRn11_Pos 11 /*!< SCT OUTPUTCLR11: CLRn11 Position */
+#define SCT_OUTPUTCLR11_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn11_Pos) /*!< SCT OUTPUTCLR11: CLRn11 Mask */
+#define SCT_OUTPUTCLR11_CLRn12_Pos 12 /*!< SCT OUTPUTCLR11: CLRn12 Position */
+#define SCT_OUTPUTCLR11_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn12_Pos) /*!< SCT OUTPUTCLR11: CLRn12 Mask */
+#define SCT_OUTPUTCLR11_CLRn13_Pos 13 /*!< SCT OUTPUTCLR11: CLRn13 Position */
+#define SCT_OUTPUTCLR11_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn13_Pos) /*!< SCT OUTPUTCLR11: CLRn13 Mask */
+#define SCT_OUTPUTCLR11_CLRn14_Pos 14 /*!< SCT OUTPUTCLR11: CLRn14 Position */
+#define SCT_OUTPUTCLR11_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn14_Pos) /*!< SCT OUTPUTCLR11: CLRn14 Mask */
+#define SCT_OUTPUTCLR11_CLRn15_Pos 15 /*!< SCT OUTPUTCLR11: CLRn15 Position */
+#define SCT_OUTPUTCLR11_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn15_Pos) /*!< SCT OUTPUTCLR11: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET12 ----------------------------------------
+#define SCT_OUTPUTSET12_SETn0_Pos 0 /*!< SCT OUTPUTSET12: SETn0 Position */
+#define SCT_OUTPUTSET12_SETn0_Msk (0x01UL << SCT_OUTPUTSET12_SETn0_Pos) /*!< SCT OUTPUTSET12: SETn0 Mask */
+#define SCT_OUTPUTSET12_SETn1_Pos 1 /*!< SCT OUTPUTSET12: SETn1 Position */
+#define SCT_OUTPUTSET12_SETn1_Msk (0x01UL << SCT_OUTPUTSET12_SETn1_Pos) /*!< SCT OUTPUTSET12: SETn1 Mask */
+#define SCT_OUTPUTSET12_SETn2_Pos 2 /*!< SCT OUTPUTSET12: SETn2 Position */
+#define SCT_OUTPUTSET12_SETn2_Msk (0x01UL << SCT_OUTPUTSET12_SETn2_Pos) /*!< SCT OUTPUTSET12: SETn2 Mask */
+#define SCT_OUTPUTSET12_SETn3_Pos 3 /*!< SCT OUTPUTSET12: SETn3 Position */
+#define SCT_OUTPUTSET12_SETn3_Msk (0x01UL << SCT_OUTPUTSET12_SETn3_Pos) /*!< SCT OUTPUTSET12: SETn3 Mask */
+#define SCT_OUTPUTSET12_SETn4_Pos 4 /*!< SCT OUTPUTSET12: SETn4 Position */
+#define SCT_OUTPUTSET12_SETn4_Msk (0x01UL << SCT_OUTPUTSET12_SETn4_Pos) /*!< SCT OUTPUTSET12: SETn4 Mask */
+#define SCT_OUTPUTSET12_SETn5_Pos 5 /*!< SCT OUTPUTSET12: SETn5 Position */
+#define SCT_OUTPUTSET12_SETn5_Msk (0x01UL << SCT_OUTPUTSET12_SETn5_Pos) /*!< SCT OUTPUTSET12: SETn5 Mask */
+#define SCT_OUTPUTSET12_SETn6_Pos 6 /*!< SCT OUTPUTSET12: SETn6 Position */
+#define SCT_OUTPUTSET12_SETn6_Msk (0x01UL << SCT_OUTPUTSET12_SETn6_Pos) /*!< SCT OUTPUTSET12: SETn6 Mask */
+#define SCT_OUTPUTSET12_SETn7_Pos 7 /*!< SCT OUTPUTSET12: SETn7 Position */
+#define SCT_OUTPUTSET12_SETn7_Msk (0x01UL << SCT_OUTPUTSET12_SETn7_Pos) /*!< SCT OUTPUTSET12: SETn7 Mask */
+#define SCT_OUTPUTSET12_SETn8_Pos 8 /*!< SCT OUTPUTSET12: SETn8 Position */
+#define SCT_OUTPUTSET12_SETn8_Msk (0x01UL << SCT_OUTPUTSET12_SETn8_Pos) /*!< SCT OUTPUTSET12: SETn8 Mask */
+#define SCT_OUTPUTSET12_SETn9_Pos 9 /*!< SCT OUTPUTSET12: SETn9 Position */
+#define SCT_OUTPUTSET12_SETn9_Msk (0x01UL << SCT_OUTPUTSET12_SETn9_Pos) /*!< SCT OUTPUTSET12: SETn9 Mask */
+#define SCT_OUTPUTSET12_SETn10_Pos 10 /*!< SCT OUTPUTSET12: SETn10 Position */
+#define SCT_OUTPUTSET12_SETn10_Msk (0x01UL << SCT_OUTPUTSET12_SETn10_Pos) /*!< SCT OUTPUTSET12: SETn10 Mask */
+#define SCT_OUTPUTSET12_SETn11_Pos 11 /*!< SCT OUTPUTSET12: SETn11 Position */
+#define SCT_OUTPUTSET12_SETn11_Msk (0x01UL << SCT_OUTPUTSET12_SETn11_Pos) /*!< SCT OUTPUTSET12: SETn11 Mask */
+#define SCT_OUTPUTSET12_SETn12_Pos 12 /*!< SCT OUTPUTSET12: SETn12 Position */
+#define SCT_OUTPUTSET12_SETn12_Msk (0x01UL << SCT_OUTPUTSET12_SETn12_Pos) /*!< SCT OUTPUTSET12: SETn12 Mask */
+#define SCT_OUTPUTSET12_SETn13_Pos 13 /*!< SCT OUTPUTSET12: SETn13 Position */
+#define SCT_OUTPUTSET12_SETn13_Msk (0x01UL << SCT_OUTPUTSET12_SETn13_Pos) /*!< SCT OUTPUTSET12: SETn13 Mask */
+#define SCT_OUTPUTSET12_SETn14_Pos 14 /*!< SCT OUTPUTSET12: SETn14 Position */
+#define SCT_OUTPUTSET12_SETn14_Msk (0x01UL << SCT_OUTPUTSET12_SETn14_Pos) /*!< SCT OUTPUTSET12: SETn14 Mask */
+#define SCT_OUTPUTSET12_SETn15_Pos 15 /*!< SCT OUTPUTSET12: SETn15 Position */
+#define SCT_OUTPUTSET12_SETn15_Msk (0x01UL << SCT_OUTPUTSET12_SETn15_Pos) /*!< SCT OUTPUTSET12: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR12 ----------------------------------------
+#define SCT_OUTPUTCLR12_CLRn0_Pos 0 /*!< SCT OUTPUTCLR12: CLRn0 Position */
+#define SCT_OUTPUTCLR12_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn0_Pos) /*!< SCT OUTPUTCLR12: CLRn0 Mask */
+#define SCT_OUTPUTCLR12_CLRn1_Pos 1 /*!< SCT OUTPUTCLR12: CLRn1 Position */
+#define SCT_OUTPUTCLR12_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn1_Pos) /*!< SCT OUTPUTCLR12: CLRn1 Mask */
+#define SCT_OUTPUTCLR12_CLRn2_Pos 2 /*!< SCT OUTPUTCLR12: CLRn2 Position */
+#define SCT_OUTPUTCLR12_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn2_Pos) /*!< SCT OUTPUTCLR12: CLRn2 Mask */
+#define SCT_OUTPUTCLR12_CLRn3_Pos 3 /*!< SCT OUTPUTCLR12: CLRn3 Position */
+#define SCT_OUTPUTCLR12_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn3_Pos) /*!< SCT OUTPUTCLR12: CLRn3 Mask */
+#define SCT_OUTPUTCLR12_CLRn4_Pos 4 /*!< SCT OUTPUTCLR12: CLRn4 Position */
+#define SCT_OUTPUTCLR12_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn4_Pos) /*!< SCT OUTPUTCLR12: CLRn4 Mask */
+#define SCT_OUTPUTCLR12_CLRn5_Pos 5 /*!< SCT OUTPUTCLR12: CLRn5 Position */
+#define SCT_OUTPUTCLR12_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn5_Pos) /*!< SCT OUTPUTCLR12: CLRn5 Mask */
+#define SCT_OUTPUTCLR12_CLRn6_Pos 6 /*!< SCT OUTPUTCLR12: CLRn6 Position */
+#define SCT_OUTPUTCLR12_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn6_Pos) /*!< SCT OUTPUTCLR12: CLRn6 Mask */
+#define SCT_OUTPUTCLR12_CLRn7_Pos 7 /*!< SCT OUTPUTCLR12: CLRn7 Position */
+#define SCT_OUTPUTCLR12_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn7_Pos) /*!< SCT OUTPUTCLR12: CLRn7 Mask */
+#define SCT_OUTPUTCLR12_CLRn8_Pos 8 /*!< SCT OUTPUTCLR12: CLRn8 Position */
+#define SCT_OUTPUTCLR12_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn8_Pos) /*!< SCT OUTPUTCLR12: CLRn8 Mask */
+#define SCT_OUTPUTCLR12_CLRn9_Pos 9 /*!< SCT OUTPUTCLR12: CLRn9 Position */
+#define SCT_OUTPUTCLR12_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn9_Pos) /*!< SCT OUTPUTCLR12: CLRn9 Mask */
+#define SCT_OUTPUTCLR12_CLRn10_Pos 10 /*!< SCT OUTPUTCLR12: CLRn10 Position */
+#define SCT_OUTPUTCLR12_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn10_Pos) /*!< SCT OUTPUTCLR12: CLRn10 Mask */
+#define SCT_OUTPUTCLR12_CLRn11_Pos 11 /*!< SCT OUTPUTCLR12: CLRn11 Position */
+#define SCT_OUTPUTCLR12_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn11_Pos) /*!< SCT OUTPUTCLR12: CLRn11 Mask */
+#define SCT_OUTPUTCLR12_CLRn12_Pos 12 /*!< SCT OUTPUTCLR12: CLRn12 Position */
+#define SCT_OUTPUTCLR12_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn12_Pos) /*!< SCT OUTPUTCLR12: CLRn12 Mask */
+#define SCT_OUTPUTCLR12_CLRn13_Pos 13 /*!< SCT OUTPUTCLR12: CLRn13 Position */
+#define SCT_OUTPUTCLR12_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn13_Pos) /*!< SCT OUTPUTCLR12: CLRn13 Mask */
+#define SCT_OUTPUTCLR12_CLRn14_Pos 14 /*!< SCT OUTPUTCLR12: CLRn14 Position */
+#define SCT_OUTPUTCLR12_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn14_Pos) /*!< SCT OUTPUTCLR12: CLRn14 Mask */
+#define SCT_OUTPUTCLR12_CLRn15_Pos 15 /*!< SCT OUTPUTCLR12: CLRn15 Position */
+#define SCT_OUTPUTCLR12_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn15_Pos) /*!< SCT OUTPUTCLR12: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET13 ----------------------------------------
+#define SCT_OUTPUTSET13_SETn0_Pos 0 /*!< SCT OUTPUTSET13: SETn0 Position */
+#define SCT_OUTPUTSET13_SETn0_Msk (0x01UL << SCT_OUTPUTSET13_SETn0_Pos) /*!< SCT OUTPUTSET13: SETn0 Mask */
+#define SCT_OUTPUTSET13_SETn1_Pos 1 /*!< SCT OUTPUTSET13: SETn1 Position */
+#define SCT_OUTPUTSET13_SETn1_Msk (0x01UL << SCT_OUTPUTSET13_SETn1_Pos) /*!< SCT OUTPUTSET13: SETn1 Mask */
+#define SCT_OUTPUTSET13_SETn2_Pos 2 /*!< SCT OUTPUTSET13: SETn2 Position */
+#define SCT_OUTPUTSET13_SETn2_Msk (0x01UL << SCT_OUTPUTSET13_SETn2_Pos) /*!< SCT OUTPUTSET13: SETn2 Mask */
+#define SCT_OUTPUTSET13_SETn3_Pos 3 /*!< SCT OUTPUTSET13: SETn3 Position */
+#define SCT_OUTPUTSET13_SETn3_Msk (0x01UL << SCT_OUTPUTSET13_SETn3_Pos) /*!< SCT OUTPUTSET13: SETn3 Mask */
+#define SCT_OUTPUTSET13_SETn4_Pos 4 /*!< SCT OUTPUTSET13: SETn4 Position */
+#define SCT_OUTPUTSET13_SETn4_Msk (0x01UL << SCT_OUTPUTSET13_SETn4_Pos) /*!< SCT OUTPUTSET13: SETn4 Mask */
+#define SCT_OUTPUTSET13_SETn5_Pos 5 /*!< SCT OUTPUTSET13: SETn5 Position */
+#define SCT_OUTPUTSET13_SETn5_Msk (0x01UL << SCT_OUTPUTSET13_SETn5_Pos) /*!< SCT OUTPUTSET13: SETn5 Mask */
+#define SCT_OUTPUTSET13_SETn6_Pos 6 /*!< SCT OUTPUTSET13: SETn6 Position */
+#define SCT_OUTPUTSET13_SETn6_Msk (0x01UL << SCT_OUTPUTSET13_SETn6_Pos) /*!< SCT OUTPUTSET13: SETn6 Mask */
+#define SCT_OUTPUTSET13_SETn7_Pos 7 /*!< SCT OUTPUTSET13: SETn7 Position */
+#define SCT_OUTPUTSET13_SETn7_Msk (0x01UL << SCT_OUTPUTSET13_SETn7_Pos) /*!< SCT OUTPUTSET13: SETn7 Mask */
+#define SCT_OUTPUTSET13_SETn8_Pos 8 /*!< SCT OUTPUTSET13: SETn8 Position */
+#define SCT_OUTPUTSET13_SETn8_Msk (0x01UL << SCT_OUTPUTSET13_SETn8_Pos) /*!< SCT OUTPUTSET13: SETn8 Mask */
+#define SCT_OUTPUTSET13_SETn9_Pos 9 /*!< SCT OUTPUTSET13: SETn9 Position */
+#define SCT_OUTPUTSET13_SETn9_Msk (0x01UL << SCT_OUTPUTSET13_SETn9_Pos) /*!< SCT OUTPUTSET13: SETn9 Mask */
+#define SCT_OUTPUTSET13_SETn10_Pos 10 /*!< SCT OUTPUTSET13: SETn10 Position */
+#define SCT_OUTPUTSET13_SETn10_Msk (0x01UL << SCT_OUTPUTSET13_SETn10_Pos) /*!< SCT OUTPUTSET13: SETn10 Mask */
+#define SCT_OUTPUTSET13_SETn11_Pos 11 /*!< SCT OUTPUTSET13: SETn11 Position */
+#define SCT_OUTPUTSET13_SETn11_Msk (0x01UL << SCT_OUTPUTSET13_SETn11_Pos) /*!< SCT OUTPUTSET13: SETn11 Mask */
+#define SCT_OUTPUTSET13_SETn12_Pos 12 /*!< SCT OUTPUTSET13: SETn12 Position */
+#define SCT_OUTPUTSET13_SETn12_Msk (0x01UL << SCT_OUTPUTSET13_SETn12_Pos) /*!< SCT OUTPUTSET13: SETn12 Mask */
+#define SCT_OUTPUTSET13_SETn13_Pos 13 /*!< SCT OUTPUTSET13: SETn13 Position */
+#define SCT_OUTPUTSET13_SETn13_Msk (0x01UL << SCT_OUTPUTSET13_SETn13_Pos) /*!< SCT OUTPUTSET13: SETn13 Mask */
+#define SCT_OUTPUTSET13_SETn14_Pos 14 /*!< SCT OUTPUTSET13: SETn14 Position */
+#define SCT_OUTPUTSET13_SETn14_Msk (0x01UL << SCT_OUTPUTSET13_SETn14_Pos) /*!< SCT OUTPUTSET13: SETn14 Mask */
+#define SCT_OUTPUTSET13_SETn15_Pos 15 /*!< SCT OUTPUTSET13: SETn15 Position */
+#define SCT_OUTPUTSET13_SETn15_Msk (0x01UL << SCT_OUTPUTSET13_SETn15_Pos) /*!< SCT OUTPUTSET13: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR13 ----------------------------------------
+#define SCT_OUTPUTCLR13_CLRn0_Pos 0 /*!< SCT OUTPUTCLR13: CLRn0 Position */
+#define SCT_OUTPUTCLR13_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn0_Pos) /*!< SCT OUTPUTCLR13: CLRn0 Mask */
+#define SCT_OUTPUTCLR13_CLRn1_Pos 1 /*!< SCT OUTPUTCLR13: CLRn1 Position */
+#define SCT_OUTPUTCLR13_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn1_Pos) /*!< SCT OUTPUTCLR13: CLRn1 Mask */
+#define SCT_OUTPUTCLR13_CLRn2_Pos 2 /*!< SCT OUTPUTCLR13: CLRn2 Position */
+#define SCT_OUTPUTCLR13_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn2_Pos) /*!< SCT OUTPUTCLR13: CLRn2 Mask */
+#define SCT_OUTPUTCLR13_CLRn3_Pos 3 /*!< SCT OUTPUTCLR13: CLRn3 Position */
+#define SCT_OUTPUTCLR13_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn3_Pos) /*!< SCT OUTPUTCLR13: CLRn3 Mask */
+#define SCT_OUTPUTCLR13_CLRn4_Pos 4 /*!< SCT OUTPUTCLR13: CLRn4 Position */
+#define SCT_OUTPUTCLR13_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn4_Pos) /*!< SCT OUTPUTCLR13: CLRn4 Mask */
+#define SCT_OUTPUTCLR13_CLRn5_Pos 5 /*!< SCT OUTPUTCLR13: CLRn5 Position */
+#define SCT_OUTPUTCLR13_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn5_Pos) /*!< SCT OUTPUTCLR13: CLRn5 Mask */
+#define SCT_OUTPUTCLR13_CLRn6_Pos 6 /*!< SCT OUTPUTCLR13: CLRn6 Position */
+#define SCT_OUTPUTCLR13_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn6_Pos) /*!< SCT OUTPUTCLR13: CLRn6 Mask */
+#define SCT_OUTPUTCLR13_CLRn7_Pos 7 /*!< SCT OUTPUTCLR13: CLRn7 Position */
+#define SCT_OUTPUTCLR13_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn7_Pos) /*!< SCT OUTPUTCLR13: CLRn7 Mask */
+#define SCT_OUTPUTCLR13_CLRn8_Pos 8 /*!< SCT OUTPUTCLR13: CLRn8 Position */
+#define SCT_OUTPUTCLR13_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn8_Pos) /*!< SCT OUTPUTCLR13: CLRn8 Mask */
+#define SCT_OUTPUTCLR13_CLRn9_Pos 9 /*!< SCT OUTPUTCLR13: CLRn9 Position */
+#define SCT_OUTPUTCLR13_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn9_Pos) /*!< SCT OUTPUTCLR13: CLRn9 Mask */
+#define SCT_OUTPUTCLR13_CLRn10_Pos 10 /*!< SCT OUTPUTCLR13: CLRn10 Position */
+#define SCT_OUTPUTCLR13_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn10_Pos) /*!< SCT OUTPUTCLR13: CLRn10 Mask */
+#define SCT_OUTPUTCLR13_CLRn11_Pos 11 /*!< SCT OUTPUTCLR13: CLRn11 Position */
+#define SCT_OUTPUTCLR13_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn11_Pos) /*!< SCT OUTPUTCLR13: CLRn11 Mask */
+#define SCT_OUTPUTCLR13_CLRn12_Pos 12 /*!< SCT OUTPUTCLR13: CLRn12 Position */
+#define SCT_OUTPUTCLR13_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn12_Pos) /*!< SCT OUTPUTCLR13: CLRn12 Mask */
+#define SCT_OUTPUTCLR13_CLRn13_Pos 13 /*!< SCT OUTPUTCLR13: CLRn13 Position */
+#define SCT_OUTPUTCLR13_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn13_Pos) /*!< SCT OUTPUTCLR13: CLRn13 Mask */
+#define SCT_OUTPUTCLR13_CLRn14_Pos 14 /*!< SCT OUTPUTCLR13: CLRn14 Position */
+#define SCT_OUTPUTCLR13_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn14_Pos) /*!< SCT OUTPUTCLR13: CLRn14 Mask */
+#define SCT_OUTPUTCLR13_CLRn15_Pos 15 /*!< SCT OUTPUTCLR13: CLRn15 Position */
+#define SCT_OUTPUTCLR13_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn15_Pos) /*!< SCT OUTPUTCLR13: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET14 ----------------------------------------
+#define SCT_OUTPUTSET14_SETn0_Pos 0 /*!< SCT OUTPUTSET14: SETn0 Position */
+#define SCT_OUTPUTSET14_SETn0_Msk (0x01UL << SCT_OUTPUTSET14_SETn0_Pos) /*!< SCT OUTPUTSET14: SETn0 Mask */
+#define SCT_OUTPUTSET14_SETn1_Pos 1 /*!< SCT OUTPUTSET14: SETn1 Position */
+#define SCT_OUTPUTSET14_SETn1_Msk (0x01UL << SCT_OUTPUTSET14_SETn1_Pos) /*!< SCT OUTPUTSET14: SETn1 Mask */
+#define SCT_OUTPUTSET14_SETn2_Pos 2 /*!< SCT OUTPUTSET14: SETn2 Position */
+#define SCT_OUTPUTSET14_SETn2_Msk (0x01UL << SCT_OUTPUTSET14_SETn2_Pos) /*!< SCT OUTPUTSET14: SETn2 Mask */
+#define SCT_OUTPUTSET14_SETn3_Pos 3 /*!< SCT OUTPUTSET14: SETn3 Position */
+#define SCT_OUTPUTSET14_SETn3_Msk (0x01UL << SCT_OUTPUTSET14_SETn3_Pos) /*!< SCT OUTPUTSET14: SETn3 Mask */
+#define SCT_OUTPUTSET14_SETn4_Pos 4 /*!< SCT OUTPUTSET14: SETn4 Position */
+#define SCT_OUTPUTSET14_SETn4_Msk (0x01UL << SCT_OUTPUTSET14_SETn4_Pos) /*!< SCT OUTPUTSET14: SETn4 Mask */
+#define SCT_OUTPUTSET14_SETn5_Pos 5 /*!< SCT OUTPUTSET14: SETn5 Position */
+#define SCT_OUTPUTSET14_SETn5_Msk (0x01UL << SCT_OUTPUTSET14_SETn5_Pos) /*!< SCT OUTPUTSET14: SETn5 Mask */
+#define SCT_OUTPUTSET14_SETn6_Pos 6 /*!< SCT OUTPUTSET14: SETn6 Position */
+#define SCT_OUTPUTSET14_SETn6_Msk (0x01UL << SCT_OUTPUTSET14_SETn6_Pos) /*!< SCT OUTPUTSET14: SETn6 Mask */
+#define SCT_OUTPUTSET14_SETn7_Pos 7 /*!< SCT OUTPUTSET14: SETn7 Position */
+#define SCT_OUTPUTSET14_SETn7_Msk (0x01UL << SCT_OUTPUTSET14_SETn7_Pos) /*!< SCT OUTPUTSET14: SETn7 Mask */
+#define SCT_OUTPUTSET14_SETn8_Pos 8 /*!< SCT OUTPUTSET14: SETn8 Position */
+#define SCT_OUTPUTSET14_SETn8_Msk (0x01UL << SCT_OUTPUTSET14_SETn8_Pos) /*!< SCT OUTPUTSET14: SETn8 Mask */
+#define SCT_OUTPUTSET14_SETn9_Pos 9 /*!< SCT OUTPUTSET14: SETn9 Position */
+#define SCT_OUTPUTSET14_SETn9_Msk (0x01UL << SCT_OUTPUTSET14_SETn9_Pos) /*!< SCT OUTPUTSET14: SETn9 Mask */
+#define SCT_OUTPUTSET14_SETn10_Pos 10 /*!< SCT OUTPUTSET14: SETn10 Position */
+#define SCT_OUTPUTSET14_SETn10_Msk (0x01UL << SCT_OUTPUTSET14_SETn10_Pos) /*!< SCT OUTPUTSET14: SETn10 Mask */
+#define SCT_OUTPUTSET14_SETn11_Pos 11 /*!< SCT OUTPUTSET14: SETn11 Position */
+#define SCT_OUTPUTSET14_SETn11_Msk (0x01UL << SCT_OUTPUTSET14_SETn11_Pos) /*!< SCT OUTPUTSET14: SETn11 Mask */
+#define SCT_OUTPUTSET14_SETn12_Pos 12 /*!< SCT OUTPUTSET14: SETn12 Position */
+#define SCT_OUTPUTSET14_SETn12_Msk (0x01UL << SCT_OUTPUTSET14_SETn12_Pos) /*!< SCT OUTPUTSET14: SETn12 Mask */
+#define SCT_OUTPUTSET14_SETn13_Pos 13 /*!< SCT OUTPUTSET14: SETn13 Position */
+#define SCT_OUTPUTSET14_SETn13_Msk (0x01UL << SCT_OUTPUTSET14_SETn13_Pos) /*!< SCT OUTPUTSET14: SETn13 Mask */
+#define SCT_OUTPUTSET14_SETn14_Pos 14 /*!< SCT OUTPUTSET14: SETn14 Position */
+#define SCT_OUTPUTSET14_SETn14_Msk (0x01UL << SCT_OUTPUTSET14_SETn14_Pos) /*!< SCT OUTPUTSET14: SETn14 Mask */
+#define SCT_OUTPUTSET14_SETn15_Pos 15 /*!< SCT OUTPUTSET14: SETn15 Position */
+#define SCT_OUTPUTSET14_SETn15_Msk (0x01UL << SCT_OUTPUTSET14_SETn15_Pos) /*!< SCT OUTPUTSET14: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR14 ----------------------------------------
+#define SCT_OUTPUTCLR14_CLRn0_Pos 0 /*!< SCT OUTPUTCLR14: CLRn0 Position */
+#define SCT_OUTPUTCLR14_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn0_Pos) /*!< SCT OUTPUTCLR14: CLRn0 Mask */
+#define SCT_OUTPUTCLR14_CLRn1_Pos 1 /*!< SCT OUTPUTCLR14: CLRn1 Position */
+#define SCT_OUTPUTCLR14_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn1_Pos) /*!< SCT OUTPUTCLR14: CLRn1 Mask */
+#define SCT_OUTPUTCLR14_CLRn2_Pos 2 /*!< SCT OUTPUTCLR14: CLRn2 Position */
+#define SCT_OUTPUTCLR14_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn2_Pos) /*!< SCT OUTPUTCLR14: CLRn2 Mask */
+#define SCT_OUTPUTCLR14_CLRn3_Pos 3 /*!< SCT OUTPUTCLR14: CLRn3 Position */
+#define SCT_OUTPUTCLR14_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn3_Pos) /*!< SCT OUTPUTCLR14: CLRn3 Mask */
+#define SCT_OUTPUTCLR14_CLRn4_Pos 4 /*!< SCT OUTPUTCLR14: CLRn4 Position */
+#define SCT_OUTPUTCLR14_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn4_Pos) /*!< SCT OUTPUTCLR14: CLRn4 Mask */
+#define SCT_OUTPUTCLR14_CLRn5_Pos 5 /*!< SCT OUTPUTCLR14: CLRn5 Position */
+#define SCT_OUTPUTCLR14_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn5_Pos) /*!< SCT OUTPUTCLR14: CLRn5 Mask */
+#define SCT_OUTPUTCLR14_CLRn6_Pos 6 /*!< SCT OUTPUTCLR14: CLRn6 Position */
+#define SCT_OUTPUTCLR14_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn6_Pos) /*!< SCT OUTPUTCLR14: CLRn6 Mask */
+#define SCT_OUTPUTCLR14_CLRn7_Pos 7 /*!< SCT OUTPUTCLR14: CLRn7 Position */
+#define SCT_OUTPUTCLR14_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn7_Pos) /*!< SCT OUTPUTCLR14: CLRn7 Mask */
+#define SCT_OUTPUTCLR14_CLRn8_Pos 8 /*!< SCT OUTPUTCLR14: CLRn8 Position */
+#define SCT_OUTPUTCLR14_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn8_Pos) /*!< SCT OUTPUTCLR14: CLRn8 Mask */
+#define SCT_OUTPUTCLR14_CLRn9_Pos 9 /*!< SCT OUTPUTCLR14: CLRn9 Position */
+#define SCT_OUTPUTCLR14_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn9_Pos) /*!< SCT OUTPUTCLR14: CLRn9 Mask */
+#define SCT_OUTPUTCLR14_CLRn10_Pos 10 /*!< SCT OUTPUTCLR14: CLRn10 Position */
+#define SCT_OUTPUTCLR14_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn10_Pos) /*!< SCT OUTPUTCLR14: CLRn10 Mask */
+#define SCT_OUTPUTCLR14_CLRn11_Pos 11 /*!< SCT OUTPUTCLR14: CLRn11 Position */
+#define SCT_OUTPUTCLR14_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn11_Pos) /*!< SCT OUTPUTCLR14: CLRn11 Mask */
+#define SCT_OUTPUTCLR14_CLRn12_Pos 12 /*!< SCT OUTPUTCLR14: CLRn12 Position */
+#define SCT_OUTPUTCLR14_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn12_Pos) /*!< SCT OUTPUTCLR14: CLRn12 Mask */
+#define SCT_OUTPUTCLR14_CLRn13_Pos 13 /*!< SCT OUTPUTCLR14: CLRn13 Position */
+#define SCT_OUTPUTCLR14_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn13_Pos) /*!< SCT OUTPUTCLR14: CLRn13 Mask */
+#define SCT_OUTPUTCLR14_CLRn14_Pos 14 /*!< SCT OUTPUTCLR14: CLRn14 Position */
+#define SCT_OUTPUTCLR14_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn14_Pos) /*!< SCT OUTPUTCLR14: CLRn14 Mask */
+#define SCT_OUTPUTCLR14_CLRn15_Pos 15 /*!< SCT OUTPUTCLR14: CLRn15 Position */
+#define SCT_OUTPUTCLR14_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn15_Pos) /*!< SCT OUTPUTCLR14: CLRn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTSET15 ----------------------------------------
+#define SCT_OUTPUTSET15_SETn0_Pos 0 /*!< SCT OUTPUTSET15: SETn0 Position */
+#define SCT_OUTPUTSET15_SETn0_Msk (0x01UL << SCT_OUTPUTSET15_SETn0_Pos) /*!< SCT OUTPUTSET15: SETn0 Mask */
+#define SCT_OUTPUTSET15_SETn1_Pos 1 /*!< SCT OUTPUTSET15: SETn1 Position */
+#define SCT_OUTPUTSET15_SETn1_Msk (0x01UL << SCT_OUTPUTSET15_SETn1_Pos) /*!< SCT OUTPUTSET15: SETn1 Mask */
+#define SCT_OUTPUTSET15_SETn2_Pos 2 /*!< SCT OUTPUTSET15: SETn2 Position */
+#define SCT_OUTPUTSET15_SETn2_Msk (0x01UL << SCT_OUTPUTSET15_SETn2_Pos) /*!< SCT OUTPUTSET15: SETn2 Mask */
+#define SCT_OUTPUTSET15_SETn3_Pos 3 /*!< SCT OUTPUTSET15: SETn3 Position */
+#define SCT_OUTPUTSET15_SETn3_Msk (0x01UL << SCT_OUTPUTSET15_SETn3_Pos) /*!< SCT OUTPUTSET15: SETn3 Mask */
+#define SCT_OUTPUTSET15_SETn4_Pos 4 /*!< SCT OUTPUTSET15: SETn4 Position */
+#define SCT_OUTPUTSET15_SETn4_Msk (0x01UL << SCT_OUTPUTSET15_SETn4_Pos) /*!< SCT OUTPUTSET15: SETn4 Mask */
+#define SCT_OUTPUTSET15_SETn5_Pos 5 /*!< SCT OUTPUTSET15: SETn5 Position */
+#define SCT_OUTPUTSET15_SETn5_Msk (0x01UL << SCT_OUTPUTSET15_SETn5_Pos) /*!< SCT OUTPUTSET15: SETn5 Mask */
+#define SCT_OUTPUTSET15_SETn6_Pos 6 /*!< SCT OUTPUTSET15: SETn6 Position */
+#define SCT_OUTPUTSET15_SETn6_Msk (0x01UL << SCT_OUTPUTSET15_SETn6_Pos) /*!< SCT OUTPUTSET15: SETn6 Mask */
+#define SCT_OUTPUTSET15_SETn7_Pos 7 /*!< SCT OUTPUTSET15: SETn7 Position */
+#define SCT_OUTPUTSET15_SETn7_Msk (0x01UL << SCT_OUTPUTSET15_SETn7_Pos) /*!< SCT OUTPUTSET15: SETn7 Mask */
+#define SCT_OUTPUTSET15_SETn8_Pos 8 /*!< SCT OUTPUTSET15: SETn8 Position */
+#define SCT_OUTPUTSET15_SETn8_Msk (0x01UL << SCT_OUTPUTSET15_SETn8_Pos) /*!< SCT OUTPUTSET15: SETn8 Mask */
+#define SCT_OUTPUTSET15_SETn9_Pos 9 /*!< SCT OUTPUTSET15: SETn9 Position */
+#define SCT_OUTPUTSET15_SETn9_Msk (0x01UL << SCT_OUTPUTSET15_SETn9_Pos) /*!< SCT OUTPUTSET15: SETn9 Mask */
+#define SCT_OUTPUTSET15_SETn10_Pos 10 /*!< SCT OUTPUTSET15: SETn10 Position */
+#define SCT_OUTPUTSET15_SETn10_Msk (0x01UL << SCT_OUTPUTSET15_SETn10_Pos) /*!< SCT OUTPUTSET15: SETn10 Mask */
+#define SCT_OUTPUTSET15_SETn11_Pos 11 /*!< SCT OUTPUTSET15: SETn11 Position */
+#define SCT_OUTPUTSET15_SETn11_Msk (0x01UL << SCT_OUTPUTSET15_SETn11_Pos) /*!< SCT OUTPUTSET15: SETn11 Mask */
+#define SCT_OUTPUTSET15_SETn12_Pos 12 /*!< SCT OUTPUTSET15: SETn12 Position */
+#define SCT_OUTPUTSET15_SETn12_Msk (0x01UL << SCT_OUTPUTSET15_SETn12_Pos) /*!< SCT OUTPUTSET15: SETn12 Mask */
+#define SCT_OUTPUTSET15_SETn13_Pos 13 /*!< SCT OUTPUTSET15: SETn13 Position */
+#define SCT_OUTPUTSET15_SETn13_Msk (0x01UL << SCT_OUTPUTSET15_SETn13_Pos) /*!< SCT OUTPUTSET15: SETn13 Mask */
+#define SCT_OUTPUTSET15_SETn14_Pos 14 /*!< SCT OUTPUTSET15: SETn14 Position */
+#define SCT_OUTPUTSET15_SETn14_Msk (0x01UL << SCT_OUTPUTSET15_SETn14_Pos) /*!< SCT OUTPUTSET15: SETn14 Mask */
+#define SCT_OUTPUTSET15_SETn15_Pos 15 /*!< SCT OUTPUTSET15: SETn15 Position */
+#define SCT_OUTPUTSET15_SETn15_Msk (0x01UL << SCT_OUTPUTSET15_SETn15_Pos) /*!< SCT OUTPUTSET15: SETn15 Mask */
+
+// ------------------------------------- SCT_OUTPUTCLR15 ----------------------------------------
+#define SCT_OUTPUTCLR15_CLRn0_Pos 0 /*!< SCT OUTPUTCLR15: CLRn0 Position */
+#define SCT_OUTPUTCLR15_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn0_Pos) /*!< SCT OUTPUTCLR15: CLRn0 Mask */
+#define SCT_OUTPUTCLR15_CLRn1_Pos 1 /*!< SCT OUTPUTCLR15: CLRn1 Position */
+#define SCT_OUTPUTCLR15_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn1_Pos) /*!< SCT OUTPUTCLR15: CLRn1 Mask */
+#define SCT_OUTPUTCLR15_CLRn2_Pos 2 /*!< SCT OUTPUTCLR15: CLRn2 Position */
+#define SCT_OUTPUTCLR15_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn2_Pos) /*!< SCT OUTPUTCLR15: CLRn2 Mask */
+#define SCT_OUTPUTCLR15_CLRn3_Pos 3 /*!< SCT OUTPUTCLR15: CLRn3 Position */
+#define SCT_OUTPUTCLR15_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn3_Pos) /*!< SCT OUTPUTCLR15: CLRn3 Mask */
+#define SCT_OUTPUTCLR15_CLRn4_Pos 4 /*!< SCT OUTPUTCLR15: CLRn4 Position */
+#define SCT_OUTPUTCLR15_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn4_Pos) /*!< SCT OUTPUTCLR15: CLRn4 Mask */
+#define SCT_OUTPUTCLR15_CLRn5_Pos 5 /*!< SCT OUTPUTCLR15: CLRn5 Position */
+#define SCT_OUTPUTCLR15_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn5_Pos) /*!< SCT OUTPUTCLR15: CLRn5 Mask */
+#define SCT_OUTPUTCLR15_CLRn6_Pos 6 /*!< SCT OUTPUTCLR15: CLRn6 Position */
+#define SCT_OUTPUTCLR15_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn6_Pos) /*!< SCT OUTPUTCLR15: CLRn6 Mask */
+#define SCT_OUTPUTCLR15_CLRn7_Pos 7 /*!< SCT OUTPUTCLR15: CLRn7 Position */
+#define SCT_OUTPUTCLR15_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn7_Pos) /*!< SCT OUTPUTCLR15: CLRn7 Mask */
+#define SCT_OUTPUTCLR15_CLRn8_Pos 8 /*!< SCT OUTPUTCLR15: CLRn8 Position */
+#define SCT_OUTPUTCLR15_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn8_Pos) /*!< SCT OUTPUTCLR15: CLRn8 Mask */
+#define SCT_OUTPUTCLR15_CLRn9_Pos 9 /*!< SCT OUTPUTCLR15: CLRn9 Position */
+#define SCT_OUTPUTCLR15_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn9_Pos) /*!< SCT OUTPUTCLR15: CLRn9 Mask */
+#define SCT_OUTPUTCLR15_CLRn10_Pos 10 /*!< SCT OUTPUTCLR15: CLRn10 Position */
+#define SCT_OUTPUTCLR15_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn10_Pos) /*!< SCT OUTPUTCLR15: CLRn10 Mask */
+#define SCT_OUTPUTCLR15_CLRn11_Pos 11 /*!< SCT OUTPUTCLR15: CLRn11 Position */
+#define SCT_OUTPUTCLR15_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn11_Pos) /*!< SCT OUTPUTCLR15: CLRn11 Mask */
+#define SCT_OUTPUTCLR15_CLRn12_Pos 12 /*!< SCT OUTPUTCLR15: CLRn12 Position */
+#define SCT_OUTPUTCLR15_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn12_Pos) /*!< SCT OUTPUTCLR15: CLRn12 Mask */
+#define SCT_OUTPUTCLR15_CLRn13_Pos 13 /*!< SCT OUTPUTCLR15: CLRn13 Position */
+#define SCT_OUTPUTCLR15_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn13_Pos) /*!< SCT OUTPUTCLR15: CLRn13 Mask */
+#define SCT_OUTPUTCLR15_CLRn14_Pos 14 /*!< SCT OUTPUTCLR15: CLRn14 Position */
+#define SCT_OUTPUTCLR15_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn14_Pos) /*!< SCT OUTPUTCLR15: CLRn14 Mask */
+#define SCT_OUTPUTCLR15_CLRn15_Pos 15 /*!< SCT OUTPUTCLR15: CLRn15 Position */
+#define SCT_OUTPUTCLR15_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn15_Pos) /*!< SCT OUTPUTCLR15: CLRn15 Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPDMA Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -------------------------------------- GPDMA_INTSTAT -----------------------------------------
+#define GPDMA_INTSTAT_INTSTAT0_Pos 0 /*!< GPDMA INTSTAT: INTSTAT0 Position */
+#define GPDMA_INTSTAT_INTSTAT0_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT0_Pos) /*!< GPDMA INTSTAT: INTSTAT0 Mask */
+#define GPDMA_INTSTAT_INTSTAT1_Pos 1 /*!< GPDMA INTSTAT: INTSTAT1 Position */
+#define GPDMA_INTSTAT_INTSTAT1_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT1_Pos) /*!< GPDMA INTSTAT: INTSTAT1 Mask */
+#define GPDMA_INTSTAT_INTSTAT2_Pos 2 /*!< GPDMA INTSTAT: INTSTAT2 Position */
+#define GPDMA_INTSTAT_INTSTAT2_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT2_Pos) /*!< GPDMA INTSTAT: INTSTAT2 Mask */
+#define GPDMA_INTSTAT_INTSTAT3_Pos 3 /*!< GPDMA INTSTAT: INTSTAT3 Position */
+#define GPDMA_INTSTAT_INTSTAT3_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT3_Pos) /*!< GPDMA INTSTAT: INTSTAT3 Mask */
+#define GPDMA_INTSTAT_INTSTAT4_Pos 4 /*!< GPDMA INTSTAT: INTSTAT4 Position */
+#define GPDMA_INTSTAT_INTSTAT4_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT4_Pos) /*!< GPDMA INTSTAT: INTSTAT4 Mask */
+#define GPDMA_INTSTAT_INTSTAT5_Pos 5 /*!< GPDMA INTSTAT: INTSTAT5 Position */
+#define GPDMA_INTSTAT_INTSTAT5_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT5_Pos) /*!< GPDMA INTSTAT: INTSTAT5 Mask */
+#define GPDMA_INTSTAT_INTSTAT6_Pos 6 /*!< GPDMA INTSTAT: INTSTAT6 Position */
+#define GPDMA_INTSTAT_INTSTAT6_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT6_Pos) /*!< GPDMA INTSTAT: INTSTAT6 Mask */
+#define GPDMA_INTSTAT_INTSTAT7_Pos 7 /*!< GPDMA INTSTAT: INTSTAT7 Position */
+#define GPDMA_INTSTAT_INTSTAT7_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT7_Pos) /*!< GPDMA INTSTAT: INTSTAT7 Mask */
+
+// ------------------------------------- GPDMA_INTTCSTAT ----------------------------------------
+#define GPDMA_INTTCSTAT_INTTCSTAT0_Pos 0 /*!< GPDMA INTTCSTAT: INTTCSTAT0 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT0_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT0_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT0 Mask */
+#define GPDMA_INTTCSTAT_INTTCSTAT1_Pos 1 /*!< GPDMA INTTCSTAT: INTTCSTAT1 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT1_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT1_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT1 Mask */
+#define GPDMA_INTTCSTAT_INTTCSTAT2_Pos 2 /*!< GPDMA INTTCSTAT: INTTCSTAT2 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT2_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT2_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT2 Mask */
+#define GPDMA_INTTCSTAT_INTTCSTAT3_Pos 3 /*!< GPDMA INTTCSTAT: INTTCSTAT3 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT3_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT3_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT3 Mask */
+#define GPDMA_INTTCSTAT_INTTCSTAT4_Pos 4 /*!< GPDMA INTTCSTAT: INTTCSTAT4 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT4_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT4_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT4 Mask */
+#define GPDMA_INTTCSTAT_INTTCSTAT5_Pos 5 /*!< GPDMA INTTCSTAT: INTTCSTAT5 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT5_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT5_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT5 Mask */
+#define GPDMA_INTTCSTAT_INTTCSTAT6_Pos 6 /*!< GPDMA INTTCSTAT: INTTCSTAT6 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT6_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT6_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT6 Mask */
+#define GPDMA_INTTCSTAT_INTTCSTAT7_Pos 7 /*!< GPDMA INTTCSTAT: INTTCSTAT7 Position */
+#define GPDMA_INTTCSTAT_INTTCSTAT7_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT7_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT7 Mask */
+
+// ------------------------------------ GPDMA_INTTCCLEAR ----------------------------------------
+#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos 0 /*!< GPDMA INTTCCLEAR: INTTCCLEAR0 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR0 Mask */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos 1 /*!< GPDMA INTTCCLEAR: INTTCCLEAR1 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR1 Mask */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos 2 /*!< GPDMA INTTCCLEAR: INTTCCLEAR2 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR2 Mask */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos 3 /*!< GPDMA INTTCCLEAR: INTTCCLEAR3 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR3 Mask */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos 4 /*!< GPDMA INTTCCLEAR: INTTCCLEAR4 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR4 Mask */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos 5 /*!< GPDMA INTTCCLEAR: INTTCCLEAR5 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR5 Mask */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos 6 /*!< GPDMA INTTCCLEAR: INTTCCLEAR6 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR6 Mask */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos 7 /*!< GPDMA INTTCCLEAR: INTTCCLEAR7 Position */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR7 Mask */
+
+// ------------------------------------ GPDMA_INTERRSTAT ----------------------------------------
+#define GPDMA_INTERRSTAT_INTERRSTAT0_Pos 0 /*!< GPDMA INTERRSTAT: INTERRSTAT0 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT0_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT0_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT0 Mask */
+#define GPDMA_INTERRSTAT_INTERRSTAT1_Pos 1 /*!< GPDMA INTERRSTAT: INTERRSTAT1 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT1_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT1_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT1 Mask */
+#define GPDMA_INTERRSTAT_INTERRSTAT2_Pos 2 /*!< GPDMA INTERRSTAT: INTERRSTAT2 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT2_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT2_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT2 Mask */
+#define GPDMA_INTERRSTAT_INTERRSTAT3_Pos 3 /*!< GPDMA INTERRSTAT: INTERRSTAT3 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT3_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT3_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT3 Mask */
+#define GPDMA_INTERRSTAT_INTERRSTAT4_Pos 4 /*!< GPDMA INTERRSTAT: INTERRSTAT4 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT4_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT4_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT4 Mask */
+#define GPDMA_INTERRSTAT_INTERRSTAT5_Pos 5 /*!< GPDMA INTERRSTAT: INTERRSTAT5 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT5_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT5_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT5 Mask */
+#define GPDMA_INTERRSTAT_INTERRSTAT6_Pos 6 /*!< GPDMA INTERRSTAT: INTERRSTAT6 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT6_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT6_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT6 Mask */
+#define GPDMA_INTERRSTAT_INTERRSTAT7_Pos 7 /*!< GPDMA INTERRSTAT: INTERRSTAT7 Position */
+#define GPDMA_INTERRSTAT_INTERRSTAT7_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT7_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT7 Mask */
+
+// ------------------------------------- GPDMA_INTERRCLR ----------------------------------------
+#define GPDMA_INTERRCLR_INTERRCLR0_Pos 0 /*!< GPDMA INTERRCLR: INTERRCLR0 Position */
+#define GPDMA_INTERRCLR_INTERRCLR0_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR0_Pos) /*!< GPDMA INTERRCLR: INTERRCLR0 Mask */
+#define GPDMA_INTERRCLR_INTERRCLR1_Pos 1 /*!< GPDMA INTERRCLR: INTERRCLR1 Position */
+#define GPDMA_INTERRCLR_INTERRCLR1_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR1_Pos) /*!< GPDMA INTERRCLR: INTERRCLR1 Mask */
+#define GPDMA_INTERRCLR_INTERRCLR2_Pos 2 /*!< GPDMA INTERRCLR: INTERRCLR2 Position */
+#define GPDMA_INTERRCLR_INTERRCLR2_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR2_Pos) /*!< GPDMA INTERRCLR: INTERRCLR2 Mask */
+#define GPDMA_INTERRCLR_INTERRCLR3_Pos 3 /*!< GPDMA INTERRCLR: INTERRCLR3 Position */
+#define GPDMA_INTERRCLR_INTERRCLR3_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR3_Pos) /*!< GPDMA INTERRCLR: INTERRCLR3 Mask */
+#define GPDMA_INTERRCLR_INTERRCLR4_Pos 4 /*!< GPDMA INTERRCLR: INTERRCLR4 Position */
+#define GPDMA_INTERRCLR_INTERRCLR4_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR4_Pos) /*!< GPDMA INTERRCLR: INTERRCLR4 Mask */
+#define GPDMA_INTERRCLR_INTERRCLR5_Pos 5 /*!< GPDMA INTERRCLR: INTERRCLR5 Position */
+#define GPDMA_INTERRCLR_INTERRCLR5_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR5_Pos) /*!< GPDMA INTERRCLR: INTERRCLR5 Mask */
+#define GPDMA_INTERRCLR_INTERRCLR6_Pos 6 /*!< GPDMA INTERRCLR: INTERRCLR6 Position */
+#define GPDMA_INTERRCLR_INTERRCLR6_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR6_Pos) /*!< GPDMA INTERRCLR: INTERRCLR6 Mask */
+#define GPDMA_INTERRCLR_INTERRCLR7_Pos 7 /*!< GPDMA INTERRCLR: INTERRCLR7 Position */
+#define GPDMA_INTERRCLR_INTERRCLR7_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR7_Pos) /*!< GPDMA INTERRCLR: INTERRCLR7 Mask */
+
+// ----------------------------------- GPDMA_RAWINTTCSTAT ---------------------------------------
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos 0 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT0 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT0 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos 1 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT1 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT1 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos 2 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT2 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT2 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos 3 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT3 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT3 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos 4 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT4 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT4 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos 5 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT5 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT5 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos 6 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT6 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT6 Mask */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos 7 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT7 Position */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT7 Mask */
+
+// ----------------------------------- GPDMA_RAWINTERRSTAT --------------------------------------
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos 0 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT0 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT0 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos 1 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT1 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT1 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos 2 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT2 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT2 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos 3 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT3 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT3 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos 4 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT4 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT4 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos 5 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT5 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT5 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos 6 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT6 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT6 Mask */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos 7 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT7 Position */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT7 Mask */
+
+// ------------------------------------- GPDMA_ENBLDCHNS ----------------------------------------
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos 0 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS0 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS0 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos 1 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS1 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS1 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos 2 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS2 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS2 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos 3 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS3 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS3 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos 4 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS4 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS4 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos 5 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS5 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS5 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos 6 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS6 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS6 Mask */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos 7 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS7 Position */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS7 Mask */
+
+// ------------------------------------- GPDMA_SOFTBREQ -----------------------------------------
+#define GPDMA_SOFTBREQ_SOFTBREQ0_Pos 0 /*!< GPDMA SOFTBREQ: SOFTBREQ0 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ0_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ0_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ0 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ1_Pos 1 /*!< GPDMA SOFTBREQ: SOFTBREQ1 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ1_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ1_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ1 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ2_Pos 2 /*!< GPDMA SOFTBREQ: SOFTBREQ2 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ2_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ2_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ2 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ3_Pos 3 /*!< GPDMA SOFTBREQ: SOFTBREQ3 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ3_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ3_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ3 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ4_Pos 4 /*!< GPDMA SOFTBREQ: SOFTBREQ4 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ4_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ4_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ4 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ5_Pos 5 /*!< GPDMA SOFTBREQ: SOFTBREQ5 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ5_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ5_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ5 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ6_Pos 6 /*!< GPDMA SOFTBREQ: SOFTBREQ6 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ6_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ6_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ6 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ7_Pos 7 /*!< GPDMA SOFTBREQ: SOFTBREQ7 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ7_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ7_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ7 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ8_Pos 8 /*!< GPDMA SOFTBREQ: SOFTBREQ8 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ8_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ8_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ8 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ9_Pos 9 /*!< GPDMA SOFTBREQ: SOFTBREQ9 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ9_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ9_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ9 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ10_Pos 10 /*!< GPDMA SOFTBREQ: SOFTBREQ10 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ10_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ10_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ10 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ11_Pos 11 /*!< GPDMA SOFTBREQ: SOFTBREQ11 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ11_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ11_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ11 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ12_Pos 12 /*!< GPDMA SOFTBREQ: SOFTBREQ12 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ12_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ12_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ12 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ13_Pos 13 /*!< GPDMA SOFTBREQ: SOFTBREQ13 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ13_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ13_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ13 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ14_Pos 14 /*!< GPDMA SOFTBREQ: SOFTBREQ14 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ14_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ14_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ14 Mask */
+#define GPDMA_SOFTBREQ_SOFTBREQ15_Pos 15 /*!< GPDMA SOFTBREQ: SOFTBREQ15 Position */
+#define GPDMA_SOFTBREQ_SOFTBREQ15_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ15_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ15 Mask */
+
+// ------------------------------------- GPDMA_SOFTSREQ -----------------------------------------
+#define GPDMA_SOFTSREQ_SOFTSREQ0_Pos 0 /*!< GPDMA SOFTSREQ: SOFTSREQ0 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ0_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ0_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ0 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ1_Pos 1 /*!< GPDMA SOFTSREQ: SOFTSREQ1 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ1_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ1_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ1 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ2_Pos 2 /*!< GPDMA SOFTSREQ: SOFTSREQ2 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ2_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ2_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ2 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ3_Pos 3 /*!< GPDMA SOFTSREQ: SOFTSREQ3 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ3_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ3_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ3 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ4_Pos 4 /*!< GPDMA SOFTSREQ: SOFTSREQ4 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ4_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ4_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ4 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ5_Pos 5 /*!< GPDMA SOFTSREQ: SOFTSREQ5 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ5_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ5_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ5 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ6_Pos 6 /*!< GPDMA SOFTSREQ: SOFTSREQ6 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ6_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ6_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ6 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ7_Pos 7 /*!< GPDMA SOFTSREQ: SOFTSREQ7 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ7_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ7_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ7 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ8_Pos 8 /*!< GPDMA SOFTSREQ: SOFTSREQ8 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ8_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ8_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ8 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ9_Pos 9 /*!< GPDMA SOFTSREQ: SOFTSREQ9 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ9_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ9_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ9 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ10_Pos 10 /*!< GPDMA SOFTSREQ: SOFTSREQ10 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ10_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ10_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ10 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ11_Pos 11 /*!< GPDMA SOFTSREQ: SOFTSREQ11 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ11_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ11_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ11 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ12_Pos 12 /*!< GPDMA SOFTSREQ: SOFTSREQ12 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ12_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ12_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ12 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ13_Pos 13 /*!< GPDMA SOFTSREQ: SOFTSREQ13 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ13_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ13_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ13 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ14_Pos 14 /*!< GPDMA SOFTSREQ: SOFTSREQ14 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ14_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ14_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ14 Mask */
+#define GPDMA_SOFTSREQ_SOFTSREQ15_Pos 15 /*!< GPDMA SOFTSREQ: SOFTSREQ15 Position */
+#define GPDMA_SOFTSREQ_SOFTSREQ15_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ15_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ15 Mask */
+
+// ------------------------------------- GPDMA_SOFTLBREQ ----------------------------------------
+#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos 0 /*!< GPDMA SOFTLBREQ: SOFTLBREQ0 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ0 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos 1 /*!< GPDMA SOFTLBREQ: SOFTLBREQ1 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ1 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos 2 /*!< GPDMA SOFTLBREQ: SOFTLBREQ2 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ2 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos 3 /*!< GPDMA SOFTLBREQ: SOFTLBREQ3 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ3 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos 4 /*!< GPDMA SOFTLBREQ: SOFTLBREQ4 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ4 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos 5 /*!< GPDMA SOFTLBREQ: SOFTLBREQ5 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ5 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos 6 /*!< GPDMA SOFTLBREQ: SOFTLBREQ6 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ6 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos 7 /*!< GPDMA SOFTLBREQ: SOFTLBREQ7 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ7 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos 8 /*!< GPDMA SOFTLBREQ: SOFTLBREQ8 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ8 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos 9 /*!< GPDMA SOFTLBREQ: SOFTLBREQ9 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ9 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos 10 /*!< GPDMA SOFTLBREQ: SOFTLBREQ10 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ10 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos 11 /*!< GPDMA SOFTLBREQ: SOFTLBREQ11 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ11 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos 12 /*!< GPDMA SOFTLBREQ: SOFTLBREQ12 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ12 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos 13 /*!< GPDMA SOFTLBREQ: SOFTLBREQ13 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ13 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos 14 /*!< GPDMA SOFTLBREQ: SOFTLBREQ14 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ14 Mask */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos 15 /*!< GPDMA SOFTLBREQ: SOFTLBREQ15 Position */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ15 Mask */
+
+// ------------------------------------- GPDMA_SOFTLSREQ ----------------------------------------
+#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos 0 /*!< GPDMA SOFTLSREQ: SOFTLSREQ0 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ0 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos 1 /*!< GPDMA SOFTLSREQ: SOFTLSREQ1 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ1 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos 2 /*!< GPDMA SOFTLSREQ: SOFTLSREQ2 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ2 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos 3 /*!< GPDMA SOFTLSREQ: SOFTLSREQ3 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ3 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos 4 /*!< GPDMA SOFTLSREQ: SOFTLSREQ4 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ4 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos 5 /*!< GPDMA SOFTLSREQ: SOFTLSREQ5 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ5 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos 6 /*!< GPDMA SOFTLSREQ: SOFTLSREQ6 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ6 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos 7 /*!< GPDMA SOFTLSREQ: SOFTLSREQ7 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ7 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos 8 /*!< GPDMA SOFTLSREQ: SOFTLSREQ8 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ8 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos 9 /*!< GPDMA SOFTLSREQ: SOFTLSREQ9 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ9 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos 10 /*!< GPDMA SOFTLSREQ: SOFTLSREQ10 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ10 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos 11 /*!< GPDMA SOFTLSREQ: SOFTLSREQ11 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ11 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos 12 /*!< GPDMA SOFTLSREQ: SOFTLSREQ12 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ12 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos 13 /*!< GPDMA SOFTLSREQ: SOFTLSREQ13 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ13 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos 14 /*!< GPDMA SOFTLSREQ: SOFTLSREQ14 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ14 Mask */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos 15 /*!< GPDMA SOFTLSREQ: SOFTLSREQ15 Position */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ15 Mask */
+
+// -------------------------------------- GPDMA_CONFIG ------------------------------------------
+#define GPDMA_CONFIG_E_Pos 0 /*!< GPDMA CONFIG: E Position */
+#define GPDMA_CONFIG_E_Msk (0x01UL << GPDMA_CONFIG_E_Pos) /*!< GPDMA CONFIG: E Mask */
+#define GPDMA_CONFIG_M0_Pos 1 /*!< GPDMA CONFIG: M0 Position */
+#define GPDMA_CONFIG_M0_Msk (0x01UL << GPDMA_CONFIG_M0_Pos) /*!< GPDMA CONFIG: M0 Mask */
+#define GPDMA_CONFIG_M1_Pos 2 /*!< GPDMA CONFIG: M1 Position */
+#define GPDMA_CONFIG_M1_Msk (0x01UL << GPDMA_CONFIG_M1_Pos) /*!< GPDMA CONFIG: M1 Mask */
+
+// --------------------------------------- GPDMA_SYNC -------------------------------------------
+#define GPDMA_SYNC_DMACSYNC0_Pos 0 /*!< GPDMA SYNC: DMACSYNC0 Position */
+#define GPDMA_SYNC_DMACSYNC0_Msk (0x01UL << GPDMA_SYNC_DMACSYNC0_Pos) /*!< GPDMA SYNC: DMACSYNC0 Mask */
+#define GPDMA_SYNC_DMACSYNC1_Pos 1 /*!< GPDMA SYNC: DMACSYNC1 Position */
+#define GPDMA_SYNC_DMACSYNC1_Msk (0x01UL << GPDMA_SYNC_DMACSYNC1_Pos) /*!< GPDMA SYNC: DMACSYNC1 Mask */
+#define GPDMA_SYNC_DMACSYNC2_Pos 2 /*!< GPDMA SYNC: DMACSYNC2 Position */
+#define GPDMA_SYNC_DMACSYNC2_Msk (0x01UL << GPDMA_SYNC_DMACSYNC2_Pos) /*!< GPDMA SYNC: DMACSYNC2 Mask */
+#define GPDMA_SYNC_DMACSYNC3_Pos 3 /*!< GPDMA SYNC: DMACSYNC3 Position */
+#define GPDMA_SYNC_DMACSYNC3_Msk (0x01UL << GPDMA_SYNC_DMACSYNC3_Pos) /*!< GPDMA SYNC: DMACSYNC3 Mask */
+#define GPDMA_SYNC_DMACSYNC4_Pos 4 /*!< GPDMA SYNC: DMACSYNC4 Position */
+#define GPDMA_SYNC_DMACSYNC4_Msk (0x01UL << GPDMA_SYNC_DMACSYNC4_Pos) /*!< GPDMA SYNC: DMACSYNC4 Mask */
+#define GPDMA_SYNC_DMACSYNC5_Pos 5 /*!< GPDMA SYNC: DMACSYNC5 Position */
+#define GPDMA_SYNC_DMACSYNC5_Msk (0x01UL << GPDMA_SYNC_DMACSYNC5_Pos) /*!< GPDMA SYNC: DMACSYNC5 Mask */
+#define GPDMA_SYNC_DMACSYNC6_Pos 6 /*!< GPDMA SYNC: DMACSYNC6 Position */
+#define GPDMA_SYNC_DMACSYNC6_Msk (0x01UL << GPDMA_SYNC_DMACSYNC6_Pos) /*!< GPDMA SYNC: DMACSYNC6 Mask */
+#define GPDMA_SYNC_DMACSYNC7_Pos 7 /*!< GPDMA SYNC: DMACSYNC7 Position */
+#define GPDMA_SYNC_DMACSYNC7_Msk (0x01UL << GPDMA_SYNC_DMACSYNC7_Pos) /*!< GPDMA SYNC: DMACSYNC7 Mask */
+#define GPDMA_SYNC_DMACSYNC8_Pos 8 /*!< GPDMA SYNC: DMACSYNC8 Position */
+#define GPDMA_SYNC_DMACSYNC8_Msk (0x01UL << GPDMA_SYNC_DMACSYNC8_Pos) /*!< GPDMA SYNC: DMACSYNC8 Mask */
+#define GPDMA_SYNC_DMACSYNC9_Pos 9 /*!< GPDMA SYNC: DMACSYNC9 Position */
+#define GPDMA_SYNC_DMACSYNC9_Msk (0x01UL << GPDMA_SYNC_DMACSYNC9_Pos) /*!< GPDMA SYNC: DMACSYNC9 Mask */
+#define GPDMA_SYNC_DMACSYNC10_Pos 10 /*!< GPDMA SYNC: DMACSYNC10 Position */
+#define GPDMA_SYNC_DMACSYNC10_Msk (0x01UL << GPDMA_SYNC_DMACSYNC10_Pos) /*!< GPDMA SYNC: DMACSYNC10 Mask */
+#define GPDMA_SYNC_DMACSYNC11_Pos 11 /*!< GPDMA SYNC: DMACSYNC11 Position */
+#define GPDMA_SYNC_DMACSYNC11_Msk (0x01UL << GPDMA_SYNC_DMACSYNC11_Pos) /*!< GPDMA SYNC: DMACSYNC11 Mask */
+#define GPDMA_SYNC_DMACSYNC12_Pos 12 /*!< GPDMA SYNC: DMACSYNC12 Position */
+#define GPDMA_SYNC_DMACSYNC12_Msk (0x01UL << GPDMA_SYNC_DMACSYNC12_Pos) /*!< GPDMA SYNC: DMACSYNC12 Mask */
+#define GPDMA_SYNC_DMACSYNC13_Pos 13 /*!< GPDMA SYNC: DMACSYNC13 Position */
+#define GPDMA_SYNC_DMACSYNC13_Msk (0x01UL << GPDMA_SYNC_DMACSYNC13_Pos) /*!< GPDMA SYNC: DMACSYNC13 Mask */
+#define GPDMA_SYNC_DMACSYNC14_Pos 14 /*!< GPDMA SYNC: DMACSYNC14 Position */
+#define GPDMA_SYNC_DMACSYNC14_Msk (0x01UL << GPDMA_SYNC_DMACSYNC14_Pos) /*!< GPDMA SYNC: DMACSYNC14 Mask */
+#define GPDMA_SYNC_DMACSYNC15_Pos 15 /*!< GPDMA SYNC: DMACSYNC15 Position */
+#define GPDMA_SYNC_DMACSYNC15_Msk (0x01UL << GPDMA_SYNC_DMACSYNC15_Pos) /*!< GPDMA SYNC: DMACSYNC15 Mask */
+
+// ------------------------------------- GPDMA_C0SRCADDR ----------------------------------------
+#define GPDMA_C0SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C0SRCADDR: SRCADDR Position */
+#define GPDMA_C0SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C0SRCADDR_SRCADDR_Pos) /*!< GPDMA C0SRCADDR: SRCADDR Mask */
+
+// ------------------------------------ GPDMA_C0DESTADDR ----------------------------------------
+#define GPDMA_C0DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C0DESTADDR: DESTADDR Position */
+#define GPDMA_C0DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C0DESTADDR_DESTADDR_Pos) /*!< GPDMA C0DESTADDR: DESTADDR Mask */
+
+// --------------------------------------- GPDMA_C0LLI ------------------------------------------
+#define GPDMA_C0LLI_LM_Pos 0 /*!< GPDMA C0LLI: LM Position */
+#define GPDMA_C0LLI_LM_Msk (0x01UL << GPDMA_C0LLI_LM_Pos) /*!< GPDMA C0LLI: LM Mask */
+#define GPDMA_C0LLI_R_Pos 1 /*!< GPDMA C0LLI: R Position */
+#define GPDMA_C0LLI_R_Msk (0x01UL << GPDMA_C0LLI_R_Pos) /*!< GPDMA C0LLI: R Mask */
+#define GPDMA_C0LLI_LLI_Pos 2 /*!< GPDMA C0LLI: LLI Position */
+#define GPDMA_C0LLI_LLI_Msk (0x3fffffffUL << GPDMA_C0LLI_LLI_Pos) /*!< GPDMA C0LLI: LLI Mask */
+
+// ------------------------------------- GPDMA_C0CONTROL ----------------------------------------
+#define GPDMA_C0CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C0CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C0CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C0CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C0CONTROL: TRANSFERSIZE Mask */
+#define GPDMA_C0CONTROL_SBSIZE_Pos 12 /*!< GPDMA C0CONTROL: SBSIZE Position */
+#define GPDMA_C0CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C0CONTROL_SBSIZE_Pos) /*!< GPDMA C0CONTROL: SBSIZE Mask */
+#define GPDMA_C0CONTROL_DBSIZE_Pos 15 /*!< GPDMA C0CONTROL: DBSIZE Position */
+#define GPDMA_C0CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C0CONTROL_DBSIZE_Pos) /*!< GPDMA C0CONTROL: DBSIZE Mask */
+#define GPDMA_C0CONTROL_SWIDTH_Pos 18 /*!< GPDMA C0CONTROL: SWIDTH Position */
+#define GPDMA_C0CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C0CONTROL_SWIDTH_Pos) /*!< GPDMA C0CONTROL: SWIDTH Mask */
+#define GPDMA_C0CONTROL_DWIDTH_Pos 21 /*!< GPDMA C0CONTROL: DWIDTH Position */
+#define GPDMA_C0CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C0CONTROL_DWIDTH_Pos) /*!< GPDMA C0CONTROL: DWIDTH Mask */
+#define GPDMA_C0CONTROL_S_Pos 24 /*!< GPDMA C0CONTROL: S Position */
+#define GPDMA_C0CONTROL_S_Msk (0x01UL << GPDMA_C0CONTROL_S_Pos) /*!< GPDMA C0CONTROL: S Mask */
+#define GPDMA_C0CONTROL_D_Pos 25 /*!< GPDMA C0CONTROL: D Position */
+#define GPDMA_C0CONTROL_D_Msk (0x01UL << GPDMA_C0CONTROL_D_Pos) /*!< GPDMA C0CONTROL: D Mask */
+#define GPDMA_C0CONTROL_SI_Pos 26 /*!< GPDMA C0CONTROL: SI Position */
+#define GPDMA_C0CONTROL_SI_Msk (0x01UL << GPDMA_C0CONTROL_SI_Pos) /*!< GPDMA C0CONTROL: SI Mask */
+#define GPDMA_C0CONTROL_DI_Pos 27 /*!< GPDMA C0CONTROL: DI Position */
+#define GPDMA_C0CONTROL_DI_Msk (0x01UL << GPDMA_C0CONTROL_DI_Pos) /*!< GPDMA C0CONTROL: DI Mask */
+#define GPDMA_C0CONTROL_PROT1_Pos 28 /*!< GPDMA C0CONTROL: PROT1 Position */
+#define GPDMA_C0CONTROL_PROT1_Msk (0x01UL << GPDMA_C0CONTROL_PROT1_Pos) /*!< GPDMA C0CONTROL: PROT1 Mask */
+#define GPDMA_C0CONTROL_PROT2_Pos 29 /*!< GPDMA C0CONTROL: PROT2 Position */
+#define GPDMA_C0CONTROL_PROT2_Msk (0x01UL << GPDMA_C0CONTROL_PROT2_Pos) /*!< GPDMA C0CONTROL: PROT2 Mask */
+#define GPDMA_C0CONTROL_PROT3_Pos 30 /*!< GPDMA C0CONTROL: PROT3 Position */
+#define GPDMA_C0CONTROL_PROT3_Msk (0x01UL << GPDMA_C0CONTROL_PROT3_Pos) /*!< GPDMA C0CONTROL: PROT3 Mask */
+#define GPDMA_C0CONTROL_I_Pos 31 /*!< GPDMA C0CONTROL: I Position */
+#define GPDMA_C0CONTROL_I_Msk (0x01UL << GPDMA_C0CONTROL_I_Pos) /*!< GPDMA C0CONTROL: I Mask */
+
+// ------------------------------------- GPDMA_C0CONFIG -----------------------------------------
+#define GPDMA_C0CONFIG_E_Pos 0 /*!< GPDMA C0CONFIG: E Position */
+#define GPDMA_C0CONFIG_E_Msk (0x01UL << GPDMA_C0CONFIG_E_Pos) /*!< GPDMA C0CONFIG: E Mask */
+#define GPDMA_C0CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C0CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C0CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C0CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C0CONFIG: SRCPERIPHERAL Mask */
+#define GPDMA_C0CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C0CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C0CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C0CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C0CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C0CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C0CONFIG: FLOWCNTRL Position */
+#define GPDMA_C0CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C0CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C0CONFIG: FLOWCNTRL Mask */
+#define GPDMA_C0CONFIG_IE_Pos 14 /*!< GPDMA C0CONFIG: IE Position */
+#define GPDMA_C0CONFIG_IE_Msk (0x01UL << GPDMA_C0CONFIG_IE_Pos) /*!< GPDMA C0CONFIG: IE Mask */
+#define GPDMA_C0CONFIG_ITC_Pos 15 /*!< GPDMA C0CONFIG: ITC Position */
+#define GPDMA_C0CONFIG_ITC_Msk (0x01UL << GPDMA_C0CONFIG_ITC_Pos) /*!< GPDMA C0CONFIG: ITC Mask */
+#define GPDMA_C0CONFIG_L_Pos 16 /*!< GPDMA C0CONFIG: L Position */
+#define GPDMA_C0CONFIG_L_Msk (0x01UL << GPDMA_C0CONFIG_L_Pos) /*!< GPDMA C0CONFIG: L Mask */
+#define GPDMA_C0CONFIG_A_Pos 17 /*!< GPDMA C0CONFIG: A Position */
+#define GPDMA_C0CONFIG_A_Msk (0x01UL << GPDMA_C0CONFIG_A_Pos) /*!< GPDMA C0CONFIG: A Mask */
+#define GPDMA_C0CONFIG_H_Pos 18 /*!< GPDMA C0CONFIG: H Position */
+#define GPDMA_C0CONFIG_H_Msk (0x01UL << GPDMA_C0CONFIG_H_Pos) /*!< GPDMA C0CONFIG: H Mask */
+
+// ------------------------------------- GPDMA_C1SRCADDR ----------------------------------------
+#define GPDMA_C1SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C1SRCADDR: SRCADDR Position */
+#define GPDMA_C1SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C1SRCADDR_SRCADDR_Pos) /*!< GPDMA C1SRCADDR: SRCADDR Mask */
+
+// ------------------------------------ GPDMA_C1DESTADDR ----------------------------------------
+#define GPDMA_C1DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C1DESTADDR: DESTADDR Position */
+#define GPDMA_C1DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C1DESTADDR_DESTADDR_Pos) /*!< GPDMA C1DESTADDR: DESTADDR Mask */
+
+// --------------------------------------- GPDMA_C1LLI ------------------------------------------
+#define GPDMA_C1LLI_LM_Pos 0 /*!< GPDMA C1LLI: LM Position */
+#define GPDMA_C1LLI_LM_Msk (0x01UL << GPDMA_C1LLI_LM_Pos) /*!< GPDMA C1LLI: LM Mask */
+#define GPDMA_C1LLI_R_Pos 1 /*!< GPDMA C1LLI: R Position */
+#define GPDMA_C1LLI_R_Msk (0x01UL << GPDMA_C1LLI_R_Pos) /*!< GPDMA C1LLI: R Mask */
+#define GPDMA_C1LLI_LLI_Pos 2 /*!< GPDMA C1LLI: LLI Position */
+#define GPDMA_C1LLI_LLI_Msk (0x3fffffffUL << GPDMA_C1LLI_LLI_Pos) /*!< GPDMA C1LLI: LLI Mask */
+
+// ------------------------------------- GPDMA_C1CONTROL ----------------------------------------
+#define GPDMA_C1CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C1CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C1CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C1CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C1CONTROL: TRANSFERSIZE Mask */
+#define GPDMA_C1CONTROL_SBSIZE_Pos 12 /*!< GPDMA C1CONTROL: SBSIZE Position */
+#define GPDMA_C1CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C1CONTROL_SBSIZE_Pos) /*!< GPDMA C1CONTROL: SBSIZE Mask */
+#define GPDMA_C1CONTROL_DBSIZE_Pos 15 /*!< GPDMA C1CONTROL: DBSIZE Position */
+#define GPDMA_C1CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C1CONTROL_DBSIZE_Pos) /*!< GPDMA C1CONTROL: DBSIZE Mask */
+#define GPDMA_C1CONTROL_SWIDTH_Pos 18 /*!< GPDMA C1CONTROL: SWIDTH Position */
+#define GPDMA_C1CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C1CONTROL_SWIDTH_Pos) /*!< GPDMA C1CONTROL: SWIDTH Mask */
+#define GPDMA_C1CONTROL_DWIDTH_Pos 21 /*!< GPDMA C1CONTROL: DWIDTH Position */
+#define GPDMA_C1CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C1CONTROL_DWIDTH_Pos) /*!< GPDMA C1CONTROL: DWIDTH Mask */
+#define GPDMA_C1CONTROL_S_Pos 24 /*!< GPDMA C1CONTROL: S Position */
+#define GPDMA_C1CONTROL_S_Msk (0x01UL << GPDMA_C1CONTROL_S_Pos) /*!< GPDMA C1CONTROL: S Mask */
+#define GPDMA_C1CONTROL_D_Pos 25 /*!< GPDMA C1CONTROL: D Position */
+#define GPDMA_C1CONTROL_D_Msk (0x01UL << GPDMA_C1CONTROL_D_Pos) /*!< GPDMA C1CONTROL: D Mask */
+#define GPDMA_C1CONTROL_SI_Pos 26 /*!< GPDMA C1CONTROL: SI Position */
+#define GPDMA_C1CONTROL_SI_Msk (0x01UL << GPDMA_C1CONTROL_SI_Pos) /*!< GPDMA C1CONTROL: SI Mask */
+#define GPDMA_C1CONTROL_DI_Pos 27 /*!< GPDMA C1CONTROL: DI Position */
+#define GPDMA_C1CONTROL_DI_Msk (0x01UL << GPDMA_C1CONTROL_DI_Pos) /*!< GPDMA C1CONTROL: DI Mask */
+#define GPDMA_C1CONTROL_PROT1_Pos 28 /*!< GPDMA C1CONTROL: PROT1 Position */
+#define GPDMA_C1CONTROL_PROT1_Msk (0x01UL << GPDMA_C1CONTROL_PROT1_Pos) /*!< GPDMA C1CONTROL: PROT1 Mask */
+#define GPDMA_C1CONTROL_PROT2_Pos 29 /*!< GPDMA C1CONTROL: PROT2 Position */
+#define GPDMA_C1CONTROL_PROT2_Msk (0x01UL << GPDMA_C1CONTROL_PROT2_Pos) /*!< GPDMA C1CONTROL: PROT2 Mask */
+#define GPDMA_C1CONTROL_PROT3_Pos 30 /*!< GPDMA C1CONTROL: PROT3 Position */
+#define GPDMA_C1CONTROL_PROT3_Msk (0x01UL << GPDMA_C1CONTROL_PROT3_Pos) /*!< GPDMA C1CONTROL: PROT3 Mask */
+#define GPDMA_C1CONTROL_I_Pos 31 /*!< GPDMA C1CONTROL: I Position */
+#define GPDMA_C1CONTROL_I_Msk (0x01UL << GPDMA_C1CONTROL_I_Pos) /*!< GPDMA C1CONTROL: I Mask */
+
+// ------------------------------------- GPDMA_C1CONFIG -----------------------------------------
+#define GPDMA_C1CONFIG_E_Pos 0 /*!< GPDMA C1CONFIG: E Position */
+#define GPDMA_C1CONFIG_E_Msk (0x01UL << GPDMA_C1CONFIG_E_Pos) /*!< GPDMA C1CONFIG: E Mask */
+#define GPDMA_C1CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C1CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C1CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C1CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C1CONFIG: SRCPERIPHERAL Mask */
+#define GPDMA_C1CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C1CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C1CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C1CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C1CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C1CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C1CONFIG: FLOWCNTRL Position */
+#define GPDMA_C1CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C1CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C1CONFIG: FLOWCNTRL Mask */
+#define GPDMA_C1CONFIG_IE_Pos 14 /*!< GPDMA C1CONFIG: IE Position */
+#define GPDMA_C1CONFIG_IE_Msk (0x01UL << GPDMA_C1CONFIG_IE_Pos) /*!< GPDMA C1CONFIG: IE Mask */
+#define GPDMA_C1CONFIG_ITC_Pos 15 /*!< GPDMA C1CONFIG: ITC Position */
+#define GPDMA_C1CONFIG_ITC_Msk (0x01UL << GPDMA_C1CONFIG_ITC_Pos) /*!< GPDMA C1CONFIG: ITC Mask */
+#define GPDMA_C1CONFIG_L_Pos 16 /*!< GPDMA C1CONFIG: L Position */
+#define GPDMA_C1CONFIG_L_Msk (0x01UL << GPDMA_C1CONFIG_L_Pos) /*!< GPDMA C1CONFIG: L Mask */
+#define GPDMA_C1CONFIG_A_Pos 17 /*!< GPDMA C1CONFIG: A Position */
+#define GPDMA_C1CONFIG_A_Msk (0x01UL << GPDMA_C1CONFIG_A_Pos) /*!< GPDMA C1CONFIG: A Mask */
+#define GPDMA_C1CONFIG_H_Pos 18 /*!< GPDMA C1CONFIG: H Position */
+#define GPDMA_C1CONFIG_H_Msk (0x01UL << GPDMA_C1CONFIG_H_Pos) /*!< GPDMA C1CONFIG: H Mask */
+
+// ------------------------------------- GPDMA_C2SRCADDR ----------------------------------------
+#define GPDMA_C2SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C2SRCADDR: SRCADDR Position */
+#define GPDMA_C2SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C2SRCADDR_SRCADDR_Pos) /*!< GPDMA C2SRCADDR: SRCADDR Mask */
+
+// ------------------------------------ GPDMA_C2DESTADDR ----------------------------------------
+#define GPDMA_C2DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C2DESTADDR: DESTADDR Position */
+#define GPDMA_C2DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C2DESTADDR_DESTADDR_Pos) /*!< GPDMA C2DESTADDR: DESTADDR Mask */
+
+// --------------------------------------- GPDMA_C2LLI ------------------------------------------
+#define GPDMA_C2LLI_LM_Pos 0 /*!< GPDMA C2LLI: LM Position */
+#define GPDMA_C2LLI_LM_Msk (0x01UL << GPDMA_C2LLI_LM_Pos) /*!< GPDMA C2LLI: LM Mask */
+#define GPDMA_C2LLI_R_Pos 1 /*!< GPDMA C2LLI: R Position */
+#define GPDMA_C2LLI_R_Msk (0x01UL << GPDMA_C2LLI_R_Pos) /*!< GPDMA C2LLI: R Mask */
+#define GPDMA_C2LLI_LLI_Pos 2 /*!< GPDMA C2LLI: LLI Position */
+#define GPDMA_C2LLI_LLI_Msk (0x3fffffffUL << GPDMA_C2LLI_LLI_Pos) /*!< GPDMA C2LLI: LLI Mask */
+
+// ------------------------------------- GPDMA_C2CONTROL ----------------------------------------
+#define GPDMA_C2CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C2CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C2CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C2CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C2CONTROL: TRANSFERSIZE Mask */
+#define GPDMA_C2CONTROL_SBSIZE_Pos 12 /*!< GPDMA C2CONTROL: SBSIZE Position */
+#define GPDMA_C2CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C2CONTROL_SBSIZE_Pos) /*!< GPDMA C2CONTROL: SBSIZE Mask */
+#define GPDMA_C2CONTROL_DBSIZE_Pos 15 /*!< GPDMA C2CONTROL: DBSIZE Position */
+#define GPDMA_C2CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C2CONTROL_DBSIZE_Pos) /*!< GPDMA C2CONTROL: DBSIZE Mask */
+#define GPDMA_C2CONTROL_SWIDTH_Pos 18 /*!< GPDMA C2CONTROL: SWIDTH Position */
+#define GPDMA_C2CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C2CONTROL_SWIDTH_Pos) /*!< GPDMA C2CONTROL: SWIDTH Mask */
+#define GPDMA_C2CONTROL_DWIDTH_Pos 21 /*!< GPDMA C2CONTROL: DWIDTH Position */
+#define GPDMA_C2CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C2CONTROL_DWIDTH_Pos) /*!< GPDMA C2CONTROL: DWIDTH Mask */
+#define GPDMA_C2CONTROL_S_Pos 24 /*!< GPDMA C2CONTROL: S Position */
+#define GPDMA_C2CONTROL_S_Msk (0x01UL << GPDMA_C2CONTROL_S_Pos) /*!< GPDMA C2CONTROL: S Mask */
+#define GPDMA_C2CONTROL_D_Pos 25 /*!< GPDMA C2CONTROL: D Position */
+#define GPDMA_C2CONTROL_D_Msk (0x01UL << GPDMA_C2CONTROL_D_Pos) /*!< GPDMA C2CONTROL: D Mask */
+#define GPDMA_C2CONTROL_SI_Pos 26 /*!< GPDMA C2CONTROL: SI Position */
+#define GPDMA_C2CONTROL_SI_Msk (0x01UL << GPDMA_C2CONTROL_SI_Pos) /*!< GPDMA C2CONTROL: SI Mask */
+#define GPDMA_C2CONTROL_DI_Pos 27 /*!< GPDMA C2CONTROL: DI Position */
+#define GPDMA_C2CONTROL_DI_Msk (0x01UL << GPDMA_C2CONTROL_DI_Pos) /*!< GPDMA C2CONTROL: DI Mask */
+#define GPDMA_C2CONTROL_PROT1_Pos 28 /*!< GPDMA C2CONTROL: PROT1 Position */
+#define GPDMA_C2CONTROL_PROT1_Msk (0x01UL << GPDMA_C2CONTROL_PROT1_Pos) /*!< GPDMA C2CONTROL: PROT1 Mask */
+#define GPDMA_C2CONTROL_PROT2_Pos 29 /*!< GPDMA C2CONTROL: PROT2 Position */
+#define GPDMA_C2CONTROL_PROT2_Msk (0x01UL << GPDMA_C2CONTROL_PROT2_Pos) /*!< GPDMA C2CONTROL: PROT2 Mask */
+#define GPDMA_C2CONTROL_PROT3_Pos 30 /*!< GPDMA C2CONTROL: PROT3 Position */
+#define GPDMA_C2CONTROL_PROT3_Msk (0x01UL << GPDMA_C2CONTROL_PROT3_Pos) /*!< GPDMA C2CONTROL: PROT3 Mask */
+#define GPDMA_C2CONTROL_I_Pos 31 /*!< GPDMA C2CONTROL: I Position */
+#define GPDMA_C2CONTROL_I_Msk (0x01UL << GPDMA_C2CONTROL_I_Pos) /*!< GPDMA C2CONTROL: I Mask */
+
+// ------------------------------------- GPDMA_C2CONFIG -----------------------------------------
+#define GPDMA_C2CONFIG_E_Pos 0 /*!< GPDMA C2CONFIG: E Position */
+#define GPDMA_C2CONFIG_E_Msk (0x01UL << GPDMA_C2CONFIG_E_Pos) /*!< GPDMA C2CONFIG: E Mask */
+#define GPDMA_C2CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C2CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C2CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C2CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C2CONFIG: SRCPERIPHERAL Mask */
+#define GPDMA_C2CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C2CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C2CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C2CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C2CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C2CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C2CONFIG: FLOWCNTRL Position */
+#define GPDMA_C2CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C2CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C2CONFIG: FLOWCNTRL Mask */
+#define GPDMA_C2CONFIG_IE_Pos 14 /*!< GPDMA C2CONFIG: IE Position */
+#define GPDMA_C2CONFIG_IE_Msk (0x01UL << GPDMA_C2CONFIG_IE_Pos) /*!< GPDMA C2CONFIG: IE Mask */
+#define GPDMA_C2CONFIG_ITC_Pos 15 /*!< GPDMA C2CONFIG: ITC Position */
+#define GPDMA_C2CONFIG_ITC_Msk (0x01UL << GPDMA_C2CONFIG_ITC_Pos) /*!< GPDMA C2CONFIG: ITC Mask */
+#define GPDMA_C2CONFIG_L_Pos 16 /*!< GPDMA C2CONFIG: L Position */
+#define GPDMA_C2CONFIG_L_Msk (0x01UL << GPDMA_C2CONFIG_L_Pos) /*!< GPDMA C2CONFIG: L Mask */
+#define GPDMA_C2CONFIG_A_Pos 17 /*!< GPDMA C2CONFIG: A Position */
+#define GPDMA_C2CONFIG_A_Msk (0x01UL << GPDMA_C2CONFIG_A_Pos) /*!< GPDMA C2CONFIG: A Mask */
+#define GPDMA_C2CONFIG_H_Pos 18 /*!< GPDMA C2CONFIG: H Position */
+#define GPDMA_C2CONFIG_H_Msk (0x01UL << GPDMA_C2CONFIG_H_Pos) /*!< GPDMA C2CONFIG: H Mask */
+
+// ------------------------------------- GPDMA_C3SRCADDR ----------------------------------------
+#define GPDMA_C3SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C3SRCADDR: SRCADDR Position */
+#define GPDMA_C3SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C3SRCADDR_SRCADDR_Pos) /*!< GPDMA C3SRCADDR: SRCADDR Mask */
+
+// ------------------------------------ GPDMA_C3DESTADDR ----------------------------------------
+#define GPDMA_C3DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C3DESTADDR: DESTADDR Position */
+#define GPDMA_C3DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C3DESTADDR_DESTADDR_Pos) /*!< GPDMA C3DESTADDR: DESTADDR Mask */
+
+// --------------------------------------- GPDMA_C3LLI ------------------------------------------
+#define GPDMA_C3LLI_LM_Pos 0 /*!< GPDMA C3LLI: LM Position */
+#define GPDMA_C3LLI_LM_Msk (0x01UL << GPDMA_C3LLI_LM_Pos) /*!< GPDMA C3LLI: LM Mask */
+#define GPDMA_C3LLI_R_Pos 1 /*!< GPDMA C3LLI: R Position */
+#define GPDMA_C3LLI_R_Msk (0x01UL << GPDMA_C3LLI_R_Pos) /*!< GPDMA C3LLI: R Mask */
+#define GPDMA_C3LLI_LLI_Pos 2 /*!< GPDMA C3LLI: LLI Position */
+#define GPDMA_C3LLI_LLI_Msk (0x3fffffffUL << GPDMA_C3LLI_LLI_Pos) /*!< GPDMA C3LLI: LLI Mask */
+
+// ------------------------------------- GPDMA_C3CONTROL ----------------------------------------
+#define GPDMA_C3CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C3CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C3CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C3CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C3CONTROL: TRANSFERSIZE Mask */
+#define GPDMA_C3CONTROL_SBSIZE_Pos 12 /*!< GPDMA C3CONTROL: SBSIZE Position */
+#define GPDMA_C3CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C3CONTROL_SBSIZE_Pos) /*!< GPDMA C3CONTROL: SBSIZE Mask */
+#define GPDMA_C3CONTROL_DBSIZE_Pos 15 /*!< GPDMA C3CONTROL: DBSIZE Position */
+#define GPDMA_C3CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C3CONTROL_DBSIZE_Pos) /*!< GPDMA C3CONTROL: DBSIZE Mask */
+#define GPDMA_C3CONTROL_SWIDTH_Pos 18 /*!< GPDMA C3CONTROL: SWIDTH Position */
+#define GPDMA_C3CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C3CONTROL_SWIDTH_Pos) /*!< GPDMA C3CONTROL: SWIDTH Mask */
+#define GPDMA_C3CONTROL_DWIDTH_Pos 21 /*!< GPDMA C3CONTROL: DWIDTH Position */
+#define GPDMA_C3CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C3CONTROL_DWIDTH_Pos) /*!< GPDMA C3CONTROL: DWIDTH Mask */
+#define GPDMA_C3CONTROL_S_Pos 24 /*!< GPDMA C3CONTROL: S Position */
+#define GPDMA_C3CONTROL_S_Msk (0x01UL << GPDMA_C3CONTROL_S_Pos) /*!< GPDMA C3CONTROL: S Mask */
+#define GPDMA_C3CONTROL_D_Pos 25 /*!< GPDMA C3CONTROL: D Position */
+#define GPDMA_C3CONTROL_D_Msk (0x01UL << GPDMA_C3CONTROL_D_Pos) /*!< GPDMA C3CONTROL: D Mask */
+#define GPDMA_C3CONTROL_SI_Pos 26 /*!< GPDMA C3CONTROL: SI Position */
+#define GPDMA_C3CONTROL_SI_Msk (0x01UL << GPDMA_C3CONTROL_SI_Pos) /*!< GPDMA C3CONTROL: SI Mask */
+#define GPDMA_C3CONTROL_DI_Pos 27 /*!< GPDMA C3CONTROL: DI Position */
+#define GPDMA_C3CONTROL_DI_Msk (0x01UL << GPDMA_C3CONTROL_DI_Pos) /*!< GPDMA C3CONTROL: DI Mask */
+#define GPDMA_C3CONTROL_PROT1_Pos 28 /*!< GPDMA C3CONTROL: PROT1 Position */
+#define GPDMA_C3CONTROL_PROT1_Msk (0x01UL << GPDMA_C3CONTROL_PROT1_Pos) /*!< GPDMA C3CONTROL: PROT1 Mask */
+#define GPDMA_C3CONTROL_PROT2_Pos 29 /*!< GPDMA C3CONTROL: PROT2 Position */
+#define GPDMA_C3CONTROL_PROT2_Msk (0x01UL << GPDMA_C3CONTROL_PROT2_Pos) /*!< GPDMA C3CONTROL: PROT2 Mask */
+#define GPDMA_C3CONTROL_PROT3_Pos 30 /*!< GPDMA C3CONTROL: PROT3 Position */
+#define GPDMA_C3CONTROL_PROT3_Msk (0x01UL << GPDMA_C3CONTROL_PROT3_Pos) /*!< GPDMA C3CONTROL: PROT3 Mask */
+#define GPDMA_C3CONTROL_I_Pos 31 /*!< GPDMA C3CONTROL: I Position */
+#define GPDMA_C3CONTROL_I_Msk (0x01UL << GPDMA_C3CONTROL_I_Pos) /*!< GPDMA C3CONTROL: I Mask */
+
+// ------------------------------------- GPDMA_C3CONFIG -----------------------------------------
+#define GPDMA_C3CONFIG_E_Pos 0 /*!< GPDMA C3CONFIG: E Position */
+#define GPDMA_C3CONFIG_E_Msk (0x01UL << GPDMA_C3CONFIG_E_Pos) /*!< GPDMA C3CONFIG: E Mask */
+#define GPDMA_C3CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C3CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C3CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C3CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C3CONFIG: SRCPERIPHERAL Mask */
+#define GPDMA_C3CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C3CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C3CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C3CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C3CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C3CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C3CONFIG: FLOWCNTRL Position */
+#define GPDMA_C3CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C3CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C3CONFIG: FLOWCNTRL Mask */
+#define GPDMA_C3CONFIG_IE_Pos 14 /*!< GPDMA C3CONFIG: IE Position */
+#define GPDMA_C3CONFIG_IE_Msk (0x01UL << GPDMA_C3CONFIG_IE_Pos) /*!< GPDMA C3CONFIG: IE Mask */
+#define GPDMA_C3CONFIG_ITC_Pos 15 /*!< GPDMA C3CONFIG: ITC Position */
+#define GPDMA_C3CONFIG_ITC_Msk (0x01UL << GPDMA_C3CONFIG_ITC_Pos) /*!< GPDMA C3CONFIG: ITC Mask */
+#define GPDMA_C3CONFIG_L_Pos 16 /*!< GPDMA C3CONFIG: L Position */
+#define GPDMA_C3CONFIG_L_Msk (0x01UL << GPDMA_C3CONFIG_L_Pos) /*!< GPDMA C3CONFIG: L Mask */
+#define GPDMA_C3CONFIG_A_Pos 17 /*!< GPDMA C3CONFIG: A Position */
+#define GPDMA_C3CONFIG_A_Msk (0x01UL << GPDMA_C3CONFIG_A_Pos) /*!< GPDMA C3CONFIG: A Mask */
+#define GPDMA_C3CONFIG_H_Pos 18 /*!< GPDMA C3CONFIG: H Position */
+#define GPDMA_C3CONFIG_H_Msk (0x01UL << GPDMA_C3CONFIG_H_Pos) /*!< GPDMA C3CONFIG: H Mask */
+
+// ------------------------------------- GPDMA_C4SRCADDR ----------------------------------------
+#define GPDMA_C4SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C4SRCADDR: SRCADDR Position */
+#define GPDMA_C4SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C4SRCADDR_SRCADDR_Pos) /*!< GPDMA C4SRCADDR: SRCADDR Mask */
+
+// ------------------------------------ GPDMA_C4DESTADDR ----------------------------------------
+#define GPDMA_C4DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C4DESTADDR: DESTADDR Position */
+#define GPDMA_C4DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C4DESTADDR_DESTADDR_Pos) /*!< GPDMA C4DESTADDR: DESTADDR Mask */
+
+// --------------------------------------- GPDMA_C4LLI ------------------------------------------
+#define GPDMA_C4LLI_LM_Pos 0 /*!< GPDMA C4LLI: LM Position */
+#define GPDMA_C4LLI_LM_Msk (0x01UL << GPDMA_C4LLI_LM_Pos) /*!< GPDMA C4LLI: LM Mask */
+#define GPDMA_C4LLI_R_Pos 1 /*!< GPDMA C4LLI: R Position */
+#define GPDMA_C4LLI_R_Msk (0x01UL << GPDMA_C4LLI_R_Pos) /*!< GPDMA C4LLI: R Mask */
+#define GPDMA_C4LLI_LLI_Pos 2 /*!< GPDMA C4LLI: LLI Position */
+#define GPDMA_C4LLI_LLI_Msk (0x3fffffffUL << GPDMA_C4LLI_LLI_Pos) /*!< GPDMA C4LLI: LLI Mask */
+
+// ------------------------------------- GPDMA_C4CONTROL ----------------------------------------
+#define GPDMA_C4CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C4CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C4CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C4CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C4CONTROL: TRANSFERSIZE Mask */
+#define GPDMA_C4CONTROL_SBSIZE_Pos 12 /*!< GPDMA C4CONTROL: SBSIZE Position */
+#define GPDMA_C4CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C4CONTROL_SBSIZE_Pos) /*!< GPDMA C4CONTROL: SBSIZE Mask */
+#define GPDMA_C4CONTROL_DBSIZE_Pos 15 /*!< GPDMA C4CONTROL: DBSIZE Position */
+#define GPDMA_C4CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C4CONTROL_DBSIZE_Pos) /*!< GPDMA C4CONTROL: DBSIZE Mask */
+#define GPDMA_C4CONTROL_SWIDTH_Pos 18 /*!< GPDMA C4CONTROL: SWIDTH Position */
+#define GPDMA_C4CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C4CONTROL_SWIDTH_Pos) /*!< GPDMA C4CONTROL: SWIDTH Mask */
+#define GPDMA_C4CONTROL_DWIDTH_Pos 21 /*!< GPDMA C4CONTROL: DWIDTH Position */
+#define GPDMA_C4CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C4CONTROL_DWIDTH_Pos) /*!< GPDMA C4CONTROL: DWIDTH Mask */
+#define GPDMA_C4CONTROL_S_Pos 24 /*!< GPDMA C4CONTROL: S Position */
+#define GPDMA_C4CONTROL_S_Msk (0x01UL << GPDMA_C4CONTROL_S_Pos) /*!< GPDMA C4CONTROL: S Mask */
+#define GPDMA_C4CONTROL_D_Pos 25 /*!< GPDMA C4CONTROL: D Position */
+#define GPDMA_C4CONTROL_D_Msk (0x01UL << GPDMA_C4CONTROL_D_Pos) /*!< GPDMA C4CONTROL: D Mask */
+#define GPDMA_C4CONTROL_SI_Pos 26 /*!< GPDMA C4CONTROL: SI Position */
+#define GPDMA_C4CONTROL_SI_Msk (0x01UL << GPDMA_C4CONTROL_SI_Pos) /*!< GPDMA C4CONTROL: SI Mask */
+#define GPDMA_C4CONTROL_DI_Pos 27 /*!< GPDMA C4CONTROL: DI Position */
+#define GPDMA_C4CONTROL_DI_Msk (0x01UL << GPDMA_C4CONTROL_DI_Pos) /*!< GPDMA C4CONTROL: DI Mask */
+#define GPDMA_C4CONTROL_PROT1_Pos 28 /*!< GPDMA C4CONTROL: PROT1 Position */
+#define GPDMA_C4CONTROL_PROT1_Msk (0x01UL << GPDMA_C4CONTROL_PROT1_Pos) /*!< GPDMA C4CONTROL: PROT1 Mask */
+#define GPDMA_C4CONTROL_PROT2_Pos 29 /*!< GPDMA C4CONTROL: PROT2 Position */
+#define GPDMA_C4CONTROL_PROT2_Msk (0x01UL << GPDMA_C4CONTROL_PROT2_Pos) /*!< GPDMA C4CONTROL: PROT2 Mask */
+#define GPDMA_C4CONTROL_PROT3_Pos 30 /*!< GPDMA C4CONTROL: PROT3 Position */
+#define GPDMA_C4CONTROL_PROT3_Msk (0x01UL << GPDMA_C4CONTROL_PROT3_Pos) /*!< GPDMA C4CONTROL: PROT3 Mask */
+#define GPDMA_C4CONTROL_I_Pos 31 /*!< GPDMA C4CONTROL: I Position */
+#define GPDMA_C4CONTROL_I_Msk (0x01UL << GPDMA_C4CONTROL_I_Pos) /*!< GPDMA C4CONTROL: I Mask */
+
+// ------------------------------------- GPDMA_C4CONFIG -----------------------------------------
+#define GPDMA_C4CONFIG_E_Pos 0 /*!< GPDMA C4CONFIG: E Position */
+#define GPDMA_C4CONFIG_E_Msk (0x01UL << GPDMA_C4CONFIG_E_Pos) /*!< GPDMA C4CONFIG: E Mask */
+#define GPDMA_C4CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C4CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C4CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C4CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C4CONFIG: SRCPERIPHERAL Mask */
+#define GPDMA_C4CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C4CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C4CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C4CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C4CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C4CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C4CONFIG: FLOWCNTRL Position */
+#define GPDMA_C4CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C4CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C4CONFIG: FLOWCNTRL Mask */
+#define GPDMA_C4CONFIG_IE_Pos 14 /*!< GPDMA C4CONFIG: IE Position */
+#define GPDMA_C4CONFIG_IE_Msk (0x01UL << GPDMA_C4CONFIG_IE_Pos) /*!< GPDMA C4CONFIG: IE Mask */
+#define GPDMA_C4CONFIG_ITC_Pos 15 /*!< GPDMA C4CONFIG: ITC Position */
+#define GPDMA_C4CONFIG_ITC_Msk (0x01UL << GPDMA_C4CONFIG_ITC_Pos) /*!< GPDMA C4CONFIG: ITC Mask */
+#define GPDMA_C4CONFIG_L_Pos 16 /*!< GPDMA C4CONFIG: L Position */
+#define GPDMA_C4CONFIG_L_Msk (0x01UL << GPDMA_C4CONFIG_L_Pos) /*!< GPDMA C4CONFIG: L Mask */
+#define GPDMA_C4CONFIG_A_Pos 17 /*!< GPDMA C4CONFIG: A Position */
+#define GPDMA_C4CONFIG_A_Msk (0x01UL << GPDMA_C4CONFIG_A_Pos) /*!< GPDMA C4CONFIG: A Mask */
+#define GPDMA_C4CONFIG_H_Pos 18 /*!< GPDMA C4CONFIG: H Position */
+#define GPDMA_C4CONFIG_H_Msk (0x01UL << GPDMA_C4CONFIG_H_Pos) /*!< GPDMA C4CONFIG: H Mask */
+
+// ------------------------------------- GPDMA_C5SRCADDR ----------------------------------------
+#define GPDMA_C5SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C5SRCADDR: SRCADDR Position */
+#define GPDMA_C5SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C5SRCADDR_SRCADDR_Pos) /*!< GPDMA C5SRCADDR: SRCADDR Mask */
+
+// ------------------------------------ GPDMA_C5DESTADDR ----------------------------------------
+#define GPDMA_C5DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C5DESTADDR: DESTADDR Position */
+#define GPDMA_C5DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C5DESTADDR_DESTADDR_Pos) /*!< GPDMA C5DESTADDR: DESTADDR Mask */
+
+// --------------------------------------- GPDMA_C5LLI ------------------------------------------
+#define GPDMA_C5LLI_LM_Pos 0 /*!< GPDMA C5LLI: LM Position */
+#define GPDMA_C5LLI_LM_Msk (0x01UL << GPDMA_C5LLI_LM_Pos) /*!< GPDMA C5LLI: LM Mask */
+#define GPDMA_C5LLI_R_Pos 1 /*!< GPDMA C5LLI: R Position */
+#define GPDMA_C5LLI_R_Msk (0x01UL << GPDMA_C5LLI_R_Pos) /*!< GPDMA C5LLI: R Mask */
+#define GPDMA_C5LLI_LLI_Pos 2 /*!< GPDMA C5LLI: LLI Position */
+#define GPDMA_C5LLI_LLI_Msk (0x3fffffffUL << GPDMA_C5LLI_LLI_Pos) /*!< GPDMA C5LLI: LLI Mask */
+
+// ------------------------------------- GPDMA_C5CONTROL ----------------------------------------
+#define GPDMA_C5CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C5CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C5CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C5CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C5CONTROL: TRANSFERSIZE Mask */
+#define GPDMA_C5CONTROL_SBSIZE_Pos 12 /*!< GPDMA C5CONTROL: SBSIZE Position */
+#define GPDMA_C5CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C5CONTROL_SBSIZE_Pos) /*!< GPDMA C5CONTROL: SBSIZE Mask */
+#define GPDMA_C5CONTROL_DBSIZE_Pos 15 /*!< GPDMA C5CONTROL: DBSIZE Position */
+#define GPDMA_C5CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C5CONTROL_DBSIZE_Pos) /*!< GPDMA C5CONTROL: DBSIZE Mask */
+#define GPDMA_C5CONTROL_SWIDTH_Pos 18 /*!< GPDMA C5CONTROL: SWIDTH Position */
+#define GPDMA_C5CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C5CONTROL_SWIDTH_Pos) /*!< GPDMA C5CONTROL: SWIDTH Mask */
+#define GPDMA_C5CONTROL_DWIDTH_Pos 21 /*!< GPDMA C5CONTROL: DWIDTH Position */
+#define GPDMA_C5CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C5CONTROL_DWIDTH_Pos) /*!< GPDMA C5CONTROL: DWIDTH Mask */
+#define GPDMA_C5CONTROL_S_Pos 24 /*!< GPDMA C5CONTROL: S Position */
+#define GPDMA_C5CONTROL_S_Msk (0x01UL << GPDMA_C5CONTROL_S_Pos) /*!< GPDMA C5CONTROL: S Mask */
+#define GPDMA_C5CONTROL_D_Pos 25 /*!< GPDMA C5CONTROL: D Position */
+#define GPDMA_C5CONTROL_D_Msk (0x01UL << GPDMA_C5CONTROL_D_Pos) /*!< GPDMA C5CONTROL: D Mask */
+#define GPDMA_C5CONTROL_SI_Pos 26 /*!< GPDMA C5CONTROL: SI Position */
+#define GPDMA_C5CONTROL_SI_Msk (0x01UL << GPDMA_C5CONTROL_SI_Pos) /*!< GPDMA C5CONTROL: SI Mask */
+#define GPDMA_C5CONTROL_DI_Pos 27 /*!< GPDMA C5CONTROL: DI Position */
+#define GPDMA_C5CONTROL_DI_Msk (0x01UL << GPDMA_C5CONTROL_DI_Pos) /*!< GPDMA C5CONTROL: DI Mask */
+#define GPDMA_C5CONTROL_PROT1_Pos 28 /*!< GPDMA C5CONTROL: PROT1 Position */
+#define GPDMA_C5CONTROL_PROT1_Msk (0x01UL << GPDMA_C5CONTROL_PROT1_Pos) /*!< GPDMA C5CONTROL: PROT1 Mask */
+#define GPDMA_C5CONTROL_PROT2_Pos 29 /*!< GPDMA C5CONTROL: PROT2 Position */
+#define GPDMA_C5CONTROL_PROT2_Msk (0x01UL << GPDMA_C5CONTROL_PROT2_Pos) /*!< GPDMA C5CONTROL: PROT2 Mask */
+#define GPDMA_C5CONTROL_PROT3_Pos 30 /*!< GPDMA C5CONTROL: PROT3 Position */
+#define GPDMA_C5CONTROL_PROT3_Msk (0x01UL << GPDMA_C5CONTROL_PROT3_Pos) /*!< GPDMA C5CONTROL: PROT3 Mask */
+#define GPDMA_C5CONTROL_I_Pos 31 /*!< GPDMA C5CONTROL: I Position */
+#define GPDMA_C5CONTROL_I_Msk (0x01UL << GPDMA_C5CONTROL_I_Pos) /*!< GPDMA C5CONTROL: I Mask */
+
+// ------------------------------------- GPDMA_C5CONFIG -----------------------------------------
+#define GPDMA_C5CONFIG_E_Pos 0 /*!< GPDMA C5CONFIG: E Position */
+#define GPDMA_C5CONFIG_E_Msk (0x01UL << GPDMA_C5CONFIG_E_Pos) /*!< GPDMA C5CONFIG: E Mask */
+#define GPDMA_C5CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C5CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C5CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C5CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C5CONFIG: SRCPERIPHERAL Mask */
+#define GPDMA_C5CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C5CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C5CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C5CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C5CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C5CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C5CONFIG: FLOWCNTRL Position */
+#define GPDMA_C5CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C5CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C5CONFIG: FLOWCNTRL Mask */
+#define GPDMA_C5CONFIG_IE_Pos 14 /*!< GPDMA C5CONFIG: IE Position */
+#define GPDMA_C5CONFIG_IE_Msk (0x01UL << GPDMA_C5CONFIG_IE_Pos) /*!< GPDMA C5CONFIG: IE Mask */
+#define GPDMA_C5CONFIG_ITC_Pos 15 /*!< GPDMA C5CONFIG: ITC Position */
+#define GPDMA_C5CONFIG_ITC_Msk (0x01UL << GPDMA_C5CONFIG_ITC_Pos) /*!< GPDMA C5CONFIG: ITC Mask */
+#define GPDMA_C5CONFIG_L_Pos 16 /*!< GPDMA C5CONFIG: L Position */
+#define GPDMA_C5CONFIG_L_Msk (0x01UL << GPDMA_C5CONFIG_L_Pos) /*!< GPDMA C5CONFIG: L Mask */
+#define GPDMA_C5CONFIG_A_Pos 17 /*!< GPDMA C5CONFIG: A Position */
+#define GPDMA_C5CONFIG_A_Msk (0x01UL << GPDMA_C5CONFIG_A_Pos) /*!< GPDMA C5CONFIG: A Mask */
+#define GPDMA_C5CONFIG_H_Pos 18 /*!< GPDMA C5CONFIG: H Position */
+#define GPDMA_C5CONFIG_H_Msk (0x01UL << GPDMA_C5CONFIG_H_Pos) /*!< GPDMA C5CONFIG: H Mask */
+
+// ------------------------------------- GPDMA_C6SRCADDR ----------------------------------------
+#define GPDMA_C6SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C6SRCADDR: SRCADDR Position */
+#define GPDMA_C6SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C6SRCADDR_SRCADDR_Pos) /*!< GPDMA C6SRCADDR: SRCADDR Mask */
+
+// ------------------------------------ GPDMA_C6DESTADDR ----------------------------------------
+#define GPDMA_C6DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C6DESTADDR: DESTADDR Position */
+#define GPDMA_C6DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C6DESTADDR_DESTADDR_Pos) /*!< GPDMA C6DESTADDR: DESTADDR Mask */
+
+// --------------------------------------- GPDMA_C6LLI ------------------------------------------
+#define GPDMA_C6LLI_LM_Pos 0 /*!< GPDMA C6LLI: LM Position */
+#define GPDMA_C6LLI_LM_Msk (0x01UL << GPDMA_C6LLI_LM_Pos) /*!< GPDMA C6LLI: LM Mask */
+#define GPDMA_C6LLI_R_Pos 1 /*!< GPDMA C6LLI: R Position */
+#define GPDMA_C6LLI_R_Msk (0x01UL << GPDMA_C6LLI_R_Pos) /*!< GPDMA C6LLI: R Mask */
+#define GPDMA_C6LLI_LLI_Pos 2 /*!< GPDMA C6LLI: LLI Position */
+#define GPDMA_C6LLI_LLI_Msk (0x3fffffffUL << GPDMA_C6LLI_LLI_Pos) /*!< GPDMA C6LLI: LLI Mask */
+
+// ------------------------------------- GPDMA_C6CONTROL ----------------------------------------
+#define GPDMA_C6CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C6CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C6CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C6CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C6CONTROL: TRANSFERSIZE Mask */
+#define GPDMA_C6CONTROL_SBSIZE_Pos 12 /*!< GPDMA C6CONTROL: SBSIZE Position */
+#define GPDMA_C6CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C6CONTROL_SBSIZE_Pos) /*!< GPDMA C6CONTROL: SBSIZE Mask */
+#define GPDMA_C6CONTROL_DBSIZE_Pos 15 /*!< GPDMA C6CONTROL: DBSIZE Position */
+#define GPDMA_C6CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C6CONTROL_DBSIZE_Pos) /*!< GPDMA C6CONTROL: DBSIZE Mask */
+#define GPDMA_C6CONTROL_SWIDTH_Pos 18 /*!< GPDMA C6CONTROL: SWIDTH Position */
+#define GPDMA_C6CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C6CONTROL_SWIDTH_Pos) /*!< GPDMA C6CONTROL: SWIDTH Mask */
+#define GPDMA_C6CONTROL_DWIDTH_Pos 21 /*!< GPDMA C6CONTROL: DWIDTH Position */
+#define GPDMA_C6CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C6CONTROL_DWIDTH_Pos) /*!< GPDMA C6CONTROL: DWIDTH Mask */
+#define GPDMA_C6CONTROL_S_Pos 24 /*!< GPDMA C6CONTROL: S Position */
+#define GPDMA_C6CONTROL_S_Msk (0x01UL << GPDMA_C6CONTROL_S_Pos) /*!< GPDMA C6CONTROL: S Mask */
+#define GPDMA_C6CONTROL_D_Pos 25 /*!< GPDMA C6CONTROL: D Position */
+#define GPDMA_C6CONTROL_D_Msk (0x01UL << GPDMA_C6CONTROL_D_Pos) /*!< GPDMA C6CONTROL: D Mask */
+#define GPDMA_C6CONTROL_SI_Pos 26 /*!< GPDMA C6CONTROL: SI Position */
+#define GPDMA_C6CONTROL_SI_Msk (0x01UL << GPDMA_C6CONTROL_SI_Pos) /*!< GPDMA C6CONTROL: SI Mask */
+#define GPDMA_C6CONTROL_DI_Pos 27 /*!< GPDMA C6CONTROL: DI Position */
+#define GPDMA_C6CONTROL_DI_Msk (0x01UL << GPDMA_C6CONTROL_DI_Pos) /*!< GPDMA C6CONTROL: DI Mask */
+#define GPDMA_C6CONTROL_PROT1_Pos 28 /*!< GPDMA C6CONTROL: PROT1 Position */
+#define GPDMA_C6CONTROL_PROT1_Msk (0x01UL << GPDMA_C6CONTROL_PROT1_Pos) /*!< GPDMA C6CONTROL: PROT1 Mask */
+#define GPDMA_C6CONTROL_PROT2_Pos 29 /*!< GPDMA C6CONTROL: PROT2 Position */
+#define GPDMA_C6CONTROL_PROT2_Msk (0x01UL << GPDMA_C6CONTROL_PROT2_Pos) /*!< GPDMA C6CONTROL: PROT2 Mask */
+#define GPDMA_C6CONTROL_PROT3_Pos 30 /*!< GPDMA C6CONTROL: PROT3 Position */
+#define GPDMA_C6CONTROL_PROT3_Msk (0x01UL << GPDMA_C6CONTROL_PROT3_Pos) /*!< GPDMA C6CONTROL: PROT3 Mask */
+#define GPDMA_C6CONTROL_I_Pos 31 /*!< GPDMA C6CONTROL: I Position */
+#define GPDMA_C6CONTROL_I_Msk (0x01UL << GPDMA_C6CONTROL_I_Pos) /*!< GPDMA C6CONTROL: I Mask */
+
+// ------------------------------------- GPDMA_C6CONFIG -----------------------------------------
+#define GPDMA_C6CONFIG_E_Pos 0 /*!< GPDMA C6CONFIG: E Position */
+#define GPDMA_C6CONFIG_E_Msk (0x01UL << GPDMA_C6CONFIG_E_Pos) /*!< GPDMA C6CONFIG: E Mask */
+#define GPDMA_C6CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C6CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C6CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C6CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C6CONFIG: SRCPERIPHERAL Mask */
+#define GPDMA_C6CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C6CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C6CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C6CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C6CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C6CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C6CONFIG: FLOWCNTRL Position */
+#define GPDMA_C6CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C6CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C6CONFIG: FLOWCNTRL Mask */
+#define GPDMA_C6CONFIG_IE_Pos 14 /*!< GPDMA C6CONFIG: IE Position */
+#define GPDMA_C6CONFIG_IE_Msk (0x01UL << GPDMA_C6CONFIG_IE_Pos) /*!< GPDMA C6CONFIG: IE Mask */
+#define GPDMA_C6CONFIG_ITC_Pos 15 /*!< GPDMA C6CONFIG: ITC Position */
+#define GPDMA_C6CONFIG_ITC_Msk (0x01UL << GPDMA_C6CONFIG_ITC_Pos) /*!< GPDMA C6CONFIG: ITC Mask */
+#define GPDMA_C6CONFIG_L_Pos 16 /*!< GPDMA C6CONFIG: L Position */
+#define GPDMA_C6CONFIG_L_Msk (0x01UL << GPDMA_C6CONFIG_L_Pos) /*!< GPDMA C6CONFIG: L Mask */
+#define GPDMA_C6CONFIG_A_Pos 17 /*!< GPDMA C6CONFIG: A Position */
+#define GPDMA_C6CONFIG_A_Msk (0x01UL << GPDMA_C6CONFIG_A_Pos) /*!< GPDMA C6CONFIG: A Mask */
+#define GPDMA_C6CONFIG_H_Pos 18 /*!< GPDMA C6CONFIG: H Position */
+#define GPDMA_C6CONFIG_H_Msk (0x01UL << GPDMA_C6CONFIG_H_Pos) /*!< GPDMA C6CONFIG: H Mask */
+
+// ------------------------------------- GPDMA_C7SRCADDR ----------------------------------------
+#define GPDMA_C7SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C7SRCADDR: SRCADDR Position */
+#define GPDMA_C7SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C7SRCADDR_SRCADDR_Pos) /*!< GPDMA C7SRCADDR: SRCADDR Mask */
+
+// ------------------------------------ GPDMA_C7DESTADDR ----------------------------------------
+#define GPDMA_C7DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C7DESTADDR: DESTADDR Position */
+#define GPDMA_C7DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C7DESTADDR_DESTADDR_Pos) /*!< GPDMA C7DESTADDR: DESTADDR Mask */
+
+// --------------------------------------- GPDMA_C7LLI ------------------------------------------
+#define GPDMA_C7LLI_LM_Pos 0 /*!< GPDMA C7LLI: LM Position */
+#define GPDMA_C7LLI_LM_Msk (0x01UL << GPDMA_C7LLI_LM_Pos) /*!< GPDMA C7LLI: LM Mask */
+#define GPDMA_C7LLI_R_Pos 1 /*!< GPDMA C7LLI: R Position */
+#define GPDMA_C7LLI_R_Msk (0x01UL << GPDMA_C7LLI_R_Pos) /*!< GPDMA C7LLI: R Mask */
+#define GPDMA_C7LLI_LLI_Pos 2 /*!< GPDMA C7LLI: LLI Position */
+#define GPDMA_C7LLI_LLI_Msk (0x3fffffffUL << GPDMA_C7LLI_LLI_Pos) /*!< GPDMA C7LLI: LLI Mask */
+
+// ------------------------------------- GPDMA_C7CONTROL ----------------------------------------
+#define GPDMA_C7CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C7CONTROL: TRANSFERSIZE Position */
+#define GPDMA_C7CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C7CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C7CONTROL: TRANSFERSIZE Mask */
+#define GPDMA_C7CONTROL_SBSIZE_Pos 12 /*!< GPDMA C7CONTROL: SBSIZE Position */
+#define GPDMA_C7CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C7CONTROL_SBSIZE_Pos) /*!< GPDMA C7CONTROL: SBSIZE Mask */
+#define GPDMA_C7CONTROL_DBSIZE_Pos 15 /*!< GPDMA C7CONTROL: DBSIZE Position */
+#define GPDMA_C7CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C7CONTROL_DBSIZE_Pos) /*!< GPDMA C7CONTROL: DBSIZE Mask */
+#define GPDMA_C7CONTROL_SWIDTH_Pos 18 /*!< GPDMA C7CONTROL: SWIDTH Position */
+#define GPDMA_C7CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C7CONTROL_SWIDTH_Pos) /*!< GPDMA C7CONTROL: SWIDTH Mask */
+#define GPDMA_C7CONTROL_DWIDTH_Pos 21 /*!< GPDMA C7CONTROL: DWIDTH Position */
+#define GPDMA_C7CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C7CONTROL_DWIDTH_Pos) /*!< GPDMA C7CONTROL: DWIDTH Mask */
+#define GPDMA_C7CONTROL_S_Pos 24 /*!< GPDMA C7CONTROL: S Position */
+#define GPDMA_C7CONTROL_S_Msk (0x01UL << GPDMA_C7CONTROL_S_Pos) /*!< GPDMA C7CONTROL: S Mask */
+#define GPDMA_C7CONTROL_D_Pos 25 /*!< GPDMA C7CONTROL: D Position */
+#define GPDMA_C7CONTROL_D_Msk (0x01UL << GPDMA_C7CONTROL_D_Pos) /*!< GPDMA C7CONTROL: D Mask */
+#define GPDMA_C7CONTROL_SI_Pos 26 /*!< GPDMA C7CONTROL: SI Position */
+#define GPDMA_C7CONTROL_SI_Msk (0x01UL << GPDMA_C7CONTROL_SI_Pos) /*!< GPDMA C7CONTROL: SI Mask */
+#define GPDMA_C7CONTROL_DI_Pos 27 /*!< GPDMA C7CONTROL: DI Position */
+#define GPDMA_C7CONTROL_DI_Msk (0x01UL << GPDMA_C7CONTROL_DI_Pos) /*!< GPDMA C7CONTROL: DI Mask */
+#define GPDMA_C7CONTROL_PROT1_Pos 28 /*!< GPDMA C7CONTROL: PROT1 Position */
+#define GPDMA_C7CONTROL_PROT1_Msk (0x01UL << GPDMA_C7CONTROL_PROT1_Pos) /*!< GPDMA C7CONTROL: PROT1 Mask */
+#define GPDMA_C7CONTROL_PROT2_Pos 29 /*!< GPDMA C7CONTROL: PROT2 Position */
+#define GPDMA_C7CONTROL_PROT2_Msk (0x01UL << GPDMA_C7CONTROL_PROT2_Pos) /*!< GPDMA C7CONTROL: PROT2 Mask */
+#define GPDMA_C7CONTROL_PROT3_Pos 30 /*!< GPDMA C7CONTROL: PROT3 Position */
+#define GPDMA_C7CONTROL_PROT3_Msk (0x01UL << GPDMA_C7CONTROL_PROT3_Pos) /*!< GPDMA C7CONTROL: PROT3 Mask */
+#define GPDMA_C7CONTROL_I_Pos 31 /*!< GPDMA C7CONTROL: I Position */
+#define GPDMA_C7CONTROL_I_Msk (0x01UL << GPDMA_C7CONTROL_I_Pos) /*!< GPDMA C7CONTROL: I Mask */
+
+// ------------------------------------- GPDMA_C7CONFIG -----------------------------------------
+#define GPDMA_C7CONFIG_E_Pos 0 /*!< GPDMA C7CONFIG: E Position */
+#define GPDMA_C7CONFIG_E_Msk (0x01UL << GPDMA_C7CONFIG_E_Pos) /*!< GPDMA C7CONFIG: E Mask */
+#define GPDMA_C7CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C7CONFIG: SRCPERIPHERAL Position */
+#define GPDMA_C7CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C7CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C7CONFIG: SRCPERIPHERAL Mask */
+#define GPDMA_C7CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C7CONFIG: DESTPERIPHERAL Position */
+#define GPDMA_C7CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C7CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C7CONFIG: DESTPERIPHERAL Mask */
+#define GPDMA_C7CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C7CONFIG: FLOWCNTRL Position */
+#define GPDMA_C7CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C7CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C7CONFIG: FLOWCNTRL Mask */
+#define GPDMA_C7CONFIG_IE_Pos 14 /*!< GPDMA C7CONFIG: IE Position */
+#define GPDMA_C7CONFIG_IE_Msk (0x01UL << GPDMA_C7CONFIG_IE_Pos) /*!< GPDMA C7CONFIG: IE Mask */
+#define GPDMA_C7CONFIG_ITC_Pos 15 /*!< GPDMA C7CONFIG: ITC Position */
+#define GPDMA_C7CONFIG_ITC_Msk (0x01UL << GPDMA_C7CONFIG_ITC_Pos) /*!< GPDMA C7CONFIG: ITC Mask */
+#define GPDMA_C7CONFIG_L_Pos 16 /*!< GPDMA C7CONFIG: L Position */
+#define GPDMA_C7CONFIG_L_Msk (0x01UL << GPDMA_C7CONFIG_L_Pos) /*!< GPDMA C7CONFIG: L Mask */
+#define GPDMA_C7CONFIG_A_Pos 17 /*!< GPDMA C7CONFIG: A Position */
+#define GPDMA_C7CONFIG_A_Msk (0x01UL << GPDMA_C7CONFIG_A_Pos) /*!< GPDMA C7CONFIG: A Mask */
+#define GPDMA_C7CONFIG_H_Pos 18 /*!< GPDMA C7CONFIG: H Position */
+#define GPDMA_C7CONFIG_H_Msk (0x01UL << GPDMA_C7CONFIG_H_Pos) /*!< GPDMA C7CONFIG: H Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SDMMC Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------- SDMMC_CTRL -------------------------------------------
+#define SDMMC_CTRL_CONTROLLER_RESET_Pos 0 /*!< SDMMC CTRL: CONTROLLER_RESET Position */
+#define SDMMC_CTRL_CONTROLLER_RESET_Msk (0x01UL << SDMMC_CTRL_CONTROLLER_RESET_Pos) /*!< SDMMC CTRL: CONTROLLER_RESET Mask */
+#define SDMMC_CTRL_FIFO_RESET_Pos 1 /*!< SDMMC CTRL: FIFO_RESET Position */
+#define SDMMC_CTRL_FIFO_RESET_Msk (0x01UL << SDMMC_CTRL_FIFO_RESET_Pos) /*!< SDMMC CTRL: FIFO_RESET Mask */
+#define SDMMC_CTRL_DMA_RESET_Pos 2 /*!< SDMMC CTRL: DMA_RESET Position */
+#define SDMMC_CTRL_DMA_RESET_Msk (0x01UL << SDMMC_CTRL_DMA_RESET_Pos) /*!< SDMMC CTRL: DMA_RESET Mask */
+#define SDMMC_CTRL_INT_ENABLE_Pos 4 /*!< SDMMC CTRL: INT_ENABLE Position */
+#define SDMMC_CTRL_INT_ENABLE_Msk (0x01UL << SDMMC_CTRL_INT_ENABLE_Pos) /*!< SDMMC CTRL: INT_ENABLE Mask */
+#define SDMMC_CTRL_DMA_ENABLE_Pos 5 /*!< SDMMC CTRL: DMA_ENABLE Position */
+#define SDMMC_CTRL_DMA_ENABLE_Msk (0x01UL << SDMMC_CTRL_DMA_ENABLE_Pos) /*!< SDMMC CTRL: DMA_ENABLE Mask */
+#define SDMMC_CTRL_READ_WAIT_Pos 6 /*!< SDMMC CTRL: READ_WAIT Position */
+#define SDMMC_CTRL_READ_WAIT_Msk (0x01UL << SDMMC_CTRL_READ_WAIT_Pos) /*!< SDMMC CTRL: READ_WAIT Mask */
+#define SDMMC_CTRL_SEND_IRQ_RESPONSE_Pos 7 /*!< SDMMC CTRL: SEND_IRQ_RESPONSE Position */
+#define SDMMC_CTRL_SEND_IRQ_RESPONSE_Msk (0x01UL << SDMMC_CTRL_SEND_IRQ_RESPONSE_Pos) /*!< SDMMC CTRL: SEND_IRQ_RESPONSE Mask */
+#define SDMMC_CTRL_ABORT_READ_DATA_Pos 8 /*!< SDMMC CTRL: ABORT_READ_DATA Position */
+#define SDMMC_CTRL_ABORT_READ_DATA_Msk (0x01UL << SDMMC_CTRL_ABORT_READ_DATA_Pos) /*!< SDMMC CTRL: ABORT_READ_DATA Mask */
+#define SDMMC_CTRL_SEND_CCSD_Pos 9 /*!< SDMMC CTRL: SEND_CCSD Position */
+#define SDMMC_CTRL_SEND_CCSD_Msk (0x01UL << SDMMC_CTRL_SEND_CCSD_Pos) /*!< SDMMC CTRL: SEND_CCSD Mask */
+#define SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Pos 10 /*!< SDMMC CTRL: SEND_AUTO_STOP_CCSD Position */
+#define SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Msk (0x01UL << SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Pos) /*!< SDMMC CTRL: SEND_AUTO_STOP_CCSD Mask */
+#define SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos 11 /*!< SDMMC CTRL: CEATA_DEVICE_INTERRUPT_STATUS Position */
+#define SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Msk (0x01UL << SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos) /*!< SDMMC CTRL: CEATA_DEVICE_INTERRUPT_STATUS Mask */
+#define SDMMC_CTRL_CARD_VOLTAGE_A_Pos 16 /*!< SDMMC CTRL: CARD_VOLTAGE_A Position */
+#define SDMMC_CTRL_CARD_VOLTAGE_A_Msk (0x0fUL << SDMMC_CTRL_CARD_VOLTAGE_A_Pos) /*!< SDMMC CTRL: CARD_VOLTAGE_A Mask */
+#define SDMMC_CTRL_CARD_VOLTAGE_B_Pos 20 /*!< SDMMC CTRL: CARD_VOLTAGE_B Position */
+#define SDMMC_CTRL_CARD_VOLTAGE_B_Msk (0x0fUL << SDMMC_CTRL_CARD_VOLTAGE_B_Pos) /*!< SDMMC CTRL: CARD_VOLTAGE_B Mask */
+#define SDMMC_CTRL_ENABLE_OD_PULLUP_Pos 24 /*!< SDMMC CTRL: ENABLE_OD_PULLUP Position */
+#define SDMMC_CTRL_ENABLE_OD_PULLUP_Msk (0x01UL << SDMMC_CTRL_ENABLE_OD_PULLUP_Pos) /*!< SDMMC CTRL: ENABLE_OD_PULLUP Mask */
+#define SDMMC_CTRL_USE_INTERNAL_DMAC_Pos 25 /*!< SDMMC CTRL: USE_INTERNAL_DMAC Position */
+#define SDMMC_CTRL_USE_INTERNAL_DMAC_Msk (0x01UL << SDMMC_CTRL_USE_INTERNAL_DMAC_Pos) /*!< SDMMC CTRL: USE_INTERNAL_DMAC Mask */
+
+// --------------------------------------- SDMMC_PWREN ------------------------------------------
+#define SDMMC_PWREN_POWER_ENABLE_Pos 0 /*!< SDMMC PWREN: POWER_ENABLE Position */
+#define SDMMC_PWREN_POWER_ENABLE_Msk (0x3fffffffUL << SDMMC_PWREN_POWER_ENABLE_Pos) /*!< SDMMC PWREN: POWER_ENABLE Mask */
+
+// -------------------------------------- SDMMC_CLKDIV ------------------------------------------
+#define SDMMC_CLKDIV_CLK_DIVIDER0_Pos 0 /*!< SDMMC CLKDIV: CLK_DIVIDER0 Position */
+#define SDMMC_CLKDIV_CLK_DIVIDER0_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER0_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER0 Mask */
+#define SDMMC_CLKDIV_CLK_DIVIDER1_Pos 8 /*!< SDMMC CLKDIV: CLK_DIVIDER1 Position */
+#define SDMMC_CLKDIV_CLK_DIVIDER1_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER1_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER1 Mask */
+#define SDMMC_CLKDIV_CLK_DIVIDER2_Pos 16 /*!< SDMMC CLKDIV: CLK_DIVIDER2 Position */
+#define SDMMC_CLKDIV_CLK_DIVIDER2_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER2_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER2 Mask */
+#define SDMMC_CLKDIV_CLK_DIVIDER3_Pos 24 /*!< SDMMC CLKDIV: CLK_DIVIDER3 Position */
+#define SDMMC_CLKDIV_CLK_DIVIDER3_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER3_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER3 Mask */
+
+// -------------------------------------- SDMMC_CLKSRC ------------------------------------------
+#define SDMMC_CLKSRC_CLK_SOURCE_Pos 0 /*!< SDMMC CLKSRC: CLK_SOURCE Position */
+#define SDMMC_CLKSRC_CLK_SOURCE_Msk (0xffffffffUL << SDMMC_CLKSRC_CLK_SOURCE_Pos) /*!< SDMMC CLKSRC: CLK_SOURCE Mask */
+
+// -------------------------------------- SDMMC_CLKENA ------------------------------------------
+#define SDMMC_CLKENA_CCLK_ENABLE_Pos 0 /*!< SDMMC CLKENA: CCLK_ENABLE Position */
+#define SDMMC_CLKENA_CCLK_ENABLE_Msk (0x0000ffffUL << SDMMC_CLKENA_CCLK_ENABLE_Pos) /*!< SDMMC CLKENA: CCLK_ENABLE Mask */
+#define SDMMC_CLKENA_CCLK_LOW_POWER_Pos 16 /*!< SDMMC CLKENA: CCLK_LOW_POWER Position */
+#define SDMMC_CLKENA_CCLK_LOW_POWER_Msk (0x0000ffffUL << SDMMC_CLKENA_CCLK_LOW_POWER_Pos) /*!< SDMMC CLKENA: CCLK_LOW_POWER Mask */
+
+// --------------------------------------- SDMMC_TMOUT ------------------------------------------
+#define SDMMC_TMOUT_RESPONSE_TIMEOUT_Pos 0 /*!< SDMMC TMOUT: RESPONSE_TIMEOUT Position */
+#define SDMMC_TMOUT_RESPONSE_TIMEOUT_Msk (0x000000ffUL << SDMMC_TMOUT_RESPONSE_TIMEOUT_Pos) /*!< SDMMC TMOUT: RESPONSE_TIMEOUT Mask */
+#define SDMMC_TMOUT_DATA_TIMEOUT_Pos 8 /*!< SDMMC TMOUT: DATA_TIMEOUT Position */
+#define SDMMC_TMOUT_DATA_TIMEOUT_Msk (0x00ffffffUL << SDMMC_TMOUT_DATA_TIMEOUT_Pos) /*!< SDMMC TMOUT: DATA_TIMEOUT Mask */
+
+// --------------------------------------- SDMMC_CTYPE ------------------------------------------
+#define SDMMC_CTYPE_CARD_WIDTH0_Pos 0 /*!< SDMMC CTYPE: CARD_WIDTH0 Position */
+#define SDMMC_CTYPE_CARD_WIDTH0_Msk (0x0000ffffUL << SDMMC_CTYPE_CARD_WIDTH0_Pos) /*!< SDMMC CTYPE: CARD_WIDTH0 Mask */
+#define SDMMC_CTYPE_CARD_WIDTH1_Pos 16 /*!< SDMMC CTYPE: CARD_WIDTH1 Position */
+#define SDMMC_CTYPE_CARD_WIDTH1_Msk (0x0000ffffUL << SDMMC_CTYPE_CARD_WIDTH1_Pos) /*!< SDMMC CTYPE: CARD_WIDTH1 Mask */
+
+// -------------------------------------- SDMMC_BLKSIZ ------------------------------------------
+#define SDMMC_BLKSIZ_BLOCK_SIZE_Pos 0 /*!< SDMMC BLKSIZ: BLOCK_SIZE Position */
+#define SDMMC_BLKSIZ_BLOCK_SIZE_Msk (0x0000ffffUL << SDMMC_BLKSIZ_BLOCK_SIZE_Pos) /*!< SDMMC BLKSIZ: BLOCK_SIZE Mask */
+
+// -------------------------------------- SDMMC_BYTCNT ------------------------------------------
+#define SDMMC_BYTCNT_BYTE_COUNT_Pos 0 /*!< SDMMC BYTCNT: BYTE_COUNT Position */
+#define SDMMC_BYTCNT_BYTE_COUNT_Msk (0xffffffffUL << SDMMC_BYTCNT_BYTE_COUNT_Pos) /*!< SDMMC BYTCNT: BYTE_COUNT Mask */
+
+// -------------------------------------- SDMMC_INTMASK -----------------------------------------
+#define SDMMC_INTMASK_CDET_Pos 0 /*!< SDMMC INTMASK: CDET Position */
+#define SDMMC_INTMASK_CDET_Msk (0x01UL << SDMMC_INTMASK_CDET_Pos) /*!< SDMMC INTMASK: CDET Mask */
+#define SDMMC_INTMASK_RE_Pos 1 /*!< SDMMC INTMASK: RE Position */
+#define SDMMC_INTMASK_RE_Msk (0x01UL << SDMMC_INTMASK_RE_Pos) /*!< SDMMC INTMASK: RE Mask */
+#define SDMMC_INTMASK_CDONE_Pos 2 /*!< SDMMC INTMASK: CDONE Position */
+#define SDMMC_INTMASK_CDONE_Msk (0x01UL << SDMMC_INTMASK_CDONE_Pos) /*!< SDMMC INTMASK: CDONE Mask */
+#define SDMMC_INTMASK_DTO_Pos 3 /*!< SDMMC INTMASK: DTO Position */
+#define SDMMC_INTMASK_DTO_Msk (0x01UL << SDMMC_INTMASK_DTO_Pos) /*!< SDMMC INTMASK: DTO Mask */
+#define SDMMC_INTMASK_TXDR_Pos 4 /*!< SDMMC INTMASK: TXDR Position */
+#define SDMMC_INTMASK_TXDR_Msk (0x01UL << SDMMC_INTMASK_TXDR_Pos) /*!< SDMMC INTMASK: TXDR Mask */
+#define SDMMC_INTMASK_RXDR_Pos 5 /*!< SDMMC INTMASK: RXDR Position */
+#define SDMMC_INTMASK_RXDR_Msk (0x01UL << SDMMC_INTMASK_RXDR_Pos) /*!< SDMMC INTMASK: RXDR Mask */
+#define SDMMC_INTMASK_RCRC_Pos 6 /*!< SDMMC INTMASK: RCRC Position */
+#define SDMMC_INTMASK_RCRC_Msk (0x01UL << SDMMC_INTMASK_RCRC_Pos) /*!< SDMMC INTMASK: RCRC Mask */
+#define SDMMC_INTMASK_DCRC_Pos 7 /*!< SDMMC INTMASK: DCRC Position */
+#define SDMMC_INTMASK_DCRC_Msk (0x01UL << SDMMC_INTMASK_DCRC_Pos) /*!< SDMMC INTMASK: DCRC Mask */
+#define SDMMC_INTMASK_RTO_Pos 8 /*!< SDMMC INTMASK: RTO Position */
+#define SDMMC_INTMASK_RTO_Msk (0x01UL << SDMMC_INTMASK_RTO_Pos) /*!< SDMMC INTMASK: RTO Mask */
+#define SDMMC_INTMASK_DRTO_Pos 9 /*!< SDMMC INTMASK: DRTO Position */
+#define SDMMC_INTMASK_DRTO_Msk (0x01UL << SDMMC_INTMASK_DRTO_Pos) /*!< SDMMC INTMASK: DRTO Mask */
+#define SDMMC_INTMASK_HTO_Pos 10 /*!< SDMMC INTMASK: HTO Position */
+#define SDMMC_INTMASK_HTO_Msk (0x01UL << SDMMC_INTMASK_HTO_Pos) /*!< SDMMC INTMASK: HTO Mask */
+#define SDMMC_INTMASK_FRUN_Pos 11 /*!< SDMMC INTMASK: FRUN Position */
+#define SDMMC_INTMASK_FRUN_Msk (0x01UL << SDMMC_INTMASK_FRUN_Pos) /*!< SDMMC INTMASK: FRUN Mask */
+#define SDMMC_INTMASK_HLE_Pos 12 /*!< SDMMC INTMASK: HLE Position */
+#define SDMMC_INTMASK_HLE_Msk (0x01UL << SDMMC_INTMASK_HLE_Pos) /*!< SDMMC INTMASK: HLE Mask */
+#define SDMMC_INTMASK_SBE_Pos 13 /*!< SDMMC INTMASK: SBE Position */
+#define SDMMC_INTMASK_SBE_Msk (0x01UL << SDMMC_INTMASK_SBE_Pos) /*!< SDMMC INTMASK: SBE Mask */
+#define SDMMC_INTMASK_ACD_Pos 14 /*!< SDMMC INTMASK: ACD Position */
+#define SDMMC_INTMASK_ACD_Msk (0x01UL << SDMMC_INTMASK_ACD_Pos) /*!< SDMMC INTMASK: ACD Mask */
+#define SDMMC_INTMASK_EBE_Pos 15 /*!< SDMMC INTMASK: EBE Position */
+#define SDMMC_INTMASK_EBE_Msk (0x01UL << SDMMC_INTMASK_EBE_Pos) /*!< SDMMC INTMASK: EBE Mask */
+#define SDMMC_INTMASK_SDIO_INT_MASK_Pos 16 /*!< SDMMC INTMASK: SDIO_INT_MASK Position */
+#define SDMMC_INTMASK_SDIO_INT_MASK_Msk (0x0000ffffUL << SDMMC_INTMASK_SDIO_INT_MASK_Pos) /*!< SDMMC INTMASK: SDIO_INT_MASK Mask */
+
+// -------------------------------------- SDMMC_CMDARG ------------------------------------------
+#define SDMMC_CMDARG_CMD_ARG_Pos 0 /*!< SDMMC CMDARG: CMD_ARG Position */
+#define SDMMC_CMDARG_CMD_ARG_Msk (0xffffffffUL << SDMMC_CMDARG_CMD_ARG_Pos) /*!< SDMMC CMDARG: CMD_ARG Mask */
+
+// ---------------------------------------- SDMMC_CMD -------------------------------------------
+#define SDMMC_CMD_CMD_INDEX_Pos 0 /*!< SDMMC CMD: CMD_INDEX Position */
+#define SDMMC_CMD_CMD_INDEX_Msk (0x3fUL << SDMMC_CMD_CMD_INDEX_Pos) /*!< SDMMC CMD: CMD_INDEX Mask */
+#define SDMMC_CMD_RESPONSE_EXPECT_Pos 6 /*!< SDMMC CMD: RESPONSE_EXPECT Position */
+#define SDMMC_CMD_RESPONSE_EXPECT_Msk (0x01UL << SDMMC_CMD_RESPONSE_EXPECT_Pos) /*!< SDMMC CMD: RESPONSE_EXPECT Mask */
+#define SDMMC_CMD_RESPONSE_LENGTH_Pos 7 /*!< SDMMC CMD: RESPONSE_LENGTH Position */
+#define SDMMC_CMD_RESPONSE_LENGTH_Msk (0x01UL << SDMMC_CMD_RESPONSE_LENGTH_Pos) /*!< SDMMC CMD: RESPONSE_LENGTH Mask */
+#define SDMMC_CMD_CHECK_RESPONSE_CRC_Pos 8 /*!< SDMMC CMD: CHECK_RESPONSE_CRC Position */
+#define SDMMC_CMD_CHECK_RESPONSE_CRC_Msk (0x01UL << SDMMC_CMD_CHECK_RESPONSE_CRC_Pos) /*!< SDMMC CMD: CHECK_RESPONSE_CRC Mask */
+#define SDMMC_CMD_DATA_EXPECTED_Pos 9 /*!< SDMMC CMD: DATA_EXPECTED Position */
+#define SDMMC_CMD_DATA_EXPECTED_Msk (0x01UL << SDMMC_CMD_DATA_EXPECTED_Pos) /*!< SDMMC CMD: DATA_EXPECTED Mask */
+#define SDMMC_CMD_READ_WRITE_Pos 10 /*!< SDMMC CMD: READ_WRITE Position */
+#define SDMMC_CMD_READ_WRITE_Msk (0x01UL << SDMMC_CMD_READ_WRITE_Pos) /*!< SDMMC CMD: READ_WRITE Mask */
+#define SDMMC_CMD_TRANSFER_MODE_Pos 11 /*!< SDMMC CMD: TRANSFER_MODE Position */
+#define SDMMC_CMD_TRANSFER_MODE_Msk (0x01UL << SDMMC_CMD_TRANSFER_MODE_Pos) /*!< SDMMC CMD: TRANSFER_MODE Mask */
+#define SDMMC_CMD_SEND_AUTO_STOP_Pos 12 /*!< SDMMC CMD: SEND_AUTO_STOP Position */
+#define SDMMC_CMD_SEND_AUTO_STOP_Msk (0x01UL << SDMMC_CMD_SEND_AUTO_STOP_Pos) /*!< SDMMC CMD: SEND_AUTO_STOP Mask */
+#define SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Pos 13 /*!< SDMMC CMD: WAIT_PRVDATA_COMPLETE Position */
+#define SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Msk (0x01UL << SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Pos) /*!< SDMMC CMD: WAIT_PRVDATA_COMPLETE Mask */
+#define SDMMC_CMD_STOP_ABORT_CMd_Pos 14 /*!< SDMMC CMD: STOP_ABORT_CMd Position */
+#define SDMMC_CMD_STOP_ABORT_CMd_Msk (0x01UL << SDMMC_CMD_STOP_ABORT_CMd_Pos) /*!< SDMMC CMD: STOP_ABORT_CMd Mask */
+#define SDMMC_CMD_SEND_INITIALIZATION_Pos 15 /*!< SDMMC CMD: SEND_INITIALIZATION Position */
+#define SDMMC_CMD_SEND_INITIALIZATION_Msk (0x01UL << SDMMC_CMD_SEND_INITIALIZATION_Pos) /*!< SDMMC CMD: SEND_INITIALIZATION Mask */
+#define SDMMC_CMD_CARD_NUMBER_Pos 16 /*!< SDMMC CMD: CARD_NUMBER Position */
+#define SDMMC_CMD_CARD_NUMBER_Msk (0x1fUL << SDMMC_CMD_CARD_NUMBER_Pos) /*!< SDMMC CMD: CARD_NUMBER Mask */
+#define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos 21 /*!< SDMMC CMD: UPDATE_CLOCK_REGISTERS_ONLY Position */
+#define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Msk (0x01UL << SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos) /*!< SDMMC CMD: UPDATE_CLOCK_REGISTERS_ONLY Mask */
+#define SDMMC_CMD_READ_CEATA_DEVICE_Pos 22 /*!< SDMMC CMD: READ_CEATA_DEVICE Position */
+#define SDMMC_CMD_READ_CEATA_DEVICE_Msk (0x01UL << SDMMC_CMD_READ_CEATA_DEVICE_Pos) /*!< SDMMC CMD: READ_CEATA_DEVICE Mask */
+#define SDMMC_CMD_CCS_EXPECTED_Pos 23 /*!< SDMMC CMD: CCS_EXPECTED Position */
+#define SDMMC_CMD_CCS_EXPECTED_Msk (0x01UL << SDMMC_CMD_CCS_EXPECTED_Pos) /*!< SDMMC CMD: CCS_EXPECTED Mask */
+#define SDMMC_CMD_ENABLE_BOOT_Pos 24 /*!< SDMMC CMD: ENABLE_BOOT Position */
+#define SDMMC_CMD_ENABLE_BOOT_Msk (0x01UL << SDMMC_CMD_ENABLE_BOOT_Pos) /*!< SDMMC CMD: ENABLE_BOOT Mask */
+#define SDMMC_CMD_EXPECT_BOOT_ACK_Pos 25 /*!< SDMMC CMD: EXPECT_BOOT_ACK Position */
+#define SDMMC_CMD_EXPECT_BOOT_ACK_Msk (0x01UL << SDMMC_CMD_EXPECT_BOOT_ACK_Pos) /*!< SDMMC CMD: EXPECT_BOOT_ACK Mask */
+#define SDMMC_CMD_DISABLE_BOOT_Pos 26 /*!< SDMMC CMD: DISABLE_BOOT Position */
+#define SDMMC_CMD_DISABLE_BOOT_Msk (0x01UL << SDMMC_CMD_DISABLE_BOOT_Pos) /*!< SDMMC CMD: DISABLE_BOOT Mask */
+#define SDMMC_CMD_BOOT_MODE_Pos 27 /*!< SDMMC CMD: BOOT_MODE Position */
+#define SDMMC_CMD_BOOT_MODE_Msk (0x01UL << SDMMC_CMD_BOOT_MODE_Pos) /*!< SDMMC CMD: BOOT_MODE Mask */
+#define SDMMC_CMD_VOLT_SWITCH_Pos 28 /*!< SDMMC CMD: VOLT_SWITCH Position */
+#define SDMMC_CMD_VOLT_SWITCH_Msk (0x01UL << SDMMC_CMD_VOLT_SWITCH_Pos) /*!< SDMMC CMD: VOLT_SWITCH Mask */
+#define SDMMC_CMD_START_CMD_Pos 31 /*!< SDMMC CMD: START_CMD Position */
+#define SDMMC_CMD_START_CMD_Msk (0x01UL << SDMMC_CMD_START_CMD_Pos) /*!< SDMMC CMD: START_CMD Mask */
+
+// --------------------------------------- SDMMC_RESP0 ------------------------------------------
+#define SDMMC_RESP0_RESPONSE0_Pos 0 /*!< SDMMC RESP0: RESPONSE0 Position */
+#define SDMMC_RESP0_RESPONSE0_Msk (0xffffffffUL << SDMMC_RESP0_RESPONSE0_Pos) /*!< SDMMC RESP0: RESPONSE0 Mask */
+
+// --------------------------------------- SDMMC_RESP1 ------------------------------------------
+#define SDMMC_RESP1_RESPONSE1_Pos 0 /*!< SDMMC RESP1: RESPONSE1 Position */
+#define SDMMC_RESP1_RESPONSE1_Msk (0xffffffffUL << SDMMC_RESP1_RESPONSE1_Pos) /*!< SDMMC RESP1: RESPONSE1 Mask */
+
+// --------------------------------------- SDMMC_RESP2 ------------------------------------------
+#define SDMMC_RESP2_RESPONSE2_Pos 0 /*!< SDMMC RESP2: RESPONSE2 Position */
+#define SDMMC_RESP2_RESPONSE2_Msk (0xffffffffUL << SDMMC_RESP2_RESPONSE2_Pos) /*!< SDMMC RESP2: RESPONSE2 Mask */
+
+// --------------------------------------- SDMMC_RESP3 ------------------------------------------
+#define SDMMC_RESP3_RESPONSE3_Pos 0 /*!< SDMMC RESP3: RESPONSE3 Position */
+#define SDMMC_RESP3_RESPONSE3_Msk (0xffffffffUL << SDMMC_RESP3_RESPONSE3_Pos) /*!< SDMMC RESP3: RESPONSE3 Mask */
+
+// -------------------------------------- SDMMC_MINTSTS -----------------------------------------
+#define SDMMC_MINTSTS_CDET_Pos 0 /*!< SDMMC MINTSTS: CDET Position */
+#define SDMMC_MINTSTS_CDET_Msk (0x01UL << SDMMC_MINTSTS_CDET_Pos) /*!< SDMMC MINTSTS: CDET Mask */
+#define SDMMC_MINTSTS_RE_Pos 1 /*!< SDMMC MINTSTS: RE Position */
+#define SDMMC_MINTSTS_RE_Msk (0x01UL << SDMMC_MINTSTS_RE_Pos) /*!< SDMMC MINTSTS: RE Mask */
+#define SDMMC_MINTSTS_CDONE_Pos 2 /*!< SDMMC MINTSTS: CDONE Position */
+#define SDMMC_MINTSTS_CDONE_Msk (0x01UL << SDMMC_MINTSTS_CDONE_Pos) /*!< SDMMC MINTSTS: CDONE Mask */
+#define SDMMC_MINTSTS_DTO_Pos 3 /*!< SDMMC MINTSTS: DTO Position */
+#define SDMMC_MINTSTS_DTO_Msk (0x01UL << SDMMC_MINTSTS_DTO_Pos) /*!< SDMMC MINTSTS: DTO Mask */
+#define SDMMC_MINTSTS_TXDR_Pos 4 /*!< SDMMC MINTSTS: TXDR Position */
+#define SDMMC_MINTSTS_TXDR_Msk (0x01UL << SDMMC_MINTSTS_TXDR_Pos) /*!< SDMMC MINTSTS: TXDR Mask */
+#define SDMMC_MINTSTS_RXDR_Pos 5 /*!< SDMMC MINTSTS: RXDR Position */
+#define SDMMC_MINTSTS_RXDR_Msk (0x01UL << SDMMC_MINTSTS_RXDR_Pos) /*!< SDMMC MINTSTS: RXDR Mask */
+#define SDMMC_MINTSTS_RCRC_Pos 6 /*!< SDMMC MINTSTS: RCRC Position */
+#define SDMMC_MINTSTS_RCRC_Msk (0x01UL << SDMMC_MINTSTS_RCRC_Pos) /*!< SDMMC MINTSTS: RCRC Mask */
+#define SDMMC_MINTSTS_DCRC_Pos 7 /*!< SDMMC MINTSTS: DCRC Position */
+#define SDMMC_MINTSTS_DCRC_Msk (0x01UL << SDMMC_MINTSTS_DCRC_Pos) /*!< SDMMC MINTSTS: DCRC Mask */
+#define SDMMC_MINTSTS_RTO_Pos 8 /*!< SDMMC MINTSTS: RTO Position */
+#define SDMMC_MINTSTS_RTO_Msk (0x01UL << SDMMC_MINTSTS_RTO_Pos) /*!< SDMMC MINTSTS: RTO Mask */
+#define SDMMC_MINTSTS_DRTO_Pos 9 /*!< SDMMC MINTSTS: DRTO Position */
+#define SDMMC_MINTSTS_DRTO_Msk (0x01UL << SDMMC_MINTSTS_DRTO_Pos) /*!< SDMMC MINTSTS: DRTO Mask */
+#define SDMMC_MINTSTS_HTO_Pos 10 /*!< SDMMC MINTSTS: HTO Position */
+#define SDMMC_MINTSTS_HTO_Msk (0x01UL << SDMMC_MINTSTS_HTO_Pos) /*!< SDMMC MINTSTS: HTO Mask */
+#define SDMMC_MINTSTS_FRUN_Pos 11 /*!< SDMMC MINTSTS: FRUN Position */
+#define SDMMC_MINTSTS_FRUN_Msk (0x01UL << SDMMC_MINTSTS_FRUN_Pos) /*!< SDMMC MINTSTS: FRUN Mask */
+#define SDMMC_MINTSTS_HLE_Pos 12 /*!< SDMMC MINTSTS: HLE Position */
+#define SDMMC_MINTSTS_HLE_Msk (0x01UL << SDMMC_MINTSTS_HLE_Pos) /*!< SDMMC MINTSTS: HLE Mask */
+#define SDMMC_MINTSTS_SBE_Pos 13 /*!< SDMMC MINTSTS: SBE Position */
+#define SDMMC_MINTSTS_SBE_Msk (0x01UL << SDMMC_MINTSTS_SBE_Pos) /*!< SDMMC MINTSTS: SBE Mask */
+#define SDMMC_MINTSTS_ACD_Pos 14 /*!< SDMMC MINTSTS: ACD Position */
+#define SDMMC_MINTSTS_ACD_Msk (0x01UL << SDMMC_MINTSTS_ACD_Pos) /*!< SDMMC MINTSTS: ACD Mask */
+#define SDMMC_MINTSTS_EBE_Pos 15 /*!< SDMMC MINTSTS: EBE Position */
+#define SDMMC_MINTSTS_EBE_Msk (0x01UL << SDMMC_MINTSTS_EBE_Pos) /*!< SDMMC MINTSTS: EBE Mask */
+#define SDMMC_MINTSTS_SDIO_INTERRUPT_Pos 16 /*!< SDMMC MINTSTS: SDIO_INTERRUPT Position */
+#define SDMMC_MINTSTS_SDIO_INTERRUPT_Msk (0x0000ffffUL << SDMMC_MINTSTS_SDIO_INTERRUPT_Pos) /*!< SDMMC MINTSTS: SDIO_INTERRUPT Mask */
+
+// -------------------------------------- SDMMC_RINTSTS -----------------------------------------
+#define SDMMC_RINTSTS_CDET_Pos 0 /*!< SDMMC RINTSTS: CDET Position */
+#define SDMMC_RINTSTS_CDET_Msk (0x01UL << SDMMC_RINTSTS_CDET_Pos) /*!< SDMMC RINTSTS: CDET Mask */
+#define SDMMC_RINTSTS_RE_Pos 1 /*!< SDMMC RINTSTS: RE Position */
+#define SDMMC_RINTSTS_RE_Msk (0x01UL << SDMMC_RINTSTS_RE_Pos) /*!< SDMMC RINTSTS: RE Mask */
+#define SDMMC_RINTSTS_CDONE_Pos 2 /*!< SDMMC RINTSTS: CDONE Position */
+#define SDMMC_RINTSTS_CDONE_Msk (0x01UL << SDMMC_RINTSTS_CDONE_Pos) /*!< SDMMC RINTSTS: CDONE Mask */
+#define SDMMC_RINTSTS_DTO_Pos 3 /*!< SDMMC RINTSTS: DTO Position */
+#define SDMMC_RINTSTS_DTO_Msk (0x01UL << SDMMC_RINTSTS_DTO_Pos) /*!< SDMMC RINTSTS: DTO Mask */
+#define SDMMC_RINTSTS_TXDR_Pos 4 /*!< SDMMC RINTSTS: TXDR Position */
+#define SDMMC_RINTSTS_TXDR_Msk (0x01UL << SDMMC_RINTSTS_TXDR_Pos) /*!< SDMMC RINTSTS: TXDR Mask */
+#define SDMMC_RINTSTS_RXDR_Pos 5 /*!< SDMMC RINTSTS: RXDR Position */
+#define SDMMC_RINTSTS_RXDR_Msk (0x01UL << SDMMC_RINTSTS_RXDR_Pos) /*!< SDMMC RINTSTS: RXDR Mask */
+#define SDMMC_RINTSTS_RCRC_Pos 6 /*!< SDMMC RINTSTS: RCRC Position */
+#define SDMMC_RINTSTS_RCRC_Msk (0x01UL << SDMMC_RINTSTS_RCRC_Pos) /*!< SDMMC RINTSTS: RCRC Mask */
+#define SDMMC_RINTSTS_DCRC_Pos 7 /*!< SDMMC RINTSTS: DCRC Position */
+#define SDMMC_RINTSTS_DCRC_Msk (0x01UL << SDMMC_RINTSTS_DCRC_Pos) /*!< SDMMC RINTSTS: DCRC Mask */
+#define SDMMC_RINTSTS_RTO_BAR_Pos 8 /*!< SDMMC RINTSTS: RTO_BAR Position */
+#define SDMMC_RINTSTS_RTO_BAR_Msk (0x01UL << SDMMC_RINTSTS_RTO_BAR_Pos) /*!< SDMMC RINTSTS: RTO_BAR Mask */
+#define SDMMC_RINTSTS_DRTO_BDS_Pos 9 /*!< SDMMC RINTSTS: DRTO_BDS Position */
+#define SDMMC_RINTSTS_DRTO_BDS_Msk (0x01UL << SDMMC_RINTSTS_DRTO_BDS_Pos) /*!< SDMMC RINTSTS: DRTO_BDS Mask */
+#define SDMMC_RINTSTS_HTO_Pos 10 /*!< SDMMC RINTSTS: HTO Position */
+#define SDMMC_RINTSTS_HTO_Msk (0x01UL << SDMMC_RINTSTS_HTO_Pos) /*!< SDMMC RINTSTS: HTO Mask */
+#define SDMMC_RINTSTS_FRUN_Pos 11 /*!< SDMMC RINTSTS: FRUN Position */
+#define SDMMC_RINTSTS_FRUN_Msk (0x01UL << SDMMC_RINTSTS_FRUN_Pos) /*!< SDMMC RINTSTS: FRUN Mask */
+#define SDMMC_RINTSTS_HLE_Pos 12 /*!< SDMMC RINTSTS: HLE Position */
+#define SDMMC_RINTSTS_HLE_Msk (0x01UL << SDMMC_RINTSTS_HLE_Pos) /*!< SDMMC RINTSTS: HLE Mask */
+#define SDMMC_RINTSTS_SBE_Pos 13 /*!< SDMMC RINTSTS: SBE Position */
+#define SDMMC_RINTSTS_SBE_Msk (0x01UL << SDMMC_RINTSTS_SBE_Pos) /*!< SDMMC RINTSTS: SBE Mask */
+#define SDMMC_RINTSTS_ACD_Pos 14 /*!< SDMMC RINTSTS: ACD Position */
+#define SDMMC_RINTSTS_ACD_Msk (0x01UL << SDMMC_RINTSTS_ACD_Pos) /*!< SDMMC RINTSTS: ACD Mask */
+#define SDMMC_RINTSTS_EBE_Pos 15 /*!< SDMMC RINTSTS: EBE Position */
+#define SDMMC_RINTSTS_EBE_Msk (0x01UL << SDMMC_RINTSTS_EBE_Pos) /*!< SDMMC RINTSTS: EBE Mask */
+#define SDMMC_RINTSTS_SDIO_INTERRUPT_Pos 16 /*!< SDMMC RINTSTS: SDIO_INTERRUPT Position */
+#define SDMMC_RINTSTS_SDIO_INTERRUPT_Msk (0x0000ffffUL << SDMMC_RINTSTS_SDIO_INTERRUPT_Pos) /*!< SDMMC RINTSTS: SDIO_INTERRUPT Mask */
+
+// -------------------------------------- SDMMC_STATUS ------------------------------------------
+#define SDMMC_STATUS_FIFO_RX_WATERMARK_Pos 0 /*!< SDMMC STATUS: FIFO_RX_WATERMARK Position */
+#define SDMMC_STATUS_FIFO_RX_WATERMARK_Msk (0x01UL << SDMMC_STATUS_FIFO_RX_WATERMARK_Pos) /*!< SDMMC STATUS: FIFO_RX_WATERMARK Mask */
+#define SDMMC_STATUS_FIFO_TX_WATERMARK_Pos 1 /*!< SDMMC STATUS: FIFO_TX_WATERMARK Position */
+#define SDMMC_STATUS_FIFO_TX_WATERMARK_Msk (0x01UL << SDMMC_STATUS_FIFO_TX_WATERMARK_Pos) /*!< SDMMC STATUS: FIFO_TX_WATERMARK Mask */
+#define SDMMC_STATUS_FIFO_EMPTY_Pos 2 /*!< SDMMC STATUS: FIFO_EMPTY Position */
+#define SDMMC_STATUS_FIFO_EMPTY_Msk (0x01UL << SDMMC_STATUS_FIFO_EMPTY_Pos) /*!< SDMMC STATUS: FIFO_EMPTY Mask */
+#define SDMMC_STATUS_FIFO_FULL_Pos 3 /*!< SDMMC STATUS: FIFO_FULL Position */
+#define SDMMC_STATUS_FIFO_FULL_Msk (0x01UL << SDMMC_STATUS_FIFO_FULL_Pos) /*!< SDMMC STATUS: FIFO_FULL Mask */
+#define SDMMC_STATUS_CMDFSMSTATES_Pos 4 /*!< SDMMC STATUS: CMDFSMSTATES Position */
+#define SDMMC_STATUS_CMDFSMSTATES_Msk (0x0fUL << SDMMC_STATUS_CMDFSMSTATES_Pos) /*!< SDMMC STATUS: CMDFSMSTATES Mask */
+#define SDMMC_STATUS_DATA_3_STATUS_Pos 8 /*!< SDMMC STATUS: DATA_3_STATUS Position */
+#define SDMMC_STATUS_DATA_3_STATUS_Msk (0x01UL << SDMMC_STATUS_DATA_3_STATUS_Pos) /*!< SDMMC STATUS: DATA_3_STATUS Mask */
+#define SDMMC_STATUS_DATA_BUSY_Pos 9 /*!< SDMMC STATUS: DATA_BUSY Position */
+#define SDMMC_STATUS_DATA_BUSY_Msk (0x01UL << SDMMC_STATUS_DATA_BUSY_Pos) /*!< SDMMC STATUS: DATA_BUSY Mask */
+#define SDMMC_STATUS_DATA_STATE_MC_BUSY_Pos 10 /*!< SDMMC STATUS: DATA_STATE_MC_BUSY Position */
+#define SDMMC_STATUS_DATA_STATE_MC_BUSY_Msk (0x01UL << SDMMC_STATUS_DATA_STATE_MC_BUSY_Pos) /*!< SDMMC STATUS: DATA_STATE_MC_BUSY Mask */
+#define SDMMC_STATUS_RESPONSE_INDEX_Pos 11 /*!< SDMMC STATUS: RESPONSE_INDEX Position */
+#define SDMMC_STATUS_RESPONSE_INDEX_Msk (0x3fUL << SDMMC_STATUS_RESPONSE_INDEX_Pos) /*!< SDMMC STATUS: RESPONSE_INDEX Mask */
+#define SDMMC_STATUS_FIFO_COUNT_Pos 17 /*!< SDMMC STATUS: FIFO_COUNT Position */
+#define SDMMC_STATUS_FIFO_COUNT_Msk (0x00001fffUL << SDMMC_STATUS_FIFO_COUNT_Pos) /*!< SDMMC STATUS: FIFO_COUNT Mask */
+#define SDMMC_STATUS_DMA_ACK_Pos 30 /*!< SDMMC STATUS: DMA_ACK Position */
+#define SDMMC_STATUS_DMA_ACK_Msk (0x01UL << SDMMC_STATUS_DMA_ACK_Pos) /*!< SDMMC STATUS: DMA_ACK Mask */
+#define SDMMC_STATUS_DMA_REQ_Pos 31 /*!< SDMMC STATUS: DMA_REQ Position */
+#define SDMMC_STATUS_DMA_REQ_Msk (0x01UL << SDMMC_STATUS_DMA_REQ_Pos) /*!< SDMMC STATUS: DMA_REQ Mask */
+
+// -------------------------------------- SDMMC_FIFOTH ------------------------------------------
+#define SDMMC_FIFOTH_TX_WMARK_Pos 0 /*!< SDMMC FIFOTH: TX_WMARK Position */
+#define SDMMC_FIFOTH_TX_WMARK_Msk (0x00000fffUL << SDMMC_FIFOTH_TX_WMARK_Pos) /*!< SDMMC FIFOTH: TX_WMARK Mask */
+#define SDMMC_FIFOTH_RX_WMARK_Pos 16 /*!< SDMMC FIFOTH: RX_WMARK Position */
+#define SDMMC_FIFOTH_RX_WMARK_Msk (0x00000fffUL << SDMMC_FIFOTH_RX_WMARK_Pos) /*!< SDMMC FIFOTH: RX_WMARK Mask */
+#define SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Pos 28 /*!< SDMMC FIFOTH: DW_DMA_MUTIPLE_TRANSACTION_SIZE Position */
+#define SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Msk (0x07UL << SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Pos)/*!< SDMMC FIFOTH: DW_DMA_MUTIPLE_TRANSACTION_SIZE Mask */
+
+// -------------------------------------- SDMMC_CDETECT -----------------------------------------
+#define SDMMC_CDETECT_CARD_DETECT_N_Pos 0 /*!< SDMMC CDETECT: CARD_DETECT_N Position */
+#define SDMMC_CDETECT_CARD_DETECT_N_Msk (0x3fffffffUL << SDMMC_CDETECT_CARD_DETECT_N_Pos) /*!< SDMMC CDETECT: CARD_DETECT_N Mask */
+
+// -------------------------------------- SDMMC_WRTPRT ------------------------------------------
+#define SDMMC_WRTPRT_WRITE_PROTECT_Pos 0 /*!< SDMMC WRTPRT: WRITE_PROTECT Position */
+#define SDMMC_WRTPRT_WRITE_PROTECT_Msk (0x3fffffffUL << SDMMC_WRTPRT_WRITE_PROTECT_Pos) /*!< SDMMC WRTPRT: WRITE_PROTECT Mask */
+
+// --------------------------------------- SDMMC_GPIO -------------------------------------------
+#define SDMMC_GPIO_GPI_Pos 0 /*!< SDMMC GPIO: GPI Position */
+#define SDMMC_GPIO_GPI_Msk (0x000000ffUL << SDMMC_GPIO_GPI_Pos) /*!< SDMMC GPIO: GPI Mask */
+#define SDMMC_GPIO_GPO_Pos 8 /*!< SDMMC GPIO: GPO Position */
+#define SDMMC_GPIO_GPO_Msk (0x0000ffffUL << SDMMC_GPIO_GPO_Pos) /*!< SDMMC GPIO: GPO Mask */
+
+// -------------------------------------- SDMMC_TCBCNT ------------------------------------------
+#define SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Pos 0 /*!< SDMMC TCBCNT: TRANS_CARD_BYTE_COUNT Position */
+#define SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Msk (0xffffffffUL << SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Pos) /*!< SDMMC TCBCNT: TRANS_CARD_BYTE_COUNT Mask */
+
+// -------------------------------------- SDMMC_TBBCNT ------------------------------------------
+#define SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Pos 0 /*!< SDMMC TBBCNT: TRANS_FIFO_BYTE_COUNT Position */
+#define SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Msk (0xffffffffUL << SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Pos) /*!< SDMMC TBBCNT: TRANS_FIFO_BYTE_COUNT Mask */
+
+// -------------------------------------- SDMMC_DEBNCE ------------------------------------------
+#define SDMMC_DEBNCE_DEBOUNCE_COUNT_Pos 0 /*!< SDMMC DEBNCE: DEBOUNCE_COUNT Position */
+#define SDMMC_DEBNCE_DEBOUNCE_COUNT_Msk (0x00ffffffUL << SDMMC_DEBNCE_DEBOUNCE_COUNT_Pos) /*!< SDMMC DEBNCE: DEBOUNCE_COUNT Mask */
+
+// --------------------------------------- SDMMC_USRID ------------------------------------------
+#define SDMMC_USRID_USRID_Pos 0 /*!< SDMMC USRID: USRID Position */
+#define SDMMC_USRID_USRID_Msk (0xffffffffUL << SDMMC_USRID_USRID_Pos) /*!< SDMMC USRID: USRID Mask */
+
+// --------------------------------------- SDMMC_VERID ------------------------------------------
+#define SDMMC_VERID_VERID_Pos 0 /*!< SDMMC VERID: VERID Position */
+#define SDMMC_VERID_VERID_Msk (0xffffffffUL << SDMMC_VERID_VERID_Pos) /*!< SDMMC VERID: VERID Mask */
+
+// -------------------------------------- SDMMC_UHS_REG -----------------------------------------
+#define SDMMC_UHS_REG_VOLT_REG_Pos 0 /*!< SDMMC UHS_REG: VOLT_REG Position */
+#define SDMMC_UHS_REG_VOLT_REG_Msk (0x0000ffffUL << SDMMC_UHS_REG_VOLT_REG_Pos) /*!< SDMMC UHS_REG: VOLT_REG Mask */
+#define SDMMC_UHS_REG_DDR_REG_Pos 16 /*!< SDMMC UHS_REG: DDR_REG Position */
+#define SDMMC_UHS_REG_DDR_REG_Msk (0x0000ffffUL << SDMMC_UHS_REG_DDR_REG_Pos) /*!< SDMMC UHS_REG: DDR_REG Mask */
+
+// --------------------------------------- SDMMC_RST_N ------------------------------------------
+#define SDMMC_RST_N_CARD_RESET_Pos 0 /*!< SDMMC RST_N: CARD_RESET Position */
+#define SDMMC_RST_N_CARD_RESET_Msk (0x0000ffffUL << SDMMC_RST_N_CARD_RESET_Pos) /*!< SDMMC RST_N: CARD_RESET Mask */
+
+// --------------------------------------- SDMMC_BMOD -------------------------------------------
+#define SDMMC_BMOD_SWR_Pos 0 /*!< SDMMC BMOD: SWR Position */
+#define SDMMC_BMOD_SWR_Msk (0x01UL << SDMMC_BMOD_SWR_Pos) /*!< SDMMC BMOD: SWR Mask */
+#define SDMMC_BMOD_FB_Pos 1 /*!< SDMMC BMOD: FB Position */
+#define SDMMC_BMOD_FB_Msk (0x01UL << SDMMC_BMOD_FB_Pos) /*!< SDMMC BMOD: FB Mask */
+#define SDMMC_BMOD_DSL_Pos 2 /*!< SDMMC BMOD: DSL Position */
+#define SDMMC_BMOD_DSL_Msk (0x1fUL << SDMMC_BMOD_DSL_Pos) /*!< SDMMC BMOD: DSL Mask */
+#define SDMMC_BMOD_DE_Pos 7 /*!< SDMMC BMOD: DE Position */
+#define SDMMC_BMOD_DE_Msk (0x01UL << SDMMC_BMOD_DE_Pos) /*!< SDMMC BMOD: DE Mask */
+#define SDMMC_BMOD_PBL_Pos 8 /*!< SDMMC BMOD: PBL Position */
+#define SDMMC_BMOD_PBL_Msk (0x07UL << SDMMC_BMOD_PBL_Pos) /*!< SDMMC BMOD: PBL Mask */
+
+// -------------------------------------- SDMMC_PLDMND ------------------------------------------
+#define SDMMC_PLDMND_PD_Pos 0 /*!< SDMMC PLDMND: PD Position */
+#define SDMMC_PLDMND_PD_Msk (0xffffffffUL << SDMMC_PLDMND_PD_Pos) /*!< SDMMC PLDMND: PD Mask */
+
+// -------------------------------------- SDMMC_DBADDR ------------------------------------------
+#define SDMMC_DBADDR_SDL_Pos 0 /*!< SDMMC DBADDR: SDL Position */
+#define SDMMC_DBADDR_SDL_Msk (0xffffffffUL << SDMMC_DBADDR_SDL_Pos) /*!< SDMMC DBADDR: SDL Mask */
+
+// --------------------------------------- SDMMC_IDSTS ------------------------------------------
+#define SDMMC_IDSTS_TI_Pos 0 /*!< SDMMC IDSTS: TI Position */
+#define SDMMC_IDSTS_TI_Msk (0x01UL << SDMMC_IDSTS_TI_Pos) /*!< SDMMC IDSTS: TI Mask */
+#define SDMMC_IDSTS_RI_Pos 1 /*!< SDMMC IDSTS: RI Position */
+#define SDMMC_IDSTS_RI_Msk (0x01UL << SDMMC_IDSTS_RI_Pos) /*!< SDMMC IDSTS: RI Mask */
+#define SDMMC_IDSTS_FBE_Pos 2 /*!< SDMMC IDSTS: FBE Position */
+#define SDMMC_IDSTS_FBE_Msk (0x01UL << SDMMC_IDSTS_FBE_Pos) /*!< SDMMC IDSTS: FBE Mask */
+#define SDMMC_IDSTS_DU_Pos 4 /*!< SDMMC IDSTS: DU Position */
+#define SDMMC_IDSTS_DU_Msk (0x01UL << SDMMC_IDSTS_DU_Pos) /*!< SDMMC IDSTS: DU Mask */
+#define SDMMC_IDSTS_CES_Pos 5 /*!< SDMMC IDSTS: CES Position */
+#define SDMMC_IDSTS_CES_Msk (0x01UL << SDMMC_IDSTS_CES_Pos) /*!< SDMMC IDSTS: CES Mask */
+#define SDMMC_IDSTS_NIS_Pos 8 /*!< SDMMC IDSTS: NIS Position */
+#define SDMMC_IDSTS_NIS_Msk (0x01UL << SDMMC_IDSTS_NIS_Pos) /*!< SDMMC IDSTS: NIS Mask */
+#define SDMMC_IDSTS_AIS_Pos 9 /*!< SDMMC IDSTS: AIS Position */
+#define SDMMC_IDSTS_AIS_Msk (0x01UL << SDMMC_IDSTS_AIS_Pos) /*!< SDMMC IDSTS: AIS Mask */
+#define SDMMC_IDSTS_EB_Pos 10 /*!< SDMMC IDSTS: EB Position */
+#define SDMMC_IDSTS_EB_Msk (0x07UL << SDMMC_IDSTS_EB_Pos) /*!< SDMMC IDSTS: EB Mask */
+#define SDMMC_IDSTS_FSM_Pos 13 /*!< SDMMC IDSTS: FSM Position */
+#define SDMMC_IDSTS_FSM_Msk (0x0fUL << SDMMC_IDSTS_FSM_Pos) /*!< SDMMC IDSTS: FSM Mask */
+
+// -------------------------------------- SDMMC_IDINTEN -----------------------------------------
+#define SDMMC_IDINTEN_TI_Pos 0 /*!< SDMMC IDINTEN: TI Position */
+#define SDMMC_IDINTEN_TI_Msk (0x01UL << SDMMC_IDINTEN_TI_Pos) /*!< SDMMC IDINTEN: TI Mask */
+#define SDMMC_IDINTEN_RI_Pos 1 /*!< SDMMC IDINTEN: RI Position */
+#define SDMMC_IDINTEN_RI_Msk (0x01UL << SDMMC_IDINTEN_RI_Pos) /*!< SDMMC IDINTEN: RI Mask */
+#define SDMMC_IDINTEN_FBE_Pos 2 /*!< SDMMC IDINTEN: FBE Position */
+#define SDMMC_IDINTEN_FBE_Msk (0x01UL << SDMMC_IDINTEN_FBE_Pos) /*!< SDMMC IDINTEN: FBE Mask */
+#define SDMMC_IDINTEN_DU_Pos 4 /*!< SDMMC IDINTEN: DU Position */
+#define SDMMC_IDINTEN_DU_Msk (0x01UL << SDMMC_IDINTEN_DU_Pos) /*!< SDMMC IDINTEN: DU Mask */
+#define SDMMC_IDINTEN_CES_Pos 5 /*!< SDMMC IDINTEN: CES Position */
+#define SDMMC_IDINTEN_CES_Msk (0x01UL << SDMMC_IDINTEN_CES_Pos) /*!< SDMMC IDINTEN: CES Mask */
+#define SDMMC_IDINTEN_NIS_Pos 8 /*!< SDMMC IDINTEN: NIS Position */
+#define SDMMC_IDINTEN_NIS_Msk (0x01UL << SDMMC_IDINTEN_NIS_Pos) /*!< SDMMC IDINTEN: NIS Mask */
+#define SDMMC_IDINTEN_AIS_Pos 9 /*!< SDMMC IDINTEN: AIS Position */
+#define SDMMC_IDINTEN_AIS_Msk (0x01UL << SDMMC_IDINTEN_AIS_Pos) /*!< SDMMC IDINTEN: AIS Mask */
+
+// -------------------------------------- SDMMC_DSCADDR -----------------------------------------
+#define SDMMC_DSCADDR_HDA_Pos 0 /*!< SDMMC DSCADDR: HDA Position */
+#define SDMMC_DSCADDR_HDA_Msk (0xffffffffUL << SDMMC_DSCADDR_HDA_Pos) /*!< SDMMC DSCADDR: HDA Mask */
+
+// -------------------------------------- SDMMC_BUFADDR -----------------------------------------
+#define SDMMC_BUFADDR_HBA_Pos 0 /*!< SDMMC BUFADDR: HBA Position */
+#define SDMMC_BUFADDR_HBA_Msk (0xffffffffUL << SDMMC_BUFADDR_HBA_Pos) /*!< SDMMC BUFADDR: HBA Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- EMC Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------- EMC_CONTROL ------------------------------------------
+#define EMC_CONTROL_E_Pos 0 /*!< EMC CONTROL: E Position */
+#define EMC_CONTROL_E_Msk (0x01UL << EMC_CONTROL_E_Pos) /*!< EMC CONTROL: E Mask */
+#define EMC_CONTROL_M_Pos 1 /*!< EMC CONTROL: M Position */
+#define EMC_CONTROL_M_Msk (0x01UL << EMC_CONTROL_M_Pos) /*!< EMC CONTROL: M Mask */
+#define EMC_CONTROL_L_Pos 2 /*!< EMC CONTROL: L Position */
+#define EMC_CONTROL_L_Msk (0x01UL << EMC_CONTROL_L_Pos) /*!< EMC CONTROL: L Mask */
+
+// --------------------------------------- EMC_STATUS -------------------------------------------
+#define EMC_STATUS_B_Pos 0 /*!< EMC STATUS: B Position */
+#define EMC_STATUS_B_Msk (0x01UL << EMC_STATUS_B_Pos) /*!< EMC STATUS: B Mask */
+#define EMC_STATUS_S_Pos 1 /*!< EMC STATUS: S Position */
+#define EMC_STATUS_S_Msk (0x01UL << EMC_STATUS_S_Pos) /*!< EMC STATUS: S Mask */
+#define EMC_STATUS_SA_Pos 2 /*!< EMC STATUS: SA Position */
+#define EMC_STATUS_SA_Msk (0x01UL << EMC_STATUS_SA_Pos) /*!< EMC STATUS: SA Mask */
+
+// --------------------------------------- EMC_CONFIG -------------------------------------------
+#define EMC_CONFIG_EM_Pos 0 /*!< EMC CONFIG: EM Position */
+#define EMC_CONFIG_EM_Msk (0x01UL << EMC_CONFIG_EM_Pos) /*!< EMC CONFIG: EM Mask */
+#define EMC_CONFIG_CR_Pos 8 /*!< EMC CONFIG: CR Position */
+#define EMC_CONFIG_CR_Msk (0x01UL << EMC_CONFIG_CR_Pos) /*!< EMC CONFIG: CR Mask */
+
+// ----------------------------------- EMC_DYNAMICCONTROL ---------------------------------------
+#define EMC_DYNAMICCONTROL_CE_Pos 0 /*!< EMC DYNAMICCONTROL: CE Position */
+#define EMC_DYNAMICCONTROL_CE_Msk (0x01UL << EMC_DYNAMICCONTROL_CE_Pos) /*!< EMC DYNAMICCONTROL: CE Mask */
+#define EMC_DYNAMICCONTROL_CS_Pos 1 /*!< EMC DYNAMICCONTROL: CS Position */
+#define EMC_DYNAMICCONTROL_CS_Msk (0x01UL << EMC_DYNAMICCONTROL_CS_Pos) /*!< EMC DYNAMICCONTROL: CS Mask */
+#define EMC_DYNAMICCONTROL_SR_Pos 2 /*!< EMC DYNAMICCONTROL: SR Position */
+#define EMC_DYNAMICCONTROL_SR_Msk (0x01UL << EMC_DYNAMICCONTROL_SR_Pos) /*!< EMC DYNAMICCONTROL: SR Mask */
+#define EMC_DYNAMICCONTROL_MMC_Pos 5 /*!< EMC DYNAMICCONTROL: MMC Position */
+#define EMC_DYNAMICCONTROL_MMC_Msk (0x01UL << EMC_DYNAMICCONTROL_MMC_Pos) /*!< EMC DYNAMICCONTROL: MMC Mask */
+#define EMC_DYNAMICCONTROL_I_Pos 7 /*!< EMC DYNAMICCONTROL: I Position */
+#define EMC_DYNAMICCONTROL_I_Msk (0x03UL << EMC_DYNAMICCONTROL_I_Pos) /*!< EMC DYNAMICCONTROL: I Mask */
+#define EMC_DYNAMICCONTROL_DP_Pos 13 /*!< EMC DYNAMICCONTROL: DP Position */
+#define EMC_DYNAMICCONTROL_DP_Msk (0x01UL << EMC_DYNAMICCONTROL_DP_Pos) /*!< EMC DYNAMICCONTROL: DP Mask */
+
+// ----------------------------------- EMC_DYNAMICREFRESH ---------------------------------------
+#define EMC_DYNAMICREFRESH_REFRESH_Pos 0 /*!< EMC DYNAMICREFRESH: REFRESH Position */
+#define EMC_DYNAMICREFRESH_REFRESH_Msk (0x000007ffUL << EMC_DYNAMICREFRESH_REFRESH_Pos) /*!< EMC DYNAMICREFRESH: REFRESH Mask */
+
+// ---------------------------------- EMC_DYNAMICREADCONFIG -------------------------------------
+#define EMC_DYNAMICREADCONFIG_RD_Pos 0 /*!< EMC DYNAMICREADCONFIG: RD Position */
+#define EMC_DYNAMICREADCONFIG_RD_Msk (0x03UL << EMC_DYNAMICREADCONFIG_RD_Pos) /*!< EMC DYNAMICREADCONFIG: RD Mask */
+
+// -------------------------------------- EMC_DYNAMICRP -----------------------------------------
+#define EMC_DYNAMICRP_tRP_Pos 0 /*!< EMC DYNAMICRP: tRP Position */
+#define EMC_DYNAMICRP_tRP_Msk (0x0fUL << EMC_DYNAMICRP_tRP_Pos) /*!< EMC DYNAMICRP: tRP Mask */
+
+// ------------------------------------- EMC_DYNAMICRAS -----------------------------------------
+#define EMC_DYNAMICRAS_tRAS_Pos 0 /*!< EMC DYNAMICRAS: tRAS Position */
+#define EMC_DYNAMICRAS_tRAS_Msk (0x0fUL << EMC_DYNAMICRAS_tRAS_Pos) /*!< EMC DYNAMICRAS: tRAS Mask */
+
+// ------------------------------------- EMC_DYNAMICSREX ----------------------------------------
+#define EMC_DYNAMICSREX_tSREX_Pos 0 /*!< EMC DYNAMICSREX: tSREX Position */
+#define EMC_DYNAMICSREX_tSREX_Msk (0x0fUL << EMC_DYNAMICSREX_tSREX_Pos) /*!< EMC DYNAMICSREX: tSREX Mask */
+
+// ------------------------------------- EMC_DYNAMICAPR -----------------------------------------
+#define EMC_DYNAMICAPR_tAPR_Pos 0 /*!< EMC DYNAMICAPR: tAPR Position */
+#define EMC_DYNAMICAPR_tAPR_Msk (0x0fUL << EMC_DYNAMICAPR_tAPR_Pos) /*!< EMC DYNAMICAPR: tAPR Mask */
+
+// ------------------------------------- EMC_DYNAMICDAL -----------------------------------------
+#define EMC_DYNAMICDAL_tDAL_Pos 0 /*!< EMC DYNAMICDAL: tDAL Position */
+#define EMC_DYNAMICDAL_tDAL_Msk (0x0fUL << EMC_DYNAMICDAL_tDAL_Pos) /*!< EMC DYNAMICDAL: tDAL Mask */
+
+// -------------------------------------- EMC_DYNAMICWR -----------------------------------------
+#define EMC_DYNAMICWR_tWR_Pos 0 /*!< EMC DYNAMICWR: tWR Position */
+#define EMC_DYNAMICWR_tWR_Msk (0x0fUL << EMC_DYNAMICWR_tWR_Pos) /*!< EMC DYNAMICWR: tWR Mask */
+
+// -------------------------------------- EMC_DYNAMICRC -----------------------------------------
+#define EMC_DYNAMICRC_tRC_Pos 0 /*!< EMC DYNAMICRC: tRC Position */
+#define EMC_DYNAMICRC_tRC_Msk (0x1fUL << EMC_DYNAMICRC_tRC_Pos) /*!< EMC DYNAMICRC: tRC Mask */
+
+// ------------------------------------- EMC_DYNAMICRFC -----------------------------------------
+#define EMC_DYNAMICRFC_tRFC_Pos 0 /*!< EMC DYNAMICRFC: tRFC Position */
+#define EMC_DYNAMICRFC_tRFC_Msk (0x1fUL << EMC_DYNAMICRFC_tRFC_Pos) /*!< EMC DYNAMICRFC: tRFC Mask */
+
+// ------------------------------------- EMC_DYNAMICXSR -----------------------------------------
+#define EMC_DYNAMICXSR_tXSR_Pos 0 /*!< EMC DYNAMICXSR: tXSR Position */
+#define EMC_DYNAMICXSR_tXSR_Msk (0x1fUL << EMC_DYNAMICXSR_tXSR_Pos) /*!< EMC DYNAMICXSR: tXSR Mask */
+
+// ------------------------------------- EMC_DYNAMICRRD -----------------------------------------
+#define EMC_DYNAMICRRD_tRRD_Pos 0 /*!< EMC DYNAMICRRD: tRRD Position */
+#define EMC_DYNAMICRRD_tRRD_Msk (0x0fUL << EMC_DYNAMICRRD_tRRD_Pos) /*!< EMC DYNAMICRRD: tRRD Mask */
+
+// ------------------------------------- EMC_DYNAMICMRD -----------------------------------------
+#define EMC_DYNAMICMRD_tMRD_Pos 0 /*!< EMC DYNAMICMRD: tMRD Position */
+#define EMC_DYNAMICMRD_tMRD_Msk (0x0fUL << EMC_DYNAMICMRD_tMRD_Pos) /*!< EMC DYNAMICMRD: tMRD Mask */
+
+// --------------------------------- EMC_STATICEXTENDEDWAIT -------------------------------------
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Pos 0 /*!< EMC STATICEXTENDEDWAIT: EXTENDEDWAIT Position */
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Msk (0x000003ffUL << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Pos) /*!< EMC STATICEXTENDEDWAIT: EXTENDEDWAIT Mask */
+
+// ----------------------------------- EMC_DYNAMICCONFIG0 ---------------------------------------
+#define EMC_DYNAMICCONFIG0_MD_Pos 3 /*!< EMC DYNAMICCONFIG0: MD Position */
+#define EMC_DYNAMICCONFIG0_MD_Msk (0x03UL << EMC_DYNAMICCONFIG0_MD_Pos) /*!< EMC DYNAMICCONFIG0: MD Mask */
+#define EMC_DYNAMICCONFIG0_AM0_Pos 7 /*!< EMC DYNAMICCONFIG0: AM0 Position */
+#define EMC_DYNAMICCONFIG0_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG0_AM0_Pos) /*!< EMC DYNAMICCONFIG0: AM0 Mask */
+#define EMC_DYNAMICCONFIG0_AM1_Pos 14 /*!< EMC DYNAMICCONFIG0: AM1 Position */
+#define EMC_DYNAMICCONFIG0_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG0_AM1_Pos) /*!< EMC DYNAMICCONFIG0: AM1 Mask */
+#define EMC_DYNAMICCONFIG0_B_Pos 19 /*!< EMC DYNAMICCONFIG0: B Position */
+#define EMC_DYNAMICCONFIG0_B_Msk (0x01UL << EMC_DYNAMICCONFIG0_B_Pos) /*!< EMC DYNAMICCONFIG0: B Mask */
+#define EMC_DYNAMICCONFIG0_P_Pos 20 /*!< EMC DYNAMICCONFIG0: P Position */
+#define EMC_DYNAMICCONFIG0_P_Msk (0x01UL << EMC_DYNAMICCONFIG0_P_Pos) /*!< EMC DYNAMICCONFIG0: P Mask */
+
+// ----------------------------------- EMC_DYNAMICRASCAS0 ---------------------------------------
+#define EMC_DYNAMICRASCAS0_RAS_Pos 0 /*!< EMC DYNAMICRASCAS0: RAS Position */
+#define EMC_DYNAMICRASCAS0_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS0_RAS_Pos) /*!< EMC DYNAMICRASCAS0: RAS Mask */
+#define EMC_DYNAMICRASCAS0_CAS_Pos 8 /*!< EMC DYNAMICRASCAS0: CAS Position */
+#define EMC_DYNAMICRASCAS0_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS0_CAS_Pos) /*!< EMC DYNAMICRASCAS0: CAS Mask */
+
+// ----------------------------------- EMC_DYNAMICCONFIG1 ---------------------------------------
+#define EMC_DYNAMICCONFIG1_MD_Pos 3 /*!< EMC DYNAMICCONFIG1: MD Position */
+#define EMC_DYNAMICCONFIG1_MD_Msk (0x03UL << EMC_DYNAMICCONFIG1_MD_Pos) /*!< EMC DYNAMICCONFIG1: MD Mask */
+#define EMC_DYNAMICCONFIG1_AM0_Pos 7 /*!< EMC DYNAMICCONFIG1: AM0 Position */
+#define EMC_DYNAMICCONFIG1_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG1_AM0_Pos) /*!< EMC DYNAMICCONFIG1: AM0 Mask */
+#define EMC_DYNAMICCONFIG1_AM1_Pos 14 /*!< EMC DYNAMICCONFIG1: AM1 Position */
+#define EMC_DYNAMICCONFIG1_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG1_AM1_Pos) /*!< EMC DYNAMICCONFIG1: AM1 Mask */
+#define EMC_DYNAMICCONFIG1_B_Pos 19 /*!< EMC DYNAMICCONFIG1: B Position */
+#define EMC_DYNAMICCONFIG1_B_Msk (0x01UL << EMC_DYNAMICCONFIG1_B_Pos) /*!< EMC DYNAMICCONFIG1: B Mask */
+#define EMC_DYNAMICCONFIG1_P_Pos 20 /*!< EMC DYNAMICCONFIG1: P Position */
+#define EMC_DYNAMICCONFIG1_P_Msk (0x01UL << EMC_DYNAMICCONFIG1_P_Pos) /*!< EMC DYNAMICCONFIG1: P Mask */
+
+// ----------------------------------- EMC_DYNAMICRASCAS1 ---------------------------------------
+#define EMC_DYNAMICRASCAS1_RAS_Pos 0 /*!< EMC DYNAMICRASCAS1: RAS Position */
+#define EMC_DYNAMICRASCAS1_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS1_RAS_Pos) /*!< EMC DYNAMICRASCAS1: RAS Mask */
+#define EMC_DYNAMICRASCAS1_CAS_Pos 8 /*!< EMC DYNAMICRASCAS1: CAS Position */
+#define EMC_DYNAMICRASCAS1_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS1_CAS_Pos) /*!< EMC DYNAMICRASCAS1: CAS Mask */
+
+// ----------------------------------- EMC_DYNAMICCONFIG2 ---------------------------------------
+#define EMC_DYNAMICCONFIG2_MD_Pos 3 /*!< EMC DYNAMICCONFIG2: MD Position */
+#define EMC_DYNAMICCONFIG2_MD_Msk (0x03UL << EMC_DYNAMICCONFIG2_MD_Pos) /*!< EMC DYNAMICCONFIG2: MD Mask */
+#define EMC_DYNAMICCONFIG2_AM0_Pos 7 /*!< EMC DYNAMICCONFIG2: AM0 Position */
+#define EMC_DYNAMICCONFIG2_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG2_AM0_Pos) /*!< EMC DYNAMICCONFIG2: AM0 Mask */
+#define EMC_DYNAMICCONFIG2_AM1_Pos 14 /*!< EMC DYNAMICCONFIG2: AM1 Position */
+#define EMC_DYNAMICCONFIG2_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG2_AM1_Pos) /*!< EMC DYNAMICCONFIG2: AM1 Mask */
+#define EMC_DYNAMICCONFIG2_B_Pos 19 /*!< EMC DYNAMICCONFIG2: B Position */
+#define EMC_DYNAMICCONFIG2_B_Msk (0x01UL << EMC_DYNAMICCONFIG2_B_Pos) /*!< EMC DYNAMICCONFIG2: B Mask */
+#define EMC_DYNAMICCONFIG2_P_Pos 20 /*!< EMC DYNAMICCONFIG2: P Position */
+#define EMC_DYNAMICCONFIG2_P_Msk (0x01UL << EMC_DYNAMICCONFIG2_P_Pos) /*!< EMC DYNAMICCONFIG2: P Mask */
+
+// ----------------------------------- EMC_DYNAMICRASCAS2 ---------------------------------------
+#define EMC_DYNAMICRASCAS2_RAS_Pos 0 /*!< EMC DYNAMICRASCAS2: RAS Position */
+#define EMC_DYNAMICRASCAS2_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS2_RAS_Pos) /*!< EMC DYNAMICRASCAS2: RAS Mask */
+#define EMC_DYNAMICRASCAS2_CAS_Pos 8 /*!< EMC DYNAMICRASCAS2: CAS Position */
+#define EMC_DYNAMICRASCAS2_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS2_CAS_Pos) /*!< EMC DYNAMICRASCAS2: CAS Mask */
+
+// ----------------------------------- EMC_DYNAMICCONFIG3 ---------------------------------------
+#define EMC_DYNAMICCONFIG3_MD_Pos 3 /*!< EMC DYNAMICCONFIG3: MD Position */
+#define EMC_DYNAMICCONFIG3_MD_Msk (0x03UL << EMC_DYNAMICCONFIG3_MD_Pos) /*!< EMC DYNAMICCONFIG3: MD Mask */
+#define EMC_DYNAMICCONFIG3_AM0_Pos 7 /*!< EMC DYNAMICCONFIG3: AM0 Position */
+#define EMC_DYNAMICCONFIG3_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG3_AM0_Pos) /*!< EMC DYNAMICCONFIG3: AM0 Mask */
+#define EMC_DYNAMICCONFIG3_AM1_Pos 14 /*!< EMC DYNAMICCONFIG3: AM1 Position */
+#define EMC_DYNAMICCONFIG3_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG3_AM1_Pos) /*!< EMC DYNAMICCONFIG3: AM1 Mask */
+#define EMC_DYNAMICCONFIG3_B_Pos 19 /*!< EMC DYNAMICCONFIG3: B Position */
+#define EMC_DYNAMICCONFIG3_B_Msk (0x01UL << EMC_DYNAMICCONFIG3_B_Pos) /*!< EMC DYNAMICCONFIG3: B Mask */
+#define EMC_DYNAMICCONFIG3_P_Pos 20 /*!< EMC DYNAMICCONFIG3: P Position */
+#define EMC_DYNAMICCONFIG3_P_Msk (0x01UL << EMC_DYNAMICCONFIG3_P_Pos) /*!< EMC DYNAMICCONFIG3: P Mask */
+
+// ----------------------------------- EMC_DYNAMICRASCAS3 ---------------------------------------
+#define EMC_DYNAMICRASCAS3_RAS_Pos 0 /*!< EMC DYNAMICRASCAS3: RAS Position */
+#define EMC_DYNAMICRASCAS3_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS3_RAS_Pos) /*!< EMC DYNAMICRASCAS3: RAS Mask */
+#define EMC_DYNAMICRASCAS3_CAS_Pos 8 /*!< EMC DYNAMICRASCAS3: CAS Position */
+#define EMC_DYNAMICRASCAS3_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS3_CAS_Pos) /*!< EMC DYNAMICRASCAS3: CAS Mask */
+
+// ------------------------------------ EMC_STATICCONFIG0 ---------------------------------------
+#define EMC_STATICCONFIG0_MW_Pos 0 /*!< EMC STATICCONFIG0: MW Position */
+#define EMC_STATICCONFIG0_MW_Msk (0x03UL << EMC_STATICCONFIG0_MW_Pos) /*!< EMC STATICCONFIG0: MW Mask */
+#define EMC_STATICCONFIG0_PM_Pos 3 /*!< EMC STATICCONFIG0: PM Position */
+#define EMC_STATICCONFIG0_PM_Msk (0x01UL << EMC_STATICCONFIG0_PM_Pos) /*!< EMC STATICCONFIG0: PM Mask */
+#define EMC_STATICCONFIG0_PC_Pos 6 /*!< EMC STATICCONFIG0: PC Position */
+#define EMC_STATICCONFIG0_PC_Msk (0x01UL << EMC_STATICCONFIG0_PC_Pos) /*!< EMC STATICCONFIG0: PC Mask */
+#define EMC_STATICCONFIG0_PB_Pos 7 /*!< EMC STATICCONFIG0: PB Position */
+#define EMC_STATICCONFIG0_PB_Msk (0x01UL << EMC_STATICCONFIG0_PB_Pos) /*!< EMC STATICCONFIG0: PB Mask */
+#define EMC_STATICCONFIG0_EW_Pos 8 /*!< EMC STATICCONFIG0: EW Position */
+#define EMC_STATICCONFIG0_EW_Msk (0x01UL << EMC_STATICCONFIG0_EW_Pos) /*!< EMC STATICCONFIG0: EW Mask */
+#define EMC_STATICCONFIG0_B_Pos 19 /*!< EMC STATICCONFIG0: B Position */
+#define EMC_STATICCONFIG0_B_Msk (0x01UL << EMC_STATICCONFIG0_B_Pos) /*!< EMC STATICCONFIG0: B Mask */
+#define EMC_STATICCONFIG0_P_Pos 20 /*!< EMC STATICCONFIG0: P Position */
+#define EMC_STATICCONFIG0_P_Msk (0x01UL << EMC_STATICCONFIG0_P_Pos) /*!< EMC STATICCONFIG0: P Mask */
+
+// ----------------------------------- EMC_STATICWAITWEN0 ---------------------------------------
+#define EMC_STATICWAITWEN0_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN0: WAITWEN Position */
+#define EMC_STATICWAITWEN0_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN0_WAITWEN_Pos) /*!< EMC STATICWAITWEN0: WAITWEN Mask */
+
+// ----------------------------------- EMC_STATICWAITOEN0 ---------------------------------------
+#define EMC_STATICWAITOEN0_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN0: WAITOEN Position */
+#define EMC_STATICWAITOEN0_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN0_WAITOEN_Pos) /*!< EMC STATICWAITOEN0: WAITOEN Mask */
+
+// ------------------------------------ EMC_STATICWAITRD0 ---------------------------------------
+#define EMC_STATICWAITRD0_WAITRD_Pos 0 /*!< EMC STATICWAITRD0: WAITRD Position */
+#define EMC_STATICWAITRD0_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD0_WAITRD_Pos) /*!< EMC STATICWAITRD0: WAITRD Mask */
+
+// ----------------------------------- EMC_STATICWAITPAG0 ---------------------------------------
+#define EMC_STATICWAITPAG0_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAG0: WAITPAGE Position */
+#define EMC_STATICWAITPAG0_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAG0_WAITPAGE_Pos) /*!< EMC STATICWAITPAG0: WAITPAGE Mask */
+
+// ------------------------------------ EMC_STATICWAITWR0 ---------------------------------------
+#define EMC_STATICWAITWR0_WAITWR_Pos 0 /*!< EMC STATICWAITWR0: WAITWR Position */
+#define EMC_STATICWAITWR0_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR0_WAITWR_Pos) /*!< EMC STATICWAITWR0: WAITWR Mask */
+
+// ----------------------------------- EMC_STATICWAITTURN0 --------------------------------------
+#define EMC_STATICWAITTURN0_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN0: WAITTURN Position */
+#define EMC_STATICWAITTURN0_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN0_WAITTURN_Pos) /*!< EMC STATICWAITTURN0: WAITTURN Mask */
+
+// ------------------------------------ EMC_STATICCONFIG1 ---------------------------------------
+#define EMC_STATICCONFIG1_MW_Pos 0 /*!< EMC STATICCONFIG1: MW Position */
+#define EMC_STATICCONFIG1_MW_Msk (0x03UL << EMC_STATICCONFIG1_MW_Pos) /*!< EMC STATICCONFIG1: MW Mask */
+#define EMC_STATICCONFIG1_PM_Pos 3 /*!< EMC STATICCONFIG1: PM Position */
+#define EMC_STATICCONFIG1_PM_Msk (0x01UL << EMC_STATICCONFIG1_PM_Pos) /*!< EMC STATICCONFIG1: PM Mask */
+#define EMC_STATICCONFIG1_PC_Pos 6 /*!< EMC STATICCONFIG1: PC Position */
+#define EMC_STATICCONFIG1_PC_Msk (0x01UL << EMC_STATICCONFIG1_PC_Pos) /*!< EMC STATICCONFIG1: PC Mask */
+#define EMC_STATICCONFIG1_PB_Pos 7 /*!< EMC STATICCONFIG1: PB Position */
+#define EMC_STATICCONFIG1_PB_Msk (0x01UL << EMC_STATICCONFIG1_PB_Pos) /*!< EMC STATICCONFIG1: PB Mask */
+#define EMC_STATICCONFIG1_EW_Pos 8 /*!< EMC STATICCONFIG1: EW Position */
+#define EMC_STATICCONFIG1_EW_Msk (0x01UL << EMC_STATICCONFIG1_EW_Pos) /*!< EMC STATICCONFIG1: EW Mask */
+#define EMC_STATICCONFIG1_B_Pos 19 /*!< EMC STATICCONFIG1: B Position */
+#define EMC_STATICCONFIG1_B_Msk (0x01UL << EMC_STATICCONFIG1_B_Pos) /*!< EMC STATICCONFIG1: B Mask */
+#define EMC_STATICCONFIG1_P_Pos 20 /*!< EMC STATICCONFIG1: P Position */
+#define EMC_STATICCONFIG1_P_Msk (0x01UL << EMC_STATICCONFIG1_P_Pos) /*!< EMC STATICCONFIG1: P Mask */
+
+// ----------------------------------- EMC_STATICWAITWEN1 ---------------------------------------
+#define EMC_STATICWAITWEN1_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN1: WAITWEN Position */
+#define EMC_STATICWAITWEN1_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN1_WAITWEN_Pos) /*!< EMC STATICWAITWEN1: WAITWEN Mask */
+
+// ----------------------------------- EMC_STATICWAITOEN1 ---------------------------------------
+#define EMC_STATICWAITOEN1_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN1: WAITOEN Position */
+#define EMC_STATICWAITOEN1_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN1_WAITOEN_Pos) /*!< EMC STATICWAITOEN1: WAITOEN Mask */
+
+// ------------------------------------ EMC_STATICWAITRD1 ---------------------------------------
+#define EMC_STATICWAITRD1_WAITRD_Pos 0 /*!< EMC STATICWAITRD1: WAITRD Position */
+#define EMC_STATICWAITRD1_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD1_WAITRD_Pos) /*!< EMC STATICWAITRD1: WAITRD Mask */
+
+// ----------------------------------- EMC_STATICWAITPAG1 ---------------------------------------
+#define EMC_STATICWAITPAG1_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAG1: WAITPAGE Position */
+#define EMC_STATICWAITPAG1_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAG1_WAITPAGE_Pos) /*!< EMC STATICWAITPAG1: WAITPAGE Mask */
+
+// ------------------------------------ EMC_STATICWAITWR1 ---------------------------------------
+#define EMC_STATICWAITWR1_WAITWR_Pos 0 /*!< EMC STATICWAITWR1: WAITWR Position */
+#define EMC_STATICWAITWR1_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR1_WAITWR_Pos) /*!< EMC STATICWAITWR1: WAITWR Mask */
+
+// ----------------------------------- EMC_STATICWAITTURN1 --------------------------------------
+#define EMC_STATICWAITTURN1_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN1: WAITTURN Position */
+#define EMC_STATICWAITTURN1_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN1_WAITTURN_Pos) /*!< EMC STATICWAITTURN1: WAITTURN Mask */
+
+// ------------------------------------ EMC_STATICCONFIG2 ---------------------------------------
+#define EMC_STATICCONFIG2_MW_Pos 0 /*!< EMC STATICCONFIG2: MW Position */
+#define EMC_STATICCONFIG2_MW_Msk (0x03UL << EMC_STATICCONFIG2_MW_Pos) /*!< EMC STATICCONFIG2: MW Mask */
+#define EMC_STATICCONFIG2_PM_Pos 3 /*!< EMC STATICCONFIG2: PM Position */
+#define EMC_STATICCONFIG2_PM_Msk (0x01UL << EMC_STATICCONFIG2_PM_Pos) /*!< EMC STATICCONFIG2: PM Mask */
+#define EMC_STATICCONFIG2_PC_Pos 6 /*!< EMC STATICCONFIG2: PC Position */
+#define EMC_STATICCONFIG2_PC_Msk (0x01UL << EMC_STATICCONFIG2_PC_Pos) /*!< EMC STATICCONFIG2: PC Mask */
+#define EMC_STATICCONFIG2_PB_Pos 7 /*!< EMC STATICCONFIG2: PB Position */
+#define EMC_STATICCONFIG2_PB_Msk (0x01UL << EMC_STATICCONFIG2_PB_Pos) /*!< EMC STATICCONFIG2: PB Mask */
+#define EMC_STATICCONFIG2_EW_Pos 8 /*!< EMC STATICCONFIG2: EW Position */
+#define EMC_STATICCONFIG2_EW_Msk (0x01UL << EMC_STATICCONFIG2_EW_Pos) /*!< EMC STATICCONFIG2: EW Mask */
+#define EMC_STATICCONFIG2_B_Pos 19 /*!< EMC STATICCONFIG2: B Position */
+#define EMC_STATICCONFIG2_B_Msk (0x01UL << EMC_STATICCONFIG2_B_Pos) /*!< EMC STATICCONFIG2: B Mask */
+#define EMC_STATICCONFIG2_P_Pos 20 /*!< EMC STATICCONFIG2: P Position */
+#define EMC_STATICCONFIG2_P_Msk (0x01UL << EMC_STATICCONFIG2_P_Pos) /*!< EMC STATICCONFIG2: P Mask */
+
+// ----------------------------------- EMC_STATICWAITWEN2 ---------------------------------------
+#define EMC_STATICWAITWEN2_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN2: WAITWEN Position */
+#define EMC_STATICWAITWEN2_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN2_WAITWEN_Pos) /*!< EMC STATICWAITWEN2: WAITWEN Mask */
+
+// ----------------------------------- EMC_STATICWAITOEN2 ---------------------------------------
+#define EMC_STATICWAITOEN2_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN2: WAITOEN Position */
+#define EMC_STATICWAITOEN2_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN2_WAITOEN_Pos) /*!< EMC STATICWAITOEN2: WAITOEN Mask */
+
+// ------------------------------------ EMC_STATICWAITRD2 ---------------------------------------
+#define EMC_STATICWAITRD2_WAITRD_Pos 0 /*!< EMC STATICWAITRD2: WAITRD Position */
+#define EMC_STATICWAITRD2_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD2_WAITRD_Pos) /*!< EMC STATICWAITRD2: WAITRD Mask */
+
+// ----------------------------------- EMC_STATICWAITPAG2 ---------------------------------------
+#define EMC_STATICWAITPAG2_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAG2: WAITPAGE Position */
+#define EMC_STATICWAITPAG2_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAG2_WAITPAGE_Pos) /*!< EMC STATICWAITPAG2: WAITPAGE Mask */
+
+// ------------------------------------ EMC_STATICWAITWR2 ---------------------------------------
+#define EMC_STATICWAITWR2_WAITWR_Pos 0 /*!< EMC STATICWAITWR2: WAITWR Position */
+#define EMC_STATICWAITWR2_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR2_WAITWR_Pos) /*!< EMC STATICWAITWR2: WAITWR Mask */
+
+// ----------------------------------- EMC_STATICWAITTURN2 --------------------------------------
+#define EMC_STATICWAITTURN2_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN2: WAITTURN Position */
+#define EMC_STATICWAITTURN2_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN2_WAITTURN_Pos) /*!< EMC STATICWAITTURN2: WAITTURN Mask */
+
+// ------------------------------------ EMC_STATICCONFIG3 ---------------------------------------
+#define EMC_STATICCONFIG3_MW_Pos 0 /*!< EMC STATICCONFIG3: MW Position */
+#define EMC_STATICCONFIG3_MW_Msk (0x03UL << EMC_STATICCONFIG3_MW_Pos) /*!< EMC STATICCONFIG3: MW Mask */
+#define EMC_STATICCONFIG3_PM_Pos 3 /*!< EMC STATICCONFIG3: PM Position */
+#define EMC_STATICCONFIG3_PM_Msk (0x01UL << EMC_STATICCONFIG3_PM_Pos) /*!< EMC STATICCONFIG3: PM Mask */
+#define EMC_STATICCONFIG3_PC_Pos 6 /*!< EMC STATICCONFIG3: PC Position */
+#define EMC_STATICCONFIG3_PC_Msk (0x01UL << EMC_STATICCONFIG3_PC_Pos) /*!< EMC STATICCONFIG3: PC Mask */
+#define EMC_STATICCONFIG3_PB_Pos 7 /*!< EMC STATICCONFIG3: PB Position */
+#define EMC_STATICCONFIG3_PB_Msk (0x01UL << EMC_STATICCONFIG3_PB_Pos) /*!< EMC STATICCONFIG3: PB Mask */
+#define EMC_STATICCONFIG3_EW_Pos 8 /*!< EMC STATICCONFIG3: EW Position */
+#define EMC_STATICCONFIG3_EW_Msk (0x01UL << EMC_STATICCONFIG3_EW_Pos) /*!< EMC STATICCONFIG3: EW Mask */
+#define EMC_STATICCONFIG3_B_Pos 19 /*!< EMC STATICCONFIG3: B Position */
+#define EMC_STATICCONFIG3_B_Msk (0x01UL << EMC_STATICCONFIG3_B_Pos) /*!< EMC STATICCONFIG3: B Mask */
+#define EMC_STATICCONFIG3_P_Pos 20 /*!< EMC STATICCONFIG3: P Position */
+#define EMC_STATICCONFIG3_P_Msk (0x01UL << EMC_STATICCONFIG3_P_Pos) /*!< EMC STATICCONFIG3: P Mask */
+
+// ----------------------------------- EMC_STATICWAITWEN3 ---------------------------------------
+#define EMC_STATICWAITWEN3_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN3: WAITWEN Position */
+#define EMC_STATICWAITWEN3_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN3_WAITWEN_Pos) /*!< EMC STATICWAITWEN3: WAITWEN Mask */
+
+// ----------------------------------- EMC_STATICWAITOEN3 ---------------------------------------
+#define EMC_STATICWAITOEN3_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN3: WAITOEN Position */
+#define EMC_STATICWAITOEN3_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN3_WAITOEN_Pos) /*!< EMC STATICWAITOEN3: WAITOEN Mask */
+
+// ------------------------------------ EMC_STATICWAITRD3 ---------------------------------------
+#define EMC_STATICWAITRD3_WAITRD_Pos 0 /*!< EMC STATICWAITRD3: WAITRD Position */
+#define EMC_STATICWAITRD3_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD3_WAITRD_Pos) /*!< EMC STATICWAITRD3: WAITRD Mask */
+
+// ----------------------------------- EMC_STATICWAITPAG3 ---------------------------------------
+#define EMC_STATICWAITPAG3_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAG3: WAITPAGE Position */
+#define EMC_STATICWAITPAG3_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAG3_WAITPAGE_Pos) /*!< EMC STATICWAITPAG3: WAITPAGE Mask */
+
+// ------------------------------------ EMC_STATICWAITWR3 ---------------------------------------
+#define EMC_STATICWAITWR3_WAITWR_Pos 0 /*!< EMC STATICWAITWR3: WAITWR Position */
+#define EMC_STATICWAITWR3_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR3_WAITWR_Pos) /*!< EMC STATICWAITWR3: WAITWR Mask */
+
+// ----------------------------------- EMC_STATICWAITTURN3 --------------------------------------
+#define EMC_STATICWAITTURN3_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN3: WAITTURN Position */
+#define EMC_STATICWAITTURN3_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN3_WAITTURN_Pos) /*!< EMC STATICWAITTURN3: WAITTURN Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USB0 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ------------------------------------- USB0_CAPLENGTH -----------------------------------------
+#define USB0_CAPLENGTH_CAPLENGTH_Pos 0 /*!< USB0 CAPLENGTH: CAPLENGTH Position */
+#define USB0_CAPLENGTH_CAPLENGTH_Msk (0x000000ffUL << USB0_CAPLENGTH_CAPLENGTH_Pos) /*!< USB0 CAPLENGTH: CAPLENGTH Mask */
+#define USB0_CAPLENGTH_HCIVERSION_Pos 8 /*!< USB0 CAPLENGTH: HCIVERSION Position */
+#define USB0_CAPLENGTH_HCIVERSION_Msk (0x0000ffffUL << USB0_CAPLENGTH_HCIVERSION_Pos) /*!< USB0 CAPLENGTH: HCIVERSION Mask */
+
+// ------------------------------------- USB0_HCSPARAMS -----------------------------------------
+#define USB0_HCSPARAMS_N_PORTS_Pos 0 /*!< USB0 HCSPARAMS: N_PORTS Position */
+#define USB0_HCSPARAMS_N_PORTS_Msk (0x0fUL << USB0_HCSPARAMS_N_PORTS_Pos) /*!< USB0 HCSPARAMS: N_PORTS Mask */
+#define USB0_HCSPARAMS_PPC_Pos 4 /*!< USB0 HCSPARAMS: PPC Position */
+#define USB0_HCSPARAMS_PPC_Msk (0x01UL << USB0_HCSPARAMS_PPC_Pos) /*!< USB0 HCSPARAMS: PPC Mask */
+#define USB0_HCSPARAMS_N_PCC_Pos 8 /*!< USB0 HCSPARAMS: N_PCC Position */
+#define USB0_HCSPARAMS_N_PCC_Msk (0x0fUL << USB0_HCSPARAMS_N_PCC_Pos) /*!< USB0 HCSPARAMS: N_PCC Mask */
+#define USB0_HCSPARAMS_N_CC_Pos 12 /*!< USB0 HCSPARAMS: N_CC Position */
+#define USB0_HCSPARAMS_N_CC_Msk (0x0fUL << USB0_HCSPARAMS_N_CC_Pos) /*!< USB0 HCSPARAMS: N_CC Mask */
+#define USB0_HCSPARAMS_PI_Pos 16 /*!< USB0 HCSPARAMS: PI Position */
+#define USB0_HCSPARAMS_PI_Msk (0x01UL << USB0_HCSPARAMS_PI_Pos) /*!< USB0 HCSPARAMS: PI Mask */
+#define USB0_HCSPARAMS_N_PTT_Pos 20 /*!< USB0 HCSPARAMS: N_PTT Position */
+#define USB0_HCSPARAMS_N_PTT_Msk (0x0fUL << USB0_HCSPARAMS_N_PTT_Pos) /*!< USB0 HCSPARAMS: N_PTT Mask */
+#define USB0_HCSPARAMS_N_TT_Pos 24 /*!< USB0 HCSPARAMS: N_TT Position */
+#define USB0_HCSPARAMS_N_TT_Msk (0x0fUL << USB0_HCSPARAMS_N_TT_Pos) /*!< USB0 HCSPARAMS: N_TT Mask */
+
+// ------------------------------------- USB0_HCCPARAMS -----------------------------------------
+#define USB0_HCCPARAMS_ADC_Pos 0 /*!< USB0 HCCPARAMS: ADC Position */
+#define USB0_HCCPARAMS_ADC_Msk (0x01UL << USB0_HCCPARAMS_ADC_Pos) /*!< USB0 HCCPARAMS: ADC Mask */
+#define USB0_HCCPARAMS_PFL_Pos 1 /*!< USB0 HCCPARAMS: PFL Position */
+#define USB0_HCCPARAMS_PFL_Msk (0x01UL << USB0_HCCPARAMS_PFL_Pos) /*!< USB0 HCCPARAMS: PFL Mask */
+#define USB0_HCCPARAMS_ASP_Pos 2 /*!< USB0 HCCPARAMS: ASP Position */
+#define USB0_HCCPARAMS_ASP_Msk (0x01UL << USB0_HCCPARAMS_ASP_Pos) /*!< USB0 HCCPARAMS: ASP Mask */
+#define USB0_HCCPARAMS_IST_Pos 4 /*!< USB0 HCCPARAMS: IST Position */
+#define USB0_HCCPARAMS_IST_Msk (0x0fUL << USB0_HCCPARAMS_IST_Pos) /*!< USB0 HCCPARAMS: IST Mask */
+#define USB0_HCCPARAMS_EECP_Pos 8 /*!< USB0 HCCPARAMS: EECP Position */
+#define USB0_HCCPARAMS_EECP_Msk (0x000000ffUL << USB0_HCCPARAMS_EECP_Pos) /*!< USB0 HCCPARAMS: EECP Mask */
+
+// ------------------------------------- USB0_DCIVERSION ----------------------------------------
+#define USB0_DCIVERSION_DCIVERSION_Pos 0 /*!< USB0 DCIVERSION: DCIVERSION Position */
+#define USB0_DCIVERSION_DCIVERSION_Msk (0x0000ffffUL << USB0_DCIVERSION_DCIVERSION_Pos) /*!< USB0 DCIVERSION: DCIVERSION Mask */
+
+// -------------------------------------- USB0_USBCMD_D -----------------------------------------
+#define USB0_USBCMD_D_RS_Pos 0 /*!< USB0 USBCMD_D: RS Position */
+#define USB0_USBCMD_D_RS_Msk (0x01UL << USB0_USBCMD_D_RS_Pos) /*!< USB0 USBCMD_D: RS Mask */
+#define USB0_USBCMD_D_RST_Pos 1 /*!< USB0 USBCMD_D: RST Position */
+#define USB0_USBCMD_D_RST_Msk (0x01UL << USB0_USBCMD_D_RST_Pos) /*!< USB0 USBCMD_D: RST Mask */
+#define USB0_USBCMD_D_SUTW_Pos 13 /*!< USB0 USBCMD_D: SUTW Position */
+#define USB0_USBCMD_D_SUTW_Msk (0x01UL << USB0_USBCMD_D_SUTW_Pos) /*!< USB0 USBCMD_D: SUTW Mask */
+#define USB0_USBCMD_D_ATDTW_Pos 14 /*!< USB0 USBCMD_D: ATDTW Position */
+#define USB0_USBCMD_D_ATDTW_Msk (0x01UL << USB0_USBCMD_D_ATDTW_Pos) /*!< USB0 USBCMD_D: ATDTW Mask */
+#define USB0_USBCMD_D_ITC_Pos 16 /*!< USB0 USBCMD_D: ITC Position */
+#define USB0_USBCMD_D_ITC_Msk (0x000000ffUL << USB0_USBCMD_D_ITC_Pos) /*!< USB0 USBCMD_D: ITC Mask */
+
+// -------------------------------------- USB0_USBCMD_H -----------------------------------------
+#define USB0_USBCMD_H_RS_Pos 0 /*!< USB0 USBCMD_H: RS Position */
+#define USB0_USBCMD_H_RS_Msk (0x01UL << USB0_USBCMD_H_RS_Pos) /*!< USB0 USBCMD_H: RS Mask */
+#define USB0_USBCMD_H_RST_Pos 1 /*!< USB0 USBCMD_H: RST Position */
+#define USB0_USBCMD_H_RST_Msk (0x01UL << USB0_USBCMD_H_RST_Pos) /*!< USB0 USBCMD_H: RST Mask */
+#define USB0_USBCMD_H_FS0_Pos 2 /*!< USB0 USBCMD_H: FS0 Position */
+#define USB0_USBCMD_H_FS0_Msk (0x01UL << USB0_USBCMD_H_FS0_Pos) /*!< USB0 USBCMD_H: FS0 Mask */
+#define USB0_USBCMD_H_FS1_Pos 3 /*!< USB0 USBCMD_H: FS1 Position */
+#define USB0_USBCMD_H_FS1_Msk (0x01UL << USB0_USBCMD_H_FS1_Pos) /*!< USB0 USBCMD_H: FS1 Mask */
+#define USB0_USBCMD_H_PSE_Pos 4 /*!< USB0 USBCMD_H: PSE Position */
+#define USB0_USBCMD_H_PSE_Msk (0x01UL << USB0_USBCMD_H_PSE_Pos) /*!< USB0 USBCMD_H: PSE Mask */
+#define USB0_USBCMD_H_ASE_Pos 5 /*!< USB0 USBCMD_H: ASE Position */
+#define USB0_USBCMD_H_ASE_Msk (0x01UL << USB0_USBCMD_H_ASE_Pos) /*!< USB0 USBCMD_H: ASE Mask */
+#define USB0_USBCMD_H_IAA_Pos 6 /*!< USB0 USBCMD_H: IAA Position */
+#define USB0_USBCMD_H_IAA_Msk (0x01UL << USB0_USBCMD_H_IAA_Pos) /*!< USB0 USBCMD_H: IAA Mask */
+#define USB0_USBCMD_H_ASP1_0_Pos 8 /*!< USB0 USBCMD_H: ASP1_0 Position */
+#define USB0_USBCMD_H_ASP1_0_Msk (0x03UL << USB0_USBCMD_H_ASP1_0_Pos) /*!< USB0 USBCMD_H: ASP1_0 Mask */
+#define USB0_USBCMD_H_ASPE_Pos 11 /*!< USB0 USBCMD_H: ASPE Position */
+#define USB0_USBCMD_H_ASPE_Msk (0x01UL << USB0_USBCMD_H_ASPE_Pos) /*!< USB0 USBCMD_H: ASPE Mask */
+#define USB0_USBCMD_H_FS2_Pos 15 /*!< USB0 USBCMD_H: FS2 Position */
+#define USB0_USBCMD_H_FS2_Msk (0x01UL << USB0_USBCMD_H_FS2_Pos) /*!< USB0 USBCMD_H: FS2 Mask */
+#define USB0_USBCMD_H_ITC_Pos 16 /*!< USB0 USBCMD_H: ITC Position */
+#define USB0_USBCMD_H_ITC_Msk (0x000000ffUL << USB0_USBCMD_H_ITC_Pos) /*!< USB0 USBCMD_H: ITC Mask */
+
+// -------------------------------------- USB0_USBSTS_D -----------------------------------------
+#define USB0_USBSTS_D_UI_Pos 0 /*!< USB0 USBSTS_D: UI Position */
+#define USB0_USBSTS_D_UI_Msk (0x01UL << USB0_USBSTS_D_UI_Pos) /*!< USB0 USBSTS_D: UI Mask */
+#define USB0_USBSTS_D_UEI_Pos 1 /*!< USB0 USBSTS_D: UEI Position */
+#define USB0_USBSTS_D_UEI_Msk (0x01UL << USB0_USBSTS_D_UEI_Pos) /*!< USB0 USBSTS_D: UEI Mask */
+#define USB0_USBSTS_D_PCI_Pos 2 /*!< USB0 USBSTS_D: PCI Position */
+#define USB0_USBSTS_D_PCI_Msk (0x01UL << USB0_USBSTS_D_PCI_Pos) /*!< USB0 USBSTS_D: PCI Mask */
+#define USB0_USBSTS_D_AAI_Pos 5 /*!< USB0 USBSTS_D: AAI Position */
+#define USB0_USBSTS_D_AAI_Msk (0x01UL << USB0_USBSTS_D_AAI_Pos) /*!< USB0 USBSTS_D: AAI Mask */
+#define USB0_USBSTS_D_URI_Pos 6 /*!< USB0 USBSTS_D: URI Position */
+#define USB0_USBSTS_D_URI_Msk (0x01UL << USB0_USBSTS_D_URI_Pos) /*!< USB0 USBSTS_D: URI Mask */
+#define USB0_USBSTS_D_SRI_Pos 7 /*!< USB0 USBSTS_D: SRI Position */
+#define USB0_USBSTS_D_SRI_Msk (0x01UL << USB0_USBSTS_D_SRI_Pos) /*!< USB0 USBSTS_D: SRI Mask */
+#define USB0_USBSTS_D_SLI_Pos 8 /*!< USB0 USBSTS_D: SLI Position */
+#define USB0_USBSTS_D_SLI_Msk (0x01UL << USB0_USBSTS_D_SLI_Pos) /*!< USB0 USBSTS_D: SLI Mask */
+#define USB0_USBSTS_D_NAKI_Pos 16 /*!< USB0 USBSTS_D: NAKI Position */
+#define USB0_USBSTS_D_NAKI_Msk (0x01UL << USB0_USBSTS_D_NAKI_Pos) /*!< USB0 USBSTS_D: NAKI Mask */
+
+// -------------------------------------- USB0_USBSTS_H -----------------------------------------
+#define USB0_USBSTS_H_UI_Pos 0 /*!< USB0 USBSTS_H: UI Position */
+#define USB0_USBSTS_H_UI_Msk (0x01UL << USB0_USBSTS_H_UI_Pos) /*!< USB0 USBSTS_H: UI Mask */
+#define USB0_USBSTS_H_UEI_Pos 1 /*!< USB0 USBSTS_H: UEI Position */
+#define USB0_USBSTS_H_UEI_Msk (0x01UL << USB0_USBSTS_H_UEI_Pos) /*!< USB0 USBSTS_H: UEI Mask */
+#define USB0_USBSTS_H_PCI_Pos 2 /*!< USB0 USBSTS_H: PCI Position */
+#define USB0_USBSTS_H_PCI_Msk (0x01UL << USB0_USBSTS_H_PCI_Pos) /*!< USB0 USBSTS_H: PCI Mask */
+#define USB0_USBSTS_H_FRI_Pos 3 /*!< USB0 USBSTS_H: FRI Position */
+#define USB0_USBSTS_H_FRI_Msk (0x01UL << USB0_USBSTS_H_FRI_Pos) /*!< USB0 USBSTS_H: FRI Mask */
+#define USB0_USBSTS_H_AAI_Pos 5 /*!< USB0 USBSTS_H: AAI Position */
+#define USB0_USBSTS_H_AAI_Msk (0x01UL << USB0_USBSTS_H_AAI_Pos) /*!< USB0 USBSTS_H: AAI Mask */
+#define USB0_USBSTS_H_SRI_Pos 7 /*!< USB0 USBSTS_H: SRI Position */
+#define USB0_USBSTS_H_SRI_Msk (0x01UL << USB0_USBSTS_H_SRI_Pos) /*!< USB0 USBSTS_H: SRI Mask */
+#define USB0_USBSTS_H_HCH_Pos 12 /*!< USB0 USBSTS_H: HCH Position */
+#define USB0_USBSTS_H_HCH_Msk (0x01UL << USB0_USBSTS_H_HCH_Pos) /*!< USB0 USBSTS_H: HCH Mask */
+#define USB0_USBSTS_H_RCL_Pos 13 /*!< USB0 USBSTS_H: RCL Position */
+#define USB0_USBSTS_H_RCL_Msk (0x01UL << USB0_USBSTS_H_RCL_Pos) /*!< USB0 USBSTS_H: RCL Mask */
+#define USB0_USBSTS_H_PS_Pos 14 /*!< USB0 USBSTS_H: PS Position */
+#define USB0_USBSTS_H_PS_Msk (0x01UL << USB0_USBSTS_H_PS_Pos) /*!< USB0 USBSTS_H: PS Mask */
+#define USB0_USBSTS_H_AS_Pos 15 /*!< USB0 USBSTS_H: AS Position */
+#define USB0_USBSTS_H_AS_Msk (0x01UL << USB0_USBSTS_H_AS_Pos) /*!< USB0 USBSTS_H: AS Mask */
+#define USB0_USBSTS_H_UAI_Pos 18 /*!< USB0 USBSTS_H: UAI Position */
+#define USB0_USBSTS_H_UAI_Msk (0x01UL << USB0_USBSTS_H_UAI_Pos) /*!< USB0 USBSTS_H: UAI Mask */
+#define USB0_USBSTS_H_UPI_Pos 19 /*!< USB0 USBSTS_H: UPI Position */
+#define USB0_USBSTS_H_UPI_Msk (0x01UL << USB0_USBSTS_H_UPI_Pos) /*!< USB0 USBSTS_H: UPI Mask */
+
+// ------------------------------------- USB0_USBINTR_D -----------------------------------------
+#define USB0_USBINTR_D_UE_Pos 0 /*!< USB0 USBINTR_D: UE Position */
+#define USB0_USBINTR_D_UE_Msk (0x01UL << USB0_USBINTR_D_UE_Pos) /*!< USB0 USBINTR_D: UE Mask */
+#define USB0_USBINTR_D_UEE_Pos 1 /*!< USB0 USBINTR_D: UEE Position */
+#define USB0_USBINTR_D_UEE_Msk (0x01UL << USB0_USBINTR_D_UEE_Pos) /*!< USB0 USBINTR_D: UEE Mask */
+#define USB0_USBINTR_D_PCE_Pos 2 /*!< USB0 USBINTR_D: PCE Position */
+#define USB0_USBINTR_D_PCE_Msk (0x01UL << USB0_USBINTR_D_PCE_Pos) /*!< USB0 USBINTR_D: PCE Mask */
+#define USB0_USBINTR_D_URE_Pos 6 /*!< USB0 USBINTR_D: URE Position */
+#define USB0_USBINTR_D_URE_Msk (0x01UL << USB0_USBINTR_D_URE_Pos) /*!< USB0 USBINTR_D: URE Mask */
+#define USB0_USBINTR_D_SRE_Pos 7 /*!< USB0 USBINTR_D: SRE Position */
+#define USB0_USBINTR_D_SRE_Msk (0x01UL << USB0_USBINTR_D_SRE_Pos) /*!< USB0 USBINTR_D: SRE Mask */
+#define USB0_USBINTR_D_SLE_Pos 8 /*!< USB0 USBINTR_D: SLE Position */
+#define USB0_USBINTR_D_SLE_Msk (0x01UL << USB0_USBINTR_D_SLE_Pos) /*!< USB0 USBINTR_D: SLE Mask */
+#define USB0_USBINTR_D_NAKE_Pos 16 /*!< USB0 USBINTR_D: NAKE Position */
+#define USB0_USBINTR_D_NAKE_Msk (0x01UL << USB0_USBINTR_D_NAKE_Pos) /*!< USB0 USBINTR_D: NAKE Mask */
+
+// ------------------------------------- USB0_USBINTR_H -----------------------------------------
+#define USB0_USBINTR_H_UE_Pos 0 /*!< USB0 USBINTR_H: UE Position */
+#define USB0_USBINTR_H_UE_Msk (0x01UL << USB0_USBINTR_H_UE_Pos) /*!< USB0 USBINTR_H: UE Mask */
+#define USB0_USBINTR_H_UEE_Pos 1 /*!< USB0 USBINTR_H: UEE Position */
+#define USB0_USBINTR_H_UEE_Msk (0x01UL << USB0_USBINTR_H_UEE_Pos) /*!< USB0 USBINTR_H: UEE Mask */
+#define USB0_USBINTR_H_PCE_Pos 2 /*!< USB0 USBINTR_H: PCE Position */
+#define USB0_USBINTR_H_PCE_Msk (0x01UL << USB0_USBINTR_H_PCE_Pos) /*!< USB0 USBINTR_H: PCE Mask */
+#define USB0_USBINTR_H_FRE_Pos 3 /*!< USB0 USBINTR_H: FRE Position */
+#define USB0_USBINTR_H_FRE_Msk (0x01UL << USB0_USBINTR_H_FRE_Pos) /*!< USB0 USBINTR_H: FRE Mask */
+#define USB0_USBINTR_H_AAE_Pos 5 /*!< USB0 USBINTR_H: AAE Position */
+#define USB0_USBINTR_H_AAE_Msk (0x01UL << USB0_USBINTR_H_AAE_Pos) /*!< USB0 USBINTR_H: AAE Mask */
+#define USB0_USBINTR_H_SRE_Pos 7 /*!< USB0 USBINTR_H: SRE Position */
+#define USB0_USBINTR_H_SRE_Msk (0x01UL << USB0_USBINTR_H_SRE_Pos) /*!< USB0 USBINTR_H: SRE Mask */
+#define USB0_USBINTR_H_UAIE_Pos 18 /*!< USB0 USBINTR_H: UAIE Position */
+#define USB0_USBINTR_H_UAIE_Msk (0x01UL << USB0_USBINTR_H_UAIE_Pos) /*!< USB0 USBINTR_H: UAIE Mask */
+#define USB0_USBINTR_H_UPIA_Pos 19 /*!< USB0 USBINTR_H: UPIA Position */
+#define USB0_USBINTR_H_UPIA_Msk (0x01UL << USB0_USBINTR_H_UPIA_Pos) /*!< USB0 USBINTR_H: UPIA Mask */
+
+// ------------------------------------- USB0_FRINDEX_D -----------------------------------------
+#define USB0_FRINDEX_D_FRINDEX2_0_Pos 0 /*!< USB0 FRINDEX_D: FRINDEX2_0 Position */
+#define USB0_FRINDEX_D_FRINDEX2_0_Msk (0x07UL << USB0_FRINDEX_D_FRINDEX2_0_Pos) /*!< USB0 FRINDEX_D: FRINDEX2_0 Mask */
+#define USB0_FRINDEX_D_FRINDEX13_3_Pos 3 /*!< USB0 FRINDEX_D: FRINDEX13_3 Position */
+#define USB0_FRINDEX_D_FRINDEX13_3_Msk (0x000007ffUL << USB0_FRINDEX_D_FRINDEX13_3_Pos) /*!< USB0 FRINDEX_D: FRINDEX13_3 Mask */
+
+// ------------------------------------- USB0_FRINDEX_H -----------------------------------------
+#define USB0_FRINDEX_H_FRINDEX2_0_Pos 0 /*!< USB0 FRINDEX_H: FRINDEX2_0 Position */
+#define USB0_FRINDEX_H_FRINDEX2_0_Msk (0x07UL << USB0_FRINDEX_H_FRINDEX2_0_Pos) /*!< USB0 FRINDEX_H: FRINDEX2_0 Mask */
+#define USB0_FRINDEX_H_FRINDEX12_3_Pos 3 /*!< USB0 FRINDEX_H: FRINDEX12_3 Position */
+#define USB0_FRINDEX_H_FRINDEX12_3_Msk (0x000003ffUL << USB0_FRINDEX_H_FRINDEX12_3_Pos) /*!< USB0 FRINDEX_H: FRINDEX12_3 Mask */
+
+// ------------------------------------- USB0_DEVICEADDR ----------------------------------------
+#define USB0_DEVICEADDR_USBADRA_Pos 24 /*!< USB0 DEVICEADDR: USBADRA Position */
+#define USB0_DEVICEADDR_USBADRA_Msk (0x01UL << USB0_DEVICEADDR_USBADRA_Pos) /*!< USB0 DEVICEADDR: USBADRA Mask */
+#define USB0_DEVICEADDR_USBADR_Pos 25 /*!< USB0 DEVICEADDR: USBADR Position */
+#define USB0_DEVICEADDR_USBADR_Msk (0x7fUL << USB0_DEVICEADDR_USBADR_Pos) /*!< USB0 DEVICEADDR: USBADR Mask */
+
+// ---------------------------------- USB0_PERIODICLISTBASE -------------------------------------
+#define USB0_PERIODICLISTBASE_PERBASE31_12_Pos 12 /*!< USB0 PERIODICLISTBASE: PERBASE31_12 Position */
+#define USB0_PERIODICLISTBASE_PERBASE31_12_Msk (0x000fffffUL << USB0_PERIODICLISTBASE_PERBASE31_12_Pos) /*!< USB0 PERIODICLISTBASE: PERBASE31_12 Mask */
+
+// ---------------------------------- USB0_ENDPOINTLISTADDR -------------------------------------
+#define USB0_ENDPOINTLISTADDR_EPBASE31_11_Pos 11 /*!< USB0 ENDPOINTLISTADDR: EPBASE31_11 Position */
+#define USB0_ENDPOINTLISTADDR_EPBASE31_11_Msk (0x001fffffUL << USB0_ENDPOINTLISTADDR_EPBASE31_11_Pos) /*!< USB0 ENDPOINTLISTADDR: EPBASE31_11 Mask */
+
+// ----------------------------------- USB0_ASYNCLISTADDR ---------------------------------------
+#define USB0_ASYNCLISTADDR_ASYBASE31_5_Pos 5 /*!< USB0 ASYNCLISTADDR: ASYBASE31_5 Position */
+#define USB0_ASYNCLISTADDR_ASYBASE31_5_Msk (0x07ffffffUL << USB0_ASYNCLISTADDR_ASYBASE31_5_Pos) /*!< USB0 ASYNCLISTADDR: ASYBASE31_5 Mask */
+
+// --------------------------------------- USB0_TTCTRL ------------------------------------------
+#define USB0_TTCTRL_TTHA_Pos 24 /*!< USB0 TTCTRL: TTHA Position */
+#define USB0_TTCTRL_TTHA_Msk (0x7fUL << USB0_TTCTRL_TTHA_Pos) /*!< USB0 TTCTRL: TTHA Mask */
+
+// ------------------------------------- USB0_BURSTSIZE -----------------------------------------
+#define USB0_BURSTSIZE_RXPBURST_Pos 0 /*!< USB0 BURSTSIZE: RXPBURST Position */
+#define USB0_BURSTSIZE_RXPBURST_Msk (0x000000ffUL << USB0_BURSTSIZE_RXPBURST_Pos) /*!< USB0 BURSTSIZE: RXPBURST Mask */
+#define USB0_BURSTSIZE_TXPBURST_Pos 8 /*!< USB0 BURSTSIZE: TXPBURST Position */
+#define USB0_BURSTSIZE_TXPBURST_Msk (0x000000ffUL << USB0_BURSTSIZE_TXPBURST_Pos) /*!< USB0 BURSTSIZE: TXPBURST Mask */
+
+// ------------------------------------ USB0_TXFILLTUNING ---------------------------------------
+#define USB0_TXFILLTUNING_TXSCHOH_Pos 0 /*!< USB0 TXFILLTUNING: TXSCHOH Position */
+#define USB0_TXFILLTUNING_TXSCHOH_Msk (0x000000ffUL << USB0_TXFILLTUNING_TXSCHOH_Pos) /*!< USB0 TXFILLTUNING: TXSCHOH Mask */
+#define USB0_TXFILLTUNING_TXSCHEATLTH_Pos 8 /*!< USB0 TXFILLTUNING: TXSCHEATLTH Position */
+#define USB0_TXFILLTUNING_TXSCHEATLTH_Msk (0x1fUL << USB0_TXFILLTUNING_TXSCHEATLTH_Pos) /*!< USB0 TXFILLTUNING: TXSCHEATLTH Mask */
+#define USB0_TXFILLTUNING_TXFIFOTHRES_Pos 16 /*!< USB0 TXFILLTUNING: TXFIFOTHRES Position */
+#define USB0_TXFILLTUNING_TXFIFOTHRES_Msk (0x3fUL << USB0_TXFILLTUNING_TXFIFOTHRES_Pos) /*!< USB0 TXFILLTUNING: TXFIFOTHRES Mask */
+
+// ------------------------------------- USB0_BINTERVAL -----------------------------------------
+#define USB0_BINTERVAL_BINT_Pos 0 /*!< USB0 BINTERVAL: BINT Position */
+#define USB0_BINTERVAL_BINT_Msk (0x0fUL << USB0_BINTERVAL_BINT_Pos) /*!< USB0 BINTERVAL: BINT Mask */
+
+// -------------------------------------- USB0_ENDPTNAK -----------------------------------------
+#define USB0_ENDPTNAK_EPRN0_Pos 0 /*!< USB0 ENDPTNAK: EPRN0 Position */
+#define USB0_ENDPTNAK_EPRN0_Msk (0x01UL << USB0_ENDPTNAK_EPRN0_Pos) /*!< USB0 ENDPTNAK: EPRN0 Mask */
+#define USB0_ENDPTNAK_EPRN1_Pos 1 /*!< USB0 ENDPTNAK: EPRN1 Position */
+#define USB0_ENDPTNAK_EPRN1_Msk (0x01UL << USB0_ENDPTNAK_EPRN1_Pos) /*!< USB0 ENDPTNAK: EPRN1 Mask */
+#define USB0_ENDPTNAK_EPRN2_Pos 2 /*!< USB0 ENDPTNAK: EPRN2 Position */
+#define USB0_ENDPTNAK_EPRN2_Msk (0x01UL << USB0_ENDPTNAK_EPRN2_Pos) /*!< USB0 ENDPTNAK: EPRN2 Mask */
+#define USB0_ENDPTNAK_EPRN3_Pos 3 /*!< USB0 ENDPTNAK: EPRN3 Position */
+#define USB0_ENDPTNAK_EPRN3_Msk (0x01UL << USB0_ENDPTNAK_EPRN3_Pos) /*!< USB0 ENDPTNAK: EPRN3 Mask */
+#define USB0_ENDPTNAK_EPRN4_Pos 4 /*!< USB0 ENDPTNAK: EPRN4 Position */
+#define USB0_ENDPTNAK_EPRN4_Msk (0x01UL << USB0_ENDPTNAK_EPRN4_Pos) /*!< USB0 ENDPTNAK: EPRN4 Mask */
+#define USB0_ENDPTNAK_EPRN5_Pos 5 /*!< USB0 ENDPTNAK: EPRN5 Position */
+#define USB0_ENDPTNAK_EPRN5_Msk (0x01UL << USB0_ENDPTNAK_EPRN5_Pos) /*!< USB0 ENDPTNAK: EPRN5 Mask */
+#define USB0_ENDPTNAK_EPTN0_Pos 16 /*!< USB0 ENDPTNAK: EPTN0 Position */
+#define USB0_ENDPTNAK_EPTN0_Msk (0x01UL << USB0_ENDPTNAK_EPTN0_Pos) /*!< USB0 ENDPTNAK: EPTN0 Mask */
+#define USB0_ENDPTNAK_EPTN1_Pos 17 /*!< USB0 ENDPTNAK: EPTN1 Position */
+#define USB0_ENDPTNAK_EPTN1_Msk (0x01UL << USB0_ENDPTNAK_EPTN1_Pos) /*!< USB0 ENDPTNAK: EPTN1 Mask */
+#define USB0_ENDPTNAK_EPTN2_Pos 18 /*!< USB0 ENDPTNAK: EPTN2 Position */
+#define USB0_ENDPTNAK_EPTN2_Msk (0x01UL << USB0_ENDPTNAK_EPTN2_Pos) /*!< USB0 ENDPTNAK: EPTN2 Mask */
+#define USB0_ENDPTNAK_EPTN3_Pos 19 /*!< USB0 ENDPTNAK: EPTN3 Position */
+#define USB0_ENDPTNAK_EPTN3_Msk (0x01UL << USB0_ENDPTNAK_EPTN3_Pos) /*!< USB0 ENDPTNAK: EPTN3 Mask */
+#define USB0_ENDPTNAK_EPTN4_Pos 20 /*!< USB0 ENDPTNAK: EPTN4 Position */
+#define USB0_ENDPTNAK_EPTN4_Msk (0x01UL << USB0_ENDPTNAK_EPTN4_Pos) /*!< USB0 ENDPTNAK: EPTN4 Mask */
+#define USB0_ENDPTNAK_EPTN5_Pos 21 /*!< USB0 ENDPTNAK: EPTN5 Position */
+#define USB0_ENDPTNAK_EPTN5_Msk (0x01UL << USB0_ENDPTNAK_EPTN5_Pos) /*!< USB0 ENDPTNAK: EPTN5 Mask */
+
+// ------------------------------------- USB0_ENDPTNAKEN ----------------------------------------
+#define USB0_ENDPTNAKEN_EPRNE0_Pos 0 /*!< USB0 ENDPTNAKEN: EPRNE0 Position */
+#define USB0_ENDPTNAKEN_EPRNE0_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE0_Pos) /*!< USB0 ENDPTNAKEN: EPRNE0 Mask */
+#define USB0_ENDPTNAKEN_EPRNE1_Pos 1 /*!< USB0 ENDPTNAKEN: EPRNE1 Position */
+#define USB0_ENDPTNAKEN_EPRNE1_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE1_Pos) /*!< USB0 ENDPTNAKEN: EPRNE1 Mask */
+#define USB0_ENDPTNAKEN_EPRNE2_Pos 2 /*!< USB0 ENDPTNAKEN: EPRNE2 Position */
+#define USB0_ENDPTNAKEN_EPRNE2_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE2_Pos) /*!< USB0 ENDPTNAKEN: EPRNE2 Mask */
+#define USB0_ENDPTNAKEN_EPRNE3_Pos 3 /*!< USB0 ENDPTNAKEN: EPRNE3 Position */
+#define USB0_ENDPTNAKEN_EPRNE3_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE3_Pos) /*!< USB0 ENDPTNAKEN: EPRNE3 Mask */
+#define USB0_ENDPTNAKEN_EPRNE4_Pos 4 /*!< USB0 ENDPTNAKEN: EPRNE4 Position */
+#define USB0_ENDPTNAKEN_EPRNE4_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE4_Pos) /*!< USB0 ENDPTNAKEN: EPRNE4 Mask */
+#define USB0_ENDPTNAKEN_EPRNE5_Pos 5 /*!< USB0 ENDPTNAKEN: EPRNE5 Position */
+#define USB0_ENDPTNAKEN_EPRNE5_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE5_Pos) /*!< USB0 ENDPTNAKEN: EPRNE5 Mask */
+#define USB0_ENDPTNAKEN_EPTNE0_Pos 16 /*!< USB0 ENDPTNAKEN: EPTNE0 Position */
+#define USB0_ENDPTNAKEN_EPTNE0_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE0_Pos) /*!< USB0 ENDPTNAKEN: EPTNE0 Mask */
+#define USB0_ENDPTNAKEN_EPTNE1_Pos 17 /*!< USB0 ENDPTNAKEN: EPTNE1 Position */
+#define USB0_ENDPTNAKEN_EPTNE1_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE1_Pos) /*!< USB0 ENDPTNAKEN: EPTNE1 Mask */
+#define USB0_ENDPTNAKEN_EPTNE2_Pos 18 /*!< USB0 ENDPTNAKEN: EPTNE2 Position */
+#define USB0_ENDPTNAKEN_EPTNE2_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE2_Pos) /*!< USB0 ENDPTNAKEN: EPTNE2 Mask */
+#define USB0_ENDPTNAKEN_EPTNE3_Pos 19 /*!< USB0 ENDPTNAKEN: EPTNE3 Position */
+#define USB0_ENDPTNAKEN_EPTNE3_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE3_Pos) /*!< USB0 ENDPTNAKEN: EPTNE3 Mask */
+#define USB0_ENDPTNAKEN_EPTNE4_Pos 20 /*!< USB0 ENDPTNAKEN: EPTNE4 Position */
+#define USB0_ENDPTNAKEN_EPTNE4_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE4_Pos) /*!< USB0 ENDPTNAKEN: EPTNE4 Mask */
+#define USB0_ENDPTNAKEN_EPTNE5_Pos 21 /*!< USB0 ENDPTNAKEN: EPTNE5 Position */
+#define USB0_ENDPTNAKEN_EPTNE5_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE5_Pos) /*!< USB0 ENDPTNAKEN: EPTNE5 Mask */
+
+// ------------------------------------- USB0_PORTSC1_D -----------------------------------------
+#define USB0_PORTSC1_D_CCS_Pos 0 /*!< USB0 PORTSC1_D: CCS Position */
+#define USB0_PORTSC1_D_CCS_Msk (0x01UL << USB0_PORTSC1_D_CCS_Pos) /*!< USB0 PORTSC1_D: CCS Mask */
+#define USB0_PORTSC1_D_PE_Pos 2 /*!< USB0 PORTSC1_D: PE Position */
+#define USB0_PORTSC1_D_PE_Msk (0x01UL << USB0_PORTSC1_D_PE_Pos) /*!< USB0 PORTSC1_D: PE Mask */
+#define USB0_PORTSC1_D_PEC_Pos 3 /*!< USB0 PORTSC1_D: PEC Position */
+#define USB0_PORTSC1_D_PEC_Msk (0x01UL << USB0_PORTSC1_D_PEC_Pos) /*!< USB0 PORTSC1_D: PEC Mask */
+#define USB0_PORTSC1_D_FPR_Pos 6 /*!< USB0 PORTSC1_D: FPR Position */
+#define USB0_PORTSC1_D_FPR_Msk (0x01UL << USB0_PORTSC1_D_FPR_Pos) /*!< USB0 PORTSC1_D: FPR Mask */
+#define USB0_PORTSC1_D_SUSP_Pos 7 /*!< USB0 PORTSC1_D: SUSP Position */
+#define USB0_PORTSC1_D_SUSP_Msk (0x01UL << USB0_PORTSC1_D_SUSP_Pos) /*!< USB0 PORTSC1_D: SUSP Mask */
+#define USB0_PORTSC1_D_PR_Pos 8 /*!< USB0 PORTSC1_D: PR Position */
+#define USB0_PORTSC1_D_PR_Msk (0x01UL << USB0_PORTSC1_D_PR_Pos) /*!< USB0 PORTSC1_D: PR Mask */
+#define USB0_PORTSC1_D_HSP_Pos 9 /*!< USB0 PORTSC1_D: HSP Position */
+#define USB0_PORTSC1_D_HSP_Msk (0x01UL << USB0_PORTSC1_D_HSP_Pos) /*!< USB0 PORTSC1_D: HSP Mask */
+#define USB0_PORTSC1_D_PIC1_0_Pos 14 /*!< USB0 PORTSC1_D: PIC1_0 Position */
+#define USB0_PORTSC1_D_PIC1_0_Msk (0x03UL << USB0_PORTSC1_D_PIC1_0_Pos) /*!< USB0 PORTSC1_D: PIC1_0 Mask */
+#define USB0_PORTSC1_D_PTC3_0_Pos 16 /*!< USB0 PORTSC1_D: PTC3_0 Position */
+#define USB0_PORTSC1_D_PTC3_0_Msk (0x0fUL << USB0_PORTSC1_D_PTC3_0_Pos) /*!< USB0 PORTSC1_D: PTC3_0 Mask */
+#define USB0_PORTSC1_D_PHCD_Pos 23 /*!< USB0 PORTSC1_D: PHCD Position */
+#define USB0_PORTSC1_D_PHCD_Msk (0x01UL << USB0_PORTSC1_D_PHCD_Pos) /*!< USB0 PORTSC1_D: PHCD Mask */
+#define USB0_PORTSC1_D_PFSC_Pos 24 /*!< USB0 PORTSC1_D: PFSC Position */
+#define USB0_PORTSC1_D_PFSC_Msk (0x01UL << USB0_PORTSC1_D_PFSC_Pos) /*!< USB0 PORTSC1_D: PFSC Mask */
+#define USB0_PORTSC1_D_PSPD_Pos 26 /*!< USB0 PORTSC1_D: PSPD Position */
+#define USB0_PORTSC1_D_PSPD_Msk (0x03UL << USB0_PORTSC1_D_PSPD_Pos) /*!< USB0 PORTSC1_D: PSPD Mask */
+
+// ------------------------------------- USB0_PORTSC1_H -----------------------------------------
+#define USB0_PORTSC1_H_CCS_Pos 0 /*!< USB0 PORTSC1_H: CCS Position */
+#define USB0_PORTSC1_H_CCS_Msk (0x01UL << USB0_PORTSC1_H_CCS_Pos) /*!< USB0 PORTSC1_H: CCS Mask */
+#define USB0_PORTSC1_H_CSC_Pos 1 /*!< USB0 PORTSC1_H: CSC Position */
+#define USB0_PORTSC1_H_CSC_Msk (0x01UL << USB0_PORTSC1_H_CSC_Pos) /*!< USB0 PORTSC1_H: CSC Mask */
+#define USB0_PORTSC1_H_PE_Pos 2 /*!< USB0 PORTSC1_H: PE Position */
+#define USB0_PORTSC1_H_PE_Msk (0x01UL << USB0_PORTSC1_H_PE_Pos) /*!< USB0 PORTSC1_H: PE Mask */
+#define USB0_PORTSC1_H_PEC_Pos 3 /*!< USB0 PORTSC1_H: PEC Position */
+#define USB0_PORTSC1_H_PEC_Msk (0x01UL << USB0_PORTSC1_H_PEC_Pos) /*!< USB0 PORTSC1_H: PEC Mask */
+#define USB0_PORTSC1_H_OCA_Pos 4 /*!< USB0 PORTSC1_H: OCA Position */
+#define USB0_PORTSC1_H_OCA_Msk (0x01UL << USB0_PORTSC1_H_OCA_Pos) /*!< USB0 PORTSC1_H: OCA Mask */
+#define USB0_PORTSC1_H_OCC_Pos 5 /*!< USB0 PORTSC1_H: OCC Position */
+#define USB0_PORTSC1_H_OCC_Msk (0x01UL << USB0_PORTSC1_H_OCC_Pos) /*!< USB0 PORTSC1_H: OCC Mask */
+#define USB0_PORTSC1_H_FPR_Pos 6 /*!< USB0 PORTSC1_H: FPR Position */
+#define USB0_PORTSC1_H_FPR_Msk (0x01UL << USB0_PORTSC1_H_FPR_Pos) /*!< USB0 PORTSC1_H: FPR Mask */
+#define USB0_PORTSC1_H_SUSP_Pos 7 /*!< USB0 PORTSC1_H: SUSP Position */
+#define USB0_PORTSC1_H_SUSP_Msk (0x01UL << USB0_PORTSC1_H_SUSP_Pos) /*!< USB0 PORTSC1_H: SUSP Mask */
+#define USB0_PORTSC1_H_PR_Pos 8 /*!< USB0 PORTSC1_H: PR Position */
+#define USB0_PORTSC1_H_PR_Msk (0x01UL << USB0_PORTSC1_H_PR_Pos) /*!< USB0 PORTSC1_H: PR Mask */
+#define USB0_PORTSC1_H_HSP_Pos 9 /*!< USB0 PORTSC1_H: HSP Position */
+#define USB0_PORTSC1_H_HSP_Msk (0x01UL << USB0_PORTSC1_H_HSP_Pos) /*!< USB0 PORTSC1_H: HSP Mask */
+#define USB0_PORTSC1_H_LS_Pos 10 /*!< USB0 PORTSC1_H: LS Position */
+#define USB0_PORTSC1_H_LS_Msk (0x03UL << USB0_PORTSC1_H_LS_Pos) /*!< USB0 PORTSC1_H: LS Mask */
+#define USB0_PORTSC1_H_PP_Pos 12 /*!< USB0 PORTSC1_H: PP Position */
+#define USB0_PORTSC1_H_PP_Msk (0x01UL << USB0_PORTSC1_H_PP_Pos) /*!< USB0 PORTSC1_H: PP Mask */
+#define USB0_PORTSC1_H_PIC1_0_Pos 14 /*!< USB0 PORTSC1_H: PIC1_0 Position */
+#define USB0_PORTSC1_H_PIC1_0_Msk (0x03UL << USB0_PORTSC1_H_PIC1_0_Pos) /*!< USB0 PORTSC1_H: PIC1_0 Mask */
+#define USB0_PORTSC1_H_PTC3_0_Pos 16 /*!< USB0 PORTSC1_H: PTC3_0 Position */
+#define USB0_PORTSC1_H_PTC3_0_Msk (0x0fUL << USB0_PORTSC1_H_PTC3_0_Pos) /*!< USB0 PORTSC1_H: PTC3_0 Mask */
+#define USB0_PORTSC1_H_WKCN_Pos 20 /*!< USB0 PORTSC1_H: WKCN Position */
+#define USB0_PORTSC1_H_WKCN_Msk (0x01UL << USB0_PORTSC1_H_WKCN_Pos) /*!< USB0 PORTSC1_H: WKCN Mask */
+#define USB0_PORTSC1_H_WKDC_Pos 21 /*!< USB0 PORTSC1_H: WKDC Position */
+#define USB0_PORTSC1_H_WKDC_Msk (0x01UL << USB0_PORTSC1_H_WKDC_Pos) /*!< USB0 PORTSC1_H: WKDC Mask */
+#define USB0_PORTSC1_H_WKOC_Pos 22 /*!< USB0 PORTSC1_H: WKOC Position */
+#define USB0_PORTSC1_H_WKOC_Msk (0x01UL << USB0_PORTSC1_H_WKOC_Pos) /*!< USB0 PORTSC1_H: WKOC Mask */
+#define USB0_PORTSC1_H_PHCD_Pos 23 /*!< USB0 PORTSC1_H: PHCD Position */
+#define USB0_PORTSC1_H_PHCD_Msk (0x01UL << USB0_PORTSC1_H_PHCD_Pos) /*!< USB0 PORTSC1_H: PHCD Mask */
+#define USB0_PORTSC1_H_PFSC_Pos 24 /*!< USB0 PORTSC1_H: PFSC Position */
+#define USB0_PORTSC1_H_PFSC_Msk (0x01UL << USB0_PORTSC1_H_PFSC_Pos) /*!< USB0 PORTSC1_H: PFSC Mask */
+#define USB0_PORTSC1_H_PSPD_Pos 26 /*!< USB0 PORTSC1_H: PSPD Position */
+#define USB0_PORTSC1_H_PSPD_Msk (0x03UL << USB0_PORTSC1_H_PSPD_Pos) /*!< USB0 PORTSC1_H: PSPD Mask */
+
+// --------------------------------------- USB0_OTGSC -------------------------------------------
+#define USB0_OTGSC_VD_Pos 0 /*!< USB0 OTGSC: VD Position */
+#define USB0_OTGSC_VD_Msk (0x01UL << USB0_OTGSC_VD_Pos) /*!< USB0 OTGSC: VD Mask */
+#define USB0_OTGSC_VC_Pos 1 /*!< USB0 OTGSC: VC Position */
+#define USB0_OTGSC_VC_Msk (0x01UL << USB0_OTGSC_VC_Pos) /*!< USB0 OTGSC: VC Mask */
+#define USB0_OTGSC_HAAR_Pos 2 /*!< USB0 OTGSC: HAAR Position */
+#define USB0_OTGSC_HAAR_Msk (0x01UL << USB0_OTGSC_HAAR_Pos) /*!< USB0 OTGSC: HAAR Mask */
+#define USB0_OTGSC_OT_Pos 3 /*!< USB0 OTGSC: OT Position */
+#define USB0_OTGSC_OT_Msk (0x01UL << USB0_OTGSC_OT_Pos) /*!< USB0 OTGSC: OT Mask */
+#define USB0_OTGSC_DP_Pos 4 /*!< USB0 OTGSC: DP Position */
+#define USB0_OTGSC_DP_Msk (0x01UL << USB0_OTGSC_DP_Pos) /*!< USB0 OTGSC: DP Mask */
+#define USB0_OTGSC_IDPU_Pos 5 /*!< USB0 OTGSC: IDPU Position */
+#define USB0_OTGSC_IDPU_Msk (0x01UL << USB0_OTGSC_IDPU_Pos) /*!< USB0 OTGSC: IDPU Mask */
+#define USB0_OTGSC_HADP_Pos 6 /*!< USB0 OTGSC: HADP Position */
+#define USB0_OTGSC_HADP_Msk (0x01UL << USB0_OTGSC_HADP_Pos) /*!< USB0 OTGSC: HADP Mask */
+#define USB0_OTGSC_HABA_Pos 7 /*!< USB0 OTGSC: HABA Position */
+#define USB0_OTGSC_HABA_Msk (0x01UL << USB0_OTGSC_HABA_Pos) /*!< USB0 OTGSC: HABA Mask */
+#define USB0_OTGSC_ID_Pos 8 /*!< USB0 OTGSC: ID Position */
+#define USB0_OTGSC_ID_Msk (0x01UL << USB0_OTGSC_ID_Pos) /*!< USB0 OTGSC: ID Mask */
+#define USB0_OTGSC_AVV_Pos 9 /*!< USB0 OTGSC: AVV Position */
+#define USB0_OTGSC_AVV_Msk (0x01UL << USB0_OTGSC_AVV_Pos) /*!< USB0 OTGSC: AVV Mask */
+#define USB0_OTGSC_ASV_Pos 10 /*!< USB0 OTGSC: ASV Position */
+#define USB0_OTGSC_ASV_Msk (0x01UL << USB0_OTGSC_ASV_Pos) /*!< USB0 OTGSC: ASV Mask */
+#define USB0_OTGSC_BSV_Pos 11 /*!< USB0 OTGSC: BSV Position */
+#define USB0_OTGSC_BSV_Msk (0x01UL << USB0_OTGSC_BSV_Pos) /*!< USB0 OTGSC: BSV Mask */
+#define USB0_OTGSC_BSE_Pos 12 /*!< USB0 OTGSC: BSE Position */
+#define USB0_OTGSC_BSE_Msk (0x01UL << USB0_OTGSC_BSE_Pos) /*!< USB0 OTGSC: BSE Mask */
+#define USB0_OTGSC_MS1T_Pos 13 /*!< USB0 OTGSC: MS1T Position */
+#define USB0_OTGSC_MS1T_Msk (0x01UL << USB0_OTGSC_MS1T_Pos) /*!< USB0 OTGSC: MS1T Mask */
+#define USB0_OTGSC_DPS_Pos 14 /*!< USB0 OTGSC: DPS Position */
+#define USB0_OTGSC_DPS_Msk (0x01UL << USB0_OTGSC_DPS_Pos) /*!< USB0 OTGSC: DPS Mask */
+#define USB0_OTGSC_IDIS_Pos 16 /*!< USB0 OTGSC: IDIS Position */
+#define USB0_OTGSC_IDIS_Msk (0x01UL << USB0_OTGSC_IDIS_Pos) /*!< USB0 OTGSC: IDIS Mask */
+#define USB0_OTGSC_AVVIS_Pos 17 /*!< USB0 OTGSC: AVVIS Position */
+#define USB0_OTGSC_AVVIS_Msk (0x01UL << USB0_OTGSC_AVVIS_Pos) /*!< USB0 OTGSC: AVVIS Mask */
+#define USB0_OTGSC_ASVIS_Pos 18 /*!< USB0 OTGSC: ASVIS Position */
+#define USB0_OTGSC_ASVIS_Msk (0x01UL << USB0_OTGSC_ASVIS_Pos) /*!< USB0 OTGSC: ASVIS Mask */
+#define USB0_OTGSC_BSVIS_Pos 19 /*!< USB0 OTGSC: BSVIS Position */
+#define USB0_OTGSC_BSVIS_Msk (0x01UL << USB0_OTGSC_BSVIS_Pos) /*!< USB0 OTGSC: BSVIS Mask */
+#define USB0_OTGSC_BSEIS_Pos 20 /*!< USB0 OTGSC: BSEIS Position */
+#define USB0_OTGSC_BSEIS_Msk (0x01UL << USB0_OTGSC_BSEIS_Pos) /*!< USB0 OTGSC: BSEIS Mask */
+#define USB0_OTGSC_ms1S_Pos 21 /*!< USB0 OTGSC: ms1S Position */
+#define USB0_OTGSC_ms1S_Msk (0x01UL << USB0_OTGSC_ms1S_Pos) /*!< USB0 OTGSC: ms1S Mask */
+#define USB0_OTGSC_DPIS_Pos 22 /*!< USB0 OTGSC: DPIS Position */
+#define USB0_OTGSC_DPIS_Msk (0x01UL << USB0_OTGSC_DPIS_Pos) /*!< USB0 OTGSC: DPIS Mask */
+#define USB0_OTGSC_IDIE_Pos 24 /*!< USB0 OTGSC: IDIE Position */
+#define USB0_OTGSC_IDIE_Msk (0x01UL << USB0_OTGSC_IDIE_Pos) /*!< USB0 OTGSC: IDIE Mask */
+#define USB0_OTGSC_AVVIE_Pos 25 /*!< USB0 OTGSC: AVVIE Position */
+#define USB0_OTGSC_AVVIE_Msk (0x01UL << USB0_OTGSC_AVVIE_Pos) /*!< USB0 OTGSC: AVVIE Mask */
+#define USB0_OTGSC_ASVIE_Pos 26 /*!< USB0 OTGSC: ASVIE Position */
+#define USB0_OTGSC_ASVIE_Msk (0x01UL << USB0_OTGSC_ASVIE_Pos) /*!< USB0 OTGSC: ASVIE Mask */
+#define USB0_OTGSC_BSVIE_Pos 27 /*!< USB0 OTGSC: BSVIE Position */
+#define USB0_OTGSC_BSVIE_Msk (0x01UL << USB0_OTGSC_BSVIE_Pos) /*!< USB0 OTGSC: BSVIE Mask */
+#define USB0_OTGSC_BSEIE_Pos 28 /*!< USB0 OTGSC: BSEIE Position */
+#define USB0_OTGSC_BSEIE_Msk (0x01UL << USB0_OTGSC_BSEIE_Pos) /*!< USB0 OTGSC: BSEIE Mask */
+#define USB0_OTGSC_MS1E_Pos 29 /*!< USB0 OTGSC: MS1E Position */
+#define USB0_OTGSC_MS1E_Msk (0x01UL << USB0_OTGSC_MS1E_Pos) /*!< USB0 OTGSC: MS1E Mask */
+#define USB0_OTGSC_DPIE_Pos 30 /*!< USB0 OTGSC: DPIE Position */
+#define USB0_OTGSC_DPIE_Msk (0x01UL << USB0_OTGSC_DPIE_Pos) /*!< USB0 OTGSC: DPIE Mask */
+
+// ------------------------------------- USB0_USBMODE_D -----------------------------------------
+#define USB0_USBMODE_D_CM1_0_Pos 0 /*!< USB0 USBMODE_D: CM1_0 Position */
+#define USB0_USBMODE_D_CM1_0_Msk (0x03UL << USB0_USBMODE_D_CM1_0_Pos) /*!< USB0 USBMODE_D: CM1_0 Mask */
+#define USB0_USBMODE_D_ES_Pos 2 /*!< USB0 USBMODE_D: ES Position */
+#define USB0_USBMODE_D_ES_Msk (0x01UL << USB0_USBMODE_D_ES_Pos) /*!< USB0 USBMODE_D: ES Mask */
+#define USB0_USBMODE_D_SLOM_Pos 3 /*!< USB0 USBMODE_D: SLOM Position */
+#define USB0_USBMODE_D_SLOM_Msk (0x01UL << USB0_USBMODE_D_SLOM_Pos) /*!< USB0 USBMODE_D: SLOM Mask */
+#define USB0_USBMODE_D_SDIS_Pos 4 /*!< USB0 USBMODE_D: SDIS Position */
+#define USB0_USBMODE_D_SDIS_Msk (0x01UL << USB0_USBMODE_D_SDIS_Pos) /*!< USB0 USBMODE_D: SDIS Mask */
+
+// ------------------------------------- USB0_USBMODE_H -----------------------------------------
+#define USB0_USBMODE_H_CM_Pos 0 /*!< USB0 USBMODE_H: CM Position */
+#define USB0_USBMODE_H_CM_Msk (0x03UL << USB0_USBMODE_H_CM_Pos) /*!< USB0 USBMODE_H: CM Mask */
+#define USB0_USBMODE_H_ES_Pos 2 /*!< USB0 USBMODE_H: ES Position */
+#define USB0_USBMODE_H_ES_Msk (0x01UL << USB0_USBMODE_H_ES_Pos) /*!< USB0 USBMODE_H: ES Mask */
+#define USB0_USBMODE_H_SDIS_Pos 4 /*!< USB0 USBMODE_H: SDIS Position */
+#define USB0_USBMODE_H_SDIS_Msk (0x01UL << USB0_USBMODE_H_SDIS_Pos) /*!< USB0 USBMODE_H: SDIS Mask */
+#define USB0_USBMODE_H_VBPS_Pos 5 /*!< USB0 USBMODE_H: VBPS Position */
+#define USB0_USBMODE_H_VBPS_Msk (0x01UL << USB0_USBMODE_H_VBPS_Pos) /*!< USB0 USBMODE_H: VBPS Mask */
+
+// ----------------------------------- USB0_ENDPTSETUPSTAT --------------------------------------
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos 0 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Position */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Mask */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos 1 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Position */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Mask */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos 2 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Position */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Mask */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos 3 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Position */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Mask */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Pos 4 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT4 Position */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT4 Mask */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Pos 5 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT5 Position */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT5 Mask */
+
+// ------------------------------------- USB0_ENDPTPRIME ----------------------------------------
+#define USB0_ENDPTPRIME_PERB0_Pos 0 /*!< USB0 ENDPTPRIME: PERB0 Position */
+#define USB0_ENDPTPRIME_PERB0_Msk (0x01UL << USB0_ENDPTPRIME_PERB0_Pos) /*!< USB0 ENDPTPRIME: PERB0 Mask */
+#define USB0_ENDPTPRIME_PERB1_Pos 1 /*!< USB0 ENDPTPRIME: PERB1 Position */
+#define USB0_ENDPTPRIME_PERB1_Msk (0x01UL << USB0_ENDPTPRIME_PERB1_Pos) /*!< USB0 ENDPTPRIME: PERB1 Mask */
+#define USB0_ENDPTPRIME_PERB2_Pos 2 /*!< USB0 ENDPTPRIME: PERB2 Position */
+#define USB0_ENDPTPRIME_PERB2_Msk (0x01UL << USB0_ENDPTPRIME_PERB2_Pos) /*!< USB0 ENDPTPRIME: PERB2 Mask */
+#define USB0_ENDPTPRIME_PERB3_Pos 3 /*!< USB0 ENDPTPRIME: PERB3 Position */
+#define USB0_ENDPTPRIME_PERB3_Msk (0x01UL << USB0_ENDPTPRIME_PERB3_Pos) /*!< USB0 ENDPTPRIME: PERB3 Mask */
+#define USB0_ENDPTPRIME_PERB4_Pos 4 /*!< USB0 ENDPTPRIME: PERB4 Position */
+#define USB0_ENDPTPRIME_PERB4_Msk (0x01UL << USB0_ENDPTPRIME_PERB4_Pos) /*!< USB0 ENDPTPRIME: PERB4 Mask */
+#define USB0_ENDPTPRIME_PERB5_Pos 5 /*!< USB0 ENDPTPRIME: PERB5 Position */
+#define USB0_ENDPTPRIME_PERB5_Msk (0x01UL << USB0_ENDPTPRIME_PERB5_Pos) /*!< USB0 ENDPTPRIME: PERB5 Mask */
+#define USB0_ENDPTPRIME_PETB0_Pos 16 /*!< USB0 ENDPTPRIME: PETB0 Position */
+#define USB0_ENDPTPRIME_PETB0_Msk (0x01UL << USB0_ENDPTPRIME_PETB0_Pos) /*!< USB0 ENDPTPRIME: PETB0 Mask */
+#define USB0_ENDPTPRIME_PETB1_Pos 17 /*!< USB0 ENDPTPRIME: PETB1 Position */
+#define USB0_ENDPTPRIME_PETB1_Msk (0x01UL << USB0_ENDPTPRIME_PETB1_Pos) /*!< USB0 ENDPTPRIME: PETB1 Mask */
+#define USB0_ENDPTPRIME_PETB2_Pos 18 /*!< USB0 ENDPTPRIME: PETB2 Position */
+#define USB0_ENDPTPRIME_PETB2_Msk (0x01UL << USB0_ENDPTPRIME_PETB2_Pos) /*!< USB0 ENDPTPRIME: PETB2 Mask */
+#define USB0_ENDPTPRIME_PETB3_Pos 19 /*!< USB0 ENDPTPRIME: PETB3 Position */
+#define USB0_ENDPTPRIME_PETB3_Msk (0x01UL << USB0_ENDPTPRIME_PETB3_Pos) /*!< USB0 ENDPTPRIME: PETB3 Mask */
+#define USB0_ENDPTPRIME_PETB4_Pos 20 /*!< USB0 ENDPTPRIME: PETB4 Position */
+#define USB0_ENDPTPRIME_PETB4_Msk (0x01UL << USB0_ENDPTPRIME_PETB4_Pos) /*!< USB0 ENDPTPRIME: PETB4 Mask */
+#define USB0_ENDPTPRIME_PETB5_Pos 21 /*!< USB0 ENDPTPRIME: PETB5 Position */
+#define USB0_ENDPTPRIME_PETB5_Msk (0x01UL << USB0_ENDPTPRIME_PETB5_Pos) /*!< USB0 ENDPTPRIME: PETB5 Mask */
+
+// ------------------------------------- USB0_ENDPTFLUSH ----------------------------------------
+#define USB0_ENDPTFLUSH_FERB0_Pos 0 /*!< USB0 ENDPTFLUSH: FERB0 Position */
+#define USB0_ENDPTFLUSH_FERB0_Msk (0x01UL << USB0_ENDPTFLUSH_FERB0_Pos) /*!< USB0 ENDPTFLUSH: FERB0 Mask */
+#define USB0_ENDPTFLUSH_FERB1_Pos 1 /*!< USB0 ENDPTFLUSH: FERB1 Position */
+#define USB0_ENDPTFLUSH_FERB1_Msk (0x01UL << USB0_ENDPTFLUSH_FERB1_Pos) /*!< USB0 ENDPTFLUSH: FERB1 Mask */
+#define USB0_ENDPTFLUSH_FERB2_Pos 2 /*!< USB0 ENDPTFLUSH: FERB2 Position */
+#define USB0_ENDPTFLUSH_FERB2_Msk (0x01UL << USB0_ENDPTFLUSH_FERB2_Pos) /*!< USB0 ENDPTFLUSH: FERB2 Mask */
+#define USB0_ENDPTFLUSH_FERB3_Pos 3 /*!< USB0 ENDPTFLUSH: FERB3 Position */
+#define USB0_ENDPTFLUSH_FERB3_Msk (0x01UL << USB0_ENDPTFLUSH_FERB3_Pos) /*!< USB0 ENDPTFLUSH: FERB3 Mask */
+#define USB0_ENDPTFLUSH_FERB4_Pos 4 /*!< USB0 ENDPTFLUSH: FERB4 Position */
+#define USB0_ENDPTFLUSH_FERB4_Msk (0x01UL << USB0_ENDPTFLUSH_FERB4_Pos) /*!< USB0 ENDPTFLUSH: FERB4 Mask */
+#define USB0_ENDPTFLUSH_FERB5_Pos 5 /*!< USB0 ENDPTFLUSH: FERB5 Position */
+#define USB0_ENDPTFLUSH_FERB5_Msk (0x01UL << USB0_ENDPTFLUSH_FERB5_Pos) /*!< USB0 ENDPTFLUSH: FERB5 Mask */
+#define USB0_ENDPTFLUSH_FETB0_Pos 16 /*!< USB0 ENDPTFLUSH: FETB0 Position */
+#define USB0_ENDPTFLUSH_FETB0_Msk (0x01UL << USB0_ENDPTFLUSH_FETB0_Pos) /*!< USB0 ENDPTFLUSH: FETB0 Mask */
+#define USB0_ENDPTFLUSH_FETB1_Pos 17 /*!< USB0 ENDPTFLUSH: FETB1 Position */
+#define USB0_ENDPTFLUSH_FETB1_Msk (0x01UL << USB0_ENDPTFLUSH_FETB1_Pos) /*!< USB0 ENDPTFLUSH: FETB1 Mask */
+#define USB0_ENDPTFLUSH_FETB2_Pos 18 /*!< USB0 ENDPTFLUSH: FETB2 Position */
+#define USB0_ENDPTFLUSH_FETB2_Msk (0x01UL << USB0_ENDPTFLUSH_FETB2_Pos) /*!< USB0 ENDPTFLUSH: FETB2 Mask */
+#define USB0_ENDPTFLUSH_FETB3_Pos 19 /*!< USB0 ENDPTFLUSH: FETB3 Position */
+#define USB0_ENDPTFLUSH_FETB3_Msk (0x01UL << USB0_ENDPTFLUSH_FETB3_Pos) /*!< USB0 ENDPTFLUSH: FETB3 Mask */
+#define USB0_ENDPTFLUSH_FETB4_Pos 20 /*!< USB0 ENDPTFLUSH: FETB4 Position */
+#define USB0_ENDPTFLUSH_FETB4_Msk (0x01UL << USB0_ENDPTFLUSH_FETB4_Pos) /*!< USB0 ENDPTFLUSH: FETB4 Mask */
+#define USB0_ENDPTFLUSH_FETB5_Pos 21 /*!< USB0 ENDPTFLUSH: FETB5 Position */
+#define USB0_ENDPTFLUSH_FETB5_Msk (0x01UL << USB0_ENDPTFLUSH_FETB5_Pos) /*!< USB0 ENDPTFLUSH: FETB5 Mask */
+
+// ------------------------------------- USB0_ENDPTSTAT -----------------------------------------
+#define USB0_ENDPTSTAT_ERBR0_Pos 0 /*!< USB0 ENDPTSTAT: ERBR0 Position */
+#define USB0_ENDPTSTAT_ERBR0_Msk (0x01UL << USB0_ENDPTSTAT_ERBR0_Pos) /*!< USB0 ENDPTSTAT: ERBR0 Mask */
+#define USB0_ENDPTSTAT_ERBR1_Pos 1 /*!< USB0 ENDPTSTAT: ERBR1 Position */
+#define USB0_ENDPTSTAT_ERBR1_Msk (0x01UL << USB0_ENDPTSTAT_ERBR1_Pos) /*!< USB0 ENDPTSTAT: ERBR1 Mask */
+#define USB0_ENDPTSTAT_ERBR2_Pos 2 /*!< USB0 ENDPTSTAT: ERBR2 Position */
+#define USB0_ENDPTSTAT_ERBR2_Msk (0x01UL << USB0_ENDPTSTAT_ERBR2_Pos) /*!< USB0 ENDPTSTAT: ERBR2 Mask */
+#define USB0_ENDPTSTAT_ERBR3_Pos 3 /*!< USB0 ENDPTSTAT: ERBR3 Position */
+#define USB0_ENDPTSTAT_ERBR3_Msk (0x01UL << USB0_ENDPTSTAT_ERBR3_Pos) /*!< USB0 ENDPTSTAT: ERBR3 Mask */
+#define USB0_ENDPTSTAT_ERBR4_Pos 4 /*!< USB0 ENDPTSTAT: ERBR4 Position */
+#define USB0_ENDPTSTAT_ERBR4_Msk (0x01UL << USB0_ENDPTSTAT_ERBR4_Pos) /*!< USB0 ENDPTSTAT: ERBR4 Mask */
+#define USB0_ENDPTSTAT_ERBR5_Pos 5 /*!< USB0 ENDPTSTAT: ERBR5 Position */
+#define USB0_ENDPTSTAT_ERBR5_Msk (0x01UL << USB0_ENDPTSTAT_ERBR5_Pos) /*!< USB0 ENDPTSTAT: ERBR5 Mask */
+#define USB0_ENDPTSTAT_ETBR0_Pos 16 /*!< USB0 ENDPTSTAT: ETBR0 Position */
+#define USB0_ENDPTSTAT_ETBR0_Msk (0x01UL << USB0_ENDPTSTAT_ETBR0_Pos) /*!< USB0 ENDPTSTAT: ETBR0 Mask */
+#define USB0_ENDPTSTAT_ETBR1_Pos 17 /*!< USB0 ENDPTSTAT: ETBR1 Position */
+#define USB0_ENDPTSTAT_ETBR1_Msk (0x01UL << USB0_ENDPTSTAT_ETBR1_Pos) /*!< USB0 ENDPTSTAT: ETBR1 Mask */
+#define USB0_ENDPTSTAT_ETBR2_Pos 18 /*!< USB0 ENDPTSTAT: ETBR2 Position */
+#define USB0_ENDPTSTAT_ETBR2_Msk (0x01UL << USB0_ENDPTSTAT_ETBR2_Pos) /*!< USB0 ENDPTSTAT: ETBR2 Mask */
+#define USB0_ENDPTSTAT_ETBR3_Pos 19 /*!< USB0 ENDPTSTAT: ETBR3 Position */
+#define USB0_ENDPTSTAT_ETBR3_Msk (0x01UL << USB0_ENDPTSTAT_ETBR3_Pos) /*!< USB0 ENDPTSTAT: ETBR3 Mask */
+#define USB0_ENDPTSTAT_ETBR4_Pos 20 /*!< USB0 ENDPTSTAT: ETBR4 Position */
+#define USB0_ENDPTSTAT_ETBR4_Msk (0x01UL << USB0_ENDPTSTAT_ETBR4_Pos) /*!< USB0 ENDPTSTAT: ETBR4 Mask */
+#define USB0_ENDPTSTAT_ETBR5_Pos 21 /*!< USB0 ENDPTSTAT: ETBR5 Position */
+#define USB0_ENDPTSTAT_ETBR5_Msk (0x01UL << USB0_ENDPTSTAT_ETBR5_Pos) /*!< USB0 ENDPTSTAT: ETBR5 Mask */
+
+// ----------------------------------- USB0_ENDPTCOMPLETE ---------------------------------------
+#define USB0_ENDPTCOMPLETE_ERCE0_Pos 0 /*!< USB0 ENDPTCOMPLETE: ERCE0 Position */
+#define USB0_ENDPTCOMPLETE_ERCE0_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE0_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE0 Mask */
+#define USB0_ENDPTCOMPLETE_ERCE1_Pos 1 /*!< USB0 ENDPTCOMPLETE: ERCE1 Position */
+#define USB0_ENDPTCOMPLETE_ERCE1_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE1_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE1 Mask */
+#define USB0_ENDPTCOMPLETE_ERCE2_Pos 2 /*!< USB0 ENDPTCOMPLETE: ERCE2 Position */
+#define USB0_ENDPTCOMPLETE_ERCE2_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE2_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE2 Mask */
+#define USB0_ENDPTCOMPLETE_ERCE3_Pos 3 /*!< USB0 ENDPTCOMPLETE: ERCE3 Position */
+#define USB0_ENDPTCOMPLETE_ERCE3_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE3_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE3 Mask */
+#define USB0_ENDPTCOMPLETE_ERCE4_Pos 4 /*!< USB0 ENDPTCOMPLETE: ERCE4 Position */
+#define USB0_ENDPTCOMPLETE_ERCE4_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE4_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE4 Mask */
+#define USB0_ENDPTCOMPLETE_ERCE5_Pos 5 /*!< USB0 ENDPTCOMPLETE: ERCE5 Position */
+#define USB0_ENDPTCOMPLETE_ERCE5_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE5_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE5 Mask */
+#define USB0_ENDPTCOMPLETE_ETCE0_Pos 16 /*!< USB0 ENDPTCOMPLETE: ETCE0 Position */
+#define USB0_ENDPTCOMPLETE_ETCE0_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE0_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE0 Mask */
+#define USB0_ENDPTCOMPLETE_ETCE1_Pos 17 /*!< USB0 ENDPTCOMPLETE: ETCE1 Position */
+#define USB0_ENDPTCOMPLETE_ETCE1_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE1_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE1 Mask */
+#define USB0_ENDPTCOMPLETE_ETCE2_Pos 18 /*!< USB0 ENDPTCOMPLETE: ETCE2 Position */
+#define USB0_ENDPTCOMPLETE_ETCE2_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE2_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE2 Mask */
+#define USB0_ENDPTCOMPLETE_ETCE3_Pos 19 /*!< USB0 ENDPTCOMPLETE: ETCE3 Position */
+#define USB0_ENDPTCOMPLETE_ETCE3_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE3_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE3 Mask */
+#define USB0_ENDPTCOMPLETE_ETCE4_Pos 20 /*!< USB0 ENDPTCOMPLETE: ETCE4 Position */
+#define USB0_ENDPTCOMPLETE_ETCE4_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE4_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE4 Mask */
+#define USB0_ENDPTCOMPLETE_ETCE5_Pos 21 /*!< USB0 ENDPTCOMPLETE: ETCE5 Position */
+#define USB0_ENDPTCOMPLETE_ETCE5_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE5_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE5 Mask */
+
+// ------------------------------------- USB0_ENDPTCTRL0 ----------------------------------------
+#define USB0_ENDPTCTRL0_RXS_Pos 0 /*!< USB0 ENDPTCTRL0: RXS Position */
+#define USB0_ENDPTCTRL0_RXS_Msk (0x01UL << USB0_ENDPTCTRL0_RXS_Pos) /*!< USB0 ENDPTCTRL0: RXS Mask */
+#define USB0_ENDPTCTRL0_RXT1_0_Pos 2 /*!< USB0 ENDPTCTRL0: RXT1_0 Position */
+#define USB0_ENDPTCTRL0_RXT1_0_Msk (0x03UL << USB0_ENDPTCTRL0_RXT1_0_Pos) /*!< USB0 ENDPTCTRL0: RXT1_0 Mask */
+#define USB0_ENDPTCTRL0_RXE_Pos 7 /*!< USB0 ENDPTCTRL0: RXE Position */
+#define USB0_ENDPTCTRL0_RXE_Msk (0x01UL << USB0_ENDPTCTRL0_RXE_Pos) /*!< USB0 ENDPTCTRL0: RXE Mask */
+#define USB0_ENDPTCTRL0_TXS_Pos 16 /*!< USB0 ENDPTCTRL0: TXS Position */
+#define USB0_ENDPTCTRL0_TXS_Msk (0x01UL << USB0_ENDPTCTRL0_TXS_Pos) /*!< USB0 ENDPTCTRL0: TXS Mask */
+#define USB0_ENDPTCTRL0_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL0: TXT1_0 Position */
+#define USB0_ENDPTCTRL0_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL0_TXT1_0_Pos) /*!< USB0 ENDPTCTRL0: TXT1_0 Mask */
+#define USB0_ENDPTCTRL0_TXE_Pos 23 /*!< USB0 ENDPTCTRL0: TXE Position */
+#define USB0_ENDPTCTRL0_TXE_Msk (0x01UL << USB0_ENDPTCTRL0_TXE_Pos) /*!< USB0 ENDPTCTRL0: TXE Mask */
+
+// ------------------------------------- USB0_ENDPTCTRL1 ----------------------------------------
+#define USB0_ENDPTCTRL1_RXS_Pos 0 /*!< USB0 ENDPTCTRL1: RXS Position */
+#define USB0_ENDPTCTRL1_RXS_Msk (0x01UL << USB0_ENDPTCTRL1_RXS_Pos) /*!< USB0 ENDPTCTRL1: RXS Mask */
+#define USB0_ENDPTCTRL1_RXT_Pos 2 /*!< USB0 ENDPTCTRL1: RXT Position */
+#define USB0_ENDPTCTRL1_RXT_Msk (0x03UL << USB0_ENDPTCTRL1_RXT_Pos) /*!< USB0 ENDPTCTRL1: RXT Mask */
+#define USB0_ENDPTCTRL1_RXI_Pos 5 /*!< USB0 ENDPTCTRL1: RXI Position */
+#define USB0_ENDPTCTRL1_RXI_Msk (0x01UL << USB0_ENDPTCTRL1_RXI_Pos) /*!< USB0 ENDPTCTRL1: RXI Mask */
+#define USB0_ENDPTCTRL1_RXR_Pos 6 /*!< USB0 ENDPTCTRL1: RXR Position */
+#define USB0_ENDPTCTRL1_RXR_Msk (0x01UL << USB0_ENDPTCTRL1_RXR_Pos) /*!< USB0 ENDPTCTRL1: RXR Mask */
+#define USB0_ENDPTCTRL1_RXE_Pos 7 /*!< USB0 ENDPTCTRL1: RXE Position */
+#define USB0_ENDPTCTRL1_RXE_Msk (0x01UL << USB0_ENDPTCTRL1_RXE_Pos) /*!< USB0 ENDPTCTRL1: RXE Mask */
+#define USB0_ENDPTCTRL1_TXS_Pos 16 /*!< USB0 ENDPTCTRL1: TXS Position */
+#define USB0_ENDPTCTRL1_TXS_Msk (0x01UL << USB0_ENDPTCTRL1_TXS_Pos) /*!< USB0 ENDPTCTRL1: TXS Mask */
+#define USB0_ENDPTCTRL1_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL1: TXT1_0 Position */
+#define USB0_ENDPTCTRL1_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL1_TXT1_0_Pos) /*!< USB0 ENDPTCTRL1: TXT1_0 Mask */
+#define USB0_ENDPTCTRL1_TXI_Pos 21 /*!< USB0 ENDPTCTRL1: TXI Position */
+#define USB0_ENDPTCTRL1_TXI_Msk (0x01UL << USB0_ENDPTCTRL1_TXI_Pos) /*!< USB0 ENDPTCTRL1: TXI Mask */
+#define USB0_ENDPTCTRL1_TXR_Pos 22 /*!< USB0 ENDPTCTRL1: TXR Position */
+#define USB0_ENDPTCTRL1_TXR_Msk (0x01UL << USB0_ENDPTCTRL1_TXR_Pos) /*!< USB0 ENDPTCTRL1: TXR Mask */
+#define USB0_ENDPTCTRL1_TXE_Pos 23 /*!< USB0 ENDPTCTRL1: TXE Position */
+#define USB0_ENDPTCTRL1_TXE_Msk (0x01UL << USB0_ENDPTCTRL1_TXE_Pos) /*!< USB0 ENDPTCTRL1: TXE Mask */
+
+// ------------------------------------- USB0_ENDPTCTRL2 ----------------------------------------
+#define USB0_ENDPTCTRL2_RXS_Pos 0 /*!< USB0 ENDPTCTRL2: RXS Position */
+#define USB0_ENDPTCTRL2_RXS_Msk (0x01UL << USB0_ENDPTCTRL2_RXS_Pos) /*!< USB0 ENDPTCTRL2: RXS Mask */
+#define USB0_ENDPTCTRL2_RXT_Pos 2 /*!< USB0 ENDPTCTRL2: RXT Position */
+#define USB0_ENDPTCTRL2_RXT_Msk (0x03UL << USB0_ENDPTCTRL2_RXT_Pos) /*!< USB0 ENDPTCTRL2: RXT Mask */
+#define USB0_ENDPTCTRL2_RXI_Pos 5 /*!< USB0 ENDPTCTRL2: RXI Position */
+#define USB0_ENDPTCTRL2_RXI_Msk (0x01UL << USB0_ENDPTCTRL2_RXI_Pos) /*!< USB0 ENDPTCTRL2: RXI Mask */
+#define USB0_ENDPTCTRL2_RXR_Pos 6 /*!< USB0 ENDPTCTRL2: RXR Position */
+#define USB0_ENDPTCTRL2_RXR_Msk (0x01UL << USB0_ENDPTCTRL2_RXR_Pos) /*!< USB0 ENDPTCTRL2: RXR Mask */
+#define USB0_ENDPTCTRL2_RXE_Pos 7 /*!< USB0 ENDPTCTRL2: RXE Position */
+#define USB0_ENDPTCTRL2_RXE_Msk (0x01UL << USB0_ENDPTCTRL2_RXE_Pos) /*!< USB0 ENDPTCTRL2: RXE Mask */
+#define USB0_ENDPTCTRL2_TXS_Pos 16 /*!< USB0 ENDPTCTRL2: TXS Position */
+#define USB0_ENDPTCTRL2_TXS_Msk (0x01UL << USB0_ENDPTCTRL2_TXS_Pos) /*!< USB0 ENDPTCTRL2: TXS Mask */
+#define USB0_ENDPTCTRL2_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL2: TXT1_0 Position */
+#define USB0_ENDPTCTRL2_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL2_TXT1_0_Pos) /*!< USB0 ENDPTCTRL2: TXT1_0 Mask */
+#define USB0_ENDPTCTRL2_TXI_Pos 21 /*!< USB0 ENDPTCTRL2: TXI Position */
+#define USB0_ENDPTCTRL2_TXI_Msk (0x01UL << USB0_ENDPTCTRL2_TXI_Pos) /*!< USB0 ENDPTCTRL2: TXI Mask */
+#define USB0_ENDPTCTRL2_TXR_Pos 22 /*!< USB0 ENDPTCTRL2: TXR Position */
+#define USB0_ENDPTCTRL2_TXR_Msk (0x01UL << USB0_ENDPTCTRL2_TXR_Pos) /*!< USB0 ENDPTCTRL2: TXR Mask */
+#define USB0_ENDPTCTRL2_TXE_Pos 23 /*!< USB0 ENDPTCTRL2: TXE Position */
+#define USB0_ENDPTCTRL2_TXE_Msk (0x01UL << USB0_ENDPTCTRL2_TXE_Pos) /*!< USB0 ENDPTCTRL2: TXE Mask */
+
+// ------------------------------------- USB0_ENDPTCTRL3 ----------------------------------------
+#define USB0_ENDPTCTRL3_RXS_Pos 0 /*!< USB0 ENDPTCTRL3: RXS Position */
+#define USB0_ENDPTCTRL3_RXS_Msk (0x01UL << USB0_ENDPTCTRL3_RXS_Pos) /*!< USB0 ENDPTCTRL3: RXS Mask */
+#define USB0_ENDPTCTRL3_RXT_Pos 2 /*!< USB0 ENDPTCTRL3: RXT Position */
+#define USB0_ENDPTCTRL3_RXT_Msk (0x03UL << USB0_ENDPTCTRL3_RXT_Pos) /*!< USB0 ENDPTCTRL3: RXT Mask */
+#define USB0_ENDPTCTRL3_RXI_Pos 5 /*!< USB0 ENDPTCTRL3: RXI Position */
+#define USB0_ENDPTCTRL3_RXI_Msk (0x01UL << USB0_ENDPTCTRL3_RXI_Pos) /*!< USB0 ENDPTCTRL3: RXI Mask */
+#define USB0_ENDPTCTRL3_RXR_Pos 6 /*!< USB0 ENDPTCTRL3: RXR Position */
+#define USB0_ENDPTCTRL3_RXR_Msk (0x01UL << USB0_ENDPTCTRL3_RXR_Pos) /*!< USB0 ENDPTCTRL3: RXR Mask */
+#define USB0_ENDPTCTRL3_RXE_Pos 7 /*!< USB0 ENDPTCTRL3: RXE Position */
+#define USB0_ENDPTCTRL3_RXE_Msk (0x01UL << USB0_ENDPTCTRL3_RXE_Pos) /*!< USB0 ENDPTCTRL3: RXE Mask */
+#define USB0_ENDPTCTRL3_TXS_Pos 16 /*!< USB0 ENDPTCTRL3: TXS Position */
+#define USB0_ENDPTCTRL3_TXS_Msk (0x01UL << USB0_ENDPTCTRL3_TXS_Pos) /*!< USB0 ENDPTCTRL3: TXS Mask */
+#define USB0_ENDPTCTRL3_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL3: TXT1_0 Position */
+#define USB0_ENDPTCTRL3_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL3_TXT1_0_Pos) /*!< USB0 ENDPTCTRL3: TXT1_0 Mask */
+#define USB0_ENDPTCTRL3_TXI_Pos 21 /*!< USB0 ENDPTCTRL3: TXI Position */
+#define USB0_ENDPTCTRL3_TXI_Msk (0x01UL << USB0_ENDPTCTRL3_TXI_Pos) /*!< USB0 ENDPTCTRL3: TXI Mask */
+#define USB0_ENDPTCTRL3_TXR_Pos 22 /*!< USB0 ENDPTCTRL3: TXR Position */
+#define USB0_ENDPTCTRL3_TXR_Msk (0x01UL << USB0_ENDPTCTRL3_TXR_Pos) /*!< USB0 ENDPTCTRL3: TXR Mask */
+#define USB0_ENDPTCTRL3_TXE_Pos 23 /*!< USB0 ENDPTCTRL3: TXE Position */
+#define USB0_ENDPTCTRL3_TXE_Msk (0x01UL << USB0_ENDPTCTRL3_TXE_Pos) /*!< USB0 ENDPTCTRL3: TXE Mask */
+
+// ------------------------------------- USB0_ENDPTCTRL4 ----------------------------------------
+#define USB0_ENDPTCTRL4_RXS_Pos 0 /*!< USB0 ENDPTCTRL4: RXS Position */
+#define USB0_ENDPTCTRL4_RXS_Msk (0x01UL << USB0_ENDPTCTRL4_RXS_Pos) /*!< USB0 ENDPTCTRL4: RXS Mask */
+#define USB0_ENDPTCTRL4_RXT_Pos 2 /*!< USB0 ENDPTCTRL4: RXT Position */
+#define USB0_ENDPTCTRL4_RXT_Msk (0x03UL << USB0_ENDPTCTRL4_RXT_Pos) /*!< USB0 ENDPTCTRL4: RXT Mask */
+#define USB0_ENDPTCTRL4_RXI_Pos 5 /*!< USB0 ENDPTCTRL4: RXI Position */
+#define USB0_ENDPTCTRL4_RXI_Msk (0x01UL << USB0_ENDPTCTRL4_RXI_Pos) /*!< USB0 ENDPTCTRL4: RXI Mask */
+#define USB0_ENDPTCTRL4_RXR_Pos 6 /*!< USB0 ENDPTCTRL4: RXR Position */
+#define USB0_ENDPTCTRL4_RXR_Msk (0x01UL << USB0_ENDPTCTRL4_RXR_Pos) /*!< USB0 ENDPTCTRL4: RXR Mask */
+#define USB0_ENDPTCTRL4_RXE_Pos 7 /*!< USB0 ENDPTCTRL4: RXE Position */
+#define USB0_ENDPTCTRL4_RXE_Msk (0x01UL << USB0_ENDPTCTRL4_RXE_Pos) /*!< USB0 ENDPTCTRL4: RXE Mask */
+#define USB0_ENDPTCTRL4_TXS_Pos 16 /*!< USB0 ENDPTCTRL4: TXS Position */
+#define USB0_ENDPTCTRL4_TXS_Msk (0x01UL << USB0_ENDPTCTRL4_TXS_Pos) /*!< USB0 ENDPTCTRL4: TXS Mask */
+#define USB0_ENDPTCTRL4_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL4: TXT1_0 Position */
+#define USB0_ENDPTCTRL4_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL4_TXT1_0_Pos) /*!< USB0 ENDPTCTRL4: TXT1_0 Mask */
+#define USB0_ENDPTCTRL4_TXI_Pos 21 /*!< USB0 ENDPTCTRL4: TXI Position */
+#define USB0_ENDPTCTRL4_TXI_Msk (0x01UL << USB0_ENDPTCTRL4_TXI_Pos) /*!< USB0 ENDPTCTRL4: TXI Mask */
+#define USB0_ENDPTCTRL4_TXR_Pos 22 /*!< USB0 ENDPTCTRL4: TXR Position */
+#define USB0_ENDPTCTRL4_TXR_Msk (0x01UL << USB0_ENDPTCTRL4_TXR_Pos) /*!< USB0 ENDPTCTRL4: TXR Mask */
+#define USB0_ENDPTCTRL4_TXE_Pos 23 /*!< USB0 ENDPTCTRL4: TXE Position */
+#define USB0_ENDPTCTRL4_TXE_Msk (0x01UL << USB0_ENDPTCTRL4_TXE_Pos) /*!< USB0 ENDPTCTRL4: TXE Mask */
+
+// ------------------------------------- USB0_ENDPTCTRL5 ----------------------------------------
+#define USB0_ENDPTCTRL5_RXS_Pos 0 /*!< USB0 ENDPTCTRL5: RXS Position */
+#define USB0_ENDPTCTRL5_RXS_Msk (0x01UL << USB0_ENDPTCTRL5_RXS_Pos) /*!< USB0 ENDPTCTRL5: RXS Mask */
+#define USB0_ENDPTCTRL5_RXT_Pos 2 /*!< USB0 ENDPTCTRL5: RXT Position */
+#define USB0_ENDPTCTRL5_RXT_Msk (0x03UL << USB0_ENDPTCTRL5_RXT_Pos) /*!< USB0 ENDPTCTRL5: RXT Mask */
+#define USB0_ENDPTCTRL5_RXI_Pos 5 /*!< USB0 ENDPTCTRL5: RXI Position */
+#define USB0_ENDPTCTRL5_RXI_Msk (0x01UL << USB0_ENDPTCTRL5_RXI_Pos) /*!< USB0 ENDPTCTRL5: RXI Mask */
+#define USB0_ENDPTCTRL5_RXR_Pos 6 /*!< USB0 ENDPTCTRL5: RXR Position */
+#define USB0_ENDPTCTRL5_RXR_Msk (0x01UL << USB0_ENDPTCTRL5_RXR_Pos) /*!< USB0 ENDPTCTRL5: RXR Mask */
+#define USB0_ENDPTCTRL5_RXE_Pos 7 /*!< USB0 ENDPTCTRL5: RXE Position */
+#define USB0_ENDPTCTRL5_RXE_Msk (0x01UL << USB0_ENDPTCTRL5_RXE_Pos) /*!< USB0 ENDPTCTRL5: RXE Mask */
+#define USB0_ENDPTCTRL5_TXS_Pos 16 /*!< USB0 ENDPTCTRL5: TXS Position */
+#define USB0_ENDPTCTRL5_TXS_Msk (0x01UL << USB0_ENDPTCTRL5_TXS_Pos) /*!< USB0 ENDPTCTRL5: TXS Mask */
+#define USB0_ENDPTCTRL5_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL5: TXT1_0 Position */
+#define USB0_ENDPTCTRL5_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL5_TXT1_0_Pos) /*!< USB0 ENDPTCTRL5: TXT1_0 Mask */
+#define USB0_ENDPTCTRL5_TXI_Pos 21 /*!< USB0 ENDPTCTRL5: TXI Position */
+#define USB0_ENDPTCTRL5_TXI_Msk (0x01UL << USB0_ENDPTCTRL5_TXI_Pos) /*!< USB0 ENDPTCTRL5: TXI Mask */
+#define USB0_ENDPTCTRL5_TXR_Pos 22 /*!< USB0 ENDPTCTRL5: TXR Position */
+#define USB0_ENDPTCTRL5_TXR_Msk (0x01UL << USB0_ENDPTCTRL5_TXR_Pos) /*!< USB0 ENDPTCTRL5: TXR Mask */
+#define USB0_ENDPTCTRL5_TXE_Pos 23 /*!< USB0 ENDPTCTRL5: TXE Position */
+#define USB0_ENDPTCTRL5_TXE_Msk (0x01UL << USB0_ENDPTCTRL5_TXE_Pos) /*!< USB0 ENDPTCTRL5: TXE Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USB1 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ------------------------------------- USB1_CAPLENGTH -----------------------------------------
+#define USB1_CAPLENGTH_CAPLENGTH_Pos 0 /*!< USB1 CAPLENGTH: CAPLENGTH Position */
+#define USB1_CAPLENGTH_CAPLENGTH_Msk (0x000000ffUL << USB1_CAPLENGTH_CAPLENGTH_Pos) /*!< USB1 CAPLENGTH: CAPLENGTH Mask */
+#define USB1_CAPLENGTH_HCIVERSION_Pos 8 /*!< USB1 CAPLENGTH: HCIVERSION Position */
+#define USB1_CAPLENGTH_HCIVERSION_Msk (0x0000ffffUL << USB1_CAPLENGTH_HCIVERSION_Pos) /*!< USB1 CAPLENGTH: HCIVERSION Mask */
+
+// ------------------------------------- USB1_HCSPARAMS -----------------------------------------
+#define USB1_HCSPARAMS_N_PORTS_Pos 0 /*!< USB1 HCSPARAMS: N_PORTS Position */
+#define USB1_HCSPARAMS_N_PORTS_Msk (0x0fUL << USB1_HCSPARAMS_N_PORTS_Pos) /*!< USB1 HCSPARAMS: N_PORTS Mask */
+#define USB1_HCSPARAMS_PPC_Pos 4 /*!< USB1 HCSPARAMS: PPC Position */
+#define USB1_HCSPARAMS_PPC_Msk (0x01UL << USB1_HCSPARAMS_PPC_Pos) /*!< USB1 HCSPARAMS: PPC Mask */
+#define USB1_HCSPARAMS_N_PCC_Pos 8 /*!< USB1 HCSPARAMS: N_PCC Position */
+#define USB1_HCSPARAMS_N_PCC_Msk (0x0fUL << USB1_HCSPARAMS_N_PCC_Pos) /*!< USB1 HCSPARAMS: N_PCC Mask */
+#define USB1_HCSPARAMS_N_CC_Pos 12 /*!< USB1 HCSPARAMS: N_CC Position */
+#define USB1_HCSPARAMS_N_CC_Msk (0x0fUL << USB1_HCSPARAMS_N_CC_Pos) /*!< USB1 HCSPARAMS: N_CC Mask */
+#define USB1_HCSPARAMS_PI_Pos 16 /*!< USB1 HCSPARAMS: PI Position */
+#define USB1_HCSPARAMS_PI_Msk (0x01UL << USB1_HCSPARAMS_PI_Pos) /*!< USB1 HCSPARAMS: PI Mask */
+#define USB1_HCSPARAMS_N_PTT_Pos 20 /*!< USB1 HCSPARAMS: N_PTT Position */
+#define USB1_HCSPARAMS_N_PTT_Msk (0x0fUL << USB1_HCSPARAMS_N_PTT_Pos) /*!< USB1 HCSPARAMS: N_PTT Mask */
+#define USB1_HCSPARAMS_N_TT_Pos 24 /*!< USB1 HCSPARAMS: N_TT Position */
+#define USB1_HCSPARAMS_N_TT_Msk (0x0fUL << USB1_HCSPARAMS_N_TT_Pos) /*!< USB1 HCSPARAMS: N_TT Mask */
+
+// ------------------------------------- USB1_HCCPARAMS -----------------------------------------
+#define USB1_HCCPARAMS_ADC_Pos 0 /*!< USB1 HCCPARAMS: ADC Position */
+#define USB1_HCCPARAMS_ADC_Msk (0x01UL << USB1_HCCPARAMS_ADC_Pos) /*!< USB1 HCCPARAMS: ADC Mask */
+#define USB1_HCCPARAMS_PFL_Pos 1 /*!< USB1 HCCPARAMS: PFL Position */
+#define USB1_HCCPARAMS_PFL_Msk (0x01UL << USB1_HCCPARAMS_PFL_Pos) /*!< USB1 HCCPARAMS: PFL Mask */
+#define USB1_HCCPARAMS_ASP_Pos 2 /*!< USB1 HCCPARAMS: ASP Position */
+#define USB1_HCCPARAMS_ASP_Msk (0x01UL << USB1_HCCPARAMS_ASP_Pos) /*!< USB1 HCCPARAMS: ASP Mask */
+#define USB1_HCCPARAMS_IST_Pos 4 /*!< USB1 HCCPARAMS: IST Position */
+#define USB1_HCCPARAMS_IST_Msk (0x0fUL << USB1_HCCPARAMS_IST_Pos) /*!< USB1 HCCPARAMS: IST Mask */
+#define USB1_HCCPARAMS_EECP_Pos 8 /*!< USB1 HCCPARAMS: EECP Position */
+#define USB1_HCCPARAMS_EECP_Msk (0x000000ffUL << USB1_HCCPARAMS_EECP_Pos) /*!< USB1 HCCPARAMS: EECP Mask */
+
+// ------------------------------------- USB1_DCIVERSION ----------------------------------------
+#define USB1_DCIVERSION_DCIVERSION_Pos 0 /*!< USB1 DCIVERSION: DCIVERSION Position */
+#define USB1_DCIVERSION_DCIVERSION_Msk (0x0000ffffUL << USB1_DCIVERSION_DCIVERSION_Pos) /*!< USB1 DCIVERSION: DCIVERSION Mask */
+
+// -------------------------------------- USB1_USBCMD_D -----------------------------------------
+#define USB1_USBCMD_D_RS_Pos 0 /*!< USB1 USBCMD_D: RS Position */
+#define USB1_USBCMD_D_RS_Msk (0x01UL << USB1_USBCMD_D_RS_Pos) /*!< USB1 USBCMD_D: RS Mask */
+#define USB1_USBCMD_D_RST_Pos 1 /*!< USB1 USBCMD_D: RST Position */
+#define USB1_USBCMD_D_RST_Msk (0x01UL << USB1_USBCMD_D_RST_Pos) /*!< USB1 USBCMD_D: RST Mask */
+#define USB1_USBCMD_D_SUTW_Pos 13 /*!< USB1 USBCMD_D: SUTW Position */
+#define USB1_USBCMD_D_SUTW_Msk (0x01UL << USB1_USBCMD_D_SUTW_Pos) /*!< USB1 USBCMD_D: SUTW Mask */
+#define USB1_USBCMD_D_ATDTW_Pos 14 /*!< USB1 USBCMD_D: ATDTW Position */
+#define USB1_USBCMD_D_ATDTW_Msk (0x01UL << USB1_USBCMD_D_ATDTW_Pos) /*!< USB1 USBCMD_D: ATDTW Mask */
+#define USB1_USBCMD_D_FS2_Pos 15 /*!< USB1 USBCMD_D: FS2 Position */
+#define USB1_USBCMD_D_FS2_Msk (0x01UL << USB1_USBCMD_D_FS2_Pos) /*!< USB1 USBCMD_D: FS2 Mask */
+#define USB1_USBCMD_D_ITC_Pos 16 /*!< USB1 USBCMD_D: ITC Position */
+#define USB1_USBCMD_D_ITC_Msk (0x000000ffUL << USB1_USBCMD_D_ITC_Pos) /*!< USB1 USBCMD_D: ITC Mask */
+
+// -------------------------------------- USB1_USBCMD_H -----------------------------------------
+#define USB1_USBCMD_H_RS_Pos 0 /*!< USB1 USBCMD_H: RS Position */
+#define USB1_USBCMD_H_RS_Msk (0x01UL << USB1_USBCMD_H_RS_Pos) /*!< USB1 USBCMD_H: RS Mask */
+#define USB1_USBCMD_H_RST_Pos 1 /*!< USB1 USBCMD_H: RST Position */
+#define USB1_USBCMD_H_RST_Msk (0x01UL << USB1_USBCMD_H_RST_Pos) /*!< USB1 USBCMD_H: RST Mask */
+#define USB1_USBCMD_H_FS0_Pos 2 /*!< USB1 USBCMD_H: FS0 Position */
+#define USB1_USBCMD_H_FS0_Msk (0x01UL << USB1_USBCMD_H_FS0_Pos) /*!< USB1 USBCMD_H: FS0 Mask */
+#define USB1_USBCMD_H_FS1_Pos 3 /*!< USB1 USBCMD_H: FS1 Position */
+#define USB1_USBCMD_H_FS1_Msk (0x01UL << USB1_USBCMD_H_FS1_Pos) /*!< USB1 USBCMD_H: FS1 Mask */
+#define USB1_USBCMD_H_PSE_Pos 4 /*!< USB1 USBCMD_H: PSE Position */
+#define USB1_USBCMD_H_PSE_Msk (0x01UL << USB1_USBCMD_H_PSE_Pos) /*!< USB1 USBCMD_H: PSE Mask */
+#define USB1_USBCMD_H_ASE_Pos 5 /*!< USB1 USBCMD_H: ASE Position */
+#define USB1_USBCMD_H_ASE_Msk (0x01UL << USB1_USBCMD_H_ASE_Pos) /*!< USB1 USBCMD_H: ASE Mask */
+#define USB1_USBCMD_H_IAA_Pos 6 /*!< USB1 USBCMD_H: IAA Position */
+#define USB1_USBCMD_H_IAA_Msk (0x01UL << USB1_USBCMD_H_IAA_Pos) /*!< USB1 USBCMD_H: IAA Mask */
+#define USB1_USBCMD_H_ASP1_0_Pos 8 /*!< USB1 USBCMD_H: ASP1_0 Position */
+#define USB1_USBCMD_H_ASP1_0_Msk (0x03UL << USB1_USBCMD_H_ASP1_0_Pos) /*!< USB1 USBCMD_H: ASP1_0 Mask */
+#define USB1_USBCMD_H_ASPE_Pos 11 /*!< USB1 USBCMD_H: ASPE Position */
+#define USB1_USBCMD_H_ASPE_Msk (0x01UL << USB1_USBCMD_H_ASPE_Pos) /*!< USB1 USBCMD_H: ASPE Mask */
+#define USB1_USBCMD_H_FS2_Pos 15 /*!< USB1 USBCMD_H: FS2 Position */
+#define USB1_USBCMD_H_FS2_Msk (0x01UL << USB1_USBCMD_H_FS2_Pos) /*!< USB1 USBCMD_H: FS2 Mask */
+#define USB1_USBCMD_H_ITC_Pos 16 /*!< USB1 USBCMD_H: ITC Position */
+#define USB1_USBCMD_H_ITC_Msk (0x000000ffUL << USB1_USBCMD_H_ITC_Pos) /*!< USB1 USBCMD_H: ITC Mask */
+
+// -------------------------------------- USB1_USBSTS_D -----------------------------------------
+#define USB1_USBSTS_D_UI_Pos 0 /*!< USB1 USBSTS_D: UI Position */
+#define USB1_USBSTS_D_UI_Msk (0x01UL << USB1_USBSTS_D_UI_Pos) /*!< USB1 USBSTS_D: UI Mask */
+#define USB1_USBSTS_D_UEI_Pos 1 /*!< USB1 USBSTS_D: UEI Position */
+#define USB1_USBSTS_D_UEI_Msk (0x01UL << USB1_USBSTS_D_UEI_Pos) /*!< USB1 USBSTS_D: UEI Mask */
+#define USB1_USBSTS_D_PCI_Pos 2 /*!< USB1 USBSTS_D: PCI Position */
+#define USB1_USBSTS_D_PCI_Msk (0x01UL << USB1_USBSTS_D_PCI_Pos) /*!< USB1 USBSTS_D: PCI Mask */
+#define USB1_USBSTS_D_URI_Pos 6 /*!< USB1 USBSTS_D: URI Position */
+#define USB1_USBSTS_D_URI_Msk (0x01UL << USB1_USBSTS_D_URI_Pos) /*!< USB1 USBSTS_D: URI Mask */
+#define USB1_USBSTS_D_SRI_Pos 7 /*!< USB1 USBSTS_D: SRI Position */
+#define USB1_USBSTS_D_SRI_Msk (0x01UL << USB1_USBSTS_D_SRI_Pos) /*!< USB1 USBSTS_D: SRI Mask */
+#define USB1_USBSTS_D_SLI_Pos 8 /*!< USB1 USBSTS_D: SLI Position */
+#define USB1_USBSTS_D_SLI_Msk (0x01UL << USB1_USBSTS_D_SLI_Pos) /*!< USB1 USBSTS_D: SLI Mask */
+#define USB1_USBSTS_D_NAKI_Pos 16 /*!< USB1 USBSTS_D: NAKI Position */
+#define USB1_USBSTS_D_NAKI_Msk (0x01UL << USB1_USBSTS_D_NAKI_Pos) /*!< USB1 USBSTS_D: NAKI Mask */
+
+// -------------------------------------- USB1_USBSTS_H -----------------------------------------
+#define USB1_USBSTS_H_UI_Pos 0 /*!< USB1 USBSTS_H: UI Position */
+#define USB1_USBSTS_H_UI_Msk (0x01UL << USB1_USBSTS_H_UI_Pos) /*!< USB1 USBSTS_H: UI Mask */
+#define USB1_USBSTS_H_UEI_Pos 1 /*!< USB1 USBSTS_H: UEI Position */
+#define USB1_USBSTS_H_UEI_Msk (0x01UL << USB1_USBSTS_H_UEI_Pos) /*!< USB1 USBSTS_H: UEI Mask */
+#define USB1_USBSTS_H_PCI_Pos 2 /*!< USB1 USBSTS_H: PCI Position */
+#define USB1_USBSTS_H_PCI_Msk (0x01UL << USB1_USBSTS_H_PCI_Pos) /*!< USB1 USBSTS_H: PCI Mask */
+#define USB1_USBSTS_H_FRI_Pos 3 /*!< USB1 USBSTS_H: FRI Position */
+#define USB1_USBSTS_H_FRI_Msk (0x01UL << USB1_USBSTS_H_FRI_Pos) /*!< USB1 USBSTS_H: FRI Mask */
+#define USB1_USBSTS_H_AAI_Pos 5 /*!< USB1 USBSTS_H: AAI Position */
+#define USB1_USBSTS_H_AAI_Msk (0x01UL << USB1_USBSTS_H_AAI_Pos) /*!< USB1 USBSTS_H: AAI Mask */
+#define USB1_USBSTS_H_SRI_Pos 7 /*!< USB1 USBSTS_H: SRI Position */
+#define USB1_USBSTS_H_SRI_Msk (0x01UL << USB1_USBSTS_H_SRI_Pos) /*!< USB1 USBSTS_H: SRI Mask */
+#define USB1_USBSTS_H_SLI_Pos 8 /*!< USB1 USBSTS_H: SLI Position */
+#define USB1_USBSTS_H_SLI_Msk (0x01UL << USB1_USBSTS_H_SLI_Pos) /*!< USB1 USBSTS_H: SLI Mask */
+#define USB1_USBSTS_H_HCH_Pos 12 /*!< USB1 USBSTS_H: HCH Position */
+#define USB1_USBSTS_H_HCH_Msk (0x01UL << USB1_USBSTS_H_HCH_Pos) /*!< USB1 USBSTS_H: HCH Mask */
+#define USB1_USBSTS_H_RCL_Pos 13 /*!< USB1 USBSTS_H: RCL Position */
+#define USB1_USBSTS_H_RCL_Msk (0x01UL << USB1_USBSTS_H_RCL_Pos) /*!< USB1 USBSTS_H: RCL Mask */
+#define USB1_USBSTS_H_PS_Pos 14 /*!< USB1 USBSTS_H: PS Position */
+#define USB1_USBSTS_H_PS_Msk (0x01UL << USB1_USBSTS_H_PS_Pos) /*!< USB1 USBSTS_H: PS Mask */
+#define USB1_USBSTS_H_AS_Pos 15 /*!< USB1 USBSTS_H: AS Position */
+#define USB1_USBSTS_H_AS_Msk (0x01UL << USB1_USBSTS_H_AS_Pos) /*!< USB1 USBSTS_H: AS Mask */
+#define USB1_USBSTS_H_UAI_Pos 18 /*!< USB1 USBSTS_H: UAI Position */
+#define USB1_USBSTS_H_UAI_Msk (0x01UL << USB1_USBSTS_H_UAI_Pos) /*!< USB1 USBSTS_H: UAI Mask */
+#define USB1_USBSTS_H_UPI_Pos 19 /*!< USB1 USBSTS_H: UPI Position */
+#define USB1_USBSTS_H_UPI_Msk (0x01UL << USB1_USBSTS_H_UPI_Pos) /*!< USB1 USBSTS_H: UPI Mask */
+
+// ------------------------------------- USB1_USBINTR_D -----------------------------------------
+#define USB1_USBINTR_D_UE_Pos 0 /*!< USB1 USBINTR_D: UE Position */
+#define USB1_USBINTR_D_UE_Msk (0x01UL << USB1_USBINTR_D_UE_Pos) /*!< USB1 USBINTR_D: UE Mask */
+#define USB1_USBINTR_D_UEE_Pos 1 /*!< USB1 USBINTR_D: UEE Position */
+#define USB1_USBINTR_D_UEE_Msk (0x01UL << USB1_USBINTR_D_UEE_Pos) /*!< USB1 USBINTR_D: UEE Mask */
+#define USB1_USBINTR_D_PCE_Pos 2 /*!< USB1 USBINTR_D: PCE Position */
+#define USB1_USBINTR_D_PCE_Msk (0x01UL << USB1_USBINTR_D_PCE_Pos) /*!< USB1 USBINTR_D: PCE Mask */
+#define USB1_USBINTR_D_URE_Pos 6 /*!< USB1 USBINTR_D: URE Position */
+#define USB1_USBINTR_D_URE_Msk (0x01UL << USB1_USBINTR_D_URE_Pos) /*!< USB1 USBINTR_D: URE Mask */
+#define USB1_USBINTR_D_SRE_Pos 7 /*!< USB1 USBINTR_D: SRE Position */
+#define USB1_USBINTR_D_SRE_Msk (0x01UL << USB1_USBINTR_D_SRE_Pos) /*!< USB1 USBINTR_D: SRE Mask */
+#define USB1_USBINTR_D_SLE_Pos 8 /*!< USB1 USBINTR_D: SLE Position */
+#define USB1_USBINTR_D_SLE_Msk (0x01UL << USB1_USBINTR_D_SLE_Pos) /*!< USB1 USBINTR_D: SLE Mask */
+#define USB1_USBINTR_D_NAKE_Pos 16 /*!< USB1 USBINTR_D: NAKE Position */
+#define USB1_USBINTR_D_NAKE_Msk (0x01UL << USB1_USBINTR_D_NAKE_Pos) /*!< USB1 USBINTR_D: NAKE Mask */
+#define USB1_USBINTR_D_UAIE_Pos 18 /*!< USB1 USBINTR_D: UAIE Position */
+#define USB1_USBINTR_D_UAIE_Msk (0x01UL << USB1_USBINTR_D_UAIE_Pos) /*!< USB1 USBINTR_D: UAIE Mask */
+#define USB1_USBINTR_D_UPIA_Pos 19 /*!< USB1 USBINTR_D: UPIA Position */
+#define USB1_USBINTR_D_UPIA_Msk (0x01UL << USB1_USBINTR_D_UPIA_Pos) /*!< USB1 USBINTR_D: UPIA Mask */
+
+// ------------------------------------- USB1_USBINTR_H -----------------------------------------
+#define USB1_USBINTR_H_UE_Pos 0 /*!< USB1 USBINTR_H: UE Position */
+#define USB1_USBINTR_H_UE_Msk (0x01UL << USB1_USBINTR_H_UE_Pos) /*!< USB1 USBINTR_H: UE Mask */
+#define USB1_USBINTR_H_UEE_Pos 1 /*!< USB1 USBINTR_H: UEE Position */
+#define USB1_USBINTR_H_UEE_Msk (0x01UL << USB1_USBINTR_H_UEE_Pos) /*!< USB1 USBINTR_H: UEE Mask */
+#define USB1_USBINTR_H_PCE_Pos 2 /*!< USB1 USBINTR_H: PCE Position */
+#define USB1_USBINTR_H_PCE_Msk (0x01UL << USB1_USBINTR_H_PCE_Pos) /*!< USB1 USBINTR_H: PCE Mask */
+#define USB1_USBINTR_H_FRE_Pos 3 /*!< USB1 USBINTR_H: FRE Position */
+#define USB1_USBINTR_H_FRE_Msk (0x01UL << USB1_USBINTR_H_FRE_Pos) /*!< USB1 USBINTR_H: FRE Mask */
+#define USB1_USBINTR_H_AAE_Pos 5 /*!< USB1 USBINTR_H: AAE Position */
+#define USB1_USBINTR_H_AAE_Msk (0x01UL << USB1_USBINTR_H_AAE_Pos) /*!< USB1 USBINTR_H: AAE Mask */
+#define USB1_USBINTR_H_SRE_Pos 7 /*!< USB1 USBINTR_H: SRE Position */
+#define USB1_USBINTR_H_SRE_Msk (0x01UL << USB1_USBINTR_H_SRE_Pos) /*!< USB1 USBINTR_H: SRE Mask */
+#define USB1_USBINTR_H_UAIE_Pos 18 /*!< USB1 USBINTR_H: UAIE Position */
+#define USB1_USBINTR_H_UAIE_Msk (0x01UL << USB1_USBINTR_H_UAIE_Pos) /*!< USB1 USBINTR_H: UAIE Mask */
+#define USB1_USBINTR_H_UPIA_Pos 19 /*!< USB1 USBINTR_H: UPIA Position */
+#define USB1_USBINTR_H_UPIA_Msk (0x01UL << USB1_USBINTR_H_UPIA_Pos) /*!< USB1 USBINTR_H: UPIA Mask */
+
+// ------------------------------------- USB1_FRINDEX_D -----------------------------------------
+#define USB1_FRINDEX_D_FRINDEX2_0_Pos 0 /*!< USB1 FRINDEX_D: FRINDEX2_0 Position */
+#define USB1_FRINDEX_D_FRINDEX2_0_Msk (0x07UL << USB1_FRINDEX_D_FRINDEX2_0_Pos) /*!< USB1 FRINDEX_D: FRINDEX2_0 Mask */
+#define USB1_FRINDEX_D_FRINDEX13_3_Pos 3 /*!< USB1 FRINDEX_D: FRINDEX13_3 Position */
+#define USB1_FRINDEX_D_FRINDEX13_3_Msk (0x000007ffUL << USB1_FRINDEX_D_FRINDEX13_3_Pos) /*!< USB1 FRINDEX_D: FRINDEX13_3 Mask */
+
+// ------------------------------------- USB1_FRINDEX_H -----------------------------------------
+#define USB1_FRINDEX_H_FRINDEX2_0_Pos 0 /*!< USB1 FRINDEX_H: FRINDEX2_0 Position */
+#define USB1_FRINDEX_H_FRINDEX2_0_Msk (0x07UL << USB1_FRINDEX_H_FRINDEX2_0_Pos) /*!< USB1 FRINDEX_H: FRINDEX2_0 Mask */
+#define USB1_FRINDEX_H_FRINDEX12_3_Pos 3 /*!< USB1 FRINDEX_H: FRINDEX12_3 Position */
+#define USB1_FRINDEX_H_FRINDEX12_3_Msk (0x000003ffUL << USB1_FRINDEX_H_FRINDEX12_3_Pos) /*!< USB1 FRINDEX_H: FRINDEX12_3 Mask */
+
+// ------------------------------------- USB1_DEVICEADDR ----------------------------------------
+#define USB1_DEVICEADDR_USBADRA_Pos 24 /*!< USB1 DEVICEADDR: USBADRA Position */
+#define USB1_DEVICEADDR_USBADRA_Msk (0x01UL << USB1_DEVICEADDR_USBADRA_Pos) /*!< USB1 DEVICEADDR: USBADRA Mask */
+#define USB1_DEVICEADDR_USBADR_Pos 25 /*!< USB1 DEVICEADDR: USBADR Position */
+#define USB1_DEVICEADDR_USBADR_Msk (0x7fUL << USB1_DEVICEADDR_USBADR_Pos) /*!< USB1 DEVICEADDR: USBADR Mask */
+
+// ---------------------------------- USB1_PERIODICLISTBASE -------------------------------------
+#define USB1_PERIODICLISTBASE_PERBASE31_12_Pos 12 /*!< USB1 PERIODICLISTBASE: PERBASE31_12 Position */
+#define USB1_PERIODICLISTBASE_PERBASE31_12_Msk (0x000fffffUL << USB1_PERIODICLISTBASE_PERBASE31_12_Pos) /*!< USB1 PERIODICLISTBASE: PERBASE31_12 Mask */
+
+// ---------------------------------- USB1_ENDPOINTLISTADDR -------------------------------------
+#define USB1_ENDPOINTLISTADDR_EPBASE31_11_Pos 11 /*!< USB1 ENDPOINTLISTADDR: EPBASE31_11 Position */
+#define USB1_ENDPOINTLISTADDR_EPBASE31_11_Msk (0x001fffffUL << USB1_ENDPOINTLISTADDR_EPBASE31_11_Pos) /*!< USB1 ENDPOINTLISTADDR: EPBASE31_11 Mask */
+
+// ----------------------------------- USB1_ASYNCLISTADDR ---------------------------------------
+#define USB1_ASYNCLISTADDR_ASYBASE31_5_Pos 5 /*!< USB1 ASYNCLISTADDR: ASYBASE31_5 Position */
+#define USB1_ASYNCLISTADDR_ASYBASE31_5_Msk (0x07ffffffUL << USB1_ASYNCLISTADDR_ASYBASE31_5_Pos) /*!< USB1 ASYNCLISTADDR: ASYBASE31_5 Mask */
+
+// --------------------------------------- USB1_TTCTRL ------------------------------------------
+#define USB1_TTCTRL_TTHA_Pos 24 /*!< USB1 TTCTRL: TTHA Position */
+#define USB1_TTCTRL_TTHA_Msk (0x7fUL << USB1_TTCTRL_TTHA_Pos) /*!< USB1 TTCTRL: TTHA Mask */
+
+// ------------------------------------- USB1_BURSTSIZE -----------------------------------------
+#define USB1_BURSTSIZE_RXPBURST_Pos 0 /*!< USB1 BURSTSIZE: RXPBURST Position */
+#define USB1_BURSTSIZE_RXPBURST_Msk (0x000000ffUL << USB1_BURSTSIZE_RXPBURST_Pos) /*!< USB1 BURSTSIZE: RXPBURST Mask */
+#define USB1_BURSTSIZE_TXPBURST_Pos 8 /*!< USB1 BURSTSIZE: TXPBURST Position */
+#define USB1_BURSTSIZE_TXPBURST_Msk (0x000000ffUL << USB1_BURSTSIZE_TXPBURST_Pos) /*!< USB1 BURSTSIZE: TXPBURST Mask */
+
+// ------------------------------------ USB1_TXFILLTUNING ---------------------------------------
+#define USB1_TXFILLTUNING_TXSCHOH_Pos 0 /*!< USB1 TXFILLTUNING: TXSCHOH Position */
+#define USB1_TXFILLTUNING_TXSCHOH_Msk (0x000000ffUL << USB1_TXFILLTUNING_TXSCHOH_Pos) /*!< USB1 TXFILLTUNING: TXSCHOH Mask */
+#define USB1_TXFILLTUNING_TXSCHEATLTH_Pos 8 /*!< USB1 TXFILLTUNING: TXSCHEATLTH Position */
+#define USB1_TXFILLTUNING_TXSCHEATLTH_Msk (0x1fUL << USB1_TXFILLTUNING_TXSCHEATLTH_Pos) /*!< USB1 TXFILLTUNING: TXSCHEATLTH Mask */
+#define USB1_TXFILLTUNING_TXFIFOTHRES_Pos 16 /*!< USB1 TXFILLTUNING: TXFIFOTHRES Position */
+#define USB1_TXFILLTUNING_TXFIFOTHRES_Msk (0x3fUL << USB1_TXFILLTUNING_TXFIFOTHRES_Pos) /*!< USB1 TXFILLTUNING: TXFIFOTHRES Mask */
+
+// ------------------------------------ USB1_ULPIVIEWPORT ---------------------------------------
+#define USB1_ULPIVIEWPORT_ULPIDATWR_Pos 0 /*!< USB1 ULPIVIEWPORT: ULPIDATWR Position */
+#define USB1_ULPIVIEWPORT_ULPIDATWR_Msk (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIDATWR_Pos) /*!< USB1 ULPIVIEWPORT: ULPIDATWR Mask */
+#define USB1_ULPIVIEWPORT_ULPIDATRD_Pos 8 /*!< USB1 ULPIVIEWPORT: ULPIDATRD Position */
+#define USB1_ULPIVIEWPORT_ULPIDATRD_Msk (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIDATRD_Pos) /*!< USB1 ULPIVIEWPORT: ULPIDATRD Mask */
+#define USB1_ULPIVIEWPORT_ULPIADDR_Pos 16 /*!< USB1 ULPIVIEWPORT: ULPIADDR Position */
+#define USB1_ULPIVIEWPORT_ULPIADDR_Msk (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIADDR_Pos) /*!< USB1 ULPIVIEWPORT: ULPIADDR Mask */
+#define USB1_ULPIVIEWPORT_ULPIPORT_Pos 24 /*!< USB1 ULPIVIEWPORT: ULPIPORT Position */
+#define USB1_ULPIVIEWPORT_ULPIPORT_Msk (0x07UL << USB1_ULPIVIEWPORT_ULPIPORT_Pos) /*!< USB1 ULPIVIEWPORT: ULPIPORT Mask */
+#define USB1_ULPIVIEWPORT_ULPISS_Pos 27 /*!< USB1 ULPIVIEWPORT: ULPISS Position */
+#define USB1_ULPIVIEWPORT_ULPISS_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPISS_Pos) /*!< USB1 ULPIVIEWPORT: ULPISS Mask */
+#define USB1_ULPIVIEWPORT_ULPIRW_Pos 29 /*!< USB1 ULPIVIEWPORT: ULPIRW Position */
+#define USB1_ULPIVIEWPORT_ULPIRW_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPIRW_Pos) /*!< USB1 ULPIVIEWPORT: ULPIRW Mask */
+#define USB1_ULPIVIEWPORT_ULPIRUN_Pos 30 /*!< USB1 ULPIVIEWPORT: ULPIRUN Position */
+#define USB1_ULPIVIEWPORT_ULPIRUN_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPIRUN_Pos) /*!< USB1 ULPIVIEWPORT: ULPIRUN Mask */
+#define USB1_ULPIVIEWPORT_ULPIWU_Pos 31 /*!< USB1 ULPIVIEWPORT: ULPIWU Position */
+#define USB1_ULPIVIEWPORT_ULPIWU_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPIWU_Pos) /*!< USB1 ULPIVIEWPORT: ULPIWU Mask */
+
+// ------------------------------------- USB1_BINTERVAL -----------------------------------------
+#define USB1_BINTERVAL_BINT_Pos 0 /*!< USB1 BINTERVAL: BINT Position */
+#define USB1_BINTERVAL_BINT_Msk (0x0fUL << USB1_BINTERVAL_BINT_Pos) /*!< USB1 BINTERVAL: BINT Mask */
+
+// -------------------------------------- USB1_ENDPTNAK -----------------------------------------
+#define USB1_ENDPTNAK_EPRN0_Pos 0 /*!< USB1 ENDPTNAK: EPRN0 Position */
+#define USB1_ENDPTNAK_EPRN0_Msk (0x01UL << USB1_ENDPTNAK_EPRN0_Pos) /*!< USB1 ENDPTNAK: EPRN0 Mask */
+#define USB1_ENDPTNAK_EPRN1_Pos 1 /*!< USB1 ENDPTNAK: EPRN1 Position */
+#define USB1_ENDPTNAK_EPRN1_Msk (0x01UL << USB1_ENDPTNAK_EPRN1_Pos) /*!< USB1 ENDPTNAK: EPRN1 Mask */
+#define USB1_ENDPTNAK_EPRN2_Pos 2 /*!< USB1 ENDPTNAK: EPRN2 Position */
+#define USB1_ENDPTNAK_EPRN2_Msk (0x01UL << USB1_ENDPTNAK_EPRN2_Pos) /*!< USB1 ENDPTNAK: EPRN2 Mask */
+#define USB1_ENDPTNAK_EPRN3_Pos 3 /*!< USB1 ENDPTNAK: EPRN3 Position */
+#define USB1_ENDPTNAK_EPRN3_Msk (0x01UL << USB1_ENDPTNAK_EPRN3_Pos) /*!< USB1 ENDPTNAK: EPRN3 Mask */
+#define USB1_ENDPTNAK_EPTN16_Pos 16 /*!< USB1 ENDPTNAK: EPTN16 Position */
+#define USB1_ENDPTNAK_EPTN16_Msk (0x01UL << USB1_ENDPTNAK_EPTN16_Pos) /*!< USB1 ENDPTNAK: EPTN16 Mask */
+#define USB1_ENDPTNAK_EPTN17_Pos 17 /*!< USB1 ENDPTNAK: EPTN17 Position */
+#define USB1_ENDPTNAK_EPTN17_Msk (0x01UL << USB1_ENDPTNAK_EPTN17_Pos) /*!< USB1 ENDPTNAK: EPTN17 Mask */
+#define USB1_ENDPTNAK_EPTN18_Pos 18 /*!< USB1 ENDPTNAK: EPTN18 Position */
+#define USB1_ENDPTNAK_EPTN18_Msk (0x01UL << USB1_ENDPTNAK_EPTN18_Pos) /*!< USB1 ENDPTNAK: EPTN18 Mask */
+#define USB1_ENDPTNAK_EPTN19_Pos 19 /*!< USB1 ENDPTNAK: EPTN19 Position */
+#define USB1_ENDPTNAK_EPTN19_Msk (0x01UL << USB1_ENDPTNAK_EPTN19_Pos) /*!< USB1 ENDPTNAK: EPTN19 Mask */
+
+// ------------------------------------- USB1_ENDPTNAKEN ----------------------------------------
+#define USB1_ENDPTNAKEN_EPRNE0_Pos 0 /*!< USB1 ENDPTNAKEN: EPRNE0 Position */
+#define USB1_ENDPTNAKEN_EPRNE0_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE0_Pos) /*!< USB1 ENDPTNAKEN: EPRNE0 Mask */
+#define USB1_ENDPTNAKEN_EPRNE1_Pos 1 /*!< USB1 ENDPTNAKEN: EPRNE1 Position */
+#define USB1_ENDPTNAKEN_EPRNE1_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE1_Pos) /*!< USB1 ENDPTNAKEN: EPRNE1 Mask */
+#define USB1_ENDPTNAKEN_EPRNE2_Pos 2 /*!< USB1 ENDPTNAKEN: EPRNE2 Position */
+#define USB1_ENDPTNAKEN_EPRNE2_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE2_Pos) /*!< USB1 ENDPTNAKEN: EPRNE2 Mask */
+#define USB1_ENDPTNAKEN_EPRNE3_Pos 3 /*!< USB1 ENDPTNAKEN: EPRNE3 Position */
+#define USB1_ENDPTNAKEN_EPRNE3_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE3_Pos) /*!< USB1 ENDPTNAKEN: EPRNE3 Mask */
+#define USB1_ENDPTNAKEN_EPTNE16_Pos 16 /*!< USB1 ENDPTNAKEN: EPTNE16 Position */
+#define USB1_ENDPTNAKEN_EPTNE16_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE16_Pos) /*!< USB1 ENDPTNAKEN: EPTNE16 Mask */
+#define USB1_ENDPTNAKEN_EPTNE17_Pos 17 /*!< USB1 ENDPTNAKEN: EPTNE17 Position */
+#define USB1_ENDPTNAKEN_EPTNE17_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE17_Pos) /*!< USB1 ENDPTNAKEN: EPTNE17 Mask */
+#define USB1_ENDPTNAKEN_EPTNE18_Pos 18 /*!< USB1 ENDPTNAKEN: EPTNE18 Position */
+#define USB1_ENDPTNAKEN_EPTNE18_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE18_Pos) /*!< USB1 ENDPTNAKEN: EPTNE18 Mask */
+#define USB1_ENDPTNAKEN_EPTNE19_Pos 19 /*!< USB1 ENDPTNAKEN: EPTNE19 Position */
+#define USB1_ENDPTNAKEN_EPTNE19_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE19_Pos) /*!< USB1 ENDPTNAKEN: EPTNE19 Mask */
+
+// ------------------------------------- USB1_PORTSC1_D -----------------------------------------
+#define USB1_PORTSC1_D_CCS_Pos 0 /*!< USB1 PORTSC1_D: CCS Position */
+#define USB1_PORTSC1_D_CCS_Msk (0x01UL << USB1_PORTSC1_D_CCS_Pos) /*!< USB1 PORTSC1_D: CCS Mask */
+#define USB1_PORTSC1_D_CSC_Pos 1 /*!< USB1 PORTSC1_D: CSC Position */
+#define USB1_PORTSC1_D_CSC_Msk (0x01UL << USB1_PORTSC1_D_CSC_Pos) /*!< USB1 PORTSC1_D: CSC Mask */
+#define USB1_PORTSC1_D_PE_Pos 2 /*!< USB1 PORTSC1_D: PE Position */
+#define USB1_PORTSC1_D_PE_Msk (0x01UL << USB1_PORTSC1_D_PE_Pos) /*!< USB1 PORTSC1_D: PE Mask */
+#define USB1_PORTSC1_D_PEC_Pos 3 /*!< USB1 PORTSC1_D: PEC Position */
+#define USB1_PORTSC1_D_PEC_Msk (0x01UL << USB1_PORTSC1_D_PEC_Pos) /*!< USB1 PORTSC1_D: PEC Mask */
+#define USB1_PORTSC1_D_FPR_Pos 6 /*!< USB1 PORTSC1_D: FPR Position */
+#define USB1_PORTSC1_D_FPR_Msk (0x01UL << USB1_PORTSC1_D_FPR_Pos) /*!< USB1 PORTSC1_D: FPR Mask */
+#define USB1_PORTSC1_D_SUSP_Pos 7 /*!< USB1 PORTSC1_D: SUSP Position */
+#define USB1_PORTSC1_D_SUSP_Msk (0x01UL << USB1_PORTSC1_D_SUSP_Pos) /*!< USB1 PORTSC1_D: SUSP Mask */
+#define USB1_PORTSC1_D_PR_Pos 8 /*!< USB1 PORTSC1_D: PR Position */
+#define USB1_PORTSC1_D_PR_Msk (0x01UL << USB1_PORTSC1_D_PR_Pos) /*!< USB1 PORTSC1_D: PR Mask */
+#define USB1_PORTSC1_D_HSP_Pos 9 /*!< USB1 PORTSC1_D: HSP Position */
+#define USB1_PORTSC1_D_HSP_Msk (0x01UL << USB1_PORTSC1_D_HSP_Pos) /*!< USB1 PORTSC1_D: HSP Mask */
+#define USB1_PORTSC1_D_LS_Pos 10 /*!< USB1 PORTSC1_D: LS Position */
+#define USB1_PORTSC1_D_LS_Msk (0x03UL << USB1_PORTSC1_D_LS_Pos) /*!< USB1 PORTSC1_D: LS Mask */
+#define USB1_PORTSC1_D_PP_Pos 12 /*!< USB1 PORTSC1_D: PP Position */
+#define USB1_PORTSC1_D_PP_Msk (0x01UL << USB1_PORTSC1_D_PP_Pos) /*!< USB1 PORTSC1_D: PP Mask */
+#define USB1_PORTSC1_D_PIC1_0_Pos 14 /*!< USB1 PORTSC1_D: PIC1_0 Position */
+#define USB1_PORTSC1_D_PIC1_0_Msk (0x03UL << USB1_PORTSC1_D_PIC1_0_Pos) /*!< USB1 PORTSC1_D: PIC1_0 Mask */
+#define USB1_PORTSC1_D_PTC3_0_Pos 16 /*!< USB1 PORTSC1_D: PTC3_0 Position */
+#define USB1_PORTSC1_D_PTC3_0_Msk (0x0fUL << USB1_PORTSC1_D_PTC3_0_Pos) /*!< USB1 PORTSC1_D: PTC3_0 Mask */
+#define USB1_PORTSC1_D_PHCD_Pos 23 /*!< USB1 PORTSC1_D: PHCD Position */
+#define USB1_PORTSC1_D_PHCD_Msk (0x01UL << USB1_PORTSC1_D_PHCD_Pos) /*!< USB1 PORTSC1_D: PHCD Mask */
+#define USB1_PORTSC1_D_PFSC_Pos 24 /*!< USB1 PORTSC1_D: PFSC Position */
+#define USB1_PORTSC1_D_PFSC_Msk (0x01UL << USB1_PORTSC1_D_PFSC_Pos) /*!< USB1 PORTSC1_D: PFSC Mask */
+#define USB1_PORTSC1_D_PSPD_Pos 26 /*!< USB1 PORTSC1_D: PSPD Position */
+#define USB1_PORTSC1_D_PSPD_Msk (0x03UL << USB1_PORTSC1_D_PSPD_Pos) /*!< USB1 PORTSC1_D: PSPD Mask */
+#define USB1_PORTSC1_D_PTS_Pos 30 /*!< USB1 PORTSC1_D: PTS Position */
+#define USB1_PORTSC1_D_PTS_Msk (0x03UL << USB1_PORTSC1_D_PTS_Pos) /*!< USB1 PORTSC1_D: PTS Mask */
+
+// ------------------------------------- USB1_PORTSC1_H -----------------------------------------
+#define USB1_PORTSC1_H_CCS_Pos 0 /*!< USB1 PORTSC1_H: CCS Position */
+#define USB1_PORTSC1_H_CCS_Msk (0x01UL << USB1_PORTSC1_H_CCS_Pos) /*!< USB1 PORTSC1_H: CCS Mask */
+#define USB1_PORTSC1_H_CSC_Pos 1 /*!< USB1 PORTSC1_H: CSC Position */
+#define USB1_PORTSC1_H_CSC_Msk (0x01UL << USB1_PORTSC1_H_CSC_Pos) /*!< USB1 PORTSC1_H: CSC Mask */
+#define USB1_PORTSC1_H_PE_Pos 2 /*!< USB1 PORTSC1_H: PE Position */
+#define USB1_PORTSC1_H_PE_Msk (0x01UL << USB1_PORTSC1_H_PE_Pos) /*!< USB1 PORTSC1_H: PE Mask */
+#define USB1_PORTSC1_H_PEC_Pos 3 /*!< USB1 PORTSC1_H: PEC Position */
+#define USB1_PORTSC1_H_PEC_Msk (0x01UL << USB1_PORTSC1_H_PEC_Pos) /*!< USB1 PORTSC1_H: PEC Mask */
+#define USB1_PORTSC1_H_OCA_Pos 4 /*!< USB1 PORTSC1_H: OCA Position */
+#define USB1_PORTSC1_H_OCA_Msk (0x01UL << USB1_PORTSC1_H_OCA_Pos) /*!< USB1 PORTSC1_H: OCA Mask */
+#define USB1_PORTSC1_H_OCC_Pos 5 /*!< USB1 PORTSC1_H: OCC Position */
+#define USB1_PORTSC1_H_OCC_Msk (0x01UL << USB1_PORTSC1_H_OCC_Pos) /*!< USB1 PORTSC1_H: OCC Mask */
+#define USB1_PORTSC1_H_FPR_Pos 6 /*!< USB1 PORTSC1_H: FPR Position */
+#define USB1_PORTSC1_H_FPR_Msk (0x01UL << USB1_PORTSC1_H_FPR_Pos) /*!< USB1 PORTSC1_H: FPR Mask */
+#define USB1_PORTSC1_H_SUSP_Pos 7 /*!< USB1 PORTSC1_H: SUSP Position */
+#define USB1_PORTSC1_H_SUSP_Msk (0x01UL << USB1_PORTSC1_H_SUSP_Pos) /*!< USB1 PORTSC1_H: SUSP Mask */
+#define USB1_PORTSC1_H_PR_Pos 8 /*!< USB1 PORTSC1_H: PR Position */
+#define USB1_PORTSC1_H_PR_Msk (0x01UL << USB1_PORTSC1_H_PR_Pos) /*!< USB1 PORTSC1_H: PR Mask */
+#define USB1_PORTSC1_H_HSP_Pos 9 /*!< USB1 PORTSC1_H: HSP Position */
+#define USB1_PORTSC1_H_HSP_Msk (0x01UL << USB1_PORTSC1_H_HSP_Pos) /*!< USB1 PORTSC1_H: HSP Mask */
+#define USB1_PORTSC1_H_LS_Pos 10 /*!< USB1 PORTSC1_H: LS Position */
+#define USB1_PORTSC1_H_LS_Msk (0x03UL << USB1_PORTSC1_H_LS_Pos) /*!< USB1 PORTSC1_H: LS Mask */
+#define USB1_PORTSC1_H_PP_Pos 12 /*!< USB1 PORTSC1_H: PP Position */
+#define USB1_PORTSC1_H_PP_Msk (0x01UL << USB1_PORTSC1_H_PP_Pos) /*!< USB1 PORTSC1_H: PP Mask */
+#define USB1_PORTSC1_H_PIC1_0_Pos 14 /*!< USB1 PORTSC1_H: PIC1_0 Position */
+#define USB1_PORTSC1_H_PIC1_0_Msk (0x03UL << USB1_PORTSC1_H_PIC1_0_Pos) /*!< USB1 PORTSC1_H: PIC1_0 Mask */
+#define USB1_PORTSC1_H_PTC3_0_Pos 16 /*!< USB1 PORTSC1_H: PTC3_0 Position */
+#define USB1_PORTSC1_H_PTC3_0_Msk (0x0fUL << USB1_PORTSC1_H_PTC3_0_Pos) /*!< USB1 PORTSC1_H: PTC3_0 Mask */
+#define USB1_PORTSC1_H_WKCN_Pos 20 /*!< USB1 PORTSC1_H: WKCN Position */
+#define USB1_PORTSC1_H_WKCN_Msk (0x01UL << USB1_PORTSC1_H_WKCN_Pos) /*!< USB1 PORTSC1_H: WKCN Mask */
+#define USB1_PORTSC1_H_WKDC_Pos 21 /*!< USB1 PORTSC1_H: WKDC Position */
+#define USB1_PORTSC1_H_WKDC_Msk (0x01UL << USB1_PORTSC1_H_WKDC_Pos) /*!< USB1 PORTSC1_H: WKDC Mask */
+#define USB1_PORTSC1_H_WKOC_Pos 22 /*!< USB1 PORTSC1_H: WKOC Position */
+#define USB1_PORTSC1_H_WKOC_Msk (0x01UL << USB1_PORTSC1_H_WKOC_Pos) /*!< USB1 PORTSC1_H: WKOC Mask */
+#define USB1_PORTSC1_H_PHCD_Pos 23 /*!< USB1 PORTSC1_H: PHCD Position */
+#define USB1_PORTSC1_H_PHCD_Msk (0x01UL << USB1_PORTSC1_H_PHCD_Pos) /*!< USB1 PORTSC1_H: PHCD Mask */
+#define USB1_PORTSC1_H_PFSC_Pos 24 /*!< USB1 PORTSC1_H: PFSC Position */
+#define USB1_PORTSC1_H_PFSC_Msk (0x01UL << USB1_PORTSC1_H_PFSC_Pos) /*!< USB1 PORTSC1_H: PFSC Mask */
+#define USB1_PORTSC1_H_PSPD_Pos 26 /*!< USB1 PORTSC1_H: PSPD Position */
+#define USB1_PORTSC1_H_PSPD_Msk (0x03UL << USB1_PORTSC1_H_PSPD_Pos) /*!< USB1 PORTSC1_H: PSPD Mask */
+#define USB1_PORTSC1_H_PTS_Pos 30 /*!< USB1 PORTSC1_H: PTS Position */
+#define USB1_PORTSC1_H_PTS_Msk (0x03UL << USB1_PORTSC1_H_PTS_Pos) /*!< USB1 PORTSC1_H: PTS Mask */
+
+// ------------------------------------- USB1_USBMODE_D -----------------------------------------
+#define USB1_USBMODE_D_CM1_0_Pos 0 /*!< USB1 USBMODE_D: CM1_0 Position */
+#define USB1_USBMODE_D_CM1_0_Msk (0x03UL << USB1_USBMODE_D_CM1_0_Pos) /*!< USB1 USBMODE_D: CM1_0 Mask */
+#define USB1_USBMODE_D_ES_Pos 2 /*!< USB1 USBMODE_D: ES Position */
+#define USB1_USBMODE_D_ES_Msk (0x01UL << USB1_USBMODE_D_ES_Pos) /*!< USB1 USBMODE_D: ES Mask */
+#define USB1_USBMODE_D_SLOM_Pos 3 /*!< USB1 USBMODE_D: SLOM Position */
+#define USB1_USBMODE_D_SLOM_Msk (0x01UL << USB1_USBMODE_D_SLOM_Pos) /*!< USB1 USBMODE_D: SLOM Mask */
+#define USB1_USBMODE_D_SDIS_Pos 4 /*!< USB1 USBMODE_D: SDIS Position */
+#define USB1_USBMODE_D_SDIS_Msk (0x01UL << USB1_USBMODE_D_SDIS_Pos) /*!< USB1 USBMODE_D: SDIS Mask */
+
+// ------------------------------------- USB1_USBMODE_H -----------------------------------------
+#define USB1_USBMODE_H_CM1_0_Pos 0 /*!< USB1 USBMODE_H: CM1_0 Position */
+#define USB1_USBMODE_H_CM1_0_Msk (0x03UL << USB1_USBMODE_H_CM1_0_Pos) /*!< USB1 USBMODE_H: CM1_0 Mask */
+#define USB1_USBMODE_H_ES_Pos 2 /*!< USB1 USBMODE_H: ES Position */
+#define USB1_USBMODE_H_ES_Msk (0x01UL << USB1_USBMODE_H_ES_Pos) /*!< USB1 USBMODE_H: ES Mask */
+#define USB1_USBMODE_H_SDIS_Pos 4 /*!< USB1 USBMODE_H: SDIS Position */
+#define USB1_USBMODE_H_SDIS_Msk (0x01UL << USB1_USBMODE_H_SDIS_Pos) /*!< USB1 USBMODE_H: SDIS Mask */
+#define USB1_USBMODE_H_VBPS_Pos 5 /*!< USB1 USBMODE_H: VBPS Position */
+#define USB1_USBMODE_H_VBPS_Msk (0x01UL << USB1_USBMODE_H_VBPS_Pos) /*!< USB1 USBMODE_H: VBPS Mask */
+
+// ----------------------------------- USB1_ENDPTSETUPSTAT --------------------------------------
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos 0 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Position */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Mask */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos 1 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Position */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Mask */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos 2 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Position */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Mask */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos 3 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Position */
+#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Mask */
+
+// ------------------------------------- USB1_ENDPTPRIME ----------------------------------------
+#define USB1_ENDPTPRIME_PERB0_Pos 0 /*!< USB1 ENDPTPRIME: PERB0 Position */
+#define USB1_ENDPTPRIME_PERB0_Msk (0x01UL << USB1_ENDPTPRIME_PERB0_Pos) /*!< USB1 ENDPTPRIME: PERB0 Mask */
+#define USB1_ENDPTPRIME_PERB1_Pos 1 /*!< USB1 ENDPTPRIME: PERB1 Position */
+#define USB1_ENDPTPRIME_PERB1_Msk (0x01UL << USB1_ENDPTPRIME_PERB1_Pos) /*!< USB1 ENDPTPRIME: PERB1 Mask */
+#define USB1_ENDPTPRIME_PERB2_Pos 2 /*!< USB1 ENDPTPRIME: PERB2 Position */
+#define USB1_ENDPTPRIME_PERB2_Msk (0x01UL << USB1_ENDPTPRIME_PERB2_Pos) /*!< USB1 ENDPTPRIME: PERB2 Mask */
+#define USB1_ENDPTPRIME_PERB3_Pos 3 /*!< USB1 ENDPTPRIME: PERB3 Position */
+#define USB1_ENDPTPRIME_PERB3_Msk (0x01UL << USB1_ENDPTPRIME_PERB3_Pos) /*!< USB1 ENDPTPRIME: PERB3 Mask */
+#define USB1_ENDPTPRIME_PETB0_Pos 16 /*!< USB1 ENDPTPRIME: PETB0 Position */
+#define USB1_ENDPTPRIME_PETB0_Msk (0x01UL << USB1_ENDPTPRIME_PETB0_Pos) /*!< USB1 ENDPTPRIME: PETB0 Mask */
+#define USB1_ENDPTPRIME_PETB1_Pos 17 /*!< USB1 ENDPTPRIME: PETB1 Position */
+#define USB1_ENDPTPRIME_PETB1_Msk (0x01UL << USB1_ENDPTPRIME_PETB1_Pos) /*!< USB1 ENDPTPRIME: PETB1 Mask */
+#define USB1_ENDPTPRIME_PETB2_Pos 18 /*!< USB1 ENDPTPRIME: PETB2 Position */
+#define USB1_ENDPTPRIME_PETB2_Msk (0x01UL << USB1_ENDPTPRIME_PETB2_Pos) /*!< USB1 ENDPTPRIME: PETB2 Mask */
+#define USB1_ENDPTPRIME_PETB3_Pos 19 /*!< USB1 ENDPTPRIME: PETB3 Position */
+#define USB1_ENDPTPRIME_PETB3_Msk (0x01UL << USB1_ENDPTPRIME_PETB3_Pos) /*!< USB1 ENDPTPRIME: PETB3 Mask */
+
+// ------------------------------------- USB1_ENDPTFLUSH ----------------------------------------
+#define USB1_ENDPTFLUSH_FERB0_Pos 0 /*!< USB1 ENDPTFLUSH: FERB0 Position */
+#define USB1_ENDPTFLUSH_FERB0_Msk (0x01UL << USB1_ENDPTFLUSH_FERB0_Pos) /*!< USB1 ENDPTFLUSH: FERB0 Mask */
+#define USB1_ENDPTFLUSH_FERB1_Pos 1 /*!< USB1 ENDPTFLUSH: FERB1 Position */
+#define USB1_ENDPTFLUSH_FERB1_Msk (0x01UL << USB1_ENDPTFLUSH_FERB1_Pos) /*!< USB1 ENDPTFLUSH: FERB1 Mask */
+#define USB1_ENDPTFLUSH_FERB2_Pos 2 /*!< USB1 ENDPTFLUSH: FERB2 Position */
+#define USB1_ENDPTFLUSH_FERB2_Msk (0x01UL << USB1_ENDPTFLUSH_FERB2_Pos) /*!< USB1 ENDPTFLUSH: FERB2 Mask */
+#define USB1_ENDPTFLUSH_FERB3_Pos 3 /*!< USB1 ENDPTFLUSH: FERB3 Position */
+#define USB1_ENDPTFLUSH_FERB3_Msk (0x01UL << USB1_ENDPTFLUSH_FERB3_Pos) /*!< USB1 ENDPTFLUSH: FERB3 Mask */
+#define USB1_ENDPTFLUSH_FETB0_Pos 16 /*!< USB1 ENDPTFLUSH: FETB0 Position */
+#define USB1_ENDPTFLUSH_FETB0_Msk (0x01UL << USB1_ENDPTFLUSH_FETB0_Pos) /*!< USB1 ENDPTFLUSH: FETB0 Mask */
+#define USB1_ENDPTFLUSH_FETB1_Pos 17 /*!< USB1 ENDPTFLUSH: FETB1 Position */
+#define USB1_ENDPTFLUSH_FETB1_Msk (0x01UL << USB1_ENDPTFLUSH_FETB1_Pos) /*!< USB1 ENDPTFLUSH: FETB1 Mask */
+#define USB1_ENDPTFLUSH_FETB2_Pos 18 /*!< USB1 ENDPTFLUSH: FETB2 Position */
+#define USB1_ENDPTFLUSH_FETB2_Msk (0x01UL << USB1_ENDPTFLUSH_FETB2_Pos) /*!< USB1 ENDPTFLUSH: FETB2 Mask */
+#define USB1_ENDPTFLUSH_FETB3_Pos 19 /*!< USB1 ENDPTFLUSH: FETB3 Position */
+#define USB1_ENDPTFLUSH_FETB3_Msk (0x01UL << USB1_ENDPTFLUSH_FETB3_Pos) /*!< USB1 ENDPTFLUSH: FETB3 Mask */
+
+// ------------------------------------- USB1_ENDPTSTAT -----------------------------------------
+#define USB1_ENDPTSTAT_ERBR0_Pos 0 /*!< USB1 ENDPTSTAT: ERBR0 Position */
+#define USB1_ENDPTSTAT_ERBR0_Msk (0x01UL << USB1_ENDPTSTAT_ERBR0_Pos) /*!< USB1 ENDPTSTAT: ERBR0 Mask */
+#define USB1_ENDPTSTAT_ERBR1_Pos 1 /*!< USB1 ENDPTSTAT: ERBR1 Position */
+#define USB1_ENDPTSTAT_ERBR1_Msk (0x01UL << USB1_ENDPTSTAT_ERBR1_Pos) /*!< USB1 ENDPTSTAT: ERBR1 Mask */
+#define USB1_ENDPTSTAT_ERBR2_Pos 2 /*!< USB1 ENDPTSTAT: ERBR2 Position */
+#define USB1_ENDPTSTAT_ERBR2_Msk (0x01UL << USB1_ENDPTSTAT_ERBR2_Pos) /*!< USB1 ENDPTSTAT: ERBR2 Mask */
+#define USB1_ENDPTSTAT_ERBR3_Pos 3 /*!< USB1 ENDPTSTAT: ERBR3 Position */
+#define USB1_ENDPTSTAT_ERBR3_Msk (0x01UL << USB1_ENDPTSTAT_ERBR3_Pos) /*!< USB1 ENDPTSTAT: ERBR3 Mask */
+#define USB1_ENDPTSTAT_ETBR0_Pos 16 /*!< USB1 ENDPTSTAT: ETBR0 Position */
+#define USB1_ENDPTSTAT_ETBR0_Msk (0x01UL << USB1_ENDPTSTAT_ETBR0_Pos) /*!< USB1 ENDPTSTAT: ETBR0 Mask */
+#define USB1_ENDPTSTAT_ETBR1_Pos 17 /*!< USB1 ENDPTSTAT: ETBR1 Position */
+#define USB1_ENDPTSTAT_ETBR1_Msk (0x01UL << USB1_ENDPTSTAT_ETBR1_Pos) /*!< USB1 ENDPTSTAT: ETBR1 Mask */
+#define USB1_ENDPTSTAT_ETBR2_Pos 18 /*!< USB1 ENDPTSTAT: ETBR2 Position */
+#define USB1_ENDPTSTAT_ETBR2_Msk (0x01UL << USB1_ENDPTSTAT_ETBR2_Pos) /*!< USB1 ENDPTSTAT: ETBR2 Mask */
+#define USB1_ENDPTSTAT_ETBR3_Pos 19 /*!< USB1 ENDPTSTAT: ETBR3 Position */
+#define USB1_ENDPTSTAT_ETBR3_Msk (0x01UL << USB1_ENDPTSTAT_ETBR3_Pos) /*!< USB1 ENDPTSTAT: ETBR3 Mask */
+
+// ----------------------------------- USB1_ENDPTCOMPLETE ---------------------------------------
+#define USB1_ENDPTCOMPLETE_ERCE0_Pos 0 /*!< USB1 ENDPTCOMPLETE: ERCE0 Position */
+#define USB1_ENDPTCOMPLETE_ERCE0_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE0_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE0 Mask */
+#define USB1_ENDPTCOMPLETE_ERCE1_Pos 1 /*!< USB1 ENDPTCOMPLETE: ERCE1 Position */
+#define USB1_ENDPTCOMPLETE_ERCE1_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE1_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE1 Mask */
+#define USB1_ENDPTCOMPLETE_ERCE2_Pos 2 /*!< USB1 ENDPTCOMPLETE: ERCE2 Position */
+#define USB1_ENDPTCOMPLETE_ERCE2_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE2_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE2 Mask */
+#define USB1_ENDPTCOMPLETE_ERCE3_Pos 3 /*!< USB1 ENDPTCOMPLETE: ERCE3 Position */
+#define USB1_ENDPTCOMPLETE_ERCE3_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE3_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE3 Mask */
+#define USB1_ENDPTCOMPLETE_ETCE0_Pos 16 /*!< USB1 ENDPTCOMPLETE: ETCE0 Position */
+#define USB1_ENDPTCOMPLETE_ETCE0_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE0_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE0 Mask */
+#define USB1_ENDPTCOMPLETE_ETCE1_Pos 17 /*!< USB1 ENDPTCOMPLETE: ETCE1 Position */
+#define USB1_ENDPTCOMPLETE_ETCE1_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE1_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE1 Mask */
+#define USB1_ENDPTCOMPLETE_ETCE2_Pos 18 /*!< USB1 ENDPTCOMPLETE: ETCE2 Position */
+#define USB1_ENDPTCOMPLETE_ETCE2_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE2_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE2 Mask */
+#define USB1_ENDPTCOMPLETE_ETCE3_Pos 19 /*!< USB1 ENDPTCOMPLETE: ETCE3 Position */
+#define USB1_ENDPTCOMPLETE_ETCE3_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE3_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE3 Mask */
+
+// ------------------------------------- USB1_ENDPTCTRL0 ----------------------------------------
+#define USB1_ENDPTCTRL0_RXS_Pos 0 /*!< USB1 ENDPTCTRL0: RXS Position */
+#define USB1_ENDPTCTRL0_RXS_Msk (0x01UL << USB1_ENDPTCTRL0_RXS_Pos) /*!< USB1 ENDPTCTRL0: RXS Mask */
+#define USB1_ENDPTCTRL0_RXT_Pos 2 /*!< USB1 ENDPTCTRL0: RXT Position */
+#define USB1_ENDPTCTRL0_RXT_Msk (0x03UL << USB1_ENDPTCTRL0_RXT_Pos) /*!< USB1 ENDPTCTRL0: RXT Mask */
+#define USB1_ENDPTCTRL0_RXE_Pos 7 /*!< USB1 ENDPTCTRL0: RXE Position */
+#define USB1_ENDPTCTRL0_RXE_Msk (0x01UL << USB1_ENDPTCTRL0_RXE_Pos) /*!< USB1 ENDPTCTRL0: RXE Mask */
+#define USB1_ENDPTCTRL0_TXS_Pos 16 /*!< USB1 ENDPTCTRL0: TXS Position */
+#define USB1_ENDPTCTRL0_TXS_Msk (0x01UL << USB1_ENDPTCTRL0_TXS_Pos) /*!< USB1 ENDPTCTRL0: TXS Mask */
+#define USB1_ENDPTCTRL0_TXT_Pos 18 /*!< USB1 ENDPTCTRL0: TXT Position */
+#define USB1_ENDPTCTRL0_TXT_Msk (0x03UL << USB1_ENDPTCTRL0_TXT_Pos) /*!< USB1 ENDPTCTRL0: TXT Mask */
+#define USB1_ENDPTCTRL0_TXE_Pos 23 /*!< USB1 ENDPTCTRL0: TXE Position */
+#define USB1_ENDPTCTRL0_TXE_Msk (0x01UL << USB1_ENDPTCTRL0_TXE_Pos) /*!< USB1 ENDPTCTRL0: TXE Mask */
+
+// ------------------------------------- USB1_ENDPTCTRL1 ----------------------------------------
+#define USB1_ENDPTCTRL1_RXS_Pos 0 /*!< USB1 ENDPTCTRL1: RXS Position */
+#define USB1_ENDPTCTRL1_RXS_Msk (0x01UL << USB1_ENDPTCTRL1_RXS_Pos) /*!< USB1 ENDPTCTRL1: RXS Mask */
+#define USB1_ENDPTCTRL1_RXT_Pos 2 /*!< USB1 ENDPTCTRL1: RXT Position */
+#define USB1_ENDPTCTRL1_RXT_Msk (0x03UL << USB1_ENDPTCTRL1_RXT_Pos) /*!< USB1 ENDPTCTRL1: RXT Mask */
+#define USB1_ENDPTCTRL1_RXI_Pos 5 /*!< USB1 ENDPTCTRL1: RXI Position */
+#define USB1_ENDPTCTRL1_RXI_Msk (0x01UL << USB1_ENDPTCTRL1_RXI_Pos) /*!< USB1 ENDPTCTRL1: RXI Mask */
+#define USB1_ENDPTCTRL1_RXR_Pos 6 /*!< USB1 ENDPTCTRL1: RXR Position */
+#define USB1_ENDPTCTRL1_RXR_Msk (0x01UL << USB1_ENDPTCTRL1_RXR_Pos) /*!< USB1 ENDPTCTRL1: RXR Mask */
+#define USB1_ENDPTCTRL1_RXE_Pos 7 /*!< USB1 ENDPTCTRL1: RXE Position */
+#define USB1_ENDPTCTRL1_RXE_Msk (0x01UL << USB1_ENDPTCTRL1_RXE_Pos) /*!< USB1 ENDPTCTRL1: RXE Mask */
+#define USB1_ENDPTCTRL1_TXS_Pos 16 /*!< USB1 ENDPTCTRL1: TXS Position */
+#define USB1_ENDPTCTRL1_TXS_Msk (0x01UL << USB1_ENDPTCTRL1_TXS_Pos) /*!< USB1 ENDPTCTRL1: TXS Mask */
+#define USB1_ENDPTCTRL1_TXT_Pos 18 /*!< USB1 ENDPTCTRL1: TXT Position */
+#define USB1_ENDPTCTRL1_TXT_Msk (0x03UL << USB1_ENDPTCTRL1_TXT_Pos) /*!< USB1 ENDPTCTRL1: TXT Mask */
+#define USB1_ENDPTCTRL1_TXI_Pos 21 /*!< USB1 ENDPTCTRL1: TXI Position */
+#define USB1_ENDPTCTRL1_TXI_Msk (0x01UL << USB1_ENDPTCTRL1_TXI_Pos) /*!< USB1 ENDPTCTRL1: TXI Mask */
+#define USB1_ENDPTCTRL1_TXR_Pos 22 /*!< USB1 ENDPTCTRL1: TXR Position */
+#define USB1_ENDPTCTRL1_TXR_Msk (0x01UL << USB1_ENDPTCTRL1_TXR_Pos) /*!< USB1 ENDPTCTRL1: TXR Mask */
+#define USB1_ENDPTCTRL1_TXE_Pos 23 /*!< USB1 ENDPTCTRL1: TXE Position */
+#define USB1_ENDPTCTRL1_TXE_Msk (0x01UL << USB1_ENDPTCTRL1_TXE_Pos) /*!< USB1 ENDPTCTRL1: TXE Mask */
+
+// ------------------------------------- USB1_ENDPTCTRL2 ----------------------------------------
+#define USB1_ENDPTCTRL2_RXS_Pos 0 /*!< USB1 ENDPTCTRL2: RXS Position */
+#define USB1_ENDPTCTRL2_RXS_Msk (0x01UL << USB1_ENDPTCTRL2_RXS_Pos) /*!< USB1 ENDPTCTRL2: RXS Mask */
+#define USB1_ENDPTCTRL2_RXT_Pos 2 /*!< USB1 ENDPTCTRL2: RXT Position */
+#define USB1_ENDPTCTRL2_RXT_Msk (0x03UL << USB1_ENDPTCTRL2_RXT_Pos) /*!< USB1 ENDPTCTRL2: RXT Mask */
+#define USB1_ENDPTCTRL2_RXI_Pos 5 /*!< USB1 ENDPTCTRL2: RXI Position */
+#define USB1_ENDPTCTRL2_RXI_Msk (0x01UL << USB1_ENDPTCTRL2_RXI_Pos) /*!< USB1 ENDPTCTRL2: RXI Mask */
+#define USB1_ENDPTCTRL2_RXR_Pos 6 /*!< USB1 ENDPTCTRL2: RXR Position */
+#define USB1_ENDPTCTRL2_RXR_Msk (0x01UL << USB1_ENDPTCTRL2_RXR_Pos) /*!< USB1 ENDPTCTRL2: RXR Mask */
+#define USB1_ENDPTCTRL2_RXE_Pos 7 /*!< USB1 ENDPTCTRL2: RXE Position */
+#define USB1_ENDPTCTRL2_RXE_Msk (0x01UL << USB1_ENDPTCTRL2_RXE_Pos) /*!< USB1 ENDPTCTRL2: RXE Mask */
+#define USB1_ENDPTCTRL2_TXS_Pos 16 /*!< USB1 ENDPTCTRL2: TXS Position */
+#define USB1_ENDPTCTRL2_TXS_Msk (0x01UL << USB1_ENDPTCTRL2_TXS_Pos) /*!< USB1 ENDPTCTRL2: TXS Mask */
+#define USB1_ENDPTCTRL2_TXT_Pos 18 /*!< USB1 ENDPTCTRL2: TXT Position */
+#define USB1_ENDPTCTRL2_TXT_Msk (0x03UL << USB1_ENDPTCTRL2_TXT_Pos) /*!< USB1 ENDPTCTRL2: TXT Mask */
+#define USB1_ENDPTCTRL2_TXI_Pos 21 /*!< USB1 ENDPTCTRL2: TXI Position */
+#define USB1_ENDPTCTRL2_TXI_Msk (0x01UL << USB1_ENDPTCTRL2_TXI_Pos) /*!< USB1 ENDPTCTRL2: TXI Mask */
+#define USB1_ENDPTCTRL2_TXR_Pos 22 /*!< USB1 ENDPTCTRL2: TXR Position */
+#define USB1_ENDPTCTRL2_TXR_Msk (0x01UL << USB1_ENDPTCTRL2_TXR_Pos) /*!< USB1 ENDPTCTRL2: TXR Mask */
+#define USB1_ENDPTCTRL2_TXE_Pos 23 /*!< USB1 ENDPTCTRL2: TXE Position */
+#define USB1_ENDPTCTRL2_TXE_Msk (0x01UL << USB1_ENDPTCTRL2_TXE_Pos) /*!< USB1 ENDPTCTRL2: TXE Mask */
+
+// ------------------------------------- USB1_ENDPTCTRL3 ----------------------------------------
+#define USB1_ENDPTCTRL3_RXS_Pos 0 /*!< USB1 ENDPTCTRL3: RXS Position */
+#define USB1_ENDPTCTRL3_RXS_Msk (0x01UL << USB1_ENDPTCTRL3_RXS_Pos) /*!< USB1 ENDPTCTRL3: RXS Mask */
+#define USB1_ENDPTCTRL3_RXT_Pos 2 /*!< USB1 ENDPTCTRL3: RXT Position */
+#define USB1_ENDPTCTRL3_RXT_Msk (0x03UL << USB1_ENDPTCTRL3_RXT_Pos) /*!< USB1 ENDPTCTRL3: RXT Mask */
+#define USB1_ENDPTCTRL3_RXI_Pos 5 /*!< USB1 ENDPTCTRL3: RXI Position */
+#define USB1_ENDPTCTRL3_RXI_Msk (0x01UL << USB1_ENDPTCTRL3_RXI_Pos) /*!< USB1 ENDPTCTRL3: RXI Mask */
+#define USB1_ENDPTCTRL3_RXR_Pos 6 /*!< USB1 ENDPTCTRL3: RXR Position */
+#define USB1_ENDPTCTRL3_RXR_Msk (0x01UL << USB1_ENDPTCTRL3_RXR_Pos) /*!< USB1 ENDPTCTRL3: RXR Mask */
+#define USB1_ENDPTCTRL3_RXE_Pos 7 /*!< USB1 ENDPTCTRL3: RXE Position */
+#define USB1_ENDPTCTRL3_RXE_Msk (0x01UL << USB1_ENDPTCTRL3_RXE_Pos) /*!< USB1 ENDPTCTRL3: RXE Mask */
+#define USB1_ENDPTCTRL3_TXS_Pos 16 /*!< USB1 ENDPTCTRL3: TXS Position */
+#define USB1_ENDPTCTRL3_TXS_Msk (0x01UL << USB1_ENDPTCTRL3_TXS_Pos) /*!< USB1 ENDPTCTRL3: TXS Mask */
+#define USB1_ENDPTCTRL3_TXT_Pos 18 /*!< USB1 ENDPTCTRL3: TXT Position */
+#define USB1_ENDPTCTRL3_TXT_Msk (0x03UL << USB1_ENDPTCTRL3_TXT_Pos) /*!< USB1 ENDPTCTRL3: TXT Mask */
+#define USB1_ENDPTCTRL3_TXI_Pos 21 /*!< USB1 ENDPTCTRL3: TXI Position */
+#define USB1_ENDPTCTRL3_TXI_Msk (0x01UL << USB1_ENDPTCTRL3_TXI_Pos) /*!< USB1 ENDPTCTRL3: TXI Mask */
+#define USB1_ENDPTCTRL3_TXR_Pos 22 /*!< USB1 ENDPTCTRL3: TXR Position */
+#define USB1_ENDPTCTRL3_TXR_Msk (0x01UL << USB1_ENDPTCTRL3_TXR_Pos) /*!< USB1 ENDPTCTRL3: TXR Mask */
+#define USB1_ENDPTCTRL3_TXE_Pos 23 /*!< USB1 ENDPTCTRL3: TXE Position */
+#define USB1_ENDPTCTRL3_TXE_Msk (0x01UL << USB1_ENDPTCTRL3_TXE_Pos) /*!< USB1 ENDPTCTRL3: TXE Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- LCD Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------- LCD_TIMH --------------------------------------------
+#define LCD_TIMH_PPL_Pos 2 /*!< LCD TIMH: PPL Position */
+#define LCD_TIMH_PPL_Msk (0x3fUL << LCD_TIMH_PPL_Pos) /*!< LCD TIMH: PPL Mask */
+#define LCD_TIMH_HSW_Pos 8 /*!< LCD TIMH: HSW Position */
+#define LCD_TIMH_HSW_Msk (0x000000ffUL << LCD_TIMH_HSW_Pos) /*!< LCD TIMH: HSW Mask */
+#define LCD_TIMH_HFP_Pos 16 /*!< LCD TIMH: HFP Position */
+#define LCD_TIMH_HFP_Msk (0x000000ffUL << LCD_TIMH_HFP_Pos) /*!< LCD TIMH: HFP Mask */
+#define LCD_TIMH_HBP_Pos 24 /*!< LCD TIMH: HBP Position */
+#define LCD_TIMH_HBP_Msk (0x000000ffUL << LCD_TIMH_HBP_Pos) /*!< LCD TIMH: HBP Mask */
+
+// ---------------------------------------- LCD_TIMV --------------------------------------------
+#define LCD_TIMV_LPP_Pos 0 /*!< LCD TIMV: LPP Position */
+#define LCD_TIMV_LPP_Msk (0x000003ffUL << LCD_TIMV_LPP_Pos) /*!< LCD TIMV: LPP Mask */
+#define LCD_TIMV_VSW_Pos 10 /*!< LCD TIMV: VSW Position */
+#define LCD_TIMV_VSW_Msk (0x3fUL << LCD_TIMV_VSW_Pos) /*!< LCD TIMV: VSW Mask */
+#define LCD_TIMV_VFP_Pos 16 /*!< LCD TIMV: VFP Position */
+#define LCD_TIMV_VFP_Msk (0x000000ffUL << LCD_TIMV_VFP_Pos) /*!< LCD TIMV: VFP Mask */
+#define LCD_TIMV_VBP_Pos 24 /*!< LCD TIMV: VBP Position */
+#define LCD_TIMV_VBP_Msk (0x000000ffUL << LCD_TIMV_VBP_Pos) /*!< LCD TIMV: VBP Mask */
+
+// ----------------------------------------- LCD_POL --------------------------------------------
+#define LCD_POL_PCD_LO_Pos 0 /*!< LCD POL: PCD_LO Position */
+#define LCD_POL_PCD_LO_Msk (0x1fUL << LCD_POL_PCD_LO_Pos) /*!< LCD POL: PCD_LO Mask */
+#define LCD_POL_CLKSEL_Pos 5 /*!< LCD POL: CLKSEL Position */
+#define LCD_POL_CLKSEL_Msk (0x01UL << LCD_POL_CLKSEL_Pos) /*!< LCD POL: CLKSEL Mask */
+#define LCD_POL_ACB_Pos 6 /*!< LCD POL: ACB Position */
+#define LCD_POL_ACB_Msk (0x1fUL << LCD_POL_ACB_Pos) /*!< LCD POL: ACB Mask */
+#define LCD_POL_IVS_Pos 11 /*!< LCD POL: IVS Position */
+#define LCD_POL_IVS_Msk (0x01UL << LCD_POL_IVS_Pos) /*!< LCD POL: IVS Mask */
+#define LCD_POL_IHS_Pos 12 /*!< LCD POL: IHS Position */
+#define LCD_POL_IHS_Msk (0x01UL << LCD_POL_IHS_Pos) /*!< LCD POL: IHS Mask */
+#define LCD_POL_IPC_Pos 13 /*!< LCD POL: IPC Position */
+#define LCD_POL_IPC_Msk (0x01UL << LCD_POL_IPC_Pos) /*!< LCD POL: IPC Mask */
+#define LCD_POL_IOE_Pos 14 /*!< LCD POL: IOE Position */
+#define LCD_POL_IOE_Msk (0x01UL << LCD_POL_IOE_Pos) /*!< LCD POL: IOE Mask */
+#define LCD_POL_CPL_Pos 16 /*!< LCD POL: CPL Position */
+#define LCD_POL_CPL_Msk (0x000003ffUL << LCD_POL_CPL_Pos) /*!< LCD POL: CPL Mask */
+#define LCD_POL_BCD_Pos 26 /*!< LCD POL: BCD Position */
+#define LCD_POL_BCD_Msk (0x01UL << LCD_POL_BCD_Pos) /*!< LCD POL: BCD Mask */
+#define LCD_POL_PCD_HI_Pos 27 /*!< LCD POL: PCD_HI Position */
+#define LCD_POL_PCD_HI_Msk (0x1fUL << LCD_POL_PCD_HI_Pos) /*!< LCD POL: PCD_HI Mask */
+
+// ----------------------------------------- LCD_LE ---------------------------------------------
+#define LCD_LE_LED_Pos 0 /*!< LCD LE: LED Position */
+#define LCD_LE_LED_Msk (0x7fUL << LCD_LE_LED_Pos) /*!< LCD LE: LED Mask */
+#define LCD_LE_LEE_Pos 16 /*!< LCD LE: LEE Position */
+#define LCD_LE_LEE_Msk (0x01UL << LCD_LE_LEE_Pos) /*!< LCD LE: LEE Mask */
+
+// --------------------------------------- LCD_UPBASE -------------------------------------------
+#define LCD_UPBASE_LCDUPBASE_Pos 3 /*!< LCD UPBASE: LCDUPBASE Position */
+#define LCD_UPBASE_LCDUPBASE_Msk (0x1fffffffUL << LCD_UPBASE_LCDUPBASE_Pos) /*!< LCD UPBASE: LCDUPBASE Mask */
+
+// --------------------------------------- LCD_LPBASE -------------------------------------------
+#define LCD_LPBASE_LCDLPBASE_Pos 3 /*!< LCD LPBASE: LCDLPBASE Position */
+#define LCD_LPBASE_LCDLPBASE_Msk (0x1fffffffUL << LCD_LPBASE_LCDLPBASE_Pos) /*!< LCD LPBASE: LCDLPBASE Mask */
+
+// ---------------------------------------- LCD_CTRL --------------------------------------------
+#define LCD_CTRL_LCDEN_Pos 0 /*!< LCD CTRL: LCDEN Position */
+#define LCD_CTRL_LCDEN_Msk (0x01UL << LCD_CTRL_LCDEN_Pos) /*!< LCD CTRL: LCDEN Mask */
+#define LCD_CTRL_LCDBPP_Pos 1 /*!< LCD CTRL: LCDBPP Position */
+#define LCD_CTRL_LCDBPP_Msk (0x07UL << LCD_CTRL_LCDBPP_Pos) /*!< LCD CTRL: LCDBPP Mask */
+#define LCD_CTRL_LCDBW_Pos 4 /*!< LCD CTRL: LCDBW Position */
+#define LCD_CTRL_LCDBW_Msk (0x01UL << LCD_CTRL_LCDBW_Pos) /*!< LCD CTRL: LCDBW Mask */
+#define LCD_CTRL_LCDTFT_Pos 5 /*!< LCD CTRL: LCDTFT Position */
+#define LCD_CTRL_LCDTFT_Msk (0x01UL << LCD_CTRL_LCDTFT_Pos) /*!< LCD CTRL: LCDTFT Mask */
+#define LCD_CTRL_LCDMONO8_Pos 6 /*!< LCD CTRL: LCDMONO8 Position */
+#define LCD_CTRL_LCDMONO8_Msk (0x01UL << LCD_CTRL_LCDMONO8_Pos) /*!< LCD CTRL: LCDMONO8 Mask */
+#define LCD_CTRL_LCDDUAL_Pos 7 /*!< LCD CTRL: LCDDUAL Position */
+#define LCD_CTRL_LCDDUAL_Msk (0x01UL << LCD_CTRL_LCDDUAL_Pos) /*!< LCD CTRL: LCDDUAL Mask */
+#define LCD_CTRL_BGR_Pos 8 /*!< LCD CTRL: BGR Position */
+#define LCD_CTRL_BGR_Msk (0x01UL << LCD_CTRL_BGR_Pos) /*!< LCD CTRL: BGR Mask */
+#define LCD_CTRL_BEBO_Pos 9 /*!< LCD CTRL: BEBO Position */
+#define LCD_CTRL_BEBO_Msk (0x01UL << LCD_CTRL_BEBO_Pos) /*!< LCD CTRL: BEBO Mask */
+#define LCD_CTRL_BEPO_Pos 10 /*!< LCD CTRL: BEPO Position */
+#define LCD_CTRL_BEPO_Msk (0x01UL << LCD_CTRL_BEPO_Pos) /*!< LCD CTRL: BEPO Mask */
+#define LCD_CTRL_LCDPWR_Pos 11 /*!< LCD CTRL: LCDPWR Position */
+#define LCD_CTRL_LCDPWR_Msk (0x01UL << LCD_CTRL_LCDPWR_Pos) /*!< LCD CTRL: LCDPWR Mask */
+#define LCD_CTRL_LCDVCOMP_Pos 12 /*!< LCD CTRL: LCDVCOMP Position */
+#define LCD_CTRL_LCDVCOMP_Msk (0x03UL << LCD_CTRL_LCDVCOMP_Pos) /*!< LCD CTRL: LCDVCOMP Mask */
+#define LCD_CTRL_WATERMARK_Pos 16 /*!< LCD CTRL: WATERMARK Position */
+#define LCD_CTRL_WATERMARK_Msk (0x01UL << LCD_CTRL_WATERMARK_Pos) /*!< LCD CTRL: WATERMARK Mask */
+
+// --------------------------------------- LCD_INTMSK -------------------------------------------
+#define LCD_INTMSK_FUFIM_Pos 1 /*!< LCD INTMSK: FUFIM Position */
+#define LCD_INTMSK_FUFIM_Msk (0x01UL << LCD_INTMSK_FUFIM_Pos) /*!< LCD INTMSK: FUFIM Mask */
+#define LCD_INTMSK_LNBUIM_Pos 2 /*!< LCD INTMSK: LNBUIM Position */
+#define LCD_INTMSK_LNBUIM_Msk (0x01UL << LCD_INTMSK_LNBUIM_Pos) /*!< LCD INTMSK: LNBUIM Mask */
+#define LCD_INTMSK_VCOMPIM_Pos 3 /*!< LCD INTMSK: VCOMPIM Position */
+#define LCD_INTMSK_VCOMPIM_Msk (0x01UL << LCD_INTMSK_VCOMPIM_Pos) /*!< LCD INTMSK: VCOMPIM Mask */
+#define LCD_INTMSK_BERIM_Pos 4 /*!< LCD INTMSK: BERIM Position */
+#define LCD_INTMSK_BERIM_Msk (0x01UL << LCD_INTMSK_BERIM_Pos) /*!< LCD INTMSK: BERIM Mask */
+
+// --------------------------------------- LCD_INTRAW -------------------------------------------
+#define LCD_INTRAW_FUFRIS_Pos 1 /*!< LCD INTRAW: FUFRIS Position */
+#define LCD_INTRAW_FUFRIS_Msk (0x01UL << LCD_INTRAW_FUFRIS_Pos) /*!< LCD INTRAW: FUFRIS Mask */
+#define LCD_INTRAW_LNBURIS_Pos 2 /*!< LCD INTRAW: LNBURIS Position */
+#define LCD_INTRAW_LNBURIS_Msk (0x01UL << LCD_INTRAW_LNBURIS_Pos) /*!< LCD INTRAW: LNBURIS Mask */
+#define LCD_INTRAW_VCOMPRIS_Pos 3 /*!< LCD INTRAW: VCOMPRIS Position */
+#define LCD_INTRAW_VCOMPRIS_Msk (0x01UL << LCD_INTRAW_VCOMPRIS_Pos) /*!< LCD INTRAW: VCOMPRIS Mask */
+#define LCD_INTRAW_BERRAW_Pos 4 /*!< LCD INTRAW: BERRAW Position */
+#define LCD_INTRAW_BERRAW_Msk (0x01UL << LCD_INTRAW_BERRAW_Pos) /*!< LCD INTRAW: BERRAW Mask */
+
+// --------------------------------------- LCD_INTSTAT ------------------------------------------
+#define LCD_INTSTAT_FUFMIS_Pos 1 /*!< LCD INTSTAT: FUFMIS Position */
+#define LCD_INTSTAT_FUFMIS_Msk (0x01UL << LCD_INTSTAT_FUFMIS_Pos) /*!< LCD INTSTAT: FUFMIS Mask */
+#define LCD_INTSTAT_LNBUMIS_Pos 2 /*!< LCD INTSTAT: LNBUMIS Position */
+#define LCD_INTSTAT_LNBUMIS_Msk (0x01UL << LCD_INTSTAT_LNBUMIS_Pos) /*!< LCD INTSTAT: LNBUMIS Mask */
+#define LCD_INTSTAT_VCOMPMIS_Pos 3 /*!< LCD INTSTAT: VCOMPMIS Position */
+#define LCD_INTSTAT_VCOMPMIS_Msk (0x01UL << LCD_INTSTAT_VCOMPMIS_Pos) /*!< LCD INTSTAT: VCOMPMIS Mask */
+#define LCD_INTSTAT_BERMIS_Pos 4 /*!< LCD INTSTAT: BERMIS Position */
+#define LCD_INTSTAT_BERMIS_Msk (0x01UL << LCD_INTSTAT_BERMIS_Pos) /*!< LCD INTSTAT: BERMIS Mask */
+
+// --------------------------------------- LCD_INTCLR -------------------------------------------
+#define LCD_INTCLR_FUFIC_Pos 1 /*!< LCD INTCLR: FUFIC Position */
+#define LCD_INTCLR_FUFIC_Msk (0x01UL << LCD_INTCLR_FUFIC_Pos) /*!< LCD INTCLR: FUFIC Mask */
+#define LCD_INTCLR_LNBUIC_Pos 2 /*!< LCD INTCLR: LNBUIC Position */
+#define LCD_INTCLR_LNBUIC_Msk (0x01UL << LCD_INTCLR_LNBUIC_Pos) /*!< LCD INTCLR: LNBUIC Mask */
+#define LCD_INTCLR_VCOMPIC_Pos 3 /*!< LCD INTCLR: VCOMPIC Position */
+#define LCD_INTCLR_VCOMPIC_Msk (0x01UL << LCD_INTCLR_VCOMPIC_Pos) /*!< LCD INTCLR: VCOMPIC Mask */
+#define LCD_INTCLR_BERIC_Pos 4 /*!< LCD INTCLR: BERIC Position */
+#define LCD_INTCLR_BERIC_Msk (0x01UL << LCD_INTCLR_BERIC_Pos) /*!< LCD INTCLR: BERIC Mask */
+
+// --------------------------------------- LCD_UPCURR -------------------------------------------
+#define LCD_UPCURR_LCDUPCURR_Pos 0 /*!< LCD UPCURR: LCDUPCURR Position */
+#define LCD_UPCURR_LCDUPCURR_Msk (0xffffffffUL << LCD_UPCURR_LCDUPCURR_Pos) /*!< LCD UPCURR: LCDUPCURR Mask */
+
+// --------------------------------------- LCD_LPCURR -------------------------------------------
+#define LCD_LPCURR_LCDLPCURR_Pos 0 /*!< LCD LPCURR: LCDLPCURR Position */
+#define LCD_LPCURR_LCDLPCURR_Msk (0xffffffffUL << LCD_LPCURR_LCDLPCURR_Pos) /*!< LCD LPCURR: LCDLPCURR Mask */
+
+// ---------------------------------------- LCD_PAL0 --------------------------------------------
+#define LCD_PAL0_R04_0_Pos 0 /*!< LCD PAL0: R04_0 Position */
+#define LCD_PAL0_R04_0_Msk (0x1fUL << LCD_PAL0_R04_0_Pos) /*!< LCD PAL0: R04_0 Mask */
+#define LCD_PAL0_G04_0_Pos 5 /*!< LCD PAL0: G04_0 Position */
+#define LCD_PAL0_G04_0_Msk (0x1fUL << LCD_PAL0_G04_0_Pos) /*!< LCD PAL0: G04_0 Mask */
+#define LCD_PAL0_B04_0_Pos 10 /*!< LCD PAL0: B04_0 Position */
+#define LCD_PAL0_B04_0_Msk (0x1fUL << LCD_PAL0_B04_0_Pos) /*!< LCD PAL0: B04_0 Mask */
+#define LCD_PAL0_I0_Pos 15 /*!< LCD PAL0: I0 Position */
+#define LCD_PAL0_I0_Msk (0x01UL << LCD_PAL0_I0_Pos) /*!< LCD PAL0: I0 Mask */
+#define LCD_PAL0_R14_0_Pos 16 /*!< LCD PAL0: R14_0 Position */
+#define LCD_PAL0_R14_0_Msk (0x1fUL << LCD_PAL0_R14_0_Pos) /*!< LCD PAL0: R14_0 Mask */
+#define LCD_PAL0_G14_0_Pos 21 /*!< LCD PAL0: G14_0 Position */
+#define LCD_PAL0_G14_0_Msk (0x1fUL << LCD_PAL0_G14_0_Pos) /*!< LCD PAL0: G14_0 Mask */
+#define LCD_PAL0_B14_0_Pos 26 /*!< LCD PAL0: B14_0 Position */
+#define LCD_PAL0_B14_0_Msk (0x1fUL << LCD_PAL0_B14_0_Pos) /*!< LCD PAL0: B14_0 Mask */
+#define LCD_PAL0_I1_Pos 31 /*!< LCD PAL0: I1 Position */
+#define LCD_PAL0_I1_Msk (0x01UL << LCD_PAL0_I1_Pos) /*!< LCD PAL0: I1 Mask */
+
+// ---------------------------------------- LCD_PAL1 --------------------------------------------
+#define LCD_PAL1_R04_0_Pos 0 /*!< LCD PAL1: R04_0 Position */
+#define LCD_PAL1_R04_0_Msk (0x1fUL << LCD_PAL1_R04_0_Pos) /*!< LCD PAL1: R04_0 Mask */
+#define LCD_PAL1_G04_0_Pos 5 /*!< LCD PAL1: G04_0 Position */
+#define LCD_PAL1_G04_0_Msk (0x1fUL << LCD_PAL1_G04_0_Pos) /*!< LCD PAL1: G04_0 Mask */
+#define LCD_PAL1_B04_0_Pos 10 /*!< LCD PAL1: B04_0 Position */
+#define LCD_PAL1_B04_0_Msk (0x1fUL << LCD_PAL1_B04_0_Pos) /*!< LCD PAL1: B04_0 Mask */
+#define LCD_PAL1_I0_Pos 15 /*!< LCD PAL1: I0 Position */
+#define LCD_PAL1_I0_Msk (0x01UL << LCD_PAL1_I0_Pos) /*!< LCD PAL1: I0 Mask */
+#define LCD_PAL1_R14_0_Pos 16 /*!< LCD PAL1: R14_0 Position */
+#define LCD_PAL1_R14_0_Msk (0x1fUL << LCD_PAL1_R14_0_Pos) /*!< LCD PAL1: R14_0 Mask */
+#define LCD_PAL1_G14_0_Pos 21 /*!< LCD PAL1: G14_0 Position */
+#define LCD_PAL1_G14_0_Msk (0x1fUL << LCD_PAL1_G14_0_Pos) /*!< LCD PAL1: G14_0 Mask */
+#define LCD_PAL1_B14_0_Pos 26 /*!< LCD PAL1: B14_0 Position */
+#define LCD_PAL1_B14_0_Msk (0x1fUL << LCD_PAL1_B14_0_Pos) /*!< LCD PAL1: B14_0 Mask */
+#define LCD_PAL1_I1_Pos 31 /*!< LCD PAL1: I1 Position */
+#define LCD_PAL1_I1_Msk (0x01UL << LCD_PAL1_I1_Pos) /*!< LCD PAL1: I1 Mask */
+
+// ---------------------------------------- LCD_PAL2 --------------------------------------------
+#define LCD_PAL2_R04_0_Pos 0 /*!< LCD PAL2: R04_0 Position */
+#define LCD_PAL2_R04_0_Msk (0x1fUL << LCD_PAL2_R04_0_Pos) /*!< LCD PAL2: R04_0 Mask */
+#define LCD_PAL2_G04_0_Pos 5 /*!< LCD PAL2: G04_0 Position */
+#define LCD_PAL2_G04_0_Msk (0x1fUL << LCD_PAL2_G04_0_Pos) /*!< LCD PAL2: G04_0 Mask */
+#define LCD_PAL2_B04_0_Pos 10 /*!< LCD PAL2: B04_0 Position */
+#define LCD_PAL2_B04_0_Msk (0x1fUL << LCD_PAL2_B04_0_Pos) /*!< LCD PAL2: B04_0 Mask */
+#define LCD_PAL2_I0_Pos 15 /*!< LCD PAL2: I0 Position */
+#define LCD_PAL2_I0_Msk (0x01UL << LCD_PAL2_I0_Pos) /*!< LCD PAL2: I0 Mask */
+#define LCD_PAL2_R14_0_Pos 16 /*!< LCD PAL2: R14_0 Position */
+#define LCD_PAL2_R14_0_Msk (0x1fUL << LCD_PAL2_R14_0_Pos) /*!< LCD PAL2: R14_0 Mask */
+#define LCD_PAL2_G14_0_Pos 21 /*!< LCD PAL2: G14_0 Position */
+#define LCD_PAL2_G14_0_Msk (0x1fUL << LCD_PAL2_G14_0_Pos) /*!< LCD PAL2: G14_0 Mask */
+#define LCD_PAL2_B14_0_Pos 26 /*!< LCD PAL2: B14_0 Position */
+#define LCD_PAL2_B14_0_Msk (0x1fUL << LCD_PAL2_B14_0_Pos) /*!< LCD PAL2: B14_0 Mask */
+#define LCD_PAL2_I1_Pos 31 /*!< LCD PAL2: I1 Position */
+#define LCD_PAL2_I1_Msk (0x01UL << LCD_PAL2_I1_Pos) /*!< LCD PAL2: I1 Mask */
+
+// ---------------------------------------- LCD_PAL3 --------------------------------------------
+#define LCD_PAL3_R04_0_Pos 0 /*!< LCD PAL3: R04_0 Position */
+#define LCD_PAL3_R04_0_Msk (0x1fUL << LCD_PAL3_R04_0_Pos) /*!< LCD PAL3: R04_0 Mask */
+#define LCD_PAL3_G04_0_Pos 5 /*!< LCD PAL3: G04_0 Position */
+#define LCD_PAL3_G04_0_Msk (0x1fUL << LCD_PAL3_G04_0_Pos) /*!< LCD PAL3: G04_0 Mask */
+#define LCD_PAL3_B04_0_Pos 10 /*!< LCD PAL3: B04_0 Position */
+#define LCD_PAL3_B04_0_Msk (0x1fUL << LCD_PAL3_B04_0_Pos) /*!< LCD PAL3: B04_0 Mask */
+#define LCD_PAL3_I0_Pos 15 /*!< LCD PAL3: I0 Position */
+#define LCD_PAL3_I0_Msk (0x01UL << LCD_PAL3_I0_Pos) /*!< LCD PAL3: I0 Mask */
+#define LCD_PAL3_R14_0_Pos 16 /*!< LCD PAL3: R14_0 Position */
+#define LCD_PAL3_R14_0_Msk (0x1fUL << LCD_PAL3_R14_0_Pos) /*!< LCD PAL3: R14_0 Mask */
+#define LCD_PAL3_G14_0_Pos 21 /*!< LCD PAL3: G14_0 Position */
+#define LCD_PAL3_G14_0_Msk (0x1fUL << LCD_PAL3_G14_0_Pos) /*!< LCD PAL3: G14_0 Mask */
+#define LCD_PAL3_B14_0_Pos 26 /*!< LCD PAL3: B14_0 Position */
+#define LCD_PAL3_B14_0_Msk (0x1fUL << LCD_PAL3_B14_0_Pos) /*!< LCD PAL3: B14_0 Mask */
+#define LCD_PAL3_I1_Pos 31 /*!< LCD PAL3: I1 Position */
+#define LCD_PAL3_I1_Msk (0x01UL << LCD_PAL3_I1_Pos) /*!< LCD PAL3: I1 Mask */
+
+// ---------------------------------------- LCD_PAL4 --------------------------------------------
+#define LCD_PAL4_R04_0_Pos 0 /*!< LCD PAL4: R04_0 Position */
+#define LCD_PAL4_R04_0_Msk (0x1fUL << LCD_PAL4_R04_0_Pos) /*!< LCD PAL4: R04_0 Mask */
+#define LCD_PAL4_G04_0_Pos 5 /*!< LCD PAL4: G04_0 Position */
+#define LCD_PAL4_G04_0_Msk (0x1fUL << LCD_PAL4_G04_0_Pos) /*!< LCD PAL4: G04_0 Mask */
+#define LCD_PAL4_B04_0_Pos 10 /*!< LCD PAL4: B04_0 Position */
+#define LCD_PAL4_B04_0_Msk (0x1fUL << LCD_PAL4_B04_0_Pos) /*!< LCD PAL4: B04_0 Mask */
+#define LCD_PAL4_I0_Pos 15 /*!< LCD PAL4: I0 Position */
+#define LCD_PAL4_I0_Msk (0x01UL << LCD_PAL4_I0_Pos) /*!< LCD PAL4: I0 Mask */
+#define LCD_PAL4_R14_0_Pos 16 /*!< LCD PAL4: R14_0 Position */
+#define LCD_PAL4_R14_0_Msk (0x1fUL << LCD_PAL4_R14_0_Pos) /*!< LCD PAL4: R14_0 Mask */
+#define LCD_PAL4_G14_0_Pos 21 /*!< LCD PAL4: G14_0 Position */
+#define LCD_PAL4_G14_0_Msk (0x1fUL << LCD_PAL4_G14_0_Pos) /*!< LCD PAL4: G14_0 Mask */
+#define LCD_PAL4_B14_0_Pos 26 /*!< LCD PAL4: B14_0 Position */
+#define LCD_PAL4_B14_0_Msk (0x1fUL << LCD_PAL4_B14_0_Pos) /*!< LCD PAL4: B14_0 Mask */
+#define LCD_PAL4_I1_Pos 31 /*!< LCD PAL4: I1 Position */
+#define LCD_PAL4_I1_Msk (0x01UL << LCD_PAL4_I1_Pos) /*!< LCD PAL4: I1 Mask */
+
+// ---------------------------------------- LCD_PAL5 --------------------------------------------
+#define LCD_PAL5_R04_0_Pos 0 /*!< LCD PAL5: R04_0 Position */
+#define LCD_PAL5_R04_0_Msk (0x1fUL << LCD_PAL5_R04_0_Pos) /*!< LCD PAL5: R04_0 Mask */
+#define LCD_PAL5_G04_0_Pos 5 /*!< LCD PAL5: G04_0 Position */
+#define LCD_PAL5_G04_0_Msk (0x1fUL << LCD_PAL5_G04_0_Pos) /*!< LCD PAL5: G04_0 Mask */
+#define LCD_PAL5_B04_0_Pos 10 /*!< LCD PAL5: B04_0 Position */
+#define LCD_PAL5_B04_0_Msk (0x1fUL << LCD_PAL5_B04_0_Pos) /*!< LCD PAL5: B04_0 Mask */
+#define LCD_PAL5_I0_Pos 15 /*!< LCD PAL5: I0 Position */
+#define LCD_PAL5_I0_Msk (0x01UL << LCD_PAL5_I0_Pos) /*!< LCD PAL5: I0 Mask */
+#define LCD_PAL5_R14_0_Pos 16 /*!< LCD PAL5: R14_0 Position */
+#define LCD_PAL5_R14_0_Msk (0x1fUL << LCD_PAL5_R14_0_Pos) /*!< LCD PAL5: R14_0 Mask */
+#define LCD_PAL5_G14_0_Pos 21 /*!< LCD PAL5: G14_0 Position */
+#define LCD_PAL5_G14_0_Msk (0x1fUL << LCD_PAL5_G14_0_Pos) /*!< LCD PAL5: G14_0 Mask */
+#define LCD_PAL5_B14_0_Pos 26 /*!< LCD PAL5: B14_0 Position */
+#define LCD_PAL5_B14_0_Msk (0x1fUL << LCD_PAL5_B14_0_Pos) /*!< LCD PAL5: B14_0 Mask */
+#define LCD_PAL5_I1_Pos 31 /*!< LCD PAL5: I1 Position */
+#define LCD_PAL5_I1_Msk (0x01UL << LCD_PAL5_I1_Pos) /*!< LCD PAL5: I1 Mask */
+
+// ---------------------------------------- LCD_PAL6 --------------------------------------------
+#define LCD_PAL6_R04_0_Pos 0 /*!< LCD PAL6: R04_0 Position */
+#define LCD_PAL6_R04_0_Msk (0x1fUL << LCD_PAL6_R04_0_Pos) /*!< LCD PAL6: R04_0 Mask */
+#define LCD_PAL6_G04_0_Pos 5 /*!< LCD PAL6: G04_0 Position */
+#define LCD_PAL6_G04_0_Msk (0x1fUL << LCD_PAL6_G04_0_Pos) /*!< LCD PAL6: G04_0 Mask */
+#define LCD_PAL6_B04_0_Pos 10 /*!< LCD PAL6: B04_0 Position */
+#define LCD_PAL6_B04_0_Msk (0x1fUL << LCD_PAL6_B04_0_Pos) /*!< LCD PAL6: B04_0 Mask */
+#define LCD_PAL6_I0_Pos 15 /*!< LCD PAL6: I0 Position */
+#define LCD_PAL6_I0_Msk (0x01UL << LCD_PAL6_I0_Pos) /*!< LCD PAL6: I0 Mask */
+#define LCD_PAL6_R14_0_Pos 16 /*!< LCD PAL6: R14_0 Position */
+#define LCD_PAL6_R14_0_Msk (0x1fUL << LCD_PAL6_R14_0_Pos) /*!< LCD PAL6: R14_0 Mask */
+#define LCD_PAL6_G14_0_Pos 21 /*!< LCD PAL6: G14_0 Position */
+#define LCD_PAL6_G14_0_Msk (0x1fUL << LCD_PAL6_G14_0_Pos) /*!< LCD PAL6: G14_0 Mask */
+#define LCD_PAL6_B14_0_Pos 26 /*!< LCD PAL6: B14_0 Position */
+#define LCD_PAL6_B14_0_Msk (0x1fUL << LCD_PAL6_B14_0_Pos) /*!< LCD PAL6: B14_0 Mask */
+#define LCD_PAL6_I1_Pos 31 /*!< LCD PAL6: I1 Position */
+#define LCD_PAL6_I1_Msk (0x01UL << LCD_PAL6_I1_Pos) /*!< LCD PAL6: I1 Mask */
+
+// ---------------------------------------- LCD_PAL7 --------------------------------------------
+#define LCD_PAL7_R04_0_Pos 0 /*!< LCD PAL7: R04_0 Position */
+#define LCD_PAL7_R04_0_Msk (0x1fUL << LCD_PAL7_R04_0_Pos) /*!< LCD PAL7: R04_0 Mask */
+#define LCD_PAL7_G04_0_Pos 5 /*!< LCD PAL7: G04_0 Position */
+#define LCD_PAL7_G04_0_Msk (0x1fUL << LCD_PAL7_G04_0_Pos) /*!< LCD PAL7: G04_0 Mask */
+#define LCD_PAL7_B04_0_Pos 10 /*!< LCD PAL7: B04_0 Position */
+#define LCD_PAL7_B04_0_Msk (0x1fUL << LCD_PAL7_B04_0_Pos) /*!< LCD PAL7: B04_0 Mask */
+#define LCD_PAL7_I0_Pos 15 /*!< LCD PAL7: I0 Position */
+#define LCD_PAL7_I0_Msk (0x01UL << LCD_PAL7_I0_Pos) /*!< LCD PAL7: I0 Mask */
+#define LCD_PAL7_R14_0_Pos 16 /*!< LCD PAL7: R14_0 Position */
+#define LCD_PAL7_R14_0_Msk (0x1fUL << LCD_PAL7_R14_0_Pos) /*!< LCD PAL7: R14_0 Mask */
+#define LCD_PAL7_G14_0_Pos 21 /*!< LCD PAL7: G14_0 Position */
+#define LCD_PAL7_G14_0_Msk (0x1fUL << LCD_PAL7_G14_0_Pos) /*!< LCD PAL7: G14_0 Mask */
+#define LCD_PAL7_B14_0_Pos 26 /*!< LCD PAL7: B14_0 Position */
+#define LCD_PAL7_B14_0_Msk (0x1fUL << LCD_PAL7_B14_0_Pos) /*!< LCD PAL7: B14_0 Mask */
+#define LCD_PAL7_I1_Pos 31 /*!< LCD PAL7: I1 Position */
+#define LCD_PAL7_I1_Msk (0x01UL << LCD_PAL7_I1_Pos) /*!< LCD PAL7: I1 Mask */
+
+// ---------------------------------------- LCD_PAL8 --------------------------------------------
+#define LCD_PAL8_R04_0_Pos 0 /*!< LCD PAL8: R04_0 Position */
+#define LCD_PAL8_R04_0_Msk (0x1fUL << LCD_PAL8_R04_0_Pos) /*!< LCD PAL8: R04_0 Mask */
+#define LCD_PAL8_G04_0_Pos 5 /*!< LCD PAL8: G04_0 Position */
+#define LCD_PAL8_G04_0_Msk (0x1fUL << LCD_PAL8_G04_0_Pos) /*!< LCD PAL8: G04_0 Mask */
+#define LCD_PAL8_B04_0_Pos 10 /*!< LCD PAL8: B04_0 Position */
+#define LCD_PAL8_B04_0_Msk (0x1fUL << LCD_PAL8_B04_0_Pos) /*!< LCD PAL8: B04_0 Mask */
+#define LCD_PAL8_I0_Pos 15 /*!< LCD PAL8: I0 Position */
+#define LCD_PAL8_I0_Msk (0x01UL << LCD_PAL8_I0_Pos) /*!< LCD PAL8: I0 Mask */
+#define LCD_PAL8_R14_0_Pos 16 /*!< LCD PAL8: R14_0 Position */
+#define LCD_PAL8_R14_0_Msk (0x1fUL << LCD_PAL8_R14_0_Pos) /*!< LCD PAL8: R14_0 Mask */
+#define LCD_PAL8_G14_0_Pos 21 /*!< LCD PAL8: G14_0 Position */
+#define LCD_PAL8_G14_0_Msk (0x1fUL << LCD_PAL8_G14_0_Pos) /*!< LCD PAL8: G14_0 Mask */
+#define LCD_PAL8_B14_0_Pos 26 /*!< LCD PAL8: B14_0 Position */
+#define LCD_PAL8_B14_0_Msk (0x1fUL << LCD_PAL8_B14_0_Pos) /*!< LCD PAL8: B14_0 Mask */
+#define LCD_PAL8_I1_Pos 31 /*!< LCD PAL8: I1 Position */
+#define LCD_PAL8_I1_Msk (0x01UL << LCD_PAL8_I1_Pos) /*!< LCD PAL8: I1 Mask */
+
+// ---------------------------------------- LCD_PAL9 --------------------------------------------
+#define LCD_PAL9_R04_0_Pos 0 /*!< LCD PAL9: R04_0 Position */
+#define LCD_PAL9_R04_0_Msk (0x1fUL << LCD_PAL9_R04_0_Pos) /*!< LCD PAL9: R04_0 Mask */
+#define LCD_PAL9_G04_0_Pos 5 /*!< LCD PAL9: G04_0 Position */
+#define LCD_PAL9_G04_0_Msk (0x1fUL << LCD_PAL9_G04_0_Pos) /*!< LCD PAL9: G04_0 Mask */
+#define LCD_PAL9_B04_0_Pos 10 /*!< LCD PAL9: B04_0 Position */
+#define LCD_PAL9_B04_0_Msk (0x1fUL << LCD_PAL9_B04_0_Pos) /*!< LCD PAL9: B04_0 Mask */
+#define LCD_PAL9_I0_Pos 15 /*!< LCD PAL9: I0 Position */
+#define LCD_PAL9_I0_Msk (0x01UL << LCD_PAL9_I0_Pos) /*!< LCD PAL9: I0 Mask */
+#define LCD_PAL9_R14_0_Pos 16 /*!< LCD PAL9: R14_0 Position */
+#define LCD_PAL9_R14_0_Msk (0x1fUL << LCD_PAL9_R14_0_Pos) /*!< LCD PAL9: R14_0 Mask */
+#define LCD_PAL9_G14_0_Pos 21 /*!< LCD PAL9: G14_0 Position */
+#define LCD_PAL9_G14_0_Msk (0x1fUL << LCD_PAL9_G14_0_Pos) /*!< LCD PAL9: G14_0 Mask */
+#define LCD_PAL9_B14_0_Pos 26 /*!< LCD PAL9: B14_0 Position */
+#define LCD_PAL9_B14_0_Msk (0x1fUL << LCD_PAL9_B14_0_Pos) /*!< LCD PAL9: B14_0 Mask */
+#define LCD_PAL9_I1_Pos 31 /*!< LCD PAL9: I1 Position */
+#define LCD_PAL9_I1_Msk (0x01UL << LCD_PAL9_I1_Pos) /*!< LCD PAL9: I1 Mask */
+
+// ---------------------------------------- LCD_PAL10 -------------------------------------------
+#define LCD_PAL10_R04_0_Pos 0 /*!< LCD PAL10: R04_0 Position */
+#define LCD_PAL10_R04_0_Msk (0x1fUL << LCD_PAL10_R04_0_Pos) /*!< LCD PAL10: R04_0 Mask */
+#define LCD_PAL10_G04_0_Pos 5 /*!< LCD PAL10: G04_0 Position */
+#define LCD_PAL10_G04_0_Msk (0x1fUL << LCD_PAL10_G04_0_Pos) /*!< LCD PAL10: G04_0 Mask */
+#define LCD_PAL10_B04_0_Pos 10 /*!< LCD PAL10: B04_0 Position */
+#define LCD_PAL10_B04_0_Msk (0x1fUL << LCD_PAL10_B04_0_Pos) /*!< LCD PAL10: B04_0 Mask */
+#define LCD_PAL10_I0_Pos 15 /*!< LCD PAL10: I0 Position */
+#define LCD_PAL10_I0_Msk (0x01UL << LCD_PAL10_I0_Pos) /*!< LCD PAL10: I0 Mask */
+#define LCD_PAL10_R14_0_Pos 16 /*!< LCD PAL10: R14_0 Position */
+#define LCD_PAL10_R14_0_Msk (0x1fUL << LCD_PAL10_R14_0_Pos) /*!< LCD PAL10: R14_0 Mask */
+#define LCD_PAL10_G14_0_Pos 21 /*!< LCD PAL10: G14_0 Position */
+#define LCD_PAL10_G14_0_Msk (0x1fUL << LCD_PAL10_G14_0_Pos) /*!< LCD PAL10: G14_0 Mask */
+#define LCD_PAL10_B14_0_Pos 26 /*!< LCD PAL10: B14_0 Position */
+#define LCD_PAL10_B14_0_Msk (0x1fUL << LCD_PAL10_B14_0_Pos) /*!< LCD PAL10: B14_0 Mask */
+#define LCD_PAL10_I1_Pos 31 /*!< LCD PAL10: I1 Position */
+#define LCD_PAL10_I1_Msk (0x01UL << LCD_PAL10_I1_Pos) /*!< LCD PAL10: I1 Mask */
+
+// ---------------------------------------- LCD_PAL11 -------------------------------------------
+#define LCD_PAL11_R04_0_Pos 0 /*!< LCD PAL11: R04_0 Position */
+#define LCD_PAL11_R04_0_Msk (0x1fUL << LCD_PAL11_R04_0_Pos) /*!< LCD PAL11: R04_0 Mask */
+#define LCD_PAL11_G04_0_Pos 5 /*!< LCD PAL11: G04_0 Position */
+#define LCD_PAL11_G04_0_Msk (0x1fUL << LCD_PAL11_G04_0_Pos) /*!< LCD PAL11: G04_0 Mask */
+#define LCD_PAL11_B04_0_Pos 10 /*!< LCD PAL11: B04_0 Position */
+#define LCD_PAL11_B04_0_Msk (0x1fUL << LCD_PAL11_B04_0_Pos) /*!< LCD PAL11: B04_0 Mask */
+#define LCD_PAL11_I0_Pos 15 /*!< LCD PAL11: I0 Position */
+#define LCD_PAL11_I0_Msk (0x01UL << LCD_PAL11_I0_Pos) /*!< LCD PAL11: I0 Mask */
+#define LCD_PAL11_R14_0_Pos 16 /*!< LCD PAL11: R14_0 Position */
+#define LCD_PAL11_R14_0_Msk (0x1fUL << LCD_PAL11_R14_0_Pos) /*!< LCD PAL11: R14_0 Mask */
+#define LCD_PAL11_G14_0_Pos 21 /*!< LCD PAL11: G14_0 Position */
+#define LCD_PAL11_G14_0_Msk (0x1fUL << LCD_PAL11_G14_0_Pos) /*!< LCD PAL11: G14_0 Mask */
+#define LCD_PAL11_B14_0_Pos 26 /*!< LCD PAL11: B14_0 Position */
+#define LCD_PAL11_B14_0_Msk (0x1fUL << LCD_PAL11_B14_0_Pos) /*!< LCD PAL11: B14_0 Mask */
+#define LCD_PAL11_I1_Pos 31 /*!< LCD PAL11: I1 Position */
+#define LCD_PAL11_I1_Msk (0x01UL << LCD_PAL11_I1_Pos) /*!< LCD PAL11: I1 Mask */
+
+// ---------------------------------------- LCD_PAL12 -------------------------------------------
+#define LCD_PAL12_R04_0_Pos 0 /*!< LCD PAL12: R04_0 Position */
+#define LCD_PAL12_R04_0_Msk (0x1fUL << LCD_PAL12_R04_0_Pos) /*!< LCD PAL12: R04_0 Mask */
+#define LCD_PAL12_G04_0_Pos 5 /*!< LCD PAL12: G04_0 Position */
+#define LCD_PAL12_G04_0_Msk (0x1fUL << LCD_PAL12_G04_0_Pos) /*!< LCD PAL12: G04_0 Mask */
+#define LCD_PAL12_B04_0_Pos 10 /*!< LCD PAL12: B04_0 Position */
+#define LCD_PAL12_B04_0_Msk (0x1fUL << LCD_PAL12_B04_0_Pos) /*!< LCD PAL12: B04_0 Mask */
+#define LCD_PAL12_I0_Pos 15 /*!< LCD PAL12: I0 Position */
+#define LCD_PAL12_I0_Msk (0x01UL << LCD_PAL12_I0_Pos) /*!< LCD PAL12: I0 Mask */
+#define LCD_PAL12_R14_0_Pos 16 /*!< LCD PAL12: R14_0 Position */
+#define LCD_PAL12_R14_0_Msk (0x1fUL << LCD_PAL12_R14_0_Pos) /*!< LCD PAL12: R14_0 Mask */
+#define LCD_PAL12_G14_0_Pos 21 /*!< LCD PAL12: G14_0 Position */
+#define LCD_PAL12_G14_0_Msk (0x1fUL << LCD_PAL12_G14_0_Pos) /*!< LCD PAL12: G14_0 Mask */
+#define LCD_PAL12_B14_0_Pos 26 /*!< LCD PAL12: B14_0 Position */
+#define LCD_PAL12_B14_0_Msk (0x1fUL << LCD_PAL12_B14_0_Pos) /*!< LCD PAL12: B14_0 Mask */
+#define LCD_PAL12_I1_Pos 31 /*!< LCD PAL12: I1 Position */
+#define LCD_PAL12_I1_Msk (0x01UL << LCD_PAL12_I1_Pos) /*!< LCD PAL12: I1 Mask */
+
+// ---------------------------------------- LCD_PAL13 -------------------------------------------
+#define LCD_PAL13_R04_0_Pos 0 /*!< LCD PAL13: R04_0 Position */
+#define LCD_PAL13_R04_0_Msk (0x1fUL << LCD_PAL13_R04_0_Pos) /*!< LCD PAL13: R04_0 Mask */
+#define LCD_PAL13_G04_0_Pos 5 /*!< LCD PAL13: G04_0 Position */
+#define LCD_PAL13_G04_0_Msk (0x1fUL << LCD_PAL13_G04_0_Pos) /*!< LCD PAL13: G04_0 Mask */
+#define LCD_PAL13_B04_0_Pos 10 /*!< LCD PAL13: B04_0 Position */
+#define LCD_PAL13_B04_0_Msk (0x1fUL << LCD_PAL13_B04_0_Pos) /*!< LCD PAL13: B04_0 Mask */
+#define LCD_PAL13_I0_Pos 15 /*!< LCD PAL13: I0 Position */
+#define LCD_PAL13_I0_Msk (0x01UL << LCD_PAL13_I0_Pos) /*!< LCD PAL13: I0 Mask */
+#define LCD_PAL13_R14_0_Pos 16 /*!< LCD PAL13: R14_0 Position */
+#define LCD_PAL13_R14_0_Msk (0x1fUL << LCD_PAL13_R14_0_Pos) /*!< LCD PAL13: R14_0 Mask */
+#define LCD_PAL13_G14_0_Pos 21 /*!< LCD PAL13: G14_0 Position */
+#define LCD_PAL13_G14_0_Msk (0x1fUL << LCD_PAL13_G14_0_Pos) /*!< LCD PAL13: G14_0 Mask */
+#define LCD_PAL13_B14_0_Pos 26 /*!< LCD PAL13: B14_0 Position */
+#define LCD_PAL13_B14_0_Msk (0x1fUL << LCD_PAL13_B14_0_Pos) /*!< LCD PAL13: B14_0 Mask */
+#define LCD_PAL13_I1_Pos 31 /*!< LCD PAL13: I1 Position */
+#define LCD_PAL13_I1_Msk (0x01UL << LCD_PAL13_I1_Pos) /*!< LCD PAL13: I1 Mask */
+
+// ---------------------------------------- LCD_PAL14 -------------------------------------------
+#define LCD_PAL14_R04_0_Pos 0 /*!< LCD PAL14: R04_0 Position */
+#define LCD_PAL14_R04_0_Msk (0x1fUL << LCD_PAL14_R04_0_Pos) /*!< LCD PAL14: R04_0 Mask */
+#define LCD_PAL14_G04_0_Pos 5 /*!< LCD PAL14: G04_0 Position */
+#define LCD_PAL14_G04_0_Msk (0x1fUL << LCD_PAL14_G04_0_Pos) /*!< LCD PAL14: G04_0 Mask */
+#define LCD_PAL14_B04_0_Pos 10 /*!< LCD PAL14: B04_0 Position */
+#define LCD_PAL14_B04_0_Msk (0x1fUL << LCD_PAL14_B04_0_Pos) /*!< LCD PAL14: B04_0 Mask */
+#define LCD_PAL14_I0_Pos 15 /*!< LCD PAL14: I0 Position */
+#define LCD_PAL14_I0_Msk (0x01UL << LCD_PAL14_I0_Pos) /*!< LCD PAL14: I0 Mask */
+#define LCD_PAL14_R14_0_Pos 16 /*!< LCD PAL14: R14_0 Position */
+#define LCD_PAL14_R14_0_Msk (0x1fUL << LCD_PAL14_R14_0_Pos) /*!< LCD PAL14: R14_0 Mask */
+#define LCD_PAL14_G14_0_Pos 21 /*!< LCD PAL14: G14_0 Position */
+#define LCD_PAL14_G14_0_Msk (0x1fUL << LCD_PAL14_G14_0_Pos) /*!< LCD PAL14: G14_0 Mask */
+#define LCD_PAL14_B14_0_Pos 26 /*!< LCD PAL14: B14_0 Position */
+#define LCD_PAL14_B14_0_Msk (0x1fUL << LCD_PAL14_B14_0_Pos) /*!< LCD PAL14: B14_0 Mask */
+#define LCD_PAL14_I1_Pos 31 /*!< LCD PAL14: I1 Position */
+#define LCD_PAL14_I1_Msk (0x01UL << LCD_PAL14_I1_Pos) /*!< LCD PAL14: I1 Mask */
+
+// ---------------------------------------- LCD_PAL15 -------------------------------------------
+#define LCD_PAL15_R04_0_Pos 0 /*!< LCD PAL15: R04_0 Position */
+#define LCD_PAL15_R04_0_Msk (0x1fUL << LCD_PAL15_R04_0_Pos) /*!< LCD PAL15: R04_0 Mask */
+#define LCD_PAL15_G04_0_Pos 5 /*!< LCD PAL15: G04_0 Position */
+#define LCD_PAL15_G04_0_Msk (0x1fUL << LCD_PAL15_G04_0_Pos) /*!< LCD PAL15: G04_0 Mask */
+#define LCD_PAL15_B04_0_Pos 10 /*!< LCD PAL15: B04_0 Position */
+#define LCD_PAL15_B04_0_Msk (0x1fUL << LCD_PAL15_B04_0_Pos) /*!< LCD PAL15: B04_0 Mask */
+#define LCD_PAL15_I0_Pos 15 /*!< LCD PAL15: I0 Position */
+#define LCD_PAL15_I0_Msk (0x01UL << LCD_PAL15_I0_Pos) /*!< LCD PAL15: I0 Mask */
+#define LCD_PAL15_R14_0_Pos 16 /*!< LCD PAL15: R14_0 Position */
+#define LCD_PAL15_R14_0_Msk (0x1fUL << LCD_PAL15_R14_0_Pos) /*!< LCD PAL15: R14_0 Mask */
+#define LCD_PAL15_G14_0_Pos 21 /*!< LCD PAL15: G14_0 Position */
+#define LCD_PAL15_G14_0_Msk (0x1fUL << LCD_PAL15_G14_0_Pos) /*!< LCD PAL15: G14_0 Mask */
+#define LCD_PAL15_B14_0_Pos 26 /*!< LCD PAL15: B14_0 Position */
+#define LCD_PAL15_B14_0_Msk (0x1fUL << LCD_PAL15_B14_0_Pos) /*!< LCD PAL15: B14_0 Mask */
+#define LCD_PAL15_I1_Pos 31 /*!< LCD PAL15: I1 Position */
+#define LCD_PAL15_I1_Msk (0x01UL << LCD_PAL15_I1_Pos) /*!< LCD PAL15: I1 Mask */
+
+// ---------------------------------------- LCD_PAL16 -------------------------------------------
+#define LCD_PAL16_R04_0_Pos 0 /*!< LCD PAL16: R04_0 Position */
+#define LCD_PAL16_R04_0_Msk (0x1fUL << LCD_PAL16_R04_0_Pos) /*!< LCD PAL16: R04_0 Mask */
+#define LCD_PAL16_G04_0_Pos 5 /*!< LCD PAL16: G04_0 Position */
+#define LCD_PAL16_G04_0_Msk (0x1fUL << LCD_PAL16_G04_0_Pos) /*!< LCD PAL16: G04_0 Mask */
+#define LCD_PAL16_B04_0_Pos 10 /*!< LCD PAL16: B04_0 Position */
+#define LCD_PAL16_B04_0_Msk (0x1fUL << LCD_PAL16_B04_0_Pos) /*!< LCD PAL16: B04_0 Mask */
+#define LCD_PAL16_I0_Pos 15 /*!< LCD PAL16: I0 Position */
+#define LCD_PAL16_I0_Msk (0x01UL << LCD_PAL16_I0_Pos) /*!< LCD PAL16: I0 Mask */
+#define LCD_PAL16_R14_0_Pos 16 /*!< LCD PAL16: R14_0 Position */
+#define LCD_PAL16_R14_0_Msk (0x1fUL << LCD_PAL16_R14_0_Pos) /*!< LCD PAL16: R14_0 Mask */
+#define LCD_PAL16_G14_0_Pos 21 /*!< LCD PAL16: G14_0 Position */
+#define LCD_PAL16_G14_0_Msk (0x1fUL << LCD_PAL16_G14_0_Pos) /*!< LCD PAL16: G14_0 Mask */
+#define LCD_PAL16_B14_0_Pos 26 /*!< LCD PAL16: B14_0 Position */
+#define LCD_PAL16_B14_0_Msk (0x1fUL << LCD_PAL16_B14_0_Pos) /*!< LCD PAL16: B14_0 Mask */
+#define LCD_PAL16_I1_Pos 31 /*!< LCD PAL16: I1 Position */
+#define LCD_PAL16_I1_Msk (0x01UL << LCD_PAL16_I1_Pos) /*!< LCD PAL16: I1 Mask */
+
+// ---------------------------------------- LCD_PAL17 -------------------------------------------
+#define LCD_PAL17_R04_0_Pos 0 /*!< LCD PAL17: R04_0 Position */
+#define LCD_PAL17_R04_0_Msk (0x1fUL << LCD_PAL17_R04_0_Pos) /*!< LCD PAL17: R04_0 Mask */
+#define LCD_PAL17_G04_0_Pos 5 /*!< LCD PAL17: G04_0 Position */
+#define LCD_PAL17_G04_0_Msk (0x1fUL << LCD_PAL17_G04_0_Pos) /*!< LCD PAL17: G04_0 Mask */
+#define LCD_PAL17_B04_0_Pos 10 /*!< LCD PAL17: B04_0 Position */
+#define LCD_PAL17_B04_0_Msk (0x1fUL << LCD_PAL17_B04_0_Pos) /*!< LCD PAL17: B04_0 Mask */
+#define LCD_PAL17_I0_Pos 15 /*!< LCD PAL17: I0 Position */
+#define LCD_PAL17_I0_Msk (0x01UL << LCD_PAL17_I0_Pos) /*!< LCD PAL17: I0 Mask */
+#define LCD_PAL17_R14_0_Pos 16 /*!< LCD PAL17: R14_0 Position */
+#define LCD_PAL17_R14_0_Msk (0x1fUL << LCD_PAL17_R14_0_Pos) /*!< LCD PAL17: R14_0 Mask */
+#define LCD_PAL17_G14_0_Pos 21 /*!< LCD PAL17: G14_0 Position */
+#define LCD_PAL17_G14_0_Msk (0x1fUL << LCD_PAL17_G14_0_Pos) /*!< LCD PAL17: G14_0 Mask */
+#define LCD_PAL17_B14_0_Pos 26 /*!< LCD PAL17: B14_0 Position */
+#define LCD_PAL17_B14_0_Msk (0x1fUL << LCD_PAL17_B14_0_Pos) /*!< LCD PAL17: B14_0 Mask */
+#define LCD_PAL17_I1_Pos 31 /*!< LCD PAL17: I1 Position */
+#define LCD_PAL17_I1_Msk (0x01UL << LCD_PAL17_I1_Pos) /*!< LCD PAL17: I1 Mask */
+
+// ---------------------------------------- LCD_PAL18 -------------------------------------------
+#define LCD_PAL18_R04_0_Pos 0 /*!< LCD PAL18: R04_0 Position */
+#define LCD_PAL18_R04_0_Msk (0x1fUL << LCD_PAL18_R04_0_Pos) /*!< LCD PAL18: R04_0 Mask */
+#define LCD_PAL18_G04_0_Pos 5 /*!< LCD PAL18: G04_0 Position */
+#define LCD_PAL18_G04_0_Msk (0x1fUL << LCD_PAL18_G04_0_Pos) /*!< LCD PAL18: G04_0 Mask */
+#define LCD_PAL18_B04_0_Pos 10 /*!< LCD PAL18: B04_0 Position */
+#define LCD_PAL18_B04_0_Msk (0x1fUL << LCD_PAL18_B04_0_Pos) /*!< LCD PAL18: B04_0 Mask */
+#define LCD_PAL18_I0_Pos 15 /*!< LCD PAL18: I0 Position */
+#define LCD_PAL18_I0_Msk (0x01UL << LCD_PAL18_I0_Pos) /*!< LCD PAL18: I0 Mask */
+#define LCD_PAL18_R14_0_Pos 16 /*!< LCD PAL18: R14_0 Position */
+#define LCD_PAL18_R14_0_Msk (0x1fUL << LCD_PAL18_R14_0_Pos) /*!< LCD PAL18: R14_0 Mask */
+#define LCD_PAL18_G14_0_Pos 21 /*!< LCD PAL18: G14_0 Position */
+#define LCD_PAL18_G14_0_Msk (0x1fUL << LCD_PAL18_G14_0_Pos) /*!< LCD PAL18: G14_0 Mask */
+#define LCD_PAL18_B14_0_Pos 26 /*!< LCD PAL18: B14_0 Position */
+#define LCD_PAL18_B14_0_Msk (0x1fUL << LCD_PAL18_B14_0_Pos) /*!< LCD PAL18: B14_0 Mask */
+#define LCD_PAL18_I1_Pos 31 /*!< LCD PAL18: I1 Position */
+#define LCD_PAL18_I1_Msk (0x01UL << LCD_PAL18_I1_Pos) /*!< LCD PAL18: I1 Mask */
+
+// ---------------------------------------- LCD_PAL19 -------------------------------------------
+#define LCD_PAL19_R04_0_Pos 0 /*!< LCD PAL19: R04_0 Position */
+#define LCD_PAL19_R04_0_Msk (0x1fUL << LCD_PAL19_R04_0_Pos) /*!< LCD PAL19: R04_0 Mask */
+#define LCD_PAL19_G04_0_Pos 5 /*!< LCD PAL19: G04_0 Position */
+#define LCD_PAL19_G04_0_Msk (0x1fUL << LCD_PAL19_G04_0_Pos) /*!< LCD PAL19: G04_0 Mask */
+#define LCD_PAL19_B04_0_Pos 10 /*!< LCD PAL19: B04_0 Position */
+#define LCD_PAL19_B04_0_Msk (0x1fUL << LCD_PAL19_B04_0_Pos) /*!< LCD PAL19: B04_0 Mask */
+#define LCD_PAL19_I0_Pos 15 /*!< LCD PAL19: I0 Position */
+#define LCD_PAL19_I0_Msk (0x01UL << LCD_PAL19_I0_Pos) /*!< LCD PAL19: I0 Mask */
+#define LCD_PAL19_R14_0_Pos 16 /*!< LCD PAL19: R14_0 Position */
+#define LCD_PAL19_R14_0_Msk (0x1fUL << LCD_PAL19_R14_0_Pos) /*!< LCD PAL19: R14_0 Mask */
+#define LCD_PAL19_G14_0_Pos 21 /*!< LCD PAL19: G14_0 Position */
+#define LCD_PAL19_G14_0_Msk (0x1fUL << LCD_PAL19_G14_0_Pos) /*!< LCD PAL19: G14_0 Mask */
+#define LCD_PAL19_B14_0_Pos 26 /*!< LCD PAL19: B14_0 Position */
+#define LCD_PAL19_B14_0_Msk (0x1fUL << LCD_PAL19_B14_0_Pos) /*!< LCD PAL19: B14_0 Mask */
+#define LCD_PAL19_I1_Pos 31 /*!< LCD PAL19: I1 Position */
+#define LCD_PAL19_I1_Msk (0x01UL << LCD_PAL19_I1_Pos) /*!< LCD PAL19: I1 Mask */
+
+// ---------------------------------------- LCD_PAL20 -------------------------------------------
+#define LCD_PAL20_R04_0_Pos 0 /*!< LCD PAL20: R04_0 Position */
+#define LCD_PAL20_R04_0_Msk (0x1fUL << LCD_PAL20_R04_0_Pos) /*!< LCD PAL20: R04_0 Mask */
+#define LCD_PAL20_G04_0_Pos 5 /*!< LCD PAL20: G04_0 Position */
+#define LCD_PAL20_G04_0_Msk (0x1fUL << LCD_PAL20_G04_0_Pos) /*!< LCD PAL20: G04_0 Mask */
+#define LCD_PAL20_B04_0_Pos 10 /*!< LCD PAL20: B04_0 Position */
+#define LCD_PAL20_B04_0_Msk (0x1fUL << LCD_PAL20_B04_0_Pos) /*!< LCD PAL20: B04_0 Mask */
+#define LCD_PAL20_I0_Pos 15 /*!< LCD PAL20: I0 Position */
+#define LCD_PAL20_I0_Msk (0x01UL << LCD_PAL20_I0_Pos) /*!< LCD PAL20: I0 Mask */
+#define LCD_PAL20_R14_0_Pos 16 /*!< LCD PAL20: R14_0 Position */
+#define LCD_PAL20_R14_0_Msk (0x1fUL << LCD_PAL20_R14_0_Pos) /*!< LCD PAL20: R14_0 Mask */
+#define LCD_PAL20_G14_0_Pos 21 /*!< LCD PAL20: G14_0 Position */
+#define LCD_PAL20_G14_0_Msk (0x1fUL << LCD_PAL20_G14_0_Pos) /*!< LCD PAL20: G14_0 Mask */
+#define LCD_PAL20_B14_0_Pos 26 /*!< LCD PAL20: B14_0 Position */
+#define LCD_PAL20_B14_0_Msk (0x1fUL << LCD_PAL20_B14_0_Pos) /*!< LCD PAL20: B14_0 Mask */
+#define LCD_PAL20_I1_Pos 31 /*!< LCD PAL20: I1 Position */
+#define LCD_PAL20_I1_Msk (0x01UL << LCD_PAL20_I1_Pos) /*!< LCD PAL20: I1 Mask */
+
+// ---------------------------------------- LCD_PAL21 -------------------------------------------
+#define LCD_PAL21_R04_0_Pos 0 /*!< LCD PAL21: R04_0 Position */
+#define LCD_PAL21_R04_0_Msk (0x1fUL << LCD_PAL21_R04_0_Pos) /*!< LCD PAL21: R04_0 Mask */
+#define LCD_PAL21_G04_0_Pos 5 /*!< LCD PAL21: G04_0 Position */
+#define LCD_PAL21_G04_0_Msk (0x1fUL << LCD_PAL21_G04_0_Pos) /*!< LCD PAL21: G04_0 Mask */
+#define LCD_PAL21_B04_0_Pos 10 /*!< LCD PAL21: B04_0 Position */
+#define LCD_PAL21_B04_0_Msk (0x1fUL << LCD_PAL21_B04_0_Pos) /*!< LCD PAL21: B04_0 Mask */
+#define LCD_PAL21_I0_Pos 15 /*!< LCD PAL21: I0 Position */
+#define LCD_PAL21_I0_Msk (0x01UL << LCD_PAL21_I0_Pos) /*!< LCD PAL21: I0 Mask */
+#define LCD_PAL21_R14_0_Pos 16 /*!< LCD PAL21: R14_0 Position */
+#define LCD_PAL21_R14_0_Msk (0x1fUL << LCD_PAL21_R14_0_Pos) /*!< LCD PAL21: R14_0 Mask */
+#define LCD_PAL21_G14_0_Pos 21 /*!< LCD PAL21: G14_0 Position */
+#define LCD_PAL21_G14_0_Msk (0x1fUL << LCD_PAL21_G14_0_Pos) /*!< LCD PAL21: G14_0 Mask */
+#define LCD_PAL21_B14_0_Pos 26 /*!< LCD PAL21: B14_0 Position */
+#define LCD_PAL21_B14_0_Msk (0x1fUL << LCD_PAL21_B14_0_Pos) /*!< LCD PAL21: B14_0 Mask */
+#define LCD_PAL21_I1_Pos 31 /*!< LCD PAL21: I1 Position */
+#define LCD_PAL21_I1_Msk (0x01UL << LCD_PAL21_I1_Pos) /*!< LCD PAL21: I1 Mask */
+
+// ---------------------------------------- LCD_PAL22 -------------------------------------------
+#define LCD_PAL22_R04_0_Pos 0 /*!< LCD PAL22: R04_0 Position */
+#define LCD_PAL22_R04_0_Msk (0x1fUL << LCD_PAL22_R04_0_Pos) /*!< LCD PAL22: R04_0 Mask */
+#define LCD_PAL22_G04_0_Pos 5 /*!< LCD PAL22: G04_0 Position */
+#define LCD_PAL22_G04_0_Msk (0x1fUL << LCD_PAL22_G04_0_Pos) /*!< LCD PAL22: G04_0 Mask */
+#define LCD_PAL22_B04_0_Pos 10 /*!< LCD PAL22: B04_0 Position */
+#define LCD_PAL22_B04_0_Msk (0x1fUL << LCD_PAL22_B04_0_Pos) /*!< LCD PAL22: B04_0 Mask */
+#define LCD_PAL22_I0_Pos 15 /*!< LCD PAL22: I0 Position */
+#define LCD_PAL22_I0_Msk (0x01UL << LCD_PAL22_I0_Pos) /*!< LCD PAL22: I0 Mask */
+#define LCD_PAL22_R14_0_Pos 16 /*!< LCD PAL22: R14_0 Position */
+#define LCD_PAL22_R14_0_Msk (0x1fUL << LCD_PAL22_R14_0_Pos) /*!< LCD PAL22: R14_0 Mask */
+#define LCD_PAL22_G14_0_Pos 21 /*!< LCD PAL22: G14_0 Position */
+#define LCD_PAL22_G14_0_Msk (0x1fUL << LCD_PAL22_G14_0_Pos) /*!< LCD PAL22: G14_0 Mask */
+#define LCD_PAL22_B14_0_Pos 26 /*!< LCD PAL22: B14_0 Position */
+#define LCD_PAL22_B14_0_Msk (0x1fUL << LCD_PAL22_B14_0_Pos) /*!< LCD PAL22: B14_0 Mask */
+#define LCD_PAL22_I1_Pos 31 /*!< LCD PAL22: I1 Position */
+#define LCD_PAL22_I1_Msk (0x01UL << LCD_PAL22_I1_Pos) /*!< LCD PAL22: I1 Mask */
+
+// ---------------------------------------- LCD_PAL23 -------------------------------------------
+#define LCD_PAL23_R04_0_Pos 0 /*!< LCD PAL23: R04_0 Position */
+#define LCD_PAL23_R04_0_Msk (0x1fUL << LCD_PAL23_R04_0_Pos) /*!< LCD PAL23: R04_0 Mask */
+#define LCD_PAL23_G04_0_Pos 5 /*!< LCD PAL23: G04_0 Position */
+#define LCD_PAL23_G04_0_Msk (0x1fUL << LCD_PAL23_G04_0_Pos) /*!< LCD PAL23: G04_0 Mask */
+#define LCD_PAL23_B04_0_Pos 10 /*!< LCD PAL23: B04_0 Position */
+#define LCD_PAL23_B04_0_Msk (0x1fUL << LCD_PAL23_B04_0_Pos) /*!< LCD PAL23: B04_0 Mask */
+#define LCD_PAL23_I0_Pos 15 /*!< LCD PAL23: I0 Position */
+#define LCD_PAL23_I0_Msk (0x01UL << LCD_PAL23_I0_Pos) /*!< LCD PAL23: I0 Mask */
+#define LCD_PAL23_R14_0_Pos 16 /*!< LCD PAL23: R14_0 Position */
+#define LCD_PAL23_R14_0_Msk (0x1fUL << LCD_PAL23_R14_0_Pos) /*!< LCD PAL23: R14_0 Mask */
+#define LCD_PAL23_G14_0_Pos 21 /*!< LCD PAL23: G14_0 Position */
+#define LCD_PAL23_G14_0_Msk (0x1fUL << LCD_PAL23_G14_0_Pos) /*!< LCD PAL23: G14_0 Mask */
+#define LCD_PAL23_B14_0_Pos 26 /*!< LCD PAL23: B14_0 Position */
+#define LCD_PAL23_B14_0_Msk (0x1fUL << LCD_PAL23_B14_0_Pos) /*!< LCD PAL23: B14_0 Mask */
+#define LCD_PAL23_I1_Pos 31 /*!< LCD PAL23: I1 Position */
+#define LCD_PAL23_I1_Msk (0x01UL << LCD_PAL23_I1_Pos) /*!< LCD PAL23: I1 Mask */
+
+// ---------------------------------------- LCD_PAL24 -------------------------------------------
+#define LCD_PAL24_R04_0_Pos 0 /*!< LCD PAL24: R04_0 Position */
+#define LCD_PAL24_R04_0_Msk (0x1fUL << LCD_PAL24_R04_0_Pos) /*!< LCD PAL24: R04_0 Mask */
+#define LCD_PAL24_G04_0_Pos 5 /*!< LCD PAL24: G04_0 Position */
+#define LCD_PAL24_G04_0_Msk (0x1fUL << LCD_PAL24_G04_0_Pos) /*!< LCD PAL24: G04_0 Mask */
+#define LCD_PAL24_B04_0_Pos 10 /*!< LCD PAL24: B04_0 Position */
+#define LCD_PAL24_B04_0_Msk (0x1fUL << LCD_PAL24_B04_0_Pos) /*!< LCD PAL24: B04_0 Mask */
+#define LCD_PAL24_I0_Pos 15 /*!< LCD PAL24: I0 Position */
+#define LCD_PAL24_I0_Msk (0x01UL << LCD_PAL24_I0_Pos) /*!< LCD PAL24: I0 Mask */
+#define LCD_PAL24_R14_0_Pos 16 /*!< LCD PAL24: R14_0 Position */
+#define LCD_PAL24_R14_0_Msk (0x1fUL << LCD_PAL24_R14_0_Pos) /*!< LCD PAL24: R14_0 Mask */
+#define LCD_PAL24_G14_0_Pos 21 /*!< LCD PAL24: G14_0 Position */
+#define LCD_PAL24_G14_0_Msk (0x1fUL << LCD_PAL24_G14_0_Pos) /*!< LCD PAL24: G14_0 Mask */
+#define LCD_PAL24_B14_0_Pos 26 /*!< LCD PAL24: B14_0 Position */
+#define LCD_PAL24_B14_0_Msk (0x1fUL << LCD_PAL24_B14_0_Pos) /*!< LCD PAL24: B14_0 Mask */
+#define LCD_PAL24_I1_Pos 31 /*!< LCD PAL24: I1 Position */
+#define LCD_PAL24_I1_Msk (0x01UL << LCD_PAL24_I1_Pos) /*!< LCD PAL24: I1 Mask */
+
+// ---------------------------------------- LCD_PAL25 -------------------------------------------
+#define LCD_PAL25_R04_0_Pos 0 /*!< LCD PAL25: R04_0 Position */
+#define LCD_PAL25_R04_0_Msk (0x1fUL << LCD_PAL25_R04_0_Pos) /*!< LCD PAL25: R04_0 Mask */
+#define LCD_PAL25_G04_0_Pos 5 /*!< LCD PAL25: G04_0 Position */
+#define LCD_PAL25_G04_0_Msk (0x1fUL << LCD_PAL25_G04_0_Pos) /*!< LCD PAL25: G04_0 Mask */
+#define LCD_PAL25_B04_0_Pos 10 /*!< LCD PAL25: B04_0 Position */
+#define LCD_PAL25_B04_0_Msk (0x1fUL << LCD_PAL25_B04_0_Pos) /*!< LCD PAL25: B04_0 Mask */
+#define LCD_PAL25_I0_Pos 15 /*!< LCD PAL25: I0 Position */
+#define LCD_PAL25_I0_Msk (0x01UL << LCD_PAL25_I0_Pos) /*!< LCD PAL25: I0 Mask */
+#define LCD_PAL25_R14_0_Pos 16 /*!< LCD PAL25: R14_0 Position */
+#define LCD_PAL25_R14_0_Msk (0x1fUL << LCD_PAL25_R14_0_Pos) /*!< LCD PAL25: R14_0 Mask */
+#define LCD_PAL25_G14_0_Pos 21 /*!< LCD PAL25: G14_0 Position */
+#define LCD_PAL25_G14_0_Msk (0x1fUL << LCD_PAL25_G14_0_Pos) /*!< LCD PAL25: G14_0 Mask */
+#define LCD_PAL25_B14_0_Pos 26 /*!< LCD PAL25: B14_0 Position */
+#define LCD_PAL25_B14_0_Msk (0x1fUL << LCD_PAL25_B14_0_Pos) /*!< LCD PAL25: B14_0 Mask */
+#define LCD_PAL25_I1_Pos 31 /*!< LCD PAL25: I1 Position */
+#define LCD_PAL25_I1_Msk (0x01UL << LCD_PAL25_I1_Pos) /*!< LCD PAL25: I1 Mask */
+
+// ---------------------------------------- LCD_PAL26 -------------------------------------------
+#define LCD_PAL26_R04_0_Pos 0 /*!< LCD PAL26: R04_0 Position */
+#define LCD_PAL26_R04_0_Msk (0x1fUL << LCD_PAL26_R04_0_Pos) /*!< LCD PAL26: R04_0 Mask */
+#define LCD_PAL26_G04_0_Pos 5 /*!< LCD PAL26: G04_0 Position */
+#define LCD_PAL26_G04_0_Msk (0x1fUL << LCD_PAL26_G04_0_Pos) /*!< LCD PAL26: G04_0 Mask */
+#define LCD_PAL26_B04_0_Pos 10 /*!< LCD PAL26: B04_0 Position */
+#define LCD_PAL26_B04_0_Msk (0x1fUL << LCD_PAL26_B04_0_Pos) /*!< LCD PAL26: B04_0 Mask */
+#define LCD_PAL26_I0_Pos 15 /*!< LCD PAL26: I0 Position */
+#define LCD_PAL26_I0_Msk (0x01UL << LCD_PAL26_I0_Pos) /*!< LCD PAL26: I0 Mask */
+#define LCD_PAL26_R14_0_Pos 16 /*!< LCD PAL26: R14_0 Position */
+#define LCD_PAL26_R14_0_Msk (0x1fUL << LCD_PAL26_R14_0_Pos) /*!< LCD PAL26: R14_0 Mask */
+#define LCD_PAL26_G14_0_Pos 21 /*!< LCD PAL26: G14_0 Position */
+#define LCD_PAL26_G14_0_Msk (0x1fUL << LCD_PAL26_G14_0_Pos) /*!< LCD PAL26: G14_0 Mask */
+#define LCD_PAL26_B14_0_Pos 26 /*!< LCD PAL26: B14_0 Position */
+#define LCD_PAL26_B14_0_Msk (0x1fUL << LCD_PAL26_B14_0_Pos) /*!< LCD PAL26: B14_0 Mask */
+#define LCD_PAL26_I1_Pos 31 /*!< LCD PAL26: I1 Position */
+#define LCD_PAL26_I1_Msk (0x01UL << LCD_PAL26_I1_Pos) /*!< LCD PAL26: I1 Mask */
+
+// ---------------------------------------- LCD_PAL27 -------------------------------------------
+#define LCD_PAL27_R04_0_Pos 0 /*!< LCD PAL27: R04_0 Position */
+#define LCD_PAL27_R04_0_Msk (0x1fUL << LCD_PAL27_R04_0_Pos) /*!< LCD PAL27: R04_0 Mask */
+#define LCD_PAL27_G04_0_Pos 5 /*!< LCD PAL27: G04_0 Position */
+#define LCD_PAL27_G04_0_Msk (0x1fUL << LCD_PAL27_G04_0_Pos) /*!< LCD PAL27: G04_0 Mask */
+#define LCD_PAL27_B04_0_Pos 10 /*!< LCD PAL27: B04_0 Position */
+#define LCD_PAL27_B04_0_Msk (0x1fUL << LCD_PAL27_B04_0_Pos) /*!< LCD PAL27: B04_0 Mask */
+#define LCD_PAL27_I0_Pos 15 /*!< LCD PAL27: I0 Position */
+#define LCD_PAL27_I0_Msk (0x01UL << LCD_PAL27_I0_Pos) /*!< LCD PAL27: I0 Mask */
+#define LCD_PAL27_R14_0_Pos 16 /*!< LCD PAL27: R14_0 Position */
+#define LCD_PAL27_R14_0_Msk (0x1fUL << LCD_PAL27_R14_0_Pos) /*!< LCD PAL27: R14_0 Mask */
+#define LCD_PAL27_G14_0_Pos 21 /*!< LCD PAL27: G14_0 Position */
+#define LCD_PAL27_G14_0_Msk (0x1fUL << LCD_PAL27_G14_0_Pos) /*!< LCD PAL27: G14_0 Mask */
+#define LCD_PAL27_B14_0_Pos 26 /*!< LCD PAL27: B14_0 Position */
+#define LCD_PAL27_B14_0_Msk (0x1fUL << LCD_PAL27_B14_0_Pos) /*!< LCD PAL27: B14_0 Mask */
+#define LCD_PAL27_I1_Pos 31 /*!< LCD PAL27: I1 Position */
+#define LCD_PAL27_I1_Msk (0x01UL << LCD_PAL27_I1_Pos) /*!< LCD PAL27: I1 Mask */
+
+// ---------------------------------------- LCD_PAL28 -------------------------------------------
+#define LCD_PAL28_R04_0_Pos 0 /*!< LCD PAL28: R04_0 Position */
+#define LCD_PAL28_R04_0_Msk (0x1fUL << LCD_PAL28_R04_0_Pos) /*!< LCD PAL28: R04_0 Mask */
+#define LCD_PAL28_G04_0_Pos 5 /*!< LCD PAL28: G04_0 Position */
+#define LCD_PAL28_G04_0_Msk (0x1fUL << LCD_PAL28_G04_0_Pos) /*!< LCD PAL28: G04_0 Mask */
+#define LCD_PAL28_B04_0_Pos 10 /*!< LCD PAL28: B04_0 Position */
+#define LCD_PAL28_B04_0_Msk (0x1fUL << LCD_PAL28_B04_0_Pos) /*!< LCD PAL28: B04_0 Mask */
+#define LCD_PAL28_I0_Pos 15 /*!< LCD PAL28: I0 Position */
+#define LCD_PAL28_I0_Msk (0x01UL << LCD_PAL28_I0_Pos) /*!< LCD PAL28: I0 Mask */
+#define LCD_PAL28_R14_0_Pos 16 /*!< LCD PAL28: R14_0 Position */
+#define LCD_PAL28_R14_0_Msk (0x1fUL << LCD_PAL28_R14_0_Pos) /*!< LCD PAL28: R14_0 Mask */
+#define LCD_PAL28_G14_0_Pos 21 /*!< LCD PAL28: G14_0 Position */
+#define LCD_PAL28_G14_0_Msk (0x1fUL << LCD_PAL28_G14_0_Pos) /*!< LCD PAL28: G14_0 Mask */
+#define LCD_PAL28_B14_0_Pos 26 /*!< LCD PAL28: B14_0 Position */
+#define LCD_PAL28_B14_0_Msk (0x1fUL << LCD_PAL28_B14_0_Pos) /*!< LCD PAL28: B14_0 Mask */
+#define LCD_PAL28_I1_Pos 31 /*!< LCD PAL28: I1 Position */
+#define LCD_PAL28_I1_Msk (0x01UL << LCD_PAL28_I1_Pos) /*!< LCD PAL28: I1 Mask */
+
+// ---------------------------------------- LCD_PAL29 -------------------------------------------
+#define LCD_PAL29_R04_0_Pos 0 /*!< LCD PAL29: R04_0 Position */
+#define LCD_PAL29_R04_0_Msk (0x1fUL << LCD_PAL29_R04_0_Pos) /*!< LCD PAL29: R04_0 Mask */
+#define LCD_PAL29_G04_0_Pos 5 /*!< LCD PAL29: G04_0 Position */
+#define LCD_PAL29_G04_0_Msk (0x1fUL << LCD_PAL29_G04_0_Pos) /*!< LCD PAL29: G04_0 Mask */
+#define LCD_PAL29_B04_0_Pos 10 /*!< LCD PAL29: B04_0 Position */
+#define LCD_PAL29_B04_0_Msk (0x1fUL << LCD_PAL29_B04_0_Pos) /*!< LCD PAL29: B04_0 Mask */
+#define LCD_PAL29_I0_Pos 15 /*!< LCD PAL29: I0 Position */
+#define LCD_PAL29_I0_Msk (0x01UL << LCD_PAL29_I0_Pos) /*!< LCD PAL29: I0 Mask */
+#define LCD_PAL29_R14_0_Pos 16 /*!< LCD PAL29: R14_0 Position */
+#define LCD_PAL29_R14_0_Msk (0x1fUL << LCD_PAL29_R14_0_Pos) /*!< LCD PAL29: R14_0 Mask */
+#define LCD_PAL29_G14_0_Pos 21 /*!< LCD PAL29: G14_0 Position */
+#define LCD_PAL29_G14_0_Msk (0x1fUL << LCD_PAL29_G14_0_Pos) /*!< LCD PAL29: G14_0 Mask */
+#define LCD_PAL29_B14_0_Pos 26 /*!< LCD PAL29: B14_0 Position */
+#define LCD_PAL29_B14_0_Msk (0x1fUL << LCD_PAL29_B14_0_Pos) /*!< LCD PAL29: B14_0 Mask */
+#define LCD_PAL29_I1_Pos 31 /*!< LCD PAL29: I1 Position */
+#define LCD_PAL29_I1_Msk (0x01UL << LCD_PAL29_I1_Pos) /*!< LCD PAL29: I1 Mask */
+
+// ---------------------------------------- LCD_PAL30 -------------------------------------------
+#define LCD_PAL30_R04_0_Pos 0 /*!< LCD PAL30: R04_0 Position */
+#define LCD_PAL30_R04_0_Msk (0x1fUL << LCD_PAL30_R04_0_Pos) /*!< LCD PAL30: R04_0 Mask */
+#define LCD_PAL30_G04_0_Pos 5 /*!< LCD PAL30: G04_0 Position */
+#define LCD_PAL30_G04_0_Msk (0x1fUL << LCD_PAL30_G04_0_Pos) /*!< LCD PAL30: G04_0 Mask */
+#define LCD_PAL30_B04_0_Pos 10 /*!< LCD PAL30: B04_0 Position */
+#define LCD_PAL30_B04_0_Msk (0x1fUL << LCD_PAL30_B04_0_Pos) /*!< LCD PAL30: B04_0 Mask */
+#define LCD_PAL30_I0_Pos 15 /*!< LCD PAL30: I0 Position */
+#define LCD_PAL30_I0_Msk (0x01UL << LCD_PAL30_I0_Pos) /*!< LCD PAL30: I0 Mask */
+#define LCD_PAL30_R14_0_Pos 16 /*!< LCD PAL30: R14_0 Position */
+#define LCD_PAL30_R14_0_Msk (0x1fUL << LCD_PAL30_R14_0_Pos) /*!< LCD PAL30: R14_0 Mask */
+#define LCD_PAL30_G14_0_Pos 21 /*!< LCD PAL30: G14_0 Position */
+#define LCD_PAL30_G14_0_Msk (0x1fUL << LCD_PAL30_G14_0_Pos) /*!< LCD PAL30: G14_0 Mask */
+#define LCD_PAL30_B14_0_Pos 26 /*!< LCD PAL30: B14_0 Position */
+#define LCD_PAL30_B14_0_Msk (0x1fUL << LCD_PAL30_B14_0_Pos) /*!< LCD PAL30: B14_0 Mask */
+#define LCD_PAL30_I1_Pos 31 /*!< LCD PAL30: I1 Position */
+#define LCD_PAL30_I1_Msk (0x01UL << LCD_PAL30_I1_Pos) /*!< LCD PAL30: I1 Mask */
+
+// ---------------------------------------- LCD_PAL31 -------------------------------------------
+#define LCD_PAL31_R04_0_Pos 0 /*!< LCD PAL31: R04_0 Position */
+#define LCD_PAL31_R04_0_Msk (0x1fUL << LCD_PAL31_R04_0_Pos) /*!< LCD PAL31: R04_0 Mask */
+#define LCD_PAL31_G04_0_Pos 5 /*!< LCD PAL31: G04_0 Position */
+#define LCD_PAL31_G04_0_Msk (0x1fUL << LCD_PAL31_G04_0_Pos) /*!< LCD PAL31: G04_0 Mask */
+#define LCD_PAL31_B04_0_Pos 10 /*!< LCD PAL31: B04_0 Position */
+#define LCD_PAL31_B04_0_Msk (0x1fUL << LCD_PAL31_B04_0_Pos) /*!< LCD PAL31: B04_0 Mask */
+#define LCD_PAL31_I0_Pos 15 /*!< LCD PAL31: I0 Position */
+#define LCD_PAL31_I0_Msk (0x01UL << LCD_PAL31_I0_Pos) /*!< LCD PAL31: I0 Mask */
+#define LCD_PAL31_R14_0_Pos 16 /*!< LCD PAL31: R14_0 Position */
+#define LCD_PAL31_R14_0_Msk (0x1fUL << LCD_PAL31_R14_0_Pos) /*!< LCD PAL31: R14_0 Mask */
+#define LCD_PAL31_G14_0_Pos 21 /*!< LCD PAL31: G14_0 Position */
+#define LCD_PAL31_G14_0_Msk (0x1fUL << LCD_PAL31_G14_0_Pos) /*!< LCD PAL31: G14_0 Mask */
+#define LCD_PAL31_B14_0_Pos 26 /*!< LCD PAL31: B14_0 Position */
+#define LCD_PAL31_B14_0_Msk (0x1fUL << LCD_PAL31_B14_0_Pos) /*!< LCD PAL31: B14_0 Mask */
+#define LCD_PAL31_I1_Pos 31 /*!< LCD PAL31: I1 Position */
+#define LCD_PAL31_I1_Msk (0x01UL << LCD_PAL31_I1_Pos) /*!< LCD PAL31: I1 Mask */
+
+// ---------------------------------------- LCD_PAL32 -------------------------------------------
+#define LCD_PAL32_R04_0_Pos 0 /*!< LCD PAL32: R04_0 Position */
+#define LCD_PAL32_R04_0_Msk (0x1fUL << LCD_PAL32_R04_0_Pos) /*!< LCD PAL32: R04_0 Mask */
+#define LCD_PAL32_G04_0_Pos 5 /*!< LCD PAL32: G04_0 Position */
+#define LCD_PAL32_G04_0_Msk (0x1fUL << LCD_PAL32_G04_0_Pos) /*!< LCD PAL32: G04_0 Mask */
+#define LCD_PAL32_B04_0_Pos 10 /*!< LCD PAL32: B04_0 Position */
+#define LCD_PAL32_B04_0_Msk (0x1fUL << LCD_PAL32_B04_0_Pos) /*!< LCD PAL32: B04_0 Mask */
+#define LCD_PAL32_I0_Pos 15 /*!< LCD PAL32: I0 Position */
+#define LCD_PAL32_I0_Msk (0x01UL << LCD_PAL32_I0_Pos) /*!< LCD PAL32: I0 Mask */
+#define LCD_PAL32_R14_0_Pos 16 /*!< LCD PAL32: R14_0 Position */
+#define LCD_PAL32_R14_0_Msk (0x1fUL << LCD_PAL32_R14_0_Pos) /*!< LCD PAL32: R14_0 Mask */
+#define LCD_PAL32_G14_0_Pos 21 /*!< LCD PAL32: G14_0 Position */
+#define LCD_PAL32_G14_0_Msk (0x1fUL << LCD_PAL32_G14_0_Pos) /*!< LCD PAL32: G14_0 Mask */
+#define LCD_PAL32_B14_0_Pos 26 /*!< LCD PAL32: B14_0 Position */
+#define LCD_PAL32_B14_0_Msk (0x1fUL << LCD_PAL32_B14_0_Pos) /*!< LCD PAL32: B14_0 Mask */
+#define LCD_PAL32_I1_Pos 31 /*!< LCD PAL32: I1 Position */
+#define LCD_PAL32_I1_Msk (0x01UL << LCD_PAL32_I1_Pos) /*!< LCD PAL32: I1 Mask */
+
+// ---------------------------------------- LCD_PAL33 -------------------------------------------
+#define LCD_PAL33_R04_0_Pos 0 /*!< LCD PAL33: R04_0 Position */
+#define LCD_PAL33_R04_0_Msk (0x1fUL << LCD_PAL33_R04_0_Pos) /*!< LCD PAL33: R04_0 Mask */
+#define LCD_PAL33_G04_0_Pos 5 /*!< LCD PAL33: G04_0 Position */
+#define LCD_PAL33_G04_0_Msk (0x1fUL << LCD_PAL33_G04_0_Pos) /*!< LCD PAL33: G04_0 Mask */
+#define LCD_PAL33_B04_0_Pos 10 /*!< LCD PAL33: B04_0 Position */
+#define LCD_PAL33_B04_0_Msk (0x1fUL << LCD_PAL33_B04_0_Pos) /*!< LCD PAL33: B04_0 Mask */
+#define LCD_PAL33_I0_Pos 15 /*!< LCD PAL33: I0 Position */
+#define LCD_PAL33_I0_Msk (0x01UL << LCD_PAL33_I0_Pos) /*!< LCD PAL33: I0 Mask */
+#define LCD_PAL33_R14_0_Pos 16 /*!< LCD PAL33: R14_0 Position */
+#define LCD_PAL33_R14_0_Msk (0x1fUL << LCD_PAL33_R14_0_Pos) /*!< LCD PAL33: R14_0 Mask */
+#define LCD_PAL33_G14_0_Pos 21 /*!< LCD PAL33: G14_0 Position */
+#define LCD_PAL33_G14_0_Msk (0x1fUL << LCD_PAL33_G14_0_Pos) /*!< LCD PAL33: G14_0 Mask */
+#define LCD_PAL33_B14_0_Pos 26 /*!< LCD PAL33: B14_0 Position */
+#define LCD_PAL33_B14_0_Msk (0x1fUL << LCD_PAL33_B14_0_Pos) /*!< LCD PAL33: B14_0 Mask */
+#define LCD_PAL33_I1_Pos 31 /*!< LCD PAL33: I1 Position */
+#define LCD_PAL33_I1_Msk (0x01UL << LCD_PAL33_I1_Pos) /*!< LCD PAL33: I1 Mask */
+
+// ---------------------------------------- LCD_PAL34 -------------------------------------------
+#define LCD_PAL34_R04_0_Pos 0 /*!< LCD PAL34: R04_0 Position */
+#define LCD_PAL34_R04_0_Msk (0x1fUL << LCD_PAL34_R04_0_Pos) /*!< LCD PAL34: R04_0 Mask */
+#define LCD_PAL34_G04_0_Pos 5 /*!< LCD PAL34: G04_0 Position */
+#define LCD_PAL34_G04_0_Msk (0x1fUL << LCD_PAL34_G04_0_Pos) /*!< LCD PAL34: G04_0 Mask */
+#define LCD_PAL34_B04_0_Pos 10 /*!< LCD PAL34: B04_0 Position */
+#define LCD_PAL34_B04_0_Msk (0x1fUL << LCD_PAL34_B04_0_Pos) /*!< LCD PAL34: B04_0 Mask */
+#define LCD_PAL34_I0_Pos 15 /*!< LCD PAL34: I0 Position */
+#define LCD_PAL34_I0_Msk (0x01UL << LCD_PAL34_I0_Pos) /*!< LCD PAL34: I0 Mask */
+#define LCD_PAL34_R14_0_Pos 16 /*!< LCD PAL34: R14_0 Position */
+#define LCD_PAL34_R14_0_Msk (0x1fUL << LCD_PAL34_R14_0_Pos) /*!< LCD PAL34: R14_0 Mask */
+#define LCD_PAL34_G14_0_Pos 21 /*!< LCD PAL34: G14_0 Position */
+#define LCD_PAL34_G14_0_Msk (0x1fUL << LCD_PAL34_G14_0_Pos) /*!< LCD PAL34: G14_0 Mask */
+#define LCD_PAL34_B14_0_Pos 26 /*!< LCD PAL34: B14_0 Position */
+#define LCD_PAL34_B14_0_Msk (0x1fUL << LCD_PAL34_B14_0_Pos) /*!< LCD PAL34: B14_0 Mask */
+#define LCD_PAL34_I1_Pos 31 /*!< LCD PAL34: I1 Position */
+#define LCD_PAL34_I1_Msk (0x01UL << LCD_PAL34_I1_Pos) /*!< LCD PAL34: I1 Mask */
+
+// ---------------------------------------- LCD_PAL35 -------------------------------------------
+#define LCD_PAL35_R04_0_Pos 0 /*!< LCD PAL35: R04_0 Position */
+#define LCD_PAL35_R04_0_Msk (0x1fUL << LCD_PAL35_R04_0_Pos) /*!< LCD PAL35: R04_0 Mask */
+#define LCD_PAL35_G04_0_Pos 5 /*!< LCD PAL35: G04_0 Position */
+#define LCD_PAL35_G04_0_Msk (0x1fUL << LCD_PAL35_G04_0_Pos) /*!< LCD PAL35: G04_0 Mask */
+#define LCD_PAL35_B04_0_Pos 10 /*!< LCD PAL35: B04_0 Position */
+#define LCD_PAL35_B04_0_Msk (0x1fUL << LCD_PAL35_B04_0_Pos) /*!< LCD PAL35: B04_0 Mask */
+#define LCD_PAL35_I0_Pos 15 /*!< LCD PAL35: I0 Position */
+#define LCD_PAL35_I0_Msk (0x01UL << LCD_PAL35_I0_Pos) /*!< LCD PAL35: I0 Mask */
+#define LCD_PAL35_R14_0_Pos 16 /*!< LCD PAL35: R14_0 Position */
+#define LCD_PAL35_R14_0_Msk (0x1fUL << LCD_PAL35_R14_0_Pos) /*!< LCD PAL35: R14_0 Mask */
+#define LCD_PAL35_G14_0_Pos 21 /*!< LCD PAL35: G14_0 Position */
+#define LCD_PAL35_G14_0_Msk (0x1fUL << LCD_PAL35_G14_0_Pos) /*!< LCD PAL35: G14_0 Mask */
+#define LCD_PAL35_B14_0_Pos 26 /*!< LCD PAL35: B14_0 Position */
+#define LCD_PAL35_B14_0_Msk (0x1fUL << LCD_PAL35_B14_0_Pos) /*!< LCD PAL35: B14_0 Mask */
+#define LCD_PAL35_I1_Pos 31 /*!< LCD PAL35: I1 Position */
+#define LCD_PAL35_I1_Msk (0x01UL << LCD_PAL35_I1_Pos) /*!< LCD PAL35: I1 Mask */
+
+// ---------------------------------------- LCD_PAL36 -------------------------------------------
+#define LCD_PAL36_R04_0_Pos 0 /*!< LCD PAL36: R04_0 Position */
+#define LCD_PAL36_R04_0_Msk (0x1fUL << LCD_PAL36_R04_0_Pos) /*!< LCD PAL36: R04_0 Mask */
+#define LCD_PAL36_G04_0_Pos 5 /*!< LCD PAL36: G04_0 Position */
+#define LCD_PAL36_G04_0_Msk (0x1fUL << LCD_PAL36_G04_0_Pos) /*!< LCD PAL36: G04_0 Mask */
+#define LCD_PAL36_B04_0_Pos 10 /*!< LCD PAL36: B04_0 Position */
+#define LCD_PAL36_B04_0_Msk (0x1fUL << LCD_PAL36_B04_0_Pos) /*!< LCD PAL36: B04_0 Mask */
+#define LCD_PAL36_I0_Pos 15 /*!< LCD PAL36: I0 Position */
+#define LCD_PAL36_I0_Msk (0x01UL << LCD_PAL36_I0_Pos) /*!< LCD PAL36: I0 Mask */
+#define LCD_PAL36_R14_0_Pos 16 /*!< LCD PAL36: R14_0 Position */
+#define LCD_PAL36_R14_0_Msk (0x1fUL << LCD_PAL36_R14_0_Pos) /*!< LCD PAL36: R14_0 Mask */
+#define LCD_PAL36_G14_0_Pos 21 /*!< LCD PAL36: G14_0 Position */
+#define LCD_PAL36_G14_0_Msk (0x1fUL << LCD_PAL36_G14_0_Pos) /*!< LCD PAL36: G14_0 Mask */
+#define LCD_PAL36_B14_0_Pos 26 /*!< LCD PAL36: B14_0 Position */
+#define LCD_PAL36_B14_0_Msk (0x1fUL << LCD_PAL36_B14_0_Pos) /*!< LCD PAL36: B14_0 Mask */
+#define LCD_PAL36_I1_Pos 31 /*!< LCD PAL36: I1 Position */
+#define LCD_PAL36_I1_Msk (0x01UL << LCD_PAL36_I1_Pos) /*!< LCD PAL36: I1 Mask */
+
+// ---------------------------------------- LCD_PAL37 -------------------------------------------
+#define LCD_PAL37_R04_0_Pos 0 /*!< LCD PAL37: R04_0 Position */
+#define LCD_PAL37_R04_0_Msk (0x1fUL << LCD_PAL37_R04_0_Pos) /*!< LCD PAL37: R04_0 Mask */
+#define LCD_PAL37_G04_0_Pos 5 /*!< LCD PAL37: G04_0 Position */
+#define LCD_PAL37_G04_0_Msk (0x1fUL << LCD_PAL37_G04_0_Pos) /*!< LCD PAL37: G04_0 Mask */
+#define LCD_PAL37_B04_0_Pos 10 /*!< LCD PAL37: B04_0 Position */
+#define LCD_PAL37_B04_0_Msk (0x1fUL << LCD_PAL37_B04_0_Pos) /*!< LCD PAL37: B04_0 Mask */
+#define LCD_PAL37_I0_Pos 15 /*!< LCD PAL37: I0 Position */
+#define LCD_PAL37_I0_Msk (0x01UL << LCD_PAL37_I0_Pos) /*!< LCD PAL37: I0 Mask */
+#define LCD_PAL37_R14_0_Pos 16 /*!< LCD PAL37: R14_0 Position */
+#define LCD_PAL37_R14_0_Msk (0x1fUL << LCD_PAL37_R14_0_Pos) /*!< LCD PAL37: R14_0 Mask */
+#define LCD_PAL37_G14_0_Pos 21 /*!< LCD PAL37: G14_0 Position */
+#define LCD_PAL37_G14_0_Msk (0x1fUL << LCD_PAL37_G14_0_Pos) /*!< LCD PAL37: G14_0 Mask */
+#define LCD_PAL37_B14_0_Pos 26 /*!< LCD PAL37: B14_0 Position */
+#define LCD_PAL37_B14_0_Msk (0x1fUL << LCD_PAL37_B14_0_Pos) /*!< LCD PAL37: B14_0 Mask */
+#define LCD_PAL37_I1_Pos 31 /*!< LCD PAL37: I1 Position */
+#define LCD_PAL37_I1_Msk (0x01UL << LCD_PAL37_I1_Pos) /*!< LCD PAL37: I1 Mask */
+
+// ---------------------------------------- LCD_PAL38 -------------------------------------------
+#define LCD_PAL38_R04_0_Pos 0 /*!< LCD PAL38: R04_0 Position */
+#define LCD_PAL38_R04_0_Msk (0x1fUL << LCD_PAL38_R04_0_Pos) /*!< LCD PAL38: R04_0 Mask */
+#define LCD_PAL38_G04_0_Pos 5 /*!< LCD PAL38: G04_0 Position */
+#define LCD_PAL38_G04_0_Msk (0x1fUL << LCD_PAL38_G04_0_Pos) /*!< LCD PAL38: G04_0 Mask */
+#define LCD_PAL38_B04_0_Pos 10 /*!< LCD PAL38: B04_0 Position */
+#define LCD_PAL38_B04_0_Msk (0x1fUL << LCD_PAL38_B04_0_Pos) /*!< LCD PAL38: B04_0 Mask */
+#define LCD_PAL38_I0_Pos 15 /*!< LCD PAL38: I0 Position */
+#define LCD_PAL38_I0_Msk (0x01UL << LCD_PAL38_I0_Pos) /*!< LCD PAL38: I0 Mask */
+#define LCD_PAL38_R14_0_Pos 16 /*!< LCD PAL38: R14_0 Position */
+#define LCD_PAL38_R14_0_Msk (0x1fUL << LCD_PAL38_R14_0_Pos) /*!< LCD PAL38: R14_0 Mask */
+#define LCD_PAL38_G14_0_Pos 21 /*!< LCD PAL38: G14_0 Position */
+#define LCD_PAL38_G14_0_Msk (0x1fUL << LCD_PAL38_G14_0_Pos) /*!< LCD PAL38: G14_0 Mask */
+#define LCD_PAL38_B14_0_Pos 26 /*!< LCD PAL38: B14_0 Position */
+#define LCD_PAL38_B14_0_Msk (0x1fUL << LCD_PAL38_B14_0_Pos) /*!< LCD PAL38: B14_0 Mask */
+#define LCD_PAL38_I1_Pos 31 /*!< LCD PAL38: I1 Position */
+#define LCD_PAL38_I1_Msk (0x01UL << LCD_PAL38_I1_Pos) /*!< LCD PAL38: I1 Mask */
+
+// ---------------------------------------- LCD_PAL39 -------------------------------------------
+#define LCD_PAL39_R04_0_Pos 0 /*!< LCD PAL39: R04_0 Position */
+#define LCD_PAL39_R04_0_Msk (0x1fUL << LCD_PAL39_R04_0_Pos) /*!< LCD PAL39: R04_0 Mask */
+#define LCD_PAL39_G04_0_Pos 5 /*!< LCD PAL39: G04_0 Position */
+#define LCD_PAL39_G04_0_Msk (0x1fUL << LCD_PAL39_G04_0_Pos) /*!< LCD PAL39: G04_0 Mask */
+#define LCD_PAL39_B04_0_Pos 10 /*!< LCD PAL39: B04_0 Position */
+#define LCD_PAL39_B04_0_Msk (0x1fUL << LCD_PAL39_B04_0_Pos) /*!< LCD PAL39: B04_0 Mask */
+#define LCD_PAL39_I0_Pos 15 /*!< LCD PAL39: I0 Position */
+#define LCD_PAL39_I0_Msk (0x01UL << LCD_PAL39_I0_Pos) /*!< LCD PAL39: I0 Mask */
+#define LCD_PAL39_R14_0_Pos 16 /*!< LCD PAL39: R14_0 Position */
+#define LCD_PAL39_R14_0_Msk (0x1fUL << LCD_PAL39_R14_0_Pos) /*!< LCD PAL39: R14_0 Mask */
+#define LCD_PAL39_G14_0_Pos 21 /*!< LCD PAL39: G14_0 Position */
+#define LCD_PAL39_G14_0_Msk (0x1fUL << LCD_PAL39_G14_0_Pos) /*!< LCD PAL39: G14_0 Mask */
+#define LCD_PAL39_B14_0_Pos 26 /*!< LCD PAL39: B14_0 Position */
+#define LCD_PAL39_B14_0_Msk (0x1fUL << LCD_PAL39_B14_0_Pos) /*!< LCD PAL39: B14_0 Mask */
+#define LCD_PAL39_I1_Pos 31 /*!< LCD PAL39: I1 Position */
+#define LCD_PAL39_I1_Msk (0x01UL << LCD_PAL39_I1_Pos) /*!< LCD PAL39: I1 Mask */
+
+// ---------------------------------------- LCD_PAL40 -------------------------------------------
+#define LCD_PAL40_R04_0_Pos 0 /*!< LCD PAL40: R04_0 Position */
+#define LCD_PAL40_R04_0_Msk (0x1fUL << LCD_PAL40_R04_0_Pos) /*!< LCD PAL40: R04_0 Mask */
+#define LCD_PAL40_G04_0_Pos 5 /*!< LCD PAL40: G04_0 Position */
+#define LCD_PAL40_G04_0_Msk (0x1fUL << LCD_PAL40_G04_0_Pos) /*!< LCD PAL40: G04_0 Mask */
+#define LCD_PAL40_B04_0_Pos 10 /*!< LCD PAL40: B04_0 Position */
+#define LCD_PAL40_B04_0_Msk (0x1fUL << LCD_PAL40_B04_0_Pos) /*!< LCD PAL40: B04_0 Mask */
+#define LCD_PAL40_I0_Pos 15 /*!< LCD PAL40: I0 Position */
+#define LCD_PAL40_I0_Msk (0x01UL << LCD_PAL40_I0_Pos) /*!< LCD PAL40: I0 Mask */
+#define LCD_PAL40_R14_0_Pos 16 /*!< LCD PAL40: R14_0 Position */
+#define LCD_PAL40_R14_0_Msk (0x1fUL << LCD_PAL40_R14_0_Pos) /*!< LCD PAL40: R14_0 Mask */
+#define LCD_PAL40_G14_0_Pos 21 /*!< LCD PAL40: G14_0 Position */
+#define LCD_PAL40_G14_0_Msk (0x1fUL << LCD_PAL40_G14_0_Pos) /*!< LCD PAL40: G14_0 Mask */
+#define LCD_PAL40_B14_0_Pos 26 /*!< LCD PAL40: B14_0 Position */
+#define LCD_PAL40_B14_0_Msk (0x1fUL << LCD_PAL40_B14_0_Pos) /*!< LCD PAL40: B14_0 Mask */
+#define LCD_PAL40_I1_Pos 31 /*!< LCD PAL40: I1 Position */
+#define LCD_PAL40_I1_Msk (0x01UL << LCD_PAL40_I1_Pos) /*!< LCD PAL40: I1 Mask */
+
+// ---------------------------------------- LCD_PAL41 -------------------------------------------
+#define LCD_PAL41_R04_0_Pos 0 /*!< LCD PAL41: R04_0 Position */
+#define LCD_PAL41_R04_0_Msk (0x1fUL << LCD_PAL41_R04_0_Pos) /*!< LCD PAL41: R04_0 Mask */
+#define LCD_PAL41_G04_0_Pos 5 /*!< LCD PAL41: G04_0 Position */
+#define LCD_PAL41_G04_0_Msk (0x1fUL << LCD_PAL41_G04_0_Pos) /*!< LCD PAL41: G04_0 Mask */
+#define LCD_PAL41_B04_0_Pos 10 /*!< LCD PAL41: B04_0 Position */
+#define LCD_PAL41_B04_0_Msk (0x1fUL << LCD_PAL41_B04_0_Pos) /*!< LCD PAL41: B04_0 Mask */
+#define LCD_PAL41_I0_Pos 15 /*!< LCD PAL41: I0 Position */
+#define LCD_PAL41_I0_Msk (0x01UL << LCD_PAL41_I0_Pos) /*!< LCD PAL41: I0 Mask */
+#define LCD_PAL41_R14_0_Pos 16 /*!< LCD PAL41: R14_0 Position */
+#define LCD_PAL41_R14_0_Msk (0x1fUL << LCD_PAL41_R14_0_Pos) /*!< LCD PAL41: R14_0 Mask */
+#define LCD_PAL41_G14_0_Pos 21 /*!< LCD PAL41: G14_0 Position */
+#define LCD_PAL41_G14_0_Msk (0x1fUL << LCD_PAL41_G14_0_Pos) /*!< LCD PAL41: G14_0 Mask */
+#define LCD_PAL41_B14_0_Pos 26 /*!< LCD PAL41: B14_0 Position */
+#define LCD_PAL41_B14_0_Msk (0x1fUL << LCD_PAL41_B14_0_Pos) /*!< LCD PAL41: B14_0 Mask */
+#define LCD_PAL41_I1_Pos 31 /*!< LCD PAL41: I1 Position */
+#define LCD_PAL41_I1_Msk (0x01UL << LCD_PAL41_I1_Pos) /*!< LCD PAL41: I1 Mask */
+
+// ---------------------------------------- LCD_PAL42 -------------------------------------------
+#define LCD_PAL42_R04_0_Pos 0 /*!< LCD PAL42: R04_0 Position */
+#define LCD_PAL42_R04_0_Msk (0x1fUL << LCD_PAL42_R04_0_Pos) /*!< LCD PAL42: R04_0 Mask */
+#define LCD_PAL42_G04_0_Pos 5 /*!< LCD PAL42: G04_0 Position */
+#define LCD_PAL42_G04_0_Msk (0x1fUL << LCD_PAL42_G04_0_Pos) /*!< LCD PAL42: G04_0 Mask */
+#define LCD_PAL42_B04_0_Pos 10 /*!< LCD PAL42: B04_0 Position */
+#define LCD_PAL42_B04_0_Msk (0x1fUL << LCD_PAL42_B04_0_Pos) /*!< LCD PAL42: B04_0 Mask */
+#define LCD_PAL42_I0_Pos 15 /*!< LCD PAL42: I0 Position */
+#define LCD_PAL42_I0_Msk (0x01UL << LCD_PAL42_I0_Pos) /*!< LCD PAL42: I0 Mask */
+#define LCD_PAL42_R14_0_Pos 16 /*!< LCD PAL42: R14_0 Position */
+#define LCD_PAL42_R14_0_Msk (0x1fUL << LCD_PAL42_R14_0_Pos) /*!< LCD PAL42: R14_0 Mask */
+#define LCD_PAL42_G14_0_Pos 21 /*!< LCD PAL42: G14_0 Position */
+#define LCD_PAL42_G14_0_Msk (0x1fUL << LCD_PAL42_G14_0_Pos) /*!< LCD PAL42: G14_0 Mask */
+#define LCD_PAL42_B14_0_Pos 26 /*!< LCD PAL42: B14_0 Position */
+#define LCD_PAL42_B14_0_Msk (0x1fUL << LCD_PAL42_B14_0_Pos) /*!< LCD PAL42: B14_0 Mask */
+#define LCD_PAL42_I1_Pos 31 /*!< LCD PAL42: I1 Position */
+#define LCD_PAL42_I1_Msk (0x01UL << LCD_PAL42_I1_Pos) /*!< LCD PAL42: I1 Mask */
+
+// ---------------------------------------- LCD_PAL43 -------------------------------------------
+#define LCD_PAL43_R04_0_Pos 0 /*!< LCD PAL43: R04_0 Position */
+#define LCD_PAL43_R04_0_Msk (0x1fUL << LCD_PAL43_R04_0_Pos) /*!< LCD PAL43: R04_0 Mask */
+#define LCD_PAL43_G04_0_Pos 5 /*!< LCD PAL43: G04_0 Position */
+#define LCD_PAL43_G04_0_Msk (0x1fUL << LCD_PAL43_G04_0_Pos) /*!< LCD PAL43: G04_0 Mask */
+#define LCD_PAL43_B04_0_Pos 10 /*!< LCD PAL43: B04_0 Position */
+#define LCD_PAL43_B04_0_Msk (0x1fUL << LCD_PAL43_B04_0_Pos) /*!< LCD PAL43: B04_0 Mask */
+#define LCD_PAL43_I0_Pos 15 /*!< LCD PAL43: I0 Position */
+#define LCD_PAL43_I0_Msk (0x01UL << LCD_PAL43_I0_Pos) /*!< LCD PAL43: I0 Mask */
+#define LCD_PAL43_R14_0_Pos 16 /*!< LCD PAL43: R14_0 Position */
+#define LCD_PAL43_R14_0_Msk (0x1fUL << LCD_PAL43_R14_0_Pos) /*!< LCD PAL43: R14_0 Mask */
+#define LCD_PAL43_G14_0_Pos 21 /*!< LCD PAL43: G14_0 Position */
+#define LCD_PAL43_G14_0_Msk (0x1fUL << LCD_PAL43_G14_0_Pos) /*!< LCD PAL43: G14_0 Mask */
+#define LCD_PAL43_B14_0_Pos 26 /*!< LCD PAL43: B14_0 Position */
+#define LCD_PAL43_B14_0_Msk (0x1fUL << LCD_PAL43_B14_0_Pos) /*!< LCD PAL43: B14_0 Mask */
+#define LCD_PAL43_I1_Pos 31 /*!< LCD PAL43: I1 Position */
+#define LCD_PAL43_I1_Msk (0x01UL << LCD_PAL43_I1_Pos) /*!< LCD PAL43: I1 Mask */
+
+// ---------------------------------------- LCD_PAL44 -------------------------------------------
+#define LCD_PAL44_R04_0_Pos 0 /*!< LCD PAL44: R04_0 Position */
+#define LCD_PAL44_R04_0_Msk (0x1fUL << LCD_PAL44_R04_0_Pos) /*!< LCD PAL44: R04_0 Mask */
+#define LCD_PAL44_G04_0_Pos 5 /*!< LCD PAL44: G04_0 Position */
+#define LCD_PAL44_G04_0_Msk (0x1fUL << LCD_PAL44_G04_0_Pos) /*!< LCD PAL44: G04_0 Mask */
+#define LCD_PAL44_B04_0_Pos 10 /*!< LCD PAL44: B04_0 Position */
+#define LCD_PAL44_B04_0_Msk (0x1fUL << LCD_PAL44_B04_0_Pos) /*!< LCD PAL44: B04_0 Mask */
+#define LCD_PAL44_I0_Pos 15 /*!< LCD PAL44: I0 Position */
+#define LCD_PAL44_I0_Msk (0x01UL << LCD_PAL44_I0_Pos) /*!< LCD PAL44: I0 Mask */
+#define LCD_PAL44_R14_0_Pos 16 /*!< LCD PAL44: R14_0 Position */
+#define LCD_PAL44_R14_0_Msk (0x1fUL << LCD_PAL44_R14_0_Pos) /*!< LCD PAL44: R14_0 Mask */
+#define LCD_PAL44_G14_0_Pos 21 /*!< LCD PAL44: G14_0 Position */
+#define LCD_PAL44_G14_0_Msk (0x1fUL << LCD_PAL44_G14_0_Pos) /*!< LCD PAL44: G14_0 Mask */
+#define LCD_PAL44_B14_0_Pos 26 /*!< LCD PAL44: B14_0 Position */
+#define LCD_PAL44_B14_0_Msk (0x1fUL << LCD_PAL44_B14_0_Pos) /*!< LCD PAL44: B14_0 Mask */
+#define LCD_PAL44_I1_Pos 31 /*!< LCD PAL44: I1 Position */
+#define LCD_PAL44_I1_Msk (0x01UL << LCD_PAL44_I1_Pos) /*!< LCD PAL44: I1 Mask */
+
+// ---------------------------------------- LCD_PAL45 -------------------------------------------
+#define LCD_PAL45_R04_0_Pos 0 /*!< LCD PAL45: R04_0 Position */
+#define LCD_PAL45_R04_0_Msk (0x1fUL << LCD_PAL45_R04_0_Pos) /*!< LCD PAL45: R04_0 Mask */
+#define LCD_PAL45_G04_0_Pos 5 /*!< LCD PAL45: G04_0 Position */
+#define LCD_PAL45_G04_0_Msk (0x1fUL << LCD_PAL45_G04_0_Pos) /*!< LCD PAL45: G04_0 Mask */
+#define LCD_PAL45_B04_0_Pos 10 /*!< LCD PAL45: B04_0 Position */
+#define LCD_PAL45_B04_0_Msk (0x1fUL << LCD_PAL45_B04_0_Pos) /*!< LCD PAL45: B04_0 Mask */
+#define LCD_PAL45_I0_Pos 15 /*!< LCD PAL45: I0 Position */
+#define LCD_PAL45_I0_Msk (0x01UL << LCD_PAL45_I0_Pos) /*!< LCD PAL45: I0 Mask */
+#define LCD_PAL45_R14_0_Pos 16 /*!< LCD PAL45: R14_0 Position */
+#define LCD_PAL45_R14_0_Msk (0x1fUL << LCD_PAL45_R14_0_Pos) /*!< LCD PAL45: R14_0 Mask */
+#define LCD_PAL45_G14_0_Pos 21 /*!< LCD PAL45: G14_0 Position */
+#define LCD_PAL45_G14_0_Msk (0x1fUL << LCD_PAL45_G14_0_Pos) /*!< LCD PAL45: G14_0 Mask */
+#define LCD_PAL45_B14_0_Pos 26 /*!< LCD PAL45: B14_0 Position */
+#define LCD_PAL45_B14_0_Msk (0x1fUL << LCD_PAL45_B14_0_Pos) /*!< LCD PAL45: B14_0 Mask */
+#define LCD_PAL45_I1_Pos 31 /*!< LCD PAL45: I1 Position */
+#define LCD_PAL45_I1_Msk (0x01UL << LCD_PAL45_I1_Pos) /*!< LCD PAL45: I1 Mask */
+
+// ---------------------------------------- LCD_PAL46 -------------------------------------------
+#define LCD_PAL46_R04_0_Pos 0 /*!< LCD PAL46: R04_0 Position */
+#define LCD_PAL46_R04_0_Msk (0x1fUL << LCD_PAL46_R04_0_Pos) /*!< LCD PAL46: R04_0 Mask */
+#define LCD_PAL46_G04_0_Pos 5 /*!< LCD PAL46: G04_0 Position */
+#define LCD_PAL46_G04_0_Msk (0x1fUL << LCD_PAL46_G04_0_Pos) /*!< LCD PAL46: G04_0 Mask */
+#define LCD_PAL46_B04_0_Pos 10 /*!< LCD PAL46: B04_0 Position */
+#define LCD_PAL46_B04_0_Msk (0x1fUL << LCD_PAL46_B04_0_Pos) /*!< LCD PAL46: B04_0 Mask */
+#define LCD_PAL46_I0_Pos 15 /*!< LCD PAL46: I0 Position */
+#define LCD_PAL46_I0_Msk (0x01UL << LCD_PAL46_I0_Pos) /*!< LCD PAL46: I0 Mask */
+#define LCD_PAL46_R14_0_Pos 16 /*!< LCD PAL46: R14_0 Position */
+#define LCD_PAL46_R14_0_Msk (0x1fUL << LCD_PAL46_R14_0_Pos) /*!< LCD PAL46: R14_0 Mask */
+#define LCD_PAL46_G14_0_Pos 21 /*!< LCD PAL46: G14_0 Position */
+#define LCD_PAL46_G14_0_Msk (0x1fUL << LCD_PAL46_G14_0_Pos) /*!< LCD PAL46: G14_0 Mask */
+#define LCD_PAL46_B14_0_Pos 26 /*!< LCD PAL46: B14_0 Position */
+#define LCD_PAL46_B14_0_Msk (0x1fUL << LCD_PAL46_B14_0_Pos) /*!< LCD PAL46: B14_0 Mask */
+#define LCD_PAL46_I1_Pos 31 /*!< LCD PAL46: I1 Position */
+#define LCD_PAL46_I1_Msk (0x01UL << LCD_PAL46_I1_Pos) /*!< LCD PAL46: I1 Mask */
+
+// ---------------------------------------- LCD_PAL47 -------------------------------------------
+#define LCD_PAL47_R04_0_Pos 0 /*!< LCD PAL47: R04_0 Position */
+#define LCD_PAL47_R04_0_Msk (0x1fUL << LCD_PAL47_R04_0_Pos) /*!< LCD PAL47: R04_0 Mask */
+#define LCD_PAL47_G04_0_Pos 5 /*!< LCD PAL47: G04_0 Position */
+#define LCD_PAL47_G04_0_Msk (0x1fUL << LCD_PAL47_G04_0_Pos) /*!< LCD PAL47: G04_0 Mask */
+#define LCD_PAL47_B04_0_Pos 10 /*!< LCD PAL47: B04_0 Position */
+#define LCD_PAL47_B04_0_Msk (0x1fUL << LCD_PAL47_B04_0_Pos) /*!< LCD PAL47: B04_0 Mask */
+#define LCD_PAL47_I0_Pos 15 /*!< LCD PAL47: I0 Position */
+#define LCD_PAL47_I0_Msk (0x01UL << LCD_PAL47_I0_Pos) /*!< LCD PAL47: I0 Mask */
+#define LCD_PAL47_R14_0_Pos 16 /*!< LCD PAL47: R14_0 Position */
+#define LCD_PAL47_R14_0_Msk (0x1fUL << LCD_PAL47_R14_0_Pos) /*!< LCD PAL47: R14_0 Mask */
+#define LCD_PAL47_G14_0_Pos 21 /*!< LCD PAL47: G14_0 Position */
+#define LCD_PAL47_G14_0_Msk (0x1fUL << LCD_PAL47_G14_0_Pos) /*!< LCD PAL47: G14_0 Mask */
+#define LCD_PAL47_B14_0_Pos 26 /*!< LCD PAL47: B14_0 Position */
+#define LCD_PAL47_B14_0_Msk (0x1fUL << LCD_PAL47_B14_0_Pos) /*!< LCD PAL47: B14_0 Mask */
+#define LCD_PAL47_I1_Pos 31 /*!< LCD PAL47: I1 Position */
+#define LCD_PAL47_I1_Msk (0x01UL << LCD_PAL47_I1_Pos) /*!< LCD PAL47: I1 Mask */
+
+// ---------------------------------------- LCD_PAL48 -------------------------------------------
+#define LCD_PAL48_R04_0_Pos 0 /*!< LCD PAL48: R04_0 Position */
+#define LCD_PAL48_R04_0_Msk (0x1fUL << LCD_PAL48_R04_0_Pos) /*!< LCD PAL48: R04_0 Mask */
+#define LCD_PAL48_G04_0_Pos 5 /*!< LCD PAL48: G04_0 Position */
+#define LCD_PAL48_G04_0_Msk (0x1fUL << LCD_PAL48_G04_0_Pos) /*!< LCD PAL48: G04_0 Mask */
+#define LCD_PAL48_B04_0_Pos 10 /*!< LCD PAL48: B04_0 Position */
+#define LCD_PAL48_B04_0_Msk (0x1fUL << LCD_PAL48_B04_0_Pos) /*!< LCD PAL48: B04_0 Mask */
+#define LCD_PAL48_I0_Pos 15 /*!< LCD PAL48: I0 Position */
+#define LCD_PAL48_I0_Msk (0x01UL << LCD_PAL48_I0_Pos) /*!< LCD PAL48: I0 Mask */
+#define LCD_PAL48_R14_0_Pos 16 /*!< LCD PAL48: R14_0 Position */
+#define LCD_PAL48_R14_0_Msk (0x1fUL << LCD_PAL48_R14_0_Pos) /*!< LCD PAL48: R14_0 Mask */
+#define LCD_PAL48_G14_0_Pos 21 /*!< LCD PAL48: G14_0 Position */
+#define LCD_PAL48_G14_0_Msk (0x1fUL << LCD_PAL48_G14_0_Pos) /*!< LCD PAL48: G14_0 Mask */
+#define LCD_PAL48_B14_0_Pos 26 /*!< LCD PAL48: B14_0 Position */
+#define LCD_PAL48_B14_0_Msk (0x1fUL << LCD_PAL48_B14_0_Pos) /*!< LCD PAL48: B14_0 Mask */
+#define LCD_PAL48_I1_Pos 31 /*!< LCD PAL48: I1 Position */
+#define LCD_PAL48_I1_Msk (0x01UL << LCD_PAL48_I1_Pos) /*!< LCD PAL48: I1 Mask */
+
+// ---------------------------------------- LCD_PAL49 -------------------------------------------
+#define LCD_PAL49_R04_0_Pos 0 /*!< LCD PAL49: R04_0 Position */
+#define LCD_PAL49_R04_0_Msk (0x1fUL << LCD_PAL49_R04_0_Pos) /*!< LCD PAL49: R04_0 Mask */
+#define LCD_PAL49_G04_0_Pos 5 /*!< LCD PAL49: G04_0 Position */
+#define LCD_PAL49_G04_0_Msk (0x1fUL << LCD_PAL49_G04_0_Pos) /*!< LCD PAL49: G04_0 Mask */
+#define LCD_PAL49_B04_0_Pos 10 /*!< LCD PAL49: B04_0 Position */
+#define LCD_PAL49_B04_0_Msk (0x1fUL << LCD_PAL49_B04_0_Pos) /*!< LCD PAL49: B04_0 Mask */
+#define LCD_PAL49_I0_Pos 15 /*!< LCD PAL49: I0 Position */
+#define LCD_PAL49_I0_Msk (0x01UL << LCD_PAL49_I0_Pos) /*!< LCD PAL49: I0 Mask */
+#define LCD_PAL49_R14_0_Pos 16 /*!< LCD PAL49: R14_0 Position */
+#define LCD_PAL49_R14_0_Msk (0x1fUL << LCD_PAL49_R14_0_Pos) /*!< LCD PAL49: R14_0 Mask */
+#define LCD_PAL49_G14_0_Pos 21 /*!< LCD PAL49: G14_0 Position */
+#define LCD_PAL49_G14_0_Msk (0x1fUL << LCD_PAL49_G14_0_Pos) /*!< LCD PAL49: G14_0 Mask */
+#define LCD_PAL49_B14_0_Pos 26 /*!< LCD PAL49: B14_0 Position */
+#define LCD_PAL49_B14_0_Msk (0x1fUL << LCD_PAL49_B14_0_Pos) /*!< LCD PAL49: B14_0 Mask */
+#define LCD_PAL49_I1_Pos 31 /*!< LCD PAL49: I1 Position */
+#define LCD_PAL49_I1_Msk (0x01UL << LCD_PAL49_I1_Pos) /*!< LCD PAL49: I1 Mask */
+
+// ---------------------------------------- LCD_PAL50 -------------------------------------------
+#define LCD_PAL50_R04_0_Pos 0 /*!< LCD PAL50: R04_0 Position */
+#define LCD_PAL50_R04_0_Msk (0x1fUL << LCD_PAL50_R04_0_Pos) /*!< LCD PAL50: R04_0 Mask */
+#define LCD_PAL50_G04_0_Pos 5 /*!< LCD PAL50: G04_0 Position */
+#define LCD_PAL50_G04_0_Msk (0x1fUL << LCD_PAL50_G04_0_Pos) /*!< LCD PAL50: G04_0 Mask */
+#define LCD_PAL50_B04_0_Pos 10 /*!< LCD PAL50: B04_0 Position */
+#define LCD_PAL50_B04_0_Msk (0x1fUL << LCD_PAL50_B04_0_Pos) /*!< LCD PAL50: B04_0 Mask */
+#define LCD_PAL50_I0_Pos 15 /*!< LCD PAL50: I0 Position */
+#define LCD_PAL50_I0_Msk (0x01UL << LCD_PAL50_I0_Pos) /*!< LCD PAL50: I0 Mask */
+#define LCD_PAL50_R14_0_Pos 16 /*!< LCD PAL50: R14_0 Position */
+#define LCD_PAL50_R14_0_Msk (0x1fUL << LCD_PAL50_R14_0_Pos) /*!< LCD PAL50: R14_0 Mask */
+#define LCD_PAL50_G14_0_Pos 21 /*!< LCD PAL50: G14_0 Position */
+#define LCD_PAL50_G14_0_Msk (0x1fUL << LCD_PAL50_G14_0_Pos) /*!< LCD PAL50: G14_0 Mask */
+#define LCD_PAL50_B14_0_Pos 26 /*!< LCD PAL50: B14_0 Position */
+#define LCD_PAL50_B14_0_Msk (0x1fUL << LCD_PAL50_B14_0_Pos) /*!< LCD PAL50: B14_0 Mask */
+#define LCD_PAL50_I1_Pos 31 /*!< LCD PAL50: I1 Position */
+#define LCD_PAL50_I1_Msk (0x01UL << LCD_PAL50_I1_Pos) /*!< LCD PAL50: I1 Mask */
+
+// ---------------------------------------- LCD_PAL51 -------------------------------------------
+#define LCD_PAL51_R04_0_Pos 0 /*!< LCD PAL51: R04_0 Position */
+#define LCD_PAL51_R04_0_Msk (0x1fUL << LCD_PAL51_R04_0_Pos) /*!< LCD PAL51: R04_0 Mask */
+#define LCD_PAL51_G04_0_Pos 5 /*!< LCD PAL51: G04_0 Position */
+#define LCD_PAL51_G04_0_Msk (0x1fUL << LCD_PAL51_G04_0_Pos) /*!< LCD PAL51: G04_0 Mask */
+#define LCD_PAL51_B04_0_Pos 10 /*!< LCD PAL51: B04_0 Position */
+#define LCD_PAL51_B04_0_Msk (0x1fUL << LCD_PAL51_B04_0_Pos) /*!< LCD PAL51: B04_0 Mask */
+#define LCD_PAL51_I0_Pos 15 /*!< LCD PAL51: I0 Position */
+#define LCD_PAL51_I0_Msk (0x01UL << LCD_PAL51_I0_Pos) /*!< LCD PAL51: I0 Mask */
+#define LCD_PAL51_R14_0_Pos 16 /*!< LCD PAL51: R14_0 Position */
+#define LCD_PAL51_R14_0_Msk (0x1fUL << LCD_PAL51_R14_0_Pos) /*!< LCD PAL51: R14_0 Mask */
+#define LCD_PAL51_G14_0_Pos 21 /*!< LCD PAL51: G14_0 Position */
+#define LCD_PAL51_G14_0_Msk (0x1fUL << LCD_PAL51_G14_0_Pos) /*!< LCD PAL51: G14_0 Mask */
+#define LCD_PAL51_B14_0_Pos 26 /*!< LCD PAL51: B14_0 Position */
+#define LCD_PAL51_B14_0_Msk (0x1fUL << LCD_PAL51_B14_0_Pos) /*!< LCD PAL51: B14_0 Mask */
+#define LCD_PAL51_I1_Pos 31 /*!< LCD PAL51: I1 Position */
+#define LCD_PAL51_I1_Msk (0x01UL << LCD_PAL51_I1_Pos) /*!< LCD PAL51: I1 Mask */
+
+// ---------------------------------------- LCD_PAL52 -------------------------------------------
+#define LCD_PAL52_R04_0_Pos 0 /*!< LCD PAL52: R04_0 Position */
+#define LCD_PAL52_R04_0_Msk (0x1fUL << LCD_PAL52_R04_0_Pos) /*!< LCD PAL52: R04_0 Mask */
+#define LCD_PAL52_G04_0_Pos 5 /*!< LCD PAL52: G04_0 Position */
+#define LCD_PAL52_G04_0_Msk (0x1fUL << LCD_PAL52_G04_0_Pos) /*!< LCD PAL52: G04_0 Mask */
+#define LCD_PAL52_B04_0_Pos 10 /*!< LCD PAL52: B04_0 Position */
+#define LCD_PAL52_B04_0_Msk (0x1fUL << LCD_PAL52_B04_0_Pos) /*!< LCD PAL52: B04_0 Mask */
+#define LCD_PAL52_I0_Pos 15 /*!< LCD PAL52: I0 Position */
+#define LCD_PAL52_I0_Msk (0x01UL << LCD_PAL52_I0_Pos) /*!< LCD PAL52: I0 Mask */
+#define LCD_PAL52_R14_0_Pos 16 /*!< LCD PAL52: R14_0 Position */
+#define LCD_PAL52_R14_0_Msk (0x1fUL << LCD_PAL52_R14_0_Pos) /*!< LCD PAL52: R14_0 Mask */
+#define LCD_PAL52_G14_0_Pos 21 /*!< LCD PAL52: G14_0 Position */
+#define LCD_PAL52_G14_0_Msk (0x1fUL << LCD_PAL52_G14_0_Pos) /*!< LCD PAL52: G14_0 Mask */
+#define LCD_PAL52_B14_0_Pos 26 /*!< LCD PAL52: B14_0 Position */
+#define LCD_PAL52_B14_0_Msk (0x1fUL << LCD_PAL52_B14_0_Pos) /*!< LCD PAL52: B14_0 Mask */
+#define LCD_PAL52_I1_Pos 31 /*!< LCD PAL52: I1 Position */
+#define LCD_PAL52_I1_Msk (0x01UL << LCD_PAL52_I1_Pos) /*!< LCD PAL52: I1 Mask */
+
+// ---------------------------------------- LCD_PAL53 -------------------------------------------
+#define LCD_PAL53_R04_0_Pos 0 /*!< LCD PAL53: R04_0 Position */
+#define LCD_PAL53_R04_0_Msk (0x1fUL << LCD_PAL53_R04_0_Pos) /*!< LCD PAL53: R04_0 Mask */
+#define LCD_PAL53_G04_0_Pos 5 /*!< LCD PAL53: G04_0 Position */
+#define LCD_PAL53_G04_0_Msk (0x1fUL << LCD_PAL53_G04_0_Pos) /*!< LCD PAL53: G04_0 Mask */
+#define LCD_PAL53_B04_0_Pos 10 /*!< LCD PAL53: B04_0 Position */
+#define LCD_PAL53_B04_0_Msk (0x1fUL << LCD_PAL53_B04_0_Pos) /*!< LCD PAL53: B04_0 Mask */
+#define LCD_PAL53_I0_Pos 15 /*!< LCD PAL53: I0 Position */
+#define LCD_PAL53_I0_Msk (0x01UL << LCD_PAL53_I0_Pos) /*!< LCD PAL53: I0 Mask */
+#define LCD_PAL53_R14_0_Pos 16 /*!< LCD PAL53: R14_0 Position */
+#define LCD_PAL53_R14_0_Msk (0x1fUL << LCD_PAL53_R14_0_Pos) /*!< LCD PAL53: R14_0 Mask */
+#define LCD_PAL53_G14_0_Pos 21 /*!< LCD PAL53: G14_0 Position */
+#define LCD_PAL53_G14_0_Msk (0x1fUL << LCD_PAL53_G14_0_Pos) /*!< LCD PAL53: G14_0 Mask */
+#define LCD_PAL53_B14_0_Pos 26 /*!< LCD PAL53: B14_0 Position */
+#define LCD_PAL53_B14_0_Msk (0x1fUL << LCD_PAL53_B14_0_Pos) /*!< LCD PAL53: B14_0 Mask */
+#define LCD_PAL53_I1_Pos 31 /*!< LCD PAL53: I1 Position */
+#define LCD_PAL53_I1_Msk (0x01UL << LCD_PAL53_I1_Pos) /*!< LCD PAL53: I1 Mask */
+
+// ---------------------------------------- LCD_PAL54 -------------------------------------------
+#define LCD_PAL54_R04_0_Pos 0 /*!< LCD PAL54: R04_0 Position */
+#define LCD_PAL54_R04_0_Msk (0x1fUL << LCD_PAL54_R04_0_Pos) /*!< LCD PAL54: R04_0 Mask */
+#define LCD_PAL54_G04_0_Pos 5 /*!< LCD PAL54: G04_0 Position */
+#define LCD_PAL54_G04_0_Msk (0x1fUL << LCD_PAL54_G04_0_Pos) /*!< LCD PAL54: G04_0 Mask */
+#define LCD_PAL54_B04_0_Pos 10 /*!< LCD PAL54: B04_0 Position */
+#define LCD_PAL54_B04_0_Msk (0x1fUL << LCD_PAL54_B04_0_Pos) /*!< LCD PAL54: B04_0 Mask */
+#define LCD_PAL54_I0_Pos 15 /*!< LCD PAL54: I0 Position */
+#define LCD_PAL54_I0_Msk (0x01UL << LCD_PAL54_I0_Pos) /*!< LCD PAL54: I0 Mask */
+#define LCD_PAL54_R14_0_Pos 16 /*!< LCD PAL54: R14_0 Position */
+#define LCD_PAL54_R14_0_Msk (0x1fUL << LCD_PAL54_R14_0_Pos) /*!< LCD PAL54: R14_0 Mask */
+#define LCD_PAL54_G14_0_Pos 21 /*!< LCD PAL54: G14_0 Position */
+#define LCD_PAL54_G14_0_Msk (0x1fUL << LCD_PAL54_G14_0_Pos) /*!< LCD PAL54: G14_0 Mask */
+#define LCD_PAL54_B14_0_Pos 26 /*!< LCD PAL54: B14_0 Position */
+#define LCD_PAL54_B14_0_Msk (0x1fUL << LCD_PAL54_B14_0_Pos) /*!< LCD PAL54: B14_0 Mask */
+#define LCD_PAL54_I1_Pos 31 /*!< LCD PAL54: I1 Position */
+#define LCD_PAL54_I1_Msk (0x01UL << LCD_PAL54_I1_Pos) /*!< LCD PAL54: I1 Mask */
+
+// ---------------------------------------- LCD_PAL55 -------------------------------------------
+#define LCD_PAL55_R04_0_Pos 0 /*!< LCD PAL55: R04_0 Position */
+#define LCD_PAL55_R04_0_Msk (0x1fUL << LCD_PAL55_R04_0_Pos) /*!< LCD PAL55: R04_0 Mask */
+#define LCD_PAL55_G04_0_Pos 5 /*!< LCD PAL55: G04_0 Position */
+#define LCD_PAL55_G04_0_Msk (0x1fUL << LCD_PAL55_G04_0_Pos) /*!< LCD PAL55: G04_0 Mask */
+#define LCD_PAL55_B04_0_Pos 10 /*!< LCD PAL55: B04_0 Position */
+#define LCD_PAL55_B04_0_Msk (0x1fUL << LCD_PAL55_B04_0_Pos) /*!< LCD PAL55: B04_0 Mask */
+#define LCD_PAL55_I0_Pos 15 /*!< LCD PAL55: I0 Position */
+#define LCD_PAL55_I0_Msk (0x01UL << LCD_PAL55_I0_Pos) /*!< LCD PAL55: I0 Mask */
+#define LCD_PAL55_R14_0_Pos 16 /*!< LCD PAL55: R14_0 Position */
+#define LCD_PAL55_R14_0_Msk (0x1fUL << LCD_PAL55_R14_0_Pos) /*!< LCD PAL55: R14_0 Mask */
+#define LCD_PAL55_G14_0_Pos 21 /*!< LCD PAL55: G14_0 Position */
+#define LCD_PAL55_G14_0_Msk (0x1fUL << LCD_PAL55_G14_0_Pos) /*!< LCD PAL55: G14_0 Mask */
+#define LCD_PAL55_B14_0_Pos 26 /*!< LCD PAL55: B14_0 Position */
+#define LCD_PAL55_B14_0_Msk (0x1fUL << LCD_PAL55_B14_0_Pos) /*!< LCD PAL55: B14_0 Mask */
+#define LCD_PAL55_I1_Pos 31 /*!< LCD PAL55: I1 Position */
+#define LCD_PAL55_I1_Msk (0x01UL << LCD_PAL55_I1_Pos) /*!< LCD PAL55: I1 Mask */
+
+// ---------------------------------------- LCD_PAL56 -------------------------------------------
+#define LCD_PAL56_R04_0_Pos 0 /*!< LCD PAL56: R04_0 Position */
+#define LCD_PAL56_R04_0_Msk (0x1fUL << LCD_PAL56_R04_0_Pos) /*!< LCD PAL56: R04_0 Mask */
+#define LCD_PAL56_G04_0_Pos 5 /*!< LCD PAL56: G04_0 Position */
+#define LCD_PAL56_G04_0_Msk (0x1fUL << LCD_PAL56_G04_0_Pos) /*!< LCD PAL56: G04_0 Mask */
+#define LCD_PAL56_B04_0_Pos 10 /*!< LCD PAL56: B04_0 Position */
+#define LCD_PAL56_B04_0_Msk (0x1fUL << LCD_PAL56_B04_0_Pos) /*!< LCD PAL56: B04_0 Mask */
+#define LCD_PAL56_I0_Pos 15 /*!< LCD PAL56: I0 Position */
+#define LCD_PAL56_I0_Msk (0x01UL << LCD_PAL56_I0_Pos) /*!< LCD PAL56: I0 Mask */
+#define LCD_PAL56_R14_0_Pos 16 /*!< LCD PAL56: R14_0 Position */
+#define LCD_PAL56_R14_0_Msk (0x1fUL << LCD_PAL56_R14_0_Pos) /*!< LCD PAL56: R14_0 Mask */
+#define LCD_PAL56_G14_0_Pos 21 /*!< LCD PAL56: G14_0 Position */
+#define LCD_PAL56_G14_0_Msk (0x1fUL << LCD_PAL56_G14_0_Pos) /*!< LCD PAL56: G14_0 Mask */
+#define LCD_PAL56_B14_0_Pos 26 /*!< LCD PAL56: B14_0 Position */
+#define LCD_PAL56_B14_0_Msk (0x1fUL << LCD_PAL56_B14_0_Pos) /*!< LCD PAL56: B14_0 Mask */
+#define LCD_PAL56_I1_Pos 31 /*!< LCD PAL56: I1 Position */
+#define LCD_PAL56_I1_Msk (0x01UL << LCD_PAL56_I1_Pos) /*!< LCD PAL56: I1 Mask */
+
+// ---------------------------------------- LCD_PAL57 -------------------------------------------
+#define LCD_PAL57_R04_0_Pos 0 /*!< LCD PAL57: R04_0 Position */
+#define LCD_PAL57_R04_0_Msk (0x1fUL << LCD_PAL57_R04_0_Pos) /*!< LCD PAL57: R04_0 Mask */
+#define LCD_PAL57_G04_0_Pos 5 /*!< LCD PAL57: G04_0 Position */
+#define LCD_PAL57_G04_0_Msk (0x1fUL << LCD_PAL57_G04_0_Pos) /*!< LCD PAL57: G04_0 Mask */
+#define LCD_PAL57_B04_0_Pos 10 /*!< LCD PAL57: B04_0 Position */
+#define LCD_PAL57_B04_0_Msk (0x1fUL << LCD_PAL57_B04_0_Pos) /*!< LCD PAL57: B04_0 Mask */
+#define LCD_PAL57_I0_Pos 15 /*!< LCD PAL57: I0 Position */
+#define LCD_PAL57_I0_Msk (0x01UL << LCD_PAL57_I0_Pos) /*!< LCD PAL57: I0 Mask */
+#define LCD_PAL57_R14_0_Pos 16 /*!< LCD PAL57: R14_0 Position */
+#define LCD_PAL57_R14_0_Msk (0x1fUL << LCD_PAL57_R14_0_Pos) /*!< LCD PAL57: R14_0 Mask */
+#define LCD_PAL57_G14_0_Pos 21 /*!< LCD PAL57: G14_0 Position */
+#define LCD_PAL57_G14_0_Msk (0x1fUL << LCD_PAL57_G14_0_Pos) /*!< LCD PAL57: G14_0 Mask */
+#define LCD_PAL57_B14_0_Pos 26 /*!< LCD PAL57: B14_0 Position */
+#define LCD_PAL57_B14_0_Msk (0x1fUL << LCD_PAL57_B14_0_Pos) /*!< LCD PAL57: B14_0 Mask */
+#define LCD_PAL57_I1_Pos 31 /*!< LCD PAL57: I1 Position */
+#define LCD_PAL57_I1_Msk (0x01UL << LCD_PAL57_I1_Pos) /*!< LCD PAL57: I1 Mask */
+
+// ---------------------------------------- LCD_PAL58 -------------------------------------------
+#define LCD_PAL58_R04_0_Pos 0 /*!< LCD PAL58: R04_0 Position */
+#define LCD_PAL58_R04_0_Msk (0x1fUL << LCD_PAL58_R04_0_Pos) /*!< LCD PAL58: R04_0 Mask */
+#define LCD_PAL58_G04_0_Pos 5 /*!< LCD PAL58: G04_0 Position */
+#define LCD_PAL58_G04_0_Msk (0x1fUL << LCD_PAL58_G04_0_Pos) /*!< LCD PAL58: G04_0 Mask */
+#define LCD_PAL58_B04_0_Pos 10 /*!< LCD PAL58: B04_0 Position */
+#define LCD_PAL58_B04_0_Msk (0x1fUL << LCD_PAL58_B04_0_Pos) /*!< LCD PAL58: B04_0 Mask */
+#define LCD_PAL58_I0_Pos 15 /*!< LCD PAL58: I0 Position */
+#define LCD_PAL58_I0_Msk (0x01UL << LCD_PAL58_I0_Pos) /*!< LCD PAL58: I0 Mask */
+#define LCD_PAL58_R14_0_Pos 16 /*!< LCD PAL58: R14_0 Position */
+#define LCD_PAL58_R14_0_Msk (0x1fUL << LCD_PAL58_R14_0_Pos) /*!< LCD PAL58: R14_0 Mask */
+#define LCD_PAL58_G14_0_Pos 21 /*!< LCD PAL58: G14_0 Position */
+#define LCD_PAL58_G14_0_Msk (0x1fUL << LCD_PAL58_G14_0_Pos) /*!< LCD PAL58: G14_0 Mask */
+#define LCD_PAL58_B14_0_Pos 26 /*!< LCD PAL58: B14_0 Position */
+#define LCD_PAL58_B14_0_Msk (0x1fUL << LCD_PAL58_B14_0_Pos) /*!< LCD PAL58: B14_0 Mask */
+#define LCD_PAL58_I1_Pos 31 /*!< LCD PAL58: I1 Position */
+#define LCD_PAL58_I1_Msk (0x01UL << LCD_PAL58_I1_Pos) /*!< LCD PAL58: I1 Mask */
+
+// ---------------------------------------- LCD_PAL59 -------------------------------------------
+#define LCD_PAL59_R04_0_Pos 0 /*!< LCD PAL59: R04_0 Position */
+#define LCD_PAL59_R04_0_Msk (0x1fUL << LCD_PAL59_R04_0_Pos) /*!< LCD PAL59: R04_0 Mask */
+#define LCD_PAL59_G04_0_Pos 5 /*!< LCD PAL59: G04_0 Position */
+#define LCD_PAL59_G04_0_Msk (0x1fUL << LCD_PAL59_G04_0_Pos) /*!< LCD PAL59: G04_0 Mask */
+#define LCD_PAL59_B04_0_Pos 10 /*!< LCD PAL59: B04_0 Position */
+#define LCD_PAL59_B04_0_Msk (0x1fUL << LCD_PAL59_B04_0_Pos) /*!< LCD PAL59: B04_0 Mask */
+#define LCD_PAL59_I0_Pos 15 /*!< LCD PAL59: I0 Position */
+#define LCD_PAL59_I0_Msk (0x01UL << LCD_PAL59_I0_Pos) /*!< LCD PAL59: I0 Mask */
+#define LCD_PAL59_R14_0_Pos 16 /*!< LCD PAL59: R14_0 Position */
+#define LCD_PAL59_R14_0_Msk (0x1fUL << LCD_PAL59_R14_0_Pos) /*!< LCD PAL59: R14_0 Mask */
+#define LCD_PAL59_G14_0_Pos 21 /*!< LCD PAL59: G14_0 Position */
+#define LCD_PAL59_G14_0_Msk (0x1fUL << LCD_PAL59_G14_0_Pos) /*!< LCD PAL59: G14_0 Mask */
+#define LCD_PAL59_B14_0_Pos 26 /*!< LCD PAL59: B14_0 Position */
+#define LCD_PAL59_B14_0_Msk (0x1fUL << LCD_PAL59_B14_0_Pos) /*!< LCD PAL59: B14_0 Mask */
+#define LCD_PAL59_I1_Pos 31 /*!< LCD PAL59: I1 Position */
+#define LCD_PAL59_I1_Msk (0x01UL << LCD_PAL59_I1_Pos) /*!< LCD PAL59: I1 Mask */
+
+// ---------------------------------------- LCD_PAL60 -------------------------------------------
+#define LCD_PAL60_R04_0_Pos 0 /*!< LCD PAL60: R04_0 Position */
+#define LCD_PAL60_R04_0_Msk (0x1fUL << LCD_PAL60_R04_0_Pos) /*!< LCD PAL60: R04_0 Mask */
+#define LCD_PAL60_G04_0_Pos 5 /*!< LCD PAL60: G04_0 Position */
+#define LCD_PAL60_G04_0_Msk (0x1fUL << LCD_PAL60_G04_0_Pos) /*!< LCD PAL60: G04_0 Mask */
+#define LCD_PAL60_B04_0_Pos 10 /*!< LCD PAL60: B04_0 Position */
+#define LCD_PAL60_B04_0_Msk (0x1fUL << LCD_PAL60_B04_0_Pos) /*!< LCD PAL60: B04_0 Mask */
+#define LCD_PAL60_I0_Pos 15 /*!< LCD PAL60: I0 Position */
+#define LCD_PAL60_I0_Msk (0x01UL << LCD_PAL60_I0_Pos) /*!< LCD PAL60: I0 Mask */
+#define LCD_PAL60_R14_0_Pos 16 /*!< LCD PAL60: R14_0 Position */
+#define LCD_PAL60_R14_0_Msk (0x1fUL << LCD_PAL60_R14_0_Pos) /*!< LCD PAL60: R14_0 Mask */
+#define LCD_PAL60_G14_0_Pos 21 /*!< LCD PAL60: G14_0 Position */
+#define LCD_PAL60_G14_0_Msk (0x1fUL << LCD_PAL60_G14_0_Pos) /*!< LCD PAL60: G14_0 Mask */
+#define LCD_PAL60_B14_0_Pos 26 /*!< LCD PAL60: B14_0 Position */
+#define LCD_PAL60_B14_0_Msk (0x1fUL << LCD_PAL60_B14_0_Pos) /*!< LCD PAL60: B14_0 Mask */
+#define LCD_PAL60_I1_Pos 31 /*!< LCD PAL60: I1 Position */
+#define LCD_PAL60_I1_Msk (0x01UL << LCD_PAL60_I1_Pos) /*!< LCD PAL60: I1 Mask */
+
+// ---------------------------------------- LCD_PAL61 -------------------------------------------
+#define LCD_PAL61_R04_0_Pos 0 /*!< LCD PAL61: R04_0 Position */
+#define LCD_PAL61_R04_0_Msk (0x1fUL << LCD_PAL61_R04_0_Pos) /*!< LCD PAL61: R04_0 Mask */
+#define LCD_PAL61_G04_0_Pos 5 /*!< LCD PAL61: G04_0 Position */
+#define LCD_PAL61_G04_0_Msk (0x1fUL << LCD_PAL61_G04_0_Pos) /*!< LCD PAL61: G04_0 Mask */
+#define LCD_PAL61_B04_0_Pos 10 /*!< LCD PAL61: B04_0 Position */
+#define LCD_PAL61_B04_0_Msk (0x1fUL << LCD_PAL61_B04_0_Pos) /*!< LCD PAL61: B04_0 Mask */
+#define LCD_PAL61_I0_Pos 15 /*!< LCD PAL61: I0 Position */
+#define LCD_PAL61_I0_Msk (0x01UL << LCD_PAL61_I0_Pos) /*!< LCD PAL61: I0 Mask */
+#define LCD_PAL61_R14_0_Pos 16 /*!< LCD PAL61: R14_0 Position */
+#define LCD_PAL61_R14_0_Msk (0x1fUL << LCD_PAL61_R14_0_Pos) /*!< LCD PAL61: R14_0 Mask */
+#define LCD_PAL61_G14_0_Pos 21 /*!< LCD PAL61: G14_0 Position */
+#define LCD_PAL61_G14_0_Msk (0x1fUL << LCD_PAL61_G14_0_Pos) /*!< LCD PAL61: G14_0 Mask */
+#define LCD_PAL61_B14_0_Pos 26 /*!< LCD PAL61: B14_0 Position */
+#define LCD_PAL61_B14_0_Msk (0x1fUL << LCD_PAL61_B14_0_Pos) /*!< LCD PAL61: B14_0 Mask */
+#define LCD_PAL61_I1_Pos 31 /*!< LCD PAL61: I1 Position */
+#define LCD_PAL61_I1_Msk (0x01UL << LCD_PAL61_I1_Pos) /*!< LCD PAL61: I1 Mask */
+
+// ---------------------------------------- LCD_PAL62 -------------------------------------------
+#define LCD_PAL62_R04_0_Pos 0 /*!< LCD PAL62: R04_0 Position */
+#define LCD_PAL62_R04_0_Msk (0x1fUL << LCD_PAL62_R04_0_Pos) /*!< LCD PAL62: R04_0 Mask */
+#define LCD_PAL62_G04_0_Pos 5 /*!< LCD PAL62: G04_0 Position */
+#define LCD_PAL62_G04_0_Msk (0x1fUL << LCD_PAL62_G04_0_Pos) /*!< LCD PAL62: G04_0 Mask */
+#define LCD_PAL62_B04_0_Pos 10 /*!< LCD PAL62: B04_0 Position */
+#define LCD_PAL62_B04_0_Msk (0x1fUL << LCD_PAL62_B04_0_Pos) /*!< LCD PAL62: B04_0 Mask */
+#define LCD_PAL62_I0_Pos 15 /*!< LCD PAL62: I0 Position */
+#define LCD_PAL62_I0_Msk (0x01UL << LCD_PAL62_I0_Pos) /*!< LCD PAL62: I0 Mask */
+#define LCD_PAL62_R14_0_Pos 16 /*!< LCD PAL62: R14_0 Position */
+#define LCD_PAL62_R14_0_Msk (0x1fUL << LCD_PAL62_R14_0_Pos) /*!< LCD PAL62: R14_0 Mask */
+#define LCD_PAL62_G14_0_Pos 21 /*!< LCD PAL62: G14_0 Position */
+#define LCD_PAL62_G14_0_Msk (0x1fUL << LCD_PAL62_G14_0_Pos) /*!< LCD PAL62: G14_0 Mask */
+#define LCD_PAL62_B14_0_Pos 26 /*!< LCD PAL62: B14_0 Position */
+#define LCD_PAL62_B14_0_Msk (0x1fUL << LCD_PAL62_B14_0_Pos) /*!< LCD PAL62: B14_0 Mask */
+#define LCD_PAL62_I1_Pos 31 /*!< LCD PAL62: I1 Position */
+#define LCD_PAL62_I1_Msk (0x01UL << LCD_PAL62_I1_Pos) /*!< LCD PAL62: I1 Mask */
+
+// ---------------------------------------- LCD_PAL63 -------------------------------------------
+#define LCD_PAL63_R04_0_Pos 0 /*!< LCD PAL63: R04_0 Position */
+#define LCD_PAL63_R04_0_Msk (0x1fUL << LCD_PAL63_R04_0_Pos) /*!< LCD PAL63: R04_0 Mask */
+#define LCD_PAL63_G04_0_Pos 5 /*!< LCD PAL63: G04_0 Position */
+#define LCD_PAL63_G04_0_Msk (0x1fUL << LCD_PAL63_G04_0_Pos) /*!< LCD PAL63: G04_0 Mask */
+#define LCD_PAL63_B04_0_Pos 10 /*!< LCD PAL63: B04_0 Position */
+#define LCD_PAL63_B04_0_Msk (0x1fUL << LCD_PAL63_B04_0_Pos) /*!< LCD PAL63: B04_0 Mask */
+#define LCD_PAL63_I0_Pos 15 /*!< LCD PAL63: I0 Position */
+#define LCD_PAL63_I0_Msk (0x01UL << LCD_PAL63_I0_Pos) /*!< LCD PAL63: I0 Mask */
+#define LCD_PAL63_R14_0_Pos 16 /*!< LCD PAL63: R14_0 Position */
+#define LCD_PAL63_R14_0_Msk (0x1fUL << LCD_PAL63_R14_0_Pos) /*!< LCD PAL63: R14_0 Mask */
+#define LCD_PAL63_G14_0_Pos 21 /*!< LCD PAL63: G14_0 Position */
+#define LCD_PAL63_G14_0_Msk (0x1fUL << LCD_PAL63_G14_0_Pos) /*!< LCD PAL63: G14_0 Mask */
+#define LCD_PAL63_B14_0_Pos 26 /*!< LCD PAL63: B14_0 Position */
+#define LCD_PAL63_B14_0_Msk (0x1fUL << LCD_PAL63_B14_0_Pos) /*!< LCD PAL63: B14_0 Mask */
+#define LCD_PAL63_I1_Pos 31 /*!< LCD PAL63: I1 Position */
+#define LCD_PAL63_I1_Msk (0x01UL << LCD_PAL63_I1_Pos) /*!< LCD PAL63: I1 Mask */
+
+// ---------------------------------------- LCD_PAL64 -------------------------------------------
+#define LCD_PAL64_R04_0_Pos 0 /*!< LCD PAL64: R04_0 Position */
+#define LCD_PAL64_R04_0_Msk (0x1fUL << LCD_PAL64_R04_0_Pos) /*!< LCD PAL64: R04_0 Mask */
+#define LCD_PAL64_G04_0_Pos 5 /*!< LCD PAL64: G04_0 Position */
+#define LCD_PAL64_G04_0_Msk (0x1fUL << LCD_PAL64_G04_0_Pos) /*!< LCD PAL64: G04_0 Mask */
+#define LCD_PAL64_B04_0_Pos 10 /*!< LCD PAL64: B04_0 Position */
+#define LCD_PAL64_B04_0_Msk (0x1fUL << LCD_PAL64_B04_0_Pos) /*!< LCD PAL64: B04_0 Mask */
+#define LCD_PAL64_I0_Pos 15 /*!< LCD PAL64: I0 Position */
+#define LCD_PAL64_I0_Msk (0x01UL << LCD_PAL64_I0_Pos) /*!< LCD PAL64: I0 Mask */
+#define LCD_PAL64_R14_0_Pos 16 /*!< LCD PAL64: R14_0 Position */
+#define LCD_PAL64_R14_0_Msk (0x1fUL << LCD_PAL64_R14_0_Pos) /*!< LCD PAL64: R14_0 Mask */
+#define LCD_PAL64_G14_0_Pos 21 /*!< LCD PAL64: G14_0 Position */
+#define LCD_PAL64_G14_0_Msk (0x1fUL << LCD_PAL64_G14_0_Pos) /*!< LCD PAL64: G14_0 Mask */
+#define LCD_PAL64_B14_0_Pos 26 /*!< LCD PAL64: B14_0 Position */
+#define LCD_PAL64_B14_0_Msk (0x1fUL << LCD_PAL64_B14_0_Pos) /*!< LCD PAL64: B14_0 Mask */
+#define LCD_PAL64_I1_Pos 31 /*!< LCD PAL64: I1 Position */
+#define LCD_PAL64_I1_Msk (0x01UL << LCD_PAL64_I1_Pos) /*!< LCD PAL64: I1 Mask */
+
+// ---------------------------------------- LCD_PAL65 -------------------------------------------
+#define LCD_PAL65_R04_0_Pos 0 /*!< LCD PAL65: R04_0 Position */
+#define LCD_PAL65_R04_0_Msk (0x1fUL << LCD_PAL65_R04_0_Pos) /*!< LCD PAL65: R04_0 Mask */
+#define LCD_PAL65_G04_0_Pos 5 /*!< LCD PAL65: G04_0 Position */
+#define LCD_PAL65_G04_0_Msk (0x1fUL << LCD_PAL65_G04_0_Pos) /*!< LCD PAL65: G04_0 Mask */
+#define LCD_PAL65_B04_0_Pos 10 /*!< LCD PAL65: B04_0 Position */
+#define LCD_PAL65_B04_0_Msk (0x1fUL << LCD_PAL65_B04_0_Pos) /*!< LCD PAL65: B04_0 Mask */
+#define LCD_PAL65_I0_Pos 15 /*!< LCD PAL65: I0 Position */
+#define LCD_PAL65_I0_Msk (0x01UL << LCD_PAL65_I0_Pos) /*!< LCD PAL65: I0 Mask */
+#define LCD_PAL65_R14_0_Pos 16 /*!< LCD PAL65: R14_0 Position */
+#define LCD_PAL65_R14_0_Msk (0x1fUL << LCD_PAL65_R14_0_Pos) /*!< LCD PAL65: R14_0 Mask */
+#define LCD_PAL65_G14_0_Pos 21 /*!< LCD PAL65: G14_0 Position */
+#define LCD_PAL65_G14_0_Msk (0x1fUL << LCD_PAL65_G14_0_Pos) /*!< LCD PAL65: G14_0 Mask */
+#define LCD_PAL65_B14_0_Pos 26 /*!< LCD PAL65: B14_0 Position */
+#define LCD_PAL65_B14_0_Msk (0x1fUL << LCD_PAL65_B14_0_Pos) /*!< LCD PAL65: B14_0 Mask */
+#define LCD_PAL65_I1_Pos 31 /*!< LCD PAL65: I1 Position */
+#define LCD_PAL65_I1_Msk (0x01UL << LCD_PAL65_I1_Pos) /*!< LCD PAL65: I1 Mask */
+
+// ---------------------------------------- LCD_PAL66 -------------------------------------------
+#define LCD_PAL66_R04_0_Pos 0 /*!< LCD PAL66: R04_0 Position */
+#define LCD_PAL66_R04_0_Msk (0x1fUL << LCD_PAL66_R04_0_Pos) /*!< LCD PAL66: R04_0 Mask */
+#define LCD_PAL66_G04_0_Pos 5 /*!< LCD PAL66: G04_0 Position */
+#define LCD_PAL66_G04_0_Msk (0x1fUL << LCD_PAL66_G04_0_Pos) /*!< LCD PAL66: G04_0 Mask */
+#define LCD_PAL66_B04_0_Pos 10 /*!< LCD PAL66: B04_0 Position */
+#define LCD_PAL66_B04_0_Msk (0x1fUL << LCD_PAL66_B04_0_Pos) /*!< LCD PAL66: B04_0 Mask */
+#define LCD_PAL66_I0_Pos 15 /*!< LCD PAL66: I0 Position */
+#define LCD_PAL66_I0_Msk (0x01UL << LCD_PAL66_I0_Pos) /*!< LCD PAL66: I0 Mask */
+#define LCD_PAL66_R14_0_Pos 16 /*!< LCD PAL66: R14_0 Position */
+#define LCD_PAL66_R14_0_Msk (0x1fUL << LCD_PAL66_R14_0_Pos) /*!< LCD PAL66: R14_0 Mask */
+#define LCD_PAL66_G14_0_Pos 21 /*!< LCD PAL66: G14_0 Position */
+#define LCD_PAL66_G14_0_Msk (0x1fUL << LCD_PAL66_G14_0_Pos) /*!< LCD PAL66: G14_0 Mask */
+#define LCD_PAL66_B14_0_Pos 26 /*!< LCD PAL66: B14_0 Position */
+#define LCD_PAL66_B14_0_Msk (0x1fUL << LCD_PAL66_B14_0_Pos) /*!< LCD PAL66: B14_0 Mask */
+#define LCD_PAL66_I1_Pos 31 /*!< LCD PAL66: I1 Position */
+#define LCD_PAL66_I1_Msk (0x01UL << LCD_PAL66_I1_Pos) /*!< LCD PAL66: I1 Mask */
+
+// ---------------------------------------- LCD_PAL67 -------------------------------------------
+#define LCD_PAL67_R04_0_Pos 0 /*!< LCD PAL67: R04_0 Position */
+#define LCD_PAL67_R04_0_Msk (0x1fUL << LCD_PAL67_R04_0_Pos) /*!< LCD PAL67: R04_0 Mask */
+#define LCD_PAL67_G04_0_Pos 5 /*!< LCD PAL67: G04_0 Position */
+#define LCD_PAL67_G04_0_Msk (0x1fUL << LCD_PAL67_G04_0_Pos) /*!< LCD PAL67: G04_0 Mask */
+#define LCD_PAL67_B04_0_Pos 10 /*!< LCD PAL67: B04_0 Position */
+#define LCD_PAL67_B04_0_Msk (0x1fUL << LCD_PAL67_B04_0_Pos) /*!< LCD PAL67: B04_0 Mask */
+#define LCD_PAL67_I0_Pos 15 /*!< LCD PAL67: I0 Position */
+#define LCD_PAL67_I0_Msk (0x01UL << LCD_PAL67_I0_Pos) /*!< LCD PAL67: I0 Mask */
+#define LCD_PAL67_R14_0_Pos 16 /*!< LCD PAL67: R14_0 Position */
+#define LCD_PAL67_R14_0_Msk (0x1fUL << LCD_PAL67_R14_0_Pos) /*!< LCD PAL67: R14_0 Mask */
+#define LCD_PAL67_G14_0_Pos 21 /*!< LCD PAL67: G14_0 Position */
+#define LCD_PAL67_G14_0_Msk (0x1fUL << LCD_PAL67_G14_0_Pos) /*!< LCD PAL67: G14_0 Mask */
+#define LCD_PAL67_B14_0_Pos 26 /*!< LCD PAL67: B14_0 Position */
+#define LCD_PAL67_B14_0_Msk (0x1fUL << LCD_PAL67_B14_0_Pos) /*!< LCD PAL67: B14_0 Mask */
+#define LCD_PAL67_I1_Pos 31 /*!< LCD PAL67: I1 Position */
+#define LCD_PAL67_I1_Msk (0x01UL << LCD_PAL67_I1_Pos) /*!< LCD PAL67: I1 Mask */
+
+// ---------------------------------------- LCD_PAL68 -------------------------------------------
+#define LCD_PAL68_R04_0_Pos 0 /*!< LCD PAL68: R04_0 Position */
+#define LCD_PAL68_R04_0_Msk (0x1fUL << LCD_PAL68_R04_0_Pos) /*!< LCD PAL68: R04_0 Mask */
+#define LCD_PAL68_G04_0_Pos 5 /*!< LCD PAL68: G04_0 Position */
+#define LCD_PAL68_G04_0_Msk (0x1fUL << LCD_PAL68_G04_0_Pos) /*!< LCD PAL68: G04_0 Mask */
+#define LCD_PAL68_B04_0_Pos 10 /*!< LCD PAL68: B04_0 Position */
+#define LCD_PAL68_B04_0_Msk (0x1fUL << LCD_PAL68_B04_0_Pos) /*!< LCD PAL68: B04_0 Mask */
+#define LCD_PAL68_I0_Pos 15 /*!< LCD PAL68: I0 Position */
+#define LCD_PAL68_I0_Msk (0x01UL << LCD_PAL68_I0_Pos) /*!< LCD PAL68: I0 Mask */
+#define LCD_PAL68_R14_0_Pos 16 /*!< LCD PAL68: R14_0 Position */
+#define LCD_PAL68_R14_0_Msk (0x1fUL << LCD_PAL68_R14_0_Pos) /*!< LCD PAL68: R14_0 Mask */
+#define LCD_PAL68_G14_0_Pos 21 /*!< LCD PAL68: G14_0 Position */
+#define LCD_PAL68_G14_0_Msk (0x1fUL << LCD_PAL68_G14_0_Pos) /*!< LCD PAL68: G14_0 Mask */
+#define LCD_PAL68_B14_0_Pos 26 /*!< LCD PAL68: B14_0 Position */
+#define LCD_PAL68_B14_0_Msk (0x1fUL << LCD_PAL68_B14_0_Pos) /*!< LCD PAL68: B14_0 Mask */
+#define LCD_PAL68_I1_Pos 31 /*!< LCD PAL68: I1 Position */
+#define LCD_PAL68_I1_Msk (0x01UL << LCD_PAL68_I1_Pos) /*!< LCD PAL68: I1 Mask */
+
+// ---------------------------------------- LCD_PAL69 -------------------------------------------
+#define LCD_PAL69_R04_0_Pos 0 /*!< LCD PAL69: R04_0 Position */
+#define LCD_PAL69_R04_0_Msk (0x1fUL << LCD_PAL69_R04_0_Pos) /*!< LCD PAL69: R04_0 Mask */
+#define LCD_PAL69_G04_0_Pos 5 /*!< LCD PAL69: G04_0 Position */
+#define LCD_PAL69_G04_0_Msk (0x1fUL << LCD_PAL69_G04_0_Pos) /*!< LCD PAL69: G04_0 Mask */
+#define LCD_PAL69_B04_0_Pos 10 /*!< LCD PAL69: B04_0 Position */
+#define LCD_PAL69_B04_0_Msk (0x1fUL << LCD_PAL69_B04_0_Pos) /*!< LCD PAL69: B04_0 Mask */
+#define LCD_PAL69_I0_Pos 15 /*!< LCD PAL69: I0 Position */
+#define LCD_PAL69_I0_Msk (0x01UL << LCD_PAL69_I0_Pos) /*!< LCD PAL69: I0 Mask */
+#define LCD_PAL69_R14_0_Pos 16 /*!< LCD PAL69: R14_0 Position */
+#define LCD_PAL69_R14_0_Msk (0x1fUL << LCD_PAL69_R14_0_Pos) /*!< LCD PAL69: R14_0 Mask */
+#define LCD_PAL69_G14_0_Pos 21 /*!< LCD PAL69: G14_0 Position */
+#define LCD_PAL69_G14_0_Msk (0x1fUL << LCD_PAL69_G14_0_Pos) /*!< LCD PAL69: G14_0 Mask */
+#define LCD_PAL69_B14_0_Pos 26 /*!< LCD PAL69: B14_0 Position */
+#define LCD_PAL69_B14_0_Msk (0x1fUL << LCD_PAL69_B14_0_Pos) /*!< LCD PAL69: B14_0 Mask */
+#define LCD_PAL69_I1_Pos 31 /*!< LCD PAL69: I1 Position */
+#define LCD_PAL69_I1_Msk (0x01UL << LCD_PAL69_I1_Pos) /*!< LCD PAL69: I1 Mask */
+
+// ---------------------------------------- LCD_PAL70 -------------------------------------------
+#define LCD_PAL70_R04_0_Pos 0 /*!< LCD PAL70: R04_0 Position */
+#define LCD_PAL70_R04_0_Msk (0x1fUL << LCD_PAL70_R04_0_Pos) /*!< LCD PAL70: R04_0 Mask */
+#define LCD_PAL70_G04_0_Pos 5 /*!< LCD PAL70: G04_0 Position */
+#define LCD_PAL70_G04_0_Msk (0x1fUL << LCD_PAL70_G04_0_Pos) /*!< LCD PAL70: G04_0 Mask */
+#define LCD_PAL70_B04_0_Pos 10 /*!< LCD PAL70: B04_0 Position */
+#define LCD_PAL70_B04_0_Msk (0x1fUL << LCD_PAL70_B04_0_Pos) /*!< LCD PAL70: B04_0 Mask */
+#define LCD_PAL70_I0_Pos 15 /*!< LCD PAL70: I0 Position */
+#define LCD_PAL70_I0_Msk (0x01UL << LCD_PAL70_I0_Pos) /*!< LCD PAL70: I0 Mask */
+#define LCD_PAL70_R14_0_Pos 16 /*!< LCD PAL70: R14_0 Position */
+#define LCD_PAL70_R14_0_Msk (0x1fUL << LCD_PAL70_R14_0_Pos) /*!< LCD PAL70: R14_0 Mask */
+#define LCD_PAL70_G14_0_Pos 21 /*!< LCD PAL70: G14_0 Position */
+#define LCD_PAL70_G14_0_Msk (0x1fUL << LCD_PAL70_G14_0_Pos) /*!< LCD PAL70: G14_0 Mask */
+#define LCD_PAL70_B14_0_Pos 26 /*!< LCD PAL70: B14_0 Position */
+#define LCD_PAL70_B14_0_Msk (0x1fUL << LCD_PAL70_B14_0_Pos) /*!< LCD PAL70: B14_0 Mask */
+#define LCD_PAL70_I1_Pos 31 /*!< LCD PAL70: I1 Position */
+#define LCD_PAL70_I1_Msk (0x01UL << LCD_PAL70_I1_Pos) /*!< LCD PAL70: I1 Mask */
+
+// ---------------------------------------- LCD_PAL71 -------------------------------------------
+#define LCD_PAL71_R04_0_Pos 0 /*!< LCD PAL71: R04_0 Position */
+#define LCD_PAL71_R04_0_Msk (0x1fUL << LCD_PAL71_R04_0_Pos) /*!< LCD PAL71: R04_0 Mask */
+#define LCD_PAL71_G04_0_Pos 5 /*!< LCD PAL71: G04_0 Position */
+#define LCD_PAL71_G04_0_Msk (0x1fUL << LCD_PAL71_G04_0_Pos) /*!< LCD PAL71: G04_0 Mask */
+#define LCD_PAL71_B04_0_Pos 10 /*!< LCD PAL71: B04_0 Position */
+#define LCD_PAL71_B04_0_Msk (0x1fUL << LCD_PAL71_B04_0_Pos) /*!< LCD PAL71: B04_0 Mask */
+#define LCD_PAL71_I0_Pos 15 /*!< LCD PAL71: I0 Position */
+#define LCD_PAL71_I0_Msk (0x01UL << LCD_PAL71_I0_Pos) /*!< LCD PAL71: I0 Mask */
+#define LCD_PAL71_R14_0_Pos 16 /*!< LCD PAL71: R14_0 Position */
+#define LCD_PAL71_R14_0_Msk (0x1fUL << LCD_PAL71_R14_0_Pos) /*!< LCD PAL71: R14_0 Mask */
+#define LCD_PAL71_G14_0_Pos 21 /*!< LCD PAL71: G14_0 Position */
+#define LCD_PAL71_G14_0_Msk (0x1fUL << LCD_PAL71_G14_0_Pos) /*!< LCD PAL71: G14_0 Mask */
+#define LCD_PAL71_B14_0_Pos 26 /*!< LCD PAL71: B14_0 Position */
+#define LCD_PAL71_B14_0_Msk (0x1fUL << LCD_PAL71_B14_0_Pos) /*!< LCD PAL71: B14_0 Mask */
+#define LCD_PAL71_I1_Pos 31 /*!< LCD PAL71: I1 Position */
+#define LCD_PAL71_I1_Msk (0x01UL << LCD_PAL71_I1_Pos) /*!< LCD PAL71: I1 Mask */
+
+// ---------------------------------------- LCD_PAL72 -------------------------------------------
+#define LCD_PAL72_R04_0_Pos 0 /*!< LCD PAL72: R04_0 Position */
+#define LCD_PAL72_R04_0_Msk (0x1fUL << LCD_PAL72_R04_0_Pos) /*!< LCD PAL72: R04_0 Mask */
+#define LCD_PAL72_G04_0_Pos 5 /*!< LCD PAL72: G04_0 Position */
+#define LCD_PAL72_G04_0_Msk (0x1fUL << LCD_PAL72_G04_0_Pos) /*!< LCD PAL72: G04_0 Mask */
+#define LCD_PAL72_B04_0_Pos 10 /*!< LCD PAL72: B04_0 Position */
+#define LCD_PAL72_B04_0_Msk (0x1fUL << LCD_PAL72_B04_0_Pos) /*!< LCD PAL72: B04_0 Mask */
+#define LCD_PAL72_I0_Pos 15 /*!< LCD PAL72: I0 Position */
+#define LCD_PAL72_I0_Msk (0x01UL << LCD_PAL72_I0_Pos) /*!< LCD PAL72: I0 Mask */
+#define LCD_PAL72_R14_0_Pos 16 /*!< LCD PAL72: R14_0 Position */
+#define LCD_PAL72_R14_0_Msk (0x1fUL << LCD_PAL72_R14_0_Pos) /*!< LCD PAL72: R14_0 Mask */
+#define LCD_PAL72_G14_0_Pos 21 /*!< LCD PAL72: G14_0 Position */
+#define LCD_PAL72_G14_0_Msk (0x1fUL << LCD_PAL72_G14_0_Pos) /*!< LCD PAL72: G14_0 Mask */
+#define LCD_PAL72_B14_0_Pos 26 /*!< LCD PAL72: B14_0 Position */
+#define LCD_PAL72_B14_0_Msk (0x1fUL << LCD_PAL72_B14_0_Pos) /*!< LCD PAL72: B14_0 Mask */
+#define LCD_PAL72_I1_Pos 31 /*!< LCD PAL72: I1 Position */
+#define LCD_PAL72_I1_Msk (0x01UL << LCD_PAL72_I1_Pos) /*!< LCD PAL72: I1 Mask */
+
+// ---------------------------------------- LCD_PAL73 -------------------------------------------
+#define LCD_PAL73_R04_0_Pos 0 /*!< LCD PAL73: R04_0 Position */
+#define LCD_PAL73_R04_0_Msk (0x1fUL << LCD_PAL73_R04_0_Pos) /*!< LCD PAL73: R04_0 Mask */
+#define LCD_PAL73_G04_0_Pos 5 /*!< LCD PAL73: G04_0 Position */
+#define LCD_PAL73_G04_0_Msk (0x1fUL << LCD_PAL73_G04_0_Pos) /*!< LCD PAL73: G04_0 Mask */
+#define LCD_PAL73_B04_0_Pos 10 /*!< LCD PAL73: B04_0 Position */
+#define LCD_PAL73_B04_0_Msk (0x1fUL << LCD_PAL73_B04_0_Pos) /*!< LCD PAL73: B04_0 Mask */
+#define LCD_PAL73_I0_Pos 15 /*!< LCD PAL73: I0 Position */
+#define LCD_PAL73_I0_Msk (0x01UL << LCD_PAL73_I0_Pos) /*!< LCD PAL73: I0 Mask */
+#define LCD_PAL73_R14_0_Pos 16 /*!< LCD PAL73: R14_0 Position */
+#define LCD_PAL73_R14_0_Msk (0x1fUL << LCD_PAL73_R14_0_Pos) /*!< LCD PAL73: R14_0 Mask */
+#define LCD_PAL73_G14_0_Pos 21 /*!< LCD PAL73: G14_0 Position */
+#define LCD_PAL73_G14_0_Msk (0x1fUL << LCD_PAL73_G14_0_Pos) /*!< LCD PAL73: G14_0 Mask */
+#define LCD_PAL73_B14_0_Pos 26 /*!< LCD PAL73: B14_0 Position */
+#define LCD_PAL73_B14_0_Msk (0x1fUL << LCD_PAL73_B14_0_Pos) /*!< LCD PAL73: B14_0 Mask */
+#define LCD_PAL73_I1_Pos 31 /*!< LCD PAL73: I1 Position */
+#define LCD_PAL73_I1_Msk (0x01UL << LCD_PAL73_I1_Pos) /*!< LCD PAL73: I1 Mask */
+
+// ---------------------------------------- LCD_PAL74 -------------------------------------------
+#define LCD_PAL74_R04_0_Pos 0 /*!< LCD PAL74: R04_0 Position */
+#define LCD_PAL74_R04_0_Msk (0x1fUL << LCD_PAL74_R04_0_Pos) /*!< LCD PAL74: R04_0 Mask */
+#define LCD_PAL74_G04_0_Pos 5 /*!< LCD PAL74: G04_0 Position */
+#define LCD_PAL74_G04_0_Msk (0x1fUL << LCD_PAL74_G04_0_Pos) /*!< LCD PAL74: G04_0 Mask */
+#define LCD_PAL74_B04_0_Pos 10 /*!< LCD PAL74: B04_0 Position */
+#define LCD_PAL74_B04_0_Msk (0x1fUL << LCD_PAL74_B04_0_Pos) /*!< LCD PAL74: B04_0 Mask */
+#define LCD_PAL74_I0_Pos 15 /*!< LCD PAL74: I0 Position */
+#define LCD_PAL74_I0_Msk (0x01UL << LCD_PAL74_I0_Pos) /*!< LCD PAL74: I0 Mask */
+#define LCD_PAL74_R14_0_Pos 16 /*!< LCD PAL74: R14_0 Position */
+#define LCD_PAL74_R14_0_Msk (0x1fUL << LCD_PAL74_R14_0_Pos) /*!< LCD PAL74: R14_0 Mask */
+#define LCD_PAL74_G14_0_Pos 21 /*!< LCD PAL74: G14_0 Position */
+#define LCD_PAL74_G14_0_Msk (0x1fUL << LCD_PAL74_G14_0_Pos) /*!< LCD PAL74: G14_0 Mask */
+#define LCD_PAL74_B14_0_Pos 26 /*!< LCD PAL74: B14_0 Position */
+#define LCD_PAL74_B14_0_Msk (0x1fUL << LCD_PAL74_B14_0_Pos) /*!< LCD PAL74: B14_0 Mask */
+#define LCD_PAL74_I1_Pos 31 /*!< LCD PAL74: I1 Position */
+#define LCD_PAL74_I1_Msk (0x01UL << LCD_PAL74_I1_Pos) /*!< LCD PAL74: I1 Mask */
+
+// ---------------------------------------- LCD_PAL75 -------------------------------------------
+#define LCD_PAL75_R04_0_Pos 0 /*!< LCD PAL75: R04_0 Position */
+#define LCD_PAL75_R04_0_Msk (0x1fUL << LCD_PAL75_R04_0_Pos) /*!< LCD PAL75: R04_0 Mask */
+#define LCD_PAL75_G04_0_Pos 5 /*!< LCD PAL75: G04_0 Position */
+#define LCD_PAL75_G04_0_Msk (0x1fUL << LCD_PAL75_G04_0_Pos) /*!< LCD PAL75: G04_0 Mask */
+#define LCD_PAL75_B04_0_Pos 10 /*!< LCD PAL75: B04_0 Position */
+#define LCD_PAL75_B04_0_Msk (0x1fUL << LCD_PAL75_B04_0_Pos) /*!< LCD PAL75: B04_0 Mask */
+#define LCD_PAL75_I0_Pos 15 /*!< LCD PAL75: I0 Position */
+#define LCD_PAL75_I0_Msk (0x01UL << LCD_PAL75_I0_Pos) /*!< LCD PAL75: I0 Mask */
+#define LCD_PAL75_R14_0_Pos 16 /*!< LCD PAL75: R14_0 Position */
+#define LCD_PAL75_R14_0_Msk (0x1fUL << LCD_PAL75_R14_0_Pos) /*!< LCD PAL75: R14_0 Mask */
+#define LCD_PAL75_G14_0_Pos 21 /*!< LCD PAL75: G14_0 Position */
+#define LCD_PAL75_G14_0_Msk (0x1fUL << LCD_PAL75_G14_0_Pos) /*!< LCD PAL75: G14_0 Mask */
+#define LCD_PAL75_B14_0_Pos 26 /*!< LCD PAL75: B14_0 Position */
+#define LCD_PAL75_B14_0_Msk (0x1fUL << LCD_PAL75_B14_0_Pos) /*!< LCD PAL75: B14_0 Mask */
+#define LCD_PAL75_I1_Pos 31 /*!< LCD PAL75: I1 Position */
+#define LCD_PAL75_I1_Msk (0x01UL << LCD_PAL75_I1_Pos) /*!< LCD PAL75: I1 Mask */
+
+// ---------------------------------------- LCD_PAL76 -------------------------------------------
+#define LCD_PAL76_R04_0_Pos 0 /*!< LCD PAL76: R04_0 Position */
+#define LCD_PAL76_R04_0_Msk (0x1fUL << LCD_PAL76_R04_0_Pos) /*!< LCD PAL76: R04_0 Mask */
+#define LCD_PAL76_G04_0_Pos 5 /*!< LCD PAL76: G04_0 Position */
+#define LCD_PAL76_G04_0_Msk (0x1fUL << LCD_PAL76_G04_0_Pos) /*!< LCD PAL76: G04_0 Mask */
+#define LCD_PAL76_B04_0_Pos 10 /*!< LCD PAL76: B04_0 Position */
+#define LCD_PAL76_B04_0_Msk (0x1fUL << LCD_PAL76_B04_0_Pos) /*!< LCD PAL76: B04_0 Mask */
+#define LCD_PAL76_I0_Pos 15 /*!< LCD PAL76: I0 Position */
+#define LCD_PAL76_I0_Msk (0x01UL << LCD_PAL76_I0_Pos) /*!< LCD PAL76: I0 Mask */
+#define LCD_PAL76_R14_0_Pos 16 /*!< LCD PAL76: R14_0 Position */
+#define LCD_PAL76_R14_0_Msk (0x1fUL << LCD_PAL76_R14_0_Pos) /*!< LCD PAL76: R14_0 Mask */
+#define LCD_PAL76_G14_0_Pos 21 /*!< LCD PAL76: G14_0 Position */
+#define LCD_PAL76_G14_0_Msk (0x1fUL << LCD_PAL76_G14_0_Pos) /*!< LCD PAL76: G14_0 Mask */
+#define LCD_PAL76_B14_0_Pos 26 /*!< LCD PAL76: B14_0 Position */
+#define LCD_PAL76_B14_0_Msk (0x1fUL << LCD_PAL76_B14_0_Pos) /*!< LCD PAL76: B14_0 Mask */
+#define LCD_PAL76_I1_Pos 31 /*!< LCD PAL76: I1 Position */
+#define LCD_PAL76_I1_Msk (0x01UL << LCD_PAL76_I1_Pos) /*!< LCD PAL76: I1 Mask */
+
+// ---------------------------------------- LCD_PAL77 -------------------------------------------
+#define LCD_PAL77_R04_0_Pos 0 /*!< LCD PAL77: R04_0 Position */
+#define LCD_PAL77_R04_0_Msk (0x1fUL << LCD_PAL77_R04_0_Pos) /*!< LCD PAL77: R04_0 Mask */
+#define LCD_PAL77_G04_0_Pos 5 /*!< LCD PAL77: G04_0 Position */
+#define LCD_PAL77_G04_0_Msk (0x1fUL << LCD_PAL77_G04_0_Pos) /*!< LCD PAL77: G04_0 Mask */
+#define LCD_PAL77_B04_0_Pos 10 /*!< LCD PAL77: B04_0 Position */
+#define LCD_PAL77_B04_0_Msk (0x1fUL << LCD_PAL77_B04_0_Pos) /*!< LCD PAL77: B04_0 Mask */
+#define LCD_PAL77_I0_Pos 15 /*!< LCD PAL77: I0 Position */
+#define LCD_PAL77_I0_Msk (0x01UL << LCD_PAL77_I0_Pos) /*!< LCD PAL77: I0 Mask */
+#define LCD_PAL77_R14_0_Pos 16 /*!< LCD PAL77: R14_0 Position */
+#define LCD_PAL77_R14_0_Msk (0x1fUL << LCD_PAL77_R14_0_Pos) /*!< LCD PAL77: R14_0 Mask */
+#define LCD_PAL77_G14_0_Pos 21 /*!< LCD PAL77: G14_0 Position */
+#define LCD_PAL77_G14_0_Msk (0x1fUL << LCD_PAL77_G14_0_Pos) /*!< LCD PAL77: G14_0 Mask */
+#define LCD_PAL77_B14_0_Pos 26 /*!< LCD PAL77: B14_0 Position */
+#define LCD_PAL77_B14_0_Msk (0x1fUL << LCD_PAL77_B14_0_Pos) /*!< LCD PAL77: B14_0 Mask */
+#define LCD_PAL77_I1_Pos 31 /*!< LCD PAL77: I1 Position */
+#define LCD_PAL77_I1_Msk (0x01UL << LCD_PAL77_I1_Pos) /*!< LCD PAL77: I1 Mask */
+
+// ---------------------------------------- LCD_PAL78 -------------------------------------------
+#define LCD_PAL78_R04_0_Pos 0 /*!< LCD PAL78: R04_0 Position */
+#define LCD_PAL78_R04_0_Msk (0x1fUL << LCD_PAL78_R04_0_Pos) /*!< LCD PAL78: R04_0 Mask */
+#define LCD_PAL78_G04_0_Pos 5 /*!< LCD PAL78: G04_0 Position */
+#define LCD_PAL78_G04_0_Msk (0x1fUL << LCD_PAL78_G04_0_Pos) /*!< LCD PAL78: G04_0 Mask */
+#define LCD_PAL78_B04_0_Pos 10 /*!< LCD PAL78: B04_0 Position */
+#define LCD_PAL78_B04_0_Msk (0x1fUL << LCD_PAL78_B04_0_Pos) /*!< LCD PAL78: B04_0 Mask */
+#define LCD_PAL78_I0_Pos 15 /*!< LCD PAL78: I0 Position */
+#define LCD_PAL78_I0_Msk (0x01UL << LCD_PAL78_I0_Pos) /*!< LCD PAL78: I0 Mask */
+#define LCD_PAL78_R14_0_Pos 16 /*!< LCD PAL78: R14_0 Position */
+#define LCD_PAL78_R14_0_Msk (0x1fUL << LCD_PAL78_R14_0_Pos) /*!< LCD PAL78: R14_0 Mask */
+#define LCD_PAL78_G14_0_Pos 21 /*!< LCD PAL78: G14_0 Position */
+#define LCD_PAL78_G14_0_Msk (0x1fUL << LCD_PAL78_G14_0_Pos) /*!< LCD PAL78: G14_0 Mask */
+#define LCD_PAL78_B14_0_Pos 26 /*!< LCD PAL78: B14_0 Position */
+#define LCD_PAL78_B14_0_Msk (0x1fUL << LCD_PAL78_B14_0_Pos) /*!< LCD PAL78: B14_0 Mask */
+#define LCD_PAL78_I1_Pos 31 /*!< LCD PAL78: I1 Position */
+#define LCD_PAL78_I1_Msk (0x01UL << LCD_PAL78_I1_Pos) /*!< LCD PAL78: I1 Mask */
+
+// ---------------------------------------- LCD_PAL79 -------------------------------------------
+#define LCD_PAL79_R04_0_Pos 0 /*!< LCD PAL79: R04_0 Position */
+#define LCD_PAL79_R04_0_Msk (0x1fUL << LCD_PAL79_R04_0_Pos) /*!< LCD PAL79: R04_0 Mask */
+#define LCD_PAL79_G04_0_Pos 5 /*!< LCD PAL79: G04_0 Position */
+#define LCD_PAL79_G04_0_Msk (0x1fUL << LCD_PAL79_G04_0_Pos) /*!< LCD PAL79: G04_0 Mask */
+#define LCD_PAL79_B04_0_Pos 10 /*!< LCD PAL79: B04_0 Position */
+#define LCD_PAL79_B04_0_Msk (0x1fUL << LCD_PAL79_B04_0_Pos) /*!< LCD PAL79: B04_0 Mask */
+#define LCD_PAL79_I0_Pos 15 /*!< LCD PAL79: I0 Position */
+#define LCD_PAL79_I0_Msk (0x01UL << LCD_PAL79_I0_Pos) /*!< LCD PAL79: I0 Mask */
+#define LCD_PAL79_R14_0_Pos 16 /*!< LCD PAL79: R14_0 Position */
+#define LCD_PAL79_R14_0_Msk (0x1fUL << LCD_PAL79_R14_0_Pos) /*!< LCD PAL79: R14_0 Mask */
+#define LCD_PAL79_G14_0_Pos 21 /*!< LCD PAL79: G14_0 Position */
+#define LCD_PAL79_G14_0_Msk (0x1fUL << LCD_PAL79_G14_0_Pos) /*!< LCD PAL79: G14_0 Mask */
+#define LCD_PAL79_B14_0_Pos 26 /*!< LCD PAL79: B14_0 Position */
+#define LCD_PAL79_B14_0_Msk (0x1fUL << LCD_PAL79_B14_0_Pos) /*!< LCD PAL79: B14_0 Mask */
+#define LCD_PAL79_I1_Pos 31 /*!< LCD PAL79: I1 Position */
+#define LCD_PAL79_I1_Msk (0x01UL << LCD_PAL79_I1_Pos) /*!< LCD PAL79: I1 Mask */
+
+// ---------------------------------------- LCD_PAL80 -------------------------------------------
+#define LCD_PAL80_R04_0_Pos 0 /*!< LCD PAL80: R04_0 Position */
+#define LCD_PAL80_R04_0_Msk (0x1fUL << LCD_PAL80_R04_0_Pos) /*!< LCD PAL80: R04_0 Mask */
+#define LCD_PAL80_G04_0_Pos 5 /*!< LCD PAL80: G04_0 Position */
+#define LCD_PAL80_G04_0_Msk (0x1fUL << LCD_PAL80_G04_0_Pos) /*!< LCD PAL80: G04_0 Mask */
+#define LCD_PAL80_B04_0_Pos 10 /*!< LCD PAL80: B04_0 Position */
+#define LCD_PAL80_B04_0_Msk (0x1fUL << LCD_PAL80_B04_0_Pos) /*!< LCD PAL80: B04_0 Mask */
+#define LCD_PAL80_I0_Pos 15 /*!< LCD PAL80: I0 Position */
+#define LCD_PAL80_I0_Msk (0x01UL << LCD_PAL80_I0_Pos) /*!< LCD PAL80: I0 Mask */
+#define LCD_PAL80_R14_0_Pos 16 /*!< LCD PAL80: R14_0 Position */
+#define LCD_PAL80_R14_0_Msk (0x1fUL << LCD_PAL80_R14_0_Pos) /*!< LCD PAL80: R14_0 Mask */
+#define LCD_PAL80_G14_0_Pos 21 /*!< LCD PAL80: G14_0 Position */
+#define LCD_PAL80_G14_0_Msk (0x1fUL << LCD_PAL80_G14_0_Pos) /*!< LCD PAL80: G14_0 Mask */
+#define LCD_PAL80_B14_0_Pos 26 /*!< LCD PAL80: B14_0 Position */
+#define LCD_PAL80_B14_0_Msk (0x1fUL << LCD_PAL80_B14_0_Pos) /*!< LCD PAL80: B14_0 Mask */
+#define LCD_PAL80_I1_Pos 31 /*!< LCD PAL80: I1 Position */
+#define LCD_PAL80_I1_Msk (0x01UL << LCD_PAL80_I1_Pos) /*!< LCD PAL80: I1 Mask */
+
+// ---------------------------------------- LCD_PAL81 -------------------------------------------
+#define LCD_PAL81_R04_0_Pos 0 /*!< LCD PAL81: R04_0 Position */
+#define LCD_PAL81_R04_0_Msk (0x1fUL << LCD_PAL81_R04_0_Pos) /*!< LCD PAL81: R04_0 Mask */
+#define LCD_PAL81_G04_0_Pos 5 /*!< LCD PAL81: G04_0 Position */
+#define LCD_PAL81_G04_0_Msk (0x1fUL << LCD_PAL81_G04_0_Pos) /*!< LCD PAL81: G04_0 Mask */
+#define LCD_PAL81_B04_0_Pos 10 /*!< LCD PAL81: B04_0 Position */
+#define LCD_PAL81_B04_0_Msk (0x1fUL << LCD_PAL81_B04_0_Pos) /*!< LCD PAL81: B04_0 Mask */
+#define LCD_PAL81_I0_Pos 15 /*!< LCD PAL81: I0 Position */
+#define LCD_PAL81_I0_Msk (0x01UL << LCD_PAL81_I0_Pos) /*!< LCD PAL81: I0 Mask */
+#define LCD_PAL81_R14_0_Pos 16 /*!< LCD PAL81: R14_0 Position */
+#define LCD_PAL81_R14_0_Msk (0x1fUL << LCD_PAL81_R14_0_Pos) /*!< LCD PAL81: R14_0 Mask */
+#define LCD_PAL81_G14_0_Pos 21 /*!< LCD PAL81: G14_0 Position */
+#define LCD_PAL81_G14_0_Msk (0x1fUL << LCD_PAL81_G14_0_Pos) /*!< LCD PAL81: G14_0 Mask */
+#define LCD_PAL81_B14_0_Pos 26 /*!< LCD PAL81: B14_0 Position */
+#define LCD_PAL81_B14_0_Msk (0x1fUL << LCD_PAL81_B14_0_Pos) /*!< LCD PAL81: B14_0 Mask */
+#define LCD_PAL81_I1_Pos 31 /*!< LCD PAL81: I1 Position */
+#define LCD_PAL81_I1_Msk (0x01UL << LCD_PAL81_I1_Pos) /*!< LCD PAL81: I1 Mask */
+
+// ---------------------------------------- LCD_PAL82 -------------------------------------------
+#define LCD_PAL82_R04_0_Pos 0 /*!< LCD PAL82: R04_0 Position */
+#define LCD_PAL82_R04_0_Msk (0x1fUL << LCD_PAL82_R04_0_Pos) /*!< LCD PAL82: R04_0 Mask */
+#define LCD_PAL82_G04_0_Pos 5 /*!< LCD PAL82: G04_0 Position */
+#define LCD_PAL82_G04_0_Msk (0x1fUL << LCD_PAL82_G04_0_Pos) /*!< LCD PAL82: G04_0 Mask */
+#define LCD_PAL82_B04_0_Pos 10 /*!< LCD PAL82: B04_0 Position */
+#define LCD_PAL82_B04_0_Msk (0x1fUL << LCD_PAL82_B04_0_Pos) /*!< LCD PAL82: B04_0 Mask */
+#define LCD_PAL82_I0_Pos 15 /*!< LCD PAL82: I0 Position */
+#define LCD_PAL82_I0_Msk (0x01UL << LCD_PAL82_I0_Pos) /*!< LCD PAL82: I0 Mask */
+#define LCD_PAL82_R14_0_Pos 16 /*!< LCD PAL82: R14_0 Position */
+#define LCD_PAL82_R14_0_Msk (0x1fUL << LCD_PAL82_R14_0_Pos) /*!< LCD PAL82: R14_0 Mask */
+#define LCD_PAL82_G14_0_Pos 21 /*!< LCD PAL82: G14_0 Position */
+#define LCD_PAL82_G14_0_Msk (0x1fUL << LCD_PAL82_G14_0_Pos) /*!< LCD PAL82: G14_0 Mask */
+#define LCD_PAL82_B14_0_Pos 26 /*!< LCD PAL82: B14_0 Position */
+#define LCD_PAL82_B14_0_Msk (0x1fUL << LCD_PAL82_B14_0_Pos) /*!< LCD PAL82: B14_0 Mask */
+#define LCD_PAL82_I1_Pos 31 /*!< LCD PAL82: I1 Position */
+#define LCD_PAL82_I1_Msk (0x01UL << LCD_PAL82_I1_Pos) /*!< LCD PAL82: I1 Mask */
+
+// ---------------------------------------- LCD_PAL83 -------------------------------------------
+#define LCD_PAL83_R04_0_Pos 0 /*!< LCD PAL83: R04_0 Position */
+#define LCD_PAL83_R04_0_Msk (0x1fUL << LCD_PAL83_R04_0_Pos) /*!< LCD PAL83: R04_0 Mask */
+#define LCD_PAL83_G04_0_Pos 5 /*!< LCD PAL83: G04_0 Position */
+#define LCD_PAL83_G04_0_Msk (0x1fUL << LCD_PAL83_G04_0_Pos) /*!< LCD PAL83: G04_0 Mask */
+#define LCD_PAL83_B04_0_Pos 10 /*!< LCD PAL83: B04_0 Position */
+#define LCD_PAL83_B04_0_Msk (0x1fUL << LCD_PAL83_B04_0_Pos) /*!< LCD PAL83: B04_0 Mask */
+#define LCD_PAL83_I0_Pos 15 /*!< LCD PAL83: I0 Position */
+#define LCD_PAL83_I0_Msk (0x01UL << LCD_PAL83_I0_Pos) /*!< LCD PAL83: I0 Mask */
+#define LCD_PAL83_R14_0_Pos 16 /*!< LCD PAL83: R14_0 Position */
+#define LCD_PAL83_R14_0_Msk (0x1fUL << LCD_PAL83_R14_0_Pos) /*!< LCD PAL83: R14_0 Mask */
+#define LCD_PAL83_G14_0_Pos 21 /*!< LCD PAL83: G14_0 Position */
+#define LCD_PAL83_G14_0_Msk (0x1fUL << LCD_PAL83_G14_0_Pos) /*!< LCD PAL83: G14_0 Mask */
+#define LCD_PAL83_B14_0_Pos 26 /*!< LCD PAL83: B14_0 Position */
+#define LCD_PAL83_B14_0_Msk (0x1fUL << LCD_PAL83_B14_0_Pos) /*!< LCD PAL83: B14_0 Mask */
+#define LCD_PAL83_I1_Pos 31 /*!< LCD PAL83: I1 Position */
+#define LCD_PAL83_I1_Msk (0x01UL << LCD_PAL83_I1_Pos) /*!< LCD PAL83: I1 Mask */
+
+// ---------------------------------------- LCD_PAL84 -------------------------------------------
+#define LCD_PAL84_R04_0_Pos 0 /*!< LCD PAL84: R04_0 Position */
+#define LCD_PAL84_R04_0_Msk (0x1fUL << LCD_PAL84_R04_0_Pos) /*!< LCD PAL84: R04_0 Mask */
+#define LCD_PAL84_G04_0_Pos 5 /*!< LCD PAL84: G04_0 Position */
+#define LCD_PAL84_G04_0_Msk (0x1fUL << LCD_PAL84_G04_0_Pos) /*!< LCD PAL84: G04_0 Mask */
+#define LCD_PAL84_B04_0_Pos 10 /*!< LCD PAL84: B04_0 Position */
+#define LCD_PAL84_B04_0_Msk (0x1fUL << LCD_PAL84_B04_0_Pos) /*!< LCD PAL84: B04_0 Mask */
+#define LCD_PAL84_I0_Pos 15 /*!< LCD PAL84: I0 Position */
+#define LCD_PAL84_I0_Msk (0x01UL << LCD_PAL84_I0_Pos) /*!< LCD PAL84: I0 Mask */
+#define LCD_PAL84_R14_0_Pos 16 /*!< LCD PAL84: R14_0 Position */
+#define LCD_PAL84_R14_0_Msk (0x1fUL << LCD_PAL84_R14_0_Pos) /*!< LCD PAL84: R14_0 Mask */
+#define LCD_PAL84_G14_0_Pos 21 /*!< LCD PAL84: G14_0 Position */
+#define LCD_PAL84_G14_0_Msk (0x1fUL << LCD_PAL84_G14_0_Pos) /*!< LCD PAL84: G14_0 Mask */
+#define LCD_PAL84_B14_0_Pos 26 /*!< LCD PAL84: B14_0 Position */
+#define LCD_PAL84_B14_0_Msk (0x1fUL << LCD_PAL84_B14_0_Pos) /*!< LCD PAL84: B14_0 Mask */
+#define LCD_PAL84_I1_Pos 31 /*!< LCD PAL84: I1 Position */
+#define LCD_PAL84_I1_Msk (0x01UL << LCD_PAL84_I1_Pos) /*!< LCD PAL84: I1 Mask */
+
+// ---------------------------------------- LCD_PAL85 -------------------------------------------
+#define LCD_PAL85_R04_0_Pos 0 /*!< LCD PAL85: R04_0 Position */
+#define LCD_PAL85_R04_0_Msk (0x1fUL << LCD_PAL85_R04_0_Pos) /*!< LCD PAL85: R04_0 Mask */
+#define LCD_PAL85_G04_0_Pos 5 /*!< LCD PAL85: G04_0 Position */
+#define LCD_PAL85_G04_0_Msk (0x1fUL << LCD_PAL85_G04_0_Pos) /*!< LCD PAL85: G04_0 Mask */
+#define LCD_PAL85_B04_0_Pos 10 /*!< LCD PAL85: B04_0 Position */
+#define LCD_PAL85_B04_0_Msk (0x1fUL << LCD_PAL85_B04_0_Pos) /*!< LCD PAL85: B04_0 Mask */
+#define LCD_PAL85_I0_Pos 15 /*!< LCD PAL85: I0 Position */
+#define LCD_PAL85_I0_Msk (0x01UL << LCD_PAL85_I0_Pos) /*!< LCD PAL85: I0 Mask */
+#define LCD_PAL85_R14_0_Pos 16 /*!< LCD PAL85: R14_0 Position */
+#define LCD_PAL85_R14_0_Msk (0x1fUL << LCD_PAL85_R14_0_Pos) /*!< LCD PAL85: R14_0 Mask */
+#define LCD_PAL85_G14_0_Pos 21 /*!< LCD PAL85: G14_0 Position */
+#define LCD_PAL85_G14_0_Msk (0x1fUL << LCD_PAL85_G14_0_Pos) /*!< LCD PAL85: G14_0 Mask */
+#define LCD_PAL85_B14_0_Pos 26 /*!< LCD PAL85: B14_0 Position */
+#define LCD_PAL85_B14_0_Msk (0x1fUL << LCD_PAL85_B14_0_Pos) /*!< LCD PAL85: B14_0 Mask */
+#define LCD_PAL85_I1_Pos 31 /*!< LCD PAL85: I1 Position */
+#define LCD_PAL85_I1_Msk (0x01UL << LCD_PAL85_I1_Pos) /*!< LCD PAL85: I1 Mask */
+
+// ---------------------------------------- LCD_PAL86 -------------------------------------------
+#define LCD_PAL86_R04_0_Pos 0 /*!< LCD PAL86: R04_0 Position */
+#define LCD_PAL86_R04_0_Msk (0x1fUL << LCD_PAL86_R04_0_Pos) /*!< LCD PAL86: R04_0 Mask */
+#define LCD_PAL86_G04_0_Pos 5 /*!< LCD PAL86: G04_0 Position */
+#define LCD_PAL86_G04_0_Msk (0x1fUL << LCD_PAL86_G04_0_Pos) /*!< LCD PAL86: G04_0 Mask */
+#define LCD_PAL86_B04_0_Pos 10 /*!< LCD PAL86: B04_0 Position */
+#define LCD_PAL86_B04_0_Msk (0x1fUL << LCD_PAL86_B04_0_Pos) /*!< LCD PAL86: B04_0 Mask */
+#define LCD_PAL86_I0_Pos 15 /*!< LCD PAL86: I0 Position */
+#define LCD_PAL86_I0_Msk (0x01UL << LCD_PAL86_I0_Pos) /*!< LCD PAL86: I0 Mask */
+#define LCD_PAL86_R14_0_Pos 16 /*!< LCD PAL86: R14_0 Position */
+#define LCD_PAL86_R14_0_Msk (0x1fUL << LCD_PAL86_R14_0_Pos) /*!< LCD PAL86: R14_0 Mask */
+#define LCD_PAL86_G14_0_Pos 21 /*!< LCD PAL86: G14_0 Position */
+#define LCD_PAL86_G14_0_Msk (0x1fUL << LCD_PAL86_G14_0_Pos) /*!< LCD PAL86: G14_0 Mask */
+#define LCD_PAL86_B14_0_Pos 26 /*!< LCD PAL86: B14_0 Position */
+#define LCD_PAL86_B14_0_Msk (0x1fUL << LCD_PAL86_B14_0_Pos) /*!< LCD PAL86: B14_0 Mask */
+#define LCD_PAL86_I1_Pos 31 /*!< LCD PAL86: I1 Position */
+#define LCD_PAL86_I1_Msk (0x01UL << LCD_PAL86_I1_Pos) /*!< LCD PAL86: I1 Mask */
+
+// ---------------------------------------- LCD_PAL87 -------------------------------------------
+#define LCD_PAL87_R04_0_Pos 0 /*!< LCD PAL87: R04_0 Position */
+#define LCD_PAL87_R04_0_Msk (0x1fUL << LCD_PAL87_R04_0_Pos) /*!< LCD PAL87: R04_0 Mask */
+#define LCD_PAL87_G04_0_Pos 5 /*!< LCD PAL87: G04_0 Position */
+#define LCD_PAL87_G04_0_Msk (0x1fUL << LCD_PAL87_G04_0_Pos) /*!< LCD PAL87: G04_0 Mask */
+#define LCD_PAL87_B04_0_Pos 10 /*!< LCD PAL87: B04_0 Position */
+#define LCD_PAL87_B04_0_Msk (0x1fUL << LCD_PAL87_B04_0_Pos) /*!< LCD PAL87: B04_0 Mask */
+#define LCD_PAL87_I0_Pos 15 /*!< LCD PAL87: I0 Position */
+#define LCD_PAL87_I0_Msk (0x01UL << LCD_PAL87_I0_Pos) /*!< LCD PAL87: I0 Mask */
+#define LCD_PAL87_R14_0_Pos 16 /*!< LCD PAL87: R14_0 Position */
+#define LCD_PAL87_R14_0_Msk (0x1fUL << LCD_PAL87_R14_0_Pos) /*!< LCD PAL87: R14_0 Mask */
+#define LCD_PAL87_G14_0_Pos 21 /*!< LCD PAL87: G14_0 Position */
+#define LCD_PAL87_G14_0_Msk (0x1fUL << LCD_PAL87_G14_0_Pos) /*!< LCD PAL87: G14_0 Mask */
+#define LCD_PAL87_B14_0_Pos 26 /*!< LCD PAL87: B14_0 Position */
+#define LCD_PAL87_B14_0_Msk (0x1fUL << LCD_PAL87_B14_0_Pos) /*!< LCD PAL87: B14_0 Mask */
+#define LCD_PAL87_I1_Pos 31 /*!< LCD PAL87: I1 Position */
+#define LCD_PAL87_I1_Msk (0x01UL << LCD_PAL87_I1_Pos) /*!< LCD PAL87: I1 Mask */
+
+// ---------------------------------------- LCD_PAL88 -------------------------------------------
+#define LCD_PAL88_R04_0_Pos 0 /*!< LCD PAL88: R04_0 Position */
+#define LCD_PAL88_R04_0_Msk (0x1fUL << LCD_PAL88_R04_0_Pos) /*!< LCD PAL88: R04_0 Mask */
+#define LCD_PAL88_G04_0_Pos 5 /*!< LCD PAL88: G04_0 Position */
+#define LCD_PAL88_G04_0_Msk (0x1fUL << LCD_PAL88_G04_0_Pos) /*!< LCD PAL88: G04_0 Mask */
+#define LCD_PAL88_B04_0_Pos 10 /*!< LCD PAL88: B04_0 Position */
+#define LCD_PAL88_B04_0_Msk (0x1fUL << LCD_PAL88_B04_0_Pos) /*!< LCD PAL88: B04_0 Mask */
+#define LCD_PAL88_I0_Pos 15 /*!< LCD PAL88: I0 Position */
+#define LCD_PAL88_I0_Msk (0x01UL << LCD_PAL88_I0_Pos) /*!< LCD PAL88: I0 Mask */
+#define LCD_PAL88_R14_0_Pos 16 /*!< LCD PAL88: R14_0 Position */
+#define LCD_PAL88_R14_0_Msk (0x1fUL << LCD_PAL88_R14_0_Pos) /*!< LCD PAL88: R14_0 Mask */
+#define LCD_PAL88_G14_0_Pos 21 /*!< LCD PAL88: G14_0 Position */
+#define LCD_PAL88_G14_0_Msk (0x1fUL << LCD_PAL88_G14_0_Pos) /*!< LCD PAL88: G14_0 Mask */
+#define LCD_PAL88_B14_0_Pos 26 /*!< LCD PAL88: B14_0 Position */
+#define LCD_PAL88_B14_0_Msk (0x1fUL << LCD_PAL88_B14_0_Pos) /*!< LCD PAL88: B14_0 Mask */
+#define LCD_PAL88_I1_Pos 31 /*!< LCD PAL88: I1 Position */
+#define LCD_PAL88_I1_Msk (0x01UL << LCD_PAL88_I1_Pos) /*!< LCD PAL88: I1 Mask */
+
+// ---------------------------------------- LCD_PAL89 -------------------------------------------
+#define LCD_PAL89_R04_0_Pos 0 /*!< LCD PAL89: R04_0 Position */
+#define LCD_PAL89_R04_0_Msk (0x1fUL << LCD_PAL89_R04_0_Pos) /*!< LCD PAL89: R04_0 Mask */
+#define LCD_PAL89_G04_0_Pos 5 /*!< LCD PAL89: G04_0 Position */
+#define LCD_PAL89_G04_0_Msk (0x1fUL << LCD_PAL89_G04_0_Pos) /*!< LCD PAL89: G04_0 Mask */
+#define LCD_PAL89_B04_0_Pos 10 /*!< LCD PAL89: B04_0 Position */
+#define LCD_PAL89_B04_0_Msk (0x1fUL << LCD_PAL89_B04_0_Pos) /*!< LCD PAL89: B04_0 Mask */
+#define LCD_PAL89_I0_Pos 15 /*!< LCD PAL89: I0 Position */
+#define LCD_PAL89_I0_Msk (0x01UL << LCD_PAL89_I0_Pos) /*!< LCD PAL89: I0 Mask */
+#define LCD_PAL89_R14_0_Pos 16 /*!< LCD PAL89: R14_0 Position */
+#define LCD_PAL89_R14_0_Msk (0x1fUL << LCD_PAL89_R14_0_Pos) /*!< LCD PAL89: R14_0 Mask */
+#define LCD_PAL89_G14_0_Pos 21 /*!< LCD PAL89: G14_0 Position */
+#define LCD_PAL89_G14_0_Msk (0x1fUL << LCD_PAL89_G14_0_Pos) /*!< LCD PAL89: G14_0 Mask */
+#define LCD_PAL89_B14_0_Pos 26 /*!< LCD PAL89: B14_0 Position */
+#define LCD_PAL89_B14_0_Msk (0x1fUL << LCD_PAL89_B14_0_Pos) /*!< LCD PAL89: B14_0 Mask */
+#define LCD_PAL89_I1_Pos 31 /*!< LCD PAL89: I1 Position */
+#define LCD_PAL89_I1_Msk (0x01UL << LCD_PAL89_I1_Pos) /*!< LCD PAL89: I1 Mask */
+
+// ---------------------------------------- LCD_PAL90 -------------------------------------------
+#define LCD_PAL90_R04_0_Pos 0 /*!< LCD PAL90: R04_0 Position */
+#define LCD_PAL90_R04_0_Msk (0x1fUL << LCD_PAL90_R04_0_Pos) /*!< LCD PAL90: R04_0 Mask */
+#define LCD_PAL90_G04_0_Pos 5 /*!< LCD PAL90: G04_0 Position */
+#define LCD_PAL90_G04_0_Msk (0x1fUL << LCD_PAL90_G04_0_Pos) /*!< LCD PAL90: G04_0 Mask */
+#define LCD_PAL90_B04_0_Pos 10 /*!< LCD PAL90: B04_0 Position */
+#define LCD_PAL90_B04_0_Msk (0x1fUL << LCD_PAL90_B04_0_Pos) /*!< LCD PAL90: B04_0 Mask */
+#define LCD_PAL90_I0_Pos 15 /*!< LCD PAL90: I0 Position */
+#define LCD_PAL90_I0_Msk (0x01UL << LCD_PAL90_I0_Pos) /*!< LCD PAL90: I0 Mask */
+#define LCD_PAL90_R14_0_Pos 16 /*!< LCD PAL90: R14_0 Position */
+#define LCD_PAL90_R14_0_Msk (0x1fUL << LCD_PAL90_R14_0_Pos) /*!< LCD PAL90: R14_0 Mask */
+#define LCD_PAL90_G14_0_Pos 21 /*!< LCD PAL90: G14_0 Position */
+#define LCD_PAL90_G14_0_Msk (0x1fUL << LCD_PAL90_G14_0_Pos) /*!< LCD PAL90: G14_0 Mask */
+#define LCD_PAL90_B14_0_Pos 26 /*!< LCD PAL90: B14_0 Position */
+#define LCD_PAL90_B14_0_Msk (0x1fUL << LCD_PAL90_B14_0_Pos) /*!< LCD PAL90: B14_0 Mask */
+#define LCD_PAL90_I1_Pos 31 /*!< LCD PAL90: I1 Position */
+#define LCD_PAL90_I1_Msk (0x01UL << LCD_PAL90_I1_Pos) /*!< LCD PAL90: I1 Mask */
+
+// ---------------------------------------- LCD_PAL91 -------------------------------------------
+#define LCD_PAL91_R04_0_Pos 0 /*!< LCD PAL91: R04_0 Position */
+#define LCD_PAL91_R04_0_Msk (0x1fUL << LCD_PAL91_R04_0_Pos) /*!< LCD PAL91: R04_0 Mask */
+#define LCD_PAL91_G04_0_Pos 5 /*!< LCD PAL91: G04_0 Position */
+#define LCD_PAL91_G04_0_Msk (0x1fUL << LCD_PAL91_G04_0_Pos) /*!< LCD PAL91: G04_0 Mask */
+#define LCD_PAL91_B04_0_Pos 10 /*!< LCD PAL91: B04_0 Position */
+#define LCD_PAL91_B04_0_Msk (0x1fUL << LCD_PAL91_B04_0_Pos) /*!< LCD PAL91: B04_0 Mask */
+#define LCD_PAL91_I0_Pos 15 /*!< LCD PAL91: I0 Position */
+#define LCD_PAL91_I0_Msk (0x01UL << LCD_PAL91_I0_Pos) /*!< LCD PAL91: I0 Mask */
+#define LCD_PAL91_R14_0_Pos 16 /*!< LCD PAL91: R14_0 Position */
+#define LCD_PAL91_R14_0_Msk (0x1fUL << LCD_PAL91_R14_0_Pos) /*!< LCD PAL91: R14_0 Mask */
+#define LCD_PAL91_G14_0_Pos 21 /*!< LCD PAL91: G14_0 Position */
+#define LCD_PAL91_G14_0_Msk (0x1fUL << LCD_PAL91_G14_0_Pos) /*!< LCD PAL91: G14_0 Mask */
+#define LCD_PAL91_B14_0_Pos 26 /*!< LCD PAL91: B14_0 Position */
+#define LCD_PAL91_B14_0_Msk (0x1fUL << LCD_PAL91_B14_0_Pos) /*!< LCD PAL91: B14_0 Mask */
+#define LCD_PAL91_I1_Pos 31 /*!< LCD PAL91: I1 Position */
+#define LCD_PAL91_I1_Msk (0x01UL << LCD_PAL91_I1_Pos) /*!< LCD PAL91: I1 Mask */
+
+// ---------------------------------------- LCD_PAL92 -------------------------------------------
+#define LCD_PAL92_R04_0_Pos 0 /*!< LCD PAL92: R04_0 Position */
+#define LCD_PAL92_R04_0_Msk (0x1fUL << LCD_PAL92_R04_0_Pos) /*!< LCD PAL92: R04_0 Mask */
+#define LCD_PAL92_G04_0_Pos 5 /*!< LCD PAL92: G04_0 Position */
+#define LCD_PAL92_G04_0_Msk (0x1fUL << LCD_PAL92_G04_0_Pos) /*!< LCD PAL92: G04_0 Mask */
+#define LCD_PAL92_B04_0_Pos 10 /*!< LCD PAL92: B04_0 Position */
+#define LCD_PAL92_B04_0_Msk (0x1fUL << LCD_PAL92_B04_0_Pos) /*!< LCD PAL92: B04_0 Mask */
+#define LCD_PAL92_I0_Pos 15 /*!< LCD PAL92: I0 Position */
+#define LCD_PAL92_I0_Msk (0x01UL << LCD_PAL92_I0_Pos) /*!< LCD PAL92: I0 Mask */
+#define LCD_PAL92_R14_0_Pos 16 /*!< LCD PAL92: R14_0 Position */
+#define LCD_PAL92_R14_0_Msk (0x1fUL << LCD_PAL92_R14_0_Pos) /*!< LCD PAL92: R14_0 Mask */
+#define LCD_PAL92_G14_0_Pos 21 /*!< LCD PAL92: G14_0 Position */
+#define LCD_PAL92_G14_0_Msk (0x1fUL << LCD_PAL92_G14_0_Pos) /*!< LCD PAL92: G14_0 Mask */
+#define LCD_PAL92_B14_0_Pos 26 /*!< LCD PAL92: B14_0 Position */
+#define LCD_PAL92_B14_0_Msk (0x1fUL << LCD_PAL92_B14_0_Pos) /*!< LCD PAL92: B14_0 Mask */
+#define LCD_PAL92_I1_Pos 31 /*!< LCD PAL92: I1 Position */
+#define LCD_PAL92_I1_Msk (0x01UL << LCD_PAL92_I1_Pos) /*!< LCD PAL92: I1 Mask */
+
+// ---------------------------------------- LCD_PAL93 -------------------------------------------
+#define LCD_PAL93_R04_0_Pos 0 /*!< LCD PAL93: R04_0 Position */
+#define LCD_PAL93_R04_0_Msk (0x1fUL << LCD_PAL93_R04_0_Pos) /*!< LCD PAL93: R04_0 Mask */
+#define LCD_PAL93_G04_0_Pos 5 /*!< LCD PAL93: G04_0 Position */
+#define LCD_PAL93_G04_0_Msk (0x1fUL << LCD_PAL93_G04_0_Pos) /*!< LCD PAL93: G04_0 Mask */
+#define LCD_PAL93_B04_0_Pos 10 /*!< LCD PAL93: B04_0 Position */
+#define LCD_PAL93_B04_0_Msk (0x1fUL << LCD_PAL93_B04_0_Pos) /*!< LCD PAL93: B04_0 Mask */
+#define LCD_PAL93_I0_Pos 15 /*!< LCD PAL93: I0 Position */
+#define LCD_PAL93_I0_Msk (0x01UL << LCD_PAL93_I0_Pos) /*!< LCD PAL93: I0 Mask */
+#define LCD_PAL93_R14_0_Pos 16 /*!< LCD PAL93: R14_0 Position */
+#define LCD_PAL93_R14_0_Msk (0x1fUL << LCD_PAL93_R14_0_Pos) /*!< LCD PAL93: R14_0 Mask */
+#define LCD_PAL93_G14_0_Pos 21 /*!< LCD PAL93: G14_0 Position */
+#define LCD_PAL93_G14_0_Msk (0x1fUL << LCD_PAL93_G14_0_Pos) /*!< LCD PAL93: G14_0 Mask */
+#define LCD_PAL93_B14_0_Pos 26 /*!< LCD PAL93: B14_0 Position */
+#define LCD_PAL93_B14_0_Msk (0x1fUL << LCD_PAL93_B14_0_Pos) /*!< LCD PAL93: B14_0 Mask */
+#define LCD_PAL93_I1_Pos 31 /*!< LCD PAL93: I1 Position */
+#define LCD_PAL93_I1_Msk (0x01UL << LCD_PAL93_I1_Pos) /*!< LCD PAL93: I1 Mask */
+
+// ---------------------------------------- LCD_PAL94 -------------------------------------------
+#define LCD_PAL94_R04_0_Pos 0 /*!< LCD PAL94: R04_0 Position */
+#define LCD_PAL94_R04_0_Msk (0x1fUL << LCD_PAL94_R04_0_Pos) /*!< LCD PAL94: R04_0 Mask */
+#define LCD_PAL94_G04_0_Pos 5 /*!< LCD PAL94: G04_0 Position */
+#define LCD_PAL94_G04_0_Msk (0x1fUL << LCD_PAL94_G04_0_Pos) /*!< LCD PAL94: G04_0 Mask */
+#define LCD_PAL94_B04_0_Pos 10 /*!< LCD PAL94: B04_0 Position */
+#define LCD_PAL94_B04_0_Msk (0x1fUL << LCD_PAL94_B04_0_Pos) /*!< LCD PAL94: B04_0 Mask */
+#define LCD_PAL94_I0_Pos 15 /*!< LCD PAL94: I0 Position */
+#define LCD_PAL94_I0_Msk (0x01UL << LCD_PAL94_I0_Pos) /*!< LCD PAL94: I0 Mask */
+#define LCD_PAL94_R14_0_Pos 16 /*!< LCD PAL94: R14_0 Position */
+#define LCD_PAL94_R14_0_Msk (0x1fUL << LCD_PAL94_R14_0_Pos) /*!< LCD PAL94: R14_0 Mask */
+#define LCD_PAL94_G14_0_Pos 21 /*!< LCD PAL94: G14_0 Position */
+#define LCD_PAL94_G14_0_Msk (0x1fUL << LCD_PAL94_G14_0_Pos) /*!< LCD PAL94: G14_0 Mask */
+#define LCD_PAL94_B14_0_Pos 26 /*!< LCD PAL94: B14_0 Position */
+#define LCD_PAL94_B14_0_Msk (0x1fUL << LCD_PAL94_B14_0_Pos) /*!< LCD PAL94: B14_0 Mask */
+#define LCD_PAL94_I1_Pos 31 /*!< LCD PAL94: I1 Position */
+#define LCD_PAL94_I1_Msk (0x01UL << LCD_PAL94_I1_Pos) /*!< LCD PAL94: I1 Mask */
+
+// ---------------------------------------- LCD_PAL95 -------------------------------------------
+#define LCD_PAL95_R04_0_Pos 0 /*!< LCD PAL95: R04_0 Position */
+#define LCD_PAL95_R04_0_Msk (0x1fUL << LCD_PAL95_R04_0_Pos) /*!< LCD PAL95: R04_0 Mask */
+#define LCD_PAL95_G04_0_Pos 5 /*!< LCD PAL95: G04_0 Position */
+#define LCD_PAL95_G04_0_Msk (0x1fUL << LCD_PAL95_G04_0_Pos) /*!< LCD PAL95: G04_0 Mask */
+#define LCD_PAL95_B04_0_Pos 10 /*!< LCD PAL95: B04_0 Position */
+#define LCD_PAL95_B04_0_Msk (0x1fUL << LCD_PAL95_B04_0_Pos) /*!< LCD PAL95: B04_0 Mask */
+#define LCD_PAL95_I0_Pos 15 /*!< LCD PAL95: I0 Position */
+#define LCD_PAL95_I0_Msk (0x01UL << LCD_PAL95_I0_Pos) /*!< LCD PAL95: I0 Mask */
+#define LCD_PAL95_R14_0_Pos 16 /*!< LCD PAL95: R14_0 Position */
+#define LCD_PAL95_R14_0_Msk (0x1fUL << LCD_PAL95_R14_0_Pos) /*!< LCD PAL95: R14_0 Mask */
+#define LCD_PAL95_G14_0_Pos 21 /*!< LCD PAL95: G14_0 Position */
+#define LCD_PAL95_G14_0_Msk (0x1fUL << LCD_PAL95_G14_0_Pos) /*!< LCD PAL95: G14_0 Mask */
+#define LCD_PAL95_B14_0_Pos 26 /*!< LCD PAL95: B14_0 Position */
+#define LCD_PAL95_B14_0_Msk (0x1fUL << LCD_PAL95_B14_0_Pos) /*!< LCD PAL95: B14_0 Mask */
+#define LCD_PAL95_I1_Pos 31 /*!< LCD PAL95: I1 Position */
+#define LCD_PAL95_I1_Msk (0x01UL << LCD_PAL95_I1_Pos) /*!< LCD PAL95: I1 Mask */
+
+// ---------------------------------------- LCD_PAL96 -------------------------------------------
+#define LCD_PAL96_R04_0_Pos 0 /*!< LCD PAL96: R04_0 Position */
+#define LCD_PAL96_R04_0_Msk (0x1fUL << LCD_PAL96_R04_0_Pos) /*!< LCD PAL96: R04_0 Mask */
+#define LCD_PAL96_G04_0_Pos 5 /*!< LCD PAL96: G04_0 Position */
+#define LCD_PAL96_G04_0_Msk (0x1fUL << LCD_PAL96_G04_0_Pos) /*!< LCD PAL96: G04_0 Mask */
+#define LCD_PAL96_B04_0_Pos 10 /*!< LCD PAL96: B04_0 Position */
+#define LCD_PAL96_B04_0_Msk (0x1fUL << LCD_PAL96_B04_0_Pos) /*!< LCD PAL96: B04_0 Mask */
+#define LCD_PAL96_I0_Pos 15 /*!< LCD PAL96: I0 Position */
+#define LCD_PAL96_I0_Msk (0x01UL << LCD_PAL96_I0_Pos) /*!< LCD PAL96: I0 Mask */
+#define LCD_PAL96_R14_0_Pos 16 /*!< LCD PAL96: R14_0 Position */
+#define LCD_PAL96_R14_0_Msk (0x1fUL << LCD_PAL96_R14_0_Pos) /*!< LCD PAL96: R14_0 Mask */
+#define LCD_PAL96_G14_0_Pos 21 /*!< LCD PAL96: G14_0 Position */
+#define LCD_PAL96_G14_0_Msk (0x1fUL << LCD_PAL96_G14_0_Pos) /*!< LCD PAL96: G14_0 Mask */
+#define LCD_PAL96_B14_0_Pos 26 /*!< LCD PAL96: B14_0 Position */
+#define LCD_PAL96_B14_0_Msk (0x1fUL << LCD_PAL96_B14_0_Pos) /*!< LCD PAL96: B14_0 Mask */
+#define LCD_PAL96_I1_Pos 31 /*!< LCD PAL96: I1 Position */
+#define LCD_PAL96_I1_Msk (0x01UL << LCD_PAL96_I1_Pos) /*!< LCD PAL96: I1 Mask */
+
+// ---------------------------------------- LCD_PAL97 -------------------------------------------
+#define LCD_PAL97_R04_0_Pos 0 /*!< LCD PAL97: R04_0 Position */
+#define LCD_PAL97_R04_0_Msk (0x1fUL << LCD_PAL97_R04_0_Pos) /*!< LCD PAL97: R04_0 Mask */
+#define LCD_PAL97_G04_0_Pos 5 /*!< LCD PAL97: G04_0 Position */
+#define LCD_PAL97_G04_0_Msk (0x1fUL << LCD_PAL97_G04_0_Pos) /*!< LCD PAL97: G04_0 Mask */
+#define LCD_PAL97_B04_0_Pos 10 /*!< LCD PAL97: B04_0 Position */
+#define LCD_PAL97_B04_0_Msk (0x1fUL << LCD_PAL97_B04_0_Pos) /*!< LCD PAL97: B04_0 Mask */
+#define LCD_PAL97_I0_Pos 15 /*!< LCD PAL97: I0 Position */
+#define LCD_PAL97_I0_Msk (0x01UL << LCD_PAL97_I0_Pos) /*!< LCD PAL97: I0 Mask */
+#define LCD_PAL97_R14_0_Pos 16 /*!< LCD PAL97: R14_0 Position */
+#define LCD_PAL97_R14_0_Msk (0x1fUL << LCD_PAL97_R14_0_Pos) /*!< LCD PAL97: R14_0 Mask */
+#define LCD_PAL97_G14_0_Pos 21 /*!< LCD PAL97: G14_0 Position */
+#define LCD_PAL97_G14_0_Msk (0x1fUL << LCD_PAL97_G14_0_Pos) /*!< LCD PAL97: G14_0 Mask */
+#define LCD_PAL97_B14_0_Pos 26 /*!< LCD PAL97: B14_0 Position */
+#define LCD_PAL97_B14_0_Msk (0x1fUL << LCD_PAL97_B14_0_Pos) /*!< LCD PAL97: B14_0 Mask */
+#define LCD_PAL97_I1_Pos 31 /*!< LCD PAL97: I1 Position */
+#define LCD_PAL97_I1_Msk (0x01UL << LCD_PAL97_I1_Pos) /*!< LCD PAL97: I1 Mask */
+
+// ---------------------------------------- LCD_PAL98 -------------------------------------------
+#define LCD_PAL98_R04_0_Pos 0 /*!< LCD PAL98: R04_0 Position */
+#define LCD_PAL98_R04_0_Msk (0x1fUL << LCD_PAL98_R04_0_Pos) /*!< LCD PAL98: R04_0 Mask */
+#define LCD_PAL98_G04_0_Pos 5 /*!< LCD PAL98: G04_0 Position */
+#define LCD_PAL98_G04_0_Msk (0x1fUL << LCD_PAL98_G04_0_Pos) /*!< LCD PAL98: G04_0 Mask */
+#define LCD_PAL98_B04_0_Pos 10 /*!< LCD PAL98: B04_0 Position */
+#define LCD_PAL98_B04_0_Msk (0x1fUL << LCD_PAL98_B04_0_Pos) /*!< LCD PAL98: B04_0 Mask */
+#define LCD_PAL98_I0_Pos 15 /*!< LCD PAL98: I0 Position */
+#define LCD_PAL98_I0_Msk (0x01UL << LCD_PAL98_I0_Pos) /*!< LCD PAL98: I0 Mask */
+#define LCD_PAL98_R14_0_Pos 16 /*!< LCD PAL98: R14_0 Position */
+#define LCD_PAL98_R14_0_Msk (0x1fUL << LCD_PAL98_R14_0_Pos) /*!< LCD PAL98: R14_0 Mask */
+#define LCD_PAL98_G14_0_Pos 21 /*!< LCD PAL98: G14_0 Position */
+#define LCD_PAL98_G14_0_Msk (0x1fUL << LCD_PAL98_G14_0_Pos) /*!< LCD PAL98: G14_0 Mask */
+#define LCD_PAL98_B14_0_Pos 26 /*!< LCD PAL98: B14_0 Position */
+#define LCD_PAL98_B14_0_Msk (0x1fUL << LCD_PAL98_B14_0_Pos) /*!< LCD PAL98: B14_0 Mask */
+#define LCD_PAL98_I1_Pos 31 /*!< LCD PAL98: I1 Position */
+#define LCD_PAL98_I1_Msk (0x01UL << LCD_PAL98_I1_Pos) /*!< LCD PAL98: I1 Mask */
+
+// ---------------------------------------- LCD_PAL99 -------------------------------------------
+#define LCD_PAL99_R04_0_Pos 0 /*!< LCD PAL99: R04_0 Position */
+#define LCD_PAL99_R04_0_Msk (0x1fUL << LCD_PAL99_R04_0_Pos) /*!< LCD PAL99: R04_0 Mask */
+#define LCD_PAL99_G04_0_Pos 5 /*!< LCD PAL99: G04_0 Position */
+#define LCD_PAL99_G04_0_Msk (0x1fUL << LCD_PAL99_G04_0_Pos) /*!< LCD PAL99: G04_0 Mask */
+#define LCD_PAL99_B04_0_Pos 10 /*!< LCD PAL99: B04_0 Position */
+#define LCD_PAL99_B04_0_Msk (0x1fUL << LCD_PAL99_B04_0_Pos) /*!< LCD PAL99: B04_0 Mask */
+#define LCD_PAL99_I0_Pos 15 /*!< LCD PAL99: I0 Position */
+#define LCD_PAL99_I0_Msk (0x01UL << LCD_PAL99_I0_Pos) /*!< LCD PAL99: I0 Mask */
+#define LCD_PAL99_R14_0_Pos 16 /*!< LCD PAL99: R14_0 Position */
+#define LCD_PAL99_R14_0_Msk (0x1fUL << LCD_PAL99_R14_0_Pos) /*!< LCD PAL99: R14_0 Mask */
+#define LCD_PAL99_G14_0_Pos 21 /*!< LCD PAL99: G14_0 Position */
+#define LCD_PAL99_G14_0_Msk (0x1fUL << LCD_PAL99_G14_0_Pos) /*!< LCD PAL99: G14_0 Mask */
+#define LCD_PAL99_B14_0_Pos 26 /*!< LCD PAL99: B14_0 Position */
+#define LCD_PAL99_B14_0_Msk (0x1fUL << LCD_PAL99_B14_0_Pos) /*!< LCD PAL99: B14_0 Mask */
+#define LCD_PAL99_I1_Pos 31 /*!< LCD PAL99: I1 Position */
+#define LCD_PAL99_I1_Msk (0x01UL << LCD_PAL99_I1_Pos) /*!< LCD PAL99: I1 Mask */
+
+// --------------------------------------- LCD_PAL100 -------------------------------------------
+#define LCD_PAL100_R04_0_Pos 0 /*!< LCD PAL100: R04_0 Position */
+#define LCD_PAL100_R04_0_Msk (0x1fUL << LCD_PAL100_R04_0_Pos) /*!< LCD PAL100: R04_0 Mask */
+#define LCD_PAL100_G04_0_Pos 5 /*!< LCD PAL100: G04_0 Position */
+#define LCD_PAL100_G04_0_Msk (0x1fUL << LCD_PAL100_G04_0_Pos) /*!< LCD PAL100: G04_0 Mask */
+#define LCD_PAL100_B04_0_Pos 10 /*!< LCD PAL100: B04_0 Position */
+#define LCD_PAL100_B04_0_Msk (0x1fUL << LCD_PAL100_B04_0_Pos) /*!< LCD PAL100: B04_0 Mask */
+#define LCD_PAL100_I0_Pos 15 /*!< LCD PAL100: I0 Position */
+#define LCD_PAL100_I0_Msk (0x01UL << LCD_PAL100_I0_Pos) /*!< LCD PAL100: I0 Mask */
+#define LCD_PAL100_R14_0_Pos 16 /*!< LCD PAL100: R14_0 Position */
+#define LCD_PAL100_R14_0_Msk (0x1fUL << LCD_PAL100_R14_0_Pos) /*!< LCD PAL100: R14_0 Mask */
+#define LCD_PAL100_G14_0_Pos 21 /*!< LCD PAL100: G14_0 Position */
+#define LCD_PAL100_G14_0_Msk (0x1fUL << LCD_PAL100_G14_0_Pos) /*!< LCD PAL100: G14_0 Mask */
+#define LCD_PAL100_B14_0_Pos 26 /*!< LCD PAL100: B14_0 Position */
+#define LCD_PAL100_B14_0_Msk (0x1fUL << LCD_PAL100_B14_0_Pos) /*!< LCD PAL100: B14_0 Mask */
+#define LCD_PAL100_I1_Pos 31 /*!< LCD PAL100: I1 Position */
+#define LCD_PAL100_I1_Msk (0x01UL << LCD_PAL100_I1_Pos) /*!< LCD PAL100: I1 Mask */
+
+// --------------------------------------- LCD_PAL101 -------------------------------------------
+#define LCD_PAL101_R04_0_Pos 0 /*!< LCD PAL101: R04_0 Position */
+#define LCD_PAL101_R04_0_Msk (0x1fUL << LCD_PAL101_R04_0_Pos) /*!< LCD PAL101: R04_0 Mask */
+#define LCD_PAL101_G04_0_Pos 5 /*!< LCD PAL101: G04_0 Position */
+#define LCD_PAL101_G04_0_Msk (0x1fUL << LCD_PAL101_G04_0_Pos) /*!< LCD PAL101: G04_0 Mask */
+#define LCD_PAL101_B04_0_Pos 10 /*!< LCD PAL101: B04_0 Position */
+#define LCD_PAL101_B04_0_Msk (0x1fUL << LCD_PAL101_B04_0_Pos) /*!< LCD PAL101: B04_0 Mask */
+#define LCD_PAL101_I0_Pos 15 /*!< LCD PAL101: I0 Position */
+#define LCD_PAL101_I0_Msk (0x01UL << LCD_PAL101_I0_Pos) /*!< LCD PAL101: I0 Mask */
+#define LCD_PAL101_R14_0_Pos 16 /*!< LCD PAL101: R14_0 Position */
+#define LCD_PAL101_R14_0_Msk (0x1fUL << LCD_PAL101_R14_0_Pos) /*!< LCD PAL101: R14_0 Mask */
+#define LCD_PAL101_G14_0_Pos 21 /*!< LCD PAL101: G14_0 Position */
+#define LCD_PAL101_G14_0_Msk (0x1fUL << LCD_PAL101_G14_0_Pos) /*!< LCD PAL101: G14_0 Mask */
+#define LCD_PAL101_B14_0_Pos 26 /*!< LCD PAL101: B14_0 Position */
+#define LCD_PAL101_B14_0_Msk (0x1fUL << LCD_PAL101_B14_0_Pos) /*!< LCD PAL101: B14_0 Mask */
+#define LCD_PAL101_I1_Pos 31 /*!< LCD PAL101: I1 Position */
+#define LCD_PAL101_I1_Msk (0x01UL << LCD_PAL101_I1_Pos) /*!< LCD PAL101: I1 Mask */
+
+// --------------------------------------- LCD_PAL102 -------------------------------------------
+#define LCD_PAL102_R04_0_Pos 0 /*!< LCD PAL102: R04_0 Position */
+#define LCD_PAL102_R04_0_Msk (0x1fUL << LCD_PAL102_R04_0_Pos) /*!< LCD PAL102: R04_0 Mask */
+#define LCD_PAL102_G04_0_Pos 5 /*!< LCD PAL102: G04_0 Position */
+#define LCD_PAL102_G04_0_Msk (0x1fUL << LCD_PAL102_G04_0_Pos) /*!< LCD PAL102: G04_0 Mask */
+#define LCD_PAL102_B04_0_Pos 10 /*!< LCD PAL102: B04_0 Position */
+#define LCD_PAL102_B04_0_Msk (0x1fUL << LCD_PAL102_B04_0_Pos) /*!< LCD PAL102: B04_0 Mask */
+#define LCD_PAL102_I0_Pos 15 /*!< LCD PAL102: I0 Position */
+#define LCD_PAL102_I0_Msk (0x01UL << LCD_PAL102_I0_Pos) /*!< LCD PAL102: I0 Mask */
+#define LCD_PAL102_R14_0_Pos 16 /*!< LCD PAL102: R14_0 Position */
+#define LCD_PAL102_R14_0_Msk (0x1fUL << LCD_PAL102_R14_0_Pos) /*!< LCD PAL102: R14_0 Mask */
+#define LCD_PAL102_G14_0_Pos 21 /*!< LCD PAL102: G14_0 Position */
+#define LCD_PAL102_G14_0_Msk (0x1fUL << LCD_PAL102_G14_0_Pos) /*!< LCD PAL102: G14_0 Mask */
+#define LCD_PAL102_B14_0_Pos 26 /*!< LCD PAL102: B14_0 Position */
+#define LCD_PAL102_B14_0_Msk (0x1fUL << LCD_PAL102_B14_0_Pos) /*!< LCD PAL102: B14_0 Mask */
+#define LCD_PAL102_I1_Pos 31 /*!< LCD PAL102: I1 Position */
+#define LCD_PAL102_I1_Msk (0x01UL << LCD_PAL102_I1_Pos) /*!< LCD PAL102: I1 Mask */
+
+// --------------------------------------- LCD_PAL103 -------------------------------------------
+#define LCD_PAL103_R04_0_Pos 0 /*!< LCD PAL103: R04_0 Position */
+#define LCD_PAL103_R04_0_Msk (0x1fUL << LCD_PAL103_R04_0_Pos) /*!< LCD PAL103: R04_0 Mask */
+#define LCD_PAL103_G04_0_Pos 5 /*!< LCD PAL103: G04_0 Position */
+#define LCD_PAL103_G04_0_Msk (0x1fUL << LCD_PAL103_G04_0_Pos) /*!< LCD PAL103: G04_0 Mask */
+#define LCD_PAL103_B04_0_Pos 10 /*!< LCD PAL103: B04_0 Position */
+#define LCD_PAL103_B04_0_Msk (0x1fUL << LCD_PAL103_B04_0_Pos) /*!< LCD PAL103: B04_0 Mask */
+#define LCD_PAL103_I0_Pos 15 /*!< LCD PAL103: I0 Position */
+#define LCD_PAL103_I0_Msk (0x01UL << LCD_PAL103_I0_Pos) /*!< LCD PAL103: I0 Mask */
+#define LCD_PAL103_R14_0_Pos 16 /*!< LCD PAL103: R14_0 Position */
+#define LCD_PAL103_R14_0_Msk (0x1fUL << LCD_PAL103_R14_0_Pos) /*!< LCD PAL103: R14_0 Mask */
+#define LCD_PAL103_G14_0_Pos 21 /*!< LCD PAL103: G14_0 Position */
+#define LCD_PAL103_G14_0_Msk (0x1fUL << LCD_PAL103_G14_0_Pos) /*!< LCD PAL103: G14_0 Mask */
+#define LCD_PAL103_B14_0_Pos 26 /*!< LCD PAL103: B14_0 Position */
+#define LCD_PAL103_B14_0_Msk (0x1fUL << LCD_PAL103_B14_0_Pos) /*!< LCD PAL103: B14_0 Mask */
+#define LCD_PAL103_I1_Pos 31 /*!< LCD PAL103: I1 Position */
+#define LCD_PAL103_I1_Msk (0x01UL << LCD_PAL103_I1_Pos) /*!< LCD PAL103: I1 Mask */
+
+// --------------------------------------- LCD_PAL104 -------------------------------------------
+#define LCD_PAL104_R04_0_Pos 0 /*!< LCD PAL104: R04_0 Position */
+#define LCD_PAL104_R04_0_Msk (0x1fUL << LCD_PAL104_R04_0_Pos) /*!< LCD PAL104: R04_0 Mask */
+#define LCD_PAL104_G04_0_Pos 5 /*!< LCD PAL104: G04_0 Position */
+#define LCD_PAL104_G04_0_Msk (0x1fUL << LCD_PAL104_G04_0_Pos) /*!< LCD PAL104: G04_0 Mask */
+#define LCD_PAL104_B04_0_Pos 10 /*!< LCD PAL104: B04_0 Position */
+#define LCD_PAL104_B04_0_Msk (0x1fUL << LCD_PAL104_B04_0_Pos) /*!< LCD PAL104: B04_0 Mask */
+#define LCD_PAL104_I0_Pos 15 /*!< LCD PAL104: I0 Position */
+#define LCD_PAL104_I0_Msk (0x01UL << LCD_PAL104_I0_Pos) /*!< LCD PAL104: I0 Mask */
+#define LCD_PAL104_R14_0_Pos 16 /*!< LCD PAL104: R14_0 Position */
+#define LCD_PAL104_R14_0_Msk (0x1fUL << LCD_PAL104_R14_0_Pos) /*!< LCD PAL104: R14_0 Mask */
+#define LCD_PAL104_G14_0_Pos 21 /*!< LCD PAL104: G14_0 Position */
+#define LCD_PAL104_G14_0_Msk (0x1fUL << LCD_PAL104_G14_0_Pos) /*!< LCD PAL104: G14_0 Mask */
+#define LCD_PAL104_B14_0_Pos 26 /*!< LCD PAL104: B14_0 Position */
+#define LCD_PAL104_B14_0_Msk (0x1fUL << LCD_PAL104_B14_0_Pos) /*!< LCD PAL104: B14_0 Mask */
+#define LCD_PAL104_I1_Pos 31 /*!< LCD PAL104: I1 Position */
+#define LCD_PAL104_I1_Msk (0x01UL << LCD_PAL104_I1_Pos) /*!< LCD PAL104: I1 Mask */
+
+// --------------------------------------- LCD_PAL105 -------------------------------------------
+#define LCD_PAL105_R04_0_Pos 0 /*!< LCD PAL105: R04_0 Position */
+#define LCD_PAL105_R04_0_Msk (0x1fUL << LCD_PAL105_R04_0_Pos) /*!< LCD PAL105: R04_0 Mask */
+#define LCD_PAL105_G04_0_Pos 5 /*!< LCD PAL105: G04_0 Position */
+#define LCD_PAL105_G04_0_Msk (0x1fUL << LCD_PAL105_G04_0_Pos) /*!< LCD PAL105: G04_0 Mask */
+#define LCD_PAL105_B04_0_Pos 10 /*!< LCD PAL105: B04_0 Position */
+#define LCD_PAL105_B04_0_Msk (0x1fUL << LCD_PAL105_B04_0_Pos) /*!< LCD PAL105: B04_0 Mask */
+#define LCD_PAL105_I0_Pos 15 /*!< LCD PAL105: I0 Position */
+#define LCD_PAL105_I0_Msk (0x01UL << LCD_PAL105_I0_Pos) /*!< LCD PAL105: I0 Mask */
+#define LCD_PAL105_R14_0_Pos 16 /*!< LCD PAL105: R14_0 Position */
+#define LCD_PAL105_R14_0_Msk (0x1fUL << LCD_PAL105_R14_0_Pos) /*!< LCD PAL105: R14_0 Mask */
+#define LCD_PAL105_G14_0_Pos 21 /*!< LCD PAL105: G14_0 Position */
+#define LCD_PAL105_G14_0_Msk (0x1fUL << LCD_PAL105_G14_0_Pos) /*!< LCD PAL105: G14_0 Mask */
+#define LCD_PAL105_B14_0_Pos 26 /*!< LCD PAL105: B14_0 Position */
+#define LCD_PAL105_B14_0_Msk (0x1fUL << LCD_PAL105_B14_0_Pos) /*!< LCD PAL105: B14_0 Mask */
+#define LCD_PAL105_I1_Pos 31 /*!< LCD PAL105: I1 Position */
+#define LCD_PAL105_I1_Msk (0x01UL << LCD_PAL105_I1_Pos) /*!< LCD PAL105: I1 Mask */
+
+// --------------------------------------- LCD_PAL106 -------------------------------------------
+#define LCD_PAL106_R04_0_Pos 0 /*!< LCD PAL106: R04_0 Position */
+#define LCD_PAL106_R04_0_Msk (0x1fUL << LCD_PAL106_R04_0_Pos) /*!< LCD PAL106: R04_0 Mask */
+#define LCD_PAL106_G04_0_Pos 5 /*!< LCD PAL106: G04_0 Position */
+#define LCD_PAL106_G04_0_Msk (0x1fUL << LCD_PAL106_G04_0_Pos) /*!< LCD PAL106: G04_0 Mask */
+#define LCD_PAL106_B04_0_Pos 10 /*!< LCD PAL106: B04_0 Position */
+#define LCD_PAL106_B04_0_Msk (0x1fUL << LCD_PAL106_B04_0_Pos) /*!< LCD PAL106: B04_0 Mask */
+#define LCD_PAL106_I0_Pos 15 /*!< LCD PAL106: I0 Position */
+#define LCD_PAL106_I0_Msk (0x01UL << LCD_PAL106_I0_Pos) /*!< LCD PAL106: I0 Mask */
+#define LCD_PAL106_R14_0_Pos 16 /*!< LCD PAL106: R14_0 Position */
+#define LCD_PAL106_R14_0_Msk (0x1fUL << LCD_PAL106_R14_0_Pos) /*!< LCD PAL106: R14_0 Mask */
+#define LCD_PAL106_G14_0_Pos 21 /*!< LCD PAL106: G14_0 Position */
+#define LCD_PAL106_G14_0_Msk (0x1fUL << LCD_PAL106_G14_0_Pos) /*!< LCD PAL106: G14_0 Mask */
+#define LCD_PAL106_B14_0_Pos 26 /*!< LCD PAL106: B14_0 Position */
+#define LCD_PAL106_B14_0_Msk (0x1fUL << LCD_PAL106_B14_0_Pos) /*!< LCD PAL106: B14_0 Mask */
+#define LCD_PAL106_I1_Pos 31 /*!< LCD PAL106: I1 Position */
+#define LCD_PAL106_I1_Msk (0x01UL << LCD_PAL106_I1_Pos) /*!< LCD PAL106: I1 Mask */
+
+// --------------------------------------- LCD_PAL107 -------------------------------------------
+#define LCD_PAL107_R04_0_Pos 0 /*!< LCD PAL107: R04_0 Position */
+#define LCD_PAL107_R04_0_Msk (0x1fUL << LCD_PAL107_R04_0_Pos) /*!< LCD PAL107: R04_0 Mask */
+#define LCD_PAL107_G04_0_Pos 5 /*!< LCD PAL107: G04_0 Position */
+#define LCD_PAL107_G04_0_Msk (0x1fUL << LCD_PAL107_G04_0_Pos) /*!< LCD PAL107: G04_0 Mask */
+#define LCD_PAL107_B04_0_Pos 10 /*!< LCD PAL107: B04_0 Position */
+#define LCD_PAL107_B04_0_Msk (0x1fUL << LCD_PAL107_B04_0_Pos) /*!< LCD PAL107: B04_0 Mask */
+#define LCD_PAL107_I0_Pos 15 /*!< LCD PAL107: I0 Position */
+#define LCD_PAL107_I0_Msk (0x01UL << LCD_PAL107_I0_Pos) /*!< LCD PAL107: I0 Mask */
+#define LCD_PAL107_R14_0_Pos 16 /*!< LCD PAL107: R14_0 Position */
+#define LCD_PAL107_R14_0_Msk (0x1fUL << LCD_PAL107_R14_0_Pos) /*!< LCD PAL107: R14_0 Mask */
+#define LCD_PAL107_G14_0_Pos 21 /*!< LCD PAL107: G14_0 Position */
+#define LCD_PAL107_G14_0_Msk (0x1fUL << LCD_PAL107_G14_0_Pos) /*!< LCD PAL107: G14_0 Mask */
+#define LCD_PAL107_B14_0_Pos 26 /*!< LCD PAL107: B14_0 Position */
+#define LCD_PAL107_B14_0_Msk (0x1fUL << LCD_PAL107_B14_0_Pos) /*!< LCD PAL107: B14_0 Mask */
+#define LCD_PAL107_I1_Pos 31 /*!< LCD PAL107: I1 Position */
+#define LCD_PAL107_I1_Msk (0x01UL << LCD_PAL107_I1_Pos) /*!< LCD PAL107: I1 Mask */
+
+// --------------------------------------- LCD_PAL108 -------------------------------------------
+#define LCD_PAL108_R04_0_Pos 0 /*!< LCD PAL108: R04_0 Position */
+#define LCD_PAL108_R04_0_Msk (0x1fUL << LCD_PAL108_R04_0_Pos) /*!< LCD PAL108: R04_0 Mask */
+#define LCD_PAL108_G04_0_Pos 5 /*!< LCD PAL108: G04_0 Position */
+#define LCD_PAL108_G04_0_Msk (0x1fUL << LCD_PAL108_G04_0_Pos) /*!< LCD PAL108: G04_0 Mask */
+#define LCD_PAL108_B04_0_Pos 10 /*!< LCD PAL108: B04_0 Position */
+#define LCD_PAL108_B04_0_Msk (0x1fUL << LCD_PAL108_B04_0_Pos) /*!< LCD PAL108: B04_0 Mask */
+#define LCD_PAL108_I0_Pos 15 /*!< LCD PAL108: I0 Position */
+#define LCD_PAL108_I0_Msk (0x01UL << LCD_PAL108_I0_Pos) /*!< LCD PAL108: I0 Mask */
+#define LCD_PAL108_R14_0_Pos 16 /*!< LCD PAL108: R14_0 Position */
+#define LCD_PAL108_R14_0_Msk (0x1fUL << LCD_PAL108_R14_0_Pos) /*!< LCD PAL108: R14_0 Mask */
+#define LCD_PAL108_G14_0_Pos 21 /*!< LCD PAL108: G14_0 Position */
+#define LCD_PAL108_G14_0_Msk (0x1fUL << LCD_PAL108_G14_0_Pos) /*!< LCD PAL108: G14_0 Mask */
+#define LCD_PAL108_B14_0_Pos 26 /*!< LCD PAL108: B14_0 Position */
+#define LCD_PAL108_B14_0_Msk (0x1fUL << LCD_PAL108_B14_0_Pos) /*!< LCD PAL108: B14_0 Mask */
+#define LCD_PAL108_I1_Pos 31 /*!< LCD PAL108: I1 Position */
+#define LCD_PAL108_I1_Msk (0x01UL << LCD_PAL108_I1_Pos) /*!< LCD PAL108: I1 Mask */
+
+// --------------------------------------- LCD_PAL109 -------------------------------------------
+#define LCD_PAL109_R04_0_Pos 0 /*!< LCD PAL109: R04_0 Position */
+#define LCD_PAL109_R04_0_Msk (0x1fUL << LCD_PAL109_R04_0_Pos) /*!< LCD PAL109: R04_0 Mask */
+#define LCD_PAL109_G04_0_Pos 5 /*!< LCD PAL109: G04_0 Position */
+#define LCD_PAL109_G04_0_Msk (0x1fUL << LCD_PAL109_G04_0_Pos) /*!< LCD PAL109: G04_0 Mask */
+#define LCD_PAL109_B04_0_Pos 10 /*!< LCD PAL109: B04_0 Position */
+#define LCD_PAL109_B04_0_Msk (0x1fUL << LCD_PAL109_B04_0_Pos) /*!< LCD PAL109: B04_0 Mask */
+#define LCD_PAL109_I0_Pos 15 /*!< LCD PAL109: I0 Position */
+#define LCD_PAL109_I0_Msk (0x01UL << LCD_PAL109_I0_Pos) /*!< LCD PAL109: I0 Mask */
+#define LCD_PAL109_R14_0_Pos 16 /*!< LCD PAL109: R14_0 Position */
+#define LCD_PAL109_R14_0_Msk (0x1fUL << LCD_PAL109_R14_0_Pos) /*!< LCD PAL109: R14_0 Mask */
+#define LCD_PAL109_G14_0_Pos 21 /*!< LCD PAL109: G14_0 Position */
+#define LCD_PAL109_G14_0_Msk (0x1fUL << LCD_PAL109_G14_0_Pos) /*!< LCD PAL109: G14_0 Mask */
+#define LCD_PAL109_B14_0_Pos 26 /*!< LCD PAL109: B14_0 Position */
+#define LCD_PAL109_B14_0_Msk (0x1fUL << LCD_PAL109_B14_0_Pos) /*!< LCD PAL109: B14_0 Mask */
+#define LCD_PAL109_I1_Pos 31 /*!< LCD PAL109: I1 Position */
+#define LCD_PAL109_I1_Msk (0x01UL << LCD_PAL109_I1_Pos) /*!< LCD PAL109: I1 Mask */
+
+// --------------------------------------- LCD_PAL110 -------------------------------------------
+#define LCD_PAL110_R04_0_Pos 0 /*!< LCD PAL110: R04_0 Position */
+#define LCD_PAL110_R04_0_Msk (0x1fUL << LCD_PAL110_R04_0_Pos) /*!< LCD PAL110: R04_0 Mask */
+#define LCD_PAL110_G04_0_Pos 5 /*!< LCD PAL110: G04_0 Position */
+#define LCD_PAL110_G04_0_Msk (0x1fUL << LCD_PAL110_G04_0_Pos) /*!< LCD PAL110: G04_0 Mask */
+#define LCD_PAL110_B04_0_Pos 10 /*!< LCD PAL110: B04_0 Position */
+#define LCD_PAL110_B04_0_Msk (0x1fUL << LCD_PAL110_B04_0_Pos) /*!< LCD PAL110: B04_0 Mask */
+#define LCD_PAL110_I0_Pos 15 /*!< LCD PAL110: I0 Position */
+#define LCD_PAL110_I0_Msk (0x01UL << LCD_PAL110_I0_Pos) /*!< LCD PAL110: I0 Mask */
+#define LCD_PAL110_R14_0_Pos 16 /*!< LCD PAL110: R14_0 Position */
+#define LCD_PAL110_R14_0_Msk (0x1fUL << LCD_PAL110_R14_0_Pos) /*!< LCD PAL110: R14_0 Mask */
+#define LCD_PAL110_G14_0_Pos 21 /*!< LCD PAL110: G14_0 Position */
+#define LCD_PAL110_G14_0_Msk (0x1fUL << LCD_PAL110_G14_0_Pos) /*!< LCD PAL110: G14_0 Mask */
+#define LCD_PAL110_B14_0_Pos 26 /*!< LCD PAL110: B14_0 Position */
+#define LCD_PAL110_B14_0_Msk (0x1fUL << LCD_PAL110_B14_0_Pos) /*!< LCD PAL110: B14_0 Mask */
+#define LCD_PAL110_I1_Pos 31 /*!< LCD PAL110: I1 Position */
+#define LCD_PAL110_I1_Msk (0x01UL << LCD_PAL110_I1_Pos) /*!< LCD PAL110: I1 Mask */
+
+// --------------------------------------- LCD_PAL111 -------------------------------------------
+#define LCD_PAL111_R04_0_Pos 0 /*!< LCD PAL111: R04_0 Position */
+#define LCD_PAL111_R04_0_Msk (0x1fUL << LCD_PAL111_R04_0_Pos) /*!< LCD PAL111: R04_0 Mask */
+#define LCD_PAL111_G04_0_Pos 5 /*!< LCD PAL111: G04_0 Position */
+#define LCD_PAL111_G04_0_Msk (0x1fUL << LCD_PAL111_G04_0_Pos) /*!< LCD PAL111: G04_0 Mask */
+#define LCD_PAL111_B04_0_Pos 10 /*!< LCD PAL111: B04_0 Position */
+#define LCD_PAL111_B04_0_Msk (0x1fUL << LCD_PAL111_B04_0_Pos) /*!< LCD PAL111: B04_0 Mask */
+#define LCD_PAL111_I0_Pos 15 /*!< LCD PAL111: I0 Position */
+#define LCD_PAL111_I0_Msk (0x01UL << LCD_PAL111_I0_Pos) /*!< LCD PAL111: I0 Mask */
+#define LCD_PAL111_R14_0_Pos 16 /*!< LCD PAL111: R14_0 Position */
+#define LCD_PAL111_R14_0_Msk (0x1fUL << LCD_PAL111_R14_0_Pos) /*!< LCD PAL111: R14_0 Mask */
+#define LCD_PAL111_G14_0_Pos 21 /*!< LCD PAL111: G14_0 Position */
+#define LCD_PAL111_G14_0_Msk (0x1fUL << LCD_PAL111_G14_0_Pos) /*!< LCD PAL111: G14_0 Mask */
+#define LCD_PAL111_B14_0_Pos 26 /*!< LCD PAL111: B14_0 Position */
+#define LCD_PAL111_B14_0_Msk (0x1fUL << LCD_PAL111_B14_0_Pos) /*!< LCD PAL111: B14_0 Mask */
+#define LCD_PAL111_I1_Pos 31 /*!< LCD PAL111: I1 Position */
+#define LCD_PAL111_I1_Msk (0x01UL << LCD_PAL111_I1_Pos) /*!< LCD PAL111: I1 Mask */
+
+// --------------------------------------- LCD_PAL112 -------------------------------------------
+#define LCD_PAL112_R04_0_Pos 0 /*!< LCD PAL112: R04_0 Position */
+#define LCD_PAL112_R04_0_Msk (0x1fUL << LCD_PAL112_R04_0_Pos) /*!< LCD PAL112: R04_0 Mask */
+#define LCD_PAL112_G04_0_Pos 5 /*!< LCD PAL112: G04_0 Position */
+#define LCD_PAL112_G04_0_Msk (0x1fUL << LCD_PAL112_G04_0_Pos) /*!< LCD PAL112: G04_0 Mask */
+#define LCD_PAL112_B04_0_Pos 10 /*!< LCD PAL112: B04_0 Position */
+#define LCD_PAL112_B04_0_Msk (0x1fUL << LCD_PAL112_B04_0_Pos) /*!< LCD PAL112: B04_0 Mask */
+#define LCD_PAL112_I0_Pos 15 /*!< LCD PAL112: I0 Position */
+#define LCD_PAL112_I0_Msk (0x01UL << LCD_PAL112_I0_Pos) /*!< LCD PAL112: I0 Mask */
+#define LCD_PAL112_R14_0_Pos 16 /*!< LCD PAL112: R14_0 Position */
+#define LCD_PAL112_R14_0_Msk (0x1fUL << LCD_PAL112_R14_0_Pos) /*!< LCD PAL112: R14_0 Mask */
+#define LCD_PAL112_G14_0_Pos 21 /*!< LCD PAL112: G14_0 Position */
+#define LCD_PAL112_G14_0_Msk (0x1fUL << LCD_PAL112_G14_0_Pos) /*!< LCD PAL112: G14_0 Mask */
+#define LCD_PAL112_B14_0_Pos 26 /*!< LCD PAL112: B14_0 Position */
+#define LCD_PAL112_B14_0_Msk (0x1fUL << LCD_PAL112_B14_0_Pos) /*!< LCD PAL112: B14_0 Mask */
+#define LCD_PAL112_I1_Pos 31 /*!< LCD PAL112: I1 Position */
+#define LCD_PAL112_I1_Msk (0x01UL << LCD_PAL112_I1_Pos) /*!< LCD PAL112: I1 Mask */
+
+// --------------------------------------- LCD_PAL113 -------------------------------------------
+#define LCD_PAL113_R04_0_Pos 0 /*!< LCD PAL113: R04_0 Position */
+#define LCD_PAL113_R04_0_Msk (0x1fUL << LCD_PAL113_R04_0_Pos) /*!< LCD PAL113: R04_0 Mask */
+#define LCD_PAL113_G04_0_Pos 5 /*!< LCD PAL113: G04_0 Position */
+#define LCD_PAL113_G04_0_Msk (0x1fUL << LCD_PAL113_G04_0_Pos) /*!< LCD PAL113: G04_0 Mask */
+#define LCD_PAL113_B04_0_Pos 10 /*!< LCD PAL113: B04_0 Position */
+#define LCD_PAL113_B04_0_Msk (0x1fUL << LCD_PAL113_B04_0_Pos) /*!< LCD PAL113: B04_0 Mask */
+#define LCD_PAL113_I0_Pos 15 /*!< LCD PAL113: I0 Position */
+#define LCD_PAL113_I0_Msk (0x01UL << LCD_PAL113_I0_Pos) /*!< LCD PAL113: I0 Mask */
+#define LCD_PAL113_R14_0_Pos 16 /*!< LCD PAL113: R14_0 Position */
+#define LCD_PAL113_R14_0_Msk (0x1fUL << LCD_PAL113_R14_0_Pos) /*!< LCD PAL113: R14_0 Mask */
+#define LCD_PAL113_G14_0_Pos 21 /*!< LCD PAL113: G14_0 Position */
+#define LCD_PAL113_G14_0_Msk (0x1fUL << LCD_PAL113_G14_0_Pos) /*!< LCD PAL113: G14_0 Mask */
+#define LCD_PAL113_B14_0_Pos 26 /*!< LCD PAL113: B14_0 Position */
+#define LCD_PAL113_B14_0_Msk (0x1fUL << LCD_PAL113_B14_0_Pos) /*!< LCD PAL113: B14_0 Mask */
+#define LCD_PAL113_I1_Pos 31 /*!< LCD PAL113: I1 Position */
+#define LCD_PAL113_I1_Msk (0x01UL << LCD_PAL113_I1_Pos) /*!< LCD PAL113: I1 Mask */
+
+// --------------------------------------- LCD_PAL114 -------------------------------------------
+#define LCD_PAL114_R04_0_Pos 0 /*!< LCD PAL114: R04_0 Position */
+#define LCD_PAL114_R04_0_Msk (0x1fUL << LCD_PAL114_R04_0_Pos) /*!< LCD PAL114: R04_0 Mask */
+#define LCD_PAL114_G04_0_Pos 5 /*!< LCD PAL114: G04_0 Position */
+#define LCD_PAL114_G04_0_Msk (0x1fUL << LCD_PAL114_G04_0_Pos) /*!< LCD PAL114: G04_0 Mask */
+#define LCD_PAL114_B04_0_Pos 10 /*!< LCD PAL114: B04_0 Position */
+#define LCD_PAL114_B04_0_Msk (0x1fUL << LCD_PAL114_B04_0_Pos) /*!< LCD PAL114: B04_0 Mask */
+#define LCD_PAL114_I0_Pos 15 /*!< LCD PAL114: I0 Position */
+#define LCD_PAL114_I0_Msk (0x01UL << LCD_PAL114_I0_Pos) /*!< LCD PAL114: I0 Mask */
+#define LCD_PAL114_R14_0_Pos 16 /*!< LCD PAL114: R14_0 Position */
+#define LCD_PAL114_R14_0_Msk (0x1fUL << LCD_PAL114_R14_0_Pos) /*!< LCD PAL114: R14_0 Mask */
+#define LCD_PAL114_G14_0_Pos 21 /*!< LCD PAL114: G14_0 Position */
+#define LCD_PAL114_G14_0_Msk (0x1fUL << LCD_PAL114_G14_0_Pos) /*!< LCD PAL114: G14_0 Mask */
+#define LCD_PAL114_B14_0_Pos 26 /*!< LCD PAL114: B14_0 Position */
+#define LCD_PAL114_B14_0_Msk (0x1fUL << LCD_PAL114_B14_0_Pos) /*!< LCD PAL114: B14_0 Mask */
+#define LCD_PAL114_I1_Pos 31 /*!< LCD PAL114: I1 Position */
+#define LCD_PAL114_I1_Msk (0x01UL << LCD_PAL114_I1_Pos) /*!< LCD PAL114: I1 Mask */
+
+// --------------------------------------- LCD_PAL115 -------------------------------------------
+#define LCD_PAL115_R04_0_Pos 0 /*!< LCD PAL115: R04_0 Position */
+#define LCD_PAL115_R04_0_Msk (0x1fUL << LCD_PAL115_R04_0_Pos) /*!< LCD PAL115: R04_0 Mask */
+#define LCD_PAL115_G04_0_Pos 5 /*!< LCD PAL115: G04_0 Position */
+#define LCD_PAL115_G04_0_Msk (0x1fUL << LCD_PAL115_G04_0_Pos) /*!< LCD PAL115: G04_0 Mask */
+#define LCD_PAL115_B04_0_Pos 10 /*!< LCD PAL115: B04_0 Position */
+#define LCD_PAL115_B04_0_Msk (0x1fUL << LCD_PAL115_B04_0_Pos) /*!< LCD PAL115: B04_0 Mask */
+#define LCD_PAL115_I0_Pos 15 /*!< LCD PAL115: I0 Position */
+#define LCD_PAL115_I0_Msk (0x01UL << LCD_PAL115_I0_Pos) /*!< LCD PAL115: I0 Mask */
+#define LCD_PAL115_R14_0_Pos 16 /*!< LCD PAL115: R14_0 Position */
+#define LCD_PAL115_R14_0_Msk (0x1fUL << LCD_PAL115_R14_0_Pos) /*!< LCD PAL115: R14_0 Mask */
+#define LCD_PAL115_G14_0_Pos 21 /*!< LCD PAL115: G14_0 Position */
+#define LCD_PAL115_G14_0_Msk (0x1fUL << LCD_PAL115_G14_0_Pos) /*!< LCD PAL115: G14_0 Mask */
+#define LCD_PAL115_B14_0_Pos 26 /*!< LCD PAL115: B14_0 Position */
+#define LCD_PAL115_B14_0_Msk (0x1fUL << LCD_PAL115_B14_0_Pos) /*!< LCD PAL115: B14_0 Mask */
+#define LCD_PAL115_I1_Pos 31 /*!< LCD PAL115: I1 Position */
+#define LCD_PAL115_I1_Msk (0x01UL << LCD_PAL115_I1_Pos) /*!< LCD PAL115: I1 Mask */
+
+// --------------------------------------- LCD_PAL116 -------------------------------------------
+#define LCD_PAL116_R04_0_Pos 0 /*!< LCD PAL116: R04_0 Position */
+#define LCD_PAL116_R04_0_Msk (0x1fUL << LCD_PAL116_R04_0_Pos) /*!< LCD PAL116: R04_0 Mask */
+#define LCD_PAL116_G04_0_Pos 5 /*!< LCD PAL116: G04_0 Position */
+#define LCD_PAL116_G04_0_Msk (0x1fUL << LCD_PAL116_G04_0_Pos) /*!< LCD PAL116: G04_0 Mask */
+#define LCD_PAL116_B04_0_Pos 10 /*!< LCD PAL116: B04_0 Position */
+#define LCD_PAL116_B04_0_Msk (0x1fUL << LCD_PAL116_B04_0_Pos) /*!< LCD PAL116: B04_0 Mask */
+#define LCD_PAL116_I0_Pos 15 /*!< LCD PAL116: I0 Position */
+#define LCD_PAL116_I0_Msk (0x01UL << LCD_PAL116_I0_Pos) /*!< LCD PAL116: I0 Mask */
+#define LCD_PAL116_R14_0_Pos 16 /*!< LCD PAL116: R14_0 Position */
+#define LCD_PAL116_R14_0_Msk (0x1fUL << LCD_PAL116_R14_0_Pos) /*!< LCD PAL116: R14_0 Mask */
+#define LCD_PAL116_G14_0_Pos 21 /*!< LCD PAL116: G14_0 Position */
+#define LCD_PAL116_G14_0_Msk (0x1fUL << LCD_PAL116_G14_0_Pos) /*!< LCD PAL116: G14_0 Mask */
+#define LCD_PAL116_B14_0_Pos 26 /*!< LCD PAL116: B14_0 Position */
+#define LCD_PAL116_B14_0_Msk (0x1fUL << LCD_PAL116_B14_0_Pos) /*!< LCD PAL116: B14_0 Mask */
+#define LCD_PAL116_I1_Pos 31 /*!< LCD PAL116: I1 Position */
+#define LCD_PAL116_I1_Msk (0x01UL << LCD_PAL116_I1_Pos) /*!< LCD PAL116: I1 Mask */
+
+// --------------------------------------- LCD_PAL117 -------------------------------------------
+#define LCD_PAL117_R04_0_Pos 0 /*!< LCD PAL117: R04_0 Position */
+#define LCD_PAL117_R04_0_Msk (0x1fUL << LCD_PAL117_R04_0_Pos) /*!< LCD PAL117: R04_0 Mask */
+#define LCD_PAL117_G04_0_Pos 5 /*!< LCD PAL117: G04_0 Position */
+#define LCD_PAL117_G04_0_Msk (0x1fUL << LCD_PAL117_G04_0_Pos) /*!< LCD PAL117: G04_0 Mask */
+#define LCD_PAL117_B04_0_Pos 10 /*!< LCD PAL117: B04_0 Position */
+#define LCD_PAL117_B04_0_Msk (0x1fUL << LCD_PAL117_B04_0_Pos) /*!< LCD PAL117: B04_0 Mask */
+#define LCD_PAL117_I0_Pos 15 /*!< LCD PAL117: I0 Position */
+#define LCD_PAL117_I0_Msk (0x01UL << LCD_PAL117_I0_Pos) /*!< LCD PAL117: I0 Mask */
+#define LCD_PAL117_R14_0_Pos 16 /*!< LCD PAL117: R14_0 Position */
+#define LCD_PAL117_R14_0_Msk (0x1fUL << LCD_PAL117_R14_0_Pos) /*!< LCD PAL117: R14_0 Mask */
+#define LCD_PAL117_G14_0_Pos 21 /*!< LCD PAL117: G14_0 Position */
+#define LCD_PAL117_G14_0_Msk (0x1fUL << LCD_PAL117_G14_0_Pos) /*!< LCD PAL117: G14_0 Mask */
+#define LCD_PAL117_B14_0_Pos 26 /*!< LCD PAL117: B14_0 Position */
+#define LCD_PAL117_B14_0_Msk (0x1fUL << LCD_PAL117_B14_0_Pos) /*!< LCD PAL117: B14_0 Mask */
+#define LCD_PAL117_I1_Pos 31 /*!< LCD PAL117: I1 Position */
+#define LCD_PAL117_I1_Msk (0x01UL << LCD_PAL117_I1_Pos) /*!< LCD PAL117: I1 Mask */
+
+// --------------------------------------- LCD_PAL118 -------------------------------------------
+#define LCD_PAL118_R04_0_Pos 0 /*!< LCD PAL118: R04_0 Position */
+#define LCD_PAL118_R04_0_Msk (0x1fUL << LCD_PAL118_R04_0_Pos) /*!< LCD PAL118: R04_0 Mask */
+#define LCD_PAL118_G04_0_Pos 5 /*!< LCD PAL118: G04_0 Position */
+#define LCD_PAL118_G04_0_Msk (0x1fUL << LCD_PAL118_G04_0_Pos) /*!< LCD PAL118: G04_0 Mask */
+#define LCD_PAL118_B04_0_Pos 10 /*!< LCD PAL118: B04_0 Position */
+#define LCD_PAL118_B04_0_Msk (0x1fUL << LCD_PAL118_B04_0_Pos) /*!< LCD PAL118: B04_0 Mask */
+#define LCD_PAL118_I0_Pos 15 /*!< LCD PAL118: I0 Position */
+#define LCD_PAL118_I0_Msk (0x01UL << LCD_PAL118_I0_Pos) /*!< LCD PAL118: I0 Mask */
+#define LCD_PAL118_R14_0_Pos 16 /*!< LCD PAL118: R14_0 Position */
+#define LCD_PAL118_R14_0_Msk (0x1fUL << LCD_PAL118_R14_0_Pos) /*!< LCD PAL118: R14_0 Mask */
+#define LCD_PAL118_G14_0_Pos 21 /*!< LCD PAL118: G14_0 Position */
+#define LCD_PAL118_G14_0_Msk (0x1fUL << LCD_PAL118_G14_0_Pos) /*!< LCD PAL118: G14_0 Mask */
+#define LCD_PAL118_B14_0_Pos 26 /*!< LCD PAL118: B14_0 Position */
+#define LCD_PAL118_B14_0_Msk (0x1fUL << LCD_PAL118_B14_0_Pos) /*!< LCD PAL118: B14_0 Mask */
+#define LCD_PAL118_I1_Pos 31 /*!< LCD PAL118: I1 Position */
+#define LCD_PAL118_I1_Msk (0x01UL << LCD_PAL118_I1_Pos) /*!< LCD PAL118: I1 Mask */
+
+// --------------------------------------- LCD_PAL119 -------------------------------------------
+#define LCD_PAL119_R04_0_Pos 0 /*!< LCD PAL119: R04_0 Position */
+#define LCD_PAL119_R04_0_Msk (0x1fUL << LCD_PAL119_R04_0_Pos) /*!< LCD PAL119: R04_0 Mask */
+#define LCD_PAL119_G04_0_Pos 5 /*!< LCD PAL119: G04_0 Position */
+#define LCD_PAL119_G04_0_Msk (0x1fUL << LCD_PAL119_G04_0_Pos) /*!< LCD PAL119: G04_0 Mask */
+#define LCD_PAL119_B04_0_Pos 10 /*!< LCD PAL119: B04_0 Position */
+#define LCD_PAL119_B04_0_Msk (0x1fUL << LCD_PAL119_B04_0_Pos) /*!< LCD PAL119: B04_0 Mask */
+#define LCD_PAL119_I0_Pos 15 /*!< LCD PAL119: I0 Position */
+#define LCD_PAL119_I0_Msk (0x01UL << LCD_PAL119_I0_Pos) /*!< LCD PAL119: I0 Mask */
+#define LCD_PAL119_R14_0_Pos 16 /*!< LCD PAL119: R14_0 Position */
+#define LCD_PAL119_R14_0_Msk (0x1fUL << LCD_PAL119_R14_0_Pos) /*!< LCD PAL119: R14_0 Mask */
+#define LCD_PAL119_G14_0_Pos 21 /*!< LCD PAL119: G14_0 Position */
+#define LCD_PAL119_G14_0_Msk (0x1fUL << LCD_PAL119_G14_0_Pos) /*!< LCD PAL119: G14_0 Mask */
+#define LCD_PAL119_B14_0_Pos 26 /*!< LCD PAL119: B14_0 Position */
+#define LCD_PAL119_B14_0_Msk (0x1fUL << LCD_PAL119_B14_0_Pos) /*!< LCD PAL119: B14_0 Mask */
+#define LCD_PAL119_I1_Pos 31 /*!< LCD PAL119: I1 Position */
+#define LCD_PAL119_I1_Msk (0x01UL << LCD_PAL119_I1_Pos) /*!< LCD PAL119: I1 Mask */
+
+// --------------------------------------- LCD_PAL120 -------------------------------------------
+#define LCD_PAL120_R04_0_Pos 0 /*!< LCD PAL120: R04_0 Position */
+#define LCD_PAL120_R04_0_Msk (0x1fUL << LCD_PAL120_R04_0_Pos) /*!< LCD PAL120: R04_0 Mask */
+#define LCD_PAL120_G04_0_Pos 5 /*!< LCD PAL120: G04_0 Position */
+#define LCD_PAL120_G04_0_Msk (0x1fUL << LCD_PAL120_G04_0_Pos) /*!< LCD PAL120: G04_0 Mask */
+#define LCD_PAL120_B04_0_Pos 10 /*!< LCD PAL120: B04_0 Position */
+#define LCD_PAL120_B04_0_Msk (0x1fUL << LCD_PAL120_B04_0_Pos) /*!< LCD PAL120: B04_0 Mask */
+#define LCD_PAL120_I0_Pos 15 /*!< LCD PAL120: I0 Position */
+#define LCD_PAL120_I0_Msk (0x01UL << LCD_PAL120_I0_Pos) /*!< LCD PAL120: I0 Mask */
+#define LCD_PAL120_R14_0_Pos 16 /*!< LCD PAL120: R14_0 Position */
+#define LCD_PAL120_R14_0_Msk (0x1fUL << LCD_PAL120_R14_0_Pos) /*!< LCD PAL120: R14_0 Mask */
+#define LCD_PAL120_G14_0_Pos 21 /*!< LCD PAL120: G14_0 Position */
+#define LCD_PAL120_G14_0_Msk (0x1fUL << LCD_PAL120_G14_0_Pos) /*!< LCD PAL120: G14_0 Mask */
+#define LCD_PAL120_B14_0_Pos 26 /*!< LCD PAL120: B14_0 Position */
+#define LCD_PAL120_B14_0_Msk (0x1fUL << LCD_PAL120_B14_0_Pos) /*!< LCD PAL120: B14_0 Mask */
+#define LCD_PAL120_I1_Pos 31 /*!< LCD PAL120: I1 Position */
+#define LCD_PAL120_I1_Msk (0x01UL << LCD_PAL120_I1_Pos) /*!< LCD PAL120: I1 Mask */
+
+// --------------------------------------- LCD_PAL121 -------------------------------------------
+#define LCD_PAL121_R04_0_Pos 0 /*!< LCD PAL121: R04_0 Position */
+#define LCD_PAL121_R04_0_Msk (0x1fUL << LCD_PAL121_R04_0_Pos) /*!< LCD PAL121: R04_0 Mask */
+#define LCD_PAL121_G04_0_Pos 5 /*!< LCD PAL121: G04_0 Position */
+#define LCD_PAL121_G04_0_Msk (0x1fUL << LCD_PAL121_G04_0_Pos) /*!< LCD PAL121: G04_0 Mask */
+#define LCD_PAL121_B04_0_Pos 10 /*!< LCD PAL121: B04_0 Position */
+#define LCD_PAL121_B04_0_Msk (0x1fUL << LCD_PAL121_B04_0_Pos) /*!< LCD PAL121: B04_0 Mask */
+#define LCD_PAL121_I0_Pos 15 /*!< LCD PAL121: I0 Position */
+#define LCD_PAL121_I0_Msk (0x01UL << LCD_PAL121_I0_Pos) /*!< LCD PAL121: I0 Mask */
+#define LCD_PAL121_R14_0_Pos 16 /*!< LCD PAL121: R14_0 Position */
+#define LCD_PAL121_R14_0_Msk (0x1fUL << LCD_PAL121_R14_0_Pos) /*!< LCD PAL121: R14_0 Mask */
+#define LCD_PAL121_G14_0_Pos 21 /*!< LCD PAL121: G14_0 Position */
+#define LCD_PAL121_G14_0_Msk (0x1fUL << LCD_PAL121_G14_0_Pos) /*!< LCD PAL121: G14_0 Mask */
+#define LCD_PAL121_B14_0_Pos 26 /*!< LCD PAL121: B14_0 Position */
+#define LCD_PAL121_B14_0_Msk (0x1fUL << LCD_PAL121_B14_0_Pos) /*!< LCD PAL121: B14_0 Mask */
+#define LCD_PAL121_I1_Pos 31 /*!< LCD PAL121: I1 Position */
+#define LCD_PAL121_I1_Msk (0x01UL << LCD_PAL121_I1_Pos) /*!< LCD PAL121: I1 Mask */
+
+// --------------------------------------- LCD_PAL122 -------------------------------------------
+#define LCD_PAL122_R04_0_Pos 0 /*!< LCD PAL122: R04_0 Position */
+#define LCD_PAL122_R04_0_Msk (0x1fUL << LCD_PAL122_R04_0_Pos) /*!< LCD PAL122: R04_0 Mask */
+#define LCD_PAL122_G04_0_Pos 5 /*!< LCD PAL122: G04_0 Position */
+#define LCD_PAL122_G04_0_Msk (0x1fUL << LCD_PAL122_G04_0_Pos) /*!< LCD PAL122: G04_0 Mask */
+#define LCD_PAL122_B04_0_Pos 10 /*!< LCD PAL122: B04_0 Position */
+#define LCD_PAL122_B04_0_Msk (0x1fUL << LCD_PAL122_B04_0_Pos) /*!< LCD PAL122: B04_0 Mask */
+#define LCD_PAL122_I0_Pos 15 /*!< LCD PAL122: I0 Position */
+#define LCD_PAL122_I0_Msk (0x01UL << LCD_PAL122_I0_Pos) /*!< LCD PAL122: I0 Mask */
+#define LCD_PAL122_R14_0_Pos 16 /*!< LCD PAL122: R14_0 Position */
+#define LCD_PAL122_R14_0_Msk (0x1fUL << LCD_PAL122_R14_0_Pos) /*!< LCD PAL122: R14_0 Mask */
+#define LCD_PAL122_G14_0_Pos 21 /*!< LCD PAL122: G14_0 Position */
+#define LCD_PAL122_G14_0_Msk (0x1fUL << LCD_PAL122_G14_0_Pos) /*!< LCD PAL122: G14_0 Mask */
+#define LCD_PAL122_B14_0_Pos 26 /*!< LCD PAL122: B14_0 Position */
+#define LCD_PAL122_B14_0_Msk (0x1fUL << LCD_PAL122_B14_0_Pos) /*!< LCD PAL122: B14_0 Mask */
+#define LCD_PAL122_I1_Pos 31 /*!< LCD PAL122: I1 Position */
+#define LCD_PAL122_I1_Msk (0x01UL << LCD_PAL122_I1_Pos) /*!< LCD PAL122: I1 Mask */
+
+// --------------------------------------- LCD_PAL123 -------------------------------------------
+#define LCD_PAL123_R04_0_Pos 0 /*!< LCD PAL123: R04_0 Position */
+#define LCD_PAL123_R04_0_Msk (0x1fUL << LCD_PAL123_R04_0_Pos) /*!< LCD PAL123: R04_0 Mask */
+#define LCD_PAL123_G04_0_Pos 5 /*!< LCD PAL123: G04_0 Position */
+#define LCD_PAL123_G04_0_Msk (0x1fUL << LCD_PAL123_G04_0_Pos) /*!< LCD PAL123: G04_0 Mask */
+#define LCD_PAL123_B04_0_Pos 10 /*!< LCD PAL123: B04_0 Position */
+#define LCD_PAL123_B04_0_Msk (0x1fUL << LCD_PAL123_B04_0_Pos) /*!< LCD PAL123: B04_0 Mask */
+#define LCD_PAL123_I0_Pos 15 /*!< LCD PAL123: I0 Position */
+#define LCD_PAL123_I0_Msk (0x01UL << LCD_PAL123_I0_Pos) /*!< LCD PAL123: I0 Mask */
+#define LCD_PAL123_R14_0_Pos 16 /*!< LCD PAL123: R14_0 Position */
+#define LCD_PAL123_R14_0_Msk (0x1fUL << LCD_PAL123_R14_0_Pos) /*!< LCD PAL123: R14_0 Mask */
+#define LCD_PAL123_G14_0_Pos 21 /*!< LCD PAL123: G14_0 Position */
+#define LCD_PAL123_G14_0_Msk (0x1fUL << LCD_PAL123_G14_0_Pos) /*!< LCD PAL123: G14_0 Mask */
+#define LCD_PAL123_B14_0_Pos 26 /*!< LCD PAL123: B14_0 Position */
+#define LCD_PAL123_B14_0_Msk (0x1fUL << LCD_PAL123_B14_0_Pos) /*!< LCD PAL123: B14_0 Mask */
+#define LCD_PAL123_I1_Pos 31 /*!< LCD PAL123: I1 Position */
+#define LCD_PAL123_I1_Msk (0x01UL << LCD_PAL123_I1_Pos) /*!< LCD PAL123: I1 Mask */
+
+// --------------------------------------- LCD_PAL124 -------------------------------------------
+#define LCD_PAL124_R04_0_Pos 0 /*!< LCD PAL124: R04_0 Position */
+#define LCD_PAL124_R04_0_Msk (0x1fUL << LCD_PAL124_R04_0_Pos) /*!< LCD PAL124: R04_0 Mask */
+#define LCD_PAL124_G04_0_Pos 5 /*!< LCD PAL124: G04_0 Position */
+#define LCD_PAL124_G04_0_Msk (0x1fUL << LCD_PAL124_G04_0_Pos) /*!< LCD PAL124: G04_0 Mask */
+#define LCD_PAL124_B04_0_Pos 10 /*!< LCD PAL124: B04_0 Position */
+#define LCD_PAL124_B04_0_Msk (0x1fUL << LCD_PAL124_B04_0_Pos) /*!< LCD PAL124: B04_0 Mask */
+#define LCD_PAL124_I0_Pos 15 /*!< LCD PAL124: I0 Position */
+#define LCD_PAL124_I0_Msk (0x01UL << LCD_PAL124_I0_Pos) /*!< LCD PAL124: I0 Mask */
+#define LCD_PAL124_R14_0_Pos 16 /*!< LCD PAL124: R14_0 Position */
+#define LCD_PAL124_R14_0_Msk (0x1fUL << LCD_PAL124_R14_0_Pos) /*!< LCD PAL124: R14_0 Mask */
+#define LCD_PAL124_G14_0_Pos 21 /*!< LCD PAL124: G14_0 Position */
+#define LCD_PAL124_G14_0_Msk (0x1fUL << LCD_PAL124_G14_0_Pos) /*!< LCD PAL124: G14_0 Mask */
+#define LCD_PAL124_B14_0_Pos 26 /*!< LCD PAL124: B14_0 Position */
+#define LCD_PAL124_B14_0_Msk (0x1fUL << LCD_PAL124_B14_0_Pos) /*!< LCD PAL124: B14_0 Mask */
+#define LCD_PAL124_I1_Pos 31 /*!< LCD PAL124: I1 Position */
+#define LCD_PAL124_I1_Msk (0x01UL << LCD_PAL124_I1_Pos) /*!< LCD PAL124: I1 Mask */
+
+// --------------------------------------- LCD_PAL125 -------------------------------------------
+#define LCD_PAL125_R04_0_Pos 0 /*!< LCD PAL125: R04_0 Position */
+#define LCD_PAL125_R04_0_Msk (0x1fUL << LCD_PAL125_R04_0_Pos) /*!< LCD PAL125: R04_0 Mask */
+#define LCD_PAL125_G04_0_Pos 5 /*!< LCD PAL125: G04_0 Position */
+#define LCD_PAL125_G04_0_Msk (0x1fUL << LCD_PAL125_G04_0_Pos) /*!< LCD PAL125: G04_0 Mask */
+#define LCD_PAL125_B04_0_Pos 10 /*!< LCD PAL125: B04_0 Position */
+#define LCD_PAL125_B04_0_Msk (0x1fUL << LCD_PAL125_B04_0_Pos) /*!< LCD PAL125: B04_0 Mask */
+#define LCD_PAL125_I0_Pos 15 /*!< LCD PAL125: I0 Position */
+#define LCD_PAL125_I0_Msk (0x01UL << LCD_PAL125_I0_Pos) /*!< LCD PAL125: I0 Mask */
+#define LCD_PAL125_R14_0_Pos 16 /*!< LCD PAL125: R14_0 Position */
+#define LCD_PAL125_R14_0_Msk (0x1fUL << LCD_PAL125_R14_0_Pos) /*!< LCD PAL125: R14_0 Mask */
+#define LCD_PAL125_G14_0_Pos 21 /*!< LCD PAL125: G14_0 Position */
+#define LCD_PAL125_G14_0_Msk (0x1fUL << LCD_PAL125_G14_0_Pos) /*!< LCD PAL125: G14_0 Mask */
+#define LCD_PAL125_B14_0_Pos 26 /*!< LCD PAL125: B14_0 Position */
+#define LCD_PAL125_B14_0_Msk (0x1fUL << LCD_PAL125_B14_0_Pos) /*!< LCD PAL125: B14_0 Mask */
+#define LCD_PAL125_I1_Pos 31 /*!< LCD PAL125: I1 Position */
+#define LCD_PAL125_I1_Msk (0x01UL << LCD_PAL125_I1_Pos) /*!< LCD PAL125: I1 Mask */
+
+// --------------------------------------- LCD_PAL126 -------------------------------------------
+#define LCD_PAL126_R04_0_Pos 0 /*!< LCD PAL126: R04_0 Position */
+#define LCD_PAL126_R04_0_Msk (0x1fUL << LCD_PAL126_R04_0_Pos) /*!< LCD PAL126: R04_0 Mask */
+#define LCD_PAL126_G04_0_Pos 5 /*!< LCD PAL126: G04_0 Position */
+#define LCD_PAL126_G04_0_Msk (0x1fUL << LCD_PAL126_G04_0_Pos) /*!< LCD PAL126: G04_0 Mask */
+#define LCD_PAL126_B04_0_Pos 10 /*!< LCD PAL126: B04_0 Position */
+#define LCD_PAL126_B04_0_Msk (0x1fUL << LCD_PAL126_B04_0_Pos) /*!< LCD PAL126: B04_0 Mask */
+#define LCD_PAL126_I0_Pos 15 /*!< LCD PAL126: I0 Position */
+#define LCD_PAL126_I0_Msk (0x01UL << LCD_PAL126_I0_Pos) /*!< LCD PAL126: I0 Mask */
+#define LCD_PAL126_R14_0_Pos 16 /*!< LCD PAL126: R14_0 Position */
+#define LCD_PAL126_R14_0_Msk (0x1fUL << LCD_PAL126_R14_0_Pos) /*!< LCD PAL126: R14_0 Mask */
+#define LCD_PAL126_G14_0_Pos 21 /*!< LCD PAL126: G14_0 Position */
+#define LCD_PAL126_G14_0_Msk (0x1fUL << LCD_PAL126_G14_0_Pos) /*!< LCD PAL126: G14_0 Mask */
+#define LCD_PAL126_B14_0_Pos 26 /*!< LCD PAL126: B14_0 Position */
+#define LCD_PAL126_B14_0_Msk (0x1fUL << LCD_PAL126_B14_0_Pos) /*!< LCD PAL126: B14_0 Mask */
+#define LCD_PAL126_I1_Pos 31 /*!< LCD PAL126: I1 Position */
+#define LCD_PAL126_I1_Msk (0x01UL << LCD_PAL126_I1_Pos) /*!< LCD PAL126: I1 Mask */
+
+// --------------------------------------- LCD_PAL127 -------------------------------------------
+#define LCD_PAL127_R04_0_Pos 0 /*!< LCD PAL127: R04_0 Position */
+#define LCD_PAL127_R04_0_Msk (0x1fUL << LCD_PAL127_R04_0_Pos) /*!< LCD PAL127: R04_0 Mask */
+#define LCD_PAL127_G04_0_Pos 5 /*!< LCD PAL127: G04_0 Position */
+#define LCD_PAL127_G04_0_Msk (0x1fUL << LCD_PAL127_G04_0_Pos) /*!< LCD PAL127: G04_0 Mask */
+#define LCD_PAL127_B04_0_Pos 10 /*!< LCD PAL127: B04_0 Position */
+#define LCD_PAL127_B04_0_Msk (0x1fUL << LCD_PAL127_B04_0_Pos) /*!< LCD PAL127: B04_0 Mask */
+#define LCD_PAL127_I0_Pos 15 /*!< LCD PAL127: I0 Position */
+#define LCD_PAL127_I0_Msk (0x01UL << LCD_PAL127_I0_Pos) /*!< LCD PAL127: I0 Mask */
+#define LCD_PAL127_R14_0_Pos 16 /*!< LCD PAL127: R14_0 Position */
+#define LCD_PAL127_R14_0_Msk (0x1fUL << LCD_PAL127_R14_0_Pos) /*!< LCD PAL127: R14_0 Mask */
+#define LCD_PAL127_G14_0_Pos 21 /*!< LCD PAL127: G14_0 Position */
+#define LCD_PAL127_G14_0_Msk (0x1fUL << LCD_PAL127_G14_0_Pos) /*!< LCD PAL127: G14_0 Mask */
+#define LCD_PAL127_B14_0_Pos 26 /*!< LCD PAL127: B14_0 Position */
+#define LCD_PAL127_B14_0_Msk (0x1fUL << LCD_PAL127_B14_0_Pos) /*!< LCD PAL127: B14_0 Mask */
+#define LCD_PAL127_I1_Pos 31 /*!< LCD PAL127: I1 Position */
+#define LCD_PAL127_I1_Msk (0x01UL << LCD_PAL127_I1_Pos) /*!< LCD PAL127: I1 Mask */
+
+// --------------------------------------- LCD_PAL128 -------------------------------------------
+#define LCD_PAL128_R04_0_Pos 0 /*!< LCD PAL128: R04_0 Position */
+#define LCD_PAL128_R04_0_Msk (0x1fUL << LCD_PAL128_R04_0_Pos) /*!< LCD PAL128: R04_0 Mask */
+#define LCD_PAL128_G04_0_Pos 5 /*!< LCD PAL128: G04_0 Position */
+#define LCD_PAL128_G04_0_Msk (0x1fUL << LCD_PAL128_G04_0_Pos) /*!< LCD PAL128: G04_0 Mask */
+#define LCD_PAL128_B04_0_Pos 10 /*!< LCD PAL128: B04_0 Position */
+#define LCD_PAL128_B04_0_Msk (0x1fUL << LCD_PAL128_B04_0_Pos) /*!< LCD PAL128: B04_0 Mask */
+#define LCD_PAL128_I0_Pos 15 /*!< LCD PAL128: I0 Position */
+#define LCD_PAL128_I0_Msk (0x01UL << LCD_PAL128_I0_Pos) /*!< LCD PAL128: I0 Mask */
+#define LCD_PAL128_R14_0_Pos 16 /*!< LCD PAL128: R14_0 Position */
+#define LCD_PAL128_R14_0_Msk (0x1fUL << LCD_PAL128_R14_0_Pos) /*!< LCD PAL128: R14_0 Mask */
+#define LCD_PAL128_G14_0_Pos 21 /*!< LCD PAL128: G14_0 Position */
+#define LCD_PAL128_G14_0_Msk (0x1fUL << LCD_PAL128_G14_0_Pos) /*!< LCD PAL128: G14_0 Mask */
+#define LCD_PAL128_B14_0_Pos 26 /*!< LCD PAL128: B14_0 Position */
+#define LCD_PAL128_B14_0_Msk (0x1fUL << LCD_PAL128_B14_0_Pos) /*!< LCD PAL128: B14_0 Mask */
+#define LCD_PAL128_I1_Pos 31 /*!< LCD PAL128: I1 Position */
+#define LCD_PAL128_I1_Msk (0x01UL << LCD_PAL128_I1_Pos) /*!< LCD PAL128: I1 Mask */
+
+// --------------------------------------- LCD_PAL129 -------------------------------------------
+#define LCD_PAL129_R04_0_Pos 0 /*!< LCD PAL129: R04_0 Position */
+#define LCD_PAL129_R04_0_Msk (0x1fUL << LCD_PAL129_R04_0_Pos) /*!< LCD PAL129: R04_0 Mask */
+#define LCD_PAL129_G04_0_Pos 5 /*!< LCD PAL129: G04_0 Position */
+#define LCD_PAL129_G04_0_Msk (0x1fUL << LCD_PAL129_G04_0_Pos) /*!< LCD PAL129: G04_0 Mask */
+#define LCD_PAL129_B04_0_Pos 10 /*!< LCD PAL129: B04_0 Position */
+#define LCD_PAL129_B04_0_Msk (0x1fUL << LCD_PAL129_B04_0_Pos) /*!< LCD PAL129: B04_0 Mask */
+#define LCD_PAL129_I0_Pos 15 /*!< LCD PAL129: I0 Position */
+#define LCD_PAL129_I0_Msk (0x01UL << LCD_PAL129_I0_Pos) /*!< LCD PAL129: I0 Mask */
+#define LCD_PAL129_R14_0_Pos 16 /*!< LCD PAL129: R14_0 Position */
+#define LCD_PAL129_R14_0_Msk (0x1fUL << LCD_PAL129_R14_0_Pos) /*!< LCD PAL129: R14_0 Mask */
+#define LCD_PAL129_G14_0_Pos 21 /*!< LCD PAL129: G14_0 Position */
+#define LCD_PAL129_G14_0_Msk (0x1fUL << LCD_PAL129_G14_0_Pos) /*!< LCD PAL129: G14_0 Mask */
+#define LCD_PAL129_B14_0_Pos 26 /*!< LCD PAL129: B14_0 Position */
+#define LCD_PAL129_B14_0_Msk (0x1fUL << LCD_PAL129_B14_0_Pos) /*!< LCD PAL129: B14_0 Mask */
+#define LCD_PAL129_I1_Pos 31 /*!< LCD PAL129: I1 Position */
+#define LCD_PAL129_I1_Msk (0x01UL << LCD_PAL129_I1_Pos) /*!< LCD PAL129: I1 Mask */
+
+// --------------------------------------- LCD_PAL130 -------------------------------------------
+#define LCD_PAL130_R04_0_Pos 0 /*!< LCD PAL130: R04_0 Position */
+#define LCD_PAL130_R04_0_Msk (0x1fUL << LCD_PAL130_R04_0_Pos) /*!< LCD PAL130: R04_0 Mask */
+#define LCD_PAL130_G04_0_Pos 5 /*!< LCD PAL130: G04_0 Position */
+#define LCD_PAL130_G04_0_Msk (0x1fUL << LCD_PAL130_G04_0_Pos) /*!< LCD PAL130: G04_0 Mask */
+#define LCD_PAL130_B04_0_Pos 10 /*!< LCD PAL130: B04_0 Position */
+#define LCD_PAL130_B04_0_Msk (0x1fUL << LCD_PAL130_B04_0_Pos) /*!< LCD PAL130: B04_0 Mask */
+#define LCD_PAL130_I0_Pos 15 /*!< LCD PAL130: I0 Position */
+#define LCD_PAL130_I0_Msk (0x01UL << LCD_PAL130_I0_Pos) /*!< LCD PAL130: I0 Mask */
+#define LCD_PAL130_R14_0_Pos 16 /*!< LCD PAL130: R14_0 Position */
+#define LCD_PAL130_R14_0_Msk (0x1fUL << LCD_PAL130_R14_0_Pos) /*!< LCD PAL130: R14_0 Mask */
+#define LCD_PAL130_G14_0_Pos 21 /*!< LCD PAL130: G14_0 Position */
+#define LCD_PAL130_G14_0_Msk (0x1fUL << LCD_PAL130_G14_0_Pos) /*!< LCD PAL130: G14_0 Mask */
+#define LCD_PAL130_B14_0_Pos 26 /*!< LCD PAL130: B14_0 Position */
+#define LCD_PAL130_B14_0_Msk (0x1fUL << LCD_PAL130_B14_0_Pos) /*!< LCD PAL130: B14_0 Mask */
+#define LCD_PAL130_I1_Pos 31 /*!< LCD PAL130: I1 Position */
+#define LCD_PAL130_I1_Msk (0x01UL << LCD_PAL130_I1_Pos) /*!< LCD PAL130: I1 Mask */
+
+// --------------------------------------- LCD_PAL131 -------------------------------------------
+#define LCD_PAL131_R04_0_Pos 0 /*!< LCD PAL131: R04_0 Position */
+#define LCD_PAL131_R04_0_Msk (0x1fUL << LCD_PAL131_R04_0_Pos) /*!< LCD PAL131: R04_0 Mask */
+#define LCD_PAL131_G04_0_Pos 5 /*!< LCD PAL131: G04_0 Position */
+#define LCD_PAL131_G04_0_Msk (0x1fUL << LCD_PAL131_G04_0_Pos) /*!< LCD PAL131: G04_0 Mask */
+#define LCD_PAL131_B04_0_Pos 10 /*!< LCD PAL131: B04_0 Position */
+#define LCD_PAL131_B04_0_Msk (0x1fUL << LCD_PAL131_B04_0_Pos) /*!< LCD PAL131: B04_0 Mask */
+#define LCD_PAL131_I0_Pos 15 /*!< LCD PAL131: I0 Position */
+#define LCD_PAL131_I0_Msk (0x01UL << LCD_PAL131_I0_Pos) /*!< LCD PAL131: I0 Mask */
+#define LCD_PAL131_R14_0_Pos 16 /*!< LCD PAL131: R14_0 Position */
+#define LCD_PAL131_R14_0_Msk (0x1fUL << LCD_PAL131_R14_0_Pos) /*!< LCD PAL131: R14_0 Mask */
+#define LCD_PAL131_G14_0_Pos 21 /*!< LCD PAL131: G14_0 Position */
+#define LCD_PAL131_G14_0_Msk (0x1fUL << LCD_PAL131_G14_0_Pos) /*!< LCD PAL131: G14_0 Mask */
+#define LCD_PAL131_B14_0_Pos 26 /*!< LCD PAL131: B14_0 Position */
+#define LCD_PAL131_B14_0_Msk (0x1fUL << LCD_PAL131_B14_0_Pos) /*!< LCD PAL131: B14_0 Mask */
+#define LCD_PAL131_I1_Pos 31 /*!< LCD PAL131: I1 Position */
+#define LCD_PAL131_I1_Msk (0x01UL << LCD_PAL131_I1_Pos) /*!< LCD PAL131: I1 Mask */
+
+// --------------------------------------- LCD_PAL132 -------------------------------------------
+#define LCD_PAL132_R04_0_Pos 0 /*!< LCD PAL132: R04_0 Position */
+#define LCD_PAL132_R04_0_Msk (0x1fUL << LCD_PAL132_R04_0_Pos) /*!< LCD PAL132: R04_0 Mask */
+#define LCD_PAL132_G04_0_Pos 5 /*!< LCD PAL132: G04_0 Position */
+#define LCD_PAL132_G04_0_Msk (0x1fUL << LCD_PAL132_G04_0_Pos) /*!< LCD PAL132: G04_0 Mask */
+#define LCD_PAL132_B04_0_Pos 10 /*!< LCD PAL132: B04_0 Position */
+#define LCD_PAL132_B04_0_Msk (0x1fUL << LCD_PAL132_B04_0_Pos) /*!< LCD PAL132: B04_0 Mask */
+#define LCD_PAL132_I0_Pos 15 /*!< LCD PAL132: I0 Position */
+#define LCD_PAL132_I0_Msk (0x01UL << LCD_PAL132_I0_Pos) /*!< LCD PAL132: I0 Mask */
+#define LCD_PAL132_R14_0_Pos 16 /*!< LCD PAL132: R14_0 Position */
+#define LCD_PAL132_R14_0_Msk (0x1fUL << LCD_PAL132_R14_0_Pos) /*!< LCD PAL132: R14_0 Mask */
+#define LCD_PAL132_G14_0_Pos 21 /*!< LCD PAL132: G14_0 Position */
+#define LCD_PAL132_G14_0_Msk (0x1fUL << LCD_PAL132_G14_0_Pos) /*!< LCD PAL132: G14_0 Mask */
+#define LCD_PAL132_B14_0_Pos 26 /*!< LCD PAL132: B14_0 Position */
+#define LCD_PAL132_B14_0_Msk (0x1fUL << LCD_PAL132_B14_0_Pos) /*!< LCD PAL132: B14_0 Mask */
+#define LCD_PAL132_I1_Pos 31 /*!< LCD PAL132: I1 Position */
+#define LCD_PAL132_I1_Msk (0x01UL << LCD_PAL132_I1_Pos) /*!< LCD PAL132: I1 Mask */
+
+// --------------------------------------- LCD_PAL133 -------------------------------------------
+#define LCD_PAL133_R04_0_Pos 0 /*!< LCD PAL133: R04_0 Position */
+#define LCD_PAL133_R04_0_Msk (0x1fUL << LCD_PAL133_R04_0_Pos) /*!< LCD PAL133: R04_0 Mask */
+#define LCD_PAL133_G04_0_Pos 5 /*!< LCD PAL133: G04_0 Position */
+#define LCD_PAL133_G04_0_Msk (0x1fUL << LCD_PAL133_G04_0_Pos) /*!< LCD PAL133: G04_0 Mask */
+#define LCD_PAL133_B04_0_Pos 10 /*!< LCD PAL133: B04_0 Position */
+#define LCD_PAL133_B04_0_Msk (0x1fUL << LCD_PAL133_B04_0_Pos) /*!< LCD PAL133: B04_0 Mask */
+#define LCD_PAL133_I0_Pos 15 /*!< LCD PAL133: I0 Position */
+#define LCD_PAL133_I0_Msk (0x01UL << LCD_PAL133_I0_Pos) /*!< LCD PAL133: I0 Mask */
+#define LCD_PAL133_R14_0_Pos 16 /*!< LCD PAL133: R14_0 Position */
+#define LCD_PAL133_R14_0_Msk (0x1fUL << LCD_PAL133_R14_0_Pos) /*!< LCD PAL133: R14_0 Mask */
+#define LCD_PAL133_G14_0_Pos 21 /*!< LCD PAL133: G14_0 Position */
+#define LCD_PAL133_G14_0_Msk (0x1fUL << LCD_PAL133_G14_0_Pos) /*!< LCD PAL133: G14_0 Mask */
+#define LCD_PAL133_B14_0_Pos 26 /*!< LCD PAL133: B14_0 Position */
+#define LCD_PAL133_B14_0_Msk (0x1fUL << LCD_PAL133_B14_0_Pos) /*!< LCD PAL133: B14_0 Mask */
+#define LCD_PAL133_I1_Pos 31 /*!< LCD PAL133: I1 Position */
+#define LCD_PAL133_I1_Msk (0x01UL << LCD_PAL133_I1_Pos) /*!< LCD PAL133: I1 Mask */
+
+// --------------------------------------- LCD_PAL134 -------------------------------------------
+#define LCD_PAL134_R04_0_Pos 0 /*!< LCD PAL134: R04_0 Position */
+#define LCD_PAL134_R04_0_Msk (0x1fUL << LCD_PAL134_R04_0_Pos) /*!< LCD PAL134: R04_0 Mask */
+#define LCD_PAL134_G04_0_Pos 5 /*!< LCD PAL134: G04_0 Position */
+#define LCD_PAL134_G04_0_Msk (0x1fUL << LCD_PAL134_G04_0_Pos) /*!< LCD PAL134: G04_0 Mask */
+#define LCD_PAL134_B04_0_Pos 10 /*!< LCD PAL134: B04_0 Position */
+#define LCD_PAL134_B04_0_Msk (0x1fUL << LCD_PAL134_B04_0_Pos) /*!< LCD PAL134: B04_0 Mask */
+#define LCD_PAL134_I0_Pos 15 /*!< LCD PAL134: I0 Position */
+#define LCD_PAL134_I0_Msk (0x01UL << LCD_PAL134_I0_Pos) /*!< LCD PAL134: I0 Mask */
+#define LCD_PAL134_R14_0_Pos 16 /*!< LCD PAL134: R14_0 Position */
+#define LCD_PAL134_R14_0_Msk (0x1fUL << LCD_PAL134_R14_0_Pos) /*!< LCD PAL134: R14_0 Mask */
+#define LCD_PAL134_G14_0_Pos 21 /*!< LCD PAL134: G14_0 Position */
+#define LCD_PAL134_G14_0_Msk (0x1fUL << LCD_PAL134_G14_0_Pos) /*!< LCD PAL134: G14_0 Mask */
+#define LCD_PAL134_B14_0_Pos 26 /*!< LCD PAL134: B14_0 Position */
+#define LCD_PAL134_B14_0_Msk (0x1fUL << LCD_PAL134_B14_0_Pos) /*!< LCD PAL134: B14_0 Mask */
+#define LCD_PAL134_I1_Pos 31 /*!< LCD PAL134: I1 Position */
+#define LCD_PAL134_I1_Msk (0x01UL << LCD_PAL134_I1_Pos) /*!< LCD PAL134: I1 Mask */
+
+// --------------------------------------- LCD_PAL135 -------------------------------------------
+#define LCD_PAL135_R04_0_Pos 0 /*!< LCD PAL135: R04_0 Position */
+#define LCD_PAL135_R04_0_Msk (0x1fUL << LCD_PAL135_R04_0_Pos) /*!< LCD PAL135: R04_0 Mask */
+#define LCD_PAL135_G04_0_Pos 5 /*!< LCD PAL135: G04_0 Position */
+#define LCD_PAL135_G04_0_Msk (0x1fUL << LCD_PAL135_G04_0_Pos) /*!< LCD PAL135: G04_0 Mask */
+#define LCD_PAL135_B04_0_Pos 10 /*!< LCD PAL135: B04_0 Position */
+#define LCD_PAL135_B04_0_Msk (0x1fUL << LCD_PAL135_B04_0_Pos) /*!< LCD PAL135: B04_0 Mask */
+#define LCD_PAL135_I0_Pos 15 /*!< LCD PAL135: I0 Position */
+#define LCD_PAL135_I0_Msk (0x01UL << LCD_PAL135_I0_Pos) /*!< LCD PAL135: I0 Mask */
+#define LCD_PAL135_R14_0_Pos 16 /*!< LCD PAL135: R14_0 Position */
+#define LCD_PAL135_R14_0_Msk (0x1fUL << LCD_PAL135_R14_0_Pos) /*!< LCD PAL135: R14_0 Mask */
+#define LCD_PAL135_G14_0_Pos 21 /*!< LCD PAL135: G14_0 Position */
+#define LCD_PAL135_G14_0_Msk (0x1fUL << LCD_PAL135_G14_0_Pos) /*!< LCD PAL135: G14_0 Mask */
+#define LCD_PAL135_B14_0_Pos 26 /*!< LCD PAL135: B14_0 Position */
+#define LCD_PAL135_B14_0_Msk (0x1fUL << LCD_PAL135_B14_0_Pos) /*!< LCD PAL135: B14_0 Mask */
+#define LCD_PAL135_I1_Pos 31 /*!< LCD PAL135: I1 Position */
+#define LCD_PAL135_I1_Msk (0x01UL << LCD_PAL135_I1_Pos) /*!< LCD PAL135: I1 Mask */
+
+// --------------------------------------- LCD_PAL136 -------------------------------------------
+#define LCD_PAL136_R04_0_Pos 0 /*!< LCD PAL136: R04_0 Position */
+#define LCD_PAL136_R04_0_Msk (0x1fUL << LCD_PAL136_R04_0_Pos) /*!< LCD PAL136: R04_0 Mask */
+#define LCD_PAL136_G04_0_Pos 5 /*!< LCD PAL136: G04_0 Position */
+#define LCD_PAL136_G04_0_Msk (0x1fUL << LCD_PAL136_G04_0_Pos) /*!< LCD PAL136: G04_0 Mask */
+#define LCD_PAL136_B04_0_Pos 10 /*!< LCD PAL136: B04_0 Position */
+#define LCD_PAL136_B04_0_Msk (0x1fUL << LCD_PAL136_B04_0_Pos) /*!< LCD PAL136: B04_0 Mask */
+#define LCD_PAL136_I0_Pos 15 /*!< LCD PAL136: I0 Position */
+#define LCD_PAL136_I0_Msk (0x01UL << LCD_PAL136_I0_Pos) /*!< LCD PAL136: I0 Mask */
+#define LCD_PAL136_R14_0_Pos 16 /*!< LCD PAL136: R14_0 Position */
+#define LCD_PAL136_R14_0_Msk (0x1fUL << LCD_PAL136_R14_0_Pos) /*!< LCD PAL136: R14_0 Mask */
+#define LCD_PAL136_G14_0_Pos 21 /*!< LCD PAL136: G14_0 Position */
+#define LCD_PAL136_G14_0_Msk (0x1fUL << LCD_PAL136_G14_0_Pos) /*!< LCD PAL136: G14_0 Mask */
+#define LCD_PAL136_B14_0_Pos 26 /*!< LCD PAL136: B14_0 Position */
+#define LCD_PAL136_B14_0_Msk (0x1fUL << LCD_PAL136_B14_0_Pos) /*!< LCD PAL136: B14_0 Mask */
+#define LCD_PAL136_I1_Pos 31 /*!< LCD PAL136: I1 Position */
+#define LCD_PAL136_I1_Msk (0x01UL << LCD_PAL136_I1_Pos) /*!< LCD PAL136: I1 Mask */
+
+// --------------------------------------- LCD_PAL137 -------------------------------------------
+#define LCD_PAL137_R04_0_Pos 0 /*!< LCD PAL137: R04_0 Position */
+#define LCD_PAL137_R04_0_Msk (0x1fUL << LCD_PAL137_R04_0_Pos) /*!< LCD PAL137: R04_0 Mask */
+#define LCD_PAL137_G04_0_Pos 5 /*!< LCD PAL137: G04_0 Position */
+#define LCD_PAL137_G04_0_Msk (0x1fUL << LCD_PAL137_G04_0_Pos) /*!< LCD PAL137: G04_0 Mask */
+#define LCD_PAL137_B04_0_Pos 10 /*!< LCD PAL137: B04_0 Position */
+#define LCD_PAL137_B04_0_Msk (0x1fUL << LCD_PAL137_B04_0_Pos) /*!< LCD PAL137: B04_0 Mask */
+#define LCD_PAL137_I0_Pos 15 /*!< LCD PAL137: I0 Position */
+#define LCD_PAL137_I0_Msk (0x01UL << LCD_PAL137_I0_Pos) /*!< LCD PAL137: I0 Mask */
+#define LCD_PAL137_R14_0_Pos 16 /*!< LCD PAL137: R14_0 Position */
+#define LCD_PAL137_R14_0_Msk (0x1fUL << LCD_PAL137_R14_0_Pos) /*!< LCD PAL137: R14_0 Mask */
+#define LCD_PAL137_G14_0_Pos 21 /*!< LCD PAL137: G14_0 Position */
+#define LCD_PAL137_G14_0_Msk (0x1fUL << LCD_PAL137_G14_0_Pos) /*!< LCD PAL137: G14_0 Mask */
+#define LCD_PAL137_B14_0_Pos 26 /*!< LCD PAL137: B14_0 Position */
+#define LCD_PAL137_B14_0_Msk (0x1fUL << LCD_PAL137_B14_0_Pos) /*!< LCD PAL137: B14_0 Mask */
+#define LCD_PAL137_I1_Pos 31 /*!< LCD PAL137: I1 Position */
+#define LCD_PAL137_I1_Msk (0x01UL << LCD_PAL137_I1_Pos) /*!< LCD PAL137: I1 Mask */
+
+// --------------------------------------- LCD_PAL138 -------------------------------------------
+#define LCD_PAL138_R04_0_Pos 0 /*!< LCD PAL138: R04_0 Position */
+#define LCD_PAL138_R04_0_Msk (0x1fUL << LCD_PAL138_R04_0_Pos) /*!< LCD PAL138: R04_0 Mask */
+#define LCD_PAL138_G04_0_Pos 5 /*!< LCD PAL138: G04_0 Position */
+#define LCD_PAL138_G04_0_Msk (0x1fUL << LCD_PAL138_G04_0_Pos) /*!< LCD PAL138: G04_0 Mask */
+#define LCD_PAL138_B04_0_Pos 10 /*!< LCD PAL138: B04_0 Position */
+#define LCD_PAL138_B04_0_Msk (0x1fUL << LCD_PAL138_B04_0_Pos) /*!< LCD PAL138: B04_0 Mask */
+#define LCD_PAL138_I0_Pos 15 /*!< LCD PAL138: I0 Position */
+#define LCD_PAL138_I0_Msk (0x01UL << LCD_PAL138_I0_Pos) /*!< LCD PAL138: I0 Mask */
+#define LCD_PAL138_R14_0_Pos 16 /*!< LCD PAL138: R14_0 Position */
+#define LCD_PAL138_R14_0_Msk (0x1fUL << LCD_PAL138_R14_0_Pos) /*!< LCD PAL138: R14_0 Mask */
+#define LCD_PAL138_G14_0_Pos 21 /*!< LCD PAL138: G14_0 Position */
+#define LCD_PAL138_G14_0_Msk (0x1fUL << LCD_PAL138_G14_0_Pos) /*!< LCD PAL138: G14_0 Mask */
+#define LCD_PAL138_B14_0_Pos 26 /*!< LCD PAL138: B14_0 Position */
+#define LCD_PAL138_B14_0_Msk (0x1fUL << LCD_PAL138_B14_0_Pos) /*!< LCD PAL138: B14_0 Mask */
+#define LCD_PAL138_I1_Pos 31 /*!< LCD PAL138: I1 Position */
+#define LCD_PAL138_I1_Msk (0x01UL << LCD_PAL138_I1_Pos) /*!< LCD PAL138: I1 Mask */
+
+// --------------------------------------- LCD_PAL139 -------------------------------------------
+#define LCD_PAL139_R04_0_Pos 0 /*!< LCD PAL139: R04_0 Position */
+#define LCD_PAL139_R04_0_Msk (0x1fUL << LCD_PAL139_R04_0_Pos) /*!< LCD PAL139: R04_0 Mask */
+#define LCD_PAL139_G04_0_Pos 5 /*!< LCD PAL139: G04_0 Position */
+#define LCD_PAL139_G04_0_Msk (0x1fUL << LCD_PAL139_G04_0_Pos) /*!< LCD PAL139: G04_0 Mask */
+#define LCD_PAL139_B04_0_Pos 10 /*!< LCD PAL139: B04_0 Position */
+#define LCD_PAL139_B04_0_Msk (0x1fUL << LCD_PAL139_B04_0_Pos) /*!< LCD PAL139: B04_0 Mask */
+#define LCD_PAL139_I0_Pos 15 /*!< LCD PAL139: I0 Position */
+#define LCD_PAL139_I0_Msk (0x01UL << LCD_PAL139_I0_Pos) /*!< LCD PAL139: I0 Mask */
+#define LCD_PAL139_R14_0_Pos 16 /*!< LCD PAL139: R14_0 Position */
+#define LCD_PAL139_R14_0_Msk (0x1fUL << LCD_PAL139_R14_0_Pos) /*!< LCD PAL139: R14_0 Mask */
+#define LCD_PAL139_G14_0_Pos 21 /*!< LCD PAL139: G14_0 Position */
+#define LCD_PAL139_G14_0_Msk (0x1fUL << LCD_PAL139_G14_0_Pos) /*!< LCD PAL139: G14_0 Mask */
+#define LCD_PAL139_B14_0_Pos 26 /*!< LCD PAL139: B14_0 Position */
+#define LCD_PAL139_B14_0_Msk (0x1fUL << LCD_PAL139_B14_0_Pos) /*!< LCD PAL139: B14_0 Mask */
+#define LCD_PAL139_I1_Pos 31 /*!< LCD PAL139: I1 Position */
+#define LCD_PAL139_I1_Msk (0x01UL << LCD_PAL139_I1_Pos) /*!< LCD PAL139: I1 Mask */
+
+// --------------------------------------- LCD_PAL140 -------------------------------------------
+#define LCD_PAL140_R04_0_Pos 0 /*!< LCD PAL140: R04_0 Position */
+#define LCD_PAL140_R04_0_Msk (0x1fUL << LCD_PAL140_R04_0_Pos) /*!< LCD PAL140: R04_0 Mask */
+#define LCD_PAL140_G04_0_Pos 5 /*!< LCD PAL140: G04_0 Position */
+#define LCD_PAL140_G04_0_Msk (0x1fUL << LCD_PAL140_G04_0_Pos) /*!< LCD PAL140: G04_0 Mask */
+#define LCD_PAL140_B04_0_Pos 10 /*!< LCD PAL140: B04_0 Position */
+#define LCD_PAL140_B04_0_Msk (0x1fUL << LCD_PAL140_B04_0_Pos) /*!< LCD PAL140: B04_0 Mask */
+#define LCD_PAL140_I0_Pos 15 /*!< LCD PAL140: I0 Position */
+#define LCD_PAL140_I0_Msk (0x01UL << LCD_PAL140_I0_Pos) /*!< LCD PAL140: I0 Mask */
+#define LCD_PAL140_R14_0_Pos 16 /*!< LCD PAL140: R14_0 Position */
+#define LCD_PAL140_R14_0_Msk (0x1fUL << LCD_PAL140_R14_0_Pos) /*!< LCD PAL140: R14_0 Mask */
+#define LCD_PAL140_G14_0_Pos 21 /*!< LCD PAL140: G14_0 Position */
+#define LCD_PAL140_G14_0_Msk (0x1fUL << LCD_PAL140_G14_0_Pos) /*!< LCD PAL140: G14_0 Mask */
+#define LCD_PAL140_B14_0_Pos 26 /*!< LCD PAL140: B14_0 Position */
+#define LCD_PAL140_B14_0_Msk (0x1fUL << LCD_PAL140_B14_0_Pos) /*!< LCD PAL140: B14_0 Mask */
+#define LCD_PAL140_I1_Pos 31 /*!< LCD PAL140: I1 Position */
+#define LCD_PAL140_I1_Msk (0x01UL << LCD_PAL140_I1_Pos) /*!< LCD PAL140: I1 Mask */
+
+// --------------------------------------- LCD_PAL141 -------------------------------------------
+#define LCD_PAL141_R04_0_Pos 0 /*!< LCD PAL141: R04_0 Position */
+#define LCD_PAL141_R04_0_Msk (0x1fUL << LCD_PAL141_R04_0_Pos) /*!< LCD PAL141: R04_0 Mask */
+#define LCD_PAL141_G04_0_Pos 5 /*!< LCD PAL141: G04_0 Position */
+#define LCD_PAL141_G04_0_Msk (0x1fUL << LCD_PAL141_G04_0_Pos) /*!< LCD PAL141: G04_0 Mask */
+#define LCD_PAL141_B04_0_Pos 10 /*!< LCD PAL141: B04_0 Position */
+#define LCD_PAL141_B04_0_Msk (0x1fUL << LCD_PAL141_B04_0_Pos) /*!< LCD PAL141: B04_0 Mask */
+#define LCD_PAL141_I0_Pos 15 /*!< LCD PAL141: I0 Position */
+#define LCD_PAL141_I0_Msk (0x01UL << LCD_PAL141_I0_Pos) /*!< LCD PAL141: I0 Mask */
+#define LCD_PAL141_R14_0_Pos 16 /*!< LCD PAL141: R14_0 Position */
+#define LCD_PAL141_R14_0_Msk (0x1fUL << LCD_PAL141_R14_0_Pos) /*!< LCD PAL141: R14_0 Mask */
+#define LCD_PAL141_G14_0_Pos 21 /*!< LCD PAL141: G14_0 Position */
+#define LCD_PAL141_G14_0_Msk (0x1fUL << LCD_PAL141_G14_0_Pos) /*!< LCD PAL141: G14_0 Mask */
+#define LCD_PAL141_B14_0_Pos 26 /*!< LCD PAL141: B14_0 Position */
+#define LCD_PAL141_B14_0_Msk (0x1fUL << LCD_PAL141_B14_0_Pos) /*!< LCD PAL141: B14_0 Mask */
+#define LCD_PAL141_I1_Pos 31 /*!< LCD PAL141: I1 Position */
+#define LCD_PAL141_I1_Msk (0x01UL << LCD_PAL141_I1_Pos) /*!< LCD PAL141: I1 Mask */
+
+// --------------------------------------- LCD_PAL142 -------------------------------------------
+#define LCD_PAL142_R04_0_Pos 0 /*!< LCD PAL142: R04_0 Position */
+#define LCD_PAL142_R04_0_Msk (0x1fUL << LCD_PAL142_R04_0_Pos) /*!< LCD PAL142: R04_0 Mask */
+#define LCD_PAL142_G04_0_Pos 5 /*!< LCD PAL142: G04_0 Position */
+#define LCD_PAL142_G04_0_Msk (0x1fUL << LCD_PAL142_G04_0_Pos) /*!< LCD PAL142: G04_0 Mask */
+#define LCD_PAL142_B04_0_Pos 10 /*!< LCD PAL142: B04_0 Position */
+#define LCD_PAL142_B04_0_Msk (0x1fUL << LCD_PAL142_B04_0_Pos) /*!< LCD PAL142: B04_0 Mask */
+#define LCD_PAL142_I0_Pos 15 /*!< LCD PAL142: I0 Position */
+#define LCD_PAL142_I0_Msk (0x01UL << LCD_PAL142_I0_Pos) /*!< LCD PAL142: I0 Mask */
+#define LCD_PAL142_R14_0_Pos 16 /*!< LCD PAL142: R14_0 Position */
+#define LCD_PAL142_R14_0_Msk (0x1fUL << LCD_PAL142_R14_0_Pos) /*!< LCD PAL142: R14_0 Mask */
+#define LCD_PAL142_G14_0_Pos 21 /*!< LCD PAL142: G14_0 Position */
+#define LCD_PAL142_G14_0_Msk (0x1fUL << LCD_PAL142_G14_0_Pos) /*!< LCD PAL142: G14_0 Mask */
+#define LCD_PAL142_B14_0_Pos 26 /*!< LCD PAL142: B14_0 Position */
+#define LCD_PAL142_B14_0_Msk (0x1fUL << LCD_PAL142_B14_0_Pos) /*!< LCD PAL142: B14_0 Mask */
+#define LCD_PAL142_I1_Pos 31 /*!< LCD PAL142: I1 Position */
+#define LCD_PAL142_I1_Msk (0x01UL << LCD_PAL142_I1_Pos) /*!< LCD PAL142: I1 Mask */
+
+// --------------------------------------- LCD_PAL143 -------------------------------------------
+#define LCD_PAL143_R04_0_Pos 0 /*!< LCD PAL143: R04_0 Position */
+#define LCD_PAL143_R04_0_Msk (0x1fUL << LCD_PAL143_R04_0_Pos) /*!< LCD PAL143: R04_0 Mask */
+#define LCD_PAL143_G04_0_Pos 5 /*!< LCD PAL143: G04_0 Position */
+#define LCD_PAL143_G04_0_Msk (0x1fUL << LCD_PAL143_G04_0_Pos) /*!< LCD PAL143: G04_0 Mask */
+#define LCD_PAL143_B04_0_Pos 10 /*!< LCD PAL143: B04_0 Position */
+#define LCD_PAL143_B04_0_Msk (0x1fUL << LCD_PAL143_B04_0_Pos) /*!< LCD PAL143: B04_0 Mask */
+#define LCD_PAL143_I0_Pos 15 /*!< LCD PAL143: I0 Position */
+#define LCD_PAL143_I0_Msk (0x01UL << LCD_PAL143_I0_Pos) /*!< LCD PAL143: I0 Mask */
+#define LCD_PAL143_R14_0_Pos 16 /*!< LCD PAL143: R14_0 Position */
+#define LCD_PAL143_R14_0_Msk (0x1fUL << LCD_PAL143_R14_0_Pos) /*!< LCD PAL143: R14_0 Mask */
+#define LCD_PAL143_G14_0_Pos 21 /*!< LCD PAL143: G14_0 Position */
+#define LCD_PAL143_G14_0_Msk (0x1fUL << LCD_PAL143_G14_0_Pos) /*!< LCD PAL143: G14_0 Mask */
+#define LCD_PAL143_B14_0_Pos 26 /*!< LCD PAL143: B14_0 Position */
+#define LCD_PAL143_B14_0_Msk (0x1fUL << LCD_PAL143_B14_0_Pos) /*!< LCD PAL143: B14_0 Mask */
+#define LCD_PAL143_I1_Pos 31 /*!< LCD PAL143: I1 Position */
+#define LCD_PAL143_I1_Msk (0x01UL << LCD_PAL143_I1_Pos) /*!< LCD PAL143: I1 Mask */
+
+// --------------------------------------- LCD_PAL144 -------------------------------------------
+#define LCD_PAL144_R04_0_Pos 0 /*!< LCD PAL144: R04_0 Position */
+#define LCD_PAL144_R04_0_Msk (0x1fUL << LCD_PAL144_R04_0_Pos) /*!< LCD PAL144: R04_0 Mask */
+#define LCD_PAL144_G04_0_Pos 5 /*!< LCD PAL144: G04_0 Position */
+#define LCD_PAL144_G04_0_Msk (0x1fUL << LCD_PAL144_G04_0_Pos) /*!< LCD PAL144: G04_0 Mask */
+#define LCD_PAL144_B04_0_Pos 10 /*!< LCD PAL144: B04_0 Position */
+#define LCD_PAL144_B04_0_Msk (0x1fUL << LCD_PAL144_B04_0_Pos) /*!< LCD PAL144: B04_0 Mask */
+#define LCD_PAL144_I0_Pos 15 /*!< LCD PAL144: I0 Position */
+#define LCD_PAL144_I0_Msk (0x01UL << LCD_PAL144_I0_Pos) /*!< LCD PAL144: I0 Mask */
+#define LCD_PAL144_R14_0_Pos 16 /*!< LCD PAL144: R14_0 Position */
+#define LCD_PAL144_R14_0_Msk (0x1fUL << LCD_PAL144_R14_0_Pos) /*!< LCD PAL144: R14_0 Mask */
+#define LCD_PAL144_G14_0_Pos 21 /*!< LCD PAL144: G14_0 Position */
+#define LCD_PAL144_G14_0_Msk (0x1fUL << LCD_PAL144_G14_0_Pos) /*!< LCD PAL144: G14_0 Mask */
+#define LCD_PAL144_B14_0_Pos 26 /*!< LCD PAL144: B14_0 Position */
+#define LCD_PAL144_B14_0_Msk (0x1fUL << LCD_PAL144_B14_0_Pos) /*!< LCD PAL144: B14_0 Mask */
+#define LCD_PAL144_I1_Pos 31 /*!< LCD PAL144: I1 Position */
+#define LCD_PAL144_I1_Msk (0x01UL << LCD_PAL144_I1_Pos) /*!< LCD PAL144: I1 Mask */
+
+// --------------------------------------- LCD_PAL145 -------------------------------------------
+#define LCD_PAL145_R04_0_Pos 0 /*!< LCD PAL145: R04_0 Position */
+#define LCD_PAL145_R04_0_Msk (0x1fUL << LCD_PAL145_R04_0_Pos) /*!< LCD PAL145: R04_0 Mask */
+#define LCD_PAL145_G04_0_Pos 5 /*!< LCD PAL145: G04_0 Position */
+#define LCD_PAL145_G04_0_Msk (0x1fUL << LCD_PAL145_G04_0_Pos) /*!< LCD PAL145: G04_0 Mask */
+#define LCD_PAL145_B04_0_Pos 10 /*!< LCD PAL145: B04_0 Position */
+#define LCD_PAL145_B04_0_Msk (0x1fUL << LCD_PAL145_B04_0_Pos) /*!< LCD PAL145: B04_0 Mask */
+#define LCD_PAL145_I0_Pos 15 /*!< LCD PAL145: I0 Position */
+#define LCD_PAL145_I0_Msk (0x01UL << LCD_PAL145_I0_Pos) /*!< LCD PAL145: I0 Mask */
+#define LCD_PAL145_R14_0_Pos 16 /*!< LCD PAL145: R14_0 Position */
+#define LCD_PAL145_R14_0_Msk (0x1fUL << LCD_PAL145_R14_0_Pos) /*!< LCD PAL145: R14_0 Mask */
+#define LCD_PAL145_G14_0_Pos 21 /*!< LCD PAL145: G14_0 Position */
+#define LCD_PAL145_G14_0_Msk (0x1fUL << LCD_PAL145_G14_0_Pos) /*!< LCD PAL145: G14_0 Mask */
+#define LCD_PAL145_B14_0_Pos 26 /*!< LCD PAL145: B14_0 Position */
+#define LCD_PAL145_B14_0_Msk (0x1fUL << LCD_PAL145_B14_0_Pos) /*!< LCD PAL145: B14_0 Mask */
+#define LCD_PAL145_I1_Pos 31 /*!< LCD PAL145: I1 Position */
+#define LCD_PAL145_I1_Msk (0x01UL << LCD_PAL145_I1_Pos) /*!< LCD PAL145: I1 Mask */
+
+// --------------------------------------- LCD_PAL146 -------------------------------------------
+#define LCD_PAL146_R04_0_Pos 0 /*!< LCD PAL146: R04_0 Position */
+#define LCD_PAL146_R04_0_Msk (0x1fUL << LCD_PAL146_R04_0_Pos) /*!< LCD PAL146: R04_0 Mask */
+#define LCD_PAL146_G04_0_Pos 5 /*!< LCD PAL146: G04_0 Position */
+#define LCD_PAL146_G04_0_Msk (0x1fUL << LCD_PAL146_G04_0_Pos) /*!< LCD PAL146: G04_0 Mask */
+#define LCD_PAL146_B04_0_Pos 10 /*!< LCD PAL146: B04_0 Position */
+#define LCD_PAL146_B04_0_Msk (0x1fUL << LCD_PAL146_B04_0_Pos) /*!< LCD PAL146: B04_0 Mask */
+#define LCD_PAL146_I0_Pos 15 /*!< LCD PAL146: I0 Position */
+#define LCD_PAL146_I0_Msk (0x01UL << LCD_PAL146_I0_Pos) /*!< LCD PAL146: I0 Mask */
+#define LCD_PAL146_R14_0_Pos 16 /*!< LCD PAL146: R14_0 Position */
+#define LCD_PAL146_R14_0_Msk (0x1fUL << LCD_PAL146_R14_0_Pos) /*!< LCD PAL146: R14_0 Mask */
+#define LCD_PAL146_G14_0_Pos 21 /*!< LCD PAL146: G14_0 Position */
+#define LCD_PAL146_G14_0_Msk (0x1fUL << LCD_PAL146_G14_0_Pos) /*!< LCD PAL146: G14_0 Mask */
+#define LCD_PAL146_B14_0_Pos 26 /*!< LCD PAL146: B14_0 Position */
+#define LCD_PAL146_B14_0_Msk (0x1fUL << LCD_PAL146_B14_0_Pos) /*!< LCD PAL146: B14_0 Mask */
+#define LCD_PAL146_I1_Pos 31 /*!< LCD PAL146: I1 Position */
+#define LCD_PAL146_I1_Msk (0x01UL << LCD_PAL146_I1_Pos) /*!< LCD PAL146: I1 Mask */
+
+// --------------------------------------- LCD_PAL147 -------------------------------------------
+#define LCD_PAL147_R04_0_Pos 0 /*!< LCD PAL147: R04_0 Position */
+#define LCD_PAL147_R04_0_Msk (0x1fUL << LCD_PAL147_R04_0_Pos) /*!< LCD PAL147: R04_0 Mask */
+#define LCD_PAL147_G04_0_Pos 5 /*!< LCD PAL147: G04_0 Position */
+#define LCD_PAL147_G04_0_Msk (0x1fUL << LCD_PAL147_G04_0_Pos) /*!< LCD PAL147: G04_0 Mask */
+#define LCD_PAL147_B04_0_Pos 10 /*!< LCD PAL147: B04_0 Position */
+#define LCD_PAL147_B04_0_Msk (0x1fUL << LCD_PAL147_B04_0_Pos) /*!< LCD PAL147: B04_0 Mask */
+#define LCD_PAL147_I0_Pos 15 /*!< LCD PAL147: I0 Position */
+#define LCD_PAL147_I0_Msk (0x01UL << LCD_PAL147_I0_Pos) /*!< LCD PAL147: I0 Mask */
+#define LCD_PAL147_R14_0_Pos 16 /*!< LCD PAL147: R14_0 Position */
+#define LCD_PAL147_R14_0_Msk (0x1fUL << LCD_PAL147_R14_0_Pos) /*!< LCD PAL147: R14_0 Mask */
+#define LCD_PAL147_G14_0_Pos 21 /*!< LCD PAL147: G14_0 Position */
+#define LCD_PAL147_G14_0_Msk (0x1fUL << LCD_PAL147_G14_0_Pos) /*!< LCD PAL147: G14_0 Mask */
+#define LCD_PAL147_B14_0_Pos 26 /*!< LCD PAL147: B14_0 Position */
+#define LCD_PAL147_B14_0_Msk (0x1fUL << LCD_PAL147_B14_0_Pos) /*!< LCD PAL147: B14_0 Mask */
+#define LCD_PAL147_I1_Pos 31 /*!< LCD PAL147: I1 Position */
+#define LCD_PAL147_I1_Msk (0x01UL << LCD_PAL147_I1_Pos) /*!< LCD PAL147: I1 Mask */
+
+// --------------------------------------- LCD_PAL148 -------------------------------------------
+#define LCD_PAL148_R04_0_Pos 0 /*!< LCD PAL148: R04_0 Position */
+#define LCD_PAL148_R04_0_Msk (0x1fUL << LCD_PAL148_R04_0_Pos) /*!< LCD PAL148: R04_0 Mask */
+#define LCD_PAL148_G04_0_Pos 5 /*!< LCD PAL148: G04_0 Position */
+#define LCD_PAL148_G04_0_Msk (0x1fUL << LCD_PAL148_G04_0_Pos) /*!< LCD PAL148: G04_0 Mask */
+#define LCD_PAL148_B04_0_Pos 10 /*!< LCD PAL148: B04_0 Position */
+#define LCD_PAL148_B04_0_Msk (0x1fUL << LCD_PAL148_B04_0_Pos) /*!< LCD PAL148: B04_0 Mask */
+#define LCD_PAL148_I0_Pos 15 /*!< LCD PAL148: I0 Position */
+#define LCD_PAL148_I0_Msk (0x01UL << LCD_PAL148_I0_Pos) /*!< LCD PAL148: I0 Mask */
+#define LCD_PAL148_R14_0_Pos 16 /*!< LCD PAL148: R14_0 Position */
+#define LCD_PAL148_R14_0_Msk (0x1fUL << LCD_PAL148_R14_0_Pos) /*!< LCD PAL148: R14_0 Mask */
+#define LCD_PAL148_G14_0_Pos 21 /*!< LCD PAL148: G14_0 Position */
+#define LCD_PAL148_G14_0_Msk (0x1fUL << LCD_PAL148_G14_0_Pos) /*!< LCD PAL148: G14_0 Mask */
+#define LCD_PAL148_B14_0_Pos 26 /*!< LCD PAL148: B14_0 Position */
+#define LCD_PAL148_B14_0_Msk (0x1fUL << LCD_PAL148_B14_0_Pos) /*!< LCD PAL148: B14_0 Mask */
+#define LCD_PAL148_I1_Pos 31 /*!< LCD PAL148: I1 Position */
+#define LCD_PAL148_I1_Msk (0x01UL << LCD_PAL148_I1_Pos) /*!< LCD PAL148: I1 Mask */
+
+// --------------------------------------- LCD_PAL149 -------------------------------------------
+#define LCD_PAL149_R04_0_Pos 0 /*!< LCD PAL149: R04_0 Position */
+#define LCD_PAL149_R04_0_Msk (0x1fUL << LCD_PAL149_R04_0_Pos) /*!< LCD PAL149: R04_0 Mask */
+#define LCD_PAL149_G04_0_Pos 5 /*!< LCD PAL149: G04_0 Position */
+#define LCD_PAL149_G04_0_Msk (0x1fUL << LCD_PAL149_G04_0_Pos) /*!< LCD PAL149: G04_0 Mask */
+#define LCD_PAL149_B04_0_Pos 10 /*!< LCD PAL149: B04_0 Position */
+#define LCD_PAL149_B04_0_Msk (0x1fUL << LCD_PAL149_B04_0_Pos) /*!< LCD PAL149: B04_0 Mask */
+#define LCD_PAL149_I0_Pos 15 /*!< LCD PAL149: I0 Position */
+#define LCD_PAL149_I0_Msk (0x01UL << LCD_PAL149_I0_Pos) /*!< LCD PAL149: I0 Mask */
+#define LCD_PAL149_R14_0_Pos 16 /*!< LCD PAL149: R14_0 Position */
+#define LCD_PAL149_R14_0_Msk (0x1fUL << LCD_PAL149_R14_0_Pos) /*!< LCD PAL149: R14_0 Mask */
+#define LCD_PAL149_G14_0_Pos 21 /*!< LCD PAL149: G14_0 Position */
+#define LCD_PAL149_G14_0_Msk (0x1fUL << LCD_PAL149_G14_0_Pos) /*!< LCD PAL149: G14_0 Mask */
+#define LCD_PAL149_B14_0_Pos 26 /*!< LCD PAL149: B14_0 Position */
+#define LCD_PAL149_B14_0_Msk (0x1fUL << LCD_PAL149_B14_0_Pos) /*!< LCD PAL149: B14_0 Mask */
+#define LCD_PAL149_I1_Pos 31 /*!< LCD PAL149: I1 Position */
+#define LCD_PAL149_I1_Msk (0x01UL << LCD_PAL149_I1_Pos) /*!< LCD PAL149: I1 Mask */
+
+// --------------------------------------- LCD_PAL150 -------------------------------------------
+#define LCD_PAL150_R04_0_Pos 0 /*!< LCD PAL150: R04_0 Position */
+#define LCD_PAL150_R04_0_Msk (0x1fUL << LCD_PAL150_R04_0_Pos) /*!< LCD PAL150: R04_0 Mask */
+#define LCD_PAL150_G04_0_Pos 5 /*!< LCD PAL150: G04_0 Position */
+#define LCD_PAL150_G04_0_Msk (0x1fUL << LCD_PAL150_G04_0_Pos) /*!< LCD PAL150: G04_0 Mask */
+#define LCD_PAL150_B04_0_Pos 10 /*!< LCD PAL150: B04_0 Position */
+#define LCD_PAL150_B04_0_Msk (0x1fUL << LCD_PAL150_B04_0_Pos) /*!< LCD PAL150: B04_0 Mask */
+#define LCD_PAL150_I0_Pos 15 /*!< LCD PAL150: I0 Position */
+#define LCD_PAL150_I0_Msk (0x01UL << LCD_PAL150_I0_Pos) /*!< LCD PAL150: I0 Mask */
+#define LCD_PAL150_R14_0_Pos 16 /*!< LCD PAL150: R14_0 Position */
+#define LCD_PAL150_R14_0_Msk (0x1fUL << LCD_PAL150_R14_0_Pos) /*!< LCD PAL150: R14_0 Mask */
+#define LCD_PAL150_G14_0_Pos 21 /*!< LCD PAL150: G14_0 Position */
+#define LCD_PAL150_G14_0_Msk (0x1fUL << LCD_PAL150_G14_0_Pos) /*!< LCD PAL150: G14_0 Mask */
+#define LCD_PAL150_B14_0_Pos 26 /*!< LCD PAL150: B14_0 Position */
+#define LCD_PAL150_B14_0_Msk (0x1fUL << LCD_PAL150_B14_0_Pos) /*!< LCD PAL150: B14_0 Mask */
+#define LCD_PAL150_I1_Pos 31 /*!< LCD PAL150: I1 Position */
+#define LCD_PAL150_I1_Msk (0x01UL << LCD_PAL150_I1_Pos) /*!< LCD PAL150: I1 Mask */
+
+// --------------------------------------- LCD_PAL151 -------------------------------------------
+#define LCD_PAL151_R04_0_Pos 0 /*!< LCD PAL151: R04_0 Position */
+#define LCD_PAL151_R04_0_Msk (0x1fUL << LCD_PAL151_R04_0_Pos) /*!< LCD PAL151: R04_0 Mask */
+#define LCD_PAL151_G04_0_Pos 5 /*!< LCD PAL151: G04_0 Position */
+#define LCD_PAL151_G04_0_Msk (0x1fUL << LCD_PAL151_G04_0_Pos) /*!< LCD PAL151: G04_0 Mask */
+#define LCD_PAL151_B04_0_Pos 10 /*!< LCD PAL151: B04_0 Position */
+#define LCD_PAL151_B04_0_Msk (0x1fUL << LCD_PAL151_B04_0_Pos) /*!< LCD PAL151: B04_0 Mask */
+#define LCD_PAL151_I0_Pos 15 /*!< LCD PAL151: I0 Position */
+#define LCD_PAL151_I0_Msk (0x01UL << LCD_PAL151_I0_Pos) /*!< LCD PAL151: I0 Mask */
+#define LCD_PAL151_R14_0_Pos 16 /*!< LCD PAL151: R14_0 Position */
+#define LCD_PAL151_R14_0_Msk (0x1fUL << LCD_PAL151_R14_0_Pos) /*!< LCD PAL151: R14_0 Mask */
+#define LCD_PAL151_G14_0_Pos 21 /*!< LCD PAL151: G14_0 Position */
+#define LCD_PAL151_G14_0_Msk (0x1fUL << LCD_PAL151_G14_0_Pos) /*!< LCD PAL151: G14_0 Mask */
+#define LCD_PAL151_B14_0_Pos 26 /*!< LCD PAL151: B14_0 Position */
+#define LCD_PAL151_B14_0_Msk (0x1fUL << LCD_PAL151_B14_0_Pos) /*!< LCD PAL151: B14_0 Mask */
+#define LCD_PAL151_I1_Pos 31 /*!< LCD PAL151: I1 Position */
+#define LCD_PAL151_I1_Msk (0x01UL << LCD_PAL151_I1_Pos) /*!< LCD PAL151: I1 Mask */
+
+// --------------------------------------- LCD_PAL152 -------------------------------------------
+#define LCD_PAL152_R04_0_Pos 0 /*!< LCD PAL152: R04_0 Position */
+#define LCD_PAL152_R04_0_Msk (0x1fUL << LCD_PAL152_R04_0_Pos) /*!< LCD PAL152: R04_0 Mask */
+#define LCD_PAL152_G04_0_Pos 5 /*!< LCD PAL152: G04_0 Position */
+#define LCD_PAL152_G04_0_Msk (0x1fUL << LCD_PAL152_G04_0_Pos) /*!< LCD PAL152: G04_0 Mask */
+#define LCD_PAL152_B04_0_Pos 10 /*!< LCD PAL152: B04_0 Position */
+#define LCD_PAL152_B04_0_Msk (0x1fUL << LCD_PAL152_B04_0_Pos) /*!< LCD PAL152: B04_0 Mask */
+#define LCD_PAL152_I0_Pos 15 /*!< LCD PAL152: I0 Position */
+#define LCD_PAL152_I0_Msk (0x01UL << LCD_PAL152_I0_Pos) /*!< LCD PAL152: I0 Mask */
+#define LCD_PAL152_R14_0_Pos 16 /*!< LCD PAL152: R14_0 Position */
+#define LCD_PAL152_R14_0_Msk (0x1fUL << LCD_PAL152_R14_0_Pos) /*!< LCD PAL152: R14_0 Mask */
+#define LCD_PAL152_G14_0_Pos 21 /*!< LCD PAL152: G14_0 Position */
+#define LCD_PAL152_G14_0_Msk (0x1fUL << LCD_PAL152_G14_0_Pos) /*!< LCD PAL152: G14_0 Mask */
+#define LCD_PAL152_B14_0_Pos 26 /*!< LCD PAL152: B14_0 Position */
+#define LCD_PAL152_B14_0_Msk (0x1fUL << LCD_PAL152_B14_0_Pos) /*!< LCD PAL152: B14_0 Mask */
+#define LCD_PAL152_I1_Pos 31 /*!< LCD PAL152: I1 Position */
+#define LCD_PAL152_I1_Msk (0x01UL << LCD_PAL152_I1_Pos) /*!< LCD PAL152: I1 Mask */
+
+// --------------------------------------- LCD_PAL153 -------------------------------------------
+#define LCD_PAL153_R04_0_Pos 0 /*!< LCD PAL153: R04_0 Position */
+#define LCD_PAL153_R04_0_Msk (0x1fUL << LCD_PAL153_R04_0_Pos) /*!< LCD PAL153: R04_0 Mask */
+#define LCD_PAL153_G04_0_Pos 5 /*!< LCD PAL153: G04_0 Position */
+#define LCD_PAL153_G04_0_Msk (0x1fUL << LCD_PAL153_G04_0_Pos) /*!< LCD PAL153: G04_0 Mask */
+#define LCD_PAL153_B04_0_Pos 10 /*!< LCD PAL153: B04_0 Position */
+#define LCD_PAL153_B04_0_Msk (0x1fUL << LCD_PAL153_B04_0_Pos) /*!< LCD PAL153: B04_0 Mask */
+#define LCD_PAL153_I0_Pos 15 /*!< LCD PAL153: I0 Position */
+#define LCD_PAL153_I0_Msk (0x01UL << LCD_PAL153_I0_Pos) /*!< LCD PAL153: I0 Mask */
+#define LCD_PAL153_R14_0_Pos 16 /*!< LCD PAL153: R14_0 Position */
+#define LCD_PAL153_R14_0_Msk (0x1fUL << LCD_PAL153_R14_0_Pos) /*!< LCD PAL153: R14_0 Mask */
+#define LCD_PAL153_G14_0_Pos 21 /*!< LCD PAL153: G14_0 Position */
+#define LCD_PAL153_G14_0_Msk (0x1fUL << LCD_PAL153_G14_0_Pos) /*!< LCD PAL153: G14_0 Mask */
+#define LCD_PAL153_B14_0_Pos 26 /*!< LCD PAL153: B14_0 Position */
+#define LCD_PAL153_B14_0_Msk (0x1fUL << LCD_PAL153_B14_0_Pos) /*!< LCD PAL153: B14_0 Mask */
+#define LCD_PAL153_I1_Pos 31 /*!< LCD PAL153: I1 Position */
+#define LCD_PAL153_I1_Msk (0x01UL << LCD_PAL153_I1_Pos) /*!< LCD PAL153: I1 Mask */
+
+// --------------------------------------- LCD_PAL154 -------------------------------------------
+#define LCD_PAL154_R04_0_Pos 0 /*!< LCD PAL154: R04_0 Position */
+#define LCD_PAL154_R04_0_Msk (0x1fUL << LCD_PAL154_R04_0_Pos) /*!< LCD PAL154: R04_0 Mask */
+#define LCD_PAL154_G04_0_Pos 5 /*!< LCD PAL154: G04_0 Position */
+#define LCD_PAL154_G04_0_Msk (0x1fUL << LCD_PAL154_G04_0_Pos) /*!< LCD PAL154: G04_0 Mask */
+#define LCD_PAL154_B04_0_Pos 10 /*!< LCD PAL154: B04_0 Position */
+#define LCD_PAL154_B04_0_Msk (0x1fUL << LCD_PAL154_B04_0_Pos) /*!< LCD PAL154: B04_0 Mask */
+#define LCD_PAL154_I0_Pos 15 /*!< LCD PAL154: I0 Position */
+#define LCD_PAL154_I0_Msk (0x01UL << LCD_PAL154_I0_Pos) /*!< LCD PAL154: I0 Mask */
+#define LCD_PAL154_R14_0_Pos 16 /*!< LCD PAL154: R14_0 Position */
+#define LCD_PAL154_R14_0_Msk (0x1fUL << LCD_PAL154_R14_0_Pos) /*!< LCD PAL154: R14_0 Mask */
+#define LCD_PAL154_G14_0_Pos 21 /*!< LCD PAL154: G14_0 Position */
+#define LCD_PAL154_G14_0_Msk (0x1fUL << LCD_PAL154_G14_0_Pos) /*!< LCD PAL154: G14_0 Mask */
+#define LCD_PAL154_B14_0_Pos 26 /*!< LCD PAL154: B14_0 Position */
+#define LCD_PAL154_B14_0_Msk (0x1fUL << LCD_PAL154_B14_0_Pos) /*!< LCD PAL154: B14_0 Mask */
+#define LCD_PAL154_I1_Pos 31 /*!< LCD PAL154: I1 Position */
+#define LCD_PAL154_I1_Msk (0x01UL << LCD_PAL154_I1_Pos) /*!< LCD PAL154: I1 Mask */
+
+// --------------------------------------- LCD_PAL155 -------------------------------------------
+#define LCD_PAL155_R04_0_Pos 0 /*!< LCD PAL155: R04_0 Position */
+#define LCD_PAL155_R04_0_Msk (0x1fUL << LCD_PAL155_R04_0_Pos) /*!< LCD PAL155: R04_0 Mask */
+#define LCD_PAL155_G04_0_Pos 5 /*!< LCD PAL155: G04_0 Position */
+#define LCD_PAL155_G04_0_Msk (0x1fUL << LCD_PAL155_G04_0_Pos) /*!< LCD PAL155: G04_0 Mask */
+#define LCD_PAL155_B04_0_Pos 10 /*!< LCD PAL155: B04_0 Position */
+#define LCD_PAL155_B04_0_Msk (0x1fUL << LCD_PAL155_B04_0_Pos) /*!< LCD PAL155: B04_0 Mask */
+#define LCD_PAL155_I0_Pos 15 /*!< LCD PAL155: I0 Position */
+#define LCD_PAL155_I0_Msk (0x01UL << LCD_PAL155_I0_Pos) /*!< LCD PAL155: I0 Mask */
+#define LCD_PAL155_R14_0_Pos 16 /*!< LCD PAL155: R14_0 Position */
+#define LCD_PAL155_R14_0_Msk (0x1fUL << LCD_PAL155_R14_0_Pos) /*!< LCD PAL155: R14_0 Mask */
+#define LCD_PAL155_G14_0_Pos 21 /*!< LCD PAL155: G14_0 Position */
+#define LCD_PAL155_G14_0_Msk (0x1fUL << LCD_PAL155_G14_0_Pos) /*!< LCD PAL155: G14_0 Mask */
+#define LCD_PAL155_B14_0_Pos 26 /*!< LCD PAL155: B14_0 Position */
+#define LCD_PAL155_B14_0_Msk (0x1fUL << LCD_PAL155_B14_0_Pos) /*!< LCD PAL155: B14_0 Mask */
+#define LCD_PAL155_I1_Pos 31 /*!< LCD PAL155: I1 Position */
+#define LCD_PAL155_I1_Msk (0x01UL << LCD_PAL155_I1_Pos) /*!< LCD PAL155: I1 Mask */
+
+// --------------------------------------- LCD_PAL156 -------------------------------------------
+#define LCD_PAL156_R04_0_Pos 0 /*!< LCD PAL156: R04_0 Position */
+#define LCD_PAL156_R04_0_Msk (0x1fUL << LCD_PAL156_R04_0_Pos) /*!< LCD PAL156: R04_0 Mask */
+#define LCD_PAL156_G04_0_Pos 5 /*!< LCD PAL156: G04_0 Position */
+#define LCD_PAL156_G04_0_Msk (0x1fUL << LCD_PAL156_G04_0_Pos) /*!< LCD PAL156: G04_0 Mask */
+#define LCD_PAL156_B04_0_Pos 10 /*!< LCD PAL156: B04_0 Position */
+#define LCD_PAL156_B04_0_Msk (0x1fUL << LCD_PAL156_B04_0_Pos) /*!< LCD PAL156: B04_0 Mask */
+#define LCD_PAL156_I0_Pos 15 /*!< LCD PAL156: I0 Position */
+#define LCD_PAL156_I0_Msk (0x01UL << LCD_PAL156_I0_Pos) /*!< LCD PAL156: I0 Mask */
+#define LCD_PAL156_R14_0_Pos 16 /*!< LCD PAL156: R14_0 Position */
+#define LCD_PAL156_R14_0_Msk (0x1fUL << LCD_PAL156_R14_0_Pos) /*!< LCD PAL156: R14_0 Mask */
+#define LCD_PAL156_G14_0_Pos 21 /*!< LCD PAL156: G14_0 Position */
+#define LCD_PAL156_G14_0_Msk (0x1fUL << LCD_PAL156_G14_0_Pos) /*!< LCD PAL156: G14_0 Mask */
+#define LCD_PAL156_B14_0_Pos 26 /*!< LCD PAL156: B14_0 Position */
+#define LCD_PAL156_B14_0_Msk (0x1fUL << LCD_PAL156_B14_0_Pos) /*!< LCD PAL156: B14_0 Mask */
+#define LCD_PAL156_I1_Pos 31 /*!< LCD PAL156: I1 Position */
+#define LCD_PAL156_I1_Msk (0x01UL << LCD_PAL156_I1_Pos) /*!< LCD PAL156: I1 Mask */
+
+// --------------------------------------- LCD_PAL157 -------------------------------------------
+#define LCD_PAL157_R04_0_Pos 0 /*!< LCD PAL157: R04_0 Position */
+#define LCD_PAL157_R04_0_Msk (0x1fUL << LCD_PAL157_R04_0_Pos) /*!< LCD PAL157: R04_0 Mask */
+#define LCD_PAL157_G04_0_Pos 5 /*!< LCD PAL157: G04_0 Position */
+#define LCD_PAL157_G04_0_Msk (0x1fUL << LCD_PAL157_G04_0_Pos) /*!< LCD PAL157: G04_0 Mask */
+#define LCD_PAL157_B04_0_Pos 10 /*!< LCD PAL157: B04_0 Position */
+#define LCD_PAL157_B04_0_Msk (0x1fUL << LCD_PAL157_B04_0_Pos) /*!< LCD PAL157: B04_0 Mask */
+#define LCD_PAL157_I0_Pos 15 /*!< LCD PAL157: I0 Position */
+#define LCD_PAL157_I0_Msk (0x01UL << LCD_PAL157_I0_Pos) /*!< LCD PAL157: I0 Mask */
+#define LCD_PAL157_R14_0_Pos 16 /*!< LCD PAL157: R14_0 Position */
+#define LCD_PAL157_R14_0_Msk (0x1fUL << LCD_PAL157_R14_0_Pos) /*!< LCD PAL157: R14_0 Mask */
+#define LCD_PAL157_G14_0_Pos 21 /*!< LCD PAL157: G14_0 Position */
+#define LCD_PAL157_G14_0_Msk (0x1fUL << LCD_PAL157_G14_0_Pos) /*!< LCD PAL157: G14_0 Mask */
+#define LCD_PAL157_B14_0_Pos 26 /*!< LCD PAL157: B14_0 Position */
+#define LCD_PAL157_B14_0_Msk (0x1fUL << LCD_PAL157_B14_0_Pos) /*!< LCD PAL157: B14_0 Mask */
+#define LCD_PAL157_I1_Pos 31 /*!< LCD PAL157: I1 Position */
+#define LCD_PAL157_I1_Msk (0x01UL << LCD_PAL157_I1_Pos) /*!< LCD PAL157: I1 Mask */
+
+// --------------------------------------- LCD_PAL158 -------------------------------------------
+#define LCD_PAL158_R04_0_Pos 0 /*!< LCD PAL158: R04_0 Position */
+#define LCD_PAL158_R04_0_Msk (0x1fUL << LCD_PAL158_R04_0_Pos) /*!< LCD PAL158: R04_0 Mask */
+#define LCD_PAL158_G04_0_Pos 5 /*!< LCD PAL158: G04_0 Position */
+#define LCD_PAL158_G04_0_Msk (0x1fUL << LCD_PAL158_G04_0_Pos) /*!< LCD PAL158: G04_0 Mask */
+#define LCD_PAL158_B04_0_Pos 10 /*!< LCD PAL158: B04_0 Position */
+#define LCD_PAL158_B04_0_Msk (0x1fUL << LCD_PAL158_B04_0_Pos) /*!< LCD PAL158: B04_0 Mask */
+#define LCD_PAL158_I0_Pos 15 /*!< LCD PAL158: I0 Position */
+#define LCD_PAL158_I0_Msk (0x01UL << LCD_PAL158_I0_Pos) /*!< LCD PAL158: I0 Mask */
+#define LCD_PAL158_R14_0_Pos 16 /*!< LCD PAL158: R14_0 Position */
+#define LCD_PAL158_R14_0_Msk (0x1fUL << LCD_PAL158_R14_0_Pos) /*!< LCD PAL158: R14_0 Mask */
+#define LCD_PAL158_G14_0_Pos 21 /*!< LCD PAL158: G14_0 Position */
+#define LCD_PAL158_G14_0_Msk (0x1fUL << LCD_PAL158_G14_0_Pos) /*!< LCD PAL158: G14_0 Mask */
+#define LCD_PAL158_B14_0_Pos 26 /*!< LCD PAL158: B14_0 Position */
+#define LCD_PAL158_B14_0_Msk (0x1fUL << LCD_PAL158_B14_0_Pos) /*!< LCD PAL158: B14_0 Mask */
+#define LCD_PAL158_I1_Pos 31 /*!< LCD PAL158: I1 Position */
+#define LCD_PAL158_I1_Msk (0x01UL << LCD_PAL158_I1_Pos) /*!< LCD PAL158: I1 Mask */
+
+// --------------------------------------- LCD_PAL159 -------------------------------------------
+#define LCD_PAL159_R04_0_Pos 0 /*!< LCD PAL159: R04_0 Position */
+#define LCD_PAL159_R04_0_Msk (0x1fUL << LCD_PAL159_R04_0_Pos) /*!< LCD PAL159: R04_0 Mask */
+#define LCD_PAL159_G04_0_Pos 5 /*!< LCD PAL159: G04_0 Position */
+#define LCD_PAL159_G04_0_Msk (0x1fUL << LCD_PAL159_G04_0_Pos) /*!< LCD PAL159: G04_0 Mask */
+#define LCD_PAL159_B04_0_Pos 10 /*!< LCD PAL159: B04_0 Position */
+#define LCD_PAL159_B04_0_Msk (0x1fUL << LCD_PAL159_B04_0_Pos) /*!< LCD PAL159: B04_0 Mask */
+#define LCD_PAL159_I0_Pos 15 /*!< LCD PAL159: I0 Position */
+#define LCD_PAL159_I0_Msk (0x01UL << LCD_PAL159_I0_Pos) /*!< LCD PAL159: I0 Mask */
+#define LCD_PAL159_R14_0_Pos 16 /*!< LCD PAL159: R14_0 Position */
+#define LCD_PAL159_R14_0_Msk (0x1fUL << LCD_PAL159_R14_0_Pos) /*!< LCD PAL159: R14_0 Mask */
+#define LCD_PAL159_G14_0_Pos 21 /*!< LCD PAL159: G14_0 Position */
+#define LCD_PAL159_G14_0_Msk (0x1fUL << LCD_PAL159_G14_0_Pos) /*!< LCD PAL159: G14_0 Mask */
+#define LCD_PAL159_B14_0_Pos 26 /*!< LCD PAL159: B14_0 Position */
+#define LCD_PAL159_B14_0_Msk (0x1fUL << LCD_PAL159_B14_0_Pos) /*!< LCD PAL159: B14_0 Mask */
+#define LCD_PAL159_I1_Pos 31 /*!< LCD PAL159: I1 Position */
+#define LCD_PAL159_I1_Msk (0x01UL << LCD_PAL159_I1_Pos) /*!< LCD PAL159: I1 Mask */
+
+// --------------------------------------- LCD_PAL160 -------------------------------------------
+#define LCD_PAL160_R04_0_Pos 0 /*!< LCD PAL160: R04_0 Position */
+#define LCD_PAL160_R04_0_Msk (0x1fUL << LCD_PAL160_R04_0_Pos) /*!< LCD PAL160: R04_0 Mask */
+#define LCD_PAL160_G04_0_Pos 5 /*!< LCD PAL160: G04_0 Position */
+#define LCD_PAL160_G04_0_Msk (0x1fUL << LCD_PAL160_G04_0_Pos) /*!< LCD PAL160: G04_0 Mask */
+#define LCD_PAL160_B04_0_Pos 10 /*!< LCD PAL160: B04_0 Position */
+#define LCD_PAL160_B04_0_Msk (0x1fUL << LCD_PAL160_B04_0_Pos) /*!< LCD PAL160: B04_0 Mask */
+#define LCD_PAL160_I0_Pos 15 /*!< LCD PAL160: I0 Position */
+#define LCD_PAL160_I0_Msk (0x01UL << LCD_PAL160_I0_Pos) /*!< LCD PAL160: I0 Mask */
+#define LCD_PAL160_R14_0_Pos 16 /*!< LCD PAL160: R14_0 Position */
+#define LCD_PAL160_R14_0_Msk (0x1fUL << LCD_PAL160_R14_0_Pos) /*!< LCD PAL160: R14_0 Mask */
+#define LCD_PAL160_G14_0_Pos 21 /*!< LCD PAL160: G14_0 Position */
+#define LCD_PAL160_G14_0_Msk (0x1fUL << LCD_PAL160_G14_0_Pos) /*!< LCD PAL160: G14_0 Mask */
+#define LCD_PAL160_B14_0_Pos 26 /*!< LCD PAL160: B14_0 Position */
+#define LCD_PAL160_B14_0_Msk (0x1fUL << LCD_PAL160_B14_0_Pos) /*!< LCD PAL160: B14_0 Mask */
+#define LCD_PAL160_I1_Pos 31 /*!< LCD PAL160: I1 Position */
+#define LCD_PAL160_I1_Msk (0x01UL << LCD_PAL160_I1_Pos) /*!< LCD PAL160: I1 Mask */
+
+// --------------------------------------- LCD_PAL161 -------------------------------------------
+#define LCD_PAL161_R04_0_Pos 0 /*!< LCD PAL161: R04_0 Position */
+#define LCD_PAL161_R04_0_Msk (0x1fUL << LCD_PAL161_R04_0_Pos) /*!< LCD PAL161: R04_0 Mask */
+#define LCD_PAL161_G04_0_Pos 5 /*!< LCD PAL161: G04_0 Position */
+#define LCD_PAL161_G04_0_Msk (0x1fUL << LCD_PAL161_G04_0_Pos) /*!< LCD PAL161: G04_0 Mask */
+#define LCD_PAL161_B04_0_Pos 10 /*!< LCD PAL161: B04_0 Position */
+#define LCD_PAL161_B04_0_Msk (0x1fUL << LCD_PAL161_B04_0_Pos) /*!< LCD PAL161: B04_0 Mask */
+#define LCD_PAL161_I0_Pos 15 /*!< LCD PAL161: I0 Position */
+#define LCD_PAL161_I0_Msk (0x01UL << LCD_PAL161_I0_Pos) /*!< LCD PAL161: I0 Mask */
+#define LCD_PAL161_R14_0_Pos 16 /*!< LCD PAL161: R14_0 Position */
+#define LCD_PAL161_R14_0_Msk (0x1fUL << LCD_PAL161_R14_0_Pos) /*!< LCD PAL161: R14_0 Mask */
+#define LCD_PAL161_G14_0_Pos 21 /*!< LCD PAL161: G14_0 Position */
+#define LCD_PAL161_G14_0_Msk (0x1fUL << LCD_PAL161_G14_0_Pos) /*!< LCD PAL161: G14_0 Mask */
+#define LCD_PAL161_B14_0_Pos 26 /*!< LCD PAL161: B14_0 Position */
+#define LCD_PAL161_B14_0_Msk (0x1fUL << LCD_PAL161_B14_0_Pos) /*!< LCD PAL161: B14_0 Mask */
+#define LCD_PAL161_I1_Pos 31 /*!< LCD PAL161: I1 Position */
+#define LCD_PAL161_I1_Msk (0x01UL << LCD_PAL161_I1_Pos) /*!< LCD PAL161: I1 Mask */
+
+// --------------------------------------- LCD_PAL162 -------------------------------------------
+#define LCD_PAL162_R04_0_Pos 0 /*!< LCD PAL162: R04_0 Position */
+#define LCD_PAL162_R04_0_Msk (0x1fUL << LCD_PAL162_R04_0_Pos) /*!< LCD PAL162: R04_0 Mask */
+#define LCD_PAL162_G04_0_Pos 5 /*!< LCD PAL162: G04_0 Position */
+#define LCD_PAL162_G04_0_Msk (0x1fUL << LCD_PAL162_G04_0_Pos) /*!< LCD PAL162: G04_0 Mask */
+#define LCD_PAL162_B04_0_Pos 10 /*!< LCD PAL162: B04_0 Position */
+#define LCD_PAL162_B04_0_Msk (0x1fUL << LCD_PAL162_B04_0_Pos) /*!< LCD PAL162: B04_0 Mask */
+#define LCD_PAL162_I0_Pos 15 /*!< LCD PAL162: I0 Position */
+#define LCD_PAL162_I0_Msk (0x01UL << LCD_PAL162_I0_Pos) /*!< LCD PAL162: I0 Mask */
+#define LCD_PAL162_R14_0_Pos 16 /*!< LCD PAL162: R14_0 Position */
+#define LCD_PAL162_R14_0_Msk (0x1fUL << LCD_PAL162_R14_0_Pos) /*!< LCD PAL162: R14_0 Mask */
+#define LCD_PAL162_G14_0_Pos 21 /*!< LCD PAL162: G14_0 Position */
+#define LCD_PAL162_G14_0_Msk (0x1fUL << LCD_PAL162_G14_0_Pos) /*!< LCD PAL162: G14_0 Mask */
+#define LCD_PAL162_B14_0_Pos 26 /*!< LCD PAL162: B14_0 Position */
+#define LCD_PAL162_B14_0_Msk (0x1fUL << LCD_PAL162_B14_0_Pos) /*!< LCD PAL162: B14_0 Mask */
+#define LCD_PAL162_I1_Pos 31 /*!< LCD PAL162: I1 Position */
+#define LCD_PAL162_I1_Msk (0x01UL << LCD_PAL162_I1_Pos) /*!< LCD PAL162: I1 Mask */
+
+// --------------------------------------- LCD_PAL163 -------------------------------------------
+#define LCD_PAL163_R04_0_Pos 0 /*!< LCD PAL163: R04_0 Position */
+#define LCD_PAL163_R04_0_Msk (0x1fUL << LCD_PAL163_R04_0_Pos) /*!< LCD PAL163: R04_0 Mask */
+#define LCD_PAL163_G04_0_Pos 5 /*!< LCD PAL163: G04_0 Position */
+#define LCD_PAL163_G04_0_Msk (0x1fUL << LCD_PAL163_G04_0_Pos) /*!< LCD PAL163: G04_0 Mask */
+#define LCD_PAL163_B04_0_Pos 10 /*!< LCD PAL163: B04_0 Position */
+#define LCD_PAL163_B04_0_Msk (0x1fUL << LCD_PAL163_B04_0_Pos) /*!< LCD PAL163: B04_0 Mask */
+#define LCD_PAL163_I0_Pos 15 /*!< LCD PAL163: I0 Position */
+#define LCD_PAL163_I0_Msk (0x01UL << LCD_PAL163_I0_Pos) /*!< LCD PAL163: I0 Mask */
+#define LCD_PAL163_R14_0_Pos 16 /*!< LCD PAL163: R14_0 Position */
+#define LCD_PAL163_R14_0_Msk (0x1fUL << LCD_PAL163_R14_0_Pos) /*!< LCD PAL163: R14_0 Mask */
+#define LCD_PAL163_G14_0_Pos 21 /*!< LCD PAL163: G14_0 Position */
+#define LCD_PAL163_G14_0_Msk (0x1fUL << LCD_PAL163_G14_0_Pos) /*!< LCD PAL163: G14_0 Mask */
+#define LCD_PAL163_B14_0_Pos 26 /*!< LCD PAL163: B14_0 Position */
+#define LCD_PAL163_B14_0_Msk (0x1fUL << LCD_PAL163_B14_0_Pos) /*!< LCD PAL163: B14_0 Mask */
+#define LCD_PAL163_I1_Pos 31 /*!< LCD PAL163: I1 Position */
+#define LCD_PAL163_I1_Msk (0x01UL << LCD_PAL163_I1_Pos) /*!< LCD PAL163: I1 Mask */
+
+// --------------------------------------- LCD_PAL164 -------------------------------------------
+#define LCD_PAL164_R04_0_Pos 0 /*!< LCD PAL164: R04_0 Position */
+#define LCD_PAL164_R04_0_Msk (0x1fUL << LCD_PAL164_R04_0_Pos) /*!< LCD PAL164: R04_0 Mask */
+#define LCD_PAL164_G04_0_Pos 5 /*!< LCD PAL164: G04_0 Position */
+#define LCD_PAL164_G04_0_Msk (0x1fUL << LCD_PAL164_G04_0_Pos) /*!< LCD PAL164: G04_0 Mask */
+#define LCD_PAL164_B04_0_Pos 10 /*!< LCD PAL164: B04_0 Position */
+#define LCD_PAL164_B04_0_Msk (0x1fUL << LCD_PAL164_B04_0_Pos) /*!< LCD PAL164: B04_0 Mask */
+#define LCD_PAL164_I0_Pos 15 /*!< LCD PAL164: I0 Position */
+#define LCD_PAL164_I0_Msk (0x01UL << LCD_PAL164_I0_Pos) /*!< LCD PAL164: I0 Mask */
+#define LCD_PAL164_R14_0_Pos 16 /*!< LCD PAL164: R14_0 Position */
+#define LCD_PAL164_R14_0_Msk (0x1fUL << LCD_PAL164_R14_0_Pos) /*!< LCD PAL164: R14_0 Mask */
+#define LCD_PAL164_G14_0_Pos 21 /*!< LCD PAL164: G14_0 Position */
+#define LCD_PAL164_G14_0_Msk (0x1fUL << LCD_PAL164_G14_0_Pos) /*!< LCD PAL164: G14_0 Mask */
+#define LCD_PAL164_B14_0_Pos 26 /*!< LCD PAL164: B14_0 Position */
+#define LCD_PAL164_B14_0_Msk (0x1fUL << LCD_PAL164_B14_0_Pos) /*!< LCD PAL164: B14_0 Mask */
+#define LCD_PAL164_I1_Pos 31 /*!< LCD PAL164: I1 Position */
+#define LCD_PAL164_I1_Msk (0x01UL << LCD_PAL164_I1_Pos) /*!< LCD PAL164: I1 Mask */
+
+// --------------------------------------- LCD_PAL165 -------------------------------------------
+#define LCD_PAL165_R04_0_Pos 0 /*!< LCD PAL165: R04_0 Position */
+#define LCD_PAL165_R04_0_Msk (0x1fUL << LCD_PAL165_R04_0_Pos) /*!< LCD PAL165: R04_0 Mask */
+#define LCD_PAL165_G04_0_Pos 5 /*!< LCD PAL165: G04_0 Position */
+#define LCD_PAL165_G04_0_Msk (0x1fUL << LCD_PAL165_G04_0_Pos) /*!< LCD PAL165: G04_0 Mask */
+#define LCD_PAL165_B04_0_Pos 10 /*!< LCD PAL165: B04_0 Position */
+#define LCD_PAL165_B04_0_Msk (0x1fUL << LCD_PAL165_B04_0_Pos) /*!< LCD PAL165: B04_0 Mask */
+#define LCD_PAL165_I0_Pos 15 /*!< LCD PAL165: I0 Position */
+#define LCD_PAL165_I0_Msk (0x01UL << LCD_PAL165_I0_Pos) /*!< LCD PAL165: I0 Mask */
+#define LCD_PAL165_R14_0_Pos 16 /*!< LCD PAL165: R14_0 Position */
+#define LCD_PAL165_R14_0_Msk (0x1fUL << LCD_PAL165_R14_0_Pos) /*!< LCD PAL165: R14_0 Mask */
+#define LCD_PAL165_G14_0_Pos 21 /*!< LCD PAL165: G14_0 Position */
+#define LCD_PAL165_G14_0_Msk (0x1fUL << LCD_PAL165_G14_0_Pos) /*!< LCD PAL165: G14_0 Mask */
+#define LCD_PAL165_B14_0_Pos 26 /*!< LCD PAL165: B14_0 Position */
+#define LCD_PAL165_B14_0_Msk (0x1fUL << LCD_PAL165_B14_0_Pos) /*!< LCD PAL165: B14_0 Mask */
+#define LCD_PAL165_I1_Pos 31 /*!< LCD PAL165: I1 Position */
+#define LCD_PAL165_I1_Msk (0x01UL << LCD_PAL165_I1_Pos) /*!< LCD PAL165: I1 Mask */
+
+// --------------------------------------- LCD_PAL166 -------------------------------------------
+#define LCD_PAL166_R04_0_Pos 0 /*!< LCD PAL166: R04_0 Position */
+#define LCD_PAL166_R04_0_Msk (0x1fUL << LCD_PAL166_R04_0_Pos) /*!< LCD PAL166: R04_0 Mask */
+#define LCD_PAL166_G04_0_Pos 5 /*!< LCD PAL166: G04_0 Position */
+#define LCD_PAL166_G04_0_Msk (0x1fUL << LCD_PAL166_G04_0_Pos) /*!< LCD PAL166: G04_0 Mask */
+#define LCD_PAL166_B04_0_Pos 10 /*!< LCD PAL166: B04_0 Position */
+#define LCD_PAL166_B04_0_Msk (0x1fUL << LCD_PAL166_B04_0_Pos) /*!< LCD PAL166: B04_0 Mask */
+#define LCD_PAL166_I0_Pos 15 /*!< LCD PAL166: I0 Position */
+#define LCD_PAL166_I0_Msk (0x01UL << LCD_PAL166_I0_Pos) /*!< LCD PAL166: I0 Mask */
+#define LCD_PAL166_R14_0_Pos 16 /*!< LCD PAL166: R14_0 Position */
+#define LCD_PAL166_R14_0_Msk (0x1fUL << LCD_PAL166_R14_0_Pos) /*!< LCD PAL166: R14_0 Mask */
+#define LCD_PAL166_G14_0_Pos 21 /*!< LCD PAL166: G14_0 Position */
+#define LCD_PAL166_G14_0_Msk (0x1fUL << LCD_PAL166_G14_0_Pos) /*!< LCD PAL166: G14_0 Mask */
+#define LCD_PAL166_B14_0_Pos 26 /*!< LCD PAL166: B14_0 Position */
+#define LCD_PAL166_B14_0_Msk (0x1fUL << LCD_PAL166_B14_0_Pos) /*!< LCD PAL166: B14_0 Mask */
+#define LCD_PAL166_I1_Pos 31 /*!< LCD PAL166: I1 Position */
+#define LCD_PAL166_I1_Msk (0x01UL << LCD_PAL166_I1_Pos) /*!< LCD PAL166: I1 Mask */
+
+// --------------------------------------- LCD_PAL167 -------------------------------------------
+#define LCD_PAL167_R04_0_Pos 0 /*!< LCD PAL167: R04_0 Position */
+#define LCD_PAL167_R04_0_Msk (0x1fUL << LCD_PAL167_R04_0_Pos) /*!< LCD PAL167: R04_0 Mask */
+#define LCD_PAL167_G04_0_Pos 5 /*!< LCD PAL167: G04_0 Position */
+#define LCD_PAL167_G04_0_Msk (0x1fUL << LCD_PAL167_G04_0_Pos) /*!< LCD PAL167: G04_0 Mask */
+#define LCD_PAL167_B04_0_Pos 10 /*!< LCD PAL167: B04_0 Position */
+#define LCD_PAL167_B04_0_Msk (0x1fUL << LCD_PAL167_B04_0_Pos) /*!< LCD PAL167: B04_0 Mask */
+#define LCD_PAL167_I0_Pos 15 /*!< LCD PAL167: I0 Position */
+#define LCD_PAL167_I0_Msk (0x01UL << LCD_PAL167_I0_Pos) /*!< LCD PAL167: I0 Mask */
+#define LCD_PAL167_R14_0_Pos 16 /*!< LCD PAL167: R14_0 Position */
+#define LCD_PAL167_R14_0_Msk (0x1fUL << LCD_PAL167_R14_0_Pos) /*!< LCD PAL167: R14_0 Mask */
+#define LCD_PAL167_G14_0_Pos 21 /*!< LCD PAL167: G14_0 Position */
+#define LCD_PAL167_G14_0_Msk (0x1fUL << LCD_PAL167_G14_0_Pos) /*!< LCD PAL167: G14_0 Mask */
+#define LCD_PAL167_B14_0_Pos 26 /*!< LCD PAL167: B14_0 Position */
+#define LCD_PAL167_B14_0_Msk (0x1fUL << LCD_PAL167_B14_0_Pos) /*!< LCD PAL167: B14_0 Mask */
+#define LCD_PAL167_I1_Pos 31 /*!< LCD PAL167: I1 Position */
+#define LCD_PAL167_I1_Msk (0x01UL << LCD_PAL167_I1_Pos) /*!< LCD PAL167: I1 Mask */
+
+// --------------------------------------- LCD_PAL168 -------------------------------------------
+#define LCD_PAL168_R04_0_Pos 0 /*!< LCD PAL168: R04_0 Position */
+#define LCD_PAL168_R04_0_Msk (0x1fUL << LCD_PAL168_R04_0_Pos) /*!< LCD PAL168: R04_0 Mask */
+#define LCD_PAL168_G04_0_Pos 5 /*!< LCD PAL168: G04_0 Position */
+#define LCD_PAL168_G04_0_Msk (0x1fUL << LCD_PAL168_G04_0_Pos) /*!< LCD PAL168: G04_0 Mask */
+#define LCD_PAL168_B04_0_Pos 10 /*!< LCD PAL168: B04_0 Position */
+#define LCD_PAL168_B04_0_Msk (0x1fUL << LCD_PAL168_B04_0_Pos) /*!< LCD PAL168: B04_0 Mask */
+#define LCD_PAL168_I0_Pos 15 /*!< LCD PAL168: I0 Position */
+#define LCD_PAL168_I0_Msk (0x01UL << LCD_PAL168_I0_Pos) /*!< LCD PAL168: I0 Mask */
+#define LCD_PAL168_R14_0_Pos 16 /*!< LCD PAL168: R14_0 Position */
+#define LCD_PAL168_R14_0_Msk (0x1fUL << LCD_PAL168_R14_0_Pos) /*!< LCD PAL168: R14_0 Mask */
+#define LCD_PAL168_G14_0_Pos 21 /*!< LCD PAL168: G14_0 Position */
+#define LCD_PAL168_G14_0_Msk (0x1fUL << LCD_PAL168_G14_0_Pos) /*!< LCD PAL168: G14_0 Mask */
+#define LCD_PAL168_B14_0_Pos 26 /*!< LCD PAL168: B14_0 Position */
+#define LCD_PAL168_B14_0_Msk (0x1fUL << LCD_PAL168_B14_0_Pos) /*!< LCD PAL168: B14_0 Mask */
+#define LCD_PAL168_I1_Pos 31 /*!< LCD PAL168: I1 Position */
+#define LCD_PAL168_I1_Msk (0x01UL << LCD_PAL168_I1_Pos) /*!< LCD PAL168: I1 Mask */
+
+// --------------------------------------- LCD_PAL169 -------------------------------------------
+#define LCD_PAL169_R04_0_Pos 0 /*!< LCD PAL169: R04_0 Position */
+#define LCD_PAL169_R04_0_Msk (0x1fUL << LCD_PAL169_R04_0_Pos) /*!< LCD PAL169: R04_0 Mask */
+#define LCD_PAL169_G04_0_Pos 5 /*!< LCD PAL169: G04_0 Position */
+#define LCD_PAL169_G04_0_Msk (0x1fUL << LCD_PAL169_G04_0_Pos) /*!< LCD PAL169: G04_0 Mask */
+#define LCD_PAL169_B04_0_Pos 10 /*!< LCD PAL169: B04_0 Position */
+#define LCD_PAL169_B04_0_Msk (0x1fUL << LCD_PAL169_B04_0_Pos) /*!< LCD PAL169: B04_0 Mask */
+#define LCD_PAL169_I0_Pos 15 /*!< LCD PAL169: I0 Position */
+#define LCD_PAL169_I0_Msk (0x01UL << LCD_PAL169_I0_Pos) /*!< LCD PAL169: I0 Mask */
+#define LCD_PAL169_R14_0_Pos 16 /*!< LCD PAL169: R14_0 Position */
+#define LCD_PAL169_R14_0_Msk (0x1fUL << LCD_PAL169_R14_0_Pos) /*!< LCD PAL169: R14_0 Mask */
+#define LCD_PAL169_G14_0_Pos 21 /*!< LCD PAL169: G14_0 Position */
+#define LCD_PAL169_G14_0_Msk (0x1fUL << LCD_PAL169_G14_0_Pos) /*!< LCD PAL169: G14_0 Mask */
+#define LCD_PAL169_B14_0_Pos 26 /*!< LCD PAL169: B14_0 Position */
+#define LCD_PAL169_B14_0_Msk (0x1fUL << LCD_PAL169_B14_0_Pos) /*!< LCD PAL169: B14_0 Mask */
+#define LCD_PAL169_I1_Pos 31 /*!< LCD PAL169: I1 Position */
+#define LCD_PAL169_I1_Msk (0x01UL << LCD_PAL169_I1_Pos) /*!< LCD PAL169: I1 Mask */
+
+// --------------------------------------- LCD_PAL170 -------------------------------------------
+#define LCD_PAL170_R04_0_Pos 0 /*!< LCD PAL170: R04_0 Position */
+#define LCD_PAL170_R04_0_Msk (0x1fUL << LCD_PAL170_R04_0_Pos) /*!< LCD PAL170: R04_0 Mask */
+#define LCD_PAL170_G04_0_Pos 5 /*!< LCD PAL170: G04_0 Position */
+#define LCD_PAL170_G04_0_Msk (0x1fUL << LCD_PAL170_G04_0_Pos) /*!< LCD PAL170: G04_0 Mask */
+#define LCD_PAL170_B04_0_Pos 10 /*!< LCD PAL170: B04_0 Position */
+#define LCD_PAL170_B04_0_Msk (0x1fUL << LCD_PAL170_B04_0_Pos) /*!< LCD PAL170: B04_0 Mask */
+#define LCD_PAL170_I0_Pos 15 /*!< LCD PAL170: I0 Position */
+#define LCD_PAL170_I0_Msk (0x01UL << LCD_PAL170_I0_Pos) /*!< LCD PAL170: I0 Mask */
+#define LCD_PAL170_R14_0_Pos 16 /*!< LCD PAL170: R14_0 Position */
+#define LCD_PAL170_R14_0_Msk (0x1fUL << LCD_PAL170_R14_0_Pos) /*!< LCD PAL170: R14_0 Mask */
+#define LCD_PAL170_G14_0_Pos 21 /*!< LCD PAL170: G14_0 Position */
+#define LCD_PAL170_G14_0_Msk (0x1fUL << LCD_PAL170_G14_0_Pos) /*!< LCD PAL170: G14_0 Mask */
+#define LCD_PAL170_B14_0_Pos 26 /*!< LCD PAL170: B14_0 Position */
+#define LCD_PAL170_B14_0_Msk (0x1fUL << LCD_PAL170_B14_0_Pos) /*!< LCD PAL170: B14_0 Mask */
+#define LCD_PAL170_I1_Pos 31 /*!< LCD PAL170: I1 Position */
+#define LCD_PAL170_I1_Msk (0x01UL << LCD_PAL170_I1_Pos) /*!< LCD PAL170: I1 Mask */
+
+// --------------------------------------- LCD_PAL171 -------------------------------------------
+#define LCD_PAL171_R04_0_Pos 0 /*!< LCD PAL171: R04_0 Position */
+#define LCD_PAL171_R04_0_Msk (0x1fUL << LCD_PAL171_R04_0_Pos) /*!< LCD PAL171: R04_0 Mask */
+#define LCD_PAL171_G04_0_Pos 5 /*!< LCD PAL171: G04_0 Position */
+#define LCD_PAL171_G04_0_Msk (0x1fUL << LCD_PAL171_G04_0_Pos) /*!< LCD PAL171: G04_0 Mask */
+#define LCD_PAL171_B04_0_Pos 10 /*!< LCD PAL171: B04_0 Position */
+#define LCD_PAL171_B04_0_Msk (0x1fUL << LCD_PAL171_B04_0_Pos) /*!< LCD PAL171: B04_0 Mask */
+#define LCD_PAL171_I0_Pos 15 /*!< LCD PAL171: I0 Position */
+#define LCD_PAL171_I0_Msk (0x01UL << LCD_PAL171_I0_Pos) /*!< LCD PAL171: I0 Mask */
+#define LCD_PAL171_R14_0_Pos 16 /*!< LCD PAL171: R14_0 Position */
+#define LCD_PAL171_R14_0_Msk (0x1fUL << LCD_PAL171_R14_0_Pos) /*!< LCD PAL171: R14_0 Mask */
+#define LCD_PAL171_G14_0_Pos 21 /*!< LCD PAL171: G14_0 Position */
+#define LCD_PAL171_G14_0_Msk (0x1fUL << LCD_PAL171_G14_0_Pos) /*!< LCD PAL171: G14_0 Mask */
+#define LCD_PAL171_B14_0_Pos 26 /*!< LCD PAL171: B14_0 Position */
+#define LCD_PAL171_B14_0_Msk (0x1fUL << LCD_PAL171_B14_0_Pos) /*!< LCD PAL171: B14_0 Mask */
+#define LCD_PAL171_I1_Pos 31 /*!< LCD PAL171: I1 Position */
+#define LCD_PAL171_I1_Msk (0x01UL << LCD_PAL171_I1_Pos) /*!< LCD PAL171: I1 Mask */
+
+// --------------------------------------- LCD_PAL172 -------------------------------------------
+#define LCD_PAL172_R04_0_Pos 0 /*!< LCD PAL172: R04_0 Position */
+#define LCD_PAL172_R04_0_Msk (0x1fUL << LCD_PAL172_R04_0_Pos) /*!< LCD PAL172: R04_0 Mask */
+#define LCD_PAL172_G04_0_Pos 5 /*!< LCD PAL172: G04_0 Position */
+#define LCD_PAL172_G04_0_Msk (0x1fUL << LCD_PAL172_G04_0_Pos) /*!< LCD PAL172: G04_0 Mask */
+#define LCD_PAL172_B04_0_Pos 10 /*!< LCD PAL172: B04_0 Position */
+#define LCD_PAL172_B04_0_Msk (0x1fUL << LCD_PAL172_B04_0_Pos) /*!< LCD PAL172: B04_0 Mask */
+#define LCD_PAL172_I0_Pos 15 /*!< LCD PAL172: I0 Position */
+#define LCD_PAL172_I0_Msk (0x01UL << LCD_PAL172_I0_Pos) /*!< LCD PAL172: I0 Mask */
+#define LCD_PAL172_R14_0_Pos 16 /*!< LCD PAL172: R14_0 Position */
+#define LCD_PAL172_R14_0_Msk (0x1fUL << LCD_PAL172_R14_0_Pos) /*!< LCD PAL172: R14_0 Mask */
+#define LCD_PAL172_G14_0_Pos 21 /*!< LCD PAL172: G14_0 Position */
+#define LCD_PAL172_G14_0_Msk (0x1fUL << LCD_PAL172_G14_0_Pos) /*!< LCD PAL172: G14_0 Mask */
+#define LCD_PAL172_B14_0_Pos 26 /*!< LCD PAL172: B14_0 Position */
+#define LCD_PAL172_B14_0_Msk (0x1fUL << LCD_PAL172_B14_0_Pos) /*!< LCD PAL172: B14_0 Mask */
+#define LCD_PAL172_I1_Pos 31 /*!< LCD PAL172: I1 Position */
+#define LCD_PAL172_I1_Msk (0x01UL << LCD_PAL172_I1_Pos) /*!< LCD PAL172: I1 Mask */
+
+// --------------------------------------- LCD_PAL173 -------------------------------------------
+#define LCD_PAL173_R04_0_Pos 0 /*!< LCD PAL173: R04_0 Position */
+#define LCD_PAL173_R04_0_Msk (0x1fUL << LCD_PAL173_R04_0_Pos) /*!< LCD PAL173: R04_0 Mask */
+#define LCD_PAL173_G04_0_Pos 5 /*!< LCD PAL173: G04_0 Position */
+#define LCD_PAL173_G04_0_Msk (0x1fUL << LCD_PAL173_G04_0_Pos) /*!< LCD PAL173: G04_0 Mask */
+#define LCD_PAL173_B04_0_Pos 10 /*!< LCD PAL173: B04_0 Position */
+#define LCD_PAL173_B04_0_Msk (0x1fUL << LCD_PAL173_B04_0_Pos) /*!< LCD PAL173: B04_0 Mask */
+#define LCD_PAL173_I0_Pos 15 /*!< LCD PAL173: I0 Position */
+#define LCD_PAL173_I0_Msk (0x01UL << LCD_PAL173_I0_Pos) /*!< LCD PAL173: I0 Mask */
+#define LCD_PAL173_R14_0_Pos 16 /*!< LCD PAL173: R14_0 Position */
+#define LCD_PAL173_R14_0_Msk (0x1fUL << LCD_PAL173_R14_0_Pos) /*!< LCD PAL173: R14_0 Mask */
+#define LCD_PAL173_G14_0_Pos 21 /*!< LCD PAL173: G14_0 Position */
+#define LCD_PAL173_G14_0_Msk (0x1fUL << LCD_PAL173_G14_0_Pos) /*!< LCD PAL173: G14_0 Mask */
+#define LCD_PAL173_B14_0_Pos 26 /*!< LCD PAL173: B14_0 Position */
+#define LCD_PAL173_B14_0_Msk (0x1fUL << LCD_PAL173_B14_0_Pos) /*!< LCD PAL173: B14_0 Mask */
+#define LCD_PAL173_I1_Pos 31 /*!< LCD PAL173: I1 Position */
+#define LCD_PAL173_I1_Msk (0x01UL << LCD_PAL173_I1_Pos) /*!< LCD PAL173: I1 Mask */
+
+// --------------------------------------- LCD_PAL174 -------------------------------------------
+#define LCD_PAL174_R04_0_Pos 0 /*!< LCD PAL174: R04_0 Position */
+#define LCD_PAL174_R04_0_Msk (0x1fUL << LCD_PAL174_R04_0_Pos) /*!< LCD PAL174: R04_0 Mask */
+#define LCD_PAL174_G04_0_Pos 5 /*!< LCD PAL174: G04_0 Position */
+#define LCD_PAL174_G04_0_Msk (0x1fUL << LCD_PAL174_G04_0_Pos) /*!< LCD PAL174: G04_0 Mask */
+#define LCD_PAL174_B04_0_Pos 10 /*!< LCD PAL174: B04_0 Position */
+#define LCD_PAL174_B04_0_Msk (0x1fUL << LCD_PAL174_B04_0_Pos) /*!< LCD PAL174: B04_0 Mask */
+#define LCD_PAL174_I0_Pos 15 /*!< LCD PAL174: I0 Position */
+#define LCD_PAL174_I0_Msk (0x01UL << LCD_PAL174_I0_Pos) /*!< LCD PAL174: I0 Mask */
+#define LCD_PAL174_R14_0_Pos 16 /*!< LCD PAL174: R14_0 Position */
+#define LCD_PAL174_R14_0_Msk (0x1fUL << LCD_PAL174_R14_0_Pos) /*!< LCD PAL174: R14_0 Mask */
+#define LCD_PAL174_G14_0_Pos 21 /*!< LCD PAL174: G14_0 Position */
+#define LCD_PAL174_G14_0_Msk (0x1fUL << LCD_PAL174_G14_0_Pos) /*!< LCD PAL174: G14_0 Mask */
+#define LCD_PAL174_B14_0_Pos 26 /*!< LCD PAL174: B14_0 Position */
+#define LCD_PAL174_B14_0_Msk (0x1fUL << LCD_PAL174_B14_0_Pos) /*!< LCD PAL174: B14_0 Mask */
+#define LCD_PAL174_I1_Pos 31 /*!< LCD PAL174: I1 Position */
+#define LCD_PAL174_I1_Msk (0x01UL << LCD_PAL174_I1_Pos) /*!< LCD PAL174: I1 Mask */
+
+// --------------------------------------- LCD_PAL175 -------------------------------------------
+#define LCD_PAL175_R04_0_Pos 0 /*!< LCD PAL175: R04_0 Position */
+#define LCD_PAL175_R04_0_Msk (0x1fUL << LCD_PAL175_R04_0_Pos) /*!< LCD PAL175: R04_0 Mask */
+#define LCD_PAL175_G04_0_Pos 5 /*!< LCD PAL175: G04_0 Position */
+#define LCD_PAL175_G04_0_Msk (0x1fUL << LCD_PAL175_G04_0_Pos) /*!< LCD PAL175: G04_0 Mask */
+#define LCD_PAL175_B04_0_Pos 10 /*!< LCD PAL175: B04_0 Position */
+#define LCD_PAL175_B04_0_Msk (0x1fUL << LCD_PAL175_B04_0_Pos) /*!< LCD PAL175: B04_0 Mask */
+#define LCD_PAL175_I0_Pos 15 /*!< LCD PAL175: I0 Position */
+#define LCD_PAL175_I0_Msk (0x01UL << LCD_PAL175_I0_Pos) /*!< LCD PAL175: I0 Mask */
+#define LCD_PAL175_R14_0_Pos 16 /*!< LCD PAL175: R14_0 Position */
+#define LCD_PAL175_R14_0_Msk (0x1fUL << LCD_PAL175_R14_0_Pos) /*!< LCD PAL175: R14_0 Mask */
+#define LCD_PAL175_G14_0_Pos 21 /*!< LCD PAL175: G14_0 Position */
+#define LCD_PAL175_G14_0_Msk (0x1fUL << LCD_PAL175_G14_0_Pos) /*!< LCD PAL175: G14_0 Mask */
+#define LCD_PAL175_B14_0_Pos 26 /*!< LCD PAL175: B14_0 Position */
+#define LCD_PAL175_B14_0_Msk (0x1fUL << LCD_PAL175_B14_0_Pos) /*!< LCD PAL175: B14_0 Mask */
+#define LCD_PAL175_I1_Pos 31 /*!< LCD PAL175: I1 Position */
+#define LCD_PAL175_I1_Msk (0x01UL << LCD_PAL175_I1_Pos) /*!< LCD PAL175: I1 Mask */
+
+// --------------------------------------- LCD_PAL176 -------------------------------------------
+#define LCD_PAL176_R04_0_Pos 0 /*!< LCD PAL176: R04_0 Position */
+#define LCD_PAL176_R04_0_Msk (0x1fUL << LCD_PAL176_R04_0_Pos) /*!< LCD PAL176: R04_0 Mask */
+#define LCD_PAL176_G04_0_Pos 5 /*!< LCD PAL176: G04_0 Position */
+#define LCD_PAL176_G04_0_Msk (0x1fUL << LCD_PAL176_G04_0_Pos) /*!< LCD PAL176: G04_0 Mask */
+#define LCD_PAL176_B04_0_Pos 10 /*!< LCD PAL176: B04_0 Position */
+#define LCD_PAL176_B04_0_Msk (0x1fUL << LCD_PAL176_B04_0_Pos) /*!< LCD PAL176: B04_0 Mask */
+#define LCD_PAL176_I0_Pos 15 /*!< LCD PAL176: I0 Position */
+#define LCD_PAL176_I0_Msk (0x01UL << LCD_PAL176_I0_Pos) /*!< LCD PAL176: I0 Mask */
+#define LCD_PAL176_R14_0_Pos 16 /*!< LCD PAL176: R14_0 Position */
+#define LCD_PAL176_R14_0_Msk (0x1fUL << LCD_PAL176_R14_0_Pos) /*!< LCD PAL176: R14_0 Mask */
+#define LCD_PAL176_G14_0_Pos 21 /*!< LCD PAL176: G14_0 Position */
+#define LCD_PAL176_G14_0_Msk (0x1fUL << LCD_PAL176_G14_0_Pos) /*!< LCD PAL176: G14_0 Mask */
+#define LCD_PAL176_B14_0_Pos 26 /*!< LCD PAL176: B14_0 Position */
+#define LCD_PAL176_B14_0_Msk (0x1fUL << LCD_PAL176_B14_0_Pos) /*!< LCD PAL176: B14_0 Mask */
+#define LCD_PAL176_I1_Pos 31 /*!< LCD PAL176: I1 Position */
+#define LCD_PAL176_I1_Msk (0x01UL << LCD_PAL176_I1_Pos) /*!< LCD PAL176: I1 Mask */
+
+// --------------------------------------- LCD_PAL177 -------------------------------------------
+#define LCD_PAL177_R04_0_Pos 0 /*!< LCD PAL177: R04_0 Position */
+#define LCD_PAL177_R04_0_Msk (0x1fUL << LCD_PAL177_R04_0_Pos) /*!< LCD PAL177: R04_0 Mask */
+#define LCD_PAL177_G04_0_Pos 5 /*!< LCD PAL177: G04_0 Position */
+#define LCD_PAL177_G04_0_Msk (0x1fUL << LCD_PAL177_G04_0_Pos) /*!< LCD PAL177: G04_0 Mask */
+#define LCD_PAL177_B04_0_Pos 10 /*!< LCD PAL177: B04_0 Position */
+#define LCD_PAL177_B04_0_Msk (0x1fUL << LCD_PAL177_B04_0_Pos) /*!< LCD PAL177: B04_0 Mask */
+#define LCD_PAL177_I0_Pos 15 /*!< LCD PAL177: I0 Position */
+#define LCD_PAL177_I0_Msk (0x01UL << LCD_PAL177_I0_Pos) /*!< LCD PAL177: I0 Mask */
+#define LCD_PAL177_R14_0_Pos 16 /*!< LCD PAL177: R14_0 Position */
+#define LCD_PAL177_R14_0_Msk (0x1fUL << LCD_PAL177_R14_0_Pos) /*!< LCD PAL177: R14_0 Mask */
+#define LCD_PAL177_G14_0_Pos 21 /*!< LCD PAL177: G14_0 Position */
+#define LCD_PAL177_G14_0_Msk (0x1fUL << LCD_PAL177_G14_0_Pos) /*!< LCD PAL177: G14_0 Mask */
+#define LCD_PAL177_B14_0_Pos 26 /*!< LCD PAL177: B14_0 Position */
+#define LCD_PAL177_B14_0_Msk (0x1fUL << LCD_PAL177_B14_0_Pos) /*!< LCD PAL177: B14_0 Mask */
+#define LCD_PAL177_I1_Pos 31 /*!< LCD PAL177: I1 Position */
+#define LCD_PAL177_I1_Msk (0x01UL << LCD_PAL177_I1_Pos) /*!< LCD PAL177: I1 Mask */
+
+// --------------------------------------- LCD_PAL178 -------------------------------------------
+#define LCD_PAL178_R04_0_Pos 0 /*!< LCD PAL178: R04_0 Position */
+#define LCD_PAL178_R04_0_Msk (0x1fUL << LCD_PAL178_R04_0_Pos) /*!< LCD PAL178: R04_0 Mask */
+#define LCD_PAL178_G04_0_Pos 5 /*!< LCD PAL178: G04_0 Position */
+#define LCD_PAL178_G04_0_Msk (0x1fUL << LCD_PAL178_G04_0_Pos) /*!< LCD PAL178: G04_0 Mask */
+#define LCD_PAL178_B04_0_Pos 10 /*!< LCD PAL178: B04_0 Position */
+#define LCD_PAL178_B04_0_Msk (0x1fUL << LCD_PAL178_B04_0_Pos) /*!< LCD PAL178: B04_0 Mask */
+#define LCD_PAL178_I0_Pos 15 /*!< LCD PAL178: I0 Position */
+#define LCD_PAL178_I0_Msk (0x01UL << LCD_PAL178_I0_Pos) /*!< LCD PAL178: I0 Mask */
+#define LCD_PAL178_R14_0_Pos 16 /*!< LCD PAL178: R14_0 Position */
+#define LCD_PAL178_R14_0_Msk (0x1fUL << LCD_PAL178_R14_0_Pos) /*!< LCD PAL178: R14_0 Mask */
+#define LCD_PAL178_G14_0_Pos 21 /*!< LCD PAL178: G14_0 Position */
+#define LCD_PAL178_G14_0_Msk (0x1fUL << LCD_PAL178_G14_0_Pos) /*!< LCD PAL178: G14_0 Mask */
+#define LCD_PAL178_B14_0_Pos 26 /*!< LCD PAL178: B14_0 Position */
+#define LCD_PAL178_B14_0_Msk (0x1fUL << LCD_PAL178_B14_0_Pos) /*!< LCD PAL178: B14_0 Mask */
+#define LCD_PAL178_I1_Pos 31 /*!< LCD PAL178: I1 Position */
+#define LCD_PAL178_I1_Msk (0x01UL << LCD_PAL178_I1_Pos) /*!< LCD PAL178: I1 Mask */
+
+// --------------------------------------- LCD_PAL179 -------------------------------------------
+#define LCD_PAL179_R04_0_Pos 0 /*!< LCD PAL179: R04_0 Position */
+#define LCD_PAL179_R04_0_Msk (0x1fUL << LCD_PAL179_R04_0_Pos) /*!< LCD PAL179: R04_0 Mask */
+#define LCD_PAL179_G04_0_Pos 5 /*!< LCD PAL179: G04_0 Position */
+#define LCD_PAL179_G04_0_Msk (0x1fUL << LCD_PAL179_G04_0_Pos) /*!< LCD PAL179: G04_0 Mask */
+#define LCD_PAL179_B04_0_Pos 10 /*!< LCD PAL179: B04_0 Position */
+#define LCD_PAL179_B04_0_Msk (0x1fUL << LCD_PAL179_B04_0_Pos) /*!< LCD PAL179: B04_0 Mask */
+#define LCD_PAL179_I0_Pos 15 /*!< LCD PAL179: I0 Position */
+#define LCD_PAL179_I0_Msk (0x01UL << LCD_PAL179_I0_Pos) /*!< LCD PAL179: I0 Mask */
+#define LCD_PAL179_R14_0_Pos 16 /*!< LCD PAL179: R14_0 Position */
+#define LCD_PAL179_R14_0_Msk (0x1fUL << LCD_PAL179_R14_0_Pos) /*!< LCD PAL179: R14_0 Mask */
+#define LCD_PAL179_G14_0_Pos 21 /*!< LCD PAL179: G14_0 Position */
+#define LCD_PAL179_G14_0_Msk (0x1fUL << LCD_PAL179_G14_0_Pos) /*!< LCD PAL179: G14_0 Mask */
+#define LCD_PAL179_B14_0_Pos 26 /*!< LCD PAL179: B14_0 Position */
+#define LCD_PAL179_B14_0_Msk (0x1fUL << LCD_PAL179_B14_0_Pos) /*!< LCD PAL179: B14_0 Mask */
+#define LCD_PAL179_I1_Pos 31 /*!< LCD PAL179: I1 Position */
+#define LCD_PAL179_I1_Msk (0x01UL << LCD_PAL179_I1_Pos) /*!< LCD PAL179: I1 Mask */
+
+// --------------------------------------- LCD_PAL180 -------------------------------------------
+#define LCD_PAL180_R04_0_Pos 0 /*!< LCD PAL180: R04_0 Position */
+#define LCD_PAL180_R04_0_Msk (0x1fUL << LCD_PAL180_R04_0_Pos) /*!< LCD PAL180: R04_0 Mask */
+#define LCD_PAL180_G04_0_Pos 5 /*!< LCD PAL180: G04_0 Position */
+#define LCD_PAL180_G04_0_Msk (0x1fUL << LCD_PAL180_G04_0_Pos) /*!< LCD PAL180: G04_0 Mask */
+#define LCD_PAL180_B04_0_Pos 10 /*!< LCD PAL180: B04_0 Position */
+#define LCD_PAL180_B04_0_Msk (0x1fUL << LCD_PAL180_B04_0_Pos) /*!< LCD PAL180: B04_0 Mask */
+#define LCD_PAL180_I0_Pos 15 /*!< LCD PAL180: I0 Position */
+#define LCD_PAL180_I0_Msk (0x01UL << LCD_PAL180_I0_Pos) /*!< LCD PAL180: I0 Mask */
+#define LCD_PAL180_R14_0_Pos 16 /*!< LCD PAL180: R14_0 Position */
+#define LCD_PAL180_R14_0_Msk (0x1fUL << LCD_PAL180_R14_0_Pos) /*!< LCD PAL180: R14_0 Mask */
+#define LCD_PAL180_G14_0_Pos 21 /*!< LCD PAL180: G14_0 Position */
+#define LCD_PAL180_G14_0_Msk (0x1fUL << LCD_PAL180_G14_0_Pos) /*!< LCD PAL180: G14_0 Mask */
+#define LCD_PAL180_B14_0_Pos 26 /*!< LCD PAL180: B14_0 Position */
+#define LCD_PAL180_B14_0_Msk (0x1fUL << LCD_PAL180_B14_0_Pos) /*!< LCD PAL180: B14_0 Mask */
+#define LCD_PAL180_I1_Pos 31 /*!< LCD PAL180: I1 Position */
+#define LCD_PAL180_I1_Msk (0x01UL << LCD_PAL180_I1_Pos) /*!< LCD PAL180: I1 Mask */
+
+// --------------------------------------- LCD_PAL181 -------------------------------------------
+#define LCD_PAL181_R04_0_Pos 0 /*!< LCD PAL181: R04_0 Position */
+#define LCD_PAL181_R04_0_Msk (0x1fUL << LCD_PAL181_R04_0_Pos) /*!< LCD PAL181: R04_0 Mask */
+#define LCD_PAL181_G04_0_Pos 5 /*!< LCD PAL181: G04_0 Position */
+#define LCD_PAL181_G04_0_Msk (0x1fUL << LCD_PAL181_G04_0_Pos) /*!< LCD PAL181: G04_0 Mask */
+#define LCD_PAL181_B04_0_Pos 10 /*!< LCD PAL181: B04_0 Position */
+#define LCD_PAL181_B04_0_Msk (0x1fUL << LCD_PAL181_B04_0_Pos) /*!< LCD PAL181: B04_0 Mask */
+#define LCD_PAL181_I0_Pos 15 /*!< LCD PAL181: I0 Position */
+#define LCD_PAL181_I0_Msk (0x01UL << LCD_PAL181_I0_Pos) /*!< LCD PAL181: I0 Mask */
+#define LCD_PAL181_R14_0_Pos 16 /*!< LCD PAL181: R14_0 Position */
+#define LCD_PAL181_R14_0_Msk (0x1fUL << LCD_PAL181_R14_0_Pos) /*!< LCD PAL181: R14_0 Mask */
+#define LCD_PAL181_G14_0_Pos 21 /*!< LCD PAL181: G14_0 Position */
+#define LCD_PAL181_G14_0_Msk (0x1fUL << LCD_PAL181_G14_0_Pos) /*!< LCD PAL181: G14_0 Mask */
+#define LCD_PAL181_B14_0_Pos 26 /*!< LCD PAL181: B14_0 Position */
+#define LCD_PAL181_B14_0_Msk (0x1fUL << LCD_PAL181_B14_0_Pos) /*!< LCD PAL181: B14_0 Mask */
+#define LCD_PAL181_I1_Pos 31 /*!< LCD PAL181: I1 Position */
+#define LCD_PAL181_I1_Msk (0x01UL << LCD_PAL181_I1_Pos) /*!< LCD PAL181: I1 Mask */
+
+// --------------------------------------- LCD_PAL182 -------------------------------------------
+#define LCD_PAL182_R04_0_Pos 0 /*!< LCD PAL182: R04_0 Position */
+#define LCD_PAL182_R04_0_Msk (0x1fUL << LCD_PAL182_R04_0_Pos) /*!< LCD PAL182: R04_0 Mask */
+#define LCD_PAL182_G04_0_Pos 5 /*!< LCD PAL182: G04_0 Position */
+#define LCD_PAL182_G04_0_Msk (0x1fUL << LCD_PAL182_G04_0_Pos) /*!< LCD PAL182: G04_0 Mask */
+#define LCD_PAL182_B04_0_Pos 10 /*!< LCD PAL182: B04_0 Position */
+#define LCD_PAL182_B04_0_Msk (0x1fUL << LCD_PAL182_B04_0_Pos) /*!< LCD PAL182: B04_0 Mask */
+#define LCD_PAL182_I0_Pos 15 /*!< LCD PAL182: I0 Position */
+#define LCD_PAL182_I0_Msk (0x01UL << LCD_PAL182_I0_Pos) /*!< LCD PAL182: I0 Mask */
+#define LCD_PAL182_R14_0_Pos 16 /*!< LCD PAL182: R14_0 Position */
+#define LCD_PAL182_R14_0_Msk (0x1fUL << LCD_PAL182_R14_0_Pos) /*!< LCD PAL182: R14_0 Mask */
+#define LCD_PAL182_G14_0_Pos 21 /*!< LCD PAL182: G14_0 Position */
+#define LCD_PAL182_G14_0_Msk (0x1fUL << LCD_PAL182_G14_0_Pos) /*!< LCD PAL182: G14_0 Mask */
+#define LCD_PAL182_B14_0_Pos 26 /*!< LCD PAL182: B14_0 Position */
+#define LCD_PAL182_B14_0_Msk (0x1fUL << LCD_PAL182_B14_0_Pos) /*!< LCD PAL182: B14_0 Mask */
+#define LCD_PAL182_I1_Pos 31 /*!< LCD PAL182: I1 Position */
+#define LCD_PAL182_I1_Msk (0x01UL << LCD_PAL182_I1_Pos) /*!< LCD PAL182: I1 Mask */
+
+// --------------------------------------- LCD_PAL183 -------------------------------------------
+#define LCD_PAL183_R04_0_Pos 0 /*!< LCD PAL183: R04_0 Position */
+#define LCD_PAL183_R04_0_Msk (0x1fUL << LCD_PAL183_R04_0_Pos) /*!< LCD PAL183: R04_0 Mask */
+#define LCD_PAL183_G04_0_Pos 5 /*!< LCD PAL183: G04_0 Position */
+#define LCD_PAL183_G04_0_Msk (0x1fUL << LCD_PAL183_G04_0_Pos) /*!< LCD PAL183: G04_0 Mask */
+#define LCD_PAL183_B04_0_Pos 10 /*!< LCD PAL183: B04_0 Position */
+#define LCD_PAL183_B04_0_Msk (0x1fUL << LCD_PAL183_B04_0_Pos) /*!< LCD PAL183: B04_0 Mask */
+#define LCD_PAL183_I0_Pos 15 /*!< LCD PAL183: I0 Position */
+#define LCD_PAL183_I0_Msk (0x01UL << LCD_PAL183_I0_Pos) /*!< LCD PAL183: I0 Mask */
+#define LCD_PAL183_R14_0_Pos 16 /*!< LCD PAL183: R14_0 Position */
+#define LCD_PAL183_R14_0_Msk (0x1fUL << LCD_PAL183_R14_0_Pos) /*!< LCD PAL183: R14_0 Mask */
+#define LCD_PAL183_G14_0_Pos 21 /*!< LCD PAL183: G14_0 Position */
+#define LCD_PAL183_G14_0_Msk (0x1fUL << LCD_PAL183_G14_0_Pos) /*!< LCD PAL183: G14_0 Mask */
+#define LCD_PAL183_B14_0_Pos 26 /*!< LCD PAL183: B14_0 Position */
+#define LCD_PAL183_B14_0_Msk (0x1fUL << LCD_PAL183_B14_0_Pos) /*!< LCD PAL183: B14_0 Mask */
+#define LCD_PAL183_I1_Pos 31 /*!< LCD PAL183: I1 Position */
+#define LCD_PAL183_I1_Msk (0x01UL << LCD_PAL183_I1_Pos) /*!< LCD PAL183: I1 Mask */
+
+// --------------------------------------- LCD_PAL184 -------------------------------------------
+#define LCD_PAL184_R04_0_Pos 0 /*!< LCD PAL184: R04_0 Position */
+#define LCD_PAL184_R04_0_Msk (0x1fUL << LCD_PAL184_R04_0_Pos) /*!< LCD PAL184: R04_0 Mask */
+#define LCD_PAL184_G04_0_Pos 5 /*!< LCD PAL184: G04_0 Position */
+#define LCD_PAL184_G04_0_Msk (0x1fUL << LCD_PAL184_G04_0_Pos) /*!< LCD PAL184: G04_0 Mask */
+#define LCD_PAL184_B04_0_Pos 10 /*!< LCD PAL184: B04_0 Position */
+#define LCD_PAL184_B04_0_Msk (0x1fUL << LCD_PAL184_B04_0_Pos) /*!< LCD PAL184: B04_0 Mask */
+#define LCD_PAL184_I0_Pos 15 /*!< LCD PAL184: I0 Position */
+#define LCD_PAL184_I0_Msk (0x01UL << LCD_PAL184_I0_Pos) /*!< LCD PAL184: I0 Mask */
+#define LCD_PAL184_R14_0_Pos 16 /*!< LCD PAL184: R14_0 Position */
+#define LCD_PAL184_R14_0_Msk (0x1fUL << LCD_PAL184_R14_0_Pos) /*!< LCD PAL184: R14_0 Mask */
+#define LCD_PAL184_G14_0_Pos 21 /*!< LCD PAL184: G14_0 Position */
+#define LCD_PAL184_G14_0_Msk (0x1fUL << LCD_PAL184_G14_0_Pos) /*!< LCD PAL184: G14_0 Mask */
+#define LCD_PAL184_B14_0_Pos 26 /*!< LCD PAL184: B14_0 Position */
+#define LCD_PAL184_B14_0_Msk (0x1fUL << LCD_PAL184_B14_0_Pos) /*!< LCD PAL184: B14_0 Mask */
+#define LCD_PAL184_I1_Pos 31 /*!< LCD PAL184: I1 Position */
+#define LCD_PAL184_I1_Msk (0x01UL << LCD_PAL184_I1_Pos) /*!< LCD PAL184: I1 Mask */
+
+// --------------------------------------- LCD_PAL185 -------------------------------------------
+#define LCD_PAL185_R04_0_Pos 0 /*!< LCD PAL185: R04_0 Position */
+#define LCD_PAL185_R04_0_Msk (0x1fUL << LCD_PAL185_R04_0_Pos) /*!< LCD PAL185: R04_0 Mask */
+#define LCD_PAL185_G04_0_Pos 5 /*!< LCD PAL185: G04_0 Position */
+#define LCD_PAL185_G04_0_Msk (0x1fUL << LCD_PAL185_G04_0_Pos) /*!< LCD PAL185: G04_0 Mask */
+#define LCD_PAL185_B04_0_Pos 10 /*!< LCD PAL185: B04_0 Position */
+#define LCD_PAL185_B04_0_Msk (0x1fUL << LCD_PAL185_B04_0_Pos) /*!< LCD PAL185: B04_0 Mask */
+#define LCD_PAL185_I0_Pos 15 /*!< LCD PAL185: I0 Position */
+#define LCD_PAL185_I0_Msk (0x01UL << LCD_PAL185_I0_Pos) /*!< LCD PAL185: I0 Mask */
+#define LCD_PAL185_R14_0_Pos 16 /*!< LCD PAL185: R14_0 Position */
+#define LCD_PAL185_R14_0_Msk (0x1fUL << LCD_PAL185_R14_0_Pos) /*!< LCD PAL185: R14_0 Mask */
+#define LCD_PAL185_G14_0_Pos 21 /*!< LCD PAL185: G14_0 Position */
+#define LCD_PAL185_G14_0_Msk (0x1fUL << LCD_PAL185_G14_0_Pos) /*!< LCD PAL185: G14_0 Mask */
+#define LCD_PAL185_B14_0_Pos 26 /*!< LCD PAL185: B14_0 Position */
+#define LCD_PAL185_B14_0_Msk (0x1fUL << LCD_PAL185_B14_0_Pos) /*!< LCD PAL185: B14_0 Mask */
+#define LCD_PAL185_I1_Pos 31 /*!< LCD PAL185: I1 Position */
+#define LCD_PAL185_I1_Msk (0x01UL << LCD_PAL185_I1_Pos) /*!< LCD PAL185: I1 Mask */
+
+// --------------------------------------- LCD_PAL186 -------------------------------------------
+#define LCD_PAL186_R04_0_Pos 0 /*!< LCD PAL186: R04_0 Position */
+#define LCD_PAL186_R04_0_Msk (0x1fUL << LCD_PAL186_R04_0_Pos) /*!< LCD PAL186: R04_0 Mask */
+#define LCD_PAL186_G04_0_Pos 5 /*!< LCD PAL186: G04_0 Position */
+#define LCD_PAL186_G04_0_Msk (0x1fUL << LCD_PAL186_G04_0_Pos) /*!< LCD PAL186: G04_0 Mask */
+#define LCD_PAL186_B04_0_Pos 10 /*!< LCD PAL186: B04_0 Position */
+#define LCD_PAL186_B04_0_Msk (0x1fUL << LCD_PAL186_B04_0_Pos) /*!< LCD PAL186: B04_0 Mask */
+#define LCD_PAL186_I0_Pos 15 /*!< LCD PAL186: I0 Position */
+#define LCD_PAL186_I0_Msk (0x01UL << LCD_PAL186_I0_Pos) /*!< LCD PAL186: I0 Mask */
+#define LCD_PAL186_R14_0_Pos 16 /*!< LCD PAL186: R14_0 Position */
+#define LCD_PAL186_R14_0_Msk (0x1fUL << LCD_PAL186_R14_0_Pos) /*!< LCD PAL186: R14_0 Mask */
+#define LCD_PAL186_G14_0_Pos 21 /*!< LCD PAL186: G14_0 Position */
+#define LCD_PAL186_G14_0_Msk (0x1fUL << LCD_PAL186_G14_0_Pos) /*!< LCD PAL186: G14_0 Mask */
+#define LCD_PAL186_B14_0_Pos 26 /*!< LCD PAL186: B14_0 Position */
+#define LCD_PAL186_B14_0_Msk (0x1fUL << LCD_PAL186_B14_0_Pos) /*!< LCD PAL186: B14_0 Mask */
+#define LCD_PAL186_I1_Pos 31 /*!< LCD PAL186: I1 Position */
+#define LCD_PAL186_I1_Msk (0x01UL << LCD_PAL186_I1_Pos) /*!< LCD PAL186: I1 Mask */
+
+// --------------------------------------- LCD_PAL187 -------------------------------------------
+#define LCD_PAL187_R04_0_Pos 0 /*!< LCD PAL187: R04_0 Position */
+#define LCD_PAL187_R04_0_Msk (0x1fUL << LCD_PAL187_R04_0_Pos) /*!< LCD PAL187: R04_0 Mask */
+#define LCD_PAL187_G04_0_Pos 5 /*!< LCD PAL187: G04_0 Position */
+#define LCD_PAL187_G04_0_Msk (0x1fUL << LCD_PAL187_G04_0_Pos) /*!< LCD PAL187: G04_0 Mask */
+#define LCD_PAL187_B04_0_Pos 10 /*!< LCD PAL187: B04_0 Position */
+#define LCD_PAL187_B04_0_Msk (0x1fUL << LCD_PAL187_B04_0_Pos) /*!< LCD PAL187: B04_0 Mask */
+#define LCD_PAL187_I0_Pos 15 /*!< LCD PAL187: I0 Position */
+#define LCD_PAL187_I0_Msk (0x01UL << LCD_PAL187_I0_Pos) /*!< LCD PAL187: I0 Mask */
+#define LCD_PAL187_R14_0_Pos 16 /*!< LCD PAL187: R14_0 Position */
+#define LCD_PAL187_R14_0_Msk (0x1fUL << LCD_PAL187_R14_0_Pos) /*!< LCD PAL187: R14_0 Mask */
+#define LCD_PAL187_G14_0_Pos 21 /*!< LCD PAL187: G14_0 Position */
+#define LCD_PAL187_G14_0_Msk (0x1fUL << LCD_PAL187_G14_0_Pos) /*!< LCD PAL187: G14_0 Mask */
+#define LCD_PAL187_B14_0_Pos 26 /*!< LCD PAL187: B14_0 Position */
+#define LCD_PAL187_B14_0_Msk (0x1fUL << LCD_PAL187_B14_0_Pos) /*!< LCD PAL187: B14_0 Mask */
+#define LCD_PAL187_I1_Pos 31 /*!< LCD PAL187: I1 Position */
+#define LCD_PAL187_I1_Msk (0x01UL << LCD_PAL187_I1_Pos) /*!< LCD PAL187: I1 Mask */
+
+// --------------------------------------- LCD_PAL188 -------------------------------------------
+#define LCD_PAL188_R04_0_Pos 0 /*!< LCD PAL188: R04_0 Position */
+#define LCD_PAL188_R04_0_Msk (0x1fUL << LCD_PAL188_R04_0_Pos) /*!< LCD PAL188: R04_0 Mask */
+#define LCD_PAL188_G04_0_Pos 5 /*!< LCD PAL188: G04_0 Position */
+#define LCD_PAL188_G04_0_Msk (0x1fUL << LCD_PAL188_G04_0_Pos) /*!< LCD PAL188: G04_0 Mask */
+#define LCD_PAL188_B04_0_Pos 10 /*!< LCD PAL188: B04_0 Position */
+#define LCD_PAL188_B04_0_Msk (0x1fUL << LCD_PAL188_B04_0_Pos) /*!< LCD PAL188: B04_0 Mask */
+#define LCD_PAL188_I0_Pos 15 /*!< LCD PAL188: I0 Position */
+#define LCD_PAL188_I0_Msk (0x01UL << LCD_PAL188_I0_Pos) /*!< LCD PAL188: I0 Mask */
+#define LCD_PAL188_R14_0_Pos 16 /*!< LCD PAL188: R14_0 Position */
+#define LCD_PAL188_R14_0_Msk (0x1fUL << LCD_PAL188_R14_0_Pos) /*!< LCD PAL188: R14_0 Mask */
+#define LCD_PAL188_G14_0_Pos 21 /*!< LCD PAL188: G14_0 Position */
+#define LCD_PAL188_G14_0_Msk (0x1fUL << LCD_PAL188_G14_0_Pos) /*!< LCD PAL188: G14_0 Mask */
+#define LCD_PAL188_B14_0_Pos 26 /*!< LCD PAL188: B14_0 Position */
+#define LCD_PAL188_B14_0_Msk (0x1fUL << LCD_PAL188_B14_0_Pos) /*!< LCD PAL188: B14_0 Mask */
+#define LCD_PAL188_I1_Pos 31 /*!< LCD PAL188: I1 Position */
+#define LCD_PAL188_I1_Msk (0x01UL << LCD_PAL188_I1_Pos) /*!< LCD PAL188: I1 Mask */
+
+// --------------------------------------- LCD_PAL189 -------------------------------------------
+#define LCD_PAL189_R04_0_Pos 0 /*!< LCD PAL189: R04_0 Position */
+#define LCD_PAL189_R04_0_Msk (0x1fUL << LCD_PAL189_R04_0_Pos) /*!< LCD PAL189: R04_0 Mask */
+#define LCD_PAL189_G04_0_Pos 5 /*!< LCD PAL189: G04_0 Position */
+#define LCD_PAL189_G04_0_Msk (0x1fUL << LCD_PAL189_G04_0_Pos) /*!< LCD PAL189: G04_0 Mask */
+#define LCD_PAL189_B04_0_Pos 10 /*!< LCD PAL189: B04_0 Position */
+#define LCD_PAL189_B04_0_Msk (0x1fUL << LCD_PAL189_B04_0_Pos) /*!< LCD PAL189: B04_0 Mask */
+#define LCD_PAL189_I0_Pos 15 /*!< LCD PAL189: I0 Position */
+#define LCD_PAL189_I0_Msk (0x01UL << LCD_PAL189_I0_Pos) /*!< LCD PAL189: I0 Mask */
+#define LCD_PAL189_R14_0_Pos 16 /*!< LCD PAL189: R14_0 Position */
+#define LCD_PAL189_R14_0_Msk (0x1fUL << LCD_PAL189_R14_0_Pos) /*!< LCD PAL189: R14_0 Mask */
+#define LCD_PAL189_G14_0_Pos 21 /*!< LCD PAL189: G14_0 Position */
+#define LCD_PAL189_G14_0_Msk (0x1fUL << LCD_PAL189_G14_0_Pos) /*!< LCD PAL189: G14_0 Mask */
+#define LCD_PAL189_B14_0_Pos 26 /*!< LCD PAL189: B14_0 Position */
+#define LCD_PAL189_B14_0_Msk (0x1fUL << LCD_PAL189_B14_0_Pos) /*!< LCD PAL189: B14_0 Mask */
+#define LCD_PAL189_I1_Pos 31 /*!< LCD PAL189: I1 Position */
+#define LCD_PAL189_I1_Msk (0x01UL << LCD_PAL189_I1_Pos) /*!< LCD PAL189: I1 Mask */
+
+// --------------------------------------- LCD_PAL190 -------------------------------------------
+#define LCD_PAL190_R04_0_Pos 0 /*!< LCD PAL190: R04_0 Position */
+#define LCD_PAL190_R04_0_Msk (0x1fUL << LCD_PAL190_R04_0_Pos) /*!< LCD PAL190: R04_0 Mask */
+#define LCD_PAL190_G04_0_Pos 5 /*!< LCD PAL190: G04_0 Position */
+#define LCD_PAL190_G04_0_Msk (0x1fUL << LCD_PAL190_G04_0_Pos) /*!< LCD PAL190: G04_0 Mask */
+#define LCD_PAL190_B04_0_Pos 10 /*!< LCD PAL190: B04_0 Position */
+#define LCD_PAL190_B04_0_Msk (0x1fUL << LCD_PAL190_B04_0_Pos) /*!< LCD PAL190: B04_0 Mask */
+#define LCD_PAL190_I0_Pos 15 /*!< LCD PAL190: I0 Position */
+#define LCD_PAL190_I0_Msk (0x01UL << LCD_PAL190_I0_Pos) /*!< LCD PAL190: I0 Mask */
+#define LCD_PAL190_R14_0_Pos 16 /*!< LCD PAL190: R14_0 Position */
+#define LCD_PAL190_R14_0_Msk (0x1fUL << LCD_PAL190_R14_0_Pos) /*!< LCD PAL190: R14_0 Mask */
+#define LCD_PAL190_G14_0_Pos 21 /*!< LCD PAL190: G14_0 Position */
+#define LCD_PAL190_G14_0_Msk (0x1fUL << LCD_PAL190_G14_0_Pos) /*!< LCD PAL190: G14_0 Mask */
+#define LCD_PAL190_B14_0_Pos 26 /*!< LCD PAL190: B14_0 Position */
+#define LCD_PAL190_B14_0_Msk (0x1fUL << LCD_PAL190_B14_0_Pos) /*!< LCD PAL190: B14_0 Mask */
+#define LCD_PAL190_I1_Pos 31 /*!< LCD PAL190: I1 Position */
+#define LCD_PAL190_I1_Msk (0x01UL << LCD_PAL190_I1_Pos) /*!< LCD PAL190: I1 Mask */
+
+// --------------------------------------- LCD_PAL191 -------------------------------------------
+#define LCD_PAL191_R04_0_Pos 0 /*!< LCD PAL191: R04_0 Position */
+#define LCD_PAL191_R04_0_Msk (0x1fUL << LCD_PAL191_R04_0_Pos) /*!< LCD PAL191: R04_0 Mask */
+#define LCD_PAL191_G04_0_Pos 5 /*!< LCD PAL191: G04_0 Position */
+#define LCD_PAL191_G04_0_Msk (0x1fUL << LCD_PAL191_G04_0_Pos) /*!< LCD PAL191: G04_0 Mask */
+#define LCD_PAL191_B04_0_Pos 10 /*!< LCD PAL191: B04_0 Position */
+#define LCD_PAL191_B04_0_Msk (0x1fUL << LCD_PAL191_B04_0_Pos) /*!< LCD PAL191: B04_0 Mask */
+#define LCD_PAL191_I0_Pos 15 /*!< LCD PAL191: I0 Position */
+#define LCD_PAL191_I0_Msk (0x01UL << LCD_PAL191_I0_Pos) /*!< LCD PAL191: I0 Mask */
+#define LCD_PAL191_R14_0_Pos 16 /*!< LCD PAL191: R14_0 Position */
+#define LCD_PAL191_R14_0_Msk (0x1fUL << LCD_PAL191_R14_0_Pos) /*!< LCD PAL191: R14_0 Mask */
+#define LCD_PAL191_G14_0_Pos 21 /*!< LCD PAL191: G14_0 Position */
+#define LCD_PAL191_G14_0_Msk (0x1fUL << LCD_PAL191_G14_0_Pos) /*!< LCD PAL191: G14_0 Mask */
+#define LCD_PAL191_B14_0_Pos 26 /*!< LCD PAL191: B14_0 Position */
+#define LCD_PAL191_B14_0_Msk (0x1fUL << LCD_PAL191_B14_0_Pos) /*!< LCD PAL191: B14_0 Mask */
+#define LCD_PAL191_I1_Pos 31 /*!< LCD PAL191: I1 Position */
+#define LCD_PAL191_I1_Msk (0x01UL << LCD_PAL191_I1_Pos) /*!< LCD PAL191: I1 Mask */
+
+// --------------------------------------- LCD_PAL192 -------------------------------------------
+#define LCD_PAL192_R04_0_Pos 0 /*!< LCD PAL192: R04_0 Position */
+#define LCD_PAL192_R04_0_Msk (0x1fUL << LCD_PAL192_R04_0_Pos) /*!< LCD PAL192: R04_0 Mask */
+#define LCD_PAL192_G04_0_Pos 5 /*!< LCD PAL192: G04_0 Position */
+#define LCD_PAL192_G04_0_Msk (0x1fUL << LCD_PAL192_G04_0_Pos) /*!< LCD PAL192: G04_0 Mask */
+#define LCD_PAL192_B04_0_Pos 10 /*!< LCD PAL192: B04_0 Position */
+#define LCD_PAL192_B04_0_Msk (0x1fUL << LCD_PAL192_B04_0_Pos) /*!< LCD PAL192: B04_0 Mask */
+#define LCD_PAL192_I0_Pos 15 /*!< LCD PAL192: I0 Position */
+#define LCD_PAL192_I0_Msk (0x01UL << LCD_PAL192_I0_Pos) /*!< LCD PAL192: I0 Mask */
+#define LCD_PAL192_R14_0_Pos 16 /*!< LCD PAL192: R14_0 Position */
+#define LCD_PAL192_R14_0_Msk (0x1fUL << LCD_PAL192_R14_0_Pos) /*!< LCD PAL192: R14_0 Mask */
+#define LCD_PAL192_G14_0_Pos 21 /*!< LCD PAL192: G14_0 Position */
+#define LCD_PAL192_G14_0_Msk (0x1fUL << LCD_PAL192_G14_0_Pos) /*!< LCD PAL192: G14_0 Mask */
+#define LCD_PAL192_B14_0_Pos 26 /*!< LCD PAL192: B14_0 Position */
+#define LCD_PAL192_B14_0_Msk (0x1fUL << LCD_PAL192_B14_0_Pos) /*!< LCD PAL192: B14_0 Mask */
+#define LCD_PAL192_I1_Pos 31 /*!< LCD PAL192: I1 Position */
+#define LCD_PAL192_I1_Msk (0x01UL << LCD_PAL192_I1_Pos) /*!< LCD PAL192: I1 Mask */
+
+// --------------------------------------- LCD_PAL193 -------------------------------------------
+#define LCD_PAL193_R04_0_Pos 0 /*!< LCD PAL193: R04_0 Position */
+#define LCD_PAL193_R04_0_Msk (0x1fUL << LCD_PAL193_R04_0_Pos) /*!< LCD PAL193: R04_0 Mask */
+#define LCD_PAL193_G04_0_Pos 5 /*!< LCD PAL193: G04_0 Position */
+#define LCD_PAL193_G04_0_Msk (0x1fUL << LCD_PAL193_G04_0_Pos) /*!< LCD PAL193: G04_0 Mask */
+#define LCD_PAL193_B04_0_Pos 10 /*!< LCD PAL193: B04_0 Position */
+#define LCD_PAL193_B04_0_Msk (0x1fUL << LCD_PAL193_B04_0_Pos) /*!< LCD PAL193: B04_0 Mask */
+#define LCD_PAL193_I0_Pos 15 /*!< LCD PAL193: I0 Position */
+#define LCD_PAL193_I0_Msk (0x01UL << LCD_PAL193_I0_Pos) /*!< LCD PAL193: I0 Mask */
+#define LCD_PAL193_R14_0_Pos 16 /*!< LCD PAL193: R14_0 Position */
+#define LCD_PAL193_R14_0_Msk (0x1fUL << LCD_PAL193_R14_0_Pos) /*!< LCD PAL193: R14_0 Mask */
+#define LCD_PAL193_G14_0_Pos 21 /*!< LCD PAL193: G14_0 Position */
+#define LCD_PAL193_G14_0_Msk (0x1fUL << LCD_PAL193_G14_0_Pos) /*!< LCD PAL193: G14_0 Mask */
+#define LCD_PAL193_B14_0_Pos 26 /*!< LCD PAL193: B14_0 Position */
+#define LCD_PAL193_B14_0_Msk (0x1fUL << LCD_PAL193_B14_0_Pos) /*!< LCD PAL193: B14_0 Mask */
+#define LCD_PAL193_I1_Pos 31 /*!< LCD PAL193: I1 Position */
+#define LCD_PAL193_I1_Msk (0x01UL << LCD_PAL193_I1_Pos) /*!< LCD PAL193: I1 Mask */
+
+// --------------------------------------- LCD_PAL194 -------------------------------------------
+#define LCD_PAL194_R04_0_Pos 0 /*!< LCD PAL194: R04_0 Position */
+#define LCD_PAL194_R04_0_Msk (0x1fUL << LCD_PAL194_R04_0_Pos) /*!< LCD PAL194: R04_0 Mask */
+#define LCD_PAL194_G04_0_Pos 5 /*!< LCD PAL194: G04_0 Position */
+#define LCD_PAL194_G04_0_Msk (0x1fUL << LCD_PAL194_G04_0_Pos) /*!< LCD PAL194: G04_0 Mask */
+#define LCD_PAL194_B04_0_Pos 10 /*!< LCD PAL194: B04_0 Position */
+#define LCD_PAL194_B04_0_Msk (0x1fUL << LCD_PAL194_B04_0_Pos) /*!< LCD PAL194: B04_0 Mask */
+#define LCD_PAL194_I0_Pos 15 /*!< LCD PAL194: I0 Position */
+#define LCD_PAL194_I0_Msk (0x01UL << LCD_PAL194_I0_Pos) /*!< LCD PAL194: I0 Mask */
+#define LCD_PAL194_R14_0_Pos 16 /*!< LCD PAL194: R14_0 Position */
+#define LCD_PAL194_R14_0_Msk (0x1fUL << LCD_PAL194_R14_0_Pos) /*!< LCD PAL194: R14_0 Mask */
+#define LCD_PAL194_G14_0_Pos 21 /*!< LCD PAL194: G14_0 Position */
+#define LCD_PAL194_G14_0_Msk (0x1fUL << LCD_PAL194_G14_0_Pos) /*!< LCD PAL194: G14_0 Mask */
+#define LCD_PAL194_B14_0_Pos 26 /*!< LCD PAL194: B14_0 Position */
+#define LCD_PAL194_B14_0_Msk (0x1fUL << LCD_PAL194_B14_0_Pos) /*!< LCD PAL194: B14_0 Mask */
+#define LCD_PAL194_I1_Pos 31 /*!< LCD PAL194: I1 Position */
+#define LCD_PAL194_I1_Msk (0x01UL << LCD_PAL194_I1_Pos) /*!< LCD PAL194: I1 Mask */
+
+// --------------------------------------- LCD_PAL195 -------------------------------------------
+#define LCD_PAL195_R04_0_Pos 0 /*!< LCD PAL195: R04_0 Position */
+#define LCD_PAL195_R04_0_Msk (0x1fUL << LCD_PAL195_R04_0_Pos) /*!< LCD PAL195: R04_0 Mask */
+#define LCD_PAL195_G04_0_Pos 5 /*!< LCD PAL195: G04_0 Position */
+#define LCD_PAL195_G04_0_Msk (0x1fUL << LCD_PAL195_G04_0_Pos) /*!< LCD PAL195: G04_0 Mask */
+#define LCD_PAL195_B04_0_Pos 10 /*!< LCD PAL195: B04_0 Position */
+#define LCD_PAL195_B04_0_Msk (0x1fUL << LCD_PAL195_B04_0_Pos) /*!< LCD PAL195: B04_0 Mask */
+#define LCD_PAL195_I0_Pos 15 /*!< LCD PAL195: I0 Position */
+#define LCD_PAL195_I0_Msk (0x01UL << LCD_PAL195_I0_Pos) /*!< LCD PAL195: I0 Mask */
+#define LCD_PAL195_R14_0_Pos 16 /*!< LCD PAL195: R14_0 Position */
+#define LCD_PAL195_R14_0_Msk (0x1fUL << LCD_PAL195_R14_0_Pos) /*!< LCD PAL195: R14_0 Mask */
+#define LCD_PAL195_G14_0_Pos 21 /*!< LCD PAL195: G14_0 Position */
+#define LCD_PAL195_G14_0_Msk (0x1fUL << LCD_PAL195_G14_0_Pos) /*!< LCD PAL195: G14_0 Mask */
+#define LCD_PAL195_B14_0_Pos 26 /*!< LCD PAL195: B14_0 Position */
+#define LCD_PAL195_B14_0_Msk (0x1fUL << LCD_PAL195_B14_0_Pos) /*!< LCD PAL195: B14_0 Mask */
+#define LCD_PAL195_I1_Pos 31 /*!< LCD PAL195: I1 Position */
+#define LCD_PAL195_I1_Msk (0x01UL << LCD_PAL195_I1_Pos) /*!< LCD PAL195: I1 Mask */
+
+// --------------------------------------- LCD_PAL196 -------------------------------------------
+#define LCD_PAL196_R04_0_Pos 0 /*!< LCD PAL196: R04_0 Position */
+#define LCD_PAL196_R04_0_Msk (0x1fUL << LCD_PAL196_R04_0_Pos) /*!< LCD PAL196: R04_0 Mask */
+#define LCD_PAL196_G04_0_Pos 5 /*!< LCD PAL196: G04_0 Position */
+#define LCD_PAL196_G04_0_Msk (0x1fUL << LCD_PAL196_G04_0_Pos) /*!< LCD PAL196: G04_0 Mask */
+#define LCD_PAL196_B04_0_Pos 10 /*!< LCD PAL196: B04_0 Position */
+#define LCD_PAL196_B04_0_Msk (0x1fUL << LCD_PAL196_B04_0_Pos) /*!< LCD PAL196: B04_0 Mask */
+#define LCD_PAL196_I0_Pos 15 /*!< LCD PAL196: I0 Position */
+#define LCD_PAL196_I0_Msk (0x01UL << LCD_PAL196_I0_Pos) /*!< LCD PAL196: I0 Mask */
+#define LCD_PAL196_R14_0_Pos 16 /*!< LCD PAL196: R14_0 Position */
+#define LCD_PAL196_R14_0_Msk (0x1fUL << LCD_PAL196_R14_0_Pos) /*!< LCD PAL196: R14_0 Mask */
+#define LCD_PAL196_G14_0_Pos 21 /*!< LCD PAL196: G14_0 Position */
+#define LCD_PAL196_G14_0_Msk (0x1fUL << LCD_PAL196_G14_0_Pos) /*!< LCD PAL196: G14_0 Mask */
+#define LCD_PAL196_B14_0_Pos 26 /*!< LCD PAL196: B14_0 Position */
+#define LCD_PAL196_B14_0_Msk (0x1fUL << LCD_PAL196_B14_0_Pos) /*!< LCD PAL196: B14_0 Mask */
+#define LCD_PAL196_I1_Pos 31 /*!< LCD PAL196: I1 Position */
+#define LCD_PAL196_I1_Msk (0x01UL << LCD_PAL196_I1_Pos) /*!< LCD PAL196: I1 Mask */
+
+// --------------------------------------- LCD_PAL197 -------------------------------------------
+#define LCD_PAL197_R04_0_Pos 0 /*!< LCD PAL197: R04_0 Position */
+#define LCD_PAL197_R04_0_Msk (0x1fUL << LCD_PAL197_R04_0_Pos) /*!< LCD PAL197: R04_0 Mask */
+#define LCD_PAL197_G04_0_Pos 5 /*!< LCD PAL197: G04_0 Position */
+#define LCD_PAL197_G04_0_Msk (0x1fUL << LCD_PAL197_G04_0_Pos) /*!< LCD PAL197: G04_0 Mask */
+#define LCD_PAL197_B04_0_Pos 10 /*!< LCD PAL197: B04_0 Position */
+#define LCD_PAL197_B04_0_Msk (0x1fUL << LCD_PAL197_B04_0_Pos) /*!< LCD PAL197: B04_0 Mask */
+#define LCD_PAL197_I0_Pos 15 /*!< LCD PAL197: I0 Position */
+#define LCD_PAL197_I0_Msk (0x01UL << LCD_PAL197_I0_Pos) /*!< LCD PAL197: I0 Mask */
+#define LCD_PAL197_R14_0_Pos 16 /*!< LCD PAL197: R14_0 Position */
+#define LCD_PAL197_R14_0_Msk (0x1fUL << LCD_PAL197_R14_0_Pos) /*!< LCD PAL197: R14_0 Mask */
+#define LCD_PAL197_G14_0_Pos 21 /*!< LCD PAL197: G14_0 Position */
+#define LCD_PAL197_G14_0_Msk (0x1fUL << LCD_PAL197_G14_0_Pos) /*!< LCD PAL197: G14_0 Mask */
+#define LCD_PAL197_B14_0_Pos 26 /*!< LCD PAL197: B14_0 Position */
+#define LCD_PAL197_B14_0_Msk (0x1fUL << LCD_PAL197_B14_0_Pos) /*!< LCD PAL197: B14_0 Mask */
+#define LCD_PAL197_I1_Pos 31 /*!< LCD PAL197: I1 Position */
+#define LCD_PAL197_I1_Msk (0x01UL << LCD_PAL197_I1_Pos) /*!< LCD PAL197: I1 Mask */
+
+// --------------------------------------- LCD_PAL198 -------------------------------------------
+#define LCD_PAL198_R04_0_Pos 0 /*!< LCD PAL198: R04_0 Position */
+#define LCD_PAL198_R04_0_Msk (0x1fUL << LCD_PAL198_R04_0_Pos) /*!< LCD PAL198: R04_0 Mask */
+#define LCD_PAL198_G04_0_Pos 5 /*!< LCD PAL198: G04_0 Position */
+#define LCD_PAL198_G04_0_Msk (0x1fUL << LCD_PAL198_G04_0_Pos) /*!< LCD PAL198: G04_0 Mask */
+#define LCD_PAL198_B04_0_Pos 10 /*!< LCD PAL198: B04_0 Position */
+#define LCD_PAL198_B04_0_Msk (0x1fUL << LCD_PAL198_B04_0_Pos) /*!< LCD PAL198: B04_0 Mask */
+#define LCD_PAL198_I0_Pos 15 /*!< LCD PAL198: I0 Position */
+#define LCD_PAL198_I0_Msk (0x01UL << LCD_PAL198_I0_Pos) /*!< LCD PAL198: I0 Mask */
+#define LCD_PAL198_R14_0_Pos 16 /*!< LCD PAL198: R14_0 Position */
+#define LCD_PAL198_R14_0_Msk (0x1fUL << LCD_PAL198_R14_0_Pos) /*!< LCD PAL198: R14_0 Mask */
+#define LCD_PAL198_G14_0_Pos 21 /*!< LCD PAL198: G14_0 Position */
+#define LCD_PAL198_G14_0_Msk (0x1fUL << LCD_PAL198_G14_0_Pos) /*!< LCD PAL198: G14_0 Mask */
+#define LCD_PAL198_B14_0_Pos 26 /*!< LCD PAL198: B14_0 Position */
+#define LCD_PAL198_B14_0_Msk (0x1fUL << LCD_PAL198_B14_0_Pos) /*!< LCD PAL198: B14_0 Mask */
+#define LCD_PAL198_I1_Pos 31 /*!< LCD PAL198: I1 Position */
+#define LCD_PAL198_I1_Msk (0x01UL << LCD_PAL198_I1_Pos) /*!< LCD PAL198: I1 Mask */
+
+// --------------------------------------- LCD_PAL199 -------------------------------------------
+#define LCD_PAL199_R04_0_Pos 0 /*!< LCD PAL199: R04_0 Position */
+#define LCD_PAL199_R04_0_Msk (0x1fUL << LCD_PAL199_R04_0_Pos) /*!< LCD PAL199: R04_0 Mask */
+#define LCD_PAL199_G04_0_Pos 5 /*!< LCD PAL199: G04_0 Position */
+#define LCD_PAL199_G04_0_Msk (0x1fUL << LCD_PAL199_G04_0_Pos) /*!< LCD PAL199: G04_0 Mask */
+#define LCD_PAL199_B04_0_Pos 10 /*!< LCD PAL199: B04_0 Position */
+#define LCD_PAL199_B04_0_Msk (0x1fUL << LCD_PAL199_B04_0_Pos) /*!< LCD PAL199: B04_0 Mask */
+#define LCD_PAL199_I0_Pos 15 /*!< LCD PAL199: I0 Position */
+#define LCD_PAL199_I0_Msk (0x01UL << LCD_PAL199_I0_Pos) /*!< LCD PAL199: I0 Mask */
+#define LCD_PAL199_R14_0_Pos 16 /*!< LCD PAL199: R14_0 Position */
+#define LCD_PAL199_R14_0_Msk (0x1fUL << LCD_PAL199_R14_0_Pos) /*!< LCD PAL199: R14_0 Mask */
+#define LCD_PAL199_G14_0_Pos 21 /*!< LCD PAL199: G14_0 Position */
+#define LCD_PAL199_G14_0_Msk (0x1fUL << LCD_PAL199_G14_0_Pos) /*!< LCD PAL199: G14_0 Mask */
+#define LCD_PAL199_B14_0_Pos 26 /*!< LCD PAL199: B14_0 Position */
+#define LCD_PAL199_B14_0_Msk (0x1fUL << LCD_PAL199_B14_0_Pos) /*!< LCD PAL199: B14_0 Mask */
+#define LCD_PAL199_I1_Pos 31 /*!< LCD PAL199: I1 Position */
+#define LCD_PAL199_I1_Msk (0x01UL << LCD_PAL199_I1_Pos) /*!< LCD PAL199: I1 Mask */
+
+// --------------------------------------- LCD_PAL200 -------------------------------------------
+#define LCD_PAL200_R04_0_Pos 0 /*!< LCD PAL200: R04_0 Position */
+#define LCD_PAL200_R04_0_Msk (0x1fUL << LCD_PAL200_R04_0_Pos) /*!< LCD PAL200: R04_0 Mask */
+#define LCD_PAL200_G04_0_Pos 5 /*!< LCD PAL200: G04_0 Position */
+#define LCD_PAL200_G04_0_Msk (0x1fUL << LCD_PAL200_G04_0_Pos) /*!< LCD PAL200: G04_0 Mask */
+#define LCD_PAL200_B04_0_Pos 10 /*!< LCD PAL200: B04_0 Position */
+#define LCD_PAL200_B04_0_Msk (0x1fUL << LCD_PAL200_B04_0_Pos) /*!< LCD PAL200: B04_0 Mask */
+#define LCD_PAL200_I0_Pos 15 /*!< LCD PAL200: I0 Position */
+#define LCD_PAL200_I0_Msk (0x01UL << LCD_PAL200_I0_Pos) /*!< LCD PAL200: I0 Mask */
+#define LCD_PAL200_R14_0_Pos 16 /*!< LCD PAL200: R14_0 Position */
+#define LCD_PAL200_R14_0_Msk (0x1fUL << LCD_PAL200_R14_0_Pos) /*!< LCD PAL200: R14_0 Mask */
+#define LCD_PAL200_G14_0_Pos 21 /*!< LCD PAL200: G14_0 Position */
+#define LCD_PAL200_G14_0_Msk (0x1fUL << LCD_PAL200_G14_0_Pos) /*!< LCD PAL200: G14_0 Mask */
+#define LCD_PAL200_B14_0_Pos 26 /*!< LCD PAL200: B14_0 Position */
+#define LCD_PAL200_B14_0_Msk (0x1fUL << LCD_PAL200_B14_0_Pos) /*!< LCD PAL200: B14_0 Mask */
+#define LCD_PAL200_I1_Pos 31 /*!< LCD PAL200: I1 Position */
+#define LCD_PAL200_I1_Msk (0x01UL << LCD_PAL200_I1_Pos) /*!< LCD PAL200: I1 Mask */
+
+// --------------------------------------- LCD_PAL201 -------------------------------------------
+#define LCD_PAL201_R04_0_Pos 0 /*!< LCD PAL201: R04_0 Position */
+#define LCD_PAL201_R04_0_Msk (0x1fUL << LCD_PAL201_R04_0_Pos) /*!< LCD PAL201: R04_0 Mask */
+#define LCD_PAL201_G04_0_Pos 5 /*!< LCD PAL201: G04_0 Position */
+#define LCD_PAL201_G04_0_Msk (0x1fUL << LCD_PAL201_G04_0_Pos) /*!< LCD PAL201: G04_0 Mask */
+#define LCD_PAL201_B04_0_Pos 10 /*!< LCD PAL201: B04_0 Position */
+#define LCD_PAL201_B04_0_Msk (0x1fUL << LCD_PAL201_B04_0_Pos) /*!< LCD PAL201: B04_0 Mask */
+#define LCD_PAL201_I0_Pos 15 /*!< LCD PAL201: I0 Position */
+#define LCD_PAL201_I0_Msk (0x01UL << LCD_PAL201_I0_Pos) /*!< LCD PAL201: I0 Mask */
+#define LCD_PAL201_R14_0_Pos 16 /*!< LCD PAL201: R14_0 Position */
+#define LCD_PAL201_R14_0_Msk (0x1fUL << LCD_PAL201_R14_0_Pos) /*!< LCD PAL201: R14_0 Mask */
+#define LCD_PAL201_G14_0_Pos 21 /*!< LCD PAL201: G14_0 Position */
+#define LCD_PAL201_G14_0_Msk (0x1fUL << LCD_PAL201_G14_0_Pos) /*!< LCD PAL201: G14_0 Mask */
+#define LCD_PAL201_B14_0_Pos 26 /*!< LCD PAL201: B14_0 Position */
+#define LCD_PAL201_B14_0_Msk (0x1fUL << LCD_PAL201_B14_0_Pos) /*!< LCD PAL201: B14_0 Mask */
+#define LCD_PAL201_I1_Pos 31 /*!< LCD PAL201: I1 Position */
+#define LCD_PAL201_I1_Msk (0x01UL << LCD_PAL201_I1_Pos) /*!< LCD PAL201: I1 Mask */
+
+// --------------------------------------- LCD_PAL202 -------------------------------------------
+#define LCD_PAL202_R04_0_Pos 0 /*!< LCD PAL202: R04_0 Position */
+#define LCD_PAL202_R04_0_Msk (0x1fUL << LCD_PAL202_R04_0_Pos) /*!< LCD PAL202: R04_0 Mask */
+#define LCD_PAL202_G04_0_Pos 5 /*!< LCD PAL202: G04_0 Position */
+#define LCD_PAL202_G04_0_Msk (0x1fUL << LCD_PAL202_G04_0_Pos) /*!< LCD PAL202: G04_0 Mask */
+#define LCD_PAL202_B04_0_Pos 10 /*!< LCD PAL202: B04_0 Position */
+#define LCD_PAL202_B04_0_Msk (0x1fUL << LCD_PAL202_B04_0_Pos) /*!< LCD PAL202: B04_0 Mask */
+#define LCD_PAL202_I0_Pos 15 /*!< LCD PAL202: I0 Position */
+#define LCD_PAL202_I0_Msk (0x01UL << LCD_PAL202_I0_Pos) /*!< LCD PAL202: I0 Mask */
+#define LCD_PAL202_R14_0_Pos 16 /*!< LCD PAL202: R14_0 Position */
+#define LCD_PAL202_R14_0_Msk (0x1fUL << LCD_PAL202_R14_0_Pos) /*!< LCD PAL202: R14_0 Mask */
+#define LCD_PAL202_G14_0_Pos 21 /*!< LCD PAL202: G14_0 Position */
+#define LCD_PAL202_G14_0_Msk (0x1fUL << LCD_PAL202_G14_0_Pos) /*!< LCD PAL202: G14_0 Mask */
+#define LCD_PAL202_B14_0_Pos 26 /*!< LCD PAL202: B14_0 Position */
+#define LCD_PAL202_B14_0_Msk (0x1fUL << LCD_PAL202_B14_0_Pos) /*!< LCD PAL202: B14_0 Mask */
+#define LCD_PAL202_I1_Pos 31 /*!< LCD PAL202: I1 Position */
+#define LCD_PAL202_I1_Msk (0x01UL << LCD_PAL202_I1_Pos) /*!< LCD PAL202: I1 Mask */
+
+// --------------------------------------- LCD_PAL203 -------------------------------------------
+#define LCD_PAL203_R04_0_Pos 0 /*!< LCD PAL203: R04_0 Position */
+#define LCD_PAL203_R04_0_Msk (0x1fUL << LCD_PAL203_R04_0_Pos) /*!< LCD PAL203: R04_0 Mask */
+#define LCD_PAL203_G04_0_Pos 5 /*!< LCD PAL203: G04_0 Position */
+#define LCD_PAL203_G04_0_Msk (0x1fUL << LCD_PAL203_G04_0_Pos) /*!< LCD PAL203: G04_0 Mask */
+#define LCD_PAL203_B04_0_Pos 10 /*!< LCD PAL203: B04_0 Position */
+#define LCD_PAL203_B04_0_Msk (0x1fUL << LCD_PAL203_B04_0_Pos) /*!< LCD PAL203: B04_0 Mask */
+#define LCD_PAL203_I0_Pos 15 /*!< LCD PAL203: I0 Position */
+#define LCD_PAL203_I0_Msk (0x01UL << LCD_PAL203_I0_Pos) /*!< LCD PAL203: I0 Mask */
+#define LCD_PAL203_R14_0_Pos 16 /*!< LCD PAL203: R14_0 Position */
+#define LCD_PAL203_R14_0_Msk (0x1fUL << LCD_PAL203_R14_0_Pos) /*!< LCD PAL203: R14_0 Mask */
+#define LCD_PAL203_G14_0_Pos 21 /*!< LCD PAL203: G14_0 Position */
+#define LCD_PAL203_G14_0_Msk (0x1fUL << LCD_PAL203_G14_0_Pos) /*!< LCD PAL203: G14_0 Mask */
+#define LCD_PAL203_B14_0_Pos 26 /*!< LCD PAL203: B14_0 Position */
+#define LCD_PAL203_B14_0_Msk (0x1fUL << LCD_PAL203_B14_0_Pos) /*!< LCD PAL203: B14_0 Mask */
+#define LCD_PAL203_I1_Pos 31 /*!< LCD PAL203: I1 Position */
+#define LCD_PAL203_I1_Msk (0x01UL << LCD_PAL203_I1_Pos) /*!< LCD PAL203: I1 Mask */
+
+// --------------------------------------- LCD_PAL204 -------------------------------------------
+#define LCD_PAL204_R04_0_Pos 0 /*!< LCD PAL204: R04_0 Position */
+#define LCD_PAL204_R04_0_Msk (0x1fUL << LCD_PAL204_R04_0_Pos) /*!< LCD PAL204: R04_0 Mask */
+#define LCD_PAL204_G04_0_Pos 5 /*!< LCD PAL204: G04_0 Position */
+#define LCD_PAL204_G04_0_Msk (0x1fUL << LCD_PAL204_G04_0_Pos) /*!< LCD PAL204: G04_0 Mask */
+#define LCD_PAL204_B04_0_Pos 10 /*!< LCD PAL204: B04_0 Position */
+#define LCD_PAL204_B04_0_Msk (0x1fUL << LCD_PAL204_B04_0_Pos) /*!< LCD PAL204: B04_0 Mask */
+#define LCD_PAL204_I0_Pos 15 /*!< LCD PAL204: I0 Position */
+#define LCD_PAL204_I0_Msk (0x01UL << LCD_PAL204_I0_Pos) /*!< LCD PAL204: I0 Mask */
+#define LCD_PAL204_R14_0_Pos 16 /*!< LCD PAL204: R14_0 Position */
+#define LCD_PAL204_R14_0_Msk (0x1fUL << LCD_PAL204_R14_0_Pos) /*!< LCD PAL204: R14_0 Mask */
+#define LCD_PAL204_G14_0_Pos 21 /*!< LCD PAL204: G14_0 Position */
+#define LCD_PAL204_G14_0_Msk (0x1fUL << LCD_PAL204_G14_0_Pos) /*!< LCD PAL204: G14_0 Mask */
+#define LCD_PAL204_B14_0_Pos 26 /*!< LCD PAL204: B14_0 Position */
+#define LCD_PAL204_B14_0_Msk (0x1fUL << LCD_PAL204_B14_0_Pos) /*!< LCD PAL204: B14_0 Mask */
+#define LCD_PAL204_I1_Pos 31 /*!< LCD PAL204: I1 Position */
+#define LCD_PAL204_I1_Msk (0x01UL << LCD_PAL204_I1_Pos) /*!< LCD PAL204: I1 Mask */
+
+// --------------------------------------- LCD_PAL205 -------------------------------------------
+#define LCD_PAL205_R04_0_Pos 0 /*!< LCD PAL205: R04_0 Position */
+#define LCD_PAL205_R04_0_Msk (0x1fUL << LCD_PAL205_R04_0_Pos) /*!< LCD PAL205: R04_0 Mask */
+#define LCD_PAL205_G04_0_Pos 5 /*!< LCD PAL205: G04_0 Position */
+#define LCD_PAL205_G04_0_Msk (0x1fUL << LCD_PAL205_G04_0_Pos) /*!< LCD PAL205: G04_0 Mask */
+#define LCD_PAL205_B04_0_Pos 10 /*!< LCD PAL205: B04_0 Position */
+#define LCD_PAL205_B04_0_Msk (0x1fUL << LCD_PAL205_B04_0_Pos) /*!< LCD PAL205: B04_0 Mask */
+#define LCD_PAL205_I0_Pos 15 /*!< LCD PAL205: I0 Position */
+#define LCD_PAL205_I0_Msk (0x01UL << LCD_PAL205_I0_Pos) /*!< LCD PAL205: I0 Mask */
+#define LCD_PAL205_R14_0_Pos 16 /*!< LCD PAL205: R14_0 Position */
+#define LCD_PAL205_R14_0_Msk (0x1fUL << LCD_PAL205_R14_0_Pos) /*!< LCD PAL205: R14_0 Mask */
+#define LCD_PAL205_G14_0_Pos 21 /*!< LCD PAL205: G14_0 Position */
+#define LCD_PAL205_G14_0_Msk (0x1fUL << LCD_PAL205_G14_0_Pos) /*!< LCD PAL205: G14_0 Mask */
+#define LCD_PAL205_B14_0_Pos 26 /*!< LCD PAL205: B14_0 Position */
+#define LCD_PAL205_B14_0_Msk (0x1fUL << LCD_PAL205_B14_0_Pos) /*!< LCD PAL205: B14_0 Mask */
+#define LCD_PAL205_I1_Pos 31 /*!< LCD PAL205: I1 Position */
+#define LCD_PAL205_I1_Msk (0x01UL << LCD_PAL205_I1_Pos) /*!< LCD PAL205: I1 Mask */
+
+// --------------------------------------- LCD_PAL206 -------------------------------------------
+#define LCD_PAL206_R04_0_Pos 0 /*!< LCD PAL206: R04_0 Position */
+#define LCD_PAL206_R04_0_Msk (0x1fUL << LCD_PAL206_R04_0_Pos) /*!< LCD PAL206: R04_0 Mask */
+#define LCD_PAL206_G04_0_Pos 5 /*!< LCD PAL206: G04_0 Position */
+#define LCD_PAL206_G04_0_Msk (0x1fUL << LCD_PAL206_G04_0_Pos) /*!< LCD PAL206: G04_0 Mask */
+#define LCD_PAL206_B04_0_Pos 10 /*!< LCD PAL206: B04_0 Position */
+#define LCD_PAL206_B04_0_Msk (0x1fUL << LCD_PAL206_B04_0_Pos) /*!< LCD PAL206: B04_0 Mask */
+#define LCD_PAL206_I0_Pos 15 /*!< LCD PAL206: I0 Position */
+#define LCD_PAL206_I0_Msk (0x01UL << LCD_PAL206_I0_Pos) /*!< LCD PAL206: I0 Mask */
+#define LCD_PAL206_R14_0_Pos 16 /*!< LCD PAL206: R14_0 Position */
+#define LCD_PAL206_R14_0_Msk (0x1fUL << LCD_PAL206_R14_0_Pos) /*!< LCD PAL206: R14_0 Mask */
+#define LCD_PAL206_G14_0_Pos 21 /*!< LCD PAL206: G14_0 Position */
+#define LCD_PAL206_G14_0_Msk (0x1fUL << LCD_PAL206_G14_0_Pos) /*!< LCD PAL206: G14_0 Mask */
+#define LCD_PAL206_B14_0_Pos 26 /*!< LCD PAL206: B14_0 Position */
+#define LCD_PAL206_B14_0_Msk (0x1fUL << LCD_PAL206_B14_0_Pos) /*!< LCD PAL206: B14_0 Mask */
+#define LCD_PAL206_I1_Pos 31 /*!< LCD PAL206: I1 Position */
+#define LCD_PAL206_I1_Msk (0x01UL << LCD_PAL206_I1_Pos) /*!< LCD PAL206: I1 Mask */
+
+// --------------------------------------- LCD_PAL207 -------------------------------------------
+#define LCD_PAL207_R04_0_Pos 0 /*!< LCD PAL207: R04_0 Position */
+#define LCD_PAL207_R04_0_Msk (0x1fUL << LCD_PAL207_R04_0_Pos) /*!< LCD PAL207: R04_0 Mask */
+#define LCD_PAL207_G04_0_Pos 5 /*!< LCD PAL207: G04_0 Position */
+#define LCD_PAL207_G04_0_Msk (0x1fUL << LCD_PAL207_G04_0_Pos) /*!< LCD PAL207: G04_0 Mask */
+#define LCD_PAL207_B04_0_Pos 10 /*!< LCD PAL207: B04_0 Position */
+#define LCD_PAL207_B04_0_Msk (0x1fUL << LCD_PAL207_B04_0_Pos) /*!< LCD PAL207: B04_0 Mask */
+#define LCD_PAL207_I0_Pos 15 /*!< LCD PAL207: I0 Position */
+#define LCD_PAL207_I0_Msk (0x01UL << LCD_PAL207_I0_Pos) /*!< LCD PAL207: I0 Mask */
+#define LCD_PAL207_R14_0_Pos 16 /*!< LCD PAL207: R14_0 Position */
+#define LCD_PAL207_R14_0_Msk (0x1fUL << LCD_PAL207_R14_0_Pos) /*!< LCD PAL207: R14_0 Mask */
+#define LCD_PAL207_G14_0_Pos 21 /*!< LCD PAL207: G14_0 Position */
+#define LCD_PAL207_G14_0_Msk (0x1fUL << LCD_PAL207_G14_0_Pos) /*!< LCD PAL207: G14_0 Mask */
+#define LCD_PAL207_B14_0_Pos 26 /*!< LCD PAL207: B14_0 Position */
+#define LCD_PAL207_B14_0_Msk (0x1fUL << LCD_PAL207_B14_0_Pos) /*!< LCD PAL207: B14_0 Mask */
+#define LCD_PAL207_I1_Pos 31 /*!< LCD PAL207: I1 Position */
+#define LCD_PAL207_I1_Msk (0x01UL << LCD_PAL207_I1_Pos) /*!< LCD PAL207: I1 Mask */
+
+// --------------------------------------- LCD_PAL208 -------------------------------------------
+#define LCD_PAL208_R04_0_Pos 0 /*!< LCD PAL208: R04_0 Position */
+#define LCD_PAL208_R04_0_Msk (0x1fUL << LCD_PAL208_R04_0_Pos) /*!< LCD PAL208: R04_0 Mask */
+#define LCD_PAL208_G04_0_Pos 5 /*!< LCD PAL208: G04_0 Position */
+#define LCD_PAL208_G04_0_Msk (0x1fUL << LCD_PAL208_G04_0_Pos) /*!< LCD PAL208: G04_0 Mask */
+#define LCD_PAL208_B04_0_Pos 10 /*!< LCD PAL208: B04_0 Position */
+#define LCD_PAL208_B04_0_Msk (0x1fUL << LCD_PAL208_B04_0_Pos) /*!< LCD PAL208: B04_0 Mask */
+#define LCD_PAL208_I0_Pos 15 /*!< LCD PAL208: I0 Position */
+#define LCD_PAL208_I0_Msk (0x01UL << LCD_PAL208_I0_Pos) /*!< LCD PAL208: I0 Mask */
+#define LCD_PAL208_R14_0_Pos 16 /*!< LCD PAL208: R14_0 Position */
+#define LCD_PAL208_R14_0_Msk (0x1fUL << LCD_PAL208_R14_0_Pos) /*!< LCD PAL208: R14_0 Mask */
+#define LCD_PAL208_G14_0_Pos 21 /*!< LCD PAL208: G14_0 Position */
+#define LCD_PAL208_G14_0_Msk (0x1fUL << LCD_PAL208_G14_0_Pos) /*!< LCD PAL208: G14_0 Mask */
+#define LCD_PAL208_B14_0_Pos 26 /*!< LCD PAL208: B14_0 Position */
+#define LCD_PAL208_B14_0_Msk (0x1fUL << LCD_PAL208_B14_0_Pos) /*!< LCD PAL208: B14_0 Mask */
+#define LCD_PAL208_I1_Pos 31 /*!< LCD PAL208: I1 Position */
+#define LCD_PAL208_I1_Msk (0x01UL << LCD_PAL208_I1_Pos) /*!< LCD PAL208: I1 Mask */
+
+// --------------------------------------- LCD_PAL209 -------------------------------------------
+#define LCD_PAL209_R04_0_Pos 0 /*!< LCD PAL209: R04_0 Position */
+#define LCD_PAL209_R04_0_Msk (0x1fUL << LCD_PAL209_R04_0_Pos) /*!< LCD PAL209: R04_0 Mask */
+#define LCD_PAL209_G04_0_Pos 5 /*!< LCD PAL209: G04_0 Position */
+#define LCD_PAL209_G04_0_Msk (0x1fUL << LCD_PAL209_G04_0_Pos) /*!< LCD PAL209: G04_0 Mask */
+#define LCD_PAL209_B04_0_Pos 10 /*!< LCD PAL209: B04_0 Position */
+#define LCD_PAL209_B04_0_Msk (0x1fUL << LCD_PAL209_B04_0_Pos) /*!< LCD PAL209: B04_0 Mask */
+#define LCD_PAL209_I0_Pos 15 /*!< LCD PAL209: I0 Position */
+#define LCD_PAL209_I0_Msk (0x01UL << LCD_PAL209_I0_Pos) /*!< LCD PAL209: I0 Mask */
+#define LCD_PAL209_R14_0_Pos 16 /*!< LCD PAL209: R14_0 Position */
+#define LCD_PAL209_R14_0_Msk (0x1fUL << LCD_PAL209_R14_0_Pos) /*!< LCD PAL209: R14_0 Mask */
+#define LCD_PAL209_G14_0_Pos 21 /*!< LCD PAL209: G14_0 Position */
+#define LCD_PAL209_G14_0_Msk (0x1fUL << LCD_PAL209_G14_0_Pos) /*!< LCD PAL209: G14_0 Mask */
+#define LCD_PAL209_B14_0_Pos 26 /*!< LCD PAL209: B14_0 Position */
+#define LCD_PAL209_B14_0_Msk (0x1fUL << LCD_PAL209_B14_0_Pos) /*!< LCD PAL209: B14_0 Mask */
+#define LCD_PAL209_I1_Pos 31 /*!< LCD PAL209: I1 Position */
+#define LCD_PAL209_I1_Msk (0x01UL << LCD_PAL209_I1_Pos) /*!< LCD PAL209: I1 Mask */
+
+// --------------------------------------- LCD_PAL210 -------------------------------------------
+#define LCD_PAL210_R04_0_Pos 0 /*!< LCD PAL210: R04_0 Position */
+#define LCD_PAL210_R04_0_Msk (0x1fUL << LCD_PAL210_R04_0_Pos) /*!< LCD PAL210: R04_0 Mask */
+#define LCD_PAL210_G04_0_Pos 5 /*!< LCD PAL210: G04_0 Position */
+#define LCD_PAL210_G04_0_Msk (0x1fUL << LCD_PAL210_G04_0_Pos) /*!< LCD PAL210: G04_0 Mask */
+#define LCD_PAL210_B04_0_Pos 10 /*!< LCD PAL210: B04_0 Position */
+#define LCD_PAL210_B04_0_Msk (0x1fUL << LCD_PAL210_B04_0_Pos) /*!< LCD PAL210: B04_0 Mask */
+#define LCD_PAL210_I0_Pos 15 /*!< LCD PAL210: I0 Position */
+#define LCD_PAL210_I0_Msk (0x01UL << LCD_PAL210_I0_Pos) /*!< LCD PAL210: I0 Mask */
+#define LCD_PAL210_R14_0_Pos 16 /*!< LCD PAL210: R14_0 Position */
+#define LCD_PAL210_R14_0_Msk (0x1fUL << LCD_PAL210_R14_0_Pos) /*!< LCD PAL210: R14_0 Mask */
+#define LCD_PAL210_G14_0_Pos 21 /*!< LCD PAL210: G14_0 Position */
+#define LCD_PAL210_G14_0_Msk (0x1fUL << LCD_PAL210_G14_0_Pos) /*!< LCD PAL210: G14_0 Mask */
+#define LCD_PAL210_B14_0_Pos 26 /*!< LCD PAL210: B14_0 Position */
+#define LCD_PAL210_B14_0_Msk (0x1fUL << LCD_PAL210_B14_0_Pos) /*!< LCD PAL210: B14_0 Mask */
+#define LCD_PAL210_I1_Pos 31 /*!< LCD PAL210: I1 Position */
+#define LCD_PAL210_I1_Msk (0x01UL << LCD_PAL210_I1_Pos) /*!< LCD PAL210: I1 Mask */
+
+// --------------------------------------- LCD_PAL211 -------------------------------------------
+#define LCD_PAL211_R04_0_Pos 0 /*!< LCD PAL211: R04_0 Position */
+#define LCD_PAL211_R04_0_Msk (0x1fUL << LCD_PAL211_R04_0_Pos) /*!< LCD PAL211: R04_0 Mask */
+#define LCD_PAL211_G04_0_Pos 5 /*!< LCD PAL211: G04_0 Position */
+#define LCD_PAL211_G04_0_Msk (0x1fUL << LCD_PAL211_G04_0_Pos) /*!< LCD PAL211: G04_0 Mask */
+#define LCD_PAL211_B04_0_Pos 10 /*!< LCD PAL211: B04_0 Position */
+#define LCD_PAL211_B04_0_Msk (0x1fUL << LCD_PAL211_B04_0_Pos) /*!< LCD PAL211: B04_0 Mask */
+#define LCD_PAL211_I0_Pos 15 /*!< LCD PAL211: I0 Position */
+#define LCD_PAL211_I0_Msk (0x01UL << LCD_PAL211_I0_Pos) /*!< LCD PAL211: I0 Mask */
+#define LCD_PAL211_R14_0_Pos 16 /*!< LCD PAL211: R14_0 Position */
+#define LCD_PAL211_R14_0_Msk (0x1fUL << LCD_PAL211_R14_0_Pos) /*!< LCD PAL211: R14_0 Mask */
+#define LCD_PAL211_G14_0_Pos 21 /*!< LCD PAL211: G14_0 Position */
+#define LCD_PAL211_G14_0_Msk (0x1fUL << LCD_PAL211_G14_0_Pos) /*!< LCD PAL211: G14_0 Mask */
+#define LCD_PAL211_B14_0_Pos 26 /*!< LCD PAL211: B14_0 Position */
+#define LCD_PAL211_B14_0_Msk (0x1fUL << LCD_PAL211_B14_0_Pos) /*!< LCD PAL211: B14_0 Mask */
+#define LCD_PAL211_I1_Pos 31 /*!< LCD PAL211: I1 Position */
+#define LCD_PAL211_I1_Msk (0x01UL << LCD_PAL211_I1_Pos) /*!< LCD PAL211: I1 Mask */
+
+// --------------------------------------- LCD_PAL212 -------------------------------------------
+#define LCD_PAL212_R04_0_Pos 0 /*!< LCD PAL212: R04_0 Position */
+#define LCD_PAL212_R04_0_Msk (0x1fUL << LCD_PAL212_R04_0_Pos) /*!< LCD PAL212: R04_0 Mask */
+#define LCD_PAL212_G04_0_Pos 5 /*!< LCD PAL212: G04_0 Position */
+#define LCD_PAL212_G04_0_Msk (0x1fUL << LCD_PAL212_G04_0_Pos) /*!< LCD PAL212: G04_0 Mask */
+#define LCD_PAL212_B04_0_Pos 10 /*!< LCD PAL212: B04_0 Position */
+#define LCD_PAL212_B04_0_Msk (0x1fUL << LCD_PAL212_B04_0_Pos) /*!< LCD PAL212: B04_0 Mask */
+#define LCD_PAL212_I0_Pos 15 /*!< LCD PAL212: I0 Position */
+#define LCD_PAL212_I0_Msk (0x01UL << LCD_PAL212_I0_Pos) /*!< LCD PAL212: I0 Mask */
+#define LCD_PAL212_R14_0_Pos 16 /*!< LCD PAL212: R14_0 Position */
+#define LCD_PAL212_R14_0_Msk (0x1fUL << LCD_PAL212_R14_0_Pos) /*!< LCD PAL212: R14_0 Mask */
+#define LCD_PAL212_G14_0_Pos 21 /*!< LCD PAL212: G14_0 Position */
+#define LCD_PAL212_G14_0_Msk (0x1fUL << LCD_PAL212_G14_0_Pos) /*!< LCD PAL212: G14_0 Mask */
+#define LCD_PAL212_B14_0_Pos 26 /*!< LCD PAL212: B14_0 Position */
+#define LCD_PAL212_B14_0_Msk (0x1fUL << LCD_PAL212_B14_0_Pos) /*!< LCD PAL212: B14_0 Mask */
+#define LCD_PAL212_I1_Pos 31 /*!< LCD PAL212: I1 Position */
+#define LCD_PAL212_I1_Msk (0x01UL << LCD_PAL212_I1_Pos) /*!< LCD PAL212: I1 Mask */
+
+// --------------------------------------- LCD_PAL213 -------------------------------------------
+#define LCD_PAL213_R04_0_Pos 0 /*!< LCD PAL213: R04_0 Position */
+#define LCD_PAL213_R04_0_Msk (0x1fUL << LCD_PAL213_R04_0_Pos) /*!< LCD PAL213: R04_0 Mask */
+#define LCD_PAL213_G04_0_Pos 5 /*!< LCD PAL213: G04_0 Position */
+#define LCD_PAL213_G04_0_Msk (0x1fUL << LCD_PAL213_G04_0_Pos) /*!< LCD PAL213: G04_0 Mask */
+#define LCD_PAL213_B04_0_Pos 10 /*!< LCD PAL213: B04_0 Position */
+#define LCD_PAL213_B04_0_Msk (0x1fUL << LCD_PAL213_B04_0_Pos) /*!< LCD PAL213: B04_0 Mask */
+#define LCD_PAL213_I0_Pos 15 /*!< LCD PAL213: I0 Position */
+#define LCD_PAL213_I0_Msk (0x01UL << LCD_PAL213_I0_Pos) /*!< LCD PAL213: I0 Mask */
+#define LCD_PAL213_R14_0_Pos 16 /*!< LCD PAL213: R14_0 Position */
+#define LCD_PAL213_R14_0_Msk (0x1fUL << LCD_PAL213_R14_0_Pos) /*!< LCD PAL213: R14_0 Mask */
+#define LCD_PAL213_G14_0_Pos 21 /*!< LCD PAL213: G14_0 Position */
+#define LCD_PAL213_G14_0_Msk (0x1fUL << LCD_PAL213_G14_0_Pos) /*!< LCD PAL213: G14_0 Mask */
+#define LCD_PAL213_B14_0_Pos 26 /*!< LCD PAL213: B14_0 Position */
+#define LCD_PAL213_B14_0_Msk (0x1fUL << LCD_PAL213_B14_0_Pos) /*!< LCD PAL213: B14_0 Mask */
+#define LCD_PAL213_I1_Pos 31 /*!< LCD PAL213: I1 Position */
+#define LCD_PAL213_I1_Msk (0x01UL << LCD_PAL213_I1_Pos) /*!< LCD PAL213: I1 Mask */
+
+// --------------------------------------- LCD_PAL214 -------------------------------------------
+#define LCD_PAL214_R04_0_Pos 0 /*!< LCD PAL214: R04_0 Position */
+#define LCD_PAL214_R04_0_Msk (0x1fUL << LCD_PAL214_R04_0_Pos) /*!< LCD PAL214: R04_0 Mask */
+#define LCD_PAL214_G04_0_Pos 5 /*!< LCD PAL214: G04_0 Position */
+#define LCD_PAL214_G04_0_Msk (0x1fUL << LCD_PAL214_G04_0_Pos) /*!< LCD PAL214: G04_0 Mask */
+#define LCD_PAL214_B04_0_Pos 10 /*!< LCD PAL214: B04_0 Position */
+#define LCD_PAL214_B04_0_Msk (0x1fUL << LCD_PAL214_B04_0_Pos) /*!< LCD PAL214: B04_0 Mask */
+#define LCD_PAL214_I0_Pos 15 /*!< LCD PAL214: I0 Position */
+#define LCD_PAL214_I0_Msk (0x01UL << LCD_PAL214_I0_Pos) /*!< LCD PAL214: I0 Mask */
+#define LCD_PAL214_R14_0_Pos 16 /*!< LCD PAL214: R14_0 Position */
+#define LCD_PAL214_R14_0_Msk (0x1fUL << LCD_PAL214_R14_0_Pos) /*!< LCD PAL214: R14_0 Mask */
+#define LCD_PAL214_G14_0_Pos 21 /*!< LCD PAL214: G14_0 Position */
+#define LCD_PAL214_G14_0_Msk (0x1fUL << LCD_PAL214_G14_0_Pos) /*!< LCD PAL214: G14_0 Mask */
+#define LCD_PAL214_B14_0_Pos 26 /*!< LCD PAL214: B14_0 Position */
+#define LCD_PAL214_B14_0_Msk (0x1fUL << LCD_PAL214_B14_0_Pos) /*!< LCD PAL214: B14_0 Mask */
+#define LCD_PAL214_I1_Pos 31 /*!< LCD PAL214: I1 Position */
+#define LCD_PAL214_I1_Msk (0x01UL << LCD_PAL214_I1_Pos) /*!< LCD PAL214: I1 Mask */
+
+// --------------------------------------- LCD_PAL215 -------------------------------------------
+#define LCD_PAL215_R04_0_Pos 0 /*!< LCD PAL215: R04_0 Position */
+#define LCD_PAL215_R04_0_Msk (0x1fUL << LCD_PAL215_R04_0_Pos) /*!< LCD PAL215: R04_0 Mask */
+#define LCD_PAL215_G04_0_Pos 5 /*!< LCD PAL215: G04_0 Position */
+#define LCD_PAL215_G04_0_Msk (0x1fUL << LCD_PAL215_G04_0_Pos) /*!< LCD PAL215: G04_0 Mask */
+#define LCD_PAL215_B04_0_Pos 10 /*!< LCD PAL215: B04_0 Position */
+#define LCD_PAL215_B04_0_Msk (0x1fUL << LCD_PAL215_B04_0_Pos) /*!< LCD PAL215: B04_0 Mask */
+#define LCD_PAL215_I0_Pos 15 /*!< LCD PAL215: I0 Position */
+#define LCD_PAL215_I0_Msk (0x01UL << LCD_PAL215_I0_Pos) /*!< LCD PAL215: I0 Mask */
+#define LCD_PAL215_R14_0_Pos 16 /*!< LCD PAL215: R14_0 Position */
+#define LCD_PAL215_R14_0_Msk (0x1fUL << LCD_PAL215_R14_0_Pos) /*!< LCD PAL215: R14_0 Mask */
+#define LCD_PAL215_G14_0_Pos 21 /*!< LCD PAL215: G14_0 Position */
+#define LCD_PAL215_G14_0_Msk (0x1fUL << LCD_PAL215_G14_0_Pos) /*!< LCD PAL215: G14_0 Mask */
+#define LCD_PAL215_B14_0_Pos 26 /*!< LCD PAL215: B14_0 Position */
+#define LCD_PAL215_B14_0_Msk (0x1fUL << LCD_PAL215_B14_0_Pos) /*!< LCD PAL215: B14_0 Mask */
+#define LCD_PAL215_I1_Pos 31 /*!< LCD PAL215: I1 Position */
+#define LCD_PAL215_I1_Msk (0x01UL << LCD_PAL215_I1_Pos) /*!< LCD PAL215: I1 Mask */
+
+// --------------------------------------- LCD_PAL216 -------------------------------------------
+#define LCD_PAL216_R04_0_Pos 0 /*!< LCD PAL216: R04_0 Position */
+#define LCD_PAL216_R04_0_Msk (0x1fUL << LCD_PAL216_R04_0_Pos) /*!< LCD PAL216: R04_0 Mask */
+#define LCD_PAL216_G04_0_Pos 5 /*!< LCD PAL216: G04_0 Position */
+#define LCD_PAL216_G04_0_Msk (0x1fUL << LCD_PAL216_G04_0_Pos) /*!< LCD PAL216: G04_0 Mask */
+#define LCD_PAL216_B04_0_Pos 10 /*!< LCD PAL216: B04_0 Position */
+#define LCD_PAL216_B04_0_Msk (0x1fUL << LCD_PAL216_B04_0_Pos) /*!< LCD PAL216: B04_0 Mask */
+#define LCD_PAL216_I0_Pos 15 /*!< LCD PAL216: I0 Position */
+#define LCD_PAL216_I0_Msk (0x01UL << LCD_PAL216_I0_Pos) /*!< LCD PAL216: I0 Mask */
+#define LCD_PAL216_R14_0_Pos 16 /*!< LCD PAL216: R14_0 Position */
+#define LCD_PAL216_R14_0_Msk (0x1fUL << LCD_PAL216_R14_0_Pos) /*!< LCD PAL216: R14_0 Mask */
+#define LCD_PAL216_G14_0_Pos 21 /*!< LCD PAL216: G14_0 Position */
+#define LCD_PAL216_G14_0_Msk (0x1fUL << LCD_PAL216_G14_0_Pos) /*!< LCD PAL216: G14_0 Mask */
+#define LCD_PAL216_B14_0_Pos 26 /*!< LCD PAL216: B14_0 Position */
+#define LCD_PAL216_B14_0_Msk (0x1fUL << LCD_PAL216_B14_0_Pos) /*!< LCD PAL216: B14_0 Mask */
+#define LCD_PAL216_I1_Pos 31 /*!< LCD PAL216: I1 Position */
+#define LCD_PAL216_I1_Msk (0x01UL << LCD_PAL216_I1_Pos) /*!< LCD PAL216: I1 Mask */
+
+// --------------------------------------- LCD_PAL217 -------------------------------------------
+#define LCD_PAL217_R04_0_Pos 0 /*!< LCD PAL217: R04_0 Position */
+#define LCD_PAL217_R04_0_Msk (0x1fUL << LCD_PAL217_R04_0_Pos) /*!< LCD PAL217: R04_0 Mask */
+#define LCD_PAL217_G04_0_Pos 5 /*!< LCD PAL217: G04_0 Position */
+#define LCD_PAL217_G04_0_Msk (0x1fUL << LCD_PAL217_G04_0_Pos) /*!< LCD PAL217: G04_0 Mask */
+#define LCD_PAL217_B04_0_Pos 10 /*!< LCD PAL217: B04_0 Position */
+#define LCD_PAL217_B04_0_Msk (0x1fUL << LCD_PAL217_B04_0_Pos) /*!< LCD PAL217: B04_0 Mask */
+#define LCD_PAL217_I0_Pos 15 /*!< LCD PAL217: I0 Position */
+#define LCD_PAL217_I0_Msk (0x01UL << LCD_PAL217_I0_Pos) /*!< LCD PAL217: I0 Mask */
+#define LCD_PAL217_R14_0_Pos 16 /*!< LCD PAL217: R14_0 Position */
+#define LCD_PAL217_R14_0_Msk (0x1fUL << LCD_PAL217_R14_0_Pos) /*!< LCD PAL217: R14_0 Mask */
+#define LCD_PAL217_G14_0_Pos 21 /*!< LCD PAL217: G14_0 Position */
+#define LCD_PAL217_G14_0_Msk (0x1fUL << LCD_PAL217_G14_0_Pos) /*!< LCD PAL217: G14_0 Mask */
+#define LCD_PAL217_B14_0_Pos 26 /*!< LCD PAL217: B14_0 Position */
+#define LCD_PAL217_B14_0_Msk (0x1fUL << LCD_PAL217_B14_0_Pos) /*!< LCD PAL217: B14_0 Mask */
+#define LCD_PAL217_I1_Pos 31 /*!< LCD PAL217: I1 Position */
+#define LCD_PAL217_I1_Msk (0x01UL << LCD_PAL217_I1_Pos) /*!< LCD PAL217: I1 Mask */
+
+// --------------------------------------- LCD_PAL218 -------------------------------------------
+#define LCD_PAL218_R04_0_Pos 0 /*!< LCD PAL218: R04_0 Position */
+#define LCD_PAL218_R04_0_Msk (0x1fUL << LCD_PAL218_R04_0_Pos) /*!< LCD PAL218: R04_0 Mask */
+#define LCD_PAL218_G04_0_Pos 5 /*!< LCD PAL218: G04_0 Position */
+#define LCD_PAL218_G04_0_Msk (0x1fUL << LCD_PAL218_G04_0_Pos) /*!< LCD PAL218: G04_0 Mask */
+#define LCD_PAL218_B04_0_Pos 10 /*!< LCD PAL218: B04_0 Position */
+#define LCD_PAL218_B04_0_Msk (0x1fUL << LCD_PAL218_B04_0_Pos) /*!< LCD PAL218: B04_0 Mask */
+#define LCD_PAL218_I0_Pos 15 /*!< LCD PAL218: I0 Position */
+#define LCD_PAL218_I0_Msk (0x01UL << LCD_PAL218_I0_Pos) /*!< LCD PAL218: I0 Mask */
+#define LCD_PAL218_R14_0_Pos 16 /*!< LCD PAL218: R14_0 Position */
+#define LCD_PAL218_R14_0_Msk (0x1fUL << LCD_PAL218_R14_0_Pos) /*!< LCD PAL218: R14_0 Mask */
+#define LCD_PAL218_G14_0_Pos 21 /*!< LCD PAL218: G14_0 Position */
+#define LCD_PAL218_G14_0_Msk (0x1fUL << LCD_PAL218_G14_0_Pos) /*!< LCD PAL218: G14_0 Mask */
+#define LCD_PAL218_B14_0_Pos 26 /*!< LCD PAL218: B14_0 Position */
+#define LCD_PAL218_B14_0_Msk (0x1fUL << LCD_PAL218_B14_0_Pos) /*!< LCD PAL218: B14_0 Mask */
+#define LCD_PAL218_I1_Pos 31 /*!< LCD PAL218: I1 Position */
+#define LCD_PAL218_I1_Msk (0x01UL << LCD_PAL218_I1_Pos) /*!< LCD PAL218: I1 Mask */
+
+// --------------------------------------- LCD_PAL219 -------------------------------------------
+#define LCD_PAL219_R04_0_Pos 0 /*!< LCD PAL219: R04_0 Position */
+#define LCD_PAL219_R04_0_Msk (0x1fUL << LCD_PAL219_R04_0_Pos) /*!< LCD PAL219: R04_0 Mask */
+#define LCD_PAL219_G04_0_Pos 5 /*!< LCD PAL219: G04_0 Position */
+#define LCD_PAL219_G04_0_Msk (0x1fUL << LCD_PAL219_G04_0_Pos) /*!< LCD PAL219: G04_0 Mask */
+#define LCD_PAL219_B04_0_Pos 10 /*!< LCD PAL219: B04_0 Position */
+#define LCD_PAL219_B04_0_Msk (0x1fUL << LCD_PAL219_B04_0_Pos) /*!< LCD PAL219: B04_0 Mask */
+#define LCD_PAL219_I0_Pos 15 /*!< LCD PAL219: I0 Position */
+#define LCD_PAL219_I0_Msk (0x01UL << LCD_PAL219_I0_Pos) /*!< LCD PAL219: I0 Mask */
+#define LCD_PAL219_R14_0_Pos 16 /*!< LCD PAL219: R14_0 Position */
+#define LCD_PAL219_R14_0_Msk (0x1fUL << LCD_PAL219_R14_0_Pos) /*!< LCD PAL219: R14_0 Mask */
+#define LCD_PAL219_G14_0_Pos 21 /*!< LCD PAL219: G14_0 Position */
+#define LCD_PAL219_G14_0_Msk (0x1fUL << LCD_PAL219_G14_0_Pos) /*!< LCD PAL219: G14_0 Mask */
+#define LCD_PAL219_B14_0_Pos 26 /*!< LCD PAL219: B14_0 Position */
+#define LCD_PAL219_B14_0_Msk (0x1fUL << LCD_PAL219_B14_0_Pos) /*!< LCD PAL219: B14_0 Mask */
+#define LCD_PAL219_I1_Pos 31 /*!< LCD PAL219: I1 Position */
+#define LCD_PAL219_I1_Msk (0x01UL << LCD_PAL219_I1_Pos) /*!< LCD PAL219: I1 Mask */
+
+// --------------------------------------- LCD_PAL220 -------------------------------------------
+#define LCD_PAL220_R04_0_Pos 0 /*!< LCD PAL220: R04_0 Position */
+#define LCD_PAL220_R04_0_Msk (0x1fUL << LCD_PAL220_R04_0_Pos) /*!< LCD PAL220: R04_0 Mask */
+#define LCD_PAL220_G04_0_Pos 5 /*!< LCD PAL220: G04_0 Position */
+#define LCD_PAL220_G04_0_Msk (0x1fUL << LCD_PAL220_G04_0_Pos) /*!< LCD PAL220: G04_0 Mask */
+#define LCD_PAL220_B04_0_Pos 10 /*!< LCD PAL220: B04_0 Position */
+#define LCD_PAL220_B04_0_Msk (0x1fUL << LCD_PAL220_B04_0_Pos) /*!< LCD PAL220: B04_0 Mask */
+#define LCD_PAL220_I0_Pos 15 /*!< LCD PAL220: I0 Position */
+#define LCD_PAL220_I0_Msk (0x01UL << LCD_PAL220_I0_Pos) /*!< LCD PAL220: I0 Mask */
+#define LCD_PAL220_R14_0_Pos 16 /*!< LCD PAL220: R14_0 Position */
+#define LCD_PAL220_R14_0_Msk (0x1fUL << LCD_PAL220_R14_0_Pos) /*!< LCD PAL220: R14_0 Mask */
+#define LCD_PAL220_G14_0_Pos 21 /*!< LCD PAL220: G14_0 Position */
+#define LCD_PAL220_G14_0_Msk (0x1fUL << LCD_PAL220_G14_0_Pos) /*!< LCD PAL220: G14_0 Mask */
+#define LCD_PAL220_B14_0_Pos 26 /*!< LCD PAL220: B14_0 Position */
+#define LCD_PAL220_B14_0_Msk (0x1fUL << LCD_PAL220_B14_0_Pos) /*!< LCD PAL220: B14_0 Mask */
+#define LCD_PAL220_I1_Pos 31 /*!< LCD PAL220: I1 Position */
+#define LCD_PAL220_I1_Msk (0x01UL << LCD_PAL220_I1_Pos) /*!< LCD PAL220: I1 Mask */
+
+// --------------------------------------- LCD_PAL221 -------------------------------------------
+#define LCD_PAL221_R04_0_Pos 0 /*!< LCD PAL221: R04_0 Position */
+#define LCD_PAL221_R04_0_Msk (0x1fUL << LCD_PAL221_R04_0_Pos) /*!< LCD PAL221: R04_0 Mask */
+#define LCD_PAL221_G04_0_Pos 5 /*!< LCD PAL221: G04_0 Position */
+#define LCD_PAL221_G04_0_Msk (0x1fUL << LCD_PAL221_G04_0_Pos) /*!< LCD PAL221: G04_0 Mask */
+#define LCD_PAL221_B04_0_Pos 10 /*!< LCD PAL221: B04_0 Position */
+#define LCD_PAL221_B04_0_Msk (0x1fUL << LCD_PAL221_B04_0_Pos) /*!< LCD PAL221: B04_0 Mask */
+#define LCD_PAL221_I0_Pos 15 /*!< LCD PAL221: I0 Position */
+#define LCD_PAL221_I0_Msk (0x01UL << LCD_PAL221_I0_Pos) /*!< LCD PAL221: I0 Mask */
+#define LCD_PAL221_R14_0_Pos 16 /*!< LCD PAL221: R14_0 Position */
+#define LCD_PAL221_R14_0_Msk (0x1fUL << LCD_PAL221_R14_0_Pos) /*!< LCD PAL221: R14_0 Mask */
+#define LCD_PAL221_G14_0_Pos 21 /*!< LCD PAL221: G14_0 Position */
+#define LCD_PAL221_G14_0_Msk (0x1fUL << LCD_PAL221_G14_0_Pos) /*!< LCD PAL221: G14_0 Mask */
+#define LCD_PAL221_B14_0_Pos 26 /*!< LCD PAL221: B14_0 Position */
+#define LCD_PAL221_B14_0_Msk (0x1fUL << LCD_PAL221_B14_0_Pos) /*!< LCD PAL221: B14_0 Mask */
+#define LCD_PAL221_I1_Pos 31 /*!< LCD PAL221: I1 Position */
+#define LCD_PAL221_I1_Msk (0x01UL << LCD_PAL221_I1_Pos) /*!< LCD PAL221: I1 Mask */
+
+// --------------------------------------- LCD_PAL222 -------------------------------------------
+#define LCD_PAL222_R04_0_Pos 0 /*!< LCD PAL222: R04_0 Position */
+#define LCD_PAL222_R04_0_Msk (0x1fUL << LCD_PAL222_R04_0_Pos) /*!< LCD PAL222: R04_0 Mask */
+#define LCD_PAL222_G04_0_Pos 5 /*!< LCD PAL222: G04_0 Position */
+#define LCD_PAL222_G04_0_Msk (0x1fUL << LCD_PAL222_G04_0_Pos) /*!< LCD PAL222: G04_0 Mask */
+#define LCD_PAL222_B04_0_Pos 10 /*!< LCD PAL222: B04_0 Position */
+#define LCD_PAL222_B04_0_Msk (0x1fUL << LCD_PAL222_B04_0_Pos) /*!< LCD PAL222: B04_0 Mask */
+#define LCD_PAL222_I0_Pos 15 /*!< LCD PAL222: I0 Position */
+#define LCD_PAL222_I0_Msk (0x01UL << LCD_PAL222_I0_Pos) /*!< LCD PAL222: I0 Mask */
+#define LCD_PAL222_R14_0_Pos 16 /*!< LCD PAL222: R14_0 Position */
+#define LCD_PAL222_R14_0_Msk (0x1fUL << LCD_PAL222_R14_0_Pos) /*!< LCD PAL222: R14_0 Mask */
+#define LCD_PAL222_G14_0_Pos 21 /*!< LCD PAL222: G14_0 Position */
+#define LCD_PAL222_G14_0_Msk (0x1fUL << LCD_PAL222_G14_0_Pos) /*!< LCD PAL222: G14_0 Mask */
+#define LCD_PAL222_B14_0_Pos 26 /*!< LCD PAL222: B14_0 Position */
+#define LCD_PAL222_B14_0_Msk (0x1fUL << LCD_PAL222_B14_0_Pos) /*!< LCD PAL222: B14_0 Mask */
+#define LCD_PAL222_I1_Pos 31 /*!< LCD PAL222: I1 Position */
+#define LCD_PAL222_I1_Msk (0x01UL << LCD_PAL222_I1_Pos) /*!< LCD PAL222: I1 Mask */
+
+// --------------------------------------- LCD_PAL223 -------------------------------------------
+#define LCD_PAL223_R04_0_Pos 0 /*!< LCD PAL223: R04_0 Position */
+#define LCD_PAL223_R04_0_Msk (0x1fUL << LCD_PAL223_R04_0_Pos) /*!< LCD PAL223: R04_0 Mask */
+#define LCD_PAL223_G04_0_Pos 5 /*!< LCD PAL223: G04_0 Position */
+#define LCD_PAL223_G04_0_Msk (0x1fUL << LCD_PAL223_G04_0_Pos) /*!< LCD PAL223: G04_0 Mask */
+#define LCD_PAL223_B04_0_Pos 10 /*!< LCD PAL223: B04_0 Position */
+#define LCD_PAL223_B04_0_Msk (0x1fUL << LCD_PAL223_B04_0_Pos) /*!< LCD PAL223: B04_0 Mask */
+#define LCD_PAL223_I0_Pos 15 /*!< LCD PAL223: I0 Position */
+#define LCD_PAL223_I0_Msk (0x01UL << LCD_PAL223_I0_Pos) /*!< LCD PAL223: I0 Mask */
+#define LCD_PAL223_R14_0_Pos 16 /*!< LCD PAL223: R14_0 Position */
+#define LCD_PAL223_R14_0_Msk (0x1fUL << LCD_PAL223_R14_0_Pos) /*!< LCD PAL223: R14_0 Mask */
+#define LCD_PAL223_G14_0_Pos 21 /*!< LCD PAL223: G14_0 Position */
+#define LCD_PAL223_G14_0_Msk (0x1fUL << LCD_PAL223_G14_0_Pos) /*!< LCD PAL223: G14_0 Mask */
+#define LCD_PAL223_B14_0_Pos 26 /*!< LCD PAL223: B14_0 Position */
+#define LCD_PAL223_B14_0_Msk (0x1fUL << LCD_PAL223_B14_0_Pos) /*!< LCD PAL223: B14_0 Mask */
+#define LCD_PAL223_I1_Pos 31 /*!< LCD PAL223: I1 Position */
+#define LCD_PAL223_I1_Msk (0x01UL << LCD_PAL223_I1_Pos) /*!< LCD PAL223: I1 Mask */
+
+// --------------------------------------- LCD_PAL224 -------------------------------------------
+#define LCD_PAL224_R04_0_Pos 0 /*!< LCD PAL224: R04_0 Position */
+#define LCD_PAL224_R04_0_Msk (0x1fUL << LCD_PAL224_R04_0_Pos) /*!< LCD PAL224: R04_0 Mask */
+#define LCD_PAL224_G04_0_Pos 5 /*!< LCD PAL224: G04_0 Position */
+#define LCD_PAL224_G04_0_Msk (0x1fUL << LCD_PAL224_G04_0_Pos) /*!< LCD PAL224: G04_0 Mask */
+#define LCD_PAL224_B04_0_Pos 10 /*!< LCD PAL224: B04_0 Position */
+#define LCD_PAL224_B04_0_Msk (0x1fUL << LCD_PAL224_B04_0_Pos) /*!< LCD PAL224: B04_0 Mask */
+#define LCD_PAL224_I0_Pos 15 /*!< LCD PAL224: I0 Position */
+#define LCD_PAL224_I0_Msk (0x01UL << LCD_PAL224_I0_Pos) /*!< LCD PAL224: I0 Mask */
+#define LCD_PAL224_R14_0_Pos 16 /*!< LCD PAL224: R14_0 Position */
+#define LCD_PAL224_R14_0_Msk (0x1fUL << LCD_PAL224_R14_0_Pos) /*!< LCD PAL224: R14_0 Mask */
+#define LCD_PAL224_G14_0_Pos 21 /*!< LCD PAL224: G14_0 Position */
+#define LCD_PAL224_G14_0_Msk (0x1fUL << LCD_PAL224_G14_0_Pos) /*!< LCD PAL224: G14_0 Mask */
+#define LCD_PAL224_B14_0_Pos 26 /*!< LCD PAL224: B14_0 Position */
+#define LCD_PAL224_B14_0_Msk (0x1fUL << LCD_PAL224_B14_0_Pos) /*!< LCD PAL224: B14_0 Mask */
+#define LCD_PAL224_I1_Pos 31 /*!< LCD PAL224: I1 Position */
+#define LCD_PAL224_I1_Msk (0x01UL << LCD_PAL224_I1_Pos) /*!< LCD PAL224: I1 Mask */
+
+// --------------------------------------- LCD_PAL225 -------------------------------------------
+#define LCD_PAL225_R04_0_Pos 0 /*!< LCD PAL225: R04_0 Position */
+#define LCD_PAL225_R04_0_Msk (0x1fUL << LCD_PAL225_R04_0_Pos) /*!< LCD PAL225: R04_0 Mask */
+#define LCD_PAL225_G04_0_Pos 5 /*!< LCD PAL225: G04_0 Position */
+#define LCD_PAL225_G04_0_Msk (0x1fUL << LCD_PAL225_G04_0_Pos) /*!< LCD PAL225: G04_0 Mask */
+#define LCD_PAL225_B04_0_Pos 10 /*!< LCD PAL225: B04_0 Position */
+#define LCD_PAL225_B04_0_Msk (0x1fUL << LCD_PAL225_B04_0_Pos) /*!< LCD PAL225: B04_0 Mask */
+#define LCD_PAL225_I0_Pos 15 /*!< LCD PAL225: I0 Position */
+#define LCD_PAL225_I0_Msk (0x01UL << LCD_PAL225_I0_Pos) /*!< LCD PAL225: I0 Mask */
+#define LCD_PAL225_R14_0_Pos 16 /*!< LCD PAL225: R14_0 Position */
+#define LCD_PAL225_R14_0_Msk (0x1fUL << LCD_PAL225_R14_0_Pos) /*!< LCD PAL225: R14_0 Mask */
+#define LCD_PAL225_G14_0_Pos 21 /*!< LCD PAL225: G14_0 Position */
+#define LCD_PAL225_G14_0_Msk (0x1fUL << LCD_PAL225_G14_0_Pos) /*!< LCD PAL225: G14_0 Mask */
+#define LCD_PAL225_B14_0_Pos 26 /*!< LCD PAL225: B14_0 Position */
+#define LCD_PAL225_B14_0_Msk (0x1fUL << LCD_PAL225_B14_0_Pos) /*!< LCD PAL225: B14_0 Mask */
+#define LCD_PAL225_I1_Pos 31 /*!< LCD PAL225: I1 Position */
+#define LCD_PAL225_I1_Msk (0x01UL << LCD_PAL225_I1_Pos) /*!< LCD PAL225: I1 Mask */
+
+// --------------------------------------- LCD_PAL226 -------------------------------------------
+#define LCD_PAL226_R04_0_Pos 0 /*!< LCD PAL226: R04_0 Position */
+#define LCD_PAL226_R04_0_Msk (0x1fUL << LCD_PAL226_R04_0_Pos) /*!< LCD PAL226: R04_0 Mask */
+#define LCD_PAL226_G04_0_Pos 5 /*!< LCD PAL226: G04_0 Position */
+#define LCD_PAL226_G04_0_Msk (0x1fUL << LCD_PAL226_G04_0_Pos) /*!< LCD PAL226: G04_0 Mask */
+#define LCD_PAL226_B04_0_Pos 10 /*!< LCD PAL226: B04_0 Position */
+#define LCD_PAL226_B04_0_Msk (0x1fUL << LCD_PAL226_B04_0_Pos) /*!< LCD PAL226: B04_0 Mask */
+#define LCD_PAL226_I0_Pos 15 /*!< LCD PAL226: I0 Position */
+#define LCD_PAL226_I0_Msk (0x01UL << LCD_PAL226_I0_Pos) /*!< LCD PAL226: I0 Mask */
+#define LCD_PAL226_R14_0_Pos 16 /*!< LCD PAL226: R14_0 Position */
+#define LCD_PAL226_R14_0_Msk (0x1fUL << LCD_PAL226_R14_0_Pos) /*!< LCD PAL226: R14_0 Mask */
+#define LCD_PAL226_G14_0_Pos 21 /*!< LCD PAL226: G14_0 Position */
+#define LCD_PAL226_G14_0_Msk (0x1fUL << LCD_PAL226_G14_0_Pos) /*!< LCD PAL226: G14_0 Mask */
+#define LCD_PAL226_B14_0_Pos 26 /*!< LCD PAL226: B14_0 Position */
+#define LCD_PAL226_B14_0_Msk (0x1fUL << LCD_PAL226_B14_0_Pos) /*!< LCD PAL226: B14_0 Mask */
+#define LCD_PAL226_I1_Pos 31 /*!< LCD PAL226: I1 Position */
+#define LCD_PAL226_I1_Msk (0x01UL << LCD_PAL226_I1_Pos) /*!< LCD PAL226: I1 Mask */
+
+// --------------------------------------- LCD_PAL227 -------------------------------------------
+#define LCD_PAL227_R04_0_Pos 0 /*!< LCD PAL227: R04_0 Position */
+#define LCD_PAL227_R04_0_Msk (0x1fUL << LCD_PAL227_R04_0_Pos) /*!< LCD PAL227: R04_0 Mask */
+#define LCD_PAL227_G04_0_Pos 5 /*!< LCD PAL227: G04_0 Position */
+#define LCD_PAL227_G04_0_Msk (0x1fUL << LCD_PAL227_G04_0_Pos) /*!< LCD PAL227: G04_0 Mask */
+#define LCD_PAL227_B04_0_Pos 10 /*!< LCD PAL227: B04_0 Position */
+#define LCD_PAL227_B04_0_Msk (0x1fUL << LCD_PAL227_B04_0_Pos) /*!< LCD PAL227: B04_0 Mask */
+#define LCD_PAL227_I0_Pos 15 /*!< LCD PAL227: I0 Position */
+#define LCD_PAL227_I0_Msk (0x01UL << LCD_PAL227_I0_Pos) /*!< LCD PAL227: I0 Mask */
+#define LCD_PAL227_R14_0_Pos 16 /*!< LCD PAL227: R14_0 Position */
+#define LCD_PAL227_R14_0_Msk (0x1fUL << LCD_PAL227_R14_0_Pos) /*!< LCD PAL227: R14_0 Mask */
+#define LCD_PAL227_G14_0_Pos 21 /*!< LCD PAL227: G14_0 Position */
+#define LCD_PAL227_G14_0_Msk (0x1fUL << LCD_PAL227_G14_0_Pos) /*!< LCD PAL227: G14_0 Mask */
+#define LCD_PAL227_B14_0_Pos 26 /*!< LCD PAL227: B14_0 Position */
+#define LCD_PAL227_B14_0_Msk (0x1fUL << LCD_PAL227_B14_0_Pos) /*!< LCD PAL227: B14_0 Mask */
+#define LCD_PAL227_I1_Pos 31 /*!< LCD PAL227: I1 Position */
+#define LCD_PAL227_I1_Msk (0x01UL << LCD_PAL227_I1_Pos) /*!< LCD PAL227: I1 Mask */
+
+// --------------------------------------- LCD_PAL228 -------------------------------------------
+#define LCD_PAL228_R04_0_Pos 0 /*!< LCD PAL228: R04_0 Position */
+#define LCD_PAL228_R04_0_Msk (0x1fUL << LCD_PAL228_R04_0_Pos) /*!< LCD PAL228: R04_0 Mask */
+#define LCD_PAL228_G04_0_Pos 5 /*!< LCD PAL228: G04_0 Position */
+#define LCD_PAL228_G04_0_Msk (0x1fUL << LCD_PAL228_G04_0_Pos) /*!< LCD PAL228: G04_0 Mask */
+#define LCD_PAL228_B04_0_Pos 10 /*!< LCD PAL228: B04_0 Position */
+#define LCD_PAL228_B04_0_Msk (0x1fUL << LCD_PAL228_B04_0_Pos) /*!< LCD PAL228: B04_0 Mask */
+#define LCD_PAL228_I0_Pos 15 /*!< LCD PAL228: I0 Position */
+#define LCD_PAL228_I0_Msk (0x01UL << LCD_PAL228_I0_Pos) /*!< LCD PAL228: I0 Mask */
+#define LCD_PAL228_R14_0_Pos 16 /*!< LCD PAL228: R14_0 Position */
+#define LCD_PAL228_R14_0_Msk (0x1fUL << LCD_PAL228_R14_0_Pos) /*!< LCD PAL228: R14_0 Mask */
+#define LCD_PAL228_G14_0_Pos 21 /*!< LCD PAL228: G14_0 Position */
+#define LCD_PAL228_G14_0_Msk (0x1fUL << LCD_PAL228_G14_0_Pos) /*!< LCD PAL228: G14_0 Mask */
+#define LCD_PAL228_B14_0_Pos 26 /*!< LCD PAL228: B14_0 Position */
+#define LCD_PAL228_B14_0_Msk (0x1fUL << LCD_PAL228_B14_0_Pos) /*!< LCD PAL228: B14_0 Mask */
+#define LCD_PAL228_I1_Pos 31 /*!< LCD PAL228: I1 Position */
+#define LCD_PAL228_I1_Msk (0x01UL << LCD_PAL228_I1_Pos) /*!< LCD PAL228: I1 Mask */
+
+// --------------------------------------- LCD_PAL229 -------------------------------------------
+#define LCD_PAL229_R04_0_Pos 0 /*!< LCD PAL229: R04_0 Position */
+#define LCD_PAL229_R04_0_Msk (0x1fUL << LCD_PAL229_R04_0_Pos) /*!< LCD PAL229: R04_0 Mask */
+#define LCD_PAL229_G04_0_Pos 5 /*!< LCD PAL229: G04_0 Position */
+#define LCD_PAL229_G04_0_Msk (0x1fUL << LCD_PAL229_G04_0_Pos) /*!< LCD PAL229: G04_0 Mask */
+#define LCD_PAL229_B04_0_Pos 10 /*!< LCD PAL229: B04_0 Position */
+#define LCD_PAL229_B04_0_Msk (0x1fUL << LCD_PAL229_B04_0_Pos) /*!< LCD PAL229: B04_0 Mask */
+#define LCD_PAL229_I0_Pos 15 /*!< LCD PAL229: I0 Position */
+#define LCD_PAL229_I0_Msk (0x01UL << LCD_PAL229_I0_Pos) /*!< LCD PAL229: I0 Mask */
+#define LCD_PAL229_R14_0_Pos 16 /*!< LCD PAL229: R14_0 Position */
+#define LCD_PAL229_R14_0_Msk (0x1fUL << LCD_PAL229_R14_0_Pos) /*!< LCD PAL229: R14_0 Mask */
+#define LCD_PAL229_G14_0_Pos 21 /*!< LCD PAL229: G14_0 Position */
+#define LCD_PAL229_G14_0_Msk (0x1fUL << LCD_PAL229_G14_0_Pos) /*!< LCD PAL229: G14_0 Mask */
+#define LCD_PAL229_B14_0_Pos 26 /*!< LCD PAL229: B14_0 Position */
+#define LCD_PAL229_B14_0_Msk (0x1fUL << LCD_PAL229_B14_0_Pos) /*!< LCD PAL229: B14_0 Mask */
+#define LCD_PAL229_I1_Pos 31 /*!< LCD PAL229: I1 Position */
+#define LCD_PAL229_I1_Msk (0x01UL << LCD_PAL229_I1_Pos) /*!< LCD PAL229: I1 Mask */
+
+// --------------------------------------- LCD_PAL230 -------------------------------------------
+#define LCD_PAL230_R04_0_Pos 0 /*!< LCD PAL230: R04_0 Position */
+#define LCD_PAL230_R04_0_Msk (0x1fUL << LCD_PAL230_R04_0_Pos) /*!< LCD PAL230: R04_0 Mask */
+#define LCD_PAL230_G04_0_Pos 5 /*!< LCD PAL230: G04_0 Position */
+#define LCD_PAL230_G04_0_Msk (0x1fUL << LCD_PAL230_G04_0_Pos) /*!< LCD PAL230: G04_0 Mask */
+#define LCD_PAL230_B04_0_Pos 10 /*!< LCD PAL230: B04_0 Position */
+#define LCD_PAL230_B04_0_Msk (0x1fUL << LCD_PAL230_B04_0_Pos) /*!< LCD PAL230: B04_0 Mask */
+#define LCD_PAL230_I0_Pos 15 /*!< LCD PAL230: I0 Position */
+#define LCD_PAL230_I0_Msk (0x01UL << LCD_PAL230_I0_Pos) /*!< LCD PAL230: I0 Mask */
+#define LCD_PAL230_R14_0_Pos 16 /*!< LCD PAL230: R14_0 Position */
+#define LCD_PAL230_R14_0_Msk (0x1fUL << LCD_PAL230_R14_0_Pos) /*!< LCD PAL230: R14_0 Mask */
+#define LCD_PAL230_G14_0_Pos 21 /*!< LCD PAL230: G14_0 Position */
+#define LCD_PAL230_G14_0_Msk (0x1fUL << LCD_PAL230_G14_0_Pos) /*!< LCD PAL230: G14_0 Mask */
+#define LCD_PAL230_B14_0_Pos 26 /*!< LCD PAL230: B14_0 Position */
+#define LCD_PAL230_B14_0_Msk (0x1fUL << LCD_PAL230_B14_0_Pos) /*!< LCD PAL230: B14_0 Mask */
+#define LCD_PAL230_I1_Pos 31 /*!< LCD PAL230: I1 Position */
+#define LCD_PAL230_I1_Msk (0x01UL << LCD_PAL230_I1_Pos) /*!< LCD PAL230: I1 Mask */
+
+// --------------------------------------- LCD_PAL231 -------------------------------------------
+#define LCD_PAL231_R04_0_Pos 0 /*!< LCD PAL231: R04_0 Position */
+#define LCD_PAL231_R04_0_Msk (0x1fUL << LCD_PAL231_R04_0_Pos) /*!< LCD PAL231: R04_0 Mask */
+#define LCD_PAL231_G04_0_Pos 5 /*!< LCD PAL231: G04_0 Position */
+#define LCD_PAL231_G04_0_Msk (0x1fUL << LCD_PAL231_G04_0_Pos) /*!< LCD PAL231: G04_0 Mask */
+#define LCD_PAL231_B04_0_Pos 10 /*!< LCD PAL231: B04_0 Position */
+#define LCD_PAL231_B04_0_Msk (0x1fUL << LCD_PAL231_B04_0_Pos) /*!< LCD PAL231: B04_0 Mask */
+#define LCD_PAL231_I0_Pos 15 /*!< LCD PAL231: I0 Position */
+#define LCD_PAL231_I0_Msk (0x01UL << LCD_PAL231_I0_Pos) /*!< LCD PAL231: I0 Mask */
+#define LCD_PAL231_R14_0_Pos 16 /*!< LCD PAL231: R14_0 Position */
+#define LCD_PAL231_R14_0_Msk (0x1fUL << LCD_PAL231_R14_0_Pos) /*!< LCD PAL231: R14_0 Mask */
+#define LCD_PAL231_G14_0_Pos 21 /*!< LCD PAL231: G14_0 Position */
+#define LCD_PAL231_G14_0_Msk (0x1fUL << LCD_PAL231_G14_0_Pos) /*!< LCD PAL231: G14_0 Mask */
+#define LCD_PAL231_B14_0_Pos 26 /*!< LCD PAL231: B14_0 Position */
+#define LCD_PAL231_B14_0_Msk (0x1fUL << LCD_PAL231_B14_0_Pos) /*!< LCD PAL231: B14_0 Mask */
+#define LCD_PAL231_I1_Pos 31 /*!< LCD PAL231: I1 Position */
+#define LCD_PAL231_I1_Msk (0x01UL << LCD_PAL231_I1_Pos) /*!< LCD PAL231: I1 Mask */
+
+// --------------------------------------- LCD_PAL232 -------------------------------------------
+#define LCD_PAL232_R04_0_Pos 0 /*!< LCD PAL232: R04_0 Position */
+#define LCD_PAL232_R04_0_Msk (0x1fUL << LCD_PAL232_R04_0_Pos) /*!< LCD PAL232: R04_0 Mask */
+#define LCD_PAL232_G04_0_Pos 5 /*!< LCD PAL232: G04_0 Position */
+#define LCD_PAL232_G04_0_Msk (0x1fUL << LCD_PAL232_G04_0_Pos) /*!< LCD PAL232: G04_0 Mask */
+#define LCD_PAL232_B04_0_Pos 10 /*!< LCD PAL232: B04_0 Position */
+#define LCD_PAL232_B04_0_Msk (0x1fUL << LCD_PAL232_B04_0_Pos) /*!< LCD PAL232: B04_0 Mask */
+#define LCD_PAL232_I0_Pos 15 /*!< LCD PAL232: I0 Position */
+#define LCD_PAL232_I0_Msk (0x01UL << LCD_PAL232_I0_Pos) /*!< LCD PAL232: I0 Mask */
+#define LCD_PAL232_R14_0_Pos 16 /*!< LCD PAL232: R14_0 Position */
+#define LCD_PAL232_R14_0_Msk (0x1fUL << LCD_PAL232_R14_0_Pos) /*!< LCD PAL232: R14_0 Mask */
+#define LCD_PAL232_G14_0_Pos 21 /*!< LCD PAL232: G14_0 Position */
+#define LCD_PAL232_G14_0_Msk (0x1fUL << LCD_PAL232_G14_0_Pos) /*!< LCD PAL232: G14_0 Mask */
+#define LCD_PAL232_B14_0_Pos 26 /*!< LCD PAL232: B14_0 Position */
+#define LCD_PAL232_B14_0_Msk (0x1fUL << LCD_PAL232_B14_0_Pos) /*!< LCD PAL232: B14_0 Mask */
+#define LCD_PAL232_I1_Pos 31 /*!< LCD PAL232: I1 Position */
+#define LCD_PAL232_I1_Msk (0x01UL << LCD_PAL232_I1_Pos) /*!< LCD PAL232: I1 Mask */
+
+// --------------------------------------- LCD_PAL233 -------------------------------------------
+#define LCD_PAL233_R04_0_Pos 0 /*!< LCD PAL233: R04_0 Position */
+#define LCD_PAL233_R04_0_Msk (0x1fUL << LCD_PAL233_R04_0_Pos) /*!< LCD PAL233: R04_0 Mask */
+#define LCD_PAL233_G04_0_Pos 5 /*!< LCD PAL233: G04_0 Position */
+#define LCD_PAL233_G04_0_Msk (0x1fUL << LCD_PAL233_G04_0_Pos) /*!< LCD PAL233: G04_0 Mask */
+#define LCD_PAL233_B04_0_Pos 10 /*!< LCD PAL233: B04_0 Position */
+#define LCD_PAL233_B04_0_Msk (0x1fUL << LCD_PAL233_B04_0_Pos) /*!< LCD PAL233: B04_0 Mask */
+#define LCD_PAL233_I0_Pos 15 /*!< LCD PAL233: I0 Position */
+#define LCD_PAL233_I0_Msk (0x01UL << LCD_PAL233_I0_Pos) /*!< LCD PAL233: I0 Mask */
+#define LCD_PAL233_R14_0_Pos 16 /*!< LCD PAL233: R14_0 Position */
+#define LCD_PAL233_R14_0_Msk (0x1fUL << LCD_PAL233_R14_0_Pos) /*!< LCD PAL233: R14_0 Mask */
+#define LCD_PAL233_G14_0_Pos 21 /*!< LCD PAL233: G14_0 Position */
+#define LCD_PAL233_G14_0_Msk (0x1fUL << LCD_PAL233_G14_0_Pos) /*!< LCD PAL233: G14_0 Mask */
+#define LCD_PAL233_B14_0_Pos 26 /*!< LCD PAL233: B14_0 Position */
+#define LCD_PAL233_B14_0_Msk (0x1fUL << LCD_PAL233_B14_0_Pos) /*!< LCD PAL233: B14_0 Mask */
+#define LCD_PAL233_I1_Pos 31 /*!< LCD PAL233: I1 Position */
+#define LCD_PAL233_I1_Msk (0x01UL << LCD_PAL233_I1_Pos) /*!< LCD PAL233: I1 Mask */
+
+// --------------------------------------- LCD_PAL234 -------------------------------------------
+#define LCD_PAL234_R04_0_Pos 0 /*!< LCD PAL234: R04_0 Position */
+#define LCD_PAL234_R04_0_Msk (0x1fUL << LCD_PAL234_R04_0_Pos) /*!< LCD PAL234: R04_0 Mask */
+#define LCD_PAL234_G04_0_Pos 5 /*!< LCD PAL234: G04_0 Position */
+#define LCD_PAL234_G04_0_Msk (0x1fUL << LCD_PAL234_G04_0_Pos) /*!< LCD PAL234: G04_0 Mask */
+#define LCD_PAL234_B04_0_Pos 10 /*!< LCD PAL234: B04_0 Position */
+#define LCD_PAL234_B04_0_Msk (0x1fUL << LCD_PAL234_B04_0_Pos) /*!< LCD PAL234: B04_0 Mask */
+#define LCD_PAL234_I0_Pos 15 /*!< LCD PAL234: I0 Position */
+#define LCD_PAL234_I0_Msk (0x01UL << LCD_PAL234_I0_Pos) /*!< LCD PAL234: I0 Mask */
+#define LCD_PAL234_R14_0_Pos 16 /*!< LCD PAL234: R14_0 Position */
+#define LCD_PAL234_R14_0_Msk (0x1fUL << LCD_PAL234_R14_0_Pos) /*!< LCD PAL234: R14_0 Mask */
+#define LCD_PAL234_G14_0_Pos 21 /*!< LCD PAL234: G14_0 Position */
+#define LCD_PAL234_G14_0_Msk (0x1fUL << LCD_PAL234_G14_0_Pos) /*!< LCD PAL234: G14_0 Mask */
+#define LCD_PAL234_B14_0_Pos 26 /*!< LCD PAL234: B14_0 Position */
+#define LCD_PAL234_B14_0_Msk (0x1fUL << LCD_PAL234_B14_0_Pos) /*!< LCD PAL234: B14_0 Mask */
+#define LCD_PAL234_I1_Pos 31 /*!< LCD PAL234: I1 Position */
+#define LCD_PAL234_I1_Msk (0x01UL << LCD_PAL234_I1_Pos) /*!< LCD PAL234: I1 Mask */
+
+// --------------------------------------- LCD_PAL235 -------------------------------------------
+#define LCD_PAL235_R04_0_Pos 0 /*!< LCD PAL235: R04_0 Position */
+#define LCD_PAL235_R04_0_Msk (0x1fUL << LCD_PAL235_R04_0_Pos) /*!< LCD PAL235: R04_0 Mask */
+#define LCD_PAL235_G04_0_Pos 5 /*!< LCD PAL235: G04_0 Position */
+#define LCD_PAL235_G04_0_Msk (0x1fUL << LCD_PAL235_G04_0_Pos) /*!< LCD PAL235: G04_0 Mask */
+#define LCD_PAL235_B04_0_Pos 10 /*!< LCD PAL235: B04_0 Position */
+#define LCD_PAL235_B04_0_Msk (0x1fUL << LCD_PAL235_B04_0_Pos) /*!< LCD PAL235: B04_0 Mask */
+#define LCD_PAL235_I0_Pos 15 /*!< LCD PAL235: I0 Position */
+#define LCD_PAL235_I0_Msk (0x01UL << LCD_PAL235_I0_Pos) /*!< LCD PAL235: I0 Mask */
+#define LCD_PAL235_R14_0_Pos 16 /*!< LCD PAL235: R14_0 Position */
+#define LCD_PAL235_R14_0_Msk (0x1fUL << LCD_PAL235_R14_0_Pos) /*!< LCD PAL235: R14_0 Mask */
+#define LCD_PAL235_G14_0_Pos 21 /*!< LCD PAL235: G14_0 Position */
+#define LCD_PAL235_G14_0_Msk (0x1fUL << LCD_PAL235_G14_0_Pos) /*!< LCD PAL235: G14_0 Mask */
+#define LCD_PAL235_B14_0_Pos 26 /*!< LCD PAL235: B14_0 Position */
+#define LCD_PAL235_B14_0_Msk (0x1fUL << LCD_PAL235_B14_0_Pos) /*!< LCD PAL235: B14_0 Mask */
+#define LCD_PAL235_I1_Pos 31 /*!< LCD PAL235: I1 Position */
+#define LCD_PAL235_I1_Msk (0x01UL << LCD_PAL235_I1_Pos) /*!< LCD PAL235: I1 Mask */
+
+// --------------------------------------- LCD_PAL236 -------------------------------------------
+#define LCD_PAL236_R04_0_Pos 0 /*!< LCD PAL236: R04_0 Position */
+#define LCD_PAL236_R04_0_Msk (0x1fUL << LCD_PAL236_R04_0_Pos) /*!< LCD PAL236: R04_0 Mask */
+#define LCD_PAL236_G04_0_Pos 5 /*!< LCD PAL236: G04_0 Position */
+#define LCD_PAL236_G04_0_Msk (0x1fUL << LCD_PAL236_G04_0_Pos) /*!< LCD PAL236: G04_0 Mask */
+#define LCD_PAL236_B04_0_Pos 10 /*!< LCD PAL236: B04_0 Position */
+#define LCD_PAL236_B04_0_Msk (0x1fUL << LCD_PAL236_B04_0_Pos) /*!< LCD PAL236: B04_0 Mask */
+#define LCD_PAL236_I0_Pos 15 /*!< LCD PAL236: I0 Position */
+#define LCD_PAL236_I0_Msk (0x01UL << LCD_PAL236_I0_Pos) /*!< LCD PAL236: I0 Mask */
+#define LCD_PAL236_R14_0_Pos 16 /*!< LCD PAL236: R14_0 Position */
+#define LCD_PAL236_R14_0_Msk (0x1fUL << LCD_PAL236_R14_0_Pos) /*!< LCD PAL236: R14_0 Mask */
+#define LCD_PAL236_G14_0_Pos 21 /*!< LCD PAL236: G14_0 Position */
+#define LCD_PAL236_G14_0_Msk (0x1fUL << LCD_PAL236_G14_0_Pos) /*!< LCD PAL236: G14_0 Mask */
+#define LCD_PAL236_B14_0_Pos 26 /*!< LCD PAL236: B14_0 Position */
+#define LCD_PAL236_B14_0_Msk (0x1fUL << LCD_PAL236_B14_0_Pos) /*!< LCD PAL236: B14_0 Mask */
+#define LCD_PAL236_I1_Pos 31 /*!< LCD PAL236: I1 Position */
+#define LCD_PAL236_I1_Msk (0x01UL << LCD_PAL236_I1_Pos) /*!< LCD PAL236: I1 Mask */
+
+// --------------------------------------- LCD_PAL237 -------------------------------------------
+#define LCD_PAL237_R04_0_Pos 0 /*!< LCD PAL237: R04_0 Position */
+#define LCD_PAL237_R04_0_Msk (0x1fUL << LCD_PAL237_R04_0_Pos) /*!< LCD PAL237: R04_0 Mask */
+#define LCD_PAL237_G04_0_Pos 5 /*!< LCD PAL237: G04_0 Position */
+#define LCD_PAL237_G04_0_Msk (0x1fUL << LCD_PAL237_G04_0_Pos) /*!< LCD PAL237: G04_0 Mask */
+#define LCD_PAL237_B04_0_Pos 10 /*!< LCD PAL237: B04_0 Position */
+#define LCD_PAL237_B04_0_Msk (0x1fUL << LCD_PAL237_B04_0_Pos) /*!< LCD PAL237: B04_0 Mask */
+#define LCD_PAL237_I0_Pos 15 /*!< LCD PAL237: I0 Position */
+#define LCD_PAL237_I0_Msk (0x01UL << LCD_PAL237_I0_Pos) /*!< LCD PAL237: I0 Mask */
+#define LCD_PAL237_R14_0_Pos 16 /*!< LCD PAL237: R14_0 Position */
+#define LCD_PAL237_R14_0_Msk (0x1fUL << LCD_PAL237_R14_0_Pos) /*!< LCD PAL237: R14_0 Mask */
+#define LCD_PAL237_G14_0_Pos 21 /*!< LCD PAL237: G14_0 Position */
+#define LCD_PAL237_G14_0_Msk (0x1fUL << LCD_PAL237_G14_0_Pos) /*!< LCD PAL237: G14_0 Mask */
+#define LCD_PAL237_B14_0_Pos 26 /*!< LCD PAL237: B14_0 Position */
+#define LCD_PAL237_B14_0_Msk (0x1fUL << LCD_PAL237_B14_0_Pos) /*!< LCD PAL237: B14_0 Mask */
+#define LCD_PAL237_I1_Pos 31 /*!< LCD PAL237: I1 Position */
+#define LCD_PAL237_I1_Msk (0x01UL << LCD_PAL237_I1_Pos) /*!< LCD PAL237: I1 Mask */
+
+// --------------------------------------- LCD_PAL238 -------------------------------------------
+#define LCD_PAL238_R04_0_Pos 0 /*!< LCD PAL238: R04_0 Position */
+#define LCD_PAL238_R04_0_Msk (0x1fUL << LCD_PAL238_R04_0_Pos) /*!< LCD PAL238: R04_0 Mask */
+#define LCD_PAL238_G04_0_Pos 5 /*!< LCD PAL238: G04_0 Position */
+#define LCD_PAL238_G04_0_Msk (0x1fUL << LCD_PAL238_G04_0_Pos) /*!< LCD PAL238: G04_0 Mask */
+#define LCD_PAL238_B04_0_Pos 10 /*!< LCD PAL238: B04_0 Position */
+#define LCD_PAL238_B04_0_Msk (0x1fUL << LCD_PAL238_B04_0_Pos) /*!< LCD PAL238: B04_0 Mask */
+#define LCD_PAL238_I0_Pos 15 /*!< LCD PAL238: I0 Position */
+#define LCD_PAL238_I0_Msk (0x01UL << LCD_PAL238_I0_Pos) /*!< LCD PAL238: I0 Mask */
+#define LCD_PAL238_R14_0_Pos 16 /*!< LCD PAL238: R14_0 Position */
+#define LCD_PAL238_R14_0_Msk (0x1fUL << LCD_PAL238_R14_0_Pos) /*!< LCD PAL238: R14_0 Mask */
+#define LCD_PAL238_G14_0_Pos 21 /*!< LCD PAL238: G14_0 Position */
+#define LCD_PAL238_G14_0_Msk (0x1fUL << LCD_PAL238_G14_0_Pos) /*!< LCD PAL238: G14_0 Mask */
+#define LCD_PAL238_B14_0_Pos 26 /*!< LCD PAL238: B14_0 Position */
+#define LCD_PAL238_B14_0_Msk (0x1fUL << LCD_PAL238_B14_0_Pos) /*!< LCD PAL238: B14_0 Mask */
+#define LCD_PAL238_I1_Pos 31 /*!< LCD PAL238: I1 Position */
+#define LCD_PAL238_I1_Msk (0x01UL << LCD_PAL238_I1_Pos) /*!< LCD PAL238: I1 Mask */
+
+// --------------------------------------- LCD_PAL239 -------------------------------------------
+#define LCD_PAL239_R04_0_Pos 0 /*!< LCD PAL239: R04_0 Position */
+#define LCD_PAL239_R04_0_Msk (0x1fUL << LCD_PAL239_R04_0_Pos) /*!< LCD PAL239: R04_0 Mask */
+#define LCD_PAL239_G04_0_Pos 5 /*!< LCD PAL239: G04_0 Position */
+#define LCD_PAL239_G04_0_Msk (0x1fUL << LCD_PAL239_G04_0_Pos) /*!< LCD PAL239: G04_0 Mask */
+#define LCD_PAL239_B04_0_Pos 10 /*!< LCD PAL239: B04_0 Position */
+#define LCD_PAL239_B04_0_Msk (0x1fUL << LCD_PAL239_B04_0_Pos) /*!< LCD PAL239: B04_0 Mask */
+#define LCD_PAL239_I0_Pos 15 /*!< LCD PAL239: I0 Position */
+#define LCD_PAL239_I0_Msk (0x01UL << LCD_PAL239_I0_Pos) /*!< LCD PAL239: I0 Mask */
+#define LCD_PAL239_R14_0_Pos 16 /*!< LCD PAL239: R14_0 Position */
+#define LCD_PAL239_R14_0_Msk (0x1fUL << LCD_PAL239_R14_0_Pos) /*!< LCD PAL239: R14_0 Mask */
+#define LCD_PAL239_G14_0_Pos 21 /*!< LCD PAL239: G14_0 Position */
+#define LCD_PAL239_G14_0_Msk (0x1fUL << LCD_PAL239_G14_0_Pos) /*!< LCD PAL239: G14_0 Mask */
+#define LCD_PAL239_B14_0_Pos 26 /*!< LCD PAL239: B14_0 Position */
+#define LCD_PAL239_B14_0_Msk (0x1fUL << LCD_PAL239_B14_0_Pos) /*!< LCD PAL239: B14_0 Mask */
+#define LCD_PAL239_I1_Pos 31 /*!< LCD PAL239: I1 Position */
+#define LCD_PAL239_I1_Msk (0x01UL << LCD_PAL239_I1_Pos) /*!< LCD PAL239: I1 Mask */
+
+// --------------------------------------- LCD_PAL240 -------------------------------------------
+#define LCD_PAL240_R04_0_Pos 0 /*!< LCD PAL240: R04_0 Position */
+#define LCD_PAL240_R04_0_Msk (0x1fUL << LCD_PAL240_R04_0_Pos) /*!< LCD PAL240: R04_0 Mask */
+#define LCD_PAL240_G04_0_Pos 5 /*!< LCD PAL240: G04_0 Position */
+#define LCD_PAL240_G04_0_Msk (0x1fUL << LCD_PAL240_G04_0_Pos) /*!< LCD PAL240: G04_0 Mask */
+#define LCD_PAL240_B04_0_Pos 10 /*!< LCD PAL240: B04_0 Position */
+#define LCD_PAL240_B04_0_Msk (0x1fUL << LCD_PAL240_B04_0_Pos) /*!< LCD PAL240: B04_0 Mask */
+#define LCD_PAL240_I0_Pos 15 /*!< LCD PAL240: I0 Position */
+#define LCD_PAL240_I0_Msk (0x01UL << LCD_PAL240_I0_Pos) /*!< LCD PAL240: I0 Mask */
+#define LCD_PAL240_R14_0_Pos 16 /*!< LCD PAL240: R14_0 Position */
+#define LCD_PAL240_R14_0_Msk (0x1fUL << LCD_PAL240_R14_0_Pos) /*!< LCD PAL240: R14_0 Mask */
+#define LCD_PAL240_G14_0_Pos 21 /*!< LCD PAL240: G14_0 Position */
+#define LCD_PAL240_G14_0_Msk (0x1fUL << LCD_PAL240_G14_0_Pos) /*!< LCD PAL240: G14_0 Mask */
+#define LCD_PAL240_B14_0_Pos 26 /*!< LCD PAL240: B14_0 Position */
+#define LCD_PAL240_B14_0_Msk (0x1fUL << LCD_PAL240_B14_0_Pos) /*!< LCD PAL240: B14_0 Mask */
+#define LCD_PAL240_I1_Pos 31 /*!< LCD PAL240: I1 Position */
+#define LCD_PAL240_I1_Msk (0x01UL << LCD_PAL240_I1_Pos) /*!< LCD PAL240: I1 Mask */
+
+// --------------------------------------- LCD_PAL241 -------------------------------------------
+#define LCD_PAL241_R04_0_Pos 0 /*!< LCD PAL241: R04_0 Position */
+#define LCD_PAL241_R04_0_Msk (0x1fUL << LCD_PAL241_R04_0_Pos) /*!< LCD PAL241: R04_0 Mask */
+#define LCD_PAL241_G04_0_Pos 5 /*!< LCD PAL241: G04_0 Position */
+#define LCD_PAL241_G04_0_Msk (0x1fUL << LCD_PAL241_G04_0_Pos) /*!< LCD PAL241: G04_0 Mask */
+#define LCD_PAL241_B04_0_Pos 10 /*!< LCD PAL241: B04_0 Position */
+#define LCD_PAL241_B04_0_Msk (0x1fUL << LCD_PAL241_B04_0_Pos) /*!< LCD PAL241: B04_0 Mask */
+#define LCD_PAL241_I0_Pos 15 /*!< LCD PAL241: I0 Position */
+#define LCD_PAL241_I0_Msk (0x01UL << LCD_PAL241_I0_Pos) /*!< LCD PAL241: I0 Mask */
+#define LCD_PAL241_R14_0_Pos 16 /*!< LCD PAL241: R14_0 Position */
+#define LCD_PAL241_R14_0_Msk (0x1fUL << LCD_PAL241_R14_0_Pos) /*!< LCD PAL241: R14_0 Mask */
+#define LCD_PAL241_G14_0_Pos 21 /*!< LCD PAL241: G14_0 Position */
+#define LCD_PAL241_G14_0_Msk (0x1fUL << LCD_PAL241_G14_0_Pos) /*!< LCD PAL241: G14_0 Mask */
+#define LCD_PAL241_B14_0_Pos 26 /*!< LCD PAL241: B14_0 Position */
+#define LCD_PAL241_B14_0_Msk (0x1fUL << LCD_PAL241_B14_0_Pos) /*!< LCD PAL241: B14_0 Mask */
+#define LCD_PAL241_I1_Pos 31 /*!< LCD PAL241: I1 Position */
+#define LCD_PAL241_I1_Msk (0x01UL << LCD_PAL241_I1_Pos) /*!< LCD PAL241: I1 Mask */
+
+// --------------------------------------- LCD_PAL242 -------------------------------------------
+#define LCD_PAL242_R04_0_Pos 0 /*!< LCD PAL242: R04_0 Position */
+#define LCD_PAL242_R04_0_Msk (0x1fUL << LCD_PAL242_R04_0_Pos) /*!< LCD PAL242: R04_0 Mask */
+#define LCD_PAL242_G04_0_Pos 5 /*!< LCD PAL242: G04_0 Position */
+#define LCD_PAL242_G04_0_Msk (0x1fUL << LCD_PAL242_G04_0_Pos) /*!< LCD PAL242: G04_0 Mask */
+#define LCD_PAL242_B04_0_Pos 10 /*!< LCD PAL242: B04_0 Position */
+#define LCD_PAL242_B04_0_Msk (0x1fUL << LCD_PAL242_B04_0_Pos) /*!< LCD PAL242: B04_0 Mask */
+#define LCD_PAL242_I0_Pos 15 /*!< LCD PAL242: I0 Position */
+#define LCD_PAL242_I0_Msk (0x01UL << LCD_PAL242_I0_Pos) /*!< LCD PAL242: I0 Mask */
+#define LCD_PAL242_R14_0_Pos 16 /*!< LCD PAL242: R14_0 Position */
+#define LCD_PAL242_R14_0_Msk (0x1fUL << LCD_PAL242_R14_0_Pos) /*!< LCD PAL242: R14_0 Mask */
+#define LCD_PAL242_G14_0_Pos 21 /*!< LCD PAL242: G14_0 Position */
+#define LCD_PAL242_G14_0_Msk (0x1fUL << LCD_PAL242_G14_0_Pos) /*!< LCD PAL242: G14_0 Mask */
+#define LCD_PAL242_B14_0_Pos 26 /*!< LCD PAL242: B14_0 Position */
+#define LCD_PAL242_B14_0_Msk (0x1fUL << LCD_PAL242_B14_0_Pos) /*!< LCD PAL242: B14_0 Mask */
+#define LCD_PAL242_I1_Pos 31 /*!< LCD PAL242: I1 Position */
+#define LCD_PAL242_I1_Msk (0x01UL << LCD_PAL242_I1_Pos) /*!< LCD PAL242: I1 Mask */
+
+// --------------------------------------- LCD_PAL243 -------------------------------------------
+#define LCD_PAL243_R04_0_Pos 0 /*!< LCD PAL243: R04_0 Position */
+#define LCD_PAL243_R04_0_Msk (0x1fUL << LCD_PAL243_R04_0_Pos) /*!< LCD PAL243: R04_0 Mask */
+#define LCD_PAL243_G04_0_Pos 5 /*!< LCD PAL243: G04_0 Position */
+#define LCD_PAL243_G04_0_Msk (0x1fUL << LCD_PAL243_G04_0_Pos) /*!< LCD PAL243: G04_0 Mask */
+#define LCD_PAL243_B04_0_Pos 10 /*!< LCD PAL243: B04_0 Position */
+#define LCD_PAL243_B04_0_Msk (0x1fUL << LCD_PAL243_B04_0_Pos) /*!< LCD PAL243: B04_0 Mask */
+#define LCD_PAL243_I0_Pos 15 /*!< LCD PAL243: I0 Position */
+#define LCD_PAL243_I0_Msk (0x01UL << LCD_PAL243_I0_Pos) /*!< LCD PAL243: I0 Mask */
+#define LCD_PAL243_R14_0_Pos 16 /*!< LCD PAL243: R14_0 Position */
+#define LCD_PAL243_R14_0_Msk (0x1fUL << LCD_PAL243_R14_0_Pos) /*!< LCD PAL243: R14_0 Mask */
+#define LCD_PAL243_G14_0_Pos 21 /*!< LCD PAL243: G14_0 Position */
+#define LCD_PAL243_G14_0_Msk (0x1fUL << LCD_PAL243_G14_0_Pos) /*!< LCD PAL243: G14_0 Mask */
+#define LCD_PAL243_B14_0_Pos 26 /*!< LCD PAL243: B14_0 Position */
+#define LCD_PAL243_B14_0_Msk (0x1fUL << LCD_PAL243_B14_0_Pos) /*!< LCD PAL243: B14_0 Mask */
+#define LCD_PAL243_I1_Pos 31 /*!< LCD PAL243: I1 Position */
+#define LCD_PAL243_I1_Msk (0x01UL << LCD_PAL243_I1_Pos) /*!< LCD PAL243: I1 Mask */
+
+// --------------------------------------- LCD_PAL244 -------------------------------------------
+#define LCD_PAL244_R04_0_Pos 0 /*!< LCD PAL244: R04_0 Position */
+#define LCD_PAL244_R04_0_Msk (0x1fUL << LCD_PAL244_R04_0_Pos) /*!< LCD PAL244: R04_0 Mask */
+#define LCD_PAL244_G04_0_Pos 5 /*!< LCD PAL244: G04_0 Position */
+#define LCD_PAL244_G04_0_Msk (0x1fUL << LCD_PAL244_G04_0_Pos) /*!< LCD PAL244: G04_0 Mask */
+#define LCD_PAL244_B04_0_Pos 10 /*!< LCD PAL244: B04_0 Position */
+#define LCD_PAL244_B04_0_Msk (0x1fUL << LCD_PAL244_B04_0_Pos) /*!< LCD PAL244: B04_0 Mask */
+#define LCD_PAL244_I0_Pos 15 /*!< LCD PAL244: I0 Position */
+#define LCD_PAL244_I0_Msk (0x01UL << LCD_PAL244_I0_Pos) /*!< LCD PAL244: I0 Mask */
+#define LCD_PAL244_R14_0_Pos 16 /*!< LCD PAL244: R14_0 Position */
+#define LCD_PAL244_R14_0_Msk (0x1fUL << LCD_PAL244_R14_0_Pos) /*!< LCD PAL244: R14_0 Mask */
+#define LCD_PAL244_G14_0_Pos 21 /*!< LCD PAL244: G14_0 Position */
+#define LCD_PAL244_G14_0_Msk (0x1fUL << LCD_PAL244_G14_0_Pos) /*!< LCD PAL244: G14_0 Mask */
+#define LCD_PAL244_B14_0_Pos 26 /*!< LCD PAL244: B14_0 Position */
+#define LCD_PAL244_B14_0_Msk (0x1fUL << LCD_PAL244_B14_0_Pos) /*!< LCD PAL244: B14_0 Mask */
+#define LCD_PAL244_I1_Pos 31 /*!< LCD PAL244: I1 Position */
+#define LCD_PAL244_I1_Msk (0x01UL << LCD_PAL244_I1_Pos) /*!< LCD PAL244: I1 Mask */
+
+// --------------------------------------- LCD_PAL245 -------------------------------------------
+#define LCD_PAL245_R04_0_Pos 0 /*!< LCD PAL245: R04_0 Position */
+#define LCD_PAL245_R04_0_Msk (0x1fUL << LCD_PAL245_R04_0_Pos) /*!< LCD PAL245: R04_0 Mask */
+#define LCD_PAL245_G04_0_Pos 5 /*!< LCD PAL245: G04_0 Position */
+#define LCD_PAL245_G04_0_Msk (0x1fUL << LCD_PAL245_G04_0_Pos) /*!< LCD PAL245: G04_0 Mask */
+#define LCD_PAL245_B04_0_Pos 10 /*!< LCD PAL245: B04_0 Position */
+#define LCD_PAL245_B04_0_Msk (0x1fUL << LCD_PAL245_B04_0_Pos) /*!< LCD PAL245: B04_0 Mask */
+#define LCD_PAL245_I0_Pos 15 /*!< LCD PAL245: I0 Position */
+#define LCD_PAL245_I0_Msk (0x01UL << LCD_PAL245_I0_Pos) /*!< LCD PAL245: I0 Mask */
+#define LCD_PAL245_R14_0_Pos 16 /*!< LCD PAL245: R14_0 Position */
+#define LCD_PAL245_R14_0_Msk (0x1fUL << LCD_PAL245_R14_0_Pos) /*!< LCD PAL245: R14_0 Mask */
+#define LCD_PAL245_G14_0_Pos 21 /*!< LCD PAL245: G14_0 Position */
+#define LCD_PAL245_G14_0_Msk (0x1fUL << LCD_PAL245_G14_0_Pos) /*!< LCD PAL245: G14_0 Mask */
+#define LCD_PAL245_B14_0_Pos 26 /*!< LCD PAL245: B14_0 Position */
+#define LCD_PAL245_B14_0_Msk (0x1fUL << LCD_PAL245_B14_0_Pos) /*!< LCD PAL245: B14_0 Mask */
+#define LCD_PAL245_I1_Pos 31 /*!< LCD PAL245: I1 Position */
+#define LCD_PAL245_I1_Msk (0x01UL << LCD_PAL245_I1_Pos) /*!< LCD PAL245: I1 Mask */
+
+// --------------------------------------- LCD_PAL246 -------------------------------------------
+#define LCD_PAL246_R04_0_Pos 0 /*!< LCD PAL246: R04_0 Position */
+#define LCD_PAL246_R04_0_Msk (0x1fUL << LCD_PAL246_R04_0_Pos) /*!< LCD PAL246: R04_0 Mask */
+#define LCD_PAL246_G04_0_Pos 5 /*!< LCD PAL246: G04_0 Position */
+#define LCD_PAL246_G04_0_Msk (0x1fUL << LCD_PAL246_G04_0_Pos) /*!< LCD PAL246: G04_0 Mask */
+#define LCD_PAL246_B04_0_Pos 10 /*!< LCD PAL246: B04_0 Position */
+#define LCD_PAL246_B04_0_Msk (0x1fUL << LCD_PAL246_B04_0_Pos) /*!< LCD PAL246: B04_0 Mask */
+#define LCD_PAL246_I0_Pos 15 /*!< LCD PAL246: I0 Position */
+#define LCD_PAL246_I0_Msk (0x01UL << LCD_PAL246_I0_Pos) /*!< LCD PAL246: I0 Mask */
+#define LCD_PAL246_R14_0_Pos 16 /*!< LCD PAL246: R14_0 Position */
+#define LCD_PAL246_R14_0_Msk (0x1fUL << LCD_PAL246_R14_0_Pos) /*!< LCD PAL246: R14_0 Mask */
+#define LCD_PAL246_G14_0_Pos 21 /*!< LCD PAL246: G14_0 Position */
+#define LCD_PAL246_G14_0_Msk (0x1fUL << LCD_PAL246_G14_0_Pos) /*!< LCD PAL246: G14_0 Mask */
+#define LCD_PAL246_B14_0_Pos 26 /*!< LCD PAL246: B14_0 Position */
+#define LCD_PAL246_B14_0_Msk (0x1fUL << LCD_PAL246_B14_0_Pos) /*!< LCD PAL246: B14_0 Mask */
+#define LCD_PAL246_I1_Pos 31 /*!< LCD PAL246: I1 Position */
+#define LCD_PAL246_I1_Msk (0x01UL << LCD_PAL246_I1_Pos) /*!< LCD PAL246: I1 Mask */
+
+// --------------------------------------- LCD_PAL247 -------------------------------------------
+#define LCD_PAL247_R04_0_Pos 0 /*!< LCD PAL247: R04_0 Position */
+#define LCD_PAL247_R04_0_Msk (0x1fUL << LCD_PAL247_R04_0_Pos) /*!< LCD PAL247: R04_0 Mask */
+#define LCD_PAL247_G04_0_Pos 5 /*!< LCD PAL247: G04_0 Position */
+#define LCD_PAL247_G04_0_Msk (0x1fUL << LCD_PAL247_G04_0_Pos) /*!< LCD PAL247: G04_0 Mask */
+#define LCD_PAL247_B04_0_Pos 10 /*!< LCD PAL247: B04_0 Position */
+#define LCD_PAL247_B04_0_Msk (0x1fUL << LCD_PAL247_B04_0_Pos) /*!< LCD PAL247: B04_0 Mask */
+#define LCD_PAL247_I0_Pos 15 /*!< LCD PAL247: I0 Position */
+#define LCD_PAL247_I0_Msk (0x01UL << LCD_PAL247_I0_Pos) /*!< LCD PAL247: I0 Mask */
+#define LCD_PAL247_R14_0_Pos 16 /*!< LCD PAL247: R14_0 Position */
+#define LCD_PAL247_R14_0_Msk (0x1fUL << LCD_PAL247_R14_0_Pos) /*!< LCD PAL247: R14_0 Mask */
+#define LCD_PAL247_G14_0_Pos 21 /*!< LCD PAL247: G14_0 Position */
+#define LCD_PAL247_G14_0_Msk (0x1fUL << LCD_PAL247_G14_0_Pos) /*!< LCD PAL247: G14_0 Mask */
+#define LCD_PAL247_B14_0_Pos 26 /*!< LCD PAL247: B14_0 Position */
+#define LCD_PAL247_B14_0_Msk (0x1fUL << LCD_PAL247_B14_0_Pos) /*!< LCD PAL247: B14_0 Mask */
+#define LCD_PAL247_I1_Pos 31 /*!< LCD PAL247: I1 Position */
+#define LCD_PAL247_I1_Msk (0x01UL << LCD_PAL247_I1_Pos) /*!< LCD PAL247: I1 Mask */
+
+// --------------------------------------- LCD_PAL248 -------------------------------------------
+#define LCD_PAL248_R04_0_Pos 0 /*!< LCD PAL248: R04_0 Position */
+#define LCD_PAL248_R04_0_Msk (0x1fUL << LCD_PAL248_R04_0_Pos) /*!< LCD PAL248: R04_0 Mask */
+#define LCD_PAL248_G04_0_Pos 5 /*!< LCD PAL248: G04_0 Position */
+#define LCD_PAL248_G04_0_Msk (0x1fUL << LCD_PAL248_G04_0_Pos) /*!< LCD PAL248: G04_0 Mask */
+#define LCD_PAL248_B04_0_Pos 10 /*!< LCD PAL248: B04_0 Position */
+#define LCD_PAL248_B04_0_Msk (0x1fUL << LCD_PAL248_B04_0_Pos) /*!< LCD PAL248: B04_0 Mask */
+#define LCD_PAL248_I0_Pos 15 /*!< LCD PAL248: I0 Position */
+#define LCD_PAL248_I0_Msk (0x01UL << LCD_PAL248_I0_Pos) /*!< LCD PAL248: I0 Mask */
+#define LCD_PAL248_R14_0_Pos 16 /*!< LCD PAL248: R14_0 Position */
+#define LCD_PAL248_R14_0_Msk (0x1fUL << LCD_PAL248_R14_0_Pos) /*!< LCD PAL248: R14_0 Mask */
+#define LCD_PAL248_G14_0_Pos 21 /*!< LCD PAL248: G14_0 Position */
+#define LCD_PAL248_G14_0_Msk (0x1fUL << LCD_PAL248_G14_0_Pos) /*!< LCD PAL248: G14_0 Mask */
+#define LCD_PAL248_B14_0_Pos 26 /*!< LCD PAL248: B14_0 Position */
+#define LCD_PAL248_B14_0_Msk (0x1fUL << LCD_PAL248_B14_0_Pos) /*!< LCD PAL248: B14_0 Mask */
+#define LCD_PAL248_I1_Pos 31 /*!< LCD PAL248: I1 Position */
+#define LCD_PAL248_I1_Msk (0x01UL << LCD_PAL248_I1_Pos) /*!< LCD PAL248: I1 Mask */
+
+// --------------------------------------- LCD_PAL249 -------------------------------------------
+#define LCD_PAL249_R04_0_Pos 0 /*!< LCD PAL249: R04_0 Position */
+#define LCD_PAL249_R04_0_Msk (0x1fUL << LCD_PAL249_R04_0_Pos) /*!< LCD PAL249: R04_0 Mask */
+#define LCD_PAL249_G04_0_Pos 5 /*!< LCD PAL249: G04_0 Position */
+#define LCD_PAL249_G04_0_Msk (0x1fUL << LCD_PAL249_G04_0_Pos) /*!< LCD PAL249: G04_0 Mask */
+#define LCD_PAL249_B04_0_Pos 10 /*!< LCD PAL249: B04_0 Position */
+#define LCD_PAL249_B04_0_Msk (0x1fUL << LCD_PAL249_B04_0_Pos) /*!< LCD PAL249: B04_0 Mask */
+#define LCD_PAL249_I0_Pos 15 /*!< LCD PAL249: I0 Position */
+#define LCD_PAL249_I0_Msk (0x01UL << LCD_PAL249_I0_Pos) /*!< LCD PAL249: I0 Mask */
+#define LCD_PAL249_R14_0_Pos 16 /*!< LCD PAL249: R14_0 Position */
+#define LCD_PAL249_R14_0_Msk (0x1fUL << LCD_PAL249_R14_0_Pos) /*!< LCD PAL249: R14_0 Mask */
+#define LCD_PAL249_G14_0_Pos 21 /*!< LCD PAL249: G14_0 Position */
+#define LCD_PAL249_G14_0_Msk (0x1fUL << LCD_PAL249_G14_0_Pos) /*!< LCD PAL249: G14_0 Mask */
+#define LCD_PAL249_B14_0_Pos 26 /*!< LCD PAL249: B14_0 Position */
+#define LCD_PAL249_B14_0_Msk (0x1fUL << LCD_PAL249_B14_0_Pos) /*!< LCD PAL249: B14_0 Mask */
+#define LCD_PAL249_I1_Pos 31 /*!< LCD PAL249: I1 Position */
+#define LCD_PAL249_I1_Msk (0x01UL << LCD_PAL249_I1_Pos) /*!< LCD PAL249: I1 Mask */
+
+// --------------------------------------- LCD_PAL250 -------------------------------------------
+#define LCD_PAL250_R04_0_Pos 0 /*!< LCD PAL250: R04_0 Position */
+#define LCD_PAL250_R04_0_Msk (0x1fUL << LCD_PAL250_R04_0_Pos) /*!< LCD PAL250: R04_0 Mask */
+#define LCD_PAL250_G04_0_Pos 5 /*!< LCD PAL250: G04_0 Position */
+#define LCD_PAL250_G04_0_Msk (0x1fUL << LCD_PAL250_G04_0_Pos) /*!< LCD PAL250: G04_0 Mask */
+#define LCD_PAL250_B04_0_Pos 10 /*!< LCD PAL250: B04_0 Position */
+#define LCD_PAL250_B04_0_Msk (0x1fUL << LCD_PAL250_B04_0_Pos) /*!< LCD PAL250: B04_0 Mask */
+#define LCD_PAL250_I0_Pos 15 /*!< LCD PAL250: I0 Position */
+#define LCD_PAL250_I0_Msk (0x01UL << LCD_PAL250_I0_Pos) /*!< LCD PAL250: I0 Mask */
+#define LCD_PAL250_R14_0_Pos 16 /*!< LCD PAL250: R14_0 Position */
+#define LCD_PAL250_R14_0_Msk (0x1fUL << LCD_PAL250_R14_0_Pos) /*!< LCD PAL250: R14_0 Mask */
+#define LCD_PAL250_G14_0_Pos 21 /*!< LCD PAL250: G14_0 Position */
+#define LCD_PAL250_G14_0_Msk (0x1fUL << LCD_PAL250_G14_0_Pos) /*!< LCD PAL250: G14_0 Mask */
+#define LCD_PAL250_B14_0_Pos 26 /*!< LCD PAL250: B14_0 Position */
+#define LCD_PAL250_B14_0_Msk (0x1fUL << LCD_PAL250_B14_0_Pos) /*!< LCD PAL250: B14_0 Mask */
+#define LCD_PAL250_I1_Pos 31 /*!< LCD PAL250: I1 Position */
+#define LCD_PAL250_I1_Msk (0x01UL << LCD_PAL250_I1_Pos) /*!< LCD PAL250: I1 Mask */
+
+// --------------------------------------- LCD_PAL251 -------------------------------------------
+#define LCD_PAL251_R04_0_Pos 0 /*!< LCD PAL251: R04_0 Position */
+#define LCD_PAL251_R04_0_Msk (0x1fUL << LCD_PAL251_R04_0_Pos) /*!< LCD PAL251: R04_0 Mask */
+#define LCD_PAL251_G04_0_Pos 5 /*!< LCD PAL251: G04_0 Position */
+#define LCD_PAL251_G04_0_Msk (0x1fUL << LCD_PAL251_G04_0_Pos) /*!< LCD PAL251: G04_0 Mask */
+#define LCD_PAL251_B04_0_Pos 10 /*!< LCD PAL251: B04_0 Position */
+#define LCD_PAL251_B04_0_Msk (0x1fUL << LCD_PAL251_B04_0_Pos) /*!< LCD PAL251: B04_0 Mask */
+#define LCD_PAL251_I0_Pos 15 /*!< LCD PAL251: I0 Position */
+#define LCD_PAL251_I0_Msk (0x01UL << LCD_PAL251_I0_Pos) /*!< LCD PAL251: I0 Mask */
+#define LCD_PAL251_R14_0_Pos 16 /*!< LCD PAL251: R14_0 Position */
+#define LCD_PAL251_R14_0_Msk (0x1fUL << LCD_PAL251_R14_0_Pos) /*!< LCD PAL251: R14_0 Mask */
+#define LCD_PAL251_G14_0_Pos 21 /*!< LCD PAL251: G14_0 Position */
+#define LCD_PAL251_G14_0_Msk (0x1fUL << LCD_PAL251_G14_0_Pos) /*!< LCD PAL251: G14_0 Mask */
+#define LCD_PAL251_B14_0_Pos 26 /*!< LCD PAL251: B14_0 Position */
+#define LCD_PAL251_B14_0_Msk (0x1fUL << LCD_PAL251_B14_0_Pos) /*!< LCD PAL251: B14_0 Mask */
+#define LCD_PAL251_I1_Pos 31 /*!< LCD PAL251: I1 Position */
+#define LCD_PAL251_I1_Msk (0x01UL << LCD_PAL251_I1_Pos) /*!< LCD PAL251: I1 Mask */
+
+// --------------------------------------- LCD_PAL252 -------------------------------------------
+#define LCD_PAL252_R04_0_Pos 0 /*!< LCD PAL252: R04_0 Position */
+#define LCD_PAL252_R04_0_Msk (0x1fUL << LCD_PAL252_R04_0_Pos) /*!< LCD PAL252: R04_0 Mask */
+#define LCD_PAL252_G04_0_Pos 5 /*!< LCD PAL252: G04_0 Position */
+#define LCD_PAL252_G04_0_Msk (0x1fUL << LCD_PAL252_G04_0_Pos) /*!< LCD PAL252: G04_0 Mask */
+#define LCD_PAL252_B04_0_Pos 10 /*!< LCD PAL252: B04_0 Position */
+#define LCD_PAL252_B04_0_Msk (0x1fUL << LCD_PAL252_B04_0_Pos) /*!< LCD PAL252: B04_0 Mask */
+#define LCD_PAL252_I0_Pos 15 /*!< LCD PAL252: I0 Position */
+#define LCD_PAL252_I0_Msk (0x01UL << LCD_PAL252_I0_Pos) /*!< LCD PAL252: I0 Mask */
+#define LCD_PAL252_R14_0_Pos 16 /*!< LCD PAL252: R14_0 Position */
+#define LCD_PAL252_R14_0_Msk (0x1fUL << LCD_PAL252_R14_0_Pos) /*!< LCD PAL252: R14_0 Mask */
+#define LCD_PAL252_G14_0_Pos 21 /*!< LCD PAL252: G14_0 Position */
+#define LCD_PAL252_G14_0_Msk (0x1fUL << LCD_PAL252_G14_0_Pos) /*!< LCD PAL252: G14_0 Mask */
+#define LCD_PAL252_B14_0_Pos 26 /*!< LCD PAL252: B14_0 Position */
+#define LCD_PAL252_B14_0_Msk (0x1fUL << LCD_PAL252_B14_0_Pos) /*!< LCD PAL252: B14_0 Mask */
+#define LCD_PAL252_I1_Pos 31 /*!< LCD PAL252: I1 Position */
+#define LCD_PAL252_I1_Msk (0x01UL << LCD_PAL252_I1_Pos) /*!< LCD PAL252: I1 Mask */
+
+// --------------------------------------- LCD_PAL253 -------------------------------------------
+#define LCD_PAL253_R04_0_Pos 0 /*!< LCD PAL253: R04_0 Position */
+#define LCD_PAL253_R04_0_Msk (0x1fUL << LCD_PAL253_R04_0_Pos) /*!< LCD PAL253: R04_0 Mask */
+#define LCD_PAL253_G04_0_Pos 5 /*!< LCD PAL253: G04_0 Position */
+#define LCD_PAL253_G04_0_Msk (0x1fUL << LCD_PAL253_G04_0_Pos) /*!< LCD PAL253: G04_0 Mask */
+#define LCD_PAL253_B04_0_Pos 10 /*!< LCD PAL253: B04_0 Position */
+#define LCD_PAL253_B04_0_Msk (0x1fUL << LCD_PAL253_B04_0_Pos) /*!< LCD PAL253: B04_0 Mask */
+#define LCD_PAL253_I0_Pos 15 /*!< LCD PAL253: I0 Position */
+#define LCD_PAL253_I0_Msk (0x01UL << LCD_PAL253_I0_Pos) /*!< LCD PAL253: I0 Mask */
+#define LCD_PAL253_R14_0_Pos 16 /*!< LCD PAL253: R14_0 Position */
+#define LCD_PAL253_R14_0_Msk (0x1fUL << LCD_PAL253_R14_0_Pos) /*!< LCD PAL253: R14_0 Mask */
+#define LCD_PAL253_G14_0_Pos 21 /*!< LCD PAL253: G14_0 Position */
+#define LCD_PAL253_G14_0_Msk (0x1fUL << LCD_PAL253_G14_0_Pos) /*!< LCD PAL253: G14_0 Mask */
+#define LCD_PAL253_B14_0_Pos 26 /*!< LCD PAL253: B14_0 Position */
+#define LCD_PAL253_B14_0_Msk (0x1fUL << LCD_PAL253_B14_0_Pos) /*!< LCD PAL253: B14_0 Mask */
+#define LCD_PAL253_I1_Pos 31 /*!< LCD PAL253: I1 Position */
+#define LCD_PAL253_I1_Msk (0x01UL << LCD_PAL253_I1_Pos) /*!< LCD PAL253: I1 Mask */
+
+// --------------------------------------- LCD_PAL254 -------------------------------------------
+#define LCD_PAL254_R04_0_Pos 0 /*!< LCD PAL254: R04_0 Position */
+#define LCD_PAL254_R04_0_Msk (0x1fUL << LCD_PAL254_R04_0_Pos) /*!< LCD PAL254: R04_0 Mask */
+#define LCD_PAL254_G04_0_Pos 5 /*!< LCD PAL254: G04_0 Position */
+#define LCD_PAL254_G04_0_Msk (0x1fUL << LCD_PAL254_G04_0_Pos) /*!< LCD PAL254: G04_0 Mask */
+#define LCD_PAL254_B04_0_Pos 10 /*!< LCD PAL254: B04_0 Position */
+#define LCD_PAL254_B04_0_Msk (0x1fUL << LCD_PAL254_B04_0_Pos) /*!< LCD PAL254: B04_0 Mask */
+#define LCD_PAL254_I0_Pos 15 /*!< LCD PAL254: I0 Position */
+#define LCD_PAL254_I0_Msk (0x01UL << LCD_PAL254_I0_Pos) /*!< LCD PAL254: I0 Mask */
+#define LCD_PAL254_R14_0_Pos 16 /*!< LCD PAL254: R14_0 Position */
+#define LCD_PAL254_R14_0_Msk (0x1fUL << LCD_PAL254_R14_0_Pos) /*!< LCD PAL254: R14_0 Mask */
+#define LCD_PAL254_G14_0_Pos 21 /*!< LCD PAL254: G14_0 Position */
+#define LCD_PAL254_G14_0_Msk (0x1fUL << LCD_PAL254_G14_0_Pos) /*!< LCD PAL254: G14_0 Mask */
+#define LCD_PAL254_B14_0_Pos 26 /*!< LCD PAL254: B14_0 Position */
+#define LCD_PAL254_B14_0_Msk (0x1fUL << LCD_PAL254_B14_0_Pos) /*!< LCD PAL254: B14_0 Mask */
+#define LCD_PAL254_I1_Pos 31 /*!< LCD PAL254: I1 Position */
+#define LCD_PAL254_I1_Msk (0x01UL << LCD_PAL254_I1_Pos) /*!< LCD PAL254: I1 Mask */
+
+// --------------------------------------- LCD_PAL255 -------------------------------------------
+#define LCD_PAL255_R04_0_Pos 0 /*!< LCD PAL255: R04_0 Position */
+#define LCD_PAL255_R04_0_Msk (0x1fUL << LCD_PAL255_R04_0_Pos) /*!< LCD PAL255: R04_0 Mask */
+#define LCD_PAL255_G04_0_Pos 5 /*!< LCD PAL255: G04_0 Position */
+#define LCD_PAL255_G04_0_Msk (0x1fUL << LCD_PAL255_G04_0_Pos) /*!< LCD PAL255: G04_0 Mask */
+#define LCD_PAL255_B04_0_Pos 10 /*!< LCD PAL255: B04_0 Position */
+#define LCD_PAL255_B04_0_Msk (0x1fUL << LCD_PAL255_B04_0_Pos) /*!< LCD PAL255: B04_0 Mask */
+#define LCD_PAL255_I0_Pos 15 /*!< LCD PAL255: I0 Position */
+#define LCD_PAL255_I0_Msk (0x01UL << LCD_PAL255_I0_Pos) /*!< LCD PAL255: I0 Mask */
+#define LCD_PAL255_R14_0_Pos 16 /*!< LCD PAL255: R14_0 Position */
+#define LCD_PAL255_R14_0_Msk (0x1fUL << LCD_PAL255_R14_0_Pos) /*!< LCD PAL255: R14_0 Mask */
+#define LCD_PAL255_G14_0_Pos 21 /*!< LCD PAL255: G14_0 Position */
+#define LCD_PAL255_G14_0_Msk (0x1fUL << LCD_PAL255_G14_0_Pos) /*!< LCD PAL255: G14_0 Mask */
+#define LCD_PAL255_B14_0_Pos 26 /*!< LCD PAL255: B14_0 Position */
+#define LCD_PAL255_B14_0_Msk (0x1fUL << LCD_PAL255_B14_0_Pos) /*!< LCD PAL255: B14_0 Mask */
+#define LCD_PAL255_I1_Pos 31 /*!< LCD PAL255: I1 Position */
+#define LCD_PAL255_I1_Msk (0x01UL << LCD_PAL255_I1_Pos) /*!< LCD PAL255: I1 Mask */
+
+// -------------------------------------- LCD_CRSR_IMG0 -----------------------------------------
+#define LCD_CRSR_IMG0_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG0: CRSR_IMG Position */
+#define LCD_CRSR_IMG0_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG0_CRSR_IMG_Pos) /*!< LCD CRSR_IMG0: CRSR_IMG Mask */
+
+// -------------------------------------- LCD_CRSR_IMG1 -----------------------------------------
+#define LCD_CRSR_IMG1_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG1: CRSR_IMG Position */
+#define LCD_CRSR_IMG1_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG1_CRSR_IMG_Pos) /*!< LCD CRSR_IMG1: CRSR_IMG Mask */
+
+// -------------------------------------- LCD_CRSR_IMG2 -----------------------------------------
+#define LCD_CRSR_IMG2_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG2: CRSR_IMG Position */
+#define LCD_CRSR_IMG2_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG2_CRSR_IMG_Pos) /*!< LCD CRSR_IMG2: CRSR_IMG Mask */
+
+// -------------------------------------- LCD_CRSR_IMG3 -----------------------------------------
+#define LCD_CRSR_IMG3_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG3: CRSR_IMG Position */
+#define LCD_CRSR_IMG3_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG3_CRSR_IMG_Pos) /*!< LCD CRSR_IMG3: CRSR_IMG Mask */
+
+// -------------------------------------- LCD_CRSR_IMG4 -----------------------------------------
+#define LCD_CRSR_IMG4_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG4: CRSR_IMG Position */
+#define LCD_CRSR_IMG4_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG4_CRSR_IMG_Pos) /*!< LCD CRSR_IMG4: CRSR_IMG Mask */
+
+// -------------------------------------- LCD_CRSR_IMG5 -----------------------------------------
+#define LCD_CRSR_IMG5_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG5: CRSR_IMG Position */
+#define LCD_CRSR_IMG5_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG5_CRSR_IMG_Pos) /*!< LCD CRSR_IMG5: CRSR_IMG Mask */
+
+// -------------------------------------- LCD_CRSR_IMG6 -----------------------------------------
+#define LCD_CRSR_IMG6_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG6: CRSR_IMG Position */
+#define LCD_CRSR_IMG6_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG6_CRSR_IMG_Pos) /*!< LCD CRSR_IMG6: CRSR_IMG Mask */
+
+// -------------------------------------- LCD_CRSR_IMG7 -----------------------------------------
+#define LCD_CRSR_IMG7_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG7: CRSR_IMG Position */
+#define LCD_CRSR_IMG7_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG7_CRSR_IMG_Pos) /*!< LCD CRSR_IMG7: CRSR_IMG Mask */
+
+// -------------------------------------- LCD_CRSR_IMG8 -----------------------------------------
+#define LCD_CRSR_IMG8_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG8: CRSR_IMG Position */
+#define LCD_CRSR_IMG8_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG8_CRSR_IMG_Pos) /*!< LCD CRSR_IMG8: CRSR_IMG Mask */
+
+// -------------------------------------- LCD_CRSR_IMG9 -----------------------------------------
+#define LCD_CRSR_IMG9_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG9: CRSR_IMG Position */
+#define LCD_CRSR_IMG9_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG9_CRSR_IMG_Pos) /*!< LCD CRSR_IMG9: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG10 -----------------------------------------
+#define LCD_CRSR_IMG10_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG10: CRSR_IMG Position */
+#define LCD_CRSR_IMG10_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG10_CRSR_IMG_Pos) /*!< LCD CRSR_IMG10: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG11 -----------------------------------------
+#define LCD_CRSR_IMG11_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG11: CRSR_IMG Position */
+#define LCD_CRSR_IMG11_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG11_CRSR_IMG_Pos) /*!< LCD CRSR_IMG11: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG12 -----------------------------------------
+#define LCD_CRSR_IMG12_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG12: CRSR_IMG Position */
+#define LCD_CRSR_IMG12_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG12_CRSR_IMG_Pos) /*!< LCD CRSR_IMG12: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG13 -----------------------------------------
+#define LCD_CRSR_IMG13_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG13: CRSR_IMG Position */
+#define LCD_CRSR_IMG13_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG13_CRSR_IMG_Pos) /*!< LCD CRSR_IMG13: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG14 -----------------------------------------
+#define LCD_CRSR_IMG14_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG14: CRSR_IMG Position */
+#define LCD_CRSR_IMG14_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG14_CRSR_IMG_Pos) /*!< LCD CRSR_IMG14: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG15 -----------------------------------------
+#define LCD_CRSR_IMG15_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG15: CRSR_IMG Position */
+#define LCD_CRSR_IMG15_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG15_CRSR_IMG_Pos) /*!< LCD CRSR_IMG15: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG16 -----------------------------------------
+#define LCD_CRSR_IMG16_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG16: CRSR_IMG Position */
+#define LCD_CRSR_IMG16_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG16_CRSR_IMG_Pos) /*!< LCD CRSR_IMG16: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG17 -----------------------------------------
+#define LCD_CRSR_IMG17_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG17: CRSR_IMG Position */
+#define LCD_CRSR_IMG17_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG17_CRSR_IMG_Pos) /*!< LCD CRSR_IMG17: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG18 -----------------------------------------
+#define LCD_CRSR_IMG18_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG18: CRSR_IMG Position */
+#define LCD_CRSR_IMG18_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG18_CRSR_IMG_Pos) /*!< LCD CRSR_IMG18: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG19 -----------------------------------------
+#define LCD_CRSR_IMG19_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG19: CRSR_IMG Position */
+#define LCD_CRSR_IMG19_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG19_CRSR_IMG_Pos) /*!< LCD CRSR_IMG19: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG20 -----------------------------------------
+#define LCD_CRSR_IMG20_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG20: CRSR_IMG Position */
+#define LCD_CRSR_IMG20_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG20_CRSR_IMG_Pos) /*!< LCD CRSR_IMG20: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG21 -----------------------------------------
+#define LCD_CRSR_IMG21_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG21: CRSR_IMG Position */
+#define LCD_CRSR_IMG21_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG21_CRSR_IMG_Pos) /*!< LCD CRSR_IMG21: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG22 -----------------------------------------
+#define LCD_CRSR_IMG22_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG22: CRSR_IMG Position */
+#define LCD_CRSR_IMG22_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG22_CRSR_IMG_Pos) /*!< LCD CRSR_IMG22: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG23 -----------------------------------------
+#define LCD_CRSR_IMG23_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG23: CRSR_IMG Position */
+#define LCD_CRSR_IMG23_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG23_CRSR_IMG_Pos) /*!< LCD CRSR_IMG23: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG24 -----------------------------------------
+#define LCD_CRSR_IMG24_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG24: CRSR_IMG Position */
+#define LCD_CRSR_IMG24_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG24_CRSR_IMG_Pos) /*!< LCD CRSR_IMG24: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG25 -----------------------------------------
+#define LCD_CRSR_IMG25_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG25: CRSR_IMG Position */
+#define LCD_CRSR_IMG25_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG25_CRSR_IMG_Pos) /*!< LCD CRSR_IMG25: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG26 -----------------------------------------
+#define LCD_CRSR_IMG26_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG26: CRSR_IMG Position */
+#define LCD_CRSR_IMG26_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG26_CRSR_IMG_Pos) /*!< LCD CRSR_IMG26: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG27 -----------------------------------------
+#define LCD_CRSR_IMG27_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG27: CRSR_IMG Position */
+#define LCD_CRSR_IMG27_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG27_CRSR_IMG_Pos) /*!< LCD CRSR_IMG27: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG28 -----------------------------------------
+#define LCD_CRSR_IMG28_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG28: CRSR_IMG Position */
+#define LCD_CRSR_IMG28_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG28_CRSR_IMG_Pos) /*!< LCD CRSR_IMG28: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG29 -----------------------------------------
+#define LCD_CRSR_IMG29_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG29: CRSR_IMG Position */
+#define LCD_CRSR_IMG29_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG29_CRSR_IMG_Pos) /*!< LCD CRSR_IMG29: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG30 -----------------------------------------
+#define LCD_CRSR_IMG30_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG30: CRSR_IMG Position */
+#define LCD_CRSR_IMG30_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG30_CRSR_IMG_Pos) /*!< LCD CRSR_IMG30: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG31 -----------------------------------------
+#define LCD_CRSR_IMG31_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG31: CRSR_IMG Position */
+#define LCD_CRSR_IMG31_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG31_CRSR_IMG_Pos) /*!< LCD CRSR_IMG31: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG32 -----------------------------------------
+#define LCD_CRSR_IMG32_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG32: CRSR_IMG Position */
+#define LCD_CRSR_IMG32_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG32_CRSR_IMG_Pos) /*!< LCD CRSR_IMG32: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG33 -----------------------------------------
+#define LCD_CRSR_IMG33_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG33: CRSR_IMG Position */
+#define LCD_CRSR_IMG33_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG33_CRSR_IMG_Pos) /*!< LCD CRSR_IMG33: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG34 -----------------------------------------
+#define LCD_CRSR_IMG34_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG34: CRSR_IMG Position */
+#define LCD_CRSR_IMG34_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG34_CRSR_IMG_Pos) /*!< LCD CRSR_IMG34: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG35 -----------------------------------------
+#define LCD_CRSR_IMG35_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG35: CRSR_IMG Position */
+#define LCD_CRSR_IMG35_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG35_CRSR_IMG_Pos) /*!< LCD CRSR_IMG35: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG36 -----------------------------------------
+#define LCD_CRSR_IMG36_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG36: CRSR_IMG Position */
+#define LCD_CRSR_IMG36_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG36_CRSR_IMG_Pos) /*!< LCD CRSR_IMG36: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG37 -----------------------------------------
+#define LCD_CRSR_IMG37_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG37: CRSR_IMG Position */
+#define LCD_CRSR_IMG37_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG37_CRSR_IMG_Pos) /*!< LCD CRSR_IMG37: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG38 -----------------------------------------
+#define LCD_CRSR_IMG38_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG38: CRSR_IMG Position */
+#define LCD_CRSR_IMG38_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG38_CRSR_IMG_Pos) /*!< LCD CRSR_IMG38: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG39 -----------------------------------------
+#define LCD_CRSR_IMG39_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG39: CRSR_IMG Position */
+#define LCD_CRSR_IMG39_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG39_CRSR_IMG_Pos) /*!< LCD CRSR_IMG39: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG40 -----------------------------------------
+#define LCD_CRSR_IMG40_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG40: CRSR_IMG Position */
+#define LCD_CRSR_IMG40_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG40_CRSR_IMG_Pos) /*!< LCD CRSR_IMG40: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG41 -----------------------------------------
+#define LCD_CRSR_IMG41_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG41: CRSR_IMG Position */
+#define LCD_CRSR_IMG41_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG41_CRSR_IMG_Pos) /*!< LCD CRSR_IMG41: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG42 -----------------------------------------
+#define LCD_CRSR_IMG42_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG42: CRSR_IMG Position */
+#define LCD_CRSR_IMG42_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG42_CRSR_IMG_Pos) /*!< LCD CRSR_IMG42: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG43 -----------------------------------------
+#define LCD_CRSR_IMG43_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG43: CRSR_IMG Position */
+#define LCD_CRSR_IMG43_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG43_CRSR_IMG_Pos) /*!< LCD CRSR_IMG43: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG44 -----------------------------------------
+#define LCD_CRSR_IMG44_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG44: CRSR_IMG Position */
+#define LCD_CRSR_IMG44_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG44_CRSR_IMG_Pos) /*!< LCD CRSR_IMG44: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG45 -----------------------------------------
+#define LCD_CRSR_IMG45_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG45: CRSR_IMG Position */
+#define LCD_CRSR_IMG45_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG45_CRSR_IMG_Pos) /*!< LCD CRSR_IMG45: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG46 -----------------------------------------
+#define LCD_CRSR_IMG46_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG46: CRSR_IMG Position */
+#define LCD_CRSR_IMG46_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG46_CRSR_IMG_Pos) /*!< LCD CRSR_IMG46: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG47 -----------------------------------------
+#define LCD_CRSR_IMG47_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG47: CRSR_IMG Position */
+#define LCD_CRSR_IMG47_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG47_CRSR_IMG_Pos) /*!< LCD CRSR_IMG47: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG48 -----------------------------------------
+#define LCD_CRSR_IMG48_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG48: CRSR_IMG Position */
+#define LCD_CRSR_IMG48_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG48_CRSR_IMG_Pos) /*!< LCD CRSR_IMG48: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG49 -----------------------------------------
+#define LCD_CRSR_IMG49_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG49: CRSR_IMG Position */
+#define LCD_CRSR_IMG49_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG49_CRSR_IMG_Pos) /*!< LCD CRSR_IMG49: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG50 -----------------------------------------
+#define LCD_CRSR_IMG50_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG50: CRSR_IMG Position */
+#define LCD_CRSR_IMG50_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG50_CRSR_IMG_Pos) /*!< LCD CRSR_IMG50: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG51 -----------------------------------------
+#define LCD_CRSR_IMG51_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG51: CRSR_IMG Position */
+#define LCD_CRSR_IMG51_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG51_CRSR_IMG_Pos) /*!< LCD CRSR_IMG51: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG52 -----------------------------------------
+#define LCD_CRSR_IMG52_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG52: CRSR_IMG Position */
+#define LCD_CRSR_IMG52_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG52_CRSR_IMG_Pos) /*!< LCD CRSR_IMG52: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG53 -----------------------------------------
+#define LCD_CRSR_IMG53_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG53: CRSR_IMG Position */
+#define LCD_CRSR_IMG53_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG53_CRSR_IMG_Pos) /*!< LCD CRSR_IMG53: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG54 -----------------------------------------
+#define LCD_CRSR_IMG54_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG54: CRSR_IMG Position */
+#define LCD_CRSR_IMG54_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG54_CRSR_IMG_Pos) /*!< LCD CRSR_IMG54: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG55 -----------------------------------------
+#define LCD_CRSR_IMG55_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG55: CRSR_IMG Position */
+#define LCD_CRSR_IMG55_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG55_CRSR_IMG_Pos) /*!< LCD CRSR_IMG55: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG56 -----------------------------------------
+#define LCD_CRSR_IMG56_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG56: CRSR_IMG Position */
+#define LCD_CRSR_IMG56_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG56_CRSR_IMG_Pos) /*!< LCD CRSR_IMG56: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG57 -----------------------------------------
+#define LCD_CRSR_IMG57_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG57: CRSR_IMG Position */
+#define LCD_CRSR_IMG57_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG57_CRSR_IMG_Pos) /*!< LCD CRSR_IMG57: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG58 -----------------------------------------
+#define LCD_CRSR_IMG58_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG58: CRSR_IMG Position */
+#define LCD_CRSR_IMG58_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG58_CRSR_IMG_Pos) /*!< LCD CRSR_IMG58: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG59 -----------------------------------------
+#define LCD_CRSR_IMG59_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG59: CRSR_IMG Position */
+#define LCD_CRSR_IMG59_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG59_CRSR_IMG_Pos) /*!< LCD CRSR_IMG59: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG60 -----------------------------------------
+#define LCD_CRSR_IMG60_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG60: CRSR_IMG Position */
+#define LCD_CRSR_IMG60_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG60_CRSR_IMG_Pos) /*!< LCD CRSR_IMG60: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG61 -----------------------------------------
+#define LCD_CRSR_IMG61_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG61: CRSR_IMG Position */
+#define LCD_CRSR_IMG61_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG61_CRSR_IMG_Pos) /*!< LCD CRSR_IMG61: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG62 -----------------------------------------
+#define LCD_CRSR_IMG62_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG62: CRSR_IMG Position */
+#define LCD_CRSR_IMG62_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG62_CRSR_IMG_Pos) /*!< LCD CRSR_IMG62: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG63 -----------------------------------------
+#define LCD_CRSR_IMG63_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG63: CRSR_IMG Position */
+#define LCD_CRSR_IMG63_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG63_CRSR_IMG_Pos) /*!< LCD CRSR_IMG63: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG64 -----------------------------------------
+#define LCD_CRSR_IMG64_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG64: CRSR_IMG Position */
+#define LCD_CRSR_IMG64_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG64_CRSR_IMG_Pos) /*!< LCD CRSR_IMG64: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG65 -----------------------------------------
+#define LCD_CRSR_IMG65_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG65: CRSR_IMG Position */
+#define LCD_CRSR_IMG65_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG65_CRSR_IMG_Pos) /*!< LCD CRSR_IMG65: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG66 -----------------------------------------
+#define LCD_CRSR_IMG66_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG66: CRSR_IMG Position */
+#define LCD_CRSR_IMG66_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG66_CRSR_IMG_Pos) /*!< LCD CRSR_IMG66: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG67 -----------------------------------------
+#define LCD_CRSR_IMG67_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG67: CRSR_IMG Position */
+#define LCD_CRSR_IMG67_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG67_CRSR_IMG_Pos) /*!< LCD CRSR_IMG67: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG68 -----------------------------------------
+#define LCD_CRSR_IMG68_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG68: CRSR_IMG Position */
+#define LCD_CRSR_IMG68_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG68_CRSR_IMG_Pos) /*!< LCD CRSR_IMG68: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG69 -----------------------------------------
+#define LCD_CRSR_IMG69_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG69: CRSR_IMG Position */
+#define LCD_CRSR_IMG69_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG69_CRSR_IMG_Pos) /*!< LCD CRSR_IMG69: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG70 -----------------------------------------
+#define LCD_CRSR_IMG70_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG70: CRSR_IMG Position */
+#define LCD_CRSR_IMG70_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG70_CRSR_IMG_Pos) /*!< LCD CRSR_IMG70: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG71 -----------------------------------------
+#define LCD_CRSR_IMG71_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG71: CRSR_IMG Position */
+#define LCD_CRSR_IMG71_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG71_CRSR_IMG_Pos) /*!< LCD CRSR_IMG71: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG72 -----------------------------------------
+#define LCD_CRSR_IMG72_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG72: CRSR_IMG Position */
+#define LCD_CRSR_IMG72_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG72_CRSR_IMG_Pos) /*!< LCD CRSR_IMG72: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG73 -----------------------------------------
+#define LCD_CRSR_IMG73_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG73: CRSR_IMG Position */
+#define LCD_CRSR_IMG73_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG73_CRSR_IMG_Pos) /*!< LCD CRSR_IMG73: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG74 -----------------------------------------
+#define LCD_CRSR_IMG74_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG74: CRSR_IMG Position */
+#define LCD_CRSR_IMG74_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG74_CRSR_IMG_Pos) /*!< LCD CRSR_IMG74: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG75 -----------------------------------------
+#define LCD_CRSR_IMG75_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG75: CRSR_IMG Position */
+#define LCD_CRSR_IMG75_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG75_CRSR_IMG_Pos) /*!< LCD CRSR_IMG75: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG76 -----------------------------------------
+#define LCD_CRSR_IMG76_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG76: CRSR_IMG Position */
+#define LCD_CRSR_IMG76_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG76_CRSR_IMG_Pos) /*!< LCD CRSR_IMG76: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG77 -----------------------------------------
+#define LCD_CRSR_IMG77_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG77: CRSR_IMG Position */
+#define LCD_CRSR_IMG77_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG77_CRSR_IMG_Pos) /*!< LCD CRSR_IMG77: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG78 -----------------------------------------
+#define LCD_CRSR_IMG78_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG78: CRSR_IMG Position */
+#define LCD_CRSR_IMG78_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG78_CRSR_IMG_Pos) /*!< LCD CRSR_IMG78: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG79 -----------------------------------------
+#define LCD_CRSR_IMG79_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG79: CRSR_IMG Position */
+#define LCD_CRSR_IMG79_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG79_CRSR_IMG_Pos) /*!< LCD CRSR_IMG79: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG80 -----------------------------------------
+#define LCD_CRSR_IMG80_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG80: CRSR_IMG Position */
+#define LCD_CRSR_IMG80_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG80_CRSR_IMG_Pos) /*!< LCD CRSR_IMG80: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG81 -----------------------------------------
+#define LCD_CRSR_IMG81_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG81: CRSR_IMG Position */
+#define LCD_CRSR_IMG81_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG81_CRSR_IMG_Pos) /*!< LCD CRSR_IMG81: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG82 -----------------------------------------
+#define LCD_CRSR_IMG82_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG82: CRSR_IMG Position */
+#define LCD_CRSR_IMG82_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG82_CRSR_IMG_Pos) /*!< LCD CRSR_IMG82: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG83 -----------------------------------------
+#define LCD_CRSR_IMG83_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG83: CRSR_IMG Position */
+#define LCD_CRSR_IMG83_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG83_CRSR_IMG_Pos) /*!< LCD CRSR_IMG83: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG84 -----------------------------------------
+#define LCD_CRSR_IMG84_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG84: CRSR_IMG Position */
+#define LCD_CRSR_IMG84_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG84_CRSR_IMG_Pos) /*!< LCD CRSR_IMG84: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG85 -----------------------------------------
+#define LCD_CRSR_IMG85_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG85: CRSR_IMG Position */
+#define LCD_CRSR_IMG85_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG85_CRSR_IMG_Pos) /*!< LCD CRSR_IMG85: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG86 -----------------------------------------
+#define LCD_CRSR_IMG86_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG86: CRSR_IMG Position */
+#define LCD_CRSR_IMG86_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG86_CRSR_IMG_Pos) /*!< LCD CRSR_IMG86: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG87 -----------------------------------------
+#define LCD_CRSR_IMG87_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG87: CRSR_IMG Position */
+#define LCD_CRSR_IMG87_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG87_CRSR_IMG_Pos) /*!< LCD CRSR_IMG87: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG88 -----------------------------------------
+#define LCD_CRSR_IMG88_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG88: CRSR_IMG Position */
+#define LCD_CRSR_IMG88_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG88_CRSR_IMG_Pos) /*!< LCD CRSR_IMG88: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG89 -----------------------------------------
+#define LCD_CRSR_IMG89_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG89: CRSR_IMG Position */
+#define LCD_CRSR_IMG89_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG89_CRSR_IMG_Pos) /*!< LCD CRSR_IMG89: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG90 -----------------------------------------
+#define LCD_CRSR_IMG90_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG90: CRSR_IMG Position */
+#define LCD_CRSR_IMG90_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG90_CRSR_IMG_Pos) /*!< LCD CRSR_IMG90: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG91 -----------------------------------------
+#define LCD_CRSR_IMG91_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG91: CRSR_IMG Position */
+#define LCD_CRSR_IMG91_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG91_CRSR_IMG_Pos) /*!< LCD CRSR_IMG91: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG92 -----------------------------------------
+#define LCD_CRSR_IMG92_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG92: CRSR_IMG Position */
+#define LCD_CRSR_IMG92_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG92_CRSR_IMG_Pos) /*!< LCD CRSR_IMG92: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG93 -----------------------------------------
+#define LCD_CRSR_IMG93_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG93: CRSR_IMG Position */
+#define LCD_CRSR_IMG93_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG93_CRSR_IMG_Pos) /*!< LCD CRSR_IMG93: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG94 -----------------------------------------
+#define LCD_CRSR_IMG94_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG94: CRSR_IMG Position */
+#define LCD_CRSR_IMG94_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG94_CRSR_IMG_Pos) /*!< LCD CRSR_IMG94: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG95 -----------------------------------------
+#define LCD_CRSR_IMG95_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG95: CRSR_IMG Position */
+#define LCD_CRSR_IMG95_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG95_CRSR_IMG_Pos) /*!< LCD CRSR_IMG95: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG96 -----------------------------------------
+#define LCD_CRSR_IMG96_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG96: CRSR_IMG Position */
+#define LCD_CRSR_IMG96_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG96_CRSR_IMG_Pos) /*!< LCD CRSR_IMG96: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG97 -----------------------------------------
+#define LCD_CRSR_IMG97_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG97: CRSR_IMG Position */
+#define LCD_CRSR_IMG97_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG97_CRSR_IMG_Pos) /*!< LCD CRSR_IMG97: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG98 -----------------------------------------
+#define LCD_CRSR_IMG98_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG98: CRSR_IMG Position */
+#define LCD_CRSR_IMG98_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG98_CRSR_IMG_Pos) /*!< LCD CRSR_IMG98: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG99 -----------------------------------------
+#define LCD_CRSR_IMG99_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG99: CRSR_IMG Position */
+#define LCD_CRSR_IMG99_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG99_CRSR_IMG_Pos) /*!< LCD CRSR_IMG99: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG100 ----------------------------------------
+#define LCD_CRSR_IMG100_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG100: CRSR_IMG Position */
+#define LCD_CRSR_IMG100_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG100_CRSR_IMG_Pos) /*!< LCD CRSR_IMG100: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG101 ----------------------------------------
+#define LCD_CRSR_IMG101_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG101: CRSR_IMG Position */
+#define LCD_CRSR_IMG101_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG101_CRSR_IMG_Pos) /*!< LCD CRSR_IMG101: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG102 ----------------------------------------
+#define LCD_CRSR_IMG102_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG102: CRSR_IMG Position */
+#define LCD_CRSR_IMG102_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG102_CRSR_IMG_Pos) /*!< LCD CRSR_IMG102: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG103 ----------------------------------------
+#define LCD_CRSR_IMG103_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG103: CRSR_IMG Position */
+#define LCD_CRSR_IMG103_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG103_CRSR_IMG_Pos) /*!< LCD CRSR_IMG103: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG104 ----------------------------------------
+#define LCD_CRSR_IMG104_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG104: CRSR_IMG Position */
+#define LCD_CRSR_IMG104_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG104_CRSR_IMG_Pos) /*!< LCD CRSR_IMG104: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG105 ----------------------------------------
+#define LCD_CRSR_IMG105_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG105: CRSR_IMG Position */
+#define LCD_CRSR_IMG105_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG105_CRSR_IMG_Pos) /*!< LCD CRSR_IMG105: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG106 ----------------------------------------
+#define LCD_CRSR_IMG106_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG106: CRSR_IMG Position */
+#define LCD_CRSR_IMG106_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG106_CRSR_IMG_Pos) /*!< LCD CRSR_IMG106: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG107 ----------------------------------------
+#define LCD_CRSR_IMG107_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG107: CRSR_IMG Position */
+#define LCD_CRSR_IMG107_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG107_CRSR_IMG_Pos) /*!< LCD CRSR_IMG107: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG108 ----------------------------------------
+#define LCD_CRSR_IMG108_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG108: CRSR_IMG Position */
+#define LCD_CRSR_IMG108_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG108_CRSR_IMG_Pos) /*!< LCD CRSR_IMG108: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG109 ----------------------------------------
+#define LCD_CRSR_IMG109_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG109: CRSR_IMG Position */
+#define LCD_CRSR_IMG109_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG109_CRSR_IMG_Pos) /*!< LCD CRSR_IMG109: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG110 ----------------------------------------
+#define LCD_CRSR_IMG110_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG110: CRSR_IMG Position */
+#define LCD_CRSR_IMG110_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG110_CRSR_IMG_Pos) /*!< LCD CRSR_IMG110: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG111 ----------------------------------------
+#define LCD_CRSR_IMG111_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG111: CRSR_IMG Position */
+#define LCD_CRSR_IMG111_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG111_CRSR_IMG_Pos) /*!< LCD CRSR_IMG111: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG112 ----------------------------------------
+#define LCD_CRSR_IMG112_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG112: CRSR_IMG Position */
+#define LCD_CRSR_IMG112_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG112_CRSR_IMG_Pos) /*!< LCD CRSR_IMG112: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG113 ----------------------------------------
+#define LCD_CRSR_IMG113_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG113: CRSR_IMG Position */
+#define LCD_CRSR_IMG113_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG113_CRSR_IMG_Pos) /*!< LCD CRSR_IMG113: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG114 ----------------------------------------
+#define LCD_CRSR_IMG114_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG114: CRSR_IMG Position */
+#define LCD_CRSR_IMG114_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG114_CRSR_IMG_Pos) /*!< LCD CRSR_IMG114: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG115 ----------------------------------------
+#define LCD_CRSR_IMG115_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG115: CRSR_IMG Position */
+#define LCD_CRSR_IMG115_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG115_CRSR_IMG_Pos) /*!< LCD CRSR_IMG115: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG116 ----------------------------------------
+#define LCD_CRSR_IMG116_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG116: CRSR_IMG Position */
+#define LCD_CRSR_IMG116_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG116_CRSR_IMG_Pos) /*!< LCD CRSR_IMG116: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG117 ----------------------------------------
+#define LCD_CRSR_IMG117_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG117: CRSR_IMG Position */
+#define LCD_CRSR_IMG117_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG117_CRSR_IMG_Pos) /*!< LCD CRSR_IMG117: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG118 ----------------------------------------
+#define LCD_CRSR_IMG118_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG118: CRSR_IMG Position */
+#define LCD_CRSR_IMG118_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG118_CRSR_IMG_Pos) /*!< LCD CRSR_IMG118: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG119 ----------------------------------------
+#define LCD_CRSR_IMG119_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG119: CRSR_IMG Position */
+#define LCD_CRSR_IMG119_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG119_CRSR_IMG_Pos) /*!< LCD CRSR_IMG119: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG120 ----------------------------------------
+#define LCD_CRSR_IMG120_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG120: CRSR_IMG Position */
+#define LCD_CRSR_IMG120_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG120_CRSR_IMG_Pos) /*!< LCD CRSR_IMG120: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG121 ----------------------------------------
+#define LCD_CRSR_IMG121_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG121: CRSR_IMG Position */
+#define LCD_CRSR_IMG121_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG121_CRSR_IMG_Pos) /*!< LCD CRSR_IMG121: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG122 ----------------------------------------
+#define LCD_CRSR_IMG122_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG122: CRSR_IMG Position */
+#define LCD_CRSR_IMG122_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG122_CRSR_IMG_Pos) /*!< LCD CRSR_IMG122: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG123 ----------------------------------------
+#define LCD_CRSR_IMG123_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG123: CRSR_IMG Position */
+#define LCD_CRSR_IMG123_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG123_CRSR_IMG_Pos) /*!< LCD CRSR_IMG123: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG124 ----------------------------------------
+#define LCD_CRSR_IMG124_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG124: CRSR_IMG Position */
+#define LCD_CRSR_IMG124_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG124_CRSR_IMG_Pos) /*!< LCD CRSR_IMG124: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG125 ----------------------------------------
+#define LCD_CRSR_IMG125_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG125: CRSR_IMG Position */
+#define LCD_CRSR_IMG125_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG125_CRSR_IMG_Pos) /*!< LCD CRSR_IMG125: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG126 ----------------------------------------
+#define LCD_CRSR_IMG126_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG126: CRSR_IMG Position */
+#define LCD_CRSR_IMG126_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG126_CRSR_IMG_Pos) /*!< LCD CRSR_IMG126: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG127 ----------------------------------------
+#define LCD_CRSR_IMG127_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG127: CRSR_IMG Position */
+#define LCD_CRSR_IMG127_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG127_CRSR_IMG_Pos) /*!< LCD CRSR_IMG127: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG128 ----------------------------------------
+#define LCD_CRSR_IMG128_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG128: CRSR_IMG Position */
+#define LCD_CRSR_IMG128_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG128_CRSR_IMG_Pos) /*!< LCD CRSR_IMG128: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG129 ----------------------------------------
+#define LCD_CRSR_IMG129_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG129: CRSR_IMG Position */
+#define LCD_CRSR_IMG129_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG129_CRSR_IMG_Pos) /*!< LCD CRSR_IMG129: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG130 ----------------------------------------
+#define LCD_CRSR_IMG130_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG130: CRSR_IMG Position */
+#define LCD_CRSR_IMG130_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG130_CRSR_IMG_Pos) /*!< LCD CRSR_IMG130: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG131 ----------------------------------------
+#define LCD_CRSR_IMG131_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG131: CRSR_IMG Position */
+#define LCD_CRSR_IMG131_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG131_CRSR_IMG_Pos) /*!< LCD CRSR_IMG131: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG132 ----------------------------------------
+#define LCD_CRSR_IMG132_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG132: CRSR_IMG Position */
+#define LCD_CRSR_IMG132_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG132_CRSR_IMG_Pos) /*!< LCD CRSR_IMG132: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG133 ----------------------------------------
+#define LCD_CRSR_IMG133_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG133: CRSR_IMG Position */
+#define LCD_CRSR_IMG133_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG133_CRSR_IMG_Pos) /*!< LCD CRSR_IMG133: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG134 ----------------------------------------
+#define LCD_CRSR_IMG134_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG134: CRSR_IMG Position */
+#define LCD_CRSR_IMG134_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG134_CRSR_IMG_Pos) /*!< LCD CRSR_IMG134: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG135 ----------------------------------------
+#define LCD_CRSR_IMG135_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG135: CRSR_IMG Position */
+#define LCD_CRSR_IMG135_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG135_CRSR_IMG_Pos) /*!< LCD CRSR_IMG135: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG136 ----------------------------------------
+#define LCD_CRSR_IMG136_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG136: CRSR_IMG Position */
+#define LCD_CRSR_IMG136_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG136_CRSR_IMG_Pos) /*!< LCD CRSR_IMG136: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG137 ----------------------------------------
+#define LCD_CRSR_IMG137_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG137: CRSR_IMG Position */
+#define LCD_CRSR_IMG137_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG137_CRSR_IMG_Pos) /*!< LCD CRSR_IMG137: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG138 ----------------------------------------
+#define LCD_CRSR_IMG138_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG138: CRSR_IMG Position */
+#define LCD_CRSR_IMG138_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG138_CRSR_IMG_Pos) /*!< LCD CRSR_IMG138: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG139 ----------------------------------------
+#define LCD_CRSR_IMG139_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG139: CRSR_IMG Position */
+#define LCD_CRSR_IMG139_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG139_CRSR_IMG_Pos) /*!< LCD CRSR_IMG139: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG140 ----------------------------------------
+#define LCD_CRSR_IMG140_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG140: CRSR_IMG Position */
+#define LCD_CRSR_IMG140_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG140_CRSR_IMG_Pos) /*!< LCD CRSR_IMG140: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG141 ----------------------------------------
+#define LCD_CRSR_IMG141_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG141: CRSR_IMG Position */
+#define LCD_CRSR_IMG141_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG141_CRSR_IMG_Pos) /*!< LCD CRSR_IMG141: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG142 ----------------------------------------
+#define LCD_CRSR_IMG142_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG142: CRSR_IMG Position */
+#define LCD_CRSR_IMG142_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG142_CRSR_IMG_Pos) /*!< LCD CRSR_IMG142: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG143 ----------------------------------------
+#define LCD_CRSR_IMG143_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG143: CRSR_IMG Position */
+#define LCD_CRSR_IMG143_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG143_CRSR_IMG_Pos) /*!< LCD CRSR_IMG143: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG144 ----------------------------------------
+#define LCD_CRSR_IMG144_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG144: CRSR_IMG Position */
+#define LCD_CRSR_IMG144_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG144_CRSR_IMG_Pos) /*!< LCD CRSR_IMG144: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG145 ----------------------------------------
+#define LCD_CRSR_IMG145_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG145: CRSR_IMG Position */
+#define LCD_CRSR_IMG145_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG145_CRSR_IMG_Pos) /*!< LCD CRSR_IMG145: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG146 ----------------------------------------
+#define LCD_CRSR_IMG146_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG146: CRSR_IMG Position */
+#define LCD_CRSR_IMG146_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG146_CRSR_IMG_Pos) /*!< LCD CRSR_IMG146: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG147 ----------------------------------------
+#define LCD_CRSR_IMG147_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG147: CRSR_IMG Position */
+#define LCD_CRSR_IMG147_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG147_CRSR_IMG_Pos) /*!< LCD CRSR_IMG147: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG148 ----------------------------------------
+#define LCD_CRSR_IMG148_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG148: CRSR_IMG Position */
+#define LCD_CRSR_IMG148_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG148_CRSR_IMG_Pos) /*!< LCD CRSR_IMG148: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG149 ----------------------------------------
+#define LCD_CRSR_IMG149_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG149: CRSR_IMG Position */
+#define LCD_CRSR_IMG149_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG149_CRSR_IMG_Pos) /*!< LCD CRSR_IMG149: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG150 ----------------------------------------
+#define LCD_CRSR_IMG150_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG150: CRSR_IMG Position */
+#define LCD_CRSR_IMG150_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG150_CRSR_IMG_Pos) /*!< LCD CRSR_IMG150: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG151 ----------------------------------------
+#define LCD_CRSR_IMG151_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG151: CRSR_IMG Position */
+#define LCD_CRSR_IMG151_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG151_CRSR_IMG_Pos) /*!< LCD CRSR_IMG151: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG152 ----------------------------------------
+#define LCD_CRSR_IMG152_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG152: CRSR_IMG Position */
+#define LCD_CRSR_IMG152_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG152_CRSR_IMG_Pos) /*!< LCD CRSR_IMG152: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG153 ----------------------------------------
+#define LCD_CRSR_IMG153_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG153: CRSR_IMG Position */
+#define LCD_CRSR_IMG153_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG153_CRSR_IMG_Pos) /*!< LCD CRSR_IMG153: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG154 ----------------------------------------
+#define LCD_CRSR_IMG154_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG154: CRSR_IMG Position */
+#define LCD_CRSR_IMG154_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG154_CRSR_IMG_Pos) /*!< LCD CRSR_IMG154: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG155 ----------------------------------------
+#define LCD_CRSR_IMG155_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG155: CRSR_IMG Position */
+#define LCD_CRSR_IMG155_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG155_CRSR_IMG_Pos) /*!< LCD CRSR_IMG155: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG156 ----------------------------------------
+#define LCD_CRSR_IMG156_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG156: CRSR_IMG Position */
+#define LCD_CRSR_IMG156_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG156_CRSR_IMG_Pos) /*!< LCD CRSR_IMG156: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG157 ----------------------------------------
+#define LCD_CRSR_IMG157_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG157: CRSR_IMG Position */
+#define LCD_CRSR_IMG157_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG157_CRSR_IMG_Pos) /*!< LCD CRSR_IMG157: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG158 ----------------------------------------
+#define LCD_CRSR_IMG158_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG158: CRSR_IMG Position */
+#define LCD_CRSR_IMG158_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG158_CRSR_IMG_Pos) /*!< LCD CRSR_IMG158: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG159 ----------------------------------------
+#define LCD_CRSR_IMG159_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG159: CRSR_IMG Position */
+#define LCD_CRSR_IMG159_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG159_CRSR_IMG_Pos) /*!< LCD CRSR_IMG159: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG160 ----------------------------------------
+#define LCD_CRSR_IMG160_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG160: CRSR_IMG Position */
+#define LCD_CRSR_IMG160_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG160_CRSR_IMG_Pos) /*!< LCD CRSR_IMG160: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG161 ----------------------------------------
+#define LCD_CRSR_IMG161_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG161: CRSR_IMG Position */
+#define LCD_CRSR_IMG161_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG161_CRSR_IMG_Pos) /*!< LCD CRSR_IMG161: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG162 ----------------------------------------
+#define LCD_CRSR_IMG162_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG162: CRSR_IMG Position */
+#define LCD_CRSR_IMG162_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG162_CRSR_IMG_Pos) /*!< LCD CRSR_IMG162: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG163 ----------------------------------------
+#define LCD_CRSR_IMG163_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG163: CRSR_IMG Position */
+#define LCD_CRSR_IMG163_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG163_CRSR_IMG_Pos) /*!< LCD CRSR_IMG163: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG164 ----------------------------------------
+#define LCD_CRSR_IMG164_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG164: CRSR_IMG Position */
+#define LCD_CRSR_IMG164_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG164_CRSR_IMG_Pos) /*!< LCD CRSR_IMG164: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG165 ----------------------------------------
+#define LCD_CRSR_IMG165_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG165: CRSR_IMG Position */
+#define LCD_CRSR_IMG165_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG165_CRSR_IMG_Pos) /*!< LCD CRSR_IMG165: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG166 ----------------------------------------
+#define LCD_CRSR_IMG166_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG166: CRSR_IMG Position */
+#define LCD_CRSR_IMG166_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG166_CRSR_IMG_Pos) /*!< LCD CRSR_IMG166: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG167 ----------------------------------------
+#define LCD_CRSR_IMG167_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG167: CRSR_IMG Position */
+#define LCD_CRSR_IMG167_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG167_CRSR_IMG_Pos) /*!< LCD CRSR_IMG167: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG168 ----------------------------------------
+#define LCD_CRSR_IMG168_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG168: CRSR_IMG Position */
+#define LCD_CRSR_IMG168_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG168_CRSR_IMG_Pos) /*!< LCD CRSR_IMG168: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG169 ----------------------------------------
+#define LCD_CRSR_IMG169_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG169: CRSR_IMG Position */
+#define LCD_CRSR_IMG169_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG169_CRSR_IMG_Pos) /*!< LCD CRSR_IMG169: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG170 ----------------------------------------
+#define LCD_CRSR_IMG170_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG170: CRSR_IMG Position */
+#define LCD_CRSR_IMG170_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG170_CRSR_IMG_Pos) /*!< LCD CRSR_IMG170: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG171 ----------------------------------------
+#define LCD_CRSR_IMG171_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG171: CRSR_IMG Position */
+#define LCD_CRSR_IMG171_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG171_CRSR_IMG_Pos) /*!< LCD CRSR_IMG171: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG172 ----------------------------------------
+#define LCD_CRSR_IMG172_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG172: CRSR_IMG Position */
+#define LCD_CRSR_IMG172_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG172_CRSR_IMG_Pos) /*!< LCD CRSR_IMG172: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG173 ----------------------------------------
+#define LCD_CRSR_IMG173_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG173: CRSR_IMG Position */
+#define LCD_CRSR_IMG173_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG173_CRSR_IMG_Pos) /*!< LCD CRSR_IMG173: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG174 ----------------------------------------
+#define LCD_CRSR_IMG174_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG174: CRSR_IMG Position */
+#define LCD_CRSR_IMG174_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG174_CRSR_IMG_Pos) /*!< LCD CRSR_IMG174: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG175 ----------------------------------------
+#define LCD_CRSR_IMG175_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG175: CRSR_IMG Position */
+#define LCD_CRSR_IMG175_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG175_CRSR_IMG_Pos) /*!< LCD CRSR_IMG175: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG176 ----------------------------------------
+#define LCD_CRSR_IMG176_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG176: CRSR_IMG Position */
+#define LCD_CRSR_IMG176_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG176_CRSR_IMG_Pos) /*!< LCD CRSR_IMG176: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG177 ----------------------------------------
+#define LCD_CRSR_IMG177_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG177: CRSR_IMG Position */
+#define LCD_CRSR_IMG177_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG177_CRSR_IMG_Pos) /*!< LCD CRSR_IMG177: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG178 ----------------------------------------
+#define LCD_CRSR_IMG178_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG178: CRSR_IMG Position */
+#define LCD_CRSR_IMG178_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG178_CRSR_IMG_Pos) /*!< LCD CRSR_IMG178: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG179 ----------------------------------------
+#define LCD_CRSR_IMG179_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG179: CRSR_IMG Position */
+#define LCD_CRSR_IMG179_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG179_CRSR_IMG_Pos) /*!< LCD CRSR_IMG179: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG180 ----------------------------------------
+#define LCD_CRSR_IMG180_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG180: CRSR_IMG Position */
+#define LCD_CRSR_IMG180_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG180_CRSR_IMG_Pos) /*!< LCD CRSR_IMG180: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG181 ----------------------------------------
+#define LCD_CRSR_IMG181_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG181: CRSR_IMG Position */
+#define LCD_CRSR_IMG181_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG181_CRSR_IMG_Pos) /*!< LCD CRSR_IMG181: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG182 ----------------------------------------
+#define LCD_CRSR_IMG182_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG182: CRSR_IMG Position */
+#define LCD_CRSR_IMG182_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG182_CRSR_IMG_Pos) /*!< LCD CRSR_IMG182: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG183 ----------------------------------------
+#define LCD_CRSR_IMG183_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG183: CRSR_IMG Position */
+#define LCD_CRSR_IMG183_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG183_CRSR_IMG_Pos) /*!< LCD CRSR_IMG183: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG184 ----------------------------------------
+#define LCD_CRSR_IMG184_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG184: CRSR_IMG Position */
+#define LCD_CRSR_IMG184_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG184_CRSR_IMG_Pos) /*!< LCD CRSR_IMG184: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG185 ----------------------------------------
+#define LCD_CRSR_IMG185_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG185: CRSR_IMG Position */
+#define LCD_CRSR_IMG185_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG185_CRSR_IMG_Pos) /*!< LCD CRSR_IMG185: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG186 ----------------------------------------
+#define LCD_CRSR_IMG186_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG186: CRSR_IMG Position */
+#define LCD_CRSR_IMG186_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG186_CRSR_IMG_Pos) /*!< LCD CRSR_IMG186: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG187 ----------------------------------------
+#define LCD_CRSR_IMG187_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG187: CRSR_IMG Position */
+#define LCD_CRSR_IMG187_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG187_CRSR_IMG_Pos) /*!< LCD CRSR_IMG187: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG188 ----------------------------------------
+#define LCD_CRSR_IMG188_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG188: CRSR_IMG Position */
+#define LCD_CRSR_IMG188_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG188_CRSR_IMG_Pos) /*!< LCD CRSR_IMG188: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG189 ----------------------------------------
+#define LCD_CRSR_IMG189_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG189: CRSR_IMG Position */
+#define LCD_CRSR_IMG189_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG189_CRSR_IMG_Pos) /*!< LCD CRSR_IMG189: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG190 ----------------------------------------
+#define LCD_CRSR_IMG190_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG190: CRSR_IMG Position */
+#define LCD_CRSR_IMG190_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG190_CRSR_IMG_Pos) /*!< LCD CRSR_IMG190: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG191 ----------------------------------------
+#define LCD_CRSR_IMG191_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG191: CRSR_IMG Position */
+#define LCD_CRSR_IMG191_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG191_CRSR_IMG_Pos) /*!< LCD CRSR_IMG191: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG192 ----------------------------------------
+#define LCD_CRSR_IMG192_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG192: CRSR_IMG Position */
+#define LCD_CRSR_IMG192_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG192_CRSR_IMG_Pos) /*!< LCD CRSR_IMG192: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG193 ----------------------------------------
+#define LCD_CRSR_IMG193_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG193: CRSR_IMG Position */
+#define LCD_CRSR_IMG193_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG193_CRSR_IMG_Pos) /*!< LCD CRSR_IMG193: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG194 ----------------------------------------
+#define LCD_CRSR_IMG194_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG194: CRSR_IMG Position */
+#define LCD_CRSR_IMG194_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG194_CRSR_IMG_Pos) /*!< LCD CRSR_IMG194: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG195 ----------------------------------------
+#define LCD_CRSR_IMG195_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG195: CRSR_IMG Position */
+#define LCD_CRSR_IMG195_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG195_CRSR_IMG_Pos) /*!< LCD CRSR_IMG195: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG196 ----------------------------------------
+#define LCD_CRSR_IMG196_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG196: CRSR_IMG Position */
+#define LCD_CRSR_IMG196_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG196_CRSR_IMG_Pos) /*!< LCD CRSR_IMG196: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG197 ----------------------------------------
+#define LCD_CRSR_IMG197_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG197: CRSR_IMG Position */
+#define LCD_CRSR_IMG197_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG197_CRSR_IMG_Pos) /*!< LCD CRSR_IMG197: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG198 ----------------------------------------
+#define LCD_CRSR_IMG198_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG198: CRSR_IMG Position */
+#define LCD_CRSR_IMG198_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG198_CRSR_IMG_Pos) /*!< LCD CRSR_IMG198: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG199 ----------------------------------------
+#define LCD_CRSR_IMG199_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG199: CRSR_IMG Position */
+#define LCD_CRSR_IMG199_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG199_CRSR_IMG_Pos) /*!< LCD CRSR_IMG199: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG200 ----------------------------------------
+#define LCD_CRSR_IMG200_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG200: CRSR_IMG Position */
+#define LCD_CRSR_IMG200_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG200_CRSR_IMG_Pos) /*!< LCD CRSR_IMG200: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG201 ----------------------------------------
+#define LCD_CRSR_IMG201_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG201: CRSR_IMG Position */
+#define LCD_CRSR_IMG201_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG201_CRSR_IMG_Pos) /*!< LCD CRSR_IMG201: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG202 ----------------------------------------
+#define LCD_CRSR_IMG202_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG202: CRSR_IMG Position */
+#define LCD_CRSR_IMG202_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG202_CRSR_IMG_Pos) /*!< LCD CRSR_IMG202: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG203 ----------------------------------------
+#define LCD_CRSR_IMG203_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG203: CRSR_IMG Position */
+#define LCD_CRSR_IMG203_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG203_CRSR_IMG_Pos) /*!< LCD CRSR_IMG203: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG204 ----------------------------------------
+#define LCD_CRSR_IMG204_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG204: CRSR_IMG Position */
+#define LCD_CRSR_IMG204_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG204_CRSR_IMG_Pos) /*!< LCD CRSR_IMG204: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG205 ----------------------------------------
+#define LCD_CRSR_IMG205_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG205: CRSR_IMG Position */
+#define LCD_CRSR_IMG205_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG205_CRSR_IMG_Pos) /*!< LCD CRSR_IMG205: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG206 ----------------------------------------
+#define LCD_CRSR_IMG206_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG206: CRSR_IMG Position */
+#define LCD_CRSR_IMG206_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG206_CRSR_IMG_Pos) /*!< LCD CRSR_IMG206: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG207 ----------------------------------------
+#define LCD_CRSR_IMG207_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG207: CRSR_IMG Position */
+#define LCD_CRSR_IMG207_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG207_CRSR_IMG_Pos) /*!< LCD CRSR_IMG207: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG208 ----------------------------------------
+#define LCD_CRSR_IMG208_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG208: CRSR_IMG Position */
+#define LCD_CRSR_IMG208_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG208_CRSR_IMG_Pos) /*!< LCD CRSR_IMG208: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG209 ----------------------------------------
+#define LCD_CRSR_IMG209_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG209: CRSR_IMG Position */
+#define LCD_CRSR_IMG209_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG209_CRSR_IMG_Pos) /*!< LCD CRSR_IMG209: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG210 ----------------------------------------
+#define LCD_CRSR_IMG210_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG210: CRSR_IMG Position */
+#define LCD_CRSR_IMG210_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG210_CRSR_IMG_Pos) /*!< LCD CRSR_IMG210: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG211 ----------------------------------------
+#define LCD_CRSR_IMG211_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG211: CRSR_IMG Position */
+#define LCD_CRSR_IMG211_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG211_CRSR_IMG_Pos) /*!< LCD CRSR_IMG211: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG212 ----------------------------------------
+#define LCD_CRSR_IMG212_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG212: CRSR_IMG Position */
+#define LCD_CRSR_IMG212_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG212_CRSR_IMG_Pos) /*!< LCD CRSR_IMG212: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG213 ----------------------------------------
+#define LCD_CRSR_IMG213_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG213: CRSR_IMG Position */
+#define LCD_CRSR_IMG213_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG213_CRSR_IMG_Pos) /*!< LCD CRSR_IMG213: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG214 ----------------------------------------
+#define LCD_CRSR_IMG214_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG214: CRSR_IMG Position */
+#define LCD_CRSR_IMG214_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG214_CRSR_IMG_Pos) /*!< LCD CRSR_IMG214: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG215 ----------------------------------------
+#define LCD_CRSR_IMG215_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG215: CRSR_IMG Position */
+#define LCD_CRSR_IMG215_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG215_CRSR_IMG_Pos) /*!< LCD CRSR_IMG215: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG216 ----------------------------------------
+#define LCD_CRSR_IMG216_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG216: CRSR_IMG Position */
+#define LCD_CRSR_IMG216_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG216_CRSR_IMG_Pos) /*!< LCD CRSR_IMG216: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG217 ----------------------------------------
+#define LCD_CRSR_IMG217_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG217: CRSR_IMG Position */
+#define LCD_CRSR_IMG217_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG217_CRSR_IMG_Pos) /*!< LCD CRSR_IMG217: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG218 ----------------------------------------
+#define LCD_CRSR_IMG218_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG218: CRSR_IMG Position */
+#define LCD_CRSR_IMG218_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG218_CRSR_IMG_Pos) /*!< LCD CRSR_IMG218: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG219 ----------------------------------------
+#define LCD_CRSR_IMG219_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG219: CRSR_IMG Position */
+#define LCD_CRSR_IMG219_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG219_CRSR_IMG_Pos) /*!< LCD CRSR_IMG219: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG220 ----------------------------------------
+#define LCD_CRSR_IMG220_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG220: CRSR_IMG Position */
+#define LCD_CRSR_IMG220_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG220_CRSR_IMG_Pos) /*!< LCD CRSR_IMG220: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG221 ----------------------------------------
+#define LCD_CRSR_IMG221_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG221: CRSR_IMG Position */
+#define LCD_CRSR_IMG221_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG221_CRSR_IMG_Pos) /*!< LCD CRSR_IMG221: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG222 ----------------------------------------
+#define LCD_CRSR_IMG222_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG222: CRSR_IMG Position */
+#define LCD_CRSR_IMG222_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG222_CRSR_IMG_Pos) /*!< LCD CRSR_IMG222: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG223 ----------------------------------------
+#define LCD_CRSR_IMG223_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG223: CRSR_IMG Position */
+#define LCD_CRSR_IMG223_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG223_CRSR_IMG_Pos) /*!< LCD CRSR_IMG223: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG224 ----------------------------------------
+#define LCD_CRSR_IMG224_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG224: CRSR_IMG Position */
+#define LCD_CRSR_IMG224_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG224_CRSR_IMG_Pos) /*!< LCD CRSR_IMG224: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG225 ----------------------------------------
+#define LCD_CRSR_IMG225_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG225: CRSR_IMG Position */
+#define LCD_CRSR_IMG225_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG225_CRSR_IMG_Pos) /*!< LCD CRSR_IMG225: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG226 ----------------------------------------
+#define LCD_CRSR_IMG226_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG226: CRSR_IMG Position */
+#define LCD_CRSR_IMG226_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG226_CRSR_IMG_Pos) /*!< LCD CRSR_IMG226: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG227 ----------------------------------------
+#define LCD_CRSR_IMG227_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG227: CRSR_IMG Position */
+#define LCD_CRSR_IMG227_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG227_CRSR_IMG_Pos) /*!< LCD CRSR_IMG227: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG228 ----------------------------------------
+#define LCD_CRSR_IMG228_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG228: CRSR_IMG Position */
+#define LCD_CRSR_IMG228_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG228_CRSR_IMG_Pos) /*!< LCD CRSR_IMG228: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG229 ----------------------------------------
+#define LCD_CRSR_IMG229_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG229: CRSR_IMG Position */
+#define LCD_CRSR_IMG229_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG229_CRSR_IMG_Pos) /*!< LCD CRSR_IMG229: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG230 ----------------------------------------
+#define LCD_CRSR_IMG230_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG230: CRSR_IMG Position */
+#define LCD_CRSR_IMG230_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG230_CRSR_IMG_Pos) /*!< LCD CRSR_IMG230: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG231 ----------------------------------------
+#define LCD_CRSR_IMG231_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG231: CRSR_IMG Position */
+#define LCD_CRSR_IMG231_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG231_CRSR_IMG_Pos) /*!< LCD CRSR_IMG231: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG232 ----------------------------------------
+#define LCD_CRSR_IMG232_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG232: CRSR_IMG Position */
+#define LCD_CRSR_IMG232_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG232_CRSR_IMG_Pos) /*!< LCD CRSR_IMG232: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG233 ----------------------------------------
+#define LCD_CRSR_IMG233_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG233: CRSR_IMG Position */
+#define LCD_CRSR_IMG233_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG233_CRSR_IMG_Pos) /*!< LCD CRSR_IMG233: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG234 ----------------------------------------
+#define LCD_CRSR_IMG234_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG234: CRSR_IMG Position */
+#define LCD_CRSR_IMG234_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG234_CRSR_IMG_Pos) /*!< LCD CRSR_IMG234: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG235 ----------------------------------------
+#define LCD_CRSR_IMG235_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG235: CRSR_IMG Position */
+#define LCD_CRSR_IMG235_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG235_CRSR_IMG_Pos) /*!< LCD CRSR_IMG235: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG236 ----------------------------------------
+#define LCD_CRSR_IMG236_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG236: CRSR_IMG Position */
+#define LCD_CRSR_IMG236_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG236_CRSR_IMG_Pos) /*!< LCD CRSR_IMG236: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG237 ----------------------------------------
+#define LCD_CRSR_IMG237_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG237: CRSR_IMG Position */
+#define LCD_CRSR_IMG237_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG237_CRSR_IMG_Pos) /*!< LCD CRSR_IMG237: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG238 ----------------------------------------
+#define LCD_CRSR_IMG238_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG238: CRSR_IMG Position */
+#define LCD_CRSR_IMG238_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG238_CRSR_IMG_Pos) /*!< LCD CRSR_IMG238: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG239 ----------------------------------------
+#define LCD_CRSR_IMG239_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG239: CRSR_IMG Position */
+#define LCD_CRSR_IMG239_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG239_CRSR_IMG_Pos) /*!< LCD CRSR_IMG239: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG240 ----------------------------------------
+#define LCD_CRSR_IMG240_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG240: CRSR_IMG Position */
+#define LCD_CRSR_IMG240_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG240_CRSR_IMG_Pos) /*!< LCD CRSR_IMG240: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG241 ----------------------------------------
+#define LCD_CRSR_IMG241_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG241: CRSR_IMG Position */
+#define LCD_CRSR_IMG241_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG241_CRSR_IMG_Pos) /*!< LCD CRSR_IMG241: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG242 ----------------------------------------
+#define LCD_CRSR_IMG242_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG242: CRSR_IMG Position */
+#define LCD_CRSR_IMG242_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG242_CRSR_IMG_Pos) /*!< LCD CRSR_IMG242: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG243 ----------------------------------------
+#define LCD_CRSR_IMG243_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG243: CRSR_IMG Position */
+#define LCD_CRSR_IMG243_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG243_CRSR_IMG_Pos) /*!< LCD CRSR_IMG243: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG244 ----------------------------------------
+#define LCD_CRSR_IMG244_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG244: CRSR_IMG Position */
+#define LCD_CRSR_IMG244_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG244_CRSR_IMG_Pos) /*!< LCD CRSR_IMG244: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG245 ----------------------------------------
+#define LCD_CRSR_IMG245_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG245: CRSR_IMG Position */
+#define LCD_CRSR_IMG245_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG245_CRSR_IMG_Pos) /*!< LCD CRSR_IMG245: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG246 ----------------------------------------
+#define LCD_CRSR_IMG246_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG246: CRSR_IMG Position */
+#define LCD_CRSR_IMG246_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG246_CRSR_IMG_Pos) /*!< LCD CRSR_IMG246: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG247 ----------------------------------------
+#define LCD_CRSR_IMG247_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG247: CRSR_IMG Position */
+#define LCD_CRSR_IMG247_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG247_CRSR_IMG_Pos) /*!< LCD CRSR_IMG247: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG248 ----------------------------------------
+#define LCD_CRSR_IMG248_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG248: CRSR_IMG Position */
+#define LCD_CRSR_IMG248_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG248_CRSR_IMG_Pos) /*!< LCD CRSR_IMG248: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG249 ----------------------------------------
+#define LCD_CRSR_IMG249_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG249: CRSR_IMG Position */
+#define LCD_CRSR_IMG249_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG249_CRSR_IMG_Pos) /*!< LCD CRSR_IMG249: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG250 ----------------------------------------
+#define LCD_CRSR_IMG250_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG250: CRSR_IMG Position */
+#define LCD_CRSR_IMG250_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG250_CRSR_IMG_Pos) /*!< LCD CRSR_IMG250: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG251 ----------------------------------------
+#define LCD_CRSR_IMG251_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG251: CRSR_IMG Position */
+#define LCD_CRSR_IMG251_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG251_CRSR_IMG_Pos) /*!< LCD CRSR_IMG251: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG252 ----------------------------------------
+#define LCD_CRSR_IMG252_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG252: CRSR_IMG Position */
+#define LCD_CRSR_IMG252_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG252_CRSR_IMG_Pos) /*!< LCD CRSR_IMG252: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG253 ----------------------------------------
+#define LCD_CRSR_IMG253_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG253: CRSR_IMG Position */
+#define LCD_CRSR_IMG253_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG253_CRSR_IMG_Pos) /*!< LCD CRSR_IMG253: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG254 ----------------------------------------
+#define LCD_CRSR_IMG254_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG254: CRSR_IMG Position */
+#define LCD_CRSR_IMG254_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG254_CRSR_IMG_Pos) /*!< LCD CRSR_IMG254: CRSR_IMG Mask */
+
+// ------------------------------------- LCD_CRSR_IMG255 ----------------------------------------
+#define LCD_CRSR_IMG255_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG255: CRSR_IMG Position */
+#define LCD_CRSR_IMG255_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG255_CRSR_IMG_Pos) /*!< LCD CRSR_IMG255: CRSR_IMG Mask */
+
+// -------------------------------------- LCD_CRSR_CTRL -----------------------------------------
+#define LCD_CRSR_CTRL_CrsrOn_Pos 0 /*!< LCD CRSR_CTRL: CrsrOn Position */
+#define LCD_CRSR_CTRL_CrsrOn_Msk (0x01UL << LCD_CRSR_CTRL_CrsrOn_Pos) /*!< LCD CRSR_CTRL: CrsrOn Mask */
+#define LCD_CRSR_CTRL_CRSRNUM1_0_Pos 4 /*!< LCD CRSR_CTRL: CRSRNUM1_0 Position */
+#define LCD_CRSR_CTRL_CRSRNUM1_0_Msk (0x03UL << LCD_CRSR_CTRL_CRSRNUM1_0_Pos) /*!< LCD CRSR_CTRL: CRSRNUM1_0 Mask */
+
+// -------------------------------------- LCD_CRSR_CFG ------------------------------------------
+#define LCD_CRSR_CFG_CrsrSize_Pos 0 /*!< LCD CRSR_CFG: CrsrSize Position */
+#define LCD_CRSR_CFG_CrsrSize_Msk (0x01UL << LCD_CRSR_CFG_CrsrSize_Pos) /*!< LCD CRSR_CFG: CrsrSize Mask */
+#define LCD_CRSR_CFG_FRAMESYNC_Pos 1 /*!< LCD CRSR_CFG: FRAMESYNC Position */
+#define LCD_CRSR_CFG_FRAMESYNC_Msk (0x01UL << LCD_CRSR_CFG_FRAMESYNC_Pos) /*!< LCD CRSR_CFG: FRAMESYNC Mask */
+
+// -------------------------------------- LCD_CRSR_PAL0 -----------------------------------------
+#define LCD_CRSR_PAL0_RED_Pos 0 /*!< LCD CRSR_PAL0: RED Position */
+#define LCD_CRSR_PAL0_RED_Msk (0x000000ffUL << LCD_CRSR_PAL0_RED_Pos) /*!< LCD CRSR_PAL0: RED Mask */
+#define LCD_CRSR_PAL0_GREEN_Pos 8 /*!< LCD CRSR_PAL0: GREEN Position */
+#define LCD_CRSR_PAL0_GREEN_Msk (0x000000ffUL << LCD_CRSR_PAL0_GREEN_Pos) /*!< LCD CRSR_PAL0: GREEN Mask */
+#define LCD_CRSR_PAL0_BLUE_Pos 16 /*!< LCD CRSR_PAL0: BLUE Position */
+#define LCD_CRSR_PAL0_BLUE_Msk (0x000000ffUL << LCD_CRSR_PAL0_BLUE_Pos) /*!< LCD CRSR_PAL0: BLUE Mask */
+
+// -------------------------------------- LCD_CRSR_PAL1 -----------------------------------------
+#define LCD_CRSR_PAL1_RED_Pos 0 /*!< LCD CRSR_PAL1: RED Position */
+#define LCD_CRSR_PAL1_RED_Msk (0x000000ffUL << LCD_CRSR_PAL1_RED_Pos) /*!< LCD CRSR_PAL1: RED Mask */
+#define LCD_CRSR_PAL1_GREEN_Pos 8 /*!< LCD CRSR_PAL1: GREEN Position */
+#define LCD_CRSR_PAL1_GREEN_Msk (0x000000ffUL << LCD_CRSR_PAL1_GREEN_Pos) /*!< LCD CRSR_PAL1: GREEN Mask */
+#define LCD_CRSR_PAL1_BLUE_Pos 16 /*!< LCD CRSR_PAL1: BLUE Position */
+#define LCD_CRSR_PAL1_BLUE_Msk (0x000000ffUL << LCD_CRSR_PAL1_BLUE_Pos) /*!< LCD CRSR_PAL1: BLUE Mask */
+
+// --------------------------------------- LCD_CRSR_XY ------------------------------------------
+#define LCD_CRSR_XY_CRSRX_Pos 0 /*!< LCD CRSR_XY: CRSRX Position */
+#define LCD_CRSR_XY_CRSRX_Msk (0x000003ffUL << LCD_CRSR_XY_CRSRX_Pos) /*!< LCD CRSR_XY: CRSRX Mask */
+#define LCD_CRSR_XY_CRSRY_Pos 16 /*!< LCD CRSR_XY: CRSRY Position */
+#define LCD_CRSR_XY_CRSRY_Msk (0x000003ffUL << LCD_CRSR_XY_CRSRY_Pos) /*!< LCD CRSR_XY: CRSRY Mask */
+
+// -------------------------------------- LCD_CRSR_CLIP -----------------------------------------
+#define LCD_CRSR_CLIP_CRSRCLIPX_Pos 0 /*!< LCD CRSR_CLIP: CRSRCLIPX Position */
+#define LCD_CRSR_CLIP_CRSRCLIPX_Msk (0x3fUL << LCD_CRSR_CLIP_CRSRCLIPX_Pos) /*!< LCD CRSR_CLIP: CRSRCLIPX Mask */
+#define LCD_CRSR_CLIP_CRSRCLIPY_Pos 8 /*!< LCD CRSR_CLIP: CRSRCLIPY Position */
+#define LCD_CRSR_CLIP_CRSRCLIPY_Msk (0x3fUL << LCD_CRSR_CLIP_CRSRCLIPY_Pos) /*!< LCD CRSR_CLIP: CRSRCLIPY Mask */
+
+// ------------------------------------- LCD_CRSR_INTMSK ----------------------------------------
+#define LCD_CRSR_INTMSK_CRSRIM_Pos 0 /*!< LCD CRSR_INTMSK: CRSRIM Position */
+#define LCD_CRSR_INTMSK_CRSRIM_Msk (0x01UL << LCD_CRSR_INTMSK_CRSRIM_Pos) /*!< LCD CRSR_INTMSK: CRSRIM Mask */
+
+// ------------------------------------- LCD_CRSR_INTCLR ----------------------------------------
+#define LCD_CRSR_INTCLR_CRSRIC_Pos 0 /*!< LCD CRSR_INTCLR: CRSRIC Position */
+#define LCD_CRSR_INTCLR_CRSRIC_Msk (0x01UL << LCD_CRSR_INTCLR_CRSRIC_Pos) /*!< LCD CRSR_INTCLR: CRSRIC Mask */
+
+// ------------------------------------- LCD_CRSR_INTRAW ----------------------------------------
+#define LCD_CRSR_INTRAW_CRSRRIS_Pos 0 /*!< LCD CRSR_INTRAW: CRSRRIS Position */
+#define LCD_CRSR_INTRAW_CRSRRIS_Msk (0x01UL << LCD_CRSR_INTRAW_CRSRRIS_Pos) /*!< LCD CRSR_INTRAW: CRSRRIS Mask */
+
+// ------------------------------------ LCD_CRSR_INTSTAT ----------------------------------------
+#define LCD_CRSR_INTSTAT_CRSRMIS_Pos 0 /*!< LCD CRSR_INTSTAT: CRSRMIS Position */
+#define LCD_CRSR_INTSTAT_CRSRMIS_Msk (0x01UL << LCD_CRSR_INTSTAT_CRSRMIS_Pos) /*!< LCD CRSR_INTSTAT: CRSRMIS Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- ETHERNET Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------- ETHERNET_MAC_CONFIG --------------------------------------
+#define ETHERNET_MAC_CONFIG_RE_Pos 2 /*!< ETHERNET MAC_CONFIG: RE Position */
+#define ETHERNET_MAC_CONFIG_RE_Msk (0x01UL << ETHERNET_MAC_CONFIG_RE_Pos) /*!< ETHERNET MAC_CONFIG: RE Mask */
+#define ETHERNET_MAC_CONFIG_TE_Pos 3 /*!< ETHERNET MAC_CONFIG: TE Position */
+#define ETHERNET_MAC_CONFIG_TE_Msk (0x01UL << ETHERNET_MAC_CONFIG_TE_Pos) /*!< ETHERNET MAC_CONFIG: TE Mask */
+#define ETHERNET_MAC_CONFIG_DF_Pos 4 /*!< ETHERNET MAC_CONFIG: DF Position */
+#define ETHERNET_MAC_CONFIG_DF_Msk (0x01UL << ETHERNET_MAC_CONFIG_DF_Pos) /*!< ETHERNET MAC_CONFIG: DF Mask */
+#define ETHERNET_MAC_CONFIG_BL_Pos 5 /*!< ETHERNET MAC_CONFIG: BL Position */
+#define ETHERNET_MAC_CONFIG_BL_Msk (0x03UL << ETHERNET_MAC_CONFIG_BL_Pos) /*!< ETHERNET MAC_CONFIG: BL Mask */
+#define ETHERNET_MAC_CONFIG_ACS_Pos 7 /*!< ETHERNET MAC_CONFIG: ACS Position */
+#define ETHERNET_MAC_CONFIG_ACS_Msk (0x01UL << ETHERNET_MAC_CONFIG_ACS_Pos) /*!< ETHERNET MAC_CONFIG: ACS Mask */
+#define ETHERNET_MAC_CONFIG_DR_Pos 9 /*!< ETHERNET MAC_CONFIG: DR Position */
+#define ETHERNET_MAC_CONFIG_DR_Msk (0x01UL << ETHERNET_MAC_CONFIG_DR_Pos) /*!< ETHERNET MAC_CONFIG: DR Mask */
+#define ETHERNET_MAC_CONFIG_IPC_Pos 10 /*!< ETHERNET MAC_CONFIG: IPC Position */
+#define ETHERNET_MAC_CONFIG_IPC_Msk (0x01UL << ETHERNET_MAC_CONFIG_IPC_Pos) /*!< ETHERNET MAC_CONFIG: IPC Mask */
+#define ETHERNET_MAC_CONFIG_DM_Pos 11 /*!< ETHERNET MAC_CONFIG: DM Position */
+#define ETHERNET_MAC_CONFIG_DM_Msk (0x01UL << ETHERNET_MAC_CONFIG_DM_Pos) /*!< ETHERNET MAC_CONFIG: DM Mask */
+#define ETHERNET_MAC_CONFIG_LM_Pos 12 /*!< ETHERNET MAC_CONFIG: LM Position */
+#define ETHERNET_MAC_CONFIG_LM_Msk (0x01UL << ETHERNET_MAC_CONFIG_LM_Pos) /*!< ETHERNET MAC_CONFIG: LM Mask */
+#define ETHERNET_MAC_CONFIG_DO_Pos 13 /*!< ETHERNET MAC_CONFIG: DO Position */
+#define ETHERNET_MAC_CONFIG_DO_Msk (0x01UL << ETHERNET_MAC_CONFIG_DO_Pos) /*!< ETHERNET MAC_CONFIG: DO Mask */
+#define ETHERNET_MAC_CONFIG_FES_Pos 14 /*!< ETHERNET MAC_CONFIG: FES Position */
+#define ETHERNET_MAC_CONFIG_FES_Msk (0x01UL << ETHERNET_MAC_CONFIG_FES_Pos) /*!< ETHERNET MAC_CONFIG: FES Mask */
+#define ETHERNET_MAC_CONFIG_PS_Pos 15 /*!< ETHERNET MAC_CONFIG: PS Position */
+#define ETHERNET_MAC_CONFIG_PS_Msk (0x01UL << ETHERNET_MAC_CONFIG_PS_Pos) /*!< ETHERNET MAC_CONFIG: PS Mask */
+#define ETHERNET_MAC_CONFIG_DCRS_Pos 16 /*!< ETHERNET MAC_CONFIG: DCRS Position */
+#define ETHERNET_MAC_CONFIG_DCRS_Msk (0x01UL << ETHERNET_MAC_CONFIG_DCRS_Pos) /*!< ETHERNET MAC_CONFIG: DCRS Mask */
+#define ETHERNET_MAC_CONFIG_IFG_Pos 17 /*!< ETHERNET MAC_CONFIG: IFG Position */
+#define ETHERNET_MAC_CONFIG_IFG_Msk (0x07UL << ETHERNET_MAC_CONFIG_IFG_Pos) /*!< ETHERNET MAC_CONFIG: IFG Mask */
+#define ETHERNET_MAC_CONFIG_JE_Pos 20 /*!< ETHERNET MAC_CONFIG: JE Position */
+#define ETHERNET_MAC_CONFIG_JE_Msk (0x01UL << ETHERNET_MAC_CONFIG_JE_Pos) /*!< ETHERNET MAC_CONFIG: JE Mask */
+#define ETHERNET_MAC_CONFIG_JD_Pos 22 /*!< ETHERNET MAC_CONFIG: JD Position */
+#define ETHERNET_MAC_CONFIG_JD_Msk (0x01UL << ETHERNET_MAC_CONFIG_JD_Pos) /*!< ETHERNET MAC_CONFIG: JD Mask */
+#define ETHERNET_MAC_CONFIG_WD_Pos 23 /*!< ETHERNET MAC_CONFIG: WD Position */
+#define ETHERNET_MAC_CONFIG_WD_Msk (0x01UL << ETHERNET_MAC_CONFIG_WD_Pos) /*!< ETHERNET MAC_CONFIG: WD Mask */
+
+// -------------------------------- ETHERNET_MAC_FRAME_FILTER -----------------------------------
+#define ETHERNET_MAC_FRAME_FILTER_PR_Pos 0 /*!< ETHERNET MAC_FRAME_FILTER: PR Position */
+#define ETHERNET_MAC_FRAME_FILTER_PR_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_PR_Pos) /*!< ETHERNET MAC_FRAME_FILTER: PR Mask */
+#define ETHERNET_MAC_FRAME_FILTER_DAIF_Pos 3 /*!< ETHERNET MAC_FRAME_FILTER: DAIF Position */
+#define ETHERNET_MAC_FRAME_FILTER_DAIF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_DAIF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: DAIF Mask */
+#define ETHERNET_MAC_FRAME_FILTER_PM_Pos 4 /*!< ETHERNET MAC_FRAME_FILTER: PM Position */
+#define ETHERNET_MAC_FRAME_FILTER_PM_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_PM_Pos) /*!< ETHERNET MAC_FRAME_FILTER: PM Mask */
+#define ETHERNET_MAC_FRAME_FILTER_DBF_Pos 5 /*!< ETHERNET MAC_FRAME_FILTER: DBF Position */
+#define ETHERNET_MAC_FRAME_FILTER_DBF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_DBF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: DBF Mask */
+#define ETHERNET_MAC_FRAME_FILTER_PCF_Pos 6 /*!< ETHERNET MAC_FRAME_FILTER: PCF Position */
+#define ETHERNET_MAC_FRAME_FILTER_PCF_Msk (0x03UL << ETHERNET_MAC_FRAME_FILTER_PCF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: PCF Mask */
+#define ETHERNET_MAC_FRAME_FILTER_SAIF_Pos 8 /*!< ETHERNET MAC_FRAME_FILTER: SAIF Position */
+#define ETHERNET_MAC_FRAME_FILTER_SAIF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_SAIF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: SAIF Mask */
+#define ETHERNET_MAC_FRAME_FILTER_SAF_Pos 9 /*!< ETHERNET MAC_FRAME_FILTER: SAF Position */
+#define ETHERNET_MAC_FRAME_FILTER_SAF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_SAF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: SAF Mask */
+#define ETHERNET_MAC_FRAME_FILTER_RA_Pos 31 /*!< ETHERNET MAC_FRAME_FILTER: RA Position */
+#define ETHERNET_MAC_FRAME_FILTER_RA_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_RA_Pos) /*!< ETHERNET MAC_FRAME_FILTER: RA Mask */
+
+// ------------------------------- ETHERNET_MAC_HASHTABLE_HIGH ----------------------------------
+#define ETHERNET_MAC_HASHTABLE_HIGH_HTH_Pos 0 /*!< ETHERNET MAC_HASHTABLE_HIGH: HTH Position */
+#define ETHERNET_MAC_HASHTABLE_HIGH_HTH_Msk (0xffffffffUL << ETHERNET_MAC_HASHTABLE_HIGH_HTH_Pos) /*!< ETHERNET MAC_HASHTABLE_HIGH: HTH Mask */
+
+// ------------------------------- ETHERNET_MAC_HASHTABLE_LOW -----------------------------------
+#define ETHERNET_MAC_HASHTABLE_LOW_HTL_Pos 0 /*!< ETHERNET MAC_HASHTABLE_LOW: HTL Position */
+#define ETHERNET_MAC_HASHTABLE_LOW_HTL_Msk (0xffffffffUL << ETHERNET_MAC_HASHTABLE_LOW_HTL_Pos) /*!< ETHERNET MAC_HASHTABLE_LOW: HTL Mask */
+
+// ---------------------------------- ETHERNET_MAC_MII_ADDR -------------------------------------
+#define ETHERNET_MAC_MII_ADDR_GB_Pos 0 /*!< ETHERNET MAC_MII_ADDR: GB Position */
+#define ETHERNET_MAC_MII_ADDR_GB_Msk (0x01UL << ETHERNET_MAC_MII_ADDR_GB_Pos) /*!< ETHERNET MAC_MII_ADDR: GB Mask */
+#define ETHERNET_MAC_MII_ADDR_W_Pos 1 /*!< ETHERNET MAC_MII_ADDR: W Position */
+#define ETHERNET_MAC_MII_ADDR_W_Msk (0x01UL << ETHERNET_MAC_MII_ADDR_W_Pos) /*!< ETHERNET MAC_MII_ADDR: W Mask */
+#define ETHERNET_MAC_MII_ADDR_CR_Pos 2 /*!< ETHERNET MAC_MII_ADDR: CR Position */
+#define ETHERNET_MAC_MII_ADDR_CR_Msk (0x0fUL << ETHERNET_MAC_MII_ADDR_CR_Pos) /*!< ETHERNET MAC_MII_ADDR: CR Mask */
+#define ETHERNET_MAC_MII_ADDR_GR_Pos 6 /*!< ETHERNET MAC_MII_ADDR: GR Position */
+#define ETHERNET_MAC_MII_ADDR_GR_Msk (0x1fUL << ETHERNET_MAC_MII_ADDR_GR_Pos) /*!< ETHERNET MAC_MII_ADDR: GR Mask */
+#define ETHERNET_MAC_MII_ADDR_PA_Pos 11 /*!< ETHERNET MAC_MII_ADDR: PA Position */
+#define ETHERNET_MAC_MII_ADDR_PA_Msk (0x1fUL << ETHERNET_MAC_MII_ADDR_PA_Pos) /*!< ETHERNET MAC_MII_ADDR: PA Mask */
+
+// ---------------------------------- ETHERNET_MAC_MII_DATA -------------------------------------
+#define ETHERNET_MAC_MII_DATA_GD_Pos 0 /*!< ETHERNET MAC_MII_DATA: GD Position */
+#define ETHERNET_MAC_MII_DATA_GD_Msk (0x0000ffffUL << ETHERNET_MAC_MII_DATA_GD_Pos) /*!< ETHERNET MAC_MII_DATA: GD Mask */
+
+// --------------------------------- ETHERNET_MAC_FLOW_CTRL -------------------------------------
+#define ETHERNET_MAC_FLOW_CTRL_FCB_Pos 0 /*!< ETHERNET MAC_FLOW_CTRL: FCB Position */
+#define ETHERNET_MAC_FLOW_CTRL_FCB_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_FCB_Pos) /*!< ETHERNET MAC_FLOW_CTRL: FCB Mask */
+#define ETHERNET_MAC_FLOW_CTRL_TFE_Pos 1 /*!< ETHERNET MAC_FLOW_CTRL: TFE Position */
+#define ETHERNET_MAC_FLOW_CTRL_TFE_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_TFE_Pos) /*!< ETHERNET MAC_FLOW_CTRL: TFE Mask */
+#define ETHERNET_MAC_FLOW_CTRL_RFE_Pos 2 /*!< ETHERNET MAC_FLOW_CTRL: RFE Position */
+#define ETHERNET_MAC_FLOW_CTRL_RFE_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_RFE_Pos) /*!< ETHERNET MAC_FLOW_CTRL: RFE Mask */
+#define ETHERNET_MAC_FLOW_CTRL_UP_Pos 3 /*!< ETHERNET MAC_FLOW_CTRL: UP Position */
+#define ETHERNET_MAC_FLOW_CTRL_UP_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_UP_Pos) /*!< ETHERNET MAC_FLOW_CTRL: UP Mask */
+#define ETHERNET_MAC_FLOW_CTRL_PLT_Pos 4 /*!< ETHERNET MAC_FLOW_CTRL: PLT Position */
+#define ETHERNET_MAC_FLOW_CTRL_PLT_Msk (0x03UL << ETHERNET_MAC_FLOW_CTRL_PLT_Pos) /*!< ETHERNET MAC_FLOW_CTRL: PLT Mask */
+#define ETHERNET_MAC_FLOW_CTRL_DZPQ_Pos 7 /*!< ETHERNET MAC_FLOW_CTRL: DZPQ Position */
+#define ETHERNET_MAC_FLOW_CTRL_DZPQ_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_DZPQ_Pos) /*!< ETHERNET MAC_FLOW_CTRL: DZPQ Mask */
+#define ETHERNET_MAC_FLOW_CTRL_PT_Pos 16 /*!< ETHERNET MAC_FLOW_CTRL: PT Position */
+#define ETHERNET_MAC_FLOW_CTRL_PT_Msk (0x0000ffffUL << ETHERNET_MAC_FLOW_CTRL_PT_Pos) /*!< ETHERNET MAC_FLOW_CTRL: PT Mask */
+
+// ---------------------------------- ETHERNET_MAC_VLAN_TAG -------------------------------------
+#define ETHERNET_MAC_VLAN_TAG_VL_Pos 0 /*!< ETHERNET MAC_VLAN_TAG: VL Position */
+#define ETHERNET_MAC_VLAN_TAG_VL_Msk (0x0000ffffUL << ETHERNET_MAC_VLAN_TAG_VL_Pos) /*!< ETHERNET MAC_VLAN_TAG: VL Mask */
+#define ETHERNET_MAC_VLAN_TAG_ETV_Pos 16 /*!< ETHERNET MAC_VLAN_TAG: ETV Position */
+#define ETHERNET_MAC_VLAN_TAG_ETV_Msk (0x01UL << ETHERNET_MAC_VLAN_TAG_ETV_Pos) /*!< ETHERNET MAC_VLAN_TAG: ETV Mask */
+
+// ----------------------------------- ETHERNET_MAC_DEBUG ---------------------------------------
+#define ETHERNET_MAC_DEBUG_RXIDLESTAT_Pos 0 /*!< ETHERNET MAC_DEBUG: RXIDLESTAT Position */
+#define ETHERNET_MAC_DEBUG_RXIDLESTAT_Msk (0x01UL << ETHERNET_MAC_DEBUG_RXIDLESTAT_Pos) /*!< ETHERNET MAC_DEBUG: RXIDLESTAT Mask */
+#define ETHERNET_MAC_DEBUG_FIFOSTAT0_Pos 1 /*!< ETHERNET MAC_DEBUG: FIFOSTAT0 Position */
+#define ETHERNET_MAC_DEBUG_FIFOSTAT0_Msk (0x03UL << ETHERNET_MAC_DEBUG_FIFOSTAT0_Pos) /*!< ETHERNET MAC_DEBUG: FIFOSTAT0 Mask */
+#define ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Pos 4 /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT1 Position */
+#define ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Msk (0x01UL << ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Pos) /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT1 Mask */
+#define ETHERNET_MAC_DEBUG_RXFIFOSTAT_Pos 5 /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT Position */
+#define ETHERNET_MAC_DEBUG_RXFIFOSTAT_Msk (0x03UL << ETHERNET_MAC_DEBUG_RXFIFOSTAT_Pos) /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT Mask */
+#define ETHERNET_MAC_DEBUG_RXFIFOLVL_Pos 8 /*!< ETHERNET MAC_DEBUG: RXFIFOLVL Position */
+#define ETHERNET_MAC_DEBUG_RXFIFOLVL_Msk (0x03UL << ETHERNET_MAC_DEBUG_RXFIFOLVL_Pos) /*!< ETHERNET MAC_DEBUG: RXFIFOLVL Mask */
+#define ETHERNET_MAC_DEBUG_TXIDLESTAT_Pos 16 /*!< ETHERNET MAC_DEBUG: TXIDLESTAT Position */
+#define ETHERNET_MAC_DEBUG_TXIDLESTAT_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXIDLESTAT_Pos) /*!< ETHERNET MAC_DEBUG: TXIDLESTAT Mask */
+#define ETHERNET_MAC_DEBUG_TXSTAT_Pos 17 /*!< ETHERNET MAC_DEBUG: TXSTAT Position */
+#define ETHERNET_MAC_DEBUG_TXSTAT_Msk (0x03UL << ETHERNET_MAC_DEBUG_TXSTAT_Pos) /*!< ETHERNET MAC_DEBUG: TXSTAT Mask */
+#define ETHERNET_MAC_DEBUG_PAUSE_Pos 19 /*!< ETHERNET MAC_DEBUG: PAUSE Position */
+#define ETHERNET_MAC_DEBUG_PAUSE_Msk (0x01UL << ETHERNET_MAC_DEBUG_PAUSE_Pos) /*!< ETHERNET MAC_DEBUG: PAUSE Mask */
+#define ETHERNET_MAC_DEBUG_TXFIFOSTAT_Pos 20 /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT Position */
+#define ETHERNET_MAC_DEBUG_TXFIFOSTAT_Msk (0x03UL << ETHERNET_MAC_DEBUG_TXFIFOSTAT_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT Mask */
+#define ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Pos 22 /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT1 Position */
+#define ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT1 Mask */
+#define ETHERNET_MAC_DEBUG_TXFIFOLVL_Pos 24 /*!< ETHERNET MAC_DEBUG: TXFIFOLVL Position */
+#define ETHERNET_MAC_DEBUG_TXFIFOLVL_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOLVL_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOLVL Mask */
+#define ETHERNET_MAC_DEBUG_TXFIFOFULL_Pos 25 /*!< ETHERNET MAC_DEBUG: TXFIFOFULL Position */
+#define ETHERNET_MAC_DEBUG_TXFIFOFULL_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOFULL_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOFULL Mask */
+
+// -------------------------------- ETHERNET_MAC_RWAKE_FRFLT ------------------------------------
+#define ETHERNET_MAC_RWAKE_FRFLT_ADDR_Pos 0 /*!< ETHERNET MAC_RWAKE_FRFLT: ADDR Position */
+#define ETHERNET_MAC_RWAKE_FRFLT_ADDR_Msk (0xffffffffUL << ETHERNET_MAC_RWAKE_FRFLT_ADDR_Pos) /*!< ETHERNET MAC_RWAKE_FRFLT: ADDR Mask */
+
+// ------------------------------- ETHERNET_MAC_PMT_CTRL_STAT -----------------------------------
+#define ETHERNET_MAC_PMT_CTRL_STAT_PD_Pos 0 /*!< ETHERNET MAC_PMT_CTRL_STAT: PD Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_PD_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_PD_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: PD Mask */
+#define ETHERNET_MAC_PMT_CTRL_STAT_MPE_Pos 1 /*!< ETHERNET MAC_PMT_CTRL_STAT: MPE Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_MPE_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_MPE_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: MPE Mask */
+#define ETHERNET_MAC_PMT_CTRL_STAT_WFE_Pos 2 /*!< ETHERNET MAC_PMT_CTRL_STAT: WFE Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_WFE_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFE_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: WFE Mask */
+#define ETHERNET_MAC_PMT_CTRL_STAT_MPR_Pos 5 /*!< ETHERNET MAC_PMT_CTRL_STAT: MPR Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_MPR_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_MPR_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: MPR Mask */
+#define ETHERNET_MAC_PMT_CTRL_STAT_WFR_Pos 6 /*!< ETHERNET MAC_PMT_CTRL_STAT: WFR Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_WFR_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFR_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: WFR Mask */
+#define ETHERNET_MAC_PMT_CTRL_STAT_GU_Pos 9 /*!< ETHERNET MAC_PMT_CTRL_STAT: GU Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_GU_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_GU_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: GU Mask */
+#define ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Pos 31 /*!< ETHERNET MAC_PMT_CTRL_STAT: WFFRPR Position */
+#define ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: WFFRPR Mask */
+
+// --------------------------------- ETHERNET_MAC_INTR_MASK -------------------------------------
+#define ETHERNET_MAC_INTR_MASK_PMTMSK_Pos 3 /*!< ETHERNET MAC_INTR_MASK: PMTMSK Position */
+#define ETHERNET_MAC_INTR_MASK_PMTMSK_Msk (0x01UL << ETHERNET_MAC_INTR_MASK_PMTMSK_Pos) /*!< ETHERNET MAC_INTR_MASK: PMTMSK Mask */
+
+// --------------------------------- ETHERNET_MAC_ADDR0_HIGH ------------------------------------
+#define ETHERNET_MAC_ADDR0_HIGH_A47_32_Pos 0 /*!< ETHERNET MAC_ADDR0_HIGH: A47_32 Position */
+#define ETHERNET_MAC_ADDR0_HIGH_A47_32_Msk (0x0000ffffUL << ETHERNET_MAC_ADDR0_HIGH_A47_32_Pos) /*!< ETHERNET MAC_ADDR0_HIGH: A47_32 Mask */
+#define ETHERNET_MAC_ADDR0_HIGH_MO_Pos 31 /*!< ETHERNET MAC_ADDR0_HIGH: MO Position */
+#define ETHERNET_MAC_ADDR0_HIGH_MO_Msk (0x01UL << ETHERNET_MAC_ADDR0_HIGH_MO_Pos) /*!< ETHERNET MAC_ADDR0_HIGH: MO Mask */
+
+// --------------------------------- ETHERNET_MAC_ADDR0_LOW -------------------------------------
+#define ETHERNET_MAC_ADDR0_LOW_A31_0_Pos 0 /*!< ETHERNET MAC_ADDR0_LOW: A31_0 Position */
+#define ETHERNET_MAC_ADDR0_LOW_A31_0_Msk (0xffffffffUL << ETHERNET_MAC_ADDR0_LOW_A31_0_Pos) /*!< ETHERNET MAC_ADDR0_LOW: A31_0 Mask */
+
+// -------------------------------- ETHERNET_MAC_TIMESTP_CTRL -----------------------------------
+#define ETHERNET_MAC_TIMESTP_CTRL_TSENA_Pos 0 /*!< ETHERNET MAC_TIMESTP_CTRL: TSENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Pos 1 /*!< ETHERNET MAC_TIMESTP_CTRL: TSCFUPDT Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSCFUPDT Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Pos 2 /*!< ETHERNET MAC_TIMESTP_CTRL: TSINIT Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSINIT Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Pos 3 /*!< ETHERNET MAC_TIMESTP_CTRL: TSUPDT Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSUPDT Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Pos 4 /*!< ETHERNET MAC_TIMESTP_CTRL: TSTRIG Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSTRIG Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Pos 5 /*!< ETHERNET MAC_TIMESTP_CTRL: TSADDREG Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSADDREG Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Pos 8 /*!< ETHERNET MAC_TIMESTP_CTRL: TSENALL Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSENALL Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Pos 9 /*!< ETHERNET MAC_TIMESTP_CTRL: TSCTRLSSR Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSCTRLSSR Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Pos 10 /*!< ETHERNET MAC_TIMESTP_CTRL: TSVER2ENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSVER2ENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Pos 11 /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Pos 12 /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV6ENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV6ENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Pos 13 /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV4ENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV4ENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Pos 14 /*!< ETHERNET MAC_TIMESTP_CTRL: TSEVNTENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSEVNTENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Pos 15 /*!< ETHERNET MAC_TIMESTP_CTRL: TSMSTRENA Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSMSTRENA Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Pos 16 /*!< ETHERNET MAC_TIMESTP_CTRL: TSCLKTYPE Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Msk (0x03UL << ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSCLKTYPE Mask */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Pos 18 /*!< ETHERNET MAC_TIMESTP_CTRL: TSENMACADDR Position */
+#define ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSENMACADDR Mask */
+
+// --------------------------------- ETHERNET_SUBSECOND_INCR ------------------------------------
+#define ETHERNET_SUBSECOND_INCR_SSINC_Pos 0 /*!< ETHERNET SUBSECOND_INCR: SSINC Position */
+#define ETHERNET_SUBSECOND_INCR_SSINC_Msk (0x000000ffUL << ETHERNET_SUBSECOND_INCR_SSINC_Pos) /*!< ETHERNET SUBSECOND_INCR: SSINC Mask */
+
+// ------------------------------------ ETHERNET_SECONDS ----------------------------------------
+#define ETHERNET_SECONDS_TSS_Pos 0 /*!< ETHERNET SECONDS: TSS Position */
+#define ETHERNET_SECONDS_TSS_Msk (0xffffffffUL << ETHERNET_SECONDS_TSS_Pos) /*!< ETHERNET SECONDS: TSS Mask */
+
+// ---------------------------------- ETHERNET_NANOSECONDS --------------------------------------
+#define ETHERNET_NANOSECONDS_TSSS_Pos 0 /*!< ETHERNET NANOSECONDS: TSSS Position */
+#define ETHERNET_NANOSECONDS_TSSS_Msk (0x7fffffffUL << ETHERNET_NANOSECONDS_TSSS_Pos) /*!< ETHERNET NANOSECONDS: TSSS Mask */
+#define ETHERNET_NANOSECONDS_PSNT_Pos 31 /*!< ETHERNET NANOSECONDS: PSNT Position */
+#define ETHERNET_NANOSECONDS_PSNT_Msk (0x01UL << ETHERNET_NANOSECONDS_PSNT_Pos) /*!< ETHERNET NANOSECONDS: PSNT Mask */
+
+// --------------------------------- ETHERNET_SECONDSUPDATE -------------------------------------
+#define ETHERNET_SECONDSUPDATE_TSS_Pos 0 /*!< ETHERNET SECONDSUPDATE: TSS Position */
+#define ETHERNET_SECONDSUPDATE_TSS_Msk (0xffffffffUL << ETHERNET_SECONDSUPDATE_TSS_Pos) /*!< ETHERNET SECONDSUPDATE: TSS Mask */
+
+// ------------------------------- ETHERNET_NANOSECONDSUPDATE -----------------------------------
+#define ETHERNET_NANOSECONDSUPDATE_TSSS_Pos 0 /*!< ETHERNET NANOSECONDSUPDATE: TSSS Position */
+#define ETHERNET_NANOSECONDSUPDATE_TSSS_Msk (0x7fffffffUL << ETHERNET_NANOSECONDSUPDATE_TSSS_Pos) /*!< ETHERNET NANOSECONDSUPDATE: TSSS Mask */
+#define ETHERNET_NANOSECONDSUPDATE_ADDSUB_Pos 31 /*!< ETHERNET NANOSECONDSUPDATE: ADDSUB Position */
+#define ETHERNET_NANOSECONDSUPDATE_ADDSUB_Msk (0x01UL << ETHERNET_NANOSECONDSUPDATE_ADDSUB_Pos) /*!< ETHERNET NANOSECONDSUPDATE: ADDSUB Mask */
+
+// ------------------------------------- ETHERNET_ADDEND ----------------------------------------
+#define ETHERNET_ADDEND_TSAR_Pos 0 /*!< ETHERNET ADDEND: TSAR Position */
+#define ETHERNET_ADDEND_TSAR_Msk (0xffffffffUL << ETHERNET_ADDEND_TSAR_Pos) /*!< ETHERNET ADDEND: TSAR Mask */
+
+// --------------------------------- ETHERNET_TARGETSECONDS -------------------------------------
+#define ETHERNET_TARGETSECONDS_TSTR_Pos 0 /*!< ETHERNET TARGETSECONDS: TSTR Position */
+#define ETHERNET_TARGETSECONDS_TSTR_Msk (0xffffffffUL << ETHERNET_TARGETSECONDS_TSTR_Pos) /*!< ETHERNET TARGETSECONDS: TSTR Mask */
+
+// ------------------------------- ETHERNET_TARGETNANOSECONDS -----------------------------------
+#define ETHERNET_TARGETNANOSECONDS_TSTR_Pos 0 /*!< ETHERNET TARGETNANOSECONDS: TSTR Position */
+#define ETHERNET_TARGETNANOSECONDS_TSTR_Msk (0x7fffffffUL << ETHERNET_TARGETNANOSECONDS_TSTR_Pos) /*!< ETHERNET TARGETNANOSECONDS: TSTR Mask */
+
+// ------------------------------------ ETHERNET_HIGHWORD ---------------------------------------
+#define ETHERNET_HIGHWORD_TSHWR_Pos 0 /*!< ETHERNET HIGHWORD: TSHWR Position */
+#define ETHERNET_HIGHWORD_TSHWR_Msk (0x0000ffffUL << ETHERNET_HIGHWORD_TSHWR_Pos) /*!< ETHERNET HIGHWORD: TSHWR Mask */
+
+// --------------------------------- ETHERNET_TIMESTAMPSTAT -------------------------------------
+#define ETHERNET_TIMESTAMPSTAT_TSSOVF_Pos 0 /*!< ETHERNET TIMESTAMPSTAT: TSSOVF Position */
+#define ETHERNET_TIMESTAMPSTAT_TSSOVF_Msk (0x01UL << ETHERNET_TIMESTAMPSTAT_TSSOVF_Pos) /*!< ETHERNET TIMESTAMPSTAT: TSSOVF Mask */
+#define ETHERNET_TIMESTAMPSTAT_TSTARGT_Pos 1 /*!< ETHERNET TIMESTAMPSTAT: TSTARGT Position */
+#define ETHERNET_TIMESTAMPSTAT_TSTARGT_Msk (0x01UL << ETHERNET_TIMESTAMPSTAT_TSTARGT_Pos) /*!< ETHERNET TIMESTAMPSTAT: TSTARGT Mask */
+#define ETHERNET_TIMESTAMPSTAT_AUXSS_Pos 2 /*!< ETHERNET TIMESTAMPSTAT: AUXSS Position */
+#define ETHERNET_TIMESTAMPSTAT_AUXSS_Msk (0x01UL << ETHERNET_TIMESTAMPSTAT_AUXSS_Pos) /*!< ETHERNET TIMESTAMPSTAT: AUXSS Mask */
+#define ETHERNET_TIMESTAMPSTAT_ATSSTM_Pos 24 /*!< ETHERNET TIMESTAMPSTAT: ATSSTM Position */
+#define ETHERNET_TIMESTAMPSTAT_ATSSTM_Msk (0x01UL << ETHERNET_TIMESTAMPSTAT_ATSSTM_Pos) /*!< ETHERNET TIMESTAMPSTAT: ATSSTM Mask */
+#define ETHERNET_TIMESTAMPSTAT_ATSNS_Pos 25 /*!< ETHERNET TIMESTAMPSTAT: ATSNS Position */
+#define ETHERNET_TIMESTAMPSTAT_ATSNS_Msk (0x07UL << ETHERNET_TIMESTAMPSTAT_ATSNS_Pos) /*!< ETHERNET TIMESTAMPSTAT: ATSNS Mask */
+
+// ------------------------------------ ETHERNET_PPSCTRL ----------------------------------------
+#define ETHERNET_PPSCTRL_PPSCTRL_Pos 0 /*!< ETHERNET PPSCTRL: PPSCTRL Position */
+#define ETHERNET_PPSCTRL_PPSCTRL_Msk (0x0fUL << ETHERNET_PPSCTRL_PPSCTRL_Pos) /*!< ETHERNET PPSCTRL: PPSCTRL Mask */
+
+// --------------------------------- ETHERNET_AUXNANOSECONDS ------------------------------------
+#define ETHERNET_AUXNANOSECONDS_AUXNS_Pos 0 /*!< ETHERNET AUXNANOSECONDS: AUXNS Position */
+#define ETHERNET_AUXNANOSECONDS_AUXNS_Msk (0xffffffffUL << ETHERNET_AUXNANOSECONDS_AUXNS_Pos) /*!< ETHERNET AUXNANOSECONDS: AUXNS Mask */
+
+// ----------------------------------- ETHERNET_AUXSECONDS --------------------------------------
+#define ETHERNET_AUXSECONDS_AUXS_Pos 0 /*!< ETHERNET AUXSECONDS: AUXS Position */
+#define ETHERNET_AUXSECONDS_AUXS_Msk (0xffffffffUL << ETHERNET_AUXSECONDS_AUXS_Pos) /*!< ETHERNET AUXSECONDS: AUXS Mask */
+
+// ---------------------------------- ETHERNET_DMA_BUS_MODE -------------------------------------
+#define ETHERNET_DMA_BUS_MODE_SWR_Pos 0 /*!< ETHERNET DMA_BUS_MODE: SWR Position */
+#define ETHERNET_DMA_BUS_MODE_SWR_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_SWR_Pos) /*!< ETHERNET DMA_BUS_MODE: SWR Mask */
+#define ETHERNET_DMA_BUS_MODE_DA_Pos 1 /*!< ETHERNET DMA_BUS_MODE: DA Position */
+#define ETHERNET_DMA_BUS_MODE_DA_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_DA_Pos) /*!< ETHERNET DMA_BUS_MODE: DA Mask */
+#define ETHERNET_DMA_BUS_MODE_DSL_Pos 2 /*!< ETHERNET DMA_BUS_MODE: DSL Position */
+#define ETHERNET_DMA_BUS_MODE_DSL_Msk (0x1fUL << ETHERNET_DMA_BUS_MODE_DSL_Pos) /*!< ETHERNET DMA_BUS_MODE: DSL Mask */
+#define ETHERNET_DMA_BUS_MODE_ATDS_Pos 7 /*!< ETHERNET DMA_BUS_MODE: ATDS Position */
+#define ETHERNET_DMA_BUS_MODE_ATDS_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_ATDS_Pos) /*!< ETHERNET DMA_BUS_MODE: ATDS Mask */
+#define ETHERNET_DMA_BUS_MODE_PBL_Pos 8 /*!< ETHERNET DMA_BUS_MODE: PBL Position */
+#define ETHERNET_DMA_BUS_MODE_PBL_Msk (0x3fUL << ETHERNET_DMA_BUS_MODE_PBL_Pos) /*!< ETHERNET DMA_BUS_MODE: PBL Mask */
+#define ETHERNET_DMA_BUS_MODE_PR_Pos 14 /*!< ETHERNET DMA_BUS_MODE: PR Position */
+#define ETHERNET_DMA_BUS_MODE_PR_Msk (0x03UL << ETHERNET_DMA_BUS_MODE_PR_Pos) /*!< ETHERNET DMA_BUS_MODE: PR Mask */
+#define ETHERNET_DMA_BUS_MODE_FB_Pos 16 /*!< ETHERNET DMA_BUS_MODE: FB Position */
+#define ETHERNET_DMA_BUS_MODE_FB_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_FB_Pos) /*!< ETHERNET DMA_BUS_MODE: FB Mask */
+#define ETHERNET_DMA_BUS_MODE_RPBL_Pos 17 /*!< ETHERNET DMA_BUS_MODE: RPBL Position */
+#define ETHERNET_DMA_BUS_MODE_RPBL_Msk (0x3fUL << ETHERNET_DMA_BUS_MODE_RPBL_Pos) /*!< ETHERNET DMA_BUS_MODE: RPBL Mask */
+#define ETHERNET_DMA_BUS_MODE_USP_Pos 23 /*!< ETHERNET DMA_BUS_MODE: USP Position */
+#define ETHERNET_DMA_BUS_MODE_USP_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_USP_Pos) /*!< ETHERNET DMA_BUS_MODE: USP Mask */
+#define ETHERNET_DMA_BUS_MODE_PBL8X_Pos 24 /*!< ETHERNET DMA_BUS_MODE: PBL8X Position */
+#define ETHERNET_DMA_BUS_MODE_PBL8X_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_PBL8X_Pos) /*!< ETHERNET DMA_BUS_MODE: PBL8X Mask */
+#define ETHERNET_DMA_BUS_MODE_AAL_Pos 25 /*!< ETHERNET DMA_BUS_MODE: AAL Position */
+#define ETHERNET_DMA_BUS_MODE_AAL_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_AAL_Pos) /*!< ETHERNET DMA_BUS_MODE: AAL Mask */
+#define ETHERNET_DMA_BUS_MODE_MB_Pos 26 /*!< ETHERNET DMA_BUS_MODE: MB Position */
+#define ETHERNET_DMA_BUS_MODE_MB_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_MB_Pos) /*!< ETHERNET DMA_BUS_MODE: MB Mask */
+#define ETHERNET_DMA_BUS_MODE_TXPR_Pos 27 /*!< ETHERNET DMA_BUS_MODE: TXPR Position */
+#define ETHERNET_DMA_BUS_MODE_TXPR_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_TXPR_Pos) /*!< ETHERNET DMA_BUS_MODE: TXPR Mask */
+
+// ----------------------------- ETHERNET_DMA_TRANS_POLL_DEMAND ---------------------------------
+#define ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Pos 0 /*!< ETHERNET DMA_TRANS_POLL_DEMAND: TPD Position */
+#define ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Msk (0xffffffffUL << ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Pos) /*!< ETHERNET DMA_TRANS_POLL_DEMAND: TPD Mask */
+
+// ------------------------------ ETHERNET_DMA_REC_POLL_DEMAND ----------------------------------
+#define ETHERNET_DMA_REC_POLL_DEMAND_RPD_Pos 0 /*!< ETHERNET DMA_REC_POLL_DEMAND: RPD Position */
+#define ETHERNET_DMA_REC_POLL_DEMAND_RPD_Msk (0xffffffffUL << ETHERNET_DMA_REC_POLL_DEMAND_RPD_Pos) /*!< ETHERNET DMA_REC_POLL_DEMAND: RPD Mask */
+
+// -------------------------------- ETHERNET_DMA_REC_DES_ADDR -----------------------------------
+#define ETHERNET_DMA_REC_DES_ADDR_SRL_Pos 0 /*!< ETHERNET DMA_REC_DES_ADDR: SRL Position */
+#define ETHERNET_DMA_REC_DES_ADDR_SRL_Msk (0xffffffffUL << ETHERNET_DMA_REC_DES_ADDR_SRL_Pos) /*!< ETHERNET DMA_REC_DES_ADDR: SRL Mask */
+
+// ------------------------------- ETHERNET_DMA_TRANS_DES_ADDR ----------------------------------
+#define ETHERNET_DMA_TRANS_DES_ADDR_SRL_Pos 0 /*!< ETHERNET DMA_TRANS_DES_ADDR: SRL Position */
+#define ETHERNET_DMA_TRANS_DES_ADDR_SRL_Msk (0xffffffffUL << ETHERNET_DMA_TRANS_DES_ADDR_SRL_Pos) /*!< ETHERNET DMA_TRANS_DES_ADDR: SRL Mask */
+
+// ------------------------------------ ETHERNET_DMA_STAT ---------------------------------------
+#define ETHERNET_DMA_STAT_TI_Pos 0 /*!< ETHERNET DMA_STAT: TI Position */
+#define ETHERNET_DMA_STAT_TI_Msk (0x01UL << ETHERNET_DMA_STAT_TI_Pos) /*!< ETHERNET DMA_STAT: TI Mask */
+#define ETHERNET_DMA_STAT_TPS_Pos 1 /*!< ETHERNET DMA_STAT: TPS Position */
+#define ETHERNET_DMA_STAT_TPS_Msk (0x01UL << ETHERNET_DMA_STAT_TPS_Pos) /*!< ETHERNET DMA_STAT: TPS Mask */
+#define ETHERNET_DMA_STAT_TU_Pos 2 /*!< ETHERNET DMA_STAT: TU Position */
+#define ETHERNET_DMA_STAT_TU_Msk (0x01UL << ETHERNET_DMA_STAT_TU_Pos) /*!< ETHERNET DMA_STAT: TU Mask */
+#define ETHERNET_DMA_STAT_TJT_Pos 3 /*!< ETHERNET DMA_STAT: TJT Position */
+#define ETHERNET_DMA_STAT_TJT_Msk (0x01UL << ETHERNET_DMA_STAT_TJT_Pos) /*!< ETHERNET DMA_STAT: TJT Mask */
+#define ETHERNET_DMA_STAT_OVF_Pos 4 /*!< ETHERNET DMA_STAT: OVF Position */
+#define ETHERNET_DMA_STAT_OVF_Msk (0x01UL << ETHERNET_DMA_STAT_OVF_Pos) /*!< ETHERNET DMA_STAT: OVF Mask */
+#define ETHERNET_DMA_STAT_UNF_Pos 5 /*!< ETHERNET DMA_STAT: UNF Position */
+#define ETHERNET_DMA_STAT_UNF_Msk (0x01UL << ETHERNET_DMA_STAT_UNF_Pos) /*!< ETHERNET DMA_STAT: UNF Mask */
+#define ETHERNET_DMA_STAT_RI_Pos 6 /*!< ETHERNET DMA_STAT: RI Position */
+#define ETHERNET_DMA_STAT_RI_Msk (0x01UL << ETHERNET_DMA_STAT_RI_Pos) /*!< ETHERNET DMA_STAT: RI Mask */
+#define ETHERNET_DMA_STAT_RU_Pos 7 /*!< ETHERNET DMA_STAT: RU Position */
+#define ETHERNET_DMA_STAT_RU_Msk (0x01UL << ETHERNET_DMA_STAT_RU_Pos) /*!< ETHERNET DMA_STAT: RU Mask */
+#define ETHERNET_DMA_STAT_RPS_Pos 8 /*!< ETHERNET DMA_STAT: RPS Position */
+#define ETHERNET_DMA_STAT_RPS_Msk (0x01UL << ETHERNET_DMA_STAT_RPS_Pos) /*!< ETHERNET DMA_STAT: RPS Mask */
+#define ETHERNET_DMA_STAT_RWT_Pos 9 /*!< ETHERNET DMA_STAT: RWT Position */
+#define ETHERNET_DMA_STAT_RWT_Msk (0x01UL << ETHERNET_DMA_STAT_RWT_Pos) /*!< ETHERNET DMA_STAT: RWT Mask */
+#define ETHERNET_DMA_STAT_ETI_Pos 10 /*!< ETHERNET DMA_STAT: ETI Position */
+#define ETHERNET_DMA_STAT_ETI_Msk (0x01UL << ETHERNET_DMA_STAT_ETI_Pos) /*!< ETHERNET DMA_STAT: ETI Mask */
+#define ETHERNET_DMA_STAT_FBI_Pos 13 /*!< ETHERNET DMA_STAT: FBI Position */
+#define ETHERNET_DMA_STAT_FBI_Msk (0x01UL << ETHERNET_DMA_STAT_FBI_Pos) /*!< ETHERNET DMA_STAT: FBI Mask */
+#define ETHERNET_DMA_STAT_ERI_Pos 14 /*!< ETHERNET DMA_STAT: ERI Position */
+#define ETHERNET_DMA_STAT_ERI_Msk (0x01UL << ETHERNET_DMA_STAT_ERI_Pos) /*!< ETHERNET DMA_STAT: ERI Mask */
+#define ETHERNET_DMA_STAT_AIE_Pos 15 /*!< ETHERNET DMA_STAT: AIE Position */
+#define ETHERNET_DMA_STAT_AIE_Msk (0x01UL << ETHERNET_DMA_STAT_AIE_Pos) /*!< ETHERNET DMA_STAT: AIE Mask */
+#define ETHERNET_DMA_STAT_NIS_Pos 16 /*!< ETHERNET DMA_STAT: NIS Position */
+#define ETHERNET_DMA_STAT_NIS_Msk (0x01UL << ETHERNET_DMA_STAT_NIS_Pos) /*!< ETHERNET DMA_STAT: NIS Mask */
+
+// ---------------------------------- ETHERNET_DMA_OP_MODE --------------------------------------
+#define ETHERNET_DMA_OP_MODE_SR_Pos 1 /*!< ETHERNET DMA_OP_MODE: SR Position */
+#define ETHERNET_DMA_OP_MODE_SR_Msk (0x01UL << ETHERNET_DMA_OP_MODE_SR_Pos) /*!< ETHERNET DMA_OP_MODE: SR Mask */
+#define ETHERNET_DMA_OP_MODE_OSF_Pos 2 /*!< ETHERNET DMA_OP_MODE: OSF Position */
+#define ETHERNET_DMA_OP_MODE_OSF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_OSF_Pos) /*!< ETHERNET DMA_OP_MODE: OSF Mask */
+#define ETHERNET_DMA_OP_MODE_RTC_Pos 3 /*!< ETHERNET DMA_OP_MODE: RTC Position */
+#define ETHERNET_DMA_OP_MODE_RTC_Msk (0x03UL << ETHERNET_DMA_OP_MODE_RTC_Pos) /*!< ETHERNET DMA_OP_MODE: RTC Mask */
+#define ETHERNET_DMA_OP_MODE_FUF_Pos 6 /*!< ETHERNET DMA_OP_MODE: FUF Position */
+#define ETHERNET_DMA_OP_MODE_FUF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_FUF_Pos) /*!< ETHERNET DMA_OP_MODE: FUF Mask */
+#define ETHERNET_DMA_OP_MODE_FEF_Pos 7 /*!< ETHERNET DMA_OP_MODE: FEF Position */
+#define ETHERNET_DMA_OP_MODE_FEF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_FEF_Pos) /*!< ETHERNET DMA_OP_MODE: FEF Mask */
+#define ETHERNET_DMA_OP_MODE_ST_Pos 13 /*!< ETHERNET DMA_OP_MODE: ST Position */
+#define ETHERNET_DMA_OP_MODE_ST_Msk (0x01UL << ETHERNET_DMA_OP_MODE_ST_Pos) /*!< ETHERNET DMA_OP_MODE: ST Mask */
+#define ETHERNET_DMA_OP_MODE_TTC_Pos 14 /*!< ETHERNET DMA_OP_MODE: TTC Position */
+#define ETHERNET_DMA_OP_MODE_TTC_Msk (0x07UL << ETHERNET_DMA_OP_MODE_TTC_Pos) /*!< ETHERNET DMA_OP_MODE: TTC Mask */
+#define ETHERNET_DMA_OP_MODE_FTF_Pos 20 /*!< ETHERNET DMA_OP_MODE: FTF Position */
+#define ETHERNET_DMA_OP_MODE_FTF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_FTF_Pos) /*!< ETHERNET DMA_OP_MODE: FTF Mask */
+#define ETHERNET_DMA_OP_MODE_TSF_Pos 21 /*!< ETHERNET DMA_OP_MODE: TSF Position */
+#define ETHERNET_DMA_OP_MODE_TSF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_TSF_Pos) /*!< ETHERNET DMA_OP_MODE: TSF Mask */
+#define ETHERNET_DMA_OP_MODE_DFF_Pos 24 /*!< ETHERNET DMA_OP_MODE: DFF Position */
+#define ETHERNET_DMA_OP_MODE_DFF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_DFF_Pos) /*!< ETHERNET DMA_OP_MODE: DFF Mask */
+#define ETHERNET_DMA_OP_MODE_RSF_Pos 25 /*!< ETHERNET DMA_OP_MODE: RSF Position */
+#define ETHERNET_DMA_OP_MODE_RSF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_RSF_Pos) /*!< ETHERNET DMA_OP_MODE: RSF Mask */
+#define ETHERNET_DMA_OP_MODE_DT_Pos 26 /*!< ETHERNET DMA_OP_MODE: DT Position */
+#define ETHERNET_DMA_OP_MODE_DT_Msk (0x01UL << ETHERNET_DMA_OP_MODE_DT_Pos) /*!< ETHERNET DMA_OP_MODE: DT Mask */
+
+// ----------------------------------- ETHERNET_DMA_INT_EN --------------------------------------
+#define ETHERNET_DMA_INT_EN_TIE_Pos 0 /*!< ETHERNET DMA_INT_EN: TIE Position */
+#define ETHERNET_DMA_INT_EN_TIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TIE_Pos) /*!< ETHERNET DMA_INT_EN: TIE Mask */
+#define ETHERNET_DMA_INT_EN_TSE_Pos 1 /*!< ETHERNET DMA_INT_EN: TSE Position */
+#define ETHERNET_DMA_INT_EN_TSE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TSE_Pos) /*!< ETHERNET DMA_INT_EN: TSE Mask */
+#define ETHERNET_DMA_INT_EN_TUE_Pos 2 /*!< ETHERNET DMA_INT_EN: TUE Position */
+#define ETHERNET_DMA_INT_EN_TUE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TUE_Pos) /*!< ETHERNET DMA_INT_EN: TUE Mask */
+#define ETHERNET_DMA_INT_EN_TJE_Pos 3 /*!< ETHERNET DMA_INT_EN: TJE Position */
+#define ETHERNET_DMA_INT_EN_TJE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TJE_Pos) /*!< ETHERNET DMA_INT_EN: TJE Mask */
+#define ETHERNET_DMA_INT_EN_OVE_Pos 4 /*!< ETHERNET DMA_INT_EN: OVE Position */
+#define ETHERNET_DMA_INT_EN_OVE_Msk (0x01UL << ETHERNET_DMA_INT_EN_OVE_Pos) /*!< ETHERNET DMA_INT_EN: OVE Mask */
+#define ETHERNET_DMA_INT_EN_UNE_Pos 5 /*!< ETHERNET DMA_INT_EN: UNE Position */
+#define ETHERNET_DMA_INT_EN_UNE_Msk (0x01UL << ETHERNET_DMA_INT_EN_UNE_Pos) /*!< ETHERNET DMA_INT_EN: UNE Mask */
+#define ETHERNET_DMA_INT_EN_RIE_Pos 6 /*!< ETHERNET DMA_INT_EN: RIE Position */
+#define ETHERNET_DMA_INT_EN_RIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RIE_Pos) /*!< ETHERNET DMA_INT_EN: RIE Mask */
+#define ETHERNET_DMA_INT_EN_RUE_Pos 7 /*!< ETHERNET DMA_INT_EN: RUE Position */
+#define ETHERNET_DMA_INT_EN_RUE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RUE_Pos) /*!< ETHERNET DMA_INT_EN: RUE Mask */
+#define ETHERNET_DMA_INT_EN_RSE_Pos 8 /*!< ETHERNET DMA_INT_EN: RSE Position */
+#define ETHERNET_DMA_INT_EN_RSE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RSE_Pos) /*!< ETHERNET DMA_INT_EN: RSE Mask */
+#define ETHERNET_DMA_INT_EN_RWE_Pos 9 /*!< ETHERNET DMA_INT_EN: RWE Position */
+#define ETHERNET_DMA_INT_EN_RWE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RWE_Pos) /*!< ETHERNET DMA_INT_EN: RWE Mask */
+#define ETHERNET_DMA_INT_EN_ETE_Pos 10 /*!< ETHERNET DMA_INT_EN: ETE Position */
+#define ETHERNET_DMA_INT_EN_ETE_Msk (0x01UL << ETHERNET_DMA_INT_EN_ETE_Pos) /*!< ETHERNET DMA_INT_EN: ETE Mask */
+#define ETHERNET_DMA_INT_EN_FBE_Pos 13 /*!< ETHERNET DMA_INT_EN: FBE Position */
+#define ETHERNET_DMA_INT_EN_FBE_Msk (0x01UL << ETHERNET_DMA_INT_EN_FBE_Pos) /*!< ETHERNET DMA_INT_EN: FBE Mask */
+#define ETHERNET_DMA_INT_EN_ERE_Pos 14 /*!< ETHERNET DMA_INT_EN: ERE Position */
+#define ETHERNET_DMA_INT_EN_ERE_Msk (0x01UL << ETHERNET_DMA_INT_EN_ERE_Pos) /*!< ETHERNET DMA_INT_EN: ERE Mask */
+#define ETHERNET_DMA_INT_EN_AIE_Pos 15 /*!< ETHERNET DMA_INT_EN: AIE Position */
+#define ETHERNET_DMA_INT_EN_AIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_AIE_Pos) /*!< ETHERNET DMA_INT_EN: AIE Mask */
+#define ETHERNET_DMA_INT_EN_NIE_Pos 16 /*!< ETHERNET DMA_INT_EN: NIE Position */
+#define ETHERNET_DMA_INT_EN_NIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_NIE_Pos) /*!< ETHERNET DMA_INT_EN: NIE Mask */
+
+// --------------------------------- ETHERNET_DMA_MFRM_BUFOF ------------------------------------
+#define ETHERNET_DMA_MFRM_BUFOF_FMC_Pos 0 /*!< ETHERNET DMA_MFRM_BUFOF: FMC Position */
+#define ETHERNET_DMA_MFRM_BUFOF_FMC_Msk (0x0000ffffUL << ETHERNET_DMA_MFRM_BUFOF_FMC_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: FMC Mask */
+#define ETHERNET_DMA_MFRM_BUFOF_OC_Pos 16 /*!< ETHERNET DMA_MFRM_BUFOF: OC Position */
+#define ETHERNET_DMA_MFRM_BUFOF_OC_Msk (0x01UL << ETHERNET_DMA_MFRM_BUFOF_OC_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: OC Mask */
+#define ETHERNET_DMA_MFRM_BUFOF_FMA_Pos 17 /*!< ETHERNET DMA_MFRM_BUFOF: FMA Position */
+#define ETHERNET_DMA_MFRM_BUFOF_FMA_Msk (0x000007ffUL << ETHERNET_DMA_MFRM_BUFOF_FMA_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: FMA Mask */
+#define ETHERNET_DMA_MFRM_BUFOF_OF_Pos 28 /*!< ETHERNET DMA_MFRM_BUFOF: OF Position */
+#define ETHERNET_DMA_MFRM_BUFOF_OF_Msk (0x01UL << ETHERNET_DMA_MFRM_BUFOF_OF_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: OF Mask */
+
+// -------------------------------- ETHERNET_DMA_REC_INT_WDT ------------------------------------
+#define ETHERNET_DMA_REC_INT_WDT_RIWT_Pos 0 /*!< ETHERNET DMA_REC_INT_WDT: RIWT Position */
+#define ETHERNET_DMA_REC_INT_WDT_RIWT_Msk (0x000000ffUL << ETHERNET_DMA_REC_INT_WDT_RIWT_Pos) /*!< ETHERNET DMA_REC_INT_WDT: RIWT Mask */
+
+// ----------------------------- ETHERNET_DMA_CURHOST_TRANS_DES ---------------------------------
+#define ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Pos 0 /*!< ETHERNET DMA_CURHOST_TRANS_DES: HTD Position */
+#define ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Pos) /*!< ETHERNET DMA_CURHOST_TRANS_DES: HTD Mask */
+
+// ------------------------------ ETHERNET_DMA_CURHOST_REC_DES ----------------------------------
+#define ETHERNET_DMA_CURHOST_REC_DES_HRD_Pos 0 /*!< ETHERNET DMA_CURHOST_REC_DES: HRD Position */
+#define ETHERNET_DMA_CURHOST_REC_DES_HRD_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_REC_DES_HRD_Pos) /*!< ETHERNET DMA_CURHOST_REC_DES: HRD Mask */
+
+// ----------------------------- ETHERNET_DMA_CURHOST_TRANS_BUF ---------------------------------
+#define ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Pos 0 /*!< ETHERNET DMA_CURHOST_TRANS_BUF: HTB Position */
+#define ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Pos) /*!< ETHERNET DMA_CURHOST_TRANS_BUF: HTB Mask */
+
+// ------------------------------ ETHERNET_DMA_CURHOST_REC_BUF ----------------------------------
+#define ETHERNET_DMA_CURHOST_REC_BUF_HRB_Pos 0 /*!< ETHERNET DMA_CURHOST_REC_BUF: HRB Position */
+#define ETHERNET_DMA_CURHOST_REC_BUF_HRB_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_REC_BUF_HRB_Pos) /*!< ETHERNET DMA_CURHOST_REC_BUF: HRB Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- ATIMER Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------- ATIMER_DOWNCOUNTER ---------------------------------------
+#define ATIMER_DOWNCOUNTER_CVAL_Pos 0 /*!< ATIMER DOWNCOUNTER: CVAL Position */
+#define ATIMER_DOWNCOUNTER_CVAL_Msk (0x0000ffffUL << ATIMER_DOWNCOUNTER_CVAL_Pos) /*!< ATIMER DOWNCOUNTER: CVAL Mask */
+
+// -------------------------------------- ATIMER_PRESET -----------------------------------------
+#define ATIMER_PRESET_PRESETVAL_Pos 0 /*!< ATIMER PRESET: PRESETVAL Position */
+#define ATIMER_PRESET_PRESETVAL_Msk (0x0000ffffUL << ATIMER_PRESET_PRESETVAL_Pos) /*!< ATIMER PRESET: PRESETVAL Mask */
+
+// -------------------------------------- ATIMER_CLR_EN -----------------------------------------
+#define ATIMER_CLR_EN_CLR_EN_Pos 0 /*!< ATIMER CLR_EN: CLR_EN Position */
+#define ATIMER_CLR_EN_CLR_EN_Msk (0x01UL << ATIMER_CLR_EN_CLR_EN_Pos) /*!< ATIMER CLR_EN: CLR_EN Mask */
+
+// -------------------------------------- ATIMER_SET_EN -----------------------------------------
+#define ATIMER_SET_EN_SET_EN_Pos 0 /*!< ATIMER SET_EN: SET_EN Position */
+#define ATIMER_SET_EN_SET_EN_Msk (0x01UL << ATIMER_SET_EN_SET_EN_Pos) /*!< ATIMER SET_EN: SET_EN Mask */
+
+// -------------------------------------- ATIMER_STATUS -----------------------------------------
+#define ATIMER_STATUS_STAT_Pos 0 /*!< ATIMER STATUS: STAT Position */
+#define ATIMER_STATUS_STAT_Msk (0x01UL << ATIMER_STATUS_STAT_Pos) /*!< ATIMER STATUS: STAT Mask */
+
+// -------------------------------------- ATIMER_ENABLE -----------------------------------------
+#define ATIMER_ENABLE_EN_Pos 0 /*!< ATIMER ENABLE: EN Position */
+#define ATIMER_ENABLE_EN_Msk (0x01UL << ATIMER_ENABLE_EN_Pos) /*!< ATIMER ENABLE: EN Mask */
+
+// ------------------------------------- ATIMER_CLR_STAT ----------------------------------------
+#define ATIMER_CLR_STAT_CSTAT_Pos 0 /*!< ATIMER CLR_STAT: CSTAT Position */
+#define ATIMER_CLR_STAT_CSTAT_Msk (0x01UL << ATIMER_CLR_STAT_CSTAT_Pos) /*!< ATIMER CLR_STAT: CSTAT Mask */
+
+// ------------------------------------- ATIMER_SET_STAT ----------------------------------------
+#define ATIMER_SET_STAT_SSTAT_Pos 0 /*!< ATIMER SET_STAT: SSTAT Position */
+#define ATIMER_SET_STAT_SSTAT_Msk (0x01UL << ATIMER_SET_STAT_SSTAT_Pos) /*!< ATIMER SET_STAT: SSTAT Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- REGFILE Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ------------------------------------ REGFILE_REGFILE0 ----------------------------------------
+#define REGFILE_REGFILE0_REGVAL_Pos 0 /*!< REGFILE REGFILE0: REGVAL Position */
+#define REGFILE_REGFILE0_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE0_REGVAL_Pos) /*!< REGFILE REGFILE0: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE1 ----------------------------------------
+#define REGFILE_REGFILE1_REGVAL_Pos 0 /*!< REGFILE REGFILE1: REGVAL Position */
+#define REGFILE_REGFILE1_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE1_REGVAL_Pos) /*!< REGFILE REGFILE1: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE2 ----------------------------------------
+#define REGFILE_REGFILE2_REGVAL_Pos 0 /*!< REGFILE REGFILE2: REGVAL Position */
+#define REGFILE_REGFILE2_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE2_REGVAL_Pos) /*!< REGFILE REGFILE2: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE3 ----------------------------------------
+#define REGFILE_REGFILE3_REGVAL_Pos 0 /*!< REGFILE REGFILE3: REGVAL Position */
+#define REGFILE_REGFILE3_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE3_REGVAL_Pos) /*!< REGFILE REGFILE3: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE4 ----------------------------------------
+#define REGFILE_REGFILE4_REGVAL_Pos 0 /*!< REGFILE REGFILE4: REGVAL Position */
+#define REGFILE_REGFILE4_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE4_REGVAL_Pos) /*!< REGFILE REGFILE4: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE5 ----------------------------------------
+#define REGFILE_REGFILE5_REGVAL_Pos 0 /*!< REGFILE REGFILE5: REGVAL Position */
+#define REGFILE_REGFILE5_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE5_REGVAL_Pos) /*!< REGFILE REGFILE5: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE6 ----------------------------------------
+#define REGFILE_REGFILE6_REGVAL_Pos 0 /*!< REGFILE REGFILE6: REGVAL Position */
+#define REGFILE_REGFILE6_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE6_REGVAL_Pos) /*!< REGFILE REGFILE6: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE7 ----------------------------------------
+#define REGFILE_REGFILE7_REGVAL_Pos 0 /*!< REGFILE REGFILE7: REGVAL Position */
+#define REGFILE_REGFILE7_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE7_REGVAL_Pos) /*!< REGFILE REGFILE7: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE8 ----------------------------------------
+#define REGFILE_REGFILE8_REGVAL_Pos 0 /*!< REGFILE REGFILE8: REGVAL Position */
+#define REGFILE_REGFILE8_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE8_REGVAL_Pos) /*!< REGFILE REGFILE8: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE9 ----------------------------------------
+#define REGFILE_REGFILE9_REGVAL_Pos 0 /*!< REGFILE REGFILE9: REGVAL Position */
+#define REGFILE_REGFILE9_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE9_REGVAL_Pos) /*!< REGFILE REGFILE9: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE10 ---------------------------------------
+#define REGFILE_REGFILE10_REGVAL_Pos 0 /*!< REGFILE REGFILE10: REGVAL Position */
+#define REGFILE_REGFILE10_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE10_REGVAL_Pos) /*!< REGFILE REGFILE10: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE11 ---------------------------------------
+#define REGFILE_REGFILE11_REGVAL_Pos 0 /*!< REGFILE REGFILE11: REGVAL Position */
+#define REGFILE_REGFILE11_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE11_REGVAL_Pos) /*!< REGFILE REGFILE11: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE12 ---------------------------------------
+#define REGFILE_REGFILE12_REGVAL_Pos 0 /*!< REGFILE REGFILE12: REGVAL Position */
+#define REGFILE_REGFILE12_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE12_REGVAL_Pos) /*!< REGFILE REGFILE12: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE13 ---------------------------------------
+#define REGFILE_REGFILE13_REGVAL_Pos 0 /*!< REGFILE REGFILE13: REGVAL Position */
+#define REGFILE_REGFILE13_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE13_REGVAL_Pos) /*!< REGFILE REGFILE13: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE14 ---------------------------------------
+#define REGFILE_REGFILE14_REGVAL_Pos 0 /*!< REGFILE REGFILE14: REGVAL Position */
+#define REGFILE_REGFILE14_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE14_REGVAL_Pos) /*!< REGFILE REGFILE14: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE15 ---------------------------------------
+#define REGFILE_REGFILE15_REGVAL_Pos 0 /*!< REGFILE REGFILE15: REGVAL Position */
+#define REGFILE_REGFILE15_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE15_REGVAL_Pos) /*!< REGFILE REGFILE15: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE16 ---------------------------------------
+#define REGFILE_REGFILE16_REGVAL_Pos 0 /*!< REGFILE REGFILE16: REGVAL Position */
+#define REGFILE_REGFILE16_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE16_REGVAL_Pos) /*!< REGFILE REGFILE16: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE17 ---------------------------------------
+#define REGFILE_REGFILE17_REGVAL_Pos 0 /*!< REGFILE REGFILE17: REGVAL Position */
+#define REGFILE_REGFILE17_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE17_REGVAL_Pos) /*!< REGFILE REGFILE17: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE18 ---------------------------------------
+#define REGFILE_REGFILE18_REGVAL_Pos 0 /*!< REGFILE REGFILE18: REGVAL Position */
+#define REGFILE_REGFILE18_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE18_REGVAL_Pos) /*!< REGFILE REGFILE18: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE19 ---------------------------------------
+#define REGFILE_REGFILE19_REGVAL_Pos 0 /*!< REGFILE REGFILE19: REGVAL Position */
+#define REGFILE_REGFILE19_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE19_REGVAL_Pos) /*!< REGFILE REGFILE19: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE20 ---------------------------------------
+#define REGFILE_REGFILE20_REGVAL_Pos 0 /*!< REGFILE REGFILE20: REGVAL Position */
+#define REGFILE_REGFILE20_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE20_REGVAL_Pos) /*!< REGFILE REGFILE20: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE21 ---------------------------------------
+#define REGFILE_REGFILE21_REGVAL_Pos 0 /*!< REGFILE REGFILE21: REGVAL Position */
+#define REGFILE_REGFILE21_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE21_REGVAL_Pos) /*!< REGFILE REGFILE21: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE22 ---------------------------------------
+#define REGFILE_REGFILE22_REGVAL_Pos 0 /*!< REGFILE REGFILE22: REGVAL Position */
+#define REGFILE_REGFILE22_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE22_REGVAL_Pos) /*!< REGFILE REGFILE22: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE23 ---------------------------------------
+#define REGFILE_REGFILE23_REGVAL_Pos 0 /*!< REGFILE REGFILE23: REGVAL Position */
+#define REGFILE_REGFILE23_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE23_REGVAL_Pos) /*!< REGFILE REGFILE23: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE24 ---------------------------------------
+#define REGFILE_REGFILE24_REGVAL_Pos 0 /*!< REGFILE REGFILE24: REGVAL Position */
+#define REGFILE_REGFILE24_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE24_REGVAL_Pos) /*!< REGFILE REGFILE24: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE25 ---------------------------------------
+#define REGFILE_REGFILE25_REGVAL_Pos 0 /*!< REGFILE REGFILE25: REGVAL Position */
+#define REGFILE_REGFILE25_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE25_REGVAL_Pos) /*!< REGFILE REGFILE25: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE26 ---------------------------------------
+#define REGFILE_REGFILE26_REGVAL_Pos 0 /*!< REGFILE REGFILE26: REGVAL Position */
+#define REGFILE_REGFILE26_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE26_REGVAL_Pos) /*!< REGFILE REGFILE26: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE27 ---------------------------------------
+#define REGFILE_REGFILE27_REGVAL_Pos 0 /*!< REGFILE REGFILE27: REGVAL Position */
+#define REGFILE_REGFILE27_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE27_REGVAL_Pos) /*!< REGFILE REGFILE27: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE28 ---------------------------------------
+#define REGFILE_REGFILE28_REGVAL_Pos 0 /*!< REGFILE REGFILE28: REGVAL Position */
+#define REGFILE_REGFILE28_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE28_REGVAL_Pos) /*!< REGFILE REGFILE28: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE29 ---------------------------------------
+#define REGFILE_REGFILE29_REGVAL_Pos 0 /*!< REGFILE REGFILE29: REGVAL Position */
+#define REGFILE_REGFILE29_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE29_REGVAL_Pos) /*!< REGFILE REGFILE29: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE30 ---------------------------------------
+#define REGFILE_REGFILE30_REGVAL_Pos 0 /*!< REGFILE REGFILE30: REGVAL Position */
+#define REGFILE_REGFILE30_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE30_REGVAL_Pos) /*!< REGFILE REGFILE30: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE31 ---------------------------------------
+#define REGFILE_REGFILE31_REGVAL_Pos 0 /*!< REGFILE REGFILE31: REGVAL Position */
+#define REGFILE_REGFILE31_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE31_REGVAL_Pos) /*!< REGFILE REGFILE31: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE32 ---------------------------------------
+#define REGFILE_REGFILE32_REGVAL_Pos 0 /*!< REGFILE REGFILE32: REGVAL Position */
+#define REGFILE_REGFILE32_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE32_REGVAL_Pos) /*!< REGFILE REGFILE32: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE33 ---------------------------------------
+#define REGFILE_REGFILE33_REGVAL_Pos 0 /*!< REGFILE REGFILE33: REGVAL Position */
+#define REGFILE_REGFILE33_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE33_REGVAL_Pos) /*!< REGFILE REGFILE33: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE34 ---------------------------------------
+#define REGFILE_REGFILE34_REGVAL_Pos 0 /*!< REGFILE REGFILE34: REGVAL Position */
+#define REGFILE_REGFILE34_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE34_REGVAL_Pos) /*!< REGFILE REGFILE34: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE35 ---------------------------------------
+#define REGFILE_REGFILE35_REGVAL_Pos 0 /*!< REGFILE REGFILE35: REGVAL Position */
+#define REGFILE_REGFILE35_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE35_REGVAL_Pos) /*!< REGFILE REGFILE35: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE36 ---------------------------------------
+#define REGFILE_REGFILE36_REGVAL_Pos 0 /*!< REGFILE REGFILE36: REGVAL Position */
+#define REGFILE_REGFILE36_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE36_REGVAL_Pos) /*!< REGFILE REGFILE36: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE37 ---------------------------------------
+#define REGFILE_REGFILE37_REGVAL_Pos 0 /*!< REGFILE REGFILE37: REGVAL Position */
+#define REGFILE_REGFILE37_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE37_REGVAL_Pos) /*!< REGFILE REGFILE37: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE38 ---------------------------------------
+#define REGFILE_REGFILE38_REGVAL_Pos 0 /*!< REGFILE REGFILE38: REGVAL Position */
+#define REGFILE_REGFILE38_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE38_REGVAL_Pos) /*!< REGFILE REGFILE38: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE39 ---------------------------------------
+#define REGFILE_REGFILE39_REGVAL_Pos 0 /*!< REGFILE REGFILE39: REGVAL Position */
+#define REGFILE_REGFILE39_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE39_REGVAL_Pos) /*!< REGFILE REGFILE39: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE40 ---------------------------------------
+#define REGFILE_REGFILE40_REGVAL_Pos 0 /*!< REGFILE REGFILE40: REGVAL Position */
+#define REGFILE_REGFILE40_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE40_REGVAL_Pos) /*!< REGFILE REGFILE40: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE41 ---------------------------------------
+#define REGFILE_REGFILE41_REGVAL_Pos 0 /*!< REGFILE REGFILE41: REGVAL Position */
+#define REGFILE_REGFILE41_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE41_REGVAL_Pos) /*!< REGFILE REGFILE41: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE42 ---------------------------------------
+#define REGFILE_REGFILE42_REGVAL_Pos 0 /*!< REGFILE REGFILE42: REGVAL Position */
+#define REGFILE_REGFILE42_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE42_REGVAL_Pos) /*!< REGFILE REGFILE42: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE43 ---------------------------------------
+#define REGFILE_REGFILE43_REGVAL_Pos 0 /*!< REGFILE REGFILE43: REGVAL Position */
+#define REGFILE_REGFILE43_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE43_REGVAL_Pos) /*!< REGFILE REGFILE43: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE44 ---------------------------------------
+#define REGFILE_REGFILE44_REGVAL_Pos 0 /*!< REGFILE REGFILE44: REGVAL Position */
+#define REGFILE_REGFILE44_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE44_REGVAL_Pos) /*!< REGFILE REGFILE44: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE45 ---------------------------------------
+#define REGFILE_REGFILE45_REGVAL_Pos 0 /*!< REGFILE REGFILE45: REGVAL Position */
+#define REGFILE_REGFILE45_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE45_REGVAL_Pos) /*!< REGFILE REGFILE45: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE46 ---------------------------------------
+#define REGFILE_REGFILE46_REGVAL_Pos 0 /*!< REGFILE REGFILE46: REGVAL Position */
+#define REGFILE_REGFILE46_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE46_REGVAL_Pos) /*!< REGFILE REGFILE46: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE47 ---------------------------------------
+#define REGFILE_REGFILE47_REGVAL_Pos 0 /*!< REGFILE REGFILE47: REGVAL Position */
+#define REGFILE_REGFILE47_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE47_REGVAL_Pos) /*!< REGFILE REGFILE47: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE48 ---------------------------------------
+#define REGFILE_REGFILE48_REGVAL_Pos 0 /*!< REGFILE REGFILE48: REGVAL Position */
+#define REGFILE_REGFILE48_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE48_REGVAL_Pos) /*!< REGFILE REGFILE48: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE49 ---------------------------------------
+#define REGFILE_REGFILE49_REGVAL_Pos 0 /*!< REGFILE REGFILE49: REGVAL Position */
+#define REGFILE_REGFILE49_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE49_REGVAL_Pos) /*!< REGFILE REGFILE49: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE50 ---------------------------------------
+#define REGFILE_REGFILE50_REGVAL_Pos 0 /*!< REGFILE REGFILE50: REGVAL Position */
+#define REGFILE_REGFILE50_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE50_REGVAL_Pos) /*!< REGFILE REGFILE50: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE51 ---------------------------------------
+#define REGFILE_REGFILE51_REGVAL_Pos 0 /*!< REGFILE REGFILE51: REGVAL Position */
+#define REGFILE_REGFILE51_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE51_REGVAL_Pos) /*!< REGFILE REGFILE51: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE52 ---------------------------------------
+#define REGFILE_REGFILE52_REGVAL_Pos 0 /*!< REGFILE REGFILE52: REGVAL Position */
+#define REGFILE_REGFILE52_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE52_REGVAL_Pos) /*!< REGFILE REGFILE52: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE53 ---------------------------------------
+#define REGFILE_REGFILE53_REGVAL_Pos 0 /*!< REGFILE REGFILE53: REGVAL Position */
+#define REGFILE_REGFILE53_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE53_REGVAL_Pos) /*!< REGFILE REGFILE53: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE54 ---------------------------------------
+#define REGFILE_REGFILE54_REGVAL_Pos 0 /*!< REGFILE REGFILE54: REGVAL Position */
+#define REGFILE_REGFILE54_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE54_REGVAL_Pos) /*!< REGFILE REGFILE54: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE55 ---------------------------------------
+#define REGFILE_REGFILE55_REGVAL_Pos 0 /*!< REGFILE REGFILE55: REGVAL Position */
+#define REGFILE_REGFILE55_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE55_REGVAL_Pos) /*!< REGFILE REGFILE55: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE56 ---------------------------------------
+#define REGFILE_REGFILE56_REGVAL_Pos 0 /*!< REGFILE REGFILE56: REGVAL Position */
+#define REGFILE_REGFILE56_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE56_REGVAL_Pos) /*!< REGFILE REGFILE56: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE57 ---------------------------------------
+#define REGFILE_REGFILE57_REGVAL_Pos 0 /*!< REGFILE REGFILE57: REGVAL Position */
+#define REGFILE_REGFILE57_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE57_REGVAL_Pos) /*!< REGFILE REGFILE57: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE58 ---------------------------------------
+#define REGFILE_REGFILE58_REGVAL_Pos 0 /*!< REGFILE REGFILE58: REGVAL Position */
+#define REGFILE_REGFILE58_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE58_REGVAL_Pos) /*!< REGFILE REGFILE58: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE59 ---------------------------------------
+#define REGFILE_REGFILE59_REGVAL_Pos 0 /*!< REGFILE REGFILE59: REGVAL Position */
+#define REGFILE_REGFILE59_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE59_REGVAL_Pos) /*!< REGFILE REGFILE59: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE60 ---------------------------------------
+#define REGFILE_REGFILE60_REGVAL_Pos 0 /*!< REGFILE REGFILE60: REGVAL Position */
+#define REGFILE_REGFILE60_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE60_REGVAL_Pos) /*!< REGFILE REGFILE60: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE61 ---------------------------------------
+#define REGFILE_REGFILE61_REGVAL_Pos 0 /*!< REGFILE REGFILE61: REGVAL Position */
+#define REGFILE_REGFILE61_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE61_REGVAL_Pos) /*!< REGFILE REGFILE61: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE62 ---------------------------------------
+#define REGFILE_REGFILE62_REGVAL_Pos 0 /*!< REGFILE REGFILE62: REGVAL Position */
+#define REGFILE_REGFILE62_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE62_REGVAL_Pos) /*!< REGFILE REGFILE62: REGVAL Mask */
+
+// ------------------------------------ REGFILE_REGFILE63 ---------------------------------------
+#define REGFILE_REGFILE63_REGVAL_Pos 0 /*!< REGFILE REGFILE63: REGVAL Position */
+#define REGFILE_REGFILE63_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE63_REGVAL_Pos) /*!< REGFILE REGFILE63: REGVAL Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- PMC Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------- PMC_PD0_SLEEP0_HW_ENA -------------------------------------
+#define PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Pos 0 /*!< PMC PD0_SLEEP0_HW_ENA: ENA_EVENT0 Position */
+#define PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Msk (0x01UL << PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Pos) /*!< PMC PD0_SLEEP0_HW_ENA: ENA_EVENT0 Mask */
+
+// ----------------------------------- PMC_PD0_SLEEP0_MODE --------------------------------------
+#define PMC_PD0_SLEEP0_MODE_PWR_STATE_Pos 0 /*!< PMC PD0_SLEEP0_MODE: PWR_STATE Position */
+#define PMC_PD0_SLEEP0_MODE_PWR_STATE_Msk (0xffffffffUL << PMC_PD0_SLEEP0_MODE_PWR_STATE_Pos) /*!< PMC PD0_SLEEP0_MODE: PWR_STATE Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- CREG Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------- CREG_IRCTRM ------------------------------------------
+#define CREG_IRCTRM_TRM_Pos 0 /*!< CREG IRCTRM: TRM Position */
+#define CREG_IRCTRM_TRM_Msk (0x00000fffUL << CREG_IRCTRM_TRM_Pos) /*!< CREG IRCTRM: TRM Mask */
+
+// --------------------------------------- CREG_CREG0 -------------------------------------------
+#define CREG_CREG0_EN1KHZ_Pos 0 /*!< CREG CREG0: EN1KHZ Position */
+#define CREG_CREG0_EN1KHZ_Msk (0x01UL << CREG_CREG0_EN1KHZ_Pos) /*!< CREG CREG0: EN1KHZ Mask */
+#define CREG_CREG0_EN32KHZ_Pos 1 /*!< CREG CREG0: EN32KHZ Position */
+#define CREG_CREG0_EN32KHZ_Msk (0x01UL << CREG_CREG0_EN32KHZ_Pos) /*!< CREG CREG0: EN32KHZ Mask */
+#define CREG_CREG0_RESET32KHZ_Pos 2 /*!< CREG CREG0: RESET32KHZ Position */
+#define CREG_CREG0_RESET32KHZ_Msk (0x01UL << CREG_CREG0_RESET32KHZ_Pos) /*!< CREG CREG0: RESET32KHZ Mask */
+#define CREG_CREG0_32KHZPD_Pos 3 /*!< CREG CREG0: 32KHZPD Position */
+#define CREG_CREG0_32KHZPD_Msk (0x01UL << CREG_CREG0_32KHZPD_Pos) /*!< CREG CREG0: 32KHZPD Mask */
+#define CREG_CREG0_USB0PHY_Pos 5 /*!< CREG CREG0: USB0PHY Position */
+#define CREG_CREG0_USB0PHY_Msk (0x01UL << CREG_CREG0_USB0PHY_Pos) /*!< CREG CREG0: USB0PHY Mask */
+#define CREG_CREG0_ALARMCTRL_Pos 6 /*!< CREG CREG0: ALARMCTRL Position */
+#define CREG_CREG0_ALARMCTRL_Msk (0x03UL << CREG_CREG0_ALARMCTRL_Pos) /*!< CREG CREG0: ALARMCTRL Mask */
+#define CREG_CREG0_BODLVL1_Pos 8 /*!< CREG CREG0: BODLVL1 Position */
+#define CREG_CREG0_BODLVL1_Msk (0x03UL << CREG_CREG0_BODLVL1_Pos) /*!< CREG CREG0: BODLVL1 Mask */
+#define CREG_CREG0_BODLVL2_Pos 10 /*!< CREG CREG0: BODLVL2 Position */
+#define CREG_CREG0_BODLVL2_Msk (0x03UL << CREG_CREG0_BODLVL2_Pos) /*!< CREG CREG0: BODLVL2 Mask */
+#define CREG_CREG0_WAKEUP0CTRL_Pos 14 /*!< CREG CREG0: WAKEUP0CTRL Position */
+#define CREG_CREG0_WAKEUP0CTRL_Msk (0x03UL << CREG_CREG0_WAKEUP0CTRL_Pos) /*!< CREG CREG0: WAKEUP0CTRL Mask */
+#define CREG_CREG0_WAKEUP1CTRL_Pos 16 /*!< CREG CREG0: WAKEUP1CTRL Position */
+#define CREG_CREG0_WAKEUP1CTRL_Msk (0x03UL << CREG_CREG0_WAKEUP1CTRL_Pos) /*!< CREG CREG0: WAKEUP1CTRL Mask */
+
+// -------------------------------------- CREG_M4MEMMAP -----------------------------------------
+#define CREG_M4MEMMAP_M4MAP_Pos 12 /*!< CREG M4MEMMAP: M4MAP Position */
+#define CREG_M4MEMMAP_M4MAP_Msk (0x000fffffUL << CREG_M4MEMMAP_M4MAP_Pos) /*!< CREG M4MEMMAP: M4MAP Mask */
+
+// --------------------------------------- CREG_CREG5 -------------------------------------------
+#define CREG_CREG5_M4TAPSEL_Pos 6 /*!< CREG CREG5: M4TAPSEL Position */
+#define CREG_CREG5_M4TAPSEL_Msk (0x01UL << CREG_CREG5_M4TAPSEL_Pos) /*!< CREG CREG5: M4TAPSEL Mask */
+
+// --------------------------------------- CREG_DMAMUX ------------------------------------------
+#define CREG_DMAMUX_DMAMUXCH0_Pos 0 /*!< CREG DMAMUX: DMAMUXCH0 Position */
+#define CREG_DMAMUX_DMAMUXCH0_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH0_Pos) /*!< CREG DMAMUX: DMAMUXCH0 Mask */
+#define CREG_DMAMUX_DMAMUXCH1_Pos 2 /*!< CREG DMAMUX: DMAMUXCH1 Position */
+#define CREG_DMAMUX_DMAMUXCH1_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH1_Pos) /*!< CREG DMAMUX: DMAMUXCH1 Mask */
+#define CREG_DMAMUX_DMAMUXCH2_Pos 4 /*!< CREG DMAMUX: DMAMUXCH2 Position */
+#define CREG_DMAMUX_DMAMUXCH2_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH2_Pos) /*!< CREG DMAMUX: DMAMUXCH2 Mask */
+#define CREG_DMAMUX_DMAMUXCH3_Pos 6 /*!< CREG DMAMUX: DMAMUXCH3 Position */
+#define CREG_DMAMUX_DMAMUXCH3_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH3_Pos) /*!< CREG DMAMUX: DMAMUXCH3 Mask */
+#define CREG_DMAMUX_DMAMUXCH4_Pos 8 /*!< CREG DMAMUX: DMAMUXCH4 Position */
+#define CREG_DMAMUX_DMAMUXCH4_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH4_Pos) /*!< CREG DMAMUX: DMAMUXCH4 Mask */
+#define CREG_DMAMUX_DMAMUXCH5_Pos 10 /*!< CREG DMAMUX: DMAMUXCH5 Position */
+#define CREG_DMAMUX_DMAMUXCH5_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH5_Pos) /*!< CREG DMAMUX: DMAMUXCH5 Mask */
+#define CREG_DMAMUX_DMAMUXCH6_Pos 12 /*!< CREG DMAMUX: DMAMUXCH6 Position */
+#define CREG_DMAMUX_DMAMUXCH6_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH6_Pos) /*!< CREG DMAMUX: DMAMUXCH6 Mask */
+#define CREG_DMAMUX_DMAMUXCH7_Pos 14 /*!< CREG DMAMUX: DMAMUXCH7 Position */
+#define CREG_DMAMUX_DMAMUXCH7_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH7_Pos) /*!< CREG DMAMUX: DMAMUXCH7 Mask */
+#define CREG_DMAMUX_DMAMUXCH8_Pos 16 /*!< CREG DMAMUX: DMAMUXCH8 Position */
+#define CREG_DMAMUX_DMAMUXCH8_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH8_Pos) /*!< CREG DMAMUX: DMAMUXCH8 Mask */
+#define CREG_DMAMUX_DMAMUXCH9_Pos 18 /*!< CREG DMAMUX: DMAMUXCH9 Position */
+#define CREG_DMAMUX_DMAMUXCH9_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH9_Pos) /*!< CREG DMAMUX: DMAMUXCH9 Mask */
+#define CREG_DMAMUX_DMAMUXCH10_Pos 20 /*!< CREG DMAMUX: DMAMUXCH10 Position */
+#define CREG_DMAMUX_DMAMUXCH10_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH10_Pos) /*!< CREG DMAMUX: DMAMUXCH10 Mask */
+#define CREG_DMAMUX_DMAMUXCH11_Pos 22 /*!< CREG DMAMUX: DMAMUXCH11 Position */
+#define CREG_DMAMUX_DMAMUXCH11_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH11_Pos) /*!< CREG DMAMUX: DMAMUXCH11 Mask */
+#define CREG_DMAMUX_DMAMUXCH12_Pos 24 /*!< CREG DMAMUX: DMAMUXCH12 Position */
+#define CREG_DMAMUX_DMAMUXCH12_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH12_Pos) /*!< CREG DMAMUX: DMAMUXCH12 Mask */
+#define CREG_DMAMUX_DMAMUXCH13_Pos 26 /*!< CREG DMAMUX: DMAMUXCH13 Position */
+#define CREG_DMAMUX_DMAMUXCH13_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH13_Pos) /*!< CREG DMAMUX: DMAMUXCH13 Mask */
+#define CREG_DMAMUX_DMAMUXCH14_Pos 28 /*!< CREG DMAMUX: DMAMUXCH14 Position */
+#define CREG_DMAMUX_DMAMUXCH14_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH14_Pos) /*!< CREG DMAMUX: DMAMUXCH14 Mask */
+#define CREG_DMAMUX_DMAMUXCH15_Pos 30 /*!< CREG DMAMUX: DMAMUXCH15 Position */
+#define CREG_DMAMUX_DMAMUXCH15_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH15_Pos) /*!< CREG DMAMUX: DMAMUXCH15 Mask */
+
+// --------------------------------------- CREG_ETBCFG ------------------------------------------
+#define CREG_ETBCFG_ETB_Pos 0 /*!< CREG ETBCFG: ETB Position */
+#define CREG_ETBCFG_ETB_Msk (0x01UL << CREG_ETBCFG_ETB_Pos) /*!< CREG ETBCFG: ETB Mask */
+
+// --------------------------------------- CREG_CREG6 -------------------------------------------
+#define CREG_CREG6_ETHMODE_Pos 0 /*!< CREG CREG6: ETHMODE Position */
+#define CREG_CREG6_ETHMODE_Msk (0x07UL << CREG_CREG6_ETHMODE_Pos) /*!< CREG CREG6: ETHMODE Mask */
+#define CREG_CREG6_TIMCTRL_Pos 4 /*!< CREG CREG6: TIMCTRL Position */
+#define CREG_CREG6_TIMCTRL_Msk (0x01UL << CREG_CREG6_TIMCTRL_Pos) /*!< CREG CREG6: TIMCTRL Mask */
+#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_Pos 12 /*!< CREG CREG6: I2S0_TX_SCK_IN_SEL Position */
+#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S0_TX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S0_TX_SCK_IN_SEL Mask */
+#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_Pos 13 /*!< CREG CREG6: I2S0_RX_SCK_IN_SEL Position */
+#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S0_RX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S0_RX_SCK_IN_SEL Mask */
+#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_Pos 14 /*!< CREG CREG6: I2S1_TX_SCK_IN_SEL Position */
+#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S1_TX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S1_TX_SCK_IN_SEL Mask */
+#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_Pos 15 /*!< CREG CREG6: I2S1_RX_SCK_IN_SEL Position */
+#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S1_RX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S1_RX_SCK_IN_SEL Mask */
+#define CREG_CREG6_EMC_CLK_SEL_Pos 16 /*!< CREG CREG6: EMC_CLK_SEL Position */
+#define CREG_CREG6_EMC_CLK_SEL_Msk (0x01UL << CREG_CREG6_EMC_CLK_SEL_Pos) /*!< CREG CREG6: EMC_CLK_SEL Mask */
+
+// ------------------------------------- CREG_M4TXEVENT -----------------------------------------
+#define CREG_M4TXEVENT_TXEVCLR_Pos 0 /*!< CREG M4TXEVENT: TXEVCLR Position */
+#define CREG_M4TXEVENT_TXEVCLR_Msk (0x01UL << CREG_M4TXEVENT_TXEVCLR_Pos) /*!< CREG M4TXEVENT: TXEVCLR Mask */
+
+// --------------------------------------- CREG_CHIPID ------------------------------------------
+#define CREG_CHIPID_ID_Pos 0 /*!< CREG CHIPID: ID Position */
+#define CREG_CHIPID_ID_Msk (0xffffffffUL << CREG_CHIPID_ID_Pos) /*!< CREG CHIPID: ID Mask */
+
+// ------------------------------------- CREG_M0TXEVENT -----------------------------------------
+#define CREG_M0TXEVENT_TXEVCLR_Pos 0 /*!< CREG M0TXEVENT: TXEVCLR Position */
+#define CREG_M0TXEVENT_TXEVCLR_Msk (0x01UL << CREG_M0TXEVENT_TXEVCLR_Pos) /*!< CREG M0TXEVENT: TXEVCLR Mask */
+
+// ------------------------------------ CREG_M0APPMEMMAP ----------------------------------------
+#define CREG_M0APPMEMMAP_M0APPMAP_Pos 12 /*!< CREG M0APPMEMMAP: M0APPMAP Position */
+#define CREG_M0APPMEMMAP_M0APPMAP_Msk (0x000fffffUL << CREG_M0APPMEMMAP_M0APPMAP_Pos) /*!< CREG M0APPMEMMAP: M0APPMAP Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- EVENTROUTER Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ------------------------------------ EVENTROUTER_HILO ----------------------------------------
+#define EVENTROUTER_HILO_WAKEUP0_L_Pos 0 /*!< EVENTROUTER HILO: WAKEUP0_L Position */
+#define EVENTROUTER_HILO_WAKEUP0_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP0_L_Pos) /*!< EVENTROUTER HILO: WAKEUP0_L Mask */
+#define EVENTROUTER_HILO_WAKEUP1_L_Pos 1 /*!< EVENTROUTER HILO: WAKEUP1_L Position */
+#define EVENTROUTER_HILO_WAKEUP1_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP1_L_Pos) /*!< EVENTROUTER HILO: WAKEUP1_L Mask */
+#define EVENTROUTER_HILO_WAKEUP2_L_Pos 2 /*!< EVENTROUTER HILO: WAKEUP2_L Position */
+#define EVENTROUTER_HILO_WAKEUP2_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP2_L_Pos) /*!< EVENTROUTER HILO: WAKEUP2_L Mask */
+#define EVENTROUTER_HILO_WAKEUP3_L_Pos 3 /*!< EVENTROUTER HILO: WAKEUP3_L Position */
+#define EVENTROUTER_HILO_WAKEUP3_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP3_L_Pos) /*!< EVENTROUTER HILO: WAKEUP3_L Mask */
+#define EVENTROUTER_HILO_ATIMER_L_Pos 4 /*!< EVENTROUTER HILO: ATIMER_L Position */
+#define EVENTROUTER_HILO_ATIMER_L_Msk (0x01UL << EVENTROUTER_HILO_ATIMER_L_Pos) /*!< EVENTROUTER HILO: ATIMER_L Mask */
+#define EVENTROUTER_HILO_RTC_L_Pos 5 /*!< EVENTROUTER HILO: RTC_L Position */
+#define EVENTROUTER_HILO_RTC_L_Msk (0x01UL << EVENTROUTER_HILO_RTC_L_Pos) /*!< EVENTROUTER HILO: RTC_L Mask */
+#define EVENTROUTER_HILO_BOD_L_Pos 6 /*!< EVENTROUTER HILO: BOD_L Position */
+#define EVENTROUTER_HILO_BOD_L_Msk (0x01UL << EVENTROUTER_HILO_BOD_L_Pos) /*!< EVENTROUTER HILO: BOD_L Mask */
+#define EVENTROUTER_HILO_WWDT_L_Pos 7 /*!< EVENTROUTER HILO: WWDT_L Position */
+#define EVENTROUTER_HILO_WWDT_L_Msk (0x01UL << EVENTROUTER_HILO_WWDT_L_Pos) /*!< EVENTROUTER HILO: WWDT_L Mask */
+#define EVENTROUTER_HILO_ETH_L_Pos 8 /*!< EVENTROUTER HILO: ETH_L Position */
+#define EVENTROUTER_HILO_ETH_L_Msk (0x01UL << EVENTROUTER_HILO_ETH_L_Pos) /*!< EVENTROUTER HILO: ETH_L Mask */
+#define EVENTROUTER_HILO_USB0_L_Pos 9 /*!< EVENTROUTER HILO: USB0_L Position */
+#define EVENTROUTER_HILO_USB0_L_Msk (0x01UL << EVENTROUTER_HILO_USB0_L_Pos) /*!< EVENTROUTER HILO: USB0_L Mask */
+#define EVENTROUTER_HILO_USB1_L_Pos 10 /*!< EVENTROUTER HILO: USB1_L Position */
+#define EVENTROUTER_HILO_USB1_L_Msk (0x01UL << EVENTROUTER_HILO_USB1_L_Pos) /*!< EVENTROUTER HILO: USB1_L Mask */
+#define EVENTROUTER_HILO_SDMMC_L_Pos 11 /*!< EVENTROUTER HILO: SDMMC_L Position */
+#define EVENTROUTER_HILO_SDMMC_L_Msk (0x01UL << EVENTROUTER_HILO_SDMMC_L_Pos) /*!< EVENTROUTER HILO: SDMMC_L Mask */
+#define EVENTROUTER_HILO_CAN_L_Pos 12 /*!< EVENTROUTER HILO: CAN_L Position */
+#define EVENTROUTER_HILO_CAN_L_Msk (0x01UL << EVENTROUTER_HILO_CAN_L_Pos) /*!< EVENTROUTER HILO: CAN_L Mask */
+#define EVENTROUTER_HILO_TIM2_L_Pos 13 /*!< EVENTROUTER HILO: TIM2_L Position */
+#define EVENTROUTER_HILO_TIM2_L_Msk (0x01UL << EVENTROUTER_HILO_TIM2_L_Pos) /*!< EVENTROUTER HILO: TIM2_L Mask */
+#define EVENTROUTER_HILO_TIM6_L_Pos 14 /*!< EVENTROUTER HILO: TIM6_L Position */
+#define EVENTROUTER_HILO_TIM6_L_Msk (0x01UL << EVENTROUTER_HILO_TIM6_L_Pos) /*!< EVENTROUTER HILO: TIM6_L Mask */
+#define EVENTROUTER_HILO_QEI_L_Pos 15 /*!< EVENTROUTER HILO: QEI_L Position */
+#define EVENTROUTER_HILO_QEI_L_Msk (0x01UL << EVENTROUTER_HILO_QEI_L_Pos) /*!< EVENTROUTER HILO: QEI_L Mask */
+#define EVENTROUTER_HILO_TIM14_L_Pos 16 /*!< EVENTROUTER HILO: TIM14_L Position */
+#define EVENTROUTER_HILO_TIM14_L_Msk (0x01UL << EVENTROUTER_HILO_TIM14_L_Pos) /*!< EVENTROUTER HILO: TIM14_L Mask */
+#define EVENTROUTER_HILO_RESET_L_Pos 19 /*!< EVENTROUTER HILO: RESET_L Position */
+#define EVENTROUTER_HILO_RESET_L_Msk (0x01UL << EVENTROUTER_HILO_RESET_L_Pos) /*!< EVENTROUTER HILO: RESET_L Mask */
+
+// ------------------------------------ EVENTROUTER_EDGE ----------------------------------------
+#define EVENTROUTER_EDGE_WAKEUP0_E_Pos 0 /*!< EVENTROUTER EDGE: WAKEUP0_E Position */
+#define EVENTROUTER_EDGE_WAKEUP0_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP0_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP0_E Mask */
+#define EVENTROUTER_EDGE_WAKEUP1_E_Pos 1 /*!< EVENTROUTER EDGE: WAKEUP1_E Position */
+#define EVENTROUTER_EDGE_WAKEUP1_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP1_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP1_E Mask */
+#define EVENTROUTER_EDGE_WAKEUP2_E_Pos 2 /*!< EVENTROUTER EDGE: WAKEUP2_E Position */
+#define EVENTROUTER_EDGE_WAKEUP2_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP2_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP2_E Mask */
+#define EVENTROUTER_EDGE_WAKEUP3_E_Pos 3 /*!< EVENTROUTER EDGE: WAKEUP3_E Position */
+#define EVENTROUTER_EDGE_WAKEUP3_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP3_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP3_E Mask */
+#define EVENTROUTER_EDGE_ATIMER_E_Pos 4 /*!< EVENTROUTER EDGE: ATIMER_E Position */
+#define EVENTROUTER_EDGE_ATIMER_E_Msk (0x01UL << EVENTROUTER_EDGE_ATIMER_E_Pos) /*!< EVENTROUTER EDGE: ATIMER_E Mask */
+#define EVENTROUTER_EDGE_RTC_E_Pos 5 /*!< EVENTROUTER EDGE: RTC_E Position */
+#define EVENTROUTER_EDGE_RTC_E_Msk (0x01UL << EVENTROUTER_EDGE_RTC_E_Pos) /*!< EVENTROUTER EDGE: RTC_E Mask */
+#define EVENTROUTER_EDGE_BOD_E_Pos 6 /*!< EVENTROUTER EDGE: BOD_E Position */
+#define EVENTROUTER_EDGE_BOD_E_Msk (0x01UL << EVENTROUTER_EDGE_BOD_E_Pos) /*!< EVENTROUTER EDGE: BOD_E Mask */
+#define EVENTROUTER_EDGE_WWDT_E_Pos 7 /*!< EVENTROUTER EDGE: WWDT_E Position */
+#define EVENTROUTER_EDGE_WWDT_E_Msk (0x01UL << EVENTROUTER_EDGE_WWDT_E_Pos) /*!< EVENTROUTER EDGE: WWDT_E Mask */
+#define EVENTROUTER_EDGE_ETH_E_Pos 8 /*!< EVENTROUTER EDGE: ETH_E Position */
+#define EVENTROUTER_EDGE_ETH_E_Msk (0x01UL << EVENTROUTER_EDGE_ETH_E_Pos) /*!< EVENTROUTER EDGE: ETH_E Mask */
+#define EVENTROUTER_EDGE_USB0_E_Pos 9 /*!< EVENTROUTER EDGE: USB0_E Position */
+#define EVENTROUTER_EDGE_USB0_E_Msk (0x01UL << EVENTROUTER_EDGE_USB0_E_Pos) /*!< EVENTROUTER EDGE: USB0_E Mask */
+#define EVENTROUTER_EDGE_USB1_E_Pos 10 /*!< EVENTROUTER EDGE: USB1_E Position */
+#define EVENTROUTER_EDGE_USB1_E_Msk (0x01UL << EVENTROUTER_EDGE_USB1_E_Pos) /*!< EVENTROUTER EDGE: USB1_E Mask */
+#define EVENTROUTER_EDGE_SDMMC_E_Pos 11 /*!< EVENTROUTER EDGE: SDMMC_E Position */
+#define EVENTROUTER_EDGE_SDMMC_E_Msk (0x01UL << EVENTROUTER_EDGE_SDMMC_E_Pos) /*!< EVENTROUTER EDGE: SDMMC_E Mask */
+#define EVENTROUTER_EDGE_CAN_E_Pos 12 /*!< EVENTROUTER EDGE: CAN_E Position */
+#define EVENTROUTER_EDGE_CAN_E_Msk (0x01UL << EVENTROUTER_EDGE_CAN_E_Pos) /*!< EVENTROUTER EDGE: CAN_E Mask */
+#define EVENTROUTER_EDGE_TIM2_E_Pos 13 /*!< EVENTROUTER EDGE: TIM2_E Position */
+#define EVENTROUTER_EDGE_TIM2_E_Msk (0x01UL << EVENTROUTER_EDGE_TIM2_E_Pos) /*!< EVENTROUTER EDGE: TIM2_E Mask */
+#define EVENTROUTER_EDGE_TIM6_E_Pos 14 /*!< EVENTROUTER EDGE: TIM6_E Position */
+#define EVENTROUTER_EDGE_TIM6_E_Msk (0x01UL << EVENTROUTER_EDGE_TIM6_E_Pos) /*!< EVENTROUTER EDGE: TIM6_E Mask */
+#define EVENTROUTER_EDGE_QEI_E_Pos 15 /*!< EVENTROUTER EDGE: QEI_E Position */
+#define EVENTROUTER_EDGE_QEI_E_Msk (0x01UL << EVENTROUTER_EDGE_QEI_E_Pos) /*!< EVENTROUTER EDGE: QEI_E Mask */
+#define EVENTROUTER_EDGE_TIM14_E_Pos 16 /*!< EVENTROUTER EDGE: TIM14_E Position */
+#define EVENTROUTER_EDGE_TIM14_E_Msk (0x01UL << EVENTROUTER_EDGE_TIM14_E_Pos) /*!< EVENTROUTER EDGE: TIM14_E Mask */
+#define EVENTROUTER_EDGE_RESET_E_Pos 19 /*!< EVENTROUTER EDGE: RESET_E Position */
+#define EVENTROUTER_EDGE_RESET_E_Msk (0x01UL << EVENTROUTER_EDGE_RESET_E_Pos) /*!< EVENTROUTER EDGE: RESET_E Mask */
+
+// ----------------------------------- EVENTROUTER_CLR_EN ---------------------------------------
+#define EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Pos 0 /*!< EVENTROUTER CLR_EN: WAKEUP0_CLREN Position */
+#define EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP0_CLREN Mask */
+#define EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Pos 1 /*!< EVENTROUTER CLR_EN: WAKEUP1_CLREN Position */
+#define EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP1_CLREN Mask */
+#define EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Pos 2 /*!< EVENTROUTER CLR_EN: WAKEUP2_CLREN Position */
+#define EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP2_CLREN Mask */
+#define EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Pos 3 /*!< EVENTROUTER CLR_EN: WAKEUP3_CLREN Position */
+#define EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP3_CLREN Mask */
+#define EVENTROUTER_CLR_EN_ATIMER_CLREN_Pos 4 /*!< EVENTROUTER CLR_EN: ATIMER_CLREN Position */
+#define EVENTROUTER_CLR_EN_ATIMER_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_ATIMER_CLREN_Pos) /*!< EVENTROUTER CLR_EN: ATIMER_CLREN Mask */
+#define EVENTROUTER_CLR_EN_RTC_CLREN_Pos 5 /*!< EVENTROUTER CLR_EN: RTC_CLREN Position */
+#define EVENTROUTER_CLR_EN_RTC_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_RTC_CLREN_Pos) /*!< EVENTROUTER CLR_EN: RTC_CLREN Mask */
+#define EVENTROUTER_CLR_EN_BOD_CLREN_Pos 6 /*!< EVENTROUTER CLR_EN: BOD_CLREN Position */
+#define EVENTROUTER_CLR_EN_BOD_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_BOD_CLREN_Pos) /*!< EVENTROUTER CLR_EN: BOD_CLREN Mask */
+#define EVENTROUTER_CLR_EN_WWDT_CLREN_Pos 7 /*!< EVENTROUTER CLR_EN: WWDT_CLREN Position */
+#define EVENTROUTER_CLR_EN_WWDT_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WWDT_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WWDT_CLREN Mask */
+#define EVENTROUTER_CLR_EN_ETH_CLREN_Pos 8 /*!< EVENTROUTER CLR_EN: ETH_CLREN Position */
+#define EVENTROUTER_CLR_EN_ETH_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_ETH_CLREN_Pos) /*!< EVENTROUTER CLR_EN: ETH_CLREN Mask */
+#define EVENTROUTER_CLR_EN_USB0_CLREN_Pos 9 /*!< EVENTROUTER CLR_EN: USB0_CLREN Position */
+#define EVENTROUTER_CLR_EN_USB0_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_USB0_CLREN_Pos) /*!< EVENTROUTER CLR_EN: USB0_CLREN Mask */
+#define EVENTROUTER_CLR_EN_USB1_CLREN_Pos 10 /*!< EVENTROUTER CLR_EN: USB1_CLREN Position */
+#define EVENTROUTER_CLR_EN_USB1_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_USB1_CLREN_Pos) /*!< EVENTROUTER CLR_EN: USB1_CLREN Mask */
+#define EVENTROUTER_CLR_EN_SDMMC_CLREN_Pos 11 /*!< EVENTROUTER CLR_EN: SDMMC_CLREN Position */
+#define EVENTROUTER_CLR_EN_SDMMC_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_SDMMC_CLREN_Pos) /*!< EVENTROUTER CLR_EN: SDMMC_CLREN Mask */
+#define EVENTROUTER_CLR_EN_CAN_CLREN_Pos 12 /*!< EVENTROUTER CLR_EN: CAN_CLREN Position */
+#define EVENTROUTER_CLR_EN_CAN_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_CAN_CLREN_Pos) /*!< EVENTROUTER CLR_EN: CAN_CLREN Mask */
+#define EVENTROUTER_CLR_EN_TIM2_CLREN_Pos 13 /*!< EVENTROUTER CLR_EN: TIM2_CLREN Position */
+#define EVENTROUTER_CLR_EN_TIM2_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_TIM2_CLREN_Pos) /*!< EVENTROUTER CLR_EN: TIM2_CLREN Mask */
+#define EVENTROUTER_CLR_EN_TIM6_CLREN_Pos 14 /*!< EVENTROUTER CLR_EN: TIM6_CLREN Position */
+#define EVENTROUTER_CLR_EN_TIM6_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_TIM6_CLREN_Pos) /*!< EVENTROUTER CLR_EN: TIM6_CLREN Mask */
+#define EVENTROUTER_CLR_EN_QEI_CLREN_Pos 15 /*!< EVENTROUTER CLR_EN: QEI_CLREN Position */
+#define EVENTROUTER_CLR_EN_QEI_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_QEI_CLREN_Pos) /*!< EVENTROUTER CLR_EN: QEI_CLREN Mask */
+#define EVENTROUTER_CLR_EN_TIM14_CLREN_Pos 16 /*!< EVENTROUTER CLR_EN: TIM14_CLREN Position */
+#define EVENTROUTER_CLR_EN_TIM14_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_TIM14_CLREN_Pos) /*!< EVENTROUTER CLR_EN: TIM14_CLREN Mask */
+#define EVENTROUTER_CLR_EN_RESET_CLREN_Pos 19 /*!< EVENTROUTER CLR_EN: RESET_CLREN Position */
+#define EVENTROUTER_CLR_EN_RESET_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_RESET_CLREN_Pos) /*!< EVENTROUTER CLR_EN: RESET_CLREN Mask */
+
+// ----------------------------------- EVENTROUTER_SET_EN ---------------------------------------
+#define EVENTROUTER_SET_EN_WAKEUP0_SETEN_Pos 0 /*!< EVENTROUTER SET_EN: WAKEUP0_SETEN Position */
+#define EVENTROUTER_SET_EN_WAKEUP0_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP0_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP0_SETEN Mask */
+#define EVENTROUTER_SET_EN_WAKEUP1_SETEN_Pos 1 /*!< EVENTROUTER SET_EN: WAKEUP1_SETEN Position */
+#define EVENTROUTER_SET_EN_WAKEUP1_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP1_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP1_SETEN Mask */
+#define EVENTROUTER_SET_EN_WAKEUP2_SETEN_Pos 2 /*!< EVENTROUTER SET_EN: WAKEUP2_SETEN Position */
+#define EVENTROUTER_SET_EN_WAKEUP2_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP2_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP2_SETEN Mask */
+#define EVENTROUTER_SET_EN_WAKEUP3_SETEN_Pos 3 /*!< EVENTROUTER SET_EN: WAKEUP3_SETEN Position */
+#define EVENTROUTER_SET_EN_WAKEUP3_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP3_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP3_SETEN Mask */
+#define EVENTROUTER_SET_EN_ATIMER_SETEN_Pos 4 /*!< EVENTROUTER SET_EN: ATIMER_SETEN Position */
+#define EVENTROUTER_SET_EN_ATIMER_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_ATIMER_SETEN_Pos) /*!< EVENTROUTER SET_EN: ATIMER_SETEN Mask */
+#define EVENTROUTER_SET_EN_RTC_SETEN_Pos 5 /*!< EVENTROUTER SET_EN: RTC_SETEN Position */
+#define EVENTROUTER_SET_EN_RTC_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_RTC_SETEN_Pos) /*!< EVENTROUTER SET_EN: RTC_SETEN Mask */
+#define EVENTROUTER_SET_EN_BOD_SETEN_Pos 6 /*!< EVENTROUTER SET_EN: BOD_SETEN Position */
+#define EVENTROUTER_SET_EN_BOD_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_BOD_SETEN_Pos) /*!< EVENTROUTER SET_EN: BOD_SETEN Mask */
+#define EVENTROUTER_SET_EN_WWDT_SETEN_Pos 7 /*!< EVENTROUTER SET_EN: WWDT_SETEN Position */
+#define EVENTROUTER_SET_EN_WWDT_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WWDT_SETEN_Pos) /*!< EVENTROUTER SET_EN: WWDT_SETEN Mask */
+#define EVENTROUTER_SET_EN_ETH_SETEN_Pos 8 /*!< EVENTROUTER SET_EN: ETH_SETEN Position */
+#define EVENTROUTER_SET_EN_ETH_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_ETH_SETEN_Pos) /*!< EVENTROUTER SET_EN: ETH_SETEN Mask */
+#define EVENTROUTER_SET_EN_USB0_SETEN_Pos 9 /*!< EVENTROUTER SET_EN: USB0_SETEN Position */
+#define EVENTROUTER_SET_EN_USB0_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_USB0_SETEN_Pos) /*!< EVENTROUTER SET_EN: USB0_SETEN Mask */
+#define EVENTROUTER_SET_EN_USB1_SETEN_Pos 10 /*!< EVENTROUTER SET_EN: USB1_SETEN Position */
+#define EVENTROUTER_SET_EN_USB1_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_USB1_SETEN_Pos) /*!< EVENTROUTER SET_EN: USB1_SETEN Mask */
+#define EVENTROUTER_SET_EN_SDMMC_SETEN_Pos 11 /*!< EVENTROUTER SET_EN: SDMMC_SETEN Position */
+#define EVENTROUTER_SET_EN_SDMMC_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_SDMMC_SETEN_Pos) /*!< EVENTROUTER SET_EN: SDMMC_SETEN Mask */
+#define EVENTROUTER_SET_EN_CAN_SETEN_Pos 12 /*!< EVENTROUTER SET_EN: CAN_SETEN Position */
+#define EVENTROUTER_SET_EN_CAN_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_CAN_SETEN_Pos) /*!< EVENTROUTER SET_EN: CAN_SETEN Mask */
+#define EVENTROUTER_SET_EN_TIM2_SETEN_Pos 13 /*!< EVENTROUTER SET_EN: TIM2_SETEN Position */
+#define EVENTROUTER_SET_EN_TIM2_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_TIM2_SETEN_Pos) /*!< EVENTROUTER SET_EN: TIM2_SETEN Mask */
+#define EVENTROUTER_SET_EN_TIM6_SETEN_Pos 14 /*!< EVENTROUTER SET_EN: TIM6_SETEN Position */
+#define EVENTROUTER_SET_EN_TIM6_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_TIM6_SETEN_Pos) /*!< EVENTROUTER SET_EN: TIM6_SETEN Mask */
+#define EVENTROUTER_SET_EN_QEI_SETEN_Pos 15 /*!< EVENTROUTER SET_EN: QEI_SETEN Position */
+#define EVENTROUTER_SET_EN_QEI_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_QEI_SETEN_Pos) /*!< EVENTROUTER SET_EN: QEI_SETEN Mask */
+#define EVENTROUTER_SET_EN_TIM14_SETEN_Pos 16 /*!< EVENTROUTER SET_EN: TIM14_SETEN Position */
+#define EVENTROUTER_SET_EN_TIM14_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_TIM14_SETEN_Pos) /*!< EVENTROUTER SET_EN: TIM14_SETEN Mask */
+#define EVENTROUTER_SET_EN_RESET_SETEN_Pos 19 /*!< EVENTROUTER SET_EN: RESET_SETEN Position */
+#define EVENTROUTER_SET_EN_RESET_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_RESET_SETEN_Pos) /*!< EVENTROUTER SET_EN: RESET_SETEN Mask */
+
+// ----------------------------------- EVENTROUTER_STATUS ---------------------------------------
+#define EVENTROUTER_STATUS_WAKEUP0_ST_Pos 0 /*!< EVENTROUTER STATUS: WAKEUP0_ST Position */
+#define EVENTROUTER_STATUS_WAKEUP0_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP0_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP0_ST Mask */
+#define EVENTROUTER_STATUS_WAKEUP1_ST_Pos 1 /*!< EVENTROUTER STATUS: WAKEUP1_ST Position */
+#define EVENTROUTER_STATUS_WAKEUP1_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP1_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP1_ST Mask */
+#define EVENTROUTER_STATUS_WAKEUP2_ST_Pos 2 /*!< EVENTROUTER STATUS: WAKEUP2_ST Position */
+#define EVENTROUTER_STATUS_WAKEUP2_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP2_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP2_ST Mask */
+#define EVENTROUTER_STATUS_WAKEUP3_ST_Pos 3 /*!< EVENTROUTER STATUS: WAKEUP3_ST Position */
+#define EVENTROUTER_STATUS_WAKEUP3_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP3_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP3_ST Mask */
+#define EVENTROUTER_STATUS_ATIMER_ST_Pos 4 /*!< EVENTROUTER STATUS: ATIMER_ST Position */
+#define EVENTROUTER_STATUS_ATIMER_ST_Msk (0x01UL << EVENTROUTER_STATUS_ATIMER_ST_Pos) /*!< EVENTROUTER STATUS: ATIMER_ST Mask */
+#define EVENTROUTER_STATUS_RTC_ST_Pos 5 /*!< EVENTROUTER STATUS: RTC_ST Position */
+#define EVENTROUTER_STATUS_RTC_ST_Msk (0x01UL << EVENTROUTER_STATUS_RTC_ST_Pos) /*!< EVENTROUTER STATUS: RTC_ST Mask */
+#define EVENTROUTER_STATUS_BOD_ST_Pos 6 /*!< EVENTROUTER STATUS: BOD_ST Position */
+#define EVENTROUTER_STATUS_BOD_ST_Msk (0x01UL << EVENTROUTER_STATUS_BOD_ST_Pos) /*!< EVENTROUTER STATUS: BOD_ST Mask */
+#define EVENTROUTER_STATUS_WWDT_ST_Pos 7 /*!< EVENTROUTER STATUS: WWDT_ST Position */
+#define EVENTROUTER_STATUS_WWDT_ST_Msk (0x01UL << EVENTROUTER_STATUS_WWDT_ST_Pos) /*!< EVENTROUTER STATUS: WWDT_ST Mask */
+#define EVENTROUTER_STATUS_ETH_ST_Pos 8 /*!< EVENTROUTER STATUS: ETH_ST Position */
+#define EVENTROUTER_STATUS_ETH_ST_Msk (0x01UL << EVENTROUTER_STATUS_ETH_ST_Pos) /*!< EVENTROUTER STATUS: ETH_ST Mask */
+#define EVENTROUTER_STATUS_USB0_ST_Pos 9 /*!< EVENTROUTER STATUS: USB0_ST Position */
+#define EVENTROUTER_STATUS_USB0_ST_Msk (0x01UL << EVENTROUTER_STATUS_USB0_ST_Pos) /*!< EVENTROUTER STATUS: USB0_ST Mask */
+#define EVENTROUTER_STATUS_USB1_ST_Pos 10 /*!< EVENTROUTER STATUS: USB1_ST Position */
+#define EVENTROUTER_STATUS_USB1_ST_Msk (0x01UL << EVENTROUTER_STATUS_USB1_ST_Pos) /*!< EVENTROUTER STATUS: USB1_ST Mask */
+#define EVENTROUTER_STATUS_SDMMC_ST_Pos 11 /*!< EVENTROUTER STATUS: SDMMC_ST Position */
+#define EVENTROUTER_STATUS_SDMMC_ST_Msk (0x01UL << EVENTROUTER_STATUS_SDMMC_ST_Pos) /*!< EVENTROUTER STATUS: SDMMC_ST Mask */
+#define EVENTROUTER_STATUS_CAN_ST_Pos 12 /*!< EVENTROUTER STATUS: CAN_ST Position */
+#define EVENTROUTER_STATUS_CAN_ST_Msk (0x01UL << EVENTROUTER_STATUS_CAN_ST_Pos) /*!< EVENTROUTER STATUS: CAN_ST Mask */
+#define EVENTROUTER_STATUS_TIM2_ST_Pos 13 /*!< EVENTROUTER STATUS: TIM2_ST Position */
+#define EVENTROUTER_STATUS_TIM2_ST_Msk (0x01UL << EVENTROUTER_STATUS_TIM2_ST_Pos) /*!< EVENTROUTER STATUS: TIM2_ST Mask */
+#define EVENTROUTER_STATUS_TIM6_ST_Pos 14 /*!< EVENTROUTER STATUS: TIM6_ST Position */
+#define EVENTROUTER_STATUS_TIM6_ST_Msk (0x01UL << EVENTROUTER_STATUS_TIM6_ST_Pos) /*!< EVENTROUTER STATUS: TIM6_ST Mask */
+#define EVENTROUTER_STATUS_QEI_ST_Pos 15 /*!< EVENTROUTER STATUS: QEI_ST Position */
+#define EVENTROUTER_STATUS_QEI_ST_Msk (0x01UL << EVENTROUTER_STATUS_QEI_ST_Pos) /*!< EVENTROUTER STATUS: QEI_ST Mask */
+#define EVENTROUTER_STATUS_TIM14_ST_Pos 16 /*!< EVENTROUTER STATUS: TIM14_ST Position */
+#define EVENTROUTER_STATUS_TIM14_ST_Msk (0x01UL << EVENTROUTER_STATUS_TIM14_ST_Pos) /*!< EVENTROUTER STATUS: TIM14_ST Mask */
+#define EVENTROUTER_STATUS_RESET_ST_Pos 19 /*!< EVENTROUTER STATUS: RESET_ST Position */
+#define EVENTROUTER_STATUS_RESET_ST_Msk (0x01UL << EVENTROUTER_STATUS_RESET_ST_Pos) /*!< EVENTROUTER STATUS: RESET_ST Mask */
+
+// ----------------------------------- EVENTROUTER_ENABLE ---------------------------------------
+#define EVENTROUTER_ENABLE_WAKEUP0_EN_Pos 0 /*!< EVENTROUTER ENABLE: WAKEUP0_EN Position */
+#define EVENTROUTER_ENABLE_WAKEUP0_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP0_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP0_EN Mask */
+#define EVENTROUTER_ENABLE_WAKEUP1_EN_Pos 1 /*!< EVENTROUTER ENABLE: WAKEUP1_EN Position */
+#define EVENTROUTER_ENABLE_WAKEUP1_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP1_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP1_EN Mask */
+#define EVENTROUTER_ENABLE_WAKEUP2_EN_Pos 2 /*!< EVENTROUTER ENABLE: WAKEUP2_EN Position */
+#define EVENTROUTER_ENABLE_WAKEUP2_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP2_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP2_EN Mask */
+#define EVENTROUTER_ENABLE_WAKEUP3_EN_Pos 3 /*!< EVENTROUTER ENABLE: WAKEUP3_EN Position */
+#define EVENTROUTER_ENABLE_WAKEUP3_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP3_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP3_EN Mask */
+#define EVENTROUTER_ENABLE_ATIMER_EN_Pos 4 /*!< EVENTROUTER ENABLE: ATIMER_EN Position */
+#define EVENTROUTER_ENABLE_ATIMER_EN_Msk (0x01UL << EVENTROUTER_ENABLE_ATIMER_EN_Pos) /*!< EVENTROUTER ENABLE: ATIMER_EN Mask */
+#define EVENTROUTER_ENABLE_RTC_EN_Pos 5 /*!< EVENTROUTER ENABLE: RTC_EN Position */
+#define EVENTROUTER_ENABLE_RTC_EN_Msk (0x01UL << EVENTROUTER_ENABLE_RTC_EN_Pos) /*!< EVENTROUTER ENABLE: RTC_EN Mask */
+#define EVENTROUTER_ENABLE_BOD_EN_Pos 6 /*!< EVENTROUTER ENABLE: BOD_EN Position */
+#define EVENTROUTER_ENABLE_BOD_EN_Msk (0x01UL << EVENTROUTER_ENABLE_BOD_EN_Pos) /*!< EVENTROUTER ENABLE: BOD_EN Mask */
+#define EVENTROUTER_ENABLE_WWDT_EN_Pos 7 /*!< EVENTROUTER ENABLE: WWDT_EN Position */
+#define EVENTROUTER_ENABLE_WWDT_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WWDT_EN_Pos) /*!< EVENTROUTER ENABLE: WWDT_EN Mask */
+#define EVENTROUTER_ENABLE_ETH_EN_Pos 8 /*!< EVENTROUTER ENABLE: ETH_EN Position */
+#define EVENTROUTER_ENABLE_ETH_EN_Msk (0x01UL << EVENTROUTER_ENABLE_ETH_EN_Pos) /*!< EVENTROUTER ENABLE: ETH_EN Mask */
+#define EVENTROUTER_ENABLE_USB0_EN_Pos 9 /*!< EVENTROUTER ENABLE: USB0_EN Position */
+#define EVENTROUTER_ENABLE_USB0_EN_Msk (0x01UL << EVENTROUTER_ENABLE_USB0_EN_Pos) /*!< EVENTROUTER ENABLE: USB0_EN Mask */
+#define EVENTROUTER_ENABLE_USB1_EN_Pos 10 /*!< EVENTROUTER ENABLE: USB1_EN Position */
+#define EVENTROUTER_ENABLE_USB1_EN_Msk (0x01UL << EVENTROUTER_ENABLE_USB1_EN_Pos) /*!< EVENTROUTER ENABLE: USB1_EN Mask */
+#define EVENTROUTER_ENABLE_SDMMC_EN_Pos 11 /*!< EVENTROUTER ENABLE: SDMMC_EN Position */
+#define EVENTROUTER_ENABLE_SDMMC_EN_Msk (0x01UL << EVENTROUTER_ENABLE_SDMMC_EN_Pos) /*!< EVENTROUTER ENABLE: SDMMC_EN Mask */
+#define EVENTROUTER_ENABLE_CAN_EN_Pos 12 /*!< EVENTROUTER ENABLE: CAN_EN Position */
+#define EVENTROUTER_ENABLE_CAN_EN_Msk (0x01UL << EVENTROUTER_ENABLE_CAN_EN_Pos) /*!< EVENTROUTER ENABLE: CAN_EN Mask */
+#define EVENTROUTER_ENABLE_TIM2_EN_Pos 13 /*!< EVENTROUTER ENABLE: TIM2_EN Position */
+#define EVENTROUTER_ENABLE_TIM2_EN_Msk (0x01UL << EVENTROUTER_ENABLE_TIM2_EN_Pos) /*!< EVENTROUTER ENABLE: TIM2_EN Mask */
+#define EVENTROUTER_ENABLE_TIM6_EN_Pos 14 /*!< EVENTROUTER ENABLE: TIM6_EN Position */
+#define EVENTROUTER_ENABLE_TIM6_EN_Msk (0x01UL << EVENTROUTER_ENABLE_TIM6_EN_Pos) /*!< EVENTROUTER ENABLE: TIM6_EN Mask */
+#define EVENTROUTER_ENABLE_QEI_EN_Pos 15 /*!< EVENTROUTER ENABLE: QEI_EN Position */
+#define EVENTROUTER_ENABLE_QEI_EN_Msk (0x01UL << EVENTROUTER_ENABLE_QEI_EN_Pos) /*!< EVENTROUTER ENABLE: QEI_EN Mask */
+#define EVENTROUTER_ENABLE_TIM14_EN_Pos 16 /*!< EVENTROUTER ENABLE: TIM14_EN Position */
+#define EVENTROUTER_ENABLE_TIM14_EN_Msk (0x01UL << EVENTROUTER_ENABLE_TIM14_EN_Pos) /*!< EVENTROUTER ENABLE: TIM14_EN Mask */
+#define EVENTROUTER_ENABLE_RESET_EN_Pos 19 /*!< EVENTROUTER ENABLE: RESET_EN Position */
+#define EVENTROUTER_ENABLE_RESET_EN_Msk (0x01UL << EVENTROUTER_ENABLE_RESET_EN_Pos) /*!< EVENTROUTER ENABLE: RESET_EN Mask */
+
+// ---------------------------------- EVENTROUTER_CLR_STAT --------------------------------------
+#define EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Pos 0 /*!< EVENTROUTER CLR_STAT: WAKEUP0_CLRST Position */
+#define EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP0_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Pos 1 /*!< EVENTROUTER CLR_STAT: WAKEUP1_CLRST Position */
+#define EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP1_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Pos 2 /*!< EVENTROUTER CLR_STAT: WAKEUP2_CLRST Position */
+#define EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP2_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Pos 3 /*!< EVENTROUTER CLR_STAT: WAKEUP3_CLRST Position */
+#define EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP3_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_ATIMER_CLRST_Pos 4 /*!< EVENTROUTER CLR_STAT: ATIMER_CLRST Position */
+#define EVENTROUTER_CLR_STAT_ATIMER_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_ATIMER_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: ATIMER_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_RTC_CLRST_Pos 5 /*!< EVENTROUTER CLR_STAT: RTC_CLRST Position */
+#define EVENTROUTER_CLR_STAT_RTC_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_RTC_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: RTC_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_BOD_CLRST_Pos 6 /*!< EVENTROUTER CLR_STAT: BOD_CLRST Position */
+#define EVENTROUTER_CLR_STAT_BOD_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_BOD_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: BOD_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_WWDT_CLRST_Pos 7 /*!< EVENTROUTER CLR_STAT: WWDT_CLRST Position */
+#define EVENTROUTER_CLR_STAT_WWDT_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WWDT_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WWDT_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_ETH_CLRST_Pos 8 /*!< EVENTROUTER CLR_STAT: ETH_CLRST Position */
+#define EVENTROUTER_CLR_STAT_ETH_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_ETH_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: ETH_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_USB0_CLRST_Pos 9 /*!< EVENTROUTER CLR_STAT: USB0_CLRST Position */
+#define EVENTROUTER_CLR_STAT_USB0_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_USB0_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: USB0_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_USB1_CLRST_Pos 10 /*!< EVENTROUTER CLR_STAT: USB1_CLRST Position */
+#define EVENTROUTER_CLR_STAT_USB1_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_USB1_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: USB1_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_SDMMC_CLRST_Pos 11 /*!< EVENTROUTER CLR_STAT: SDMMC_CLRST Position */
+#define EVENTROUTER_CLR_STAT_SDMMC_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_SDMMC_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: SDMMC_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_CAN_CLRST_Pos 12 /*!< EVENTROUTER CLR_STAT: CAN_CLRST Position */
+#define EVENTROUTER_CLR_STAT_CAN_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_CAN_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: CAN_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_TIM2_CLRST_Pos 13 /*!< EVENTROUTER CLR_STAT: TIM2_CLRST Position */
+#define EVENTROUTER_CLR_STAT_TIM2_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_TIM2_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: TIM2_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_TIM6_CLRST_Pos 14 /*!< EVENTROUTER CLR_STAT: TIM6_CLRST Position */
+#define EVENTROUTER_CLR_STAT_TIM6_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_TIM6_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: TIM6_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_QEI_CLRST_Pos 15 /*!< EVENTROUTER CLR_STAT: QEI_CLRST Position */
+#define EVENTROUTER_CLR_STAT_QEI_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_QEI_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: QEI_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_TIM14_CLRST_Pos 16 /*!< EVENTROUTER CLR_STAT: TIM14_CLRST Position */
+#define EVENTROUTER_CLR_STAT_TIM14_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_TIM14_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: TIM14_CLRST Mask */
+#define EVENTROUTER_CLR_STAT_RESET_CLRST_Pos 19 /*!< EVENTROUTER CLR_STAT: RESET_CLRST Position */
+#define EVENTROUTER_CLR_STAT_RESET_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_RESET_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: RESET_CLRST Mask */
+
+// ---------------------------------- EVENTROUTER_SET_STAT --------------------------------------
+#define EVENTROUTER_SET_STAT_WAKEUP0_SETST_Pos 0 /*!< EVENTROUTER SET_STAT: WAKEUP0_SETST Position */
+#define EVENTROUTER_SET_STAT_WAKEUP0_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP0_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP0_SETST Mask */
+#define EVENTROUTER_SET_STAT_WAKEUP1_SETST_Pos 1 /*!< EVENTROUTER SET_STAT: WAKEUP1_SETST Position */
+#define EVENTROUTER_SET_STAT_WAKEUP1_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP1_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP1_SETST Mask */
+#define EVENTROUTER_SET_STAT_WAKEUP2_SETST_Pos 2 /*!< EVENTROUTER SET_STAT: WAKEUP2_SETST Position */
+#define EVENTROUTER_SET_STAT_WAKEUP2_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP2_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP2_SETST Mask */
+#define EVENTROUTER_SET_STAT_WAKEUP3_SETST_Pos 3 /*!< EVENTROUTER SET_STAT: WAKEUP3_SETST Position */
+#define EVENTROUTER_SET_STAT_WAKEUP3_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP3_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP3_SETST Mask */
+#define EVENTROUTER_SET_STAT_ATIMER_SETST_Pos 4 /*!< EVENTROUTER SET_STAT: ATIMER_SETST Position */
+#define EVENTROUTER_SET_STAT_ATIMER_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_ATIMER_SETST_Pos) /*!< EVENTROUTER SET_STAT: ATIMER_SETST Mask */
+#define EVENTROUTER_SET_STAT_RTC_SETST_Pos 5 /*!< EVENTROUTER SET_STAT: RTC_SETST Position */
+#define EVENTROUTER_SET_STAT_RTC_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_RTC_SETST_Pos) /*!< EVENTROUTER SET_STAT: RTC_SETST Mask */
+#define EVENTROUTER_SET_STAT_BOD_SETST_Pos 6 /*!< EVENTROUTER SET_STAT: BOD_SETST Position */
+#define EVENTROUTER_SET_STAT_BOD_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_BOD_SETST_Pos) /*!< EVENTROUTER SET_STAT: BOD_SETST Mask */
+#define EVENTROUTER_SET_STAT_WWDT_SETST_Pos 7 /*!< EVENTROUTER SET_STAT: WWDT_SETST Position */
+#define EVENTROUTER_SET_STAT_WWDT_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WWDT_SETST_Pos) /*!< EVENTROUTER SET_STAT: WWDT_SETST Mask */
+#define EVENTROUTER_SET_STAT_ETH_SETST_Pos 8 /*!< EVENTROUTER SET_STAT: ETH_SETST Position */
+#define EVENTROUTER_SET_STAT_ETH_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_ETH_SETST_Pos) /*!< EVENTROUTER SET_STAT: ETH_SETST Mask */
+#define EVENTROUTER_SET_STAT_USB0_SETST_Pos 9 /*!< EVENTROUTER SET_STAT: USB0_SETST Position */
+#define EVENTROUTER_SET_STAT_USB0_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_USB0_SETST_Pos) /*!< EVENTROUTER SET_STAT: USB0_SETST Mask */
+#define EVENTROUTER_SET_STAT_USB1_SETST_Pos 10 /*!< EVENTROUTER SET_STAT: USB1_SETST Position */
+#define EVENTROUTER_SET_STAT_USB1_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_USB1_SETST_Pos) /*!< EVENTROUTER SET_STAT: USB1_SETST Mask */
+#define EVENTROUTER_SET_STAT_SDMMC_SETST_Pos 11 /*!< EVENTROUTER SET_STAT: SDMMC_SETST Position */
+#define EVENTROUTER_SET_STAT_SDMMC_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_SDMMC_SETST_Pos) /*!< EVENTROUTER SET_STAT: SDMMC_SETST Mask */
+#define EVENTROUTER_SET_STAT_CAN_SETST_Pos 12 /*!< EVENTROUTER SET_STAT: CAN_SETST Position */
+#define EVENTROUTER_SET_STAT_CAN_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_CAN_SETST_Pos) /*!< EVENTROUTER SET_STAT: CAN_SETST Mask */
+#define EVENTROUTER_SET_STAT_TIM2_SETST_Pos 13 /*!< EVENTROUTER SET_STAT: TIM2_SETST Position */
+#define EVENTROUTER_SET_STAT_TIM2_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_TIM2_SETST_Pos) /*!< EVENTROUTER SET_STAT: TIM2_SETST Mask */
+#define EVENTROUTER_SET_STAT_TIM6_SETST_Pos 14 /*!< EVENTROUTER SET_STAT: TIM6_SETST Position */
+#define EVENTROUTER_SET_STAT_TIM6_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_TIM6_SETST_Pos) /*!< EVENTROUTER SET_STAT: TIM6_SETST Mask */
+#define EVENTROUTER_SET_STAT_QEI_SETST_Pos 15 /*!< EVENTROUTER SET_STAT: QEI_SETST Position */
+#define EVENTROUTER_SET_STAT_QEI_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_QEI_SETST_Pos) /*!< EVENTROUTER SET_STAT: QEI_SETST Mask */
+#define EVENTROUTER_SET_STAT_TIM14_SETST_Pos 16 /*!< EVENTROUTER SET_STAT: TIM14_SETST Position */
+#define EVENTROUTER_SET_STAT_TIM14_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_TIM14_SETST_Pos) /*!< EVENTROUTER SET_STAT: TIM14_SETST Mask */
+#define EVENTROUTER_SET_STAT_RESET_SETST_Pos 19 /*!< EVENTROUTER SET_STAT: RESET_SETST Position */
+#define EVENTROUTER_SET_STAT_RESET_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_RESET_SETST_Pos) /*!< EVENTROUTER SET_STAT: RESET_SETST Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- RTC Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------- RTC_ILR --------------------------------------------
+#define RTC_ILR_RTCCIF_Pos 0 /*!< RTC ILR: RTCCIF Position */
+#define RTC_ILR_RTCCIF_Msk (0x01UL << RTC_ILR_RTCCIF_Pos) /*!< RTC ILR: RTCCIF Mask */
+#define RTC_ILR_RTCALF_Pos 1 /*!< RTC ILR: RTCALF Position */
+#define RTC_ILR_RTCALF_Msk (0x01UL << RTC_ILR_RTCALF_Pos) /*!< RTC ILR: RTCALF Mask */
+
+// ----------------------------------------- RTC_CCR --------------------------------------------
+#define RTC_CCR_CLKEN_Pos 0 /*!< RTC CCR: CLKEN Position */
+#define RTC_CCR_CLKEN_Msk (0x01UL << RTC_CCR_CLKEN_Pos) /*!< RTC CCR: CLKEN Mask */
+#define RTC_CCR_CTCRST_Pos 1 /*!< RTC CCR: CTCRST Position */
+#define RTC_CCR_CTCRST_Msk (0x01UL << RTC_CCR_CTCRST_Pos) /*!< RTC CCR: CTCRST Mask */
+#define RTC_CCR_CCALEN_Pos 4 /*!< RTC CCR: CCALEN Position */
+#define RTC_CCR_CCALEN_Msk (0x01UL << RTC_CCR_CCALEN_Pos) /*!< RTC CCR: CCALEN Mask */
+
+// ---------------------------------------- RTC_CIIR --------------------------------------------
+#define RTC_CIIR_IMSEC_Pos 0 /*!< RTC CIIR: IMSEC Position */
+#define RTC_CIIR_IMSEC_Msk (0x01UL << RTC_CIIR_IMSEC_Pos) /*!< RTC CIIR: IMSEC Mask */
+#define RTC_CIIR_IMMIN_Pos 1 /*!< RTC CIIR: IMMIN Position */
+#define RTC_CIIR_IMMIN_Msk (0x01UL << RTC_CIIR_IMMIN_Pos) /*!< RTC CIIR: IMMIN Mask */
+#define RTC_CIIR_IMHOUR_Pos 2 /*!< RTC CIIR: IMHOUR Position */
+#define RTC_CIIR_IMHOUR_Msk (0x01UL << RTC_CIIR_IMHOUR_Pos) /*!< RTC CIIR: IMHOUR Mask */
+#define RTC_CIIR_IMDOM_Pos 3 /*!< RTC CIIR: IMDOM Position */
+#define RTC_CIIR_IMDOM_Msk (0x01UL << RTC_CIIR_IMDOM_Pos) /*!< RTC CIIR: IMDOM Mask */
+#define RTC_CIIR_IMDOW_Pos 4 /*!< RTC CIIR: IMDOW Position */
+#define RTC_CIIR_IMDOW_Msk (0x01UL << RTC_CIIR_IMDOW_Pos) /*!< RTC CIIR: IMDOW Mask */
+#define RTC_CIIR_IMDOY_Pos 5 /*!< RTC CIIR: IMDOY Position */
+#define RTC_CIIR_IMDOY_Msk (0x01UL << RTC_CIIR_IMDOY_Pos) /*!< RTC CIIR: IMDOY Mask */
+#define RTC_CIIR_IMMON_Pos 6 /*!< RTC CIIR: IMMON Position */
+#define RTC_CIIR_IMMON_Msk (0x01UL << RTC_CIIR_IMMON_Pos) /*!< RTC CIIR: IMMON Mask */
+#define RTC_CIIR_IMYEAR_Pos 7 /*!< RTC CIIR: IMYEAR Position */
+#define RTC_CIIR_IMYEAR_Msk (0x01UL << RTC_CIIR_IMYEAR_Pos) /*!< RTC CIIR: IMYEAR Mask */
+
+// ----------------------------------------- RTC_AMR --------------------------------------------
+#define RTC_AMR_AMRSEC_Pos 0 /*!< RTC AMR: AMRSEC Position */
+#define RTC_AMR_AMRSEC_Msk (0x01UL << RTC_AMR_AMRSEC_Pos) /*!< RTC AMR: AMRSEC Mask */
+#define RTC_AMR_AMRMIN_Pos 1 /*!< RTC AMR: AMRMIN Position */
+#define RTC_AMR_AMRMIN_Msk (0x01UL << RTC_AMR_AMRMIN_Pos) /*!< RTC AMR: AMRMIN Mask */
+#define RTC_AMR_AMRHOUR_Pos 2 /*!< RTC AMR: AMRHOUR Position */
+#define RTC_AMR_AMRHOUR_Msk (0x01UL << RTC_AMR_AMRHOUR_Pos) /*!< RTC AMR: AMRHOUR Mask */
+#define RTC_AMR_AMRDOM_Pos 3 /*!< RTC AMR: AMRDOM Position */
+#define RTC_AMR_AMRDOM_Msk (0x01UL << RTC_AMR_AMRDOM_Pos) /*!< RTC AMR: AMRDOM Mask */
+#define RTC_AMR_AMRDOW_Pos 4 /*!< RTC AMR: AMRDOW Position */
+#define RTC_AMR_AMRDOW_Msk (0x01UL << RTC_AMR_AMRDOW_Pos) /*!< RTC AMR: AMRDOW Mask */
+#define RTC_AMR_AMRDOY_Pos 5 /*!< RTC AMR: AMRDOY Position */
+#define RTC_AMR_AMRDOY_Msk (0x01UL << RTC_AMR_AMRDOY_Pos) /*!< RTC AMR: AMRDOY Mask */
+#define RTC_AMR_AMRMON_Pos 6 /*!< RTC AMR: AMRMON Position */
+#define RTC_AMR_AMRMON_Msk (0x01UL << RTC_AMR_AMRMON_Pos) /*!< RTC AMR: AMRMON Mask */
+#define RTC_AMR_AMRYEAR_Pos 7 /*!< RTC AMR: AMRYEAR Position */
+#define RTC_AMR_AMRYEAR_Msk (0x01UL << RTC_AMR_AMRYEAR_Pos) /*!< RTC AMR: AMRYEAR Mask */
+
+// --------------------------------------- RTC_CTIME0 -------------------------------------------
+#define RTC_CTIME0_SECONDS_Pos 0 /*!< RTC CTIME0: SECONDS Position */
+#define RTC_CTIME0_SECONDS_Msk (0x3fUL << RTC_CTIME0_SECONDS_Pos) /*!< RTC CTIME0: SECONDS Mask */
+#define RTC_CTIME0_MINUTES_Pos 8 /*!< RTC CTIME0: MINUTES Position */
+#define RTC_CTIME0_MINUTES_Msk (0x3fUL << RTC_CTIME0_MINUTES_Pos) /*!< RTC CTIME0: MINUTES Mask */
+#define RTC_CTIME0_HOURS_Pos 16 /*!< RTC CTIME0: HOURS Position */
+#define RTC_CTIME0_HOURS_Msk (0x1fUL << RTC_CTIME0_HOURS_Pos) /*!< RTC CTIME0: HOURS Mask */
+#define RTC_CTIME0_DOW_Pos 24 /*!< RTC CTIME0: DOW Position */
+#define RTC_CTIME0_DOW_Msk (0x07UL << RTC_CTIME0_DOW_Pos) /*!< RTC CTIME0: DOW Mask */
+
+// --------------------------------------- RTC_CTIME1 -------------------------------------------
+#define RTC_CTIME1_DOM_Pos 0 /*!< RTC CTIME1: DOM Position */
+#define RTC_CTIME1_DOM_Msk (0x1fUL << RTC_CTIME1_DOM_Pos) /*!< RTC CTIME1: DOM Mask */
+#define RTC_CTIME1_MONTH_Pos 8 /*!< RTC CTIME1: MONTH Position */
+#define RTC_CTIME1_MONTH_Msk (0x0fUL << RTC_CTIME1_MONTH_Pos) /*!< RTC CTIME1: MONTH Mask */
+#define RTC_CTIME1_YEAR_Pos 16 /*!< RTC CTIME1: YEAR Position */
+#define RTC_CTIME1_YEAR_Msk (0x00000fffUL << RTC_CTIME1_YEAR_Pos) /*!< RTC CTIME1: YEAR Mask */
+
+// --------------------------------------- RTC_CTIME2 -------------------------------------------
+#define RTC_CTIME2_DOY_Pos 0 /*!< RTC CTIME2: DOY Position */
+#define RTC_CTIME2_DOY_Msk (0x00000fffUL << RTC_CTIME2_DOY_Pos) /*!< RTC CTIME2: DOY Mask */
+
+// ----------------------------------------- RTC_SEC --------------------------------------------
+#define RTC_SEC_SECONDS_Pos 0 /*!< RTC SEC: SECONDS Position */
+#define RTC_SEC_SECONDS_Msk (0x3fUL << RTC_SEC_SECONDS_Pos) /*!< RTC SEC: SECONDS Mask */
+
+// ----------------------------------------- RTC_MIN --------------------------------------------
+#define RTC_MIN_MINUTES_Pos 0 /*!< RTC MIN: MINUTES Position */
+#define RTC_MIN_MINUTES_Msk (0x3fUL << RTC_MIN_MINUTES_Pos) /*!< RTC MIN: MINUTES Mask */
+
+// ----------------------------------------- RTC_HRS --------------------------------------------
+#define RTC_HRS_HOURS_Pos 0 /*!< RTC HRS: HOURS Position */
+#define RTC_HRS_HOURS_Msk (0x1fUL << RTC_HRS_HOURS_Pos) /*!< RTC HRS: HOURS Mask */
+
+// ----------------------------------------- RTC_DOM --------------------------------------------
+#define RTC_DOM_DOM_Pos 0 /*!< RTC DOM: DOM Position */
+#define RTC_DOM_DOM_Msk (0x1fUL << RTC_DOM_DOM_Pos) /*!< RTC DOM: DOM Mask */
+
+// ----------------------------------------- RTC_DOW --------------------------------------------
+#define RTC_DOW_DOW_Pos 0 /*!< RTC DOW: DOW Position */
+#define RTC_DOW_DOW_Msk (0x07UL << RTC_DOW_DOW_Pos) /*!< RTC DOW: DOW Mask */
+
+// ----------------------------------------- RTC_DOY --------------------------------------------
+#define RTC_DOY_DOY_Pos 0 /*!< RTC DOY: DOY Position */
+#define RTC_DOY_DOY_Msk (0x000001ffUL << RTC_DOY_DOY_Pos) /*!< RTC DOY: DOY Mask */
+
+// ---------------------------------------- RTC_MONTH -------------------------------------------
+#define RTC_MONTH_MONTH_Pos 0 /*!< RTC MONTH: MONTH Position */
+#define RTC_MONTH_MONTH_Msk (0x0fUL << RTC_MONTH_MONTH_Pos) /*!< RTC MONTH: MONTH Mask */
+
+// ---------------------------------------- RTC_YEAR --------------------------------------------
+#define RTC_YEAR_YEAR_Pos 0 /*!< RTC YEAR: YEAR Position */
+#define RTC_YEAR_YEAR_Msk (0x00000fffUL << RTC_YEAR_YEAR_Pos) /*!< RTC YEAR: YEAR Mask */
+
+// ------------------------------------- RTC_CALIBRATION ----------------------------------------
+#define RTC_CALIBRATION_CALVAL_Pos 0 /*!< RTC CALIBRATION: CALVAL Position */
+#define RTC_CALIBRATION_CALVAL_Msk (0x0001ffffUL << RTC_CALIBRATION_CALVAL_Pos) /*!< RTC CALIBRATION: CALVAL Mask */
+#define RTC_CALIBRATION_CALDIR_Pos 17 /*!< RTC CALIBRATION: CALDIR Position */
+#define RTC_CALIBRATION_CALDIR_Msk (0x01UL << RTC_CALIBRATION_CALDIR_Pos) /*!< RTC CALIBRATION: CALDIR Mask */
+
+// ---------------------------------------- RTC_ASEC --------------------------------------------
+#define RTC_ASEC_SECONDS_Pos 0 /*!< RTC ASEC: SECONDS Position */
+#define RTC_ASEC_SECONDS_Msk (0x3fUL << RTC_ASEC_SECONDS_Pos) /*!< RTC ASEC: SECONDS Mask */
+
+// ---------------------------------------- RTC_AMIN --------------------------------------------
+#define RTC_AMIN_MINUTES_Pos 0 /*!< RTC AMIN: MINUTES Position */
+#define RTC_AMIN_MINUTES_Msk (0x3fUL << RTC_AMIN_MINUTES_Pos) /*!< RTC AMIN: MINUTES Mask */
+
+// ---------------------------------------- RTC_AHRS --------------------------------------------
+#define RTC_AHRS_HOURS_Pos 0 /*!< RTC AHRS: HOURS Position */
+#define RTC_AHRS_HOURS_Msk (0x1fUL << RTC_AHRS_HOURS_Pos) /*!< RTC AHRS: HOURS Mask */
+
+// ---------------------------------------- RTC_ADOM --------------------------------------------
+#define RTC_ADOM_DOM_Pos 0 /*!< RTC ADOM: DOM Position */
+#define RTC_ADOM_DOM_Msk (0x1fUL << RTC_ADOM_DOM_Pos) /*!< RTC ADOM: DOM Mask */
+
+// ---------------------------------------- RTC_ADOW --------------------------------------------
+#define RTC_ADOW_DOW_Pos 0 /*!< RTC ADOW: DOW Position */
+#define RTC_ADOW_DOW_Msk (0x07UL << RTC_ADOW_DOW_Pos) /*!< RTC ADOW: DOW Mask */
+
+// ---------------------------------------- RTC_ADOY --------------------------------------------
+#define RTC_ADOY_DOY_Pos 0 /*!< RTC ADOY: DOY Position */
+#define RTC_ADOY_DOY_Msk (0x000001ffUL << RTC_ADOY_DOY_Pos) /*!< RTC ADOY: DOY Mask */
+
+// ---------------------------------------- RTC_AMON --------------------------------------------
+#define RTC_AMON_MONTH_Pos 0 /*!< RTC AMON: MONTH Position */
+#define RTC_AMON_MONTH_Msk (0x0fUL << RTC_AMON_MONTH_Pos) /*!< RTC AMON: MONTH Mask */
+
+// ---------------------------------------- RTC_AYRS --------------------------------------------
+#define RTC_AYRS_YEAR_Pos 0 /*!< RTC AYRS: YEAR Position */
+#define RTC_AYRS_YEAR_Msk (0x00000fffUL << RTC_AYRS_YEAR_Pos) /*!< RTC AYRS: YEAR Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- CGU Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -------------------------------------- CGU_FREQ_MON ------------------------------------------
+#define CGU_FREQ_MON_RCNT_Pos 0 /*!< CGU FREQ_MON: RCNT Position */
+#define CGU_FREQ_MON_RCNT_Msk (0x000001ffUL << CGU_FREQ_MON_RCNT_Pos) /*!< CGU FREQ_MON: RCNT Mask */
+#define CGU_FREQ_MON_FCNT_Pos 9 /*!< CGU FREQ_MON: FCNT Position */
+#define CGU_FREQ_MON_FCNT_Msk (0x00003fffUL << CGU_FREQ_MON_FCNT_Pos) /*!< CGU FREQ_MON: FCNT Mask */
+#define CGU_FREQ_MON_MEAS_Pos 23 /*!< CGU FREQ_MON: MEAS Position */
+#define CGU_FREQ_MON_MEAS_Msk (0x01UL << CGU_FREQ_MON_MEAS_Pos) /*!< CGU FREQ_MON: MEAS Mask */
+#define CGU_FREQ_MON_CLK_SEL_Pos 24 /*!< CGU FREQ_MON: CLK_SEL Position */
+#define CGU_FREQ_MON_CLK_SEL_Msk (0x1fUL << CGU_FREQ_MON_CLK_SEL_Pos) /*!< CGU FREQ_MON: CLK_SEL Mask */
+
+// ------------------------------------ CGU_XTAL_OSC_CTRL ---------------------------------------
+#define CGU_XTAL_OSC_CTRL_ENABLE_Pos 0 /*!< CGU XTAL_OSC_CTRL: ENABLE Position */
+#define CGU_XTAL_OSC_CTRL_ENABLE_Msk (0x01UL << CGU_XTAL_OSC_CTRL_ENABLE_Pos) /*!< CGU XTAL_OSC_CTRL: ENABLE Mask */
+#define CGU_XTAL_OSC_CTRL_BYPASS_Pos 1 /*!< CGU XTAL_OSC_CTRL: BYPASS Position */
+#define CGU_XTAL_OSC_CTRL_BYPASS_Msk (0x01UL << CGU_XTAL_OSC_CTRL_BYPASS_Pos) /*!< CGU XTAL_OSC_CTRL: BYPASS Mask */
+#define CGU_XTAL_OSC_CTRL_HF_Pos 2 /*!< CGU XTAL_OSC_CTRL: HF Position */
+#define CGU_XTAL_OSC_CTRL_HF_Msk (0x01UL << CGU_XTAL_OSC_CTRL_HF_Pos) /*!< CGU XTAL_OSC_CTRL: HF Mask */
+
+// ------------------------------------ CGU_PLL0USB_STAT ----------------------------------------
+#define CGU_PLL0USB_STAT_LOCK_Pos 0 /*!< CGU PLL0USB_STAT: LOCK Position */
+#define CGU_PLL0USB_STAT_LOCK_Msk (0x01UL << CGU_PLL0USB_STAT_LOCK_Pos) /*!< CGU PLL0USB_STAT: LOCK Mask */
+#define CGU_PLL0USB_STAT_FR_Pos 1 /*!< CGU PLL0USB_STAT: FR Position */
+#define CGU_PLL0USB_STAT_FR_Msk (0x01UL << CGU_PLL0USB_STAT_FR_Pos) /*!< CGU PLL0USB_STAT: FR Mask */
+
+// ------------------------------------ CGU_PLL0USB_CTRL ----------------------------------------
+#define CGU_PLL0USB_CTRL_PD_Pos 0 /*!< CGU PLL0USB_CTRL: PD Position */
+#define CGU_PLL0USB_CTRL_PD_Msk (0x01UL << CGU_PLL0USB_CTRL_PD_Pos) /*!< CGU PLL0USB_CTRL: PD Mask */
+#define CGU_PLL0USB_CTRL_BYPASS_Pos 1 /*!< CGU PLL0USB_CTRL: BYPASS Position */
+#define CGU_PLL0USB_CTRL_BYPASS_Msk (0x01UL << CGU_PLL0USB_CTRL_BYPASS_Pos) /*!< CGU PLL0USB_CTRL: BYPASS Mask */
+#define CGU_PLL0USB_CTRL_DIRECTI_Pos 2 /*!< CGU PLL0USB_CTRL: DIRECTI Position */
+#define CGU_PLL0USB_CTRL_DIRECTI_Msk (0x01UL << CGU_PLL0USB_CTRL_DIRECTI_Pos) /*!< CGU PLL0USB_CTRL: DIRECTI Mask */
+#define CGU_PLL0USB_CTRL_DIRECTO_Pos 3 /*!< CGU PLL0USB_CTRL: DIRECTO Position */
+#define CGU_PLL0USB_CTRL_DIRECTO_Msk (0x01UL << CGU_PLL0USB_CTRL_DIRECTO_Pos) /*!< CGU PLL0USB_CTRL: DIRECTO Mask */
+#define CGU_PLL0USB_CTRL_CLKEN_Pos 4 /*!< CGU PLL0USB_CTRL: CLKEN Position */
+#define CGU_PLL0USB_CTRL_CLKEN_Msk (0x01UL << CGU_PLL0USB_CTRL_CLKEN_Pos) /*!< CGU PLL0USB_CTRL: CLKEN Mask */
+#define CGU_PLL0USB_CTRL_FRM_Pos 6 /*!< CGU PLL0USB_CTRL: FRM Position */
+#define CGU_PLL0USB_CTRL_FRM_Msk (0x01UL << CGU_PLL0USB_CTRL_FRM_Pos) /*!< CGU PLL0USB_CTRL: FRM Mask */
+#define CGU_PLL0USB_CTRL_AUTOBLOCK_Pos 11 /*!< CGU PLL0USB_CTRL: AUTOBLOCK Position */
+#define CGU_PLL0USB_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_PLL0USB_CTRL_AUTOBLOCK_Pos) /*!< CGU PLL0USB_CTRL: AUTOBLOCK Mask */
+#define CGU_PLL0USB_CTRL_CLK_SEL_Pos 24 /*!< CGU PLL0USB_CTRL: CLK_SEL Position */
+#define CGU_PLL0USB_CTRL_CLK_SEL_Msk (0x1fUL << CGU_PLL0USB_CTRL_CLK_SEL_Pos) /*!< CGU PLL0USB_CTRL: CLK_SEL Mask */
+
+// ------------------------------------ CGU_PLL0USB_MDIV ----------------------------------------
+#define CGU_PLL0USB_MDIV_MDEC_Pos 0 /*!< CGU PLL0USB_MDIV: MDEC Position */
+#define CGU_PLL0USB_MDIV_MDEC_Msk (0x0001ffffUL << CGU_PLL0USB_MDIV_MDEC_Pos) /*!< CGU PLL0USB_MDIV: MDEC Mask */
+#define CGU_PLL0USB_MDIV_SELP_Pos 17 /*!< CGU PLL0USB_MDIV: SELP Position */
+#define CGU_PLL0USB_MDIV_SELP_Msk (0x1fUL << CGU_PLL0USB_MDIV_SELP_Pos) /*!< CGU PLL0USB_MDIV: SELP Mask */
+#define CGU_PLL0USB_MDIV_SELI_Pos 22 /*!< CGU PLL0USB_MDIV: SELI Position */
+#define CGU_PLL0USB_MDIV_SELI_Msk (0x3fUL << CGU_PLL0USB_MDIV_SELI_Pos) /*!< CGU PLL0USB_MDIV: SELI Mask */
+#define CGU_PLL0USB_MDIV_SELR_Pos 28 /*!< CGU PLL0USB_MDIV: SELR Position */
+#define CGU_PLL0USB_MDIV_SELR_Msk (0x0fUL << CGU_PLL0USB_MDIV_SELR_Pos) /*!< CGU PLL0USB_MDIV: SELR Mask */
+
+// ----------------------------------- CGU_PLL0USB_NP_DIV ---------------------------------------
+#define CGU_PLL0USB_NP_DIV_PDEC_Pos 0 /*!< CGU PLL0USB_NP_DIV: PDEC Position */
+#define CGU_PLL0USB_NP_DIV_PDEC_Msk (0x7fUL << CGU_PLL0USB_NP_DIV_PDEC_Pos) /*!< CGU PLL0USB_NP_DIV: PDEC Mask */
+#define CGU_PLL0USB_NP_DIV_NDEC_Pos 12 /*!< CGU PLL0USB_NP_DIV: NDEC Position */
+#define CGU_PLL0USB_NP_DIV_NDEC_Msk (0x000003ffUL << CGU_PLL0USB_NP_DIV_NDEC_Pos) /*!< CGU PLL0USB_NP_DIV: NDEC Mask */
+
+// ----------------------------------- CGU_PLL0AUDIO_STAT ---------------------------------------
+#define CGU_PLL0AUDIO_STAT_LOCK_Pos 0 /*!< CGU PLL0AUDIO_STAT: LOCK Position */
+#define CGU_PLL0AUDIO_STAT_LOCK_Msk (0x01UL << CGU_PLL0AUDIO_STAT_LOCK_Pos) /*!< CGU PLL0AUDIO_STAT: LOCK Mask */
+#define CGU_PLL0AUDIO_STAT_FR_Pos 1 /*!< CGU PLL0AUDIO_STAT: FR Position */
+#define CGU_PLL0AUDIO_STAT_FR_Msk (0x01UL << CGU_PLL0AUDIO_STAT_FR_Pos) /*!< CGU PLL0AUDIO_STAT: FR Mask */
+
+// ----------------------------------- CGU_PLL0AUDIO_CTRL ---------------------------------------
+#define CGU_PLL0AUDIO_CTRL_PD_Pos 0 /*!< CGU PLL0AUDIO_CTRL: PD Position */
+#define CGU_PLL0AUDIO_CTRL_PD_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_PD_Pos) /*!< CGU PLL0AUDIO_CTRL: PD Mask */
+#define CGU_PLL0AUDIO_CTRL_BYPASS_Pos 1 /*!< CGU PLL0AUDIO_CTRL: BYPASS Position */
+#define CGU_PLL0AUDIO_CTRL_BYPASS_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_BYPASS_Pos) /*!< CGU PLL0AUDIO_CTRL: BYPASS Mask */
+#define CGU_PLL0AUDIO_CTRL_DIRECTI_Pos 2 /*!< CGU PLL0AUDIO_CTRL: DIRECTI Position */
+#define CGU_PLL0AUDIO_CTRL_DIRECTI_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_DIRECTI_Pos) /*!< CGU PLL0AUDIO_CTRL: DIRECTI Mask */
+#define CGU_PLL0AUDIO_CTRL_DIRECTO_Pos 3 /*!< CGU PLL0AUDIO_CTRL: DIRECTO Position */
+#define CGU_PLL0AUDIO_CTRL_DIRECTO_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_DIRECTO_Pos) /*!< CGU PLL0AUDIO_CTRL: DIRECTO Mask */
+#define CGU_PLL0AUDIO_CTRL_CLKEN_Pos 4 /*!< CGU PLL0AUDIO_CTRL: CLKEN Position */
+#define CGU_PLL0AUDIO_CTRL_CLKEN_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_CLKEN_Pos) /*!< CGU PLL0AUDIO_CTRL: CLKEN Mask */
+#define CGU_PLL0AUDIO_CTRL_FRM_Pos 6 /*!< CGU PLL0AUDIO_CTRL: FRM Position */
+#define CGU_PLL0AUDIO_CTRL_FRM_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_FRM_Pos) /*!< CGU PLL0AUDIO_CTRL: FRM Mask */
+#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Pos 11 /*!< CGU PLL0AUDIO_CTRL: AUTOBLOCK Position */
+#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Pos) /*!< CGU PLL0AUDIO_CTRL: AUTOBLOCK Mask */
+#define CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Pos 12 /*!< CGU PLL0AUDIO_CTRL: PLLFRAQ_REQ Position */
+#define CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Pos) /*!< CGU PLL0AUDIO_CTRL: PLLFRAQ_REQ Mask */
+#define CGU_PLL0AUDIO_CTRL_SEL_EXT_Pos 13 /*!< CGU PLL0AUDIO_CTRL: SEL_EXT Position */
+#define CGU_PLL0AUDIO_CTRL_SEL_EXT_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_SEL_EXT_Pos) /*!< CGU PLL0AUDIO_CTRL: SEL_EXT Mask */
+#define CGU_PLL0AUDIO_CTRL_MOD_PD_Pos 14 /*!< CGU PLL0AUDIO_CTRL: MOD_PD Position */
+#define CGU_PLL0AUDIO_CTRL_MOD_PD_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_MOD_PD_Pos) /*!< CGU PLL0AUDIO_CTRL: MOD_PD Mask */
+#define CGU_PLL0AUDIO_CTRL_CLK_SEL_Pos 24 /*!< CGU PLL0AUDIO_CTRL: CLK_SEL Position */
+#define CGU_PLL0AUDIO_CTRL_CLK_SEL_Msk (0x1fUL << CGU_PLL0AUDIO_CTRL_CLK_SEL_Pos) /*!< CGU PLL0AUDIO_CTRL: CLK_SEL Mask */
+
+// ----------------------------------- CGU_PLL0AUDIO_MDIV ---------------------------------------
+#define CGU_PLL0AUDIO_MDIV_MDEC_Pos 0 /*!< CGU PLL0AUDIO_MDIV: MDEC Position */
+#define CGU_PLL0AUDIO_MDIV_MDEC_Msk (0x0001ffffUL << CGU_PLL0AUDIO_MDIV_MDEC_Pos) /*!< CGU PLL0AUDIO_MDIV: MDEC Mask */
+
+// ---------------------------------- CGU_PLL0AUDIO_NP_DIV --------------------------------------
+#define CGU_PLL0AUDIO_NP_DIV_PDEC_Pos 0 /*!< CGU PLL0AUDIO_NP_DIV: PDEC Position */
+#define CGU_PLL0AUDIO_NP_DIV_PDEC_Msk (0x7fUL << CGU_PLL0AUDIO_NP_DIV_PDEC_Pos) /*!< CGU PLL0AUDIO_NP_DIV: PDEC Mask */
+#define CGU_PLL0AUDIO_NP_DIV_NDEC_Pos 12 /*!< CGU PLL0AUDIO_NP_DIV: NDEC Position */
+#define CGU_PLL0AUDIO_NP_DIV_NDEC_Msk (0x000003ffUL << CGU_PLL0AUDIO_NP_DIV_NDEC_Pos) /*!< CGU PLL0AUDIO_NP_DIV: NDEC Mask */
+
+// ----------------------------------- CGU_PLL0AUDIO_FRAC ---------------------------------------
+#define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Pos 0 /*!< CGU PLL0AUDIO_FRAC: PLLFRACT_CTRL Position */
+#define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Msk (0x003fffffUL << CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Pos) /*!< CGU PLL0AUDIO_FRAC: PLLFRACT_CTRL Mask */
+
+// -------------------------------------- CGU_PLL1_STAT -----------------------------------------
+#define CGU_PLL1_STAT_LOCK_Pos 0 /*!< CGU PLL1_STAT: LOCK Position */
+#define CGU_PLL1_STAT_LOCK_Msk (0x01UL << CGU_PLL1_STAT_LOCK_Pos) /*!< CGU PLL1_STAT: LOCK Mask */
+
+// -------------------------------------- CGU_PLL1_CTRL -----------------------------------------
+#define CGU_PLL1_CTRL_PD_Pos 0 /*!< CGU PLL1_CTRL: PD Position */
+#define CGU_PLL1_CTRL_PD_Msk (0x01UL << CGU_PLL1_CTRL_PD_Pos) /*!< CGU PLL1_CTRL: PD Mask */
+#define CGU_PLL1_CTRL_BYPASS_Pos 1 /*!< CGU PLL1_CTRL: BYPASS Position */
+#define CGU_PLL1_CTRL_BYPASS_Msk (0x01UL << CGU_PLL1_CTRL_BYPASS_Pos) /*!< CGU PLL1_CTRL: BYPASS Mask */
+#define CGU_PLL1_CTRL_FBSEL_Pos 6 /*!< CGU PLL1_CTRL: FBSEL Position */
+#define CGU_PLL1_CTRL_FBSEL_Msk (0x01UL << CGU_PLL1_CTRL_FBSEL_Pos) /*!< CGU PLL1_CTRL: FBSEL Mask */
+#define CGU_PLL1_CTRL_DIRECT_Pos 7 /*!< CGU PLL1_CTRL: DIRECT Position */
+#define CGU_PLL1_CTRL_DIRECT_Msk (0x01UL << CGU_PLL1_CTRL_DIRECT_Pos) /*!< CGU PLL1_CTRL: DIRECT Mask */
+#define CGU_PLL1_CTRL_PSEL_Pos 8 /*!< CGU PLL1_CTRL: PSEL Position */
+#define CGU_PLL1_CTRL_PSEL_Msk (0x03UL << CGU_PLL1_CTRL_PSEL_Pos) /*!< CGU PLL1_CTRL: PSEL Mask */
+#define CGU_PLL1_CTRL_AUTOBLOCK_Pos 11 /*!< CGU PLL1_CTRL: AUTOBLOCK Position */
+#define CGU_PLL1_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_PLL1_CTRL_AUTOBLOCK_Pos) /*!< CGU PLL1_CTRL: AUTOBLOCK Mask */
+#define CGU_PLL1_CTRL_NSEL_Pos 12 /*!< CGU PLL1_CTRL: NSEL Position */
+#define CGU_PLL1_CTRL_NSEL_Msk (0x03UL << CGU_PLL1_CTRL_NSEL_Pos) /*!< CGU PLL1_CTRL: NSEL Mask */
+#define CGU_PLL1_CTRL_MSEL_Pos 16 /*!< CGU PLL1_CTRL: MSEL Position */
+#define CGU_PLL1_CTRL_MSEL_Msk (0x000000ffUL << CGU_PLL1_CTRL_MSEL_Pos) /*!< CGU PLL1_CTRL: MSEL Mask */
+#define CGU_PLL1_CTRL_CLK_SEL_Pos 24 /*!< CGU PLL1_CTRL: CLK_SEL Position */
+#define CGU_PLL1_CTRL_CLK_SEL_Msk (0x1fUL << CGU_PLL1_CTRL_CLK_SEL_Pos) /*!< CGU PLL1_CTRL: CLK_SEL Mask */
+
+// ------------------------------------- CGU_IDIVA_CTRL -----------------------------------------
+#define CGU_IDIVA_CTRL_PD_Pos 0 /*!< CGU IDIVA_CTRL: PD Position */
+#define CGU_IDIVA_CTRL_PD_Msk (0x01UL << CGU_IDIVA_CTRL_PD_Pos) /*!< CGU IDIVA_CTRL: PD Mask */
+#define CGU_IDIVA_CTRL_IDIV_Pos 2 /*!< CGU IDIVA_CTRL: IDIV Position */
+#define CGU_IDIVA_CTRL_IDIV_Msk (0x03UL << CGU_IDIVA_CTRL_IDIV_Pos) /*!< CGU IDIVA_CTRL: IDIV Mask */
+#define CGU_IDIVA_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVA_CTRL: AUTOBLOCK Position */
+#define CGU_IDIVA_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVA_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVA_CTRL: AUTOBLOCK Mask */
+#define CGU_IDIVA_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVA_CTRL: CLK_SEL Position */
+#define CGU_IDIVA_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVA_CTRL_CLK_SEL_Pos) /*!< CGU IDIVA_CTRL: CLK_SEL Mask */
+
+// ------------------------------------- CGU_IDIVB_CTRL -----------------------------------------
+#define CGU_IDIVB_CTRL_PD_Pos 0 /*!< CGU IDIVB_CTRL: PD Position */
+#define CGU_IDIVB_CTRL_PD_Msk (0x01UL << CGU_IDIVB_CTRL_PD_Pos) /*!< CGU IDIVB_CTRL: PD Mask */
+#define CGU_IDIVB_CTRL_IDIV_Pos 2 /*!< CGU IDIVB_CTRL: IDIV Position */
+#define CGU_IDIVB_CTRL_IDIV_Msk (0x0fUL << CGU_IDIVB_CTRL_IDIV_Pos) /*!< CGU IDIVB_CTRL: IDIV Mask */
+#define CGU_IDIVB_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVB_CTRL: AUTOBLOCK Position */
+#define CGU_IDIVB_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVB_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVB_CTRL: AUTOBLOCK Mask */
+#define CGU_IDIVB_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVB_CTRL: CLK_SEL Position */
+#define CGU_IDIVB_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVB_CTRL_CLK_SEL_Pos) /*!< CGU IDIVB_CTRL: CLK_SEL Mask */
+
+// ------------------------------------- CGU_IDIVE_CTRL -----------------------------------------
+#define CGU_IDIVE_CTRL_PD_Pos 0 /*!< CGU IDIVE_CTRL: PD Position */
+#define CGU_IDIVE_CTRL_PD_Msk (0x01UL << CGU_IDIVE_CTRL_PD_Pos) /*!< CGU IDIVE_CTRL: PD Mask */
+#define CGU_IDIVE_CTRL_IDIV_Pos 2 /*!< CGU IDIVE_CTRL: IDIV Position */
+#define CGU_IDIVE_CTRL_IDIV_Msk (0x000000ffUL << CGU_IDIVE_CTRL_IDIV_Pos) /*!< CGU IDIVE_CTRL: IDIV Mask */
+#define CGU_IDIVE_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVE_CTRL: AUTOBLOCK Position */
+#define CGU_IDIVE_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVE_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVE_CTRL: AUTOBLOCK Mask */
+#define CGU_IDIVE_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVE_CTRL: CLK_SEL Position */
+#define CGU_IDIVE_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVE_CTRL_CLK_SEL_Pos) /*!< CGU IDIVE_CTRL: CLK_SEL Mask */
+
+// ------------------------------------ CGU_BASE_SAFE_CLK ---------------------------------------
+#define CGU_BASE_SAFE_CLK_PD_Pos 0 /*!< CGU BASE_SAFE_CLK: PD Position */
+#define CGU_BASE_SAFE_CLK_PD_Msk (0x01UL << CGU_BASE_SAFE_CLK_PD_Pos) /*!< CGU BASE_SAFE_CLK: PD Mask */
+#define CGU_BASE_SAFE_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SAFE_CLK: AUTOBLOCK Position */
+#define CGU_BASE_SAFE_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SAFE_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SAFE_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_SAFE_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SAFE_CLK: CLK_SEL Position */
+#define CGU_BASE_SAFE_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SAFE_CLK_CLK_SEL_Pos) /*!< CGU BASE_SAFE_CLK: CLK_SEL Mask */
+
+// ------------------------------------ CGU_BASE_USB0_CLK ---------------------------------------
+#define CGU_BASE_USB0_CLK_PD_Pos 0 /*!< CGU BASE_USB0_CLK: PD Position */
+#define CGU_BASE_USB0_CLK_PD_Msk (0x01UL << CGU_BASE_USB0_CLK_PD_Pos) /*!< CGU BASE_USB0_CLK: PD Mask */
+#define CGU_BASE_USB0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_USB0_CLK: AUTOBLOCK Position */
+#define CGU_BASE_USB0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_USB0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_USB0_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_USB0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_USB0_CLK: CLK_SEL Position */
+#define CGU_BASE_USB0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_USB0_CLK_CLK_SEL_Pos) /*!< CGU BASE_USB0_CLK: CLK_SEL Mask */
+
+// ----------------------------------- CGU_BASE_PERIPH_CLK --------------------------------------
+#define CGU_BASE_PERIPH_CLK_PD_Pos 0 /*!< CGU BASE_PERIPH_CLK: PD Position */
+#define CGU_BASE_PERIPH_CLK_PD_Msk (0x01UL << CGU_BASE_PERIPH_CLK_PD_Pos) /*!< CGU BASE_PERIPH_CLK: PD Mask */
+#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_PERIPH_CLK: AUTOBLOCK Position */
+#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_PERIPH_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_PERIPH_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_PERIPH_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_PERIPH_CLK: CLK_SEL Position */
+#define CGU_BASE_PERIPH_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_PERIPH_CLK_CLK_SEL_Pos) /*!< CGU BASE_PERIPH_CLK: CLK_SEL Mask */
+
+// ------------------------------------ CGU_BASE_USB1_CLK ---------------------------------------
+#define CGU_BASE_USB1_CLK_PD_Pos 0 /*!< CGU BASE_USB1_CLK: PD Position */
+#define CGU_BASE_USB1_CLK_PD_Msk (0x01UL << CGU_BASE_USB1_CLK_PD_Pos) /*!< CGU BASE_USB1_CLK: PD Mask */
+#define CGU_BASE_USB1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_USB1_CLK: AUTOBLOCK Position */
+#define CGU_BASE_USB1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_USB1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_USB1_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_USB1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_USB1_CLK: CLK_SEL Position */
+#define CGU_BASE_USB1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_USB1_CLK_CLK_SEL_Pos) /*!< CGU BASE_USB1_CLK: CLK_SEL Mask */
+
+// ------------------------------------- CGU_BASE_M4_CLK ----------------------------------------
+#define CGU_BASE_M4_CLK_PD_Pos 0 /*!< CGU BASE_M4_CLK: PD Position */
+#define CGU_BASE_M4_CLK_PD_Msk (0x01UL << CGU_BASE_M4_CLK_PD_Pos) /*!< CGU BASE_M4_CLK: PD Mask */
+#define CGU_BASE_M4_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_M4_CLK: AUTOBLOCK Position */
+#define CGU_BASE_M4_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_M4_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_M4_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_M4_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_M4_CLK: CLK_SEL Position */
+#define CGU_BASE_M4_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_M4_CLK_CLK_SEL_Pos) /*!< CGU BASE_M4_CLK: CLK_SEL Mask */
+
+// ----------------------------------- CGU_BASE_SPIFI_CLK ---------------------------------------
+#define CGU_BASE_SPIFI_CLK_PD_Pos 0 /*!< CGU BASE_SPIFI_CLK: PD Position */
+#define CGU_BASE_SPIFI_CLK_PD_Msk (0x01UL << CGU_BASE_SPIFI_CLK_PD_Pos) /*!< CGU BASE_SPIFI_CLK: PD Mask */
+#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SPIFI_CLK: AUTOBLOCK Position */
+#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SPIFI_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SPIFI_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_SPIFI_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SPIFI_CLK: CLK_SEL Position */
+#define CGU_BASE_SPIFI_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SPIFI_CLK_CLK_SEL_Pos) /*!< CGU BASE_SPIFI_CLK: CLK_SEL Mask */
+
+// ------------------------------------ CGU_BASE_SPI_CLK ----------------------------------------
+#define CGU_BASE_SPI_CLK_PD_Pos 0 /*!< CGU BASE_SPI_CLK: PD Position */
+#define CGU_BASE_SPI_CLK_PD_Msk (0x01UL << CGU_BASE_SPI_CLK_PD_Pos) /*!< CGU BASE_SPI_CLK: PD Mask */
+#define CGU_BASE_SPI_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SPI_CLK: AUTOBLOCK Position */
+#define CGU_BASE_SPI_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SPI_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SPI_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_SPI_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SPI_CLK: CLK_SEL Position */
+#define CGU_BASE_SPI_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SPI_CLK_CLK_SEL_Pos) /*!< CGU BASE_SPI_CLK: CLK_SEL Mask */
+
+// ----------------------------------- CGU_BASE_PHY_RX_CLK --------------------------------------
+#define CGU_BASE_PHY_RX_CLK_PD_Pos 0 /*!< CGU BASE_PHY_RX_CLK: PD Position */
+#define CGU_BASE_PHY_RX_CLK_PD_Msk (0x01UL << CGU_BASE_PHY_RX_CLK_PD_Pos) /*!< CGU BASE_PHY_RX_CLK: PD Mask */
+#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_PHY_RX_CLK: AUTOBLOCK Position */
+#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_PHY_RX_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_PHY_RX_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_PHY_RX_CLK: CLK_SEL Position */
+#define CGU_BASE_PHY_RX_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_PHY_RX_CLK_CLK_SEL_Pos) /*!< CGU BASE_PHY_RX_CLK: CLK_SEL Mask */
+
+// ----------------------------------- CGU_BASE_PHY_TX_CLK --------------------------------------
+#define CGU_BASE_PHY_TX_CLK_PD_Pos 0 /*!< CGU BASE_PHY_TX_CLK: PD Position */
+#define CGU_BASE_PHY_TX_CLK_PD_Msk (0x01UL << CGU_BASE_PHY_TX_CLK_PD_Pos) /*!< CGU BASE_PHY_TX_CLK: PD Mask */
+#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_PHY_TX_CLK: AUTOBLOCK Position */
+#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_PHY_TX_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_PHY_TX_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_PHY_TX_CLK: CLK_SEL Position */
+#define CGU_BASE_PHY_TX_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_PHY_TX_CLK_CLK_SEL_Pos) /*!< CGU BASE_PHY_TX_CLK: CLK_SEL Mask */
+
+// ------------------------------------ CGU_BASE_APB1_CLK ---------------------------------------
+#define CGU_BASE_APB1_CLK_PD_Pos 0 /*!< CGU BASE_APB1_CLK: PD Position */
+#define CGU_BASE_APB1_CLK_PD_Msk (0x01UL << CGU_BASE_APB1_CLK_PD_Pos) /*!< CGU BASE_APB1_CLK: PD Mask */
+#define CGU_BASE_APB1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_APB1_CLK: AUTOBLOCK Position */
+#define CGU_BASE_APB1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_APB1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_APB1_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_APB1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_APB1_CLK: CLK_SEL Position */
+#define CGU_BASE_APB1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_APB1_CLK_CLK_SEL_Pos) /*!< CGU BASE_APB1_CLK: CLK_SEL Mask */
+
+// ------------------------------------ CGU_BASE_APB3_CLK ---------------------------------------
+#define CGU_BASE_APB3_CLK_PD_Pos 0 /*!< CGU BASE_APB3_CLK: PD Position */
+#define CGU_BASE_APB3_CLK_PD_Msk (0x01UL << CGU_BASE_APB3_CLK_PD_Pos) /*!< CGU BASE_APB3_CLK: PD Mask */
+#define CGU_BASE_APB3_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_APB3_CLK: AUTOBLOCK Position */
+#define CGU_BASE_APB3_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_APB3_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_APB3_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_APB3_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_APB3_CLK: CLK_SEL Position */
+#define CGU_BASE_APB3_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_APB3_CLK_CLK_SEL_Pos) /*!< CGU BASE_APB3_CLK: CLK_SEL Mask */
+
+// ------------------------------------ CGU_BASE_LCD_CLK ----------------------------------------
+#define CGU_BASE_LCD_CLK_PD_Pos 0 /*!< CGU BASE_LCD_CLK: PD Position */
+#define CGU_BASE_LCD_CLK_PD_Msk (0x01UL << CGU_BASE_LCD_CLK_PD_Pos) /*!< CGU BASE_LCD_CLK: PD Mask */
+#define CGU_BASE_LCD_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_LCD_CLK: AUTOBLOCK Position */
+#define CGU_BASE_LCD_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_LCD_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_LCD_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_LCD_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_LCD_CLK: CLK_SEL Position */
+#define CGU_BASE_LCD_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_LCD_CLK_CLK_SEL_Pos) /*!< CGU BASE_LCD_CLK: CLK_SEL Mask */
+
+// ------------------------------------ CGU_BASE_SDIO_CLK ---------------------------------------
+#define CGU_BASE_SDIO_CLK_PD_Pos 0 /*!< CGU BASE_SDIO_CLK: PD Position */
+#define CGU_BASE_SDIO_CLK_PD_Msk (0x01UL << CGU_BASE_SDIO_CLK_PD_Pos) /*!< CGU BASE_SDIO_CLK: PD Mask */
+#define CGU_BASE_SDIO_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SDIO_CLK: AUTOBLOCK Position */
+#define CGU_BASE_SDIO_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SDIO_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SDIO_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_SDIO_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SDIO_CLK: CLK_SEL Position */
+#define CGU_BASE_SDIO_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SDIO_CLK_CLK_SEL_Pos) /*!< CGU BASE_SDIO_CLK: CLK_SEL Mask */
+
+// ------------------------------------ CGU_BASE_SSP0_CLK ---------------------------------------
+#define CGU_BASE_SSP0_CLK_PD_Pos 0 /*!< CGU BASE_SSP0_CLK: PD Position */
+#define CGU_BASE_SSP0_CLK_PD_Msk (0x01UL << CGU_BASE_SSP0_CLK_PD_Pos) /*!< CGU BASE_SSP0_CLK: PD Mask */
+#define CGU_BASE_SSP0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SSP0_CLK: AUTOBLOCK Position */
+#define CGU_BASE_SSP0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SSP0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SSP0_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_SSP0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SSP0_CLK: CLK_SEL Position */
+#define CGU_BASE_SSP0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SSP0_CLK_CLK_SEL_Pos) /*!< CGU BASE_SSP0_CLK: CLK_SEL Mask */
+
+// ------------------------------------ CGU_BASE_SSP1_CLK ---------------------------------------
+#define CGU_BASE_SSP1_CLK_PD_Pos 0 /*!< CGU BASE_SSP1_CLK: PD Position */
+#define CGU_BASE_SSP1_CLK_PD_Msk (0x01UL << CGU_BASE_SSP1_CLK_PD_Pos) /*!< CGU BASE_SSP1_CLK: PD Mask */
+#define CGU_BASE_SSP1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SSP1_CLK: AUTOBLOCK Position */
+#define CGU_BASE_SSP1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SSP1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SSP1_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_SSP1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SSP1_CLK: CLK_SEL Position */
+#define CGU_BASE_SSP1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SSP1_CLK_CLK_SEL_Pos) /*!< CGU BASE_SSP1_CLK: CLK_SEL Mask */
+
+// ----------------------------------- CGU_BASE_UART0_CLK ---------------------------------------
+#define CGU_BASE_UART0_CLK_PD_Pos 0 /*!< CGU BASE_UART0_CLK: PD Position */
+#define CGU_BASE_UART0_CLK_PD_Msk (0x01UL << CGU_BASE_UART0_CLK_PD_Pos) /*!< CGU BASE_UART0_CLK: PD Mask */
+#define CGU_BASE_UART0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART0_CLK: AUTOBLOCK Position */
+#define CGU_BASE_UART0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART0_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_UART0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART0_CLK: CLK_SEL Position */
+#define CGU_BASE_UART0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART0_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART0_CLK: CLK_SEL Mask */
+
+// ----------------------------------- CGU_BASE_UART1_CLK ---------------------------------------
+#define CGU_BASE_UART1_CLK_PD_Pos 0 /*!< CGU BASE_UART1_CLK: PD Position */
+#define CGU_BASE_UART1_CLK_PD_Msk (0x01UL << CGU_BASE_UART1_CLK_PD_Pos) /*!< CGU BASE_UART1_CLK: PD Mask */
+#define CGU_BASE_UART1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART1_CLK: AUTOBLOCK Position */
+#define CGU_BASE_UART1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART1_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_UART1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART1_CLK: CLK_SEL Position */
+#define CGU_BASE_UART1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART1_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART1_CLK: CLK_SEL Mask */
+
+// ----------------------------------- CGU_BASE_UART2_CLK ---------------------------------------
+#define CGU_BASE_UART2_CLK_PD_Pos 0 /*!< CGU BASE_UART2_CLK: PD Position */
+#define CGU_BASE_UART2_CLK_PD_Msk (0x01UL << CGU_BASE_UART2_CLK_PD_Pos) /*!< CGU BASE_UART2_CLK: PD Mask */
+#define CGU_BASE_UART2_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART2_CLK: AUTOBLOCK Position */
+#define CGU_BASE_UART2_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART2_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART2_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_UART2_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART2_CLK: CLK_SEL Position */
+#define CGU_BASE_UART2_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART2_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART2_CLK: CLK_SEL Mask */
+
+// ----------------------------------- CGU_BASE_UART3_CLK ---------------------------------------
+#define CGU_BASE_UART3_CLK_PD_Pos 0 /*!< CGU BASE_UART3_CLK: PD Position */
+#define CGU_BASE_UART3_CLK_PD_Msk (0x01UL << CGU_BASE_UART3_CLK_PD_Pos) /*!< CGU BASE_UART3_CLK: PD Mask */
+#define CGU_BASE_UART3_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART3_CLK: AUTOBLOCK Position */
+#define CGU_BASE_UART3_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART3_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART3_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_UART3_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART3_CLK: CLK_SEL Position */
+#define CGU_BASE_UART3_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART3_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART3_CLK: CLK_SEL Mask */
+
+// ------------------------------------ CGU_BASE_OUT_CLK ----------------------------------------
+#define CGU_BASE_OUT_CLK_PD_Pos 0 /*!< CGU BASE_OUT_CLK: PD Position */
+#define CGU_BASE_OUT_CLK_PD_Msk (0x01UL << CGU_BASE_OUT_CLK_PD_Pos) /*!< CGU BASE_OUT_CLK: PD Mask */
+#define CGU_BASE_OUT_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_OUT_CLK: AUTOBLOCK Position */
+#define CGU_BASE_OUT_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_OUT_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_OUT_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_OUT_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_OUT_CLK: CLK_SEL Position */
+#define CGU_BASE_OUT_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_OUT_CLK_CLK_SEL_Pos) /*!< CGU BASE_OUT_CLK: CLK_SEL Mask */
+
+// ------------------------------------ CGU_BASE_APLL_CLK ---------------------------------------
+#define CGU_BASE_APLL_CLK_PD_Pos 0 /*!< CGU BASE_APLL_CLK: PD Position */
+#define CGU_BASE_APLL_CLK_PD_Msk (0x01UL << CGU_BASE_APLL_CLK_PD_Pos) /*!< CGU BASE_APLL_CLK: PD Mask */
+#define CGU_BASE_APLL_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_APLL_CLK: AUTOBLOCK Position */
+#define CGU_BASE_APLL_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_APLL_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_APLL_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_APLL_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_APLL_CLK: CLK_SEL Position */
+#define CGU_BASE_APLL_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_APLL_CLK_CLK_SEL_Pos) /*!< CGU BASE_APLL_CLK: CLK_SEL Mask */
+
+// ---------------------------------- CGU_BASE_CGU_OUT0_CLK -------------------------------------
+#define CGU_BASE_CGU_OUT0_CLK_PD_Pos 0 /*!< CGU BASE_CGU_OUT0_CLK: PD Position */
+#define CGU_BASE_CGU_OUT0_CLK_PD_Msk (0x01UL << CGU_BASE_CGU_OUT0_CLK_PD_Pos) /*!< CGU BASE_CGU_OUT0_CLK: PD Mask */
+#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_CGU_OUT0_CLK: AUTOBLOCK Position */
+#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_CGU_OUT0_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_CGU_OUT0_CLK: CLK_SEL Position */
+#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Pos) /*!< CGU BASE_CGU_OUT0_CLK: CLK_SEL Mask */
+
+// ---------------------------------- CGU_BASE_CGU_OUT1_CLK -------------------------------------
+#define CGU_BASE_CGU_OUT1_CLK_PD_Pos 0 /*!< CGU BASE_CGU_OUT1_CLK: PD Position */
+#define CGU_BASE_CGU_OUT1_CLK_PD_Msk (0x01UL << CGU_BASE_CGU_OUT1_CLK_PD_Pos) /*!< CGU BASE_CGU_OUT1_CLK: PD Mask */
+#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_CGU_OUT1_CLK: AUTOBLOCK Position */
+#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_CGU_OUT1_CLK: AUTOBLOCK Mask */
+#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_CGU_OUT1_CLK: CLK_SEL Position */
+#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Pos) /*!< CGU BASE_CGU_OUT1_CLK: CLK_SEL Mask */
+
+// ------------------------------------- CGU_IDIVC_CTRL -----------------------------------------
+#define CGU_IDIVC_CTRL_PD_Pos 0 /*!< CGU IDIVC_CTRL: PD Position */
+#define CGU_IDIVC_CTRL_PD_Msk (0x01UL << CGU_IDIVC_CTRL_PD_Pos) /*!< CGU IDIVC_CTRL: PD Mask */
+#define CGU_IDIVC_CTRL_IDIV_Pos 2 /*!< CGU IDIVC_CTRL: IDIV Position */
+#define CGU_IDIVC_CTRL_IDIV_Msk (0x0fUL << CGU_IDIVC_CTRL_IDIV_Pos) /*!< CGU IDIVC_CTRL: IDIV Mask */
+#define CGU_IDIVC_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVC_CTRL: AUTOBLOCK Position */
+#define CGU_IDIVC_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVC_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVC_CTRL: AUTOBLOCK Mask */
+#define CGU_IDIVC_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVC_CTRL: CLK_SEL Position */
+#define CGU_IDIVC_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVC_CTRL_CLK_SEL_Pos) /*!< CGU IDIVC_CTRL: CLK_SEL Mask */
+
+// ------------------------------------- CGU_IDIVD_CTRL -----------------------------------------
+#define CGU_IDIVD_CTRL_PD_Pos 0 /*!< CGU IDIVD_CTRL: PD Position */
+#define CGU_IDIVD_CTRL_PD_Msk (0x01UL << CGU_IDIVD_CTRL_PD_Pos) /*!< CGU IDIVD_CTRL: PD Mask */
+#define CGU_IDIVD_CTRL_IDIV_Pos 2 /*!< CGU IDIVD_CTRL: IDIV Position */
+#define CGU_IDIVD_CTRL_IDIV_Msk (0x0fUL << CGU_IDIVD_CTRL_IDIV_Pos) /*!< CGU IDIVD_CTRL: IDIV Mask */
+#define CGU_IDIVD_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVD_CTRL: AUTOBLOCK Position */
+#define CGU_IDIVD_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVD_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVD_CTRL: AUTOBLOCK Mask */
+#define CGU_IDIVD_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVD_CTRL: CLK_SEL Position */
+#define CGU_IDIVD_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVD_CTRL_CLK_SEL_Pos) /*!< CGU IDIVD_CTRL: CLK_SEL Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- CCU1 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------- CCU1_PM --------------------------------------------
+#define CCU1_PM_PD_Pos 0 /*!< CCU1 PM: PD Position */
+#define CCU1_PM_PD_Msk (0x01UL << CCU1_PM_PD_Pos) /*!< CCU1 PM: PD Mask */
+
+// ------------------------------------- CCU1_BASE_STAT -----------------------------------------
+#define CCU1_BASE_STAT_BASE_APB3_CLK_IND_Pos 0 /*!< CCU1 BASE_STAT: BASE_APB3_CLK_IND Position */
+#define CCU1_BASE_STAT_BASE_APB3_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_APB3_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_APB3_CLK_IND Mask */
+#define CCU1_BASE_STAT_BASE_APB1_CLK_IND_Pos 1 /*!< CCU1 BASE_STAT: BASE_APB1_CLK_IND Position */
+#define CCU1_BASE_STAT_BASE_APB1_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_APB1_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_APB1_CLK_IND Mask */
+#define CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Pos 2 /*!< CCU1 BASE_STAT: BASE_SPIFI_CLK_IND Position */
+#define CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_SPIFI_CLK_IND Mask */
+#define CCU1_BASE_STAT_BASE_M3_CLK_IND_Pos 3 /*!< CCU1 BASE_STAT: BASE_M3_CLK_IND Position */
+#define CCU1_BASE_STAT_BASE_M3_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_M3_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_M3_CLK_IND Mask */
+#define CCU1_BASE_STAT_BASE_USB0_CLK_IND_Pos 7 /*!< CCU1 BASE_STAT: BASE_USB0_CLK_IND Position */
+#define CCU1_BASE_STAT_BASE_USB0_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_USB0_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_USB0_CLK_IND Mask */
+#define CCU1_BASE_STAT_BASE_USB1_CLK_IND_Pos 8 /*!< CCU1 BASE_STAT: BASE_USB1_CLK_IND Position */
+#define CCU1_BASE_STAT_BASE_USB1_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_USB1_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_USB1_CLK_IND Mask */
+
+// ---------------------------------- CCU1_CLK_APB3_BUS_CFG -------------------------------------
+#define CCU1_CLK_APB3_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_BUS_CFG: RUN Position */
+#define CCU1_CLK_APB3_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_BUS_CFG: RUN Mask */
+#define CCU1_CLK_APB3_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_BUS_CFG: AUTO Position */
+#define CCU1_CLK_APB3_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_BUS_CFG: AUTO Mask */
+#define CCU1_CLK_APB3_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_BUS_CFG: WAKEUP Position */
+#define CCU1_CLK_APB3_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_BUS_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB3_BUS_STAT -------------------------------------
+#define CCU1_CLK_APB3_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_BUS_STAT: RUN Position */
+#define CCU1_CLK_APB3_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_BUS_STAT: RUN Mask */
+#define CCU1_CLK_APB3_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_BUS_STAT: AUTO Position */
+#define CCU1_CLK_APB3_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_BUS_STAT: AUTO Mask */
+#define CCU1_CLK_APB3_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_BUS_STAT: WAKEUP Position */
+#define CCU1_CLK_APB3_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_BUS_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB3_I2C1_CFG -------------------------------------
+#define CCU1_CLK_APB3_I2C1_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_I2C1_CFG: RUN Position */
+#define CCU1_CLK_APB3_I2C1_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_I2C1_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_I2C1_CFG: RUN Mask */
+#define CCU1_CLK_APB3_I2C1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_I2C1_CFG: AUTO Position */
+#define CCU1_CLK_APB3_I2C1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_I2C1_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_I2C1_CFG: AUTO Mask */
+#define CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_I2C1_CFG: WAKEUP Position */
+#define CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_I2C1_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB3_I2C1_STAT ------------------------------------
+#define CCU1_CLK_APB3_I2C1_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_I2C1_STAT: RUN Position */
+#define CCU1_CLK_APB3_I2C1_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_I2C1_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_I2C1_STAT: RUN Mask */
+#define CCU1_CLK_APB3_I2C1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_I2C1_STAT: AUTO Position */
+#define CCU1_CLK_APB3_I2C1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_I2C1_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_I2C1_STAT: AUTO Mask */
+#define CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_I2C1_STAT: WAKEUP Position */
+#define CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_I2C1_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_APB3_DAC_CFG -------------------------------------
+#define CCU1_CLK_APB3_DAC_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_DAC_CFG: RUN Position */
+#define CCU1_CLK_APB3_DAC_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_DAC_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_DAC_CFG: RUN Mask */
+#define CCU1_CLK_APB3_DAC_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_DAC_CFG: AUTO Position */
+#define CCU1_CLK_APB3_DAC_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_DAC_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_DAC_CFG: AUTO Mask */
+#define CCU1_CLK_APB3_DAC_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_DAC_CFG: WAKEUP Position */
+#define CCU1_CLK_APB3_DAC_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_DAC_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_DAC_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB3_DAC_STAT -------------------------------------
+#define CCU1_CLK_APB3_DAC_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_DAC_STAT: RUN Position */
+#define CCU1_CLK_APB3_DAC_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_DAC_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_DAC_STAT: RUN Mask */
+#define CCU1_CLK_APB3_DAC_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_DAC_STAT: AUTO Position */
+#define CCU1_CLK_APB3_DAC_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_DAC_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_DAC_STAT: AUTO Mask */
+#define CCU1_CLK_APB3_DAC_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_DAC_STAT: WAKEUP Position */
+#define CCU1_CLK_APB3_DAC_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_DAC_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_DAC_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB3_ADC0_CFG -------------------------------------
+#define CCU1_CLK_APB3_ADC0_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC0_CFG: RUN Position */
+#define CCU1_CLK_APB3_ADC0_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC0_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_ADC0_CFG: RUN Mask */
+#define CCU1_CLK_APB3_ADC0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC0_CFG: AUTO Position */
+#define CCU1_CLK_APB3_ADC0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC0_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC0_CFG: AUTO Mask */
+#define CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC0_CFG: WAKEUP Position */
+#define CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC0_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB3_ADC0_STAT ------------------------------------
+#define CCU1_CLK_APB3_ADC0_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC0_STAT: RUN Position */
+#define CCU1_CLK_APB3_ADC0_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC0_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_ADC0_STAT: RUN Mask */
+#define CCU1_CLK_APB3_ADC0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC0_STAT: AUTO Position */
+#define CCU1_CLK_APB3_ADC0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC0_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC0_STAT: AUTO Mask */
+#define CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC0_STAT: WAKEUP Position */
+#define CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC0_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB3_ADC1_CFG -------------------------------------
+#define CCU1_CLK_APB3_ADC1_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC1_CFG: RUN Position */
+#define CCU1_CLK_APB3_ADC1_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC1_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_ADC1_CFG: RUN Mask */
+#define CCU1_CLK_APB3_ADC1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC1_CFG: AUTO Position */
+#define CCU1_CLK_APB3_ADC1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC1_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC1_CFG: AUTO Mask */
+#define CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC1_CFG: WAKEUP Position */
+#define CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC1_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB3_ADC1_STAT ------------------------------------
+#define CCU1_CLK_APB3_ADC1_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC1_STAT: RUN Position */
+#define CCU1_CLK_APB3_ADC1_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC1_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_ADC1_STAT: RUN Mask */
+#define CCU1_CLK_APB3_ADC1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC1_STAT: AUTO Position */
+#define CCU1_CLK_APB3_ADC1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC1_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC1_STAT: AUTO Mask */
+#define CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC1_STAT: WAKEUP Position */
+#define CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC1_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB3_CAN0_CFG -------------------------------------
+#define CCU1_CLK_APB3_CAN0_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_CAN0_CFG: RUN Position */
+#define CCU1_CLK_APB3_CAN0_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_CAN0_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_CAN0_CFG: RUN Mask */
+#define CCU1_CLK_APB3_CAN0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_CAN0_CFG: AUTO Position */
+#define CCU1_CLK_APB3_CAN0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_CAN0_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_CAN0_CFG: AUTO Mask */
+#define CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_CAN0_CFG: WAKEUP Position */
+#define CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_CAN0_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB3_CAN0_STAT ------------------------------------
+#define CCU1_CLK_APB3_CAN0_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_CAN0_STAT: RUN Position */
+#define CCU1_CLK_APB3_CAN0_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_CAN0_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_CAN0_STAT: RUN Mask */
+#define CCU1_CLK_APB3_CAN0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_CAN0_STAT: AUTO Position */
+#define CCU1_CLK_APB3_CAN0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_CAN0_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_CAN0_STAT: AUTO Mask */
+#define CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_CAN0_STAT: WAKEUP Position */
+#define CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_CAN0_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_APB1_BUS_CFG -------------------------------------
+#define CCU1_CLK_APB1_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_BUS_CFG: RUN Position */
+#define CCU1_CLK_APB1_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_BUS_CFG: RUN Mask */
+#define CCU1_CLK_APB1_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_BUS_CFG: AUTO Position */
+#define CCU1_CLK_APB1_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_BUS_CFG: AUTO Mask */
+#define CCU1_CLK_APB1_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_BUS_CFG: WAKEUP Position */
+#define CCU1_CLK_APB1_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_BUS_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB1_BUS_STAT -------------------------------------
+#define CCU1_CLK_APB1_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_BUS_STAT: RUN Position */
+#define CCU1_CLK_APB1_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_BUS_STAT: RUN Mask */
+#define CCU1_CLK_APB1_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_BUS_STAT: AUTO Position */
+#define CCU1_CLK_APB1_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_BUS_STAT: AUTO Mask */
+#define CCU1_CLK_APB1_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_BUS_STAT: WAKEUP Position */
+#define CCU1_CLK_APB1_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_BUS_STAT: WAKEUP Mask */
+
+// ------------------------------ CCU1_CLK_APB1_MOTOCONPWM_CFG ----------------------------------
+#define CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: RUN Position */
+#define CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: RUN Mask */
+#define CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: AUTO Position */
+#define CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: AUTO Mask */
+#define CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: WAKEUP Position */
+#define CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: WAKEUP Mask */
+
+// ------------------------------ CCU1_CLK_APB1_MOTOCONPWM_STAT ---------------------------------
+#define CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: RUN Position */
+#define CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: RUN Mask */
+#define CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: AUTO Position */
+#define CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: AUTO Mask */
+#define CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: WAKEUP Position */
+#define CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_ABP1_I2C0_CFG -------------------------------------
+#define CCU1_CLK_ABP1_I2C0_CFG_RUN_Pos 0 /*!< CCU1 CLK_ABP1_I2C0_CFG: RUN Position */
+#define CCU1_CLK_ABP1_I2C0_CFG_RUN_Msk (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_RUN_Pos) /*!< CCU1 CLK_ABP1_I2C0_CFG: RUN Mask */
+#define CCU1_CLK_ABP1_I2C0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_ABP1_I2C0_CFG: AUTO Position */
+#define CCU1_CLK_ABP1_I2C0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_AUTO_Pos) /*!< CCU1 CLK_ABP1_I2C0_CFG: AUTO Mask */
+#define CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_ABP1_I2C0_CFG: WAKEUP Position */
+#define CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_ABP1_I2C0_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB1_I2C0_STAT ------------------------------------
+#define CCU1_CLK_APB1_I2C0_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_I2C0_STAT: RUN Position */
+#define CCU1_CLK_APB1_I2C0_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_I2C0_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_I2C0_STAT: RUN Mask */
+#define CCU1_CLK_APB1_I2C0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_I2C0_STAT: AUTO Position */
+#define CCU1_CLK_APB1_I2C0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_I2C0_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_I2C0_STAT: AUTO Mask */
+#define CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_I2C0_STAT: WAKEUP Position */
+#define CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_I2C0_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_APB1_I2S_CFG -------------------------------------
+#define CCU1_CLK_APB1_I2S_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_I2S_CFG: RUN Position */
+#define CCU1_CLK_APB1_I2S_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_I2S_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_I2S_CFG: RUN Mask */
+#define CCU1_CLK_APB1_I2S_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_I2S_CFG: AUTO Position */
+#define CCU1_CLK_APB1_I2S_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_I2S_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_I2S_CFG: AUTO Mask */
+#define CCU1_CLK_APB1_I2S_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_I2S_CFG: WAKEUP Position */
+#define CCU1_CLK_APB1_I2S_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_I2S_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_I2S_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB1_I2S_STAT -------------------------------------
+#define CCU1_CLK_APB1_I2S_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_I2S_STAT: RUN Position */
+#define CCU1_CLK_APB1_I2S_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_I2S_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_I2S_STAT: RUN Mask */
+#define CCU1_CLK_APB1_I2S_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_I2S_STAT: AUTO Position */
+#define CCU1_CLK_APB1_I2S_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_I2S_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_I2S_STAT: AUTO Mask */
+#define CCU1_CLK_APB1_I2S_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_I2S_STAT: WAKEUP Position */
+#define CCU1_CLK_APB1_I2S_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_I2S_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_I2S_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB1_CAN1_CFG -------------------------------------
+#define CCU1_CLK_APB1_CAN1_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_CAN1_CFG: RUN Position */
+#define CCU1_CLK_APB1_CAN1_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_CAN1_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_CAN1_CFG: RUN Mask */
+#define CCU1_CLK_APB1_CAN1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_CAN1_CFG: AUTO Position */
+#define CCU1_CLK_APB1_CAN1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_CAN1_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_CAN1_CFG: AUTO Mask */
+#define CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_CAN1_CFG: WAKEUP Position */
+#define CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_CAN1_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_APB1_CAN1_STAT ------------------------------------
+#define CCU1_CLK_APB1_CAN1_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_CAN1_STAT: RUN Position */
+#define CCU1_CLK_APB1_CAN1_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_CAN1_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_CAN1_STAT: RUN Mask */
+#define CCU1_CLK_APB1_CAN1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_CAN1_STAT: AUTO Position */
+#define CCU1_CLK_APB1_CAN1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_CAN1_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_CAN1_STAT: AUTO Mask */
+#define CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_CAN1_STAT: WAKEUP Position */
+#define CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_CAN1_STAT: WAKEUP Mask */
+
+// ----------------------------------- CCU1_CLK_SPIFI_CFG ---------------------------------------
+#define CCU1_CLK_SPIFI_CFG_RUN_Pos 0 /*!< CCU1 CLK_SPIFI_CFG: RUN Position */
+#define CCU1_CLK_SPIFI_CFG_RUN_Msk (0x01UL << CCU1_CLK_SPIFI_CFG_RUN_Pos) /*!< CCU1 CLK_SPIFI_CFG: RUN Mask */
+#define CCU1_CLK_SPIFI_CFG_AUTO_Pos 1 /*!< CCU1 CLK_SPIFI_CFG: AUTO Position */
+#define CCU1_CLK_SPIFI_CFG_AUTO_Msk (0x01UL << CCU1_CLK_SPIFI_CFG_AUTO_Pos) /*!< CCU1 CLK_SPIFI_CFG: AUTO Mask */
+#define CCU1_CLK_SPIFI_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_SPIFI_CFG: WAKEUP Position */
+#define CCU1_CLK_SPIFI_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_SPIFI_CFG_WAKEUP_Pos) /*!< CCU1 CLK_SPIFI_CFG: WAKEUP Mask */
+
+// ----------------------------------- CCU1_CLK_SPIFI_STAT --------------------------------------
+#define CCU1_CLK_SPIFI_STAT_RUN_Pos 0 /*!< CCU1 CLK_SPIFI_STAT: RUN Position */
+#define CCU1_CLK_SPIFI_STAT_RUN_Msk (0x01UL << CCU1_CLK_SPIFI_STAT_RUN_Pos) /*!< CCU1 CLK_SPIFI_STAT: RUN Mask */
+#define CCU1_CLK_SPIFI_STAT_AUTO_Pos 1 /*!< CCU1 CLK_SPIFI_STAT: AUTO Position */
+#define CCU1_CLK_SPIFI_STAT_AUTO_Msk (0x01UL << CCU1_CLK_SPIFI_STAT_AUTO_Pos) /*!< CCU1 CLK_SPIFI_STAT: AUTO Mask */
+#define CCU1_CLK_SPIFI_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_SPIFI_STAT: WAKEUP Position */
+#define CCU1_CLK_SPIFI_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_SPIFI_STAT_WAKEUP_Pos) /*!< CCU1 CLK_SPIFI_STAT: WAKEUP Mask */
+
+// ----------------------------------- CCU1_CLK_M4_BUS_CFG --------------------------------------
+#define CCU1_CLK_M4_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_BUS_CFG: RUN Position */
+#define CCU1_CLK_M4_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_M4_BUS_CFG: RUN Mask */
+#define CCU1_CLK_M4_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_BUS_CFG: AUTO Position */
+#define CCU1_CLK_M4_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_BUS_CFG: AUTO Mask */
+#define CCU1_CLK_M4_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_BUS_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_BUS_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_BUS_STAT --------------------------------------
+#define CCU1_CLK_M4_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_BUS_STAT: RUN Position */
+#define CCU1_CLK_M4_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_M4_BUS_STAT: RUN Mask */
+#define CCU1_CLK_M4_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_BUS_STAT: AUTO Position */
+#define CCU1_CLK_M4_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_BUS_STAT: AUTO Mask */
+#define CCU1_CLK_M4_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_BUS_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_BUS_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_SPIFI_CFG -------------------------------------
+#define CCU1_CLK_M4_SPIFI_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_SPIFI_CFG: RUN Position */
+#define CCU1_CLK_M4_SPIFI_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_SPIFI_CFG_RUN_Pos) /*!< CCU1 CLK_M4_SPIFI_CFG: RUN Mask */
+#define CCU1_CLK_M4_SPIFI_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_SPIFI_CFG: AUTO Position */
+#define CCU1_CLK_M4_SPIFI_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_SPIFI_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_SPIFI_CFG: AUTO Mask */
+#define CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SPIFI_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_SPIFI_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M4_SPIFI_STAT -------------------------------------
+#define CCU1_CLK_M4_SPIFI_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_SPIFI_STAT: RUN Position */
+#define CCU1_CLK_M4_SPIFI_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_SPIFI_STAT_RUN_Pos) /*!< CCU1 CLK_M4_SPIFI_STAT: RUN Mask */
+#define CCU1_CLK_M4_SPIFI_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_SPIFI_STAT: AUTO Position */
+#define CCU1_CLK_M4_SPIFI_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_SPIFI_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_SPIFI_STAT: AUTO Mask */
+#define CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SPIFI_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_SPIFI_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_GPIO_CFG --------------------------------------
+#define CCU1_CLK_M4_GPIO_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_GPIO_CFG: RUN Position */
+#define CCU1_CLK_M4_GPIO_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_GPIO_CFG_RUN_Pos) /*!< CCU1 CLK_M4_GPIO_CFG: RUN Mask */
+#define CCU1_CLK_M4_GPIO_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_GPIO_CFG: AUTO Position */
+#define CCU1_CLK_M4_GPIO_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_GPIO_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_GPIO_CFG: AUTO Mask */
+#define CCU1_CLK_M4_GPIO_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_GPIO_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_GPIO_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_GPIO_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_GPIO_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_GPIO_STAT -------------------------------------
+#define CCU1_CLK_M4_GPIO_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_GPIO_STAT: RUN Position */
+#define CCU1_CLK_M4_GPIO_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_GPIO_STAT_RUN_Pos) /*!< CCU1 CLK_M4_GPIO_STAT: RUN Mask */
+#define CCU1_CLK_M4_GPIO_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_GPIO_STAT: AUTO Position */
+#define CCU1_CLK_M4_GPIO_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_GPIO_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_GPIO_STAT: AUTO Mask */
+#define CCU1_CLK_M4_GPIO_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_GPIO_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_GPIO_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_GPIO_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_GPIO_STAT: WAKEUP Mask */
+
+// ----------------------------------- CCU1_CLK_M4_LCD_CFG --------------------------------------
+#define CCU1_CLK_M4_LCD_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_LCD_CFG: RUN Position */
+#define CCU1_CLK_M4_LCD_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_LCD_CFG_RUN_Pos) /*!< CCU1 CLK_M4_LCD_CFG: RUN Mask */
+#define CCU1_CLK_M4_LCD_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_LCD_CFG: AUTO Position */
+#define CCU1_CLK_M4_LCD_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_LCD_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_LCD_CFG: AUTO Mask */
+#define CCU1_CLK_M4_LCD_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_LCD_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_LCD_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_LCD_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_LCD_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_LCD_STAT --------------------------------------
+#define CCU1_CLK_M4_LCD_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_LCD_STAT: RUN Position */
+#define CCU1_CLK_M4_LCD_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_LCD_STAT_RUN_Pos) /*!< CCU1 CLK_M4_LCD_STAT: RUN Mask */
+#define CCU1_CLK_M4_LCD_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_LCD_STAT: AUTO Position */
+#define CCU1_CLK_M4_LCD_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_LCD_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_LCD_STAT: AUTO Mask */
+#define CCU1_CLK_M4_LCD_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_LCD_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_LCD_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_LCD_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_LCD_STAT: WAKEUP Mask */
+
+// -------------------------------- CCU1_CLK_M4_ETHERNET_CFG ------------------------------------
+#define CCU1_CLK_M4_ETHERNET_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_ETHERNET_CFG: RUN Position */
+#define CCU1_CLK_M4_ETHERNET_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_RUN_Pos) /*!< CCU1 CLK_M4_ETHERNET_CFG: RUN Mask */
+#define CCU1_CLK_M4_ETHERNET_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_ETHERNET_CFG: AUTO Position */
+#define CCU1_CLK_M4_ETHERNET_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_ETHERNET_CFG: AUTO Mask */
+#define CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_ETHERNET_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_ETHERNET_CFG: WAKEUP Mask */
+
+// -------------------------------- CCU1_CLK_M4_ETHERNET_STAT -----------------------------------
+#define CCU1_CLK_M4_ETHERNET_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_ETHERNET_STAT: RUN Position */
+#define CCU1_CLK_M4_ETHERNET_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_RUN_Pos) /*!< CCU1 CLK_M4_ETHERNET_STAT: RUN Mask */
+#define CCU1_CLK_M4_ETHERNET_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_ETHERNET_STAT: AUTO Position */
+#define CCU1_CLK_M4_ETHERNET_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_ETHERNET_STAT: AUTO Mask */
+#define CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_ETHERNET_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_ETHERNET_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_USB0_CFG --------------------------------------
+#define CCU1_CLK_M4_USB0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_USB0_CFG: RUN Position */
+#define CCU1_CLK_M4_USB0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_USB0_CFG_RUN_Pos) /*!< CCU1 CLK_M4_USB0_CFG: RUN Mask */
+#define CCU1_CLK_M4_USB0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_USB0_CFG: AUTO Position */
+#define CCU1_CLK_M4_USB0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_USB0_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_USB0_CFG: AUTO Mask */
+#define CCU1_CLK_M4_USB0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USB0_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_USB0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USB0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_USB0_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_USB0_STAT -------------------------------------
+#define CCU1_CLK_M4_USB0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_USB0_STAT: RUN Position */
+#define CCU1_CLK_M4_USB0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_USB0_STAT_RUN_Pos) /*!< CCU1 CLK_M4_USB0_STAT: RUN Mask */
+#define CCU1_CLK_M4_USB0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_USB0_STAT: AUTO Position */
+#define CCU1_CLK_M4_USB0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_USB0_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_USB0_STAT: AUTO Mask */
+#define CCU1_CLK_M4_USB0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USB0_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_USB0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USB0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_USB0_STAT: WAKEUP Mask */
+
+// ----------------------------------- CCU1_CLK_M4_EMC_CFG --------------------------------------
+#define CCU1_CLK_M4_EMC_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_EMC_CFG: RUN Position */
+#define CCU1_CLK_M4_EMC_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_EMC_CFG_RUN_Pos) /*!< CCU1 CLK_M4_EMC_CFG: RUN Mask */
+#define CCU1_CLK_M4_EMC_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_EMC_CFG: AUTO Position */
+#define CCU1_CLK_M4_EMC_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_EMC_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_EMC_CFG: AUTO Mask */
+#define CCU1_CLK_M4_EMC_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_EMC_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_EMC_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_EMC_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_EMC_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_EMC_STAT --------------------------------------
+#define CCU1_CLK_M4_EMC_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_EMC_STAT: RUN Position */
+#define CCU1_CLK_M4_EMC_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_EMC_STAT_RUN_Pos) /*!< CCU1 CLK_M4_EMC_STAT: RUN Mask */
+#define CCU1_CLK_M4_EMC_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_EMC_STAT: AUTO Position */
+#define CCU1_CLK_M4_EMC_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_EMC_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_EMC_STAT: AUTO Mask */
+#define CCU1_CLK_M4_EMC_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_EMC_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_EMC_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_EMC_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_EMC_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_SDIO_CFG --------------------------------------
+#define CCU1_CLK_M4_SDIO_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_SDIO_CFG: RUN Position */
+#define CCU1_CLK_M4_SDIO_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_SDIO_CFG_RUN_Pos) /*!< CCU1 CLK_M4_SDIO_CFG: RUN Mask */
+#define CCU1_CLK_M4_SDIO_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_SDIO_CFG: AUTO Position */
+#define CCU1_CLK_M4_SDIO_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_SDIO_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_SDIO_CFG: AUTO Mask */
+#define CCU1_CLK_M4_SDIO_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SDIO_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_SDIO_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SDIO_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_SDIO_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_SDIO_STAT -------------------------------------
+#define CCU1_CLK_M4_SDIO_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_SDIO_STAT: RUN Position */
+#define CCU1_CLK_M4_SDIO_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_SDIO_STAT_RUN_Pos) /*!< CCU1 CLK_M4_SDIO_STAT: RUN Mask */
+#define CCU1_CLK_M4_SDIO_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_SDIO_STAT: AUTO Position */
+#define CCU1_CLK_M4_SDIO_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_SDIO_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_SDIO_STAT: AUTO Mask */
+#define CCU1_CLK_M4_SDIO_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SDIO_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_SDIO_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SDIO_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_SDIO_STAT: WAKEUP Mask */
+
+// ----------------------------------- CCU1_CLK_M4_DMA_CFG --------------------------------------
+#define CCU1_CLK_M4_DMA_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_DMA_CFG: RUN Position */
+#define CCU1_CLK_M4_DMA_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_DMA_CFG_RUN_Pos) /*!< CCU1 CLK_M4_DMA_CFG: RUN Mask */
+#define CCU1_CLK_M4_DMA_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_DMA_CFG: AUTO Position */
+#define CCU1_CLK_M4_DMA_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_DMA_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_DMA_CFG: AUTO Mask */
+#define CCU1_CLK_M4_DMA_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_DMA_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_DMA_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_DMA_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_DMA_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_DMA_STAT --------------------------------------
+#define CCU1_CLK_M4_DMA_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_DMA_STAT: RUN Position */
+#define CCU1_CLK_M4_DMA_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_DMA_STAT_RUN_Pos) /*!< CCU1 CLK_M4_DMA_STAT: RUN Mask */
+#define CCU1_CLK_M4_DMA_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_DMA_STAT: AUTO Position */
+#define CCU1_CLK_M4_DMA_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_DMA_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_DMA_STAT: AUTO Mask */
+#define CCU1_CLK_M4_DMA_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_DMA_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_DMA_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_DMA_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_DMA_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M4_M4CORE_CFG -------------------------------------
+#define CCU1_CLK_M4_M4CORE_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_M4CORE_CFG: RUN Position */
+#define CCU1_CLK_M4_M4CORE_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_M4CORE_CFG_RUN_Pos) /*!< CCU1 CLK_M4_M4CORE_CFG: RUN Mask */
+#define CCU1_CLK_M4_M4CORE_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_M4CORE_CFG: AUTO Position */
+#define CCU1_CLK_M4_M4CORE_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_M4CORE_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_M4CORE_CFG: AUTO Mask */
+#define CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_M4CORE_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_M4CORE_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M4_M3CORE_STAT ------------------------------------
+#define CCU1_CLK_M4_M3CORE_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_M3CORE_STAT: RUN Position */
+#define CCU1_CLK_M4_M3CORE_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_M3CORE_STAT_RUN_Pos) /*!< CCU1 CLK_M4_M3CORE_STAT: RUN Mask */
+#define CCU1_CLK_M4_M3CORE_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_M3CORE_STAT: AUTO Position */
+#define CCU1_CLK_M4_M3CORE_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_M3CORE_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_M3CORE_STAT: AUTO Mask */
+#define CCU1_CLK_M4_M3CORE_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_M3CORE_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_M3CORE_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_M3CORE_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_M3CORE_STAT: WAKEUP Mask */
+
+// ----------------------------------- CCU1_CLK_M4_SCT_CFG --------------------------------------
+#define CCU1_CLK_M4_SCT_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_SCT_CFG: RUN Position */
+#define CCU1_CLK_M4_SCT_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_SCT_CFG_RUN_Pos) /*!< CCU1 CLK_M4_SCT_CFG: RUN Mask */
+#define CCU1_CLK_M4_SCT_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_SCT_CFG: AUTO Position */
+#define CCU1_CLK_M4_SCT_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_SCT_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_SCT_CFG: AUTO Mask */
+#define CCU1_CLK_M4_SCT_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SCT_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_SCT_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SCT_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_SCT_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_SCT_STAT --------------------------------------
+#define CCU1_CLK_M4_SCT_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_SCT_STAT: RUN Position */
+#define CCU1_CLK_M4_SCT_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_SCT_STAT_RUN_Pos) /*!< CCU1 CLK_M4_SCT_STAT: RUN Mask */
+#define CCU1_CLK_M4_SCT_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_SCT_STAT: AUTO Position */
+#define CCU1_CLK_M4_SCT_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_SCT_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_SCT_STAT: AUTO Mask */
+#define CCU1_CLK_M4_SCT_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SCT_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_SCT_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SCT_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_SCT_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_USB1_CFG --------------------------------------
+#define CCU1_CLK_M4_USB1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_USB1_CFG: RUN Position */
+#define CCU1_CLK_M4_USB1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_USB1_CFG_RUN_Pos) /*!< CCU1 CLK_M4_USB1_CFG: RUN Mask */
+#define CCU1_CLK_M4_USB1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_USB1_CFG: AUTO Position */
+#define CCU1_CLK_M4_USB1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_USB1_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_USB1_CFG: AUTO Mask */
+#define CCU1_CLK_M4_USB1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USB1_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_USB1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USB1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_USB1_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_USB1_STAT -------------------------------------
+#define CCU1_CLK_M4_USB1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_USB1_STAT: RUN Position */
+#define CCU1_CLK_M4_USB1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_USB1_STAT_RUN_Pos) /*!< CCU1 CLK_M4_USB1_STAT: RUN Mask */
+#define CCU1_CLK_M4_USB1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_USB1_STAT: AUTO Position */
+#define CCU1_CLK_M4_USB1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_USB1_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_USB1_STAT: AUTO Mask */
+#define CCU1_CLK_M4_USB1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USB1_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_USB1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USB1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_USB1_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M4_EMCDIV_CFG -------------------------------------
+#define CCU1_CLK_M4_EMCDIV_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_EMCDIV_CFG: RUN Position */
+#define CCU1_CLK_M4_EMCDIV_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_RUN_Pos) /*!< CCU1 CLK_M4_EMCDIV_CFG: RUN Mask */
+#define CCU1_CLK_M4_EMCDIV_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_EMCDIV_CFG: AUTO Position */
+#define CCU1_CLK_M4_EMCDIV_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_EMCDIV_CFG: AUTO Mask */
+#define CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_EMCDIV_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_EMCDIV_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M4_EMCDIV_STAT ------------------------------------
+#define CCU1_CLK_M4_EMCDIV_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_EMCDIV_STAT: RUN Position */
+#define CCU1_CLK_M4_EMCDIV_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_RUN_Pos) /*!< CCU1 CLK_M4_EMCDIV_STAT: RUN Mask */
+#define CCU1_CLK_M4_EMCDIV_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_EMCDIV_STAT: AUTO Position */
+#define CCU1_CLK_M4_EMCDIV_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_EMCDIV_STAT: AUTO Mask */
+#define CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_EMCDIV_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_EMCDIV_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_M0APP_CFG -------------------------------------
+#define CCU1_CLK_M4_M0APP_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_M0APP_CFG: RUN Position */
+#define CCU1_CLK_M4_M0APP_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_M0APP_CFG_RUN_Pos) /*!< CCU1 CLK_M4_M0APP_CFG: RUN Mask */
+#define CCU1_CLK_M4_M0APP_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_M0APP_CFG: AUTO Position */
+#define CCU1_CLK_M4_M0APP_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_M0APP_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_M0APP_CFG: AUTO Mask */
+#define CCU1_CLK_M4_M0APP_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_M0APP_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_M0APP_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_M0APP_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_M0APP_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M4_M0APP_STAT -------------------------------------
+#define CCU1_CLK_M4_M0APP_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_M0APP_STAT: RUN Position */
+#define CCU1_CLK_M4_M0APP_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_M0APP_STAT_RUN_Pos) /*!< CCU1 CLK_M4_M0APP_STAT: RUN Mask */
+#define CCU1_CLK_M4_M0APP_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_M0APP_STAT: AUTO Position */
+#define CCU1_CLK_M4_M0APP_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_M0APP_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_M0APP_STAT: AUTO Mask */
+#define CCU1_CLK_M4_M0APP_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_M0APP_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_M0APP_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_M0APP_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_M0APP_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_WWDT_CFG --------------------------------------
+#define CCU1_CLK_M4_WWDT_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_WWDT_CFG: RUN Position */
+#define CCU1_CLK_M4_WWDT_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_WWDT_CFG_RUN_Pos) /*!< CCU1 CLK_M4_WWDT_CFG: RUN Mask */
+#define CCU1_CLK_M4_WWDT_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_WWDT_CFG: AUTO Position */
+#define CCU1_CLK_M4_WWDT_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_WWDT_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_WWDT_CFG: AUTO Mask */
+#define CCU1_CLK_M4_WWDT_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_WWDT_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_WWDT_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_WWDT_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_WWDT_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_WWDT_STAT -------------------------------------
+#define CCU1_CLK_M4_WWDT_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_WWDT_STAT: RUN Position */
+#define CCU1_CLK_M4_WWDT_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_WWDT_STAT_RUN_Pos) /*!< CCU1 CLK_M4_WWDT_STAT: RUN Mask */
+#define CCU1_CLK_M4_WWDT_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_WWDT_STAT: AUTO Position */
+#define CCU1_CLK_M4_WWDT_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_WWDT_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_WWDT_STAT: AUTO Mask */
+#define CCU1_CLK_M4_WWDT_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_WWDT_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_WWDT_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_WWDT_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_WWDT_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M4_USART0_CFG -------------------------------------
+#define CCU1_CLK_M4_USART0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_USART0_CFG: RUN Position */
+#define CCU1_CLK_M4_USART0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_USART0_CFG_RUN_Pos) /*!< CCU1 CLK_M4_USART0_CFG: RUN Mask */
+#define CCU1_CLK_M4_USART0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_USART0_CFG: AUTO Position */
+#define CCU1_CLK_M4_USART0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_USART0_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_USART0_CFG: AUTO Mask */
+#define CCU1_CLK_M4_USART0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USART0_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_USART0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USART0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_USART0_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M4_USART0_STAT ------------------------------------
+#define CCU1_CLK_M4_USART0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_USART0_STAT: RUN Position */
+#define CCU1_CLK_M4_USART0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_USART0_STAT_RUN_Pos) /*!< CCU1 CLK_M4_USART0_STAT: RUN Mask */
+#define CCU1_CLK_M4_USART0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_USART0_STAT: AUTO Position */
+#define CCU1_CLK_M4_USART0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_USART0_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_USART0_STAT: AUTO Mask */
+#define CCU1_CLK_M4_USART0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USART0_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_USART0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USART0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_USART0_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_UART1_CFG -------------------------------------
+#define CCU1_CLK_M4_UART1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_UART1_CFG: RUN Position */
+#define CCU1_CLK_M4_UART1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_UART1_CFG_RUN_Pos) /*!< CCU1 CLK_M4_UART1_CFG: RUN Mask */
+#define CCU1_CLK_M4_UART1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_UART1_CFG: AUTO Position */
+#define CCU1_CLK_M4_UART1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_UART1_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_UART1_CFG: AUTO Mask */
+#define CCU1_CLK_M4_UART1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_UART1_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_UART1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_UART1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_UART1_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M4_UART1_STAT -------------------------------------
+#define CCU1_CLK_M4_UART1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_UART1_STAT: RUN Position */
+#define CCU1_CLK_M4_UART1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_UART1_STAT_RUN_Pos) /*!< CCU1 CLK_M4_UART1_STAT: RUN Mask */
+#define CCU1_CLK_M4_UART1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_UART1_STAT: AUTO Position */
+#define CCU1_CLK_M4_UART1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_UART1_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_UART1_STAT: AUTO Mask */
+#define CCU1_CLK_M4_UART1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_UART1_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_UART1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_UART1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_UART1_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_SSP0_CFG --------------------------------------
+#define CCU1_CLK_M4_SSP0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_SSP0_CFG: RUN Position */
+#define CCU1_CLK_M4_SSP0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_SSP0_CFG_RUN_Pos) /*!< CCU1 CLK_M4_SSP0_CFG: RUN Mask */
+#define CCU1_CLK_M4_SSP0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_SSP0_CFG: AUTO Position */
+#define CCU1_CLK_M4_SSP0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_SSP0_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_SSP0_CFG: AUTO Mask */
+#define CCU1_CLK_M4_SSP0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SSP0_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_SSP0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SSP0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_SSP0_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_SSP0_STAT -------------------------------------
+#define CCU1_CLK_M4_SSP0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_SSP0_STAT: RUN Position */
+#define CCU1_CLK_M4_SSP0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_SSP0_STAT_RUN_Pos) /*!< CCU1 CLK_M4_SSP0_STAT: RUN Mask */
+#define CCU1_CLK_M4_SSP0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_SSP0_STAT: AUTO Position */
+#define CCU1_CLK_M4_SSP0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_SSP0_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_SSP0_STAT: AUTO Mask */
+#define CCU1_CLK_M4_SSP0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SSP0_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_SSP0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SSP0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_SSP0_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M4_TIMER0_CFG -------------------------------------
+#define CCU1_CLK_M4_TIMER0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER0_CFG: RUN Position */
+#define CCU1_CLK_M4_TIMER0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER0_CFG_RUN_Pos) /*!< CCU1 CLK_M4_TIMER0_CFG: RUN Mask */
+#define CCU1_CLK_M4_TIMER0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER0_CFG: AUTO Position */
+#define CCU1_CLK_M4_TIMER0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER0_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER0_CFG: AUTO Mask */
+#define CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER0_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER0_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M4_TIMER0_STAT ------------------------------------
+#define CCU1_CLK_M4_TIMER0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER0_STAT: RUN Position */
+#define CCU1_CLK_M4_TIMER0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER0_STAT_RUN_Pos) /*!< CCU1 CLK_M4_TIMER0_STAT: RUN Mask */
+#define CCU1_CLK_M4_TIMER0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER0_STAT: AUTO Position */
+#define CCU1_CLK_M4_TIMER0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER0_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER0_STAT: AUTO Mask */
+#define CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER0_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER0_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M4_TIMER1_CFG -------------------------------------
+#define CCU1_CLK_M4_TIMER1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER1_CFG: RUN Position */
+#define CCU1_CLK_M4_TIMER1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER1_CFG_RUN_Pos) /*!< CCU1 CLK_M4_TIMER1_CFG: RUN Mask */
+#define CCU1_CLK_M4_TIMER1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER1_CFG: AUTO Position */
+#define CCU1_CLK_M4_TIMER1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER1_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER1_CFG: AUTO Mask */
+#define CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER1_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER1_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M4_TIMER1_STAT ------------------------------------
+#define CCU1_CLK_M4_TIMER1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER1_STAT: RUN Position */
+#define CCU1_CLK_M4_TIMER1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER1_STAT_RUN_Pos) /*!< CCU1 CLK_M4_TIMER1_STAT: RUN Mask */
+#define CCU1_CLK_M4_TIMER1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER1_STAT: AUTO Position */
+#define CCU1_CLK_M4_TIMER1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER1_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER1_STAT: AUTO Mask */
+#define CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER1_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER1_STAT: WAKEUP Mask */
+
+// ----------------------------------- CCU1_CLK_M4_SCU_CFG --------------------------------------
+#define CCU1_CLK_M4_SCU_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_SCU_CFG: RUN Position */
+#define CCU1_CLK_M4_SCU_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_SCU_CFG_RUN_Pos) /*!< CCU1 CLK_M4_SCU_CFG: RUN Mask */
+#define CCU1_CLK_M4_SCU_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_SCU_CFG: AUTO Position */
+#define CCU1_CLK_M4_SCU_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_SCU_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_SCU_CFG: AUTO Mask */
+#define CCU1_CLK_M4_SCU_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SCU_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_SCU_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SCU_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_SCU_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_SCU_STAT --------------------------------------
+#define CCU1_CLK_M4_SCU_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_SCU_STAT: RUN Position */
+#define CCU1_CLK_M4_SCU_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_SCU_STAT_RUN_Pos) /*!< CCU1 CLK_M4_SCU_STAT: RUN Mask */
+#define CCU1_CLK_M4_SCU_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_SCU_STAT: AUTO Position */
+#define CCU1_CLK_M4_SCU_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_SCU_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_SCU_STAT: AUTO Mask */
+#define CCU1_CLK_M4_SCU_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SCU_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_SCU_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SCU_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_SCU_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_CREG_CFG --------------------------------------
+#define CCU1_CLK_M4_CREG_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_CREG_CFG: RUN Position */
+#define CCU1_CLK_M4_CREG_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_CREG_CFG_RUN_Pos) /*!< CCU1 CLK_M4_CREG_CFG: RUN Mask */
+#define CCU1_CLK_M4_CREG_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_CREG_CFG: AUTO Position */
+#define CCU1_CLK_M4_CREG_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_CREG_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_CREG_CFG: AUTO Mask */
+#define CCU1_CLK_M4_CREG_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_CREG_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_CREG_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_CREG_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_CREG_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_CREG_STAT -------------------------------------
+#define CCU1_CLK_M4_CREG_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_CREG_STAT: RUN Position */
+#define CCU1_CLK_M4_CREG_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_CREG_STAT_RUN_Pos) /*!< CCU1 CLK_M4_CREG_STAT: RUN Mask */
+#define CCU1_CLK_M4_CREG_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_CREG_STAT: AUTO Position */
+#define CCU1_CLK_M4_CREG_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_CREG_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_CREG_STAT: AUTO Mask */
+#define CCU1_CLK_M4_CREG_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_CREG_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_CREG_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_CREG_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_CREG_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M4_RITIMER_CFG ------------------------------------
+#define CCU1_CLK_M4_RITIMER_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_RITIMER_CFG: RUN Position */
+#define CCU1_CLK_M4_RITIMER_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_RITIMER_CFG_RUN_Pos) /*!< CCU1 CLK_M4_RITIMER_CFG: RUN Mask */
+#define CCU1_CLK_M4_RITIMER_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_RITIMER_CFG: AUTO Position */
+#define CCU1_CLK_M4_RITIMER_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_RITIMER_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_RITIMER_CFG: AUTO Mask */
+#define CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_RITIMER_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_RITIMER_CFG: WAKEUP Mask */
+
+// -------------------------------- CCU1_CLK_M4_RITIMER_STAT ------------------------------------
+#define CCU1_CLK_M4_RITIMER_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_RITIMER_STAT: RUN Position */
+#define CCU1_CLK_M4_RITIMER_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_RITIMER_STAT_RUN_Pos) /*!< CCU1 CLK_M4_RITIMER_STAT: RUN Mask */
+#define CCU1_CLK_M4_RITIMER_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_RITIMER_STAT: AUTO Position */
+#define CCU1_CLK_M4_RITIMER_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_RITIMER_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_RITIMER_STAT: AUTO Mask */
+#define CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_RITIMER_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_RITIMER_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M4_USART2_CFG -------------------------------------
+#define CCU1_CLK_M4_USART2_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_USART2_CFG: RUN Position */
+#define CCU1_CLK_M4_USART2_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_USART2_CFG_RUN_Pos) /*!< CCU1 CLK_M4_USART2_CFG: RUN Mask */
+#define CCU1_CLK_M4_USART2_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_USART2_CFG: AUTO Position */
+#define CCU1_CLK_M4_USART2_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_USART2_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_USART2_CFG: AUTO Mask */
+#define CCU1_CLK_M4_USART2_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USART2_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_USART2_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USART2_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_USART2_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M4_USART2_STAT ------------------------------------
+#define CCU1_CLK_M4_USART2_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_USART2_STAT: RUN Position */
+#define CCU1_CLK_M4_USART2_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_USART2_STAT_RUN_Pos) /*!< CCU1 CLK_M4_USART2_STAT: RUN Mask */
+#define CCU1_CLK_M4_USART2_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_USART2_STAT: AUTO Position */
+#define CCU1_CLK_M4_USART2_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_USART2_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_USART2_STAT: AUTO Mask */
+#define CCU1_CLK_M4_USART2_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USART2_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_USART2_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USART2_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_USART2_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M4_USART3_CFG -------------------------------------
+#define CCU1_CLK_M4_USART3_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_USART3_CFG: RUN Position */
+#define CCU1_CLK_M4_USART3_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_USART3_CFG_RUN_Pos) /*!< CCU1 CLK_M4_USART3_CFG: RUN Mask */
+#define CCU1_CLK_M4_USART3_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_USART3_CFG: AUTO Position */
+#define CCU1_CLK_M4_USART3_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_USART3_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_USART3_CFG: AUTO Mask */
+#define CCU1_CLK_M4_USART3_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USART3_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_USART3_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USART3_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_USART3_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M4_USART3_STAT ------------------------------------
+#define CCU1_CLK_M4_USART3_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_USART3_STAT: RUN Position */
+#define CCU1_CLK_M4_USART3_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_USART3_STAT_RUN_Pos) /*!< CCU1 CLK_M4_USART3_STAT: RUN Mask */
+#define CCU1_CLK_M4_USART3_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_USART3_STAT: AUTO Position */
+#define CCU1_CLK_M4_USART3_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_USART3_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_USART3_STAT: AUTO Mask */
+#define CCU1_CLK_M4_USART3_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USART3_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_USART3_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USART3_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_USART3_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M4_TIMER2_CFG -------------------------------------
+#define CCU1_CLK_M4_TIMER2_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER2_CFG: RUN Position */
+#define CCU1_CLK_M4_TIMER2_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER2_CFG_RUN_Pos) /*!< CCU1 CLK_M4_TIMER2_CFG: RUN Mask */
+#define CCU1_CLK_M4_TIMER2_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER2_CFG: AUTO Position */
+#define CCU1_CLK_M4_TIMER2_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER2_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER2_CFG: AUTO Mask */
+#define CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER2_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER2_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M4_TIMER2_STAT ------------------------------------
+#define CCU1_CLK_M4_TIMER2_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER2_STAT: RUN Position */
+#define CCU1_CLK_M4_TIMER2_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER2_STAT_RUN_Pos) /*!< CCU1 CLK_M4_TIMER2_STAT: RUN Mask */
+#define CCU1_CLK_M4_TIMER2_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER2_STAT: AUTO Position */
+#define CCU1_CLK_M4_TIMER2_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER2_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER2_STAT: AUTO Mask */
+#define CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER2_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER2_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M4_TIMER3_CFG -------------------------------------
+#define CCU1_CLK_M4_TIMER3_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER3_CFG: RUN Position */
+#define CCU1_CLK_M4_TIMER3_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER3_CFG_RUN_Pos) /*!< CCU1 CLK_M4_TIMER3_CFG: RUN Mask */
+#define CCU1_CLK_M4_TIMER3_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER3_CFG: AUTO Position */
+#define CCU1_CLK_M4_TIMER3_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER3_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER3_CFG: AUTO Mask */
+#define CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER3_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER3_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_M4_TIMER3_STAT ------------------------------------
+#define CCU1_CLK_M4_TIMER3_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER3_STAT: RUN Position */
+#define CCU1_CLK_M4_TIMER3_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER3_STAT_RUN_Pos) /*!< CCU1 CLK_M4_TIMER3_STAT: RUN Mask */
+#define CCU1_CLK_M4_TIMER3_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER3_STAT: AUTO Position */
+#define CCU1_CLK_M4_TIMER3_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER3_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER3_STAT: AUTO Mask */
+#define CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER3_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER3_STAT: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_SSP1_CFG --------------------------------------
+#define CCU1_CLK_M4_SSP1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_SSP1_CFG: RUN Position */
+#define CCU1_CLK_M4_SSP1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_SSP1_CFG_RUN_Pos) /*!< CCU1 CLK_M4_SSP1_CFG: RUN Mask */
+#define CCU1_CLK_M4_SSP1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_SSP1_CFG: AUTO Position */
+#define CCU1_CLK_M4_SSP1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_SSP1_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_SSP1_CFG: AUTO Mask */
+#define CCU1_CLK_M4_SSP1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SSP1_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_SSP1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SSP1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_SSP1_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_SSP1_STAT -------------------------------------
+#define CCU1_CLK_M4_SSP1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_SSP1_STAT: RUN Position */
+#define CCU1_CLK_M4_SSP1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_SSP1_STAT_RUN_Pos) /*!< CCU1 CLK_M4_SSP1_STAT: RUN Mask */
+#define CCU1_CLK_M4_SSP1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_SSP1_STAT: AUTO Position */
+#define CCU1_CLK_M4_SSP1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_SSP1_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_SSP1_STAT: AUTO Mask */
+#define CCU1_CLK_M4_SSP1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SSP1_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_SSP1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SSP1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_SSP1_STAT: WAKEUP Mask */
+
+// ----------------------------------- CCU1_CLK_M4_QEI_CFG --------------------------------------
+#define CCU1_CLK_M4_QEI_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_QEI_CFG: RUN Position */
+#define CCU1_CLK_M4_QEI_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_QEI_CFG_RUN_Pos) /*!< CCU1 CLK_M4_QEI_CFG: RUN Mask */
+#define CCU1_CLK_M4_QEI_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_QEI_CFG: AUTO Position */
+#define CCU1_CLK_M4_QEI_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_QEI_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_QEI_CFG: AUTO Mask */
+#define CCU1_CLK_M4_QEI_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_QEI_CFG: WAKEUP Position */
+#define CCU1_CLK_M4_QEI_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_QEI_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_QEI_CFG: WAKEUP Mask */
+
+// ---------------------------------- CCU1_CLK_M4_QEI_STAT --------------------------------------
+#define CCU1_CLK_M4_QEI_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_QEI_STAT: RUN Position */
+#define CCU1_CLK_M4_QEI_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_QEI_STAT_RUN_Pos) /*!< CCU1 CLK_M4_QEI_STAT: RUN Mask */
+#define CCU1_CLK_M4_QEI_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_QEI_STAT: AUTO Position */
+#define CCU1_CLK_M4_QEI_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_QEI_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_QEI_STAT: AUTO Mask */
+#define CCU1_CLK_M4_QEI_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_QEI_STAT: WAKEUP Position */
+#define CCU1_CLK_M4_QEI_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_QEI_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_QEI_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU1_CLK_PERIPH_BUS_CFG ------------------------------------
+#define CCU1_CLK_PERIPH_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_BUS_CFG: RUN Position */
+#define CCU1_CLK_PERIPH_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_PERIPH_BUS_CFG: RUN Mask */
+#define CCU1_CLK_PERIPH_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_BUS_CFG: AUTO Position */
+#define CCU1_CLK_PERIPH_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_PERIPH_BUS_CFG: AUTO Mask */
+#define CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_BUS_CFG: WAKEUP Position */
+#define CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_BUS_CFG: WAKEUP Mask */
+
+// -------------------------------- CCU1_CLK_PERIPH_BUS_STAT ------------------------------------
+#define CCU1_CLK_PERIPH_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_BUS_STAT: RUN Position */
+#define CCU1_CLK_PERIPH_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_PERIPH_BUS_STAT: RUN Mask */
+#define CCU1_CLK_PERIPH_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_BUS_STAT: AUTO Position */
+#define CCU1_CLK_PERIPH_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_PERIPH_BUS_STAT: AUTO Mask */
+#define CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_BUS_STAT: WAKEUP Position */
+#define CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_BUS_STAT: WAKEUP Mask */
+
+// -------------------------------- CCU1_CLK_PERIPH_CORE_CFG ------------------------------------
+#define CCU1_CLK_PERIPH_CORE_CFG_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_CORE_CFG: RUN Position */
+#define CCU1_CLK_PERIPH_CORE_CFG_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_RUN_Pos) /*!< CCU1 CLK_PERIPH_CORE_CFG: RUN Mask */
+#define CCU1_CLK_PERIPH_CORE_CFG_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_CORE_CFG: AUTO Position */
+#define CCU1_CLK_PERIPH_CORE_CFG_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_AUTO_Pos) /*!< CCU1 CLK_PERIPH_CORE_CFG: AUTO Mask */
+#define CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_CORE_CFG: WAKEUP Position */
+#define CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_CORE_CFG: WAKEUP Mask */
+
+// -------------------------------- CCU1_CLK_PERIPH_CORE_STAT -----------------------------------
+#define CCU1_CLK_PERIPH_CORE_STAT_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_CORE_STAT: RUN Position */
+#define CCU1_CLK_PERIPH_CORE_STAT_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_RUN_Pos) /*!< CCU1 CLK_PERIPH_CORE_STAT: RUN Mask */
+#define CCU1_CLK_PERIPH_CORE_STAT_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_CORE_STAT: AUTO Position */
+#define CCU1_CLK_PERIPH_CORE_STAT_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_AUTO_Pos) /*!< CCU1 CLK_PERIPH_CORE_STAT: AUTO Mask */
+#define CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_CORE_STAT: WAKEUP Position */
+#define CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_CORE_STAT: WAKEUP Mask */
+
+// -------------------------------- CCU1_CLK_PERIPH_SGPIO_CFG -----------------------------------
+#define CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_SGPIO_CFG: RUN Position */
+#define CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Pos) /*!< CCU1 CLK_PERIPH_SGPIO_CFG: RUN Mask */
+#define CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_SGPIO_CFG: AUTO Position */
+#define CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Pos) /*!< CCU1 CLK_PERIPH_SGPIO_CFG: AUTO Mask */
+#define CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_SGPIO_CFG: WAKEUP Position */
+#define CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_SGPIO_CFG: WAKEUP Mask */
+
+// ------------------------------- CCU1_CLK_PERIPH_SGPIO_STAT -----------------------------------
+#define CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_SGPIO_STAT: RUN Position */
+#define CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Pos) /*!< CCU1 CLK_PERIPH_SGPIO_STAT: RUN Mask */
+#define CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_SGPIO_STAT: AUTO Position */
+#define CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Pos) /*!< CCU1 CLK_PERIPH_SGPIO_STAT: AUTO Mask */
+#define CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_SGPIO_STAT: WAKEUP Position */
+#define CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_SGPIO_STAT: WAKEUP Mask */
+
+// ------------------------------------ CCU1_CLK_USB0_CFG ---------------------------------------
+#define CCU1_CLK_USB0_CFG_RUN_Pos 0 /*!< CCU1 CLK_USB0_CFG: RUN Position */
+#define CCU1_CLK_USB0_CFG_RUN_Msk (0x01UL << CCU1_CLK_USB0_CFG_RUN_Pos) /*!< CCU1 CLK_USB0_CFG: RUN Mask */
+#define CCU1_CLK_USB0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_USB0_CFG: AUTO Position */
+#define CCU1_CLK_USB0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_USB0_CFG_AUTO_Pos) /*!< CCU1 CLK_USB0_CFG: AUTO Mask */
+#define CCU1_CLK_USB0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_USB0_CFG: WAKEUP Position */
+#define CCU1_CLK_USB0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_USB0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_USB0_CFG: WAKEUP Mask */
+
+// ----------------------------------- CCU1_CLK_USB0_STAT ---------------------------------------
+#define CCU1_CLK_USB0_STAT_RUN_Pos 0 /*!< CCU1 CLK_USB0_STAT: RUN Position */
+#define CCU1_CLK_USB0_STAT_RUN_Msk (0x01UL << CCU1_CLK_USB0_STAT_RUN_Pos) /*!< CCU1 CLK_USB0_STAT: RUN Mask */
+#define CCU1_CLK_USB0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_USB0_STAT: AUTO Position */
+#define CCU1_CLK_USB0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_USB0_STAT_AUTO_Pos) /*!< CCU1 CLK_USB0_STAT: AUTO Mask */
+#define CCU1_CLK_USB0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_USB0_STAT: WAKEUP Position */
+#define CCU1_CLK_USB0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_USB0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_USB0_STAT: WAKEUP Mask */
+
+// ------------------------------------ CCU1_CLK_USB1_CFG ---------------------------------------
+#define CCU1_CLK_USB1_CFG_RUN_Pos 0 /*!< CCU1 CLK_USB1_CFG: RUN Position */
+#define CCU1_CLK_USB1_CFG_RUN_Msk (0x01UL << CCU1_CLK_USB1_CFG_RUN_Pos) /*!< CCU1 CLK_USB1_CFG: RUN Mask */
+#define CCU1_CLK_USB1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_USB1_CFG: AUTO Position */
+#define CCU1_CLK_USB1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_USB1_CFG_AUTO_Pos) /*!< CCU1 CLK_USB1_CFG: AUTO Mask */
+#define CCU1_CLK_USB1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_USB1_CFG: WAKEUP Position */
+#define CCU1_CLK_USB1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_USB1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_USB1_CFG: WAKEUP Mask */
+
+// ----------------------------------- CCU1_CLK_USB1_STAT ---------------------------------------
+#define CCU1_CLK_USB1_STAT_RUN_Pos 0 /*!< CCU1 CLK_USB1_STAT: RUN Position */
+#define CCU1_CLK_USB1_STAT_RUN_Msk (0x01UL << CCU1_CLK_USB1_STAT_RUN_Pos) /*!< CCU1 CLK_USB1_STAT: RUN Mask */
+#define CCU1_CLK_USB1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_USB1_STAT: AUTO Position */
+#define CCU1_CLK_USB1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_USB1_STAT_AUTO_Pos) /*!< CCU1 CLK_USB1_STAT: AUTO Mask */
+#define CCU1_CLK_USB1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_USB1_STAT: WAKEUP Position */
+#define CCU1_CLK_USB1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_USB1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_USB1_STAT: WAKEUP Mask */
+
+// ------------------------------------ CCU1_CLK_SPI_CFG ----------------------------------------
+#define CCU1_CLK_SPI_CFG_RUN_Pos 0 /*!< CCU1 CLK_SPI_CFG: RUN Position */
+#define CCU1_CLK_SPI_CFG_RUN_Msk (0x01UL << CCU1_CLK_SPI_CFG_RUN_Pos) /*!< CCU1 CLK_SPI_CFG: RUN Mask */
+#define CCU1_CLK_SPI_CFG_AUTO_Pos 1 /*!< CCU1 CLK_SPI_CFG: AUTO Position */
+#define CCU1_CLK_SPI_CFG_AUTO_Msk (0x01UL << CCU1_CLK_SPI_CFG_AUTO_Pos) /*!< CCU1 CLK_SPI_CFG: AUTO Mask */
+#define CCU1_CLK_SPI_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_SPI_CFG: WAKEUP Position */
+#define CCU1_CLK_SPI_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_SPI_CFG_WAKEUP_Pos) /*!< CCU1 CLK_SPI_CFG: WAKEUP Mask */
+
+// ------------------------------------ CCU1_CLK_SPI_STAT ---------------------------------------
+#define CCU1_CLK_SPI_STAT_RUN_Pos 0 /*!< CCU1 CLK_SPI_STAT: RUN Position */
+#define CCU1_CLK_SPI_STAT_RUN_Msk (0x01UL << CCU1_CLK_SPI_STAT_RUN_Pos) /*!< CCU1 CLK_SPI_STAT: RUN Mask */
+#define CCU1_CLK_SPI_STAT_AUTO_Pos 1 /*!< CCU1 CLK_SPI_STAT: AUTO Position */
+#define CCU1_CLK_SPI_STAT_AUTO_Msk (0x01UL << CCU1_CLK_SPI_STAT_AUTO_Pos) /*!< CCU1 CLK_SPI_STAT: AUTO Mask */
+#define CCU1_CLK_SPI_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_SPI_STAT: WAKEUP Position */
+#define CCU1_CLK_SPI_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_SPI_STAT_WAKEUP_Pos) /*!< CCU1 CLK_SPI_STAT: WAKEUP Mask */
+
+// ------------------------------------ CCU1_CLK_VADC_CFG ---------------------------------------
+#define CCU1_CLK_VADC_CFG_RUN_Pos 0 /*!< CCU1 CLK_VADC_CFG: RUN Position */
+#define CCU1_CLK_VADC_CFG_RUN_Msk (0x01UL << CCU1_CLK_VADC_CFG_RUN_Pos) /*!< CCU1 CLK_VADC_CFG: RUN Mask */
+#define CCU1_CLK_VADC_CFG_AUTO_Pos 1 /*!< CCU1 CLK_VADC_CFG: AUTO Position */
+#define CCU1_CLK_VADC_CFG_AUTO_Msk (0x01UL << CCU1_CLK_VADC_CFG_AUTO_Pos) /*!< CCU1 CLK_VADC_CFG: AUTO Mask */
+#define CCU1_CLK_VADC_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_VADC_CFG: WAKEUP Position */
+#define CCU1_CLK_VADC_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_VADC_CFG_WAKEUP_Pos) /*!< CCU1 CLK_VADC_CFG: WAKEUP Mask */
+
+// ----------------------------------- CCU1_CLK_VADC_STAT ---------------------------------------
+#define CCU1_CLK_VADC_STAT_RUN_Pos 0 /*!< CCU1 CLK_VADC_STAT: RUN Position */
+#define CCU1_CLK_VADC_STAT_RUN_Msk (0x01UL << CCU1_CLK_VADC_STAT_RUN_Pos) /*!< CCU1 CLK_VADC_STAT: RUN Mask */
+#define CCU1_CLK_VADC_STAT_AUTO_Pos 1 /*!< CCU1 CLK_VADC_STAT: AUTO Position */
+#define CCU1_CLK_VADC_STAT_AUTO_Msk (0x01UL << CCU1_CLK_VADC_STAT_AUTO_Pos) /*!< CCU1 CLK_VADC_STAT: AUTO Mask */
+#define CCU1_CLK_VADC_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_VADC_STAT: WAKEUP Position */
+#define CCU1_CLK_VADC_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_VADC_STAT_WAKEUP_Pos) /*!< CCU1 CLK_VADC_STAT: WAKEUP Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- CCU2 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------- CCU2_PM --------------------------------------------
+#define CCU2_PM_PD_Pos 0 /*!< CCU2 PM: PD Position */
+#define CCU2_PM_PD_Msk (0x01UL << CCU2_PM_PD_Pos) /*!< CCU2 PM: PD Mask */
+
+// ------------------------------------- CCU2_BASE_STAT -----------------------------------------
+#define CCU2_BASE_STAT_BASE_UART3_CLK_Pos 1 /*!< CCU2 BASE_STAT: BASE_UART3_CLK Position */
+#define CCU2_BASE_STAT_BASE_UART3_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART3_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART3_CLK Mask */
+#define CCU2_BASE_STAT_BASE_UART2_CLK_Pos 2 /*!< CCU2 BASE_STAT: BASE_UART2_CLK Position */
+#define CCU2_BASE_STAT_BASE_UART2_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART2_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART2_CLK Mask */
+#define CCU2_BASE_STAT_BASE_UART1_CLK_Pos 3 /*!< CCU2 BASE_STAT: BASE_UART1_CLK Position */
+#define CCU2_BASE_STAT_BASE_UART1_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART1_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART1_CLK Mask */
+#define CCU2_BASE_STAT_BASE_UART0_CLK_Pos 4 /*!< CCU2 BASE_STAT: BASE_UART0_CLK Position */
+#define CCU2_BASE_STAT_BASE_UART0_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART0_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART0_CLK Mask */
+#define CCU2_BASE_STAT_BASE_SSP1_CLK_Pos 5 /*!< CCU2 BASE_STAT: BASE_SSP1_CLK Position */
+#define CCU2_BASE_STAT_BASE_SSP1_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_SSP1_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_SSP1_CLK Mask */
+#define CCU2_BASE_STAT_BASE_SSP0_CLK_Pos 6 /*!< CCU2 BASE_STAT: BASE_SSP0_CLK Position */
+#define CCU2_BASE_STAT_BASE_SSP0_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_SSP0_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_SSP0_CLK Mask */
+
+// ------------------------------------ CCU2_CLK_APLL_CFG ---------------------------------------
+#define CCU2_CLK_APLL_CFG_RUN_Pos 0 /*!< CCU2 CLK_APLL_CFG: RUN Position */
+#define CCU2_CLK_APLL_CFG_RUN_Msk (0x01UL << CCU2_CLK_APLL_CFG_RUN_Pos) /*!< CCU2 CLK_APLL_CFG: RUN Mask */
+#define CCU2_CLK_APLL_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APLL_CFG: AUTO Position */
+#define CCU2_CLK_APLL_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APLL_CFG_AUTO_Pos) /*!< CCU2 CLK_APLL_CFG: AUTO Mask */
+#define CCU2_CLK_APLL_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APLL_CFG: WAKEUP Position */
+#define CCU2_CLK_APLL_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APLL_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APLL_CFG: WAKEUP Mask */
+
+// ----------------------------------- CCU2_CLK_APLL_STAT ---------------------------------------
+#define CCU2_CLK_APLL_STAT_RUN_Pos 0 /*!< CCU2 CLK_APLL_STAT: RUN Position */
+#define CCU2_CLK_APLL_STAT_RUN_Msk (0x01UL << CCU2_CLK_APLL_STAT_RUN_Pos) /*!< CCU2 CLK_APLL_STAT: RUN Mask */
+#define CCU2_CLK_APLL_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APLL_STAT: AUTO Position */
+#define CCU2_CLK_APLL_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APLL_STAT_AUTO_Pos) /*!< CCU2 CLK_APLL_STAT: AUTO Mask */
+#define CCU2_CLK_APLL_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APLL_STAT: WAKEUP Position */
+#define CCU2_CLK_APLL_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APLL_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APLL_STAT: WAKEUP Mask */
+
+// -------------------------------- CCU2_CLK_APB2_USART3_CFG ------------------------------------
+#define CCU2_CLK_APB2_USART3_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART3_CFG: RUN Position */
+#define CCU2_CLK_APB2_USART3_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART3_CFG_RUN_Pos) /*!< CCU2 CLK_APB2_USART3_CFG: RUN Mask */
+#define CCU2_CLK_APB2_USART3_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART3_CFG: AUTO Position */
+#define CCU2_CLK_APB2_USART3_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART3_CFG_AUTO_Pos) /*!< CCU2 CLK_APB2_USART3_CFG: AUTO Mask */
+#define CCU2_CLK_APB2_USART3_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART3_CFG: WAKEUP Position */
+#define CCU2_CLK_APB2_USART3_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART3_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART3_CFG: WAKEUP Mask */
+
+// -------------------------------- CCU2_CLK_APB2_USART3_STAT -----------------------------------
+#define CCU2_CLK_APB2_USART3_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART3_STAT: RUN Position */
+#define CCU2_CLK_APB2_USART3_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART3_STAT_RUN_Pos) /*!< CCU2 CLK_APB2_USART3_STAT: RUN Mask */
+#define CCU2_CLK_APB2_USART3_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART3_STAT: AUTO Position */
+#define CCU2_CLK_APB2_USART3_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART3_STAT_AUTO_Pos) /*!< CCU2 CLK_APB2_USART3_STAT: AUTO Mask */
+#define CCU2_CLK_APB2_USART3_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART3_STAT: WAKEUP Position */
+#define CCU2_CLK_APB2_USART3_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART3_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART3_STAT: WAKEUP Mask */
+
+// -------------------------------- CCU2_CLK_APB2_USART2_CFG ------------------------------------
+#define CCU2_CLK_APB2_USART2_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART2_CFG: RUN Position */
+#define CCU2_CLK_APB2_USART2_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART2_CFG_RUN_Pos) /*!< CCU2 CLK_APB2_USART2_CFG: RUN Mask */
+#define CCU2_CLK_APB2_USART2_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART2_CFG: AUTO Position */
+#define CCU2_CLK_APB2_USART2_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART2_CFG_AUTO_Pos) /*!< CCU2 CLK_APB2_USART2_CFG: AUTO Mask */
+#define CCU2_CLK_APB2_USART2_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART2_CFG: WAKEUP Position */
+#define CCU2_CLK_APB2_USART2_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART2_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART2_CFG: WAKEUP Mask */
+
+// -------------------------------- CCU2_CLK_APB2_USART2_STAT -----------------------------------
+#define CCU2_CLK_APB2_USART2_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART2_STAT: RUN Position */
+#define CCU2_CLK_APB2_USART2_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART2_STAT_RUN_Pos) /*!< CCU2 CLK_APB2_USART2_STAT: RUN Mask */
+#define CCU2_CLK_APB2_USART2_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART2_STAT: AUTO Position */
+#define CCU2_CLK_APB2_USART2_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART2_STAT_AUTO_Pos) /*!< CCU2 CLK_APB2_USART2_STAT: AUTO Mask */
+#define CCU2_CLK_APB2_USART2_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART2_STAT: WAKEUP Position */
+#define CCU2_CLK_APB2_USART2_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART2_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART2_STAT: WAKEUP Mask */
+
+// ------------------------------- CCU2_CLK_APB0_UART1_BUS_CFG ----------------------------------
+#define CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB0_UART1_BUS_CFG: RUN Position */
+#define CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Pos) /*!< CCU2 CLK_APB0_UART1_BUS_CFG: RUN Mask */
+#define CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB0_UART1_BUS_CFG: AUTO Position */
+#define CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Pos) /*!< CCU2 CLK_APB0_UART1_BUS_CFG: AUTO Mask */
+#define CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_UART1_BUS_CFG: WAKEUP Position */
+#define CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB0_UART1_BUS_CFG: WAKEUP Mask */
+
+// -------------------------------- CCU2_CLK_APB0_UART1_STAT ------------------------------------
+#define CCU2_CLK_APB0_UART1_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB0_UART1_STAT: RUN Position */
+#define CCU2_CLK_APB0_UART1_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB0_UART1_STAT_RUN_Pos) /*!< CCU2 CLK_APB0_UART1_STAT: RUN Mask */
+#define CCU2_CLK_APB0_UART1_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB0_UART1_STAT: AUTO Position */
+#define CCU2_CLK_APB0_UART1_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB0_UART1_STAT_AUTO_Pos) /*!< CCU2 CLK_APB0_UART1_STAT: AUTO Mask */
+#define CCU2_CLK_APB0_UART1_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_UART1_STAT: WAKEUP Position */
+#define CCU2_CLK_APB0_UART1_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_UART1_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB0_UART1_STAT: WAKEUP Mask */
+
+// -------------------------------- CCU2_CLK_APB0_USART0_CFG ------------------------------------
+#define CCU2_CLK_APB0_USART0_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB0_USART0_CFG: RUN Position */
+#define CCU2_CLK_APB0_USART0_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB0_USART0_CFG_RUN_Pos) /*!< CCU2 CLK_APB0_USART0_CFG: RUN Mask */
+#define CCU2_CLK_APB0_USART0_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB0_USART0_CFG: AUTO Position */
+#define CCU2_CLK_APB0_USART0_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB0_USART0_CFG_AUTO_Pos) /*!< CCU2 CLK_APB0_USART0_CFG: AUTO Mask */
+#define CCU2_CLK_APB0_USART0_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_USART0_CFG: WAKEUP Position */
+#define CCU2_CLK_APB0_USART0_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_USART0_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB0_USART0_CFG: WAKEUP Mask */
+
+// -------------------------------- CCU2_CLK_APB0_USART0_STAT -----------------------------------
+#define CCU2_CLK_APB0_USART0_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB0_USART0_STAT: RUN Position */
+#define CCU2_CLK_APB0_USART0_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB0_USART0_STAT_RUN_Pos) /*!< CCU2 CLK_APB0_USART0_STAT: RUN Mask */
+#define CCU2_CLK_APB0_USART0_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB0_USART0_STAT: AUTO Position */
+#define CCU2_CLK_APB0_USART0_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB0_USART0_STAT_AUTO_Pos) /*!< CCU2 CLK_APB0_USART0_STAT: AUTO Mask */
+#define CCU2_CLK_APB0_USART0_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_USART0_STAT: WAKEUP Position */
+#define CCU2_CLK_APB0_USART0_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_USART0_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB0_USART0_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU2_CLK_APB2_SSP1_CFG -------------------------------------
+#define CCU2_CLK_APB2_SSP1_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB2_SSP1_CFG: RUN Position */
+#define CCU2_CLK_APB2_SSP1_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB2_SSP1_CFG_RUN_Pos) /*!< CCU2 CLK_APB2_SSP1_CFG: RUN Mask */
+#define CCU2_CLK_APB2_SSP1_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB2_SSP1_CFG: AUTO Position */
+#define CCU2_CLK_APB2_SSP1_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB2_SSP1_CFG_AUTO_Pos) /*!< CCU2 CLK_APB2_SSP1_CFG: AUTO Mask */
+#define CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_SSP1_CFG: WAKEUP Position */
+#define CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB2_SSP1_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU2_CLK_APB2_SSP1_STAT ------------------------------------
+#define CCU2_CLK_APB2_SSP1_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB2_SSP1_STAT: RUN Position */
+#define CCU2_CLK_APB2_SSP1_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB2_SSP1_STAT_RUN_Pos) /*!< CCU2 CLK_APB2_SSP1_STAT: RUN Mask */
+#define CCU2_CLK_APB2_SSP1_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB2_SSP1_STAT: AUTO Position */
+#define CCU2_CLK_APB2_SSP1_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB2_SSP1_STAT_AUTO_Pos) /*!< CCU2 CLK_APB2_SSP1_STAT: AUTO Mask */
+#define CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_SSP1_STAT: WAKEUP Position */
+#define CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB2_SSP1_STAT: WAKEUP Mask */
+
+// --------------------------------- CCU2_CLK_APB0_SSP0_CFG -------------------------------------
+#define CCU2_CLK_APB0_SSP0_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB0_SSP0_CFG: RUN Position */
+#define CCU2_CLK_APB0_SSP0_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB0_SSP0_CFG_RUN_Pos) /*!< CCU2 CLK_APB0_SSP0_CFG: RUN Mask */
+#define CCU2_CLK_APB0_SSP0_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB0_SSP0_CFG: AUTO Position */
+#define CCU2_CLK_APB0_SSP0_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB0_SSP0_CFG_AUTO_Pos) /*!< CCU2 CLK_APB0_SSP0_CFG: AUTO Mask */
+#define CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_SSP0_CFG: WAKEUP Position */
+#define CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB0_SSP0_CFG: WAKEUP Mask */
+
+// --------------------------------- CCU2_CLK_APB0_SSP0_STAT ------------------------------------
+#define CCU2_CLK_APB0_SSP0_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB0_SSP0_STAT: RUN Position */
+#define CCU2_CLK_APB0_SSP0_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB0_SSP0_STAT_RUN_Pos) /*!< CCU2 CLK_APB0_SSP0_STAT: RUN Mask */
+#define CCU2_CLK_APB0_SSP0_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB0_SSP0_STAT: AUTO Position */
+#define CCU2_CLK_APB0_SSP0_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB0_SSP0_STAT_AUTO_Pos) /*!< CCU2 CLK_APB0_SSP0_STAT: AUTO Mask */
+#define CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_SSP0_STAT: WAKEUP Position */
+#define CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB0_SSP0_STAT: WAKEUP Mask */
+
+// ------------------------------------ CCU2_CLK_SDIO_CFG ---------------------------------------
+#define CCU2_CLK_SDIO_CFG_RUN_Pos 0 /*!< CCU2 CLK_SDIO_CFG: RUN Position */
+#define CCU2_CLK_SDIO_CFG_RUN_Msk (0x01UL << CCU2_CLK_SDIO_CFG_RUN_Pos) /*!< CCU2 CLK_SDIO_CFG: RUN Mask */
+#define CCU2_CLK_SDIO_CFG_AUTO_Pos 1 /*!< CCU2 CLK_SDIO_CFG: AUTO Position */
+#define CCU2_CLK_SDIO_CFG_AUTO_Msk (0x01UL << CCU2_CLK_SDIO_CFG_AUTO_Pos) /*!< CCU2 CLK_SDIO_CFG: AUTO Mask */
+#define CCU2_CLK_SDIO_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_SDIO_CFG: WAKEUP Position */
+#define CCU2_CLK_SDIO_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_SDIO_CFG_WAKEUP_Pos) /*!< CCU2 CLK_SDIO_CFG: WAKEUP Mask */
+
+// ----------------------------------- CCU2_CLK_SDIO_STAT ---------------------------------------
+#define CCU2_CLK_SDIO_STAT_RUN_Pos 0 /*!< CCU2 CLK_SDIO_STAT: RUN Position */
+#define CCU2_CLK_SDIO_STAT_RUN_Msk (0x01UL << CCU2_CLK_SDIO_STAT_RUN_Pos) /*!< CCU2 CLK_SDIO_STAT: RUN Mask */
+#define CCU2_CLK_SDIO_STAT_AUTO_Pos 1 /*!< CCU2 CLK_SDIO_STAT: AUTO Position */
+#define CCU2_CLK_SDIO_STAT_AUTO_Msk (0x01UL << CCU2_CLK_SDIO_STAT_AUTO_Pos) /*!< CCU2 CLK_SDIO_STAT: AUTO Mask */
+#define CCU2_CLK_SDIO_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_SDIO_STAT: WAKEUP Position */
+#define CCU2_CLK_SDIO_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_SDIO_STAT_WAKEUP_Pos) /*!< CCU2 CLK_SDIO_STAT: WAKEUP Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- RGU Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ------------------------------------- RGU_RESET_CTRL0 ----------------------------------------
+#define RGU_RESET_CTRL0_CORE_RST_Pos 0 /*!< RGU RESET_CTRL0: CORE_RST Position */
+#define RGU_RESET_CTRL0_CORE_RST_Msk (0x01UL << RGU_RESET_CTRL0_CORE_RST_Pos) /*!< RGU RESET_CTRL0: CORE_RST Mask */
+#define RGU_RESET_CTRL0_PERIPH_RST_Pos 1 /*!< RGU RESET_CTRL0: PERIPH_RST Position */
+#define RGU_RESET_CTRL0_PERIPH_RST_Msk (0x01UL << RGU_RESET_CTRL0_PERIPH_RST_Pos) /*!< RGU RESET_CTRL0: PERIPH_RST Mask */
+#define RGU_RESET_CTRL0_MASTER_RST_Pos 2 /*!< RGU RESET_CTRL0: MASTER_RST Position */
+#define RGU_RESET_CTRL0_MASTER_RST_Msk (0x01UL << RGU_RESET_CTRL0_MASTER_RST_Pos) /*!< RGU RESET_CTRL0: MASTER_RST Mask */
+#define RGU_RESET_CTRL0_WWDT_RST_Pos 4 /*!< RGU RESET_CTRL0: WWDT_RST Position */
+#define RGU_RESET_CTRL0_WWDT_RST_Msk (0x01UL << RGU_RESET_CTRL0_WWDT_RST_Pos) /*!< RGU RESET_CTRL0: WWDT_RST Mask */
+#define RGU_RESET_CTRL0_CREG_RST_Pos 5 /*!< RGU RESET_CTRL0: CREG_RST Position */
+#define RGU_RESET_CTRL0_CREG_RST_Msk (0x01UL << RGU_RESET_CTRL0_CREG_RST_Pos) /*!< RGU RESET_CTRL0: CREG_RST Mask */
+#define RGU_RESET_CTRL0_BUS_RST_Pos 8 /*!< RGU RESET_CTRL0: BUS_RST Position */
+#define RGU_RESET_CTRL0_BUS_RST_Msk (0x01UL << RGU_RESET_CTRL0_BUS_RST_Pos) /*!< RGU RESET_CTRL0: BUS_RST Mask */
+#define RGU_RESET_CTRL0_SCU_RST_Pos 9 /*!< RGU RESET_CTRL0: SCU_RST Position */
+#define RGU_RESET_CTRL0_SCU_RST_Msk (0x01UL << RGU_RESET_CTRL0_SCU_RST_Pos) /*!< RGU RESET_CTRL0: SCU_RST Mask */
+#define RGU_RESET_CTRL0_PINMUX_RST_Pos 10 /*!< RGU RESET_CTRL0: PINMUX_RST Position */
+#define RGU_RESET_CTRL0_PINMUX_RST_Msk (0x01UL << RGU_RESET_CTRL0_PINMUX_RST_Pos) /*!< RGU RESET_CTRL0: PINMUX_RST Mask */
+#define RGU_RESET_CTRL0_M4_RST_Pos 13 /*!< RGU RESET_CTRL0: M4_RST Position */
+#define RGU_RESET_CTRL0_M4_RST_Msk (0x01UL << RGU_RESET_CTRL0_M4_RST_Pos) /*!< RGU RESET_CTRL0: M4_RST Mask */
+#define RGU_RESET_CTRL0_LCD_RST_Pos 16 /*!< RGU RESET_CTRL0: LCD_RST Position */
+#define RGU_RESET_CTRL0_LCD_RST_Msk (0x01UL << RGU_RESET_CTRL0_LCD_RST_Pos) /*!< RGU RESET_CTRL0: LCD_RST Mask */
+#define RGU_RESET_CTRL0_USB0_RST_Pos 17 /*!< RGU RESET_CTRL0: USB0_RST Position */
+#define RGU_RESET_CTRL0_USB0_RST_Msk (0x01UL << RGU_RESET_CTRL0_USB0_RST_Pos) /*!< RGU RESET_CTRL0: USB0_RST Mask */
+#define RGU_RESET_CTRL0_USB1_RST_Pos 18 /*!< RGU RESET_CTRL0: USB1_RST Position */
+#define RGU_RESET_CTRL0_USB1_RST_Msk (0x01UL << RGU_RESET_CTRL0_USB1_RST_Pos) /*!< RGU RESET_CTRL0: USB1_RST Mask */
+#define RGU_RESET_CTRL0_DMA_RST_Pos 19 /*!< RGU RESET_CTRL0: DMA_RST Position */
+#define RGU_RESET_CTRL0_DMA_RST_Msk (0x01UL << RGU_RESET_CTRL0_DMA_RST_Pos) /*!< RGU RESET_CTRL0: DMA_RST Mask */
+#define RGU_RESET_CTRL0_SDIO_RST_Pos 20 /*!< RGU RESET_CTRL0: SDIO_RST Position */
+#define RGU_RESET_CTRL0_SDIO_RST_Msk (0x01UL << RGU_RESET_CTRL0_SDIO_RST_Pos) /*!< RGU RESET_CTRL0: SDIO_RST Mask */
+#define RGU_RESET_CTRL0_EMC_RST_Pos 21 /*!< RGU RESET_CTRL0: EMC_RST Position */
+#define RGU_RESET_CTRL0_EMC_RST_Msk (0x01UL << RGU_RESET_CTRL0_EMC_RST_Pos) /*!< RGU RESET_CTRL0: EMC_RST Mask */
+#define RGU_RESET_CTRL0_ETHERNET_RST_Pos 22 /*!< RGU RESET_CTRL0: ETHERNET_RST Position */
+#define RGU_RESET_CTRL0_ETHERNET_RST_Msk (0x01UL << RGU_RESET_CTRL0_ETHERNET_RST_Pos) /*!< RGU RESET_CTRL0: ETHERNET_RST Mask */
+#define RGU_RESET_CTRL0_GPIO_RST_Pos 28 /*!< RGU RESET_CTRL0: GPIO_RST Position */
+#define RGU_RESET_CTRL0_GPIO_RST_Msk (0x01UL << RGU_RESET_CTRL0_GPIO_RST_Pos) /*!< RGU RESET_CTRL0: GPIO_RST Mask */
+
+// ------------------------------------- RGU_RESET_CTRL1 ----------------------------------------
+#define RGU_RESET_CTRL1_TIMER0_RST_Pos 0 /*!< RGU RESET_CTRL1: TIMER0_RST Position */
+#define RGU_RESET_CTRL1_TIMER0_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER0_RST_Pos) /*!< RGU RESET_CTRL1: TIMER0_RST Mask */
+#define RGU_RESET_CTRL1_TIMER1_RST_Pos 1 /*!< RGU RESET_CTRL1: TIMER1_RST Position */
+#define RGU_RESET_CTRL1_TIMER1_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER1_RST_Pos) /*!< RGU RESET_CTRL1: TIMER1_RST Mask */
+#define RGU_RESET_CTRL1_TIMER2_RST_Pos 2 /*!< RGU RESET_CTRL1: TIMER2_RST Position */
+#define RGU_RESET_CTRL1_TIMER2_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER2_RST_Pos) /*!< RGU RESET_CTRL1: TIMER2_RST Mask */
+#define RGU_RESET_CTRL1_TIMER3_RST_Pos 3 /*!< RGU RESET_CTRL1: TIMER3_RST Position */
+#define RGU_RESET_CTRL1_TIMER3_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER3_RST_Pos) /*!< RGU RESET_CTRL1: TIMER3_RST Mask */
+#define RGU_RESET_CTRL1_RITIMER_RST_Pos 4 /*!< RGU RESET_CTRL1: RITIMER_RST Position */
+#define RGU_RESET_CTRL1_RITIMER_RST_Msk (0x01UL << RGU_RESET_CTRL1_RITIMER_RST_Pos) /*!< RGU RESET_CTRL1: RITIMER_RST Mask */
+#define RGU_RESET_CTRL1_SCT_RST_Pos 5 /*!< RGU RESET_CTRL1: SCT_RST Position */
+#define RGU_RESET_CTRL1_SCT_RST_Msk (0x01UL << RGU_RESET_CTRL1_SCT_RST_Pos) /*!< RGU RESET_CTRL1: SCT_RST Mask */
+#define RGU_RESET_CTRL1_MOTOCONPWM_RST_Pos 6 /*!< RGU RESET_CTRL1: MOTOCONPWM_RST Position */
+#define RGU_RESET_CTRL1_MOTOCONPWM_RST_Msk (0x01UL << RGU_RESET_CTRL1_MOTOCONPWM_RST_Pos) /*!< RGU RESET_CTRL1: MOTOCONPWM_RST Mask */
+#define RGU_RESET_CTRL1_QEI_RST_Pos 7 /*!< RGU RESET_CTRL1: QEI_RST Position */
+#define RGU_RESET_CTRL1_QEI_RST_Msk (0x01UL << RGU_RESET_CTRL1_QEI_RST_Pos) /*!< RGU RESET_CTRL1: QEI_RST Mask */
+#define RGU_RESET_CTRL1_ADC0_RST_Pos 8 /*!< RGU RESET_CTRL1: ADC0_RST Position */
+#define RGU_RESET_CTRL1_ADC0_RST_Msk (0x01UL << RGU_RESET_CTRL1_ADC0_RST_Pos) /*!< RGU RESET_CTRL1: ADC0_RST Mask */
+#define RGU_RESET_CTRL1_ADC1_RST_Pos 9 /*!< RGU RESET_CTRL1: ADC1_RST Position */
+#define RGU_RESET_CTRL1_ADC1_RST_Msk (0x01UL << RGU_RESET_CTRL1_ADC1_RST_Pos) /*!< RGU RESET_CTRL1: ADC1_RST Mask */
+#define RGU_RESET_CTRL1_DAC_RST_Pos 10 /*!< RGU RESET_CTRL1: DAC_RST Position */
+#define RGU_RESET_CTRL1_DAC_RST_Msk (0x01UL << RGU_RESET_CTRL1_DAC_RST_Pos) /*!< RGU RESET_CTRL1: DAC_RST Mask */
+#define RGU_RESET_CTRL1_UART0_RST_Pos 12 /*!< RGU RESET_CTRL1: UART0_RST Position */
+#define RGU_RESET_CTRL1_UART0_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART0_RST_Pos) /*!< RGU RESET_CTRL1: UART0_RST Mask */
+#define RGU_RESET_CTRL1_UART1_RST_Pos 13 /*!< RGU RESET_CTRL1: UART1_RST Position */
+#define RGU_RESET_CTRL1_UART1_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART1_RST_Pos) /*!< RGU RESET_CTRL1: UART1_RST Mask */
+#define RGU_RESET_CTRL1_UART2_RST_Pos 14 /*!< RGU RESET_CTRL1: UART2_RST Position */
+#define RGU_RESET_CTRL1_UART2_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART2_RST_Pos) /*!< RGU RESET_CTRL1: UART2_RST Mask */
+#define RGU_RESET_CTRL1_UART3_RST_Pos 15 /*!< RGU RESET_CTRL1: UART3_RST Position */
+#define RGU_RESET_CTRL1_UART3_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART3_RST_Pos) /*!< RGU RESET_CTRL1: UART3_RST Mask */
+#define RGU_RESET_CTRL1_I2C0_RST_Pos 16 /*!< RGU RESET_CTRL1: I2C0_RST Position */
+#define RGU_RESET_CTRL1_I2C0_RST_Msk (0x01UL << RGU_RESET_CTRL1_I2C0_RST_Pos) /*!< RGU RESET_CTRL1: I2C0_RST Mask */
+#define RGU_RESET_CTRL1_I2C1_RST_Pos 17 /*!< RGU RESET_CTRL1: I2C1_RST Position */
+#define RGU_RESET_CTRL1_I2C1_RST_Msk (0x01UL << RGU_RESET_CTRL1_I2C1_RST_Pos) /*!< RGU RESET_CTRL1: I2C1_RST Mask */
+#define RGU_RESET_CTRL1_SSP0_RST_Pos 18 /*!< RGU RESET_CTRL1: SSP0_RST Position */
+#define RGU_RESET_CTRL1_SSP0_RST_Msk (0x01UL << RGU_RESET_CTRL1_SSP0_RST_Pos) /*!< RGU RESET_CTRL1: SSP0_RST Mask */
+#define RGU_RESET_CTRL1_SSP1_RST_Pos 19 /*!< RGU RESET_CTRL1: SSP1_RST Position */
+#define RGU_RESET_CTRL1_SSP1_RST_Msk (0x01UL << RGU_RESET_CTRL1_SSP1_RST_Pos) /*!< RGU RESET_CTRL1: SSP1_RST Mask */
+#define RGU_RESET_CTRL1_I2S_RST_Pos 20 /*!< RGU RESET_CTRL1: I2S_RST Position */
+#define RGU_RESET_CTRL1_I2S_RST_Msk (0x01UL << RGU_RESET_CTRL1_I2S_RST_Pos) /*!< RGU RESET_CTRL1: I2S_RST Mask */
+#define RGU_RESET_CTRL1_SPIFI_RST_Pos 21 /*!< RGU RESET_CTRL1: SPIFI_RST Position */
+#define RGU_RESET_CTRL1_SPIFI_RST_Msk (0x01UL << RGU_RESET_CTRL1_SPIFI_RST_Pos) /*!< RGU RESET_CTRL1: SPIFI_RST Mask */
+#define RGU_RESET_CTRL1_CAN1_RST_Pos 22 /*!< RGU RESET_CTRL1: CAN1_RST Position */
+#define RGU_RESET_CTRL1_CAN1_RST_Msk (0x01UL << RGU_RESET_CTRL1_CAN1_RST_Pos) /*!< RGU RESET_CTRL1: CAN1_RST Mask */
+#define RGU_RESET_CTRL1_CAN0_RST_Pos 23 /*!< RGU RESET_CTRL1: CAN0_RST Position */
+#define RGU_RESET_CTRL1_CAN0_RST_Msk (0x01UL << RGU_RESET_CTRL1_CAN0_RST_Pos) /*!< RGU RESET_CTRL1: CAN0_RST Mask */
+#define RGU_RESET_CTRL1_M0APP_RST_Pos 24 /*!< RGU RESET_CTRL1: M0APP_RST Position */
+#define RGU_RESET_CTRL1_M0APP_RST_Msk (0x01UL << RGU_RESET_CTRL1_M0APP_RST_Pos) /*!< RGU RESET_CTRL1: M0APP_RST Mask */
+#define RGU_RESET_CTRL1_SGPIO_RST_Pos 25 /*!< RGU RESET_CTRL1: SGPIO_RST Position */
+#define RGU_RESET_CTRL1_SGPIO_RST_Msk (0x01UL << RGU_RESET_CTRL1_SGPIO_RST_Pos) /*!< RGU RESET_CTRL1: SGPIO_RST Mask */
+#define RGU_RESET_CTRL1_SPI_RST_Pos 26 /*!< RGU RESET_CTRL1: SPI_RST Position */
+#define RGU_RESET_CTRL1_SPI_RST_Msk (0x01UL << RGU_RESET_CTRL1_SPI_RST_Pos) /*!< RGU RESET_CTRL1: SPI_RST Mask */
+
+// ------------------------------------ RGU_RESET_STATUS0 ---------------------------------------
+#define RGU_RESET_STATUS0_CORE_RST_Pos 0 /*!< RGU RESET_STATUS0: CORE_RST Position */
+#define RGU_RESET_STATUS0_CORE_RST_Msk (0x03UL << RGU_RESET_STATUS0_CORE_RST_Pos) /*!< RGU RESET_STATUS0: CORE_RST Mask */
+#define RGU_RESET_STATUS0_PERIPH_RST_Pos 2 /*!< RGU RESET_STATUS0: PERIPH_RST Position */
+#define RGU_RESET_STATUS0_PERIPH_RST_Msk (0x03UL << RGU_RESET_STATUS0_PERIPH_RST_Pos) /*!< RGU RESET_STATUS0: PERIPH_RST Mask */
+#define RGU_RESET_STATUS0_MASTER_RST_Pos 4 /*!< RGU RESET_STATUS0: MASTER_RST Position */
+#define RGU_RESET_STATUS0_MASTER_RST_Msk (0x03UL << RGU_RESET_STATUS0_MASTER_RST_Pos) /*!< RGU RESET_STATUS0: MASTER_RST Mask */
+#define RGU_RESET_STATUS0_WWDT_RST_Pos 8 /*!< RGU RESET_STATUS0: WWDT_RST Position */
+#define RGU_RESET_STATUS0_WWDT_RST_Msk (0x03UL << RGU_RESET_STATUS0_WWDT_RST_Pos) /*!< RGU RESET_STATUS0: WWDT_RST Mask */
+#define RGU_RESET_STATUS0_CREG_RST_Pos 10 /*!< RGU RESET_STATUS0: CREG_RST Position */
+#define RGU_RESET_STATUS0_CREG_RST_Msk (0x03UL << RGU_RESET_STATUS0_CREG_RST_Pos) /*!< RGU RESET_STATUS0: CREG_RST Mask */
+#define RGU_RESET_STATUS0_BUS_RST_Pos 16 /*!< RGU RESET_STATUS0: BUS_RST Position */
+#define RGU_RESET_STATUS0_BUS_RST_Msk (0x03UL << RGU_RESET_STATUS0_BUS_RST_Pos) /*!< RGU RESET_STATUS0: BUS_RST Mask */
+#define RGU_RESET_STATUS0_SCU_RST_Pos 18 /*!< RGU RESET_STATUS0: SCU_RST Position */
+#define RGU_RESET_STATUS0_SCU_RST_Msk (0x03UL << RGU_RESET_STATUS0_SCU_RST_Pos) /*!< RGU RESET_STATUS0: SCU_RST Mask */
+#define RGU_RESET_STATUS0_M4_RST_Pos 26 /*!< RGU RESET_STATUS0: M4_RST Position */
+#define RGU_RESET_STATUS0_M4_RST_Msk (0x03UL << RGU_RESET_STATUS0_M4_RST_Pos) /*!< RGU RESET_STATUS0: M4_RST Mask */
+
+// ------------------------------------ RGU_RESET_STATUS1 ---------------------------------------
+#define RGU_RESET_STATUS1_LCD_RST_Pos 0 /*!< RGU RESET_STATUS1: LCD_RST Position */
+#define RGU_RESET_STATUS1_LCD_RST_Msk (0x03UL << RGU_RESET_STATUS1_LCD_RST_Pos) /*!< RGU RESET_STATUS1: LCD_RST Mask */
+#define RGU_RESET_STATUS1_USB0_RST_Pos 2 /*!< RGU RESET_STATUS1: USB0_RST Position */
+#define RGU_RESET_STATUS1_USB0_RST_Msk (0x03UL << RGU_RESET_STATUS1_USB0_RST_Pos) /*!< RGU RESET_STATUS1: USB0_RST Mask */
+#define RGU_RESET_STATUS1_USB1_RST_Pos 4 /*!< RGU RESET_STATUS1: USB1_RST Position */
+#define RGU_RESET_STATUS1_USB1_RST_Msk (0x03UL << RGU_RESET_STATUS1_USB1_RST_Pos) /*!< RGU RESET_STATUS1: USB1_RST Mask */
+#define RGU_RESET_STATUS1_DMA_RST_Pos 6 /*!< RGU RESET_STATUS1: DMA_RST Position */
+#define RGU_RESET_STATUS1_DMA_RST_Msk (0x03UL << RGU_RESET_STATUS1_DMA_RST_Pos) /*!< RGU RESET_STATUS1: DMA_RST Mask */
+#define RGU_RESET_STATUS1_SDIO_RST_Pos 8 /*!< RGU RESET_STATUS1: SDIO_RST Position */
+#define RGU_RESET_STATUS1_SDIO_RST_Msk (0x03UL << RGU_RESET_STATUS1_SDIO_RST_Pos) /*!< RGU RESET_STATUS1: SDIO_RST Mask */
+#define RGU_RESET_STATUS1_EMC_RST_Pos 10 /*!< RGU RESET_STATUS1: EMC_RST Position */
+#define RGU_RESET_STATUS1_EMC_RST_Msk (0x03UL << RGU_RESET_STATUS1_EMC_RST_Pos) /*!< RGU RESET_STATUS1: EMC_RST Mask */
+#define RGU_RESET_STATUS1_ETHERNET_RST_Pos 12 /*!< RGU RESET_STATUS1: ETHERNET_RST Position */
+#define RGU_RESET_STATUS1_ETHERNET_RST_Msk (0x03UL << RGU_RESET_STATUS1_ETHERNET_RST_Pos) /*!< RGU RESET_STATUS1: ETHERNET_RST Mask */
+#define RGU_RESET_STATUS1_GPIO_RST_Pos 24 /*!< RGU RESET_STATUS1: GPIO_RST Position */
+#define RGU_RESET_STATUS1_GPIO_RST_Msk (0x03UL << RGU_RESET_STATUS1_GPIO_RST_Pos) /*!< RGU RESET_STATUS1: GPIO_RST Mask */
+
+// ------------------------------------ RGU_RESET_STATUS2 ---------------------------------------
+#define RGU_RESET_STATUS2_TIMER0_RST_Pos 0 /*!< RGU RESET_STATUS2: TIMER0_RST Position */
+#define RGU_RESET_STATUS2_TIMER0_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER0_RST_Pos) /*!< RGU RESET_STATUS2: TIMER0_RST Mask */
+#define RGU_RESET_STATUS2_TIMER1_RST_Pos 2 /*!< RGU RESET_STATUS2: TIMER1_RST Position */
+#define RGU_RESET_STATUS2_TIMER1_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER1_RST_Pos) /*!< RGU RESET_STATUS2: TIMER1_RST Mask */
+#define RGU_RESET_STATUS2_TIMER2_RST_Pos 4 /*!< RGU RESET_STATUS2: TIMER2_RST Position */
+#define RGU_RESET_STATUS2_TIMER2_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER2_RST_Pos) /*!< RGU RESET_STATUS2: TIMER2_RST Mask */
+#define RGU_RESET_STATUS2_TIMER3_RST_Pos 6 /*!< RGU RESET_STATUS2: TIMER3_RST Position */
+#define RGU_RESET_STATUS2_TIMER3_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER3_RST_Pos) /*!< RGU RESET_STATUS2: TIMER3_RST Mask */
+#define RGU_RESET_STATUS2_RITIMER_RST_Pos 8 /*!< RGU RESET_STATUS2: RITIMER_RST Position */
+#define RGU_RESET_STATUS2_RITIMER_RST_Msk (0x03UL << RGU_RESET_STATUS2_RITIMER_RST_Pos) /*!< RGU RESET_STATUS2: RITIMER_RST Mask */
+#define RGU_RESET_STATUS2_SCT_RST_Pos 10 /*!< RGU RESET_STATUS2: SCT_RST Position */
+#define RGU_RESET_STATUS2_SCT_RST_Msk (0x03UL << RGU_RESET_STATUS2_SCT_RST_Pos) /*!< RGU RESET_STATUS2: SCT_RST Mask */
+#define RGU_RESET_STATUS2_MOTOCONPWM_RST_Pos 12 /*!< RGU RESET_STATUS2: MOTOCONPWM_RST Position */
+#define RGU_RESET_STATUS2_MOTOCONPWM_RST_Msk (0x03UL << RGU_RESET_STATUS2_MOTOCONPWM_RST_Pos) /*!< RGU RESET_STATUS2: MOTOCONPWM_RST Mask */
+#define RGU_RESET_STATUS2_QEI_RST_Pos 14 /*!< RGU RESET_STATUS2: QEI_RST Position */
+#define RGU_RESET_STATUS2_QEI_RST_Msk (0x03UL << RGU_RESET_STATUS2_QEI_RST_Pos) /*!< RGU RESET_STATUS2: QEI_RST Mask */
+#define RGU_RESET_STATUS2_ADC0_RST_Pos 16 /*!< RGU RESET_STATUS2: ADC0_RST Position */
+#define RGU_RESET_STATUS2_ADC0_RST_Msk (0x03UL << RGU_RESET_STATUS2_ADC0_RST_Pos) /*!< RGU RESET_STATUS2: ADC0_RST Mask */
+#define RGU_RESET_STATUS2_ADC1_RST_Pos 18 /*!< RGU RESET_STATUS2: ADC1_RST Position */
+#define RGU_RESET_STATUS2_ADC1_RST_Msk (0x03UL << RGU_RESET_STATUS2_ADC1_RST_Pos) /*!< RGU RESET_STATUS2: ADC1_RST Mask */
+#define RGU_RESET_STATUS2_DAC_RST_Pos 20 /*!< RGU RESET_STATUS2: DAC_RST Position */
+#define RGU_RESET_STATUS2_DAC_RST_Msk (0x03UL << RGU_RESET_STATUS2_DAC_RST_Pos) /*!< RGU RESET_STATUS2: DAC_RST Mask */
+#define RGU_RESET_STATUS2_UART0_RST_Pos 24 /*!< RGU RESET_STATUS2: UART0_RST Position */
+#define RGU_RESET_STATUS2_UART0_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART0_RST_Pos) /*!< RGU RESET_STATUS2: UART0_RST Mask */
+#define RGU_RESET_STATUS2_UART1_RST_Pos 26 /*!< RGU RESET_STATUS2: UART1_RST Position */
+#define RGU_RESET_STATUS2_UART1_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART1_RST_Pos) /*!< RGU RESET_STATUS2: UART1_RST Mask */
+#define RGU_RESET_STATUS2_UART2_RST_Pos 28 /*!< RGU RESET_STATUS2: UART2_RST Position */
+#define RGU_RESET_STATUS2_UART2_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART2_RST_Pos) /*!< RGU RESET_STATUS2: UART2_RST Mask */
+#define RGU_RESET_STATUS2_UART3_RST_Pos 30 /*!< RGU RESET_STATUS2: UART3_RST Position */
+#define RGU_RESET_STATUS2_UART3_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART3_RST_Pos) /*!< RGU RESET_STATUS2: UART3_RST Mask */
+
+// ------------------------------------ RGU_RESET_STATUS3 ---------------------------------------
+#define RGU_RESET_STATUS3_I2C0_RST_Pos 0 /*!< RGU RESET_STATUS3: I2C0_RST Position */
+#define RGU_RESET_STATUS3_I2C0_RST_Msk (0x03UL << RGU_RESET_STATUS3_I2C0_RST_Pos) /*!< RGU RESET_STATUS3: I2C0_RST Mask */
+#define RGU_RESET_STATUS3_I2C1_RST_Pos 2 /*!< RGU RESET_STATUS3: I2C1_RST Position */
+#define RGU_RESET_STATUS3_I2C1_RST_Msk (0x03UL << RGU_RESET_STATUS3_I2C1_RST_Pos) /*!< RGU RESET_STATUS3: I2C1_RST Mask */
+#define RGU_RESET_STATUS3_SSP0_RST_Pos 4 /*!< RGU RESET_STATUS3: SSP0_RST Position */
+#define RGU_RESET_STATUS3_SSP0_RST_Msk (0x03UL << RGU_RESET_STATUS3_SSP0_RST_Pos) /*!< RGU RESET_STATUS3: SSP0_RST Mask */
+#define RGU_RESET_STATUS3_SSP1_RST_Pos 6 /*!< RGU RESET_STATUS3: SSP1_RST Position */
+#define RGU_RESET_STATUS3_SSP1_RST_Msk (0x03UL << RGU_RESET_STATUS3_SSP1_RST_Pos) /*!< RGU RESET_STATUS3: SSP1_RST Mask */
+#define RGU_RESET_STATUS3_I2S_RST_Pos 8 /*!< RGU RESET_STATUS3: I2S_RST Position */
+#define RGU_RESET_STATUS3_I2S_RST_Msk (0x03UL << RGU_RESET_STATUS3_I2S_RST_Pos) /*!< RGU RESET_STATUS3: I2S_RST Mask */
+#define RGU_RESET_STATUS3_SPIFI_RST_Pos 10 /*!< RGU RESET_STATUS3: SPIFI_RST Position */
+#define RGU_RESET_STATUS3_SPIFI_RST_Msk (0x03UL << RGU_RESET_STATUS3_SPIFI_RST_Pos) /*!< RGU RESET_STATUS3: SPIFI_RST Mask */
+#define RGU_RESET_STATUS3_CAN1_RST_Pos 12 /*!< RGU RESET_STATUS3: CAN1_RST Position */
+#define RGU_RESET_STATUS3_CAN1_RST_Msk (0x03UL << RGU_RESET_STATUS3_CAN1_RST_Pos) /*!< RGU RESET_STATUS3: CAN1_RST Mask */
+#define RGU_RESET_STATUS3_CAN0_RST_Pos 14 /*!< RGU RESET_STATUS3: CAN0_RST Position */
+#define RGU_RESET_STATUS3_CAN0_RST_Msk (0x03UL << RGU_RESET_STATUS3_CAN0_RST_Pos) /*!< RGU RESET_STATUS3: CAN0_RST Mask */
+#define RGU_RESET_STATUS3_M0APP_RST_Pos 16 /*!< RGU RESET_STATUS3: M0APP_RST Position */
+#define RGU_RESET_STATUS3_M0APP_RST_Msk (0x03UL << RGU_RESET_STATUS3_M0APP_RST_Pos) /*!< RGU RESET_STATUS3: M0APP_RST Mask */
+#define RGU_RESET_STATUS3_SGPIO_RST_Pos 18 /*!< RGU RESET_STATUS3: SGPIO_RST Position */
+#define RGU_RESET_STATUS3_SGPIO_RST_Msk (0x03UL << RGU_RESET_STATUS3_SGPIO_RST_Pos) /*!< RGU RESET_STATUS3: SGPIO_RST Mask */
+#define RGU_RESET_STATUS3_SPI_RST_Pos 20 /*!< RGU RESET_STATUS3: SPI_RST Position */
+#define RGU_RESET_STATUS3_SPI_RST_Msk (0x03UL << RGU_RESET_STATUS3_SPI_RST_Pos) /*!< RGU RESET_STATUS3: SPI_RST Mask */
+
+// -------------------------------- RGU_RESET_ACTIVE_STATUS0 ------------------------------------
+#define RGU_RESET_ACTIVE_STATUS0_CORE_RST_Pos 0 /*!< RGU RESET_ACTIVE_STATUS0: CORE_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_CORE_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_CORE_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: CORE_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Pos 1 /*!< RGU RESET_ACTIVE_STATUS0: PERIPH_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: PERIPH_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Pos 2 /*!< RGU RESET_ACTIVE_STATUS0: MASTER_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: MASTER_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Pos 4 /*!< RGU RESET_ACTIVE_STATUS0: WWDT_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: WWDT_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_CREG_RST_Pos 5 /*!< RGU RESET_ACTIVE_STATUS0: CREG_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_CREG_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_CREG_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: CREG_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_BUS_RST_Pos 8 /*!< RGU RESET_ACTIVE_STATUS0: BUS_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_BUS_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_BUS_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: BUS_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_SCU_RST_Pos 9 /*!< RGU RESET_ACTIVE_STATUS0: SCU_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_SCU_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_SCU_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: SCU_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Pos 10 /*!< RGU RESET_ACTIVE_STATUS0: PINMUX_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: PINMUX_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_M3_RST_Pos 13 /*!< RGU RESET_ACTIVE_STATUS0: M3_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_M3_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_M3_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: M3_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_LCD_RST_Pos 16 /*!< RGU RESET_ACTIVE_STATUS0: LCD_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_LCD_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_LCD_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: LCD_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_USB0_RST_Pos 17 /*!< RGU RESET_ACTIVE_STATUS0: USB0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_USB0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_USB0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: USB0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_USB1_RST_Pos 18 /*!< RGU RESET_ACTIVE_STATUS0: USB1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_USB1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_USB1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: USB1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_DMA_RST_Pos 19 /*!< RGU RESET_ACTIVE_STATUS0: DMA_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_DMA_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_DMA_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: DMA_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Pos 20 /*!< RGU RESET_ACTIVE_STATUS0: SDIO_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: SDIO_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_EMC_RST_Pos 21 /*!< RGU RESET_ACTIVE_STATUS0: EMC_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_EMC_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_EMC_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: EMC_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Pos 22 /*!< RGU RESET_ACTIVE_STATUS0: ETHERNET_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: ETHERNET_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Pos 28 /*!< RGU RESET_ACTIVE_STATUS0: GPIO_RST Position */
+#define RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: GPIO_RST Mask */
+
+// -------------------------------- RGU_RESET_ACTIVE_STATUS1 ------------------------------------
+#define RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Pos 0 /*!< RGU RESET_ACTIVE_STATUS1: TIMER0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Pos 1 /*!< RGU RESET_ACTIVE_STATUS1: TIMER1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Pos 2 /*!< RGU RESET_ACTIVE_STATUS1: TIMER2_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER2_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Pos 3 /*!< RGU RESET_ACTIVE_STATUS1: TIMER3_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER3_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Pos 4 /*!< RGU RESET_ACTIVE_STATUS1: RITIMER_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: RITIMER_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_SCT_RST_Pos 5 /*!< RGU RESET_ACTIVE_STATUS1: SCT_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_SCT_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SCT_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SCT_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Pos 6 /*!< RGU RESET_ACTIVE_STATUS1: MOTOCONPWM_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: MOTOCONPWM_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_QEI_RST_Pos 7 /*!< RGU RESET_ACTIVE_STATUS1: QEI_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_QEI_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_QEI_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: QEI_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Pos 8 /*!< RGU RESET_ACTIVE_STATUS1: ADC0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: ADC0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Pos 9 /*!< RGU RESET_ACTIVE_STATUS1: ADC1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: ADC1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_DAC_RST_Pos 10 /*!< RGU RESET_ACTIVE_STATUS1: DAC_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_DAC_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_DAC_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: DAC_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_UART0_RST_Pos 12 /*!< RGU RESET_ACTIVE_STATUS1: UART0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_UART0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_UART1_RST_Pos 13 /*!< RGU RESET_ACTIVE_STATUS1: UART1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_UART1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_UART2_RST_Pos 14 /*!< RGU RESET_ACTIVE_STATUS1: UART2_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_UART2_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART2_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART2_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_UART3_RST_Pos 15 /*!< RGU RESET_ACTIVE_STATUS1: UART3_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_UART3_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART3_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART3_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Pos 16 /*!< RGU RESET_ACTIVE_STATUS1: I2C0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: I2C0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Pos 17 /*!< RGU RESET_ACTIVE_STATUS1: I2C1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: I2C1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Pos 18 /*!< RGU RESET_ACTIVE_STATUS1: SSP0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SSP0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Pos 19 /*!< RGU RESET_ACTIVE_STATUS1: SSP1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SSP1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_I2S_RST_Pos 20 /*!< RGU RESET_ACTIVE_STATUS1: I2S_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_I2S_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2S_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: I2S_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Pos 21 /*!< RGU RESET_ACTIVE_STATUS1: SPIFI_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SPIFI_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Pos 22 /*!< RGU RESET_ACTIVE_STATUS1: CAN1_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: CAN1_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Pos 23 /*!< RGU RESET_ACTIVE_STATUS1: CAN0_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: CAN0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_MOAPP_RST_Pos 24 /*!< RGU RESET_ACTIVE_STATUS1: MOAPP_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_MOAPP_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_MOAPP_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: MOAPP_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Pos 25 /*!< RGU RESET_ACTIVE_STATUS1: SGPIO_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SGPIO_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_SPI_RST_Pos 26 /*!< RGU RESET_ACTIVE_STATUS1: SPI_RST Position */
+#define RGU_RESET_ACTIVE_STATUS1_SPI_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SPI_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SPI_RST Mask */
+
+// ----------------------------------- RGU_RESET_EXT_STAT0 --------------------------------------
+#define RGU_RESET_EXT_STAT0_EXT_RESET_Pos 0 /*!< RGU RESET_EXT_STAT0: EXT_RESET Position */
+#define RGU_RESET_EXT_STAT0_EXT_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT0_EXT_RESET_Pos) /*!< RGU RESET_EXT_STAT0: EXT_RESET Mask */
+#define RGU_RESET_EXT_STAT0_BOD_RESET_Pos 4 /*!< RGU RESET_EXT_STAT0: BOD_RESET Position */
+#define RGU_RESET_EXT_STAT0_BOD_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT0_BOD_RESET_Pos) /*!< RGU RESET_EXT_STAT0: BOD_RESET Mask */
+#define RGU_RESET_EXT_STAT0_WWDT_RESET_Pos 5 /*!< RGU RESET_EXT_STAT0: WWDT_RESET Position */
+#define RGU_RESET_EXT_STAT0_WWDT_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT0_WWDT_RESET_Pos) /*!< RGU RESET_EXT_STAT0: WWDT_RESET Mask */
+
+// ----------------------------------- RGU_RESET_EXT_STAT1 --------------------------------------
+#define RGU_RESET_EXT_STAT1_CORE_RESET_Pos 1 /*!< RGU RESET_EXT_STAT1: CORE_RESET Position */
+#define RGU_RESET_EXT_STAT1_CORE_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT1_CORE_RESET_Pos) /*!< RGU RESET_EXT_STAT1: CORE_RESET Mask */
+
+// ----------------------------------- RGU_RESET_EXT_STAT2 --------------------------------------
+#define RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT2: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT2: PERIPHERAL_RESET Mask */
+
+// ----------------------------------- RGU_RESET_EXT_STAT4 --------------------------------------
+#define RGU_RESET_EXT_STAT4_CORE_RESET_Pos 1 /*!< RGU RESET_EXT_STAT4: CORE_RESET Position */
+#define RGU_RESET_EXT_STAT4_CORE_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT4_CORE_RESET_Pos) /*!< RGU RESET_EXT_STAT4: CORE_RESET Mask */
+
+// ----------------------------------- RGU_RESET_EXT_STAT5 --------------------------------------
+#define RGU_RESET_EXT_STAT5_CORE_RESET_Pos 1 /*!< RGU RESET_EXT_STAT5: CORE_RESET Position */
+#define RGU_RESET_EXT_STAT5_CORE_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT5_CORE_RESET_Pos) /*!< RGU RESET_EXT_STAT5: CORE_RESET Mask */
+
+// ----------------------------------- RGU_RESET_EXT_STAT8 --------------------------------------
+#define RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT8: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT8: PERIPHERAL_RESET Mask */
+
+// ----------------------------------- RGU_RESET_EXT_STAT9 --------------------------------------
+#define RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT9: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT9: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT13 --------------------------------------
+#define RGU_RESET_EXT_STAT13_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT13: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT13_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT13_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT13: MASTER_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT16 --------------------------------------
+#define RGU_RESET_EXT_STAT16_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT16: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT16_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT16_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT16: MASTER_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT17 --------------------------------------
+#define RGU_RESET_EXT_STAT17_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT17: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT17_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT17_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT17: MASTER_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT18 --------------------------------------
+#define RGU_RESET_EXT_STAT18_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT18: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT18_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT18_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT18: MASTER_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT19 --------------------------------------
+#define RGU_RESET_EXT_STAT19_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT19: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT19_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT19_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT19: MASTER_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT20 --------------------------------------
+#define RGU_RESET_EXT_STAT20_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT20: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT20_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT20_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT20: MASTER_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT21 --------------------------------------
+#define RGU_RESET_EXT_STAT21_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT21: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT21_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT21_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT21: MASTER_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT22 --------------------------------------
+#define RGU_RESET_EXT_STAT22_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT22: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT22_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT22_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT22: MASTER_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT23 --------------------------------------
+#define RGU_RESET_EXT_STAT23_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT23: MASTER_RESET Position */
+#define RGU_RESET_EXT_STAT23_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT23_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT23: MASTER_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT28 --------------------------------------
+#define RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT28: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT28: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT32 --------------------------------------
+#define RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT32: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT32: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT33 --------------------------------------
+#define RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT33: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT33: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT34 --------------------------------------
+#define RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT34: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT34: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT35 --------------------------------------
+#define RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT35: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT35: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT36 --------------------------------------
+#define RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT36: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT36: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT37 --------------------------------------
+#define RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT37: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT37: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT38 --------------------------------------
+#define RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT38: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT38: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT39 --------------------------------------
+#define RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT39: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT39: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT40 --------------------------------------
+#define RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT40: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT40: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT41 --------------------------------------
+#define RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT41: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT41: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT42 --------------------------------------
+#define RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT42: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT42: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT44 --------------------------------------
+#define RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT44: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT44: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT45 --------------------------------------
+#define RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT45: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT45: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT46 --------------------------------------
+#define RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT46: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT46: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT47 --------------------------------------
+#define RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT47: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT47: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT48 --------------------------------------
+#define RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT48: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT48: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT49 --------------------------------------
+#define RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT49: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT49: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT50 --------------------------------------
+#define RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT50: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT50: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT51 --------------------------------------
+#define RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT51: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT51: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT52 --------------------------------------
+#define RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT52: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT52: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT53 --------------------------------------
+#define RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT53: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT53: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT54 --------------------------------------
+#define RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT54: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT54: PERIPHERAL_RESET Mask */
+
+// ---------------------------------- RGU_RESET_EXT_STAT55 --------------------------------------
+#define RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT55: PERIPHERAL_RESET Position */
+#define RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT55: PERIPHERAL_RESET Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- WWDT Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------- WWDT_MOD --------------------------------------------
+#define WWDT_MOD_WDEN_Pos 0 /*!< WWDT MOD: WDEN Position */
+#define WWDT_MOD_WDEN_Msk (0x01UL << WWDT_MOD_WDEN_Pos) /*!< WWDT MOD: WDEN Mask */
+#define WWDT_MOD_WDRESET_Pos 1 /*!< WWDT MOD: WDRESET Position */
+#define WWDT_MOD_WDRESET_Msk (0x01UL << WWDT_MOD_WDRESET_Pos) /*!< WWDT MOD: WDRESET Mask */
+#define WWDT_MOD_WDTOF_Pos 2 /*!< WWDT MOD: WDTOF Position */
+#define WWDT_MOD_WDTOF_Msk (0x01UL << WWDT_MOD_WDTOF_Pos) /*!< WWDT MOD: WDTOF Mask */
+#define WWDT_MOD_WDINT_Pos 3 /*!< WWDT MOD: WDINT Position */
+#define WWDT_MOD_WDINT_Msk (0x01UL << WWDT_MOD_WDINT_Pos) /*!< WWDT MOD: WDINT Mask */
+#define WWDT_MOD_WDPROTECT_Pos 4 /*!< WWDT MOD: WDPROTECT Position */
+#define WWDT_MOD_WDPROTECT_Msk (0x01UL << WWDT_MOD_WDPROTECT_Pos) /*!< WWDT MOD: WDPROTECT Mask */
+
+// ----------------------------------------- WWDT_TC --------------------------------------------
+#define WWDT_TC_WDTC_Pos 0 /*!< WWDT TC: WDTC Position */
+#define WWDT_TC_WDTC_Msk (0x00ffffffUL << WWDT_TC_WDTC_Pos) /*!< WWDT TC: WDTC Mask */
+
+// ---------------------------------------- WWDT_FEED -------------------------------------------
+#define WWDT_FEED_Feed_Pos 0 /*!< WWDT FEED: Feed Position */
+#define WWDT_FEED_Feed_Msk (0x000000ffUL << WWDT_FEED_Feed_Pos) /*!< WWDT FEED: Feed Mask */
+
+// ----------------------------------------- WWDT_TV --------------------------------------------
+#define WWDT_TV_Count_Pos 0 /*!< WWDT TV: Count Position */
+#define WWDT_TV_Count_Msk (0x00ffffffUL << WWDT_TV_Count_Pos) /*!< WWDT TV: Count Mask */
+
+// -------------------------------------- WWDT_WARNINT ------------------------------------------
+#define WWDT_WARNINT_WDWARNINT_Pos 0 /*!< WWDT WARNINT: WDWARNINT Position */
+#define WWDT_WARNINT_WDWARNINT_Msk (0x000003ffUL << WWDT_WARNINT_WDWARNINT_Pos) /*!< WWDT WARNINT: WDWARNINT Mask */
+
+// --------------------------------------- WWDT_WINDOW ------------------------------------------
+#define WWDT_WINDOW_WDWINDOW_Pos 0 /*!< WWDT WINDOW: WDWINDOW Position */
+#define WWDT_WINDOW_WDWINDOW_Msk (0x00ffffffUL << WWDT_WINDOW_WDWINDOW_Pos) /*!< WWDT WINDOW: WDWINDOW Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USART0 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------- USART0_RBR -------------------------------------------
+#define USART0_RBR_RBR_Pos 0 /*!< USART0 RBR: RBR Position */
+#define USART0_RBR_RBR_Msk (0x000000ffUL << USART0_RBR_RBR_Pos) /*!< USART0 RBR: RBR Mask */
+
+// --------------------------------------- USART0_THR -------------------------------------------
+#define USART0_THR_THR_Pos 0 /*!< USART0 THR: THR Position */
+#define USART0_THR_THR_Msk (0x000000ffUL << USART0_THR_THR_Pos) /*!< USART0 THR: THR Mask */
+
+// --------------------------------------- USART0_DLL -------------------------------------------
+#define USART0_DLL_DLLSB_Pos 0 /*!< USART0 DLL: DLLSB Position */
+#define USART0_DLL_DLLSB_Msk (0x000000ffUL << USART0_DLL_DLLSB_Pos) /*!< USART0 DLL: DLLSB Mask */
+
+// --------------------------------------- USART0_DLM -------------------------------------------
+#define USART0_DLM_DLMSB_Pos 0 /*!< USART0 DLM: DLMSB Position */
+#define USART0_DLM_DLMSB_Msk (0x000000ffUL << USART0_DLM_DLMSB_Pos) /*!< USART0 DLM: DLMSB Mask */
+
+// --------------------------------------- USART0_IER -------------------------------------------
+#define USART0_IER_RBRIE_Pos 0 /*!< USART0 IER: RBRIE Position */
+#define USART0_IER_RBRIE_Msk (0x01UL << USART0_IER_RBRIE_Pos) /*!< USART0 IER: RBRIE Mask */
+#define USART0_IER_THREIE_Pos 1 /*!< USART0 IER: THREIE Position */
+#define USART0_IER_THREIE_Msk (0x01UL << USART0_IER_THREIE_Pos) /*!< USART0 IER: THREIE Mask */
+#define USART0_IER_RXIE_Pos 2 /*!< USART0 IER: RXIE Position */
+#define USART0_IER_RXIE_Msk (0x01UL << USART0_IER_RXIE_Pos) /*!< USART0 IER: RXIE Mask */
+#define USART0_IER_ABEOINTEN_Pos 8 /*!< USART0 IER: ABEOINTEN Position */
+#define USART0_IER_ABEOINTEN_Msk (0x01UL << USART0_IER_ABEOINTEN_Pos) /*!< USART0 IER: ABEOINTEN Mask */
+#define USART0_IER_ABTOINTEN_Pos 9 /*!< USART0 IER: ABTOINTEN Position */
+#define USART0_IER_ABTOINTEN_Msk (0x01UL << USART0_IER_ABTOINTEN_Pos) /*!< USART0 IER: ABTOINTEN Mask */
+
+// --------------------------------------- USART0_IIR -------------------------------------------
+#define USART0_IIR_INTSTATUS_Pos 0 /*!< USART0 IIR: INTSTATUS Position */
+#define USART0_IIR_INTSTATUS_Msk (0x01UL << USART0_IIR_INTSTATUS_Pos) /*!< USART0 IIR: INTSTATUS Mask */
+#define USART0_IIR_INTID_Pos 1 /*!< USART0 IIR: INTID Position */
+#define USART0_IIR_INTID_Msk (0x07UL << USART0_IIR_INTID_Pos) /*!< USART0 IIR: INTID Mask */
+#define USART0_IIR_FIFOENABLE_Pos 6 /*!< USART0 IIR: FIFOENABLE Position */
+#define USART0_IIR_FIFOENABLE_Msk (0x03UL << USART0_IIR_FIFOENABLE_Pos) /*!< USART0 IIR: FIFOENABLE Mask */
+#define USART0_IIR_ABEOINT_Pos 8 /*!< USART0 IIR: ABEOINT Position */
+#define USART0_IIR_ABEOINT_Msk (0x01UL << USART0_IIR_ABEOINT_Pos) /*!< USART0 IIR: ABEOINT Mask */
+#define USART0_IIR_ABTOINT_Pos 9 /*!< USART0 IIR: ABTOINT Position */
+#define USART0_IIR_ABTOINT_Msk (0x01UL << USART0_IIR_ABTOINT_Pos) /*!< USART0 IIR: ABTOINT Mask */
+
+// --------------------------------------- USART0_FCR -------------------------------------------
+#define USART0_FCR_FIFOEN_Pos 0 /*!< USART0 FCR: FIFOEN Position */
+#define USART0_FCR_FIFOEN_Msk (0x01UL << USART0_FCR_FIFOEN_Pos) /*!< USART0 FCR: FIFOEN Mask */
+#define USART0_FCR_RXFIFORES_Pos 1 /*!< USART0 FCR: RXFIFORES Position */
+#define USART0_FCR_RXFIFORES_Msk (0x01UL << USART0_FCR_RXFIFORES_Pos) /*!< USART0 FCR: RXFIFORES Mask */
+#define USART0_FCR_TXFIFORES_Pos 2 /*!< USART0 FCR: TXFIFORES Position */
+#define USART0_FCR_TXFIFORES_Msk (0x01UL << USART0_FCR_TXFIFORES_Pos) /*!< USART0 FCR: TXFIFORES Mask */
+#define USART0_FCR_DMAMODE_Pos 3 /*!< USART0 FCR: DMAMODE Position */
+#define USART0_FCR_DMAMODE_Msk (0x01UL << USART0_FCR_DMAMODE_Pos) /*!< USART0 FCR: DMAMODE Mask */
+#define USART0_FCR_RXTRIGLVL_Pos 6 /*!< USART0 FCR: RXTRIGLVL Position */
+#define USART0_FCR_RXTRIGLVL_Msk (0x03UL << USART0_FCR_RXTRIGLVL_Pos) /*!< USART0 FCR: RXTRIGLVL Mask */
+
+// --------------------------------------- USART0_LCR -------------------------------------------
+#define USART0_LCR_WLS_Pos 0 /*!< USART0 LCR: WLS Position */
+#define USART0_LCR_WLS_Msk (0x03UL << USART0_LCR_WLS_Pos) /*!< USART0 LCR: WLS Mask */
+#define USART0_LCR_SBS_Pos 2 /*!< USART0 LCR: SBS Position */
+#define USART0_LCR_SBS_Msk (0x01UL << USART0_LCR_SBS_Pos) /*!< USART0 LCR: SBS Mask */
+#define USART0_LCR_PE_Pos 3 /*!< USART0 LCR: PE Position */
+#define USART0_LCR_PE_Msk (0x01UL << USART0_LCR_PE_Pos) /*!< USART0 LCR: PE Mask */
+#define USART0_LCR_PS_Pos 4 /*!< USART0 LCR: PS Position */
+#define USART0_LCR_PS_Msk (0x03UL << USART0_LCR_PS_Pos) /*!< USART0 LCR: PS Mask */
+#define USART0_LCR_BC_Pos 6 /*!< USART0 LCR: BC Position */
+#define USART0_LCR_BC_Msk (0x01UL << USART0_LCR_BC_Pos) /*!< USART0 LCR: BC Mask */
+#define USART0_LCR_DLAB_Pos 7 /*!< USART0 LCR: DLAB Position */
+#define USART0_LCR_DLAB_Msk (0x01UL << USART0_LCR_DLAB_Pos) /*!< USART0 LCR: DLAB Mask */
+
+// --------------------------------------- USART0_LSR -------------------------------------------
+#define USART0_LSR_RDR_Pos 0 /*!< USART0 LSR: RDR Position */
+#define USART0_LSR_RDR_Msk (0x01UL << USART0_LSR_RDR_Pos) /*!< USART0 LSR: RDR Mask */
+#define USART0_LSR_OE_Pos 1 /*!< USART0 LSR: OE Position */
+#define USART0_LSR_OE_Msk (0x01UL << USART0_LSR_OE_Pos) /*!< USART0 LSR: OE Mask */
+#define USART0_LSR_PE_Pos 2 /*!< USART0 LSR: PE Position */
+#define USART0_LSR_PE_Msk (0x01UL << USART0_LSR_PE_Pos) /*!< USART0 LSR: PE Mask */
+#define USART0_LSR_FE_Pos 3 /*!< USART0 LSR: FE Position */
+#define USART0_LSR_FE_Msk (0x01UL << USART0_LSR_FE_Pos) /*!< USART0 LSR: FE Mask */
+#define USART0_LSR_BI_Pos 4 /*!< USART0 LSR: BI Position */
+#define USART0_LSR_BI_Msk (0x01UL << USART0_LSR_BI_Pos) /*!< USART0 LSR: BI Mask */
+#define USART0_LSR_THRE_Pos 5 /*!< USART0 LSR: THRE Position */
+#define USART0_LSR_THRE_Msk (0x01UL << USART0_LSR_THRE_Pos) /*!< USART0 LSR: THRE Mask */
+#define USART0_LSR_TEMT_Pos 6 /*!< USART0 LSR: TEMT Position */
+#define USART0_LSR_TEMT_Msk (0x01UL << USART0_LSR_TEMT_Pos) /*!< USART0 LSR: TEMT Mask */
+#define USART0_LSR_RXFE_Pos 7 /*!< USART0 LSR: RXFE Position */
+#define USART0_LSR_RXFE_Msk (0x01UL << USART0_LSR_RXFE_Pos) /*!< USART0 LSR: RXFE Mask */
+#define USART0_LSR_TXERR_Pos 8 /*!< USART0 LSR: TXERR Position */
+#define USART0_LSR_TXERR_Msk (0x01UL << USART0_LSR_TXERR_Pos) /*!< USART0 LSR: TXERR Mask */
+
+// --------------------------------------- USART0_SCR -------------------------------------------
+#define USART0_SCR_PAD_Pos 0 /*!< USART0 SCR: PAD Position */
+#define USART0_SCR_PAD_Msk (0x000000ffUL << USART0_SCR_PAD_Pos) /*!< USART0 SCR: PAD Mask */
+
+// --------------------------------------- USART0_ACR -------------------------------------------
+#define USART0_ACR_START_Pos 0 /*!< USART0 ACR: START Position */
+#define USART0_ACR_START_Msk (0x01UL << USART0_ACR_START_Pos) /*!< USART0 ACR: START Mask */
+#define USART0_ACR_MODE_Pos 1 /*!< USART0 ACR: MODE Position */
+#define USART0_ACR_MODE_Msk (0x01UL << USART0_ACR_MODE_Pos) /*!< USART0 ACR: MODE Mask */
+#define USART0_ACR_AUTORESTART_Pos 2 /*!< USART0 ACR: AUTORESTART Position */
+#define USART0_ACR_AUTORESTART_Msk (0x01UL << USART0_ACR_AUTORESTART_Pos) /*!< USART0 ACR: AUTORESTART Mask */
+#define USART0_ACR_ABEOINTCLR_Pos 8 /*!< USART0 ACR: ABEOINTCLR Position */
+#define USART0_ACR_ABEOINTCLR_Msk (0x01UL << USART0_ACR_ABEOINTCLR_Pos) /*!< USART0 ACR: ABEOINTCLR Mask */
+#define USART0_ACR_ABTOINTCLR_Pos 9 /*!< USART0 ACR: ABTOINTCLR Position */
+#define USART0_ACR_ABTOINTCLR_Msk (0x01UL << USART0_ACR_ABTOINTCLR_Pos) /*!< USART0 ACR: ABTOINTCLR Mask */
+
+// --------------------------------------- USART0_ICR -------------------------------------------
+#define USART0_ICR_IRDAEN_Pos 0 /*!< USART0 ICR: IRDAEN Position */
+#define USART0_ICR_IRDAEN_Msk (0x01UL << USART0_ICR_IRDAEN_Pos) /*!< USART0 ICR: IRDAEN Mask */
+#define USART0_ICR_IRDAINV_Pos 1 /*!< USART0 ICR: IRDAINV Position */
+#define USART0_ICR_IRDAINV_Msk (0x01UL << USART0_ICR_IRDAINV_Pos) /*!< USART0 ICR: IRDAINV Mask */
+#define USART0_ICR_FIXPULSEEN_Pos 2 /*!< USART0 ICR: FIXPULSEEN Position */
+#define USART0_ICR_FIXPULSEEN_Msk (0x01UL << USART0_ICR_FIXPULSEEN_Pos) /*!< USART0 ICR: FIXPULSEEN Mask */
+#define USART0_ICR_PULSEDIV_Pos 3 /*!< USART0 ICR: PULSEDIV Position */
+#define USART0_ICR_PULSEDIV_Msk (0x07UL << USART0_ICR_PULSEDIV_Pos) /*!< USART0 ICR: PULSEDIV Mask */
+
+// --------------------------------------- USART0_FDR -------------------------------------------
+#define USART0_FDR_DIVADDVAL_Pos 0 /*!< USART0 FDR: DIVADDVAL Position */
+#define USART0_FDR_DIVADDVAL_Msk (0x0fUL << USART0_FDR_DIVADDVAL_Pos) /*!< USART0 FDR: DIVADDVAL Mask */
+#define USART0_FDR_MULVAL_Pos 4 /*!< USART0 FDR: MULVAL Position */
+#define USART0_FDR_MULVAL_Msk (0x0fUL << USART0_FDR_MULVAL_Pos) /*!< USART0 FDR: MULVAL Mask */
+
+// --------------------------------------- USART0_OSR -------------------------------------------
+#define USART0_OSR_OSFRAC_Pos 1 /*!< USART0 OSR: OSFRAC Position */
+#define USART0_OSR_OSFRAC_Msk (0x07UL << USART0_OSR_OSFRAC_Pos) /*!< USART0 OSR: OSFRAC Mask */
+#define USART0_OSR_OSINT_Pos 4 /*!< USART0 OSR: OSINT Position */
+#define USART0_OSR_OSINT_Msk (0x0fUL << USART0_OSR_OSINT_Pos) /*!< USART0 OSR: OSINT Mask */
+#define USART0_OSR_FDINT_Pos 8 /*!< USART0 OSR: FDINT Position */
+#define USART0_OSR_FDINT_Msk (0x7fUL << USART0_OSR_FDINT_Pos) /*!< USART0 OSR: FDINT Mask */
+
+// --------------------------------------- USART0_HDEN ------------------------------------------
+#define USART0_HDEN_HDEN_Pos 0 /*!< USART0 HDEN: HDEN Position */
+#define USART0_HDEN_HDEN_Msk (0x01UL << USART0_HDEN_HDEN_Pos) /*!< USART0 HDEN: HDEN Mask */
+
+// ------------------------------------- USART0_SCICTRL -----------------------------------------
+#define USART0_SCICTRL_SCIEN_Pos 0 /*!< USART0 SCICTRL: SCIEN Position */
+#define USART0_SCICTRL_SCIEN_Msk (0x01UL << USART0_SCICTRL_SCIEN_Pos) /*!< USART0 SCICTRL: SCIEN Mask */
+#define USART0_SCICTRL_NACKDIS_Pos 1 /*!< USART0 SCICTRL: NACKDIS Position */
+#define USART0_SCICTRL_NACKDIS_Msk (0x01UL << USART0_SCICTRL_NACKDIS_Pos) /*!< USART0 SCICTRL: NACKDIS Mask */
+#define USART0_SCICTRL_PROTSEL_Pos 2 /*!< USART0 SCICTRL: PROTSEL Position */
+#define USART0_SCICTRL_PROTSEL_Msk (0x01UL << USART0_SCICTRL_PROTSEL_Pos) /*!< USART0 SCICTRL: PROTSEL Mask */
+#define USART0_SCICTRL_TXRETRY_Pos 5 /*!< USART0 SCICTRL: TXRETRY Position */
+#define USART0_SCICTRL_TXRETRY_Msk (0x07UL << USART0_SCICTRL_TXRETRY_Pos) /*!< USART0 SCICTRL: TXRETRY Mask */
+#define USART0_SCICTRL_GUARDTIME_Pos 8 /*!< USART0 SCICTRL: GUARDTIME Position */
+#define USART0_SCICTRL_GUARDTIME_Msk (0x000000ffUL << USART0_SCICTRL_GUARDTIME_Pos) /*!< USART0 SCICTRL: GUARDTIME Mask */
+
+// ------------------------------------ USART0_RS485CTRL ----------------------------------------
+#define USART0_RS485CTRL_NMMEN_Pos 0 /*!< USART0 RS485CTRL: NMMEN Position */
+#define USART0_RS485CTRL_NMMEN_Msk (0x01UL << USART0_RS485CTRL_NMMEN_Pos) /*!< USART0 RS485CTRL: NMMEN Mask */
+#define USART0_RS485CTRL_RXDIS_Pos 1 /*!< USART0 RS485CTRL: RXDIS Position */
+#define USART0_RS485CTRL_RXDIS_Msk (0x01UL << USART0_RS485CTRL_RXDIS_Pos) /*!< USART0 RS485CTRL: RXDIS Mask */
+#define USART0_RS485CTRL_AADEN_Pos 2 /*!< USART0 RS485CTRL: AADEN Position */
+#define USART0_RS485CTRL_AADEN_Msk (0x01UL << USART0_RS485CTRL_AADEN_Pos) /*!< USART0 RS485CTRL: AADEN Mask */
+#define USART0_RS485CTRL_DCTRL_Pos 4 /*!< USART0 RS485CTRL: DCTRL Position */
+#define USART0_RS485CTRL_DCTRL_Msk (0x01UL << USART0_RS485CTRL_DCTRL_Pos) /*!< USART0 RS485CTRL: DCTRL Mask */
+#define USART0_RS485CTRL_OINV_Pos 5 /*!< USART0 RS485CTRL: OINV Position */
+#define USART0_RS485CTRL_OINV_Msk (0x01UL << USART0_RS485CTRL_OINV_Pos) /*!< USART0 RS485CTRL: OINV Mask */
+
+// ---------------------------------- USART0_RS485ADRMATCH --------------------------------------
+#define USART0_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< USART0 RS485ADRMATCH: ADRMATCH Position */
+#define USART0_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << USART0_RS485ADRMATCH_ADRMATCH_Pos) /*!< USART0 RS485ADRMATCH: ADRMATCH Mask */
+
+// ------------------------------------- USART0_RS485DLY ----------------------------------------
+#define USART0_RS485DLY_DLY_Pos 0 /*!< USART0 RS485DLY: DLY Position */
+#define USART0_RS485DLY_DLY_Msk (0x000000ffUL << USART0_RS485DLY_DLY_Pos) /*!< USART0 RS485DLY: DLY Mask */
+
+// ------------------------------------- USART0_SYNCCTRL ----------------------------------------
+#define USART0_SYNCCTRL_SYNC_Pos 0 /*!< USART0 SYNCCTRL: SYNC Position */
+#define USART0_SYNCCTRL_SYNC_Msk (0x01UL << USART0_SYNCCTRL_SYNC_Pos) /*!< USART0 SYNCCTRL: SYNC Mask */
+#define USART0_SYNCCTRL_CSRC_Pos 1 /*!< USART0 SYNCCTRL: CSRC Position */
+#define USART0_SYNCCTRL_CSRC_Msk (0x01UL << USART0_SYNCCTRL_CSRC_Pos) /*!< USART0 SYNCCTRL: CSRC Mask */
+#define USART0_SYNCCTRL_FES_Pos 2 /*!< USART0 SYNCCTRL: FES Position */
+#define USART0_SYNCCTRL_FES_Msk (0x01UL << USART0_SYNCCTRL_FES_Pos) /*!< USART0 SYNCCTRL: FES Mask */
+#define USART0_SYNCCTRL_TSBYPASS_Pos 3 /*!< USART0 SYNCCTRL: TSBYPASS Position */
+#define USART0_SYNCCTRL_TSBYPASS_Msk (0x01UL << USART0_SYNCCTRL_TSBYPASS_Pos) /*!< USART0 SYNCCTRL: TSBYPASS Mask */
+#define USART0_SYNCCTRL_CSCEN_Pos 4 /*!< USART0 SYNCCTRL: CSCEN Position */
+#define USART0_SYNCCTRL_CSCEN_Msk (0x01UL << USART0_SYNCCTRL_CSCEN_Pos) /*!< USART0 SYNCCTRL: CSCEN Mask */
+#define USART0_SYNCCTRL_SSSDIS_Pos 5 /*!< USART0 SYNCCTRL: SSSDIS Position */
+#define USART0_SYNCCTRL_SSSDIS_Msk (0x01UL << USART0_SYNCCTRL_SSSDIS_Pos) /*!< USART0 SYNCCTRL: SSSDIS Mask */
+#define USART0_SYNCCTRL_CCCLR_Pos 6 /*!< USART0 SYNCCTRL: CCCLR Position */
+#define USART0_SYNCCTRL_CCCLR_Msk (0x01UL << USART0_SYNCCTRL_CCCLR_Pos) /*!< USART0 SYNCCTRL: CCCLR Mask */
+
+// --------------------------------------- USART0_TER -------------------------------------------
+#define USART0_TER_TXEN_Pos 0 /*!< USART0 TER: TXEN Position */
+#define USART0_TER_TXEN_Msk (0x01UL << USART0_TER_TXEN_Pos) /*!< USART0 TER: TXEN Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USART2 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------- USART2_DLL -------------------------------------------
+#define USART2_DLL_DLLSB_Pos 0 /*!< USART2 DLL: DLLSB Position */
+#define USART2_DLL_DLLSB_Msk (0x000000ffUL << USART2_DLL_DLLSB_Pos) /*!< USART2 DLL: DLLSB Mask */
+
+// --------------------------------------- USART2_THR -------------------------------------------
+#define USART2_THR_THR_Pos 0 /*!< USART2 THR: THR Position */
+#define USART2_THR_THR_Msk (0x000000ffUL << USART2_THR_THR_Pos) /*!< USART2 THR: THR Mask */
+
+// --------------------------------------- USART2_RBR -------------------------------------------
+#define USART2_RBR_RBR_Pos 0 /*!< USART2 RBR: RBR Position */
+#define USART2_RBR_RBR_Msk (0x000000ffUL << USART2_RBR_RBR_Pos) /*!< USART2 RBR: RBR Mask */
+
+// --------------------------------------- USART2_IER -------------------------------------------
+#define USART2_IER_RBRIE_Pos 0 /*!< USART2 IER: RBRIE Position */
+#define USART2_IER_RBRIE_Msk (0x01UL << USART2_IER_RBRIE_Pos) /*!< USART2 IER: RBRIE Mask */
+#define USART2_IER_THREIE_Pos 1 /*!< USART2 IER: THREIE Position */
+#define USART2_IER_THREIE_Msk (0x01UL << USART2_IER_THREIE_Pos) /*!< USART2 IER: THREIE Mask */
+#define USART2_IER_RXIE_Pos 2 /*!< USART2 IER: RXIE Position */
+#define USART2_IER_RXIE_Msk (0x01UL << USART2_IER_RXIE_Pos) /*!< USART2 IER: RXIE Mask */
+#define USART2_IER_ABEOINTEN_Pos 8 /*!< USART2 IER: ABEOINTEN Position */
+#define USART2_IER_ABEOINTEN_Msk (0x01UL << USART2_IER_ABEOINTEN_Pos) /*!< USART2 IER: ABEOINTEN Mask */
+#define USART2_IER_ABTOINTEN_Pos 9 /*!< USART2 IER: ABTOINTEN Position */
+#define USART2_IER_ABTOINTEN_Msk (0x01UL << USART2_IER_ABTOINTEN_Pos) /*!< USART2 IER: ABTOINTEN Mask */
+
+// --------------------------------------- USART2_DLM -------------------------------------------
+#define USART2_DLM_DLMSB_Pos 0 /*!< USART2 DLM: DLMSB Position */
+#define USART2_DLM_DLMSB_Msk (0x000000ffUL << USART2_DLM_DLMSB_Pos) /*!< USART2 DLM: DLMSB Mask */
+
+// --------------------------------------- USART2_FCR -------------------------------------------
+#define USART2_FCR_FIFOEN_Pos 0 /*!< USART2 FCR: FIFOEN Position */
+#define USART2_FCR_FIFOEN_Msk (0x01UL << USART2_FCR_FIFOEN_Pos) /*!< USART2 FCR: FIFOEN Mask */
+#define USART2_FCR_RXFIFORES_Pos 1 /*!< USART2 FCR: RXFIFORES Position */
+#define USART2_FCR_RXFIFORES_Msk (0x01UL << USART2_FCR_RXFIFORES_Pos) /*!< USART2 FCR: RXFIFORES Mask */
+#define USART2_FCR_TXFIFORES_Pos 2 /*!< USART2 FCR: TXFIFORES Position */
+#define USART2_FCR_TXFIFORES_Msk (0x01UL << USART2_FCR_TXFIFORES_Pos) /*!< USART2 FCR: TXFIFORES Mask */
+#define USART2_FCR_DMAMODE_Pos 3 /*!< USART2 FCR: DMAMODE Position */
+#define USART2_FCR_DMAMODE_Msk (0x01UL << USART2_FCR_DMAMODE_Pos) /*!< USART2 FCR: DMAMODE Mask */
+#define USART2_FCR_RXTRIGLVL_Pos 6 /*!< USART2 FCR: RXTRIGLVL Position */
+#define USART2_FCR_RXTRIGLVL_Msk (0x03UL << USART2_FCR_RXTRIGLVL_Pos) /*!< USART2 FCR: RXTRIGLVL Mask */
+
+// --------------------------------------- USART2_IIR -------------------------------------------
+#define USART2_IIR_INTSTATUS_Pos 0 /*!< USART2 IIR: INTSTATUS Position */
+#define USART2_IIR_INTSTATUS_Msk (0x01UL << USART2_IIR_INTSTATUS_Pos) /*!< USART2 IIR: INTSTATUS Mask */
+#define USART2_IIR_INTID_Pos 1 /*!< USART2 IIR: INTID Position */
+#define USART2_IIR_INTID_Msk (0x07UL << USART2_IIR_INTID_Pos) /*!< USART2 IIR: INTID Mask */
+#define USART2_IIR_FIFOENABLE_Pos 6 /*!< USART2 IIR: FIFOENABLE Position */
+#define USART2_IIR_FIFOENABLE_Msk (0x03UL << USART2_IIR_FIFOENABLE_Pos) /*!< USART2 IIR: FIFOENABLE Mask */
+#define USART2_IIR_ABEOINT_Pos 8 /*!< USART2 IIR: ABEOINT Position */
+#define USART2_IIR_ABEOINT_Msk (0x01UL << USART2_IIR_ABEOINT_Pos) /*!< USART2 IIR: ABEOINT Mask */
+#define USART2_IIR_ABTOINT_Pos 9 /*!< USART2 IIR: ABTOINT Position */
+#define USART2_IIR_ABTOINT_Msk (0x01UL << USART2_IIR_ABTOINT_Pos) /*!< USART2 IIR: ABTOINT Mask */
+
+// --------------------------------------- USART2_LCR -------------------------------------------
+#define USART2_LCR_WLS_Pos 0 /*!< USART2 LCR: WLS Position */
+#define USART2_LCR_WLS_Msk (0x03UL << USART2_LCR_WLS_Pos) /*!< USART2 LCR: WLS Mask */
+#define USART2_LCR_SBS_Pos 2 /*!< USART2 LCR: SBS Position */
+#define USART2_LCR_SBS_Msk (0x01UL << USART2_LCR_SBS_Pos) /*!< USART2 LCR: SBS Mask */
+#define USART2_LCR_PE_Pos 3 /*!< USART2 LCR: PE Position */
+#define USART2_LCR_PE_Msk (0x01UL << USART2_LCR_PE_Pos) /*!< USART2 LCR: PE Mask */
+#define USART2_LCR_PS_Pos 4 /*!< USART2 LCR: PS Position */
+#define USART2_LCR_PS_Msk (0x03UL << USART2_LCR_PS_Pos) /*!< USART2 LCR: PS Mask */
+#define USART2_LCR_BC_Pos 6 /*!< USART2 LCR: BC Position */
+#define USART2_LCR_BC_Msk (0x01UL << USART2_LCR_BC_Pos) /*!< USART2 LCR: BC Mask */
+#define USART2_LCR_DLAB_Pos 7 /*!< USART2 LCR: DLAB Position */
+#define USART2_LCR_DLAB_Msk (0x01UL << USART2_LCR_DLAB_Pos) /*!< USART2 LCR: DLAB Mask */
+
+// --------------------------------------- USART2_LSR -------------------------------------------
+#define USART2_LSR_RDR_Pos 0 /*!< USART2 LSR: RDR Position */
+#define USART2_LSR_RDR_Msk (0x01UL << USART2_LSR_RDR_Pos) /*!< USART2 LSR: RDR Mask */
+#define USART2_LSR_OE_Pos 1 /*!< USART2 LSR: OE Position */
+#define USART2_LSR_OE_Msk (0x01UL << USART2_LSR_OE_Pos) /*!< USART2 LSR: OE Mask */
+#define USART2_LSR_PE_Pos 2 /*!< USART2 LSR: PE Position */
+#define USART2_LSR_PE_Msk (0x01UL << USART2_LSR_PE_Pos) /*!< USART2 LSR: PE Mask */
+#define USART2_LSR_FE_Pos 3 /*!< USART2 LSR: FE Position */
+#define USART2_LSR_FE_Msk (0x01UL << USART2_LSR_FE_Pos) /*!< USART2 LSR: FE Mask */
+#define USART2_LSR_BI_Pos 4 /*!< USART2 LSR: BI Position */
+#define USART2_LSR_BI_Msk (0x01UL << USART2_LSR_BI_Pos) /*!< USART2 LSR: BI Mask */
+#define USART2_LSR_THRE_Pos 5 /*!< USART2 LSR: THRE Position */
+#define USART2_LSR_THRE_Msk (0x01UL << USART2_LSR_THRE_Pos) /*!< USART2 LSR: THRE Mask */
+#define USART2_LSR_TEMT_Pos 6 /*!< USART2 LSR: TEMT Position */
+#define USART2_LSR_TEMT_Msk (0x01UL << USART2_LSR_TEMT_Pos) /*!< USART2 LSR: TEMT Mask */
+#define USART2_LSR_RXFE_Pos 7 /*!< USART2 LSR: RXFE Position */
+#define USART2_LSR_RXFE_Msk (0x01UL << USART2_LSR_RXFE_Pos) /*!< USART2 LSR: RXFE Mask */
+#define USART2_LSR_TXERR_Pos 8 /*!< USART2 LSR: TXERR Position */
+#define USART2_LSR_TXERR_Msk (0x01UL << USART2_LSR_TXERR_Pos) /*!< USART2 LSR: TXERR Mask */
+
+// --------------------------------------- USART2_SCR -------------------------------------------
+#define USART2_SCR_PAD_Pos 0 /*!< USART2 SCR: PAD Position */
+#define USART2_SCR_PAD_Msk (0x000000ffUL << USART2_SCR_PAD_Pos) /*!< USART2 SCR: PAD Mask */
+
+// --------------------------------------- USART2_ACR -------------------------------------------
+#define USART2_ACR_START_Pos 0 /*!< USART2 ACR: START Position */
+#define USART2_ACR_START_Msk (0x01UL << USART2_ACR_START_Pos) /*!< USART2 ACR: START Mask */
+#define USART2_ACR_MODE_Pos 1 /*!< USART2 ACR: MODE Position */
+#define USART2_ACR_MODE_Msk (0x01UL << USART2_ACR_MODE_Pos) /*!< USART2 ACR: MODE Mask */
+#define USART2_ACR_AUTORESTART_Pos 2 /*!< USART2 ACR: AUTORESTART Position */
+#define USART2_ACR_AUTORESTART_Msk (0x01UL << USART2_ACR_AUTORESTART_Pos) /*!< USART2 ACR: AUTORESTART Mask */
+#define USART2_ACR_ABEOINTCLR_Pos 8 /*!< USART2 ACR: ABEOINTCLR Position */
+#define USART2_ACR_ABEOINTCLR_Msk (0x01UL << USART2_ACR_ABEOINTCLR_Pos) /*!< USART2 ACR: ABEOINTCLR Mask */
+#define USART2_ACR_ABTOINTCLR_Pos 9 /*!< USART2 ACR: ABTOINTCLR Position */
+#define USART2_ACR_ABTOINTCLR_Msk (0x01UL << USART2_ACR_ABTOINTCLR_Pos) /*!< USART2 ACR: ABTOINTCLR Mask */
+
+// --------------------------------------- USART2_ICR -------------------------------------------
+#define USART2_ICR_IRDAEN_Pos 0 /*!< USART2 ICR: IRDAEN Position */
+#define USART2_ICR_IRDAEN_Msk (0x01UL << USART2_ICR_IRDAEN_Pos) /*!< USART2 ICR: IRDAEN Mask */
+#define USART2_ICR_IRDAINV_Pos 1 /*!< USART2 ICR: IRDAINV Position */
+#define USART2_ICR_IRDAINV_Msk (0x01UL << USART2_ICR_IRDAINV_Pos) /*!< USART2 ICR: IRDAINV Mask */
+#define USART2_ICR_FIXPULSEEN_Pos 2 /*!< USART2 ICR: FIXPULSEEN Position */
+#define USART2_ICR_FIXPULSEEN_Msk (0x01UL << USART2_ICR_FIXPULSEEN_Pos) /*!< USART2 ICR: FIXPULSEEN Mask */
+#define USART2_ICR_PULSEDIV_Pos 3 /*!< USART2 ICR: PULSEDIV Position */
+#define USART2_ICR_PULSEDIV_Msk (0x07UL << USART2_ICR_PULSEDIV_Pos) /*!< USART2 ICR: PULSEDIV Mask */
+
+// --------------------------------------- USART2_FDR -------------------------------------------
+#define USART2_FDR_DIVADDVAL_Pos 0 /*!< USART2 FDR: DIVADDVAL Position */
+#define USART2_FDR_DIVADDVAL_Msk (0x0fUL << USART2_FDR_DIVADDVAL_Pos) /*!< USART2 FDR: DIVADDVAL Mask */
+#define USART2_FDR_MULVAL_Pos 4 /*!< USART2 FDR: MULVAL Position */
+#define USART2_FDR_MULVAL_Msk (0x0fUL << USART2_FDR_MULVAL_Pos) /*!< USART2 FDR: MULVAL Mask */
+
+// --------------------------------------- USART2_OSR -------------------------------------------
+#define USART2_OSR_OSFRAC_Pos 1 /*!< USART2 OSR: OSFRAC Position */
+#define USART2_OSR_OSFRAC_Msk (0x07UL << USART2_OSR_OSFRAC_Pos) /*!< USART2 OSR: OSFRAC Mask */
+#define USART2_OSR_OSINT_Pos 4 /*!< USART2 OSR: OSINT Position */
+#define USART2_OSR_OSINT_Msk (0x0fUL << USART2_OSR_OSINT_Pos) /*!< USART2 OSR: OSINT Mask */
+#define USART2_OSR_FDINT_Pos 8 /*!< USART2 OSR: FDINT Position */
+#define USART2_OSR_FDINT_Msk (0x7fUL << USART2_OSR_FDINT_Pos) /*!< USART2 OSR: FDINT Mask */
+
+// --------------------------------------- USART2_HDEN ------------------------------------------
+#define USART2_HDEN_HDEN_Pos 0 /*!< USART2 HDEN: HDEN Position */
+#define USART2_HDEN_HDEN_Msk (0x01UL << USART2_HDEN_HDEN_Pos) /*!< USART2 HDEN: HDEN Mask */
+
+// ------------------------------------- USART2_SCICTRL -----------------------------------------
+#define USART2_SCICTRL_SCIEN_Pos 0 /*!< USART2 SCICTRL: SCIEN Position */
+#define USART2_SCICTRL_SCIEN_Msk (0x01UL << USART2_SCICTRL_SCIEN_Pos) /*!< USART2 SCICTRL: SCIEN Mask */
+#define USART2_SCICTRL_NACKDIS_Pos 1 /*!< USART2 SCICTRL: NACKDIS Position */
+#define USART2_SCICTRL_NACKDIS_Msk (0x01UL << USART2_SCICTRL_NACKDIS_Pos) /*!< USART2 SCICTRL: NACKDIS Mask */
+#define USART2_SCICTRL_PROTSEL_Pos 2 /*!< USART2 SCICTRL: PROTSEL Position */
+#define USART2_SCICTRL_PROTSEL_Msk (0x01UL << USART2_SCICTRL_PROTSEL_Pos) /*!< USART2 SCICTRL: PROTSEL Mask */
+#define USART2_SCICTRL_TXRETRY_Pos 5 /*!< USART2 SCICTRL: TXRETRY Position */
+#define USART2_SCICTRL_TXRETRY_Msk (0x07UL << USART2_SCICTRL_TXRETRY_Pos) /*!< USART2 SCICTRL: TXRETRY Mask */
+#define USART2_SCICTRL_GUARDTIME_Pos 8 /*!< USART2 SCICTRL: GUARDTIME Position */
+#define USART2_SCICTRL_GUARDTIME_Msk (0x000000ffUL << USART2_SCICTRL_GUARDTIME_Pos) /*!< USART2 SCICTRL: GUARDTIME Mask */
+
+// ------------------------------------ USART2_RS485CTRL ----------------------------------------
+#define USART2_RS485CTRL_NMMEN_Pos 0 /*!< USART2 RS485CTRL: NMMEN Position */
+#define USART2_RS485CTRL_NMMEN_Msk (0x01UL << USART2_RS485CTRL_NMMEN_Pos) /*!< USART2 RS485CTRL: NMMEN Mask */
+#define USART2_RS485CTRL_RXDIS_Pos 1 /*!< USART2 RS485CTRL: RXDIS Position */
+#define USART2_RS485CTRL_RXDIS_Msk (0x01UL << USART2_RS485CTRL_RXDIS_Pos) /*!< USART2 RS485CTRL: RXDIS Mask */
+#define USART2_RS485CTRL_AADEN_Pos 2 /*!< USART2 RS485CTRL: AADEN Position */
+#define USART2_RS485CTRL_AADEN_Msk (0x01UL << USART2_RS485CTRL_AADEN_Pos) /*!< USART2 RS485CTRL: AADEN Mask */
+#define USART2_RS485CTRL_DCTRL_Pos 4 /*!< USART2 RS485CTRL: DCTRL Position */
+#define USART2_RS485CTRL_DCTRL_Msk (0x01UL << USART2_RS485CTRL_DCTRL_Pos) /*!< USART2 RS485CTRL: DCTRL Mask */
+#define USART2_RS485CTRL_OINV_Pos 5 /*!< USART2 RS485CTRL: OINV Position */
+#define USART2_RS485CTRL_OINV_Msk (0x01UL << USART2_RS485CTRL_OINV_Pos) /*!< USART2 RS485CTRL: OINV Mask */
+
+// ---------------------------------- USART2_RS485ADRMATCH --------------------------------------
+#define USART2_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< USART2 RS485ADRMATCH: ADRMATCH Position */
+#define USART2_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << USART2_RS485ADRMATCH_ADRMATCH_Pos) /*!< USART2 RS485ADRMATCH: ADRMATCH Mask */
+
+// ------------------------------------- USART2_RS485DLY ----------------------------------------
+#define USART2_RS485DLY_DLY_Pos 0 /*!< USART2 RS485DLY: DLY Position */
+#define USART2_RS485DLY_DLY_Msk (0x000000ffUL << USART2_RS485DLY_DLY_Pos) /*!< USART2 RS485DLY: DLY Mask */
+
+// ------------------------------------- USART2_SYNCCTRL ----------------------------------------
+#define USART2_SYNCCTRL_SYNC_Pos 0 /*!< USART2 SYNCCTRL: SYNC Position */
+#define USART2_SYNCCTRL_SYNC_Msk (0x01UL << USART2_SYNCCTRL_SYNC_Pos) /*!< USART2 SYNCCTRL: SYNC Mask */
+#define USART2_SYNCCTRL_CSRC_Pos 1 /*!< USART2 SYNCCTRL: CSRC Position */
+#define USART2_SYNCCTRL_CSRC_Msk (0x01UL << USART2_SYNCCTRL_CSRC_Pos) /*!< USART2 SYNCCTRL: CSRC Mask */
+#define USART2_SYNCCTRL_FES_Pos 2 /*!< USART2 SYNCCTRL: FES Position */
+#define USART2_SYNCCTRL_FES_Msk (0x01UL << USART2_SYNCCTRL_FES_Pos) /*!< USART2 SYNCCTRL: FES Mask */
+#define USART2_SYNCCTRL_TSBYPASS_Pos 3 /*!< USART2 SYNCCTRL: TSBYPASS Position */
+#define USART2_SYNCCTRL_TSBYPASS_Msk (0x01UL << USART2_SYNCCTRL_TSBYPASS_Pos) /*!< USART2 SYNCCTRL: TSBYPASS Mask */
+#define USART2_SYNCCTRL_CSCEN_Pos 4 /*!< USART2 SYNCCTRL: CSCEN Position */
+#define USART2_SYNCCTRL_CSCEN_Msk (0x01UL << USART2_SYNCCTRL_CSCEN_Pos) /*!< USART2 SYNCCTRL: CSCEN Mask */
+#define USART2_SYNCCTRL_SSSDIS_Pos 5 /*!< USART2 SYNCCTRL: SSSDIS Position */
+#define USART2_SYNCCTRL_SSSDIS_Msk (0x01UL << USART2_SYNCCTRL_SSSDIS_Pos) /*!< USART2 SYNCCTRL: SSSDIS Mask */
+#define USART2_SYNCCTRL_CCCLR_Pos 6 /*!< USART2 SYNCCTRL: CCCLR Position */
+#define USART2_SYNCCTRL_CCCLR_Msk (0x01UL << USART2_SYNCCTRL_CCCLR_Pos) /*!< USART2 SYNCCTRL: CCCLR Mask */
+
+// --------------------------------------- USART2_TER -------------------------------------------
+#define USART2_TER_TXEN_Pos 0 /*!< USART2 TER: TXEN Position */
+#define USART2_TER_TXEN_Msk (0x01UL << USART2_TER_TXEN_Pos) /*!< USART2 TER: TXEN Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USART3 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------- USART3_DLL -------------------------------------------
+#define USART3_DLL_DLLSB_Pos 0 /*!< USART3 DLL: DLLSB Position */
+#define USART3_DLL_DLLSB_Msk (0x000000ffUL << USART3_DLL_DLLSB_Pos) /*!< USART3 DLL: DLLSB Mask */
+
+// --------------------------------------- USART3_THR -------------------------------------------
+#define USART3_THR_THR_Pos 0 /*!< USART3 THR: THR Position */
+#define USART3_THR_THR_Msk (0x000000ffUL << USART3_THR_THR_Pos) /*!< USART3 THR: THR Mask */
+
+// --------------------------------------- USART3_RBR -------------------------------------------
+#define USART3_RBR_RBR_Pos 0 /*!< USART3 RBR: RBR Position */
+#define USART3_RBR_RBR_Msk (0x000000ffUL << USART3_RBR_RBR_Pos) /*!< USART3 RBR: RBR Mask */
+
+// --------------------------------------- USART3_IER -------------------------------------------
+#define USART3_IER_RBRIE_Pos 0 /*!< USART3 IER: RBRIE Position */
+#define USART3_IER_RBRIE_Msk (0x01UL << USART3_IER_RBRIE_Pos) /*!< USART3 IER: RBRIE Mask */
+#define USART3_IER_THREIE_Pos 1 /*!< USART3 IER: THREIE Position */
+#define USART3_IER_THREIE_Msk (0x01UL << USART3_IER_THREIE_Pos) /*!< USART3 IER: THREIE Mask */
+#define USART3_IER_RXIE_Pos 2 /*!< USART3 IER: RXIE Position */
+#define USART3_IER_RXIE_Msk (0x01UL << USART3_IER_RXIE_Pos) /*!< USART3 IER: RXIE Mask */
+#define USART3_IER_ABEOINTEN_Pos 8 /*!< USART3 IER: ABEOINTEN Position */
+#define USART3_IER_ABEOINTEN_Msk (0x01UL << USART3_IER_ABEOINTEN_Pos) /*!< USART3 IER: ABEOINTEN Mask */
+#define USART3_IER_ABTOINTEN_Pos 9 /*!< USART3 IER: ABTOINTEN Position */
+#define USART3_IER_ABTOINTEN_Msk (0x01UL << USART3_IER_ABTOINTEN_Pos) /*!< USART3 IER: ABTOINTEN Mask */
+
+// --------------------------------------- USART3_DLM -------------------------------------------
+#define USART3_DLM_DLMSB_Pos 0 /*!< USART3 DLM: DLMSB Position */
+#define USART3_DLM_DLMSB_Msk (0x000000ffUL << USART3_DLM_DLMSB_Pos) /*!< USART3 DLM: DLMSB Mask */
+
+// --------------------------------------- USART3_FCR -------------------------------------------
+#define USART3_FCR_FIFOEN_Pos 0 /*!< USART3 FCR: FIFOEN Position */
+#define USART3_FCR_FIFOEN_Msk (0x01UL << USART3_FCR_FIFOEN_Pos) /*!< USART3 FCR: FIFOEN Mask */
+#define USART3_FCR_RXFIFORES_Pos 1 /*!< USART3 FCR: RXFIFORES Position */
+#define USART3_FCR_RXFIFORES_Msk (0x01UL << USART3_FCR_RXFIFORES_Pos) /*!< USART3 FCR: RXFIFORES Mask */
+#define USART3_FCR_TXFIFORES_Pos 2 /*!< USART3 FCR: TXFIFORES Position */
+#define USART3_FCR_TXFIFORES_Msk (0x01UL << USART3_FCR_TXFIFORES_Pos) /*!< USART3 FCR: TXFIFORES Mask */
+#define USART3_FCR_DMAMODE_Pos 3 /*!< USART3 FCR: DMAMODE Position */
+#define USART3_FCR_DMAMODE_Msk (0x01UL << USART3_FCR_DMAMODE_Pos) /*!< USART3 FCR: DMAMODE Mask */
+#define USART3_FCR_RXTRIGLVL_Pos 6 /*!< USART3 FCR: RXTRIGLVL Position */
+#define USART3_FCR_RXTRIGLVL_Msk (0x03UL << USART3_FCR_RXTRIGLVL_Pos) /*!< USART3 FCR: RXTRIGLVL Mask */
+
+// --------------------------------------- USART3_IIR -------------------------------------------
+#define USART3_IIR_INTSTATUS_Pos 0 /*!< USART3 IIR: INTSTATUS Position */
+#define USART3_IIR_INTSTATUS_Msk (0x01UL << USART3_IIR_INTSTATUS_Pos) /*!< USART3 IIR: INTSTATUS Mask */
+#define USART3_IIR_INTID_Pos 1 /*!< USART3 IIR: INTID Position */
+#define USART3_IIR_INTID_Msk (0x07UL << USART3_IIR_INTID_Pos) /*!< USART3 IIR: INTID Mask */
+#define USART3_IIR_FIFOENABLE_Pos 6 /*!< USART3 IIR: FIFOENABLE Position */
+#define USART3_IIR_FIFOENABLE_Msk (0x03UL << USART3_IIR_FIFOENABLE_Pos) /*!< USART3 IIR: FIFOENABLE Mask */
+#define USART3_IIR_ABEOINT_Pos 8 /*!< USART3 IIR: ABEOINT Position */
+#define USART3_IIR_ABEOINT_Msk (0x01UL << USART3_IIR_ABEOINT_Pos) /*!< USART3 IIR: ABEOINT Mask */
+#define USART3_IIR_ABTOINT_Pos 9 /*!< USART3 IIR: ABTOINT Position */
+#define USART3_IIR_ABTOINT_Msk (0x01UL << USART3_IIR_ABTOINT_Pos) /*!< USART3 IIR: ABTOINT Mask */
+
+// --------------------------------------- USART3_LCR -------------------------------------------
+#define USART3_LCR_WLS_Pos 0 /*!< USART3 LCR: WLS Position */
+#define USART3_LCR_WLS_Msk (0x03UL << USART3_LCR_WLS_Pos) /*!< USART3 LCR: WLS Mask */
+#define USART3_LCR_SBS_Pos 2 /*!< USART3 LCR: SBS Position */
+#define USART3_LCR_SBS_Msk (0x01UL << USART3_LCR_SBS_Pos) /*!< USART3 LCR: SBS Mask */
+#define USART3_LCR_PE_Pos 3 /*!< USART3 LCR: PE Position */
+#define USART3_LCR_PE_Msk (0x01UL << USART3_LCR_PE_Pos) /*!< USART3 LCR: PE Mask */
+#define USART3_LCR_PS_Pos 4 /*!< USART3 LCR: PS Position */
+#define USART3_LCR_PS_Msk (0x03UL << USART3_LCR_PS_Pos) /*!< USART3 LCR: PS Mask */
+#define USART3_LCR_BC_Pos 6 /*!< USART3 LCR: BC Position */
+#define USART3_LCR_BC_Msk (0x01UL << USART3_LCR_BC_Pos) /*!< USART3 LCR: BC Mask */
+#define USART3_LCR_DLAB_Pos 7 /*!< USART3 LCR: DLAB Position */
+#define USART3_LCR_DLAB_Msk (0x01UL << USART3_LCR_DLAB_Pos) /*!< USART3 LCR: DLAB Mask */
+
+// --------------------------------------- USART3_LSR -------------------------------------------
+#define USART3_LSR_RDR_Pos 0 /*!< USART3 LSR: RDR Position */
+#define USART3_LSR_RDR_Msk (0x01UL << USART3_LSR_RDR_Pos) /*!< USART3 LSR: RDR Mask */
+#define USART3_LSR_OE_Pos 1 /*!< USART3 LSR: OE Position */
+#define USART3_LSR_OE_Msk (0x01UL << USART3_LSR_OE_Pos) /*!< USART3 LSR: OE Mask */
+#define USART3_LSR_PE_Pos 2 /*!< USART3 LSR: PE Position */
+#define USART3_LSR_PE_Msk (0x01UL << USART3_LSR_PE_Pos) /*!< USART3 LSR: PE Mask */
+#define USART3_LSR_FE_Pos 3 /*!< USART3 LSR: FE Position */
+#define USART3_LSR_FE_Msk (0x01UL << USART3_LSR_FE_Pos) /*!< USART3 LSR: FE Mask */
+#define USART3_LSR_BI_Pos 4 /*!< USART3 LSR: BI Position */
+#define USART3_LSR_BI_Msk (0x01UL << USART3_LSR_BI_Pos) /*!< USART3 LSR: BI Mask */
+#define USART3_LSR_THRE_Pos 5 /*!< USART3 LSR: THRE Position */
+#define USART3_LSR_THRE_Msk (0x01UL << USART3_LSR_THRE_Pos) /*!< USART3 LSR: THRE Mask */
+#define USART3_LSR_TEMT_Pos 6 /*!< USART3 LSR: TEMT Position */
+#define USART3_LSR_TEMT_Msk (0x01UL << USART3_LSR_TEMT_Pos) /*!< USART3 LSR: TEMT Mask */
+#define USART3_LSR_RXFE_Pos 7 /*!< USART3 LSR: RXFE Position */
+#define USART3_LSR_RXFE_Msk (0x01UL << USART3_LSR_RXFE_Pos) /*!< USART3 LSR: RXFE Mask */
+#define USART3_LSR_TXERR_Pos 8 /*!< USART3 LSR: TXERR Position */
+#define USART3_LSR_TXERR_Msk (0x01UL << USART3_LSR_TXERR_Pos) /*!< USART3 LSR: TXERR Mask */
+
+// --------------------------------------- USART3_SCR -------------------------------------------
+#define USART3_SCR_PAD_Pos 0 /*!< USART3 SCR: PAD Position */
+#define USART3_SCR_PAD_Msk (0x000000ffUL << USART3_SCR_PAD_Pos) /*!< USART3 SCR: PAD Mask */
+
+// --------------------------------------- USART3_ACR -------------------------------------------
+#define USART3_ACR_START_Pos 0 /*!< USART3 ACR: START Position */
+#define USART3_ACR_START_Msk (0x01UL << USART3_ACR_START_Pos) /*!< USART3 ACR: START Mask */
+#define USART3_ACR_MODE_Pos 1 /*!< USART3 ACR: MODE Position */
+#define USART3_ACR_MODE_Msk (0x01UL << USART3_ACR_MODE_Pos) /*!< USART3 ACR: MODE Mask */
+#define USART3_ACR_AUTORESTART_Pos 2 /*!< USART3 ACR: AUTORESTART Position */
+#define USART3_ACR_AUTORESTART_Msk (0x01UL << USART3_ACR_AUTORESTART_Pos) /*!< USART3 ACR: AUTORESTART Mask */
+#define USART3_ACR_ABEOINTCLR_Pos 8 /*!< USART3 ACR: ABEOINTCLR Position */
+#define USART3_ACR_ABEOINTCLR_Msk (0x01UL << USART3_ACR_ABEOINTCLR_Pos) /*!< USART3 ACR: ABEOINTCLR Mask */
+#define USART3_ACR_ABTOINTCLR_Pos 9 /*!< USART3 ACR: ABTOINTCLR Position */
+#define USART3_ACR_ABTOINTCLR_Msk (0x01UL << USART3_ACR_ABTOINTCLR_Pos) /*!< USART3 ACR: ABTOINTCLR Mask */
+
+// --------------------------------------- USART3_ICR -------------------------------------------
+#define USART3_ICR_IRDAEN_Pos 0 /*!< USART3 ICR: IRDAEN Position */
+#define USART3_ICR_IRDAEN_Msk (0x01UL << USART3_ICR_IRDAEN_Pos) /*!< USART3 ICR: IRDAEN Mask */
+#define USART3_ICR_IRDAINV_Pos 1 /*!< USART3 ICR: IRDAINV Position */
+#define USART3_ICR_IRDAINV_Msk (0x01UL << USART3_ICR_IRDAINV_Pos) /*!< USART3 ICR: IRDAINV Mask */
+#define USART3_ICR_FIXPULSEEN_Pos 2 /*!< USART3 ICR: FIXPULSEEN Position */
+#define USART3_ICR_FIXPULSEEN_Msk (0x01UL << USART3_ICR_FIXPULSEEN_Pos) /*!< USART3 ICR: FIXPULSEEN Mask */
+#define USART3_ICR_PULSEDIV_Pos 3 /*!< USART3 ICR: PULSEDIV Position */
+#define USART3_ICR_PULSEDIV_Msk (0x07UL << USART3_ICR_PULSEDIV_Pos) /*!< USART3 ICR: PULSEDIV Mask */
+
+// --------------------------------------- USART3_FDR -------------------------------------------
+#define USART3_FDR_DIVADDVAL_Pos 0 /*!< USART3 FDR: DIVADDVAL Position */
+#define USART3_FDR_DIVADDVAL_Msk (0x0fUL << USART3_FDR_DIVADDVAL_Pos) /*!< USART3 FDR: DIVADDVAL Mask */
+#define USART3_FDR_MULVAL_Pos 4 /*!< USART3 FDR: MULVAL Position */
+#define USART3_FDR_MULVAL_Msk (0x0fUL << USART3_FDR_MULVAL_Pos) /*!< USART3 FDR: MULVAL Mask */
+
+// --------------------------------------- USART3_OSR -------------------------------------------
+#define USART3_OSR_OSFRAC_Pos 1 /*!< USART3 OSR: OSFRAC Position */
+#define USART3_OSR_OSFRAC_Msk (0x07UL << USART3_OSR_OSFRAC_Pos) /*!< USART3 OSR: OSFRAC Mask */
+#define USART3_OSR_OSINT_Pos 4 /*!< USART3 OSR: OSINT Position */
+#define USART3_OSR_OSINT_Msk (0x0fUL << USART3_OSR_OSINT_Pos) /*!< USART3 OSR: OSINT Mask */
+#define USART3_OSR_FDINT_Pos 8 /*!< USART3 OSR: FDINT Position */
+#define USART3_OSR_FDINT_Msk (0x7fUL << USART3_OSR_FDINT_Pos) /*!< USART3 OSR: FDINT Mask */
+
+// --------------------------------------- USART3_HDEN ------------------------------------------
+#define USART3_HDEN_HDEN_Pos 0 /*!< USART3 HDEN: HDEN Position */
+#define USART3_HDEN_HDEN_Msk (0x01UL << USART3_HDEN_HDEN_Pos) /*!< USART3 HDEN: HDEN Mask */
+
+// ------------------------------------- USART3_SCICTRL -----------------------------------------
+#define USART3_SCICTRL_SCIEN_Pos 0 /*!< USART3 SCICTRL: SCIEN Position */
+#define USART3_SCICTRL_SCIEN_Msk (0x01UL << USART3_SCICTRL_SCIEN_Pos) /*!< USART3 SCICTRL: SCIEN Mask */
+#define USART3_SCICTRL_NACKDIS_Pos 1 /*!< USART3 SCICTRL: NACKDIS Position */
+#define USART3_SCICTRL_NACKDIS_Msk (0x01UL << USART3_SCICTRL_NACKDIS_Pos) /*!< USART3 SCICTRL: NACKDIS Mask */
+#define USART3_SCICTRL_PROTSEL_Pos 2 /*!< USART3 SCICTRL: PROTSEL Position */
+#define USART3_SCICTRL_PROTSEL_Msk (0x01UL << USART3_SCICTRL_PROTSEL_Pos) /*!< USART3 SCICTRL: PROTSEL Mask */
+#define USART3_SCICTRL_TXRETRY_Pos 5 /*!< USART3 SCICTRL: TXRETRY Position */
+#define USART3_SCICTRL_TXRETRY_Msk (0x07UL << USART3_SCICTRL_TXRETRY_Pos) /*!< USART3 SCICTRL: TXRETRY Mask */
+#define USART3_SCICTRL_GUARDTIME_Pos 8 /*!< USART3 SCICTRL: GUARDTIME Position */
+#define USART3_SCICTRL_GUARDTIME_Msk (0x000000ffUL << USART3_SCICTRL_GUARDTIME_Pos) /*!< USART3 SCICTRL: GUARDTIME Mask */
+
+// ------------------------------------ USART3_RS485CTRL ----------------------------------------
+#define USART3_RS485CTRL_NMMEN_Pos 0 /*!< USART3 RS485CTRL: NMMEN Position */
+#define USART3_RS485CTRL_NMMEN_Msk (0x01UL << USART3_RS485CTRL_NMMEN_Pos) /*!< USART3 RS485CTRL: NMMEN Mask */
+#define USART3_RS485CTRL_RXDIS_Pos 1 /*!< USART3 RS485CTRL: RXDIS Position */
+#define USART3_RS485CTRL_RXDIS_Msk (0x01UL << USART3_RS485CTRL_RXDIS_Pos) /*!< USART3 RS485CTRL: RXDIS Mask */
+#define USART3_RS485CTRL_AADEN_Pos 2 /*!< USART3 RS485CTRL: AADEN Position */
+#define USART3_RS485CTRL_AADEN_Msk (0x01UL << USART3_RS485CTRL_AADEN_Pos) /*!< USART3 RS485CTRL: AADEN Mask */
+#define USART3_RS485CTRL_DCTRL_Pos 4 /*!< USART3 RS485CTRL: DCTRL Position */
+#define USART3_RS485CTRL_DCTRL_Msk (0x01UL << USART3_RS485CTRL_DCTRL_Pos) /*!< USART3 RS485CTRL: DCTRL Mask */
+#define USART3_RS485CTRL_OINV_Pos 5 /*!< USART3 RS485CTRL: OINV Position */
+#define USART3_RS485CTRL_OINV_Msk (0x01UL << USART3_RS485CTRL_OINV_Pos) /*!< USART3 RS485CTRL: OINV Mask */
+
+// ---------------------------------- USART3_RS485ADRMATCH --------------------------------------
+#define USART3_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< USART3 RS485ADRMATCH: ADRMATCH Position */
+#define USART3_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << USART3_RS485ADRMATCH_ADRMATCH_Pos) /*!< USART3 RS485ADRMATCH: ADRMATCH Mask */
+
+// ------------------------------------- USART3_RS485DLY ----------------------------------------
+#define USART3_RS485DLY_DLY_Pos 0 /*!< USART3 RS485DLY: DLY Position */
+#define USART3_RS485DLY_DLY_Msk (0x000000ffUL << USART3_RS485DLY_DLY_Pos) /*!< USART3 RS485DLY: DLY Mask */
+
+// ------------------------------------- USART3_SYNCCTRL ----------------------------------------
+#define USART3_SYNCCTRL_SYNC_Pos 0 /*!< USART3 SYNCCTRL: SYNC Position */
+#define USART3_SYNCCTRL_SYNC_Msk (0x01UL << USART3_SYNCCTRL_SYNC_Pos) /*!< USART3 SYNCCTRL: SYNC Mask */
+#define USART3_SYNCCTRL_CSRC_Pos 1 /*!< USART3 SYNCCTRL: CSRC Position */
+#define USART3_SYNCCTRL_CSRC_Msk (0x01UL << USART3_SYNCCTRL_CSRC_Pos) /*!< USART3 SYNCCTRL: CSRC Mask */
+#define USART3_SYNCCTRL_FES_Pos 2 /*!< USART3 SYNCCTRL: FES Position */
+#define USART3_SYNCCTRL_FES_Msk (0x01UL << USART3_SYNCCTRL_FES_Pos) /*!< USART3 SYNCCTRL: FES Mask */
+#define USART3_SYNCCTRL_TSBYPASS_Pos 3 /*!< USART3 SYNCCTRL: TSBYPASS Position */
+#define USART3_SYNCCTRL_TSBYPASS_Msk (0x01UL << USART3_SYNCCTRL_TSBYPASS_Pos) /*!< USART3 SYNCCTRL: TSBYPASS Mask */
+#define USART3_SYNCCTRL_CSCEN_Pos 4 /*!< USART3 SYNCCTRL: CSCEN Position */
+#define USART3_SYNCCTRL_CSCEN_Msk (0x01UL << USART3_SYNCCTRL_CSCEN_Pos) /*!< USART3 SYNCCTRL: CSCEN Mask */
+#define USART3_SYNCCTRL_SSSDIS_Pos 5 /*!< USART3 SYNCCTRL: SSSDIS Position */
+#define USART3_SYNCCTRL_SSSDIS_Msk (0x01UL << USART3_SYNCCTRL_SSSDIS_Pos) /*!< USART3 SYNCCTRL: SSSDIS Mask */
+#define USART3_SYNCCTRL_CCCLR_Pos 6 /*!< USART3 SYNCCTRL: CCCLR Position */
+#define USART3_SYNCCTRL_CCCLR_Msk (0x01UL << USART3_SYNCCTRL_CCCLR_Pos) /*!< USART3 SYNCCTRL: CCCLR Mask */
+
+// --------------------------------------- USART3_TER -------------------------------------------
+#define USART3_TER_TXEN_Pos 0 /*!< USART3 TER: TXEN Position */
+#define USART3_TER_TXEN_Msk (0x01UL << USART3_TER_TXEN_Pos) /*!< USART3 TER: TXEN Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- UART1 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------- UART1_RBR -------------------------------------------
+#define UART1_RBR_RBR_Pos 0 /*!< UART1 RBR: RBR Position */
+#define UART1_RBR_RBR_Msk (0x000000ffUL << UART1_RBR_RBR_Pos) /*!< UART1 RBR: RBR Mask */
+
+// ---------------------------------------- UART1_THR -------------------------------------------
+#define UART1_THR_THR_Pos 0 /*!< UART1 THR: THR Position */
+#define UART1_THR_THR_Msk (0x000000ffUL << UART1_THR_THR_Pos) /*!< UART1 THR: THR Mask */
+
+// ---------------------------------------- UART1_DLL -------------------------------------------
+#define UART1_DLL_DLLSB_Pos 0 /*!< UART1 DLL: DLLSB Position */
+#define UART1_DLL_DLLSB_Msk (0x000000ffUL << UART1_DLL_DLLSB_Pos) /*!< UART1 DLL: DLLSB Mask */
+
+// ---------------------------------------- UART1_DLM -------------------------------------------
+#define UART1_DLM_DLMSB_Pos 0 /*!< UART1 DLM: DLMSB Position */
+#define UART1_DLM_DLMSB_Msk (0x000000ffUL << UART1_DLM_DLMSB_Pos) /*!< UART1 DLM: DLMSB Mask */
+
+// ---------------------------------------- UART1_IER -------------------------------------------
+#define UART1_IER_RBRIE_Pos 0 /*!< UART1 IER: RBRIE Position */
+#define UART1_IER_RBRIE_Msk (0x01UL << UART1_IER_RBRIE_Pos) /*!< UART1 IER: RBRIE Mask */
+#define UART1_IER_THREIE_Pos 1 /*!< UART1 IER: THREIE Position */
+#define UART1_IER_THREIE_Msk (0x01UL << UART1_IER_THREIE_Pos) /*!< UART1 IER: THREIE Mask */
+#define UART1_IER_RXIE_Pos 2 /*!< UART1 IER: RXIE Position */
+#define UART1_IER_RXIE_Msk (0x01UL << UART1_IER_RXIE_Pos) /*!< UART1 IER: RXIE Mask */
+#define UART1_IER_MSIE_Pos 3 /*!< UART1 IER: MSIE Position */
+#define UART1_IER_MSIE_Msk (0x01UL << UART1_IER_MSIE_Pos) /*!< UART1 IER: MSIE Mask */
+#define UART1_IER_CTSIE_Pos 7 /*!< UART1 IER: CTSIE Position */
+#define UART1_IER_CTSIE_Msk (0x01UL << UART1_IER_CTSIE_Pos) /*!< UART1 IER: CTSIE Mask */
+#define UART1_IER_ABEOIE_Pos 8 /*!< UART1 IER: ABEOIE Position */
+#define UART1_IER_ABEOIE_Msk (0x01UL << UART1_IER_ABEOIE_Pos) /*!< UART1 IER: ABEOIE Mask */
+#define UART1_IER_ABTOIE_Pos 9 /*!< UART1 IER: ABTOIE Position */
+#define UART1_IER_ABTOIE_Msk (0x01UL << UART1_IER_ABTOIE_Pos) /*!< UART1 IER: ABTOIE Mask */
+
+// ---------------------------------------- UART1_IIR -------------------------------------------
+#define UART1_IIR_INTSTATUS_Pos 0 /*!< UART1 IIR: INTSTATUS Position */
+#define UART1_IIR_INTSTATUS_Msk (0x01UL << UART1_IIR_INTSTATUS_Pos) /*!< UART1 IIR: INTSTATUS Mask */
+#define UART1_IIR_INTID_Pos 1 /*!< UART1 IIR: INTID Position */
+#define UART1_IIR_INTID_Msk (0x07UL << UART1_IIR_INTID_Pos) /*!< UART1 IIR: INTID Mask */
+#define UART1_IIR_FIFOENABLE_Pos 6 /*!< UART1 IIR: FIFOENABLE Position */
+#define UART1_IIR_FIFOENABLE_Msk (0x03UL << UART1_IIR_FIFOENABLE_Pos) /*!< UART1 IIR: FIFOENABLE Mask */
+#define UART1_IIR_ABEOINT_Pos 8 /*!< UART1 IIR: ABEOINT Position */
+#define UART1_IIR_ABEOINT_Msk (0x01UL << UART1_IIR_ABEOINT_Pos) /*!< UART1 IIR: ABEOINT Mask */
+#define UART1_IIR_ABTOINT_Pos 9 /*!< UART1 IIR: ABTOINT Position */
+#define UART1_IIR_ABTOINT_Msk (0x01UL << UART1_IIR_ABTOINT_Pos) /*!< UART1 IIR: ABTOINT Mask */
+
+// ---------------------------------------- UART1_FCR -------------------------------------------
+#define UART1_FCR_FIFOEN_Pos 0 /*!< UART1 FCR: FIFOEN Position */
+#define UART1_FCR_FIFOEN_Msk (0x01UL << UART1_FCR_FIFOEN_Pos) /*!< UART1 FCR: FIFOEN Mask */
+#define UART1_FCR_RXFIFORES_Pos 1 /*!< UART1 FCR: RXFIFORES Position */
+#define UART1_FCR_RXFIFORES_Msk (0x01UL << UART1_FCR_RXFIFORES_Pos) /*!< UART1 FCR: RXFIFORES Mask */
+#define UART1_FCR_TXFIFORES_Pos 2 /*!< UART1 FCR: TXFIFORES Position */
+#define UART1_FCR_TXFIFORES_Msk (0x01UL << UART1_FCR_TXFIFORES_Pos) /*!< UART1 FCR: TXFIFORES Mask */
+#define UART1_FCR_DMAMODE_Pos 3 /*!< UART1 FCR: DMAMODE Position */
+#define UART1_FCR_DMAMODE_Msk (0x01UL << UART1_FCR_DMAMODE_Pos) /*!< UART1 FCR: DMAMODE Mask */
+#define UART1_FCR_RXTRIGLVL_Pos 6 /*!< UART1 FCR: RXTRIGLVL Position */
+#define UART1_FCR_RXTRIGLVL_Msk (0x03UL << UART1_FCR_RXTRIGLVL_Pos) /*!< UART1 FCR: RXTRIGLVL Mask */
+
+// ---------------------------------------- UART1_LCR -------------------------------------------
+#define UART1_LCR_WLS_Pos 0 /*!< UART1 LCR: WLS Position */
+#define UART1_LCR_WLS_Msk (0x03UL << UART1_LCR_WLS_Pos) /*!< UART1 LCR: WLS Mask */
+#define UART1_LCR_SBS_Pos 2 /*!< UART1 LCR: SBS Position */
+#define UART1_LCR_SBS_Msk (0x01UL << UART1_LCR_SBS_Pos) /*!< UART1 LCR: SBS Mask */
+#define UART1_LCR_PE_Pos 3 /*!< UART1 LCR: PE Position */
+#define UART1_LCR_PE_Msk (0x01UL << UART1_LCR_PE_Pos) /*!< UART1 LCR: PE Mask */
+#define UART1_LCR_PS_Pos 4 /*!< UART1 LCR: PS Position */
+#define UART1_LCR_PS_Msk (0x03UL << UART1_LCR_PS_Pos) /*!< UART1 LCR: PS Mask */
+#define UART1_LCR_BC_Pos 6 /*!< UART1 LCR: BC Position */
+#define UART1_LCR_BC_Msk (0x01UL << UART1_LCR_BC_Pos) /*!< UART1 LCR: BC Mask */
+#define UART1_LCR_DLAB_Pos 7 /*!< UART1 LCR: DLAB Position */
+#define UART1_LCR_DLAB_Msk (0x01UL << UART1_LCR_DLAB_Pos) /*!< UART1 LCR: DLAB Mask */
+
+// ---------------------------------------- UART1_MCR -------------------------------------------
+#define UART1_MCR_DTRCTRL_Pos 0 /*!< UART1 MCR: DTRCTRL Position */
+#define UART1_MCR_DTRCTRL_Msk (0x01UL << UART1_MCR_DTRCTRL_Pos) /*!< UART1 MCR: DTRCTRL Mask */
+#define UART1_MCR_RTSCTRL_Pos 1 /*!< UART1 MCR: RTSCTRL Position */
+#define UART1_MCR_RTSCTRL_Msk (0x01UL << UART1_MCR_RTSCTRL_Pos) /*!< UART1 MCR: RTSCTRL Mask */
+#define UART1_MCR_LMS_Pos 4 /*!< UART1 MCR: LMS Position */
+#define UART1_MCR_LMS_Msk (0x01UL << UART1_MCR_LMS_Pos) /*!< UART1 MCR: LMS Mask */
+#define UART1_MCR_RTSEN_Pos 6 /*!< UART1 MCR: RTSEN Position */
+#define UART1_MCR_RTSEN_Msk (0x01UL << UART1_MCR_RTSEN_Pos) /*!< UART1 MCR: RTSEN Mask */
+#define UART1_MCR_CTSEN_Pos 7 /*!< UART1 MCR: CTSEN Position */
+#define UART1_MCR_CTSEN_Msk (0x01UL << UART1_MCR_CTSEN_Pos) /*!< UART1 MCR: CTSEN Mask */
+
+// ---------------------------------------- UART1_LSR -------------------------------------------
+#define UART1_LSR_RDR_Pos 0 /*!< UART1 LSR: RDR Position */
+#define UART1_LSR_RDR_Msk (0x01UL << UART1_LSR_RDR_Pos) /*!< UART1 LSR: RDR Mask */
+#define UART1_LSR_OE_Pos 1 /*!< UART1 LSR: OE Position */
+#define UART1_LSR_OE_Msk (0x01UL << UART1_LSR_OE_Pos) /*!< UART1 LSR: OE Mask */
+#define UART1_LSR_PE_Pos 2 /*!< UART1 LSR: PE Position */
+#define UART1_LSR_PE_Msk (0x01UL << UART1_LSR_PE_Pos) /*!< UART1 LSR: PE Mask */
+#define UART1_LSR_FE_Pos 3 /*!< UART1 LSR: FE Position */
+#define UART1_LSR_FE_Msk (0x01UL << UART1_LSR_FE_Pos) /*!< UART1 LSR: FE Mask */
+#define UART1_LSR_BI_Pos 4 /*!< UART1 LSR: BI Position */
+#define UART1_LSR_BI_Msk (0x01UL << UART1_LSR_BI_Pos) /*!< UART1 LSR: BI Mask */
+#define UART1_LSR_THRE_Pos 5 /*!< UART1 LSR: THRE Position */
+#define UART1_LSR_THRE_Msk (0x01UL << UART1_LSR_THRE_Pos) /*!< UART1 LSR: THRE Mask */
+#define UART1_LSR_TEMT_Pos 6 /*!< UART1 LSR: TEMT Position */
+#define UART1_LSR_TEMT_Msk (0x01UL << UART1_LSR_TEMT_Pos) /*!< UART1 LSR: TEMT Mask */
+#define UART1_LSR_RXFE_Pos 7 /*!< UART1 LSR: RXFE Position */
+#define UART1_LSR_RXFE_Msk (0x01UL << UART1_LSR_RXFE_Pos) /*!< UART1 LSR: RXFE Mask */
+
+// ---------------------------------------- UART1_MSR -------------------------------------------
+#define UART1_MSR_DCTS_Pos 0 /*!< UART1 MSR: DCTS Position */
+#define UART1_MSR_DCTS_Msk (0x01UL << UART1_MSR_DCTS_Pos) /*!< UART1 MSR: DCTS Mask */
+#define UART1_MSR_DDSR_Pos 1 /*!< UART1 MSR: DDSR Position */
+#define UART1_MSR_DDSR_Msk (0x01UL << UART1_MSR_DDSR_Pos) /*!< UART1 MSR: DDSR Mask */
+#define UART1_MSR_TERI_Pos 2 /*!< UART1 MSR: TERI Position */
+#define UART1_MSR_TERI_Msk (0x01UL << UART1_MSR_TERI_Pos) /*!< UART1 MSR: TERI Mask */
+#define UART1_MSR_DDCD_Pos 3 /*!< UART1 MSR: DDCD Position */
+#define UART1_MSR_DDCD_Msk (0x01UL << UART1_MSR_DDCD_Pos) /*!< UART1 MSR: DDCD Mask */
+#define UART1_MSR_CTS_Pos 4 /*!< UART1 MSR: CTS Position */
+#define UART1_MSR_CTS_Msk (0x01UL << UART1_MSR_CTS_Pos) /*!< UART1 MSR: CTS Mask */
+#define UART1_MSR_DSR_Pos 5 /*!< UART1 MSR: DSR Position */
+#define UART1_MSR_DSR_Msk (0x01UL << UART1_MSR_DSR_Pos) /*!< UART1 MSR: DSR Mask */
+#define UART1_MSR_RI_Pos 6 /*!< UART1 MSR: RI Position */
+#define UART1_MSR_RI_Msk (0x01UL << UART1_MSR_RI_Pos) /*!< UART1 MSR: RI Mask */
+#define UART1_MSR_DCD_Pos 7 /*!< UART1 MSR: DCD Position */
+#define UART1_MSR_DCD_Msk (0x01UL << UART1_MSR_DCD_Pos) /*!< UART1 MSR: DCD Mask */
+
+// ---------------------------------------- UART1_SCR -------------------------------------------
+#define UART1_SCR_Pad_Pos 0 /*!< UART1 SCR: Pad Position */
+#define UART1_SCR_Pad_Msk (0x000000ffUL << UART1_SCR_Pad_Pos) /*!< UART1 SCR: Pad Mask */
+
+// ---------------------------------------- UART1_ACR -------------------------------------------
+#define UART1_ACR_START_Pos 0 /*!< UART1 ACR: START Position */
+#define UART1_ACR_START_Msk (0x01UL << UART1_ACR_START_Pos) /*!< UART1 ACR: START Mask */
+#define UART1_ACR_MODE_Pos 1 /*!< UART1 ACR: MODE Position */
+#define UART1_ACR_MODE_Msk (0x01UL << UART1_ACR_MODE_Pos) /*!< UART1 ACR: MODE Mask */
+#define UART1_ACR_AUTORESTART_Pos 2 /*!< UART1 ACR: AUTORESTART Position */
+#define UART1_ACR_AUTORESTART_Msk (0x01UL << UART1_ACR_AUTORESTART_Pos) /*!< UART1 ACR: AUTORESTART Mask */
+#define UART1_ACR_ABEOINTCLR_Pos 8 /*!< UART1 ACR: ABEOINTCLR Position */
+#define UART1_ACR_ABEOINTCLR_Msk (0x01UL << UART1_ACR_ABEOINTCLR_Pos) /*!< UART1 ACR: ABEOINTCLR Mask */
+#define UART1_ACR_ABTOINTCLR_Pos 9 /*!< UART1 ACR: ABTOINTCLR Position */
+#define UART1_ACR_ABTOINTCLR_Msk (0x01UL << UART1_ACR_ABTOINTCLR_Pos) /*!< UART1 ACR: ABTOINTCLR Mask */
+
+// ---------------------------------------- UART1_FDR -------------------------------------------
+#define UART1_FDR_DIVADDVAL_Pos 0 /*!< UART1 FDR: DIVADDVAL Position */
+#define UART1_FDR_DIVADDVAL_Msk (0x0fUL << UART1_FDR_DIVADDVAL_Pos) /*!< UART1 FDR: DIVADDVAL Mask */
+#define UART1_FDR_MULVAL_Pos 4 /*!< UART1 FDR: MULVAL Position */
+#define UART1_FDR_MULVAL_Msk (0x0fUL << UART1_FDR_MULVAL_Pos) /*!< UART1 FDR: MULVAL Mask */
+
+// ---------------------------------------- UART1_TER -------------------------------------------
+#define UART1_TER_TXEN_Pos 7 /*!< UART1 TER: TXEN Position */
+#define UART1_TER_TXEN_Msk (0x01UL << UART1_TER_TXEN_Pos) /*!< UART1 TER: TXEN Mask */
+
+// ------------------------------------- UART1_RS485CTRL ----------------------------------------
+#define UART1_RS485CTRL_NMMEN_Pos 0 /*!< UART1 RS485CTRL: NMMEN Position */
+#define UART1_RS485CTRL_NMMEN_Msk (0x01UL << UART1_RS485CTRL_NMMEN_Pos) /*!< UART1 RS485CTRL: NMMEN Mask */
+#define UART1_RS485CTRL_RXDIS_Pos 1 /*!< UART1 RS485CTRL: RXDIS Position */
+#define UART1_RS485CTRL_RXDIS_Msk (0x01UL << UART1_RS485CTRL_RXDIS_Pos) /*!< UART1 RS485CTRL: RXDIS Mask */
+#define UART1_RS485CTRL_AADEN_Pos 2 /*!< UART1 RS485CTRL: AADEN Position */
+#define UART1_RS485CTRL_AADEN_Msk (0x01UL << UART1_RS485CTRL_AADEN_Pos) /*!< UART1 RS485CTRL: AADEN Mask */
+#define UART1_RS485CTRL_SEL_Pos 3 /*!< UART1 RS485CTRL: SEL Position */
+#define UART1_RS485CTRL_SEL_Msk (0x01UL << UART1_RS485CTRL_SEL_Pos) /*!< UART1 RS485CTRL: SEL Mask */
+#define UART1_RS485CTRL_DCTRL_Pos 4 /*!< UART1 RS485CTRL: DCTRL Position */
+#define UART1_RS485CTRL_DCTRL_Msk (0x01UL << UART1_RS485CTRL_DCTRL_Pos) /*!< UART1 RS485CTRL: DCTRL Mask */
+#define UART1_RS485CTRL_OINV_Pos 5 /*!< UART1 RS485CTRL: OINV Position */
+#define UART1_RS485CTRL_OINV_Msk (0x01UL << UART1_RS485CTRL_OINV_Pos) /*!< UART1 RS485CTRL: OINV Mask */
+
+// ----------------------------------- UART1_RS485ADRMATCH --------------------------------------
+#define UART1_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< UART1 RS485ADRMATCH: ADRMATCH Position */
+#define UART1_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << UART1_RS485ADRMATCH_ADRMATCH_Pos) /*!< UART1 RS485ADRMATCH: ADRMATCH Mask */
+
+// ------------------------------------- UART1_RS485DLY -----------------------------------------
+#define UART1_RS485DLY_DLY_Pos 0 /*!< UART1 RS485DLY: DLY Position */
+#define UART1_RS485DLY_DLY_Msk (0x000000ffUL << UART1_RS485DLY_DLY_Pos) /*!< UART1 RS485DLY: DLY Mask */
+
+// -------------------------------------- UART1_FIFOLVL -----------------------------------------
+#define UART1_FIFOLVL_RXFIFILVL_Pos 0 /*!< UART1 FIFOLVL: RXFIFILVL Position */
+#define UART1_FIFOLVL_RXFIFILVL_Msk (0x0fUL << UART1_FIFOLVL_RXFIFILVL_Pos) /*!< UART1 FIFOLVL: RXFIFILVL Mask */
+#define UART1_FIFOLVL_TXFIFOLVL_Pos 8 /*!< UART1 FIFOLVL: TXFIFOLVL Position */
+#define UART1_FIFOLVL_TXFIFOLVL_Msk (0x0fUL << UART1_FIFOLVL_TXFIFOLVL_Pos) /*!< UART1 FIFOLVL: TXFIFOLVL Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SSP0 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------- SSP0_CR0 --------------------------------------------
+#define SSP0_CR0_DSS_Pos 0 /*!< SSP0 CR0: DSS Position */
+#define SSP0_CR0_DSS_Msk (0x0fUL << SSP0_CR0_DSS_Pos) /*!< SSP0 CR0: DSS Mask */
+#define SSP0_CR0_FRF_Pos 4 /*!< SSP0 CR0: FRF Position */
+#define SSP0_CR0_FRF_Msk (0x03UL << SSP0_CR0_FRF_Pos) /*!< SSP0 CR0: FRF Mask */
+#define SSP0_CR0_CPOL_Pos 6 /*!< SSP0 CR0: CPOL Position */
+#define SSP0_CR0_CPOL_Msk (0x01UL << SSP0_CR0_CPOL_Pos) /*!< SSP0 CR0: CPOL Mask */
+#define SSP0_CR0_CPHA_Pos 7 /*!< SSP0 CR0: CPHA Position */
+#define SSP0_CR0_CPHA_Msk (0x01UL << SSP0_CR0_CPHA_Pos) /*!< SSP0 CR0: CPHA Mask */
+#define SSP0_CR0_SCR_Pos 8 /*!< SSP0 CR0: SCR Position */
+#define SSP0_CR0_SCR_Msk (0x000000ffUL << SSP0_CR0_SCR_Pos) /*!< SSP0 CR0: SCR Mask */
+
+// ---------------------------------------- SSP0_CR1 --------------------------------------------
+#define SSP0_CR1_LBM_Pos 0 /*!< SSP0 CR1: LBM Position */
+#define SSP0_CR1_LBM_Msk (0x01UL << SSP0_CR1_LBM_Pos) /*!< SSP0 CR1: LBM Mask */
+#define SSP0_CR1_SSE_Pos 1 /*!< SSP0 CR1: SSE Position */
+#define SSP0_CR1_SSE_Msk (0x01UL << SSP0_CR1_SSE_Pos) /*!< SSP0 CR1: SSE Mask */
+#define SSP0_CR1_MS_Pos 2 /*!< SSP0 CR1: MS Position */
+#define SSP0_CR1_MS_Msk (0x01UL << SSP0_CR1_MS_Pos) /*!< SSP0 CR1: MS Mask */
+#define SSP0_CR1_SOD_Pos 3 /*!< SSP0 CR1: SOD Position */
+#define SSP0_CR1_SOD_Msk (0x01UL << SSP0_CR1_SOD_Pos) /*!< SSP0 CR1: SOD Mask */
+
+// ----------------------------------------- SSP0_DR --------------------------------------------
+#define SSP0_DR_DATA_Pos 0 /*!< SSP0 DR: DATA Position */
+#define SSP0_DR_DATA_Msk (0x0000ffffUL << SSP0_DR_DATA_Pos) /*!< SSP0 DR: DATA Mask */
+
+// ----------------------------------------- SSP0_SR --------------------------------------------
+#define SSP0_SR_TFE_Pos 0 /*!< SSP0 SR: TFE Position */
+#define SSP0_SR_TFE_Msk (0x01UL << SSP0_SR_TFE_Pos) /*!< SSP0 SR: TFE Mask */
+#define SSP0_SR_TNF_Pos 1 /*!< SSP0 SR: TNF Position */
+#define SSP0_SR_TNF_Msk (0x01UL << SSP0_SR_TNF_Pos) /*!< SSP0 SR: TNF Mask */
+#define SSP0_SR_RNE_Pos 2 /*!< SSP0 SR: RNE Position */
+#define SSP0_SR_RNE_Msk (0x01UL << SSP0_SR_RNE_Pos) /*!< SSP0 SR: RNE Mask */
+#define SSP0_SR_RFF_Pos 3 /*!< SSP0 SR: RFF Position */
+#define SSP0_SR_RFF_Msk (0x01UL << SSP0_SR_RFF_Pos) /*!< SSP0 SR: RFF Mask */
+#define SSP0_SR_BSY_Pos 4 /*!< SSP0 SR: BSY Position */
+#define SSP0_SR_BSY_Msk (0x01UL << SSP0_SR_BSY_Pos) /*!< SSP0 SR: BSY Mask */
+
+// ---------------------------------------- SSP0_CPSR -------------------------------------------
+#define SSP0_CPSR_CPSDVSR_Pos 0 /*!< SSP0 CPSR: CPSDVSR Position */
+#define SSP0_CPSR_CPSDVSR_Msk (0x000000ffUL << SSP0_CPSR_CPSDVSR_Pos) /*!< SSP0 CPSR: CPSDVSR Mask */
+
+// ---------------------------------------- SSP0_IMSC -------------------------------------------
+#define SSP0_IMSC_RORIM_Pos 0 /*!< SSP0 IMSC: RORIM Position */
+#define SSP0_IMSC_RORIM_Msk (0x01UL << SSP0_IMSC_RORIM_Pos) /*!< SSP0 IMSC: RORIM Mask */
+#define SSP0_IMSC_RTIM_Pos 1 /*!< SSP0 IMSC: RTIM Position */
+#define SSP0_IMSC_RTIM_Msk (0x01UL << SSP0_IMSC_RTIM_Pos) /*!< SSP0 IMSC: RTIM Mask */
+#define SSP0_IMSC_RXIM_Pos 2 /*!< SSP0 IMSC: RXIM Position */
+#define SSP0_IMSC_RXIM_Msk (0x01UL << SSP0_IMSC_RXIM_Pos) /*!< SSP0 IMSC: RXIM Mask */
+#define SSP0_IMSC_TXIM_Pos 3 /*!< SSP0 IMSC: TXIM Position */
+#define SSP0_IMSC_TXIM_Msk (0x01UL << SSP0_IMSC_TXIM_Pos) /*!< SSP0 IMSC: TXIM Mask */
+
+// ---------------------------------------- SSP0_RIS --------------------------------------------
+#define SSP0_RIS_RORRIS_Pos 0 /*!< SSP0 RIS: RORRIS Position */
+#define SSP0_RIS_RORRIS_Msk (0x01UL << SSP0_RIS_RORRIS_Pos) /*!< SSP0 RIS: RORRIS Mask */
+#define SSP0_RIS_RTRIS_Pos 1 /*!< SSP0 RIS: RTRIS Position */
+#define SSP0_RIS_RTRIS_Msk (0x01UL << SSP0_RIS_RTRIS_Pos) /*!< SSP0 RIS: RTRIS Mask */
+#define SSP0_RIS_RXRIS_Pos 2 /*!< SSP0 RIS: RXRIS Position */
+#define SSP0_RIS_RXRIS_Msk (0x01UL << SSP0_RIS_RXRIS_Pos) /*!< SSP0 RIS: RXRIS Mask */
+#define SSP0_RIS_TXRIS_Pos 3 /*!< SSP0 RIS: TXRIS Position */
+#define SSP0_RIS_TXRIS_Msk (0x01UL << SSP0_RIS_TXRIS_Pos) /*!< SSP0 RIS: TXRIS Mask */
+
+// ---------------------------------------- SSP0_MIS --------------------------------------------
+#define SSP0_MIS_RORMIS_Pos 0 /*!< SSP0 MIS: RORMIS Position */
+#define SSP0_MIS_RORMIS_Msk (0x01UL << SSP0_MIS_RORMIS_Pos) /*!< SSP0 MIS: RORMIS Mask */
+#define SSP0_MIS_RTMIS_Pos 1 /*!< SSP0 MIS: RTMIS Position */
+#define SSP0_MIS_RTMIS_Msk (0x01UL << SSP0_MIS_RTMIS_Pos) /*!< SSP0 MIS: RTMIS Mask */
+#define SSP0_MIS_RXMIS_Pos 2 /*!< SSP0 MIS: RXMIS Position */
+#define SSP0_MIS_RXMIS_Msk (0x01UL << SSP0_MIS_RXMIS_Pos) /*!< SSP0 MIS: RXMIS Mask */
+#define SSP0_MIS_TXMIS_Pos 3 /*!< SSP0 MIS: TXMIS Position */
+#define SSP0_MIS_TXMIS_Msk (0x01UL << SSP0_MIS_TXMIS_Pos) /*!< SSP0 MIS: TXMIS Mask */
+
+// ---------------------------------------- SSP0_ICR --------------------------------------------
+#define SSP0_ICR_RORIC_Pos 0 /*!< SSP0 ICR: RORIC Position */
+#define SSP0_ICR_RORIC_Msk (0x01UL << SSP0_ICR_RORIC_Pos) /*!< SSP0 ICR: RORIC Mask */
+#define SSP0_ICR_RTIC_Pos 1 /*!< SSP0 ICR: RTIC Position */
+#define SSP0_ICR_RTIC_Msk (0x01UL << SSP0_ICR_RTIC_Pos) /*!< SSP0 ICR: RTIC Mask */
+
+// --------------------------------------- SSP0_DMACR -------------------------------------------
+#define SSP0_DMACR_RXDMAE_Pos 0 /*!< SSP0 DMACR: RXDMAE Position */
+#define SSP0_DMACR_RXDMAE_Msk (0x01UL << SSP0_DMACR_RXDMAE_Pos) /*!< SSP0 DMACR: RXDMAE Mask */
+#define SSP0_DMACR_TXDMAE_Pos 1 /*!< SSP0 DMACR: TXDMAE Position */
+#define SSP0_DMACR_TXDMAE_Msk (0x01UL << SSP0_DMACR_TXDMAE_Pos) /*!< SSP0 DMACR: TXDMAE Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SSP1 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------- SSP1_CR0 --------------------------------------------
+#define SSP1_CR0_DSS_Pos 0 /*!< SSP1 CR0: DSS Position */
+#define SSP1_CR0_DSS_Msk (0x0fUL << SSP1_CR0_DSS_Pos) /*!< SSP1 CR0: DSS Mask */
+#define SSP1_CR0_FRF_Pos 4 /*!< SSP1 CR0: FRF Position */
+#define SSP1_CR0_FRF_Msk (0x03UL << SSP1_CR0_FRF_Pos) /*!< SSP1 CR0: FRF Mask */
+#define SSP1_CR0_CPOL_Pos 6 /*!< SSP1 CR0: CPOL Position */
+#define SSP1_CR0_CPOL_Msk (0x01UL << SSP1_CR0_CPOL_Pos) /*!< SSP1 CR0: CPOL Mask */
+#define SSP1_CR0_CPHA_Pos 7 /*!< SSP1 CR0: CPHA Position */
+#define SSP1_CR0_CPHA_Msk (0x01UL << SSP1_CR0_CPHA_Pos) /*!< SSP1 CR0: CPHA Mask */
+#define SSP1_CR0_SCR_Pos 8 /*!< SSP1 CR0: SCR Position */
+#define SSP1_CR0_SCR_Msk (0x000000ffUL << SSP1_CR0_SCR_Pos) /*!< SSP1 CR0: SCR Mask */
+
+// ---------------------------------------- SSP1_CR1 --------------------------------------------
+#define SSP1_CR1_LBM_Pos 0 /*!< SSP1 CR1: LBM Position */
+#define SSP1_CR1_LBM_Msk (0x01UL << SSP1_CR1_LBM_Pos) /*!< SSP1 CR1: LBM Mask */
+#define SSP1_CR1_SSE_Pos 1 /*!< SSP1 CR1: SSE Position */
+#define SSP1_CR1_SSE_Msk (0x01UL << SSP1_CR1_SSE_Pos) /*!< SSP1 CR1: SSE Mask */
+#define SSP1_CR1_MS_Pos 2 /*!< SSP1 CR1: MS Position */
+#define SSP1_CR1_MS_Msk (0x01UL << SSP1_CR1_MS_Pos) /*!< SSP1 CR1: MS Mask */
+#define SSP1_CR1_SOD_Pos 3 /*!< SSP1 CR1: SOD Position */
+#define SSP1_CR1_SOD_Msk (0x01UL << SSP1_CR1_SOD_Pos) /*!< SSP1 CR1: SOD Mask */
+
+// ----------------------------------------- SSP1_DR --------------------------------------------
+#define SSP1_DR_DATA_Pos 0 /*!< SSP1 DR: DATA Position */
+#define SSP1_DR_DATA_Msk (0x0000ffffUL << SSP1_DR_DATA_Pos) /*!< SSP1 DR: DATA Mask */
+
+// ----------------------------------------- SSP1_SR --------------------------------------------
+#define SSP1_SR_TFE_Pos 0 /*!< SSP1 SR: TFE Position */
+#define SSP1_SR_TFE_Msk (0x01UL << SSP1_SR_TFE_Pos) /*!< SSP1 SR: TFE Mask */
+#define SSP1_SR_TNF_Pos 1 /*!< SSP1 SR: TNF Position */
+#define SSP1_SR_TNF_Msk (0x01UL << SSP1_SR_TNF_Pos) /*!< SSP1 SR: TNF Mask */
+#define SSP1_SR_RNE_Pos 2 /*!< SSP1 SR: RNE Position */
+#define SSP1_SR_RNE_Msk (0x01UL << SSP1_SR_RNE_Pos) /*!< SSP1 SR: RNE Mask */
+#define SSP1_SR_RFF_Pos 3 /*!< SSP1 SR: RFF Position */
+#define SSP1_SR_RFF_Msk (0x01UL << SSP1_SR_RFF_Pos) /*!< SSP1 SR: RFF Mask */
+#define SSP1_SR_BSY_Pos 4 /*!< SSP1 SR: BSY Position */
+#define SSP1_SR_BSY_Msk (0x01UL << SSP1_SR_BSY_Pos) /*!< SSP1 SR: BSY Mask */
+
+// ---------------------------------------- SSP1_CPSR -------------------------------------------
+#define SSP1_CPSR_CPSDVSR_Pos 0 /*!< SSP1 CPSR: CPSDVSR Position */
+#define SSP1_CPSR_CPSDVSR_Msk (0x000000ffUL << SSP1_CPSR_CPSDVSR_Pos) /*!< SSP1 CPSR: CPSDVSR Mask */
+
+// ---------------------------------------- SSP1_IMSC -------------------------------------------
+#define SSP1_IMSC_RORIM_Pos 0 /*!< SSP1 IMSC: RORIM Position */
+#define SSP1_IMSC_RORIM_Msk (0x01UL << SSP1_IMSC_RORIM_Pos) /*!< SSP1 IMSC: RORIM Mask */
+#define SSP1_IMSC_RTIM_Pos 1 /*!< SSP1 IMSC: RTIM Position */
+#define SSP1_IMSC_RTIM_Msk (0x01UL << SSP1_IMSC_RTIM_Pos) /*!< SSP1 IMSC: RTIM Mask */
+#define SSP1_IMSC_RXIM_Pos 2 /*!< SSP1 IMSC: RXIM Position */
+#define SSP1_IMSC_RXIM_Msk (0x01UL << SSP1_IMSC_RXIM_Pos) /*!< SSP1 IMSC: RXIM Mask */
+#define SSP1_IMSC_TXIM_Pos 3 /*!< SSP1 IMSC: TXIM Position */
+#define SSP1_IMSC_TXIM_Msk (0x01UL << SSP1_IMSC_TXIM_Pos) /*!< SSP1 IMSC: TXIM Mask */
+
+// ---------------------------------------- SSP1_RIS --------------------------------------------
+#define SSP1_RIS_RORRIS_Pos 0 /*!< SSP1 RIS: RORRIS Position */
+#define SSP1_RIS_RORRIS_Msk (0x01UL << SSP1_RIS_RORRIS_Pos) /*!< SSP1 RIS: RORRIS Mask */
+#define SSP1_RIS_RTRIS_Pos 1 /*!< SSP1 RIS: RTRIS Position */
+#define SSP1_RIS_RTRIS_Msk (0x01UL << SSP1_RIS_RTRIS_Pos) /*!< SSP1 RIS: RTRIS Mask */
+#define SSP1_RIS_RXRIS_Pos 2 /*!< SSP1 RIS: RXRIS Position */
+#define SSP1_RIS_RXRIS_Msk (0x01UL << SSP1_RIS_RXRIS_Pos) /*!< SSP1 RIS: RXRIS Mask */
+#define SSP1_RIS_TXRIS_Pos 3 /*!< SSP1 RIS: TXRIS Position */
+#define SSP1_RIS_TXRIS_Msk (0x01UL << SSP1_RIS_TXRIS_Pos) /*!< SSP1 RIS: TXRIS Mask */
+
+// ---------------------------------------- SSP1_MIS --------------------------------------------
+#define SSP1_MIS_RORMIS_Pos 0 /*!< SSP1 MIS: RORMIS Position */
+#define SSP1_MIS_RORMIS_Msk (0x01UL << SSP1_MIS_RORMIS_Pos) /*!< SSP1 MIS: RORMIS Mask */
+#define SSP1_MIS_RTMIS_Pos 1 /*!< SSP1 MIS: RTMIS Position */
+#define SSP1_MIS_RTMIS_Msk (0x01UL << SSP1_MIS_RTMIS_Pos) /*!< SSP1 MIS: RTMIS Mask */
+#define SSP1_MIS_RXMIS_Pos 2 /*!< SSP1 MIS: RXMIS Position */
+#define SSP1_MIS_RXMIS_Msk (0x01UL << SSP1_MIS_RXMIS_Pos) /*!< SSP1 MIS: RXMIS Mask */
+#define SSP1_MIS_TXMIS_Pos 3 /*!< SSP1 MIS: TXMIS Position */
+#define SSP1_MIS_TXMIS_Msk (0x01UL << SSP1_MIS_TXMIS_Pos) /*!< SSP1 MIS: TXMIS Mask */
+
+// ---------------------------------------- SSP1_ICR --------------------------------------------
+#define SSP1_ICR_RORIC_Pos 0 /*!< SSP1 ICR: RORIC Position */
+#define SSP1_ICR_RORIC_Msk (0x01UL << SSP1_ICR_RORIC_Pos) /*!< SSP1 ICR: RORIC Mask */
+#define SSP1_ICR_RTIC_Pos 1 /*!< SSP1 ICR: RTIC Position */
+#define SSP1_ICR_RTIC_Msk (0x01UL << SSP1_ICR_RTIC_Pos) /*!< SSP1 ICR: RTIC Mask */
+
+// --------------------------------------- SSP1_DMACR -------------------------------------------
+#define SSP1_DMACR_RXDMAE_Pos 0 /*!< SSP1 DMACR: RXDMAE Position */
+#define SSP1_DMACR_RXDMAE_Msk (0x01UL << SSP1_DMACR_RXDMAE_Pos) /*!< SSP1 DMACR: RXDMAE Mask */
+#define SSP1_DMACR_TXDMAE_Pos 1 /*!< SSP1 DMACR: TXDMAE Position */
+#define SSP1_DMACR_TXDMAE_Msk (0x01UL << SSP1_DMACR_TXDMAE_Pos) /*!< SSP1 DMACR: TXDMAE Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- TIMER0 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------- TIMER0_IR -------------------------------------------
+#define TIMER0_IR_MR0INT_Pos 0 /*!< TIMER0 IR: MR0INT Position */
+#define TIMER0_IR_MR0INT_Msk (0x01UL << TIMER0_IR_MR0INT_Pos) /*!< TIMER0 IR: MR0INT Mask */
+#define TIMER0_IR_MR1INT_Pos 1 /*!< TIMER0 IR: MR1INT Position */
+#define TIMER0_IR_MR1INT_Msk (0x01UL << TIMER0_IR_MR1INT_Pos) /*!< TIMER0 IR: MR1INT Mask */
+#define TIMER0_IR_MR2INT_Pos 2 /*!< TIMER0 IR: MR2INT Position */
+#define TIMER0_IR_MR2INT_Msk (0x01UL << TIMER0_IR_MR2INT_Pos) /*!< TIMER0 IR: MR2INT Mask */
+#define TIMER0_IR_MR3INT_Pos 3 /*!< TIMER0 IR: MR3INT Position */
+#define TIMER0_IR_MR3INT_Msk (0x01UL << TIMER0_IR_MR3INT_Pos) /*!< TIMER0 IR: MR3INT Mask */
+#define TIMER0_IR_CR0INT_Pos 4 /*!< TIMER0 IR: CR0INT Position */
+#define TIMER0_IR_CR0INT_Msk (0x01UL << TIMER0_IR_CR0INT_Pos) /*!< TIMER0 IR: CR0INT Mask */
+#define TIMER0_IR_CR1INT_Pos 5 /*!< TIMER0 IR: CR1INT Position */
+#define TIMER0_IR_CR1INT_Msk (0x01UL << TIMER0_IR_CR1INT_Pos) /*!< TIMER0 IR: CR1INT Mask */
+#define TIMER0_IR_CR2INT_Pos 6 /*!< TIMER0 IR: CR2INT Position */
+#define TIMER0_IR_CR2INT_Msk (0x01UL << TIMER0_IR_CR2INT_Pos) /*!< TIMER0 IR: CR2INT Mask */
+#define TIMER0_IR_CR3INT_Pos 7 /*!< TIMER0 IR: CR3INT Position */
+#define TIMER0_IR_CR3INT_Msk (0x01UL << TIMER0_IR_CR3INT_Pos) /*!< TIMER0 IR: CR3INT Mask */
+
+// --------------------------------------- TIMER0_TCR -------------------------------------------
+#define TIMER0_TCR_CEN_Pos 0 /*!< TIMER0 TCR: CEN Position */
+#define TIMER0_TCR_CEN_Msk (0x01UL << TIMER0_TCR_CEN_Pos) /*!< TIMER0 TCR: CEN Mask */
+#define TIMER0_TCR_CRST_Pos 1 /*!< TIMER0 TCR: CRST Position */
+#define TIMER0_TCR_CRST_Msk (0x01UL << TIMER0_TCR_CRST_Pos) /*!< TIMER0 TCR: CRST Mask */
+
+// ---------------------------------------- TIMER0_TC -------------------------------------------
+#define TIMER0_TC_TC_Pos 0 /*!< TIMER0 TC: TC Position */
+#define TIMER0_TC_TC_Msk (0xffffffffUL << TIMER0_TC_TC_Pos) /*!< TIMER0 TC: TC Mask */
+
+// ---------------------------------------- TIMER0_PR -------------------------------------------
+#define TIMER0_PR_PM_Pos 0 /*!< TIMER0 PR: PM Position */
+#define TIMER0_PR_PM_Msk (0xffffffffUL << TIMER0_PR_PM_Pos) /*!< TIMER0 PR: PM Mask */
+
+// ---------------------------------------- TIMER0_PC -------------------------------------------
+#define TIMER0_PC_PC_Pos 0 /*!< TIMER0 PC: PC Position */
+#define TIMER0_PC_PC_Msk (0xffffffffUL << TIMER0_PC_PC_Pos) /*!< TIMER0 PC: PC Mask */
+
+// --------------------------------------- TIMER0_MCR -------------------------------------------
+#define TIMER0_MCR_MR0I_Pos 0 /*!< TIMER0 MCR: MR0I Position */
+#define TIMER0_MCR_MR0I_Msk (0x01UL << TIMER0_MCR_MR0I_Pos) /*!< TIMER0 MCR: MR0I Mask */
+#define TIMER0_MCR_MR0R_Pos 1 /*!< TIMER0 MCR: MR0R Position */
+#define TIMER0_MCR_MR0R_Msk (0x01UL << TIMER0_MCR_MR0R_Pos) /*!< TIMER0 MCR: MR0R Mask */
+#define TIMER0_MCR_MR0S_Pos 2 /*!< TIMER0 MCR: MR0S Position */
+#define TIMER0_MCR_MR0S_Msk (0x01UL << TIMER0_MCR_MR0S_Pos) /*!< TIMER0 MCR: MR0S Mask */
+#define TIMER0_MCR_MR1I_Pos 3 /*!< TIMER0 MCR: MR1I Position */
+#define TIMER0_MCR_MR1I_Msk (0x01UL << TIMER0_MCR_MR1I_Pos) /*!< TIMER0 MCR: MR1I Mask */
+#define TIMER0_MCR_MR1R_Pos 4 /*!< TIMER0 MCR: MR1R Position */
+#define TIMER0_MCR_MR1R_Msk (0x01UL << TIMER0_MCR_MR1R_Pos) /*!< TIMER0 MCR: MR1R Mask */
+#define TIMER0_MCR_MR1S_Pos 5 /*!< TIMER0 MCR: MR1S Position */
+#define TIMER0_MCR_MR1S_Msk (0x01UL << TIMER0_MCR_MR1S_Pos) /*!< TIMER0 MCR: MR1S Mask */
+#define TIMER0_MCR_MR2I_Pos 6 /*!< TIMER0 MCR: MR2I Position */
+#define TIMER0_MCR_MR2I_Msk (0x01UL << TIMER0_MCR_MR2I_Pos) /*!< TIMER0 MCR: MR2I Mask */
+#define TIMER0_MCR_MR2R_Pos 7 /*!< TIMER0 MCR: MR2R Position */
+#define TIMER0_MCR_MR2R_Msk (0x01UL << TIMER0_MCR_MR2R_Pos) /*!< TIMER0 MCR: MR2R Mask */
+#define TIMER0_MCR_MR2S_Pos 8 /*!< TIMER0 MCR: MR2S Position */
+#define TIMER0_MCR_MR2S_Msk (0x01UL << TIMER0_MCR_MR2S_Pos) /*!< TIMER0 MCR: MR2S Mask */
+#define TIMER0_MCR_MR3I_Pos 9 /*!< TIMER0 MCR: MR3I Position */
+#define TIMER0_MCR_MR3I_Msk (0x01UL << TIMER0_MCR_MR3I_Pos) /*!< TIMER0 MCR: MR3I Mask */
+#define TIMER0_MCR_MR3R_Pos 10 /*!< TIMER0 MCR: MR3R Position */
+#define TIMER0_MCR_MR3R_Msk (0x01UL << TIMER0_MCR_MR3R_Pos) /*!< TIMER0 MCR: MR3R Mask */
+#define TIMER0_MCR_MR3S_Pos 11 /*!< TIMER0 MCR: MR3S Position */
+#define TIMER0_MCR_MR3S_Msk (0x01UL << TIMER0_MCR_MR3S_Pos) /*!< TIMER0 MCR: MR3S Mask */
+
+// --------------------------------------- TIMER0_MR0 -------------------------------------------
+#define TIMER0_MR0_MATCH_Pos 0 /*!< TIMER0 MR0: MATCH Position */
+#define TIMER0_MR0_MATCH_Msk (0xffffffffUL << TIMER0_MR0_MATCH_Pos) /*!< TIMER0 MR0: MATCH Mask */
+
+// --------------------------------------- TIMER0_MR1 -------------------------------------------
+#define TIMER0_MR1_MATCH_Pos 0 /*!< TIMER0 MR1: MATCH Position */
+#define TIMER0_MR1_MATCH_Msk (0xffffffffUL << TIMER0_MR1_MATCH_Pos) /*!< TIMER0 MR1: MATCH Mask */
+
+// --------------------------------------- TIMER0_MR2 -------------------------------------------
+#define TIMER0_MR2_MATCH_Pos 0 /*!< TIMER0 MR2: MATCH Position */
+#define TIMER0_MR2_MATCH_Msk (0xffffffffUL << TIMER0_MR2_MATCH_Pos) /*!< TIMER0 MR2: MATCH Mask */
+
+// --------------------------------------- TIMER0_MR3 -------------------------------------------
+#define TIMER0_MR3_MATCH_Pos 0 /*!< TIMER0 MR3: MATCH Position */
+#define TIMER0_MR3_MATCH_Msk (0xffffffffUL << TIMER0_MR3_MATCH_Pos) /*!< TIMER0 MR3: MATCH Mask */
+
+// --------------------------------------- TIMER0_CCR -------------------------------------------
+#define TIMER0_CCR_CAP0RE_Pos 0 /*!< TIMER0 CCR: CAP0RE Position */
+#define TIMER0_CCR_CAP0RE_Msk (0x01UL << TIMER0_CCR_CAP0RE_Pos) /*!< TIMER0 CCR: CAP0RE Mask */
+#define TIMER0_CCR_CAP0FE_Pos 1 /*!< TIMER0 CCR: CAP0FE Position */
+#define TIMER0_CCR_CAP0FE_Msk (0x01UL << TIMER0_CCR_CAP0FE_Pos) /*!< TIMER0 CCR: CAP0FE Mask */
+#define TIMER0_CCR_CAP0I_Pos 2 /*!< TIMER0 CCR: CAP0I Position */
+#define TIMER0_CCR_CAP0I_Msk (0x01UL << TIMER0_CCR_CAP0I_Pos) /*!< TIMER0 CCR: CAP0I Mask */
+#define TIMER0_CCR_CAP1RE_Pos 3 /*!< TIMER0 CCR: CAP1RE Position */
+#define TIMER0_CCR_CAP1RE_Msk (0x01UL << TIMER0_CCR_CAP1RE_Pos) /*!< TIMER0 CCR: CAP1RE Mask */
+#define TIMER0_CCR_CAP1FE_Pos 4 /*!< TIMER0 CCR: CAP1FE Position */
+#define TIMER0_CCR_CAP1FE_Msk (0x01UL << TIMER0_CCR_CAP1FE_Pos) /*!< TIMER0 CCR: CAP1FE Mask */
+#define TIMER0_CCR_CAP1I_Pos 5 /*!< TIMER0 CCR: CAP1I Position */
+#define TIMER0_CCR_CAP1I_Msk (0x01UL << TIMER0_CCR_CAP1I_Pos) /*!< TIMER0 CCR: CAP1I Mask */
+#define TIMER0_CCR_CAP2RE_Pos 6 /*!< TIMER0 CCR: CAP2RE Position */
+#define TIMER0_CCR_CAP2RE_Msk (0x01UL << TIMER0_CCR_CAP2RE_Pos) /*!< TIMER0 CCR: CAP2RE Mask */
+#define TIMER0_CCR_CAP2FE_Pos 7 /*!< TIMER0 CCR: CAP2FE Position */
+#define TIMER0_CCR_CAP2FE_Msk (0x01UL << TIMER0_CCR_CAP2FE_Pos) /*!< TIMER0 CCR: CAP2FE Mask */
+#define TIMER0_CCR_CAP2I_Pos 8 /*!< TIMER0 CCR: CAP2I Position */
+#define TIMER0_CCR_CAP2I_Msk (0x01UL << TIMER0_CCR_CAP2I_Pos) /*!< TIMER0 CCR: CAP2I Mask */
+#define TIMER0_CCR_CAP3RE_Pos 9 /*!< TIMER0 CCR: CAP3RE Position */
+#define TIMER0_CCR_CAP3RE_Msk (0x01UL << TIMER0_CCR_CAP3RE_Pos) /*!< TIMER0 CCR: CAP3RE Mask */
+#define TIMER0_CCR_CAP3FE_Pos 10 /*!< TIMER0 CCR: CAP3FE Position */
+#define TIMER0_CCR_CAP3FE_Msk (0x01UL << TIMER0_CCR_CAP3FE_Pos) /*!< TIMER0 CCR: CAP3FE Mask */
+#define TIMER0_CCR_CAP3I_Pos 11 /*!< TIMER0 CCR: CAP3I Position */
+#define TIMER0_CCR_CAP3I_Msk (0x01UL << TIMER0_CCR_CAP3I_Pos) /*!< TIMER0 CCR: CAP3I Mask */
+
+// --------------------------------------- TIMER0_CR0 -------------------------------------------
+#define TIMER0_CR0_CAP_Pos 0 /*!< TIMER0 CR0: CAP Position */
+#define TIMER0_CR0_CAP_Msk (0xffffffffUL << TIMER0_CR0_CAP_Pos) /*!< TIMER0 CR0: CAP Mask */
+
+// --------------------------------------- TIMER0_CR1 -------------------------------------------
+#define TIMER0_CR1_CAP_Pos 0 /*!< TIMER0 CR1: CAP Position */
+#define TIMER0_CR1_CAP_Msk (0xffffffffUL << TIMER0_CR1_CAP_Pos) /*!< TIMER0 CR1: CAP Mask */
+
+// --------------------------------------- TIMER0_CR2 -------------------------------------------
+#define TIMER0_CR2_CAP_Pos 0 /*!< TIMER0 CR2: CAP Position */
+#define TIMER0_CR2_CAP_Msk (0xffffffffUL << TIMER0_CR2_CAP_Pos) /*!< TIMER0 CR2: CAP Mask */
+
+// --------------------------------------- TIMER0_CR3 -------------------------------------------
+#define TIMER0_CR3_CAP_Pos 0 /*!< TIMER0 CR3: CAP Position */
+#define TIMER0_CR3_CAP_Msk (0xffffffffUL << TIMER0_CR3_CAP_Pos) /*!< TIMER0 CR3: CAP Mask */
+
+// --------------------------------------- TIMER0_EMR -------------------------------------------
+#define TIMER0_EMR_EM0_Pos 0 /*!< TIMER0 EMR: EM0 Position */
+#define TIMER0_EMR_EM0_Msk (0x01UL << TIMER0_EMR_EM0_Pos) /*!< TIMER0 EMR: EM0 Mask */
+#define TIMER0_EMR_EM1_Pos 1 /*!< TIMER0 EMR: EM1 Position */
+#define TIMER0_EMR_EM1_Msk (0x01UL << TIMER0_EMR_EM1_Pos) /*!< TIMER0 EMR: EM1 Mask */
+#define TIMER0_EMR_EM2_Pos 2 /*!< TIMER0 EMR: EM2 Position */
+#define TIMER0_EMR_EM2_Msk (0x01UL << TIMER0_EMR_EM2_Pos) /*!< TIMER0 EMR: EM2 Mask */
+#define TIMER0_EMR_EM3_Pos 3 /*!< TIMER0 EMR: EM3 Position */
+#define TIMER0_EMR_EM3_Msk (0x01UL << TIMER0_EMR_EM3_Pos) /*!< TIMER0 EMR: EM3 Mask */
+#define TIMER0_EMR_EMC0_Pos 4 /*!< TIMER0 EMR: EMC0 Position */
+#define TIMER0_EMR_EMC0_Msk (0x03UL << TIMER0_EMR_EMC0_Pos) /*!< TIMER0 EMR: EMC0 Mask */
+#define TIMER0_EMR_EMC1_Pos 6 /*!< TIMER0 EMR: EMC1 Position */
+#define TIMER0_EMR_EMC1_Msk (0x03UL << TIMER0_EMR_EMC1_Pos) /*!< TIMER0 EMR: EMC1 Mask */
+#define TIMER0_EMR_EMC2_Pos 8 /*!< TIMER0 EMR: EMC2 Position */
+#define TIMER0_EMR_EMC2_Msk (0x03UL << TIMER0_EMR_EMC2_Pos) /*!< TIMER0 EMR: EMC2 Mask */
+#define TIMER0_EMR_EMC3_Pos 10 /*!< TIMER0 EMR: EMC3 Position */
+#define TIMER0_EMR_EMC3_Msk (0x03UL << TIMER0_EMR_EMC3_Pos) /*!< TIMER0 EMR: EMC3 Mask */
+
+// --------------------------------------- TIMER0_CTCR ------------------------------------------
+#define TIMER0_CTCR_CTMODE_Pos 0 /*!< TIMER0 CTCR: CTMODE Position */
+#define TIMER0_CTCR_CTMODE_Msk (0x03UL << TIMER0_CTCR_CTMODE_Pos) /*!< TIMER0 CTCR: CTMODE Mask */
+#define TIMER0_CTCR_CINSEL_Pos 2 /*!< TIMER0 CTCR: CINSEL Position */
+#define TIMER0_CTCR_CINSEL_Msk (0x03UL << TIMER0_CTCR_CINSEL_Pos) /*!< TIMER0 CTCR: CINSEL Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- TIMER1 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------- TIMER1_IR -------------------------------------------
+#define TIMER1_IR_MR0INT_Pos 0 /*!< TIMER1 IR: MR0INT Position */
+#define TIMER1_IR_MR0INT_Msk (0x01UL << TIMER1_IR_MR0INT_Pos) /*!< TIMER1 IR: MR0INT Mask */
+#define TIMER1_IR_MR1INT_Pos 1 /*!< TIMER1 IR: MR1INT Position */
+#define TIMER1_IR_MR1INT_Msk (0x01UL << TIMER1_IR_MR1INT_Pos) /*!< TIMER1 IR: MR1INT Mask */
+#define TIMER1_IR_MR2INT_Pos 2 /*!< TIMER1 IR: MR2INT Position */
+#define TIMER1_IR_MR2INT_Msk (0x01UL << TIMER1_IR_MR2INT_Pos) /*!< TIMER1 IR: MR2INT Mask */
+#define TIMER1_IR_MR3INT_Pos 3 /*!< TIMER1 IR: MR3INT Position */
+#define TIMER1_IR_MR3INT_Msk (0x01UL << TIMER1_IR_MR3INT_Pos) /*!< TIMER1 IR: MR3INT Mask */
+#define TIMER1_IR_CR0INT_Pos 4 /*!< TIMER1 IR: CR0INT Position */
+#define TIMER1_IR_CR0INT_Msk (0x01UL << TIMER1_IR_CR0INT_Pos) /*!< TIMER1 IR: CR0INT Mask */
+#define TIMER1_IR_CR1INT_Pos 5 /*!< TIMER1 IR: CR1INT Position */
+#define TIMER1_IR_CR1INT_Msk (0x01UL << TIMER1_IR_CR1INT_Pos) /*!< TIMER1 IR: CR1INT Mask */
+#define TIMER1_IR_CR2INT_Pos 6 /*!< TIMER1 IR: CR2INT Position */
+#define TIMER1_IR_CR2INT_Msk (0x01UL << TIMER1_IR_CR2INT_Pos) /*!< TIMER1 IR: CR2INT Mask */
+#define TIMER1_IR_CR3INT_Pos 7 /*!< TIMER1 IR: CR3INT Position */
+#define TIMER1_IR_CR3INT_Msk (0x01UL << TIMER1_IR_CR3INT_Pos) /*!< TIMER1 IR: CR3INT Mask */
+
+// --------------------------------------- TIMER1_TCR -------------------------------------------
+#define TIMER1_TCR_CEN_Pos 0 /*!< TIMER1 TCR: CEN Position */
+#define TIMER1_TCR_CEN_Msk (0x01UL << TIMER1_TCR_CEN_Pos) /*!< TIMER1 TCR: CEN Mask */
+#define TIMER1_TCR_CRST_Pos 1 /*!< TIMER1 TCR: CRST Position */
+#define TIMER1_TCR_CRST_Msk (0x01UL << TIMER1_TCR_CRST_Pos) /*!< TIMER1 TCR: CRST Mask */
+
+// ---------------------------------------- TIMER1_TC -------------------------------------------
+#define TIMER1_TC_TC_Pos 0 /*!< TIMER1 TC: TC Position */
+#define TIMER1_TC_TC_Msk (0xffffffffUL << TIMER1_TC_TC_Pos) /*!< TIMER1 TC: TC Mask */
+
+// ---------------------------------------- TIMER1_PR -------------------------------------------
+#define TIMER1_PR_PM_Pos 0 /*!< TIMER1 PR: PM Position */
+#define TIMER1_PR_PM_Msk (0xffffffffUL << TIMER1_PR_PM_Pos) /*!< TIMER1 PR: PM Mask */
+
+// ---------------------------------------- TIMER1_PC -------------------------------------------
+#define TIMER1_PC_PC_Pos 0 /*!< TIMER1 PC: PC Position */
+#define TIMER1_PC_PC_Msk (0xffffffffUL << TIMER1_PC_PC_Pos) /*!< TIMER1 PC: PC Mask */
+
+// --------------------------------------- TIMER1_MCR -------------------------------------------
+#define TIMER1_MCR_MR0I_Pos 0 /*!< TIMER1 MCR: MR0I Position */
+#define TIMER1_MCR_MR0I_Msk (0x01UL << TIMER1_MCR_MR0I_Pos) /*!< TIMER1 MCR: MR0I Mask */
+#define TIMER1_MCR_MR0R_Pos 1 /*!< TIMER1 MCR: MR0R Position */
+#define TIMER1_MCR_MR0R_Msk (0x01UL << TIMER1_MCR_MR0R_Pos) /*!< TIMER1 MCR: MR0R Mask */
+#define TIMER1_MCR_MR0S_Pos 2 /*!< TIMER1 MCR: MR0S Position */
+#define TIMER1_MCR_MR0S_Msk (0x01UL << TIMER1_MCR_MR0S_Pos) /*!< TIMER1 MCR: MR0S Mask */
+#define TIMER1_MCR_MR1I_Pos 3 /*!< TIMER1 MCR: MR1I Position */
+#define TIMER1_MCR_MR1I_Msk (0x01UL << TIMER1_MCR_MR1I_Pos) /*!< TIMER1 MCR: MR1I Mask */
+#define TIMER1_MCR_MR1R_Pos 4 /*!< TIMER1 MCR: MR1R Position */
+#define TIMER1_MCR_MR1R_Msk (0x01UL << TIMER1_MCR_MR1R_Pos) /*!< TIMER1 MCR: MR1R Mask */
+#define TIMER1_MCR_MR1S_Pos 5 /*!< TIMER1 MCR: MR1S Position */
+#define TIMER1_MCR_MR1S_Msk (0x01UL << TIMER1_MCR_MR1S_Pos) /*!< TIMER1 MCR: MR1S Mask */
+#define TIMER1_MCR_MR2I_Pos 6 /*!< TIMER1 MCR: MR2I Position */
+#define TIMER1_MCR_MR2I_Msk (0x01UL << TIMER1_MCR_MR2I_Pos) /*!< TIMER1 MCR: MR2I Mask */
+#define TIMER1_MCR_MR2R_Pos 7 /*!< TIMER1 MCR: MR2R Position */
+#define TIMER1_MCR_MR2R_Msk (0x01UL << TIMER1_MCR_MR2R_Pos) /*!< TIMER1 MCR: MR2R Mask */
+#define TIMER1_MCR_MR2S_Pos 8 /*!< TIMER1 MCR: MR2S Position */
+#define TIMER1_MCR_MR2S_Msk (0x01UL << TIMER1_MCR_MR2S_Pos) /*!< TIMER1 MCR: MR2S Mask */
+#define TIMER1_MCR_MR3I_Pos 9 /*!< TIMER1 MCR: MR3I Position */
+#define TIMER1_MCR_MR3I_Msk (0x01UL << TIMER1_MCR_MR3I_Pos) /*!< TIMER1 MCR: MR3I Mask */
+#define TIMER1_MCR_MR3R_Pos 10 /*!< TIMER1 MCR: MR3R Position */
+#define TIMER1_MCR_MR3R_Msk (0x01UL << TIMER1_MCR_MR3R_Pos) /*!< TIMER1 MCR: MR3R Mask */
+#define TIMER1_MCR_MR3S_Pos 11 /*!< TIMER1 MCR: MR3S Position */
+#define TIMER1_MCR_MR3S_Msk (0x01UL << TIMER1_MCR_MR3S_Pos) /*!< TIMER1 MCR: MR3S Mask */
+
+// --------------------------------------- TIMER1_MR0 -------------------------------------------
+#define TIMER1_MR0_MATCH_Pos 0 /*!< TIMER1 MR0: MATCH Position */
+#define TIMER1_MR0_MATCH_Msk (0xffffffffUL << TIMER1_MR0_MATCH_Pos) /*!< TIMER1 MR0: MATCH Mask */
+
+// --------------------------------------- TIMER1_MR1 -------------------------------------------
+#define TIMER1_MR1_MATCH_Pos 0 /*!< TIMER1 MR1: MATCH Position */
+#define TIMER1_MR1_MATCH_Msk (0xffffffffUL << TIMER1_MR1_MATCH_Pos) /*!< TIMER1 MR1: MATCH Mask */
+
+// --------------------------------------- TIMER1_MR2 -------------------------------------------
+#define TIMER1_MR2_MATCH_Pos 0 /*!< TIMER1 MR2: MATCH Position */
+#define TIMER1_MR2_MATCH_Msk (0xffffffffUL << TIMER1_MR2_MATCH_Pos) /*!< TIMER1 MR2: MATCH Mask */
+
+// --------------------------------------- TIMER1_MR3 -------------------------------------------
+#define TIMER1_MR3_MATCH_Pos 0 /*!< TIMER1 MR3: MATCH Position */
+#define TIMER1_MR3_MATCH_Msk (0xffffffffUL << TIMER1_MR3_MATCH_Pos) /*!< TIMER1 MR3: MATCH Mask */
+
+// --------------------------------------- TIMER1_CCR -------------------------------------------
+#define TIMER1_CCR_CAP0RE_Pos 0 /*!< TIMER1 CCR: CAP0RE Position */
+#define TIMER1_CCR_CAP0RE_Msk (0x01UL << TIMER1_CCR_CAP0RE_Pos) /*!< TIMER1 CCR: CAP0RE Mask */
+#define TIMER1_CCR_CAP0FE_Pos 1 /*!< TIMER1 CCR: CAP0FE Position */
+#define TIMER1_CCR_CAP0FE_Msk (0x01UL << TIMER1_CCR_CAP0FE_Pos) /*!< TIMER1 CCR: CAP0FE Mask */
+#define TIMER1_CCR_CAP0I_Pos 2 /*!< TIMER1 CCR: CAP0I Position */
+#define TIMER1_CCR_CAP0I_Msk (0x01UL << TIMER1_CCR_CAP0I_Pos) /*!< TIMER1 CCR: CAP0I Mask */
+#define TIMER1_CCR_CAP1RE_Pos 3 /*!< TIMER1 CCR: CAP1RE Position */
+#define TIMER1_CCR_CAP1RE_Msk (0x01UL << TIMER1_CCR_CAP1RE_Pos) /*!< TIMER1 CCR: CAP1RE Mask */
+#define TIMER1_CCR_CAP1FE_Pos 4 /*!< TIMER1 CCR: CAP1FE Position */
+#define TIMER1_CCR_CAP1FE_Msk (0x01UL << TIMER1_CCR_CAP1FE_Pos) /*!< TIMER1 CCR: CAP1FE Mask */
+#define TIMER1_CCR_CAP1I_Pos 5 /*!< TIMER1 CCR: CAP1I Position */
+#define TIMER1_CCR_CAP1I_Msk (0x01UL << TIMER1_CCR_CAP1I_Pos) /*!< TIMER1 CCR: CAP1I Mask */
+#define TIMER1_CCR_CAP2RE_Pos 6 /*!< TIMER1 CCR: CAP2RE Position */
+#define TIMER1_CCR_CAP2RE_Msk (0x01UL << TIMER1_CCR_CAP2RE_Pos) /*!< TIMER1 CCR: CAP2RE Mask */
+#define TIMER1_CCR_CAP2FE_Pos 7 /*!< TIMER1 CCR: CAP2FE Position */
+#define TIMER1_CCR_CAP2FE_Msk (0x01UL << TIMER1_CCR_CAP2FE_Pos) /*!< TIMER1 CCR: CAP2FE Mask */
+#define TIMER1_CCR_CAP2I_Pos 8 /*!< TIMER1 CCR: CAP2I Position */
+#define TIMER1_CCR_CAP2I_Msk (0x01UL << TIMER1_CCR_CAP2I_Pos) /*!< TIMER1 CCR: CAP2I Mask */
+#define TIMER1_CCR_CAP3RE_Pos 9 /*!< TIMER1 CCR: CAP3RE Position */
+#define TIMER1_CCR_CAP3RE_Msk (0x01UL << TIMER1_CCR_CAP3RE_Pos) /*!< TIMER1 CCR: CAP3RE Mask */
+#define TIMER1_CCR_CAP3FE_Pos 10 /*!< TIMER1 CCR: CAP3FE Position */
+#define TIMER1_CCR_CAP3FE_Msk (0x01UL << TIMER1_CCR_CAP3FE_Pos) /*!< TIMER1 CCR: CAP3FE Mask */
+#define TIMER1_CCR_CAP3I_Pos 11 /*!< TIMER1 CCR: CAP3I Position */
+#define TIMER1_CCR_CAP3I_Msk (0x01UL << TIMER1_CCR_CAP3I_Pos) /*!< TIMER1 CCR: CAP3I Mask */
+
+// --------------------------------------- TIMER1_CR0 -------------------------------------------
+#define TIMER1_CR0_CAP_Pos 0 /*!< TIMER1 CR0: CAP Position */
+#define TIMER1_CR0_CAP_Msk (0xffffffffUL << TIMER1_CR0_CAP_Pos) /*!< TIMER1 CR0: CAP Mask */
+
+// --------------------------------------- TIMER1_CR1 -------------------------------------------
+#define TIMER1_CR1_CAP_Pos 0 /*!< TIMER1 CR1: CAP Position */
+#define TIMER1_CR1_CAP_Msk (0xffffffffUL << TIMER1_CR1_CAP_Pos) /*!< TIMER1 CR1: CAP Mask */
+
+// --------------------------------------- TIMER1_CR2 -------------------------------------------
+#define TIMER1_CR2_CAP_Pos 0 /*!< TIMER1 CR2: CAP Position */
+#define TIMER1_CR2_CAP_Msk (0xffffffffUL << TIMER1_CR2_CAP_Pos) /*!< TIMER1 CR2: CAP Mask */
+
+// --------------------------------------- TIMER1_CR3 -------------------------------------------
+#define TIMER1_CR3_CAP_Pos 0 /*!< TIMER1 CR3: CAP Position */
+#define TIMER1_CR3_CAP_Msk (0xffffffffUL << TIMER1_CR3_CAP_Pos) /*!< TIMER1 CR3: CAP Mask */
+
+// --------------------------------------- TIMER1_EMR -------------------------------------------
+#define TIMER1_EMR_EM0_Pos 0 /*!< TIMER1 EMR: EM0 Position */
+#define TIMER1_EMR_EM0_Msk (0x01UL << TIMER1_EMR_EM0_Pos) /*!< TIMER1 EMR: EM0 Mask */
+#define TIMER1_EMR_EM1_Pos 1 /*!< TIMER1 EMR: EM1 Position */
+#define TIMER1_EMR_EM1_Msk (0x01UL << TIMER1_EMR_EM1_Pos) /*!< TIMER1 EMR: EM1 Mask */
+#define TIMER1_EMR_EM2_Pos 2 /*!< TIMER1 EMR: EM2 Position */
+#define TIMER1_EMR_EM2_Msk (0x01UL << TIMER1_EMR_EM2_Pos) /*!< TIMER1 EMR: EM2 Mask */
+#define TIMER1_EMR_EM3_Pos 3 /*!< TIMER1 EMR: EM3 Position */
+#define TIMER1_EMR_EM3_Msk (0x01UL << TIMER1_EMR_EM3_Pos) /*!< TIMER1 EMR: EM3 Mask */
+#define TIMER1_EMR_EMC0_Pos 4 /*!< TIMER1 EMR: EMC0 Position */
+#define TIMER1_EMR_EMC0_Msk (0x03UL << TIMER1_EMR_EMC0_Pos) /*!< TIMER1 EMR: EMC0 Mask */
+#define TIMER1_EMR_EMC1_Pos 6 /*!< TIMER1 EMR: EMC1 Position */
+#define TIMER1_EMR_EMC1_Msk (0x03UL << TIMER1_EMR_EMC1_Pos) /*!< TIMER1 EMR: EMC1 Mask */
+#define TIMER1_EMR_EMC2_Pos 8 /*!< TIMER1 EMR: EMC2 Position */
+#define TIMER1_EMR_EMC2_Msk (0x03UL << TIMER1_EMR_EMC2_Pos) /*!< TIMER1 EMR: EMC2 Mask */
+#define TIMER1_EMR_EMC3_Pos 10 /*!< TIMER1 EMR: EMC3 Position */
+#define TIMER1_EMR_EMC3_Msk (0x03UL << TIMER1_EMR_EMC3_Pos) /*!< TIMER1 EMR: EMC3 Mask */
+
+// --------------------------------------- TIMER1_CTCR ------------------------------------------
+#define TIMER1_CTCR_CTMODE_Pos 0 /*!< TIMER1 CTCR: CTMODE Position */
+#define TIMER1_CTCR_CTMODE_Msk (0x03UL << TIMER1_CTCR_CTMODE_Pos) /*!< TIMER1 CTCR: CTMODE Mask */
+#define TIMER1_CTCR_CINSEL_Pos 2 /*!< TIMER1 CTCR: CINSEL Position */
+#define TIMER1_CTCR_CINSEL_Msk (0x03UL << TIMER1_CTCR_CINSEL_Pos) /*!< TIMER1 CTCR: CINSEL Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- TIMER2 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------- TIMER2_IR -------------------------------------------
+#define TIMER2_IR_MR0INT_Pos 0 /*!< TIMER2 IR: MR0INT Position */
+#define TIMER2_IR_MR0INT_Msk (0x01UL << TIMER2_IR_MR0INT_Pos) /*!< TIMER2 IR: MR0INT Mask */
+#define TIMER2_IR_MR1INT_Pos 1 /*!< TIMER2 IR: MR1INT Position */
+#define TIMER2_IR_MR1INT_Msk (0x01UL << TIMER2_IR_MR1INT_Pos) /*!< TIMER2 IR: MR1INT Mask */
+#define TIMER2_IR_MR2INT_Pos 2 /*!< TIMER2 IR: MR2INT Position */
+#define TIMER2_IR_MR2INT_Msk (0x01UL << TIMER2_IR_MR2INT_Pos) /*!< TIMER2 IR: MR2INT Mask */
+#define TIMER2_IR_MR3INT_Pos 3 /*!< TIMER2 IR: MR3INT Position */
+#define TIMER2_IR_MR3INT_Msk (0x01UL << TIMER2_IR_MR3INT_Pos) /*!< TIMER2 IR: MR3INT Mask */
+#define TIMER2_IR_CR0INT_Pos 4 /*!< TIMER2 IR: CR0INT Position */
+#define TIMER2_IR_CR0INT_Msk (0x01UL << TIMER2_IR_CR0INT_Pos) /*!< TIMER2 IR: CR0INT Mask */
+#define TIMER2_IR_CR1INT_Pos 5 /*!< TIMER2 IR: CR1INT Position */
+#define TIMER2_IR_CR1INT_Msk (0x01UL << TIMER2_IR_CR1INT_Pos) /*!< TIMER2 IR: CR1INT Mask */
+#define TIMER2_IR_CR2INT_Pos 6 /*!< TIMER2 IR: CR2INT Position */
+#define TIMER2_IR_CR2INT_Msk (0x01UL << TIMER2_IR_CR2INT_Pos) /*!< TIMER2 IR: CR2INT Mask */
+#define TIMER2_IR_CR3INT_Pos 7 /*!< TIMER2 IR: CR3INT Position */
+#define TIMER2_IR_CR3INT_Msk (0x01UL << TIMER2_IR_CR3INT_Pos) /*!< TIMER2 IR: CR3INT Mask */
+
+// --------------------------------------- TIMER2_TCR -------------------------------------------
+#define TIMER2_TCR_CEN_Pos 0 /*!< TIMER2 TCR: CEN Position */
+#define TIMER2_TCR_CEN_Msk (0x01UL << TIMER2_TCR_CEN_Pos) /*!< TIMER2 TCR: CEN Mask */
+#define TIMER2_TCR_CRST_Pos 1 /*!< TIMER2 TCR: CRST Position */
+#define TIMER2_TCR_CRST_Msk (0x01UL << TIMER2_TCR_CRST_Pos) /*!< TIMER2 TCR: CRST Mask */
+
+// ---------------------------------------- TIMER2_TC -------------------------------------------
+#define TIMER2_TC_TC_Pos 0 /*!< TIMER2 TC: TC Position */
+#define TIMER2_TC_TC_Msk (0xffffffffUL << TIMER2_TC_TC_Pos) /*!< TIMER2 TC: TC Mask */
+
+// ---------------------------------------- TIMER2_PR -------------------------------------------
+#define TIMER2_PR_PM_Pos 0 /*!< TIMER2 PR: PM Position */
+#define TIMER2_PR_PM_Msk (0xffffffffUL << TIMER2_PR_PM_Pos) /*!< TIMER2 PR: PM Mask */
+
+// ---------------------------------------- TIMER2_PC -------------------------------------------
+#define TIMER2_PC_PC_Pos 0 /*!< TIMER2 PC: PC Position */
+#define TIMER2_PC_PC_Msk (0xffffffffUL << TIMER2_PC_PC_Pos) /*!< TIMER2 PC: PC Mask */
+
+// --------------------------------------- TIMER2_MCR -------------------------------------------
+#define TIMER2_MCR_MR0I_Pos 0 /*!< TIMER2 MCR: MR0I Position */
+#define TIMER2_MCR_MR0I_Msk (0x01UL << TIMER2_MCR_MR0I_Pos) /*!< TIMER2 MCR: MR0I Mask */
+#define TIMER2_MCR_MR0R_Pos 1 /*!< TIMER2 MCR: MR0R Position */
+#define TIMER2_MCR_MR0R_Msk (0x01UL << TIMER2_MCR_MR0R_Pos) /*!< TIMER2 MCR: MR0R Mask */
+#define TIMER2_MCR_MR0S_Pos 2 /*!< TIMER2 MCR: MR0S Position */
+#define TIMER2_MCR_MR0S_Msk (0x01UL << TIMER2_MCR_MR0S_Pos) /*!< TIMER2 MCR: MR0S Mask */
+#define TIMER2_MCR_MR1I_Pos 3 /*!< TIMER2 MCR: MR1I Position */
+#define TIMER2_MCR_MR1I_Msk (0x01UL << TIMER2_MCR_MR1I_Pos) /*!< TIMER2 MCR: MR1I Mask */
+#define TIMER2_MCR_MR1R_Pos 4 /*!< TIMER2 MCR: MR1R Position */
+#define TIMER2_MCR_MR1R_Msk (0x01UL << TIMER2_MCR_MR1R_Pos) /*!< TIMER2 MCR: MR1R Mask */
+#define TIMER2_MCR_MR1S_Pos 5 /*!< TIMER2 MCR: MR1S Position */
+#define TIMER2_MCR_MR1S_Msk (0x01UL << TIMER2_MCR_MR1S_Pos) /*!< TIMER2 MCR: MR1S Mask */
+#define TIMER2_MCR_MR2I_Pos 6 /*!< TIMER2 MCR: MR2I Position */
+#define TIMER2_MCR_MR2I_Msk (0x01UL << TIMER2_MCR_MR2I_Pos) /*!< TIMER2 MCR: MR2I Mask */
+#define TIMER2_MCR_MR2R_Pos 7 /*!< TIMER2 MCR: MR2R Position */
+#define TIMER2_MCR_MR2R_Msk (0x01UL << TIMER2_MCR_MR2R_Pos) /*!< TIMER2 MCR: MR2R Mask */
+#define TIMER2_MCR_MR2S_Pos 8 /*!< TIMER2 MCR: MR2S Position */
+#define TIMER2_MCR_MR2S_Msk (0x01UL << TIMER2_MCR_MR2S_Pos) /*!< TIMER2 MCR: MR2S Mask */
+#define TIMER2_MCR_MR3I_Pos 9 /*!< TIMER2 MCR: MR3I Position */
+#define TIMER2_MCR_MR3I_Msk (0x01UL << TIMER2_MCR_MR3I_Pos) /*!< TIMER2 MCR: MR3I Mask */
+#define TIMER2_MCR_MR3R_Pos 10 /*!< TIMER2 MCR: MR3R Position */
+#define TIMER2_MCR_MR3R_Msk (0x01UL << TIMER2_MCR_MR3R_Pos) /*!< TIMER2 MCR: MR3R Mask */
+#define TIMER2_MCR_MR3S_Pos 11 /*!< TIMER2 MCR: MR3S Position */
+#define TIMER2_MCR_MR3S_Msk (0x01UL << TIMER2_MCR_MR3S_Pos) /*!< TIMER2 MCR: MR3S Mask */
+
+// --------------------------------------- TIMER2_MR0 -------------------------------------------
+#define TIMER2_MR0_MATCH_Pos 0 /*!< TIMER2 MR0: MATCH Position */
+#define TIMER2_MR0_MATCH_Msk (0xffffffffUL << TIMER2_MR0_MATCH_Pos) /*!< TIMER2 MR0: MATCH Mask */
+
+// --------------------------------------- TIMER2_MR1 -------------------------------------------
+#define TIMER2_MR1_MATCH_Pos 0 /*!< TIMER2 MR1: MATCH Position */
+#define TIMER2_MR1_MATCH_Msk (0xffffffffUL << TIMER2_MR1_MATCH_Pos) /*!< TIMER2 MR1: MATCH Mask */
+
+// --------------------------------------- TIMER2_MR2 -------------------------------------------
+#define TIMER2_MR2_MATCH_Pos 0 /*!< TIMER2 MR2: MATCH Position */
+#define TIMER2_MR2_MATCH_Msk (0xffffffffUL << TIMER2_MR2_MATCH_Pos) /*!< TIMER2 MR2: MATCH Mask */
+
+// --------------------------------------- TIMER2_MR3 -------------------------------------------
+#define TIMER2_MR3_MATCH_Pos 0 /*!< TIMER2 MR3: MATCH Position */
+#define TIMER2_MR3_MATCH_Msk (0xffffffffUL << TIMER2_MR3_MATCH_Pos) /*!< TIMER2 MR3: MATCH Mask */
+
+// --------------------------------------- TIMER2_CCR -------------------------------------------
+#define TIMER2_CCR_CAP0RE_Pos 0 /*!< TIMER2 CCR: CAP0RE Position */
+#define TIMER2_CCR_CAP0RE_Msk (0x01UL << TIMER2_CCR_CAP0RE_Pos) /*!< TIMER2 CCR: CAP0RE Mask */
+#define TIMER2_CCR_CAP0FE_Pos 1 /*!< TIMER2 CCR: CAP0FE Position */
+#define TIMER2_CCR_CAP0FE_Msk (0x01UL << TIMER2_CCR_CAP0FE_Pos) /*!< TIMER2 CCR: CAP0FE Mask */
+#define TIMER2_CCR_CAP0I_Pos 2 /*!< TIMER2 CCR: CAP0I Position */
+#define TIMER2_CCR_CAP0I_Msk (0x01UL << TIMER2_CCR_CAP0I_Pos) /*!< TIMER2 CCR: CAP0I Mask */
+#define TIMER2_CCR_CAP1RE_Pos 3 /*!< TIMER2 CCR: CAP1RE Position */
+#define TIMER2_CCR_CAP1RE_Msk (0x01UL << TIMER2_CCR_CAP1RE_Pos) /*!< TIMER2 CCR: CAP1RE Mask */
+#define TIMER2_CCR_CAP1FE_Pos 4 /*!< TIMER2 CCR: CAP1FE Position */
+#define TIMER2_CCR_CAP1FE_Msk (0x01UL << TIMER2_CCR_CAP1FE_Pos) /*!< TIMER2 CCR: CAP1FE Mask */
+#define TIMER2_CCR_CAP1I_Pos 5 /*!< TIMER2 CCR: CAP1I Position */
+#define TIMER2_CCR_CAP1I_Msk (0x01UL << TIMER2_CCR_CAP1I_Pos) /*!< TIMER2 CCR: CAP1I Mask */
+#define TIMER2_CCR_CAP2RE_Pos 6 /*!< TIMER2 CCR: CAP2RE Position */
+#define TIMER2_CCR_CAP2RE_Msk (0x01UL << TIMER2_CCR_CAP2RE_Pos) /*!< TIMER2 CCR: CAP2RE Mask */
+#define TIMER2_CCR_CAP2FE_Pos 7 /*!< TIMER2 CCR: CAP2FE Position */
+#define TIMER2_CCR_CAP2FE_Msk (0x01UL << TIMER2_CCR_CAP2FE_Pos) /*!< TIMER2 CCR: CAP2FE Mask */
+#define TIMER2_CCR_CAP2I_Pos 8 /*!< TIMER2 CCR: CAP2I Position */
+#define TIMER2_CCR_CAP2I_Msk (0x01UL << TIMER2_CCR_CAP2I_Pos) /*!< TIMER2 CCR: CAP2I Mask */
+#define TIMER2_CCR_CAP3RE_Pos 9 /*!< TIMER2 CCR: CAP3RE Position */
+#define TIMER2_CCR_CAP3RE_Msk (0x01UL << TIMER2_CCR_CAP3RE_Pos) /*!< TIMER2 CCR: CAP3RE Mask */
+#define TIMER2_CCR_CAP3FE_Pos 10 /*!< TIMER2 CCR: CAP3FE Position */
+#define TIMER2_CCR_CAP3FE_Msk (0x01UL << TIMER2_CCR_CAP3FE_Pos) /*!< TIMER2 CCR: CAP3FE Mask */
+#define TIMER2_CCR_CAP3I_Pos 11 /*!< TIMER2 CCR: CAP3I Position */
+#define TIMER2_CCR_CAP3I_Msk (0x01UL << TIMER2_CCR_CAP3I_Pos) /*!< TIMER2 CCR: CAP3I Mask */
+
+// --------------------------------------- TIMER2_CR0 -------------------------------------------
+#define TIMER2_CR0_CAP_Pos 0 /*!< TIMER2 CR0: CAP Position */
+#define TIMER2_CR0_CAP_Msk (0xffffffffUL << TIMER2_CR0_CAP_Pos) /*!< TIMER2 CR0: CAP Mask */
+
+// --------------------------------------- TIMER2_CR1 -------------------------------------------
+#define TIMER2_CR1_CAP_Pos 0 /*!< TIMER2 CR1: CAP Position */
+#define TIMER2_CR1_CAP_Msk (0xffffffffUL << TIMER2_CR1_CAP_Pos) /*!< TIMER2 CR1: CAP Mask */
+
+// --------------------------------------- TIMER2_CR2 -------------------------------------------
+#define TIMER2_CR2_CAP_Pos 0 /*!< TIMER2 CR2: CAP Position */
+#define TIMER2_CR2_CAP_Msk (0xffffffffUL << TIMER2_CR2_CAP_Pos) /*!< TIMER2 CR2: CAP Mask */
+
+// --------------------------------------- TIMER2_CR3 -------------------------------------------
+#define TIMER2_CR3_CAP_Pos 0 /*!< TIMER2 CR3: CAP Position */
+#define TIMER2_CR3_CAP_Msk (0xffffffffUL << TIMER2_CR3_CAP_Pos) /*!< TIMER2 CR3: CAP Mask */
+
+// --------------------------------------- TIMER2_EMR -------------------------------------------
+#define TIMER2_EMR_EM0_Pos 0 /*!< TIMER2 EMR: EM0 Position */
+#define TIMER2_EMR_EM0_Msk (0x01UL << TIMER2_EMR_EM0_Pos) /*!< TIMER2 EMR: EM0 Mask */
+#define TIMER2_EMR_EM1_Pos 1 /*!< TIMER2 EMR: EM1 Position */
+#define TIMER2_EMR_EM1_Msk (0x01UL << TIMER2_EMR_EM1_Pos) /*!< TIMER2 EMR: EM1 Mask */
+#define TIMER2_EMR_EM2_Pos 2 /*!< TIMER2 EMR: EM2 Position */
+#define TIMER2_EMR_EM2_Msk (0x01UL << TIMER2_EMR_EM2_Pos) /*!< TIMER2 EMR: EM2 Mask */
+#define TIMER2_EMR_EM3_Pos 3 /*!< TIMER2 EMR: EM3 Position */
+#define TIMER2_EMR_EM3_Msk (0x01UL << TIMER2_EMR_EM3_Pos) /*!< TIMER2 EMR: EM3 Mask */
+#define TIMER2_EMR_EMC0_Pos 4 /*!< TIMER2 EMR: EMC0 Position */
+#define TIMER2_EMR_EMC0_Msk (0x03UL << TIMER2_EMR_EMC0_Pos) /*!< TIMER2 EMR: EMC0 Mask */
+#define TIMER2_EMR_EMC1_Pos 6 /*!< TIMER2 EMR: EMC1 Position */
+#define TIMER2_EMR_EMC1_Msk (0x03UL << TIMER2_EMR_EMC1_Pos) /*!< TIMER2 EMR: EMC1 Mask */
+#define TIMER2_EMR_EMC2_Pos 8 /*!< TIMER2 EMR: EMC2 Position */
+#define TIMER2_EMR_EMC2_Msk (0x03UL << TIMER2_EMR_EMC2_Pos) /*!< TIMER2 EMR: EMC2 Mask */
+#define TIMER2_EMR_EMC3_Pos 10 /*!< TIMER2 EMR: EMC3 Position */
+#define TIMER2_EMR_EMC3_Msk (0x03UL << TIMER2_EMR_EMC3_Pos) /*!< TIMER2 EMR: EMC3 Mask */
+
+// --------------------------------------- TIMER2_CTCR ------------------------------------------
+#define TIMER2_CTCR_CTMODE_Pos 0 /*!< TIMER2 CTCR: CTMODE Position */
+#define TIMER2_CTCR_CTMODE_Msk (0x03UL << TIMER2_CTCR_CTMODE_Pos) /*!< TIMER2 CTCR: CTMODE Mask */
+#define TIMER2_CTCR_CINSEL_Pos 2 /*!< TIMER2 CTCR: CINSEL Position */
+#define TIMER2_CTCR_CINSEL_Msk (0x03UL << TIMER2_CTCR_CINSEL_Pos) /*!< TIMER2 CTCR: CINSEL Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- TIMER3 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------- TIMER3_IR -------------------------------------------
+#define TIMER3_IR_MR0INT_Pos 0 /*!< TIMER3 IR: MR0INT Position */
+#define TIMER3_IR_MR0INT_Msk (0x01UL << TIMER3_IR_MR0INT_Pos) /*!< TIMER3 IR: MR0INT Mask */
+#define TIMER3_IR_MR1INT_Pos 1 /*!< TIMER3 IR: MR1INT Position */
+#define TIMER3_IR_MR1INT_Msk (0x01UL << TIMER3_IR_MR1INT_Pos) /*!< TIMER3 IR: MR1INT Mask */
+#define TIMER3_IR_MR2INT_Pos 2 /*!< TIMER3 IR: MR2INT Position */
+#define TIMER3_IR_MR2INT_Msk (0x01UL << TIMER3_IR_MR2INT_Pos) /*!< TIMER3 IR: MR2INT Mask */
+#define TIMER3_IR_MR3INT_Pos 3 /*!< TIMER3 IR: MR3INT Position */
+#define TIMER3_IR_MR3INT_Msk (0x01UL << TIMER3_IR_MR3INT_Pos) /*!< TIMER3 IR: MR3INT Mask */
+#define TIMER3_IR_CR0INT_Pos 4 /*!< TIMER3 IR: CR0INT Position */
+#define TIMER3_IR_CR0INT_Msk (0x01UL << TIMER3_IR_CR0INT_Pos) /*!< TIMER3 IR: CR0INT Mask */
+#define TIMER3_IR_CR1INT_Pos 5 /*!< TIMER3 IR: CR1INT Position */
+#define TIMER3_IR_CR1INT_Msk (0x01UL << TIMER3_IR_CR1INT_Pos) /*!< TIMER3 IR: CR1INT Mask */
+#define TIMER3_IR_CR2INT_Pos 6 /*!< TIMER3 IR: CR2INT Position */
+#define TIMER3_IR_CR2INT_Msk (0x01UL << TIMER3_IR_CR2INT_Pos) /*!< TIMER3 IR: CR2INT Mask */
+#define TIMER3_IR_CR3INT_Pos 7 /*!< TIMER3 IR: CR3INT Position */
+#define TIMER3_IR_CR3INT_Msk (0x01UL << TIMER3_IR_CR3INT_Pos) /*!< TIMER3 IR: CR3INT Mask */
+
+// --------------------------------------- TIMER3_TCR -------------------------------------------
+#define TIMER3_TCR_CEN_Pos 0 /*!< TIMER3 TCR: CEN Position */
+#define TIMER3_TCR_CEN_Msk (0x01UL << TIMER3_TCR_CEN_Pos) /*!< TIMER3 TCR: CEN Mask */
+#define TIMER3_TCR_CRST_Pos 1 /*!< TIMER3 TCR: CRST Position */
+#define TIMER3_TCR_CRST_Msk (0x01UL << TIMER3_TCR_CRST_Pos) /*!< TIMER3 TCR: CRST Mask */
+
+// ---------------------------------------- TIMER3_TC -------------------------------------------
+#define TIMER3_TC_TC_Pos 0 /*!< TIMER3 TC: TC Position */
+#define TIMER3_TC_TC_Msk (0xffffffffUL << TIMER3_TC_TC_Pos) /*!< TIMER3 TC: TC Mask */
+
+// ---------------------------------------- TIMER3_PR -------------------------------------------
+#define TIMER3_PR_PM_Pos 0 /*!< TIMER3 PR: PM Position */
+#define TIMER3_PR_PM_Msk (0xffffffffUL << TIMER3_PR_PM_Pos) /*!< TIMER3 PR: PM Mask */
+
+// ---------------------------------------- TIMER3_PC -------------------------------------------
+#define TIMER3_PC_PC_Pos 0 /*!< TIMER3 PC: PC Position */
+#define TIMER3_PC_PC_Msk (0xffffffffUL << TIMER3_PC_PC_Pos) /*!< TIMER3 PC: PC Mask */
+
+// --------------------------------------- TIMER3_MCR -------------------------------------------
+#define TIMER3_MCR_MR0I_Pos 0 /*!< TIMER3 MCR: MR0I Position */
+#define TIMER3_MCR_MR0I_Msk (0x01UL << TIMER3_MCR_MR0I_Pos) /*!< TIMER3 MCR: MR0I Mask */
+#define TIMER3_MCR_MR0R_Pos 1 /*!< TIMER3 MCR: MR0R Position */
+#define TIMER3_MCR_MR0R_Msk (0x01UL << TIMER3_MCR_MR0R_Pos) /*!< TIMER3 MCR: MR0R Mask */
+#define TIMER3_MCR_MR0S_Pos 2 /*!< TIMER3 MCR: MR0S Position */
+#define TIMER3_MCR_MR0S_Msk (0x01UL << TIMER3_MCR_MR0S_Pos) /*!< TIMER3 MCR: MR0S Mask */
+#define TIMER3_MCR_MR1I_Pos 3 /*!< TIMER3 MCR: MR1I Position */
+#define TIMER3_MCR_MR1I_Msk (0x01UL << TIMER3_MCR_MR1I_Pos) /*!< TIMER3 MCR: MR1I Mask */
+#define TIMER3_MCR_MR1R_Pos 4 /*!< TIMER3 MCR: MR1R Position */
+#define TIMER3_MCR_MR1R_Msk (0x01UL << TIMER3_MCR_MR1R_Pos) /*!< TIMER3 MCR: MR1R Mask */
+#define TIMER3_MCR_MR1S_Pos 5 /*!< TIMER3 MCR: MR1S Position */
+#define TIMER3_MCR_MR1S_Msk (0x01UL << TIMER3_MCR_MR1S_Pos) /*!< TIMER3 MCR: MR1S Mask */
+#define TIMER3_MCR_MR2I_Pos 6 /*!< TIMER3 MCR: MR2I Position */
+#define TIMER3_MCR_MR2I_Msk (0x01UL << TIMER3_MCR_MR2I_Pos) /*!< TIMER3 MCR: MR2I Mask */
+#define TIMER3_MCR_MR2R_Pos 7 /*!< TIMER3 MCR: MR2R Position */
+#define TIMER3_MCR_MR2R_Msk (0x01UL << TIMER3_MCR_MR2R_Pos) /*!< TIMER3 MCR: MR2R Mask */
+#define TIMER3_MCR_MR2S_Pos 8 /*!< TIMER3 MCR: MR2S Position */
+#define TIMER3_MCR_MR2S_Msk (0x01UL << TIMER3_MCR_MR2S_Pos) /*!< TIMER3 MCR: MR2S Mask */
+#define TIMER3_MCR_MR3I_Pos 9 /*!< TIMER3 MCR: MR3I Position */
+#define TIMER3_MCR_MR3I_Msk (0x01UL << TIMER3_MCR_MR3I_Pos) /*!< TIMER3 MCR: MR3I Mask */
+#define TIMER3_MCR_MR3R_Pos 10 /*!< TIMER3 MCR: MR3R Position */
+#define TIMER3_MCR_MR3R_Msk (0x01UL << TIMER3_MCR_MR3R_Pos) /*!< TIMER3 MCR: MR3R Mask */
+#define TIMER3_MCR_MR3S_Pos 11 /*!< TIMER3 MCR: MR3S Position */
+#define TIMER3_MCR_MR3S_Msk (0x01UL << TIMER3_MCR_MR3S_Pos) /*!< TIMER3 MCR: MR3S Mask */
+
+// --------------------------------------- TIMER3_MR0 -------------------------------------------
+#define TIMER3_MR0_MATCH_Pos 0 /*!< TIMER3 MR0: MATCH Position */
+#define TIMER3_MR0_MATCH_Msk (0xffffffffUL << TIMER3_MR0_MATCH_Pos) /*!< TIMER3 MR0: MATCH Mask */
+
+// --------------------------------------- TIMER3_MR1 -------------------------------------------
+#define TIMER3_MR1_MATCH_Pos 0 /*!< TIMER3 MR1: MATCH Position */
+#define TIMER3_MR1_MATCH_Msk (0xffffffffUL << TIMER3_MR1_MATCH_Pos) /*!< TIMER3 MR1: MATCH Mask */
+
+// --------------------------------------- TIMER3_MR2 -------------------------------------------
+#define TIMER3_MR2_MATCH_Pos 0 /*!< TIMER3 MR2: MATCH Position */
+#define TIMER3_MR2_MATCH_Msk (0xffffffffUL << TIMER3_MR2_MATCH_Pos) /*!< TIMER3 MR2: MATCH Mask */
+
+// --------------------------------------- TIMER3_MR3 -------------------------------------------
+#define TIMER3_MR3_MATCH_Pos 0 /*!< TIMER3 MR3: MATCH Position */
+#define TIMER3_MR3_MATCH_Msk (0xffffffffUL << TIMER3_MR3_MATCH_Pos) /*!< TIMER3 MR3: MATCH Mask */
+
+// --------------------------------------- TIMER3_CCR -------------------------------------------
+#define TIMER3_CCR_CAP0RE_Pos 0 /*!< TIMER3 CCR: CAP0RE Position */
+#define TIMER3_CCR_CAP0RE_Msk (0x01UL << TIMER3_CCR_CAP0RE_Pos) /*!< TIMER3 CCR: CAP0RE Mask */
+#define TIMER3_CCR_CAP0FE_Pos 1 /*!< TIMER3 CCR: CAP0FE Position */
+#define TIMER3_CCR_CAP0FE_Msk (0x01UL << TIMER3_CCR_CAP0FE_Pos) /*!< TIMER3 CCR: CAP0FE Mask */
+#define TIMER3_CCR_CAP0I_Pos 2 /*!< TIMER3 CCR: CAP0I Position */
+#define TIMER3_CCR_CAP0I_Msk (0x01UL << TIMER3_CCR_CAP0I_Pos) /*!< TIMER3 CCR: CAP0I Mask */
+#define TIMER3_CCR_CAP1RE_Pos 3 /*!< TIMER3 CCR: CAP1RE Position */
+#define TIMER3_CCR_CAP1RE_Msk (0x01UL << TIMER3_CCR_CAP1RE_Pos) /*!< TIMER3 CCR: CAP1RE Mask */
+#define TIMER3_CCR_CAP1FE_Pos 4 /*!< TIMER3 CCR: CAP1FE Position */
+#define TIMER3_CCR_CAP1FE_Msk (0x01UL << TIMER3_CCR_CAP1FE_Pos) /*!< TIMER3 CCR: CAP1FE Mask */
+#define TIMER3_CCR_CAP1I_Pos 5 /*!< TIMER3 CCR: CAP1I Position */
+#define TIMER3_CCR_CAP1I_Msk (0x01UL << TIMER3_CCR_CAP1I_Pos) /*!< TIMER3 CCR: CAP1I Mask */
+#define TIMER3_CCR_CAP2RE_Pos 6 /*!< TIMER3 CCR: CAP2RE Position */
+#define TIMER3_CCR_CAP2RE_Msk (0x01UL << TIMER3_CCR_CAP2RE_Pos) /*!< TIMER3 CCR: CAP2RE Mask */
+#define TIMER3_CCR_CAP2FE_Pos 7 /*!< TIMER3 CCR: CAP2FE Position */
+#define TIMER3_CCR_CAP2FE_Msk (0x01UL << TIMER3_CCR_CAP2FE_Pos) /*!< TIMER3 CCR: CAP2FE Mask */
+#define TIMER3_CCR_CAP2I_Pos 8 /*!< TIMER3 CCR: CAP2I Position */
+#define TIMER3_CCR_CAP2I_Msk (0x01UL << TIMER3_CCR_CAP2I_Pos) /*!< TIMER3 CCR: CAP2I Mask */
+#define TIMER3_CCR_CAP3RE_Pos 9 /*!< TIMER3 CCR: CAP3RE Position */
+#define TIMER3_CCR_CAP3RE_Msk (0x01UL << TIMER3_CCR_CAP3RE_Pos) /*!< TIMER3 CCR: CAP3RE Mask */
+#define TIMER3_CCR_CAP3FE_Pos 10 /*!< TIMER3 CCR: CAP3FE Position */
+#define TIMER3_CCR_CAP3FE_Msk (0x01UL << TIMER3_CCR_CAP3FE_Pos) /*!< TIMER3 CCR: CAP3FE Mask */
+#define TIMER3_CCR_CAP3I_Pos 11 /*!< TIMER3 CCR: CAP3I Position */
+#define TIMER3_CCR_CAP3I_Msk (0x01UL << TIMER3_CCR_CAP3I_Pos) /*!< TIMER3 CCR: CAP3I Mask */
+
+// --------------------------------------- TIMER3_CR0 -------------------------------------------
+#define TIMER3_CR0_CAP_Pos 0 /*!< TIMER3 CR0: CAP Position */
+#define TIMER3_CR0_CAP_Msk (0xffffffffUL << TIMER3_CR0_CAP_Pos) /*!< TIMER3 CR0: CAP Mask */
+
+// --------------------------------------- TIMER3_CR1 -------------------------------------------
+#define TIMER3_CR1_CAP_Pos 0 /*!< TIMER3 CR1: CAP Position */
+#define TIMER3_CR1_CAP_Msk (0xffffffffUL << TIMER3_CR1_CAP_Pos) /*!< TIMER3 CR1: CAP Mask */
+
+// --------------------------------------- TIMER3_CR2 -------------------------------------------
+#define TIMER3_CR2_CAP_Pos 0 /*!< TIMER3 CR2: CAP Position */
+#define TIMER3_CR2_CAP_Msk (0xffffffffUL << TIMER3_CR2_CAP_Pos) /*!< TIMER3 CR2: CAP Mask */
+
+// --------------------------------------- TIMER3_CR3 -------------------------------------------
+#define TIMER3_CR3_CAP_Pos 0 /*!< TIMER3 CR3: CAP Position */
+#define TIMER3_CR3_CAP_Msk (0xffffffffUL << TIMER3_CR3_CAP_Pos) /*!< TIMER3 CR3: CAP Mask */
+
+// --------------------------------------- TIMER3_EMR -------------------------------------------
+#define TIMER3_EMR_EM0_Pos 0 /*!< TIMER3 EMR: EM0 Position */
+#define TIMER3_EMR_EM0_Msk (0x01UL << TIMER3_EMR_EM0_Pos) /*!< TIMER3 EMR: EM0 Mask */
+#define TIMER3_EMR_EM1_Pos 1 /*!< TIMER3 EMR: EM1 Position */
+#define TIMER3_EMR_EM1_Msk (0x01UL << TIMER3_EMR_EM1_Pos) /*!< TIMER3 EMR: EM1 Mask */
+#define TIMER3_EMR_EM2_Pos 2 /*!< TIMER3 EMR: EM2 Position */
+#define TIMER3_EMR_EM2_Msk (0x01UL << TIMER3_EMR_EM2_Pos) /*!< TIMER3 EMR: EM2 Mask */
+#define TIMER3_EMR_EM3_Pos 3 /*!< TIMER3 EMR: EM3 Position */
+#define TIMER3_EMR_EM3_Msk (0x01UL << TIMER3_EMR_EM3_Pos) /*!< TIMER3 EMR: EM3 Mask */
+#define TIMER3_EMR_EMC0_Pos 4 /*!< TIMER3 EMR: EMC0 Position */
+#define TIMER3_EMR_EMC0_Msk (0x03UL << TIMER3_EMR_EMC0_Pos) /*!< TIMER3 EMR: EMC0 Mask */
+#define TIMER3_EMR_EMC1_Pos 6 /*!< TIMER3 EMR: EMC1 Position */
+#define TIMER3_EMR_EMC1_Msk (0x03UL << TIMER3_EMR_EMC1_Pos) /*!< TIMER3 EMR: EMC1 Mask */
+#define TIMER3_EMR_EMC2_Pos 8 /*!< TIMER3 EMR: EMC2 Position */
+#define TIMER3_EMR_EMC2_Msk (0x03UL << TIMER3_EMR_EMC2_Pos) /*!< TIMER3 EMR: EMC2 Mask */
+#define TIMER3_EMR_EMC3_Pos 10 /*!< TIMER3 EMR: EMC3 Position */
+#define TIMER3_EMR_EMC3_Msk (0x03UL << TIMER3_EMR_EMC3_Pos) /*!< TIMER3 EMR: EMC3 Mask */
+
+// --------------------------------------- TIMER3_CTCR ------------------------------------------
+#define TIMER3_CTCR_CTMODE_Pos 0 /*!< TIMER3 CTCR: CTMODE Position */
+#define TIMER3_CTCR_CTMODE_Msk (0x03UL << TIMER3_CTCR_CTMODE_Pos) /*!< TIMER3 CTCR: CTMODE Mask */
+#define TIMER3_CTCR_CINSEL_Pos 2 /*!< TIMER3 CTCR: CINSEL Position */
+#define TIMER3_CTCR_CINSEL_Msk (0x03UL << TIMER3_CTCR_CINSEL_Pos) /*!< TIMER3 CTCR: CINSEL Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SCU Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------- SCU_SFSP0_0 ------------------------------------------
+#define SCU_SFSP0_0_MODE_Pos 0 /*!< SCU SFSP0_0: MODE Position */
+#define SCU_SFSP0_0_MODE_Msk (0x07UL << SCU_SFSP0_0_MODE_Pos) /*!< SCU SFSP0_0: MODE Mask */
+#define SCU_SFSP0_0_EPD_Pos 3 /*!< SCU SFSP0_0: EPD Position */
+#define SCU_SFSP0_0_EPD_Msk (0x01UL << SCU_SFSP0_0_EPD_Pos) /*!< SCU SFSP0_0: EPD Mask */
+#define SCU_SFSP0_0_EPUN_Pos 4 /*!< SCU SFSP0_0: EPUN Position */
+#define SCU_SFSP0_0_EPUN_Msk (0x01UL << SCU_SFSP0_0_EPUN_Pos) /*!< SCU SFSP0_0: EPUN Mask */
+#define SCU_SFSP0_0_EHS_Pos 5 /*!< SCU SFSP0_0: EHS Position */
+#define SCU_SFSP0_0_EHS_Msk (0x01UL << SCU_SFSP0_0_EHS_Pos) /*!< SCU SFSP0_0: EHS Mask */
+#define SCU_SFSP0_0_EZI_Pos 6 /*!< SCU SFSP0_0: EZI Position */
+#define SCU_SFSP0_0_EZI_Msk (0x01UL << SCU_SFSP0_0_EZI_Pos) /*!< SCU SFSP0_0: EZI Mask */
+
+// --------------------------------------- SCU_SFSP0_1 ------------------------------------------
+#define SCU_SFSP0_1_MODE_Pos 0 /*!< SCU SFSP0_1: MODE Position */
+#define SCU_SFSP0_1_MODE_Msk (0x07UL << SCU_SFSP0_1_MODE_Pos) /*!< SCU SFSP0_1: MODE Mask */
+#define SCU_SFSP0_1_EPD_Pos 3 /*!< SCU SFSP0_1: EPD Position */
+#define SCU_SFSP0_1_EPD_Msk (0x01UL << SCU_SFSP0_1_EPD_Pos) /*!< SCU SFSP0_1: EPD Mask */
+#define SCU_SFSP0_1_EPUN_Pos 4 /*!< SCU SFSP0_1: EPUN Position */
+#define SCU_SFSP0_1_EPUN_Msk (0x01UL << SCU_SFSP0_1_EPUN_Pos) /*!< SCU SFSP0_1: EPUN Mask */
+#define SCU_SFSP0_1_EHS_Pos 5 /*!< SCU SFSP0_1: EHS Position */
+#define SCU_SFSP0_1_EHS_Msk (0x01UL << SCU_SFSP0_1_EHS_Pos) /*!< SCU SFSP0_1: EHS Mask */
+#define SCU_SFSP0_1_EZI_Pos 6 /*!< SCU SFSP0_1: EZI Position */
+#define SCU_SFSP0_1_EZI_Msk (0x01UL << SCU_SFSP0_1_EZI_Pos) /*!< SCU SFSP0_1: EZI Mask */
+
+// --------------------------------------- SCU_SFSP1_0 ------------------------------------------
+#define SCU_SFSP1_0_MODE_Pos 0 /*!< SCU SFSP1_0: MODE Position */
+#define SCU_SFSP1_0_MODE_Msk (0x07UL << SCU_SFSP1_0_MODE_Pos) /*!< SCU SFSP1_0: MODE Mask */
+#define SCU_SFSP1_0_EPD_Pos 3 /*!< SCU SFSP1_0: EPD Position */
+#define SCU_SFSP1_0_EPD_Msk (0x01UL << SCU_SFSP1_0_EPD_Pos) /*!< SCU SFSP1_0: EPD Mask */
+#define SCU_SFSP1_0_EPUN_Pos 4 /*!< SCU SFSP1_0: EPUN Position */
+#define SCU_SFSP1_0_EPUN_Msk (0x01UL << SCU_SFSP1_0_EPUN_Pos) /*!< SCU SFSP1_0: EPUN Mask */
+#define SCU_SFSP1_0_EHS_Pos 5 /*!< SCU SFSP1_0: EHS Position */
+#define SCU_SFSP1_0_EHS_Msk (0x01UL << SCU_SFSP1_0_EHS_Pos) /*!< SCU SFSP1_0: EHS Mask */
+#define SCU_SFSP1_0_EZI_Pos 6 /*!< SCU SFSP1_0: EZI Position */
+#define SCU_SFSP1_0_EZI_Msk (0x01UL << SCU_SFSP1_0_EZI_Pos) /*!< SCU SFSP1_0: EZI Mask */
+#define SCU_SFSP1_0_EHD_Pos 8 /*!< SCU SFSP1_0: EHD Position */
+#define SCU_SFSP1_0_EHD_Msk (0x03UL << SCU_SFSP1_0_EHD_Pos) /*!< SCU SFSP1_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSP1_1 ------------------------------------------
+#define SCU_SFSP1_1_MODE_Pos 0 /*!< SCU SFSP1_1: MODE Position */
+#define SCU_SFSP1_1_MODE_Msk (0x07UL << SCU_SFSP1_1_MODE_Pos) /*!< SCU SFSP1_1: MODE Mask */
+#define SCU_SFSP1_1_EPD_Pos 3 /*!< SCU SFSP1_1: EPD Position */
+#define SCU_SFSP1_1_EPD_Msk (0x01UL << SCU_SFSP1_1_EPD_Pos) /*!< SCU SFSP1_1: EPD Mask */
+#define SCU_SFSP1_1_EPUN_Pos 4 /*!< SCU SFSP1_1: EPUN Position */
+#define SCU_SFSP1_1_EPUN_Msk (0x01UL << SCU_SFSP1_1_EPUN_Pos) /*!< SCU SFSP1_1: EPUN Mask */
+#define SCU_SFSP1_1_EHS_Pos 5 /*!< SCU SFSP1_1: EHS Position */
+#define SCU_SFSP1_1_EHS_Msk (0x01UL << SCU_SFSP1_1_EHS_Pos) /*!< SCU SFSP1_1: EHS Mask */
+#define SCU_SFSP1_1_EZI_Pos 6 /*!< SCU SFSP1_1: EZI Position */
+#define SCU_SFSP1_1_EZI_Msk (0x01UL << SCU_SFSP1_1_EZI_Pos) /*!< SCU SFSP1_1: EZI Mask */
+#define SCU_SFSP1_1_EHD_Pos 8 /*!< SCU SFSP1_1: EHD Position */
+#define SCU_SFSP1_1_EHD_Msk (0x03UL << SCU_SFSP1_1_EHD_Pos) /*!< SCU SFSP1_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSP1_2 ------------------------------------------
+#define SCU_SFSP1_2_MODE_Pos 0 /*!< SCU SFSP1_2: MODE Position */
+#define SCU_SFSP1_2_MODE_Msk (0x07UL << SCU_SFSP1_2_MODE_Pos) /*!< SCU SFSP1_2: MODE Mask */
+#define SCU_SFSP1_2_EPD_Pos 3 /*!< SCU SFSP1_2: EPD Position */
+#define SCU_SFSP1_2_EPD_Msk (0x01UL << SCU_SFSP1_2_EPD_Pos) /*!< SCU SFSP1_2: EPD Mask */
+#define SCU_SFSP1_2_EPUN_Pos 4 /*!< SCU SFSP1_2: EPUN Position */
+#define SCU_SFSP1_2_EPUN_Msk (0x01UL << SCU_SFSP1_2_EPUN_Pos) /*!< SCU SFSP1_2: EPUN Mask */
+#define SCU_SFSP1_2_EHS_Pos 5 /*!< SCU SFSP1_2: EHS Position */
+#define SCU_SFSP1_2_EHS_Msk (0x01UL << SCU_SFSP1_2_EHS_Pos) /*!< SCU SFSP1_2: EHS Mask */
+#define SCU_SFSP1_2_EZI_Pos 6 /*!< SCU SFSP1_2: EZI Position */
+#define SCU_SFSP1_2_EZI_Msk (0x01UL << SCU_SFSP1_2_EZI_Pos) /*!< SCU SFSP1_2: EZI Mask */
+#define SCU_SFSP1_2_EHD_Pos 8 /*!< SCU SFSP1_2: EHD Position */
+#define SCU_SFSP1_2_EHD_Msk (0x03UL << SCU_SFSP1_2_EHD_Pos) /*!< SCU SFSP1_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSP1_3 ------------------------------------------
+#define SCU_SFSP1_3_MODE_Pos 0 /*!< SCU SFSP1_3: MODE Position */
+#define SCU_SFSP1_3_MODE_Msk (0x07UL << SCU_SFSP1_3_MODE_Pos) /*!< SCU SFSP1_3: MODE Mask */
+#define SCU_SFSP1_3_EPD_Pos 3 /*!< SCU SFSP1_3: EPD Position */
+#define SCU_SFSP1_3_EPD_Msk (0x01UL << SCU_SFSP1_3_EPD_Pos) /*!< SCU SFSP1_3: EPD Mask */
+#define SCU_SFSP1_3_EPUN_Pos 4 /*!< SCU SFSP1_3: EPUN Position */
+#define SCU_SFSP1_3_EPUN_Msk (0x01UL << SCU_SFSP1_3_EPUN_Pos) /*!< SCU SFSP1_3: EPUN Mask */
+#define SCU_SFSP1_3_EHS_Pos 5 /*!< SCU SFSP1_3: EHS Position */
+#define SCU_SFSP1_3_EHS_Msk (0x01UL << SCU_SFSP1_3_EHS_Pos) /*!< SCU SFSP1_3: EHS Mask */
+#define SCU_SFSP1_3_EZI_Pos 6 /*!< SCU SFSP1_3: EZI Position */
+#define SCU_SFSP1_3_EZI_Msk (0x01UL << SCU_SFSP1_3_EZI_Pos) /*!< SCU SFSP1_3: EZI Mask */
+#define SCU_SFSP1_3_EHD_Pos 8 /*!< SCU SFSP1_3: EHD Position */
+#define SCU_SFSP1_3_EHD_Msk (0x03UL << SCU_SFSP1_3_EHD_Pos) /*!< SCU SFSP1_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSP1_4 ------------------------------------------
+#define SCU_SFSP1_4_MODE_Pos 0 /*!< SCU SFSP1_4: MODE Position */
+#define SCU_SFSP1_4_MODE_Msk (0x07UL << SCU_SFSP1_4_MODE_Pos) /*!< SCU SFSP1_4: MODE Mask */
+#define SCU_SFSP1_4_EPD_Pos 3 /*!< SCU SFSP1_4: EPD Position */
+#define SCU_SFSP1_4_EPD_Msk (0x01UL << SCU_SFSP1_4_EPD_Pos) /*!< SCU SFSP1_4: EPD Mask */
+#define SCU_SFSP1_4_EPUN_Pos 4 /*!< SCU SFSP1_4: EPUN Position */
+#define SCU_SFSP1_4_EPUN_Msk (0x01UL << SCU_SFSP1_4_EPUN_Pos) /*!< SCU SFSP1_4: EPUN Mask */
+#define SCU_SFSP1_4_EHS_Pos 5 /*!< SCU SFSP1_4: EHS Position */
+#define SCU_SFSP1_4_EHS_Msk (0x01UL << SCU_SFSP1_4_EHS_Pos) /*!< SCU SFSP1_4: EHS Mask */
+#define SCU_SFSP1_4_EZI_Pos 6 /*!< SCU SFSP1_4: EZI Position */
+#define SCU_SFSP1_4_EZI_Msk (0x01UL << SCU_SFSP1_4_EZI_Pos) /*!< SCU SFSP1_4: EZI Mask */
+#define SCU_SFSP1_4_EHD_Pos 8 /*!< SCU SFSP1_4: EHD Position */
+#define SCU_SFSP1_4_EHD_Msk (0x03UL << SCU_SFSP1_4_EHD_Pos) /*!< SCU SFSP1_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSP1_5 ------------------------------------------
+#define SCU_SFSP1_5_MODE_Pos 0 /*!< SCU SFSP1_5: MODE Position */
+#define SCU_SFSP1_5_MODE_Msk (0x07UL << SCU_SFSP1_5_MODE_Pos) /*!< SCU SFSP1_5: MODE Mask */
+#define SCU_SFSP1_5_EPD_Pos 3 /*!< SCU SFSP1_5: EPD Position */
+#define SCU_SFSP1_5_EPD_Msk (0x01UL << SCU_SFSP1_5_EPD_Pos) /*!< SCU SFSP1_5: EPD Mask */
+#define SCU_SFSP1_5_EPUN_Pos 4 /*!< SCU SFSP1_5: EPUN Position */
+#define SCU_SFSP1_5_EPUN_Msk (0x01UL << SCU_SFSP1_5_EPUN_Pos) /*!< SCU SFSP1_5: EPUN Mask */
+#define SCU_SFSP1_5_EHS_Pos 5 /*!< SCU SFSP1_5: EHS Position */
+#define SCU_SFSP1_5_EHS_Msk (0x01UL << SCU_SFSP1_5_EHS_Pos) /*!< SCU SFSP1_5: EHS Mask */
+#define SCU_SFSP1_5_EZI_Pos 6 /*!< SCU SFSP1_5: EZI Position */
+#define SCU_SFSP1_5_EZI_Msk (0x01UL << SCU_SFSP1_5_EZI_Pos) /*!< SCU SFSP1_5: EZI Mask */
+#define SCU_SFSP1_5_EHD_Pos 8 /*!< SCU SFSP1_5: EHD Position */
+#define SCU_SFSP1_5_EHD_Msk (0x03UL << SCU_SFSP1_5_EHD_Pos) /*!< SCU SFSP1_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSP1_6 ------------------------------------------
+#define SCU_SFSP1_6_MODE_Pos 0 /*!< SCU SFSP1_6: MODE Position */
+#define SCU_SFSP1_6_MODE_Msk (0x07UL << SCU_SFSP1_6_MODE_Pos) /*!< SCU SFSP1_6: MODE Mask */
+#define SCU_SFSP1_6_EPD_Pos 3 /*!< SCU SFSP1_6: EPD Position */
+#define SCU_SFSP1_6_EPD_Msk (0x01UL << SCU_SFSP1_6_EPD_Pos) /*!< SCU SFSP1_6: EPD Mask */
+#define SCU_SFSP1_6_EPUN_Pos 4 /*!< SCU SFSP1_6: EPUN Position */
+#define SCU_SFSP1_6_EPUN_Msk (0x01UL << SCU_SFSP1_6_EPUN_Pos) /*!< SCU SFSP1_6: EPUN Mask */
+#define SCU_SFSP1_6_EHS_Pos 5 /*!< SCU SFSP1_6: EHS Position */
+#define SCU_SFSP1_6_EHS_Msk (0x01UL << SCU_SFSP1_6_EHS_Pos) /*!< SCU SFSP1_6: EHS Mask */
+#define SCU_SFSP1_6_EZI_Pos 6 /*!< SCU SFSP1_6: EZI Position */
+#define SCU_SFSP1_6_EZI_Msk (0x01UL << SCU_SFSP1_6_EZI_Pos) /*!< SCU SFSP1_6: EZI Mask */
+#define SCU_SFSP1_6_EHD_Pos 8 /*!< SCU SFSP1_6: EHD Position */
+#define SCU_SFSP1_6_EHD_Msk (0x03UL << SCU_SFSP1_6_EHD_Pos) /*!< SCU SFSP1_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSP1_7 ------------------------------------------
+#define SCU_SFSP1_7_MODE_Pos 0 /*!< SCU SFSP1_7: MODE Position */
+#define SCU_SFSP1_7_MODE_Msk (0x07UL << SCU_SFSP1_7_MODE_Pos) /*!< SCU SFSP1_7: MODE Mask */
+#define SCU_SFSP1_7_EPD_Pos 3 /*!< SCU SFSP1_7: EPD Position */
+#define SCU_SFSP1_7_EPD_Msk (0x01UL << SCU_SFSP1_7_EPD_Pos) /*!< SCU SFSP1_7: EPD Mask */
+#define SCU_SFSP1_7_EPUN_Pos 4 /*!< SCU SFSP1_7: EPUN Position */
+#define SCU_SFSP1_7_EPUN_Msk (0x01UL << SCU_SFSP1_7_EPUN_Pos) /*!< SCU SFSP1_7: EPUN Mask */
+#define SCU_SFSP1_7_EHS_Pos 5 /*!< SCU SFSP1_7: EHS Position */
+#define SCU_SFSP1_7_EHS_Msk (0x01UL << SCU_SFSP1_7_EHS_Pos) /*!< SCU SFSP1_7: EHS Mask */
+#define SCU_SFSP1_7_EZI_Pos 6 /*!< SCU SFSP1_7: EZI Position */
+#define SCU_SFSP1_7_EZI_Msk (0x01UL << SCU_SFSP1_7_EZI_Pos) /*!< SCU SFSP1_7: EZI Mask */
+#define SCU_SFSP1_7_EHD_Pos 8 /*!< SCU SFSP1_7: EHD Position */
+#define SCU_SFSP1_7_EHD_Msk (0x03UL << SCU_SFSP1_7_EHD_Pos) /*!< SCU SFSP1_7: EHD Mask */
+
+// --------------------------------------- SCU_SFSP1_8 ------------------------------------------
+#define SCU_SFSP1_8_MODE_Pos 0 /*!< SCU SFSP1_8: MODE Position */
+#define SCU_SFSP1_8_MODE_Msk (0x07UL << SCU_SFSP1_8_MODE_Pos) /*!< SCU SFSP1_8: MODE Mask */
+#define SCU_SFSP1_8_EPD_Pos 3 /*!< SCU SFSP1_8: EPD Position */
+#define SCU_SFSP1_8_EPD_Msk (0x01UL << SCU_SFSP1_8_EPD_Pos) /*!< SCU SFSP1_8: EPD Mask */
+#define SCU_SFSP1_8_EPUN_Pos 4 /*!< SCU SFSP1_8: EPUN Position */
+#define SCU_SFSP1_8_EPUN_Msk (0x01UL << SCU_SFSP1_8_EPUN_Pos) /*!< SCU SFSP1_8: EPUN Mask */
+#define SCU_SFSP1_8_EHS_Pos 5 /*!< SCU SFSP1_8: EHS Position */
+#define SCU_SFSP1_8_EHS_Msk (0x01UL << SCU_SFSP1_8_EHS_Pos) /*!< SCU SFSP1_8: EHS Mask */
+#define SCU_SFSP1_8_EZI_Pos 6 /*!< SCU SFSP1_8: EZI Position */
+#define SCU_SFSP1_8_EZI_Msk (0x01UL << SCU_SFSP1_8_EZI_Pos) /*!< SCU SFSP1_8: EZI Mask */
+#define SCU_SFSP1_8_EHD_Pos 8 /*!< SCU SFSP1_8: EHD Position */
+#define SCU_SFSP1_8_EHD_Msk (0x03UL << SCU_SFSP1_8_EHD_Pos) /*!< SCU SFSP1_8: EHD Mask */
+
+// --------------------------------------- SCU_SFSP1_9 ------------------------------------------
+#define SCU_SFSP1_9_MODE_Pos 0 /*!< SCU SFSP1_9: MODE Position */
+#define SCU_SFSP1_9_MODE_Msk (0x07UL << SCU_SFSP1_9_MODE_Pos) /*!< SCU SFSP1_9: MODE Mask */
+#define SCU_SFSP1_9_EPD_Pos 3 /*!< SCU SFSP1_9: EPD Position */
+#define SCU_SFSP1_9_EPD_Msk (0x01UL << SCU_SFSP1_9_EPD_Pos) /*!< SCU SFSP1_9: EPD Mask */
+#define SCU_SFSP1_9_EPUN_Pos 4 /*!< SCU SFSP1_9: EPUN Position */
+#define SCU_SFSP1_9_EPUN_Msk (0x01UL << SCU_SFSP1_9_EPUN_Pos) /*!< SCU SFSP1_9: EPUN Mask */
+#define SCU_SFSP1_9_EHS_Pos 5 /*!< SCU SFSP1_9: EHS Position */
+#define SCU_SFSP1_9_EHS_Msk (0x01UL << SCU_SFSP1_9_EHS_Pos) /*!< SCU SFSP1_9: EHS Mask */
+#define SCU_SFSP1_9_EZI_Pos 6 /*!< SCU SFSP1_9: EZI Position */
+#define SCU_SFSP1_9_EZI_Msk (0x01UL << SCU_SFSP1_9_EZI_Pos) /*!< SCU SFSP1_9: EZI Mask */
+#define SCU_SFSP1_9_EHD_Pos 8 /*!< SCU SFSP1_9: EHD Position */
+#define SCU_SFSP1_9_EHD_Msk (0x03UL << SCU_SFSP1_9_EHD_Pos) /*!< SCU SFSP1_9: EHD Mask */
+
+// -------------------------------------- SCU_SFSP1_10 ------------------------------------------
+#define SCU_SFSP1_10_MODE_Pos 0 /*!< SCU SFSP1_10: MODE Position */
+#define SCU_SFSP1_10_MODE_Msk (0x07UL << SCU_SFSP1_10_MODE_Pos) /*!< SCU SFSP1_10: MODE Mask */
+#define SCU_SFSP1_10_EPD_Pos 3 /*!< SCU SFSP1_10: EPD Position */
+#define SCU_SFSP1_10_EPD_Msk (0x01UL << SCU_SFSP1_10_EPD_Pos) /*!< SCU SFSP1_10: EPD Mask */
+#define SCU_SFSP1_10_EPUN_Pos 4 /*!< SCU SFSP1_10: EPUN Position */
+#define SCU_SFSP1_10_EPUN_Msk (0x01UL << SCU_SFSP1_10_EPUN_Pos) /*!< SCU SFSP1_10: EPUN Mask */
+#define SCU_SFSP1_10_EHS_Pos 5 /*!< SCU SFSP1_10: EHS Position */
+#define SCU_SFSP1_10_EHS_Msk (0x01UL << SCU_SFSP1_10_EHS_Pos) /*!< SCU SFSP1_10: EHS Mask */
+#define SCU_SFSP1_10_EZI_Pos 6 /*!< SCU SFSP1_10: EZI Position */
+#define SCU_SFSP1_10_EZI_Msk (0x01UL << SCU_SFSP1_10_EZI_Pos) /*!< SCU SFSP1_10: EZI Mask */
+#define SCU_SFSP1_10_EHD_Pos 8 /*!< SCU SFSP1_10: EHD Position */
+#define SCU_SFSP1_10_EHD_Msk (0x03UL << SCU_SFSP1_10_EHD_Pos) /*!< SCU SFSP1_10: EHD Mask */
+
+// -------------------------------------- SCU_SFSP1_11 ------------------------------------------
+#define SCU_SFSP1_11_MODE_Pos 0 /*!< SCU SFSP1_11: MODE Position */
+#define SCU_SFSP1_11_MODE_Msk (0x07UL << SCU_SFSP1_11_MODE_Pos) /*!< SCU SFSP1_11: MODE Mask */
+#define SCU_SFSP1_11_EPD_Pos 3 /*!< SCU SFSP1_11: EPD Position */
+#define SCU_SFSP1_11_EPD_Msk (0x01UL << SCU_SFSP1_11_EPD_Pos) /*!< SCU SFSP1_11: EPD Mask */
+#define SCU_SFSP1_11_EPUN_Pos 4 /*!< SCU SFSP1_11: EPUN Position */
+#define SCU_SFSP1_11_EPUN_Msk (0x01UL << SCU_SFSP1_11_EPUN_Pos) /*!< SCU SFSP1_11: EPUN Mask */
+#define SCU_SFSP1_11_EHS_Pos 5 /*!< SCU SFSP1_11: EHS Position */
+#define SCU_SFSP1_11_EHS_Msk (0x01UL << SCU_SFSP1_11_EHS_Pos) /*!< SCU SFSP1_11: EHS Mask */
+#define SCU_SFSP1_11_EZI_Pos 6 /*!< SCU SFSP1_11: EZI Position */
+#define SCU_SFSP1_11_EZI_Msk (0x01UL << SCU_SFSP1_11_EZI_Pos) /*!< SCU SFSP1_11: EZI Mask */
+#define SCU_SFSP1_11_EHD_Pos 8 /*!< SCU SFSP1_11: EHD Position */
+#define SCU_SFSP1_11_EHD_Msk (0x03UL << SCU_SFSP1_11_EHD_Pos) /*!< SCU SFSP1_11: EHD Mask */
+
+// -------------------------------------- SCU_SFSP1_12 ------------------------------------------
+#define SCU_SFSP1_12_MODE_Pos 0 /*!< SCU SFSP1_12: MODE Position */
+#define SCU_SFSP1_12_MODE_Msk (0x07UL << SCU_SFSP1_12_MODE_Pos) /*!< SCU SFSP1_12: MODE Mask */
+#define SCU_SFSP1_12_EPD_Pos 3 /*!< SCU SFSP1_12: EPD Position */
+#define SCU_SFSP1_12_EPD_Msk (0x01UL << SCU_SFSP1_12_EPD_Pos) /*!< SCU SFSP1_12: EPD Mask */
+#define SCU_SFSP1_12_EPUN_Pos 4 /*!< SCU SFSP1_12: EPUN Position */
+#define SCU_SFSP1_12_EPUN_Msk (0x01UL << SCU_SFSP1_12_EPUN_Pos) /*!< SCU SFSP1_12: EPUN Mask */
+#define SCU_SFSP1_12_EHS_Pos 5 /*!< SCU SFSP1_12: EHS Position */
+#define SCU_SFSP1_12_EHS_Msk (0x01UL << SCU_SFSP1_12_EHS_Pos) /*!< SCU SFSP1_12: EHS Mask */
+#define SCU_SFSP1_12_EZI_Pos 6 /*!< SCU SFSP1_12: EZI Position */
+#define SCU_SFSP1_12_EZI_Msk (0x01UL << SCU_SFSP1_12_EZI_Pos) /*!< SCU SFSP1_12: EZI Mask */
+#define SCU_SFSP1_12_EHD_Pos 8 /*!< SCU SFSP1_12: EHD Position */
+#define SCU_SFSP1_12_EHD_Msk (0x03UL << SCU_SFSP1_12_EHD_Pos) /*!< SCU SFSP1_12: EHD Mask */
+
+// -------------------------------------- SCU_SFSP1_13 ------------------------------------------
+#define SCU_SFSP1_13_MODE_Pos 0 /*!< SCU SFSP1_13: MODE Position */
+#define SCU_SFSP1_13_MODE_Msk (0x07UL << SCU_SFSP1_13_MODE_Pos) /*!< SCU SFSP1_13: MODE Mask */
+#define SCU_SFSP1_13_EPD_Pos 3 /*!< SCU SFSP1_13: EPD Position */
+#define SCU_SFSP1_13_EPD_Msk (0x01UL << SCU_SFSP1_13_EPD_Pos) /*!< SCU SFSP1_13: EPD Mask */
+#define SCU_SFSP1_13_EPUN_Pos 4 /*!< SCU SFSP1_13: EPUN Position */
+#define SCU_SFSP1_13_EPUN_Msk (0x01UL << SCU_SFSP1_13_EPUN_Pos) /*!< SCU SFSP1_13: EPUN Mask */
+#define SCU_SFSP1_13_EHS_Pos 5 /*!< SCU SFSP1_13: EHS Position */
+#define SCU_SFSP1_13_EHS_Msk (0x01UL << SCU_SFSP1_13_EHS_Pos) /*!< SCU SFSP1_13: EHS Mask */
+#define SCU_SFSP1_13_EZI_Pos 6 /*!< SCU SFSP1_13: EZI Position */
+#define SCU_SFSP1_13_EZI_Msk (0x01UL << SCU_SFSP1_13_EZI_Pos) /*!< SCU SFSP1_13: EZI Mask */
+#define SCU_SFSP1_13_EHD_Pos 8 /*!< SCU SFSP1_13: EHD Position */
+#define SCU_SFSP1_13_EHD_Msk (0x03UL << SCU_SFSP1_13_EHD_Pos) /*!< SCU SFSP1_13: EHD Mask */
+
+// -------------------------------------- SCU_SFSP1_14 ------------------------------------------
+#define SCU_SFSP1_14_MODE_Pos 0 /*!< SCU SFSP1_14: MODE Position */
+#define SCU_SFSP1_14_MODE_Msk (0x07UL << SCU_SFSP1_14_MODE_Pos) /*!< SCU SFSP1_14: MODE Mask */
+#define SCU_SFSP1_14_EPD_Pos 3 /*!< SCU SFSP1_14: EPD Position */
+#define SCU_SFSP1_14_EPD_Msk (0x01UL << SCU_SFSP1_14_EPD_Pos) /*!< SCU SFSP1_14: EPD Mask */
+#define SCU_SFSP1_14_EPUN_Pos 4 /*!< SCU SFSP1_14: EPUN Position */
+#define SCU_SFSP1_14_EPUN_Msk (0x01UL << SCU_SFSP1_14_EPUN_Pos) /*!< SCU SFSP1_14: EPUN Mask */
+#define SCU_SFSP1_14_EHS_Pos 5 /*!< SCU SFSP1_14: EHS Position */
+#define SCU_SFSP1_14_EHS_Msk (0x01UL << SCU_SFSP1_14_EHS_Pos) /*!< SCU SFSP1_14: EHS Mask */
+#define SCU_SFSP1_14_EZI_Pos 6 /*!< SCU SFSP1_14: EZI Position */
+#define SCU_SFSP1_14_EZI_Msk (0x01UL << SCU_SFSP1_14_EZI_Pos) /*!< SCU SFSP1_14: EZI Mask */
+#define SCU_SFSP1_14_EHD_Pos 8 /*!< SCU SFSP1_14: EHD Position */
+#define SCU_SFSP1_14_EHD_Msk (0x03UL << SCU_SFSP1_14_EHD_Pos) /*!< SCU SFSP1_14: EHD Mask */
+
+// -------------------------------------- SCU_SFSP1_15 ------------------------------------------
+#define SCU_SFSP1_15_MODE_Pos 0 /*!< SCU SFSP1_15: MODE Position */
+#define SCU_SFSP1_15_MODE_Msk (0x07UL << SCU_SFSP1_15_MODE_Pos) /*!< SCU SFSP1_15: MODE Mask */
+#define SCU_SFSP1_15_EPD_Pos 3 /*!< SCU SFSP1_15: EPD Position */
+#define SCU_SFSP1_15_EPD_Msk (0x01UL << SCU_SFSP1_15_EPD_Pos) /*!< SCU SFSP1_15: EPD Mask */
+#define SCU_SFSP1_15_EPUN_Pos 4 /*!< SCU SFSP1_15: EPUN Position */
+#define SCU_SFSP1_15_EPUN_Msk (0x01UL << SCU_SFSP1_15_EPUN_Pos) /*!< SCU SFSP1_15: EPUN Mask */
+#define SCU_SFSP1_15_EHS_Pos 5 /*!< SCU SFSP1_15: EHS Position */
+#define SCU_SFSP1_15_EHS_Msk (0x01UL << SCU_SFSP1_15_EHS_Pos) /*!< SCU SFSP1_15: EHS Mask */
+#define SCU_SFSP1_15_EZI_Pos 6 /*!< SCU SFSP1_15: EZI Position */
+#define SCU_SFSP1_15_EZI_Msk (0x01UL << SCU_SFSP1_15_EZI_Pos) /*!< SCU SFSP1_15: EZI Mask */
+#define SCU_SFSP1_15_EHD_Pos 8 /*!< SCU SFSP1_15: EHD Position */
+#define SCU_SFSP1_15_EHD_Msk (0x03UL << SCU_SFSP1_15_EHD_Pos) /*!< SCU SFSP1_15: EHD Mask */
+
+// -------------------------------------- SCU_SFSP1_16 ------------------------------------------
+#define SCU_SFSP1_16_MODE_Pos 0 /*!< SCU SFSP1_16: MODE Position */
+#define SCU_SFSP1_16_MODE_Msk (0x07UL << SCU_SFSP1_16_MODE_Pos) /*!< SCU SFSP1_16: MODE Mask */
+#define SCU_SFSP1_16_EPD_Pos 3 /*!< SCU SFSP1_16: EPD Position */
+#define SCU_SFSP1_16_EPD_Msk (0x01UL << SCU_SFSP1_16_EPD_Pos) /*!< SCU SFSP1_16: EPD Mask */
+#define SCU_SFSP1_16_EPUN_Pos 4 /*!< SCU SFSP1_16: EPUN Position */
+#define SCU_SFSP1_16_EPUN_Msk (0x01UL << SCU_SFSP1_16_EPUN_Pos) /*!< SCU SFSP1_16: EPUN Mask */
+#define SCU_SFSP1_16_EHS_Pos 5 /*!< SCU SFSP1_16: EHS Position */
+#define SCU_SFSP1_16_EHS_Msk (0x01UL << SCU_SFSP1_16_EHS_Pos) /*!< SCU SFSP1_16: EHS Mask */
+#define SCU_SFSP1_16_EZI_Pos 6 /*!< SCU SFSP1_16: EZI Position */
+#define SCU_SFSP1_16_EZI_Msk (0x01UL << SCU_SFSP1_16_EZI_Pos) /*!< SCU SFSP1_16: EZI Mask */
+#define SCU_SFSP1_16_EHD_Pos 8 /*!< SCU SFSP1_16: EHD Position */
+#define SCU_SFSP1_16_EHD_Msk (0x03UL << SCU_SFSP1_16_EHD_Pos) /*!< SCU SFSP1_16: EHD Mask */
+
+// -------------------------------------- SCU_SFSP1_17 ------------------------------------------
+#define SCU_SFSP1_17_MODE_Pos 0 /*!< SCU SFSP1_17: MODE Position */
+#define SCU_SFSP1_17_MODE_Msk (0x07UL << SCU_SFSP1_17_MODE_Pos) /*!< SCU SFSP1_17: MODE Mask */
+#define SCU_SFSP1_17_EPD_Pos 3 /*!< SCU SFSP1_17: EPD Position */
+#define SCU_SFSP1_17_EPD_Msk (0x01UL << SCU_SFSP1_17_EPD_Pos) /*!< SCU SFSP1_17: EPD Mask */
+#define SCU_SFSP1_17_EPUN_Pos 4 /*!< SCU SFSP1_17: EPUN Position */
+#define SCU_SFSP1_17_EPUN_Msk (0x01UL << SCU_SFSP1_17_EPUN_Pos) /*!< SCU SFSP1_17: EPUN Mask */
+#define SCU_SFSP1_17_EHS_Pos 5 /*!< SCU SFSP1_17: EHS Position */
+#define SCU_SFSP1_17_EHS_Msk (0x01UL << SCU_SFSP1_17_EHS_Pos) /*!< SCU SFSP1_17: EHS Mask */
+#define SCU_SFSP1_17_EZI_Pos 6 /*!< SCU SFSP1_17: EZI Position */
+#define SCU_SFSP1_17_EZI_Msk (0x01UL << SCU_SFSP1_17_EZI_Pos) /*!< SCU SFSP1_17: EZI Mask */
+#define SCU_SFSP1_17_EHD_Pos 8 /*!< SCU SFSP1_17: EHD Position */
+#define SCU_SFSP1_17_EHD_Msk (0x03UL << SCU_SFSP1_17_EHD_Pos) /*!< SCU SFSP1_17: EHD Mask */
+
+// -------------------------------------- SCU_SFSP1_18 ------------------------------------------
+#define SCU_SFSP1_18_MODE_Pos 0 /*!< SCU SFSP1_18: MODE Position */
+#define SCU_SFSP1_18_MODE_Msk (0x07UL << SCU_SFSP1_18_MODE_Pos) /*!< SCU SFSP1_18: MODE Mask */
+#define SCU_SFSP1_18_EPD_Pos 3 /*!< SCU SFSP1_18: EPD Position */
+#define SCU_SFSP1_18_EPD_Msk (0x01UL << SCU_SFSP1_18_EPD_Pos) /*!< SCU SFSP1_18: EPD Mask */
+#define SCU_SFSP1_18_EPUN_Pos 4 /*!< SCU SFSP1_18: EPUN Position */
+#define SCU_SFSP1_18_EPUN_Msk (0x01UL << SCU_SFSP1_18_EPUN_Pos) /*!< SCU SFSP1_18: EPUN Mask */
+#define SCU_SFSP1_18_EHS_Pos 5 /*!< SCU SFSP1_18: EHS Position */
+#define SCU_SFSP1_18_EHS_Msk (0x01UL << SCU_SFSP1_18_EHS_Pos) /*!< SCU SFSP1_18: EHS Mask */
+#define SCU_SFSP1_18_EZI_Pos 6 /*!< SCU SFSP1_18: EZI Position */
+#define SCU_SFSP1_18_EZI_Msk (0x01UL << SCU_SFSP1_18_EZI_Pos) /*!< SCU SFSP1_18: EZI Mask */
+#define SCU_SFSP1_18_EHD_Pos 8 /*!< SCU SFSP1_18: EHD Position */
+#define SCU_SFSP1_18_EHD_Msk (0x03UL << SCU_SFSP1_18_EHD_Pos) /*!< SCU SFSP1_18: EHD Mask */
+
+// -------------------------------------- SCU_SFSP1_19 ------------------------------------------
+#define SCU_SFSP1_19_MODE_Pos 0 /*!< SCU SFSP1_19: MODE Position */
+#define SCU_SFSP1_19_MODE_Msk (0x07UL << SCU_SFSP1_19_MODE_Pos) /*!< SCU SFSP1_19: MODE Mask */
+#define SCU_SFSP1_19_EPD_Pos 3 /*!< SCU SFSP1_19: EPD Position */
+#define SCU_SFSP1_19_EPD_Msk (0x01UL << SCU_SFSP1_19_EPD_Pos) /*!< SCU SFSP1_19: EPD Mask */
+#define SCU_SFSP1_19_EPUN_Pos 4 /*!< SCU SFSP1_19: EPUN Position */
+#define SCU_SFSP1_19_EPUN_Msk (0x01UL << SCU_SFSP1_19_EPUN_Pos) /*!< SCU SFSP1_19: EPUN Mask */
+#define SCU_SFSP1_19_EHS_Pos 5 /*!< SCU SFSP1_19: EHS Position */
+#define SCU_SFSP1_19_EHS_Msk (0x01UL << SCU_SFSP1_19_EHS_Pos) /*!< SCU SFSP1_19: EHS Mask */
+#define SCU_SFSP1_19_EZI_Pos 6 /*!< SCU SFSP1_19: EZI Position */
+#define SCU_SFSP1_19_EZI_Msk (0x01UL << SCU_SFSP1_19_EZI_Pos) /*!< SCU SFSP1_19: EZI Mask */
+#define SCU_SFSP1_19_EHD_Pos 8 /*!< SCU SFSP1_19: EHD Position */
+#define SCU_SFSP1_19_EHD_Msk (0x03UL << SCU_SFSP1_19_EHD_Pos) /*!< SCU SFSP1_19: EHD Mask */
+
+// -------------------------------------- SCU_SFSP1_20 ------------------------------------------
+#define SCU_SFSP1_20_MODE_Pos 0 /*!< SCU SFSP1_20: MODE Position */
+#define SCU_SFSP1_20_MODE_Msk (0x07UL << SCU_SFSP1_20_MODE_Pos) /*!< SCU SFSP1_20: MODE Mask */
+#define SCU_SFSP1_20_EPD_Pos 3 /*!< SCU SFSP1_20: EPD Position */
+#define SCU_SFSP1_20_EPD_Msk (0x01UL << SCU_SFSP1_20_EPD_Pos) /*!< SCU SFSP1_20: EPD Mask */
+#define SCU_SFSP1_20_EPUN_Pos 4 /*!< SCU SFSP1_20: EPUN Position */
+#define SCU_SFSP1_20_EPUN_Msk (0x01UL << SCU_SFSP1_20_EPUN_Pos) /*!< SCU SFSP1_20: EPUN Mask */
+#define SCU_SFSP1_20_EHS_Pos 5 /*!< SCU SFSP1_20: EHS Position */
+#define SCU_SFSP1_20_EHS_Msk (0x01UL << SCU_SFSP1_20_EHS_Pos) /*!< SCU SFSP1_20: EHS Mask */
+#define SCU_SFSP1_20_EZI_Pos 6 /*!< SCU SFSP1_20: EZI Position */
+#define SCU_SFSP1_20_EZI_Msk (0x01UL << SCU_SFSP1_20_EZI_Pos) /*!< SCU SFSP1_20: EZI Mask */
+#define SCU_SFSP1_20_EHD_Pos 8 /*!< SCU SFSP1_20: EHD Position */
+#define SCU_SFSP1_20_EHD_Msk (0x03UL << SCU_SFSP1_20_EHD_Pos) /*!< SCU SFSP1_20: EHD Mask */
+
+// --------------------------------------- SCU_SFSP2_0 ------------------------------------------
+#define SCU_SFSP2_0_MODE_Pos 0 /*!< SCU SFSP2_0: MODE Position */
+#define SCU_SFSP2_0_MODE_Msk (0x07UL << SCU_SFSP2_0_MODE_Pos) /*!< SCU SFSP2_0: MODE Mask */
+#define SCU_SFSP2_0_EPD_Pos 3 /*!< SCU SFSP2_0: EPD Position */
+#define SCU_SFSP2_0_EPD_Msk (0x01UL << SCU_SFSP2_0_EPD_Pos) /*!< SCU SFSP2_0: EPD Mask */
+#define SCU_SFSP2_0_EPUN_Pos 4 /*!< SCU SFSP2_0: EPUN Position */
+#define SCU_SFSP2_0_EPUN_Msk (0x01UL << SCU_SFSP2_0_EPUN_Pos) /*!< SCU SFSP2_0: EPUN Mask */
+#define SCU_SFSP2_0_EHS_Pos 5 /*!< SCU SFSP2_0: EHS Position */
+#define SCU_SFSP2_0_EHS_Msk (0x01UL << SCU_SFSP2_0_EHS_Pos) /*!< SCU SFSP2_0: EHS Mask */
+#define SCU_SFSP2_0_EZI_Pos 6 /*!< SCU SFSP2_0: EZI Position */
+#define SCU_SFSP2_0_EZI_Msk (0x01UL << SCU_SFSP2_0_EZI_Pos) /*!< SCU SFSP2_0: EZI Mask */
+#define SCU_SFSP2_0_EHD_Pos 8 /*!< SCU SFSP2_0: EHD Position */
+#define SCU_SFSP2_0_EHD_Msk (0x03UL << SCU_SFSP2_0_EHD_Pos) /*!< SCU SFSP2_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSP2_1 ------------------------------------------
+#define SCU_SFSP2_1_MODE_Pos 0 /*!< SCU SFSP2_1: MODE Position */
+#define SCU_SFSP2_1_MODE_Msk (0x07UL << SCU_SFSP2_1_MODE_Pos) /*!< SCU SFSP2_1: MODE Mask */
+#define SCU_SFSP2_1_EPD_Pos 3 /*!< SCU SFSP2_1: EPD Position */
+#define SCU_SFSP2_1_EPD_Msk (0x01UL << SCU_SFSP2_1_EPD_Pos) /*!< SCU SFSP2_1: EPD Mask */
+#define SCU_SFSP2_1_EPUN_Pos 4 /*!< SCU SFSP2_1: EPUN Position */
+#define SCU_SFSP2_1_EPUN_Msk (0x01UL << SCU_SFSP2_1_EPUN_Pos) /*!< SCU SFSP2_1: EPUN Mask */
+#define SCU_SFSP2_1_EHS_Pos 5 /*!< SCU SFSP2_1: EHS Position */
+#define SCU_SFSP2_1_EHS_Msk (0x01UL << SCU_SFSP2_1_EHS_Pos) /*!< SCU SFSP2_1: EHS Mask */
+#define SCU_SFSP2_1_EZI_Pos 6 /*!< SCU SFSP2_1: EZI Position */
+#define SCU_SFSP2_1_EZI_Msk (0x01UL << SCU_SFSP2_1_EZI_Pos) /*!< SCU SFSP2_1: EZI Mask */
+#define SCU_SFSP2_1_EHD_Pos 8 /*!< SCU SFSP2_1: EHD Position */
+#define SCU_SFSP2_1_EHD_Msk (0x03UL << SCU_SFSP2_1_EHD_Pos) /*!< SCU SFSP2_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSP2_2 ------------------------------------------
+#define SCU_SFSP2_2_MODE_Pos 0 /*!< SCU SFSP2_2: MODE Position */
+#define SCU_SFSP2_2_MODE_Msk (0x07UL << SCU_SFSP2_2_MODE_Pos) /*!< SCU SFSP2_2: MODE Mask */
+#define SCU_SFSP2_2_EPD_Pos 3 /*!< SCU SFSP2_2: EPD Position */
+#define SCU_SFSP2_2_EPD_Msk (0x01UL << SCU_SFSP2_2_EPD_Pos) /*!< SCU SFSP2_2: EPD Mask */
+#define SCU_SFSP2_2_EPUN_Pos 4 /*!< SCU SFSP2_2: EPUN Position */
+#define SCU_SFSP2_2_EPUN_Msk (0x01UL << SCU_SFSP2_2_EPUN_Pos) /*!< SCU SFSP2_2: EPUN Mask */
+#define SCU_SFSP2_2_EHS_Pos 5 /*!< SCU SFSP2_2: EHS Position */
+#define SCU_SFSP2_2_EHS_Msk (0x01UL << SCU_SFSP2_2_EHS_Pos) /*!< SCU SFSP2_2: EHS Mask */
+#define SCU_SFSP2_2_EZI_Pos 6 /*!< SCU SFSP2_2: EZI Position */
+#define SCU_SFSP2_2_EZI_Msk (0x01UL << SCU_SFSP2_2_EZI_Pos) /*!< SCU SFSP2_2: EZI Mask */
+#define SCU_SFSP2_2_EHD_Pos 8 /*!< SCU SFSP2_2: EHD Position */
+#define SCU_SFSP2_2_EHD_Msk (0x03UL << SCU_SFSP2_2_EHD_Pos) /*!< SCU SFSP2_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSP2_3 ------------------------------------------
+#define SCU_SFSP2_3_MODE_Pos 0 /*!< SCU SFSP2_3: MODE Position */
+#define SCU_SFSP2_3_MODE_Msk (0x07UL << SCU_SFSP2_3_MODE_Pos) /*!< SCU SFSP2_3: MODE Mask */
+#define SCU_SFSP2_3_EPD_Pos 3 /*!< SCU SFSP2_3: EPD Position */
+#define SCU_SFSP2_3_EPD_Msk (0x01UL << SCU_SFSP2_3_EPD_Pos) /*!< SCU SFSP2_3: EPD Mask */
+#define SCU_SFSP2_3_EPUN_Pos 4 /*!< SCU SFSP2_3: EPUN Position */
+#define SCU_SFSP2_3_EPUN_Msk (0x01UL << SCU_SFSP2_3_EPUN_Pos) /*!< SCU SFSP2_3: EPUN Mask */
+#define SCU_SFSP2_3_EHS_Pos 5 /*!< SCU SFSP2_3: EHS Position */
+#define SCU_SFSP2_3_EHS_Msk (0x01UL << SCU_SFSP2_3_EHS_Pos) /*!< SCU SFSP2_3: EHS Mask */
+#define SCU_SFSP2_3_EZI_Pos 6 /*!< SCU SFSP2_3: EZI Position */
+#define SCU_SFSP2_3_EZI_Msk (0x01UL << SCU_SFSP2_3_EZI_Pos) /*!< SCU SFSP2_3: EZI Mask */
+#define SCU_SFSP2_3_EHD_Pos 8 /*!< SCU SFSP2_3: EHD Position */
+#define SCU_SFSP2_3_EHD_Msk (0x03UL << SCU_SFSP2_3_EHD_Pos) /*!< SCU SFSP2_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSP2_4 ------------------------------------------
+#define SCU_SFSP2_4_MODE_Pos 0 /*!< SCU SFSP2_4: MODE Position */
+#define SCU_SFSP2_4_MODE_Msk (0x07UL << SCU_SFSP2_4_MODE_Pos) /*!< SCU SFSP2_4: MODE Mask */
+#define SCU_SFSP2_4_EPD_Pos 3 /*!< SCU SFSP2_4: EPD Position */
+#define SCU_SFSP2_4_EPD_Msk (0x01UL << SCU_SFSP2_4_EPD_Pos) /*!< SCU SFSP2_4: EPD Mask */
+#define SCU_SFSP2_4_EPUN_Pos 4 /*!< SCU SFSP2_4: EPUN Position */
+#define SCU_SFSP2_4_EPUN_Msk (0x01UL << SCU_SFSP2_4_EPUN_Pos) /*!< SCU SFSP2_4: EPUN Mask */
+#define SCU_SFSP2_4_EHS_Pos 5 /*!< SCU SFSP2_4: EHS Position */
+#define SCU_SFSP2_4_EHS_Msk (0x01UL << SCU_SFSP2_4_EHS_Pos) /*!< SCU SFSP2_4: EHS Mask */
+#define SCU_SFSP2_4_EZI_Pos 6 /*!< SCU SFSP2_4: EZI Position */
+#define SCU_SFSP2_4_EZI_Msk (0x01UL << SCU_SFSP2_4_EZI_Pos) /*!< SCU SFSP2_4: EZI Mask */
+#define SCU_SFSP2_4_EHD_Pos 8 /*!< SCU SFSP2_4: EHD Position */
+#define SCU_SFSP2_4_EHD_Msk (0x03UL << SCU_SFSP2_4_EHD_Pos) /*!< SCU SFSP2_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSP2_5 ------------------------------------------
+#define SCU_SFSP2_5_MODE_Pos 0 /*!< SCU SFSP2_5: MODE Position */
+#define SCU_SFSP2_5_MODE_Msk (0x07UL << SCU_SFSP2_5_MODE_Pos) /*!< SCU SFSP2_5: MODE Mask */
+#define SCU_SFSP2_5_EPD_Pos 3 /*!< SCU SFSP2_5: EPD Position */
+#define SCU_SFSP2_5_EPD_Msk (0x01UL << SCU_SFSP2_5_EPD_Pos) /*!< SCU SFSP2_5: EPD Mask */
+#define SCU_SFSP2_5_EPUN_Pos 4 /*!< SCU SFSP2_5: EPUN Position */
+#define SCU_SFSP2_5_EPUN_Msk (0x01UL << SCU_SFSP2_5_EPUN_Pos) /*!< SCU SFSP2_5: EPUN Mask */
+#define SCU_SFSP2_5_EHS_Pos 5 /*!< SCU SFSP2_5: EHS Position */
+#define SCU_SFSP2_5_EHS_Msk (0x01UL << SCU_SFSP2_5_EHS_Pos) /*!< SCU SFSP2_5: EHS Mask */
+#define SCU_SFSP2_5_EZI_Pos 6 /*!< SCU SFSP2_5: EZI Position */
+#define SCU_SFSP2_5_EZI_Msk (0x01UL << SCU_SFSP2_5_EZI_Pos) /*!< SCU SFSP2_5: EZI Mask */
+#define SCU_SFSP2_5_EHD_Pos 8 /*!< SCU SFSP2_5: EHD Position */
+#define SCU_SFSP2_5_EHD_Msk (0x03UL << SCU_SFSP2_5_EHD_Pos) /*!< SCU SFSP2_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSP2_6 ------------------------------------------
+#define SCU_SFSP2_6_MODE_Pos 0 /*!< SCU SFSP2_6: MODE Position */
+#define SCU_SFSP2_6_MODE_Msk (0x07UL << SCU_SFSP2_6_MODE_Pos) /*!< SCU SFSP2_6: MODE Mask */
+#define SCU_SFSP2_6_EPD_Pos 3 /*!< SCU SFSP2_6: EPD Position */
+#define SCU_SFSP2_6_EPD_Msk (0x01UL << SCU_SFSP2_6_EPD_Pos) /*!< SCU SFSP2_6: EPD Mask */
+#define SCU_SFSP2_6_EPUN_Pos 4 /*!< SCU SFSP2_6: EPUN Position */
+#define SCU_SFSP2_6_EPUN_Msk (0x01UL << SCU_SFSP2_6_EPUN_Pos) /*!< SCU SFSP2_6: EPUN Mask */
+#define SCU_SFSP2_6_EHS_Pos 5 /*!< SCU SFSP2_6: EHS Position */
+#define SCU_SFSP2_6_EHS_Msk (0x01UL << SCU_SFSP2_6_EHS_Pos) /*!< SCU SFSP2_6: EHS Mask */
+#define SCU_SFSP2_6_EZI_Pos 6 /*!< SCU SFSP2_6: EZI Position */
+#define SCU_SFSP2_6_EZI_Msk (0x01UL << SCU_SFSP2_6_EZI_Pos) /*!< SCU SFSP2_6: EZI Mask */
+#define SCU_SFSP2_6_EHD_Pos 8 /*!< SCU SFSP2_6: EHD Position */
+#define SCU_SFSP2_6_EHD_Msk (0x03UL << SCU_SFSP2_6_EHD_Pos) /*!< SCU SFSP2_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSP2_7 ------------------------------------------
+#define SCU_SFSP2_7_MODE_Pos 0 /*!< SCU SFSP2_7: MODE Position */
+#define SCU_SFSP2_7_MODE_Msk (0x07UL << SCU_SFSP2_7_MODE_Pos) /*!< SCU SFSP2_7: MODE Mask */
+#define SCU_SFSP2_7_EPD_Pos 3 /*!< SCU SFSP2_7: EPD Position */
+#define SCU_SFSP2_7_EPD_Msk (0x01UL << SCU_SFSP2_7_EPD_Pos) /*!< SCU SFSP2_7: EPD Mask */
+#define SCU_SFSP2_7_EPUN_Pos 4 /*!< SCU SFSP2_7: EPUN Position */
+#define SCU_SFSP2_7_EPUN_Msk (0x01UL << SCU_SFSP2_7_EPUN_Pos) /*!< SCU SFSP2_7: EPUN Mask */
+#define SCU_SFSP2_7_EHS_Pos 5 /*!< SCU SFSP2_7: EHS Position */
+#define SCU_SFSP2_7_EHS_Msk (0x01UL << SCU_SFSP2_7_EHS_Pos) /*!< SCU SFSP2_7: EHS Mask */
+#define SCU_SFSP2_7_EZI_Pos 6 /*!< SCU SFSP2_7: EZI Position */
+#define SCU_SFSP2_7_EZI_Msk (0x01UL << SCU_SFSP2_7_EZI_Pos) /*!< SCU SFSP2_7: EZI Mask */
+#define SCU_SFSP2_7_EHD_Pos 8 /*!< SCU SFSP2_7: EHD Position */
+#define SCU_SFSP2_7_EHD_Msk (0x03UL << SCU_SFSP2_7_EHD_Pos) /*!< SCU SFSP2_7: EHD Mask */
+
+// --------------------------------------- SCU_SFSP2_8 ------------------------------------------
+#define SCU_SFSP2_8_MODE_Pos 0 /*!< SCU SFSP2_8: MODE Position */
+#define SCU_SFSP2_8_MODE_Msk (0x07UL << SCU_SFSP2_8_MODE_Pos) /*!< SCU SFSP2_8: MODE Mask */
+#define SCU_SFSP2_8_EPD_Pos 3 /*!< SCU SFSP2_8: EPD Position */
+#define SCU_SFSP2_8_EPD_Msk (0x01UL << SCU_SFSP2_8_EPD_Pos) /*!< SCU SFSP2_8: EPD Mask */
+#define SCU_SFSP2_8_EPUN_Pos 4 /*!< SCU SFSP2_8: EPUN Position */
+#define SCU_SFSP2_8_EPUN_Msk (0x01UL << SCU_SFSP2_8_EPUN_Pos) /*!< SCU SFSP2_8: EPUN Mask */
+#define SCU_SFSP2_8_EHS_Pos 5 /*!< SCU SFSP2_8: EHS Position */
+#define SCU_SFSP2_8_EHS_Msk (0x01UL << SCU_SFSP2_8_EHS_Pos) /*!< SCU SFSP2_8: EHS Mask */
+#define SCU_SFSP2_8_EZI_Pos 6 /*!< SCU SFSP2_8: EZI Position */
+#define SCU_SFSP2_8_EZI_Msk (0x01UL << SCU_SFSP2_8_EZI_Pos) /*!< SCU SFSP2_8: EZI Mask */
+#define SCU_SFSP2_8_EHD_Pos 8 /*!< SCU SFSP2_8: EHD Position */
+#define SCU_SFSP2_8_EHD_Msk (0x03UL << SCU_SFSP2_8_EHD_Pos) /*!< SCU SFSP2_8: EHD Mask */
+
+// --------------------------------------- SCU_SFSP2_9 ------------------------------------------
+#define SCU_SFSP2_9_MODE_Pos 0 /*!< SCU SFSP2_9: MODE Position */
+#define SCU_SFSP2_9_MODE_Msk (0x07UL << SCU_SFSP2_9_MODE_Pos) /*!< SCU SFSP2_9: MODE Mask */
+#define SCU_SFSP2_9_EPD_Pos 3 /*!< SCU SFSP2_9: EPD Position */
+#define SCU_SFSP2_9_EPD_Msk (0x01UL << SCU_SFSP2_9_EPD_Pos) /*!< SCU SFSP2_9: EPD Mask */
+#define SCU_SFSP2_9_EPUN_Pos 4 /*!< SCU SFSP2_9: EPUN Position */
+#define SCU_SFSP2_9_EPUN_Msk (0x01UL << SCU_SFSP2_9_EPUN_Pos) /*!< SCU SFSP2_9: EPUN Mask */
+#define SCU_SFSP2_9_EHS_Pos 5 /*!< SCU SFSP2_9: EHS Position */
+#define SCU_SFSP2_9_EHS_Msk (0x01UL << SCU_SFSP2_9_EHS_Pos) /*!< SCU SFSP2_9: EHS Mask */
+#define SCU_SFSP2_9_EZI_Pos 6 /*!< SCU SFSP2_9: EZI Position */
+#define SCU_SFSP2_9_EZI_Msk (0x01UL << SCU_SFSP2_9_EZI_Pos) /*!< SCU SFSP2_9: EZI Mask */
+#define SCU_SFSP2_9_EHD_Pos 8 /*!< SCU SFSP2_9: EHD Position */
+#define SCU_SFSP2_9_EHD_Msk (0x03UL << SCU_SFSP2_9_EHD_Pos) /*!< SCU SFSP2_9: EHD Mask */
+
+// -------------------------------------- SCU_SFSP2_10 ------------------------------------------
+#define SCU_SFSP2_10_MODE_Pos 0 /*!< SCU SFSP2_10: MODE Position */
+#define SCU_SFSP2_10_MODE_Msk (0x07UL << SCU_SFSP2_10_MODE_Pos) /*!< SCU SFSP2_10: MODE Mask */
+#define SCU_SFSP2_10_EPD_Pos 3 /*!< SCU SFSP2_10: EPD Position */
+#define SCU_SFSP2_10_EPD_Msk (0x01UL << SCU_SFSP2_10_EPD_Pos) /*!< SCU SFSP2_10: EPD Mask */
+#define SCU_SFSP2_10_EPUN_Pos 4 /*!< SCU SFSP2_10: EPUN Position */
+#define SCU_SFSP2_10_EPUN_Msk (0x01UL << SCU_SFSP2_10_EPUN_Pos) /*!< SCU SFSP2_10: EPUN Mask */
+#define SCU_SFSP2_10_EHS_Pos 5 /*!< SCU SFSP2_10: EHS Position */
+#define SCU_SFSP2_10_EHS_Msk (0x01UL << SCU_SFSP2_10_EHS_Pos) /*!< SCU SFSP2_10: EHS Mask */
+#define SCU_SFSP2_10_EZI_Pos 6 /*!< SCU SFSP2_10: EZI Position */
+#define SCU_SFSP2_10_EZI_Msk (0x01UL << SCU_SFSP2_10_EZI_Pos) /*!< SCU SFSP2_10: EZI Mask */
+#define SCU_SFSP2_10_EHD_Pos 8 /*!< SCU SFSP2_10: EHD Position */
+#define SCU_SFSP2_10_EHD_Msk (0x03UL << SCU_SFSP2_10_EHD_Pos) /*!< SCU SFSP2_10: EHD Mask */
+
+// -------------------------------------- SCU_SFSP2_11 ------------------------------------------
+#define SCU_SFSP2_11_MODE_Pos 0 /*!< SCU SFSP2_11: MODE Position */
+#define SCU_SFSP2_11_MODE_Msk (0x07UL << SCU_SFSP2_11_MODE_Pos) /*!< SCU SFSP2_11: MODE Mask */
+#define SCU_SFSP2_11_EPD_Pos 3 /*!< SCU SFSP2_11: EPD Position */
+#define SCU_SFSP2_11_EPD_Msk (0x01UL << SCU_SFSP2_11_EPD_Pos) /*!< SCU SFSP2_11: EPD Mask */
+#define SCU_SFSP2_11_EPUN_Pos 4 /*!< SCU SFSP2_11: EPUN Position */
+#define SCU_SFSP2_11_EPUN_Msk (0x01UL << SCU_SFSP2_11_EPUN_Pos) /*!< SCU SFSP2_11: EPUN Mask */
+#define SCU_SFSP2_11_EHS_Pos 5 /*!< SCU SFSP2_11: EHS Position */
+#define SCU_SFSP2_11_EHS_Msk (0x01UL << SCU_SFSP2_11_EHS_Pos) /*!< SCU SFSP2_11: EHS Mask */
+#define SCU_SFSP2_11_EZI_Pos 6 /*!< SCU SFSP2_11: EZI Position */
+#define SCU_SFSP2_11_EZI_Msk (0x01UL << SCU_SFSP2_11_EZI_Pos) /*!< SCU SFSP2_11: EZI Mask */
+#define SCU_SFSP2_11_EHD_Pos 8 /*!< SCU SFSP2_11: EHD Position */
+#define SCU_SFSP2_11_EHD_Msk (0x03UL << SCU_SFSP2_11_EHD_Pos) /*!< SCU SFSP2_11: EHD Mask */
+
+// -------------------------------------- SCU_SFSP2_12 ------------------------------------------
+#define SCU_SFSP2_12_MODE_Pos 0 /*!< SCU SFSP2_12: MODE Position */
+#define SCU_SFSP2_12_MODE_Msk (0x07UL << SCU_SFSP2_12_MODE_Pos) /*!< SCU SFSP2_12: MODE Mask */
+#define SCU_SFSP2_12_EPD_Pos 3 /*!< SCU SFSP2_12: EPD Position */
+#define SCU_SFSP2_12_EPD_Msk (0x01UL << SCU_SFSP2_12_EPD_Pos) /*!< SCU SFSP2_12: EPD Mask */
+#define SCU_SFSP2_12_EPUN_Pos 4 /*!< SCU SFSP2_12: EPUN Position */
+#define SCU_SFSP2_12_EPUN_Msk (0x01UL << SCU_SFSP2_12_EPUN_Pos) /*!< SCU SFSP2_12: EPUN Mask */
+#define SCU_SFSP2_12_EHS_Pos 5 /*!< SCU SFSP2_12: EHS Position */
+#define SCU_SFSP2_12_EHS_Msk (0x01UL << SCU_SFSP2_12_EHS_Pos) /*!< SCU SFSP2_12: EHS Mask */
+#define SCU_SFSP2_12_EZI_Pos 6 /*!< SCU SFSP2_12: EZI Position */
+#define SCU_SFSP2_12_EZI_Msk (0x01UL << SCU_SFSP2_12_EZI_Pos) /*!< SCU SFSP2_12: EZI Mask */
+#define SCU_SFSP2_12_EHD_Pos 8 /*!< SCU SFSP2_12: EHD Position */
+#define SCU_SFSP2_12_EHD_Msk (0x03UL << SCU_SFSP2_12_EHD_Pos) /*!< SCU SFSP2_12: EHD Mask */
+
+// -------------------------------------- SCU_SFSP2_13 ------------------------------------------
+#define SCU_SFSP2_13_MODE_Pos 0 /*!< SCU SFSP2_13: MODE Position */
+#define SCU_SFSP2_13_MODE_Msk (0x07UL << SCU_SFSP2_13_MODE_Pos) /*!< SCU SFSP2_13: MODE Mask */
+#define SCU_SFSP2_13_EPD_Pos 3 /*!< SCU SFSP2_13: EPD Position */
+#define SCU_SFSP2_13_EPD_Msk (0x01UL << SCU_SFSP2_13_EPD_Pos) /*!< SCU SFSP2_13: EPD Mask */
+#define SCU_SFSP2_13_EPUN_Pos 4 /*!< SCU SFSP2_13: EPUN Position */
+#define SCU_SFSP2_13_EPUN_Msk (0x01UL << SCU_SFSP2_13_EPUN_Pos) /*!< SCU SFSP2_13: EPUN Mask */
+#define SCU_SFSP2_13_EHS_Pos 5 /*!< SCU SFSP2_13: EHS Position */
+#define SCU_SFSP2_13_EHS_Msk (0x01UL << SCU_SFSP2_13_EHS_Pos) /*!< SCU SFSP2_13: EHS Mask */
+#define SCU_SFSP2_13_EZI_Pos 6 /*!< SCU SFSP2_13: EZI Position */
+#define SCU_SFSP2_13_EZI_Msk (0x01UL << SCU_SFSP2_13_EZI_Pos) /*!< SCU SFSP2_13: EZI Mask */
+#define SCU_SFSP2_13_EHD_Pos 8 /*!< SCU SFSP2_13: EHD Position */
+#define SCU_SFSP2_13_EHD_Msk (0x03UL << SCU_SFSP2_13_EHD_Pos) /*!< SCU SFSP2_13: EHD Mask */
+
+// --------------------------------------- SCU_SFSP3_0 ------------------------------------------
+#define SCU_SFSP3_0_MODE_Pos 0 /*!< SCU SFSP3_0: MODE Position */
+#define SCU_SFSP3_0_MODE_Msk (0x07UL << SCU_SFSP3_0_MODE_Pos) /*!< SCU SFSP3_0: MODE Mask */
+#define SCU_SFSP3_0_EPD_Pos 3 /*!< SCU SFSP3_0: EPD Position */
+#define SCU_SFSP3_0_EPD_Msk (0x01UL << SCU_SFSP3_0_EPD_Pos) /*!< SCU SFSP3_0: EPD Mask */
+#define SCU_SFSP3_0_EPUN_Pos 4 /*!< SCU SFSP3_0: EPUN Position */
+#define SCU_SFSP3_0_EPUN_Msk (0x01UL << SCU_SFSP3_0_EPUN_Pos) /*!< SCU SFSP3_0: EPUN Mask */
+#define SCU_SFSP3_0_EHS_Pos 5 /*!< SCU SFSP3_0: EHS Position */
+#define SCU_SFSP3_0_EHS_Msk (0x01UL << SCU_SFSP3_0_EHS_Pos) /*!< SCU SFSP3_0: EHS Mask */
+#define SCU_SFSP3_0_EZI_Pos 6 /*!< SCU SFSP3_0: EZI Position */
+#define SCU_SFSP3_0_EZI_Msk (0x01UL << SCU_SFSP3_0_EZI_Pos) /*!< SCU SFSP3_0: EZI Mask */
+#define SCU_SFSP3_0_EHD_Pos 8 /*!< SCU SFSP3_0: EHD Position */
+#define SCU_SFSP3_0_EHD_Msk (0x03UL << SCU_SFSP3_0_EHD_Pos) /*!< SCU SFSP3_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSP3_1 ------------------------------------------
+#define SCU_SFSP3_1_MODE_Pos 0 /*!< SCU SFSP3_1: MODE Position */
+#define SCU_SFSP3_1_MODE_Msk (0x07UL << SCU_SFSP3_1_MODE_Pos) /*!< SCU SFSP3_1: MODE Mask */
+#define SCU_SFSP3_1_EPD_Pos 3 /*!< SCU SFSP3_1: EPD Position */
+#define SCU_SFSP3_1_EPD_Msk (0x01UL << SCU_SFSP3_1_EPD_Pos) /*!< SCU SFSP3_1: EPD Mask */
+#define SCU_SFSP3_1_EPUN_Pos 4 /*!< SCU SFSP3_1: EPUN Position */
+#define SCU_SFSP3_1_EPUN_Msk (0x01UL << SCU_SFSP3_1_EPUN_Pos) /*!< SCU SFSP3_1: EPUN Mask */
+#define SCU_SFSP3_1_EHS_Pos 5 /*!< SCU SFSP3_1: EHS Position */
+#define SCU_SFSP3_1_EHS_Msk (0x01UL << SCU_SFSP3_1_EHS_Pos) /*!< SCU SFSP3_1: EHS Mask */
+#define SCU_SFSP3_1_EZI_Pos 6 /*!< SCU SFSP3_1: EZI Position */
+#define SCU_SFSP3_1_EZI_Msk (0x01UL << SCU_SFSP3_1_EZI_Pos) /*!< SCU SFSP3_1: EZI Mask */
+#define SCU_SFSP3_1_EHD_Pos 8 /*!< SCU SFSP3_1: EHD Position */
+#define SCU_SFSP3_1_EHD_Msk (0x03UL << SCU_SFSP3_1_EHD_Pos) /*!< SCU SFSP3_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSP3_2 ------------------------------------------
+#define SCU_SFSP3_2_MODE_Pos 0 /*!< SCU SFSP3_2: MODE Position */
+#define SCU_SFSP3_2_MODE_Msk (0x07UL << SCU_SFSP3_2_MODE_Pos) /*!< SCU SFSP3_2: MODE Mask */
+#define SCU_SFSP3_2_EPD_Pos 3 /*!< SCU SFSP3_2: EPD Position */
+#define SCU_SFSP3_2_EPD_Msk (0x01UL << SCU_SFSP3_2_EPD_Pos) /*!< SCU SFSP3_2: EPD Mask */
+#define SCU_SFSP3_2_EPUN_Pos 4 /*!< SCU SFSP3_2: EPUN Position */
+#define SCU_SFSP3_2_EPUN_Msk (0x01UL << SCU_SFSP3_2_EPUN_Pos) /*!< SCU SFSP3_2: EPUN Mask */
+#define SCU_SFSP3_2_EHS_Pos 5 /*!< SCU SFSP3_2: EHS Position */
+#define SCU_SFSP3_2_EHS_Msk (0x01UL << SCU_SFSP3_2_EHS_Pos) /*!< SCU SFSP3_2: EHS Mask */
+#define SCU_SFSP3_2_EZI_Pos 6 /*!< SCU SFSP3_2: EZI Position */
+#define SCU_SFSP3_2_EZI_Msk (0x01UL << SCU_SFSP3_2_EZI_Pos) /*!< SCU SFSP3_2: EZI Mask */
+#define SCU_SFSP3_2_EHD_Pos 8 /*!< SCU SFSP3_2: EHD Position */
+#define SCU_SFSP3_2_EHD_Msk (0x03UL << SCU_SFSP3_2_EHD_Pos) /*!< SCU SFSP3_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSP3_3 ------------------------------------------
+#define SCU_SFSP3_3_MODE_Pos 0 /*!< SCU SFSP3_3: MODE Position */
+#define SCU_SFSP3_3_MODE_Msk (0x07UL << SCU_SFSP3_3_MODE_Pos) /*!< SCU SFSP3_3: MODE Mask */
+#define SCU_SFSP3_3_EPD_Pos 3 /*!< SCU SFSP3_3: EPD Position */
+#define SCU_SFSP3_3_EPD_Msk (0x01UL << SCU_SFSP3_3_EPD_Pos) /*!< SCU SFSP3_3: EPD Mask */
+#define SCU_SFSP3_3_EPUN_Pos 4 /*!< SCU SFSP3_3: EPUN Position */
+#define SCU_SFSP3_3_EPUN_Msk (0x01UL << SCU_SFSP3_3_EPUN_Pos) /*!< SCU SFSP3_3: EPUN Mask */
+#define SCU_SFSP3_3_EHS_Pos 5 /*!< SCU SFSP3_3: EHS Position */
+#define SCU_SFSP3_3_EHS_Msk (0x01UL << SCU_SFSP3_3_EHS_Pos) /*!< SCU SFSP3_3: EHS Mask */
+#define SCU_SFSP3_3_EZI_Pos 6 /*!< SCU SFSP3_3: EZI Position */
+#define SCU_SFSP3_3_EZI_Msk (0x01UL << SCU_SFSP3_3_EZI_Pos) /*!< SCU SFSP3_3: EZI Mask */
+#define SCU_SFSP3_3_EHD_Pos 8 /*!< SCU SFSP3_3: EHD Position */
+#define SCU_SFSP3_3_EHD_Msk (0x03UL << SCU_SFSP3_3_EHD_Pos) /*!< SCU SFSP3_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSP3_4 ------------------------------------------
+#define SCU_SFSP3_4_MODE_Pos 0 /*!< SCU SFSP3_4: MODE Position */
+#define SCU_SFSP3_4_MODE_Msk (0x07UL << SCU_SFSP3_4_MODE_Pos) /*!< SCU SFSP3_4: MODE Mask */
+#define SCU_SFSP3_4_EPD_Pos 3 /*!< SCU SFSP3_4: EPD Position */
+#define SCU_SFSP3_4_EPD_Msk (0x01UL << SCU_SFSP3_4_EPD_Pos) /*!< SCU SFSP3_4: EPD Mask */
+#define SCU_SFSP3_4_EPUN_Pos 4 /*!< SCU SFSP3_4: EPUN Position */
+#define SCU_SFSP3_4_EPUN_Msk (0x01UL << SCU_SFSP3_4_EPUN_Pos) /*!< SCU SFSP3_4: EPUN Mask */
+#define SCU_SFSP3_4_EHS_Pos 5 /*!< SCU SFSP3_4: EHS Position */
+#define SCU_SFSP3_4_EHS_Msk (0x01UL << SCU_SFSP3_4_EHS_Pos) /*!< SCU SFSP3_4: EHS Mask */
+#define SCU_SFSP3_4_EZI_Pos 6 /*!< SCU SFSP3_4: EZI Position */
+#define SCU_SFSP3_4_EZI_Msk (0x01UL << SCU_SFSP3_4_EZI_Pos) /*!< SCU SFSP3_4: EZI Mask */
+#define SCU_SFSP3_4_EHD_Pos 8 /*!< SCU SFSP3_4: EHD Position */
+#define SCU_SFSP3_4_EHD_Msk (0x03UL << SCU_SFSP3_4_EHD_Pos) /*!< SCU SFSP3_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSP3_5 ------------------------------------------
+#define SCU_SFSP3_5_MODE_Pos 0 /*!< SCU SFSP3_5: MODE Position */
+#define SCU_SFSP3_5_MODE_Msk (0x07UL << SCU_SFSP3_5_MODE_Pos) /*!< SCU SFSP3_5: MODE Mask */
+#define SCU_SFSP3_5_EPD_Pos 3 /*!< SCU SFSP3_5: EPD Position */
+#define SCU_SFSP3_5_EPD_Msk (0x01UL << SCU_SFSP3_5_EPD_Pos) /*!< SCU SFSP3_5: EPD Mask */
+#define SCU_SFSP3_5_EPUN_Pos 4 /*!< SCU SFSP3_5: EPUN Position */
+#define SCU_SFSP3_5_EPUN_Msk (0x01UL << SCU_SFSP3_5_EPUN_Pos) /*!< SCU SFSP3_5: EPUN Mask */
+#define SCU_SFSP3_5_EHS_Pos 5 /*!< SCU SFSP3_5: EHS Position */
+#define SCU_SFSP3_5_EHS_Msk (0x01UL << SCU_SFSP3_5_EHS_Pos) /*!< SCU SFSP3_5: EHS Mask */
+#define SCU_SFSP3_5_EZI_Pos 6 /*!< SCU SFSP3_5: EZI Position */
+#define SCU_SFSP3_5_EZI_Msk (0x01UL << SCU_SFSP3_5_EZI_Pos) /*!< SCU SFSP3_5: EZI Mask */
+#define SCU_SFSP3_5_EHD_Pos 8 /*!< SCU SFSP3_5: EHD Position */
+#define SCU_SFSP3_5_EHD_Msk (0x03UL << SCU_SFSP3_5_EHD_Pos) /*!< SCU SFSP3_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSP3_6 ------------------------------------------
+#define SCU_SFSP3_6_MODE_Pos 0 /*!< SCU SFSP3_6: MODE Position */
+#define SCU_SFSP3_6_MODE_Msk (0x07UL << SCU_SFSP3_6_MODE_Pos) /*!< SCU SFSP3_6: MODE Mask */
+#define SCU_SFSP3_6_EPD_Pos 3 /*!< SCU SFSP3_6: EPD Position */
+#define SCU_SFSP3_6_EPD_Msk (0x01UL << SCU_SFSP3_6_EPD_Pos) /*!< SCU SFSP3_6: EPD Mask */
+#define SCU_SFSP3_6_EPUN_Pos 4 /*!< SCU SFSP3_6: EPUN Position */
+#define SCU_SFSP3_6_EPUN_Msk (0x01UL << SCU_SFSP3_6_EPUN_Pos) /*!< SCU SFSP3_6: EPUN Mask */
+#define SCU_SFSP3_6_EHS_Pos 5 /*!< SCU SFSP3_6: EHS Position */
+#define SCU_SFSP3_6_EHS_Msk (0x01UL << SCU_SFSP3_6_EHS_Pos) /*!< SCU SFSP3_6: EHS Mask */
+#define SCU_SFSP3_6_EZI_Pos 6 /*!< SCU SFSP3_6: EZI Position */
+#define SCU_SFSP3_6_EZI_Msk (0x01UL << SCU_SFSP3_6_EZI_Pos) /*!< SCU SFSP3_6: EZI Mask */
+#define SCU_SFSP3_6_EHD_Pos 8 /*!< SCU SFSP3_6: EHD Position */
+#define SCU_SFSP3_6_EHD_Msk (0x03UL << SCU_SFSP3_6_EHD_Pos) /*!< SCU SFSP3_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSP3_7 ------------------------------------------
+#define SCU_SFSP3_7_MODE_Pos 0 /*!< SCU SFSP3_7: MODE Position */
+#define SCU_SFSP3_7_MODE_Msk (0x07UL << SCU_SFSP3_7_MODE_Pos) /*!< SCU SFSP3_7: MODE Mask */
+#define SCU_SFSP3_7_EPD_Pos 3 /*!< SCU SFSP3_7: EPD Position */
+#define SCU_SFSP3_7_EPD_Msk (0x01UL << SCU_SFSP3_7_EPD_Pos) /*!< SCU SFSP3_7: EPD Mask */
+#define SCU_SFSP3_7_EPUN_Pos 4 /*!< SCU SFSP3_7: EPUN Position */
+#define SCU_SFSP3_7_EPUN_Msk (0x01UL << SCU_SFSP3_7_EPUN_Pos) /*!< SCU SFSP3_7: EPUN Mask */
+#define SCU_SFSP3_7_EHS_Pos 5 /*!< SCU SFSP3_7: EHS Position */
+#define SCU_SFSP3_7_EHS_Msk (0x01UL << SCU_SFSP3_7_EHS_Pos) /*!< SCU SFSP3_7: EHS Mask */
+#define SCU_SFSP3_7_EZI_Pos 6 /*!< SCU SFSP3_7: EZI Position */
+#define SCU_SFSP3_7_EZI_Msk (0x01UL << SCU_SFSP3_7_EZI_Pos) /*!< SCU SFSP3_7: EZI Mask */
+#define SCU_SFSP3_7_EHD_Pos 8 /*!< SCU SFSP3_7: EHD Position */
+#define SCU_SFSP3_7_EHD_Msk (0x03UL << SCU_SFSP3_7_EHD_Pos) /*!< SCU SFSP3_7: EHD Mask */
+
+// --------------------------------------- SCU_SFSP3_8 ------------------------------------------
+#define SCU_SFSP3_8_MODE_Pos 0 /*!< SCU SFSP3_8: MODE Position */
+#define SCU_SFSP3_8_MODE_Msk (0x07UL << SCU_SFSP3_8_MODE_Pos) /*!< SCU SFSP3_8: MODE Mask */
+#define SCU_SFSP3_8_EPD_Pos 3 /*!< SCU SFSP3_8: EPD Position */
+#define SCU_SFSP3_8_EPD_Msk (0x01UL << SCU_SFSP3_8_EPD_Pos) /*!< SCU SFSP3_8: EPD Mask */
+#define SCU_SFSP3_8_EPUN_Pos 4 /*!< SCU SFSP3_8: EPUN Position */
+#define SCU_SFSP3_8_EPUN_Msk (0x01UL << SCU_SFSP3_8_EPUN_Pos) /*!< SCU SFSP3_8: EPUN Mask */
+#define SCU_SFSP3_8_EHS_Pos 5 /*!< SCU SFSP3_8: EHS Position */
+#define SCU_SFSP3_8_EHS_Msk (0x01UL << SCU_SFSP3_8_EHS_Pos) /*!< SCU SFSP3_8: EHS Mask */
+#define SCU_SFSP3_8_EZI_Pos 6 /*!< SCU SFSP3_8: EZI Position */
+#define SCU_SFSP3_8_EZI_Msk (0x01UL << SCU_SFSP3_8_EZI_Pos) /*!< SCU SFSP3_8: EZI Mask */
+#define SCU_SFSP3_8_EHD_Pos 8 /*!< SCU SFSP3_8: EHD Position */
+#define SCU_SFSP3_8_EHD_Msk (0x03UL << SCU_SFSP3_8_EHD_Pos) /*!< SCU SFSP3_8: EHD Mask */
+
+// --------------------------------------- SCU_SFSP4_0 ------------------------------------------
+#define SCU_SFSP4_0_MODE_Pos 0 /*!< SCU SFSP4_0: MODE Position */
+#define SCU_SFSP4_0_MODE_Msk (0x07UL << SCU_SFSP4_0_MODE_Pos) /*!< SCU SFSP4_0: MODE Mask */
+#define SCU_SFSP4_0_EPD_Pos 3 /*!< SCU SFSP4_0: EPD Position */
+#define SCU_SFSP4_0_EPD_Msk (0x01UL << SCU_SFSP4_0_EPD_Pos) /*!< SCU SFSP4_0: EPD Mask */
+#define SCU_SFSP4_0_EPUN_Pos 4 /*!< SCU SFSP4_0: EPUN Position */
+#define SCU_SFSP4_0_EPUN_Msk (0x01UL << SCU_SFSP4_0_EPUN_Pos) /*!< SCU SFSP4_0: EPUN Mask */
+#define SCU_SFSP4_0_EHS_Pos 5 /*!< SCU SFSP4_0: EHS Position */
+#define SCU_SFSP4_0_EHS_Msk (0x01UL << SCU_SFSP4_0_EHS_Pos) /*!< SCU SFSP4_0: EHS Mask */
+#define SCU_SFSP4_0_EZI_Pos 6 /*!< SCU SFSP4_0: EZI Position */
+#define SCU_SFSP4_0_EZI_Msk (0x01UL << SCU_SFSP4_0_EZI_Pos) /*!< SCU SFSP4_0: EZI Mask */
+#define SCU_SFSP4_0_EHD_Pos 8 /*!< SCU SFSP4_0: EHD Position */
+#define SCU_SFSP4_0_EHD_Msk (0x03UL << SCU_SFSP4_0_EHD_Pos) /*!< SCU SFSP4_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSP4_1 ------------------------------------------
+#define SCU_SFSP4_1_MODE_Pos 0 /*!< SCU SFSP4_1: MODE Position */
+#define SCU_SFSP4_1_MODE_Msk (0x07UL << SCU_SFSP4_1_MODE_Pos) /*!< SCU SFSP4_1: MODE Mask */
+#define SCU_SFSP4_1_EPD_Pos 3 /*!< SCU SFSP4_1: EPD Position */
+#define SCU_SFSP4_1_EPD_Msk (0x01UL << SCU_SFSP4_1_EPD_Pos) /*!< SCU SFSP4_1: EPD Mask */
+#define SCU_SFSP4_1_EPUN_Pos 4 /*!< SCU SFSP4_1: EPUN Position */
+#define SCU_SFSP4_1_EPUN_Msk (0x01UL << SCU_SFSP4_1_EPUN_Pos) /*!< SCU SFSP4_1: EPUN Mask */
+#define SCU_SFSP4_1_EHS_Pos 5 /*!< SCU SFSP4_1: EHS Position */
+#define SCU_SFSP4_1_EHS_Msk (0x01UL << SCU_SFSP4_1_EHS_Pos) /*!< SCU SFSP4_1: EHS Mask */
+#define SCU_SFSP4_1_EZI_Pos 6 /*!< SCU SFSP4_1: EZI Position */
+#define SCU_SFSP4_1_EZI_Msk (0x01UL << SCU_SFSP4_1_EZI_Pos) /*!< SCU SFSP4_1: EZI Mask */
+#define SCU_SFSP4_1_EHD_Pos 8 /*!< SCU SFSP4_1: EHD Position */
+#define SCU_SFSP4_1_EHD_Msk (0x03UL << SCU_SFSP4_1_EHD_Pos) /*!< SCU SFSP4_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSP4_2 ------------------------------------------
+#define SCU_SFSP4_2_MODE_Pos 0 /*!< SCU SFSP4_2: MODE Position */
+#define SCU_SFSP4_2_MODE_Msk (0x07UL << SCU_SFSP4_2_MODE_Pos) /*!< SCU SFSP4_2: MODE Mask */
+#define SCU_SFSP4_2_EPD_Pos 3 /*!< SCU SFSP4_2: EPD Position */
+#define SCU_SFSP4_2_EPD_Msk (0x01UL << SCU_SFSP4_2_EPD_Pos) /*!< SCU SFSP4_2: EPD Mask */
+#define SCU_SFSP4_2_EPUN_Pos 4 /*!< SCU SFSP4_2: EPUN Position */
+#define SCU_SFSP4_2_EPUN_Msk (0x01UL << SCU_SFSP4_2_EPUN_Pos) /*!< SCU SFSP4_2: EPUN Mask */
+#define SCU_SFSP4_2_EHS_Pos 5 /*!< SCU SFSP4_2: EHS Position */
+#define SCU_SFSP4_2_EHS_Msk (0x01UL << SCU_SFSP4_2_EHS_Pos) /*!< SCU SFSP4_2: EHS Mask */
+#define SCU_SFSP4_2_EZI_Pos 6 /*!< SCU SFSP4_2: EZI Position */
+#define SCU_SFSP4_2_EZI_Msk (0x01UL << SCU_SFSP4_2_EZI_Pos) /*!< SCU SFSP4_2: EZI Mask */
+#define SCU_SFSP4_2_EHD_Pos 8 /*!< SCU SFSP4_2: EHD Position */
+#define SCU_SFSP4_2_EHD_Msk (0x03UL << SCU_SFSP4_2_EHD_Pos) /*!< SCU SFSP4_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSP4_3 ------------------------------------------
+#define SCU_SFSP4_3_MODE_Pos 0 /*!< SCU SFSP4_3: MODE Position */
+#define SCU_SFSP4_3_MODE_Msk (0x07UL << SCU_SFSP4_3_MODE_Pos) /*!< SCU SFSP4_3: MODE Mask */
+#define SCU_SFSP4_3_EPD_Pos 3 /*!< SCU SFSP4_3: EPD Position */
+#define SCU_SFSP4_3_EPD_Msk (0x01UL << SCU_SFSP4_3_EPD_Pos) /*!< SCU SFSP4_3: EPD Mask */
+#define SCU_SFSP4_3_EPUN_Pos 4 /*!< SCU SFSP4_3: EPUN Position */
+#define SCU_SFSP4_3_EPUN_Msk (0x01UL << SCU_SFSP4_3_EPUN_Pos) /*!< SCU SFSP4_3: EPUN Mask */
+#define SCU_SFSP4_3_EHS_Pos 5 /*!< SCU SFSP4_3: EHS Position */
+#define SCU_SFSP4_3_EHS_Msk (0x01UL << SCU_SFSP4_3_EHS_Pos) /*!< SCU SFSP4_3: EHS Mask */
+#define SCU_SFSP4_3_EZI_Pos 6 /*!< SCU SFSP4_3: EZI Position */
+#define SCU_SFSP4_3_EZI_Msk (0x01UL << SCU_SFSP4_3_EZI_Pos) /*!< SCU SFSP4_3: EZI Mask */
+#define SCU_SFSP4_3_EHD_Pos 8 /*!< SCU SFSP4_3: EHD Position */
+#define SCU_SFSP4_3_EHD_Msk (0x03UL << SCU_SFSP4_3_EHD_Pos) /*!< SCU SFSP4_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSP4_4 ------------------------------------------
+#define SCU_SFSP4_4_MODE_Pos 0 /*!< SCU SFSP4_4: MODE Position */
+#define SCU_SFSP4_4_MODE_Msk (0x07UL << SCU_SFSP4_4_MODE_Pos) /*!< SCU SFSP4_4: MODE Mask */
+#define SCU_SFSP4_4_EPD_Pos 3 /*!< SCU SFSP4_4: EPD Position */
+#define SCU_SFSP4_4_EPD_Msk (0x01UL << SCU_SFSP4_4_EPD_Pos) /*!< SCU SFSP4_4: EPD Mask */
+#define SCU_SFSP4_4_EPUN_Pos 4 /*!< SCU SFSP4_4: EPUN Position */
+#define SCU_SFSP4_4_EPUN_Msk (0x01UL << SCU_SFSP4_4_EPUN_Pos) /*!< SCU SFSP4_4: EPUN Mask */
+#define SCU_SFSP4_4_EHS_Pos 5 /*!< SCU SFSP4_4: EHS Position */
+#define SCU_SFSP4_4_EHS_Msk (0x01UL << SCU_SFSP4_4_EHS_Pos) /*!< SCU SFSP4_4: EHS Mask */
+#define SCU_SFSP4_4_EZI_Pos 6 /*!< SCU SFSP4_4: EZI Position */
+#define SCU_SFSP4_4_EZI_Msk (0x01UL << SCU_SFSP4_4_EZI_Pos) /*!< SCU SFSP4_4: EZI Mask */
+#define SCU_SFSP4_4_EHD_Pos 8 /*!< SCU SFSP4_4: EHD Position */
+#define SCU_SFSP4_4_EHD_Msk (0x03UL << SCU_SFSP4_4_EHD_Pos) /*!< SCU SFSP4_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSP4_5 ------------------------------------------
+#define SCU_SFSP4_5_MODE_Pos 0 /*!< SCU SFSP4_5: MODE Position */
+#define SCU_SFSP4_5_MODE_Msk (0x07UL << SCU_SFSP4_5_MODE_Pos) /*!< SCU SFSP4_5: MODE Mask */
+#define SCU_SFSP4_5_EPD_Pos 3 /*!< SCU SFSP4_5: EPD Position */
+#define SCU_SFSP4_5_EPD_Msk (0x01UL << SCU_SFSP4_5_EPD_Pos) /*!< SCU SFSP4_5: EPD Mask */
+#define SCU_SFSP4_5_EPUN_Pos 4 /*!< SCU SFSP4_5: EPUN Position */
+#define SCU_SFSP4_5_EPUN_Msk (0x01UL << SCU_SFSP4_5_EPUN_Pos) /*!< SCU SFSP4_5: EPUN Mask */
+#define SCU_SFSP4_5_EHS_Pos 5 /*!< SCU SFSP4_5: EHS Position */
+#define SCU_SFSP4_5_EHS_Msk (0x01UL << SCU_SFSP4_5_EHS_Pos) /*!< SCU SFSP4_5: EHS Mask */
+#define SCU_SFSP4_5_EZI_Pos 6 /*!< SCU SFSP4_5: EZI Position */
+#define SCU_SFSP4_5_EZI_Msk (0x01UL << SCU_SFSP4_5_EZI_Pos) /*!< SCU SFSP4_5: EZI Mask */
+#define SCU_SFSP4_5_EHD_Pos 8 /*!< SCU SFSP4_5: EHD Position */
+#define SCU_SFSP4_5_EHD_Msk (0x03UL << SCU_SFSP4_5_EHD_Pos) /*!< SCU SFSP4_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSP4_6 ------------------------------------------
+#define SCU_SFSP4_6_MODE_Pos 0 /*!< SCU SFSP4_6: MODE Position */
+#define SCU_SFSP4_6_MODE_Msk (0x07UL << SCU_SFSP4_6_MODE_Pos) /*!< SCU SFSP4_6: MODE Mask */
+#define SCU_SFSP4_6_EPD_Pos 3 /*!< SCU SFSP4_6: EPD Position */
+#define SCU_SFSP4_6_EPD_Msk (0x01UL << SCU_SFSP4_6_EPD_Pos) /*!< SCU SFSP4_6: EPD Mask */
+#define SCU_SFSP4_6_EPUN_Pos 4 /*!< SCU SFSP4_6: EPUN Position */
+#define SCU_SFSP4_6_EPUN_Msk (0x01UL << SCU_SFSP4_6_EPUN_Pos) /*!< SCU SFSP4_6: EPUN Mask */
+#define SCU_SFSP4_6_EHS_Pos 5 /*!< SCU SFSP4_6: EHS Position */
+#define SCU_SFSP4_6_EHS_Msk (0x01UL << SCU_SFSP4_6_EHS_Pos) /*!< SCU SFSP4_6: EHS Mask */
+#define SCU_SFSP4_6_EZI_Pos 6 /*!< SCU SFSP4_6: EZI Position */
+#define SCU_SFSP4_6_EZI_Msk (0x01UL << SCU_SFSP4_6_EZI_Pos) /*!< SCU SFSP4_6: EZI Mask */
+#define SCU_SFSP4_6_EHD_Pos 8 /*!< SCU SFSP4_6: EHD Position */
+#define SCU_SFSP4_6_EHD_Msk (0x03UL << SCU_SFSP4_6_EHD_Pos) /*!< SCU SFSP4_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSP4_7 ------------------------------------------
+#define SCU_SFSP4_7_MODE_Pos 0 /*!< SCU SFSP4_7: MODE Position */
+#define SCU_SFSP4_7_MODE_Msk (0x07UL << SCU_SFSP4_7_MODE_Pos) /*!< SCU SFSP4_7: MODE Mask */
+#define SCU_SFSP4_7_EPD_Pos 3 /*!< SCU SFSP4_7: EPD Position */
+#define SCU_SFSP4_7_EPD_Msk (0x01UL << SCU_SFSP4_7_EPD_Pos) /*!< SCU SFSP4_7: EPD Mask */
+#define SCU_SFSP4_7_EPUN_Pos 4 /*!< SCU SFSP4_7: EPUN Position */
+#define SCU_SFSP4_7_EPUN_Msk (0x01UL << SCU_SFSP4_7_EPUN_Pos) /*!< SCU SFSP4_7: EPUN Mask */
+#define SCU_SFSP4_7_EHS_Pos 5 /*!< SCU SFSP4_7: EHS Position */
+#define SCU_SFSP4_7_EHS_Msk (0x01UL << SCU_SFSP4_7_EHS_Pos) /*!< SCU SFSP4_7: EHS Mask */
+#define SCU_SFSP4_7_EZI_Pos 6 /*!< SCU SFSP4_7: EZI Position */
+#define SCU_SFSP4_7_EZI_Msk (0x01UL << SCU_SFSP4_7_EZI_Pos) /*!< SCU SFSP4_7: EZI Mask */
+#define SCU_SFSP4_7_EHD_Pos 8 /*!< SCU SFSP4_7: EHD Position */
+#define SCU_SFSP4_7_EHD_Msk (0x03UL << SCU_SFSP4_7_EHD_Pos) /*!< SCU SFSP4_7: EHD Mask */
+
+// --------------------------------------- SCU_SFSP4_8 ------------------------------------------
+#define SCU_SFSP4_8_MODE_Pos 0 /*!< SCU SFSP4_8: MODE Position */
+#define SCU_SFSP4_8_MODE_Msk (0x07UL << SCU_SFSP4_8_MODE_Pos) /*!< SCU SFSP4_8: MODE Mask */
+#define SCU_SFSP4_8_EPD_Pos 3 /*!< SCU SFSP4_8: EPD Position */
+#define SCU_SFSP4_8_EPD_Msk (0x01UL << SCU_SFSP4_8_EPD_Pos) /*!< SCU SFSP4_8: EPD Mask */
+#define SCU_SFSP4_8_EPUN_Pos 4 /*!< SCU SFSP4_8: EPUN Position */
+#define SCU_SFSP4_8_EPUN_Msk (0x01UL << SCU_SFSP4_8_EPUN_Pos) /*!< SCU SFSP4_8: EPUN Mask */
+#define SCU_SFSP4_8_EHS_Pos 5 /*!< SCU SFSP4_8: EHS Position */
+#define SCU_SFSP4_8_EHS_Msk (0x01UL << SCU_SFSP4_8_EHS_Pos) /*!< SCU SFSP4_8: EHS Mask */
+#define SCU_SFSP4_8_EZI_Pos 6 /*!< SCU SFSP4_8: EZI Position */
+#define SCU_SFSP4_8_EZI_Msk (0x01UL << SCU_SFSP4_8_EZI_Pos) /*!< SCU SFSP4_8: EZI Mask */
+#define SCU_SFSP4_8_EHD_Pos 8 /*!< SCU SFSP4_8: EHD Position */
+#define SCU_SFSP4_8_EHD_Msk (0x03UL << SCU_SFSP4_8_EHD_Pos) /*!< SCU SFSP4_8: EHD Mask */
+
+// --------------------------------------- SCU_SFSP4_9 ------------------------------------------
+#define SCU_SFSP4_9_MODE_Pos 0 /*!< SCU SFSP4_9: MODE Position */
+#define SCU_SFSP4_9_MODE_Msk (0x07UL << SCU_SFSP4_9_MODE_Pos) /*!< SCU SFSP4_9: MODE Mask */
+#define SCU_SFSP4_9_EPD_Pos 3 /*!< SCU SFSP4_9: EPD Position */
+#define SCU_SFSP4_9_EPD_Msk (0x01UL << SCU_SFSP4_9_EPD_Pos) /*!< SCU SFSP4_9: EPD Mask */
+#define SCU_SFSP4_9_EPUN_Pos 4 /*!< SCU SFSP4_9: EPUN Position */
+#define SCU_SFSP4_9_EPUN_Msk (0x01UL << SCU_SFSP4_9_EPUN_Pos) /*!< SCU SFSP4_9: EPUN Mask */
+#define SCU_SFSP4_9_EHS_Pos 5 /*!< SCU SFSP4_9: EHS Position */
+#define SCU_SFSP4_9_EHS_Msk (0x01UL << SCU_SFSP4_9_EHS_Pos) /*!< SCU SFSP4_9: EHS Mask */
+#define SCU_SFSP4_9_EZI_Pos 6 /*!< SCU SFSP4_9: EZI Position */
+#define SCU_SFSP4_9_EZI_Msk (0x01UL << SCU_SFSP4_9_EZI_Pos) /*!< SCU SFSP4_9: EZI Mask */
+#define SCU_SFSP4_9_EHD_Pos 8 /*!< SCU SFSP4_9: EHD Position */
+#define SCU_SFSP4_9_EHD_Msk (0x03UL << SCU_SFSP4_9_EHD_Pos) /*!< SCU SFSP4_9: EHD Mask */
+
+// -------------------------------------- SCU_SFSP4_10 ------------------------------------------
+#define SCU_SFSP4_10_MODE_Pos 0 /*!< SCU SFSP4_10: MODE Position */
+#define SCU_SFSP4_10_MODE_Msk (0x07UL << SCU_SFSP4_10_MODE_Pos) /*!< SCU SFSP4_10: MODE Mask */
+#define SCU_SFSP4_10_EPD_Pos 3 /*!< SCU SFSP4_10: EPD Position */
+#define SCU_SFSP4_10_EPD_Msk (0x01UL << SCU_SFSP4_10_EPD_Pos) /*!< SCU SFSP4_10: EPD Mask */
+#define SCU_SFSP4_10_EPUN_Pos 4 /*!< SCU SFSP4_10: EPUN Position */
+#define SCU_SFSP4_10_EPUN_Msk (0x01UL << SCU_SFSP4_10_EPUN_Pos) /*!< SCU SFSP4_10: EPUN Mask */
+#define SCU_SFSP4_10_EHS_Pos 5 /*!< SCU SFSP4_10: EHS Position */
+#define SCU_SFSP4_10_EHS_Msk (0x01UL << SCU_SFSP4_10_EHS_Pos) /*!< SCU SFSP4_10: EHS Mask */
+#define SCU_SFSP4_10_EZI_Pos 6 /*!< SCU SFSP4_10: EZI Position */
+#define SCU_SFSP4_10_EZI_Msk (0x01UL << SCU_SFSP4_10_EZI_Pos) /*!< SCU SFSP4_10: EZI Mask */
+#define SCU_SFSP4_10_EHD_Pos 8 /*!< SCU SFSP4_10: EHD Position */
+#define SCU_SFSP4_10_EHD_Msk (0x03UL << SCU_SFSP4_10_EHD_Pos) /*!< SCU SFSP4_10: EHD Mask */
+
+// --------------------------------------- SCU_SFSP5_0 ------------------------------------------
+#define SCU_SFSP5_0_MODE_Pos 0 /*!< SCU SFSP5_0: MODE Position */
+#define SCU_SFSP5_0_MODE_Msk (0x07UL << SCU_SFSP5_0_MODE_Pos) /*!< SCU SFSP5_0: MODE Mask */
+#define SCU_SFSP5_0_EPD_Pos 3 /*!< SCU SFSP5_0: EPD Position */
+#define SCU_SFSP5_0_EPD_Msk (0x01UL << SCU_SFSP5_0_EPD_Pos) /*!< SCU SFSP5_0: EPD Mask */
+#define SCU_SFSP5_0_EPUN_Pos 4 /*!< SCU SFSP5_0: EPUN Position */
+#define SCU_SFSP5_0_EPUN_Msk (0x01UL << SCU_SFSP5_0_EPUN_Pos) /*!< SCU SFSP5_0: EPUN Mask */
+#define SCU_SFSP5_0_EHS_Pos 5 /*!< SCU SFSP5_0: EHS Position */
+#define SCU_SFSP5_0_EHS_Msk (0x01UL << SCU_SFSP5_0_EHS_Pos) /*!< SCU SFSP5_0: EHS Mask */
+#define SCU_SFSP5_0_EZI_Pos 6 /*!< SCU SFSP5_0: EZI Position */
+#define SCU_SFSP5_0_EZI_Msk (0x01UL << SCU_SFSP5_0_EZI_Pos) /*!< SCU SFSP5_0: EZI Mask */
+#define SCU_SFSP5_0_EHD_Pos 8 /*!< SCU SFSP5_0: EHD Position */
+#define SCU_SFSP5_0_EHD_Msk (0x03UL << SCU_SFSP5_0_EHD_Pos) /*!< SCU SFSP5_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSP5_1 ------------------------------------------
+#define SCU_SFSP5_1_MODE_Pos 0 /*!< SCU SFSP5_1: MODE Position */
+#define SCU_SFSP5_1_MODE_Msk (0x07UL << SCU_SFSP5_1_MODE_Pos) /*!< SCU SFSP5_1: MODE Mask */
+#define SCU_SFSP5_1_EPD_Pos 3 /*!< SCU SFSP5_1: EPD Position */
+#define SCU_SFSP5_1_EPD_Msk (0x01UL << SCU_SFSP5_1_EPD_Pos) /*!< SCU SFSP5_1: EPD Mask */
+#define SCU_SFSP5_1_EPUN_Pos 4 /*!< SCU SFSP5_1: EPUN Position */
+#define SCU_SFSP5_1_EPUN_Msk (0x01UL << SCU_SFSP5_1_EPUN_Pos) /*!< SCU SFSP5_1: EPUN Mask */
+#define SCU_SFSP5_1_EHS_Pos 5 /*!< SCU SFSP5_1: EHS Position */
+#define SCU_SFSP5_1_EHS_Msk (0x01UL << SCU_SFSP5_1_EHS_Pos) /*!< SCU SFSP5_1: EHS Mask */
+#define SCU_SFSP5_1_EZI_Pos 6 /*!< SCU SFSP5_1: EZI Position */
+#define SCU_SFSP5_1_EZI_Msk (0x01UL << SCU_SFSP5_1_EZI_Pos) /*!< SCU SFSP5_1: EZI Mask */
+#define SCU_SFSP5_1_EHD_Pos 8 /*!< SCU SFSP5_1: EHD Position */
+#define SCU_SFSP5_1_EHD_Msk (0x03UL << SCU_SFSP5_1_EHD_Pos) /*!< SCU SFSP5_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSP5_2 ------------------------------------------
+#define SCU_SFSP5_2_MODE_Pos 0 /*!< SCU SFSP5_2: MODE Position */
+#define SCU_SFSP5_2_MODE_Msk (0x07UL << SCU_SFSP5_2_MODE_Pos) /*!< SCU SFSP5_2: MODE Mask */
+#define SCU_SFSP5_2_EPD_Pos 3 /*!< SCU SFSP5_2: EPD Position */
+#define SCU_SFSP5_2_EPD_Msk (0x01UL << SCU_SFSP5_2_EPD_Pos) /*!< SCU SFSP5_2: EPD Mask */
+#define SCU_SFSP5_2_EPUN_Pos 4 /*!< SCU SFSP5_2: EPUN Position */
+#define SCU_SFSP5_2_EPUN_Msk (0x01UL << SCU_SFSP5_2_EPUN_Pos) /*!< SCU SFSP5_2: EPUN Mask */
+#define SCU_SFSP5_2_EHS_Pos 5 /*!< SCU SFSP5_2: EHS Position */
+#define SCU_SFSP5_2_EHS_Msk (0x01UL << SCU_SFSP5_2_EHS_Pos) /*!< SCU SFSP5_2: EHS Mask */
+#define SCU_SFSP5_2_EZI_Pos 6 /*!< SCU SFSP5_2: EZI Position */
+#define SCU_SFSP5_2_EZI_Msk (0x01UL << SCU_SFSP5_2_EZI_Pos) /*!< SCU SFSP5_2: EZI Mask */
+#define SCU_SFSP5_2_EHD_Pos 8 /*!< SCU SFSP5_2: EHD Position */
+#define SCU_SFSP5_2_EHD_Msk (0x03UL << SCU_SFSP5_2_EHD_Pos) /*!< SCU SFSP5_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSP5_3 ------------------------------------------
+#define SCU_SFSP5_3_MODE_Pos 0 /*!< SCU SFSP5_3: MODE Position */
+#define SCU_SFSP5_3_MODE_Msk (0x07UL << SCU_SFSP5_3_MODE_Pos) /*!< SCU SFSP5_3: MODE Mask */
+#define SCU_SFSP5_3_EPD_Pos 3 /*!< SCU SFSP5_3: EPD Position */
+#define SCU_SFSP5_3_EPD_Msk (0x01UL << SCU_SFSP5_3_EPD_Pos) /*!< SCU SFSP5_3: EPD Mask */
+#define SCU_SFSP5_3_EPUN_Pos 4 /*!< SCU SFSP5_3: EPUN Position */
+#define SCU_SFSP5_3_EPUN_Msk (0x01UL << SCU_SFSP5_3_EPUN_Pos) /*!< SCU SFSP5_3: EPUN Mask */
+#define SCU_SFSP5_3_EHS_Pos 5 /*!< SCU SFSP5_3: EHS Position */
+#define SCU_SFSP5_3_EHS_Msk (0x01UL << SCU_SFSP5_3_EHS_Pos) /*!< SCU SFSP5_3: EHS Mask */
+#define SCU_SFSP5_3_EZI_Pos 6 /*!< SCU SFSP5_3: EZI Position */
+#define SCU_SFSP5_3_EZI_Msk (0x01UL << SCU_SFSP5_3_EZI_Pos) /*!< SCU SFSP5_3: EZI Mask */
+#define SCU_SFSP5_3_EHD_Pos 8 /*!< SCU SFSP5_3: EHD Position */
+#define SCU_SFSP5_3_EHD_Msk (0x03UL << SCU_SFSP5_3_EHD_Pos) /*!< SCU SFSP5_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSP5_4 ------------------------------------------
+#define SCU_SFSP5_4_MODE_Pos 0 /*!< SCU SFSP5_4: MODE Position */
+#define SCU_SFSP5_4_MODE_Msk (0x07UL << SCU_SFSP5_4_MODE_Pos) /*!< SCU SFSP5_4: MODE Mask */
+#define SCU_SFSP5_4_EPD_Pos 3 /*!< SCU SFSP5_4: EPD Position */
+#define SCU_SFSP5_4_EPD_Msk (0x01UL << SCU_SFSP5_4_EPD_Pos) /*!< SCU SFSP5_4: EPD Mask */
+#define SCU_SFSP5_4_EPUN_Pos 4 /*!< SCU SFSP5_4: EPUN Position */
+#define SCU_SFSP5_4_EPUN_Msk (0x01UL << SCU_SFSP5_4_EPUN_Pos) /*!< SCU SFSP5_4: EPUN Mask */
+#define SCU_SFSP5_4_EHS_Pos 5 /*!< SCU SFSP5_4: EHS Position */
+#define SCU_SFSP5_4_EHS_Msk (0x01UL << SCU_SFSP5_4_EHS_Pos) /*!< SCU SFSP5_4: EHS Mask */
+#define SCU_SFSP5_4_EZI_Pos 6 /*!< SCU SFSP5_4: EZI Position */
+#define SCU_SFSP5_4_EZI_Msk (0x01UL << SCU_SFSP5_4_EZI_Pos) /*!< SCU SFSP5_4: EZI Mask */
+#define SCU_SFSP5_4_EHD_Pos 8 /*!< SCU SFSP5_4: EHD Position */
+#define SCU_SFSP5_4_EHD_Msk (0x03UL << SCU_SFSP5_4_EHD_Pos) /*!< SCU SFSP5_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSP5_5 ------------------------------------------
+#define SCU_SFSP5_5_MODE_Pos 0 /*!< SCU SFSP5_5: MODE Position */
+#define SCU_SFSP5_5_MODE_Msk (0x07UL << SCU_SFSP5_5_MODE_Pos) /*!< SCU SFSP5_5: MODE Mask */
+#define SCU_SFSP5_5_EPD_Pos 3 /*!< SCU SFSP5_5: EPD Position */
+#define SCU_SFSP5_5_EPD_Msk (0x01UL << SCU_SFSP5_5_EPD_Pos) /*!< SCU SFSP5_5: EPD Mask */
+#define SCU_SFSP5_5_EPUN_Pos 4 /*!< SCU SFSP5_5: EPUN Position */
+#define SCU_SFSP5_5_EPUN_Msk (0x01UL << SCU_SFSP5_5_EPUN_Pos) /*!< SCU SFSP5_5: EPUN Mask */
+#define SCU_SFSP5_5_EHS_Pos 5 /*!< SCU SFSP5_5: EHS Position */
+#define SCU_SFSP5_5_EHS_Msk (0x01UL << SCU_SFSP5_5_EHS_Pos) /*!< SCU SFSP5_5: EHS Mask */
+#define SCU_SFSP5_5_EZI_Pos 6 /*!< SCU SFSP5_5: EZI Position */
+#define SCU_SFSP5_5_EZI_Msk (0x01UL << SCU_SFSP5_5_EZI_Pos) /*!< SCU SFSP5_5: EZI Mask */
+#define SCU_SFSP5_5_EHD_Pos 8 /*!< SCU SFSP5_5: EHD Position */
+#define SCU_SFSP5_5_EHD_Msk (0x03UL << SCU_SFSP5_5_EHD_Pos) /*!< SCU SFSP5_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSP5_6 ------------------------------------------
+#define SCU_SFSP5_6_MODE_Pos 0 /*!< SCU SFSP5_6: MODE Position */
+#define SCU_SFSP5_6_MODE_Msk (0x07UL << SCU_SFSP5_6_MODE_Pos) /*!< SCU SFSP5_6: MODE Mask */
+#define SCU_SFSP5_6_EPD_Pos 3 /*!< SCU SFSP5_6: EPD Position */
+#define SCU_SFSP5_6_EPD_Msk (0x01UL << SCU_SFSP5_6_EPD_Pos) /*!< SCU SFSP5_6: EPD Mask */
+#define SCU_SFSP5_6_EPUN_Pos 4 /*!< SCU SFSP5_6: EPUN Position */
+#define SCU_SFSP5_6_EPUN_Msk (0x01UL << SCU_SFSP5_6_EPUN_Pos) /*!< SCU SFSP5_6: EPUN Mask */
+#define SCU_SFSP5_6_EHS_Pos 5 /*!< SCU SFSP5_6: EHS Position */
+#define SCU_SFSP5_6_EHS_Msk (0x01UL << SCU_SFSP5_6_EHS_Pos) /*!< SCU SFSP5_6: EHS Mask */
+#define SCU_SFSP5_6_EZI_Pos 6 /*!< SCU SFSP5_6: EZI Position */
+#define SCU_SFSP5_6_EZI_Msk (0x01UL << SCU_SFSP5_6_EZI_Pos) /*!< SCU SFSP5_6: EZI Mask */
+#define SCU_SFSP5_6_EHD_Pos 8 /*!< SCU SFSP5_6: EHD Position */
+#define SCU_SFSP5_6_EHD_Msk (0x03UL << SCU_SFSP5_6_EHD_Pos) /*!< SCU SFSP5_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSP5_7 ------------------------------------------
+#define SCU_SFSP5_7_MODE_Pos 0 /*!< SCU SFSP5_7: MODE Position */
+#define SCU_SFSP5_7_MODE_Msk (0x07UL << SCU_SFSP5_7_MODE_Pos) /*!< SCU SFSP5_7: MODE Mask */
+#define SCU_SFSP5_7_EPD_Pos 3 /*!< SCU SFSP5_7: EPD Position */
+#define SCU_SFSP5_7_EPD_Msk (0x01UL << SCU_SFSP5_7_EPD_Pos) /*!< SCU SFSP5_7: EPD Mask */
+#define SCU_SFSP5_7_EPUN_Pos 4 /*!< SCU SFSP5_7: EPUN Position */
+#define SCU_SFSP5_7_EPUN_Msk (0x01UL << SCU_SFSP5_7_EPUN_Pos) /*!< SCU SFSP5_7: EPUN Mask */
+#define SCU_SFSP5_7_EHS_Pos 5 /*!< SCU SFSP5_7: EHS Position */
+#define SCU_SFSP5_7_EHS_Msk (0x01UL << SCU_SFSP5_7_EHS_Pos) /*!< SCU SFSP5_7: EHS Mask */
+#define SCU_SFSP5_7_EZI_Pos 6 /*!< SCU SFSP5_7: EZI Position */
+#define SCU_SFSP5_7_EZI_Msk (0x01UL << SCU_SFSP5_7_EZI_Pos) /*!< SCU SFSP5_7: EZI Mask */
+#define SCU_SFSP5_7_EHD_Pos 8 /*!< SCU SFSP5_7: EHD Position */
+#define SCU_SFSP5_7_EHD_Msk (0x03UL << SCU_SFSP5_7_EHD_Pos) /*!< SCU SFSP5_7: EHD Mask */
+
+// --------------------------------------- SCU_SFSP6_0 ------------------------------------------
+#define SCU_SFSP6_0_MODE_Pos 0 /*!< SCU SFSP6_0: MODE Position */
+#define SCU_SFSP6_0_MODE_Msk (0x07UL << SCU_SFSP6_0_MODE_Pos) /*!< SCU SFSP6_0: MODE Mask */
+#define SCU_SFSP6_0_EPD_Pos 3 /*!< SCU SFSP6_0: EPD Position */
+#define SCU_SFSP6_0_EPD_Msk (0x01UL << SCU_SFSP6_0_EPD_Pos) /*!< SCU SFSP6_0: EPD Mask */
+#define SCU_SFSP6_0_EPUN_Pos 4 /*!< SCU SFSP6_0: EPUN Position */
+#define SCU_SFSP6_0_EPUN_Msk (0x01UL << SCU_SFSP6_0_EPUN_Pos) /*!< SCU SFSP6_0: EPUN Mask */
+#define SCU_SFSP6_0_EHS_Pos 5 /*!< SCU SFSP6_0: EHS Position */
+#define SCU_SFSP6_0_EHS_Msk (0x01UL << SCU_SFSP6_0_EHS_Pos) /*!< SCU SFSP6_0: EHS Mask */
+#define SCU_SFSP6_0_EZI_Pos 6 /*!< SCU SFSP6_0: EZI Position */
+#define SCU_SFSP6_0_EZI_Msk (0x01UL << SCU_SFSP6_0_EZI_Pos) /*!< SCU SFSP6_0: EZI Mask */
+#define SCU_SFSP6_0_EHD_Pos 8 /*!< SCU SFSP6_0: EHD Position */
+#define SCU_SFSP6_0_EHD_Msk (0x03UL << SCU_SFSP6_0_EHD_Pos) /*!< SCU SFSP6_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSP6_1 ------------------------------------------
+#define SCU_SFSP6_1_MODE_Pos 0 /*!< SCU SFSP6_1: MODE Position */
+#define SCU_SFSP6_1_MODE_Msk (0x07UL << SCU_SFSP6_1_MODE_Pos) /*!< SCU SFSP6_1: MODE Mask */
+#define SCU_SFSP6_1_EPD_Pos 3 /*!< SCU SFSP6_1: EPD Position */
+#define SCU_SFSP6_1_EPD_Msk (0x01UL << SCU_SFSP6_1_EPD_Pos) /*!< SCU SFSP6_1: EPD Mask */
+#define SCU_SFSP6_1_EPUN_Pos 4 /*!< SCU SFSP6_1: EPUN Position */
+#define SCU_SFSP6_1_EPUN_Msk (0x01UL << SCU_SFSP6_1_EPUN_Pos) /*!< SCU SFSP6_1: EPUN Mask */
+#define SCU_SFSP6_1_EHS_Pos 5 /*!< SCU SFSP6_1: EHS Position */
+#define SCU_SFSP6_1_EHS_Msk (0x01UL << SCU_SFSP6_1_EHS_Pos) /*!< SCU SFSP6_1: EHS Mask */
+#define SCU_SFSP6_1_EZI_Pos 6 /*!< SCU SFSP6_1: EZI Position */
+#define SCU_SFSP6_1_EZI_Msk (0x01UL << SCU_SFSP6_1_EZI_Pos) /*!< SCU SFSP6_1: EZI Mask */
+#define SCU_SFSP6_1_EHD_Pos 8 /*!< SCU SFSP6_1: EHD Position */
+#define SCU_SFSP6_1_EHD_Msk (0x03UL << SCU_SFSP6_1_EHD_Pos) /*!< SCU SFSP6_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSP6_2 ------------------------------------------
+#define SCU_SFSP6_2_MODE_Pos 0 /*!< SCU SFSP6_2: MODE Position */
+#define SCU_SFSP6_2_MODE_Msk (0x07UL << SCU_SFSP6_2_MODE_Pos) /*!< SCU SFSP6_2: MODE Mask */
+#define SCU_SFSP6_2_EPD_Pos 3 /*!< SCU SFSP6_2: EPD Position */
+#define SCU_SFSP6_2_EPD_Msk (0x01UL << SCU_SFSP6_2_EPD_Pos) /*!< SCU SFSP6_2: EPD Mask */
+#define SCU_SFSP6_2_EPUN_Pos 4 /*!< SCU SFSP6_2: EPUN Position */
+#define SCU_SFSP6_2_EPUN_Msk (0x01UL << SCU_SFSP6_2_EPUN_Pos) /*!< SCU SFSP6_2: EPUN Mask */
+#define SCU_SFSP6_2_EHS_Pos 5 /*!< SCU SFSP6_2: EHS Position */
+#define SCU_SFSP6_2_EHS_Msk (0x01UL << SCU_SFSP6_2_EHS_Pos) /*!< SCU SFSP6_2: EHS Mask */
+#define SCU_SFSP6_2_EZI_Pos 6 /*!< SCU SFSP6_2: EZI Position */
+#define SCU_SFSP6_2_EZI_Msk (0x01UL << SCU_SFSP6_2_EZI_Pos) /*!< SCU SFSP6_2: EZI Mask */
+#define SCU_SFSP6_2_EHD_Pos 8 /*!< SCU SFSP6_2: EHD Position */
+#define SCU_SFSP6_2_EHD_Msk (0x03UL << SCU_SFSP6_2_EHD_Pos) /*!< SCU SFSP6_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSP6_3 ------------------------------------------
+#define SCU_SFSP6_3_MODE_Pos 0 /*!< SCU SFSP6_3: MODE Position */
+#define SCU_SFSP6_3_MODE_Msk (0x07UL << SCU_SFSP6_3_MODE_Pos) /*!< SCU SFSP6_3: MODE Mask */
+#define SCU_SFSP6_3_EPD_Pos 3 /*!< SCU SFSP6_3: EPD Position */
+#define SCU_SFSP6_3_EPD_Msk (0x01UL << SCU_SFSP6_3_EPD_Pos) /*!< SCU SFSP6_3: EPD Mask */
+#define SCU_SFSP6_3_EPUN_Pos 4 /*!< SCU SFSP6_3: EPUN Position */
+#define SCU_SFSP6_3_EPUN_Msk (0x01UL << SCU_SFSP6_3_EPUN_Pos) /*!< SCU SFSP6_3: EPUN Mask */
+#define SCU_SFSP6_3_EHS_Pos 5 /*!< SCU SFSP6_3: EHS Position */
+#define SCU_SFSP6_3_EHS_Msk (0x01UL << SCU_SFSP6_3_EHS_Pos) /*!< SCU SFSP6_3: EHS Mask */
+#define SCU_SFSP6_3_EZI_Pos 6 /*!< SCU SFSP6_3: EZI Position */
+#define SCU_SFSP6_3_EZI_Msk (0x01UL << SCU_SFSP6_3_EZI_Pos) /*!< SCU SFSP6_3: EZI Mask */
+#define SCU_SFSP6_3_EHD_Pos 8 /*!< SCU SFSP6_3: EHD Position */
+#define SCU_SFSP6_3_EHD_Msk (0x03UL << SCU_SFSP6_3_EHD_Pos) /*!< SCU SFSP6_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSP6_4 ------------------------------------------
+#define SCU_SFSP6_4_MODE_Pos 0 /*!< SCU SFSP6_4: MODE Position */
+#define SCU_SFSP6_4_MODE_Msk (0x07UL << SCU_SFSP6_4_MODE_Pos) /*!< SCU SFSP6_4: MODE Mask */
+#define SCU_SFSP6_4_EPD_Pos 3 /*!< SCU SFSP6_4: EPD Position */
+#define SCU_SFSP6_4_EPD_Msk (0x01UL << SCU_SFSP6_4_EPD_Pos) /*!< SCU SFSP6_4: EPD Mask */
+#define SCU_SFSP6_4_EPUN_Pos 4 /*!< SCU SFSP6_4: EPUN Position */
+#define SCU_SFSP6_4_EPUN_Msk (0x01UL << SCU_SFSP6_4_EPUN_Pos) /*!< SCU SFSP6_4: EPUN Mask */
+#define SCU_SFSP6_4_EHS_Pos 5 /*!< SCU SFSP6_4: EHS Position */
+#define SCU_SFSP6_4_EHS_Msk (0x01UL << SCU_SFSP6_4_EHS_Pos) /*!< SCU SFSP6_4: EHS Mask */
+#define SCU_SFSP6_4_EZI_Pos 6 /*!< SCU SFSP6_4: EZI Position */
+#define SCU_SFSP6_4_EZI_Msk (0x01UL << SCU_SFSP6_4_EZI_Pos) /*!< SCU SFSP6_4: EZI Mask */
+#define SCU_SFSP6_4_EHD_Pos 8 /*!< SCU SFSP6_4: EHD Position */
+#define SCU_SFSP6_4_EHD_Msk (0x03UL << SCU_SFSP6_4_EHD_Pos) /*!< SCU SFSP6_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSP6_5 ------------------------------------------
+#define SCU_SFSP6_5_MODE_Pos 0 /*!< SCU SFSP6_5: MODE Position */
+#define SCU_SFSP6_5_MODE_Msk (0x07UL << SCU_SFSP6_5_MODE_Pos) /*!< SCU SFSP6_5: MODE Mask */
+#define SCU_SFSP6_5_EPD_Pos 3 /*!< SCU SFSP6_5: EPD Position */
+#define SCU_SFSP6_5_EPD_Msk (0x01UL << SCU_SFSP6_5_EPD_Pos) /*!< SCU SFSP6_5: EPD Mask */
+#define SCU_SFSP6_5_EPUN_Pos 4 /*!< SCU SFSP6_5: EPUN Position */
+#define SCU_SFSP6_5_EPUN_Msk (0x01UL << SCU_SFSP6_5_EPUN_Pos) /*!< SCU SFSP6_5: EPUN Mask */
+#define SCU_SFSP6_5_EHS_Pos 5 /*!< SCU SFSP6_5: EHS Position */
+#define SCU_SFSP6_5_EHS_Msk (0x01UL << SCU_SFSP6_5_EHS_Pos) /*!< SCU SFSP6_5: EHS Mask */
+#define SCU_SFSP6_5_EZI_Pos 6 /*!< SCU SFSP6_5: EZI Position */
+#define SCU_SFSP6_5_EZI_Msk (0x01UL << SCU_SFSP6_5_EZI_Pos) /*!< SCU SFSP6_5: EZI Mask */
+#define SCU_SFSP6_5_EHD_Pos 8 /*!< SCU SFSP6_5: EHD Position */
+#define SCU_SFSP6_5_EHD_Msk (0x03UL << SCU_SFSP6_5_EHD_Pos) /*!< SCU SFSP6_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSP6_6 ------------------------------------------
+#define SCU_SFSP6_6_MODE_Pos 0 /*!< SCU SFSP6_6: MODE Position */
+#define SCU_SFSP6_6_MODE_Msk (0x07UL << SCU_SFSP6_6_MODE_Pos) /*!< SCU SFSP6_6: MODE Mask */
+#define SCU_SFSP6_6_EPD_Pos 3 /*!< SCU SFSP6_6: EPD Position */
+#define SCU_SFSP6_6_EPD_Msk (0x01UL << SCU_SFSP6_6_EPD_Pos) /*!< SCU SFSP6_6: EPD Mask */
+#define SCU_SFSP6_6_EPUN_Pos 4 /*!< SCU SFSP6_6: EPUN Position */
+#define SCU_SFSP6_6_EPUN_Msk (0x01UL << SCU_SFSP6_6_EPUN_Pos) /*!< SCU SFSP6_6: EPUN Mask */
+#define SCU_SFSP6_6_EHS_Pos 5 /*!< SCU SFSP6_6: EHS Position */
+#define SCU_SFSP6_6_EHS_Msk (0x01UL << SCU_SFSP6_6_EHS_Pos) /*!< SCU SFSP6_6: EHS Mask */
+#define SCU_SFSP6_6_EZI_Pos 6 /*!< SCU SFSP6_6: EZI Position */
+#define SCU_SFSP6_6_EZI_Msk (0x01UL << SCU_SFSP6_6_EZI_Pos) /*!< SCU SFSP6_6: EZI Mask */
+#define SCU_SFSP6_6_EHD_Pos 8 /*!< SCU SFSP6_6: EHD Position */
+#define SCU_SFSP6_6_EHD_Msk (0x03UL << SCU_SFSP6_6_EHD_Pos) /*!< SCU SFSP6_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSP6_7 ------------------------------------------
+#define SCU_SFSP6_7_MODE_Pos 0 /*!< SCU SFSP6_7: MODE Position */
+#define SCU_SFSP6_7_MODE_Msk (0x07UL << SCU_SFSP6_7_MODE_Pos) /*!< SCU SFSP6_7: MODE Mask */
+#define SCU_SFSP6_7_EPD_Pos 3 /*!< SCU SFSP6_7: EPD Position */
+#define SCU_SFSP6_7_EPD_Msk (0x01UL << SCU_SFSP6_7_EPD_Pos) /*!< SCU SFSP6_7: EPD Mask */
+#define SCU_SFSP6_7_EPUN_Pos 4 /*!< SCU SFSP6_7: EPUN Position */
+#define SCU_SFSP6_7_EPUN_Msk (0x01UL << SCU_SFSP6_7_EPUN_Pos) /*!< SCU SFSP6_7: EPUN Mask */
+#define SCU_SFSP6_7_EHS_Pos 5 /*!< SCU SFSP6_7: EHS Position */
+#define SCU_SFSP6_7_EHS_Msk (0x01UL << SCU_SFSP6_7_EHS_Pos) /*!< SCU SFSP6_7: EHS Mask */
+#define SCU_SFSP6_7_EZI_Pos 6 /*!< SCU SFSP6_7: EZI Position */
+#define SCU_SFSP6_7_EZI_Msk (0x01UL << SCU_SFSP6_7_EZI_Pos) /*!< SCU SFSP6_7: EZI Mask */
+#define SCU_SFSP6_7_EHD_Pos 8 /*!< SCU SFSP6_7: EHD Position */
+#define SCU_SFSP6_7_EHD_Msk (0x03UL << SCU_SFSP6_7_EHD_Pos) /*!< SCU SFSP6_7: EHD Mask */
+
+// --------------------------------------- SCU_SFSP6_8 ------------------------------------------
+#define SCU_SFSP6_8_MODE_Pos 0 /*!< SCU SFSP6_8: MODE Position */
+#define SCU_SFSP6_8_MODE_Msk (0x07UL << SCU_SFSP6_8_MODE_Pos) /*!< SCU SFSP6_8: MODE Mask */
+#define SCU_SFSP6_8_EPD_Pos 3 /*!< SCU SFSP6_8: EPD Position */
+#define SCU_SFSP6_8_EPD_Msk (0x01UL << SCU_SFSP6_8_EPD_Pos) /*!< SCU SFSP6_8: EPD Mask */
+#define SCU_SFSP6_8_EPUN_Pos 4 /*!< SCU SFSP6_8: EPUN Position */
+#define SCU_SFSP6_8_EPUN_Msk (0x01UL << SCU_SFSP6_8_EPUN_Pos) /*!< SCU SFSP6_8: EPUN Mask */
+#define SCU_SFSP6_8_EHS_Pos 5 /*!< SCU SFSP6_8: EHS Position */
+#define SCU_SFSP6_8_EHS_Msk (0x01UL << SCU_SFSP6_8_EHS_Pos) /*!< SCU SFSP6_8: EHS Mask */
+#define SCU_SFSP6_8_EZI_Pos 6 /*!< SCU SFSP6_8: EZI Position */
+#define SCU_SFSP6_8_EZI_Msk (0x01UL << SCU_SFSP6_8_EZI_Pos) /*!< SCU SFSP6_8: EZI Mask */
+#define SCU_SFSP6_8_EHD_Pos 8 /*!< SCU SFSP6_8: EHD Position */
+#define SCU_SFSP6_8_EHD_Msk (0x03UL << SCU_SFSP6_8_EHD_Pos) /*!< SCU SFSP6_8: EHD Mask */
+
+// --------------------------------------- SCU_SFSP6_9 ------------------------------------------
+#define SCU_SFSP6_9_MODE_Pos 0 /*!< SCU SFSP6_9: MODE Position */
+#define SCU_SFSP6_9_MODE_Msk (0x07UL << SCU_SFSP6_9_MODE_Pos) /*!< SCU SFSP6_9: MODE Mask */
+#define SCU_SFSP6_9_EPD_Pos 3 /*!< SCU SFSP6_9: EPD Position */
+#define SCU_SFSP6_9_EPD_Msk (0x01UL << SCU_SFSP6_9_EPD_Pos) /*!< SCU SFSP6_9: EPD Mask */
+#define SCU_SFSP6_9_EPUN_Pos 4 /*!< SCU SFSP6_9: EPUN Position */
+#define SCU_SFSP6_9_EPUN_Msk (0x01UL << SCU_SFSP6_9_EPUN_Pos) /*!< SCU SFSP6_9: EPUN Mask */
+#define SCU_SFSP6_9_EHS_Pos 5 /*!< SCU SFSP6_9: EHS Position */
+#define SCU_SFSP6_9_EHS_Msk (0x01UL << SCU_SFSP6_9_EHS_Pos) /*!< SCU SFSP6_9: EHS Mask */
+#define SCU_SFSP6_9_EZI_Pos 6 /*!< SCU SFSP6_9: EZI Position */
+#define SCU_SFSP6_9_EZI_Msk (0x01UL << SCU_SFSP6_9_EZI_Pos) /*!< SCU SFSP6_9: EZI Mask */
+#define SCU_SFSP6_9_EHD_Pos 8 /*!< SCU SFSP6_9: EHD Position */
+#define SCU_SFSP6_9_EHD_Msk (0x03UL << SCU_SFSP6_9_EHD_Pos) /*!< SCU SFSP6_9: EHD Mask */
+
+// -------------------------------------- SCU_SFSP6_10 ------------------------------------------
+#define SCU_SFSP6_10_MODE_Pos 0 /*!< SCU SFSP6_10: MODE Position */
+#define SCU_SFSP6_10_MODE_Msk (0x07UL << SCU_SFSP6_10_MODE_Pos) /*!< SCU SFSP6_10: MODE Mask */
+#define SCU_SFSP6_10_EPD_Pos 3 /*!< SCU SFSP6_10: EPD Position */
+#define SCU_SFSP6_10_EPD_Msk (0x01UL << SCU_SFSP6_10_EPD_Pos) /*!< SCU SFSP6_10: EPD Mask */
+#define SCU_SFSP6_10_EPUN_Pos 4 /*!< SCU SFSP6_10: EPUN Position */
+#define SCU_SFSP6_10_EPUN_Msk (0x01UL << SCU_SFSP6_10_EPUN_Pos) /*!< SCU SFSP6_10: EPUN Mask */
+#define SCU_SFSP6_10_EHS_Pos 5 /*!< SCU SFSP6_10: EHS Position */
+#define SCU_SFSP6_10_EHS_Msk (0x01UL << SCU_SFSP6_10_EHS_Pos) /*!< SCU SFSP6_10: EHS Mask */
+#define SCU_SFSP6_10_EZI_Pos 6 /*!< SCU SFSP6_10: EZI Position */
+#define SCU_SFSP6_10_EZI_Msk (0x01UL << SCU_SFSP6_10_EZI_Pos) /*!< SCU SFSP6_10: EZI Mask */
+#define SCU_SFSP6_10_EHD_Pos 8 /*!< SCU SFSP6_10: EHD Position */
+#define SCU_SFSP6_10_EHD_Msk (0x03UL << SCU_SFSP6_10_EHD_Pos) /*!< SCU SFSP6_10: EHD Mask */
+
+// -------------------------------------- SCU_SFSP6_11 ------------------------------------------
+#define SCU_SFSP6_11_MODE_Pos 0 /*!< SCU SFSP6_11: MODE Position */
+#define SCU_SFSP6_11_MODE_Msk (0x07UL << SCU_SFSP6_11_MODE_Pos) /*!< SCU SFSP6_11: MODE Mask */
+#define SCU_SFSP6_11_EPD_Pos 3 /*!< SCU SFSP6_11: EPD Position */
+#define SCU_SFSP6_11_EPD_Msk (0x01UL << SCU_SFSP6_11_EPD_Pos) /*!< SCU SFSP6_11: EPD Mask */
+#define SCU_SFSP6_11_EPUN_Pos 4 /*!< SCU SFSP6_11: EPUN Position */
+#define SCU_SFSP6_11_EPUN_Msk (0x01UL << SCU_SFSP6_11_EPUN_Pos) /*!< SCU SFSP6_11: EPUN Mask */
+#define SCU_SFSP6_11_EHS_Pos 5 /*!< SCU SFSP6_11: EHS Position */
+#define SCU_SFSP6_11_EHS_Msk (0x01UL << SCU_SFSP6_11_EHS_Pos) /*!< SCU SFSP6_11: EHS Mask */
+#define SCU_SFSP6_11_EZI_Pos 6 /*!< SCU SFSP6_11: EZI Position */
+#define SCU_SFSP6_11_EZI_Msk (0x01UL << SCU_SFSP6_11_EZI_Pos) /*!< SCU SFSP6_11: EZI Mask */
+#define SCU_SFSP6_11_EHD_Pos 8 /*!< SCU SFSP6_11: EHD Position */
+#define SCU_SFSP6_11_EHD_Msk (0x03UL << SCU_SFSP6_11_EHD_Pos) /*!< SCU SFSP6_11: EHD Mask */
+
+// -------------------------------------- SCU_SFSP6_12 ------------------------------------------
+#define SCU_SFSP6_12_MODE_Pos 0 /*!< SCU SFSP6_12: MODE Position */
+#define SCU_SFSP6_12_MODE_Msk (0x07UL << SCU_SFSP6_12_MODE_Pos) /*!< SCU SFSP6_12: MODE Mask */
+#define SCU_SFSP6_12_EPD_Pos 3 /*!< SCU SFSP6_12: EPD Position */
+#define SCU_SFSP6_12_EPD_Msk (0x01UL << SCU_SFSP6_12_EPD_Pos) /*!< SCU SFSP6_12: EPD Mask */
+#define SCU_SFSP6_12_EPUN_Pos 4 /*!< SCU SFSP6_12: EPUN Position */
+#define SCU_SFSP6_12_EPUN_Msk (0x01UL << SCU_SFSP6_12_EPUN_Pos) /*!< SCU SFSP6_12: EPUN Mask */
+#define SCU_SFSP6_12_EHS_Pos 5 /*!< SCU SFSP6_12: EHS Position */
+#define SCU_SFSP6_12_EHS_Msk (0x01UL << SCU_SFSP6_12_EHS_Pos) /*!< SCU SFSP6_12: EHS Mask */
+#define SCU_SFSP6_12_EZI_Pos 6 /*!< SCU SFSP6_12: EZI Position */
+#define SCU_SFSP6_12_EZI_Msk (0x01UL << SCU_SFSP6_12_EZI_Pos) /*!< SCU SFSP6_12: EZI Mask */
+#define SCU_SFSP6_12_EHD_Pos 8 /*!< SCU SFSP6_12: EHD Position */
+#define SCU_SFSP6_12_EHD_Msk (0x03UL << SCU_SFSP6_12_EHD_Pos) /*!< SCU SFSP6_12: EHD Mask */
+
+// --------------------------------------- SCU_SFSP7_0 ------------------------------------------
+#define SCU_SFSP7_0_MODE_Pos 0 /*!< SCU SFSP7_0: MODE Position */
+#define SCU_SFSP7_0_MODE_Msk (0x07UL << SCU_SFSP7_0_MODE_Pos) /*!< SCU SFSP7_0: MODE Mask */
+#define SCU_SFSP7_0_EPD_Pos 3 /*!< SCU SFSP7_0: EPD Position */
+#define SCU_SFSP7_0_EPD_Msk (0x01UL << SCU_SFSP7_0_EPD_Pos) /*!< SCU SFSP7_0: EPD Mask */
+#define SCU_SFSP7_0_EPUN_Pos 4 /*!< SCU SFSP7_0: EPUN Position */
+#define SCU_SFSP7_0_EPUN_Msk (0x01UL << SCU_SFSP7_0_EPUN_Pos) /*!< SCU SFSP7_0: EPUN Mask */
+#define SCU_SFSP7_0_EHS_Pos 5 /*!< SCU SFSP7_0: EHS Position */
+#define SCU_SFSP7_0_EHS_Msk (0x01UL << SCU_SFSP7_0_EHS_Pos) /*!< SCU SFSP7_0: EHS Mask */
+#define SCU_SFSP7_0_EZI_Pos 6 /*!< SCU SFSP7_0: EZI Position */
+#define SCU_SFSP7_0_EZI_Msk (0x01UL << SCU_SFSP7_0_EZI_Pos) /*!< SCU SFSP7_0: EZI Mask */
+#define SCU_SFSP7_0_EHD_Pos 8 /*!< SCU SFSP7_0: EHD Position */
+#define SCU_SFSP7_0_EHD_Msk (0x03UL << SCU_SFSP7_0_EHD_Pos) /*!< SCU SFSP7_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSP7_1 ------------------------------------------
+#define SCU_SFSP7_1_MODE_Pos 0 /*!< SCU SFSP7_1: MODE Position */
+#define SCU_SFSP7_1_MODE_Msk (0x07UL << SCU_SFSP7_1_MODE_Pos) /*!< SCU SFSP7_1: MODE Mask */
+#define SCU_SFSP7_1_EPD_Pos 3 /*!< SCU SFSP7_1: EPD Position */
+#define SCU_SFSP7_1_EPD_Msk (0x01UL << SCU_SFSP7_1_EPD_Pos) /*!< SCU SFSP7_1: EPD Mask */
+#define SCU_SFSP7_1_EPUN_Pos 4 /*!< SCU SFSP7_1: EPUN Position */
+#define SCU_SFSP7_1_EPUN_Msk (0x01UL << SCU_SFSP7_1_EPUN_Pos) /*!< SCU SFSP7_1: EPUN Mask */
+#define SCU_SFSP7_1_EHS_Pos 5 /*!< SCU SFSP7_1: EHS Position */
+#define SCU_SFSP7_1_EHS_Msk (0x01UL << SCU_SFSP7_1_EHS_Pos) /*!< SCU SFSP7_1: EHS Mask */
+#define SCU_SFSP7_1_EZI_Pos 6 /*!< SCU SFSP7_1: EZI Position */
+#define SCU_SFSP7_1_EZI_Msk (0x01UL << SCU_SFSP7_1_EZI_Pos) /*!< SCU SFSP7_1: EZI Mask */
+#define SCU_SFSP7_1_EHD_Pos 8 /*!< SCU SFSP7_1: EHD Position */
+#define SCU_SFSP7_1_EHD_Msk (0x03UL << SCU_SFSP7_1_EHD_Pos) /*!< SCU SFSP7_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSP7_2 ------------------------------------------
+#define SCU_SFSP7_2_MODE_Pos 0 /*!< SCU SFSP7_2: MODE Position */
+#define SCU_SFSP7_2_MODE_Msk (0x07UL << SCU_SFSP7_2_MODE_Pos) /*!< SCU SFSP7_2: MODE Mask */
+#define SCU_SFSP7_2_EPD_Pos 3 /*!< SCU SFSP7_2: EPD Position */
+#define SCU_SFSP7_2_EPD_Msk (0x01UL << SCU_SFSP7_2_EPD_Pos) /*!< SCU SFSP7_2: EPD Mask */
+#define SCU_SFSP7_2_EPUN_Pos 4 /*!< SCU SFSP7_2: EPUN Position */
+#define SCU_SFSP7_2_EPUN_Msk (0x01UL << SCU_SFSP7_2_EPUN_Pos) /*!< SCU SFSP7_2: EPUN Mask */
+#define SCU_SFSP7_2_EHS_Pos 5 /*!< SCU SFSP7_2: EHS Position */
+#define SCU_SFSP7_2_EHS_Msk (0x01UL << SCU_SFSP7_2_EHS_Pos) /*!< SCU SFSP7_2: EHS Mask */
+#define SCU_SFSP7_2_EZI_Pos 6 /*!< SCU SFSP7_2: EZI Position */
+#define SCU_SFSP7_2_EZI_Msk (0x01UL << SCU_SFSP7_2_EZI_Pos) /*!< SCU SFSP7_2: EZI Mask */
+#define SCU_SFSP7_2_EHD_Pos 8 /*!< SCU SFSP7_2: EHD Position */
+#define SCU_SFSP7_2_EHD_Msk (0x03UL << SCU_SFSP7_2_EHD_Pos) /*!< SCU SFSP7_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSP7_3 ------------------------------------------
+#define SCU_SFSP7_3_MODE_Pos 0 /*!< SCU SFSP7_3: MODE Position */
+#define SCU_SFSP7_3_MODE_Msk (0x07UL << SCU_SFSP7_3_MODE_Pos) /*!< SCU SFSP7_3: MODE Mask */
+#define SCU_SFSP7_3_EPD_Pos 3 /*!< SCU SFSP7_3: EPD Position */
+#define SCU_SFSP7_3_EPD_Msk (0x01UL << SCU_SFSP7_3_EPD_Pos) /*!< SCU SFSP7_3: EPD Mask */
+#define SCU_SFSP7_3_EPUN_Pos 4 /*!< SCU SFSP7_3: EPUN Position */
+#define SCU_SFSP7_3_EPUN_Msk (0x01UL << SCU_SFSP7_3_EPUN_Pos) /*!< SCU SFSP7_3: EPUN Mask */
+#define SCU_SFSP7_3_EHS_Pos 5 /*!< SCU SFSP7_3: EHS Position */
+#define SCU_SFSP7_3_EHS_Msk (0x01UL << SCU_SFSP7_3_EHS_Pos) /*!< SCU SFSP7_3: EHS Mask */
+#define SCU_SFSP7_3_EZI_Pos 6 /*!< SCU SFSP7_3: EZI Position */
+#define SCU_SFSP7_3_EZI_Msk (0x01UL << SCU_SFSP7_3_EZI_Pos) /*!< SCU SFSP7_3: EZI Mask */
+#define SCU_SFSP7_3_EHD_Pos 8 /*!< SCU SFSP7_3: EHD Position */
+#define SCU_SFSP7_3_EHD_Msk (0x03UL << SCU_SFSP7_3_EHD_Pos) /*!< SCU SFSP7_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSP7_4 ------------------------------------------
+#define SCU_SFSP7_4_MODE_Pos 0 /*!< SCU SFSP7_4: MODE Position */
+#define SCU_SFSP7_4_MODE_Msk (0x07UL << SCU_SFSP7_4_MODE_Pos) /*!< SCU SFSP7_4: MODE Mask */
+#define SCU_SFSP7_4_EPD_Pos 3 /*!< SCU SFSP7_4: EPD Position */
+#define SCU_SFSP7_4_EPD_Msk (0x01UL << SCU_SFSP7_4_EPD_Pos) /*!< SCU SFSP7_4: EPD Mask */
+#define SCU_SFSP7_4_EPUN_Pos 4 /*!< SCU SFSP7_4: EPUN Position */
+#define SCU_SFSP7_4_EPUN_Msk (0x01UL << SCU_SFSP7_4_EPUN_Pos) /*!< SCU SFSP7_4: EPUN Mask */
+#define SCU_SFSP7_4_EHS_Pos 5 /*!< SCU SFSP7_4: EHS Position */
+#define SCU_SFSP7_4_EHS_Msk (0x01UL << SCU_SFSP7_4_EHS_Pos) /*!< SCU SFSP7_4: EHS Mask */
+#define SCU_SFSP7_4_EZI_Pos 6 /*!< SCU SFSP7_4: EZI Position */
+#define SCU_SFSP7_4_EZI_Msk (0x01UL << SCU_SFSP7_4_EZI_Pos) /*!< SCU SFSP7_4: EZI Mask */
+#define SCU_SFSP7_4_EHD_Pos 8 /*!< SCU SFSP7_4: EHD Position */
+#define SCU_SFSP7_4_EHD_Msk (0x03UL << SCU_SFSP7_4_EHD_Pos) /*!< SCU SFSP7_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSP7_5 ------------------------------------------
+#define SCU_SFSP7_5_MODE_Pos 0 /*!< SCU SFSP7_5: MODE Position */
+#define SCU_SFSP7_5_MODE_Msk (0x07UL << SCU_SFSP7_5_MODE_Pos) /*!< SCU SFSP7_5: MODE Mask */
+#define SCU_SFSP7_5_EPD_Pos 3 /*!< SCU SFSP7_5: EPD Position */
+#define SCU_SFSP7_5_EPD_Msk (0x01UL << SCU_SFSP7_5_EPD_Pos) /*!< SCU SFSP7_5: EPD Mask */
+#define SCU_SFSP7_5_EPUN_Pos 4 /*!< SCU SFSP7_5: EPUN Position */
+#define SCU_SFSP7_5_EPUN_Msk (0x01UL << SCU_SFSP7_5_EPUN_Pos) /*!< SCU SFSP7_5: EPUN Mask */
+#define SCU_SFSP7_5_EHS_Pos 5 /*!< SCU SFSP7_5: EHS Position */
+#define SCU_SFSP7_5_EHS_Msk (0x01UL << SCU_SFSP7_5_EHS_Pos) /*!< SCU SFSP7_5: EHS Mask */
+#define SCU_SFSP7_5_EZI_Pos 6 /*!< SCU SFSP7_5: EZI Position */
+#define SCU_SFSP7_5_EZI_Msk (0x01UL << SCU_SFSP7_5_EZI_Pos) /*!< SCU SFSP7_5: EZI Mask */
+#define SCU_SFSP7_5_EHD_Pos 8 /*!< SCU SFSP7_5: EHD Position */
+#define SCU_SFSP7_5_EHD_Msk (0x03UL << SCU_SFSP7_5_EHD_Pos) /*!< SCU SFSP7_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSP7_6 ------------------------------------------
+#define SCU_SFSP7_6_MODE_Pos 0 /*!< SCU SFSP7_6: MODE Position */
+#define SCU_SFSP7_6_MODE_Msk (0x07UL << SCU_SFSP7_6_MODE_Pos) /*!< SCU SFSP7_6: MODE Mask */
+#define SCU_SFSP7_6_EPD_Pos 3 /*!< SCU SFSP7_6: EPD Position */
+#define SCU_SFSP7_6_EPD_Msk (0x01UL << SCU_SFSP7_6_EPD_Pos) /*!< SCU SFSP7_6: EPD Mask */
+#define SCU_SFSP7_6_EPUN_Pos 4 /*!< SCU SFSP7_6: EPUN Position */
+#define SCU_SFSP7_6_EPUN_Msk (0x01UL << SCU_SFSP7_6_EPUN_Pos) /*!< SCU SFSP7_6: EPUN Mask */
+#define SCU_SFSP7_6_EHS_Pos 5 /*!< SCU SFSP7_6: EHS Position */
+#define SCU_SFSP7_6_EHS_Msk (0x01UL << SCU_SFSP7_6_EHS_Pos) /*!< SCU SFSP7_6: EHS Mask */
+#define SCU_SFSP7_6_EZI_Pos 6 /*!< SCU SFSP7_6: EZI Position */
+#define SCU_SFSP7_6_EZI_Msk (0x01UL << SCU_SFSP7_6_EZI_Pos) /*!< SCU SFSP7_6: EZI Mask */
+#define SCU_SFSP7_6_EHD_Pos 8 /*!< SCU SFSP7_6: EHD Position */
+#define SCU_SFSP7_6_EHD_Msk (0x03UL << SCU_SFSP7_6_EHD_Pos) /*!< SCU SFSP7_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSP7_7 ------------------------------------------
+#define SCU_SFSP7_7_MODE_Pos 0 /*!< SCU SFSP7_7: MODE Position */
+#define SCU_SFSP7_7_MODE_Msk (0x07UL << SCU_SFSP7_7_MODE_Pos) /*!< SCU SFSP7_7: MODE Mask */
+#define SCU_SFSP7_7_EPD_Pos 3 /*!< SCU SFSP7_7: EPD Position */
+#define SCU_SFSP7_7_EPD_Msk (0x01UL << SCU_SFSP7_7_EPD_Pos) /*!< SCU SFSP7_7: EPD Mask */
+#define SCU_SFSP7_7_EPUN_Pos 4 /*!< SCU SFSP7_7: EPUN Position */
+#define SCU_SFSP7_7_EPUN_Msk (0x01UL << SCU_SFSP7_7_EPUN_Pos) /*!< SCU SFSP7_7: EPUN Mask */
+#define SCU_SFSP7_7_EHS_Pos 5 /*!< SCU SFSP7_7: EHS Position */
+#define SCU_SFSP7_7_EHS_Msk (0x01UL << SCU_SFSP7_7_EHS_Pos) /*!< SCU SFSP7_7: EHS Mask */
+#define SCU_SFSP7_7_EZI_Pos 6 /*!< SCU SFSP7_7: EZI Position */
+#define SCU_SFSP7_7_EZI_Msk (0x01UL << SCU_SFSP7_7_EZI_Pos) /*!< SCU SFSP7_7: EZI Mask */
+#define SCU_SFSP7_7_EHD_Pos 8 /*!< SCU SFSP7_7: EHD Position */
+#define SCU_SFSP7_7_EHD_Msk (0x03UL << SCU_SFSP7_7_EHD_Pos) /*!< SCU SFSP7_7: EHD Mask */
+
+// --------------------------------------- SCU_SFSP8_0 ------------------------------------------
+#define SCU_SFSP8_0_MODE_Pos 0 /*!< SCU SFSP8_0: MODE Position */
+#define SCU_SFSP8_0_MODE_Msk (0x07UL << SCU_SFSP8_0_MODE_Pos) /*!< SCU SFSP8_0: MODE Mask */
+#define SCU_SFSP8_0_EPD_Pos 3 /*!< SCU SFSP8_0: EPD Position */
+#define SCU_SFSP8_0_EPD_Msk (0x01UL << SCU_SFSP8_0_EPD_Pos) /*!< SCU SFSP8_0: EPD Mask */
+#define SCU_SFSP8_0_EPUN_Pos 4 /*!< SCU SFSP8_0: EPUN Position */
+#define SCU_SFSP8_0_EPUN_Msk (0x01UL << SCU_SFSP8_0_EPUN_Pos) /*!< SCU SFSP8_0: EPUN Mask */
+#define SCU_SFSP8_0_EHS_Pos 5 /*!< SCU SFSP8_0: EHS Position */
+#define SCU_SFSP8_0_EHS_Msk (0x01UL << SCU_SFSP8_0_EHS_Pos) /*!< SCU SFSP8_0: EHS Mask */
+#define SCU_SFSP8_0_EZI_Pos 6 /*!< SCU SFSP8_0: EZI Position */
+#define SCU_SFSP8_0_EZI_Msk (0x01UL << SCU_SFSP8_0_EZI_Pos) /*!< SCU SFSP8_0: EZI Mask */
+#define SCU_SFSP8_0_EHD_Pos 8 /*!< SCU SFSP8_0: EHD Position */
+#define SCU_SFSP8_0_EHD_Msk (0x03UL << SCU_SFSP8_0_EHD_Pos) /*!< SCU SFSP8_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSP8_1 ------------------------------------------
+#define SCU_SFSP8_1_MODE_Pos 0 /*!< SCU SFSP8_1: MODE Position */
+#define SCU_SFSP8_1_MODE_Msk (0x07UL << SCU_SFSP8_1_MODE_Pos) /*!< SCU SFSP8_1: MODE Mask */
+#define SCU_SFSP8_1_EPD_Pos 3 /*!< SCU SFSP8_1: EPD Position */
+#define SCU_SFSP8_1_EPD_Msk (0x01UL << SCU_SFSP8_1_EPD_Pos) /*!< SCU SFSP8_1: EPD Mask */
+#define SCU_SFSP8_1_EPUN_Pos 4 /*!< SCU SFSP8_1: EPUN Position */
+#define SCU_SFSP8_1_EPUN_Msk (0x01UL << SCU_SFSP8_1_EPUN_Pos) /*!< SCU SFSP8_1: EPUN Mask */
+#define SCU_SFSP8_1_EHS_Pos 5 /*!< SCU SFSP8_1: EHS Position */
+#define SCU_SFSP8_1_EHS_Msk (0x01UL << SCU_SFSP8_1_EHS_Pos) /*!< SCU SFSP8_1: EHS Mask */
+#define SCU_SFSP8_1_EZI_Pos 6 /*!< SCU SFSP8_1: EZI Position */
+#define SCU_SFSP8_1_EZI_Msk (0x01UL << SCU_SFSP8_1_EZI_Pos) /*!< SCU SFSP8_1: EZI Mask */
+#define SCU_SFSP8_1_EHD_Pos 8 /*!< SCU SFSP8_1: EHD Position */
+#define SCU_SFSP8_1_EHD_Msk (0x03UL << SCU_SFSP8_1_EHD_Pos) /*!< SCU SFSP8_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSP8_2 ------------------------------------------
+#define SCU_SFSP8_2_MODE_Pos 0 /*!< SCU SFSP8_2: MODE Position */
+#define SCU_SFSP8_2_MODE_Msk (0x07UL << SCU_SFSP8_2_MODE_Pos) /*!< SCU SFSP8_2: MODE Mask */
+#define SCU_SFSP8_2_EPD_Pos 3 /*!< SCU SFSP8_2: EPD Position */
+#define SCU_SFSP8_2_EPD_Msk (0x01UL << SCU_SFSP8_2_EPD_Pos) /*!< SCU SFSP8_2: EPD Mask */
+#define SCU_SFSP8_2_EPUN_Pos 4 /*!< SCU SFSP8_2: EPUN Position */
+#define SCU_SFSP8_2_EPUN_Msk (0x01UL << SCU_SFSP8_2_EPUN_Pos) /*!< SCU SFSP8_2: EPUN Mask */
+#define SCU_SFSP8_2_EHS_Pos 5 /*!< SCU SFSP8_2: EHS Position */
+#define SCU_SFSP8_2_EHS_Msk (0x01UL << SCU_SFSP8_2_EHS_Pos) /*!< SCU SFSP8_2: EHS Mask */
+#define SCU_SFSP8_2_EZI_Pos 6 /*!< SCU SFSP8_2: EZI Position */
+#define SCU_SFSP8_2_EZI_Msk (0x01UL << SCU_SFSP8_2_EZI_Pos) /*!< SCU SFSP8_2: EZI Mask */
+#define SCU_SFSP8_2_EHD_Pos 8 /*!< SCU SFSP8_2: EHD Position */
+#define SCU_SFSP8_2_EHD_Msk (0x03UL << SCU_SFSP8_2_EHD_Pos) /*!< SCU SFSP8_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSP8_3 ------------------------------------------
+#define SCU_SFSP8_3_MODE_Pos 0 /*!< SCU SFSP8_3: MODE Position */
+#define SCU_SFSP8_3_MODE_Msk (0x07UL << SCU_SFSP8_3_MODE_Pos) /*!< SCU SFSP8_3: MODE Mask */
+#define SCU_SFSP8_3_EPD_Pos 3 /*!< SCU SFSP8_3: EPD Position */
+#define SCU_SFSP8_3_EPD_Msk (0x01UL << SCU_SFSP8_3_EPD_Pos) /*!< SCU SFSP8_3: EPD Mask */
+#define SCU_SFSP8_3_EPUN_Pos 4 /*!< SCU SFSP8_3: EPUN Position */
+#define SCU_SFSP8_3_EPUN_Msk (0x01UL << SCU_SFSP8_3_EPUN_Pos) /*!< SCU SFSP8_3: EPUN Mask */
+#define SCU_SFSP8_3_EHS_Pos 5 /*!< SCU SFSP8_3: EHS Position */
+#define SCU_SFSP8_3_EHS_Msk (0x01UL << SCU_SFSP8_3_EHS_Pos) /*!< SCU SFSP8_3: EHS Mask */
+#define SCU_SFSP8_3_EZI_Pos 6 /*!< SCU SFSP8_3: EZI Position */
+#define SCU_SFSP8_3_EZI_Msk (0x01UL << SCU_SFSP8_3_EZI_Pos) /*!< SCU SFSP8_3: EZI Mask */
+#define SCU_SFSP8_3_EHD_Pos 8 /*!< SCU SFSP8_3: EHD Position */
+#define SCU_SFSP8_3_EHD_Msk (0x03UL << SCU_SFSP8_3_EHD_Pos) /*!< SCU SFSP8_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSP8_4 ------------------------------------------
+#define SCU_SFSP8_4_MODE_Pos 0 /*!< SCU SFSP8_4: MODE Position */
+#define SCU_SFSP8_4_MODE_Msk (0x07UL << SCU_SFSP8_4_MODE_Pos) /*!< SCU SFSP8_4: MODE Mask */
+#define SCU_SFSP8_4_EPD_Pos 3 /*!< SCU SFSP8_4: EPD Position */
+#define SCU_SFSP8_4_EPD_Msk (0x01UL << SCU_SFSP8_4_EPD_Pos) /*!< SCU SFSP8_4: EPD Mask */
+#define SCU_SFSP8_4_EPUN_Pos 4 /*!< SCU SFSP8_4: EPUN Position */
+#define SCU_SFSP8_4_EPUN_Msk (0x01UL << SCU_SFSP8_4_EPUN_Pos) /*!< SCU SFSP8_4: EPUN Mask */
+#define SCU_SFSP8_4_EHS_Pos 5 /*!< SCU SFSP8_4: EHS Position */
+#define SCU_SFSP8_4_EHS_Msk (0x01UL << SCU_SFSP8_4_EHS_Pos) /*!< SCU SFSP8_4: EHS Mask */
+#define SCU_SFSP8_4_EZI_Pos 6 /*!< SCU SFSP8_4: EZI Position */
+#define SCU_SFSP8_4_EZI_Msk (0x01UL << SCU_SFSP8_4_EZI_Pos) /*!< SCU SFSP8_4: EZI Mask */
+#define SCU_SFSP8_4_EHD_Pos 8 /*!< SCU SFSP8_4: EHD Position */
+#define SCU_SFSP8_4_EHD_Msk (0x03UL << SCU_SFSP8_4_EHD_Pos) /*!< SCU SFSP8_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSP8_5 ------------------------------------------
+#define SCU_SFSP8_5_MODE_Pos 0 /*!< SCU SFSP8_5: MODE Position */
+#define SCU_SFSP8_5_MODE_Msk (0x07UL << SCU_SFSP8_5_MODE_Pos) /*!< SCU SFSP8_5: MODE Mask */
+#define SCU_SFSP8_5_EPD_Pos 3 /*!< SCU SFSP8_5: EPD Position */
+#define SCU_SFSP8_5_EPD_Msk (0x01UL << SCU_SFSP8_5_EPD_Pos) /*!< SCU SFSP8_5: EPD Mask */
+#define SCU_SFSP8_5_EPUN_Pos 4 /*!< SCU SFSP8_5: EPUN Position */
+#define SCU_SFSP8_5_EPUN_Msk (0x01UL << SCU_SFSP8_5_EPUN_Pos) /*!< SCU SFSP8_5: EPUN Mask */
+#define SCU_SFSP8_5_EHS_Pos 5 /*!< SCU SFSP8_5: EHS Position */
+#define SCU_SFSP8_5_EHS_Msk (0x01UL << SCU_SFSP8_5_EHS_Pos) /*!< SCU SFSP8_5: EHS Mask */
+#define SCU_SFSP8_5_EZI_Pos 6 /*!< SCU SFSP8_5: EZI Position */
+#define SCU_SFSP8_5_EZI_Msk (0x01UL << SCU_SFSP8_5_EZI_Pos) /*!< SCU SFSP8_5: EZI Mask */
+#define SCU_SFSP8_5_EHD_Pos 8 /*!< SCU SFSP8_5: EHD Position */
+#define SCU_SFSP8_5_EHD_Msk (0x03UL << SCU_SFSP8_5_EHD_Pos) /*!< SCU SFSP8_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSP8_6 ------------------------------------------
+#define SCU_SFSP8_6_MODE_Pos 0 /*!< SCU SFSP8_6: MODE Position */
+#define SCU_SFSP8_6_MODE_Msk (0x07UL << SCU_SFSP8_6_MODE_Pos) /*!< SCU SFSP8_6: MODE Mask */
+#define SCU_SFSP8_6_EPD_Pos 3 /*!< SCU SFSP8_6: EPD Position */
+#define SCU_SFSP8_6_EPD_Msk (0x01UL << SCU_SFSP8_6_EPD_Pos) /*!< SCU SFSP8_6: EPD Mask */
+#define SCU_SFSP8_6_EPUN_Pos 4 /*!< SCU SFSP8_6: EPUN Position */
+#define SCU_SFSP8_6_EPUN_Msk (0x01UL << SCU_SFSP8_6_EPUN_Pos) /*!< SCU SFSP8_6: EPUN Mask */
+#define SCU_SFSP8_6_EHS_Pos 5 /*!< SCU SFSP8_6: EHS Position */
+#define SCU_SFSP8_6_EHS_Msk (0x01UL << SCU_SFSP8_6_EHS_Pos) /*!< SCU SFSP8_6: EHS Mask */
+#define SCU_SFSP8_6_EZI_Pos 6 /*!< SCU SFSP8_6: EZI Position */
+#define SCU_SFSP8_6_EZI_Msk (0x01UL << SCU_SFSP8_6_EZI_Pos) /*!< SCU SFSP8_6: EZI Mask */
+#define SCU_SFSP8_6_EHD_Pos 8 /*!< SCU SFSP8_6: EHD Position */
+#define SCU_SFSP8_6_EHD_Msk (0x03UL << SCU_SFSP8_6_EHD_Pos) /*!< SCU SFSP8_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSP8_7 ------------------------------------------
+#define SCU_SFSP8_7_MODE_Pos 0 /*!< SCU SFSP8_7: MODE Position */
+#define SCU_SFSP8_7_MODE_Msk (0x07UL << SCU_SFSP8_7_MODE_Pos) /*!< SCU SFSP8_7: MODE Mask */
+#define SCU_SFSP8_7_EPD_Pos 3 /*!< SCU SFSP8_7: EPD Position */
+#define SCU_SFSP8_7_EPD_Msk (0x01UL << SCU_SFSP8_7_EPD_Pos) /*!< SCU SFSP8_7: EPD Mask */
+#define SCU_SFSP8_7_EPUN_Pos 4 /*!< SCU SFSP8_7: EPUN Position */
+#define SCU_SFSP8_7_EPUN_Msk (0x01UL << SCU_SFSP8_7_EPUN_Pos) /*!< SCU SFSP8_7: EPUN Mask */
+#define SCU_SFSP8_7_EHS_Pos 5 /*!< SCU SFSP8_7: EHS Position */
+#define SCU_SFSP8_7_EHS_Msk (0x01UL << SCU_SFSP8_7_EHS_Pos) /*!< SCU SFSP8_7: EHS Mask */
+#define SCU_SFSP8_7_EZI_Pos 6 /*!< SCU SFSP8_7: EZI Position */
+#define SCU_SFSP8_7_EZI_Msk (0x01UL << SCU_SFSP8_7_EZI_Pos) /*!< SCU SFSP8_7: EZI Mask */
+#define SCU_SFSP8_7_EHD_Pos 8 /*!< SCU SFSP8_7: EHD Position */
+#define SCU_SFSP8_7_EHD_Msk (0x03UL << SCU_SFSP8_7_EHD_Pos) /*!< SCU SFSP8_7: EHD Mask */
+
+// --------------------------------------- SCU_SFSP8_8 ------------------------------------------
+#define SCU_SFSP8_8_MODE_Pos 0 /*!< SCU SFSP8_8: MODE Position */
+#define SCU_SFSP8_8_MODE_Msk (0x07UL << SCU_SFSP8_8_MODE_Pos) /*!< SCU SFSP8_8: MODE Mask */
+#define SCU_SFSP8_8_EPD_Pos 3 /*!< SCU SFSP8_8: EPD Position */
+#define SCU_SFSP8_8_EPD_Msk (0x01UL << SCU_SFSP8_8_EPD_Pos) /*!< SCU SFSP8_8: EPD Mask */
+#define SCU_SFSP8_8_EPUN_Pos 4 /*!< SCU SFSP8_8: EPUN Position */
+#define SCU_SFSP8_8_EPUN_Msk (0x01UL << SCU_SFSP8_8_EPUN_Pos) /*!< SCU SFSP8_8: EPUN Mask */
+#define SCU_SFSP8_8_EHS_Pos 5 /*!< SCU SFSP8_8: EHS Position */
+#define SCU_SFSP8_8_EHS_Msk (0x01UL << SCU_SFSP8_8_EHS_Pos) /*!< SCU SFSP8_8: EHS Mask */
+#define SCU_SFSP8_8_EZI_Pos 6 /*!< SCU SFSP8_8: EZI Position */
+#define SCU_SFSP8_8_EZI_Msk (0x01UL << SCU_SFSP8_8_EZI_Pos) /*!< SCU SFSP8_8: EZI Mask */
+#define SCU_SFSP8_8_EHD_Pos 8 /*!< SCU SFSP8_8: EHD Position */
+#define SCU_SFSP8_8_EHD_Msk (0x03UL << SCU_SFSP8_8_EHD_Pos) /*!< SCU SFSP8_8: EHD Mask */
+
+// --------------------------------------- SCU_SFSP9_0 ------------------------------------------
+#define SCU_SFSP9_0_MODE_Pos 0 /*!< SCU SFSP9_0: MODE Position */
+#define SCU_SFSP9_0_MODE_Msk (0x07UL << SCU_SFSP9_0_MODE_Pos) /*!< SCU SFSP9_0: MODE Mask */
+#define SCU_SFSP9_0_EPD_Pos 3 /*!< SCU SFSP9_0: EPD Position */
+#define SCU_SFSP9_0_EPD_Msk (0x01UL << SCU_SFSP9_0_EPD_Pos) /*!< SCU SFSP9_0: EPD Mask */
+#define SCU_SFSP9_0_EPUN_Pos 4 /*!< SCU SFSP9_0: EPUN Position */
+#define SCU_SFSP9_0_EPUN_Msk (0x01UL << SCU_SFSP9_0_EPUN_Pos) /*!< SCU SFSP9_0: EPUN Mask */
+#define SCU_SFSP9_0_EHS_Pos 5 /*!< SCU SFSP9_0: EHS Position */
+#define SCU_SFSP9_0_EHS_Msk (0x01UL << SCU_SFSP9_0_EHS_Pos) /*!< SCU SFSP9_0: EHS Mask */
+#define SCU_SFSP9_0_EZI_Pos 6 /*!< SCU SFSP9_0: EZI Position */
+#define SCU_SFSP9_0_EZI_Msk (0x01UL << SCU_SFSP9_0_EZI_Pos) /*!< SCU SFSP9_0: EZI Mask */
+#define SCU_SFSP9_0_EHD_Pos 8 /*!< SCU SFSP9_0: EHD Position */
+#define SCU_SFSP9_0_EHD_Msk (0x03UL << SCU_SFSP9_0_EHD_Pos) /*!< SCU SFSP9_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSP9_1 ------------------------------------------
+#define SCU_SFSP9_1_MODE_Pos 0 /*!< SCU SFSP9_1: MODE Position */
+#define SCU_SFSP9_1_MODE_Msk (0x07UL << SCU_SFSP9_1_MODE_Pos) /*!< SCU SFSP9_1: MODE Mask */
+#define SCU_SFSP9_1_EPD_Pos 3 /*!< SCU SFSP9_1: EPD Position */
+#define SCU_SFSP9_1_EPD_Msk (0x01UL << SCU_SFSP9_1_EPD_Pos) /*!< SCU SFSP9_1: EPD Mask */
+#define SCU_SFSP9_1_EPUN_Pos 4 /*!< SCU SFSP9_1: EPUN Position */
+#define SCU_SFSP9_1_EPUN_Msk (0x01UL << SCU_SFSP9_1_EPUN_Pos) /*!< SCU SFSP9_1: EPUN Mask */
+#define SCU_SFSP9_1_EHS_Pos 5 /*!< SCU SFSP9_1: EHS Position */
+#define SCU_SFSP9_1_EHS_Msk (0x01UL << SCU_SFSP9_1_EHS_Pos) /*!< SCU SFSP9_1: EHS Mask */
+#define SCU_SFSP9_1_EZI_Pos 6 /*!< SCU SFSP9_1: EZI Position */
+#define SCU_SFSP9_1_EZI_Msk (0x01UL << SCU_SFSP9_1_EZI_Pos) /*!< SCU SFSP9_1: EZI Mask */
+#define SCU_SFSP9_1_EHD_Pos 8 /*!< SCU SFSP9_1: EHD Position */
+#define SCU_SFSP9_1_EHD_Msk (0x03UL << SCU_SFSP9_1_EHD_Pos) /*!< SCU SFSP9_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSP9_2 ------------------------------------------
+#define SCU_SFSP9_2_MODE_Pos 0 /*!< SCU SFSP9_2: MODE Position */
+#define SCU_SFSP9_2_MODE_Msk (0x07UL << SCU_SFSP9_2_MODE_Pos) /*!< SCU SFSP9_2: MODE Mask */
+#define SCU_SFSP9_2_EPD_Pos 3 /*!< SCU SFSP9_2: EPD Position */
+#define SCU_SFSP9_2_EPD_Msk (0x01UL << SCU_SFSP9_2_EPD_Pos) /*!< SCU SFSP9_2: EPD Mask */
+#define SCU_SFSP9_2_EPUN_Pos 4 /*!< SCU SFSP9_2: EPUN Position */
+#define SCU_SFSP9_2_EPUN_Msk (0x01UL << SCU_SFSP9_2_EPUN_Pos) /*!< SCU SFSP9_2: EPUN Mask */
+#define SCU_SFSP9_2_EHS_Pos 5 /*!< SCU SFSP9_2: EHS Position */
+#define SCU_SFSP9_2_EHS_Msk (0x01UL << SCU_SFSP9_2_EHS_Pos) /*!< SCU SFSP9_2: EHS Mask */
+#define SCU_SFSP9_2_EZI_Pos 6 /*!< SCU SFSP9_2: EZI Position */
+#define SCU_SFSP9_2_EZI_Msk (0x01UL << SCU_SFSP9_2_EZI_Pos) /*!< SCU SFSP9_2: EZI Mask */
+#define SCU_SFSP9_2_EHD_Pos 8 /*!< SCU SFSP9_2: EHD Position */
+#define SCU_SFSP9_2_EHD_Msk (0x03UL << SCU_SFSP9_2_EHD_Pos) /*!< SCU SFSP9_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSP9_3 ------------------------------------------
+#define SCU_SFSP9_3_MODE_Pos 0 /*!< SCU SFSP9_3: MODE Position */
+#define SCU_SFSP9_3_MODE_Msk (0x07UL << SCU_SFSP9_3_MODE_Pos) /*!< SCU SFSP9_3: MODE Mask */
+#define SCU_SFSP9_3_EPD_Pos 3 /*!< SCU SFSP9_3: EPD Position */
+#define SCU_SFSP9_3_EPD_Msk (0x01UL << SCU_SFSP9_3_EPD_Pos) /*!< SCU SFSP9_3: EPD Mask */
+#define SCU_SFSP9_3_EPUN_Pos 4 /*!< SCU SFSP9_3: EPUN Position */
+#define SCU_SFSP9_3_EPUN_Msk (0x01UL << SCU_SFSP9_3_EPUN_Pos) /*!< SCU SFSP9_3: EPUN Mask */
+#define SCU_SFSP9_3_EHS_Pos 5 /*!< SCU SFSP9_3: EHS Position */
+#define SCU_SFSP9_3_EHS_Msk (0x01UL << SCU_SFSP9_3_EHS_Pos) /*!< SCU SFSP9_3: EHS Mask */
+#define SCU_SFSP9_3_EZI_Pos 6 /*!< SCU SFSP9_3: EZI Position */
+#define SCU_SFSP9_3_EZI_Msk (0x01UL << SCU_SFSP9_3_EZI_Pos) /*!< SCU SFSP9_3: EZI Mask */
+#define SCU_SFSP9_3_EHD_Pos 8 /*!< SCU SFSP9_3: EHD Position */
+#define SCU_SFSP9_3_EHD_Msk (0x03UL << SCU_SFSP9_3_EHD_Pos) /*!< SCU SFSP9_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSP9_4 ------------------------------------------
+#define SCU_SFSP9_4_MODE_Pos 0 /*!< SCU SFSP9_4: MODE Position */
+#define SCU_SFSP9_4_MODE_Msk (0x07UL << SCU_SFSP9_4_MODE_Pos) /*!< SCU SFSP9_4: MODE Mask */
+#define SCU_SFSP9_4_EPD_Pos 3 /*!< SCU SFSP9_4: EPD Position */
+#define SCU_SFSP9_4_EPD_Msk (0x01UL << SCU_SFSP9_4_EPD_Pos) /*!< SCU SFSP9_4: EPD Mask */
+#define SCU_SFSP9_4_EPUN_Pos 4 /*!< SCU SFSP9_4: EPUN Position */
+#define SCU_SFSP9_4_EPUN_Msk (0x01UL << SCU_SFSP9_4_EPUN_Pos) /*!< SCU SFSP9_4: EPUN Mask */
+#define SCU_SFSP9_4_EHS_Pos 5 /*!< SCU SFSP9_4: EHS Position */
+#define SCU_SFSP9_4_EHS_Msk (0x01UL << SCU_SFSP9_4_EHS_Pos) /*!< SCU SFSP9_4: EHS Mask */
+#define SCU_SFSP9_4_EZI_Pos 6 /*!< SCU SFSP9_4: EZI Position */
+#define SCU_SFSP9_4_EZI_Msk (0x01UL << SCU_SFSP9_4_EZI_Pos) /*!< SCU SFSP9_4: EZI Mask */
+#define SCU_SFSP9_4_EHD_Pos 8 /*!< SCU SFSP9_4: EHD Position */
+#define SCU_SFSP9_4_EHD_Msk (0x03UL << SCU_SFSP9_4_EHD_Pos) /*!< SCU SFSP9_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSP9_5 ------------------------------------------
+#define SCU_SFSP9_5_MODE_Pos 0 /*!< SCU SFSP9_5: MODE Position */
+#define SCU_SFSP9_5_MODE_Msk (0x07UL << SCU_SFSP9_5_MODE_Pos) /*!< SCU SFSP9_5: MODE Mask */
+#define SCU_SFSP9_5_EPD_Pos 3 /*!< SCU SFSP9_5: EPD Position */
+#define SCU_SFSP9_5_EPD_Msk (0x01UL << SCU_SFSP9_5_EPD_Pos) /*!< SCU SFSP9_5: EPD Mask */
+#define SCU_SFSP9_5_EPUN_Pos 4 /*!< SCU SFSP9_5: EPUN Position */
+#define SCU_SFSP9_5_EPUN_Msk (0x01UL << SCU_SFSP9_5_EPUN_Pos) /*!< SCU SFSP9_5: EPUN Mask */
+#define SCU_SFSP9_5_EHS_Pos 5 /*!< SCU SFSP9_5: EHS Position */
+#define SCU_SFSP9_5_EHS_Msk (0x01UL << SCU_SFSP9_5_EHS_Pos) /*!< SCU SFSP9_5: EHS Mask */
+#define SCU_SFSP9_5_EZI_Pos 6 /*!< SCU SFSP9_5: EZI Position */
+#define SCU_SFSP9_5_EZI_Msk (0x01UL << SCU_SFSP9_5_EZI_Pos) /*!< SCU SFSP9_5: EZI Mask */
+#define SCU_SFSP9_5_EHD_Pos 8 /*!< SCU SFSP9_5: EHD Position */
+#define SCU_SFSP9_5_EHD_Msk (0x03UL << SCU_SFSP9_5_EHD_Pos) /*!< SCU SFSP9_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSP9_6 ------------------------------------------
+#define SCU_SFSP9_6_MODE_Pos 0 /*!< SCU SFSP9_6: MODE Position */
+#define SCU_SFSP9_6_MODE_Msk (0x07UL << SCU_SFSP9_6_MODE_Pos) /*!< SCU SFSP9_6: MODE Mask */
+#define SCU_SFSP9_6_EPD_Pos 3 /*!< SCU SFSP9_6: EPD Position */
+#define SCU_SFSP9_6_EPD_Msk (0x01UL << SCU_SFSP9_6_EPD_Pos) /*!< SCU SFSP9_6: EPD Mask */
+#define SCU_SFSP9_6_EPUN_Pos 4 /*!< SCU SFSP9_6: EPUN Position */
+#define SCU_SFSP9_6_EPUN_Msk (0x01UL << SCU_SFSP9_6_EPUN_Pos) /*!< SCU SFSP9_6: EPUN Mask */
+#define SCU_SFSP9_6_EHS_Pos 5 /*!< SCU SFSP9_6: EHS Position */
+#define SCU_SFSP9_6_EHS_Msk (0x01UL << SCU_SFSP9_6_EHS_Pos) /*!< SCU SFSP9_6: EHS Mask */
+#define SCU_SFSP9_6_EZI_Pos 6 /*!< SCU SFSP9_6: EZI Position */
+#define SCU_SFSP9_6_EZI_Msk (0x01UL << SCU_SFSP9_6_EZI_Pos) /*!< SCU SFSP9_6: EZI Mask */
+#define SCU_SFSP9_6_EHD_Pos 8 /*!< SCU SFSP9_6: EHD Position */
+#define SCU_SFSP9_6_EHD_Msk (0x03UL << SCU_SFSP9_6_EHD_Pos) /*!< SCU SFSP9_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSPA_0 ------------------------------------------
+#define SCU_SFSPA_0_MODE_Pos 0 /*!< SCU SFSPA_0: MODE Position */
+#define SCU_SFSPA_0_MODE_Msk (0x07UL << SCU_SFSPA_0_MODE_Pos) /*!< SCU SFSPA_0: MODE Mask */
+#define SCU_SFSPA_0_EPD_Pos 3 /*!< SCU SFSPA_0: EPD Position */
+#define SCU_SFSPA_0_EPD_Msk (0x01UL << SCU_SFSPA_0_EPD_Pos) /*!< SCU SFSPA_0: EPD Mask */
+#define SCU_SFSPA_0_EPUN_Pos 4 /*!< SCU SFSPA_0: EPUN Position */
+#define SCU_SFSPA_0_EPUN_Msk (0x01UL << SCU_SFSPA_0_EPUN_Pos) /*!< SCU SFSPA_0: EPUN Mask */
+#define SCU_SFSPA_0_EHS_Pos 5 /*!< SCU SFSPA_0: EHS Position */
+#define SCU_SFSPA_0_EHS_Msk (0x01UL << SCU_SFSPA_0_EHS_Pos) /*!< SCU SFSPA_0: EHS Mask */
+#define SCU_SFSPA_0_EZI_Pos 6 /*!< SCU SFSPA_0: EZI Position */
+#define SCU_SFSPA_0_EZI_Msk (0x01UL << SCU_SFSPA_0_EZI_Pos) /*!< SCU SFSPA_0: EZI Mask */
+#define SCU_SFSPA_0_EHD_Pos 8 /*!< SCU SFSPA_0: EHD Position */
+#define SCU_SFSPA_0_EHD_Msk (0x03UL << SCU_SFSPA_0_EHD_Pos) /*!< SCU SFSPA_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSPA_1 ------------------------------------------
+#define SCU_SFSPA_1_MODE_Pos 0 /*!< SCU SFSPA_1: MODE Position */
+#define SCU_SFSPA_1_MODE_Msk (0x07UL << SCU_SFSPA_1_MODE_Pos) /*!< SCU SFSPA_1: MODE Mask */
+#define SCU_SFSPA_1_EPD_Pos 3 /*!< SCU SFSPA_1: EPD Position */
+#define SCU_SFSPA_1_EPD_Msk (0x01UL << SCU_SFSPA_1_EPD_Pos) /*!< SCU SFSPA_1: EPD Mask */
+#define SCU_SFSPA_1_EPUN_Pos 4 /*!< SCU SFSPA_1: EPUN Position */
+#define SCU_SFSPA_1_EPUN_Msk (0x01UL << SCU_SFSPA_1_EPUN_Pos) /*!< SCU SFSPA_1: EPUN Mask */
+#define SCU_SFSPA_1_EHS_Pos 5 /*!< SCU SFSPA_1: EHS Position */
+#define SCU_SFSPA_1_EHS_Msk (0x01UL << SCU_SFSPA_1_EHS_Pos) /*!< SCU SFSPA_1: EHS Mask */
+#define SCU_SFSPA_1_EZI_Pos 6 /*!< SCU SFSPA_1: EZI Position */
+#define SCU_SFSPA_1_EZI_Msk (0x01UL << SCU_SFSPA_1_EZI_Pos) /*!< SCU SFSPA_1: EZI Mask */
+#define SCU_SFSPA_1_EHD_Pos 8 /*!< SCU SFSPA_1: EHD Position */
+#define SCU_SFSPA_1_EHD_Msk (0x03UL << SCU_SFSPA_1_EHD_Pos) /*!< SCU SFSPA_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSPA_2 ------------------------------------------
+#define SCU_SFSPA_2_MODE_Pos 0 /*!< SCU SFSPA_2: MODE Position */
+#define SCU_SFSPA_2_MODE_Msk (0x07UL << SCU_SFSPA_2_MODE_Pos) /*!< SCU SFSPA_2: MODE Mask */
+#define SCU_SFSPA_2_EPD_Pos 3 /*!< SCU SFSPA_2: EPD Position */
+#define SCU_SFSPA_2_EPD_Msk (0x01UL << SCU_SFSPA_2_EPD_Pos) /*!< SCU SFSPA_2: EPD Mask */
+#define SCU_SFSPA_2_EPUN_Pos 4 /*!< SCU SFSPA_2: EPUN Position */
+#define SCU_SFSPA_2_EPUN_Msk (0x01UL << SCU_SFSPA_2_EPUN_Pos) /*!< SCU SFSPA_2: EPUN Mask */
+#define SCU_SFSPA_2_EHS_Pos 5 /*!< SCU SFSPA_2: EHS Position */
+#define SCU_SFSPA_2_EHS_Msk (0x01UL << SCU_SFSPA_2_EHS_Pos) /*!< SCU SFSPA_2: EHS Mask */
+#define SCU_SFSPA_2_EZI_Pos 6 /*!< SCU SFSPA_2: EZI Position */
+#define SCU_SFSPA_2_EZI_Msk (0x01UL << SCU_SFSPA_2_EZI_Pos) /*!< SCU SFSPA_2: EZI Mask */
+#define SCU_SFSPA_2_EHD_Pos 8 /*!< SCU SFSPA_2: EHD Position */
+#define SCU_SFSPA_2_EHD_Msk (0x03UL << SCU_SFSPA_2_EHD_Pos) /*!< SCU SFSPA_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSPA_3 ------------------------------------------
+#define SCU_SFSPA_3_MODE_Pos 0 /*!< SCU SFSPA_3: MODE Position */
+#define SCU_SFSPA_3_MODE_Msk (0x07UL << SCU_SFSPA_3_MODE_Pos) /*!< SCU SFSPA_3: MODE Mask */
+#define SCU_SFSPA_3_EPD_Pos 3 /*!< SCU SFSPA_3: EPD Position */
+#define SCU_SFSPA_3_EPD_Msk (0x01UL << SCU_SFSPA_3_EPD_Pos) /*!< SCU SFSPA_3: EPD Mask */
+#define SCU_SFSPA_3_EPUN_Pos 4 /*!< SCU SFSPA_3: EPUN Position */
+#define SCU_SFSPA_3_EPUN_Msk (0x01UL << SCU_SFSPA_3_EPUN_Pos) /*!< SCU SFSPA_3: EPUN Mask */
+#define SCU_SFSPA_3_EHS_Pos 5 /*!< SCU SFSPA_3: EHS Position */
+#define SCU_SFSPA_3_EHS_Msk (0x01UL << SCU_SFSPA_3_EHS_Pos) /*!< SCU SFSPA_3: EHS Mask */
+#define SCU_SFSPA_3_EZI_Pos 6 /*!< SCU SFSPA_3: EZI Position */
+#define SCU_SFSPA_3_EZI_Msk (0x01UL << SCU_SFSPA_3_EZI_Pos) /*!< SCU SFSPA_3: EZI Mask */
+#define SCU_SFSPA_3_EHD_Pos 8 /*!< SCU SFSPA_3: EHD Position */
+#define SCU_SFSPA_3_EHD_Msk (0x03UL << SCU_SFSPA_3_EHD_Pos) /*!< SCU SFSPA_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSPA_4 ------------------------------------------
+#define SCU_SFSPA_4_MODE_Pos 0 /*!< SCU SFSPA_4: MODE Position */
+#define SCU_SFSPA_4_MODE_Msk (0x07UL << SCU_SFSPA_4_MODE_Pos) /*!< SCU SFSPA_4: MODE Mask */
+#define SCU_SFSPA_4_EPD_Pos 3 /*!< SCU SFSPA_4: EPD Position */
+#define SCU_SFSPA_4_EPD_Msk (0x01UL << SCU_SFSPA_4_EPD_Pos) /*!< SCU SFSPA_4: EPD Mask */
+#define SCU_SFSPA_4_EPUN_Pos 4 /*!< SCU SFSPA_4: EPUN Position */
+#define SCU_SFSPA_4_EPUN_Msk (0x01UL << SCU_SFSPA_4_EPUN_Pos) /*!< SCU SFSPA_4: EPUN Mask */
+#define SCU_SFSPA_4_EHS_Pos 5 /*!< SCU SFSPA_4: EHS Position */
+#define SCU_SFSPA_4_EHS_Msk (0x01UL << SCU_SFSPA_4_EHS_Pos) /*!< SCU SFSPA_4: EHS Mask */
+#define SCU_SFSPA_4_EZI_Pos 6 /*!< SCU SFSPA_4: EZI Position */
+#define SCU_SFSPA_4_EZI_Msk (0x01UL << SCU_SFSPA_4_EZI_Pos) /*!< SCU SFSPA_4: EZI Mask */
+#define SCU_SFSPA_4_EHD_Pos 8 /*!< SCU SFSPA_4: EHD Position */
+#define SCU_SFSPA_4_EHD_Msk (0x03UL << SCU_SFSPA_4_EHD_Pos) /*!< SCU SFSPA_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSPB_0 ------------------------------------------
+#define SCU_SFSPB_0_MODE_Pos 0 /*!< SCU SFSPB_0: MODE Position */
+#define SCU_SFSPB_0_MODE_Msk (0x07UL << SCU_SFSPB_0_MODE_Pos) /*!< SCU SFSPB_0: MODE Mask */
+#define SCU_SFSPB_0_EPD_Pos 3 /*!< SCU SFSPB_0: EPD Position */
+#define SCU_SFSPB_0_EPD_Msk (0x01UL << SCU_SFSPB_0_EPD_Pos) /*!< SCU SFSPB_0: EPD Mask */
+#define SCU_SFSPB_0_EPUN_Pos 4 /*!< SCU SFSPB_0: EPUN Position */
+#define SCU_SFSPB_0_EPUN_Msk (0x01UL << SCU_SFSPB_0_EPUN_Pos) /*!< SCU SFSPB_0: EPUN Mask */
+#define SCU_SFSPB_0_EHS_Pos 5 /*!< SCU SFSPB_0: EHS Position */
+#define SCU_SFSPB_0_EHS_Msk (0x01UL << SCU_SFSPB_0_EHS_Pos) /*!< SCU SFSPB_0: EHS Mask */
+#define SCU_SFSPB_0_EZI_Pos 6 /*!< SCU SFSPB_0: EZI Position */
+#define SCU_SFSPB_0_EZI_Msk (0x01UL << SCU_SFSPB_0_EZI_Pos) /*!< SCU SFSPB_0: EZI Mask */
+#define SCU_SFSPB_0_EHD_Pos 8 /*!< SCU SFSPB_0: EHD Position */
+#define SCU_SFSPB_0_EHD_Msk (0x03UL << SCU_SFSPB_0_EHD_Pos) /*!< SCU SFSPB_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSPB_1 ------------------------------------------
+#define SCU_SFSPB_1_MODE_Pos 0 /*!< SCU SFSPB_1: MODE Position */
+#define SCU_SFSPB_1_MODE_Msk (0x07UL << SCU_SFSPB_1_MODE_Pos) /*!< SCU SFSPB_1: MODE Mask */
+#define SCU_SFSPB_1_EPD_Pos 3 /*!< SCU SFSPB_1: EPD Position */
+#define SCU_SFSPB_1_EPD_Msk (0x01UL << SCU_SFSPB_1_EPD_Pos) /*!< SCU SFSPB_1: EPD Mask */
+#define SCU_SFSPB_1_EPUN_Pos 4 /*!< SCU SFSPB_1: EPUN Position */
+#define SCU_SFSPB_1_EPUN_Msk (0x01UL << SCU_SFSPB_1_EPUN_Pos) /*!< SCU SFSPB_1: EPUN Mask */
+#define SCU_SFSPB_1_EHS_Pos 5 /*!< SCU SFSPB_1: EHS Position */
+#define SCU_SFSPB_1_EHS_Msk (0x01UL << SCU_SFSPB_1_EHS_Pos) /*!< SCU SFSPB_1: EHS Mask */
+#define SCU_SFSPB_1_EZI_Pos 6 /*!< SCU SFSPB_1: EZI Position */
+#define SCU_SFSPB_1_EZI_Msk (0x01UL << SCU_SFSPB_1_EZI_Pos) /*!< SCU SFSPB_1: EZI Mask */
+#define SCU_SFSPB_1_EHD_Pos 8 /*!< SCU SFSPB_1: EHD Position */
+#define SCU_SFSPB_1_EHD_Msk (0x03UL << SCU_SFSPB_1_EHD_Pos) /*!< SCU SFSPB_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSPB_2 ------------------------------------------
+#define SCU_SFSPB_2_MODE_Pos 0 /*!< SCU SFSPB_2: MODE Position */
+#define SCU_SFSPB_2_MODE_Msk (0x07UL << SCU_SFSPB_2_MODE_Pos) /*!< SCU SFSPB_2: MODE Mask */
+#define SCU_SFSPB_2_EPD_Pos 3 /*!< SCU SFSPB_2: EPD Position */
+#define SCU_SFSPB_2_EPD_Msk (0x01UL << SCU_SFSPB_2_EPD_Pos) /*!< SCU SFSPB_2: EPD Mask */
+#define SCU_SFSPB_2_EPUN_Pos 4 /*!< SCU SFSPB_2: EPUN Position */
+#define SCU_SFSPB_2_EPUN_Msk (0x01UL << SCU_SFSPB_2_EPUN_Pos) /*!< SCU SFSPB_2: EPUN Mask */
+#define SCU_SFSPB_2_EHS_Pos 5 /*!< SCU SFSPB_2: EHS Position */
+#define SCU_SFSPB_2_EHS_Msk (0x01UL << SCU_SFSPB_2_EHS_Pos) /*!< SCU SFSPB_2: EHS Mask */
+#define SCU_SFSPB_2_EZI_Pos 6 /*!< SCU SFSPB_2: EZI Position */
+#define SCU_SFSPB_2_EZI_Msk (0x01UL << SCU_SFSPB_2_EZI_Pos) /*!< SCU SFSPB_2: EZI Mask */
+#define SCU_SFSPB_2_EHD_Pos 8 /*!< SCU SFSPB_2: EHD Position */
+#define SCU_SFSPB_2_EHD_Msk (0x03UL << SCU_SFSPB_2_EHD_Pos) /*!< SCU SFSPB_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSPB_3 ------------------------------------------
+#define SCU_SFSPB_3_MODE_Pos 0 /*!< SCU SFSPB_3: MODE Position */
+#define SCU_SFSPB_3_MODE_Msk (0x07UL << SCU_SFSPB_3_MODE_Pos) /*!< SCU SFSPB_3: MODE Mask */
+#define SCU_SFSPB_3_EPD_Pos 3 /*!< SCU SFSPB_3: EPD Position */
+#define SCU_SFSPB_3_EPD_Msk (0x01UL << SCU_SFSPB_3_EPD_Pos) /*!< SCU SFSPB_3: EPD Mask */
+#define SCU_SFSPB_3_EPUN_Pos 4 /*!< SCU SFSPB_3: EPUN Position */
+#define SCU_SFSPB_3_EPUN_Msk (0x01UL << SCU_SFSPB_3_EPUN_Pos) /*!< SCU SFSPB_3: EPUN Mask */
+#define SCU_SFSPB_3_EHS_Pos 5 /*!< SCU SFSPB_3: EHS Position */
+#define SCU_SFSPB_3_EHS_Msk (0x01UL << SCU_SFSPB_3_EHS_Pos) /*!< SCU SFSPB_3: EHS Mask */
+#define SCU_SFSPB_3_EZI_Pos 6 /*!< SCU SFSPB_3: EZI Position */
+#define SCU_SFSPB_3_EZI_Msk (0x01UL << SCU_SFSPB_3_EZI_Pos) /*!< SCU SFSPB_3: EZI Mask */
+#define SCU_SFSPB_3_EHD_Pos 8 /*!< SCU SFSPB_3: EHD Position */
+#define SCU_SFSPB_3_EHD_Msk (0x03UL << SCU_SFSPB_3_EHD_Pos) /*!< SCU SFSPB_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSPB_4 ------------------------------------------
+#define SCU_SFSPB_4_MODE_Pos 0 /*!< SCU SFSPB_4: MODE Position */
+#define SCU_SFSPB_4_MODE_Msk (0x07UL << SCU_SFSPB_4_MODE_Pos) /*!< SCU SFSPB_4: MODE Mask */
+#define SCU_SFSPB_4_EPD_Pos 3 /*!< SCU SFSPB_4: EPD Position */
+#define SCU_SFSPB_4_EPD_Msk (0x01UL << SCU_SFSPB_4_EPD_Pos) /*!< SCU SFSPB_4: EPD Mask */
+#define SCU_SFSPB_4_EPUN_Pos 4 /*!< SCU SFSPB_4: EPUN Position */
+#define SCU_SFSPB_4_EPUN_Msk (0x01UL << SCU_SFSPB_4_EPUN_Pos) /*!< SCU SFSPB_4: EPUN Mask */
+#define SCU_SFSPB_4_EHS_Pos 5 /*!< SCU SFSPB_4: EHS Position */
+#define SCU_SFSPB_4_EHS_Msk (0x01UL << SCU_SFSPB_4_EHS_Pos) /*!< SCU SFSPB_4: EHS Mask */
+#define SCU_SFSPB_4_EZI_Pos 6 /*!< SCU SFSPB_4: EZI Position */
+#define SCU_SFSPB_4_EZI_Msk (0x01UL << SCU_SFSPB_4_EZI_Pos) /*!< SCU SFSPB_4: EZI Mask */
+#define SCU_SFSPB_4_EHD_Pos 8 /*!< SCU SFSPB_4: EHD Position */
+#define SCU_SFSPB_4_EHD_Msk (0x03UL << SCU_SFSPB_4_EHD_Pos) /*!< SCU SFSPB_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSPB_5 ------------------------------------------
+#define SCU_SFSPB_5_MODE_Pos 0 /*!< SCU SFSPB_5: MODE Position */
+#define SCU_SFSPB_5_MODE_Msk (0x07UL << SCU_SFSPB_5_MODE_Pos) /*!< SCU SFSPB_5: MODE Mask */
+#define SCU_SFSPB_5_EPD_Pos 3 /*!< SCU SFSPB_5: EPD Position */
+#define SCU_SFSPB_5_EPD_Msk (0x01UL << SCU_SFSPB_5_EPD_Pos) /*!< SCU SFSPB_5: EPD Mask */
+#define SCU_SFSPB_5_EPUN_Pos 4 /*!< SCU SFSPB_5: EPUN Position */
+#define SCU_SFSPB_5_EPUN_Msk (0x01UL << SCU_SFSPB_5_EPUN_Pos) /*!< SCU SFSPB_5: EPUN Mask */
+#define SCU_SFSPB_5_EHS_Pos 5 /*!< SCU SFSPB_5: EHS Position */
+#define SCU_SFSPB_5_EHS_Msk (0x01UL << SCU_SFSPB_5_EHS_Pos) /*!< SCU SFSPB_5: EHS Mask */
+#define SCU_SFSPB_5_EZI_Pos 6 /*!< SCU SFSPB_5: EZI Position */
+#define SCU_SFSPB_5_EZI_Msk (0x01UL << SCU_SFSPB_5_EZI_Pos) /*!< SCU SFSPB_5: EZI Mask */
+#define SCU_SFSPB_5_EHD_Pos 8 /*!< SCU SFSPB_5: EHD Position */
+#define SCU_SFSPB_5_EHD_Msk (0x03UL << SCU_SFSPB_5_EHD_Pos) /*!< SCU SFSPB_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSPB_6 ------------------------------------------
+#define SCU_SFSPB_6_MODE_Pos 0 /*!< SCU SFSPB_6: MODE Position */
+#define SCU_SFSPB_6_MODE_Msk (0x07UL << SCU_SFSPB_6_MODE_Pos) /*!< SCU SFSPB_6: MODE Mask */
+#define SCU_SFSPB_6_EPD_Pos 3 /*!< SCU SFSPB_6: EPD Position */
+#define SCU_SFSPB_6_EPD_Msk (0x01UL << SCU_SFSPB_6_EPD_Pos) /*!< SCU SFSPB_6: EPD Mask */
+#define SCU_SFSPB_6_EPUN_Pos 4 /*!< SCU SFSPB_6: EPUN Position */
+#define SCU_SFSPB_6_EPUN_Msk (0x01UL << SCU_SFSPB_6_EPUN_Pos) /*!< SCU SFSPB_6: EPUN Mask */
+#define SCU_SFSPB_6_EHS_Pos 5 /*!< SCU SFSPB_6: EHS Position */
+#define SCU_SFSPB_6_EHS_Msk (0x01UL << SCU_SFSPB_6_EHS_Pos) /*!< SCU SFSPB_6: EHS Mask */
+#define SCU_SFSPB_6_EZI_Pos 6 /*!< SCU SFSPB_6: EZI Position */
+#define SCU_SFSPB_6_EZI_Msk (0x01UL << SCU_SFSPB_6_EZI_Pos) /*!< SCU SFSPB_6: EZI Mask */
+#define SCU_SFSPB_6_EHD_Pos 8 /*!< SCU SFSPB_6: EHD Position */
+#define SCU_SFSPB_6_EHD_Msk (0x03UL << SCU_SFSPB_6_EHD_Pos) /*!< SCU SFSPB_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSPC_0 ------------------------------------------
+#define SCU_SFSPC_0_MODE_Pos 0 /*!< SCU SFSPC_0: MODE Position */
+#define SCU_SFSPC_0_MODE_Msk (0x07UL << SCU_SFSPC_0_MODE_Pos) /*!< SCU SFSPC_0: MODE Mask */
+#define SCU_SFSPC_0_EPD_Pos 3 /*!< SCU SFSPC_0: EPD Position */
+#define SCU_SFSPC_0_EPD_Msk (0x01UL << SCU_SFSPC_0_EPD_Pos) /*!< SCU SFSPC_0: EPD Mask */
+#define SCU_SFSPC_0_EPUN_Pos 4 /*!< SCU SFSPC_0: EPUN Position */
+#define SCU_SFSPC_0_EPUN_Msk (0x01UL << SCU_SFSPC_0_EPUN_Pos) /*!< SCU SFSPC_0: EPUN Mask */
+#define SCU_SFSPC_0_EHS_Pos 5 /*!< SCU SFSPC_0: EHS Position */
+#define SCU_SFSPC_0_EHS_Msk (0x01UL << SCU_SFSPC_0_EHS_Pos) /*!< SCU SFSPC_0: EHS Mask */
+#define SCU_SFSPC_0_EZI_Pos 6 /*!< SCU SFSPC_0: EZI Position */
+#define SCU_SFSPC_0_EZI_Msk (0x01UL << SCU_SFSPC_0_EZI_Pos) /*!< SCU SFSPC_0: EZI Mask */
+#define SCU_SFSPC_0_EHD_Pos 8 /*!< SCU SFSPC_0: EHD Position */
+#define SCU_SFSPC_0_EHD_Msk (0x03UL << SCU_SFSPC_0_EHD_Pos) /*!< SCU SFSPC_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSPC_1 ------------------------------------------
+#define SCU_SFSPC_1_MODE_Pos 0 /*!< SCU SFSPC_1: MODE Position */
+#define SCU_SFSPC_1_MODE_Msk (0x07UL << SCU_SFSPC_1_MODE_Pos) /*!< SCU SFSPC_1: MODE Mask */
+#define SCU_SFSPC_1_EPD_Pos 3 /*!< SCU SFSPC_1: EPD Position */
+#define SCU_SFSPC_1_EPD_Msk (0x01UL << SCU_SFSPC_1_EPD_Pos) /*!< SCU SFSPC_1: EPD Mask */
+#define SCU_SFSPC_1_EPUN_Pos 4 /*!< SCU SFSPC_1: EPUN Position */
+#define SCU_SFSPC_1_EPUN_Msk (0x01UL << SCU_SFSPC_1_EPUN_Pos) /*!< SCU SFSPC_1: EPUN Mask */
+#define SCU_SFSPC_1_EHS_Pos 5 /*!< SCU SFSPC_1: EHS Position */
+#define SCU_SFSPC_1_EHS_Msk (0x01UL << SCU_SFSPC_1_EHS_Pos) /*!< SCU SFSPC_1: EHS Mask */
+#define SCU_SFSPC_1_EZI_Pos 6 /*!< SCU SFSPC_1: EZI Position */
+#define SCU_SFSPC_1_EZI_Msk (0x01UL << SCU_SFSPC_1_EZI_Pos) /*!< SCU SFSPC_1: EZI Mask */
+#define SCU_SFSPC_1_EHD_Pos 8 /*!< SCU SFSPC_1: EHD Position */
+#define SCU_SFSPC_1_EHD_Msk (0x03UL << SCU_SFSPC_1_EHD_Pos) /*!< SCU SFSPC_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSPC_2 ------------------------------------------
+#define SCU_SFSPC_2_MODE_Pos 0 /*!< SCU SFSPC_2: MODE Position */
+#define SCU_SFSPC_2_MODE_Msk (0x07UL << SCU_SFSPC_2_MODE_Pos) /*!< SCU SFSPC_2: MODE Mask */
+#define SCU_SFSPC_2_EPD_Pos 3 /*!< SCU SFSPC_2: EPD Position */
+#define SCU_SFSPC_2_EPD_Msk (0x01UL << SCU_SFSPC_2_EPD_Pos) /*!< SCU SFSPC_2: EPD Mask */
+#define SCU_SFSPC_2_EPUN_Pos 4 /*!< SCU SFSPC_2: EPUN Position */
+#define SCU_SFSPC_2_EPUN_Msk (0x01UL << SCU_SFSPC_2_EPUN_Pos) /*!< SCU SFSPC_2: EPUN Mask */
+#define SCU_SFSPC_2_EHS_Pos 5 /*!< SCU SFSPC_2: EHS Position */
+#define SCU_SFSPC_2_EHS_Msk (0x01UL << SCU_SFSPC_2_EHS_Pos) /*!< SCU SFSPC_2: EHS Mask */
+#define SCU_SFSPC_2_EZI_Pos 6 /*!< SCU SFSPC_2: EZI Position */
+#define SCU_SFSPC_2_EZI_Msk (0x01UL << SCU_SFSPC_2_EZI_Pos) /*!< SCU SFSPC_2: EZI Mask */
+#define SCU_SFSPC_2_EHD_Pos 8 /*!< SCU SFSPC_2: EHD Position */
+#define SCU_SFSPC_2_EHD_Msk (0x03UL << SCU_SFSPC_2_EHD_Pos) /*!< SCU SFSPC_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSPC_3 ------------------------------------------
+#define SCU_SFSPC_3_MODE_Pos 0 /*!< SCU SFSPC_3: MODE Position */
+#define SCU_SFSPC_3_MODE_Msk (0x07UL << SCU_SFSPC_3_MODE_Pos) /*!< SCU SFSPC_3: MODE Mask */
+#define SCU_SFSPC_3_EPD_Pos 3 /*!< SCU SFSPC_3: EPD Position */
+#define SCU_SFSPC_3_EPD_Msk (0x01UL << SCU_SFSPC_3_EPD_Pos) /*!< SCU SFSPC_3: EPD Mask */
+#define SCU_SFSPC_3_EPUN_Pos 4 /*!< SCU SFSPC_3: EPUN Position */
+#define SCU_SFSPC_3_EPUN_Msk (0x01UL << SCU_SFSPC_3_EPUN_Pos) /*!< SCU SFSPC_3: EPUN Mask */
+#define SCU_SFSPC_3_EHS_Pos 5 /*!< SCU SFSPC_3: EHS Position */
+#define SCU_SFSPC_3_EHS_Msk (0x01UL << SCU_SFSPC_3_EHS_Pos) /*!< SCU SFSPC_3: EHS Mask */
+#define SCU_SFSPC_3_EZI_Pos 6 /*!< SCU SFSPC_3: EZI Position */
+#define SCU_SFSPC_3_EZI_Msk (0x01UL << SCU_SFSPC_3_EZI_Pos) /*!< SCU SFSPC_3: EZI Mask */
+#define SCU_SFSPC_3_EHD_Pos 8 /*!< SCU SFSPC_3: EHD Position */
+#define SCU_SFSPC_3_EHD_Msk (0x03UL << SCU_SFSPC_3_EHD_Pos) /*!< SCU SFSPC_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSPC_4 ------------------------------------------
+#define SCU_SFSPC_4_MODE_Pos 0 /*!< SCU SFSPC_4: MODE Position */
+#define SCU_SFSPC_4_MODE_Msk (0x07UL << SCU_SFSPC_4_MODE_Pos) /*!< SCU SFSPC_4: MODE Mask */
+#define SCU_SFSPC_4_EPD_Pos 3 /*!< SCU SFSPC_4: EPD Position */
+#define SCU_SFSPC_4_EPD_Msk (0x01UL << SCU_SFSPC_4_EPD_Pos) /*!< SCU SFSPC_4: EPD Mask */
+#define SCU_SFSPC_4_EPUN_Pos 4 /*!< SCU SFSPC_4: EPUN Position */
+#define SCU_SFSPC_4_EPUN_Msk (0x01UL << SCU_SFSPC_4_EPUN_Pos) /*!< SCU SFSPC_4: EPUN Mask */
+#define SCU_SFSPC_4_EHS_Pos 5 /*!< SCU SFSPC_4: EHS Position */
+#define SCU_SFSPC_4_EHS_Msk (0x01UL << SCU_SFSPC_4_EHS_Pos) /*!< SCU SFSPC_4: EHS Mask */
+#define SCU_SFSPC_4_EZI_Pos 6 /*!< SCU SFSPC_4: EZI Position */
+#define SCU_SFSPC_4_EZI_Msk (0x01UL << SCU_SFSPC_4_EZI_Pos) /*!< SCU SFSPC_4: EZI Mask */
+#define SCU_SFSPC_4_EHD_Pos 8 /*!< SCU SFSPC_4: EHD Position */
+#define SCU_SFSPC_4_EHD_Msk (0x03UL << SCU_SFSPC_4_EHD_Pos) /*!< SCU SFSPC_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSPC_5 ------------------------------------------
+#define SCU_SFSPC_5_MODE_Pos 0 /*!< SCU SFSPC_5: MODE Position */
+#define SCU_SFSPC_5_MODE_Msk (0x07UL << SCU_SFSPC_5_MODE_Pos) /*!< SCU SFSPC_5: MODE Mask */
+#define SCU_SFSPC_5_EPD_Pos 3 /*!< SCU SFSPC_5: EPD Position */
+#define SCU_SFSPC_5_EPD_Msk (0x01UL << SCU_SFSPC_5_EPD_Pos) /*!< SCU SFSPC_5: EPD Mask */
+#define SCU_SFSPC_5_EPUN_Pos 4 /*!< SCU SFSPC_5: EPUN Position */
+#define SCU_SFSPC_5_EPUN_Msk (0x01UL << SCU_SFSPC_5_EPUN_Pos) /*!< SCU SFSPC_5: EPUN Mask */
+#define SCU_SFSPC_5_EHS_Pos 5 /*!< SCU SFSPC_5: EHS Position */
+#define SCU_SFSPC_5_EHS_Msk (0x01UL << SCU_SFSPC_5_EHS_Pos) /*!< SCU SFSPC_5: EHS Mask */
+#define SCU_SFSPC_5_EZI_Pos 6 /*!< SCU SFSPC_5: EZI Position */
+#define SCU_SFSPC_5_EZI_Msk (0x01UL << SCU_SFSPC_5_EZI_Pos) /*!< SCU SFSPC_5: EZI Mask */
+#define SCU_SFSPC_5_EHD_Pos 8 /*!< SCU SFSPC_5: EHD Position */
+#define SCU_SFSPC_5_EHD_Msk (0x03UL << SCU_SFSPC_5_EHD_Pos) /*!< SCU SFSPC_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSPC_6 ------------------------------------------
+#define SCU_SFSPC_6_MODE_Pos 0 /*!< SCU SFSPC_6: MODE Position */
+#define SCU_SFSPC_6_MODE_Msk (0x07UL << SCU_SFSPC_6_MODE_Pos) /*!< SCU SFSPC_6: MODE Mask */
+#define SCU_SFSPC_6_EPD_Pos 3 /*!< SCU SFSPC_6: EPD Position */
+#define SCU_SFSPC_6_EPD_Msk (0x01UL << SCU_SFSPC_6_EPD_Pos) /*!< SCU SFSPC_6: EPD Mask */
+#define SCU_SFSPC_6_EPUN_Pos 4 /*!< SCU SFSPC_6: EPUN Position */
+#define SCU_SFSPC_6_EPUN_Msk (0x01UL << SCU_SFSPC_6_EPUN_Pos) /*!< SCU SFSPC_6: EPUN Mask */
+#define SCU_SFSPC_6_EHS_Pos 5 /*!< SCU SFSPC_6: EHS Position */
+#define SCU_SFSPC_6_EHS_Msk (0x01UL << SCU_SFSPC_6_EHS_Pos) /*!< SCU SFSPC_6: EHS Mask */
+#define SCU_SFSPC_6_EZI_Pos 6 /*!< SCU SFSPC_6: EZI Position */
+#define SCU_SFSPC_6_EZI_Msk (0x01UL << SCU_SFSPC_6_EZI_Pos) /*!< SCU SFSPC_6: EZI Mask */
+#define SCU_SFSPC_6_EHD_Pos 8 /*!< SCU SFSPC_6: EHD Position */
+#define SCU_SFSPC_6_EHD_Msk (0x03UL << SCU_SFSPC_6_EHD_Pos) /*!< SCU SFSPC_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSPC_7 ------------------------------------------
+#define SCU_SFSPC_7_MODE_Pos 0 /*!< SCU SFSPC_7: MODE Position */
+#define SCU_SFSPC_7_MODE_Msk (0x07UL << SCU_SFSPC_7_MODE_Pos) /*!< SCU SFSPC_7: MODE Mask */
+#define SCU_SFSPC_7_EPD_Pos 3 /*!< SCU SFSPC_7: EPD Position */
+#define SCU_SFSPC_7_EPD_Msk (0x01UL << SCU_SFSPC_7_EPD_Pos) /*!< SCU SFSPC_7: EPD Mask */
+#define SCU_SFSPC_7_EPUN_Pos 4 /*!< SCU SFSPC_7: EPUN Position */
+#define SCU_SFSPC_7_EPUN_Msk (0x01UL << SCU_SFSPC_7_EPUN_Pos) /*!< SCU SFSPC_7: EPUN Mask */
+#define SCU_SFSPC_7_EHS_Pos 5 /*!< SCU SFSPC_7: EHS Position */
+#define SCU_SFSPC_7_EHS_Msk (0x01UL << SCU_SFSPC_7_EHS_Pos) /*!< SCU SFSPC_7: EHS Mask */
+#define SCU_SFSPC_7_EZI_Pos 6 /*!< SCU SFSPC_7: EZI Position */
+#define SCU_SFSPC_7_EZI_Msk (0x01UL << SCU_SFSPC_7_EZI_Pos) /*!< SCU SFSPC_7: EZI Mask */
+#define SCU_SFSPC_7_EHD_Pos 8 /*!< SCU SFSPC_7: EHD Position */
+#define SCU_SFSPC_7_EHD_Msk (0x03UL << SCU_SFSPC_7_EHD_Pos) /*!< SCU SFSPC_7: EHD Mask */
+
+// --------------------------------------- SCU_SFSPC_8 ------------------------------------------
+#define SCU_SFSPC_8_MODE_Pos 0 /*!< SCU SFSPC_8: MODE Position */
+#define SCU_SFSPC_8_MODE_Msk (0x07UL << SCU_SFSPC_8_MODE_Pos) /*!< SCU SFSPC_8: MODE Mask */
+#define SCU_SFSPC_8_EPD_Pos 3 /*!< SCU SFSPC_8: EPD Position */
+#define SCU_SFSPC_8_EPD_Msk (0x01UL << SCU_SFSPC_8_EPD_Pos) /*!< SCU SFSPC_8: EPD Mask */
+#define SCU_SFSPC_8_EPUN_Pos 4 /*!< SCU SFSPC_8: EPUN Position */
+#define SCU_SFSPC_8_EPUN_Msk (0x01UL << SCU_SFSPC_8_EPUN_Pos) /*!< SCU SFSPC_8: EPUN Mask */
+#define SCU_SFSPC_8_EHS_Pos 5 /*!< SCU SFSPC_8: EHS Position */
+#define SCU_SFSPC_8_EHS_Msk (0x01UL << SCU_SFSPC_8_EHS_Pos) /*!< SCU SFSPC_8: EHS Mask */
+#define SCU_SFSPC_8_EZI_Pos 6 /*!< SCU SFSPC_8: EZI Position */
+#define SCU_SFSPC_8_EZI_Msk (0x01UL << SCU_SFSPC_8_EZI_Pos) /*!< SCU SFSPC_8: EZI Mask */
+#define SCU_SFSPC_8_EHD_Pos 8 /*!< SCU SFSPC_8: EHD Position */
+#define SCU_SFSPC_8_EHD_Msk (0x03UL << SCU_SFSPC_8_EHD_Pos) /*!< SCU SFSPC_8: EHD Mask */
+
+// --------------------------------------- SCU_SFSPC_9 ------------------------------------------
+#define SCU_SFSPC_9_MODE_Pos 0 /*!< SCU SFSPC_9: MODE Position */
+#define SCU_SFSPC_9_MODE_Msk (0x07UL << SCU_SFSPC_9_MODE_Pos) /*!< SCU SFSPC_9: MODE Mask */
+#define SCU_SFSPC_9_EPD_Pos 3 /*!< SCU SFSPC_9: EPD Position */
+#define SCU_SFSPC_9_EPD_Msk (0x01UL << SCU_SFSPC_9_EPD_Pos) /*!< SCU SFSPC_9: EPD Mask */
+#define SCU_SFSPC_9_EPUN_Pos 4 /*!< SCU SFSPC_9: EPUN Position */
+#define SCU_SFSPC_9_EPUN_Msk (0x01UL << SCU_SFSPC_9_EPUN_Pos) /*!< SCU SFSPC_9: EPUN Mask */
+#define SCU_SFSPC_9_EHS_Pos 5 /*!< SCU SFSPC_9: EHS Position */
+#define SCU_SFSPC_9_EHS_Msk (0x01UL << SCU_SFSPC_9_EHS_Pos) /*!< SCU SFSPC_9: EHS Mask */
+#define SCU_SFSPC_9_EZI_Pos 6 /*!< SCU SFSPC_9: EZI Position */
+#define SCU_SFSPC_9_EZI_Msk (0x01UL << SCU_SFSPC_9_EZI_Pos) /*!< SCU SFSPC_9: EZI Mask */
+#define SCU_SFSPC_9_EHD_Pos 8 /*!< SCU SFSPC_9: EHD Position */
+#define SCU_SFSPC_9_EHD_Msk (0x03UL << SCU_SFSPC_9_EHD_Pos) /*!< SCU SFSPC_9: EHD Mask */
+
+// -------------------------------------- SCU_SFSPC_10 ------------------------------------------
+#define SCU_SFSPC_10_MODE_Pos 0 /*!< SCU SFSPC_10: MODE Position */
+#define SCU_SFSPC_10_MODE_Msk (0x07UL << SCU_SFSPC_10_MODE_Pos) /*!< SCU SFSPC_10: MODE Mask */
+#define SCU_SFSPC_10_EPD_Pos 3 /*!< SCU SFSPC_10: EPD Position */
+#define SCU_SFSPC_10_EPD_Msk (0x01UL << SCU_SFSPC_10_EPD_Pos) /*!< SCU SFSPC_10: EPD Mask */
+#define SCU_SFSPC_10_EPUN_Pos 4 /*!< SCU SFSPC_10: EPUN Position */
+#define SCU_SFSPC_10_EPUN_Msk (0x01UL << SCU_SFSPC_10_EPUN_Pos) /*!< SCU SFSPC_10: EPUN Mask */
+#define SCU_SFSPC_10_EHS_Pos 5 /*!< SCU SFSPC_10: EHS Position */
+#define SCU_SFSPC_10_EHS_Msk (0x01UL << SCU_SFSPC_10_EHS_Pos) /*!< SCU SFSPC_10: EHS Mask */
+#define SCU_SFSPC_10_EZI_Pos 6 /*!< SCU SFSPC_10: EZI Position */
+#define SCU_SFSPC_10_EZI_Msk (0x01UL << SCU_SFSPC_10_EZI_Pos) /*!< SCU SFSPC_10: EZI Mask */
+#define SCU_SFSPC_10_EHD_Pos 8 /*!< SCU SFSPC_10: EHD Position */
+#define SCU_SFSPC_10_EHD_Msk (0x03UL << SCU_SFSPC_10_EHD_Pos) /*!< SCU SFSPC_10: EHD Mask */
+
+// -------------------------------------- SCU_SFSPC_11 ------------------------------------------
+#define SCU_SFSPC_11_MODE_Pos 0 /*!< SCU SFSPC_11: MODE Position */
+#define SCU_SFSPC_11_MODE_Msk (0x07UL << SCU_SFSPC_11_MODE_Pos) /*!< SCU SFSPC_11: MODE Mask */
+#define SCU_SFSPC_11_EPD_Pos 3 /*!< SCU SFSPC_11: EPD Position */
+#define SCU_SFSPC_11_EPD_Msk (0x01UL << SCU_SFSPC_11_EPD_Pos) /*!< SCU SFSPC_11: EPD Mask */
+#define SCU_SFSPC_11_EPUN_Pos 4 /*!< SCU SFSPC_11: EPUN Position */
+#define SCU_SFSPC_11_EPUN_Msk (0x01UL << SCU_SFSPC_11_EPUN_Pos) /*!< SCU SFSPC_11: EPUN Mask */
+#define SCU_SFSPC_11_EHS_Pos 5 /*!< SCU SFSPC_11: EHS Position */
+#define SCU_SFSPC_11_EHS_Msk (0x01UL << SCU_SFSPC_11_EHS_Pos) /*!< SCU SFSPC_11: EHS Mask */
+#define SCU_SFSPC_11_EZI_Pos 6 /*!< SCU SFSPC_11: EZI Position */
+#define SCU_SFSPC_11_EZI_Msk (0x01UL << SCU_SFSPC_11_EZI_Pos) /*!< SCU SFSPC_11: EZI Mask */
+#define SCU_SFSPC_11_EHD_Pos 8 /*!< SCU SFSPC_11: EHD Position */
+#define SCU_SFSPC_11_EHD_Msk (0x03UL << SCU_SFSPC_11_EHD_Pos) /*!< SCU SFSPC_11: EHD Mask */
+
+// -------------------------------------- SCU_SFSPC_12 ------------------------------------------
+#define SCU_SFSPC_12_MODE_Pos 0 /*!< SCU SFSPC_12: MODE Position */
+#define SCU_SFSPC_12_MODE_Msk (0x07UL << SCU_SFSPC_12_MODE_Pos) /*!< SCU SFSPC_12: MODE Mask */
+#define SCU_SFSPC_12_EPD_Pos 3 /*!< SCU SFSPC_12: EPD Position */
+#define SCU_SFSPC_12_EPD_Msk (0x01UL << SCU_SFSPC_12_EPD_Pos) /*!< SCU SFSPC_12: EPD Mask */
+#define SCU_SFSPC_12_EPUN_Pos 4 /*!< SCU SFSPC_12: EPUN Position */
+#define SCU_SFSPC_12_EPUN_Msk (0x01UL << SCU_SFSPC_12_EPUN_Pos) /*!< SCU SFSPC_12: EPUN Mask */
+#define SCU_SFSPC_12_EHS_Pos 5 /*!< SCU SFSPC_12: EHS Position */
+#define SCU_SFSPC_12_EHS_Msk (0x01UL << SCU_SFSPC_12_EHS_Pos) /*!< SCU SFSPC_12: EHS Mask */
+#define SCU_SFSPC_12_EZI_Pos 6 /*!< SCU SFSPC_12: EZI Position */
+#define SCU_SFSPC_12_EZI_Msk (0x01UL << SCU_SFSPC_12_EZI_Pos) /*!< SCU SFSPC_12: EZI Mask */
+#define SCU_SFSPC_12_EHD_Pos 8 /*!< SCU SFSPC_12: EHD Position */
+#define SCU_SFSPC_12_EHD_Msk (0x03UL << SCU_SFSPC_12_EHD_Pos) /*!< SCU SFSPC_12: EHD Mask */
+
+// -------------------------------------- SCU_SFSPC_13 ------------------------------------------
+#define SCU_SFSPC_13_MODE_Pos 0 /*!< SCU SFSPC_13: MODE Position */
+#define SCU_SFSPC_13_MODE_Msk (0x07UL << SCU_SFSPC_13_MODE_Pos) /*!< SCU SFSPC_13: MODE Mask */
+#define SCU_SFSPC_13_EPD_Pos 3 /*!< SCU SFSPC_13: EPD Position */
+#define SCU_SFSPC_13_EPD_Msk (0x01UL << SCU_SFSPC_13_EPD_Pos) /*!< SCU SFSPC_13: EPD Mask */
+#define SCU_SFSPC_13_EPUN_Pos 4 /*!< SCU SFSPC_13: EPUN Position */
+#define SCU_SFSPC_13_EPUN_Msk (0x01UL << SCU_SFSPC_13_EPUN_Pos) /*!< SCU SFSPC_13: EPUN Mask */
+#define SCU_SFSPC_13_EHS_Pos 5 /*!< SCU SFSPC_13: EHS Position */
+#define SCU_SFSPC_13_EHS_Msk (0x01UL << SCU_SFSPC_13_EHS_Pos) /*!< SCU SFSPC_13: EHS Mask */
+#define SCU_SFSPC_13_EZI_Pos 6 /*!< SCU SFSPC_13: EZI Position */
+#define SCU_SFSPC_13_EZI_Msk (0x01UL << SCU_SFSPC_13_EZI_Pos) /*!< SCU SFSPC_13: EZI Mask */
+#define SCU_SFSPC_13_EHD_Pos 8 /*!< SCU SFSPC_13: EHD Position */
+#define SCU_SFSPC_13_EHD_Msk (0x03UL << SCU_SFSPC_13_EHD_Pos) /*!< SCU SFSPC_13: EHD Mask */
+
+// -------------------------------------- SCU_SFSPC_14 ------------------------------------------
+#define SCU_SFSPC_14_MODE_Pos 0 /*!< SCU SFSPC_14: MODE Position */
+#define SCU_SFSPC_14_MODE_Msk (0x07UL << SCU_SFSPC_14_MODE_Pos) /*!< SCU SFSPC_14: MODE Mask */
+#define SCU_SFSPC_14_EPD_Pos 3 /*!< SCU SFSPC_14: EPD Position */
+#define SCU_SFSPC_14_EPD_Msk (0x01UL << SCU_SFSPC_14_EPD_Pos) /*!< SCU SFSPC_14: EPD Mask */
+#define SCU_SFSPC_14_EPUN_Pos 4 /*!< SCU SFSPC_14: EPUN Position */
+#define SCU_SFSPC_14_EPUN_Msk (0x01UL << SCU_SFSPC_14_EPUN_Pos) /*!< SCU SFSPC_14: EPUN Mask */
+#define SCU_SFSPC_14_EHS_Pos 5 /*!< SCU SFSPC_14: EHS Position */
+#define SCU_SFSPC_14_EHS_Msk (0x01UL << SCU_SFSPC_14_EHS_Pos) /*!< SCU SFSPC_14: EHS Mask */
+#define SCU_SFSPC_14_EZI_Pos 6 /*!< SCU SFSPC_14: EZI Position */
+#define SCU_SFSPC_14_EZI_Msk (0x01UL << SCU_SFSPC_14_EZI_Pos) /*!< SCU SFSPC_14: EZI Mask */
+#define SCU_SFSPC_14_EHD_Pos 8 /*!< SCU SFSPC_14: EHD Position */
+#define SCU_SFSPC_14_EHD_Msk (0x03UL << SCU_SFSPC_14_EHD_Pos) /*!< SCU SFSPC_14: EHD Mask */
+
+// --------------------------------------- SCU_SFSPD_0 ------------------------------------------
+#define SCU_SFSPD_0_MODE_Pos 0 /*!< SCU SFSPD_0: MODE Position */
+#define SCU_SFSPD_0_MODE_Msk (0x07UL << SCU_SFSPD_0_MODE_Pos) /*!< SCU SFSPD_0: MODE Mask */
+#define SCU_SFSPD_0_EPD_Pos 3 /*!< SCU SFSPD_0: EPD Position */
+#define SCU_SFSPD_0_EPD_Msk (0x01UL << SCU_SFSPD_0_EPD_Pos) /*!< SCU SFSPD_0: EPD Mask */
+#define SCU_SFSPD_0_EPUN_Pos 4 /*!< SCU SFSPD_0: EPUN Position */
+#define SCU_SFSPD_0_EPUN_Msk (0x01UL << SCU_SFSPD_0_EPUN_Pos) /*!< SCU SFSPD_0: EPUN Mask */
+#define SCU_SFSPD_0_EHS_Pos 5 /*!< SCU SFSPD_0: EHS Position */
+#define SCU_SFSPD_0_EHS_Msk (0x01UL << SCU_SFSPD_0_EHS_Pos) /*!< SCU SFSPD_0: EHS Mask */
+#define SCU_SFSPD_0_EZI_Pos 6 /*!< SCU SFSPD_0: EZI Position */
+#define SCU_SFSPD_0_EZI_Msk (0x01UL << SCU_SFSPD_0_EZI_Pos) /*!< SCU SFSPD_0: EZI Mask */
+#define SCU_SFSPD_0_EHD_Pos 8 /*!< SCU SFSPD_0: EHD Position */
+#define SCU_SFSPD_0_EHD_Msk (0x03UL << SCU_SFSPD_0_EHD_Pos) /*!< SCU SFSPD_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSPD_1 ------------------------------------------
+#define SCU_SFSPD_1_MODE_Pos 0 /*!< SCU SFSPD_1: MODE Position */
+#define SCU_SFSPD_1_MODE_Msk (0x07UL << SCU_SFSPD_1_MODE_Pos) /*!< SCU SFSPD_1: MODE Mask */
+#define SCU_SFSPD_1_EPD_Pos 3 /*!< SCU SFSPD_1: EPD Position */
+#define SCU_SFSPD_1_EPD_Msk (0x01UL << SCU_SFSPD_1_EPD_Pos) /*!< SCU SFSPD_1: EPD Mask */
+#define SCU_SFSPD_1_EPUN_Pos 4 /*!< SCU SFSPD_1: EPUN Position */
+#define SCU_SFSPD_1_EPUN_Msk (0x01UL << SCU_SFSPD_1_EPUN_Pos) /*!< SCU SFSPD_1: EPUN Mask */
+#define SCU_SFSPD_1_EHS_Pos 5 /*!< SCU SFSPD_1: EHS Position */
+#define SCU_SFSPD_1_EHS_Msk (0x01UL << SCU_SFSPD_1_EHS_Pos) /*!< SCU SFSPD_1: EHS Mask */
+#define SCU_SFSPD_1_EZI_Pos 6 /*!< SCU SFSPD_1: EZI Position */
+#define SCU_SFSPD_1_EZI_Msk (0x01UL << SCU_SFSPD_1_EZI_Pos) /*!< SCU SFSPD_1: EZI Mask */
+#define SCU_SFSPD_1_EHD_Pos 8 /*!< SCU SFSPD_1: EHD Position */
+#define SCU_SFSPD_1_EHD_Msk (0x03UL << SCU_SFSPD_1_EHD_Pos) /*!< SCU SFSPD_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSPD_2 ------------------------------------------
+#define SCU_SFSPD_2_MODE_Pos 0 /*!< SCU SFSPD_2: MODE Position */
+#define SCU_SFSPD_2_MODE_Msk (0x07UL << SCU_SFSPD_2_MODE_Pos) /*!< SCU SFSPD_2: MODE Mask */
+#define SCU_SFSPD_2_EPD_Pos 3 /*!< SCU SFSPD_2: EPD Position */
+#define SCU_SFSPD_2_EPD_Msk (0x01UL << SCU_SFSPD_2_EPD_Pos) /*!< SCU SFSPD_2: EPD Mask */
+#define SCU_SFSPD_2_EPUN_Pos 4 /*!< SCU SFSPD_2: EPUN Position */
+#define SCU_SFSPD_2_EPUN_Msk (0x01UL << SCU_SFSPD_2_EPUN_Pos) /*!< SCU SFSPD_2: EPUN Mask */
+#define SCU_SFSPD_2_EHS_Pos 5 /*!< SCU SFSPD_2: EHS Position */
+#define SCU_SFSPD_2_EHS_Msk (0x01UL << SCU_SFSPD_2_EHS_Pos) /*!< SCU SFSPD_2: EHS Mask */
+#define SCU_SFSPD_2_EZI_Pos 6 /*!< SCU SFSPD_2: EZI Position */
+#define SCU_SFSPD_2_EZI_Msk (0x01UL << SCU_SFSPD_2_EZI_Pos) /*!< SCU SFSPD_2: EZI Mask */
+#define SCU_SFSPD_2_EHD_Pos 8 /*!< SCU SFSPD_2: EHD Position */
+#define SCU_SFSPD_2_EHD_Msk (0x03UL << SCU_SFSPD_2_EHD_Pos) /*!< SCU SFSPD_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSPD_3 ------------------------------------------
+#define SCU_SFSPD_3_MODE_Pos 0 /*!< SCU SFSPD_3: MODE Position */
+#define SCU_SFSPD_3_MODE_Msk (0x07UL << SCU_SFSPD_3_MODE_Pos) /*!< SCU SFSPD_3: MODE Mask */
+#define SCU_SFSPD_3_EPD_Pos 3 /*!< SCU SFSPD_3: EPD Position */
+#define SCU_SFSPD_3_EPD_Msk (0x01UL << SCU_SFSPD_3_EPD_Pos) /*!< SCU SFSPD_3: EPD Mask */
+#define SCU_SFSPD_3_EPUN_Pos 4 /*!< SCU SFSPD_3: EPUN Position */
+#define SCU_SFSPD_3_EPUN_Msk (0x01UL << SCU_SFSPD_3_EPUN_Pos) /*!< SCU SFSPD_3: EPUN Mask */
+#define SCU_SFSPD_3_EHS_Pos 5 /*!< SCU SFSPD_3: EHS Position */
+#define SCU_SFSPD_3_EHS_Msk (0x01UL << SCU_SFSPD_3_EHS_Pos) /*!< SCU SFSPD_3: EHS Mask */
+#define SCU_SFSPD_3_EZI_Pos 6 /*!< SCU SFSPD_3: EZI Position */
+#define SCU_SFSPD_3_EZI_Msk (0x01UL << SCU_SFSPD_3_EZI_Pos) /*!< SCU SFSPD_3: EZI Mask */
+#define SCU_SFSPD_3_EHD_Pos 8 /*!< SCU SFSPD_3: EHD Position */
+#define SCU_SFSPD_3_EHD_Msk (0x03UL << SCU_SFSPD_3_EHD_Pos) /*!< SCU SFSPD_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSPD_4 ------------------------------------------
+#define SCU_SFSPD_4_MODE_Pos 0 /*!< SCU SFSPD_4: MODE Position */
+#define SCU_SFSPD_4_MODE_Msk (0x07UL << SCU_SFSPD_4_MODE_Pos) /*!< SCU SFSPD_4: MODE Mask */
+#define SCU_SFSPD_4_EPD_Pos 3 /*!< SCU SFSPD_4: EPD Position */
+#define SCU_SFSPD_4_EPD_Msk (0x01UL << SCU_SFSPD_4_EPD_Pos) /*!< SCU SFSPD_4: EPD Mask */
+#define SCU_SFSPD_4_EPUN_Pos 4 /*!< SCU SFSPD_4: EPUN Position */
+#define SCU_SFSPD_4_EPUN_Msk (0x01UL << SCU_SFSPD_4_EPUN_Pos) /*!< SCU SFSPD_4: EPUN Mask */
+#define SCU_SFSPD_4_EHS_Pos 5 /*!< SCU SFSPD_4: EHS Position */
+#define SCU_SFSPD_4_EHS_Msk (0x01UL << SCU_SFSPD_4_EHS_Pos) /*!< SCU SFSPD_4: EHS Mask */
+#define SCU_SFSPD_4_EZI_Pos 6 /*!< SCU SFSPD_4: EZI Position */
+#define SCU_SFSPD_4_EZI_Msk (0x01UL << SCU_SFSPD_4_EZI_Pos) /*!< SCU SFSPD_4: EZI Mask */
+#define SCU_SFSPD_4_EHD_Pos 8 /*!< SCU SFSPD_4: EHD Position */
+#define SCU_SFSPD_4_EHD_Msk (0x03UL << SCU_SFSPD_4_EHD_Pos) /*!< SCU SFSPD_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSPD_5 ------------------------------------------
+#define SCU_SFSPD_5_MODE_Pos 0 /*!< SCU SFSPD_5: MODE Position */
+#define SCU_SFSPD_5_MODE_Msk (0x07UL << SCU_SFSPD_5_MODE_Pos) /*!< SCU SFSPD_5: MODE Mask */
+#define SCU_SFSPD_5_EPD_Pos 3 /*!< SCU SFSPD_5: EPD Position */
+#define SCU_SFSPD_5_EPD_Msk (0x01UL << SCU_SFSPD_5_EPD_Pos) /*!< SCU SFSPD_5: EPD Mask */
+#define SCU_SFSPD_5_EPUN_Pos 4 /*!< SCU SFSPD_5: EPUN Position */
+#define SCU_SFSPD_5_EPUN_Msk (0x01UL << SCU_SFSPD_5_EPUN_Pos) /*!< SCU SFSPD_5: EPUN Mask */
+#define SCU_SFSPD_5_EHS_Pos 5 /*!< SCU SFSPD_5: EHS Position */
+#define SCU_SFSPD_5_EHS_Msk (0x01UL << SCU_SFSPD_5_EHS_Pos) /*!< SCU SFSPD_5: EHS Mask */
+#define SCU_SFSPD_5_EZI_Pos 6 /*!< SCU SFSPD_5: EZI Position */
+#define SCU_SFSPD_5_EZI_Msk (0x01UL << SCU_SFSPD_5_EZI_Pos) /*!< SCU SFSPD_5: EZI Mask */
+#define SCU_SFSPD_5_EHD_Pos 8 /*!< SCU SFSPD_5: EHD Position */
+#define SCU_SFSPD_5_EHD_Msk (0x03UL << SCU_SFSPD_5_EHD_Pos) /*!< SCU SFSPD_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSPD_6 ------------------------------------------
+#define SCU_SFSPD_6_MODE_Pos 0 /*!< SCU SFSPD_6: MODE Position */
+#define SCU_SFSPD_6_MODE_Msk (0x07UL << SCU_SFSPD_6_MODE_Pos) /*!< SCU SFSPD_6: MODE Mask */
+#define SCU_SFSPD_6_EPD_Pos 3 /*!< SCU SFSPD_6: EPD Position */
+#define SCU_SFSPD_6_EPD_Msk (0x01UL << SCU_SFSPD_6_EPD_Pos) /*!< SCU SFSPD_6: EPD Mask */
+#define SCU_SFSPD_6_EPUN_Pos 4 /*!< SCU SFSPD_6: EPUN Position */
+#define SCU_SFSPD_6_EPUN_Msk (0x01UL << SCU_SFSPD_6_EPUN_Pos) /*!< SCU SFSPD_6: EPUN Mask */
+#define SCU_SFSPD_6_EHS_Pos 5 /*!< SCU SFSPD_6: EHS Position */
+#define SCU_SFSPD_6_EHS_Msk (0x01UL << SCU_SFSPD_6_EHS_Pos) /*!< SCU SFSPD_6: EHS Mask */
+#define SCU_SFSPD_6_EZI_Pos 6 /*!< SCU SFSPD_6: EZI Position */
+#define SCU_SFSPD_6_EZI_Msk (0x01UL << SCU_SFSPD_6_EZI_Pos) /*!< SCU SFSPD_6: EZI Mask */
+#define SCU_SFSPD_6_EHD_Pos 8 /*!< SCU SFSPD_6: EHD Position */
+#define SCU_SFSPD_6_EHD_Msk (0x03UL << SCU_SFSPD_6_EHD_Pos) /*!< SCU SFSPD_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSPD_7 ------------------------------------------
+#define SCU_SFSPD_7_MODE_Pos 0 /*!< SCU SFSPD_7: MODE Position */
+#define SCU_SFSPD_7_MODE_Msk (0x07UL << SCU_SFSPD_7_MODE_Pos) /*!< SCU SFSPD_7: MODE Mask */
+#define SCU_SFSPD_7_EPD_Pos 3 /*!< SCU SFSPD_7: EPD Position */
+#define SCU_SFSPD_7_EPD_Msk (0x01UL << SCU_SFSPD_7_EPD_Pos) /*!< SCU SFSPD_7: EPD Mask */
+#define SCU_SFSPD_7_EPUN_Pos 4 /*!< SCU SFSPD_7: EPUN Position */
+#define SCU_SFSPD_7_EPUN_Msk (0x01UL << SCU_SFSPD_7_EPUN_Pos) /*!< SCU SFSPD_7: EPUN Mask */
+#define SCU_SFSPD_7_EHS_Pos 5 /*!< SCU SFSPD_7: EHS Position */
+#define SCU_SFSPD_7_EHS_Msk (0x01UL << SCU_SFSPD_7_EHS_Pos) /*!< SCU SFSPD_7: EHS Mask */
+#define SCU_SFSPD_7_EZI_Pos 6 /*!< SCU SFSPD_7: EZI Position */
+#define SCU_SFSPD_7_EZI_Msk (0x01UL << SCU_SFSPD_7_EZI_Pos) /*!< SCU SFSPD_7: EZI Mask */
+#define SCU_SFSPD_7_EHD_Pos 8 /*!< SCU SFSPD_7: EHD Position */
+#define SCU_SFSPD_7_EHD_Msk (0x03UL << SCU_SFSPD_7_EHD_Pos) /*!< SCU SFSPD_7: EHD Mask */
+
+// --------------------------------------- SCU_SFSPD_8 ------------------------------------------
+#define SCU_SFSPD_8_MODE_Pos 0 /*!< SCU SFSPD_8: MODE Position */
+#define SCU_SFSPD_8_MODE_Msk (0x07UL << SCU_SFSPD_8_MODE_Pos) /*!< SCU SFSPD_8: MODE Mask */
+#define SCU_SFSPD_8_EPD_Pos 3 /*!< SCU SFSPD_8: EPD Position */
+#define SCU_SFSPD_8_EPD_Msk (0x01UL << SCU_SFSPD_8_EPD_Pos) /*!< SCU SFSPD_8: EPD Mask */
+#define SCU_SFSPD_8_EPUN_Pos 4 /*!< SCU SFSPD_8: EPUN Position */
+#define SCU_SFSPD_8_EPUN_Msk (0x01UL << SCU_SFSPD_8_EPUN_Pos) /*!< SCU SFSPD_8: EPUN Mask */
+#define SCU_SFSPD_8_EHS_Pos 5 /*!< SCU SFSPD_8: EHS Position */
+#define SCU_SFSPD_8_EHS_Msk (0x01UL << SCU_SFSPD_8_EHS_Pos) /*!< SCU SFSPD_8: EHS Mask */
+#define SCU_SFSPD_8_EZI_Pos 6 /*!< SCU SFSPD_8: EZI Position */
+#define SCU_SFSPD_8_EZI_Msk (0x01UL << SCU_SFSPD_8_EZI_Pos) /*!< SCU SFSPD_8: EZI Mask */
+#define SCU_SFSPD_8_EHD_Pos 8 /*!< SCU SFSPD_8: EHD Position */
+#define SCU_SFSPD_8_EHD_Msk (0x03UL << SCU_SFSPD_8_EHD_Pos) /*!< SCU SFSPD_8: EHD Mask */
+
+// --------------------------------------- SCU_SFSPD_9 ------------------------------------------
+#define SCU_SFSPD_9_MODE_Pos 0 /*!< SCU SFSPD_9: MODE Position */
+#define SCU_SFSPD_9_MODE_Msk (0x07UL << SCU_SFSPD_9_MODE_Pos) /*!< SCU SFSPD_9: MODE Mask */
+#define SCU_SFSPD_9_EPD_Pos 3 /*!< SCU SFSPD_9: EPD Position */
+#define SCU_SFSPD_9_EPD_Msk (0x01UL << SCU_SFSPD_9_EPD_Pos) /*!< SCU SFSPD_9: EPD Mask */
+#define SCU_SFSPD_9_EPUN_Pos 4 /*!< SCU SFSPD_9: EPUN Position */
+#define SCU_SFSPD_9_EPUN_Msk (0x01UL << SCU_SFSPD_9_EPUN_Pos) /*!< SCU SFSPD_9: EPUN Mask */
+#define SCU_SFSPD_9_EHS_Pos 5 /*!< SCU SFSPD_9: EHS Position */
+#define SCU_SFSPD_9_EHS_Msk (0x01UL << SCU_SFSPD_9_EHS_Pos) /*!< SCU SFSPD_9: EHS Mask */
+#define SCU_SFSPD_9_EZI_Pos 6 /*!< SCU SFSPD_9: EZI Position */
+#define SCU_SFSPD_9_EZI_Msk (0x01UL << SCU_SFSPD_9_EZI_Pos) /*!< SCU SFSPD_9: EZI Mask */
+#define SCU_SFSPD_9_EHD_Pos 8 /*!< SCU SFSPD_9: EHD Position */
+#define SCU_SFSPD_9_EHD_Msk (0x03UL << SCU_SFSPD_9_EHD_Pos) /*!< SCU SFSPD_9: EHD Mask */
+
+// -------------------------------------- SCU_SFSPD_10 ------------------------------------------
+#define SCU_SFSPD_10_MODE_Pos 0 /*!< SCU SFSPD_10: MODE Position */
+#define SCU_SFSPD_10_MODE_Msk (0x07UL << SCU_SFSPD_10_MODE_Pos) /*!< SCU SFSPD_10: MODE Mask */
+#define SCU_SFSPD_10_EPD_Pos 3 /*!< SCU SFSPD_10: EPD Position */
+#define SCU_SFSPD_10_EPD_Msk (0x01UL << SCU_SFSPD_10_EPD_Pos) /*!< SCU SFSPD_10: EPD Mask */
+#define SCU_SFSPD_10_EPUN_Pos 4 /*!< SCU SFSPD_10: EPUN Position */
+#define SCU_SFSPD_10_EPUN_Msk (0x01UL << SCU_SFSPD_10_EPUN_Pos) /*!< SCU SFSPD_10: EPUN Mask */
+#define SCU_SFSPD_10_EHS_Pos 5 /*!< SCU SFSPD_10: EHS Position */
+#define SCU_SFSPD_10_EHS_Msk (0x01UL << SCU_SFSPD_10_EHS_Pos) /*!< SCU SFSPD_10: EHS Mask */
+#define SCU_SFSPD_10_EZI_Pos 6 /*!< SCU SFSPD_10: EZI Position */
+#define SCU_SFSPD_10_EZI_Msk (0x01UL << SCU_SFSPD_10_EZI_Pos) /*!< SCU SFSPD_10: EZI Mask */
+#define SCU_SFSPD_10_EHD_Pos 8 /*!< SCU SFSPD_10: EHD Position */
+#define SCU_SFSPD_10_EHD_Msk (0x03UL << SCU_SFSPD_10_EHD_Pos) /*!< SCU SFSPD_10: EHD Mask */
+
+// -------------------------------------- SCU_SFSPD_11 ------------------------------------------
+#define SCU_SFSPD_11_MODE_Pos 0 /*!< SCU SFSPD_11: MODE Position */
+#define SCU_SFSPD_11_MODE_Msk (0x07UL << SCU_SFSPD_11_MODE_Pos) /*!< SCU SFSPD_11: MODE Mask */
+#define SCU_SFSPD_11_EPD_Pos 3 /*!< SCU SFSPD_11: EPD Position */
+#define SCU_SFSPD_11_EPD_Msk (0x01UL << SCU_SFSPD_11_EPD_Pos) /*!< SCU SFSPD_11: EPD Mask */
+#define SCU_SFSPD_11_EPUN_Pos 4 /*!< SCU SFSPD_11: EPUN Position */
+#define SCU_SFSPD_11_EPUN_Msk (0x01UL << SCU_SFSPD_11_EPUN_Pos) /*!< SCU SFSPD_11: EPUN Mask */
+#define SCU_SFSPD_11_EHS_Pos 5 /*!< SCU SFSPD_11: EHS Position */
+#define SCU_SFSPD_11_EHS_Msk (0x01UL << SCU_SFSPD_11_EHS_Pos) /*!< SCU SFSPD_11: EHS Mask */
+#define SCU_SFSPD_11_EZI_Pos 6 /*!< SCU SFSPD_11: EZI Position */
+#define SCU_SFSPD_11_EZI_Msk (0x01UL << SCU_SFSPD_11_EZI_Pos) /*!< SCU SFSPD_11: EZI Mask */
+#define SCU_SFSPD_11_EHD_Pos 8 /*!< SCU SFSPD_11: EHD Position */
+#define SCU_SFSPD_11_EHD_Msk (0x03UL << SCU_SFSPD_11_EHD_Pos) /*!< SCU SFSPD_11: EHD Mask */
+
+// -------------------------------------- SCU_SFSPD_12 ------------------------------------------
+#define SCU_SFSPD_12_MODE_Pos 0 /*!< SCU SFSPD_12: MODE Position */
+#define SCU_SFSPD_12_MODE_Msk (0x07UL << SCU_SFSPD_12_MODE_Pos) /*!< SCU SFSPD_12: MODE Mask */
+#define SCU_SFSPD_12_EPD_Pos 3 /*!< SCU SFSPD_12: EPD Position */
+#define SCU_SFSPD_12_EPD_Msk (0x01UL << SCU_SFSPD_12_EPD_Pos) /*!< SCU SFSPD_12: EPD Mask */
+#define SCU_SFSPD_12_EPUN_Pos 4 /*!< SCU SFSPD_12: EPUN Position */
+#define SCU_SFSPD_12_EPUN_Msk (0x01UL << SCU_SFSPD_12_EPUN_Pos) /*!< SCU SFSPD_12: EPUN Mask */
+#define SCU_SFSPD_12_EHS_Pos 5 /*!< SCU SFSPD_12: EHS Position */
+#define SCU_SFSPD_12_EHS_Msk (0x01UL << SCU_SFSPD_12_EHS_Pos) /*!< SCU SFSPD_12: EHS Mask */
+#define SCU_SFSPD_12_EZI_Pos 6 /*!< SCU SFSPD_12: EZI Position */
+#define SCU_SFSPD_12_EZI_Msk (0x01UL << SCU_SFSPD_12_EZI_Pos) /*!< SCU SFSPD_12: EZI Mask */
+#define SCU_SFSPD_12_EHD_Pos 8 /*!< SCU SFSPD_12: EHD Position */
+#define SCU_SFSPD_12_EHD_Msk (0x03UL << SCU_SFSPD_12_EHD_Pos) /*!< SCU SFSPD_12: EHD Mask */
+
+// -------------------------------------- SCU_SFSPD_13 ------------------------------------------
+#define SCU_SFSPD_13_MODE_Pos 0 /*!< SCU SFSPD_13: MODE Position */
+#define SCU_SFSPD_13_MODE_Msk (0x07UL << SCU_SFSPD_13_MODE_Pos) /*!< SCU SFSPD_13: MODE Mask */
+#define SCU_SFSPD_13_EPD_Pos 3 /*!< SCU SFSPD_13: EPD Position */
+#define SCU_SFSPD_13_EPD_Msk (0x01UL << SCU_SFSPD_13_EPD_Pos) /*!< SCU SFSPD_13: EPD Mask */
+#define SCU_SFSPD_13_EPUN_Pos 4 /*!< SCU SFSPD_13: EPUN Position */
+#define SCU_SFSPD_13_EPUN_Msk (0x01UL << SCU_SFSPD_13_EPUN_Pos) /*!< SCU SFSPD_13: EPUN Mask */
+#define SCU_SFSPD_13_EHS_Pos 5 /*!< SCU SFSPD_13: EHS Position */
+#define SCU_SFSPD_13_EHS_Msk (0x01UL << SCU_SFSPD_13_EHS_Pos) /*!< SCU SFSPD_13: EHS Mask */
+#define SCU_SFSPD_13_EZI_Pos 6 /*!< SCU SFSPD_13: EZI Position */
+#define SCU_SFSPD_13_EZI_Msk (0x01UL << SCU_SFSPD_13_EZI_Pos) /*!< SCU SFSPD_13: EZI Mask */
+#define SCU_SFSPD_13_EHD_Pos 8 /*!< SCU SFSPD_13: EHD Position */
+#define SCU_SFSPD_13_EHD_Msk (0x03UL << SCU_SFSPD_13_EHD_Pos) /*!< SCU SFSPD_13: EHD Mask */
+
+// -------------------------------------- SCU_SFSPD_14 ------------------------------------------
+#define SCU_SFSPD_14_MODE_Pos 0 /*!< SCU SFSPD_14: MODE Position */
+#define SCU_SFSPD_14_MODE_Msk (0x07UL << SCU_SFSPD_14_MODE_Pos) /*!< SCU SFSPD_14: MODE Mask */
+#define SCU_SFSPD_14_EPD_Pos 3 /*!< SCU SFSPD_14: EPD Position */
+#define SCU_SFSPD_14_EPD_Msk (0x01UL << SCU_SFSPD_14_EPD_Pos) /*!< SCU SFSPD_14: EPD Mask */
+#define SCU_SFSPD_14_EPUN_Pos 4 /*!< SCU SFSPD_14: EPUN Position */
+#define SCU_SFSPD_14_EPUN_Msk (0x01UL << SCU_SFSPD_14_EPUN_Pos) /*!< SCU SFSPD_14: EPUN Mask */
+#define SCU_SFSPD_14_EHS_Pos 5 /*!< SCU SFSPD_14: EHS Position */
+#define SCU_SFSPD_14_EHS_Msk (0x01UL << SCU_SFSPD_14_EHS_Pos) /*!< SCU SFSPD_14: EHS Mask */
+#define SCU_SFSPD_14_EZI_Pos 6 /*!< SCU SFSPD_14: EZI Position */
+#define SCU_SFSPD_14_EZI_Msk (0x01UL << SCU_SFSPD_14_EZI_Pos) /*!< SCU SFSPD_14: EZI Mask */
+#define SCU_SFSPD_14_EHD_Pos 8 /*!< SCU SFSPD_14: EHD Position */
+#define SCU_SFSPD_14_EHD_Msk (0x03UL << SCU_SFSPD_14_EHD_Pos) /*!< SCU SFSPD_14: EHD Mask */
+
+// -------------------------------------- SCU_SFSPD_15 ------------------------------------------
+#define SCU_SFSPD_15_MODE_Pos 0 /*!< SCU SFSPD_15: MODE Position */
+#define SCU_SFSPD_15_MODE_Msk (0x07UL << SCU_SFSPD_15_MODE_Pos) /*!< SCU SFSPD_15: MODE Mask */
+#define SCU_SFSPD_15_EPD_Pos 3 /*!< SCU SFSPD_15: EPD Position */
+#define SCU_SFSPD_15_EPD_Msk (0x01UL << SCU_SFSPD_15_EPD_Pos) /*!< SCU SFSPD_15: EPD Mask */
+#define SCU_SFSPD_15_EPUN_Pos 4 /*!< SCU SFSPD_15: EPUN Position */
+#define SCU_SFSPD_15_EPUN_Msk (0x01UL << SCU_SFSPD_15_EPUN_Pos) /*!< SCU SFSPD_15: EPUN Mask */
+#define SCU_SFSPD_15_EHS_Pos 5 /*!< SCU SFSPD_15: EHS Position */
+#define SCU_SFSPD_15_EHS_Msk (0x01UL << SCU_SFSPD_15_EHS_Pos) /*!< SCU SFSPD_15: EHS Mask */
+#define SCU_SFSPD_15_EZI_Pos 6 /*!< SCU SFSPD_15: EZI Position */
+#define SCU_SFSPD_15_EZI_Msk (0x01UL << SCU_SFSPD_15_EZI_Pos) /*!< SCU SFSPD_15: EZI Mask */
+#define SCU_SFSPD_15_EHD_Pos 8 /*!< SCU SFSPD_15: EHD Position */
+#define SCU_SFSPD_15_EHD_Msk (0x03UL << SCU_SFSPD_15_EHD_Pos) /*!< SCU SFSPD_15: EHD Mask */
+
+// -------------------------------------- SCU_SFSPD_16 ------------------------------------------
+#define SCU_SFSPD_16_MODE_Pos 0 /*!< SCU SFSPD_16: MODE Position */
+#define SCU_SFSPD_16_MODE_Msk (0x07UL << SCU_SFSPD_16_MODE_Pos) /*!< SCU SFSPD_16: MODE Mask */
+#define SCU_SFSPD_16_EPD_Pos 3 /*!< SCU SFSPD_16: EPD Position */
+#define SCU_SFSPD_16_EPD_Msk (0x01UL << SCU_SFSPD_16_EPD_Pos) /*!< SCU SFSPD_16: EPD Mask */
+#define SCU_SFSPD_16_EPUN_Pos 4 /*!< SCU SFSPD_16: EPUN Position */
+#define SCU_SFSPD_16_EPUN_Msk (0x01UL << SCU_SFSPD_16_EPUN_Pos) /*!< SCU SFSPD_16: EPUN Mask */
+#define SCU_SFSPD_16_EHS_Pos 5 /*!< SCU SFSPD_16: EHS Position */
+#define SCU_SFSPD_16_EHS_Msk (0x01UL << SCU_SFSPD_16_EHS_Pos) /*!< SCU SFSPD_16: EHS Mask */
+#define SCU_SFSPD_16_EZI_Pos 6 /*!< SCU SFSPD_16: EZI Position */
+#define SCU_SFSPD_16_EZI_Msk (0x01UL << SCU_SFSPD_16_EZI_Pos) /*!< SCU SFSPD_16: EZI Mask */
+#define SCU_SFSPD_16_EHD_Pos 8 /*!< SCU SFSPD_16: EHD Position */
+#define SCU_SFSPD_16_EHD_Msk (0x03UL << SCU_SFSPD_16_EHD_Pos) /*!< SCU SFSPD_16: EHD Mask */
+
+// --------------------------------------- SCU_SFSPE_0 ------------------------------------------
+#define SCU_SFSPE_0_MODE_Pos 0 /*!< SCU SFSPE_0: MODE Position */
+#define SCU_SFSPE_0_MODE_Msk (0x07UL << SCU_SFSPE_0_MODE_Pos) /*!< SCU SFSPE_0: MODE Mask */
+#define SCU_SFSPE_0_EPD_Pos 3 /*!< SCU SFSPE_0: EPD Position */
+#define SCU_SFSPE_0_EPD_Msk (0x01UL << SCU_SFSPE_0_EPD_Pos) /*!< SCU SFSPE_0: EPD Mask */
+#define SCU_SFSPE_0_EPUN_Pos 4 /*!< SCU SFSPE_0: EPUN Position */
+#define SCU_SFSPE_0_EPUN_Msk (0x01UL << SCU_SFSPE_0_EPUN_Pos) /*!< SCU SFSPE_0: EPUN Mask */
+#define SCU_SFSPE_0_EHS_Pos 5 /*!< SCU SFSPE_0: EHS Position */
+#define SCU_SFSPE_0_EHS_Msk (0x01UL << SCU_SFSPE_0_EHS_Pos) /*!< SCU SFSPE_0: EHS Mask */
+#define SCU_SFSPE_0_EZI_Pos 6 /*!< SCU SFSPE_0: EZI Position */
+#define SCU_SFSPE_0_EZI_Msk (0x01UL << SCU_SFSPE_0_EZI_Pos) /*!< SCU SFSPE_0: EZI Mask */
+#define SCU_SFSPE_0_EHD_Pos 8 /*!< SCU SFSPE_0: EHD Position */
+#define SCU_SFSPE_0_EHD_Msk (0x03UL << SCU_SFSPE_0_EHD_Pos) /*!< SCU SFSPE_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSPE_1 ------------------------------------------
+#define SCU_SFSPE_1_MODE_Pos 0 /*!< SCU SFSPE_1: MODE Position */
+#define SCU_SFSPE_1_MODE_Msk (0x07UL << SCU_SFSPE_1_MODE_Pos) /*!< SCU SFSPE_1: MODE Mask */
+#define SCU_SFSPE_1_EPD_Pos 3 /*!< SCU SFSPE_1: EPD Position */
+#define SCU_SFSPE_1_EPD_Msk (0x01UL << SCU_SFSPE_1_EPD_Pos) /*!< SCU SFSPE_1: EPD Mask */
+#define SCU_SFSPE_1_EPUN_Pos 4 /*!< SCU SFSPE_1: EPUN Position */
+#define SCU_SFSPE_1_EPUN_Msk (0x01UL << SCU_SFSPE_1_EPUN_Pos) /*!< SCU SFSPE_1: EPUN Mask */
+#define SCU_SFSPE_1_EHS_Pos 5 /*!< SCU SFSPE_1: EHS Position */
+#define SCU_SFSPE_1_EHS_Msk (0x01UL << SCU_SFSPE_1_EHS_Pos) /*!< SCU SFSPE_1: EHS Mask */
+#define SCU_SFSPE_1_EZI_Pos 6 /*!< SCU SFSPE_1: EZI Position */
+#define SCU_SFSPE_1_EZI_Msk (0x01UL << SCU_SFSPE_1_EZI_Pos) /*!< SCU SFSPE_1: EZI Mask */
+#define SCU_SFSPE_1_EHD_Pos 8 /*!< SCU SFSPE_1: EHD Position */
+#define SCU_SFSPE_1_EHD_Msk (0x03UL << SCU_SFSPE_1_EHD_Pos) /*!< SCU SFSPE_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSPE_2 ------------------------------------------
+#define SCU_SFSPE_2_MODE_Pos 0 /*!< SCU SFSPE_2: MODE Position */
+#define SCU_SFSPE_2_MODE_Msk (0x07UL << SCU_SFSPE_2_MODE_Pos) /*!< SCU SFSPE_2: MODE Mask */
+#define SCU_SFSPE_2_EPD_Pos 3 /*!< SCU SFSPE_2: EPD Position */
+#define SCU_SFSPE_2_EPD_Msk (0x01UL << SCU_SFSPE_2_EPD_Pos) /*!< SCU SFSPE_2: EPD Mask */
+#define SCU_SFSPE_2_EPUN_Pos 4 /*!< SCU SFSPE_2: EPUN Position */
+#define SCU_SFSPE_2_EPUN_Msk (0x01UL << SCU_SFSPE_2_EPUN_Pos) /*!< SCU SFSPE_2: EPUN Mask */
+#define SCU_SFSPE_2_EHS_Pos 5 /*!< SCU SFSPE_2: EHS Position */
+#define SCU_SFSPE_2_EHS_Msk (0x01UL << SCU_SFSPE_2_EHS_Pos) /*!< SCU SFSPE_2: EHS Mask */
+#define SCU_SFSPE_2_EZI_Pos 6 /*!< SCU SFSPE_2: EZI Position */
+#define SCU_SFSPE_2_EZI_Msk (0x01UL << SCU_SFSPE_2_EZI_Pos) /*!< SCU SFSPE_2: EZI Mask */
+#define SCU_SFSPE_2_EHD_Pos 8 /*!< SCU SFSPE_2: EHD Position */
+#define SCU_SFSPE_2_EHD_Msk (0x03UL << SCU_SFSPE_2_EHD_Pos) /*!< SCU SFSPE_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSPE_3 ------------------------------------------
+#define SCU_SFSPE_3_MODE_Pos 0 /*!< SCU SFSPE_3: MODE Position */
+#define SCU_SFSPE_3_MODE_Msk (0x07UL << SCU_SFSPE_3_MODE_Pos) /*!< SCU SFSPE_3: MODE Mask */
+#define SCU_SFSPE_3_EPD_Pos 3 /*!< SCU SFSPE_3: EPD Position */
+#define SCU_SFSPE_3_EPD_Msk (0x01UL << SCU_SFSPE_3_EPD_Pos) /*!< SCU SFSPE_3: EPD Mask */
+#define SCU_SFSPE_3_EPUN_Pos 4 /*!< SCU SFSPE_3: EPUN Position */
+#define SCU_SFSPE_3_EPUN_Msk (0x01UL << SCU_SFSPE_3_EPUN_Pos) /*!< SCU SFSPE_3: EPUN Mask */
+#define SCU_SFSPE_3_EHS_Pos 5 /*!< SCU SFSPE_3: EHS Position */
+#define SCU_SFSPE_3_EHS_Msk (0x01UL << SCU_SFSPE_3_EHS_Pos) /*!< SCU SFSPE_3: EHS Mask */
+#define SCU_SFSPE_3_EZI_Pos 6 /*!< SCU SFSPE_3: EZI Position */
+#define SCU_SFSPE_3_EZI_Msk (0x01UL << SCU_SFSPE_3_EZI_Pos) /*!< SCU SFSPE_3: EZI Mask */
+#define SCU_SFSPE_3_EHD_Pos 8 /*!< SCU SFSPE_3: EHD Position */
+#define SCU_SFSPE_3_EHD_Msk (0x03UL << SCU_SFSPE_3_EHD_Pos) /*!< SCU SFSPE_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSPE_4 ------------------------------------------
+#define SCU_SFSPE_4_MODE_Pos 0 /*!< SCU SFSPE_4: MODE Position */
+#define SCU_SFSPE_4_MODE_Msk (0x07UL << SCU_SFSPE_4_MODE_Pos) /*!< SCU SFSPE_4: MODE Mask */
+#define SCU_SFSPE_4_EPD_Pos 3 /*!< SCU SFSPE_4: EPD Position */
+#define SCU_SFSPE_4_EPD_Msk (0x01UL << SCU_SFSPE_4_EPD_Pos) /*!< SCU SFSPE_4: EPD Mask */
+#define SCU_SFSPE_4_EPUN_Pos 4 /*!< SCU SFSPE_4: EPUN Position */
+#define SCU_SFSPE_4_EPUN_Msk (0x01UL << SCU_SFSPE_4_EPUN_Pos) /*!< SCU SFSPE_4: EPUN Mask */
+#define SCU_SFSPE_4_EHS_Pos 5 /*!< SCU SFSPE_4: EHS Position */
+#define SCU_SFSPE_4_EHS_Msk (0x01UL << SCU_SFSPE_4_EHS_Pos) /*!< SCU SFSPE_4: EHS Mask */
+#define SCU_SFSPE_4_EZI_Pos 6 /*!< SCU SFSPE_4: EZI Position */
+#define SCU_SFSPE_4_EZI_Msk (0x01UL << SCU_SFSPE_4_EZI_Pos) /*!< SCU SFSPE_4: EZI Mask */
+#define SCU_SFSPE_4_EHD_Pos 8 /*!< SCU SFSPE_4: EHD Position */
+#define SCU_SFSPE_4_EHD_Msk (0x03UL << SCU_SFSPE_4_EHD_Pos) /*!< SCU SFSPE_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSPE_5 ------------------------------------------
+#define SCU_SFSPE_5_MODE_Pos 0 /*!< SCU SFSPE_5: MODE Position */
+#define SCU_SFSPE_5_MODE_Msk (0x07UL << SCU_SFSPE_5_MODE_Pos) /*!< SCU SFSPE_5: MODE Mask */
+#define SCU_SFSPE_5_EPD_Pos 3 /*!< SCU SFSPE_5: EPD Position */
+#define SCU_SFSPE_5_EPD_Msk (0x01UL << SCU_SFSPE_5_EPD_Pos) /*!< SCU SFSPE_5: EPD Mask */
+#define SCU_SFSPE_5_EPUN_Pos 4 /*!< SCU SFSPE_5: EPUN Position */
+#define SCU_SFSPE_5_EPUN_Msk (0x01UL << SCU_SFSPE_5_EPUN_Pos) /*!< SCU SFSPE_5: EPUN Mask */
+#define SCU_SFSPE_5_EHS_Pos 5 /*!< SCU SFSPE_5: EHS Position */
+#define SCU_SFSPE_5_EHS_Msk (0x01UL << SCU_SFSPE_5_EHS_Pos) /*!< SCU SFSPE_5: EHS Mask */
+#define SCU_SFSPE_5_EZI_Pos 6 /*!< SCU SFSPE_5: EZI Position */
+#define SCU_SFSPE_5_EZI_Msk (0x01UL << SCU_SFSPE_5_EZI_Pos) /*!< SCU SFSPE_5: EZI Mask */
+#define SCU_SFSPE_5_EHD_Pos 8 /*!< SCU SFSPE_5: EHD Position */
+#define SCU_SFSPE_5_EHD_Msk (0x03UL << SCU_SFSPE_5_EHD_Pos) /*!< SCU SFSPE_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSPE_6 ------------------------------------------
+#define SCU_SFSPE_6_MODE_Pos 0 /*!< SCU SFSPE_6: MODE Position */
+#define SCU_SFSPE_6_MODE_Msk (0x07UL << SCU_SFSPE_6_MODE_Pos) /*!< SCU SFSPE_6: MODE Mask */
+#define SCU_SFSPE_6_EPD_Pos 3 /*!< SCU SFSPE_6: EPD Position */
+#define SCU_SFSPE_6_EPD_Msk (0x01UL << SCU_SFSPE_6_EPD_Pos) /*!< SCU SFSPE_6: EPD Mask */
+#define SCU_SFSPE_6_EPUN_Pos 4 /*!< SCU SFSPE_6: EPUN Position */
+#define SCU_SFSPE_6_EPUN_Msk (0x01UL << SCU_SFSPE_6_EPUN_Pos) /*!< SCU SFSPE_6: EPUN Mask */
+#define SCU_SFSPE_6_EHS_Pos 5 /*!< SCU SFSPE_6: EHS Position */
+#define SCU_SFSPE_6_EHS_Msk (0x01UL << SCU_SFSPE_6_EHS_Pos) /*!< SCU SFSPE_6: EHS Mask */
+#define SCU_SFSPE_6_EZI_Pos 6 /*!< SCU SFSPE_6: EZI Position */
+#define SCU_SFSPE_6_EZI_Msk (0x01UL << SCU_SFSPE_6_EZI_Pos) /*!< SCU SFSPE_6: EZI Mask */
+#define SCU_SFSPE_6_EHD_Pos 8 /*!< SCU SFSPE_6: EHD Position */
+#define SCU_SFSPE_6_EHD_Msk (0x03UL << SCU_SFSPE_6_EHD_Pos) /*!< SCU SFSPE_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSPE_7 ------------------------------------------
+#define SCU_SFSPE_7_MODE_Pos 0 /*!< SCU SFSPE_7: MODE Position */
+#define SCU_SFSPE_7_MODE_Msk (0x07UL << SCU_SFSPE_7_MODE_Pos) /*!< SCU SFSPE_7: MODE Mask */
+#define SCU_SFSPE_7_EPD_Pos 3 /*!< SCU SFSPE_7: EPD Position */
+#define SCU_SFSPE_7_EPD_Msk (0x01UL << SCU_SFSPE_7_EPD_Pos) /*!< SCU SFSPE_7: EPD Mask */
+#define SCU_SFSPE_7_EPUN_Pos 4 /*!< SCU SFSPE_7: EPUN Position */
+#define SCU_SFSPE_7_EPUN_Msk (0x01UL << SCU_SFSPE_7_EPUN_Pos) /*!< SCU SFSPE_7: EPUN Mask */
+#define SCU_SFSPE_7_EHS_Pos 5 /*!< SCU SFSPE_7: EHS Position */
+#define SCU_SFSPE_7_EHS_Msk (0x01UL << SCU_SFSPE_7_EHS_Pos) /*!< SCU SFSPE_7: EHS Mask */
+#define SCU_SFSPE_7_EZI_Pos 6 /*!< SCU SFSPE_7: EZI Position */
+#define SCU_SFSPE_7_EZI_Msk (0x01UL << SCU_SFSPE_7_EZI_Pos) /*!< SCU SFSPE_7: EZI Mask */
+#define SCU_SFSPE_7_EHD_Pos 8 /*!< SCU SFSPE_7: EHD Position */
+#define SCU_SFSPE_7_EHD_Msk (0x03UL << SCU_SFSPE_7_EHD_Pos) /*!< SCU SFSPE_7: EHD Mask */
+
+// --------------------------------------- SCU_SFSPE_8 ------------------------------------------
+#define SCU_SFSPE_8_MODE_Pos 0 /*!< SCU SFSPE_8: MODE Position */
+#define SCU_SFSPE_8_MODE_Msk (0x07UL << SCU_SFSPE_8_MODE_Pos) /*!< SCU SFSPE_8: MODE Mask */
+#define SCU_SFSPE_8_EPD_Pos 3 /*!< SCU SFSPE_8: EPD Position */
+#define SCU_SFSPE_8_EPD_Msk (0x01UL << SCU_SFSPE_8_EPD_Pos) /*!< SCU SFSPE_8: EPD Mask */
+#define SCU_SFSPE_8_EPUN_Pos 4 /*!< SCU SFSPE_8: EPUN Position */
+#define SCU_SFSPE_8_EPUN_Msk (0x01UL << SCU_SFSPE_8_EPUN_Pos) /*!< SCU SFSPE_8: EPUN Mask */
+#define SCU_SFSPE_8_EHS_Pos 5 /*!< SCU SFSPE_8: EHS Position */
+#define SCU_SFSPE_8_EHS_Msk (0x01UL << SCU_SFSPE_8_EHS_Pos) /*!< SCU SFSPE_8: EHS Mask */
+#define SCU_SFSPE_8_EZI_Pos 6 /*!< SCU SFSPE_8: EZI Position */
+#define SCU_SFSPE_8_EZI_Msk (0x01UL << SCU_SFSPE_8_EZI_Pos) /*!< SCU SFSPE_8: EZI Mask */
+#define SCU_SFSPE_8_EHD_Pos 8 /*!< SCU SFSPE_8: EHD Position */
+#define SCU_SFSPE_8_EHD_Msk (0x03UL << SCU_SFSPE_8_EHD_Pos) /*!< SCU SFSPE_8: EHD Mask */
+
+// --------------------------------------- SCU_SFSPE_9 ------------------------------------------
+#define SCU_SFSPE_9_MODE_Pos 0 /*!< SCU SFSPE_9: MODE Position */
+#define SCU_SFSPE_9_MODE_Msk (0x07UL << SCU_SFSPE_9_MODE_Pos) /*!< SCU SFSPE_9: MODE Mask */
+#define SCU_SFSPE_9_EPD_Pos 3 /*!< SCU SFSPE_9: EPD Position */
+#define SCU_SFSPE_9_EPD_Msk (0x01UL << SCU_SFSPE_9_EPD_Pos) /*!< SCU SFSPE_9: EPD Mask */
+#define SCU_SFSPE_9_EPUN_Pos 4 /*!< SCU SFSPE_9: EPUN Position */
+#define SCU_SFSPE_9_EPUN_Msk (0x01UL << SCU_SFSPE_9_EPUN_Pos) /*!< SCU SFSPE_9: EPUN Mask */
+#define SCU_SFSPE_9_EHS_Pos 5 /*!< SCU SFSPE_9: EHS Position */
+#define SCU_SFSPE_9_EHS_Msk (0x01UL << SCU_SFSPE_9_EHS_Pos) /*!< SCU SFSPE_9: EHS Mask */
+#define SCU_SFSPE_9_EZI_Pos 6 /*!< SCU SFSPE_9: EZI Position */
+#define SCU_SFSPE_9_EZI_Msk (0x01UL << SCU_SFSPE_9_EZI_Pos) /*!< SCU SFSPE_9: EZI Mask */
+#define SCU_SFSPE_9_EHD_Pos 8 /*!< SCU SFSPE_9: EHD Position */
+#define SCU_SFSPE_9_EHD_Msk (0x03UL << SCU_SFSPE_9_EHD_Pos) /*!< SCU SFSPE_9: EHD Mask */
+
+// -------------------------------------- SCU_SFSPE_10 ------------------------------------------
+#define SCU_SFSPE_10_MODE_Pos 0 /*!< SCU SFSPE_10: MODE Position */
+#define SCU_SFSPE_10_MODE_Msk (0x07UL << SCU_SFSPE_10_MODE_Pos) /*!< SCU SFSPE_10: MODE Mask */
+#define SCU_SFSPE_10_EPD_Pos 3 /*!< SCU SFSPE_10: EPD Position */
+#define SCU_SFSPE_10_EPD_Msk (0x01UL << SCU_SFSPE_10_EPD_Pos) /*!< SCU SFSPE_10: EPD Mask */
+#define SCU_SFSPE_10_EPUN_Pos 4 /*!< SCU SFSPE_10: EPUN Position */
+#define SCU_SFSPE_10_EPUN_Msk (0x01UL << SCU_SFSPE_10_EPUN_Pos) /*!< SCU SFSPE_10: EPUN Mask */
+#define SCU_SFSPE_10_EHS_Pos 5 /*!< SCU SFSPE_10: EHS Position */
+#define SCU_SFSPE_10_EHS_Msk (0x01UL << SCU_SFSPE_10_EHS_Pos) /*!< SCU SFSPE_10: EHS Mask */
+#define SCU_SFSPE_10_EZI_Pos 6 /*!< SCU SFSPE_10: EZI Position */
+#define SCU_SFSPE_10_EZI_Msk (0x01UL << SCU_SFSPE_10_EZI_Pos) /*!< SCU SFSPE_10: EZI Mask */
+#define SCU_SFSPE_10_EHD_Pos 8 /*!< SCU SFSPE_10: EHD Position */
+#define SCU_SFSPE_10_EHD_Msk (0x03UL << SCU_SFSPE_10_EHD_Pos) /*!< SCU SFSPE_10: EHD Mask */
+
+// -------------------------------------- SCU_SFSPE_11 ------------------------------------------
+#define SCU_SFSPE_11_MODE_Pos 0 /*!< SCU SFSPE_11: MODE Position */
+#define SCU_SFSPE_11_MODE_Msk (0x07UL << SCU_SFSPE_11_MODE_Pos) /*!< SCU SFSPE_11: MODE Mask */
+#define SCU_SFSPE_11_EPD_Pos 3 /*!< SCU SFSPE_11: EPD Position */
+#define SCU_SFSPE_11_EPD_Msk (0x01UL << SCU_SFSPE_11_EPD_Pos) /*!< SCU SFSPE_11: EPD Mask */
+#define SCU_SFSPE_11_EPUN_Pos 4 /*!< SCU SFSPE_11: EPUN Position */
+#define SCU_SFSPE_11_EPUN_Msk (0x01UL << SCU_SFSPE_11_EPUN_Pos) /*!< SCU SFSPE_11: EPUN Mask */
+#define SCU_SFSPE_11_EHS_Pos 5 /*!< SCU SFSPE_11: EHS Position */
+#define SCU_SFSPE_11_EHS_Msk (0x01UL << SCU_SFSPE_11_EHS_Pos) /*!< SCU SFSPE_11: EHS Mask */
+#define SCU_SFSPE_11_EZI_Pos 6 /*!< SCU SFSPE_11: EZI Position */
+#define SCU_SFSPE_11_EZI_Msk (0x01UL << SCU_SFSPE_11_EZI_Pos) /*!< SCU SFSPE_11: EZI Mask */
+#define SCU_SFSPE_11_EHD_Pos 8 /*!< SCU SFSPE_11: EHD Position */
+#define SCU_SFSPE_11_EHD_Msk (0x03UL << SCU_SFSPE_11_EHD_Pos) /*!< SCU SFSPE_11: EHD Mask */
+
+// -------------------------------------- SCU_SFSPE_12 ------------------------------------------
+#define SCU_SFSPE_12_MODE_Pos 0 /*!< SCU SFSPE_12: MODE Position */
+#define SCU_SFSPE_12_MODE_Msk (0x07UL << SCU_SFSPE_12_MODE_Pos) /*!< SCU SFSPE_12: MODE Mask */
+#define SCU_SFSPE_12_EPD_Pos 3 /*!< SCU SFSPE_12: EPD Position */
+#define SCU_SFSPE_12_EPD_Msk (0x01UL << SCU_SFSPE_12_EPD_Pos) /*!< SCU SFSPE_12: EPD Mask */
+#define SCU_SFSPE_12_EPUN_Pos 4 /*!< SCU SFSPE_12: EPUN Position */
+#define SCU_SFSPE_12_EPUN_Msk (0x01UL << SCU_SFSPE_12_EPUN_Pos) /*!< SCU SFSPE_12: EPUN Mask */
+#define SCU_SFSPE_12_EHS_Pos 5 /*!< SCU SFSPE_12: EHS Position */
+#define SCU_SFSPE_12_EHS_Msk (0x01UL << SCU_SFSPE_12_EHS_Pos) /*!< SCU SFSPE_12: EHS Mask */
+#define SCU_SFSPE_12_EZI_Pos 6 /*!< SCU SFSPE_12: EZI Position */
+#define SCU_SFSPE_12_EZI_Msk (0x01UL << SCU_SFSPE_12_EZI_Pos) /*!< SCU SFSPE_12: EZI Mask */
+#define SCU_SFSPE_12_EHD_Pos 8 /*!< SCU SFSPE_12: EHD Position */
+#define SCU_SFSPE_12_EHD_Msk (0x03UL << SCU_SFSPE_12_EHD_Pos) /*!< SCU SFSPE_12: EHD Mask */
+
+// -------------------------------------- SCU_SFSPE_13 ------------------------------------------
+#define SCU_SFSPE_13_MODE_Pos 0 /*!< SCU SFSPE_13: MODE Position */
+#define SCU_SFSPE_13_MODE_Msk (0x07UL << SCU_SFSPE_13_MODE_Pos) /*!< SCU SFSPE_13: MODE Mask */
+#define SCU_SFSPE_13_EPD_Pos 3 /*!< SCU SFSPE_13: EPD Position */
+#define SCU_SFSPE_13_EPD_Msk (0x01UL << SCU_SFSPE_13_EPD_Pos) /*!< SCU SFSPE_13: EPD Mask */
+#define SCU_SFSPE_13_EPUN_Pos 4 /*!< SCU SFSPE_13: EPUN Position */
+#define SCU_SFSPE_13_EPUN_Msk (0x01UL << SCU_SFSPE_13_EPUN_Pos) /*!< SCU SFSPE_13: EPUN Mask */
+#define SCU_SFSPE_13_EHS_Pos 5 /*!< SCU SFSPE_13: EHS Position */
+#define SCU_SFSPE_13_EHS_Msk (0x01UL << SCU_SFSPE_13_EHS_Pos) /*!< SCU SFSPE_13: EHS Mask */
+#define SCU_SFSPE_13_EZI_Pos 6 /*!< SCU SFSPE_13: EZI Position */
+#define SCU_SFSPE_13_EZI_Msk (0x01UL << SCU_SFSPE_13_EZI_Pos) /*!< SCU SFSPE_13: EZI Mask */
+#define SCU_SFSPE_13_EHD_Pos 8 /*!< SCU SFSPE_13: EHD Position */
+#define SCU_SFSPE_13_EHD_Msk (0x03UL << SCU_SFSPE_13_EHD_Pos) /*!< SCU SFSPE_13: EHD Mask */
+
+// -------------------------------------- SCU_SFSPE_14 ------------------------------------------
+#define SCU_SFSPE_14_MODE_Pos 0 /*!< SCU SFSPE_14: MODE Position */
+#define SCU_SFSPE_14_MODE_Msk (0x07UL << SCU_SFSPE_14_MODE_Pos) /*!< SCU SFSPE_14: MODE Mask */
+#define SCU_SFSPE_14_EPD_Pos 3 /*!< SCU SFSPE_14: EPD Position */
+#define SCU_SFSPE_14_EPD_Msk (0x01UL << SCU_SFSPE_14_EPD_Pos) /*!< SCU SFSPE_14: EPD Mask */
+#define SCU_SFSPE_14_EPUN_Pos 4 /*!< SCU SFSPE_14: EPUN Position */
+#define SCU_SFSPE_14_EPUN_Msk (0x01UL << SCU_SFSPE_14_EPUN_Pos) /*!< SCU SFSPE_14: EPUN Mask */
+#define SCU_SFSPE_14_EHS_Pos 5 /*!< SCU SFSPE_14: EHS Position */
+#define SCU_SFSPE_14_EHS_Msk (0x01UL << SCU_SFSPE_14_EHS_Pos) /*!< SCU SFSPE_14: EHS Mask */
+#define SCU_SFSPE_14_EZI_Pos 6 /*!< SCU SFSPE_14: EZI Position */
+#define SCU_SFSPE_14_EZI_Msk (0x01UL << SCU_SFSPE_14_EZI_Pos) /*!< SCU SFSPE_14: EZI Mask */
+#define SCU_SFSPE_14_EHD_Pos 8 /*!< SCU SFSPE_14: EHD Position */
+#define SCU_SFSPE_14_EHD_Msk (0x03UL << SCU_SFSPE_14_EHD_Pos) /*!< SCU SFSPE_14: EHD Mask */
+
+// -------------------------------------- SCU_SFSPE_15 ------------------------------------------
+#define SCU_SFSPE_15_MODE_Pos 0 /*!< SCU SFSPE_15: MODE Position */
+#define SCU_SFSPE_15_MODE_Msk (0x07UL << SCU_SFSPE_15_MODE_Pos) /*!< SCU SFSPE_15: MODE Mask */
+#define SCU_SFSPE_15_EPD_Pos 3 /*!< SCU SFSPE_15: EPD Position */
+#define SCU_SFSPE_15_EPD_Msk (0x01UL << SCU_SFSPE_15_EPD_Pos) /*!< SCU SFSPE_15: EPD Mask */
+#define SCU_SFSPE_15_EPUN_Pos 4 /*!< SCU SFSPE_15: EPUN Position */
+#define SCU_SFSPE_15_EPUN_Msk (0x01UL << SCU_SFSPE_15_EPUN_Pos) /*!< SCU SFSPE_15: EPUN Mask */
+#define SCU_SFSPE_15_EHS_Pos 5 /*!< SCU SFSPE_15: EHS Position */
+#define SCU_SFSPE_15_EHS_Msk (0x01UL << SCU_SFSPE_15_EHS_Pos) /*!< SCU SFSPE_15: EHS Mask */
+#define SCU_SFSPE_15_EZI_Pos 6 /*!< SCU SFSPE_15: EZI Position */
+#define SCU_SFSPE_15_EZI_Msk (0x01UL << SCU_SFSPE_15_EZI_Pos) /*!< SCU SFSPE_15: EZI Mask */
+#define SCU_SFSPE_15_EHD_Pos 8 /*!< SCU SFSPE_15: EHD Position */
+#define SCU_SFSPE_15_EHD_Msk (0x03UL << SCU_SFSPE_15_EHD_Pos) /*!< SCU SFSPE_15: EHD Mask */
+
+// --------------------------------------- SCU_SFSPF_0 ------------------------------------------
+#define SCU_SFSPF_0_MODE_Pos 0 /*!< SCU SFSPF_0: MODE Position */
+#define SCU_SFSPF_0_MODE_Msk (0x07UL << SCU_SFSPF_0_MODE_Pos) /*!< SCU SFSPF_0: MODE Mask */
+#define SCU_SFSPF_0_EPD_Pos 3 /*!< SCU SFSPF_0: EPD Position */
+#define SCU_SFSPF_0_EPD_Msk (0x01UL << SCU_SFSPF_0_EPD_Pos) /*!< SCU SFSPF_0: EPD Mask */
+#define SCU_SFSPF_0_EPUN_Pos 4 /*!< SCU SFSPF_0: EPUN Position */
+#define SCU_SFSPF_0_EPUN_Msk (0x01UL << SCU_SFSPF_0_EPUN_Pos) /*!< SCU SFSPF_0: EPUN Mask */
+#define SCU_SFSPF_0_EHS_Pos 5 /*!< SCU SFSPF_0: EHS Position */
+#define SCU_SFSPF_0_EHS_Msk (0x01UL << SCU_SFSPF_0_EHS_Pos) /*!< SCU SFSPF_0: EHS Mask */
+#define SCU_SFSPF_0_EZI_Pos 6 /*!< SCU SFSPF_0: EZI Position */
+#define SCU_SFSPF_0_EZI_Msk (0x01UL << SCU_SFSPF_0_EZI_Pos) /*!< SCU SFSPF_0: EZI Mask */
+#define SCU_SFSPF_0_EHD_Pos 8 /*!< SCU SFSPF_0: EHD Position */
+#define SCU_SFSPF_0_EHD_Msk (0x03UL << SCU_SFSPF_0_EHD_Pos) /*!< SCU SFSPF_0: EHD Mask */
+
+// --------------------------------------- SCU_SFSPF_1 ------------------------------------------
+#define SCU_SFSPF_1_MODE_Pos 0 /*!< SCU SFSPF_1: MODE Position */
+#define SCU_SFSPF_1_MODE_Msk (0x07UL << SCU_SFSPF_1_MODE_Pos) /*!< SCU SFSPF_1: MODE Mask */
+#define SCU_SFSPF_1_EPD_Pos 3 /*!< SCU SFSPF_1: EPD Position */
+#define SCU_SFSPF_1_EPD_Msk (0x01UL << SCU_SFSPF_1_EPD_Pos) /*!< SCU SFSPF_1: EPD Mask */
+#define SCU_SFSPF_1_EPUN_Pos 4 /*!< SCU SFSPF_1: EPUN Position */
+#define SCU_SFSPF_1_EPUN_Msk (0x01UL << SCU_SFSPF_1_EPUN_Pos) /*!< SCU SFSPF_1: EPUN Mask */
+#define SCU_SFSPF_1_EHS_Pos 5 /*!< SCU SFSPF_1: EHS Position */
+#define SCU_SFSPF_1_EHS_Msk (0x01UL << SCU_SFSPF_1_EHS_Pos) /*!< SCU SFSPF_1: EHS Mask */
+#define SCU_SFSPF_1_EZI_Pos 6 /*!< SCU SFSPF_1: EZI Position */
+#define SCU_SFSPF_1_EZI_Msk (0x01UL << SCU_SFSPF_1_EZI_Pos) /*!< SCU SFSPF_1: EZI Mask */
+#define SCU_SFSPF_1_EHD_Pos 8 /*!< SCU SFSPF_1: EHD Position */
+#define SCU_SFSPF_1_EHD_Msk (0x03UL << SCU_SFSPF_1_EHD_Pos) /*!< SCU SFSPF_1: EHD Mask */
+
+// --------------------------------------- SCU_SFSPF_2 ------------------------------------------
+#define SCU_SFSPF_2_MODE_Pos 0 /*!< SCU SFSPF_2: MODE Position */
+#define SCU_SFSPF_2_MODE_Msk (0x07UL << SCU_SFSPF_2_MODE_Pos) /*!< SCU SFSPF_2: MODE Mask */
+#define SCU_SFSPF_2_EPD_Pos 3 /*!< SCU SFSPF_2: EPD Position */
+#define SCU_SFSPF_2_EPD_Msk (0x01UL << SCU_SFSPF_2_EPD_Pos) /*!< SCU SFSPF_2: EPD Mask */
+#define SCU_SFSPF_2_EPUN_Pos 4 /*!< SCU SFSPF_2: EPUN Position */
+#define SCU_SFSPF_2_EPUN_Msk (0x01UL << SCU_SFSPF_2_EPUN_Pos) /*!< SCU SFSPF_2: EPUN Mask */
+#define SCU_SFSPF_2_EHS_Pos 5 /*!< SCU SFSPF_2: EHS Position */
+#define SCU_SFSPF_2_EHS_Msk (0x01UL << SCU_SFSPF_2_EHS_Pos) /*!< SCU SFSPF_2: EHS Mask */
+#define SCU_SFSPF_2_EZI_Pos 6 /*!< SCU SFSPF_2: EZI Position */
+#define SCU_SFSPF_2_EZI_Msk (0x01UL << SCU_SFSPF_2_EZI_Pos) /*!< SCU SFSPF_2: EZI Mask */
+#define SCU_SFSPF_2_EHD_Pos 8 /*!< SCU SFSPF_2: EHD Position */
+#define SCU_SFSPF_2_EHD_Msk (0x03UL << SCU_SFSPF_2_EHD_Pos) /*!< SCU SFSPF_2: EHD Mask */
+
+// --------------------------------------- SCU_SFSPF_3 ------------------------------------------
+#define SCU_SFSPF_3_MODE_Pos 0 /*!< SCU SFSPF_3: MODE Position */
+#define SCU_SFSPF_3_MODE_Msk (0x07UL << SCU_SFSPF_3_MODE_Pos) /*!< SCU SFSPF_3: MODE Mask */
+#define SCU_SFSPF_3_EPD_Pos 3 /*!< SCU SFSPF_3: EPD Position */
+#define SCU_SFSPF_3_EPD_Msk (0x01UL << SCU_SFSPF_3_EPD_Pos) /*!< SCU SFSPF_3: EPD Mask */
+#define SCU_SFSPF_3_EPUN_Pos 4 /*!< SCU SFSPF_3: EPUN Position */
+#define SCU_SFSPF_3_EPUN_Msk (0x01UL << SCU_SFSPF_3_EPUN_Pos) /*!< SCU SFSPF_3: EPUN Mask */
+#define SCU_SFSPF_3_EHS_Pos 5 /*!< SCU SFSPF_3: EHS Position */
+#define SCU_SFSPF_3_EHS_Msk (0x01UL << SCU_SFSPF_3_EHS_Pos) /*!< SCU SFSPF_3: EHS Mask */
+#define SCU_SFSPF_3_EZI_Pos 6 /*!< SCU SFSPF_3: EZI Position */
+#define SCU_SFSPF_3_EZI_Msk (0x01UL << SCU_SFSPF_3_EZI_Pos) /*!< SCU SFSPF_3: EZI Mask */
+#define SCU_SFSPF_3_EHD_Pos 8 /*!< SCU SFSPF_3: EHD Position */
+#define SCU_SFSPF_3_EHD_Msk (0x03UL << SCU_SFSPF_3_EHD_Pos) /*!< SCU SFSPF_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSPF_4 ------------------------------------------
+#define SCU_SFSPF_4_MODE_Pos 0 /*!< SCU SFSPF_4: MODE Position */
+#define SCU_SFSPF_4_MODE_Msk (0x07UL << SCU_SFSPF_4_MODE_Pos) /*!< SCU SFSPF_4: MODE Mask */
+#define SCU_SFSPF_4_EPD_Pos 3 /*!< SCU SFSPF_4: EPD Position */
+#define SCU_SFSPF_4_EPD_Msk (0x01UL << SCU_SFSPF_4_EPD_Pos) /*!< SCU SFSPF_4: EPD Mask */
+#define SCU_SFSPF_4_EPUN_Pos 4 /*!< SCU SFSPF_4: EPUN Position */
+#define SCU_SFSPF_4_EPUN_Msk (0x01UL << SCU_SFSPF_4_EPUN_Pos) /*!< SCU SFSPF_4: EPUN Mask */
+#define SCU_SFSPF_4_EHS_Pos 5 /*!< SCU SFSPF_4: EHS Position */
+#define SCU_SFSPF_4_EHS_Msk (0x01UL << SCU_SFSPF_4_EHS_Pos) /*!< SCU SFSPF_4: EHS Mask */
+#define SCU_SFSPF_4_EZI_Pos 6 /*!< SCU SFSPF_4: EZI Position */
+#define SCU_SFSPF_4_EZI_Msk (0x01UL << SCU_SFSPF_4_EZI_Pos) /*!< SCU SFSPF_4: EZI Mask */
+#define SCU_SFSPF_4_EHD_Pos 8 /*!< SCU SFSPF_4: EHD Position */
+#define SCU_SFSPF_4_EHD_Msk (0x03UL << SCU_SFSPF_4_EHD_Pos) /*!< SCU SFSPF_4: EHD Mask */
+
+// --------------------------------------- SCU_SFSPF_5 ------------------------------------------
+#define SCU_SFSPF_5_MODE_Pos 0 /*!< SCU SFSPF_5: MODE Position */
+#define SCU_SFSPF_5_MODE_Msk (0x07UL << SCU_SFSPF_5_MODE_Pos) /*!< SCU SFSPF_5: MODE Mask */
+#define SCU_SFSPF_5_EPD_Pos 3 /*!< SCU SFSPF_5: EPD Position */
+#define SCU_SFSPF_5_EPD_Msk (0x01UL << SCU_SFSPF_5_EPD_Pos) /*!< SCU SFSPF_5: EPD Mask */
+#define SCU_SFSPF_5_EPUN_Pos 4 /*!< SCU SFSPF_5: EPUN Position */
+#define SCU_SFSPF_5_EPUN_Msk (0x01UL << SCU_SFSPF_5_EPUN_Pos) /*!< SCU SFSPF_5: EPUN Mask */
+#define SCU_SFSPF_5_EHS_Pos 5 /*!< SCU SFSPF_5: EHS Position */
+#define SCU_SFSPF_5_EHS_Msk (0x01UL << SCU_SFSPF_5_EHS_Pos) /*!< SCU SFSPF_5: EHS Mask */
+#define SCU_SFSPF_5_EZI_Pos 6 /*!< SCU SFSPF_5: EZI Position */
+#define SCU_SFSPF_5_EZI_Msk (0x01UL << SCU_SFSPF_5_EZI_Pos) /*!< SCU SFSPF_5: EZI Mask */
+#define SCU_SFSPF_5_EHD_Pos 8 /*!< SCU SFSPF_5: EHD Position */
+#define SCU_SFSPF_5_EHD_Msk (0x03UL << SCU_SFSPF_5_EHD_Pos) /*!< SCU SFSPF_5: EHD Mask */
+
+// --------------------------------------- SCU_SFSPF_6 ------------------------------------------
+#define SCU_SFSPF_6_MODE_Pos 0 /*!< SCU SFSPF_6: MODE Position */
+#define SCU_SFSPF_6_MODE_Msk (0x07UL << SCU_SFSPF_6_MODE_Pos) /*!< SCU SFSPF_6: MODE Mask */
+#define SCU_SFSPF_6_EPD_Pos 3 /*!< SCU SFSPF_6: EPD Position */
+#define SCU_SFSPF_6_EPD_Msk (0x01UL << SCU_SFSPF_6_EPD_Pos) /*!< SCU SFSPF_6: EPD Mask */
+#define SCU_SFSPF_6_EPUN_Pos 4 /*!< SCU SFSPF_6: EPUN Position */
+#define SCU_SFSPF_6_EPUN_Msk (0x01UL << SCU_SFSPF_6_EPUN_Pos) /*!< SCU SFSPF_6: EPUN Mask */
+#define SCU_SFSPF_6_EHS_Pos 5 /*!< SCU SFSPF_6: EHS Position */
+#define SCU_SFSPF_6_EHS_Msk (0x01UL << SCU_SFSPF_6_EHS_Pos) /*!< SCU SFSPF_6: EHS Mask */
+#define SCU_SFSPF_6_EZI_Pos 6 /*!< SCU SFSPF_6: EZI Position */
+#define SCU_SFSPF_6_EZI_Msk (0x01UL << SCU_SFSPF_6_EZI_Pos) /*!< SCU SFSPF_6: EZI Mask */
+#define SCU_SFSPF_6_EHD_Pos 8 /*!< SCU SFSPF_6: EHD Position */
+#define SCU_SFSPF_6_EHD_Msk (0x03UL << SCU_SFSPF_6_EHD_Pos) /*!< SCU SFSPF_6: EHD Mask */
+
+// --------------------------------------- SCU_SFSPF_7 ------------------------------------------
+#define SCU_SFSPF_7_MODE_Pos 0 /*!< SCU SFSPF_7: MODE Position */
+#define SCU_SFSPF_7_MODE_Msk (0x07UL << SCU_SFSPF_7_MODE_Pos) /*!< SCU SFSPF_7: MODE Mask */
+#define SCU_SFSPF_7_EPD_Pos 3 /*!< SCU SFSPF_7: EPD Position */
+#define SCU_SFSPF_7_EPD_Msk (0x01UL << SCU_SFSPF_7_EPD_Pos) /*!< SCU SFSPF_7: EPD Mask */
+#define SCU_SFSPF_7_EPUN_Pos 4 /*!< SCU SFSPF_7: EPUN Position */
+#define SCU_SFSPF_7_EPUN_Msk (0x01UL << SCU_SFSPF_7_EPUN_Pos) /*!< SCU SFSPF_7: EPUN Mask */
+#define SCU_SFSPF_7_EHS_Pos 5 /*!< SCU SFSPF_7: EHS Position */
+#define SCU_SFSPF_7_EHS_Msk (0x01UL << SCU_SFSPF_7_EHS_Pos) /*!< SCU SFSPF_7: EHS Mask */
+#define SCU_SFSPF_7_EZI_Pos 6 /*!< SCU SFSPF_7: EZI Position */
+#define SCU_SFSPF_7_EZI_Msk (0x01UL << SCU_SFSPF_7_EZI_Pos) /*!< SCU SFSPF_7: EZI Mask */
+#define SCU_SFSPF_7_EHD_Pos 8 /*!< SCU SFSPF_7: EHD Position */
+#define SCU_SFSPF_7_EHD_Msk (0x03UL << SCU_SFSPF_7_EHD_Pos) /*!< SCU SFSPF_7: EHD Mask */
+
+// --------------------------------------- SCU_SFSPF_8 ------------------------------------------
+#define SCU_SFSPF_8_MODE_Pos 0 /*!< SCU SFSPF_8: MODE Position */
+#define SCU_SFSPF_8_MODE_Msk (0x07UL << SCU_SFSPF_8_MODE_Pos) /*!< SCU SFSPF_8: MODE Mask */
+#define SCU_SFSPF_8_EPD_Pos 3 /*!< SCU SFSPF_8: EPD Position */
+#define SCU_SFSPF_8_EPD_Msk (0x01UL << SCU_SFSPF_8_EPD_Pos) /*!< SCU SFSPF_8: EPD Mask */
+#define SCU_SFSPF_8_EPUN_Pos 4 /*!< SCU SFSPF_8: EPUN Position */
+#define SCU_SFSPF_8_EPUN_Msk (0x01UL << SCU_SFSPF_8_EPUN_Pos) /*!< SCU SFSPF_8: EPUN Mask */
+#define SCU_SFSPF_8_EHS_Pos 5 /*!< SCU SFSPF_8: EHS Position */
+#define SCU_SFSPF_8_EHS_Msk (0x01UL << SCU_SFSPF_8_EHS_Pos) /*!< SCU SFSPF_8: EHS Mask */
+#define SCU_SFSPF_8_EZI_Pos 6 /*!< SCU SFSPF_8: EZI Position */
+#define SCU_SFSPF_8_EZI_Msk (0x01UL << SCU_SFSPF_8_EZI_Pos) /*!< SCU SFSPF_8: EZI Mask */
+#define SCU_SFSPF_8_EHD_Pos 8 /*!< SCU SFSPF_8: EHD Position */
+#define SCU_SFSPF_8_EHD_Msk (0x03UL << SCU_SFSPF_8_EHD_Pos) /*!< SCU SFSPF_8: EHD Mask */
+
+// --------------------------------------- SCU_SFSPF_9 ------------------------------------------
+#define SCU_SFSPF_9_MODE_Pos 0 /*!< SCU SFSPF_9: MODE Position */
+#define SCU_SFSPF_9_MODE_Msk (0x07UL << SCU_SFSPF_9_MODE_Pos) /*!< SCU SFSPF_9: MODE Mask */
+#define SCU_SFSPF_9_EPD_Pos 3 /*!< SCU SFSPF_9: EPD Position */
+#define SCU_SFSPF_9_EPD_Msk (0x01UL << SCU_SFSPF_9_EPD_Pos) /*!< SCU SFSPF_9: EPD Mask */
+#define SCU_SFSPF_9_EPUN_Pos 4 /*!< SCU SFSPF_9: EPUN Position */
+#define SCU_SFSPF_9_EPUN_Msk (0x01UL << SCU_SFSPF_9_EPUN_Pos) /*!< SCU SFSPF_9: EPUN Mask */
+#define SCU_SFSPF_9_EHS_Pos 5 /*!< SCU SFSPF_9: EHS Position */
+#define SCU_SFSPF_9_EHS_Msk (0x01UL << SCU_SFSPF_9_EHS_Pos) /*!< SCU SFSPF_9: EHS Mask */
+#define SCU_SFSPF_9_EZI_Pos 6 /*!< SCU SFSPF_9: EZI Position */
+#define SCU_SFSPF_9_EZI_Msk (0x01UL << SCU_SFSPF_9_EZI_Pos) /*!< SCU SFSPF_9: EZI Mask */
+#define SCU_SFSPF_9_EHD_Pos 8 /*!< SCU SFSPF_9: EHD Position */
+#define SCU_SFSPF_9_EHD_Msk (0x03UL << SCU_SFSPF_9_EHD_Pos) /*!< SCU SFSPF_9: EHD Mask */
+
+// -------------------------------------- SCU_SFSPF_10 ------------------------------------------
+#define SCU_SFSPF_10_MODE_Pos 0 /*!< SCU SFSPF_10: MODE Position */
+#define SCU_SFSPF_10_MODE_Msk (0x07UL << SCU_SFSPF_10_MODE_Pos) /*!< SCU SFSPF_10: MODE Mask */
+#define SCU_SFSPF_10_EPD_Pos 3 /*!< SCU SFSPF_10: EPD Position */
+#define SCU_SFSPF_10_EPD_Msk (0x01UL << SCU_SFSPF_10_EPD_Pos) /*!< SCU SFSPF_10: EPD Mask */
+#define SCU_SFSPF_10_EPUN_Pos 4 /*!< SCU SFSPF_10: EPUN Position */
+#define SCU_SFSPF_10_EPUN_Msk (0x01UL << SCU_SFSPF_10_EPUN_Pos) /*!< SCU SFSPF_10: EPUN Mask */
+#define SCU_SFSPF_10_EHS_Pos 5 /*!< SCU SFSPF_10: EHS Position */
+#define SCU_SFSPF_10_EHS_Msk (0x01UL << SCU_SFSPF_10_EHS_Pos) /*!< SCU SFSPF_10: EHS Mask */
+#define SCU_SFSPF_10_EZI_Pos 6 /*!< SCU SFSPF_10: EZI Position */
+#define SCU_SFSPF_10_EZI_Msk (0x01UL << SCU_SFSPF_10_EZI_Pos) /*!< SCU SFSPF_10: EZI Mask */
+#define SCU_SFSPF_10_EHD_Pos 8 /*!< SCU SFSPF_10: EHD Position */
+#define SCU_SFSPF_10_EHD_Msk (0x03UL << SCU_SFSPF_10_EHD_Pos) /*!< SCU SFSPF_10: EHD Mask */
+
+// -------------------------------------- SCU_SFSPF_11 ------------------------------------------
+#define SCU_SFSPF_11_MODE_Pos 0 /*!< SCU SFSPF_11: MODE Position */
+#define SCU_SFSPF_11_MODE_Msk (0x07UL << SCU_SFSPF_11_MODE_Pos) /*!< SCU SFSPF_11: MODE Mask */
+#define SCU_SFSPF_11_EPD_Pos 3 /*!< SCU SFSPF_11: EPD Position */
+#define SCU_SFSPF_11_EPD_Msk (0x01UL << SCU_SFSPF_11_EPD_Pos) /*!< SCU SFSPF_11: EPD Mask */
+#define SCU_SFSPF_11_EPUN_Pos 4 /*!< SCU SFSPF_11: EPUN Position */
+#define SCU_SFSPF_11_EPUN_Msk (0x01UL << SCU_SFSPF_11_EPUN_Pos) /*!< SCU SFSPF_11: EPUN Mask */
+#define SCU_SFSPF_11_EHS_Pos 5 /*!< SCU SFSPF_11: EHS Position */
+#define SCU_SFSPF_11_EHS_Msk (0x01UL << SCU_SFSPF_11_EHS_Pos) /*!< SCU SFSPF_11: EHS Mask */
+#define SCU_SFSPF_11_EZI_Pos 6 /*!< SCU SFSPF_11: EZI Position */
+#define SCU_SFSPF_11_EZI_Msk (0x01UL << SCU_SFSPF_11_EZI_Pos) /*!< SCU SFSPF_11: EZI Mask */
+#define SCU_SFSPF_11_EHD_Pos 8 /*!< SCU SFSPF_11: EHD Position */
+#define SCU_SFSPF_11_EHD_Msk (0x03UL << SCU_SFSPF_11_EHD_Pos) /*!< SCU SFSPF_11: EHD Mask */
+
+// -------------------------------------- SCU_SFSCLK_0 ------------------------------------------
+#define SCU_SFSCLK_0_MODE_Pos 0 /*!< SCU SFSCLK_0: MODE Position */
+#define SCU_SFSCLK_0_MODE_Msk (0x07UL << SCU_SFSCLK_0_MODE_Pos) /*!< SCU SFSCLK_0: MODE Mask */
+#define SCU_SFSCLK_0_EPD_Pos 3 /*!< SCU SFSCLK_0: EPD Position */
+#define SCU_SFSCLK_0_EPD_Msk (0x01UL << SCU_SFSCLK_0_EPD_Pos) /*!< SCU SFSCLK_0: EPD Mask */
+#define SCU_SFSCLK_0_EPUN_Pos 4 /*!< SCU SFSCLK_0: EPUN Position */
+#define SCU_SFSCLK_0_EPUN_Msk (0x01UL << SCU_SFSCLK_0_EPUN_Pos) /*!< SCU SFSCLK_0: EPUN Mask */
+#define SCU_SFSCLK_0_EHS_Pos 5 /*!< SCU SFSCLK_0: EHS Position */
+#define SCU_SFSCLK_0_EHS_Msk (0x01UL << SCU_SFSCLK_0_EHS_Pos) /*!< SCU SFSCLK_0: EHS Mask */
+#define SCU_SFSCLK_0_EZI_Pos 6 /*!< SCU SFSCLK_0: EZI Position */
+#define SCU_SFSCLK_0_EZI_Msk (0x01UL << SCU_SFSCLK_0_EZI_Pos) /*!< SCU SFSCLK_0: EZI Mask */
+#define SCU_SFSCLK_0_EHD_Pos 8 /*!< SCU SFSCLK_0: EHD Position */
+#define SCU_SFSCLK_0_EHD_Msk (0x03UL << SCU_SFSCLK_0_EHD_Pos) /*!< SCU SFSCLK_0: EHD Mask */
+
+// -------------------------------------- SCU_SFSCLK_1 ------------------------------------------
+#define SCU_SFSCLK_1_MODE_Pos 0 /*!< SCU SFSCLK_1: MODE Position */
+#define SCU_SFSCLK_1_MODE_Msk (0x07UL << SCU_SFSCLK_1_MODE_Pos) /*!< SCU SFSCLK_1: MODE Mask */
+#define SCU_SFSCLK_1_EPD_Pos 3 /*!< SCU SFSCLK_1: EPD Position */
+#define SCU_SFSCLK_1_EPD_Msk (0x01UL << SCU_SFSCLK_1_EPD_Pos) /*!< SCU SFSCLK_1: EPD Mask */
+#define SCU_SFSCLK_1_EPUN_Pos 4 /*!< SCU SFSCLK_1: EPUN Position */
+#define SCU_SFSCLK_1_EPUN_Msk (0x01UL << SCU_SFSCLK_1_EPUN_Pos) /*!< SCU SFSCLK_1: EPUN Mask */
+#define SCU_SFSCLK_1_EHS_Pos 5 /*!< SCU SFSCLK_1: EHS Position */
+#define SCU_SFSCLK_1_EHS_Msk (0x01UL << SCU_SFSCLK_1_EHS_Pos) /*!< SCU SFSCLK_1: EHS Mask */
+#define SCU_SFSCLK_1_EZI_Pos 6 /*!< SCU SFSCLK_1: EZI Position */
+#define SCU_SFSCLK_1_EZI_Msk (0x01UL << SCU_SFSCLK_1_EZI_Pos) /*!< SCU SFSCLK_1: EZI Mask */
+#define SCU_SFSCLK_1_EHD_Pos 8 /*!< SCU SFSCLK_1: EHD Position */
+#define SCU_SFSCLK_1_EHD_Msk (0x03UL << SCU_SFSCLK_1_EHD_Pos) /*!< SCU SFSCLK_1: EHD Mask */
+
+// -------------------------------------- SCU_SFSCLK_2 ------------------------------------------
+#define SCU_SFSCLK_2_MODE_Pos 0 /*!< SCU SFSCLK_2: MODE Position */
+#define SCU_SFSCLK_2_MODE_Msk (0x07UL << SCU_SFSCLK_2_MODE_Pos) /*!< SCU SFSCLK_2: MODE Mask */
+#define SCU_SFSCLK_2_EPD_Pos 3 /*!< SCU SFSCLK_2: EPD Position */
+#define SCU_SFSCLK_2_EPD_Msk (0x01UL << SCU_SFSCLK_2_EPD_Pos) /*!< SCU SFSCLK_2: EPD Mask */
+#define SCU_SFSCLK_2_EPUN_Pos 4 /*!< SCU SFSCLK_2: EPUN Position */
+#define SCU_SFSCLK_2_EPUN_Msk (0x01UL << SCU_SFSCLK_2_EPUN_Pos) /*!< SCU SFSCLK_2: EPUN Mask */
+#define SCU_SFSCLK_2_EHS_Pos 5 /*!< SCU SFSCLK_2: EHS Position */
+#define SCU_SFSCLK_2_EHS_Msk (0x01UL << SCU_SFSCLK_2_EHS_Pos) /*!< SCU SFSCLK_2: EHS Mask */
+#define SCU_SFSCLK_2_EZI_Pos 6 /*!< SCU SFSCLK_2: EZI Position */
+#define SCU_SFSCLK_2_EZI_Msk (0x01UL << SCU_SFSCLK_2_EZI_Pos) /*!< SCU SFSCLK_2: EZI Mask */
+#define SCU_SFSCLK_2_EHD_Pos 8 /*!< SCU SFSCLK_2: EHD Position */
+#define SCU_SFSCLK_2_EHD_Msk (0x03UL << SCU_SFSCLK_2_EHD_Pos) /*!< SCU SFSCLK_2: EHD Mask */
+
+// -------------------------------------- SCU_SFSCLK_3 ------------------------------------------
+#define SCU_SFSCLK_3_MODE_Pos 0 /*!< SCU SFSCLK_3: MODE Position */
+#define SCU_SFSCLK_3_MODE_Msk (0x07UL << SCU_SFSCLK_3_MODE_Pos) /*!< SCU SFSCLK_3: MODE Mask */
+#define SCU_SFSCLK_3_EPD_Pos 3 /*!< SCU SFSCLK_3: EPD Position */
+#define SCU_SFSCLK_3_EPD_Msk (0x01UL << SCU_SFSCLK_3_EPD_Pos) /*!< SCU SFSCLK_3: EPD Mask */
+#define SCU_SFSCLK_3_EPUN_Pos 4 /*!< SCU SFSCLK_3: EPUN Position */
+#define SCU_SFSCLK_3_EPUN_Msk (0x01UL << SCU_SFSCLK_3_EPUN_Pos) /*!< SCU SFSCLK_3: EPUN Mask */
+#define SCU_SFSCLK_3_EHS_Pos 5 /*!< SCU SFSCLK_3: EHS Position */
+#define SCU_SFSCLK_3_EHS_Msk (0x01UL << SCU_SFSCLK_3_EHS_Pos) /*!< SCU SFSCLK_3: EHS Mask */
+#define SCU_SFSCLK_3_EZI_Pos 6 /*!< SCU SFSCLK_3: EZI Position */
+#define SCU_SFSCLK_3_EZI_Msk (0x01UL << SCU_SFSCLK_3_EZI_Pos) /*!< SCU SFSCLK_3: EZI Mask */
+#define SCU_SFSCLK_3_EHD_Pos 8 /*!< SCU SFSCLK_3: EHD Position */
+#define SCU_SFSCLK_3_EHD_Msk (0x03UL << SCU_SFSCLK_3_EHD_Pos) /*!< SCU SFSCLK_3: EHD Mask */
+
+// --------------------------------------- SCU_SFSUSB -------------------------------------------
+#define SCU_SFSUSB_USB_AIM_Pos 0 /*!< SCU SFSUSB: USB_AIM Position */
+#define SCU_SFSUSB_USB_AIM_Msk (0x01UL << SCU_SFSUSB_USB_AIM_Pos) /*!< SCU SFSUSB: USB_AIM Mask */
+#define SCU_SFSUSB_USB_ESEA_Pos 1 /*!< SCU SFSUSB: USB_ESEA Position */
+#define SCU_SFSUSB_USB_ESEA_Msk (0x01UL << SCU_SFSUSB_USB_ESEA_Pos) /*!< SCU SFSUSB: USB_ESEA Mask */
+
+// --------------------------------------- SCU_SFSI2C0 ------------------------------------------
+#define SCU_SFSI2C0_SDA_EHS_Pos 0 /*!< SCU SFSI2C0: SDA_EHS Position */
+#define SCU_SFSI2C0_SDA_EHS_Msk (0x01UL << SCU_SFSI2C0_SDA_EHS_Pos) /*!< SCU SFSI2C0: SDA_EHS Mask */
+#define SCU_SFSI2C0_SCL_EHS_Pos 1 /*!< SCU SFSI2C0: SCL_EHS Position */
+#define SCU_SFSI2C0_SCL_EHS_Msk (0x01UL << SCU_SFSI2C0_SCL_EHS_Pos) /*!< SCU SFSI2C0: SCL_EHS Mask */
+#define SCU_SFSI2C0_SCL_ECS_Pos 2 /*!< SCU SFSI2C0: SCL_ECS Position */
+#define SCU_SFSI2C0_SCL_ECS_Msk (0x01UL << SCU_SFSI2C0_SCL_ECS_Pos) /*!< SCU SFSI2C0: SCL_ECS Mask */
+
+// --------------------------------------- SCU_ENAIO0 -------------------------------------------
+#define SCU_ENAIO0_ADC0_0_Pos 0 /*!< SCU ENAIO0: ADC0_0 Position */
+#define SCU_ENAIO0_ADC0_0_Msk (0x01UL << SCU_ENAIO0_ADC0_0_Pos) /*!< SCU ENAIO0: ADC0_0 Mask */
+#define SCU_ENAIO0_ADC0_1_Pos 1 /*!< SCU ENAIO0: ADC0_1 Position */
+#define SCU_ENAIO0_ADC0_1_Msk (0x01UL << SCU_ENAIO0_ADC0_1_Pos) /*!< SCU ENAIO0: ADC0_1 Mask */
+#define SCU_ENAIO0_ADC0_2_Pos 2 /*!< SCU ENAIO0: ADC0_2 Position */
+#define SCU_ENAIO0_ADC0_2_Msk (0x01UL << SCU_ENAIO0_ADC0_2_Pos) /*!< SCU ENAIO0: ADC0_2 Mask */
+#define SCU_ENAIO0_ADC0_3_Pos 3 /*!< SCU ENAIO0: ADC0_3 Position */
+#define SCU_ENAIO0_ADC0_3_Msk (0x01UL << SCU_ENAIO0_ADC0_3_Pos) /*!< SCU ENAIO0: ADC0_3 Mask */
+#define SCU_ENAIO0_ADC0_4_Pos 4 /*!< SCU ENAIO0: ADC0_4 Position */
+#define SCU_ENAIO0_ADC0_4_Msk (0x01UL << SCU_ENAIO0_ADC0_4_Pos) /*!< SCU ENAIO0: ADC0_4 Mask */
+#define SCU_ENAIO0_ADC0_5_Pos 5 /*!< SCU ENAIO0: ADC0_5 Position */
+#define SCU_ENAIO0_ADC0_5_Msk (0x01UL << SCU_ENAIO0_ADC0_5_Pos) /*!< SCU ENAIO0: ADC0_5 Mask */
+#define SCU_ENAIO0_ADC0_6_Pos 6 /*!< SCU ENAIO0: ADC0_6 Position */
+#define SCU_ENAIO0_ADC0_6_Msk (0x01UL << SCU_ENAIO0_ADC0_6_Pos) /*!< SCU ENAIO0: ADC0_6 Mask */
+
+// --------------------------------------- SCU_ENAIO1 -------------------------------------------
+#define SCU_ENAIO1_ADC1_0_Pos 0 /*!< SCU ENAIO1: ADC1_0 Position */
+#define SCU_ENAIO1_ADC1_0_Msk (0x01UL << SCU_ENAIO1_ADC1_0_Pos) /*!< SCU ENAIO1: ADC1_0 Mask */
+#define SCU_ENAIO1_ADC1_1_Pos 1 /*!< SCU ENAIO1: ADC1_1 Position */
+#define SCU_ENAIO1_ADC1_1_Msk (0x01UL << SCU_ENAIO1_ADC1_1_Pos) /*!< SCU ENAIO1: ADC1_1 Mask */
+#define SCU_ENAIO1_ADC1_2_Pos 2 /*!< SCU ENAIO1: ADC1_2 Position */
+#define SCU_ENAIO1_ADC1_2_Msk (0x01UL << SCU_ENAIO1_ADC1_2_Pos) /*!< SCU ENAIO1: ADC1_2 Mask */
+#define SCU_ENAIO1_ADC1_3_Pos 3 /*!< SCU ENAIO1: ADC1_3 Position */
+#define SCU_ENAIO1_ADC1_3_Msk (0x01UL << SCU_ENAIO1_ADC1_3_Pos) /*!< SCU ENAIO1: ADC1_3 Mask */
+#define SCU_ENAIO1_ADC1_4_Pos 4 /*!< SCU ENAIO1: ADC1_4 Position */
+#define SCU_ENAIO1_ADC1_4_Msk (0x01UL << SCU_ENAIO1_ADC1_4_Pos) /*!< SCU ENAIO1: ADC1_4 Mask */
+#define SCU_ENAIO1_ADC1_5_Pos 5 /*!< SCU ENAIO1: ADC1_5 Position */
+#define SCU_ENAIO1_ADC1_5_Msk (0x01UL << SCU_ENAIO1_ADC1_5_Pos) /*!< SCU ENAIO1: ADC1_5 Mask */
+#define SCU_ENAIO1_ADC1_6_Pos 6 /*!< SCU ENAIO1: ADC1_6 Position */
+#define SCU_ENAIO1_ADC1_6_Msk (0x01UL << SCU_ENAIO1_ADC1_6_Pos) /*!< SCU ENAIO1: ADC1_6 Mask */
+#define SCU_ENAIO1_ADC1_7_Pos 7 /*!< SCU ENAIO1: ADC1_7 Position */
+#define SCU_ENAIO1_ADC1_7_Msk (0x01UL << SCU_ENAIO1_ADC1_7_Pos) /*!< SCU ENAIO1: ADC1_7 Mask */
+
+// --------------------------------------- SCU_ENAIO2 -------------------------------------------
+#define SCU_ENAIO2_DAC_Pos 0 /*!< SCU ENAIO2: DAC Position */
+#define SCU_ENAIO2_DAC_Msk (0x01UL << SCU_ENAIO2_DAC_Pos) /*!< SCU ENAIO2: DAC Mask */
+#define SCU_ENAIO2_BG_Pos 4 /*!< SCU ENAIO2: BG Position */
+#define SCU_ENAIO2_BG_Msk (0x01UL << SCU_ENAIO2_BG_Pos) /*!< SCU ENAIO2: BG Mask */
+
+// ------------------------------------- SCU_EMCDELAYCLK ----------------------------------------
+#define SCU_EMCDELAYCLK_CLK0_DELAY_Pos 0 /*!< SCU EMCDELAYCLK: CLK0_DELAY Position */
+#define SCU_EMCDELAYCLK_CLK0_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CLK0_DELAY_Pos) /*!< SCU EMCDELAYCLK: CLK0_DELAY Mask */
+#define SCU_EMCDELAYCLK_CLK1_DELAY_Pos 4 /*!< SCU EMCDELAYCLK: CLK1_DELAY Position */
+#define SCU_EMCDELAYCLK_CLK1_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CLK1_DELAY_Pos) /*!< SCU EMCDELAYCLK: CLK1_DELAY Mask */
+#define SCU_EMCDELAYCLK_CLK2_DELAY_Pos 8 /*!< SCU EMCDELAYCLK: CLK2_DELAY Position */
+#define SCU_EMCDELAYCLK_CLK2_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CLK2_DELAY_Pos) /*!< SCU EMCDELAYCLK: CLK2_DELAY Mask */
+#define SCU_EMCDELAYCLK_CLK3_DELAY_Pos 12 /*!< SCU EMCDELAYCLK: CLK3_DELAY Position */
+#define SCU_EMCDELAYCLK_CLK3_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CLK3_DELAY_Pos) /*!< SCU EMCDELAYCLK: CLK3_DELAY Mask */
+#define SCU_EMCDELAYCLK_CKE0_DELAY_Pos 16 /*!< SCU EMCDELAYCLK: CKE0_DELAY Position */
+#define SCU_EMCDELAYCLK_CKE0_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CKE0_DELAY_Pos) /*!< SCU EMCDELAYCLK: CKE0_DELAY Mask */
+#define SCU_EMCDELAYCLK_CKE1_DELAY_Pos 20 /*!< SCU EMCDELAYCLK: CKE1_DELAY Position */
+#define SCU_EMCDELAYCLK_CKE1_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CKE1_DELAY_Pos) /*!< SCU EMCDELAYCLK: CKE1_DELAY Mask */
+#define SCU_EMCDELAYCLK_CKE2_DELAY_Pos 24 /*!< SCU EMCDELAYCLK: CKE2_DELAY Position */
+#define SCU_EMCDELAYCLK_CKE2_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CKE2_DELAY_Pos) /*!< SCU EMCDELAYCLK: CKE2_DELAY Mask */
+#define SCU_EMCDELAYCLK_CKE3_DELAY_Pos 28 /*!< SCU EMCDELAYCLK: CKE3_DELAY Position */
+#define SCU_EMCDELAYCLK_CKE3_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CKE3_DELAY_Pos) /*!< SCU EMCDELAYCLK: CKE3_DELAY Mask */
+
+// -------------------------------------- SCU_PINTSEL0 ------------------------------------------
+#define SCU_PINTSEL0_INTPIN0_Pos 0 /*!< SCU PINTSEL0: INTPIN0 Position */
+#define SCU_PINTSEL0_INTPIN0_Msk (0x1fUL << SCU_PINTSEL0_INTPIN0_Pos) /*!< SCU PINTSEL0: INTPIN0 Mask */
+#define SCU_PINTSEL0_PORTSEL0_Pos 5 /*!< SCU PINTSEL0: PORTSEL0 Position */
+#define SCU_PINTSEL0_PORTSEL0_Msk (0x07UL << SCU_PINTSEL0_PORTSEL0_Pos) /*!< SCU PINTSEL0: PORTSEL0 Mask */
+#define SCU_PINTSEL0_INTPIN1_Pos 8 /*!< SCU PINTSEL0: INTPIN1 Position */
+#define SCU_PINTSEL0_INTPIN1_Msk (0x1fUL << SCU_PINTSEL0_INTPIN1_Pos) /*!< SCU PINTSEL0: INTPIN1 Mask */
+#define SCU_PINTSEL0_PORTSEL1_Pos 13 /*!< SCU PINTSEL0: PORTSEL1 Position */
+#define SCU_PINTSEL0_PORTSEL1_Msk (0x07UL << SCU_PINTSEL0_PORTSEL1_Pos) /*!< SCU PINTSEL0: PORTSEL1 Mask */
+#define SCU_PINTSEL0_INTPIN2_Pos 16 /*!< SCU PINTSEL0: INTPIN2 Position */
+#define SCU_PINTSEL0_INTPIN2_Msk (0x1fUL << SCU_PINTSEL0_INTPIN2_Pos) /*!< SCU PINTSEL0: INTPIN2 Mask */
+#define SCU_PINTSEL0_PORTSEL2_Pos 21 /*!< SCU PINTSEL0: PORTSEL2 Position */
+#define SCU_PINTSEL0_PORTSEL2_Msk (0x07UL << SCU_PINTSEL0_PORTSEL2_Pos) /*!< SCU PINTSEL0: PORTSEL2 Mask */
+#define SCU_PINTSEL0_INTPIN3_Pos 24 /*!< SCU PINTSEL0: INTPIN3 Position */
+#define SCU_PINTSEL0_INTPIN3_Msk (0x1fUL << SCU_PINTSEL0_INTPIN3_Pos) /*!< SCU PINTSEL0: INTPIN3 Mask */
+#define SCU_PINTSEL0_PORTSEL3_Pos 29 /*!< SCU PINTSEL0: PORTSEL3 Position */
+#define SCU_PINTSEL0_PORTSEL3_Msk (0x07UL << SCU_PINTSEL0_PORTSEL3_Pos) /*!< SCU PINTSEL0: PORTSEL3 Mask */
+
+// -------------------------------------- SCU_PINTSEL1 ------------------------------------------
+#define SCU_PINTSEL1_INTPIN4_Pos 0 /*!< SCU PINTSEL1: INTPIN4 Position */
+#define SCU_PINTSEL1_INTPIN4_Msk (0x1fUL << SCU_PINTSEL1_INTPIN4_Pos) /*!< SCU PINTSEL1: INTPIN4 Mask */
+#define SCU_PINTSEL1_PORTSEL4_Pos 5 /*!< SCU PINTSEL1: PORTSEL4 Position */
+#define SCU_PINTSEL1_PORTSEL4_Msk (0x07UL << SCU_PINTSEL1_PORTSEL4_Pos) /*!< SCU PINTSEL1: PORTSEL4 Mask */
+#define SCU_PINTSEL1_INTPIN5_Pos 8 /*!< SCU PINTSEL1: INTPIN5 Position */
+#define SCU_PINTSEL1_INTPIN5_Msk (0x1fUL << SCU_PINTSEL1_INTPIN5_Pos) /*!< SCU PINTSEL1: INTPIN5 Mask */
+#define SCU_PINTSEL1_PORTSEL5_Pos 13 /*!< SCU PINTSEL1: PORTSEL5 Position */
+#define SCU_PINTSEL1_PORTSEL5_Msk (0x07UL << SCU_PINTSEL1_PORTSEL5_Pos) /*!< SCU PINTSEL1: PORTSEL5 Mask */
+#define SCU_PINTSEL1_INTPIN6_Pos 16 /*!< SCU PINTSEL1: INTPIN6 Position */
+#define SCU_PINTSEL1_INTPIN6_Msk (0x1fUL << SCU_PINTSEL1_INTPIN6_Pos) /*!< SCU PINTSEL1: INTPIN6 Mask */
+#define SCU_PINTSEL1_PORTSEL6_Pos 21 /*!< SCU PINTSEL1: PORTSEL6 Position */
+#define SCU_PINTSEL1_PORTSEL6_Msk (0x07UL << SCU_PINTSEL1_PORTSEL6_Pos) /*!< SCU PINTSEL1: PORTSEL6 Mask */
+#define SCU_PINTSEL1_INTPIN7_Pos 24 /*!< SCU PINTSEL1: INTPIN7 Position */
+#define SCU_PINTSEL1_INTPIN7_Msk (0x1fUL << SCU_PINTSEL1_INTPIN7_Pos) /*!< SCU PINTSEL1: INTPIN7 Mask */
+#define SCU_PINTSEL1_PORTSEL7_Pos 29 /*!< SCU PINTSEL1: PORTSEL7 Position */
+#define SCU_PINTSEL1_PORTSEL7_Msk (0x07UL << SCU_PINTSEL1_PORTSEL7_Pos) /*!< SCU PINTSEL1: PORTSEL7 Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_PIN_INT Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ------------------------------------ GPIO_PIN_INT_ISEL ---------------------------------------
+#define GPIO_PIN_INT_ISEL_PMODE0_Pos 0 /*!< GPIO_PIN_INT ISEL: PMODE0 Position */
+#define GPIO_PIN_INT_ISEL_PMODE0_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE0_Pos) /*!< GPIO_PIN_INT ISEL: PMODE0 Mask */
+#define GPIO_PIN_INT_ISEL_PMODE1_Pos 1 /*!< GPIO_PIN_INT ISEL: PMODE1 Position */
+#define GPIO_PIN_INT_ISEL_PMODE1_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE1_Pos) /*!< GPIO_PIN_INT ISEL: PMODE1 Mask */
+#define GPIO_PIN_INT_ISEL_PMODE2_Pos 2 /*!< GPIO_PIN_INT ISEL: PMODE2 Position */
+#define GPIO_PIN_INT_ISEL_PMODE2_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE2_Pos) /*!< GPIO_PIN_INT ISEL: PMODE2 Mask */
+#define GPIO_PIN_INT_ISEL_PMODE3_Pos 3 /*!< GPIO_PIN_INT ISEL: PMODE3 Position */
+#define GPIO_PIN_INT_ISEL_PMODE3_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE3_Pos) /*!< GPIO_PIN_INT ISEL: PMODE3 Mask */
+#define GPIO_PIN_INT_ISEL_PMODE4_Pos 4 /*!< GPIO_PIN_INT ISEL: PMODE4 Position */
+#define GPIO_PIN_INT_ISEL_PMODE4_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE4_Pos) /*!< GPIO_PIN_INT ISEL: PMODE4 Mask */
+#define GPIO_PIN_INT_ISEL_PMODE5_Pos 5 /*!< GPIO_PIN_INT ISEL: PMODE5 Position */
+#define GPIO_PIN_INT_ISEL_PMODE5_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE5_Pos) /*!< GPIO_PIN_INT ISEL: PMODE5 Mask */
+#define GPIO_PIN_INT_ISEL_PMODE6_Pos 6 /*!< GPIO_PIN_INT ISEL: PMODE6 Position */
+#define GPIO_PIN_INT_ISEL_PMODE6_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE6_Pos) /*!< GPIO_PIN_INT ISEL: PMODE6 Mask */
+#define GPIO_PIN_INT_ISEL_PMODE7_Pos 7 /*!< GPIO_PIN_INT ISEL: PMODE7 Position */
+#define GPIO_PIN_INT_ISEL_PMODE7_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE7_Pos) /*!< GPIO_PIN_INT ISEL: PMODE7 Mask */
+
+// ------------------------------------ GPIO_PIN_INT_IENR ---------------------------------------
+#define GPIO_PIN_INT_IENR_ENRL0_Pos 0 /*!< GPIO_PIN_INT IENR: ENRL0 Position */
+#define GPIO_PIN_INT_IENR_ENRL0_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL0_Pos) /*!< GPIO_PIN_INT IENR: ENRL0 Mask */
+#define GPIO_PIN_INT_IENR_ENRL1_Pos 1 /*!< GPIO_PIN_INT IENR: ENRL1 Position */
+#define GPIO_PIN_INT_IENR_ENRL1_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL1_Pos) /*!< GPIO_PIN_INT IENR: ENRL1 Mask */
+#define GPIO_PIN_INT_IENR_ENRL2_Pos 2 /*!< GPIO_PIN_INT IENR: ENRL2 Position */
+#define GPIO_PIN_INT_IENR_ENRL2_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL2_Pos) /*!< GPIO_PIN_INT IENR: ENRL2 Mask */
+#define GPIO_PIN_INT_IENR_ENRL3_Pos 3 /*!< GPIO_PIN_INT IENR: ENRL3 Position */
+#define GPIO_PIN_INT_IENR_ENRL3_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL3_Pos) /*!< GPIO_PIN_INT IENR: ENRL3 Mask */
+#define GPIO_PIN_INT_IENR_ENRL4_Pos 4 /*!< GPIO_PIN_INT IENR: ENRL4 Position */
+#define GPIO_PIN_INT_IENR_ENRL4_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL4_Pos) /*!< GPIO_PIN_INT IENR: ENRL4 Mask */
+#define GPIO_PIN_INT_IENR_ENRL5_Pos 5 /*!< GPIO_PIN_INT IENR: ENRL5 Position */
+#define GPIO_PIN_INT_IENR_ENRL5_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL5_Pos) /*!< GPIO_PIN_INT IENR: ENRL5 Mask */
+#define GPIO_PIN_INT_IENR_ENRL6_Pos 6 /*!< GPIO_PIN_INT IENR: ENRL6 Position */
+#define GPIO_PIN_INT_IENR_ENRL6_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL6_Pos) /*!< GPIO_PIN_INT IENR: ENRL6 Mask */
+#define GPIO_PIN_INT_IENR_ENRL7_Pos 7 /*!< GPIO_PIN_INT IENR: ENRL7 Position */
+#define GPIO_PIN_INT_IENR_ENRL7_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL7_Pos) /*!< GPIO_PIN_INT IENR: ENRL7 Mask */
+
+// ----------------------------------- GPIO_PIN_INT_SIENR ---------------------------------------
+#define GPIO_PIN_INT_SIENR_SETENRL0_Pos 0 /*!< GPIO_PIN_INT SIENR: SETENRL0 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL0_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL0_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL0 Mask */
+#define GPIO_PIN_INT_SIENR_SETENRL1_Pos 1 /*!< GPIO_PIN_INT SIENR: SETENRL1 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL1_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL1_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL1 Mask */
+#define GPIO_PIN_INT_SIENR_SETENRL2_Pos 2 /*!< GPIO_PIN_INT SIENR: SETENRL2 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL2_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL2_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL2 Mask */
+#define GPIO_PIN_INT_SIENR_SETENRL3_Pos 3 /*!< GPIO_PIN_INT SIENR: SETENRL3 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL3_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL3_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL3 Mask */
+#define GPIO_PIN_INT_SIENR_SETENRL4_Pos 4 /*!< GPIO_PIN_INT SIENR: SETENRL4 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL4_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL4_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL4 Mask */
+#define GPIO_PIN_INT_SIENR_SETENRL5_Pos 5 /*!< GPIO_PIN_INT SIENR: SETENRL5 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL5_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL5_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL5 Mask */
+#define GPIO_PIN_INT_SIENR_SETENRL6_Pos 6 /*!< GPIO_PIN_INT SIENR: SETENRL6 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL6_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL6_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL6 Mask */
+#define GPIO_PIN_INT_SIENR_SETENRL7_Pos 7 /*!< GPIO_PIN_INT SIENR: SETENRL7 Position */
+#define GPIO_PIN_INT_SIENR_SETENRL7_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL7_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL7 Mask */
+
+// ----------------------------------- GPIO_PIN_INT_CIENR ---------------------------------------
+#define GPIO_PIN_INT_CIENR_CENRL0_Pos 0 /*!< GPIO_PIN_INT CIENR: CENRL0 Position */
+#define GPIO_PIN_INT_CIENR_CENRL0_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL0_Pos) /*!< GPIO_PIN_INT CIENR: CENRL0 Mask */
+#define GPIO_PIN_INT_CIENR_CENRL1_Pos 1 /*!< GPIO_PIN_INT CIENR: CENRL1 Position */
+#define GPIO_PIN_INT_CIENR_CENRL1_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL1_Pos) /*!< GPIO_PIN_INT CIENR: CENRL1 Mask */
+#define GPIO_PIN_INT_CIENR_CENRL2_Pos 2 /*!< GPIO_PIN_INT CIENR: CENRL2 Position */
+#define GPIO_PIN_INT_CIENR_CENRL2_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL2_Pos) /*!< GPIO_PIN_INT CIENR: CENRL2 Mask */
+#define GPIO_PIN_INT_CIENR_CENRL3_Pos 3 /*!< GPIO_PIN_INT CIENR: CENRL3 Position */
+#define GPIO_PIN_INT_CIENR_CENRL3_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL3_Pos) /*!< GPIO_PIN_INT CIENR: CENRL3 Mask */
+#define GPIO_PIN_INT_CIENR_CENRL4_Pos 4 /*!< GPIO_PIN_INT CIENR: CENRL4 Position */
+#define GPIO_PIN_INT_CIENR_CENRL4_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL4_Pos) /*!< GPIO_PIN_INT CIENR: CENRL4 Mask */
+#define GPIO_PIN_INT_CIENR_CENRL5_Pos 5 /*!< GPIO_PIN_INT CIENR: CENRL5 Position */
+#define GPIO_PIN_INT_CIENR_CENRL5_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL5_Pos) /*!< GPIO_PIN_INT CIENR: CENRL5 Mask */
+#define GPIO_PIN_INT_CIENR_CENRL6_Pos 6 /*!< GPIO_PIN_INT CIENR: CENRL6 Position */
+#define GPIO_PIN_INT_CIENR_CENRL6_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL6_Pos) /*!< GPIO_PIN_INT CIENR: CENRL6 Mask */
+#define GPIO_PIN_INT_CIENR_CENRL7_Pos 7 /*!< GPIO_PIN_INT CIENR: CENRL7 Position */
+#define GPIO_PIN_INT_CIENR_CENRL7_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL7_Pos) /*!< GPIO_PIN_INT CIENR: CENRL7 Mask */
+
+// ------------------------------------ GPIO_PIN_INT_IENF ---------------------------------------
+#define GPIO_PIN_INT_IENF_ENAF0_Pos 0 /*!< GPIO_PIN_INT IENF: ENAF0 Position */
+#define GPIO_PIN_INT_IENF_ENAF0_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF0_Pos) /*!< GPIO_PIN_INT IENF: ENAF0 Mask */
+#define GPIO_PIN_INT_IENF_ENAF1_Pos 1 /*!< GPIO_PIN_INT IENF: ENAF1 Position */
+#define GPIO_PIN_INT_IENF_ENAF1_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF1_Pos) /*!< GPIO_PIN_INT IENF: ENAF1 Mask */
+#define GPIO_PIN_INT_IENF_ENAF2_Pos 2 /*!< GPIO_PIN_INT IENF: ENAF2 Position */
+#define GPIO_PIN_INT_IENF_ENAF2_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF2_Pos) /*!< GPIO_PIN_INT IENF: ENAF2 Mask */
+#define GPIO_PIN_INT_IENF_ENAF3_Pos 3 /*!< GPIO_PIN_INT IENF: ENAF3 Position */
+#define GPIO_PIN_INT_IENF_ENAF3_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF3_Pos) /*!< GPIO_PIN_INT IENF: ENAF3 Mask */
+#define GPIO_PIN_INT_IENF_ENAF4_Pos 4 /*!< GPIO_PIN_INT IENF: ENAF4 Position */
+#define GPIO_PIN_INT_IENF_ENAF4_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF4_Pos) /*!< GPIO_PIN_INT IENF: ENAF4 Mask */
+#define GPIO_PIN_INT_IENF_ENAF5_Pos 5 /*!< GPIO_PIN_INT IENF: ENAF5 Position */
+#define GPIO_PIN_INT_IENF_ENAF5_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF5_Pos) /*!< GPIO_PIN_INT IENF: ENAF5 Mask */
+#define GPIO_PIN_INT_IENF_ENAF6_Pos 6 /*!< GPIO_PIN_INT IENF: ENAF6 Position */
+#define GPIO_PIN_INT_IENF_ENAF6_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF6_Pos) /*!< GPIO_PIN_INT IENF: ENAF6 Mask */
+#define GPIO_PIN_INT_IENF_ENAF7_Pos 7 /*!< GPIO_PIN_INT IENF: ENAF7 Position */
+#define GPIO_PIN_INT_IENF_ENAF7_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF7_Pos) /*!< GPIO_PIN_INT IENF: ENAF7 Mask */
+
+// ----------------------------------- GPIO_PIN_INT_SIENF ---------------------------------------
+#define GPIO_PIN_INT_SIENF_SETENAF0_Pos 0 /*!< GPIO_PIN_INT SIENF: SETENAF0 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF0_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF0_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF0 Mask */
+#define GPIO_PIN_INT_SIENF_SETENAF1_Pos 1 /*!< GPIO_PIN_INT SIENF: SETENAF1 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF1_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF1_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF1 Mask */
+#define GPIO_PIN_INT_SIENF_SETENAF2_Pos 2 /*!< GPIO_PIN_INT SIENF: SETENAF2 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF2_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF2_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF2 Mask */
+#define GPIO_PIN_INT_SIENF_SETENAF3_Pos 3 /*!< GPIO_PIN_INT SIENF: SETENAF3 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF3_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF3_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF3 Mask */
+#define GPIO_PIN_INT_SIENF_SETENAF4_Pos 4 /*!< GPIO_PIN_INT SIENF: SETENAF4 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF4_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF4_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF4 Mask */
+#define GPIO_PIN_INT_SIENF_SETENAF5_Pos 5 /*!< GPIO_PIN_INT SIENF: SETENAF5 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF5_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF5_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF5 Mask */
+#define GPIO_PIN_INT_SIENF_SETENAF6_Pos 6 /*!< GPIO_PIN_INT SIENF: SETENAF6 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF6_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF6_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF6 Mask */
+#define GPIO_PIN_INT_SIENF_SETENAF7_Pos 7 /*!< GPIO_PIN_INT SIENF: SETENAF7 Position */
+#define GPIO_PIN_INT_SIENF_SETENAF7_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF7_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF7 Mask */
+
+// ----------------------------------- GPIO_PIN_INT_CIENF ---------------------------------------
+#define GPIO_PIN_INT_CIENF_CENAF0_Pos 0 /*!< GPIO_PIN_INT CIENF: CENAF0 Position */
+#define GPIO_PIN_INT_CIENF_CENAF0_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF0_Pos) /*!< GPIO_PIN_INT CIENF: CENAF0 Mask */
+#define GPIO_PIN_INT_CIENF_CENAF1_Pos 1 /*!< GPIO_PIN_INT CIENF: CENAF1 Position */
+#define GPIO_PIN_INT_CIENF_CENAF1_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF1_Pos) /*!< GPIO_PIN_INT CIENF: CENAF1 Mask */
+#define GPIO_PIN_INT_CIENF_CENAF2_Pos 2 /*!< GPIO_PIN_INT CIENF: CENAF2 Position */
+#define GPIO_PIN_INT_CIENF_CENAF2_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF2_Pos) /*!< GPIO_PIN_INT CIENF: CENAF2 Mask */
+#define GPIO_PIN_INT_CIENF_CENAF3_Pos 3 /*!< GPIO_PIN_INT CIENF: CENAF3 Position */
+#define GPIO_PIN_INT_CIENF_CENAF3_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF3_Pos) /*!< GPIO_PIN_INT CIENF: CENAF3 Mask */
+#define GPIO_PIN_INT_CIENF_CENAF4_Pos 4 /*!< GPIO_PIN_INT CIENF: CENAF4 Position */
+#define GPIO_PIN_INT_CIENF_CENAF4_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF4_Pos) /*!< GPIO_PIN_INT CIENF: CENAF4 Mask */
+#define GPIO_PIN_INT_CIENF_CENAF5_Pos 5 /*!< GPIO_PIN_INT CIENF: CENAF5 Position */
+#define GPIO_PIN_INT_CIENF_CENAF5_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF5_Pos) /*!< GPIO_PIN_INT CIENF: CENAF5 Mask */
+#define GPIO_PIN_INT_CIENF_CENAF6_Pos 6 /*!< GPIO_PIN_INT CIENF: CENAF6 Position */
+#define GPIO_PIN_INT_CIENF_CENAF6_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF6_Pos) /*!< GPIO_PIN_INT CIENF: CENAF6 Mask */
+#define GPIO_PIN_INT_CIENF_CENAF7_Pos 7 /*!< GPIO_PIN_INT CIENF: CENAF7 Position */
+#define GPIO_PIN_INT_CIENF_CENAF7_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF7_Pos) /*!< GPIO_PIN_INT CIENF: CENAF7 Mask */
+
+// ------------------------------------ GPIO_PIN_INT_RISE ---------------------------------------
+#define GPIO_PIN_INT_RISE_RDET0_Pos 0 /*!< GPIO_PIN_INT RISE: RDET0 Position */
+#define GPIO_PIN_INT_RISE_RDET0_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET0_Pos) /*!< GPIO_PIN_INT RISE: RDET0 Mask */
+#define GPIO_PIN_INT_RISE_RDET1_Pos 1 /*!< GPIO_PIN_INT RISE: RDET1 Position */
+#define GPIO_PIN_INT_RISE_RDET1_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET1_Pos) /*!< GPIO_PIN_INT RISE: RDET1 Mask */
+#define GPIO_PIN_INT_RISE_RDET2_Pos 2 /*!< GPIO_PIN_INT RISE: RDET2 Position */
+#define GPIO_PIN_INT_RISE_RDET2_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET2_Pos) /*!< GPIO_PIN_INT RISE: RDET2 Mask */
+#define GPIO_PIN_INT_RISE_RDET3_Pos 3 /*!< GPIO_PIN_INT RISE: RDET3 Position */
+#define GPIO_PIN_INT_RISE_RDET3_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET3_Pos) /*!< GPIO_PIN_INT RISE: RDET3 Mask */
+#define GPIO_PIN_INT_RISE_RDET4_Pos 4 /*!< GPIO_PIN_INT RISE: RDET4 Position */
+#define GPIO_PIN_INT_RISE_RDET4_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET4_Pos) /*!< GPIO_PIN_INT RISE: RDET4 Mask */
+#define GPIO_PIN_INT_RISE_RDET5_Pos 5 /*!< GPIO_PIN_INT RISE: RDET5 Position */
+#define GPIO_PIN_INT_RISE_RDET5_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET5_Pos) /*!< GPIO_PIN_INT RISE: RDET5 Mask */
+#define GPIO_PIN_INT_RISE_RDET6_Pos 6 /*!< GPIO_PIN_INT RISE: RDET6 Position */
+#define GPIO_PIN_INT_RISE_RDET6_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET6_Pos) /*!< GPIO_PIN_INT RISE: RDET6 Mask */
+#define GPIO_PIN_INT_RISE_RDET7_Pos 7 /*!< GPIO_PIN_INT RISE: RDET7 Position */
+#define GPIO_PIN_INT_RISE_RDET7_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET7_Pos) /*!< GPIO_PIN_INT RISE: RDET7 Mask */
+
+// ------------------------------------ GPIO_PIN_INT_FALL ---------------------------------------
+#define GPIO_PIN_INT_FALL_FDET0_Pos 0 /*!< GPIO_PIN_INT FALL: FDET0 Position */
+#define GPIO_PIN_INT_FALL_FDET0_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET0_Pos) /*!< GPIO_PIN_INT FALL: FDET0 Mask */
+#define GPIO_PIN_INT_FALL_FDET1_Pos 1 /*!< GPIO_PIN_INT FALL: FDET1 Position */
+#define GPIO_PIN_INT_FALL_FDET1_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET1_Pos) /*!< GPIO_PIN_INT FALL: FDET1 Mask */
+#define GPIO_PIN_INT_FALL_FDET2_Pos 2 /*!< GPIO_PIN_INT FALL: FDET2 Position */
+#define GPIO_PIN_INT_FALL_FDET2_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET2_Pos) /*!< GPIO_PIN_INT FALL: FDET2 Mask */
+#define GPIO_PIN_INT_FALL_FDET3_Pos 3 /*!< GPIO_PIN_INT FALL: FDET3 Position */
+#define GPIO_PIN_INT_FALL_FDET3_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET3_Pos) /*!< GPIO_PIN_INT FALL: FDET3 Mask */
+#define GPIO_PIN_INT_FALL_FDET4_Pos 4 /*!< GPIO_PIN_INT FALL: FDET4 Position */
+#define GPIO_PIN_INT_FALL_FDET4_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET4_Pos) /*!< GPIO_PIN_INT FALL: FDET4 Mask */
+#define GPIO_PIN_INT_FALL_FDET5_Pos 5 /*!< GPIO_PIN_INT FALL: FDET5 Position */
+#define GPIO_PIN_INT_FALL_FDET5_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET5_Pos) /*!< GPIO_PIN_INT FALL: FDET5 Mask */
+#define GPIO_PIN_INT_FALL_FDET6_Pos 6 /*!< GPIO_PIN_INT FALL: FDET6 Position */
+#define GPIO_PIN_INT_FALL_FDET6_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET6_Pos) /*!< GPIO_PIN_INT FALL: FDET6 Mask */
+#define GPIO_PIN_INT_FALL_FDET7_Pos 7 /*!< GPIO_PIN_INT FALL: FDET7 Position */
+#define GPIO_PIN_INT_FALL_FDET7_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET7_Pos) /*!< GPIO_PIN_INT FALL: FDET7 Mask */
+
+// ------------------------------------ GPIO_PIN_INT_IST ----------------------------------------
+#define GPIO_PIN_INT_IST_PSTAT0_Pos 0 /*!< GPIO_PIN_INT IST: PSTAT0 Position */
+#define GPIO_PIN_INT_IST_PSTAT0_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT0_Pos) /*!< GPIO_PIN_INT IST: PSTAT0 Mask */
+#define GPIO_PIN_INT_IST_PSTAT1_Pos 1 /*!< GPIO_PIN_INT IST: PSTAT1 Position */
+#define GPIO_PIN_INT_IST_PSTAT1_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT1_Pos) /*!< GPIO_PIN_INT IST: PSTAT1 Mask */
+#define GPIO_PIN_INT_IST_PSTAT2_Pos 2 /*!< GPIO_PIN_INT IST: PSTAT2 Position */
+#define GPIO_PIN_INT_IST_PSTAT2_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT2_Pos) /*!< GPIO_PIN_INT IST: PSTAT2 Mask */
+#define GPIO_PIN_INT_IST_PSTAT3_Pos 3 /*!< GPIO_PIN_INT IST: PSTAT3 Position */
+#define GPIO_PIN_INT_IST_PSTAT3_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT3_Pos) /*!< GPIO_PIN_INT IST: PSTAT3 Mask */
+#define GPIO_PIN_INT_IST_PSTAT4_Pos 4 /*!< GPIO_PIN_INT IST: PSTAT4 Position */
+#define GPIO_PIN_INT_IST_PSTAT4_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT4_Pos) /*!< GPIO_PIN_INT IST: PSTAT4 Mask */
+#define GPIO_PIN_INT_IST_PSTAT5_Pos 5 /*!< GPIO_PIN_INT IST: PSTAT5 Position */
+#define GPIO_PIN_INT_IST_PSTAT5_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT5_Pos) /*!< GPIO_PIN_INT IST: PSTAT5 Mask */
+#define GPIO_PIN_INT_IST_PSTAT6_Pos 6 /*!< GPIO_PIN_INT IST: PSTAT6 Position */
+#define GPIO_PIN_INT_IST_PSTAT6_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT6_Pos) /*!< GPIO_PIN_INT IST: PSTAT6 Mask */
+#define GPIO_PIN_INT_IST_PSTAT7_Pos 7 /*!< GPIO_PIN_INT IST: PSTAT7 Position */
+#define GPIO_PIN_INT_IST_PSTAT7_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT7_Pos) /*!< GPIO_PIN_INT IST: PSTAT7 Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_GROUP_INTn Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------- GPIO_GROUP_INTn_CTRL --------------------------------------
+#define GPIO_GROUP_INTn_CTRL_INT_Pos 0 /*!< GPIO_GROUP_INTn CTRL: INT Position */
+#define GPIO_GROUP_INTn_CTRL_INT_Msk (0x01UL << GPIO_GROUP_INTn_CTRL_INT_Pos) /*!< GPIO_GROUP_INTn CTRL: INT Mask */
+#define GPIO_GROUP_INTn_CTRL_COMB_Pos 1 /*!< GPIO_GROUP_INTn CTRL: COMB Position */
+#define GPIO_GROUP_INTn_CTRL_COMB_Msk (0x01UL << GPIO_GROUP_INTn_CTRL_COMB_Pos) /*!< GPIO_GROUP_INTn CTRL: COMB Mask */
+#define GPIO_GROUP_INTn_CTRL_TRIG_Pos 2 /*!< GPIO_GROUP_INTn CTRL: TRIG Position */
+#define GPIO_GROUP_INTn_CTRL_TRIG_Msk (0x01UL << GPIO_GROUP_INTn_CTRL_TRIG_Pos) /*!< GPIO_GROUP_INTn CTRL: TRIG Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_POL0 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL0_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL0: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL0: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL0: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL0: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL0: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL0: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL0: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL0: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL0: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL0: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL0: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL0: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL0: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL0: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL0: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL0: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL0: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL0: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL0: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL0: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL0: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL0: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL0: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL0: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL0: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL0: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL0: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL0: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL0: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL0: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL0: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL0: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL0_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_POL1 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL1_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL1: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL1: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL1: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL1: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL1: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL1: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL1: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL1: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL1: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL1: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL1: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL1: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL1: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL1: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL1: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL1: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL1: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL1: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL1: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL1: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL1: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL1: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL1: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL1: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL1: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL1: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL1: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL1: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL1: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL1: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL1: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL1: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL1_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_POL2 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL2_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL2: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL2: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL2: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL2: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL2: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL2: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL2: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL2: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL2: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL2: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL2: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL2: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL2: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL2: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL2: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL2: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL2: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL2: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL2: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL2: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL2: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL2: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL2: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL2: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL2: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL2: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL2: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL2: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL2: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL2: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL2: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL2: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL2_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_POL3 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL3_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL3: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL3: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL3: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL3: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL3: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL3: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL3: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL3: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL3: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL3: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL3: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL3: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL3: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL3: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL3: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL3: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL3: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL3: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL3: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL3: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL3: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL3: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL3: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL3: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL3: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL3: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL3: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL3: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL3: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL3: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL3: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL3: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL3_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_POL4 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL4_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL4: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL4: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL4: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL4: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL4: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL4: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL4: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL4: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL4: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL4: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL4: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL4: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL4: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL4: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL4: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL4: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL4: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL4: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL4: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL4: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL4: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL4: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL4: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL4: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL4: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL4: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL4: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL4: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL4: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL4: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL4: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL4: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL4_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_POL5 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL5_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL5: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL5: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL5: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL5: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL5: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL5: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL5: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL5: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL5: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL5: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL5: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL5: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL5: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL5: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL5: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL5: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL5: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL5: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL5: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL5: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL5: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL5: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL5: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL5: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL5: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL5: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL5: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL5: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL5: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL5: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL5: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL5: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL5_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_POL6 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL6_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL6: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL6: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL6: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL6: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL6: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL6: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL6: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL6: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL6: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL6: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL6: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL6: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL6: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL6: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL6: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL6: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL6: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL6: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL6: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL6: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL6: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL6: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL6: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL6: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL6: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL6: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL6: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL6: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL6: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL6: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL6: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL6: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL6_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_POL7 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_POL7_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL7: POL_0 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_0 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL7: POL_1 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_1 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL7: POL_2 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_2 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL7: POL_3 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_3 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL7: POL_4 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_4 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL7: POL_5 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_5 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL7: POL_6 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_6 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL7: POL_7 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_7 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL7: POL_8 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_8 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL7: POL_9 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_9 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL7: POL_10 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_10 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL7: POL_11 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_11 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL7: POL_12 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_12 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL7: POL_13 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_13 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL7: POL_14 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_14 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL7: POL_15 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_15 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL7: POL_16 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_16 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL7: POL_17 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_17 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL7: POL_18 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_18 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL7: POL_19 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_19 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL7: POL_20 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_20 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL7: POL_21 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_21 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL7: POL_22 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_22 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL7: POL_23 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_23 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL7: POL_24 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_24 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL7: POL_25 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_25 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL7: POL_26 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_26 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL7: POL_27 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_27 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL7: POL_28 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_28 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL7: POL_29 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_29 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL7: POL_30 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_30 Mask */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL7: POL_31 Position */
+#define GPIO_GROUP_INTn_PORT_POL7_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_ENA0 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_ENA1 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_ENA2 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_ENA3 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_ENA4 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_ENA5 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_ENA6 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INTn_PORT_ENA7 -----------------------------------
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_0 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_0 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_1 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_1 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_2 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_2 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_3 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_3 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_4 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_4 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_5 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_5 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_6 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_6 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_7 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_7 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_8 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_8 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_9 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_9 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_10 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_10 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_11 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_11 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_12 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_12 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_13 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_13 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_14 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_14 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_15 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_15 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_16 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_16 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_17 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_17 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_18 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_18 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_19 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_19 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_20 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_20 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_21 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_21 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_22 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_22 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_23 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_23 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_24 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_24 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_25 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_25 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_26 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_26 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_27 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_27 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_28 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_28 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_29 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_29 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_30 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_30 Mask */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_31 Position */
+#define GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_31 Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_GROUP_INT1 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------- GPIO_GROUP_INT1_CTRL --------------------------------------
+#define GPIO_GROUP_INT1_CTRL_INT_Pos 0 /*!< GPIO_GROUP_INT1 CTRL: INT Position */
+#define GPIO_GROUP_INT1_CTRL_INT_Msk (0x01UL << GPIO_GROUP_INT1_CTRL_INT_Pos) /*!< GPIO_GROUP_INT1 CTRL: INT Mask */
+#define GPIO_GROUP_INT1_CTRL_COMB_Pos 1 /*!< GPIO_GROUP_INT1 CTRL: COMB Position */
+#define GPIO_GROUP_INT1_CTRL_COMB_Msk (0x01UL << GPIO_GROUP_INT1_CTRL_COMB_Pos) /*!< GPIO_GROUP_INT1 CTRL: COMB Mask */
+#define GPIO_GROUP_INT1_CTRL_TRIG_Pos 2 /*!< GPIO_GROUP_INT1 CTRL: TRIG Position */
+#define GPIO_GROUP_INT1_CTRL_TRIG_Msk (0x01UL << GPIO_GROUP_INT1_CTRL_TRIG_Pos) /*!< GPIO_GROUP_INT1 CTRL: TRIG Mask */
+
+// -------------------------------- GPIO_GROUP_INT1_PORT_POL0 -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL0_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL0_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INT1_PORT_POL1 -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL1_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL1_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INT1_PORT_POL2 -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL2_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL2_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INT1_PORT_POL3 -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL3_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL3_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INT1_PORT_POL4 -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL4_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL4_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INT1_PORT_POL5 -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL5_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL5_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INT1_PORT_POL6 -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL6_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL6_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INT1_PORT_POL7 -----------------------------------
+#define GPIO_GROUP_INT1_PORT_POL7_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_0 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_0 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_1 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_1 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_2 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_2 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_3 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_3 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_4 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_4 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_5 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_5 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_6 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_6 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_7 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_7 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_8 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_8 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_9 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_9 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_10 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_10 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_11 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_11 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_12 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_12 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_13 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_13 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_14 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_14 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_15 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_15 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_16 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_16 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_17 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_17 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_18 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_18 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_19 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_19 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_20 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_20 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_21 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_21 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_22 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_22 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_23 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_23 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_24 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_24 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_25 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_25 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_26 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_26 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_27 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_27 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_28 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_28 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_29 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_29 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_30 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_30 Mask */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_31 Position */
+#define GPIO_GROUP_INT1_PORT_POL7_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INT1_PORT_ENA0 -----------------------------------
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_0 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_0 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_1 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_1 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_2 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_2 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_3 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_3 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_4 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_4 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_5 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_5 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_6 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_6 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_7 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_7 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_8 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_8 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_9 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_9 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_10 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_10 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_11 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_11 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_12 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_12 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_13 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_13 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_14 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_14 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_15 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_15 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_16 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_16 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_17 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_17 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_18 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_18 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_19 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_19 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_20 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_20 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_21 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_21 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_22 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_22 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_23 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_23 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_24 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_24 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_25 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_25 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_26 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_26 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_27 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_27 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_28 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_28 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_29 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_29 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_30 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_30 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_31 Position */
+#define GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INT1_PORT_ENA1 -----------------------------------
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_0 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_0 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_1 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_1 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_2 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_2 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_3 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_3 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_4 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_4 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_5 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_5 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_6 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_6 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_7 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_7 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_8 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_8 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_9 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_9 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_10 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_10 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_11 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_11 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_12 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_12 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_13 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_13 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_14 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_14 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_15 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_15 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_16 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_16 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_17 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_17 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_18 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_18 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_19 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_19 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_20 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_20 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_21 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_21 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_22 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_22 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_23 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_23 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_24 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_24 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_25 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_25 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_26 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_26 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_27 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_27 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_28 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_28 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_29 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_29 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_30 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_30 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_31 Position */
+#define GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INT1_PORT_ENA2 -----------------------------------
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_0 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_0 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_1 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_1 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_2 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_2 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_3 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_3 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_4 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_4 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_5 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_5 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_6 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_6 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_7 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_7 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_8 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_8 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_9 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_9 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_10 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_10 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_11 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_11 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_12 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_12 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_13 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_13 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_14 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_14 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_15 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_15 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_16 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_16 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_17 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_17 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_18 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_18 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_19 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_19 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_20 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_20 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_21 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_21 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_22 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_22 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_23 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_23 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_24 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_24 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_25 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_25 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_26 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_26 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_27 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_27 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_28 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_28 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_29 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_29 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_30 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_30 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_31 Position */
+#define GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INT1_PORT_ENA3 -----------------------------------
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_0 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_0 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_1 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_1 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_2 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_2 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_3 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_3 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_4 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_4 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_5 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_5 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_6 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_6 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_7 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_7 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_8 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_8 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_9 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_9 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_10 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_10 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_11 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_11 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_12 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_12 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_13 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_13 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_14 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_14 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_15 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_15 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_16 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_16 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_17 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_17 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_18 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_18 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_19 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_19 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_20 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_20 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_21 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_21 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_22 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_22 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_23 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_23 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_24 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_24 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_25 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_25 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_26 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_26 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_27 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_27 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_28 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_28 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_29 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_29 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_30 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_30 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_31 Position */
+#define GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INT1_PORT_ENA4 -----------------------------------
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_0 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_0 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_1 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_1 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_2 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_2 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_3 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_3 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_4 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_4 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_5 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_5 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_6 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_6 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_7 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_7 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_8 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_8 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_9 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_9 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_10 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_10 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_11 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_11 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_12 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_12 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_13 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_13 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_14 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_14 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_15 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_15 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_16 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_16 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_17 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_17 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_18 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_18 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_19 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_19 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_20 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_20 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_21 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_21 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_22 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_22 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_23 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_23 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_24 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_24 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_25 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_25 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_26 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_26 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_27 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_27 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_28 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_28 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_29 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_29 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_30 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_30 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_31 Position */
+#define GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INT1_PORT_ENA5 -----------------------------------
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_0 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_0 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_1 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_1 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_2 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_2 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_3 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_3 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_4 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_4 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_5 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_5 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_6 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_6 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_7 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_7 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_8 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_8 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_9 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_9 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_10 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_10 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_11 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_11 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_12 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_12 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_13 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_13 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_14 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_14 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_15 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_15 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_16 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_16 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_17 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_17 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_18 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_18 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_19 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_19 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_20 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_20 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_21 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_21 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_22 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_22 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_23 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_23 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_24 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_24 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_25 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_25 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_26 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_26 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_27 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_27 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_28 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_28 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_29 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_29 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_30 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_30 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_31 Position */
+#define GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INT1_PORT_ENA6 -----------------------------------
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_0 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_0 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_1 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_1 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_2 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_2 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_3 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_3 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_4 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_4 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_5 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_5 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_6 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_6 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_7 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_7 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_8 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_8 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_9 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_9 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_10 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_10 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_11 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_11 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_12 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_12 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_13 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_13 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_14 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_14 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_15 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_15 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_16 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_16 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_17 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_17 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_18 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_18 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_19 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_19 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_20 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_20 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_21 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_21 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_22 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_22 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_23 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_23 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_24 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_24 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_25 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_25 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_26 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_26 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_27 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_27 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_28 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_28 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_29 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_29 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_30 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_30 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_31 Position */
+#define GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_31 Mask */
+
+// -------------------------------- GPIO_GROUP_INT1_PORT_ENA7 -----------------------------------
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_0 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_0 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_1 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_1 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_2 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_2 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_3 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_3 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_4 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_4 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_5 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_5 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_6 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_6 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_7 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_7 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_8 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_8 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_9 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_9 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_10 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_10 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_11 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_11 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_12 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_12 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_13 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_13 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_14 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_14 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_15 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_15 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_16 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_16 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_17 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_17 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_18 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_18 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_19 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_19 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_20 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_20 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_21 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_21 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_22 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_22 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_23 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_23 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_24 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_24 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_25 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_25 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_26 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_26 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_27 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_27 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_28 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_28 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_29 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_29 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_30 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_30 Mask */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_31 Position */
+#define GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_31 Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- MCPWM Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------- MCPWM_CON -------------------------------------------
+#define MCPWM_CON_RUN0_Pos 0 /*!< MCPWM CON: RUN0 Position */
+#define MCPWM_CON_RUN0_Msk (0x01UL << MCPWM_CON_RUN0_Pos) /*!< MCPWM CON: RUN0 Mask */
+#define MCPWM_CON_CENTER0_Pos 1 /*!< MCPWM CON: CENTER0 Position */
+#define MCPWM_CON_CENTER0_Msk (0x01UL << MCPWM_CON_CENTER0_Pos) /*!< MCPWM CON: CENTER0 Mask */
+#define MCPWM_CON_POLA0_Pos 2 /*!< MCPWM CON: POLA0 Position */
+#define MCPWM_CON_POLA0_Msk (0x01UL << MCPWM_CON_POLA0_Pos) /*!< MCPWM CON: POLA0 Mask */
+#define MCPWM_CON_DTE0_Pos 3 /*!< MCPWM CON: DTE0 Position */
+#define MCPWM_CON_DTE0_Msk (0x01UL << MCPWM_CON_DTE0_Pos) /*!< MCPWM CON: DTE0 Mask */
+#define MCPWM_CON_DISUP0_Pos 4 /*!< MCPWM CON: DISUP0 Position */
+#define MCPWM_CON_DISUP0_Msk (0x01UL << MCPWM_CON_DISUP0_Pos) /*!< MCPWM CON: DISUP0 Mask */
+#define MCPWM_CON_RUN1_Pos 8 /*!< MCPWM CON: RUN1 Position */
+#define MCPWM_CON_RUN1_Msk (0x01UL << MCPWM_CON_RUN1_Pos) /*!< MCPWM CON: RUN1 Mask */
+#define MCPWM_CON_CENTER1_Pos 9 /*!< MCPWM CON: CENTER1 Position */
+#define MCPWM_CON_CENTER1_Msk (0x01UL << MCPWM_CON_CENTER1_Pos) /*!< MCPWM CON: CENTER1 Mask */
+#define MCPWM_CON_POLA1_Pos 10 /*!< MCPWM CON: POLA1 Position */
+#define MCPWM_CON_POLA1_Msk (0x01UL << MCPWM_CON_POLA1_Pos) /*!< MCPWM CON: POLA1 Mask */
+#define MCPWM_CON_DTE1_Pos 11 /*!< MCPWM CON: DTE1 Position */
+#define MCPWM_CON_DTE1_Msk (0x01UL << MCPWM_CON_DTE1_Pos) /*!< MCPWM CON: DTE1 Mask */
+#define MCPWM_CON_DISUP1_Pos 12 /*!< MCPWM CON: DISUP1 Position */
+#define MCPWM_CON_DISUP1_Msk (0x01UL << MCPWM_CON_DISUP1_Pos) /*!< MCPWM CON: DISUP1 Mask */
+#define MCPWM_CON_RUN2_Pos 16 /*!< MCPWM CON: RUN2 Position */
+#define MCPWM_CON_RUN2_Msk (0x01UL << MCPWM_CON_RUN2_Pos) /*!< MCPWM CON: RUN2 Mask */
+#define MCPWM_CON_CENTER2_Pos 17 /*!< MCPWM CON: CENTER2 Position */
+#define MCPWM_CON_CENTER2_Msk (0x01UL << MCPWM_CON_CENTER2_Pos) /*!< MCPWM CON: CENTER2 Mask */
+#define MCPWM_CON_POLA2_Pos 18 /*!< MCPWM CON: POLA2 Position */
+#define MCPWM_CON_POLA2_Msk (0x01UL << MCPWM_CON_POLA2_Pos) /*!< MCPWM CON: POLA2 Mask */
+#define MCPWM_CON_DTE2_Pos 19 /*!< MCPWM CON: DTE2 Position */
+#define MCPWM_CON_DTE2_Msk (0x01UL << MCPWM_CON_DTE2_Pos) /*!< MCPWM CON: DTE2 Mask */
+#define MCPWM_CON_DISUP2_Pos 20 /*!< MCPWM CON: DISUP2 Position */
+#define MCPWM_CON_DISUP2_Msk (0x01UL << MCPWM_CON_DISUP2_Pos) /*!< MCPWM CON: DISUP2 Mask */
+#define MCPWM_CON_INVBDC_Pos 29 /*!< MCPWM CON: INVBDC Position */
+#define MCPWM_CON_INVBDC_Msk (0x01UL << MCPWM_CON_INVBDC_Pos) /*!< MCPWM CON: INVBDC Mask */
+#define MCPWM_CON_ACMODE_Pos 30 /*!< MCPWM CON: ACMODE Position */
+#define MCPWM_CON_ACMODE_Msk (0x01UL << MCPWM_CON_ACMODE_Pos) /*!< MCPWM CON: ACMODE Mask */
+#define MCPWM_CON_DCMODE_Pos 31 /*!< MCPWM CON: DCMODE Position */
+#define MCPWM_CON_DCMODE_Msk (0x01UL << MCPWM_CON_DCMODE_Pos) /*!< MCPWM CON: DCMODE Mask */
+
+// -------------------------------------- MCPWM_CON_SET -----------------------------------------
+#define MCPWM_CON_SET_RUN0_SET_Pos 0 /*!< MCPWM CON_SET: RUN0_SET Position */
+#define MCPWM_CON_SET_RUN0_SET_Msk (0x01UL << MCPWM_CON_SET_RUN0_SET_Pos) /*!< MCPWM CON_SET: RUN0_SET Mask */
+#define MCPWM_CON_SET_CENTER0_SET_Pos 1 /*!< MCPWM CON_SET: CENTER0_SET Position */
+#define MCPWM_CON_SET_CENTER0_SET_Msk (0x01UL << MCPWM_CON_SET_CENTER0_SET_Pos) /*!< MCPWM CON_SET: CENTER0_SET Mask */
+#define MCPWM_CON_SET_POLA0_SET_Pos 2 /*!< MCPWM CON_SET: POLA0_SET Position */
+#define MCPWM_CON_SET_POLA0_SET_Msk (0x01UL << MCPWM_CON_SET_POLA0_SET_Pos) /*!< MCPWM CON_SET: POLA0_SET Mask */
+#define MCPWM_CON_SET_DTE0_SET_Pos 3 /*!< MCPWM CON_SET: DTE0_SET Position */
+#define MCPWM_CON_SET_DTE0_SET_Msk (0x01UL << MCPWM_CON_SET_DTE0_SET_Pos) /*!< MCPWM CON_SET: DTE0_SET Mask */
+#define MCPWM_CON_SET_DISUP0_SET_Pos 4 /*!< MCPWM CON_SET: DISUP0_SET Position */
+#define MCPWM_CON_SET_DISUP0_SET_Msk (0x01UL << MCPWM_CON_SET_DISUP0_SET_Pos) /*!< MCPWM CON_SET: DISUP0_SET Mask */
+#define MCPWM_CON_SET_RUN1_SET_Pos 8 /*!< MCPWM CON_SET: RUN1_SET Position */
+#define MCPWM_CON_SET_RUN1_SET_Msk (0x01UL << MCPWM_CON_SET_RUN1_SET_Pos) /*!< MCPWM CON_SET: RUN1_SET Mask */
+#define MCPWM_CON_SET_CENTER1_SET_Pos 9 /*!< MCPWM CON_SET: CENTER1_SET Position */
+#define MCPWM_CON_SET_CENTER1_SET_Msk (0x01UL << MCPWM_CON_SET_CENTER1_SET_Pos) /*!< MCPWM CON_SET: CENTER1_SET Mask */
+#define MCPWM_CON_SET_POLA1_SET_Pos 10 /*!< MCPWM CON_SET: POLA1_SET Position */
+#define MCPWM_CON_SET_POLA1_SET_Msk (0x01UL << MCPWM_CON_SET_POLA1_SET_Pos) /*!< MCPWM CON_SET: POLA1_SET Mask */
+#define MCPWM_CON_SET_DTE1_SET_Pos 11 /*!< MCPWM CON_SET: DTE1_SET Position */
+#define MCPWM_CON_SET_DTE1_SET_Msk (0x01UL << MCPWM_CON_SET_DTE1_SET_Pos) /*!< MCPWM CON_SET: DTE1_SET Mask */
+#define MCPWM_CON_SET_DISUP1_SET_Pos 12 /*!< MCPWM CON_SET: DISUP1_SET Position */
+#define MCPWM_CON_SET_DISUP1_SET_Msk (0x01UL << MCPWM_CON_SET_DISUP1_SET_Pos) /*!< MCPWM CON_SET: DISUP1_SET Mask */
+#define MCPWM_CON_SET_RUN2_SET_Pos 16 /*!< MCPWM CON_SET: RUN2_SET Position */
+#define MCPWM_CON_SET_RUN2_SET_Msk (0x01UL << MCPWM_CON_SET_RUN2_SET_Pos) /*!< MCPWM CON_SET: RUN2_SET Mask */
+#define MCPWM_CON_SET_CENTER2_SET_Pos 17 /*!< MCPWM CON_SET: CENTER2_SET Position */
+#define MCPWM_CON_SET_CENTER2_SET_Msk (0x01UL << MCPWM_CON_SET_CENTER2_SET_Pos) /*!< MCPWM CON_SET: CENTER2_SET Mask */
+#define MCPWM_CON_SET_POLA2_SET_Pos 18 /*!< MCPWM CON_SET: POLA2_SET Position */
+#define MCPWM_CON_SET_POLA2_SET_Msk (0x01UL << MCPWM_CON_SET_POLA2_SET_Pos) /*!< MCPWM CON_SET: POLA2_SET Mask */
+#define MCPWM_CON_SET_DTE2_SET_Pos 19 /*!< MCPWM CON_SET: DTE2_SET Position */
+#define MCPWM_CON_SET_DTE2_SET_Msk (0x01UL << MCPWM_CON_SET_DTE2_SET_Pos) /*!< MCPWM CON_SET: DTE2_SET Mask */
+#define MCPWM_CON_SET_DISUP2_SET_Pos 20 /*!< MCPWM CON_SET: DISUP2_SET Position */
+#define MCPWM_CON_SET_DISUP2_SET_Msk (0x01UL << MCPWM_CON_SET_DISUP2_SET_Pos) /*!< MCPWM CON_SET: DISUP2_SET Mask */
+#define MCPWM_CON_SET_INVBDC_SET_Pos 29 /*!< MCPWM CON_SET: INVBDC_SET Position */
+#define MCPWM_CON_SET_INVBDC_SET_Msk (0x01UL << MCPWM_CON_SET_INVBDC_SET_Pos) /*!< MCPWM CON_SET: INVBDC_SET Mask */
+#define MCPWM_CON_SET_ACMODE_SET_Pos 30 /*!< MCPWM CON_SET: ACMODE_SET Position */
+#define MCPWM_CON_SET_ACMODE_SET_Msk (0x01UL << MCPWM_CON_SET_ACMODE_SET_Pos) /*!< MCPWM CON_SET: ACMODE_SET Mask */
+#define MCPWM_CON_SET_DCMODE_SET_Pos 31 /*!< MCPWM CON_SET: DCMODE_SET Position */
+#define MCPWM_CON_SET_DCMODE_SET_Msk (0x01UL << MCPWM_CON_SET_DCMODE_SET_Pos) /*!< MCPWM CON_SET: DCMODE_SET Mask */
+
+// -------------------------------------- MCPWM_CON_CLR -----------------------------------------
+#define MCPWM_CON_CLR_RUN0_CLR_Pos 0 /*!< MCPWM CON_CLR: RUN0_CLR Position */
+#define MCPWM_CON_CLR_RUN0_CLR_Msk (0x01UL << MCPWM_CON_CLR_RUN0_CLR_Pos) /*!< MCPWM CON_CLR: RUN0_CLR Mask */
+#define MCPWM_CON_CLR_CENTER0_CLR_Pos 1 /*!< MCPWM CON_CLR: CENTER0_CLR Position */
+#define MCPWM_CON_CLR_CENTER0_CLR_Msk (0x01UL << MCPWM_CON_CLR_CENTER0_CLR_Pos) /*!< MCPWM CON_CLR: CENTER0_CLR Mask */
+#define MCPWM_CON_CLR_POLA0_CLR_Pos 2 /*!< MCPWM CON_CLR: POLA0_CLR Position */
+#define MCPWM_CON_CLR_POLA0_CLR_Msk (0x01UL << MCPWM_CON_CLR_POLA0_CLR_Pos) /*!< MCPWM CON_CLR: POLA0_CLR Mask */
+#define MCPWM_CON_CLR_DTE0_CLR_Pos 3 /*!< MCPWM CON_CLR: DTE0_CLR Position */
+#define MCPWM_CON_CLR_DTE0_CLR_Msk (0x01UL << MCPWM_CON_CLR_DTE0_CLR_Pos) /*!< MCPWM CON_CLR: DTE0_CLR Mask */
+#define MCPWM_CON_CLR_DISUP0_CLR_Pos 4 /*!< MCPWM CON_CLR: DISUP0_CLR Position */
+#define MCPWM_CON_CLR_DISUP0_CLR_Msk (0x01UL << MCPWM_CON_CLR_DISUP0_CLR_Pos) /*!< MCPWM CON_CLR: DISUP0_CLR Mask */
+#define MCPWM_CON_CLR_RUN1_CLR_Pos 8 /*!< MCPWM CON_CLR: RUN1_CLR Position */
+#define MCPWM_CON_CLR_RUN1_CLR_Msk (0x01UL << MCPWM_CON_CLR_RUN1_CLR_Pos) /*!< MCPWM CON_CLR: RUN1_CLR Mask */
+#define MCPWM_CON_CLR_CENTER1_CLR_Pos 9 /*!< MCPWM CON_CLR: CENTER1_CLR Position */
+#define MCPWM_CON_CLR_CENTER1_CLR_Msk (0x01UL << MCPWM_CON_CLR_CENTER1_CLR_Pos) /*!< MCPWM CON_CLR: CENTER1_CLR Mask */
+#define MCPWM_CON_CLR_POLA1_CLR_Pos 10 /*!< MCPWM CON_CLR: POLA1_CLR Position */
+#define MCPWM_CON_CLR_POLA1_CLR_Msk (0x01UL << MCPWM_CON_CLR_POLA1_CLR_Pos) /*!< MCPWM CON_CLR: POLA1_CLR Mask */
+#define MCPWM_CON_CLR_DTE1_CLR_Pos 11 /*!< MCPWM CON_CLR: DTE1_CLR Position */
+#define MCPWM_CON_CLR_DTE1_CLR_Msk (0x01UL << MCPWM_CON_CLR_DTE1_CLR_Pos) /*!< MCPWM CON_CLR: DTE1_CLR Mask */
+#define MCPWM_CON_CLR_DISUP1_CLR_Pos 12 /*!< MCPWM CON_CLR: DISUP1_CLR Position */
+#define MCPWM_CON_CLR_DISUP1_CLR_Msk (0x01UL << MCPWM_CON_CLR_DISUP1_CLR_Pos) /*!< MCPWM CON_CLR: DISUP1_CLR Mask */
+#define MCPWM_CON_CLR_RUN2_CLR_Pos 16 /*!< MCPWM CON_CLR: RUN2_CLR Position */
+#define MCPWM_CON_CLR_RUN2_CLR_Msk (0x01UL << MCPWM_CON_CLR_RUN2_CLR_Pos) /*!< MCPWM CON_CLR: RUN2_CLR Mask */
+#define MCPWM_CON_CLR_CENTER2_CLR_Pos 17 /*!< MCPWM CON_CLR: CENTER2_CLR Position */
+#define MCPWM_CON_CLR_CENTER2_CLR_Msk (0x01UL << MCPWM_CON_CLR_CENTER2_CLR_Pos) /*!< MCPWM CON_CLR: CENTER2_CLR Mask */
+#define MCPWM_CON_CLR_POLA2_CLR_Pos 18 /*!< MCPWM CON_CLR: POLA2_CLR Position */
+#define MCPWM_CON_CLR_POLA2_CLR_Msk (0x01UL << MCPWM_CON_CLR_POLA2_CLR_Pos) /*!< MCPWM CON_CLR: POLA2_CLR Mask */
+#define MCPWM_CON_CLR_DTE2_CLR_Pos 19 /*!< MCPWM CON_CLR: DTE2_CLR Position */
+#define MCPWM_CON_CLR_DTE2_CLR_Msk (0x01UL << MCPWM_CON_CLR_DTE2_CLR_Pos) /*!< MCPWM CON_CLR: DTE2_CLR Mask */
+#define MCPWM_CON_CLR_DISUP2_CLR_Pos 20 /*!< MCPWM CON_CLR: DISUP2_CLR Position */
+#define MCPWM_CON_CLR_DISUP2_CLR_Msk (0x01UL << MCPWM_CON_CLR_DISUP2_CLR_Pos) /*!< MCPWM CON_CLR: DISUP2_CLR Mask */
+#define MCPWM_CON_CLR_INVBDC_CLR_Pos 29 /*!< MCPWM CON_CLR: INVBDC_CLR Position */
+#define MCPWM_CON_CLR_INVBDC_CLR_Msk (0x01UL << MCPWM_CON_CLR_INVBDC_CLR_Pos) /*!< MCPWM CON_CLR: INVBDC_CLR Mask */
+#define MCPWM_CON_CLR_ACMOD_CLR_Pos 30 /*!< MCPWM CON_CLR: ACMOD_CLR Position */
+#define MCPWM_CON_CLR_ACMOD_CLR_Msk (0x01UL << MCPWM_CON_CLR_ACMOD_CLR_Pos) /*!< MCPWM CON_CLR: ACMOD_CLR Mask */
+#define MCPWM_CON_CLR_DCMODE_CLR_Pos 31 /*!< MCPWM CON_CLR: DCMODE_CLR Position */
+#define MCPWM_CON_CLR_DCMODE_CLR_Msk (0x01UL << MCPWM_CON_CLR_DCMODE_CLR_Pos) /*!< MCPWM CON_CLR: DCMODE_CLR Mask */
+
+// -------------------------------------- MCPWM_CAPCON ------------------------------------------
+#define MCPWM_CAPCON_CAP0MCI0_RE_Pos 0 /*!< MCPWM CAPCON: CAP0MCI0_RE Position */
+#define MCPWM_CAPCON_CAP0MCI0_RE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI0_RE_Pos) /*!< MCPWM CAPCON: CAP0MCI0_RE Mask */
+#define MCPWM_CAPCON_CAP0MCI0_FE_Pos 1 /*!< MCPWM CAPCON: CAP0MCI0_FE Position */
+#define MCPWM_CAPCON_CAP0MCI0_FE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI0_FE_Pos) /*!< MCPWM CAPCON: CAP0MCI0_FE Mask */
+#define MCPWM_CAPCON_CAP0MCI1_RE_Pos 2 /*!< MCPWM CAPCON: CAP0MCI1_RE Position */
+#define MCPWM_CAPCON_CAP0MCI1_RE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI1_RE_Pos) /*!< MCPWM CAPCON: CAP0MCI1_RE Mask */
+#define MCPWM_CAPCON_CAP0MCI1_FE_Pos 3 /*!< MCPWM CAPCON: CAP0MCI1_FE Position */
+#define MCPWM_CAPCON_CAP0MCI1_FE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI1_FE_Pos) /*!< MCPWM CAPCON: CAP0MCI1_FE Mask */
+#define MCPWM_CAPCON_CAP0MCI2_RE_Pos 4 /*!< MCPWM CAPCON: CAP0MCI2_RE Position */
+#define MCPWM_CAPCON_CAP0MCI2_RE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI2_RE_Pos) /*!< MCPWM CAPCON: CAP0MCI2_RE Mask */
+#define MCPWM_CAPCON_CAP0MCI2_FE_Pos 5 /*!< MCPWM CAPCON: CAP0MCI2_FE Position */
+#define MCPWM_CAPCON_CAP0MCI2_FE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI2_FE_Pos) /*!< MCPWM CAPCON: CAP0MCI2_FE Mask */
+#define MCPWM_CAPCON_CAP1MCI0_RE_Pos 6 /*!< MCPWM CAPCON: CAP1MCI0_RE Position */
+#define MCPWM_CAPCON_CAP1MCI0_RE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI0_RE_Pos) /*!< MCPWM CAPCON: CAP1MCI0_RE Mask */
+#define MCPWM_CAPCON_CAP1MCI0_FE_Pos 7 /*!< MCPWM CAPCON: CAP1MCI0_FE Position */
+#define MCPWM_CAPCON_CAP1MCI0_FE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI0_FE_Pos) /*!< MCPWM CAPCON: CAP1MCI0_FE Mask */
+#define MCPWM_CAPCON_CAP1MCI1_RE_Pos 8 /*!< MCPWM CAPCON: CAP1MCI1_RE Position */
+#define MCPWM_CAPCON_CAP1MCI1_RE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI1_RE_Pos) /*!< MCPWM CAPCON: CAP1MCI1_RE Mask */
+#define MCPWM_CAPCON_CAP1MCI1_FE_Pos 9 /*!< MCPWM CAPCON: CAP1MCI1_FE Position */
+#define MCPWM_CAPCON_CAP1MCI1_FE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI1_FE_Pos) /*!< MCPWM CAPCON: CAP1MCI1_FE Mask */
+#define MCPWM_CAPCON_CAP1MCI2_RE_Pos 10 /*!< MCPWM CAPCON: CAP1MCI2_RE Position */
+#define MCPWM_CAPCON_CAP1MCI2_RE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI2_RE_Pos) /*!< MCPWM CAPCON: CAP1MCI2_RE Mask */
+#define MCPWM_CAPCON_CAP1MCI2_FE_Pos 11 /*!< MCPWM CAPCON: CAP1MCI2_FE Position */
+#define MCPWM_CAPCON_CAP1MCI2_FE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI2_FE_Pos) /*!< MCPWM CAPCON: CAP1MCI2_FE Mask */
+#define MCPWM_CAPCON_CAP2MCI0_RE_Pos 12 /*!< MCPWM CAPCON: CAP2MCI0_RE Position */
+#define MCPWM_CAPCON_CAP2MCI0_RE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI0_RE_Pos) /*!< MCPWM CAPCON: CAP2MCI0_RE Mask */
+#define MCPWM_CAPCON_CAP2MCI0_FE_Pos 13 /*!< MCPWM CAPCON: CAP2MCI0_FE Position */
+#define MCPWM_CAPCON_CAP2MCI0_FE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI0_FE_Pos) /*!< MCPWM CAPCON: CAP2MCI0_FE Mask */
+#define MCPWM_CAPCON_CAP2MCI1_RE_Pos 14 /*!< MCPWM CAPCON: CAP2MCI1_RE Position */
+#define MCPWM_CAPCON_CAP2MCI1_RE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI1_RE_Pos) /*!< MCPWM CAPCON: CAP2MCI1_RE Mask */
+#define MCPWM_CAPCON_CAP2MCI1_FE_Pos 15 /*!< MCPWM CAPCON: CAP2MCI1_FE Position */
+#define MCPWM_CAPCON_CAP2MCI1_FE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI1_FE_Pos) /*!< MCPWM CAPCON: CAP2MCI1_FE Mask */
+#define MCPWM_CAPCON_CAP2MCI2_RE_Pos 16 /*!< MCPWM CAPCON: CAP2MCI2_RE Position */
+#define MCPWM_CAPCON_CAP2MCI2_RE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI2_RE_Pos) /*!< MCPWM CAPCON: CAP2MCI2_RE Mask */
+#define MCPWM_CAPCON_CAP2MCI2_FE_Pos 17 /*!< MCPWM CAPCON: CAP2MCI2_FE Position */
+#define MCPWM_CAPCON_CAP2MCI2_FE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI2_FE_Pos) /*!< MCPWM CAPCON: CAP2MCI2_FE Mask */
+#define MCPWM_CAPCON_RT0_Pos 18 /*!< MCPWM CAPCON: RT0 Position */
+#define MCPWM_CAPCON_RT0_Msk (0x01UL << MCPWM_CAPCON_RT0_Pos) /*!< MCPWM CAPCON: RT0 Mask */
+#define MCPWM_CAPCON_RT1_Pos 19 /*!< MCPWM CAPCON: RT1 Position */
+#define MCPWM_CAPCON_RT1_Msk (0x01UL << MCPWM_CAPCON_RT1_Pos) /*!< MCPWM CAPCON: RT1 Mask */
+#define MCPWM_CAPCON_RT2_Pos 20 /*!< MCPWM CAPCON: RT2 Position */
+#define MCPWM_CAPCON_RT2_Msk (0x01UL << MCPWM_CAPCON_RT2_Pos) /*!< MCPWM CAPCON: RT2 Mask */
+#define MCPWM_CAPCON_HNFCAP0_Pos 21 /*!< MCPWM CAPCON: HNFCAP0 Position */
+#define MCPWM_CAPCON_HNFCAP0_Msk (0x01UL << MCPWM_CAPCON_HNFCAP0_Pos) /*!< MCPWM CAPCON: HNFCAP0 Mask */
+#define MCPWM_CAPCON_HNFCAP1_Pos 22 /*!< MCPWM CAPCON: HNFCAP1 Position */
+#define MCPWM_CAPCON_HNFCAP1_Msk (0x01UL << MCPWM_CAPCON_HNFCAP1_Pos) /*!< MCPWM CAPCON: HNFCAP1 Mask */
+#define MCPWM_CAPCON_HNFCAP2_Pos 23 /*!< MCPWM CAPCON: HNFCAP2 Position */
+#define MCPWM_CAPCON_HNFCAP2_Msk (0x01UL << MCPWM_CAPCON_HNFCAP2_Pos) /*!< MCPWM CAPCON: HNFCAP2 Mask */
+
+// ------------------------------------ MCPWM_CAPCON_SET ----------------------------------------
+#define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Pos 0 /*!< MCPWM CAPCON_SET: CAP0MCI0_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI0_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Pos 1 /*!< MCPWM CAPCON_SET: CAP0MCI0_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI0_FE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Pos 2 /*!< MCPWM CAPCON_SET: CAP0MCI1_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI1_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Pos 3 /*!< MCPWM CAPCON_SET: CAP0MCI1_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI1_FE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Pos 4 /*!< MCPWM CAPCON_SET: CAP0MCI2_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI2_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Pos 5 /*!< MCPWM CAPCON_SET: CAP0MCI2_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI2_FE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Pos 6 /*!< MCPWM CAPCON_SET: CAP1MCI0_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI0_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Pos 7 /*!< MCPWM CAPCON_SET: CAP1MCI0_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI0_FE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Pos 8 /*!< MCPWM CAPCON_SET: CAP1MCI1_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI1_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Pos 9 /*!< MCPWM CAPCON_SET: CAP1MCI1_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI1_FE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Pos 10 /*!< MCPWM CAPCON_SET: CAP1MCI2_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI2_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Pos 11 /*!< MCPWM CAPCON_SET: CAP1MCI2_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI2_FE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Pos 12 /*!< MCPWM CAPCON_SET: CAP2MCI0_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI0_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Pos 13 /*!< MCPWM CAPCON_SET: CAP2MCI0_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI0_FE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Pos 14 /*!< MCPWM CAPCON_SET: CAP2MCI1_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI1_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Pos 15 /*!< MCPWM CAPCON_SET: CAP2MCI1_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI1_FE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Pos 16 /*!< MCPWM CAPCON_SET: CAP2MCI2_RE_SET Position */
+#define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI2_RE_SET Mask */
+#define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Pos 17 /*!< MCPWM CAPCON_SET: CAP2MCI2_FE_SET Position */
+#define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI2_FE_SET Mask */
+#define MCPWM_CAPCON_SET_RT0_SET_Pos 18 /*!< MCPWM CAPCON_SET: RT0_SET Position */
+#define MCPWM_CAPCON_SET_RT0_SET_Msk (0x01UL << MCPWM_CAPCON_SET_RT0_SET_Pos) /*!< MCPWM CAPCON_SET: RT0_SET Mask */
+#define MCPWM_CAPCON_SET_RT1_SET_Pos 19 /*!< MCPWM CAPCON_SET: RT1_SET Position */
+#define MCPWM_CAPCON_SET_RT1_SET_Msk (0x01UL << MCPWM_CAPCON_SET_RT1_SET_Pos) /*!< MCPWM CAPCON_SET: RT1_SET Mask */
+#define MCPWM_CAPCON_SET_RT2_SET_Pos 20 /*!< MCPWM CAPCON_SET: RT2_SET Position */
+#define MCPWM_CAPCON_SET_RT2_SET_Msk (0x01UL << MCPWM_CAPCON_SET_RT2_SET_Pos) /*!< MCPWM CAPCON_SET: RT2_SET Mask */
+#define MCPWM_CAPCON_SET_HNFCAP0_SET_Pos 21 /*!< MCPWM CAPCON_SET: HNFCAP0_SET Position */
+#define MCPWM_CAPCON_SET_HNFCAP0_SET_Msk (0x01UL << MCPWM_CAPCON_SET_HNFCAP0_SET_Pos) /*!< MCPWM CAPCON_SET: HNFCAP0_SET Mask */
+#define MCPWM_CAPCON_SET_HNFCAP1_SET_Pos 22 /*!< MCPWM CAPCON_SET: HNFCAP1_SET Position */
+#define MCPWM_CAPCON_SET_HNFCAP1_SET_Msk (0x01UL << MCPWM_CAPCON_SET_HNFCAP1_SET_Pos) /*!< MCPWM CAPCON_SET: HNFCAP1_SET Mask */
+#define MCPWM_CAPCON_SET_HNFCAP2_SET_Pos 23 /*!< MCPWM CAPCON_SET: HNFCAP2_SET Position */
+#define MCPWM_CAPCON_SET_HNFCAP2_SET_Msk (0x01UL << MCPWM_CAPCON_SET_HNFCAP2_SET_Pos) /*!< MCPWM CAPCON_SET: HNFCAP2_SET Mask */
+
+// ------------------------------------ MCPWM_CAPCON_CLR ----------------------------------------
+#define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Pos 0 /*!< MCPWM CAPCON_CLR: CAP0MCI0_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI0_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Pos 1 /*!< MCPWM CAPCON_CLR: CAP0MCI0_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI0_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Pos 2 /*!< MCPWM CAPCON_CLR: CAP0MCI1_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI1_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Pos 3 /*!< MCPWM CAPCON_CLR: CAP0MCI1_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI1_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Pos 4 /*!< MCPWM CAPCON_CLR: CAP0MCI2_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI2_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Pos 5 /*!< MCPWM CAPCON_CLR: CAP0MCI2_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI2_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Pos 6 /*!< MCPWM CAPCON_CLR: CAP1MCI0_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI0_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Pos 7 /*!< MCPWM CAPCON_CLR: CAP1MCI0_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI0_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Pos 8 /*!< MCPWM CAPCON_CLR: CAP1MCI1_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI1_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Pos 9 /*!< MCPWM CAPCON_CLR: CAP1MCI1_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI1_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Pos 10 /*!< MCPWM CAPCON_CLR: CAP1MCI2_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI2_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Pos 11 /*!< MCPWM CAPCON_CLR: CAP1MCI2_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI2_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Pos 12 /*!< MCPWM CAPCON_CLR: CAP2MCI0_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI0_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Pos 13 /*!< MCPWM CAPCON_CLR: CAP2MCI0_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI0_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Pos 14 /*!< MCPWM CAPCON_CLR: CAP2MCI1_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI1_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Pos 15 /*!< MCPWM CAPCON_CLR: CAP2MCI1_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI1_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Pos 16 /*!< MCPWM CAPCON_CLR: CAP2MCI2_RE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI2_RE_CLR Mask */
+#define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Pos 17 /*!< MCPWM CAPCON_CLR: CAP2MCI2_FE_CLR Position */
+#define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI2_FE_CLR Mask */
+#define MCPWM_CAPCON_CLR_RT0_CLR_Pos 18 /*!< MCPWM CAPCON_CLR: RT0_CLR Position */
+#define MCPWM_CAPCON_CLR_RT0_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_RT0_CLR_Pos) /*!< MCPWM CAPCON_CLR: RT0_CLR Mask */
+#define MCPWM_CAPCON_CLR_RT1_CLR_Pos 19 /*!< MCPWM CAPCON_CLR: RT1_CLR Position */
+#define MCPWM_CAPCON_CLR_RT1_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_RT1_CLR_Pos) /*!< MCPWM CAPCON_CLR: RT1_CLR Mask */
+#define MCPWM_CAPCON_CLR_RT2_CLR_Pos 20 /*!< MCPWM CAPCON_CLR: RT2_CLR Position */
+#define MCPWM_CAPCON_CLR_RT2_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_RT2_CLR_Pos) /*!< MCPWM CAPCON_CLR: RT2_CLR Mask */
+#define MCPWM_CAPCON_CLR_HNFCAP0_CLR_Pos 21 /*!< MCPWM CAPCON_CLR: HNFCAP0_CLR Position */
+#define MCPWM_CAPCON_CLR_HNFCAP0_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_HNFCAP0_CLR_Pos) /*!< MCPWM CAPCON_CLR: HNFCAP0_CLR Mask */
+#define MCPWM_CAPCON_CLR_HNFCAP1_CLR_Pos 22 /*!< MCPWM CAPCON_CLR: HNFCAP1_CLR Position */
+#define MCPWM_CAPCON_CLR_HNFCAP1_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_HNFCAP1_CLR_Pos) /*!< MCPWM CAPCON_CLR: HNFCAP1_CLR Mask */
+#define MCPWM_CAPCON_CLR_HNFCAP2_CLR_Pos 23 /*!< MCPWM CAPCON_CLR: HNFCAP2_CLR Position */
+#define MCPWM_CAPCON_CLR_HNFCAP2_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_HNFCAP2_CLR_Pos) /*!< MCPWM CAPCON_CLR: HNFCAP2_CLR Mask */
+
+// ---------------------------------------- MCPWM_TC0 -------------------------------------------
+#define MCPWM_TC0_MCTC_Pos 0 /*!< MCPWM TC0: MCTC Position */
+#define MCPWM_TC0_MCTC_Msk (0xffffffffUL << MCPWM_TC0_MCTC_Pos) /*!< MCPWM TC0: MCTC Mask */
+
+// ---------------------------------------- MCPWM_TC1 -------------------------------------------
+#define MCPWM_TC1_MCTC_Pos 0 /*!< MCPWM TC1: MCTC Position */
+#define MCPWM_TC1_MCTC_Msk (0xffffffffUL << MCPWM_TC1_MCTC_Pos) /*!< MCPWM TC1: MCTC Mask */
+
+// ---------------------------------------- MCPWM_TC2 -------------------------------------------
+#define MCPWM_TC2_MCTC_Pos 0 /*!< MCPWM TC2: MCTC Position */
+#define MCPWM_TC2_MCTC_Msk (0xffffffffUL << MCPWM_TC2_MCTC_Pos) /*!< MCPWM TC2: MCTC Mask */
+
+// --------------------------------------- MCPWM_LIM0 -------------------------------------------
+#define MCPWM_LIM0_MCLIM_Pos 0 /*!< MCPWM LIM0: MCLIM Position */
+#define MCPWM_LIM0_MCLIM_Msk (0xffffffffUL << MCPWM_LIM0_MCLIM_Pos) /*!< MCPWM LIM0: MCLIM Mask */
+
+// --------------------------------------- MCPWM_LIM1 -------------------------------------------
+#define MCPWM_LIM1_MCLIM_Pos 0 /*!< MCPWM LIM1: MCLIM Position */
+#define MCPWM_LIM1_MCLIM_Msk (0xffffffffUL << MCPWM_LIM1_MCLIM_Pos) /*!< MCPWM LIM1: MCLIM Mask */
+
+// --------------------------------------- MCPWM_LIM2 -------------------------------------------
+#define MCPWM_LIM2_MCLIM_Pos 0 /*!< MCPWM LIM2: MCLIM Position */
+#define MCPWM_LIM2_MCLIM_Msk (0xffffffffUL << MCPWM_LIM2_MCLIM_Pos) /*!< MCPWM LIM2: MCLIM Mask */
+
+// --------------------------------------- MCPWM_MAT0 -------------------------------------------
+#define MCPWM_MAT0_MCMAT_Pos 0 /*!< MCPWM MAT0: MCMAT Position */
+#define MCPWM_MAT0_MCMAT_Msk (0xffffffffUL << MCPWM_MAT0_MCMAT_Pos) /*!< MCPWM MAT0: MCMAT Mask */
+
+// --------------------------------------- MCPWM_MAT1 -------------------------------------------
+#define MCPWM_MAT1_MCMAT_Pos 0 /*!< MCPWM MAT1: MCMAT Position */
+#define MCPWM_MAT1_MCMAT_Msk (0xffffffffUL << MCPWM_MAT1_MCMAT_Pos) /*!< MCPWM MAT1: MCMAT Mask */
+
+// --------------------------------------- MCPWM_MAT2 -------------------------------------------
+#define MCPWM_MAT2_MCMAT_Pos 0 /*!< MCPWM MAT2: MCMAT Position */
+#define MCPWM_MAT2_MCMAT_Msk (0xffffffffUL << MCPWM_MAT2_MCMAT_Pos) /*!< MCPWM MAT2: MCMAT Mask */
+
+// ---------------------------------------- MCPWM_DT --------------------------------------------
+#define MCPWM_DT_DT0_Pos 0 /*!< MCPWM DT: DT0 Position */
+#define MCPWM_DT_DT0_Msk (0x000003ffUL << MCPWM_DT_DT0_Pos) /*!< MCPWM DT: DT0 Mask */
+#define MCPWM_DT_DT1_Pos 10 /*!< MCPWM DT: DT1 Position */
+#define MCPWM_DT_DT1_Msk (0x000003ffUL << MCPWM_DT_DT1_Pos) /*!< MCPWM DT: DT1 Mask */
+#define MCPWM_DT_DT2_Pos 20 /*!< MCPWM DT: DT2 Position */
+#define MCPWM_DT_DT2_Msk (0x000003ffUL << MCPWM_DT_DT2_Pos) /*!< MCPWM DT: DT2 Mask */
+
+// ---------------------------------------- MCPWM_CCP -------------------------------------------
+#define MCPWM_CCP_CCPA0_Pos 0 /*!< MCPWM CCP: CCPA0 Position */
+#define MCPWM_CCP_CCPA0_Msk (0x01UL << MCPWM_CCP_CCPA0_Pos) /*!< MCPWM CCP: CCPA0 Mask */
+#define MCPWM_CCP_CCPB0_Pos 1 /*!< MCPWM CCP: CCPB0 Position */
+#define MCPWM_CCP_CCPB0_Msk (0x01UL << MCPWM_CCP_CCPB0_Pos) /*!< MCPWM CCP: CCPB0 Mask */
+#define MCPWM_CCP_CCPA1_Pos 2 /*!< MCPWM CCP: CCPA1 Position */
+#define MCPWM_CCP_CCPA1_Msk (0x01UL << MCPWM_CCP_CCPA1_Pos) /*!< MCPWM CCP: CCPA1 Mask */
+#define MCPWM_CCP_CCPB1_Pos 3 /*!< MCPWM CCP: CCPB1 Position */
+#define MCPWM_CCP_CCPB1_Msk (0x01UL << MCPWM_CCP_CCPB1_Pos) /*!< MCPWM CCP: CCPB1 Mask */
+#define MCPWM_CCP_CCPA2_Pos 4 /*!< MCPWM CCP: CCPA2 Position */
+#define MCPWM_CCP_CCPA2_Msk (0x01UL << MCPWM_CCP_CCPA2_Pos) /*!< MCPWM CCP: CCPA2 Mask */
+#define MCPWM_CCP_CCPB2_Pos 5 /*!< MCPWM CCP: CCPB2 Position */
+#define MCPWM_CCP_CCPB2_Msk (0x01UL << MCPWM_CCP_CCPB2_Pos) /*!< MCPWM CCP: CCPB2 Mask */
+
+// --------------------------------------- MCPWM_CAP0 -------------------------------------------
+#define MCPWM_CAP0_CAP_Pos 0 /*!< MCPWM CAP0: CAP Position */
+#define MCPWM_CAP0_CAP_Msk (0xffffffffUL << MCPWM_CAP0_CAP_Pos) /*!< MCPWM CAP0: CAP Mask */
+
+// --------------------------------------- MCPWM_CAP1 -------------------------------------------
+#define MCPWM_CAP1_CAP_Pos 0 /*!< MCPWM CAP1: CAP Position */
+#define MCPWM_CAP1_CAP_Msk (0xffffffffUL << MCPWM_CAP1_CAP_Pos) /*!< MCPWM CAP1: CAP Mask */
+
+// --------------------------------------- MCPWM_CAP2 -------------------------------------------
+#define MCPWM_CAP2_CAP_Pos 0 /*!< MCPWM CAP2: CAP Position */
+#define MCPWM_CAP2_CAP_Msk (0xffffffffUL << MCPWM_CAP2_CAP_Pos) /*!< MCPWM CAP2: CAP Mask */
+
+// --------------------------------------- MCPWM_INTEN ------------------------------------------
+#define MCPWM_INTEN_ILIM0_Pos 0 /*!< MCPWM INTEN: ILIM0 Position */
+#define MCPWM_INTEN_ILIM0_Msk (0x01UL << MCPWM_INTEN_ILIM0_Pos) /*!< MCPWM INTEN: ILIM0 Mask */
+#define MCPWM_INTEN_IMAT0_Pos 1 /*!< MCPWM INTEN: IMAT0 Position */
+#define MCPWM_INTEN_IMAT0_Msk (0x01UL << MCPWM_INTEN_IMAT0_Pos) /*!< MCPWM INTEN: IMAT0 Mask */
+#define MCPWM_INTEN_ICAP0_Pos 2 /*!< MCPWM INTEN: ICAP0 Position */
+#define MCPWM_INTEN_ICAP0_Msk (0x01UL << MCPWM_INTEN_ICAP0_Pos) /*!< MCPWM INTEN: ICAP0 Mask */
+#define MCPWM_INTEN_ILIM1_Pos 4 /*!< MCPWM INTEN: ILIM1 Position */
+#define MCPWM_INTEN_ILIM1_Msk (0x01UL << MCPWM_INTEN_ILIM1_Pos) /*!< MCPWM INTEN: ILIM1 Mask */
+#define MCPWM_INTEN_IMAT1_Pos 5 /*!< MCPWM INTEN: IMAT1 Position */
+#define MCPWM_INTEN_IMAT1_Msk (0x01UL << MCPWM_INTEN_IMAT1_Pos) /*!< MCPWM INTEN: IMAT1 Mask */
+#define MCPWM_INTEN_ICAP1_Pos 6 /*!< MCPWM INTEN: ICAP1 Position */
+#define MCPWM_INTEN_ICAP1_Msk (0x01UL << MCPWM_INTEN_ICAP1_Pos) /*!< MCPWM INTEN: ICAP1 Mask */
+#define MCPWM_INTEN_ILIM2_Pos 8 /*!< MCPWM INTEN: ILIM2 Position */
+#define MCPWM_INTEN_ILIM2_Msk (0x01UL << MCPWM_INTEN_ILIM2_Pos) /*!< MCPWM INTEN: ILIM2 Mask */
+#define MCPWM_INTEN_IMAT2_Pos 9 /*!< MCPWM INTEN: IMAT2 Position */
+#define MCPWM_INTEN_IMAT2_Msk (0x01UL << MCPWM_INTEN_IMAT2_Pos) /*!< MCPWM INTEN: IMAT2 Mask */
+#define MCPWM_INTEN_ICAP2_Pos 10 /*!< MCPWM INTEN: ICAP2 Position */
+#define MCPWM_INTEN_ICAP2_Msk (0x01UL << MCPWM_INTEN_ICAP2_Pos) /*!< MCPWM INTEN: ICAP2 Mask */
+#define MCPWM_INTEN_ABORT_Pos 15 /*!< MCPWM INTEN: ABORT Position */
+#define MCPWM_INTEN_ABORT_Msk (0x01UL << MCPWM_INTEN_ABORT_Pos) /*!< MCPWM INTEN: ABORT Mask */
+
+// ------------------------------------- MCPWM_INTEN_SET ----------------------------------------
+#define MCPWM_INTEN_SET_ILIM0_SET_Pos 0 /*!< MCPWM INTEN_SET: ILIM0_SET Position */
+#define MCPWM_INTEN_SET_ILIM0_SET_Msk (0x01UL << MCPWM_INTEN_SET_ILIM0_SET_Pos) /*!< MCPWM INTEN_SET: ILIM0_SET Mask */
+#define MCPWM_INTEN_SET_IMAT0_SET_Pos 1 /*!< MCPWM INTEN_SET: IMAT0_SET Position */
+#define MCPWM_INTEN_SET_IMAT0_SET_Msk (0x01UL << MCPWM_INTEN_SET_IMAT0_SET_Pos) /*!< MCPWM INTEN_SET: IMAT0_SET Mask */
+#define MCPWM_INTEN_SET_ICAP0_SET_Pos 2 /*!< MCPWM INTEN_SET: ICAP0_SET Position */
+#define MCPWM_INTEN_SET_ICAP0_SET_Msk (0x01UL << MCPWM_INTEN_SET_ICAP0_SET_Pos) /*!< MCPWM INTEN_SET: ICAP0_SET Mask */
+#define MCPWM_INTEN_SET_ILIM1_SET_Pos 4 /*!< MCPWM INTEN_SET: ILIM1_SET Position */
+#define MCPWM_INTEN_SET_ILIM1_SET_Msk (0x01UL << MCPWM_INTEN_SET_ILIM1_SET_Pos) /*!< MCPWM INTEN_SET: ILIM1_SET Mask */
+#define MCPWM_INTEN_SET_IMAT1_SET_Pos 5 /*!< MCPWM INTEN_SET: IMAT1_SET Position */
+#define MCPWM_INTEN_SET_IMAT1_SET_Msk (0x01UL << MCPWM_INTEN_SET_IMAT1_SET_Pos) /*!< MCPWM INTEN_SET: IMAT1_SET Mask */
+#define MCPWM_INTEN_SET_ICAP1_SET_Pos 6 /*!< MCPWM INTEN_SET: ICAP1_SET Position */
+#define MCPWM_INTEN_SET_ICAP1_SET_Msk (0x01UL << MCPWM_INTEN_SET_ICAP1_SET_Pos) /*!< MCPWM INTEN_SET: ICAP1_SET Mask */
+#define MCPWM_INTEN_SET_ILIM2_SET_Pos 9 /*!< MCPWM INTEN_SET: ILIM2_SET Position */
+#define MCPWM_INTEN_SET_ILIM2_SET_Msk (0x01UL << MCPWM_INTEN_SET_ILIM2_SET_Pos) /*!< MCPWM INTEN_SET: ILIM2_SET Mask */
+#define MCPWM_INTEN_SET_IMAT2_SET_Pos 10 /*!< MCPWM INTEN_SET: IMAT2_SET Position */
+#define MCPWM_INTEN_SET_IMAT2_SET_Msk (0x01UL << MCPWM_INTEN_SET_IMAT2_SET_Pos) /*!< MCPWM INTEN_SET: IMAT2_SET Mask */
+#define MCPWM_INTEN_SET_ICAP2_SET_Pos 11 /*!< MCPWM INTEN_SET: ICAP2_SET Position */
+#define MCPWM_INTEN_SET_ICAP2_SET_Msk (0x01UL << MCPWM_INTEN_SET_ICAP2_SET_Pos) /*!< MCPWM INTEN_SET: ICAP2_SET Mask */
+#define MCPWM_INTEN_SET_ABORT_SET_Pos 15 /*!< MCPWM INTEN_SET: ABORT_SET Position */
+#define MCPWM_INTEN_SET_ABORT_SET_Msk (0x01UL << MCPWM_INTEN_SET_ABORT_SET_Pos) /*!< MCPWM INTEN_SET: ABORT_SET Mask */
+
+// ------------------------------------- MCPWM_INTEN_CLR ----------------------------------------
+#define MCPWM_INTEN_CLR_ILIM0_CLR_Pos 0 /*!< MCPWM INTEN_CLR: ILIM0_CLR Position */
+#define MCPWM_INTEN_CLR_ILIM0_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ILIM0_CLR_Pos) /*!< MCPWM INTEN_CLR: ILIM0_CLR Mask */
+#define MCPWM_INTEN_CLR_IMAT0_CLR_Pos 1 /*!< MCPWM INTEN_CLR: IMAT0_CLR Position */
+#define MCPWM_INTEN_CLR_IMAT0_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_IMAT0_CLR_Pos) /*!< MCPWM INTEN_CLR: IMAT0_CLR Mask */
+#define MCPWM_INTEN_CLR_ICAP0_CLR_Pos 2 /*!< MCPWM INTEN_CLR: ICAP0_CLR Position */
+#define MCPWM_INTEN_CLR_ICAP0_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ICAP0_CLR_Pos) /*!< MCPWM INTEN_CLR: ICAP0_CLR Mask */
+#define MCPWM_INTEN_CLR_ILIM1_CLR_Pos 4 /*!< MCPWM INTEN_CLR: ILIM1_CLR Position */
+#define MCPWM_INTEN_CLR_ILIM1_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ILIM1_CLR_Pos) /*!< MCPWM INTEN_CLR: ILIM1_CLR Mask */
+#define MCPWM_INTEN_CLR_IMAT1_CLR_Pos 5 /*!< MCPWM INTEN_CLR: IMAT1_CLR Position */
+#define MCPWM_INTEN_CLR_IMAT1_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_IMAT1_CLR_Pos) /*!< MCPWM INTEN_CLR: IMAT1_CLR Mask */
+#define MCPWM_INTEN_CLR_ICAP1_CLR_Pos 6 /*!< MCPWM INTEN_CLR: ICAP1_CLR Position */
+#define MCPWM_INTEN_CLR_ICAP1_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ICAP1_CLR_Pos) /*!< MCPWM INTEN_CLR: ICAP1_CLR Mask */
+#define MCPWM_INTEN_CLR_ILIM2_CLR_Pos 8 /*!< MCPWM INTEN_CLR: ILIM2_CLR Position */
+#define MCPWM_INTEN_CLR_ILIM2_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ILIM2_CLR_Pos) /*!< MCPWM INTEN_CLR: ILIM2_CLR Mask */
+#define MCPWM_INTEN_CLR_IMAT2_CLR_Pos 9 /*!< MCPWM INTEN_CLR: IMAT2_CLR Position */
+#define MCPWM_INTEN_CLR_IMAT2_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_IMAT2_CLR_Pos) /*!< MCPWM INTEN_CLR: IMAT2_CLR Mask */
+#define MCPWM_INTEN_CLR_ICAP2_CLR_Pos 10 /*!< MCPWM INTEN_CLR: ICAP2_CLR Position */
+#define MCPWM_INTEN_CLR_ICAP2_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ICAP2_CLR_Pos) /*!< MCPWM INTEN_CLR: ICAP2_CLR Mask */
+#define MCPWM_INTEN_CLR_ABORT_CLR_Pos 15 /*!< MCPWM INTEN_CLR: ABORT_CLR Position */
+#define MCPWM_INTEN_CLR_ABORT_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ABORT_CLR_Pos) /*!< MCPWM INTEN_CLR: ABORT_CLR Mask */
+
+// -------------------------------------- MCPWM_CNTCON ------------------------------------------
+#define MCPWM_CNTCON_TC0MCI0_RE_Pos 0 /*!< MCPWM CNTCON: TC0MCI0_RE Position */
+#define MCPWM_CNTCON_TC0MCI0_RE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI0_RE_Pos) /*!< MCPWM CNTCON: TC0MCI0_RE Mask */
+#define MCPWM_CNTCON_TC0MCI0_FE_Pos 1 /*!< MCPWM CNTCON: TC0MCI0_FE Position */
+#define MCPWM_CNTCON_TC0MCI0_FE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI0_FE_Pos) /*!< MCPWM CNTCON: TC0MCI0_FE Mask */
+#define MCPWM_CNTCON_TC0MCI1_RE_Pos 2 /*!< MCPWM CNTCON: TC0MCI1_RE Position */
+#define MCPWM_CNTCON_TC0MCI1_RE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI1_RE_Pos) /*!< MCPWM CNTCON: TC0MCI1_RE Mask */
+#define MCPWM_CNTCON_TC0MCI1_FE_Pos 3 /*!< MCPWM CNTCON: TC0MCI1_FE Position */
+#define MCPWM_CNTCON_TC0MCI1_FE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI1_FE_Pos) /*!< MCPWM CNTCON: TC0MCI1_FE Mask */
+#define MCPWM_CNTCON_TC0MCI2_RE_Pos 4 /*!< MCPWM CNTCON: TC0MCI2_RE Position */
+#define MCPWM_CNTCON_TC0MCI2_RE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI2_RE_Pos) /*!< MCPWM CNTCON: TC0MCI2_RE Mask */
+#define MCPWM_CNTCON_TC0MCI2_FE_Pos 5 /*!< MCPWM CNTCON: TC0MCI2_FE Position */
+#define MCPWM_CNTCON_TC0MCI2_FE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI2_FE_Pos) /*!< MCPWM CNTCON: TC0MCI2_FE Mask */
+#define MCPWM_CNTCON_TC1MCI0_RE_Pos 6 /*!< MCPWM CNTCON: TC1MCI0_RE Position */
+#define MCPWM_CNTCON_TC1MCI0_RE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI0_RE_Pos) /*!< MCPWM CNTCON: TC1MCI0_RE Mask */
+#define MCPWM_CNTCON_TC1MCI0_FE_Pos 7 /*!< MCPWM CNTCON: TC1MCI0_FE Position */
+#define MCPWM_CNTCON_TC1MCI0_FE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI0_FE_Pos) /*!< MCPWM CNTCON: TC1MCI0_FE Mask */
+#define MCPWM_CNTCON_TC1MCI1_RE_Pos 8 /*!< MCPWM CNTCON: TC1MCI1_RE Position */
+#define MCPWM_CNTCON_TC1MCI1_RE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI1_RE_Pos) /*!< MCPWM CNTCON: TC1MCI1_RE Mask */
+#define MCPWM_CNTCON_TC1MCI1_FE_Pos 9 /*!< MCPWM CNTCON: TC1MCI1_FE Position */
+#define MCPWM_CNTCON_TC1MCI1_FE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI1_FE_Pos) /*!< MCPWM CNTCON: TC1MCI1_FE Mask */
+#define MCPWM_CNTCON_TC1MCI2_RE_Pos 10 /*!< MCPWM CNTCON: TC1MCI2_RE Position */
+#define MCPWM_CNTCON_TC1MCI2_RE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI2_RE_Pos) /*!< MCPWM CNTCON: TC1MCI2_RE Mask */
+#define MCPWM_CNTCON_TC1MCI2_FE_Pos 11 /*!< MCPWM CNTCON: TC1MCI2_FE Position */
+#define MCPWM_CNTCON_TC1MCI2_FE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI2_FE_Pos) /*!< MCPWM CNTCON: TC1MCI2_FE Mask */
+#define MCPWM_CNTCON_TC2MCI0_RE_Pos 12 /*!< MCPWM CNTCON: TC2MCI0_RE Position */
+#define MCPWM_CNTCON_TC2MCI0_RE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI0_RE_Pos) /*!< MCPWM CNTCON: TC2MCI0_RE Mask */
+#define MCPWM_CNTCON_TC2MCI0_FE_Pos 13 /*!< MCPWM CNTCON: TC2MCI0_FE Position */
+#define MCPWM_CNTCON_TC2MCI0_FE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI0_FE_Pos) /*!< MCPWM CNTCON: TC2MCI0_FE Mask */
+#define MCPWM_CNTCON_TC2MCI1_RE_Pos 14 /*!< MCPWM CNTCON: TC2MCI1_RE Position */
+#define MCPWM_CNTCON_TC2MCI1_RE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI1_RE_Pos) /*!< MCPWM CNTCON: TC2MCI1_RE Mask */
+#define MCPWM_CNTCON_TC2MCI1_FE_Pos 15 /*!< MCPWM CNTCON: TC2MCI1_FE Position */
+#define MCPWM_CNTCON_TC2MCI1_FE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI1_FE_Pos) /*!< MCPWM CNTCON: TC2MCI1_FE Mask */
+#define MCPWM_CNTCON_TC2MCI2_RE_Pos 16 /*!< MCPWM CNTCON: TC2MCI2_RE Position */
+#define MCPWM_CNTCON_TC2MCI2_RE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI2_RE_Pos) /*!< MCPWM CNTCON: TC2MCI2_RE Mask */
+#define MCPWM_CNTCON_TC2MCI2_FE_Pos 17 /*!< MCPWM CNTCON: TC2MCI2_FE Position */
+#define MCPWM_CNTCON_TC2MCI2_FE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI2_FE_Pos) /*!< MCPWM CNTCON: TC2MCI2_FE Mask */
+#define MCPWM_CNTCON_CNTR0_Pos 29 /*!< MCPWM CNTCON: CNTR0 Position */
+#define MCPWM_CNTCON_CNTR0_Msk (0x01UL << MCPWM_CNTCON_CNTR0_Pos) /*!< MCPWM CNTCON: CNTR0 Mask */
+#define MCPWM_CNTCON_CNTR1_Pos 30 /*!< MCPWM CNTCON: CNTR1 Position */
+#define MCPWM_CNTCON_CNTR1_Msk (0x01UL << MCPWM_CNTCON_CNTR1_Pos) /*!< MCPWM CNTCON: CNTR1 Mask */
+#define MCPWM_CNTCON_CNTR2_Pos 31 /*!< MCPWM CNTCON: CNTR2 Position */
+#define MCPWM_CNTCON_CNTR2_Msk (0x01UL << MCPWM_CNTCON_CNTR2_Pos) /*!< MCPWM CNTCON: CNTR2 Mask */
+
+// ------------------------------------ MCPWM_CNTCON_SET ----------------------------------------
+#define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Pos 0 /*!< MCPWM CNTCON_SET: TC0MCI0_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI0_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Pos 1 /*!< MCPWM CNTCON_SET: TC0MCI0_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI0_FE_SET Mask */
+#define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Pos 2 /*!< MCPWM CNTCON_SET: TC0MCI1_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI1_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Pos 3 /*!< MCPWM CNTCON_SET: TC0MCI1_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI1_FE_SET Mask */
+#define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Pos 4 /*!< MCPWM CNTCON_SET: TC0MCI2_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI2_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Pos 5 /*!< MCPWM CNTCON_SET: TC0MCI2_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI2_FE_SET Mask */
+#define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Pos 6 /*!< MCPWM CNTCON_SET: TC1MCI0_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI0_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Pos 7 /*!< MCPWM CNTCON_SET: TC1MCI0_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI0_FE_SET Mask */
+#define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Pos 8 /*!< MCPWM CNTCON_SET: TC1MCI1_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI1_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Pos 9 /*!< MCPWM CNTCON_SET: TC1MCI1_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI1_FE_SET Mask */
+#define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Pos 10 /*!< MCPWM CNTCON_SET: TC1MCI2_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI2_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Pos 11 /*!< MCPWM CNTCON_SET: TC1MCI2_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI2_FE_SET Mask */
+#define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Pos 12 /*!< MCPWM CNTCON_SET: TC2MCI0_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI0_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Pos 13 /*!< MCPWM CNTCON_SET: TC2MCI0_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI0_FE_SET Mask */
+#define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Pos 14 /*!< MCPWM CNTCON_SET: TC2MCI1_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI1_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Pos 15 /*!< MCPWM CNTCON_SET: TC2MCI1_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI1_FE_SET Mask */
+#define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Pos 16 /*!< MCPWM CNTCON_SET: TC2MCI2_RE_SET Position */
+#define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI2_RE_SET Mask */
+#define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Pos 17 /*!< MCPWM CNTCON_SET: TC2MCI2_FE_SET Position */
+#define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI2_FE_SET Mask */
+#define MCPWM_CNTCON_SET_CNTR0_SET_Pos 29 /*!< MCPWM CNTCON_SET: CNTR0_SET Position */
+#define MCPWM_CNTCON_SET_CNTR0_SET_Msk (0x01UL << MCPWM_CNTCON_SET_CNTR0_SET_Pos) /*!< MCPWM CNTCON_SET: CNTR0_SET Mask */
+#define MCPWM_CNTCON_SET_CNTR1_SET_Pos 30 /*!< MCPWM CNTCON_SET: CNTR1_SET Position */
+#define MCPWM_CNTCON_SET_CNTR1_SET_Msk (0x01UL << MCPWM_CNTCON_SET_CNTR1_SET_Pos) /*!< MCPWM CNTCON_SET: CNTR1_SET Mask */
+#define MCPWM_CNTCON_SET_CNTR2_SET_Pos 31 /*!< MCPWM CNTCON_SET: CNTR2_SET Position */
+#define MCPWM_CNTCON_SET_CNTR2_SET_Msk (0x01UL << MCPWM_CNTCON_SET_CNTR2_SET_Pos) /*!< MCPWM CNTCON_SET: CNTR2_SET Mask */
+
+// ------------------------------------ MCPWM_CNTCON_CLR ----------------------------------------
+#define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Pos 0 /*!< MCPWM CNTCON_CLR: TC0MCI0_RE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI0_RE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Pos 1 /*!< MCPWM CNTCON_CLR: TC0MCI0_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI0_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Pos 2 /*!< MCPWM CNTCON_CLR: TC0MCI1_RE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI1_RE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Pos 3 /*!< MCPWM CNTCON_CLR: TC0MCI1_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI1_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC0MCI2_RE_Pos 4 /*!< MCPWM CNTCON_CLR: TC0MCI2_RE Position */
+#define MCPWM_CNTCON_CLR_TC0MCI2_RE_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI2_RE_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI2_RE Mask */
+#define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Pos 5 /*!< MCPWM CNTCON_CLR: TC0MCI2_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI2_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Pos 6 /*!< MCPWM CNTCON_CLR: TC1MCI0_RE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI0_RE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Pos 7 /*!< MCPWM CNTCON_CLR: TC1MCI0_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI0_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Pos 8 /*!< MCPWM CNTCON_CLR: TC1MCI1_RE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI1_RE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Pos 9 /*!< MCPWM CNTCON_CLR: TC1MCI1_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI1_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Pos 10 /*!< MCPWM CNTCON_CLR: TC1MCI2_RE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI2_RE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Pos 11 /*!< MCPWM CNTCON_CLR: TC1MCI2_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI2_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Pos 12 /*!< MCPWM CNTCON_CLR: TC2MCI0_RE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI0_RE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Pos 13 /*!< MCPWM CNTCON_CLR: TC2MCI0_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI0_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Pos 14 /*!< MCPWM CNTCON_CLR: TC2MCI1_RE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI1_RE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Pos 15 /*!< MCPWM CNTCON_CLR: TC2MCI1_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI1_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Pos 16 /*!< MCPWM CNTCON_CLR: TC2MCI2_RE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI2_RE_CLR Mask */
+#define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Pos 17 /*!< MCPWM CNTCON_CLR: TC2MCI2_FE_CLR Position */
+#define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI2_FE_CLR Mask */
+#define MCPWM_CNTCON_CLR_CNTR0_CLR_Pos 29 /*!< MCPWM CNTCON_CLR: CNTR0_CLR Position */
+#define MCPWM_CNTCON_CLR_CNTR0_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_CNTR0_CLR_Pos) /*!< MCPWM CNTCON_CLR: CNTR0_CLR Mask */
+#define MCPWM_CNTCON_CLR_CNTR1_CLR_Pos 30 /*!< MCPWM CNTCON_CLR: CNTR1_CLR Position */
+#define MCPWM_CNTCON_CLR_CNTR1_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_CNTR1_CLR_Pos) /*!< MCPWM CNTCON_CLR: CNTR1_CLR Mask */
+#define MCPWM_CNTCON_CLR_CNTR2_CLR_Pos 31 /*!< MCPWM CNTCON_CLR: CNTR2_CLR Position */
+#define MCPWM_CNTCON_CLR_CNTR2_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_CNTR2_CLR_Pos) /*!< MCPWM CNTCON_CLR: CNTR2_CLR Mask */
+
+// --------------------------------------- MCPWM_INTF -------------------------------------------
+#define MCPWM_INTF_ILIM0_F_Pos 0 /*!< MCPWM INTF: ILIM0_F Position */
+#define MCPWM_INTF_ILIM0_F_Msk (0x01UL << MCPWM_INTF_ILIM0_F_Pos) /*!< MCPWM INTF: ILIM0_F Mask */
+#define MCPWM_INTF_IMAT0_F_Pos 1 /*!< MCPWM INTF: IMAT0_F Position */
+#define MCPWM_INTF_IMAT0_F_Msk (0x01UL << MCPWM_INTF_IMAT0_F_Pos) /*!< MCPWM INTF: IMAT0_F Mask */
+#define MCPWM_INTF_ICAP0_F_Pos 2 /*!< MCPWM INTF: ICAP0_F Position */
+#define MCPWM_INTF_ICAP0_F_Msk (0x01UL << MCPWM_INTF_ICAP0_F_Pos) /*!< MCPWM INTF: ICAP0_F Mask */
+#define MCPWM_INTF_ILIM1_F_Pos 4 /*!< MCPWM INTF: ILIM1_F Position */
+#define MCPWM_INTF_ILIM1_F_Msk (0x01UL << MCPWM_INTF_ILIM1_F_Pos) /*!< MCPWM INTF: ILIM1_F Mask */
+#define MCPWM_INTF_IMAT1_F_Pos 5 /*!< MCPWM INTF: IMAT1_F Position */
+#define MCPWM_INTF_IMAT1_F_Msk (0x01UL << MCPWM_INTF_IMAT1_F_Pos) /*!< MCPWM INTF: IMAT1_F Mask */
+#define MCPWM_INTF_ICAP1_F_Pos 6 /*!< MCPWM INTF: ICAP1_F Position */
+#define MCPWM_INTF_ICAP1_F_Msk (0x01UL << MCPWM_INTF_ICAP1_F_Pos) /*!< MCPWM INTF: ICAP1_F Mask */
+#define MCPWM_INTF_ILIM2_F_Pos 8 /*!< MCPWM INTF: ILIM2_F Position */
+#define MCPWM_INTF_ILIM2_F_Msk (0x01UL << MCPWM_INTF_ILIM2_F_Pos) /*!< MCPWM INTF: ILIM2_F Mask */
+#define MCPWM_INTF_IMAT2_F_Pos 9 /*!< MCPWM INTF: IMAT2_F Position */
+#define MCPWM_INTF_IMAT2_F_Msk (0x01UL << MCPWM_INTF_IMAT2_F_Pos) /*!< MCPWM INTF: IMAT2_F Mask */
+#define MCPWM_INTF_ICAP2_F_Pos 10 /*!< MCPWM INTF: ICAP2_F Position */
+#define MCPWM_INTF_ICAP2_F_Msk (0x01UL << MCPWM_INTF_ICAP2_F_Pos) /*!< MCPWM INTF: ICAP2_F Mask */
+#define MCPWM_INTF_ABORT_F_Pos 15 /*!< MCPWM INTF: ABORT_F Position */
+#define MCPWM_INTF_ABORT_F_Msk (0x01UL << MCPWM_INTF_ABORT_F_Pos) /*!< MCPWM INTF: ABORT_F Mask */
+
+// ------------------------------------- MCPWM_INTF_SET -----------------------------------------
+#define MCPWM_INTF_SET_ILIM0_F_SET_Pos 0 /*!< MCPWM INTF_SET: ILIM0_F_SET Position */
+#define MCPWM_INTF_SET_ILIM0_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ILIM0_F_SET_Pos) /*!< MCPWM INTF_SET: ILIM0_F_SET Mask */
+#define MCPWM_INTF_SET_IMAT0_F_SET_Pos 1 /*!< MCPWM INTF_SET: IMAT0_F_SET Position */
+#define MCPWM_INTF_SET_IMAT0_F_SET_Msk (0x01UL << MCPWM_INTF_SET_IMAT0_F_SET_Pos) /*!< MCPWM INTF_SET: IMAT0_F_SET Mask */
+#define MCPWM_INTF_SET_ICAP0_F_SET_Pos 2 /*!< MCPWM INTF_SET: ICAP0_F_SET Position */
+#define MCPWM_INTF_SET_ICAP0_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ICAP0_F_SET_Pos) /*!< MCPWM INTF_SET: ICAP0_F_SET Mask */
+#define MCPWM_INTF_SET_ILIM1_F_SET_Pos 4 /*!< MCPWM INTF_SET: ILIM1_F_SET Position */
+#define MCPWM_INTF_SET_ILIM1_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ILIM1_F_SET_Pos) /*!< MCPWM INTF_SET: ILIM1_F_SET Mask */
+#define MCPWM_INTF_SET_IMAT1_F_SET_Pos 5 /*!< MCPWM INTF_SET: IMAT1_F_SET Position */
+#define MCPWM_INTF_SET_IMAT1_F_SET_Msk (0x01UL << MCPWM_INTF_SET_IMAT1_F_SET_Pos) /*!< MCPWM INTF_SET: IMAT1_F_SET Mask */
+#define MCPWM_INTF_SET_ICAP1_F_SET_Pos 6 /*!< MCPWM INTF_SET: ICAP1_F_SET Position */
+#define MCPWM_INTF_SET_ICAP1_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ICAP1_F_SET_Pos) /*!< MCPWM INTF_SET: ICAP1_F_SET Mask */
+#define MCPWM_INTF_SET_ILIM2_F_SET_Pos 8 /*!< MCPWM INTF_SET: ILIM2_F_SET Position */
+#define MCPWM_INTF_SET_ILIM2_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ILIM2_F_SET_Pos) /*!< MCPWM INTF_SET: ILIM2_F_SET Mask */
+#define MCPWM_INTF_SET_IMAT2_F_SET_Pos 9 /*!< MCPWM INTF_SET: IMAT2_F_SET Position */
+#define MCPWM_INTF_SET_IMAT2_F_SET_Msk (0x01UL << MCPWM_INTF_SET_IMAT2_F_SET_Pos) /*!< MCPWM INTF_SET: IMAT2_F_SET Mask */
+#define MCPWM_INTF_SET_ICAP2_F_SET_Pos 10 /*!< MCPWM INTF_SET: ICAP2_F_SET Position */
+#define MCPWM_INTF_SET_ICAP2_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ICAP2_F_SET_Pos) /*!< MCPWM INTF_SET: ICAP2_F_SET Mask */
+#define MCPWM_INTF_SET_ABORT_F_SET_Pos 15 /*!< MCPWM INTF_SET: ABORT_F_SET Position */
+#define MCPWM_INTF_SET_ABORT_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ABORT_F_SET_Pos) /*!< MCPWM INTF_SET: ABORT_F_SET Mask */
+
+// ------------------------------------- MCPWM_INTF_CLR -----------------------------------------
+#define MCPWM_INTF_CLR_ILIM0_F_CLR_Pos 0 /*!< MCPWM INTF_CLR: ILIM0_F_CLR Position */
+#define MCPWM_INTF_CLR_ILIM0_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ILIM0_F_CLR_Pos) /*!< MCPWM INTF_CLR: ILIM0_F_CLR Mask */
+#define MCPWM_INTF_CLR_IMAT0_F_CLR_Pos 1 /*!< MCPWM INTF_CLR: IMAT0_F_CLR Position */
+#define MCPWM_INTF_CLR_IMAT0_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_IMAT0_F_CLR_Pos) /*!< MCPWM INTF_CLR: IMAT0_F_CLR Mask */
+#define MCPWM_INTF_CLR_ICAP0_F_CLR_Pos 2 /*!< MCPWM INTF_CLR: ICAP0_F_CLR Position */
+#define MCPWM_INTF_CLR_ICAP0_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ICAP0_F_CLR_Pos) /*!< MCPWM INTF_CLR: ICAP0_F_CLR Mask */
+#define MCPWM_INTF_CLR_ILIM1_F_CLR_Pos 4 /*!< MCPWM INTF_CLR: ILIM1_F_CLR Position */
+#define MCPWM_INTF_CLR_ILIM1_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ILIM1_F_CLR_Pos) /*!< MCPWM INTF_CLR: ILIM1_F_CLR Mask */
+#define MCPWM_INTF_CLR_IMAT1_F_CLR_Pos 5 /*!< MCPWM INTF_CLR: IMAT1_F_CLR Position */
+#define MCPWM_INTF_CLR_IMAT1_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_IMAT1_F_CLR_Pos) /*!< MCPWM INTF_CLR: IMAT1_F_CLR Mask */
+#define MCPWM_INTF_CLR_ICAP1_F_CLR_Pos 6 /*!< MCPWM INTF_CLR: ICAP1_F_CLR Position */
+#define MCPWM_INTF_CLR_ICAP1_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ICAP1_F_CLR_Pos) /*!< MCPWM INTF_CLR: ICAP1_F_CLR Mask */
+#define MCPWM_INTF_CLR_ILIM2_F_CLR_Pos 8 /*!< MCPWM INTF_CLR: ILIM2_F_CLR Position */
+#define MCPWM_INTF_CLR_ILIM2_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ILIM2_F_CLR_Pos) /*!< MCPWM INTF_CLR: ILIM2_F_CLR Mask */
+#define MCPWM_INTF_CLR_IMAT2_F_CLR_Pos 9 /*!< MCPWM INTF_CLR: IMAT2_F_CLR Position */
+#define MCPWM_INTF_CLR_IMAT2_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_IMAT2_F_CLR_Pos) /*!< MCPWM INTF_CLR: IMAT2_F_CLR Mask */
+#define MCPWM_INTF_CLR_ICAP2_F_CLR_Pos 10 /*!< MCPWM INTF_CLR: ICAP2_F_CLR Position */
+#define MCPWM_INTF_CLR_ICAP2_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ICAP2_F_CLR_Pos) /*!< MCPWM INTF_CLR: ICAP2_F_CLR Mask */
+#define MCPWM_INTF_CLR_ABORT_F_CLR_Pos 15 /*!< MCPWM INTF_CLR: ABORT_F_CLR Position */
+#define MCPWM_INTF_CLR_ABORT_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ABORT_F_CLR_Pos) /*!< MCPWM INTF_CLR: ABORT_F_CLR Mask */
+
+// -------------------------------------- MCPWM_CAP_CLR -----------------------------------------
+#define MCPWM_CAP_CLR_CAP_CLR0_Pos 0 /*!< MCPWM CAP_CLR: CAP_CLR0 Position */
+#define MCPWM_CAP_CLR_CAP_CLR0_Msk (0x01UL << MCPWM_CAP_CLR_CAP_CLR0_Pos) /*!< MCPWM CAP_CLR: CAP_CLR0 Mask */
+#define MCPWM_CAP_CLR_CAP_CLR1_Pos 1 /*!< MCPWM CAP_CLR: CAP_CLR1 Position */
+#define MCPWM_CAP_CLR_CAP_CLR1_Msk (0x01UL << MCPWM_CAP_CLR_CAP_CLR1_Pos) /*!< MCPWM CAP_CLR: CAP_CLR1 Mask */
+#define MCPWM_CAP_CLR_CAP_CLR2_Pos 2 /*!< MCPWM CAP_CLR: CAP_CLR2 Position */
+#define MCPWM_CAP_CLR_CAP_CLR2_Msk (0x01UL << MCPWM_CAP_CLR_CAP_CLR2_Pos) /*!< MCPWM CAP_CLR: CAP_CLR2 Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- I2C0 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------- I2C0_CONSET ------------------------------------------
+#define I2C0_CONSET_AA_Pos 2 /*!< I2C0 CONSET: AA Position */
+#define I2C0_CONSET_AA_Msk (0x01UL << I2C0_CONSET_AA_Pos) /*!< I2C0 CONSET: AA Mask */
+#define I2C0_CONSET_SI_Pos 3 /*!< I2C0 CONSET: SI Position */
+#define I2C0_CONSET_SI_Msk (0x01UL << I2C0_CONSET_SI_Pos) /*!< I2C0 CONSET: SI Mask */
+#define I2C0_CONSET_STO_Pos 4 /*!< I2C0 CONSET: STO Position */
+#define I2C0_CONSET_STO_Msk (0x01UL << I2C0_CONSET_STO_Pos) /*!< I2C0 CONSET: STO Mask */
+#define I2C0_CONSET_STA_Pos 5 /*!< I2C0 CONSET: STA Position */
+#define I2C0_CONSET_STA_Msk (0x01UL << I2C0_CONSET_STA_Pos) /*!< I2C0 CONSET: STA Mask */
+#define I2C0_CONSET_I2EN_Pos 6 /*!< I2C0 CONSET: I2EN Position */
+#define I2C0_CONSET_I2EN_Msk (0x01UL << I2C0_CONSET_I2EN_Pos) /*!< I2C0 CONSET: I2EN Mask */
+
+// ---------------------------------------- I2C0_STAT -------------------------------------------
+#define I2C0_STAT_Status_Pos 3 /*!< I2C0 STAT: Status Position */
+#define I2C0_STAT_Status_Msk (0x1fUL << I2C0_STAT_Status_Pos) /*!< I2C0 STAT: Status Mask */
+
+// ---------------------------------------- I2C0_DAT --------------------------------------------
+#define I2C0_DAT_Data_Pos 0 /*!< I2C0 DAT: Data Position */
+#define I2C0_DAT_Data_Msk (0x000000ffUL << I2C0_DAT_Data_Pos) /*!< I2C0 DAT: Data Mask */
+
+// ---------------------------------------- I2C0_ADR0 -------------------------------------------
+#define I2C0_ADR0_GC_Pos 0 /*!< I2C0 ADR0: GC Position */
+#define I2C0_ADR0_GC_Msk (0x01UL << I2C0_ADR0_GC_Pos) /*!< I2C0 ADR0: GC Mask */
+#define I2C0_ADR0_Address_Pos 1 /*!< I2C0 ADR0: Address Position */
+#define I2C0_ADR0_Address_Msk (0x7fUL << I2C0_ADR0_Address_Pos) /*!< I2C0 ADR0: Address Mask */
+
+// ---------------------------------------- I2C0_SCLH -------------------------------------------
+#define I2C0_SCLH_SCLH_Pos 0 /*!< I2C0 SCLH: SCLH Position */
+#define I2C0_SCLH_SCLH_Msk (0x0000ffffUL << I2C0_SCLH_SCLH_Pos) /*!< I2C0 SCLH: SCLH Mask */
+
+// ---------------------------------------- I2C0_SCLL -------------------------------------------
+#define I2C0_SCLL_SCLL_Pos 0 /*!< I2C0 SCLL: SCLL Position */
+#define I2C0_SCLL_SCLL_Msk (0x0000ffffUL << I2C0_SCLL_SCLL_Pos) /*!< I2C0 SCLL: SCLL Mask */
+
+// --------------------------------------- I2C0_CONCLR ------------------------------------------
+#define I2C0_CONCLR_AAC_Pos 2 /*!< I2C0 CONCLR: AAC Position */
+#define I2C0_CONCLR_AAC_Msk (0x01UL << I2C0_CONCLR_AAC_Pos) /*!< I2C0 CONCLR: AAC Mask */
+#define I2C0_CONCLR_SIC_Pos 3 /*!< I2C0 CONCLR: SIC Position */
+#define I2C0_CONCLR_SIC_Msk (0x01UL << I2C0_CONCLR_SIC_Pos) /*!< I2C0 CONCLR: SIC Mask */
+#define I2C0_CONCLR_STAC_Pos 5 /*!< I2C0 CONCLR: STAC Position */
+#define I2C0_CONCLR_STAC_Msk (0x01UL << I2C0_CONCLR_STAC_Pos) /*!< I2C0 CONCLR: STAC Mask */
+#define I2C0_CONCLR_I2ENC_Pos 6 /*!< I2C0 CONCLR: I2ENC Position */
+#define I2C0_CONCLR_I2ENC_Msk (0x01UL << I2C0_CONCLR_I2ENC_Pos) /*!< I2C0 CONCLR: I2ENC Mask */
+
+// --------------------------------------- I2C0_MMCTRL ------------------------------------------
+#define I2C0_MMCTRL_MM_ENA_Pos 0 /*!< I2C0 MMCTRL: MM_ENA Position */
+#define I2C0_MMCTRL_MM_ENA_Msk (0x01UL << I2C0_MMCTRL_MM_ENA_Pos) /*!< I2C0 MMCTRL: MM_ENA Mask */
+#define I2C0_MMCTRL_ENA_SCL_Pos 1 /*!< I2C0 MMCTRL: ENA_SCL Position */
+#define I2C0_MMCTRL_ENA_SCL_Msk (0x01UL << I2C0_MMCTRL_ENA_SCL_Pos) /*!< I2C0 MMCTRL: ENA_SCL Mask */
+#define I2C0_MMCTRL_MATCH_ALL_Pos 2 /*!< I2C0 MMCTRL: MATCH_ALL Position */
+#define I2C0_MMCTRL_MATCH_ALL_Msk (0x01UL << I2C0_MMCTRL_MATCH_ALL_Pos) /*!< I2C0 MMCTRL: MATCH_ALL Mask */
+
+// ---------------------------------------- I2C0_ADR1 -------------------------------------------
+#define I2C0_ADR1_GC_Pos 0 /*!< I2C0 ADR1: GC Position */
+#define I2C0_ADR1_GC_Msk (0x01UL << I2C0_ADR1_GC_Pos) /*!< I2C0 ADR1: GC Mask */
+#define I2C0_ADR1_Address_Pos 1 /*!< I2C0 ADR1: Address Position */
+#define I2C0_ADR1_Address_Msk (0x7fUL << I2C0_ADR1_Address_Pos) /*!< I2C0 ADR1: Address Mask */
+
+// ---------------------------------------- I2C0_ADR2 -------------------------------------------
+#define I2C0_ADR2_GC_Pos 0 /*!< I2C0 ADR2: GC Position */
+#define I2C0_ADR2_GC_Msk (0x01UL << I2C0_ADR2_GC_Pos) /*!< I2C0 ADR2: GC Mask */
+#define I2C0_ADR2_Address_Pos 1 /*!< I2C0 ADR2: Address Position */
+#define I2C0_ADR2_Address_Msk (0x7fUL << I2C0_ADR2_Address_Pos) /*!< I2C0 ADR2: Address Mask */
+
+// ---------------------------------------- I2C0_ADR3 -------------------------------------------
+#define I2C0_ADR3_GC_Pos 0 /*!< I2C0 ADR3: GC Position */
+#define I2C0_ADR3_GC_Msk (0x01UL << I2C0_ADR3_GC_Pos) /*!< I2C0 ADR3: GC Mask */
+#define I2C0_ADR3_Address_Pos 1 /*!< I2C0 ADR3: Address Position */
+#define I2C0_ADR3_Address_Msk (0x7fUL << I2C0_ADR3_Address_Pos) /*!< I2C0 ADR3: Address Mask */
+
+// ------------------------------------ I2C0_DATA_BUFFER ----------------------------------------
+#define I2C0_DATA_BUFFER_Data_Pos 0 /*!< I2C0 DATA_BUFFER: Data Position */
+#define I2C0_DATA_BUFFER_Data_Msk (0x000000ffUL << I2C0_DATA_BUFFER_Data_Pos) /*!< I2C0 DATA_BUFFER: Data Mask */
+
+// --------------------------------------- I2C0_MASK0 -------------------------------------------
+#define I2C0_MASK0_MASK_Pos 1 /*!< I2C0 MASK0: MASK Position */
+#define I2C0_MASK0_MASK_Msk (0x7fUL << I2C0_MASK0_MASK_Pos) /*!< I2C0 MASK0: MASK Mask */
+
+// --------------------------------------- I2C0_MASK1 -------------------------------------------
+#define I2C0_MASK1_MASK_Pos 1 /*!< I2C0 MASK1: MASK Position */
+#define I2C0_MASK1_MASK_Msk (0x7fUL << I2C0_MASK1_MASK_Pos) /*!< I2C0 MASK1: MASK Mask */
+
+// --------------------------------------- I2C0_MASK2 -------------------------------------------
+#define I2C0_MASK2_MASK_Pos 1 /*!< I2C0 MASK2: MASK Position */
+#define I2C0_MASK2_MASK_Msk (0x7fUL << I2C0_MASK2_MASK_Pos) /*!< I2C0 MASK2: MASK Mask */
+
+// --------------------------------------- I2C0_MASK3 -------------------------------------------
+#define I2C0_MASK3_MASK_Pos 1 /*!< I2C0 MASK3: MASK Position */
+#define I2C0_MASK3_MASK_Msk (0x7fUL << I2C0_MASK3_MASK_Pos) /*!< I2C0 MASK3: MASK Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- I2C1 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------- I2C1_CONSET ------------------------------------------
+#define I2C1_CONSET_AA_Pos 2 /*!< I2C1 CONSET: AA Position */
+#define I2C1_CONSET_AA_Msk (0x01UL << I2C1_CONSET_AA_Pos) /*!< I2C1 CONSET: AA Mask */
+#define I2C1_CONSET_SI_Pos 3 /*!< I2C1 CONSET: SI Position */
+#define I2C1_CONSET_SI_Msk (0x01UL << I2C1_CONSET_SI_Pos) /*!< I2C1 CONSET: SI Mask */
+#define I2C1_CONSET_STO_Pos 4 /*!< I2C1 CONSET: STO Position */
+#define I2C1_CONSET_STO_Msk (0x01UL << I2C1_CONSET_STO_Pos) /*!< I2C1 CONSET: STO Mask */
+#define I2C1_CONSET_STA_Pos 5 /*!< I2C1 CONSET: STA Position */
+#define I2C1_CONSET_STA_Msk (0x01UL << I2C1_CONSET_STA_Pos) /*!< I2C1 CONSET: STA Mask */
+#define I2C1_CONSET_I2EN_Pos 6 /*!< I2C1 CONSET: I2EN Position */
+#define I2C1_CONSET_I2EN_Msk (0x01UL << I2C1_CONSET_I2EN_Pos) /*!< I2C1 CONSET: I2EN Mask */
+
+// ---------------------------------------- I2C1_STAT -------------------------------------------
+#define I2C1_STAT_Status_Pos 3 /*!< I2C1 STAT: Status Position */
+#define I2C1_STAT_Status_Msk (0x1fUL << I2C1_STAT_Status_Pos) /*!< I2C1 STAT: Status Mask */
+
+// ---------------------------------------- I2C1_DAT --------------------------------------------
+#define I2C1_DAT_Data_Pos 0 /*!< I2C1 DAT: Data Position */
+#define I2C1_DAT_Data_Msk (0x000000ffUL << I2C1_DAT_Data_Pos) /*!< I2C1 DAT: Data Mask */
+
+// ---------------------------------------- I2C1_ADR0 -------------------------------------------
+#define I2C1_ADR0_GC_Pos 0 /*!< I2C1 ADR0: GC Position */
+#define I2C1_ADR0_GC_Msk (0x01UL << I2C1_ADR0_GC_Pos) /*!< I2C1 ADR0: GC Mask */
+#define I2C1_ADR0_Address_Pos 1 /*!< I2C1 ADR0: Address Position */
+#define I2C1_ADR0_Address_Msk (0x7fUL << I2C1_ADR0_Address_Pos) /*!< I2C1 ADR0: Address Mask */
+
+// ---------------------------------------- I2C1_SCLH -------------------------------------------
+#define I2C1_SCLH_SCLH_Pos 0 /*!< I2C1 SCLH: SCLH Position */
+#define I2C1_SCLH_SCLH_Msk (0x0000ffffUL << I2C1_SCLH_SCLH_Pos) /*!< I2C1 SCLH: SCLH Mask */
+
+// ---------------------------------------- I2C1_SCLL -------------------------------------------
+#define I2C1_SCLL_SCLL_Pos 0 /*!< I2C1 SCLL: SCLL Position */
+#define I2C1_SCLL_SCLL_Msk (0x0000ffffUL << I2C1_SCLL_SCLL_Pos) /*!< I2C1 SCLL: SCLL Mask */
+
+// --------------------------------------- I2C1_CONCLR ------------------------------------------
+#define I2C1_CONCLR_AAC_Pos 2 /*!< I2C1 CONCLR: AAC Position */
+#define I2C1_CONCLR_AAC_Msk (0x01UL << I2C1_CONCLR_AAC_Pos) /*!< I2C1 CONCLR: AAC Mask */
+#define I2C1_CONCLR_SIC_Pos 3 /*!< I2C1 CONCLR: SIC Position */
+#define I2C1_CONCLR_SIC_Msk (0x01UL << I2C1_CONCLR_SIC_Pos) /*!< I2C1 CONCLR: SIC Mask */
+#define I2C1_CONCLR_STAC_Pos 5 /*!< I2C1 CONCLR: STAC Position */
+#define I2C1_CONCLR_STAC_Msk (0x01UL << I2C1_CONCLR_STAC_Pos) /*!< I2C1 CONCLR: STAC Mask */
+#define I2C1_CONCLR_I2ENC_Pos 6 /*!< I2C1 CONCLR: I2ENC Position */
+#define I2C1_CONCLR_I2ENC_Msk (0x01UL << I2C1_CONCLR_I2ENC_Pos) /*!< I2C1 CONCLR: I2ENC Mask */
+
+// --------------------------------------- I2C1_MMCTRL ------------------------------------------
+#define I2C1_MMCTRL_MM_ENA_Pos 0 /*!< I2C1 MMCTRL: MM_ENA Position */
+#define I2C1_MMCTRL_MM_ENA_Msk (0x01UL << I2C1_MMCTRL_MM_ENA_Pos) /*!< I2C1 MMCTRL: MM_ENA Mask */
+#define I2C1_MMCTRL_ENA_SCL_Pos 1 /*!< I2C1 MMCTRL: ENA_SCL Position */
+#define I2C1_MMCTRL_ENA_SCL_Msk (0x01UL << I2C1_MMCTRL_ENA_SCL_Pos) /*!< I2C1 MMCTRL: ENA_SCL Mask */
+#define I2C1_MMCTRL_MATCH_ALL_Pos 2 /*!< I2C1 MMCTRL: MATCH_ALL Position */
+#define I2C1_MMCTRL_MATCH_ALL_Msk (0x01UL << I2C1_MMCTRL_MATCH_ALL_Pos) /*!< I2C1 MMCTRL: MATCH_ALL Mask */
+
+// ---------------------------------------- I2C1_ADR1 -------------------------------------------
+#define I2C1_ADR1_GC_Pos 0 /*!< I2C1 ADR1: GC Position */
+#define I2C1_ADR1_GC_Msk (0x01UL << I2C1_ADR1_GC_Pos) /*!< I2C1 ADR1: GC Mask */
+#define I2C1_ADR1_Address_Pos 1 /*!< I2C1 ADR1: Address Position */
+#define I2C1_ADR1_Address_Msk (0x7fUL << I2C1_ADR1_Address_Pos) /*!< I2C1 ADR1: Address Mask */
+
+// ---------------------------------------- I2C1_ADR2 -------------------------------------------
+#define I2C1_ADR2_GC_Pos 0 /*!< I2C1 ADR2: GC Position */
+#define I2C1_ADR2_GC_Msk (0x01UL << I2C1_ADR2_GC_Pos) /*!< I2C1 ADR2: GC Mask */
+#define I2C1_ADR2_Address_Pos 1 /*!< I2C1 ADR2: Address Position */
+#define I2C1_ADR2_Address_Msk (0x7fUL << I2C1_ADR2_Address_Pos) /*!< I2C1 ADR2: Address Mask */
+
+// ---------------------------------------- I2C1_ADR3 -------------------------------------------
+#define I2C1_ADR3_GC_Pos 0 /*!< I2C1 ADR3: GC Position */
+#define I2C1_ADR3_GC_Msk (0x01UL << I2C1_ADR3_GC_Pos) /*!< I2C1 ADR3: GC Mask */
+#define I2C1_ADR3_Address_Pos 1 /*!< I2C1 ADR3: Address Position */
+#define I2C1_ADR3_Address_Msk (0x7fUL << I2C1_ADR3_Address_Pos) /*!< I2C1 ADR3: Address Mask */
+
+// ------------------------------------ I2C1_DATA_BUFFER ----------------------------------------
+#define I2C1_DATA_BUFFER_Data_Pos 0 /*!< I2C1 DATA_BUFFER: Data Position */
+#define I2C1_DATA_BUFFER_Data_Msk (0x000000ffUL << I2C1_DATA_BUFFER_Data_Pos) /*!< I2C1 DATA_BUFFER: Data Mask */
+
+// --------------------------------------- I2C1_MASK0 -------------------------------------------
+#define I2C1_MASK0_MASK_Pos 1 /*!< I2C1 MASK0: MASK Position */
+#define I2C1_MASK0_MASK_Msk (0x7fUL << I2C1_MASK0_MASK_Pos) /*!< I2C1 MASK0: MASK Mask */
+
+// --------------------------------------- I2C1_MASK1 -------------------------------------------
+#define I2C1_MASK1_MASK_Pos 1 /*!< I2C1 MASK1: MASK Position */
+#define I2C1_MASK1_MASK_Msk (0x7fUL << I2C1_MASK1_MASK_Pos) /*!< I2C1 MASK1: MASK Mask */
+
+// --------------------------------------- I2C1_MASK2 -------------------------------------------
+#define I2C1_MASK2_MASK_Pos 1 /*!< I2C1 MASK2: MASK Position */
+#define I2C1_MASK2_MASK_Msk (0x7fUL << I2C1_MASK2_MASK_Pos) /*!< I2C1 MASK2: MASK Mask */
+
+// --------------------------------------- I2C1_MASK3 -------------------------------------------
+#define I2C1_MASK3_MASK_Pos 1 /*!< I2C1 MASK3: MASK Position */
+#define I2C1_MASK3_MASK_Msk (0x7fUL << I2C1_MASK3_MASK_Pos) /*!< I2C1 MASK3: MASK Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- I2S0 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------- I2S0_DAO --------------------------------------------
+#define I2S0_DAO_WORDWIDTH_Pos 0 /*!< I2S0 DAO: WORDWIDTH Position */
+#define I2S0_DAO_WORDWIDTH_Msk (0x03UL << I2S0_DAO_WORDWIDTH_Pos) /*!< I2S0 DAO: WORDWIDTH Mask */
+#define I2S0_DAO_MONO_Pos 2 /*!< I2S0 DAO: MONO Position */
+#define I2S0_DAO_MONO_Msk (0x01UL << I2S0_DAO_MONO_Pos) /*!< I2S0 DAO: MONO Mask */
+#define I2S0_DAO_STOP_Pos 3 /*!< I2S0 DAO: STOP Position */
+#define I2S0_DAO_STOP_Msk (0x01UL << I2S0_DAO_STOP_Pos) /*!< I2S0 DAO: STOP Mask */
+#define I2S0_DAO_RESET_Pos 4 /*!< I2S0 DAO: RESET Position */
+#define I2S0_DAO_RESET_Msk (0x01UL << I2S0_DAO_RESET_Pos) /*!< I2S0 DAO: RESET Mask */
+#define I2S0_DAO_WS_SEL_Pos 5 /*!< I2S0 DAO: WS_SEL Position */
+#define I2S0_DAO_WS_SEL_Msk (0x01UL << I2S0_DAO_WS_SEL_Pos) /*!< I2S0 DAO: WS_SEL Mask */
+#define I2S0_DAO_WS_HALFPERIOD_Pos 6 /*!< I2S0 DAO: WS_HALFPERIOD Position */
+#define I2S0_DAO_WS_HALFPERIOD_Msk (0x000001ffUL << I2S0_DAO_WS_HALFPERIOD_Pos) /*!< I2S0 DAO: WS_HALFPERIOD Mask */
+#define I2S0_DAO_MUTE_Pos 15 /*!< I2S0 DAO: MUTE Position */
+#define I2S0_DAO_MUTE_Msk (0x01UL << I2S0_DAO_MUTE_Pos) /*!< I2S0 DAO: MUTE Mask */
+
+// ---------------------------------------- I2S0_DAI --------------------------------------------
+#define I2S0_DAI_WORDWIDTH_Pos 0 /*!< I2S0 DAI: WORDWIDTH Position */
+#define I2S0_DAI_WORDWIDTH_Msk (0x03UL << I2S0_DAI_WORDWIDTH_Pos) /*!< I2S0 DAI: WORDWIDTH Mask */
+#define I2S0_DAI_MONO_Pos 2 /*!< I2S0 DAI: MONO Position */
+#define I2S0_DAI_MONO_Msk (0x01UL << I2S0_DAI_MONO_Pos) /*!< I2S0 DAI: MONO Mask */
+#define I2S0_DAI_STOP_Pos 3 /*!< I2S0 DAI: STOP Position */
+#define I2S0_DAI_STOP_Msk (0x01UL << I2S0_DAI_STOP_Pos) /*!< I2S0 DAI: STOP Mask */
+#define I2S0_DAI_RESET_Pos 4 /*!< I2S0 DAI: RESET Position */
+#define I2S0_DAI_RESET_Msk (0x01UL << I2S0_DAI_RESET_Pos) /*!< I2S0 DAI: RESET Mask */
+#define I2S0_DAI_WS_SEL_Pos 5 /*!< I2S0 DAI: WS_SEL Position */
+#define I2S0_DAI_WS_SEL_Msk (0x01UL << I2S0_DAI_WS_SEL_Pos) /*!< I2S0 DAI: WS_SEL Mask */
+#define I2S0_DAI_WS_HALFPERIOD_Pos 6 /*!< I2S0 DAI: WS_HALFPERIOD Position */
+#define I2S0_DAI_WS_HALFPERIOD_Msk (0x000001ffUL << I2S0_DAI_WS_HALFPERIOD_Pos) /*!< I2S0 DAI: WS_HALFPERIOD Mask */
+
+// --------------------------------------- I2S0_TXFIFO ------------------------------------------
+#define I2S0_TXFIFO_I2STXFIFO_Pos 0 /*!< I2S0 TXFIFO: I2STXFIFO Position */
+#define I2S0_TXFIFO_I2STXFIFO_Msk (0xffffffffUL << I2S0_TXFIFO_I2STXFIFO_Pos) /*!< I2S0 TXFIFO: I2STXFIFO Mask */
+
+// --------------------------------------- I2S0_RXFIFO ------------------------------------------
+#define I2S0_RXFIFO_I2SRXFIFO_Pos 0 /*!< I2S0 RXFIFO: I2SRXFIFO Position */
+#define I2S0_RXFIFO_I2SRXFIFO_Msk (0xffffffffUL << I2S0_RXFIFO_I2SRXFIFO_Pos) /*!< I2S0 RXFIFO: I2SRXFIFO Mask */
+
+// --------------------------------------- I2S0_STATE -------------------------------------------
+#define I2S0_STATE_IRQ_Pos 0 /*!< I2S0 STATE: IRQ Position */
+#define I2S0_STATE_IRQ_Msk (0x01UL << I2S0_STATE_IRQ_Pos) /*!< I2S0 STATE: IRQ Mask */
+#define I2S0_STATE_DMAREQ1_Pos 1 /*!< I2S0 STATE: DMAREQ1 Position */
+#define I2S0_STATE_DMAREQ1_Msk (0x01UL << I2S0_STATE_DMAREQ1_Pos) /*!< I2S0 STATE: DMAREQ1 Mask */
+#define I2S0_STATE_DMAREQ2_Pos 2 /*!< I2S0 STATE: DMAREQ2 Position */
+#define I2S0_STATE_DMAREQ2_Msk (0x01UL << I2S0_STATE_DMAREQ2_Pos) /*!< I2S0 STATE: DMAREQ2 Mask */
+#define I2S0_STATE_RX_LEVEL_Pos 8 /*!< I2S0 STATE: RX_LEVEL Position */
+#define I2S0_STATE_RX_LEVEL_Msk (0x0fUL << I2S0_STATE_RX_LEVEL_Pos) /*!< I2S0 STATE: RX_LEVEL Mask */
+#define I2S0_STATE_TX_LEVEL_Pos 16 /*!< I2S0 STATE: TX_LEVEL Position */
+#define I2S0_STATE_TX_LEVEL_Msk (0x0fUL << I2S0_STATE_TX_LEVEL_Pos) /*!< I2S0 STATE: TX_LEVEL Mask */
+
+// ---------------------------------------- I2S0_DMA1 -------------------------------------------
+#define I2S0_DMA1_RX_DMA1_ENABLE_Pos 0 /*!< I2S0 DMA1: RX_DMA1_ENABLE Position */
+#define I2S0_DMA1_RX_DMA1_ENABLE_Msk (0x01UL << I2S0_DMA1_RX_DMA1_ENABLE_Pos) /*!< I2S0 DMA1: RX_DMA1_ENABLE Mask */
+#define I2S0_DMA1_TX_DMA1_ENABLE_Pos 1 /*!< I2S0 DMA1: TX_DMA1_ENABLE Position */
+#define I2S0_DMA1_TX_DMA1_ENABLE_Msk (0x01UL << I2S0_DMA1_TX_DMA1_ENABLE_Pos) /*!< I2S0 DMA1: TX_DMA1_ENABLE Mask */
+#define I2S0_DMA1_RX_DEPTH_DMA1_Pos 8 /*!< I2S0 DMA1: RX_DEPTH_DMA1 Position */
+#define I2S0_DMA1_RX_DEPTH_DMA1_Msk (0x0fUL << I2S0_DMA1_RX_DEPTH_DMA1_Pos) /*!< I2S0 DMA1: RX_DEPTH_DMA1 Mask */
+#define I2S0_DMA1_TX_DEPTH_DMA1_Pos 16 /*!< I2S0 DMA1: TX_DEPTH_DMA1 Position */
+#define I2S0_DMA1_TX_DEPTH_DMA1_Msk (0x0fUL << I2S0_DMA1_TX_DEPTH_DMA1_Pos) /*!< I2S0 DMA1: TX_DEPTH_DMA1 Mask */
+
+// ---------------------------------------- I2S0_DMA2 -------------------------------------------
+#define I2S0_DMA2_RX_DMA2_ENABLE_Pos 0 /*!< I2S0 DMA2: RX_DMA2_ENABLE Position */
+#define I2S0_DMA2_RX_DMA2_ENABLE_Msk (0x01UL << I2S0_DMA2_RX_DMA2_ENABLE_Pos) /*!< I2S0 DMA2: RX_DMA2_ENABLE Mask */
+#define I2S0_DMA2_TX_DMA2_ENABLE_Pos 1 /*!< I2S0 DMA2: TX_DMA2_ENABLE Position */
+#define I2S0_DMA2_TX_DMA2_ENABLE_Msk (0x01UL << I2S0_DMA2_TX_DMA2_ENABLE_Pos) /*!< I2S0 DMA2: TX_DMA2_ENABLE Mask */
+#define I2S0_DMA2_RX_DEPTH_DMA2_Pos 8 /*!< I2S0 DMA2: RX_DEPTH_DMA2 Position */
+#define I2S0_DMA2_RX_DEPTH_DMA2_Msk (0x0fUL << I2S0_DMA2_RX_DEPTH_DMA2_Pos) /*!< I2S0 DMA2: RX_DEPTH_DMA2 Mask */
+#define I2S0_DMA2_TX_DEPTH_DMA2_Pos 16 /*!< I2S0 DMA2: TX_DEPTH_DMA2 Position */
+#define I2S0_DMA2_TX_DEPTH_DMA2_Msk (0x0fUL << I2S0_DMA2_TX_DEPTH_DMA2_Pos) /*!< I2S0 DMA2: TX_DEPTH_DMA2 Mask */
+
+// ---------------------------------------- I2S0_IRQ --------------------------------------------
+#define I2S0_IRQ_RX_IRQ_ENABLE_Pos 0 /*!< I2S0 IRQ: RX_IRQ_ENABLE Position */
+#define I2S0_IRQ_RX_IRQ_ENABLE_Msk (0x01UL << I2S0_IRQ_RX_IRQ_ENABLE_Pos) /*!< I2S0 IRQ: RX_IRQ_ENABLE Mask */
+#define I2S0_IRQ_TX_IRQ_ENABLE_Pos 1 /*!< I2S0 IRQ: TX_IRQ_ENABLE Position */
+#define I2S0_IRQ_TX_IRQ_ENABLE_Msk (0x01UL << I2S0_IRQ_TX_IRQ_ENABLE_Pos) /*!< I2S0 IRQ: TX_IRQ_ENABLE Mask */
+#define I2S0_IRQ_RX_DEPTH_IRQ_Pos 8 /*!< I2S0 IRQ: RX_DEPTH_IRQ Position */
+#define I2S0_IRQ_RX_DEPTH_IRQ_Msk (0x0fUL << I2S0_IRQ_RX_DEPTH_IRQ_Pos) /*!< I2S0 IRQ: RX_DEPTH_IRQ Mask */
+#define I2S0_IRQ_TX_DEPTH_IRQ_Pos 16 /*!< I2S0 IRQ: TX_DEPTH_IRQ Position */
+#define I2S0_IRQ_TX_DEPTH_IRQ_Msk (0x0fUL << I2S0_IRQ_TX_DEPTH_IRQ_Pos) /*!< I2S0 IRQ: TX_DEPTH_IRQ Mask */
+
+// --------------------------------------- I2S0_TXRATE ------------------------------------------
+#define I2S0_TXRATE_Y_DIVIDER_Pos 0 /*!< I2S0 TXRATE: Y_DIVIDER Position */
+#define I2S0_TXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2S0_TXRATE_Y_DIVIDER_Pos) /*!< I2S0 TXRATE: Y_DIVIDER Mask */
+#define I2S0_TXRATE_X_DIVIDER_Pos 8 /*!< I2S0 TXRATE: X_DIVIDER Position */
+#define I2S0_TXRATE_X_DIVIDER_Msk (0x000000ffUL << I2S0_TXRATE_X_DIVIDER_Pos) /*!< I2S0 TXRATE: X_DIVIDER Mask */
+
+// --------------------------------------- I2S0_RXRATE ------------------------------------------
+#define I2S0_RXRATE_Y_DIVIDER_Pos 0 /*!< I2S0 RXRATE: Y_DIVIDER Position */
+#define I2S0_RXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2S0_RXRATE_Y_DIVIDER_Pos) /*!< I2S0 RXRATE: Y_DIVIDER Mask */
+#define I2S0_RXRATE_X_DIVIDER_Pos 8 /*!< I2S0 RXRATE: X_DIVIDER Position */
+#define I2S0_RXRATE_X_DIVIDER_Msk (0x000000ffUL << I2S0_RXRATE_X_DIVIDER_Pos) /*!< I2S0 RXRATE: X_DIVIDER Mask */
+
+// ------------------------------------- I2S0_TXBITRATE -----------------------------------------
+#define I2S0_TXBITRATE_TX_BITRATE_Pos 0 /*!< I2S0 TXBITRATE: TX_BITRATE Position */
+#define I2S0_TXBITRATE_TX_BITRATE_Msk (0x3fUL << I2S0_TXBITRATE_TX_BITRATE_Pos) /*!< I2S0 TXBITRATE: TX_BITRATE Mask */
+
+// ------------------------------------- I2S0_RXBITRATE -----------------------------------------
+#define I2S0_RXBITRATE_RX_BITRATE_Pos 0 /*!< I2S0 RXBITRATE: RX_BITRATE Position */
+#define I2S0_RXBITRATE_RX_BITRATE_Msk (0x3fUL << I2S0_RXBITRATE_RX_BITRATE_Pos) /*!< I2S0 RXBITRATE: RX_BITRATE Mask */
+
+// --------------------------------------- I2S0_TXMODE ------------------------------------------
+#define I2S0_TXMODE_TXCLKSEL_Pos 0 /*!< I2S0 TXMODE: TXCLKSEL Position */
+#define I2S0_TXMODE_TXCLKSEL_Msk (0x03UL << I2S0_TXMODE_TXCLKSEL_Pos) /*!< I2S0 TXMODE: TXCLKSEL Mask */
+#define I2S0_TXMODE_TX4PIN_Pos 2 /*!< I2S0 TXMODE: TX4PIN Position */
+#define I2S0_TXMODE_TX4PIN_Msk (0x01UL << I2S0_TXMODE_TX4PIN_Pos) /*!< I2S0 TXMODE: TX4PIN Mask */
+#define I2S0_TXMODE_TXMCENA_Pos 3 /*!< I2S0 TXMODE: TXMCENA Position */
+#define I2S0_TXMODE_TXMCENA_Msk (0x01UL << I2S0_TXMODE_TXMCENA_Pos) /*!< I2S0 TXMODE: TXMCENA Mask */
+
+// --------------------------------------- I2S0_RXMODE ------------------------------------------
+#define I2S0_RXMODE_RXCLKSEL_Pos 0 /*!< I2S0 RXMODE: RXCLKSEL Position */
+#define I2S0_RXMODE_RXCLKSEL_Msk (0x03UL << I2S0_RXMODE_RXCLKSEL_Pos) /*!< I2S0 RXMODE: RXCLKSEL Mask */
+#define I2S0_RXMODE_RX4PIN_Pos 2 /*!< I2S0 RXMODE: RX4PIN Position */
+#define I2S0_RXMODE_RX4PIN_Msk (0x01UL << I2S0_RXMODE_RX4PIN_Pos) /*!< I2S0 RXMODE: RX4PIN Mask */
+#define I2S0_RXMODE_RXMCENA_Pos 3 /*!< I2S0 RXMODE: RXMCENA Position */
+#define I2S0_RXMODE_RXMCENA_Msk (0x01UL << I2S0_RXMODE_RXMCENA_Pos) /*!< I2S0 RXMODE: RXMCENA Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- I2S1 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ---------------------------------------- I2S1_DAO --------------------------------------------
+#define I2S1_DAO_WORDWIDTH_Pos 0 /*!< I2S1 DAO: WORDWIDTH Position */
+#define I2S1_DAO_WORDWIDTH_Msk (0x03UL << I2S1_DAO_WORDWIDTH_Pos) /*!< I2S1 DAO: WORDWIDTH Mask */
+#define I2S1_DAO_MONO_Pos 2 /*!< I2S1 DAO: MONO Position */
+#define I2S1_DAO_MONO_Msk (0x01UL << I2S1_DAO_MONO_Pos) /*!< I2S1 DAO: MONO Mask */
+#define I2S1_DAO_STOP_Pos 3 /*!< I2S1 DAO: STOP Position */
+#define I2S1_DAO_STOP_Msk (0x01UL << I2S1_DAO_STOP_Pos) /*!< I2S1 DAO: STOP Mask */
+#define I2S1_DAO_RESET_Pos 4 /*!< I2S1 DAO: RESET Position */
+#define I2S1_DAO_RESET_Msk (0x01UL << I2S1_DAO_RESET_Pos) /*!< I2S1 DAO: RESET Mask */
+#define I2S1_DAO_WS_SEL_Pos 5 /*!< I2S1 DAO: WS_SEL Position */
+#define I2S1_DAO_WS_SEL_Msk (0x01UL << I2S1_DAO_WS_SEL_Pos) /*!< I2S1 DAO: WS_SEL Mask */
+#define I2S1_DAO_WS_HALFPERIOD_Pos 6 /*!< I2S1 DAO: WS_HALFPERIOD Position */
+#define I2S1_DAO_WS_HALFPERIOD_Msk (0x000001ffUL << I2S1_DAO_WS_HALFPERIOD_Pos) /*!< I2S1 DAO: WS_HALFPERIOD Mask */
+#define I2S1_DAO_MUTE_Pos 15 /*!< I2S1 DAO: MUTE Position */
+#define I2S1_DAO_MUTE_Msk (0x01UL << I2S1_DAO_MUTE_Pos) /*!< I2S1 DAO: MUTE Mask */
+
+// ---------------------------------------- I2S1_DAI --------------------------------------------
+#define I2S1_DAI_WORDWIDTH_Pos 0 /*!< I2S1 DAI: WORDWIDTH Position */
+#define I2S1_DAI_WORDWIDTH_Msk (0x03UL << I2S1_DAI_WORDWIDTH_Pos) /*!< I2S1 DAI: WORDWIDTH Mask */
+#define I2S1_DAI_MONO_Pos 2 /*!< I2S1 DAI: MONO Position */
+#define I2S1_DAI_MONO_Msk (0x01UL << I2S1_DAI_MONO_Pos) /*!< I2S1 DAI: MONO Mask */
+#define I2S1_DAI_STOP_Pos 3 /*!< I2S1 DAI: STOP Position */
+#define I2S1_DAI_STOP_Msk (0x01UL << I2S1_DAI_STOP_Pos) /*!< I2S1 DAI: STOP Mask */
+#define I2S1_DAI_RESET_Pos 4 /*!< I2S1 DAI: RESET Position */
+#define I2S1_DAI_RESET_Msk (0x01UL << I2S1_DAI_RESET_Pos) /*!< I2S1 DAI: RESET Mask */
+#define I2S1_DAI_WS_SEL_Pos 5 /*!< I2S1 DAI: WS_SEL Position */
+#define I2S1_DAI_WS_SEL_Msk (0x01UL << I2S1_DAI_WS_SEL_Pos) /*!< I2S1 DAI: WS_SEL Mask */
+#define I2S1_DAI_WS_HALFPERIOD_Pos 6 /*!< I2S1 DAI: WS_HALFPERIOD Position */
+#define I2S1_DAI_WS_HALFPERIOD_Msk (0x000001ffUL << I2S1_DAI_WS_HALFPERIOD_Pos) /*!< I2S1 DAI: WS_HALFPERIOD Mask */
+
+// --------------------------------------- I2S1_TXFIFO ------------------------------------------
+#define I2S1_TXFIFO_I2STXFIFO_Pos 0 /*!< I2S1 TXFIFO: I2STXFIFO Position */
+#define I2S1_TXFIFO_I2STXFIFO_Msk (0xffffffffUL << I2S1_TXFIFO_I2STXFIFO_Pos) /*!< I2S1 TXFIFO: I2STXFIFO Mask */
+
+// --------------------------------------- I2S1_RXFIFO ------------------------------------------
+#define I2S1_RXFIFO_I2SRXFIFO_Pos 0 /*!< I2S1 RXFIFO: I2SRXFIFO Position */
+#define I2S1_RXFIFO_I2SRXFIFO_Msk (0xffffffffUL << I2S1_RXFIFO_I2SRXFIFO_Pos) /*!< I2S1 RXFIFO: I2SRXFIFO Mask */
+
+// --------------------------------------- I2S1_STATE -------------------------------------------
+#define I2S1_STATE_IRQ_Pos 0 /*!< I2S1 STATE: IRQ Position */
+#define I2S1_STATE_IRQ_Msk (0x01UL << I2S1_STATE_IRQ_Pos) /*!< I2S1 STATE: IRQ Mask */
+#define I2S1_STATE_DMAREQ1_Pos 1 /*!< I2S1 STATE: DMAREQ1 Position */
+#define I2S1_STATE_DMAREQ1_Msk (0x01UL << I2S1_STATE_DMAREQ1_Pos) /*!< I2S1 STATE: DMAREQ1 Mask */
+#define I2S1_STATE_DMAREQ2_Pos 2 /*!< I2S1 STATE: DMAREQ2 Position */
+#define I2S1_STATE_DMAREQ2_Msk (0x01UL << I2S1_STATE_DMAREQ2_Pos) /*!< I2S1 STATE: DMAREQ2 Mask */
+#define I2S1_STATE_RX_LEVEL_Pos 8 /*!< I2S1 STATE: RX_LEVEL Position */
+#define I2S1_STATE_RX_LEVEL_Msk (0x0fUL << I2S1_STATE_RX_LEVEL_Pos) /*!< I2S1 STATE: RX_LEVEL Mask */
+#define I2S1_STATE_TX_LEVEL_Pos 16 /*!< I2S1 STATE: TX_LEVEL Position */
+#define I2S1_STATE_TX_LEVEL_Msk (0x0fUL << I2S1_STATE_TX_LEVEL_Pos) /*!< I2S1 STATE: TX_LEVEL Mask */
+
+// ---------------------------------------- I2S1_DMA1 -------------------------------------------
+#define I2S1_DMA1_RX_DMA1_ENABLE_Pos 0 /*!< I2S1 DMA1: RX_DMA1_ENABLE Position */
+#define I2S1_DMA1_RX_DMA1_ENABLE_Msk (0x01UL << I2S1_DMA1_RX_DMA1_ENABLE_Pos) /*!< I2S1 DMA1: RX_DMA1_ENABLE Mask */
+#define I2S1_DMA1_TX_DMA1_ENABLE_Pos 1 /*!< I2S1 DMA1: TX_DMA1_ENABLE Position */
+#define I2S1_DMA1_TX_DMA1_ENABLE_Msk (0x01UL << I2S1_DMA1_TX_DMA1_ENABLE_Pos) /*!< I2S1 DMA1: TX_DMA1_ENABLE Mask */
+#define I2S1_DMA1_RX_DEPTH_DMA1_Pos 8 /*!< I2S1 DMA1: RX_DEPTH_DMA1 Position */
+#define I2S1_DMA1_RX_DEPTH_DMA1_Msk (0x0fUL << I2S1_DMA1_RX_DEPTH_DMA1_Pos) /*!< I2S1 DMA1: RX_DEPTH_DMA1 Mask */
+#define I2S1_DMA1_TX_DEPTH_DMA1_Pos 16 /*!< I2S1 DMA1: TX_DEPTH_DMA1 Position */
+#define I2S1_DMA1_TX_DEPTH_DMA1_Msk (0x0fUL << I2S1_DMA1_TX_DEPTH_DMA1_Pos) /*!< I2S1 DMA1: TX_DEPTH_DMA1 Mask */
+
+// ---------------------------------------- I2S1_DMA2 -------------------------------------------
+#define I2S1_DMA2_RX_DMA2_ENABLE_Pos 0 /*!< I2S1 DMA2: RX_DMA2_ENABLE Position */
+#define I2S1_DMA2_RX_DMA2_ENABLE_Msk (0x01UL << I2S1_DMA2_RX_DMA2_ENABLE_Pos) /*!< I2S1 DMA2: RX_DMA2_ENABLE Mask */
+#define I2S1_DMA2_TX_DMA2_ENABLE_Pos 1 /*!< I2S1 DMA2: TX_DMA2_ENABLE Position */
+#define I2S1_DMA2_TX_DMA2_ENABLE_Msk (0x01UL << I2S1_DMA2_TX_DMA2_ENABLE_Pos) /*!< I2S1 DMA2: TX_DMA2_ENABLE Mask */
+#define I2S1_DMA2_RX_DEPTH_DMA2_Pos 8 /*!< I2S1 DMA2: RX_DEPTH_DMA2 Position */
+#define I2S1_DMA2_RX_DEPTH_DMA2_Msk (0x0fUL << I2S1_DMA2_RX_DEPTH_DMA2_Pos) /*!< I2S1 DMA2: RX_DEPTH_DMA2 Mask */
+#define I2S1_DMA2_TX_DEPTH_DMA2_Pos 16 /*!< I2S1 DMA2: TX_DEPTH_DMA2 Position */
+#define I2S1_DMA2_TX_DEPTH_DMA2_Msk (0x0fUL << I2S1_DMA2_TX_DEPTH_DMA2_Pos) /*!< I2S1 DMA2: TX_DEPTH_DMA2 Mask */
+
+// ---------------------------------------- I2S1_IRQ --------------------------------------------
+#define I2S1_IRQ_RX_IRQ_ENABLE_Pos 0 /*!< I2S1 IRQ: RX_IRQ_ENABLE Position */
+#define I2S1_IRQ_RX_IRQ_ENABLE_Msk (0x01UL << I2S1_IRQ_RX_IRQ_ENABLE_Pos) /*!< I2S1 IRQ: RX_IRQ_ENABLE Mask */
+#define I2S1_IRQ_TX_IRQ_ENABLE_Pos 1 /*!< I2S1 IRQ: TX_IRQ_ENABLE Position */
+#define I2S1_IRQ_TX_IRQ_ENABLE_Msk (0x01UL << I2S1_IRQ_TX_IRQ_ENABLE_Pos) /*!< I2S1 IRQ: TX_IRQ_ENABLE Mask */
+#define I2S1_IRQ_RX_DEPTH_IRQ_Pos 8 /*!< I2S1 IRQ: RX_DEPTH_IRQ Position */
+#define I2S1_IRQ_RX_DEPTH_IRQ_Msk (0x0fUL << I2S1_IRQ_RX_DEPTH_IRQ_Pos) /*!< I2S1 IRQ: RX_DEPTH_IRQ Mask */
+#define I2S1_IRQ_TX_DEPTH_IRQ_Pos 16 /*!< I2S1 IRQ: TX_DEPTH_IRQ Position */
+#define I2S1_IRQ_TX_DEPTH_IRQ_Msk (0x0fUL << I2S1_IRQ_TX_DEPTH_IRQ_Pos) /*!< I2S1 IRQ: TX_DEPTH_IRQ Mask */
+
+// --------------------------------------- I2S1_TXRATE ------------------------------------------
+#define I2S1_TXRATE_Y_DIVIDER_Pos 0 /*!< I2S1 TXRATE: Y_DIVIDER Position */
+#define I2S1_TXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2S1_TXRATE_Y_DIVIDER_Pos) /*!< I2S1 TXRATE: Y_DIVIDER Mask */
+#define I2S1_TXRATE_X_DIVIDER_Pos 8 /*!< I2S1 TXRATE: X_DIVIDER Position */
+#define I2S1_TXRATE_X_DIVIDER_Msk (0x000000ffUL << I2S1_TXRATE_X_DIVIDER_Pos) /*!< I2S1 TXRATE: X_DIVIDER Mask */
+
+// --------------------------------------- I2S1_RXRATE ------------------------------------------
+#define I2S1_RXRATE_Y_DIVIDER_Pos 0 /*!< I2S1 RXRATE: Y_DIVIDER Position */
+#define I2S1_RXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2S1_RXRATE_Y_DIVIDER_Pos) /*!< I2S1 RXRATE: Y_DIVIDER Mask */
+#define I2S1_RXRATE_X_DIVIDER_Pos 8 /*!< I2S1 RXRATE: X_DIVIDER Position */
+#define I2S1_RXRATE_X_DIVIDER_Msk (0x000000ffUL << I2S1_RXRATE_X_DIVIDER_Pos) /*!< I2S1 RXRATE: X_DIVIDER Mask */
+
+// ------------------------------------- I2S1_TXBITRATE -----------------------------------------
+#define I2S1_TXBITRATE_TX_BITRATE_Pos 0 /*!< I2S1 TXBITRATE: TX_BITRATE Position */
+#define I2S1_TXBITRATE_TX_BITRATE_Msk (0x3fUL << I2S1_TXBITRATE_TX_BITRATE_Pos) /*!< I2S1 TXBITRATE: TX_BITRATE Mask */
+
+// ------------------------------------- I2S1_RXBITRATE -----------------------------------------
+#define I2S1_RXBITRATE_RX_BITRATE_Pos 0 /*!< I2S1 RXBITRATE: RX_BITRATE Position */
+#define I2S1_RXBITRATE_RX_BITRATE_Msk (0x3fUL << I2S1_RXBITRATE_RX_BITRATE_Pos) /*!< I2S1 RXBITRATE: RX_BITRATE Mask */
+
+// --------------------------------------- I2S1_TXMODE ------------------------------------------
+#define I2S1_TXMODE_TXCLKSEL_Pos 0 /*!< I2S1 TXMODE: TXCLKSEL Position */
+#define I2S1_TXMODE_TXCLKSEL_Msk (0x03UL << I2S1_TXMODE_TXCLKSEL_Pos) /*!< I2S1 TXMODE: TXCLKSEL Mask */
+#define I2S1_TXMODE_TX4PIN_Pos 2 /*!< I2S1 TXMODE: TX4PIN Position */
+#define I2S1_TXMODE_TX4PIN_Msk (0x01UL << I2S1_TXMODE_TX4PIN_Pos) /*!< I2S1 TXMODE: TX4PIN Mask */
+#define I2S1_TXMODE_TXMCENA_Pos 3 /*!< I2S1 TXMODE: TXMCENA Position */
+#define I2S1_TXMODE_TXMCENA_Msk (0x01UL << I2S1_TXMODE_TXMCENA_Pos) /*!< I2S1 TXMODE: TXMCENA Mask */
+
+// --------------------------------------- I2S1_RXMODE ------------------------------------------
+#define I2S1_RXMODE_RXCLKSEL_Pos 0 /*!< I2S1 RXMODE: RXCLKSEL Position */
+#define I2S1_RXMODE_RXCLKSEL_Msk (0x03UL << I2S1_RXMODE_RXCLKSEL_Pos) /*!< I2S1 RXMODE: RXCLKSEL Mask */
+#define I2S1_RXMODE_RX4PIN_Pos 2 /*!< I2S1 RXMODE: RX4PIN Position */
+#define I2S1_RXMODE_RX4PIN_Msk (0x01UL << I2S1_RXMODE_RX4PIN_Pos) /*!< I2S1 RXMODE: RX4PIN Mask */
+#define I2S1_RXMODE_RXMCENA_Pos 3 /*!< I2S1 RXMODE: RXMCENA Position */
+#define I2S1_RXMODE_RXMCENA_Msk (0x01UL << I2S1_RXMODE_RXMCENA_Pos) /*!< I2S1 RXMODE: RXMCENA Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- C_CAN1 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------- C_CAN1_CNTL ------------------------------------------
+#define C_CAN1_CNTL_INIT_Pos 0 /*!< C_CAN1 CNTL: INIT Position */
+#define C_CAN1_CNTL_INIT_Msk (0x01UL << C_CAN1_CNTL_INIT_Pos) /*!< C_CAN1 CNTL: INIT Mask */
+#define C_CAN1_CNTL_IE_Pos 1 /*!< C_CAN1 CNTL: IE Position */
+#define C_CAN1_CNTL_IE_Msk (0x01UL << C_CAN1_CNTL_IE_Pos) /*!< C_CAN1 CNTL: IE Mask */
+#define C_CAN1_CNTL_SIE_Pos 2 /*!< C_CAN1 CNTL: SIE Position */
+#define C_CAN1_CNTL_SIE_Msk (0x01UL << C_CAN1_CNTL_SIE_Pos) /*!< C_CAN1 CNTL: SIE Mask */
+#define C_CAN1_CNTL_EIE_Pos 3 /*!< C_CAN1 CNTL: EIE Position */
+#define C_CAN1_CNTL_EIE_Msk (0x01UL << C_CAN1_CNTL_EIE_Pos) /*!< C_CAN1 CNTL: EIE Mask */
+#define C_CAN1_CNTL_DAR_Pos 5 /*!< C_CAN1 CNTL: DAR Position */
+#define C_CAN1_CNTL_DAR_Msk (0x01UL << C_CAN1_CNTL_DAR_Pos) /*!< C_CAN1 CNTL: DAR Mask */
+#define C_CAN1_CNTL_CCE_Pos 6 /*!< C_CAN1 CNTL: CCE Position */
+#define C_CAN1_CNTL_CCE_Msk (0x01UL << C_CAN1_CNTL_CCE_Pos) /*!< C_CAN1 CNTL: CCE Mask */
+#define C_CAN1_CNTL_TEST_Pos 7 /*!< C_CAN1 CNTL: TEST Position */
+#define C_CAN1_CNTL_TEST_Msk (0x01UL << C_CAN1_CNTL_TEST_Pos) /*!< C_CAN1 CNTL: TEST Mask */
+
+// --------------------------------------- C_CAN1_STAT ------------------------------------------
+#define C_CAN1_STAT_LEC_Pos 0 /*!< C_CAN1 STAT: LEC Position */
+#define C_CAN1_STAT_LEC_Msk (0x07UL << C_CAN1_STAT_LEC_Pos) /*!< C_CAN1 STAT: LEC Mask */
+#define C_CAN1_STAT_TXOK_Pos 3 /*!< C_CAN1 STAT: TXOK Position */
+#define C_CAN1_STAT_TXOK_Msk (0x01UL << C_CAN1_STAT_TXOK_Pos) /*!< C_CAN1 STAT: TXOK Mask */
+#define C_CAN1_STAT_RXOK_Pos 4 /*!< C_CAN1 STAT: RXOK Position */
+#define C_CAN1_STAT_RXOK_Msk (0x01UL << C_CAN1_STAT_RXOK_Pos) /*!< C_CAN1 STAT: RXOK Mask */
+#define C_CAN1_STAT_EPASS_Pos 5 /*!< C_CAN1 STAT: EPASS Position */
+#define C_CAN1_STAT_EPASS_Msk (0x01UL << C_CAN1_STAT_EPASS_Pos) /*!< C_CAN1 STAT: EPASS Mask */
+#define C_CAN1_STAT_EWARN_Pos 6 /*!< C_CAN1 STAT: EWARN Position */
+#define C_CAN1_STAT_EWARN_Msk (0x01UL << C_CAN1_STAT_EWARN_Pos) /*!< C_CAN1 STAT: EWARN Mask */
+#define C_CAN1_STAT_BOFF_Pos 7 /*!< C_CAN1 STAT: BOFF Position */
+#define C_CAN1_STAT_BOFF_Msk (0x01UL << C_CAN1_STAT_BOFF_Pos) /*!< C_CAN1 STAT: BOFF Mask */
+
+// ---------------------------------------- C_CAN1_EC -------------------------------------------
+#define C_CAN1_EC_TEC_7_0_Pos 0 /*!< C_CAN1 EC: TEC_7_0 Position */
+#define C_CAN1_EC_TEC_7_0_Msk (0x000000ffUL << C_CAN1_EC_TEC_7_0_Pos) /*!< C_CAN1 EC: TEC_7_0 Mask */
+#define C_CAN1_EC_REC_6_0_Pos 8 /*!< C_CAN1 EC: REC_6_0 Position */
+#define C_CAN1_EC_REC_6_0_Msk (0x7fUL << C_CAN1_EC_REC_6_0_Pos) /*!< C_CAN1 EC: REC_6_0 Mask */
+#define C_CAN1_EC_RP_Pos 15 /*!< C_CAN1 EC: RP Position */
+#define C_CAN1_EC_RP_Msk (0x01UL << C_CAN1_EC_RP_Pos) /*!< C_CAN1 EC: RP Mask */
+
+// ---------------------------------------- C_CAN1_BT -------------------------------------------
+#define C_CAN1_BT_BRP_Pos 0 /*!< C_CAN1 BT: BRP Position */
+#define C_CAN1_BT_BRP_Msk (0x3fUL << C_CAN1_BT_BRP_Pos) /*!< C_CAN1 BT: BRP Mask */
+#define C_CAN1_BT_SJW_Pos 6 /*!< C_CAN1 BT: SJW Position */
+#define C_CAN1_BT_SJW_Msk (0x03UL << C_CAN1_BT_SJW_Pos) /*!< C_CAN1 BT: SJW Mask */
+#define C_CAN1_BT_TSEG1_Pos 8 /*!< C_CAN1 BT: TSEG1 Position */
+#define C_CAN1_BT_TSEG1_Msk (0x0fUL << C_CAN1_BT_TSEG1_Pos) /*!< C_CAN1 BT: TSEG1 Mask */
+#define C_CAN1_BT_TSEG2_Pos 12 /*!< C_CAN1 BT: TSEG2 Position */
+#define C_CAN1_BT_TSEG2_Msk (0x07UL << C_CAN1_BT_TSEG2_Pos) /*!< C_CAN1 BT: TSEG2 Mask */
+
+// --------------------------------------- C_CAN1_INT -------------------------------------------
+#define C_CAN1_INT_INTID15_0_Pos 0 /*!< C_CAN1 INT: INTID15_0 Position */
+#define C_CAN1_INT_INTID15_0_Msk (0x0000ffffUL << C_CAN1_INT_INTID15_0_Pos) /*!< C_CAN1 INT: INTID15_0 Mask */
+
+// --------------------------------------- C_CAN1_TEST ------------------------------------------
+#define C_CAN1_TEST_BASIC_Pos 2 /*!< C_CAN1 TEST: BASIC Position */
+#define C_CAN1_TEST_BASIC_Msk (0x01UL << C_CAN1_TEST_BASIC_Pos) /*!< C_CAN1 TEST: BASIC Mask */
+#define C_CAN1_TEST_SILENT_Pos 3 /*!< C_CAN1 TEST: SILENT Position */
+#define C_CAN1_TEST_SILENT_Msk (0x01UL << C_CAN1_TEST_SILENT_Pos) /*!< C_CAN1 TEST: SILENT Mask */
+#define C_CAN1_TEST_LBACK_Pos 4 /*!< C_CAN1 TEST: LBACK Position */
+#define C_CAN1_TEST_LBACK_Msk (0x01UL << C_CAN1_TEST_LBACK_Pos) /*!< C_CAN1 TEST: LBACK Mask */
+#define C_CAN1_TEST_TX1_0_Pos 5 /*!< C_CAN1 TEST: TX1_0 Position */
+#define C_CAN1_TEST_TX1_0_Msk (0x03UL << C_CAN1_TEST_TX1_0_Pos) /*!< C_CAN1 TEST: TX1_0 Mask */
+#define C_CAN1_TEST_RX_Pos 7 /*!< C_CAN1 TEST: RX Position */
+#define C_CAN1_TEST_RX_Msk (0x01UL << C_CAN1_TEST_RX_Pos) /*!< C_CAN1 TEST: RX Mask */
+
+// --------------------------------------- C_CAN1_BRPE ------------------------------------------
+#define C_CAN1_BRPE_BRPE_Pos 0 /*!< C_CAN1 BRPE: BRPE Position */
+#define C_CAN1_BRPE_BRPE_Msk (0x0fUL << C_CAN1_BRPE_BRPE_Pos) /*!< C_CAN1 BRPE: BRPE Mask */
+
+// ------------------------------------ C_CAN1_IF1_CMDREQ ---------------------------------------
+#define C_CAN1_IF1_CMDREQ_MESSNUM_Pos 0 /*!< C_CAN1 IF1_CMDREQ: MESSNUM Position */
+#define C_CAN1_IF1_CMDREQ_MESSNUM_Msk (0x3fUL << C_CAN1_IF1_CMDREQ_MESSNUM_Pos) /*!< C_CAN1 IF1_CMDREQ: MESSNUM Mask */
+#define C_CAN1_IF1_CMDREQ_BUSY_Pos 15 /*!< C_CAN1 IF1_CMDREQ: BUSY Position */
+#define C_CAN1_IF1_CMDREQ_BUSY_Msk (0x01UL << C_CAN1_IF1_CMDREQ_BUSY_Pos) /*!< C_CAN1 IF1_CMDREQ: BUSY Mask */
+
+// ----------------------------------- C_CAN1_IF1_CMDMSK_W --------------------------------------
+#define C_CAN1_IF1_CMDMSK_W_DATA_B_Pos 0 /*!< C_CAN1 IF1_CMDMSK_W: DATA_B Position */
+#define C_CAN1_IF1_CMDMSK_W_DATA_B_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_DATA_B_Pos) /*!< C_CAN1 IF1_CMDMSK_W: DATA_B Mask */
+#define C_CAN1_IF1_CMDMSK_W_DATA_A_Pos 1 /*!< C_CAN1 IF1_CMDMSK_W: DATA_A Position */
+#define C_CAN1_IF1_CMDMSK_W_DATA_A_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_DATA_A_Pos) /*!< C_CAN1 IF1_CMDMSK_W: DATA_A Mask */
+#define C_CAN1_IF1_CMDMSK_W_TXRQST_Pos 2 /*!< C_CAN1 IF1_CMDMSK_W: TXRQST Position */
+#define C_CAN1_IF1_CMDMSK_W_TXRQST_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_TXRQST_Pos) /*!< C_CAN1 IF1_CMDMSK_W: TXRQST Mask */
+#define C_CAN1_IF1_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CAN1 IF1_CMDMSK_W: CLRINTPND Position */
+#define C_CAN1_IF1_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_CLRINTPND_Pos) /*!< C_CAN1 IF1_CMDMSK_W: CLRINTPND Mask */
+#define C_CAN1_IF1_CMDMSK_W_CTRL_Pos 4 /*!< C_CAN1 IF1_CMDMSK_W: CTRL Position */
+#define C_CAN1_IF1_CMDMSK_W_CTRL_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_CTRL_Pos) /*!< C_CAN1 IF1_CMDMSK_W: CTRL Mask */
+#define C_CAN1_IF1_CMDMSK_W_ARB_Pos 5 /*!< C_CAN1 IF1_CMDMSK_W: ARB Position */
+#define C_CAN1_IF1_CMDMSK_W_ARB_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_ARB_Pos) /*!< C_CAN1 IF1_CMDMSK_W: ARB Mask */
+#define C_CAN1_IF1_CMDMSK_W_MASK_Pos 6 /*!< C_CAN1 IF1_CMDMSK_W: MASK Position */
+#define C_CAN1_IF1_CMDMSK_W_MASK_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_MASK_Pos) /*!< C_CAN1 IF1_CMDMSK_W: MASK Mask */
+#define C_CAN1_IF1_CMDMSK_W_WR_RD_Pos 7 /*!< C_CAN1 IF1_CMDMSK_W: WR_RD Position */
+#define C_CAN1_IF1_CMDMSK_W_WR_RD_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_WR_RD_Pos) /*!< C_CAN1 IF1_CMDMSK_W: WR_RD Mask */
+
+// ----------------------------------- C_CAN1_IF1_CMDMSK_R --------------------------------------
+#define C_CAN1_IF1_CMDMSK_R_DATA_B_Pos 0 /*!< C_CAN1 IF1_CMDMSK_R: DATA_B Position */
+#define C_CAN1_IF1_CMDMSK_R_DATA_B_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_DATA_B_Pos) /*!< C_CAN1 IF1_CMDMSK_R: DATA_B Mask */
+#define C_CAN1_IF1_CMDMSK_R_DATA_A_Pos 1 /*!< C_CAN1 IF1_CMDMSK_R: DATA_A Position */
+#define C_CAN1_IF1_CMDMSK_R_DATA_A_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_DATA_A_Pos) /*!< C_CAN1 IF1_CMDMSK_R: DATA_A Mask */
+#define C_CAN1_IF1_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CAN1 IF1_CMDMSK_R: NEWDAT Position */
+#define C_CAN1_IF1_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_NEWDAT_Pos) /*!< C_CAN1 IF1_CMDMSK_R: NEWDAT Mask */
+#define C_CAN1_IF1_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CAN1 IF1_CMDMSK_R: CLRINTPND Position */
+#define C_CAN1_IF1_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_CLRINTPND_Pos) /*!< C_CAN1 IF1_CMDMSK_R: CLRINTPND Mask */
+#define C_CAN1_IF1_CMDMSK_R_CTRL_Pos 4 /*!< C_CAN1 IF1_CMDMSK_R: CTRL Position */
+#define C_CAN1_IF1_CMDMSK_R_CTRL_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_CTRL_Pos) /*!< C_CAN1 IF1_CMDMSK_R: CTRL Mask */
+#define C_CAN1_IF1_CMDMSK_R_ARB_Pos 5 /*!< C_CAN1 IF1_CMDMSK_R: ARB Position */
+#define C_CAN1_IF1_CMDMSK_R_ARB_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_ARB_Pos) /*!< C_CAN1 IF1_CMDMSK_R: ARB Mask */
+#define C_CAN1_IF1_CMDMSK_R_MASK_Pos 6 /*!< C_CAN1 IF1_CMDMSK_R: MASK Position */
+#define C_CAN1_IF1_CMDMSK_R_MASK_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_MASK_Pos) /*!< C_CAN1 IF1_CMDMSK_R: MASK Mask */
+#define C_CAN1_IF1_CMDMSK_R_WR_RD_Pos 7 /*!< C_CAN1 IF1_CMDMSK_R: WR_RD Position */
+#define C_CAN1_IF1_CMDMSK_R_WR_RD_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_WR_RD_Pos) /*!< C_CAN1 IF1_CMDMSK_R: WR_RD Mask */
+
+// ------------------------------------- C_CAN1_IF1_MSK1 ----------------------------------------
+#define C_CAN1_IF1_MSK1_MSK15_0_Pos 0 /*!< C_CAN1 IF1_MSK1: MSK15_0 Position */
+#define C_CAN1_IF1_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CAN1_IF1_MSK1_MSK15_0_Pos) /*!< C_CAN1 IF1_MSK1: MSK15_0 Mask */
+
+// ------------------------------------- C_CAN1_IF1_MSK2 ----------------------------------------
+#define C_CAN1_IF1_MSK2_MSK28_16_Pos 0 /*!< C_CAN1 IF1_MSK2: MSK28_16 Position */
+#define C_CAN1_IF1_MSK2_MSK28_16_Msk (0x00001fffUL << C_CAN1_IF1_MSK2_MSK28_16_Pos) /*!< C_CAN1 IF1_MSK2: MSK28_16 Mask */
+#define C_CAN1_IF1_MSK2_MDIR_Pos 14 /*!< C_CAN1 IF1_MSK2: MDIR Position */
+#define C_CAN1_IF1_MSK2_MDIR_Msk (0x01UL << C_CAN1_IF1_MSK2_MDIR_Pos) /*!< C_CAN1 IF1_MSK2: MDIR Mask */
+#define C_CAN1_IF1_MSK2_MXTD_Pos 15 /*!< C_CAN1 IF1_MSK2: MXTD Position */
+#define C_CAN1_IF1_MSK2_MXTD_Msk (0x01UL << C_CAN1_IF1_MSK2_MXTD_Pos) /*!< C_CAN1 IF1_MSK2: MXTD Mask */
+
+// ------------------------------------- C_CAN1_IF1_ARB1 ----------------------------------------
+#define C_CAN1_IF1_ARB1_ID15_0_Pos 0 /*!< C_CAN1 IF1_ARB1: ID15_0 Position */
+#define C_CAN1_IF1_ARB1_ID15_0_Msk (0x0000ffffUL << C_CAN1_IF1_ARB1_ID15_0_Pos) /*!< C_CAN1 IF1_ARB1: ID15_0 Mask */
+
+// ------------------------------------- C_CAN1_IF1_ARB2 ----------------------------------------
+#define C_CAN1_IF1_ARB2_ID28_16_Pos 0 /*!< C_CAN1 IF1_ARB2: ID28_16 Position */
+#define C_CAN1_IF1_ARB2_ID28_16_Msk (0x00001fffUL << C_CAN1_IF1_ARB2_ID28_16_Pos) /*!< C_CAN1 IF1_ARB2: ID28_16 Mask */
+#define C_CAN1_IF1_ARB2_DIR_Pos 13 /*!< C_CAN1 IF1_ARB2: DIR Position */
+#define C_CAN1_IF1_ARB2_DIR_Msk (0x01UL << C_CAN1_IF1_ARB2_DIR_Pos) /*!< C_CAN1 IF1_ARB2: DIR Mask */
+#define C_CAN1_IF1_ARB2_XTD_Pos 14 /*!< C_CAN1 IF1_ARB2: XTD Position */
+#define C_CAN1_IF1_ARB2_XTD_Msk (0x01UL << C_CAN1_IF1_ARB2_XTD_Pos) /*!< C_CAN1 IF1_ARB2: XTD Mask */
+#define C_CAN1_IF1_ARB2_MSGVAL_Pos 15 /*!< C_CAN1 IF1_ARB2: MSGVAL Position */
+#define C_CAN1_IF1_ARB2_MSGVAL_Msk (0x01UL << C_CAN1_IF1_ARB2_MSGVAL_Pos) /*!< C_CAN1 IF1_ARB2: MSGVAL Mask */
+
+// ------------------------------------ C_CAN1_IF1_MCTRL ----------------------------------------
+#define C_CAN1_IF1_MCTRL_DLC3_0_Pos 0 /*!< C_CAN1 IF1_MCTRL: DLC3_0 Position */
+#define C_CAN1_IF1_MCTRL_DLC3_0_Msk (0x0fUL << C_CAN1_IF1_MCTRL_DLC3_0_Pos) /*!< C_CAN1 IF1_MCTRL: DLC3_0 Mask */
+#define C_CAN1_IF1_MCTRL_EOB_Pos 7 /*!< C_CAN1 IF1_MCTRL: EOB Position */
+#define C_CAN1_IF1_MCTRL_EOB_Msk (0x01UL << C_CAN1_IF1_MCTRL_EOB_Pos) /*!< C_CAN1 IF1_MCTRL: EOB Mask */
+#define C_CAN1_IF1_MCTRL_TXRQST_Pos 8 /*!< C_CAN1 IF1_MCTRL: TXRQST Position */
+#define C_CAN1_IF1_MCTRL_TXRQST_Msk (0x01UL << C_CAN1_IF1_MCTRL_TXRQST_Pos) /*!< C_CAN1 IF1_MCTRL: TXRQST Mask */
+#define C_CAN1_IF1_MCTRL_RMTEN_Pos 9 /*!< C_CAN1 IF1_MCTRL: RMTEN Position */
+#define C_CAN1_IF1_MCTRL_RMTEN_Msk (0x01UL << C_CAN1_IF1_MCTRL_RMTEN_Pos) /*!< C_CAN1 IF1_MCTRL: RMTEN Mask */
+#define C_CAN1_IF1_MCTRL_RXIE_Pos 10 /*!< C_CAN1 IF1_MCTRL: RXIE Position */
+#define C_CAN1_IF1_MCTRL_RXIE_Msk (0x01UL << C_CAN1_IF1_MCTRL_RXIE_Pos) /*!< C_CAN1 IF1_MCTRL: RXIE Mask */
+#define C_CAN1_IF1_MCTRL_TXIE_Pos 11 /*!< C_CAN1 IF1_MCTRL: TXIE Position */
+#define C_CAN1_IF1_MCTRL_TXIE_Msk (0x01UL << C_CAN1_IF1_MCTRL_TXIE_Pos) /*!< C_CAN1 IF1_MCTRL: TXIE Mask */
+#define C_CAN1_IF1_MCTRL_UMASK_Pos 12 /*!< C_CAN1 IF1_MCTRL: UMASK Position */
+#define C_CAN1_IF1_MCTRL_UMASK_Msk (0x01UL << C_CAN1_IF1_MCTRL_UMASK_Pos) /*!< C_CAN1 IF1_MCTRL: UMASK Mask */
+#define C_CAN1_IF1_MCTRL_INTPND_Pos 13 /*!< C_CAN1 IF1_MCTRL: INTPND Position */
+#define C_CAN1_IF1_MCTRL_INTPND_Msk (0x01UL << C_CAN1_IF1_MCTRL_INTPND_Pos) /*!< C_CAN1 IF1_MCTRL: INTPND Mask */
+#define C_CAN1_IF1_MCTRL_MSGLST_Pos 14 /*!< C_CAN1 IF1_MCTRL: MSGLST Position */
+#define C_CAN1_IF1_MCTRL_MSGLST_Msk (0x01UL << C_CAN1_IF1_MCTRL_MSGLST_Pos) /*!< C_CAN1 IF1_MCTRL: MSGLST Mask */
+#define C_CAN1_IF1_MCTRL_NEWDAT_Pos 15 /*!< C_CAN1 IF1_MCTRL: NEWDAT Position */
+#define C_CAN1_IF1_MCTRL_NEWDAT_Msk (0x01UL << C_CAN1_IF1_MCTRL_NEWDAT_Pos) /*!< C_CAN1 IF1_MCTRL: NEWDAT Mask */
+
+// ------------------------------------- C_CAN1_IF1_DA1 -----------------------------------------
+#define C_CAN1_IF1_DA1_DATA0_Pos 0 /*!< C_CAN1 IF1_DA1: DATA0 Position */
+#define C_CAN1_IF1_DA1_DATA0_Msk (0x000000ffUL << C_CAN1_IF1_DA1_DATA0_Pos) /*!< C_CAN1 IF1_DA1: DATA0 Mask */
+#define C_CAN1_IF1_DA1_DATA1_Pos 8 /*!< C_CAN1 IF1_DA1: DATA1 Position */
+#define C_CAN1_IF1_DA1_DATA1_Msk (0x000000ffUL << C_CAN1_IF1_DA1_DATA1_Pos) /*!< C_CAN1 IF1_DA1: DATA1 Mask */
+
+// ------------------------------------- C_CAN1_IF1_DA2 -----------------------------------------
+#define C_CAN1_IF1_DA2_DATA2_Pos 0 /*!< C_CAN1 IF1_DA2: DATA2 Position */
+#define C_CAN1_IF1_DA2_DATA2_Msk (0x000000ffUL << C_CAN1_IF1_DA2_DATA2_Pos) /*!< C_CAN1 IF1_DA2: DATA2 Mask */
+#define C_CAN1_IF1_DA2_DATA3_Pos 8 /*!< C_CAN1 IF1_DA2: DATA3 Position */
+#define C_CAN1_IF1_DA2_DATA3_Msk (0x000000ffUL << C_CAN1_IF1_DA2_DATA3_Pos) /*!< C_CAN1 IF1_DA2: DATA3 Mask */
+
+// ------------------------------------- C_CAN1_IF1_DB1 -----------------------------------------
+#define C_CAN1_IF1_DB1_DATA4_Pos 0 /*!< C_CAN1 IF1_DB1: DATA4 Position */
+#define C_CAN1_IF1_DB1_DATA4_Msk (0x000000ffUL << C_CAN1_IF1_DB1_DATA4_Pos) /*!< C_CAN1 IF1_DB1: DATA4 Mask */
+#define C_CAN1_IF1_DB1_DATA5_Pos 8 /*!< C_CAN1 IF1_DB1: DATA5 Position */
+#define C_CAN1_IF1_DB1_DATA5_Msk (0x000000ffUL << C_CAN1_IF1_DB1_DATA5_Pos) /*!< C_CAN1 IF1_DB1: DATA5 Mask */
+
+// ------------------------------------- C_CAN1_IF1_DB2 -----------------------------------------
+#define C_CAN1_IF1_DB2_DATA6_Pos 0 /*!< C_CAN1 IF1_DB2: DATA6 Position */
+#define C_CAN1_IF1_DB2_DATA6_Msk (0x000000ffUL << C_CAN1_IF1_DB2_DATA6_Pos) /*!< C_CAN1 IF1_DB2: DATA6 Mask */
+#define C_CAN1_IF1_DB2_DATA7_Pos 8 /*!< C_CAN1 IF1_DB2: DATA7 Position */
+#define C_CAN1_IF1_DB2_DATA7_Msk (0x000000ffUL << C_CAN1_IF1_DB2_DATA7_Pos) /*!< C_CAN1 IF1_DB2: DATA7 Mask */
+
+// ------------------------------------ C_CAN1_IF2_CMDREQ ---------------------------------------
+#define C_CAN1_IF2_CMDREQ_MESSNUM_Pos 0 /*!< C_CAN1 IF2_CMDREQ: MESSNUM Position */
+#define C_CAN1_IF2_CMDREQ_MESSNUM_Msk (0x3fUL << C_CAN1_IF2_CMDREQ_MESSNUM_Pos) /*!< C_CAN1 IF2_CMDREQ: MESSNUM Mask */
+#define C_CAN1_IF2_CMDREQ_BUSY_Pos 15 /*!< C_CAN1 IF2_CMDREQ: BUSY Position */
+#define C_CAN1_IF2_CMDREQ_BUSY_Msk (0x01UL << C_CAN1_IF2_CMDREQ_BUSY_Pos) /*!< C_CAN1 IF2_CMDREQ: BUSY Mask */
+
+// ----------------------------------- C_CAN1_IF2_CMDMSK_W --------------------------------------
+#define C_CAN1_IF2_CMDMSK_W_DATA_B_Pos 0 /*!< C_CAN1 IF2_CMDMSK_W: DATA_B Position */
+#define C_CAN1_IF2_CMDMSK_W_DATA_B_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_DATA_B_Pos) /*!< C_CAN1 IF2_CMDMSK_W: DATA_B Mask */
+#define C_CAN1_IF2_CMDMSK_W_DATA_A_Pos 1 /*!< C_CAN1 IF2_CMDMSK_W: DATA_A Position */
+#define C_CAN1_IF2_CMDMSK_W_DATA_A_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_DATA_A_Pos) /*!< C_CAN1 IF2_CMDMSK_W: DATA_A Mask */
+#define C_CAN1_IF2_CMDMSK_W_TXRQST_Pos 2 /*!< C_CAN1 IF2_CMDMSK_W: TXRQST Position */
+#define C_CAN1_IF2_CMDMSK_W_TXRQST_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_TXRQST_Pos) /*!< C_CAN1 IF2_CMDMSK_W: TXRQST Mask */
+#define C_CAN1_IF2_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CAN1 IF2_CMDMSK_W: CLRINTPND Position */
+#define C_CAN1_IF2_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_CLRINTPND_Pos) /*!< C_CAN1 IF2_CMDMSK_W: CLRINTPND Mask */
+#define C_CAN1_IF2_CMDMSK_W_CTRL_Pos 4 /*!< C_CAN1 IF2_CMDMSK_W: CTRL Position */
+#define C_CAN1_IF2_CMDMSK_W_CTRL_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_CTRL_Pos) /*!< C_CAN1 IF2_CMDMSK_W: CTRL Mask */
+#define C_CAN1_IF2_CMDMSK_W_ARB_Pos 5 /*!< C_CAN1 IF2_CMDMSK_W: ARB Position */
+#define C_CAN1_IF2_CMDMSK_W_ARB_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_ARB_Pos) /*!< C_CAN1 IF2_CMDMSK_W: ARB Mask */
+#define C_CAN1_IF2_CMDMSK_W_MASK_Pos 6 /*!< C_CAN1 IF2_CMDMSK_W: MASK Position */
+#define C_CAN1_IF2_CMDMSK_W_MASK_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_MASK_Pos) /*!< C_CAN1 IF2_CMDMSK_W: MASK Mask */
+#define C_CAN1_IF2_CMDMSK_W_WR_RD_Pos 7 /*!< C_CAN1 IF2_CMDMSK_W: WR_RD Position */
+#define C_CAN1_IF2_CMDMSK_W_WR_RD_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_WR_RD_Pos) /*!< C_CAN1 IF2_CMDMSK_W: WR_RD Mask */
+
+// ----------------------------------- C_CAN1_IF2_CMDMSK_R --------------------------------------
+#define C_CAN1_IF2_CMDMSK_R_DATA_B_Pos 0 /*!< C_CAN1 IF2_CMDMSK_R: DATA_B Position */
+#define C_CAN1_IF2_CMDMSK_R_DATA_B_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_DATA_B_Pos) /*!< C_CAN1 IF2_CMDMSK_R: DATA_B Mask */
+#define C_CAN1_IF2_CMDMSK_R_DATA_A_Pos 1 /*!< C_CAN1 IF2_CMDMSK_R: DATA_A Position */
+#define C_CAN1_IF2_CMDMSK_R_DATA_A_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_DATA_A_Pos) /*!< C_CAN1 IF2_CMDMSK_R: DATA_A Mask */
+#define C_CAN1_IF2_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CAN1 IF2_CMDMSK_R: NEWDAT Position */
+#define C_CAN1_IF2_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_NEWDAT_Pos) /*!< C_CAN1 IF2_CMDMSK_R: NEWDAT Mask */
+#define C_CAN1_IF2_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CAN1 IF2_CMDMSK_R: CLRINTPND Position */
+#define C_CAN1_IF2_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_CLRINTPND_Pos) /*!< C_CAN1 IF2_CMDMSK_R: CLRINTPND Mask */
+#define C_CAN1_IF2_CMDMSK_R_CTRL_Pos 4 /*!< C_CAN1 IF2_CMDMSK_R: CTRL Position */
+#define C_CAN1_IF2_CMDMSK_R_CTRL_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_CTRL_Pos) /*!< C_CAN1 IF2_CMDMSK_R: CTRL Mask */
+#define C_CAN1_IF2_CMDMSK_R_ARB_Pos 5 /*!< C_CAN1 IF2_CMDMSK_R: ARB Position */
+#define C_CAN1_IF2_CMDMSK_R_ARB_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_ARB_Pos) /*!< C_CAN1 IF2_CMDMSK_R: ARB Mask */
+#define C_CAN1_IF2_CMDMSK_R_MASK_Pos 6 /*!< C_CAN1 IF2_CMDMSK_R: MASK Position */
+#define C_CAN1_IF2_CMDMSK_R_MASK_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_MASK_Pos) /*!< C_CAN1 IF2_CMDMSK_R: MASK Mask */
+#define C_CAN1_IF2_CMDMSK_R_WR_RD_Pos 7 /*!< C_CAN1 IF2_CMDMSK_R: WR_RD Position */
+#define C_CAN1_IF2_CMDMSK_R_WR_RD_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_WR_RD_Pos) /*!< C_CAN1 IF2_CMDMSK_R: WR_RD Mask */
+
+// ------------------------------------- C_CAN1_IF2_MSK1 ----------------------------------------
+#define C_CAN1_IF2_MSK1_MSK15_0_Pos 0 /*!< C_CAN1 IF2_MSK1: MSK15_0 Position */
+#define C_CAN1_IF2_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CAN1_IF2_MSK1_MSK15_0_Pos) /*!< C_CAN1 IF2_MSK1: MSK15_0 Mask */
+
+// ------------------------------------- C_CAN1_IF2_MSK2 ----------------------------------------
+#define C_CAN1_IF2_MSK2_MSK28_16_Pos 0 /*!< C_CAN1 IF2_MSK2: MSK28_16 Position */
+#define C_CAN1_IF2_MSK2_MSK28_16_Msk (0x00001fffUL << C_CAN1_IF2_MSK2_MSK28_16_Pos) /*!< C_CAN1 IF2_MSK2: MSK28_16 Mask */
+#define C_CAN1_IF2_MSK2_MDIR_Pos 14 /*!< C_CAN1 IF2_MSK2: MDIR Position */
+#define C_CAN1_IF2_MSK2_MDIR_Msk (0x01UL << C_CAN1_IF2_MSK2_MDIR_Pos) /*!< C_CAN1 IF2_MSK2: MDIR Mask */
+#define C_CAN1_IF2_MSK2_MXTD_Pos 15 /*!< C_CAN1 IF2_MSK2: MXTD Position */
+#define C_CAN1_IF2_MSK2_MXTD_Msk (0x01UL << C_CAN1_IF2_MSK2_MXTD_Pos) /*!< C_CAN1 IF2_MSK2: MXTD Mask */
+
+// ------------------------------------- C_CAN1_IF2_ARB1 ----------------------------------------
+#define C_CAN1_IF2_ARB1_ID15_0_Pos 0 /*!< C_CAN1 IF2_ARB1: ID15_0 Position */
+#define C_CAN1_IF2_ARB1_ID15_0_Msk (0x0000ffffUL << C_CAN1_IF2_ARB1_ID15_0_Pos) /*!< C_CAN1 IF2_ARB1: ID15_0 Mask */
+
+// ------------------------------------- C_CAN1_IF2_ARB2 ----------------------------------------
+#define C_CAN1_IF2_ARB2_ID28_16_Pos 0 /*!< C_CAN1 IF2_ARB2: ID28_16 Position */
+#define C_CAN1_IF2_ARB2_ID28_16_Msk (0x00001fffUL << C_CAN1_IF2_ARB2_ID28_16_Pos) /*!< C_CAN1 IF2_ARB2: ID28_16 Mask */
+#define C_CAN1_IF2_ARB2_DIR_Pos 13 /*!< C_CAN1 IF2_ARB2: DIR Position */
+#define C_CAN1_IF2_ARB2_DIR_Msk (0x01UL << C_CAN1_IF2_ARB2_DIR_Pos) /*!< C_CAN1 IF2_ARB2: DIR Mask */
+#define C_CAN1_IF2_ARB2_XTD_Pos 14 /*!< C_CAN1 IF2_ARB2: XTD Position */
+#define C_CAN1_IF2_ARB2_XTD_Msk (0x01UL << C_CAN1_IF2_ARB2_XTD_Pos) /*!< C_CAN1 IF2_ARB2: XTD Mask */
+#define C_CAN1_IF2_ARB2_MSGVAL_Pos 15 /*!< C_CAN1 IF2_ARB2: MSGVAL Position */
+#define C_CAN1_IF2_ARB2_MSGVAL_Msk (0x01UL << C_CAN1_IF2_ARB2_MSGVAL_Pos) /*!< C_CAN1 IF2_ARB2: MSGVAL Mask */
+
+// ------------------------------------ C_CAN1_IF2_MCTRL ----------------------------------------
+#define C_CAN1_IF2_MCTRL_DLC3_0_Pos 0 /*!< C_CAN1 IF2_MCTRL: DLC3_0 Position */
+#define C_CAN1_IF2_MCTRL_DLC3_0_Msk (0x0fUL << C_CAN1_IF2_MCTRL_DLC3_0_Pos) /*!< C_CAN1 IF2_MCTRL: DLC3_0 Mask */
+#define C_CAN1_IF2_MCTRL_EOB_Pos 7 /*!< C_CAN1 IF2_MCTRL: EOB Position */
+#define C_CAN1_IF2_MCTRL_EOB_Msk (0x01UL << C_CAN1_IF2_MCTRL_EOB_Pos) /*!< C_CAN1 IF2_MCTRL: EOB Mask */
+#define C_CAN1_IF2_MCTRL_TXRQST_Pos 8 /*!< C_CAN1 IF2_MCTRL: TXRQST Position */
+#define C_CAN1_IF2_MCTRL_TXRQST_Msk (0x01UL << C_CAN1_IF2_MCTRL_TXRQST_Pos) /*!< C_CAN1 IF2_MCTRL: TXRQST Mask */
+#define C_CAN1_IF2_MCTRL_RMTEN_Pos 9 /*!< C_CAN1 IF2_MCTRL: RMTEN Position */
+#define C_CAN1_IF2_MCTRL_RMTEN_Msk (0x01UL << C_CAN1_IF2_MCTRL_RMTEN_Pos) /*!< C_CAN1 IF2_MCTRL: RMTEN Mask */
+#define C_CAN1_IF2_MCTRL_RXIE_Pos 10 /*!< C_CAN1 IF2_MCTRL: RXIE Position */
+#define C_CAN1_IF2_MCTRL_RXIE_Msk (0x01UL << C_CAN1_IF2_MCTRL_RXIE_Pos) /*!< C_CAN1 IF2_MCTRL: RXIE Mask */
+#define C_CAN1_IF2_MCTRL_TXIE_Pos 11 /*!< C_CAN1 IF2_MCTRL: TXIE Position */
+#define C_CAN1_IF2_MCTRL_TXIE_Msk (0x01UL << C_CAN1_IF2_MCTRL_TXIE_Pos) /*!< C_CAN1 IF2_MCTRL: TXIE Mask */
+#define C_CAN1_IF2_MCTRL_UMASK_Pos 12 /*!< C_CAN1 IF2_MCTRL: UMASK Position */
+#define C_CAN1_IF2_MCTRL_UMASK_Msk (0x01UL << C_CAN1_IF2_MCTRL_UMASK_Pos) /*!< C_CAN1 IF2_MCTRL: UMASK Mask */
+#define C_CAN1_IF2_MCTRL_INTPND_Pos 13 /*!< C_CAN1 IF2_MCTRL: INTPND Position */
+#define C_CAN1_IF2_MCTRL_INTPND_Msk (0x01UL << C_CAN1_IF2_MCTRL_INTPND_Pos) /*!< C_CAN1 IF2_MCTRL: INTPND Mask */
+#define C_CAN1_IF2_MCTRL_MSGLST_Pos 14 /*!< C_CAN1 IF2_MCTRL: MSGLST Position */
+#define C_CAN1_IF2_MCTRL_MSGLST_Msk (0x01UL << C_CAN1_IF2_MCTRL_MSGLST_Pos) /*!< C_CAN1 IF2_MCTRL: MSGLST Mask */
+#define C_CAN1_IF2_MCTRL_NEWDAT_Pos 15 /*!< C_CAN1 IF2_MCTRL: NEWDAT Position */
+#define C_CAN1_IF2_MCTRL_NEWDAT_Msk (0x01UL << C_CAN1_IF2_MCTRL_NEWDAT_Pos) /*!< C_CAN1 IF2_MCTRL: NEWDAT Mask */
+
+// ------------------------------------- C_CAN1_IF2_DA1 -----------------------------------------
+#define C_CAN1_IF2_DA1_DATA0_Pos 0 /*!< C_CAN1 IF2_DA1: DATA0 Position */
+#define C_CAN1_IF2_DA1_DATA0_Msk (0x000000ffUL << C_CAN1_IF2_DA1_DATA0_Pos) /*!< C_CAN1 IF2_DA1: DATA0 Mask */
+#define C_CAN1_IF2_DA1_DATA1_Pos 8 /*!< C_CAN1 IF2_DA1: DATA1 Position */
+#define C_CAN1_IF2_DA1_DATA1_Msk (0x000000ffUL << C_CAN1_IF2_DA1_DATA1_Pos) /*!< C_CAN1 IF2_DA1: DATA1 Mask */
+
+// ------------------------------------- C_CAN1_IF2_DA2 -----------------------------------------
+#define C_CAN1_IF2_DA2_DATA2_Pos 0 /*!< C_CAN1 IF2_DA2: DATA2 Position */
+#define C_CAN1_IF2_DA2_DATA2_Msk (0x000000ffUL << C_CAN1_IF2_DA2_DATA2_Pos) /*!< C_CAN1 IF2_DA2: DATA2 Mask */
+#define C_CAN1_IF2_DA2_DATA3_Pos 8 /*!< C_CAN1 IF2_DA2: DATA3 Position */
+#define C_CAN1_IF2_DA2_DATA3_Msk (0x000000ffUL << C_CAN1_IF2_DA2_DATA3_Pos) /*!< C_CAN1 IF2_DA2: DATA3 Mask */
+
+// ------------------------------------- C_CAN1_IF2_DB1 -----------------------------------------
+#define C_CAN1_IF2_DB1_DATA4_Pos 0 /*!< C_CAN1 IF2_DB1: DATA4 Position */
+#define C_CAN1_IF2_DB1_DATA4_Msk (0x000000ffUL << C_CAN1_IF2_DB1_DATA4_Pos) /*!< C_CAN1 IF2_DB1: DATA4 Mask */
+#define C_CAN1_IF2_DB1_DATA5_Pos 8 /*!< C_CAN1 IF2_DB1: DATA5 Position */
+#define C_CAN1_IF2_DB1_DATA5_Msk (0x000000ffUL << C_CAN1_IF2_DB1_DATA5_Pos) /*!< C_CAN1 IF2_DB1: DATA5 Mask */
+
+// ------------------------------------- C_CAN1_IF2_DB2 -----------------------------------------
+#define C_CAN1_IF2_DB2_DATA6_Pos 0 /*!< C_CAN1 IF2_DB2: DATA6 Position */
+#define C_CAN1_IF2_DB2_DATA6_Msk (0x000000ffUL << C_CAN1_IF2_DB2_DATA6_Pos) /*!< C_CAN1 IF2_DB2: DATA6 Mask */
+#define C_CAN1_IF2_DB2_DATA7_Pos 8 /*!< C_CAN1 IF2_DB2: DATA7 Position */
+#define C_CAN1_IF2_DB2_DATA7_Msk (0x000000ffUL << C_CAN1_IF2_DB2_DATA7_Pos) /*!< C_CAN1 IF2_DB2: DATA7 Mask */
+
+// -------------------------------------- C_CAN1_TXREQ1 -----------------------------------------
+#define C_CAN1_TXREQ1_TXRQST16_1_Pos 0 /*!< C_CAN1 TXREQ1: TXRQST16_1 Position */
+#define C_CAN1_TXREQ1_TXRQST16_1_Msk (0x0000ffffUL << C_CAN1_TXREQ1_TXRQST16_1_Pos) /*!< C_CAN1 TXREQ1: TXRQST16_1 Mask */
+
+// -------------------------------------- C_CAN1_TXREQ2 -----------------------------------------
+#define C_CAN1_TXREQ2_TXRQST32_17_Pos 0 /*!< C_CAN1 TXREQ2: TXRQST32_17 Position */
+#define C_CAN1_TXREQ2_TXRQST32_17_Msk (0x0000ffffUL << C_CAN1_TXREQ2_TXRQST32_17_Pos) /*!< C_CAN1 TXREQ2: TXRQST32_17 Mask */
+
+// --------------------------------------- C_CAN1_ND1 -------------------------------------------
+#define C_CAN1_ND1_NEWDAT16_1_Pos 0 /*!< C_CAN1 ND1: NEWDAT16_1 Position */
+#define C_CAN1_ND1_NEWDAT16_1_Msk (0x0000ffffUL << C_CAN1_ND1_NEWDAT16_1_Pos) /*!< C_CAN1 ND1: NEWDAT16_1 Mask */
+
+// --------------------------------------- C_CAN1_ND2 -------------------------------------------
+#define C_CAN1_ND2_NEWDAT32_17_Pos 0 /*!< C_CAN1 ND2: NEWDAT32_17 Position */
+#define C_CAN1_ND2_NEWDAT32_17_Msk (0x0000ffffUL << C_CAN1_ND2_NEWDAT32_17_Pos) /*!< C_CAN1 ND2: NEWDAT32_17 Mask */
+
+// --------------------------------------- C_CAN1_IR1 -------------------------------------------
+#define C_CAN1_IR1_INTPND16_1_Pos 0 /*!< C_CAN1 IR1: INTPND16_1 Position */
+#define C_CAN1_IR1_INTPND16_1_Msk (0x0000ffffUL << C_CAN1_IR1_INTPND16_1_Pos) /*!< C_CAN1 IR1: INTPND16_1 Mask */
+
+// --------------------------------------- C_CAN1_IR2 -------------------------------------------
+#define C_CAN1_IR2_INTPND32_17_Pos 0 /*!< C_CAN1 IR2: INTPND32_17 Position */
+#define C_CAN1_IR2_INTPND32_17_Msk (0x0000ffffUL << C_CAN1_IR2_INTPND32_17_Pos) /*!< C_CAN1 IR2: INTPND32_17 Mask */
+
+// -------------------------------------- C_CAN1_MSGV1 ------------------------------------------
+#define C_CAN1_MSGV1_MSGVAL16_1_Pos 0 /*!< C_CAN1 MSGV1: MSGVAL16_1 Position */
+#define C_CAN1_MSGV1_MSGVAL16_1_Msk (0x0000ffffUL << C_CAN1_MSGV1_MSGVAL16_1_Pos) /*!< C_CAN1 MSGV1: MSGVAL16_1 Mask */
+
+// -------------------------------------- C_CAN1_MSGV2 ------------------------------------------
+#define C_CAN1_MSGV2_MSGVAL32_17_Pos 0 /*!< C_CAN1 MSGV2: MSGVAL32_17 Position */
+#define C_CAN1_MSGV2_MSGVAL32_17_Msk (0x0000ffffUL << C_CAN1_MSGV2_MSGVAL32_17_Pos) /*!< C_CAN1 MSGV2: MSGVAL32_17 Mask */
+
+// -------------------------------------- C_CAN1_CLKDIV -----------------------------------------
+#define C_CAN1_CLKDIV_CLKDIVVAL_Pos 0 /*!< C_CAN1 CLKDIV: CLKDIVVAL Position */
+#define C_CAN1_CLKDIV_CLKDIVVAL_Msk (0x0fUL << C_CAN1_CLKDIV_CLKDIVVAL_Pos) /*!< C_CAN1 CLKDIV: CLKDIVVAL Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- RITIMER Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ------------------------------------- RITIMER_COMPVAL ----------------------------------------
+#define RITIMER_COMPVAL_RICOMP_Pos 0 /*!< RITIMER COMPVAL: RICOMP Position */
+#define RITIMER_COMPVAL_RICOMP_Msk (0xffffffffUL << RITIMER_COMPVAL_RICOMP_Pos) /*!< RITIMER COMPVAL: RICOMP Mask */
+
+// -------------------------------------- RITIMER_MASK ------------------------------------------
+#define RITIMER_MASK_RIMASK_Pos 0 /*!< RITIMER MASK: RIMASK Position */
+#define RITIMER_MASK_RIMASK_Msk (0xffffffffUL << RITIMER_MASK_RIMASK_Pos) /*!< RITIMER MASK: RIMASK Mask */
+
+// -------------------------------------- RITIMER_CTRL ------------------------------------------
+#define RITIMER_CTRL_RITINT_Pos 0 /*!< RITIMER CTRL: RITINT Position */
+#define RITIMER_CTRL_RITINT_Msk (0x01UL << RITIMER_CTRL_RITINT_Pos) /*!< RITIMER CTRL: RITINT Mask */
+#define RITIMER_CTRL_RITENCLR_Pos 1 /*!< RITIMER CTRL: RITENCLR Position */
+#define RITIMER_CTRL_RITENCLR_Msk (0x01UL << RITIMER_CTRL_RITENCLR_Pos) /*!< RITIMER CTRL: RITENCLR Mask */
+#define RITIMER_CTRL_RITENBR_Pos 2 /*!< RITIMER CTRL: RITENBR Position */
+#define RITIMER_CTRL_RITENBR_Msk (0x01UL << RITIMER_CTRL_RITENBR_Pos) /*!< RITIMER CTRL: RITENBR Mask */
+#define RITIMER_CTRL_RITEN_Pos 3 /*!< RITIMER CTRL: RITEN Position */
+#define RITIMER_CTRL_RITEN_Msk (0x01UL << RITIMER_CTRL_RITEN_Pos) /*!< RITIMER CTRL: RITEN Mask */
+
+// ------------------------------------- RITIMER_COUNTER ----------------------------------------
+#define RITIMER_COUNTER_RICOUNTER_Pos 0 /*!< RITIMER COUNTER: RICOUNTER Position */
+#define RITIMER_COUNTER_RICOUNTER_Msk (0xffffffffUL << RITIMER_COUNTER_RICOUNTER_Pos) /*!< RITIMER COUNTER: RICOUNTER Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- QEI Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------- QEI_CON --------------------------------------------
+#define QEI_CON_RESP_Pos 0 /*!< QEI CON: RESP Position */
+#define QEI_CON_RESP_Msk (0x01UL << QEI_CON_RESP_Pos) /*!< QEI CON: RESP Mask */
+#define QEI_CON_RESPI_Pos 1 /*!< QEI CON: RESPI Position */
+#define QEI_CON_RESPI_Msk (0x01UL << QEI_CON_RESPI_Pos) /*!< QEI CON: RESPI Mask */
+#define QEI_CON_RESV_Pos 2 /*!< QEI CON: RESV Position */
+#define QEI_CON_RESV_Msk (0x01UL << QEI_CON_RESV_Pos) /*!< QEI CON: RESV Mask */
+#define QEI_CON_RESI_Pos 3 /*!< QEI CON: RESI Position */
+#define QEI_CON_RESI_Msk (0x01UL << QEI_CON_RESI_Pos) /*!< QEI CON: RESI Mask */
+
+// ---------------------------------------- QEI_STAT --------------------------------------------
+#define QEI_STAT_DIR_Pos 0 /*!< QEI STAT: DIR Position */
+#define QEI_STAT_DIR_Msk (0x01UL << QEI_STAT_DIR_Pos) /*!< QEI STAT: DIR Mask */
+
+// ---------------------------------------- QEI_CONF --------------------------------------------
+#define QEI_CONF_DIRINV_Pos 0 /*!< QEI CONF: DIRINV Position */
+#define QEI_CONF_DIRINV_Msk (0x01UL << QEI_CONF_DIRINV_Pos) /*!< QEI CONF: DIRINV Mask */
+#define QEI_CONF_SIGMODE_Pos 1 /*!< QEI CONF: SIGMODE Position */
+#define QEI_CONF_SIGMODE_Msk (0x01UL << QEI_CONF_SIGMODE_Pos) /*!< QEI CONF: SIGMODE Mask */
+#define QEI_CONF_CAPMODE_Pos 2 /*!< QEI CONF: CAPMODE Position */
+#define QEI_CONF_CAPMODE_Msk (0x01UL << QEI_CONF_CAPMODE_Pos) /*!< QEI CONF: CAPMODE Mask */
+#define QEI_CONF_INVINX_Pos 3 /*!< QEI CONF: INVINX Position */
+#define QEI_CONF_INVINX_Msk (0x01UL << QEI_CONF_INVINX_Pos) /*!< QEI CONF: INVINX Mask */
+#define QEI_CONF_CRESPI_Pos 4 /*!< QEI CONF: CRESPI Position */
+#define QEI_CONF_CRESPI_Msk (0x01UL << QEI_CONF_CRESPI_Pos) /*!< QEI CONF: CRESPI Mask */
+#define QEI_CONF_INXGATE_Pos 16 /*!< QEI CONF: INXGATE Position */
+#define QEI_CONF_INXGATE_Msk (0x0fUL << QEI_CONF_INXGATE_Pos) /*!< QEI CONF: INXGATE Mask */
+
+// ----------------------------------------- QEI_POS --------------------------------------------
+#define QEI_POS_POS_Pos 0 /*!< QEI POS: POS Position */
+#define QEI_POS_POS_Msk (0xffffffffUL << QEI_POS_POS_Pos) /*!< QEI POS: POS Mask */
+
+// --------------------------------------- QEI_MAXPOS -------------------------------------------
+#define QEI_MAXPOS_MAXPOS_Pos 0 /*!< QEI MAXPOS: MAXPOS Position */
+#define QEI_MAXPOS_MAXPOS_Msk (0xffffffffUL << QEI_MAXPOS_MAXPOS_Pos) /*!< QEI MAXPOS: MAXPOS Mask */
+
+// --------------------------------------- QEI_CMPOS0 -------------------------------------------
+#define QEI_CMPOS0_PCMP0_Pos 0 /*!< QEI CMPOS0: PCMP0 Position */
+#define QEI_CMPOS0_PCMP0_Msk (0xffffffffUL << QEI_CMPOS0_PCMP0_Pos) /*!< QEI CMPOS0: PCMP0 Mask */
+
+// --------------------------------------- QEI_CMPOS1 -------------------------------------------
+#define QEI_CMPOS1_PCMP1_Pos 0 /*!< QEI CMPOS1: PCMP1 Position */
+#define QEI_CMPOS1_PCMP1_Msk (0xffffffffUL << QEI_CMPOS1_PCMP1_Pos) /*!< QEI CMPOS1: PCMP1 Mask */
+
+// --------------------------------------- QEI_CMPOS2 -------------------------------------------
+#define QEI_CMPOS2_PCMP2_Pos 0 /*!< QEI CMPOS2: PCMP2 Position */
+#define QEI_CMPOS2_PCMP2_Msk (0xffffffffUL << QEI_CMPOS2_PCMP2_Pos) /*!< QEI CMPOS2: PCMP2 Mask */
+
+// --------------------------------------- QEI_INXCNT -------------------------------------------
+#define QEI_INXCNT_ENCPOS_Pos 0 /*!< QEI INXCNT: ENCPOS Position */
+#define QEI_INXCNT_ENCPOS_Msk (0xffffffffUL << QEI_INXCNT_ENCPOS_Pos) /*!< QEI INXCNT: ENCPOS Mask */
+
+// --------------------------------------- QEI_INXCMP0 ------------------------------------------
+#define QEI_INXCMP0_ICMP0_Pos 0 /*!< QEI INXCMP0: ICMP0 Position */
+#define QEI_INXCMP0_ICMP0_Msk (0xffffffffUL << QEI_INXCMP0_ICMP0_Pos) /*!< QEI INXCMP0: ICMP0 Mask */
+
+// ---------------------------------------- QEI_LOAD --------------------------------------------
+#define QEI_LOAD_VELLOAD_Pos 0 /*!< QEI LOAD: VELLOAD Position */
+#define QEI_LOAD_VELLOAD_Msk (0xffffffffUL << QEI_LOAD_VELLOAD_Pos) /*!< QEI LOAD: VELLOAD Mask */
+
+// ---------------------------------------- QEI_TIME --------------------------------------------
+#define QEI_TIME_VELVAL_Pos 0 /*!< QEI TIME: VELVAL Position */
+#define QEI_TIME_VELVAL_Msk (0xffffffffUL << QEI_TIME_VELVAL_Pos) /*!< QEI TIME: VELVAL Mask */
+
+// ----------------------------------------- QEI_VEL --------------------------------------------
+#define QEI_VEL_VELPC_Pos 0 /*!< QEI VEL: VELPC Position */
+#define QEI_VEL_VELPC_Msk (0xffffffffUL << QEI_VEL_VELPC_Pos) /*!< QEI VEL: VELPC Mask */
+
+// ----------------------------------------- QEI_CAP --------------------------------------------
+#define QEI_CAP_VELCAP_Pos 0 /*!< QEI CAP: VELCAP Position */
+#define QEI_CAP_VELCAP_Msk (0xffffffffUL << QEI_CAP_VELCAP_Pos) /*!< QEI CAP: VELCAP Mask */
+
+// --------------------------------------- QEI_VELCOMP ------------------------------------------
+#define QEI_VELCOMP_VELCMP_Pos 0 /*!< QEI VELCOMP: VELCMP Position */
+#define QEI_VELCOMP_VELCMP_Msk (0xffffffffUL << QEI_VELCOMP_VELCMP_Pos) /*!< QEI VELCOMP: VELCMP Mask */
+
+// -------------------------------------- QEI_FILTERPHA -----------------------------------------
+#define QEI_FILTERPHA_FILTA_Pos 0 /*!< QEI FILTERPHA: FILTA Position */
+#define QEI_FILTERPHA_FILTA_Msk (0xffffffffUL << QEI_FILTERPHA_FILTA_Pos) /*!< QEI FILTERPHA: FILTA Mask */
+
+// -------------------------------------- QEI_FILTERPHB -----------------------------------------
+#define QEI_FILTERPHB_FILTB_Pos 0 /*!< QEI FILTERPHB: FILTB Position */
+#define QEI_FILTERPHB_FILTB_Msk (0xffffffffUL << QEI_FILTERPHB_FILTB_Pos) /*!< QEI FILTERPHB: FILTB Mask */
+
+// -------------------------------------- QEI_FILTERINX -----------------------------------------
+#define QEI_FILTERINX_FITLINX_Pos 0 /*!< QEI FILTERINX: FITLINX Position */
+#define QEI_FILTERINX_FITLINX_Msk (0xffffffffUL << QEI_FILTERINX_FITLINX_Pos) /*!< QEI FILTERINX: FITLINX Mask */
+
+// --------------------------------------- QEI_WINDOW -------------------------------------------
+#define QEI_WINDOW_WINDOW_Pos 0 /*!< QEI WINDOW: WINDOW Position */
+#define QEI_WINDOW_WINDOW_Msk (0xffffffffUL << QEI_WINDOW_WINDOW_Pos) /*!< QEI WINDOW: WINDOW Mask */
+
+// --------------------------------------- QEI_INXCMP1 ------------------------------------------
+#define QEI_INXCMP1_ICMP1_Pos 0 /*!< QEI INXCMP1: ICMP1 Position */
+#define QEI_INXCMP1_ICMP1_Msk (0xffffffffUL << QEI_INXCMP1_ICMP1_Pos) /*!< QEI INXCMP1: ICMP1 Mask */
+
+// --------------------------------------- QEI_INXCMP2 ------------------------------------------
+#define QEI_INXCMP2_ICMP2_Pos 0 /*!< QEI INXCMP2: ICMP2 Position */
+#define QEI_INXCMP2_ICMP2_Msk (0xffffffffUL << QEI_INXCMP2_ICMP2_Pos) /*!< QEI INXCMP2: ICMP2 Mask */
+
+// ----------------------------------------- QEI_IEC --------------------------------------------
+#define QEI_IEC_INX_EN_Pos 0 /*!< QEI IEC: INX_EN Position */
+#define QEI_IEC_INX_EN_Msk (0x01UL << QEI_IEC_INX_EN_Pos) /*!< QEI IEC: INX_EN Mask */
+#define QEI_IEC_TIM_EN_Pos 1 /*!< QEI IEC: TIM_EN Position */
+#define QEI_IEC_TIM_EN_Msk (0x01UL << QEI_IEC_TIM_EN_Pos) /*!< QEI IEC: TIM_EN Mask */
+#define QEI_IEC_VELC_EN_Pos 2 /*!< QEI IEC: VELC_EN Position */
+#define QEI_IEC_VELC_EN_Msk (0x01UL << QEI_IEC_VELC_EN_Pos) /*!< QEI IEC: VELC_EN Mask */
+#define QEI_IEC_DIR_EN_Pos 3 /*!< QEI IEC: DIR_EN Position */
+#define QEI_IEC_DIR_EN_Msk (0x01UL << QEI_IEC_DIR_EN_Pos) /*!< QEI IEC: DIR_EN Mask */
+#define QEI_IEC_ERR_EN_Pos 4 /*!< QEI IEC: ERR_EN Position */
+#define QEI_IEC_ERR_EN_Msk (0x01UL << QEI_IEC_ERR_EN_Pos) /*!< QEI IEC: ERR_EN Mask */
+#define QEI_IEC_ENCLK_EN_Pos 5 /*!< QEI IEC: ENCLK_EN Position */
+#define QEI_IEC_ENCLK_EN_Msk (0x01UL << QEI_IEC_ENCLK_EN_Pos) /*!< QEI IEC: ENCLK_EN Mask */
+#define QEI_IEC_POS0_Int_Pos 6 /*!< QEI IEC: POS0_Int Position */
+#define QEI_IEC_POS0_Int_Msk (0x01UL << QEI_IEC_POS0_Int_Pos) /*!< QEI IEC: POS0_Int Mask */
+#define QEI_IEC_POS1_Int_Pos 7 /*!< QEI IEC: POS1_Int Position */
+#define QEI_IEC_POS1_Int_Msk (0x01UL << QEI_IEC_POS1_Int_Pos) /*!< QEI IEC: POS1_Int Mask */
+#define QEI_IEC_POS2_Int_Pos 8 /*!< QEI IEC: POS2_Int Position */
+#define QEI_IEC_POS2_Int_Msk (0x01UL << QEI_IEC_POS2_Int_Pos) /*!< QEI IEC: POS2_Int Mask */
+#define QEI_IEC_REV_Int_Pos 9 /*!< QEI IEC: REV_Int Position */
+#define QEI_IEC_REV_Int_Msk (0x01UL << QEI_IEC_REV_Int_Pos) /*!< QEI IEC: REV_Int Mask */
+#define QEI_IEC_POS0REV_Int_Pos 10 /*!< QEI IEC: POS0REV_Int Position */
+#define QEI_IEC_POS0REV_Int_Msk (0x01UL << QEI_IEC_POS0REV_Int_Pos) /*!< QEI IEC: POS0REV_Int Mask */
+#define QEI_IEC_POS1REV_Int_Pos 11 /*!< QEI IEC: POS1REV_Int Position */
+#define QEI_IEC_POS1REV_Int_Msk (0x01UL << QEI_IEC_POS1REV_Int_Pos) /*!< QEI IEC: POS1REV_Int Mask */
+#define QEI_IEC_POS2REV_Int_Pos 12 /*!< QEI IEC: POS2REV_Int Position */
+#define QEI_IEC_POS2REV_Int_Msk (0x01UL << QEI_IEC_POS2REV_Int_Pos) /*!< QEI IEC: POS2REV_Int Mask */
+#define QEI_IEC_REV1_Int_Pos 13 /*!< QEI IEC: REV1_Int Position */
+#define QEI_IEC_REV1_Int_Msk (0x01UL << QEI_IEC_REV1_Int_Pos) /*!< QEI IEC: REV1_Int Mask */
+#define QEI_IEC_REV2_Int_Pos 14 /*!< QEI IEC: REV2_Int Position */
+#define QEI_IEC_REV2_Int_Msk (0x01UL << QEI_IEC_REV2_Int_Pos) /*!< QEI IEC: REV2_Int Mask */
+#define QEI_IEC_MAXPOS_Int_Pos 15 /*!< QEI IEC: MAXPOS_Int Position */
+#define QEI_IEC_MAXPOS_Int_Msk (0x01UL << QEI_IEC_MAXPOS_Int_Pos) /*!< QEI IEC: MAXPOS_Int Mask */
+
+// ----------------------------------------- QEI_IES --------------------------------------------
+#define QEI_IES_INX_EN_Pos 0 /*!< QEI IES: INX_EN Position */
+#define QEI_IES_INX_EN_Msk (0x01UL << QEI_IES_INX_EN_Pos) /*!< QEI IES: INX_EN Mask */
+#define QEI_IES_TIM_EN_Pos 1 /*!< QEI IES: TIM_EN Position */
+#define QEI_IES_TIM_EN_Msk (0x01UL << QEI_IES_TIM_EN_Pos) /*!< QEI IES: TIM_EN Mask */
+#define QEI_IES_VELC_EN_Pos 2 /*!< QEI IES: VELC_EN Position */
+#define QEI_IES_VELC_EN_Msk (0x01UL << QEI_IES_VELC_EN_Pos) /*!< QEI IES: VELC_EN Mask */
+#define QEI_IES_DIR_EN_Pos 3 /*!< QEI IES: DIR_EN Position */
+#define QEI_IES_DIR_EN_Msk (0x01UL << QEI_IES_DIR_EN_Pos) /*!< QEI IES: DIR_EN Mask */
+#define QEI_IES_ERR_EN_Pos 4 /*!< QEI IES: ERR_EN Position */
+#define QEI_IES_ERR_EN_Msk (0x01UL << QEI_IES_ERR_EN_Pos) /*!< QEI IES: ERR_EN Mask */
+#define QEI_IES_ENCLK_EN_Pos 5 /*!< QEI IES: ENCLK_EN Position */
+#define QEI_IES_ENCLK_EN_Msk (0x01UL << QEI_IES_ENCLK_EN_Pos) /*!< QEI IES: ENCLK_EN Mask */
+#define QEI_IES_POS0_Int_Pos 6 /*!< QEI IES: POS0_Int Position */
+#define QEI_IES_POS0_Int_Msk (0x01UL << QEI_IES_POS0_Int_Pos) /*!< QEI IES: POS0_Int Mask */
+#define QEI_IES_POS1_Int_Pos 7 /*!< QEI IES: POS1_Int Position */
+#define QEI_IES_POS1_Int_Msk (0x01UL << QEI_IES_POS1_Int_Pos) /*!< QEI IES: POS1_Int Mask */
+#define QEI_IES_POS2_Int_Pos 8 /*!< QEI IES: POS2_Int Position */
+#define QEI_IES_POS2_Int_Msk (0x01UL << QEI_IES_POS2_Int_Pos) /*!< QEI IES: POS2_Int Mask */
+#define QEI_IES_REV_Int_Pos 9 /*!< QEI IES: REV_Int Position */
+#define QEI_IES_REV_Int_Msk (0x01UL << QEI_IES_REV_Int_Pos) /*!< QEI IES: REV_Int Mask */
+#define QEI_IES_POS0REV_Int_Pos 10 /*!< QEI IES: POS0REV_Int Position */
+#define QEI_IES_POS0REV_Int_Msk (0x01UL << QEI_IES_POS0REV_Int_Pos) /*!< QEI IES: POS0REV_Int Mask */
+#define QEI_IES_POS1REV_Int_Pos 11 /*!< QEI IES: POS1REV_Int Position */
+#define QEI_IES_POS1REV_Int_Msk (0x01UL << QEI_IES_POS1REV_Int_Pos) /*!< QEI IES: POS1REV_Int Mask */
+#define QEI_IES_POS2REV_Int_Pos 12 /*!< QEI IES: POS2REV_Int Position */
+#define QEI_IES_POS2REV_Int_Msk (0x01UL << QEI_IES_POS2REV_Int_Pos) /*!< QEI IES: POS2REV_Int Mask */
+#define QEI_IES_REV1_Int_Pos 13 /*!< QEI IES: REV1_Int Position */
+#define QEI_IES_REV1_Int_Msk (0x01UL << QEI_IES_REV1_Int_Pos) /*!< QEI IES: REV1_Int Mask */
+#define QEI_IES_REV2_Int_Pos 14 /*!< QEI IES: REV2_Int Position */
+#define QEI_IES_REV2_Int_Msk (0x01UL << QEI_IES_REV2_Int_Pos) /*!< QEI IES: REV2_Int Mask */
+#define QEI_IES_MAXPOS_Int_Pos 15 /*!< QEI IES: MAXPOS_Int Position */
+#define QEI_IES_MAXPOS_Int_Msk (0x01UL << QEI_IES_MAXPOS_Int_Pos) /*!< QEI IES: MAXPOS_Int Mask */
+
+// --------------------------------------- QEI_INTSTAT ------------------------------------------
+#define QEI_INTSTAT_INX_Int_Pos 0 /*!< QEI INTSTAT: INX_Int Position */
+#define QEI_INTSTAT_INX_Int_Msk (0x01UL << QEI_INTSTAT_INX_Int_Pos) /*!< QEI INTSTAT: INX_Int Mask */
+#define QEI_INTSTAT_TIM_Int_Pos 1 /*!< QEI INTSTAT: TIM_Int Position */
+#define QEI_INTSTAT_TIM_Int_Msk (0x01UL << QEI_INTSTAT_TIM_Int_Pos) /*!< QEI INTSTAT: TIM_Int Mask */
+#define QEI_INTSTAT_VELC_Int_Pos 2 /*!< QEI INTSTAT: VELC_Int Position */
+#define QEI_INTSTAT_VELC_Int_Msk (0x01UL << QEI_INTSTAT_VELC_Int_Pos) /*!< QEI INTSTAT: VELC_Int Mask */
+#define QEI_INTSTAT_DIR_Int_Pos 3 /*!< QEI INTSTAT: DIR_Int Position */
+#define QEI_INTSTAT_DIR_Int_Msk (0x01UL << QEI_INTSTAT_DIR_Int_Pos) /*!< QEI INTSTAT: DIR_Int Mask */
+#define QEI_INTSTAT_ERR_Int_Pos 4 /*!< QEI INTSTAT: ERR_Int Position */
+#define QEI_INTSTAT_ERR_Int_Msk (0x01UL << QEI_INTSTAT_ERR_Int_Pos) /*!< QEI INTSTAT: ERR_Int Mask */
+#define QEI_INTSTAT_ENCLK_Int_Pos 5 /*!< QEI INTSTAT: ENCLK_Int Position */
+#define QEI_INTSTAT_ENCLK_Int_Msk (0x01UL << QEI_INTSTAT_ENCLK_Int_Pos) /*!< QEI INTSTAT: ENCLK_Int Mask */
+#define QEI_INTSTAT_POS0_Int_Pos 6 /*!< QEI INTSTAT: POS0_Int Position */
+#define QEI_INTSTAT_POS0_Int_Msk (0x01UL << QEI_INTSTAT_POS0_Int_Pos) /*!< QEI INTSTAT: POS0_Int Mask */
+#define QEI_INTSTAT_POS1_Int_Pos 7 /*!< QEI INTSTAT: POS1_Int Position */
+#define QEI_INTSTAT_POS1_Int_Msk (0x01UL << QEI_INTSTAT_POS1_Int_Pos) /*!< QEI INTSTAT: POS1_Int Mask */
+#define QEI_INTSTAT_POS2_Int_Pos 8 /*!< QEI INTSTAT: POS2_Int Position */
+#define QEI_INTSTAT_POS2_Int_Msk (0x01UL << QEI_INTSTAT_POS2_Int_Pos) /*!< QEI INTSTAT: POS2_Int Mask */
+#define QEI_INTSTAT_REV_Int_Pos 9 /*!< QEI INTSTAT: REV_Int Position */
+#define QEI_INTSTAT_REV_Int_Msk (0x01UL << QEI_INTSTAT_REV_Int_Pos) /*!< QEI INTSTAT: REV_Int Mask */
+#define QEI_INTSTAT_POS0REV_Int_Pos 10 /*!< QEI INTSTAT: POS0REV_Int Position */
+#define QEI_INTSTAT_POS0REV_Int_Msk (0x01UL << QEI_INTSTAT_POS0REV_Int_Pos) /*!< QEI INTSTAT: POS0REV_Int Mask */
+#define QEI_INTSTAT_POS1REV_Int_Pos 11 /*!< QEI INTSTAT: POS1REV_Int Position */
+#define QEI_INTSTAT_POS1REV_Int_Msk (0x01UL << QEI_INTSTAT_POS1REV_Int_Pos) /*!< QEI INTSTAT: POS1REV_Int Mask */
+#define QEI_INTSTAT_POS2REV_Int_Pos 12 /*!< QEI INTSTAT: POS2REV_Int Position */
+#define QEI_INTSTAT_POS2REV_Int_Msk (0x01UL << QEI_INTSTAT_POS2REV_Int_Pos) /*!< QEI INTSTAT: POS2REV_Int Mask */
+#define QEI_INTSTAT_REV1_Int_Pos 13 /*!< QEI INTSTAT: REV1_Int Position */
+#define QEI_INTSTAT_REV1_Int_Msk (0x01UL << QEI_INTSTAT_REV1_Int_Pos) /*!< QEI INTSTAT: REV1_Int Mask */
+#define QEI_INTSTAT_REV2_Int_Pos 14 /*!< QEI INTSTAT: REV2_Int Position */
+#define QEI_INTSTAT_REV2_Int_Msk (0x01UL << QEI_INTSTAT_REV2_Int_Pos) /*!< QEI INTSTAT: REV2_Int Mask */
+#define QEI_INTSTAT_MAXPOS_Int_Pos 15 /*!< QEI INTSTAT: MAXPOS_Int Position */
+#define QEI_INTSTAT_MAXPOS_Int_Msk (0x01UL << QEI_INTSTAT_MAXPOS_Int_Pos) /*!< QEI INTSTAT: MAXPOS_Int Mask */
+
+// ----------------------------------------- QEI_IE ---------------------------------------------
+#define QEI_IE_INX_Int_Pos 0 /*!< QEI IE: INX_Int Position */
+#define QEI_IE_INX_Int_Msk (0x01UL << QEI_IE_INX_Int_Pos) /*!< QEI IE: INX_Int Mask */
+#define QEI_IE_TIM_Int_Pos 1 /*!< QEI IE: TIM_Int Position */
+#define QEI_IE_TIM_Int_Msk (0x01UL << QEI_IE_TIM_Int_Pos) /*!< QEI IE: TIM_Int Mask */
+#define QEI_IE_VELC_Int_Pos 2 /*!< QEI IE: VELC_Int Position */
+#define QEI_IE_VELC_Int_Msk (0x01UL << QEI_IE_VELC_Int_Pos) /*!< QEI IE: VELC_Int Mask */
+#define QEI_IE_DIR_Int_Pos 3 /*!< QEI IE: DIR_Int Position */
+#define QEI_IE_DIR_Int_Msk (0x01UL << QEI_IE_DIR_Int_Pos) /*!< QEI IE: DIR_Int Mask */
+#define QEI_IE_ERR_Int_Pos 4 /*!< QEI IE: ERR_Int Position */
+#define QEI_IE_ERR_Int_Msk (0x01UL << QEI_IE_ERR_Int_Pos) /*!< QEI IE: ERR_Int Mask */
+#define QEI_IE_ENCLK_Int_Pos 5 /*!< QEI IE: ENCLK_Int Position */
+#define QEI_IE_ENCLK_Int_Msk (0x01UL << QEI_IE_ENCLK_Int_Pos) /*!< QEI IE: ENCLK_Int Mask */
+#define QEI_IE_POS0_Int_Pos 6 /*!< QEI IE: POS0_Int Position */
+#define QEI_IE_POS0_Int_Msk (0x01UL << QEI_IE_POS0_Int_Pos) /*!< QEI IE: POS0_Int Mask */
+#define QEI_IE_POS1_Int_Pos 7 /*!< QEI IE: POS1_Int Position */
+#define QEI_IE_POS1_Int_Msk (0x01UL << QEI_IE_POS1_Int_Pos) /*!< QEI IE: POS1_Int Mask */
+#define QEI_IE_POS2_Int_Pos 8 /*!< QEI IE: POS2_Int Position */
+#define QEI_IE_POS2_Int_Msk (0x01UL << QEI_IE_POS2_Int_Pos) /*!< QEI IE: POS2_Int Mask */
+#define QEI_IE_REV_Int_Pos 9 /*!< QEI IE: REV_Int Position */
+#define QEI_IE_REV_Int_Msk (0x01UL << QEI_IE_REV_Int_Pos) /*!< QEI IE: REV_Int Mask */
+#define QEI_IE_POS0REV_Int_Pos 10 /*!< QEI IE: POS0REV_Int Position */
+#define QEI_IE_POS0REV_Int_Msk (0x01UL << QEI_IE_POS0REV_Int_Pos) /*!< QEI IE: POS0REV_Int Mask */
+#define QEI_IE_POS1REV_Int_Pos 11 /*!< QEI IE: POS1REV_Int Position */
+#define QEI_IE_POS1REV_Int_Msk (0x01UL << QEI_IE_POS1REV_Int_Pos) /*!< QEI IE: POS1REV_Int Mask */
+#define QEI_IE_POS2REV_Int_Pos 12 /*!< QEI IE: POS2REV_Int Position */
+#define QEI_IE_POS2REV_Int_Msk (0x01UL << QEI_IE_POS2REV_Int_Pos) /*!< QEI IE: POS2REV_Int Mask */
+#define QEI_IE_REV1_Int_Pos 13 /*!< QEI IE: REV1_Int Position */
+#define QEI_IE_REV1_Int_Msk (0x01UL << QEI_IE_REV1_Int_Pos) /*!< QEI IE: REV1_Int Mask */
+#define QEI_IE_REV2_Int_Pos 14 /*!< QEI IE: REV2_Int Position */
+#define QEI_IE_REV2_Int_Msk (0x01UL << QEI_IE_REV2_Int_Pos) /*!< QEI IE: REV2_Int Mask */
+#define QEI_IE_MAXPOS_Int_Pos 15 /*!< QEI IE: MAXPOS_Int Position */
+#define QEI_IE_MAXPOS_Int_Msk (0x01UL << QEI_IE_MAXPOS_Int_Pos) /*!< QEI IE: MAXPOS_Int Mask */
+
+// ----------------------------------------- QEI_CLR --------------------------------------------
+#define QEI_CLR_INX_Int_Pos 0 /*!< QEI CLR: INX_Int Position */
+#define QEI_CLR_INX_Int_Msk (0x01UL << QEI_CLR_INX_Int_Pos) /*!< QEI CLR: INX_Int Mask */
+#define QEI_CLR_TIM_Int_Pos 1 /*!< QEI CLR: TIM_Int Position */
+#define QEI_CLR_TIM_Int_Msk (0x01UL << QEI_CLR_TIM_Int_Pos) /*!< QEI CLR: TIM_Int Mask */
+#define QEI_CLR_VELC_Int_Pos 2 /*!< QEI CLR: VELC_Int Position */
+#define QEI_CLR_VELC_Int_Msk (0x01UL << QEI_CLR_VELC_Int_Pos) /*!< QEI CLR: VELC_Int Mask */
+#define QEI_CLR_DIR_Int_Pos 3 /*!< QEI CLR: DIR_Int Position */
+#define QEI_CLR_DIR_Int_Msk (0x01UL << QEI_CLR_DIR_Int_Pos) /*!< QEI CLR: DIR_Int Mask */
+#define QEI_CLR_ERR_Int_Pos 4 /*!< QEI CLR: ERR_Int Position */
+#define QEI_CLR_ERR_Int_Msk (0x01UL << QEI_CLR_ERR_Int_Pos) /*!< QEI CLR: ERR_Int Mask */
+#define QEI_CLR_ENCLK_Int_Pos 5 /*!< QEI CLR: ENCLK_Int Position */
+#define QEI_CLR_ENCLK_Int_Msk (0x01UL << QEI_CLR_ENCLK_Int_Pos) /*!< QEI CLR: ENCLK_Int Mask */
+#define QEI_CLR_POS0_Int_Pos 6 /*!< QEI CLR: POS0_Int Position */
+#define QEI_CLR_POS0_Int_Msk (0x01UL << QEI_CLR_POS0_Int_Pos) /*!< QEI CLR: POS0_Int Mask */
+#define QEI_CLR_POS1_Int_Pos 7 /*!< QEI CLR: POS1_Int Position */
+#define QEI_CLR_POS1_Int_Msk (0x01UL << QEI_CLR_POS1_Int_Pos) /*!< QEI CLR: POS1_Int Mask */
+#define QEI_CLR_POS2_Int_Pos 8 /*!< QEI CLR: POS2_Int Position */
+#define QEI_CLR_POS2_Int_Msk (0x01UL << QEI_CLR_POS2_Int_Pos) /*!< QEI CLR: POS2_Int Mask */
+#define QEI_CLR_REV_Int_Pos 9 /*!< QEI CLR: REV_Int Position */
+#define QEI_CLR_REV_Int_Msk (0x01UL << QEI_CLR_REV_Int_Pos) /*!< QEI CLR: REV_Int Mask */
+#define QEI_CLR_POS0REV_Int_Pos 10 /*!< QEI CLR: POS0REV_Int Position */
+#define QEI_CLR_POS0REV_Int_Msk (0x01UL << QEI_CLR_POS0REV_Int_Pos) /*!< QEI CLR: POS0REV_Int Mask */
+#define QEI_CLR_POS1REV_Int_Pos 11 /*!< QEI CLR: POS1REV_Int Position */
+#define QEI_CLR_POS1REV_Int_Msk (0x01UL << QEI_CLR_POS1REV_Int_Pos) /*!< QEI CLR: POS1REV_Int Mask */
+#define QEI_CLR_REV1_Int_Pos 13 /*!< QEI CLR: REV1_Int Position */
+#define QEI_CLR_REV1_Int_Msk (0x01UL << QEI_CLR_REV1_Int_Pos) /*!< QEI CLR: REV1_Int Mask */
+#define QEI_CLR_REV2_Int_Pos 14 /*!< QEI CLR: REV2_Int Position */
+#define QEI_CLR_REV2_Int_Msk (0x01UL << QEI_CLR_REV2_Int_Pos) /*!< QEI CLR: REV2_Int Mask */
+#define QEI_CLR_MAXPOS_Int_Pos 15 /*!< QEI CLR: MAXPOS_Int Position */
+#define QEI_CLR_MAXPOS_Int_Msk (0x01UL << QEI_CLR_MAXPOS_Int_Pos) /*!< QEI CLR: MAXPOS_Int Mask */
+
+// ----------------------------------------- QEI_SET --------------------------------------------
+#define QEI_SET_INX_Int_Pos 0 /*!< QEI SET: INX_Int Position */
+#define QEI_SET_INX_Int_Msk (0x01UL << QEI_SET_INX_Int_Pos) /*!< QEI SET: INX_Int Mask */
+#define QEI_SET_TIM_Int_Pos 1 /*!< QEI SET: TIM_Int Position */
+#define QEI_SET_TIM_Int_Msk (0x01UL << QEI_SET_TIM_Int_Pos) /*!< QEI SET: TIM_Int Mask */
+#define QEI_SET_VELC_Int_Pos 2 /*!< QEI SET: VELC_Int Position */
+#define QEI_SET_VELC_Int_Msk (0x01UL << QEI_SET_VELC_Int_Pos) /*!< QEI SET: VELC_Int Mask */
+#define QEI_SET_DIR_Int_Pos 3 /*!< QEI SET: DIR_Int Position */
+#define QEI_SET_DIR_Int_Msk (0x01UL << QEI_SET_DIR_Int_Pos) /*!< QEI SET: DIR_Int Mask */
+#define QEI_SET_ERR_Int_Pos 4 /*!< QEI SET: ERR_Int Position */
+#define QEI_SET_ERR_Int_Msk (0x01UL << QEI_SET_ERR_Int_Pos) /*!< QEI SET: ERR_Int Mask */
+#define QEI_SET_ENCLK_Int_Pos 5 /*!< QEI SET: ENCLK_Int Position */
+#define QEI_SET_ENCLK_Int_Msk (0x01UL << QEI_SET_ENCLK_Int_Pos) /*!< QEI SET: ENCLK_Int Mask */
+#define QEI_SET_POS0_Int_Pos 6 /*!< QEI SET: POS0_Int Position */
+#define QEI_SET_POS0_Int_Msk (0x01UL << QEI_SET_POS0_Int_Pos) /*!< QEI SET: POS0_Int Mask */
+#define QEI_SET_POS1_Int_Pos 7 /*!< QEI SET: POS1_Int Position */
+#define QEI_SET_POS1_Int_Msk (0x01UL << QEI_SET_POS1_Int_Pos) /*!< QEI SET: POS1_Int Mask */
+#define QEI_SET_POS2_Int_Pos 8 /*!< QEI SET: POS2_Int Position */
+#define QEI_SET_POS2_Int_Msk (0x01UL << QEI_SET_POS2_Int_Pos) /*!< QEI SET: POS2_Int Mask */
+#define QEI_SET_REV_Int_Pos 9 /*!< QEI SET: REV_Int Position */
+#define QEI_SET_REV_Int_Msk (0x01UL << QEI_SET_REV_Int_Pos) /*!< QEI SET: REV_Int Mask */
+#define QEI_SET_POS0REV_Int_Pos 10 /*!< QEI SET: POS0REV_Int Position */
+#define QEI_SET_POS0REV_Int_Msk (0x01UL << QEI_SET_POS0REV_Int_Pos) /*!< QEI SET: POS0REV_Int Mask */
+#define QEI_SET_POS1REV_Int_Pos 11 /*!< QEI SET: POS1REV_Int Position */
+#define QEI_SET_POS1REV_Int_Msk (0x01UL << QEI_SET_POS1REV_Int_Pos) /*!< QEI SET: POS1REV_Int Mask */
+#define QEI_SET_POS2REV_Int_Pos 12 /*!< QEI SET: POS2REV_Int Position */
+#define QEI_SET_POS2REV_Int_Msk (0x01UL << QEI_SET_POS2REV_Int_Pos) /*!< QEI SET: POS2REV_Int Mask */
+#define QEI_SET_REV1_Int_Pos 13 /*!< QEI SET: REV1_Int Position */
+#define QEI_SET_REV1_Int_Msk (0x01UL << QEI_SET_REV1_Int_Pos) /*!< QEI SET: REV1_Int Mask */
+#define QEI_SET_REV2_Int_Pos 14 /*!< QEI SET: REV2_Int Position */
+#define QEI_SET_REV2_Int_Msk (0x01UL << QEI_SET_REV2_Int_Pos) /*!< QEI SET: REV2_Int Mask */
+#define QEI_SET_MAXPOS_Int_Pos 15 /*!< QEI SET: MAXPOS_Int Position */
+#define QEI_SET_MAXPOS_Int_Msk (0x01UL << QEI_SET_MAXPOS_Int_Pos) /*!< QEI SET: MAXPOS_Int Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GIMA Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ------------------------------------- GIMA_CAP0_0_IN -----------------------------------------
+#define GIMA_CAP0_0_IN_INV_Pos 0 /*!< GIMA CAP0_0_IN: INV Position */
+#define GIMA_CAP0_0_IN_INV_Msk (0x01UL << GIMA_CAP0_0_IN_INV_Pos) /*!< GIMA CAP0_0_IN: INV Mask */
+#define GIMA_CAP0_0_IN_EDGE_Pos 1 /*!< GIMA CAP0_0_IN: EDGE Position */
+#define GIMA_CAP0_0_IN_EDGE_Msk (0x01UL << GIMA_CAP0_0_IN_EDGE_Pos) /*!< GIMA CAP0_0_IN: EDGE Mask */
+#define GIMA_CAP0_0_IN_SYNCH_Pos 2 /*!< GIMA CAP0_0_IN: SYNCH Position */
+#define GIMA_CAP0_0_IN_SYNCH_Msk (0x01UL << GIMA_CAP0_0_IN_SYNCH_Pos) /*!< GIMA CAP0_0_IN: SYNCH Mask */
+#define GIMA_CAP0_0_IN_PULSE_Pos 3 /*!< GIMA CAP0_0_IN: PULSE Position */
+#define GIMA_CAP0_0_IN_PULSE_Msk (0x01UL << GIMA_CAP0_0_IN_PULSE_Pos) /*!< GIMA CAP0_0_IN: PULSE Mask */
+#define GIMA_CAP0_0_IN_SELECT_Pos 4 /*!< GIMA CAP0_0_IN: SELECT Position */
+#define GIMA_CAP0_0_IN_SELECT_Msk (0x0fUL << GIMA_CAP0_0_IN_SELECT_Pos) /*!< GIMA CAP0_0_IN: SELECT Mask */
+
+// ------------------------------------- GIMA_CAP0_1_IN -----------------------------------------
+#define GIMA_CAP0_1_IN_INV_Pos 0 /*!< GIMA CAP0_1_IN: INV Position */
+#define GIMA_CAP0_1_IN_INV_Msk (0x01UL << GIMA_CAP0_1_IN_INV_Pos) /*!< GIMA CAP0_1_IN: INV Mask */
+#define GIMA_CAP0_1_IN_EDGE_Pos 1 /*!< GIMA CAP0_1_IN: EDGE Position */
+#define GIMA_CAP0_1_IN_EDGE_Msk (0x01UL << GIMA_CAP0_1_IN_EDGE_Pos) /*!< GIMA CAP0_1_IN: EDGE Mask */
+#define GIMA_CAP0_1_IN_SYNCH_Pos 2 /*!< GIMA CAP0_1_IN: SYNCH Position */
+#define GIMA_CAP0_1_IN_SYNCH_Msk (0x01UL << GIMA_CAP0_1_IN_SYNCH_Pos) /*!< GIMA CAP0_1_IN: SYNCH Mask */
+#define GIMA_CAP0_1_IN_PULSE_Pos 3 /*!< GIMA CAP0_1_IN: PULSE Position */
+#define GIMA_CAP0_1_IN_PULSE_Msk (0x01UL << GIMA_CAP0_1_IN_PULSE_Pos) /*!< GIMA CAP0_1_IN: PULSE Mask */
+#define GIMA_CAP0_1_IN_SELECT_Pos 4 /*!< GIMA CAP0_1_IN: SELECT Position */
+#define GIMA_CAP0_1_IN_SELECT_Msk (0x0fUL << GIMA_CAP0_1_IN_SELECT_Pos) /*!< GIMA CAP0_1_IN: SELECT Mask */
+
+// ------------------------------------- GIMA_CAP0_2_IN -----------------------------------------
+#define GIMA_CAP0_2_IN_INV_Pos 0 /*!< GIMA CAP0_2_IN: INV Position */
+#define GIMA_CAP0_2_IN_INV_Msk (0x01UL << GIMA_CAP0_2_IN_INV_Pos) /*!< GIMA CAP0_2_IN: INV Mask */
+#define GIMA_CAP0_2_IN_EDGE_Pos 1 /*!< GIMA CAP0_2_IN: EDGE Position */
+#define GIMA_CAP0_2_IN_EDGE_Msk (0x01UL << GIMA_CAP0_2_IN_EDGE_Pos) /*!< GIMA CAP0_2_IN: EDGE Mask */
+#define GIMA_CAP0_2_IN_SYNCH_Pos 2 /*!< GIMA CAP0_2_IN: SYNCH Position */
+#define GIMA_CAP0_2_IN_SYNCH_Msk (0x01UL << GIMA_CAP0_2_IN_SYNCH_Pos) /*!< GIMA CAP0_2_IN: SYNCH Mask */
+#define GIMA_CAP0_2_IN_PULSE_Pos 3 /*!< GIMA CAP0_2_IN: PULSE Position */
+#define GIMA_CAP0_2_IN_PULSE_Msk (0x01UL << GIMA_CAP0_2_IN_PULSE_Pos) /*!< GIMA CAP0_2_IN: PULSE Mask */
+#define GIMA_CAP0_2_IN_SELECT_Pos 4 /*!< GIMA CAP0_2_IN: SELECT Position */
+#define GIMA_CAP0_2_IN_SELECT_Msk (0x0fUL << GIMA_CAP0_2_IN_SELECT_Pos) /*!< GIMA CAP0_2_IN: SELECT Mask */
+
+// ------------------------------------- GIMA_CAP0_3_IN -----------------------------------------
+#define GIMA_CAP0_3_IN_INV_Pos 0 /*!< GIMA CAP0_3_IN: INV Position */
+#define GIMA_CAP0_3_IN_INV_Msk (0x01UL << GIMA_CAP0_3_IN_INV_Pos) /*!< GIMA CAP0_3_IN: INV Mask */
+#define GIMA_CAP0_3_IN_EDGE_Pos 1 /*!< GIMA CAP0_3_IN: EDGE Position */
+#define GIMA_CAP0_3_IN_EDGE_Msk (0x01UL << GIMA_CAP0_3_IN_EDGE_Pos) /*!< GIMA CAP0_3_IN: EDGE Mask */
+#define GIMA_CAP0_3_IN_SYNCH_Pos 2 /*!< GIMA CAP0_3_IN: SYNCH Position */
+#define GIMA_CAP0_3_IN_SYNCH_Msk (0x01UL << GIMA_CAP0_3_IN_SYNCH_Pos) /*!< GIMA CAP0_3_IN: SYNCH Mask */
+#define GIMA_CAP0_3_IN_PULSE_Pos 3 /*!< GIMA CAP0_3_IN: PULSE Position */
+#define GIMA_CAP0_3_IN_PULSE_Msk (0x01UL << GIMA_CAP0_3_IN_PULSE_Pos) /*!< GIMA CAP0_3_IN: PULSE Mask */
+#define GIMA_CAP0_3_IN_SELECT_Pos 4 /*!< GIMA CAP0_3_IN: SELECT Position */
+#define GIMA_CAP0_3_IN_SELECT_Msk (0x0fUL << GIMA_CAP0_3_IN_SELECT_Pos) /*!< GIMA CAP0_3_IN: SELECT Mask */
+
+// ------------------------------------- GIMA_CAP1_0_IN -----------------------------------------
+#define GIMA_CAP1_0_IN_INV_Pos 0 /*!< GIMA CAP1_0_IN: INV Position */
+#define GIMA_CAP1_0_IN_INV_Msk (0x01UL << GIMA_CAP1_0_IN_INV_Pos) /*!< GIMA CAP1_0_IN: INV Mask */
+#define GIMA_CAP1_0_IN_EDGE_Pos 1 /*!< GIMA CAP1_0_IN: EDGE Position */
+#define GIMA_CAP1_0_IN_EDGE_Msk (0x01UL << GIMA_CAP1_0_IN_EDGE_Pos) /*!< GIMA CAP1_0_IN: EDGE Mask */
+#define GIMA_CAP1_0_IN_SYNCH_Pos 2 /*!< GIMA CAP1_0_IN: SYNCH Position */
+#define GIMA_CAP1_0_IN_SYNCH_Msk (0x01UL << GIMA_CAP1_0_IN_SYNCH_Pos) /*!< GIMA CAP1_0_IN: SYNCH Mask */
+#define GIMA_CAP1_0_IN_PULSE_Pos 3 /*!< GIMA CAP1_0_IN: PULSE Position */
+#define GIMA_CAP1_0_IN_PULSE_Msk (0x01UL << GIMA_CAP1_0_IN_PULSE_Pos) /*!< GIMA CAP1_0_IN: PULSE Mask */
+#define GIMA_CAP1_0_IN_SELECT_Pos 4 /*!< GIMA CAP1_0_IN: SELECT Position */
+#define GIMA_CAP1_0_IN_SELECT_Msk (0x0fUL << GIMA_CAP1_0_IN_SELECT_Pos) /*!< GIMA CAP1_0_IN: SELECT Mask */
+
+// ------------------------------------- GIMA_CAP1_1_IN -----------------------------------------
+#define GIMA_CAP1_1_IN_INV_Pos 0 /*!< GIMA CAP1_1_IN: INV Position */
+#define GIMA_CAP1_1_IN_INV_Msk (0x01UL << GIMA_CAP1_1_IN_INV_Pos) /*!< GIMA CAP1_1_IN: INV Mask */
+#define GIMA_CAP1_1_IN_EDGE_Pos 1 /*!< GIMA CAP1_1_IN: EDGE Position */
+#define GIMA_CAP1_1_IN_EDGE_Msk (0x01UL << GIMA_CAP1_1_IN_EDGE_Pos) /*!< GIMA CAP1_1_IN: EDGE Mask */
+#define GIMA_CAP1_1_IN_SYNCH_Pos 2 /*!< GIMA CAP1_1_IN: SYNCH Position */
+#define GIMA_CAP1_1_IN_SYNCH_Msk (0x01UL << GIMA_CAP1_1_IN_SYNCH_Pos) /*!< GIMA CAP1_1_IN: SYNCH Mask */
+#define GIMA_CAP1_1_IN_PULSE_Pos 3 /*!< GIMA CAP1_1_IN: PULSE Position */
+#define GIMA_CAP1_1_IN_PULSE_Msk (0x01UL << GIMA_CAP1_1_IN_PULSE_Pos) /*!< GIMA CAP1_1_IN: PULSE Mask */
+#define GIMA_CAP1_1_IN_SELECT_Pos 4 /*!< GIMA CAP1_1_IN: SELECT Position */
+#define GIMA_CAP1_1_IN_SELECT_Msk (0x0fUL << GIMA_CAP1_1_IN_SELECT_Pos) /*!< GIMA CAP1_1_IN: SELECT Mask */
+
+// ------------------------------------- GIMA_CAP1_2_IN -----------------------------------------
+#define GIMA_CAP1_2_IN_INV_Pos 0 /*!< GIMA CAP1_2_IN: INV Position */
+#define GIMA_CAP1_2_IN_INV_Msk (0x01UL << GIMA_CAP1_2_IN_INV_Pos) /*!< GIMA CAP1_2_IN: INV Mask */
+#define GIMA_CAP1_2_IN_EDGE_Pos 1 /*!< GIMA CAP1_2_IN: EDGE Position */
+#define GIMA_CAP1_2_IN_EDGE_Msk (0x01UL << GIMA_CAP1_2_IN_EDGE_Pos) /*!< GIMA CAP1_2_IN: EDGE Mask */
+#define GIMA_CAP1_2_IN_SYNCH_Pos 2 /*!< GIMA CAP1_2_IN: SYNCH Position */
+#define GIMA_CAP1_2_IN_SYNCH_Msk (0x01UL << GIMA_CAP1_2_IN_SYNCH_Pos) /*!< GIMA CAP1_2_IN: SYNCH Mask */
+#define GIMA_CAP1_2_IN_PULSE_Pos 3 /*!< GIMA CAP1_2_IN: PULSE Position */
+#define GIMA_CAP1_2_IN_PULSE_Msk (0x01UL << GIMA_CAP1_2_IN_PULSE_Pos) /*!< GIMA CAP1_2_IN: PULSE Mask */
+#define GIMA_CAP1_2_IN_SELECT_Pos 4 /*!< GIMA CAP1_2_IN: SELECT Position */
+#define GIMA_CAP1_2_IN_SELECT_Msk (0x0fUL << GIMA_CAP1_2_IN_SELECT_Pos) /*!< GIMA CAP1_2_IN: SELECT Mask */
+
+// ------------------------------------- GIMA_CAP1_3_IN -----------------------------------------
+#define GIMA_CAP1_3_IN_INV_Pos 0 /*!< GIMA CAP1_3_IN: INV Position */
+#define GIMA_CAP1_3_IN_INV_Msk (0x01UL << GIMA_CAP1_3_IN_INV_Pos) /*!< GIMA CAP1_3_IN: INV Mask */
+#define GIMA_CAP1_3_IN_EDGE_Pos 1 /*!< GIMA CAP1_3_IN: EDGE Position */
+#define GIMA_CAP1_3_IN_EDGE_Msk (0x01UL << GIMA_CAP1_3_IN_EDGE_Pos) /*!< GIMA CAP1_3_IN: EDGE Mask */
+#define GIMA_CAP1_3_IN_SYNCH_Pos 2 /*!< GIMA CAP1_3_IN: SYNCH Position */
+#define GIMA_CAP1_3_IN_SYNCH_Msk (0x01UL << GIMA_CAP1_3_IN_SYNCH_Pos) /*!< GIMA CAP1_3_IN: SYNCH Mask */
+#define GIMA_CAP1_3_IN_PULSE_Pos 3 /*!< GIMA CAP1_3_IN: PULSE Position */
+#define GIMA_CAP1_3_IN_PULSE_Msk (0x01UL << GIMA_CAP1_3_IN_PULSE_Pos) /*!< GIMA CAP1_3_IN: PULSE Mask */
+#define GIMA_CAP1_3_IN_SELECT_Pos 4 /*!< GIMA CAP1_3_IN: SELECT Position */
+#define GIMA_CAP1_3_IN_SELECT_Msk (0x0fUL << GIMA_CAP1_3_IN_SELECT_Pos) /*!< GIMA CAP1_3_IN: SELECT Mask */
+
+// ------------------------------------- GIMA_CAP2_0_IN -----------------------------------------
+#define GIMA_CAP2_0_IN_INV_Pos 0 /*!< GIMA CAP2_0_IN: INV Position */
+#define GIMA_CAP2_0_IN_INV_Msk (0x01UL << GIMA_CAP2_0_IN_INV_Pos) /*!< GIMA CAP2_0_IN: INV Mask */
+#define GIMA_CAP2_0_IN_EDGE_Pos 1 /*!< GIMA CAP2_0_IN: EDGE Position */
+#define GIMA_CAP2_0_IN_EDGE_Msk (0x01UL << GIMA_CAP2_0_IN_EDGE_Pos) /*!< GIMA CAP2_0_IN: EDGE Mask */
+#define GIMA_CAP2_0_IN_SYNCH_Pos 2 /*!< GIMA CAP2_0_IN: SYNCH Position */
+#define GIMA_CAP2_0_IN_SYNCH_Msk (0x01UL << GIMA_CAP2_0_IN_SYNCH_Pos) /*!< GIMA CAP2_0_IN: SYNCH Mask */
+#define GIMA_CAP2_0_IN_PULSE_Pos 3 /*!< GIMA CAP2_0_IN: PULSE Position */
+#define GIMA_CAP2_0_IN_PULSE_Msk (0x01UL << GIMA_CAP2_0_IN_PULSE_Pos) /*!< GIMA CAP2_0_IN: PULSE Mask */
+#define GIMA_CAP2_0_IN_SELECT_Pos 4 /*!< GIMA CAP2_0_IN: SELECT Position */
+#define GIMA_CAP2_0_IN_SELECT_Msk (0x0fUL << GIMA_CAP2_0_IN_SELECT_Pos) /*!< GIMA CAP2_0_IN: SELECT Mask */
+
+// ------------------------------------- GIMA_CAP2_1_IN -----------------------------------------
+#define GIMA_CAP2_1_IN_INV_Pos 0 /*!< GIMA CAP2_1_IN: INV Position */
+#define GIMA_CAP2_1_IN_INV_Msk (0x01UL << GIMA_CAP2_1_IN_INV_Pos) /*!< GIMA CAP2_1_IN: INV Mask */
+#define GIMA_CAP2_1_IN_EDGE_Pos 1 /*!< GIMA CAP2_1_IN: EDGE Position */
+#define GIMA_CAP2_1_IN_EDGE_Msk (0x01UL << GIMA_CAP2_1_IN_EDGE_Pos) /*!< GIMA CAP2_1_IN: EDGE Mask */
+#define GIMA_CAP2_1_IN_SYNCH_Pos 2 /*!< GIMA CAP2_1_IN: SYNCH Position */
+#define GIMA_CAP2_1_IN_SYNCH_Msk (0x01UL << GIMA_CAP2_1_IN_SYNCH_Pos) /*!< GIMA CAP2_1_IN: SYNCH Mask */
+#define GIMA_CAP2_1_IN_PULSE_Pos 3 /*!< GIMA CAP2_1_IN: PULSE Position */
+#define GIMA_CAP2_1_IN_PULSE_Msk (0x01UL << GIMA_CAP2_1_IN_PULSE_Pos) /*!< GIMA CAP2_1_IN: PULSE Mask */
+#define GIMA_CAP2_1_IN_SELECT_Pos 4 /*!< GIMA CAP2_1_IN: SELECT Position */
+#define GIMA_CAP2_1_IN_SELECT_Msk (0x0fUL << GIMA_CAP2_1_IN_SELECT_Pos) /*!< GIMA CAP2_1_IN: SELECT Mask */
+
+// ------------------------------------- GIMA_CAP2_2_IN -----------------------------------------
+#define GIMA_CAP2_2_IN_INV_Pos 0 /*!< GIMA CAP2_2_IN: INV Position */
+#define GIMA_CAP2_2_IN_INV_Msk (0x01UL << GIMA_CAP2_2_IN_INV_Pos) /*!< GIMA CAP2_2_IN: INV Mask */
+#define GIMA_CAP2_2_IN_EDGE_Pos 1 /*!< GIMA CAP2_2_IN: EDGE Position */
+#define GIMA_CAP2_2_IN_EDGE_Msk (0x01UL << GIMA_CAP2_2_IN_EDGE_Pos) /*!< GIMA CAP2_2_IN: EDGE Mask */
+#define GIMA_CAP2_2_IN_SYNCH_Pos 2 /*!< GIMA CAP2_2_IN: SYNCH Position */
+#define GIMA_CAP2_2_IN_SYNCH_Msk (0x01UL << GIMA_CAP2_2_IN_SYNCH_Pos) /*!< GIMA CAP2_2_IN: SYNCH Mask */
+#define GIMA_CAP2_2_IN_PULSE_Pos 3 /*!< GIMA CAP2_2_IN: PULSE Position */
+#define GIMA_CAP2_2_IN_PULSE_Msk (0x01UL << GIMA_CAP2_2_IN_PULSE_Pos) /*!< GIMA CAP2_2_IN: PULSE Mask */
+#define GIMA_CAP2_2_IN_SELECT_Pos 4 /*!< GIMA CAP2_2_IN: SELECT Position */
+#define GIMA_CAP2_2_IN_SELECT_Msk (0x0fUL << GIMA_CAP2_2_IN_SELECT_Pos) /*!< GIMA CAP2_2_IN: SELECT Mask */
+
+// ------------------------------------- GIMA_CAP2_3_IN -----------------------------------------
+#define GIMA_CAP2_3_IN_INV_Pos 0 /*!< GIMA CAP2_3_IN: INV Position */
+#define GIMA_CAP2_3_IN_INV_Msk (0x01UL << GIMA_CAP2_3_IN_INV_Pos) /*!< GIMA CAP2_3_IN: INV Mask */
+#define GIMA_CAP2_3_IN_EDGE_Pos 1 /*!< GIMA CAP2_3_IN: EDGE Position */
+#define GIMA_CAP2_3_IN_EDGE_Msk (0x01UL << GIMA_CAP2_3_IN_EDGE_Pos) /*!< GIMA CAP2_3_IN: EDGE Mask */
+#define GIMA_CAP2_3_IN_SYNCH_Pos 2 /*!< GIMA CAP2_3_IN: SYNCH Position */
+#define GIMA_CAP2_3_IN_SYNCH_Msk (0x01UL << GIMA_CAP2_3_IN_SYNCH_Pos) /*!< GIMA CAP2_3_IN: SYNCH Mask */
+#define GIMA_CAP2_3_IN_PULSE_Pos 3 /*!< GIMA CAP2_3_IN: PULSE Position */
+#define GIMA_CAP2_3_IN_PULSE_Msk (0x01UL << GIMA_CAP2_3_IN_PULSE_Pos) /*!< GIMA CAP2_3_IN: PULSE Mask */
+#define GIMA_CAP2_3_IN_SELECT_Pos 4 /*!< GIMA CAP2_3_IN: SELECT Position */
+#define GIMA_CAP2_3_IN_SELECT_Msk (0x0fUL << GIMA_CAP2_3_IN_SELECT_Pos) /*!< GIMA CAP2_3_IN: SELECT Mask */
+
+// ------------------------------------- GIMA_CAP3_0_IN -----------------------------------------
+#define GIMA_CAP3_0_IN_INV_Pos 0 /*!< GIMA CAP3_0_IN: INV Position */
+#define GIMA_CAP3_0_IN_INV_Msk (0x01UL << GIMA_CAP3_0_IN_INV_Pos) /*!< GIMA CAP3_0_IN: INV Mask */
+#define GIMA_CAP3_0_IN_EDGE_Pos 1 /*!< GIMA CAP3_0_IN: EDGE Position */
+#define GIMA_CAP3_0_IN_EDGE_Msk (0x01UL << GIMA_CAP3_0_IN_EDGE_Pos) /*!< GIMA CAP3_0_IN: EDGE Mask */
+#define GIMA_CAP3_0_IN_SYNCH_Pos 2 /*!< GIMA CAP3_0_IN: SYNCH Position */
+#define GIMA_CAP3_0_IN_SYNCH_Msk (0x01UL << GIMA_CAP3_0_IN_SYNCH_Pos) /*!< GIMA CAP3_0_IN: SYNCH Mask */
+#define GIMA_CAP3_0_IN_PULSE_Pos 3 /*!< GIMA CAP3_0_IN: PULSE Position */
+#define GIMA_CAP3_0_IN_PULSE_Msk (0x01UL << GIMA_CAP3_0_IN_PULSE_Pos) /*!< GIMA CAP3_0_IN: PULSE Mask */
+#define GIMA_CAP3_0_IN_SELECT_Pos 4 /*!< GIMA CAP3_0_IN: SELECT Position */
+#define GIMA_CAP3_0_IN_SELECT_Msk (0x0fUL << GIMA_CAP3_0_IN_SELECT_Pos) /*!< GIMA CAP3_0_IN: SELECT Mask */
+
+// ------------------------------------- GIMA_CAP3_1_IN -----------------------------------------
+#define GIMA_CAP3_1_IN_INV_Pos 0 /*!< GIMA CAP3_1_IN: INV Position */
+#define GIMA_CAP3_1_IN_INV_Msk (0x01UL << GIMA_CAP3_1_IN_INV_Pos) /*!< GIMA CAP3_1_IN: INV Mask */
+#define GIMA_CAP3_1_IN_EDGE_Pos 1 /*!< GIMA CAP3_1_IN: EDGE Position */
+#define GIMA_CAP3_1_IN_EDGE_Msk (0x01UL << GIMA_CAP3_1_IN_EDGE_Pos) /*!< GIMA CAP3_1_IN: EDGE Mask */
+#define GIMA_CAP3_1_IN_SYNCH_Pos 2 /*!< GIMA CAP3_1_IN: SYNCH Position */
+#define GIMA_CAP3_1_IN_SYNCH_Msk (0x01UL << GIMA_CAP3_1_IN_SYNCH_Pos) /*!< GIMA CAP3_1_IN: SYNCH Mask */
+#define GIMA_CAP3_1_IN_PULSE_Pos 3 /*!< GIMA CAP3_1_IN: PULSE Position */
+#define GIMA_CAP3_1_IN_PULSE_Msk (0x01UL << GIMA_CAP3_1_IN_PULSE_Pos) /*!< GIMA CAP3_1_IN: PULSE Mask */
+#define GIMA_CAP3_1_IN_SELECT_Pos 4 /*!< GIMA CAP3_1_IN: SELECT Position */
+#define GIMA_CAP3_1_IN_SELECT_Msk (0x0fUL << GIMA_CAP3_1_IN_SELECT_Pos) /*!< GIMA CAP3_1_IN: SELECT Mask */
+
+// ------------------------------------- GIMA_CAP3_2_IN -----------------------------------------
+#define GIMA_CAP3_2_IN_INV_Pos 0 /*!< GIMA CAP3_2_IN: INV Position */
+#define GIMA_CAP3_2_IN_INV_Msk (0x01UL << GIMA_CAP3_2_IN_INV_Pos) /*!< GIMA CAP3_2_IN: INV Mask */
+#define GIMA_CAP3_2_IN_EDGE_Pos 1 /*!< GIMA CAP3_2_IN: EDGE Position */
+#define GIMA_CAP3_2_IN_EDGE_Msk (0x01UL << GIMA_CAP3_2_IN_EDGE_Pos) /*!< GIMA CAP3_2_IN: EDGE Mask */
+#define GIMA_CAP3_2_IN_SYNCH_Pos 2 /*!< GIMA CAP3_2_IN: SYNCH Position */
+#define GIMA_CAP3_2_IN_SYNCH_Msk (0x01UL << GIMA_CAP3_2_IN_SYNCH_Pos) /*!< GIMA CAP3_2_IN: SYNCH Mask */
+#define GIMA_CAP3_2_IN_PULSE_Pos 3 /*!< GIMA CAP3_2_IN: PULSE Position */
+#define GIMA_CAP3_2_IN_PULSE_Msk (0x01UL << GIMA_CAP3_2_IN_PULSE_Pos) /*!< GIMA CAP3_2_IN: PULSE Mask */
+#define GIMA_CAP3_2_IN_SELECT_Pos 4 /*!< GIMA CAP3_2_IN: SELECT Position */
+#define GIMA_CAP3_2_IN_SELECT_Msk (0x0fUL << GIMA_CAP3_2_IN_SELECT_Pos) /*!< GIMA CAP3_2_IN: SELECT Mask */
+
+// ------------------------------------- GIMA_CAP3_3_IN -----------------------------------------
+#define GIMA_CAP3_3_IN_INV_Pos 0 /*!< GIMA CAP3_3_IN: INV Position */
+#define GIMA_CAP3_3_IN_INV_Msk (0x01UL << GIMA_CAP3_3_IN_INV_Pos) /*!< GIMA CAP3_3_IN: INV Mask */
+#define GIMA_CAP3_3_IN_EDGE_Pos 1 /*!< GIMA CAP3_3_IN: EDGE Position */
+#define GIMA_CAP3_3_IN_EDGE_Msk (0x01UL << GIMA_CAP3_3_IN_EDGE_Pos) /*!< GIMA CAP3_3_IN: EDGE Mask */
+#define GIMA_CAP3_3_IN_SYNCH_Pos 2 /*!< GIMA CAP3_3_IN: SYNCH Position */
+#define GIMA_CAP3_3_IN_SYNCH_Msk (0x01UL << GIMA_CAP3_3_IN_SYNCH_Pos) /*!< GIMA CAP3_3_IN: SYNCH Mask */
+#define GIMA_CAP3_3_IN_PULSE_Pos 3 /*!< GIMA CAP3_3_IN: PULSE Position */
+#define GIMA_CAP3_3_IN_PULSE_Msk (0x01UL << GIMA_CAP3_3_IN_PULSE_Pos) /*!< GIMA CAP3_3_IN: PULSE Mask */
+#define GIMA_CAP3_3_IN_SELECT_Pos 4 /*!< GIMA CAP3_3_IN: SELECT Position */
+#define GIMA_CAP3_3_IN_SELECT_Msk (0x0fUL << GIMA_CAP3_3_IN_SELECT_Pos) /*!< GIMA CAP3_3_IN: SELECT Mask */
+
+// ------------------------------------- GIMA_CTIN_0_IN -----------------------------------------
+#define GIMA_CTIN_0_IN_INV_Pos 0 /*!< GIMA CTIN_0_IN: INV Position */
+#define GIMA_CTIN_0_IN_INV_Msk (0x01UL << GIMA_CTIN_0_IN_INV_Pos) /*!< GIMA CTIN_0_IN: INV Mask */
+#define GIMA_CTIN_0_IN_EDGE_Pos 1 /*!< GIMA CTIN_0_IN: EDGE Position */
+#define GIMA_CTIN_0_IN_EDGE_Msk (0x01UL << GIMA_CTIN_0_IN_EDGE_Pos) /*!< GIMA CTIN_0_IN: EDGE Mask */
+#define GIMA_CTIN_0_IN_SYNCH_Pos 2 /*!< GIMA CTIN_0_IN: SYNCH Position */
+#define GIMA_CTIN_0_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_0_IN_SYNCH_Pos) /*!< GIMA CTIN_0_IN: SYNCH Mask */
+#define GIMA_CTIN_0_IN_PULSE_Pos 3 /*!< GIMA CTIN_0_IN: PULSE Position */
+#define GIMA_CTIN_0_IN_PULSE_Msk (0x01UL << GIMA_CTIN_0_IN_PULSE_Pos) /*!< GIMA CTIN_0_IN: PULSE Mask */
+#define GIMA_CTIN_0_IN_SELECT_Pos 4 /*!< GIMA CTIN_0_IN: SELECT Position */
+#define GIMA_CTIN_0_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_0_IN_SELECT_Pos) /*!< GIMA CTIN_0_IN: SELECT Mask */
+
+// ------------------------------------- GIMA_CTIN_1_IN -----------------------------------------
+#define GIMA_CTIN_1_IN_INV_Pos 0 /*!< GIMA CTIN_1_IN: INV Position */
+#define GIMA_CTIN_1_IN_INV_Msk (0x01UL << GIMA_CTIN_1_IN_INV_Pos) /*!< GIMA CTIN_1_IN: INV Mask */
+#define GIMA_CTIN_1_IN_EDGE_Pos 1 /*!< GIMA CTIN_1_IN: EDGE Position */
+#define GIMA_CTIN_1_IN_EDGE_Msk (0x01UL << GIMA_CTIN_1_IN_EDGE_Pos) /*!< GIMA CTIN_1_IN: EDGE Mask */
+#define GIMA_CTIN_1_IN_SYNCH_Pos 2 /*!< GIMA CTIN_1_IN: SYNCH Position */
+#define GIMA_CTIN_1_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_1_IN_SYNCH_Pos) /*!< GIMA CTIN_1_IN: SYNCH Mask */
+#define GIMA_CTIN_1_IN_PULSE_Pos 3 /*!< GIMA CTIN_1_IN: PULSE Position */
+#define GIMA_CTIN_1_IN_PULSE_Msk (0x01UL << GIMA_CTIN_1_IN_PULSE_Pos) /*!< GIMA CTIN_1_IN: PULSE Mask */
+#define GIMA_CTIN_1_IN_SELECT_Pos 4 /*!< GIMA CTIN_1_IN: SELECT Position */
+#define GIMA_CTIN_1_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_1_IN_SELECT_Pos) /*!< GIMA CTIN_1_IN: SELECT Mask */
+
+// ------------------------------------- GIMA_CTIN_2_IN -----------------------------------------
+#define GIMA_CTIN_2_IN_INV_Pos 0 /*!< GIMA CTIN_2_IN: INV Position */
+#define GIMA_CTIN_2_IN_INV_Msk (0x01UL << GIMA_CTIN_2_IN_INV_Pos) /*!< GIMA CTIN_2_IN: INV Mask */
+#define GIMA_CTIN_2_IN_EDGE_Pos 1 /*!< GIMA CTIN_2_IN: EDGE Position */
+#define GIMA_CTIN_2_IN_EDGE_Msk (0x01UL << GIMA_CTIN_2_IN_EDGE_Pos) /*!< GIMA CTIN_2_IN: EDGE Mask */
+#define GIMA_CTIN_2_IN_SYNCH_Pos 2 /*!< GIMA CTIN_2_IN: SYNCH Position */
+#define GIMA_CTIN_2_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_2_IN_SYNCH_Pos) /*!< GIMA CTIN_2_IN: SYNCH Mask */
+#define GIMA_CTIN_2_IN_PULSE_Pos 3 /*!< GIMA CTIN_2_IN: PULSE Position */
+#define GIMA_CTIN_2_IN_PULSE_Msk (0x01UL << GIMA_CTIN_2_IN_PULSE_Pos) /*!< GIMA CTIN_2_IN: PULSE Mask */
+#define GIMA_CTIN_2_IN_SELECT_Pos 4 /*!< GIMA CTIN_2_IN: SELECT Position */
+#define GIMA_CTIN_2_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_2_IN_SELECT_Pos) /*!< GIMA CTIN_2_IN: SELECT Mask */
+
+// ------------------------------------- GIMA_CTIN_3_IN -----------------------------------------
+#define GIMA_CTIN_3_IN_INV_Pos 0 /*!< GIMA CTIN_3_IN: INV Position */
+#define GIMA_CTIN_3_IN_INV_Msk (0x01UL << GIMA_CTIN_3_IN_INV_Pos) /*!< GIMA CTIN_3_IN: INV Mask */
+#define GIMA_CTIN_3_IN_EDGE_Pos 1 /*!< GIMA CTIN_3_IN: EDGE Position */
+#define GIMA_CTIN_3_IN_EDGE_Msk (0x01UL << GIMA_CTIN_3_IN_EDGE_Pos) /*!< GIMA CTIN_3_IN: EDGE Mask */
+#define GIMA_CTIN_3_IN_SYNCH_Pos 2 /*!< GIMA CTIN_3_IN: SYNCH Position */
+#define GIMA_CTIN_3_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_3_IN_SYNCH_Pos) /*!< GIMA CTIN_3_IN: SYNCH Mask */
+#define GIMA_CTIN_3_IN_PULSE_Pos 3 /*!< GIMA CTIN_3_IN: PULSE Position */
+#define GIMA_CTIN_3_IN_PULSE_Msk (0x01UL << GIMA_CTIN_3_IN_PULSE_Pos) /*!< GIMA CTIN_3_IN: PULSE Mask */
+#define GIMA_CTIN_3_IN_SELECT_Pos 4 /*!< GIMA CTIN_3_IN: SELECT Position */
+#define GIMA_CTIN_3_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_3_IN_SELECT_Pos) /*!< GIMA CTIN_3_IN: SELECT Mask */
+
+// ------------------------------------- GIMA_CTIN_4_IN -----------------------------------------
+#define GIMA_CTIN_4_IN_INV_Pos 0 /*!< GIMA CTIN_4_IN: INV Position */
+#define GIMA_CTIN_4_IN_INV_Msk (0x01UL << GIMA_CTIN_4_IN_INV_Pos) /*!< GIMA CTIN_4_IN: INV Mask */
+#define GIMA_CTIN_4_IN_EDGE_Pos 1 /*!< GIMA CTIN_4_IN: EDGE Position */
+#define GIMA_CTIN_4_IN_EDGE_Msk (0x01UL << GIMA_CTIN_4_IN_EDGE_Pos) /*!< GIMA CTIN_4_IN: EDGE Mask */
+#define GIMA_CTIN_4_IN_SYNCH_Pos 2 /*!< GIMA CTIN_4_IN: SYNCH Position */
+#define GIMA_CTIN_4_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_4_IN_SYNCH_Pos) /*!< GIMA CTIN_4_IN: SYNCH Mask */
+#define GIMA_CTIN_4_IN_PULSE_Pos 3 /*!< GIMA CTIN_4_IN: PULSE Position */
+#define GIMA_CTIN_4_IN_PULSE_Msk (0x01UL << GIMA_CTIN_4_IN_PULSE_Pos) /*!< GIMA CTIN_4_IN: PULSE Mask */
+#define GIMA_CTIN_4_IN_SELECT_Pos 4 /*!< GIMA CTIN_4_IN: SELECT Position */
+#define GIMA_CTIN_4_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_4_IN_SELECT_Pos) /*!< GIMA CTIN_4_IN: SELECT Mask */
+
+// ------------------------------------- GIMA_CTIN_5_IN -----------------------------------------
+#define GIMA_CTIN_5_IN_INV_Pos 0 /*!< GIMA CTIN_5_IN: INV Position */
+#define GIMA_CTIN_5_IN_INV_Msk (0x01UL << GIMA_CTIN_5_IN_INV_Pos) /*!< GIMA CTIN_5_IN: INV Mask */
+#define GIMA_CTIN_5_IN_EDGE_Pos 1 /*!< GIMA CTIN_5_IN: EDGE Position */
+#define GIMA_CTIN_5_IN_EDGE_Msk (0x01UL << GIMA_CTIN_5_IN_EDGE_Pos) /*!< GIMA CTIN_5_IN: EDGE Mask */
+#define GIMA_CTIN_5_IN_SYNCH_Pos 2 /*!< GIMA CTIN_5_IN: SYNCH Position */
+#define GIMA_CTIN_5_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_5_IN_SYNCH_Pos) /*!< GIMA CTIN_5_IN: SYNCH Mask */
+#define GIMA_CTIN_5_IN_PULSE_Pos 3 /*!< GIMA CTIN_5_IN: PULSE Position */
+#define GIMA_CTIN_5_IN_PULSE_Msk (0x01UL << GIMA_CTIN_5_IN_PULSE_Pos) /*!< GIMA CTIN_5_IN: PULSE Mask */
+#define GIMA_CTIN_5_IN_SELECT_Pos 4 /*!< GIMA CTIN_5_IN: SELECT Position */
+#define GIMA_CTIN_5_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_5_IN_SELECT_Pos) /*!< GIMA CTIN_5_IN: SELECT Mask */
+
+// ------------------------------------- GIMA_CTIN_6_IN -----------------------------------------
+#define GIMA_CTIN_6_IN_INV_Pos 0 /*!< GIMA CTIN_6_IN: INV Position */
+#define GIMA_CTIN_6_IN_INV_Msk (0x01UL << GIMA_CTIN_6_IN_INV_Pos) /*!< GIMA CTIN_6_IN: INV Mask */
+#define GIMA_CTIN_6_IN_EDGE_Pos 1 /*!< GIMA CTIN_6_IN: EDGE Position */
+#define GIMA_CTIN_6_IN_EDGE_Msk (0x01UL << GIMA_CTIN_6_IN_EDGE_Pos) /*!< GIMA CTIN_6_IN: EDGE Mask */
+#define GIMA_CTIN_6_IN_SYNCH_Pos 2 /*!< GIMA CTIN_6_IN: SYNCH Position */
+#define GIMA_CTIN_6_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_6_IN_SYNCH_Pos) /*!< GIMA CTIN_6_IN: SYNCH Mask */
+#define GIMA_CTIN_6_IN_PULSE_Pos 3 /*!< GIMA CTIN_6_IN: PULSE Position */
+#define GIMA_CTIN_6_IN_PULSE_Msk (0x01UL << GIMA_CTIN_6_IN_PULSE_Pos) /*!< GIMA CTIN_6_IN: PULSE Mask */
+#define GIMA_CTIN_6_IN_SELECT_Pos 4 /*!< GIMA CTIN_6_IN: SELECT Position */
+#define GIMA_CTIN_6_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_6_IN_SELECT_Pos) /*!< GIMA CTIN_6_IN: SELECT Mask */
+
+// ------------------------------------- GIMA_CTIN_7_IN -----------------------------------------
+#define GIMA_CTIN_7_IN_INV_Pos 0 /*!< GIMA CTIN_7_IN: INV Position */
+#define GIMA_CTIN_7_IN_INV_Msk (0x01UL << GIMA_CTIN_7_IN_INV_Pos) /*!< GIMA CTIN_7_IN: INV Mask */
+#define GIMA_CTIN_7_IN_EDGE_Pos 1 /*!< GIMA CTIN_7_IN: EDGE Position */
+#define GIMA_CTIN_7_IN_EDGE_Msk (0x01UL << GIMA_CTIN_7_IN_EDGE_Pos) /*!< GIMA CTIN_7_IN: EDGE Mask */
+#define GIMA_CTIN_7_IN_SYNCH_Pos 2 /*!< GIMA CTIN_7_IN: SYNCH Position */
+#define GIMA_CTIN_7_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_7_IN_SYNCH_Pos) /*!< GIMA CTIN_7_IN: SYNCH Mask */
+#define GIMA_CTIN_7_IN_PULSE_Pos 3 /*!< GIMA CTIN_7_IN: PULSE Position */
+#define GIMA_CTIN_7_IN_PULSE_Msk (0x01UL << GIMA_CTIN_7_IN_PULSE_Pos) /*!< GIMA CTIN_7_IN: PULSE Mask */
+#define GIMA_CTIN_7_IN_SELECT_Pos 4 /*!< GIMA CTIN_7_IN: SELECT Position */
+#define GIMA_CTIN_7_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_7_IN_SELECT_Pos) /*!< GIMA CTIN_7_IN: SELECT Mask */
+
+// ---------------------------------- GIMA_VADC_TRIGGER_IN --------------------------------------
+#define GIMA_VADC_TRIGGER_IN_INV_Pos 0 /*!< GIMA VADC_TRIGGER_IN: INV Position */
+#define GIMA_VADC_TRIGGER_IN_INV_Msk (0x01UL << GIMA_VADC_TRIGGER_IN_INV_Pos) /*!< GIMA VADC_TRIGGER_IN: INV Mask */
+#define GIMA_VADC_TRIGGER_IN_EDGE_Pos 1 /*!< GIMA VADC_TRIGGER_IN: EDGE Position */
+#define GIMA_VADC_TRIGGER_IN_EDGE_Msk (0x01UL << GIMA_VADC_TRIGGER_IN_EDGE_Pos) /*!< GIMA VADC_TRIGGER_IN: EDGE Mask */
+#define GIMA_VADC_TRIGGER_IN_SYNCH_Pos 2 /*!< GIMA VADC_TRIGGER_IN: SYNCH Position */
+#define GIMA_VADC_TRIGGER_IN_SYNCH_Msk (0x01UL << GIMA_VADC_TRIGGER_IN_SYNCH_Pos) /*!< GIMA VADC_TRIGGER_IN: SYNCH Mask */
+#define GIMA_VADC_TRIGGER_IN_PULSE_Pos 3 /*!< GIMA VADC_TRIGGER_IN: PULSE Position */
+#define GIMA_VADC_TRIGGER_IN_PULSE_Msk (0x01UL << GIMA_VADC_TRIGGER_IN_PULSE_Pos) /*!< GIMA VADC_TRIGGER_IN: PULSE Mask */
+#define GIMA_VADC_TRIGGER_IN_SELECT_Pos 4 /*!< GIMA VADC_TRIGGER_IN: SELECT Position */
+#define GIMA_VADC_TRIGGER_IN_SELECT_Msk (0x0fUL << GIMA_VADC_TRIGGER_IN_SELECT_Pos) /*!< GIMA VADC_TRIGGER_IN: SELECT Mask */
+
+// --------------------------------- GIMA_EVENTROUTER_13_IN -------------------------------------
+#define GIMA_EVENTROUTER_13_IN_INV_Pos 0 /*!< GIMA EVENTROUTER_13_IN: INV Position */
+#define GIMA_EVENTROUTER_13_IN_INV_Msk (0x01UL << GIMA_EVENTROUTER_13_IN_INV_Pos) /*!< GIMA EVENTROUTER_13_IN: INV Mask */
+#define GIMA_EVENTROUTER_13_IN_EDGE_Pos 1 /*!< GIMA EVENTROUTER_13_IN: EDGE Position */
+#define GIMA_EVENTROUTER_13_IN_EDGE_Msk (0x01UL << GIMA_EVENTROUTER_13_IN_EDGE_Pos) /*!< GIMA EVENTROUTER_13_IN: EDGE Mask */
+#define GIMA_EVENTROUTER_13_IN_SYNCH_Pos 2 /*!< GIMA EVENTROUTER_13_IN: SYNCH Position */
+#define GIMA_EVENTROUTER_13_IN_SYNCH_Msk (0x01UL << GIMA_EVENTROUTER_13_IN_SYNCH_Pos) /*!< GIMA EVENTROUTER_13_IN: SYNCH Mask */
+#define GIMA_EVENTROUTER_13_IN_PULSE_Pos 3 /*!< GIMA EVENTROUTER_13_IN: PULSE Position */
+#define GIMA_EVENTROUTER_13_IN_PULSE_Msk (0x01UL << GIMA_EVENTROUTER_13_IN_PULSE_Pos) /*!< GIMA EVENTROUTER_13_IN: PULSE Mask */
+#define GIMA_EVENTROUTER_13_IN_SELECT_Pos 4 /*!< GIMA EVENTROUTER_13_IN: SELECT Position */
+#define GIMA_EVENTROUTER_13_IN_SELECT_Msk (0x0fUL << GIMA_EVENTROUTER_13_IN_SELECT_Pos) /*!< GIMA EVENTROUTER_13_IN: SELECT Mask */
+
+// --------------------------------- GIMA_EVENTROUTER_14_IN -------------------------------------
+#define GIMA_EVENTROUTER_14_IN_INV_Pos 0 /*!< GIMA EVENTROUTER_14_IN: INV Position */
+#define GIMA_EVENTROUTER_14_IN_INV_Msk (0x01UL << GIMA_EVENTROUTER_14_IN_INV_Pos) /*!< GIMA EVENTROUTER_14_IN: INV Mask */
+#define GIMA_EVENTROUTER_14_IN_EDGE_Pos 1 /*!< GIMA EVENTROUTER_14_IN: EDGE Position */
+#define GIMA_EVENTROUTER_14_IN_EDGE_Msk (0x01UL << GIMA_EVENTROUTER_14_IN_EDGE_Pos) /*!< GIMA EVENTROUTER_14_IN: EDGE Mask */
+#define GIMA_EVENTROUTER_14_IN_SYNCH_Pos 2 /*!< GIMA EVENTROUTER_14_IN: SYNCH Position */
+#define GIMA_EVENTROUTER_14_IN_SYNCH_Msk (0x01UL << GIMA_EVENTROUTER_14_IN_SYNCH_Pos) /*!< GIMA EVENTROUTER_14_IN: SYNCH Mask */
+#define GIMA_EVENTROUTER_14_IN_PULSE_Pos 3 /*!< GIMA EVENTROUTER_14_IN: PULSE Position */
+#define GIMA_EVENTROUTER_14_IN_PULSE_Msk (0x01UL << GIMA_EVENTROUTER_14_IN_PULSE_Pos) /*!< GIMA EVENTROUTER_14_IN: PULSE Mask */
+#define GIMA_EVENTROUTER_14_IN_SELECT_Pos 4 /*!< GIMA EVENTROUTER_14_IN: SELECT Position */
+#define GIMA_EVENTROUTER_14_IN_SELECT_Msk (0x0fUL << GIMA_EVENTROUTER_14_IN_SELECT_Pos) /*!< GIMA EVENTROUTER_14_IN: SELECT Mask */
+
+// --------------------------------- GIMA_EVENTROUTER_16_IN -------------------------------------
+#define GIMA_EVENTROUTER_16_IN_INV_Pos 0 /*!< GIMA EVENTROUTER_16_IN: INV Position */
+#define GIMA_EVENTROUTER_16_IN_INV_Msk (0x01UL << GIMA_EVENTROUTER_16_IN_INV_Pos) /*!< GIMA EVENTROUTER_16_IN: INV Mask */
+#define GIMA_EVENTROUTER_16_IN_EDGE_Pos 1 /*!< GIMA EVENTROUTER_16_IN: EDGE Position */
+#define GIMA_EVENTROUTER_16_IN_EDGE_Msk (0x01UL << GIMA_EVENTROUTER_16_IN_EDGE_Pos) /*!< GIMA EVENTROUTER_16_IN: EDGE Mask */
+#define GIMA_EVENTROUTER_16_IN_SYNCH_Pos 2 /*!< GIMA EVENTROUTER_16_IN: SYNCH Position */
+#define GIMA_EVENTROUTER_16_IN_SYNCH_Msk (0x01UL << GIMA_EVENTROUTER_16_IN_SYNCH_Pos) /*!< GIMA EVENTROUTER_16_IN: SYNCH Mask */
+#define GIMA_EVENTROUTER_16_IN_PULSE_Pos 3 /*!< GIMA EVENTROUTER_16_IN: PULSE Position */
+#define GIMA_EVENTROUTER_16_IN_PULSE_Msk (0x01UL << GIMA_EVENTROUTER_16_IN_PULSE_Pos) /*!< GIMA EVENTROUTER_16_IN: PULSE Mask */
+#define GIMA_EVENTROUTER_16_IN_SELECT_Pos 4 /*!< GIMA EVENTROUTER_16_IN: SELECT Position */
+#define GIMA_EVENTROUTER_16_IN_SELECT_Msk (0x0fUL << GIMA_EVENTROUTER_16_IN_SELECT_Pos) /*!< GIMA EVENTROUTER_16_IN: SELECT Mask */
+
+// ------------------------------------ GIMA_ADCSTART0_IN ---------------------------------------
+#define GIMA_ADCSTART0_IN_INV_Pos 0 /*!< GIMA ADCSTART0_IN: INV Position */
+#define GIMA_ADCSTART0_IN_INV_Msk (0x01UL << GIMA_ADCSTART0_IN_INV_Pos) /*!< GIMA ADCSTART0_IN: INV Mask */
+#define GIMA_ADCSTART0_IN_EDGE_Pos 1 /*!< GIMA ADCSTART0_IN: EDGE Position */
+#define GIMA_ADCSTART0_IN_EDGE_Msk (0x01UL << GIMA_ADCSTART0_IN_EDGE_Pos) /*!< GIMA ADCSTART0_IN: EDGE Mask */
+#define GIMA_ADCSTART0_IN_SYNCH_Pos 2 /*!< GIMA ADCSTART0_IN: SYNCH Position */
+#define GIMA_ADCSTART0_IN_SYNCH_Msk (0x01UL << GIMA_ADCSTART0_IN_SYNCH_Pos) /*!< GIMA ADCSTART0_IN: SYNCH Mask */
+#define GIMA_ADCSTART0_IN_PULSE_Pos 3 /*!< GIMA ADCSTART0_IN: PULSE Position */
+#define GIMA_ADCSTART0_IN_PULSE_Msk (0x01UL << GIMA_ADCSTART0_IN_PULSE_Pos) /*!< GIMA ADCSTART0_IN: PULSE Mask */
+#define GIMA_ADCSTART0_IN_SELECT_Pos 4 /*!< GIMA ADCSTART0_IN: SELECT Position */
+#define GIMA_ADCSTART0_IN_SELECT_Msk (0x0fUL << GIMA_ADCSTART0_IN_SELECT_Pos) /*!< GIMA ADCSTART0_IN: SELECT Mask */
+
+// ------------------------------------ GIMA_ADCSTART1_IN ---------------------------------------
+#define GIMA_ADCSTART1_IN_INV_Pos 0 /*!< GIMA ADCSTART1_IN: INV Position */
+#define GIMA_ADCSTART1_IN_INV_Msk (0x01UL << GIMA_ADCSTART1_IN_INV_Pos) /*!< GIMA ADCSTART1_IN: INV Mask */
+#define GIMA_ADCSTART1_IN_EDGE_Pos 1 /*!< GIMA ADCSTART1_IN: EDGE Position */
+#define GIMA_ADCSTART1_IN_EDGE_Msk (0x01UL << GIMA_ADCSTART1_IN_EDGE_Pos) /*!< GIMA ADCSTART1_IN: EDGE Mask */
+#define GIMA_ADCSTART1_IN_SYNCH_Pos 2 /*!< GIMA ADCSTART1_IN: SYNCH Position */
+#define GIMA_ADCSTART1_IN_SYNCH_Msk (0x01UL << GIMA_ADCSTART1_IN_SYNCH_Pos) /*!< GIMA ADCSTART1_IN: SYNCH Mask */
+#define GIMA_ADCSTART1_IN_PULSE_Pos 3 /*!< GIMA ADCSTART1_IN: PULSE Position */
+#define GIMA_ADCSTART1_IN_PULSE_Msk (0x01UL << GIMA_ADCSTART1_IN_PULSE_Pos) /*!< GIMA ADCSTART1_IN: PULSE Mask */
+#define GIMA_ADCSTART1_IN_SELECT_Pos 4 /*!< GIMA ADCSTART1_IN: SELECT Position */
+#define GIMA_ADCSTART1_IN_SELECT_Msk (0x0fUL << GIMA_ADCSTART1_IN_SELECT_Pos) /*!< GIMA ADCSTART1_IN: SELECT Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- DAC Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------- DAC_CR ---------------------------------------------
+#define DAC_CR_VALUE_Pos 6 /*!< DAC CR: VALUE Position */
+#define DAC_CR_VALUE_Msk (0x000003ffUL << DAC_CR_VALUE_Pos) /*!< DAC CR: VALUE Mask */
+#define DAC_CR_BIAS_Pos 16 /*!< DAC CR: BIAS Position */
+#define DAC_CR_BIAS_Msk (0x01UL << DAC_CR_BIAS_Pos) /*!< DAC CR: BIAS Mask */
+
+// ---------------------------------------- DAC_CTRL --------------------------------------------
+#define DAC_CTRL_INT_DMA_REQ_Pos 0 /*!< DAC CTRL: INT_DMA_REQ Position */
+#define DAC_CTRL_INT_DMA_REQ_Msk (0x01UL << DAC_CTRL_INT_DMA_REQ_Pos) /*!< DAC CTRL: INT_DMA_REQ Mask */
+#define DAC_CTRL_DBLBUF_ENA_Pos 1 /*!< DAC CTRL: DBLBUF_ENA Position */
+#define DAC_CTRL_DBLBUF_ENA_Msk (0x01UL << DAC_CTRL_DBLBUF_ENA_Pos) /*!< DAC CTRL: DBLBUF_ENA Mask */
+#define DAC_CTRL_CNT_ENA_Pos 2 /*!< DAC CTRL: CNT_ENA Position */
+#define DAC_CTRL_CNT_ENA_Msk (0x01UL << DAC_CTRL_CNT_ENA_Pos) /*!< DAC CTRL: CNT_ENA Mask */
+#define DAC_CTRL_DMA_ENA_Pos 3 /*!< DAC CTRL: DMA_ENA Position */
+#define DAC_CTRL_DMA_ENA_Msk (0x01UL << DAC_CTRL_DMA_ENA_Pos) /*!< DAC CTRL: DMA_ENA Mask */
+
+// --------------------------------------- DAC_CNTVAL -------------------------------------------
+#define DAC_CNTVAL_VALUE_Pos 0 /*!< DAC CNTVAL: VALUE Position */
+#define DAC_CNTVAL_VALUE_Msk (0x0000ffffUL << DAC_CNTVAL_VALUE_Pos) /*!< DAC CNTVAL: VALUE Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- C_CAN0 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// --------------------------------------- C_CAN0_CNTL ------------------------------------------
+#define C_CAN0_CNTL_INIT_Pos 0 /*!< C_CAN0 CNTL: INIT Position */
+#define C_CAN0_CNTL_INIT_Msk (0x01UL << C_CAN0_CNTL_INIT_Pos) /*!< C_CAN0 CNTL: INIT Mask */
+#define C_CAN0_CNTL_IE_Pos 1 /*!< C_CAN0 CNTL: IE Position */
+#define C_CAN0_CNTL_IE_Msk (0x01UL << C_CAN0_CNTL_IE_Pos) /*!< C_CAN0 CNTL: IE Mask */
+#define C_CAN0_CNTL_SIE_Pos 2 /*!< C_CAN0 CNTL: SIE Position */
+#define C_CAN0_CNTL_SIE_Msk (0x01UL << C_CAN0_CNTL_SIE_Pos) /*!< C_CAN0 CNTL: SIE Mask */
+#define C_CAN0_CNTL_EIE_Pos 3 /*!< C_CAN0 CNTL: EIE Position */
+#define C_CAN0_CNTL_EIE_Msk (0x01UL << C_CAN0_CNTL_EIE_Pos) /*!< C_CAN0 CNTL: EIE Mask */
+#define C_CAN0_CNTL_DAR_Pos 5 /*!< C_CAN0 CNTL: DAR Position */
+#define C_CAN0_CNTL_DAR_Msk (0x01UL << C_CAN0_CNTL_DAR_Pos) /*!< C_CAN0 CNTL: DAR Mask */
+#define C_CAN0_CNTL_CCE_Pos 6 /*!< C_CAN0 CNTL: CCE Position */
+#define C_CAN0_CNTL_CCE_Msk (0x01UL << C_CAN0_CNTL_CCE_Pos) /*!< C_CAN0 CNTL: CCE Mask */
+#define C_CAN0_CNTL_TEST_Pos 7 /*!< C_CAN0 CNTL: TEST Position */
+#define C_CAN0_CNTL_TEST_Msk (0x01UL << C_CAN0_CNTL_TEST_Pos) /*!< C_CAN0 CNTL: TEST Mask */
+
+// --------------------------------------- C_CAN0_STAT ------------------------------------------
+#define C_CAN0_STAT_LEC_Pos 0 /*!< C_CAN0 STAT: LEC Position */
+#define C_CAN0_STAT_LEC_Msk (0x07UL << C_CAN0_STAT_LEC_Pos) /*!< C_CAN0 STAT: LEC Mask */
+#define C_CAN0_STAT_TXOK_Pos 3 /*!< C_CAN0 STAT: TXOK Position */
+#define C_CAN0_STAT_TXOK_Msk (0x01UL << C_CAN0_STAT_TXOK_Pos) /*!< C_CAN0 STAT: TXOK Mask */
+#define C_CAN0_STAT_RXOK_Pos 4 /*!< C_CAN0 STAT: RXOK Position */
+#define C_CAN0_STAT_RXOK_Msk (0x01UL << C_CAN0_STAT_RXOK_Pos) /*!< C_CAN0 STAT: RXOK Mask */
+#define C_CAN0_STAT_EPASS_Pos 5 /*!< C_CAN0 STAT: EPASS Position */
+#define C_CAN0_STAT_EPASS_Msk (0x01UL << C_CAN0_STAT_EPASS_Pos) /*!< C_CAN0 STAT: EPASS Mask */
+#define C_CAN0_STAT_EWARN_Pos 6 /*!< C_CAN0 STAT: EWARN Position */
+#define C_CAN0_STAT_EWARN_Msk (0x01UL << C_CAN0_STAT_EWARN_Pos) /*!< C_CAN0 STAT: EWARN Mask */
+#define C_CAN0_STAT_BOFF_Pos 7 /*!< C_CAN0 STAT: BOFF Position */
+#define C_CAN0_STAT_BOFF_Msk (0x01UL << C_CAN0_STAT_BOFF_Pos) /*!< C_CAN0 STAT: BOFF Mask */
+
+// ---------------------------------------- C_CAN0_EC -------------------------------------------
+#define C_CAN0_EC_TEC_7_0_Pos 0 /*!< C_CAN0 EC: TEC_7_0 Position */
+#define C_CAN0_EC_TEC_7_0_Msk (0x000000ffUL << C_CAN0_EC_TEC_7_0_Pos) /*!< C_CAN0 EC: TEC_7_0 Mask */
+#define C_CAN0_EC_REC_6_0_Pos 8 /*!< C_CAN0 EC: REC_6_0 Position */
+#define C_CAN0_EC_REC_6_0_Msk (0x7fUL << C_CAN0_EC_REC_6_0_Pos) /*!< C_CAN0 EC: REC_6_0 Mask */
+#define C_CAN0_EC_RP_Pos 15 /*!< C_CAN0 EC: RP Position */
+#define C_CAN0_EC_RP_Msk (0x01UL << C_CAN0_EC_RP_Pos) /*!< C_CAN0 EC: RP Mask */
+
+// ---------------------------------------- C_CAN0_BT -------------------------------------------
+#define C_CAN0_BT_BRP_Pos 0 /*!< C_CAN0 BT: BRP Position */
+#define C_CAN0_BT_BRP_Msk (0x3fUL << C_CAN0_BT_BRP_Pos) /*!< C_CAN0 BT: BRP Mask */
+#define C_CAN0_BT_SJW_Pos 6 /*!< C_CAN0 BT: SJW Position */
+#define C_CAN0_BT_SJW_Msk (0x03UL << C_CAN0_BT_SJW_Pos) /*!< C_CAN0 BT: SJW Mask */
+#define C_CAN0_BT_TSEG1_Pos 8 /*!< C_CAN0 BT: TSEG1 Position */
+#define C_CAN0_BT_TSEG1_Msk (0x0fUL << C_CAN0_BT_TSEG1_Pos) /*!< C_CAN0 BT: TSEG1 Mask */
+#define C_CAN0_BT_TSEG2_Pos 12 /*!< C_CAN0 BT: TSEG2 Position */
+#define C_CAN0_BT_TSEG2_Msk (0x07UL << C_CAN0_BT_TSEG2_Pos) /*!< C_CAN0 BT: TSEG2 Mask */
+
+// --------------------------------------- C_CAN0_INT -------------------------------------------
+#define C_CAN0_INT_INTID15_0_Pos 0 /*!< C_CAN0 INT: INTID15_0 Position */
+#define C_CAN0_INT_INTID15_0_Msk (0x0000ffffUL << C_CAN0_INT_INTID15_0_Pos) /*!< C_CAN0 INT: INTID15_0 Mask */
+
+// --------------------------------------- C_CAN0_TEST ------------------------------------------
+#define C_CAN0_TEST_BASIC_Pos 2 /*!< C_CAN0 TEST: BASIC Position */
+#define C_CAN0_TEST_BASIC_Msk (0x01UL << C_CAN0_TEST_BASIC_Pos) /*!< C_CAN0 TEST: BASIC Mask */
+#define C_CAN0_TEST_SILENT_Pos 3 /*!< C_CAN0 TEST: SILENT Position */
+#define C_CAN0_TEST_SILENT_Msk (0x01UL << C_CAN0_TEST_SILENT_Pos) /*!< C_CAN0 TEST: SILENT Mask */
+#define C_CAN0_TEST_LBACK_Pos 4 /*!< C_CAN0 TEST: LBACK Position */
+#define C_CAN0_TEST_LBACK_Msk (0x01UL << C_CAN0_TEST_LBACK_Pos) /*!< C_CAN0 TEST: LBACK Mask */
+#define C_CAN0_TEST_TX1_0_Pos 5 /*!< C_CAN0 TEST: TX1_0 Position */
+#define C_CAN0_TEST_TX1_0_Msk (0x03UL << C_CAN0_TEST_TX1_0_Pos) /*!< C_CAN0 TEST: TX1_0 Mask */
+#define C_CAN0_TEST_RX_Pos 7 /*!< C_CAN0 TEST: RX Position */
+#define C_CAN0_TEST_RX_Msk (0x01UL << C_CAN0_TEST_RX_Pos) /*!< C_CAN0 TEST: RX Mask */
+
+// --------------------------------------- C_CAN0_BRPE ------------------------------------------
+#define C_CAN0_BRPE_BRPE_Pos 0 /*!< C_CAN0 BRPE: BRPE Position */
+#define C_CAN0_BRPE_BRPE_Msk (0x0fUL << C_CAN0_BRPE_BRPE_Pos) /*!< C_CAN0 BRPE: BRPE Mask */
+
+// ------------------------------------ C_CAN0_IF1_CMDREQ ---------------------------------------
+#define C_CAN0_IF1_CMDREQ_MESSNUM_Pos 0 /*!< C_CAN0 IF1_CMDREQ: MESSNUM Position */
+#define C_CAN0_IF1_CMDREQ_MESSNUM_Msk (0x3fUL << C_CAN0_IF1_CMDREQ_MESSNUM_Pos) /*!< C_CAN0 IF1_CMDREQ: MESSNUM Mask */
+#define C_CAN0_IF1_CMDREQ_BUSY_Pos 15 /*!< C_CAN0 IF1_CMDREQ: BUSY Position */
+#define C_CAN0_IF1_CMDREQ_BUSY_Msk (0x01UL << C_CAN0_IF1_CMDREQ_BUSY_Pos) /*!< C_CAN0 IF1_CMDREQ: BUSY Mask */
+
+// ----------------------------------- C_CAN0_IF1_CMDMSK_R --------------------------------------
+#define C_CAN0_IF1_CMDMSK_R_DATA_B_Pos 0 /*!< C_CAN0 IF1_CMDMSK_R: DATA_B Position */
+#define C_CAN0_IF1_CMDMSK_R_DATA_B_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_DATA_B_Pos) /*!< C_CAN0 IF1_CMDMSK_R: DATA_B Mask */
+#define C_CAN0_IF1_CMDMSK_R_DATA_A_Pos 1 /*!< C_CAN0 IF1_CMDMSK_R: DATA_A Position */
+#define C_CAN0_IF1_CMDMSK_R_DATA_A_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_DATA_A_Pos) /*!< C_CAN0 IF1_CMDMSK_R: DATA_A Mask */
+#define C_CAN0_IF1_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CAN0 IF1_CMDMSK_R: NEWDAT Position */
+#define C_CAN0_IF1_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_NEWDAT_Pos) /*!< C_CAN0 IF1_CMDMSK_R: NEWDAT Mask */
+#define C_CAN0_IF1_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CAN0 IF1_CMDMSK_R: CLRINTPND Position */
+#define C_CAN0_IF1_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_CLRINTPND_Pos) /*!< C_CAN0 IF1_CMDMSK_R: CLRINTPND Mask */
+#define C_CAN0_IF1_CMDMSK_R_CTRL_Pos 4 /*!< C_CAN0 IF1_CMDMSK_R: CTRL Position */
+#define C_CAN0_IF1_CMDMSK_R_CTRL_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_CTRL_Pos) /*!< C_CAN0 IF1_CMDMSK_R: CTRL Mask */
+#define C_CAN0_IF1_CMDMSK_R_ARB_Pos 5 /*!< C_CAN0 IF1_CMDMSK_R: ARB Position */
+#define C_CAN0_IF1_CMDMSK_R_ARB_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_ARB_Pos) /*!< C_CAN0 IF1_CMDMSK_R: ARB Mask */
+#define C_CAN0_IF1_CMDMSK_R_MASK_Pos 6 /*!< C_CAN0 IF1_CMDMSK_R: MASK Position */
+#define C_CAN0_IF1_CMDMSK_R_MASK_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_MASK_Pos) /*!< C_CAN0 IF1_CMDMSK_R: MASK Mask */
+#define C_CAN0_IF1_CMDMSK_R_WR_RD_Pos 7 /*!< C_CAN0 IF1_CMDMSK_R: WR_RD Position */
+#define C_CAN0_IF1_CMDMSK_R_WR_RD_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_WR_RD_Pos) /*!< C_CAN0 IF1_CMDMSK_R: WR_RD Mask */
+
+// ----------------------------------- C_CAN0_IF1_CMDMSK_W --------------------------------------
+#define C_CAN0_IF1_CMDMSK_W_DATA_B_Pos 0 /*!< C_CAN0 IF1_CMDMSK_W: DATA_B Position */
+#define C_CAN0_IF1_CMDMSK_W_DATA_B_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_DATA_B_Pos) /*!< C_CAN0 IF1_CMDMSK_W: DATA_B Mask */
+#define C_CAN0_IF1_CMDMSK_W_DATA_A_Pos 1 /*!< C_CAN0 IF1_CMDMSK_W: DATA_A Position */
+#define C_CAN0_IF1_CMDMSK_W_DATA_A_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_DATA_A_Pos) /*!< C_CAN0 IF1_CMDMSK_W: DATA_A Mask */
+#define C_CAN0_IF1_CMDMSK_W_TXRQST_Pos 2 /*!< C_CAN0 IF1_CMDMSK_W: TXRQST Position */
+#define C_CAN0_IF1_CMDMSK_W_TXRQST_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_TXRQST_Pos) /*!< C_CAN0 IF1_CMDMSK_W: TXRQST Mask */
+#define C_CAN0_IF1_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CAN0 IF1_CMDMSK_W: CLRINTPND Position */
+#define C_CAN0_IF1_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_CLRINTPND_Pos) /*!< C_CAN0 IF1_CMDMSK_W: CLRINTPND Mask */
+#define C_CAN0_IF1_CMDMSK_W_CTRL_Pos 4 /*!< C_CAN0 IF1_CMDMSK_W: CTRL Position */
+#define C_CAN0_IF1_CMDMSK_W_CTRL_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_CTRL_Pos) /*!< C_CAN0 IF1_CMDMSK_W: CTRL Mask */
+#define C_CAN0_IF1_CMDMSK_W_ARB_Pos 5 /*!< C_CAN0 IF1_CMDMSK_W: ARB Position */
+#define C_CAN0_IF1_CMDMSK_W_ARB_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_ARB_Pos) /*!< C_CAN0 IF1_CMDMSK_W: ARB Mask */
+#define C_CAN0_IF1_CMDMSK_W_MASK_Pos 6 /*!< C_CAN0 IF1_CMDMSK_W: MASK Position */
+#define C_CAN0_IF1_CMDMSK_W_MASK_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_MASK_Pos) /*!< C_CAN0 IF1_CMDMSK_W: MASK Mask */
+#define C_CAN0_IF1_CMDMSK_W_WR_RD_Pos 7 /*!< C_CAN0 IF1_CMDMSK_W: WR_RD Position */
+#define C_CAN0_IF1_CMDMSK_W_WR_RD_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_WR_RD_Pos) /*!< C_CAN0 IF1_CMDMSK_W: WR_RD Mask */
+
+// ------------------------------------- C_CAN0_IF1_MSK1 ----------------------------------------
+#define C_CAN0_IF1_MSK1_MSK15_0_Pos 0 /*!< C_CAN0 IF1_MSK1: MSK15_0 Position */
+#define C_CAN0_IF1_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CAN0_IF1_MSK1_MSK15_0_Pos) /*!< C_CAN0 IF1_MSK1: MSK15_0 Mask */
+
+// ------------------------------------- C_CAN0_IF1_MSK2 ----------------------------------------
+#define C_CAN0_IF1_MSK2_MSK28_16_Pos 0 /*!< C_CAN0 IF1_MSK2: MSK28_16 Position */
+#define C_CAN0_IF1_MSK2_MSK28_16_Msk (0x00001fffUL << C_CAN0_IF1_MSK2_MSK28_16_Pos) /*!< C_CAN0 IF1_MSK2: MSK28_16 Mask */
+#define C_CAN0_IF1_MSK2_MDIR_Pos 14 /*!< C_CAN0 IF1_MSK2: MDIR Position */
+#define C_CAN0_IF1_MSK2_MDIR_Msk (0x01UL << C_CAN0_IF1_MSK2_MDIR_Pos) /*!< C_CAN0 IF1_MSK2: MDIR Mask */
+#define C_CAN0_IF1_MSK2_MXTD_Pos 15 /*!< C_CAN0 IF1_MSK2: MXTD Position */
+#define C_CAN0_IF1_MSK2_MXTD_Msk (0x01UL << C_CAN0_IF1_MSK2_MXTD_Pos) /*!< C_CAN0 IF1_MSK2: MXTD Mask */
+
+// ------------------------------------- C_CAN0_IF1_ARB1 ----------------------------------------
+#define C_CAN0_IF1_ARB1_ID15_0_Pos 0 /*!< C_CAN0 IF1_ARB1: ID15_0 Position */
+#define C_CAN0_IF1_ARB1_ID15_0_Msk (0x0000ffffUL << C_CAN0_IF1_ARB1_ID15_0_Pos) /*!< C_CAN0 IF1_ARB1: ID15_0 Mask */
+
+// ------------------------------------- C_CAN0_IF1_ARB2 ----------------------------------------
+#define C_CAN0_IF1_ARB2_ID28_16_Pos 0 /*!< C_CAN0 IF1_ARB2: ID28_16 Position */
+#define C_CAN0_IF1_ARB2_ID28_16_Msk (0x00001fffUL << C_CAN0_IF1_ARB2_ID28_16_Pos) /*!< C_CAN0 IF1_ARB2: ID28_16 Mask */
+#define C_CAN0_IF1_ARB2_DIR_Pos 13 /*!< C_CAN0 IF1_ARB2: DIR Position */
+#define C_CAN0_IF1_ARB2_DIR_Msk (0x01UL << C_CAN0_IF1_ARB2_DIR_Pos) /*!< C_CAN0 IF1_ARB2: DIR Mask */
+#define C_CAN0_IF1_ARB2_XTD_Pos 14 /*!< C_CAN0 IF1_ARB2: XTD Position */
+#define C_CAN0_IF1_ARB2_XTD_Msk (0x01UL << C_CAN0_IF1_ARB2_XTD_Pos) /*!< C_CAN0 IF1_ARB2: XTD Mask */
+#define C_CAN0_IF1_ARB2_MSGVAL_Pos 15 /*!< C_CAN0 IF1_ARB2: MSGVAL Position */
+#define C_CAN0_IF1_ARB2_MSGVAL_Msk (0x01UL << C_CAN0_IF1_ARB2_MSGVAL_Pos) /*!< C_CAN0 IF1_ARB2: MSGVAL Mask */
+
+// ------------------------------------ C_CAN0_IF1_MCTRL ----------------------------------------
+#define C_CAN0_IF1_MCTRL_DLC3_0_Pos 0 /*!< C_CAN0 IF1_MCTRL: DLC3_0 Position */
+#define C_CAN0_IF1_MCTRL_DLC3_0_Msk (0x0fUL << C_CAN0_IF1_MCTRL_DLC3_0_Pos) /*!< C_CAN0 IF1_MCTRL: DLC3_0 Mask */
+#define C_CAN0_IF1_MCTRL_EOB_Pos 7 /*!< C_CAN0 IF1_MCTRL: EOB Position */
+#define C_CAN0_IF1_MCTRL_EOB_Msk (0x01UL << C_CAN0_IF1_MCTRL_EOB_Pos) /*!< C_CAN0 IF1_MCTRL: EOB Mask */
+#define C_CAN0_IF1_MCTRL_TXRQST_Pos 8 /*!< C_CAN0 IF1_MCTRL: TXRQST Position */
+#define C_CAN0_IF1_MCTRL_TXRQST_Msk (0x01UL << C_CAN0_IF1_MCTRL_TXRQST_Pos) /*!< C_CAN0 IF1_MCTRL: TXRQST Mask */
+#define C_CAN0_IF1_MCTRL_RMTEN_Pos 9 /*!< C_CAN0 IF1_MCTRL: RMTEN Position */
+#define C_CAN0_IF1_MCTRL_RMTEN_Msk (0x01UL << C_CAN0_IF1_MCTRL_RMTEN_Pos) /*!< C_CAN0 IF1_MCTRL: RMTEN Mask */
+#define C_CAN0_IF1_MCTRL_RXIE_Pos 10 /*!< C_CAN0 IF1_MCTRL: RXIE Position */
+#define C_CAN0_IF1_MCTRL_RXIE_Msk (0x01UL << C_CAN0_IF1_MCTRL_RXIE_Pos) /*!< C_CAN0 IF1_MCTRL: RXIE Mask */
+#define C_CAN0_IF1_MCTRL_TXIE_Pos 11 /*!< C_CAN0 IF1_MCTRL: TXIE Position */
+#define C_CAN0_IF1_MCTRL_TXIE_Msk (0x01UL << C_CAN0_IF1_MCTRL_TXIE_Pos) /*!< C_CAN0 IF1_MCTRL: TXIE Mask */
+#define C_CAN0_IF1_MCTRL_UMASK_Pos 12 /*!< C_CAN0 IF1_MCTRL: UMASK Position */
+#define C_CAN0_IF1_MCTRL_UMASK_Msk (0x01UL << C_CAN0_IF1_MCTRL_UMASK_Pos) /*!< C_CAN0 IF1_MCTRL: UMASK Mask */
+#define C_CAN0_IF1_MCTRL_INTPND_Pos 13 /*!< C_CAN0 IF1_MCTRL: INTPND Position */
+#define C_CAN0_IF1_MCTRL_INTPND_Msk (0x01UL << C_CAN0_IF1_MCTRL_INTPND_Pos) /*!< C_CAN0 IF1_MCTRL: INTPND Mask */
+#define C_CAN0_IF1_MCTRL_MSGLST_Pos 14 /*!< C_CAN0 IF1_MCTRL: MSGLST Position */
+#define C_CAN0_IF1_MCTRL_MSGLST_Msk (0x01UL << C_CAN0_IF1_MCTRL_MSGLST_Pos) /*!< C_CAN0 IF1_MCTRL: MSGLST Mask */
+#define C_CAN0_IF1_MCTRL_NEWDAT_Pos 15 /*!< C_CAN0 IF1_MCTRL: NEWDAT Position */
+#define C_CAN0_IF1_MCTRL_NEWDAT_Msk (0x01UL << C_CAN0_IF1_MCTRL_NEWDAT_Pos) /*!< C_CAN0 IF1_MCTRL: NEWDAT Mask */
+
+// ------------------------------------- C_CAN0_IF1_DA1 -----------------------------------------
+#define C_CAN0_IF1_DA1_DATA0_Pos 0 /*!< C_CAN0 IF1_DA1: DATA0 Position */
+#define C_CAN0_IF1_DA1_DATA0_Msk (0x000000ffUL << C_CAN0_IF1_DA1_DATA0_Pos) /*!< C_CAN0 IF1_DA1: DATA0 Mask */
+#define C_CAN0_IF1_DA1_DATA1_Pos 8 /*!< C_CAN0 IF1_DA1: DATA1 Position */
+#define C_CAN0_IF1_DA1_DATA1_Msk (0x000000ffUL << C_CAN0_IF1_DA1_DATA1_Pos) /*!< C_CAN0 IF1_DA1: DATA1 Mask */
+
+// ------------------------------------- C_CAN0_IF1_DA2 -----------------------------------------
+#define C_CAN0_IF1_DA2_DATA2_Pos 0 /*!< C_CAN0 IF1_DA2: DATA2 Position */
+#define C_CAN0_IF1_DA2_DATA2_Msk (0x000000ffUL << C_CAN0_IF1_DA2_DATA2_Pos) /*!< C_CAN0 IF1_DA2: DATA2 Mask */
+#define C_CAN0_IF1_DA2_DATA3_Pos 8 /*!< C_CAN0 IF1_DA2: DATA3 Position */
+#define C_CAN0_IF1_DA2_DATA3_Msk (0x000000ffUL << C_CAN0_IF1_DA2_DATA3_Pos) /*!< C_CAN0 IF1_DA2: DATA3 Mask */
+
+// ------------------------------------- C_CAN0_IF1_DB1 -----------------------------------------
+#define C_CAN0_IF1_DB1_DATA4_Pos 0 /*!< C_CAN0 IF1_DB1: DATA4 Position */
+#define C_CAN0_IF1_DB1_DATA4_Msk (0x000000ffUL << C_CAN0_IF1_DB1_DATA4_Pos) /*!< C_CAN0 IF1_DB1: DATA4 Mask */
+#define C_CAN0_IF1_DB1_DATA5_Pos 8 /*!< C_CAN0 IF1_DB1: DATA5 Position */
+#define C_CAN0_IF1_DB1_DATA5_Msk (0x000000ffUL << C_CAN0_IF1_DB1_DATA5_Pos) /*!< C_CAN0 IF1_DB1: DATA5 Mask */
+
+// ------------------------------------- C_CAN0_IF1_DB2 -----------------------------------------
+#define C_CAN0_IF1_DB2_DATA6_Pos 0 /*!< C_CAN0 IF1_DB2: DATA6 Position */
+#define C_CAN0_IF1_DB2_DATA6_Msk (0x000000ffUL << C_CAN0_IF1_DB2_DATA6_Pos) /*!< C_CAN0 IF1_DB2: DATA6 Mask */
+#define C_CAN0_IF1_DB2_DATA7_Pos 8 /*!< C_CAN0 IF1_DB2: DATA7 Position */
+#define C_CAN0_IF1_DB2_DATA7_Msk (0x000000ffUL << C_CAN0_IF1_DB2_DATA7_Pos) /*!< C_CAN0 IF1_DB2: DATA7 Mask */
+
+// ------------------------------------ C_CAN0_IF2_CMDREQ ---------------------------------------
+#define C_CAN0_IF2_CMDREQ_MESSNUM_Pos 0 /*!< C_CAN0 IF2_CMDREQ: MESSNUM Position */
+#define C_CAN0_IF2_CMDREQ_MESSNUM_Msk (0x3fUL << C_CAN0_IF2_CMDREQ_MESSNUM_Pos) /*!< C_CAN0 IF2_CMDREQ: MESSNUM Mask */
+#define C_CAN0_IF2_CMDREQ_BUSY_Pos 15 /*!< C_CAN0 IF2_CMDREQ: BUSY Position */
+#define C_CAN0_IF2_CMDREQ_BUSY_Msk (0x01UL << C_CAN0_IF2_CMDREQ_BUSY_Pos) /*!< C_CAN0 IF2_CMDREQ: BUSY Mask */
+
+// ----------------------------------- C_CAN0_IF2_CMDMSK_R --------------------------------------
+#define C_CAN0_IF2_CMDMSK_R_DATA_B_Pos 0 /*!< C_CAN0 IF2_CMDMSK_R: DATA_B Position */
+#define C_CAN0_IF2_CMDMSK_R_DATA_B_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_DATA_B_Pos) /*!< C_CAN0 IF2_CMDMSK_R: DATA_B Mask */
+#define C_CAN0_IF2_CMDMSK_R_DATA_A_Pos 1 /*!< C_CAN0 IF2_CMDMSK_R: DATA_A Position */
+#define C_CAN0_IF2_CMDMSK_R_DATA_A_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_DATA_A_Pos) /*!< C_CAN0 IF2_CMDMSK_R: DATA_A Mask */
+#define C_CAN0_IF2_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CAN0 IF2_CMDMSK_R: NEWDAT Position */
+#define C_CAN0_IF2_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_NEWDAT_Pos) /*!< C_CAN0 IF2_CMDMSK_R: NEWDAT Mask */
+#define C_CAN0_IF2_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CAN0 IF2_CMDMSK_R: CLRINTPND Position */
+#define C_CAN0_IF2_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_CLRINTPND_Pos) /*!< C_CAN0 IF2_CMDMSK_R: CLRINTPND Mask */
+#define C_CAN0_IF2_CMDMSK_R_CTRL_Pos 4 /*!< C_CAN0 IF2_CMDMSK_R: CTRL Position */
+#define C_CAN0_IF2_CMDMSK_R_CTRL_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_CTRL_Pos) /*!< C_CAN0 IF2_CMDMSK_R: CTRL Mask */
+#define C_CAN0_IF2_CMDMSK_R_ARB_Pos 5 /*!< C_CAN0 IF2_CMDMSK_R: ARB Position */
+#define C_CAN0_IF2_CMDMSK_R_ARB_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_ARB_Pos) /*!< C_CAN0 IF2_CMDMSK_R: ARB Mask */
+#define C_CAN0_IF2_CMDMSK_R_MASK_Pos 6 /*!< C_CAN0 IF2_CMDMSK_R: MASK Position */
+#define C_CAN0_IF2_CMDMSK_R_MASK_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_MASK_Pos) /*!< C_CAN0 IF2_CMDMSK_R: MASK Mask */
+#define C_CAN0_IF2_CMDMSK_R_WR_RD_Pos 7 /*!< C_CAN0 IF2_CMDMSK_R: WR_RD Position */
+#define C_CAN0_IF2_CMDMSK_R_WR_RD_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_WR_RD_Pos) /*!< C_CAN0 IF2_CMDMSK_R: WR_RD Mask */
+
+// ----------------------------------- C_CAN0_IF2_CMDMSK_W --------------------------------------
+#define C_CAN0_IF2_CMDMSK_W_DATA_B_Pos 0 /*!< C_CAN0 IF2_CMDMSK_W: DATA_B Position */
+#define C_CAN0_IF2_CMDMSK_W_DATA_B_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_DATA_B_Pos) /*!< C_CAN0 IF2_CMDMSK_W: DATA_B Mask */
+#define C_CAN0_IF2_CMDMSK_W_DATA_A_Pos 1 /*!< C_CAN0 IF2_CMDMSK_W: DATA_A Position */
+#define C_CAN0_IF2_CMDMSK_W_DATA_A_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_DATA_A_Pos) /*!< C_CAN0 IF2_CMDMSK_W: DATA_A Mask */
+#define C_CAN0_IF2_CMDMSK_W_TXRQST_Pos 2 /*!< C_CAN0 IF2_CMDMSK_W: TXRQST Position */
+#define C_CAN0_IF2_CMDMSK_W_TXRQST_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_TXRQST_Pos) /*!< C_CAN0 IF2_CMDMSK_W: TXRQST Mask */
+#define C_CAN0_IF2_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CAN0 IF2_CMDMSK_W: CLRINTPND Position */
+#define C_CAN0_IF2_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_CLRINTPND_Pos) /*!< C_CAN0 IF2_CMDMSK_W: CLRINTPND Mask */
+#define C_CAN0_IF2_CMDMSK_W_CTRL_Pos 4 /*!< C_CAN0 IF2_CMDMSK_W: CTRL Position */
+#define C_CAN0_IF2_CMDMSK_W_CTRL_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_CTRL_Pos) /*!< C_CAN0 IF2_CMDMSK_W: CTRL Mask */
+#define C_CAN0_IF2_CMDMSK_W_ARB_Pos 5 /*!< C_CAN0 IF2_CMDMSK_W: ARB Position */
+#define C_CAN0_IF2_CMDMSK_W_ARB_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_ARB_Pos) /*!< C_CAN0 IF2_CMDMSK_W: ARB Mask */
+#define C_CAN0_IF2_CMDMSK_W_MASK_Pos 6 /*!< C_CAN0 IF2_CMDMSK_W: MASK Position */
+#define C_CAN0_IF2_CMDMSK_W_MASK_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_MASK_Pos) /*!< C_CAN0 IF2_CMDMSK_W: MASK Mask */
+#define C_CAN0_IF2_CMDMSK_W_WR_RD_Pos 7 /*!< C_CAN0 IF2_CMDMSK_W: WR_RD Position */
+#define C_CAN0_IF2_CMDMSK_W_WR_RD_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_WR_RD_Pos) /*!< C_CAN0 IF2_CMDMSK_W: WR_RD Mask */
+
+// ------------------------------------- C_CAN0_IF2_MSK1 ----------------------------------------
+#define C_CAN0_IF2_MSK1_MSK15_0_Pos 0 /*!< C_CAN0 IF2_MSK1: MSK15_0 Position */
+#define C_CAN0_IF2_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CAN0_IF2_MSK1_MSK15_0_Pos) /*!< C_CAN0 IF2_MSK1: MSK15_0 Mask */
+
+// ------------------------------------- C_CAN0_IF2_MSK2 ----------------------------------------
+#define C_CAN0_IF2_MSK2_MSK28_16_Pos 0 /*!< C_CAN0 IF2_MSK2: MSK28_16 Position */
+#define C_CAN0_IF2_MSK2_MSK28_16_Msk (0x00001fffUL << C_CAN0_IF2_MSK2_MSK28_16_Pos) /*!< C_CAN0 IF2_MSK2: MSK28_16 Mask */
+#define C_CAN0_IF2_MSK2_MDIR_Pos 14 /*!< C_CAN0 IF2_MSK2: MDIR Position */
+#define C_CAN0_IF2_MSK2_MDIR_Msk (0x01UL << C_CAN0_IF2_MSK2_MDIR_Pos) /*!< C_CAN0 IF2_MSK2: MDIR Mask */
+#define C_CAN0_IF2_MSK2_MXTD_Pos 15 /*!< C_CAN0 IF2_MSK2: MXTD Position */
+#define C_CAN0_IF2_MSK2_MXTD_Msk (0x01UL << C_CAN0_IF2_MSK2_MXTD_Pos) /*!< C_CAN0 IF2_MSK2: MXTD Mask */
+
+// ------------------------------------- C_CAN0_IF2_ARB1 ----------------------------------------
+#define C_CAN0_IF2_ARB1_ID15_0_Pos 0 /*!< C_CAN0 IF2_ARB1: ID15_0 Position */
+#define C_CAN0_IF2_ARB1_ID15_0_Msk (0x0000ffffUL << C_CAN0_IF2_ARB1_ID15_0_Pos) /*!< C_CAN0 IF2_ARB1: ID15_0 Mask */
+
+// ------------------------------------- C_CAN0_IF2_ARB2 ----------------------------------------
+#define C_CAN0_IF2_ARB2_ID28_16_Pos 0 /*!< C_CAN0 IF2_ARB2: ID28_16 Position */
+#define C_CAN0_IF2_ARB2_ID28_16_Msk (0x00001fffUL << C_CAN0_IF2_ARB2_ID28_16_Pos) /*!< C_CAN0 IF2_ARB2: ID28_16 Mask */
+#define C_CAN0_IF2_ARB2_DIR_Pos 13 /*!< C_CAN0 IF2_ARB2: DIR Position */
+#define C_CAN0_IF2_ARB2_DIR_Msk (0x01UL << C_CAN0_IF2_ARB2_DIR_Pos) /*!< C_CAN0 IF2_ARB2: DIR Mask */
+#define C_CAN0_IF2_ARB2_XTD_Pos 14 /*!< C_CAN0 IF2_ARB2: XTD Position */
+#define C_CAN0_IF2_ARB2_XTD_Msk (0x01UL << C_CAN0_IF2_ARB2_XTD_Pos) /*!< C_CAN0 IF2_ARB2: XTD Mask */
+#define C_CAN0_IF2_ARB2_MSGVAL_Pos 15 /*!< C_CAN0 IF2_ARB2: MSGVAL Position */
+#define C_CAN0_IF2_ARB2_MSGVAL_Msk (0x01UL << C_CAN0_IF2_ARB2_MSGVAL_Pos) /*!< C_CAN0 IF2_ARB2: MSGVAL Mask */
+
+// ------------------------------------ C_CAN0_IF2_MCTRL ----------------------------------------
+#define C_CAN0_IF2_MCTRL_DLC3_0_Pos 0 /*!< C_CAN0 IF2_MCTRL: DLC3_0 Position */
+#define C_CAN0_IF2_MCTRL_DLC3_0_Msk (0x0fUL << C_CAN0_IF2_MCTRL_DLC3_0_Pos) /*!< C_CAN0 IF2_MCTRL: DLC3_0 Mask */
+#define C_CAN0_IF2_MCTRL_EOB_Pos 7 /*!< C_CAN0 IF2_MCTRL: EOB Position */
+#define C_CAN0_IF2_MCTRL_EOB_Msk (0x01UL << C_CAN0_IF2_MCTRL_EOB_Pos) /*!< C_CAN0 IF2_MCTRL: EOB Mask */
+#define C_CAN0_IF2_MCTRL_TXRQST_Pos 8 /*!< C_CAN0 IF2_MCTRL: TXRQST Position */
+#define C_CAN0_IF2_MCTRL_TXRQST_Msk (0x01UL << C_CAN0_IF2_MCTRL_TXRQST_Pos) /*!< C_CAN0 IF2_MCTRL: TXRQST Mask */
+#define C_CAN0_IF2_MCTRL_RMTEN_Pos 9 /*!< C_CAN0 IF2_MCTRL: RMTEN Position */
+#define C_CAN0_IF2_MCTRL_RMTEN_Msk (0x01UL << C_CAN0_IF2_MCTRL_RMTEN_Pos) /*!< C_CAN0 IF2_MCTRL: RMTEN Mask */
+#define C_CAN0_IF2_MCTRL_RXIE_Pos 10 /*!< C_CAN0 IF2_MCTRL: RXIE Position */
+#define C_CAN0_IF2_MCTRL_RXIE_Msk (0x01UL << C_CAN0_IF2_MCTRL_RXIE_Pos) /*!< C_CAN0 IF2_MCTRL: RXIE Mask */
+#define C_CAN0_IF2_MCTRL_TXIE_Pos 11 /*!< C_CAN0 IF2_MCTRL: TXIE Position */
+#define C_CAN0_IF2_MCTRL_TXIE_Msk (0x01UL << C_CAN0_IF2_MCTRL_TXIE_Pos) /*!< C_CAN0 IF2_MCTRL: TXIE Mask */
+#define C_CAN0_IF2_MCTRL_UMASK_Pos 12 /*!< C_CAN0 IF2_MCTRL: UMASK Position */
+#define C_CAN0_IF2_MCTRL_UMASK_Msk (0x01UL << C_CAN0_IF2_MCTRL_UMASK_Pos) /*!< C_CAN0 IF2_MCTRL: UMASK Mask */
+#define C_CAN0_IF2_MCTRL_INTPND_Pos 13 /*!< C_CAN0 IF2_MCTRL: INTPND Position */
+#define C_CAN0_IF2_MCTRL_INTPND_Msk (0x01UL << C_CAN0_IF2_MCTRL_INTPND_Pos) /*!< C_CAN0 IF2_MCTRL: INTPND Mask */
+#define C_CAN0_IF2_MCTRL_MSGLST_Pos 14 /*!< C_CAN0 IF2_MCTRL: MSGLST Position */
+#define C_CAN0_IF2_MCTRL_MSGLST_Msk (0x01UL << C_CAN0_IF2_MCTRL_MSGLST_Pos) /*!< C_CAN0 IF2_MCTRL: MSGLST Mask */
+#define C_CAN0_IF2_MCTRL_NEWDAT_Pos 15 /*!< C_CAN0 IF2_MCTRL: NEWDAT Position */
+#define C_CAN0_IF2_MCTRL_NEWDAT_Msk (0x01UL << C_CAN0_IF2_MCTRL_NEWDAT_Pos) /*!< C_CAN0 IF2_MCTRL: NEWDAT Mask */
+
+// ------------------------------------- C_CAN0_IF2_DA1 -----------------------------------------
+#define C_CAN0_IF2_DA1_DATA0_Pos 0 /*!< C_CAN0 IF2_DA1: DATA0 Position */
+#define C_CAN0_IF2_DA1_DATA0_Msk (0x000000ffUL << C_CAN0_IF2_DA1_DATA0_Pos) /*!< C_CAN0 IF2_DA1: DATA0 Mask */
+#define C_CAN0_IF2_DA1_DATA1_Pos 8 /*!< C_CAN0 IF2_DA1: DATA1 Position */
+#define C_CAN0_IF2_DA1_DATA1_Msk (0x000000ffUL << C_CAN0_IF2_DA1_DATA1_Pos) /*!< C_CAN0 IF2_DA1: DATA1 Mask */
+
+// ------------------------------------- C_CAN0_IF2_DA2 -----------------------------------------
+#define C_CAN0_IF2_DA2_DATA2_Pos 0 /*!< C_CAN0 IF2_DA2: DATA2 Position */
+#define C_CAN0_IF2_DA2_DATA2_Msk (0x000000ffUL << C_CAN0_IF2_DA2_DATA2_Pos) /*!< C_CAN0 IF2_DA2: DATA2 Mask */
+#define C_CAN0_IF2_DA2_DATA3_Pos 8 /*!< C_CAN0 IF2_DA2: DATA3 Position */
+#define C_CAN0_IF2_DA2_DATA3_Msk (0x000000ffUL << C_CAN0_IF2_DA2_DATA3_Pos) /*!< C_CAN0 IF2_DA2: DATA3 Mask */
+
+// ------------------------------------- C_CAN0_IF2_DB1 -----------------------------------------
+#define C_CAN0_IF2_DB1_DATA4_Pos 0 /*!< C_CAN0 IF2_DB1: DATA4 Position */
+#define C_CAN0_IF2_DB1_DATA4_Msk (0x000000ffUL << C_CAN0_IF2_DB1_DATA4_Pos) /*!< C_CAN0 IF2_DB1: DATA4 Mask */
+#define C_CAN0_IF2_DB1_DATA5_Pos 8 /*!< C_CAN0 IF2_DB1: DATA5 Position */
+#define C_CAN0_IF2_DB1_DATA5_Msk (0x000000ffUL << C_CAN0_IF2_DB1_DATA5_Pos) /*!< C_CAN0 IF2_DB1: DATA5 Mask */
+
+// ------------------------------------- C_CAN0_IF2_DB2 -----------------------------------------
+#define C_CAN0_IF2_DB2_DATA6_Pos 0 /*!< C_CAN0 IF2_DB2: DATA6 Position */
+#define C_CAN0_IF2_DB2_DATA6_Msk (0x000000ffUL << C_CAN0_IF2_DB2_DATA6_Pos) /*!< C_CAN0 IF2_DB2: DATA6 Mask */
+#define C_CAN0_IF2_DB2_DATA7_Pos 8 /*!< C_CAN0 IF2_DB2: DATA7 Position */
+#define C_CAN0_IF2_DB2_DATA7_Msk (0x000000ffUL << C_CAN0_IF2_DB2_DATA7_Pos) /*!< C_CAN0 IF2_DB2: DATA7 Mask */
+
+// -------------------------------------- C_CAN0_TXREQ1 -----------------------------------------
+#define C_CAN0_TXREQ1_TXRQST16_1_Pos 0 /*!< C_CAN0 TXREQ1: TXRQST16_1 Position */
+#define C_CAN0_TXREQ1_TXRQST16_1_Msk (0x0000ffffUL << C_CAN0_TXREQ1_TXRQST16_1_Pos) /*!< C_CAN0 TXREQ1: TXRQST16_1 Mask */
+
+// -------------------------------------- C_CAN0_TXREQ2 -----------------------------------------
+#define C_CAN0_TXREQ2_TXRQST32_17_Pos 0 /*!< C_CAN0 TXREQ2: TXRQST32_17 Position */
+#define C_CAN0_TXREQ2_TXRQST32_17_Msk (0x0000ffffUL << C_CAN0_TXREQ2_TXRQST32_17_Pos) /*!< C_CAN0 TXREQ2: TXRQST32_17 Mask */
+
+// --------------------------------------- C_CAN0_ND1 -------------------------------------------
+#define C_CAN0_ND1_NEWDAT16_1_Pos 0 /*!< C_CAN0 ND1: NEWDAT16_1 Position */
+#define C_CAN0_ND1_NEWDAT16_1_Msk (0x0000ffffUL << C_CAN0_ND1_NEWDAT16_1_Pos) /*!< C_CAN0 ND1: NEWDAT16_1 Mask */
+
+// --------------------------------------- C_CAN0_ND2 -------------------------------------------
+#define C_CAN0_ND2_NEWDAT32_17_Pos 0 /*!< C_CAN0 ND2: NEWDAT32_17 Position */
+#define C_CAN0_ND2_NEWDAT32_17_Msk (0x0000ffffUL << C_CAN0_ND2_NEWDAT32_17_Pos) /*!< C_CAN0 ND2: NEWDAT32_17 Mask */
+
+// --------------------------------------- C_CAN0_IR1 -------------------------------------------
+#define C_CAN0_IR1_INTPND16_1_Pos 0 /*!< C_CAN0 IR1: INTPND16_1 Position */
+#define C_CAN0_IR1_INTPND16_1_Msk (0x0000ffffUL << C_CAN0_IR1_INTPND16_1_Pos) /*!< C_CAN0 IR1: INTPND16_1 Mask */
+
+// --------------------------------------- C_CAN0_IR2 -------------------------------------------
+#define C_CAN0_IR2_INTPND32_17_Pos 0 /*!< C_CAN0 IR2: INTPND32_17 Position */
+#define C_CAN0_IR2_INTPND32_17_Msk (0x0000ffffUL << C_CAN0_IR2_INTPND32_17_Pos) /*!< C_CAN0 IR2: INTPND32_17 Mask */
+
+// -------------------------------------- C_CAN0_MSGV1 ------------------------------------------
+#define C_CAN0_MSGV1_MSGVAL16_1_Pos 0 /*!< C_CAN0 MSGV1: MSGVAL16_1 Position */
+#define C_CAN0_MSGV1_MSGVAL16_1_Msk (0x0000ffffUL << C_CAN0_MSGV1_MSGVAL16_1_Pos) /*!< C_CAN0 MSGV1: MSGVAL16_1 Mask */
+
+// -------------------------------------- C_CAN0_MSGV2 ------------------------------------------
+#define C_CAN0_MSGV2_MSGVAL32_17_Pos 0 /*!< C_CAN0 MSGV2: MSGVAL32_17 Position */
+#define C_CAN0_MSGV2_MSGVAL32_17_Msk (0x0000ffffUL << C_CAN0_MSGV2_MSGVAL32_17_Pos) /*!< C_CAN0 MSGV2: MSGVAL32_17 Mask */
+
+// -------------------------------------- C_CAN0_CLKDIV -----------------------------------------
+#define C_CAN0_CLKDIV_CLKDIVVAL_Pos 0 /*!< C_CAN0 CLKDIV: CLKDIVVAL Position */
+#define C_CAN0_CLKDIV_CLKDIVVAL_Msk (0x0fUL << C_CAN0_CLKDIV_CLKDIVVAL_Pos) /*!< C_CAN0 CLKDIV: CLKDIVVAL Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- ADC0 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------- ADC0_CR --------------------------------------------
+#define ADC0_CR_SEL_Pos 0 /*!< ADC0 CR: SEL Position */
+#define ADC0_CR_SEL_Msk (0x000000ffUL << ADC0_CR_SEL_Pos) /*!< ADC0 CR: SEL Mask */
+#define ADC0_CR_CLKDIV_Pos 8 /*!< ADC0 CR: CLKDIV Position */
+#define ADC0_CR_CLKDIV_Msk (0x000000ffUL << ADC0_CR_CLKDIV_Pos) /*!< ADC0 CR: CLKDIV Mask */
+#define ADC0_CR_BURST_Pos 16 /*!< ADC0 CR: BURST Position */
+#define ADC0_CR_BURST_Msk (0x01UL << ADC0_CR_BURST_Pos) /*!< ADC0 CR: BURST Mask */
+#define ADC0_CR_CLKS_Pos 17 /*!< ADC0 CR: CLKS Position */
+#define ADC0_CR_CLKS_Msk (0x07UL << ADC0_CR_CLKS_Pos) /*!< ADC0 CR: CLKS Mask */
+#define ADC0_CR_PDN_Pos 21 /*!< ADC0 CR: PDN Position */
+#define ADC0_CR_PDN_Msk (0x01UL << ADC0_CR_PDN_Pos) /*!< ADC0 CR: PDN Mask */
+#define ADC0_CR_START_Pos 24 /*!< ADC0 CR: START Position */
+#define ADC0_CR_START_Msk (0x07UL << ADC0_CR_START_Pos) /*!< ADC0 CR: START Mask */
+#define ADC0_CR_EDGE_Pos 27 /*!< ADC0 CR: EDGE Position */
+#define ADC0_CR_EDGE_Msk (0x01UL << ADC0_CR_EDGE_Pos) /*!< ADC0 CR: EDGE Mask */
+
+// ---------------------------------------- ADC0_GDR --------------------------------------------
+#define ADC0_GDR_V_VREF_Pos 6 /*!< ADC0 GDR: V_VREF Position */
+#define ADC0_GDR_V_VREF_Msk (0x000003ffUL << ADC0_GDR_V_VREF_Pos) /*!< ADC0 GDR: V_VREF Mask */
+#define ADC0_GDR_CHN_Pos 24 /*!< ADC0 GDR: CHN Position */
+#define ADC0_GDR_CHN_Msk (0x07UL << ADC0_GDR_CHN_Pos) /*!< ADC0 GDR: CHN Mask */
+#define ADC0_GDR_OVERRUN_Pos 30 /*!< ADC0 GDR: OVERRUN Position */
+#define ADC0_GDR_OVERRUN_Msk (0x01UL << ADC0_GDR_OVERRUN_Pos) /*!< ADC0 GDR: OVERRUN Mask */
+#define ADC0_GDR_DONE_Pos 31 /*!< ADC0 GDR: DONE Position */
+#define ADC0_GDR_DONE_Msk (0x01UL << ADC0_GDR_DONE_Pos) /*!< ADC0 GDR: DONE Mask */
+
+// --------------------------------------- ADC0_INTEN -------------------------------------------
+#define ADC0_INTEN_ADINTEN_Pos 0 /*!< ADC0 INTEN: ADINTEN Position */
+#define ADC0_INTEN_ADINTEN_Msk (0x000000ffUL << ADC0_INTEN_ADINTEN_Pos) /*!< ADC0 INTEN: ADINTEN Mask */
+#define ADC0_INTEN_ADGINTEN_Pos 8 /*!< ADC0 INTEN: ADGINTEN Position */
+#define ADC0_INTEN_ADGINTEN_Msk (0x01UL << ADC0_INTEN_ADGINTEN_Pos) /*!< ADC0 INTEN: ADGINTEN Mask */
+
+// ---------------------------------------- ADC0_DR0 --------------------------------------------
+#define ADC0_DR0_V_VREF_Pos 6 /*!< ADC0 DR0: V_VREF Position */
+#define ADC0_DR0_V_VREF_Msk (0x000003ffUL << ADC0_DR0_V_VREF_Pos) /*!< ADC0 DR0: V_VREF Mask */
+#define ADC0_DR0_OVERRUN_Pos 30 /*!< ADC0 DR0: OVERRUN Position */
+#define ADC0_DR0_OVERRUN_Msk (0x01UL << ADC0_DR0_OVERRUN_Pos) /*!< ADC0 DR0: OVERRUN Mask */
+#define ADC0_DR0_DONE_Pos 31 /*!< ADC0 DR0: DONE Position */
+#define ADC0_DR0_DONE_Msk (0x01UL << ADC0_DR0_DONE_Pos) /*!< ADC0 DR0: DONE Mask */
+
+// ---------------------------------------- ADC0_DR1 --------------------------------------------
+#define ADC0_DR1_V_VREF_Pos 6 /*!< ADC0 DR1: V_VREF Position */
+#define ADC0_DR1_V_VREF_Msk (0x000003ffUL << ADC0_DR1_V_VREF_Pos) /*!< ADC0 DR1: V_VREF Mask */
+#define ADC0_DR1_OVERRUN_Pos 30 /*!< ADC0 DR1: OVERRUN Position */
+#define ADC0_DR1_OVERRUN_Msk (0x01UL << ADC0_DR1_OVERRUN_Pos) /*!< ADC0 DR1: OVERRUN Mask */
+#define ADC0_DR1_DONE_Pos 31 /*!< ADC0 DR1: DONE Position */
+#define ADC0_DR1_DONE_Msk (0x01UL << ADC0_DR1_DONE_Pos) /*!< ADC0 DR1: DONE Mask */
+
+// ---------------------------------------- ADC0_DR2 --------------------------------------------
+#define ADC0_DR2_V_VREF_Pos 6 /*!< ADC0 DR2: V_VREF Position */
+#define ADC0_DR2_V_VREF_Msk (0x000003ffUL << ADC0_DR2_V_VREF_Pos) /*!< ADC0 DR2: V_VREF Mask */
+#define ADC0_DR2_OVERRUN_Pos 30 /*!< ADC0 DR2: OVERRUN Position */
+#define ADC0_DR2_OVERRUN_Msk (0x01UL << ADC0_DR2_OVERRUN_Pos) /*!< ADC0 DR2: OVERRUN Mask */
+#define ADC0_DR2_DONE_Pos 31 /*!< ADC0 DR2: DONE Position */
+#define ADC0_DR2_DONE_Msk (0x01UL << ADC0_DR2_DONE_Pos) /*!< ADC0 DR2: DONE Mask */
+
+// ---------------------------------------- ADC0_DR3 --------------------------------------------
+#define ADC0_DR3_V_VREF_Pos 6 /*!< ADC0 DR3: V_VREF Position */
+#define ADC0_DR3_V_VREF_Msk (0x000003ffUL << ADC0_DR3_V_VREF_Pos) /*!< ADC0 DR3: V_VREF Mask */
+#define ADC0_DR3_OVERRUN_Pos 30 /*!< ADC0 DR3: OVERRUN Position */
+#define ADC0_DR3_OVERRUN_Msk (0x01UL << ADC0_DR3_OVERRUN_Pos) /*!< ADC0 DR3: OVERRUN Mask */
+#define ADC0_DR3_DONE_Pos 31 /*!< ADC0 DR3: DONE Position */
+#define ADC0_DR3_DONE_Msk (0x01UL << ADC0_DR3_DONE_Pos) /*!< ADC0 DR3: DONE Mask */
+
+// ---------------------------------------- ADC0_DR4 --------------------------------------------
+#define ADC0_DR4_V_VREF_Pos 6 /*!< ADC0 DR4: V_VREF Position */
+#define ADC0_DR4_V_VREF_Msk (0x000003ffUL << ADC0_DR4_V_VREF_Pos) /*!< ADC0 DR4: V_VREF Mask */
+#define ADC0_DR4_OVERRUN_Pos 30 /*!< ADC0 DR4: OVERRUN Position */
+#define ADC0_DR4_OVERRUN_Msk (0x01UL << ADC0_DR4_OVERRUN_Pos) /*!< ADC0 DR4: OVERRUN Mask */
+#define ADC0_DR4_DONE_Pos 31 /*!< ADC0 DR4: DONE Position */
+#define ADC0_DR4_DONE_Msk (0x01UL << ADC0_DR4_DONE_Pos) /*!< ADC0 DR4: DONE Mask */
+
+// ---------------------------------------- ADC0_DR5 --------------------------------------------
+#define ADC0_DR5_V_VREF_Pos 6 /*!< ADC0 DR5: V_VREF Position */
+#define ADC0_DR5_V_VREF_Msk (0x000003ffUL << ADC0_DR5_V_VREF_Pos) /*!< ADC0 DR5: V_VREF Mask */
+#define ADC0_DR5_OVERRUN_Pos 30 /*!< ADC0 DR5: OVERRUN Position */
+#define ADC0_DR5_OVERRUN_Msk (0x01UL << ADC0_DR5_OVERRUN_Pos) /*!< ADC0 DR5: OVERRUN Mask */
+#define ADC0_DR5_DONE_Pos 31 /*!< ADC0 DR5: DONE Position */
+#define ADC0_DR5_DONE_Msk (0x01UL << ADC0_DR5_DONE_Pos) /*!< ADC0 DR5: DONE Mask */
+
+// ---------------------------------------- ADC0_DR6 --------------------------------------------
+#define ADC0_DR6_V_VREF_Pos 6 /*!< ADC0 DR6: V_VREF Position */
+#define ADC0_DR6_V_VREF_Msk (0x000003ffUL << ADC0_DR6_V_VREF_Pos) /*!< ADC0 DR6: V_VREF Mask */
+#define ADC0_DR6_OVERRUN_Pos 30 /*!< ADC0 DR6: OVERRUN Position */
+#define ADC0_DR6_OVERRUN_Msk (0x01UL << ADC0_DR6_OVERRUN_Pos) /*!< ADC0 DR6: OVERRUN Mask */
+#define ADC0_DR6_DONE_Pos 31 /*!< ADC0 DR6: DONE Position */
+#define ADC0_DR6_DONE_Msk (0x01UL << ADC0_DR6_DONE_Pos) /*!< ADC0 DR6: DONE Mask */
+
+// ---------------------------------------- ADC0_DR7 --------------------------------------------
+#define ADC0_DR7_V_VREF_Pos 6 /*!< ADC0 DR7: V_VREF Position */
+#define ADC0_DR7_V_VREF_Msk (0x000003ffUL << ADC0_DR7_V_VREF_Pos) /*!< ADC0 DR7: V_VREF Mask */
+#define ADC0_DR7_OVERRUN_Pos 30 /*!< ADC0 DR7: OVERRUN Position */
+#define ADC0_DR7_OVERRUN_Msk (0x01UL << ADC0_DR7_OVERRUN_Pos) /*!< ADC0 DR7: OVERRUN Mask */
+#define ADC0_DR7_DONE_Pos 31 /*!< ADC0 DR7: DONE Position */
+#define ADC0_DR7_DONE_Msk (0x01UL << ADC0_DR7_DONE_Pos) /*!< ADC0 DR7: DONE Mask */
+
+// ---------------------------------------- ADC0_STAT -------------------------------------------
+#define ADC0_STAT_DONE_Pos 0 /*!< ADC0 STAT: DONE Position */
+#define ADC0_STAT_DONE_Msk (0x000000ffUL << ADC0_STAT_DONE_Pos) /*!< ADC0 STAT: DONE Mask */
+#define ADC0_STAT_OVERUN_Pos 8 /*!< ADC0 STAT: OVERUN Position */
+#define ADC0_STAT_OVERUN_Msk (0x000000ffUL << ADC0_STAT_OVERUN_Pos) /*!< ADC0 STAT: OVERUN Mask */
+#define ADC0_STAT_ADINT_Pos 16 /*!< ADC0 STAT: ADINT Position */
+#define ADC0_STAT_ADINT_Msk (0x01UL << ADC0_STAT_ADINT_Pos) /*!< ADC0 STAT: ADINT Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- ADC1 Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------- ADC1_CR --------------------------------------------
+#define ADC1_CR_SEL_Pos 0 /*!< ADC1 CR: SEL Position */
+#define ADC1_CR_SEL_Msk (0x000000ffUL << ADC1_CR_SEL_Pos) /*!< ADC1 CR: SEL Mask */
+#define ADC1_CR_CLKDIV_Pos 8 /*!< ADC1 CR: CLKDIV Position */
+#define ADC1_CR_CLKDIV_Msk (0x000000ffUL << ADC1_CR_CLKDIV_Pos) /*!< ADC1 CR: CLKDIV Mask */
+#define ADC1_CR_BURST_Pos 16 /*!< ADC1 CR: BURST Position */
+#define ADC1_CR_BURST_Msk (0x01UL << ADC1_CR_BURST_Pos) /*!< ADC1 CR: BURST Mask */
+#define ADC1_CR_CLKS_Pos 17 /*!< ADC1 CR: CLKS Position */
+#define ADC1_CR_CLKS_Msk (0x07UL << ADC1_CR_CLKS_Pos) /*!< ADC1 CR: CLKS Mask */
+#define ADC1_CR_PDN_Pos 21 /*!< ADC1 CR: PDN Position */
+#define ADC1_CR_PDN_Msk (0x01UL << ADC1_CR_PDN_Pos) /*!< ADC1 CR: PDN Mask */
+#define ADC1_CR_START_Pos 24 /*!< ADC1 CR: START Position */
+#define ADC1_CR_START_Msk (0x07UL << ADC1_CR_START_Pos) /*!< ADC1 CR: START Mask */
+#define ADC1_CR_EDGE_Pos 27 /*!< ADC1 CR: EDGE Position */
+#define ADC1_CR_EDGE_Msk (0x01UL << ADC1_CR_EDGE_Pos) /*!< ADC1 CR: EDGE Mask */
+
+// ---------------------------------------- ADC1_GDR --------------------------------------------
+#define ADC1_GDR_V_VREF_Pos 6 /*!< ADC1 GDR: V_VREF Position */
+#define ADC1_GDR_V_VREF_Msk (0x000003ffUL << ADC1_GDR_V_VREF_Pos) /*!< ADC1 GDR: V_VREF Mask */
+#define ADC1_GDR_CHN_Pos 24 /*!< ADC1 GDR: CHN Position */
+#define ADC1_GDR_CHN_Msk (0x07UL << ADC1_GDR_CHN_Pos) /*!< ADC1 GDR: CHN Mask */
+#define ADC1_GDR_OVERRUN_Pos 30 /*!< ADC1 GDR: OVERRUN Position */
+#define ADC1_GDR_OVERRUN_Msk (0x01UL << ADC1_GDR_OVERRUN_Pos) /*!< ADC1 GDR: OVERRUN Mask */
+#define ADC1_GDR_DONE_Pos 31 /*!< ADC1 GDR: DONE Position */
+#define ADC1_GDR_DONE_Msk (0x01UL << ADC1_GDR_DONE_Pos) /*!< ADC1 GDR: DONE Mask */
+
+// --------------------------------------- ADC1_INTEN -------------------------------------------
+#define ADC1_INTEN_ADINTEN_Pos 0 /*!< ADC1 INTEN: ADINTEN Position */
+#define ADC1_INTEN_ADINTEN_Msk (0x000000ffUL << ADC1_INTEN_ADINTEN_Pos) /*!< ADC1 INTEN: ADINTEN Mask */
+#define ADC1_INTEN_ADGINTEN_Pos 8 /*!< ADC1 INTEN: ADGINTEN Position */
+#define ADC1_INTEN_ADGINTEN_Msk (0x01UL << ADC1_INTEN_ADGINTEN_Pos) /*!< ADC1 INTEN: ADGINTEN Mask */
+
+// ---------------------------------------- ADC1_DR0 --------------------------------------------
+#define ADC1_DR0_V_VREF_Pos 6 /*!< ADC1 DR0: V_VREF Position */
+#define ADC1_DR0_V_VREF_Msk (0x000003ffUL << ADC1_DR0_V_VREF_Pos) /*!< ADC1 DR0: V_VREF Mask */
+#define ADC1_DR0_OVERRUN_Pos 30 /*!< ADC1 DR0: OVERRUN Position */
+#define ADC1_DR0_OVERRUN_Msk (0x01UL << ADC1_DR0_OVERRUN_Pos) /*!< ADC1 DR0: OVERRUN Mask */
+#define ADC1_DR0_DONE_Pos 31 /*!< ADC1 DR0: DONE Position */
+#define ADC1_DR0_DONE_Msk (0x01UL << ADC1_DR0_DONE_Pos) /*!< ADC1 DR0: DONE Mask */
+
+// ---------------------------------------- ADC1_DR1 --------------------------------------------
+#define ADC1_DR1_V_VREF_Pos 6 /*!< ADC1 DR1: V_VREF Position */
+#define ADC1_DR1_V_VREF_Msk (0x000003ffUL << ADC1_DR1_V_VREF_Pos) /*!< ADC1 DR1: V_VREF Mask */
+#define ADC1_DR1_OVERRUN_Pos 30 /*!< ADC1 DR1: OVERRUN Position */
+#define ADC1_DR1_OVERRUN_Msk (0x01UL << ADC1_DR1_OVERRUN_Pos) /*!< ADC1 DR1: OVERRUN Mask */
+#define ADC1_DR1_DONE_Pos 31 /*!< ADC1 DR1: DONE Position */
+#define ADC1_DR1_DONE_Msk (0x01UL << ADC1_DR1_DONE_Pos) /*!< ADC1 DR1: DONE Mask */
+
+// ---------------------------------------- ADC1_DR2 --------------------------------------------
+#define ADC1_DR2_V_VREF_Pos 6 /*!< ADC1 DR2: V_VREF Position */
+#define ADC1_DR2_V_VREF_Msk (0x000003ffUL << ADC1_DR2_V_VREF_Pos) /*!< ADC1 DR2: V_VREF Mask */
+#define ADC1_DR2_OVERRUN_Pos 30 /*!< ADC1 DR2: OVERRUN Position */
+#define ADC1_DR2_OVERRUN_Msk (0x01UL << ADC1_DR2_OVERRUN_Pos) /*!< ADC1 DR2: OVERRUN Mask */
+#define ADC1_DR2_DONE_Pos 31 /*!< ADC1 DR2: DONE Position */
+#define ADC1_DR2_DONE_Msk (0x01UL << ADC1_DR2_DONE_Pos) /*!< ADC1 DR2: DONE Mask */
+
+// ---------------------------------------- ADC1_DR3 --------------------------------------------
+#define ADC1_DR3_V_VREF_Pos 6 /*!< ADC1 DR3: V_VREF Position */
+#define ADC1_DR3_V_VREF_Msk (0x000003ffUL << ADC1_DR3_V_VREF_Pos) /*!< ADC1 DR3: V_VREF Mask */
+#define ADC1_DR3_OVERRUN_Pos 30 /*!< ADC1 DR3: OVERRUN Position */
+#define ADC1_DR3_OVERRUN_Msk (0x01UL << ADC1_DR3_OVERRUN_Pos) /*!< ADC1 DR3: OVERRUN Mask */
+#define ADC1_DR3_DONE_Pos 31 /*!< ADC1 DR3: DONE Position */
+#define ADC1_DR3_DONE_Msk (0x01UL << ADC1_DR3_DONE_Pos) /*!< ADC1 DR3: DONE Mask */
+
+// ---------------------------------------- ADC1_DR4 --------------------------------------------
+#define ADC1_DR4_V_VREF_Pos 6 /*!< ADC1 DR4: V_VREF Position */
+#define ADC1_DR4_V_VREF_Msk (0x000003ffUL << ADC1_DR4_V_VREF_Pos) /*!< ADC1 DR4: V_VREF Mask */
+#define ADC1_DR4_OVERRUN_Pos 30 /*!< ADC1 DR4: OVERRUN Position */
+#define ADC1_DR4_OVERRUN_Msk (0x01UL << ADC1_DR4_OVERRUN_Pos) /*!< ADC1 DR4: OVERRUN Mask */
+#define ADC1_DR4_DONE_Pos 31 /*!< ADC1 DR4: DONE Position */
+#define ADC1_DR4_DONE_Msk (0x01UL << ADC1_DR4_DONE_Pos) /*!< ADC1 DR4: DONE Mask */
+
+// ---------------------------------------- ADC1_DR5 --------------------------------------------
+#define ADC1_DR5_V_VREF_Pos 6 /*!< ADC1 DR5: V_VREF Position */
+#define ADC1_DR5_V_VREF_Msk (0x000003ffUL << ADC1_DR5_V_VREF_Pos) /*!< ADC1 DR5: V_VREF Mask */
+#define ADC1_DR5_OVERRUN_Pos 30 /*!< ADC1 DR5: OVERRUN Position */
+#define ADC1_DR5_OVERRUN_Msk (0x01UL << ADC1_DR5_OVERRUN_Pos) /*!< ADC1 DR5: OVERRUN Mask */
+#define ADC1_DR5_DONE_Pos 31 /*!< ADC1 DR5: DONE Position */
+#define ADC1_DR5_DONE_Msk (0x01UL << ADC1_DR5_DONE_Pos) /*!< ADC1 DR5: DONE Mask */
+
+// ---------------------------------------- ADC1_DR6 --------------------------------------------
+#define ADC1_DR6_V_VREF_Pos 6 /*!< ADC1 DR6: V_VREF Position */
+#define ADC1_DR6_V_VREF_Msk (0x000003ffUL << ADC1_DR6_V_VREF_Pos) /*!< ADC1 DR6: V_VREF Mask */
+#define ADC1_DR6_OVERRUN_Pos 30 /*!< ADC1 DR6: OVERRUN Position */
+#define ADC1_DR6_OVERRUN_Msk (0x01UL << ADC1_DR6_OVERRUN_Pos) /*!< ADC1 DR6: OVERRUN Mask */
+#define ADC1_DR6_DONE_Pos 31 /*!< ADC1 DR6: DONE Position */
+#define ADC1_DR6_DONE_Msk (0x01UL << ADC1_DR6_DONE_Pos) /*!< ADC1 DR6: DONE Mask */
+
+// ---------------------------------------- ADC1_DR7 --------------------------------------------
+#define ADC1_DR7_V_VREF_Pos 6 /*!< ADC1 DR7: V_VREF Position */
+#define ADC1_DR7_V_VREF_Msk (0x000003ffUL << ADC1_DR7_V_VREF_Pos) /*!< ADC1 DR7: V_VREF Mask */
+#define ADC1_DR7_OVERRUN_Pos 30 /*!< ADC1 DR7: OVERRUN Position */
+#define ADC1_DR7_OVERRUN_Msk (0x01UL << ADC1_DR7_OVERRUN_Pos) /*!< ADC1 DR7: OVERRUN Mask */
+#define ADC1_DR7_DONE_Pos 31 /*!< ADC1 DR7: DONE Position */
+#define ADC1_DR7_DONE_Msk (0x01UL << ADC1_DR7_DONE_Pos) /*!< ADC1 DR7: DONE Mask */
+
+// ---------------------------------------- ADC1_STAT -------------------------------------------
+#define ADC1_STAT_DONE_Pos 0 /*!< ADC1 STAT: DONE Position */
+#define ADC1_STAT_DONE_Msk (0x000000ffUL << ADC1_STAT_DONE_Pos) /*!< ADC1 STAT: DONE Mask */
+#define ADC1_STAT_OVERUN_Pos 8 /*!< ADC1 STAT: OVERUN Position */
+#define ADC1_STAT_OVERUN_Msk (0x000000ffUL << ADC1_STAT_OVERUN_Pos) /*!< ADC1 STAT: OVERUN Mask */
+#define ADC1_STAT_ADINT_Pos 16 /*!< ADC1 STAT: ADINT Position */
+#define ADC1_STAT_ADINT_Msk (0x01UL << ADC1_STAT_ADINT_Pos) /*!< ADC1 STAT: ADINT Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_PORT Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// -------------------------------------- GPIO_PORT_B0 ------------------------------------------
+#define GPIO_PORT_B0_PBYTE_Pos 0 /*!< GPIO_PORT B0: PBYTE Position */
+#define GPIO_PORT_B0_PBYTE_Msk (0x01UL << GPIO_PORT_B0_PBYTE_Pos) /*!< GPIO_PORT B0: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B1 ------------------------------------------
+#define GPIO_PORT_B1_PBYTE_Pos 0 /*!< GPIO_PORT B1: PBYTE Position */
+#define GPIO_PORT_B1_PBYTE_Msk (0x01UL << GPIO_PORT_B1_PBYTE_Pos) /*!< GPIO_PORT B1: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B2 ------------------------------------------
+#define GPIO_PORT_B2_PBYTE_Pos 0 /*!< GPIO_PORT B2: PBYTE Position */
+#define GPIO_PORT_B2_PBYTE_Msk (0x01UL << GPIO_PORT_B2_PBYTE_Pos) /*!< GPIO_PORT B2: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B3 ------------------------------------------
+#define GPIO_PORT_B3_PBYTE_Pos 0 /*!< GPIO_PORT B3: PBYTE Position */
+#define GPIO_PORT_B3_PBYTE_Msk (0x01UL << GPIO_PORT_B3_PBYTE_Pos) /*!< GPIO_PORT B3: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B4 ------------------------------------------
+#define GPIO_PORT_B4_PBYTE_Pos 0 /*!< GPIO_PORT B4: PBYTE Position */
+#define GPIO_PORT_B4_PBYTE_Msk (0x01UL << GPIO_PORT_B4_PBYTE_Pos) /*!< GPIO_PORT B4: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B5 ------------------------------------------
+#define GPIO_PORT_B5_PBYTE_Pos 0 /*!< GPIO_PORT B5: PBYTE Position */
+#define GPIO_PORT_B5_PBYTE_Msk (0x01UL << GPIO_PORT_B5_PBYTE_Pos) /*!< GPIO_PORT B5: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B6 ------------------------------------------
+#define GPIO_PORT_B6_PBYTE_Pos 0 /*!< GPIO_PORT B6: PBYTE Position */
+#define GPIO_PORT_B6_PBYTE_Msk (0x01UL << GPIO_PORT_B6_PBYTE_Pos) /*!< GPIO_PORT B6: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B7 ------------------------------------------
+#define GPIO_PORT_B7_PBYTE_Pos 0 /*!< GPIO_PORT B7: PBYTE Position */
+#define GPIO_PORT_B7_PBYTE_Msk (0x01UL << GPIO_PORT_B7_PBYTE_Pos) /*!< GPIO_PORT B7: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B8 ------------------------------------------
+#define GPIO_PORT_B8_PBYTE_Pos 0 /*!< GPIO_PORT B8: PBYTE Position */
+#define GPIO_PORT_B8_PBYTE_Msk (0x01UL << GPIO_PORT_B8_PBYTE_Pos) /*!< GPIO_PORT B8: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B9 ------------------------------------------
+#define GPIO_PORT_B9_PBYTE_Pos 0 /*!< GPIO_PORT B9: PBYTE Position */
+#define GPIO_PORT_B9_PBYTE_Msk (0x01UL << GPIO_PORT_B9_PBYTE_Pos) /*!< GPIO_PORT B9: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B10 -----------------------------------------
+#define GPIO_PORT_B10_PBYTE_Pos 0 /*!< GPIO_PORT B10: PBYTE Position */
+#define GPIO_PORT_B10_PBYTE_Msk (0x01UL << GPIO_PORT_B10_PBYTE_Pos) /*!< GPIO_PORT B10: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B11 -----------------------------------------
+#define GPIO_PORT_B11_PBYTE_Pos 0 /*!< GPIO_PORT B11: PBYTE Position */
+#define GPIO_PORT_B11_PBYTE_Msk (0x01UL << GPIO_PORT_B11_PBYTE_Pos) /*!< GPIO_PORT B11: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B12 -----------------------------------------
+#define GPIO_PORT_B12_PBYTE_Pos 0 /*!< GPIO_PORT B12: PBYTE Position */
+#define GPIO_PORT_B12_PBYTE_Msk (0x01UL << GPIO_PORT_B12_PBYTE_Pos) /*!< GPIO_PORT B12: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B13 -----------------------------------------
+#define GPIO_PORT_B13_PBYTE_Pos 0 /*!< GPIO_PORT B13: PBYTE Position */
+#define GPIO_PORT_B13_PBYTE_Msk (0x01UL << GPIO_PORT_B13_PBYTE_Pos) /*!< GPIO_PORT B13: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B14 -----------------------------------------
+#define GPIO_PORT_B14_PBYTE_Pos 0 /*!< GPIO_PORT B14: PBYTE Position */
+#define GPIO_PORT_B14_PBYTE_Msk (0x01UL << GPIO_PORT_B14_PBYTE_Pos) /*!< GPIO_PORT B14: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B15 -----------------------------------------
+#define GPIO_PORT_B15_PBYTE_Pos 0 /*!< GPIO_PORT B15: PBYTE Position */
+#define GPIO_PORT_B15_PBYTE_Msk (0x01UL << GPIO_PORT_B15_PBYTE_Pos) /*!< GPIO_PORT B15: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B16 -----------------------------------------
+#define GPIO_PORT_B16_PBYTE_Pos 0 /*!< GPIO_PORT B16: PBYTE Position */
+#define GPIO_PORT_B16_PBYTE_Msk (0x01UL << GPIO_PORT_B16_PBYTE_Pos) /*!< GPIO_PORT B16: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B17 -----------------------------------------
+#define GPIO_PORT_B17_PBYTE_Pos 0 /*!< GPIO_PORT B17: PBYTE Position */
+#define GPIO_PORT_B17_PBYTE_Msk (0x01UL << GPIO_PORT_B17_PBYTE_Pos) /*!< GPIO_PORT B17: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B18 -----------------------------------------
+#define GPIO_PORT_B18_PBYTE_Pos 0 /*!< GPIO_PORT B18: PBYTE Position */
+#define GPIO_PORT_B18_PBYTE_Msk (0x01UL << GPIO_PORT_B18_PBYTE_Pos) /*!< GPIO_PORT B18: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B19 -----------------------------------------
+#define GPIO_PORT_B19_PBYTE_Pos 0 /*!< GPIO_PORT B19: PBYTE Position */
+#define GPIO_PORT_B19_PBYTE_Msk (0x01UL << GPIO_PORT_B19_PBYTE_Pos) /*!< GPIO_PORT B19: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B20 -----------------------------------------
+#define GPIO_PORT_B20_PBYTE_Pos 0 /*!< GPIO_PORT B20: PBYTE Position */
+#define GPIO_PORT_B20_PBYTE_Msk (0x01UL << GPIO_PORT_B20_PBYTE_Pos) /*!< GPIO_PORT B20: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B21 -----------------------------------------
+#define GPIO_PORT_B21_PBYTE_Pos 0 /*!< GPIO_PORT B21: PBYTE Position */
+#define GPIO_PORT_B21_PBYTE_Msk (0x01UL << GPIO_PORT_B21_PBYTE_Pos) /*!< GPIO_PORT B21: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B22 -----------------------------------------
+#define GPIO_PORT_B22_PBYTE_Pos 0 /*!< GPIO_PORT B22: PBYTE Position */
+#define GPIO_PORT_B22_PBYTE_Msk (0x01UL << GPIO_PORT_B22_PBYTE_Pos) /*!< GPIO_PORT B22: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B23 -----------------------------------------
+#define GPIO_PORT_B23_PBYTE_Pos 0 /*!< GPIO_PORT B23: PBYTE Position */
+#define GPIO_PORT_B23_PBYTE_Msk (0x01UL << GPIO_PORT_B23_PBYTE_Pos) /*!< GPIO_PORT B23: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B24 -----------------------------------------
+#define GPIO_PORT_B24_PBYTE_Pos 0 /*!< GPIO_PORT B24: PBYTE Position */
+#define GPIO_PORT_B24_PBYTE_Msk (0x01UL << GPIO_PORT_B24_PBYTE_Pos) /*!< GPIO_PORT B24: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B25 -----------------------------------------
+#define GPIO_PORT_B25_PBYTE_Pos 0 /*!< GPIO_PORT B25: PBYTE Position */
+#define GPIO_PORT_B25_PBYTE_Msk (0x01UL << GPIO_PORT_B25_PBYTE_Pos) /*!< GPIO_PORT B25: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B26 -----------------------------------------
+#define GPIO_PORT_B26_PBYTE_Pos 0 /*!< GPIO_PORT B26: PBYTE Position */
+#define GPIO_PORT_B26_PBYTE_Msk (0x01UL << GPIO_PORT_B26_PBYTE_Pos) /*!< GPIO_PORT B26: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B27 -----------------------------------------
+#define GPIO_PORT_B27_PBYTE_Pos 0 /*!< GPIO_PORT B27: PBYTE Position */
+#define GPIO_PORT_B27_PBYTE_Msk (0x01UL << GPIO_PORT_B27_PBYTE_Pos) /*!< GPIO_PORT B27: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B28 -----------------------------------------
+#define GPIO_PORT_B28_PBYTE_Pos 0 /*!< GPIO_PORT B28: PBYTE Position */
+#define GPIO_PORT_B28_PBYTE_Msk (0x01UL << GPIO_PORT_B28_PBYTE_Pos) /*!< GPIO_PORT B28: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B29 -----------------------------------------
+#define GPIO_PORT_B29_PBYTE_Pos 0 /*!< GPIO_PORT B29: PBYTE Position */
+#define GPIO_PORT_B29_PBYTE_Msk (0x01UL << GPIO_PORT_B29_PBYTE_Pos) /*!< GPIO_PORT B29: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B30 -----------------------------------------
+#define GPIO_PORT_B30_PBYTE_Pos 0 /*!< GPIO_PORT B30: PBYTE Position */
+#define GPIO_PORT_B30_PBYTE_Msk (0x01UL << GPIO_PORT_B30_PBYTE_Pos) /*!< GPIO_PORT B30: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B31 -----------------------------------------
+#define GPIO_PORT_B31_PBYTE_Pos 0 /*!< GPIO_PORT B31: PBYTE Position */
+#define GPIO_PORT_B31_PBYTE_Msk (0x01UL << GPIO_PORT_B31_PBYTE_Pos) /*!< GPIO_PORT B31: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B32 -----------------------------------------
+#define GPIO_PORT_B32_PBYTE_Pos 0 /*!< GPIO_PORT B32: PBYTE Position */
+#define GPIO_PORT_B32_PBYTE_Msk (0x01UL << GPIO_PORT_B32_PBYTE_Pos) /*!< GPIO_PORT B32: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B33 -----------------------------------------
+#define GPIO_PORT_B33_PBYTE_Pos 0 /*!< GPIO_PORT B33: PBYTE Position */
+#define GPIO_PORT_B33_PBYTE_Msk (0x01UL << GPIO_PORT_B33_PBYTE_Pos) /*!< GPIO_PORT B33: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B34 -----------------------------------------
+#define GPIO_PORT_B34_PBYTE_Pos 0 /*!< GPIO_PORT B34: PBYTE Position */
+#define GPIO_PORT_B34_PBYTE_Msk (0x01UL << GPIO_PORT_B34_PBYTE_Pos) /*!< GPIO_PORT B34: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B35 -----------------------------------------
+#define GPIO_PORT_B35_PBYTE_Pos 0 /*!< GPIO_PORT B35: PBYTE Position */
+#define GPIO_PORT_B35_PBYTE_Msk (0x01UL << GPIO_PORT_B35_PBYTE_Pos) /*!< GPIO_PORT B35: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B36 -----------------------------------------
+#define GPIO_PORT_B36_PBYTE_Pos 0 /*!< GPIO_PORT B36: PBYTE Position */
+#define GPIO_PORT_B36_PBYTE_Msk (0x01UL << GPIO_PORT_B36_PBYTE_Pos) /*!< GPIO_PORT B36: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B37 -----------------------------------------
+#define GPIO_PORT_B37_PBYTE_Pos 0 /*!< GPIO_PORT B37: PBYTE Position */
+#define GPIO_PORT_B37_PBYTE_Msk (0x01UL << GPIO_PORT_B37_PBYTE_Pos) /*!< GPIO_PORT B37: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B38 -----------------------------------------
+#define GPIO_PORT_B38_PBYTE_Pos 0 /*!< GPIO_PORT B38: PBYTE Position */
+#define GPIO_PORT_B38_PBYTE_Msk (0x01UL << GPIO_PORT_B38_PBYTE_Pos) /*!< GPIO_PORT B38: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B39 -----------------------------------------
+#define GPIO_PORT_B39_PBYTE_Pos 0 /*!< GPIO_PORT B39: PBYTE Position */
+#define GPIO_PORT_B39_PBYTE_Msk (0x01UL << GPIO_PORT_B39_PBYTE_Pos) /*!< GPIO_PORT B39: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B40 -----------------------------------------
+#define GPIO_PORT_B40_PBYTE_Pos 0 /*!< GPIO_PORT B40: PBYTE Position */
+#define GPIO_PORT_B40_PBYTE_Msk (0x01UL << GPIO_PORT_B40_PBYTE_Pos) /*!< GPIO_PORT B40: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B41 -----------------------------------------
+#define GPIO_PORT_B41_PBYTE_Pos 0 /*!< GPIO_PORT B41: PBYTE Position */
+#define GPIO_PORT_B41_PBYTE_Msk (0x01UL << GPIO_PORT_B41_PBYTE_Pos) /*!< GPIO_PORT B41: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B42 -----------------------------------------
+#define GPIO_PORT_B42_PBYTE_Pos 0 /*!< GPIO_PORT B42: PBYTE Position */
+#define GPIO_PORT_B42_PBYTE_Msk (0x01UL << GPIO_PORT_B42_PBYTE_Pos) /*!< GPIO_PORT B42: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B43 -----------------------------------------
+#define GPIO_PORT_B43_PBYTE_Pos 0 /*!< GPIO_PORT B43: PBYTE Position */
+#define GPIO_PORT_B43_PBYTE_Msk (0x01UL << GPIO_PORT_B43_PBYTE_Pos) /*!< GPIO_PORT B43: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B44 -----------------------------------------
+#define GPIO_PORT_B44_PBYTE_Pos 0 /*!< GPIO_PORT B44: PBYTE Position */
+#define GPIO_PORT_B44_PBYTE_Msk (0x01UL << GPIO_PORT_B44_PBYTE_Pos) /*!< GPIO_PORT B44: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B45 -----------------------------------------
+#define GPIO_PORT_B45_PBYTE_Pos 0 /*!< GPIO_PORT B45: PBYTE Position */
+#define GPIO_PORT_B45_PBYTE_Msk (0x01UL << GPIO_PORT_B45_PBYTE_Pos) /*!< GPIO_PORT B45: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B46 -----------------------------------------
+#define GPIO_PORT_B46_PBYTE_Pos 0 /*!< GPIO_PORT B46: PBYTE Position */
+#define GPIO_PORT_B46_PBYTE_Msk (0x01UL << GPIO_PORT_B46_PBYTE_Pos) /*!< GPIO_PORT B46: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B47 -----------------------------------------
+#define GPIO_PORT_B47_PBYTE_Pos 0 /*!< GPIO_PORT B47: PBYTE Position */
+#define GPIO_PORT_B47_PBYTE_Msk (0x01UL << GPIO_PORT_B47_PBYTE_Pos) /*!< GPIO_PORT B47: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B48 -----------------------------------------
+#define GPIO_PORT_B48_PBYTE_Pos 0 /*!< GPIO_PORT B48: PBYTE Position */
+#define GPIO_PORT_B48_PBYTE_Msk (0x01UL << GPIO_PORT_B48_PBYTE_Pos) /*!< GPIO_PORT B48: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B49 -----------------------------------------
+#define GPIO_PORT_B49_PBYTE_Pos 0 /*!< GPIO_PORT B49: PBYTE Position */
+#define GPIO_PORT_B49_PBYTE_Msk (0x01UL << GPIO_PORT_B49_PBYTE_Pos) /*!< GPIO_PORT B49: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B50 -----------------------------------------
+#define GPIO_PORT_B50_PBYTE_Pos 0 /*!< GPIO_PORT B50: PBYTE Position */
+#define GPIO_PORT_B50_PBYTE_Msk (0x01UL << GPIO_PORT_B50_PBYTE_Pos) /*!< GPIO_PORT B50: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B51 -----------------------------------------
+#define GPIO_PORT_B51_PBYTE_Pos 0 /*!< GPIO_PORT B51: PBYTE Position */
+#define GPIO_PORT_B51_PBYTE_Msk (0x01UL << GPIO_PORT_B51_PBYTE_Pos) /*!< GPIO_PORT B51: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B52 -----------------------------------------
+#define GPIO_PORT_B52_PBYTE_Pos 0 /*!< GPIO_PORT B52: PBYTE Position */
+#define GPIO_PORT_B52_PBYTE_Msk (0x01UL << GPIO_PORT_B52_PBYTE_Pos) /*!< GPIO_PORT B52: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B53 -----------------------------------------
+#define GPIO_PORT_B53_PBYTE_Pos 0 /*!< GPIO_PORT B53: PBYTE Position */
+#define GPIO_PORT_B53_PBYTE_Msk (0x01UL << GPIO_PORT_B53_PBYTE_Pos) /*!< GPIO_PORT B53: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B54 -----------------------------------------
+#define GPIO_PORT_B54_PBYTE_Pos 0 /*!< GPIO_PORT B54: PBYTE Position */
+#define GPIO_PORT_B54_PBYTE_Msk (0x01UL << GPIO_PORT_B54_PBYTE_Pos) /*!< GPIO_PORT B54: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B55 -----------------------------------------
+#define GPIO_PORT_B55_PBYTE_Pos 0 /*!< GPIO_PORT B55: PBYTE Position */
+#define GPIO_PORT_B55_PBYTE_Msk (0x01UL << GPIO_PORT_B55_PBYTE_Pos) /*!< GPIO_PORT B55: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B56 -----------------------------------------
+#define GPIO_PORT_B56_PBYTE_Pos 0 /*!< GPIO_PORT B56: PBYTE Position */
+#define GPIO_PORT_B56_PBYTE_Msk (0x01UL << GPIO_PORT_B56_PBYTE_Pos) /*!< GPIO_PORT B56: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B57 -----------------------------------------
+#define GPIO_PORT_B57_PBYTE_Pos 0 /*!< GPIO_PORT B57: PBYTE Position */
+#define GPIO_PORT_B57_PBYTE_Msk (0x01UL << GPIO_PORT_B57_PBYTE_Pos) /*!< GPIO_PORT B57: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B58 -----------------------------------------
+#define GPIO_PORT_B58_PBYTE_Pos 0 /*!< GPIO_PORT B58: PBYTE Position */
+#define GPIO_PORT_B58_PBYTE_Msk (0x01UL << GPIO_PORT_B58_PBYTE_Pos) /*!< GPIO_PORT B58: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B59 -----------------------------------------
+#define GPIO_PORT_B59_PBYTE_Pos 0 /*!< GPIO_PORT B59: PBYTE Position */
+#define GPIO_PORT_B59_PBYTE_Msk (0x01UL << GPIO_PORT_B59_PBYTE_Pos) /*!< GPIO_PORT B59: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B60 -----------------------------------------
+#define GPIO_PORT_B60_PBYTE_Pos 0 /*!< GPIO_PORT B60: PBYTE Position */
+#define GPIO_PORT_B60_PBYTE_Msk (0x01UL << GPIO_PORT_B60_PBYTE_Pos) /*!< GPIO_PORT B60: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B61 -----------------------------------------
+#define GPIO_PORT_B61_PBYTE_Pos 0 /*!< GPIO_PORT B61: PBYTE Position */
+#define GPIO_PORT_B61_PBYTE_Msk (0x01UL << GPIO_PORT_B61_PBYTE_Pos) /*!< GPIO_PORT B61: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B62 -----------------------------------------
+#define GPIO_PORT_B62_PBYTE_Pos 0 /*!< GPIO_PORT B62: PBYTE Position */
+#define GPIO_PORT_B62_PBYTE_Msk (0x01UL << GPIO_PORT_B62_PBYTE_Pos) /*!< GPIO_PORT B62: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B63 -----------------------------------------
+#define GPIO_PORT_B63_PBYTE_Pos 0 /*!< GPIO_PORT B63: PBYTE Position */
+#define GPIO_PORT_B63_PBYTE_Msk (0x01UL << GPIO_PORT_B63_PBYTE_Pos) /*!< GPIO_PORT B63: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B64 -----------------------------------------
+#define GPIO_PORT_B64_PBYTE_Pos 0 /*!< GPIO_PORT B64: PBYTE Position */
+#define GPIO_PORT_B64_PBYTE_Msk (0x01UL << GPIO_PORT_B64_PBYTE_Pos) /*!< GPIO_PORT B64: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B65 -----------------------------------------
+#define GPIO_PORT_B65_PBYTE_Pos 0 /*!< GPIO_PORT B65: PBYTE Position */
+#define GPIO_PORT_B65_PBYTE_Msk (0x01UL << GPIO_PORT_B65_PBYTE_Pos) /*!< GPIO_PORT B65: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B66 -----------------------------------------
+#define GPIO_PORT_B66_PBYTE_Pos 0 /*!< GPIO_PORT B66: PBYTE Position */
+#define GPIO_PORT_B66_PBYTE_Msk (0x01UL << GPIO_PORT_B66_PBYTE_Pos) /*!< GPIO_PORT B66: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B67 -----------------------------------------
+#define GPIO_PORT_B67_PBYTE_Pos 0 /*!< GPIO_PORT B67: PBYTE Position */
+#define GPIO_PORT_B67_PBYTE_Msk (0x01UL << GPIO_PORT_B67_PBYTE_Pos) /*!< GPIO_PORT B67: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B68 -----------------------------------------
+#define GPIO_PORT_B68_PBYTE_Pos 0 /*!< GPIO_PORT B68: PBYTE Position */
+#define GPIO_PORT_B68_PBYTE_Msk (0x01UL << GPIO_PORT_B68_PBYTE_Pos) /*!< GPIO_PORT B68: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B69 -----------------------------------------
+#define GPIO_PORT_B69_PBYTE_Pos 0 /*!< GPIO_PORT B69: PBYTE Position */
+#define GPIO_PORT_B69_PBYTE_Msk (0x01UL << GPIO_PORT_B69_PBYTE_Pos) /*!< GPIO_PORT B69: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B70 -----------------------------------------
+#define GPIO_PORT_B70_PBYTE_Pos 0 /*!< GPIO_PORT B70: PBYTE Position */
+#define GPIO_PORT_B70_PBYTE_Msk (0x01UL << GPIO_PORT_B70_PBYTE_Pos) /*!< GPIO_PORT B70: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B71 -----------------------------------------
+#define GPIO_PORT_B71_PBYTE_Pos 0 /*!< GPIO_PORT B71: PBYTE Position */
+#define GPIO_PORT_B71_PBYTE_Msk (0x01UL << GPIO_PORT_B71_PBYTE_Pos) /*!< GPIO_PORT B71: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B72 -----------------------------------------
+#define GPIO_PORT_B72_PBYTE_Pos 0 /*!< GPIO_PORT B72: PBYTE Position */
+#define GPIO_PORT_B72_PBYTE_Msk (0x01UL << GPIO_PORT_B72_PBYTE_Pos) /*!< GPIO_PORT B72: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B73 -----------------------------------------
+#define GPIO_PORT_B73_PBYTE_Pos 0 /*!< GPIO_PORT B73: PBYTE Position */
+#define GPIO_PORT_B73_PBYTE_Msk (0x01UL << GPIO_PORT_B73_PBYTE_Pos) /*!< GPIO_PORT B73: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B74 -----------------------------------------
+#define GPIO_PORT_B74_PBYTE_Pos 0 /*!< GPIO_PORT B74: PBYTE Position */
+#define GPIO_PORT_B74_PBYTE_Msk (0x01UL << GPIO_PORT_B74_PBYTE_Pos) /*!< GPIO_PORT B74: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B75 -----------------------------------------
+#define GPIO_PORT_B75_PBYTE_Pos 0 /*!< GPIO_PORT B75: PBYTE Position */
+#define GPIO_PORT_B75_PBYTE_Msk (0x01UL << GPIO_PORT_B75_PBYTE_Pos) /*!< GPIO_PORT B75: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B76 -----------------------------------------
+#define GPIO_PORT_B76_PBYTE_Pos 0 /*!< GPIO_PORT B76: PBYTE Position */
+#define GPIO_PORT_B76_PBYTE_Msk (0x01UL << GPIO_PORT_B76_PBYTE_Pos) /*!< GPIO_PORT B76: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B77 -----------------------------------------
+#define GPIO_PORT_B77_PBYTE_Pos 0 /*!< GPIO_PORT B77: PBYTE Position */
+#define GPIO_PORT_B77_PBYTE_Msk (0x01UL << GPIO_PORT_B77_PBYTE_Pos) /*!< GPIO_PORT B77: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B78 -----------------------------------------
+#define GPIO_PORT_B78_PBYTE_Pos 0 /*!< GPIO_PORT B78: PBYTE Position */
+#define GPIO_PORT_B78_PBYTE_Msk (0x01UL << GPIO_PORT_B78_PBYTE_Pos) /*!< GPIO_PORT B78: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B79 -----------------------------------------
+#define GPIO_PORT_B79_PBYTE_Pos 0 /*!< GPIO_PORT B79: PBYTE Position */
+#define GPIO_PORT_B79_PBYTE_Msk (0x01UL << GPIO_PORT_B79_PBYTE_Pos) /*!< GPIO_PORT B79: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B80 -----------------------------------------
+#define GPIO_PORT_B80_PBYTE_Pos 0 /*!< GPIO_PORT B80: PBYTE Position */
+#define GPIO_PORT_B80_PBYTE_Msk (0x01UL << GPIO_PORT_B80_PBYTE_Pos) /*!< GPIO_PORT B80: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B81 -----------------------------------------
+#define GPIO_PORT_B81_PBYTE_Pos 0 /*!< GPIO_PORT B81: PBYTE Position */
+#define GPIO_PORT_B81_PBYTE_Msk (0x01UL << GPIO_PORT_B81_PBYTE_Pos) /*!< GPIO_PORT B81: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B82 -----------------------------------------
+#define GPIO_PORT_B82_PBYTE_Pos 0 /*!< GPIO_PORT B82: PBYTE Position */
+#define GPIO_PORT_B82_PBYTE_Msk (0x01UL << GPIO_PORT_B82_PBYTE_Pos) /*!< GPIO_PORT B82: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B83 -----------------------------------------
+#define GPIO_PORT_B83_PBYTE_Pos 0 /*!< GPIO_PORT B83: PBYTE Position */
+#define GPIO_PORT_B83_PBYTE_Msk (0x01UL << GPIO_PORT_B83_PBYTE_Pos) /*!< GPIO_PORT B83: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B84 -----------------------------------------
+#define GPIO_PORT_B84_PBYTE_Pos 0 /*!< GPIO_PORT B84: PBYTE Position */
+#define GPIO_PORT_B84_PBYTE_Msk (0x01UL << GPIO_PORT_B84_PBYTE_Pos) /*!< GPIO_PORT B84: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B85 -----------------------------------------
+#define GPIO_PORT_B85_PBYTE_Pos 0 /*!< GPIO_PORT B85: PBYTE Position */
+#define GPIO_PORT_B85_PBYTE_Msk (0x01UL << GPIO_PORT_B85_PBYTE_Pos) /*!< GPIO_PORT B85: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B86 -----------------------------------------
+#define GPIO_PORT_B86_PBYTE_Pos 0 /*!< GPIO_PORT B86: PBYTE Position */
+#define GPIO_PORT_B86_PBYTE_Msk (0x01UL << GPIO_PORT_B86_PBYTE_Pos) /*!< GPIO_PORT B86: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B87 -----------------------------------------
+#define GPIO_PORT_B87_PBYTE_Pos 0 /*!< GPIO_PORT B87: PBYTE Position */
+#define GPIO_PORT_B87_PBYTE_Msk (0x01UL << GPIO_PORT_B87_PBYTE_Pos) /*!< GPIO_PORT B87: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B88 -----------------------------------------
+#define GPIO_PORT_B88_PBYTE_Pos 0 /*!< GPIO_PORT B88: PBYTE Position */
+#define GPIO_PORT_B88_PBYTE_Msk (0x01UL << GPIO_PORT_B88_PBYTE_Pos) /*!< GPIO_PORT B88: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B89 -----------------------------------------
+#define GPIO_PORT_B89_PBYTE_Pos 0 /*!< GPIO_PORT B89: PBYTE Position */
+#define GPIO_PORT_B89_PBYTE_Msk (0x01UL << GPIO_PORT_B89_PBYTE_Pos) /*!< GPIO_PORT B89: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B90 -----------------------------------------
+#define GPIO_PORT_B90_PBYTE_Pos 0 /*!< GPIO_PORT B90: PBYTE Position */
+#define GPIO_PORT_B90_PBYTE_Msk (0x01UL << GPIO_PORT_B90_PBYTE_Pos) /*!< GPIO_PORT B90: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B91 -----------------------------------------
+#define GPIO_PORT_B91_PBYTE_Pos 0 /*!< GPIO_PORT B91: PBYTE Position */
+#define GPIO_PORT_B91_PBYTE_Msk (0x01UL << GPIO_PORT_B91_PBYTE_Pos) /*!< GPIO_PORT B91: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B92 -----------------------------------------
+#define GPIO_PORT_B92_PBYTE_Pos 0 /*!< GPIO_PORT B92: PBYTE Position */
+#define GPIO_PORT_B92_PBYTE_Msk (0x01UL << GPIO_PORT_B92_PBYTE_Pos) /*!< GPIO_PORT B92: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B93 -----------------------------------------
+#define GPIO_PORT_B93_PBYTE_Pos 0 /*!< GPIO_PORT B93: PBYTE Position */
+#define GPIO_PORT_B93_PBYTE_Msk (0x01UL << GPIO_PORT_B93_PBYTE_Pos) /*!< GPIO_PORT B93: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B94 -----------------------------------------
+#define GPIO_PORT_B94_PBYTE_Pos 0 /*!< GPIO_PORT B94: PBYTE Position */
+#define GPIO_PORT_B94_PBYTE_Msk (0x01UL << GPIO_PORT_B94_PBYTE_Pos) /*!< GPIO_PORT B94: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B95 -----------------------------------------
+#define GPIO_PORT_B95_PBYTE_Pos 0 /*!< GPIO_PORT B95: PBYTE Position */
+#define GPIO_PORT_B95_PBYTE_Msk (0x01UL << GPIO_PORT_B95_PBYTE_Pos) /*!< GPIO_PORT B95: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B96 -----------------------------------------
+#define GPIO_PORT_B96_PBYTE_Pos 0 /*!< GPIO_PORT B96: PBYTE Position */
+#define GPIO_PORT_B96_PBYTE_Msk (0x01UL << GPIO_PORT_B96_PBYTE_Pos) /*!< GPIO_PORT B96: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B97 -----------------------------------------
+#define GPIO_PORT_B97_PBYTE_Pos 0 /*!< GPIO_PORT B97: PBYTE Position */
+#define GPIO_PORT_B97_PBYTE_Msk (0x01UL << GPIO_PORT_B97_PBYTE_Pos) /*!< GPIO_PORT B97: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B98 -----------------------------------------
+#define GPIO_PORT_B98_PBYTE_Pos 0 /*!< GPIO_PORT B98: PBYTE Position */
+#define GPIO_PORT_B98_PBYTE_Msk (0x01UL << GPIO_PORT_B98_PBYTE_Pos) /*!< GPIO_PORT B98: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_B99 -----------------------------------------
+#define GPIO_PORT_B99_PBYTE_Pos 0 /*!< GPIO_PORT B99: PBYTE Position */
+#define GPIO_PORT_B99_PBYTE_Msk (0x01UL << GPIO_PORT_B99_PBYTE_Pos) /*!< GPIO_PORT B99: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B100 -----------------------------------------
+#define GPIO_PORT_B100_PBYTE_Pos 0 /*!< GPIO_PORT B100: PBYTE Position */
+#define GPIO_PORT_B100_PBYTE_Msk (0x01UL << GPIO_PORT_B100_PBYTE_Pos) /*!< GPIO_PORT B100: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B101 -----------------------------------------
+#define GPIO_PORT_B101_PBYTE_Pos 0 /*!< GPIO_PORT B101: PBYTE Position */
+#define GPIO_PORT_B101_PBYTE_Msk (0x01UL << GPIO_PORT_B101_PBYTE_Pos) /*!< GPIO_PORT B101: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B102 -----------------------------------------
+#define GPIO_PORT_B102_PBYTE_Pos 0 /*!< GPIO_PORT B102: PBYTE Position */
+#define GPIO_PORT_B102_PBYTE_Msk (0x01UL << GPIO_PORT_B102_PBYTE_Pos) /*!< GPIO_PORT B102: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B103 -----------------------------------------
+#define GPIO_PORT_B103_PBYTE_Pos 0 /*!< GPIO_PORT B103: PBYTE Position */
+#define GPIO_PORT_B103_PBYTE_Msk (0x01UL << GPIO_PORT_B103_PBYTE_Pos) /*!< GPIO_PORT B103: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B104 -----------------------------------------
+#define GPIO_PORT_B104_PBYTE_Pos 0 /*!< GPIO_PORT B104: PBYTE Position */
+#define GPIO_PORT_B104_PBYTE_Msk (0x01UL << GPIO_PORT_B104_PBYTE_Pos) /*!< GPIO_PORT B104: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B105 -----------------------------------------
+#define GPIO_PORT_B105_PBYTE_Pos 0 /*!< GPIO_PORT B105: PBYTE Position */
+#define GPIO_PORT_B105_PBYTE_Msk (0x01UL << GPIO_PORT_B105_PBYTE_Pos) /*!< GPIO_PORT B105: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B106 -----------------------------------------
+#define GPIO_PORT_B106_PBYTE_Pos 0 /*!< GPIO_PORT B106: PBYTE Position */
+#define GPIO_PORT_B106_PBYTE_Msk (0x01UL << GPIO_PORT_B106_PBYTE_Pos) /*!< GPIO_PORT B106: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B107 -----------------------------------------
+#define GPIO_PORT_B107_PBYTE_Pos 0 /*!< GPIO_PORT B107: PBYTE Position */
+#define GPIO_PORT_B107_PBYTE_Msk (0x01UL << GPIO_PORT_B107_PBYTE_Pos) /*!< GPIO_PORT B107: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B108 -----------------------------------------
+#define GPIO_PORT_B108_PBYTE_Pos 0 /*!< GPIO_PORT B108: PBYTE Position */
+#define GPIO_PORT_B108_PBYTE_Msk (0x01UL << GPIO_PORT_B108_PBYTE_Pos) /*!< GPIO_PORT B108: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B109 -----------------------------------------
+#define GPIO_PORT_B109_PBYTE_Pos 0 /*!< GPIO_PORT B109: PBYTE Position */
+#define GPIO_PORT_B109_PBYTE_Msk (0x01UL << GPIO_PORT_B109_PBYTE_Pos) /*!< GPIO_PORT B109: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B110 -----------------------------------------
+#define GPIO_PORT_B110_PBYTE_Pos 0 /*!< GPIO_PORT B110: PBYTE Position */
+#define GPIO_PORT_B110_PBYTE_Msk (0x01UL << GPIO_PORT_B110_PBYTE_Pos) /*!< GPIO_PORT B110: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B111 -----------------------------------------
+#define GPIO_PORT_B111_PBYTE_Pos 0 /*!< GPIO_PORT B111: PBYTE Position */
+#define GPIO_PORT_B111_PBYTE_Msk (0x01UL << GPIO_PORT_B111_PBYTE_Pos) /*!< GPIO_PORT B111: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B112 -----------------------------------------
+#define GPIO_PORT_B112_PBYTE_Pos 0 /*!< GPIO_PORT B112: PBYTE Position */
+#define GPIO_PORT_B112_PBYTE_Msk (0x01UL << GPIO_PORT_B112_PBYTE_Pos) /*!< GPIO_PORT B112: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B113 -----------------------------------------
+#define GPIO_PORT_B113_PBYTE_Pos 0 /*!< GPIO_PORT B113: PBYTE Position */
+#define GPIO_PORT_B113_PBYTE_Msk (0x01UL << GPIO_PORT_B113_PBYTE_Pos) /*!< GPIO_PORT B113: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B114 -----------------------------------------
+#define GPIO_PORT_B114_PBYTE_Pos 0 /*!< GPIO_PORT B114: PBYTE Position */
+#define GPIO_PORT_B114_PBYTE_Msk (0x01UL << GPIO_PORT_B114_PBYTE_Pos) /*!< GPIO_PORT B114: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B115 -----------------------------------------
+#define GPIO_PORT_B115_PBYTE_Pos 0 /*!< GPIO_PORT B115: PBYTE Position */
+#define GPIO_PORT_B115_PBYTE_Msk (0x01UL << GPIO_PORT_B115_PBYTE_Pos) /*!< GPIO_PORT B115: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B116 -----------------------------------------
+#define GPIO_PORT_B116_PBYTE_Pos 0 /*!< GPIO_PORT B116: PBYTE Position */
+#define GPIO_PORT_B116_PBYTE_Msk (0x01UL << GPIO_PORT_B116_PBYTE_Pos) /*!< GPIO_PORT B116: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B117 -----------------------------------------
+#define GPIO_PORT_B117_PBYTE_Pos 0 /*!< GPIO_PORT B117: PBYTE Position */
+#define GPIO_PORT_B117_PBYTE_Msk (0x01UL << GPIO_PORT_B117_PBYTE_Pos) /*!< GPIO_PORT B117: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B118 -----------------------------------------
+#define GPIO_PORT_B118_PBYTE_Pos 0 /*!< GPIO_PORT B118: PBYTE Position */
+#define GPIO_PORT_B118_PBYTE_Msk (0x01UL << GPIO_PORT_B118_PBYTE_Pos) /*!< GPIO_PORT B118: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B119 -----------------------------------------
+#define GPIO_PORT_B119_PBYTE_Pos 0 /*!< GPIO_PORT B119: PBYTE Position */
+#define GPIO_PORT_B119_PBYTE_Msk (0x01UL << GPIO_PORT_B119_PBYTE_Pos) /*!< GPIO_PORT B119: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B120 -----------------------------------------
+#define GPIO_PORT_B120_PBYTE_Pos 0 /*!< GPIO_PORT B120: PBYTE Position */
+#define GPIO_PORT_B120_PBYTE_Msk (0x01UL << GPIO_PORT_B120_PBYTE_Pos) /*!< GPIO_PORT B120: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B121 -----------------------------------------
+#define GPIO_PORT_B121_PBYTE_Pos 0 /*!< GPIO_PORT B121: PBYTE Position */
+#define GPIO_PORT_B121_PBYTE_Msk (0x01UL << GPIO_PORT_B121_PBYTE_Pos) /*!< GPIO_PORT B121: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B122 -----------------------------------------
+#define GPIO_PORT_B122_PBYTE_Pos 0 /*!< GPIO_PORT B122: PBYTE Position */
+#define GPIO_PORT_B122_PBYTE_Msk (0x01UL << GPIO_PORT_B122_PBYTE_Pos) /*!< GPIO_PORT B122: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B123 -----------------------------------------
+#define GPIO_PORT_B123_PBYTE_Pos 0 /*!< GPIO_PORT B123: PBYTE Position */
+#define GPIO_PORT_B123_PBYTE_Msk (0x01UL << GPIO_PORT_B123_PBYTE_Pos) /*!< GPIO_PORT B123: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B124 -----------------------------------------
+#define GPIO_PORT_B124_PBYTE_Pos 0 /*!< GPIO_PORT B124: PBYTE Position */
+#define GPIO_PORT_B124_PBYTE_Msk (0x01UL << GPIO_PORT_B124_PBYTE_Pos) /*!< GPIO_PORT B124: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B125 -----------------------------------------
+#define GPIO_PORT_B125_PBYTE_Pos 0 /*!< GPIO_PORT B125: PBYTE Position */
+#define GPIO_PORT_B125_PBYTE_Msk (0x01UL << GPIO_PORT_B125_PBYTE_Pos) /*!< GPIO_PORT B125: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B126 -----------------------------------------
+#define GPIO_PORT_B126_PBYTE_Pos 0 /*!< GPIO_PORT B126: PBYTE Position */
+#define GPIO_PORT_B126_PBYTE_Msk (0x01UL << GPIO_PORT_B126_PBYTE_Pos) /*!< GPIO_PORT B126: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B127 -----------------------------------------
+#define GPIO_PORT_B127_PBYTE_Pos 0 /*!< GPIO_PORT B127: PBYTE Position */
+#define GPIO_PORT_B127_PBYTE_Msk (0x01UL << GPIO_PORT_B127_PBYTE_Pos) /*!< GPIO_PORT B127: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B128 -----------------------------------------
+#define GPIO_PORT_B128_PBYTE_Pos 0 /*!< GPIO_PORT B128: PBYTE Position */
+#define GPIO_PORT_B128_PBYTE_Msk (0x01UL << GPIO_PORT_B128_PBYTE_Pos) /*!< GPIO_PORT B128: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B129 -----------------------------------------
+#define GPIO_PORT_B129_PBYTE_Pos 0 /*!< GPIO_PORT B129: PBYTE Position */
+#define GPIO_PORT_B129_PBYTE_Msk (0x01UL << GPIO_PORT_B129_PBYTE_Pos) /*!< GPIO_PORT B129: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B130 -----------------------------------------
+#define GPIO_PORT_B130_PBYTE_Pos 0 /*!< GPIO_PORT B130: PBYTE Position */
+#define GPIO_PORT_B130_PBYTE_Msk (0x01UL << GPIO_PORT_B130_PBYTE_Pos) /*!< GPIO_PORT B130: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B131 -----------------------------------------
+#define GPIO_PORT_B131_PBYTE_Pos 0 /*!< GPIO_PORT B131: PBYTE Position */
+#define GPIO_PORT_B131_PBYTE_Msk (0x01UL << GPIO_PORT_B131_PBYTE_Pos) /*!< GPIO_PORT B131: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B132 -----------------------------------------
+#define GPIO_PORT_B132_PBYTE_Pos 0 /*!< GPIO_PORT B132: PBYTE Position */
+#define GPIO_PORT_B132_PBYTE_Msk (0x01UL << GPIO_PORT_B132_PBYTE_Pos) /*!< GPIO_PORT B132: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B133 -----------------------------------------
+#define GPIO_PORT_B133_PBYTE_Pos 0 /*!< GPIO_PORT B133: PBYTE Position */
+#define GPIO_PORT_B133_PBYTE_Msk (0x01UL << GPIO_PORT_B133_PBYTE_Pos) /*!< GPIO_PORT B133: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B134 -----------------------------------------
+#define GPIO_PORT_B134_PBYTE_Pos 0 /*!< GPIO_PORT B134: PBYTE Position */
+#define GPIO_PORT_B134_PBYTE_Msk (0x01UL << GPIO_PORT_B134_PBYTE_Pos) /*!< GPIO_PORT B134: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B135 -----------------------------------------
+#define GPIO_PORT_B135_PBYTE_Pos 0 /*!< GPIO_PORT B135: PBYTE Position */
+#define GPIO_PORT_B135_PBYTE_Msk (0x01UL << GPIO_PORT_B135_PBYTE_Pos) /*!< GPIO_PORT B135: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B136 -----------------------------------------
+#define GPIO_PORT_B136_PBYTE_Pos 0 /*!< GPIO_PORT B136: PBYTE Position */
+#define GPIO_PORT_B136_PBYTE_Msk (0x01UL << GPIO_PORT_B136_PBYTE_Pos) /*!< GPIO_PORT B136: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B137 -----------------------------------------
+#define GPIO_PORT_B137_PBYTE_Pos 0 /*!< GPIO_PORT B137: PBYTE Position */
+#define GPIO_PORT_B137_PBYTE_Msk (0x01UL << GPIO_PORT_B137_PBYTE_Pos) /*!< GPIO_PORT B137: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B138 -----------------------------------------
+#define GPIO_PORT_B138_PBYTE_Pos 0 /*!< GPIO_PORT B138: PBYTE Position */
+#define GPIO_PORT_B138_PBYTE_Msk (0x01UL << GPIO_PORT_B138_PBYTE_Pos) /*!< GPIO_PORT B138: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B139 -----------------------------------------
+#define GPIO_PORT_B139_PBYTE_Pos 0 /*!< GPIO_PORT B139: PBYTE Position */
+#define GPIO_PORT_B139_PBYTE_Msk (0x01UL << GPIO_PORT_B139_PBYTE_Pos) /*!< GPIO_PORT B139: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B140 -----------------------------------------
+#define GPIO_PORT_B140_PBYTE_Pos 0 /*!< GPIO_PORT B140: PBYTE Position */
+#define GPIO_PORT_B140_PBYTE_Msk (0x01UL << GPIO_PORT_B140_PBYTE_Pos) /*!< GPIO_PORT B140: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B141 -----------------------------------------
+#define GPIO_PORT_B141_PBYTE_Pos 0 /*!< GPIO_PORT B141: PBYTE Position */
+#define GPIO_PORT_B141_PBYTE_Msk (0x01UL << GPIO_PORT_B141_PBYTE_Pos) /*!< GPIO_PORT B141: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B142 -----------------------------------------
+#define GPIO_PORT_B142_PBYTE_Pos 0 /*!< GPIO_PORT B142: PBYTE Position */
+#define GPIO_PORT_B142_PBYTE_Msk (0x01UL << GPIO_PORT_B142_PBYTE_Pos) /*!< GPIO_PORT B142: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B143 -----------------------------------------
+#define GPIO_PORT_B143_PBYTE_Pos 0 /*!< GPIO_PORT B143: PBYTE Position */
+#define GPIO_PORT_B143_PBYTE_Msk (0x01UL << GPIO_PORT_B143_PBYTE_Pos) /*!< GPIO_PORT B143: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B144 -----------------------------------------
+#define GPIO_PORT_B144_PBYTE_Pos 0 /*!< GPIO_PORT B144: PBYTE Position */
+#define GPIO_PORT_B144_PBYTE_Msk (0x01UL << GPIO_PORT_B144_PBYTE_Pos) /*!< GPIO_PORT B144: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B145 -----------------------------------------
+#define GPIO_PORT_B145_PBYTE_Pos 0 /*!< GPIO_PORT B145: PBYTE Position */
+#define GPIO_PORT_B145_PBYTE_Msk (0x01UL << GPIO_PORT_B145_PBYTE_Pos) /*!< GPIO_PORT B145: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B146 -----------------------------------------
+#define GPIO_PORT_B146_PBYTE_Pos 0 /*!< GPIO_PORT B146: PBYTE Position */
+#define GPIO_PORT_B146_PBYTE_Msk (0x01UL << GPIO_PORT_B146_PBYTE_Pos) /*!< GPIO_PORT B146: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B147 -----------------------------------------
+#define GPIO_PORT_B147_PBYTE_Pos 0 /*!< GPIO_PORT B147: PBYTE Position */
+#define GPIO_PORT_B147_PBYTE_Msk (0x01UL << GPIO_PORT_B147_PBYTE_Pos) /*!< GPIO_PORT B147: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B148 -----------------------------------------
+#define GPIO_PORT_B148_PBYTE_Pos 0 /*!< GPIO_PORT B148: PBYTE Position */
+#define GPIO_PORT_B148_PBYTE_Msk (0x01UL << GPIO_PORT_B148_PBYTE_Pos) /*!< GPIO_PORT B148: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B149 -----------------------------------------
+#define GPIO_PORT_B149_PBYTE_Pos 0 /*!< GPIO_PORT B149: PBYTE Position */
+#define GPIO_PORT_B149_PBYTE_Msk (0x01UL << GPIO_PORT_B149_PBYTE_Pos) /*!< GPIO_PORT B149: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B150 -----------------------------------------
+#define GPIO_PORT_B150_PBYTE_Pos 0 /*!< GPIO_PORT B150: PBYTE Position */
+#define GPIO_PORT_B150_PBYTE_Msk (0x01UL << GPIO_PORT_B150_PBYTE_Pos) /*!< GPIO_PORT B150: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B151 -----------------------------------------
+#define GPIO_PORT_B151_PBYTE_Pos 0 /*!< GPIO_PORT B151: PBYTE Position */
+#define GPIO_PORT_B151_PBYTE_Msk (0x01UL << GPIO_PORT_B151_PBYTE_Pos) /*!< GPIO_PORT B151: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B152 -----------------------------------------
+#define GPIO_PORT_B152_PBYTE_Pos 0 /*!< GPIO_PORT B152: PBYTE Position */
+#define GPIO_PORT_B152_PBYTE_Msk (0x01UL << GPIO_PORT_B152_PBYTE_Pos) /*!< GPIO_PORT B152: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B153 -----------------------------------------
+#define GPIO_PORT_B153_PBYTE_Pos 0 /*!< GPIO_PORT B153: PBYTE Position */
+#define GPIO_PORT_B153_PBYTE_Msk (0x01UL << GPIO_PORT_B153_PBYTE_Pos) /*!< GPIO_PORT B153: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B154 -----------------------------------------
+#define GPIO_PORT_B154_PBYTE_Pos 0 /*!< GPIO_PORT B154: PBYTE Position */
+#define GPIO_PORT_B154_PBYTE_Msk (0x01UL << GPIO_PORT_B154_PBYTE_Pos) /*!< GPIO_PORT B154: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B155 -----------------------------------------
+#define GPIO_PORT_B155_PBYTE_Pos 0 /*!< GPIO_PORT B155: PBYTE Position */
+#define GPIO_PORT_B155_PBYTE_Msk (0x01UL << GPIO_PORT_B155_PBYTE_Pos) /*!< GPIO_PORT B155: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B156 -----------------------------------------
+#define GPIO_PORT_B156_PBYTE_Pos 0 /*!< GPIO_PORT B156: PBYTE Position */
+#define GPIO_PORT_B156_PBYTE_Msk (0x01UL << GPIO_PORT_B156_PBYTE_Pos) /*!< GPIO_PORT B156: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B157 -----------------------------------------
+#define GPIO_PORT_B157_PBYTE_Pos 0 /*!< GPIO_PORT B157: PBYTE Position */
+#define GPIO_PORT_B157_PBYTE_Msk (0x01UL << GPIO_PORT_B157_PBYTE_Pos) /*!< GPIO_PORT B157: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B158 -----------------------------------------
+#define GPIO_PORT_B158_PBYTE_Pos 0 /*!< GPIO_PORT B158: PBYTE Position */
+#define GPIO_PORT_B158_PBYTE_Msk (0x01UL << GPIO_PORT_B158_PBYTE_Pos) /*!< GPIO_PORT B158: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B159 -----------------------------------------
+#define GPIO_PORT_B159_PBYTE_Pos 0 /*!< GPIO_PORT B159: PBYTE Position */
+#define GPIO_PORT_B159_PBYTE_Msk (0x01UL << GPIO_PORT_B159_PBYTE_Pos) /*!< GPIO_PORT B159: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B160 -----------------------------------------
+#define GPIO_PORT_B160_PBYTE_Pos 0 /*!< GPIO_PORT B160: PBYTE Position */
+#define GPIO_PORT_B160_PBYTE_Msk (0x01UL << GPIO_PORT_B160_PBYTE_Pos) /*!< GPIO_PORT B160: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B161 -----------------------------------------
+#define GPIO_PORT_B161_PBYTE_Pos 0 /*!< GPIO_PORT B161: PBYTE Position */
+#define GPIO_PORT_B161_PBYTE_Msk (0x01UL << GPIO_PORT_B161_PBYTE_Pos) /*!< GPIO_PORT B161: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B162 -----------------------------------------
+#define GPIO_PORT_B162_PBYTE_Pos 0 /*!< GPIO_PORT B162: PBYTE Position */
+#define GPIO_PORT_B162_PBYTE_Msk (0x01UL << GPIO_PORT_B162_PBYTE_Pos) /*!< GPIO_PORT B162: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B163 -----------------------------------------
+#define GPIO_PORT_B163_PBYTE_Pos 0 /*!< GPIO_PORT B163: PBYTE Position */
+#define GPIO_PORT_B163_PBYTE_Msk (0x01UL << GPIO_PORT_B163_PBYTE_Pos) /*!< GPIO_PORT B163: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B164 -----------------------------------------
+#define GPIO_PORT_B164_PBYTE_Pos 0 /*!< GPIO_PORT B164: PBYTE Position */
+#define GPIO_PORT_B164_PBYTE_Msk (0x01UL << GPIO_PORT_B164_PBYTE_Pos) /*!< GPIO_PORT B164: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B165 -----------------------------------------
+#define GPIO_PORT_B165_PBYTE_Pos 0 /*!< GPIO_PORT B165: PBYTE Position */
+#define GPIO_PORT_B165_PBYTE_Msk (0x01UL << GPIO_PORT_B165_PBYTE_Pos) /*!< GPIO_PORT B165: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B166 -----------------------------------------
+#define GPIO_PORT_B166_PBYTE_Pos 0 /*!< GPIO_PORT B166: PBYTE Position */
+#define GPIO_PORT_B166_PBYTE_Msk (0x01UL << GPIO_PORT_B166_PBYTE_Pos) /*!< GPIO_PORT B166: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B167 -----------------------------------------
+#define GPIO_PORT_B167_PBYTE_Pos 0 /*!< GPIO_PORT B167: PBYTE Position */
+#define GPIO_PORT_B167_PBYTE_Msk (0x01UL << GPIO_PORT_B167_PBYTE_Pos) /*!< GPIO_PORT B167: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B168 -----------------------------------------
+#define GPIO_PORT_B168_PBYTE_Pos 0 /*!< GPIO_PORT B168: PBYTE Position */
+#define GPIO_PORT_B168_PBYTE_Msk (0x01UL << GPIO_PORT_B168_PBYTE_Pos) /*!< GPIO_PORT B168: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B169 -----------------------------------------
+#define GPIO_PORT_B169_PBYTE_Pos 0 /*!< GPIO_PORT B169: PBYTE Position */
+#define GPIO_PORT_B169_PBYTE_Msk (0x01UL << GPIO_PORT_B169_PBYTE_Pos) /*!< GPIO_PORT B169: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B170 -----------------------------------------
+#define GPIO_PORT_B170_PBYTE_Pos 0 /*!< GPIO_PORT B170: PBYTE Position */
+#define GPIO_PORT_B170_PBYTE_Msk (0x01UL << GPIO_PORT_B170_PBYTE_Pos) /*!< GPIO_PORT B170: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B171 -----------------------------------------
+#define GPIO_PORT_B171_PBYTE_Pos 0 /*!< GPIO_PORT B171: PBYTE Position */
+#define GPIO_PORT_B171_PBYTE_Msk (0x01UL << GPIO_PORT_B171_PBYTE_Pos) /*!< GPIO_PORT B171: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B172 -----------------------------------------
+#define GPIO_PORT_B172_PBYTE_Pos 0 /*!< GPIO_PORT B172: PBYTE Position */
+#define GPIO_PORT_B172_PBYTE_Msk (0x01UL << GPIO_PORT_B172_PBYTE_Pos) /*!< GPIO_PORT B172: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B173 -----------------------------------------
+#define GPIO_PORT_B173_PBYTE_Pos 0 /*!< GPIO_PORT B173: PBYTE Position */
+#define GPIO_PORT_B173_PBYTE_Msk (0x01UL << GPIO_PORT_B173_PBYTE_Pos) /*!< GPIO_PORT B173: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B174 -----------------------------------------
+#define GPIO_PORT_B174_PBYTE_Pos 0 /*!< GPIO_PORT B174: PBYTE Position */
+#define GPIO_PORT_B174_PBYTE_Msk (0x01UL << GPIO_PORT_B174_PBYTE_Pos) /*!< GPIO_PORT B174: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B175 -----------------------------------------
+#define GPIO_PORT_B175_PBYTE_Pos 0 /*!< GPIO_PORT B175: PBYTE Position */
+#define GPIO_PORT_B175_PBYTE_Msk (0x01UL << GPIO_PORT_B175_PBYTE_Pos) /*!< GPIO_PORT B175: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B176 -----------------------------------------
+#define GPIO_PORT_B176_PBYTE_Pos 0 /*!< GPIO_PORT B176: PBYTE Position */
+#define GPIO_PORT_B176_PBYTE_Msk (0x01UL << GPIO_PORT_B176_PBYTE_Pos) /*!< GPIO_PORT B176: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B177 -----------------------------------------
+#define GPIO_PORT_B177_PBYTE_Pos 0 /*!< GPIO_PORT B177: PBYTE Position */
+#define GPIO_PORT_B177_PBYTE_Msk (0x01UL << GPIO_PORT_B177_PBYTE_Pos) /*!< GPIO_PORT B177: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B178 -----------------------------------------
+#define GPIO_PORT_B178_PBYTE_Pos 0 /*!< GPIO_PORT B178: PBYTE Position */
+#define GPIO_PORT_B178_PBYTE_Msk (0x01UL << GPIO_PORT_B178_PBYTE_Pos) /*!< GPIO_PORT B178: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B179 -----------------------------------------
+#define GPIO_PORT_B179_PBYTE_Pos 0 /*!< GPIO_PORT B179: PBYTE Position */
+#define GPIO_PORT_B179_PBYTE_Msk (0x01UL << GPIO_PORT_B179_PBYTE_Pos) /*!< GPIO_PORT B179: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B180 -----------------------------------------
+#define GPIO_PORT_B180_PBYTE_Pos 0 /*!< GPIO_PORT B180: PBYTE Position */
+#define GPIO_PORT_B180_PBYTE_Msk (0x01UL << GPIO_PORT_B180_PBYTE_Pos) /*!< GPIO_PORT B180: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B181 -----------------------------------------
+#define GPIO_PORT_B181_PBYTE_Pos 0 /*!< GPIO_PORT B181: PBYTE Position */
+#define GPIO_PORT_B181_PBYTE_Msk (0x01UL << GPIO_PORT_B181_PBYTE_Pos) /*!< GPIO_PORT B181: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B182 -----------------------------------------
+#define GPIO_PORT_B182_PBYTE_Pos 0 /*!< GPIO_PORT B182: PBYTE Position */
+#define GPIO_PORT_B182_PBYTE_Msk (0x01UL << GPIO_PORT_B182_PBYTE_Pos) /*!< GPIO_PORT B182: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B183 -----------------------------------------
+#define GPIO_PORT_B183_PBYTE_Pos 0 /*!< GPIO_PORT B183: PBYTE Position */
+#define GPIO_PORT_B183_PBYTE_Msk (0x01UL << GPIO_PORT_B183_PBYTE_Pos) /*!< GPIO_PORT B183: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B184 -----------------------------------------
+#define GPIO_PORT_B184_PBYTE_Pos 0 /*!< GPIO_PORT B184: PBYTE Position */
+#define GPIO_PORT_B184_PBYTE_Msk (0x01UL << GPIO_PORT_B184_PBYTE_Pos) /*!< GPIO_PORT B184: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B185 -----------------------------------------
+#define GPIO_PORT_B185_PBYTE_Pos 0 /*!< GPIO_PORT B185: PBYTE Position */
+#define GPIO_PORT_B185_PBYTE_Msk (0x01UL << GPIO_PORT_B185_PBYTE_Pos) /*!< GPIO_PORT B185: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B186 -----------------------------------------
+#define GPIO_PORT_B186_PBYTE_Pos 0 /*!< GPIO_PORT B186: PBYTE Position */
+#define GPIO_PORT_B186_PBYTE_Msk (0x01UL << GPIO_PORT_B186_PBYTE_Pos) /*!< GPIO_PORT B186: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B187 -----------------------------------------
+#define GPIO_PORT_B187_PBYTE_Pos 0 /*!< GPIO_PORT B187: PBYTE Position */
+#define GPIO_PORT_B187_PBYTE_Msk (0x01UL << GPIO_PORT_B187_PBYTE_Pos) /*!< GPIO_PORT B187: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B188 -----------------------------------------
+#define GPIO_PORT_B188_PBYTE_Pos 0 /*!< GPIO_PORT B188: PBYTE Position */
+#define GPIO_PORT_B188_PBYTE_Msk (0x01UL << GPIO_PORT_B188_PBYTE_Pos) /*!< GPIO_PORT B188: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B189 -----------------------------------------
+#define GPIO_PORT_B189_PBYTE_Pos 0 /*!< GPIO_PORT B189: PBYTE Position */
+#define GPIO_PORT_B189_PBYTE_Msk (0x01UL << GPIO_PORT_B189_PBYTE_Pos) /*!< GPIO_PORT B189: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B190 -----------------------------------------
+#define GPIO_PORT_B190_PBYTE_Pos 0 /*!< GPIO_PORT B190: PBYTE Position */
+#define GPIO_PORT_B190_PBYTE_Msk (0x01UL << GPIO_PORT_B190_PBYTE_Pos) /*!< GPIO_PORT B190: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B191 -----------------------------------------
+#define GPIO_PORT_B191_PBYTE_Pos 0 /*!< GPIO_PORT B191: PBYTE Position */
+#define GPIO_PORT_B191_PBYTE_Msk (0x01UL << GPIO_PORT_B191_PBYTE_Pos) /*!< GPIO_PORT B191: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B192 -----------------------------------------
+#define GPIO_PORT_B192_PBYTE_Pos 0 /*!< GPIO_PORT B192: PBYTE Position */
+#define GPIO_PORT_B192_PBYTE_Msk (0x01UL << GPIO_PORT_B192_PBYTE_Pos) /*!< GPIO_PORT B192: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B193 -----------------------------------------
+#define GPIO_PORT_B193_PBYTE_Pos 0 /*!< GPIO_PORT B193: PBYTE Position */
+#define GPIO_PORT_B193_PBYTE_Msk (0x01UL << GPIO_PORT_B193_PBYTE_Pos) /*!< GPIO_PORT B193: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B194 -----------------------------------------
+#define GPIO_PORT_B194_PBYTE_Pos 0 /*!< GPIO_PORT B194: PBYTE Position */
+#define GPIO_PORT_B194_PBYTE_Msk (0x01UL << GPIO_PORT_B194_PBYTE_Pos) /*!< GPIO_PORT B194: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B195 -----------------------------------------
+#define GPIO_PORT_B195_PBYTE_Pos 0 /*!< GPIO_PORT B195: PBYTE Position */
+#define GPIO_PORT_B195_PBYTE_Msk (0x01UL << GPIO_PORT_B195_PBYTE_Pos) /*!< GPIO_PORT B195: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B196 -----------------------------------------
+#define GPIO_PORT_B196_PBYTE_Pos 0 /*!< GPIO_PORT B196: PBYTE Position */
+#define GPIO_PORT_B196_PBYTE_Msk (0x01UL << GPIO_PORT_B196_PBYTE_Pos) /*!< GPIO_PORT B196: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B197 -----------------------------------------
+#define GPIO_PORT_B197_PBYTE_Pos 0 /*!< GPIO_PORT B197: PBYTE Position */
+#define GPIO_PORT_B197_PBYTE_Msk (0x01UL << GPIO_PORT_B197_PBYTE_Pos) /*!< GPIO_PORT B197: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B198 -----------------------------------------
+#define GPIO_PORT_B198_PBYTE_Pos 0 /*!< GPIO_PORT B198: PBYTE Position */
+#define GPIO_PORT_B198_PBYTE_Msk (0x01UL << GPIO_PORT_B198_PBYTE_Pos) /*!< GPIO_PORT B198: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B199 -----------------------------------------
+#define GPIO_PORT_B199_PBYTE_Pos 0 /*!< GPIO_PORT B199: PBYTE Position */
+#define GPIO_PORT_B199_PBYTE_Msk (0x01UL << GPIO_PORT_B199_PBYTE_Pos) /*!< GPIO_PORT B199: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B200 -----------------------------------------
+#define GPIO_PORT_B200_PBYTE_Pos 0 /*!< GPIO_PORT B200: PBYTE Position */
+#define GPIO_PORT_B200_PBYTE_Msk (0x01UL << GPIO_PORT_B200_PBYTE_Pos) /*!< GPIO_PORT B200: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B201 -----------------------------------------
+#define GPIO_PORT_B201_PBYTE_Pos 0 /*!< GPIO_PORT B201: PBYTE Position */
+#define GPIO_PORT_B201_PBYTE_Msk (0x01UL << GPIO_PORT_B201_PBYTE_Pos) /*!< GPIO_PORT B201: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B202 -----------------------------------------
+#define GPIO_PORT_B202_PBYTE_Pos 0 /*!< GPIO_PORT B202: PBYTE Position */
+#define GPIO_PORT_B202_PBYTE_Msk (0x01UL << GPIO_PORT_B202_PBYTE_Pos) /*!< GPIO_PORT B202: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B203 -----------------------------------------
+#define GPIO_PORT_B203_PBYTE_Pos 0 /*!< GPIO_PORT B203: PBYTE Position */
+#define GPIO_PORT_B203_PBYTE_Msk (0x01UL << GPIO_PORT_B203_PBYTE_Pos) /*!< GPIO_PORT B203: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B204 -----------------------------------------
+#define GPIO_PORT_B204_PBYTE_Pos 0 /*!< GPIO_PORT B204: PBYTE Position */
+#define GPIO_PORT_B204_PBYTE_Msk (0x01UL << GPIO_PORT_B204_PBYTE_Pos) /*!< GPIO_PORT B204: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B205 -----------------------------------------
+#define GPIO_PORT_B205_PBYTE_Pos 0 /*!< GPIO_PORT B205: PBYTE Position */
+#define GPIO_PORT_B205_PBYTE_Msk (0x01UL << GPIO_PORT_B205_PBYTE_Pos) /*!< GPIO_PORT B205: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B206 -----------------------------------------
+#define GPIO_PORT_B206_PBYTE_Pos 0 /*!< GPIO_PORT B206: PBYTE Position */
+#define GPIO_PORT_B206_PBYTE_Msk (0x01UL << GPIO_PORT_B206_PBYTE_Pos) /*!< GPIO_PORT B206: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B207 -----------------------------------------
+#define GPIO_PORT_B207_PBYTE_Pos 0 /*!< GPIO_PORT B207: PBYTE Position */
+#define GPIO_PORT_B207_PBYTE_Msk (0x01UL << GPIO_PORT_B207_PBYTE_Pos) /*!< GPIO_PORT B207: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B208 -----------------------------------------
+#define GPIO_PORT_B208_PBYTE_Pos 0 /*!< GPIO_PORT B208: PBYTE Position */
+#define GPIO_PORT_B208_PBYTE_Msk (0x01UL << GPIO_PORT_B208_PBYTE_Pos) /*!< GPIO_PORT B208: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B209 -----------------------------------------
+#define GPIO_PORT_B209_PBYTE_Pos 0 /*!< GPIO_PORT B209: PBYTE Position */
+#define GPIO_PORT_B209_PBYTE_Msk (0x01UL << GPIO_PORT_B209_PBYTE_Pos) /*!< GPIO_PORT B209: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B210 -----------------------------------------
+#define GPIO_PORT_B210_PBYTE_Pos 0 /*!< GPIO_PORT B210: PBYTE Position */
+#define GPIO_PORT_B210_PBYTE_Msk (0x01UL << GPIO_PORT_B210_PBYTE_Pos) /*!< GPIO_PORT B210: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B211 -----------------------------------------
+#define GPIO_PORT_B211_PBYTE_Pos 0 /*!< GPIO_PORT B211: PBYTE Position */
+#define GPIO_PORT_B211_PBYTE_Msk (0x01UL << GPIO_PORT_B211_PBYTE_Pos) /*!< GPIO_PORT B211: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B212 -----------------------------------------
+#define GPIO_PORT_B212_PBYTE_Pos 0 /*!< GPIO_PORT B212: PBYTE Position */
+#define GPIO_PORT_B212_PBYTE_Msk (0x01UL << GPIO_PORT_B212_PBYTE_Pos) /*!< GPIO_PORT B212: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B213 -----------------------------------------
+#define GPIO_PORT_B213_PBYTE_Pos 0 /*!< GPIO_PORT B213: PBYTE Position */
+#define GPIO_PORT_B213_PBYTE_Msk (0x01UL << GPIO_PORT_B213_PBYTE_Pos) /*!< GPIO_PORT B213: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B214 -----------------------------------------
+#define GPIO_PORT_B214_PBYTE_Pos 0 /*!< GPIO_PORT B214: PBYTE Position */
+#define GPIO_PORT_B214_PBYTE_Msk (0x01UL << GPIO_PORT_B214_PBYTE_Pos) /*!< GPIO_PORT B214: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B215 -----------------------------------------
+#define GPIO_PORT_B215_PBYTE_Pos 0 /*!< GPIO_PORT B215: PBYTE Position */
+#define GPIO_PORT_B215_PBYTE_Msk (0x01UL << GPIO_PORT_B215_PBYTE_Pos) /*!< GPIO_PORT B215: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B216 -----------------------------------------
+#define GPIO_PORT_B216_PBYTE_Pos 0 /*!< GPIO_PORT B216: PBYTE Position */
+#define GPIO_PORT_B216_PBYTE_Msk (0x01UL << GPIO_PORT_B216_PBYTE_Pos) /*!< GPIO_PORT B216: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B217 -----------------------------------------
+#define GPIO_PORT_B217_PBYTE_Pos 0 /*!< GPIO_PORT B217: PBYTE Position */
+#define GPIO_PORT_B217_PBYTE_Msk (0x01UL << GPIO_PORT_B217_PBYTE_Pos) /*!< GPIO_PORT B217: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B218 -----------------------------------------
+#define GPIO_PORT_B218_PBYTE_Pos 0 /*!< GPIO_PORT B218: PBYTE Position */
+#define GPIO_PORT_B218_PBYTE_Msk (0x01UL << GPIO_PORT_B218_PBYTE_Pos) /*!< GPIO_PORT B218: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B219 -----------------------------------------
+#define GPIO_PORT_B219_PBYTE_Pos 0 /*!< GPIO_PORT B219: PBYTE Position */
+#define GPIO_PORT_B219_PBYTE_Msk (0x01UL << GPIO_PORT_B219_PBYTE_Pos) /*!< GPIO_PORT B219: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B220 -----------------------------------------
+#define GPIO_PORT_B220_PBYTE_Pos 0 /*!< GPIO_PORT B220: PBYTE Position */
+#define GPIO_PORT_B220_PBYTE_Msk (0x01UL << GPIO_PORT_B220_PBYTE_Pos) /*!< GPIO_PORT B220: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B221 -----------------------------------------
+#define GPIO_PORT_B221_PBYTE_Pos 0 /*!< GPIO_PORT B221: PBYTE Position */
+#define GPIO_PORT_B221_PBYTE_Msk (0x01UL << GPIO_PORT_B221_PBYTE_Pos) /*!< GPIO_PORT B221: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B222 -----------------------------------------
+#define GPIO_PORT_B222_PBYTE_Pos 0 /*!< GPIO_PORT B222: PBYTE Position */
+#define GPIO_PORT_B222_PBYTE_Msk (0x01UL << GPIO_PORT_B222_PBYTE_Pos) /*!< GPIO_PORT B222: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B223 -----------------------------------------
+#define GPIO_PORT_B223_PBYTE_Pos 0 /*!< GPIO_PORT B223: PBYTE Position */
+#define GPIO_PORT_B223_PBYTE_Msk (0x01UL << GPIO_PORT_B223_PBYTE_Pos) /*!< GPIO_PORT B223: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B224 -----------------------------------------
+#define GPIO_PORT_B224_PBYTE_Pos 0 /*!< GPIO_PORT B224: PBYTE Position */
+#define GPIO_PORT_B224_PBYTE_Msk (0x01UL << GPIO_PORT_B224_PBYTE_Pos) /*!< GPIO_PORT B224: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B225 -----------------------------------------
+#define GPIO_PORT_B225_PBYTE_Pos 0 /*!< GPIO_PORT B225: PBYTE Position */
+#define GPIO_PORT_B225_PBYTE_Msk (0x01UL << GPIO_PORT_B225_PBYTE_Pos) /*!< GPIO_PORT B225: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B226 -----------------------------------------
+#define GPIO_PORT_B226_PBYTE_Pos 0 /*!< GPIO_PORT B226: PBYTE Position */
+#define GPIO_PORT_B226_PBYTE_Msk (0x01UL << GPIO_PORT_B226_PBYTE_Pos) /*!< GPIO_PORT B226: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B227 -----------------------------------------
+#define GPIO_PORT_B227_PBYTE_Pos 0 /*!< GPIO_PORT B227: PBYTE Position */
+#define GPIO_PORT_B227_PBYTE_Msk (0x01UL << GPIO_PORT_B227_PBYTE_Pos) /*!< GPIO_PORT B227: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B228 -----------------------------------------
+#define GPIO_PORT_B228_PBYTE_Pos 0 /*!< GPIO_PORT B228: PBYTE Position */
+#define GPIO_PORT_B228_PBYTE_Msk (0x01UL << GPIO_PORT_B228_PBYTE_Pos) /*!< GPIO_PORT B228: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B229 -----------------------------------------
+#define GPIO_PORT_B229_PBYTE_Pos 0 /*!< GPIO_PORT B229: PBYTE Position */
+#define GPIO_PORT_B229_PBYTE_Msk (0x01UL << GPIO_PORT_B229_PBYTE_Pos) /*!< GPIO_PORT B229: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B230 -----------------------------------------
+#define GPIO_PORT_B230_PBYTE_Pos 0 /*!< GPIO_PORT B230: PBYTE Position */
+#define GPIO_PORT_B230_PBYTE_Msk (0x01UL << GPIO_PORT_B230_PBYTE_Pos) /*!< GPIO_PORT B230: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B231 -----------------------------------------
+#define GPIO_PORT_B231_PBYTE_Pos 0 /*!< GPIO_PORT B231: PBYTE Position */
+#define GPIO_PORT_B231_PBYTE_Msk (0x01UL << GPIO_PORT_B231_PBYTE_Pos) /*!< GPIO_PORT B231: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B232 -----------------------------------------
+#define GPIO_PORT_B232_PBYTE_Pos 0 /*!< GPIO_PORT B232: PBYTE Position */
+#define GPIO_PORT_B232_PBYTE_Msk (0x01UL << GPIO_PORT_B232_PBYTE_Pos) /*!< GPIO_PORT B232: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B233 -----------------------------------------
+#define GPIO_PORT_B233_PBYTE_Pos 0 /*!< GPIO_PORT B233: PBYTE Position */
+#define GPIO_PORT_B233_PBYTE_Msk (0x01UL << GPIO_PORT_B233_PBYTE_Pos) /*!< GPIO_PORT B233: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B234 -----------------------------------------
+#define GPIO_PORT_B234_PBYTE_Pos 0 /*!< GPIO_PORT B234: PBYTE Position */
+#define GPIO_PORT_B234_PBYTE_Msk (0x01UL << GPIO_PORT_B234_PBYTE_Pos) /*!< GPIO_PORT B234: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B235 -----------------------------------------
+#define GPIO_PORT_B235_PBYTE_Pos 0 /*!< GPIO_PORT B235: PBYTE Position */
+#define GPIO_PORT_B235_PBYTE_Msk (0x01UL << GPIO_PORT_B235_PBYTE_Pos) /*!< GPIO_PORT B235: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B236 -----------------------------------------
+#define GPIO_PORT_B236_PBYTE_Pos 0 /*!< GPIO_PORT B236: PBYTE Position */
+#define GPIO_PORT_B236_PBYTE_Msk (0x01UL << GPIO_PORT_B236_PBYTE_Pos) /*!< GPIO_PORT B236: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B237 -----------------------------------------
+#define GPIO_PORT_B237_PBYTE_Pos 0 /*!< GPIO_PORT B237: PBYTE Position */
+#define GPIO_PORT_B237_PBYTE_Msk (0x01UL << GPIO_PORT_B237_PBYTE_Pos) /*!< GPIO_PORT B237: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B238 -----------------------------------------
+#define GPIO_PORT_B238_PBYTE_Pos 0 /*!< GPIO_PORT B238: PBYTE Position */
+#define GPIO_PORT_B238_PBYTE_Msk (0x01UL << GPIO_PORT_B238_PBYTE_Pos) /*!< GPIO_PORT B238: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B239 -----------------------------------------
+#define GPIO_PORT_B239_PBYTE_Pos 0 /*!< GPIO_PORT B239: PBYTE Position */
+#define GPIO_PORT_B239_PBYTE_Msk (0x01UL << GPIO_PORT_B239_PBYTE_Pos) /*!< GPIO_PORT B239: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B240 -----------------------------------------
+#define GPIO_PORT_B240_PBYTE_Pos 0 /*!< GPIO_PORT B240: PBYTE Position */
+#define GPIO_PORT_B240_PBYTE_Msk (0x01UL << GPIO_PORT_B240_PBYTE_Pos) /*!< GPIO_PORT B240: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B241 -----------------------------------------
+#define GPIO_PORT_B241_PBYTE_Pos 0 /*!< GPIO_PORT B241: PBYTE Position */
+#define GPIO_PORT_B241_PBYTE_Msk (0x01UL << GPIO_PORT_B241_PBYTE_Pos) /*!< GPIO_PORT B241: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B242 -----------------------------------------
+#define GPIO_PORT_B242_PBYTE_Pos 0 /*!< GPIO_PORT B242: PBYTE Position */
+#define GPIO_PORT_B242_PBYTE_Msk (0x01UL << GPIO_PORT_B242_PBYTE_Pos) /*!< GPIO_PORT B242: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B243 -----------------------------------------
+#define GPIO_PORT_B243_PBYTE_Pos 0 /*!< GPIO_PORT B243: PBYTE Position */
+#define GPIO_PORT_B243_PBYTE_Msk (0x01UL << GPIO_PORT_B243_PBYTE_Pos) /*!< GPIO_PORT B243: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B244 -----------------------------------------
+#define GPIO_PORT_B244_PBYTE_Pos 0 /*!< GPIO_PORT B244: PBYTE Position */
+#define GPIO_PORT_B244_PBYTE_Msk (0x01UL << GPIO_PORT_B244_PBYTE_Pos) /*!< GPIO_PORT B244: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B245 -----------------------------------------
+#define GPIO_PORT_B245_PBYTE_Pos 0 /*!< GPIO_PORT B245: PBYTE Position */
+#define GPIO_PORT_B245_PBYTE_Msk (0x01UL << GPIO_PORT_B245_PBYTE_Pos) /*!< GPIO_PORT B245: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B246 -----------------------------------------
+#define GPIO_PORT_B246_PBYTE_Pos 0 /*!< GPIO_PORT B246: PBYTE Position */
+#define GPIO_PORT_B246_PBYTE_Msk (0x01UL << GPIO_PORT_B246_PBYTE_Pos) /*!< GPIO_PORT B246: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B247 -----------------------------------------
+#define GPIO_PORT_B247_PBYTE_Pos 0 /*!< GPIO_PORT B247: PBYTE Position */
+#define GPIO_PORT_B247_PBYTE_Msk (0x01UL << GPIO_PORT_B247_PBYTE_Pos) /*!< GPIO_PORT B247: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B248 -----------------------------------------
+#define GPIO_PORT_B248_PBYTE_Pos 0 /*!< GPIO_PORT B248: PBYTE Position */
+#define GPIO_PORT_B248_PBYTE_Msk (0x01UL << GPIO_PORT_B248_PBYTE_Pos) /*!< GPIO_PORT B248: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B249 -----------------------------------------
+#define GPIO_PORT_B249_PBYTE_Pos 0 /*!< GPIO_PORT B249: PBYTE Position */
+#define GPIO_PORT_B249_PBYTE_Msk (0x01UL << GPIO_PORT_B249_PBYTE_Pos) /*!< GPIO_PORT B249: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B250 -----------------------------------------
+#define GPIO_PORT_B250_PBYTE_Pos 0 /*!< GPIO_PORT B250: PBYTE Position */
+#define GPIO_PORT_B250_PBYTE_Msk (0x01UL << GPIO_PORT_B250_PBYTE_Pos) /*!< GPIO_PORT B250: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B251 -----------------------------------------
+#define GPIO_PORT_B251_PBYTE_Pos 0 /*!< GPIO_PORT B251: PBYTE Position */
+#define GPIO_PORT_B251_PBYTE_Msk (0x01UL << GPIO_PORT_B251_PBYTE_Pos) /*!< GPIO_PORT B251: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B252 -----------------------------------------
+#define GPIO_PORT_B252_PBYTE_Pos 0 /*!< GPIO_PORT B252: PBYTE Position */
+#define GPIO_PORT_B252_PBYTE_Msk (0x01UL << GPIO_PORT_B252_PBYTE_Pos) /*!< GPIO_PORT B252: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B253 -----------------------------------------
+#define GPIO_PORT_B253_PBYTE_Pos 0 /*!< GPIO_PORT B253: PBYTE Position */
+#define GPIO_PORT_B253_PBYTE_Msk (0x01UL << GPIO_PORT_B253_PBYTE_Pos) /*!< GPIO_PORT B253: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B254 -----------------------------------------
+#define GPIO_PORT_B254_PBYTE_Pos 0 /*!< GPIO_PORT B254: PBYTE Position */
+#define GPIO_PORT_B254_PBYTE_Msk (0x01UL << GPIO_PORT_B254_PBYTE_Pos) /*!< GPIO_PORT B254: PBYTE Mask */
+
+// ------------------------------------- GPIO_PORT_B255 -----------------------------------------
+#define GPIO_PORT_B255_PBYTE_Pos 0 /*!< GPIO_PORT B255: PBYTE Position */
+#define GPIO_PORT_B255_PBYTE_Msk (0x01UL << GPIO_PORT_B255_PBYTE_Pos) /*!< GPIO_PORT B255: PBYTE Mask */
+
+// -------------------------------------- GPIO_PORT_W0 ------------------------------------------
+#define GPIO_PORT_W0_PWORD_Pos 0 /*!< GPIO_PORT W0: PWORD Position */
+#define GPIO_PORT_W0_PWORD_Msk (0xffffffffUL << GPIO_PORT_W0_PWORD_Pos) /*!< GPIO_PORT W0: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W1 ------------------------------------------
+#define GPIO_PORT_W1_PWORD_Pos 0 /*!< GPIO_PORT W1: PWORD Position */
+#define GPIO_PORT_W1_PWORD_Msk (0xffffffffUL << GPIO_PORT_W1_PWORD_Pos) /*!< GPIO_PORT W1: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W2 ------------------------------------------
+#define GPIO_PORT_W2_PWORD_Pos 0 /*!< GPIO_PORT W2: PWORD Position */
+#define GPIO_PORT_W2_PWORD_Msk (0xffffffffUL << GPIO_PORT_W2_PWORD_Pos) /*!< GPIO_PORT W2: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W3 ------------------------------------------
+#define GPIO_PORT_W3_PWORD_Pos 0 /*!< GPIO_PORT W3: PWORD Position */
+#define GPIO_PORT_W3_PWORD_Msk (0xffffffffUL << GPIO_PORT_W3_PWORD_Pos) /*!< GPIO_PORT W3: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W4 ------------------------------------------
+#define GPIO_PORT_W4_PWORD_Pos 0 /*!< GPIO_PORT W4: PWORD Position */
+#define GPIO_PORT_W4_PWORD_Msk (0xffffffffUL << GPIO_PORT_W4_PWORD_Pos) /*!< GPIO_PORT W4: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W5 ------------------------------------------
+#define GPIO_PORT_W5_PWORD_Pos 0 /*!< GPIO_PORT W5: PWORD Position */
+#define GPIO_PORT_W5_PWORD_Msk (0xffffffffUL << GPIO_PORT_W5_PWORD_Pos) /*!< GPIO_PORT W5: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W6 ------------------------------------------
+#define GPIO_PORT_W6_PWORD_Pos 0 /*!< GPIO_PORT W6: PWORD Position */
+#define GPIO_PORT_W6_PWORD_Msk (0xffffffffUL << GPIO_PORT_W6_PWORD_Pos) /*!< GPIO_PORT W6: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W7 ------------------------------------------
+#define GPIO_PORT_W7_PWORD_Pos 0 /*!< GPIO_PORT W7: PWORD Position */
+#define GPIO_PORT_W7_PWORD_Msk (0xffffffffUL << GPIO_PORT_W7_PWORD_Pos) /*!< GPIO_PORT W7: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W8 ------------------------------------------
+#define GPIO_PORT_W8_PWORD_Pos 0 /*!< GPIO_PORT W8: PWORD Position */
+#define GPIO_PORT_W8_PWORD_Msk (0xffffffffUL << GPIO_PORT_W8_PWORD_Pos) /*!< GPIO_PORT W8: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W9 ------------------------------------------
+#define GPIO_PORT_W9_PWORD_Pos 0 /*!< GPIO_PORT W9: PWORD Position */
+#define GPIO_PORT_W9_PWORD_Msk (0xffffffffUL << GPIO_PORT_W9_PWORD_Pos) /*!< GPIO_PORT W9: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W10 -----------------------------------------
+#define GPIO_PORT_W10_PWORD_Pos 0 /*!< GPIO_PORT W10: PWORD Position */
+#define GPIO_PORT_W10_PWORD_Msk (0xffffffffUL << GPIO_PORT_W10_PWORD_Pos) /*!< GPIO_PORT W10: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W11 -----------------------------------------
+#define GPIO_PORT_W11_PWORD_Pos 0 /*!< GPIO_PORT W11: PWORD Position */
+#define GPIO_PORT_W11_PWORD_Msk (0xffffffffUL << GPIO_PORT_W11_PWORD_Pos) /*!< GPIO_PORT W11: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W12 -----------------------------------------
+#define GPIO_PORT_W12_PWORD_Pos 0 /*!< GPIO_PORT W12: PWORD Position */
+#define GPIO_PORT_W12_PWORD_Msk (0xffffffffUL << GPIO_PORT_W12_PWORD_Pos) /*!< GPIO_PORT W12: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W13 -----------------------------------------
+#define GPIO_PORT_W13_PWORD_Pos 0 /*!< GPIO_PORT W13: PWORD Position */
+#define GPIO_PORT_W13_PWORD_Msk (0xffffffffUL << GPIO_PORT_W13_PWORD_Pos) /*!< GPIO_PORT W13: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W14 -----------------------------------------
+#define GPIO_PORT_W14_PWORD_Pos 0 /*!< GPIO_PORT W14: PWORD Position */
+#define GPIO_PORT_W14_PWORD_Msk (0xffffffffUL << GPIO_PORT_W14_PWORD_Pos) /*!< GPIO_PORT W14: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W15 -----------------------------------------
+#define GPIO_PORT_W15_PWORD_Pos 0 /*!< GPIO_PORT W15: PWORD Position */
+#define GPIO_PORT_W15_PWORD_Msk (0xffffffffUL << GPIO_PORT_W15_PWORD_Pos) /*!< GPIO_PORT W15: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W16 -----------------------------------------
+#define GPIO_PORT_W16_PWORD_Pos 0 /*!< GPIO_PORT W16: PWORD Position */
+#define GPIO_PORT_W16_PWORD_Msk (0xffffffffUL << GPIO_PORT_W16_PWORD_Pos) /*!< GPIO_PORT W16: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W17 -----------------------------------------
+#define GPIO_PORT_W17_PWORD_Pos 0 /*!< GPIO_PORT W17: PWORD Position */
+#define GPIO_PORT_W17_PWORD_Msk (0xffffffffUL << GPIO_PORT_W17_PWORD_Pos) /*!< GPIO_PORT W17: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W18 -----------------------------------------
+#define GPIO_PORT_W18_PWORD_Pos 0 /*!< GPIO_PORT W18: PWORD Position */
+#define GPIO_PORT_W18_PWORD_Msk (0xffffffffUL << GPIO_PORT_W18_PWORD_Pos) /*!< GPIO_PORT W18: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W19 -----------------------------------------
+#define GPIO_PORT_W19_PWORD_Pos 0 /*!< GPIO_PORT W19: PWORD Position */
+#define GPIO_PORT_W19_PWORD_Msk (0xffffffffUL << GPIO_PORT_W19_PWORD_Pos) /*!< GPIO_PORT W19: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W20 -----------------------------------------
+#define GPIO_PORT_W20_PWORD_Pos 0 /*!< GPIO_PORT W20: PWORD Position */
+#define GPIO_PORT_W20_PWORD_Msk (0xffffffffUL << GPIO_PORT_W20_PWORD_Pos) /*!< GPIO_PORT W20: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W21 -----------------------------------------
+#define GPIO_PORT_W21_PWORD_Pos 0 /*!< GPIO_PORT W21: PWORD Position */
+#define GPIO_PORT_W21_PWORD_Msk (0xffffffffUL << GPIO_PORT_W21_PWORD_Pos) /*!< GPIO_PORT W21: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W22 -----------------------------------------
+#define GPIO_PORT_W22_PWORD_Pos 0 /*!< GPIO_PORT W22: PWORD Position */
+#define GPIO_PORT_W22_PWORD_Msk (0xffffffffUL << GPIO_PORT_W22_PWORD_Pos) /*!< GPIO_PORT W22: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W23 -----------------------------------------
+#define GPIO_PORT_W23_PWORD_Pos 0 /*!< GPIO_PORT W23: PWORD Position */
+#define GPIO_PORT_W23_PWORD_Msk (0xffffffffUL << GPIO_PORT_W23_PWORD_Pos) /*!< GPIO_PORT W23: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W24 -----------------------------------------
+#define GPIO_PORT_W24_PWORD_Pos 0 /*!< GPIO_PORT W24: PWORD Position */
+#define GPIO_PORT_W24_PWORD_Msk (0xffffffffUL << GPIO_PORT_W24_PWORD_Pos) /*!< GPIO_PORT W24: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W25 -----------------------------------------
+#define GPIO_PORT_W25_PWORD_Pos 0 /*!< GPIO_PORT W25: PWORD Position */
+#define GPIO_PORT_W25_PWORD_Msk (0xffffffffUL << GPIO_PORT_W25_PWORD_Pos) /*!< GPIO_PORT W25: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W26 -----------------------------------------
+#define GPIO_PORT_W26_PWORD_Pos 0 /*!< GPIO_PORT W26: PWORD Position */
+#define GPIO_PORT_W26_PWORD_Msk (0xffffffffUL << GPIO_PORT_W26_PWORD_Pos) /*!< GPIO_PORT W26: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W27 -----------------------------------------
+#define GPIO_PORT_W27_PWORD_Pos 0 /*!< GPIO_PORT W27: PWORD Position */
+#define GPIO_PORT_W27_PWORD_Msk (0xffffffffUL << GPIO_PORT_W27_PWORD_Pos) /*!< GPIO_PORT W27: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W28 -----------------------------------------
+#define GPIO_PORT_W28_PWORD_Pos 0 /*!< GPIO_PORT W28: PWORD Position */
+#define GPIO_PORT_W28_PWORD_Msk (0xffffffffUL << GPIO_PORT_W28_PWORD_Pos) /*!< GPIO_PORT W28: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W29 -----------------------------------------
+#define GPIO_PORT_W29_PWORD_Pos 0 /*!< GPIO_PORT W29: PWORD Position */
+#define GPIO_PORT_W29_PWORD_Msk (0xffffffffUL << GPIO_PORT_W29_PWORD_Pos) /*!< GPIO_PORT W29: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W30 -----------------------------------------
+#define GPIO_PORT_W30_PWORD_Pos 0 /*!< GPIO_PORT W30: PWORD Position */
+#define GPIO_PORT_W30_PWORD_Msk (0xffffffffUL << GPIO_PORT_W30_PWORD_Pos) /*!< GPIO_PORT W30: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W31 -----------------------------------------
+#define GPIO_PORT_W31_PWORD_Pos 0 /*!< GPIO_PORT W31: PWORD Position */
+#define GPIO_PORT_W31_PWORD_Msk (0xffffffffUL << GPIO_PORT_W31_PWORD_Pos) /*!< GPIO_PORT W31: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W32 -----------------------------------------
+#define GPIO_PORT_W32_PWORD_Pos 0 /*!< GPIO_PORT W32: PWORD Position */
+#define GPIO_PORT_W32_PWORD_Msk (0xffffffffUL << GPIO_PORT_W32_PWORD_Pos) /*!< GPIO_PORT W32: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W33 -----------------------------------------
+#define GPIO_PORT_W33_PWORD_Pos 0 /*!< GPIO_PORT W33: PWORD Position */
+#define GPIO_PORT_W33_PWORD_Msk (0xffffffffUL << GPIO_PORT_W33_PWORD_Pos) /*!< GPIO_PORT W33: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W34 -----------------------------------------
+#define GPIO_PORT_W34_PWORD_Pos 0 /*!< GPIO_PORT W34: PWORD Position */
+#define GPIO_PORT_W34_PWORD_Msk (0xffffffffUL << GPIO_PORT_W34_PWORD_Pos) /*!< GPIO_PORT W34: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W35 -----------------------------------------
+#define GPIO_PORT_W35_PWORD_Pos 0 /*!< GPIO_PORT W35: PWORD Position */
+#define GPIO_PORT_W35_PWORD_Msk (0xffffffffUL << GPIO_PORT_W35_PWORD_Pos) /*!< GPIO_PORT W35: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W36 -----------------------------------------
+#define GPIO_PORT_W36_PWORD_Pos 0 /*!< GPIO_PORT W36: PWORD Position */
+#define GPIO_PORT_W36_PWORD_Msk (0xffffffffUL << GPIO_PORT_W36_PWORD_Pos) /*!< GPIO_PORT W36: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W37 -----------------------------------------
+#define GPIO_PORT_W37_PWORD_Pos 0 /*!< GPIO_PORT W37: PWORD Position */
+#define GPIO_PORT_W37_PWORD_Msk (0xffffffffUL << GPIO_PORT_W37_PWORD_Pos) /*!< GPIO_PORT W37: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W38 -----------------------------------------
+#define GPIO_PORT_W38_PWORD_Pos 0 /*!< GPIO_PORT W38: PWORD Position */
+#define GPIO_PORT_W38_PWORD_Msk (0xffffffffUL << GPIO_PORT_W38_PWORD_Pos) /*!< GPIO_PORT W38: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W39 -----------------------------------------
+#define GPIO_PORT_W39_PWORD_Pos 0 /*!< GPIO_PORT W39: PWORD Position */
+#define GPIO_PORT_W39_PWORD_Msk (0xffffffffUL << GPIO_PORT_W39_PWORD_Pos) /*!< GPIO_PORT W39: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W40 -----------------------------------------
+#define GPIO_PORT_W40_PWORD_Pos 0 /*!< GPIO_PORT W40: PWORD Position */
+#define GPIO_PORT_W40_PWORD_Msk (0xffffffffUL << GPIO_PORT_W40_PWORD_Pos) /*!< GPIO_PORT W40: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W41 -----------------------------------------
+#define GPIO_PORT_W41_PWORD_Pos 0 /*!< GPIO_PORT W41: PWORD Position */
+#define GPIO_PORT_W41_PWORD_Msk (0xffffffffUL << GPIO_PORT_W41_PWORD_Pos) /*!< GPIO_PORT W41: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W42 -----------------------------------------
+#define GPIO_PORT_W42_PWORD_Pos 0 /*!< GPIO_PORT W42: PWORD Position */
+#define GPIO_PORT_W42_PWORD_Msk (0xffffffffUL << GPIO_PORT_W42_PWORD_Pos) /*!< GPIO_PORT W42: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W43 -----------------------------------------
+#define GPIO_PORT_W43_PWORD_Pos 0 /*!< GPIO_PORT W43: PWORD Position */
+#define GPIO_PORT_W43_PWORD_Msk (0xffffffffUL << GPIO_PORT_W43_PWORD_Pos) /*!< GPIO_PORT W43: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W44 -----------------------------------------
+#define GPIO_PORT_W44_PWORD_Pos 0 /*!< GPIO_PORT W44: PWORD Position */
+#define GPIO_PORT_W44_PWORD_Msk (0xffffffffUL << GPIO_PORT_W44_PWORD_Pos) /*!< GPIO_PORT W44: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W45 -----------------------------------------
+#define GPIO_PORT_W45_PWORD_Pos 0 /*!< GPIO_PORT W45: PWORD Position */
+#define GPIO_PORT_W45_PWORD_Msk (0xffffffffUL << GPIO_PORT_W45_PWORD_Pos) /*!< GPIO_PORT W45: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W46 -----------------------------------------
+#define GPIO_PORT_W46_PWORD_Pos 0 /*!< GPIO_PORT W46: PWORD Position */
+#define GPIO_PORT_W46_PWORD_Msk (0xffffffffUL << GPIO_PORT_W46_PWORD_Pos) /*!< GPIO_PORT W46: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W47 -----------------------------------------
+#define GPIO_PORT_W47_PWORD_Pos 0 /*!< GPIO_PORT W47: PWORD Position */
+#define GPIO_PORT_W47_PWORD_Msk (0xffffffffUL << GPIO_PORT_W47_PWORD_Pos) /*!< GPIO_PORT W47: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W48 -----------------------------------------
+#define GPIO_PORT_W48_PWORD_Pos 0 /*!< GPIO_PORT W48: PWORD Position */
+#define GPIO_PORT_W48_PWORD_Msk (0xffffffffUL << GPIO_PORT_W48_PWORD_Pos) /*!< GPIO_PORT W48: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W49 -----------------------------------------
+#define GPIO_PORT_W49_PWORD_Pos 0 /*!< GPIO_PORT W49: PWORD Position */
+#define GPIO_PORT_W49_PWORD_Msk (0xffffffffUL << GPIO_PORT_W49_PWORD_Pos) /*!< GPIO_PORT W49: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W50 -----------------------------------------
+#define GPIO_PORT_W50_PWORD_Pos 0 /*!< GPIO_PORT W50: PWORD Position */
+#define GPIO_PORT_W50_PWORD_Msk (0xffffffffUL << GPIO_PORT_W50_PWORD_Pos) /*!< GPIO_PORT W50: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W51 -----------------------------------------
+#define GPIO_PORT_W51_PWORD_Pos 0 /*!< GPIO_PORT W51: PWORD Position */
+#define GPIO_PORT_W51_PWORD_Msk (0xffffffffUL << GPIO_PORT_W51_PWORD_Pos) /*!< GPIO_PORT W51: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W52 -----------------------------------------
+#define GPIO_PORT_W52_PWORD_Pos 0 /*!< GPIO_PORT W52: PWORD Position */
+#define GPIO_PORT_W52_PWORD_Msk (0xffffffffUL << GPIO_PORT_W52_PWORD_Pos) /*!< GPIO_PORT W52: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W53 -----------------------------------------
+#define GPIO_PORT_W53_PWORD_Pos 0 /*!< GPIO_PORT W53: PWORD Position */
+#define GPIO_PORT_W53_PWORD_Msk (0xffffffffUL << GPIO_PORT_W53_PWORD_Pos) /*!< GPIO_PORT W53: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W54 -----------------------------------------
+#define GPIO_PORT_W54_PWORD_Pos 0 /*!< GPIO_PORT W54: PWORD Position */
+#define GPIO_PORT_W54_PWORD_Msk (0xffffffffUL << GPIO_PORT_W54_PWORD_Pos) /*!< GPIO_PORT W54: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W55 -----------------------------------------
+#define GPIO_PORT_W55_PWORD_Pos 0 /*!< GPIO_PORT W55: PWORD Position */
+#define GPIO_PORT_W55_PWORD_Msk (0xffffffffUL << GPIO_PORT_W55_PWORD_Pos) /*!< GPIO_PORT W55: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W56 -----------------------------------------
+#define GPIO_PORT_W56_PWORD_Pos 0 /*!< GPIO_PORT W56: PWORD Position */
+#define GPIO_PORT_W56_PWORD_Msk (0xffffffffUL << GPIO_PORT_W56_PWORD_Pos) /*!< GPIO_PORT W56: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W57 -----------------------------------------
+#define GPIO_PORT_W57_PWORD_Pos 0 /*!< GPIO_PORT W57: PWORD Position */
+#define GPIO_PORT_W57_PWORD_Msk (0xffffffffUL << GPIO_PORT_W57_PWORD_Pos) /*!< GPIO_PORT W57: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W58 -----------------------------------------
+#define GPIO_PORT_W58_PWORD_Pos 0 /*!< GPIO_PORT W58: PWORD Position */
+#define GPIO_PORT_W58_PWORD_Msk (0xffffffffUL << GPIO_PORT_W58_PWORD_Pos) /*!< GPIO_PORT W58: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W59 -----------------------------------------
+#define GPIO_PORT_W59_PWORD_Pos 0 /*!< GPIO_PORT W59: PWORD Position */
+#define GPIO_PORT_W59_PWORD_Msk (0xffffffffUL << GPIO_PORT_W59_PWORD_Pos) /*!< GPIO_PORT W59: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W60 -----------------------------------------
+#define GPIO_PORT_W60_PWORD_Pos 0 /*!< GPIO_PORT W60: PWORD Position */
+#define GPIO_PORT_W60_PWORD_Msk (0xffffffffUL << GPIO_PORT_W60_PWORD_Pos) /*!< GPIO_PORT W60: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W61 -----------------------------------------
+#define GPIO_PORT_W61_PWORD_Pos 0 /*!< GPIO_PORT W61: PWORD Position */
+#define GPIO_PORT_W61_PWORD_Msk (0xffffffffUL << GPIO_PORT_W61_PWORD_Pos) /*!< GPIO_PORT W61: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W62 -----------------------------------------
+#define GPIO_PORT_W62_PWORD_Pos 0 /*!< GPIO_PORT W62: PWORD Position */
+#define GPIO_PORT_W62_PWORD_Msk (0xffffffffUL << GPIO_PORT_W62_PWORD_Pos) /*!< GPIO_PORT W62: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W63 -----------------------------------------
+#define GPIO_PORT_W63_PWORD_Pos 0 /*!< GPIO_PORT W63: PWORD Position */
+#define GPIO_PORT_W63_PWORD_Msk (0xffffffffUL << GPIO_PORT_W63_PWORD_Pos) /*!< GPIO_PORT W63: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W64 -----------------------------------------
+#define GPIO_PORT_W64_PWORD_Pos 0 /*!< GPIO_PORT W64: PWORD Position */
+#define GPIO_PORT_W64_PWORD_Msk (0xffffffffUL << GPIO_PORT_W64_PWORD_Pos) /*!< GPIO_PORT W64: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W65 -----------------------------------------
+#define GPIO_PORT_W65_PWORD_Pos 0 /*!< GPIO_PORT W65: PWORD Position */
+#define GPIO_PORT_W65_PWORD_Msk (0xffffffffUL << GPIO_PORT_W65_PWORD_Pos) /*!< GPIO_PORT W65: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W66 -----------------------------------------
+#define GPIO_PORT_W66_PWORD_Pos 0 /*!< GPIO_PORT W66: PWORD Position */
+#define GPIO_PORT_W66_PWORD_Msk (0xffffffffUL << GPIO_PORT_W66_PWORD_Pos) /*!< GPIO_PORT W66: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W67 -----------------------------------------
+#define GPIO_PORT_W67_PWORD_Pos 0 /*!< GPIO_PORT W67: PWORD Position */
+#define GPIO_PORT_W67_PWORD_Msk (0xffffffffUL << GPIO_PORT_W67_PWORD_Pos) /*!< GPIO_PORT W67: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W68 -----------------------------------------
+#define GPIO_PORT_W68_PWORD_Pos 0 /*!< GPIO_PORT W68: PWORD Position */
+#define GPIO_PORT_W68_PWORD_Msk (0xffffffffUL << GPIO_PORT_W68_PWORD_Pos) /*!< GPIO_PORT W68: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W69 -----------------------------------------
+#define GPIO_PORT_W69_PWORD_Pos 0 /*!< GPIO_PORT W69: PWORD Position */
+#define GPIO_PORT_W69_PWORD_Msk (0xffffffffUL << GPIO_PORT_W69_PWORD_Pos) /*!< GPIO_PORT W69: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W70 -----------------------------------------
+#define GPIO_PORT_W70_PWORD_Pos 0 /*!< GPIO_PORT W70: PWORD Position */
+#define GPIO_PORT_W70_PWORD_Msk (0xffffffffUL << GPIO_PORT_W70_PWORD_Pos) /*!< GPIO_PORT W70: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W71 -----------------------------------------
+#define GPIO_PORT_W71_PWORD_Pos 0 /*!< GPIO_PORT W71: PWORD Position */
+#define GPIO_PORT_W71_PWORD_Msk (0xffffffffUL << GPIO_PORT_W71_PWORD_Pos) /*!< GPIO_PORT W71: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W72 -----------------------------------------
+#define GPIO_PORT_W72_PWORD_Pos 0 /*!< GPIO_PORT W72: PWORD Position */
+#define GPIO_PORT_W72_PWORD_Msk (0xffffffffUL << GPIO_PORT_W72_PWORD_Pos) /*!< GPIO_PORT W72: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W73 -----------------------------------------
+#define GPIO_PORT_W73_PWORD_Pos 0 /*!< GPIO_PORT W73: PWORD Position */
+#define GPIO_PORT_W73_PWORD_Msk (0xffffffffUL << GPIO_PORT_W73_PWORD_Pos) /*!< GPIO_PORT W73: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W74 -----------------------------------------
+#define GPIO_PORT_W74_PWORD_Pos 0 /*!< GPIO_PORT W74: PWORD Position */
+#define GPIO_PORT_W74_PWORD_Msk (0xffffffffUL << GPIO_PORT_W74_PWORD_Pos) /*!< GPIO_PORT W74: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W75 -----------------------------------------
+#define GPIO_PORT_W75_PWORD_Pos 0 /*!< GPIO_PORT W75: PWORD Position */
+#define GPIO_PORT_W75_PWORD_Msk (0xffffffffUL << GPIO_PORT_W75_PWORD_Pos) /*!< GPIO_PORT W75: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W76 -----------------------------------------
+#define GPIO_PORT_W76_PWORD_Pos 0 /*!< GPIO_PORT W76: PWORD Position */
+#define GPIO_PORT_W76_PWORD_Msk (0xffffffffUL << GPIO_PORT_W76_PWORD_Pos) /*!< GPIO_PORT W76: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W77 -----------------------------------------
+#define GPIO_PORT_W77_PWORD_Pos 0 /*!< GPIO_PORT W77: PWORD Position */
+#define GPIO_PORT_W77_PWORD_Msk (0xffffffffUL << GPIO_PORT_W77_PWORD_Pos) /*!< GPIO_PORT W77: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W78 -----------------------------------------
+#define GPIO_PORT_W78_PWORD_Pos 0 /*!< GPIO_PORT W78: PWORD Position */
+#define GPIO_PORT_W78_PWORD_Msk (0xffffffffUL << GPIO_PORT_W78_PWORD_Pos) /*!< GPIO_PORT W78: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W79 -----------------------------------------
+#define GPIO_PORT_W79_PWORD_Pos 0 /*!< GPIO_PORT W79: PWORD Position */
+#define GPIO_PORT_W79_PWORD_Msk (0xffffffffUL << GPIO_PORT_W79_PWORD_Pos) /*!< GPIO_PORT W79: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W80 -----------------------------------------
+#define GPIO_PORT_W80_PWORD_Pos 0 /*!< GPIO_PORT W80: PWORD Position */
+#define GPIO_PORT_W80_PWORD_Msk (0xffffffffUL << GPIO_PORT_W80_PWORD_Pos) /*!< GPIO_PORT W80: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W81 -----------------------------------------
+#define GPIO_PORT_W81_PWORD_Pos 0 /*!< GPIO_PORT W81: PWORD Position */
+#define GPIO_PORT_W81_PWORD_Msk (0xffffffffUL << GPIO_PORT_W81_PWORD_Pos) /*!< GPIO_PORT W81: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W82 -----------------------------------------
+#define GPIO_PORT_W82_PWORD_Pos 0 /*!< GPIO_PORT W82: PWORD Position */
+#define GPIO_PORT_W82_PWORD_Msk (0xffffffffUL << GPIO_PORT_W82_PWORD_Pos) /*!< GPIO_PORT W82: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W83 -----------------------------------------
+#define GPIO_PORT_W83_PWORD_Pos 0 /*!< GPIO_PORT W83: PWORD Position */
+#define GPIO_PORT_W83_PWORD_Msk (0xffffffffUL << GPIO_PORT_W83_PWORD_Pos) /*!< GPIO_PORT W83: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W84 -----------------------------------------
+#define GPIO_PORT_W84_PWORD_Pos 0 /*!< GPIO_PORT W84: PWORD Position */
+#define GPIO_PORT_W84_PWORD_Msk (0xffffffffUL << GPIO_PORT_W84_PWORD_Pos) /*!< GPIO_PORT W84: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W85 -----------------------------------------
+#define GPIO_PORT_W85_PWORD_Pos 0 /*!< GPIO_PORT W85: PWORD Position */
+#define GPIO_PORT_W85_PWORD_Msk (0xffffffffUL << GPIO_PORT_W85_PWORD_Pos) /*!< GPIO_PORT W85: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W86 -----------------------------------------
+#define GPIO_PORT_W86_PWORD_Pos 0 /*!< GPIO_PORT W86: PWORD Position */
+#define GPIO_PORT_W86_PWORD_Msk (0xffffffffUL << GPIO_PORT_W86_PWORD_Pos) /*!< GPIO_PORT W86: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W87 -----------------------------------------
+#define GPIO_PORT_W87_PWORD_Pos 0 /*!< GPIO_PORT W87: PWORD Position */
+#define GPIO_PORT_W87_PWORD_Msk (0xffffffffUL << GPIO_PORT_W87_PWORD_Pos) /*!< GPIO_PORT W87: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W88 -----------------------------------------
+#define GPIO_PORT_W88_PWORD_Pos 0 /*!< GPIO_PORT W88: PWORD Position */
+#define GPIO_PORT_W88_PWORD_Msk (0xffffffffUL << GPIO_PORT_W88_PWORD_Pos) /*!< GPIO_PORT W88: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W89 -----------------------------------------
+#define GPIO_PORT_W89_PWORD_Pos 0 /*!< GPIO_PORT W89: PWORD Position */
+#define GPIO_PORT_W89_PWORD_Msk (0xffffffffUL << GPIO_PORT_W89_PWORD_Pos) /*!< GPIO_PORT W89: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W90 -----------------------------------------
+#define GPIO_PORT_W90_PWORD_Pos 0 /*!< GPIO_PORT W90: PWORD Position */
+#define GPIO_PORT_W90_PWORD_Msk (0xffffffffUL << GPIO_PORT_W90_PWORD_Pos) /*!< GPIO_PORT W90: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W91 -----------------------------------------
+#define GPIO_PORT_W91_PWORD_Pos 0 /*!< GPIO_PORT W91: PWORD Position */
+#define GPIO_PORT_W91_PWORD_Msk (0xffffffffUL << GPIO_PORT_W91_PWORD_Pos) /*!< GPIO_PORT W91: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W92 -----------------------------------------
+#define GPIO_PORT_W92_PWORD_Pos 0 /*!< GPIO_PORT W92: PWORD Position */
+#define GPIO_PORT_W92_PWORD_Msk (0xffffffffUL << GPIO_PORT_W92_PWORD_Pos) /*!< GPIO_PORT W92: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W93 -----------------------------------------
+#define GPIO_PORT_W93_PWORD_Pos 0 /*!< GPIO_PORT W93: PWORD Position */
+#define GPIO_PORT_W93_PWORD_Msk (0xffffffffUL << GPIO_PORT_W93_PWORD_Pos) /*!< GPIO_PORT W93: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W94 -----------------------------------------
+#define GPIO_PORT_W94_PWORD_Pos 0 /*!< GPIO_PORT W94: PWORD Position */
+#define GPIO_PORT_W94_PWORD_Msk (0xffffffffUL << GPIO_PORT_W94_PWORD_Pos) /*!< GPIO_PORT W94: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W95 -----------------------------------------
+#define GPIO_PORT_W95_PWORD_Pos 0 /*!< GPIO_PORT W95: PWORD Position */
+#define GPIO_PORT_W95_PWORD_Msk (0xffffffffUL << GPIO_PORT_W95_PWORD_Pos) /*!< GPIO_PORT W95: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W96 -----------------------------------------
+#define GPIO_PORT_W96_PWORD_Pos 0 /*!< GPIO_PORT W96: PWORD Position */
+#define GPIO_PORT_W96_PWORD_Msk (0xffffffffUL << GPIO_PORT_W96_PWORD_Pos) /*!< GPIO_PORT W96: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W97 -----------------------------------------
+#define GPIO_PORT_W97_PWORD_Pos 0 /*!< GPIO_PORT W97: PWORD Position */
+#define GPIO_PORT_W97_PWORD_Msk (0xffffffffUL << GPIO_PORT_W97_PWORD_Pos) /*!< GPIO_PORT W97: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W98 -----------------------------------------
+#define GPIO_PORT_W98_PWORD_Pos 0 /*!< GPIO_PORT W98: PWORD Position */
+#define GPIO_PORT_W98_PWORD_Msk (0xffffffffUL << GPIO_PORT_W98_PWORD_Pos) /*!< GPIO_PORT W98: PWORD Mask */
+
+// -------------------------------------- GPIO_PORT_W99 -----------------------------------------
+#define GPIO_PORT_W99_PWORD_Pos 0 /*!< GPIO_PORT W99: PWORD Position */
+#define GPIO_PORT_W99_PWORD_Msk (0xffffffffUL << GPIO_PORT_W99_PWORD_Pos) /*!< GPIO_PORT W99: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W100 -----------------------------------------
+#define GPIO_PORT_W100_PWORD_Pos 0 /*!< GPIO_PORT W100: PWORD Position */
+#define GPIO_PORT_W100_PWORD_Msk (0xffffffffUL << GPIO_PORT_W100_PWORD_Pos) /*!< GPIO_PORT W100: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W101 -----------------------------------------
+#define GPIO_PORT_W101_PWORD_Pos 0 /*!< GPIO_PORT W101: PWORD Position */
+#define GPIO_PORT_W101_PWORD_Msk (0xffffffffUL << GPIO_PORT_W101_PWORD_Pos) /*!< GPIO_PORT W101: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W102 -----------------------------------------
+#define GPIO_PORT_W102_PWORD_Pos 0 /*!< GPIO_PORT W102: PWORD Position */
+#define GPIO_PORT_W102_PWORD_Msk (0xffffffffUL << GPIO_PORT_W102_PWORD_Pos) /*!< GPIO_PORT W102: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W103 -----------------------------------------
+#define GPIO_PORT_W103_PWORD_Pos 0 /*!< GPIO_PORT W103: PWORD Position */
+#define GPIO_PORT_W103_PWORD_Msk (0xffffffffUL << GPIO_PORT_W103_PWORD_Pos) /*!< GPIO_PORT W103: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W104 -----------------------------------------
+#define GPIO_PORT_W104_PWORD_Pos 0 /*!< GPIO_PORT W104: PWORD Position */
+#define GPIO_PORT_W104_PWORD_Msk (0xffffffffUL << GPIO_PORT_W104_PWORD_Pos) /*!< GPIO_PORT W104: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W105 -----------------------------------------
+#define GPIO_PORT_W105_PWORD_Pos 0 /*!< GPIO_PORT W105: PWORD Position */
+#define GPIO_PORT_W105_PWORD_Msk (0xffffffffUL << GPIO_PORT_W105_PWORD_Pos) /*!< GPIO_PORT W105: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W106 -----------------------------------------
+#define GPIO_PORT_W106_PWORD_Pos 0 /*!< GPIO_PORT W106: PWORD Position */
+#define GPIO_PORT_W106_PWORD_Msk (0xffffffffUL << GPIO_PORT_W106_PWORD_Pos) /*!< GPIO_PORT W106: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W107 -----------------------------------------
+#define GPIO_PORT_W107_PWORD_Pos 0 /*!< GPIO_PORT W107: PWORD Position */
+#define GPIO_PORT_W107_PWORD_Msk (0xffffffffUL << GPIO_PORT_W107_PWORD_Pos) /*!< GPIO_PORT W107: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W108 -----------------------------------------
+#define GPIO_PORT_W108_PWORD_Pos 0 /*!< GPIO_PORT W108: PWORD Position */
+#define GPIO_PORT_W108_PWORD_Msk (0xffffffffUL << GPIO_PORT_W108_PWORD_Pos) /*!< GPIO_PORT W108: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W109 -----------------------------------------
+#define GPIO_PORT_W109_PWORD_Pos 0 /*!< GPIO_PORT W109: PWORD Position */
+#define GPIO_PORT_W109_PWORD_Msk (0xffffffffUL << GPIO_PORT_W109_PWORD_Pos) /*!< GPIO_PORT W109: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W110 -----------------------------------------
+#define GPIO_PORT_W110_PWORD_Pos 0 /*!< GPIO_PORT W110: PWORD Position */
+#define GPIO_PORT_W110_PWORD_Msk (0xffffffffUL << GPIO_PORT_W110_PWORD_Pos) /*!< GPIO_PORT W110: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W111 -----------------------------------------
+#define GPIO_PORT_W111_PWORD_Pos 0 /*!< GPIO_PORT W111: PWORD Position */
+#define GPIO_PORT_W111_PWORD_Msk (0xffffffffUL << GPIO_PORT_W111_PWORD_Pos) /*!< GPIO_PORT W111: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W112 -----------------------------------------
+#define GPIO_PORT_W112_PWORD_Pos 0 /*!< GPIO_PORT W112: PWORD Position */
+#define GPIO_PORT_W112_PWORD_Msk (0xffffffffUL << GPIO_PORT_W112_PWORD_Pos) /*!< GPIO_PORT W112: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W113 -----------------------------------------
+#define GPIO_PORT_W113_PWORD_Pos 0 /*!< GPIO_PORT W113: PWORD Position */
+#define GPIO_PORT_W113_PWORD_Msk (0xffffffffUL << GPIO_PORT_W113_PWORD_Pos) /*!< GPIO_PORT W113: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W114 -----------------------------------------
+#define GPIO_PORT_W114_PWORD_Pos 0 /*!< GPIO_PORT W114: PWORD Position */
+#define GPIO_PORT_W114_PWORD_Msk (0xffffffffUL << GPIO_PORT_W114_PWORD_Pos) /*!< GPIO_PORT W114: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W115 -----------------------------------------
+#define GPIO_PORT_W115_PWORD_Pos 0 /*!< GPIO_PORT W115: PWORD Position */
+#define GPIO_PORT_W115_PWORD_Msk (0xffffffffUL << GPIO_PORT_W115_PWORD_Pos) /*!< GPIO_PORT W115: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W116 -----------------------------------------
+#define GPIO_PORT_W116_PWORD_Pos 0 /*!< GPIO_PORT W116: PWORD Position */
+#define GPIO_PORT_W116_PWORD_Msk (0xffffffffUL << GPIO_PORT_W116_PWORD_Pos) /*!< GPIO_PORT W116: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W117 -----------------------------------------
+#define GPIO_PORT_W117_PWORD_Pos 0 /*!< GPIO_PORT W117: PWORD Position */
+#define GPIO_PORT_W117_PWORD_Msk (0xffffffffUL << GPIO_PORT_W117_PWORD_Pos) /*!< GPIO_PORT W117: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W118 -----------------------------------------
+#define GPIO_PORT_W118_PWORD_Pos 0 /*!< GPIO_PORT W118: PWORD Position */
+#define GPIO_PORT_W118_PWORD_Msk (0xffffffffUL << GPIO_PORT_W118_PWORD_Pos) /*!< GPIO_PORT W118: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W119 -----------------------------------------
+#define GPIO_PORT_W119_PWORD_Pos 0 /*!< GPIO_PORT W119: PWORD Position */
+#define GPIO_PORT_W119_PWORD_Msk (0xffffffffUL << GPIO_PORT_W119_PWORD_Pos) /*!< GPIO_PORT W119: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W120 -----------------------------------------
+#define GPIO_PORT_W120_PWORD_Pos 0 /*!< GPIO_PORT W120: PWORD Position */
+#define GPIO_PORT_W120_PWORD_Msk (0xffffffffUL << GPIO_PORT_W120_PWORD_Pos) /*!< GPIO_PORT W120: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W121 -----------------------------------------
+#define GPIO_PORT_W121_PWORD_Pos 0 /*!< GPIO_PORT W121: PWORD Position */
+#define GPIO_PORT_W121_PWORD_Msk (0xffffffffUL << GPIO_PORT_W121_PWORD_Pos) /*!< GPIO_PORT W121: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W122 -----------------------------------------
+#define GPIO_PORT_W122_PWORD_Pos 0 /*!< GPIO_PORT W122: PWORD Position */
+#define GPIO_PORT_W122_PWORD_Msk (0xffffffffUL << GPIO_PORT_W122_PWORD_Pos) /*!< GPIO_PORT W122: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W123 -----------------------------------------
+#define GPIO_PORT_W123_PWORD_Pos 0 /*!< GPIO_PORT W123: PWORD Position */
+#define GPIO_PORT_W123_PWORD_Msk (0xffffffffUL << GPIO_PORT_W123_PWORD_Pos) /*!< GPIO_PORT W123: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W124 -----------------------------------------
+#define GPIO_PORT_W124_PWORD_Pos 0 /*!< GPIO_PORT W124: PWORD Position */
+#define GPIO_PORT_W124_PWORD_Msk (0xffffffffUL << GPIO_PORT_W124_PWORD_Pos) /*!< GPIO_PORT W124: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W125 -----------------------------------------
+#define GPIO_PORT_W125_PWORD_Pos 0 /*!< GPIO_PORT W125: PWORD Position */
+#define GPIO_PORT_W125_PWORD_Msk (0xffffffffUL << GPIO_PORT_W125_PWORD_Pos) /*!< GPIO_PORT W125: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W126 -----------------------------------------
+#define GPIO_PORT_W126_PWORD_Pos 0 /*!< GPIO_PORT W126: PWORD Position */
+#define GPIO_PORT_W126_PWORD_Msk (0xffffffffUL << GPIO_PORT_W126_PWORD_Pos) /*!< GPIO_PORT W126: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W127 -----------------------------------------
+#define GPIO_PORT_W127_PWORD_Pos 0 /*!< GPIO_PORT W127: PWORD Position */
+#define GPIO_PORT_W127_PWORD_Msk (0xffffffffUL << GPIO_PORT_W127_PWORD_Pos) /*!< GPIO_PORT W127: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W128 -----------------------------------------
+#define GPIO_PORT_W128_PWORD_Pos 0 /*!< GPIO_PORT W128: PWORD Position */
+#define GPIO_PORT_W128_PWORD_Msk (0xffffffffUL << GPIO_PORT_W128_PWORD_Pos) /*!< GPIO_PORT W128: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W129 -----------------------------------------
+#define GPIO_PORT_W129_PWORD_Pos 0 /*!< GPIO_PORT W129: PWORD Position */
+#define GPIO_PORT_W129_PWORD_Msk (0xffffffffUL << GPIO_PORT_W129_PWORD_Pos) /*!< GPIO_PORT W129: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W130 -----------------------------------------
+#define GPIO_PORT_W130_PWORD_Pos 0 /*!< GPIO_PORT W130: PWORD Position */
+#define GPIO_PORT_W130_PWORD_Msk (0xffffffffUL << GPIO_PORT_W130_PWORD_Pos) /*!< GPIO_PORT W130: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W131 -----------------------------------------
+#define GPIO_PORT_W131_PWORD_Pos 0 /*!< GPIO_PORT W131: PWORD Position */
+#define GPIO_PORT_W131_PWORD_Msk (0xffffffffUL << GPIO_PORT_W131_PWORD_Pos) /*!< GPIO_PORT W131: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W132 -----------------------------------------
+#define GPIO_PORT_W132_PWORD_Pos 0 /*!< GPIO_PORT W132: PWORD Position */
+#define GPIO_PORT_W132_PWORD_Msk (0xffffffffUL << GPIO_PORT_W132_PWORD_Pos) /*!< GPIO_PORT W132: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W133 -----------------------------------------
+#define GPIO_PORT_W133_PWORD_Pos 0 /*!< GPIO_PORT W133: PWORD Position */
+#define GPIO_PORT_W133_PWORD_Msk (0xffffffffUL << GPIO_PORT_W133_PWORD_Pos) /*!< GPIO_PORT W133: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W134 -----------------------------------------
+#define GPIO_PORT_W134_PWORD_Pos 0 /*!< GPIO_PORT W134: PWORD Position */
+#define GPIO_PORT_W134_PWORD_Msk (0xffffffffUL << GPIO_PORT_W134_PWORD_Pos) /*!< GPIO_PORT W134: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W135 -----------------------------------------
+#define GPIO_PORT_W135_PWORD_Pos 0 /*!< GPIO_PORT W135: PWORD Position */
+#define GPIO_PORT_W135_PWORD_Msk (0xffffffffUL << GPIO_PORT_W135_PWORD_Pos) /*!< GPIO_PORT W135: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W136 -----------------------------------------
+#define GPIO_PORT_W136_PWORD_Pos 0 /*!< GPIO_PORT W136: PWORD Position */
+#define GPIO_PORT_W136_PWORD_Msk (0xffffffffUL << GPIO_PORT_W136_PWORD_Pos) /*!< GPIO_PORT W136: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W137 -----------------------------------------
+#define GPIO_PORT_W137_PWORD_Pos 0 /*!< GPIO_PORT W137: PWORD Position */
+#define GPIO_PORT_W137_PWORD_Msk (0xffffffffUL << GPIO_PORT_W137_PWORD_Pos) /*!< GPIO_PORT W137: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W138 -----------------------------------------
+#define GPIO_PORT_W138_PWORD_Pos 0 /*!< GPIO_PORT W138: PWORD Position */
+#define GPIO_PORT_W138_PWORD_Msk (0xffffffffUL << GPIO_PORT_W138_PWORD_Pos) /*!< GPIO_PORT W138: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W139 -----------------------------------------
+#define GPIO_PORT_W139_PWORD_Pos 0 /*!< GPIO_PORT W139: PWORD Position */
+#define GPIO_PORT_W139_PWORD_Msk (0xffffffffUL << GPIO_PORT_W139_PWORD_Pos) /*!< GPIO_PORT W139: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W140 -----------------------------------------
+#define GPIO_PORT_W140_PWORD_Pos 0 /*!< GPIO_PORT W140: PWORD Position */
+#define GPIO_PORT_W140_PWORD_Msk (0xffffffffUL << GPIO_PORT_W140_PWORD_Pos) /*!< GPIO_PORT W140: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W141 -----------------------------------------
+#define GPIO_PORT_W141_PWORD_Pos 0 /*!< GPIO_PORT W141: PWORD Position */
+#define GPIO_PORT_W141_PWORD_Msk (0xffffffffUL << GPIO_PORT_W141_PWORD_Pos) /*!< GPIO_PORT W141: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W142 -----------------------------------------
+#define GPIO_PORT_W142_PWORD_Pos 0 /*!< GPIO_PORT W142: PWORD Position */
+#define GPIO_PORT_W142_PWORD_Msk (0xffffffffUL << GPIO_PORT_W142_PWORD_Pos) /*!< GPIO_PORT W142: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W143 -----------------------------------------
+#define GPIO_PORT_W143_PWORD_Pos 0 /*!< GPIO_PORT W143: PWORD Position */
+#define GPIO_PORT_W143_PWORD_Msk (0xffffffffUL << GPIO_PORT_W143_PWORD_Pos) /*!< GPIO_PORT W143: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W144 -----------------------------------------
+#define GPIO_PORT_W144_PWORD_Pos 0 /*!< GPIO_PORT W144: PWORD Position */
+#define GPIO_PORT_W144_PWORD_Msk (0xffffffffUL << GPIO_PORT_W144_PWORD_Pos) /*!< GPIO_PORT W144: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W145 -----------------------------------------
+#define GPIO_PORT_W145_PWORD_Pos 0 /*!< GPIO_PORT W145: PWORD Position */
+#define GPIO_PORT_W145_PWORD_Msk (0xffffffffUL << GPIO_PORT_W145_PWORD_Pos) /*!< GPIO_PORT W145: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W146 -----------------------------------------
+#define GPIO_PORT_W146_PWORD_Pos 0 /*!< GPIO_PORT W146: PWORD Position */
+#define GPIO_PORT_W146_PWORD_Msk (0xffffffffUL << GPIO_PORT_W146_PWORD_Pos) /*!< GPIO_PORT W146: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W147 -----------------------------------------
+#define GPIO_PORT_W147_PWORD_Pos 0 /*!< GPIO_PORT W147: PWORD Position */
+#define GPIO_PORT_W147_PWORD_Msk (0xffffffffUL << GPIO_PORT_W147_PWORD_Pos) /*!< GPIO_PORT W147: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W148 -----------------------------------------
+#define GPIO_PORT_W148_PWORD_Pos 0 /*!< GPIO_PORT W148: PWORD Position */
+#define GPIO_PORT_W148_PWORD_Msk (0xffffffffUL << GPIO_PORT_W148_PWORD_Pos) /*!< GPIO_PORT W148: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W149 -----------------------------------------
+#define GPIO_PORT_W149_PWORD_Pos 0 /*!< GPIO_PORT W149: PWORD Position */
+#define GPIO_PORT_W149_PWORD_Msk (0xffffffffUL << GPIO_PORT_W149_PWORD_Pos) /*!< GPIO_PORT W149: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W150 -----------------------------------------
+#define GPIO_PORT_W150_PWORD_Pos 0 /*!< GPIO_PORT W150: PWORD Position */
+#define GPIO_PORT_W150_PWORD_Msk (0xffffffffUL << GPIO_PORT_W150_PWORD_Pos) /*!< GPIO_PORT W150: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W151 -----------------------------------------
+#define GPIO_PORT_W151_PWORD_Pos 0 /*!< GPIO_PORT W151: PWORD Position */
+#define GPIO_PORT_W151_PWORD_Msk (0xffffffffUL << GPIO_PORT_W151_PWORD_Pos) /*!< GPIO_PORT W151: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W152 -----------------------------------------
+#define GPIO_PORT_W152_PWORD_Pos 0 /*!< GPIO_PORT W152: PWORD Position */
+#define GPIO_PORT_W152_PWORD_Msk (0xffffffffUL << GPIO_PORT_W152_PWORD_Pos) /*!< GPIO_PORT W152: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W153 -----------------------------------------
+#define GPIO_PORT_W153_PWORD_Pos 0 /*!< GPIO_PORT W153: PWORD Position */
+#define GPIO_PORT_W153_PWORD_Msk (0xffffffffUL << GPIO_PORT_W153_PWORD_Pos) /*!< GPIO_PORT W153: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W154 -----------------------------------------
+#define GPIO_PORT_W154_PWORD_Pos 0 /*!< GPIO_PORT W154: PWORD Position */
+#define GPIO_PORT_W154_PWORD_Msk (0xffffffffUL << GPIO_PORT_W154_PWORD_Pos) /*!< GPIO_PORT W154: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W155 -----------------------------------------
+#define GPIO_PORT_W155_PWORD_Pos 0 /*!< GPIO_PORT W155: PWORD Position */
+#define GPIO_PORT_W155_PWORD_Msk (0xffffffffUL << GPIO_PORT_W155_PWORD_Pos) /*!< GPIO_PORT W155: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W156 -----------------------------------------
+#define GPIO_PORT_W156_PWORD_Pos 0 /*!< GPIO_PORT W156: PWORD Position */
+#define GPIO_PORT_W156_PWORD_Msk (0xffffffffUL << GPIO_PORT_W156_PWORD_Pos) /*!< GPIO_PORT W156: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W157 -----------------------------------------
+#define GPIO_PORT_W157_PWORD_Pos 0 /*!< GPIO_PORT W157: PWORD Position */
+#define GPIO_PORT_W157_PWORD_Msk (0xffffffffUL << GPIO_PORT_W157_PWORD_Pos) /*!< GPIO_PORT W157: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W158 -----------------------------------------
+#define GPIO_PORT_W158_PWORD_Pos 0 /*!< GPIO_PORT W158: PWORD Position */
+#define GPIO_PORT_W158_PWORD_Msk (0xffffffffUL << GPIO_PORT_W158_PWORD_Pos) /*!< GPIO_PORT W158: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W159 -----------------------------------------
+#define GPIO_PORT_W159_PWORD_Pos 0 /*!< GPIO_PORT W159: PWORD Position */
+#define GPIO_PORT_W159_PWORD_Msk (0xffffffffUL << GPIO_PORT_W159_PWORD_Pos) /*!< GPIO_PORT W159: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W160 -----------------------------------------
+#define GPIO_PORT_W160_PWORD_Pos 0 /*!< GPIO_PORT W160: PWORD Position */
+#define GPIO_PORT_W160_PWORD_Msk (0xffffffffUL << GPIO_PORT_W160_PWORD_Pos) /*!< GPIO_PORT W160: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W161 -----------------------------------------
+#define GPIO_PORT_W161_PWORD_Pos 0 /*!< GPIO_PORT W161: PWORD Position */
+#define GPIO_PORT_W161_PWORD_Msk (0xffffffffUL << GPIO_PORT_W161_PWORD_Pos) /*!< GPIO_PORT W161: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W162 -----------------------------------------
+#define GPIO_PORT_W162_PWORD_Pos 0 /*!< GPIO_PORT W162: PWORD Position */
+#define GPIO_PORT_W162_PWORD_Msk (0xffffffffUL << GPIO_PORT_W162_PWORD_Pos) /*!< GPIO_PORT W162: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W163 -----------------------------------------
+#define GPIO_PORT_W163_PWORD_Pos 0 /*!< GPIO_PORT W163: PWORD Position */
+#define GPIO_PORT_W163_PWORD_Msk (0xffffffffUL << GPIO_PORT_W163_PWORD_Pos) /*!< GPIO_PORT W163: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W164 -----------------------------------------
+#define GPIO_PORT_W164_PWORD_Pos 0 /*!< GPIO_PORT W164: PWORD Position */
+#define GPIO_PORT_W164_PWORD_Msk (0xffffffffUL << GPIO_PORT_W164_PWORD_Pos) /*!< GPIO_PORT W164: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W165 -----------------------------------------
+#define GPIO_PORT_W165_PWORD_Pos 0 /*!< GPIO_PORT W165: PWORD Position */
+#define GPIO_PORT_W165_PWORD_Msk (0xffffffffUL << GPIO_PORT_W165_PWORD_Pos) /*!< GPIO_PORT W165: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W166 -----------------------------------------
+#define GPIO_PORT_W166_PWORD_Pos 0 /*!< GPIO_PORT W166: PWORD Position */
+#define GPIO_PORT_W166_PWORD_Msk (0xffffffffUL << GPIO_PORT_W166_PWORD_Pos) /*!< GPIO_PORT W166: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W167 -----------------------------------------
+#define GPIO_PORT_W167_PWORD_Pos 0 /*!< GPIO_PORT W167: PWORD Position */
+#define GPIO_PORT_W167_PWORD_Msk (0xffffffffUL << GPIO_PORT_W167_PWORD_Pos) /*!< GPIO_PORT W167: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W168 -----------------------------------------
+#define GPIO_PORT_W168_PWORD_Pos 0 /*!< GPIO_PORT W168: PWORD Position */
+#define GPIO_PORT_W168_PWORD_Msk (0xffffffffUL << GPIO_PORT_W168_PWORD_Pos) /*!< GPIO_PORT W168: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W169 -----------------------------------------
+#define GPIO_PORT_W169_PWORD_Pos 0 /*!< GPIO_PORT W169: PWORD Position */
+#define GPIO_PORT_W169_PWORD_Msk (0xffffffffUL << GPIO_PORT_W169_PWORD_Pos) /*!< GPIO_PORT W169: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W170 -----------------------------------------
+#define GPIO_PORT_W170_PWORD_Pos 0 /*!< GPIO_PORT W170: PWORD Position */
+#define GPIO_PORT_W170_PWORD_Msk (0xffffffffUL << GPIO_PORT_W170_PWORD_Pos) /*!< GPIO_PORT W170: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W171 -----------------------------------------
+#define GPIO_PORT_W171_PWORD_Pos 0 /*!< GPIO_PORT W171: PWORD Position */
+#define GPIO_PORT_W171_PWORD_Msk (0xffffffffUL << GPIO_PORT_W171_PWORD_Pos) /*!< GPIO_PORT W171: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W172 -----------------------------------------
+#define GPIO_PORT_W172_PWORD_Pos 0 /*!< GPIO_PORT W172: PWORD Position */
+#define GPIO_PORT_W172_PWORD_Msk (0xffffffffUL << GPIO_PORT_W172_PWORD_Pos) /*!< GPIO_PORT W172: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W173 -----------------------------------------
+#define GPIO_PORT_W173_PWORD_Pos 0 /*!< GPIO_PORT W173: PWORD Position */
+#define GPIO_PORT_W173_PWORD_Msk (0xffffffffUL << GPIO_PORT_W173_PWORD_Pos) /*!< GPIO_PORT W173: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W174 -----------------------------------------
+#define GPIO_PORT_W174_PWORD_Pos 0 /*!< GPIO_PORT W174: PWORD Position */
+#define GPIO_PORT_W174_PWORD_Msk (0xffffffffUL << GPIO_PORT_W174_PWORD_Pos) /*!< GPIO_PORT W174: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W175 -----------------------------------------
+#define GPIO_PORT_W175_PWORD_Pos 0 /*!< GPIO_PORT W175: PWORD Position */
+#define GPIO_PORT_W175_PWORD_Msk (0xffffffffUL << GPIO_PORT_W175_PWORD_Pos) /*!< GPIO_PORT W175: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W176 -----------------------------------------
+#define GPIO_PORT_W176_PWORD_Pos 0 /*!< GPIO_PORT W176: PWORD Position */
+#define GPIO_PORT_W176_PWORD_Msk (0xffffffffUL << GPIO_PORT_W176_PWORD_Pos) /*!< GPIO_PORT W176: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W177 -----------------------------------------
+#define GPIO_PORT_W177_PWORD_Pos 0 /*!< GPIO_PORT W177: PWORD Position */
+#define GPIO_PORT_W177_PWORD_Msk (0xffffffffUL << GPIO_PORT_W177_PWORD_Pos) /*!< GPIO_PORT W177: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W178 -----------------------------------------
+#define GPIO_PORT_W178_PWORD_Pos 0 /*!< GPIO_PORT W178: PWORD Position */
+#define GPIO_PORT_W178_PWORD_Msk (0xffffffffUL << GPIO_PORT_W178_PWORD_Pos) /*!< GPIO_PORT W178: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W179 -----------------------------------------
+#define GPIO_PORT_W179_PWORD_Pos 0 /*!< GPIO_PORT W179: PWORD Position */
+#define GPIO_PORT_W179_PWORD_Msk (0xffffffffUL << GPIO_PORT_W179_PWORD_Pos) /*!< GPIO_PORT W179: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W180 -----------------------------------------
+#define GPIO_PORT_W180_PWORD_Pos 0 /*!< GPIO_PORT W180: PWORD Position */
+#define GPIO_PORT_W180_PWORD_Msk (0xffffffffUL << GPIO_PORT_W180_PWORD_Pos) /*!< GPIO_PORT W180: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W181 -----------------------------------------
+#define GPIO_PORT_W181_PWORD_Pos 0 /*!< GPIO_PORT W181: PWORD Position */
+#define GPIO_PORT_W181_PWORD_Msk (0xffffffffUL << GPIO_PORT_W181_PWORD_Pos) /*!< GPIO_PORT W181: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W182 -----------------------------------------
+#define GPIO_PORT_W182_PWORD_Pos 0 /*!< GPIO_PORT W182: PWORD Position */
+#define GPIO_PORT_W182_PWORD_Msk (0xffffffffUL << GPIO_PORT_W182_PWORD_Pos) /*!< GPIO_PORT W182: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W183 -----------------------------------------
+#define GPIO_PORT_W183_PWORD_Pos 0 /*!< GPIO_PORT W183: PWORD Position */
+#define GPIO_PORT_W183_PWORD_Msk (0xffffffffUL << GPIO_PORT_W183_PWORD_Pos) /*!< GPIO_PORT W183: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W184 -----------------------------------------
+#define GPIO_PORT_W184_PWORD_Pos 0 /*!< GPIO_PORT W184: PWORD Position */
+#define GPIO_PORT_W184_PWORD_Msk (0xffffffffUL << GPIO_PORT_W184_PWORD_Pos) /*!< GPIO_PORT W184: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W185 -----------------------------------------
+#define GPIO_PORT_W185_PWORD_Pos 0 /*!< GPIO_PORT W185: PWORD Position */
+#define GPIO_PORT_W185_PWORD_Msk (0xffffffffUL << GPIO_PORT_W185_PWORD_Pos) /*!< GPIO_PORT W185: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W186 -----------------------------------------
+#define GPIO_PORT_W186_PWORD_Pos 0 /*!< GPIO_PORT W186: PWORD Position */
+#define GPIO_PORT_W186_PWORD_Msk (0xffffffffUL << GPIO_PORT_W186_PWORD_Pos) /*!< GPIO_PORT W186: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W187 -----------------------------------------
+#define GPIO_PORT_W187_PWORD_Pos 0 /*!< GPIO_PORT W187: PWORD Position */
+#define GPIO_PORT_W187_PWORD_Msk (0xffffffffUL << GPIO_PORT_W187_PWORD_Pos) /*!< GPIO_PORT W187: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W188 -----------------------------------------
+#define GPIO_PORT_W188_PWORD_Pos 0 /*!< GPIO_PORT W188: PWORD Position */
+#define GPIO_PORT_W188_PWORD_Msk (0xffffffffUL << GPIO_PORT_W188_PWORD_Pos) /*!< GPIO_PORT W188: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W189 -----------------------------------------
+#define GPIO_PORT_W189_PWORD_Pos 0 /*!< GPIO_PORT W189: PWORD Position */
+#define GPIO_PORT_W189_PWORD_Msk (0xffffffffUL << GPIO_PORT_W189_PWORD_Pos) /*!< GPIO_PORT W189: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W190 -----------------------------------------
+#define GPIO_PORT_W190_PWORD_Pos 0 /*!< GPIO_PORT W190: PWORD Position */
+#define GPIO_PORT_W190_PWORD_Msk (0xffffffffUL << GPIO_PORT_W190_PWORD_Pos) /*!< GPIO_PORT W190: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W191 -----------------------------------------
+#define GPIO_PORT_W191_PWORD_Pos 0 /*!< GPIO_PORT W191: PWORD Position */
+#define GPIO_PORT_W191_PWORD_Msk (0xffffffffUL << GPIO_PORT_W191_PWORD_Pos) /*!< GPIO_PORT W191: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W192 -----------------------------------------
+#define GPIO_PORT_W192_PWORD_Pos 0 /*!< GPIO_PORT W192: PWORD Position */
+#define GPIO_PORT_W192_PWORD_Msk (0xffffffffUL << GPIO_PORT_W192_PWORD_Pos) /*!< GPIO_PORT W192: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W193 -----------------------------------------
+#define GPIO_PORT_W193_PWORD_Pos 0 /*!< GPIO_PORT W193: PWORD Position */
+#define GPIO_PORT_W193_PWORD_Msk (0xffffffffUL << GPIO_PORT_W193_PWORD_Pos) /*!< GPIO_PORT W193: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W194 -----------------------------------------
+#define GPIO_PORT_W194_PWORD_Pos 0 /*!< GPIO_PORT W194: PWORD Position */
+#define GPIO_PORT_W194_PWORD_Msk (0xffffffffUL << GPIO_PORT_W194_PWORD_Pos) /*!< GPIO_PORT W194: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W195 -----------------------------------------
+#define GPIO_PORT_W195_PWORD_Pos 0 /*!< GPIO_PORT W195: PWORD Position */
+#define GPIO_PORT_W195_PWORD_Msk (0xffffffffUL << GPIO_PORT_W195_PWORD_Pos) /*!< GPIO_PORT W195: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W196 -----------------------------------------
+#define GPIO_PORT_W196_PWORD_Pos 0 /*!< GPIO_PORT W196: PWORD Position */
+#define GPIO_PORT_W196_PWORD_Msk (0xffffffffUL << GPIO_PORT_W196_PWORD_Pos) /*!< GPIO_PORT W196: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W197 -----------------------------------------
+#define GPIO_PORT_W197_PWORD_Pos 0 /*!< GPIO_PORT W197: PWORD Position */
+#define GPIO_PORT_W197_PWORD_Msk (0xffffffffUL << GPIO_PORT_W197_PWORD_Pos) /*!< GPIO_PORT W197: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W198 -----------------------------------------
+#define GPIO_PORT_W198_PWORD_Pos 0 /*!< GPIO_PORT W198: PWORD Position */
+#define GPIO_PORT_W198_PWORD_Msk (0xffffffffUL << GPIO_PORT_W198_PWORD_Pos) /*!< GPIO_PORT W198: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W199 -----------------------------------------
+#define GPIO_PORT_W199_PWORD_Pos 0 /*!< GPIO_PORT W199: PWORD Position */
+#define GPIO_PORT_W199_PWORD_Msk (0xffffffffUL << GPIO_PORT_W199_PWORD_Pos) /*!< GPIO_PORT W199: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W200 -----------------------------------------
+#define GPIO_PORT_W200_PWORD_Pos 0 /*!< GPIO_PORT W200: PWORD Position */
+#define GPIO_PORT_W200_PWORD_Msk (0xffffffffUL << GPIO_PORT_W200_PWORD_Pos) /*!< GPIO_PORT W200: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W201 -----------------------------------------
+#define GPIO_PORT_W201_PWORD_Pos 0 /*!< GPIO_PORT W201: PWORD Position */
+#define GPIO_PORT_W201_PWORD_Msk (0xffffffffUL << GPIO_PORT_W201_PWORD_Pos) /*!< GPIO_PORT W201: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W202 -----------------------------------------
+#define GPIO_PORT_W202_PWORD_Pos 0 /*!< GPIO_PORT W202: PWORD Position */
+#define GPIO_PORT_W202_PWORD_Msk (0xffffffffUL << GPIO_PORT_W202_PWORD_Pos) /*!< GPIO_PORT W202: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W203 -----------------------------------------
+#define GPIO_PORT_W203_PWORD_Pos 0 /*!< GPIO_PORT W203: PWORD Position */
+#define GPIO_PORT_W203_PWORD_Msk (0xffffffffUL << GPIO_PORT_W203_PWORD_Pos) /*!< GPIO_PORT W203: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W204 -----------------------------------------
+#define GPIO_PORT_W204_PWORD_Pos 0 /*!< GPIO_PORT W204: PWORD Position */
+#define GPIO_PORT_W204_PWORD_Msk (0xffffffffUL << GPIO_PORT_W204_PWORD_Pos) /*!< GPIO_PORT W204: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W205 -----------------------------------------
+#define GPIO_PORT_W205_PWORD_Pos 0 /*!< GPIO_PORT W205: PWORD Position */
+#define GPIO_PORT_W205_PWORD_Msk (0xffffffffUL << GPIO_PORT_W205_PWORD_Pos) /*!< GPIO_PORT W205: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W206 -----------------------------------------
+#define GPIO_PORT_W206_PWORD_Pos 0 /*!< GPIO_PORT W206: PWORD Position */
+#define GPIO_PORT_W206_PWORD_Msk (0xffffffffUL << GPIO_PORT_W206_PWORD_Pos) /*!< GPIO_PORT W206: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W207 -----------------------------------------
+#define GPIO_PORT_W207_PWORD_Pos 0 /*!< GPIO_PORT W207: PWORD Position */
+#define GPIO_PORT_W207_PWORD_Msk (0xffffffffUL << GPIO_PORT_W207_PWORD_Pos) /*!< GPIO_PORT W207: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W208 -----------------------------------------
+#define GPIO_PORT_W208_PWORD_Pos 0 /*!< GPIO_PORT W208: PWORD Position */
+#define GPIO_PORT_W208_PWORD_Msk (0xffffffffUL << GPIO_PORT_W208_PWORD_Pos) /*!< GPIO_PORT W208: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W209 -----------------------------------------
+#define GPIO_PORT_W209_PWORD_Pos 0 /*!< GPIO_PORT W209: PWORD Position */
+#define GPIO_PORT_W209_PWORD_Msk (0xffffffffUL << GPIO_PORT_W209_PWORD_Pos) /*!< GPIO_PORT W209: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W210 -----------------------------------------
+#define GPIO_PORT_W210_PWORD_Pos 0 /*!< GPIO_PORT W210: PWORD Position */
+#define GPIO_PORT_W210_PWORD_Msk (0xffffffffUL << GPIO_PORT_W210_PWORD_Pos) /*!< GPIO_PORT W210: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W211 -----------------------------------------
+#define GPIO_PORT_W211_PWORD_Pos 0 /*!< GPIO_PORT W211: PWORD Position */
+#define GPIO_PORT_W211_PWORD_Msk (0xffffffffUL << GPIO_PORT_W211_PWORD_Pos) /*!< GPIO_PORT W211: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W212 -----------------------------------------
+#define GPIO_PORT_W212_PWORD_Pos 0 /*!< GPIO_PORT W212: PWORD Position */
+#define GPIO_PORT_W212_PWORD_Msk (0xffffffffUL << GPIO_PORT_W212_PWORD_Pos) /*!< GPIO_PORT W212: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W213 -----------------------------------------
+#define GPIO_PORT_W213_PWORD_Pos 0 /*!< GPIO_PORT W213: PWORD Position */
+#define GPIO_PORT_W213_PWORD_Msk (0xffffffffUL << GPIO_PORT_W213_PWORD_Pos) /*!< GPIO_PORT W213: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W214 -----------------------------------------
+#define GPIO_PORT_W214_PWORD_Pos 0 /*!< GPIO_PORT W214: PWORD Position */
+#define GPIO_PORT_W214_PWORD_Msk (0xffffffffUL << GPIO_PORT_W214_PWORD_Pos) /*!< GPIO_PORT W214: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W215 -----------------------------------------
+#define GPIO_PORT_W215_PWORD_Pos 0 /*!< GPIO_PORT W215: PWORD Position */
+#define GPIO_PORT_W215_PWORD_Msk (0xffffffffUL << GPIO_PORT_W215_PWORD_Pos) /*!< GPIO_PORT W215: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W216 -----------------------------------------
+#define GPIO_PORT_W216_PWORD_Pos 0 /*!< GPIO_PORT W216: PWORD Position */
+#define GPIO_PORT_W216_PWORD_Msk (0xffffffffUL << GPIO_PORT_W216_PWORD_Pos) /*!< GPIO_PORT W216: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W217 -----------------------------------------
+#define GPIO_PORT_W217_PWORD_Pos 0 /*!< GPIO_PORT W217: PWORD Position */
+#define GPIO_PORT_W217_PWORD_Msk (0xffffffffUL << GPIO_PORT_W217_PWORD_Pos) /*!< GPIO_PORT W217: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W218 -----------------------------------------
+#define GPIO_PORT_W218_PWORD_Pos 0 /*!< GPIO_PORT W218: PWORD Position */
+#define GPIO_PORT_W218_PWORD_Msk (0xffffffffUL << GPIO_PORT_W218_PWORD_Pos) /*!< GPIO_PORT W218: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W219 -----------------------------------------
+#define GPIO_PORT_W219_PWORD_Pos 0 /*!< GPIO_PORT W219: PWORD Position */
+#define GPIO_PORT_W219_PWORD_Msk (0xffffffffUL << GPIO_PORT_W219_PWORD_Pos) /*!< GPIO_PORT W219: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W220 -----------------------------------------
+#define GPIO_PORT_W220_PWORD_Pos 0 /*!< GPIO_PORT W220: PWORD Position */
+#define GPIO_PORT_W220_PWORD_Msk (0xffffffffUL << GPIO_PORT_W220_PWORD_Pos) /*!< GPIO_PORT W220: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W221 -----------------------------------------
+#define GPIO_PORT_W221_PWORD_Pos 0 /*!< GPIO_PORT W221: PWORD Position */
+#define GPIO_PORT_W221_PWORD_Msk (0xffffffffUL << GPIO_PORT_W221_PWORD_Pos) /*!< GPIO_PORT W221: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W222 -----------------------------------------
+#define GPIO_PORT_W222_PWORD_Pos 0 /*!< GPIO_PORT W222: PWORD Position */
+#define GPIO_PORT_W222_PWORD_Msk (0xffffffffUL << GPIO_PORT_W222_PWORD_Pos) /*!< GPIO_PORT W222: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W223 -----------------------------------------
+#define GPIO_PORT_W223_PWORD_Pos 0 /*!< GPIO_PORT W223: PWORD Position */
+#define GPIO_PORT_W223_PWORD_Msk (0xffffffffUL << GPIO_PORT_W223_PWORD_Pos) /*!< GPIO_PORT W223: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W224 -----------------------------------------
+#define GPIO_PORT_W224_PWORD_Pos 0 /*!< GPIO_PORT W224: PWORD Position */
+#define GPIO_PORT_W224_PWORD_Msk (0xffffffffUL << GPIO_PORT_W224_PWORD_Pos) /*!< GPIO_PORT W224: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W225 -----------------------------------------
+#define GPIO_PORT_W225_PWORD_Pos 0 /*!< GPIO_PORT W225: PWORD Position */
+#define GPIO_PORT_W225_PWORD_Msk (0xffffffffUL << GPIO_PORT_W225_PWORD_Pos) /*!< GPIO_PORT W225: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W226 -----------------------------------------
+#define GPIO_PORT_W226_PWORD_Pos 0 /*!< GPIO_PORT W226: PWORD Position */
+#define GPIO_PORT_W226_PWORD_Msk (0xffffffffUL << GPIO_PORT_W226_PWORD_Pos) /*!< GPIO_PORT W226: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W227 -----------------------------------------
+#define GPIO_PORT_W227_PWORD_Pos 0 /*!< GPIO_PORT W227: PWORD Position */
+#define GPIO_PORT_W227_PWORD_Msk (0xffffffffUL << GPIO_PORT_W227_PWORD_Pos) /*!< GPIO_PORT W227: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W228 -----------------------------------------
+#define GPIO_PORT_W228_PWORD_Pos 0 /*!< GPIO_PORT W228: PWORD Position */
+#define GPIO_PORT_W228_PWORD_Msk (0xffffffffUL << GPIO_PORT_W228_PWORD_Pos) /*!< GPIO_PORT W228: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W229 -----------------------------------------
+#define GPIO_PORT_W229_PWORD_Pos 0 /*!< GPIO_PORT W229: PWORD Position */
+#define GPIO_PORT_W229_PWORD_Msk (0xffffffffUL << GPIO_PORT_W229_PWORD_Pos) /*!< GPIO_PORT W229: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W230 -----------------------------------------
+#define GPIO_PORT_W230_PWORD_Pos 0 /*!< GPIO_PORT W230: PWORD Position */
+#define GPIO_PORT_W230_PWORD_Msk (0xffffffffUL << GPIO_PORT_W230_PWORD_Pos) /*!< GPIO_PORT W230: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W231 -----------------------------------------
+#define GPIO_PORT_W231_PWORD_Pos 0 /*!< GPIO_PORT W231: PWORD Position */
+#define GPIO_PORT_W231_PWORD_Msk (0xffffffffUL << GPIO_PORT_W231_PWORD_Pos) /*!< GPIO_PORT W231: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W232 -----------------------------------------
+#define GPIO_PORT_W232_PWORD_Pos 0 /*!< GPIO_PORT W232: PWORD Position */
+#define GPIO_PORT_W232_PWORD_Msk (0xffffffffUL << GPIO_PORT_W232_PWORD_Pos) /*!< GPIO_PORT W232: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W233 -----------------------------------------
+#define GPIO_PORT_W233_PWORD_Pos 0 /*!< GPIO_PORT W233: PWORD Position */
+#define GPIO_PORT_W233_PWORD_Msk (0xffffffffUL << GPIO_PORT_W233_PWORD_Pos) /*!< GPIO_PORT W233: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W234 -----------------------------------------
+#define GPIO_PORT_W234_PWORD_Pos 0 /*!< GPIO_PORT W234: PWORD Position */
+#define GPIO_PORT_W234_PWORD_Msk (0xffffffffUL << GPIO_PORT_W234_PWORD_Pos) /*!< GPIO_PORT W234: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W235 -----------------------------------------
+#define GPIO_PORT_W235_PWORD_Pos 0 /*!< GPIO_PORT W235: PWORD Position */
+#define GPIO_PORT_W235_PWORD_Msk (0xffffffffUL << GPIO_PORT_W235_PWORD_Pos) /*!< GPIO_PORT W235: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W236 -----------------------------------------
+#define GPIO_PORT_W236_PWORD_Pos 0 /*!< GPIO_PORT W236: PWORD Position */
+#define GPIO_PORT_W236_PWORD_Msk (0xffffffffUL << GPIO_PORT_W236_PWORD_Pos) /*!< GPIO_PORT W236: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W237 -----------------------------------------
+#define GPIO_PORT_W237_PWORD_Pos 0 /*!< GPIO_PORT W237: PWORD Position */
+#define GPIO_PORT_W237_PWORD_Msk (0xffffffffUL << GPIO_PORT_W237_PWORD_Pos) /*!< GPIO_PORT W237: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W238 -----------------------------------------
+#define GPIO_PORT_W238_PWORD_Pos 0 /*!< GPIO_PORT W238: PWORD Position */
+#define GPIO_PORT_W238_PWORD_Msk (0xffffffffUL << GPIO_PORT_W238_PWORD_Pos) /*!< GPIO_PORT W238: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W239 -----------------------------------------
+#define GPIO_PORT_W239_PWORD_Pos 0 /*!< GPIO_PORT W239: PWORD Position */
+#define GPIO_PORT_W239_PWORD_Msk (0xffffffffUL << GPIO_PORT_W239_PWORD_Pos) /*!< GPIO_PORT W239: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W240 -----------------------------------------
+#define GPIO_PORT_W240_PWORD_Pos 0 /*!< GPIO_PORT W240: PWORD Position */
+#define GPIO_PORT_W240_PWORD_Msk (0xffffffffUL << GPIO_PORT_W240_PWORD_Pos) /*!< GPIO_PORT W240: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W241 -----------------------------------------
+#define GPIO_PORT_W241_PWORD_Pos 0 /*!< GPIO_PORT W241: PWORD Position */
+#define GPIO_PORT_W241_PWORD_Msk (0xffffffffUL << GPIO_PORT_W241_PWORD_Pos) /*!< GPIO_PORT W241: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W242 -----------------------------------------
+#define GPIO_PORT_W242_PWORD_Pos 0 /*!< GPIO_PORT W242: PWORD Position */
+#define GPIO_PORT_W242_PWORD_Msk (0xffffffffUL << GPIO_PORT_W242_PWORD_Pos) /*!< GPIO_PORT W242: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W243 -----------------------------------------
+#define GPIO_PORT_W243_PWORD_Pos 0 /*!< GPIO_PORT W243: PWORD Position */
+#define GPIO_PORT_W243_PWORD_Msk (0xffffffffUL << GPIO_PORT_W243_PWORD_Pos) /*!< GPIO_PORT W243: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W244 -----------------------------------------
+#define GPIO_PORT_W244_PWORD_Pos 0 /*!< GPIO_PORT W244: PWORD Position */
+#define GPIO_PORT_W244_PWORD_Msk (0xffffffffUL << GPIO_PORT_W244_PWORD_Pos) /*!< GPIO_PORT W244: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W245 -----------------------------------------
+#define GPIO_PORT_W245_PWORD_Pos 0 /*!< GPIO_PORT W245: PWORD Position */
+#define GPIO_PORT_W245_PWORD_Msk (0xffffffffUL << GPIO_PORT_W245_PWORD_Pos) /*!< GPIO_PORT W245: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W246 -----------------------------------------
+#define GPIO_PORT_W246_PWORD_Pos 0 /*!< GPIO_PORT W246: PWORD Position */
+#define GPIO_PORT_W246_PWORD_Msk (0xffffffffUL << GPIO_PORT_W246_PWORD_Pos) /*!< GPIO_PORT W246: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W247 -----------------------------------------
+#define GPIO_PORT_W247_PWORD_Pos 0 /*!< GPIO_PORT W247: PWORD Position */
+#define GPIO_PORT_W247_PWORD_Msk (0xffffffffUL << GPIO_PORT_W247_PWORD_Pos) /*!< GPIO_PORT W247: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W248 -----------------------------------------
+#define GPIO_PORT_W248_PWORD_Pos 0 /*!< GPIO_PORT W248: PWORD Position */
+#define GPIO_PORT_W248_PWORD_Msk (0xffffffffUL << GPIO_PORT_W248_PWORD_Pos) /*!< GPIO_PORT W248: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W249 -----------------------------------------
+#define GPIO_PORT_W249_PWORD_Pos 0 /*!< GPIO_PORT W249: PWORD Position */
+#define GPIO_PORT_W249_PWORD_Msk (0xffffffffUL << GPIO_PORT_W249_PWORD_Pos) /*!< GPIO_PORT W249: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W250 -----------------------------------------
+#define GPIO_PORT_W250_PWORD_Pos 0 /*!< GPIO_PORT W250: PWORD Position */
+#define GPIO_PORT_W250_PWORD_Msk (0xffffffffUL << GPIO_PORT_W250_PWORD_Pos) /*!< GPIO_PORT W250: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W251 -----------------------------------------
+#define GPIO_PORT_W251_PWORD_Pos 0 /*!< GPIO_PORT W251: PWORD Position */
+#define GPIO_PORT_W251_PWORD_Msk (0xffffffffUL << GPIO_PORT_W251_PWORD_Pos) /*!< GPIO_PORT W251: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W252 -----------------------------------------
+#define GPIO_PORT_W252_PWORD_Pos 0 /*!< GPIO_PORT W252: PWORD Position */
+#define GPIO_PORT_W252_PWORD_Msk (0xffffffffUL << GPIO_PORT_W252_PWORD_Pos) /*!< GPIO_PORT W252: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W253 -----------------------------------------
+#define GPIO_PORT_W253_PWORD_Pos 0 /*!< GPIO_PORT W253: PWORD Position */
+#define GPIO_PORT_W253_PWORD_Msk (0xffffffffUL << GPIO_PORT_W253_PWORD_Pos) /*!< GPIO_PORT W253: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W254 -----------------------------------------
+#define GPIO_PORT_W254_PWORD_Pos 0 /*!< GPIO_PORT W254: PWORD Position */
+#define GPIO_PORT_W254_PWORD_Msk (0xffffffffUL << GPIO_PORT_W254_PWORD_Pos) /*!< GPIO_PORT W254: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_W255 -----------------------------------------
+#define GPIO_PORT_W255_PWORD_Pos 0 /*!< GPIO_PORT W255: PWORD Position */
+#define GPIO_PORT_W255_PWORD_Msk (0xffffffffUL << GPIO_PORT_W255_PWORD_Pos) /*!< GPIO_PORT W255: PWORD Mask */
+
+// ------------------------------------- GPIO_PORT_DIR0 -----------------------------------------
+#define GPIO_PORT_DIR0_DIRP0_Pos 0 /*!< GPIO_PORT DIR0: DIRP0 Position */
+#define GPIO_PORT_DIR0_DIRP0_Msk (0x01UL << GPIO_PORT_DIR0_DIRP0_Pos) /*!< GPIO_PORT DIR0: DIRP0 Mask */
+#define GPIO_PORT_DIR0_DIRP1_Pos 1 /*!< GPIO_PORT DIR0: DIRP1 Position */
+#define GPIO_PORT_DIR0_DIRP1_Msk (0x01UL << GPIO_PORT_DIR0_DIRP1_Pos) /*!< GPIO_PORT DIR0: DIRP1 Mask */
+#define GPIO_PORT_DIR0_DIRP2_Pos 2 /*!< GPIO_PORT DIR0: DIRP2 Position */
+#define GPIO_PORT_DIR0_DIRP2_Msk (0x01UL << GPIO_PORT_DIR0_DIRP2_Pos) /*!< GPIO_PORT DIR0: DIRP2 Mask */
+#define GPIO_PORT_DIR0_DIRP3_Pos 3 /*!< GPIO_PORT DIR0: DIRP3 Position */
+#define GPIO_PORT_DIR0_DIRP3_Msk (0x01UL << GPIO_PORT_DIR0_DIRP3_Pos) /*!< GPIO_PORT DIR0: DIRP3 Mask */
+#define GPIO_PORT_DIR0_DIRP4_Pos 4 /*!< GPIO_PORT DIR0: DIRP4 Position */
+#define GPIO_PORT_DIR0_DIRP4_Msk (0x01UL << GPIO_PORT_DIR0_DIRP4_Pos) /*!< GPIO_PORT DIR0: DIRP4 Mask */
+#define GPIO_PORT_DIR0_DIRP5_Pos 5 /*!< GPIO_PORT DIR0: DIRP5 Position */
+#define GPIO_PORT_DIR0_DIRP5_Msk (0x01UL << GPIO_PORT_DIR0_DIRP5_Pos) /*!< GPIO_PORT DIR0: DIRP5 Mask */
+#define GPIO_PORT_DIR0_DIRP6_Pos 6 /*!< GPIO_PORT DIR0: DIRP6 Position */
+#define GPIO_PORT_DIR0_DIRP6_Msk (0x01UL << GPIO_PORT_DIR0_DIRP6_Pos) /*!< GPIO_PORT DIR0: DIRP6 Mask */
+#define GPIO_PORT_DIR0_DIRP7_Pos 7 /*!< GPIO_PORT DIR0: DIRP7 Position */
+#define GPIO_PORT_DIR0_DIRP7_Msk (0x01UL << GPIO_PORT_DIR0_DIRP7_Pos) /*!< GPIO_PORT DIR0: DIRP7 Mask */
+#define GPIO_PORT_DIR0_DIRP8_Pos 8 /*!< GPIO_PORT DIR0: DIRP8 Position */
+#define GPIO_PORT_DIR0_DIRP8_Msk (0x01UL << GPIO_PORT_DIR0_DIRP8_Pos) /*!< GPIO_PORT DIR0: DIRP8 Mask */
+#define GPIO_PORT_DIR0_DIRP9_Pos 9 /*!< GPIO_PORT DIR0: DIRP9 Position */
+#define GPIO_PORT_DIR0_DIRP9_Msk (0x01UL << GPIO_PORT_DIR0_DIRP9_Pos) /*!< GPIO_PORT DIR0: DIRP9 Mask */
+#define GPIO_PORT_DIR0_DIRP10_Pos 10 /*!< GPIO_PORT DIR0: DIRP10 Position */
+#define GPIO_PORT_DIR0_DIRP10_Msk (0x01UL << GPIO_PORT_DIR0_DIRP10_Pos) /*!< GPIO_PORT DIR0: DIRP10 Mask */
+#define GPIO_PORT_DIR0_DIRP11_Pos 11 /*!< GPIO_PORT DIR0: DIRP11 Position */
+#define GPIO_PORT_DIR0_DIRP11_Msk (0x01UL << GPIO_PORT_DIR0_DIRP11_Pos) /*!< GPIO_PORT DIR0: DIRP11 Mask */
+#define GPIO_PORT_DIR0_DIRP12_Pos 12 /*!< GPIO_PORT DIR0: DIRP12 Position */
+#define GPIO_PORT_DIR0_DIRP12_Msk (0x01UL << GPIO_PORT_DIR0_DIRP12_Pos) /*!< GPIO_PORT DIR0: DIRP12 Mask */
+#define GPIO_PORT_DIR0_DIRP13_Pos 13 /*!< GPIO_PORT DIR0: DIRP13 Position */
+#define GPIO_PORT_DIR0_DIRP13_Msk (0x01UL << GPIO_PORT_DIR0_DIRP13_Pos) /*!< GPIO_PORT DIR0: DIRP13 Mask */
+#define GPIO_PORT_DIR0_DIRP14_Pos 14 /*!< GPIO_PORT DIR0: DIRP14 Position */
+#define GPIO_PORT_DIR0_DIRP14_Msk (0x01UL << GPIO_PORT_DIR0_DIRP14_Pos) /*!< GPIO_PORT DIR0: DIRP14 Mask */
+#define GPIO_PORT_DIR0_DIRP15_Pos 15 /*!< GPIO_PORT DIR0: DIRP15 Position */
+#define GPIO_PORT_DIR0_DIRP15_Msk (0x01UL << GPIO_PORT_DIR0_DIRP15_Pos) /*!< GPIO_PORT DIR0: DIRP15 Mask */
+#define GPIO_PORT_DIR0_DIRP16_Pos 16 /*!< GPIO_PORT DIR0: DIRP16 Position */
+#define GPIO_PORT_DIR0_DIRP16_Msk (0x01UL << GPIO_PORT_DIR0_DIRP16_Pos) /*!< GPIO_PORT DIR0: DIRP16 Mask */
+#define GPIO_PORT_DIR0_DIRP17_Pos 17 /*!< GPIO_PORT DIR0: DIRP17 Position */
+#define GPIO_PORT_DIR0_DIRP17_Msk (0x01UL << GPIO_PORT_DIR0_DIRP17_Pos) /*!< GPIO_PORT DIR0: DIRP17 Mask */
+#define GPIO_PORT_DIR0_DIRP18_Pos 18 /*!< GPIO_PORT DIR0: DIRP18 Position */
+#define GPIO_PORT_DIR0_DIRP18_Msk (0x01UL << GPIO_PORT_DIR0_DIRP18_Pos) /*!< GPIO_PORT DIR0: DIRP18 Mask */
+#define GPIO_PORT_DIR0_DIRP19_Pos 19 /*!< GPIO_PORT DIR0: DIRP19 Position */
+#define GPIO_PORT_DIR0_DIRP19_Msk (0x01UL << GPIO_PORT_DIR0_DIRP19_Pos) /*!< GPIO_PORT DIR0: DIRP19 Mask */
+#define GPIO_PORT_DIR0_DIRP20_Pos 20 /*!< GPIO_PORT DIR0: DIRP20 Position */
+#define GPIO_PORT_DIR0_DIRP20_Msk (0x01UL << GPIO_PORT_DIR0_DIRP20_Pos) /*!< GPIO_PORT DIR0: DIRP20 Mask */
+#define GPIO_PORT_DIR0_DIRP21_Pos 21 /*!< GPIO_PORT DIR0: DIRP21 Position */
+#define GPIO_PORT_DIR0_DIRP21_Msk (0x01UL << GPIO_PORT_DIR0_DIRP21_Pos) /*!< GPIO_PORT DIR0: DIRP21 Mask */
+#define GPIO_PORT_DIR0_DIRP22_Pos 22 /*!< GPIO_PORT DIR0: DIRP22 Position */
+#define GPIO_PORT_DIR0_DIRP22_Msk (0x01UL << GPIO_PORT_DIR0_DIRP22_Pos) /*!< GPIO_PORT DIR0: DIRP22 Mask */
+#define GPIO_PORT_DIR0_DIRP23_Pos 23 /*!< GPIO_PORT DIR0: DIRP23 Position */
+#define GPIO_PORT_DIR0_DIRP23_Msk (0x01UL << GPIO_PORT_DIR0_DIRP23_Pos) /*!< GPIO_PORT DIR0: DIRP23 Mask */
+#define GPIO_PORT_DIR0_DIRP24_Pos 24 /*!< GPIO_PORT DIR0: DIRP24 Position */
+#define GPIO_PORT_DIR0_DIRP24_Msk (0x01UL << GPIO_PORT_DIR0_DIRP24_Pos) /*!< GPIO_PORT DIR0: DIRP24 Mask */
+#define GPIO_PORT_DIR0_DIRP25_Pos 25 /*!< GPIO_PORT DIR0: DIRP25 Position */
+#define GPIO_PORT_DIR0_DIRP25_Msk (0x01UL << GPIO_PORT_DIR0_DIRP25_Pos) /*!< GPIO_PORT DIR0: DIRP25 Mask */
+#define GPIO_PORT_DIR0_DIRP26_Pos 26 /*!< GPIO_PORT DIR0: DIRP26 Position */
+#define GPIO_PORT_DIR0_DIRP26_Msk (0x01UL << GPIO_PORT_DIR0_DIRP26_Pos) /*!< GPIO_PORT DIR0: DIRP26 Mask */
+#define GPIO_PORT_DIR0_DIRP27_Pos 27 /*!< GPIO_PORT DIR0: DIRP27 Position */
+#define GPIO_PORT_DIR0_DIRP27_Msk (0x01UL << GPIO_PORT_DIR0_DIRP27_Pos) /*!< GPIO_PORT DIR0: DIRP27 Mask */
+#define GPIO_PORT_DIR0_DIRP28_Pos 28 /*!< GPIO_PORT DIR0: DIRP28 Position */
+#define GPIO_PORT_DIR0_DIRP28_Msk (0x01UL << GPIO_PORT_DIR0_DIRP28_Pos) /*!< GPIO_PORT DIR0: DIRP28 Mask */
+#define GPIO_PORT_DIR0_DIRP29_Pos 29 /*!< GPIO_PORT DIR0: DIRP29 Position */
+#define GPIO_PORT_DIR0_DIRP29_Msk (0x01UL << GPIO_PORT_DIR0_DIRP29_Pos) /*!< GPIO_PORT DIR0: DIRP29 Mask */
+#define GPIO_PORT_DIR0_DIRP30_Pos 30 /*!< GPIO_PORT DIR0: DIRP30 Position */
+#define GPIO_PORT_DIR0_DIRP30_Msk (0x01UL << GPIO_PORT_DIR0_DIRP30_Pos) /*!< GPIO_PORT DIR0: DIRP30 Mask */
+#define GPIO_PORT_DIR0_DIRP31_Pos 31 /*!< GPIO_PORT DIR0: DIRP31 Position */
+#define GPIO_PORT_DIR0_DIRP31_Msk (0x01UL << GPIO_PORT_DIR0_DIRP31_Pos) /*!< GPIO_PORT DIR0: DIRP31 Mask */
+
+// ------------------------------------- GPIO_PORT_DIR1 -----------------------------------------
+#define GPIO_PORT_DIR1_DIRP0_Pos 0 /*!< GPIO_PORT DIR1: DIRP0 Position */
+#define GPIO_PORT_DIR1_DIRP0_Msk (0x01UL << GPIO_PORT_DIR1_DIRP0_Pos) /*!< GPIO_PORT DIR1: DIRP0 Mask */
+#define GPIO_PORT_DIR1_DIRP1_Pos 1 /*!< GPIO_PORT DIR1: DIRP1 Position */
+#define GPIO_PORT_DIR1_DIRP1_Msk (0x01UL << GPIO_PORT_DIR1_DIRP1_Pos) /*!< GPIO_PORT DIR1: DIRP1 Mask */
+#define GPIO_PORT_DIR1_DIRP2_Pos 2 /*!< GPIO_PORT DIR1: DIRP2 Position */
+#define GPIO_PORT_DIR1_DIRP2_Msk (0x01UL << GPIO_PORT_DIR1_DIRP2_Pos) /*!< GPIO_PORT DIR1: DIRP2 Mask */
+#define GPIO_PORT_DIR1_DIRP3_Pos 3 /*!< GPIO_PORT DIR1: DIRP3 Position */
+#define GPIO_PORT_DIR1_DIRP3_Msk (0x01UL << GPIO_PORT_DIR1_DIRP3_Pos) /*!< GPIO_PORT DIR1: DIRP3 Mask */
+#define GPIO_PORT_DIR1_DIRP4_Pos 4 /*!< GPIO_PORT DIR1: DIRP4 Position */
+#define GPIO_PORT_DIR1_DIRP4_Msk (0x01UL << GPIO_PORT_DIR1_DIRP4_Pos) /*!< GPIO_PORT DIR1: DIRP4 Mask */
+#define GPIO_PORT_DIR1_DIRP5_Pos 5 /*!< GPIO_PORT DIR1: DIRP5 Position */
+#define GPIO_PORT_DIR1_DIRP5_Msk (0x01UL << GPIO_PORT_DIR1_DIRP5_Pos) /*!< GPIO_PORT DIR1: DIRP5 Mask */
+#define GPIO_PORT_DIR1_DIRP6_Pos 6 /*!< GPIO_PORT DIR1: DIRP6 Position */
+#define GPIO_PORT_DIR1_DIRP6_Msk (0x01UL << GPIO_PORT_DIR1_DIRP6_Pos) /*!< GPIO_PORT DIR1: DIRP6 Mask */
+#define GPIO_PORT_DIR1_DIRP7_Pos 7 /*!< GPIO_PORT DIR1: DIRP7 Position */
+#define GPIO_PORT_DIR1_DIRP7_Msk (0x01UL << GPIO_PORT_DIR1_DIRP7_Pos) /*!< GPIO_PORT DIR1: DIRP7 Mask */
+#define GPIO_PORT_DIR1_DIRP8_Pos 8 /*!< GPIO_PORT DIR1: DIRP8 Position */
+#define GPIO_PORT_DIR1_DIRP8_Msk (0x01UL << GPIO_PORT_DIR1_DIRP8_Pos) /*!< GPIO_PORT DIR1: DIRP8 Mask */
+#define GPIO_PORT_DIR1_DIRP9_Pos 9 /*!< GPIO_PORT DIR1: DIRP9 Position */
+#define GPIO_PORT_DIR1_DIRP9_Msk (0x01UL << GPIO_PORT_DIR1_DIRP9_Pos) /*!< GPIO_PORT DIR1: DIRP9 Mask */
+#define GPIO_PORT_DIR1_DIRP10_Pos 10 /*!< GPIO_PORT DIR1: DIRP10 Position */
+#define GPIO_PORT_DIR1_DIRP10_Msk (0x01UL << GPIO_PORT_DIR1_DIRP10_Pos) /*!< GPIO_PORT DIR1: DIRP10 Mask */
+#define GPIO_PORT_DIR1_DIRP11_Pos 11 /*!< GPIO_PORT DIR1: DIRP11 Position */
+#define GPIO_PORT_DIR1_DIRP11_Msk (0x01UL << GPIO_PORT_DIR1_DIRP11_Pos) /*!< GPIO_PORT DIR1: DIRP11 Mask */
+#define GPIO_PORT_DIR1_DIRP12_Pos 12 /*!< GPIO_PORT DIR1: DIRP12 Position */
+#define GPIO_PORT_DIR1_DIRP12_Msk (0x01UL << GPIO_PORT_DIR1_DIRP12_Pos) /*!< GPIO_PORT DIR1: DIRP12 Mask */
+#define GPIO_PORT_DIR1_DIRP13_Pos 13 /*!< GPIO_PORT DIR1: DIRP13 Position */
+#define GPIO_PORT_DIR1_DIRP13_Msk (0x01UL << GPIO_PORT_DIR1_DIRP13_Pos) /*!< GPIO_PORT DIR1: DIRP13 Mask */
+#define GPIO_PORT_DIR1_DIRP14_Pos 14 /*!< GPIO_PORT DIR1: DIRP14 Position */
+#define GPIO_PORT_DIR1_DIRP14_Msk (0x01UL << GPIO_PORT_DIR1_DIRP14_Pos) /*!< GPIO_PORT DIR1: DIRP14 Mask */
+#define GPIO_PORT_DIR1_DIRP15_Pos 15 /*!< GPIO_PORT DIR1: DIRP15 Position */
+#define GPIO_PORT_DIR1_DIRP15_Msk (0x01UL << GPIO_PORT_DIR1_DIRP15_Pos) /*!< GPIO_PORT DIR1: DIRP15 Mask */
+#define GPIO_PORT_DIR1_DIRP16_Pos 16 /*!< GPIO_PORT DIR1: DIRP16 Position */
+#define GPIO_PORT_DIR1_DIRP16_Msk (0x01UL << GPIO_PORT_DIR1_DIRP16_Pos) /*!< GPIO_PORT DIR1: DIRP16 Mask */
+#define GPIO_PORT_DIR1_DIRP17_Pos 17 /*!< GPIO_PORT DIR1: DIRP17 Position */
+#define GPIO_PORT_DIR1_DIRP17_Msk (0x01UL << GPIO_PORT_DIR1_DIRP17_Pos) /*!< GPIO_PORT DIR1: DIRP17 Mask */
+#define GPIO_PORT_DIR1_DIRP18_Pos 18 /*!< GPIO_PORT DIR1: DIRP18 Position */
+#define GPIO_PORT_DIR1_DIRP18_Msk (0x01UL << GPIO_PORT_DIR1_DIRP18_Pos) /*!< GPIO_PORT DIR1: DIRP18 Mask */
+#define GPIO_PORT_DIR1_DIRP19_Pos 19 /*!< GPIO_PORT DIR1: DIRP19 Position */
+#define GPIO_PORT_DIR1_DIRP19_Msk (0x01UL << GPIO_PORT_DIR1_DIRP19_Pos) /*!< GPIO_PORT DIR1: DIRP19 Mask */
+#define GPIO_PORT_DIR1_DIRP20_Pos 20 /*!< GPIO_PORT DIR1: DIRP20 Position */
+#define GPIO_PORT_DIR1_DIRP20_Msk (0x01UL << GPIO_PORT_DIR1_DIRP20_Pos) /*!< GPIO_PORT DIR1: DIRP20 Mask */
+#define GPIO_PORT_DIR1_DIRP21_Pos 21 /*!< GPIO_PORT DIR1: DIRP21 Position */
+#define GPIO_PORT_DIR1_DIRP21_Msk (0x01UL << GPIO_PORT_DIR1_DIRP21_Pos) /*!< GPIO_PORT DIR1: DIRP21 Mask */
+#define GPIO_PORT_DIR1_DIRP22_Pos 22 /*!< GPIO_PORT DIR1: DIRP22 Position */
+#define GPIO_PORT_DIR1_DIRP22_Msk (0x01UL << GPIO_PORT_DIR1_DIRP22_Pos) /*!< GPIO_PORT DIR1: DIRP22 Mask */
+#define GPIO_PORT_DIR1_DIRP23_Pos 23 /*!< GPIO_PORT DIR1: DIRP23 Position */
+#define GPIO_PORT_DIR1_DIRP23_Msk (0x01UL << GPIO_PORT_DIR1_DIRP23_Pos) /*!< GPIO_PORT DIR1: DIRP23 Mask */
+#define GPIO_PORT_DIR1_DIRP24_Pos 24 /*!< GPIO_PORT DIR1: DIRP24 Position */
+#define GPIO_PORT_DIR1_DIRP24_Msk (0x01UL << GPIO_PORT_DIR1_DIRP24_Pos) /*!< GPIO_PORT DIR1: DIRP24 Mask */
+#define GPIO_PORT_DIR1_DIRP25_Pos 25 /*!< GPIO_PORT DIR1: DIRP25 Position */
+#define GPIO_PORT_DIR1_DIRP25_Msk (0x01UL << GPIO_PORT_DIR1_DIRP25_Pos) /*!< GPIO_PORT DIR1: DIRP25 Mask */
+#define GPIO_PORT_DIR1_DIRP26_Pos 26 /*!< GPIO_PORT DIR1: DIRP26 Position */
+#define GPIO_PORT_DIR1_DIRP26_Msk (0x01UL << GPIO_PORT_DIR1_DIRP26_Pos) /*!< GPIO_PORT DIR1: DIRP26 Mask */
+#define GPIO_PORT_DIR1_DIRP27_Pos 27 /*!< GPIO_PORT DIR1: DIRP27 Position */
+#define GPIO_PORT_DIR1_DIRP27_Msk (0x01UL << GPIO_PORT_DIR1_DIRP27_Pos) /*!< GPIO_PORT DIR1: DIRP27 Mask */
+#define GPIO_PORT_DIR1_DIRP28_Pos 28 /*!< GPIO_PORT DIR1: DIRP28 Position */
+#define GPIO_PORT_DIR1_DIRP28_Msk (0x01UL << GPIO_PORT_DIR1_DIRP28_Pos) /*!< GPIO_PORT DIR1: DIRP28 Mask */
+#define GPIO_PORT_DIR1_DIRP29_Pos 29 /*!< GPIO_PORT DIR1: DIRP29 Position */
+#define GPIO_PORT_DIR1_DIRP29_Msk (0x01UL << GPIO_PORT_DIR1_DIRP29_Pos) /*!< GPIO_PORT DIR1: DIRP29 Mask */
+#define GPIO_PORT_DIR1_DIRP30_Pos 30 /*!< GPIO_PORT DIR1: DIRP30 Position */
+#define GPIO_PORT_DIR1_DIRP30_Msk (0x01UL << GPIO_PORT_DIR1_DIRP30_Pos) /*!< GPIO_PORT DIR1: DIRP30 Mask */
+#define GPIO_PORT_DIR1_DIRP31_Pos 31 /*!< GPIO_PORT DIR1: DIRP31 Position */
+#define GPIO_PORT_DIR1_DIRP31_Msk (0x01UL << GPIO_PORT_DIR1_DIRP31_Pos) /*!< GPIO_PORT DIR1: DIRP31 Mask */
+
+// ------------------------------------- GPIO_PORT_DIR2 -----------------------------------------
+#define GPIO_PORT_DIR2_DIRP0_Pos 0 /*!< GPIO_PORT DIR2: DIRP0 Position */
+#define GPIO_PORT_DIR2_DIRP0_Msk (0x01UL << GPIO_PORT_DIR2_DIRP0_Pos) /*!< GPIO_PORT DIR2: DIRP0 Mask */
+#define GPIO_PORT_DIR2_DIRP1_Pos 1 /*!< GPIO_PORT DIR2: DIRP1 Position */
+#define GPIO_PORT_DIR2_DIRP1_Msk (0x01UL << GPIO_PORT_DIR2_DIRP1_Pos) /*!< GPIO_PORT DIR2: DIRP1 Mask */
+#define GPIO_PORT_DIR2_DIRP2_Pos 2 /*!< GPIO_PORT DIR2: DIRP2 Position */
+#define GPIO_PORT_DIR2_DIRP2_Msk (0x01UL << GPIO_PORT_DIR2_DIRP2_Pos) /*!< GPIO_PORT DIR2: DIRP2 Mask */
+#define GPIO_PORT_DIR2_DIRP3_Pos 3 /*!< GPIO_PORT DIR2: DIRP3 Position */
+#define GPIO_PORT_DIR2_DIRP3_Msk (0x01UL << GPIO_PORT_DIR2_DIRP3_Pos) /*!< GPIO_PORT DIR2: DIRP3 Mask */
+#define GPIO_PORT_DIR2_DIRP4_Pos 4 /*!< GPIO_PORT DIR2: DIRP4 Position */
+#define GPIO_PORT_DIR2_DIRP4_Msk (0x01UL << GPIO_PORT_DIR2_DIRP4_Pos) /*!< GPIO_PORT DIR2: DIRP4 Mask */
+#define GPIO_PORT_DIR2_DIRP5_Pos 5 /*!< GPIO_PORT DIR2: DIRP5 Position */
+#define GPIO_PORT_DIR2_DIRP5_Msk (0x01UL << GPIO_PORT_DIR2_DIRP5_Pos) /*!< GPIO_PORT DIR2: DIRP5 Mask */
+#define GPIO_PORT_DIR2_DIRP6_Pos 6 /*!< GPIO_PORT DIR2: DIRP6 Position */
+#define GPIO_PORT_DIR2_DIRP6_Msk (0x01UL << GPIO_PORT_DIR2_DIRP6_Pos) /*!< GPIO_PORT DIR2: DIRP6 Mask */
+#define GPIO_PORT_DIR2_DIRP7_Pos 7 /*!< GPIO_PORT DIR2: DIRP7 Position */
+#define GPIO_PORT_DIR2_DIRP7_Msk (0x01UL << GPIO_PORT_DIR2_DIRP7_Pos) /*!< GPIO_PORT DIR2: DIRP7 Mask */
+#define GPIO_PORT_DIR2_DIRP8_Pos 8 /*!< GPIO_PORT DIR2: DIRP8 Position */
+#define GPIO_PORT_DIR2_DIRP8_Msk (0x01UL << GPIO_PORT_DIR2_DIRP8_Pos) /*!< GPIO_PORT DIR2: DIRP8 Mask */
+#define GPIO_PORT_DIR2_DIRP9_Pos 9 /*!< GPIO_PORT DIR2: DIRP9 Position */
+#define GPIO_PORT_DIR2_DIRP9_Msk (0x01UL << GPIO_PORT_DIR2_DIRP9_Pos) /*!< GPIO_PORT DIR2: DIRP9 Mask */
+#define GPIO_PORT_DIR2_DIRP10_Pos 10 /*!< GPIO_PORT DIR2: DIRP10 Position */
+#define GPIO_PORT_DIR2_DIRP10_Msk (0x01UL << GPIO_PORT_DIR2_DIRP10_Pos) /*!< GPIO_PORT DIR2: DIRP10 Mask */
+#define GPIO_PORT_DIR2_DIRP11_Pos 11 /*!< GPIO_PORT DIR2: DIRP11 Position */
+#define GPIO_PORT_DIR2_DIRP11_Msk (0x01UL << GPIO_PORT_DIR2_DIRP11_Pos) /*!< GPIO_PORT DIR2: DIRP11 Mask */
+#define GPIO_PORT_DIR2_DIRP12_Pos 12 /*!< GPIO_PORT DIR2: DIRP12 Position */
+#define GPIO_PORT_DIR2_DIRP12_Msk (0x01UL << GPIO_PORT_DIR2_DIRP12_Pos) /*!< GPIO_PORT DIR2: DIRP12 Mask */
+#define GPIO_PORT_DIR2_DIRP13_Pos 13 /*!< GPIO_PORT DIR2: DIRP13 Position */
+#define GPIO_PORT_DIR2_DIRP13_Msk (0x01UL << GPIO_PORT_DIR2_DIRP13_Pos) /*!< GPIO_PORT DIR2: DIRP13 Mask */
+#define GPIO_PORT_DIR2_DIRP14_Pos 14 /*!< GPIO_PORT DIR2: DIRP14 Position */
+#define GPIO_PORT_DIR2_DIRP14_Msk (0x01UL << GPIO_PORT_DIR2_DIRP14_Pos) /*!< GPIO_PORT DIR2: DIRP14 Mask */
+#define GPIO_PORT_DIR2_DIRP15_Pos 15 /*!< GPIO_PORT DIR2: DIRP15 Position */
+#define GPIO_PORT_DIR2_DIRP15_Msk (0x01UL << GPIO_PORT_DIR2_DIRP15_Pos) /*!< GPIO_PORT DIR2: DIRP15 Mask */
+#define GPIO_PORT_DIR2_DIRP16_Pos 16 /*!< GPIO_PORT DIR2: DIRP16 Position */
+#define GPIO_PORT_DIR2_DIRP16_Msk (0x01UL << GPIO_PORT_DIR2_DIRP16_Pos) /*!< GPIO_PORT DIR2: DIRP16 Mask */
+#define GPIO_PORT_DIR2_DIRP17_Pos 17 /*!< GPIO_PORT DIR2: DIRP17 Position */
+#define GPIO_PORT_DIR2_DIRP17_Msk (0x01UL << GPIO_PORT_DIR2_DIRP17_Pos) /*!< GPIO_PORT DIR2: DIRP17 Mask */
+#define GPIO_PORT_DIR2_DIRP18_Pos 18 /*!< GPIO_PORT DIR2: DIRP18 Position */
+#define GPIO_PORT_DIR2_DIRP18_Msk (0x01UL << GPIO_PORT_DIR2_DIRP18_Pos) /*!< GPIO_PORT DIR2: DIRP18 Mask */
+#define GPIO_PORT_DIR2_DIRP19_Pos 19 /*!< GPIO_PORT DIR2: DIRP19 Position */
+#define GPIO_PORT_DIR2_DIRP19_Msk (0x01UL << GPIO_PORT_DIR2_DIRP19_Pos) /*!< GPIO_PORT DIR2: DIRP19 Mask */
+#define GPIO_PORT_DIR2_DIRP20_Pos 20 /*!< GPIO_PORT DIR2: DIRP20 Position */
+#define GPIO_PORT_DIR2_DIRP20_Msk (0x01UL << GPIO_PORT_DIR2_DIRP20_Pos) /*!< GPIO_PORT DIR2: DIRP20 Mask */
+#define GPIO_PORT_DIR2_DIRP21_Pos 21 /*!< GPIO_PORT DIR2: DIRP21 Position */
+#define GPIO_PORT_DIR2_DIRP21_Msk (0x01UL << GPIO_PORT_DIR2_DIRP21_Pos) /*!< GPIO_PORT DIR2: DIRP21 Mask */
+#define GPIO_PORT_DIR2_DIRP22_Pos 22 /*!< GPIO_PORT DIR2: DIRP22 Position */
+#define GPIO_PORT_DIR2_DIRP22_Msk (0x01UL << GPIO_PORT_DIR2_DIRP22_Pos) /*!< GPIO_PORT DIR2: DIRP22 Mask */
+#define GPIO_PORT_DIR2_DIRP23_Pos 23 /*!< GPIO_PORT DIR2: DIRP23 Position */
+#define GPIO_PORT_DIR2_DIRP23_Msk (0x01UL << GPIO_PORT_DIR2_DIRP23_Pos) /*!< GPIO_PORT DIR2: DIRP23 Mask */
+#define GPIO_PORT_DIR2_DIRP24_Pos 24 /*!< GPIO_PORT DIR2: DIRP24 Position */
+#define GPIO_PORT_DIR2_DIRP24_Msk (0x01UL << GPIO_PORT_DIR2_DIRP24_Pos) /*!< GPIO_PORT DIR2: DIRP24 Mask */
+#define GPIO_PORT_DIR2_DIRP25_Pos 25 /*!< GPIO_PORT DIR2: DIRP25 Position */
+#define GPIO_PORT_DIR2_DIRP25_Msk (0x01UL << GPIO_PORT_DIR2_DIRP25_Pos) /*!< GPIO_PORT DIR2: DIRP25 Mask */
+#define GPIO_PORT_DIR2_DIRP26_Pos 26 /*!< GPIO_PORT DIR2: DIRP26 Position */
+#define GPIO_PORT_DIR2_DIRP26_Msk (0x01UL << GPIO_PORT_DIR2_DIRP26_Pos) /*!< GPIO_PORT DIR2: DIRP26 Mask */
+#define GPIO_PORT_DIR2_DIRP27_Pos 27 /*!< GPIO_PORT DIR2: DIRP27 Position */
+#define GPIO_PORT_DIR2_DIRP27_Msk (0x01UL << GPIO_PORT_DIR2_DIRP27_Pos) /*!< GPIO_PORT DIR2: DIRP27 Mask */
+#define GPIO_PORT_DIR2_DIRP28_Pos 28 /*!< GPIO_PORT DIR2: DIRP28 Position */
+#define GPIO_PORT_DIR2_DIRP28_Msk (0x01UL << GPIO_PORT_DIR2_DIRP28_Pos) /*!< GPIO_PORT DIR2: DIRP28 Mask */
+#define GPIO_PORT_DIR2_DIRP29_Pos 29 /*!< GPIO_PORT DIR2: DIRP29 Position */
+#define GPIO_PORT_DIR2_DIRP29_Msk (0x01UL << GPIO_PORT_DIR2_DIRP29_Pos) /*!< GPIO_PORT DIR2: DIRP29 Mask */
+#define GPIO_PORT_DIR2_DIRP30_Pos 30 /*!< GPIO_PORT DIR2: DIRP30 Position */
+#define GPIO_PORT_DIR2_DIRP30_Msk (0x01UL << GPIO_PORT_DIR2_DIRP30_Pos) /*!< GPIO_PORT DIR2: DIRP30 Mask */
+#define GPIO_PORT_DIR2_DIRP31_Pos 31 /*!< GPIO_PORT DIR2: DIRP31 Position */
+#define GPIO_PORT_DIR2_DIRP31_Msk (0x01UL << GPIO_PORT_DIR2_DIRP31_Pos) /*!< GPIO_PORT DIR2: DIRP31 Mask */
+
+// ------------------------------------- GPIO_PORT_DIR3 -----------------------------------------
+#define GPIO_PORT_DIR3_DIRP0_Pos 0 /*!< GPIO_PORT DIR3: DIRP0 Position */
+#define GPIO_PORT_DIR3_DIRP0_Msk (0x01UL << GPIO_PORT_DIR3_DIRP0_Pos) /*!< GPIO_PORT DIR3: DIRP0 Mask */
+#define GPIO_PORT_DIR3_DIRP1_Pos 1 /*!< GPIO_PORT DIR3: DIRP1 Position */
+#define GPIO_PORT_DIR3_DIRP1_Msk (0x01UL << GPIO_PORT_DIR3_DIRP1_Pos) /*!< GPIO_PORT DIR3: DIRP1 Mask */
+#define GPIO_PORT_DIR3_DIRP2_Pos 2 /*!< GPIO_PORT DIR3: DIRP2 Position */
+#define GPIO_PORT_DIR3_DIRP2_Msk (0x01UL << GPIO_PORT_DIR3_DIRP2_Pos) /*!< GPIO_PORT DIR3: DIRP2 Mask */
+#define GPIO_PORT_DIR3_DIRP3_Pos 3 /*!< GPIO_PORT DIR3: DIRP3 Position */
+#define GPIO_PORT_DIR3_DIRP3_Msk (0x01UL << GPIO_PORT_DIR3_DIRP3_Pos) /*!< GPIO_PORT DIR3: DIRP3 Mask */
+#define GPIO_PORT_DIR3_DIRP4_Pos 4 /*!< GPIO_PORT DIR3: DIRP4 Position */
+#define GPIO_PORT_DIR3_DIRP4_Msk (0x01UL << GPIO_PORT_DIR3_DIRP4_Pos) /*!< GPIO_PORT DIR3: DIRP4 Mask */
+#define GPIO_PORT_DIR3_DIRP5_Pos 5 /*!< GPIO_PORT DIR3: DIRP5 Position */
+#define GPIO_PORT_DIR3_DIRP5_Msk (0x01UL << GPIO_PORT_DIR3_DIRP5_Pos) /*!< GPIO_PORT DIR3: DIRP5 Mask */
+#define GPIO_PORT_DIR3_DIRP6_Pos 6 /*!< GPIO_PORT DIR3: DIRP6 Position */
+#define GPIO_PORT_DIR3_DIRP6_Msk (0x01UL << GPIO_PORT_DIR3_DIRP6_Pos) /*!< GPIO_PORT DIR3: DIRP6 Mask */
+#define GPIO_PORT_DIR3_DIRP7_Pos 7 /*!< GPIO_PORT DIR3: DIRP7 Position */
+#define GPIO_PORT_DIR3_DIRP7_Msk (0x01UL << GPIO_PORT_DIR3_DIRP7_Pos) /*!< GPIO_PORT DIR3: DIRP7 Mask */
+#define GPIO_PORT_DIR3_DIRP8_Pos 8 /*!< GPIO_PORT DIR3: DIRP8 Position */
+#define GPIO_PORT_DIR3_DIRP8_Msk (0x01UL << GPIO_PORT_DIR3_DIRP8_Pos) /*!< GPIO_PORT DIR3: DIRP8 Mask */
+#define GPIO_PORT_DIR3_DIRP9_Pos 9 /*!< GPIO_PORT DIR3: DIRP9 Position */
+#define GPIO_PORT_DIR3_DIRP9_Msk (0x01UL << GPIO_PORT_DIR3_DIRP9_Pos) /*!< GPIO_PORT DIR3: DIRP9 Mask */
+#define GPIO_PORT_DIR3_DIRP10_Pos 10 /*!< GPIO_PORT DIR3: DIRP10 Position */
+#define GPIO_PORT_DIR3_DIRP10_Msk (0x01UL << GPIO_PORT_DIR3_DIRP10_Pos) /*!< GPIO_PORT DIR3: DIRP10 Mask */
+#define GPIO_PORT_DIR3_DIRP11_Pos 11 /*!< GPIO_PORT DIR3: DIRP11 Position */
+#define GPIO_PORT_DIR3_DIRP11_Msk (0x01UL << GPIO_PORT_DIR3_DIRP11_Pos) /*!< GPIO_PORT DIR3: DIRP11 Mask */
+#define GPIO_PORT_DIR3_DIRP12_Pos 12 /*!< GPIO_PORT DIR3: DIRP12 Position */
+#define GPIO_PORT_DIR3_DIRP12_Msk (0x01UL << GPIO_PORT_DIR3_DIRP12_Pos) /*!< GPIO_PORT DIR3: DIRP12 Mask */
+#define GPIO_PORT_DIR3_DIRP13_Pos 13 /*!< GPIO_PORT DIR3: DIRP13 Position */
+#define GPIO_PORT_DIR3_DIRP13_Msk (0x01UL << GPIO_PORT_DIR3_DIRP13_Pos) /*!< GPIO_PORT DIR3: DIRP13 Mask */
+#define GPIO_PORT_DIR3_DIRP14_Pos 14 /*!< GPIO_PORT DIR3: DIRP14 Position */
+#define GPIO_PORT_DIR3_DIRP14_Msk (0x01UL << GPIO_PORT_DIR3_DIRP14_Pos) /*!< GPIO_PORT DIR3: DIRP14 Mask */
+#define GPIO_PORT_DIR3_DIRP15_Pos 15 /*!< GPIO_PORT DIR3: DIRP15 Position */
+#define GPIO_PORT_DIR3_DIRP15_Msk (0x01UL << GPIO_PORT_DIR3_DIRP15_Pos) /*!< GPIO_PORT DIR3: DIRP15 Mask */
+#define GPIO_PORT_DIR3_DIRP16_Pos 16 /*!< GPIO_PORT DIR3: DIRP16 Position */
+#define GPIO_PORT_DIR3_DIRP16_Msk (0x01UL << GPIO_PORT_DIR3_DIRP16_Pos) /*!< GPIO_PORT DIR3: DIRP16 Mask */
+#define GPIO_PORT_DIR3_DIRP17_Pos 17 /*!< GPIO_PORT DIR3: DIRP17 Position */
+#define GPIO_PORT_DIR3_DIRP17_Msk (0x01UL << GPIO_PORT_DIR3_DIRP17_Pos) /*!< GPIO_PORT DIR3: DIRP17 Mask */
+#define GPIO_PORT_DIR3_DIRP18_Pos 18 /*!< GPIO_PORT DIR3: DIRP18 Position */
+#define GPIO_PORT_DIR3_DIRP18_Msk (0x01UL << GPIO_PORT_DIR3_DIRP18_Pos) /*!< GPIO_PORT DIR3: DIRP18 Mask */
+#define GPIO_PORT_DIR3_DIRP19_Pos 19 /*!< GPIO_PORT DIR3: DIRP19 Position */
+#define GPIO_PORT_DIR3_DIRP19_Msk (0x01UL << GPIO_PORT_DIR3_DIRP19_Pos) /*!< GPIO_PORT DIR3: DIRP19 Mask */
+#define GPIO_PORT_DIR3_DIRP20_Pos 20 /*!< GPIO_PORT DIR3: DIRP20 Position */
+#define GPIO_PORT_DIR3_DIRP20_Msk (0x01UL << GPIO_PORT_DIR3_DIRP20_Pos) /*!< GPIO_PORT DIR3: DIRP20 Mask */
+#define GPIO_PORT_DIR3_DIRP21_Pos 21 /*!< GPIO_PORT DIR3: DIRP21 Position */
+#define GPIO_PORT_DIR3_DIRP21_Msk (0x01UL << GPIO_PORT_DIR3_DIRP21_Pos) /*!< GPIO_PORT DIR3: DIRP21 Mask */
+#define GPIO_PORT_DIR3_DIRP22_Pos 22 /*!< GPIO_PORT DIR3: DIRP22 Position */
+#define GPIO_PORT_DIR3_DIRP22_Msk (0x01UL << GPIO_PORT_DIR3_DIRP22_Pos) /*!< GPIO_PORT DIR3: DIRP22 Mask */
+#define GPIO_PORT_DIR3_DIRP23_Pos 23 /*!< GPIO_PORT DIR3: DIRP23 Position */
+#define GPIO_PORT_DIR3_DIRP23_Msk (0x01UL << GPIO_PORT_DIR3_DIRP23_Pos) /*!< GPIO_PORT DIR3: DIRP23 Mask */
+#define GPIO_PORT_DIR3_DIRP24_Pos 24 /*!< GPIO_PORT DIR3: DIRP24 Position */
+#define GPIO_PORT_DIR3_DIRP24_Msk (0x01UL << GPIO_PORT_DIR3_DIRP24_Pos) /*!< GPIO_PORT DIR3: DIRP24 Mask */
+#define GPIO_PORT_DIR3_DIRP25_Pos 25 /*!< GPIO_PORT DIR3: DIRP25 Position */
+#define GPIO_PORT_DIR3_DIRP25_Msk (0x01UL << GPIO_PORT_DIR3_DIRP25_Pos) /*!< GPIO_PORT DIR3: DIRP25 Mask */
+#define GPIO_PORT_DIR3_DIRP26_Pos 26 /*!< GPIO_PORT DIR3: DIRP26 Position */
+#define GPIO_PORT_DIR3_DIRP26_Msk (0x01UL << GPIO_PORT_DIR3_DIRP26_Pos) /*!< GPIO_PORT DIR3: DIRP26 Mask */
+#define GPIO_PORT_DIR3_DIRP27_Pos 27 /*!< GPIO_PORT DIR3: DIRP27 Position */
+#define GPIO_PORT_DIR3_DIRP27_Msk (0x01UL << GPIO_PORT_DIR3_DIRP27_Pos) /*!< GPIO_PORT DIR3: DIRP27 Mask */
+#define GPIO_PORT_DIR3_DIRP28_Pos 28 /*!< GPIO_PORT DIR3: DIRP28 Position */
+#define GPIO_PORT_DIR3_DIRP28_Msk (0x01UL << GPIO_PORT_DIR3_DIRP28_Pos) /*!< GPIO_PORT DIR3: DIRP28 Mask */
+#define GPIO_PORT_DIR3_DIRP29_Pos 29 /*!< GPIO_PORT DIR3: DIRP29 Position */
+#define GPIO_PORT_DIR3_DIRP29_Msk (0x01UL << GPIO_PORT_DIR3_DIRP29_Pos) /*!< GPIO_PORT DIR3: DIRP29 Mask */
+#define GPIO_PORT_DIR3_DIRP30_Pos 30 /*!< GPIO_PORT DIR3: DIRP30 Position */
+#define GPIO_PORT_DIR3_DIRP30_Msk (0x01UL << GPIO_PORT_DIR3_DIRP30_Pos) /*!< GPIO_PORT DIR3: DIRP30 Mask */
+#define GPIO_PORT_DIR3_DIRP31_Pos 31 /*!< GPIO_PORT DIR3: DIRP31 Position */
+#define GPIO_PORT_DIR3_DIRP31_Msk (0x01UL << GPIO_PORT_DIR3_DIRP31_Pos) /*!< GPIO_PORT DIR3: DIRP31 Mask */
+
+// ------------------------------------- GPIO_PORT_DIR4 -----------------------------------------
+#define GPIO_PORT_DIR4_DIRP0_Pos 0 /*!< GPIO_PORT DIR4: DIRP0 Position */
+#define GPIO_PORT_DIR4_DIRP0_Msk (0x01UL << GPIO_PORT_DIR4_DIRP0_Pos) /*!< GPIO_PORT DIR4: DIRP0 Mask */
+#define GPIO_PORT_DIR4_DIRP1_Pos 1 /*!< GPIO_PORT DIR4: DIRP1 Position */
+#define GPIO_PORT_DIR4_DIRP1_Msk (0x01UL << GPIO_PORT_DIR4_DIRP1_Pos) /*!< GPIO_PORT DIR4: DIRP1 Mask */
+#define GPIO_PORT_DIR4_DIRP2_Pos 2 /*!< GPIO_PORT DIR4: DIRP2 Position */
+#define GPIO_PORT_DIR4_DIRP2_Msk (0x01UL << GPIO_PORT_DIR4_DIRP2_Pos) /*!< GPIO_PORT DIR4: DIRP2 Mask */
+#define GPIO_PORT_DIR4_DIRP3_Pos 3 /*!< GPIO_PORT DIR4: DIRP3 Position */
+#define GPIO_PORT_DIR4_DIRP3_Msk (0x01UL << GPIO_PORT_DIR4_DIRP3_Pos) /*!< GPIO_PORT DIR4: DIRP3 Mask */
+#define GPIO_PORT_DIR4_DIRP4_Pos 4 /*!< GPIO_PORT DIR4: DIRP4 Position */
+#define GPIO_PORT_DIR4_DIRP4_Msk (0x01UL << GPIO_PORT_DIR4_DIRP4_Pos) /*!< GPIO_PORT DIR4: DIRP4 Mask */
+#define GPIO_PORT_DIR4_DIRP5_Pos 5 /*!< GPIO_PORT DIR4: DIRP5 Position */
+#define GPIO_PORT_DIR4_DIRP5_Msk (0x01UL << GPIO_PORT_DIR4_DIRP5_Pos) /*!< GPIO_PORT DIR4: DIRP5 Mask */
+#define GPIO_PORT_DIR4_DIRP6_Pos 6 /*!< GPIO_PORT DIR4: DIRP6 Position */
+#define GPIO_PORT_DIR4_DIRP6_Msk (0x01UL << GPIO_PORT_DIR4_DIRP6_Pos) /*!< GPIO_PORT DIR4: DIRP6 Mask */
+#define GPIO_PORT_DIR4_DIRP7_Pos 7 /*!< GPIO_PORT DIR4: DIRP7 Position */
+#define GPIO_PORT_DIR4_DIRP7_Msk (0x01UL << GPIO_PORT_DIR4_DIRP7_Pos) /*!< GPIO_PORT DIR4: DIRP7 Mask */
+#define GPIO_PORT_DIR4_DIRP8_Pos 8 /*!< GPIO_PORT DIR4: DIRP8 Position */
+#define GPIO_PORT_DIR4_DIRP8_Msk (0x01UL << GPIO_PORT_DIR4_DIRP8_Pos) /*!< GPIO_PORT DIR4: DIRP8 Mask */
+#define GPIO_PORT_DIR4_DIRP9_Pos 9 /*!< GPIO_PORT DIR4: DIRP9 Position */
+#define GPIO_PORT_DIR4_DIRP9_Msk (0x01UL << GPIO_PORT_DIR4_DIRP9_Pos) /*!< GPIO_PORT DIR4: DIRP9 Mask */
+#define GPIO_PORT_DIR4_DIRP10_Pos 10 /*!< GPIO_PORT DIR4: DIRP10 Position */
+#define GPIO_PORT_DIR4_DIRP10_Msk (0x01UL << GPIO_PORT_DIR4_DIRP10_Pos) /*!< GPIO_PORT DIR4: DIRP10 Mask */
+#define GPIO_PORT_DIR4_DIRP11_Pos 11 /*!< GPIO_PORT DIR4: DIRP11 Position */
+#define GPIO_PORT_DIR4_DIRP11_Msk (0x01UL << GPIO_PORT_DIR4_DIRP11_Pos) /*!< GPIO_PORT DIR4: DIRP11 Mask */
+#define GPIO_PORT_DIR4_DIRP12_Pos 12 /*!< GPIO_PORT DIR4: DIRP12 Position */
+#define GPIO_PORT_DIR4_DIRP12_Msk (0x01UL << GPIO_PORT_DIR4_DIRP12_Pos) /*!< GPIO_PORT DIR4: DIRP12 Mask */
+#define GPIO_PORT_DIR4_DIRP13_Pos 13 /*!< GPIO_PORT DIR4: DIRP13 Position */
+#define GPIO_PORT_DIR4_DIRP13_Msk (0x01UL << GPIO_PORT_DIR4_DIRP13_Pos) /*!< GPIO_PORT DIR4: DIRP13 Mask */
+#define GPIO_PORT_DIR4_DIRP14_Pos 14 /*!< GPIO_PORT DIR4: DIRP14 Position */
+#define GPIO_PORT_DIR4_DIRP14_Msk (0x01UL << GPIO_PORT_DIR4_DIRP14_Pos) /*!< GPIO_PORT DIR4: DIRP14 Mask */
+#define GPIO_PORT_DIR4_DIRP15_Pos 15 /*!< GPIO_PORT DIR4: DIRP15 Position */
+#define GPIO_PORT_DIR4_DIRP15_Msk (0x01UL << GPIO_PORT_DIR4_DIRP15_Pos) /*!< GPIO_PORT DIR4: DIRP15 Mask */
+#define GPIO_PORT_DIR4_DIRP16_Pos 16 /*!< GPIO_PORT DIR4: DIRP16 Position */
+#define GPIO_PORT_DIR4_DIRP16_Msk (0x01UL << GPIO_PORT_DIR4_DIRP16_Pos) /*!< GPIO_PORT DIR4: DIRP16 Mask */
+#define GPIO_PORT_DIR4_DIRP17_Pos 17 /*!< GPIO_PORT DIR4: DIRP17 Position */
+#define GPIO_PORT_DIR4_DIRP17_Msk (0x01UL << GPIO_PORT_DIR4_DIRP17_Pos) /*!< GPIO_PORT DIR4: DIRP17 Mask */
+#define GPIO_PORT_DIR4_DIRP18_Pos 18 /*!< GPIO_PORT DIR4: DIRP18 Position */
+#define GPIO_PORT_DIR4_DIRP18_Msk (0x01UL << GPIO_PORT_DIR4_DIRP18_Pos) /*!< GPIO_PORT DIR4: DIRP18 Mask */
+#define GPIO_PORT_DIR4_DIRP19_Pos 19 /*!< GPIO_PORT DIR4: DIRP19 Position */
+#define GPIO_PORT_DIR4_DIRP19_Msk (0x01UL << GPIO_PORT_DIR4_DIRP19_Pos) /*!< GPIO_PORT DIR4: DIRP19 Mask */
+#define GPIO_PORT_DIR4_DIRP20_Pos 20 /*!< GPIO_PORT DIR4: DIRP20 Position */
+#define GPIO_PORT_DIR4_DIRP20_Msk (0x01UL << GPIO_PORT_DIR4_DIRP20_Pos) /*!< GPIO_PORT DIR4: DIRP20 Mask */
+#define GPIO_PORT_DIR4_DIRP21_Pos 21 /*!< GPIO_PORT DIR4: DIRP21 Position */
+#define GPIO_PORT_DIR4_DIRP21_Msk (0x01UL << GPIO_PORT_DIR4_DIRP21_Pos) /*!< GPIO_PORT DIR4: DIRP21 Mask */
+#define GPIO_PORT_DIR4_DIRP22_Pos 22 /*!< GPIO_PORT DIR4: DIRP22 Position */
+#define GPIO_PORT_DIR4_DIRP22_Msk (0x01UL << GPIO_PORT_DIR4_DIRP22_Pos) /*!< GPIO_PORT DIR4: DIRP22 Mask */
+#define GPIO_PORT_DIR4_DIRP23_Pos 23 /*!< GPIO_PORT DIR4: DIRP23 Position */
+#define GPIO_PORT_DIR4_DIRP23_Msk (0x01UL << GPIO_PORT_DIR4_DIRP23_Pos) /*!< GPIO_PORT DIR4: DIRP23 Mask */
+#define GPIO_PORT_DIR4_DIRP24_Pos 24 /*!< GPIO_PORT DIR4: DIRP24 Position */
+#define GPIO_PORT_DIR4_DIRP24_Msk (0x01UL << GPIO_PORT_DIR4_DIRP24_Pos) /*!< GPIO_PORT DIR4: DIRP24 Mask */
+#define GPIO_PORT_DIR4_DIRP25_Pos 25 /*!< GPIO_PORT DIR4: DIRP25 Position */
+#define GPIO_PORT_DIR4_DIRP25_Msk (0x01UL << GPIO_PORT_DIR4_DIRP25_Pos) /*!< GPIO_PORT DIR4: DIRP25 Mask */
+#define GPIO_PORT_DIR4_DIRP26_Pos 26 /*!< GPIO_PORT DIR4: DIRP26 Position */
+#define GPIO_PORT_DIR4_DIRP26_Msk (0x01UL << GPIO_PORT_DIR4_DIRP26_Pos) /*!< GPIO_PORT DIR4: DIRP26 Mask */
+#define GPIO_PORT_DIR4_DIRP27_Pos 27 /*!< GPIO_PORT DIR4: DIRP27 Position */
+#define GPIO_PORT_DIR4_DIRP27_Msk (0x01UL << GPIO_PORT_DIR4_DIRP27_Pos) /*!< GPIO_PORT DIR4: DIRP27 Mask */
+#define GPIO_PORT_DIR4_DIRP28_Pos 28 /*!< GPIO_PORT DIR4: DIRP28 Position */
+#define GPIO_PORT_DIR4_DIRP28_Msk (0x01UL << GPIO_PORT_DIR4_DIRP28_Pos) /*!< GPIO_PORT DIR4: DIRP28 Mask */
+#define GPIO_PORT_DIR4_DIRP29_Pos 29 /*!< GPIO_PORT DIR4: DIRP29 Position */
+#define GPIO_PORT_DIR4_DIRP29_Msk (0x01UL << GPIO_PORT_DIR4_DIRP29_Pos) /*!< GPIO_PORT DIR4: DIRP29 Mask */
+#define GPIO_PORT_DIR4_DIRP30_Pos 30 /*!< GPIO_PORT DIR4: DIRP30 Position */
+#define GPIO_PORT_DIR4_DIRP30_Msk (0x01UL << GPIO_PORT_DIR4_DIRP30_Pos) /*!< GPIO_PORT DIR4: DIRP30 Mask */
+#define GPIO_PORT_DIR4_DIRP31_Pos 31 /*!< GPIO_PORT DIR4: DIRP31 Position */
+#define GPIO_PORT_DIR4_DIRP31_Msk (0x01UL << GPIO_PORT_DIR4_DIRP31_Pos) /*!< GPIO_PORT DIR4: DIRP31 Mask */
+
+// ------------------------------------- GPIO_PORT_DIR5 -----------------------------------------
+#define GPIO_PORT_DIR5_DIRP0_Pos 0 /*!< GPIO_PORT DIR5: DIRP0 Position */
+#define GPIO_PORT_DIR5_DIRP0_Msk (0x01UL << GPIO_PORT_DIR5_DIRP0_Pos) /*!< GPIO_PORT DIR5: DIRP0 Mask */
+#define GPIO_PORT_DIR5_DIRP1_Pos 1 /*!< GPIO_PORT DIR5: DIRP1 Position */
+#define GPIO_PORT_DIR5_DIRP1_Msk (0x01UL << GPIO_PORT_DIR5_DIRP1_Pos) /*!< GPIO_PORT DIR5: DIRP1 Mask */
+#define GPIO_PORT_DIR5_DIRP2_Pos 2 /*!< GPIO_PORT DIR5: DIRP2 Position */
+#define GPIO_PORT_DIR5_DIRP2_Msk (0x01UL << GPIO_PORT_DIR5_DIRP2_Pos) /*!< GPIO_PORT DIR5: DIRP2 Mask */
+#define GPIO_PORT_DIR5_DIRP3_Pos 3 /*!< GPIO_PORT DIR5: DIRP3 Position */
+#define GPIO_PORT_DIR5_DIRP3_Msk (0x01UL << GPIO_PORT_DIR5_DIRP3_Pos) /*!< GPIO_PORT DIR5: DIRP3 Mask */
+#define GPIO_PORT_DIR5_DIRP4_Pos 4 /*!< GPIO_PORT DIR5: DIRP4 Position */
+#define GPIO_PORT_DIR5_DIRP4_Msk (0x01UL << GPIO_PORT_DIR5_DIRP4_Pos) /*!< GPIO_PORT DIR5: DIRP4 Mask */
+#define GPIO_PORT_DIR5_DIRP5_Pos 5 /*!< GPIO_PORT DIR5: DIRP5 Position */
+#define GPIO_PORT_DIR5_DIRP5_Msk (0x01UL << GPIO_PORT_DIR5_DIRP5_Pos) /*!< GPIO_PORT DIR5: DIRP5 Mask */
+#define GPIO_PORT_DIR5_DIRP6_Pos 6 /*!< GPIO_PORT DIR5: DIRP6 Position */
+#define GPIO_PORT_DIR5_DIRP6_Msk (0x01UL << GPIO_PORT_DIR5_DIRP6_Pos) /*!< GPIO_PORT DIR5: DIRP6 Mask */
+#define GPIO_PORT_DIR5_DIRP7_Pos 7 /*!< GPIO_PORT DIR5: DIRP7 Position */
+#define GPIO_PORT_DIR5_DIRP7_Msk (0x01UL << GPIO_PORT_DIR5_DIRP7_Pos) /*!< GPIO_PORT DIR5: DIRP7 Mask */
+#define GPIO_PORT_DIR5_DIRP8_Pos 8 /*!< GPIO_PORT DIR5: DIRP8 Position */
+#define GPIO_PORT_DIR5_DIRP8_Msk (0x01UL << GPIO_PORT_DIR5_DIRP8_Pos) /*!< GPIO_PORT DIR5: DIRP8 Mask */
+#define GPIO_PORT_DIR5_DIRP9_Pos 9 /*!< GPIO_PORT DIR5: DIRP9 Position */
+#define GPIO_PORT_DIR5_DIRP9_Msk (0x01UL << GPIO_PORT_DIR5_DIRP9_Pos) /*!< GPIO_PORT DIR5: DIRP9 Mask */
+#define GPIO_PORT_DIR5_DIRP10_Pos 10 /*!< GPIO_PORT DIR5: DIRP10 Position */
+#define GPIO_PORT_DIR5_DIRP10_Msk (0x01UL << GPIO_PORT_DIR5_DIRP10_Pos) /*!< GPIO_PORT DIR5: DIRP10 Mask */
+#define GPIO_PORT_DIR5_DIRP11_Pos 11 /*!< GPIO_PORT DIR5: DIRP11 Position */
+#define GPIO_PORT_DIR5_DIRP11_Msk (0x01UL << GPIO_PORT_DIR5_DIRP11_Pos) /*!< GPIO_PORT DIR5: DIRP11 Mask */
+#define GPIO_PORT_DIR5_DIRP12_Pos 12 /*!< GPIO_PORT DIR5: DIRP12 Position */
+#define GPIO_PORT_DIR5_DIRP12_Msk (0x01UL << GPIO_PORT_DIR5_DIRP12_Pos) /*!< GPIO_PORT DIR5: DIRP12 Mask */
+#define GPIO_PORT_DIR5_DIRP13_Pos 13 /*!< GPIO_PORT DIR5: DIRP13 Position */
+#define GPIO_PORT_DIR5_DIRP13_Msk (0x01UL << GPIO_PORT_DIR5_DIRP13_Pos) /*!< GPIO_PORT DIR5: DIRP13 Mask */
+#define GPIO_PORT_DIR5_DIRP14_Pos 14 /*!< GPIO_PORT DIR5: DIRP14 Position */
+#define GPIO_PORT_DIR5_DIRP14_Msk (0x01UL << GPIO_PORT_DIR5_DIRP14_Pos) /*!< GPIO_PORT DIR5: DIRP14 Mask */
+#define GPIO_PORT_DIR5_DIRP15_Pos 15 /*!< GPIO_PORT DIR5: DIRP15 Position */
+#define GPIO_PORT_DIR5_DIRP15_Msk (0x01UL << GPIO_PORT_DIR5_DIRP15_Pos) /*!< GPIO_PORT DIR5: DIRP15 Mask */
+#define GPIO_PORT_DIR5_DIRP16_Pos 16 /*!< GPIO_PORT DIR5: DIRP16 Position */
+#define GPIO_PORT_DIR5_DIRP16_Msk (0x01UL << GPIO_PORT_DIR5_DIRP16_Pos) /*!< GPIO_PORT DIR5: DIRP16 Mask */
+#define GPIO_PORT_DIR5_DIRP17_Pos 17 /*!< GPIO_PORT DIR5: DIRP17 Position */
+#define GPIO_PORT_DIR5_DIRP17_Msk (0x01UL << GPIO_PORT_DIR5_DIRP17_Pos) /*!< GPIO_PORT DIR5: DIRP17 Mask */
+#define GPIO_PORT_DIR5_DIRP18_Pos 18 /*!< GPIO_PORT DIR5: DIRP18 Position */
+#define GPIO_PORT_DIR5_DIRP18_Msk (0x01UL << GPIO_PORT_DIR5_DIRP18_Pos) /*!< GPIO_PORT DIR5: DIRP18 Mask */
+#define GPIO_PORT_DIR5_DIRP19_Pos 19 /*!< GPIO_PORT DIR5: DIRP19 Position */
+#define GPIO_PORT_DIR5_DIRP19_Msk (0x01UL << GPIO_PORT_DIR5_DIRP19_Pos) /*!< GPIO_PORT DIR5: DIRP19 Mask */
+#define GPIO_PORT_DIR5_DIRP20_Pos 20 /*!< GPIO_PORT DIR5: DIRP20 Position */
+#define GPIO_PORT_DIR5_DIRP20_Msk (0x01UL << GPIO_PORT_DIR5_DIRP20_Pos) /*!< GPIO_PORT DIR5: DIRP20 Mask */
+#define GPIO_PORT_DIR5_DIRP21_Pos 21 /*!< GPIO_PORT DIR5: DIRP21 Position */
+#define GPIO_PORT_DIR5_DIRP21_Msk (0x01UL << GPIO_PORT_DIR5_DIRP21_Pos) /*!< GPIO_PORT DIR5: DIRP21 Mask */
+#define GPIO_PORT_DIR5_DIRP22_Pos 22 /*!< GPIO_PORT DIR5: DIRP22 Position */
+#define GPIO_PORT_DIR5_DIRP22_Msk (0x01UL << GPIO_PORT_DIR5_DIRP22_Pos) /*!< GPIO_PORT DIR5: DIRP22 Mask */
+#define GPIO_PORT_DIR5_DIRP23_Pos 23 /*!< GPIO_PORT DIR5: DIRP23 Position */
+#define GPIO_PORT_DIR5_DIRP23_Msk (0x01UL << GPIO_PORT_DIR5_DIRP23_Pos) /*!< GPIO_PORT DIR5: DIRP23 Mask */
+#define GPIO_PORT_DIR5_DIRP24_Pos 24 /*!< GPIO_PORT DIR5: DIRP24 Position */
+#define GPIO_PORT_DIR5_DIRP24_Msk (0x01UL << GPIO_PORT_DIR5_DIRP24_Pos) /*!< GPIO_PORT DIR5: DIRP24 Mask */
+#define GPIO_PORT_DIR5_DIRP25_Pos 25 /*!< GPIO_PORT DIR5: DIRP25 Position */
+#define GPIO_PORT_DIR5_DIRP25_Msk (0x01UL << GPIO_PORT_DIR5_DIRP25_Pos) /*!< GPIO_PORT DIR5: DIRP25 Mask */
+#define GPIO_PORT_DIR5_DIRP26_Pos 26 /*!< GPIO_PORT DIR5: DIRP26 Position */
+#define GPIO_PORT_DIR5_DIRP26_Msk (0x01UL << GPIO_PORT_DIR5_DIRP26_Pos) /*!< GPIO_PORT DIR5: DIRP26 Mask */
+#define GPIO_PORT_DIR5_DIRP27_Pos 27 /*!< GPIO_PORT DIR5: DIRP27 Position */
+#define GPIO_PORT_DIR5_DIRP27_Msk (0x01UL << GPIO_PORT_DIR5_DIRP27_Pos) /*!< GPIO_PORT DIR5: DIRP27 Mask */
+#define GPIO_PORT_DIR5_DIRP28_Pos 28 /*!< GPIO_PORT DIR5: DIRP28 Position */
+#define GPIO_PORT_DIR5_DIRP28_Msk (0x01UL << GPIO_PORT_DIR5_DIRP28_Pos) /*!< GPIO_PORT DIR5: DIRP28 Mask */
+#define GPIO_PORT_DIR5_DIRP29_Pos 29 /*!< GPIO_PORT DIR5: DIRP29 Position */
+#define GPIO_PORT_DIR5_DIRP29_Msk (0x01UL << GPIO_PORT_DIR5_DIRP29_Pos) /*!< GPIO_PORT DIR5: DIRP29 Mask */
+#define GPIO_PORT_DIR5_DIRP30_Pos 30 /*!< GPIO_PORT DIR5: DIRP30 Position */
+#define GPIO_PORT_DIR5_DIRP30_Msk (0x01UL << GPIO_PORT_DIR5_DIRP30_Pos) /*!< GPIO_PORT DIR5: DIRP30 Mask */
+#define GPIO_PORT_DIR5_DIRP31_Pos 31 /*!< GPIO_PORT DIR5: DIRP31 Position */
+#define GPIO_PORT_DIR5_DIRP31_Msk (0x01UL << GPIO_PORT_DIR5_DIRP31_Pos) /*!< GPIO_PORT DIR5: DIRP31 Mask */
+
+// ------------------------------------- GPIO_PORT_DIR6 -----------------------------------------
+#define GPIO_PORT_DIR6_DIRP0_Pos 0 /*!< GPIO_PORT DIR6: DIRP0 Position */
+#define GPIO_PORT_DIR6_DIRP0_Msk (0x01UL << GPIO_PORT_DIR6_DIRP0_Pos) /*!< GPIO_PORT DIR6: DIRP0 Mask */
+#define GPIO_PORT_DIR6_DIRP1_Pos 1 /*!< GPIO_PORT DIR6: DIRP1 Position */
+#define GPIO_PORT_DIR6_DIRP1_Msk (0x01UL << GPIO_PORT_DIR6_DIRP1_Pos) /*!< GPIO_PORT DIR6: DIRP1 Mask */
+#define GPIO_PORT_DIR6_DIRP2_Pos 2 /*!< GPIO_PORT DIR6: DIRP2 Position */
+#define GPIO_PORT_DIR6_DIRP2_Msk (0x01UL << GPIO_PORT_DIR6_DIRP2_Pos) /*!< GPIO_PORT DIR6: DIRP2 Mask */
+#define GPIO_PORT_DIR6_DIRP3_Pos 3 /*!< GPIO_PORT DIR6: DIRP3 Position */
+#define GPIO_PORT_DIR6_DIRP3_Msk (0x01UL << GPIO_PORT_DIR6_DIRP3_Pos) /*!< GPIO_PORT DIR6: DIRP3 Mask */
+#define GPIO_PORT_DIR6_DIRP4_Pos 4 /*!< GPIO_PORT DIR6: DIRP4 Position */
+#define GPIO_PORT_DIR6_DIRP4_Msk (0x01UL << GPIO_PORT_DIR6_DIRP4_Pos) /*!< GPIO_PORT DIR6: DIRP4 Mask */
+#define GPIO_PORT_DIR6_DIRP5_Pos 5 /*!< GPIO_PORT DIR6: DIRP5 Position */
+#define GPIO_PORT_DIR6_DIRP5_Msk (0x01UL << GPIO_PORT_DIR6_DIRP5_Pos) /*!< GPIO_PORT DIR6: DIRP5 Mask */
+#define GPIO_PORT_DIR6_DIRP6_Pos 6 /*!< GPIO_PORT DIR6: DIRP6 Position */
+#define GPIO_PORT_DIR6_DIRP6_Msk (0x01UL << GPIO_PORT_DIR6_DIRP6_Pos) /*!< GPIO_PORT DIR6: DIRP6 Mask */
+#define GPIO_PORT_DIR6_DIRP7_Pos 7 /*!< GPIO_PORT DIR6: DIRP7 Position */
+#define GPIO_PORT_DIR6_DIRP7_Msk (0x01UL << GPIO_PORT_DIR6_DIRP7_Pos) /*!< GPIO_PORT DIR6: DIRP7 Mask */
+#define GPIO_PORT_DIR6_DIRP8_Pos 8 /*!< GPIO_PORT DIR6: DIRP8 Position */
+#define GPIO_PORT_DIR6_DIRP8_Msk (0x01UL << GPIO_PORT_DIR6_DIRP8_Pos) /*!< GPIO_PORT DIR6: DIRP8 Mask */
+#define GPIO_PORT_DIR6_DIRP9_Pos 9 /*!< GPIO_PORT DIR6: DIRP9 Position */
+#define GPIO_PORT_DIR6_DIRP9_Msk (0x01UL << GPIO_PORT_DIR6_DIRP9_Pos) /*!< GPIO_PORT DIR6: DIRP9 Mask */
+#define GPIO_PORT_DIR6_DIRP10_Pos 10 /*!< GPIO_PORT DIR6: DIRP10 Position */
+#define GPIO_PORT_DIR6_DIRP10_Msk (0x01UL << GPIO_PORT_DIR6_DIRP10_Pos) /*!< GPIO_PORT DIR6: DIRP10 Mask */
+#define GPIO_PORT_DIR6_DIRP11_Pos 11 /*!< GPIO_PORT DIR6: DIRP11 Position */
+#define GPIO_PORT_DIR6_DIRP11_Msk (0x01UL << GPIO_PORT_DIR6_DIRP11_Pos) /*!< GPIO_PORT DIR6: DIRP11 Mask */
+#define GPIO_PORT_DIR6_DIRP12_Pos 12 /*!< GPIO_PORT DIR6: DIRP12 Position */
+#define GPIO_PORT_DIR6_DIRP12_Msk (0x01UL << GPIO_PORT_DIR6_DIRP12_Pos) /*!< GPIO_PORT DIR6: DIRP12 Mask */
+#define GPIO_PORT_DIR6_DIRP13_Pos 13 /*!< GPIO_PORT DIR6: DIRP13 Position */
+#define GPIO_PORT_DIR6_DIRP13_Msk (0x01UL << GPIO_PORT_DIR6_DIRP13_Pos) /*!< GPIO_PORT DIR6: DIRP13 Mask */
+#define GPIO_PORT_DIR6_DIRP14_Pos 14 /*!< GPIO_PORT DIR6: DIRP14 Position */
+#define GPIO_PORT_DIR6_DIRP14_Msk (0x01UL << GPIO_PORT_DIR6_DIRP14_Pos) /*!< GPIO_PORT DIR6: DIRP14 Mask */
+#define GPIO_PORT_DIR6_DIRP15_Pos 15 /*!< GPIO_PORT DIR6: DIRP15 Position */
+#define GPIO_PORT_DIR6_DIRP15_Msk (0x01UL << GPIO_PORT_DIR6_DIRP15_Pos) /*!< GPIO_PORT DIR6: DIRP15 Mask */
+#define GPIO_PORT_DIR6_DIRP16_Pos 16 /*!< GPIO_PORT DIR6: DIRP16 Position */
+#define GPIO_PORT_DIR6_DIRP16_Msk (0x01UL << GPIO_PORT_DIR6_DIRP16_Pos) /*!< GPIO_PORT DIR6: DIRP16 Mask */
+#define GPIO_PORT_DIR6_DIRP17_Pos 17 /*!< GPIO_PORT DIR6: DIRP17 Position */
+#define GPIO_PORT_DIR6_DIRP17_Msk (0x01UL << GPIO_PORT_DIR6_DIRP17_Pos) /*!< GPIO_PORT DIR6: DIRP17 Mask */
+#define GPIO_PORT_DIR6_DIRP18_Pos 18 /*!< GPIO_PORT DIR6: DIRP18 Position */
+#define GPIO_PORT_DIR6_DIRP18_Msk (0x01UL << GPIO_PORT_DIR6_DIRP18_Pos) /*!< GPIO_PORT DIR6: DIRP18 Mask */
+#define GPIO_PORT_DIR6_DIRP19_Pos 19 /*!< GPIO_PORT DIR6: DIRP19 Position */
+#define GPIO_PORT_DIR6_DIRP19_Msk (0x01UL << GPIO_PORT_DIR6_DIRP19_Pos) /*!< GPIO_PORT DIR6: DIRP19 Mask */
+#define GPIO_PORT_DIR6_DIRP20_Pos 20 /*!< GPIO_PORT DIR6: DIRP20 Position */
+#define GPIO_PORT_DIR6_DIRP20_Msk (0x01UL << GPIO_PORT_DIR6_DIRP20_Pos) /*!< GPIO_PORT DIR6: DIRP20 Mask */
+#define GPIO_PORT_DIR6_DIRP21_Pos 21 /*!< GPIO_PORT DIR6: DIRP21 Position */
+#define GPIO_PORT_DIR6_DIRP21_Msk (0x01UL << GPIO_PORT_DIR6_DIRP21_Pos) /*!< GPIO_PORT DIR6: DIRP21 Mask */
+#define GPIO_PORT_DIR6_DIRP22_Pos 22 /*!< GPIO_PORT DIR6: DIRP22 Position */
+#define GPIO_PORT_DIR6_DIRP22_Msk (0x01UL << GPIO_PORT_DIR6_DIRP22_Pos) /*!< GPIO_PORT DIR6: DIRP22 Mask */
+#define GPIO_PORT_DIR6_DIRP23_Pos 23 /*!< GPIO_PORT DIR6: DIRP23 Position */
+#define GPIO_PORT_DIR6_DIRP23_Msk (0x01UL << GPIO_PORT_DIR6_DIRP23_Pos) /*!< GPIO_PORT DIR6: DIRP23 Mask */
+#define GPIO_PORT_DIR6_DIRP24_Pos 24 /*!< GPIO_PORT DIR6: DIRP24 Position */
+#define GPIO_PORT_DIR6_DIRP24_Msk (0x01UL << GPIO_PORT_DIR6_DIRP24_Pos) /*!< GPIO_PORT DIR6: DIRP24 Mask */
+#define GPIO_PORT_DIR6_DIRP25_Pos 25 /*!< GPIO_PORT DIR6: DIRP25 Position */
+#define GPIO_PORT_DIR6_DIRP25_Msk (0x01UL << GPIO_PORT_DIR6_DIRP25_Pos) /*!< GPIO_PORT DIR6: DIRP25 Mask */
+#define GPIO_PORT_DIR6_DIRP26_Pos 26 /*!< GPIO_PORT DIR6: DIRP26 Position */
+#define GPIO_PORT_DIR6_DIRP26_Msk (0x01UL << GPIO_PORT_DIR6_DIRP26_Pos) /*!< GPIO_PORT DIR6: DIRP26 Mask */
+#define GPIO_PORT_DIR6_DIRP27_Pos 27 /*!< GPIO_PORT DIR6: DIRP27 Position */
+#define GPIO_PORT_DIR6_DIRP27_Msk (0x01UL << GPIO_PORT_DIR6_DIRP27_Pos) /*!< GPIO_PORT DIR6: DIRP27 Mask */
+#define GPIO_PORT_DIR6_DIRP28_Pos 28 /*!< GPIO_PORT DIR6: DIRP28 Position */
+#define GPIO_PORT_DIR6_DIRP28_Msk (0x01UL << GPIO_PORT_DIR6_DIRP28_Pos) /*!< GPIO_PORT DIR6: DIRP28 Mask */
+#define GPIO_PORT_DIR6_DIRP29_Pos 29 /*!< GPIO_PORT DIR6: DIRP29 Position */
+#define GPIO_PORT_DIR6_DIRP29_Msk (0x01UL << GPIO_PORT_DIR6_DIRP29_Pos) /*!< GPIO_PORT DIR6: DIRP29 Mask */
+#define GPIO_PORT_DIR6_DIRP30_Pos 30 /*!< GPIO_PORT DIR6: DIRP30 Position */
+#define GPIO_PORT_DIR6_DIRP30_Msk (0x01UL << GPIO_PORT_DIR6_DIRP30_Pos) /*!< GPIO_PORT DIR6: DIRP30 Mask */
+#define GPIO_PORT_DIR6_DIRP31_Pos 31 /*!< GPIO_PORT DIR6: DIRP31 Position */
+#define GPIO_PORT_DIR6_DIRP31_Msk (0x01UL << GPIO_PORT_DIR6_DIRP31_Pos) /*!< GPIO_PORT DIR6: DIRP31 Mask */
+
+// ------------------------------------- GPIO_PORT_DIR7 -----------------------------------------
+#define GPIO_PORT_DIR7_DIRP0_Pos 0 /*!< GPIO_PORT DIR7: DIRP0 Position */
+#define GPIO_PORT_DIR7_DIRP0_Msk (0x01UL << GPIO_PORT_DIR7_DIRP0_Pos) /*!< GPIO_PORT DIR7: DIRP0 Mask */
+#define GPIO_PORT_DIR7_DIRP1_Pos 1 /*!< GPIO_PORT DIR7: DIRP1 Position */
+#define GPIO_PORT_DIR7_DIRP1_Msk (0x01UL << GPIO_PORT_DIR7_DIRP1_Pos) /*!< GPIO_PORT DIR7: DIRP1 Mask */
+#define GPIO_PORT_DIR7_DIRP2_Pos 2 /*!< GPIO_PORT DIR7: DIRP2 Position */
+#define GPIO_PORT_DIR7_DIRP2_Msk (0x01UL << GPIO_PORT_DIR7_DIRP2_Pos) /*!< GPIO_PORT DIR7: DIRP2 Mask */
+#define GPIO_PORT_DIR7_DIRP3_Pos 3 /*!< GPIO_PORT DIR7: DIRP3 Position */
+#define GPIO_PORT_DIR7_DIRP3_Msk (0x01UL << GPIO_PORT_DIR7_DIRP3_Pos) /*!< GPIO_PORT DIR7: DIRP3 Mask */
+#define GPIO_PORT_DIR7_DIRP4_Pos 4 /*!< GPIO_PORT DIR7: DIRP4 Position */
+#define GPIO_PORT_DIR7_DIRP4_Msk (0x01UL << GPIO_PORT_DIR7_DIRP4_Pos) /*!< GPIO_PORT DIR7: DIRP4 Mask */
+#define GPIO_PORT_DIR7_DIRP5_Pos 5 /*!< GPIO_PORT DIR7: DIRP5 Position */
+#define GPIO_PORT_DIR7_DIRP5_Msk (0x01UL << GPIO_PORT_DIR7_DIRP5_Pos) /*!< GPIO_PORT DIR7: DIRP5 Mask */
+#define GPIO_PORT_DIR7_DIRP6_Pos 6 /*!< GPIO_PORT DIR7: DIRP6 Position */
+#define GPIO_PORT_DIR7_DIRP6_Msk (0x01UL << GPIO_PORT_DIR7_DIRP6_Pos) /*!< GPIO_PORT DIR7: DIRP6 Mask */
+#define GPIO_PORT_DIR7_DIRP7_Pos 7 /*!< GPIO_PORT DIR7: DIRP7 Position */
+#define GPIO_PORT_DIR7_DIRP7_Msk (0x01UL << GPIO_PORT_DIR7_DIRP7_Pos) /*!< GPIO_PORT DIR7: DIRP7 Mask */
+#define GPIO_PORT_DIR7_DIRP8_Pos 8 /*!< GPIO_PORT DIR7: DIRP8 Position */
+#define GPIO_PORT_DIR7_DIRP8_Msk (0x01UL << GPIO_PORT_DIR7_DIRP8_Pos) /*!< GPIO_PORT DIR7: DIRP8 Mask */
+#define GPIO_PORT_DIR7_DIRP9_Pos 9 /*!< GPIO_PORT DIR7: DIRP9 Position */
+#define GPIO_PORT_DIR7_DIRP9_Msk (0x01UL << GPIO_PORT_DIR7_DIRP9_Pos) /*!< GPIO_PORT DIR7: DIRP9 Mask */
+#define GPIO_PORT_DIR7_DIRP10_Pos 10 /*!< GPIO_PORT DIR7: DIRP10 Position */
+#define GPIO_PORT_DIR7_DIRP10_Msk (0x01UL << GPIO_PORT_DIR7_DIRP10_Pos) /*!< GPIO_PORT DIR7: DIRP10 Mask */
+#define GPIO_PORT_DIR7_DIRP11_Pos 11 /*!< GPIO_PORT DIR7: DIRP11 Position */
+#define GPIO_PORT_DIR7_DIRP11_Msk (0x01UL << GPIO_PORT_DIR7_DIRP11_Pos) /*!< GPIO_PORT DIR7: DIRP11 Mask */
+#define GPIO_PORT_DIR7_DIRP12_Pos 12 /*!< GPIO_PORT DIR7: DIRP12 Position */
+#define GPIO_PORT_DIR7_DIRP12_Msk (0x01UL << GPIO_PORT_DIR7_DIRP12_Pos) /*!< GPIO_PORT DIR7: DIRP12 Mask */
+#define GPIO_PORT_DIR7_DIRP13_Pos 13 /*!< GPIO_PORT DIR7: DIRP13 Position */
+#define GPIO_PORT_DIR7_DIRP13_Msk (0x01UL << GPIO_PORT_DIR7_DIRP13_Pos) /*!< GPIO_PORT DIR7: DIRP13 Mask */
+#define GPIO_PORT_DIR7_DIRP14_Pos 14 /*!< GPIO_PORT DIR7: DIRP14 Position */
+#define GPIO_PORT_DIR7_DIRP14_Msk (0x01UL << GPIO_PORT_DIR7_DIRP14_Pos) /*!< GPIO_PORT DIR7: DIRP14 Mask */
+#define GPIO_PORT_DIR7_DIRP15_Pos 15 /*!< GPIO_PORT DIR7: DIRP15 Position */
+#define GPIO_PORT_DIR7_DIRP15_Msk (0x01UL << GPIO_PORT_DIR7_DIRP15_Pos) /*!< GPIO_PORT DIR7: DIRP15 Mask */
+#define GPIO_PORT_DIR7_DIRP16_Pos 16 /*!< GPIO_PORT DIR7: DIRP16 Position */
+#define GPIO_PORT_DIR7_DIRP16_Msk (0x01UL << GPIO_PORT_DIR7_DIRP16_Pos) /*!< GPIO_PORT DIR7: DIRP16 Mask */
+#define GPIO_PORT_DIR7_DIRP17_Pos 17 /*!< GPIO_PORT DIR7: DIRP17 Position */
+#define GPIO_PORT_DIR7_DIRP17_Msk (0x01UL << GPIO_PORT_DIR7_DIRP17_Pos) /*!< GPIO_PORT DIR7: DIRP17 Mask */
+#define GPIO_PORT_DIR7_DIRP18_Pos 18 /*!< GPIO_PORT DIR7: DIRP18 Position */
+#define GPIO_PORT_DIR7_DIRP18_Msk (0x01UL << GPIO_PORT_DIR7_DIRP18_Pos) /*!< GPIO_PORT DIR7: DIRP18 Mask */
+#define GPIO_PORT_DIR7_DIRP19_Pos 19 /*!< GPIO_PORT DIR7: DIRP19 Position */
+#define GPIO_PORT_DIR7_DIRP19_Msk (0x01UL << GPIO_PORT_DIR7_DIRP19_Pos) /*!< GPIO_PORT DIR7: DIRP19 Mask */
+#define GPIO_PORT_DIR7_DIRP20_Pos 20 /*!< GPIO_PORT DIR7: DIRP20 Position */
+#define GPIO_PORT_DIR7_DIRP20_Msk (0x01UL << GPIO_PORT_DIR7_DIRP20_Pos) /*!< GPIO_PORT DIR7: DIRP20 Mask */
+#define GPIO_PORT_DIR7_DIRP21_Pos 21 /*!< GPIO_PORT DIR7: DIRP21 Position */
+#define GPIO_PORT_DIR7_DIRP21_Msk (0x01UL << GPIO_PORT_DIR7_DIRP21_Pos) /*!< GPIO_PORT DIR7: DIRP21 Mask */
+#define GPIO_PORT_DIR7_DIRP22_Pos 22 /*!< GPIO_PORT DIR7: DIRP22 Position */
+#define GPIO_PORT_DIR7_DIRP22_Msk (0x01UL << GPIO_PORT_DIR7_DIRP22_Pos) /*!< GPIO_PORT DIR7: DIRP22 Mask */
+#define GPIO_PORT_DIR7_DIRP23_Pos 23 /*!< GPIO_PORT DIR7: DIRP23 Position */
+#define GPIO_PORT_DIR7_DIRP23_Msk (0x01UL << GPIO_PORT_DIR7_DIRP23_Pos) /*!< GPIO_PORT DIR7: DIRP23 Mask */
+#define GPIO_PORT_DIR7_DIRP24_Pos 24 /*!< GPIO_PORT DIR7: DIRP24 Position */
+#define GPIO_PORT_DIR7_DIRP24_Msk (0x01UL << GPIO_PORT_DIR7_DIRP24_Pos) /*!< GPIO_PORT DIR7: DIRP24 Mask */
+#define GPIO_PORT_DIR7_DIRP25_Pos 25 /*!< GPIO_PORT DIR7: DIRP25 Position */
+#define GPIO_PORT_DIR7_DIRP25_Msk (0x01UL << GPIO_PORT_DIR7_DIRP25_Pos) /*!< GPIO_PORT DIR7: DIRP25 Mask */
+#define GPIO_PORT_DIR7_DIRP26_Pos 26 /*!< GPIO_PORT DIR7: DIRP26 Position */
+#define GPIO_PORT_DIR7_DIRP26_Msk (0x01UL << GPIO_PORT_DIR7_DIRP26_Pos) /*!< GPIO_PORT DIR7: DIRP26 Mask */
+#define GPIO_PORT_DIR7_DIRP27_Pos 27 /*!< GPIO_PORT DIR7: DIRP27 Position */
+#define GPIO_PORT_DIR7_DIRP27_Msk (0x01UL << GPIO_PORT_DIR7_DIRP27_Pos) /*!< GPIO_PORT DIR7: DIRP27 Mask */
+#define GPIO_PORT_DIR7_DIRP28_Pos 28 /*!< GPIO_PORT DIR7: DIRP28 Position */
+#define GPIO_PORT_DIR7_DIRP28_Msk (0x01UL << GPIO_PORT_DIR7_DIRP28_Pos) /*!< GPIO_PORT DIR7: DIRP28 Mask */
+#define GPIO_PORT_DIR7_DIRP29_Pos 29 /*!< GPIO_PORT DIR7: DIRP29 Position */
+#define GPIO_PORT_DIR7_DIRP29_Msk (0x01UL << GPIO_PORT_DIR7_DIRP29_Pos) /*!< GPIO_PORT DIR7: DIRP29 Mask */
+#define GPIO_PORT_DIR7_DIRP30_Pos 30 /*!< GPIO_PORT DIR7: DIRP30 Position */
+#define GPIO_PORT_DIR7_DIRP30_Msk (0x01UL << GPIO_PORT_DIR7_DIRP30_Pos) /*!< GPIO_PORT DIR7: DIRP30 Mask */
+#define GPIO_PORT_DIR7_DIRP31_Pos 31 /*!< GPIO_PORT DIR7: DIRP31 Position */
+#define GPIO_PORT_DIR7_DIRP31_Msk (0x01UL << GPIO_PORT_DIR7_DIRP31_Pos) /*!< GPIO_PORT DIR7: DIRP31 Mask */
+
+// ------------------------------------- GPIO_PORT_MASK0 ----------------------------------------
+#define GPIO_PORT_MASK0_MASKP0_Pos 0 /*!< GPIO_PORT MASK0: MASKP0 Position */
+#define GPIO_PORT_MASK0_MASKP0_Msk (0x01UL << GPIO_PORT_MASK0_MASKP0_Pos) /*!< GPIO_PORT MASK0: MASKP0 Mask */
+#define GPIO_PORT_MASK0_MASKP1_Pos 1 /*!< GPIO_PORT MASK0: MASKP1 Position */
+#define GPIO_PORT_MASK0_MASKP1_Msk (0x01UL << GPIO_PORT_MASK0_MASKP1_Pos) /*!< GPIO_PORT MASK0: MASKP1 Mask */
+#define GPIO_PORT_MASK0_MASKP2_Pos 2 /*!< GPIO_PORT MASK0: MASKP2 Position */
+#define GPIO_PORT_MASK0_MASKP2_Msk (0x01UL << GPIO_PORT_MASK0_MASKP2_Pos) /*!< GPIO_PORT MASK0: MASKP2 Mask */
+#define GPIO_PORT_MASK0_MASKP3_Pos 3 /*!< GPIO_PORT MASK0: MASKP3 Position */
+#define GPIO_PORT_MASK0_MASKP3_Msk (0x01UL << GPIO_PORT_MASK0_MASKP3_Pos) /*!< GPIO_PORT MASK0: MASKP3 Mask */
+#define GPIO_PORT_MASK0_MASKP4_Pos 4 /*!< GPIO_PORT MASK0: MASKP4 Position */
+#define GPIO_PORT_MASK0_MASKP4_Msk (0x01UL << GPIO_PORT_MASK0_MASKP4_Pos) /*!< GPIO_PORT MASK0: MASKP4 Mask */
+#define GPIO_PORT_MASK0_MASKP5_Pos 5 /*!< GPIO_PORT MASK0: MASKP5 Position */
+#define GPIO_PORT_MASK0_MASKP5_Msk (0x01UL << GPIO_PORT_MASK0_MASKP5_Pos) /*!< GPIO_PORT MASK0: MASKP5 Mask */
+#define GPIO_PORT_MASK0_MASKP6_Pos 6 /*!< GPIO_PORT MASK0: MASKP6 Position */
+#define GPIO_PORT_MASK0_MASKP6_Msk (0x01UL << GPIO_PORT_MASK0_MASKP6_Pos) /*!< GPIO_PORT MASK0: MASKP6 Mask */
+#define GPIO_PORT_MASK0_MASKP7_Pos 7 /*!< GPIO_PORT MASK0: MASKP7 Position */
+#define GPIO_PORT_MASK0_MASKP7_Msk (0x01UL << GPIO_PORT_MASK0_MASKP7_Pos) /*!< GPIO_PORT MASK0: MASKP7 Mask */
+#define GPIO_PORT_MASK0_MASKP8_Pos 8 /*!< GPIO_PORT MASK0: MASKP8 Position */
+#define GPIO_PORT_MASK0_MASKP8_Msk (0x01UL << GPIO_PORT_MASK0_MASKP8_Pos) /*!< GPIO_PORT MASK0: MASKP8 Mask */
+#define GPIO_PORT_MASK0_MASKP9_Pos 9 /*!< GPIO_PORT MASK0: MASKP9 Position */
+#define GPIO_PORT_MASK0_MASKP9_Msk (0x01UL << GPIO_PORT_MASK0_MASKP9_Pos) /*!< GPIO_PORT MASK0: MASKP9 Mask */
+#define GPIO_PORT_MASK0_MASKP10_Pos 10 /*!< GPIO_PORT MASK0: MASKP10 Position */
+#define GPIO_PORT_MASK0_MASKP10_Msk (0x01UL << GPIO_PORT_MASK0_MASKP10_Pos) /*!< GPIO_PORT MASK0: MASKP10 Mask */
+#define GPIO_PORT_MASK0_MASKP11_Pos 11 /*!< GPIO_PORT MASK0: MASKP11 Position */
+#define GPIO_PORT_MASK0_MASKP11_Msk (0x01UL << GPIO_PORT_MASK0_MASKP11_Pos) /*!< GPIO_PORT MASK0: MASKP11 Mask */
+#define GPIO_PORT_MASK0_MASKP12_Pos 12 /*!< GPIO_PORT MASK0: MASKP12 Position */
+#define GPIO_PORT_MASK0_MASKP12_Msk (0x01UL << GPIO_PORT_MASK0_MASKP12_Pos) /*!< GPIO_PORT MASK0: MASKP12 Mask */
+#define GPIO_PORT_MASK0_MASKP13_Pos 13 /*!< GPIO_PORT MASK0: MASKP13 Position */
+#define GPIO_PORT_MASK0_MASKP13_Msk (0x01UL << GPIO_PORT_MASK0_MASKP13_Pos) /*!< GPIO_PORT MASK0: MASKP13 Mask */
+#define GPIO_PORT_MASK0_MASKP14_Pos 14 /*!< GPIO_PORT MASK0: MASKP14 Position */
+#define GPIO_PORT_MASK0_MASKP14_Msk (0x01UL << GPIO_PORT_MASK0_MASKP14_Pos) /*!< GPIO_PORT MASK0: MASKP14 Mask */
+#define GPIO_PORT_MASK0_MASKP15_Pos 15 /*!< GPIO_PORT MASK0: MASKP15 Position */
+#define GPIO_PORT_MASK0_MASKP15_Msk (0x01UL << GPIO_PORT_MASK0_MASKP15_Pos) /*!< GPIO_PORT MASK0: MASKP15 Mask */
+#define GPIO_PORT_MASK0_MASKP16_Pos 16 /*!< GPIO_PORT MASK0: MASKP16 Position */
+#define GPIO_PORT_MASK0_MASKP16_Msk (0x01UL << GPIO_PORT_MASK0_MASKP16_Pos) /*!< GPIO_PORT MASK0: MASKP16 Mask */
+#define GPIO_PORT_MASK0_MASKP17_Pos 17 /*!< GPIO_PORT MASK0: MASKP17 Position */
+#define GPIO_PORT_MASK0_MASKP17_Msk (0x01UL << GPIO_PORT_MASK0_MASKP17_Pos) /*!< GPIO_PORT MASK0: MASKP17 Mask */
+#define GPIO_PORT_MASK0_MASKP18_Pos 18 /*!< GPIO_PORT MASK0: MASKP18 Position */
+#define GPIO_PORT_MASK0_MASKP18_Msk (0x01UL << GPIO_PORT_MASK0_MASKP18_Pos) /*!< GPIO_PORT MASK0: MASKP18 Mask */
+#define GPIO_PORT_MASK0_MASKP19_Pos 19 /*!< GPIO_PORT MASK0: MASKP19 Position */
+#define GPIO_PORT_MASK0_MASKP19_Msk (0x01UL << GPIO_PORT_MASK0_MASKP19_Pos) /*!< GPIO_PORT MASK0: MASKP19 Mask */
+#define GPIO_PORT_MASK0_MASKP20_Pos 20 /*!< GPIO_PORT MASK0: MASKP20 Position */
+#define GPIO_PORT_MASK0_MASKP20_Msk (0x01UL << GPIO_PORT_MASK0_MASKP20_Pos) /*!< GPIO_PORT MASK0: MASKP20 Mask */
+#define GPIO_PORT_MASK0_MASKP21_Pos 21 /*!< GPIO_PORT MASK0: MASKP21 Position */
+#define GPIO_PORT_MASK0_MASKP21_Msk (0x01UL << GPIO_PORT_MASK0_MASKP21_Pos) /*!< GPIO_PORT MASK0: MASKP21 Mask */
+#define GPIO_PORT_MASK0_MASKP22_Pos 22 /*!< GPIO_PORT MASK0: MASKP22 Position */
+#define GPIO_PORT_MASK0_MASKP22_Msk (0x01UL << GPIO_PORT_MASK0_MASKP22_Pos) /*!< GPIO_PORT MASK0: MASKP22 Mask */
+#define GPIO_PORT_MASK0_MASKP23_Pos 23 /*!< GPIO_PORT MASK0: MASKP23 Position */
+#define GPIO_PORT_MASK0_MASKP23_Msk (0x01UL << GPIO_PORT_MASK0_MASKP23_Pos) /*!< GPIO_PORT MASK0: MASKP23 Mask */
+#define GPIO_PORT_MASK0_MASKP24_Pos 24 /*!< GPIO_PORT MASK0: MASKP24 Position */
+#define GPIO_PORT_MASK0_MASKP24_Msk (0x01UL << GPIO_PORT_MASK0_MASKP24_Pos) /*!< GPIO_PORT MASK0: MASKP24 Mask */
+#define GPIO_PORT_MASK0_MASKP25_Pos 25 /*!< GPIO_PORT MASK0: MASKP25 Position */
+#define GPIO_PORT_MASK0_MASKP25_Msk (0x01UL << GPIO_PORT_MASK0_MASKP25_Pos) /*!< GPIO_PORT MASK0: MASKP25 Mask */
+#define GPIO_PORT_MASK0_MASKP26_Pos 26 /*!< GPIO_PORT MASK0: MASKP26 Position */
+#define GPIO_PORT_MASK0_MASKP26_Msk (0x01UL << GPIO_PORT_MASK0_MASKP26_Pos) /*!< GPIO_PORT MASK0: MASKP26 Mask */
+#define GPIO_PORT_MASK0_MASKP27_Pos 27 /*!< GPIO_PORT MASK0: MASKP27 Position */
+#define GPIO_PORT_MASK0_MASKP27_Msk (0x01UL << GPIO_PORT_MASK0_MASKP27_Pos) /*!< GPIO_PORT MASK0: MASKP27 Mask */
+#define GPIO_PORT_MASK0_MASKP28_Pos 28 /*!< GPIO_PORT MASK0: MASKP28 Position */
+#define GPIO_PORT_MASK0_MASKP28_Msk (0x01UL << GPIO_PORT_MASK0_MASKP28_Pos) /*!< GPIO_PORT MASK0: MASKP28 Mask */
+#define GPIO_PORT_MASK0_MASKP29_Pos 29 /*!< GPIO_PORT MASK0: MASKP29 Position */
+#define GPIO_PORT_MASK0_MASKP29_Msk (0x01UL << GPIO_PORT_MASK0_MASKP29_Pos) /*!< GPIO_PORT MASK0: MASKP29 Mask */
+#define GPIO_PORT_MASK0_MASKP30_Pos 30 /*!< GPIO_PORT MASK0: MASKP30 Position */
+#define GPIO_PORT_MASK0_MASKP30_Msk (0x01UL << GPIO_PORT_MASK0_MASKP30_Pos) /*!< GPIO_PORT MASK0: MASKP30 Mask */
+#define GPIO_PORT_MASK0_MASKP31_Pos 31 /*!< GPIO_PORT MASK0: MASKP31 Position */
+#define GPIO_PORT_MASK0_MASKP31_Msk (0x01UL << GPIO_PORT_MASK0_MASKP31_Pos) /*!< GPIO_PORT MASK0: MASKP31 Mask */
+
+// ------------------------------------- GPIO_PORT_MASK1 ----------------------------------------
+#define GPIO_PORT_MASK1_MASKP0_Pos 0 /*!< GPIO_PORT MASK1: MASKP0 Position */
+#define GPIO_PORT_MASK1_MASKP0_Msk (0x01UL << GPIO_PORT_MASK1_MASKP0_Pos) /*!< GPIO_PORT MASK1: MASKP0 Mask */
+#define GPIO_PORT_MASK1_MASKP1_Pos 1 /*!< GPIO_PORT MASK1: MASKP1 Position */
+#define GPIO_PORT_MASK1_MASKP1_Msk (0x01UL << GPIO_PORT_MASK1_MASKP1_Pos) /*!< GPIO_PORT MASK1: MASKP1 Mask */
+#define GPIO_PORT_MASK1_MASKP2_Pos 2 /*!< GPIO_PORT MASK1: MASKP2 Position */
+#define GPIO_PORT_MASK1_MASKP2_Msk (0x01UL << GPIO_PORT_MASK1_MASKP2_Pos) /*!< GPIO_PORT MASK1: MASKP2 Mask */
+#define GPIO_PORT_MASK1_MASKP3_Pos 3 /*!< GPIO_PORT MASK1: MASKP3 Position */
+#define GPIO_PORT_MASK1_MASKP3_Msk (0x01UL << GPIO_PORT_MASK1_MASKP3_Pos) /*!< GPIO_PORT MASK1: MASKP3 Mask */
+#define GPIO_PORT_MASK1_MASKP4_Pos 4 /*!< GPIO_PORT MASK1: MASKP4 Position */
+#define GPIO_PORT_MASK1_MASKP4_Msk (0x01UL << GPIO_PORT_MASK1_MASKP4_Pos) /*!< GPIO_PORT MASK1: MASKP4 Mask */
+#define GPIO_PORT_MASK1_MASKP5_Pos 5 /*!< GPIO_PORT MASK1: MASKP5 Position */
+#define GPIO_PORT_MASK1_MASKP5_Msk (0x01UL << GPIO_PORT_MASK1_MASKP5_Pos) /*!< GPIO_PORT MASK1: MASKP5 Mask */
+#define GPIO_PORT_MASK1_MASKP6_Pos 6 /*!< GPIO_PORT MASK1: MASKP6 Position */
+#define GPIO_PORT_MASK1_MASKP6_Msk (0x01UL << GPIO_PORT_MASK1_MASKP6_Pos) /*!< GPIO_PORT MASK1: MASKP6 Mask */
+#define GPIO_PORT_MASK1_MASKP7_Pos 7 /*!< GPIO_PORT MASK1: MASKP7 Position */
+#define GPIO_PORT_MASK1_MASKP7_Msk (0x01UL << GPIO_PORT_MASK1_MASKP7_Pos) /*!< GPIO_PORT MASK1: MASKP7 Mask */
+#define GPIO_PORT_MASK1_MASKP8_Pos 8 /*!< GPIO_PORT MASK1: MASKP8 Position */
+#define GPIO_PORT_MASK1_MASKP8_Msk (0x01UL << GPIO_PORT_MASK1_MASKP8_Pos) /*!< GPIO_PORT MASK1: MASKP8 Mask */
+#define GPIO_PORT_MASK1_MASKP9_Pos 9 /*!< GPIO_PORT MASK1: MASKP9 Position */
+#define GPIO_PORT_MASK1_MASKP9_Msk (0x01UL << GPIO_PORT_MASK1_MASKP9_Pos) /*!< GPIO_PORT MASK1: MASKP9 Mask */
+#define GPIO_PORT_MASK1_MASKP10_Pos 10 /*!< GPIO_PORT MASK1: MASKP10 Position */
+#define GPIO_PORT_MASK1_MASKP10_Msk (0x01UL << GPIO_PORT_MASK1_MASKP10_Pos) /*!< GPIO_PORT MASK1: MASKP10 Mask */
+#define GPIO_PORT_MASK1_MASKP11_Pos 11 /*!< GPIO_PORT MASK1: MASKP11 Position */
+#define GPIO_PORT_MASK1_MASKP11_Msk (0x01UL << GPIO_PORT_MASK1_MASKP11_Pos) /*!< GPIO_PORT MASK1: MASKP11 Mask */
+#define GPIO_PORT_MASK1_MASKP12_Pos 12 /*!< GPIO_PORT MASK1: MASKP12 Position */
+#define GPIO_PORT_MASK1_MASKP12_Msk (0x01UL << GPIO_PORT_MASK1_MASKP12_Pos) /*!< GPIO_PORT MASK1: MASKP12 Mask */
+#define GPIO_PORT_MASK1_MASKP13_Pos 13 /*!< GPIO_PORT MASK1: MASKP13 Position */
+#define GPIO_PORT_MASK1_MASKP13_Msk (0x01UL << GPIO_PORT_MASK1_MASKP13_Pos) /*!< GPIO_PORT MASK1: MASKP13 Mask */
+#define GPIO_PORT_MASK1_MASKP14_Pos 14 /*!< GPIO_PORT MASK1: MASKP14 Position */
+#define GPIO_PORT_MASK1_MASKP14_Msk (0x01UL << GPIO_PORT_MASK1_MASKP14_Pos) /*!< GPIO_PORT MASK1: MASKP14 Mask */
+#define GPIO_PORT_MASK1_MASKP15_Pos 15 /*!< GPIO_PORT MASK1: MASKP15 Position */
+#define GPIO_PORT_MASK1_MASKP15_Msk (0x01UL << GPIO_PORT_MASK1_MASKP15_Pos) /*!< GPIO_PORT MASK1: MASKP15 Mask */
+#define GPIO_PORT_MASK1_MASKP16_Pos 16 /*!< GPIO_PORT MASK1: MASKP16 Position */
+#define GPIO_PORT_MASK1_MASKP16_Msk (0x01UL << GPIO_PORT_MASK1_MASKP16_Pos) /*!< GPIO_PORT MASK1: MASKP16 Mask */
+#define GPIO_PORT_MASK1_MASKP17_Pos 17 /*!< GPIO_PORT MASK1: MASKP17 Position */
+#define GPIO_PORT_MASK1_MASKP17_Msk (0x01UL << GPIO_PORT_MASK1_MASKP17_Pos) /*!< GPIO_PORT MASK1: MASKP17 Mask */
+#define GPIO_PORT_MASK1_MASKP18_Pos 18 /*!< GPIO_PORT MASK1: MASKP18 Position */
+#define GPIO_PORT_MASK1_MASKP18_Msk (0x01UL << GPIO_PORT_MASK1_MASKP18_Pos) /*!< GPIO_PORT MASK1: MASKP18 Mask */
+#define GPIO_PORT_MASK1_MASKP19_Pos 19 /*!< GPIO_PORT MASK1: MASKP19 Position */
+#define GPIO_PORT_MASK1_MASKP19_Msk (0x01UL << GPIO_PORT_MASK1_MASKP19_Pos) /*!< GPIO_PORT MASK1: MASKP19 Mask */
+#define GPIO_PORT_MASK1_MASKP20_Pos 20 /*!< GPIO_PORT MASK1: MASKP20 Position */
+#define GPIO_PORT_MASK1_MASKP20_Msk (0x01UL << GPIO_PORT_MASK1_MASKP20_Pos) /*!< GPIO_PORT MASK1: MASKP20 Mask */
+#define GPIO_PORT_MASK1_MASKP21_Pos 21 /*!< GPIO_PORT MASK1: MASKP21 Position */
+#define GPIO_PORT_MASK1_MASKP21_Msk (0x01UL << GPIO_PORT_MASK1_MASKP21_Pos) /*!< GPIO_PORT MASK1: MASKP21 Mask */
+#define GPIO_PORT_MASK1_MASKP22_Pos 22 /*!< GPIO_PORT MASK1: MASKP22 Position */
+#define GPIO_PORT_MASK1_MASKP22_Msk (0x01UL << GPIO_PORT_MASK1_MASKP22_Pos) /*!< GPIO_PORT MASK1: MASKP22 Mask */
+#define GPIO_PORT_MASK1_MASKP23_Pos 23 /*!< GPIO_PORT MASK1: MASKP23 Position */
+#define GPIO_PORT_MASK1_MASKP23_Msk (0x01UL << GPIO_PORT_MASK1_MASKP23_Pos) /*!< GPIO_PORT MASK1: MASKP23 Mask */
+#define GPIO_PORT_MASK1_MASKP24_Pos 24 /*!< GPIO_PORT MASK1: MASKP24 Position */
+#define GPIO_PORT_MASK1_MASKP24_Msk (0x01UL << GPIO_PORT_MASK1_MASKP24_Pos) /*!< GPIO_PORT MASK1: MASKP24 Mask */
+#define GPIO_PORT_MASK1_MASKP25_Pos 25 /*!< GPIO_PORT MASK1: MASKP25 Position */
+#define GPIO_PORT_MASK1_MASKP25_Msk (0x01UL << GPIO_PORT_MASK1_MASKP25_Pos) /*!< GPIO_PORT MASK1: MASKP25 Mask */
+#define GPIO_PORT_MASK1_MASKP26_Pos 26 /*!< GPIO_PORT MASK1: MASKP26 Position */
+#define GPIO_PORT_MASK1_MASKP26_Msk (0x01UL << GPIO_PORT_MASK1_MASKP26_Pos) /*!< GPIO_PORT MASK1: MASKP26 Mask */
+#define GPIO_PORT_MASK1_MASKP27_Pos 27 /*!< GPIO_PORT MASK1: MASKP27 Position */
+#define GPIO_PORT_MASK1_MASKP27_Msk (0x01UL << GPIO_PORT_MASK1_MASKP27_Pos) /*!< GPIO_PORT MASK1: MASKP27 Mask */
+#define GPIO_PORT_MASK1_MASKP28_Pos 28 /*!< GPIO_PORT MASK1: MASKP28 Position */
+#define GPIO_PORT_MASK1_MASKP28_Msk (0x01UL << GPIO_PORT_MASK1_MASKP28_Pos) /*!< GPIO_PORT MASK1: MASKP28 Mask */
+#define GPIO_PORT_MASK1_MASKP29_Pos 29 /*!< GPIO_PORT MASK1: MASKP29 Position */
+#define GPIO_PORT_MASK1_MASKP29_Msk (0x01UL << GPIO_PORT_MASK1_MASKP29_Pos) /*!< GPIO_PORT MASK1: MASKP29 Mask */
+#define GPIO_PORT_MASK1_MASKP30_Pos 30 /*!< GPIO_PORT MASK1: MASKP30 Position */
+#define GPIO_PORT_MASK1_MASKP30_Msk (0x01UL << GPIO_PORT_MASK1_MASKP30_Pos) /*!< GPIO_PORT MASK1: MASKP30 Mask */
+#define GPIO_PORT_MASK1_MASKP31_Pos 31 /*!< GPIO_PORT MASK1: MASKP31 Position */
+#define GPIO_PORT_MASK1_MASKP31_Msk (0x01UL << GPIO_PORT_MASK1_MASKP31_Pos) /*!< GPIO_PORT MASK1: MASKP31 Mask */
+
+// ------------------------------------- GPIO_PORT_MASK2 ----------------------------------------
+#define GPIO_PORT_MASK2_MASKP0_Pos 0 /*!< GPIO_PORT MASK2: MASKP0 Position */
+#define GPIO_PORT_MASK2_MASKP0_Msk (0x01UL << GPIO_PORT_MASK2_MASKP0_Pos) /*!< GPIO_PORT MASK2: MASKP0 Mask */
+#define GPIO_PORT_MASK2_MASKP1_Pos 1 /*!< GPIO_PORT MASK2: MASKP1 Position */
+#define GPIO_PORT_MASK2_MASKP1_Msk (0x01UL << GPIO_PORT_MASK2_MASKP1_Pos) /*!< GPIO_PORT MASK2: MASKP1 Mask */
+#define GPIO_PORT_MASK2_MASKP2_Pos 2 /*!< GPIO_PORT MASK2: MASKP2 Position */
+#define GPIO_PORT_MASK2_MASKP2_Msk (0x01UL << GPIO_PORT_MASK2_MASKP2_Pos) /*!< GPIO_PORT MASK2: MASKP2 Mask */
+#define GPIO_PORT_MASK2_MASKP3_Pos 3 /*!< GPIO_PORT MASK2: MASKP3 Position */
+#define GPIO_PORT_MASK2_MASKP3_Msk (0x01UL << GPIO_PORT_MASK2_MASKP3_Pos) /*!< GPIO_PORT MASK2: MASKP3 Mask */
+#define GPIO_PORT_MASK2_MASKP4_Pos 4 /*!< GPIO_PORT MASK2: MASKP4 Position */
+#define GPIO_PORT_MASK2_MASKP4_Msk (0x01UL << GPIO_PORT_MASK2_MASKP4_Pos) /*!< GPIO_PORT MASK2: MASKP4 Mask */
+#define GPIO_PORT_MASK2_MASKP5_Pos 5 /*!< GPIO_PORT MASK2: MASKP5 Position */
+#define GPIO_PORT_MASK2_MASKP5_Msk (0x01UL << GPIO_PORT_MASK2_MASKP5_Pos) /*!< GPIO_PORT MASK2: MASKP5 Mask */
+#define GPIO_PORT_MASK2_MASKP6_Pos 6 /*!< GPIO_PORT MASK2: MASKP6 Position */
+#define GPIO_PORT_MASK2_MASKP6_Msk (0x01UL << GPIO_PORT_MASK2_MASKP6_Pos) /*!< GPIO_PORT MASK2: MASKP6 Mask */
+#define GPIO_PORT_MASK2_MASKP7_Pos 7 /*!< GPIO_PORT MASK2: MASKP7 Position */
+#define GPIO_PORT_MASK2_MASKP7_Msk (0x01UL << GPIO_PORT_MASK2_MASKP7_Pos) /*!< GPIO_PORT MASK2: MASKP7 Mask */
+#define GPIO_PORT_MASK2_MASKP8_Pos 8 /*!< GPIO_PORT MASK2: MASKP8 Position */
+#define GPIO_PORT_MASK2_MASKP8_Msk (0x01UL << GPIO_PORT_MASK2_MASKP8_Pos) /*!< GPIO_PORT MASK2: MASKP8 Mask */
+#define GPIO_PORT_MASK2_MASKP9_Pos 9 /*!< GPIO_PORT MASK2: MASKP9 Position */
+#define GPIO_PORT_MASK2_MASKP9_Msk (0x01UL << GPIO_PORT_MASK2_MASKP9_Pos) /*!< GPIO_PORT MASK2: MASKP9 Mask */
+#define GPIO_PORT_MASK2_MASKP10_Pos 10 /*!< GPIO_PORT MASK2: MASKP10 Position */
+#define GPIO_PORT_MASK2_MASKP10_Msk (0x01UL << GPIO_PORT_MASK2_MASKP10_Pos) /*!< GPIO_PORT MASK2: MASKP10 Mask */
+#define GPIO_PORT_MASK2_MASKP11_Pos 11 /*!< GPIO_PORT MASK2: MASKP11 Position */
+#define GPIO_PORT_MASK2_MASKP11_Msk (0x01UL << GPIO_PORT_MASK2_MASKP11_Pos) /*!< GPIO_PORT MASK2: MASKP11 Mask */
+#define GPIO_PORT_MASK2_MASKP12_Pos 12 /*!< GPIO_PORT MASK2: MASKP12 Position */
+#define GPIO_PORT_MASK2_MASKP12_Msk (0x01UL << GPIO_PORT_MASK2_MASKP12_Pos) /*!< GPIO_PORT MASK2: MASKP12 Mask */
+#define GPIO_PORT_MASK2_MASKP13_Pos 13 /*!< GPIO_PORT MASK2: MASKP13 Position */
+#define GPIO_PORT_MASK2_MASKP13_Msk (0x01UL << GPIO_PORT_MASK2_MASKP13_Pos) /*!< GPIO_PORT MASK2: MASKP13 Mask */
+#define GPIO_PORT_MASK2_MASKP14_Pos 14 /*!< GPIO_PORT MASK2: MASKP14 Position */
+#define GPIO_PORT_MASK2_MASKP14_Msk (0x01UL << GPIO_PORT_MASK2_MASKP14_Pos) /*!< GPIO_PORT MASK2: MASKP14 Mask */
+#define GPIO_PORT_MASK2_MASKP15_Pos 15 /*!< GPIO_PORT MASK2: MASKP15 Position */
+#define GPIO_PORT_MASK2_MASKP15_Msk (0x01UL << GPIO_PORT_MASK2_MASKP15_Pos) /*!< GPIO_PORT MASK2: MASKP15 Mask */
+#define GPIO_PORT_MASK2_MASKP16_Pos 16 /*!< GPIO_PORT MASK2: MASKP16 Position */
+#define GPIO_PORT_MASK2_MASKP16_Msk (0x01UL << GPIO_PORT_MASK2_MASKP16_Pos) /*!< GPIO_PORT MASK2: MASKP16 Mask */
+#define GPIO_PORT_MASK2_MASKP17_Pos 17 /*!< GPIO_PORT MASK2: MASKP17 Position */
+#define GPIO_PORT_MASK2_MASKP17_Msk (0x01UL << GPIO_PORT_MASK2_MASKP17_Pos) /*!< GPIO_PORT MASK2: MASKP17 Mask */
+#define GPIO_PORT_MASK2_MASKP18_Pos 18 /*!< GPIO_PORT MASK2: MASKP18 Position */
+#define GPIO_PORT_MASK2_MASKP18_Msk (0x01UL << GPIO_PORT_MASK2_MASKP18_Pos) /*!< GPIO_PORT MASK2: MASKP18 Mask */
+#define GPIO_PORT_MASK2_MASKP19_Pos 19 /*!< GPIO_PORT MASK2: MASKP19 Position */
+#define GPIO_PORT_MASK2_MASKP19_Msk (0x01UL << GPIO_PORT_MASK2_MASKP19_Pos) /*!< GPIO_PORT MASK2: MASKP19 Mask */
+#define GPIO_PORT_MASK2_MASKP20_Pos 20 /*!< GPIO_PORT MASK2: MASKP20 Position */
+#define GPIO_PORT_MASK2_MASKP20_Msk (0x01UL << GPIO_PORT_MASK2_MASKP20_Pos) /*!< GPIO_PORT MASK2: MASKP20 Mask */
+#define GPIO_PORT_MASK2_MASKP21_Pos 21 /*!< GPIO_PORT MASK2: MASKP21 Position */
+#define GPIO_PORT_MASK2_MASKP21_Msk (0x01UL << GPIO_PORT_MASK2_MASKP21_Pos) /*!< GPIO_PORT MASK2: MASKP21 Mask */
+#define GPIO_PORT_MASK2_MASKP22_Pos 22 /*!< GPIO_PORT MASK2: MASKP22 Position */
+#define GPIO_PORT_MASK2_MASKP22_Msk (0x01UL << GPIO_PORT_MASK2_MASKP22_Pos) /*!< GPIO_PORT MASK2: MASKP22 Mask */
+#define GPIO_PORT_MASK2_MASKP23_Pos 23 /*!< GPIO_PORT MASK2: MASKP23 Position */
+#define GPIO_PORT_MASK2_MASKP23_Msk (0x01UL << GPIO_PORT_MASK2_MASKP23_Pos) /*!< GPIO_PORT MASK2: MASKP23 Mask */
+#define GPIO_PORT_MASK2_MASKP24_Pos 24 /*!< GPIO_PORT MASK2: MASKP24 Position */
+#define GPIO_PORT_MASK2_MASKP24_Msk (0x01UL << GPIO_PORT_MASK2_MASKP24_Pos) /*!< GPIO_PORT MASK2: MASKP24 Mask */
+#define GPIO_PORT_MASK2_MASKP25_Pos 25 /*!< GPIO_PORT MASK2: MASKP25 Position */
+#define GPIO_PORT_MASK2_MASKP25_Msk (0x01UL << GPIO_PORT_MASK2_MASKP25_Pos) /*!< GPIO_PORT MASK2: MASKP25 Mask */
+#define GPIO_PORT_MASK2_MASKP26_Pos 26 /*!< GPIO_PORT MASK2: MASKP26 Position */
+#define GPIO_PORT_MASK2_MASKP26_Msk (0x01UL << GPIO_PORT_MASK2_MASKP26_Pos) /*!< GPIO_PORT MASK2: MASKP26 Mask */
+#define GPIO_PORT_MASK2_MASKP27_Pos 27 /*!< GPIO_PORT MASK2: MASKP27 Position */
+#define GPIO_PORT_MASK2_MASKP27_Msk (0x01UL << GPIO_PORT_MASK2_MASKP27_Pos) /*!< GPIO_PORT MASK2: MASKP27 Mask */
+#define GPIO_PORT_MASK2_MASKP28_Pos 28 /*!< GPIO_PORT MASK2: MASKP28 Position */
+#define GPIO_PORT_MASK2_MASKP28_Msk (0x01UL << GPIO_PORT_MASK2_MASKP28_Pos) /*!< GPIO_PORT MASK2: MASKP28 Mask */
+#define GPIO_PORT_MASK2_MASKP29_Pos 29 /*!< GPIO_PORT MASK2: MASKP29 Position */
+#define GPIO_PORT_MASK2_MASKP29_Msk (0x01UL << GPIO_PORT_MASK2_MASKP29_Pos) /*!< GPIO_PORT MASK2: MASKP29 Mask */
+#define GPIO_PORT_MASK2_MASKP30_Pos 30 /*!< GPIO_PORT MASK2: MASKP30 Position */
+#define GPIO_PORT_MASK2_MASKP30_Msk (0x01UL << GPIO_PORT_MASK2_MASKP30_Pos) /*!< GPIO_PORT MASK2: MASKP30 Mask */
+#define GPIO_PORT_MASK2_MASKP31_Pos 31 /*!< GPIO_PORT MASK2: MASKP31 Position */
+#define GPIO_PORT_MASK2_MASKP31_Msk (0x01UL << GPIO_PORT_MASK2_MASKP31_Pos) /*!< GPIO_PORT MASK2: MASKP31 Mask */
+
+// ------------------------------------- GPIO_PORT_MASK3 ----------------------------------------
+#define GPIO_PORT_MASK3_MASKP0_Pos 0 /*!< GPIO_PORT MASK3: MASKP0 Position */
+#define GPIO_PORT_MASK3_MASKP0_Msk (0x01UL << GPIO_PORT_MASK3_MASKP0_Pos) /*!< GPIO_PORT MASK3: MASKP0 Mask */
+#define GPIO_PORT_MASK3_MASKP1_Pos 1 /*!< GPIO_PORT MASK3: MASKP1 Position */
+#define GPIO_PORT_MASK3_MASKP1_Msk (0x01UL << GPIO_PORT_MASK3_MASKP1_Pos) /*!< GPIO_PORT MASK3: MASKP1 Mask */
+#define GPIO_PORT_MASK3_MASKP2_Pos 2 /*!< GPIO_PORT MASK3: MASKP2 Position */
+#define GPIO_PORT_MASK3_MASKP2_Msk (0x01UL << GPIO_PORT_MASK3_MASKP2_Pos) /*!< GPIO_PORT MASK3: MASKP2 Mask */
+#define GPIO_PORT_MASK3_MASKP3_Pos 3 /*!< GPIO_PORT MASK3: MASKP3 Position */
+#define GPIO_PORT_MASK3_MASKP3_Msk (0x01UL << GPIO_PORT_MASK3_MASKP3_Pos) /*!< GPIO_PORT MASK3: MASKP3 Mask */
+#define GPIO_PORT_MASK3_MASKP4_Pos 4 /*!< GPIO_PORT MASK3: MASKP4 Position */
+#define GPIO_PORT_MASK3_MASKP4_Msk (0x01UL << GPIO_PORT_MASK3_MASKP4_Pos) /*!< GPIO_PORT MASK3: MASKP4 Mask */
+#define GPIO_PORT_MASK3_MASKP5_Pos 5 /*!< GPIO_PORT MASK3: MASKP5 Position */
+#define GPIO_PORT_MASK3_MASKP5_Msk (0x01UL << GPIO_PORT_MASK3_MASKP5_Pos) /*!< GPIO_PORT MASK3: MASKP5 Mask */
+#define GPIO_PORT_MASK3_MASKP6_Pos 6 /*!< GPIO_PORT MASK3: MASKP6 Position */
+#define GPIO_PORT_MASK3_MASKP6_Msk (0x01UL << GPIO_PORT_MASK3_MASKP6_Pos) /*!< GPIO_PORT MASK3: MASKP6 Mask */
+#define GPIO_PORT_MASK3_MASKP7_Pos 7 /*!< GPIO_PORT MASK3: MASKP7 Position */
+#define GPIO_PORT_MASK3_MASKP7_Msk (0x01UL << GPIO_PORT_MASK3_MASKP7_Pos) /*!< GPIO_PORT MASK3: MASKP7 Mask */
+#define GPIO_PORT_MASK3_MASKP8_Pos 8 /*!< GPIO_PORT MASK3: MASKP8 Position */
+#define GPIO_PORT_MASK3_MASKP8_Msk (0x01UL << GPIO_PORT_MASK3_MASKP8_Pos) /*!< GPIO_PORT MASK3: MASKP8 Mask */
+#define GPIO_PORT_MASK3_MASKP9_Pos 9 /*!< GPIO_PORT MASK3: MASKP9 Position */
+#define GPIO_PORT_MASK3_MASKP9_Msk (0x01UL << GPIO_PORT_MASK3_MASKP9_Pos) /*!< GPIO_PORT MASK3: MASKP9 Mask */
+#define GPIO_PORT_MASK3_MASKP10_Pos 10 /*!< GPIO_PORT MASK3: MASKP10 Position */
+#define GPIO_PORT_MASK3_MASKP10_Msk (0x01UL << GPIO_PORT_MASK3_MASKP10_Pos) /*!< GPIO_PORT MASK3: MASKP10 Mask */
+#define GPIO_PORT_MASK3_MASKP11_Pos 11 /*!< GPIO_PORT MASK3: MASKP11 Position */
+#define GPIO_PORT_MASK3_MASKP11_Msk (0x01UL << GPIO_PORT_MASK3_MASKP11_Pos) /*!< GPIO_PORT MASK3: MASKP11 Mask */
+#define GPIO_PORT_MASK3_MASKP12_Pos 12 /*!< GPIO_PORT MASK3: MASKP12 Position */
+#define GPIO_PORT_MASK3_MASKP12_Msk (0x01UL << GPIO_PORT_MASK3_MASKP12_Pos) /*!< GPIO_PORT MASK3: MASKP12 Mask */
+#define GPIO_PORT_MASK3_MASKP13_Pos 13 /*!< GPIO_PORT MASK3: MASKP13 Position */
+#define GPIO_PORT_MASK3_MASKP13_Msk (0x01UL << GPIO_PORT_MASK3_MASKP13_Pos) /*!< GPIO_PORT MASK3: MASKP13 Mask */
+#define GPIO_PORT_MASK3_MASKP14_Pos 14 /*!< GPIO_PORT MASK3: MASKP14 Position */
+#define GPIO_PORT_MASK3_MASKP14_Msk (0x01UL << GPIO_PORT_MASK3_MASKP14_Pos) /*!< GPIO_PORT MASK3: MASKP14 Mask */
+#define GPIO_PORT_MASK3_MASKP15_Pos 15 /*!< GPIO_PORT MASK3: MASKP15 Position */
+#define GPIO_PORT_MASK3_MASKP15_Msk (0x01UL << GPIO_PORT_MASK3_MASKP15_Pos) /*!< GPIO_PORT MASK3: MASKP15 Mask */
+#define GPIO_PORT_MASK3_MASKP16_Pos 16 /*!< GPIO_PORT MASK3: MASKP16 Position */
+#define GPIO_PORT_MASK3_MASKP16_Msk (0x01UL << GPIO_PORT_MASK3_MASKP16_Pos) /*!< GPIO_PORT MASK3: MASKP16 Mask */
+#define GPIO_PORT_MASK3_MASKP17_Pos 17 /*!< GPIO_PORT MASK3: MASKP17 Position */
+#define GPIO_PORT_MASK3_MASKP17_Msk (0x01UL << GPIO_PORT_MASK3_MASKP17_Pos) /*!< GPIO_PORT MASK3: MASKP17 Mask */
+#define GPIO_PORT_MASK3_MASKP18_Pos 18 /*!< GPIO_PORT MASK3: MASKP18 Position */
+#define GPIO_PORT_MASK3_MASKP18_Msk (0x01UL << GPIO_PORT_MASK3_MASKP18_Pos) /*!< GPIO_PORT MASK3: MASKP18 Mask */
+#define GPIO_PORT_MASK3_MASKP19_Pos 19 /*!< GPIO_PORT MASK3: MASKP19 Position */
+#define GPIO_PORT_MASK3_MASKP19_Msk (0x01UL << GPIO_PORT_MASK3_MASKP19_Pos) /*!< GPIO_PORT MASK3: MASKP19 Mask */
+#define GPIO_PORT_MASK3_MASKP20_Pos 20 /*!< GPIO_PORT MASK3: MASKP20 Position */
+#define GPIO_PORT_MASK3_MASKP20_Msk (0x01UL << GPIO_PORT_MASK3_MASKP20_Pos) /*!< GPIO_PORT MASK3: MASKP20 Mask */
+#define GPIO_PORT_MASK3_MASKP21_Pos 21 /*!< GPIO_PORT MASK3: MASKP21 Position */
+#define GPIO_PORT_MASK3_MASKP21_Msk (0x01UL << GPIO_PORT_MASK3_MASKP21_Pos) /*!< GPIO_PORT MASK3: MASKP21 Mask */
+#define GPIO_PORT_MASK3_MASKP22_Pos 22 /*!< GPIO_PORT MASK3: MASKP22 Position */
+#define GPIO_PORT_MASK3_MASKP22_Msk (0x01UL << GPIO_PORT_MASK3_MASKP22_Pos) /*!< GPIO_PORT MASK3: MASKP22 Mask */
+#define GPIO_PORT_MASK3_MASKP23_Pos 23 /*!< GPIO_PORT MASK3: MASKP23 Position */
+#define GPIO_PORT_MASK3_MASKP23_Msk (0x01UL << GPIO_PORT_MASK3_MASKP23_Pos) /*!< GPIO_PORT MASK3: MASKP23 Mask */
+#define GPIO_PORT_MASK3_MASKP24_Pos 24 /*!< GPIO_PORT MASK3: MASKP24 Position */
+#define GPIO_PORT_MASK3_MASKP24_Msk (0x01UL << GPIO_PORT_MASK3_MASKP24_Pos) /*!< GPIO_PORT MASK3: MASKP24 Mask */
+#define GPIO_PORT_MASK3_MASKP25_Pos 25 /*!< GPIO_PORT MASK3: MASKP25 Position */
+#define GPIO_PORT_MASK3_MASKP25_Msk (0x01UL << GPIO_PORT_MASK3_MASKP25_Pos) /*!< GPIO_PORT MASK3: MASKP25 Mask */
+#define GPIO_PORT_MASK3_MASKP26_Pos 26 /*!< GPIO_PORT MASK3: MASKP26 Position */
+#define GPIO_PORT_MASK3_MASKP26_Msk (0x01UL << GPIO_PORT_MASK3_MASKP26_Pos) /*!< GPIO_PORT MASK3: MASKP26 Mask */
+#define GPIO_PORT_MASK3_MASKP27_Pos 27 /*!< GPIO_PORT MASK3: MASKP27 Position */
+#define GPIO_PORT_MASK3_MASKP27_Msk (0x01UL << GPIO_PORT_MASK3_MASKP27_Pos) /*!< GPIO_PORT MASK3: MASKP27 Mask */
+#define GPIO_PORT_MASK3_MASKP28_Pos 28 /*!< GPIO_PORT MASK3: MASKP28 Position */
+#define GPIO_PORT_MASK3_MASKP28_Msk (0x01UL << GPIO_PORT_MASK3_MASKP28_Pos) /*!< GPIO_PORT MASK3: MASKP28 Mask */
+#define GPIO_PORT_MASK3_MASKP29_Pos 29 /*!< GPIO_PORT MASK3: MASKP29 Position */
+#define GPIO_PORT_MASK3_MASKP29_Msk (0x01UL << GPIO_PORT_MASK3_MASKP29_Pos) /*!< GPIO_PORT MASK3: MASKP29 Mask */
+#define GPIO_PORT_MASK3_MASKP30_Pos 30 /*!< GPIO_PORT MASK3: MASKP30 Position */
+#define GPIO_PORT_MASK3_MASKP30_Msk (0x01UL << GPIO_PORT_MASK3_MASKP30_Pos) /*!< GPIO_PORT MASK3: MASKP30 Mask */
+#define GPIO_PORT_MASK3_MASKP31_Pos 31 /*!< GPIO_PORT MASK3: MASKP31 Position */
+#define GPIO_PORT_MASK3_MASKP31_Msk (0x01UL << GPIO_PORT_MASK3_MASKP31_Pos) /*!< GPIO_PORT MASK3: MASKP31 Mask */
+
+// ------------------------------------- GPIO_PORT_MASK4 ----------------------------------------
+#define GPIO_PORT_MASK4_MASKP0_Pos 0 /*!< GPIO_PORT MASK4: MASKP0 Position */
+#define GPIO_PORT_MASK4_MASKP0_Msk (0x01UL << GPIO_PORT_MASK4_MASKP0_Pos) /*!< GPIO_PORT MASK4: MASKP0 Mask */
+#define GPIO_PORT_MASK4_MASKP1_Pos 1 /*!< GPIO_PORT MASK4: MASKP1 Position */
+#define GPIO_PORT_MASK4_MASKP1_Msk (0x01UL << GPIO_PORT_MASK4_MASKP1_Pos) /*!< GPIO_PORT MASK4: MASKP1 Mask */
+#define GPIO_PORT_MASK4_MASKP2_Pos 2 /*!< GPIO_PORT MASK4: MASKP2 Position */
+#define GPIO_PORT_MASK4_MASKP2_Msk (0x01UL << GPIO_PORT_MASK4_MASKP2_Pos) /*!< GPIO_PORT MASK4: MASKP2 Mask */
+#define GPIO_PORT_MASK4_MASKP3_Pos 3 /*!< GPIO_PORT MASK4: MASKP3 Position */
+#define GPIO_PORT_MASK4_MASKP3_Msk (0x01UL << GPIO_PORT_MASK4_MASKP3_Pos) /*!< GPIO_PORT MASK4: MASKP3 Mask */
+#define GPIO_PORT_MASK4_MASKP4_Pos 4 /*!< GPIO_PORT MASK4: MASKP4 Position */
+#define GPIO_PORT_MASK4_MASKP4_Msk (0x01UL << GPIO_PORT_MASK4_MASKP4_Pos) /*!< GPIO_PORT MASK4: MASKP4 Mask */
+#define GPIO_PORT_MASK4_MASKP5_Pos 5 /*!< GPIO_PORT MASK4: MASKP5 Position */
+#define GPIO_PORT_MASK4_MASKP5_Msk (0x01UL << GPIO_PORT_MASK4_MASKP5_Pos) /*!< GPIO_PORT MASK4: MASKP5 Mask */
+#define GPIO_PORT_MASK4_MASKP6_Pos 6 /*!< GPIO_PORT MASK4: MASKP6 Position */
+#define GPIO_PORT_MASK4_MASKP6_Msk (0x01UL << GPIO_PORT_MASK4_MASKP6_Pos) /*!< GPIO_PORT MASK4: MASKP6 Mask */
+#define GPIO_PORT_MASK4_MASKP7_Pos 7 /*!< GPIO_PORT MASK4: MASKP7 Position */
+#define GPIO_PORT_MASK4_MASKP7_Msk (0x01UL << GPIO_PORT_MASK4_MASKP7_Pos) /*!< GPIO_PORT MASK4: MASKP7 Mask */
+#define GPIO_PORT_MASK4_MASKP8_Pos 8 /*!< GPIO_PORT MASK4: MASKP8 Position */
+#define GPIO_PORT_MASK4_MASKP8_Msk (0x01UL << GPIO_PORT_MASK4_MASKP8_Pos) /*!< GPIO_PORT MASK4: MASKP8 Mask */
+#define GPIO_PORT_MASK4_MASKP9_Pos 9 /*!< GPIO_PORT MASK4: MASKP9 Position */
+#define GPIO_PORT_MASK4_MASKP9_Msk (0x01UL << GPIO_PORT_MASK4_MASKP9_Pos) /*!< GPIO_PORT MASK4: MASKP9 Mask */
+#define GPIO_PORT_MASK4_MASKP10_Pos 10 /*!< GPIO_PORT MASK4: MASKP10 Position */
+#define GPIO_PORT_MASK4_MASKP10_Msk (0x01UL << GPIO_PORT_MASK4_MASKP10_Pos) /*!< GPIO_PORT MASK4: MASKP10 Mask */
+#define GPIO_PORT_MASK4_MASKP11_Pos 11 /*!< GPIO_PORT MASK4: MASKP11 Position */
+#define GPIO_PORT_MASK4_MASKP11_Msk (0x01UL << GPIO_PORT_MASK4_MASKP11_Pos) /*!< GPIO_PORT MASK4: MASKP11 Mask */
+#define GPIO_PORT_MASK4_MASKP12_Pos 12 /*!< GPIO_PORT MASK4: MASKP12 Position */
+#define GPIO_PORT_MASK4_MASKP12_Msk (0x01UL << GPIO_PORT_MASK4_MASKP12_Pos) /*!< GPIO_PORT MASK4: MASKP12 Mask */
+#define GPIO_PORT_MASK4_MASKP13_Pos 13 /*!< GPIO_PORT MASK4: MASKP13 Position */
+#define GPIO_PORT_MASK4_MASKP13_Msk (0x01UL << GPIO_PORT_MASK4_MASKP13_Pos) /*!< GPIO_PORT MASK4: MASKP13 Mask */
+#define GPIO_PORT_MASK4_MASKP14_Pos 14 /*!< GPIO_PORT MASK4: MASKP14 Position */
+#define GPIO_PORT_MASK4_MASKP14_Msk (0x01UL << GPIO_PORT_MASK4_MASKP14_Pos) /*!< GPIO_PORT MASK4: MASKP14 Mask */
+#define GPIO_PORT_MASK4_MASKP15_Pos 15 /*!< GPIO_PORT MASK4: MASKP15 Position */
+#define GPIO_PORT_MASK4_MASKP15_Msk (0x01UL << GPIO_PORT_MASK4_MASKP15_Pos) /*!< GPIO_PORT MASK4: MASKP15 Mask */
+#define GPIO_PORT_MASK4_MASKP16_Pos 16 /*!< GPIO_PORT MASK4: MASKP16 Position */
+#define GPIO_PORT_MASK4_MASKP16_Msk (0x01UL << GPIO_PORT_MASK4_MASKP16_Pos) /*!< GPIO_PORT MASK4: MASKP16 Mask */
+#define GPIO_PORT_MASK4_MASKP17_Pos 17 /*!< GPIO_PORT MASK4: MASKP17 Position */
+#define GPIO_PORT_MASK4_MASKP17_Msk (0x01UL << GPIO_PORT_MASK4_MASKP17_Pos) /*!< GPIO_PORT MASK4: MASKP17 Mask */
+#define GPIO_PORT_MASK4_MASKP18_Pos 18 /*!< GPIO_PORT MASK4: MASKP18 Position */
+#define GPIO_PORT_MASK4_MASKP18_Msk (0x01UL << GPIO_PORT_MASK4_MASKP18_Pos) /*!< GPIO_PORT MASK4: MASKP18 Mask */
+#define GPIO_PORT_MASK4_MASKP19_Pos 19 /*!< GPIO_PORT MASK4: MASKP19 Position */
+#define GPIO_PORT_MASK4_MASKP19_Msk (0x01UL << GPIO_PORT_MASK4_MASKP19_Pos) /*!< GPIO_PORT MASK4: MASKP19 Mask */
+#define GPIO_PORT_MASK4_MASKP20_Pos 20 /*!< GPIO_PORT MASK4: MASKP20 Position */
+#define GPIO_PORT_MASK4_MASKP20_Msk (0x01UL << GPIO_PORT_MASK4_MASKP20_Pos) /*!< GPIO_PORT MASK4: MASKP20 Mask */
+#define GPIO_PORT_MASK4_MASKP21_Pos 21 /*!< GPIO_PORT MASK4: MASKP21 Position */
+#define GPIO_PORT_MASK4_MASKP21_Msk (0x01UL << GPIO_PORT_MASK4_MASKP21_Pos) /*!< GPIO_PORT MASK4: MASKP21 Mask */
+#define GPIO_PORT_MASK4_MASKP22_Pos 22 /*!< GPIO_PORT MASK4: MASKP22 Position */
+#define GPIO_PORT_MASK4_MASKP22_Msk (0x01UL << GPIO_PORT_MASK4_MASKP22_Pos) /*!< GPIO_PORT MASK4: MASKP22 Mask */
+#define GPIO_PORT_MASK4_MASKP23_Pos 23 /*!< GPIO_PORT MASK4: MASKP23 Position */
+#define GPIO_PORT_MASK4_MASKP23_Msk (0x01UL << GPIO_PORT_MASK4_MASKP23_Pos) /*!< GPIO_PORT MASK4: MASKP23 Mask */
+#define GPIO_PORT_MASK4_MASKP24_Pos 24 /*!< GPIO_PORT MASK4: MASKP24 Position */
+#define GPIO_PORT_MASK4_MASKP24_Msk (0x01UL << GPIO_PORT_MASK4_MASKP24_Pos) /*!< GPIO_PORT MASK4: MASKP24 Mask */
+#define GPIO_PORT_MASK4_MASKP25_Pos 25 /*!< GPIO_PORT MASK4: MASKP25 Position */
+#define GPIO_PORT_MASK4_MASKP25_Msk (0x01UL << GPIO_PORT_MASK4_MASKP25_Pos) /*!< GPIO_PORT MASK4: MASKP25 Mask */
+#define GPIO_PORT_MASK4_MASKP26_Pos 26 /*!< GPIO_PORT MASK4: MASKP26 Position */
+#define GPIO_PORT_MASK4_MASKP26_Msk (0x01UL << GPIO_PORT_MASK4_MASKP26_Pos) /*!< GPIO_PORT MASK4: MASKP26 Mask */
+#define GPIO_PORT_MASK4_MASKP27_Pos 27 /*!< GPIO_PORT MASK4: MASKP27 Position */
+#define GPIO_PORT_MASK4_MASKP27_Msk (0x01UL << GPIO_PORT_MASK4_MASKP27_Pos) /*!< GPIO_PORT MASK4: MASKP27 Mask */
+#define GPIO_PORT_MASK4_MASKP28_Pos 28 /*!< GPIO_PORT MASK4: MASKP28 Position */
+#define GPIO_PORT_MASK4_MASKP28_Msk (0x01UL << GPIO_PORT_MASK4_MASKP28_Pos) /*!< GPIO_PORT MASK4: MASKP28 Mask */
+#define GPIO_PORT_MASK4_MASKP29_Pos 29 /*!< GPIO_PORT MASK4: MASKP29 Position */
+#define GPIO_PORT_MASK4_MASKP29_Msk (0x01UL << GPIO_PORT_MASK4_MASKP29_Pos) /*!< GPIO_PORT MASK4: MASKP29 Mask */
+#define GPIO_PORT_MASK4_MASKP30_Pos 30 /*!< GPIO_PORT MASK4: MASKP30 Position */
+#define GPIO_PORT_MASK4_MASKP30_Msk (0x01UL << GPIO_PORT_MASK4_MASKP30_Pos) /*!< GPIO_PORT MASK4: MASKP30 Mask */
+#define GPIO_PORT_MASK4_MASKP31_Pos 31 /*!< GPIO_PORT MASK4: MASKP31 Position */
+#define GPIO_PORT_MASK4_MASKP31_Msk (0x01UL << GPIO_PORT_MASK4_MASKP31_Pos) /*!< GPIO_PORT MASK4: MASKP31 Mask */
+
+// ------------------------------------- GPIO_PORT_MASK5 ----------------------------------------
+#define GPIO_PORT_MASK5_MASKP0_Pos 0 /*!< GPIO_PORT MASK5: MASKP0 Position */
+#define GPIO_PORT_MASK5_MASKP0_Msk (0x01UL << GPIO_PORT_MASK5_MASKP0_Pos) /*!< GPIO_PORT MASK5: MASKP0 Mask */
+#define GPIO_PORT_MASK5_MASKP1_Pos 1 /*!< GPIO_PORT MASK5: MASKP1 Position */
+#define GPIO_PORT_MASK5_MASKP1_Msk (0x01UL << GPIO_PORT_MASK5_MASKP1_Pos) /*!< GPIO_PORT MASK5: MASKP1 Mask */
+#define GPIO_PORT_MASK5_MASKP2_Pos 2 /*!< GPIO_PORT MASK5: MASKP2 Position */
+#define GPIO_PORT_MASK5_MASKP2_Msk (0x01UL << GPIO_PORT_MASK5_MASKP2_Pos) /*!< GPIO_PORT MASK5: MASKP2 Mask */
+#define GPIO_PORT_MASK5_MASKP3_Pos 3 /*!< GPIO_PORT MASK5: MASKP3 Position */
+#define GPIO_PORT_MASK5_MASKP3_Msk (0x01UL << GPIO_PORT_MASK5_MASKP3_Pos) /*!< GPIO_PORT MASK5: MASKP3 Mask */
+#define GPIO_PORT_MASK5_MASKP4_Pos 4 /*!< GPIO_PORT MASK5: MASKP4 Position */
+#define GPIO_PORT_MASK5_MASKP4_Msk (0x01UL << GPIO_PORT_MASK5_MASKP4_Pos) /*!< GPIO_PORT MASK5: MASKP4 Mask */
+#define GPIO_PORT_MASK5_MASKP5_Pos 5 /*!< GPIO_PORT MASK5: MASKP5 Position */
+#define GPIO_PORT_MASK5_MASKP5_Msk (0x01UL << GPIO_PORT_MASK5_MASKP5_Pos) /*!< GPIO_PORT MASK5: MASKP5 Mask */
+#define GPIO_PORT_MASK5_MASKP6_Pos 6 /*!< GPIO_PORT MASK5: MASKP6 Position */
+#define GPIO_PORT_MASK5_MASKP6_Msk (0x01UL << GPIO_PORT_MASK5_MASKP6_Pos) /*!< GPIO_PORT MASK5: MASKP6 Mask */
+#define GPIO_PORT_MASK5_MASKP7_Pos 7 /*!< GPIO_PORT MASK5: MASKP7 Position */
+#define GPIO_PORT_MASK5_MASKP7_Msk (0x01UL << GPIO_PORT_MASK5_MASKP7_Pos) /*!< GPIO_PORT MASK5: MASKP7 Mask */
+#define GPIO_PORT_MASK5_MASKP8_Pos 8 /*!< GPIO_PORT MASK5: MASKP8 Position */
+#define GPIO_PORT_MASK5_MASKP8_Msk (0x01UL << GPIO_PORT_MASK5_MASKP8_Pos) /*!< GPIO_PORT MASK5: MASKP8 Mask */
+#define GPIO_PORT_MASK5_MASKP9_Pos 9 /*!< GPIO_PORT MASK5: MASKP9 Position */
+#define GPIO_PORT_MASK5_MASKP9_Msk (0x01UL << GPIO_PORT_MASK5_MASKP9_Pos) /*!< GPIO_PORT MASK5: MASKP9 Mask */
+#define GPIO_PORT_MASK5_MASKP10_Pos 10 /*!< GPIO_PORT MASK5: MASKP10 Position */
+#define GPIO_PORT_MASK5_MASKP10_Msk (0x01UL << GPIO_PORT_MASK5_MASKP10_Pos) /*!< GPIO_PORT MASK5: MASKP10 Mask */
+#define GPIO_PORT_MASK5_MASKP11_Pos 11 /*!< GPIO_PORT MASK5: MASKP11 Position */
+#define GPIO_PORT_MASK5_MASKP11_Msk (0x01UL << GPIO_PORT_MASK5_MASKP11_Pos) /*!< GPIO_PORT MASK5: MASKP11 Mask */
+#define GPIO_PORT_MASK5_MASKP12_Pos 12 /*!< GPIO_PORT MASK5: MASKP12 Position */
+#define GPIO_PORT_MASK5_MASKP12_Msk (0x01UL << GPIO_PORT_MASK5_MASKP12_Pos) /*!< GPIO_PORT MASK5: MASKP12 Mask */
+#define GPIO_PORT_MASK5_MASKP13_Pos 13 /*!< GPIO_PORT MASK5: MASKP13 Position */
+#define GPIO_PORT_MASK5_MASKP13_Msk (0x01UL << GPIO_PORT_MASK5_MASKP13_Pos) /*!< GPIO_PORT MASK5: MASKP13 Mask */
+#define GPIO_PORT_MASK5_MASKP14_Pos 14 /*!< GPIO_PORT MASK5: MASKP14 Position */
+#define GPIO_PORT_MASK5_MASKP14_Msk (0x01UL << GPIO_PORT_MASK5_MASKP14_Pos) /*!< GPIO_PORT MASK5: MASKP14 Mask */
+#define GPIO_PORT_MASK5_MASKP15_Pos 15 /*!< GPIO_PORT MASK5: MASKP15 Position */
+#define GPIO_PORT_MASK5_MASKP15_Msk (0x01UL << GPIO_PORT_MASK5_MASKP15_Pos) /*!< GPIO_PORT MASK5: MASKP15 Mask */
+#define GPIO_PORT_MASK5_MASKP16_Pos 16 /*!< GPIO_PORT MASK5: MASKP16 Position */
+#define GPIO_PORT_MASK5_MASKP16_Msk (0x01UL << GPIO_PORT_MASK5_MASKP16_Pos) /*!< GPIO_PORT MASK5: MASKP16 Mask */
+#define GPIO_PORT_MASK5_MASKP17_Pos 17 /*!< GPIO_PORT MASK5: MASKP17 Position */
+#define GPIO_PORT_MASK5_MASKP17_Msk (0x01UL << GPIO_PORT_MASK5_MASKP17_Pos) /*!< GPIO_PORT MASK5: MASKP17 Mask */
+#define GPIO_PORT_MASK5_MASKP18_Pos 18 /*!< GPIO_PORT MASK5: MASKP18 Position */
+#define GPIO_PORT_MASK5_MASKP18_Msk (0x01UL << GPIO_PORT_MASK5_MASKP18_Pos) /*!< GPIO_PORT MASK5: MASKP18 Mask */
+#define GPIO_PORT_MASK5_MASKP19_Pos 19 /*!< GPIO_PORT MASK5: MASKP19 Position */
+#define GPIO_PORT_MASK5_MASKP19_Msk (0x01UL << GPIO_PORT_MASK5_MASKP19_Pos) /*!< GPIO_PORT MASK5: MASKP19 Mask */
+#define GPIO_PORT_MASK5_MASKP20_Pos 20 /*!< GPIO_PORT MASK5: MASKP20 Position */
+#define GPIO_PORT_MASK5_MASKP20_Msk (0x01UL << GPIO_PORT_MASK5_MASKP20_Pos) /*!< GPIO_PORT MASK5: MASKP20 Mask */
+#define GPIO_PORT_MASK5_MASKP21_Pos 21 /*!< GPIO_PORT MASK5: MASKP21 Position */
+#define GPIO_PORT_MASK5_MASKP21_Msk (0x01UL << GPIO_PORT_MASK5_MASKP21_Pos) /*!< GPIO_PORT MASK5: MASKP21 Mask */
+#define GPIO_PORT_MASK5_MASKP22_Pos 22 /*!< GPIO_PORT MASK5: MASKP22 Position */
+#define GPIO_PORT_MASK5_MASKP22_Msk (0x01UL << GPIO_PORT_MASK5_MASKP22_Pos) /*!< GPIO_PORT MASK5: MASKP22 Mask */
+#define GPIO_PORT_MASK5_MASKP23_Pos 23 /*!< GPIO_PORT MASK5: MASKP23 Position */
+#define GPIO_PORT_MASK5_MASKP23_Msk (0x01UL << GPIO_PORT_MASK5_MASKP23_Pos) /*!< GPIO_PORT MASK5: MASKP23 Mask */
+#define GPIO_PORT_MASK5_MASKP24_Pos 24 /*!< GPIO_PORT MASK5: MASKP24 Position */
+#define GPIO_PORT_MASK5_MASKP24_Msk (0x01UL << GPIO_PORT_MASK5_MASKP24_Pos) /*!< GPIO_PORT MASK5: MASKP24 Mask */
+#define GPIO_PORT_MASK5_MASKP25_Pos 25 /*!< GPIO_PORT MASK5: MASKP25 Position */
+#define GPIO_PORT_MASK5_MASKP25_Msk (0x01UL << GPIO_PORT_MASK5_MASKP25_Pos) /*!< GPIO_PORT MASK5: MASKP25 Mask */
+#define GPIO_PORT_MASK5_MASKP26_Pos 26 /*!< GPIO_PORT MASK5: MASKP26 Position */
+#define GPIO_PORT_MASK5_MASKP26_Msk (0x01UL << GPIO_PORT_MASK5_MASKP26_Pos) /*!< GPIO_PORT MASK5: MASKP26 Mask */
+#define GPIO_PORT_MASK5_MASKP27_Pos 27 /*!< GPIO_PORT MASK5: MASKP27 Position */
+#define GPIO_PORT_MASK5_MASKP27_Msk (0x01UL << GPIO_PORT_MASK5_MASKP27_Pos) /*!< GPIO_PORT MASK5: MASKP27 Mask */
+#define GPIO_PORT_MASK5_MASKP28_Pos 28 /*!< GPIO_PORT MASK5: MASKP28 Position */
+#define GPIO_PORT_MASK5_MASKP28_Msk (0x01UL << GPIO_PORT_MASK5_MASKP28_Pos) /*!< GPIO_PORT MASK5: MASKP28 Mask */
+#define GPIO_PORT_MASK5_MASKP29_Pos 29 /*!< GPIO_PORT MASK5: MASKP29 Position */
+#define GPIO_PORT_MASK5_MASKP29_Msk (0x01UL << GPIO_PORT_MASK5_MASKP29_Pos) /*!< GPIO_PORT MASK5: MASKP29 Mask */
+#define GPIO_PORT_MASK5_MASKP30_Pos 30 /*!< GPIO_PORT MASK5: MASKP30 Position */
+#define GPIO_PORT_MASK5_MASKP30_Msk (0x01UL << GPIO_PORT_MASK5_MASKP30_Pos) /*!< GPIO_PORT MASK5: MASKP30 Mask */
+#define GPIO_PORT_MASK5_MASKP31_Pos 31 /*!< GPIO_PORT MASK5: MASKP31 Position */
+#define GPIO_PORT_MASK5_MASKP31_Msk (0x01UL << GPIO_PORT_MASK5_MASKP31_Pos) /*!< GPIO_PORT MASK5: MASKP31 Mask */
+
+// ------------------------------------- GPIO_PORT_MASK6 ----------------------------------------
+#define GPIO_PORT_MASK6_MASKP0_Pos 0 /*!< GPIO_PORT MASK6: MASKP0 Position */
+#define GPIO_PORT_MASK6_MASKP0_Msk (0x01UL << GPIO_PORT_MASK6_MASKP0_Pos) /*!< GPIO_PORT MASK6: MASKP0 Mask */
+#define GPIO_PORT_MASK6_MASKP1_Pos 1 /*!< GPIO_PORT MASK6: MASKP1 Position */
+#define GPIO_PORT_MASK6_MASKP1_Msk (0x01UL << GPIO_PORT_MASK6_MASKP1_Pos) /*!< GPIO_PORT MASK6: MASKP1 Mask */
+#define GPIO_PORT_MASK6_MASKP2_Pos 2 /*!< GPIO_PORT MASK6: MASKP2 Position */
+#define GPIO_PORT_MASK6_MASKP2_Msk (0x01UL << GPIO_PORT_MASK6_MASKP2_Pos) /*!< GPIO_PORT MASK6: MASKP2 Mask */
+#define GPIO_PORT_MASK6_MASKP3_Pos 3 /*!< GPIO_PORT MASK6: MASKP3 Position */
+#define GPIO_PORT_MASK6_MASKP3_Msk (0x01UL << GPIO_PORT_MASK6_MASKP3_Pos) /*!< GPIO_PORT MASK6: MASKP3 Mask */
+#define GPIO_PORT_MASK6_MASKP4_Pos 4 /*!< GPIO_PORT MASK6: MASKP4 Position */
+#define GPIO_PORT_MASK6_MASKP4_Msk (0x01UL << GPIO_PORT_MASK6_MASKP4_Pos) /*!< GPIO_PORT MASK6: MASKP4 Mask */
+#define GPIO_PORT_MASK6_MASKP5_Pos 5 /*!< GPIO_PORT MASK6: MASKP5 Position */
+#define GPIO_PORT_MASK6_MASKP5_Msk (0x01UL << GPIO_PORT_MASK6_MASKP5_Pos) /*!< GPIO_PORT MASK6: MASKP5 Mask */
+#define GPIO_PORT_MASK6_MASKP6_Pos 6 /*!< GPIO_PORT MASK6: MASKP6 Position */
+#define GPIO_PORT_MASK6_MASKP6_Msk (0x01UL << GPIO_PORT_MASK6_MASKP6_Pos) /*!< GPIO_PORT MASK6: MASKP6 Mask */
+#define GPIO_PORT_MASK6_MASKP7_Pos 7 /*!< GPIO_PORT MASK6: MASKP7 Position */
+#define GPIO_PORT_MASK6_MASKP7_Msk (0x01UL << GPIO_PORT_MASK6_MASKP7_Pos) /*!< GPIO_PORT MASK6: MASKP7 Mask */
+#define GPIO_PORT_MASK6_MASKP8_Pos 8 /*!< GPIO_PORT MASK6: MASKP8 Position */
+#define GPIO_PORT_MASK6_MASKP8_Msk (0x01UL << GPIO_PORT_MASK6_MASKP8_Pos) /*!< GPIO_PORT MASK6: MASKP8 Mask */
+#define GPIO_PORT_MASK6_MASKP9_Pos 9 /*!< GPIO_PORT MASK6: MASKP9 Position */
+#define GPIO_PORT_MASK6_MASKP9_Msk (0x01UL << GPIO_PORT_MASK6_MASKP9_Pos) /*!< GPIO_PORT MASK6: MASKP9 Mask */
+#define GPIO_PORT_MASK6_MASKP10_Pos 10 /*!< GPIO_PORT MASK6: MASKP10 Position */
+#define GPIO_PORT_MASK6_MASKP10_Msk (0x01UL << GPIO_PORT_MASK6_MASKP10_Pos) /*!< GPIO_PORT MASK6: MASKP10 Mask */
+#define GPIO_PORT_MASK6_MASKP11_Pos 11 /*!< GPIO_PORT MASK6: MASKP11 Position */
+#define GPIO_PORT_MASK6_MASKP11_Msk (0x01UL << GPIO_PORT_MASK6_MASKP11_Pos) /*!< GPIO_PORT MASK6: MASKP11 Mask */
+#define GPIO_PORT_MASK6_MASKP12_Pos 12 /*!< GPIO_PORT MASK6: MASKP12 Position */
+#define GPIO_PORT_MASK6_MASKP12_Msk (0x01UL << GPIO_PORT_MASK6_MASKP12_Pos) /*!< GPIO_PORT MASK6: MASKP12 Mask */
+#define GPIO_PORT_MASK6_MASKP13_Pos 13 /*!< GPIO_PORT MASK6: MASKP13 Position */
+#define GPIO_PORT_MASK6_MASKP13_Msk (0x01UL << GPIO_PORT_MASK6_MASKP13_Pos) /*!< GPIO_PORT MASK6: MASKP13 Mask */
+#define GPIO_PORT_MASK6_MASKP14_Pos 14 /*!< GPIO_PORT MASK6: MASKP14 Position */
+#define GPIO_PORT_MASK6_MASKP14_Msk (0x01UL << GPIO_PORT_MASK6_MASKP14_Pos) /*!< GPIO_PORT MASK6: MASKP14 Mask */
+#define GPIO_PORT_MASK6_MASKP15_Pos 15 /*!< GPIO_PORT MASK6: MASKP15 Position */
+#define GPIO_PORT_MASK6_MASKP15_Msk (0x01UL << GPIO_PORT_MASK6_MASKP15_Pos) /*!< GPIO_PORT MASK6: MASKP15 Mask */
+#define GPIO_PORT_MASK6_MASKP16_Pos 16 /*!< GPIO_PORT MASK6: MASKP16 Position */
+#define GPIO_PORT_MASK6_MASKP16_Msk (0x01UL << GPIO_PORT_MASK6_MASKP16_Pos) /*!< GPIO_PORT MASK6: MASKP16 Mask */
+#define GPIO_PORT_MASK6_MASKP17_Pos 17 /*!< GPIO_PORT MASK6: MASKP17 Position */
+#define GPIO_PORT_MASK6_MASKP17_Msk (0x01UL << GPIO_PORT_MASK6_MASKP17_Pos) /*!< GPIO_PORT MASK6: MASKP17 Mask */
+#define GPIO_PORT_MASK6_MASKP18_Pos 18 /*!< GPIO_PORT MASK6: MASKP18 Position */
+#define GPIO_PORT_MASK6_MASKP18_Msk (0x01UL << GPIO_PORT_MASK6_MASKP18_Pos) /*!< GPIO_PORT MASK6: MASKP18 Mask */
+#define GPIO_PORT_MASK6_MASKP19_Pos 19 /*!< GPIO_PORT MASK6: MASKP19 Position */
+#define GPIO_PORT_MASK6_MASKP19_Msk (0x01UL << GPIO_PORT_MASK6_MASKP19_Pos) /*!< GPIO_PORT MASK6: MASKP19 Mask */
+#define GPIO_PORT_MASK6_MASKP20_Pos 20 /*!< GPIO_PORT MASK6: MASKP20 Position */
+#define GPIO_PORT_MASK6_MASKP20_Msk (0x01UL << GPIO_PORT_MASK6_MASKP20_Pos) /*!< GPIO_PORT MASK6: MASKP20 Mask */
+#define GPIO_PORT_MASK6_MASKP21_Pos 21 /*!< GPIO_PORT MASK6: MASKP21 Position */
+#define GPIO_PORT_MASK6_MASKP21_Msk (0x01UL << GPIO_PORT_MASK6_MASKP21_Pos) /*!< GPIO_PORT MASK6: MASKP21 Mask */
+#define GPIO_PORT_MASK6_MASKP22_Pos 22 /*!< GPIO_PORT MASK6: MASKP22 Position */
+#define GPIO_PORT_MASK6_MASKP22_Msk (0x01UL << GPIO_PORT_MASK6_MASKP22_Pos) /*!< GPIO_PORT MASK6: MASKP22 Mask */
+#define GPIO_PORT_MASK6_MASKP23_Pos 23 /*!< GPIO_PORT MASK6: MASKP23 Position */
+#define GPIO_PORT_MASK6_MASKP23_Msk (0x01UL << GPIO_PORT_MASK6_MASKP23_Pos) /*!< GPIO_PORT MASK6: MASKP23 Mask */
+#define GPIO_PORT_MASK6_MASKP24_Pos 24 /*!< GPIO_PORT MASK6: MASKP24 Position */
+#define GPIO_PORT_MASK6_MASKP24_Msk (0x01UL << GPIO_PORT_MASK6_MASKP24_Pos) /*!< GPIO_PORT MASK6: MASKP24 Mask */
+#define GPIO_PORT_MASK6_MASKP25_Pos 25 /*!< GPIO_PORT MASK6: MASKP25 Position */
+#define GPIO_PORT_MASK6_MASKP25_Msk (0x01UL << GPIO_PORT_MASK6_MASKP25_Pos) /*!< GPIO_PORT MASK6: MASKP25 Mask */
+#define GPIO_PORT_MASK6_MASKP26_Pos 26 /*!< GPIO_PORT MASK6: MASKP26 Position */
+#define GPIO_PORT_MASK6_MASKP26_Msk (0x01UL << GPIO_PORT_MASK6_MASKP26_Pos) /*!< GPIO_PORT MASK6: MASKP26 Mask */
+#define GPIO_PORT_MASK6_MASKP27_Pos 27 /*!< GPIO_PORT MASK6: MASKP27 Position */
+#define GPIO_PORT_MASK6_MASKP27_Msk (0x01UL << GPIO_PORT_MASK6_MASKP27_Pos) /*!< GPIO_PORT MASK6: MASKP27 Mask */
+#define GPIO_PORT_MASK6_MASKP28_Pos 28 /*!< GPIO_PORT MASK6: MASKP28 Position */
+#define GPIO_PORT_MASK6_MASKP28_Msk (0x01UL << GPIO_PORT_MASK6_MASKP28_Pos) /*!< GPIO_PORT MASK6: MASKP28 Mask */
+#define GPIO_PORT_MASK6_MASKP29_Pos 29 /*!< GPIO_PORT MASK6: MASKP29 Position */
+#define GPIO_PORT_MASK6_MASKP29_Msk (0x01UL << GPIO_PORT_MASK6_MASKP29_Pos) /*!< GPIO_PORT MASK6: MASKP29 Mask */
+#define GPIO_PORT_MASK6_MASKP30_Pos 30 /*!< GPIO_PORT MASK6: MASKP30 Position */
+#define GPIO_PORT_MASK6_MASKP30_Msk (0x01UL << GPIO_PORT_MASK6_MASKP30_Pos) /*!< GPIO_PORT MASK6: MASKP30 Mask */
+#define GPIO_PORT_MASK6_MASKP31_Pos 31 /*!< GPIO_PORT MASK6: MASKP31 Position */
+#define GPIO_PORT_MASK6_MASKP31_Msk (0x01UL << GPIO_PORT_MASK6_MASKP31_Pos) /*!< GPIO_PORT MASK6: MASKP31 Mask */
+
+// ------------------------------------- GPIO_PORT_MASK7 ----------------------------------------
+#define GPIO_PORT_MASK7_MASKP0_Pos 0 /*!< GPIO_PORT MASK7: MASKP0 Position */
+#define GPIO_PORT_MASK7_MASKP0_Msk (0x01UL << GPIO_PORT_MASK7_MASKP0_Pos) /*!< GPIO_PORT MASK7: MASKP0 Mask */
+#define GPIO_PORT_MASK7_MASKP1_Pos 1 /*!< GPIO_PORT MASK7: MASKP1 Position */
+#define GPIO_PORT_MASK7_MASKP1_Msk (0x01UL << GPIO_PORT_MASK7_MASKP1_Pos) /*!< GPIO_PORT MASK7: MASKP1 Mask */
+#define GPIO_PORT_MASK7_MASKP2_Pos 2 /*!< GPIO_PORT MASK7: MASKP2 Position */
+#define GPIO_PORT_MASK7_MASKP2_Msk (0x01UL << GPIO_PORT_MASK7_MASKP2_Pos) /*!< GPIO_PORT MASK7: MASKP2 Mask */
+#define GPIO_PORT_MASK7_MASKP3_Pos 3 /*!< GPIO_PORT MASK7: MASKP3 Position */
+#define GPIO_PORT_MASK7_MASKP3_Msk (0x01UL << GPIO_PORT_MASK7_MASKP3_Pos) /*!< GPIO_PORT MASK7: MASKP3 Mask */
+#define GPIO_PORT_MASK7_MASKP4_Pos 4 /*!< GPIO_PORT MASK7: MASKP4 Position */
+#define GPIO_PORT_MASK7_MASKP4_Msk (0x01UL << GPIO_PORT_MASK7_MASKP4_Pos) /*!< GPIO_PORT MASK7: MASKP4 Mask */
+#define GPIO_PORT_MASK7_MASKP5_Pos 5 /*!< GPIO_PORT MASK7: MASKP5 Position */
+#define GPIO_PORT_MASK7_MASKP5_Msk (0x01UL << GPIO_PORT_MASK7_MASKP5_Pos) /*!< GPIO_PORT MASK7: MASKP5 Mask */
+#define GPIO_PORT_MASK7_MASKP6_Pos 6 /*!< GPIO_PORT MASK7: MASKP6 Position */
+#define GPIO_PORT_MASK7_MASKP6_Msk (0x01UL << GPIO_PORT_MASK7_MASKP6_Pos) /*!< GPIO_PORT MASK7: MASKP6 Mask */
+#define GPIO_PORT_MASK7_MASKP7_Pos 7 /*!< GPIO_PORT MASK7: MASKP7 Position */
+#define GPIO_PORT_MASK7_MASKP7_Msk (0x01UL << GPIO_PORT_MASK7_MASKP7_Pos) /*!< GPIO_PORT MASK7: MASKP7 Mask */
+#define GPIO_PORT_MASK7_MASKP8_Pos 8 /*!< GPIO_PORT MASK7: MASKP8 Position */
+#define GPIO_PORT_MASK7_MASKP8_Msk (0x01UL << GPIO_PORT_MASK7_MASKP8_Pos) /*!< GPIO_PORT MASK7: MASKP8 Mask */
+#define GPIO_PORT_MASK7_MASKP9_Pos 9 /*!< GPIO_PORT MASK7: MASKP9 Position */
+#define GPIO_PORT_MASK7_MASKP9_Msk (0x01UL << GPIO_PORT_MASK7_MASKP9_Pos) /*!< GPIO_PORT MASK7: MASKP9 Mask */
+#define GPIO_PORT_MASK7_MASKP10_Pos 10 /*!< GPIO_PORT MASK7: MASKP10 Position */
+#define GPIO_PORT_MASK7_MASKP10_Msk (0x01UL << GPIO_PORT_MASK7_MASKP10_Pos) /*!< GPIO_PORT MASK7: MASKP10 Mask */
+#define GPIO_PORT_MASK7_MASKP11_Pos 11 /*!< GPIO_PORT MASK7: MASKP11 Position */
+#define GPIO_PORT_MASK7_MASKP11_Msk (0x01UL << GPIO_PORT_MASK7_MASKP11_Pos) /*!< GPIO_PORT MASK7: MASKP11 Mask */
+#define GPIO_PORT_MASK7_MASKP12_Pos 12 /*!< GPIO_PORT MASK7: MASKP12 Position */
+#define GPIO_PORT_MASK7_MASKP12_Msk (0x01UL << GPIO_PORT_MASK7_MASKP12_Pos) /*!< GPIO_PORT MASK7: MASKP12 Mask */
+#define GPIO_PORT_MASK7_MASKP13_Pos 13 /*!< GPIO_PORT MASK7: MASKP13 Position */
+#define GPIO_PORT_MASK7_MASKP13_Msk (0x01UL << GPIO_PORT_MASK7_MASKP13_Pos) /*!< GPIO_PORT MASK7: MASKP13 Mask */
+#define GPIO_PORT_MASK7_MASKP14_Pos 14 /*!< GPIO_PORT MASK7: MASKP14 Position */
+#define GPIO_PORT_MASK7_MASKP14_Msk (0x01UL << GPIO_PORT_MASK7_MASKP14_Pos) /*!< GPIO_PORT MASK7: MASKP14 Mask */
+#define GPIO_PORT_MASK7_MASKP15_Pos 15 /*!< GPIO_PORT MASK7: MASKP15 Position */
+#define GPIO_PORT_MASK7_MASKP15_Msk (0x01UL << GPIO_PORT_MASK7_MASKP15_Pos) /*!< GPIO_PORT MASK7: MASKP15 Mask */
+#define GPIO_PORT_MASK7_MASKP16_Pos 16 /*!< GPIO_PORT MASK7: MASKP16 Position */
+#define GPIO_PORT_MASK7_MASKP16_Msk (0x01UL << GPIO_PORT_MASK7_MASKP16_Pos) /*!< GPIO_PORT MASK7: MASKP16 Mask */
+#define GPIO_PORT_MASK7_MASKP17_Pos 17 /*!< GPIO_PORT MASK7: MASKP17 Position */
+#define GPIO_PORT_MASK7_MASKP17_Msk (0x01UL << GPIO_PORT_MASK7_MASKP17_Pos) /*!< GPIO_PORT MASK7: MASKP17 Mask */
+#define GPIO_PORT_MASK7_MASKP18_Pos 18 /*!< GPIO_PORT MASK7: MASKP18 Position */
+#define GPIO_PORT_MASK7_MASKP18_Msk (0x01UL << GPIO_PORT_MASK7_MASKP18_Pos) /*!< GPIO_PORT MASK7: MASKP18 Mask */
+#define GPIO_PORT_MASK7_MASKP19_Pos 19 /*!< GPIO_PORT MASK7: MASKP19 Position */
+#define GPIO_PORT_MASK7_MASKP19_Msk (0x01UL << GPIO_PORT_MASK7_MASKP19_Pos) /*!< GPIO_PORT MASK7: MASKP19 Mask */
+#define GPIO_PORT_MASK7_MASKP20_Pos 20 /*!< GPIO_PORT MASK7: MASKP20 Position */
+#define GPIO_PORT_MASK7_MASKP20_Msk (0x01UL << GPIO_PORT_MASK7_MASKP20_Pos) /*!< GPIO_PORT MASK7: MASKP20 Mask */
+#define GPIO_PORT_MASK7_MASKP21_Pos 21 /*!< GPIO_PORT MASK7: MASKP21 Position */
+#define GPIO_PORT_MASK7_MASKP21_Msk (0x01UL << GPIO_PORT_MASK7_MASKP21_Pos) /*!< GPIO_PORT MASK7: MASKP21 Mask */
+#define GPIO_PORT_MASK7_MASKP22_Pos 22 /*!< GPIO_PORT MASK7: MASKP22 Position */
+#define GPIO_PORT_MASK7_MASKP22_Msk (0x01UL << GPIO_PORT_MASK7_MASKP22_Pos) /*!< GPIO_PORT MASK7: MASKP22 Mask */
+#define GPIO_PORT_MASK7_MASKP23_Pos 23 /*!< GPIO_PORT MASK7: MASKP23 Position */
+#define GPIO_PORT_MASK7_MASKP23_Msk (0x01UL << GPIO_PORT_MASK7_MASKP23_Pos) /*!< GPIO_PORT MASK7: MASKP23 Mask */
+#define GPIO_PORT_MASK7_MASKP24_Pos 24 /*!< GPIO_PORT MASK7: MASKP24 Position */
+#define GPIO_PORT_MASK7_MASKP24_Msk (0x01UL << GPIO_PORT_MASK7_MASKP24_Pos) /*!< GPIO_PORT MASK7: MASKP24 Mask */
+#define GPIO_PORT_MASK7_MASKP25_Pos 25 /*!< GPIO_PORT MASK7: MASKP25 Position */
+#define GPIO_PORT_MASK7_MASKP25_Msk (0x01UL << GPIO_PORT_MASK7_MASKP25_Pos) /*!< GPIO_PORT MASK7: MASKP25 Mask */
+#define GPIO_PORT_MASK7_MASKP26_Pos 26 /*!< GPIO_PORT MASK7: MASKP26 Position */
+#define GPIO_PORT_MASK7_MASKP26_Msk (0x01UL << GPIO_PORT_MASK7_MASKP26_Pos) /*!< GPIO_PORT MASK7: MASKP26 Mask */
+#define GPIO_PORT_MASK7_MASKP27_Pos 27 /*!< GPIO_PORT MASK7: MASKP27 Position */
+#define GPIO_PORT_MASK7_MASKP27_Msk (0x01UL << GPIO_PORT_MASK7_MASKP27_Pos) /*!< GPIO_PORT MASK7: MASKP27 Mask */
+#define GPIO_PORT_MASK7_MASKP28_Pos 28 /*!< GPIO_PORT MASK7: MASKP28 Position */
+#define GPIO_PORT_MASK7_MASKP28_Msk (0x01UL << GPIO_PORT_MASK7_MASKP28_Pos) /*!< GPIO_PORT MASK7: MASKP28 Mask */
+#define GPIO_PORT_MASK7_MASKP29_Pos 29 /*!< GPIO_PORT MASK7: MASKP29 Position */
+#define GPIO_PORT_MASK7_MASKP29_Msk (0x01UL << GPIO_PORT_MASK7_MASKP29_Pos) /*!< GPIO_PORT MASK7: MASKP29 Mask */
+#define GPIO_PORT_MASK7_MASKP30_Pos 30 /*!< GPIO_PORT MASK7: MASKP30 Position */
+#define GPIO_PORT_MASK7_MASKP30_Msk (0x01UL << GPIO_PORT_MASK7_MASKP30_Pos) /*!< GPIO_PORT MASK7: MASKP30 Mask */
+#define GPIO_PORT_MASK7_MASKP31_Pos 31 /*!< GPIO_PORT MASK7: MASKP31 Position */
+#define GPIO_PORT_MASK7_MASKP31_Msk (0x01UL << GPIO_PORT_MASK7_MASKP31_Pos) /*!< GPIO_PORT MASK7: MASKP31 Mask */
+
+// ------------------------------------- GPIO_PORT_PIN0 -----------------------------------------
+#define GPIO_PORT_PIN0_PORT0_Pos 0 /*!< GPIO_PORT PIN0: PORT0 Position */
+#define GPIO_PORT_PIN0_PORT0_Msk (0x01UL << GPIO_PORT_PIN0_PORT0_Pos) /*!< GPIO_PORT PIN0: PORT0 Mask */
+#define GPIO_PORT_PIN0_PORT1_Pos 1 /*!< GPIO_PORT PIN0: PORT1 Position */
+#define GPIO_PORT_PIN0_PORT1_Msk (0x01UL << GPIO_PORT_PIN0_PORT1_Pos) /*!< GPIO_PORT PIN0: PORT1 Mask */
+#define GPIO_PORT_PIN0_PORT2_Pos 2 /*!< GPIO_PORT PIN0: PORT2 Position */
+#define GPIO_PORT_PIN0_PORT2_Msk (0x01UL << GPIO_PORT_PIN0_PORT2_Pos) /*!< GPIO_PORT PIN0: PORT2 Mask */
+#define GPIO_PORT_PIN0_PORT3_Pos 3 /*!< GPIO_PORT PIN0: PORT3 Position */
+#define GPIO_PORT_PIN0_PORT3_Msk (0x01UL << GPIO_PORT_PIN0_PORT3_Pos) /*!< GPIO_PORT PIN0: PORT3 Mask */
+#define GPIO_PORT_PIN0_PORT4_Pos 4 /*!< GPIO_PORT PIN0: PORT4 Position */
+#define GPIO_PORT_PIN0_PORT4_Msk (0x01UL << GPIO_PORT_PIN0_PORT4_Pos) /*!< GPIO_PORT PIN0: PORT4 Mask */
+#define GPIO_PORT_PIN0_PORT5_Pos 5 /*!< GPIO_PORT PIN0: PORT5 Position */
+#define GPIO_PORT_PIN0_PORT5_Msk (0x01UL << GPIO_PORT_PIN0_PORT5_Pos) /*!< GPIO_PORT PIN0: PORT5 Mask */
+#define GPIO_PORT_PIN0_PORT6_Pos 6 /*!< GPIO_PORT PIN0: PORT6 Position */
+#define GPIO_PORT_PIN0_PORT6_Msk (0x01UL << GPIO_PORT_PIN0_PORT6_Pos) /*!< GPIO_PORT PIN0: PORT6 Mask */
+#define GPIO_PORT_PIN0_PORT7_Pos 7 /*!< GPIO_PORT PIN0: PORT7 Position */
+#define GPIO_PORT_PIN0_PORT7_Msk (0x01UL << GPIO_PORT_PIN0_PORT7_Pos) /*!< GPIO_PORT PIN0: PORT7 Mask */
+#define GPIO_PORT_PIN0_PORT8_Pos 8 /*!< GPIO_PORT PIN0: PORT8 Position */
+#define GPIO_PORT_PIN0_PORT8_Msk (0x01UL << GPIO_PORT_PIN0_PORT8_Pos) /*!< GPIO_PORT PIN0: PORT8 Mask */
+#define GPIO_PORT_PIN0_PORT9_Pos 9 /*!< GPIO_PORT PIN0: PORT9 Position */
+#define GPIO_PORT_PIN0_PORT9_Msk (0x01UL << GPIO_PORT_PIN0_PORT9_Pos) /*!< GPIO_PORT PIN0: PORT9 Mask */
+#define GPIO_PORT_PIN0_PORT10_Pos 10 /*!< GPIO_PORT PIN0: PORT10 Position */
+#define GPIO_PORT_PIN0_PORT10_Msk (0x01UL << GPIO_PORT_PIN0_PORT10_Pos) /*!< GPIO_PORT PIN0: PORT10 Mask */
+#define GPIO_PORT_PIN0_PORT11_Pos 11 /*!< GPIO_PORT PIN0: PORT11 Position */
+#define GPIO_PORT_PIN0_PORT11_Msk (0x01UL << GPIO_PORT_PIN0_PORT11_Pos) /*!< GPIO_PORT PIN0: PORT11 Mask */
+#define GPIO_PORT_PIN0_PORT12_Pos 12 /*!< GPIO_PORT PIN0: PORT12 Position */
+#define GPIO_PORT_PIN0_PORT12_Msk (0x01UL << GPIO_PORT_PIN0_PORT12_Pos) /*!< GPIO_PORT PIN0: PORT12 Mask */
+#define GPIO_PORT_PIN0_PORT13_Pos 13 /*!< GPIO_PORT PIN0: PORT13 Position */
+#define GPIO_PORT_PIN0_PORT13_Msk (0x01UL << GPIO_PORT_PIN0_PORT13_Pos) /*!< GPIO_PORT PIN0: PORT13 Mask */
+#define GPIO_PORT_PIN0_PORT14_Pos 14 /*!< GPIO_PORT PIN0: PORT14 Position */
+#define GPIO_PORT_PIN0_PORT14_Msk (0x01UL << GPIO_PORT_PIN0_PORT14_Pos) /*!< GPIO_PORT PIN0: PORT14 Mask */
+#define GPIO_PORT_PIN0_PORT15_Pos 15 /*!< GPIO_PORT PIN0: PORT15 Position */
+#define GPIO_PORT_PIN0_PORT15_Msk (0x01UL << GPIO_PORT_PIN0_PORT15_Pos) /*!< GPIO_PORT PIN0: PORT15 Mask */
+#define GPIO_PORT_PIN0_PORT16_Pos 16 /*!< GPIO_PORT PIN0: PORT16 Position */
+#define GPIO_PORT_PIN0_PORT16_Msk (0x01UL << GPIO_PORT_PIN0_PORT16_Pos) /*!< GPIO_PORT PIN0: PORT16 Mask */
+#define GPIO_PORT_PIN0_PORT17_Pos 17 /*!< GPIO_PORT PIN0: PORT17 Position */
+#define GPIO_PORT_PIN0_PORT17_Msk (0x01UL << GPIO_PORT_PIN0_PORT17_Pos) /*!< GPIO_PORT PIN0: PORT17 Mask */
+#define GPIO_PORT_PIN0_PORT18_Pos 18 /*!< GPIO_PORT PIN0: PORT18 Position */
+#define GPIO_PORT_PIN0_PORT18_Msk (0x01UL << GPIO_PORT_PIN0_PORT18_Pos) /*!< GPIO_PORT PIN0: PORT18 Mask */
+#define GPIO_PORT_PIN0_PORT19_Pos 19 /*!< GPIO_PORT PIN0: PORT19 Position */
+#define GPIO_PORT_PIN0_PORT19_Msk (0x01UL << GPIO_PORT_PIN0_PORT19_Pos) /*!< GPIO_PORT PIN0: PORT19 Mask */
+#define GPIO_PORT_PIN0_PORT20_Pos 20 /*!< GPIO_PORT PIN0: PORT20 Position */
+#define GPIO_PORT_PIN0_PORT20_Msk (0x01UL << GPIO_PORT_PIN0_PORT20_Pos) /*!< GPIO_PORT PIN0: PORT20 Mask */
+#define GPIO_PORT_PIN0_PORT21_Pos 21 /*!< GPIO_PORT PIN0: PORT21 Position */
+#define GPIO_PORT_PIN0_PORT21_Msk (0x01UL << GPIO_PORT_PIN0_PORT21_Pos) /*!< GPIO_PORT PIN0: PORT21 Mask */
+#define GPIO_PORT_PIN0_PORT22_Pos 22 /*!< GPIO_PORT PIN0: PORT22 Position */
+#define GPIO_PORT_PIN0_PORT22_Msk (0x01UL << GPIO_PORT_PIN0_PORT22_Pos) /*!< GPIO_PORT PIN0: PORT22 Mask */
+#define GPIO_PORT_PIN0_PORT23_Pos 23 /*!< GPIO_PORT PIN0: PORT23 Position */
+#define GPIO_PORT_PIN0_PORT23_Msk (0x01UL << GPIO_PORT_PIN0_PORT23_Pos) /*!< GPIO_PORT PIN0: PORT23 Mask */
+#define GPIO_PORT_PIN0_PORT24_Pos 24 /*!< GPIO_PORT PIN0: PORT24 Position */
+#define GPIO_PORT_PIN0_PORT24_Msk (0x01UL << GPIO_PORT_PIN0_PORT24_Pos) /*!< GPIO_PORT PIN0: PORT24 Mask */
+#define GPIO_PORT_PIN0_PORT25_Pos 25 /*!< GPIO_PORT PIN0: PORT25 Position */
+#define GPIO_PORT_PIN0_PORT25_Msk (0x01UL << GPIO_PORT_PIN0_PORT25_Pos) /*!< GPIO_PORT PIN0: PORT25 Mask */
+#define GPIO_PORT_PIN0_PORT26_Pos 26 /*!< GPIO_PORT PIN0: PORT26 Position */
+#define GPIO_PORT_PIN0_PORT26_Msk (0x01UL << GPIO_PORT_PIN0_PORT26_Pos) /*!< GPIO_PORT PIN0: PORT26 Mask */
+#define GPIO_PORT_PIN0_PORT27_Pos 27 /*!< GPIO_PORT PIN0: PORT27 Position */
+#define GPIO_PORT_PIN0_PORT27_Msk (0x01UL << GPIO_PORT_PIN0_PORT27_Pos) /*!< GPIO_PORT PIN0: PORT27 Mask */
+#define GPIO_PORT_PIN0_PORT28_Pos 28 /*!< GPIO_PORT PIN0: PORT28 Position */
+#define GPIO_PORT_PIN0_PORT28_Msk (0x01UL << GPIO_PORT_PIN0_PORT28_Pos) /*!< GPIO_PORT PIN0: PORT28 Mask */
+#define GPIO_PORT_PIN0_PORT29_Pos 29 /*!< GPIO_PORT PIN0: PORT29 Position */
+#define GPIO_PORT_PIN0_PORT29_Msk (0x01UL << GPIO_PORT_PIN0_PORT29_Pos) /*!< GPIO_PORT PIN0: PORT29 Mask */
+#define GPIO_PORT_PIN0_PORT30_Pos 30 /*!< GPIO_PORT PIN0: PORT30 Position */
+#define GPIO_PORT_PIN0_PORT30_Msk (0x01UL << GPIO_PORT_PIN0_PORT30_Pos) /*!< GPIO_PORT PIN0: PORT30 Mask */
+#define GPIO_PORT_PIN0_PORT31_Pos 31 /*!< GPIO_PORT PIN0: PORT31 Position */
+#define GPIO_PORT_PIN0_PORT31_Msk (0x01UL << GPIO_PORT_PIN0_PORT31_Pos) /*!< GPIO_PORT PIN0: PORT31 Mask */
+
+// ------------------------------------- GPIO_PORT_PIN1 -----------------------------------------
+#define GPIO_PORT_PIN1_PORT0_Pos 0 /*!< GPIO_PORT PIN1: PORT0 Position */
+#define GPIO_PORT_PIN1_PORT0_Msk (0x01UL << GPIO_PORT_PIN1_PORT0_Pos) /*!< GPIO_PORT PIN1: PORT0 Mask */
+#define GPIO_PORT_PIN1_PORT1_Pos 1 /*!< GPIO_PORT PIN1: PORT1 Position */
+#define GPIO_PORT_PIN1_PORT1_Msk (0x01UL << GPIO_PORT_PIN1_PORT1_Pos) /*!< GPIO_PORT PIN1: PORT1 Mask */
+#define GPIO_PORT_PIN1_PORT2_Pos 2 /*!< GPIO_PORT PIN1: PORT2 Position */
+#define GPIO_PORT_PIN1_PORT2_Msk (0x01UL << GPIO_PORT_PIN1_PORT2_Pos) /*!< GPIO_PORT PIN1: PORT2 Mask */
+#define GPIO_PORT_PIN1_PORT3_Pos 3 /*!< GPIO_PORT PIN1: PORT3 Position */
+#define GPIO_PORT_PIN1_PORT3_Msk (0x01UL << GPIO_PORT_PIN1_PORT3_Pos) /*!< GPIO_PORT PIN1: PORT3 Mask */
+#define GPIO_PORT_PIN1_PORT4_Pos 4 /*!< GPIO_PORT PIN1: PORT4 Position */
+#define GPIO_PORT_PIN1_PORT4_Msk (0x01UL << GPIO_PORT_PIN1_PORT4_Pos) /*!< GPIO_PORT PIN1: PORT4 Mask */
+#define GPIO_PORT_PIN1_PORT5_Pos 5 /*!< GPIO_PORT PIN1: PORT5 Position */
+#define GPIO_PORT_PIN1_PORT5_Msk (0x01UL << GPIO_PORT_PIN1_PORT5_Pos) /*!< GPIO_PORT PIN1: PORT5 Mask */
+#define GPIO_PORT_PIN1_PORT6_Pos 6 /*!< GPIO_PORT PIN1: PORT6 Position */
+#define GPIO_PORT_PIN1_PORT6_Msk (0x01UL << GPIO_PORT_PIN1_PORT6_Pos) /*!< GPIO_PORT PIN1: PORT6 Mask */
+#define GPIO_PORT_PIN1_PORT7_Pos 7 /*!< GPIO_PORT PIN1: PORT7 Position */
+#define GPIO_PORT_PIN1_PORT7_Msk (0x01UL << GPIO_PORT_PIN1_PORT7_Pos) /*!< GPIO_PORT PIN1: PORT7 Mask */
+#define GPIO_PORT_PIN1_PORT8_Pos 8 /*!< GPIO_PORT PIN1: PORT8 Position */
+#define GPIO_PORT_PIN1_PORT8_Msk (0x01UL << GPIO_PORT_PIN1_PORT8_Pos) /*!< GPIO_PORT PIN1: PORT8 Mask */
+#define GPIO_PORT_PIN1_PORT9_Pos 9 /*!< GPIO_PORT PIN1: PORT9 Position */
+#define GPIO_PORT_PIN1_PORT9_Msk (0x01UL << GPIO_PORT_PIN1_PORT9_Pos) /*!< GPIO_PORT PIN1: PORT9 Mask */
+#define GPIO_PORT_PIN1_PORT10_Pos 10 /*!< GPIO_PORT PIN1: PORT10 Position */
+#define GPIO_PORT_PIN1_PORT10_Msk (0x01UL << GPIO_PORT_PIN1_PORT10_Pos) /*!< GPIO_PORT PIN1: PORT10 Mask */
+#define GPIO_PORT_PIN1_PORT11_Pos 11 /*!< GPIO_PORT PIN1: PORT11 Position */
+#define GPIO_PORT_PIN1_PORT11_Msk (0x01UL << GPIO_PORT_PIN1_PORT11_Pos) /*!< GPIO_PORT PIN1: PORT11 Mask */
+#define GPIO_PORT_PIN1_PORT12_Pos 12 /*!< GPIO_PORT PIN1: PORT12 Position */
+#define GPIO_PORT_PIN1_PORT12_Msk (0x01UL << GPIO_PORT_PIN1_PORT12_Pos) /*!< GPIO_PORT PIN1: PORT12 Mask */
+#define GPIO_PORT_PIN1_PORT13_Pos 13 /*!< GPIO_PORT PIN1: PORT13 Position */
+#define GPIO_PORT_PIN1_PORT13_Msk (0x01UL << GPIO_PORT_PIN1_PORT13_Pos) /*!< GPIO_PORT PIN1: PORT13 Mask */
+#define GPIO_PORT_PIN1_PORT14_Pos 14 /*!< GPIO_PORT PIN1: PORT14 Position */
+#define GPIO_PORT_PIN1_PORT14_Msk (0x01UL << GPIO_PORT_PIN1_PORT14_Pos) /*!< GPIO_PORT PIN1: PORT14 Mask */
+#define GPIO_PORT_PIN1_PORT15_Pos 15 /*!< GPIO_PORT PIN1: PORT15 Position */
+#define GPIO_PORT_PIN1_PORT15_Msk (0x01UL << GPIO_PORT_PIN1_PORT15_Pos) /*!< GPIO_PORT PIN1: PORT15 Mask */
+#define GPIO_PORT_PIN1_PORT16_Pos 16 /*!< GPIO_PORT PIN1: PORT16 Position */
+#define GPIO_PORT_PIN1_PORT16_Msk (0x01UL << GPIO_PORT_PIN1_PORT16_Pos) /*!< GPIO_PORT PIN1: PORT16 Mask */
+#define GPIO_PORT_PIN1_PORT17_Pos 17 /*!< GPIO_PORT PIN1: PORT17 Position */
+#define GPIO_PORT_PIN1_PORT17_Msk (0x01UL << GPIO_PORT_PIN1_PORT17_Pos) /*!< GPIO_PORT PIN1: PORT17 Mask */
+#define GPIO_PORT_PIN1_PORT18_Pos 18 /*!< GPIO_PORT PIN1: PORT18 Position */
+#define GPIO_PORT_PIN1_PORT18_Msk (0x01UL << GPIO_PORT_PIN1_PORT18_Pos) /*!< GPIO_PORT PIN1: PORT18 Mask */
+#define GPIO_PORT_PIN1_PORT19_Pos 19 /*!< GPIO_PORT PIN1: PORT19 Position */
+#define GPIO_PORT_PIN1_PORT19_Msk (0x01UL << GPIO_PORT_PIN1_PORT19_Pos) /*!< GPIO_PORT PIN1: PORT19 Mask */
+#define GPIO_PORT_PIN1_PORT20_Pos 20 /*!< GPIO_PORT PIN1: PORT20 Position */
+#define GPIO_PORT_PIN1_PORT20_Msk (0x01UL << GPIO_PORT_PIN1_PORT20_Pos) /*!< GPIO_PORT PIN1: PORT20 Mask */
+#define GPIO_PORT_PIN1_PORT21_Pos 21 /*!< GPIO_PORT PIN1: PORT21 Position */
+#define GPIO_PORT_PIN1_PORT21_Msk (0x01UL << GPIO_PORT_PIN1_PORT21_Pos) /*!< GPIO_PORT PIN1: PORT21 Mask */
+#define GPIO_PORT_PIN1_PORT22_Pos 22 /*!< GPIO_PORT PIN1: PORT22 Position */
+#define GPIO_PORT_PIN1_PORT22_Msk (0x01UL << GPIO_PORT_PIN1_PORT22_Pos) /*!< GPIO_PORT PIN1: PORT22 Mask */
+#define GPIO_PORT_PIN1_PORT23_Pos 23 /*!< GPIO_PORT PIN1: PORT23 Position */
+#define GPIO_PORT_PIN1_PORT23_Msk (0x01UL << GPIO_PORT_PIN1_PORT23_Pos) /*!< GPIO_PORT PIN1: PORT23 Mask */
+#define GPIO_PORT_PIN1_PORT24_Pos 24 /*!< GPIO_PORT PIN1: PORT24 Position */
+#define GPIO_PORT_PIN1_PORT24_Msk (0x01UL << GPIO_PORT_PIN1_PORT24_Pos) /*!< GPIO_PORT PIN1: PORT24 Mask */
+#define GPIO_PORT_PIN1_PORT25_Pos 25 /*!< GPIO_PORT PIN1: PORT25 Position */
+#define GPIO_PORT_PIN1_PORT25_Msk (0x01UL << GPIO_PORT_PIN1_PORT25_Pos) /*!< GPIO_PORT PIN1: PORT25 Mask */
+#define GPIO_PORT_PIN1_PORT26_Pos 26 /*!< GPIO_PORT PIN1: PORT26 Position */
+#define GPIO_PORT_PIN1_PORT26_Msk (0x01UL << GPIO_PORT_PIN1_PORT26_Pos) /*!< GPIO_PORT PIN1: PORT26 Mask */
+#define GPIO_PORT_PIN1_PORT27_Pos 27 /*!< GPIO_PORT PIN1: PORT27 Position */
+#define GPIO_PORT_PIN1_PORT27_Msk (0x01UL << GPIO_PORT_PIN1_PORT27_Pos) /*!< GPIO_PORT PIN1: PORT27 Mask */
+#define GPIO_PORT_PIN1_PORT28_Pos 28 /*!< GPIO_PORT PIN1: PORT28 Position */
+#define GPIO_PORT_PIN1_PORT28_Msk (0x01UL << GPIO_PORT_PIN1_PORT28_Pos) /*!< GPIO_PORT PIN1: PORT28 Mask */
+#define GPIO_PORT_PIN1_PORT29_Pos 29 /*!< GPIO_PORT PIN1: PORT29 Position */
+#define GPIO_PORT_PIN1_PORT29_Msk (0x01UL << GPIO_PORT_PIN1_PORT29_Pos) /*!< GPIO_PORT PIN1: PORT29 Mask */
+#define GPIO_PORT_PIN1_PORT30_Pos 30 /*!< GPIO_PORT PIN1: PORT30 Position */
+#define GPIO_PORT_PIN1_PORT30_Msk (0x01UL << GPIO_PORT_PIN1_PORT30_Pos) /*!< GPIO_PORT PIN1: PORT30 Mask */
+#define GPIO_PORT_PIN1_PORT31_Pos 31 /*!< GPIO_PORT PIN1: PORT31 Position */
+#define GPIO_PORT_PIN1_PORT31_Msk (0x01UL << GPIO_PORT_PIN1_PORT31_Pos) /*!< GPIO_PORT PIN1: PORT31 Mask */
+
+// ------------------------------------- GPIO_PORT_PIN2 -----------------------------------------
+#define GPIO_PORT_PIN2_PORT0_Pos 0 /*!< GPIO_PORT PIN2: PORT0 Position */
+#define GPIO_PORT_PIN2_PORT0_Msk (0x01UL << GPIO_PORT_PIN2_PORT0_Pos) /*!< GPIO_PORT PIN2: PORT0 Mask */
+#define GPIO_PORT_PIN2_PORT1_Pos 1 /*!< GPIO_PORT PIN2: PORT1 Position */
+#define GPIO_PORT_PIN2_PORT1_Msk (0x01UL << GPIO_PORT_PIN2_PORT1_Pos) /*!< GPIO_PORT PIN2: PORT1 Mask */
+#define GPIO_PORT_PIN2_PORT2_Pos 2 /*!< GPIO_PORT PIN2: PORT2 Position */
+#define GPIO_PORT_PIN2_PORT2_Msk (0x01UL << GPIO_PORT_PIN2_PORT2_Pos) /*!< GPIO_PORT PIN2: PORT2 Mask */
+#define GPIO_PORT_PIN2_PORT3_Pos 3 /*!< GPIO_PORT PIN2: PORT3 Position */
+#define GPIO_PORT_PIN2_PORT3_Msk (0x01UL << GPIO_PORT_PIN2_PORT3_Pos) /*!< GPIO_PORT PIN2: PORT3 Mask */
+#define GPIO_PORT_PIN2_PORT4_Pos 4 /*!< GPIO_PORT PIN2: PORT4 Position */
+#define GPIO_PORT_PIN2_PORT4_Msk (0x01UL << GPIO_PORT_PIN2_PORT4_Pos) /*!< GPIO_PORT PIN2: PORT4 Mask */
+#define GPIO_PORT_PIN2_PORT5_Pos 5 /*!< GPIO_PORT PIN2: PORT5 Position */
+#define GPIO_PORT_PIN2_PORT5_Msk (0x01UL << GPIO_PORT_PIN2_PORT5_Pos) /*!< GPIO_PORT PIN2: PORT5 Mask */
+#define GPIO_PORT_PIN2_PORT6_Pos 6 /*!< GPIO_PORT PIN2: PORT6 Position */
+#define GPIO_PORT_PIN2_PORT6_Msk (0x01UL << GPIO_PORT_PIN2_PORT6_Pos) /*!< GPIO_PORT PIN2: PORT6 Mask */
+#define GPIO_PORT_PIN2_PORT7_Pos 7 /*!< GPIO_PORT PIN2: PORT7 Position */
+#define GPIO_PORT_PIN2_PORT7_Msk (0x01UL << GPIO_PORT_PIN2_PORT7_Pos) /*!< GPIO_PORT PIN2: PORT7 Mask */
+#define GPIO_PORT_PIN2_PORT8_Pos 8 /*!< GPIO_PORT PIN2: PORT8 Position */
+#define GPIO_PORT_PIN2_PORT8_Msk (0x01UL << GPIO_PORT_PIN2_PORT8_Pos) /*!< GPIO_PORT PIN2: PORT8 Mask */
+#define GPIO_PORT_PIN2_PORT9_Pos 9 /*!< GPIO_PORT PIN2: PORT9 Position */
+#define GPIO_PORT_PIN2_PORT9_Msk (0x01UL << GPIO_PORT_PIN2_PORT9_Pos) /*!< GPIO_PORT PIN2: PORT9 Mask */
+#define GPIO_PORT_PIN2_PORT10_Pos 10 /*!< GPIO_PORT PIN2: PORT10 Position */
+#define GPIO_PORT_PIN2_PORT10_Msk (0x01UL << GPIO_PORT_PIN2_PORT10_Pos) /*!< GPIO_PORT PIN2: PORT10 Mask */
+#define GPIO_PORT_PIN2_PORT11_Pos 11 /*!< GPIO_PORT PIN2: PORT11 Position */
+#define GPIO_PORT_PIN2_PORT11_Msk (0x01UL << GPIO_PORT_PIN2_PORT11_Pos) /*!< GPIO_PORT PIN2: PORT11 Mask */
+#define GPIO_PORT_PIN2_PORT12_Pos 12 /*!< GPIO_PORT PIN2: PORT12 Position */
+#define GPIO_PORT_PIN2_PORT12_Msk (0x01UL << GPIO_PORT_PIN2_PORT12_Pos) /*!< GPIO_PORT PIN2: PORT12 Mask */
+#define GPIO_PORT_PIN2_PORT13_Pos 13 /*!< GPIO_PORT PIN2: PORT13 Position */
+#define GPIO_PORT_PIN2_PORT13_Msk (0x01UL << GPIO_PORT_PIN2_PORT13_Pos) /*!< GPIO_PORT PIN2: PORT13 Mask */
+#define GPIO_PORT_PIN2_PORT14_Pos 14 /*!< GPIO_PORT PIN2: PORT14 Position */
+#define GPIO_PORT_PIN2_PORT14_Msk (0x01UL << GPIO_PORT_PIN2_PORT14_Pos) /*!< GPIO_PORT PIN2: PORT14 Mask */
+#define GPIO_PORT_PIN2_PORT15_Pos 15 /*!< GPIO_PORT PIN2: PORT15 Position */
+#define GPIO_PORT_PIN2_PORT15_Msk (0x01UL << GPIO_PORT_PIN2_PORT15_Pos) /*!< GPIO_PORT PIN2: PORT15 Mask */
+#define GPIO_PORT_PIN2_PORT16_Pos 16 /*!< GPIO_PORT PIN2: PORT16 Position */
+#define GPIO_PORT_PIN2_PORT16_Msk (0x01UL << GPIO_PORT_PIN2_PORT16_Pos) /*!< GPIO_PORT PIN2: PORT16 Mask */
+#define GPIO_PORT_PIN2_PORT17_Pos 17 /*!< GPIO_PORT PIN2: PORT17 Position */
+#define GPIO_PORT_PIN2_PORT17_Msk (0x01UL << GPIO_PORT_PIN2_PORT17_Pos) /*!< GPIO_PORT PIN2: PORT17 Mask */
+#define GPIO_PORT_PIN2_PORT18_Pos 18 /*!< GPIO_PORT PIN2: PORT18 Position */
+#define GPIO_PORT_PIN2_PORT18_Msk (0x01UL << GPIO_PORT_PIN2_PORT18_Pos) /*!< GPIO_PORT PIN2: PORT18 Mask */
+#define GPIO_PORT_PIN2_PORT19_Pos 19 /*!< GPIO_PORT PIN2: PORT19 Position */
+#define GPIO_PORT_PIN2_PORT19_Msk (0x01UL << GPIO_PORT_PIN2_PORT19_Pos) /*!< GPIO_PORT PIN2: PORT19 Mask */
+#define GPIO_PORT_PIN2_PORT20_Pos 20 /*!< GPIO_PORT PIN2: PORT20 Position */
+#define GPIO_PORT_PIN2_PORT20_Msk (0x01UL << GPIO_PORT_PIN2_PORT20_Pos) /*!< GPIO_PORT PIN2: PORT20 Mask */
+#define GPIO_PORT_PIN2_PORT21_Pos 21 /*!< GPIO_PORT PIN2: PORT21 Position */
+#define GPIO_PORT_PIN2_PORT21_Msk (0x01UL << GPIO_PORT_PIN2_PORT21_Pos) /*!< GPIO_PORT PIN2: PORT21 Mask */
+#define GPIO_PORT_PIN2_PORT22_Pos 22 /*!< GPIO_PORT PIN2: PORT22 Position */
+#define GPIO_PORT_PIN2_PORT22_Msk (0x01UL << GPIO_PORT_PIN2_PORT22_Pos) /*!< GPIO_PORT PIN2: PORT22 Mask */
+#define GPIO_PORT_PIN2_PORT23_Pos 23 /*!< GPIO_PORT PIN2: PORT23 Position */
+#define GPIO_PORT_PIN2_PORT23_Msk (0x01UL << GPIO_PORT_PIN2_PORT23_Pos) /*!< GPIO_PORT PIN2: PORT23 Mask */
+#define GPIO_PORT_PIN2_PORT24_Pos 24 /*!< GPIO_PORT PIN2: PORT24 Position */
+#define GPIO_PORT_PIN2_PORT24_Msk (0x01UL << GPIO_PORT_PIN2_PORT24_Pos) /*!< GPIO_PORT PIN2: PORT24 Mask */
+#define GPIO_PORT_PIN2_PORT25_Pos 25 /*!< GPIO_PORT PIN2: PORT25 Position */
+#define GPIO_PORT_PIN2_PORT25_Msk (0x01UL << GPIO_PORT_PIN2_PORT25_Pos) /*!< GPIO_PORT PIN2: PORT25 Mask */
+#define GPIO_PORT_PIN2_PORT26_Pos 26 /*!< GPIO_PORT PIN2: PORT26 Position */
+#define GPIO_PORT_PIN2_PORT26_Msk (0x01UL << GPIO_PORT_PIN2_PORT26_Pos) /*!< GPIO_PORT PIN2: PORT26 Mask */
+#define GPIO_PORT_PIN2_PORT27_Pos 27 /*!< GPIO_PORT PIN2: PORT27 Position */
+#define GPIO_PORT_PIN2_PORT27_Msk (0x01UL << GPIO_PORT_PIN2_PORT27_Pos) /*!< GPIO_PORT PIN2: PORT27 Mask */
+#define GPIO_PORT_PIN2_PORT28_Pos 28 /*!< GPIO_PORT PIN2: PORT28 Position */
+#define GPIO_PORT_PIN2_PORT28_Msk (0x01UL << GPIO_PORT_PIN2_PORT28_Pos) /*!< GPIO_PORT PIN2: PORT28 Mask */
+#define GPIO_PORT_PIN2_PORT29_Pos 29 /*!< GPIO_PORT PIN2: PORT29 Position */
+#define GPIO_PORT_PIN2_PORT29_Msk (0x01UL << GPIO_PORT_PIN2_PORT29_Pos) /*!< GPIO_PORT PIN2: PORT29 Mask */
+#define GPIO_PORT_PIN2_PORT30_Pos 30 /*!< GPIO_PORT PIN2: PORT30 Position */
+#define GPIO_PORT_PIN2_PORT30_Msk (0x01UL << GPIO_PORT_PIN2_PORT30_Pos) /*!< GPIO_PORT PIN2: PORT30 Mask */
+#define GPIO_PORT_PIN2_PORT31_Pos 31 /*!< GPIO_PORT PIN2: PORT31 Position */
+#define GPIO_PORT_PIN2_PORT31_Msk (0x01UL << GPIO_PORT_PIN2_PORT31_Pos) /*!< GPIO_PORT PIN2: PORT31 Mask */
+
+// ------------------------------------- GPIO_PORT_PIN3 -----------------------------------------
+#define GPIO_PORT_PIN3_PORT0_Pos 0 /*!< GPIO_PORT PIN3: PORT0 Position */
+#define GPIO_PORT_PIN3_PORT0_Msk (0x01UL << GPIO_PORT_PIN3_PORT0_Pos) /*!< GPIO_PORT PIN3: PORT0 Mask */
+#define GPIO_PORT_PIN3_PORT1_Pos 1 /*!< GPIO_PORT PIN3: PORT1 Position */
+#define GPIO_PORT_PIN3_PORT1_Msk (0x01UL << GPIO_PORT_PIN3_PORT1_Pos) /*!< GPIO_PORT PIN3: PORT1 Mask */
+#define GPIO_PORT_PIN3_PORT2_Pos 2 /*!< GPIO_PORT PIN3: PORT2 Position */
+#define GPIO_PORT_PIN3_PORT2_Msk (0x01UL << GPIO_PORT_PIN3_PORT2_Pos) /*!< GPIO_PORT PIN3: PORT2 Mask */
+#define GPIO_PORT_PIN3_PORT3_Pos 3 /*!< GPIO_PORT PIN3: PORT3 Position */
+#define GPIO_PORT_PIN3_PORT3_Msk (0x01UL << GPIO_PORT_PIN3_PORT3_Pos) /*!< GPIO_PORT PIN3: PORT3 Mask */
+#define GPIO_PORT_PIN3_PORT4_Pos 4 /*!< GPIO_PORT PIN3: PORT4 Position */
+#define GPIO_PORT_PIN3_PORT4_Msk (0x01UL << GPIO_PORT_PIN3_PORT4_Pos) /*!< GPIO_PORT PIN3: PORT4 Mask */
+#define GPIO_PORT_PIN3_PORT5_Pos 5 /*!< GPIO_PORT PIN3: PORT5 Position */
+#define GPIO_PORT_PIN3_PORT5_Msk (0x01UL << GPIO_PORT_PIN3_PORT5_Pos) /*!< GPIO_PORT PIN3: PORT5 Mask */
+#define GPIO_PORT_PIN3_PORT6_Pos 6 /*!< GPIO_PORT PIN3: PORT6 Position */
+#define GPIO_PORT_PIN3_PORT6_Msk (0x01UL << GPIO_PORT_PIN3_PORT6_Pos) /*!< GPIO_PORT PIN3: PORT6 Mask */
+#define GPIO_PORT_PIN3_PORT7_Pos 7 /*!< GPIO_PORT PIN3: PORT7 Position */
+#define GPIO_PORT_PIN3_PORT7_Msk (0x01UL << GPIO_PORT_PIN3_PORT7_Pos) /*!< GPIO_PORT PIN3: PORT7 Mask */
+#define GPIO_PORT_PIN3_PORT8_Pos 8 /*!< GPIO_PORT PIN3: PORT8 Position */
+#define GPIO_PORT_PIN3_PORT8_Msk (0x01UL << GPIO_PORT_PIN3_PORT8_Pos) /*!< GPIO_PORT PIN3: PORT8 Mask */
+#define GPIO_PORT_PIN3_PORT9_Pos 9 /*!< GPIO_PORT PIN3: PORT9 Position */
+#define GPIO_PORT_PIN3_PORT9_Msk (0x01UL << GPIO_PORT_PIN3_PORT9_Pos) /*!< GPIO_PORT PIN3: PORT9 Mask */
+#define GPIO_PORT_PIN3_PORT10_Pos 10 /*!< GPIO_PORT PIN3: PORT10 Position */
+#define GPIO_PORT_PIN3_PORT10_Msk (0x01UL << GPIO_PORT_PIN3_PORT10_Pos) /*!< GPIO_PORT PIN3: PORT10 Mask */
+#define GPIO_PORT_PIN3_PORT11_Pos 11 /*!< GPIO_PORT PIN3: PORT11 Position */
+#define GPIO_PORT_PIN3_PORT11_Msk (0x01UL << GPIO_PORT_PIN3_PORT11_Pos) /*!< GPIO_PORT PIN3: PORT11 Mask */
+#define GPIO_PORT_PIN3_PORT12_Pos 12 /*!< GPIO_PORT PIN3: PORT12 Position */
+#define GPIO_PORT_PIN3_PORT12_Msk (0x01UL << GPIO_PORT_PIN3_PORT12_Pos) /*!< GPIO_PORT PIN3: PORT12 Mask */
+#define GPIO_PORT_PIN3_PORT13_Pos 13 /*!< GPIO_PORT PIN3: PORT13 Position */
+#define GPIO_PORT_PIN3_PORT13_Msk (0x01UL << GPIO_PORT_PIN3_PORT13_Pos) /*!< GPIO_PORT PIN3: PORT13 Mask */
+#define GPIO_PORT_PIN3_PORT14_Pos 14 /*!< GPIO_PORT PIN3: PORT14 Position */
+#define GPIO_PORT_PIN3_PORT14_Msk (0x01UL << GPIO_PORT_PIN3_PORT14_Pos) /*!< GPIO_PORT PIN3: PORT14 Mask */
+#define GPIO_PORT_PIN3_PORT15_Pos 15 /*!< GPIO_PORT PIN3: PORT15 Position */
+#define GPIO_PORT_PIN3_PORT15_Msk (0x01UL << GPIO_PORT_PIN3_PORT15_Pos) /*!< GPIO_PORT PIN3: PORT15 Mask */
+#define GPIO_PORT_PIN3_PORT16_Pos 16 /*!< GPIO_PORT PIN3: PORT16 Position */
+#define GPIO_PORT_PIN3_PORT16_Msk (0x01UL << GPIO_PORT_PIN3_PORT16_Pos) /*!< GPIO_PORT PIN3: PORT16 Mask */
+#define GPIO_PORT_PIN3_PORT17_Pos 17 /*!< GPIO_PORT PIN3: PORT17 Position */
+#define GPIO_PORT_PIN3_PORT17_Msk (0x01UL << GPIO_PORT_PIN3_PORT17_Pos) /*!< GPIO_PORT PIN3: PORT17 Mask */
+#define GPIO_PORT_PIN3_PORT18_Pos 18 /*!< GPIO_PORT PIN3: PORT18 Position */
+#define GPIO_PORT_PIN3_PORT18_Msk (0x01UL << GPIO_PORT_PIN3_PORT18_Pos) /*!< GPIO_PORT PIN3: PORT18 Mask */
+#define GPIO_PORT_PIN3_PORT19_Pos 19 /*!< GPIO_PORT PIN3: PORT19 Position */
+#define GPIO_PORT_PIN3_PORT19_Msk (0x01UL << GPIO_PORT_PIN3_PORT19_Pos) /*!< GPIO_PORT PIN3: PORT19 Mask */
+#define GPIO_PORT_PIN3_PORT20_Pos 20 /*!< GPIO_PORT PIN3: PORT20 Position */
+#define GPIO_PORT_PIN3_PORT20_Msk (0x01UL << GPIO_PORT_PIN3_PORT20_Pos) /*!< GPIO_PORT PIN3: PORT20 Mask */
+#define GPIO_PORT_PIN3_PORT21_Pos 21 /*!< GPIO_PORT PIN3: PORT21 Position */
+#define GPIO_PORT_PIN3_PORT21_Msk (0x01UL << GPIO_PORT_PIN3_PORT21_Pos) /*!< GPIO_PORT PIN3: PORT21 Mask */
+#define GPIO_PORT_PIN3_PORT22_Pos 22 /*!< GPIO_PORT PIN3: PORT22 Position */
+#define GPIO_PORT_PIN3_PORT22_Msk (0x01UL << GPIO_PORT_PIN3_PORT22_Pos) /*!< GPIO_PORT PIN3: PORT22 Mask */
+#define GPIO_PORT_PIN3_PORT23_Pos 23 /*!< GPIO_PORT PIN3: PORT23 Position */
+#define GPIO_PORT_PIN3_PORT23_Msk (0x01UL << GPIO_PORT_PIN3_PORT23_Pos) /*!< GPIO_PORT PIN3: PORT23 Mask */
+#define GPIO_PORT_PIN3_PORT24_Pos 24 /*!< GPIO_PORT PIN3: PORT24 Position */
+#define GPIO_PORT_PIN3_PORT24_Msk (0x01UL << GPIO_PORT_PIN3_PORT24_Pos) /*!< GPIO_PORT PIN3: PORT24 Mask */
+#define GPIO_PORT_PIN3_PORT25_Pos 25 /*!< GPIO_PORT PIN3: PORT25 Position */
+#define GPIO_PORT_PIN3_PORT25_Msk (0x01UL << GPIO_PORT_PIN3_PORT25_Pos) /*!< GPIO_PORT PIN3: PORT25 Mask */
+#define GPIO_PORT_PIN3_PORT26_Pos 26 /*!< GPIO_PORT PIN3: PORT26 Position */
+#define GPIO_PORT_PIN3_PORT26_Msk (0x01UL << GPIO_PORT_PIN3_PORT26_Pos) /*!< GPIO_PORT PIN3: PORT26 Mask */
+#define GPIO_PORT_PIN3_PORT27_Pos 27 /*!< GPIO_PORT PIN3: PORT27 Position */
+#define GPIO_PORT_PIN3_PORT27_Msk (0x01UL << GPIO_PORT_PIN3_PORT27_Pos) /*!< GPIO_PORT PIN3: PORT27 Mask */
+#define GPIO_PORT_PIN3_PORT28_Pos 28 /*!< GPIO_PORT PIN3: PORT28 Position */
+#define GPIO_PORT_PIN3_PORT28_Msk (0x01UL << GPIO_PORT_PIN3_PORT28_Pos) /*!< GPIO_PORT PIN3: PORT28 Mask */
+#define GPIO_PORT_PIN3_PORT29_Pos 29 /*!< GPIO_PORT PIN3: PORT29 Position */
+#define GPIO_PORT_PIN3_PORT29_Msk (0x01UL << GPIO_PORT_PIN3_PORT29_Pos) /*!< GPIO_PORT PIN3: PORT29 Mask */
+#define GPIO_PORT_PIN3_PORT30_Pos 30 /*!< GPIO_PORT PIN3: PORT30 Position */
+#define GPIO_PORT_PIN3_PORT30_Msk (0x01UL << GPIO_PORT_PIN3_PORT30_Pos) /*!< GPIO_PORT PIN3: PORT30 Mask */
+#define GPIO_PORT_PIN3_PORT31_Pos 31 /*!< GPIO_PORT PIN3: PORT31 Position */
+#define GPIO_PORT_PIN3_PORT31_Msk (0x01UL << GPIO_PORT_PIN3_PORT31_Pos) /*!< GPIO_PORT PIN3: PORT31 Mask */
+
+// ------------------------------------- GPIO_PORT_PIN4 -----------------------------------------
+#define GPIO_PORT_PIN4_PORT0_Pos 0 /*!< GPIO_PORT PIN4: PORT0 Position */
+#define GPIO_PORT_PIN4_PORT0_Msk (0x01UL << GPIO_PORT_PIN4_PORT0_Pos) /*!< GPIO_PORT PIN4: PORT0 Mask */
+#define GPIO_PORT_PIN4_PORT1_Pos 1 /*!< GPIO_PORT PIN4: PORT1 Position */
+#define GPIO_PORT_PIN4_PORT1_Msk (0x01UL << GPIO_PORT_PIN4_PORT1_Pos) /*!< GPIO_PORT PIN4: PORT1 Mask */
+#define GPIO_PORT_PIN4_PORT2_Pos 2 /*!< GPIO_PORT PIN4: PORT2 Position */
+#define GPIO_PORT_PIN4_PORT2_Msk (0x01UL << GPIO_PORT_PIN4_PORT2_Pos) /*!< GPIO_PORT PIN4: PORT2 Mask */
+#define GPIO_PORT_PIN4_PORT3_Pos 3 /*!< GPIO_PORT PIN4: PORT3 Position */
+#define GPIO_PORT_PIN4_PORT3_Msk (0x01UL << GPIO_PORT_PIN4_PORT3_Pos) /*!< GPIO_PORT PIN4: PORT3 Mask */
+#define GPIO_PORT_PIN4_PORT4_Pos 4 /*!< GPIO_PORT PIN4: PORT4 Position */
+#define GPIO_PORT_PIN4_PORT4_Msk (0x01UL << GPIO_PORT_PIN4_PORT4_Pos) /*!< GPIO_PORT PIN4: PORT4 Mask */
+#define GPIO_PORT_PIN4_PORT5_Pos 5 /*!< GPIO_PORT PIN4: PORT5 Position */
+#define GPIO_PORT_PIN4_PORT5_Msk (0x01UL << GPIO_PORT_PIN4_PORT5_Pos) /*!< GPIO_PORT PIN4: PORT5 Mask */
+#define GPIO_PORT_PIN4_PORT6_Pos 6 /*!< GPIO_PORT PIN4: PORT6 Position */
+#define GPIO_PORT_PIN4_PORT6_Msk (0x01UL << GPIO_PORT_PIN4_PORT6_Pos) /*!< GPIO_PORT PIN4: PORT6 Mask */
+#define GPIO_PORT_PIN4_PORT7_Pos 7 /*!< GPIO_PORT PIN4: PORT7 Position */
+#define GPIO_PORT_PIN4_PORT7_Msk (0x01UL << GPIO_PORT_PIN4_PORT7_Pos) /*!< GPIO_PORT PIN4: PORT7 Mask */
+#define GPIO_PORT_PIN4_PORT8_Pos 8 /*!< GPIO_PORT PIN4: PORT8 Position */
+#define GPIO_PORT_PIN4_PORT8_Msk (0x01UL << GPIO_PORT_PIN4_PORT8_Pos) /*!< GPIO_PORT PIN4: PORT8 Mask */
+#define GPIO_PORT_PIN4_PORT9_Pos 9 /*!< GPIO_PORT PIN4: PORT9 Position */
+#define GPIO_PORT_PIN4_PORT9_Msk (0x01UL << GPIO_PORT_PIN4_PORT9_Pos) /*!< GPIO_PORT PIN4: PORT9 Mask */
+#define GPIO_PORT_PIN4_PORT10_Pos 10 /*!< GPIO_PORT PIN4: PORT10 Position */
+#define GPIO_PORT_PIN4_PORT10_Msk (0x01UL << GPIO_PORT_PIN4_PORT10_Pos) /*!< GPIO_PORT PIN4: PORT10 Mask */
+#define GPIO_PORT_PIN4_PORT11_Pos 11 /*!< GPIO_PORT PIN4: PORT11 Position */
+#define GPIO_PORT_PIN4_PORT11_Msk (0x01UL << GPIO_PORT_PIN4_PORT11_Pos) /*!< GPIO_PORT PIN4: PORT11 Mask */
+#define GPIO_PORT_PIN4_PORT12_Pos 12 /*!< GPIO_PORT PIN4: PORT12 Position */
+#define GPIO_PORT_PIN4_PORT12_Msk (0x01UL << GPIO_PORT_PIN4_PORT12_Pos) /*!< GPIO_PORT PIN4: PORT12 Mask */
+#define GPIO_PORT_PIN4_PORT13_Pos 13 /*!< GPIO_PORT PIN4: PORT13 Position */
+#define GPIO_PORT_PIN4_PORT13_Msk (0x01UL << GPIO_PORT_PIN4_PORT13_Pos) /*!< GPIO_PORT PIN4: PORT13 Mask */
+#define GPIO_PORT_PIN4_PORT14_Pos 14 /*!< GPIO_PORT PIN4: PORT14 Position */
+#define GPIO_PORT_PIN4_PORT14_Msk (0x01UL << GPIO_PORT_PIN4_PORT14_Pos) /*!< GPIO_PORT PIN4: PORT14 Mask */
+#define GPIO_PORT_PIN4_PORT15_Pos 15 /*!< GPIO_PORT PIN4: PORT15 Position */
+#define GPIO_PORT_PIN4_PORT15_Msk (0x01UL << GPIO_PORT_PIN4_PORT15_Pos) /*!< GPIO_PORT PIN4: PORT15 Mask */
+#define GPIO_PORT_PIN4_PORT16_Pos 16 /*!< GPIO_PORT PIN4: PORT16 Position */
+#define GPIO_PORT_PIN4_PORT16_Msk (0x01UL << GPIO_PORT_PIN4_PORT16_Pos) /*!< GPIO_PORT PIN4: PORT16 Mask */
+#define GPIO_PORT_PIN4_PORT17_Pos 17 /*!< GPIO_PORT PIN4: PORT17 Position */
+#define GPIO_PORT_PIN4_PORT17_Msk (0x01UL << GPIO_PORT_PIN4_PORT17_Pos) /*!< GPIO_PORT PIN4: PORT17 Mask */
+#define GPIO_PORT_PIN4_PORT18_Pos 18 /*!< GPIO_PORT PIN4: PORT18 Position */
+#define GPIO_PORT_PIN4_PORT18_Msk (0x01UL << GPIO_PORT_PIN4_PORT18_Pos) /*!< GPIO_PORT PIN4: PORT18 Mask */
+#define GPIO_PORT_PIN4_PORT19_Pos 19 /*!< GPIO_PORT PIN4: PORT19 Position */
+#define GPIO_PORT_PIN4_PORT19_Msk (0x01UL << GPIO_PORT_PIN4_PORT19_Pos) /*!< GPIO_PORT PIN4: PORT19 Mask */
+#define GPIO_PORT_PIN4_PORT20_Pos 20 /*!< GPIO_PORT PIN4: PORT20 Position */
+#define GPIO_PORT_PIN4_PORT20_Msk (0x01UL << GPIO_PORT_PIN4_PORT20_Pos) /*!< GPIO_PORT PIN4: PORT20 Mask */
+#define GPIO_PORT_PIN4_PORT21_Pos 21 /*!< GPIO_PORT PIN4: PORT21 Position */
+#define GPIO_PORT_PIN4_PORT21_Msk (0x01UL << GPIO_PORT_PIN4_PORT21_Pos) /*!< GPIO_PORT PIN4: PORT21 Mask */
+#define GPIO_PORT_PIN4_PORT22_Pos 22 /*!< GPIO_PORT PIN4: PORT22 Position */
+#define GPIO_PORT_PIN4_PORT22_Msk (0x01UL << GPIO_PORT_PIN4_PORT22_Pos) /*!< GPIO_PORT PIN4: PORT22 Mask */
+#define GPIO_PORT_PIN4_PORT23_Pos 23 /*!< GPIO_PORT PIN4: PORT23 Position */
+#define GPIO_PORT_PIN4_PORT23_Msk (0x01UL << GPIO_PORT_PIN4_PORT23_Pos) /*!< GPIO_PORT PIN4: PORT23 Mask */
+#define GPIO_PORT_PIN4_PORT24_Pos 24 /*!< GPIO_PORT PIN4: PORT24 Position */
+#define GPIO_PORT_PIN4_PORT24_Msk (0x01UL << GPIO_PORT_PIN4_PORT24_Pos) /*!< GPIO_PORT PIN4: PORT24 Mask */
+#define GPIO_PORT_PIN4_PORT25_Pos 25 /*!< GPIO_PORT PIN4: PORT25 Position */
+#define GPIO_PORT_PIN4_PORT25_Msk (0x01UL << GPIO_PORT_PIN4_PORT25_Pos) /*!< GPIO_PORT PIN4: PORT25 Mask */
+#define GPIO_PORT_PIN4_PORT26_Pos 26 /*!< GPIO_PORT PIN4: PORT26 Position */
+#define GPIO_PORT_PIN4_PORT26_Msk (0x01UL << GPIO_PORT_PIN4_PORT26_Pos) /*!< GPIO_PORT PIN4: PORT26 Mask */
+#define GPIO_PORT_PIN4_PORT27_Pos 27 /*!< GPIO_PORT PIN4: PORT27 Position */
+#define GPIO_PORT_PIN4_PORT27_Msk (0x01UL << GPIO_PORT_PIN4_PORT27_Pos) /*!< GPIO_PORT PIN4: PORT27 Mask */
+#define GPIO_PORT_PIN4_PORT28_Pos 28 /*!< GPIO_PORT PIN4: PORT28 Position */
+#define GPIO_PORT_PIN4_PORT28_Msk (0x01UL << GPIO_PORT_PIN4_PORT28_Pos) /*!< GPIO_PORT PIN4: PORT28 Mask */
+#define GPIO_PORT_PIN4_PORT29_Pos 29 /*!< GPIO_PORT PIN4: PORT29 Position */
+#define GPIO_PORT_PIN4_PORT29_Msk (0x01UL << GPIO_PORT_PIN4_PORT29_Pos) /*!< GPIO_PORT PIN4: PORT29 Mask */
+#define GPIO_PORT_PIN4_PORT30_Pos 30 /*!< GPIO_PORT PIN4: PORT30 Position */
+#define GPIO_PORT_PIN4_PORT30_Msk (0x01UL << GPIO_PORT_PIN4_PORT30_Pos) /*!< GPIO_PORT PIN4: PORT30 Mask */
+#define GPIO_PORT_PIN4_PORT31_Pos 31 /*!< GPIO_PORT PIN4: PORT31 Position */
+#define GPIO_PORT_PIN4_PORT31_Msk (0x01UL << GPIO_PORT_PIN4_PORT31_Pos) /*!< GPIO_PORT PIN4: PORT31 Mask */
+
+// ------------------------------------- GPIO_PORT_PIN5 -----------------------------------------
+#define GPIO_PORT_PIN5_PORT0_Pos 0 /*!< GPIO_PORT PIN5: PORT0 Position */
+#define GPIO_PORT_PIN5_PORT0_Msk (0x01UL << GPIO_PORT_PIN5_PORT0_Pos) /*!< GPIO_PORT PIN5: PORT0 Mask */
+#define GPIO_PORT_PIN5_PORT1_Pos 1 /*!< GPIO_PORT PIN5: PORT1 Position */
+#define GPIO_PORT_PIN5_PORT1_Msk (0x01UL << GPIO_PORT_PIN5_PORT1_Pos) /*!< GPIO_PORT PIN5: PORT1 Mask */
+#define GPIO_PORT_PIN5_PORT2_Pos 2 /*!< GPIO_PORT PIN5: PORT2 Position */
+#define GPIO_PORT_PIN5_PORT2_Msk (0x01UL << GPIO_PORT_PIN5_PORT2_Pos) /*!< GPIO_PORT PIN5: PORT2 Mask */
+#define GPIO_PORT_PIN5_PORT3_Pos 3 /*!< GPIO_PORT PIN5: PORT3 Position */
+#define GPIO_PORT_PIN5_PORT3_Msk (0x01UL << GPIO_PORT_PIN5_PORT3_Pos) /*!< GPIO_PORT PIN5: PORT3 Mask */
+#define GPIO_PORT_PIN5_PORT4_Pos 4 /*!< GPIO_PORT PIN5: PORT4 Position */
+#define GPIO_PORT_PIN5_PORT4_Msk (0x01UL << GPIO_PORT_PIN5_PORT4_Pos) /*!< GPIO_PORT PIN5: PORT4 Mask */
+#define GPIO_PORT_PIN5_PORT5_Pos 5 /*!< GPIO_PORT PIN5: PORT5 Position */
+#define GPIO_PORT_PIN5_PORT5_Msk (0x01UL << GPIO_PORT_PIN5_PORT5_Pos) /*!< GPIO_PORT PIN5: PORT5 Mask */
+#define GPIO_PORT_PIN5_PORT6_Pos 6 /*!< GPIO_PORT PIN5: PORT6 Position */
+#define GPIO_PORT_PIN5_PORT6_Msk (0x01UL << GPIO_PORT_PIN5_PORT6_Pos) /*!< GPIO_PORT PIN5: PORT6 Mask */
+#define GPIO_PORT_PIN5_PORT7_Pos 7 /*!< GPIO_PORT PIN5: PORT7 Position */
+#define GPIO_PORT_PIN5_PORT7_Msk (0x01UL << GPIO_PORT_PIN5_PORT7_Pos) /*!< GPIO_PORT PIN5: PORT7 Mask */
+#define GPIO_PORT_PIN5_PORT8_Pos 8 /*!< GPIO_PORT PIN5: PORT8 Position */
+#define GPIO_PORT_PIN5_PORT8_Msk (0x01UL << GPIO_PORT_PIN5_PORT8_Pos) /*!< GPIO_PORT PIN5: PORT8 Mask */
+#define GPIO_PORT_PIN5_PORT9_Pos 9 /*!< GPIO_PORT PIN5: PORT9 Position */
+#define GPIO_PORT_PIN5_PORT9_Msk (0x01UL << GPIO_PORT_PIN5_PORT9_Pos) /*!< GPIO_PORT PIN5: PORT9 Mask */
+#define GPIO_PORT_PIN5_PORT10_Pos 10 /*!< GPIO_PORT PIN5: PORT10 Position */
+#define GPIO_PORT_PIN5_PORT10_Msk (0x01UL << GPIO_PORT_PIN5_PORT10_Pos) /*!< GPIO_PORT PIN5: PORT10 Mask */
+#define GPIO_PORT_PIN5_PORT11_Pos 11 /*!< GPIO_PORT PIN5: PORT11 Position */
+#define GPIO_PORT_PIN5_PORT11_Msk (0x01UL << GPIO_PORT_PIN5_PORT11_Pos) /*!< GPIO_PORT PIN5: PORT11 Mask */
+#define GPIO_PORT_PIN5_PORT12_Pos 12 /*!< GPIO_PORT PIN5: PORT12 Position */
+#define GPIO_PORT_PIN5_PORT12_Msk (0x01UL << GPIO_PORT_PIN5_PORT12_Pos) /*!< GPIO_PORT PIN5: PORT12 Mask */
+#define GPIO_PORT_PIN5_PORT13_Pos 13 /*!< GPIO_PORT PIN5: PORT13 Position */
+#define GPIO_PORT_PIN5_PORT13_Msk (0x01UL << GPIO_PORT_PIN5_PORT13_Pos) /*!< GPIO_PORT PIN5: PORT13 Mask */
+#define GPIO_PORT_PIN5_PORT14_Pos 14 /*!< GPIO_PORT PIN5: PORT14 Position */
+#define GPIO_PORT_PIN5_PORT14_Msk (0x01UL << GPIO_PORT_PIN5_PORT14_Pos) /*!< GPIO_PORT PIN5: PORT14 Mask */
+#define GPIO_PORT_PIN5_PORT15_Pos 15 /*!< GPIO_PORT PIN5: PORT15 Position */
+#define GPIO_PORT_PIN5_PORT15_Msk (0x01UL << GPIO_PORT_PIN5_PORT15_Pos) /*!< GPIO_PORT PIN5: PORT15 Mask */
+#define GPIO_PORT_PIN5_PORT16_Pos 16 /*!< GPIO_PORT PIN5: PORT16 Position */
+#define GPIO_PORT_PIN5_PORT16_Msk (0x01UL << GPIO_PORT_PIN5_PORT16_Pos) /*!< GPIO_PORT PIN5: PORT16 Mask */
+#define GPIO_PORT_PIN5_PORT17_Pos 17 /*!< GPIO_PORT PIN5: PORT17 Position */
+#define GPIO_PORT_PIN5_PORT17_Msk (0x01UL << GPIO_PORT_PIN5_PORT17_Pos) /*!< GPIO_PORT PIN5: PORT17 Mask */
+#define GPIO_PORT_PIN5_PORT18_Pos 18 /*!< GPIO_PORT PIN5: PORT18 Position */
+#define GPIO_PORT_PIN5_PORT18_Msk (0x01UL << GPIO_PORT_PIN5_PORT18_Pos) /*!< GPIO_PORT PIN5: PORT18 Mask */
+#define GPIO_PORT_PIN5_PORT19_Pos 19 /*!< GPIO_PORT PIN5: PORT19 Position */
+#define GPIO_PORT_PIN5_PORT19_Msk (0x01UL << GPIO_PORT_PIN5_PORT19_Pos) /*!< GPIO_PORT PIN5: PORT19 Mask */
+#define GPIO_PORT_PIN5_PORT20_Pos 20 /*!< GPIO_PORT PIN5: PORT20 Position */
+#define GPIO_PORT_PIN5_PORT20_Msk (0x01UL << GPIO_PORT_PIN5_PORT20_Pos) /*!< GPIO_PORT PIN5: PORT20 Mask */
+#define GPIO_PORT_PIN5_PORT21_Pos 21 /*!< GPIO_PORT PIN5: PORT21 Position */
+#define GPIO_PORT_PIN5_PORT21_Msk (0x01UL << GPIO_PORT_PIN5_PORT21_Pos) /*!< GPIO_PORT PIN5: PORT21 Mask */
+#define GPIO_PORT_PIN5_PORT22_Pos 22 /*!< GPIO_PORT PIN5: PORT22 Position */
+#define GPIO_PORT_PIN5_PORT22_Msk (0x01UL << GPIO_PORT_PIN5_PORT22_Pos) /*!< GPIO_PORT PIN5: PORT22 Mask */
+#define GPIO_PORT_PIN5_PORT23_Pos 23 /*!< GPIO_PORT PIN5: PORT23 Position */
+#define GPIO_PORT_PIN5_PORT23_Msk (0x01UL << GPIO_PORT_PIN5_PORT23_Pos) /*!< GPIO_PORT PIN5: PORT23 Mask */
+#define GPIO_PORT_PIN5_PORT24_Pos 24 /*!< GPIO_PORT PIN5: PORT24 Position */
+#define GPIO_PORT_PIN5_PORT24_Msk (0x01UL << GPIO_PORT_PIN5_PORT24_Pos) /*!< GPIO_PORT PIN5: PORT24 Mask */
+#define GPIO_PORT_PIN5_PORT25_Pos 25 /*!< GPIO_PORT PIN5: PORT25 Position */
+#define GPIO_PORT_PIN5_PORT25_Msk (0x01UL << GPIO_PORT_PIN5_PORT25_Pos) /*!< GPIO_PORT PIN5: PORT25 Mask */
+#define GPIO_PORT_PIN5_PORT26_Pos 26 /*!< GPIO_PORT PIN5: PORT26 Position */
+#define GPIO_PORT_PIN5_PORT26_Msk (0x01UL << GPIO_PORT_PIN5_PORT26_Pos) /*!< GPIO_PORT PIN5: PORT26 Mask */
+#define GPIO_PORT_PIN5_PORT27_Pos 27 /*!< GPIO_PORT PIN5: PORT27 Position */
+#define GPIO_PORT_PIN5_PORT27_Msk (0x01UL << GPIO_PORT_PIN5_PORT27_Pos) /*!< GPIO_PORT PIN5: PORT27 Mask */
+#define GPIO_PORT_PIN5_PORT28_Pos 28 /*!< GPIO_PORT PIN5: PORT28 Position */
+#define GPIO_PORT_PIN5_PORT28_Msk (0x01UL << GPIO_PORT_PIN5_PORT28_Pos) /*!< GPIO_PORT PIN5: PORT28 Mask */
+#define GPIO_PORT_PIN5_PORT29_Pos 29 /*!< GPIO_PORT PIN5: PORT29 Position */
+#define GPIO_PORT_PIN5_PORT29_Msk (0x01UL << GPIO_PORT_PIN5_PORT29_Pos) /*!< GPIO_PORT PIN5: PORT29 Mask */
+#define GPIO_PORT_PIN5_PORT30_Pos 30 /*!< GPIO_PORT PIN5: PORT30 Position */
+#define GPIO_PORT_PIN5_PORT30_Msk (0x01UL << GPIO_PORT_PIN5_PORT30_Pos) /*!< GPIO_PORT PIN5: PORT30 Mask */
+#define GPIO_PORT_PIN5_PORT31_Pos 31 /*!< GPIO_PORT PIN5: PORT31 Position */
+#define GPIO_PORT_PIN5_PORT31_Msk (0x01UL << GPIO_PORT_PIN5_PORT31_Pos) /*!< GPIO_PORT PIN5: PORT31 Mask */
+
+// ------------------------------------- GPIO_PORT_PIN6 -----------------------------------------
+#define GPIO_PORT_PIN6_PORT0_Pos 0 /*!< GPIO_PORT PIN6: PORT0 Position */
+#define GPIO_PORT_PIN6_PORT0_Msk (0x01UL << GPIO_PORT_PIN6_PORT0_Pos) /*!< GPIO_PORT PIN6: PORT0 Mask */
+#define GPIO_PORT_PIN6_PORT1_Pos 1 /*!< GPIO_PORT PIN6: PORT1 Position */
+#define GPIO_PORT_PIN6_PORT1_Msk (0x01UL << GPIO_PORT_PIN6_PORT1_Pos) /*!< GPIO_PORT PIN6: PORT1 Mask */
+#define GPIO_PORT_PIN6_PORT2_Pos 2 /*!< GPIO_PORT PIN6: PORT2 Position */
+#define GPIO_PORT_PIN6_PORT2_Msk (0x01UL << GPIO_PORT_PIN6_PORT2_Pos) /*!< GPIO_PORT PIN6: PORT2 Mask */
+#define GPIO_PORT_PIN6_PORT3_Pos 3 /*!< GPIO_PORT PIN6: PORT3 Position */
+#define GPIO_PORT_PIN6_PORT3_Msk (0x01UL << GPIO_PORT_PIN6_PORT3_Pos) /*!< GPIO_PORT PIN6: PORT3 Mask */
+#define GPIO_PORT_PIN6_PORT4_Pos 4 /*!< GPIO_PORT PIN6: PORT4 Position */
+#define GPIO_PORT_PIN6_PORT4_Msk (0x01UL << GPIO_PORT_PIN6_PORT4_Pos) /*!< GPIO_PORT PIN6: PORT4 Mask */
+#define GPIO_PORT_PIN6_PORT5_Pos 5 /*!< GPIO_PORT PIN6: PORT5 Position */
+#define GPIO_PORT_PIN6_PORT5_Msk (0x01UL << GPIO_PORT_PIN6_PORT5_Pos) /*!< GPIO_PORT PIN6: PORT5 Mask */
+#define GPIO_PORT_PIN6_PORT6_Pos 6 /*!< GPIO_PORT PIN6: PORT6 Position */
+#define GPIO_PORT_PIN6_PORT6_Msk (0x01UL << GPIO_PORT_PIN6_PORT6_Pos) /*!< GPIO_PORT PIN6: PORT6 Mask */
+#define GPIO_PORT_PIN6_PORT7_Pos 7 /*!< GPIO_PORT PIN6: PORT7 Position */
+#define GPIO_PORT_PIN6_PORT7_Msk (0x01UL << GPIO_PORT_PIN6_PORT7_Pos) /*!< GPIO_PORT PIN6: PORT7 Mask */
+#define GPIO_PORT_PIN6_PORT8_Pos 8 /*!< GPIO_PORT PIN6: PORT8 Position */
+#define GPIO_PORT_PIN6_PORT8_Msk (0x01UL << GPIO_PORT_PIN6_PORT8_Pos) /*!< GPIO_PORT PIN6: PORT8 Mask */
+#define GPIO_PORT_PIN6_PORT9_Pos 9 /*!< GPIO_PORT PIN6: PORT9 Position */
+#define GPIO_PORT_PIN6_PORT9_Msk (0x01UL << GPIO_PORT_PIN6_PORT9_Pos) /*!< GPIO_PORT PIN6: PORT9 Mask */
+#define GPIO_PORT_PIN6_PORT10_Pos 10 /*!< GPIO_PORT PIN6: PORT10 Position */
+#define GPIO_PORT_PIN6_PORT10_Msk (0x01UL << GPIO_PORT_PIN6_PORT10_Pos) /*!< GPIO_PORT PIN6: PORT10 Mask */
+#define GPIO_PORT_PIN6_PORT11_Pos 11 /*!< GPIO_PORT PIN6: PORT11 Position */
+#define GPIO_PORT_PIN6_PORT11_Msk (0x01UL << GPIO_PORT_PIN6_PORT11_Pos) /*!< GPIO_PORT PIN6: PORT11 Mask */
+#define GPIO_PORT_PIN6_PORT12_Pos 12 /*!< GPIO_PORT PIN6: PORT12 Position */
+#define GPIO_PORT_PIN6_PORT12_Msk (0x01UL << GPIO_PORT_PIN6_PORT12_Pos) /*!< GPIO_PORT PIN6: PORT12 Mask */
+#define GPIO_PORT_PIN6_PORT13_Pos 13 /*!< GPIO_PORT PIN6: PORT13 Position */
+#define GPIO_PORT_PIN6_PORT13_Msk (0x01UL << GPIO_PORT_PIN6_PORT13_Pos) /*!< GPIO_PORT PIN6: PORT13 Mask */
+#define GPIO_PORT_PIN6_PORT14_Pos 14 /*!< GPIO_PORT PIN6: PORT14 Position */
+#define GPIO_PORT_PIN6_PORT14_Msk (0x01UL << GPIO_PORT_PIN6_PORT14_Pos) /*!< GPIO_PORT PIN6: PORT14 Mask */
+#define GPIO_PORT_PIN6_PORT15_Pos 15 /*!< GPIO_PORT PIN6: PORT15 Position */
+#define GPIO_PORT_PIN6_PORT15_Msk (0x01UL << GPIO_PORT_PIN6_PORT15_Pos) /*!< GPIO_PORT PIN6: PORT15 Mask */
+#define GPIO_PORT_PIN6_PORT16_Pos 16 /*!< GPIO_PORT PIN6: PORT16 Position */
+#define GPIO_PORT_PIN6_PORT16_Msk (0x01UL << GPIO_PORT_PIN6_PORT16_Pos) /*!< GPIO_PORT PIN6: PORT16 Mask */
+#define GPIO_PORT_PIN6_PORT17_Pos 17 /*!< GPIO_PORT PIN6: PORT17 Position */
+#define GPIO_PORT_PIN6_PORT17_Msk (0x01UL << GPIO_PORT_PIN6_PORT17_Pos) /*!< GPIO_PORT PIN6: PORT17 Mask */
+#define GPIO_PORT_PIN6_PORT18_Pos 18 /*!< GPIO_PORT PIN6: PORT18 Position */
+#define GPIO_PORT_PIN6_PORT18_Msk (0x01UL << GPIO_PORT_PIN6_PORT18_Pos) /*!< GPIO_PORT PIN6: PORT18 Mask */
+#define GPIO_PORT_PIN6_PORT19_Pos 19 /*!< GPIO_PORT PIN6: PORT19 Position */
+#define GPIO_PORT_PIN6_PORT19_Msk (0x01UL << GPIO_PORT_PIN6_PORT19_Pos) /*!< GPIO_PORT PIN6: PORT19 Mask */
+#define GPIO_PORT_PIN6_PORT20_Pos 20 /*!< GPIO_PORT PIN6: PORT20 Position */
+#define GPIO_PORT_PIN6_PORT20_Msk (0x01UL << GPIO_PORT_PIN6_PORT20_Pos) /*!< GPIO_PORT PIN6: PORT20 Mask */
+#define GPIO_PORT_PIN6_PORT21_Pos 21 /*!< GPIO_PORT PIN6: PORT21 Position */
+#define GPIO_PORT_PIN6_PORT21_Msk (0x01UL << GPIO_PORT_PIN6_PORT21_Pos) /*!< GPIO_PORT PIN6: PORT21 Mask */
+#define GPIO_PORT_PIN6_PORT22_Pos 22 /*!< GPIO_PORT PIN6: PORT22 Position */
+#define GPIO_PORT_PIN6_PORT22_Msk (0x01UL << GPIO_PORT_PIN6_PORT22_Pos) /*!< GPIO_PORT PIN6: PORT22 Mask */
+#define GPIO_PORT_PIN6_PORT23_Pos 23 /*!< GPIO_PORT PIN6: PORT23 Position */
+#define GPIO_PORT_PIN6_PORT23_Msk (0x01UL << GPIO_PORT_PIN6_PORT23_Pos) /*!< GPIO_PORT PIN6: PORT23 Mask */
+#define GPIO_PORT_PIN6_PORT24_Pos 24 /*!< GPIO_PORT PIN6: PORT24 Position */
+#define GPIO_PORT_PIN6_PORT24_Msk (0x01UL << GPIO_PORT_PIN6_PORT24_Pos) /*!< GPIO_PORT PIN6: PORT24 Mask */
+#define GPIO_PORT_PIN6_PORT25_Pos 25 /*!< GPIO_PORT PIN6: PORT25 Position */
+#define GPIO_PORT_PIN6_PORT25_Msk (0x01UL << GPIO_PORT_PIN6_PORT25_Pos) /*!< GPIO_PORT PIN6: PORT25 Mask */
+#define GPIO_PORT_PIN6_PORT26_Pos 26 /*!< GPIO_PORT PIN6: PORT26 Position */
+#define GPIO_PORT_PIN6_PORT26_Msk (0x01UL << GPIO_PORT_PIN6_PORT26_Pos) /*!< GPIO_PORT PIN6: PORT26 Mask */
+#define GPIO_PORT_PIN6_PORT27_Pos 27 /*!< GPIO_PORT PIN6: PORT27 Position */
+#define GPIO_PORT_PIN6_PORT27_Msk (0x01UL << GPIO_PORT_PIN6_PORT27_Pos) /*!< GPIO_PORT PIN6: PORT27 Mask */
+#define GPIO_PORT_PIN6_PORT28_Pos 28 /*!< GPIO_PORT PIN6: PORT28 Position */
+#define GPIO_PORT_PIN6_PORT28_Msk (0x01UL << GPIO_PORT_PIN6_PORT28_Pos) /*!< GPIO_PORT PIN6: PORT28 Mask */
+#define GPIO_PORT_PIN6_PORT29_Pos 29 /*!< GPIO_PORT PIN6: PORT29 Position */
+#define GPIO_PORT_PIN6_PORT29_Msk (0x01UL << GPIO_PORT_PIN6_PORT29_Pos) /*!< GPIO_PORT PIN6: PORT29 Mask */
+#define GPIO_PORT_PIN6_PORT30_Pos 30 /*!< GPIO_PORT PIN6: PORT30 Position */
+#define GPIO_PORT_PIN6_PORT30_Msk (0x01UL << GPIO_PORT_PIN6_PORT30_Pos) /*!< GPIO_PORT PIN6: PORT30 Mask */
+#define GPIO_PORT_PIN6_PORT31_Pos 31 /*!< GPIO_PORT PIN6: PORT31 Position */
+#define GPIO_PORT_PIN6_PORT31_Msk (0x01UL << GPIO_PORT_PIN6_PORT31_Pos) /*!< GPIO_PORT PIN6: PORT31 Mask */
+
+// ------------------------------------- GPIO_PORT_PIN7 -----------------------------------------
+#define GPIO_PORT_PIN7_PORT0_Pos 0 /*!< GPIO_PORT PIN7: PORT0 Position */
+#define GPIO_PORT_PIN7_PORT0_Msk (0x01UL << GPIO_PORT_PIN7_PORT0_Pos) /*!< GPIO_PORT PIN7: PORT0 Mask */
+#define GPIO_PORT_PIN7_PORT1_Pos 1 /*!< GPIO_PORT PIN7: PORT1 Position */
+#define GPIO_PORT_PIN7_PORT1_Msk (0x01UL << GPIO_PORT_PIN7_PORT1_Pos) /*!< GPIO_PORT PIN7: PORT1 Mask */
+#define GPIO_PORT_PIN7_PORT2_Pos 2 /*!< GPIO_PORT PIN7: PORT2 Position */
+#define GPIO_PORT_PIN7_PORT2_Msk (0x01UL << GPIO_PORT_PIN7_PORT2_Pos) /*!< GPIO_PORT PIN7: PORT2 Mask */
+#define GPIO_PORT_PIN7_PORT3_Pos 3 /*!< GPIO_PORT PIN7: PORT3 Position */
+#define GPIO_PORT_PIN7_PORT3_Msk (0x01UL << GPIO_PORT_PIN7_PORT3_Pos) /*!< GPIO_PORT PIN7: PORT3 Mask */
+#define GPIO_PORT_PIN7_PORT4_Pos 4 /*!< GPIO_PORT PIN7: PORT4 Position */
+#define GPIO_PORT_PIN7_PORT4_Msk (0x01UL << GPIO_PORT_PIN7_PORT4_Pos) /*!< GPIO_PORT PIN7: PORT4 Mask */
+#define GPIO_PORT_PIN7_PORT5_Pos 5 /*!< GPIO_PORT PIN7: PORT5 Position */
+#define GPIO_PORT_PIN7_PORT5_Msk (0x01UL << GPIO_PORT_PIN7_PORT5_Pos) /*!< GPIO_PORT PIN7: PORT5 Mask */
+#define GPIO_PORT_PIN7_PORT6_Pos 6 /*!< GPIO_PORT PIN7: PORT6 Position */
+#define GPIO_PORT_PIN7_PORT6_Msk (0x01UL << GPIO_PORT_PIN7_PORT6_Pos) /*!< GPIO_PORT PIN7: PORT6 Mask */
+#define GPIO_PORT_PIN7_PORT7_Pos 7 /*!< GPIO_PORT PIN7: PORT7 Position */
+#define GPIO_PORT_PIN7_PORT7_Msk (0x01UL << GPIO_PORT_PIN7_PORT7_Pos) /*!< GPIO_PORT PIN7: PORT7 Mask */
+#define GPIO_PORT_PIN7_PORT8_Pos 8 /*!< GPIO_PORT PIN7: PORT8 Position */
+#define GPIO_PORT_PIN7_PORT8_Msk (0x01UL << GPIO_PORT_PIN7_PORT8_Pos) /*!< GPIO_PORT PIN7: PORT8 Mask */
+#define GPIO_PORT_PIN7_PORT9_Pos 9 /*!< GPIO_PORT PIN7: PORT9 Position */
+#define GPIO_PORT_PIN7_PORT9_Msk (0x01UL << GPIO_PORT_PIN7_PORT9_Pos) /*!< GPIO_PORT PIN7: PORT9 Mask */
+#define GPIO_PORT_PIN7_PORT10_Pos 10 /*!< GPIO_PORT PIN7: PORT10 Position */
+#define GPIO_PORT_PIN7_PORT10_Msk (0x01UL << GPIO_PORT_PIN7_PORT10_Pos) /*!< GPIO_PORT PIN7: PORT10 Mask */
+#define GPIO_PORT_PIN7_PORT11_Pos 11 /*!< GPIO_PORT PIN7: PORT11 Position */
+#define GPIO_PORT_PIN7_PORT11_Msk (0x01UL << GPIO_PORT_PIN7_PORT11_Pos) /*!< GPIO_PORT PIN7: PORT11 Mask */
+#define GPIO_PORT_PIN7_PORT12_Pos 12 /*!< GPIO_PORT PIN7: PORT12 Position */
+#define GPIO_PORT_PIN7_PORT12_Msk (0x01UL << GPIO_PORT_PIN7_PORT12_Pos) /*!< GPIO_PORT PIN7: PORT12 Mask */
+#define GPIO_PORT_PIN7_PORT13_Pos 13 /*!< GPIO_PORT PIN7: PORT13 Position */
+#define GPIO_PORT_PIN7_PORT13_Msk (0x01UL << GPIO_PORT_PIN7_PORT13_Pos) /*!< GPIO_PORT PIN7: PORT13 Mask */
+#define GPIO_PORT_PIN7_PORT14_Pos 14 /*!< GPIO_PORT PIN7: PORT14 Position */
+#define GPIO_PORT_PIN7_PORT14_Msk (0x01UL << GPIO_PORT_PIN7_PORT14_Pos) /*!< GPIO_PORT PIN7: PORT14 Mask */
+#define GPIO_PORT_PIN7_PORT15_Pos 15 /*!< GPIO_PORT PIN7: PORT15 Position */
+#define GPIO_PORT_PIN7_PORT15_Msk (0x01UL << GPIO_PORT_PIN7_PORT15_Pos) /*!< GPIO_PORT PIN7: PORT15 Mask */
+#define GPIO_PORT_PIN7_PORT16_Pos 16 /*!< GPIO_PORT PIN7: PORT16 Position */
+#define GPIO_PORT_PIN7_PORT16_Msk (0x01UL << GPIO_PORT_PIN7_PORT16_Pos) /*!< GPIO_PORT PIN7: PORT16 Mask */
+#define GPIO_PORT_PIN7_PORT17_Pos 17 /*!< GPIO_PORT PIN7: PORT17 Position */
+#define GPIO_PORT_PIN7_PORT17_Msk (0x01UL << GPIO_PORT_PIN7_PORT17_Pos) /*!< GPIO_PORT PIN7: PORT17 Mask */
+#define GPIO_PORT_PIN7_PORT18_Pos 18 /*!< GPIO_PORT PIN7: PORT18 Position */
+#define GPIO_PORT_PIN7_PORT18_Msk (0x01UL << GPIO_PORT_PIN7_PORT18_Pos) /*!< GPIO_PORT PIN7: PORT18 Mask */
+#define GPIO_PORT_PIN7_PORT19_Pos 19 /*!< GPIO_PORT PIN7: PORT19 Position */
+#define GPIO_PORT_PIN7_PORT19_Msk (0x01UL << GPIO_PORT_PIN7_PORT19_Pos) /*!< GPIO_PORT PIN7: PORT19 Mask */
+#define GPIO_PORT_PIN7_PORT20_Pos 20 /*!< GPIO_PORT PIN7: PORT20 Position */
+#define GPIO_PORT_PIN7_PORT20_Msk (0x01UL << GPIO_PORT_PIN7_PORT20_Pos) /*!< GPIO_PORT PIN7: PORT20 Mask */
+#define GPIO_PORT_PIN7_PORT21_Pos 21 /*!< GPIO_PORT PIN7: PORT21 Position */
+#define GPIO_PORT_PIN7_PORT21_Msk (0x01UL << GPIO_PORT_PIN7_PORT21_Pos) /*!< GPIO_PORT PIN7: PORT21 Mask */
+#define GPIO_PORT_PIN7_PORT22_Pos 22 /*!< GPIO_PORT PIN7: PORT22 Position */
+#define GPIO_PORT_PIN7_PORT22_Msk (0x01UL << GPIO_PORT_PIN7_PORT22_Pos) /*!< GPIO_PORT PIN7: PORT22 Mask */
+#define GPIO_PORT_PIN7_PORT23_Pos 23 /*!< GPIO_PORT PIN7: PORT23 Position */
+#define GPIO_PORT_PIN7_PORT23_Msk (0x01UL << GPIO_PORT_PIN7_PORT23_Pos) /*!< GPIO_PORT PIN7: PORT23 Mask */
+#define GPIO_PORT_PIN7_PORT24_Pos 24 /*!< GPIO_PORT PIN7: PORT24 Position */
+#define GPIO_PORT_PIN7_PORT24_Msk (0x01UL << GPIO_PORT_PIN7_PORT24_Pos) /*!< GPIO_PORT PIN7: PORT24 Mask */
+#define GPIO_PORT_PIN7_PORT25_Pos 25 /*!< GPIO_PORT PIN7: PORT25 Position */
+#define GPIO_PORT_PIN7_PORT25_Msk (0x01UL << GPIO_PORT_PIN7_PORT25_Pos) /*!< GPIO_PORT PIN7: PORT25 Mask */
+#define GPIO_PORT_PIN7_PORT26_Pos 26 /*!< GPIO_PORT PIN7: PORT26 Position */
+#define GPIO_PORT_PIN7_PORT26_Msk (0x01UL << GPIO_PORT_PIN7_PORT26_Pos) /*!< GPIO_PORT PIN7: PORT26 Mask */
+#define GPIO_PORT_PIN7_PORT27_Pos 27 /*!< GPIO_PORT PIN7: PORT27 Position */
+#define GPIO_PORT_PIN7_PORT27_Msk (0x01UL << GPIO_PORT_PIN7_PORT27_Pos) /*!< GPIO_PORT PIN7: PORT27 Mask */
+#define GPIO_PORT_PIN7_PORT28_Pos 28 /*!< GPIO_PORT PIN7: PORT28 Position */
+#define GPIO_PORT_PIN7_PORT28_Msk (0x01UL << GPIO_PORT_PIN7_PORT28_Pos) /*!< GPIO_PORT PIN7: PORT28 Mask */
+#define GPIO_PORT_PIN7_PORT29_Pos 29 /*!< GPIO_PORT PIN7: PORT29 Position */
+#define GPIO_PORT_PIN7_PORT29_Msk (0x01UL << GPIO_PORT_PIN7_PORT29_Pos) /*!< GPIO_PORT PIN7: PORT29 Mask */
+#define GPIO_PORT_PIN7_PORT30_Pos 30 /*!< GPIO_PORT PIN7: PORT30 Position */
+#define GPIO_PORT_PIN7_PORT30_Msk (0x01UL << GPIO_PORT_PIN7_PORT30_Pos) /*!< GPIO_PORT PIN7: PORT30 Mask */
+#define GPIO_PORT_PIN7_PORT31_Pos 31 /*!< GPIO_PORT PIN7: PORT31 Position */
+#define GPIO_PORT_PIN7_PORT31_Msk (0x01UL << GPIO_PORT_PIN7_PORT31_Pos) /*!< GPIO_PORT PIN7: PORT31 Mask */
+
+// ------------------------------------- GPIO_PORT_MPIN0 ----------------------------------------
+#define GPIO_PORT_MPIN0_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN0: MPORTP0 Position */
+#define GPIO_PORT_MPIN0_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP0_Pos) /*!< GPIO_PORT MPIN0: MPORTP0 Mask */
+#define GPIO_PORT_MPIN0_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN0: MPORTP1 Position */
+#define GPIO_PORT_MPIN0_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP1_Pos) /*!< GPIO_PORT MPIN0: MPORTP1 Mask */
+#define GPIO_PORT_MPIN0_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN0: MPORTP2 Position */
+#define GPIO_PORT_MPIN0_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP2_Pos) /*!< GPIO_PORT MPIN0: MPORTP2 Mask */
+#define GPIO_PORT_MPIN0_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN0: MPORTP3 Position */
+#define GPIO_PORT_MPIN0_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP3_Pos) /*!< GPIO_PORT MPIN0: MPORTP3 Mask */
+#define GPIO_PORT_MPIN0_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN0: MPORTP4 Position */
+#define GPIO_PORT_MPIN0_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP4_Pos) /*!< GPIO_PORT MPIN0: MPORTP4 Mask */
+#define GPIO_PORT_MPIN0_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN0: MPORTP5 Position */
+#define GPIO_PORT_MPIN0_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP5_Pos) /*!< GPIO_PORT MPIN0: MPORTP5 Mask */
+#define GPIO_PORT_MPIN0_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN0: MPORTP6 Position */
+#define GPIO_PORT_MPIN0_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP6_Pos) /*!< GPIO_PORT MPIN0: MPORTP6 Mask */
+#define GPIO_PORT_MPIN0_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN0: MPORTP7 Position */
+#define GPIO_PORT_MPIN0_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP7_Pos) /*!< GPIO_PORT MPIN0: MPORTP7 Mask */
+#define GPIO_PORT_MPIN0_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN0: MPORTP8 Position */
+#define GPIO_PORT_MPIN0_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP8_Pos) /*!< GPIO_PORT MPIN0: MPORTP8 Mask */
+#define GPIO_PORT_MPIN0_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN0: MPORTP9 Position */
+#define GPIO_PORT_MPIN0_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP9_Pos) /*!< GPIO_PORT MPIN0: MPORTP9 Mask */
+#define GPIO_PORT_MPIN0_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN0: MPORTP10 Position */
+#define GPIO_PORT_MPIN0_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP10_Pos) /*!< GPIO_PORT MPIN0: MPORTP10 Mask */
+#define GPIO_PORT_MPIN0_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN0: MPORTP11 Position */
+#define GPIO_PORT_MPIN0_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP11_Pos) /*!< GPIO_PORT MPIN0: MPORTP11 Mask */
+#define GPIO_PORT_MPIN0_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN0: MPORTP12 Position */
+#define GPIO_PORT_MPIN0_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP12_Pos) /*!< GPIO_PORT MPIN0: MPORTP12 Mask */
+#define GPIO_PORT_MPIN0_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN0: MPORTP13 Position */
+#define GPIO_PORT_MPIN0_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP13_Pos) /*!< GPIO_PORT MPIN0: MPORTP13 Mask */
+#define GPIO_PORT_MPIN0_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN0: MPORTP14 Position */
+#define GPIO_PORT_MPIN0_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP14_Pos) /*!< GPIO_PORT MPIN0: MPORTP14 Mask */
+#define GPIO_PORT_MPIN0_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN0: MPORTP15 Position */
+#define GPIO_PORT_MPIN0_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP15_Pos) /*!< GPIO_PORT MPIN0: MPORTP15 Mask */
+#define GPIO_PORT_MPIN0_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN0: MPORTP16 Position */
+#define GPIO_PORT_MPIN0_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP16_Pos) /*!< GPIO_PORT MPIN0: MPORTP16 Mask */
+#define GPIO_PORT_MPIN0_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN0: MPORTP17 Position */
+#define GPIO_PORT_MPIN0_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP17_Pos) /*!< GPIO_PORT MPIN0: MPORTP17 Mask */
+#define GPIO_PORT_MPIN0_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN0: MPORTP18 Position */
+#define GPIO_PORT_MPIN0_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP18_Pos) /*!< GPIO_PORT MPIN0: MPORTP18 Mask */
+#define GPIO_PORT_MPIN0_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN0: MPORTP19 Position */
+#define GPIO_PORT_MPIN0_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP19_Pos) /*!< GPIO_PORT MPIN0: MPORTP19 Mask */
+#define GPIO_PORT_MPIN0_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN0: MPORTP20 Position */
+#define GPIO_PORT_MPIN0_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP20_Pos) /*!< GPIO_PORT MPIN0: MPORTP20 Mask */
+#define GPIO_PORT_MPIN0_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN0: MPORTP21 Position */
+#define GPIO_PORT_MPIN0_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP21_Pos) /*!< GPIO_PORT MPIN0: MPORTP21 Mask */
+#define GPIO_PORT_MPIN0_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN0: MPORTP22 Position */
+#define GPIO_PORT_MPIN0_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP22_Pos) /*!< GPIO_PORT MPIN0: MPORTP22 Mask */
+#define GPIO_PORT_MPIN0_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN0: MPORTP23 Position */
+#define GPIO_PORT_MPIN0_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP23_Pos) /*!< GPIO_PORT MPIN0: MPORTP23 Mask */
+#define GPIO_PORT_MPIN0_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN0: MPORTP24 Position */
+#define GPIO_PORT_MPIN0_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP24_Pos) /*!< GPIO_PORT MPIN0: MPORTP24 Mask */
+#define GPIO_PORT_MPIN0_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN0: MPORTP25 Position */
+#define GPIO_PORT_MPIN0_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP25_Pos) /*!< GPIO_PORT MPIN0: MPORTP25 Mask */
+#define GPIO_PORT_MPIN0_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN0: MPORTP26 Position */
+#define GPIO_PORT_MPIN0_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP26_Pos) /*!< GPIO_PORT MPIN0: MPORTP26 Mask */
+#define GPIO_PORT_MPIN0_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN0: MPORTP27 Position */
+#define GPIO_PORT_MPIN0_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP27_Pos) /*!< GPIO_PORT MPIN0: MPORTP27 Mask */
+#define GPIO_PORT_MPIN0_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN0: MPORTP28 Position */
+#define GPIO_PORT_MPIN0_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP28_Pos) /*!< GPIO_PORT MPIN0: MPORTP28 Mask */
+#define GPIO_PORT_MPIN0_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN0: MPORTP29 Position */
+#define GPIO_PORT_MPIN0_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP29_Pos) /*!< GPIO_PORT MPIN0: MPORTP29 Mask */
+#define GPIO_PORT_MPIN0_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN0: MPORTP30 Position */
+#define GPIO_PORT_MPIN0_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP30_Pos) /*!< GPIO_PORT MPIN0: MPORTP30 Mask */
+#define GPIO_PORT_MPIN0_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN0: MPORTP31 Position */
+#define GPIO_PORT_MPIN0_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP31_Pos) /*!< GPIO_PORT MPIN0: MPORTP31 Mask */
+
+// ------------------------------------- GPIO_PORT_MPIN1 ----------------------------------------
+#define GPIO_PORT_MPIN1_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN1: MPORTP0 Position */
+#define GPIO_PORT_MPIN1_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP0_Pos) /*!< GPIO_PORT MPIN1: MPORTP0 Mask */
+#define GPIO_PORT_MPIN1_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN1: MPORTP1 Position */
+#define GPIO_PORT_MPIN1_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP1_Pos) /*!< GPIO_PORT MPIN1: MPORTP1 Mask */
+#define GPIO_PORT_MPIN1_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN1: MPORTP2 Position */
+#define GPIO_PORT_MPIN1_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP2_Pos) /*!< GPIO_PORT MPIN1: MPORTP2 Mask */
+#define GPIO_PORT_MPIN1_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN1: MPORTP3 Position */
+#define GPIO_PORT_MPIN1_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP3_Pos) /*!< GPIO_PORT MPIN1: MPORTP3 Mask */
+#define GPIO_PORT_MPIN1_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN1: MPORTP4 Position */
+#define GPIO_PORT_MPIN1_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP4_Pos) /*!< GPIO_PORT MPIN1: MPORTP4 Mask */
+#define GPIO_PORT_MPIN1_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN1: MPORTP5 Position */
+#define GPIO_PORT_MPIN1_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP5_Pos) /*!< GPIO_PORT MPIN1: MPORTP5 Mask */
+#define GPIO_PORT_MPIN1_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN1: MPORTP6 Position */
+#define GPIO_PORT_MPIN1_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP6_Pos) /*!< GPIO_PORT MPIN1: MPORTP6 Mask */
+#define GPIO_PORT_MPIN1_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN1: MPORTP7 Position */
+#define GPIO_PORT_MPIN1_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP7_Pos) /*!< GPIO_PORT MPIN1: MPORTP7 Mask */
+#define GPIO_PORT_MPIN1_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN1: MPORTP8 Position */
+#define GPIO_PORT_MPIN1_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP8_Pos) /*!< GPIO_PORT MPIN1: MPORTP8 Mask */
+#define GPIO_PORT_MPIN1_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN1: MPORTP9 Position */
+#define GPIO_PORT_MPIN1_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP9_Pos) /*!< GPIO_PORT MPIN1: MPORTP9 Mask */
+#define GPIO_PORT_MPIN1_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN1: MPORTP10 Position */
+#define GPIO_PORT_MPIN1_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP10_Pos) /*!< GPIO_PORT MPIN1: MPORTP10 Mask */
+#define GPIO_PORT_MPIN1_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN1: MPORTP11 Position */
+#define GPIO_PORT_MPIN1_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP11_Pos) /*!< GPIO_PORT MPIN1: MPORTP11 Mask */
+#define GPIO_PORT_MPIN1_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN1: MPORTP12 Position */
+#define GPIO_PORT_MPIN1_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP12_Pos) /*!< GPIO_PORT MPIN1: MPORTP12 Mask */
+#define GPIO_PORT_MPIN1_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN1: MPORTP13 Position */
+#define GPIO_PORT_MPIN1_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP13_Pos) /*!< GPIO_PORT MPIN1: MPORTP13 Mask */
+#define GPIO_PORT_MPIN1_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN1: MPORTP14 Position */
+#define GPIO_PORT_MPIN1_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP14_Pos) /*!< GPIO_PORT MPIN1: MPORTP14 Mask */
+#define GPIO_PORT_MPIN1_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN1: MPORTP15 Position */
+#define GPIO_PORT_MPIN1_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP15_Pos) /*!< GPIO_PORT MPIN1: MPORTP15 Mask */
+#define GPIO_PORT_MPIN1_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN1: MPORTP16 Position */
+#define GPIO_PORT_MPIN1_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP16_Pos) /*!< GPIO_PORT MPIN1: MPORTP16 Mask */
+#define GPIO_PORT_MPIN1_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN1: MPORTP17 Position */
+#define GPIO_PORT_MPIN1_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP17_Pos) /*!< GPIO_PORT MPIN1: MPORTP17 Mask */
+#define GPIO_PORT_MPIN1_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN1: MPORTP18 Position */
+#define GPIO_PORT_MPIN1_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP18_Pos) /*!< GPIO_PORT MPIN1: MPORTP18 Mask */
+#define GPIO_PORT_MPIN1_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN1: MPORTP19 Position */
+#define GPIO_PORT_MPIN1_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP19_Pos) /*!< GPIO_PORT MPIN1: MPORTP19 Mask */
+#define GPIO_PORT_MPIN1_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN1: MPORTP20 Position */
+#define GPIO_PORT_MPIN1_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP20_Pos) /*!< GPIO_PORT MPIN1: MPORTP20 Mask */
+#define GPIO_PORT_MPIN1_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN1: MPORTP21 Position */
+#define GPIO_PORT_MPIN1_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP21_Pos) /*!< GPIO_PORT MPIN1: MPORTP21 Mask */
+#define GPIO_PORT_MPIN1_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN1: MPORTP22 Position */
+#define GPIO_PORT_MPIN1_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP22_Pos) /*!< GPIO_PORT MPIN1: MPORTP22 Mask */
+#define GPIO_PORT_MPIN1_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN1: MPORTP23 Position */
+#define GPIO_PORT_MPIN1_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP23_Pos) /*!< GPIO_PORT MPIN1: MPORTP23 Mask */
+#define GPIO_PORT_MPIN1_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN1: MPORTP24 Position */
+#define GPIO_PORT_MPIN1_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP24_Pos) /*!< GPIO_PORT MPIN1: MPORTP24 Mask */
+#define GPIO_PORT_MPIN1_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN1: MPORTP25 Position */
+#define GPIO_PORT_MPIN1_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP25_Pos) /*!< GPIO_PORT MPIN1: MPORTP25 Mask */
+#define GPIO_PORT_MPIN1_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN1: MPORTP26 Position */
+#define GPIO_PORT_MPIN1_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP26_Pos) /*!< GPIO_PORT MPIN1: MPORTP26 Mask */
+#define GPIO_PORT_MPIN1_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN1: MPORTP27 Position */
+#define GPIO_PORT_MPIN1_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP27_Pos) /*!< GPIO_PORT MPIN1: MPORTP27 Mask */
+#define GPIO_PORT_MPIN1_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN1: MPORTP28 Position */
+#define GPIO_PORT_MPIN1_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP28_Pos) /*!< GPIO_PORT MPIN1: MPORTP28 Mask */
+#define GPIO_PORT_MPIN1_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN1: MPORTP29 Position */
+#define GPIO_PORT_MPIN1_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP29_Pos) /*!< GPIO_PORT MPIN1: MPORTP29 Mask */
+#define GPIO_PORT_MPIN1_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN1: MPORTP30 Position */
+#define GPIO_PORT_MPIN1_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP30_Pos) /*!< GPIO_PORT MPIN1: MPORTP30 Mask */
+#define GPIO_PORT_MPIN1_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN1: MPORTP31 Position */
+#define GPIO_PORT_MPIN1_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP31_Pos) /*!< GPIO_PORT MPIN1: MPORTP31 Mask */
+
+// ------------------------------------- GPIO_PORT_MPIN2 ----------------------------------------
+#define GPIO_PORT_MPIN2_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN2: MPORTP0 Position */
+#define GPIO_PORT_MPIN2_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP0_Pos) /*!< GPIO_PORT MPIN2: MPORTP0 Mask */
+#define GPIO_PORT_MPIN2_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN2: MPORTP1 Position */
+#define GPIO_PORT_MPIN2_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP1_Pos) /*!< GPIO_PORT MPIN2: MPORTP1 Mask */
+#define GPIO_PORT_MPIN2_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN2: MPORTP2 Position */
+#define GPIO_PORT_MPIN2_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP2_Pos) /*!< GPIO_PORT MPIN2: MPORTP2 Mask */
+#define GPIO_PORT_MPIN2_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN2: MPORTP3 Position */
+#define GPIO_PORT_MPIN2_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP3_Pos) /*!< GPIO_PORT MPIN2: MPORTP3 Mask */
+#define GPIO_PORT_MPIN2_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN2: MPORTP4 Position */
+#define GPIO_PORT_MPIN2_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP4_Pos) /*!< GPIO_PORT MPIN2: MPORTP4 Mask */
+#define GPIO_PORT_MPIN2_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN2: MPORTP5 Position */
+#define GPIO_PORT_MPIN2_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP5_Pos) /*!< GPIO_PORT MPIN2: MPORTP5 Mask */
+#define GPIO_PORT_MPIN2_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN2: MPORTP6 Position */
+#define GPIO_PORT_MPIN2_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP6_Pos) /*!< GPIO_PORT MPIN2: MPORTP6 Mask */
+#define GPIO_PORT_MPIN2_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN2: MPORTP7 Position */
+#define GPIO_PORT_MPIN2_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP7_Pos) /*!< GPIO_PORT MPIN2: MPORTP7 Mask */
+#define GPIO_PORT_MPIN2_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN2: MPORTP8 Position */
+#define GPIO_PORT_MPIN2_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP8_Pos) /*!< GPIO_PORT MPIN2: MPORTP8 Mask */
+#define GPIO_PORT_MPIN2_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN2: MPORTP9 Position */
+#define GPIO_PORT_MPIN2_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP9_Pos) /*!< GPIO_PORT MPIN2: MPORTP9 Mask */
+#define GPIO_PORT_MPIN2_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN2: MPORTP10 Position */
+#define GPIO_PORT_MPIN2_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP10_Pos) /*!< GPIO_PORT MPIN2: MPORTP10 Mask */
+#define GPIO_PORT_MPIN2_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN2: MPORTP11 Position */
+#define GPIO_PORT_MPIN2_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP11_Pos) /*!< GPIO_PORT MPIN2: MPORTP11 Mask */
+#define GPIO_PORT_MPIN2_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN2: MPORTP12 Position */
+#define GPIO_PORT_MPIN2_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP12_Pos) /*!< GPIO_PORT MPIN2: MPORTP12 Mask */
+#define GPIO_PORT_MPIN2_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN2: MPORTP13 Position */
+#define GPIO_PORT_MPIN2_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP13_Pos) /*!< GPIO_PORT MPIN2: MPORTP13 Mask */
+#define GPIO_PORT_MPIN2_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN2: MPORTP14 Position */
+#define GPIO_PORT_MPIN2_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP14_Pos) /*!< GPIO_PORT MPIN2: MPORTP14 Mask */
+#define GPIO_PORT_MPIN2_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN2: MPORTP15 Position */
+#define GPIO_PORT_MPIN2_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP15_Pos) /*!< GPIO_PORT MPIN2: MPORTP15 Mask */
+#define GPIO_PORT_MPIN2_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN2: MPORTP16 Position */
+#define GPIO_PORT_MPIN2_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP16_Pos) /*!< GPIO_PORT MPIN2: MPORTP16 Mask */
+#define GPIO_PORT_MPIN2_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN2: MPORTP17 Position */
+#define GPIO_PORT_MPIN2_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP17_Pos) /*!< GPIO_PORT MPIN2: MPORTP17 Mask */
+#define GPIO_PORT_MPIN2_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN2: MPORTP18 Position */
+#define GPIO_PORT_MPIN2_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP18_Pos) /*!< GPIO_PORT MPIN2: MPORTP18 Mask */
+#define GPIO_PORT_MPIN2_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN2: MPORTP19 Position */
+#define GPIO_PORT_MPIN2_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP19_Pos) /*!< GPIO_PORT MPIN2: MPORTP19 Mask */
+#define GPIO_PORT_MPIN2_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN2: MPORTP20 Position */
+#define GPIO_PORT_MPIN2_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP20_Pos) /*!< GPIO_PORT MPIN2: MPORTP20 Mask */
+#define GPIO_PORT_MPIN2_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN2: MPORTP21 Position */
+#define GPIO_PORT_MPIN2_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP21_Pos) /*!< GPIO_PORT MPIN2: MPORTP21 Mask */
+#define GPIO_PORT_MPIN2_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN2: MPORTP22 Position */
+#define GPIO_PORT_MPIN2_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP22_Pos) /*!< GPIO_PORT MPIN2: MPORTP22 Mask */
+#define GPIO_PORT_MPIN2_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN2: MPORTP23 Position */
+#define GPIO_PORT_MPIN2_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP23_Pos) /*!< GPIO_PORT MPIN2: MPORTP23 Mask */
+#define GPIO_PORT_MPIN2_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN2: MPORTP24 Position */
+#define GPIO_PORT_MPIN2_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP24_Pos) /*!< GPIO_PORT MPIN2: MPORTP24 Mask */
+#define GPIO_PORT_MPIN2_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN2: MPORTP25 Position */
+#define GPIO_PORT_MPIN2_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP25_Pos) /*!< GPIO_PORT MPIN2: MPORTP25 Mask */
+#define GPIO_PORT_MPIN2_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN2: MPORTP26 Position */
+#define GPIO_PORT_MPIN2_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP26_Pos) /*!< GPIO_PORT MPIN2: MPORTP26 Mask */
+#define GPIO_PORT_MPIN2_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN2: MPORTP27 Position */
+#define GPIO_PORT_MPIN2_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP27_Pos) /*!< GPIO_PORT MPIN2: MPORTP27 Mask */
+#define GPIO_PORT_MPIN2_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN2: MPORTP28 Position */
+#define GPIO_PORT_MPIN2_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP28_Pos) /*!< GPIO_PORT MPIN2: MPORTP28 Mask */
+#define GPIO_PORT_MPIN2_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN2: MPORTP29 Position */
+#define GPIO_PORT_MPIN2_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP29_Pos) /*!< GPIO_PORT MPIN2: MPORTP29 Mask */
+#define GPIO_PORT_MPIN2_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN2: MPORTP30 Position */
+#define GPIO_PORT_MPIN2_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP30_Pos) /*!< GPIO_PORT MPIN2: MPORTP30 Mask */
+#define GPIO_PORT_MPIN2_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN2: MPORTP31 Position */
+#define GPIO_PORT_MPIN2_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP31_Pos) /*!< GPIO_PORT MPIN2: MPORTP31 Mask */
+
+// ------------------------------------- GPIO_PORT_MPIN3 ----------------------------------------
+#define GPIO_PORT_MPIN3_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN3: MPORTP0 Position */
+#define GPIO_PORT_MPIN3_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP0_Pos) /*!< GPIO_PORT MPIN3: MPORTP0 Mask */
+#define GPIO_PORT_MPIN3_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN3: MPORTP1 Position */
+#define GPIO_PORT_MPIN3_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP1_Pos) /*!< GPIO_PORT MPIN3: MPORTP1 Mask */
+#define GPIO_PORT_MPIN3_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN3: MPORTP2 Position */
+#define GPIO_PORT_MPIN3_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP2_Pos) /*!< GPIO_PORT MPIN3: MPORTP2 Mask */
+#define GPIO_PORT_MPIN3_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN3: MPORTP3 Position */
+#define GPIO_PORT_MPIN3_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP3_Pos) /*!< GPIO_PORT MPIN3: MPORTP3 Mask */
+#define GPIO_PORT_MPIN3_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN3: MPORTP4 Position */
+#define GPIO_PORT_MPIN3_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP4_Pos) /*!< GPIO_PORT MPIN3: MPORTP4 Mask */
+#define GPIO_PORT_MPIN3_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN3: MPORTP5 Position */
+#define GPIO_PORT_MPIN3_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP5_Pos) /*!< GPIO_PORT MPIN3: MPORTP5 Mask */
+#define GPIO_PORT_MPIN3_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN3: MPORTP6 Position */
+#define GPIO_PORT_MPIN3_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP6_Pos) /*!< GPIO_PORT MPIN3: MPORTP6 Mask */
+#define GPIO_PORT_MPIN3_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN3: MPORTP7 Position */
+#define GPIO_PORT_MPIN3_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP7_Pos) /*!< GPIO_PORT MPIN3: MPORTP7 Mask */
+#define GPIO_PORT_MPIN3_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN3: MPORTP8 Position */
+#define GPIO_PORT_MPIN3_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP8_Pos) /*!< GPIO_PORT MPIN3: MPORTP8 Mask */
+#define GPIO_PORT_MPIN3_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN3: MPORTP9 Position */
+#define GPIO_PORT_MPIN3_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP9_Pos) /*!< GPIO_PORT MPIN3: MPORTP9 Mask */
+#define GPIO_PORT_MPIN3_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN3: MPORTP10 Position */
+#define GPIO_PORT_MPIN3_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP10_Pos) /*!< GPIO_PORT MPIN3: MPORTP10 Mask */
+#define GPIO_PORT_MPIN3_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN3: MPORTP11 Position */
+#define GPIO_PORT_MPIN3_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP11_Pos) /*!< GPIO_PORT MPIN3: MPORTP11 Mask */
+#define GPIO_PORT_MPIN3_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN3: MPORTP12 Position */
+#define GPIO_PORT_MPIN3_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP12_Pos) /*!< GPIO_PORT MPIN3: MPORTP12 Mask */
+#define GPIO_PORT_MPIN3_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN3: MPORTP13 Position */
+#define GPIO_PORT_MPIN3_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP13_Pos) /*!< GPIO_PORT MPIN3: MPORTP13 Mask */
+#define GPIO_PORT_MPIN3_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN3: MPORTP14 Position */
+#define GPIO_PORT_MPIN3_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP14_Pos) /*!< GPIO_PORT MPIN3: MPORTP14 Mask */
+#define GPIO_PORT_MPIN3_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN3: MPORTP15 Position */
+#define GPIO_PORT_MPIN3_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP15_Pos) /*!< GPIO_PORT MPIN3: MPORTP15 Mask */
+#define GPIO_PORT_MPIN3_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN3: MPORTP16 Position */
+#define GPIO_PORT_MPIN3_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP16_Pos) /*!< GPIO_PORT MPIN3: MPORTP16 Mask */
+#define GPIO_PORT_MPIN3_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN3: MPORTP17 Position */
+#define GPIO_PORT_MPIN3_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP17_Pos) /*!< GPIO_PORT MPIN3: MPORTP17 Mask */
+#define GPIO_PORT_MPIN3_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN3: MPORTP18 Position */
+#define GPIO_PORT_MPIN3_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP18_Pos) /*!< GPIO_PORT MPIN3: MPORTP18 Mask */
+#define GPIO_PORT_MPIN3_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN3: MPORTP19 Position */
+#define GPIO_PORT_MPIN3_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP19_Pos) /*!< GPIO_PORT MPIN3: MPORTP19 Mask */
+#define GPIO_PORT_MPIN3_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN3: MPORTP20 Position */
+#define GPIO_PORT_MPIN3_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP20_Pos) /*!< GPIO_PORT MPIN3: MPORTP20 Mask */
+#define GPIO_PORT_MPIN3_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN3: MPORTP21 Position */
+#define GPIO_PORT_MPIN3_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP21_Pos) /*!< GPIO_PORT MPIN3: MPORTP21 Mask */
+#define GPIO_PORT_MPIN3_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN3: MPORTP22 Position */
+#define GPIO_PORT_MPIN3_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP22_Pos) /*!< GPIO_PORT MPIN3: MPORTP22 Mask */
+#define GPIO_PORT_MPIN3_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN3: MPORTP23 Position */
+#define GPIO_PORT_MPIN3_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP23_Pos) /*!< GPIO_PORT MPIN3: MPORTP23 Mask */
+#define GPIO_PORT_MPIN3_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN3: MPORTP24 Position */
+#define GPIO_PORT_MPIN3_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP24_Pos) /*!< GPIO_PORT MPIN3: MPORTP24 Mask */
+#define GPIO_PORT_MPIN3_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN3: MPORTP25 Position */
+#define GPIO_PORT_MPIN3_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP25_Pos) /*!< GPIO_PORT MPIN3: MPORTP25 Mask */
+#define GPIO_PORT_MPIN3_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN3: MPORTP26 Position */
+#define GPIO_PORT_MPIN3_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP26_Pos) /*!< GPIO_PORT MPIN3: MPORTP26 Mask */
+#define GPIO_PORT_MPIN3_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN3: MPORTP27 Position */
+#define GPIO_PORT_MPIN3_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP27_Pos) /*!< GPIO_PORT MPIN3: MPORTP27 Mask */
+#define GPIO_PORT_MPIN3_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN3: MPORTP28 Position */
+#define GPIO_PORT_MPIN3_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP28_Pos) /*!< GPIO_PORT MPIN3: MPORTP28 Mask */
+#define GPIO_PORT_MPIN3_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN3: MPORTP29 Position */
+#define GPIO_PORT_MPIN3_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP29_Pos) /*!< GPIO_PORT MPIN3: MPORTP29 Mask */
+#define GPIO_PORT_MPIN3_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN3: MPORTP30 Position */
+#define GPIO_PORT_MPIN3_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP30_Pos) /*!< GPIO_PORT MPIN3: MPORTP30 Mask */
+#define GPIO_PORT_MPIN3_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN3: MPORTP31 Position */
+#define GPIO_PORT_MPIN3_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP31_Pos) /*!< GPIO_PORT MPIN3: MPORTP31 Mask */
+
+// ------------------------------------- GPIO_PORT_MPIN4 ----------------------------------------
+#define GPIO_PORT_MPIN4_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN4: MPORTP0 Position */
+#define GPIO_PORT_MPIN4_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP0_Pos) /*!< GPIO_PORT MPIN4: MPORTP0 Mask */
+#define GPIO_PORT_MPIN4_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN4: MPORTP1 Position */
+#define GPIO_PORT_MPIN4_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP1_Pos) /*!< GPIO_PORT MPIN4: MPORTP1 Mask */
+#define GPIO_PORT_MPIN4_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN4: MPORTP2 Position */
+#define GPIO_PORT_MPIN4_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP2_Pos) /*!< GPIO_PORT MPIN4: MPORTP2 Mask */
+#define GPIO_PORT_MPIN4_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN4: MPORTP3 Position */
+#define GPIO_PORT_MPIN4_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP3_Pos) /*!< GPIO_PORT MPIN4: MPORTP3 Mask */
+#define GPIO_PORT_MPIN4_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN4: MPORTP4 Position */
+#define GPIO_PORT_MPIN4_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP4_Pos) /*!< GPIO_PORT MPIN4: MPORTP4 Mask */
+#define GPIO_PORT_MPIN4_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN4: MPORTP5 Position */
+#define GPIO_PORT_MPIN4_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP5_Pos) /*!< GPIO_PORT MPIN4: MPORTP5 Mask */
+#define GPIO_PORT_MPIN4_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN4: MPORTP6 Position */
+#define GPIO_PORT_MPIN4_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP6_Pos) /*!< GPIO_PORT MPIN4: MPORTP6 Mask */
+#define GPIO_PORT_MPIN4_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN4: MPORTP7 Position */
+#define GPIO_PORT_MPIN4_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP7_Pos) /*!< GPIO_PORT MPIN4: MPORTP7 Mask */
+#define GPIO_PORT_MPIN4_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN4: MPORTP8 Position */
+#define GPIO_PORT_MPIN4_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP8_Pos) /*!< GPIO_PORT MPIN4: MPORTP8 Mask */
+#define GPIO_PORT_MPIN4_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN4: MPORTP9 Position */
+#define GPIO_PORT_MPIN4_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP9_Pos) /*!< GPIO_PORT MPIN4: MPORTP9 Mask */
+#define GPIO_PORT_MPIN4_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN4: MPORTP10 Position */
+#define GPIO_PORT_MPIN4_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP10_Pos) /*!< GPIO_PORT MPIN4: MPORTP10 Mask */
+#define GPIO_PORT_MPIN4_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN4: MPORTP11 Position */
+#define GPIO_PORT_MPIN4_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP11_Pos) /*!< GPIO_PORT MPIN4: MPORTP11 Mask */
+#define GPIO_PORT_MPIN4_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN4: MPORTP12 Position */
+#define GPIO_PORT_MPIN4_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP12_Pos) /*!< GPIO_PORT MPIN4: MPORTP12 Mask */
+#define GPIO_PORT_MPIN4_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN4: MPORTP13 Position */
+#define GPIO_PORT_MPIN4_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP13_Pos) /*!< GPIO_PORT MPIN4: MPORTP13 Mask */
+#define GPIO_PORT_MPIN4_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN4: MPORTP14 Position */
+#define GPIO_PORT_MPIN4_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP14_Pos) /*!< GPIO_PORT MPIN4: MPORTP14 Mask */
+#define GPIO_PORT_MPIN4_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN4: MPORTP15 Position */
+#define GPIO_PORT_MPIN4_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP15_Pos) /*!< GPIO_PORT MPIN4: MPORTP15 Mask */
+#define GPIO_PORT_MPIN4_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN4: MPORTP16 Position */
+#define GPIO_PORT_MPIN4_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP16_Pos) /*!< GPIO_PORT MPIN4: MPORTP16 Mask */
+#define GPIO_PORT_MPIN4_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN4: MPORTP17 Position */
+#define GPIO_PORT_MPIN4_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP17_Pos) /*!< GPIO_PORT MPIN4: MPORTP17 Mask */
+#define GPIO_PORT_MPIN4_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN4: MPORTP18 Position */
+#define GPIO_PORT_MPIN4_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP18_Pos) /*!< GPIO_PORT MPIN4: MPORTP18 Mask */
+#define GPIO_PORT_MPIN4_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN4: MPORTP19 Position */
+#define GPIO_PORT_MPIN4_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP19_Pos) /*!< GPIO_PORT MPIN4: MPORTP19 Mask */
+#define GPIO_PORT_MPIN4_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN4: MPORTP20 Position */
+#define GPIO_PORT_MPIN4_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP20_Pos) /*!< GPIO_PORT MPIN4: MPORTP20 Mask */
+#define GPIO_PORT_MPIN4_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN4: MPORTP21 Position */
+#define GPIO_PORT_MPIN4_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP21_Pos) /*!< GPIO_PORT MPIN4: MPORTP21 Mask */
+#define GPIO_PORT_MPIN4_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN4: MPORTP22 Position */
+#define GPIO_PORT_MPIN4_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP22_Pos) /*!< GPIO_PORT MPIN4: MPORTP22 Mask */
+#define GPIO_PORT_MPIN4_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN4: MPORTP23 Position */
+#define GPIO_PORT_MPIN4_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP23_Pos) /*!< GPIO_PORT MPIN4: MPORTP23 Mask */
+#define GPIO_PORT_MPIN4_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN4: MPORTP24 Position */
+#define GPIO_PORT_MPIN4_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP24_Pos) /*!< GPIO_PORT MPIN4: MPORTP24 Mask */
+#define GPIO_PORT_MPIN4_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN4: MPORTP25 Position */
+#define GPIO_PORT_MPIN4_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP25_Pos) /*!< GPIO_PORT MPIN4: MPORTP25 Mask */
+#define GPIO_PORT_MPIN4_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN4: MPORTP26 Position */
+#define GPIO_PORT_MPIN4_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP26_Pos) /*!< GPIO_PORT MPIN4: MPORTP26 Mask */
+#define GPIO_PORT_MPIN4_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN4: MPORTP27 Position */
+#define GPIO_PORT_MPIN4_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP27_Pos) /*!< GPIO_PORT MPIN4: MPORTP27 Mask */
+#define GPIO_PORT_MPIN4_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN4: MPORTP28 Position */
+#define GPIO_PORT_MPIN4_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP28_Pos) /*!< GPIO_PORT MPIN4: MPORTP28 Mask */
+#define GPIO_PORT_MPIN4_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN4: MPORTP29 Position */
+#define GPIO_PORT_MPIN4_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP29_Pos) /*!< GPIO_PORT MPIN4: MPORTP29 Mask */
+#define GPIO_PORT_MPIN4_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN4: MPORTP30 Position */
+#define GPIO_PORT_MPIN4_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP30_Pos) /*!< GPIO_PORT MPIN4: MPORTP30 Mask */
+#define GPIO_PORT_MPIN4_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN4: MPORTP31 Position */
+#define GPIO_PORT_MPIN4_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP31_Pos) /*!< GPIO_PORT MPIN4: MPORTP31 Mask */
+
+// ------------------------------------- GPIO_PORT_MPIN5 ----------------------------------------
+#define GPIO_PORT_MPIN5_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN5: MPORTP0 Position */
+#define GPIO_PORT_MPIN5_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP0_Pos) /*!< GPIO_PORT MPIN5: MPORTP0 Mask */
+#define GPIO_PORT_MPIN5_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN5: MPORTP1 Position */
+#define GPIO_PORT_MPIN5_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP1_Pos) /*!< GPIO_PORT MPIN5: MPORTP1 Mask */
+#define GPIO_PORT_MPIN5_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN5: MPORTP2 Position */
+#define GPIO_PORT_MPIN5_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP2_Pos) /*!< GPIO_PORT MPIN5: MPORTP2 Mask */
+#define GPIO_PORT_MPIN5_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN5: MPORTP3 Position */
+#define GPIO_PORT_MPIN5_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP3_Pos) /*!< GPIO_PORT MPIN5: MPORTP3 Mask */
+#define GPIO_PORT_MPIN5_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN5: MPORTP4 Position */
+#define GPIO_PORT_MPIN5_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP4_Pos) /*!< GPIO_PORT MPIN5: MPORTP4 Mask */
+#define GPIO_PORT_MPIN5_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN5: MPORTP5 Position */
+#define GPIO_PORT_MPIN5_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP5_Pos) /*!< GPIO_PORT MPIN5: MPORTP5 Mask */
+#define GPIO_PORT_MPIN5_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN5: MPORTP6 Position */
+#define GPIO_PORT_MPIN5_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP6_Pos) /*!< GPIO_PORT MPIN5: MPORTP6 Mask */
+#define GPIO_PORT_MPIN5_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN5: MPORTP7 Position */
+#define GPIO_PORT_MPIN5_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP7_Pos) /*!< GPIO_PORT MPIN5: MPORTP7 Mask */
+#define GPIO_PORT_MPIN5_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN5: MPORTP8 Position */
+#define GPIO_PORT_MPIN5_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP8_Pos) /*!< GPIO_PORT MPIN5: MPORTP8 Mask */
+#define GPIO_PORT_MPIN5_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN5: MPORTP9 Position */
+#define GPIO_PORT_MPIN5_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP9_Pos) /*!< GPIO_PORT MPIN5: MPORTP9 Mask */
+#define GPIO_PORT_MPIN5_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN5: MPORTP10 Position */
+#define GPIO_PORT_MPIN5_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP10_Pos) /*!< GPIO_PORT MPIN5: MPORTP10 Mask */
+#define GPIO_PORT_MPIN5_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN5: MPORTP11 Position */
+#define GPIO_PORT_MPIN5_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP11_Pos) /*!< GPIO_PORT MPIN5: MPORTP11 Mask */
+#define GPIO_PORT_MPIN5_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN5: MPORTP12 Position */
+#define GPIO_PORT_MPIN5_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP12_Pos) /*!< GPIO_PORT MPIN5: MPORTP12 Mask */
+#define GPIO_PORT_MPIN5_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN5: MPORTP13 Position */
+#define GPIO_PORT_MPIN5_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP13_Pos) /*!< GPIO_PORT MPIN5: MPORTP13 Mask */
+#define GPIO_PORT_MPIN5_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN5: MPORTP14 Position */
+#define GPIO_PORT_MPIN5_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP14_Pos) /*!< GPIO_PORT MPIN5: MPORTP14 Mask */
+#define GPIO_PORT_MPIN5_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN5: MPORTP15 Position */
+#define GPIO_PORT_MPIN5_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP15_Pos) /*!< GPIO_PORT MPIN5: MPORTP15 Mask */
+#define GPIO_PORT_MPIN5_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN5: MPORTP16 Position */
+#define GPIO_PORT_MPIN5_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP16_Pos) /*!< GPIO_PORT MPIN5: MPORTP16 Mask */
+#define GPIO_PORT_MPIN5_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN5: MPORTP17 Position */
+#define GPIO_PORT_MPIN5_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP17_Pos) /*!< GPIO_PORT MPIN5: MPORTP17 Mask */
+#define GPIO_PORT_MPIN5_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN5: MPORTP18 Position */
+#define GPIO_PORT_MPIN5_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP18_Pos) /*!< GPIO_PORT MPIN5: MPORTP18 Mask */
+#define GPIO_PORT_MPIN5_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN5: MPORTP19 Position */
+#define GPIO_PORT_MPIN5_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP19_Pos) /*!< GPIO_PORT MPIN5: MPORTP19 Mask */
+#define GPIO_PORT_MPIN5_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN5: MPORTP20 Position */
+#define GPIO_PORT_MPIN5_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP20_Pos) /*!< GPIO_PORT MPIN5: MPORTP20 Mask */
+#define GPIO_PORT_MPIN5_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN5: MPORTP21 Position */
+#define GPIO_PORT_MPIN5_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP21_Pos) /*!< GPIO_PORT MPIN5: MPORTP21 Mask */
+#define GPIO_PORT_MPIN5_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN5: MPORTP22 Position */
+#define GPIO_PORT_MPIN5_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP22_Pos) /*!< GPIO_PORT MPIN5: MPORTP22 Mask */
+#define GPIO_PORT_MPIN5_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN5: MPORTP23 Position */
+#define GPIO_PORT_MPIN5_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP23_Pos) /*!< GPIO_PORT MPIN5: MPORTP23 Mask */
+#define GPIO_PORT_MPIN5_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN5: MPORTP24 Position */
+#define GPIO_PORT_MPIN5_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP24_Pos) /*!< GPIO_PORT MPIN5: MPORTP24 Mask */
+#define GPIO_PORT_MPIN5_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN5: MPORTP25 Position */
+#define GPIO_PORT_MPIN5_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP25_Pos) /*!< GPIO_PORT MPIN5: MPORTP25 Mask */
+#define GPIO_PORT_MPIN5_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN5: MPORTP26 Position */
+#define GPIO_PORT_MPIN5_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP26_Pos) /*!< GPIO_PORT MPIN5: MPORTP26 Mask */
+#define GPIO_PORT_MPIN5_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN5: MPORTP27 Position */
+#define GPIO_PORT_MPIN5_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP27_Pos) /*!< GPIO_PORT MPIN5: MPORTP27 Mask */
+#define GPIO_PORT_MPIN5_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN5: MPORTP28 Position */
+#define GPIO_PORT_MPIN5_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP28_Pos) /*!< GPIO_PORT MPIN5: MPORTP28 Mask */
+#define GPIO_PORT_MPIN5_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN5: MPORTP29 Position */
+#define GPIO_PORT_MPIN5_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP29_Pos) /*!< GPIO_PORT MPIN5: MPORTP29 Mask */
+#define GPIO_PORT_MPIN5_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN5: MPORTP30 Position */
+#define GPIO_PORT_MPIN5_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP30_Pos) /*!< GPIO_PORT MPIN5: MPORTP30 Mask */
+#define GPIO_PORT_MPIN5_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN5: MPORTP31 Position */
+#define GPIO_PORT_MPIN5_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP31_Pos) /*!< GPIO_PORT MPIN5: MPORTP31 Mask */
+
+// ------------------------------------- GPIO_PORT_MPIN6 ----------------------------------------
+#define GPIO_PORT_MPIN6_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN6: MPORTP0 Position */
+#define GPIO_PORT_MPIN6_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP0_Pos) /*!< GPIO_PORT MPIN6: MPORTP0 Mask */
+#define GPIO_PORT_MPIN6_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN6: MPORTP1 Position */
+#define GPIO_PORT_MPIN6_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP1_Pos) /*!< GPIO_PORT MPIN6: MPORTP1 Mask */
+#define GPIO_PORT_MPIN6_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN6: MPORTP2 Position */
+#define GPIO_PORT_MPIN6_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP2_Pos) /*!< GPIO_PORT MPIN6: MPORTP2 Mask */
+#define GPIO_PORT_MPIN6_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN6: MPORTP3 Position */
+#define GPIO_PORT_MPIN6_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP3_Pos) /*!< GPIO_PORT MPIN6: MPORTP3 Mask */
+#define GPIO_PORT_MPIN6_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN6: MPORTP4 Position */
+#define GPIO_PORT_MPIN6_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP4_Pos) /*!< GPIO_PORT MPIN6: MPORTP4 Mask */
+#define GPIO_PORT_MPIN6_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN6: MPORTP5 Position */
+#define GPIO_PORT_MPIN6_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP5_Pos) /*!< GPIO_PORT MPIN6: MPORTP5 Mask */
+#define GPIO_PORT_MPIN6_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN6: MPORTP6 Position */
+#define GPIO_PORT_MPIN6_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP6_Pos) /*!< GPIO_PORT MPIN6: MPORTP6 Mask */
+#define GPIO_PORT_MPIN6_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN6: MPORTP7 Position */
+#define GPIO_PORT_MPIN6_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP7_Pos) /*!< GPIO_PORT MPIN6: MPORTP7 Mask */
+#define GPIO_PORT_MPIN6_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN6: MPORTP8 Position */
+#define GPIO_PORT_MPIN6_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP8_Pos) /*!< GPIO_PORT MPIN6: MPORTP8 Mask */
+#define GPIO_PORT_MPIN6_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN6: MPORTP9 Position */
+#define GPIO_PORT_MPIN6_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP9_Pos) /*!< GPIO_PORT MPIN6: MPORTP9 Mask */
+#define GPIO_PORT_MPIN6_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN6: MPORTP10 Position */
+#define GPIO_PORT_MPIN6_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP10_Pos) /*!< GPIO_PORT MPIN6: MPORTP10 Mask */
+#define GPIO_PORT_MPIN6_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN6: MPORTP11 Position */
+#define GPIO_PORT_MPIN6_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP11_Pos) /*!< GPIO_PORT MPIN6: MPORTP11 Mask */
+#define GPIO_PORT_MPIN6_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN6: MPORTP12 Position */
+#define GPIO_PORT_MPIN6_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP12_Pos) /*!< GPIO_PORT MPIN6: MPORTP12 Mask */
+#define GPIO_PORT_MPIN6_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN6: MPORTP13 Position */
+#define GPIO_PORT_MPIN6_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP13_Pos) /*!< GPIO_PORT MPIN6: MPORTP13 Mask */
+#define GPIO_PORT_MPIN6_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN6: MPORTP14 Position */
+#define GPIO_PORT_MPIN6_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP14_Pos) /*!< GPIO_PORT MPIN6: MPORTP14 Mask */
+#define GPIO_PORT_MPIN6_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN6: MPORTP15 Position */
+#define GPIO_PORT_MPIN6_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP15_Pos) /*!< GPIO_PORT MPIN6: MPORTP15 Mask */
+#define GPIO_PORT_MPIN6_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN6: MPORTP16 Position */
+#define GPIO_PORT_MPIN6_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP16_Pos) /*!< GPIO_PORT MPIN6: MPORTP16 Mask */
+#define GPIO_PORT_MPIN6_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN6: MPORTP17 Position */
+#define GPIO_PORT_MPIN6_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP17_Pos) /*!< GPIO_PORT MPIN6: MPORTP17 Mask */
+#define GPIO_PORT_MPIN6_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN6: MPORTP18 Position */
+#define GPIO_PORT_MPIN6_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP18_Pos) /*!< GPIO_PORT MPIN6: MPORTP18 Mask */
+#define GPIO_PORT_MPIN6_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN6: MPORTP19 Position */
+#define GPIO_PORT_MPIN6_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP19_Pos) /*!< GPIO_PORT MPIN6: MPORTP19 Mask */
+#define GPIO_PORT_MPIN6_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN6: MPORTP20 Position */
+#define GPIO_PORT_MPIN6_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP20_Pos) /*!< GPIO_PORT MPIN6: MPORTP20 Mask */
+#define GPIO_PORT_MPIN6_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN6: MPORTP21 Position */
+#define GPIO_PORT_MPIN6_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP21_Pos) /*!< GPIO_PORT MPIN6: MPORTP21 Mask */
+#define GPIO_PORT_MPIN6_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN6: MPORTP22 Position */
+#define GPIO_PORT_MPIN6_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP22_Pos) /*!< GPIO_PORT MPIN6: MPORTP22 Mask */
+#define GPIO_PORT_MPIN6_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN6: MPORTP23 Position */
+#define GPIO_PORT_MPIN6_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP23_Pos) /*!< GPIO_PORT MPIN6: MPORTP23 Mask */
+#define GPIO_PORT_MPIN6_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN6: MPORTP24 Position */
+#define GPIO_PORT_MPIN6_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP24_Pos) /*!< GPIO_PORT MPIN6: MPORTP24 Mask */
+#define GPIO_PORT_MPIN6_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN6: MPORTP25 Position */
+#define GPIO_PORT_MPIN6_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP25_Pos) /*!< GPIO_PORT MPIN6: MPORTP25 Mask */
+#define GPIO_PORT_MPIN6_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN6: MPORTP26 Position */
+#define GPIO_PORT_MPIN6_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP26_Pos) /*!< GPIO_PORT MPIN6: MPORTP26 Mask */
+#define GPIO_PORT_MPIN6_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN6: MPORTP27 Position */
+#define GPIO_PORT_MPIN6_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP27_Pos) /*!< GPIO_PORT MPIN6: MPORTP27 Mask */
+#define GPIO_PORT_MPIN6_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN6: MPORTP28 Position */
+#define GPIO_PORT_MPIN6_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP28_Pos) /*!< GPIO_PORT MPIN6: MPORTP28 Mask */
+#define GPIO_PORT_MPIN6_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN6: MPORTP29 Position */
+#define GPIO_PORT_MPIN6_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP29_Pos) /*!< GPIO_PORT MPIN6: MPORTP29 Mask */
+#define GPIO_PORT_MPIN6_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN6: MPORTP30 Position */
+#define GPIO_PORT_MPIN6_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP30_Pos) /*!< GPIO_PORT MPIN6: MPORTP30 Mask */
+#define GPIO_PORT_MPIN6_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN6: MPORTP31 Position */
+#define GPIO_PORT_MPIN6_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP31_Pos) /*!< GPIO_PORT MPIN6: MPORTP31 Mask */
+
+// ------------------------------------- GPIO_PORT_MPIN7 ----------------------------------------
+#define GPIO_PORT_MPIN7_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN7: MPORTP0 Position */
+#define GPIO_PORT_MPIN7_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP0_Pos) /*!< GPIO_PORT MPIN7: MPORTP0 Mask */
+#define GPIO_PORT_MPIN7_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN7: MPORTP1 Position */
+#define GPIO_PORT_MPIN7_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP1_Pos) /*!< GPIO_PORT MPIN7: MPORTP1 Mask */
+#define GPIO_PORT_MPIN7_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN7: MPORTP2 Position */
+#define GPIO_PORT_MPIN7_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP2_Pos) /*!< GPIO_PORT MPIN7: MPORTP2 Mask */
+#define GPIO_PORT_MPIN7_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN7: MPORTP3 Position */
+#define GPIO_PORT_MPIN7_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP3_Pos) /*!< GPIO_PORT MPIN7: MPORTP3 Mask */
+#define GPIO_PORT_MPIN7_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN7: MPORTP4 Position */
+#define GPIO_PORT_MPIN7_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP4_Pos) /*!< GPIO_PORT MPIN7: MPORTP4 Mask */
+#define GPIO_PORT_MPIN7_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN7: MPORTP5 Position */
+#define GPIO_PORT_MPIN7_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP5_Pos) /*!< GPIO_PORT MPIN7: MPORTP5 Mask */
+#define GPIO_PORT_MPIN7_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN7: MPORTP6 Position */
+#define GPIO_PORT_MPIN7_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP6_Pos) /*!< GPIO_PORT MPIN7: MPORTP6 Mask */
+#define GPIO_PORT_MPIN7_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN7: MPORTP7 Position */
+#define GPIO_PORT_MPIN7_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP7_Pos) /*!< GPIO_PORT MPIN7: MPORTP7 Mask */
+#define GPIO_PORT_MPIN7_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN7: MPORTP8 Position */
+#define GPIO_PORT_MPIN7_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP8_Pos) /*!< GPIO_PORT MPIN7: MPORTP8 Mask */
+#define GPIO_PORT_MPIN7_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN7: MPORTP9 Position */
+#define GPIO_PORT_MPIN7_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP9_Pos) /*!< GPIO_PORT MPIN7: MPORTP9 Mask */
+#define GPIO_PORT_MPIN7_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN7: MPORTP10 Position */
+#define GPIO_PORT_MPIN7_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP10_Pos) /*!< GPIO_PORT MPIN7: MPORTP10 Mask */
+#define GPIO_PORT_MPIN7_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN7: MPORTP11 Position */
+#define GPIO_PORT_MPIN7_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP11_Pos) /*!< GPIO_PORT MPIN7: MPORTP11 Mask */
+#define GPIO_PORT_MPIN7_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN7: MPORTP12 Position */
+#define GPIO_PORT_MPIN7_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP12_Pos) /*!< GPIO_PORT MPIN7: MPORTP12 Mask */
+#define GPIO_PORT_MPIN7_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN7: MPORTP13 Position */
+#define GPIO_PORT_MPIN7_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP13_Pos) /*!< GPIO_PORT MPIN7: MPORTP13 Mask */
+#define GPIO_PORT_MPIN7_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN7: MPORTP14 Position */
+#define GPIO_PORT_MPIN7_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP14_Pos) /*!< GPIO_PORT MPIN7: MPORTP14 Mask */
+#define GPIO_PORT_MPIN7_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN7: MPORTP15 Position */
+#define GPIO_PORT_MPIN7_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP15_Pos) /*!< GPIO_PORT MPIN7: MPORTP15 Mask */
+#define GPIO_PORT_MPIN7_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN7: MPORTP16 Position */
+#define GPIO_PORT_MPIN7_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP16_Pos) /*!< GPIO_PORT MPIN7: MPORTP16 Mask */
+#define GPIO_PORT_MPIN7_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN7: MPORTP17 Position */
+#define GPIO_PORT_MPIN7_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP17_Pos) /*!< GPIO_PORT MPIN7: MPORTP17 Mask */
+#define GPIO_PORT_MPIN7_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN7: MPORTP18 Position */
+#define GPIO_PORT_MPIN7_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP18_Pos) /*!< GPIO_PORT MPIN7: MPORTP18 Mask */
+#define GPIO_PORT_MPIN7_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN7: MPORTP19 Position */
+#define GPIO_PORT_MPIN7_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP19_Pos) /*!< GPIO_PORT MPIN7: MPORTP19 Mask */
+#define GPIO_PORT_MPIN7_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN7: MPORTP20 Position */
+#define GPIO_PORT_MPIN7_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP20_Pos) /*!< GPIO_PORT MPIN7: MPORTP20 Mask */
+#define GPIO_PORT_MPIN7_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN7: MPORTP21 Position */
+#define GPIO_PORT_MPIN7_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP21_Pos) /*!< GPIO_PORT MPIN7: MPORTP21 Mask */
+#define GPIO_PORT_MPIN7_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN7: MPORTP22 Position */
+#define GPIO_PORT_MPIN7_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP22_Pos) /*!< GPIO_PORT MPIN7: MPORTP22 Mask */
+#define GPIO_PORT_MPIN7_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN7: MPORTP23 Position */
+#define GPIO_PORT_MPIN7_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP23_Pos) /*!< GPIO_PORT MPIN7: MPORTP23 Mask */
+#define GPIO_PORT_MPIN7_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN7: MPORTP24 Position */
+#define GPIO_PORT_MPIN7_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP24_Pos) /*!< GPIO_PORT MPIN7: MPORTP24 Mask */
+#define GPIO_PORT_MPIN7_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN7: MPORTP25 Position */
+#define GPIO_PORT_MPIN7_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP25_Pos) /*!< GPIO_PORT MPIN7: MPORTP25 Mask */
+#define GPIO_PORT_MPIN7_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN7: MPORTP26 Position */
+#define GPIO_PORT_MPIN7_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP26_Pos) /*!< GPIO_PORT MPIN7: MPORTP26 Mask */
+#define GPIO_PORT_MPIN7_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN7: MPORTP27 Position */
+#define GPIO_PORT_MPIN7_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP27_Pos) /*!< GPIO_PORT MPIN7: MPORTP27 Mask */
+#define GPIO_PORT_MPIN7_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN7: MPORTP28 Position */
+#define GPIO_PORT_MPIN7_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP28_Pos) /*!< GPIO_PORT MPIN7: MPORTP28 Mask */
+#define GPIO_PORT_MPIN7_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN7: MPORTP29 Position */
+#define GPIO_PORT_MPIN7_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP29_Pos) /*!< GPIO_PORT MPIN7: MPORTP29 Mask */
+#define GPIO_PORT_MPIN7_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN7: MPORTP30 Position */
+#define GPIO_PORT_MPIN7_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP30_Pos) /*!< GPIO_PORT MPIN7: MPORTP30 Mask */
+#define GPIO_PORT_MPIN7_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN7: MPORTP31 Position */
+#define GPIO_PORT_MPIN7_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP31_Pos) /*!< GPIO_PORT MPIN7: MPORTP31 Mask */
+
+// ------------------------------------- GPIO_PORT_SET0 -----------------------------------------
+#define GPIO_PORT_SET0_SETP0_Pos 0 /*!< GPIO_PORT SET0: SETP0 Position */
+#define GPIO_PORT_SET0_SETP0_Msk (0x01UL << GPIO_PORT_SET0_SETP0_Pos) /*!< GPIO_PORT SET0: SETP0 Mask */
+#define GPIO_PORT_SET0_SETP1_Pos 1 /*!< GPIO_PORT SET0: SETP1 Position */
+#define GPIO_PORT_SET0_SETP1_Msk (0x01UL << GPIO_PORT_SET0_SETP1_Pos) /*!< GPIO_PORT SET0: SETP1 Mask */
+#define GPIO_PORT_SET0_SETP2_Pos 2 /*!< GPIO_PORT SET0: SETP2 Position */
+#define GPIO_PORT_SET0_SETP2_Msk (0x01UL << GPIO_PORT_SET0_SETP2_Pos) /*!< GPIO_PORT SET0: SETP2 Mask */
+#define GPIO_PORT_SET0_SETP3_Pos 3 /*!< GPIO_PORT SET0: SETP3 Position */
+#define GPIO_PORT_SET0_SETP3_Msk (0x01UL << GPIO_PORT_SET0_SETP3_Pos) /*!< GPIO_PORT SET0: SETP3 Mask */
+#define GPIO_PORT_SET0_SETP4_Pos 4 /*!< GPIO_PORT SET0: SETP4 Position */
+#define GPIO_PORT_SET0_SETP4_Msk (0x01UL << GPIO_PORT_SET0_SETP4_Pos) /*!< GPIO_PORT SET0: SETP4 Mask */
+#define GPIO_PORT_SET0_SETP5_Pos 5 /*!< GPIO_PORT SET0: SETP5 Position */
+#define GPIO_PORT_SET0_SETP5_Msk (0x01UL << GPIO_PORT_SET0_SETP5_Pos) /*!< GPIO_PORT SET0: SETP5 Mask */
+#define GPIO_PORT_SET0_SETP6_Pos 6 /*!< GPIO_PORT SET0: SETP6 Position */
+#define GPIO_PORT_SET0_SETP6_Msk (0x01UL << GPIO_PORT_SET0_SETP6_Pos) /*!< GPIO_PORT SET0: SETP6 Mask */
+#define GPIO_PORT_SET0_SETP7_Pos 7 /*!< GPIO_PORT SET0: SETP7 Position */
+#define GPIO_PORT_SET0_SETP7_Msk (0x01UL << GPIO_PORT_SET0_SETP7_Pos) /*!< GPIO_PORT SET0: SETP7 Mask */
+#define GPIO_PORT_SET0_SETP8_Pos 8 /*!< GPIO_PORT SET0: SETP8 Position */
+#define GPIO_PORT_SET0_SETP8_Msk (0x01UL << GPIO_PORT_SET0_SETP8_Pos) /*!< GPIO_PORT SET0: SETP8 Mask */
+#define GPIO_PORT_SET0_SETP9_Pos 9 /*!< GPIO_PORT SET0: SETP9 Position */
+#define GPIO_PORT_SET0_SETP9_Msk (0x01UL << GPIO_PORT_SET0_SETP9_Pos) /*!< GPIO_PORT SET0: SETP9 Mask */
+#define GPIO_PORT_SET0_SETP10_Pos 10 /*!< GPIO_PORT SET0: SETP10 Position */
+#define GPIO_PORT_SET0_SETP10_Msk (0x01UL << GPIO_PORT_SET0_SETP10_Pos) /*!< GPIO_PORT SET0: SETP10 Mask */
+#define GPIO_PORT_SET0_SETP11_Pos 11 /*!< GPIO_PORT SET0: SETP11 Position */
+#define GPIO_PORT_SET0_SETP11_Msk (0x01UL << GPIO_PORT_SET0_SETP11_Pos) /*!< GPIO_PORT SET0: SETP11 Mask */
+#define GPIO_PORT_SET0_SETP12_Pos 12 /*!< GPIO_PORT SET0: SETP12 Position */
+#define GPIO_PORT_SET0_SETP12_Msk (0x01UL << GPIO_PORT_SET0_SETP12_Pos) /*!< GPIO_PORT SET0: SETP12 Mask */
+#define GPIO_PORT_SET0_SETP13_Pos 13 /*!< GPIO_PORT SET0: SETP13 Position */
+#define GPIO_PORT_SET0_SETP13_Msk (0x01UL << GPIO_PORT_SET0_SETP13_Pos) /*!< GPIO_PORT SET0: SETP13 Mask */
+#define GPIO_PORT_SET0_SETP14_Pos 14 /*!< GPIO_PORT SET0: SETP14 Position */
+#define GPIO_PORT_SET0_SETP14_Msk (0x01UL << GPIO_PORT_SET0_SETP14_Pos) /*!< GPIO_PORT SET0: SETP14 Mask */
+#define GPIO_PORT_SET0_SETP15_Pos 15 /*!< GPIO_PORT SET0: SETP15 Position */
+#define GPIO_PORT_SET0_SETP15_Msk (0x01UL << GPIO_PORT_SET0_SETP15_Pos) /*!< GPIO_PORT SET0: SETP15 Mask */
+#define GPIO_PORT_SET0_SETP16_Pos 16 /*!< GPIO_PORT SET0: SETP16 Position */
+#define GPIO_PORT_SET0_SETP16_Msk (0x01UL << GPIO_PORT_SET0_SETP16_Pos) /*!< GPIO_PORT SET0: SETP16 Mask */
+#define GPIO_PORT_SET0_SETP17_Pos 17 /*!< GPIO_PORT SET0: SETP17 Position */
+#define GPIO_PORT_SET0_SETP17_Msk (0x01UL << GPIO_PORT_SET0_SETP17_Pos) /*!< GPIO_PORT SET0: SETP17 Mask */
+#define GPIO_PORT_SET0_SETP18_Pos 18 /*!< GPIO_PORT SET0: SETP18 Position */
+#define GPIO_PORT_SET0_SETP18_Msk (0x01UL << GPIO_PORT_SET0_SETP18_Pos) /*!< GPIO_PORT SET0: SETP18 Mask */
+#define GPIO_PORT_SET0_SETP19_Pos 19 /*!< GPIO_PORT SET0: SETP19 Position */
+#define GPIO_PORT_SET0_SETP19_Msk (0x01UL << GPIO_PORT_SET0_SETP19_Pos) /*!< GPIO_PORT SET0: SETP19 Mask */
+#define GPIO_PORT_SET0_SETP20_Pos 20 /*!< GPIO_PORT SET0: SETP20 Position */
+#define GPIO_PORT_SET0_SETP20_Msk (0x01UL << GPIO_PORT_SET0_SETP20_Pos) /*!< GPIO_PORT SET0: SETP20 Mask */
+#define GPIO_PORT_SET0_SETP21_Pos 21 /*!< GPIO_PORT SET0: SETP21 Position */
+#define GPIO_PORT_SET0_SETP21_Msk (0x01UL << GPIO_PORT_SET0_SETP21_Pos) /*!< GPIO_PORT SET0: SETP21 Mask */
+#define GPIO_PORT_SET0_SETP22_Pos 22 /*!< GPIO_PORT SET0: SETP22 Position */
+#define GPIO_PORT_SET0_SETP22_Msk (0x01UL << GPIO_PORT_SET0_SETP22_Pos) /*!< GPIO_PORT SET0: SETP22 Mask */
+#define GPIO_PORT_SET0_SETP23_Pos 23 /*!< GPIO_PORT SET0: SETP23 Position */
+#define GPIO_PORT_SET0_SETP23_Msk (0x01UL << GPIO_PORT_SET0_SETP23_Pos) /*!< GPIO_PORT SET0: SETP23 Mask */
+#define GPIO_PORT_SET0_SETP24_Pos 24 /*!< GPIO_PORT SET0: SETP24 Position */
+#define GPIO_PORT_SET0_SETP24_Msk (0x01UL << GPIO_PORT_SET0_SETP24_Pos) /*!< GPIO_PORT SET0: SETP24 Mask */
+#define GPIO_PORT_SET0_SETP25_Pos 25 /*!< GPIO_PORT SET0: SETP25 Position */
+#define GPIO_PORT_SET0_SETP25_Msk (0x01UL << GPIO_PORT_SET0_SETP25_Pos) /*!< GPIO_PORT SET0: SETP25 Mask */
+#define GPIO_PORT_SET0_SETP26_Pos 26 /*!< GPIO_PORT SET0: SETP26 Position */
+#define GPIO_PORT_SET0_SETP26_Msk (0x01UL << GPIO_PORT_SET0_SETP26_Pos) /*!< GPIO_PORT SET0: SETP26 Mask */
+#define GPIO_PORT_SET0_SETP27_Pos 27 /*!< GPIO_PORT SET0: SETP27 Position */
+#define GPIO_PORT_SET0_SETP27_Msk (0x01UL << GPIO_PORT_SET0_SETP27_Pos) /*!< GPIO_PORT SET0: SETP27 Mask */
+#define GPIO_PORT_SET0_SETP28_Pos 28 /*!< GPIO_PORT SET0: SETP28 Position */
+#define GPIO_PORT_SET0_SETP28_Msk (0x01UL << GPIO_PORT_SET0_SETP28_Pos) /*!< GPIO_PORT SET0: SETP28 Mask */
+#define GPIO_PORT_SET0_SETP29_Pos 29 /*!< GPIO_PORT SET0: SETP29 Position */
+#define GPIO_PORT_SET0_SETP29_Msk (0x01UL << GPIO_PORT_SET0_SETP29_Pos) /*!< GPIO_PORT SET0: SETP29 Mask */
+#define GPIO_PORT_SET0_SETP30_Pos 30 /*!< GPIO_PORT SET0: SETP30 Position */
+#define GPIO_PORT_SET0_SETP30_Msk (0x01UL << GPIO_PORT_SET0_SETP30_Pos) /*!< GPIO_PORT SET0: SETP30 Mask */
+#define GPIO_PORT_SET0_SETP31_Pos 31 /*!< GPIO_PORT SET0: SETP31 Position */
+#define GPIO_PORT_SET0_SETP31_Msk (0x01UL << GPIO_PORT_SET0_SETP31_Pos) /*!< GPIO_PORT SET0: SETP31 Mask */
+
+// ------------------------------------- GPIO_PORT_SET1 -----------------------------------------
+#define GPIO_PORT_SET1_SETP0_Pos 0 /*!< GPIO_PORT SET1: SETP0 Position */
+#define GPIO_PORT_SET1_SETP0_Msk (0x01UL << GPIO_PORT_SET1_SETP0_Pos) /*!< GPIO_PORT SET1: SETP0 Mask */
+#define GPIO_PORT_SET1_SETP1_Pos 1 /*!< GPIO_PORT SET1: SETP1 Position */
+#define GPIO_PORT_SET1_SETP1_Msk (0x01UL << GPIO_PORT_SET1_SETP1_Pos) /*!< GPIO_PORT SET1: SETP1 Mask */
+#define GPIO_PORT_SET1_SETP2_Pos 2 /*!< GPIO_PORT SET1: SETP2 Position */
+#define GPIO_PORT_SET1_SETP2_Msk (0x01UL << GPIO_PORT_SET1_SETP2_Pos) /*!< GPIO_PORT SET1: SETP2 Mask */
+#define GPIO_PORT_SET1_SETP3_Pos 3 /*!< GPIO_PORT SET1: SETP3 Position */
+#define GPIO_PORT_SET1_SETP3_Msk (0x01UL << GPIO_PORT_SET1_SETP3_Pos) /*!< GPIO_PORT SET1: SETP3 Mask */
+#define GPIO_PORT_SET1_SETP4_Pos 4 /*!< GPIO_PORT SET1: SETP4 Position */
+#define GPIO_PORT_SET1_SETP4_Msk (0x01UL << GPIO_PORT_SET1_SETP4_Pos) /*!< GPIO_PORT SET1: SETP4 Mask */
+#define GPIO_PORT_SET1_SETP5_Pos 5 /*!< GPIO_PORT SET1: SETP5 Position */
+#define GPIO_PORT_SET1_SETP5_Msk (0x01UL << GPIO_PORT_SET1_SETP5_Pos) /*!< GPIO_PORT SET1: SETP5 Mask */
+#define GPIO_PORT_SET1_SETP6_Pos 6 /*!< GPIO_PORT SET1: SETP6 Position */
+#define GPIO_PORT_SET1_SETP6_Msk (0x01UL << GPIO_PORT_SET1_SETP6_Pos) /*!< GPIO_PORT SET1: SETP6 Mask */
+#define GPIO_PORT_SET1_SETP7_Pos 7 /*!< GPIO_PORT SET1: SETP7 Position */
+#define GPIO_PORT_SET1_SETP7_Msk (0x01UL << GPIO_PORT_SET1_SETP7_Pos) /*!< GPIO_PORT SET1: SETP7 Mask */
+#define GPIO_PORT_SET1_SETP8_Pos 8 /*!< GPIO_PORT SET1: SETP8 Position */
+#define GPIO_PORT_SET1_SETP8_Msk (0x01UL << GPIO_PORT_SET1_SETP8_Pos) /*!< GPIO_PORT SET1: SETP8 Mask */
+#define GPIO_PORT_SET1_SETP9_Pos 9 /*!< GPIO_PORT SET1: SETP9 Position */
+#define GPIO_PORT_SET1_SETP9_Msk (0x01UL << GPIO_PORT_SET1_SETP9_Pos) /*!< GPIO_PORT SET1: SETP9 Mask */
+#define GPIO_PORT_SET1_SETP10_Pos 10 /*!< GPIO_PORT SET1: SETP10 Position */
+#define GPIO_PORT_SET1_SETP10_Msk (0x01UL << GPIO_PORT_SET1_SETP10_Pos) /*!< GPIO_PORT SET1: SETP10 Mask */
+#define GPIO_PORT_SET1_SETP11_Pos 11 /*!< GPIO_PORT SET1: SETP11 Position */
+#define GPIO_PORT_SET1_SETP11_Msk (0x01UL << GPIO_PORT_SET1_SETP11_Pos) /*!< GPIO_PORT SET1: SETP11 Mask */
+#define GPIO_PORT_SET1_SETP12_Pos 12 /*!< GPIO_PORT SET1: SETP12 Position */
+#define GPIO_PORT_SET1_SETP12_Msk (0x01UL << GPIO_PORT_SET1_SETP12_Pos) /*!< GPIO_PORT SET1: SETP12 Mask */
+#define GPIO_PORT_SET1_SETP13_Pos 13 /*!< GPIO_PORT SET1: SETP13 Position */
+#define GPIO_PORT_SET1_SETP13_Msk (0x01UL << GPIO_PORT_SET1_SETP13_Pos) /*!< GPIO_PORT SET1: SETP13 Mask */
+#define GPIO_PORT_SET1_SETP14_Pos 14 /*!< GPIO_PORT SET1: SETP14 Position */
+#define GPIO_PORT_SET1_SETP14_Msk (0x01UL << GPIO_PORT_SET1_SETP14_Pos) /*!< GPIO_PORT SET1: SETP14 Mask */
+#define GPIO_PORT_SET1_SETP15_Pos 15 /*!< GPIO_PORT SET1: SETP15 Position */
+#define GPIO_PORT_SET1_SETP15_Msk (0x01UL << GPIO_PORT_SET1_SETP15_Pos) /*!< GPIO_PORT SET1: SETP15 Mask */
+#define GPIO_PORT_SET1_SETP16_Pos 16 /*!< GPIO_PORT SET1: SETP16 Position */
+#define GPIO_PORT_SET1_SETP16_Msk (0x01UL << GPIO_PORT_SET1_SETP16_Pos) /*!< GPIO_PORT SET1: SETP16 Mask */
+#define GPIO_PORT_SET1_SETP17_Pos 17 /*!< GPIO_PORT SET1: SETP17 Position */
+#define GPIO_PORT_SET1_SETP17_Msk (0x01UL << GPIO_PORT_SET1_SETP17_Pos) /*!< GPIO_PORT SET1: SETP17 Mask */
+#define GPIO_PORT_SET1_SETP18_Pos 18 /*!< GPIO_PORT SET1: SETP18 Position */
+#define GPIO_PORT_SET1_SETP18_Msk (0x01UL << GPIO_PORT_SET1_SETP18_Pos) /*!< GPIO_PORT SET1: SETP18 Mask */
+#define GPIO_PORT_SET1_SETP19_Pos 19 /*!< GPIO_PORT SET1: SETP19 Position */
+#define GPIO_PORT_SET1_SETP19_Msk (0x01UL << GPIO_PORT_SET1_SETP19_Pos) /*!< GPIO_PORT SET1: SETP19 Mask */
+#define GPIO_PORT_SET1_SETP20_Pos 20 /*!< GPIO_PORT SET1: SETP20 Position */
+#define GPIO_PORT_SET1_SETP20_Msk (0x01UL << GPIO_PORT_SET1_SETP20_Pos) /*!< GPIO_PORT SET1: SETP20 Mask */
+#define GPIO_PORT_SET1_SETP21_Pos 21 /*!< GPIO_PORT SET1: SETP21 Position */
+#define GPIO_PORT_SET1_SETP21_Msk (0x01UL << GPIO_PORT_SET1_SETP21_Pos) /*!< GPIO_PORT SET1: SETP21 Mask */
+#define GPIO_PORT_SET1_SETP22_Pos 22 /*!< GPIO_PORT SET1: SETP22 Position */
+#define GPIO_PORT_SET1_SETP22_Msk (0x01UL << GPIO_PORT_SET1_SETP22_Pos) /*!< GPIO_PORT SET1: SETP22 Mask */
+#define GPIO_PORT_SET1_SETP23_Pos 23 /*!< GPIO_PORT SET1: SETP23 Position */
+#define GPIO_PORT_SET1_SETP23_Msk (0x01UL << GPIO_PORT_SET1_SETP23_Pos) /*!< GPIO_PORT SET1: SETP23 Mask */
+#define GPIO_PORT_SET1_SETP24_Pos 24 /*!< GPIO_PORT SET1: SETP24 Position */
+#define GPIO_PORT_SET1_SETP24_Msk (0x01UL << GPIO_PORT_SET1_SETP24_Pos) /*!< GPIO_PORT SET1: SETP24 Mask */
+#define GPIO_PORT_SET1_SETP25_Pos 25 /*!< GPIO_PORT SET1: SETP25 Position */
+#define GPIO_PORT_SET1_SETP25_Msk (0x01UL << GPIO_PORT_SET1_SETP25_Pos) /*!< GPIO_PORT SET1: SETP25 Mask */
+#define GPIO_PORT_SET1_SETP26_Pos 26 /*!< GPIO_PORT SET1: SETP26 Position */
+#define GPIO_PORT_SET1_SETP26_Msk (0x01UL << GPIO_PORT_SET1_SETP26_Pos) /*!< GPIO_PORT SET1: SETP26 Mask */
+#define GPIO_PORT_SET1_SETP27_Pos 27 /*!< GPIO_PORT SET1: SETP27 Position */
+#define GPIO_PORT_SET1_SETP27_Msk (0x01UL << GPIO_PORT_SET1_SETP27_Pos) /*!< GPIO_PORT SET1: SETP27 Mask */
+#define GPIO_PORT_SET1_SETP28_Pos 28 /*!< GPIO_PORT SET1: SETP28 Position */
+#define GPIO_PORT_SET1_SETP28_Msk (0x01UL << GPIO_PORT_SET1_SETP28_Pos) /*!< GPIO_PORT SET1: SETP28 Mask */
+#define GPIO_PORT_SET1_SETP29_Pos 29 /*!< GPIO_PORT SET1: SETP29 Position */
+#define GPIO_PORT_SET1_SETP29_Msk (0x01UL << GPIO_PORT_SET1_SETP29_Pos) /*!< GPIO_PORT SET1: SETP29 Mask */
+#define GPIO_PORT_SET1_SETP30_Pos 30 /*!< GPIO_PORT SET1: SETP30 Position */
+#define GPIO_PORT_SET1_SETP30_Msk (0x01UL << GPIO_PORT_SET1_SETP30_Pos) /*!< GPIO_PORT SET1: SETP30 Mask */
+#define GPIO_PORT_SET1_SETP31_Pos 31 /*!< GPIO_PORT SET1: SETP31 Position */
+#define GPIO_PORT_SET1_SETP31_Msk (0x01UL << GPIO_PORT_SET1_SETP31_Pos) /*!< GPIO_PORT SET1: SETP31 Mask */
+
+// ------------------------------------- GPIO_PORT_SET2 -----------------------------------------
+#define GPIO_PORT_SET2_SETP0_Pos 0 /*!< GPIO_PORT SET2: SETP0 Position */
+#define GPIO_PORT_SET2_SETP0_Msk (0x01UL << GPIO_PORT_SET2_SETP0_Pos) /*!< GPIO_PORT SET2: SETP0 Mask */
+#define GPIO_PORT_SET2_SETP1_Pos 1 /*!< GPIO_PORT SET2: SETP1 Position */
+#define GPIO_PORT_SET2_SETP1_Msk (0x01UL << GPIO_PORT_SET2_SETP1_Pos) /*!< GPIO_PORT SET2: SETP1 Mask */
+#define GPIO_PORT_SET2_SETP2_Pos 2 /*!< GPIO_PORT SET2: SETP2 Position */
+#define GPIO_PORT_SET2_SETP2_Msk (0x01UL << GPIO_PORT_SET2_SETP2_Pos) /*!< GPIO_PORT SET2: SETP2 Mask */
+#define GPIO_PORT_SET2_SETP3_Pos 3 /*!< GPIO_PORT SET2: SETP3 Position */
+#define GPIO_PORT_SET2_SETP3_Msk (0x01UL << GPIO_PORT_SET2_SETP3_Pos) /*!< GPIO_PORT SET2: SETP3 Mask */
+#define GPIO_PORT_SET2_SETP4_Pos 4 /*!< GPIO_PORT SET2: SETP4 Position */
+#define GPIO_PORT_SET2_SETP4_Msk (0x01UL << GPIO_PORT_SET2_SETP4_Pos) /*!< GPIO_PORT SET2: SETP4 Mask */
+#define GPIO_PORT_SET2_SETP5_Pos 5 /*!< GPIO_PORT SET2: SETP5 Position */
+#define GPIO_PORT_SET2_SETP5_Msk (0x01UL << GPIO_PORT_SET2_SETP5_Pos) /*!< GPIO_PORT SET2: SETP5 Mask */
+#define GPIO_PORT_SET2_SETP6_Pos 6 /*!< GPIO_PORT SET2: SETP6 Position */
+#define GPIO_PORT_SET2_SETP6_Msk (0x01UL << GPIO_PORT_SET2_SETP6_Pos) /*!< GPIO_PORT SET2: SETP6 Mask */
+#define GPIO_PORT_SET2_SETP7_Pos 7 /*!< GPIO_PORT SET2: SETP7 Position */
+#define GPIO_PORT_SET2_SETP7_Msk (0x01UL << GPIO_PORT_SET2_SETP7_Pos) /*!< GPIO_PORT SET2: SETP7 Mask */
+#define GPIO_PORT_SET2_SETP8_Pos 8 /*!< GPIO_PORT SET2: SETP8 Position */
+#define GPIO_PORT_SET2_SETP8_Msk (0x01UL << GPIO_PORT_SET2_SETP8_Pos) /*!< GPIO_PORT SET2: SETP8 Mask */
+#define GPIO_PORT_SET2_SETP9_Pos 9 /*!< GPIO_PORT SET2: SETP9 Position */
+#define GPIO_PORT_SET2_SETP9_Msk (0x01UL << GPIO_PORT_SET2_SETP9_Pos) /*!< GPIO_PORT SET2: SETP9 Mask */
+#define GPIO_PORT_SET2_SETP10_Pos 10 /*!< GPIO_PORT SET2: SETP10 Position */
+#define GPIO_PORT_SET2_SETP10_Msk (0x01UL << GPIO_PORT_SET2_SETP10_Pos) /*!< GPIO_PORT SET2: SETP10 Mask */
+#define GPIO_PORT_SET2_SETP11_Pos 11 /*!< GPIO_PORT SET2: SETP11 Position */
+#define GPIO_PORT_SET2_SETP11_Msk (0x01UL << GPIO_PORT_SET2_SETP11_Pos) /*!< GPIO_PORT SET2: SETP11 Mask */
+#define GPIO_PORT_SET2_SETP12_Pos 12 /*!< GPIO_PORT SET2: SETP12 Position */
+#define GPIO_PORT_SET2_SETP12_Msk (0x01UL << GPIO_PORT_SET2_SETP12_Pos) /*!< GPIO_PORT SET2: SETP12 Mask */
+#define GPIO_PORT_SET2_SETP13_Pos 13 /*!< GPIO_PORT SET2: SETP13 Position */
+#define GPIO_PORT_SET2_SETP13_Msk (0x01UL << GPIO_PORT_SET2_SETP13_Pos) /*!< GPIO_PORT SET2: SETP13 Mask */
+#define GPIO_PORT_SET2_SETP14_Pos 14 /*!< GPIO_PORT SET2: SETP14 Position */
+#define GPIO_PORT_SET2_SETP14_Msk (0x01UL << GPIO_PORT_SET2_SETP14_Pos) /*!< GPIO_PORT SET2: SETP14 Mask */
+#define GPIO_PORT_SET2_SETP15_Pos 15 /*!< GPIO_PORT SET2: SETP15 Position */
+#define GPIO_PORT_SET2_SETP15_Msk (0x01UL << GPIO_PORT_SET2_SETP15_Pos) /*!< GPIO_PORT SET2: SETP15 Mask */
+#define GPIO_PORT_SET2_SETP16_Pos 16 /*!< GPIO_PORT SET2: SETP16 Position */
+#define GPIO_PORT_SET2_SETP16_Msk (0x01UL << GPIO_PORT_SET2_SETP16_Pos) /*!< GPIO_PORT SET2: SETP16 Mask */
+#define GPIO_PORT_SET2_SETP17_Pos 17 /*!< GPIO_PORT SET2: SETP17 Position */
+#define GPIO_PORT_SET2_SETP17_Msk (0x01UL << GPIO_PORT_SET2_SETP17_Pos) /*!< GPIO_PORT SET2: SETP17 Mask */
+#define GPIO_PORT_SET2_SETP18_Pos 18 /*!< GPIO_PORT SET2: SETP18 Position */
+#define GPIO_PORT_SET2_SETP18_Msk (0x01UL << GPIO_PORT_SET2_SETP18_Pos) /*!< GPIO_PORT SET2: SETP18 Mask */
+#define GPIO_PORT_SET2_SETP19_Pos 19 /*!< GPIO_PORT SET2: SETP19 Position */
+#define GPIO_PORT_SET2_SETP19_Msk (0x01UL << GPIO_PORT_SET2_SETP19_Pos) /*!< GPIO_PORT SET2: SETP19 Mask */
+#define GPIO_PORT_SET2_SETP20_Pos 20 /*!< GPIO_PORT SET2: SETP20 Position */
+#define GPIO_PORT_SET2_SETP20_Msk (0x01UL << GPIO_PORT_SET2_SETP20_Pos) /*!< GPIO_PORT SET2: SETP20 Mask */
+#define GPIO_PORT_SET2_SETP21_Pos 21 /*!< GPIO_PORT SET2: SETP21 Position */
+#define GPIO_PORT_SET2_SETP21_Msk (0x01UL << GPIO_PORT_SET2_SETP21_Pos) /*!< GPIO_PORT SET2: SETP21 Mask */
+#define GPIO_PORT_SET2_SETP22_Pos 22 /*!< GPIO_PORT SET2: SETP22 Position */
+#define GPIO_PORT_SET2_SETP22_Msk (0x01UL << GPIO_PORT_SET2_SETP22_Pos) /*!< GPIO_PORT SET2: SETP22 Mask */
+#define GPIO_PORT_SET2_SETP23_Pos 23 /*!< GPIO_PORT SET2: SETP23 Position */
+#define GPIO_PORT_SET2_SETP23_Msk (0x01UL << GPIO_PORT_SET2_SETP23_Pos) /*!< GPIO_PORT SET2: SETP23 Mask */
+#define GPIO_PORT_SET2_SETP24_Pos 24 /*!< GPIO_PORT SET2: SETP24 Position */
+#define GPIO_PORT_SET2_SETP24_Msk (0x01UL << GPIO_PORT_SET2_SETP24_Pos) /*!< GPIO_PORT SET2: SETP24 Mask */
+#define GPIO_PORT_SET2_SETP25_Pos 25 /*!< GPIO_PORT SET2: SETP25 Position */
+#define GPIO_PORT_SET2_SETP25_Msk (0x01UL << GPIO_PORT_SET2_SETP25_Pos) /*!< GPIO_PORT SET2: SETP25 Mask */
+#define GPIO_PORT_SET2_SETP26_Pos 26 /*!< GPIO_PORT SET2: SETP26 Position */
+#define GPIO_PORT_SET2_SETP26_Msk (0x01UL << GPIO_PORT_SET2_SETP26_Pos) /*!< GPIO_PORT SET2: SETP26 Mask */
+#define GPIO_PORT_SET2_SETP27_Pos 27 /*!< GPIO_PORT SET2: SETP27 Position */
+#define GPIO_PORT_SET2_SETP27_Msk (0x01UL << GPIO_PORT_SET2_SETP27_Pos) /*!< GPIO_PORT SET2: SETP27 Mask */
+#define GPIO_PORT_SET2_SETP28_Pos 28 /*!< GPIO_PORT SET2: SETP28 Position */
+#define GPIO_PORT_SET2_SETP28_Msk (0x01UL << GPIO_PORT_SET2_SETP28_Pos) /*!< GPIO_PORT SET2: SETP28 Mask */
+#define GPIO_PORT_SET2_SETP29_Pos 29 /*!< GPIO_PORT SET2: SETP29 Position */
+#define GPIO_PORT_SET2_SETP29_Msk (0x01UL << GPIO_PORT_SET2_SETP29_Pos) /*!< GPIO_PORT SET2: SETP29 Mask */
+#define GPIO_PORT_SET2_SETP30_Pos 30 /*!< GPIO_PORT SET2: SETP30 Position */
+#define GPIO_PORT_SET2_SETP30_Msk (0x01UL << GPIO_PORT_SET2_SETP30_Pos) /*!< GPIO_PORT SET2: SETP30 Mask */
+#define GPIO_PORT_SET2_SETP31_Pos 31 /*!< GPIO_PORT SET2: SETP31 Position */
+#define GPIO_PORT_SET2_SETP31_Msk (0x01UL << GPIO_PORT_SET2_SETP31_Pos) /*!< GPIO_PORT SET2: SETP31 Mask */
+
+// ------------------------------------- GPIO_PORT_SET3 -----------------------------------------
+#define GPIO_PORT_SET3_SETP0_Pos 0 /*!< GPIO_PORT SET3: SETP0 Position */
+#define GPIO_PORT_SET3_SETP0_Msk (0x01UL << GPIO_PORT_SET3_SETP0_Pos) /*!< GPIO_PORT SET3: SETP0 Mask */
+#define GPIO_PORT_SET3_SETP1_Pos 1 /*!< GPIO_PORT SET3: SETP1 Position */
+#define GPIO_PORT_SET3_SETP1_Msk (0x01UL << GPIO_PORT_SET3_SETP1_Pos) /*!< GPIO_PORT SET3: SETP1 Mask */
+#define GPIO_PORT_SET3_SETP2_Pos 2 /*!< GPIO_PORT SET3: SETP2 Position */
+#define GPIO_PORT_SET3_SETP2_Msk (0x01UL << GPIO_PORT_SET3_SETP2_Pos) /*!< GPIO_PORT SET3: SETP2 Mask */
+#define GPIO_PORT_SET3_SETP3_Pos 3 /*!< GPIO_PORT SET3: SETP3 Position */
+#define GPIO_PORT_SET3_SETP3_Msk (0x01UL << GPIO_PORT_SET3_SETP3_Pos) /*!< GPIO_PORT SET3: SETP3 Mask */
+#define GPIO_PORT_SET3_SETP4_Pos 4 /*!< GPIO_PORT SET3: SETP4 Position */
+#define GPIO_PORT_SET3_SETP4_Msk (0x01UL << GPIO_PORT_SET3_SETP4_Pos) /*!< GPIO_PORT SET3: SETP4 Mask */
+#define GPIO_PORT_SET3_SETP5_Pos 5 /*!< GPIO_PORT SET3: SETP5 Position */
+#define GPIO_PORT_SET3_SETP5_Msk (0x01UL << GPIO_PORT_SET3_SETP5_Pos) /*!< GPIO_PORT SET3: SETP5 Mask */
+#define GPIO_PORT_SET3_SETP6_Pos 6 /*!< GPIO_PORT SET3: SETP6 Position */
+#define GPIO_PORT_SET3_SETP6_Msk (0x01UL << GPIO_PORT_SET3_SETP6_Pos) /*!< GPIO_PORT SET3: SETP6 Mask */
+#define GPIO_PORT_SET3_SETP7_Pos 7 /*!< GPIO_PORT SET3: SETP7 Position */
+#define GPIO_PORT_SET3_SETP7_Msk (0x01UL << GPIO_PORT_SET3_SETP7_Pos) /*!< GPIO_PORT SET3: SETP7 Mask */
+#define GPIO_PORT_SET3_SETP8_Pos 8 /*!< GPIO_PORT SET3: SETP8 Position */
+#define GPIO_PORT_SET3_SETP8_Msk (0x01UL << GPIO_PORT_SET3_SETP8_Pos) /*!< GPIO_PORT SET3: SETP8 Mask */
+#define GPIO_PORT_SET3_SETP9_Pos 9 /*!< GPIO_PORT SET3: SETP9 Position */
+#define GPIO_PORT_SET3_SETP9_Msk (0x01UL << GPIO_PORT_SET3_SETP9_Pos) /*!< GPIO_PORT SET3: SETP9 Mask */
+#define GPIO_PORT_SET3_SETP10_Pos 10 /*!< GPIO_PORT SET3: SETP10 Position */
+#define GPIO_PORT_SET3_SETP10_Msk (0x01UL << GPIO_PORT_SET3_SETP10_Pos) /*!< GPIO_PORT SET3: SETP10 Mask */
+#define GPIO_PORT_SET3_SETP11_Pos 11 /*!< GPIO_PORT SET3: SETP11 Position */
+#define GPIO_PORT_SET3_SETP11_Msk (0x01UL << GPIO_PORT_SET3_SETP11_Pos) /*!< GPIO_PORT SET3: SETP11 Mask */
+#define GPIO_PORT_SET3_SETP12_Pos 12 /*!< GPIO_PORT SET3: SETP12 Position */
+#define GPIO_PORT_SET3_SETP12_Msk (0x01UL << GPIO_PORT_SET3_SETP12_Pos) /*!< GPIO_PORT SET3: SETP12 Mask */
+#define GPIO_PORT_SET3_SETP13_Pos 13 /*!< GPIO_PORT SET3: SETP13 Position */
+#define GPIO_PORT_SET3_SETP13_Msk (0x01UL << GPIO_PORT_SET3_SETP13_Pos) /*!< GPIO_PORT SET3: SETP13 Mask */
+#define GPIO_PORT_SET3_SETP14_Pos 14 /*!< GPIO_PORT SET3: SETP14 Position */
+#define GPIO_PORT_SET3_SETP14_Msk (0x01UL << GPIO_PORT_SET3_SETP14_Pos) /*!< GPIO_PORT SET3: SETP14 Mask */
+#define GPIO_PORT_SET3_SETP15_Pos 15 /*!< GPIO_PORT SET3: SETP15 Position */
+#define GPIO_PORT_SET3_SETP15_Msk (0x01UL << GPIO_PORT_SET3_SETP15_Pos) /*!< GPIO_PORT SET3: SETP15 Mask */
+#define GPIO_PORT_SET3_SETP16_Pos 16 /*!< GPIO_PORT SET3: SETP16 Position */
+#define GPIO_PORT_SET3_SETP16_Msk (0x01UL << GPIO_PORT_SET3_SETP16_Pos) /*!< GPIO_PORT SET3: SETP16 Mask */
+#define GPIO_PORT_SET3_SETP17_Pos 17 /*!< GPIO_PORT SET3: SETP17 Position */
+#define GPIO_PORT_SET3_SETP17_Msk (0x01UL << GPIO_PORT_SET3_SETP17_Pos) /*!< GPIO_PORT SET3: SETP17 Mask */
+#define GPIO_PORT_SET3_SETP18_Pos 18 /*!< GPIO_PORT SET3: SETP18 Position */
+#define GPIO_PORT_SET3_SETP18_Msk (0x01UL << GPIO_PORT_SET3_SETP18_Pos) /*!< GPIO_PORT SET3: SETP18 Mask */
+#define GPIO_PORT_SET3_SETP19_Pos 19 /*!< GPIO_PORT SET3: SETP19 Position */
+#define GPIO_PORT_SET3_SETP19_Msk (0x01UL << GPIO_PORT_SET3_SETP19_Pos) /*!< GPIO_PORT SET3: SETP19 Mask */
+#define GPIO_PORT_SET3_SETP20_Pos 20 /*!< GPIO_PORT SET3: SETP20 Position */
+#define GPIO_PORT_SET3_SETP20_Msk (0x01UL << GPIO_PORT_SET3_SETP20_Pos) /*!< GPIO_PORT SET3: SETP20 Mask */
+#define GPIO_PORT_SET3_SETP21_Pos 21 /*!< GPIO_PORT SET3: SETP21 Position */
+#define GPIO_PORT_SET3_SETP21_Msk (0x01UL << GPIO_PORT_SET3_SETP21_Pos) /*!< GPIO_PORT SET3: SETP21 Mask */
+#define GPIO_PORT_SET3_SETP22_Pos 22 /*!< GPIO_PORT SET3: SETP22 Position */
+#define GPIO_PORT_SET3_SETP22_Msk (0x01UL << GPIO_PORT_SET3_SETP22_Pos) /*!< GPIO_PORT SET3: SETP22 Mask */
+#define GPIO_PORT_SET3_SETP23_Pos 23 /*!< GPIO_PORT SET3: SETP23 Position */
+#define GPIO_PORT_SET3_SETP23_Msk (0x01UL << GPIO_PORT_SET3_SETP23_Pos) /*!< GPIO_PORT SET3: SETP23 Mask */
+#define GPIO_PORT_SET3_SETP24_Pos 24 /*!< GPIO_PORT SET3: SETP24 Position */
+#define GPIO_PORT_SET3_SETP24_Msk (0x01UL << GPIO_PORT_SET3_SETP24_Pos) /*!< GPIO_PORT SET3: SETP24 Mask */
+#define GPIO_PORT_SET3_SETP25_Pos 25 /*!< GPIO_PORT SET3: SETP25 Position */
+#define GPIO_PORT_SET3_SETP25_Msk (0x01UL << GPIO_PORT_SET3_SETP25_Pos) /*!< GPIO_PORT SET3: SETP25 Mask */
+#define GPIO_PORT_SET3_SETP26_Pos 26 /*!< GPIO_PORT SET3: SETP26 Position */
+#define GPIO_PORT_SET3_SETP26_Msk (0x01UL << GPIO_PORT_SET3_SETP26_Pos) /*!< GPIO_PORT SET3: SETP26 Mask */
+#define GPIO_PORT_SET3_SETP27_Pos 27 /*!< GPIO_PORT SET3: SETP27 Position */
+#define GPIO_PORT_SET3_SETP27_Msk (0x01UL << GPIO_PORT_SET3_SETP27_Pos) /*!< GPIO_PORT SET3: SETP27 Mask */
+#define GPIO_PORT_SET3_SETP28_Pos 28 /*!< GPIO_PORT SET3: SETP28 Position */
+#define GPIO_PORT_SET3_SETP28_Msk (0x01UL << GPIO_PORT_SET3_SETP28_Pos) /*!< GPIO_PORT SET3: SETP28 Mask */
+#define GPIO_PORT_SET3_SETP29_Pos 29 /*!< GPIO_PORT SET3: SETP29 Position */
+#define GPIO_PORT_SET3_SETP29_Msk (0x01UL << GPIO_PORT_SET3_SETP29_Pos) /*!< GPIO_PORT SET3: SETP29 Mask */
+#define GPIO_PORT_SET3_SETP30_Pos 30 /*!< GPIO_PORT SET3: SETP30 Position */
+#define GPIO_PORT_SET3_SETP30_Msk (0x01UL << GPIO_PORT_SET3_SETP30_Pos) /*!< GPIO_PORT SET3: SETP30 Mask */
+#define GPIO_PORT_SET3_SETP31_Pos 31 /*!< GPIO_PORT SET3: SETP31 Position */
+#define GPIO_PORT_SET3_SETP31_Msk (0x01UL << GPIO_PORT_SET3_SETP31_Pos) /*!< GPIO_PORT SET3: SETP31 Mask */
+
+// ------------------------------------- GPIO_PORT_SET4 -----------------------------------------
+#define GPIO_PORT_SET4_SETP0_Pos 0 /*!< GPIO_PORT SET4: SETP0 Position */
+#define GPIO_PORT_SET4_SETP0_Msk (0x01UL << GPIO_PORT_SET4_SETP0_Pos) /*!< GPIO_PORT SET4: SETP0 Mask */
+#define GPIO_PORT_SET4_SETP1_Pos 1 /*!< GPIO_PORT SET4: SETP1 Position */
+#define GPIO_PORT_SET4_SETP1_Msk (0x01UL << GPIO_PORT_SET4_SETP1_Pos) /*!< GPIO_PORT SET4: SETP1 Mask */
+#define GPIO_PORT_SET4_SETP2_Pos 2 /*!< GPIO_PORT SET4: SETP2 Position */
+#define GPIO_PORT_SET4_SETP2_Msk (0x01UL << GPIO_PORT_SET4_SETP2_Pos) /*!< GPIO_PORT SET4: SETP2 Mask */
+#define GPIO_PORT_SET4_SETP3_Pos 3 /*!< GPIO_PORT SET4: SETP3 Position */
+#define GPIO_PORT_SET4_SETP3_Msk (0x01UL << GPIO_PORT_SET4_SETP3_Pos) /*!< GPIO_PORT SET4: SETP3 Mask */
+#define GPIO_PORT_SET4_SETP4_Pos 4 /*!< GPIO_PORT SET4: SETP4 Position */
+#define GPIO_PORT_SET4_SETP4_Msk (0x01UL << GPIO_PORT_SET4_SETP4_Pos) /*!< GPIO_PORT SET4: SETP4 Mask */
+#define GPIO_PORT_SET4_SETP5_Pos 5 /*!< GPIO_PORT SET4: SETP5 Position */
+#define GPIO_PORT_SET4_SETP5_Msk (0x01UL << GPIO_PORT_SET4_SETP5_Pos) /*!< GPIO_PORT SET4: SETP5 Mask */
+#define GPIO_PORT_SET4_SETP6_Pos 6 /*!< GPIO_PORT SET4: SETP6 Position */
+#define GPIO_PORT_SET4_SETP6_Msk (0x01UL << GPIO_PORT_SET4_SETP6_Pos) /*!< GPIO_PORT SET4: SETP6 Mask */
+#define GPIO_PORT_SET4_SETP7_Pos 7 /*!< GPIO_PORT SET4: SETP7 Position */
+#define GPIO_PORT_SET4_SETP7_Msk (0x01UL << GPIO_PORT_SET4_SETP7_Pos) /*!< GPIO_PORT SET4: SETP7 Mask */
+#define GPIO_PORT_SET4_SETP8_Pos 8 /*!< GPIO_PORT SET4: SETP8 Position */
+#define GPIO_PORT_SET4_SETP8_Msk (0x01UL << GPIO_PORT_SET4_SETP8_Pos) /*!< GPIO_PORT SET4: SETP8 Mask */
+#define GPIO_PORT_SET4_SETP9_Pos 9 /*!< GPIO_PORT SET4: SETP9 Position */
+#define GPIO_PORT_SET4_SETP9_Msk (0x01UL << GPIO_PORT_SET4_SETP9_Pos) /*!< GPIO_PORT SET4: SETP9 Mask */
+#define GPIO_PORT_SET4_SETP10_Pos 10 /*!< GPIO_PORT SET4: SETP10 Position */
+#define GPIO_PORT_SET4_SETP10_Msk (0x01UL << GPIO_PORT_SET4_SETP10_Pos) /*!< GPIO_PORT SET4: SETP10 Mask */
+#define GPIO_PORT_SET4_SETP11_Pos 11 /*!< GPIO_PORT SET4: SETP11 Position */
+#define GPIO_PORT_SET4_SETP11_Msk (0x01UL << GPIO_PORT_SET4_SETP11_Pos) /*!< GPIO_PORT SET4: SETP11 Mask */
+#define GPIO_PORT_SET4_SETP12_Pos 12 /*!< GPIO_PORT SET4: SETP12 Position */
+#define GPIO_PORT_SET4_SETP12_Msk (0x01UL << GPIO_PORT_SET4_SETP12_Pos) /*!< GPIO_PORT SET4: SETP12 Mask */
+#define GPIO_PORT_SET4_SETP13_Pos 13 /*!< GPIO_PORT SET4: SETP13 Position */
+#define GPIO_PORT_SET4_SETP13_Msk (0x01UL << GPIO_PORT_SET4_SETP13_Pos) /*!< GPIO_PORT SET4: SETP13 Mask */
+#define GPIO_PORT_SET4_SETP14_Pos 14 /*!< GPIO_PORT SET4: SETP14 Position */
+#define GPIO_PORT_SET4_SETP14_Msk (0x01UL << GPIO_PORT_SET4_SETP14_Pos) /*!< GPIO_PORT SET4: SETP14 Mask */
+#define GPIO_PORT_SET4_SETP15_Pos 15 /*!< GPIO_PORT SET4: SETP15 Position */
+#define GPIO_PORT_SET4_SETP15_Msk (0x01UL << GPIO_PORT_SET4_SETP15_Pos) /*!< GPIO_PORT SET4: SETP15 Mask */
+#define GPIO_PORT_SET4_SETP16_Pos 16 /*!< GPIO_PORT SET4: SETP16 Position */
+#define GPIO_PORT_SET4_SETP16_Msk (0x01UL << GPIO_PORT_SET4_SETP16_Pos) /*!< GPIO_PORT SET4: SETP16 Mask */
+#define GPIO_PORT_SET4_SETP17_Pos 17 /*!< GPIO_PORT SET4: SETP17 Position */
+#define GPIO_PORT_SET4_SETP17_Msk (0x01UL << GPIO_PORT_SET4_SETP17_Pos) /*!< GPIO_PORT SET4: SETP17 Mask */
+#define GPIO_PORT_SET4_SETP18_Pos 18 /*!< GPIO_PORT SET4: SETP18 Position */
+#define GPIO_PORT_SET4_SETP18_Msk (0x01UL << GPIO_PORT_SET4_SETP18_Pos) /*!< GPIO_PORT SET4: SETP18 Mask */
+#define GPIO_PORT_SET4_SETP19_Pos 19 /*!< GPIO_PORT SET4: SETP19 Position */
+#define GPIO_PORT_SET4_SETP19_Msk (0x01UL << GPIO_PORT_SET4_SETP19_Pos) /*!< GPIO_PORT SET4: SETP19 Mask */
+#define GPIO_PORT_SET4_SETP20_Pos 20 /*!< GPIO_PORT SET4: SETP20 Position */
+#define GPIO_PORT_SET4_SETP20_Msk (0x01UL << GPIO_PORT_SET4_SETP20_Pos) /*!< GPIO_PORT SET4: SETP20 Mask */
+#define GPIO_PORT_SET4_SETP21_Pos 21 /*!< GPIO_PORT SET4: SETP21 Position */
+#define GPIO_PORT_SET4_SETP21_Msk (0x01UL << GPIO_PORT_SET4_SETP21_Pos) /*!< GPIO_PORT SET4: SETP21 Mask */
+#define GPIO_PORT_SET4_SETP22_Pos 22 /*!< GPIO_PORT SET4: SETP22 Position */
+#define GPIO_PORT_SET4_SETP22_Msk (0x01UL << GPIO_PORT_SET4_SETP22_Pos) /*!< GPIO_PORT SET4: SETP22 Mask */
+#define GPIO_PORT_SET4_SETP23_Pos 23 /*!< GPIO_PORT SET4: SETP23 Position */
+#define GPIO_PORT_SET4_SETP23_Msk (0x01UL << GPIO_PORT_SET4_SETP23_Pos) /*!< GPIO_PORT SET4: SETP23 Mask */
+#define GPIO_PORT_SET4_SETP24_Pos 24 /*!< GPIO_PORT SET4: SETP24 Position */
+#define GPIO_PORT_SET4_SETP24_Msk (0x01UL << GPIO_PORT_SET4_SETP24_Pos) /*!< GPIO_PORT SET4: SETP24 Mask */
+#define GPIO_PORT_SET4_SETP25_Pos 25 /*!< GPIO_PORT SET4: SETP25 Position */
+#define GPIO_PORT_SET4_SETP25_Msk (0x01UL << GPIO_PORT_SET4_SETP25_Pos) /*!< GPIO_PORT SET4: SETP25 Mask */
+#define GPIO_PORT_SET4_SETP26_Pos 26 /*!< GPIO_PORT SET4: SETP26 Position */
+#define GPIO_PORT_SET4_SETP26_Msk (0x01UL << GPIO_PORT_SET4_SETP26_Pos) /*!< GPIO_PORT SET4: SETP26 Mask */
+#define GPIO_PORT_SET4_SETP27_Pos 27 /*!< GPIO_PORT SET4: SETP27 Position */
+#define GPIO_PORT_SET4_SETP27_Msk (0x01UL << GPIO_PORT_SET4_SETP27_Pos) /*!< GPIO_PORT SET4: SETP27 Mask */
+#define GPIO_PORT_SET4_SETP28_Pos 28 /*!< GPIO_PORT SET4: SETP28 Position */
+#define GPIO_PORT_SET4_SETP28_Msk (0x01UL << GPIO_PORT_SET4_SETP28_Pos) /*!< GPIO_PORT SET4: SETP28 Mask */
+#define GPIO_PORT_SET4_SETP29_Pos 29 /*!< GPIO_PORT SET4: SETP29 Position */
+#define GPIO_PORT_SET4_SETP29_Msk (0x01UL << GPIO_PORT_SET4_SETP29_Pos) /*!< GPIO_PORT SET4: SETP29 Mask */
+#define GPIO_PORT_SET4_SETP30_Pos 30 /*!< GPIO_PORT SET4: SETP30 Position */
+#define GPIO_PORT_SET4_SETP30_Msk (0x01UL << GPIO_PORT_SET4_SETP30_Pos) /*!< GPIO_PORT SET4: SETP30 Mask */
+#define GPIO_PORT_SET4_SETP31_Pos 31 /*!< GPIO_PORT SET4: SETP31 Position */
+#define GPIO_PORT_SET4_SETP31_Msk (0x01UL << GPIO_PORT_SET4_SETP31_Pos) /*!< GPIO_PORT SET4: SETP31 Mask */
+
+// ------------------------------------- GPIO_PORT_SET5 -----------------------------------------
+#define GPIO_PORT_SET5_SETP0_Pos 0 /*!< GPIO_PORT SET5: SETP0 Position */
+#define GPIO_PORT_SET5_SETP0_Msk (0x01UL << GPIO_PORT_SET5_SETP0_Pos) /*!< GPIO_PORT SET5: SETP0 Mask */
+#define GPIO_PORT_SET5_SETP1_Pos 1 /*!< GPIO_PORT SET5: SETP1 Position */
+#define GPIO_PORT_SET5_SETP1_Msk (0x01UL << GPIO_PORT_SET5_SETP1_Pos) /*!< GPIO_PORT SET5: SETP1 Mask */
+#define GPIO_PORT_SET5_SETP2_Pos 2 /*!< GPIO_PORT SET5: SETP2 Position */
+#define GPIO_PORT_SET5_SETP2_Msk (0x01UL << GPIO_PORT_SET5_SETP2_Pos) /*!< GPIO_PORT SET5: SETP2 Mask */
+#define GPIO_PORT_SET5_SETP3_Pos 3 /*!< GPIO_PORT SET5: SETP3 Position */
+#define GPIO_PORT_SET5_SETP3_Msk (0x01UL << GPIO_PORT_SET5_SETP3_Pos) /*!< GPIO_PORT SET5: SETP3 Mask */
+#define GPIO_PORT_SET5_SETP4_Pos 4 /*!< GPIO_PORT SET5: SETP4 Position */
+#define GPIO_PORT_SET5_SETP4_Msk (0x01UL << GPIO_PORT_SET5_SETP4_Pos) /*!< GPIO_PORT SET5: SETP4 Mask */
+#define GPIO_PORT_SET5_SETP5_Pos 5 /*!< GPIO_PORT SET5: SETP5 Position */
+#define GPIO_PORT_SET5_SETP5_Msk (0x01UL << GPIO_PORT_SET5_SETP5_Pos) /*!< GPIO_PORT SET5: SETP5 Mask */
+#define GPIO_PORT_SET5_SETP6_Pos 6 /*!< GPIO_PORT SET5: SETP6 Position */
+#define GPIO_PORT_SET5_SETP6_Msk (0x01UL << GPIO_PORT_SET5_SETP6_Pos) /*!< GPIO_PORT SET5: SETP6 Mask */
+#define GPIO_PORT_SET5_SETP7_Pos 7 /*!< GPIO_PORT SET5: SETP7 Position */
+#define GPIO_PORT_SET5_SETP7_Msk (0x01UL << GPIO_PORT_SET5_SETP7_Pos) /*!< GPIO_PORT SET5: SETP7 Mask */
+#define GPIO_PORT_SET5_SETP8_Pos 8 /*!< GPIO_PORT SET5: SETP8 Position */
+#define GPIO_PORT_SET5_SETP8_Msk (0x01UL << GPIO_PORT_SET5_SETP8_Pos) /*!< GPIO_PORT SET5: SETP8 Mask */
+#define GPIO_PORT_SET5_SETP9_Pos 9 /*!< GPIO_PORT SET5: SETP9 Position */
+#define GPIO_PORT_SET5_SETP9_Msk (0x01UL << GPIO_PORT_SET5_SETP9_Pos) /*!< GPIO_PORT SET5: SETP9 Mask */
+#define GPIO_PORT_SET5_SETP10_Pos 10 /*!< GPIO_PORT SET5: SETP10 Position */
+#define GPIO_PORT_SET5_SETP10_Msk (0x01UL << GPIO_PORT_SET5_SETP10_Pos) /*!< GPIO_PORT SET5: SETP10 Mask */
+#define GPIO_PORT_SET5_SETP11_Pos 11 /*!< GPIO_PORT SET5: SETP11 Position */
+#define GPIO_PORT_SET5_SETP11_Msk (0x01UL << GPIO_PORT_SET5_SETP11_Pos) /*!< GPIO_PORT SET5: SETP11 Mask */
+#define GPIO_PORT_SET5_SETP12_Pos 12 /*!< GPIO_PORT SET5: SETP12 Position */
+#define GPIO_PORT_SET5_SETP12_Msk (0x01UL << GPIO_PORT_SET5_SETP12_Pos) /*!< GPIO_PORT SET5: SETP12 Mask */
+#define GPIO_PORT_SET5_SETP13_Pos 13 /*!< GPIO_PORT SET5: SETP13 Position */
+#define GPIO_PORT_SET5_SETP13_Msk (0x01UL << GPIO_PORT_SET5_SETP13_Pos) /*!< GPIO_PORT SET5: SETP13 Mask */
+#define GPIO_PORT_SET5_SETP14_Pos 14 /*!< GPIO_PORT SET5: SETP14 Position */
+#define GPIO_PORT_SET5_SETP14_Msk (0x01UL << GPIO_PORT_SET5_SETP14_Pos) /*!< GPIO_PORT SET5: SETP14 Mask */
+#define GPIO_PORT_SET5_SETP15_Pos 15 /*!< GPIO_PORT SET5: SETP15 Position */
+#define GPIO_PORT_SET5_SETP15_Msk (0x01UL << GPIO_PORT_SET5_SETP15_Pos) /*!< GPIO_PORT SET5: SETP15 Mask */
+#define GPIO_PORT_SET5_SETP16_Pos 16 /*!< GPIO_PORT SET5: SETP16 Position */
+#define GPIO_PORT_SET5_SETP16_Msk (0x01UL << GPIO_PORT_SET5_SETP16_Pos) /*!< GPIO_PORT SET5: SETP16 Mask */
+#define GPIO_PORT_SET5_SETP17_Pos 17 /*!< GPIO_PORT SET5: SETP17 Position */
+#define GPIO_PORT_SET5_SETP17_Msk (0x01UL << GPIO_PORT_SET5_SETP17_Pos) /*!< GPIO_PORT SET5: SETP17 Mask */
+#define GPIO_PORT_SET5_SETP18_Pos 18 /*!< GPIO_PORT SET5: SETP18 Position */
+#define GPIO_PORT_SET5_SETP18_Msk (0x01UL << GPIO_PORT_SET5_SETP18_Pos) /*!< GPIO_PORT SET5: SETP18 Mask */
+#define GPIO_PORT_SET5_SETP19_Pos 19 /*!< GPIO_PORT SET5: SETP19 Position */
+#define GPIO_PORT_SET5_SETP19_Msk (0x01UL << GPIO_PORT_SET5_SETP19_Pos) /*!< GPIO_PORT SET5: SETP19 Mask */
+#define GPIO_PORT_SET5_SETP20_Pos 20 /*!< GPIO_PORT SET5: SETP20 Position */
+#define GPIO_PORT_SET5_SETP20_Msk (0x01UL << GPIO_PORT_SET5_SETP20_Pos) /*!< GPIO_PORT SET5: SETP20 Mask */
+#define GPIO_PORT_SET5_SETP21_Pos 21 /*!< GPIO_PORT SET5: SETP21 Position */
+#define GPIO_PORT_SET5_SETP21_Msk (0x01UL << GPIO_PORT_SET5_SETP21_Pos) /*!< GPIO_PORT SET5: SETP21 Mask */
+#define GPIO_PORT_SET5_SETP22_Pos 22 /*!< GPIO_PORT SET5: SETP22 Position */
+#define GPIO_PORT_SET5_SETP22_Msk (0x01UL << GPIO_PORT_SET5_SETP22_Pos) /*!< GPIO_PORT SET5: SETP22 Mask */
+#define GPIO_PORT_SET5_SETP23_Pos 23 /*!< GPIO_PORT SET5: SETP23 Position */
+#define GPIO_PORT_SET5_SETP23_Msk (0x01UL << GPIO_PORT_SET5_SETP23_Pos) /*!< GPIO_PORT SET5: SETP23 Mask */
+#define GPIO_PORT_SET5_SETP24_Pos 24 /*!< GPIO_PORT SET5: SETP24 Position */
+#define GPIO_PORT_SET5_SETP24_Msk (0x01UL << GPIO_PORT_SET5_SETP24_Pos) /*!< GPIO_PORT SET5: SETP24 Mask */
+#define GPIO_PORT_SET5_SETP25_Pos 25 /*!< GPIO_PORT SET5: SETP25 Position */
+#define GPIO_PORT_SET5_SETP25_Msk (0x01UL << GPIO_PORT_SET5_SETP25_Pos) /*!< GPIO_PORT SET5: SETP25 Mask */
+#define GPIO_PORT_SET5_SETP26_Pos 26 /*!< GPIO_PORT SET5: SETP26 Position */
+#define GPIO_PORT_SET5_SETP26_Msk (0x01UL << GPIO_PORT_SET5_SETP26_Pos) /*!< GPIO_PORT SET5: SETP26 Mask */
+#define GPIO_PORT_SET5_SETP27_Pos 27 /*!< GPIO_PORT SET5: SETP27 Position */
+#define GPIO_PORT_SET5_SETP27_Msk (0x01UL << GPIO_PORT_SET5_SETP27_Pos) /*!< GPIO_PORT SET5: SETP27 Mask */
+#define GPIO_PORT_SET5_SETP28_Pos 28 /*!< GPIO_PORT SET5: SETP28 Position */
+#define GPIO_PORT_SET5_SETP28_Msk (0x01UL << GPIO_PORT_SET5_SETP28_Pos) /*!< GPIO_PORT SET5: SETP28 Mask */
+#define GPIO_PORT_SET5_SETP29_Pos 29 /*!< GPIO_PORT SET5: SETP29 Position */
+#define GPIO_PORT_SET5_SETP29_Msk (0x01UL << GPIO_PORT_SET5_SETP29_Pos) /*!< GPIO_PORT SET5: SETP29 Mask */
+#define GPIO_PORT_SET5_SETP30_Pos 30 /*!< GPIO_PORT SET5: SETP30 Position */
+#define GPIO_PORT_SET5_SETP30_Msk (0x01UL << GPIO_PORT_SET5_SETP30_Pos) /*!< GPIO_PORT SET5: SETP30 Mask */
+#define GPIO_PORT_SET5_SETP31_Pos 31 /*!< GPIO_PORT SET5: SETP31 Position */
+#define GPIO_PORT_SET5_SETP31_Msk (0x01UL << GPIO_PORT_SET5_SETP31_Pos) /*!< GPIO_PORT SET5: SETP31 Mask */
+
+// ------------------------------------- GPIO_PORT_SET6 -----------------------------------------
+#define GPIO_PORT_SET6_SETP0_Pos 0 /*!< GPIO_PORT SET6: SETP0 Position */
+#define GPIO_PORT_SET6_SETP0_Msk (0x01UL << GPIO_PORT_SET6_SETP0_Pos) /*!< GPIO_PORT SET6: SETP0 Mask */
+#define GPIO_PORT_SET6_SETP1_Pos 1 /*!< GPIO_PORT SET6: SETP1 Position */
+#define GPIO_PORT_SET6_SETP1_Msk (0x01UL << GPIO_PORT_SET6_SETP1_Pos) /*!< GPIO_PORT SET6: SETP1 Mask */
+#define GPIO_PORT_SET6_SETP2_Pos 2 /*!< GPIO_PORT SET6: SETP2 Position */
+#define GPIO_PORT_SET6_SETP2_Msk (0x01UL << GPIO_PORT_SET6_SETP2_Pos) /*!< GPIO_PORT SET6: SETP2 Mask */
+#define GPIO_PORT_SET6_SETP3_Pos 3 /*!< GPIO_PORT SET6: SETP3 Position */
+#define GPIO_PORT_SET6_SETP3_Msk (0x01UL << GPIO_PORT_SET6_SETP3_Pos) /*!< GPIO_PORT SET6: SETP3 Mask */
+#define GPIO_PORT_SET6_SETP4_Pos 4 /*!< GPIO_PORT SET6: SETP4 Position */
+#define GPIO_PORT_SET6_SETP4_Msk (0x01UL << GPIO_PORT_SET6_SETP4_Pos) /*!< GPIO_PORT SET6: SETP4 Mask */
+#define GPIO_PORT_SET6_SETP5_Pos 5 /*!< GPIO_PORT SET6: SETP5 Position */
+#define GPIO_PORT_SET6_SETP5_Msk (0x01UL << GPIO_PORT_SET6_SETP5_Pos) /*!< GPIO_PORT SET6: SETP5 Mask */
+#define GPIO_PORT_SET6_SETP6_Pos 6 /*!< GPIO_PORT SET6: SETP6 Position */
+#define GPIO_PORT_SET6_SETP6_Msk (0x01UL << GPIO_PORT_SET6_SETP6_Pos) /*!< GPIO_PORT SET6: SETP6 Mask */
+#define GPIO_PORT_SET6_SETP7_Pos 7 /*!< GPIO_PORT SET6: SETP7 Position */
+#define GPIO_PORT_SET6_SETP7_Msk (0x01UL << GPIO_PORT_SET6_SETP7_Pos) /*!< GPIO_PORT SET6: SETP7 Mask */
+#define GPIO_PORT_SET6_SETP8_Pos 8 /*!< GPIO_PORT SET6: SETP8 Position */
+#define GPIO_PORT_SET6_SETP8_Msk (0x01UL << GPIO_PORT_SET6_SETP8_Pos) /*!< GPIO_PORT SET6: SETP8 Mask */
+#define GPIO_PORT_SET6_SETP9_Pos 9 /*!< GPIO_PORT SET6: SETP9 Position */
+#define GPIO_PORT_SET6_SETP9_Msk (0x01UL << GPIO_PORT_SET6_SETP9_Pos) /*!< GPIO_PORT SET6: SETP9 Mask */
+#define GPIO_PORT_SET6_SETP10_Pos 10 /*!< GPIO_PORT SET6: SETP10 Position */
+#define GPIO_PORT_SET6_SETP10_Msk (0x01UL << GPIO_PORT_SET6_SETP10_Pos) /*!< GPIO_PORT SET6: SETP10 Mask */
+#define GPIO_PORT_SET6_SETP11_Pos 11 /*!< GPIO_PORT SET6: SETP11 Position */
+#define GPIO_PORT_SET6_SETP11_Msk (0x01UL << GPIO_PORT_SET6_SETP11_Pos) /*!< GPIO_PORT SET6: SETP11 Mask */
+#define GPIO_PORT_SET6_SETP12_Pos 12 /*!< GPIO_PORT SET6: SETP12 Position */
+#define GPIO_PORT_SET6_SETP12_Msk (0x01UL << GPIO_PORT_SET6_SETP12_Pos) /*!< GPIO_PORT SET6: SETP12 Mask */
+#define GPIO_PORT_SET6_SETP13_Pos 13 /*!< GPIO_PORT SET6: SETP13 Position */
+#define GPIO_PORT_SET6_SETP13_Msk (0x01UL << GPIO_PORT_SET6_SETP13_Pos) /*!< GPIO_PORT SET6: SETP13 Mask */
+#define GPIO_PORT_SET6_SETP14_Pos 14 /*!< GPIO_PORT SET6: SETP14 Position */
+#define GPIO_PORT_SET6_SETP14_Msk (0x01UL << GPIO_PORT_SET6_SETP14_Pos) /*!< GPIO_PORT SET6: SETP14 Mask */
+#define GPIO_PORT_SET6_SETP15_Pos 15 /*!< GPIO_PORT SET6: SETP15 Position */
+#define GPIO_PORT_SET6_SETP15_Msk (0x01UL << GPIO_PORT_SET6_SETP15_Pos) /*!< GPIO_PORT SET6: SETP15 Mask */
+#define GPIO_PORT_SET6_SETP16_Pos 16 /*!< GPIO_PORT SET6: SETP16 Position */
+#define GPIO_PORT_SET6_SETP16_Msk (0x01UL << GPIO_PORT_SET6_SETP16_Pos) /*!< GPIO_PORT SET6: SETP16 Mask */
+#define GPIO_PORT_SET6_SETP17_Pos 17 /*!< GPIO_PORT SET6: SETP17 Position */
+#define GPIO_PORT_SET6_SETP17_Msk (0x01UL << GPIO_PORT_SET6_SETP17_Pos) /*!< GPIO_PORT SET6: SETP17 Mask */
+#define GPIO_PORT_SET6_SETP18_Pos 18 /*!< GPIO_PORT SET6: SETP18 Position */
+#define GPIO_PORT_SET6_SETP18_Msk (0x01UL << GPIO_PORT_SET6_SETP18_Pos) /*!< GPIO_PORT SET6: SETP18 Mask */
+#define GPIO_PORT_SET6_SETP19_Pos 19 /*!< GPIO_PORT SET6: SETP19 Position */
+#define GPIO_PORT_SET6_SETP19_Msk (0x01UL << GPIO_PORT_SET6_SETP19_Pos) /*!< GPIO_PORT SET6: SETP19 Mask */
+#define GPIO_PORT_SET6_SETP20_Pos 20 /*!< GPIO_PORT SET6: SETP20 Position */
+#define GPIO_PORT_SET6_SETP20_Msk (0x01UL << GPIO_PORT_SET6_SETP20_Pos) /*!< GPIO_PORT SET6: SETP20 Mask */
+#define GPIO_PORT_SET6_SETP21_Pos 21 /*!< GPIO_PORT SET6: SETP21 Position */
+#define GPIO_PORT_SET6_SETP21_Msk (0x01UL << GPIO_PORT_SET6_SETP21_Pos) /*!< GPIO_PORT SET6: SETP21 Mask */
+#define GPIO_PORT_SET6_SETP22_Pos 22 /*!< GPIO_PORT SET6: SETP22 Position */
+#define GPIO_PORT_SET6_SETP22_Msk (0x01UL << GPIO_PORT_SET6_SETP22_Pos) /*!< GPIO_PORT SET6: SETP22 Mask */
+#define GPIO_PORT_SET6_SETP23_Pos 23 /*!< GPIO_PORT SET6: SETP23 Position */
+#define GPIO_PORT_SET6_SETP23_Msk (0x01UL << GPIO_PORT_SET6_SETP23_Pos) /*!< GPIO_PORT SET6: SETP23 Mask */
+#define GPIO_PORT_SET6_SETP24_Pos 24 /*!< GPIO_PORT SET6: SETP24 Position */
+#define GPIO_PORT_SET6_SETP24_Msk (0x01UL << GPIO_PORT_SET6_SETP24_Pos) /*!< GPIO_PORT SET6: SETP24 Mask */
+#define GPIO_PORT_SET6_SETP25_Pos 25 /*!< GPIO_PORT SET6: SETP25 Position */
+#define GPIO_PORT_SET6_SETP25_Msk (0x01UL << GPIO_PORT_SET6_SETP25_Pos) /*!< GPIO_PORT SET6: SETP25 Mask */
+#define GPIO_PORT_SET6_SETP26_Pos 26 /*!< GPIO_PORT SET6: SETP26 Position */
+#define GPIO_PORT_SET6_SETP26_Msk (0x01UL << GPIO_PORT_SET6_SETP26_Pos) /*!< GPIO_PORT SET6: SETP26 Mask */
+#define GPIO_PORT_SET6_SETP27_Pos 27 /*!< GPIO_PORT SET6: SETP27 Position */
+#define GPIO_PORT_SET6_SETP27_Msk (0x01UL << GPIO_PORT_SET6_SETP27_Pos) /*!< GPIO_PORT SET6: SETP27 Mask */
+#define GPIO_PORT_SET6_SETP28_Pos 28 /*!< GPIO_PORT SET6: SETP28 Position */
+#define GPIO_PORT_SET6_SETP28_Msk (0x01UL << GPIO_PORT_SET6_SETP28_Pos) /*!< GPIO_PORT SET6: SETP28 Mask */
+#define GPIO_PORT_SET6_SETP29_Pos 29 /*!< GPIO_PORT SET6: SETP29 Position */
+#define GPIO_PORT_SET6_SETP29_Msk (0x01UL << GPIO_PORT_SET6_SETP29_Pos) /*!< GPIO_PORT SET6: SETP29 Mask */
+#define GPIO_PORT_SET6_SETP30_Pos 30 /*!< GPIO_PORT SET6: SETP30 Position */
+#define GPIO_PORT_SET6_SETP30_Msk (0x01UL << GPIO_PORT_SET6_SETP30_Pos) /*!< GPIO_PORT SET6: SETP30 Mask */
+#define GPIO_PORT_SET6_SETP31_Pos 31 /*!< GPIO_PORT SET6: SETP31 Position */
+#define GPIO_PORT_SET6_SETP31_Msk (0x01UL << GPIO_PORT_SET6_SETP31_Pos) /*!< GPIO_PORT SET6: SETP31 Mask */
+
+// ------------------------------------- GPIO_PORT_SET7 -----------------------------------------
+#define GPIO_PORT_SET7_SETP0_Pos 0 /*!< GPIO_PORT SET7: SETP0 Position */
+#define GPIO_PORT_SET7_SETP0_Msk (0x01UL << GPIO_PORT_SET7_SETP0_Pos) /*!< GPIO_PORT SET7: SETP0 Mask */
+#define GPIO_PORT_SET7_SETP1_Pos 1 /*!< GPIO_PORT SET7: SETP1 Position */
+#define GPIO_PORT_SET7_SETP1_Msk (0x01UL << GPIO_PORT_SET7_SETP1_Pos) /*!< GPIO_PORT SET7: SETP1 Mask */
+#define GPIO_PORT_SET7_SETP2_Pos 2 /*!< GPIO_PORT SET7: SETP2 Position */
+#define GPIO_PORT_SET7_SETP2_Msk (0x01UL << GPIO_PORT_SET7_SETP2_Pos) /*!< GPIO_PORT SET7: SETP2 Mask */
+#define GPIO_PORT_SET7_SETP3_Pos 3 /*!< GPIO_PORT SET7: SETP3 Position */
+#define GPIO_PORT_SET7_SETP3_Msk (0x01UL << GPIO_PORT_SET7_SETP3_Pos) /*!< GPIO_PORT SET7: SETP3 Mask */
+#define GPIO_PORT_SET7_SETP4_Pos 4 /*!< GPIO_PORT SET7: SETP4 Position */
+#define GPIO_PORT_SET7_SETP4_Msk (0x01UL << GPIO_PORT_SET7_SETP4_Pos) /*!< GPIO_PORT SET7: SETP4 Mask */
+#define GPIO_PORT_SET7_SETP5_Pos 5 /*!< GPIO_PORT SET7: SETP5 Position */
+#define GPIO_PORT_SET7_SETP5_Msk (0x01UL << GPIO_PORT_SET7_SETP5_Pos) /*!< GPIO_PORT SET7: SETP5 Mask */
+#define GPIO_PORT_SET7_SETP6_Pos 6 /*!< GPIO_PORT SET7: SETP6 Position */
+#define GPIO_PORT_SET7_SETP6_Msk (0x01UL << GPIO_PORT_SET7_SETP6_Pos) /*!< GPIO_PORT SET7: SETP6 Mask */
+#define GPIO_PORT_SET7_SETP7_Pos 7 /*!< GPIO_PORT SET7: SETP7 Position */
+#define GPIO_PORT_SET7_SETP7_Msk (0x01UL << GPIO_PORT_SET7_SETP7_Pos) /*!< GPIO_PORT SET7: SETP7 Mask */
+#define GPIO_PORT_SET7_SETP8_Pos 8 /*!< GPIO_PORT SET7: SETP8 Position */
+#define GPIO_PORT_SET7_SETP8_Msk (0x01UL << GPIO_PORT_SET7_SETP8_Pos) /*!< GPIO_PORT SET7: SETP8 Mask */
+#define GPIO_PORT_SET7_SETP9_Pos 9 /*!< GPIO_PORT SET7: SETP9 Position */
+#define GPIO_PORT_SET7_SETP9_Msk (0x01UL << GPIO_PORT_SET7_SETP9_Pos) /*!< GPIO_PORT SET7: SETP9 Mask */
+#define GPIO_PORT_SET7_SETP10_Pos 10 /*!< GPIO_PORT SET7: SETP10 Position */
+#define GPIO_PORT_SET7_SETP10_Msk (0x01UL << GPIO_PORT_SET7_SETP10_Pos) /*!< GPIO_PORT SET7: SETP10 Mask */
+#define GPIO_PORT_SET7_SETP11_Pos 11 /*!< GPIO_PORT SET7: SETP11 Position */
+#define GPIO_PORT_SET7_SETP11_Msk (0x01UL << GPIO_PORT_SET7_SETP11_Pos) /*!< GPIO_PORT SET7: SETP11 Mask */
+#define GPIO_PORT_SET7_SETP12_Pos 12 /*!< GPIO_PORT SET7: SETP12 Position */
+#define GPIO_PORT_SET7_SETP12_Msk (0x01UL << GPIO_PORT_SET7_SETP12_Pos) /*!< GPIO_PORT SET7: SETP12 Mask */
+#define GPIO_PORT_SET7_SETP13_Pos 13 /*!< GPIO_PORT SET7: SETP13 Position */
+#define GPIO_PORT_SET7_SETP13_Msk (0x01UL << GPIO_PORT_SET7_SETP13_Pos) /*!< GPIO_PORT SET7: SETP13 Mask */
+#define GPIO_PORT_SET7_SETP14_Pos 14 /*!< GPIO_PORT SET7: SETP14 Position */
+#define GPIO_PORT_SET7_SETP14_Msk (0x01UL << GPIO_PORT_SET7_SETP14_Pos) /*!< GPIO_PORT SET7: SETP14 Mask */
+#define GPIO_PORT_SET7_SETP15_Pos 15 /*!< GPIO_PORT SET7: SETP15 Position */
+#define GPIO_PORT_SET7_SETP15_Msk (0x01UL << GPIO_PORT_SET7_SETP15_Pos) /*!< GPIO_PORT SET7: SETP15 Mask */
+#define GPIO_PORT_SET7_SETP16_Pos 16 /*!< GPIO_PORT SET7: SETP16 Position */
+#define GPIO_PORT_SET7_SETP16_Msk (0x01UL << GPIO_PORT_SET7_SETP16_Pos) /*!< GPIO_PORT SET7: SETP16 Mask */
+#define GPIO_PORT_SET7_SETP17_Pos 17 /*!< GPIO_PORT SET7: SETP17 Position */
+#define GPIO_PORT_SET7_SETP17_Msk (0x01UL << GPIO_PORT_SET7_SETP17_Pos) /*!< GPIO_PORT SET7: SETP17 Mask */
+#define GPIO_PORT_SET7_SETP18_Pos 18 /*!< GPIO_PORT SET7: SETP18 Position */
+#define GPIO_PORT_SET7_SETP18_Msk (0x01UL << GPIO_PORT_SET7_SETP18_Pos) /*!< GPIO_PORT SET7: SETP18 Mask */
+#define GPIO_PORT_SET7_SETP19_Pos 19 /*!< GPIO_PORT SET7: SETP19 Position */
+#define GPIO_PORT_SET7_SETP19_Msk (0x01UL << GPIO_PORT_SET7_SETP19_Pos) /*!< GPIO_PORT SET7: SETP19 Mask */
+#define GPIO_PORT_SET7_SETP20_Pos 20 /*!< GPIO_PORT SET7: SETP20 Position */
+#define GPIO_PORT_SET7_SETP20_Msk (0x01UL << GPIO_PORT_SET7_SETP20_Pos) /*!< GPIO_PORT SET7: SETP20 Mask */
+#define GPIO_PORT_SET7_SETP21_Pos 21 /*!< GPIO_PORT SET7: SETP21 Position */
+#define GPIO_PORT_SET7_SETP21_Msk (0x01UL << GPIO_PORT_SET7_SETP21_Pos) /*!< GPIO_PORT SET7: SETP21 Mask */
+#define GPIO_PORT_SET7_SETP22_Pos 22 /*!< GPIO_PORT SET7: SETP22 Position */
+#define GPIO_PORT_SET7_SETP22_Msk (0x01UL << GPIO_PORT_SET7_SETP22_Pos) /*!< GPIO_PORT SET7: SETP22 Mask */
+#define GPIO_PORT_SET7_SETP23_Pos 23 /*!< GPIO_PORT SET7: SETP23 Position */
+#define GPIO_PORT_SET7_SETP23_Msk (0x01UL << GPIO_PORT_SET7_SETP23_Pos) /*!< GPIO_PORT SET7: SETP23 Mask */
+#define GPIO_PORT_SET7_SETP24_Pos 24 /*!< GPIO_PORT SET7: SETP24 Position */
+#define GPIO_PORT_SET7_SETP24_Msk (0x01UL << GPIO_PORT_SET7_SETP24_Pos) /*!< GPIO_PORT SET7: SETP24 Mask */
+#define GPIO_PORT_SET7_SETP25_Pos 25 /*!< GPIO_PORT SET7: SETP25 Position */
+#define GPIO_PORT_SET7_SETP25_Msk (0x01UL << GPIO_PORT_SET7_SETP25_Pos) /*!< GPIO_PORT SET7: SETP25 Mask */
+#define GPIO_PORT_SET7_SETP26_Pos 26 /*!< GPIO_PORT SET7: SETP26 Position */
+#define GPIO_PORT_SET7_SETP26_Msk (0x01UL << GPIO_PORT_SET7_SETP26_Pos) /*!< GPIO_PORT SET7: SETP26 Mask */
+#define GPIO_PORT_SET7_SETP27_Pos 27 /*!< GPIO_PORT SET7: SETP27 Position */
+#define GPIO_PORT_SET7_SETP27_Msk (0x01UL << GPIO_PORT_SET7_SETP27_Pos) /*!< GPIO_PORT SET7: SETP27 Mask */
+#define GPIO_PORT_SET7_SETP28_Pos 28 /*!< GPIO_PORT SET7: SETP28 Position */
+#define GPIO_PORT_SET7_SETP28_Msk (0x01UL << GPIO_PORT_SET7_SETP28_Pos) /*!< GPIO_PORT SET7: SETP28 Mask */
+#define GPIO_PORT_SET7_SETP29_Pos 29 /*!< GPIO_PORT SET7: SETP29 Position */
+#define GPIO_PORT_SET7_SETP29_Msk (0x01UL << GPIO_PORT_SET7_SETP29_Pos) /*!< GPIO_PORT SET7: SETP29 Mask */
+#define GPIO_PORT_SET7_SETP30_Pos 30 /*!< GPIO_PORT SET7: SETP30 Position */
+#define GPIO_PORT_SET7_SETP30_Msk (0x01UL << GPIO_PORT_SET7_SETP30_Pos) /*!< GPIO_PORT SET7: SETP30 Mask */
+#define GPIO_PORT_SET7_SETP31_Pos 31 /*!< GPIO_PORT SET7: SETP31 Position */
+#define GPIO_PORT_SET7_SETP31_Msk (0x01UL << GPIO_PORT_SET7_SETP31_Pos) /*!< GPIO_PORT SET7: SETP31 Mask */
+
+// ------------------------------------- GPIO_PORT_CLR0 -----------------------------------------
+#define GPIO_PORT_CLR0_CLRP00_Pos 0 /*!< GPIO_PORT CLR0: CLRP00 Position */
+#define GPIO_PORT_CLR0_CLRP00_Msk (0x01UL << GPIO_PORT_CLR0_CLRP00_Pos) /*!< GPIO_PORT CLR0: CLRP00 Mask */
+#define GPIO_PORT_CLR0_CLRP01_Pos 1 /*!< GPIO_PORT CLR0: CLRP01 Position */
+#define GPIO_PORT_CLR0_CLRP01_Msk (0x01UL << GPIO_PORT_CLR0_CLRP01_Pos) /*!< GPIO_PORT CLR0: CLRP01 Mask */
+#define GPIO_PORT_CLR0_CLRP02_Pos 2 /*!< GPIO_PORT CLR0: CLRP02 Position */
+#define GPIO_PORT_CLR0_CLRP02_Msk (0x01UL << GPIO_PORT_CLR0_CLRP02_Pos) /*!< GPIO_PORT CLR0: CLRP02 Mask */
+#define GPIO_PORT_CLR0_CLRP03_Pos 3 /*!< GPIO_PORT CLR0: CLRP03 Position */
+#define GPIO_PORT_CLR0_CLRP03_Msk (0x01UL << GPIO_PORT_CLR0_CLRP03_Pos) /*!< GPIO_PORT CLR0: CLRP03 Mask */
+#define GPIO_PORT_CLR0_CLRP04_Pos 4 /*!< GPIO_PORT CLR0: CLRP04 Position */
+#define GPIO_PORT_CLR0_CLRP04_Msk (0x01UL << GPIO_PORT_CLR0_CLRP04_Pos) /*!< GPIO_PORT CLR0: CLRP04 Mask */
+#define GPIO_PORT_CLR0_CLRP05_Pos 5 /*!< GPIO_PORT CLR0: CLRP05 Position */
+#define GPIO_PORT_CLR0_CLRP05_Msk (0x01UL << GPIO_PORT_CLR0_CLRP05_Pos) /*!< GPIO_PORT CLR0: CLRP05 Mask */
+#define GPIO_PORT_CLR0_CLRP06_Pos 6 /*!< GPIO_PORT CLR0: CLRP06 Position */
+#define GPIO_PORT_CLR0_CLRP06_Msk (0x01UL << GPIO_PORT_CLR0_CLRP06_Pos) /*!< GPIO_PORT CLR0: CLRP06 Mask */
+#define GPIO_PORT_CLR0_CLRP07_Pos 7 /*!< GPIO_PORT CLR0: CLRP07 Position */
+#define GPIO_PORT_CLR0_CLRP07_Msk (0x01UL << GPIO_PORT_CLR0_CLRP07_Pos) /*!< GPIO_PORT CLR0: CLRP07 Mask */
+#define GPIO_PORT_CLR0_CLRP08_Pos 8 /*!< GPIO_PORT CLR0: CLRP08 Position */
+#define GPIO_PORT_CLR0_CLRP08_Msk (0x01UL << GPIO_PORT_CLR0_CLRP08_Pos) /*!< GPIO_PORT CLR0: CLRP08 Mask */
+#define GPIO_PORT_CLR0_CLRP09_Pos 9 /*!< GPIO_PORT CLR0: CLRP09 Position */
+#define GPIO_PORT_CLR0_CLRP09_Msk (0x01UL << GPIO_PORT_CLR0_CLRP09_Pos) /*!< GPIO_PORT CLR0: CLRP09 Mask */
+#define GPIO_PORT_CLR0_CLRP010_Pos 10 /*!< GPIO_PORT CLR0: CLRP010 Position */
+#define GPIO_PORT_CLR0_CLRP010_Msk (0x01UL << GPIO_PORT_CLR0_CLRP010_Pos) /*!< GPIO_PORT CLR0: CLRP010 Mask */
+#define GPIO_PORT_CLR0_CLRP011_Pos 11 /*!< GPIO_PORT CLR0: CLRP011 Position */
+#define GPIO_PORT_CLR0_CLRP011_Msk (0x01UL << GPIO_PORT_CLR0_CLRP011_Pos) /*!< GPIO_PORT CLR0: CLRP011 Mask */
+#define GPIO_PORT_CLR0_CLRP012_Pos 12 /*!< GPIO_PORT CLR0: CLRP012 Position */
+#define GPIO_PORT_CLR0_CLRP012_Msk (0x01UL << GPIO_PORT_CLR0_CLRP012_Pos) /*!< GPIO_PORT CLR0: CLRP012 Mask */
+#define GPIO_PORT_CLR0_CLRP013_Pos 13 /*!< GPIO_PORT CLR0: CLRP013 Position */
+#define GPIO_PORT_CLR0_CLRP013_Msk (0x01UL << GPIO_PORT_CLR0_CLRP013_Pos) /*!< GPIO_PORT CLR0: CLRP013 Mask */
+#define GPIO_PORT_CLR0_CLRP014_Pos 14 /*!< GPIO_PORT CLR0: CLRP014 Position */
+#define GPIO_PORT_CLR0_CLRP014_Msk (0x01UL << GPIO_PORT_CLR0_CLRP014_Pos) /*!< GPIO_PORT CLR0: CLRP014 Mask */
+#define GPIO_PORT_CLR0_CLRP015_Pos 15 /*!< GPIO_PORT CLR0: CLRP015 Position */
+#define GPIO_PORT_CLR0_CLRP015_Msk (0x01UL << GPIO_PORT_CLR0_CLRP015_Pos) /*!< GPIO_PORT CLR0: CLRP015 Mask */
+#define GPIO_PORT_CLR0_CLRP016_Pos 16 /*!< GPIO_PORT CLR0: CLRP016 Position */
+#define GPIO_PORT_CLR0_CLRP016_Msk (0x01UL << GPIO_PORT_CLR0_CLRP016_Pos) /*!< GPIO_PORT CLR0: CLRP016 Mask */
+#define GPIO_PORT_CLR0_CLRP017_Pos 17 /*!< GPIO_PORT CLR0: CLRP017 Position */
+#define GPIO_PORT_CLR0_CLRP017_Msk (0x01UL << GPIO_PORT_CLR0_CLRP017_Pos) /*!< GPIO_PORT CLR0: CLRP017 Mask */
+#define GPIO_PORT_CLR0_CLRP018_Pos 18 /*!< GPIO_PORT CLR0: CLRP018 Position */
+#define GPIO_PORT_CLR0_CLRP018_Msk (0x01UL << GPIO_PORT_CLR0_CLRP018_Pos) /*!< GPIO_PORT CLR0: CLRP018 Mask */
+#define GPIO_PORT_CLR0_CLRP019_Pos 19 /*!< GPIO_PORT CLR0: CLRP019 Position */
+#define GPIO_PORT_CLR0_CLRP019_Msk (0x01UL << GPIO_PORT_CLR0_CLRP019_Pos) /*!< GPIO_PORT CLR0: CLRP019 Mask */
+#define GPIO_PORT_CLR0_CLRP020_Pos 20 /*!< GPIO_PORT CLR0: CLRP020 Position */
+#define GPIO_PORT_CLR0_CLRP020_Msk (0x01UL << GPIO_PORT_CLR0_CLRP020_Pos) /*!< GPIO_PORT CLR0: CLRP020 Mask */
+#define GPIO_PORT_CLR0_CLRP021_Pos 21 /*!< GPIO_PORT CLR0: CLRP021 Position */
+#define GPIO_PORT_CLR0_CLRP021_Msk (0x01UL << GPIO_PORT_CLR0_CLRP021_Pos) /*!< GPIO_PORT CLR0: CLRP021 Mask */
+#define GPIO_PORT_CLR0_CLRP022_Pos 22 /*!< GPIO_PORT CLR0: CLRP022 Position */
+#define GPIO_PORT_CLR0_CLRP022_Msk (0x01UL << GPIO_PORT_CLR0_CLRP022_Pos) /*!< GPIO_PORT CLR0: CLRP022 Mask */
+#define GPIO_PORT_CLR0_CLRP023_Pos 23 /*!< GPIO_PORT CLR0: CLRP023 Position */
+#define GPIO_PORT_CLR0_CLRP023_Msk (0x01UL << GPIO_PORT_CLR0_CLRP023_Pos) /*!< GPIO_PORT CLR0: CLRP023 Mask */
+#define GPIO_PORT_CLR0_CLRP024_Pos 24 /*!< GPIO_PORT CLR0: CLRP024 Position */
+#define GPIO_PORT_CLR0_CLRP024_Msk (0x01UL << GPIO_PORT_CLR0_CLRP024_Pos) /*!< GPIO_PORT CLR0: CLRP024 Mask */
+#define GPIO_PORT_CLR0_CLRP025_Pos 25 /*!< GPIO_PORT CLR0: CLRP025 Position */
+#define GPIO_PORT_CLR0_CLRP025_Msk (0x01UL << GPIO_PORT_CLR0_CLRP025_Pos) /*!< GPIO_PORT CLR0: CLRP025 Mask */
+#define GPIO_PORT_CLR0_CLRP026_Pos 26 /*!< GPIO_PORT CLR0: CLRP026 Position */
+#define GPIO_PORT_CLR0_CLRP026_Msk (0x01UL << GPIO_PORT_CLR0_CLRP026_Pos) /*!< GPIO_PORT CLR0: CLRP026 Mask */
+#define GPIO_PORT_CLR0_CLRP027_Pos 27 /*!< GPIO_PORT CLR0: CLRP027 Position */
+#define GPIO_PORT_CLR0_CLRP027_Msk (0x01UL << GPIO_PORT_CLR0_CLRP027_Pos) /*!< GPIO_PORT CLR0: CLRP027 Mask */
+#define GPIO_PORT_CLR0_CLRP028_Pos 28 /*!< GPIO_PORT CLR0: CLRP028 Position */
+#define GPIO_PORT_CLR0_CLRP028_Msk (0x01UL << GPIO_PORT_CLR0_CLRP028_Pos) /*!< GPIO_PORT CLR0: CLRP028 Mask */
+#define GPIO_PORT_CLR0_CLRP029_Pos 29 /*!< GPIO_PORT CLR0: CLRP029 Position */
+#define GPIO_PORT_CLR0_CLRP029_Msk (0x01UL << GPIO_PORT_CLR0_CLRP029_Pos) /*!< GPIO_PORT CLR0: CLRP029 Mask */
+#define GPIO_PORT_CLR0_CLRP030_Pos 30 /*!< GPIO_PORT CLR0: CLRP030 Position */
+#define GPIO_PORT_CLR0_CLRP030_Msk (0x01UL << GPIO_PORT_CLR0_CLRP030_Pos) /*!< GPIO_PORT CLR0: CLRP030 Mask */
+#define GPIO_PORT_CLR0_CLRP031_Pos 31 /*!< GPIO_PORT CLR0: CLRP031 Position */
+#define GPIO_PORT_CLR0_CLRP031_Msk (0x01UL << GPIO_PORT_CLR0_CLRP031_Pos) /*!< GPIO_PORT CLR0: CLRP031 Mask */
+
+// ------------------------------------- GPIO_PORT_CLR1 -----------------------------------------
+#define GPIO_PORT_CLR1_CLRP00_Pos 0 /*!< GPIO_PORT CLR1: CLRP00 Position */
+#define GPIO_PORT_CLR1_CLRP00_Msk (0x01UL << GPIO_PORT_CLR1_CLRP00_Pos) /*!< GPIO_PORT CLR1: CLRP00 Mask */
+#define GPIO_PORT_CLR1_CLRP01_Pos 1 /*!< GPIO_PORT CLR1: CLRP01 Position */
+#define GPIO_PORT_CLR1_CLRP01_Msk (0x01UL << GPIO_PORT_CLR1_CLRP01_Pos) /*!< GPIO_PORT CLR1: CLRP01 Mask */
+#define GPIO_PORT_CLR1_CLRP02_Pos 2 /*!< GPIO_PORT CLR1: CLRP02 Position */
+#define GPIO_PORT_CLR1_CLRP02_Msk (0x01UL << GPIO_PORT_CLR1_CLRP02_Pos) /*!< GPIO_PORT CLR1: CLRP02 Mask */
+#define GPIO_PORT_CLR1_CLRP03_Pos 3 /*!< GPIO_PORT CLR1: CLRP03 Position */
+#define GPIO_PORT_CLR1_CLRP03_Msk (0x01UL << GPIO_PORT_CLR1_CLRP03_Pos) /*!< GPIO_PORT CLR1: CLRP03 Mask */
+#define GPIO_PORT_CLR1_CLRP04_Pos 4 /*!< GPIO_PORT CLR1: CLRP04 Position */
+#define GPIO_PORT_CLR1_CLRP04_Msk (0x01UL << GPIO_PORT_CLR1_CLRP04_Pos) /*!< GPIO_PORT CLR1: CLRP04 Mask */
+#define GPIO_PORT_CLR1_CLRP05_Pos 5 /*!< GPIO_PORT CLR1: CLRP05 Position */
+#define GPIO_PORT_CLR1_CLRP05_Msk (0x01UL << GPIO_PORT_CLR1_CLRP05_Pos) /*!< GPIO_PORT CLR1: CLRP05 Mask */
+#define GPIO_PORT_CLR1_CLRP06_Pos 6 /*!< GPIO_PORT CLR1: CLRP06 Position */
+#define GPIO_PORT_CLR1_CLRP06_Msk (0x01UL << GPIO_PORT_CLR1_CLRP06_Pos) /*!< GPIO_PORT CLR1: CLRP06 Mask */
+#define GPIO_PORT_CLR1_CLRP07_Pos 7 /*!< GPIO_PORT CLR1: CLRP07 Position */
+#define GPIO_PORT_CLR1_CLRP07_Msk (0x01UL << GPIO_PORT_CLR1_CLRP07_Pos) /*!< GPIO_PORT CLR1: CLRP07 Mask */
+#define GPIO_PORT_CLR1_CLRP08_Pos 8 /*!< GPIO_PORT CLR1: CLRP08 Position */
+#define GPIO_PORT_CLR1_CLRP08_Msk (0x01UL << GPIO_PORT_CLR1_CLRP08_Pos) /*!< GPIO_PORT CLR1: CLRP08 Mask */
+#define GPIO_PORT_CLR1_CLRP09_Pos 9 /*!< GPIO_PORT CLR1: CLRP09 Position */
+#define GPIO_PORT_CLR1_CLRP09_Msk (0x01UL << GPIO_PORT_CLR1_CLRP09_Pos) /*!< GPIO_PORT CLR1: CLRP09 Mask */
+#define GPIO_PORT_CLR1_CLRP010_Pos 10 /*!< GPIO_PORT CLR1: CLRP010 Position */
+#define GPIO_PORT_CLR1_CLRP010_Msk (0x01UL << GPIO_PORT_CLR1_CLRP010_Pos) /*!< GPIO_PORT CLR1: CLRP010 Mask */
+#define GPIO_PORT_CLR1_CLRP011_Pos 11 /*!< GPIO_PORT CLR1: CLRP011 Position */
+#define GPIO_PORT_CLR1_CLRP011_Msk (0x01UL << GPIO_PORT_CLR1_CLRP011_Pos) /*!< GPIO_PORT CLR1: CLRP011 Mask */
+#define GPIO_PORT_CLR1_CLRP012_Pos 12 /*!< GPIO_PORT CLR1: CLRP012 Position */
+#define GPIO_PORT_CLR1_CLRP012_Msk (0x01UL << GPIO_PORT_CLR1_CLRP012_Pos) /*!< GPIO_PORT CLR1: CLRP012 Mask */
+#define GPIO_PORT_CLR1_CLRP013_Pos 13 /*!< GPIO_PORT CLR1: CLRP013 Position */
+#define GPIO_PORT_CLR1_CLRP013_Msk (0x01UL << GPIO_PORT_CLR1_CLRP013_Pos) /*!< GPIO_PORT CLR1: CLRP013 Mask */
+#define GPIO_PORT_CLR1_CLRP014_Pos 14 /*!< GPIO_PORT CLR1: CLRP014 Position */
+#define GPIO_PORT_CLR1_CLRP014_Msk (0x01UL << GPIO_PORT_CLR1_CLRP014_Pos) /*!< GPIO_PORT CLR1: CLRP014 Mask */
+#define GPIO_PORT_CLR1_CLRP015_Pos 15 /*!< GPIO_PORT CLR1: CLRP015 Position */
+#define GPIO_PORT_CLR1_CLRP015_Msk (0x01UL << GPIO_PORT_CLR1_CLRP015_Pos) /*!< GPIO_PORT CLR1: CLRP015 Mask */
+#define GPIO_PORT_CLR1_CLRP016_Pos 16 /*!< GPIO_PORT CLR1: CLRP016 Position */
+#define GPIO_PORT_CLR1_CLRP016_Msk (0x01UL << GPIO_PORT_CLR1_CLRP016_Pos) /*!< GPIO_PORT CLR1: CLRP016 Mask */
+#define GPIO_PORT_CLR1_CLRP017_Pos 17 /*!< GPIO_PORT CLR1: CLRP017 Position */
+#define GPIO_PORT_CLR1_CLRP017_Msk (0x01UL << GPIO_PORT_CLR1_CLRP017_Pos) /*!< GPIO_PORT CLR1: CLRP017 Mask */
+#define GPIO_PORT_CLR1_CLRP018_Pos 18 /*!< GPIO_PORT CLR1: CLRP018 Position */
+#define GPIO_PORT_CLR1_CLRP018_Msk (0x01UL << GPIO_PORT_CLR1_CLRP018_Pos) /*!< GPIO_PORT CLR1: CLRP018 Mask */
+#define GPIO_PORT_CLR1_CLRP019_Pos 19 /*!< GPIO_PORT CLR1: CLRP019 Position */
+#define GPIO_PORT_CLR1_CLRP019_Msk (0x01UL << GPIO_PORT_CLR1_CLRP019_Pos) /*!< GPIO_PORT CLR1: CLRP019 Mask */
+#define GPIO_PORT_CLR1_CLRP020_Pos 20 /*!< GPIO_PORT CLR1: CLRP020 Position */
+#define GPIO_PORT_CLR1_CLRP020_Msk (0x01UL << GPIO_PORT_CLR1_CLRP020_Pos) /*!< GPIO_PORT CLR1: CLRP020 Mask */
+#define GPIO_PORT_CLR1_CLRP021_Pos 21 /*!< GPIO_PORT CLR1: CLRP021 Position */
+#define GPIO_PORT_CLR1_CLRP021_Msk (0x01UL << GPIO_PORT_CLR1_CLRP021_Pos) /*!< GPIO_PORT CLR1: CLRP021 Mask */
+#define GPIO_PORT_CLR1_CLRP022_Pos 22 /*!< GPIO_PORT CLR1: CLRP022 Position */
+#define GPIO_PORT_CLR1_CLRP022_Msk (0x01UL << GPIO_PORT_CLR1_CLRP022_Pos) /*!< GPIO_PORT CLR1: CLRP022 Mask */
+#define GPIO_PORT_CLR1_CLRP023_Pos 23 /*!< GPIO_PORT CLR1: CLRP023 Position */
+#define GPIO_PORT_CLR1_CLRP023_Msk (0x01UL << GPIO_PORT_CLR1_CLRP023_Pos) /*!< GPIO_PORT CLR1: CLRP023 Mask */
+#define GPIO_PORT_CLR1_CLRP024_Pos 24 /*!< GPIO_PORT CLR1: CLRP024 Position */
+#define GPIO_PORT_CLR1_CLRP024_Msk (0x01UL << GPIO_PORT_CLR1_CLRP024_Pos) /*!< GPIO_PORT CLR1: CLRP024 Mask */
+#define GPIO_PORT_CLR1_CLRP025_Pos 25 /*!< GPIO_PORT CLR1: CLRP025 Position */
+#define GPIO_PORT_CLR1_CLRP025_Msk (0x01UL << GPIO_PORT_CLR1_CLRP025_Pos) /*!< GPIO_PORT CLR1: CLRP025 Mask */
+#define GPIO_PORT_CLR1_CLRP026_Pos 26 /*!< GPIO_PORT CLR1: CLRP026 Position */
+#define GPIO_PORT_CLR1_CLRP026_Msk (0x01UL << GPIO_PORT_CLR1_CLRP026_Pos) /*!< GPIO_PORT CLR1: CLRP026 Mask */
+#define GPIO_PORT_CLR1_CLRP027_Pos 27 /*!< GPIO_PORT CLR1: CLRP027 Position */
+#define GPIO_PORT_CLR1_CLRP027_Msk (0x01UL << GPIO_PORT_CLR1_CLRP027_Pos) /*!< GPIO_PORT CLR1: CLRP027 Mask */
+#define GPIO_PORT_CLR1_CLRP028_Pos 28 /*!< GPIO_PORT CLR1: CLRP028 Position */
+#define GPIO_PORT_CLR1_CLRP028_Msk (0x01UL << GPIO_PORT_CLR1_CLRP028_Pos) /*!< GPIO_PORT CLR1: CLRP028 Mask */
+#define GPIO_PORT_CLR1_CLRP029_Pos 29 /*!< GPIO_PORT CLR1: CLRP029 Position */
+#define GPIO_PORT_CLR1_CLRP029_Msk (0x01UL << GPIO_PORT_CLR1_CLRP029_Pos) /*!< GPIO_PORT CLR1: CLRP029 Mask */
+#define GPIO_PORT_CLR1_CLRP030_Pos 30 /*!< GPIO_PORT CLR1: CLRP030 Position */
+#define GPIO_PORT_CLR1_CLRP030_Msk (0x01UL << GPIO_PORT_CLR1_CLRP030_Pos) /*!< GPIO_PORT CLR1: CLRP030 Mask */
+#define GPIO_PORT_CLR1_CLRP031_Pos 31 /*!< GPIO_PORT CLR1: CLRP031 Position */
+#define GPIO_PORT_CLR1_CLRP031_Msk (0x01UL << GPIO_PORT_CLR1_CLRP031_Pos) /*!< GPIO_PORT CLR1: CLRP031 Mask */
+
+// ------------------------------------- GPIO_PORT_CLR2 -----------------------------------------
+#define GPIO_PORT_CLR2_CLRP00_Pos 0 /*!< GPIO_PORT CLR2: CLRP00 Position */
+#define GPIO_PORT_CLR2_CLRP00_Msk (0x01UL << GPIO_PORT_CLR2_CLRP00_Pos) /*!< GPIO_PORT CLR2: CLRP00 Mask */
+#define GPIO_PORT_CLR2_CLRP01_Pos 1 /*!< GPIO_PORT CLR2: CLRP01 Position */
+#define GPIO_PORT_CLR2_CLRP01_Msk (0x01UL << GPIO_PORT_CLR2_CLRP01_Pos) /*!< GPIO_PORT CLR2: CLRP01 Mask */
+#define GPIO_PORT_CLR2_CLRP02_Pos 2 /*!< GPIO_PORT CLR2: CLRP02 Position */
+#define GPIO_PORT_CLR2_CLRP02_Msk (0x01UL << GPIO_PORT_CLR2_CLRP02_Pos) /*!< GPIO_PORT CLR2: CLRP02 Mask */
+#define GPIO_PORT_CLR2_CLRP03_Pos 3 /*!< GPIO_PORT CLR2: CLRP03 Position */
+#define GPIO_PORT_CLR2_CLRP03_Msk (0x01UL << GPIO_PORT_CLR2_CLRP03_Pos) /*!< GPIO_PORT CLR2: CLRP03 Mask */
+#define GPIO_PORT_CLR2_CLRP04_Pos 4 /*!< GPIO_PORT CLR2: CLRP04 Position */
+#define GPIO_PORT_CLR2_CLRP04_Msk (0x01UL << GPIO_PORT_CLR2_CLRP04_Pos) /*!< GPIO_PORT CLR2: CLRP04 Mask */
+#define GPIO_PORT_CLR2_CLRP05_Pos 5 /*!< GPIO_PORT CLR2: CLRP05 Position */
+#define GPIO_PORT_CLR2_CLRP05_Msk (0x01UL << GPIO_PORT_CLR2_CLRP05_Pos) /*!< GPIO_PORT CLR2: CLRP05 Mask */
+#define GPIO_PORT_CLR2_CLRP06_Pos 6 /*!< GPIO_PORT CLR2: CLRP06 Position */
+#define GPIO_PORT_CLR2_CLRP06_Msk (0x01UL << GPIO_PORT_CLR2_CLRP06_Pos) /*!< GPIO_PORT CLR2: CLRP06 Mask */
+#define GPIO_PORT_CLR2_CLRP07_Pos 7 /*!< GPIO_PORT CLR2: CLRP07 Position */
+#define GPIO_PORT_CLR2_CLRP07_Msk (0x01UL << GPIO_PORT_CLR2_CLRP07_Pos) /*!< GPIO_PORT CLR2: CLRP07 Mask */
+#define GPIO_PORT_CLR2_CLRP08_Pos 8 /*!< GPIO_PORT CLR2: CLRP08 Position */
+#define GPIO_PORT_CLR2_CLRP08_Msk (0x01UL << GPIO_PORT_CLR2_CLRP08_Pos) /*!< GPIO_PORT CLR2: CLRP08 Mask */
+#define GPIO_PORT_CLR2_CLRP09_Pos 9 /*!< GPIO_PORT CLR2: CLRP09 Position */
+#define GPIO_PORT_CLR2_CLRP09_Msk (0x01UL << GPIO_PORT_CLR2_CLRP09_Pos) /*!< GPIO_PORT CLR2: CLRP09 Mask */
+#define GPIO_PORT_CLR2_CLRP010_Pos 10 /*!< GPIO_PORT CLR2: CLRP010 Position */
+#define GPIO_PORT_CLR2_CLRP010_Msk (0x01UL << GPIO_PORT_CLR2_CLRP010_Pos) /*!< GPIO_PORT CLR2: CLRP010 Mask */
+#define GPIO_PORT_CLR2_CLRP011_Pos 11 /*!< GPIO_PORT CLR2: CLRP011 Position */
+#define GPIO_PORT_CLR2_CLRP011_Msk (0x01UL << GPIO_PORT_CLR2_CLRP011_Pos) /*!< GPIO_PORT CLR2: CLRP011 Mask */
+#define GPIO_PORT_CLR2_CLRP012_Pos 12 /*!< GPIO_PORT CLR2: CLRP012 Position */
+#define GPIO_PORT_CLR2_CLRP012_Msk (0x01UL << GPIO_PORT_CLR2_CLRP012_Pos) /*!< GPIO_PORT CLR2: CLRP012 Mask */
+#define GPIO_PORT_CLR2_CLRP013_Pos 13 /*!< GPIO_PORT CLR2: CLRP013 Position */
+#define GPIO_PORT_CLR2_CLRP013_Msk (0x01UL << GPIO_PORT_CLR2_CLRP013_Pos) /*!< GPIO_PORT CLR2: CLRP013 Mask */
+#define GPIO_PORT_CLR2_CLRP014_Pos 14 /*!< GPIO_PORT CLR2: CLRP014 Position */
+#define GPIO_PORT_CLR2_CLRP014_Msk (0x01UL << GPIO_PORT_CLR2_CLRP014_Pos) /*!< GPIO_PORT CLR2: CLRP014 Mask */
+#define GPIO_PORT_CLR2_CLRP015_Pos 15 /*!< GPIO_PORT CLR2: CLRP015 Position */
+#define GPIO_PORT_CLR2_CLRP015_Msk (0x01UL << GPIO_PORT_CLR2_CLRP015_Pos) /*!< GPIO_PORT CLR2: CLRP015 Mask */
+#define GPIO_PORT_CLR2_CLRP016_Pos 16 /*!< GPIO_PORT CLR2: CLRP016 Position */
+#define GPIO_PORT_CLR2_CLRP016_Msk (0x01UL << GPIO_PORT_CLR2_CLRP016_Pos) /*!< GPIO_PORT CLR2: CLRP016 Mask */
+#define GPIO_PORT_CLR2_CLRP017_Pos 17 /*!< GPIO_PORT CLR2: CLRP017 Position */
+#define GPIO_PORT_CLR2_CLRP017_Msk (0x01UL << GPIO_PORT_CLR2_CLRP017_Pos) /*!< GPIO_PORT CLR2: CLRP017 Mask */
+#define GPIO_PORT_CLR2_CLRP018_Pos 18 /*!< GPIO_PORT CLR2: CLRP018 Position */
+#define GPIO_PORT_CLR2_CLRP018_Msk (0x01UL << GPIO_PORT_CLR2_CLRP018_Pos) /*!< GPIO_PORT CLR2: CLRP018 Mask */
+#define GPIO_PORT_CLR2_CLRP019_Pos 19 /*!< GPIO_PORT CLR2: CLRP019 Position */
+#define GPIO_PORT_CLR2_CLRP019_Msk (0x01UL << GPIO_PORT_CLR2_CLRP019_Pos) /*!< GPIO_PORT CLR2: CLRP019 Mask */
+#define GPIO_PORT_CLR2_CLRP020_Pos 20 /*!< GPIO_PORT CLR2: CLRP020 Position */
+#define GPIO_PORT_CLR2_CLRP020_Msk (0x01UL << GPIO_PORT_CLR2_CLRP020_Pos) /*!< GPIO_PORT CLR2: CLRP020 Mask */
+#define GPIO_PORT_CLR2_CLRP021_Pos 21 /*!< GPIO_PORT CLR2: CLRP021 Position */
+#define GPIO_PORT_CLR2_CLRP021_Msk (0x01UL << GPIO_PORT_CLR2_CLRP021_Pos) /*!< GPIO_PORT CLR2: CLRP021 Mask */
+#define GPIO_PORT_CLR2_CLRP022_Pos 22 /*!< GPIO_PORT CLR2: CLRP022 Position */
+#define GPIO_PORT_CLR2_CLRP022_Msk (0x01UL << GPIO_PORT_CLR2_CLRP022_Pos) /*!< GPIO_PORT CLR2: CLRP022 Mask */
+#define GPIO_PORT_CLR2_CLRP023_Pos 23 /*!< GPIO_PORT CLR2: CLRP023 Position */
+#define GPIO_PORT_CLR2_CLRP023_Msk (0x01UL << GPIO_PORT_CLR2_CLRP023_Pos) /*!< GPIO_PORT CLR2: CLRP023 Mask */
+#define GPIO_PORT_CLR2_CLRP024_Pos 24 /*!< GPIO_PORT CLR2: CLRP024 Position */
+#define GPIO_PORT_CLR2_CLRP024_Msk (0x01UL << GPIO_PORT_CLR2_CLRP024_Pos) /*!< GPIO_PORT CLR2: CLRP024 Mask */
+#define GPIO_PORT_CLR2_CLRP025_Pos 25 /*!< GPIO_PORT CLR2: CLRP025 Position */
+#define GPIO_PORT_CLR2_CLRP025_Msk (0x01UL << GPIO_PORT_CLR2_CLRP025_Pos) /*!< GPIO_PORT CLR2: CLRP025 Mask */
+#define GPIO_PORT_CLR2_CLRP026_Pos 26 /*!< GPIO_PORT CLR2: CLRP026 Position */
+#define GPIO_PORT_CLR2_CLRP026_Msk (0x01UL << GPIO_PORT_CLR2_CLRP026_Pos) /*!< GPIO_PORT CLR2: CLRP026 Mask */
+#define GPIO_PORT_CLR2_CLRP027_Pos 27 /*!< GPIO_PORT CLR2: CLRP027 Position */
+#define GPIO_PORT_CLR2_CLRP027_Msk (0x01UL << GPIO_PORT_CLR2_CLRP027_Pos) /*!< GPIO_PORT CLR2: CLRP027 Mask */
+#define GPIO_PORT_CLR2_CLRP028_Pos 28 /*!< GPIO_PORT CLR2: CLRP028 Position */
+#define GPIO_PORT_CLR2_CLRP028_Msk (0x01UL << GPIO_PORT_CLR2_CLRP028_Pos) /*!< GPIO_PORT CLR2: CLRP028 Mask */
+#define GPIO_PORT_CLR2_CLRP029_Pos 29 /*!< GPIO_PORT CLR2: CLRP029 Position */
+#define GPIO_PORT_CLR2_CLRP029_Msk (0x01UL << GPIO_PORT_CLR2_CLRP029_Pos) /*!< GPIO_PORT CLR2: CLRP029 Mask */
+#define GPIO_PORT_CLR2_CLRP030_Pos 30 /*!< GPIO_PORT CLR2: CLRP030 Position */
+#define GPIO_PORT_CLR2_CLRP030_Msk (0x01UL << GPIO_PORT_CLR2_CLRP030_Pos) /*!< GPIO_PORT CLR2: CLRP030 Mask */
+#define GPIO_PORT_CLR2_CLRP031_Pos 31 /*!< GPIO_PORT CLR2: CLRP031 Position */
+#define GPIO_PORT_CLR2_CLRP031_Msk (0x01UL << GPIO_PORT_CLR2_CLRP031_Pos) /*!< GPIO_PORT CLR2: CLRP031 Mask */
+
+// ------------------------------------- GPIO_PORT_CLR3 -----------------------------------------
+#define GPIO_PORT_CLR3_CLRP00_Pos 0 /*!< GPIO_PORT CLR3: CLRP00 Position */
+#define GPIO_PORT_CLR3_CLRP00_Msk (0x01UL << GPIO_PORT_CLR3_CLRP00_Pos) /*!< GPIO_PORT CLR3: CLRP00 Mask */
+#define GPIO_PORT_CLR3_CLRP01_Pos 1 /*!< GPIO_PORT CLR3: CLRP01 Position */
+#define GPIO_PORT_CLR3_CLRP01_Msk (0x01UL << GPIO_PORT_CLR3_CLRP01_Pos) /*!< GPIO_PORT CLR3: CLRP01 Mask */
+#define GPIO_PORT_CLR3_CLRP02_Pos 2 /*!< GPIO_PORT CLR3: CLRP02 Position */
+#define GPIO_PORT_CLR3_CLRP02_Msk (0x01UL << GPIO_PORT_CLR3_CLRP02_Pos) /*!< GPIO_PORT CLR3: CLRP02 Mask */
+#define GPIO_PORT_CLR3_CLRP03_Pos 3 /*!< GPIO_PORT CLR3: CLRP03 Position */
+#define GPIO_PORT_CLR3_CLRP03_Msk (0x01UL << GPIO_PORT_CLR3_CLRP03_Pos) /*!< GPIO_PORT CLR3: CLRP03 Mask */
+#define GPIO_PORT_CLR3_CLRP04_Pos 4 /*!< GPIO_PORT CLR3: CLRP04 Position */
+#define GPIO_PORT_CLR3_CLRP04_Msk (0x01UL << GPIO_PORT_CLR3_CLRP04_Pos) /*!< GPIO_PORT CLR3: CLRP04 Mask */
+#define GPIO_PORT_CLR3_CLRP05_Pos 5 /*!< GPIO_PORT CLR3: CLRP05 Position */
+#define GPIO_PORT_CLR3_CLRP05_Msk (0x01UL << GPIO_PORT_CLR3_CLRP05_Pos) /*!< GPIO_PORT CLR3: CLRP05 Mask */
+#define GPIO_PORT_CLR3_CLRP06_Pos 6 /*!< GPIO_PORT CLR3: CLRP06 Position */
+#define GPIO_PORT_CLR3_CLRP06_Msk (0x01UL << GPIO_PORT_CLR3_CLRP06_Pos) /*!< GPIO_PORT CLR3: CLRP06 Mask */
+#define GPIO_PORT_CLR3_CLRP07_Pos 7 /*!< GPIO_PORT CLR3: CLRP07 Position */
+#define GPIO_PORT_CLR3_CLRP07_Msk (0x01UL << GPIO_PORT_CLR3_CLRP07_Pos) /*!< GPIO_PORT CLR3: CLRP07 Mask */
+#define GPIO_PORT_CLR3_CLRP08_Pos 8 /*!< GPIO_PORT CLR3: CLRP08 Position */
+#define GPIO_PORT_CLR3_CLRP08_Msk (0x01UL << GPIO_PORT_CLR3_CLRP08_Pos) /*!< GPIO_PORT CLR3: CLRP08 Mask */
+#define GPIO_PORT_CLR3_CLRP09_Pos 9 /*!< GPIO_PORT CLR3: CLRP09 Position */
+#define GPIO_PORT_CLR3_CLRP09_Msk (0x01UL << GPIO_PORT_CLR3_CLRP09_Pos) /*!< GPIO_PORT CLR3: CLRP09 Mask */
+#define GPIO_PORT_CLR3_CLRP010_Pos 10 /*!< GPIO_PORT CLR3: CLRP010 Position */
+#define GPIO_PORT_CLR3_CLRP010_Msk (0x01UL << GPIO_PORT_CLR3_CLRP010_Pos) /*!< GPIO_PORT CLR3: CLRP010 Mask */
+#define GPIO_PORT_CLR3_CLRP011_Pos 11 /*!< GPIO_PORT CLR3: CLRP011 Position */
+#define GPIO_PORT_CLR3_CLRP011_Msk (0x01UL << GPIO_PORT_CLR3_CLRP011_Pos) /*!< GPIO_PORT CLR3: CLRP011 Mask */
+#define GPIO_PORT_CLR3_CLRP012_Pos 12 /*!< GPIO_PORT CLR3: CLRP012 Position */
+#define GPIO_PORT_CLR3_CLRP012_Msk (0x01UL << GPIO_PORT_CLR3_CLRP012_Pos) /*!< GPIO_PORT CLR3: CLRP012 Mask */
+#define GPIO_PORT_CLR3_CLRP013_Pos 13 /*!< GPIO_PORT CLR3: CLRP013 Position */
+#define GPIO_PORT_CLR3_CLRP013_Msk (0x01UL << GPIO_PORT_CLR3_CLRP013_Pos) /*!< GPIO_PORT CLR3: CLRP013 Mask */
+#define GPIO_PORT_CLR3_CLRP014_Pos 14 /*!< GPIO_PORT CLR3: CLRP014 Position */
+#define GPIO_PORT_CLR3_CLRP014_Msk (0x01UL << GPIO_PORT_CLR3_CLRP014_Pos) /*!< GPIO_PORT CLR3: CLRP014 Mask */
+#define GPIO_PORT_CLR3_CLRP015_Pos 15 /*!< GPIO_PORT CLR3: CLRP015 Position */
+#define GPIO_PORT_CLR3_CLRP015_Msk (0x01UL << GPIO_PORT_CLR3_CLRP015_Pos) /*!< GPIO_PORT CLR3: CLRP015 Mask */
+#define GPIO_PORT_CLR3_CLRP016_Pos 16 /*!< GPIO_PORT CLR3: CLRP016 Position */
+#define GPIO_PORT_CLR3_CLRP016_Msk (0x01UL << GPIO_PORT_CLR3_CLRP016_Pos) /*!< GPIO_PORT CLR3: CLRP016 Mask */
+#define GPIO_PORT_CLR3_CLRP017_Pos 17 /*!< GPIO_PORT CLR3: CLRP017 Position */
+#define GPIO_PORT_CLR3_CLRP017_Msk (0x01UL << GPIO_PORT_CLR3_CLRP017_Pos) /*!< GPIO_PORT CLR3: CLRP017 Mask */
+#define GPIO_PORT_CLR3_CLRP018_Pos 18 /*!< GPIO_PORT CLR3: CLRP018 Position */
+#define GPIO_PORT_CLR3_CLRP018_Msk (0x01UL << GPIO_PORT_CLR3_CLRP018_Pos) /*!< GPIO_PORT CLR3: CLRP018 Mask */
+#define GPIO_PORT_CLR3_CLRP019_Pos 19 /*!< GPIO_PORT CLR3: CLRP019 Position */
+#define GPIO_PORT_CLR3_CLRP019_Msk (0x01UL << GPIO_PORT_CLR3_CLRP019_Pos) /*!< GPIO_PORT CLR3: CLRP019 Mask */
+#define GPIO_PORT_CLR3_CLRP020_Pos 20 /*!< GPIO_PORT CLR3: CLRP020 Position */
+#define GPIO_PORT_CLR3_CLRP020_Msk (0x01UL << GPIO_PORT_CLR3_CLRP020_Pos) /*!< GPIO_PORT CLR3: CLRP020 Mask */
+#define GPIO_PORT_CLR3_CLRP021_Pos 21 /*!< GPIO_PORT CLR3: CLRP021 Position */
+#define GPIO_PORT_CLR3_CLRP021_Msk (0x01UL << GPIO_PORT_CLR3_CLRP021_Pos) /*!< GPIO_PORT CLR3: CLRP021 Mask */
+#define GPIO_PORT_CLR3_CLRP022_Pos 22 /*!< GPIO_PORT CLR3: CLRP022 Position */
+#define GPIO_PORT_CLR3_CLRP022_Msk (0x01UL << GPIO_PORT_CLR3_CLRP022_Pos) /*!< GPIO_PORT CLR3: CLRP022 Mask */
+#define GPIO_PORT_CLR3_CLRP023_Pos 23 /*!< GPIO_PORT CLR3: CLRP023 Position */
+#define GPIO_PORT_CLR3_CLRP023_Msk (0x01UL << GPIO_PORT_CLR3_CLRP023_Pos) /*!< GPIO_PORT CLR3: CLRP023 Mask */
+#define GPIO_PORT_CLR3_CLRP024_Pos 24 /*!< GPIO_PORT CLR3: CLRP024 Position */
+#define GPIO_PORT_CLR3_CLRP024_Msk (0x01UL << GPIO_PORT_CLR3_CLRP024_Pos) /*!< GPIO_PORT CLR3: CLRP024 Mask */
+#define GPIO_PORT_CLR3_CLRP025_Pos 25 /*!< GPIO_PORT CLR3: CLRP025 Position */
+#define GPIO_PORT_CLR3_CLRP025_Msk (0x01UL << GPIO_PORT_CLR3_CLRP025_Pos) /*!< GPIO_PORT CLR3: CLRP025 Mask */
+#define GPIO_PORT_CLR3_CLRP026_Pos 26 /*!< GPIO_PORT CLR3: CLRP026 Position */
+#define GPIO_PORT_CLR3_CLRP026_Msk (0x01UL << GPIO_PORT_CLR3_CLRP026_Pos) /*!< GPIO_PORT CLR3: CLRP026 Mask */
+#define GPIO_PORT_CLR3_CLRP027_Pos 27 /*!< GPIO_PORT CLR3: CLRP027 Position */
+#define GPIO_PORT_CLR3_CLRP027_Msk (0x01UL << GPIO_PORT_CLR3_CLRP027_Pos) /*!< GPIO_PORT CLR3: CLRP027 Mask */
+#define GPIO_PORT_CLR3_CLRP028_Pos 28 /*!< GPIO_PORT CLR3: CLRP028 Position */
+#define GPIO_PORT_CLR3_CLRP028_Msk (0x01UL << GPIO_PORT_CLR3_CLRP028_Pos) /*!< GPIO_PORT CLR3: CLRP028 Mask */
+#define GPIO_PORT_CLR3_CLRP029_Pos 29 /*!< GPIO_PORT CLR3: CLRP029 Position */
+#define GPIO_PORT_CLR3_CLRP029_Msk (0x01UL << GPIO_PORT_CLR3_CLRP029_Pos) /*!< GPIO_PORT CLR3: CLRP029 Mask */
+#define GPIO_PORT_CLR3_CLRP030_Pos 30 /*!< GPIO_PORT CLR3: CLRP030 Position */
+#define GPIO_PORT_CLR3_CLRP030_Msk (0x01UL << GPIO_PORT_CLR3_CLRP030_Pos) /*!< GPIO_PORT CLR3: CLRP030 Mask */
+#define GPIO_PORT_CLR3_CLRP031_Pos 31 /*!< GPIO_PORT CLR3: CLRP031 Position */
+#define GPIO_PORT_CLR3_CLRP031_Msk (0x01UL << GPIO_PORT_CLR3_CLRP031_Pos) /*!< GPIO_PORT CLR3: CLRP031 Mask */
+
+// ------------------------------------- GPIO_PORT_CLR4 -----------------------------------------
+#define GPIO_PORT_CLR4_CLRP00_Pos 0 /*!< GPIO_PORT CLR4: CLRP00 Position */
+#define GPIO_PORT_CLR4_CLRP00_Msk (0x01UL << GPIO_PORT_CLR4_CLRP00_Pos) /*!< GPIO_PORT CLR4: CLRP00 Mask */
+#define GPIO_PORT_CLR4_CLRP01_Pos 1 /*!< GPIO_PORT CLR4: CLRP01 Position */
+#define GPIO_PORT_CLR4_CLRP01_Msk (0x01UL << GPIO_PORT_CLR4_CLRP01_Pos) /*!< GPIO_PORT CLR4: CLRP01 Mask */
+#define GPIO_PORT_CLR4_CLRP02_Pos 2 /*!< GPIO_PORT CLR4: CLRP02 Position */
+#define GPIO_PORT_CLR4_CLRP02_Msk (0x01UL << GPIO_PORT_CLR4_CLRP02_Pos) /*!< GPIO_PORT CLR4: CLRP02 Mask */
+#define GPIO_PORT_CLR4_CLRP03_Pos 3 /*!< GPIO_PORT CLR4: CLRP03 Position */
+#define GPIO_PORT_CLR4_CLRP03_Msk (0x01UL << GPIO_PORT_CLR4_CLRP03_Pos) /*!< GPIO_PORT CLR4: CLRP03 Mask */
+#define GPIO_PORT_CLR4_CLRP04_Pos 4 /*!< GPIO_PORT CLR4: CLRP04 Position */
+#define GPIO_PORT_CLR4_CLRP04_Msk (0x01UL << GPIO_PORT_CLR4_CLRP04_Pos) /*!< GPIO_PORT CLR4: CLRP04 Mask */
+#define GPIO_PORT_CLR4_CLRP05_Pos 5 /*!< GPIO_PORT CLR4: CLRP05 Position */
+#define GPIO_PORT_CLR4_CLRP05_Msk (0x01UL << GPIO_PORT_CLR4_CLRP05_Pos) /*!< GPIO_PORT CLR4: CLRP05 Mask */
+#define GPIO_PORT_CLR4_CLRP06_Pos 6 /*!< GPIO_PORT CLR4: CLRP06 Position */
+#define GPIO_PORT_CLR4_CLRP06_Msk (0x01UL << GPIO_PORT_CLR4_CLRP06_Pos) /*!< GPIO_PORT CLR4: CLRP06 Mask */
+#define GPIO_PORT_CLR4_CLRP07_Pos 7 /*!< GPIO_PORT CLR4: CLRP07 Position */
+#define GPIO_PORT_CLR4_CLRP07_Msk (0x01UL << GPIO_PORT_CLR4_CLRP07_Pos) /*!< GPIO_PORT CLR4: CLRP07 Mask */
+#define GPIO_PORT_CLR4_CLRP08_Pos 8 /*!< GPIO_PORT CLR4: CLRP08 Position */
+#define GPIO_PORT_CLR4_CLRP08_Msk (0x01UL << GPIO_PORT_CLR4_CLRP08_Pos) /*!< GPIO_PORT CLR4: CLRP08 Mask */
+#define GPIO_PORT_CLR4_CLRP09_Pos 9 /*!< GPIO_PORT CLR4: CLRP09 Position */
+#define GPIO_PORT_CLR4_CLRP09_Msk (0x01UL << GPIO_PORT_CLR4_CLRP09_Pos) /*!< GPIO_PORT CLR4: CLRP09 Mask */
+#define GPIO_PORT_CLR4_CLRP010_Pos 10 /*!< GPIO_PORT CLR4: CLRP010 Position */
+#define GPIO_PORT_CLR4_CLRP010_Msk (0x01UL << GPIO_PORT_CLR4_CLRP010_Pos) /*!< GPIO_PORT CLR4: CLRP010 Mask */
+#define GPIO_PORT_CLR4_CLRP011_Pos 11 /*!< GPIO_PORT CLR4: CLRP011 Position */
+#define GPIO_PORT_CLR4_CLRP011_Msk (0x01UL << GPIO_PORT_CLR4_CLRP011_Pos) /*!< GPIO_PORT CLR4: CLRP011 Mask */
+#define GPIO_PORT_CLR4_CLRP012_Pos 12 /*!< GPIO_PORT CLR4: CLRP012 Position */
+#define GPIO_PORT_CLR4_CLRP012_Msk (0x01UL << GPIO_PORT_CLR4_CLRP012_Pos) /*!< GPIO_PORT CLR4: CLRP012 Mask */
+#define GPIO_PORT_CLR4_CLRP013_Pos 13 /*!< GPIO_PORT CLR4: CLRP013 Position */
+#define GPIO_PORT_CLR4_CLRP013_Msk (0x01UL << GPIO_PORT_CLR4_CLRP013_Pos) /*!< GPIO_PORT CLR4: CLRP013 Mask */
+#define GPIO_PORT_CLR4_CLRP014_Pos 14 /*!< GPIO_PORT CLR4: CLRP014 Position */
+#define GPIO_PORT_CLR4_CLRP014_Msk (0x01UL << GPIO_PORT_CLR4_CLRP014_Pos) /*!< GPIO_PORT CLR4: CLRP014 Mask */
+#define GPIO_PORT_CLR4_CLRP015_Pos 15 /*!< GPIO_PORT CLR4: CLRP015 Position */
+#define GPIO_PORT_CLR4_CLRP015_Msk (0x01UL << GPIO_PORT_CLR4_CLRP015_Pos) /*!< GPIO_PORT CLR4: CLRP015 Mask */
+#define GPIO_PORT_CLR4_CLRP016_Pos 16 /*!< GPIO_PORT CLR4: CLRP016 Position */
+#define GPIO_PORT_CLR4_CLRP016_Msk (0x01UL << GPIO_PORT_CLR4_CLRP016_Pos) /*!< GPIO_PORT CLR4: CLRP016 Mask */
+#define GPIO_PORT_CLR4_CLRP017_Pos 17 /*!< GPIO_PORT CLR4: CLRP017 Position */
+#define GPIO_PORT_CLR4_CLRP017_Msk (0x01UL << GPIO_PORT_CLR4_CLRP017_Pos) /*!< GPIO_PORT CLR4: CLRP017 Mask */
+#define GPIO_PORT_CLR4_CLRP018_Pos 18 /*!< GPIO_PORT CLR4: CLRP018 Position */
+#define GPIO_PORT_CLR4_CLRP018_Msk (0x01UL << GPIO_PORT_CLR4_CLRP018_Pos) /*!< GPIO_PORT CLR4: CLRP018 Mask */
+#define GPIO_PORT_CLR4_CLRP019_Pos 19 /*!< GPIO_PORT CLR4: CLRP019 Position */
+#define GPIO_PORT_CLR4_CLRP019_Msk (0x01UL << GPIO_PORT_CLR4_CLRP019_Pos) /*!< GPIO_PORT CLR4: CLRP019 Mask */
+#define GPIO_PORT_CLR4_CLRP020_Pos 20 /*!< GPIO_PORT CLR4: CLRP020 Position */
+#define GPIO_PORT_CLR4_CLRP020_Msk (0x01UL << GPIO_PORT_CLR4_CLRP020_Pos) /*!< GPIO_PORT CLR4: CLRP020 Mask */
+#define GPIO_PORT_CLR4_CLRP021_Pos 21 /*!< GPIO_PORT CLR4: CLRP021 Position */
+#define GPIO_PORT_CLR4_CLRP021_Msk (0x01UL << GPIO_PORT_CLR4_CLRP021_Pos) /*!< GPIO_PORT CLR4: CLRP021 Mask */
+#define GPIO_PORT_CLR4_CLRP022_Pos 22 /*!< GPIO_PORT CLR4: CLRP022 Position */
+#define GPIO_PORT_CLR4_CLRP022_Msk (0x01UL << GPIO_PORT_CLR4_CLRP022_Pos) /*!< GPIO_PORT CLR4: CLRP022 Mask */
+#define GPIO_PORT_CLR4_CLRP023_Pos 23 /*!< GPIO_PORT CLR4: CLRP023 Position */
+#define GPIO_PORT_CLR4_CLRP023_Msk (0x01UL << GPIO_PORT_CLR4_CLRP023_Pos) /*!< GPIO_PORT CLR4: CLRP023 Mask */
+#define GPIO_PORT_CLR4_CLRP024_Pos 24 /*!< GPIO_PORT CLR4: CLRP024 Position */
+#define GPIO_PORT_CLR4_CLRP024_Msk (0x01UL << GPIO_PORT_CLR4_CLRP024_Pos) /*!< GPIO_PORT CLR4: CLRP024 Mask */
+#define GPIO_PORT_CLR4_CLRP025_Pos 25 /*!< GPIO_PORT CLR4: CLRP025 Position */
+#define GPIO_PORT_CLR4_CLRP025_Msk (0x01UL << GPIO_PORT_CLR4_CLRP025_Pos) /*!< GPIO_PORT CLR4: CLRP025 Mask */
+#define GPIO_PORT_CLR4_CLRP026_Pos 26 /*!< GPIO_PORT CLR4: CLRP026 Position */
+#define GPIO_PORT_CLR4_CLRP026_Msk (0x01UL << GPIO_PORT_CLR4_CLRP026_Pos) /*!< GPIO_PORT CLR4: CLRP026 Mask */
+#define GPIO_PORT_CLR4_CLRP027_Pos 27 /*!< GPIO_PORT CLR4: CLRP027 Position */
+#define GPIO_PORT_CLR4_CLRP027_Msk (0x01UL << GPIO_PORT_CLR4_CLRP027_Pos) /*!< GPIO_PORT CLR4: CLRP027 Mask */
+#define GPIO_PORT_CLR4_CLRP028_Pos 28 /*!< GPIO_PORT CLR4: CLRP028 Position */
+#define GPIO_PORT_CLR4_CLRP028_Msk (0x01UL << GPIO_PORT_CLR4_CLRP028_Pos) /*!< GPIO_PORT CLR4: CLRP028 Mask */
+#define GPIO_PORT_CLR4_CLRP029_Pos 29 /*!< GPIO_PORT CLR4: CLRP029 Position */
+#define GPIO_PORT_CLR4_CLRP029_Msk (0x01UL << GPIO_PORT_CLR4_CLRP029_Pos) /*!< GPIO_PORT CLR4: CLRP029 Mask */
+#define GPIO_PORT_CLR4_CLRP030_Pos 30 /*!< GPIO_PORT CLR4: CLRP030 Position */
+#define GPIO_PORT_CLR4_CLRP030_Msk (0x01UL << GPIO_PORT_CLR4_CLRP030_Pos) /*!< GPIO_PORT CLR4: CLRP030 Mask */
+#define GPIO_PORT_CLR4_CLRP031_Pos 31 /*!< GPIO_PORT CLR4: CLRP031 Position */
+#define GPIO_PORT_CLR4_CLRP031_Msk (0x01UL << GPIO_PORT_CLR4_CLRP031_Pos) /*!< GPIO_PORT CLR4: CLRP031 Mask */
+
+// ------------------------------------- GPIO_PORT_CLR5 -----------------------------------------
+#define GPIO_PORT_CLR5_CLRP00_Pos 0 /*!< GPIO_PORT CLR5: CLRP00 Position */
+#define GPIO_PORT_CLR5_CLRP00_Msk (0x01UL << GPIO_PORT_CLR5_CLRP00_Pos) /*!< GPIO_PORT CLR5: CLRP00 Mask */
+#define GPIO_PORT_CLR5_CLRP01_Pos 1 /*!< GPIO_PORT CLR5: CLRP01 Position */
+#define GPIO_PORT_CLR5_CLRP01_Msk (0x01UL << GPIO_PORT_CLR5_CLRP01_Pos) /*!< GPIO_PORT CLR5: CLRP01 Mask */
+#define GPIO_PORT_CLR5_CLRP02_Pos 2 /*!< GPIO_PORT CLR5: CLRP02 Position */
+#define GPIO_PORT_CLR5_CLRP02_Msk (0x01UL << GPIO_PORT_CLR5_CLRP02_Pos) /*!< GPIO_PORT CLR5: CLRP02 Mask */
+#define GPIO_PORT_CLR5_CLRP03_Pos 3 /*!< GPIO_PORT CLR5: CLRP03 Position */
+#define GPIO_PORT_CLR5_CLRP03_Msk (0x01UL << GPIO_PORT_CLR5_CLRP03_Pos) /*!< GPIO_PORT CLR5: CLRP03 Mask */
+#define GPIO_PORT_CLR5_CLRP04_Pos 4 /*!< GPIO_PORT CLR5: CLRP04 Position */
+#define GPIO_PORT_CLR5_CLRP04_Msk (0x01UL << GPIO_PORT_CLR5_CLRP04_Pos) /*!< GPIO_PORT CLR5: CLRP04 Mask */
+#define GPIO_PORT_CLR5_CLRP05_Pos 5 /*!< GPIO_PORT CLR5: CLRP05 Position */
+#define GPIO_PORT_CLR5_CLRP05_Msk (0x01UL << GPIO_PORT_CLR5_CLRP05_Pos) /*!< GPIO_PORT CLR5: CLRP05 Mask */
+#define GPIO_PORT_CLR5_CLRP06_Pos 6 /*!< GPIO_PORT CLR5: CLRP06 Position */
+#define GPIO_PORT_CLR5_CLRP06_Msk (0x01UL << GPIO_PORT_CLR5_CLRP06_Pos) /*!< GPIO_PORT CLR5: CLRP06 Mask */
+#define GPIO_PORT_CLR5_CLRP07_Pos 7 /*!< GPIO_PORT CLR5: CLRP07 Position */
+#define GPIO_PORT_CLR5_CLRP07_Msk (0x01UL << GPIO_PORT_CLR5_CLRP07_Pos) /*!< GPIO_PORT CLR5: CLRP07 Mask */
+#define GPIO_PORT_CLR5_CLRP08_Pos 8 /*!< GPIO_PORT CLR5: CLRP08 Position */
+#define GPIO_PORT_CLR5_CLRP08_Msk (0x01UL << GPIO_PORT_CLR5_CLRP08_Pos) /*!< GPIO_PORT CLR5: CLRP08 Mask */
+#define GPIO_PORT_CLR5_CLRP09_Pos 9 /*!< GPIO_PORT CLR5: CLRP09 Position */
+#define GPIO_PORT_CLR5_CLRP09_Msk (0x01UL << GPIO_PORT_CLR5_CLRP09_Pos) /*!< GPIO_PORT CLR5: CLRP09 Mask */
+#define GPIO_PORT_CLR5_CLRP010_Pos 10 /*!< GPIO_PORT CLR5: CLRP010 Position */
+#define GPIO_PORT_CLR5_CLRP010_Msk (0x01UL << GPIO_PORT_CLR5_CLRP010_Pos) /*!< GPIO_PORT CLR5: CLRP010 Mask */
+#define GPIO_PORT_CLR5_CLRP011_Pos 11 /*!< GPIO_PORT CLR5: CLRP011 Position */
+#define GPIO_PORT_CLR5_CLRP011_Msk (0x01UL << GPIO_PORT_CLR5_CLRP011_Pos) /*!< GPIO_PORT CLR5: CLRP011 Mask */
+#define GPIO_PORT_CLR5_CLRP012_Pos 12 /*!< GPIO_PORT CLR5: CLRP012 Position */
+#define GPIO_PORT_CLR5_CLRP012_Msk (0x01UL << GPIO_PORT_CLR5_CLRP012_Pos) /*!< GPIO_PORT CLR5: CLRP012 Mask */
+#define GPIO_PORT_CLR5_CLRP013_Pos 13 /*!< GPIO_PORT CLR5: CLRP013 Position */
+#define GPIO_PORT_CLR5_CLRP013_Msk (0x01UL << GPIO_PORT_CLR5_CLRP013_Pos) /*!< GPIO_PORT CLR5: CLRP013 Mask */
+#define GPIO_PORT_CLR5_CLRP014_Pos 14 /*!< GPIO_PORT CLR5: CLRP014 Position */
+#define GPIO_PORT_CLR5_CLRP014_Msk (0x01UL << GPIO_PORT_CLR5_CLRP014_Pos) /*!< GPIO_PORT CLR5: CLRP014 Mask */
+#define GPIO_PORT_CLR5_CLRP015_Pos 15 /*!< GPIO_PORT CLR5: CLRP015 Position */
+#define GPIO_PORT_CLR5_CLRP015_Msk (0x01UL << GPIO_PORT_CLR5_CLRP015_Pos) /*!< GPIO_PORT CLR5: CLRP015 Mask */
+#define GPIO_PORT_CLR5_CLRP016_Pos 16 /*!< GPIO_PORT CLR5: CLRP016 Position */
+#define GPIO_PORT_CLR5_CLRP016_Msk (0x01UL << GPIO_PORT_CLR5_CLRP016_Pos) /*!< GPIO_PORT CLR5: CLRP016 Mask */
+#define GPIO_PORT_CLR5_CLRP017_Pos 17 /*!< GPIO_PORT CLR5: CLRP017 Position */
+#define GPIO_PORT_CLR5_CLRP017_Msk (0x01UL << GPIO_PORT_CLR5_CLRP017_Pos) /*!< GPIO_PORT CLR5: CLRP017 Mask */
+#define GPIO_PORT_CLR5_CLRP018_Pos 18 /*!< GPIO_PORT CLR5: CLRP018 Position */
+#define GPIO_PORT_CLR5_CLRP018_Msk (0x01UL << GPIO_PORT_CLR5_CLRP018_Pos) /*!< GPIO_PORT CLR5: CLRP018 Mask */
+#define GPIO_PORT_CLR5_CLRP019_Pos 19 /*!< GPIO_PORT CLR5: CLRP019 Position */
+#define GPIO_PORT_CLR5_CLRP019_Msk (0x01UL << GPIO_PORT_CLR5_CLRP019_Pos) /*!< GPIO_PORT CLR5: CLRP019 Mask */
+#define GPIO_PORT_CLR5_CLRP020_Pos 20 /*!< GPIO_PORT CLR5: CLRP020 Position */
+#define GPIO_PORT_CLR5_CLRP020_Msk (0x01UL << GPIO_PORT_CLR5_CLRP020_Pos) /*!< GPIO_PORT CLR5: CLRP020 Mask */
+#define GPIO_PORT_CLR5_CLRP021_Pos 21 /*!< GPIO_PORT CLR5: CLRP021 Position */
+#define GPIO_PORT_CLR5_CLRP021_Msk (0x01UL << GPIO_PORT_CLR5_CLRP021_Pos) /*!< GPIO_PORT CLR5: CLRP021 Mask */
+#define GPIO_PORT_CLR5_CLRP022_Pos 22 /*!< GPIO_PORT CLR5: CLRP022 Position */
+#define GPIO_PORT_CLR5_CLRP022_Msk (0x01UL << GPIO_PORT_CLR5_CLRP022_Pos) /*!< GPIO_PORT CLR5: CLRP022 Mask */
+#define GPIO_PORT_CLR5_CLRP023_Pos 23 /*!< GPIO_PORT CLR5: CLRP023 Position */
+#define GPIO_PORT_CLR5_CLRP023_Msk (0x01UL << GPIO_PORT_CLR5_CLRP023_Pos) /*!< GPIO_PORT CLR5: CLRP023 Mask */
+#define GPIO_PORT_CLR5_CLRP024_Pos 24 /*!< GPIO_PORT CLR5: CLRP024 Position */
+#define GPIO_PORT_CLR5_CLRP024_Msk (0x01UL << GPIO_PORT_CLR5_CLRP024_Pos) /*!< GPIO_PORT CLR5: CLRP024 Mask */
+#define GPIO_PORT_CLR5_CLRP025_Pos 25 /*!< GPIO_PORT CLR5: CLRP025 Position */
+#define GPIO_PORT_CLR5_CLRP025_Msk (0x01UL << GPIO_PORT_CLR5_CLRP025_Pos) /*!< GPIO_PORT CLR5: CLRP025 Mask */
+#define GPIO_PORT_CLR5_CLRP026_Pos 26 /*!< GPIO_PORT CLR5: CLRP026 Position */
+#define GPIO_PORT_CLR5_CLRP026_Msk (0x01UL << GPIO_PORT_CLR5_CLRP026_Pos) /*!< GPIO_PORT CLR5: CLRP026 Mask */
+#define GPIO_PORT_CLR5_CLRP027_Pos 27 /*!< GPIO_PORT CLR5: CLRP027 Position */
+#define GPIO_PORT_CLR5_CLRP027_Msk (0x01UL << GPIO_PORT_CLR5_CLRP027_Pos) /*!< GPIO_PORT CLR5: CLRP027 Mask */
+#define GPIO_PORT_CLR5_CLRP028_Pos 28 /*!< GPIO_PORT CLR5: CLRP028 Position */
+#define GPIO_PORT_CLR5_CLRP028_Msk (0x01UL << GPIO_PORT_CLR5_CLRP028_Pos) /*!< GPIO_PORT CLR5: CLRP028 Mask */
+#define GPIO_PORT_CLR5_CLRP029_Pos 29 /*!< GPIO_PORT CLR5: CLRP029 Position */
+#define GPIO_PORT_CLR5_CLRP029_Msk (0x01UL << GPIO_PORT_CLR5_CLRP029_Pos) /*!< GPIO_PORT CLR5: CLRP029 Mask */
+#define GPIO_PORT_CLR5_CLRP030_Pos 30 /*!< GPIO_PORT CLR5: CLRP030 Position */
+#define GPIO_PORT_CLR5_CLRP030_Msk (0x01UL << GPIO_PORT_CLR5_CLRP030_Pos) /*!< GPIO_PORT CLR5: CLRP030 Mask */
+#define GPIO_PORT_CLR5_CLRP031_Pos 31 /*!< GPIO_PORT CLR5: CLRP031 Position */
+#define GPIO_PORT_CLR5_CLRP031_Msk (0x01UL << GPIO_PORT_CLR5_CLRP031_Pos) /*!< GPIO_PORT CLR5: CLRP031 Mask */
+
+// ------------------------------------- GPIO_PORT_CLR6 -----------------------------------------
+#define GPIO_PORT_CLR6_CLRP00_Pos 0 /*!< GPIO_PORT CLR6: CLRP00 Position */
+#define GPIO_PORT_CLR6_CLRP00_Msk (0x01UL << GPIO_PORT_CLR6_CLRP00_Pos) /*!< GPIO_PORT CLR6: CLRP00 Mask */
+#define GPIO_PORT_CLR6_CLRP01_Pos 1 /*!< GPIO_PORT CLR6: CLRP01 Position */
+#define GPIO_PORT_CLR6_CLRP01_Msk (0x01UL << GPIO_PORT_CLR6_CLRP01_Pos) /*!< GPIO_PORT CLR6: CLRP01 Mask */
+#define GPIO_PORT_CLR6_CLRP02_Pos 2 /*!< GPIO_PORT CLR6: CLRP02 Position */
+#define GPIO_PORT_CLR6_CLRP02_Msk (0x01UL << GPIO_PORT_CLR6_CLRP02_Pos) /*!< GPIO_PORT CLR6: CLRP02 Mask */
+#define GPIO_PORT_CLR6_CLRP03_Pos 3 /*!< GPIO_PORT CLR6: CLRP03 Position */
+#define GPIO_PORT_CLR6_CLRP03_Msk (0x01UL << GPIO_PORT_CLR6_CLRP03_Pos) /*!< GPIO_PORT CLR6: CLRP03 Mask */
+#define GPIO_PORT_CLR6_CLRP04_Pos 4 /*!< GPIO_PORT CLR6: CLRP04 Position */
+#define GPIO_PORT_CLR6_CLRP04_Msk (0x01UL << GPIO_PORT_CLR6_CLRP04_Pos) /*!< GPIO_PORT CLR6: CLRP04 Mask */
+#define GPIO_PORT_CLR6_CLRP05_Pos 5 /*!< GPIO_PORT CLR6: CLRP05 Position */
+#define GPIO_PORT_CLR6_CLRP05_Msk (0x01UL << GPIO_PORT_CLR6_CLRP05_Pos) /*!< GPIO_PORT CLR6: CLRP05 Mask */
+#define GPIO_PORT_CLR6_CLRP06_Pos 6 /*!< GPIO_PORT CLR6: CLRP06 Position */
+#define GPIO_PORT_CLR6_CLRP06_Msk (0x01UL << GPIO_PORT_CLR6_CLRP06_Pos) /*!< GPIO_PORT CLR6: CLRP06 Mask */
+#define GPIO_PORT_CLR6_CLRP07_Pos 7 /*!< GPIO_PORT CLR6: CLRP07 Position */
+#define GPIO_PORT_CLR6_CLRP07_Msk (0x01UL << GPIO_PORT_CLR6_CLRP07_Pos) /*!< GPIO_PORT CLR6: CLRP07 Mask */
+#define GPIO_PORT_CLR6_CLRP08_Pos 8 /*!< GPIO_PORT CLR6: CLRP08 Position */
+#define GPIO_PORT_CLR6_CLRP08_Msk (0x01UL << GPIO_PORT_CLR6_CLRP08_Pos) /*!< GPIO_PORT CLR6: CLRP08 Mask */
+#define GPIO_PORT_CLR6_CLRP09_Pos 9 /*!< GPIO_PORT CLR6: CLRP09 Position */
+#define GPIO_PORT_CLR6_CLRP09_Msk (0x01UL << GPIO_PORT_CLR6_CLRP09_Pos) /*!< GPIO_PORT CLR6: CLRP09 Mask */
+#define GPIO_PORT_CLR6_CLRP010_Pos 10 /*!< GPIO_PORT CLR6: CLRP010 Position */
+#define GPIO_PORT_CLR6_CLRP010_Msk (0x01UL << GPIO_PORT_CLR6_CLRP010_Pos) /*!< GPIO_PORT CLR6: CLRP010 Mask */
+#define GPIO_PORT_CLR6_CLRP011_Pos 11 /*!< GPIO_PORT CLR6: CLRP011 Position */
+#define GPIO_PORT_CLR6_CLRP011_Msk (0x01UL << GPIO_PORT_CLR6_CLRP011_Pos) /*!< GPIO_PORT CLR6: CLRP011 Mask */
+#define GPIO_PORT_CLR6_CLRP012_Pos 12 /*!< GPIO_PORT CLR6: CLRP012 Position */
+#define GPIO_PORT_CLR6_CLRP012_Msk (0x01UL << GPIO_PORT_CLR6_CLRP012_Pos) /*!< GPIO_PORT CLR6: CLRP012 Mask */
+#define GPIO_PORT_CLR6_CLRP013_Pos 13 /*!< GPIO_PORT CLR6: CLRP013 Position */
+#define GPIO_PORT_CLR6_CLRP013_Msk (0x01UL << GPIO_PORT_CLR6_CLRP013_Pos) /*!< GPIO_PORT CLR6: CLRP013 Mask */
+#define GPIO_PORT_CLR6_CLRP014_Pos 14 /*!< GPIO_PORT CLR6: CLRP014 Position */
+#define GPIO_PORT_CLR6_CLRP014_Msk (0x01UL << GPIO_PORT_CLR6_CLRP014_Pos) /*!< GPIO_PORT CLR6: CLRP014 Mask */
+#define GPIO_PORT_CLR6_CLRP015_Pos 15 /*!< GPIO_PORT CLR6: CLRP015 Position */
+#define GPIO_PORT_CLR6_CLRP015_Msk (0x01UL << GPIO_PORT_CLR6_CLRP015_Pos) /*!< GPIO_PORT CLR6: CLRP015 Mask */
+#define GPIO_PORT_CLR6_CLRP016_Pos 16 /*!< GPIO_PORT CLR6: CLRP016 Position */
+#define GPIO_PORT_CLR6_CLRP016_Msk (0x01UL << GPIO_PORT_CLR6_CLRP016_Pos) /*!< GPIO_PORT CLR6: CLRP016 Mask */
+#define GPIO_PORT_CLR6_CLRP017_Pos 17 /*!< GPIO_PORT CLR6: CLRP017 Position */
+#define GPIO_PORT_CLR6_CLRP017_Msk (0x01UL << GPIO_PORT_CLR6_CLRP017_Pos) /*!< GPIO_PORT CLR6: CLRP017 Mask */
+#define GPIO_PORT_CLR6_CLRP018_Pos 18 /*!< GPIO_PORT CLR6: CLRP018 Position */
+#define GPIO_PORT_CLR6_CLRP018_Msk (0x01UL << GPIO_PORT_CLR6_CLRP018_Pos) /*!< GPIO_PORT CLR6: CLRP018 Mask */
+#define GPIO_PORT_CLR6_CLRP019_Pos 19 /*!< GPIO_PORT CLR6: CLRP019 Position */
+#define GPIO_PORT_CLR6_CLRP019_Msk (0x01UL << GPIO_PORT_CLR6_CLRP019_Pos) /*!< GPIO_PORT CLR6: CLRP019 Mask */
+#define GPIO_PORT_CLR6_CLRP020_Pos 20 /*!< GPIO_PORT CLR6: CLRP020 Position */
+#define GPIO_PORT_CLR6_CLRP020_Msk (0x01UL << GPIO_PORT_CLR6_CLRP020_Pos) /*!< GPIO_PORT CLR6: CLRP020 Mask */
+#define GPIO_PORT_CLR6_CLRP021_Pos 21 /*!< GPIO_PORT CLR6: CLRP021 Position */
+#define GPIO_PORT_CLR6_CLRP021_Msk (0x01UL << GPIO_PORT_CLR6_CLRP021_Pos) /*!< GPIO_PORT CLR6: CLRP021 Mask */
+#define GPIO_PORT_CLR6_CLRP022_Pos 22 /*!< GPIO_PORT CLR6: CLRP022 Position */
+#define GPIO_PORT_CLR6_CLRP022_Msk (0x01UL << GPIO_PORT_CLR6_CLRP022_Pos) /*!< GPIO_PORT CLR6: CLRP022 Mask */
+#define GPIO_PORT_CLR6_CLRP023_Pos 23 /*!< GPIO_PORT CLR6: CLRP023 Position */
+#define GPIO_PORT_CLR6_CLRP023_Msk (0x01UL << GPIO_PORT_CLR6_CLRP023_Pos) /*!< GPIO_PORT CLR6: CLRP023 Mask */
+#define GPIO_PORT_CLR6_CLRP024_Pos 24 /*!< GPIO_PORT CLR6: CLRP024 Position */
+#define GPIO_PORT_CLR6_CLRP024_Msk (0x01UL << GPIO_PORT_CLR6_CLRP024_Pos) /*!< GPIO_PORT CLR6: CLRP024 Mask */
+#define GPIO_PORT_CLR6_CLRP025_Pos 25 /*!< GPIO_PORT CLR6: CLRP025 Position */
+#define GPIO_PORT_CLR6_CLRP025_Msk (0x01UL << GPIO_PORT_CLR6_CLRP025_Pos) /*!< GPIO_PORT CLR6: CLRP025 Mask */
+#define GPIO_PORT_CLR6_CLRP026_Pos 26 /*!< GPIO_PORT CLR6: CLRP026 Position */
+#define GPIO_PORT_CLR6_CLRP026_Msk (0x01UL << GPIO_PORT_CLR6_CLRP026_Pos) /*!< GPIO_PORT CLR6: CLRP026 Mask */
+#define GPIO_PORT_CLR6_CLRP027_Pos 27 /*!< GPIO_PORT CLR6: CLRP027 Position */
+#define GPIO_PORT_CLR6_CLRP027_Msk (0x01UL << GPIO_PORT_CLR6_CLRP027_Pos) /*!< GPIO_PORT CLR6: CLRP027 Mask */
+#define GPIO_PORT_CLR6_CLRP028_Pos 28 /*!< GPIO_PORT CLR6: CLRP028 Position */
+#define GPIO_PORT_CLR6_CLRP028_Msk (0x01UL << GPIO_PORT_CLR6_CLRP028_Pos) /*!< GPIO_PORT CLR6: CLRP028 Mask */
+#define GPIO_PORT_CLR6_CLRP029_Pos 29 /*!< GPIO_PORT CLR6: CLRP029 Position */
+#define GPIO_PORT_CLR6_CLRP029_Msk (0x01UL << GPIO_PORT_CLR6_CLRP029_Pos) /*!< GPIO_PORT CLR6: CLRP029 Mask */
+#define GPIO_PORT_CLR6_CLRP030_Pos 30 /*!< GPIO_PORT CLR6: CLRP030 Position */
+#define GPIO_PORT_CLR6_CLRP030_Msk (0x01UL << GPIO_PORT_CLR6_CLRP030_Pos) /*!< GPIO_PORT CLR6: CLRP030 Mask */
+#define GPIO_PORT_CLR6_CLRP031_Pos 31 /*!< GPIO_PORT CLR6: CLRP031 Position */
+#define GPIO_PORT_CLR6_CLRP031_Msk (0x01UL << GPIO_PORT_CLR6_CLRP031_Pos) /*!< GPIO_PORT CLR6: CLRP031 Mask */
+
+// ------------------------------------- GPIO_PORT_CLR7 -----------------------------------------
+#define GPIO_PORT_CLR7_CLRP00_Pos 0 /*!< GPIO_PORT CLR7: CLRP00 Position */
+#define GPIO_PORT_CLR7_CLRP00_Msk (0x01UL << GPIO_PORT_CLR7_CLRP00_Pos) /*!< GPIO_PORT CLR7: CLRP00 Mask */
+#define GPIO_PORT_CLR7_CLRP01_Pos 1 /*!< GPIO_PORT CLR7: CLRP01 Position */
+#define GPIO_PORT_CLR7_CLRP01_Msk (0x01UL << GPIO_PORT_CLR7_CLRP01_Pos) /*!< GPIO_PORT CLR7: CLRP01 Mask */
+#define GPIO_PORT_CLR7_CLRP02_Pos 2 /*!< GPIO_PORT CLR7: CLRP02 Position */
+#define GPIO_PORT_CLR7_CLRP02_Msk (0x01UL << GPIO_PORT_CLR7_CLRP02_Pos) /*!< GPIO_PORT CLR7: CLRP02 Mask */
+#define GPIO_PORT_CLR7_CLRP03_Pos 3 /*!< GPIO_PORT CLR7: CLRP03 Position */
+#define GPIO_PORT_CLR7_CLRP03_Msk (0x01UL << GPIO_PORT_CLR7_CLRP03_Pos) /*!< GPIO_PORT CLR7: CLRP03 Mask */
+#define GPIO_PORT_CLR7_CLRP04_Pos 4 /*!< GPIO_PORT CLR7: CLRP04 Position */
+#define GPIO_PORT_CLR7_CLRP04_Msk (0x01UL << GPIO_PORT_CLR7_CLRP04_Pos) /*!< GPIO_PORT CLR7: CLRP04 Mask */
+#define GPIO_PORT_CLR7_CLRP05_Pos 5 /*!< GPIO_PORT CLR7: CLRP05 Position */
+#define GPIO_PORT_CLR7_CLRP05_Msk (0x01UL << GPIO_PORT_CLR7_CLRP05_Pos) /*!< GPIO_PORT CLR7: CLRP05 Mask */
+#define GPIO_PORT_CLR7_CLRP06_Pos 6 /*!< GPIO_PORT CLR7: CLRP06 Position */
+#define GPIO_PORT_CLR7_CLRP06_Msk (0x01UL << GPIO_PORT_CLR7_CLRP06_Pos) /*!< GPIO_PORT CLR7: CLRP06 Mask */
+#define GPIO_PORT_CLR7_CLRP07_Pos 7 /*!< GPIO_PORT CLR7: CLRP07 Position */
+#define GPIO_PORT_CLR7_CLRP07_Msk (0x01UL << GPIO_PORT_CLR7_CLRP07_Pos) /*!< GPIO_PORT CLR7: CLRP07 Mask */
+#define GPIO_PORT_CLR7_CLRP08_Pos 8 /*!< GPIO_PORT CLR7: CLRP08 Position */
+#define GPIO_PORT_CLR7_CLRP08_Msk (0x01UL << GPIO_PORT_CLR7_CLRP08_Pos) /*!< GPIO_PORT CLR7: CLRP08 Mask */
+#define GPIO_PORT_CLR7_CLRP09_Pos 9 /*!< GPIO_PORT CLR7: CLRP09 Position */
+#define GPIO_PORT_CLR7_CLRP09_Msk (0x01UL << GPIO_PORT_CLR7_CLRP09_Pos) /*!< GPIO_PORT CLR7: CLRP09 Mask */
+#define GPIO_PORT_CLR7_CLRP010_Pos 10 /*!< GPIO_PORT CLR7: CLRP010 Position */
+#define GPIO_PORT_CLR7_CLRP010_Msk (0x01UL << GPIO_PORT_CLR7_CLRP010_Pos) /*!< GPIO_PORT CLR7: CLRP010 Mask */
+#define GPIO_PORT_CLR7_CLRP011_Pos 11 /*!< GPIO_PORT CLR7: CLRP011 Position */
+#define GPIO_PORT_CLR7_CLRP011_Msk (0x01UL << GPIO_PORT_CLR7_CLRP011_Pos) /*!< GPIO_PORT CLR7: CLRP011 Mask */
+#define GPIO_PORT_CLR7_CLRP012_Pos 12 /*!< GPIO_PORT CLR7: CLRP012 Position */
+#define GPIO_PORT_CLR7_CLRP012_Msk (0x01UL << GPIO_PORT_CLR7_CLRP012_Pos) /*!< GPIO_PORT CLR7: CLRP012 Mask */
+#define GPIO_PORT_CLR7_CLRP013_Pos 13 /*!< GPIO_PORT CLR7: CLRP013 Position */
+#define GPIO_PORT_CLR7_CLRP013_Msk (0x01UL << GPIO_PORT_CLR7_CLRP013_Pos) /*!< GPIO_PORT CLR7: CLRP013 Mask */
+#define GPIO_PORT_CLR7_CLRP014_Pos 14 /*!< GPIO_PORT CLR7: CLRP014 Position */
+#define GPIO_PORT_CLR7_CLRP014_Msk (0x01UL << GPIO_PORT_CLR7_CLRP014_Pos) /*!< GPIO_PORT CLR7: CLRP014 Mask */
+#define GPIO_PORT_CLR7_CLRP015_Pos 15 /*!< GPIO_PORT CLR7: CLRP015 Position */
+#define GPIO_PORT_CLR7_CLRP015_Msk (0x01UL << GPIO_PORT_CLR7_CLRP015_Pos) /*!< GPIO_PORT CLR7: CLRP015 Mask */
+#define GPIO_PORT_CLR7_CLRP016_Pos 16 /*!< GPIO_PORT CLR7: CLRP016 Position */
+#define GPIO_PORT_CLR7_CLRP016_Msk (0x01UL << GPIO_PORT_CLR7_CLRP016_Pos) /*!< GPIO_PORT CLR7: CLRP016 Mask */
+#define GPIO_PORT_CLR7_CLRP017_Pos 17 /*!< GPIO_PORT CLR7: CLRP017 Position */
+#define GPIO_PORT_CLR7_CLRP017_Msk (0x01UL << GPIO_PORT_CLR7_CLRP017_Pos) /*!< GPIO_PORT CLR7: CLRP017 Mask */
+#define GPIO_PORT_CLR7_CLRP018_Pos 18 /*!< GPIO_PORT CLR7: CLRP018 Position */
+#define GPIO_PORT_CLR7_CLRP018_Msk (0x01UL << GPIO_PORT_CLR7_CLRP018_Pos) /*!< GPIO_PORT CLR7: CLRP018 Mask */
+#define GPIO_PORT_CLR7_CLRP019_Pos 19 /*!< GPIO_PORT CLR7: CLRP019 Position */
+#define GPIO_PORT_CLR7_CLRP019_Msk (0x01UL << GPIO_PORT_CLR7_CLRP019_Pos) /*!< GPIO_PORT CLR7: CLRP019 Mask */
+#define GPIO_PORT_CLR7_CLRP020_Pos 20 /*!< GPIO_PORT CLR7: CLRP020 Position */
+#define GPIO_PORT_CLR7_CLRP020_Msk (0x01UL << GPIO_PORT_CLR7_CLRP020_Pos) /*!< GPIO_PORT CLR7: CLRP020 Mask */
+#define GPIO_PORT_CLR7_CLRP021_Pos 21 /*!< GPIO_PORT CLR7: CLRP021 Position */
+#define GPIO_PORT_CLR7_CLRP021_Msk (0x01UL << GPIO_PORT_CLR7_CLRP021_Pos) /*!< GPIO_PORT CLR7: CLRP021 Mask */
+#define GPIO_PORT_CLR7_CLRP022_Pos 22 /*!< GPIO_PORT CLR7: CLRP022 Position */
+#define GPIO_PORT_CLR7_CLRP022_Msk (0x01UL << GPIO_PORT_CLR7_CLRP022_Pos) /*!< GPIO_PORT CLR7: CLRP022 Mask */
+#define GPIO_PORT_CLR7_CLRP023_Pos 23 /*!< GPIO_PORT CLR7: CLRP023 Position */
+#define GPIO_PORT_CLR7_CLRP023_Msk (0x01UL << GPIO_PORT_CLR7_CLRP023_Pos) /*!< GPIO_PORT CLR7: CLRP023 Mask */
+#define GPIO_PORT_CLR7_CLRP024_Pos 24 /*!< GPIO_PORT CLR7: CLRP024 Position */
+#define GPIO_PORT_CLR7_CLRP024_Msk (0x01UL << GPIO_PORT_CLR7_CLRP024_Pos) /*!< GPIO_PORT CLR7: CLRP024 Mask */
+#define GPIO_PORT_CLR7_CLRP025_Pos 25 /*!< GPIO_PORT CLR7: CLRP025 Position */
+#define GPIO_PORT_CLR7_CLRP025_Msk (0x01UL << GPIO_PORT_CLR7_CLRP025_Pos) /*!< GPIO_PORT CLR7: CLRP025 Mask */
+#define GPIO_PORT_CLR7_CLRP026_Pos 26 /*!< GPIO_PORT CLR7: CLRP026 Position */
+#define GPIO_PORT_CLR7_CLRP026_Msk (0x01UL << GPIO_PORT_CLR7_CLRP026_Pos) /*!< GPIO_PORT CLR7: CLRP026 Mask */
+#define GPIO_PORT_CLR7_CLRP027_Pos 27 /*!< GPIO_PORT CLR7: CLRP027 Position */
+#define GPIO_PORT_CLR7_CLRP027_Msk (0x01UL << GPIO_PORT_CLR7_CLRP027_Pos) /*!< GPIO_PORT CLR7: CLRP027 Mask */
+#define GPIO_PORT_CLR7_CLRP028_Pos 28 /*!< GPIO_PORT CLR7: CLRP028 Position */
+#define GPIO_PORT_CLR7_CLRP028_Msk (0x01UL << GPIO_PORT_CLR7_CLRP028_Pos) /*!< GPIO_PORT CLR7: CLRP028 Mask */
+#define GPIO_PORT_CLR7_CLRP029_Pos 29 /*!< GPIO_PORT CLR7: CLRP029 Position */
+#define GPIO_PORT_CLR7_CLRP029_Msk (0x01UL << GPIO_PORT_CLR7_CLRP029_Pos) /*!< GPIO_PORT CLR7: CLRP029 Mask */
+#define GPIO_PORT_CLR7_CLRP030_Pos 30 /*!< GPIO_PORT CLR7: CLRP030 Position */
+#define GPIO_PORT_CLR7_CLRP030_Msk (0x01UL << GPIO_PORT_CLR7_CLRP030_Pos) /*!< GPIO_PORT CLR7: CLRP030 Mask */
+#define GPIO_PORT_CLR7_CLRP031_Pos 31 /*!< GPIO_PORT CLR7: CLRP031 Position */
+#define GPIO_PORT_CLR7_CLRP031_Msk (0x01UL << GPIO_PORT_CLR7_CLRP031_Pos) /*!< GPIO_PORT CLR7: CLRP031 Mask */
+
+// ------------------------------------- GPIO_PORT_NOT0 -----------------------------------------
+#define GPIO_PORT_NOT0_NOTP0_Pos 0 /*!< GPIO_PORT NOT0: NOTP0 Position */
+#define GPIO_PORT_NOT0_NOTP0_Msk (0x01UL << GPIO_PORT_NOT0_NOTP0_Pos) /*!< GPIO_PORT NOT0: NOTP0 Mask */
+#define GPIO_PORT_NOT0_NOTP1_Pos 1 /*!< GPIO_PORT NOT0: NOTP1 Position */
+#define GPIO_PORT_NOT0_NOTP1_Msk (0x01UL << GPIO_PORT_NOT0_NOTP1_Pos) /*!< GPIO_PORT NOT0: NOTP1 Mask */
+#define GPIO_PORT_NOT0_NOTP2_Pos 2 /*!< GPIO_PORT NOT0: NOTP2 Position */
+#define GPIO_PORT_NOT0_NOTP2_Msk (0x01UL << GPIO_PORT_NOT0_NOTP2_Pos) /*!< GPIO_PORT NOT0: NOTP2 Mask */
+#define GPIO_PORT_NOT0_NOTP3_Pos 3 /*!< GPIO_PORT NOT0: NOTP3 Position */
+#define GPIO_PORT_NOT0_NOTP3_Msk (0x01UL << GPIO_PORT_NOT0_NOTP3_Pos) /*!< GPIO_PORT NOT0: NOTP3 Mask */
+#define GPIO_PORT_NOT0_NOTP4_Pos 4 /*!< GPIO_PORT NOT0: NOTP4 Position */
+#define GPIO_PORT_NOT0_NOTP4_Msk (0x01UL << GPIO_PORT_NOT0_NOTP4_Pos) /*!< GPIO_PORT NOT0: NOTP4 Mask */
+#define GPIO_PORT_NOT0_NOTP5_Pos 5 /*!< GPIO_PORT NOT0: NOTP5 Position */
+#define GPIO_PORT_NOT0_NOTP5_Msk (0x01UL << GPIO_PORT_NOT0_NOTP5_Pos) /*!< GPIO_PORT NOT0: NOTP5 Mask */
+#define GPIO_PORT_NOT0_NOTP6_Pos 6 /*!< GPIO_PORT NOT0: NOTP6 Position */
+#define GPIO_PORT_NOT0_NOTP6_Msk (0x01UL << GPIO_PORT_NOT0_NOTP6_Pos) /*!< GPIO_PORT NOT0: NOTP6 Mask */
+#define GPIO_PORT_NOT0_NOTP7_Pos 7 /*!< GPIO_PORT NOT0: NOTP7 Position */
+#define GPIO_PORT_NOT0_NOTP7_Msk (0x01UL << GPIO_PORT_NOT0_NOTP7_Pos) /*!< GPIO_PORT NOT0: NOTP7 Mask */
+#define GPIO_PORT_NOT0_NOTP8_Pos 8 /*!< GPIO_PORT NOT0: NOTP8 Position */
+#define GPIO_PORT_NOT0_NOTP8_Msk (0x01UL << GPIO_PORT_NOT0_NOTP8_Pos) /*!< GPIO_PORT NOT0: NOTP8 Mask */
+#define GPIO_PORT_NOT0_NOTP9_Pos 9 /*!< GPIO_PORT NOT0: NOTP9 Position */
+#define GPIO_PORT_NOT0_NOTP9_Msk (0x01UL << GPIO_PORT_NOT0_NOTP9_Pos) /*!< GPIO_PORT NOT0: NOTP9 Mask */
+#define GPIO_PORT_NOT0_NOTP10_Pos 10 /*!< GPIO_PORT NOT0: NOTP10 Position */
+#define GPIO_PORT_NOT0_NOTP10_Msk (0x01UL << GPIO_PORT_NOT0_NOTP10_Pos) /*!< GPIO_PORT NOT0: NOTP10 Mask */
+#define GPIO_PORT_NOT0_NOTP11_Pos 11 /*!< GPIO_PORT NOT0: NOTP11 Position */
+#define GPIO_PORT_NOT0_NOTP11_Msk (0x01UL << GPIO_PORT_NOT0_NOTP11_Pos) /*!< GPIO_PORT NOT0: NOTP11 Mask */
+#define GPIO_PORT_NOT0_NOTP12_Pos 12 /*!< GPIO_PORT NOT0: NOTP12 Position */
+#define GPIO_PORT_NOT0_NOTP12_Msk (0x01UL << GPIO_PORT_NOT0_NOTP12_Pos) /*!< GPIO_PORT NOT0: NOTP12 Mask */
+#define GPIO_PORT_NOT0_NOTP13_Pos 13 /*!< GPIO_PORT NOT0: NOTP13 Position */
+#define GPIO_PORT_NOT0_NOTP13_Msk (0x01UL << GPIO_PORT_NOT0_NOTP13_Pos) /*!< GPIO_PORT NOT0: NOTP13 Mask */
+#define GPIO_PORT_NOT0_NOTP14_Pos 14 /*!< GPIO_PORT NOT0: NOTP14 Position */
+#define GPIO_PORT_NOT0_NOTP14_Msk (0x01UL << GPIO_PORT_NOT0_NOTP14_Pos) /*!< GPIO_PORT NOT0: NOTP14 Mask */
+#define GPIO_PORT_NOT0_NOTP15_Pos 15 /*!< GPIO_PORT NOT0: NOTP15 Position */
+#define GPIO_PORT_NOT0_NOTP15_Msk (0x01UL << GPIO_PORT_NOT0_NOTP15_Pos) /*!< GPIO_PORT NOT0: NOTP15 Mask */
+#define GPIO_PORT_NOT0_NOTP16_Pos 16 /*!< GPIO_PORT NOT0: NOTP16 Position */
+#define GPIO_PORT_NOT0_NOTP16_Msk (0x01UL << GPIO_PORT_NOT0_NOTP16_Pos) /*!< GPIO_PORT NOT0: NOTP16 Mask */
+#define GPIO_PORT_NOT0_NOTP17_Pos 17 /*!< GPIO_PORT NOT0: NOTP17 Position */
+#define GPIO_PORT_NOT0_NOTP17_Msk (0x01UL << GPIO_PORT_NOT0_NOTP17_Pos) /*!< GPIO_PORT NOT0: NOTP17 Mask */
+#define GPIO_PORT_NOT0_NOTP18_Pos 18 /*!< GPIO_PORT NOT0: NOTP18 Position */
+#define GPIO_PORT_NOT0_NOTP18_Msk (0x01UL << GPIO_PORT_NOT0_NOTP18_Pos) /*!< GPIO_PORT NOT0: NOTP18 Mask */
+#define GPIO_PORT_NOT0_NOTP19_Pos 19 /*!< GPIO_PORT NOT0: NOTP19 Position */
+#define GPIO_PORT_NOT0_NOTP19_Msk (0x01UL << GPIO_PORT_NOT0_NOTP19_Pos) /*!< GPIO_PORT NOT0: NOTP19 Mask */
+#define GPIO_PORT_NOT0_NOTP20_Pos 20 /*!< GPIO_PORT NOT0: NOTP20 Position */
+#define GPIO_PORT_NOT0_NOTP20_Msk (0x01UL << GPIO_PORT_NOT0_NOTP20_Pos) /*!< GPIO_PORT NOT0: NOTP20 Mask */
+#define GPIO_PORT_NOT0_NOTP21_Pos 21 /*!< GPIO_PORT NOT0: NOTP21 Position */
+#define GPIO_PORT_NOT0_NOTP21_Msk (0x01UL << GPIO_PORT_NOT0_NOTP21_Pos) /*!< GPIO_PORT NOT0: NOTP21 Mask */
+#define GPIO_PORT_NOT0_NOTP22_Pos 22 /*!< GPIO_PORT NOT0: NOTP22 Position */
+#define GPIO_PORT_NOT0_NOTP22_Msk (0x01UL << GPIO_PORT_NOT0_NOTP22_Pos) /*!< GPIO_PORT NOT0: NOTP22 Mask */
+#define GPIO_PORT_NOT0_NOTP23_Pos 23 /*!< GPIO_PORT NOT0: NOTP23 Position */
+#define GPIO_PORT_NOT0_NOTP23_Msk (0x01UL << GPIO_PORT_NOT0_NOTP23_Pos) /*!< GPIO_PORT NOT0: NOTP23 Mask */
+#define GPIO_PORT_NOT0_NOTP24_Pos 24 /*!< GPIO_PORT NOT0: NOTP24 Position */
+#define GPIO_PORT_NOT0_NOTP24_Msk (0x01UL << GPIO_PORT_NOT0_NOTP24_Pos) /*!< GPIO_PORT NOT0: NOTP24 Mask */
+#define GPIO_PORT_NOT0_NOTP25_Pos 25 /*!< GPIO_PORT NOT0: NOTP25 Position */
+#define GPIO_PORT_NOT0_NOTP25_Msk (0x01UL << GPIO_PORT_NOT0_NOTP25_Pos) /*!< GPIO_PORT NOT0: NOTP25 Mask */
+#define GPIO_PORT_NOT0_NOTP26_Pos 26 /*!< GPIO_PORT NOT0: NOTP26 Position */
+#define GPIO_PORT_NOT0_NOTP26_Msk (0x01UL << GPIO_PORT_NOT0_NOTP26_Pos) /*!< GPIO_PORT NOT0: NOTP26 Mask */
+#define GPIO_PORT_NOT0_NOTP27_Pos 27 /*!< GPIO_PORT NOT0: NOTP27 Position */
+#define GPIO_PORT_NOT0_NOTP27_Msk (0x01UL << GPIO_PORT_NOT0_NOTP27_Pos) /*!< GPIO_PORT NOT0: NOTP27 Mask */
+#define GPIO_PORT_NOT0_NOTP28_Pos 28 /*!< GPIO_PORT NOT0: NOTP28 Position */
+#define GPIO_PORT_NOT0_NOTP28_Msk (0x01UL << GPIO_PORT_NOT0_NOTP28_Pos) /*!< GPIO_PORT NOT0: NOTP28 Mask */
+#define GPIO_PORT_NOT0_NOTP29_Pos 29 /*!< GPIO_PORT NOT0: NOTP29 Position */
+#define GPIO_PORT_NOT0_NOTP29_Msk (0x01UL << GPIO_PORT_NOT0_NOTP29_Pos) /*!< GPIO_PORT NOT0: NOTP29 Mask */
+#define GPIO_PORT_NOT0_NOTP30_Pos 30 /*!< GPIO_PORT NOT0: NOTP30 Position */
+#define GPIO_PORT_NOT0_NOTP30_Msk (0x01UL << GPIO_PORT_NOT0_NOTP30_Pos) /*!< GPIO_PORT NOT0: NOTP30 Mask */
+#define GPIO_PORT_NOT0_NOTP31_Pos 31 /*!< GPIO_PORT NOT0: NOTP31 Position */
+#define GPIO_PORT_NOT0_NOTP31_Msk (0x01UL << GPIO_PORT_NOT0_NOTP31_Pos) /*!< GPIO_PORT NOT0: NOTP31 Mask */
+
+// ------------------------------------- GPIO_PORT_NOT1 -----------------------------------------
+#define GPIO_PORT_NOT1_NOTP0_Pos 0 /*!< GPIO_PORT NOT1: NOTP0 Position */
+#define GPIO_PORT_NOT1_NOTP0_Msk (0x01UL << GPIO_PORT_NOT1_NOTP0_Pos) /*!< GPIO_PORT NOT1: NOTP0 Mask */
+#define GPIO_PORT_NOT1_NOTP1_Pos 1 /*!< GPIO_PORT NOT1: NOTP1 Position */
+#define GPIO_PORT_NOT1_NOTP1_Msk (0x01UL << GPIO_PORT_NOT1_NOTP1_Pos) /*!< GPIO_PORT NOT1: NOTP1 Mask */
+#define GPIO_PORT_NOT1_NOTP2_Pos 2 /*!< GPIO_PORT NOT1: NOTP2 Position */
+#define GPIO_PORT_NOT1_NOTP2_Msk (0x01UL << GPIO_PORT_NOT1_NOTP2_Pos) /*!< GPIO_PORT NOT1: NOTP2 Mask */
+#define GPIO_PORT_NOT1_NOTP3_Pos 3 /*!< GPIO_PORT NOT1: NOTP3 Position */
+#define GPIO_PORT_NOT1_NOTP3_Msk (0x01UL << GPIO_PORT_NOT1_NOTP3_Pos) /*!< GPIO_PORT NOT1: NOTP3 Mask */
+#define GPIO_PORT_NOT1_NOTP4_Pos 4 /*!< GPIO_PORT NOT1: NOTP4 Position */
+#define GPIO_PORT_NOT1_NOTP4_Msk (0x01UL << GPIO_PORT_NOT1_NOTP4_Pos) /*!< GPIO_PORT NOT1: NOTP4 Mask */
+#define GPIO_PORT_NOT1_NOTP5_Pos 5 /*!< GPIO_PORT NOT1: NOTP5 Position */
+#define GPIO_PORT_NOT1_NOTP5_Msk (0x01UL << GPIO_PORT_NOT1_NOTP5_Pos) /*!< GPIO_PORT NOT1: NOTP5 Mask */
+#define GPIO_PORT_NOT1_NOTP6_Pos 6 /*!< GPIO_PORT NOT1: NOTP6 Position */
+#define GPIO_PORT_NOT1_NOTP6_Msk (0x01UL << GPIO_PORT_NOT1_NOTP6_Pos) /*!< GPIO_PORT NOT1: NOTP6 Mask */
+#define GPIO_PORT_NOT1_NOTP7_Pos 7 /*!< GPIO_PORT NOT1: NOTP7 Position */
+#define GPIO_PORT_NOT1_NOTP7_Msk (0x01UL << GPIO_PORT_NOT1_NOTP7_Pos) /*!< GPIO_PORT NOT1: NOTP7 Mask */
+#define GPIO_PORT_NOT1_NOTP8_Pos 8 /*!< GPIO_PORT NOT1: NOTP8 Position */
+#define GPIO_PORT_NOT1_NOTP8_Msk (0x01UL << GPIO_PORT_NOT1_NOTP8_Pos) /*!< GPIO_PORT NOT1: NOTP8 Mask */
+#define GPIO_PORT_NOT1_NOTP9_Pos 9 /*!< GPIO_PORT NOT1: NOTP9 Position */
+#define GPIO_PORT_NOT1_NOTP9_Msk (0x01UL << GPIO_PORT_NOT1_NOTP9_Pos) /*!< GPIO_PORT NOT1: NOTP9 Mask */
+#define GPIO_PORT_NOT1_NOTP10_Pos 10 /*!< GPIO_PORT NOT1: NOTP10 Position */
+#define GPIO_PORT_NOT1_NOTP10_Msk (0x01UL << GPIO_PORT_NOT1_NOTP10_Pos) /*!< GPIO_PORT NOT1: NOTP10 Mask */
+#define GPIO_PORT_NOT1_NOTP11_Pos 11 /*!< GPIO_PORT NOT1: NOTP11 Position */
+#define GPIO_PORT_NOT1_NOTP11_Msk (0x01UL << GPIO_PORT_NOT1_NOTP11_Pos) /*!< GPIO_PORT NOT1: NOTP11 Mask */
+#define GPIO_PORT_NOT1_NOTP12_Pos 12 /*!< GPIO_PORT NOT1: NOTP12 Position */
+#define GPIO_PORT_NOT1_NOTP12_Msk (0x01UL << GPIO_PORT_NOT1_NOTP12_Pos) /*!< GPIO_PORT NOT1: NOTP12 Mask */
+#define GPIO_PORT_NOT1_NOTP13_Pos 13 /*!< GPIO_PORT NOT1: NOTP13 Position */
+#define GPIO_PORT_NOT1_NOTP13_Msk (0x01UL << GPIO_PORT_NOT1_NOTP13_Pos) /*!< GPIO_PORT NOT1: NOTP13 Mask */
+#define GPIO_PORT_NOT1_NOTP14_Pos 14 /*!< GPIO_PORT NOT1: NOTP14 Position */
+#define GPIO_PORT_NOT1_NOTP14_Msk (0x01UL << GPIO_PORT_NOT1_NOTP14_Pos) /*!< GPIO_PORT NOT1: NOTP14 Mask */
+#define GPIO_PORT_NOT1_NOTP15_Pos 15 /*!< GPIO_PORT NOT1: NOTP15 Position */
+#define GPIO_PORT_NOT1_NOTP15_Msk (0x01UL << GPIO_PORT_NOT1_NOTP15_Pos) /*!< GPIO_PORT NOT1: NOTP15 Mask */
+#define GPIO_PORT_NOT1_NOTP16_Pos 16 /*!< GPIO_PORT NOT1: NOTP16 Position */
+#define GPIO_PORT_NOT1_NOTP16_Msk (0x01UL << GPIO_PORT_NOT1_NOTP16_Pos) /*!< GPIO_PORT NOT1: NOTP16 Mask */
+#define GPIO_PORT_NOT1_NOTP17_Pos 17 /*!< GPIO_PORT NOT1: NOTP17 Position */
+#define GPIO_PORT_NOT1_NOTP17_Msk (0x01UL << GPIO_PORT_NOT1_NOTP17_Pos) /*!< GPIO_PORT NOT1: NOTP17 Mask */
+#define GPIO_PORT_NOT1_NOTP18_Pos 18 /*!< GPIO_PORT NOT1: NOTP18 Position */
+#define GPIO_PORT_NOT1_NOTP18_Msk (0x01UL << GPIO_PORT_NOT1_NOTP18_Pos) /*!< GPIO_PORT NOT1: NOTP18 Mask */
+#define GPIO_PORT_NOT1_NOTP19_Pos 19 /*!< GPIO_PORT NOT1: NOTP19 Position */
+#define GPIO_PORT_NOT1_NOTP19_Msk (0x01UL << GPIO_PORT_NOT1_NOTP19_Pos) /*!< GPIO_PORT NOT1: NOTP19 Mask */
+#define GPIO_PORT_NOT1_NOTP20_Pos 20 /*!< GPIO_PORT NOT1: NOTP20 Position */
+#define GPIO_PORT_NOT1_NOTP20_Msk (0x01UL << GPIO_PORT_NOT1_NOTP20_Pos) /*!< GPIO_PORT NOT1: NOTP20 Mask */
+#define GPIO_PORT_NOT1_NOTP21_Pos 21 /*!< GPIO_PORT NOT1: NOTP21 Position */
+#define GPIO_PORT_NOT1_NOTP21_Msk (0x01UL << GPIO_PORT_NOT1_NOTP21_Pos) /*!< GPIO_PORT NOT1: NOTP21 Mask */
+#define GPIO_PORT_NOT1_NOTP22_Pos 22 /*!< GPIO_PORT NOT1: NOTP22 Position */
+#define GPIO_PORT_NOT1_NOTP22_Msk (0x01UL << GPIO_PORT_NOT1_NOTP22_Pos) /*!< GPIO_PORT NOT1: NOTP22 Mask */
+#define GPIO_PORT_NOT1_NOTP23_Pos 23 /*!< GPIO_PORT NOT1: NOTP23 Position */
+#define GPIO_PORT_NOT1_NOTP23_Msk (0x01UL << GPIO_PORT_NOT1_NOTP23_Pos) /*!< GPIO_PORT NOT1: NOTP23 Mask */
+#define GPIO_PORT_NOT1_NOTP24_Pos 24 /*!< GPIO_PORT NOT1: NOTP24 Position */
+#define GPIO_PORT_NOT1_NOTP24_Msk (0x01UL << GPIO_PORT_NOT1_NOTP24_Pos) /*!< GPIO_PORT NOT1: NOTP24 Mask */
+#define GPIO_PORT_NOT1_NOTP25_Pos 25 /*!< GPIO_PORT NOT1: NOTP25 Position */
+#define GPIO_PORT_NOT1_NOTP25_Msk (0x01UL << GPIO_PORT_NOT1_NOTP25_Pos) /*!< GPIO_PORT NOT1: NOTP25 Mask */
+#define GPIO_PORT_NOT1_NOTP26_Pos 26 /*!< GPIO_PORT NOT1: NOTP26 Position */
+#define GPIO_PORT_NOT1_NOTP26_Msk (0x01UL << GPIO_PORT_NOT1_NOTP26_Pos) /*!< GPIO_PORT NOT1: NOTP26 Mask */
+#define GPIO_PORT_NOT1_NOTP27_Pos 27 /*!< GPIO_PORT NOT1: NOTP27 Position */
+#define GPIO_PORT_NOT1_NOTP27_Msk (0x01UL << GPIO_PORT_NOT1_NOTP27_Pos) /*!< GPIO_PORT NOT1: NOTP27 Mask */
+#define GPIO_PORT_NOT1_NOTP28_Pos 28 /*!< GPIO_PORT NOT1: NOTP28 Position */
+#define GPIO_PORT_NOT1_NOTP28_Msk (0x01UL << GPIO_PORT_NOT1_NOTP28_Pos) /*!< GPIO_PORT NOT1: NOTP28 Mask */
+#define GPIO_PORT_NOT1_NOTP29_Pos 29 /*!< GPIO_PORT NOT1: NOTP29 Position */
+#define GPIO_PORT_NOT1_NOTP29_Msk (0x01UL << GPIO_PORT_NOT1_NOTP29_Pos) /*!< GPIO_PORT NOT1: NOTP29 Mask */
+#define GPIO_PORT_NOT1_NOTP30_Pos 30 /*!< GPIO_PORT NOT1: NOTP30 Position */
+#define GPIO_PORT_NOT1_NOTP30_Msk (0x01UL << GPIO_PORT_NOT1_NOTP30_Pos) /*!< GPIO_PORT NOT1: NOTP30 Mask */
+#define GPIO_PORT_NOT1_NOTP31_Pos 31 /*!< GPIO_PORT NOT1: NOTP31 Position */
+#define GPIO_PORT_NOT1_NOTP31_Msk (0x01UL << GPIO_PORT_NOT1_NOTP31_Pos) /*!< GPIO_PORT NOT1: NOTP31 Mask */
+
+// ------------------------------------- GPIO_PORT_NOT2 -----------------------------------------
+#define GPIO_PORT_NOT2_NOTP0_Pos 0 /*!< GPIO_PORT NOT2: NOTP0 Position */
+#define GPIO_PORT_NOT2_NOTP0_Msk (0x01UL << GPIO_PORT_NOT2_NOTP0_Pos) /*!< GPIO_PORT NOT2: NOTP0 Mask */
+#define GPIO_PORT_NOT2_NOTP1_Pos 1 /*!< GPIO_PORT NOT2: NOTP1 Position */
+#define GPIO_PORT_NOT2_NOTP1_Msk (0x01UL << GPIO_PORT_NOT2_NOTP1_Pos) /*!< GPIO_PORT NOT2: NOTP1 Mask */
+#define GPIO_PORT_NOT2_NOTP2_Pos 2 /*!< GPIO_PORT NOT2: NOTP2 Position */
+#define GPIO_PORT_NOT2_NOTP2_Msk (0x01UL << GPIO_PORT_NOT2_NOTP2_Pos) /*!< GPIO_PORT NOT2: NOTP2 Mask */
+#define GPIO_PORT_NOT2_NOTP3_Pos 3 /*!< GPIO_PORT NOT2: NOTP3 Position */
+#define GPIO_PORT_NOT2_NOTP3_Msk (0x01UL << GPIO_PORT_NOT2_NOTP3_Pos) /*!< GPIO_PORT NOT2: NOTP3 Mask */
+#define GPIO_PORT_NOT2_NOTP4_Pos 4 /*!< GPIO_PORT NOT2: NOTP4 Position */
+#define GPIO_PORT_NOT2_NOTP4_Msk (0x01UL << GPIO_PORT_NOT2_NOTP4_Pos) /*!< GPIO_PORT NOT2: NOTP4 Mask */
+#define GPIO_PORT_NOT2_NOTP5_Pos 5 /*!< GPIO_PORT NOT2: NOTP5 Position */
+#define GPIO_PORT_NOT2_NOTP5_Msk (0x01UL << GPIO_PORT_NOT2_NOTP5_Pos) /*!< GPIO_PORT NOT2: NOTP5 Mask */
+#define GPIO_PORT_NOT2_NOTP6_Pos 6 /*!< GPIO_PORT NOT2: NOTP6 Position */
+#define GPIO_PORT_NOT2_NOTP6_Msk (0x01UL << GPIO_PORT_NOT2_NOTP6_Pos) /*!< GPIO_PORT NOT2: NOTP6 Mask */
+#define GPIO_PORT_NOT2_NOTP7_Pos 7 /*!< GPIO_PORT NOT2: NOTP7 Position */
+#define GPIO_PORT_NOT2_NOTP7_Msk (0x01UL << GPIO_PORT_NOT2_NOTP7_Pos) /*!< GPIO_PORT NOT2: NOTP7 Mask */
+#define GPIO_PORT_NOT2_NOTP8_Pos 8 /*!< GPIO_PORT NOT2: NOTP8 Position */
+#define GPIO_PORT_NOT2_NOTP8_Msk (0x01UL << GPIO_PORT_NOT2_NOTP8_Pos) /*!< GPIO_PORT NOT2: NOTP8 Mask */
+#define GPIO_PORT_NOT2_NOTP9_Pos 9 /*!< GPIO_PORT NOT2: NOTP9 Position */
+#define GPIO_PORT_NOT2_NOTP9_Msk (0x01UL << GPIO_PORT_NOT2_NOTP9_Pos) /*!< GPIO_PORT NOT2: NOTP9 Mask */
+#define GPIO_PORT_NOT2_NOTP10_Pos 10 /*!< GPIO_PORT NOT2: NOTP10 Position */
+#define GPIO_PORT_NOT2_NOTP10_Msk (0x01UL << GPIO_PORT_NOT2_NOTP10_Pos) /*!< GPIO_PORT NOT2: NOTP10 Mask */
+#define GPIO_PORT_NOT2_NOTP11_Pos 11 /*!< GPIO_PORT NOT2: NOTP11 Position */
+#define GPIO_PORT_NOT2_NOTP11_Msk (0x01UL << GPIO_PORT_NOT2_NOTP11_Pos) /*!< GPIO_PORT NOT2: NOTP11 Mask */
+#define GPIO_PORT_NOT2_NOTP12_Pos 12 /*!< GPIO_PORT NOT2: NOTP12 Position */
+#define GPIO_PORT_NOT2_NOTP12_Msk (0x01UL << GPIO_PORT_NOT2_NOTP12_Pos) /*!< GPIO_PORT NOT2: NOTP12 Mask */
+#define GPIO_PORT_NOT2_NOTP13_Pos 13 /*!< GPIO_PORT NOT2: NOTP13 Position */
+#define GPIO_PORT_NOT2_NOTP13_Msk (0x01UL << GPIO_PORT_NOT2_NOTP13_Pos) /*!< GPIO_PORT NOT2: NOTP13 Mask */
+#define GPIO_PORT_NOT2_NOTP14_Pos 14 /*!< GPIO_PORT NOT2: NOTP14 Position */
+#define GPIO_PORT_NOT2_NOTP14_Msk (0x01UL << GPIO_PORT_NOT2_NOTP14_Pos) /*!< GPIO_PORT NOT2: NOTP14 Mask */
+#define GPIO_PORT_NOT2_NOTP15_Pos 15 /*!< GPIO_PORT NOT2: NOTP15 Position */
+#define GPIO_PORT_NOT2_NOTP15_Msk (0x01UL << GPIO_PORT_NOT2_NOTP15_Pos) /*!< GPIO_PORT NOT2: NOTP15 Mask */
+#define GPIO_PORT_NOT2_NOTP16_Pos 16 /*!< GPIO_PORT NOT2: NOTP16 Position */
+#define GPIO_PORT_NOT2_NOTP16_Msk (0x01UL << GPIO_PORT_NOT2_NOTP16_Pos) /*!< GPIO_PORT NOT2: NOTP16 Mask */
+#define GPIO_PORT_NOT2_NOTP17_Pos 17 /*!< GPIO_PORT NOT2: NOTP17 Position */
+#define GPIO_PORT_NOT2_NOTP17_Msk (0x01UL << GPIO_PORT_NOT2_NOTP17_Pos) /*!< GPIO_PORT NOT2: NOTP17 Mask */
+#define GPIO_PORT_NOT2_NOTP18_Pos 18 /*!< GPIO_PORT NOT2: NOTP18 Position */
+#define GPIO_PORT_NOT2_NOTP18_Msk (0x01UL << GPIO_PORT_NOT2_NOTP18_Pos) /*!< GPIO_PORT NOT2: NOTP18 Mask */
+#define GPIO_PORT_NOT2_NOTP19_Pos 19 /*!< GPIO_PORT NOT2: NOTP19 Position */
+#define GPIO_PORT_NOT2_NOTP19_Msk (0x01UL << GPIO_PORT_NOT2_NOTP19_Pos) /*!< GPIO_PORT NOT2: NOTP19 Mask */
+#define GPIO_PORT_NOT2_NOTP20_Pos 20 /*!< GPIO_PORT NOT2: NOTP20 Position */
+#define GPIO_PORT_NOT2_NOTP20_Msk (0x01UL << GPIO_PORT_NOT2_NOTP20_Pos) /*!< GPIO_PORT NOT2: NOTP20 Mask */
+#define GPIO_PORT_NOT2_NOTP21_Pos 21 /*!< GPIO_PORT NOT2: NOTP21 Position */
+#define GPIO_PORT_NOT2_NOTP21_Msk (0x01UL << GPIO_PORT_NOT2_NOTP21_Pos) /*!< GPIO_PORT NOT2: NOTP21 Mask */
+#define GPIO_PORT_NOT2_NOTP22_Pos 22 /*!< GPIO_PORT NOT2: NOTP22 Position */
+#define GPIO_PORT_NOT2_NOTP22_Msk (0x01UL << GPIO_PORT_NOT2_NOTP22_Pos) /*!< GPIO_PORT NOT2: NOTP22 Mask */
+#define GPIO_PORT_NOT2_NOTP23_Pos 23 /*!< GPIO_PORT NOT2: NOTP23 Position */
+#define GPIO_PORT_NOT2_NOTP23_Msk (0x01UL << GPIO_PORT_NOT2_NOTP23_Pos) /*!< GPIO_PORT NOT2: NOTP23 Mask */
+#define GPIO_PORT_NOT2_NOTP24_Pos 24 /*!< GPIO_PORT NOT2: NOTP24 Position */
+#define GPIO_PORT_NOT2_NOTP24_Msk (0x01UL << GPIO_PORT_NOT2_NOTP24_Pos) /*!< GPIO_PORT NOT2: NOTP24 Mask */
+#define GPIO_PORT_NOT2_NOTP25_Pos 25 /*!< GPIO_PORT NOT2: NOTP25 Position */
+#define GPIO_PORT_NOT2_NOTP25_Msk (0x01UL << GPIO_PORT_NOT2_NOTP25_Pos) /*!< GPIO_PORT NOT2: NOTP25 Mask */
+#define GPIO_PORT_NOT2_NOTP26_Pos 26 /*!< GPIO_PORT NOT2: NOTP26 Position */
+#define GPIO_PORT_NOT2_NOTP26_Msk (0x01UL << GPIO_PORT_NOT2_NOTP26_Pos) /*!< GPIO_PORT NOT2: NOTP26 Mask */
+#define GPIO_PORT_NOT2_NOTP27_Pos 27 /*!< GPIO_PORT NOT2: NOTP27 Position */
+#define GPIO_PORT_NOT2_NOTP27_Msk (0x01UL << GPIO_PORT_NOT2_NOTP27_Pos) /*!< GPIO_PORT NOT2: NOTP27 Mask */
+#define GPIO_PORT_NOT2_NOTP28_Pos 28 /*!< GPIO_PORT NOT2: NOTP28 Position */
+#define GPIO_PORT_NOT2_NOTP28_Msk (0x01UL << GPIO_PORT_NOT2_NOTP28_Pos) /*!< GPIO_PORT NOT2: NOTP28 Mask */
+#define GPIO_PORT_NOT2_NOTP29_Pos 29 /*!< GPIO_PORT NOT2: NOTP29 Position */
+#define GPIO_PORT_NOT2_NOTP29_Msk (0x01UL << GPIO_PORT_NOT2_NOTP29_Pos) /*!< GPIO_PORT NOT2: NOTP29 Mask */
+#define GPIO_PORT_NOT2_NOTP30_Pos 30 /*!< GPIO_PORT NOT2: NOTP30 Position */
+#define GPIO_PORT_NOT2_NOTP30_Msk (0x01UL << GPIO_PORT_NOT2_NOTP30_Pos) /*!< GPIO_PORT NOT2: NOTP30 Mask */
+#define GPIO_PORT_NOT2_NOTP31_Pos 31 /*!< GPIO_PORT NOT2: NOTP31 Position */
+#define GPIO_PORT_NOT2_NOTP31_Msk (0x01UL << GPIO_PORT_NOT2_NOTP31_Pos) /*!< GPIO_PORT NOT2: NOTP31 Mask */
+
+// ------------------------------------- GPIO_PORT_NOT3 -----------------------------------------
+#define GPIO_PORT_NOT3_NOTP0_Pos 0 /*!< GPIO_PORT NOT3: NOTP0 Position */
+#define GPIO_PORT_NOT3_NOTP0_Msk (0x01UL << GPIO_PORT_NOT3_NOTP0_Pos) /*!< GPIO_PORT NOT3: NOTP0 Mask */
+#define GPIO_PORT_NOT3_NOTP1_Pos 1 /*!< GPIO_PORT NOT3: NOTP1 Position */
+#define GPIO_PORT_NOT3_NOTP1_Msk (0x01UL << GPIO_PORT_NOT3_NOTP1_Pos) /*!< GPIO_PORT NOT3: NOTP1 Mask */
+#define GPIO_PORT_NOT3_NOTP2_Pos 2 /*!< GPIO_PORT NOT3: NOTP2 Position */
+#define GPIO_PORT_NOT3_NOTP2_Msk (0x01UL << GPIO_PORT_NOT3_NOTP2_Pos) /*!< GPIO_PORT NOT3: NOTP2 Mask */
+#define GPIO_PORT_NOT3_NOTP3_Pos 3 /*!< GPIO_PORT NOT3: NOTP3 Position */
+#define GPIO_PORT_NOT3_NOTP3_Msk (0x01UL << GPIO_PORT_NOT3_NOTP3_Pos) /*!< GPIO_PORT NOT3: NOTP3 Mask */
+#define GPIO_PORT_NOT3_NOTP4_Pos 4 /*!< GPIO_PORT NOT3: NOTP4 Position */
+#define GPIO_PORT_NOT3_NOTP4_Msk (0x01UL << GPIO_PORT_NOT3_NOTP4_Pos) /*!< GPIO_PORT NOT3: NOTP4 Mask */
+#define GPIO_PORT_NOT3_NOTP5_Pos 5 /*!< GPIO_PORT NOT3: NOTP5 Position */
+#define GPIO_PORT_NOT3_NOTP5_Msk (0x01UL << GPIO_PORT_NOT3_NOTP5_Pos) /*!< GPIO_PORT NOT3: NOTP5 Mask */
+#define GPIO_PORT_NOT3_NOTP6_Pos 6 /*!< GPIO_PORT NOT3: NOTP6 Position */
+#define GPIO_PORT_NOT3_NOTP6_Msk (0x01UL << GPIO_PORT_NOT3_NOTP6_Pos) /*!< GPIO_PORT NOT3: NOTP6 Mask */
+#define GPIO_PORT_NOT3_NOTP7_Pos 7 /*!< GPIO_PORT NOT3: NOTP7 Position */
+#define GPIO_PORT_NOT3_NOTP7_Msk (0x01UL << GPIO_PORT_NOT3_NOTP7_Pos) /*!< GPIO_PORT NOT3: NOTP7 Mask */
+#define GPIO_PORT_NOT3_NOTP8_Pos 8 /*!< GPIO_PORT NOT3: NOTP8 Position */
+#define GPIO_PORT_NOT3_NOTP8_Msk (0x01UL << GPIO_PORT_NOT3_NOTP8_Pos) /*!< GPIO_PORT NOT3: NOTP8 Mask */
+#define GPIO_PORT_NOT3_NOTP9_Pos 9 /*!< GPIO_PORT NOT3: NOTP9 Position */
+#define GPIO_PORT_NOT3_NOTP9_Msk (0x01UL << GPIO_PORT_NOT3_NOTP9_Pos) /*!< GPIO_PORT NOT3: NOTP9 Mask */
+#define GPIO_PORT_NOT3_NOTP10_Pos 10 /*!< GPIO_PORT NOT3: NOTP10 Position */
+#define GPIO_PORT_NOT3_NOTP10_Msk (0x01UL << GPIO_PORT_NOT3_NOTP10_Pos) /*!< GPIO_PORT NOT3: NOTP10 Mask */
+#define GPIO_PORT_NOT3_NOTP11_Pos 11 /*!< GPIO_PORT NOT3: NOTP11 Position */
+#define GPIO_PORT_NOT3_NOTP11_Msk (0x01UL << GPIO_PORT_NOT3_NOTP11_Pos) /*!< GPIO_PORT NOT3: NOTP11 Mask */
+#define GPIO_PORT_NOT3_NOTP12_Pos 12 /*!< GPIO_PORT NOT3: NOTP12 Position */
+#define GPIO_PORT_NOT3_NOTP12_Msk (0x01UL << GPIO_PORT_NOT3_NOTP12_Pos) /*!< GPIO_PORT NOT3: NOTP12 Mask */
+#define GPIO_PORT_NOT3_NOTP13_Pos 13 /*!< GPIO_PORT NOT3: NOTP13 Position */
+#define GPIO_PORT_NOT3_NOTP13_Msk (0x01UL << GPIO_PORT_NOT3_NOTP13_Pos) /*!< GPIO_PORT NOT3: NOTP13 Mask */
+#define GPIO_PORT_NOT3_NOTP14_Pos 14 /*!< GPIO_PORT NOT3: NOTP14 Position */
+#define GPIO_PORT_NOT3_NOTP14_Msk (0x01UL << GPIO_PORT_NOT3_NOTP14_Pos) /*!< GPIO_PORT NOT3: NOTP14 Mask */
+#define GPIO_PORT_NOT3_NOTP15_Pos 15 /*!< GPIO_PORT NOT3: NOTP15 Position */
+#define GPIO_PORT_NOT3_NOTP15_Msk (0x01UL << GPIO_PORT_NOT3_NOTP15_Pos) /*!< GPIO_PORT NOT3: NOTP15 Mask */
+#define GPIO_PORT_NOT3_NOTP16_Pos 16 /*!< GPIO_PORT NOT3: NOTP16 Position */
+#define GPIO_PORT_NOT3_NOTP16_Msk (0x01UL << GPIO_PORT_NOT3_NOTP16_Pos) /*!< GPIO_PORT NOT3: NOTP16 Mask */
+#define GPIO_PORT_NOT3_NOTP17_Pos 17 /*!< GPIO_PORT NOT3: NOTP17 Position */
+#define GPIO_PORT_NOT3_NOTP17_Msk (0x01UL << GPIO_PORT_NOT3_NOTP17_Pos) /*!< GPIO_PORT NOT3: NOTP17 Mask */
+#define GPIO_PORT_NOT3_NOTP18_Pos 18 /*!< GPIO_PORT NOT3: NOTP18 Position */
+#define GPIO_PORT_NOT3_NOTP18_Msk (0x01UL << GPIO_PORT_NOT3_NOTP18_Pos) /*!< GPIO_PORT NOT3: NOTP18 Mask */
+#define GPIO_PORT_NOT3_NOTP19_Pos 19 /*!< GPIO_PORT NOT3: NOTP19 Position */
+#define GPIO_PORT_NOT3_NOTP19_Msk (0x01UL << GPIO_PORT_NOT3_NOTP19_Pos) /*!< GPIO_PORT NOT3: NOTP19 Mask */
+#define GPIO_PORT_NOT3_NOTP20_Pos 20 /*!< GPIO_PORT NOT3: NOTP20 Position */
+#define GPIO_PORT_NOT3_NOTP20_Msk (0x01UL << GPIO_PORT_NOT3_NOTP20_Pos) /*!< GPIO_PORT NOT3: NOTP20 Mask */
+#define GPIO_PORT_NOT3_NOTP21_Pos 21 /*!< GPIO_PORT NOT3: NOTP21 Position */
+#define GPIO_PORT_NOT3_NOTP21_Msk (0x01UL << GPIO_PORT_NOT3_NOTP21_Pos) /*!< GPIO_PORT NOT3: NOTP21 Mask */
+#define GPIO_PORT_NOT3_NOTP22_Pos 22 /*!< GPIO_PORT NOT3: NOTP22 Position */
+#define GPIO_PORT_NOT3_NOTP22_Msk (0x01UL << GPIO_PORT_NOT3_NOTP22_Pos) /*!< GPIO_PORT NOT3: NOTP22 Mask */
+#define GPIO_PORT_NOT3_NOTP23_Pos 23 /*!< GPIO_PORT NOT3: NOTP23 Position */
+#define GPIO_PORT_NOT3_NOTP23_Msk (0x01UL << GPIO_PORT_NOT3_NOTP23_Pos) /*!< GPIO_PORT NOT3: NOTP23 Mask */
+#define GPIO_PORT_NOT3_NOTP24_Pos 24 /*!< GPIO_PORT NOT3: NOTP24 Position */
+#define GPIO_PORT_NOT3_NOTP24_Msk (0x01UL << GPIO_PORT_NOT3_NOTP24_Pos) /*!< GPIO_PORT NOT3: NOTP24 Mask */
+#define GPIO_PORT_NOT3_NOTP25_Pos 25 /*!< GPIO_PORT NOT3: NOTP25 Position */
+#define GPIO_PORT_NOT3_NOTP25_Msk (0x01UL << GPIO_PORT_NOT3_NOTP25_Pos) /*!< GPIO_PORT NOT3: NOTP25 Mask */
+#define GPIO_PORT_NOT3_NOTP26_Pos 26 /*!< GPIO_PORT NOT3: NOTP26 Position */
+#define GPIO_PORT_NOT3_NOTP26_Msk (0x01UL << GPIO_PORT_NOT3_NOTP26_Pos) /*!< GPIO_PORT NOT3: NOTP26 Mask */
+#define GPIO_PORT_NOT3_NOTP27_Pos 27 /*!< GPIO_PORT NOT3: NOTP27 Position */
+#define GPIO_PORT_NOT3_NOTP27_Msk (0x01UL << GPIO_PORT_NOT3_NOTP27_Pos) /*!< GPIO_PORT NOT3: NOTP27 Mask */
+#define GPIO_PORT_NOT3_NOTP28_Pos 28 /*!< GPIO_PORT NOT3: NOTP28 Position */
+#define GPIO_PORT_NOT3_NOTP28_Msk (0x01UL << GPIO_PORT_NOT3_NOTP28_Pos) /*!< GPIO_PORT NOT3: NOTP28 Mask */
+#define GPIO_PORT_NOT3_NOTP29_Pos 29 /*!< GPIO_PORT NOT3: NOTP29 Position */
+#define GPIO_PORT_NOT3_NOTP29_Msk (0x01UL << GPIO_PORT_NOT3_NOTP29_Pos) /*!< GPIO_PORT NOT3: NOTP29 Mask */
+#define GPIO_PORT_NOT3_NOTP30_Pos 30 /*!< GPIO_PORT NOT3: NOTP30 Position */
+#define GPIO_PORT_NOT3_NOTP30_Msk (0x01UL << GPIO_PORT_NOT3_NOTP30_Pos) /*!< GPIO_PORT NOT3: NOTP30 Mask */
+#define GPIO_PORT_NOT3_NOTP31_Pos 31 /*!< GPIO_PORT NOT3: NOTP31 Position */
+#define GPIO_PORT_NOT3_NOTP31_Msk (0x01UL << GPIO_PORT_NOT3_NOTP31_Pos) /*!< GPIO_PORT NOT3: NOTP31 Mask */
+
+// ------------------------------------- GPIO_PORT_NOT4 -----------------------------------------
+#define GPIO_PORT_NOT4_NOTP0_Pos 0 /*!< GPIO_PORT NOT4: NOTP0 Position */
+#define GPIO_PORT_NOT4_NOTP0_Msk (0x01UL << GPIO_PORT_NOT4_NOTP0_Pos) /*!< GPIO_PORT NOT4: NOTP0 Mask */
+#define GPIO_PORT_NOT4_NOTP1_Pos 1 /*!< GPIO_PORT NOT4: NOTP1 Position */
+#define GPIO_PORT_NOT4_NOTP1_Msk (0x01UL << GPIO_PORT_NOT4_NOTP1_Pos) /*!< GPIO_PORT NOT4: NOTP1 Mask */
+#define GPIO_PORT_NOT4_NOTP2_Pos 2 /*!< GPIO_PORT NOT4: NOTP2 Position */
+#define GPIO_PORT_NOT4_NOTP2_Msk (0x01UL << GPIO_PORT_NOT4_NOTP2_Pos) /*!< GPIO_PORT NOT4: NOTP2 Mask */
+#define GPIO_PORT_NOT4_NOTP3_Pos 3 /*!< GPIO_PORT NOT4: NOTP3 Position */
+#define GPIO_PORT_NOT4_NOTP3_Msk (0x01UL << GPIO_PORT_NOT4_NOTP3_Pos) /*!< GPIO_PORT NOT4: NOTP3 Mask */
+#define GPIO_PORT_NOT4_NOTP4_Pos 4 /*!< GPIO_PORT NOT4: NOTP4 Position */
+#define GPIO_PORT_NOT4_NOTP4_Msk (0x01UL << GPIO_PORT_NOT4_NOTP4_Pos) /*!< GPIO_PORT NOT4: NOTP4 Mask */
+#define GPIO_PORT_NOT4_NOTP5_Pos 5 /*!< GPIO_PORT NOT4: NOTP5 Position */
+#define GPIO_PORT_NOT4_NOTP5_Msk (0x01UL << GPIO_PORT_NOT4_NOTP5_Pos) /*!< GPIO_PORT NOT4: NOTP5 Mask */
+#define GPIO_PORT_NOT4_NOTP6_Pos 6 /*!< GPIO_PORT NOT4: NOTP6 Position */
+#define GPIO_PORT_NOT4_NOTP6_Msk (0x01UL << GPIO_PORT_NOT4_NOTP6_Pos) /*!< GPIO_PORT NOT4: NOTP6 Mask */
+#define GPIO_PORT_NOT4_NOTP7_Pos 7 /*!< GPIO_PORT NOT4: NOTP7 Position */
+#define GPIO_PORT_NOT4_NOTP7_Msk (0x01UL << GPIO_PORT_NOT4_NOTP7_Pos) /*!< GPIO_PORT NOT4: NOTP7 Mask */
+#define GPIO_PORT_NOT4_NOTP8_Pos 8 /*!< GPIO_PORT NOT4: NOTP8 Position */
+#define GPIO_PORT_NOT4_NOTP8_Msk (0x01UL << GPIO_PORT_NOT4_NOTP8_Pos) /*!< GPIO_PORT NOT4: NOTP8 Mask */
+#define GPIO_PORT_NOT4_NOTP9_Pos 9 /*!< GPIO_PORT NOT4: NOTP9 Position */
+#define GPIO_PORT_NOT4_NOTP9_Msk (0x01UL << GPIO_PORT_NOT4_NOTP9_Pos) /*!< GPIO_PORT NOT4: NOTP9 Mask */
+#define GPIO_PORT_NOT4_NOTP10_Pos 10 /*!< GPIO_PORT NOT4: NOTP10 Position */
+#define GPIO_PORT_NOT4_NOTP10_Msk (0x01UL << GPIO_PORT_NOT4_NOTP10_Pos) /*!< GPIO_PORT NOT4: NOTP10 Mask */
+#define GPIO_PORT_NOT4_NOTP11_Pos 11 /*!< GPIO_PORT NOT4: NOTP11 Position */
+#define GPIO_PORT_NOT4_NOTP11_Msk (0x01UL << GPIO_PORT_NOT4_NOTP11_Pos) /*!< GPIO_PORT NOT4: NOTP11 Mask */
+#define GPIO_PORT_NOT4_NOTP12_Pos 12 /*!< GPIO_PORT NOT4: NOTP12 Position */
+#define GPIO_PORT_NOT4_NOTP12_Msk (0x01UL << GPIO_PORT_NOT4_NOTP12_Pos) /*!< GPIO_PORT NOT4: NOTP12 Mask */
+#define GPIO_PORT_NOT4_NOTP13_Pos 13 /*!< GPIO_PORT NOT4: NOTP13 Position */
+#define GPIO_PORT_NOT4_NOTP13_Msk (0x01UL << GPIO_PORT_NOT4_NOTP13_Pos) /*!< GPIO_PORT NOT4: NOTP13 Mask */
+#define GPIO_PORT_NOT4_NOTP14_Pos 14 /*!< GPIO_PORT NOT4: NOTP14 Position */
+#define GPIO_PORT_NOT4_NOTP14_Msk (0x01UL << GPIO_PORT_NOT4_NOTP14_Pos) /*!< GPIO_PORT NOT4: NOTP14 Mask */
+#define GPIO_PORT_NOT4_NOTP15_Pos 15 /*!< GPIO_PORT NOT4: NOTP15 Position */
+#define GPIO_PORT_NOT4_NOTP15_Msk (0x01UL << GPIO_PORT_NOT4_NOTP15_Pos) /*!< GPIO_PORT NOT4: NOTP15 Mask */
+#define GPIO_PORT_NOT4_NOTP16_Pos 16 /*!< GPIO_PORT NOT4: NOTP16 Position */
+#define GPIO_PORT_NOT4_NOTP16_Msk (0x01UL << GPIO_PORT_NOT4_NOTP16_Pos) /*!< GPIO_PORT NOT4: NOTP16 Mask */
+#define GPIO_PORT_NOT4_NOTP17_Pos 17 /*!< GPIO_PORT NOT4: NOTP17 Position */
+#define GPIO_PORT_NOT4_NOTP17_Msk (0x01UL << GPIO_PORT_NOT4_NOTP17_Pos) /*!< GPIO_PORT NOT4: NOTP17 Mask */
+#define GPIO_PORT_NOT4_NOTP18_Pos 18 /*!< GPIO_PORT NOT4: NOTP18 Position */
+#define GPIO_PORT_NOT4_NOTP18_Msk (0x01UL << GPIO_PORT_NOT4_NOTP18_Pos) /*!< GPIO_PORT NOT4: NOTP18 Mask */
+#define GPIO_PORT_NOT4_NOTP19_Pos 19 /*!< GPIO_PORT NOT4: NOTP19 Position */
+#define GPIO_PORT_NOT4_NOTP19_Msk (0x01UL << GPIO_PORT_NOT4_NOTP19_Pos) /*!< GPIO_PORT NOT4: NOTP19 Mask */
+#define GPIO_PORT_NOT4_NOTP20_Pos 20 /*!< GPIO_PORT NOT4: NOTP20 Position */
+#define GPIO_PORT_NOT4_NOTP20_Msk (0x01UL << GPIO_PORT_NOT4_NOTP20_Pos) /*!< GPIO_PORT NOT4: NOTP20 Mask */
+#define GPIO_PORT_NOT4_NOTP21_Pos 21 /*!< GPIO_PORT NOT4: NOTP21 Position */
+#define GPIO_PORT_NOT4_NOTP21_Msk (0x01UL << GPIO_PORT_NOT4_NOTP21_Pos) /*!< GPIO_PORT NOT4: NOTP21 Mask */
+#define GPIO_PORT_NOT4_NOTP22_Pos 22 /*!< GPIO_PORT NOT4: NOTP22 Position */
+#define GPIO_PORT_NOT4_NOTP22_Msk (0x01UL << GPIO_PORT_NOT4_NOTP22_Pos) /*!< GPIO_PORT NOT4: NOTP22 Mask */
+#define GPIO_PORT_NOT4_NOTP23_Pos 23 /*!< GPIO_PORT NOT4: NOTP23 Position */
+#define GPIO_PORT_NOT4_NOTP23_Msk (0x01UL << GPIO_PORT_NOT4_NOTP23_Pos) /*!< GPIO_PORT NOT4: NOTP23 Mask */
+#define GPIO_PORT_NOT4_NOTP24_Pos 24 /*!< GPIO_PORT NOT4: NOTP24 Position */
+#define GPIO_PORT_NOT4_NOTP24_Msk (0x01UL << GPIO_PORT_NOT4_NOTP24_Pos) /*!< GPIO_PORT NOT4: NOTP24 Mask */
+#define GPIO_PORT_NOT4_NOTP25_Pos 25 /*!< GPIO_PORT NOT4: NOTP25 Position */
+#define GPIO_PORT_NOT4_NOTP25_Msk (0x01UL << GPIO_PORT_NOT4_NOTP25_Pos) /*!< GPIO_PORT NOT4: NOTP25 Mask */
+#define GPIO_PORT_NOT4_NOTP26_Pos 26 /*!< GPIO_PORT NOT4: NOTP26 Position */
+#define GPIO_PORT_NOT4_NOTP26_Msk (0x01UL << GPIO_PORT_NOT4_NOTP26_Pos) /*!< GPIO_PORT NOT4: NOTP26 Mask */
+#define GPIO_PORT_NOT4_NOTP27_Pos 27 /*!< GPIO_PORT NOT4: NOTP27 Position */
+#define GPIO_PORT_NOT4_NOTP27_Msk (0x01UL << GPIO_PORT_NOT4_NOTP27_Pos) /*!< GPIO_PORT NOT4: NOTP27 Mask */
+#define GPIO_PORT_NOT4_NOTP28_Pos 28 /*!< GPIO_PORT NOT4: NOTP28 Position */
+#define GPIO_PORT_NOT4_NOTP28_Msk (0x01UL << GPIO_PORT_NOT4_NOTP28_Pos) /*!< GPIO_PORT NOT4: NOTP28 Mask */
+#define GPIO_PORT_NOT4_NOTP29_Pos 29 /*!< GPIO_PORT NOT4: NOTP29 Position */
+#define GPIO_PORT_NOT4_NOTP29_Msk (0x01UL << GPIO_PORT_NOT4_NOTP29_Pos) /*!< GPIO_PORT NOT4: NOTP29 Mask */
+#define GPIO_PORT_NOT4_NOTP30_Pos 30 /*!< GPIO_PORT NOT4: NOTP30 Position */
+#define GPIO_PORT_NOT4_NOTP30_Msk (0x01UL << GPIO_PORT_NOT4_NOTP30_Pos) /*!< GPIO_PORT NOT4: NOTP30 Mask */
+#define GPIO_PORT_NOT4_NOTP31_Pos 31 /*!< GPIO_PORT NOT4: NOTP31 Position */
+#define GPIO_PORT_NOT4_NOTP31_Msk (0x01UL << GPIO_PORT_NOT4_NOTP31_Pos) /*!< GPIO_PORT NOT4: NOTP31 Mask */
+
+// ------------------------------------- GPIO_PORT_NOT5 -----------------------------------------
+#define GPIO_PORT_NOT5_NOTP0_Pos 0 /*!< GPIO_PORT NOT5: NOTP0 Position */
+#define GPIO_PORT_NOT5_NOTP0_Msk (0x01UL << GPIO_PORT_NOT5_NOTP0_Pos) /*!< GPIO_PORT NOT5: NOTP0 Mask */
+#define GPIO_PORT_NOT5_NOTP1_Pos 1 /*!< GPIO_PORT NOT5: NOTP1 Position */
+#define GPIO_PORT_NOT5_NOTP1_Msk (0x01UL << GPIO_PORT_NOT5_NOTP1_Pos) /*!< GPIO_PORT NOT5: NOTP1 Mask */
+#define GPIO_PORT_NOT5_NOTP2_Pos 2 /*!< GPIO_PORT NOT5: NOTP2 Position */
+#define GPIO_PORT_NOT5_NOTP2_Msk (0x01UL << GPIO_PORT_NOT5_NOTP2_Pos) /*!< GPIO_PORT NOT5: NOTP2 Mask */
+#define GPIO_PORT_NOT5_NOTP3_Pos 3 /*!< GPIO_PORT NOT5: NOTP3 Position */
+#define GPIO_PORT_NOT5_NOTP3_Msk (0x01UL << GPIO_PORT_NOT5_NOTP3_Pos) /*!< GPIO_PORT NOT5: NOTP3 Mask */
+#define GPIO_PORT_NOT5_NOTP4_Pos 4 /*!< GPIO_PORT NOT5: NOTP4 Position */
+#define GPIO_PORT_NOT5_NOTP4_Msk (0x01UL << GPIO_PORT_NOT5_NOTP4_Pos) /*!< GPIO_PORT NOT5: NOTP4 Mask */
+#define GPIO_PORT_NOT5_NOTP5_Pos 5 /*!< GPIO_PORT NOT5: NOTP5 Position */
+#define GPIO_PORT_NOT5_NOTP5_Msk (0x01UL << GPIO_PORT_NOT5_NOTP5_Pos) /*!< GPIO_PORT NOT5: NOTP5 Mask */
+#define GPIO_PORT_NOT5_NOTP6_Pos 6 /*!< GPIO_PORT NOT5: NOTP6 Position */
+#define GPIO_PORT_NOT5_NOTP6_Msk (0x01UL << GPIO_PORT_NOT5_NOTP6_Pos) /*!< GPIO_PORT NOT5: NOTP6 Mask */
+#define GPIO_PORT_NOT5_NOTP7_Pos 7 /*!< GPIO_PORT NOT5: NOTP7 Position */
+#define GPIO_PORT_NOT5_NOTP7_Msk (0x01UL << GPIO_PORT_NOT5_NOTP7_Pos) /*!< GPIO_PORT NOT5: NOTP7 Mask */
+#define GPIO_PORT_NOT5_NOTP8_Pos 8 /*!< GPIO_PORT NOT5: NOTP8 Position */
+#define GPIO_PORT_NOT5_NOTP8_Msk (0x01UL << GPIO_PORT_NOT5_NOTP8_Pos) /*!< GPIO_PORT NOT5: NOTP8 Mask */
+#define GPIO_PORT_NOT5_NOTP9_Pos 9 /*!< GPIO_PORT NOT5: NOTP9 Position */
+#define GPIO_PORT_NOT5_NOTP9_Msk (0x01UL << GPIO_PORT_NOT5_NOTP9_Pos) /*!< GPIO_PORT NOT5: NOTP9 Mask */
+#define GPIO_PORT_NOT5_NOTP10_Pos 10 /*!< GPIO_PORT NOT5: NOTP10 Position */
+#define GPIO_PORT_NOT5_NOTP10_Msk (0x01UL << GPIO_PORT_NOT5_NOTP10_Pos) /*!< GPIO_PORT NOT5: NOTP10 Mask */
+#define GPIO_PORT_NOT5_NOTP11_Pos 11 /*!< GPIO_PORT NOT5: NOTP11 Position */
+#define GPIO_PORT_NOT5_NOTP11_Msk (0x01UL << GPIO_PORT_NOT5_NOTP11_Pos) /*!< GPIO_PORT NOT5: NOTP11 Mask */
+#define GPIO_PORT_NOT5_NOTP12_Pos 12 /*!< GPIO_PORT NOT5: NOTP12 Position */
+#define GPIO_PORT_NOT5_NOTP12_Msk (0x01UL << GPIO_PORT_NOT5_NOTP12_Pos) /*!< GPIO_PORT NOT5: NOTP12 Mask */
+#define GPIO_PORT_NOT5_NOTP13_Pos 13 /*!< GPIO_PORT NOT5: NOTP13 Position */
+#define GPIO_PORT_NOT5_NOTP13_Msk (0x01UL << GPIO_PORT_NOT5_NOTP13_Pos) /*!< GPIO_PORT NOT5: NOTP13 Mask */
+#define GPIO_PORT_NOT5_NOTP14_Pos 14 /*!< GPIO_PORT NOT5: NOTP14 Position */
+#define GPIO_PORT_NOT5_NOTP14_Msk (0x01UL << GPIO_PORT_NOT5_NOTP14_Pos) /*!< GPIO_PORT NOT5: NOTP14 Mask */
+#define GPIO_PORT_NOT5_NOTP15_Pos 15 /*!< GPIO_PORT NOT5: NOTP15 Position */
+#define GPIO_PORT_NOT5_NOTP15_Msk (0x01UL << GPIO_PORT_NOT5_NOTP15_Pos) /*!< GPIO_PORT NOT5: NOTP15 Mask */
+#define GPIO_PORT_NOT5_NOTP16_Pos 16 /*!< GPIO_PORT NOT5: NOTP16 Position */
+#define GPIO_PORT_NOT5_NOTP16_Msk (0x01UL << GPIO_PORT_NOT5_NOTP16_Pos) /*!< GPIO_PORT NOT5: NOTP16 Mask */
+#define GPIO_PORT_NOT5_NOTP17_Pos 17 /*!< GPIO_PORT NOT5: NOTP17 Position */
+#define GPIO_PORT_NOT5_NOTP17_Msk (0x01UL << GPIO_PORT_NOT5_NOTP17_Pos) /*!< GPIO_PORT NOT5: NOTP17 Mask */
+#define GPIO_PORT_NOT5_NOTP18_Pos 18 /*!< GPIO_PORT NOT5: NOTP18 Position */
+#define GPIO_PORT_NOT5_NOTP18_Msk (0x01UL << GPIO_PORT_NOT5_NOTP18_Pos) /*!< GPIO_PORT NOT5: NOTP18 Mask */
+#define GPIO_PORT_NOT5_NOTP19_Pos 19 /*!< GPIO_PORT NOT5: NOTP19 Position */
+#define GPIO_PORT_NOT5_NOTP19_Msk (0x01UL << GPIO_PORT_NOT5_NOTP19_Pos) /*!< GPIO_PORT NOT5: NOTP19 Mask */
+#define GPIO_PORT_NOT5_NOTP20_Pos 20 /*!< GPIO_PORT NOT5: NOTP20 Position */
+#define GPIO_PORT_NOT5_NOTP20_Msk (0x01UL << GPIO_PORT_NOT5_NOTP20_Pos) /*!< GPIO_PORT NOT5: NOTP20 Mask */
+#define GPIO_PORT_NOT5_NOTP21_Pos 21 /*!< GPIO_PORT NOT5: NOTP21 Position */
+#define GPIO_PORT_NOT5_NOTP21_Msk (0x01UL << GPIO_PORT_NOT5_NOTP21_Pos) /*!< GPIO_PORT NOT5: NOTP21 Mask */
+#define GPIO_PORT_NOT5_NOTP22_Pos 22 /*!< GPIO_PORT NOT5: NOTP22 Position */
+#define GPIO_PORT_NOT5_NOTP22_Msk (0x01UL << GPIO_PORT_NOT5_NOTP22_Pos) /*!< GPIO_PORT NOT5: NOTP22 Mask */
+#define GPIO_PORT_NOT5_NOTP23_Pos 23 /*!< GPIO_PORT NOT5: NOTP23 Position */
+#define GPIO_PORT_NOT5_NOTP23_Msk (0x01UL << GPIO_PORT_NOT5_NOTP23_Pos) /*!< GPIO_PORT NOT5: NOTP23 Mask */
+#define GPIO_PORT_NOT5_NOTP24_Pos 24 /*!< GPIO_PORT NOT5: NOTP24 Position */
+#define GPIO_PORT_NOT5_NOTP24_Msk (0x01UL << GPIO_PORT_NOT5_NOTP24_Pos) /*!< GPIO_PORT NOT5: NOTP24 Mask */
+#define GPIO_PORT_NOT5_NOTP25_Pos 25 /*!< GPIO_PORT NOT5: NOTP25 Position */
+#define GPIO_PORT_NOT5_NOTP25_Msk (0x01UL << GPIO_PORT_NOT5_NOTP25_Pos) /*!< GPIO_PORT NOT5: NOTP25 Mask */
+#define GPIO_PORT_NOT5_NOTP26_Pos 26 /*!< GPIO_PORT NOT5: NOTP26 Position */
+#define GPIO_PORT_NOT5_NOTP26_Msk (0x01UL << GPIO_PORT_NOT5_NOTP26_Pos) /*!< GPIO_PORT NOT5: NOTP26 Mask */
+#define GPIO_PORT_NOT5_NOTP27_Pos 27 /*!< GPIO_PORT NOT5: NOTP27 Position */
+#define GPIO_PORT_NOT5_NOTP27_Msk (0x01UL << GPIO_PORT_NOT5_NOTP27_Pos) /*!< GPIO_PORT NOT5: NOTP27 Mask */
+#define GPIO_PORT_NOT5_NOTP28_Pos 28 /*!< GPIO_PORT NOT5: NOTP28 Position */
+#define GPIO_PORT_NOT5_NOTP28_Msk (0x01UL << GPIO_PORT_NOT5_NOTP28_Pos) /*!< GPIO_PORT NOT5: NOTP28 Mask */
+#define GPIO_PORT_NOT5_NOTP29_Pos 29 /*!< GPIO_PORT NOT5: NOTP29 Position */
+#define GPIO_PORT_NOT5_NOTP29_Msk (0x01UL << GPIO_PORT_NOT5_NOTP29_Pos) /*!< GPIO_PORT NOT5: NOTP29 Mask */
+#define GPIO_PORT_NOT5_NOTP30_Pos 30 /*!< GPIO_PORT NOT5: NOTP30 Position */
+#define GPIO_PORT_NOT5_NOTP30_Msk (0x01UL << GPIO_PORT_NOT5_NOTP30_Pos) /*!< GPIO_PORT NOT5: NOTP30 Mask */
+#define GPIO_PORT_NOT5_NOTP31_Pos 31 /*!< GPIO_PORT NOT5: NOTP31 Position */
+#define GPIO_PORT_NOT5_NOTP31_Msk (0x01UL << GPIO_PORT_NOT5_NOTP31_Pos) /*!< GPIO_PORT NOT5: NOTP31 Mask */
+
+// ------------------------------------- GPIO_PORT_NOT6 -----------------------------------------
+#define GPIO_PORT_NOT6_NOTP0_Pos 0 /*!< GPIO_PORT NOT6: NOTP0 Position */
+#define GPIO_PORT_NOT6_NOTP0_Msk (0x01UL << GPIO_PORT_NOT6_NOTP0_Pos) /*!< GPIO_PORT NOT6: NOTP0 Mask */
+#define GPIO_PORT_NOT6_NOTP1_Pos 1 /*!< GPIO_PORT NOT6: NOTP1 Position */
+#define GPIO_PORT_NOT6_NOTP1_Msk (0x01UL << GPIO_PORT_NOT6_NOTP1_Pos) /*!< GPIO_PORT NOT6: NOTP1 Mask */
+#define GPIO_PORT_NOT6_NOTP2_Pos 2 /*!< GPIO_PORT NOT6: NOTP2 Position */
+#define GPIO_PORT_NOT6_NOTP2_Msk (0x01UL << GPIO_PORT_NOT6_NOTP2_Pos) /*!< GPIO_PORT NOT6: NOTP2 Mask */
+#define GPIO_PORT_NOT6_NOTP3_Pos 3 /*!< GPIO_PORT NOT6: NOTP3 Position */
+#define GPIO_PORT_NOT6_NOTP3_Msk (0x01UL << GPIO_PORT_NOT6_NOTP3_Pos) /*!< GPIO_PORT NOT6: NOTP3 Mask */
+#define GPIO_PORT_NOT6_NOTP4_Pos 4 /*!< GPIO_PORT NOT6: NOTP4 Position */
+#define GPIO_PORT_NOT6_NOTP4_Msk (0x01UL << GPIO_PORT_NOT6_NOTP4_Pos) /*!< GPIO_PORT NOT6: NOTP4 Mask */
+#define GPIO_PORT_NOT6_NOTP5_Pos 5 /*!< GPIO_PORT NOT6: NOTP5 Position */
+#define GPIO_PORT_NOT6_NOTP5_Msk (0x01UL << GPIO_PORT_NOT6_NOTP5_Pos) /*!< GPIO_PORT NOT6: NOTP5 Mask */
+#define GPIO_PORT_NOT6_NOTP6_Pos 6 /*!< GPIO_PORT NOT6: NOTP6 Position */
+#define GPIO_PORT_NOT6_NOTP6_Msk (0x01UL << GPIO_PORT_NOT6_NOTP6_Pos) /*!< GPIO_PORT NOT6: NOTP6 Mask */
+#define GPIO_PORT_NOT6_NOTP7_Pos 7 /*!< GPIO_PORT NOT6: NOTP7 Position */
+#define GPIO_PORT_NOT6_NOTP7_Msk (0x01UL << GPIO_PORT_NOT6_NOTP7_Pos) /*!< GPIO_PORT NOT6: NOTP7 Mask */
+#define GPIO_PORT_NOT6_NOTP8_Pos 8 /*!< GPIO_PORT NOT6: NOTP8 Position */
+#define GPIO_PORT_NOT6_NOTP8_Msk (0x01UL << GPIO_PORT_NOT6_NOTP8_Pos) /*!< GPIO_PORT NOT6: NOTP8 Mask */
+#define GPIO_PORT_NOT6_NOTP9_Pos 9 /*!< GPIO_PORT NOT6: NOTP9 Position */
+#define GPIO_PORT_NOT6_NOTP9_Msk (0x01UL << GPIO_PORT_NOT6_NOTP9_Pos) /*!< GPIO_PORT NOT6: NOTP9 Mask */
+#define GPIO_PORT_NOT6_NOTP10_Pos 10 /*!< GPIO_PORT NOT6: NOTP10 Position */
+#define GPIO_PORT_NOT6_NOTP10_Msk (0x01UL << GPIO_PORT_NOT6_NOTP10_Pos) /*!< GPIO_PORT NOT6: NOTP10 Mask */
+#define GPIO_PORT_NOT6_NOTP11_Pos 11 /*!< GPIO_PORT NOT6: NOTP11 Position */
+#define GPIO_PORT_NOT6_NOTP11_Msk (0x01UL << GPIO_PORT_NOT6_NOTP11_Pos) /*!< GPIO_PORT NOT6: NOTP11 Mask */
+#define GPIO_PORT_NOT6_NOTP12_Pos 12 /*!< GPIO_PORT NOT6: NOTP12 Position */
+#define GPIO_PORT_NOT6_NOTP12_Msk (0x01UL << GPIO_PORT_NOT6_NOTP12_Pos) /*!< GPIO_PORT NOT6: NOTP12 Mask */
+#define GPIO_PORT_NOT6_NOTP13_Pos 13 /*!< GPIO_PORT NOT6: NOTP13 Position */
+#define GPIO_PORT_NOT6_NOTP13_Msk (0x01UL << GPIO_PORT_NOT6_NOTP13_Pos) /*!< GPIO_PORT NOT6: NOTP13 Mask */
+#define GPIO_PORT_NOT6_NOTP14_Pos 14 /*!< GPIO_PORT NOT6: NOTP14 Position */
+#define GPIO_PORT_NOT6_NOTP14_Msk (0x01UL << GPIO_PORT_NOT6_NOTP14_Pos) /*!< GPIO_PORT NOT6: NOTP14 Mask */
+#define GPIO_PORT_NOT6_NOTP15_Pos 15 /*!< GPIO_PORT NOT6: NOTP15 Position */
+#define GPIO_PORT_NOT6_NOTP15_Msk (0x01UL << GPIO_PORT_NOT6_NOTP15_Pos) /*!< GPIO_PORT NOT6: NOTP15 Mask */
+#define GPIO_PORT_NOT6_NOTP16_Pos 16 /*!< GPIO_PORT NOT6: NOTP16 Position */
+#define GPIO_PORT_NOT6_NOTP16_Msk (0x01UL << GPIO_PORT_NOT6_NOTP16_Pos) /*!< GPIO_PORT NOT6: NOTP16 Mask */
+#define GPIO_PORT_NOT6_NOTP17_Pos 17 /*!< GPIO_PORT NOT6: NOTP17 Position */
+#define GPIO_PORT_NOT6_NOTP17_Msk (0x01UL << GPIO_PORT_NOT6_NOTP17_Pos) /*!< GPIO_PORT NOT6: NOTP17 Mask */
+#define GPIO_PORT_NOT6_NOTP18_Pos 18 /*!< GPIO_PORT NOT6: NOTP18 Position */
+#define GPIO_PORT_NOT6_NOTP18_Msk (0x01UL << GPIO_PORT_NOT6_NOTP18_Pos) /*!< GPIO_PORT NOT6: NOTP18 Mask */
+#define GPIO_PORT_NOT6_NOTP19_Pos 19 /*!< GPIO_PORT NOT6: NOTP19 Position */
+#define GPIO_PORT_NOT6_NOTP19_Msk (0x01UL << GPIO_PORT_NOT6_NOTP19_Pos) /*!< GPIO_PORT NOT6: NOTP19 Mask */
+#define GPIO_PORT_NOT6_NOTP20_Pos 20 /*!< GPIO_PORT NOT6: NOTP20 Position */
+#define GPIO_PORT_NOT6_NOTP20_Msk (0x01UL << GPIO_PORT_NOT6_NOTP20_Pos) /*!< GPIO_PORT NOT6: NOTP20 Mask */
+#define GPIO_PORT_NOT6_NOTP21_Pos 21 /*!< GPIO_PORT NOT6: NOTP21 Position */
+#define GPIO_PORT_NOT6_NOTP21_Msk (0x01UL << GPIO_PORT_NOT6_NOTP21_Pos) /*!< GPIO_PORT NOT6: NOTP21 Mask */
+#define GPIO_PORT_NOT6_NOTP22_Pos 22 /*!< GPIO_PORT NOT6: NOTP22 Position */
+#define GPIO_PORT_NOT6_NOTP22_Msk (0x01UL << GPIO_PORT_NOT6_NOTP22_Pos) /*!< GPIO_PORT NOT6: NOTP22 Mask */
+#define GPIO_PORT_NOT6_NOTP23_Pos 23 /*!< GPIO_PORT NOT6: NOTP23 Position */
+#define GPIO_PORT_NOT6_NOTP23_Msk (0x01UL << GPIO_PORT_NOT6_NOTP23_Pos) /*!< GPIO_PORT NOT6: NOTP23 Mask */
+#define GPIO_PORT_NOT6_NOTP24_Pos 24 /*!< GPIO_PORT NOT6: NOTP24 Position */
+#define GPIO_PORT_NOT6_NOTP24_Msk (0x01UL << GPIO_PORT_NOT6_NOTP24_Pos) /*!< GPIO_PORT NOT6: NOTP24 Mask */
+#define GPIO_PORT_NOT6_NOTP25_Pos 25 /*!< GPIO_PORT NOT6: NOTP25 Position */
+#define GPIO_PORT_NOT6_NOTP25_Msk (0x01UL << GPIO_PORT_NOT6_NOTP25_Pos) /*!< GPIO_PORT NOT6: NOTP25 Mask */
+#define GPIO_PORT_NOT6_NOTP26_Pos 26 /*!< GPIO_PORT NOT6: NOTP26 Position */
+#define GPIO_PORT_NOT6_NOTP26_Msk (0x01UL << GPIO_PORT_NOT6_NOTP26_Pos) /*!< GPIO_PORT NOT6: NOTP26 Mask */
+#define GPIO_PORT_NOT6_NOTP27_Pos 27 /*!< GPIO_PORT NOT6: NOTP27 Position */
+#define GPIO_PORT_NOT6_NOTP27_Msk (0x01UL << GPIO_PORT_NOT6_NOTP27_Pos) /*!< GPIO_PORT NOT6: NOTP27 Mask */
+#define GPIO_PORT_NOT6_NOTP28_Pos 28 /*!< GPIO_PORT NOT6: NOTP28 Position */
+#define GPIO_PORT_NOT6_NOTP28_Msk (0x01UL << GPIO_PORT_NOT6_NOTP28_Pos) /*!< GPIO_PORT NOT6: NOTP28 Mask */
+#define GPIO_PORT_NOT6_NOTP29_Pos 29 /*!< GPIO_PORT NOT6: NOTP29 Position */
+#define GPIO_PORT_NOT6_NOTP29_Msk (0x01UL << GPIO_PORT_NOT6_NOTP29_Pos) /*!< GPIO_PORT NOT6: NOTP29 Mask */
+#define GPIO_PORT_NOT6_NOTP30_Pos 30 /*!< GPIO_PORT NOT6: NOTP30 Position */
+#define GPIO_PORT_NOT6_NOTP30_Msk (0x01UL << GPIO_PORT_NOT6_NOTP30_Pos) /*!< GPIO_PORT NOT6: NOTP30 Mask */
+#define GPIO_PORT_NOT6_NOTP31_Pos 31 /*!< GPIO_PORT NOT6: NOTP31 Position */
+#define GPIO_PORT_NOT6_NOTP31_Msk (0x01UL << GPIO_PORT_NOT6_NOTP31_Pos) /*!< GPIO_PORT NOT6: NOTP31 Mask */
+
+// ------------------------------------- GPIO_PORT_NOT7 -----------------------------------------
+#define GPIO_PORT_NOT7_NOTP0_Pos 0 /*!< GPIO_PORT NOT7: NOTP0 Position */
+#define GPIO_PORT_NOT7_NOTP0_Msk (0x01UL << GPIO_PORT_NOT7_NOTP0_Pos) /*!< GPIO_PORT NOT7: NOTP0 Mask */
+#define GPIO_PORT_NOT7_NOTP1_Pos 1 /*!< GPIO_PORT NOT7: NOTP1 Position */
+#define GPIO_PORT_NOT7_NOTP1_Msk (0x01UL << GPIO_PORT_NOT7_NOTP1_Pos) /*!< GPIO_PORT NOT7: NOTP1 Mask */
+#define GPIO_PORT_NOT7_NOTP2_Pos 2 /*!< GPIO_PORT NOT7: NOTP2 Position */
+#define GPIO_PORT_NOT7_NOTP2_Msk (0x01UL << GPIO_PORT_NOT7_NOTP2_Pos) /*!< GPIO_PORT NOT7: NOTP2 Mask */
+#define GPIO_PORT_NOT7_NOTP3_Pos 3 /*!< GPIO_PORT NOT7: NOTP3 Position */
+#define GPIO_PORT_NOT7_NOTP3_Msk (0x01UL << GPIO_PORT_NOT7_NOTP3_Pos) /*!< GPIO_PORT NOT7: NOTP3 Mask */
+#define GPIO_PORT_NOT7_NOTP4_Pos 4 /*!< GPIO_PORT NOT7: NOTP4 Position */
+#define GPIO_PORT_NOT7_NOTP4_Msk (0x01UL << GPIO_PORT_NOT7_NOTP4_Pos) /*!< GPIO_PORT NOT7: NOTP4 Mask */
+#define GPIO_PORT_NOT7_NOTP5_Pos 5 /*!< GPIO_PORT NOT7: NOTP5 Position */
+#define GPIO_PORT_NOT7_NOTP5_Msk (0x01UL << GPIO_PORT_NOT7_NOTP5_Pos) /*!< GPIO_PORT NOT7: NOTP5 Mask */
+#define GPIO_PORT_NOT7_NOTP6_Pos 6 /*!< GPIO_PORT NOT7: NOTP6 Position */
+#define GPIO_PORT_NOT7_NOTP6_Msk (0x01UL << GPIO_PORT_NOT7_NOTP6_Pos) /*!< GPIO_PORT NOT7: NOTP6 Mask */
+#define GPIO_PORT_NOT7_NOTP7_Pos 7 /*!< GPIO_PORT NOT7: NOTP7 Position */
+#define GPIO_PORT_NOT7_NOTP7_Msk (0x01UL << GPIO_PORT_NOT7_NOTP7_Pos) /*!< GPIO_PORT NOT7: NOTP7 Mask */
+#define GPIO_PORT_NOT7_NOTP8_Pos 8 /*!< GPIO_PORT NOT7: NOTP8 Position */
+#define GPIO_PORT_NOT7_NOTP8_Msk (0x01UL << GPIO_PORT_NOT7_NOTP8_Pos) /*!< GPIO_PORT NOT7: NOTP8 Mask */
+#define GPIO_PORT_NOT7_NOTP9_Pos 9 /*!< GPIO_PORT NOT7: NOTP9 Position */
+#define GPIO_PORT_NOT7_NOTP9_Msk (0x01UL << GPIO_PORT_NOT7_NOTP9_Pos) /*!< GPIO_PORT NOT7: NOTP9 Mask */
+#define GPIO_PORT_NOT7_NOTP10_Pos 10 /*!< GPIO_PORT NOT7: NOTP10 Position */
+#define GPIO_PORT_NOT7_NOTP10_Msk (0x01UL << GPIO_PORT_NOT7_NOTP10_Pos) /*!< GPIO_PORT NOT7: NOTP10 Mask */
+#define GPIO_PORT_NOT7_NOTP11_Pos 11 /*!< GPIO_PORT NOT7: NOTP11 Position */
+#define GPIO_PORT_NOT7_NOTP11_Msk (0x01UL << GPIO_PORT_NOT7_NOTP11_Pos) /*!< GPIO_PORT NOT7: NOTP11 Mask */
+#define GPIO_PORT_NOT7_NOTP12_Pos 12 /*!< GPIO_PORT NOT7: NOTP12 Position */
+#define GPIO_PORT_NOT7_NOTP12_Msk (0x01UL << GPIO_PORT_NOT7_NOTP12_Pos) /*!< GPIO_PORT NOT7: NOTP12 Mask */
+#define GPIO_PORT_NOT7_NOTP13_Pos 13 /*!< GPIO_PORT NOT7: NOTP13 Position */
+#define GPIO_PORT_NOT7_NOTP13_Msk (0x01UL << GPIO_PORT_NOT7_NOTP13_Pos) /*!< GPIO_PORT NOT7: NOTP13 Mask */
+#define GPIO_PORT_NOT7_NOTP14_Pos 14 /*!< GPIO_PORT NOT7: NOTP14 Position */
+#define GPIO_PORT_NOT7_NOTP14_Msk (0x01UL << GPIO_PORT_NOT7_NOTP14_Pos) /*!< GPIO_PORT NOT7: NOTP14 Mask */
+#define GPIO_PORT_NOT7_NOTP15_Pos 15 /*!< GPIO_PORT NOT7: NOTP15 Position */
+#define GPIO_PORT_NOT7_NOTP15_Msk (0x01UL << GPIO_PORT_NOT7_NOTP15_Pos) /*!< GPIO_PORT NOT7: NOTP15 Mask */
+#define GPIO_PORT_NOT7_NOTP16_Pos 16 /*!< GPIO_PORT NOT7: NOTP16 Position */
+#define GPIO_PORT_NOT7_NOTP16_Msk (0x01UL << GPIO_PORT_NOT7_NOTP16_Pos) /*!< GPIO_PORT NOT7: NOTP16 Mask */
+#define GPIO_PORT_NOT7_NOTP17_Pos 17 /*!< GPIO_PORT NOT7: NOTP17 Position */
+#define GPIO_PORT_NOT7_NOTP17_Msk (0x01UL << GPIO_PORT_NOT7_NOTP17_Pos) /*!< GPIO_PORT NOT7: NOTP17 Mask */
+#define GPIO_PORT_NOT7_NOTP18_Pos 18 /*!< GPIO_PORT NOT7: NOTP18 Position */
+#define GPIO_PORT_NOT7_NOTP18_Msk (0x01UL << GPIO_PORT_NOT7_NOTP18_Pos) /*!< GPIO_PORT NOT7: NOTP18 Mask */
+#define GPIO_PORT_NOT7_NOTP19_Pos 19 /*!< GPIO_PORT NOT7: NOTP19 Position */
+#define GPIO_PORT_NOT7_NOTP19_Msk (0x01UL << GPIO_PORT_NOT7_NOTP19_Pos) /*!< GPIO_PORT NOT7: NOTP19 Mask */
+#define GPIO_PORT_NOT7_NOTP20_Pos 20 /*!< GPIO_PORT NOT7: NOTP20 Position */
+#define GPIO_PORT_NOT7_NOTP20_Msk (0x01UL << GPIO_PORT_NOT7_NOTP20_Pos) /*!< GPIO_PORT NOT7: NOTP20 Mask */
+#define GPIO_PORT_NOT7_NOTP21_Pos 21 /*!< GPIO_PORT NOT7: NOTP21 Position */
+#define GPIO_PORT_NOT7_NOTP21_Msk (0x01UL << GPIO_PORT_NOT7_NOTP21_Pos) /*!< GPIO_PORT NOT7: NOTP21 Mask */
+#define GPIO_PORT_NOT7_NOTP22_Pos 22 /*!< GPIO_PORT NOT7: NOTP22 Position */
+#define GPIO_PORT_NOT7_NOTP22_Msk (0x01UL << GPIO_PORT_NOT7_NOTP22_Pos) /*!< GPIO_PORT NOT7: NOTP22 Mask */
+#define GPIO_PORT_NOT7_NOTP23_Pos 23 /*!< GPIO_PORT NOT7: NOTP23 Position */
+#define GPIO_PORT_NOT7_NOTP23_Msk (0x01UL << GPIO_PORT_NOT7_NOTP23_Pos) /*!< GPIO_PORT NOT7: NOTP23 Mask */
+#define GPIO_PORT_NOT7_NOTP24_Pos 24 /*!< GPIO_PORT NOT7: NOTP24 Position */
+#define GPIO_PORT_NOT7_NOTP24_Msk (0x01UL << GPIO_PORT_NOT7_NOTP24_Pos) /*!< GPIO_PORT NOT7: NOTP24 Mask */
+#define GPIO_PORT_NOT7_NOTP25_Pos 25 /*!< GPIO_PORT NOT7: NOTP25 Position */
+#define GPIO_PORT_NOT7_NOTP25_Msk (0x01UL << GPIO_PORT_NOT7_NOTP25_Pos) /*!< GPIO_PORT NOT7: NOTP25 Mask */
+#define GPIO_PORT_NOT7_NOTP26_Pos 26 /*!< GPIO_PORT NOT7: NOTP26 Position */
+#define GPIO_PORT_NOT7_NOTP26_Msk (0x01UL << GPIO_PORT_NOT7_NOTP26_Pos) /*!< GPIO_PORT NOT7: NOTP26 Mask */
+#define GPIO_PORT_NOT7_NOTP27_Pos 27 /*!< GPIO_PORT NOT7: NOTP27 Position */
+#define GPIO_PORT_NOT7_NOTP27_Msk (0x01UL << GPIO_PORT_NOT7_NOTP27_Pos) /*!< GPIO_PORT NOT7: NOTP27 Mask */
+#define GPIO_PORT_NOT7_NOTP28_Pos 28 /*!< GPIO_PORT NOT7: NOTP28 Position */
+#define GPIO_PORT_NOT7_NOTP28_Msk (0x01UL << GPIO_PORT_NOT7_NOTP28_Pos) /*!< GPIO_PORT NOT7: NOTP28 Mask */
+#define GPIO_PORT_NOT7_NOTP29_Pos 29 /*!< GPIO_PORT NOT7: NOTP29 Position */
+#define GPIO_PORT_NOT7_NOTP29_Msk (0x01UL << GPIO_PORT_NOT7_NOTP29_Pos) /*!< GPIO_PORT NOT7: NOTP29 Mask */
+#define GPIO_PORT_NOT7_NOTP30_Pos 30 /*!< GPIO_PORT NOT7: NOTP30 Position */
+#define GPIO_PORT_NOT7_NOTP30_Msk (0x01UL << GPIO_PORT_NOT7_NOTP30_Pos) /*!< GPIO_PORT NOT7: NOTP30 Mask */
+#define GPIO_PORT_NOT7_NOTP31_Pos 31 /*!< GPIO_PORT NOT7: NOTP31 Position */
+#define GPIO_PORT_NOT7_NOTP31_Msk (0x01UL << GPIO_PORT_NOT7_NOTP31_Pos) /*!< GPIO_PORT NOT7: NOTP31 Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SPI Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------------- SPI_CR ---------------------------------------------
+#define SPI_CR_BITENABLE_Pos 2 /*!< SPI CR: BITENABLE Position */
+#define SPI_CR_BITENABLE_Msk (0x01UL << SPI_CR_BITENABLE_Pos) /*!< SPI CR: BITENABLE Mask */
+#define SPI_CR_CPHA_Pos 3 /*!< SPI CR: CPHA Position */
+#define SPI_CR_CPHA_Msk (0x01UL << SPI_CR_CPHA_Pos) /*!< SPI CR: CPHA Mask */
+#define SPI_CR_CPOL_Pos 4 /*!< SPI CR: CPOL Position */
+#define SPI_CR_CPOL_Msk (0x01UL << SPI_CR_CPOL_Pos) /*!< SPI CR: CPOL Mask */
+#define SPI_CR_MSTR_Pos 5 /*!< SPI CR: MSTR Position */
+#define SPI_CR_MSTR_Msk (0x01UL << SPI_CR_MSTR_Pos) /*!< SPI CR: MSTR Mask */
+#define SPI_CR_LSBF_Pos 6 /*!< SPI CR: LSBF Position */
+#define SPI_CR_LSBF_Msk (0x01UL << SPI_CR_LSBF_Pos) /*!< SPI CR: LSBF Mask */
+#define SPI_CR_SPIE_Pos 7 /*!< SPI CR: SPIE Position */
+#define SPI_CR_SPIE_Msk (0x01UL << SPI_CR_SPIE_Pos) /*!< SPI CR: SPIE Mask */
+#define SPI_CR_BITS_Pos 8 /*!< SPI CR: BITS Position */
+#define SPI_CR_BITS_Msk (0x0fUL << SPI_CR_BITS_Pos) /*!< SPI CR: BITS Mask */
+
+// ----------------------------------------- SPI_SR ---------------------------------------------
+#define SPI_SR_ABRT_Pos 3 /*!< SPI SR: ABRT Position */
+#define SPI_SR_ABRT_Msk (0x01UL << SPI_SR_ABRT_Pos) /*!< SPI SR: ABRT Mask */
+#define SPI_SR_MODF_Pos 4 /*!< SPI SR: MODF Position */
+#define SPI_SR_MODF_Msk (0x01UL << SPI_SR_MODF_Pos) /*!< SPI SR: MODF Mask */
+#define SPI_SR_ROVR_Pos 5 /*!< SPI SR: ROVR Position */
+#define SPI_SR_ROVR_Msk (0x01UL << SPI_SR_ROVR_Pos) /*!< SPI SR: ROVR Mask */
+#define SPI_SR_WCOL_Pos 6 /*!< SPI SR: WCOL Position */
+#define SPI_SR_WCOL_Msk (0x01UL << SPI_SR_WCOL_Pos) /*!< SPI SR: WCOL Mask */
+#define SPI_SR_SPIF_Pos 7 /*!< SPI SR: SPIF Position */
+#define SPI_SR_SPIF_Msk (0x01UL << SPI_SR_SPIF_Pos) /*!< SPI SR: SPIF Mask */
+
+// ----------------------------------------- SPI_DR ---------------------------------------------
+#define SPI_DR_DATALOW_Pos 0 /*!< SPI DR: DATALOW Position */
+#define SPI_DR_DATALOW_Msk (0x000000ffUL << SPI_DR_DATALOW_Pos) /*!< SPI DR: DATALOW Mask */
+#define SPI_DR_DATAHIGH_Pos 8 /*!< SPI DR: DATAHIGH Position */
+#define SPI_DR_DATAHIGH_Msk (0x000000ffUL << SPI_DR_DATAHIGH_Pos) /*!< SPI DR: DATAHIGH Mask */
+
+// ----------------------------------------- SPI_CCR --------------------------------------------
+#define SPI_CCR_COUNTER_Pos 0 /*!< SPI CCR: COUNTER Position */
+#define SPI_CCR_COUNTER_Msk (0x000000ffUL << SPI_CCR_COUNTER_Pos) /*!< SPI CCR: COUNTER Mask */
+
+// ----------------------------------------- SPI_TCR --------------------------------------------
+#define SPI_TCR_TEST_Pos 1 /*!< SPI TCR: TEST Position */
+#define SPI_TCR_TEST_Msk (0x7fUL << SPI_TCR_TEST_Pos) /*!< SPI TCR: TEST Mask */
+
+// ----------------------------------------- SPI_TSR --------------------------------------------
+#define SPI_TSR_ABRT_Pos 3 /*!< SPI TSR: ABRT Position */
+#define SPI_TSR_ABRT_Msk (0x01UL << SPI_TSR_ABRT_Pos) /*!< SPI TSR: ABRT Mask */
+#define SPI_TSR_MODF_Pos 4 /*!< SPI TSR: MODF Position */
+#define SPI_TSR_MODF_Msk (0x01UL << SPI_TSR_MODF_Pos) /*!< SPI TSR: MODF Mask */
+#define SPI_TSR_ROVR_Pos 5 /*!< SPI TSR: ROVR Position */
+#define SPI_TSR_ROVR_Msk (0x01UL << SPI_TSR_ROVR_Pos) /*!< SPI TSR: ROVR Mask */
+#define SPI_TSR_WCOL_Pos 6 /*!< SPI TSR: WCOL Position */
+#define SPI_TSR_WCOL_Msk (0x01UL << SPI_TSR_WCOL_Pos) /*!< SPI TSR: WCOL Mask */
+#define SPI_TSR_SPIF_Pos 7 /*!< SPI TSR: SPIF Position */
+#define SPI_TSR_SPIF_Msk (0x01UL << SPI_TSR_SPIF_Pos) /*!< SPI TSR: SPIF Mask */
+
+// ----------------------------------------- SPI_INT --------------------------------------------
+#define SPI_INT_SPIF_Pos 0 /*!< SPI INT: SPIF Position */
+#define SPI_INT_SPIF_Msk (0x01UL << SPI_INT_SPIF_Pos) /*!< SPI INT: SPIF Mask */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SGPIO Position & Mask -----
+// ------------------------------------------------------------------------------------------------
+
+
+// ----------------------------------- SGPIO_OUT_MUX_CFG0 ---------------------------------------
+#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG0: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG0_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG0: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG0_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG0: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG0_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG0_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG0: P_OE_CFG Mask */
+
+// ----------------------------------- SGPIO_OUT_MUX_CFG1 ---------------------------------------
+#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG1: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG1_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG1: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG1_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG1: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG1_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG1_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG1: P_OE_CFG Mask */
+
+// ----------------------------------- SGPIO_OUT_MUX_CFG2 ---------------------------------------
+#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG2: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG2_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG2: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG2_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG2: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG2_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG2_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG2: P_OE_CFG Mask */
+
+// ----------------------------------- SGPIO_OUT_MUX_CFG3 ---------------------------------------
+#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG3: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG3_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG3: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG3_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG3: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG3_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG3_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG3: P_OE_CFG Mask */
+
+// ----------------------------------- SGPIO_OUT_MUX_CFG4 ---------------------------------------
+#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG4: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG4_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG4: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG4_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG4: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG4_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG4_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG4: P_OE_CFG Mask */
+
+// ----------------------------------- SGPIO_OUT_MUX_CFG5 ---------------------------------------
+#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG5: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG5_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG5: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG5_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG5: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG5_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG5_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG5: P_OE_CFG Mask */
+
+// ----------------------------------- SGPIO_OUT_MUX_CFG6 ---------------------------------------
+#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG6: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG6_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG6: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG6_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG6: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG6_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG6_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG6: P_OE_CFG Mask */
+
+// ----------------------------------- SGPIO_OUT_MUX_CFG7 ---------------------------------------
+#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG7: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG7_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG7: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG7_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG7: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG7_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG7_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG7: P_OE_CFG Mask */
+
+// ----------------------------------- SGPIO_OUT_MUX_CFG8 ---------------------------------------
+#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG8: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG8_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG8: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG8_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG8: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG8_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG8_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG8: P_OE_CFG Mask */
+
+// ----------------------------------- SGPIO_OUT_MUX_CFG9 ---------------------------------------
+#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG9: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG9_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG9: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG9_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG9: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG9_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG9_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG9: P_OE_CFG Mask */
+
+// ----------------------------------- SGPIO_OUT_MUX_CFG10 --------------------------------------
+#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG10: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG10_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG10: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG10_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG10: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG10_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG10_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG10: P_OE_CFG Mask */
+
+// ----------------------------------- SGPIO_OUT_MUX_CFG11 --------------------------------------
+#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG11: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG11_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG11: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG11_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG11: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG11_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG11_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG11: P_OE_CFG Mask */
+
+// ----------------------------------- SGPIO_OUT_MUX_CFG12 --------------------------------------
+#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG12: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG12_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG12: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG12_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG12: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG12_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG12_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG12: P_OE_CFG Mask */
+
+// ----------------------------------- SGPIO_OUT_MUX_CFG13 --------------------------------------
+#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG13: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG13_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG13: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG13_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG13: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG13_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG13_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG13: P_OE_CFG Mask */
+
+// ----------------------------------- SGPIO_OUT_MUX_CFG14 --------------------------------------
+#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG14: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG14_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG14: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG14_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG14: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG14_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG14_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG14: P_OE_CFG Mask */
+
+// ----------------------------------- SGPIO_OUT_MUX_CFG15 --------------------------------------
+#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG15: P_OUT_CFG Position */
+#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG15_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG15: P_OUT_CFG Mask */
+#define SGPIO_OUT_MUX_CFG15_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG15: P_OE_CFG Position */
+#define SGPIO_OUT_MUX_CFG15_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG15_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG15: P_OE_CFG Mask */
+
+// ---------------------------------- SGPIO_SGPIO_MUX_CFG0 --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG0_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG0: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG0_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG0_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG0: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG0: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG0: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG0: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG0: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG0_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG0: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG0_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG0: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG0: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG0_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG0: CONCAT_ORDER Mask */
+
+// ---------------------------------- SGPIO_SGPIO_MUX_CFG1 --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG1_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG1: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG1_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG1_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG1: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG1: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG1: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG1: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG1: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG1_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG1: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG1_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG1: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG1: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG1_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG1: CONCAT_ORDER Mask */
+
+// ---------------------------------- SGPIO_SGPIO_MUX_CFG2 --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG2_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG2: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG2_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG2_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG2: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG2: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG2: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG2: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG2: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG2_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG2: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG2_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG2: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG2: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG2_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG2: CONCAT_ORDER Mask */
+
+// ---------------------------------- SGPIO_SGPIO_MUX_CFG3 --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG3_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG3: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG3_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG3_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG3: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG3: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG3: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG3: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG3: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG3_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG3: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG3_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG3: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG3: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG3_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG3: CONCAT_ORDER Mask */
+
+// ---------------------------------- SGPIO_SGPIO_MUX_CFG4 --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG4_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG4: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG4_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG4_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG4: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG4: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG4: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG4: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG4: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG4_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG4: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG4_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG4: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG4: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG4_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG4: CONCAT_ORDER Mask */
+
+// ---------------------------------- SGPIO_SGPIO_MUX_CFG5 --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG5_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG5: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG5_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG5_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG5: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG5: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG5: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG5: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG5: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG5_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG5: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG5_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG5: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG5: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG5_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG5: CONCAT_ORDER Mask */
+
+// ---------------------------------- SGPIO_SGPIO_MUX_CFG6 --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG6_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG6: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG6_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG6_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG6: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG6: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG6: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG6: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG6: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG6_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG6: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG6_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG6: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG6: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG6_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG6: CONCAT_ORDER Mask */
+
+// ---------------------------------- SGPIO_SGPIO_MUX_CFG7 --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG7_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG7: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG7_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG7_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG7: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG7: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG7: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG7: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG7: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG7_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG7: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG7_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG7: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG7: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG7_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG7: CONCAT_ORDER Mask */
+
+// ---------------------------------- SGPIO_SGPIO_MUX_CFG8 --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG8_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG8: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG8_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG8_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG8: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG8: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG8: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG8: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG8: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG8_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG8: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG8_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG8: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG8: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG8_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG8: CONCAT_ORDER Mask */
+
+// ---------------------------------- SGPIO_SGPIO_MUX_CFG9 --------------------------------------
+#define SGPIO_SGPIO_MUX_CFG9_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG9: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG9_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG9_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG9: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG9: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG9: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG9: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG9: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG9_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG9: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG9_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG9: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG9: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG9_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG9: CONCAT_ORDER Mask */
+
+// ---------------------------------- SGPIO_SGPIO_MUX_CFG10 -------------------------------------
+#define SGPIO_SGPIO_MUX_CFG10_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG10: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG10_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG10_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG10: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG10: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG10: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG10: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG10: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG10_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG10: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG10_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG10: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG10: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG10_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG10: CONCAT_ORDER Mask */
+
+// ---------------------------------- SGPIO_SGPIO_MUX_CFG11 -------------------------------------
+#define SGPIO_SGPIO_MUX_CFG11_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG11: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG11_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG11_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG11: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG11: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG11: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG11: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG11: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG11_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG11: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG11_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG11: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG11: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG11_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG11: CONCAT_ORDER Mask */
+
+// ---------------------------------- SGPIO_SGPIO_MUX_CFG12 -------------------------------------
+#define SGPIO_SGPIO_MUX_CFG12_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG12: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG12_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG12_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG12: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG12: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG12: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG12: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG12: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG12_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG12: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG12_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG12: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG12: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG12_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG12: CONCAT_ORDER Mask */
+
+// ---------------------------------- SGPIO_SGPIO_MUX_CFG13 -------------------------------------
+#define SGPIO_SGPIO_MUX_CFG13_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG13: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG13_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG13_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG13: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG13: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG13: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG13: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG13: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG13_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG13: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG13_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG13: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG13: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG13_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG13: CONCAT_ORDER Mask */
+
+// ---------------------------------- SGPIO_SGPIO_MUX_CFG14 -------------------------------------
+#define SGPIO_SGPIO_MUX_CFG14_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG14: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG14_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG14_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG14: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG14: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG14: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG14: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG14: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG14_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG14: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG14_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG14: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG14: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG14_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG14: CONCAT_ORDER Mask */
+
+// ---------------------------------- SGPIO_SGPIO_MUX_CFG15 -------------------------------------
+#define SGPIO_SGPIO_MUX_CFG15_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG15: EXT_CLK_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG15_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG15_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG15: EXT_CLK_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG15: CLK_SOURCE_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG15: CLK_SOURCE_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG15: CLK_SOURCE_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG15: CLK_SOURCE_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG15_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_PIN_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_PIN_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_SLICE_MODE Position */
+#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_SLICE_MODE Mask */
+#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG15: CONCAT_ENABLE Position */
+#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG15_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG15: CONCAT_ENABLE Mask */
+#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG15: CONCAT_ORDER Position */
+#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG15_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG15: CONCAT_ORDER Mask */
+
+// ---------------------------------- SGPIO_SLICE_MUX_CFG0 --------------------------------------
+#define SGPIO_SLICE_MUX_CFG0_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG0: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG0_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG0_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG0: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG0: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG0: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG0: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG0: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG0: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG0: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG0: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG0: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG0: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG0: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG0: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG0: INV_QUALIFIER Mask */
+
+// ---------------------------------- SGPIO_SLICE_MUX_CFG1 --------------------------------------
+#define SGPIO_SLICE_MUX_CFG1_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG1: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG1_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG1_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG1: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG1: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG1: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG1: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG1: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG1: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG1: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG1: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG1: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG1: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG1: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG1: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG1: INV_QUALIFIER Mask */
+
+// ---------------------------------- SGPIO_SLICE_MUX_CFG2 --------------------------------------
+#define SGPIO_SLICE_MUX_CFG2_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG2: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG2_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG2_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG2: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG2: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG2: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG2: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG2: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG2: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG2: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG2: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG2: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG2: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG2: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG2: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG2: INV_QUALIFIER Mask */
+
+// ---------------------------------- SGPIO_SLICE_MUX_CFG3 --------------------------------------
+#define SGPIO_SLICE_MUX_CFG3_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG3: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG3_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG3_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG3: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG3: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG3: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG3: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG3: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG3: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG3: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG3: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG3: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG3: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG3: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG3: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG3: INV_QUALIFIER Mask */
+
+// ---------------------------------- SGPIO_SLICE_MUX_CFG4 --------------------------------------
+#define SGPIO_SLICE_MUX_CFG4_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG4: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG4_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG4_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG4: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG4: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG4: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG4: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG4: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG4: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG4: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG4: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG4: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG4: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG4: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG4: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG4: INV_QUALIFIER Mask */
+
+// ---------------------------------- SGPIO_SLICE_MUX_CFG5 --------------------------------------
+#define SGPIO_SLICE_MUX_CFG5_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG5: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG5_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG5_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG5: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG5: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG5: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG5: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG5: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG5: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG5: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG5: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG5: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG5: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG5: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG5: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG5: INV_QUALIFIER Mask */
+
+// ---------------------------------- SGPIO_SLICE_MUX_CFG6 --------------------------------------
+#define SGPIO_SLICE_MUX_CFG6_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG6: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG6_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG6_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG6: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG6: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG6: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG6: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG6: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG6: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG6: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG6: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG6: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG6: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG6: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG6: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG6: INV_QUALIFIER Mask */
+
+// ---------------------------------- SGPIO_SLICE_MUX_CFG7 --------------------------------------
+#define SGPIO_SLICE_MUX_CFG7_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG7: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG7_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG7_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG7: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG7: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG7: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG7: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG7: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG7: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG7: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG7: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG7: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG7: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG7: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG7: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG7: INV_QUALIFIER Mask */
+
+// ---------------------------------- SGPIO_SLICE_MUX_CFG8 --------------------------------------
+#define SGPIO_SLICE_MUX_CFG8_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG8: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG8_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG8_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG8: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG8: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG8: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG8: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG8: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG8: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG8: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG8: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG8: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG8: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG8: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG8: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG8: INV_QUALIFIER Mask */
+
+// ---------------------------------- SGPIO_SLICE_MUX_CFG9 --------------------------------------
+#define SGPIO_SLICE_MUX_CFG9_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG9: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG9_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG9_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG9: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG9: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG9: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG9: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG9: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG9: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG9: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG9: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG9: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG9: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG9: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG9: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG9: INV_QUALIFIER Mask */
+
+// ---------------------------------- SGPIO_SLICE_MUX_CFG10 -------------------------------------
+#define SGPIO_SLICE_MUX_CFG10_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG10: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG10_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG10_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG10: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG10: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG10: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG10: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG10: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG10: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG10: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG10: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG10: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG10: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG10: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG10: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG10: INV_QUALIFIER Mask */
+
+// ---------------------------------- SGPIO_SLICE_MUX_CFG11 -------------------------------------
+#define SGPIO_SLICE_MUX_CFG11_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG11: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG11_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG11_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG11: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG11: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG11: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG11: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG11: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG11: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG11: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG11: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG11: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG11: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG11: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG11: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG11: INV_QUALIFIER Mask */
+
+// ---------------------------------- SGPIO_SLICE_MUX_CFG12 -------------------------------------
+#define SGPIO_SLICE_MUX_CFG12_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG12: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG12_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG12_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG12: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG12: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG12: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG12: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG12: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG12: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG12: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG12: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG12: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG12: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG12: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG12: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG12: INV_QUALIFIER Mask */
+
+// ---------------------------------- SGPIO_SLICE_MUX_CFG13 -------------------------------------
+#define SGPIO_SLICE_MUX_CFG13_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG13: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG13_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG13_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG13: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG13: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG13: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG13: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG13: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG13: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG13: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG13: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG13: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG13: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG13: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG13: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG13: INV_QUALIFIER Mask */
+
+// ---------------------------------- SGPIO_SLICE_MUX_CFG14 -------------------------------------
+#define SGPIO_SLICE_MUX_CFG14_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG14: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG14_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG14_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG14: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG14: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG14: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG14: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG14: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG14: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG14: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG14: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG14: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG14: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG14: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG14: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG14: INV_QUALIFIER Mask */
+
+// ---------------------------------- SGPIO_SLICE_MUX_CFG15 -------------------------------------
+#define SGPIO_SLICE_MUX_CFG15_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG15: MATCH_MODE Position */
+#define SGPIO_SLICE_MUX_CFG15_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG15_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG15: MATCH_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG15: CLK_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG15: CLK_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG15: CLKGEN_MODE Position */
+#define SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG15: CLKGEN_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG15: INV_OUT_CLK Position */
+#define SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG15: INV_OUT_CLK Mask */
+#define SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG15: DATA_CAPTURE_MODE Position */
+#define SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG15: DATA_CAPTURE_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG15: PARALLEL_MODE Position */
+#define SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG15: PARALLEL_MODE Mask */
+#define SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG15: INV_QUALIFIER Position */
+#define SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG15: INV_QUALIFIER Mask */
+
+// --------------------------------------- SGPIO_REG0 -------------------------------------------
+#define SGPIO_REG0_REG_Pos 0 /*!< SGPIO REG0: REG Position */
+#define SGPIO_REG0_REG_Msk (0xffffffffUL << SGPIO_REG0_REG_Pos) /*!< SGPIO REG0: REG Mask */
+
+// --------------------------------------- SGPIO_REG1 -------------------------------------------
+#define SGPIO_REG1_REG_Pos 0 /*!< SGPIO REG1: REG Position */
+#define SGPIO_REG1_REG_Msk (0xffffffffUL << SGPIO_REG1_REG_Pos) /*!< SGPIO REG1: REG Mask */
+
+// --------------------------------------- SGPIO_REG2 -------------------------------------------
+#define SGPIO_REG2_REG_Pos 0 /*!< SGPIO REG2: REG Position */
+#define SGPIO_REG2_REG_Msk (0xffffffffUL << SGPIO_REG2_REG_Pos) /*!< SGPIO REG2: REG Mask */
+
+// --------------------------------------- SGPIO_REG3 -------------------------------------------
+#define SGPIO_REG3_REG_Pos 0 /*!< SGPIO REG3: REG Position */
+#define SGPIO_REG3_REG_Msk (0xffffffffUL << SGPIO_REG3_REG_Pos) /*!< SGPIO REG3: REG Mask */
+
+// --------------------------------------- SGPIO_REG4 -------------------------------------------
+#define SGPIO_REG4_REG_Pos 0 /*!< SGPIO REG4: REG Position */
+#define SGPIO_REG4_REG_Msk (0xffffffffUL << SGPIO_REG4_REG_Pos) /*!< SGPIO REG4: REG Mask */
+
+// --------------------------------------- SGPIO_REG5 -------------------------------------------
+#define SGPIO_REG5_REG_Pos 0 /*!< SGPIO REG5: REG Position */
+#define SGPIO_REG5_REG_Msk (0xffffffffUL << SGPIO_REG5_REG_Pos) /*!< SGPIO REG5: REG Mask */
+
+// --------------------------------------- SGPIO_REG6 -------------------------------------------
+#define SGPIO_REG6_REG_Pos 0 /*!< SGPIO REG6: REG Position */
+#define SGPIO_REG6_REG_Msk (0xffffffffUL << SGPIO_REG6_REG_Pos) /*!< SGPIO REG6: REG Mask */
+
+// --------------------------------------- SGPIO_REG7 -------------------------------------------
+#define SGPIO_REG7_REG_Pos 0 /*!< SGPIO REG7: REG Position */
+#define SGPIO_REG7_REG_Msk (0xffffffffUL << SGPIO_REG7_REG_Pos) /*!< SGPIO REG7: REG Mask */
+
+// --------------------------------------- SGPIO_REG8 -------------------------------------------
+#define SGPIO_REG8_REG_Pos 0 /*!< SGPIO REG8: REG Position */
+#define SGPIO_REG8_REG_Msk (0xffffffffUL << SGPIO_REG8_REG_Pos) /*!< SGPIO REG8: REG Mask */
+
+// --------------------------------------- SGPIO_REG9 -------------------------------------------
+#define SGPIO_REG9_REG_Pos 0 /*!< SGPIO REG9: REG Position */
+#define SGPIO_REG9_REG_Msk (0xffffffffUL << SGPIO_REG9_REG_Pos) /*!< SGPIO REG9: REG Mask */
+
+// --------------------------------------- SGPIO_REG10 ------------------------------------------
+#define SGPIO_REG10_REG_Pos 0 /*!< SGPIO REG10: REG Position */
+#define SGPIO_REG10_REG_Msk (0xffffffffUL << SGPIO_REG10_REG_Pos) /*!< SGPIO REG10: REG Mask */
+
+// --------------------------------------- SGPIO_REG11 ------------------------------------------
+#define SGPIO_REG11_REG_Pos 0 /*!< SGPIO REG11: REG Position */
+#define SGPIO_REG11_REG_Msk (0xffffffffUL << SGPIO_REG11_REG_Pos) /*!< SGPIO REG11: REG Mask */
+
+// --------------------------------------- SGPIO_REG12 ------------------------------------------
+#define SGPIO_REG12_REG_Pos 0 /*!< SGPIO REG12: REG Position */
+#define SGPIO_REG12_REG_Msk (0xffffffffUL << SGPIO_REG12_REG_Pos) /*!< SGPIO REG12: REG Mask */
+
+// --------------------------------------- SGPIO_REG13 ------------------------------------------
+#define SGPIO_REG13_REG_Pos 0 /*!< SGPIO REG13: REG Position */
+#define SGPIO_REG13_REG_Msk (0xffffffffUL << SGPIO_REG13_REG_Pos) /*!< SGPIO REG13: REG Mask */
+
+// --------------------------------------- SGPIO_REG14 ------------------------------------------
+#define SGPIO_REG14_REG_Pos 0 /*!< SGPIO REG14: REG Position */
+#define SGPIO_REG14_REG_Msk (0xffffffffUL << SGPIO_REG14_REG_Pos) /*!< SGPIO REG14: REG Mask */
+
+// --------------------------------------- SGPIO_REG15 ------------------------------------------
+#define SGPIO_REG15_REG_Pos 0 /*!< SGPIO REG15: REG Position */
+#define SGPIO_REG15_REG_Msk (0xffffffffUL << SGPIO_REG15_REG_Pos) /*!< SGPIO REG15: REG Mask */
+
+// -------------------------------------- SGPIO_REG_SS0 -----------------------------------------
+#define SGPIO_REG_SS0_REG_SS_Pos 0 /*!< SGPIO REG_SS0: REG_SS Position */
+#define SGPIO_REG_SS0_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS0_REG_SS_Pos) /*!< SGPIO REG_SS0: REG_SS Mask */
+
+// -------------------------------------- SGPIO_REG_SS1 -----------------------------------------
+#define SGPIO_REG_SS1_REG_SS_Pos 0 /*!< SGPIO REG_SS1: REG_SS Position */
+#define SGPIO_REG_SS1_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS1_REG_SS_Pos) /*!< SGPIO REG_SS1: REG_SS Mask */
+
+// -------------------------------------- SGPIO_REG_SS2 -----------------------------------------
+#define SGPIO_REG_SS2_REG_SS_Pos 0 /*!< SGPIO REG_SS2: REG_SS Position */
+#define SGPIO_REG_SS2_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS2_REG_SS_Pos) /*!< SGPIO REG_SS2: REG_SS Mask */
+
+// -------------------------------------- SGPIO_REG_SS3 -----------------------------------------
+#define SGPIO_REG_SS3_REG_SS_Pos 0 /*!< SGPIO REG_SS3: REG_SS Position */
+#define SGPIO_REG_SS3_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS3_REG_SS_Pos) /*!< SGPIO REG_SS3: REG_SS Mask */
+
+// -------------------------------------- SGPIO_REG_SS4 -----------------------------------------
+#define SGPIO_REG_SS4_REG_SS_Pos 0 /*!< SGPIO REG_SS4: REG_SS Position */
+#define SGPIO_REG_SS4_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS4_REG_SS_Pos) /*!< SGPIO REG_SS4: REG_SS Mask */
+
+// -------------------------------------- SGPIO_REG_SS5 -----------------------------------------
+#define SGPIO_REG_SS5_REG_SS_Pos 0 /*!< SGPIO REG_SS5: REG_SS Position */
+#define SGPIO_REG_SS5_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS5_REG_SS_Pos) /*!< SGPIO REG_SS5: REG_SS Mask */
+
+// -------------------------------------- SGPIO_REG_SS6 -----------------------------------------
+#define SGPIO_REG_SS6_REG_SS_Pos 0 /*!< SGPIO REG_SS6: REG_SS Position */
+#define SGPIO_REG_SS6_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS6_REG_SS_Pos) /*!< SGPIO REG_SS6: REG_SS Mask */
+
+// -------------------------------------- SGPIO_REG_SS7 -----------------------------------------
+#define SGPIO_REG_SS7_REG_SS_Pos 0 /*!< SGPIO REG_SS7: REG_SS Position */
+#define SGPIO_REG_SS7_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS7_REG_SS_Pos) /*!< SGPIO REG_SS7: REG_SS Mask */
+
+// -------------------------------------- SGPIO_REG_SS8 -----------------------------------------
+#define SGPIO_REG_SS8_REG_SS_Pos 0 /*!< SGPIO REG_SS8: REG_SS Position */
+#define SGPIO_REG_SS8_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS8_REG_SS_Pos) /*!< SGPIO REG_SS8: REG_SS Mask */
+
+// -------------------------------------- SGPIO_REG_SS9 -----------------------------------------
+#define SGPIO_REG_SS9_REG_SS_Pos 0 /*!< SGPIO REG_SS9: REG_SS Position */
+#define SGPIO_REG_SS9_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS9_REG_SS_Pos) /*!< SGPIO REG_SS9: REG_SS Mask */
+
+// ------------------------------------- SGPIO_REG_SS10 -----------------------------------------
+#define SGPIO_REG_SS10_REG_SS_Pos 0 /*!< SGPIO REG_SS10: REG_SS Position */
+#define SGPIO_REG_SS10_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS10_REG_SS_Pos) /*!< SGPIO REG_SS10: REG_SS Mask */
+
+// ------------------------------------- SGPIO_REG_SS11 -----------------------------------------
+#define SGPIO_REG_SS11_REG_SS_Pos 0 /*!< SGPIO REG_SS11: REG_SS Position */
+#define SGPIO_REG_SS11_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS11_REG_SS_Pos) /*!< SGPIO REG_SS11: REG_SS Mask */
+
+// ------------------------------------- SGPIO_REG_SS12 -----------------------------------------
+#define SGPIO_REG_SS12_REG_SS_Pos 0 /*!< SGPIO REG_SS12: REG_SS Position */
+#define SGPIO_REG_SS12_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS12_REG_SS_Pos) /*!< SGPIO REG_SS12: REG_SS Mask */
+
+// ------------------------------------- SGPIO_REG_SS13 -----------------------------------------
+#define SGPIO_REG_SS13_REG_SS_Pos 0 /*!< SGPIO REG_SS13: REG_SS Position */
+#define SGPIO_REG_SS13_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS13_REG_SS_Pos) /*!< SGPIO REG_SS13: REG_SS Mask */
+
+// ------------------------------------- SGPIO_REG_SS14 -----------------------------------------
+#define SGPIO_REG_SS14_REG_SS_Pos 0 /*!< SGPIO REG_SS14: REG_SS Position */
+#define SGPIO_REG_SS14_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS14_REG_SS_Pos) /*!< SGPIO REG_SS14: REG_SS Mask */
+
+// ------------------------------------- SGPIO_REG_SS15 -----------------------------------------
+#define SGPIO_REG_SS15_REG_SS_Pos 0 /*!< SGPIO REG_SS15: REG_SS Position */
+#define SGPIO_REG_SS15_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS15_REG_SS_Pos) /*!< SGPIO REG_SS15: REG_SS Mask */
+
+// -------------------------------------- SGPIO_PRESET0 -----------------------------------------
+#define SGPIO_PRESET0_PRESET_Pos 0 /*!< SGPIO PRESET0: PRESET Position */
+#define SGPIO_PRESET0_PRESET_Msk (0x00000fffUL << SGPIO_PRESET0_PRESET_Pos) /*!< SGPIO PRESET0: PRESET Mask */
+
+// -------------------------------------- SGPIO_PRESET1 -----------------------------------------
+#define SGPIO_PRESET1_PRESET_Pos 0 /*!< SGPIO PRESET1: PRESET Position */
+#define SGPIO_PRESET1_PRESET_Msk (0x00000fffUL << SGPIO_PRESET1_PRESET_Pos) /*!< SGPIO PRESET1: PRESET Mask */
+
+// -------------------------------------- SGPIO_PRESET2 -----------------------------------------
+#define SGPIO_PRESET2_PRESET_Pos 0 /*!< SGPIO PRESET2: PRESET Position */
+#define SGPIO_PRESET2_PRESET_Msk (0x00000fffUL << SGPIO_PRESET2_PRESET_Pos) /*!< SGPIO PRESET2: PRESET Mask */
+
+// -------------------------------------- SGPIO_PRESET3 -----------------------------------------
+#define SGPIO_PRESET3_PRESET_Pos 0 /*!< SGPIO PRESET3: PRESET Position */
+#define SGPIO_PRESET3_PRESET_Msk (0x00000fffUL << SGPIO_PRESET3_PRESET_Pos) /*!< SGPIO PRESET3: PRESET Mask */
+
+// -------------------------------------- SGPIO_PRESET4 -----------------------------------------
+#define SGPIO_PRESET4_PRESET_Pos 0 /*!< SGPIO PRESET4: PRESET Position */
+#define SGPIO_PRESET4_PRESET_Msk (0x00000fffUL << SGPIO_PRESET4_PRESET_Pos) /*!< SGPIO PRESET4: PRESET Mask */
+
+// -------------------------------------- SGPIO_PRESET5 -----------------------------------------
+#define SGPIO_PRESET5_PRESET_Pos 0 /*!< SGPIO PRESET5: PRESET Position */
+#define SGPIO_PRESET5_PRESET_Msk (0x00000fffUL << SGPIO_PRESET5_PRESET_Pos) /*!< SGPIO PRESET5: PRESET Mask */
+
+// -------------------------------------- SGPIO_PRESET6 -----------------------------------------
+#define SGPIO_PRESET6_PRESET_Pos 0 /*!< SGPIO PRESET6: PRESET Position */
+#define SGPIO_PRESET6_PRESET_Msk (0x00000fffUL << SGPIO_PRESET6_PRESET_Pos) /*!< SGPIO PRESET6: PRESET Mask */
+
+// -------------------------------------- SGPIO_PRESET7 -----------------------------------------
+#define SGPIO_PRESET7_PRESET_Pos 0 /*!< SGPIO PRESET7: PRESET Position */
+#define SGPIO_PRESET7_PRESET_Msk (0x00000fffUL << SGPIO_PRESET7_PRESET_Pos) /*!< SGPIO PRESET7: PRESET Mask */
+
+// -------------------------------------- SGPIO_PRESET8 -----------------------------------------
+#define SGPIO_PRESET8_PRESET_Pos 0 /*!< SGPIO PRESET8: PRESET Position */
+#define SGPIO_PRESET8_PRESET_Msk (0x00000fffUL << SGPIO_PRESET8_PRESET_Pos) /*!< SGPIO PRESET8: PRESET Mask */
+
+// -------------------------------------- SGPIO_PRESET9 -----------------------------------------
+#define SGPIO_PRESET9_PRESET_Pos 0 /*!< SGPIO PRESET9: PRESET Position */
+#define SGPIO_PRESET9_PRESET_Msk (0x00000fffUL << SGPIO_PRESET9_PRESET_Pos) /*!< SGPIO PRESET9: PRESET Mask */
+
+// ------------------------------------- SGPIO_PRESET10 -----------------------------------------
+#define SGPIO_PRESET10_PRESET_Pos 0 /*!< SGPIO PRESET10: PRESET Position */
+#define SGPIO_PRESET10_PRESET_Msk (0x00000fffUL << SGPIO_PRESET10_PRESET_Pos) /*!< SGPIO PRESET10: PRESET Mask */
+
+// ------------------------------------- SGPIO_PRESET11 -----------------------------------------
+#define SGPIO_PRESET11_PRESET_Pos 0 /*!< SGPIO PRESET11: PRESET Position */
+#define SGPIO_PRESET11_PRESET_Msk (0x00000fffUL << SGPIO_PRESET11_PRESET_Pos) /*!< SGPIO PRESET11: PRESET Mask */
+
+// ------------------------------------- SGPIO_PRESET12 -----------------------------------------
+#define SGPIO_PRESET12_PRESET_Pos 0 /*!< SGPIO PRESET12: PRESET Position */
+#define SGPIO_PRESET12_PRESET_Msk (0x00000fffUL << SGPIO_PRESET12_PRESET_Pos) /*!< SGPIO PRESET12: PRESET Mask */
+
+// ------------------------------------- SGPIO_PRESET13 -----------------------------------------
+#define SGPIO_PRESET13_PRESET_Pos 0 /*!< SGPIO PRESET13: PRESET Position */
+#define SGPIO_PRESET13_PRESET_Msk (0x00000fffUL << SGPIO_PRESET13_PRESET_Pos) /*!< SGPIO PRESET13: PRESET Mask */
+
+// ------------------------------------- SGPIO_PRESET14 -----------------------------------------
+#define SGPIO_PRESET14_PRESET_Pos 0 /*!< SGPIO PRESET14: PRESET Position */
+#define SGPIO_PRESET14_PRESET_Msk (0x00000fffUL << SGPIO_PRESET14_PRESET_Pos) /*!< SGPIO PRESET14: PRESET Mask */
+
+// ------------------------------------- SGPIO_PRESET15 -----------------------------------------
+#define SGPIO_PRESET15_PRESET_Pos 0 /*!< SGPIO PRESET15: PRESET Position */
+#define SGPIO_PRESET15_PRESET_Msk (0x00000fffUL << SGPIO_PRESET15_PRESET_Pos) /*!< SGPIO PRESET15: PRESET Mask */
+
+// -------------------------------------- SGPIO_COUNT0 ------------------------------------------
+#define SGPIO_COUNT0_COUNT_Pos 0 /*!< SGPIO COUNT0: COUNT Position */
+#define SGPIO_COUNT0_COUNT_Msk (0x00000fffUL << SGPIO_COUNT0_COUNT_Pos) /*!< SGPIO COUNT0: COUNT Mask */
+
+// -------------------------------------- SGPIO_COUNT1 ------------------------------------------
+#define SGPIO_COUNT1_COUNT_Pos 0 /*!< SGPIO COUNT1: COUNT Position */
+#define SGPIO_COUNT1_COUNT_Msk (0x00000fffUL << SGPIO_COUNT1_COUNT_Pos) /*!< SGPIO COUNT1: COUNT Mask */
+
+// -------------------------------------- SGPIO_COUNT2 ------------------------------------------
+#define SGPIO_COUNT2_COUNT_Pos 0 /*!< SGPIO COUNT2: COUNT Position */
+#define SGPIO_COUNT2_COUNT_Msk (0x00000fffUL << SGPIO_COUNT2_COUNT_Pos) /*!< SGPIO COUNT2: COUNT Mask */
+
+// -------------------------------------- SGPIO_COUNT3 ------------------------------------------
+#define SGPIO_COUNT3_COUNT_Pos 0 /*!< SGPIO COUNT3: COUNT Position */
+#define SGPIO_COUNT3_COUNT_Msk (0x00000fffUL << SGPIO_COUNT3_COUNT_Pos) /*!< SGPIO COUNT3: COUNT Mask */
+
+// -------------------------------------- SGPIO_COUNT4 ------------------------------------------
+#define SGPIO_COUNT4_COUNT_Pos 0 /*!< SGPIO COUNT4: COUNT Position */
+#define SGPIO_COUNT4_COUNT_Msk (0x00000fffUL << SGPIO_COUNT4_COUNT_Pos) /*!< SGPIO COUNT4: COUNT Mask */
+
+// -------------------------------------- SGPIO_COUNT5 ------------------------------------------
+#define SGPIO_COUNT5_COUNT_Pos 0 /*!< SGPIO COUNT5: COUNT Position */
+#define SGPIO_COUNT5_COUNT_Msk (0x00000fffUL << SGPIO_COUNT5_COUNT_Pos) /*!< SGPIO COUNT5: COUNT Mask */
+
+// -------------------------------------- SGPIO_COUNT6 ------------------------------------------
+#define SGPIO_COUNT6_COUNT_Pos 0 /*!< SGPIO COUNT6: COUNT Position */
+#define SGPIO_COUNT6_COUNT_Msk (0x00000fffUL << SGPIO_COUNT6_COUNT_Pos) /*!< SGPIO COUNT6: COUNT Mask */
+
+// -------------------------------------- SGPIO_COUNT7 ------------------------------------------
+#define SGPIO_COUNT7_COUNT_Pos 0 /*!< SGPIO COUNT7: COUNT Position */
+#define SGPIO_COUNT7_COUNT_Msk (0x00000fffUL << SGPIO_COUNT7_COUNT_Pos) /*!< SGPIO COUNT7: COUNT Mask */
+
+// -------------------------------------- SGPIO_COUNT8 ------------------------------------------
+#define SGPIO_COUNT8_COUNT_Pos 0 /*!< SGPIO COUNT8: COUNT Position */
+#define SGPIO_COUNT8_COUNT_Msk (0x00000fffUL << SGPIO_COUNT8_COUNT_Pos) /*!< SGPIO COUNT8: COUNT Mask */
+
+// -------------------------------------- SGPIO_COUNT9 ------------------------------------------
+#define SGPIO_COUNT9_COUNT_Pos 0 /*!< SGPIO COUNT9: COUNT Position */
+#define SGPIO_COUNT9_COUNT_Msk (0x00000fffUL << SGPIO_COUNT9_COUNT_Pos) /*!< SGPIO COUNT9: COUNT Mask */
+
+// -------------------------------------- SGPIO_COUNT10 -----------------------------------------
+#define SGPIO_COUNT10_COUNT_Pos 0 /*!< SGPIO COUNT10: COUNT Position */
+#define SGPIO_COUNT10_COUNT_Msk (0x00000fffUL << SGPIO_COUNT10_COUNT_Pos) /*!< SGPIO COUNT10: COUNT Mask */
+
+// -------------------------------------- SGPIO_COUNT11 -----------------------------------------
+#define SGPIO_COUNT11_COUNT_Pos 0 /*!< SGPIO COUNT11: COUNT Position */
+#define SGPIO_COUNT11_COUNT_Msk (0x00000fffUL << SGPIO_COUNT11_COUNT_Pos) /*!< SGPIO COUNT11: COUNT Mask */
+
+// -------------------------------------- SGPIO_COUNT12 -----------------------------------------
+#define SGPIO_COUNT12_COUNT_Pos 0 /*!< SGPIO COUNT12: COUNT Position */
+#define SGPIO_COUNT12_COUNT_Msk (0x00000fffUL << SGPIO_COUNT12_COUNT_Pos) /*!< SGPIO COUNT12: COUNT Mask */
+
+// -------------------------------------- SGPIO_COUNT13 -----------------------------------------
+#define SGPIO_COUNT13_COUNT_Pos 0 /*!< SGPIO COUNT13: COUNT Position */
+#define SGPIO_COUNT13_COUNT_Msk (0x00000fffUL << SGPIO_COUNT13_COUNT_Pos) /*!< SGPIO COUNT13: COUNT Mask */
+
+// -------------------------------------- SGPIO_COUNT14 -----------------------------------------
+#define SGPIO_COUNT14_COUNT_Pos 0 /*!< SGPIO COUNT14: COUNT Position */
+#define SGPIO_COUNT14_COUNT_Msk (0x00000fffUL << SGPIO_COUNT14_COUNT_Pos) /*!< SGPIO COUNT14: COUNT Mask */
+
+// -------------------------------------- SGPIO_COUNT15 -----------------------------------------
+#define SGPIO_COUNT15_COUNT_Pos 0 /*!< SGPIO COUNT15: COUNT Position */
+#define SGPIO_COUNT15_COUNT_Msk (0x00000fffUL << SGPIO_COUNT15_COUNT_Pos) /*!< SGPIO COUNT15: COUNT Mask */
+
+// --------------------------------------- SGPIO_POS0 -------------------------------------------
+#define SGPIO_POS0_POS_Pos 0 /*!< SGPIO POS0: POS Position */
+#define SGPIO_POS0_POS_Msk (0x000000ffUL << SGPIO_POS0_POS_Pos) /*!< SGPIO POS0: POS Mask */
+#define SGPIO_POS0_POS_RESET_Pos 8 /*!< SGPIO POS0: POS_RESET Position */
+#define SGPIO_POS0_POS_RESET_Msk (0x000000ffUL << SGPIO_POS0_POS_RESET_Pos) /*!< SGPIO POS0: POS_RESET Mask */
+
+// --------------------------------------- SGPIO_POS1 -------------------------------------------
+#define SGPIO_POS1_POS_Pos 0 /*!< SGPIO POS1: POS Position */
+#define SGPIO_POS1_POS_Msk (0x000000ffUL << SGPIO_POS1_POS_Pos) /*!< SGPIO POS1: POS Mask */
+#define SGPIO_POS1_POS_RESET_Pos 8 /*!< SGPIO POS1: POS_RESET Position */
+#define SGPIO_POS1_POS_RESET_Msk (0x000000ffUL << SGPIO_POS1_POS_RESET_Pos) /*!< SGPIO POS1: POS_RESET Mask */
+
+// --------------------------------------- SGPIO_POS2 -------------------------------------------
+#define SGPIO_POS2_POS_Pos 0 /*!< SGPIO POS2: POS Position */
+#define SGPIO_POS2_POS_Msk (0x000000ffUL << SGPIO_POS2_POS_Pos) /*!< SGPIO POS2: POS Mask */
+#define SGPIO_POS2_POS_RESET_Pos 8 /*!< SGPIO POS2: POS_RESET Position */
+#define SGPIO_POS2_POS_RESET_Msk (0x000000ffUL << SGPIO_POS2_POS_RESET_Pos) /*!< SGPIO POS2: POS_RESET Mask */
+
+// --------------------------------------- SGPIO_POS3 -------------------------------------------
+#define SGPIO_POS3_POS_Pos 0 /*!< SGPIO POS3: POS Position */
+#define SGPIO_POS3_POS_Msk (0x000000ffUL << SGPIO_POS3_POS_Pos) /*!< SGPIO POS3: POS Mask */
+#define SGPIO_POS3_POS_RESET_Pos 8 /*!< SGPIO POS3: POS_RESET Position */
+#define SGPIO_POS3_POS_RESET_Msk (0x000000ffUL << SGPIO_POS3_POS_RESET_Pos) /*!< SGPIO POS3: POS_RESET Mask */
+
+// --------------------------------------- SGPIO_POS4 -------------------------------------------
+#define SGPIO_POS4_POS_Pos 0 /*!< SGPIO POS4: POS Position */
+#define SGPIO_POS4_POS_Msk (0x000000ffUL << SGPIO_POS4_POS_Pos) /*!< SGPIO POS4: POS Mask */
+#define SGPIO_POS4_POS_RESET_Pos 8 /*!< SGPIO POS4: POS_RESET Position */
+#define SGPIO_POS4_POS_RESET_Msk (0x000000ffUL << SGPIO_POS4_POS_RESET_Pos) /*!< SGPIO POS4: POS_RESET Mask */
+
+// --------------------------------------- SGPIO_POS5 -------------------------------------------
+#define SGPIO_POS5_POS_Pos 0 /*!< SGPIO POS5: POS Position */
+#define SGPIO_POS5_POS_Msk (0x000000ffUL << SGPIO_POS5_POS_Pos) /*!< SGPIO POS5: POS Mask */
+#define SGPIO_POS5_POS_RESET_Pos 8 /*!< SGPIO POS5: POS_RESET Position */
+#define SGPIO_POS5_POS_RESET_Msk (0x000000ffUL << SGPIO_POS5_POS_RESET_Pos) /*!< SGPIO POS5: POS_RESET Mask */
+
+// --------------------------------------- SGPIO_POS6 -------------------------------------------
+#define SGPIO_POS6_POS_Pos 0 /*!< SGPIO POS6: POS Position */
+#define SGPIO_POS6_POS_Msk (0x000000ffUL << SGPIO_POS6_POS_Pos) /*!< SGPIO POS6: POS Mask */
+#define SGPIO_POS6_POS_RESET_Pos 8 /*!< SGPIO POS6: POS_RESET Position */
+#define SGPIO_POS6_POS_RESET_Msk (0x000000ffUL << SGPIO_POS6_POS_RESET_Pos) /*!< SGPIO POS6: POS_RESET Mask */
+
+// --------------------------------------- SGPIO_POS7 -------------------------------------------
+#define SGPIO_POS7_POS_Pos 0 /*!< SGPIO POS7: POS Position */
+#define SGPIO_POS7_POS_Msk (0x000000ffUL << SGPIO_POS7_POS_Pos) /*!< SGPIO POS7: POS Mask */
+#define SGPIO_POS7_POS_RESET_Pos 8 /*!< SGPIO POS7: POS_RESET Position */
+#define SGPIO_POS7_POS_RESET_Msk (0x000000ffUL << SGPIO_POS7_POS_RESET_Pos) /*!< SGPIO POS7: POS_RESET Mask */
+
+// --------------------------------------- SGPIO_POS8 -------------------------------------------
+#define SGPIO_POS8_POS_Pos 0 /*!< SGPIO POS8: POS Position */
+#define SGPIO_POS8_POS_Msk (0x000000ffUL << SGPIO_POS8_POS_Pos) /*!< SGPIO POS8: POS Mask */
+#define SGPIO_POS8_POS_RESET_Pos 8 /*!< SGPIO POS8: POS_RESET Position */
+#define SGPIO_POS8_POS_RESET_Msk (0x000000ffUL << SGPIO_POS8_POS_RESET_Pos) /*!< SGPIO POS8: POS_RESET Mask */
+
+// --------------------------------------- SGPIO_POS9 -------------------------------------------
+#define SGPIO_POS9_POS_Pos 0 /*!< SGPIO POS9: POS Position */
+#define SGPIO_POS9_POS_Msk (0x000000ffUL << SGPIO_POS9_POS_Pos) /*!< SGPIO POS9: POS Mask */
+#define SGPIO_POS9_POS_RESET_Pos 8 /*!< SGPIO POS9: POS_RESET Position */
+#define SGPIO_POS9_POS_RESET_Msk (0x000000ffUL << SGPIO_POS9_POS_RESET_Pos) /*!< SGPIO POS9: POS_RESET Mask */
+
+// --------------------------------------- SGPIO_POS10 ------------------------------------------
+#define SGPIO_POS10_POS_Pos 0 /*!< SGPIO POS10: POS Position */
+#define SGPIO_POS10_POS_Msk (0x000000ffUL << SGPIO_POS10_POS_Pos) /*!< SGPIO POS10: POS Mask */
+#define SGPIO_POS10_POS_RESET_Pos 8 /*!< SGPIO POS10: POS_RESET Position */
+#define SGPIO_POS10_POS_RESET_Msk (0x000000ffUL << SGPIO_POS10_POS_RESET_Pos) /*!< SGPIO POS10: POS_RESET Mask */
+
+// --------------------------------------- SGPIO_POS11 ------------------------------------------
+#define SGPIO_POS11_POS_Pos 0 /*!< SGPIO POS11: POS Position */
+#define SGPIO_POS11_POS_Msk (0x000000ffUL << SGPIO_POS11_POS_Pos) /*!< SGPIO POS11: POS Mask */
+#define SGPIO_POS11_POS_RESET_Pos 8 /*!< SGPIO POS11: POS_RESET Position */
+#define SGPIO_POS11_POS_RESET_Msk (0x000000ffUL << SGPIO_POS11_POS_RESET_Pos) /*!< SGPIO POS11: POS_RESET Mask */
+
+// --------------------------------------- SGPIO_POS12 ------------------------------------------
+#define SGPIO_POS12_POS_Pos 0 /*!< SGPIO POS12: POS Position */
+#define SGPIO_POS12_POS_Msk (0x000000ffUL << SGPIO_POS12_POS_Pos) /*!< SGPIO POS12: POS Mask */
+#define SGPIO_POS12_POS_RESET_Pos 8 /*!< SGPIO POS12: POS_RESET Position */
+#define SGPIO_POS12_POS_RESET_Msk (0x000000ffUL << SGPIO_POS12_POS_RESET_Pos) /*!< SGPIO POS12: POS_RESET Mask */
+
+// --------------------------------------- SGPIO_POS13 ------------------------------------------
+#define SGPIO_POS13_POS_Pos 0 /*!< SGPIO POS13: POS Position */
+#define SGPIO_POS13_POS_Msk (0x000000ffUL << SGPIO_POS13_POS_Pos) /*!< SGPIO POS13: POS Mask */
+#define SGPIO_POS13_POS_RESET_Pos 8 /*!< SGPIO POS13: POS_RESET Position */
+#define SGPIO_POS13_POS_RESET_Msk (0x000000ffUL << SGPIO_POS13_POS_RESET_Pos) /*!< SGPIO POS13: POS_RESET Mask */
+
+// --------------------------------------- SGPIO_POS14 ------------------------------------------
+#define SGPIO_POS14_POS_Pos 0 /*!< SGPIO POS14: POS Position */
+#define SGPIO_POS14_POS_Msk (0x000000ffUL << SGPIO_POS14_POS_Pos) /*!< SGPIO POS14: POS Mask */
+#define SGPIO_POS14_POS_RESET_Pos 8 /*!< SGPIO POS14: POS_RESET Position */
+#define SGPIO_POS14_POS_RESET_Msk (0x000000ffUL << SGPIO_POS14_POS_RESET_Pos) /*!< SGPIO POS14: POS_RESET Mask */
+
+// --------------------------------------- SGPIO_POS15 ------------------------------------------
+#define SGPIO_POS15_POS_Pos 0 /*!< SGPIO POS15: POS Position */
+#define SGPIO_POS15_POS_Msk (0x000000ffUL << SGPIO_POS15_POS_Pos) /*!< SGPIO POS15: POS Mask */
+#define SGPIO_POS15_POS_RESET_Pos 8 /*!< SGPIO POS15: POS_RESET Position */
+#define SGPIO_POS15_POS_RESET_Msk (0x000000ffUL << SGPIO_POS15_POS_RESET_Pos) /*!< SGPIO POS15: POS_RESET Mask */
+
+// -------------------------------------- SGPIO_MASK_A ------------------------------------------
+#define SGPIO_MASK_A_MASK_A0_Pos 0 /*!< SGPIO MASK_A: MASK_A0 Position */
+#define SGPIO_MASK_A_MASK_A0_Msk (0x01UL << SGPIO_MASK_A_MASK_A0_Pos) /*!< SGPIO MASK_A: MASK_A0 Mask */
+#define SGPIO_MASK_A_MASK_A1_Pos 1 /*!< SGPIO MASK_A: MASK_A1 Position */
+#define SGPIO_MASK_A_MASK_A1_Msk (0x01UL << SGPIO_MASK_A_MASK_A1_Pos) /*!< SGPIO MASK_A: MASK_A1 Mask */
+#define SGPIO_MASK_A_MASK_A2_Pos 2 /*!< SGPIO MASK_A: MASK_A2 Position */
+#define SGPIO_MASK_A_MASK_A2_Msk (0x01UL << SGPIO_MASK_A_MASK_A2_Pos) /*!< SGPIO MASK_A: MASK_A2 Mask */
+#define SGPIO_MASK_A_MASK_A3_Pos 3 /*!< SGPIO MASK_A: MASK_A3 Position */
+#define SGPIO_MASK_A_MASK_A3_Msk (0x01UL << SGPIO_MASK_A_MASK_A3_Pos) /*!< SGPIO MASK_A: MASK_A3 Mask */
+#define SGPIO_MASK_A_MASK_A4_Pos 4 /*!< SGPIO MASK_A: MASK_A4 Position */
+#define SGPIO_MASK_A_MASK_A4_Msk (0x01UL << SGPIO_MASK_A_MASK_A4_Pos) /*!< SGPIO MASK_A: MASK_A4 Mask */
+#define SGPIO_MASK_A_MASK_A5_Pos 5 /*!< SGPIO MASK_A: MASK_A5 Position */
+#define SGPIO_MASK_A_MASK_A5_Msk (0x01UL << SGPIO_MASK_A_MASK_A5_Pos) /*!< SGPIO MASK_A: MASK_A5 Mask */
+#define SGPIO_MASK_A_MASK_A6_Pos 6 /*!< SGPIO MASK_A: MASK_A6 Position */
+#define SGPIO_MASK_A_MASK_A6_Msk (0x01UL << SGPIO_MASK_A_MASK_A6_Pos) /*!< SGPIO MASK_A: MASK_A6 Mask */
+#define SGPIO_MASK_A_MASK_A7_Pos 7 /*!< SGPIO MASK_A: MASK_A7 Position */
+#define SGPIO_MASK_A_MASK_A7_Msk (0x01UL << SGPIO_MASK_A_MASK_A7_Pos) /*!< SGPIO MASK_A: MASK_A7 Mask */
+#define SGPIO_MASK_A_MASK_A8_Pos 8 /*!< SGPIO MASK_A: MASK_A8 Position */
+#define SGPIO_MASK_A_MASK_A8_Msk (0x01UL << SGPIO_MASK_A_MASK_A8_Pos) /*!< SGPIO MASK_A: MASK_A8 Mask */
+#define SGPIO_MASK_A_MASK_A9_Pos 9 /*!< SGPIO MASK_A: MASK_A9 Position */
+#define SGPIO_MASK_A_MASK_A9_Msk (0x01UL << SGPIO_MASK_A_MASK_A9_Pos) /*!< SGPIO MASK_A: MASK_A9 Mask */
+#define SGPIO_MASK_A_MASK_A10_Pos 10 /*!< SGPIO MASK_A: MASK_A10 Position */
+#define SGPIO_MASK_A_MASK_A10_Msk (0x01UL << SGPIO_MASK_A_MASK_A10_Pos) /*!< SGPIO MASK_A: MASK_A10 Mask */
+#define SGPIO_MASK_A_MASK_A11_Pos 11 /*!< SGPIO MASK_A: MASK_A11 Position */
+#define SGPIO_MASK_A_MASK_A11_Msk (0x01UL << SGPIO_MASK_A_MASK_A11_Pos) /*!< SGPIO MASK_A: MASK_A11 Mask */
+#define SGPIO_MASK_A_MASK_A12_Pos 12 /*!< SGPIO MASK_A: MASK_A12 Position */
+#define SGPIO_MASK_A_MASK_A12_Msk (0x01UL << SGPIO_MASK_A_MASK_A12_Pos) /*!< SGPIO MASK_A: MASK_A12 Mask */
+#define SGPIO_MASK_A_MASK_A13_Pos 13 /*!< SGPIO MASK_A: MASK_A13 Position */
+#define SGPIO_MASK_A_MASK_A13_Msk (0x01UL << SGPIO_MASK_A_MASK_A13_Pos) /*!< SGPIO MASK_A: MASK_A13 Mask */
+#define SGPIO_MASK_A_MASK_A14_Pos 14 /*!< SGPIO MASK_A: MASK_A14 Position */
+#define SGPIO_MASK_A_MASK_A14_Msk (0x01UL << SGPIO_MASK_A_MASK_A14_Pos) /*!< SGPIO MASK_A: MASK_A14 Mask */
+#define SGPIO_MASK_A_MASK_A15_Pos 15 /*!< SGPIO MASK_A: MASK_A15 Position */
+#define SGPIO_MASK_A_MASK_A15_Msk (0x01UL << SGPIO_MASK_A_MASK_A15_Pos) /*!< SGPIO MASK_A: MASK_A15 Mask */
+#define SGPIO_MASK_A_MASK_A16_Pos 16 /*!< SGPIO MASK_A: MASK_A16 Position */
+#define SGPIO_MASK_A_MASK_A16_Msk (0x01UL << SGPIO_MASK_A_MASK_A16_Pos) /*!< SGPIO MASK_A: MASK_A16 Mask */
+#define SGPIO_MASK_A_MASK_A17_Pos 17 /*!< SGPIO MASK_A: MASK_A17 Position */
+#define SGPIO_MASK_A_MASK_A17_Msk (0x01UL << SGPIO_MASK_A_MASK_A17_Pos) /*!< SGPIO MASK_A: MASK_A17 Mask */
+#define SGPIO_MASK_A_MASK_A18_Pos 18 /*!< SGPIO MASK_A: MASK_A18 Position */
+#define SGPIO_MASK_A_MASK_A18_Msk (0x01UL << SGPIO_MASK_A_MASK_A18_Pos) /*!< SGPIO MASK_A: MASK_A18 Mask */
+#define SGPIO_MASK_A_MASK_A19_Pos 19 /*!< SGPIO MASK_A: MASK_A19 Position */
+#define SGPIO_MASK_A_MASK_A19_Msk (0x01UL << SGPIO_MASK_A_MASK_A19_Pos) /*!< SGPIO MASK_A: MASK_A19 Mask */
+#define SGPIO_MASK_A_MASK_A20_Pos 20 /*!< SGPIO MASK_A: MASK_A20 Position */
+#define SGPIO_MASK_A_MASK_A20_Msk (0x01UL << SGPIO_MASK_A_MASK_A20_Pos) /*!< SGPIO MASK_A: MASK_A20 Mask */
+#define SGPIO_MASK_A_MASK_A21_Pos 21 /*!< SGPIO MASK_A: MASK_A21 Position */
+#define SGPIO_MASK_A_MASK_A21_Msk (0x01UL << SGPIO_MASK_A_MASK_A21_Pos) /*!< SGPIO MASK_A: MASK_A21 Mask */
+#define SGPIO_MASK_A_MASK_A22_Pos 22 /*!< SGPIO MASK_A: MASK_A22 Position */
+#define SGPIO_MASK_A_MASK_A22_Msk (0x01UL << SGPIO_MASK_A_MASK_A22_Pos) /*!< SGPIO MASK_A: MASK_A22 Mask */
+#define SGPIO_MASK_A_MASK_A23_Pos 23 /*!< SGPIO MASK_A: MASK_A23 Position */
+#define SGPIO_MASK_A_MASK_A23_Msk (0x01UL << SGPIO_MASK_A_MASK_A23_Pos) /*!< SGPIO MASK_A: MASK_A23 Mask */
+#define SGPIO_MASK_A_MASK_A24_Pos 24 /*!< SGPIO MASK_A: MASK_A24 Position */
+#define SGPIO_MASK_A_MASK_A24_Msk (0x01UL << SGPIO_MASK_A_MASK_A24_Pos) /*!< SGPIO MASK_A: MASK_A24 Mask */
+#define SGPIO_MASK_A_MASK_A25_Pos 25 /*!< SGPIO MASK_A: MASK_A25 Position */
+#define SGPIO_MASK_A_MASK_A25_Msk (0x01UL << SGPIO_MASK_A_MASK_A25_Pos) /*!< SGPIO MASK_A: MASK_A25 Mask */
+#define SGPIO_MASK_A_MASK_A26_Pos 26 /*!< SGPIO MASK_A: MASK_A26 Position */
+#define SGPIO_MASK_A_MASK_A26_Msk (0x01UL << SGPIO_MASK_A_MASK_A26_Pos) /*!< SGPIO MASK_A: MASK_A26 Mask */
+#define SGPIO_MASK_A_MASK_A27_Pos 27 /*!< SGPIO MASK_A: MASK_A27 Position */
+#define SGPIO_MASK_A_MASK_A27_Msk (0x01UL << SGPIO_MASK_A_MASK_A27_Pos) /*!< SGPIO MASK_A: MASK_A27 Mask */
+#define SGPIO_MASK_A_MASK_A28_Pos 28 /*!< SGPIO MASK_A: MASK_A28 Position */
+#define SGPIO_MASK_A_MASK_A28_Msk (0x01UL << SGPIO_MASK_A_MASK_A28_Pos) /*!< SGPIO MASK_A: MASK_A28 Mask */
+#define SGPIO_MASK_A_MASK_A29_Pos 29 /*!< SGPIO MASK_A: MASK_A29 Position */
+#define SGPIO_MASK_A_MASK_A29_Msk (0x01UL << SGPIO_MASK_A_MASK_A29_Pos) /*!< SGPIO MASK_A: MASK_A29 Mask */
+#define SGPIO_MASK_A_MASK_A30_Pos 30 /*!< SGPIO MASK_A: MASK_A30 Position */
+#define SGPIO_MASK_A_MASK_A30_Msk (0x01UL << SGPIO_MASK_A_MASK_A30_Pos) /*!< SGPIO MASK_A: MASK_A30 Mask */
+#define SGPIO_MASK_A_MASK_A31_Pos 31 /*!< SGPIO MASK_A: MASK_A31 Position */
+#define SGPIO_MASK_A_MASK_A31_Msk (0x01UL << SGPIO_MASK_A_MASK_A31_Pos) /*!< SGPIO MASK_A: MASK_A31 Mask */
+
+// -------------------------------------- SGPIO_MASK_H ------------------------------------------
+#define SGPIO_MASK_H_MASK_H0_Pos 0 /*!< SGPIO MASK_H: MASK_H0 Position */
+#define SGPIO_MASK_H_MASK_H0_Msk (0x01UL << SGPIO_MASK_H_MASK_H0_Pos) /*!< SGPIO MASK_H: MASK_H0 Mask */
+#define SGPIO_MASK_H_MASK_H1_Pos 1 /*!< SGPIO MASK_H: MASK_H1 Position */
+#define SGPIO_MASK_H_MASK_H1_Msk (0x01UL << SGPIO_MASK_H_MASK_H1_Pos) /*!< SGPIO MASK_H: MASK_H1 Mask */
+#define SGPIO_MASK_H_MASK_H2_Pos 2 /*!< SGPIO MASK_H: MASK_H2 Position */
+#define SGPIO_MASK_H_MASK_H2_Msk (0x01UL << SGPIO_MASK_H_MASK_H2_Pos) /*!< SGPIO MASK_H: MASK_H2 Mask */
+#define SGPIO_MASK_H_MASK_H3_Pos 3 /*!< SGPIO MASK_H: MASK_H3 Position */
+#define SGPIO_MASK_H_MASK_H3_Msk (0x01UL << SGPIO_MASK_H_MASK_H3_Pos) /*!< SGPIO MASK_H: MASK_H3 Mask */
+#define SGPIO_MASK_H_MASK_H4_Pos 4 /*!< SGPIO MASK_H: MASK_H4 Position */
+#define SGPIO_MASK_H_MASK_H4_Msk (0x01UL << SGPIO_MASK_H_MASK_H4_Pos) /*!< SGPIO MASK_H: MASK_H4 Mask */
+#define SGPIO_MASK_H_MASK_H5_Pos 5 /*!< SGPIO MASK_H: MASK_H5 Position */
+#define SGPIO_MASK_H_MASK_H5_Msk (0x01UL << SGPIO_MASK_H_MASK_H5_Pos) /*!< SGPIO MASK_H: MASK_H5 Mask */
+#define SGPIO_MASK_H_MASK_H6_Pos 6 /*!< SGPIO MASK_H: MASK_H6 Position */
+#define SGPIO_MASK_H_MASK_H6_Msk (0x01UL << SGPIO_MASK_H_MASK_H6_Pos) /*!< SGPIO MASK_H: MASK_H6 Mask */
+#define SGPIO_MASK_H_MASK_H7_Pos 7 /*!< SGPIO MASK_H: MASK_H7 Position */
+#define SGPIO_MASK_H_MASK_H7_Msk (0x01UL << SGPIO_MASK_H_MASK_H7_Pos) /*!< SGPIO MASK_H: MASK_H7 Mask */
+#define SGPIO_MASK_H_MASK_H8_Pos 8 /*!< SGPIO MASK_H: MASK_H8 Position */
+#define SGPIO_MASK_H_MASK_H8_Msk (0x01UL << SGPIO_MASK_H_MASK_H8_Pos) /*!< SGPIO MASK_H: MASK_H8 Mask */
+#define SGPIO_MASK_H_MASK_H9_Pos 9 /*!< SGPIO MASK_H: MASK_H9 Position */
+#define SGPIO_MASK_H_MASK_H9_Msk (0x01UL << SGPIO_MASK_H_MASK_H9_Pos) /*!< SGPIO MASK_H: MASK_H9 Mask */
+#define SGPIO_MASK_H_MASK_H10_Pos 10 /*!< SGPIO MASK_H: MASK_H10 Position */
+#define SGPIO_MASK_H_MASK_H10_Msk (0x01UL << SGPIO_MASK_H_MASK_H10_Pos) /*!< SGPIO MASK_H: MASK_H10 Mask */
+#define SGPIO_MASK_H_MASK_H11_Pos 11 /*!< SGPIO MASK_H: MASK_H11 Position */
+#define SGPIO_MASK_H_MASK_H11_Msk (0x01UL << SGPIO_MASK_H_MASK_H11_Pos) /*!< SGPIO MASK_H: MASK_H11 Mask */
+#define SGPIO_MASK_H_MASK_H12_Pos 12 /*!< SGPIO MASK_H: MASK_H12 Position */
+#define SGPIO_MASK_H_MASK_H12_Msk (0x01UL << SGPIO_MASK_H_MASK_H12_Pos) /*!< SGPIO MASK_H: MASK_H12 Mask */
+#define SGPIO_MASK_H_MASK_H13_Pos 13 /*!< SGPIO MASK_H: MASK_H13 Position */
+#define SGPIO_MASK_H_MASK_H13_Msk (0x01UL << SGPIO_MASK_H_MASK_H13_Pos) /*!< SGPIO MASK_H: MASK_H13 Mask */
+#define SGPIO_MASK_H_MASK_H14_Pos 14 /*!< SGPIO MASK_H: MASK_H14 Position */
+#define SGPIO_MASK_H_MASK_H14_Msk (0x01UL << SGPIO_MASK_H_MASK_H14_Pos) /*!< SGPIO MASK_H: MASK_H14 Mask */
+#define SGPIO_MASK_H_MASK_H15_Pos 15 /*!< SGPIO MASK_H: MASK_H15 Position */
+#define SGPIO_MASK_H_MASK_H15_Msk (0x01UL << SGPIO_MASK_H_MASK_H15_Pos) /*!< SGPIO MASK_H: MASK_H15 Mask */
+#define SGPIO_MASK_H_MASK_H16_Pos 16 /*!< SGPIO MASK_H: MASK_H16 Position */
+#define SGPIO_MASK_H_MASK_H16_Msk (0x01UL << SGPIO_MASK_H_MASK_H16_Pos) /*!< SGPIO MASK_H: MASK_H16 Mask */
+#define SGPIO_MASK_H_MASK_H17_Pos 17 /*!< SGPIO MASK_H: MASK_H17 Position */
+#define SGPIO_MASK_H_MASK_H17_Msk (0x01UL << SGPIO_MASK_H_MASK_H17_Pos) /*!< SGPIO MASK_H: MASK_H17 Mask */
+#define SGPIO_MASK_H_MASK_H18_Pos 18 /*!< SGPIO MASK_H: MASK_H18 Position */
+#define SGPIO_MASK_H_MASK_H18_Msk (0x01UL << SGPIO_MASK_H_MASK_H18_Pos) /*!< SGPIO MASK_H: MASK_H18 Mask */
+#define SGPIO_MASK_H_MASK_H19_Pos 19 /*!< SGPIO MASK_H: MASK_H19 Position */
+#define SGPIO_MASK_H_MASK_H19_Msk (0x01UL << SGPIO_MASK_H_MASK_H19_Pos) /*!< SGPIO MASK_H: MASK_H19 Mask */
+#define SGPIO_MASK_H_MASK_H20_Pos 20 /*!< SGPIO MASK_H: MASK_H20 Position */
+#define SGPIO_MASK_H_MASK_H20_Msk (0x01UL << SGPIO_MASK_H_MASK_H20_Pos) /*!< SGPIO MASK_H: MASK_H20 Mask */
+#define SGPIO_MASK_H_MASK_H21_Pos 21 /*!< SGPIO MASK_H: MASK_H21 Position */
+#define SGPIO_MASK_H_MASK_H21_Msk (0x01UL << SGPIO_MASK_H_MASK_H21_Pos) /*!< SGPIO MASK_H: MASK_H21 Mask */
+#define SGPIO_MASK_H_MASK_H22_Pos 22 /*!< SGPIO MASK_H: MASK_H22 Position */
+#define SGPIO_MASK_H_MASK_H22_Msk (0x01UL << SGPIO_MASK_H_MASK_H22_Pos) /*!< SGPIO MASK_H: MASK_H22 Mask */
+#define SGPIO_MASK_H_MASK_H23_Pos 23 /*!< SGPIO MASK_H: MASK_H23 Position */
+#define SGPIO_MASK_H_MASK_H23_Msk (0x01UL << SGPIO_MASK_H_MASK_H23_Pos) /*!< SGPIO MASK_H: MASK_H23 Mask */
+#define SGPIO_MASK_H_MASK_H24_Pos 24 /*!< SGPIO MASK_H: MASK_H24 Position */
+#define SGPIO_MASK_H_MASK_H24_Msk (0x01UL << SGPIO_MASK_H_MASK_H24_Pos) /*!< SGPIO MASK_H: MASK_H24 Mask */
+#define SGPIO_MASK_H_MASK_H25_Pos 25 /*!< SGPIO MASK_H: MASK_H25 Position */
+#define SGPIO_MASK_H_MASK_H25_Msk (0x01UL << SGPIO_MASK_H_MASK_H25_Pos) /*!< SGPIO MASK_H: MASK_H25 Mask */
+#define SGPIO_MASK_H_MASK_H26_Pos 26 /*!< SGPIO MASK_H: MASK_H26 Position */
+#define SGPIO_MASK_H_MASK_H26_Msk (0x01UL << SGPIO_MASK_H_MASK_H26_Pos) /*!< SGPIO MASK_H: MASK_H26 Mask */
+#define SGPIO_MASK_H_MASK_H27_Pos 27 /*!< SGPIO MASK_H: MASK_H27 Position */
+#define SGPIO_MASK_H_MASK_H27_Msk (0x01UL << SGPIO_MASK_H_MASK_H27_Pos) /*!< SGPIO MASK_H: MASK_H27 Mask */
+#define SGPIO_MASK_H_MASK_H28_Pos 28 /*!< SGPIO MASK_H: MASK_H28 Position */
+#define SGPIO_MASK_H_MASK_H28_Msk (0x01UL << SGPIO_MASK_H_MASK_H28_Pos) /*!< SGPIO MASK_H: MASK_H28 Mask */
+#define SGPIO_MASK_H_MASK_H29_Pos 29 /*!< SGPIO MASK_H: MASK_H29 Position */
+#define SGPIO_MASK_H_MASK_H29_Msk (0x01UL << SGPIO_MASK_H_MASK_H29_Pos) /*!< SGPIO MASK_H: MASK_H29 Mask */
+#define SGPIO_MASK_H_MASK_H30_Pos 30 /*!< SGPIO MASK_H: MASK_H30 Position */
+#define SGPIO_MASK_H_MASK_H30_Msk (0x01UL << SGPIO_MASK_H_MASK_H30_Pos) /*!< SGPIO MASK_H: MASK_H30 Mask */
+#define SGPIO_MASK_H_MASK_H31_Pos 31 /*!< SGPIO MASK_H: MASK_H31 Position */
+#define SGPIO_MASK_H_MASK_H31_Msk (0x01UL << SGPIO_MASK_H_MASK_H31_Pos) /*!< SGPIO MASK_H: MASK_H31 Mask */
+
+// -------------------------------------- SGPIO_MASK_I ------------------------------------------
+#define SGPIO_MASK_I_MASK_I0_Pos 0 /*!< SGPIO MASK_I: MASK_I0 Position */
+#define SGPIO_MASK_I_MASK_I0_Msk (0x01UL << SGPIO_MASK_I_MASK_I0_Pos) /*!< SGPIO MASK_I: MASK_I0 Mask */
+#define SGPIO_MASK_I_MASK_I1_Pos 1 /*!< SGPIO MASK_I: MASK_I1 Position */
+#define SGPIO_MASK_I_MASK_I1_Msk (0x01UL << SGPIO_MASK_I_MASK_I1_Pos) /*!< SGPIO MASK_I: MASK_I1 Mask */
+#define SGPIO_MASK_I_MASK_I2_Pos 2 /*!< SGPIO MASK_I: MASK_I2 Position */
+#define SGPIO_MASK_I_MASK_I2_Msk (0x01UL << SGPIO_MASK_I_MASK_I2_Pos) /*!< SGPIO MASK_I: MASK_I2 Mask */
+#define SGPIO_MASK_I_MASK_I3_Pos 3 /*!< SGPIO MASK_I: MASK_I3 Position */
+#define SGPIO_MASK_I_MASK_I3_Msk (0x01UL << SGPIO_MASK_I_MASK_I3_Pos) /*!< SGPIO MASK_I: MASK_I3 Mask */
+#define SGPIO_MASK_I_MASK_I4_Pos 4 /*!< SGPIO MASK_I: MASK_I4 Position */
+#define SGPIO_MASK_I_MASK_I4_Msk (0x01UL << SGPIO_MASK_I_MASK_I4_Pos) /*!< SGPIO MASK_I: MASK_I4 Mask */
+#define SGPIO_MASK_I_MASK_I5_Pos 5 /*!< SGPIO MASK_I: MASK_I5 Position */
+#define SGPIO_MASK_I_MASK_I5_Msk (0x01UL << SGPIO_MASK_I_MASK_I5_Pos) /*!< SGPIO MASK_I: MASK_I5 Mask */
+#define SGPIO_MASK_I_MASK_I6_Pos 6 /*!< SGPIO MASK_I: MASK_I6 Position */
+#define SGPIO_MASK_I_MASK_I6_Msk (0x01UL << SGPIO_MASK_I_MASK_I6_Pos) /*!< SGPIO MASK_I: MASK_I6 Mask */
+#define SGPIO_MASK_I_MASK_I7_Pos 7 /*!< SGPIO MASK_I: MASK_I7 Position */
+#define SGPIO_MASK_I_MASK_I7_Msk (0x01UL << SGPIO_MASK_I_MASK_I7_Pos) /*!< SGPIO MASK_I: MASK_I7 Mask */
+#define SGPIO_MASK_I_MASK_I8_Pos 8 /*!< SGPIO MASK_I: MASK_I8 Position */
+#define SGPIO_MASK_I_MASK_I8_Msk (0x01UL << SGPIO_MASK_I_MASK_I8_Pos) /*!< SGPIO MASK_I: MASK_I8 Mask */
+#define SGPIO_MASK_I_MASK_I9_Pos 9 /*!< SGPIO MASK_I: MASK_I9 Position */
+#define SGPIO_MASK_I_MASK_I9_Msk (0x01UL << SGPIO_MASK_I_MASK_I9_Pos) /*!< SGPIO MASK_I: MASK_I9 Mask */
+#define SGPIO_MASK_I_MASK_I10_Pos 10 /*!< SGPIO MASK_I: MASK_I10 Position */
+#define SGPIO_MASK_I_MASK_I10_Msk (0x01UL << SGPIO_MASK_I_MASK_I10_Pos) /*!< SGPIO MASK_I: MASK_I10 Mask */
+#define SGPIO_MASK_I_MASK_I11_Pos 11 /*!< SGPIO MASK_I: MASK_I11 Position */
+#define SGPIO_MASK_I_MASK_I11_Msk (0x01UL << SGPIO_MASK_I_MASK_I11_Pos) /*!< SGPIO MASK_I: MASK_I11 Mask */
+#define SGPIO_MASK_I_MASK_I12_Pos 12 /*!< SGPIO MASK_I: MASK_I12 Position */
+#define SGPIO_MASK_I_MASK_I12_Msk (0x01UL << SGPIO_MASK_I_MASK_I12_Pos) /*!< SGPIO MASK_I: MASK_I12 Mask */
+#define SGPIO_MASK_I_MASK_I13_Pos 13 /*!< SGPIO MASK_I: MASK_I13 Position */
+#define SGPIO_MASK_I_MASK_I13_Msk (0x01UL << SGPIO_MASK_I_MASK_I13_Pos) /*!< SGPIO MASK_I: MASK_I13 Mask */
+#define SGPIO_MASK_I_MASK_I14_Pos 14 /*!< SGPIO MASK_I: MASK_I14 Position */
+#define SGPIO_MASK_I_MASK_I14_Msk (0x01UL << SGPIO_MASK_I_MASK_I14_Pos) /*!< SGPIO MASK_I: MASK_I14 Mask */
+#define SGPIO_MASK_I_MASK_I15_Pos 15 /*!< SGPIO MASK_I: MASK_I15 Position */
+#define SGPIO_MASK_I_MASK_I15_Msk (0x01UL << SGPIO_MASK_I_MASK_I15_Pos) /*!< SGPIO MASK_I: MASK_I15 Mask */
+#define SGPIO_MASK_I_MASK_I16_Pos 16 /*!< SGPIO MASK_I: MASK_I16 Position */
+#define SGPIO_MASK_I_MASK_I16_Msk (0x01UL << SGPIO_MASK_I_MASK_I16_Pos) /*!< SGPIO MASK_I: MASK_I16 Mask */
+#define SGPIO_MASK_I_MASK_I17_Pos 17 /*!< SGPIO MASK_I: MASK_I17 Position */
+#define SGPIO_MASK_I_MASK_I17_Msk (0x01UL << SGPIO_MASK_I_MASK_I17_Pos) /*!< SGPIO MASK_I: MASK_I17 Mask */
+#define SGPIO_MASK_I_MASK_I18_Pos 18 /*!< SGPIO MASK_I: MASK_I18 Position */
+#define SGPIO_MASK_I_MASK_I18_Msk (0x01UL << SGPIO_MASK_I_MASK_I18_Pos) /*!< SGPIO MASK_I: MASK_I18 Mask */
+#define SGPIO_MASK_I_MASK_I19_Pos 19 /*!< SGPIO MASK_I: MASK_I19 Position */
+#define SGPIO_MASK_I_MASK_I19_Msk (0x01UL << SGPIO_MASK_I_MASK_I19_Pos) /*!< SGPIO MASK_I: MASK_I19 Mask */
+#define SGPIO_MASK_I_MASK_I20_Pos 20 /*!< SGPIO MASK_I: MASK_I20 Position */
+#define SGPIO_MASK_I_MASK_I20_Msk (0x01UL << SGPIO_MASK_I_MASK_I20_Pos) /*!< SGPIO MASK_I: MASK_I20 Mask */
+#define SGPIO_MASK_I_MASK_I21_Pos 21 /*!< SGPIO MASK_I: MASK_I21 Position */
+#define SGPIO_MASK_I_MASK_I21_Msk (0x01UL << SGPIO_MASK_I_MASK_I21_Pos) /*!< SGPIO MASK_I: MASK_I21 Mask */
+#define SGPIO_MASK_I_MASK_I22_Pos 22 /*!< SGPIO MASK_I: MASK_I22 Position */
+#define SGPIO_MASK_I_MASK_I22_Msk (0x01UL << SGPIO_MASK_I_MASK_I22_Pos) /*!< SGPIO MASK_I: MASK_I22 Mask */
+#define SGPIO_MASK_I_MASK_I23_Pos 23 /*!< SGPIO MASK_I: MASK_I23 Position */
+#define SGPIO_MASK_I_MASK_I23_Msk (0x01UL << SGPIO_MASK_I_MASK_I23_Pos) /*!< SGPIO MASK_I: MASK_I23 Mask */
+#define SGPIO_MASK_I_MASK_I24_Pos 24 /*!< SGPIO MASK_I: MASK_I24 Position */
+#define SGPIO_MASK_I_MASK_I24_Msk (0x01UL << SGPIO_MASK_I_MASK_I24_Pos) /*!< SGPIO MASK_I: MASK_I24 Mask */
+#define SGPIO_MASK_I_MASK_I25_Pos 25 /*!< SGPIO MASK_I: MASK_I25 Position */
+#define SGPIO_MASK_I_MASK_I25_Msk (0x01UL << SGPIO_MASK_I_MASK_I25_Pos) /*!< SGPIO MASK_I: MASK_I25 Mask */
+#define SGPIO_MASK_I_MASK_I26_Pos 26 /*!< SGPIO MASK_I: MASK_I26 Position */
+#define SGPIO_MASK_I_MASK_I26_Msk (0x01UL << SGPIO_MASK_I_MASK_I26_Pos) /*!< SGPIO MASK_I: MASK_I26 Mask */
+#define SGPIO_MASK_I_MASK_I27_Pos 27 /*!< SGPIO MASK_I: MASK_I27 Position */
+#define SGPIO_MASK_I_MASK_I27_Msk (0x01UL << SGPIO_MASK_I_MASK_I27_Pos) /*!< SGPIO MASK_I: MASK_I27 Mask */
+#define SGPIO_MASK_I_MASK_I28_Pos 28 /*!< SGPIO MASK_I: MASK_I28 Position */
+#define SGPIO_MASK_I_MASK_I28_Msk (0x01UL << SGPIO_MASK_I_MASK_I28_Pos) /*!< SGPIO MASK_I: MASK_I28 Mask */
+#define SGPIO_MASK_I_MASK_I29_Pos 29 /*!< SGPIO MASK_I: MASK_I29 Position */
+#define SGPIO_MASK_I_MASK_I29_Msk (0x01UL << SGPIO_MASK_I_MASK_I29_Pos) /*!< SGPIO MASK_I: MASK_I29 Mask */
+#define SGPIO_MASK_I_MASK_I30_Pos 30 /*!< SGPIO MASK_I: MASK_I30 Position */
+#define SGPIO_MASK_I_MASK_I30_Msk (0x01UL << SGPIO_MASK_I_MASK_I30_Pos) /*!< SGPIO MASK_I: MASK_I30 Mask */
+#define SGPIO_MASK_I_MASK_I31_Pos 31 /*!< SGPIO MASK_I: MASK_I31 Position */
+#define SGPIO_MASK_I_MASK_I31_Msk (0x01UL << SGPIO_MASK_I_MASK_I31_Pos) /*!< SGPIO MASK_I: MASK_I31 Mask */
+
+// -------------------------------------- SGPIO_MASK_P ------------------------------------------
+#define SGPIO_MASK_P_MASK_P0_Pos 0 /*!< SGPIO MASK_P: MASK_P0 Position */
+#define SGPIO_MASK_P_MASK_P0_Msk (0x01UL << SGPIO_MASK_P_MASK_P0_Pos) /*!< SGPIO MASK_P: MASK_P0 Mask */
+#define SGPIO_MASK_P_MASK_P1_Pos 1 /*!< SGPIO MASK_P: MASK_P1 Position */
+#define SGPIO_MASK_P_MASK_P1_Msk (0x01UL << SGPIO_MASK_P_MASK_P1_Pos) /*!< SGPIO MASK_P: MASK_P1 Mask */
+#define SGPIO_MASK_P_MASK_P2_Pos 2 /*!< SGPIO MASK_P: MASK_P2 Position */
+#define SGPIO_MASK_P_MASK_P2_Msk (0x01UL << SGPIO_MASK_P_MASK_P2_Pos) /*!< SGPIO MASK_P: MASK_P2 Mask */
+#define SGPIO_MASK_P_MASK_P3_Pos 3 /*!< SGPIO MASK_P: MASK_P3 Position */
+#define SGPIO_MASK_P_MASK_P3_Msk (0x01UL << SGPIO_MASK_P_MASK_P3_Pos) /*!< SGPIO MASK_P: MASK_P3 Mask */
+#define SGPIO_MASK_P_MASK_P4_Pos 4 /*!< SGPIO MASK_P: MASK_P4 Position */
+#define SGPIO_MASK_P_MASK_P4_Msk (0x01UL << SGPIO_MASK_P_MASK_P4_Pos) /*!< SGPIO MASK_P: MASK_P4 Mask */
+#define SGPIO_MASK_P_MASK_P5_Pos 5 /*!< SGPIO MASK_P: MASK_P5 Position */
+#define SGPIO_MASK_P_MASK_P5_Msk (0x01UL << SGPIO_MASK_P_MASK_P5_Pos) /*!< SGPIO MASK_P: MASK_P5 Mask */
+#define SGPIO_MASK_P_MASK_P6_Pos 6 /*!< SGPIO MASK_P: MASK_P6 Position */
+#define SGPIO_MASK_P_MASK_P6_Msk (0x01UL << SGPIO_MASK_P_MASK_P6_Pos) /*!< SGPIO MASK_P: MASK_P6 Mask */
+#define SGPIO_MASK_P_MASK_P7_Pos 7 /*!< SGPIO MASK_P: MASK_P7 Position */
+#define SGPIO_MASK_P_MASK_P7_Msk (0x01UL << SGPIO_MASK_P_MASK_P7_Pos) /*!< SGPIO MASK_P: MASK_P7 Mask */
+#define SGPIO_MASK_P_MASK_P8_Pos 8 /*!< SGPIO MASK_P: MASK_P8 Position */
+#define SGPIO_MASK_P_MASK_P8_Msk (0x01UL << SGPIO_MASK_P_MASK_P8_Pos) /*!< SGPIO MASK_P: MASK_P8 Mask */
+#define SGPIO_MASK_P_MASK_P9_Pos 9 /*!< SGPIO MASK_P: MASK_P9 Position */
+#define SGPIO_MASK_P_MASK_P9_Msk (0x01UL << SGPIO_MASK_P_MASK_P9_Pos) /*!< SGPIO MASK_P: MASK_P9 Mask */
+#define SGPIO_MASK_P_MASK_P10_Pos 10 /*!< SGPIO MASK_P: MASK_P10 Position */
+#define SGPIO_MASK_P_MASK_P10_Msk (0x01UL << SGPIO_MASK_P_MASK_P10_Pos) /*!< SGPIO MASK_P: MASK_P10 Mask */
+#define SGPIO_MASK_P_MASK_P11_Pos 11 /*!< SGPIO MASK_P: MASK_P11 Position */
+#define SGPIO_MASK_P_MASK_P11_Msk (0x01UL << SGPIO_MASK_P_MASK_P11_Pos) /*!< SGPIO MASK_P: MASK_P11 Mask */
+#define SGPIO_MASK_P_MASK_P12_Pos 12 /*!< SGPIO MASK_P: MASK_P12 Position */
+#define SGPIO_MASK_P_MASK_P12_Msk (0x01UL << SGPIO_MASK_P_MASK_P12_Pos) /*!< SGPIO MASK_P: MASK_P12 Mask */
+#define SGPIO_MASK_P_MASK_P13_Pos 13 /*!< SGPIO MASK_P: MASK_P13 Position */
+#define SGPIO_MASK_P_MASK_P13_Msk (0x01UL << SGPIO_MASK_P_MASK_P13_Pos) /*!< SGPIO MASK_P: MASK_P13 Mask */
+#define SGPIO_MASK_P_MASK_P14_Pos 14 /*!< SGPIO MASK_P: MASK_P14 Position */
+#define SGPIO_MASK_P_MASK_P14_Msk (0x01UL << SGPIO_MASK_P_MASK_P14_Pos) /*!< SGPIO MASK_P: MASK_P14 Mask */
+#define SGPIO_MASK_P_MASK_P15_Pos 15 /*!< SGPIO MASK_P: MASK_P15 Position */
+#define SGPIO_MASK_P_MASK_P15_Msk (0x01UL << SGPIO_MASK_P_MASK_P15_Pos) /*!< SGPIO MASK_P: MASK_P15 Mask */
+#define SGPIO_MASK_P_MASK_P16_Pos 16 /*!< SGPIO MASK_P: MASK_P16 Position */
+#define SGPIO_MASK_P_MASK_P16_Msk (0x01UL << SGPIO_MASK_P_MASK_P16_Pos) /*!< SGPIO MASK_P: MASK_P16 Mask */
+#define SGPIO_MASK_P_MASK_P17_Pos 17 /*!< SGPIO MASK_P: MASK_P17 Position */
+#define SGPIO_MASK_P_MASK_P17_Msk (0x01UL << SGPIO_MASK_P_MASK_P17_Pos) /*!< SGPIO MASK_P: MASK_P17 Mask */
+#define SGPIO_MASK_P_MASK_P18_Pos 18 /*!< SGPIO MASK_P: MASK_P18 Position */
+#define SGPIO_MASK_P_MASK_P18_Msk (0x01UL << SGPIO_MASK_P_MASK_P18_Pos) /*!< SGPIO MASK_P: MASK_P18 Mask */
+#define SGPIO_MASK_P_MASK_P19_Pos 19 /*!< SGPIO MASK_P: MASK_P19 Position */
+#define SGPIO_MASK_P_MASK_P19_Msk (0x01UL << SGPIO_MASK_P_MASK_P19_Pos) /*!< SGPIO MASK_P: MASK_P19 Mask */
+#define SGPIO_MASK_P_MASK_P20_Pos 20 /*!< SGPIO MASK_P: MASK_P20 Position */
+#define SGPIO_MASK_P_MASK_P20_Msk (0x01UL << SGPIO_MASK_P_MASK_P20_Pos) /*!< SGPIO MASK_P: MASK_P20 Mask */
+#define SGPIO_MASK_P_MASK_P21_Pos 21 /*!< SGPIO MASK_P: MASK_P21 Position */
+#define SGPIO_MASK_P_MASK_P21_Msk (0x01UL << SGPIO_MASK_P_MASK_P21_Pos) /*!< SGPIO MASK_P: MASK_P21 Mask */
+#define SGPIO_MASK_P_MASK_P22_Pos 22 /*!< SGPIO MASK_P: MASK_P22 Position */
+#define SGPIO_MASK_P_MASK_P22_Msk (0x01UL << SGPIO_MASK_P_MASK_P22_Pos) /*!< SGPIO MASK_P: MASK_P22 Mask */
+#define SGPIO_MASK_P_MASK_P23_Pos 23 /*!< SGPIO MASK_P: MASK_P23 Position */
+#define SGPIO_MASK_P_MASK_P23_Msk (0x01UL << SGPIO_MASK_P_MASK_P23_Pos) /*!< SGPIO MASK_P: MASK_P23 Mask */
+#define SGPIO_MASK_P_MASK_P24_Pos 24 /*!< SGPIO MASK_P: MASK_P24 Position */
+#define SGPIO_MASK_P_MASK_P24_Msk (0x01UL << SGPIO_MASK_P_MASK_P24_Pos) /*!< SGPIO MASK_P: MASK_P24 Mask */
+#define SGPIO_MASK_P_MASK_P25_Pos 25 /*!< SGPIO MASK_P: MASK_P25 Position */
+#define SGPIO_MASK_P_MASK_P25_Msk (0x01UL << SGPIO_MASK_P_MASK_P25_Pos) /*!< SGPIO MASK_P: MASK_P25 Mask */
+#define SGPIO_MASK_P_MASK_P26_Pos 26 /*!< SGPIO MASK_P: MASK_P26 Position */
+#define SGPIO_MASK_P_MASK_P26_Msk (0x01UL << SGPIO_MASK_P_MASK_P26_Pos) /*!< SGPIO MASK_P: MASK_P26 Mask */
+#define SGPIO_MASK_P_MASK_P27_Pos 27 /*!< SGPIO MASK_P: MASK_P27 Position */
+#define SGPIO_MASK_P_MASK_P27_Msk (0x01UL << SGPIO_MASK_P_MASK_P27_Pos) /*!< SGPIO MASK_P: MASK_P27 Mask */
+#define SGPIO_MASK_P_MASK_P28_Pos 28 /*!< SGPIO MASK_P: MASK_P28 Position */
+#define SGPIO_MASK_P_MASK_P28_Msk (0x01UL << SGPIO_MASK_P_MASK_P28_Pos) /*!< SGPIO MASK_P: MASK_P28 Mask */
+#define SGPIO_MASK_P_MASK_P29_Pos 29 /*!< SGPIO MASK_P: MASK_P29 Position */
+#define SGPIO_MASK_P_MASK_P29_Msk (0x01UL << SGPIO_MASK_P_MASK_P29_Pos) /*!< SGPIO MASK_P: MASK_P29 Mask */
+#define SGPIO_MASK_P_MASK_P30_Pos 30 /*!< SGPIO MASK_P: MASK_P30 Position */
+#define SGPIO_MASK_P_MASK_P30_Msk (0x01UL << SGPIO_MASK_P_MASK_P30_Pos) /*!< SGPIO MASK_P: MASK_P30 Mask */
+#define SGPIO_MASK_P_MASK_P31_Pos 31 /*!< SGPIO MASK_P: MASK_P31 Position */
+#define SGPIO_MASK_P_MASK_P31_Msk (0x01UL << SGPIO_MASK_P_MASK_P31_Pos) /*!< SGPIO MASK_P: MASK_P31 Mask */
+
+// ------------------------------------ SGPIO_GPIO_INREG ----------------------------------------
+#define SGPIO_GPIO_INREG_GPIO_IN0_Pos 0 /*!< SGPIO GPIO_INREG: GPIO_IN0 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN0_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN0_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN0 Mask */
+#define SGPIO_GPIO_INREG_GPIO_IN1_Pos 1 /*!< SGPIO GPIO_INREG: GPIO_IN1 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN1_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN1_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN1 Mask */
+#define SGPIO_GPIO_INREG_GPIO_IN2_Pos 2 /*!< SGPIO GPIO_INREG: GPIO_IN2 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN2_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN2_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN2 Mask */
+#define SGPIO_GPIO_INREG_GPIO_IN3_Pos 3 /*!< SGPIO GPIO_INREG: GPIO_IN3 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN3_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN3_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN3 Mask */
+#define SGPIO_GPIO_INREG_GPIO_IN4_Pos 4 /*!< SGPIO GPIO_INREG: GPIO_IN4 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN4_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN4_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN4 Mask */
+#define SGPIO_GPIO_INREG_GPIO_IN5_Pos 5 /*!< SGPIO GPIO_INREG: GPIO_IN5 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN5_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN5_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN5 Mask */
+#define SGPIO_GPIO_INREG_GPIO_IN6_Pos 6 /*!< SGPIO GPIO_INREG: GPIO_IN6 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN6_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN6_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN6 Mask */
+#define SGPIO_GPIO_INREG_GPIO_IN7_Pos 7 /*!< SGPIO GPIO_INREG: GPIO_IN7 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN7_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN7_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN7 Mask */
+#define SGPIO_GPIO_INREG_GPIO_IN8_Pos 8 /*!< SGPIO GPIO_INREG: GPIO_IN8 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN8_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN8_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN8 Mask */
+#define SGPIO_GPIO_INREG_GPIO_IN9_Pos 9 /*!< SGPIO GPIO_INREG: GPIO_IN9 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN9_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN9_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN9 Mask */
+#define SGPIO_GPIO_INREG_GPIO_IN10_Pos 10 /*!< SGPIO GPIO_INREG: GPIO_IN10 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN10_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN10_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN10 Mask */
+#define SGPIO_GPIO_INREG_GPIO_IN11_Pos 11 /*!< SGPIO GPIO_INREG: GPIO_IN11 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN11_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN11_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN11 Mask */
+#define SGPIO_GPIO_INREG_GPIO_IN12_Pos 12 /*!< SGPIO GPIO_INREG: GPIO_IN12 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN12_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN12_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN12 Mask */
+#define SGPIO_GPIO_INREG_GPIO_IN13_Pos 13 /*!< SGPIO GPIO_INREG: GPIO_IN13 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN13_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN13_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN13 Mask */
+#define SGPIO_GPIO_INREG_GPIO_IN14_Pos 14 /*!< SGPIO GPIO_INREG: GPIO_IN14 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN14_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN14_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN14 Mask */
+#define SGPIO_GPIO_INREG_GPIO_IN15_Pos 15 /*!< SGPIO GPIO_INREG: GPIO_IN15 Position */
+#define SGPIO_GPIO_INREG_GPIO_IN15_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN15_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN15 Mask */
+
+// ------------------------------------ SGPIO_GPIO_OUTREG ---------------------------------------
+#define SGPIO_GPIO_OUTREG_GPIO_OUT0_Pos 0 /*!< SGPIO GPIO_OUTREG: GPIO_OUT0 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT0_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT0_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT0 Mask */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT1_Pos 1 /*!< SGPIO GPIO_OUTREG: GPIO_OUT1 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT1_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT1_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT1 Mask */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT2_Pos 2 /*!< SGPIO GPIO_OUTREG: GPIO_OUT2 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT2_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT2_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT2 Mask */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT3_Pos 3 /*!< SGPIO GPIO_OUTREG: GPIO_OUT3 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT3_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT3_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT3 Mask */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT4_Pos 4 /*!< SGPIO GPIO_OUTREG: GPIO_OUT4 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT4_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT4_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT4 Mask */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT5_Pos 5 /*!< SGPIO GPIO_OUTREG: GPIO_OUT5 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT5_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT5_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT5 Mask */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT6_Pos 6 /*!< SGPIO GPIO_OUTREG: GPIO_OUT6 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT6_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT6_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT6 Mask */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT7_Pos 7 /*!< SGPIO GPIO_OUTREG: GPIO_OUT7 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT7_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT7_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT7 Mask */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT8_Pos 8 /*!< SGPIO GPIO_OUTREG: GPIO_OUT8 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT8_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT8_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT8 Mask */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT9_Pos 9 /*!< SGPIO GPIO_OUTREG: GPIO_OUT9 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT9_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT9_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT9 Mask */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT10_Pos 10 /*!< SGPIO GPIO_OUTREG: GPIO_OUT10 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT10_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT10_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT10 Mask */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT11_Pos 11 /*!< SGPIO GPIO_OUTREG: GPIO_OUT11 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT11_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT11_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT11 Mask */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT12_Pos 12 /*!< SGPIO GPIO_OUTREG: GPIO_OUT12 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT12_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT12_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT12 Mask */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT13_Pos 13 /*!< SGPIO GPIO_OUTREG: GPIO_OUT13 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT13_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT13_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT13 Mask */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT14_Pos 14 /*!< SGPIO GPIO_OUTREG: GPIO_OUT14 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT14_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT14_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT14 Mask */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT15_Pos 15 /*!< SGPIO GPIO_OUTREG: GPIO_OUT15 Position */
+#define SGPIO_GPIO_OUTREG_GPIO_OUT15_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT15_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT15 Mask */
+
+// ------------------------------------ SGPIO_GPIO_OENREG ---------------------------------------
+#define SGPIO_GPIO_OENREG_GPIO_OE0_Pos 0 /*!< SGPIO GPIO_OENREG: GPIO_OE0 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE0_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE0_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE0 Mask */
+#define SGPIO_GPIO_OENREG_GPIO_OE1_Pos 1 /*!< SGPIO GPIO_OENREG: GPIO_OE1 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE1_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE1_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE1 Mask */
+#define SGPIO_GPIO_OENREG_GPIO_OE2_Pos 2 /*!< SGPIO GPIO_OENREG: GPIO_OE2 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE2_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE2_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE2 Mask */
+#define SGPIO_GPIO_OENREG_GPIO_OE3_Pos 3 /*!< SGPIO GPIO_OENREG: GPIO_OE3 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE3_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE3_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE3 Mask */
+#define SGPIO_GPIO_OENREG_GPIO_OE4_Pos 4 /*!< SGPIO GPIO_OENREG: GPIO_OE4 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE4_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE4_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE4 Mask */
+#define SGPIO_GPIO_OENREG_GPIO_OE5_Pos 5 /*!< SGPIO GPIO_OENREG: GPIO_OE5 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE5_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE5_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE5 Mask */
+#define SGPIO_GPIO_OENREG_GPIO_OE6_Pos 6 /*!< SGPIO GPIO_OENREG: GPIO_OE6 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE6_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE6_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE6 Mask */
+#define SGPIO_GPIO_OENREG_GPIO_OE7_Pos 7 /*!< SGPIO GPIO_OENREG: GPIO_OE7 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE7_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE7_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE7 Mask */
+#define SGPIO_GPIO_OENREG_GPIO_OE8_Pos 8 /*!< SGPIO GPIO_OENREG: GPIO_OE8 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE8_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE8_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE8 Mask */
+#define SGPIO_GPIO_OENREG_GPIO_OE9_Pos 9 /*!< SGPIO GPIO_OENREG: GPIO_OE9 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE9_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE9_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE9 Mask */
+#define SGPIO_GPIO_OENREG_GPIO_OE10_Pos 10 /*!< SGPIO GPIO_OENREG: GPIO_OE10 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE10_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE10_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE10 Mask */
+#define SGPIO_GPIO_OENREG_GPIO_OE11_Pos 11 /*!< SGPIO GPIO_OENREG: GPIO_OE11 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE11_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE11_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE11 Mask */
+#define SGPIO_GPIO_OENREG_GPIO_OE12_Pos 12 /*!< SGPIO GPIO_OENREG: GPIO_OE12 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE12_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE12_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE12 Mask */
+#define SGPIO_GPIO_OENREG_GPIO_OE13_Pos 13 /*!< SGPIO GPIO_OENREG: GPIO_OE13 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE13_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE13_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE13 Mask */
+#define SGPIO_GPIO_OENREG_GPIO_OE14_Pos 14 /*!< SGPIO GPIO_OENREG: GPIO_OE14 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE14_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE14_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE14 Mask */
+#define SGPIO_GPIO_OENREG_GPIO_OE15_Pos 15 /*!< SGPIO GPIO_OENREG: GPIO_OE15 Position */
+#define SGPIO_GPIO_OENREG_GPIO_OE15_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE15_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE15 Mask */
+
+// ----------------------------------- SGPIO_CTRL_ENABLED ---------------------------------------
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED0_Pos 0 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED0 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED0_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED0_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED0 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED1_Pos 1 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED1 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED1_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED1_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED1 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED2_Pos 2 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED2 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED2_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED2_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED2 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED3_Pos 3 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED3 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED3_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED3_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED3 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED4_Pos 4 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED4 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED4_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED4_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED4 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED5_Pos 5 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED5 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED5_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED5_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED5 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED6_Pos 6 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED6 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED6_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED6_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED6 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED7_Pos 7 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED7 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED7_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED7_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED7 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED8_Pos 8 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED8 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED8_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED8_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED8 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED9_Pos 9 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED9 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED9_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED9_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED9 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED10_Pos 10 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED10 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED10_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED10_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED10 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED11_Pos 11 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED11 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED11_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED11_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED11 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED12_Pos 12 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED12 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED12_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED12_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED12 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED13_Pos 13 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED13 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED13_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED13_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED13 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED14_Pos 14 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED14 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED14_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED14_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED14 Mask */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED15_Pos 15 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED15 Position */
+#define SGPIO_CTRL_ENABLED_CTRL_ENABLED15_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED15_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED15 Mask */
+
+// ----------------------------------- SGPIO_CTRL_DISABLED --------------------------------------
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn0_Pos 0 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn0 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn0_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn0_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn0 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn1_Pos 1 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn1 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn1_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn1_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn1 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn2_Pos 2 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn2 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn2_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn2_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn2 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn3_Pos 3 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn3 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn3_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn3_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn3 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn4_Pos 4 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn4 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn4_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn4_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn4 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn5_Pos 5 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn5 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn5_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn5_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn5 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn6_Pos 6 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn6 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn6_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn6_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn6 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn7_Pos 7 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn7 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn7_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn7_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn7 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn8_Pos 8 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn8 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn8_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn8_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn8 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn9_Pos 9 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn9 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn9_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn9_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn9 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn10_Pos 10 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn10 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn10_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn10_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn10 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn11_Pos 11 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn11 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn11_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn11_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn11 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn12_Pos 12 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn12 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn12_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn12_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn12 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn13_Pos 13 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn13 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn13_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn13_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn13 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn14_Pos 14 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn14 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn14_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn14_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn14 Mask */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn15_Pos 15 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn15 Position */
+#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn15_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn15_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn15 Mask */
+
+// ------------------------------------- SGPIO_CLR_EN_0 -----------------------------------------
+#define SGPIO_CLR_EN_0_CLR_SCI0_Pos 0 /*!< SGPIO CLR_EN_0: CLR_SCI0 Position */
+#define SGPIO_CLR_EN_0_CLR_SCI0_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI0_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI0 Mask */
+#define SGPIO_CLR_EN_0_CLR_SCI1_Pos 1 /*!< SGPIO CLR_EN_0: CLR_SCI1 Position */
+#define SGPIO_CLR_EN_0_CLR_SCI1_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI1_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI1 Mask */
+#define SGPIO_CLR_EN_0_CLR_SCI2_Pos 2 /*!< SGPIO CLR_EN_0: CLR_SCI2 Position */
+#define SGPIO_CLR_EN_0_CLR_SCI2_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI2_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI2 Mask */
+#define SGPIO_CLR_EN_0_CLR_SCI3_Pos 3 /*!< SGPIO CLR_EN_0: CLR_SCI3 Position */
+#define SGPIO_CLR_EN_0_CLR_SCI3_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI3_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI3 Mask */
+#define SGPIO_CLR_EN_0_CLR_SCI4_Pos 4 /*!< SGPIO CLR_EN_0: CLR_SCI4 Position */
+#define SGPIO_CLR_EN_0_CLR_SCI4_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI4_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI4 Mask */
+#define SGPIO_CLR_EN_0_CLR_SCI5_Pos 5 /*!< SGPIO CLR_EN_0: CLR_SCI5 Position */
+#define SGPIO_CLR_EN_0_CLR_SCI5_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI5_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI5 Mask */
+#define SGPIO_CLR_EN_0_CLR_SCI6_Pos 6 /*!< SGPIO CLR_EN_0: CLR_SCI6 Position */
+#define SGPIO_CLR_EN_0_CLR_SCI6_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI6_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI6 Mask */
+#define SGPIO_CLR_EN_0_CLR_SCI7_Pos 7 /*!< SGPIO CLR_EN_0: CLR_SCI7 Position */
+#define SGPIO_CLR_EN_0_CLR_SCI7_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI7_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI7 Mask */
+#define SGPIO_CLR_EN_0_CLR_SCI8_Pos 8 /*!< SGPIO CLR_EN_0: CLR_SCI8 Position */
+#define SGPIO_CLR_EN_0_CLR_SCI8_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI8_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI8 Mask */
+#define SGPIO_CLR_EN_0_CLR_SCI9_Pos 9 /*!< SGPIO CLR_EN_0: CLR_SCI9 Position */
+#define SGPIO_CLR_EN_0_CLR_SCI9_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI9_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI9 Mask */
+#define SGPIO_CLR_EN_0_CLR_SCI10_Pos 10 /*!< SGPIO CLR_EN_0: CLR_SCI10 Position */
+#define SGPIO_CLR_EN_0_CLR_SCI10_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI10_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI10 Mask */
+#define SGPIO_CLR_EN_0_CLR_SCI11_Pos 11 /*!< SGPIO CLR_EN_0: CLR_SCI11 Position */
+#define SGPIO_CLR_EN_0_CLR_SCI11_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI11_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI11 Mask */
+#define SGPIO_CLR_EN_0_CLR_SCI12_Pos 12 /*!< SGPIO CLR_EN_0: CLR_SCI12 Position */
+#define SGPIO_CLR_EN_0_CLR_SCI12_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI12_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI12 Mask */
+#define SGPIO_CLR_EN_0_CLR_SCI13_Pos 13 /*!< SGPIO CLR_EN_0: CLR_SCI13 Position */
+#define SGPIO_CLR_EN_0_CLR_SCI13_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI13_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI13 Mask */
+#define SGPIO_CLR_EN_0_CLR_SCI14_Pos 14 /*!< SGPIO CLR_EN_0: CLR_SCI14 Position */
+#define SGPIO_CLR_EN_0_CLR_SCI14_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI14_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI14 Mask */
+#define SGPIO_CLR_EN_0_CLR_SCI15_Pos 15 /*!< SGPIO CLR_EN_0: CLR_SCI15 Position */
+#define SGPIO_CLR_EN_0_CLR_SCI15_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI15_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI15 Mask */
+
+// ------------------------------------- SGPIO_SET_EN_0 -----------------------------------------
+#define SGPIO_SET_EN_0_SET_SCI0_Pos 0 /*!< SGPIO SET_EN_0: SET_SCI0 Position */
+#define SGPIO_SET_EN_0_SET_SCI0_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI0_Pos) /*!< SGPIO SET_EN_0: SET_SCI0 Mask */
+#define SGPIO_SET_EN_0_SET_SCI1_Pos 1 /*!< SGPIO SET_EN_0: SET_SCI1 Position */
+#define SGPIO_SET_EN_0_SET_SCI1_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI1_Pos) /*!< SGPIO SET_EN_0: SET_SCI1 Mask */
+#define SGPIO_SET_EN_0_SET_SCI2_Pos 2 /*!< SGPIO SET_EN_0: SET_SCI2 Position */
+#define SGPIO_SET_EN_0_SET_SCI2_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI2_Pos) /*!< SGPIO SET_EN_0: SET_SCI2 Mask */
+#define SGPIO_SET_EN_0_SET_SCI3_Pos 3 /*!< SGPIO SET_EN_0: SET_SCI3 Position */
+#define SGPIO_SET_EN_0_SET_SCI3_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI3_Pos) /*!< SGPIO SET_EN_0: SET_SCI3 Mask */
+#define SGPIO_SET_EN_0_SET_SCI4_Pos 4 /*!< SGPIO SET_EN_0: SET_SCI4 Position */
+#define SGPIO_SET_EN_0_SET_SCI4_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI4_Pos) /*!< SGPIO SET_EN_0: SET_SCI4 Mask */
+#define SGPIO_SET_EN_0_SET_SCI5_Pos 5 /*!< SGPIO SET_EN_0: SET_SCI5 Position */
+#define SGPIO_SET_EN_0_SET_SCI5_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI5_Pos) /*!< SGPIO SET_EN_0: SET_SCI5 Mask */
+#define SGPIO_SET_EN_0_SET_SCI6_Pos 6 /*!< SGPIO SET_EN_0: SET_SCI6 Position */
+#define SGPIO_SET_EN_0_SET_SCI6_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI6_Pos) /*!< SGPIO SET_EN_0: SET_SCI6 Mask */
+#define SGPIO_SET_EN_0_SET_SCI7_Pos 7 /*!< SGPIO SET_EN_0: SET_SCI7 Position */
+#define SGPIO_SET_EN_0_SET_SCI7_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI7_Pos) /*!< SGPIO SET_EN_0: SET_SCI7 Mask */
+#define SGPIO_SET_EN_0_SET_SCI8_Pos 8 /*!< SGPIO SET_EN_0: SET_SCI8 Position */
+#define SGPIO_SET_EN_0_SET_SCI8_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI8_Pos) /*!< SGPIO SET_EN_0: SET_SCI8 Mask */
+#define SGPIO_SET_EN_0_SET_SCI9_Pos 9 /*!< SGPIO SET_EN_0: SET_SCI9 Position */
+#define SGPIO_SET_EN_0_SET_SCI9_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI9_Pos) /*!< SGPIO SET_EN_0: SET_SCI9 Mask */
+#define SGPIO_SET_EN_0_SET_SCI10_Pos 10 /*!< SGPIO SET_EN_0: SET_SCI10 Position */
+#define SGPIO_SET_EN_0_SET_SCI10_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI10_Pos) /*!< SGPIO SET_EN_0: SET_SCI10 Mask */
+#define SGPIO_SET_EN_0_SET_SCI11_Pos 11 /*!< SGPIO SET_EN_0: SET_SCI11 Position */
+#define SGPIO_SET_EN_0_SET_SCI11_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI11_Pos) /*!< SGPIO SET_EN_0: SET_SCI11 Mask */
+#define SGPIO_SET_EN_0_SET_SCI12_Pos 12 /*!< SGPIO SET_EN_0: SET_SCI12 Position */
+#define SGPIO_SET_EN_0_SET_SCI12_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI12_Pos) /*!< SGPIO SET_EN_0: SET_SCI12 Mask */
+#define SGPIO_SET_EN_0_SET_SCI13_Pos 13 /*!< SGPIO SET_EN_0: SET_SCI13 Position */
+#define SGPIO_SET_EN_0_SET_SCI13_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI13_Pos) /*!< SGPIO SET_EN_0: SET_SCI13 Mask */
+#define SGPIO_SET_EN_0_SET_SCI14_Pos 14 /*!< SGPIO SET_EN_0: SET_SCI14 Position */
+#define SGPIO_SET_EN_0_SET_SCI14_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI14_Pos) /*!< SGPIO SET_EN_0: SET_SCI14 Mask */
+#define SGPIO_SET_EN_0_SET_SCI15_Pos 15 /*!< SGPIO SET_EN_0: SET_SCI15 Position */
+#define SGPIO_SET_EN_0_SET_SCI15_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI15_Pos) /*!< SGPIO SET_EN_0: SET_SCI15 Mask */
+
+// ------------------------------------- SGPIO_ENABLE_0 -----------------------------------------
+#define SGPIO_ENABLE_0_ENABLE_SCI0_Pos 0 /*!< SGPIO ENABLE_0: ENABLE_SCI0 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI0_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI0_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI0 Mask */
+#define SGPIO_ENABLE_0_ENABLE_SCI1_Pos 1 /*!< SGPIO ENABLE_0: ENABLE_SCI1 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI1_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI1_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI1 Mask */
+#define SGPIO_ENABLE_0_ENABLE_SCI2_Pos 2 /*!< SGPIO ENABLE_0: ENABLE_SCI2 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI2_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI2_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI2 Mask */
+#define SGPIO_ENABLE_0_ENABLE_SCI3_Pos 3 /*!< SGPIO ENABLE_0: ENABLE_SCI3 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI3_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI3_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI3 Mask */
+#define SGPIO_ENABLE_0_ENABLE_SCI4_Pos 4 /*!< SGPIO ENABLE_0: ENABLE_SCI4 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI4_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI4_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI4 Mask */
+#define SGPIO_ENABLE_0_ENABLE_SCI5_Pos 5 /*!< SGPIO ENABLE_0: ENABLE_SCI5 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI5_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI5_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI5 Mask */
+#define SGPIO_ENABLE_0_ENABLE_SCI6_Pos 6 /*!< SGPIO ENABLE_0: ENABLE_SCI6 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI6_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI6_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI6 Mask */
+#define SGPIO_ENABLE_0_ENABLE_SCI7_Pos 7 /*!< SGPIO ENABLE_0: ENABLE_SCI7 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI7_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI7_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI7 Mask */
+#define SGPIO_ENABLE_0_ENABLE_SCI8_Pos 8 /*!< SGPIO ENABLE_0: ENABLE_SCI8 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI8_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI8_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI8 Mask */
+#define SGPIO_ENABLE_0_ENABLE_SCI9_Pos 9 /*!< SGPIO ENABLE_0: ENABLE_SCI9 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI9_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI9_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI9 Mask */
+#define SGPIO_ENABLE_0_ENABLE_SCI10_Pos 10 /*!< SGPIO ENABLE_0: ENABLE_SCI10 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI10_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI10_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI10 Mask */
+#define SGPIO_ENABLE_0_ENABLE_SCI11_Pos 11 /*!< SGPIO ENABLE_0: ENABLE_SCI11 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI11_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI11_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI11 Mask */
+#define SGPIO_ENABLE_0_ENABLE_SCI12_Pos 12 /*!< SGPIO ENABLE_0: ENABLE_SCI12 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI12_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI12_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI12 Mask */
+#define SGPIO_ENABLE_0_ENABLE_SCI13_Pos 13 /*!< SGPIO ENABLE_0: ENABLE_SCI13 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI13_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI13_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI13 Mask */
+#define SGPIO_ENABLE_0_ENABLE_SCI14_Pos 14 /*!< SGPIO ENABLE_0: ENABLE_SCI14 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI14_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI14_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI14 Mask */
+#define SGPIO_ENABLE_0_ENABLE_SCI15_Pos 15 /*!< SGPIO ENABLE_0: ENABLE_SCI15 Position */
+#define SGPIO_ENABLE_0_ENABLE_SCI15_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI15_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI15 Mask */
+
+// ------------------------------------- SGPIO_STATUS_0 -----------------------------------------
+#define SGPIO_STATUS_0_STATUS_SCI0_Pos 0 /*!< SGPIO STATUS_0: STATUS_SCI0 Position */
+#define SGPIO_STATUS_0_STATUS_SCI0_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI0_Pos) /*!< SGPIO STATUS_0: STATUS_SCI0 Mask */
+#define SGPIO_STATUS_0_STATUS_SCI1_Pos 1 /*!< SGPIO STATUS_0: STATUS_SCI1 Position */
+#define SGPIO_STATUS_0_STATUS_SCI1_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI1_Pos) /*!< SGPIO STATUS_0: STATUS_SCI1 Mask */
+#define SGPIO_STATUS_0_STATUS_SCI2_Pos 2 /*!< SGPIO STATUS_0: STATUS_SCI2 Position */
+#define SGPIO_STATUS_0_STATUS_SCI2_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI2_Pos) /*!< SGPIO STATUS_0: STATUS_SCI2 Mask */
+#define SGPIO_STATUS_0_STATUS_SCI3_Pos 3 /*!< SGPIO STATUS_0: STATUS_SCI3 Position */
+#define SGPIO_STATUS_0_STATUS_SCI3_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI3_Pos) /*!< SGPIO STATUS_0: STATUS_SCI3 Mask */
+#define SGPIO_STATUS_0_STATUS_SCI4_Pos 4 /*!< SGPIO STATUS_0: STATUS_SCI4 Position */
+#define SGPIO_STATUS_0_STATUS_SCI4_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI4_Pos) /*!< SGPIO STATUS_0: STATUS_SCI4 Mask */
+#define SGPIO_STATUS_0_STATUS_SCI5_Pos 5 /*!< SGPIO STATUS_0: STATUS_SCI5 Position */
+#define SGPIO_STATUS_0_STATUS_SCI5_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI5_Pos) /*!< SGPIO STATUS_0: STATUS_SCI5 Mask */
+#define SGPIO_STATUS_0_STATUS_SCI6_Pos 6 /*!< SGPIO STATUS_0: STATUS_SCI6 Position */
+#define SGPIO_STATUS_0_STATUS_SCI6_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI6_Pos) /*!< SGPIO STATUS_0: STATUS_SCI6 Mask */
+#define SGPIO_STATUS_0_STATUS_SCI7_Pos 7 /*!< SGPIO STATUS_0: STATUS_SCI7 Position */
+#define SGPIO_STATUS_0_STATUS_SCI7_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI7_Pos) /*!< SGPIO STATUS_0: STATUS_SCI7 Mask */
+#define SGPIO_STATUS_0_STATUS_SCI8_Pos 8 /*!< SGPIO STATUS_0: STATUS_SCI8 Position */
+#define SGPIO_STATUS_0_STATUS_SCI8_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI8_Pos) /*!< SGPIO STATUS_0: STATUS_SCI8 Mask */
+#define SGPIO_STATUS_0_STATUS_SCI9_Pos 9 /*!< SGPIO STATUS_0: STATUS_SCI9 Position */
+#define SGPIO_STATUS_0_STATUS_SCI9_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI9_Pos) /*!< SGPIO STATUS_0: STATUS_SCI9 Mask */
+#define SGPIO_STATUS_0_STATUS_SCI10_Pos 10 /*!< SGPIO STATUS_0: STATUS_SCI10 Position */
+#define SGPIO_STATUS_0_STATUS_SCI10_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI10_Pos) /*!< SGPIO STATUS_0: STATUS_SCI10 Mask */
+#define SGPIO_STATUS_0_STATUS_SCI11_Pos 11 /*!< SGPIO STATUS_0: STATUS_SCI11 Position */
+#define SGPIO_STATUS_0_STATUS_SCI11_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI11_Pos) /*!< SGPIO STATUS_0: STATUS_SCI11 Mask */
+#define SGPIO_STATUS_0_STATUS_SCI12_Pos 12 /*!< SGPIO STATUS_0: STATUS_SCI12 Position */
+#define SGPIO_STATUS_0_STATUS_SCI12_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI12_Pos) /*!< SGPIO STATUS_0: STATUS_SCI12 Mask */
+#define SGPIO_STATUS_0_STATUS_SCI13_Pos 13 /*!< SGPIO STATUS_0: STATUS_SCI13 Position */
+#define SGPIO_STATUS_0_STATUS_SCI13_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI13_Pos) /*!< SGPIO STATUS_0: STATUS_SCI13 Mask */
+#define SGPIO_STATUS_0_STATUS_SCI14_Pos 14 /*!< SGPIO STATUS_0: STATUS_SCI14 Position */
+#define SGPIO_STATUS_0_STATUS_SCI14_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI14_Pos) /*!< SGPIO STATUS_0: STATUS_SCI14 Mask */
+#define SGPIO_STATUS_0_STATUS_SCI15_Pos 15 /*!< SGPIO STATUS_0: STATUS_SCI15 Position */
+#define SGPIO_STATUS_0_STATUS_SCI15_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI15_Pos) /*!< SGPIO STATUS_0: STATUS_SCI15 Mask */
+
+// ----------------------------------- SGPIO_CTR_STATUS_0 ---------------------------------------
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI0_Pos 0 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI0 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI0_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI0_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI0 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI1_Pos 1 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI1 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI1_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI1_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI1 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI2_Pos 2 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI2 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI2_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI2_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI2 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI3_Pos 3 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI3 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI3_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI3_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI3 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI4_Pos 4 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI4 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI4_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI4_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI4 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI5_Pos 5 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI5 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI5_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI5_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI5 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI6_Pos 6 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI6 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI6_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI6_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI6 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI7_Pos 7 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI7 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI7_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI7_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI7 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI8_Pos 8 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI8 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI8_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI8_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI8 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI9_Pos 9 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI9 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI9_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI9_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI9 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI10_Pos 10 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI10 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI10_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI10_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI10 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI11_Pos 11 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI11 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI11_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI11_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI11 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI12_Pos 12 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI12 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI12_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI12_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI12 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI13_Pos 13 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI13 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI13_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI13_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI13 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI14_Pos 14 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI14 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI14_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI14_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI14 Mask */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI15_Pos 15 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI15 Position */
+#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI15_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI15_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI15 Mask */
+
+// ----------------------------------- SGPIO_SET_STATUS_0 ---------------------------------------
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI0_Pos 0 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI0 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI0_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI0_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI0 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI1_Pos 1 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI1 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI1_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI1_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI1 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI2_Pos 2 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI2 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI2_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI2_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI2 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI3_Pos 3 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI3 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI3_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI3_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI3 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI4_Pos 4 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI4 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI4_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI4_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI4 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI5_Pos 5 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI5 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI5_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI5_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI5 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI6_Pos 6 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI6 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI6_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI6_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI6 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI7_Pos 7 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI7 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI7_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI7_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI7 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI8_Pos 8 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI8 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI8_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI8_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI8 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI9_Pos 9 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI9 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI9_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI9_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI9 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI10_Pos 10 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI10 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI10_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI10_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI10 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI11_Pos 11 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI11 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI11_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI11_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI11 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI12_Pos 12 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI12 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI12_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI12_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI12 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI13_Pos 13 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI13 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI13_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI13_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI13 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI14_Pos 14 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI14 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI14_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI14_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI14 Mask */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI15_Pos 15 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI15 Position */
+#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI15_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI15_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI15 Mask */
+
+// ------------------------------------- SGPIO_CLR_EN_1 -----------------------------------------
+#define SGPIO_CLR_EN_1_CLR_EN_CCI0_Pos 0 /*!< SGPIO CLR_EN_1: CLR_EN_CCI0 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI0_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI0_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI0 Mask */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI1_Pos 1 /*!< SGPIO CLR_EN_1: CLR_EN_CCI1 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI1_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI1_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI1 Mask */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI2_Pos 2 /*!< SGPIO CLR_EN_1: CLR_EN_CCI2 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI2_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI2_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI2 Mask */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI3_Pos 3 /*!< SGPIO CLR_EN_1: CLR_EN_CCI3 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI3_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI3_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI3 Mask */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI4_Pos 4 /*!< SGPIO CLR_EN_1: CLR_EN_CCI4 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI4_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI4_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI4 Mask */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI5_Pos 5 /*!< SGPIO CLR_EN_1: CLR_EN_CCI5 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI5_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI5_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI5 Mask */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI6_Pos 6 /*!< SGPIO CLR_EN_1: CLR_EN_CCI6 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI6_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI6_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI6 Mask */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI7_Pos 7 /*!< SGPIO CLR_EN_1: CLR_EN_CCI7 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI7_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI7_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI7 Mask */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI8_Pos 8 /*!< SGPIO CLR_EN_1: CLR_EN_CCI8 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI8_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI8_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI8 Mask */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI9_Pos 9 /*!< SGPIO CLR_EN_1: CLR_EN_CCI9 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI9_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI9_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI9 Mask */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI10_Pos 10 /*!< SGPIO CLR_EN_1: CLR_EN_CCI10 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI10_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI10_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI10 Mask */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI11_Pos 11 /*!< SGPIO CLR_EN_1: CLR_EN_CCI11 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI11_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI11_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI11 Mask */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI12_Pos 12 /*!< SGPIO CLR_EN_1: CLR_EN_CCI12 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI12_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI12_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI12 Mask */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI13_Pos 13 /*!< SGPIO CLR_EN_1: CLR_EN_CCI13 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI13_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI13_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI13 Mask */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI14_Pos 14 /*!< SGPIO CLR_EN_1: CLR_EN_CCI14 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI14_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI14_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI14 Mask */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI15_Pos 15 /*!< SGPIO CLR_EN_1: CLR_EN_CCI15 Position */
+#define SGPIO_CLR_EN_1_CLR_EN_CCI15_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI15_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI15 Mask */
+
+// ------------------------------------- SGPIO_SET_EN_1 -----------------------------------------
+#define SGPIO_SET_EN_1_SET_EN_CCI0_Pos 0 /*!< SGPIO SET_EN_1: SET_EN_CCI0 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI0_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI0_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI0 Mask */
+#define SGPIO_SET_EN_1_SET_EN_CCI1_Pos 1 /*!< SGPIO SET_EN_1: SET_EN_CCI1 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI1_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI1_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI1 Mask */
+#define SGPIO_SET_EN_1_SET_EN_CCI2_Pos 2 /*!< SGPIO SET_EN_1: SET_EN_CCI2 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI2_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI2_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI2 Mask */
+#define SGPIO_SET_EN_1_SET_EN_CCI3_Pos 3 /*!< SGPIO SET_EN_1: SET_EN_CCI3 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI3_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI3_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI3 Mask */
+#define SGPIO_SET_EN_1_SET_EN_CCI4_Pos 4 /*!< SGPIO SET_EN_1: SET_EN_CCI4 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI4_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI4_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI4 Mask */
+#define SGPIO_SET_EN_1_SET_EN_CCI5_Pos 5 /*!< SGPIO SET_EN_1: SET_EN_CCI5 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI5_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI5_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI5 Mask */
+#define SGPIO_SET_EN_1_SET_EN_CCI6_Pos 6 /*!< SGPIO SET_EN_1: SET_EN_CCI6 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI6_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI6_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI6 Mask */
+#define SGPIO_SET_EN_1_SET_EN_CCI7_Pos 7 /*!< SGPIO SET_EN_1: SET_EN_CCI7 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI7_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI7_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI7 Mask */
+#define SGPIO_SET_EN_1_SET_EN_CCI8_Pos 8 /*!< SGPIO SET_EN_1: SET_EN_CCI8 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI8_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI8_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI8 Mask */
+#define SGPIO_SET_EN_1_SET_EN_CCI9_Pos 9 /*!< SGPIO SET_EN_1: SET_EN_CCI9 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI9_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI9_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI9 Mask */
+#define SGPIO_SET_EN_1_SET_EN_CCI10_Pos 10 /*!< SGPIO SET_EN_1: SET_EN_CCI10 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI10_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI10_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI10 Mask */
+#define SGPIO_SET_EN_1_SET_EN_CCI11_Pos 11 /*!< SGPIO SET_EN_1: SET_EN_CCI11 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI11_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI11_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI11 Mask */
+#define SGPIO_SET_EN_1_SET_EN_CCI12_Pos 12 /*!< SGPIO SET_EN_1: SET_EN_CCI12 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI12_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI12_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI12 Mask */
+#define SGPIO_SET_EN_1_SET_EN_CCI13_Pos 13 /*!< SGPIO SET_EN_1: SET_EN_CCI13 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI13_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI13_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI13 Mask */
+#define SGPIO_SET_EN_1_SET_EN_CCI14_Pos 14 /*!< SGPIO SET_EN_1: SET_EN_CCI14 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI14_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI14_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI14 Mask */
+#define SGPIO_SET_EN_1_SET_EN_CCI15_Pos 15 /*!< SGPIO SET_EN_1: SET_EN_CCI15 Position */
+#define SGPIO_SET_EN_1_SET_EN_CCI15_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI15_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI15 Mask */
+
+// ------------------------------------- SGPIO_ENABLE_1 -----------------------------------------
+#define SGPIO_ENABLE_1_ENABLE_CCI0_Pos 0 /*!< SGPIO ENABLE_1: ENABLE_CCI0 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI0_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI0_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI0 Mask */
+#define SGPIO_ENABLE_1_ENABLE_CCI1_Pos 1 /*!< SGPIO ENABLE_1: ENABLE_CCI1 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI1_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI1_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI1 Mask */
+#define SGPIO_ENABLE_1_ENABLE_CCI2_Pos 2 /*!< SGPIO ENABLE_1: ENABLE_CCI2 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI2_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI2_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI2 Mask */
+#define SGPIO_ENABLE_1_ENABLE_CCI3_Pos 3 /*!< SGPIO ENABLE_1: ENABLE_CCI3 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI3_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI3_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI3 Mask */
+#define SGPIO_ENABLE_1_ENABLE_CCI4_Pos 4 /*!< SGPIO ENABLE_1: ENABLE_CCI4 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI4_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI4_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI4 Mask */
+#define SGPIO_ENABLE_1_ENABLE_CCI5_Pos 5 /*!< SGPIO ENABLE_1: ENABLE_CCI5 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI5_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI5_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI5 Mask */
+#define SGPIO_ENABLE_1_ENABLE_CCI6_Pos 6 /*!< SGPIO ENABLE_1: ENABLE_CCI6 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI6_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI6_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI6 Mask */
+#define SGPIO_ENABLE_1_ENABLE_CCI7_Pos 7 /*!< SGPIO ENABLE_1: ENABLE_CCI7 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI7_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI7_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI7 Mask */
+#define SGPIO_ENABLE_1_ENABLE_CCI8_Pos 8 /*!< SGPIO ENABLE_1: ENABLE_CCI8 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI8_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI8_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI8 Mask */
+#define SGPIO_ENABLE_1_ENABLE_CCI9_Pos 9 /*!< SGPIO ENABLE_1: ENABLE_CCI9 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI9_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI9_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI9 Mask */
+#define SGPIO_ENABLE_1_ENABLE_CCI10_Pos 10 /*!< SGPIO ENABLE_1: ENABLE_CCI10 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI10_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI10_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI10 Mask */
+#define SGPIO_ENABLE_1_ENABLE_CCI11_Pos 11 /*!< SGPIO ENABLE_1: ENABLE_CCI11 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI11_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI11_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI11 Mask */
+#define SGPIO_ENABLE_1_ENABLE_CCI12_Pos 12 /*!< SGPIO ENABLE_1: ENABLE_CCI12 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI12_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI12_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI12 Mask */
+#define SGPIO_ENABLE_1_ENABLE_CCI13_Pos 13 /*!< SGPIO ENABLE_1: ENABLE_CCI13 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI13_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI13_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI13 Mask */
+#define SGPIO_ENABLE_1_ENABLE_CCI14_Pos 14 /*!< SGPIO ENABLE_1: ENABLE_CCI14 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI14_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI14_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI14 Mask */
+#define SGPIO_ENABLE_1_ENABLE_CCI15_Pos 15 /*!< SGPIO ENABLE_1: ENABLE_CCI15 Position */
+#define SGPIO_ENABLE_1_ENABLE_CCI15_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI15_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI15 Mask */
+
+// ------------------------------------- SGPIO_STATUS_1 -----------------------------------------
+#define SGPIO_STATUS_1_STATUS_CCI0_Pos 0 /*!< SGPIO STATUS_1: STATUS_CCI0 Position */
+#define SGPIO_STATUS_1_STATUS_CCI0_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI0_Pos) /*!< SGPIO STATUS_1: STATUS_CCI0 Mask */
+#define SGPIO_STATUS_1_STATUS_CCI1_Pos 1 /*!< SGPIO STATUS_1: STATUS_CCI1 Position */
+#define SGPIO_STATUS_1_STATUS_CCI1_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI1_Pos) /*!< SGPIO STATUS_1: STATUS_CCI1 Mask */
+#define SGPIO_STATUS_1_STATUS_CCI2_Pos 2 /*!< SGPIO STATUS_1: STATUS_CCI2 Position */
+#define SGPIO_STATUS_1_STATUS_CCI2_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI2_Pos) /*!< SGPIO STATUS_1: STATUS_CCI2 Mask */
+#define SGPIO_STATUS_1_STATUS_CCI3_Pos 3 /*!< SGPIO STATUS_1: STATUS_CCI3 Position */
+#define SGPIO_STATUS_1_STATUS_CCI3_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI3_Pos) /*!< SGPIO STATUS_1: STATUS_CCI3 Mask */
+#define SGPIO_STATUS_1_STATUS_CCI4_Pos 4 /*!< SGPIO STATUS_1: STATUS_CCI4 Position */
+#define SGPIO_STATUS_1_STATUS_CCI4_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI4_Pos) /*!< SGPIO STATUS_1: STATUS_CCI4 Mask */
+#define SGPIO_STATUS_1_STATUS_CCI5_Pos 5 /*!< SGPIO STATUS_1: STATUS_CCI5 Position */
+#define SGPIO_STATUS_1_STATUS_CCI5_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI5_Pos) /*!< SGPIO STATUS_1: STATUS_CCI5 Mask */
+#define SGPIO_STATUS_1_STATUS_CCI6_Pos 6 /*!< SGPIO STATUS_1: STATUS_CCI6 Position */
+#define SGPIO_STATUS_1_STATUS_CCI6_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI6_Pos) /*!< SGPIO STATUS_1: STATUS_CCI6 Mask */
+#define SGPIO_STATUS_1_STATUS_CCI7_Pos 7 /*!< SGPIO STATUS_1: STATUS_CCI7 Position */
+#define SGPIO_STATUS_1_STATUS_CCI7_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI7_Pos) /*!< SGPIO STATUS_1: STATUS_CCI7 Mask */
+#define SGPIO_STATUS_1_STATUS_CCI8_Pos 8 /*!< SGPIO STATUS_1: STATUS_CCI8 Position */
+#define SGPIO_STATUS_1_STATUS_CCI8_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI8_Pos) /*!< SGPIO STATUS_1: STATUS_CCI8 Mask */
+#define SGPIO_STATUS_1_STATUS_CCI9_Pos 9 /*!< SGPIO STATUS_1: STATUS_CCI9 Position */
+#define SGPIO_STATUS_1_STATUS_CCI9_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI9_Pos) /*!< SGPIO STATUS_1: STATUS_CCI9 Mask */
+#define SGPIO_STATUS_1_STATUS_CCI10_Pos 10 /*!< SGPIO STATUS_1: STATUS_CCI10 Position */
+#define SGPIO_STATUS_1_STATUS_CCI10_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI10_Pos) /*!< SGPIO STATUS_1: STATUS_CCI10 Mask */
+#define SGPIO_STATUS_1_STATUS_CCI11_Pos 11 /*!< SGPIO STATUS_1: STATUS_CCI11 Position */
+#define SGPIO_STATUS_1_STATUS_CCI11_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI11_Pos) /*!< SGPIO STATUS_1: STATUS_CCI11 Mask */
+#define SGPIO_STATUS_1_STATUS_CCI12_Pos 12 /*!< SGPIO STATUS_1: STATUS_CCI12 Position */
+#define SGPIO_STATUS_1_STATUS_CCI12_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI12_Pos) /*!< SGPIO STATUS_1: STATUS_CCI12 Mask */
+#define SGPIO_STATUS_1_STATUS_CCI13_Pos 13 /*!< SGPIO STATUS_1: STATUS_CCI13 Position */
+#define SGPIO_STATUS_1_STATUS_CCI13_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI13_Pos) /*!< SGPIO STATUS_1: STATUS_CCI13 Mask */
+#define SGPIO_STATUS_1_STATUS_CCI14_Pos 14 /*!< SGPIO STATUS_1: STATUS_CCI14 Position */
+#define SGPIO_STATUS_1_STATUS_CCI14_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI14_Pos) /*!< SGPIO STATUS_1: STATUS_CCI14 Mask */
+#define SGPIO_STATUS_1_STATUS_CCI15_Pos 15 /*!< SGPIO STATUS_1: STATUS_CCI15 Position */
+#define SGPIO_STATUS_1_STATUS_CCI15_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI15_Pos) /*!< SGPIO STATUS_1: STATUS_CCI15 Mask */
+
+// ----------------------------------- SGPIO_CTR_STATUS_1 ---------------------------------------
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI0_Pos 0 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI0 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI0_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI0_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI0 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI1_Pos 1 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI1 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI1_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI1_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI1 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI2_Pos 2 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI2 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI2_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI2_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI2 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI3_Pos 3 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI3 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI3_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI3_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI3 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI4_Pos 4 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI4 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI4_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI4_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI4 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI5_Pos 5 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI5 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI5_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI5_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI5 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI6_Pos 6 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI6 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI6_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI6_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI6 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI7_Pos 7 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI7 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI7_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI7_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI7 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI8_Pos 8 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI8 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI8_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI8_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI8 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI9_Pos 9 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI9 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI9_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI9_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI9 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI10_Pos 10 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI10 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI10_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI10_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI10 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI11_Pos 11 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI11 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI11_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI11_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI11 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI12_Pos 12 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI12 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI12_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI12_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI12 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI13_Pos 13 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI13 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI13_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI13_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI13 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI14_Pos 14 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI14 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI14_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI14_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI14 Mask */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI15_Pos 15 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI15 Position */
+#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI15_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI15_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI15 Mask */
+
+// ----------------------------------- SGPIO_SET_STATUS_1 ---------------------------------------
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI0_Pos 0 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI0 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI0_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI0_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI0 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI1_Pos 1 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI1 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI1_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI1_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI1 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI2_Pos 2 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI2 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI2_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI2_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI2 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI3_Pos 3 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI3 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI3_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI3_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI3 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI4_Pos 4 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI4 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI4_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI4_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI4 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI5_Pos 5 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI5 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI5_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI5_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI5 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI6_Pos 6 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI6 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI6_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI6_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI6 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI7_Pos 7 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI7 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI7_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI7_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI7 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI8_Pos 8 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI8 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI8_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI8_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI8 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI9_Pos 9 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI9 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI9_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI9_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI9 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI10_Pos 10 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI10 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI10_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI10_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI10 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI11_Pos 11 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI11 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI11_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI11_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI11 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI12_Pos 12 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI12 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI12_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI12_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI12 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI13_Pos 13 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI13 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI13_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI13_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI13 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI14_Pos 14 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI14 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI14_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI14_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI14 Mask */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI15_Pos 15 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI15 Position */
+#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI15_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI15_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI15 Mask */
+
+// ------------------------------------- SGPIO_CLR_EN_2 -----------------------------------------
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI0_Pos 0 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI0 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI0_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI0_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI0 Mask */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI1_Pos 1 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI1 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI1_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI1_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI1 Mask */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI2_Pos 2 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI2 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI2_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI2_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI2 Mask */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI3_Pos 3 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI3 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI3_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI3_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI3 Mask */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI4_Pos 4 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI4 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI4_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI4_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI4 Mask */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI5_Pos 5 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI5 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI5_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI5_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI5 Mask */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI6_Pos 6 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI6 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI6_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI6_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI6 Mask */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI7_Pos 7 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI7 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI7_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI7_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI7 Mask */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI8_Pos 8 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI8 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI8_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI8_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI8 Mask */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI9_Pos 9 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI9 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI9_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI9_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI9 Mask */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI10_Pos 10 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI10 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI10_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI10_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI10 Mask */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI11_Pos 11 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI11 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI11_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI11_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI11 Mask */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI12_Pos 12 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI12 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI12_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI12_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI12 Mask */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI13_Pos 13 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI13 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI13_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI13_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI13 Mask */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI14_Pos 14 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI14 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI14_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI14_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI14 Mask */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI15_Pos 15 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI15 Position */
+#define SGPIO_CLR_EN_2_CLR_EN2_PMI15_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI15_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI15 Mask */
+
+// ------------------------------------- SGPIO_SET_EN_2 -----------------------------------------
+#define SGPIO_SET_EN_2_SET_EN_PMI0_Pos 0 /*!< SGPIO SET_EN_2: SET_EN_PMI0 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI0_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI0_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI0 Mask */
+#define SGPIO_SET_EN_2_SET_EN_PMI1_Pos 1 /*!< SGPIO SET_EN_2: SET_EN_PMI1 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI1_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI1_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI1 Mask */
+#define SGPIO_SET_EN_2_SET_EN_PMI2_Pos 2 /*!< SGPIO SET_EN_2: SET_EN_PMI2 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI2_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI2_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI2 Mask */
+#define SGPIO_SET_EN_2_SET_EN_PMI3_Pos 3 /*!< SGPIO SET_EN_2: SET_EN_PMI3 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI3_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI3_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI3 Mask */
+#define SGPIO_SET_EN_2_SET_EN_PMI4_Pos 4 /*!< SGPIO SET_EN_2: SET_EN_PMI4 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI4_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI4_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI4 Mask */
+#define SGPIO_SET_EN_2_SET_EN_PMI5_Pos 5 /*!< SGPIO SET_EN_2: SET_EN_PMI5 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI5_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI5_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI5 Mask */
+#define SGPIO_SET_EN_2_SET_EN_PMI6_Pos 6 /*!< SGPIO SET_EN_2: SET_EN_PMI6 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI6_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI6_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI6 Mask */
+#define SGPIO_SET_EN_2_SET_EN_PMI7_Pos 7 /*!< SGPIO SET_EN_2: SET_EN_PMI7 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI7_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI7_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI7 Mask */
+#define SGPIO_SET_EN_2_SET_EN_PMI8_Pos 8 /*!< SGPIO SET_EN_2: SET_EN_PMI8 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI8_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI8_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI8 Mask */
+#define SGPIO_SET_EN_2_SET_EN_PMI9_Pos 9 /*!< SGPIO SET_EN_2: SET_EN_PMI9 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI9_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI9_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI9 Mask */
+#define SGPIO_SET_EN_2_SET_EN_PMI10_Pos 10 /*!< SGPIO SET_EN_2: SET_EN_PMI10 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI10_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI10_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI10 Mask */
+#define SGPIO_SET_EN_2_SET_EN_PMI11_Pos 11 /*!< SGPIO SET_EN_2: SET_EN_PMI11 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI11_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI11_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI11 Mask */
+#define SGPIO_SET_EN_2_SET_EN_PMI12_Pos 12 /*!< SGPIO SET_EN_2: SET_EN_PMI12 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI12_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI12_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI12 Mask */
+#define SGPIO_SET_EN_2_SET_EN_PMI13_Pos 13 /*!< SGPIO SET_EN_2: SET_EN_PMI13 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI13_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI13_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI13 Mask */
+#define SGPIO_SET_EN_2_SET_EN_PMI14_Pos 14 /*!< SGPIO SET_EN_2: SET_EN_PMI14 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI14_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI14_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI14 Mask */
+#define SGPIO_SET_EN_2_SET_EN_PMI15_Pos 15 /*!< SGPIO SET_EN_2: SET_EN_PMI15 Position */
+#define SGPIO_SET_EN_2_SET_EN_PMI15_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI15_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI15 Mask */
+
+// ------------------------------------- SGPIO_ENABLE_2 -----------------------------------------
+#define SGPIO_ENABLE_2_ENABLE_PMI0_Pos 0 /*!< SGPIO ENABLE_2: ENABLE_PMI0 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI0_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI0_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI0 Mask */
+#define SGPIO_ENABLE_2_ENABLE_PMI1_Pos 1 /*!< SGPIO ENABLE_2: ENABLE_PMI1 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI1_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI1_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI1 Mask */
+#define SGPIO_ENABLE_2_ENABLE_PMI2_Pos 2 /*!< SGPIO ENABLE_2: ENABLE_PMI2 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI2_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI2_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI2 Mask */
+#define SGPIO_ENABLE_2_ENABLE_PMI3_Pos 3 /*!< SGPIO ENABLE_2: ENABLE_PMI3 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI3_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI3_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI3 Mask */
+#define SGPIO_ENABLE_2_ENABLE_PMI4_Pos 4 /*!< SGPIO ENABLE_2: ENABLE_PMI4 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI4_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI4_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI4 Mask */
+#define SGPIO_ENABLE_2_ENABLE_PMI5_Pos 5 /*!< SGPIO ENABLE_2: ENABLE_PMI5 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI5_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI5_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI5 Mask */
+#define SGPIO_ENABLE_2_ENABLE_PMI6_Pos 6 /*!< SGPIO ENABLE_2: ENABLE_PMI6 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI6_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI6_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI6 Mask */
+#define SGPIO_ENABLE_2_ENABLE_PMI7_Pos 7 /*!< SGPIO ENABLE_2: ENABLE_PMI7 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI7_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI7_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI7 Mask */
+#define SGPIO_ENABLE_2_ENABLE_PMI8_Pos 8 /*!< SGPIO ENABLE_2: ENABLE_PMI8 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI8_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI8_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI8 Mask */
+#define SGPIO_ENABLE_2_ENABLE_PMI9_Pos 9 /*!< SGPIO ENABLE_2: ENABLE_PMI9 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI9_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI9_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI9 Mask */
+#define SGPIO_ENABLE_2_ENABLE_PMI10_Pos 10 /*!< SGPIO ENABLE_2: ENABLE_PMI10 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI10_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI10_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI10 Mask */
+#define SGPIO_ENABLE_2_ENABLE_PMI11_Pos 11 /*!< SGPIO ENABLE_2: ENABLE_PMI11 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI11_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI11_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI11 Mask */
+#define SGPIO_ENABLE_2_ENABLE_PMI12_Pos 12 /*!< SGPIO ENABLE_2: ENABLE_PMI12 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI12_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI12_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI12 Mask */
+#define SGPIO_ENABLE_2_ENABLE_PMI13_Pos 13 /*!< SGPIO ENABLE_2: ENABLE_PMI13 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI13_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI13_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI13 Mask */
+#define SGPIO_ENABLE_2_ENABLE_PMI14_Pos 14 /*!< SGPIO ENABLE_2: ENABLE_PMI14 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI14_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI14_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI14 Mask */
+#define SGPIO_ENABLE_2_ENABLE_PMI15_Pos 15 /*!< SGPIO ENABLE_2: ENABLE_PMI15 Position */
+#define SGPIO_ENABLE_2_ENABLE_PMI15_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI15_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI15 Mask */
+
+// ------------------------------------- SGPIO_STATUS_2 -----------------------------------------
+#define SGPIO_STATUS_2_STATUS_PMI0_Pos 0 /*!< SGPIO STATUS_2: STATUS_PMI0 Position */
+#define SGPIO_STATUS_2_STATUS_PMI0_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI0_Pos) /*!< SGPIO STATUS_2: STATUS_PMI0 Mask */
+#define SGPIO_STATUS_2_STATUS_PMI1_Pos 1 /*!< SGPIO STATUS_2: STATUS_PMI1 Position */
+#define SGPIO_STATUS_2_STATUS_PMI1_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI1_Pos) /*!< SGPIO STATUS_2: STATUS_PMI1 Mask */
+#define SGPIO_STATUS_2_STATUS_PMI2_Pos 2 /*!< SGPIO STATUS_2: STATUS_PMI2 Position */
+#define SGPIO_STATUS_2_STATUS_PMI2_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI2_Pos) /*!< SGPIO STATUS_2: STATUS_PMI2 Mask */
+#define SGPIO_STATUS_2_STATUS_PMI3_Pos 3 /*!< SGPIO STATUS_2: STATUS_PMI3 Position */
+#define SGPIO_STATUS_2_STATUS_PMI3_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI3_Pos) /*!< SGPIO STATUS_2: STATUS_PMI3 Mask */
+#define SGPIO_STATUS_2_STATUS_PMI4_Pos 4 /*!< SGPIO STATUS_2: STATUS_PMI4 Position */
+#define SGPIO_STATUS_2_STATUS_PMI4_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI4_Pos) /*!< SGPIO STATUS_2: STATUS_PMI4 Mask */
+#define SGPIO_STATUS_2_STATUS_PMI5_Pos 5 /*!< SGPIO STATUS_2: STATUS_PMI5 Position */
+#define SGPIO_STATUS_2_STATUS_PMI5_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI5_Pos) /*!< SGPIO STATUS_2: STATUS_PMI5 Mask */
+#define SGPIO_STATUS_2_STATUS_PMI6_Pos 6 /*!< SGPIO STATUS_2: STATUS_PMI6 Position */
+#define SGPIO_STATUS_2_STATUS_PMI6_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI6_Pos) /*!< SGPIO STATUS_2: STATUS_PMI6 Mask */
+#define SGPIO_STATUS_2_STATUS_PMI7_Pos 7 /*!< SGPIO STATUS_2: STATUS_PMI7 Position */
+#define SGPIO_STATUS_2_STATUS_PMI7_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI7_Pos) /*!< SGPIO STATUS_2: STATUS_PMI7 Mask */
+#define SGPIO_STATUS_2_STATUS_PMI8_Pos 8 /*!< SGPIO STATUS_2: STATUS_PMI8 Position */
+#define SGPIO_STATUS_2_STATUS_PMI8_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI8_Pos) /*!< SGPIO STATUS_2: STATUS_PMI8 Mask */
+#define SGPIO_STATUS_2_STATUS_PMI9_Pos 9 /*!< SGPIO STATUS_2: STATUS_PMI9 Position */
+#define SGPIO_STATUS_2_STATUS_PMI9_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI9_Pos) /*!< SGPIO STATUS_2: STATUS_PMI9 Mask */
+#define SGPIO_STATUS_2_STATUS_PMI10_Pos 10 /*!< SGPIO STATUS_2: STATUS_PMI10 Position */
+#define SGPIO_STATUS_2_STATUS_PMI10_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI10_Pos) /*!< SGPIO STATUS_2: STATUS_PMI10 Mask */
+#define SGPIO_STATUS_2_STATUS_PMI11_Pos 11 /*!< SGPIO STATUS_2: STATUS_PMI11 Position */
+#define SGPIO_STATUS_2_STATUS_PMI11_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI11_Pos) /*!< SGPIO STATUS_2: STATUS_PMI11 Mask */
+#define SGPIO_STATUS_2_STATUS_PMI12_Pos 12 /*!< SGPIO STATUS_2: STATUS_PMI12 Position */
+#define SGPIO_STATUS_2_STATUS_PMI12_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI12_Pos) /*!< SGPIO STATUS_2: STATUS_PMI12 Mask */
+#define SGPIO_STATUS_2_STATUS_PMI13_Pos 13 /*!< SGPIO STATUS_2: STATUS_PMI13 Position */
+#define SGPIO_STATUS_2_STATUS_PMI13_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI13_Pos) /*!< SGPIO STATUS_2: STATUS_PMI13 Mask */
+#define SGPIO_STATUS_2_STATUS_PMI14_Pos 14 /*!< SGPIO STATUS_2: STATUS_PMI14 Position */
+#define SGPIO_STATUS_2_STATUS_PMI14_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI14_Pos) /*!< SGPIO STATUS_2: STATUS_PMI14 Mask */
+#define SGPIO_STATUS_2_STATUS_PMI15_Pos 15 /*!< SGPIO STATUS_2: STATUS_PMI15 Position */
+#define SGPIO_STATUS_2_STATUS_PMI15_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI15_Pos) /*!< SGPIO STATUS_2: STATUS_PMI15 Mask */
+
+// ----------------------------------- SGPIO_CTR_STATUS_2 ---------------------------------------
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI0_Pos 0 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI0 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI0_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI0_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI0 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI1_Pos 1 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI1 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI1_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI1_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI1 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI2_Pos 2 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI2 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI2_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI2_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI2 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI3_Pos 3 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI3 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI3_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI3_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI3 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI4_Pos 4 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI4 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI4_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI4_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI4 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI5_Pos 5 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI5 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI5_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI5_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI5 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI6_Pos 6 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI6 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI6_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI6_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI6 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI7_Pos 7 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI7 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI7_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI7_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI7 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI8_Pos 8 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI8 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI8_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI8_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI8 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI9_Pos 9 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI9 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI9_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI9_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI9 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI10_Pos 10 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI10 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI10_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI10_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI10 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI11_Pos 11 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI11 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI11_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI11_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI11 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI12_Pos 12 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI12 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI12_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI12_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI12 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI13_Pos 13 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI13 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI13_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI13_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI13 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI14_Pos 14 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI14 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI14_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI14_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI14 Mask */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI15_Pos 15 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI15 Position */
+#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI15_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI15_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI15 Mask */
+
+// ----------------------------------- SGPIO_SET_STATUS_2 ---------------------------------------
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI0_Pos 0 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI0 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI0_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI0_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI0 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI1_Pos 1 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI1 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI1_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI1_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI1 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI2_Pos 2 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI2 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI2_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI2_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI2 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI3_Pos 3 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI3 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI3_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI3_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI3 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI4_Pos 4 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI4 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI4_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI4_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI4 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI5_Pos 5 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI5 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI5_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI5_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI5 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI6_Pos 6 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI6 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI6_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI6_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI6 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI7_Pos 7 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI7 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI7_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI7_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI7 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI8_Pos 8 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI8 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI8_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI8_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI8 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI9_Pos 9 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI9 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI9_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI9_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI9 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI10_Pos 10 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI10 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI10_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI10_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI10 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI11_Pos 11 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI11 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI11_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI11_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI11 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI12_Pos 12 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI12 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI12_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI12_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI12 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI13_Pos 13 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI13 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI13_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI13_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI13 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI14_Pos 14 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI14 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI14_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI14_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI14 Mask */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI15_Pos 15 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI15 Position */
+#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI15_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI15_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI15 Mask */
+
+// ------------------------------------- SGPIO_CLR_EN_3 -----------------------------------------
+#define SGPIO_CLR_EN_3_CLR_EN_INPI0_Pos 0 /*!< SGPIO CLR_EN_3: CLR_EN_INPI0 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI0_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI0_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI0 Mask */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI1_Pos 1 /*!< SGPIO CLR_EN_3: CLR_EN_INPI1 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI1_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI1_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI1 Mask */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI2_Pos 2 /*!< SGPIO CLR_EN_3: CLR_EN_INPI2 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI2_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI2_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI2 Mask */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI3_Pos 3 /*!< SGPIO CLR_EN_3: CLR_EN_INPI3 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI3_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI3_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI3 Mask */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI4_Pos 4 /*!< SGPIO CLR_EN_3: CLR_EN_INPI4 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI4_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI4_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI4 Mask */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI5_Pos 5 /*!< SGPIO CLR_EN_3: CLR_EN_INPI5 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI5_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI5_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI5 Mask */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI6_Pos 6 /*!< SGPIO CLR_EN_3: CLR_EN_INPI6 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI6_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI6_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI6 Mask */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI7_Pos 7 /*!< SGPIO CLR_EN_3: CLR_EN_INPI7 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI7_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI7_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI7 Mask */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI8_Pos 8 /*!< SGPIO CLR_EN_3: CLR_EN_INPI8 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI8_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI8_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI8 Mask */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI9_Pos 9 /*!< SGPIO CLR_EN_3: CLR_EN_INPI9 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI9_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI9_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI9 Mask */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI10_Pos 10 /*!< SGPIO CLR_EN_3: CLR_EN_INPI10 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI10_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI10_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI10 Mask */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI11_Pos 11 /*!< SGPIO CLR_EN_3: CLR_EN_INPI11 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI11_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI11_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI11 Mask */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI12_Pos 12 /*!< SGPIO CLR_EN_3: CLR_EN_INPI12 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI12_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI12_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI12 Mask */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI13_Pos 13 /*!< SGPIO CLR_EN_3: CLR_EN_INPI13 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI13_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI13_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI13 Mask */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI14_Pos 14 /*!< SGPIO CLR_EN_3: CLR_EN_INPI14 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI14_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI14_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI14 Mask */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI15_Pos 15 /*!< SGPIO CLR_EN_3: CLR_EN_INPI15 Position */
+#define SGPIO_CLR_EN_3_CLR_EN_INPI15_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI15_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI15 Mask */
+
+// ------------------------------------- SGPIO_SET_EN_3 -----------------------------------------
+#define SGPIO_SET_EN_3_SET_EN_INPI0_Pos 0 /*!< SGPIO SET_EN_3: SET_EN_INPI0 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI0_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI0_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI0 Mask */
+#define SGPIO_SET_EN_3_SET_EN_INPI1_Pos 1 /*!< SGPIO SET_EN_3: SET_EN_INPI1 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI1_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI1_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI1 Mask */
+#define SGPIO_SET_EN_3_SET_EN_INPI2_Pos 2 /*!< SGPIO SET_EN_3: SET_EN_INPI2 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI2_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI2_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI2 Mask */
+#define SGPIO_SET_EN_3_SET_EN_INPI3_Pos 3 /*!< SGPIO SET_EN_3: SET_EN_INPI3 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI3_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI3_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI3 Mask */
+#define SGPIO_SET_EN_3_SET_EN_INPI4_Pos 4 /*!< SGPIO SET_EN_3: SET_EN_INPI4 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI4_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI4_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI4 Mask */
+#define SGPIO_SET_EN_3_SET_EN_INPI5_Pos 5 /*!< SGPIO SET_EN_3: SET_EN_INPI5 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI5_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI5_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI5 Mask */
+#define SGPIO_SET_EN_3_SET_EN_INPI6_Pos 6 /*!< SGPIO SET_EN_3: SET_EN_INPI6 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI6_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI6_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI6 Mask */
+#define SGPIO_SET_EN_3_SET_EN_INPI7_Pos 7 /*!< SGPIO SET_EN_3: SET_EN_INPI7 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI7_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI7_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI7 Mask */
+#define SGPIO_SET_EN_3_SET_EN_INPI8_Pos 8 /*!< SGPIO SET_EN_3: SET_EN_INPI8 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI8_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI8_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI8 Mask */
+#define SGPIO_SET_EN_3_SET_EN_INPI9_Pos 9 /*!< SGPIO SET_EN_3: SET_EN_INPI9 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI9_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI9_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI9 Mask */
+#define SGPIO_SET_EN_3_SET_EN_INPI10_Pos 10 /*!< SGPIO SET_EN_3: SET_EN_INPI10 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI10_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI10_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI10 Mask */
+#define SGPIO_SET_EN_3_SET_EN_INPI11_Pos 11 /*!< SGPIO SET_EN_3: SET_EN_INPI11 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI11_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI11_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI11 Mask */
+#define SGPIO_SET_EN_3_SET_EN_INPI12_Pos 12 /*!< SGPIO SET_EN_3: SET_EN_INPI12 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI12_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI12_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI12 Mask */
+#define SGPIO_SET_EN_3_SET_EN_INPI13_Pos 13 /*!< SGPIO SET_EN_3: SET_EN_INPI13 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI13_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI13_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI13 Mask */
+#define SGPIO_SET_EN_3_SET_EN_INPI14_Pos 14 /*!< SGPIO SET_EN_3: SET_EN_INPI14 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI14_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI14_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI14 Mask */
+#define SGPIO_SET_EN_3_SET_EN_INPI15_Pos 15 /*!< SGPIO SET_EN_3: SET_EN_INPI15 Position */
+#define SGPIO_SET_EN_3_SET_EN_INPI15_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI15_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI15 Mask */
+
+// ------------------------------------- SGPIO_ENABLE_3 -----------------------------------------
+#define SGPIO_ENABLE_3_ENABLE3_INPI0_Pos 0 /*!< SGPIO ENABLE_3: ENABLE3_INPI0 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI0_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI0_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI0 Mask */
+#define SGPIO_ENABLE_3_ENABLE3_INPI1_Pos 1 /*!< SGPIO ENABLE_3: ENABLE3_INPI1 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI1_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI1_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI1 Mask */
+#define SGPIO_ENABLE_3_ENABLE3_INPI2_Pos 2 /*!< SGPIO ENABLE_3: ENABLE3_INPI2 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI2_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI2_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI2 Mask */
+#define SGPIO_ENABLE_3_ENABLE3_INPI3_Pos 3 /*!< SGPIO ENABLE_3: ENABLE3_INPI3 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI3_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI3_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI3 Mask */
+#define SGPIO_ENABLE_3_ENABLE3_INPI4_Pos 4 /*!< SGPIO ENABLE_3: ENABLE3_INPI4 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI4_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI4_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI4 Mask */
+#define SGPIO_ENABLE_3_ENABLE3_INPI5_Pos 5 /*!< SGPIO ENABLE_3: ENABLE3_INPI5 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI5_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI5_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI5 Mask */
+#define SGPIO_ENABLE_3_ENABLE3_INPI6_Pos 6 /*!< SGPIO ENABLE_3: ENABLE3_INPI6 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI6_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI6_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI6 Mask */
+#define SGPIO_ENABLE_3_ENABLE3_INPI7_Pos 7 /*!< SGPIO ENABLE_3: ENABLE3_INPI7 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI7_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI7_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI7 Mask */
+#define SGPIO_ENABLE_3_ENABLE3_INPI8_Pos 8 /*!< SGPIO ENABLE_3: ENABLE3_INPI8 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI8_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI8_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI8 Mask */
+#define SGPIO_ENABLE_3_ENABLE3_INPI9_Pos 9 /*!< SGPIO ENABLE_3: ENABLE3_INPI9 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI9_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI9_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI9 Mask */
+#define SGPIO_ENABLE_3_ENABLE3_INPI10_Pos 10 /*!< SGPIO ENABLE_3: ENABLE3_INPI10 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI10_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI10_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI10 Mask */
+#define SGPIO_ENABLE_3_ENABLE3_INPI11_Pos 11 /*!< SGPIO ENABLE_3: ENABLE3_INPI11 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI11_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI11_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI11 Mask */
+#define SGPIO_ENABLE_3_ENABLE3_INPI12_Pos 12 /*!< SGPIO ENABLE_3: ENABLE3_INPI12 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI12_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI12_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI12 Mask */
+#define SGPIO_ENABLE_3_ENABLE3_INPI13_Pos 13 /*!< SGPIO ENABLE_3: ENABLE3_INPI13 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI13_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI13_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI13 Mask */
+#define SGPIO_ENABLE_3_ENABLE3_INPI14_Pos 14 /*!< SGPIO ENABLE_3: ENABLE3_INPI14 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI14_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI14_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI14 Mask */
+#define SGPIO_ENABLE_3_ENABLE3_INPI15_Pos 15 /*!< SGPIO ENABLE_3: ENABLE3_INPI15 Position */
+#define SGPIO_ENABLE_3_ENABLE3_INPI15_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI15_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI15 Mask */
+
+// ------------------------------------- SGPIO_STATUS_3 -----------------------------------------
+#define SGPIO_STATUS_3_STATUS_INPI0_Pos 0 /*!< SGPIO STATUS_3: STATUS_INPI0 Position */
+#define SGPIO_STATUS_3_STATUS_INPI0_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI0_Pos) /*!< SGPIO STATUS_3: STATUS_INPI0 Mask */
+#define SGPIO_STATUS_3_STATUS_INPI1_Pos 1 /*!< SGPIO STATUS_3: STATUS_INPI1 Position */
+#define SGPIO_STATUS_3_STATUS_INPI1_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI1_Pos) /*!< SGPIO STATUS_3: STATUS_INPI1 Mask */
+#define SGPIO_STATUS_3_STATUS_INPI2_Pos 2 /*!< SGPIO STATUS_3: STATUS_INPI2 Position */
+#define SGPIO_STATUS_3_STATUS_INPI2_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI2_Pos) /*!< SGPIO STATUS_3: STATUS_INPI2 Mask */
+#define SGPIO_STATUS_3_STATUS_INPI3_Pos 3 /*!< SGPIO STATUS_3: STATUS_INPI3 Position */
+#define SGPIO_STATUS_3_STATUS_INPI3_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI3_Pos) /*!< SGPIO STATUS_3: STATUS_INPI3 Mask */
+#define SGPIO_STATUS_3_STATUS_INPI4_Pos 4 /*!< SGPIO STATUS_3: STATUS_INPI4 Position */
+#define SGPIO_STATUS_3_STATUS_INPI4_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI4_Pos) /*!< SGPIO STATUS_3: STATUS_INPI4 Mask */
+#define SGPIO_STATUS_3_STATUS_INPI5_Pos 5 /*!< SGPIO STATUS_3: STATUS_INPI5 Position */
+#define SGPIO_STATUS_3_STATUS_INPI5_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI5_Pos) /*!< SGPIO STATUS_3: STATUS_INPI5 Mask */
+#define SGPIO_STATUS_3_STATUS_INPI6_Pos 6 /*!< SGPIO STATUS_3: STATUS_INPI6 Position */
+#define SGPIO_STATUS_3_STATUS_INPI6_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI6_Pos) /*!< SGPIO STATUS_3: STATUS_INPI6 Mask */
+#define SGPIO_STATUS_3_STATUS_INPI7_Pos 7 /*!< SGPIO STATUS_3: STATUS_INPI7 Position */
+#define SGPIO_STATUS_3_STATUS_INPI7_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI7_Pos) /*!< SGPIO STATUS_3: STATUS_INPI7 Mask */
+#define SGPIO_STATUS_3_STATUS_INPI8_Pos 8 /*!< SGPIO STATUS_3: STATUS_INPI8 Position */
+#define SGPIO_STATUS_3_STATUS_INPI8_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI8_Pos) /*!< SGPIO STATUS_3: STATUS_INPI8 Mask */
+#define SGPIO_STATUS_3_STATUS_INPI9_Pos 9 /*!< SGPIO STATUS_3: STATUS_INPI9 Position */
+#define SGPIO_STATUS_3_STATUS_INPI9_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI9_Pos) /*!< SGPIO STATUS_3: STATUS_INPI9 Mask */
+#define SGPIO_STATUS_3_STATUS_INPI10_Pos 10 /*!< SGPIO STATUS_3: STATUS_INPI10 Position */
+#define SGPIO_STATUS_3_STATUS_INPI10_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI10_Pos) /*!< SGPIO STATUS_3: STATUS_INPI10 Mask */
+#define SGPIO_STATUS_3_STATUS_INPI11_Pos 11 /*!< SGPIO STATUS_3: STATUS_INPI11 Position */
+#define SGPIO_STATUS_3_STATUS_INPI11_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI11_Pos) /*!< SGPIO STATUS_3: STATUS_INPI11 Mask */
+#define SGPIO_STATUS_3_STATUS_INPI12_Pos 12 /*!< SGPIO STATUS_3: STATUS_INPI12 Position */
+#define SGPIO_STATUS_3_STATUS_INPI12_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI12_Pos) /*!< SGPIO STATUS_3: STATUS_INPI12 Mask */
+#define SGPIO_STATUS_3_STATUS_INPI13_Pos 13 /*!< SGPIO STATUS_3: STATUS_INPI13 Position */
+#define SGPIO_STATUS_3_STATUS_INPI13_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI13_Pos) /*!< SGPIO STATUS_3: STATUS_INPI13 Mask */
+#define SGPIO_STATUS_3_STATUS_INPI14_Pos 14 /*!< SGPIO STATUS_3: STATUS_INPI14 Position */
+#define SGPIO_STATUS_3_STATUS_INPI14_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI14_Pos) /*!< SGPIO STATUS_3: STATUS_INPI14 Mask */
+#define SGPIO_STATUS_3_STATUS_INPI15_Pos 15 /*!< SGPIO STATUS_3: STATUS_INPI15 Position */
+#define SGPIO_STATUS_3_STATUS_INPI15_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI15_Pos) /*!< SGPIO STATUS_3: STATUS_INPI15 Mask */
+
+// ----------------------------------- SGPIO_CTR_STATUS_3 ---------------------------------------
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI0_Pos 0 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI0 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI0_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI0_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI0 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI1_Pos 1 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI1 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI1_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI1_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI1 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI2_Pos 2 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI2 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI2_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI2_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI2 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI3_Pos 3 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI3 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI3_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI3_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI3 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI4_Pos 4 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI4 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI4_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI4_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI4 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI5_Pos 5 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI5 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI5_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI5_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI5 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI6_Pos 6 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI6 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI6_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI6_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI6 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI7_Pos 7 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI7 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI7_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI7_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI7 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI8_Pos 8 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI8 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI8_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI8_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI8 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI9_Pos 9 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI9 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI9_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI9_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI9 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI10_Pos 10 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI10 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI10_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI10_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI10 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI11_Pos 11 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI11 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI11_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI11_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI11 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI12_Pos 12 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI12 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI12_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI12_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI12 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI13_Pos 13 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI13 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI13_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI13_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI13 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI14_Pos 14 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI14 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI14_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI14_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI14 Mask */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI15_Pos 15 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI15 Position */
+#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI15_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI15_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI15 Mask */
+
+// ----------------------------------- SGPIO_SET_STATUS_3 ---------------------------------------
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI0_Pos 0 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI0 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI0_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI0_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI0 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI1_Pos 1 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI1 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI1_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI1_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI1 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI2_Pos 2 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI2 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI2_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI2_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI2 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI3_Pos 3 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI3 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI3_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI3_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI3 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI4_Pos 4 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI4 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI4_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI4_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI4 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI5_Pos 5 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI5 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI5_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI5_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI5 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI6_Pos 6 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI6 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI6_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI6_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI6 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI7_Pos 7 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI7 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI7_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI7_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI7 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI8_Pos 8 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI8 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI8_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI8_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI8 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI9_Pos 9 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI9 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI9_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI9_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI9 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI10_Pos 10 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI10 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI10_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI10_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI10 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI11_Pos 11 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI11 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI11_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI11_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI11 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI12_Pos 12 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI12 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI12_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI12_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI12 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI13_Pos 13 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI13 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI13_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI13_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI13 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI14_Pos 14 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI14 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI14_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI14_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI14 Mask */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI15_Pos 15 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI15 Position */
+#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI15_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI15_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI15 Mask */
+
+#endif
+
+// ------------------------------------------------------------------------------------------------
+// ----- Peripheral memory map -----
+// ------------------------------------------------------------------------------------------------
+
+#define LPC_SCT_BASE 0x40000000
+#define LPC_GPDMA_BASE 0x40002000
+#define LPC_SDMMC_BASE 0x40004000
+#define LPC_EMC_BASE 0x40005000
+#define LPC_USB0_BASE 0x40006000
+#define LPC_USB1_BASE 0x40007000
+#define LPC_LCD_BASE 0x40008000
+#define LPC_ETHERNET_BASE 0x40010000
+#define LPC_ATIMER_BASE 0x40040000
+#define LPC_REGFILE_BASE 0x40041000
+#define LPC_PMC_BASE 0x40042000
+#define LPC_CREG_BASE 0x40043000
+#define LPC_EVENTROUTER_BASE 0x40044000
+#define LPC_RTC_BASE 0x40046000
+#define LPC_CGU_BASE 0x40050000
+#define LPC_CCU1_BASE 0x40051000
+#define LPC_CCU2_BASE 0x40052000
+#define LPC_RGU_BASE 0x40053000
+#define LPC_WWDT_BASE 0x40080000
+#define LPC_USART0_BASE 0x40081000
+#define LPC_USART2_BASE 0x400C1000
+#define LPC_USART3_BASE 0x400C2000
+#define LPC_UART1_BASE 0x40082000
+#define LPC_SSP0_BASE 0x40083000
+#define LPC_SSP1_BASE 0x400C5000
+#define LPC_TIMER0_BASE 0x40084000
+#define LPC_TIMER1_BASE 0x40085000
+#define LPC_TIMER2_BASE 0x400C3000
+#define LPC_TIMER3_BASE 0x400C4000
+#define LPC_SCU_BASE 0x40086000
+#define LPC_GPIO_PIN_INT_BASE 0x40087000
+#define LPC_GPIO_GROUP_INT0_BASE 0x40088000
+#define LPC_GPIO_GROUP_INT1_BASE 0x40089000
+#define LPC_MCPWM_BASE 0x400A0000
+#define LPC_I2C0_BASE 0x400A1000
+#define LPC_I2C1_BASE 0x400E0000
+#define LPC_I2S0_BASE 0x400A2000
+#define LPC_I2S1_BASE 0x400A3000
+#define LPC_C_CAN1_BASE 0x400A4000
+#define LPC_RITIMER_BASE 0x400C0000
+#define LPC_QEI_BASE 0x400C6000
+#define LPC_GIMA_BASE 0x400C7000
+#define LPC_DAC_BASE 0x400E1000
+#define LPC_C_CAN0_BASE 0x400E2000
+#define LPC_ADC0_BASE 0x400E3000
+#define LPC_ADC1_BASE 0x400E4000
+#define LPC_VADC_BASE 0x400F0000
+#define LPC_GPIO_PORT_BASE 0x400F4000
+#define LPC_SPI_BASE 0x40100000
+#define LPC_SGPIO_BASE 0x40101000
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- Peripheral declaration -----
+// ------------------------------------------------------------------------------------------------
+
+#define LPC_SCT ((LPC_SCT_Type *) LPC_SCT_BASE)
+#define LPC_GPDMA ((LPC_GPDMA_Type *) LPC_GPDMA_BASE)
+#define LPC_SDMMC ((LPC_SDMMC_Type *) LPC_SDMMC_BASE)
+#define LPC_EMC ((LPC_EMC_Type *) LPC_EMC_BASE)
+#define LPC_USB0 ((LPC_USB0_Type *) LPC_USB0_BASE)
+#define LPC_USB1 ((LPC_USB1_Type *) LPC_USB1_BASE)
+#define LPC_LCD ((LPC_LCD_Type *) LPC_LCD_BASE)
+#define LPC_ETHERNET ((LPC_ETHERNET_Type *) LPC_ETHERNET_BASE)
+#define LPC_ATIMER ((LPC_ATIMER_Type *) LPC_ATIMER_BASE)
+#define LPC_REGFILE ((LPC_REGFILE_Type *) LPC_REGFILE_BASE)
+#define LPC_PMC ((LPC_PMC_Type *) LPC_PMC_BASE)
+#define LPC_CREG ((LPC_CREG_Type *) LPC_CREG_BASE)
+#define LPC_EVENTROUTER ((LPC_EVENTROUTER_Type *) LPC_EVENTROUTER_BASE)
+#define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
+#define LPC_CGU ((LPC_CGU_Type *) LPC_CGU_BASE)
+#define LPC_CCU1 ((LPC_CCU1_Type *) LPC_CCU1_BASE)
+#define LPC_CCU2 ((LPC_CCU2_Type *) LPC_CCU2_BASE)
+#define LPC_RGU ((LPC_RGU_Type *) LPC_RGU_BASE)
+#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
+#define LPC_USART0 ((LPC_USARTn_Type *) LPC_USART0_BASE)
+#define LPC_USART2 ((LPC_USARTn_Type *) LPC_USART2_BASE)
+#define LPC_USART3 ((LPC_USARTn_Type *) LPC_USART3_BASE)
+#define LPC_UART1 ((LPC_UART1_Type *) LPC_UART1_BASE)
+#define LPC_SSP0 ((LPC_SSPn_Type *) LPC_SSP0_BASE)
+#define LPC_SSP1 ((LPC_SSPn_Type *) LPC_SSP1_BASE)
+#define LPC_TIMER0 ((LPC_TIMERn_Type *) LPC_TIMER0_BASE)
+#define LPC_TIMER1 ((LPC_TIMERn_Type *) LPC_TIMER1_BASE)
+#define LPC_TIMER2 ((LPC_TIMERn_Type *) LPC_TIMER2_BASE)
+#define LPC_TIMER3 ((LPC_TIMERn_Type *) LPC_TIMER3_BASE)
+#define LPC_SCU ((LPC_SCU_Type *) LPC_SCU_BASE)
+#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
+#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTn_Type*) LPC_GPIO_GROUP_INT0_BASE)
+#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTn_Type*) LPC_GPIO_GROUP_INT1_BASE)
+#define LPC_MCPWM ((LPC_MCPWM_Type *) LPC_MCPWM_BASE)
+#define LPC_I2C0 ((LPC_I2Cn_Type *) LPC_I2C0_BASE)
+#define LPC_I2C1 ((LPC_I2Cn_Type *) LPC_I2C1_BASE)
+#define LPC_I2S0 ((LPC_I2Sn_Type *) LPC_I2S0_BASE)
+#define LPC_I2S1 ((LPC_I2Sn_Type *) LPC_I2S1_BASE)
+#define LPC_C_CAN1 ((LPC_C_CANn_Type *) LPC_C_CAN1_BASE)
+#define LPC_RITIMER ((LPC_RITIMER_Type *) LPC_RITIMER_BASE)
+#define LPC_QEI ((LPC_QEI_Type *) LPC_QEI_BASE)
+#define LPC_GIMA ((LPC_GIMA_Type *) LPC_GIMA_BASE)
+#define LPC_DAC ((LPC_DAC_Type *) LPC_DAC_BASE)
+#define LPC_C_CAN0 ((LPC_C_CANn_Type *) LPC_C_CAN0_BASE)
+#define LPC_ADC0 ((LPC_ADCn_Type *) LPC_ADC0_BASE)
+#define LPC_ADC1 ((LPC_ADCn_Type *) LPC_ADC1_BASE)
+#define LPC_VADC ((LPC_VADC_Type *) LPC_VADC_BASE)
+#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
+#define LPC_SPI ((LPC_SPI_Type *) LPC_SPI_BASE)
+#define LPC_SGPIO ((LPC_SGPIO_Type *) LPC_SGPIO_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group LPC43xx */
+/** @} */ /* End of group (null) */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif // __LPC43xx_H__
+
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc4322/armcc/startup_LPC43xx.s --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/nxp/lpc4322/armcc/startup_LPC43xx.s Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,334 @@ +;/*********************************************************************** +; * $Id: startup_LPC18xx.s 6473 2011-02-16 17:40:54Z nxp27266 $ +; * +; * Project: LPC18xx CMSIS Package +; * +; * Description: Cortex-M3 Core Device Startup File for the NXP LPC18xx +; * Device Series. +; * +; * Copyright(C) 2011, NXP Semiconductor +; * All rights reserved. +; * +; *********************************************************************** +; * Software that is described herein is for illustrative purposes only +; * which provides customers with programming information regarding the +; * products. This software is supplied "AS IS" without any warranties. +; * NXP Semiconductors assumes no responsibility or liability for the +; * use of the software, conveys no license or title under any patent, +; * copyright, or mask work right to the product. NXP Semiconductors +; * reserves the right to make changes in the software without +; * notification. NXP Semiconductors also make no representation or +; * warranty that such application will be suitable for the specified +; * use without further testing or modification. +; **********************************************************************/ + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000100 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + IMPORT g_board_info +Sign_Value EQU 0x5A5A5A5A + +__Vectors DCD __initial_sp ; 0 Top of Stack + DCD Reset_Handler ; 1 Reset Handler + DCD NMI_Handler ; 2 NMI Handler + DCD HardFault_Handler ; 3 Hard Fault Handler + DCD MemManage_Handler ; 4 MPU Fault Handler + DCD BusFault_Handler ; 5 Bus Fault Handler + DCD UsageFault_Handler ; 6 Usage Fault Handler + DCD Sign_Value ; 7 Reserved + DCD DAPLINK_BUILD_KEY ; Build type - BL/IF + DCD DAPLINK_HIC_ID ; Compatibility + DCD DAPLINK_VERSION ; Version + DCD SVC_Handler ; 11 SVCall Handler + DCD DebugMon_Handler ; 12 Debug Monitor Handler + DCD g_board_info ; 13 Ptr to Board info, family info other target details + DCD PendSV_Handler ; 14 PendSV Handler + DCD SysTick_Handler ; 15 SysTick Handler + + ; External Interrupts + DCD DAC_IRQHandler ; 16 D/A Converter + DCD M0CORE_IRQHandler ; 17 M0 Core + DCD DMA_IRQHandler ; 18 General Purpose DMA + DCD EZH_IRQHandler ; 19 EZH/EDM + DCD FLASH_EEPROM_IRQHandler ; 20 Reserved for Typhoon + DCD ETH_IRQHandler ; 21 Ethernet + DCD SDIO_IRQHandler ; 22 SD/MMC + DCD LCD_IRQHandler ; 23 LCD + DCD USB0_IRQHandler ; 24 USB0 + DCD USB1_IRQHandler ; 25 USB1 + DCD SCT_IRQHandler ; 26 State Configurable Timer + DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer + DCD TIMER0_IRQHandler ; 28 Timer0 + DCD TIMER1_IRQHandler ; 29 Timer1 + DCD TIMER2_IRQHandler ; 30 Timer2 + DCD TIMER3_IRQHandler ; 31 Timer3 + DCD MCPWM_IRQHandler ; 32 Motor Control PWM + DCD ADC0_IRQHandler ; 33 A/D Converter 0 + DCD I2C0_IRQHandler ; 34 I2C0 + DCD I2C1_IRQHandler ; 35 I2C1 + DCD SPI_IRQHandler ; 36 SPI + DCD ADC1_IRQHandler ; 37 A/D Converter 1 + DCD SSP0_IRQHandler ; 38 SSP0 + DCD SSP1_IRQHandler ; 39 SSP1 + DCD UART0_IRQHandler ; 40 UART0 + DCD UART1_IRQHandler ; 41 UART1 + DCD UART2_IRQHandler ; 42 UART2 + DCD UART3_IRQHandler ; 43 UART3 + DCD I2S0_IRQHandler ; 44 I2S0 + DCD I2S1_IRQHandler ; 45 I2S1 + DCD SPIFI_IRQHandler ; 46 SPI Flash Interface + DCD SGPIO_IRQHandler ; 47 SGPIO + DCD GPIO0_IRQHandler ; 48 GPIO0 + DCD GPIO1_IRQHandler ; 49 GPIO1 + DCD GPIO2_IRQHandler ; 50 GPIO2 + DCD GPIO3_IRQHandler ; 51 GPIO3 + DCD GPIO4_IRQHandler ; 52 GPIO4 + DCD GPIO5_IRQHandler ; 53 GPIO5 + DCD GPIO6_IRQHandler ; 54 GPIO6 + DCD GPIO7_IRQHandler ; 55 GPIO7 + DCD GINT0_IRQHandler ; 56 GINT0 + DCD GINT1_IRQHandler ; 57 GINT1 + DCD EVRT_IRQHandler ; 58 Event Router + DCD CAN1_IRQHandler ; 59 C_CAN1 + DCD 0 ; 60 Reserved + DCD VADC_IRQHandler ; 61 VADC + DCD ATIMER_IRQHandler ; 62 ATIMER + DCD RTC_IRQHandler ; 63 RTC + DCD 0 ; 64 Reserved + DCD WDT_IRQHandler ; 65 WDT + DCD M0s_IRQHandler ; 66 M0s + DCD CAN0_IRQHandler ; 67 C_CAN0 + DCD QEI_IRQHandler ; 68 QEI + + + IF :LNOT::DEF:NO_CRP +#if defined(DAPLINK_BL) + AREA |.ARM.__at_0x1A0002FC|, CODE, READONLY +CRP_Key DCD 0xFFFFFFFF +#endif + ENDIF + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT DAC_IRQHandler [WEAK] + EXPORT M0CORE_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT EZH_IRQHandler [WEAK] + EXPORT FLASH_EEPROM_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT USB0_IRQHandler [WEAK] + EXPORT USB1_IRQHandler [WEAK] + EXPORT SCT_IRQHandler [WEAK] + EXPORT RIT_IRQHandler [WEAK] + EXPORT TIMER0_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT MCPWM_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT SSP0_IRQHandler [WEAK] + EXPORT SSP1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT I2S0_IRQHandler [WEAK] + EXPORT I2S1_IRQHandler [WEAK] + EXPORT SPIFI_IRQHandler [WEAK] + EXPORT SGPIO_IRQHandler [WEAK] + EXPORT GPIO0_IRQHandler [WEAK] + EXPORT GPIO1_IRQHandler [WEAK] + EXPORT GPIO2_IRQHandler [WEAK] + EXPORT GPIO3_IRQHandler [WEAK] + EXPORT GPIO4_IRQHandler [WEAK] + EXPORT GPIO5_IRQHandler [WEAK] + EXPORT GPIO6_IRQHandler [WEAK] + EXPORT GPIO7_IRQHandler [WEAK] + EXPORT GINT0_IRQHandler [WEAK] + EXPORT GINT1_IRQHandler [WEAK] + EXPORT EVRT_IRQHandler [WEAK] + EXPORT CAN1_IRQHandler [WEAK] +; EXPORT RESERVED3 [WEAK] + EXPORT VADC_IRQHandler [WEAK] + EXPORT ATIMER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] +; EXPORT RESERVED4 [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT M0s_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT QEI_IRQHandler [WEAK] + + +DAC_IRQHandler +M0CORE_IRQHandler +DMA_IRQHandler +EZH_IRQHandler +FLASH_EEPROM_IRQHandler +ETH_IRQHandler +SDIO_IRQHandler +LCD_IRQHandler +USB0_IRQHandler +USB1_IRQHandler +SCT_IRQHandler +RIT_IRQHandler +TIMER0_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +MCPWM_IRQHandler +ADC0_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI_IRQHandler +ADC1_IRQHandler +SSP0_IRQHandler +SSP1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +I2S0_IRQHandler +I2S1_IRQHandler +SPIFI_IRQHandler +SGPIO_IRQHandler +GPIO0_IRQHandler +GPIO1_IRQHandler +GPIO2_IRQHandler +GPIO3_IRQHandler +GPIO4_IRQHandler +GPIO5_IRQHandler +GPIO6_IRQHandler +GPIO7_IRQHandler +GINT0_IRQHandler +GINT1_IRQHandler +EVRT_IRQHandler +CAN1_IRQHandler +;RESERVED3 +VADC_IRQHandler +ATIMER_IRQHandler +RTC_IRQHandler +;RESERVED4 +WDT_IRQHandler +M0s_IRQHandler +CAN0_IRQHandler +QEI_IRQHandler + B . + + ENDP + + ALIGN + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc4322/board_LPC43xx.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc4322/board_LPC43xx.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,43 @@
+/**
+ * @file board_LPC43xx.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "sdk.h"
+#include "lpc43xx_cgu.h"
+
+void sdk_init(void)
+{
+ /* Set core clock to 96MHz */
+ CGU_Init(96000000);
+ /* Set up USB0 clock */
+ /* Disable PLL first */
+ CGU_EnableEntity(CGU_CLKSRC_PLL0, DISABLE);
+
+ /* the usb core require output clock = 480MHz */
+ if (CGU_SetPLL0() != CGU_ERROR_SUCCESS) {
+ while (1);
+ }
+
+ CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL0);
+ /* Enable PLL after all setting is done */
+ CGU_EnableEntity(CGU_CLKSRC_PLL0, ENABLE);
+ /* Turn on the USB0PHY */
+ LPC_CREG->CREG0 &= ~(1 << 5);
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc4322/daplink_addr.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/nxp/lpc4322/daplink_addr.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,81 @@ +/** + * @file daplink_addr.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef DAPLINK_ADDR_H +#define DAPLINK_ADDR_H + +/* Device sizes */ + +#define DAPLINK_ROM_START 0x1A000000 +#define DAPLINK_ROM_SIZE 0x00032000 + +#define DAPLINK_RAM_START 0x10000000 +#define DAPLINK_RAM_SIZE 0x00008000 + +/* ROM sizes */ + +#define DAPLINK_ROM_BL_START 0x1A000000 +#define DAPLINK_ROM_BL_SIZE 0x0000E000 + +#define DAPLINK_ROM_CONFIG_ADMIN_START 0x1A00E000 +#define DAPLINK_ROM_CONFIG_ADMIN_SIZE 0x00002000 + +#define DAPLINK_ROM_IF_START 0x1A010000 +#define DAPLINK_ROM_IF_SIZE 0x00020000 + +#define DAPLINK_ROM_CONFIG_USER_START 0x1A030000 +#define DAPLINK_ROM_CONFIG_USER_SIZE 0x00002000 + +/* RAM sizes */ + +#define DAPLINK_RAM_APP_START 0x10000000 +#define DAPLINK_RAM_APP_SIZE 0x00007F00 + +#define DAPLINK_RAM_SHARED_START 0x10007F00 +#define DAPLINK_RAM_SHARED_SIZE 0x00000100 + +/* Flash Programming Info */ +#define DAPLINK_SECTOR_SIZE 0x00002000 +#define DAPLINK_MIN_WRITE_SIZE 0x00000400 + +/* Current build */ + +#if defined(DAPLINK_BL) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_BL_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_IF_SIZE + +#elif defined(DAPLINK_IF) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_IF_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_BL_SIZE + +#else + +#error "Build must be either bootloader or interface" + +#endif + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc4322/flash.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc4322/flash.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,181 @@
+/**
+ * @file flash_hal_stub.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_hal.h"
+#include "system_LPC43xx.h"
+#include "daplink_addr.h"
+#include "cortex_m.h"
+
+#define END_SECTOR 14 /* 15 sectors per bank */
+#define FLASH_BANK_A 0
+#define FLASH_BANK_B 1
+
+/* IAP Structure */
+struct sIAP {
+ uint32_t cmd; // Command
+ uint32_t par[4]; // Parameters
+ uint32_t stat; // Status
+ uint32_t res[2]; // Result
+} IAP;
+
+/* IAP Call */
+typedef void (*IAP_Entry) (uint32_t *cmd, uint32_t *stat);
+#define IAP_Call ((IAP_Entry) (*(volatile unsigned int *)(0x10400100)))
+
+uint32_t GetSecNum (uint32_t adr) {
+ uint32_t n;
+ uint32_t flashadr = (adr & 0xFFFFFF);
+
+ if (flashadr < 0x10000) {
+ n = flashadr >> 13; // 8kB Sector
+ } else {
+ n = (flashadr >> 16) + 7; // 64kB Sector
+ }
+
+ return n; // Sector Number
+}
+
+
+uint32_t Init(uint32_t adr, uint32_t clk, uint32_t fnc)
+{
+ cortex_int_state_t local_state = cortex_int_get_and_disable();
+
+ IAP.cmd = 49; // Initialize
+ IAP.par[0] = 0;
+ IAP_Call(&IAP.cmd, &IAP.stat); // Call IAP Command
+
+ cortex_int_restore(local_state);
+
+ return 0;
+}
+
+uint32_t UnInit(uint32_t fnc)
+{
+ return 0;
+}
+
+uint32_t EraseChip(void)
+{
+ cortex_int_state_t local_state = cortex_int_get_and_disable();
+
+ IAP.cmd = 50; // Prepare Sector for Erase
+ IAP.par[0] = 0; // Start Sector
+ IAP.par[1] = END_SECTOR; // End Sector
+ IAP.par[2] = FLASH_BANK_A; // Flash Bank
+ IAP_Call(&IAP.cmd, &IAP.stat); // Call IAP Command
+ if (IAP.stat) {
+ cortex_int_restore(local_state);
+ return 1; // Command Failed
+ }
+
+ IAP.cmd = 52; // Erase Sector
+ IAP.par[0] = 0; // Start Sector
+ IAP.par[1] = END_SECTOR; // End Sector
+ IAP.par[2] = SystemCoreClock / 1000; // CCLK in kHz
+ IAP.par[3] = FLASH_BANK_A; // Flash Bank
+ IAP_Call(&IAP.cmd, &IAP.stat); // Call IAP Command
+ if (IAP.stat) {
+ cortex_int_restore(local_state);
+ return 1; // Command Failed
+ }
+
+ cortex_int_restore(local_state);
+
+ return 0;
+}
+
+uint32_t EraseSector(uint32_t adr)
+{
+ uint32_t n;
+
+ n = GetSecNum(adr); // Get Sector Number
+
+ cortex_int_state_t local_state = cortex_int_get_and_disable();
+
+ IAP.cmd = 50; // Prepare Sector for Erase
+ IAP.par[0] = n; // Start Sector
+ IAP.par[1] = n; // End Sector
+ IAP.par[2] = FLASH_BANK_A; // Flash Bank
+ IAP_Call(&IAP.cmd, &IAP.stat); // Call IAP Command
+ if (IAP.stat) {
+ cortex_int_restore(local_state);
+ return 1; // Command Failed
+ }
+
+ IAP.cmd = 52; // Erase Sector
+ IAP.par[0] = n; // Start Sector
+ IAP.par[1] = n; // End Sector
+ IAP.par[2] = SystemCoreClock / 1000; // CCLK in kHz
+ IAP.par[3] = FLASH_BANK_A; // Flash Bank
+ IAP_Call(&IAP.cmd, &IAP.stat); // Call IAP Command
+ if (IAP.stat) {
+ cortex_int_restore(local_state);
+ return 1; // Command Failed
+ }
+
+ cortex_int_restore(local_state);
+
+ return 0;
+}
+
+uint32_t ProgramPage(uint32_t adr, uint32_t sz, uint32_t *buf)
+{
+ uint32_t n;
+
+ if (adr == DAPLINK_ROM_START) { // Check for Vector Table
+ n = *((unsigned long *)(buf + 0)) +
+ *((unsigned long *)(buf + 1)) +
+ *((unsigned long *)(buf + 2)) +
+ *((unsigned long *)(buf + 3)) +
+ *((unsigned long *)(buf + 4)) +
+ *((unsigned long *)(buf + 5)) +
+ *((unsigned long *)(buf + 6));
+ *((unsigned long *)(buf + 7)) = 0 - n; // Signature at Reserved Vector
+ }
+ n = GetSecNum(adr); // Get Sector Number
+
+ cortex_int_state_t local_state = cortex_int_get_and_disable();
+
+ IAP.cmd = 50; // Prepare Sector for Write
+ IAP.par[0] = n; // Start Sector
+ IAP.par[1] = n; // End Sector
+ IAP.par[2] = FLASH_BANK_A; // Flash Bank
+ IAP_Call(&IAP.cmd, &IAP.stat); // Call IAP Command
+ if (IAP.stat) {
+ cortex_int_restore(local_state);
+ return 1; // Command Failed
+ }
+
+ IAP.cmd = 51; // Copy RAM to Flash
+ IAP.par[0] = adr; // Destination Flash Address
+ IAP.par[1] = (unsigned long)buf; // Source RAM Address
+ IAP.par[2] = 0x400; // Fixed Page Size
+ IAP.par[3] = SystemCoreClock / 1000; // CCLK in kHz
+ IAP_Call(&IAP.cmd, &IAP.stat); // Call IAP Command
+ if (IAP.stat) {
+ cortex_int_restore(local_state);
+ return 1; // Command Failed
+ }
+
+ cortex_int_restore(local_state);
+
+ return 0;
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc4322/fpu_enable.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc4322/fpu_enable.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,65 @@
+/***********************************************************************
+ * $Id: fpu_enable.c
+ *
+ * Project: LPC43xx
+ *
+ * Description: fpu initialization routine
+ *
+ * Copyright(C) 2011, NXP Semiconductor
+ * All rights reserved.
+ *
+ ***********************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **********************************************************************/
+
+#define LPC_CPACR 0xE000ED88
+
+#define SCB_MVFR0 0xE000EF40
+#define SCB_MVFR0_RESET 0x10110021
+
+#define SCB_MVFR1 0xE000EF44
+#define SCB_MVFR1_RESET 0x11000011
+
+#include "stdint.h"
+
+void fpuEnable(void)
+{
+ /* from arm trm manual, howto enable the FPU :
+ ; CPACR is located at address 0xE000ED88
+ LDR.W R0, =0xE000ED88
+ ; Read CPACR
+ LDR R1, [R0]
+ ; Set bits 20-23 to enable CP10 and CP11 coprocessors
+ ORR R1, R1, #(0xF << 20)
+ ; Write back the modified value to the CPACR
+ STR R1, [R0]
+ */
+ volatile uint32_t *regCpacr = (uint32_t *) LPC_CPACR;
+ volatile uint32_t *regMvfr0 = (uint32_t *) SCB_MVFR0;
+ volatile uint32_t *regMvfr1 = (uint32_t *) SCB_MVFR1;
+ volatile uint32_t Cpacr;
+ volatile uint32_t Mvfr0;
+ volatile uint32_t Mvfr1;
+ char vfpPresent = 0;
+ Mvfr0 = *regMvfr0;
+ Mvfr1 = *regMvfr1;
+ vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
+
+ /* enable the FPU if present on target */
+ if (vfpPresent) {
+ Cpacr = *regCpacr;
+ Cpacr |= (0xF << 20);
+ *regCpacr = Cpacr; // enable CP10 and CP11 for full access
+ }
+}
+
+
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc4322/fpu_enable.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc4322/fpu_enable.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,33 @@
+/***********************************************************************
+ * $Id: fpu_enable.h
+ *
+ * Project: LPC43xx
+ *
+ * Description: fpu initialization routine header
+ *
+ * Copyright(C) 2011, NXP Semiconductor
+ * All rights reserved.
+ *
+ ***********************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **********************************************************************/
+
+#ifndef __FPU_ENABLE_H
+#define __FPU_ENABLE_H
+
+#if defined(__ARMCC_VERSION)
+void fpuEnable(void) __attribute__((section("BOOTSTRAP_CODE")));
+#else
+extern void fpuEnable(void);
+#endif
+
+#endif /* __FPU_ENABLE_H */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc4322/gpio.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc4322/gpio.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,128 @@
+/**
+ * @file gpio.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "LPC43xx.h"
+#include "lpc43xx_scu.h"
+#include "gpio.h"
+#include "compiler.h"
+#include "DAP_config.h" // For the nRESET and RESET_TXE port/pin info
+#include "IO_Config.h"
+
+BOOL gpio_reset_pin_is_input = __TRUE;
+
+// Connected LED P1_1: GPIO0[8]
+#define LED_CONNECTED_PORT 0
+#define LED_CONNECTED_BIT 8
+
+// LPC43xx peripheral register bit masks (used by macros)
+#define CCU_CLK_CFG_RUN (1UL << 0)
+#define CCU_CLK_CFG_AUTO (1UL << 1)
+#define CCU_CLK_STAT_RUN (1UL << 0)
+
+static void busy_wait(uint32_t cycles)
+{
+ volatile uint32_t i;
+ i = cycles;
+
+ while (i > 0) {
+ i--;
+ }
+}
+
+void gpio_init(void)
+{
+ /* Enable clock and init GPIO outputs */
+ LPC_CCU1->CLK_M4_GPIO_CFG = CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN;
+
+ while (!(LPC_CCU1->CLK_M4_GPIO_STAT & CCU_CLK_STAT_RUN));
+
+ /* Configure I/O pins: function number, input buffer enabled, */
+ /* no pull-up/down */
+ scu_pinmux(1, 1, GPIO_NOPULL, FUNC0); /* LED: GPIO0[8] */
+ scu_pinmux(2, 11, GPIO_NOPULL, FUNC0); /* ISPCTRL: GPIO1[11] */
+ scu_pinmux(2, 5, GPIO_PUP, FUNC4); /* nRESET: GPIO5[5] */
+ scu_pinmux(2, 6, GPIO_NOPULL, FUNC4); /* nRESET_OE: GPIO5[6] */
+ /* Configure: LED as output (turned off) */
+ LPC_GPIO_PORT->CLR[LED_CONNECTED_PORT] = (1 << LED_CONNECTED_BIT);
+ LPC_GPIO_PORT->DIR[LED_CONNECTED_PORT] |= (1 << LED_CONNECTED_BIT);
+ /* Configure: ISPCTRL as output and high */
+ LPC_GPIO_PORT->SET[ISPCTRL_PORT] = (1 << ISPCTRL_BIT);
+ LPC_GPIO_PORT->DIR[ISPCTRL_PORT] |= (1 << ISPCTRL_BIT);
+ /* configure Reset Button as input, Reset Output Enable as output LOW */
+ LPC_GPIO_PORT->DIR[PORT_nRESET] &= ~(1 << PIN_nRESET_IN_BIT);
+ LPC_GPIO_PORT->CLR[PORT_RESET_TXE] = (1 << PIN_RESET_TXE_IN_BIT);
+ LPC_GPIO_PORT->DIR[PORT_RESET_TXE] |= (1 << PIN_RESET_TXE_IN_BIT);
+ /* Use Pin Interrupt 0 */
+ LPC_SCU->PINTSEL0 &= ~0xff;
+ LPC_SCU->PINTSEL0 |= (PORT_nRESET << 5) | (PIN_nRESET_IN_BIT);
+
+ busy_wait(10000);
+}
+
+void gpio_set_hid_led(gpio_led_state_t state)
+{
+ if (state) {
+ LPC_GPIO_PORT->SET[LED_CONNECTED_PORT] = (1 << LED_CONNECTED_BIT);
+ } else {
+ LPC_GPIO_PORT->CLR[LED_CONNECTED_PORT] = (1 << LED_CONNECTED_BIT);
+ }
+}
+
+void gpio_set_cdc_led(gpio_led_state_t state)
+{
+ if (state) {
+ LPC_GPIO_PORT->SET[LED_CONNECTED_PORT] = (1 << LED_CONNECTED_BIT);
+ } else {
+ LPC_GPIO_PORT->CLR[LED_CONNECTED_PORT] = (1 << LED_CONNECTED_BIT);
+ }
+}
+
+void gpio_set_msc_led(gpio_led_state_t state)
+{
+ if (state) {
+ LPC_GPIO_PORT->SET[LED_CONNECTED_PORT] = (1 << LED_CONNECTED_BIT);
+ } else {
+ LPC_GPIO_PORT->CLR[LED_CONNECTED_PORT] = (1 << LED_CONNECTED_BIT);
+ }
+}
+
+void gpio_set_isp_pin(uint8_t state)
+{
+ if (state) {
+ LPC_GPIO_PORT->SET[ISPCTRL_PORT] = (1 << ISPCTRL_BIT);
+ } else {
+ LPC_GPIO_PORT->CLR[ISPCTRL_PORT] = (1 << ISPCTRL_BIT);
+ }
+}
+
+uint8_t gpio_get_reset_btn_no_fwrd(void)
+{
+ return LPC_GPIO_PORT->W[PORT_nRESET * 32 + PIN_nRESET_IN_BIT] ? 0 : 1;
+}
+
+uint8_t gpio_get_reset_btn_fwrd(void)
+{
+ return 0;
+}
+
+void gpio_set_board_power(bool powerEnabled)
+{
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc4322/lpc43xx_cgu.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc4322/lpc43xx_cgu.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1132 @@
+/**
+ * @file lpc43xx_cgu.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "lpc_types.h"
+#include "lpc43xx_scu.h"
+#include "lpc43xx_cgu.h"
+
+/** This define used to fix mistake when run with IAR compiler */
+#ifdef __ICCARM__
+#define CGU_BRANCH_STATUS_ENABLE_MASK 0x80000001
+#else
+#define CGU_BRANCH_STATUS_ENABLE_MASK 0x01
+#endif
+
+/*TODO List:
+ * SET PLL0
+ * UPDATE Clock from PLL0
+ * SetDIV uncheck value
+ * GetBaseStatus BASE_SAFE
+ * */
+/* Local definition */
+#define CGU_ADDRESS32(x,y) (*(uint32_t*)((uint32_t)x+y))
+
+/* Local Variable */
+const int16_t CGU_Entity_ControlReg_Offset[CGU_ENTITY_NUM] = {
+ -1, //CGU_CLKSRC_32KHZ_OSC,
+ -1, //CGU_CLKSRC_IRC,
+ -1, //CGU_CLKSRC_ENET_RX_CLK,
+ -1, //CGU_CLKSRC_ENET_TX_CLK,
+ -1, //CGU_CLKSRC_GP_CLKIN,
+ -1, //CGU_CLKSRC_TCK,
+ 0x18, //CGU_CLKSRC_XTAL_OSC,
+ 0x20, //CGU_CLKSRC_PLL0,
+ 0x30, //CGU_CLKSRC_PLL0_AUDIO **REV A**
+ 0x44, //CGU_CLKSRC_PLL1,
+ -1, //CGU_CLKSRC_RESERVE,
+ -1, //CGU_CLKSRC_RESERVE,
+ 0x48, //CGU_CLKSRC_IDIVA,,
+ 0x4C, //CGU_CLKSRC_IDIVB,
+ 0x50, //CGU_CLKSRC_IDIVC,
+ 0x54, //CGU_CLKSRC_IDIVD,
+ 0x58, //CGU_CLKSRC_IDIVE,
+
+ 0x5C, //CGU_BASE_SAFE,
+ 0x60, //CGU_BASE_USB0,
+ 0x64, //CGU_BASE_PERIPH, // used for SPGPIO, peripheral control
+ 0x68, //CGU_BASE_USB1,
+ 0x6C, //CGU_BASE_M4,
+ 0x70, //CGU_BASE_SPIFI,
+ -1, //CGU_BASE_RESERVE,
+ 0x78, //CGU_BASE_PHY_RX,
+ 0x7C, //CGU_BASE_PHY_TX,
+ 0x80, //CGU_BASE_APB1,
+ 0x84, //CGU_BASE_APB3,
+ 0x88, //CGU_BASE_LCD,
+ 0X8C, //CGU_BASE_ENET_CSR, **REV A**
+ 0x90, //CGU_BASE_SDIO,
+ 0x94, //CGU_BASE_SSP0,
+ 0x98, //CGU_BASE_SSP1,
+ 0x9C, //CGU_BASE_UART0,
+ 0xA0, //CGU_BASE_UART1,
+ 0xA4, //CGU_BASE_UART2,
+ 0xA8, //CGU_BASE_UART3,
+ 0xAC, //CGU_BASE_CLKOUT
+ -1,
+ -1,
+ -1,
+ -1,
+ 0xC0, //CGU_BASE_APLL
+ 0xC4, //CGU_BASE_OUT0
+ 0xC8 //CGU_BASE_OUT1
+};
+
+const uint8_t CGU_ConnectAlloc_Tbl[CGU_CLKSRC_NUM][CGU_ENTITY_NUM] = {
+// 3 I E E G T X P P P x x D D D D D S U P U M S x P P A A L E S S S U U U U C x x x x A O O
+// 2 R R T P C T L L L I I I I I A S E S 3 P H H P P C N D S S R R R R O P U U
+// C X X I K A 0 A 1 A B C D E F B R B F RxTx1 3 D T I 0 1 0 1 2 3 L T T
+ {0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1}, /*CGU_CLKSRC_32KHZ_OSC = 0,*/
+ {0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1}, /*CGU_CLKSRC_IRC,*/
+ {0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1}, /*CGU_CLKSRC_ENET_RX_CLK,*/
+ {0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1}, /*CGU_CLKSRC_ENET_TX_CLK,*/
+ {0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1}, /*CGU_CLKSRC_GP_CLKIN,*/
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0}, /*CGU_CLKSRC_TCK,*/
+ {0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1}, /*CGU_CLKSRC_XTAL_OSC,*/
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1}, /*CGU_CLKSRC_PLL0,*/
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1}, /*CGU_CLKSRC_PLL0_AUDIO,*/
+ {0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1}, /*CGU_CLKSRC_PLL1,*/
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1}, /*CGU_CLKSRC_IDIVA = CGU_CLKSRC_PLL1 + 3,*/
+ {0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1}, /*CGU_CLKSRC_IDIVB,*/
+ {0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1}, /*CGU_CLKSRC_IDIVC,*/
+ {0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1}, /*CGU_CLKSRC_IDIVD,*/
+ {0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1} /*CGU_CLKSRC_IDIVE,*/
+};
+
+const CGU_PERIPHERAL_S CGU_PERIPHERAL_Info[CGU_PERIPHERAL_NUM] = {
+ /* Register Clock | Peripheral Clock
+ | BASE | BRANCH | BASE | BRANCH */
+ {CGU_BASE_APB3, 0x1118, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_ADC0,
+ {CGU_BASE_APB3, 0x1120, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_ADC1,
+ {CGU_BASE_M4, 0x1460, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_AES,
+ //// CGU_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,
+ {CGU_BASE_APB1, 0x1200, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_APB1_BUS,
+ {CGU_BASE_APB3, 0x1100, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_APB3_BUS,
+ {CGU_BASE_APB3, 0x1128, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_CAN0,
+ {CGU_BASE_M4, 0x1538, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_CREG,
+ {CGU_BASE_APB3, 0x1110, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_DAC,
+ {CGU_BASE_M4, 0x1440, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_DMA,
+ {CGU_BASE_M4, 0x1430, CGU_BASE_M4, 0x1478, 0},//CGU_PERIPHERAL_EMC,
+ {CGU_BASE_M4, 0x1420, CGU_BASE_PHY_RX, 0x0000, CGU_PERIPHERAL_ETHERNET_TX},//CGU_PERIPHERAL_ETHERNET,
+ {CGU_ENTITY_NONE, 0x0000, CGU_BASE_PHY_TX, 0x0000, 0}, //CGU_PERIPHERAL_ETHERNET_TX
+ {CGU_BASE_M4, 0x1410, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_GPIO,
+ {CGU_BASE_APB1, 0x1210, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_I2C0,
+ {CGU_BASE_APB3, 0x1108, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_I2C1,
+ {CGU_BASE_APB1, 0x1218, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_I2S,
+ {CGU_BASE_M4, 0x1418, CGU_BASE_LCD, 0x0000, 0},//CGU_PERIPHERAL_LCD,
+ {CGU_BASE_M4, 0x1448, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_M3CORE,
+ {CGU_BASE_M4, 0x1400, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_M3_BUS,
+ {CGU_BASE_APB1, 0x1208, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_MOTOCON,
+ {CGU_BASE_M4, 0x1630, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_QEI,
+ {CGU_BASE_M4, 0x1600, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_RITIMER,
+ {CGU_BASE_M4, 0x1468, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_SCT,
+ {CGU_BASE_M4, 0x1530, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_SCU,
+ {CGU_BASE_M4, 0x1438, CGU_BASE_SDIO, 0x2800, 0},//CGU_PERIPHERAL_SDIO,
+ {CGU_BASE_M4, 0x1408, CGU_BASE_SPIFI, 0x1300, 0},//CGU_PERIPHERAL_SPIFI,
+ {CGU_BASE_M4, 0x1518, CGU_BASE_SSP0, 0x2700, 0},//CGU_PERIPHERAL_SSP0,
+ {CGU_BASE_M4, 0x1628, CGU_BASE_SSP1, 0x2600, 0},//CGU_PERIPHERAL_SSP1,
+ {CGU_BASE_M4, 0x1520, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER0,
+ {CGU_BASE_M4, 0x1528, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER1,
+ {CGU_BASE_M4, 0x1618, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER2,
+ {CGU_BASE_M4, 0x1620, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER3,
+ {CGU_BASE_M4, 0x1508, CGU_BASE_UART0, 0x2500, 0},//CGU_PERIPHERAL_UART0,
+ {CGU_BASE_M4, 0x1510, CGU_BASE_UART1, 0x2400, 0},//CGU_PERIPHERAL_UART1,
+ {CGU_BASE_M4, 0x1608, CGU_BASE_UART2, 0x2300, 0},//CGU_PERIPHERAL_UART2,
+ {CGU_BASE_M4, 0x1610, CGU_BASE_UART3, 0x2200, 0},//CGU_PERIPHERAL_UART3,
+ {CGU_BASE_M4, 0x1428, CGU_BASE_USB0, 0x1800, 0},//CGU_PERIPHERAL_USB0,
+ {CGU_BASE_M4, 0x1470, CGU_BASE_USB1, 0x1900, 0},//CGU_PERIPHERAL_USB1,
+ {CGU_BASE_M4, 0x1500, CGU_BASE_SAFE, 0x0000, 0},//CGU_PERIPHERAL_WWDT,
+};
+
+uint32_t CGU_ClockSourceFrequency[CGU_CLKSRC_NUM] = {0, 12000000, 0, 0, 0, 0, 0, 480000000, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+#define CGU_CGU_ADDR ((uint32_t)LPC_CGU)
+#define CGU_REG_BASE_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_Entity_ControlReg_Offset[CGU_PERIPHERAL_Info[x].RegBaseEntity]))
+#define CGU_REG_BRANCH_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].RegBranchOffset))
+#define CGU_REG_BRANCH_STATUS(x) (*(volatile uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].RegBranchOffset+4))
+
+#define CGU_PER_BASE_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_Entity_ControlReg_Offset[CGU_PERIPHERAL_Info[x].PerBaseEntity]))
+#define CGU_PER_BRANCH_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].PerBranchOffset))
+#define CGU_PER_BRANCH_STATUS(x) (*(volatile uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].PerBranchOffset+4))
+
+/**************************************************************************//**
+ *
+ * @brief Rough approximation of a delay function with microsecond resolution.
+ *
+ * Used during initial clock setup as the Timers are not configured yet.
+ *
+ * @param [in] us The number of microseconds to wait
+ *
+ *****************************************************************************/
+static void cgu_WaitUS(volatile uint32_t us)
+{
+ us *= (SystemCoreClock / 1000000) / 3;
+
+ while (us--);
+}
+
+/**************************************************************************//**
+ *
+ * @brief Simple lookup of best MSEL and NSEL values for wanted frequency
+ *
+ * Not optimized.
+ *
+ * @param [in] wantedFreq The wanted PLL1 frequency
+ * @param [out] pMsel The best MSEL value for the PLL1_CTRL register
+ * @param [out] pNsel The best NSEL value for the PLL1_CTRL register
+ *
+ *****************************************************************************/
+static void cgu_findMN(uint32_t wantedFreq, uint32_t *pMsel, uint32_t *pNsel)
+{
+ uint32_t besterr = wantedFreq;
+ uint32_t m, n, f, tmp, err;
+#define ABSDIFF(__a, __b) ( ((__a) < (__b)) ? ((__b) - (__a)) : ((__a) - (__b)) )
+
+ for (n = 1; n <= 4; n++) {
+ f = 12000000 / n;
+ tmp = 0;
+
+ for (m = 1; m <= 256; m++) {
+ tmp += f;
+ err = ABSDIFF(tmp, wantedFreq);
+
+ if (err == 0) {
+ // found perfect match
+ *pMsel = m - 1;
+ *pNsel = n - 1;
+ return;
+
+ } else if (err < besterr) {
+ *pMsel = m - 1;
+ *pNsel = n - 1;
+ besterr = err;
+ }
+
+ if (tmp > wantedFreq) {
+ // no point in continuing to increase tmp as value is too high already
+ break;
+ }
+ }
+ }
+}
+
+/*********************************************************************//**
+ * @brief Initialize default clock for LPC4300 Eval board
+ * @param[in] None
+ * @return Initialize status, could be:
+ * - CGU_ERROR_SUCCESS: successful
+ * - Other: error
+ **********************************************************************/
+uint32_t CGU_Init(uint32_t wantedFreq)
+{
+ uint32_t msel = 0;
+ uint32_t nsel = 0;
+ uint32_t tmp;
+ // Setup PLL1 to 204MHz
+ // 0. Select IRC as BASE_M4_CLK source
+ CGU_EntityConnect(CGU_CLKSRC_IRC, CGU_BASE_M4);
+ SystemCoreClock = 96000000;
+ // 1. Enable the crystal oscillator
+ CGU_SetXTALOSC(12000000);
+ CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);
+ // 2. Wait 250us
+ cgu_WaitUS(250);
+ // 3. Reconfigure PLL1 as follows:
+ // - Select the M and N divider values to produce the final desired
+ // PLL1 output frequency (204MHz => M=17,N=1 => msel=16,nsel=0)
+ // - Select the crystal oscillator as clock source for PLL1
+ cgu_findMN(wantedFreq, &msel, &nsel);
+ tmp = LPC_CGU->PLL1_CTRL & ~((0xFF << 16) | (0x03 << 12));
+ LPC_CGU->PLL1_CTRL = tmp | (msel << 16) | (nsel << 12);
+ CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1);
+
+ // 4. Wait for the PLL1 to lock
+ while ((LPC_CGU->PLL1_STAT & 1) == 0x0);
+
+ // 5. Set PLL1 P-divider to divide by 2 (DIRECT=0 and PSEL=0)
+ LPC_CGU->PLL1_CTRL &= ~((0x03 << 8) | CGU_PLL1_DIRECT_MASK);
+ // 6. Select PLL1 as BASE_M4_CLK source. The BASE_M4_CLK now operates at
+ // the mid frequency range
+ CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M4);
+ SystemCoreClock = (12000000 * (msel + 1)) / ((nsel + 1) * 2);
+ // 7. Wait 20us
+ cgu_WaitUS(20);
+ // 8. Set PLL P-divider to direct output mode (DIRECT=1)
+ LPC_CGU->PLL1_CTRL |= CGU_PLL1_DIRECT_MASK;
+ // The BASE_M4_CLK now operates in the high frequency range
+ CGU_UpdateClock();
+ SystemCoreClock = (12000000 * (msel + 1)) / (nsel + 1);
+ return 0;
+}
+
+/*********************************************************************//**
+ * @brief Configure power for individual peripheral
+ * @param[in] PPType peripheral type, should be:
+ * - CGU_PERIPHERAL_ADC0 :ADC0
+ * - CGU_PERIPHERAL_ADC1 :ADC1
+ * - CGU_PERIPHERAL_AES :AES
+ * - CGU_PERIPHERAL_APB1_BUS :APB1 bus
+ * - CGU_PERIPHERAL_APB3_BUS :APB3 bus
+ * - CGU_PERIPHERAL_CAN :CAN
+ * - CGU_PERIPHERAL_CREG :CREG
+ * - CGU_PERIPHERAL_DAC :DAC
+ * - CGU_PERIPHERAL_DMA :DMA
+ * - CGU_PERIPHERAL_EMC :EMC
+ * - CGU_PERIPHERAL_ETHERNET :ETHERNET
+ * - CGU_PERIPHERAL_GPIO :GPIO
+ * - CGU_PERIPHERAL_I2C0 :I2C0
+ * - CGU_PERIPHERAL_I2C1 :I2C1
+ * - CGU_PERIPHERAL_I2S :I2S
+ * - CGU_PERIPHERAL_LCD :LCD
+ * - CGU_PERIPHERAL_M3CORE :M3 core
+ * - CGU_PERIPHERAL_M3_BUS :M3 bus
+ * - CGU_PERIPHERAL_MOTOCON :Motor control
+ * - CGU_PERIPHERAL_QEI :QEI
+ * - CGU_PERIPHERAL_RITIMER :RIT timer
+ * - CGU_PERIPHERAL_SCT :SCT
+ * - CGU_PERIPHERAL_SCU :SCU
+ * - CGU_PERIPHERAL_SDIO :SDIO
+ * - CGU_PERIPHERAL_SPIFI :SPIFI
+ * - CGU_PERIPHERAL_SSP0 :SSP0
+ * - CGU_PERIPHERAL_SSP1 :SSP1
+ * - CGU_PERIPHERAL_TIMER0 :TIMER0
+ * - CGU_PERIPHERAL_TIMER1 :TIMER1
+ * - CGU_PERIPHERAL_TIMER2 :TIMER2
+ * - CGU_PERIPHERAL_TIMER3 :TIMER3
+ * - CGU_PERIPHERAL_UART0 :UART0
+ * - CGU_PERIPHERAL_UART1 :UART1
+ * - CGU_PERIPHERAL_UART2 :UART2
+ * - CGU_PERIPHERAL_UART3 :UART3
+ * - CGU_PERIPHERAL_USB0 :USB0
+ * - CGU_PERIPHERAL_USB1 :USB1
+ * - CGU_PERIPHERAL_WWDT :WWDT
+ * @param[in] en status, should be:
+ * - ENABLE: Enable power
+ * - DISABLE: Disable power
+ * @return Configure status, could be:
+ * - CGU_ERROR_SUCCESS: successful
+ * - Other: error
+ **********************************************************************/
+uint32_t CGU_ConfigPWR(CGU_PERIPHERAL_T PPType, FunctionalState en)
+{
+ if (PPType >= CGU_PERIPHERAL_WWDT && PPType <= CGU_PERIPHERAL_ADC0) {
+ return CGU_ERROR_INVALID_PARAM;
+ }
+
+ if (en == DISABLE) { /* Going to disable clock */
+ /*Get Reg branch status */
+ if (CGU_PERIPHERAL_Info[PPType].RegBranchOffset != 0 &&
+ CGU_REG_BRANCH_STATUS(PPType) & 1) {
+ CGU_REG_BRANCH_CTRL(PPType) &= ~1; /* Disable branch clock */
+
+ while (CGU_REG_BRANCH_STATUS(PPType) & 1);
+ }
+
+ /* GetBase Status*/
+ if ((CGU_PERIPHERAL_Info[PPType].RegBaseEntity != CGU_ENTITY_NONE) &&
+ CGU_GetBaseStatus((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].RegBaseEntity) == 0) {
+ /* Disable Base */
+ CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].RegBaseEntity, 0);
+ }
+
+ /* Same for Peripheral */
+ if ((CGU_PERIPHERAL_Info[PPType].PerBranchOffset != 0) && (CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)) {
+ CGU_PER_BRANCH_CTRL(PPType) &= ~1; /* Disable branch clock */
+
+ while (CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK);
+ }
+
+ /* GetBase Status*/
+ if ((CGU_PERIPHERAL_Info[PPType].PerBaseEntity != CGU_ENTITY_NONE) &&
+ CGU_GetBaseStatus((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].PerBaseEntity) == 0) {
+ /* Disable Base */
+ CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].PerBaseEntity, 0);
+ }
+
+ } else {
+ /* enable */
+ /* GetBase Status*/
+ if ((CGU_PERIPHERAL_Info[PPType].RegBaseEntity != CGU_ENTITY_NONE) && CGU_REG_BASE_CTRL(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK) {
+ /* Enable Base */
+ CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].RegBaseEntity, 1);
+ }
+
+ /*Get Reg branch status */
+ if ((CGU_PERIPHERAL_Info[PPType].RegBranchOffset != 0) && !(CGU_REG_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)) {
+ CGU_REG_BRANCH_CTRL(PPType) |= 1; /* Enable branch clock */
+
+ while (!(CGU_REG_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK));
+ }
+
+ /* Same for Peripheral */
+ /* GetBase Status*/
+ if ((CGU_PERIPHERAL_Info[PPType].PerBaseEntity != CGU_ENTITY_NONE) &&
+ (CGU_PER_BASE_CTRL(PPType) & 1)) {
+ /* Enable Base */
+ CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].PerBaseEntity, 1);
+ }
+
+ /*Get Reg branch status */
+ if ((CGU_PERIPHERAL_Info[PPType].PerBranchOffset != 0) && !(CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)) {
+ CGU_PER_BRANCH_CTRL(PPType) |= 1; /* Enable branch clock */
+
+ while (!(CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK));
+ }
+ }
+
+ if (CGU_PERIPHERAL_Info[PPType].next) {
+ return CGU_ConfigPWR((CGU_PERIPHERAL_T)CGU_PERIPHERAL_Info[PPType].next, en);
+ }
+
+ return CGU_ERROR_SUCCESS;
+}
+
+
+/*********************************************************************//**
+ * @brief Get peripheral clock frequency
+ * @param[in] Clock Peripheral type, should be:
+ * - CGU_PERIPHERAL_ADC0 :ADC0
+ * - CGU_PERIPHERAL_ADC1 :ADC1
+ * - CGU_PERIPHERAL_AES :AES
+ * - CGU_PERIPHERAL_APB1_BUS :APB1 bus
+ * - CGU_PERIPHERAL_APB3_BUS :APB3 bus
+ * - CGU_PERIPHERAL_CAN :CAN
+ * - CGU_PERIPHERAL_CREG :CREG
+ * - CGU_PERIPHERAL_DAC :DAC
+ * - CGU_PERIPHERAL_DMA :DMA
+ * - CGU_PERIPHERAL_EMC :EMC
+ * - CGU_PERIPHERAL_ETHERNET :ETHERNET
+ * - CGU_PERIPHERAL_GPIO :GPIO
+ * - CGU_PERIPHERAL_I2C0 :I2C0
+ * - CGU_PERIPHERAL_I2C1 :I2C1
+ * - CGU_PERIPHERAL_I2S :I2S
+ * - CGU_PERIPHERAL_LCD :LCD
+ * - CGU_PERIPHERAL_M3CORE :M3 core
+ * - CGU_PERIPHERAL_M3_BUS :M3 bus
+ * - CGU_PERIPHERAL_MOTOCON :Motor control
+ * - CGU_PERIPHERAL_QEI :QEI
+ * - CGU_PERIPHERAL_RITIMER :RIT timer
+ * - CGU_PERIPHERAL_SCT :SCT
+ * - CGU_PERIPHERAL_SCU :SCU
+ * - CGU_PERIPHERAL_SDIO :SDIO
+ * - CGU_PERIPHERAL_SPIFI :SPIFI
+ * - CGU_PERIPHERAL_SSP0 :SSP0
+ * - CGU_PERIPHERAL_SSP1 :SSP1
+ * - CGU_PERIPHERAL_TIMER0 :TIMER0
+ * - CGU_PERIPHERAL_TIMER1 :TIMER1
+ * - CGU_PERIPHERAL_TIMER2 :TIMER2
+ * - CGU_PERIPHERAL_TIMER3 :TIMER3
+ * - CGU_PERIPHERAL_UART0 :UART0
+ * - CGU_PERIPHERAL_UART1 :UART1
+ * - CGU_PERIPHERAL_UART2 :UART2
+ * - CGU_PERIPHERAL_UART3 :UART3
+ * - CGU_PERIPHERAL_USB0 :USB0
+ * - CGU_PERIPHERAL_USB1 :USB1
+ * - CGU_PERIPHERAL_WWDT :WWDT
+ * @return Return frequently value
+ **********************************************************************/
+uint32_t CGU_GetPCLKFrequency(CGU_PERIPHERAL_T Clock)
+{
+ uint32_t ClkSrc;
+
+ if (Clock >= CGU_PERIPHERAL_WWDT && Clock <= CGU_PERIPHERAL_ADC0) {
+ return CGU_ERROR_INVALID_PARAM;
+ }
+
+ if (CGU_PERIPHERAL_Info[Clock].PerBaseEntity != CGU_ENTITY_NONE) {
+ /* Get Base Clock Source */
+ ClkSrc = (CGU_PER_BASE_CTRL(Clock) & CGU_CTRL_SRC_MASK) >> 24;
+
+ /* GetBase Status*/
+ if (CGU_PER_BASE_CTRL(Clock) & 1) {
+ return 0;
+ }
+
+ /* check Branch if it is enabled */
+ if ((CGU_PERIPHERAL_Info[Clock].PerBranchOffset != 0) && !(CGU_PER_BRANCH_STATUS(Clock) & CGU_BRANCH_STATUS_ENABLE_MASK)) {
+ return 0;
+ }
+
+ } else {
+ if (CGU_REG_BASE_CTRL(Clock) & 1) {
+ return 0;
+ }
+
+ ClkSrc = (CGU_REG_BASE_CTRL(Clock) & CGU_CTRL_SRC_MASK) >> 24;
+
+ /* check Branch if it is enabled */
+ if ((CGU_PERIPHERAL_Info[Clock].RegBranchOffset != 0) && !(CGU_REG_BRANCH_STATUS(Clock) & CGU_BRANCH_STATUS_ENABLE_MASK)) {
+ return 0;
+ }
+ }
+
+ return CGU_ClockSourceFrequency[ClkSrc];
+}
+
+
+/*********************************************************************//**
+ * @brief Update clock
+ * @param[in] None
+ * @return None
+ **********************************************************************/
+void CGU_UpdateClock(void)
+{
+ uint32_t ClkSrc;
+ uint32_t div;
+ uint32_t divisor;
+ int32_t RegOffset;
+
+ /* 32OSC */
+ if (ISBITSET(LPC_CREG->CREG0, 1) && ISBITCLR(LPC_CREG->CREG0, 3)) {
+ CGU_ClockSourceFrequency[CGU_CLKSRC_32KHZ_OSC] = 32768;
+
+ } else {
+ CGU_ClockSourceFrequency[CGU_CLKSRC_32KHZ_OSC] = 0;
+ }
+
+ /*PLL0*/
+ /* PLL1 */
+ if (ISBITCLR(LPC_CGU->PLL1_CTRL, 0) /* Enabled */ /* EA ANDLI: Original code tested bit 1 which is BYPASS, not PD */
+ && (LPC_CGU->PLL1_STAT & 1)) { /* Locked? */
+ ClkSrc = (LPC_CGU->PLL1_CTRL & CGU_CTRL_SRC_MASK) >> 24;
+ CGU_ClockSourceFrequency[CGU_CLKSRC_PLL1] = CGU_ClockSourceFrequency[ClkSrc] *
+ (((LPC_CGU->PLL1_CTRL >> 16) & 0xFF) + 1);
+
+ } else {
+ CGU_ClockSourceFrequency[CGU_CLKSRC_PLL1] = 0;
+ }
+
+ /* DIV */
+ for (div = CGU_CLKSRC_IDIVA; div <= CGU_CLKSRC_IDIVE; div++) {
+ RegOffset = CGU_Entity_ControlReg_Offset[div];
+
+ if (ISBITCLR(CGU_ADDRESS32(LPC_CGU, RegOffset), 1)) {
+ ClkSrc = (CGU_ADDRESS32(LPC_CGU, RegOffset) & CGU_CTRL_SRC_MASK) >> 24;
+ divisor = (CGU_ADDRESS32(LPC_CGU, RegOffset) >> 2) & 0xFF;
+ divisor ++;
+ CGU_ClockSourceFrequency[div] = CGU_ClockSourceFrequency[ClkSrc] / divisor;
+
+ } else {
+ CGU_ClockSourceFrequency[div] = 0;
+ }
+ }
+}
+
+/*********************************************************************//**
+ * @brief Set XTAL oscillator value
+ * @param[in] ClockFrequency XTAL Frequency value
+ * @return Setting status, could be:
+ * - CGU_ERROR_SUCCESS: successful
+ * - CGU_ERROR_FREQ_OUTOF_RANGE: XTAL value set is out of range
+ **********************************************************************/
+uint32_t CGU_SetXTALOSC(uint32_t ClockFrequency)
+{
+ if (ClockFrequency < 15000000) {
+ LPC_CGU->XTAL_OSC_CTRL &= ~(1 << 2);
+
+ } else if (ClockFrequency < 25000000) {
+ LPC_CGU->XTAL_OSC_CTRL |= (1 << 2);
+
+ } else {
+ return CGU_ERROR_FREQ_OUTOF_RANGE;
+ }
+
+ CGU_ClockSourceFrequency[CGU_CLKSRC_XTAL_OSC] = ClockFrequency;
+ return CGU_ERROR_SUCCESS;
+}
+
+
+/*********************************************************************//**
+ * @brief Set clock divider
+ * @param[in] SelectDivider Clock source, should be:
+ * - CGU_CLKSRC_IDIVA :Integer divider register A
+ * - CGU_CLKSRC_IDIVB :Integer divider register B
+ * - CGU_CLKSRC_IDIVC :Integer divider register C
+ * - CGU_CLKSRC_IDIVD :Integer divider register D
+ * - CGU_CLKSRC_IDIVE :Integer divider register E
+ * @param[in] divisor Divisor value, should be: 0..255
+ * @return Setting status, could be:
+ * - CGU_ERROR_SUCCESS: successful
+ * - CGU_ERROR_INVALID_ENTITY: Invalid entity
+ **********************************************************************/
+/* divisor number must >=1*/
+uint32_t CGU_SetDIV(CGU_ENTITY_T SelectDivider, uint32_t divisor)
+{
+ int32_t RegOffset;
+ uint32_t tempReg;
+
+ if (SelectDivider >= CGU_CLKSRC_IDIVA && SelectDivider <= CGU_CLKSRC_IDIVE) {
+ RegOffset = CGU_Entity_ControlReg_Offset[SelectDivider];
+
+ if (RegOffset == -1) {
+ return CGU_ERROR_INVALID_ENTITY;
+ }
+
+ tempReg = CGU_ADDRESS32(LPC_CGU, RegOffset);
+ tempReg &= ~(0xFF << 2);
+ tempReg |= ((divisor - 1) & 0xFF) << 2;
+ CGU_ADDRESS32(LPC_CGU, RegOffset) = tempReg;
+ return CGU_ERROR_SUCCESS;
+ }
+
+ return CGU_ERROR_INVALID_ENTITY;
+}
+
+/*********************************************************************//**
+ * @brief Enable clock entity
+ * @param[in] ClockEntity Clock entity, should be:
+ * - CGU_CLKSRC_32KHZ_OSC :32Khz oscillator
+ * - CGU_CLKSRC_IRC :IRC clock
+ * - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock
+ * - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock
+ * - CGU_CLKSRC_GP_CLKIN :General purpose input clock
+ * - CGU_CLKSRC_XTAL_OSC :Crystal oscillator
+ * - CGU_CLKSRC_PLL0 :PLL0 clock
+ * - CGU_CLKSRC_PLL1 :PLL1 clock
+ * - CGU_CLKSRC_IDIVA :Integer divider register A
+ * - CGU_CLKSRC_IDIVB :Integer divider register B
+ * - CGU_CLKSRC_IDIVC :Integer divider register C
+ * - CGU_CLKSRC_IDIVD :Integer divider register D
+ * - CGU_CLKSRC_IDIVE :Integer divider register E
+ * - CGU_BASE_SAFE :Base safe clock (always on)for WDT
+ * - CGU_BASE_USB0 :Base clock for USB0
+ * - CGU_BASE_PERIPH :Base clock for Peripheral bus
+ * - CGU_BASE_USB1 :Base clock for USB1
+ * - CGU_BASE_M4 :System base clock for ARM Cortex-M3 core
+ * and APB peripheral blocks #0 and #2
+ * - CGU_BASE_SPIFI :Base clock for SPIFI
+ * - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx
+ * - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx
+ * - CGU_BASE_APB1 :Base clock for APB peripheral block #1
+ * - CGU_BASE_APB3 :Base clock for APB peripheral block #3
+ * - CGU_BASE_LCD :Base clock for LCD
+ * - CGU_BASE_SDIO :Base clock for SDIO card reader
+ * - CGU_BASE_SSP0 :Base clock for SSP0
+ * - CGU_BASE_SSP1 :Base clock for SSP1
+ * - CGU_BASE_UART0 :Base clock for UART0
+ * - CGU_BASE_UART1 :Base clock for UART1
+ * - CGU_BASE_UART2 :Base clock for UART2
+ * - CGU_BASE_UART3 :Base clock for UART3
+ * - CGU_BASE_CLKOUT :Base clock for CLKOUT pin
+ * @param[in] en status, should be:
+ * - ENABLE: Enable power
+ * - DISABLE: Disable power
+ * @return Setting status, could be:
+ * - CGU_ERROR_SUCCESS: successful
+ * - CGU_ERROR_INVALID_ENTITY: Invalid entity
+ **********************************************************************/
+uint32_t CGU_EnableEntity(CGU_ENTITY_T ClockEntity, uint32_t en)
+{
+ int32_t RegOffset;
+ int32_t i;
+
+ if (ClockEntity == CGU_CLKSRC_32KHZ_OSC) {
+ if (en) {
+ LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
+ LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
+
+ } else {
+ LPC_CREG->CREG0 &= ~((1 << 1) | (1 << 0));
+ LPC_CREG->CREG0 |= (1 << 3);
+ }
+
+ for (i = 0; i < 1000000; i++);
+
+ } else if (ClockEntity == CGU_CLKSRC_ENET_RX_CLK) {
+ scu_pinmux(0xC , 0 , MD_PLN, FUNC3);
+
+ } else if (ClockEntity == CGU_CLKSRC_ENET_TX_CLK) {
+ scu_pinmux(0x1 , 19 , MD_PLN, FUNC0);
+
+ } else if (ClockEntity == CGU_CLKSRC_GP_CLKIN) {
+ } else if (ClockEntity == CGU_CLKSRC_TCK) {
+ } else if (ClockEntity == CGU_CLKSRC_XTAL_OSC) {
+ if (!en) {
+ LPC_CGU->XTAL_OSC_CTRL |= CGU_CTRL_EN_MASK;
+
+ } else {
+ LPC_CGU->XTAL_OSC_CTRL &= ~CGU_CTRL_EN_MASK;
+ }
+
+ /*Delay for stable clock*/
+ for (i = 0; i < 1000000; i++);
+
+ } else {
+ RegOffset = CGU_Entity_ControlReg_Offset[ClockEntity];
+
+ if (RegOffset == -1) {
+ return CGU_ERROR_INVALID_ENTITY;
+ }
+
+ if (!en) {
+ CGU_ADDRESS32(CGU_CGU_ADDR, RegOffset) |= CGU_CTRL_EN_MASK;
+
+ } else {
+ CGU_ADDRESS32(CGU_CGU_ADDR, RegOffset) &= ~CGU_CTRL_EN_MASK;
+
+ /*if PLL is selected check if it is locked */
+ if (ClockEntity == CGU_CLKSRC_PLL0) {
+ while ((LPC_CGU->PLL0USB_STAT & 1) == 0x0);
+ }
+
+ if (ClockEntity == CGU_CLKSRC_PLL0_AUDIO) {
+ while ((LPC_CGU->PLL0AUDIO_STAT & 1) == 0x0);
+ }
+
+ if (ClockEntity == CGU_CLKSRC_PLL1) {
+ while ((LPC_CGU->PLL1_STAT & 1) == 0x0);
+
+ /*post check lock status */
+ if (!(LPC_CGU->PLL1_STAT & 1))
+ while (1);
+ }
+ }
+ }
+
+ return CGU_ERROR_SUCCESS;
+}
+
+/*********************************************************************//**
+ * @brief Connect entity clock source
+ * @param[in] ClockSource Clock source, should be:
+ * - CGU_CLKSRC_32KHZ_OSC :32Khz oscillator
+ * - CGU_CLKSRC_IRC :IRC clock
+ * - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock
+ * - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock
+ * - CGU_CLKSRC_GP_CLKIN :General purpose input clock
+ * - CGU_CLKSRC_XTAL_OSC :Crystal oscillator
+ * - CGU_CLKSRC_PLL0 :PLL0 clock
+ * - CGU_CLKSRC_PLL1 :PLL1 clock
+ * - CGU_CLKSRC_IDIVA :Integer divider register A
+ * - CGU_CLKSRC_IDIVB :Integer divider register B
+ * - CGU_CLKSRC_IDIVC :Integer divider register C
+ * - CGU_CLKSRC_IDIVD :Integer divider register D
+ * - CGU_CLKSRC_IDIVE :Integer divider register E
+ * @param[in] ClockEntity Clock entity, should be:
+ * - CGU_CLKSRC_PLL0 :PLL0 clock
+ * - CGU_CLKSRC_PLL1 :PLL1 clock
+ * - CGU_CLKSRC_IDIVA :Integer divider register A
+ * - CGU_CLKSRC_IDIVB :Integer divider register B
+ * - CGU_CLKSRC_IDIVC :Integer divider register C
+ * - CGU_CLKSRC_IDIVD :Integer divider register D
+ * - CGU_CLKSRC_IDIVE :Integer divider register E
+ * - CGU_BASE_SAFE :Base safe clock (always on)for WDT
+ * - CGU_BASE_USB0 :Base clock for USB0
+ * - CGU_BASE_USB1 :Base clock for USB1
+ * - CGU_BASE_M4 :System base clock for ARM Cortex-M3 core
+ * and APB peripheral blocks #0 and #2
+ * - CGU_BASE_SPIFI :Base clock for SPIFI
+ * - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx
+ * - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx
+ * - CGU_BASE_APB1 :Base clock for APB peripheral block #1
+ * - CGU_BASE_APB3 :Base clock for APB peripheral block #3
+ * - CGU_BASE_LCD :Base clock for LCD
+ * - CGU_BASE_SDIO :Base clock for SDIO card reader
+ * - CGU_BASE_SSP0 :Base clock for SSP0
+ * - CGU_BASE_SSP1 :Base clock for SSP1
+ * - CGU_BASE_UART0 :Base clock for UART0
+ * - CGU_BASE_UART1 :Base clock for UART1
+ * - CGU_BASE_UART2 :Base clock for UART2
+ * - CGU_BASE_UART3 :Base clock for UART3
+ * - CGU_BASE_CLKOUT :Base clock for CLKOUT pin
+ * @return Setting status, could be:
+ * - CGU_ERROR_SUCCESS: successful
+ * - CGU_ERROR_CONNECT_TOGETHER: Error when 2 clock source connect together
+ * - CGU_ERROR_INVALID_CLOCK_SOURCE: Invalid clock source error
+ * - CGU_ERROR_INVALID_ENTITY: Invalid entity error
+ **********************************************************************/
+/* Connect one entity into clock source */
+uint32_t CGU_EntityConnect(CGU_ENTITY_T ClockSource, CGU_ENTITY_T ClockEntity)
+{
+ int32_t RegOffset;
+ uint32_t tempReg;
+
+ if (ClockSource > CGU_CLKSRC_IDIVE) {
+ return CGU_ERROR_INVALID_CLOCK_SOURCE;
+ }
+
+ if (ClockEntity >= CGU_CLKSRC_PLL0 && ClockEntity <= CGU_BASE_CLKOUT) {
+ if (CGU_ConnectAlloc_Tbl[ClockSource][ClockEntity]) {
+ RegOffset = CGU_Entity_ControlReg_Offset[ClockSource];
+
+ if (RegOffset != -1) {
+ if (ClockEntity <= CGU_CLKSRC_IDIVE &&
+ ClockEntity >= CGU_CLKSRC_PLL0) {
+ //RegOffset = (CGU_ADDRESS32(LPC_CGU,RegOffset)>>24)&0xF;
+ if (((CGU_ADDRESS32(LPC_CGU, RegOffset) >> 24) & 0xF) == ClockEntity) {
+ return CGU_ERROR_CONNECT_TOGETHER;
+ }
+ }
+ }
+
+ RegOffset = CGU_Entity_ControlReg_Offset[ClockEntity];
+
+ if (RegOffset == -1) {
+ return CGU_ERROR_INVALID_ENTITY;
+ }
+
+ tempReg = CGU_ADDRESS32(LPC_CGU, RegOffset);
+ tempReg &= ~CGU_CTRL_SRC_MASK;
+ tempReg |= ClockSource << 24 | CGU_CTRL_AUTOBLOCK_MASK;
+ CGU_ADDRESS32(LPC_CGU, RegOffset) = tempReg;
+ return CGU_ERROR_SUCCESS;
+
+ } else {
+ return CGU_ERROR_INVALID_CLOCK_SOURCE;
+ }
+
+ } else {
+ return CGU_ERROR_INVALID_ENTITY;
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Get current USB PLL clock from XTAL
+ * @param[in] None
+ * @return Returned clock value
+ **********************************************************************/
+uint32_t CGU_SetPLL0(void)
+{
+ // Setup PLL550 to generate 480MHz from 12 MHz crystal
+ LPC_CGU->PLL0USB_CTRL |= 1; // Power down PLL
+ // P N
+ LPC_CGU->PLL0USB_NP_DIV = (98 << 0) | (514 << 12);
+ // SELP SELI SELR MDEC
+ LPC_CGU->PLL0USB_MDIV = (0xB << 17) | (0x10 << 22) | (0 << 28) | (0x7FFA << 0);
+ LPC_CGU->PLL0USB_CTRL = (CGU_CLKSRC_XTAL_OSC << 24) | (0x3 << 2) | (1 << 4);
+ return CGU_ERROR_SUCCESS;
+}
+
+
+
+/*********************************************************************//**
+ * @brief Get current Audio PLL clock from XTAL
+ * @param[in] None
+ * @return Returned clock value
+ **********************************************************************/
+uint32_t CGU_SetPLL0audio(void)
+{
+ /* disable clock, disable skew enable, power down pll,
+ * (dis/en)able post divider, (dis/en)able pre-divider,
+ * disable free running mode, disable bandsel,
+ * enable up limmiter, disable bypass
+ */
+ LPC_CGU->PLL0AUDIO_CTRL = (6 << 24) /* source = XTAL OSC 12 MHz */
+ | _BIT(0); /* power down */
+ /* PLL should be set to 512fs rate 512 * 48000 = 24576000 Hz */
+ /* set mdec register */
+#if 1 // results from gcc program
+ LPC_CGU->PLL0AUDIO_MDIV = 0x23e34d3;
+ LPC_CGU->PLL0AUDIO_NP_DIV = 0x3f00e;
+ LPC_CGU->PLL0AUDIO_CTRL = (6 << 24) /* source = XTAL OSC 12 MHz */
+ | (6 << 12) // fractional divider off and bypassed
+ | _BIT(4); /* CLKEN */
+#else
+ LPC_CGU->PLL0AUDIO_MDIV = (0 << 28) /* SELR */
+ | (40 << 22) /* SELI */
+ | (31 << 17) /* SELP */
+ | 11372; /* MDEC */
+ /* set ndec, pdec register */
+ LPC_CGU->PLL0AUDIO_NP_DIV = (22 << 12) /* ndec */
+ | (10); /* pdec */
+ /* set fraction divider register. [21:15] = m, [14:0] = fractional value */
+ LPC_CGU->PLL0AUDIO_FRAC = (86 << 15) | 0x1B7;
+ LPC_CGU->PLL0AUDIO_CTRL = (6 << 24) /* source = XTAL OSC 12 MHz */
+ | _BIT(12) /* enable SD modulator to update mdec*/
+ | _BIT(4); /* CLKEN */
+#endif
+
+ /* wait for lock */
+ while (!(LPC_CGU->PLL0AUDIO_STAT & 1));
+
+ return CGU_ERROR_SUCCESS;
+}
+
+
+/*********************************************************************//**
+ * @brief Setting PLL1
+ * @param[in] mult Multiple value
+ * @return Setting status, could be:
+ * - CGU_ERROR_SUCCESS: successful
+ * - CGU_ERROR_INVALID_PARAM: Invalid parameter error
+ **********************************************************************/
+uint32_t CGU_SetPLL1(uint32_t mult)
+{
+ uint32_t msel = 0, nsel = 0, psel = 0, pval = 1;
+ uint32_t freq;
+ uint32_t ClkSrc = (LPC_CGU->PLL1_CTRL & CGU_CTRL_SRC_MASK) >> 24;
+ freq = CGU_ClockSourceFrequency[ClkSrc];
+ freq *= mult;
+ msel = mult - 1;
+ LPC_CGU->PLL1_CTRL &= ~(CGU_PLL1_FBSEL_MASK |
+ CGU_PLL1_BYPASS_MASK |
+ CGU_PLL1_DIRECT_MASK |
+ (0x03 << 8) | (0xFF << 16) | (0x03 << 12));
+
+ if (freq < 156000000) {
+ //psel is encoded such that 0=1, 1=2, 2=4, 3=8
+ while (2 * (pval)*freq < 156000000) {
+ psel++;
+ pval *= 2;
+ }
+
+// if(2*(pval)*freq > 320000000) {
+// //THIS IS OUT OF RANGE!!!
+// //HOW DO WE ASSERT IN SAMPLE CODE?
+// //__breakpoint(0);
+// return CGU_ERROR_INVALID_PARAM;
+// }
+ LPC_CGU->PLL1_CTRL |= (msel << 16) | (nsel << 12) | (psel << 8) | CGU_PLL1_FBSEL_MASK;
+
+ } else if (freq < 320000000) {
+ LPC_CGU->PLL1_CTRL |= (msel << 16) | (nsel << 12) | (psel << 8) | CGU_PLL1_DIRECT_MASK | CGU_PLL1_FBSEL_MASK;
+
+ } else {
+ return CGU_ERROR_INVALID_PARAM;
+ }
+
+ return CGU_ERROR_SUCCESS;
+}
+
+
+/*********************************************************************//**
+ * @brief Get current base status
+ * @param[in] Base Base type, should be:
+ * - CGU_BASE_USB0 :Base clock for USB0
+ * - CGU_BASE_USB1 :Base clock for USB1
+ * - CGU_BASE_M4 :System base clock for ARM Cortex-M3 core
+ * and APB peripheral blocks #0 and #2
+ * - CGU_BASE_SPIFI :Base clock for SPIFI
+ * - CGU_BASE_APB1 :Base clock for APB peripheral block #1
+ * - CGU_BASE_APB3 :Base clock for APB peripheral block #3
+ * - CGU_BASE_SDIO :Base clock for SDIO card reader
+ * - CGU_BASE_SSP0 :Base clock for SSP0
+ * - CGU_BASE_SSP1 :Base clock for SSP1
+ * - CGU_BASE_UART0 :Base clock for UART0
+ * - CGU_BASE_UART1 :Base clock for UART1
+ * - CGU_BASE_UART2 :Base clock for UART2
+ * - CGU_BASE_UART3 :Base clock for UART3
+ * @return Always return 0
+ **********************************************************************/
+uint32_t CGU_GetBaseStatus(CGU_ENTITY_T Base)
+{
+ switch (Base) {
+ /*CCU1*/
+ case CGU_BASE_APB3:
+ return LPC_CCU1->BASE_STAT & 1;
+
+ case CGU_BASE_APB1:
+ return (LPC_CCU1->BASE_STAT >> 1) & 1;
+
+ case CGU_BASE_SPIFI:
+ return (LPC_CCU1->BASE_STAT >> 2) & 1;
+
+ case CGU_BASE_M4:
+ return (LPC_CCU1->BASE_STAT >> 3) & 1;
+
+ case CGU_BASE_USB0:
+ return (LPC_CCU1->BASE_STAT >> 7) & 1;
+
+ case CGU_BASE_USB1:
+ return (LPC_CCU1->BASE_STAT >> 8) & 1;
+
+ /*CCU2*/
+ case CGU_BASE_UART3:
+ return (LPC_CCU2->BASE_STAT >> 1) & 1;
+
+ case CGU_BASE_UART2:
+ return (LPC_CCU2->BASE_STAT >> 2) & 1;
+
+ case CGU_BASE_UART1:
+ return (LPC_CCU2->BASE_STAT >> 3) & 1;
+
+ case CGU_BASE_UART0:
+ return (LPC_CCU2->BASE_STAT >> 4) & 1;
+
+ case CGU_BASE_SSP1:
+ return (LPC_CCU2->BASE_STAT >> 5) & 1;
+
+ case CGU_BASE_SSP0:
+ return (LPC_CCU2->BASE_STAT >> 6) & 1;
+
+ case CGU_BASE_SDIO:
+ return (LPC_CCU2->BASE_STAT >> 7) & 1;
+
+ /*BASE SAFE is used by WWDT and RGU*/
+ case CGU_BASE_SAFE:
+ break;
+
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+
+/*********************************************************************//**
+ * @brief Compare one source clock to IRC clock
+ * @param[in] Clock Clock entity that will be compared to IRC, should be:
+ * - CGU_CLKSRC_32KHZ_OSC :32Khz crystal oscillator
+ * - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock
+ * - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock
+ * - CGU_CLKSRC_GP_CLKIN :General purpose input clock
+ * - CGU_CLKSRC_XTAL_OSC :Crystal oscillator
+ * - CGU_CLKSRC_PLL0 :PLL0 clock
+ * - CGU_CLKSRC_PLL1 :PLL1 clock
+ * - CGU_CLKSRC_IDIVA :Integer divider register A
+ * - CGU_CLKSRC_IDIVB :Integer divider register B
+ * - CGU_CLKSRC_IDIVC :Integer divider register C
+ * - CGU_CLKSRC_IDIVD :Integer divider register D
+ * - CGU_CLKSRC_IDIVE :Integer divider register E
+ * - CGU_BASE_SAFE :Base safe clock (always on)for WDT
+ * - CGU_BASE_USB0 :Base clock for USB0
+ * - CGU_BASE_USB1 :Base clock for USB1
+ * - CGU_BASE_M4 :System base clock for ARM Cortex-M3 core
+ * and APB peripheral blocks #0 and #2
+ * - CGU_BASE_SPIFI :Base clock for SPIFI
+ * - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx
+ * - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx
+ * - CGU_BASE_APB1 :Base clock for APB peripheral block #1
+ * - CGU_BASE_APB3 :Base clock for APB peripheral block #3
+ * - CGU_BASE_LCD :Base clock for LCD
+ * - CGU_BASE_SDIO :Base clock for SDIO card reader
+ * - CGU_BASE_SSP0 :Base clock for SSP0
+ * - CGU_BASE_SSP1 :Base clock for SSP1
+ * - CGU_BASE_UART0 :Base clock for UART0
+ * - CGU_BASE_UART1 :Base clock for UART1
+ * - CGU_BASE_UART2 :Base clock for UART2
+ * - CGU_BASE_UART3 :Base clock for UART3
+ * - CGU_BASE_CLKOUT :Base clock for CLKOUT pin
+ * @param[in] m Multiple value pointer
+ * @param[in] d Divider value pointer
+ * @return Compare status, could be:
+ * - (-1): fail
+ * - 0: successful
+ * @note Formula used to compare:
+ * FClock = F_IRC* m / d
+ **********************************************************************/
+int CGU_FrequencyMonitor(CGU_ENTITY_T Clock, uint32_t *m, uint32_t *d)
+{
+ uint32_t n, c, temp;
+ int i;
+ /* Maximum allow RCOUNT number */
+ c = 511;
+ /* Check Source Clock Freq is larger or smaller */
+ LPC_CGU->FREQ_MON = (Clock << 24) | 1 << 23 | c;
+
+ while (LPC_CGU->FREQ_MON & (1 << 23));
+
+ for (i = 0; i < 10000; i++);
+
+ temp = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
+
+ if (temp == 0) { /* too low F < 12000000/511*/
+ return -1;
+ }
+
+ if (temp > 511) { /* larger */
+ c = 511 - (LPC_CGU->FREQ_MON & 0x1FF);
+
+ } else {
+ do {
+ c--;
+ LPC_CGU->FREQ_MON = (Clock << 24) | 1 << 23 | c;
+
+ while (LPC_CGU->FREQ_MON & (1 << 23));
+
+ for (i = 0; i < 10000; i++);
+
+ n = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
+ } while (n == temp);
+
+ c++;
+ }
+
+ *m = temp;
+ *d = c;
+ return 0;
+}
+
+/*********************************************************************//**
+ * @brief Compare one source clock to another source clock
+ * @param[in] Clock Clock entity that will be compared to second source, should be:
+ * - CGU_CLKSRC_32KHZ_OSC :32Khz crystal oscillator
+ * - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock
+ * - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock
+ * - CGU_CLKSRC_GP_CLKIN :General purpose input clock
+ * - CGU_CLKSRC_XTAL_OSC :Crystal oscillator
+ * - CGU_CLKSRC_PLL0 :PLL0 clock
+ * - CGU_CLKSRC_PLL1 :PLL1 clock
+ * - CGU_CLKSRC_IDIVA :Integer divider register A
+ * - CGU_CLKSRC_IDIVB :Integer divider register B
+ * - CGU_CLKSRC_IDIVC :Integer divider register C
+ * - CGU_CLKSRC_IDIVD :Integer divider register D
+ * - CGU_CLKSRC_IDIVE :Integer divider register E
+ * - CGU_BASE_SAFE :Base safe clock (always on)for WDT
+ * - CGU_BASE_USB0 :Base clock for USB0
+ * - CGU_BASE_USB1 :Base clock for USB1
+ * - CGU_BASE_M4 :System base clock for ARM Cortex-M3 core
+ * and APB peripheral blocks #0 and #2
+ * - CGU_BASE_SPIFI :Base clock for SPIFI
+ * - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx
+ * - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx
+ * - CGU_BASE_APB1 :Base clock for APB peripheral block #1
+ * - CGU_BASE_APB3 :Base clock for APB peripheral block #3
+ * - CGU_BASE_LCD :Base clock for LCD
+ * - CGU_BASE_SDIO :Base clock for SDIO card reader
+ * - CGU_BASE_SSP0 :Base clock for SSP0
+ * - CGU_BASE_SSP1 :Base clock for SSP1
+ * - CGU_BASE_UART0 :Base clock for UART0
+ * - CGU_BASE_UART1 :Base clock for UART1
+ * - CGU_BASE_UART2 :Base clock for UART2
+ * - CGU_BASE_UART3 :Base clock for UART3
+ * - CGU_BASE_CLKOUT :Base clock for CLKOUT pin
+ * @param[in] CompareToClock Clock source that to be compared to first source, should be different
+ * to first source.
+ * @param[in] m Multiple value pointer
+ * @param[in] d Divider value pointer
+ * @return Compare status, could be:
+ * - (-1): fail
+ * - 0: successful
+ * @note Formula used to compare:
+ * FClock = m*FCompareToClock/d
+ **********************************************************************/
+uint32_t CGU_RealFrequencyCompare(CGU_ENTITY_T Clock, CGU_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d)
+{
+ uint32_t m1, m2, d1, d2;
+
+ /* Check Parameter */
+ if ((Clock > CGU_CLKSRC_IDIVE) || (CompareToClock > CGU_CLKSRC_IDIVE)) {
+ return CGU_ERROR_INVALID_PARAM;
+ }
+
+ /* Check for Clock Enable - Not yet implement
+ * The Comparator will hang if Clock has not been set*/
+ CGU_FrequencyMonitor(Clock, &m1, &d1);
+ CGU_FrequencyMonitor(CompareToClock, &m2, &d2);
+ *m = m1 * d2;
+ *d = d1 * m2;
+ return 0;
+}
+
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc4322/lpc43xx_cgu.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc4322/lpc43xx_cgu.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,265 @@
+/**
+ * @file lpc43xx_cgu.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup CGU CGU (Clock Generation Unit)
+ * @ingroup LPC4300CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef lpc43xx_CGU_H_
+#define lpc43xx_CGU_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC43xx.h"
+#include "lpc_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Private Macros -------------------------------------------------------------- */
+/** @defgroup CGU_Private_Macros CGU Private Macros
+ * @{
+ */
+
+/** Branch clocks from CGU_BASE_SAFE */
+#define CGU_ENTITY_NONE CGU_ENTITY_NUM
+
+/** Check bit at specific position is clear or not */
+#define ISBITCLR(x,bit) ((x&(1<<bit))^(1<<bit))
+/** Check bit at specific position is set or not */
+#define ISBITSET(x,bit) (x&(1<<bit))
+/** Set mask */
+#define ISMASKSET(x,mask) (x&mask)
+
+/** CGU number of clock source */
+#define CGU_CLKSRC_NUM (CGU_CLKSRC_IDIVE+1)
+
+/*********************************************************************//**
+ * Macro defines for CGU control mask bit definitions
+ **********************************************************************/
+/** CGU control enable mask bit */
+#define CGU_CTRL_EN_MASK 1
+/** CGU control clock-source mask bit */
+#define CGU_CTRL_SRC_MASK (0xF<<24)
+/** CGU control auto block mask bit */
+#define CGU_CTRL_AUTOBLOCK_MASK (1<<11)
+
+/*********************************************************************//**
+ * Macro defines for CGU PLL1 mask bit definitions
+ **********************************************************************/
+/** CGU PLL1 feedback select mask bit */
+#define CGU_PLL1_FBSEL_MASK (1<<6)
+/** CGU PLL1 Input clock bypass control mask bit */
+#define CGU_PLL1_BYPASS_MASK (1<<1)
+/** CGU PLL1 direct CCO output mask bit */
+#define CGU_PLL1_DIRECT_MASK (1<<7)
+
+/**
+ * @}
+ */
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup CGU_Public_Types CGU Public Types
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief CGU enumeration
+ **********************************************************************/
+/*
+ * @brief CGU clock source enumerate definition
+ */
+typedef enum {
+ /* Clock Source */
+ CGU_CLKSRC_32KHZ_OSC = 0, /**< 32KHz oscillator clock source */
+ CGU_CLKSRC_IRC, /**< IRC 12 Mhz clock source */
+ CGU_CLKSRC_ENET_RX_CLK, /**< Ethernet receive clock source */
+ CGU_CLKSRC_ENET_TX_CLK, /**< Ethernet transmit clock source */
+ CGU_CLKSRC_GP_CLKIN, /**< General purpose clock source */
+ CGU_CLKSRC_TCK, /**< TCK clock source */
+ CGU_CLKSRC_XTAL_OSC, /**< Crystal oscillator clock source*/
+ CGU_CLKSRC_PLL0, /**< PLL0 (USB0) clock source */
+ CGU_CLKSRC_PLL0_AUDIO,
+ CGU_CLKSRC_PLL1, /**< PLL1 clock source */
+ CGU_CLKSRC_IDIVA = CGU_CLKSRC_PLL1 + 3, /**< IDIVA clock source */
+ CGU_CLKSRC_IDIVB, /**< IDIVB clock source */
+ CGU_CLKSRC_IDIVC, /**< IDIVC clock source */
+ CGU_CLKSRC_IDIVD, /**< IDIVD clock source */
+ CGU_CLKSRC_IDIVE, /**< IDIVE clock source */
+
+ /* Base */
+ CGU_BASE_SAFE, /**< Base save clock (always on) for WDT */
+ CGU_BASE_USB0, /**< USB0 base clock */
+ CGU_BASE_PERIPH, /** Peripheral bus (SGPIO) */
+ CGU_BASE_USB1, /**< USB1 base clock */
+ CGU_BASE_M4, /**< ARM Cortex-M4 Core base clock */
+ CGU_BASE_SPIFI, /**< SPIFI base clock */
+ CGU_BASE_PHY_RX = CGU_BASE_SPIFI + 2, /**< Ethernet PHY Rx base clock */
+ CGU_BASE_PHY_TX, /**< Ethernet PHY Tx base clock */
+ CGU_BASE_APB1, /**< APB peripheral block #1 base clock */
+ CGU_BASE_APB3, /**< APB peripheral block #3 base clock */
+ CGU_BASE_LCD, /**< LCD base clock */
+ CGU_BASE_ENET_CSR,
+ CGU_BASE_SDIO, /**< SDIO base clock */
+ CGU_BASE_SSP0, /**< SSP0 base clock */
+ CGU_BASE_SSP1, /**< SSP1 base clock */
+ CGU_BASE_UART0, /**< UART0 base clock */
+ CGU_BASE_UART1, /**< UART1 base clock */
+ CGU_BASE_UART2, /**< UART2 base clock */
+ CGU_BASE_UART3, /**< UART3 base clock */
+ CGU_BASE_CLKOUT, /**< CLKOUT base clock */
+ CGU_BASE_APLL = CGU_BASE_CLKOUT + 5,
+ CGU_BASE_OUT0,
+ CGU_BASE_OUT1,
+ CGU_ENTITY_NUM /**< Number or clock source entity */
+} CGU_ENTITY_T;
+
+/*
+ * @brief CGU PPL0 mode enumerate definition
+ */
+typedef enum {
+ CGU_PLL0_MODE_1d = 0,
+ CGU_PLL0_MODE_1c,
+ CGU_PLL0_MODE_1b,
+ CGU_PLL0_MODE_1a
+} CGU_PLL0_MODE;
+
+/*
+ * @brief CGU peripheral enumerate definition
+ */
+typedef enum {
+ CGU_PERIPHERAL_ADC0 = 0, /**< ADC0 */
+ CGU_PERIPHERAL_ADC1, /**< ADC1 */
+ CGU_PERIPHERAL_AES, /**< AES */
+// CGU_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,
+ CGU_PERIPHERAL_APB1_BUS, /**< APB1 bus */
+ CGU_PERIPHERAL_APB3_BUS, /**< APB3 bus */
+ CGU_PERIPHERAL_CAN, /**< CAN */
+ CGU_PERIPHERAL_CREG, /**< CREG */
+ CGU_PERIPHERAL_DAC, /**< DAC */
+ CGU_PERIPHERAL_DMA, /**< DMA */
+ CGU_PERIPHERAL_EMC, /**< EMC */
+ CGU_PERIPHERAL_ETHERNET, /**< Ethernet */
+ CGU_PERIPHERAL_ETHERNET_TX, //HIDE /**< Ethernet transmit */
+ CGU_PERIPHERAL_GPIO, /**< GPIO */
+ CGU_PERIPHERAL_I2C0, /**< I2C0 */
+ CGU_PERIPHERAL_I2C1, /**< I2C1 */
+ CGU_PERIPHERAL_I2S, /**< I2S */
+ CGU_PERIPHERAL_LCD, /**< LCD */
+ CGU_PERIPHERAL_M4CORE, /**< ARM Cortex-M4 Core */
+ CGU_PERIPHERAL_M4_BUS, /**< ARM Cortex-M4 Bus */
+ CGU_PERIPHERAL_MOTOCON, /**< Motor Control */
+ CGU_PERIPHERAL_QEI, /**< QEI */
+ CGU_PERIPHERAL_RITIMER, /**< RIT Timer */
+ CGU_PERIPHERAL_SCT, /**< SCT */
+ CGU_PERIPHERAL_SCU, /**< SCU */
+ CGU_PERIPHERAL_SDIO, /**< SDIO */
+ CGU_PERIPHERAL_SPIFI, /**< SPIFI */
+ CGU_PERIPHERAL_SSP0, /**< SSP0 */
+ CGU_PERIPHERAL_SSP1, /**< SSP1 */
+ CGU_PERIPHERAL_TIMER0, /**< TIMER 0 */
+ CGU_PERIPHERAL_TIMER1, /**< TIMER 1 */
+ CGU_PERIPHERAL_TIMER2, /**< TIMER 2 */
+ CGU_PERIPHERAL_TIMER3, /**< TIMER 3 */
+ CGU_PERIPHERAL_UART0, /**< UART0 */
+ CGU_PERIPHERAL_UART1, /**< UART1 */
+ CGU_PERIPHERAL_UART2, /**< UART2 */
+ CGU_PERIPHERAL_UART3, /**< UART3 */
+ CGU_PERIPHERAL_USB0, /**< USB0 */
+ CGU_PERIPHERAL_USB1, /**< USB1 */
+ CGU_PERIPHERAL_WWDT, /**< WWDT */
+ CGU_PERIPHERAL_NUM
+} CGU_PERIPHERAL_T;
+
+/**
+ * @brief CGU error status enumerate definition
+ */
+typedef enum {
+ CGU_ERROR_SUCCESS = 0,
+ CGU_ERROR_CONNECT_TOGETHER,
+ CGU_ERROR_INVALID_ENTITY,
+ CGU_ERROR_INVALID_CLOCK_SOURCE,
+ CGU_ERROR_INVALID_PARAM,
+ CGU_ERROR_FREQ_OUTOF_RANGE
+} CGU_ERROR;
+
+/********************************************************************//**
+* @brief CGU structure definitions
+**********************************************************************/
+/*
+ * @brief CGU peripheral clock structure
+ */
+typedef struct {
+ uint8_t RegBaseEntity; /**< Base register address */
+ uint16_t RegBranchOffset; /**< Branch register offset */
+ uint8_t PerBaseEntity; /**< Base peripheral address */
+ uint16_t PerBranchOffset; /**< Base peripheral offset */
+ uint8_t next; /**< Pointer to next structure */
+} CGU_PERIPHERAL_S;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup CGU_Public_Functions CGU Public Functions
+ * @{
+ */
+
+/** Clock generate initialize/de-initialize */
+uint32_t CGU_Init(uint32_t wantedFreq);
+uint32_t CGU_DeInit(void);
+
+/** Clock Generator and Clock Control */
+uint32_t CGU_ConfigPWR(CGU_PERIPHERAL_T PPType, FunctionalState en);
+uint32_t CGU_GetPCLKFrequency(CGU_PERIPHERAL_T Clock);
+
+/** Clock Source and Base Clock operation */
+uint32_t CGU_SetXTALOSC(uint32_t ClockFrequency);
+uint32_t CGU_SetDIV(CGU_ENTITY_T SelectDivider, uint32_t divisor);
+uint32_t CGU_SetPLL0(void);
+uint32_t CGU_SetPLL0audio(void);
+uint32_t CGU_SetPLL1(uint32_t mult);
+uint32_t CGU_EnableEntity(CGU_ENTITY_T ClockEntity, uint32_t en);
+uint32_t CGU_EntityConnect(CGU_ENTITY_T ClockSource, CGU_ENTITY_T ClockEntity);
+uint32_t CGU_GetBaseStatus(CGU_ENTITY_T Base);
+void CGU_UpdateClock(void);
+uint32_t CGU_RealFrequencyCompare(CGU_ENTITY_T Clock, CGU_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* lpc43xx_CGU_H_ */
+
+/**
+ * @}
+ */
+
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc4322/lpc43xx_scu.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc4322/lpc43xx_scu.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,87 @@
+/**
+ * @file lpc43xx_scu.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC43xx.h" /* lpc43xx definitions */
+#include "lpc_types.h"
+#include "lpc43xx_scu.h"
+
+/* Pin modes
+* =========
+* The EPUN and EPD bits in the SFS registers allow the selection of weak on-chip
+* pull-up or pull-down resistors with a typical value of 50 kOhm for each pin or the
+* selection of the repeater mode.
+* The possible on-chip resistor configurations are pull-up enabled, pull-down enabled, or no
+* pull-up/pull-down. The default value is pull-up enabled.
+*
+* The repeater mode enables the pull-up resistor if the pin is at a logic HIGH and enables
+* the pull-down resistor if the pin is at a logic LOW. This causes the pin to retain its last
+* known state if it is configured as an input and is not driven externally. Repeater mode may
+* typically be used to prevent a pin from floating (and potentially using significant power if it
+* floats to an indeterminate state) if it is temporarily not driven.
+* Repeater mode is enabled when both pull-up and pull-down are enabled.
+*
+* To be able to receive a digital signal, the input buffer must be enabled through bit EZI in
+* the pin configuration registers. By default, the input buffer is disabled.
+* For pads that support both a digital and an analog function, the input buffer must be
+* disabled before enabling the analog function.
+*
+* All digital pins support a programmable glitch filter (bit ZIF), which can be switched on or
+* off. By default, the glitch filter is on. The glitch filter should be disabled for
+* clocking signals with frequencies higher than 30 MHz.
+*
+* Normal-drive and high-speed pins support a programmable slew rate (bit EHS) to select
+* between lower noise and low speed or higher noise and high speed . The typical
+* frequencies supported are 50 MHz/80 MHz for normal-drive pins and 75 MHz/180 MHz for
+* high-speed pins.
+*/
+
+/*********************************************************************//**
+ * @brief Configure pin function
+ * @param[in] port Port number, should be: 0..15
+ * @param[in] pin Pin number, should be: 0..31
+ * @param[in] mode Pin mode, should be:
+ * - MD_PUP :Pull-up enabled
+ * - MD_BUK :Plain input
+ * - MD_PLN :Repeater mode
+ * - MD_PDN :Pull-down enabled
+ * - MD_EHS :Slew rate
+ * - MD_EZI :Input buffer enable
+ * - MD_ZI :Glitch filter enabled
+ * - MD_EHD0 :High drive 8 mA
+ * - MD_EHD1 :High drive 14 mA
+ * - MD_EHD2 :High drive 20 mA
+ * @param[in] func Function mode, should be:
+ * - FUNC0 :Function 0
+ * - FUNC1 :Function 1
+ * - FUNC2 :Function 2
+ * - FUNC3 :Function 3
+ * - FUNC4 :Function 4
+ * - FUNC5 :Function 5
+ * - FUNC6 :Function 6
+ * - FUNC7 :Function 7
+ * @return None
+ **********************************************************************/
+void scu_pinmux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func)
+{
+ uint32_t *scu_base = (uint32_t *)(LPC_SCU_BASE);
+ scu_base[(PORT_OFFSET * port + PIN_OFFSET * pin) / 4] = mode + func;
+} /* scu_pinmux */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc4322/lpc43xx_scu.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc4322/lpc43xx_scu.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,125 @@
+/**
+ * @file lpc43xx_scu.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup SCU SCU (System Control Unit)
+ * @ingroup LPC4300CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef __SCU_H
+#define __SCU_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Private macros ------------------------------------------------------------- */
+/** @defgroup SCT_Private_Macros SCT Private Macros
+ * @{
+ */
+
+/** Port offset definition */
+#define PORT_OFFSET 0x80
+/** Pin offset definition */
+#define PIN_OFFSET 0x04
+
+/* Pin mode defines, following partly a definition from older chip architectures */
+#define MD_PUP (0x0 << 3)
+#define MD_BUK (0x1 << 3)
+#define MD_PLN (0x2 << 3)
+#define MD_PDN (0x3 << 3)
+#define MD_EHS (0x1 << 5)
+#define MD_EZI (0x1 << 6)
+#define MD_ZI (0x1 << 7)
+#define MD_EHD0 (0x1 << 8)
+#define MD_EHD1 (0x1 << 9)
+#define MD_EHD2 (0x3 << 8)
+#define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
+
+
+/* Pin mode defines, more in line with the definitions in the LPC1800/4300 user manual */
+/* Defines for SFSPx_y pin configuration registers */
+#define PDN_ENABLE (1 << 3) // Pull-down enable
+#define PDN_DISABLE (0 << 3) // Pull-down disable
+#define PUP_ENABLE (0 << 4) // Pull-up enable
+#define PUP_DISABLE (1 << 4) // Pull-up disable
+#define SLEWRATE_SLOW (0 << 5) // Slew rate for low noise with medium speed
+#define SLEWRATE_FAST (1 << 5) // Slew rate for medium noise with fast speed
+#define INBUF_ENABLE (1 << 6) // Input buffer
+#define INBUF_DISABLE (0 << 6) // Input buffer
+#define FILTER_ENABLE (0 << 7) // Glitch filter (for signals below 30MHz)
+#define FILTER_DISABLE (1 << 7) // No glitch filter (for signals above 30MHz)
+#define DRIVE_8MA (1 << 8) // Drive strength of 8mA
+#define DRIVE_14MA (1 << 9) // Drive strength of 14mA
+#define DRIVE_20MA (3 << 8) // Drive strength of 20mA
+
+
+/* Configuration examples for various I/O pins */
+#define EMC_IO (PUP_ENABLE | PDN_ENABLE | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
+#define LCD_PINCONFIG (PUP_DISABLE | PDN_DISABLE | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
+#define CLK_IN (PUP_ENABLE | PDN_ENABLE | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
+#define CLK_OUT (PUP_ENABLE | PDN_ENABLE | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
+#define GPIO_PUP (PUP_ENABLE | PDN_DISABLE | SLEWRATE_SLOW | INBUF_ENABLE | FILTER_ENABLE )
+#define GPIO_PDN (PUP_DISABLE | PDN_ENABLE | SLEWRATE_SLOW | INBUF_ENABLE | FILTER_ENABLE )
+#define GPIO_NOPULL (PUP_DISABLE | PDN_DISABLE | SLEWRATE_SLOW | INBUF_ENABLE | FILTER_ENABLE )
+#define UART_RX_TX (PUP_DISABLE | PDN_ENABLE | SLEWRATE_SLOW | INBUF_ENABLE | FILTER_ENABLE )
+#define SSP_IO (PUP_ENABLE | PDN_ENABLE | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
+
+
+/* Pin function */
+#define FUNC0 0x0 /** Function 0 */
+#define FUNC1 0x1 /** Function 1 */
+#define FUNC2 0x2 /** Function 2 */
+#define FUNC3 0x3 /** Function 3 */
+#define FUNC4 0x4
+#define FUNC5 0x5
+#define FUNC6 0x6
+#define FUNC7 0x7
+/**
+ * @}
+ */
+
+#define LPC_SCU_PIN(po, pi) (*(volatile int *) (LPC_SCU_BASE + ((po) * 0x80) + ((pi) * 0x4)) )
+#define LPC_SCU_CLK(c) (*(volatile int *) (LPC_SCU_BASE + 0xC00 + ((c) * 0x4)) )
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup SCU_Public_Functions SCU Public Functions
+ * @{
+ */
+
+void scu_pinmux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end __SCU_H */
+
+/**
+ * @}
+ */
+
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc4322/lpc_types.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc4322/lpc_types.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,160 @@
+/**
+ * @file lpc_types.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef LPC_TYPES_H
+#define LPC_TYPES_H
+
+#include "stdint.h"
+
+/**
+ * @brief Boolean Type definition
+ */
+typedef enum {FALSE = 0, TRUE = !FALSE} Bool;
+
+/**
+ * @brief Flag Status and Interrupt Flag Status type definition
+ */
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
+#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET))
+
+/**
+ * @brief Functional State Definition
+ */
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE))
+
+/**
+ * @ Status type definition
+ */
+typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
+
+
+/**
+ * Read/Write transfer type mode (Block or non-block)
+ */
+typedef enum {
+ NONE_BLOCKING = 0, /**< None Blocking type */
+ BLOCKING, /**< Blocking type */
+} TRANSFER_BLOCK_Type;
+
+
+/** Pointer to Function returning Void (any number of parameters) */
+typedef void (*PFV)();
+
+/** Pointer to Function returning int32_t (any number of parameters) */
+typedef int32_t(*PFI)();
+
+/* _BIT(n) sets the bit at position "n"
+ * _BIT(n) is intended to be used in "OR" and "AND" expressions:
+ * e.g., "(_BIT(3) | _BIT(7))".
+ */
+#undef _BIT
+/* Set bit macro */
+#define _BIT(n) (1<<(n))
+
+/* _SBF(f,v) sets the bit field starting at position "f" to value "v".
+ * _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
+ * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
+ */
+#undef _SBF
+/* Set bit field macro */
+#define _SBF(f,v) ((v)<<(f))
+
+/* _BITMASK constructs a symbol with 'field_width' least significant
+ * bits set.
+ * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
+ * The symbol is intended to be used to limit the bit field width
+ * thusly:
+ * <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
+ * If "any_expression" results in a value that is larger than can be
+ * contained in 'x' bits, the bits above 'x - 1' are masked off. When
+ * used with the _SBF example above, the example would be written:
+ * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
+ * This ensures that the value written to a_reg is no wider than
+ * 16 bits, and makes the code easier to read and understand.
+ */
+#undef _BITMASK
+/* Bitmask creation macro */
+#define _BITMASK(field_width) ( _BIT(field_width) - 1)
+
+/* NULL pointer */
+#ifndef NULL
+#define NULL ((void*) 0)
+#endif
+
+/* Number of elements in an array */
+#define NELEMENTS(array) (sizeof (array) / sizeof (array[0]))
+
+/* Static data/function define */
+#define STATIC static
+/* External data/function define */
+#define EXTERN extern
+
+#if !defined(MAX)
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+#if !defined(MIN)
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+/** SMA type for character type */
+typedef char CHAR;
+
+/** SMA type for 8 bit unsigned value */
+typedef uint8_t UNS_8;
+
+/** SMA type for 8 bit signed value */
+typedef int8_t INT_8;
+
+/** SMA type for 16 bit unsigned value */
+typedef uint16_t UNS_16;
+
+/** SMA type for 16 bit signed value */
+typedef int16_t INT_16;
+
+/** SMA type for 32 bit unsigned value */
+typedef uint32_t UNS_32;
+
+/** SMA type for 32 bit signed value */
+typedef int32_t INT_32;
+
+/** SMA type for 64 bit signed value */
+typedef int64_t INT_64;
+
+/** SMA type for 64 bit unsigned value */
+typedef uint64_t UNS_64;
+
+/** 32 bit boolean type */
+typedef Bool BOOL_32;
+
+/** 16 bit boolean type */
+typedef Bool BOOL_16;
+
+/** 8 bit boolean type */
+typedef Bool BOOL_8;
+
+#ifdef __CC_ARM
+#define INLINE __inline
+#else
+#define INLINE inline
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc4322/read_uid.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc4322/read_uid.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,48 @@
+/**
+ * @file read_uid.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "read_uid.h"
+#include "cortex_m.h"
+
+#define IAP_LOCATION *(volatile unsigned int *)(0x10400100)
+static uint32_t command[5];
+static uint32_t result[5];
+typedef void (*IAP)(uint32_t[], uint32_t[]);
+
+void read_unique_id(uint32_t *id)
+{
+#if defined(INTERNAL_FLASH)
+ cortex_int_state_t local_state = cortex_int_get_and_disable();
+
+ // readUID IAP call
+ IAP iap_entry = (IAP)IAP_LOCATION;
+ command[0] = 58;
+ iap_entry(command, result);
+ *id = result[1] ^ result[2] ^ result[3] ^ result[4];
+
+ cortex_int_restore(local_state);
+#else
+ // IAP commands are only supported for parts with on-chip flash.
+ (void)command;
+ (void)result;
+ *id = 0xdeadbeef;
+#endif
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc4322/system_LPC43xx.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc4322/system_LPC43xx.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,97 @@
+/**********************************************************************
+* $Id$ system_lpc43xx.c 2012-05-21
+*//**
+* @file system_lpc43xx.c
+* @brief Cortex-M3 Device System Source File for NXP lpc43xx Series.
+* @version 1.0
+* @date 21. May. 2011
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+#include "LPC43xx.h"
+#include "fpu_enable.h"
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __IRC (12000000UL) /* IRC Oscillator frequency */
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = 96000000; /* System Clock Frequency (Core Clock)*/
+
+extern uint32_t __Vectors;
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit(void)
+{
+ // Set up Cortex_M3 or M4 VTOR register to point to vector table
+ SCB->VTOR = (unsigned int)&__Vectors;
+
+ fpuEnable();
+
+ // In case we are running from internal flash, we configure the flash
+ // accelerator.
+#define FLASH_ACCELERATOR_SPEED 6
+ {
+ uint32_t *MAM, t;
+ // Set up flash controller for both banks
+ // Bank A
+ MAM = (uint32_t *)(LPC_CREG_BASE + 0x120);
+ t = *MAM;
+ t &= ~(0xF << 12);
+ *MAM = t | (FLASH_ACCELERATOR_SPEED << 12);
+ // Bank B
+ MAM = (uint32_t *)(LPC_CREG_BASE + 0x124);
+ t = *MAM;
+ t &= ~(0xF << 12);
+ *MAM = t | (FLASH_ACCELERATOR_SPEED << 12);
+ }
+}
+
+void SystemReset(void)
+{
+ /* Ensure all outstanding memory accesses included buffered write are completed before reset */
+ __DSB();
+
+ LPC_WWDT->MOD |= (1 << 1);
+ LPC_WWDT->MOD |= (1 << 0);
+ LPC_WWDT->FEED = 0xAA;
+ LPC_WWDT->FEED = 0x55;
+
+ /* Ensure completion of memory access */
+ __DSB();
+
+ /* wait until reset */
+ while(1);
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc4322/system_LPC43xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc4322/system_LPC43xx.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,50 @@
+/**********************************************************************
+* $Id$ system_LPC43xx.h 2011-06-02
+*//**
+* @file system_LPC43xx.h
+* @brief Cortex-M3 Device System Header File for NXP lpc43xx Series.
+* @version 1.0
+* @date 02. June. 2011
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+#ifndef __SYSTEM_lpc43xx_H
+#define __SYSTEM_lpc43xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_lpc43xx_H */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc4322/uart.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc4322/uart.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,365 @@
+/**
+ * @file uart.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "LPC43xx.h"
+#include "uart.h"
+#include "lpc43xx_cgu.h"
+#include "lpc43xx_scu.h"
+#include "util.h"
+#include "circ_buf.h"
+#include "settings.h" // for config_get_overflow_detect
+
+static uint32_t baudrate;
+static uint32_t dll;
+static uint32_t tx_in_progress;
+
+extern uint32_t SystemCoreClock;
+
+#define RX_OVRF_MSG "<DAPLink:Overflow>\n"
+#define RX_OVRF_MSG_SIZE (sizeof(RX_OVRF_MSG) - 1)
+#define BUFFER_SIZE (512)
+
+circ_buf_t write_buffer;
+uint8_t write_buffer_data[BUFFER_SIZE];
+circ_buf_t read_buffer;
+uint8_t read_buffer_data[BUFFER_SIZE];
+
+static int32_t reset(void);
+
+#define UART_IRQn USART0_IRQn
+#define LPC_USART LPC_USART0
+#define UART_IRQHandler UART0_IRQHandler
+
+// UART Control Pin P2_2: GPIO5[2]
+#define PORT_UARTCTRL 5
+#define PIN_UARTCTRL_IN_BIT 2
+#define PIN_UARTCTRL (1<<PIN_UARTCTRL_IN_BIT)
+
+
+int32_t uart_initialize(void)
+{
+ NVIC_DisableIRQ(UART_IRQn);
+
+ // The baudrate calculations require the UART to be clocked as SystemCoreClock
+ CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_UART0);
+ CGU_EnableEntity(CGU_BASE_UART0, ENABLE);
+ scu_pinmux(2, 0, UART_RX_TX, FUNC1); /* P2_0: U0_TXD */
+ scu_pinmux(2, 1, UART_RX_TX, FUNC1); /* P2_1: U0_RXD */
+
+ scu_pinmux(2, 2, GPIO_NOPULL, FUNC4); /* UARTCTRL: GPIO5[2] */
+ // Control target's UART RX:
+ // UARTCTRL high: The LPC1549 gets uart input from the LPC4322
+ // UARTCTRL low: The LPC1549 gets uart input from the ISP_RX on the pinlist
+ LPC_GPIO_PORT->CLR[PORT_UARTCTRL] = PIN_UARTCTRL;
+ LPC_GPIO_PORT->DIR[PORT_UARTCTRL] |= (PIN_UARTCTRL);
+ // enable FIFOs (trigger level 1) and clear them
+ LPC_USART->FCR = 0x87;
+ // Transmit Enable
+ LPC_USART->TER = 0x01;
+ // reset uart
+ reset();
+ // enable rx and tx interrupt
+ LPC_USART->IER |= (1 << 0) | (1 << 1);
+ NVIC_EnableIRQ(UART_IRQn);
+ return 1;
+}
+
+int32_t uart_uninitialize(void)
+{
+ // disable interrupt
+ LPC_USART->IER &= ~(0x7);
+ NVIC_DisableIRQ(UART_IRQn);
+ // reset uart
+ reset();
+ return 1;
+}
+
+int32_t uart_reset(void)
+{
+ // disable interrupt
+ NVIC_DisableIRQ(UART_IRQn);
+ // reset uart
+ reset();
+ // enable interrupt
+ NVIC_EnableIRQ(UART_IRQn);
+ return 1;
+}
+
+int32_t uart_set_configuration(UART_Configuration *config)
+{
+ uint8_t DivAddVal = 0;
+ uint8_t MulVal = 1;
+ uint8_t mv, data_bits = 8, parity, stop_bits = 0;
+ // disable interrupt
+ NVIC_DisableIRQ(UART_IRQn);
+ // reset uart
+ reset();
+ baudrate = config->Baudrate;
+ // Compute baud rate dividers
+ mv = 15;
+ dll = util_div_round_down(SystemCoreClock, 16 * config->Baudrate);
+ DivAddVal = util_div_round(SystemCoreClock * mv, dll * config->Baudrate * 16) - mv;
+ // set LCR[DLAB] to enable writing to divider registers
+ LPC_USART->LCR |= (1 << 7);
+ // set divider values
+ LPC_USART->DLM = (dll >> 8) & 0xFF;
+ LPC_USART->DLL = (dll >> 0) & 0xFF;
+ LPC_USART->FDR = (uint32_t) DivAddVal << 0
+ | (uint32_t) MulVal << 4;
+ // clear LCR[DLAB]
+ LPC_USART->LCR &= ~(1 << 7);
+
+ // set data bits, stop bits, parity
+ if ((config->DataBits < 5) || (config->DataBits > 8)) {
+ data_bits = 8;
+ }
+
+ data_bits -= 5;
+
+ if (config->StopBits != 1 && config->StopBits != 2) {
+ stop_bits = 1;
+ }
+
+ stop_bits -= 1;
+
+ switch (config->Parity) {
+ case UART_PARITY_ODD:
+ parity = 0x01;
+ break; // Parity Odd
+
+ case UART_PARITY_EVEN:
+ parity = 0x03;
+ break; // Parity Even
+
+ case UART_PARITY_MARK:
+ parity = 0x05;
+ break; // Parity Mark
+
+ case UART_PARITY_SPACE:
+ parity = 0x07;
+ break; // Parity Space
+
+ case UART_PARITY_NONE: // Parity None
+ default:
+ parity = 0x00;
+ break;
+ }
+
+ LPC_USART->LCR = (data_bits << 0)
+ | (stop_bits << 2)
+ | (parity << 3);
+ // Enable UART interrupt
+ NVIC_EnableIRQ(UART_IRQn);
+ return 1;
+}
+
+int32_t uart_get_configuration(UART_Configuration *config)
+{
+ float br;
+ uint32_t lcr;
+ // line control parameter
+ lcr = LPC_USART->LCR;
+ // baudrate
+ br = SystemCoreClock / (dll * 16);
+
+ // If inside +/- 2% tolerance
+ if (((br * 100) <= (baudrate * 102)) && ((br * 100) >= (baudrate * 98))) {
+ config->Baudrate = baudrate;
+ } else {
+ config->Baudrate = br;
+ }
+
+ // get data bits
+ switch ((lcr >> 0) & 3) {
+ case 0:
+ config->DataBits = UART_DATA_BITS_5;
+ break;
+
+ case 1:
+ config->DataBits = UART_DATA_BITS_6;
+ break;
+
+ case 2:
+ config->DataBits = UART_DATA_BITS_7;
+ break;
+
+ case 3:
+ config->DataBits = UART_DATA_BITS_8;
+ break;
+
+ default:
+ return 0;
+ }
+
+ // get parity
+ switch ((lcr >> 3) & 7) {
+ case 0:
+ case 2:
+ case 4:
+ case 6:
+ config->Parity = UART_PARITY_NONE;
+ break;
+
+ case 1:
+ config->Parity = UART_PARITY_ODD;
+ break;
+
+ case 3:
+ config->Parity = UART_PARITY_MARK;
+ break;
+
+ case 5:
+ config->Parity = UART_PARITY_EVEN;
+ break;
+
+ case 7:
+ config->Parity = UART_PARITY_SPACE;
+ break;
+
+ default:
+ return 0;
+ }
+
+ // get stop bits
+ switch ((lcr >> 2) & 1) {
+ case 0:
+ config->StopBits = UART_STOP_BITS_1;
+ break;
+
+ case 1:
+ config->StopBits = UART_STOP_BITS_2;
+ break;
+
+ default:
+ return 0;
+ }
+
+ // get flow control
+ config->FlowControl = UART_FLOW_CONTROL_NONE;
+ return 1;
+}
+
+int32_t uart_write_free(void)
+{
+ return circ_buf_count_free(&write_buffer);
+}
+
+int32_t uart_write_data(uint8_t *data, uint16_t size)
+{
+ uint32_t cnt;
+
+ cnt = circ_buf_write(&write_buffer, data, size);
+
+ // Make sure that the target LPC1549 can receive the output
+ LPC_GPIO_PORT->SET[PORT_UARTCTRL] = PIN_UARTCTRL;
+
+ // enable THRE interrupt
+ LPC_USART->IER |= (1 << 1);
+
+ if (!tx_in_progress) {
+ // force THRE interrupt to start
+ NVIC_SetPendingIRQ(UART_IRQn);
+ }
+
+ return cnt;
+}
+
+
+int32_t uart_read_data(uint8_t *data, uint16_t size)
+{
+ return circ_buf_read(&read_buffer, data, size);
+}
+
+void uart_enable_flow_control(bool enabled)
+{
+ // Flow control not implemented for this platform
+}
+
+void UART_IRQHandler(void)
+{
+ uint32_t iir;
+ // read interrupt status
+ iir = LPC_USART->IIR;
+
+ // handle character to transmit
+ if (circ_buf_count_used(&write_buffer) > 0) {
+ // if THR is empty
+ if (LPC_USART->LSR & (1 << 5)) {
+ LPC_USART->THR = circ_buf_pop(&write_buffer);
+ tx_in_progress = 1;
+ }
+
+ } else if (tx_in_progress) {
+ tx_in_progress = 0;
+ // Turn back input for the target LPC1549 to it's pinlist
+ LPC_GPIO_PORT->CLR[PORT_UARTCTRL] = PIN_UARTCTRL;
+ // disable THRE interrupt
+ LPC_USART->IER &= ~(1 << 1);
+ }
+
+ // handle received character
+ if (((iir & 0x0E) == 0x04) || // Rx interrupt (RDA)
+ ((iir & 0x0E) == 0x0C)) { // Rx interrupt (CTI)
+ while (LPC_USART->LSR & 0x01) {
+ uint32_t free;
+ uint8_t data;
+
+ data = LPC_USART->RBR;
+ free = circ_buf_count_free(&read_buffer);
+ if (free > RX_OVRF_MSG_SIZE) {
+ circ_buf_push(&read_buffer, data);
+ } else if (config_get_overflow_detect()) {
+ if (RX_OVRF_MSG_SIZE == free) {
+ circ_buf_write(&read_buffer, (uint8_t*)RX_OVRF_MSG, RX_OVRF_MSG_SIZE);
+ } else {
+ // Drop newest
+ }
+ } else {
+ // Drop oldest
+ circ_buf_pop(&read_buffer);
+ circ_buf_push(&read_buffer, data);
+ }
+ }
+ }
+
+ LPC_USART->LSR;
+}
+
+static int32_t reset(void)
+{
+ // Reset FIFOs
+ LPC_USART->FCR = 0x06;
+ baudrate = 0;
+ dll = 0;
+ tx_in_progress = 0;
+
+ circ_buf_init(&write_buffer, write_buffer_data, sizeof(write_buffer_data));
+ circ_buf_init(&read_buffer, read_buffer_data, sizeof(read_buffer_data));
+
+ // Ensure a clean start, no data in either TX or RX FIFO
+ while ((LPC_USART->LSR & ((1 << 5) | (1 << 6))) != ((1 << 5) | (1 << 6)));
+
+ while (LPC_USART->LSR & 0x01) {
+ LPC_USART->RBR; // Dump data from RX FIFO
+ }
+
+ return 1;
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc4322/usb_buf.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/nxp/lpc4322/usb_buf.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,29 @@ +/** + * @file usb_buf.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef USB_BUF_H +#define USB_BUF_H + +#include "stdint.h" + +uint32_t usb_buffer[512 / 4]; + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc4322/usb_config.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/nxp/lpc4322/usb_config.c Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,557 @@ +/** + * @file usb_config.c + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "util.h" + +// <e> USB Device +// <i> Enable the USB Device functionality +#define USBD_ENABLE 1 +#define USBD_RTX_CORE_STACK 0 +#define USBD_RTX_DEVICE_STACK 0 +#define USBD_RTX_ENDPOINT0_STACK 0 + +// <o0.0> High-speed +// <i> Enable high-speed functionality (if device supports it) +#define USBD_HS_ENABLE 0 +#if (defined(WEBUSB_INTERFACE) || defined(WINUSB_INTERFACE) || defined(BULK_ENDPOINT)) +#define USBD_BOS_ENABLE 1 +#else +#define USBD_BOS_ENABLE 0 +#endif +// <h> Device Settings +// <i> These settings affect Device Descriptor +// <o0> Power +// <i> Default Power Setting +// <0=> Bus-powered +// <1=> Self-powered +// <o1> Max Endpoint 0 Packet Size +// <i> Maximum packet size for endpoint zero (bMaxPacketSize0) +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes +// <o2.0..15> Vendor ID <0x0000-0xFFFF> +// <i> Vendor ID assigned by the USB-IF (idVendor) +// <o3.0..15> Product ID <0x0000-0xFFFF> +// <i> Product ID assigned by the manufacturer (idProduct) +// <o4.0..15> Device Release Number <0x0000-0xFFFF> +// <i> Device release number in binary-coded decimal (bcdDevice) +// </h> +#define USBD_POWER 0 +#define USBD_MAX_PACKET0 64 +#define USBD_DEVDESC_IDVENDOR 0x0D28 +#define USBD_DEVDESC_IDPRODUCT 0x0204 +#define USBD_DEVDESC_BCDDEVICE 0x0100 + +// <h> Configuration Settings +// <i> These settings affect Configuration Descriptor +// <o0.5> Remote Wakeup +// <i> Configuration support for remote wakeup (D5: of bmAttributes) +// <o1.0..7> Maximum Power Consumption (in mA) <0-510><#/2> +// <i> Maximum power consumption of the USB device +// <i> from the bus in this specific configuration +// <i> when the device is fully operational (bMaxPower) +// </h> +#define USBD_CFGDESC_BMATTRIBUTES 0x80 +#define USBD_CFGDESC_BMAXPOWER 0xFA + +// <h> String Settings +// <i> These settings affect String Descriptor +// <o0.0..15> Language ID <0x0000-0xFCFF> +// <i> English (United States) = 0x0409 +// <s0.126> Manufacturer String +// <i> String descriptor describing manufacturer +// <s1.126> Product String +// <i> String descriptor describing product +// <e1.0> Serial Number +// <i> Enable serial number string +// <i> If disabled serial number string will not be assigned to the USB Device +// <s2.126> Serial Number String +// <i> String descriptor describing device's serial number +// </e> +// </h> +#define USBD_STRDESC_LANGID 0x0409 +#define USBD_STRDESC_MAN L"ARM" +#ifndef USB_PROD_STR +#define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" +#else +#define _TOWIDE(x) L ## #x +#define TOWIDE(x) _TOWIDE(x) +#define USBD_STRDESC_PROD TOWIDE(USB_PROD_STR) +#endif +#define USBD_STRDESC_SER_ENABLE 1 +#define USBD_STRDESC_SER L"0001A0000000" + +// <e0> Class Support +// <i> Enables USB Device Class specific Requests +#define USBD_CLASS_ENABLE 1 + +// <e0.0> Human Interface Device (HID) +// <i> Enable class support for Human Interface Device (HID) +// <h> Interrupt Endpoint Settings +// <o1.0..4> Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o2.0..4> Interrupt Out Endpoint Number <0=> Not used <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <i> If interrupt out endpoint is not used select "Not used" +// <h> Endpoint Settings +// <o3.0..7> Maximum Endpoint Packet Size (in bytes) <0-64> +// <o4.0..7> Endpoint polling Interval (in ms) <1-255> +// <e5> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o6.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o6.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// <o7.0..7> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// </e> +// </h> +// </h> +// <h> Human Interface Device Settings +// <i> Device specific settings +// <s0.126> HID Interface String +// <o8.0..4> Number of Input Reports <1-32> +// <o9.0..4> Number of Output Reports <1-32> +// <o10.0..15> Maximum Input Report Size (in bytes) <1-65535> +// <o11.0..15> Maximum Output Report Size (in bytes) <1-65535> +// <o12.0..15> Maximum Feature Report Size (in bytes) <1-65535> +// </h> +// </e> +#ifndef HID_ENDPOINT +#define HID_ENDPOINT 0 +#else +#define HID_ENDPOINT 1 +#endif + +#ifndef WEBUSB_INTERFACE +#define WEBUSB_INTERFACE 0 +#else +#define WEBUSB_INTERFACE 1 +#endif + +#define USBD_HID_ENABLE HID_ENDPOINT +#define USBD_HID_EP_INTIN 1 +#define USBD_HID_EP_INTOUT 1 + +#define USBD_HID_ENABLE HID_ENDPOINT +#define USBD_HID_EP_INTIN_STACK 0 +#define USBD_HID_WMAXPACKETSIZE 64 +#define USBD_HID_BINTERVAL 1 +#define USBD_HID_HS_ENABLE 0 +#define USBD_HID_HS_WMAXPACKETSIZE 64 +#define USBD_HID_HS_BINTERVAL 6 +#define USBD_HID_STRDESC L"CMSIS-DAP v1" +#define USBD_WEBUSB_STRDESC L"WebUSB: CMSIS-DAP" +#define USBD_HID_INREPORT_NUM 1 +#define USBD_HID_OUTREPORT_NUM 1 +#define USBD_HID_INREPORT_MAX_SZ 64 +#define USBD_HID_OUTREPORT_MAX_SZ 64 +#define USBD_HID_FEATREPORT_MAX_SZ 1 + +// <e0.0> Mass Storage Device (MSC) +// <i> Enable class support for Mass Storage Device (MSC) +// <h> Bulk Endpoint Settings +// <o1.0..4> Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o2.0..4> Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o3> Maximum Packet Size <1-1024> +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5> Maximum Packet Size <1-1024> +// <o6> Maximum NAK Rate <0-255> +// </e> +// </h> +// </h> +// <h> Mass Storage Device Settings +// <i> Device specific settings +// <s0.126> MSC Interface String +// <h> Inquiry Data +// <s1.8> Vendor Identification +// <s2.16> Product Identification +// <s3.4> Product Revision Level +// </h> +// </h> +// </e> +#ifndef MSC_ENDPOINT +#define MSC_ENDPOINT 0 +#else +#define MSC_ENDPOINT 1 +#endif +#define USBD_MSC_ENABLE MSC_ENDPOINT +#define USBD_MSC_EP_BULKIN 2 +#define USBD_MSC_EP_BULKOUT 2 +#define USBD_MSC_EP_BULKIN_STACK 0 +#define USBD_MSC_WMAXPACKETSIZE 64 +#define USBD_MSC_HS_ENABLE 0 +#define USBD_MSC_HS_WMAXPACKETSIZE 512 +#define USBD_MSC_HS_BINTERVAL 0 +#define USBD_MSC_STRDESC L"USB_MSC" +// Make sure changes to USBD_MSC_INQUIRY_DATA are coordinated with mbed-ls +// since this is used to detect DAPLink drives +#define USBD_MSC_INQUIRY_DATA "MBED " \ + "VFS " \ + "0.1" + +// <e0.0> Audio Device (ADC) +// <i> Enable class support for Audio Device (ADC) +// <h> Isochronous Endpoint Settings +// <o1.0..4> Isochronous Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o2.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o3.0..10> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o5.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// </e> +// </h> +// </h> +// <h> Audio Device Settings +// <i> Device specific settings +// <s0.126> Audio Control Interface String +// <s1.126> Audio Streaming (Zero Bandwidth) Interface String +// <s2.126> Audio Streaming (Operational) Interface String +// <o6.0..7> Audio Subframe Size (in bytes) <0-255> +// <o7.0..7> Sample Resolution (in bits) <0-255> +// <o8.0..23> Sample Frequency (in Hz) <0-16777215> +// <o9> Packet Size (in bytes) <1-256> +// <o10> Packet Count <1-16> +// </h> +// </e> +#define USBD_ADC_ENABLE 0 +#define USBD_ADC_EP_ISOOUT 3 +#define USBD_ADC_WMAXPACKETSIZE 64 +#define USBD_ADC_BINTERVAL 1 +#define USBD_ADC_HS_ENABLE 0 +#define USBD_ADC_HS_WMAXPACKETSIZE 64 +#define USBD_ADC_CIF_STRDESC L"USB_ADC" +#define USBD_ADC_SIF1_STRDESC L"USB_ADC1" +#define USBD_ADC_SIF2_STRDESC L"USB_ADC2" +#define USBD_ADC_BSUBFRAMESIZE 2 +#define USBD_ADC_BBITRESOLUTION 16 +#define USBD_ADC_TSAMFREQ 32000 +#define USBD_ADC_CFG_P_S 32 +#define USBD_ADC_CFG_P_C 1 + +// <e0> Communication Device (CDC) - Abstract Control Model (ACM) +// <i> Enable class support for Communication Device (CDC) - Abstract Control Model (ACM) +// <h> Interrupt Endpoint Settings +// <o1.0..4> Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o2.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o3.0..10> Endpoint polling Interval (in ms) <0-255> +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o5.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// <o6.0..10> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// </e4> +// </h> +// </h> +// <h> Bulk Endpoint Settings +// <o7.0..4> Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o8.0..4> Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o9> Maximum Packet Size <1-1024> +// <e10> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o11> Maximum Packet Size <1-1024> +// <o12> Maximum NAK Rate <0-255> +// </e10> +// </h> +// </h> +// <h> Communication Device Settings +// <i> Device specific settings +// <s0.126> Communication Class Interface String +// <s1.126> Data Class Interface String +// <o13> Maximum Communication Device Send Buffer Size +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// <o14> Maximum Communication Device Receive Buffer Size +// <i> Minimum size must be as big as maximum packet size for Bulk Out Endpoint +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// </h> +// </e> + +#ifndef CDC_ENDPOINT +#define CDC_ENDPOINT 0 +#else +#define CDC_ENDPOINT 1 +#endif +#define USBD_CDC_ACM_ENABLE CDC_ENDPOINT +#define USBD_CDC_ACM_EP_INTIN 3 +#define USBD_CDC_ACM_EP_INTIN_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE 16 +#define USBD_CDC_ACM_BINTERVAL 32 +#define USBD_CDC_ACM_HS_ENABLE 0 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE 16 +#define USBD_CDC_ACM_HS_BINTERVAL 2 +#define USBD_CDC_ACM_EP_BULKIN 4 +#define USBD_CDC_ACM_EP_BULKOUT 4 +#define USBD_CDC_ACM_EP_BULKIN_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE1 64 +#define USBD_CDC_ACM_HS_ENABLE1 0 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE1 64 +#define USBD_CDC_ACM_HS_BINTERVAL1 0 +#define USBD_CDC_ACM_CIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_DIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_SENDBUF_SIZE 64 +#define USBD_CDC_ACM_RECEIVEBUF_SIZE 64 +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Send Buffer size must be larger or equal to Bulk In maximum packet size!" +#endif +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Receive Buffer size must be larger or equal to Bulk Out maximum packet size!" +#endif + +// <e0> Custom Class Device +// <i> Enables USB Custom Class Requests +// <i> Class IDs: +// <i> 0x00 - Class Reserved ID +// <i> 0x01 - Class Audio ID +// <i> 0x02 - Class Communications ID +// <i> 0x03 - Class Human Interface ID +// <i> 0x04 - Class Monitor ID +// <i> 0x05 - Class Physical Interface ID +// <i> 0x06 - Class Power ID +// <i> 0x07 - Class Printer ID +// <i> 0x08 - Class Storage ID +// <i> 0x09 - Class HUB ID +// <i> 0xEF - Class Miscellaneous ID +// <i> 0xFF - Class Vendor Specific ID +// </e> +#define USBD_CLS_ENABLE 0 + +// WebUSB support +#define USBD_WEBUSB_ENABLE WEBUSB_INTERFACE +#define USBD_WEBUSB_VENDOR_CODE 0x21 +#define USBD_WEBUSB_LANDING_URL "os.mbed.com/webusb/landing-page/?bid=" +#define USBD_WEBUSB_ORIGIN_URL "os.mbed.com/" + +// Microsoft OS Descriptors 2.0 (WinUSB) support +#define USBD_WINUSB_ENABLE WINUSB_INTERFACE +#define USBD_WINUSB_VENDOR_CODE 0x20 +// </e> +// </e> + +#ifndef BULK_ENDPOINT +#define BULK_ENDPOINT 0 +#else +#define BULK_ENDPOINT 1 +#endif +#define USBD_BULK_ENABLE BULK_ENDPOINT +#define USBD_BULK_EP_BULKIN 5 +#define USBD_BULK_EP_BULKOUT 5 +#define USBD_BULK_WMAXPACKETSIZE 64 +#define USBD_BULK_HS_ENABLE 0 +#define USBD_BULK_HS_WMAXPACKETSIZE 512 +#define USBD_BULK_STRDESC L"CMSIS-DAP v2" + +/* USB Device Calculations ---------------------------------------------------*/ + +#define USBD_IF_NUM_MAX (USBD_BULK_ENABLE+USBD_WEBUSB_ENABLE+USBD_HID_ENABLE+USBD_MSC_ENABLE+(USBD_ADC_ENABLE*2)+(USBD_CDC_ACM_ENABLE*2)+USBD_CLS_ENABLE) +#define USBD_MULTI_IF (USBD_CDC_ACM_ENABLE*(USBD_HID_ENABLE|USBD_MSC_ENABLE|USBD_ADC_ENABLE|USBD_CLS_ENABLE|USBD_WEBUSB_ENABLE|USBD_BULK_ENABLE)) +// #define MAX(x, y) (((x) < (y)) ? (y) : (x)) +#define USBD_EP_NUM_CALC0 MAX((USBD_HID_ENABLE *(USBD_HID_EP_INTIN )), (USBD_HID_ENABLE *(USBD_HID_EP_INTOUT!=0)*(USBD_HID_EP_INTOUT))) +#define USBD_EP_NUM_CALC1 MAX((USBD_MSC_ENABLE *(USBD_MSC_EP_BULKIN )), (USBD_MSC_ENABLE *(USBD_MSC_EP_BULKOUT))) +#define USBD_EP_NUM_CALC2 MAX((USBD_ADC_ENABLE *(USBD_ADC_EP_ISOOUT )), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_INTIN))) +#define USBD_EP_NUM_CALC3 MAX((USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKIN)), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKOUT))) +#define USBD_EP_NUM_CALC4 MAX(USBD_EP_NUM_CALC0, USBD_EP_NUM_CALC1) +#define USBD_EP_NUM_CALC5 MAX(USBD_EP_NUM_CALC2, USBD_EP_NUM_CALC3) +#define USBD_EP_NUM_CALC6 MAX(USBD_EP_NUM_CALC4, USBD_EP_NUM_CALC5) +#define USBD_EP_NUM_CALC7 MAX((USBD_BULK_ENABLE*(USBD_BULK_EP_BULKIN)), (USBD_BULK_ENABLE*(USBD_BULK_EP_BULKOUT))) +#define USBD_EP_NUM MAX(USBD_EP_NUM_CALC6, USBD_EP_NUM_CALC7) + + +#if (USBD_HID_ENABLE) +#if (USBD_MSC_ENABLE) +#if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_MSC_EP_BULKOUT))) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKOUT))) +#error "HID and Mass Storage Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_ADC_ENABLE) +#if ((USBD_HID_EP_INTIN == USBD_ADC_EP_ISOOUT) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_ADC_EP_ISOOUT))) +#error "HID and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (((USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKOUT))|| \ + ((USBD_HID_EP_INTOUT != 0) && \ + ((USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKOUT)))) +#error "HID and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_MSC_ENABLE) +#if (USBD_ADC_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_ADC_EP_ISOOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_ADC_EP_ISOOUT)) +#error "Mass Storage Device and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Mass Storage Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_ADC_ENABLE) +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Audio Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#define USBD_ADC_CIF_NUM (0) +#define USBD_ADC_SIF1_NUM (1) +#define USBD_ADC_SIF2_NUM (2) + + +#define USBD_ADC_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+0) +#define USBD_ADC_SIF1_STR_NUM (3+USBD_STRDESC_SER_ENABLE+1) +#define USBD_ADC_SIF2_STR_NUM (3+USBD_STRDESC_SER_ENABLE+2) +#define USBD_CDC_ACM_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+0) +#define USBD_CDC_ACM_DIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+1) +#define USBD_HID_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2) +#define USBD_WEBUSB_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) +#define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) +#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) + + +#if (USBD_HID_ENABLE) +#if (USBD_HID_HS_ENABLE) +#define USBD_HID_MAX_PACKET ((USBD_HID_HS_WMAXPACKETSIZE > USBD_HID_WMAXPACKETSIZE) ? USBD_HID_HS_WMAXPACKETSIZE : USBD_HID_WMAXPACKETSIZE) +#else +#define USBD_HID_MAX_PACKET (USBD_HID_WMAXPACKETSIZE) +#endif +#else +#define USBD_HID_MAX_PACKET (0) +#endif +#if (USBD_MSC_ENABLE) +#if (USBD_MSC_HS_ENABLE) +#define USBD_MSC_MAX_PACKET ((USBD_MSC_HS_WMAXPACKETSIZE > USBD_MSC_WMAXPACKETSIZE) ? USBD_MSC_HS_WMAXPACKETSIZE : USBD_MSC_WMAXPACKETSIZE) +#else +#define USBD_MSC_MAX_PACKET (USBD_MSC_WMAXPACKETSIZE) +#endif +#else +#define USBD_MSC_MAX_PACKET (0) +#endif +#if (USBD_ADC_ENABLE) +#if (USBD_ADC_HS_ENABLE) +#define USBD_ADC_MAX_PACKET ((USBD_ADC_HS_WMAXPACKETSIZE > USBD_ADC_WMAXPACKETSIZE) ? USBD_ADC_HS_WMAXPACKETSIZE : USBD_ADC_WMAXPACKETSIZE) +#else +#define USBD_ADC_MAX_PACKET (USBD_ADC_WMAXPACKETSIZE) +#endif +#else +#define USBD_ADC_MAX_PACKET (0) +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (USBD_CDC_ACM_HS_ENABLE) +#define USBD_CDC_ACM_MAX_PACKET ((USBD_CDC_ACM_HS_WMAXPACKETSIZE > USBD_CDC_ACM_WMAXPACKETSIZE) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE : USBD_CDC_ACM_WMAXPACKETSIZE) +#else +#define USBD_CDC_ACM_MAX_PACKET (USBD_CDC_ACM_WMAXPACKETSIZE) +#endif +#if (USBD_CDC_ACM_HS_ENABLE1) +#define USBD_CDC_ACM_MAX_PACKET1 ((USBD_CDC_ACM_HS_WMAXPACKETSIZE1 > USBD_CDC_ACM_WMAXPACKETSIZE1) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE1 : USBD_CDC_ACM_WMAXPACKETSIZE1) +#else +#define USBD_CDC_ACM_MAX_PACKET1 (USBD_CDC_ACM_WMAXPACKETSIZE1) +#endif +#else +#define USBD_CDC_ACM_MAX_PACKET (0) +#define USBD_CDC_ACM_MAX_PACKET1 (0) +#endif + +#if (USBD_BULK_ENABLE) +#if (USBD_BULK_HS_ENABLE) +#define USBD_BULK_MAX_PACKET ((USBD_BULK_HS_WMAXPACKETSIZE > USBD_BULK_WMAXPACKETSIZE) ? USBD_BULK_HS_WMAXPACKETSIZE : USBD_BULK_WMAXPACKETSIZE) +#else +#define USBD_BULK_MAX_PACKET (USBD_BULK_WMAXPACKETSIZE) +#endif +#else +#define USBD_BULK_MAX_PACKET (0) +#endif + +#define USBD_MAX_PACKET_CALC0 ((USBD_HID_MAX_PACKET > USBD_HID_MAX_PACKET ) ? (USBD_HID_MAX_PACKET ) : (USBD_HID_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC1 ((USBD_ADC_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET ) ? (USBD_ADC_MAX_PACKET ) : (USBD_CDC_ACM_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC2 ((USBD_MAX_PACKET_CALC0 > USBD_MAX_PACKET_CALC1 ) ? (USBD_MAX_PACKET_CALC0) : (USBD_MAX_PACKET_CALC1 )) +#define USBD_MAX_PACKET_CALC3 ((USBD_BULK_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET1 ) ? (USBD_BULK_MAX_PACKET) : (USBD_CDC_ACM_MAX_PACKET1 )) +#define USBD_MAX_PACKET ((USBD_MAX_PACKET_CALC3 > USBD_MAX_PACKET_CALC2 ) ? (USBD_MAX_PACKET_CALC3) : (USBD_MAX_PACKET_CALC2 )) + + +/*------------------------------------------------------------------------------ + * USB Config Functions + *----------------------------------------------------------------------------*/ + +#ifndef __USB_CONFIG___ +#define __USB_CONFIG__ + +#ifndef __NO_USB_LIB_C +#include "usb_lib.c" +#endif + +#endif /* __USB_CONFIG__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/nxp/lpc4322/usbd_LPC43xx_USB0.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nxp/lpc4322/usbd_LPC43xx_USB0.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,901 @@
+/**
+ * @file usbd_LPC43xx_USBD0.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "rl_usb.h"
+#include "usb.h"
+#include "LPC43xx.h"
+#include "compiler.h"
+
+#define __NO_USB_LIB_C
+#include "usb_config.c"
+
+/* Endpoint queue head */
+typedef struct __EPQH {
+ uint32_t cap;
+ uint32_t curr_dTD;
+ uint32_t next_dTD;
+ uint32_t dTD_token;
+ uint32_t buf[5];
+ uint32_t reserved;
+ uint32_t setup[2];
+ uint32_t reserved1[4];
+} EPQH;
+
+/* Endpoint transfer descriptor */
+typedef struct __dTD {
+ uint32_t next_dTD;
+ uint32_t dTD_token;
+ uint32_t buf[5];
+ uint32_t reserved;
+} dTD;
+
+/* Endpoint */
+typedef struct __EP {
+ uint8_t *buf;
+ uint32_t maxPacket;
+} EP;
+
+EPQH __align(2048) EPQHx[(USBD_EP_NUM + 1) * 2];
+dTD __align(32) dTDx[(USBD_EP_NUM + 1) * 2];
+
+EP Ep[(USBD_EP_NUM + 1) * 2];
+uint32_t BufUsed;
+uint32_t IsoEp;
+uint32_t cmpl_pnd;
+
+#define LPC_USBx LPC_USB0
+#define ENDPTCTRL(EPNum) *(volatile uint32_t *)((uint32_t)(&LPC_USBx->ENDPTCTRL0) + 4 * EPNum)
+#define EP_OUT_IDX(EPNum) (EPNum * 2 )
+#define EP_IN_IDX(EPNum) (EPNum * 2 + 1)
+#define HS(en) (USBD_HS_ENABLE * en)
+
+/* reserve RAM for endpoint buffers */
+#if USBD_VENDOR_ENABLE
+/* custom class: user defined buffer size */
+#define EP_BUF_POOL_SIZE 0x1000
+uint8_t __align(4096) EPBufPool[EP_BUF_POOL_SIZE]
+#else
+/* supported classes are used */
+uint8_t __align(4096) EPBufPool[
+ USBD_MAX_PACKET0 * 2 +
+ USBD_HID_ENABLE * (HS(USBD_HID_HS_ENABLE) ? USBD_HID_HS_WMAXPACKETSIZE : USBD_HID_WMAXPACKETSIZE) * 2 +
+ USBD_MSC_ENABLE * (HS(USBD_MSC_HS_ENABLE) ? USBD_MSC_HS_WMAXPACKETSIZE : USBD_MSC_WMAXPACKETSIZE) * 2 +
+ USBD_ADC_ENABLE * (HS(USBD_ADC_HS_ENABLE) ? USBD_ADC_HS_WMAXPACKETSIZE : USBD_ADC_WMAXPACKETSIZE) +
+ USBD_CDC_ACM_ENABLE * ((HS(USBD_CDC_ACM_HS_ENABLE) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE : USBD_CDC_ACM_WMAXPACKETSIZE) +
+ (HS(USBD_CDC_ACM_HS_ENABLE) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE1 : USBD_CDC_ACM_WMAXPACKETSIZE1) * 2) +
+ USBD_BULK_ENABLE * (HS(USBD_BULK_HS_ENABLE) ? USBD_BULK_HS_WMAXPACKETSIZE : USBD_BULK_WMAXPACKETSIZE) * 2
+];
+#endif
+
+void USBD_PrimeEp(uint32_t EPNum, uint32_t cnt);
+
+/*
+ * Usb interrupt enable/disable
+ * Parameters: ena: enable/disable
+ * 0: disable interrupt
+ * 1: enable interrupt
+ */
+
+#ifdef __RTX
+void __svc(1) USBD_Intr(int ena);
+void __SVC_1(int ena)
+{
+#else
+void USBD_Intr(int ena)
+{
+#endif
+
+ if (ena) {
+ NVIC_EnableIRQ(USB0_IRQn); /* Enable USB interrupt */
+ } else {
+ NVIC_DisableIRQ(USB0_IRQn); /* Disable USB interrupt */
+ }
+}
+
+
+/*
+ * USB Device Initialize Function
+ * Called by the User to initialize USB Device
+ * Return Value: None
+ */
+
+void USBD_Init(void)
+{
+ USBD_Intr(0);
+ /* BASE_USB0_CLK */
+ LPC_CGU->BASE_USB0_CLK = (0x01 << 11) | /* Autoblock En */
+ (0x07 << 24) ; /* Clock source: PLL0 */
+ LPC_CCU1->CLK_M4_USB0_CFG |= 1;
+
+ while (!(LPC_CCU1->CLK_M4_USB0_STAT & 1));
+
+ LPC_SCU->SFSP6_3 = 1; /* pwr en */
+ LPC_SCU->SFSP6_6 = 3; /* pwr fault */
+ LPC_SCU->SFSP8_1 = 1; /* port indicator LED control out 1 */
+ LPC_SCU->SFSP8_2 = 1; /* port indicator LED control out 0 */
+ LPC_USBx->USBCMD_D |= (1UL << 1); /* usb reset */
+
+ while (LPC_USBx->USBCMD_D & (1UL << 1));
+
+ LPC_CREG->CREG0 &= ~(1 << 5);
+ LPC_USBx->USBMODE_D = 2 | (1UL << 3);/* device mode */
+#if USBD_HS_ENABLE
+ LPC_USBx->PORTSC1_D &= ~(1UL << 24);
+#else
+ LPC_USBx->PORTSC1_D |= (1UL << 24);
+#endif
+ LPC_USBx->OTGSC = 1 | (1UL << 3);
+ Ep[EP_OUT_IDX(0)].maxPacket = USBD_MAX_PACKET0;
+ LPC_USBx->USBINTR_D = (1UL << 0) | /* usb int enable */
+ (1UL << 2) | /* port change detect int enable */
+ (1UL << 8) | /* suspend int enable */
+ (1UL << 16) | /* nak int enable */
+ (1UL << 6) | /* reset int enable */
+#ifdef __RTX
+ ((USBD_RTX_DevTask != 0) ? (1UL << 7) : 0) | /* SOF */
+ ((USBD_RTX_DevTask != 0) ? (1UL << 1) : 0) ; /* Error */
+#else
+ ((USBD_P_SOF_Event != 0) ? (1UL << 7) : 0) | /* SOF */
+ ((USBD_P_Error_Event != 0) ? (1UL << 1) : 0) ; /* Error */
+#endif
+ USBD_Reset();
+ USBD_Intr(1);
+}
+
+
+/*
+ * USB Device Connect Function
+ * Called by the User to Connect/Disconnect USB Device
+ * Parameters: con: Connect/Disconnect
+ * Return Value: None
+ */
+
+void USBD_Connect(uint32_t con)
+{
+ if (con) {
+ LPC_USBx->USBCMD_D |= 1; /* run */
+ } else {
+ LPC_USBx->USBCMD_D &= ~1; /* stop */
+ }
+}
+
+
+/*
+ * USB Device Reset Function
+ * Called automatically on USB Device Reset
+ * Return Value: None
+ */
+
+void USBD_Reset(void)
+{
+ uint32_t i;
+ uint8_t *ptr;
+ cmpl_pnd = 0;
+
+ for (i = 1; i < USBD_EP_NUM + 1; i++) {
+ ENDPTCTRL(i) &= ~((1UL << 7) | (1UL << 23));
+ }
+
+ /* clear interrupts */
+ LPC_USBx->ENDPTNAK = 0xFFFFFFFF;
+ LPC_USBx->ENDPTNAKEN = 0;
+ LPC_USBx->USBSTS_D = 0xFFFFFFFF;
+ LPC_USBx->ENDPTSETUPSTAT = LPC_USBx->ENDPTSETUPSTAT;
+ LPC_USBx->ENDPTCOMPLETE = LPC_USBx->ENDPTCOMPLETE;
+
+ while (LPC_USBx->ENDPTPRIME);
+
+ LPC_USBx->ENDPTFLUSH = 0xFFFFFFFF;
+
+ while (LPC_USBx->ENDPTFLUSH);
+
+ LPC_USBx->USBCMD_D &= ~0x00FF0000; /* immediate intrrupt treshold */
+ /* clear endpoint queue heads */
+ ptr = (uint8_t *)EPQHx;
+
+ for (i = 0; i < sizeof(EPQHx); i++) {
+ ptr[i] = 0;
+ }
+
+ /* clear endpoint transfer descriptors */
+ ptr = (uint8_t *)dTDx;
+
+ for (i = 0; i < sizeof(dTDx); i++) {
+ ptr[i] = 0;
+ }
+
+ Ep[EP_OUT_IDX(0)].maxPacket = USBD_MAX_PACKET0;
+ Ep[EP_OUT_IDX(0)].buf = EPBufPool;
+ BufUsed = USBD_MAX_PACKET0;
+ Ep[EP_IN_IDX(0)].maxPacket = USBD_MAX_PACKET0;
+ Ep[EP_IN_IDX(0)].buf = &(EPBufPool[BufUsed]);
+ BufUsed += USBD_MAX_PACKET0;
+ dTDx[EP_OUT_IDX(0)].next_dTD = 1;
+ dTDx[EP_IN_IDX(0)].next_dTD = 1;
+ dTDx[EP_OUT_IDX(0)].dTD_token = (USBD_MAX_PACKET0 << 16) | /* total bytes */
+ (1UL << 15); /* int on compl */
+ dTDx[EP_IN_IDX(0)].dTD_token = (USBD_MAX_PACKET0 << 16) | /* total bytes */
+ (1UL << 15); /* int on compl */
+ EPQHx[EP_OUT_IDX(0)].next_dTD = (uint32_t) &dTDx[EP_OUT_IDX(0)];
+ EPQHx[EP_IN_IDX(0)].next_dTD = (uint32_t) &dTDx[EP_IN_IDX(0)];
+ EPQHx[EP_OUT_IDX(0)].cap = ((USBD_MAX_PACKET0 & 0x0EFF) << 16) |
+ (1UL << 29) |
+ (1UL << 15); /* int on setup */
+ EPQHx[EP_IN_IDX(0)].cap = (USBD_MAX_PACKET0 << 16) |
+ (1UL << 29) |
+ (1UL << 15); /* int on setup */
+ LPC_USBx->ENDPOINTLISTADDR = (uint32_t)EPQHx;
+ LPC_USBx->USBMODE_D |= (1UL << 3); /* Setup lockouts off */
+ LPC_USBx->ENDPTCTRL0 = 0x00C000C0;
+ USBD_PrimeEp(0, Ep[EP_OUT_IDX(0)].maxPacket);
+}
+
+
+/*
+ * USB Device Suspend Function
+ * Called automatically on USB Device Suspend
+ * Return Value: None
+ */
+
+void USBD_Suspend(void)
+{
+ /* Performed by Hardware */
+}
+
+
+/*
+ * USB Device Resume Function
+ * Called automatically on USB Device Resume
+ * Return Value: None
+ */
+
+void USBD_Resume(void)
+{
+ /* Performed by Hardware */
+}
+
+
+/*
+ * USB Device Remote Wakeup Function
+ * Called automatically on USB Device Remote Wakeup
+ * Return Value: None
+ */
+
+void USBD_WakeUp(void)
+{
+ LPC_USBx->PORTSC1_D |= (1UL << 6);
+}
+
+
+/*
+ * USB Device Remote Wakeup Configuration Function
+ * Parameters: cfg: Device Enable/Disable
+ * Return Value: None
+ */
+
+void USBD_WakeUpCfg(uint32_t cfg)
+{
+ /* Not needed */
+}
+
+
+/*
+ * USB Device Set Address Function
+ * Parameters: adr: USB Device Address
+ * Return Value: None
+ */
+
+void USBD_SetAddress(uint32_t adr, uint32_t setup)
+{
+ if (setup == 0) {
+ LPC_USBx->DEVICEADDR = (adr << 25);
+ LPC_USBx->DEVICEADDR |= (1UL << 24);
+ }
+}
+
+
+/*
+ * USB Device Configure Function
+ * Parameters: cfg: Device Configure/Deconfigure
+ * Return Value: None
+ */
+
+void USBD_Configure(uint32_t cfg)
+{
+ uint32_t i;
+
+ if (!cfg) {
+ for (i = 2; i < (2 * (USBD_EP_NUM + 1)); i++) {
+ Ep[i].buf = 0;
+ Ep[i].maxPacket = 0;
+ }
+
+ BufUsed = 2 * USBD_MAX_PACKET0;
+ }
+}
+
+
+/*
+ * Configure USB Device Endpoint according to Descriptor
+ * Parameters: pEPD: Pointer to Device Endpoint Descriptor
+ * Return Value: None
+ */
+
+void USBD_ConfigEP(USB_ENDPOINT_DESCRIPTOR *pEPD)
+{
+ uint32_t num, val, type, idx;
+
+ if ((pEPD->bEndpointAddress & USB_ENDPOINT_DIRECTION_MASK)) {
+ val = 16;
+ num = pEPD->bEndpointAddress & ~0x80;
+ idx = EP_IN_IDX(num);
+
+ } else {
+ val = 0;
+ num = pEPD->bEndpointAddress;
+ idx = EP_OUT_IDX(num);
+ }
+
+ type = pEPD->bmAttributes & USB_ENDPOINT_TYPE_MASK;
+
+ if (!(Ep[idx].buf)) {
+ Ep[idx].buf = &(EPBufPool[BufUsed]);
+ Ep[idx].maxPacket = pEPD->wMaxPacketSize;
+ BufUsed += pEPD->wMaxPacketSize;
+
+ /* Isochronous endpoint */
+ if (type == USB_ENDPOINT_TYPE_ISOCHRONOUS) {
+ IsoEp |= (1UL << (num + val));
+ }
+ }
+
+ dTDx[idx].buf[0] = (uint32_t)(Ep[idx].buf);
+ dTDx[idx].next_dTD = 1;
+ EPQHx[idx].cap = (Ep[idx].maxPacket << 16) |
+ (1UL << 29);
+ ENDPTCTRL(num) &= ~(0xFFFF << val);
+ ENDPTCTRL(num) |= ((type << 2) << val) |
+ ((1UL << 6) << val); /* Data toogle reset */
+}
+
+
+/*
+ * Set Direction for USB Device Control Endpoint
+ * Parameters: dir: Out (dir == 0), In (dir <> 0)
+ * Return Value: None
+ */
+
+void USBD_DirCtrlEP(uint32_t dir)
+{
+ /* Not needed */
+}
+
+
+/*
+ * Enable USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_EnableEP(uint32_t EPNum)
+{
+ if (EPNum & 0x80) {
+ EPNum &= 0x7F;
+ ENDPTCTRL(EPNum) |= (1UL << 23); /* EP enabled */
+ } else {
+ ENDPTCTRL(EPNum) |= (1UL << 7); /* EP enabled */
+ }
+}
+
+
+/*
+ * Disable USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_DisableEP(uint32_t EPNum)
+{
+ if (EPNum & 0x80) {
+ EPNum &= 0x7F;
+ ENDPTCTRL(EPNum) &= ~(1UL << 23); /* EP disabled */
+ } else {
+ ENDPTCTRL(EPNum) &= ~(1UL << 7); /* EP disabled */
+ }
+}
+
+
+/*
+ * Reset USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_ResetEP(uint32_t EPNum)
+{
+ if (EPNum & 0x80) {
+ EPNum &= 0x7F;
+ EPQHx[EP_IN_IDX(EPNum)].dTD_token &= 0xC0;
+ LPC_USBx->ENDPTFLUSH = (1UL << (EPNum + 16)); /* flush endpoint */
+
+ while (LPC_USBx->ENDPTFLUSH & (1UL << (EPNum + 16)));
+
+ ENDPTCTRL(EPNum) |= (1UL << 22); /* data toggle reset */
+
+ } else {
+ EPQHx[EP_OUT_IDX(EPNum)].dTD_token &= 0xC0;
+ LPC_USBx->ENDPTFLUSH = (1UL << EPNum); /* flush endpoint */
+
+ while (LPC_USBx->ENDPTFLUSH & (1UL << EPNum));
+
+ ENDPTCTRL(EPNum) |= (1UL << 6); /* data toggle reset */
+ USBD_PrimeEp(EPNum, Ep[EP_OUT_IDX(EPNum)].maxPacket);
+ }
+}
+
+
+/*
+ * Set Stall for USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_SetStallEP(uint32_t EPNum)
+{
+ if (EPNum & 0x80) {
+ EPNum &= 0x7F;
+ ENDPTCTRL(EPNum) |= (1UL << 16); /* IN endpoint stall */
+ } else {
+ ENDPTCTRL(EPNum) |= (1UL << 0); /* OUT endpoint stall */
+ }
+}
+
+
+/*
+ * Clear Stall for USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_ClrStallEP(uint32_t EPNum)
+{
+ if (EPNum & 0x80) {
+ EPNum &= 0x7F;
+ ENDPTCTRL(EPNum) &= ~(1UL << 16); /* clear stall */
+ ENDPTCTRL(EPNum) |= (1UL << 22); /* data toggle reset */
+
+ while (ENDPTCTRL(EPNum) & (1UL << 16));
+
+ USBD_ResetEP(EPNum | 0x80);
+
+ } else {
+ ENDPTCTRL(EPNum) &= ~(1UL << 0); /* clear stall */
+ ENDPTCTRL(EPNum) |= (1UL << 6); /* data toggle reset */
+ }
+}
+
+
+/*
+ * Clear USB Device Endpoint Buffer
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_ClearEPBuf(uint32_t EPNum)
+{
+}
+
+
+/*
+ * USB Device Prime endpoint function
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * cnt: Bytes to transfer/receive
+ * Return Value: None
+ */
+
+void USBD_PrimeEp(uint32_t EPNum, uint32_t cnt)
+{
+ uint32_t idx, val;
+
+ /* IN endpoint */
+ if (EPNum & 0x80) {
+ EPNum &= 0x7F;
+ idx = EP_IN_IDX(EPNum);
+ val = (1UL << (EPNum + 16));
+ }
+
+ /* OUT endpoint */
+ else {
+ val = (1UL << EPNum);
+ idx = EP_OUT_IDX(EPNum);
+ }
+
+ dTDx[idx].buf[0] = (uint32_t)(Ep[idx].buf);
+ dTDx[idx].next_dTD = 1;
+
+ if (IsoEp & val) {
+ if (Ep[idx].maxPacket <= cnt) {
+ dTDx[idx].dTD_token = (1 << 10); /* MultO = 1 */
+
+ } else if ((Ep[idx].maxPacket * 2) <= cnt) {
+ dTDx[idx].dTD_token = (2 << 10); /* MultO = 2 */
+
+ } else {
+ dTDx[idx].dTD_token = (3 << 10); /* MultO = 3 */
+ }
+
+ } else {
+ dTDx[idx].dTD_token = 0;
+ }
+
+ dTDx[idx].dTD_token |= (cnt << 16) | /* bytes to transfer */
+ (1UL << 15) | /* int on complete */
+ 0x80; /* status - active */
+ EPQHx[idx].next_dTD = (uint32_t)(&dTDx[idx]);
+ EPQHx[idx].dTD_token &= ~0xC0;
+ LPC_USBx->ENDPTPRIME = (val);
+
+ while ((LPC_USBx->ENDPTPRIME & val));
+}
+
+
+/*
+ * Read USB Device Endpoint Data
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * pData: Pointer to Data Buffer
+ * Return Value: Number of bytes read
+ */
+
+uint32_t USBD_ReadEP(uint32_t EPNum, uint8_t *pData, U32 size)
+{
+ uint32_t cnt = 0;
+ uint32_t i;
+
+ /* Setup packet */
+ if ((LPC_USBx->ENDPTSETUPSTAT & 1) && (!EPNum)) {
+ LPC_USBx->ENDPTSETUPSTAT = 1;
+
+ while (LPC_USBx->ENDPTSETUPSTAT & 1);
+
+ do {
+ *((__packed uint32_t *) pData) = EPQHx[EP_OUT_IDX(0)].setup[0];
+ *((__packed uint32_t *)(pData + 4)) = EPQHx[EP_OUT_IDX(0)].setup[1];
+ cnt = 8;
+ LPC_USBx->USBCMD_D |= (1UL << 13);
+ } while (!(LPC_USBx->USBCMD_D & (1UL << 13)));
+
+ LPC_USBx->USBCMD_D &= (~(1UL << 13));
+ LPC_USBx->ENDPTFLUSH = (1UL << EPNum) | (1UL << (EPNum + 16));
+
+ while (LPC_USBx->ENDPTFLUSH & ((1UL << (EPNum + 16)) | (1UL << EPNum)));
+
+ while (LPC_USBx->ENDPTSETUPSTAT & 1);
+
+ USBD_PrimeEp(EPNum, Ep[EP_OUT_IDX(EPNum)].maxPacket);
+ }
+
+ /* OUT Packet */
+ else {
+ if (Ep[EP_OUT_IDX(EPNum)].buf) {
+ cnt = Ep[EP_OUT_IDX(EPNum)].maxPacket -
+ ((dTDx[EP_OUT_IDX(EPNum)].dTD_token >> 16) & 0x7FFF);
+
+ cnt = cnt < size ? cnt : size;
+
+ for (i = 0; i < cnt; i++) {
+ pData[i] = Ep[EP_OUT_IDX(EPNum)].buf[i];
+ }
+ }
+
+ LPC_USBx->ENDPTCOMPLETE = (1UL << EPNum);
+ cmpl_pnd &= ~(1UL << EPNum);
+ USBD_PrimeEp(EPNum, Ep[EP_OUT_IDX(EPNum)].maxPacket);
+ }
+
+ return (cnt);
+}
+
+
+/*
+ * Write USB Device Endpoint Data
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * pData: Pointer to Data Buffer
+ * cnt: Number of bytes to write
+ * Return Value: Number of bytes written
+ */
+
+uint32_t USBD_WriteEP(uint32_t EPNum, uint8_t *pData, uint32_t cnt)
+{
+ uint32_t i;
+ EPNum &= 0x7f;
+
+ for (i = 0; i < cnt; i++) {
+ Ep[EP_IN_IDX(EPNum)].buf[i] = pData[i];
+ }
+
+ USBD_PrimeEp(EPNum | 0x80, cnt);
+ return (cnt);
+}
+
+
+/*
+ * Get USB Device Last Frame Number
+ * Parameters: None
+ * Return Value: Frame Number
+ */
+
+uint32_t USBD_GetFrame(void)
+{
+ return ((LPC_USBx->FRINDEX_D >> 3) & 0x0FFF);
+}
+
+
+#ifdef __RTX
+uint32_t LastError; /* Last Error */
+
+/*
+ * Get USB Device Last Error Code
+ * Parameters: None
+ * Return Value: Error Code
+ */
+
+uint32_t USBD_GetError(void)
+{
+ return (LastError);
+}
+#endif
+
+
+/*
+ * USB Device Interrupt Service Routine
+ */
+
+void USB0_IRQHandler(void)
+{
+ NVIC_DisableIRQ(USB0_IRQn);
+ USBD_SignalHandler();
+}
+
+void USBD_Handler(void)
+{
+ uint32_t sts, cmpl, num;
+ sts = LPC_USBx->USBSTS_D & LPC_USBx->USBINTR_D;
+ cmpl = LPC_USBx->ENDPTCOMPLETE;
+ LPC_USBx->USBSTS_D = sts; /* clear interupt flags */
+
+ /* reset interrupt */
+ if (sts & (1UL << 6)) {
+ USBD_Reset();
+ usbd_reset_core();
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_RESET, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Reset_Event) {
+ USBD_P_Reset_Event();
+ }
+
+#endif
+ }
+
+ /* suspend interrupt */
+ if (sts & (1UL << 8)) {
+ USBD_Suspend();
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_SUSPEND, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Suspend_Event) {
+ USBD_P_Suspend_Event();
+ }
+
+#endif
+ }
+
+ /* SOF interrupt */
+ if (sts & (1UL << 7)) {
+ if (IsoEp) {
+ for (num = 0; num < USBD_EP_NUM + 1; num++) {
+ if (IsoEp & (1UL << num)) {
+ USBD_PrimeEp(num, Ep[EP_OUT_IDX(num)].maxPacket);
+ }
+ }
+
+ } else {
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_SOF, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_SOF_Event) {
+ USBD_P_SOF_Event();
+ }
+
+#endif
+ }
+ }
+
+ /* port change detect interrupt */
+ if (sts & (1UL << 2)) {
+ if (((LPC_USBx->PORTSC1_D >> 26) & 0x03) == 2) {
+ USBD_HighSpeed = __TRUE;
+ }
+
+ USBD_Resume();
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_RESUME, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Resume_Event) {
+ USBD_P_Resume_Event();
+ }
+
+#endif
+ }
+
+ /* USB interrupt - completed transfer */
+ if (sts & 1) {
+ /* Setup Packet */
+ if (LPC_USBx->ENDPTSETUPSTAT) {
+#ifdef __RTX
+
+ if (USBD_RTX_EPTask[0]) {
+ isr_evt_set(USBD_EVT_SETUP, USBD_RTX_EPTask[0]);
+ }
+
+#else
+
+ if (USBD_P_EP[0]) {
+ USBD_P_EP[0](USBD_EVT_SETUP);
+ }
+
+#endif
+ }
+
+ /* IN Packet */
+ if (cmpl & (0x3F << 16)) {
+ for (num = 0; num < USBD_EP_NUM + 1; num++) {
+ if (((cmpl >> 16) & 0x3F) & (1UL << num)) {
+ LPC_USBx->ENDPTCOMPLETE = (1UL << (num + 16)); /* Clear completed */
+#ifdef __RTX
+
+ if (USBD_RTX_EPTask[num]) {
+ isr_evt_set(USBD_EVT_IN, USBD_RTX_EPTask[num]);
+ }
+
+#else
+
+ if (USBD_P_EP[num]) {
+ USBD_P_EP[num](USBD_EVT_IN);
+ }
+
+#endif
+ }
+ }
+ }
+
+ /* OUT Packet */
+ if (cmpl & 0x3F) {
+ for (num = 0; num < USBD_EP_NUM + 1; num++) {
+ if ((cmpl ^ cmpl_pnd) & cmpl & (1UL << num)) {
+ cmpl_pnd |= 1UL << num;
+#ifdef __RTX
+
+ if (USBD_RTX_EPTask[num]) {
+ isr_evt_set(USBD_EVT_OUT, USBD_RTX_EPTask[num]);
+
+ } else if (IsoEp & (1UL << num)) {
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_SOF, USBD_RTX_DevTask);
+ }
+ }
+
+#else
+
+ if (USBD_P_EP[num]) {
+ USBD_P_EP[num](USBD_EVT_OUT);
+
+ } else if (IsoEp & (1UL << num)) {
+ if (USBD_P_SOF_Event) {
+ USBD_P_SOF_Event();
+ }
+ }
+
+#endif
+ }
+ }
+ }
+ }
+
+ /* error interrupt */
+ if (sts & (1UL << 1)) {
+ for (num = 0; num < USBD_EP_NUM + 1; num++) {
+ if (cmpl & (1UL << num)) {
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ LastError = dTDx[EP_OUT_IDX(num)].dTD_token & 0xE8;
+ isr_evt_set(USBD_EVT_ERROR, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Error_Event) {
+ USBD_P_Error_Event(dTDx[EP_OUT_IDX(num)].dTD_token & 0xE8);
+ }
+
+#endif
+ }
+
+ if (cmpl & (1UL << (num + 16))) {
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ LastError = dTDx[EP_IN_IDX(num)].dTD_token & 0xE8;
+ isr_evt_set(USBD_EVT_ERROR, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Error_Event) {
+ USBD_P_Error_Event(dTDx[EP_IN_IDX(num)].dTD_token & 0xE8);
+ }
+
+#endif
+ }
+ }
+ }
+
+ NVIC_EnableIRQ(USB0_IRQn);
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/read_uid.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/read_uid.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,38 @@
+/**
+ * @file read_uid.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef READ_UID_H
+#define READ_UID_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void read_unique_id(uint32_t *id);
+void create_unique_id(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/sdk.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/sdk.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,35 @@
+/**
+ * @file sdk.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef SDK_H
+#define SDK_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void sdk_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/DAP_config.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/DAP_config.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,544 @@
+/**
+ * @file DAP_config.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __DAP_CONFIG_H__
+#define __DAP_CONFIG_H__
+
+#include "stm32f1xx.h"
+#include "stdint.h"
+#include "cmsis_os2.h"
+#include "IO_Config.h"
+#include "uart.h"
+//#include "debug_cm.h"
+//#include "swd_host.h"
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
+\ingroup DAP_ConfigIO_gr
+@{
+Provides definitions about:
+ - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
+ - Debug Unit communication packet size.
+ - Debug Access Port communication mode (JTAG or SWD).
+ - Optional information about a connected Target Device (for Evaluation Boards).
+*/
+
+/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
+/// This value is used to calculate the SWD/JTAG clock speed.
+#define CPU_CLOCK SystemCoreClock ///< Specifies the CPU Clock in Hz
+
+/// Number of processor cycles for I/O Port write operations.
+/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
+/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
+/// requrie 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
+/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
+/// requrired.
+#define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
+
+/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available
+
+/// Indicate that JTAG communication mode is available at the Debug Port.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available.
+
+/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
+/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
+#define DAP_JTAG_DEV_CNT 0 ///< Maximum number of JTAG devices on scan chain
+
+/// Default communication mode on the Debug Access Port.
+/// Used for the command \ref DAP_Connect when Port Default mode is selected.
+#define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
+
+/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
+/// Used to initialize the default SWD/JTAG clock frequency.
+/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
+#define DAP_DEFAULT_SWJ_CLOCK 5000000 ///< Default SWD/JTAG clock frequency in Hz.
+
+/// Maximum Package Size for Command and Response data.
+/// This configuration settings is used to optimized the communication performance with the
+/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
+#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed.
+
+/// Maximum Package Buffers for Command and Response data.
+/// This configuration settings is used to optimized the communication performance with the
+/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
+/// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
+#define DAP_PACKET_COUNT 4 ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
+
+/// Indicate that UART Serial Wire Output (SWO) trace is available.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available
+
+/// Maximum SWO UART Baudrate
+#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz
+
+/// Indicate that Manchester Serial Wire Output (SWO) trace is available.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available
+
+/// SWO Trace Buffer Size.
+#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n)
+
+/// SWO Streaming Trace.
+#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available.
+
+/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
+#define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported).
+
+
+/// Debug Unit is connected to fixed Target Device.
+/// The Debug Unit may be part of an evaluation board and always connected to a fixed
+/// known device. In this case a Device Vendor and Device Name string is stored which
+/// may be used by the debugger or IDE to configure device parameters.
+#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
+
+#if TARGET_DEVICE_FIXED
+#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor
+#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device
+#endif
+
+///@}
+
+
+__STATIC_INLINE void pin_out_init(GPIO_TypeDef* GPIOx, uint8_t pin_bit)
+{
+ if(pin_bit >= 8)
+ {
+ GPIOx->CRH &= ~(0x0000000F << ((pin_bit-8) << 2));
+ GPIOx->CRH |= ( ((uint32_t)(0x00|0x03) & 0x0F) << ((pin_bit-8) << 2) );
+ }
+ else
+ {
+ GPIOx->CRL &= ~(0x0000000F << ((pin_bit) << 2));
+ GPIOx->CRL |= ( ((uint32_t)(0x00|0x03) & 0x0F) << ((pin_bit) << 2) );
+ }
+}
+
+__STATIC_INLINE void pin_out_od_init(GPIO_TypeDef* GPIOx, uint8_t pin_bit)
+{
+ if(pin_bit >= 8)
+ {
+ GPIOx->CRH &= ~(0x0000000F << ((pin_bit-8) << 2));
+ GPIOx->CRH |= ( ((uint32_t)(0x04|0x03) & 0x0F) << ((pin_bit-8) << 2) );
+ }
+ else
+ {
+ GPIOx->CRL &= ~(0x0000000F << ((pin_bit) << 2));
+ GPIOx->CRL |= ( ((uint32_t)(0x04|0x03) & 0x0F) << ((pin_bit) << 2) );
+ }
+}
+
+__STATIC_INLINE void pin_in_init(GPIO_TypeDef* GPIOx, uint8_t pin_bit, uint8_t mode)
+{
+ uint8_t config;
+ if(mode == 1)
+ config = 0x08; //Up
+ else if(mode == 2)
+ config = 0x08; //down
+ else
+ config = 0x00; //GPIO_Mode_AIN
+
+ if(pin_bit >= 8)
+ {
+ GPIOx->CRH &= ~(0x0000000F << ((pin_bit-8) << 2));
+ GPIOx->CRH |= ( ((uint32_t)(config) & 0x0F) << ((pin_bit-8) << 2) );
+ if(mode == 1)
+ GPIOx->BSRR = (((uint32_t)0x01) << pin_bit);
+ else if(mode == 2)
+ GPIOx->BRR = (((uint32_t)0x01) << pin_bit);
+ }
+ else
+ {
+ GPIOx->CRL &= ~(0x0000000F << ((pin_bit) << 2));
+ GPIOx->CRL |= ( ((uint32_t)(config) & 0x0F) << ((pin_bit) << 2) );
+ if(mode == 1)
+ GPIOx->BSRR = (((uint32_t)0x01) << pin_bit);
+ else if(mode == 2)
+ GPIOx->BRR = (((uint32_t)0x01) << pin_bit);
+ }
+}
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
+\ingroup DAP_ConfigIO_gr
+@{
+
+Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
+and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
+interface of a device. The following I/O Pins are provided:
+
+JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
+---------------------------- | -------------------- | ---------------------------------------------
+TCK: Test Clock | SWCLK: Clock | Output Push/Pull
+TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
+TDI: Test Data Input | | Output Push/Pull
+TDO: Test Data Output | | Input
+nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
+nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
+
+
+DAP Hardware I/O Pin Access Functions
+-------------------------------------
+The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
+these I/O Pins.
+
+For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
+This functions are provided to achieve faster I/O that is possible with some advanced GPIO
+peripherals that can independently write/read a single I/O pin without affecting any other pins
+of the same I/O port. The following SWDIO I/O Pin functions are provided:
+ - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
+ - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
+ - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
+ - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
+*/
+
+
+// Configure DAP I/O pins ------------------------------
+
+/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
+Configures the DAP Hardware I/O pins for JTAG mode:
+ - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
+ - TDO to input mode.
+*/
+__STATIC_INLINE void PORT_JTAG_SETUP(void)
+{
+#if (DAP_JTAG != 0)
+
+#endif
+}
+
+/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
+Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
+ - SWCLK, SWDIO, nRESET to output mode and set to default high level.
+ - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
+*/
+__STATIC_INLINE void PORT_SWD_SETUP(void)
+{
+ // Set SWCLK HIGH
+ pin_out_init(SWCLK_TCK_PIN_PORT, SWCLK_TCK_PIN_Bit);
+ SWCLK_TCK_PIN_PORT->BSRR = SWCLK_TCK_PIN;
+ // Set SWDIO HIGH
+ pin_out_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit);
+ SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
+
+ pin_in_init(SWDIO_IN_PIN_PORT, SWDIO_IN_PIN_Bit, 1);
+ // Set RESET HIGH
+ pin_out_od_init(nRESET_PIN_PORT, nRESET_PIN_Bit);//TODO - fix reset logic
+ nRESET_PIN_PORT->BSRR = nRESET_PIN;
+}
+
+/** Disable JTAG/SWD I/O Pins.
+Disables the DAP Hardware I/O pins which configures:
+ - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
+*/
+__STATIC_INLINE void PORT_OFF(void)
+{
+ pin_in_init(SWCLK_TCK_PIN_PORT, SWCLK_TCK_PIN_Bit, 0);
+ pin_in_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit, 0);
+ pin_in_init(SWDIO_IN_PIN_PORT, SWDIO_IN_PIN_Bit, 0);
+}
+
+// SWCLK/TCK I/O pin -------------------------------------
+
+/** SWCLK/TCK I/O pin: Get Input.
+\return Current status of the SWCLK/TCK DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void)
+{
+ return ((SWCLK_TCK_PIN_PORT->ODR & SWCLK_TCK_PIN) ? 1 : 0);
+}
+
+/** SWCLK/TCK I/O pin: Set Output to High.
+Set the SWCLK/TCK DAP hardware I/O pin to high level.
+*/
+__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET(void)
+{
+ SWCLK_TCK_PIN_PORT->BSRR = SWCLK_TCK_PIN;
+}
+
+/** SWCLK/TCK I/O pin: Set Output to Low.
+Set the SWCLK/TCK DAP hardware I/O pin to low level.
+*/
+__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void)
+{
+ SWCLK_TCK_PIN_PORT->BRR = SWCLK_TCK_PIN;
+}
+
+// SWDIO/TMS Pin I/O --------------------------------------
+
+/** SWDIO/TMS I/O pin: Get Input.
+\return Current status of the SWDIO/TMS DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void)
+{
+ return ((SWDIO_IN_PIN_PORT->IDR & SWDIO_IN_PIN) ? 1 : 0);
+}
+
+/** SWDIO/TMS I/O pin: Set Output to High.
+Set the SWDIO/TMS DAP hardware I/O pin to high level.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET(void)
+{
+ SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
+}
+
+/** SWDIO/TMS I/O pin: Set Output to Low.
+Set the SWDIO/TMS DAP hardware I/O pin to low level.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void)
+{
+ SWDIO_OUT_PIN_PORT->BRR = SWDIO_OUT_PIN;
+}
+
+/** SWDIO I/O pin: Get Input (used in SWD mode only).
+\return Current status of the SWDIO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
+{
+ return ((SWDIO_IN_PIN_PORT->IDR & SWDIO_IN_PIN) ? 1 : 0);
+}
+
+/** SWDIO I/O pin: Set Output (used in SWD mode only).
+\param bit Output value for the SWDIO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT(uint32_t bit)
+{
+ if (bit & 1)
+ SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
+ else
+ SWDIO_OUT_PIN_PORT->BRR = SWDIO_OUT_PIN;
+}
+
+/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
+Configure the SWDIO DAP hardware I/O pin to output mode. This function is
+called prior \ref PIN_SWDIO_OUT function calls.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void)
+{
+ pin_out_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit);
+ SWDIO_OUT_PIN_PORT->BRR = SWDIO_OUT_PIN;
+}
+
+/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
+Configure the SWDIO DAP hardware I/O pin to input mode. This function is
+called prior \ref PIN_SWDIO_IN function calls.
+*/
+__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void)
+{
+ pin_in_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit, 0);
+ SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
+}
+
+
+// TDI Pin I/O ---------------------------------------------
+
+/** TDI I/O pin: Get Input.
+\return Current status of the TDI DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void)
+{
+ return (0); // Not available
+}
+
+/** TDI I/O pin: Set Output.
+\param bit Output value for the TDI DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE void PIN_TDI_OUT(uint32_t bit)
+{
+ ; // Not available
+}
+
+
+// TDO Pin I/O ---------------------------------------------
+
+/** TDO I/O pin: Get Input.
+\return Current status of the TDO DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void)
+{
+ return (0); // Not available
+}
+
+
+// nTRST Pin I/O -------------------------------------------
+
+/** nTRST I/O pin: Get Input.
+\return Current status of the nTRST DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void)
+{
+ return (0); // Not available
+}
+
+/** nTRST I/O pin: Set Output.
+\param bit JTAG TRST Test Reset pin status:
+ - 0: issue a JTAG TRST Test Reset.
+ - 1: release JTAG TRST Test Reset.
+*/
+__STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit)
+{
+ ; // Not available
+}
+
+// nRESET Pin I/O------------------------------------------
+
+/** nRESET I/O pin: Get Input.
+\return Current status of the nRESET DAP hardware I/O pin.
+*/
+__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void)
+{
+ return ((nRESET_PIN_PORT->IDR >> nRESET_PIN_Bit) & 1);
+}
+
+/** nRESET I/O pin: Set Output.
+\param bit target device hardware reset pin status:
+ - 0: issue a device hardware reset.
+ - 1: release device hardware reset.
+*/
+// TODO - sw specific implementation should be created
+
+__STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit)
+{
+ if (bit & 1)
+ nRESET_PIN_PORT->BSRR = nRESET_PIN;
+ else
+ nRESET_PIN_PORT->BRR = nRESET_PIN;
+}
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
+\ingroup DAP_ConfigIO_gr
+@{
+
+CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
+
+It is recommended to provide the following LEDs for status indication:
+ - Connect LED: is active when the DAP hardware is connected to a debugger.
+ - Running LED: is active when the debugger has put the target device into running state.
+*/
+
+/** Debug Unit: Set status of Connected LED.
+\param bit status of the Connect LED.
+ - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
+ - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
+*/
+__STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit)
+{
+ if (bit & 1)
+ CONNECTED_LED_PORT->BRR = CONNECTED_LED_PIN; // LED on
+ else
+ CONNECTED_LED_PORT->BSRR = CONNECTED_LED_PIN;// LED off
+}
+
+/** Debug Unit: Set status Target Running LED.
+\param bit status of the Target Running LED.
+ - 1: Target Running LED ON: program execution in target started.
+ - 0: Target Running LED OFF: program execution in target stopped.
+*/
+__STATIC_INLINE void LED_RUNNING_OUT(uint32_t bit)
+{
+ ; // Not available
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
+\ingroup DAP_ConfigIO_gr
+@{
+Access function for Test Domain Timer.
+
+The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
+default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
+
+*/
+
+/** Get timestamp of Test Domain Timer.
+\return Current timestamp value.
+*/
+__STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
+ return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK);
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
+\ingroup DAP_ConfigIO_gr
+@{
+
+CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
+*/
+
+/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
+This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
+Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
+ - I/O clock system enabled.
+ - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
+ - for nTRST, nRESET a weak pull-up (if available) is enabled.
+ - LED output pins are enabled and LEDs are turned off.
+*/
+__STATIC_INLINE void DAP_SETUP(void)
+{
+ /* Enable port clock */
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+ /* Configure I/O pin SWCLK */
+ pin_out_init(SWCLK_TCK_PIN_PORT, SWCLK_TCK_PIN_Bit);
+ SWCLK_TCK_PIN_PORT->BSRR = SWCLK_TCK_PIN;
+
+ pin_out_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit);
+ SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
+
+ pin_in_init(SWDIO_IN_PIN_PORT, SWDIO_IN_PIN_Bit, 1);
+
+ pin_out_od_init(nRESET_PIN_PORT, nRESET_PIN_Bit);
+ nRESET_PIN_PORT->BSRR = nRESET_PIN;
+
+ pin_out_init(CONNECTED_LED_PORT, CONNECTED_LED_PIN_Bit);
+ CONNECTED_LED_PORT->BSRR = CONNECTED_LED_PIN;
+}
+
+/** Reset Target Device with custom specific I/O pin or command sequence.
+This function allows the optional implementation of a device specific reset sequence.
+It is called when the command \ref DAP_ResetTarget and is for example required
+when a device needs a time-critical unlock sequence that enables the debug port.
+\return 0 = no device specific reset sequence is implemented.\n
+ 1 = a device specific reset sequence is implemented.
+*/
+__STATIC_INLINE uint32_t RESET_TARGET(void)
+{
+ return (0); // change to '1' when a device reset sequence is implemented
+}
+
+///@}
+
+
+#endif /* __DAP_CONFIG_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/IO_Config.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/stm32/stm32f103xb/IO_Config.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,86 @@ +/** + * @file IO_Config.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ + +#include "stm32f1xx.h" +#include "compiler.h" +#include "daplink.h" + +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_STM32F103XB); + +//USB control pin +#define USB_CONNECT_PORT_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define USB_CONNECT_PORT_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() +#define USB_CONNECT_PORT GPIOA +#define USB_CONNECT_PIN GPIO_PIN_15 +#define USB_CONNECT_ON() (USB_CONNECT_PORT->BSRR = USB_CONNECT_PIN) +#define USB_CONNECT_OFF() (USB_CONNECT_PORT->BRR = USB_CONNECT_PIN) + +//Connected LED +#define CONNECTED_LED_PORT GPIOB +#define CONNECTED_LED_PIN GPIO_PIN_6 +#define CONNECTED_LED_PIN_Bit 6 + +//When bootloader, disable the target port(not used) +#define POWER_EN_PIN_PORT GPIOB +#define POWER_EN_PIN GPIO_PIN_15 +#define POWER_EN_Bit 15 + +// nRESET OUT Pin +#define nRESET_PIN_PORT GPIOB +#define nRESET_PIN GPIO_PIN_0 +#define nRESET_PIN_Bit 0 + +//SWD +#define SWCLK_TCK_PIN_PORT GPIOB +#define SWCLK_TCK_PIN GPIO_PIN_13 +#define SWCLK_TCK_PIN_Bit 13 + +#define SWDIO_OUT_PIN_PORT GPIOB +#define SWDIO_OUT_PIN GPIO_PIN_14 +#define SWDIO_OUT_PIN_Bit 14 + +#define SWDIO_IN_PIN_PORT GPIOB +#define SWDIO_IN_PIN GPIO_PIN_12 +#define SWDIO_IN_PIN_Bit 12 + +//LEDs +//USB status LED +#define RUNNING_LED_PORT GPIOA +#define RUNNING_LED_PIN GPIO_PIN_9 +#define RUNNING_LED_Bit 9 + +#define PIN_HID_LED_PORT GPIOA +#define PIN_HID_LED GPIO_PIN_9 +#define PIN_HID_LED_Bit 9 + +#define PIN_CDC_LED_PORT GPIOA +#define PIN_CDC_LED GPIO_PIN_9 +#define PIN_CDC_LED_Bit 9 + +#define PIN_MSC_LED_PORT GPIOA +#define PIN_MSC_LED GPIO_PIN_9 +#define PIN_MSC_LED_Bit 9 + + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,3123 @@
+/**
+ ******************************************************************************
+ * @file stm32_hal_legacy.h
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief This file contains aliases definition for the STM32Cube HAL constants
+ * macros and functions maintained for legacy purpose.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_HAL_LEGACY
+#define __STM32_HAL_LEGACY
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define AES_FLAG_RDERR CRYP_FLAG_RDERR
+#define AES_FLAG_WRERR CRYP_FLAG_WRERR
+#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
+#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
+#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
+#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
+#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
+#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
+#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
+#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
+#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
+#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
+#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
+#define REGULAR_GROUP ADC_REGULAR_GROUP
+#define INJECTED_GROUP ADC_INJECTED_GROUP
+#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
+#define AWD_EVENT ADC_AWD_EVENT
+#define AWD1_EVENT ADC_AWD1_EVENT
+#define AWD2_EVENT ADC_AWD2_EVENT
+#define AWD3_EVENT ADC_AWD3_EVENT
+#define OVR_EVENT ADC_OVR_EVENT
+#define JQOVF_EVENT ADC_JQOVF_EVENT
+#define ALL_CHANNELS ADC_ALL_CHANNELS
+#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
+#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
+#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
+#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
+#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
+#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
+#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
+#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
+#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
+#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
+#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
+#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
+#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
+#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
+#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
+#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
+#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
+#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
+#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
+
+#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
+#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
+#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
+#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
+#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
+#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
+#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
+#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
+#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
+#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
+#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
+#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
+#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
+#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
+#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
+#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32L0) || defined(STM32L4)
+#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+
+#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
+#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
+#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
+
+#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
+#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
+#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
+#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
+#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
+#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
+#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
+#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
+#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
+
+#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
+#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
+
+/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
+/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
+#if defined(COMP_CSR_LOCK)
+#define COMP_FLAG_LOCK COMP_CSR_LOCK
+#elif defined(COMP_CSR_COMP1LOCK)
+#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
+#elif defined(COMP_CSR_COMPxLOCK)
+#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
+#endif
+
+#if defined(STM32L4)
+#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
+#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
+#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
+#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
+#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
+#endif
+
+#if defined(STM32L0)
+#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
+#else
+#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
+#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
+#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
+#endif
+
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
+#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define DAC1_CHANNEL_1 DAC_CHANNEL_1
+#define DAC1_CHANNEL_2 DAC_CHANNEL_2
+#define DAC2_CHANNEL_1 DAC_CHANNEL_1
+#define DAC_WAVE_NONE ((uint32_t)0x00000000U)
+#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
+#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
+#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
+#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
+#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
+#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
+#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
+#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
+#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
+#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
+#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
+#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
+#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
+#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
+#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
+
+#define IS_HAL_REMAPDMA IS_DMA_REMAP
+#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
+#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
+
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
+#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
+#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
+#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
+#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
+#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
+#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
+#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
+#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
+#define OBEX_PCROP OPTIONBYTE_PCROP
+#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
+#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
+#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
+#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
+#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
+#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
+#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
+#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
+#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
+#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
+#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
+#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
+#define PAGESIZE FLASH_PAGE_SIZE
+#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
+#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
+#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
+#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
+#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
+#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
+#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
+#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
+#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
+#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
+#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
+#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
+#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
+#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
+#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
+#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
+#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
+#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
+#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
+#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
+#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
+#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
+#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
+#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
+#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
+#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
+#define OB_WDG_SW OB_IWDG_SW
+#define OB_WDG_HW OB_IWDG_HW
+#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
+#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
+#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
+#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
+#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
+#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
+#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
+#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
+/**
+ * @}
+ */
+
+
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
+ * @{
+ */
+#if defined(STM32L4) || defined(STM32F7)
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
+#else
+#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
+#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
+#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
+#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
+/**
+ * @}
+ */
+
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define GET_GPIO_SOURCE GPIO_GET_INDEX
+#define GET_GPIO_INDEX GPIO_GET_INDEX
+
+#if defined(STM32F4)
+#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
+#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
+#endif
+
+#if defined(STM32F7)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32L4)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
+#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
+#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
+
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
+
+#if defined(STM32L1)
+ #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
+ #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
+ #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
+ #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L1 */
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
+ #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+ #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+ #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
+#endif /* STM32F0 || STM32F3 || STM32F1 */
+
+#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
+
+#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
+#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
+#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
+#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
+#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
+#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
+#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
+#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
+#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
+#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
+#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
+#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
+#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
+#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
+#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define KR_KEY_RELOAD IWDG_KEY_RELOAD
+#define KR_KEY_ENABLE IWDG_KEY_ENABLE
+#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
+#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
+
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
+
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/* The following 3 definition have also been present in a temporary version of lptim.h */
+/* They need to be renamed also to the right name, just in case */
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
+#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
+#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
+#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
+
+#define NAND_AddressTypedef NAND_AddressTypeDef
+
+#define __ARRAY_ADDRESS ARRAY_ADDRESS
+#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
+#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
+#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
+#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
+#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
+#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
+#define NOR_ERROR HAL_NOR_STATUS_ERROR
+#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
+
+#define __NOR_WRITE NOR_WRITE
+#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
+#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
+#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
+#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
+
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
+
+#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
+#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
+#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
+#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
+#if defined(STM32F7)
+ #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA ATA_DATA
+#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
+#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
+#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
+#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
+#define CF_CARD_HEAD ATA_CARD_HEAD
+#define CF_STATUS_CMD ATA_STATUS_CMD
+#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
+#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
+#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
+#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
+#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
+
+#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
+#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
+#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
+#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
+#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define FORMAT_BIN RTC_FORMAT_BIN
+#define FORMAT_BCD RTC_FORMAT_BCD
+
+#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+
+#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
+
+#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
+#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
+#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
+
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
+#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
+#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
+#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
+
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+
+#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
+#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
+
+#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
+#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
+#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
+#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
+#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
+#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
+#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
+#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
+#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
+#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
+#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
+#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
+#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
+
+#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
+#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
+
+#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
+#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
+#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
+
+#define TIM_DMABase_CR1 TIM_DMABASE_CR1
+#define TIM_DMABase_CR2 TIM_DMABASE_CR2
+#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
+#define TIM_DMABase_DIER TIM_DMABASE_DIER
+#define TIM_DMABase_SR TIM_DMABASE_SR
+#define TIM_DMABase_EGR TIM_DMABASE_EGR
+#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
+#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
+#define TIM_DMABase_CCER TIM_DMABASE_CCER
+#define TIM_DMABase_CNT TIM_DMABASE_CNT
+#define TIM_DMABase_PSC TIM_DMABASE_PSC
+#define TIM_DMABase_ARR TIM_DMABASE_ARR
+#define TIM_DMABase_RCR TIM_DMABASE_RCR
+#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
+#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
+#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
+#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
+#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
+#define TIM_DMABase_DCR TIM_DMABASE_DCR
+#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
+#define TIM_DMABase_OR1 TIM_DMABASE_OR1
+#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
+#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
+#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
+#define TIM_DMABase_OR2 TIM_DMABASE_OR2
+#define TIM_DMABase_OR3 TIM_DMABASE_OR3
+#define TIM_DMABase_OR TIM_DMABASE_OR
+
+#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
+#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
+#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
+#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
+#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
+#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
+#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
+#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
+#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
+
+#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
+#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
+#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
+#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
+#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
+#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
+#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
+#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
+#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
+#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
+#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
+#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
+#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
+#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
+#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
+#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
+#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
+#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
+#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+
+#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
+#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
+
+#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
+#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
+#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
+#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
+
+#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
+#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
+#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
+#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
+
+#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
+#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
+#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
+
+#define USARTNACK_ENABLED USART_NACK_ENABLE
+#define USARTNACK_DISABLED USART_NACK_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CFR_BASE WWDG_CFR_BASE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
+#define CAN_IT_RQCP0 CAN_IT_TME
+#define CAN_IT_RQCP1 CAN_IT_TME
+#define CAN_IT_RQCP2 CAN_IT_TME
+#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
+#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
+#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define VLAN_TAG ETH_VLAN_TAG
+#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
+#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
+#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
+#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
+#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
+#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
+#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
+
+#define ETH_MMCCR ((uint32_t)0x00000100U)
+#define ETH_MMCRIR ((uint32_t)0x00000104U)
+#define ETH_MMCTIR ((uint32_t)0x00000108U)
+#define ETH_MMCRIMR ((uint32_t)0x0000010CU)
+#define ETH_MMCTIMR ((uint32_t)0x00000110U)
+#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU)
+#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U)
+#define ETH_MMCTGFCR ((uint32_t)0x00000168U)
+#define ETH_MMCRFCECR ((uint32_t)0x00000194U)
+#define ETH_MMCRFAECR ((uint32_t)0x00000198U)
+#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
+
+#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
+#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
+#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
+#if defined(STM32F1)
+#else
+#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#endif
+#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
+#define DCMI_IT_OVF DCMI_IT_OVR
+#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
+#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
+
+#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
+#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
+#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
+
+/**
+ * @}
+ */
+
+#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
+#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
+#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
+#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
+#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
+
+#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
+#define CM_RGB888 DMA2D_INPUT_RGB888
+#define CM_RGB565 DMA2D_INPUT_RGB565
+#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
+#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
+#define CM_L8 DMA2D_INPUT_L8
+#define CM_AL44 DMA2D_INPUT_AL44
+#define CM_AL88 DMA2D_INPUT_AL88
+#define CM_L4 DMA2D_INPUT_L4
+#define CM_A8 DMA2D_INPUT_A8
+#define CM_A4 DMA2D_INPUT_A4
+/**
+ * @}
+ */
+#endif /* STM32L4xx || STM32F7*/
+
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
+#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
+#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
+
+/*HASH Algorithm Selection*/
+
+#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
+#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
+#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
+#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
+
+#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
+#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
+
+#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
+#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
+#if defined(STM32L0)
+#else
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#endif
+#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
+#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
+#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
+#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
+#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
+#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
+#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
+
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
+#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
+#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
+#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
+
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
+ * @{
+ */
+#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
+#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
+#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
+#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
+#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
+#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
+#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
+#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
+#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
+#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
+#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
+#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
+#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
+#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
+
+#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
+#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
+#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
+#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
+#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
+#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
+#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
+
+#define CR_OFFSET_BB PWR_CR_OFFSET_BB
+#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
+
+#define DBP_BitNumber DBP_BIT_NUMBER
+#define PVDE_BitNumber PVDE_BIT_NUMBER
+#define PMODE_BitNumber PMODE_BIT_NUMBER
+#define EWUP_BitNumber EWUP_BIT_NUMBER
+#define FPDS_BitNumber FPDS_BIT_NUMBER
+#define ODEN_BitNumber ODEN_BIT_NUMBER
+#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
+#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
+#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
+#define BRE_BitNumber BRE_BIT_NUMBER
+
+#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
+
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
+#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
+#define HAL_TIM_DMAError TIM_DMAError
+#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
+#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define AES_IT_CC CRYP_IT_CC
+#define AES_IT_ERR CRYP_IT_ERR
+#define AES_FLAG_CCF CRYP_FLAG_CCF
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
+#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
+#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
+#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
+#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
+#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
+#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
+#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
+#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
+#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
+#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
+#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
+#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
+
+#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
+#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
+#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
+#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __ADC_ENABLE __HAL_ADC_ENABLE
+#define __ADC_DISABLE __HAL_ADC_DISABLE
+#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
+#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
+#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
+#define __ADC_IS_ENABLED ADC_IS_ENABLE
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
+#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
+
+#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
+#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
+#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
+#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
+#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
+#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
+#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
+#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
+#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
+#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
+#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
+#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
+#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
+#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
+
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
+#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
+#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
+#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
+#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
+
+#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
+#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
+#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
+#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
+#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
+
+#define __HAL_ADC_SQR1 ADC_SQR1
+#define __HAL_ADC_SMPR1 ADC_SMPR1
+#define __HAL_ADC_SMPR2 ADC_SMPR2
+#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
+#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
+#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
+#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
+#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
+#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
+#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
+#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
+#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR ADC_JSQR
+
+#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
+#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
+#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
+#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
+#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
+#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
+#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
+#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
+#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
+
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
+
+
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32F3)
+#define COMP_START __HAL_COMP_ENABLE
+#define COMP_STOP __HAL_COMP_DISABLE
+#define COMP_LOCK __HAL_COMP_LOCK
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F302xE) || defined(STM32F302xC)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP7_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F373xC) ||defined(STM32F378xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+# endif
+#else
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+
+#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
+
+#if defined(STM32L0) || defined(STM32L4)
+/* Note: On these STM32 families, the only argument of this macro */
+/* is COMP_FLAG_LOCK. */
+/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
+/* argument. */
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
+#endif
+/**
+ * @}
+ */
+
+#if defined(STM32L0) || defined(STM32L4)
+/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+/**
+ * @}
+ */
+#endif
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
+ ((WAVE) == DAC_WAVE_NOISE)|| \
+ ((WAVE) == DAC_WAVE_TRIANGLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_WRPAREA IS_OB_WRPAREA
+#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
+#define IS_TYPEERASE IS_FLASH_TYPEERASE
+#define IS_NBSECTORS IS_FLASH_NBSECTORS
+#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
+#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
+#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
+#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
+#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
+#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
+#define __HAL_I2C_SPEED I2C_SPEED
+#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
+#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
+#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
+#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
+#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
+#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
+#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
+#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
+#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __IRDA_DISABLE __HAL_IRDA_DISABLE
+#define __IRDA_ENABLE __HAL_IRDA_ENABLE
+
+#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+
+#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
+#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
+#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
+#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
+#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
+#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
+#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
+#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
+#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
+#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
+#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
+#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
+#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
+#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
+#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
+#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
+#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
+#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
+#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
+
+#if defined (STM32F4)
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
+#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
+#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
+#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
+#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
+#endif /* STM32F4 */
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
+ * @{
+ */
+
+#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
+#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
+
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+
+#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
+#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
+#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
+#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
+#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
+#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
+#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
+#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
+#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
+#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
+#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
+#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
+#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
+#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
+#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
+#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
+#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
+#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
+#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
+#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
+#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
+#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
+#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
+#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
+#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
+#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
+#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
+#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
+#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
+#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
+#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
+#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
+#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
+#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
+#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
+#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
+#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
+#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
+#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
+#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
+#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
+
+#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
+#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
+#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
+#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
+#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
+#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
+#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
+#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
+#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
+#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
+#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
+#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
+#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
+#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
+#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
+#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
+#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
+#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
+#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
+#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
+#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
+#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
+#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
+#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
+#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
+#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
+#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
+#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
+#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
+#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
+#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
+#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
+#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
+#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
+#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
+#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
+#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
+#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
+#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
+#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
+#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
+#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
+#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
+#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
+#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
+#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
+#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
+#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
+#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
+#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
+#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
+#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
+#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
+#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
+#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
+#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
+#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
+#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
+#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
+#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
+#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
+#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
+#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
+#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
+#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
+#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
+#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
+#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
+#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
+#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
+#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
+#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
+#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
+#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
+#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
+#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
+#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
+#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
+#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
+#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
+#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
+#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
+#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
+#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
+#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
+#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
+#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
+#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
+#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
+#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
+#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
+#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
+#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
+#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
+#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
+#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
+#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
+#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
+#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
+#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
+#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
+#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
+#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
+#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+
+/* alias define maintained for legacy */
+#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+
+#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
+#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
+#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
+#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
+#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
+#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
+#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
+#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
+#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
+#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
+#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
+#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
+#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
+#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
+#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
+#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
+#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
+#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
+
+#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
+#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
+#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
+#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
+#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
+#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
+#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
+#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
+#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
+#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
+#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
+#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
+#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
+#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
+#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
+#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
+#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
+#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
+
+#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
+#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
+#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
+#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
+#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
+#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
+#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
+#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
+#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
+#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
+#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
+#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
+#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
+#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
+#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
+#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
+#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
+#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
+#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
+#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
+#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
+#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
+#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
+#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
+#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
+#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
+#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
+#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
+#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
+#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
+#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
+#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
+#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
+#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
+#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
+#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
+#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
+#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
+#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
+#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
+#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
+#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
+#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
+#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
+#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
+#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
+#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
+#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
+#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
+#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
+#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
+#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
+#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
+#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
+#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
+#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
+#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
+#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
+#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
+#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
+#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
+#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
+#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
+#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
+#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
+#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
+#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
+#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
+#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
+#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
+#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
+#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
+#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
+#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
+#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
+#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
+#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
+#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
+#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
+#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
+#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
+#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
+#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
+#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
+#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
+#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
+#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
+#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
+#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
+#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
+#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
+#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
+#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
+#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
+#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
+#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
+#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
+#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
+#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
+#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
+#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
+#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
+#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
+#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
+#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
+#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
+#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
+#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
+#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
+#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
+#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
+#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
+#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
+#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
+
+#if defined(STM32F4)
+#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
+#define Sdmmc1ClockSelection SdioClockSelection
+#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
+#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
+#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
+#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
+#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
+#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
+#define SdioClockSelection Sdmmc1ClockSelection
+#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
+#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
+#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
+#endif
+
+#if defined(STM32F7)
+#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
+#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
+#endif
+
+#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
+#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
+
+#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
+
+#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
+#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
+#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
+#define IS_RCC_HCLK_DIV IS_RCC_PCLK
+#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
+
+#define RCC_IT_HSI14 RCC_IT_HSI14RDY
+
+#if defined(STM32L0)
+#define RCC_IT_LSECSS RCC_IT_CSSLSE
+#define RCC_IT_CSS RCC_IT_CSSHSE
+#endif
+
+#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
+#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
+#define RCC_MCO_NODIV RCC_MCODIV_1
+#define RCC_MCO_DIV1 RCC_MCODIV_1
+#define RCC_MCO_DIV2 RCC_MCODIV_2
+#define RCC_MCO_DIV4 RCC_MCODIV_4
+#define RCC_MCO_DIV8 RCC_MCODIV_8
+#define RCC_MCO_DIV16 RCC_MCODIV_16
+#define RCC_MCO_DIV32 RCC_MCODIV_32
+#define RCC_MCO_DIV64 RCC_MCODIV_64
+#define RCC_MCO_DIV128 RCC_MCODIV_128
+#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
+#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
+#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
+#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
+#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
+#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
+#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
+#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
+
+#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
+
+#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
+#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
+#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
+#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
+#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
+#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
+
+#define HSION_BitNumber RCC_HSION_BIT_NUMBER
+#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
+#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
+#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
+#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
+#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
+#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
+#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
+#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
+#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
+#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
+#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
+#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
+#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
+#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
+#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
+#define LSION_BitNumber RCC_LSION_BIT_NUMBER
+#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
+#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
+#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
+#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
+#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
+#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
+#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
+#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
+#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
+#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
+#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
+#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
+#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
+#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
+
+#define CR_HSION_BB RCC_CR_HSION_BB
+#define CR_CSSON_BB RCC_CR_CSSON_BB
+#define CR_PLLON_BB RCC_CR_PLLON_BB
+#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
+#define CR_MSION_BB RCC_CR_MSION_BB
+#define CSR_LSION_BB RCC_CSR_LSION_BB
+#define CSR_LSEON_BB RCC_CSR_LSEON_BB
+#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
+#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
+#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
+#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
+#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
+#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
+#define CR_HSEON_BB RCC_CR_HSEON_BB
+#define CSR_RMVF_BB RCC_CSR_RMVF_BB
+#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
+#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
+
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
+
+#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
+
+#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
+#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
+
+#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
+#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
+#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
+#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
+#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
+#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
+
+#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
+#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
+#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
+#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
+#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
+#define DfsdmClockSelection Dfsdm1ClockSelection
+#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
+#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
+#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
+#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
+#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
+#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
+#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
+
+#if defined (STM32F1)
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
+
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
+
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
+
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
+
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+#endif /* STM32F1 */
+
+#define IS_ALARM IS_RTC_ALARM
+#define IS_ALARM_MASK IS_RTC_ALARM_MASK
+#define IS_TAMPER IS_RTC_TAMPER
+#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
+#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
+#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
+#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
+#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
+#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
+#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
+#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
+#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
+#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
+
+#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
+#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
+#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
+
+#if defined(STM32F4)
+#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
+#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
+#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
+#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
+#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
+#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
+#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
+#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
+#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
+#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
+#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
+#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
+#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
+#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
+#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
+#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
+#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
+#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
+#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
+#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
+/* alias CMSIS */
+#define SDMMC1_IRQn SDIO_IRQn
+#define SDMMC1_IRQHandler SDIO_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
+#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
+#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
+#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
+#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
+#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
+#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
+#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
+#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
+#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
+#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
+#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
+#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
+#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
+#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
+#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
+#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
+#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
+#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
+#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
+/* alias CMSIS for compatibilities */
+#define SDIO_IRQn SDMMC1_IRQn
+#define SDIO_IRQHandler SDMMC1_IRQHandler
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
+#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
+#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
+#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
+#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
+
+#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+
+#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
+#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
+#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
+#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
+#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
+#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
+#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
+#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
+#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
+#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+
+#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
+
+#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
+#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
+#define __USART_ENABLE __HAL_USART_ENABLE
+#define __USART_DISABLE __HAL_USART_DISABLE
+
+#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
+
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+
+#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
+#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
+
+#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
+#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
+
+#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
+
+#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+
+#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
+#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
+#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
+#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
+#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
+#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
+#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
+#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
+#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
+#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
+#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
+#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
+
+#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
+#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
+
+#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
+#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
+#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_LTDC_LAYER LTDC_LAYER
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
+#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
+#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
+#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
+#define SAI_STREOMODE SAI_STEREOMODE
+#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
+#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
+#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
+#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
+#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
+#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
+#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
+#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
+#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32_HAL_LEGACY */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,328 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal.h
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief This file contains all the functions prototypes for the HAL
+ * module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_H
+#define __STM32F1xx_HAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_conf.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HAL
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Macros HAL Exported Macros
+ * @{
+ */
+
+/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
+ * @brief Freeze/Unfreeze Peripherals in Debug mode
+ * Note: On devices STM32F10xx8 and STM32F10xxB,
+ * STM32F101xC/D/E and STM32F103xC/D/E,
+ * STM32F101xF/G and STM32F103xF/G
+ * STM32F10xx4 and STM32F10xx6
+ * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+ * debug mode (not accessible by the user software in normal mode).
+ * Refer to errata sheet of these devices for more details.
+ * @{
+ */
+
+/* Peripherals on APB1 */
+/**
+ * @brief TIM2 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
+
+/**
+ * @brief TIM3 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
+
+#if defined (DBGMCU_CR_DBG_TIM4_STOP)
+/**
+ * @brief TIM4 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM5_STOP)
+/**
+ * @brief TIM5 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM6_STOP)
+/**
+ * @brief TIM6 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM7_STOP)
+/**
+ * @brief TIM7 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM12_STOP)
+/**
+ * @brief TIM12 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM13_STOP)
+/**
+ * @brief TIM13 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM14_STOP)
+/**
+ * @brief TIM14 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
+#endif
+
+/**
+ * @brief WWDG Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
+
+/**
+ * @brief IWDG Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
+
+/**
+ * @brief I2C1 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
+
+#if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
+/**
+ * @brief I2C2 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
+#endif
+
+#if defined (DBGMCU_CR_DBG_CAN1_STOP)
+/**
+ * @brief CAN1 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_CAN2_STOP)
+/**
+ * @brief CAN2 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
+#endif
+
+/* Peripherals on APB2 */
+#if defined (DBGMCU_CR_DBG_TIM1_STOP)
+/**
+ * @brief TIM1 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM8_STOP)
+/**
+ * @brief TIM8 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM9_STOP)
+/**
+ * @brief TIM9 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM10_STOP)
+/**
+ * @brief TIM10 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM11_STOP)
+/**
+ * @brief TIM11 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
+#endif
+
+
+#if defined (DBGMCU_CR_DBG_TIM15_STOP)
+/**
+ * @brief TIM15 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM16_STOP)
+/**
+ * @brief TIM16 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM17_STOP)
+/**
+ * @brief TIM17 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup HAL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization and de-initialization functions ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group2
+ * @{
+ */
+
+/* Peripheral Control functions ************************************************/
+void HAL_IncTick(void);
+void HAL_Delay(__IO uint32_t Delay);
+uint32_t HAL_GetTick(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+void HAL_DBGMCU_EnableDBGSleepMode(void);
+void HAL_DBGMCU_DisableDBGSleepMode(void);
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,476 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_cortex.h
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief Header file of CORTEX HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_CORTEX_H
+#define __STM32F1xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CORTEX
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types Cortex Exported Types
+ * @{
+ */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+ * @brief MPU Region initialization structure
+ * @{
+ */
+typedef struct
+{
+ uint8_t Enable; /*!< Specifies the status of the region.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
+ uint8_t Number; /*!< Specifies the number of the region to protect.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Number */
+ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
+ uint8_t Size; /*!< Specifies the size of the region to protect.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Size */
+ uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+ uint8_t TypeExtField; /*!< Specifies the TEX field level.
+ This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
+ uint8_t AccessPermission; /*!< Specifies the region access permission type.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
+ uint8_t DisableExec; /*!< Specifies the instruction access status.
+ This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
+ uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
+ uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
+ uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
+}MPU_Region_InitTypeDef;
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+ * @{
+ */
+
+
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+ * @{
+ */
+
+#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
+ 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
+ 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
+ 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
+ 1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
+ 0 bits for subpriority */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
+ * @{
+ */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
+#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
+
+/**
+ * @}
+ */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
+ * @{
+ */
+#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
+#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
+#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
+#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+ * @{
+ */
+#define MPU_REGION_ENABLE ((uint8_t)0x01)
+#define MPU_REGION_DISABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+ * @{
+ */
+#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
+#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+ * @{
+ */
+#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
+ * @{
+ */
+#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
+ * @{
+ */
+#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
+ * @{
+ */
+#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
+#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
+#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
+ * @{
+ */
+#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
+#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
+#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
+#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
+#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
+#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
+#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
+#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
+#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
+#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
+#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
+#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
+#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
+#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
+#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
+#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
+#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
+#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
+#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
+#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
+#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
+#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
+#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
+#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
+#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
+#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
+#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
+#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
+ * @{
+ */
+#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
+#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
+#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
+#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
+#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
+#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+ * @{
+ */
+#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
+#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
+#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
+#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
+#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
+#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
+#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
+#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+ * @{
+ */
+
+/** @defgroup CORTEX_Preemption_Priority_Group_Macro CORTEX Preemption Priority Group
+ * @{
+ */
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_2) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_3) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source
+ * @{
+ */
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+/**
+ * @}
+ */
+#if (__MPU_PRESENT == 1)
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
+ ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+ ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
+
+#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
+
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
+ ((TYPE) == MPU_TEX_LEVEL1) || \
+ ((TYPE) == MPU_TEX_LEVEL2))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
+ ((TYPE) == MPU_REGION_PRIV_RW) || \
+ ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
+ ((TYPE) == MPU_REGION_FULL_ACCESS) || \
+ ((TYPE) == MPU_REGION_PRIV_RO) || \
+ ((TYPE) == MPU_REGION_PRIV_RO_URO))
+
+#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
+ ((NUMBER) == MPU_REGION_NUMBER1) || \
+ ((NUMBER) == MPU_REGION_NUMBER2) || \
+ ((NUMBER) == MPU_REGION_NUMBER3) || \
+ ((NUMBER) == MPU_REGION_NUMBER4) || \
+ ((NUMBER) == MPU_REGION_NUMBER5) || \
+ ((NUMBER) == MPU_REGION_NUMBER6) || \
+ ((NUMBER) == MPU_REGION_NUMBER7))
+
+#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
+ ((SIZE) == MPU_REGION_SIZE_64B) || \
+ ((SIZE) == MPU_REGION_SIZE_128B) || \
+ ((SIZE) == MPU_REGION_SIZE_256B) || \
+ ((SIZE) == MPU_REGION_SIZE_512B) || \
+ ((SIZE) == MPU_REGION_SIZE_1KB) || \
+ ((SIZE) == MPU_REGION_SIZE_2KB) || \
+ ((SIZE) == MPU_REGION_SIZE_4KB) || \
+ ((SIZE) == MPU_REGION_SIZE_8KB) || \
+ ((SIZE) == MPU_REGION_SIZE_16KB) || \
+ ((SIZE) == MPU_REGION_SIZE_32KB) || \
+ ((SIZE) == MPU_REGION_SIZE_64KB) || \
+ ((SIZE) == MPU_REGION_SIZE_128KB) || \
+ ((SIZE) == MPU_REGION_SIZE_256KB) || \
+ ((SIZE) == MPU_REGION_SIZE_512KB) || \
+ ((SIZE) == MPU_REGION_SIZE_1MB) || \
+ ((SIZE) == MPU_REGION_SIZE_2MB) || \
+ ((SIZE) == MPU_REGION_SIZE_4MB) || \
+ ((SIZE) == MPU_REGION_SIZE_8MB) || \
+ ((SIZE) == MPU_REGION_SIZE_16MB) || \
+ ((SIZE) == MPU_REGION_SIZE_32MB) || \
+ ((SIZE) == MPU_REGION_SIZE_64MB) || \
+ ((SIZE) == MPU_REGION_SIZE_128MB) || \
+ ((SIZE) == MPU_REGION_SIZE_256MB) || \
+ ((SIZE) == MPU_REGION_SIZE_512MB) || \
+ ((SIZE) == MPU_REGION_SIZE_1GB) || \
+ ((SIZE) == MPU_REGION_SIZE_2GB) || \
+ ((SIZE) == MPU_REGION_SIZE_4GB))
+
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CORTEX_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CORTEX_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+ * @}
+ */
+
+/** @addtogroup CORTEX_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+#if (__MPU_PRESENT == 1)
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
+ * @brief CORTEX private functions
+ * @{
+ */
+
+#if (__MPU_PRESENT == 1)
+/**
+ * @brief Disables the MPU
+ * @retval None
+ */
+__STATIC_INLINE void HAL_MPU_Disable(void)
+{
+ /* Disable fault exceptions */
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+
+ /* Disable the MPU */
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/**
+ * @brief Enables the MPU
+ * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
+ * NMI, FAULTMASK and privileged accessto the default memory
+ * This parameter can be one of the following values:
+ * @arg MPU_HFNMI_PRIVDEF_NONE
+ * @arg MPU_HARDFAULT_NMI
+ * @arg MPU_PRIVILEGED_DEFAULT
+ * @arg MPU_HFNMI_PRIVDEF
+ * @retval None
+ */
+__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+ /* Enable the MPU */
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+
+ /* Enable fault exceptions */
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+}
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_CORTEX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,214 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_def.h
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief This file contains HAL common defines, enumeration, macros and
+ * structures definitions.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_DEF
+#define __STM32F1xx_HAL_DEF
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+#include "Legacy/stm32_hal_legacy.h"
+#include <stdio.h>
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL Status structures definition
+ */
+typedef enum
+{
+ HAL_OK = 0x00,
+ HAL_ERROR = 0x01,
+ HAL_BUSY = 0x02,
+ HAL_TIMEOUT = 0x03
+} HAL_StatusTypeDef;
+
+/**
+ * @brief HAL Lock structures definition
+ */
+typedef enum
+{
+ HAL_UNLOCKED = 0x00,
+ HAL_LOCKED = 0x01
+} HAL_LockTypeDef;
+
+/* Exported macro ------------------------------------------------------------*/
+
+#define HAL_MAX_DELAY 0xFFFFFFFF
+
+#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
+#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \
+ do{ \
+ (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \
+ (__DMA_HANDLE_).Parent = (__HANDLE__); \
+ } while(0)
+
+#define UNUSED(x) ((void)(x))
+
+/** @brief Reset the Handle's State field.
+ * @param __HANDLE__: specifies the Peripheral Handle.
+ * @note This macro can be used for the following purpose:
+ * - When the Handle is declared as local variable; before passing it as parameter
+ * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
+ * to set to 0 the Handle's "State" field.
+ * Otherwise, "State" field may have any random value and the first time the function
+ * HAL_PPP_Init() is called, the low level hardware initialization will be missed
+ * (i.e. HAL_PPP_MspInit() will not be executed).
+ * - When there is a need to reconfigure the low level hardware: instead of calling
+ * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+ * In this later function, when the Handle's "State" field is set to 0, it will execute the function
+ * HAL_PPP_MspInit() which will reconfigure the low level hardware.
+ * @retval None
+ */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
+
+#if (USE_RTOS == 1)
+ #error " USE_RTOS should be 0 in the current HAL release "
+#else
+ #define __HAL_LOCK(__HANDLE__) \
+ do{ \
+ if((__HANDLE__)->Lock == HAL_LOCKED) \
+ { \
+ return HAL_BUSY; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Lock = HAL_LOCKED; \
+ } \
+ }while (0)
+
+ #define __HAL_UNLOCK(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Lock = HAL_UNLOCKED; \
+ }while (0)
+#endif /* USE_RTOS */
+
+#if defined ( __GNUC__ )
+ #ifndef __weak
+ #define __weak __attribute__((weak))
+ #endif /* __weak */
+ #ifndef __packed
+ #define __packed __attribute__((__packed__))
+ #endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined (__GNUC__) /* GNU Compiler */
+ #ifndef __ALIGN_END
+ #define __ALIGN_END __attribute__ ((aligned (4)))
+ #endif /* __ALIGN_END */
+ #ifndef __ALIGN_BEGIN
+ #define __ALIGN_BEGIN
+ #endif /* __ALIGN_BEGIN */
+#else
+ #ifndef __ALIGN_END
+ #define __ALIGN_END
+ #endif /* __ALIGN_END */
+ #ifndef __ALIGN_BEGIN
+ #if defined (__CC_ARM) /* ARM Compiler */
+ #define __ALIGN_BEGIN __align(4)
+ #elif defined (__ICCARM__) /* IAR Compiler */
+ #define __ALIGN_BEGIN
+ #endif /* __CC_ARM */
+ #endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+/**
+ * @brief __RAM_FUNC definition
+ */
+#if defined ( __CC_ARM )
+/* ARM Compiler
+ ------------
+ RAM functions are defined using the toolchain options.
+ Functions that are executed in RAM should reside in a separate source module.
+ Using the 'Options for File' dialog you can simply change the 'Code / Const'
+ area of a module to a memory space in physical RAM.
+ Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+ dialog.
+*/
+#define __RAM_FUNC HAL_StatusTypeDef
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+ ---------------
+ RAM functions are defined using a specific toolchain keyword "__ramfunc".
+*/
+#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
+
+#elif defined ( __GNUC__ )
+/* GNU Compiler
+ ------------
+ RAM functions are defined using a specific toolchain attribute
+ "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc")))
+
+#endif
+
+/**
+ * @brief __NOINLINE definition
+ */
+#if defined ( __CC_ARM ) || defined ( __GNUC__ )
+/* ARM & GNUCompiler
+ ----------------
+*/
+#define __NOINLINE __attribute__ ( (noinline) )
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+ ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32F1xx_HAL_DEF */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,480 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_dma.h
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief Header file of DMA HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_DMA_H
+#define __STM32F1xx_HAL_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Types DMA Exported Types
+ * @{
+ */
+
+/**
+ * @brief DMA Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
+ from memory to memory or from peripheral to memory.
+ This parameter can be a value of @ref DMA_Data_transfer_direction */
+
+ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
+ This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
+
+ uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
+ This parameter can be a value of @ref DMA_Memory_incremented_mode */
+
+ uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
+ This parameter can be a value of @ref DMA_Peripheral_data_size */
+
+ uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
+ This parameter can be a value of @ref DMA_Memory_data_size */
+
+ uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
+ This parameter can be a value of @ref DMA_mode
+ @note The circular buffer mode cannot be used if the memory-to-memory
+ data transfer is configured on the selected Channel */
+
+ uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
+ This parameter can be a value of @ref DMA_Priority_level */
+} DMA_InitTypeDef;
+
+/**
+ * @brief DMA Configuration enumeration values definition
+ */
+typedef enum
+{
+ DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
+ DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
+
+} DMA_ControlTypeDef;
+
+/**
+ * @brief HAL DMA State structures definition
+ */
+typedef enum
+{
+ HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
+ HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
+ HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
+ HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
+ HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
+ HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
+}HAL_DMA_StateTypeDef;
+
+/**
+ * @brief HAL DMA Error Code structure definition
+ */
+typedef enum
+{
+ HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
+ HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
+}HAL_DMA_LevelCompleteTypeDef;
+
+/**
+ * @brief DMA handle Structure definition
+ */
+typedef struct __DMA_HandleTypeDef
+{
+ DMA_Channel_TypeDef *Instance; /*!< Register base address */
+
+ DMA_InitTypeDef Init; /*!< DMA communication parameters */
+
+ HAL_LockTypeDef Lock; /*!< DMA locking object */
+
+ HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
+
+ void *Parent; /*!< Parent object state */
+
+ void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
+
+ void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
+
+ void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
+
+ __IO uint32_t ErrorCode; /*!< DMA Error code */
+} DMA_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+ * @{
+ */
+
+/** @defgroup DMA_Error_Code DMA Error Code
+ * @{
+ */
+ #define HAL_DMA_ERROR_NONE ((uint32_t)0x00) /*!< No error */
+ #define HAL_DMA_ERROR_TE ((uint32_t)0x01) /*!< Transfer error */
+ #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x20) /*!< Timeout error */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+ * @{
+ */
+#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+ * @{
+ */
+#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
+#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+ * @{
+ */
+#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
+#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+ * @{
+ */
+#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */
+#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
+#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+ * @{
+ */
+#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */
+#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
+#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_mode DMA mode
+ * @{
+ */
+#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
+#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Priority_level DMA Priority level
+ * @{
+ */
+#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
+#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
+#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
+#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+ * @{
+ */
+#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
+#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
+#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
+/**
+ * @}
+ */
+
+/** @defgroup DMA_flag_definitions DMA flag definitions
+ * @{
+ */
+#define DMA_FLAG_GL1 ((uint32_t)0x00000001)
+#define DMA_FLAG_TC1 ((uint32_t)0x00000002)
+#define DMA_FLAG_HT1 ((uint32_t)0x00000004)
+#define DMA_FLAG_TE1 ((uint32_t)0x00000008)
+#define DMA_FLAG_GL2 ((uint32_t)0x00000010)
+#define DMA_FLAG_TC2 ((uint32_t)0x00000020)
+#define DMA_FLAG_HT2 ((uint32_t)0x00000040)
+#define DMA_FLAG_TE2 ((uint32_t)0x00000080)
+#define DMA_FLAG_GL3 ((uint32_t)0x00000100)
+#define DMA_FLAG_TC3 ((uint32_t)0x00000200)
+#define DMA_FLAG_HT3 ((uint32_t)0x00000400)
+#define DMA_FLAG_TE3 ((uint32_t)0x00000800)
+#define DMA_FLAG_GL4 ((uint32_t)0x00001000)
+#define DMA_FLAG_TC4 ((uint32_t)0x00002000)
+#define DMA_FLAG_HT4 ((uint32_t)0x00004000)
+#define DMA_FLAG_TE4 ((uint32_t)0x00008000)
+#define DMA_FLAG_GL5 ((uint32_t)0x00010000)
+#define DMA_FLAG_TC5 ((uint32_t)0x00020000)
+#define DMA_FLAG_HT5 ((uint32_t)0x00040000)
+#define DMA_FLAG_TE5 ((uint32_t)0x00080000)
+#define DMA_FLAG_GL6 ((uint32_t)0x00100000)
+#define DMA_FLAG_TC6 ((uint32_t)0x00200000)
+#define DMA_FLAG_HT6 ((uint32_t)0x00400000)
+#define DMA_FLAG_TE6 ((uint32_t)0x00800000)
+#define DMA_FLAG_GL7 ((uint32_t)0x01000000)
+#define DMA_FLAG_TC7 ((uint32_t)0x02000000)
+#define DMA_FLAG_HT7 ((uint32_t)0x04000000)
+#define DMA_FLAG_TE7 ((uint32_t)0x08000000)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA_Exported_Macros DMA Exported Macros
+ * @{
+ */
+
+/** @brief Reset DMA handle state
+ * @param __HANDLE__: DMA handle.
+ * @retval None
+ */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+ * @brief Enable the specified DMA Channel.
+ * @param __HANDLE__: DMA handle
+ * @retval None.
+ */
+#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
+
+/**
+ * @brief Disable the specified DMA Channel.
+ * @param __HANDLE__: DMA handle
+ * @retval None.
+ */
+#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
+
+
+/* Interrupt & Flag management */
+
+/**
+ * @brief Enables the specified DMA Channel interrupts.
+ * @param __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask
+ * @arg DMA_IT_TE: Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
+
+/**
+ * @brief Disables the specified DMA Channel interrupts.
+ * @param __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask
+ * @arg DMA_IT_TE: Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
+
+/**
+ * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
+ * @param __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask
+ * @arg DMA_IT_TE: Transfer error interrupt mask
+ * @retval The state of DMA_IT (SET or RESET).
+ */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
+ * @param __HANDLE__: DMA handle
+ *
+ * @retval The number of remaining data units in the current DMA Channel transfer.
+ */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
+
+/**
+ * @}
+ */
+
+/* Include DMA HAL Extension module */
+#include "stm32f1xx_hal_dma_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA_Exported_Functions DMA Exported Functions
+ * @{
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private Constants -------------------------------------------------------------*/
+/** @defgroup DMA_Private_Constants DMA Private Constants
+ * @brief DMA private defines and constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+ * @brief DMA private macros
+ * @{
+ */
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
+ ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+ ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
+ ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_MDATAALIGN_WORD ))
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
+ ((MODE) == DMA_CIRCULAR))
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
+ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+ ((PRIORITY) == DMA_PRIORITY_HIGH) || \
+ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+ * @brief DMA private functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,260 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_dma_ex.h
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief Header file of DMA HAL extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_DMA_EX_H
+#define __STM32F1xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DMAEx DMAEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
+ * @{
+ */
+/* Interrupt & Flag management */
+#if defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || \
+ defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
+/** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices
+ * @{
+ */
+
+/**
+ * @brief Returns the current DMA Channel transfer complete flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer complete flag index.
+ */
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
+ DMA_FLAG_TC5)
+
+/**
+ * @brief Returns the current DMA Channel half transfer complete flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified half transfer complete flag index.
+ */
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
+ DMA_FLAG_HT5)
+
+/**
+ * @brief Returns the current DMA Channel transfer error flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
+ DMA_FLAG_TE5)
+
+/**
+ * @brief Get the DMA Channel pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
+ * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
+ (DMA1->ISR & (__FLAG__)))
+
+/**
+ * @brief Clears the DMA Channel pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
+ * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
+ * @retval None
+ */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
+ (DMA1->IFCR = (__FLAG__)))
+
+/**
+ * @}
+ */
+
+#else
+/** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices
+ * @{
+ */
+
+/**
+ * @brief Returns the current DMA Channel transfer complete flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer complete flag index.
+ */
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
+ DMA_FLAG_TC7)
+
+/**
+ * @brief Returns the current DMA Channel half transfer complete flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified half transfer complete flag index.
+ */
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
+ DMA_FLAG_HT7)
+
+/**
+ * @brief Returns the current DMA Channel transfer error flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
+ DMA_FLAG_TE7)
+
+/**
+ * @brief Get the DMA Channel pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
+ * Where x can be 1_7 to select the DMA Channel flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
+
+/**
+ * @brief Clears the DMA Channel pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
+ * Where x can be 1_7 to select the DMA Channel flag.
+ * @retval None
+ */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || */
+ /* STM32F103xG || STM32F105xC || STM32F107xC */
+
+#endif /* __STM32F1xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,348 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_flash.h
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief Header file of Flash HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_FLASH_H
+#define __STM32F1xx_HAL_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/** @addtogroup FLASH_Private_Constants
+ * @{
+ */
+#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Macros
+ * @{
+ */
+
+#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
+ ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
+ ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
+
+#if defined(FLASH_ACR_LATENCY)
+#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
+ ((__LATENCY__) == FLASH_LATENCY_1) || \
+ ((__LATENCY__) == FLASH_LATENCY_2))
+
+#else
+#define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0)
+#endif /* FLASH_ACR_LATENCY */
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Types FLASH Exported Types
+ * @{
+ */
+
+
+/**
+ * @brief FLASH Procedure structure definition
+ */
+typedef enum
+{
+ FLASH_PROC_NONE = 0,
+ FLASH_PROC_PAGEERASE = 1,
+ FLASH_PROC_MASSERASE = 2,
+ FLASH_PROC_PROGRAMHALFWORD = 3,
+ FLASH_PROC_PROGRAMWORD = 4,
+ FLASH_PROC_PROGRAMDOUBLEWORD = 5
+} FLASH_ProcedureTypeDef;
+
+/**
+ * @brief FLASH handle Structure definition
+ */
+typedef struct
+{
+ __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
+
+ __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
+
+ __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */
+
+ __IO uint64_t Data; /*!< Internal variable to save data to be programmed */
+
+ HAL_LockTypeDef Lock; /*!< FLASH locking object */
+
+ __IO uint32_t ErrorCode; /*!< FLASH error code
+ This parameter can be a value of @ref FLASH_Error_Codes */
+} FLASH_ProcessTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+ * @{
+ */
+
+/** @defgroup FLASH_Error_Codes FLASH Error Codes
+ * @{
+ */
+
+#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00) /*!< No error */
+#define HAL_FLASH_ERROR_PROG ((uint32_t)0x01) /*!< Programming error */
+#define HAL_FLASH_ERROR_WRP ((uint32_t)0x02) /*!< Write protection error */
+#define HAL_FLASH_ERROR_OPTV ((uint32_t)0x04) /*!< Option validity error */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Type_Program FLASH Type Program
+ * @{
+ */
+#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01) /*!<Program a half-word (16-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02) /*!<Program a word (32-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03) /*!<Program a double word (64-bit) at a specified address*/
+
+/**
+ * @}
+ */
+
+#if defined(FLASH_ACR_LATENCY)
+/** @defgroup FLASH_Latency FLASH Latency
+ * @{
+ */
+#define FLASH_LATENCY_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
+#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
+#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
+
+/**
+ * @}
+ */
+
+#else
+/** @defgroup FLASH_Latency FLASH Latency
+ * @{
+ */
+#define FLASH_LATENCY_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
+
+/**
+ * @}
+ */
+
+#endif /* FLASH_ACR_LATENCY */
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
+ * @brief macros to control FLASH features
+ * @{
+ */
+
+/** @defgroup FLASH_Half_Cycle FLASH Half Cycle
+ * @brief macros to handle FLASH half cycle
+ * @{
+ */
+
+/**
+ * @brief Enable the FLASH half cycle access.
+ * @note half cycle access can only be used with a low-frequency clock of less than
+ 8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
+ * @retval None
+ */
+#define __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE() (FLASH->ACR |= FLASH_ACR_HLFCYA)
+
+/**
+ * @brief Disable the FLASH half cycle access.
+ * @note half cycle access can only be used with a low-frequency clock of less than
+ 8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
+ * @retval None
+ */
+#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))
+
+/**
+ * @}
+ */
+
+#if defined(FLASH_ACR_LATENCY)
+/** @defgroup FLASH_EM_Latency FLASH Latency
+ * @brief macros to handle FLASH Latency
+ * @{
+ */
+
+/**
+ * @brief Set the FLASH Latency.
+ * @param __LATENCY__ FLASH Latency
+ * The value of this parameter depend on device used within the same series
+ * @retval None
+ */
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
+
+
+/**
+ * @brief Get the FLASH Latency.
+ * @retval FLASH Latency
+ * The value of this parameter depend on device used within the same series
+ */
+#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
+
+/**
+ * @}
+ */
+
+#endif /* FLASH_ACR_LATENCY */
+/** @defgroup FLASH_Prefetch FLASH Prefetch
+ * @brief macros to handle FLASH Prefetch buffer
+ * @{
+ */
+/**
+ * @brief Enable the FLASH prefetch buffer.
+ * @retval None
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)
+
+/**
+ * @brief Disable the FLASH prefetch buffer.
+ * @retval None
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Include FLASH HAL Extended module */
+#include "stm32f1xx_hal_flash_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group1
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+
+/* FLASH IRQ handler function */
+void HAL_FLASH_IRQHandler(void);
+/* Callbacks in non blocking modes */
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+uint32_t HAL_FLASH_GetError(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private function -------------------------------------------------*/
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+void FLASH_PageErase(uint32_t PageAddress);
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+#if defined(FLASH_BANK2_END)
+HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout);
+#endif /* FLASH_BANK2_END */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_FLASH_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,804 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_flash_ex.h
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief Header file of Flash HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_FLASH_EX_H
+#define __STM32F1xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASHEx
+ * @{
+ */
+
+/** @addtogroup FLASHEx_Private_Constants
+ * @{
+ */
+
+#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFFF7E0)
+#define OBR_REG_INDEX ((uint32_t)1)
+#define SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP))
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASHEx_Private_Macros
+ * @{
+ */
+
+#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE))
+
+#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)))
+
+#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE))
+
+#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1))
+
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
+
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
+
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
+
+#if defined(FLASH_BANK2_END)
+#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
+#endif /* FLASH_BANK2_END */
+
+/* Low Density */
+#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFF) : \
+ ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFF))
+#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
+
+/* Medium Density */
+#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFF) : \
+ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF) : \
+ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFF) : \
+ ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFF))))
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
+
+/* High Density */
+#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFF) : \
+ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFF) : \
+ ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFF)))
+#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
+
+/* XL Density */
+#if defined(FLASH_BANK2_END)
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFF) : \
+ ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFF))
+#endif /* FLASH_BANK2_END */
+
+/* Connectivity Line */
+#if (defined(STM32F105xC) || defined(STM32F107xC))
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFF) : \
+ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFF) : \
+ ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF)))
+#endif /* STM32F105xC || STM32F107xC */
+
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
+
+#if defined(FLASH_BANK2_END)
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
+ ((BANK) == FLASH_BANK_2) || \
+ ((BANK) == FLASH_BANK_BOTH))
+#else
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
+#endif /* FLASH_BANK2_END */
+
+/* Low Density */
+#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? \
+ ((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFF)))
+
+#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
+
+/* Medium Density */
+#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? \
+ ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40) ? \
+ ((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? \
+ ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFF)))))
+
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
+
+/* High Density */
+#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200) ? \
+ ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180) ? \
+ ((ADDRESS) <= 0x0805FFFF) : ((ADDRESS) <= 0x0803FFFF))))
+
+#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
+
+/* XL Density */
+#if defined(FLASH_BANK2_END)
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400) ? \
+ ((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFF)))
+
+#endif /* FLASH_BANK2_END */
+
+/* Connectivity Line */
+#if (defined(STM32F105xC) || defined(STM32F107xC))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100) ? \
+ ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? \
+ ((ADDRESS) <= 0x0801FFFF) : ((ADDRESS) <= 0x0800FFFF))))
+
+#endif /* STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief FLASH Erase structure definition
+ */
+typedef struct
+{
+ uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
+ This parameter can be a value of @ref FLASHEx_Type_Erase */
+
+ uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
+ This parameter must be a value of @ref FLASHEx_Banks */
+
+ uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
+ This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END
+ (x = 1 or 2 depending on devices)*/
+
+ uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
+ This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/
+
+} FLASH_EraseInitTypeDef;
+
+/**
+ * @brief FLASH Options bytes program structure definition
+ */
+typedef struct
+{
+ uint32_t OptionType; /*!< OptionType: Option byte to be configured.
+ This parameter can be a value of @ref FLASHEx_OB_Type */
+
+ uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
+ This parameter can be a value of @ref FLASHEx_OB_WRP_State */
+
+ uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected
+ This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
+
+ uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors.
+ This parameter must be a value of @ref FLASHEx_Banks */
+
+ uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
+ This parameter can be a value of @ref FLASHEx_OB_Read_Protection */
+
+#if defined(FLASH_BANK2_END)
+ uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
+ IWDG / STOP / STDBY / BOOT1
+ This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
+ @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1 */
+#else
+ uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
+ IWDG / STOP / STDBY
+ This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
+ @ref FLASHEx_OB_nRST_STDBY */
+#endif /* FLASH_BANK2_END */
+
+ uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
+ This parameter can be a value of @ref FLASHEx_OB_Data_Address */
+
+ uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+} FLASH_OBProgramInitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
+ * @{
+ */
+
+/** @defgroup FLASHEx_Constants FLASH Constants
+ * @{
+ */
+
+/** @defgroup FLASHEx_Page_Size Page Size
+ * @{
+ */
+#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
+#define FLASH_PAGE_SIZE ((uint32_t)0x400)
+#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
+ /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+
+#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC))
+#define FLASH_PAGE_SIZE ((uint32_t)0x800)
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+ /* STM32F101xG || STM32F103xG */
+ /* STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Type_Erase Type Erase
+ * @{
+ */
+#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!<Pages erase only*/
+#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x02) /*!<Flash mass erase activation*/
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Banks Banks
+ * @{
+ */
+#if defined(FLASH_BANK2_END)
+#define FLASH_BANK_1 ((uint32_t)1) /*!< Bank 1 */
+#define FLASH_BANK_2 ((uint32_t)2) /*!< Bank 2 */
+#define FLASH_BANK_BOTH ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
+
+#else
+#define FLASH_BANK_1 ((uint32_t)1) /*!< Bank 1 */
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants
+ * @{
+ */
+
+/** @defgroup FLASHEx_OB_Type Option Bytes Type
+ * @{
+ */
+#define OPTIONBYTE_WRP ((uint32_t)0x01) /*!<WRP option byte configuration*/
+#define OPTIONBYTE_RDP ((uint32_t)0x02) /*!<RDP option byte configuration*/
+#define OPTIONBYTE_USER ((uint32_t)0x04) /*!<USER option byte configuration*/
+#define OPTIONBYTE_DATA ((uint32_t)0x08) /*!<DATA option byte configuration*/
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State
+ * @{
+ */
+#define OB_WRPSTATE_DISABLE ((uint32_t)0x00) /*!<Disable the write protection of the desired pages*/
+#define OB_WRPSTATE_ENABLE ((uint32_t)0x01) /*!<Enable the write protection of the desired pagess*/
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_Write_Protection Option Bytes Write Protection
+ * @{
+ */
+/* STM32 Low and Medium density devices */
+#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) \
+ || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) \
+ || defined(STM32F103xB)
+#define OB_WRP_PAGES0TO3 ((uint32_t)0x00000001) /*!< Write protection of page 0 to 3 */
+#define OB_WRP_PAGES4TO7 ((uint32_t)0x00000002) /*!< Write protection of page 4 to 7 */
+#define OB_WRP_PAGES8TO11 ((uint32_t)0x00000004) /*!< Write protection of page 8 to 11 */
+#define OB_WRP_PAGES12TO15 ((uint32_t)0x00000008) /*!< Write protection of page 12 to 15 */
+#define OB_WRP_PAGES16TO19 ((uint32_t)0x00000010) /*!< Write protection of page 16 to 19 */
+#define OB_WRP_PAGES20TO23 ((uint32_t)0x00000020) /*!< Write protection of page 20 to 23 */
+#define OB_WRP_PAGES24TO27 ((uint32_t)0x00000040) /*!< Write protection of page 24 to 27 */
+#define OB_WRP_PAGES28TO31 ((uint32_t)0x00000080) /*!< Write protection of page 28 to 31 */
+#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
+ /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+
+/* STM32 Medium-density devices */
+#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
+#define OB_WRP_PAGES32TO35 ((uint32_t)0x00000100) /*!< Write protection of page 32 to 35 */
+#define OB_WRP_PAGES36TO39 ((uint32_t)0x00000200) /*!< Write protection of page 36 to 39 */
+#define OB_WRP_PAGES40TO43 ((uint32_t)0x00000400) /*!< Write protection of page 40 to 43 */
+#define OB_WRP_PAGES44TO47 ((uint32_t)0x00000800) /*!< Write protection of page 44 to 47 */
+#define OB_WRP_PAGES48TO51 ((uint32_t)0x00001000) /*!< Write protection of page 48 to 51 */
+#define OB_WRP_PAGES52TO55 ((uint32_t)0x00002000) /*!< Write protection of page 52 to 55 */
+#define OB_WRP_PAGES56TO59 ((uint32_t)0x00004000) /*!< Write protection of page 56 to 59 */
+#define OB_WRP_PAGES60TO63 ((uint32_t)0x00008000) /*!< Write protection of page 60 to 63 */
+#define OB_WRP_PAGES64TO67 ((uint32_t)0x00010000) /*!< Write protection of page 64 to 67 */
+#define OB_WRP_PAGES68TO71 ((uint32_t)0x00020000) /*!< Write protection of page 68 to 71 */
+#define OB_WRP_PAGES72TO75 ((uint32_t)0x00040000) /*!< Write protection of page 72 to 75 */
+#define OB_WRP_PAGES76TO79 ((uint32_t)0x00080000) /*!< Write protection of page 76 to 79 */
+#define OB_WRP_PAGES80TO83 ((uint32_t)0x00100000) /*!< Write protection of page 80 to 83 */
+#define OB_WRP_PAGES84TO87 ((uint32_t)0x00200000) /*!< Write protection of page 84 to 87 */
+#define OB_WRP_PAGES88TO91 ((uint32_t)0x00400000) /*!< Write protection of page 88 to 91 */
+#define OB_WRP_PAGES92TO95 ((uint32_t)0x00800000) /*!< Write protection of page 92 to 95 */
+#define OB_WRP_PAGES96TO99 ((uint32_t)0x01000000) /*!< Write protection of page 96 to 99 */
+#define OB_WRP_PAGES100TO103 ((uint32_t)0x02000000) /*!< Write protection of page 100 to 103 */
+#define OB_WRP_PAGES104TO107 ((uint32_t)0x04000000) /*!< Write protection of page 104 to 107 */
+#define OB_WRP_PAGES108TO111 ((uint32_t)0x08000000) /*!< Write protection of page 108 to 111 */
+#define OB_WRP_PAGES112TO115 ((uint32_t)0x10000000) /*!< Write protection of page 112 to 115 */
+#define OB_WRP_PAGES116TO119 ((uint32_t)0x20000000) /*!< Write protection of page 115 to 119 */
+#define OB_WRP_PAGES120TO123 ((uint32_t)0x40000000) /*!< Write protection of page 120 to 123 */
+#define OB_WRP_PAGES124TO127 ((uint32_t)0x80000000) /*!< Write protection of page 124 to 127 */
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+
+
+/* STM32 High-density, XL-density and Connectivity line devices */
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) \
+ || defined(STM32F101xG) || defined(STM32F103xG) \
+ || defined(STM32F105xC) || defined(STM32F107xC)
+#define OB_WRP_PAGES0TO1 ((uint32_t)0x00000001) /*!< Write protection of page 0 TO 1 */
+#define OB_WRP_PAGES2TO3 ((uint32_t)0x00000002) /*!< Write protection of page 2 TO 3 */
+#define OB_WRP_PAGES4TO5 ((uint32_t)0x00000004) /*!< Write protection of page 4 TO 5 */
+#define OB_WRP_PAGES6TO7 ((uint32_t)0x00000008) /*!< Write protection of page 6 TO 7 */
+#define OB_WRP_PAGES8TO9 ((uint32_t)0x00000010) /*!< Write protection of page 8 TO 9 */
+#define OB_WRP_PAGES10TO11 ((uint32_t)0x00000020) /*!< Write protection of page 10 TO 11 */
+#define OB_WRP_PAGES12TO13 ((uint32_t)0x00000040) /*!< Write protection of page 12 TO 13 */
+#define OB_WRP_PAGES14TO15 ((uint32_t)0x00000080) /*!< Write protection of page 14 TO 15 */
+#define OB_WRP_PAGES16TO17 ((uint32_t)0x00000100) /*!< Write protection of page 16 TO 17 */
+#define OB_WRP_PAGES18TO19 ((uint32_t)0x00000200) /*!< Write protection of page 18 TO 19 */
+#define OB_WRP_PAGES20TO21 ((uint32_t)0x00000400) /*!< Write protection of page 20 TO 21 */
+#define OB_WRP_PAGES22TO23 ((uint32_t)0x00000800) /*!< Write protection of page 22 TO 23 */
+#define OB_WRP_PAGES24TO25 ((uint32_t)0x00001000) /*!< Write protection of page 24 TO 25 */
+#define OB_WRP_PAGES26TO27 ((uint32_t)0x00002000) /*!< Write protection of page 26 TO 27 */
+#define OB_WRP_PAGES28TO29 ((uint32_t)0x00004000) /*!< Write protection of page 28 TO 29 */
+#define OB_WRP_PAGES30TO31 ((uint32_t)0x00008000) /*!< Write protection of page 30 TO 31 */
+#define OB_WRP_PAGES32TO33 ((uint32_t)0x00010000) /*!< Write protection of page 32 TO 33 */
+#define OB_WRP_PAGES34TO35 ((uint32_t)0x00020000) /*!< Write protection of page 34 TO 35 */
+#define OB_WRP_PAGES36TO37 ((uint32_t)0x00040000) /*!< Write protection of page 36 TO 37 */
+#define OB_WRP_PAGES38TO39 ((uint32_t)0x00080000) /*!< Write protection of page 38 TO 39 */
+#define OB_WRP_PAGES40TO41 ((uint32_t)0x00100000) /*!< Write protection of page 40 TO 41 */
+#define OB_WRP_PAGES42TO43 ((uint32_t)0x00200000) /*!< Write protection of page 42 TO 43 */
+#define OB_WRP_PAGES44TO45 ((uint32_t)0x00400000) /*!< Write protection of page 44 TO 45 */
+#define OB_WRP_PAGES46TO47 ((uint32_t)0x00800000) /*!< Write protection of page 46 TO 47 */
+#define OB_WRP_PAGES48TO49 ((uint32_t)0x01000000) /*!< Write protection of page 48 TO 49 */
+#define OB_WRP_PAGES50TO51 ((uint32_t)0x02000000) /*!< Write protection of page 50 TO 51 */
+#define OB_WRP_PAGES52TO53 ((uint32_t)0x04000000) /*!< Write protection of page 52 TO 53 */
+#define OB_WRP_PAGES54TO55 ((uint32_t)0x08000000) /*!< Write protection of page 54 TO 55 */
+#define OB_WRP_PAGES56TO57 ((uint32_t)0x10000000) /*!< Write protection of page 56 TO 57 */
+#define OB_WRP_PAGES58TO59 ((uint32_t)0x20000000) /*!< Write protection of page 58 TO 59 */
+#define OB_WRP_PAGES60TO61 ((uint32_t)0x40000000) /*!< Write protection of page 60 TO 61 */
+#define OB_WRP_PAGES62TO127 ((uint32_t)0x80000000) /*!< Write protection of page 62 TO 127 */
+#define OB_WRP_PAGES62TO255 ((uint32_t)0x80000000) /*!< Write protection of page 62 TO 255 */
+#define OB_WRP_PAGES62TO511 ((uint32_t)0x80000000) /*!< Write protection of page 62 TO 511 */
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+ /* STM32F101xG || STM32F103xG */
+ /* STM32F105xC || STM32F107xC */
+
+#define OB_WRP_ALLPAGES ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
+
+/* Low Density */
+#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)
+#define OB_WRP_PAGES0TO31MASK ((uint32_t)0x000000FF)
+#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
+
+/* Medium Density */
+#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
+#define OB_WRP_PAGES0TO31MASK ((uint32_t)0x000000FF)
+#define OB_WRP_PAGES32TO63MASK ((uint32_t)0x0000FF00)
+#define OB_WRP_PAGES64TO95MASK ((uint32_t)0x00FF0000)
+#define OB_WRP_PAGES96TO127MASK ((uint32_t)0xFF000000)
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
+
+/* High Density */
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)
+#define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FF)
+#define OB_WRP_PAGES16TO31MASK ((uint32_t)0x0000FF00)
+#define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000)
+#define OB_WRP_PAGES48TO255MASK ((uint32_t)0xFF000000)
+#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
+
+/* XL Density */
+#if defined(STM32F101xG) || defined(STM32F103xG)
+#define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FF)
+#define OB_WRP_PAGES16TO31MASK ((uint32_t)0x0000FF00)
+#define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000)
+#define OB_WRP_PAGES48TO511MASK ((uint32_t)0xFF000000)
+#endif /* STM32F101xG || STM32F103xG */
+
+/* Connectivity line devices */
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FF)
+#define OB_WRP_PAGES16TO31MASK ((uint32_t)0x0000FF00)
+#define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000)
+#define OB_WRP_PAGES48TO127MASK ((uint32_t)0xFF000000)
+#endif /* STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_Read_Protection Option Byte Read Protection
+ * @{
+ */
+#define OB_RDP_LEVEL_0 ((uint8_t)0xA5)
+#define OB_RDP_LEVEL_1 ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog
+ * @{
+ */
+#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */
+#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP
+ * @{
+ */
+#define OB_STOP_NO_RST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY
+ * @{
+ */
+#define OB_STDBY_NO_RST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
+/**
+ * @}
+ */
+
+#if defined(FLASH_BANK2_END)
+/** @defgroup FLASHEx_OB_BOOT1 Option Byte BOOT1
+ * @{
+ */
+#define OB_BOOT1_RESET ((uint16_t)0x0000) /*!< BOOT1 Reset */
+#define OB_BOOT1_SET ((uint16_t)0x0008) /*!< BOOT1 Set */
+/**
+ * @}
+ */
+#endif /* FLASH_BANK2_END */
+
+/** @defgroup FLASHEx_OB_Data_Address Option Byte Data Address
+ * @{
+ */
+#define OB_DATA_ADDRESS_DATA0 ((uint32_t)0x1FFFF804)
+#define OB_DATA_ADDRESS_DATA1 ((uint32_t)0x1FFFF806)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASHEx_Constants
+ * @{
+ */
+
+/** @defgroup FLASH_Flag_definition Flag definition
+ * @brief Flag definition
+ * @{
+ */
+#if defined(FLASH_BANK2_END)
+ #define FLASH_FLAG_BSY FLASH_FLAG_BSY_BANK1 /*!< FLASH Bank1 Busy flag */
+ #define FLASH_FLAG_PGERR FLASH_FLAG_PGERR_BANK1 /*!< FLASH Bank1 Programming error flag */
+ #define FLASH_FLAG_WRPERR FLASH_FLAG_WRPERR_BANK1 /*!< FLASH Bank1 Write protected error flag */
+ #define FLASH_FLAG_EOP FLASH_FLAG_EOP_BANK1 /*!< FLASH Bank1 End of Operation flag */
+
+ #define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank1 Busy flag */
+ #define FLASH_FLAG_PGERR_BANK1 FLASH_SR_PGERR /*!< FLASH Bank1 Programming error flag */
+ #define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPRTERR /*!< FLASH Bank1 Write protected error flag */
+ #define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP /*!< FLASH Bank1 End of Operation flag */
+
+ #define FLASH_FLAG_BSY_BANK2 (FLASH_SR2_BSY << 16) /*!< FLASH Bank2 Busy flag */
+ #define FLASH_FLAG_PGERR_BANK2 (FLASH_SR2_PGERR << 16) /*!< FLASH Bank2 Programming error flag */
+ #define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR2_WRPRTERR << 16) /*!< FLASH Bank2 Write protected error flag */
+ #define FLASH_FLAG_EOP_BANK2 (FLASH_SR2_EOP << 16) /*!< FLASH Bank2 End of Operation flag */
+
+#else
+
+ #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
+ #define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
+ #define FLASH_FLAG_WRPERR FLASH_SR_WRPRTERR /*!< FLASH Write protected error flag */
+ #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */
+
+#endif
+ #define FLASH_FLAG_OPTVERR ((OBR_REG_INDEX << 8 | FLASH_OBR_OPTERR)) /*!< Option Byte Error */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Interrupt_definition Interrupt definition
+ * @brief FLASH Interrupt definition
+ * @{
+ */
+#if defined(FLASH_BANK2_END)
+ #define FLASH_IT_EOP FLASH_IT_EOP_BANK1 /*!< End of FLASH Operation Interrupt source Bank1 */
+ #define FLASH_IT_ERR FLASH_IT_ERR_BANK1 /*!< Error Interrupt source Bank1 */
+
+ #define FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source Bank1 */
+ #define FLASH_IT_ERR_BANK1 FLASH_CR_ERRIE /*!< Error Interrupt source Bank1 */
+
+ #define FLASH_IT_EOP_BANK2 (FLASH_CR2_EOPIE << 16) /*!< End of FLASH Operation Interrupt source Bank2 */
+ #define FLASH_IT_ERR_BANK2 (FLASH_CR2_ERRIE << 16) /*!< Error Interrupt source Bank2 */
+
+#else
+
+ #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
+ #define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error Interrupt source */
+
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
+ * @{
+ */
+
+/** @defgroup FLASH_Interrupt Interrupt
+ * @brief macros to handle FLASH interrupts
+ * @{
+ */
+
+#if defined(FLASH_BANK2_END)
+/**
+ * @brief Enable the specified FLASH interrupt.
+ * @param __INTERRUPT__ FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1
+ * @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1
+ * @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2
+ * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
+ * @retval none
+ */
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { \
+ /* Enable Bank1 IT */ \
+ SET_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFF)); \
+ /* Enable Bank2 IT */ \
+ SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16)); \
+ } while(0)
+
+/**
+ * @brief Disable the specified FLASH interrupt.
+ * @param __INTERRUPT__ FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1
+ * @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1
+ * @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2
+ * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
+ * @retval none
+ */
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { \
+ /* Disable Bank1 IT */ \
+ CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFF)); \
+ /* Disable Bank2 IT */ \
+ CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16)); \
+ } while(0)
+
+/**
+ * @brief Get the specified FLASH flag status.
+ * @param __FLAG__ specifies the FLASH flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1
+ * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1
+ * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1
+ * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1
+ * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2
+ * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2
+ * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2
+ * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2
+ * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
+ * @retval The new state of __FLAG__ (SET or RESET).
+ */
+#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \
+ (FLASH->OBR & FLASH_OBR_OPTERR) : \
+ ((((__FLAG__) & SR_FLAG_MASK) != RESET)? \
+ (FLASH->SR & ((__FLAG__) & SR_FLAG_MASK)) : \
+ (FLASH->SR2 & ((__FLAG__) >> 16))))
+
+/**
+ * @brief Clear the specified FLASH flag.
+ * @param __FLAG__ specifies the FLASH flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1
+ * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1
+ * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1
+ * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1
+ * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2
+ * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2
+ * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2
+ * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2
+ * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
+ * @retval none
+ */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \
+ /* Clear FLASH_FLAG_OPTVERR flag */ \
+ if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
+ { \
+ CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
+ } \
+ else { \
+ /* Clear Flag in Bank1 */ \
+ if (((__FLAG__) & SR_FLAG_MASK) != RESET) \
+ { \
+ FLASH->SR = ((__FLAG__) & SR_FLAG_MASK); \
+ } \
+ /* Clear Flag in Bank2 */ \
+ if (((__FLAG__) >> 16) != RESET) \
+ { \
+ FLASH->SR2 = ((__FLAG__) >> 16); \
+ } \
+ } \
+ } while(0)
+#else
+/**
+ * @brief Enable the specified FLASH interrupt.
+ * @param __INTERRUPT__ FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
+ * @arg @ref FLASH_IT_ERR Error Interrupt
+ * @retval none
+ */
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified FLASH interrupt.
+ * @param __INTERRUPT__ FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
+ * @arg @ref FLASH_IT_ERR Error Interrupt
+ * @retval none
+ */
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Get the specified FLASH flag status.
+ * @param __FLAG__ specifies the FLASH flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
+ * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
+ * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
+ * @arg @ref FLASH_FLAG_BSY FLASH Busy flag
+ * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
+ * @retval The new state of __FLAG__ (SET or RESET).
+ */
+#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \
+ (FLASH->OBR & FLASH_OBR_OPTERR) : \
+ (FLASH->SR & (__FLAG__)))
+/**
+ * @brief Clear the specified FLASH flag.
+ * @param __FLAG__ specifies the FLASH flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
+ * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
+ * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
+ * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
+ * @retval none
+ */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \
+ /* Clear FLASH_FLAG_OPTVERR flag */ \
+ if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
+ { \
+ CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
+ } \
+ else { \
+ /* Clear Flag in Bank1 */ \
+ FLASH->SR = (__FLAG__); \
+ } \
+ } while(0)
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASHEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FLASHEx_Exported_Functions_Group1
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASHEx_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_FLASHEx_OBErase(void);
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_FLASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,324 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_gpio.h
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief Header file of GPIO HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_GPIO_H
+#define __STM32F1xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+ * @{
+ */
+
+/**
+ * @brief GPIO Init structure definition
+ */
+typedef struct
+{
+ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_pins_define */
+
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIO_mode_define */
+
+ uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+ This parameter can be a value of @ref GPIO_pull_define */
+
+ uint32_t Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIO_speed_define */
+}GPIO_InitTypeDef;
+
+/**
+ * @brief GPIO Bit SET and Bit RESET enumeration
+ */
+typedef enum
+{
+ GPIO_PIN_RESET = 0,
+ GPIO_PIN_SET
+}GPIO_PinState;
+
+/**
+ * @}
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIO_pins_define GPIO pins define
+ * @{
+ */
+#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
+#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
+#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
+#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
+#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
+#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
+#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
+#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
+#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
+#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
+#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
+#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
+#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
+#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
+#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
+#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
+#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
+
+#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
+/**
+ * @}
+ */
+
+
+/** @defgroup GPIO_mode_define GPIO mode define
+ * @brief GPIO Configuration Mode
+ * Elements values convention: 0xX0yz00YZ
+ * - X : GPIO mode or EXTI Mode
+ * - y : External IT or Event trigger detection
+ * - z : IO configuration on External IT or Event
+ * - Y : Output type (Push Pull or Open Drain)
+ * - Z : IO Direction mode (Input, Output, Alternate or Analog)
+ * @{
+ */
+#define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */
+#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */
+#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */
+#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */
+#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */
+#define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT /*!< Alternate Function Input Mode */
+
+#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */
+
+#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+
+#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */
+#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */
+#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup GPIO_speed_define GPIO speed define
+ * @brief GPIO Output Maximum frequency
+ * @{
+ */
+#define GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1) /*!< Low speed */
+#define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */
+#define GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0) /*!< High speed */
+
+/**
+ * @}
+ */
+
+
+ /** @defgroup GPIO_pull_define GPIO pull define
+ * @brief GPIO Pull-Up or Pull-Down Activation
+ * @{
+ */
+#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */
+#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */
+#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup GPIO_Private_Macros
+ * @{
+ */
+
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+
+#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
+
+#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
+ ((PULL) == GPIO_PULLDOWN))
+
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \
+ ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))
+
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
+ ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
+ ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
+ ((MODE) == GPIO_MODE_AF_PP) ||\
+ ((MODE) == GPIO_MODE_AF_OD) ||\
+ ((MODE) == GPIO_MODE_IT_RISING) ||\
+ ((MODE) == GPIO_MODE_IT_FALLING) ||\
+ ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
+ ((MODE) == GPIO_MODE_EVT_RISING) ||\
+ ((MODE) == GPIO_MODE_EVT_FALLING) ||\
+ ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
+ ((MODE) == GPIO_MODE_ANALOG))
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Checks whether the specified EXTI line flag is set or not.
+ * @param __EXTI_LINE__: specifies the EXTI line flag to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+ * @brief Clears the EXTI's line pending flags.
+ * @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+ * @brief Checks whether the specified EXTI line is asserted or not.
+ * @param __EXTI_LINE__: specifies the EXTI line to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+ * @brief Clears the EXTI's line pending bits.
+ * @param __EXTI_LINE__: specifies the EXTI lines to clear.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+ * @brief Generates a Software interrupt on selected EXTI line.
+ * @param __EXTI_LINE__: specifies the EXTI line to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
+
+/* Include GPIO HAL Extension module */
+#include "stm32f1xx_hal_gpio_ex.h"
+
+/**
+ * @}
+ */
+
+
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization and de-initialization functions *******************************/
+/** @addtogroup GPIO_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup GPIO_Exported_Functions_Group1
+ * @{
+ */
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+/**
+ * @}
+ */
+
+/* IO operation functions *******************************************************/
+/** @addtogroup GPIO_Exported_Functions_Group2
+ * @{
+ */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,887 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_gpio_ex.h
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief Header file of GPIO HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_GPIO_EX_H
+#define __STM32F1xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup GPIOEx GPIOEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration
+ * @brief This section propose definition to use the Cortex EVENTOUT signal.
+ * @{
+ */
+
+/** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin
+ * @{
+ */
+
+#define AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */
+#define AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */
+#define AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */
+#define AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */
+#define AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */
+#define AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */
+#define AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */
+#define AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */
+#define AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */
+#define AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */
+#define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */
+#define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */
+#define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */
+#define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */
+#define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
+#define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
+
+#define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_1) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_2) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_3) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_4) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_5) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_6) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_7) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_8) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_9) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_10) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_11) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_12) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_13) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_14) || \
+ ((__PIN__) == AFIO_EVENTOUT_PIN_15))
+/**
+ * @}
+ */
+
+/** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port
+ * @{
+ */
+
+#define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */
+#define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */
+#define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */
+#define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
+#define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
+
+#define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \
+ ((__PORT__) == AFIO_EVENTOUT_PORT_B) || \
+ ((__PORT__) == AFIO_EVENTOUT_PORT_C) || \
+ ((__PORT__) == AFIO_EVENTOUT_PORT_D) || \
+ ((__PORT__) == AFIO_EVENTOUT_PORT_E))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping
+ * @brief This section propose definition to remap the alternate function to some other port/pins.
+ * @{
+ */
+
+/**
+ * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
+ * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SPI1_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP)
+
+/**
+ * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
+ * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SPI1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP)
+
+/**
+ * @brief Enable the remapping of I2C1 alternate function SCL and SDA.
+ * @note ENABLE: Remap (SCL/PB8, SDA/PB9)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_I2C1_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP)
+
+/**
+ * @brief Disable the remapping of I2C1 alternate function SCL and SDA.
+ * @note DISABLE: No remap (SCL/PB6, SDA/PB7)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_I2C1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP)
+
+/**
+ * @brief Enable the remapping of USART1 alternate function TX and RX.
+ * @note ENABLE: Remap (TX/PB6, RX/PB7)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART1_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP)
+
+/**
+ * @brief Disable the remapping of USART1 alternate function TX and RX.
+ * @note DISABLE: No remap (TX/PA9, RX/PA10)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP)
+
+/**
+ * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
+ * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART2_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP)
+
+/**
+ * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
+ * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART2_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP)
+
+/**
+ * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
+ * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART3_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
+ * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART3_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_PARTIALREMAP)
+
+/**
+ * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
+ * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART3_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_NOREMAP)
+
+/**
+ * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
+ * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM1_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
+ * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM1_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP)
+
+/**
+ * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
+ * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM1_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_NOREMAP)
+
+/**
+ * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+ * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM2_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+ * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2)
+
+/**
+ * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+ * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1)
+
+/**
+ * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+ * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM2_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_NOREMAP)
+
+/**
+ * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
+ * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
+ * @note TIM3_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM3_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
+ * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
+ * @note TIM3_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM3_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP)
+
+/**
+ * @brief Disable the remapping of TIM3 alternate function channels 1 to 4
+ * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
+ * @note TIM3_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM3_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_NOREMAP)
+
+/**
+ * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
+ * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
+ * @note TIM4_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM4_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
+ * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
+ * @note TIM4_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM4_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP)
+
+#if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
+
+/**
+ * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
+ * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CAN1_1() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP1)
+
+/**
+ * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
+ * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CAN1_2() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP2)
+
+/**
+ * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
+ * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CAN1_3() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP3)
+#endif
+
+/**
+ * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
+ * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
+ * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
+ * on 100-pin and 144-pin packages, no need for remapping).
+ * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_PD01_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP)
+
+/**
+ * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
+ * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
+ * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
+ * on 100-pin and 144-pin packages, no need for remapping).
+ * @note DISABLE: No remapping of PD0 and PD1
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_PD01_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP)
+
+#if defined(AFIO_MAPR_TIM5CH4_IREMAP)
+/**
+ * @brief Enable the remapping of TIM5CH4.
+ * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
+ * @note This function is available only in high density value line devices.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM5CH4_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP)
+
+/**
+ * @brief Disable the remapping of TIM5CH4.
+ * @note DISABLE: TIM5_CH4 is connected to PA3
+ * @note This function is available only in high density value line devices.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP)
+#endif
+
+#if defined(AFIO_MAPR_ETH_REMAP)
+/**
+ * @brief Enable the remapping of Ethernet MAC connections with the PHY.
+ * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ETH_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP)
+
+/**
+ * @brief Disable the remapping of Ethernet MAC connections with the PHY.
+ * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1)
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ETH_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP)
+#endif
+
+#if defined(AFIO_MAPR_CAN2_REMAP)
+
+/**
+ * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
+ * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6)
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CAN2_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP)
+
+/**
+ * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
+ * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CAN2_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP)
+#endif
+
+#if defined(AFIO_MAPR_MII_RMII_SEL)
+/**
+ * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
+ * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_ETH_RMII() SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL)
+
+/**
+ * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
+ * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_ETH_MII() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL)
+#endif
+
+/**
+ * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
+ * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP)
+
+/**
+ * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
+ * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP)
+
+/**
+ * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
+ * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP)
+
+/**
+ * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
+ * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP)
+
+#if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
+
+/**
+ * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
+ * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP)
+
+/**
+ * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
+ * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP)
+#endif
+
+#if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)
+
+/**
+ * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+ * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP)
+
+/**
+ * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+ * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP)
+#endif
+
+/**
+ * @brief Enable the Serial wire JTAG configuration
+ * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SWJ_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_RESET)
+
+/**
+ * @brief Enable the Serial wire JTAG configuration
+ * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SWJ_NONJTRST() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_NOJNTRST)
+
+/**
+ * @brief Enable the Serial wire JTAG configuration
+ * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SWJ_NOJTAG() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_JTAGDISABLE)
+
+/**
+ * @brief Disable the Serial wire JTAG configuration
+ * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SWJ_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_DISABLE)
+
+#if defined(AFIO_MAPR_SPI3_REMAP)
+
+/**
+ * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
+ * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SPI3_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP)
+
+/**
+ * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
+ * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5).
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SPI3_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP)
+#endif
+
+#if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
+
+/**
+ * @brief Control of TIM2_ITR1 internal mapping.
+ * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_TIM2ITR1_TO_USB() SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP)
+
+/**
+ * @brief Control of TIM2_ITR1 internal mapping.
+ * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_TIM2ITR1_TO_ETH() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP)
+#endif
+
+#if defined(AFIO_MAPR_PTP_PPS_REMAP)
+
+/**
+ * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+ * @note ENABLE: PTP_PPS is output on PB5 pin.
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_ETH_PTP_PPS_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP)
+
+/**
+ * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+ * @note DISABLE: PTP_PPS not output on PB5 pin.
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_ETH_PTP_PPS_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM9_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
+ * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM9_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
+ * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM10_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM10_CH1.
+ * @note ENABLE: Remap (TIM10_CH1 on PF6).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM10_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM10_CH1.
+ * @note DISABLE: No remap (TIM10_CH1 on PB8).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM11_REMAP)
+/**
+ * @brief Enable the remapping of TIM11_CH1.
+ * @note ENABLE: Remap (TIM11_CH1 on PF7).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM11_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM11_CH1.
+ * @note DISABLE: No remap (TIM11_CH1 on PB9).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM13_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM13_CH1.
+ * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM13_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM13_CH1.
+ * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM14_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM14_CH1.
+ * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM14_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM14_CH1.
+ * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
+
+/**
+ * @brief Controls the use of the optional FSMC_NADV signal.
+ * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
+ * @retval None
+ */
+#define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
+
+/**
+ * @brief Controls the use of the optional FSMC_NADV signal.
+ * @note CONNECTED: The NADV signal is connected to the output (default).
+ * @retval None
+ */
+#define __HAL_AFIO_FSMCNADV_CONNECTED() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM15_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
+ * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM15_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
+ * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM16_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM16_CH1.
+ * @note ENABLE: Remap (TIM16_CH1 on PA6).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM16_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM16_CH1.
+ * @note DISABLE: No remap (TIM16_CH1 on PB8).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM17_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM17_CH1.
+ * @note ENABLE: Remap (TIM17_CH1 on PA7).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM17_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM17_CH1.
+ * @note DISABLE: No remap (TIM17_CH1 on PB9).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_CEC_REMAP)
+
+/**
+ * @brief Enable the remapping of CEC.
+ * @note ENABLE: Remap (CEC on PB10).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CEC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
+
+/**
+ * @brief Disable the remapping of CEC.
+ * @note DISABLE: No remap (CEC on PB8).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
+
+/**
+ * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
+ * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM1DMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
+
+/**
+ * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
+ * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
+
+/**
+ * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
+ * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
+
+/**
+ * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
+ * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM12_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
+ * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
+ * @note This bit is available only in high density value line devices.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM12_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
+ * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5).
+ * @note This bit is available only in high density value line devices.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_MISC_REMAP)
+
+/**
+ * @brief Miscellaneous features remapping.
+ * This bit is set and cleared by software. It controls miscellaneous features.
+ * The DMA2 channel 5 interrupt position in the vector table.
+ * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
+ * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
+ * selected as DAC Trigger 3, TIM15 triggers TIM1/3.
+ * @note This bit is available only in high density value line devices.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_MISC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
+
+/**
+ * @brief Miscellaneous features remapping.
+ * This bit is set and cleared by software. It controls miscellaneous features.
+ * The DMA2 channel 5 interrupt position in the vector table.
+ * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
+ * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
+ * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
+ * @note This bit is available only in high density value line devices.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros
+ * @{
+ */
+#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :3U)
+#elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC)
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :4U)
+#elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :\
+ ((__GPIOx__) == (GPIOE))? 4U :\
+ ((__GPIOx__) == (GPIOF))? 5U :6U)
+#endif
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup GPIOEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup GPIOEx_Exported_Functions_Group1
+ * @{
+ */
+void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource);
+void HAL_GPIOEx_EnableEventout(void);
+void HAL_GPIOEx_DisableEventout(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_GPIO_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1395 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_rcc.h
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief Header file of RCC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_RCC_H
+#define __STM32F1xx_HAL_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/** @addtogroup RCC_Private_Constants
+ * @{
+ */
+
+/** @defgroup RCC_Timeout RCC Timeout
+ * @{
+ */
+
+/* Disable Backup domain write protection state change timeout */
+#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+/* LSE state change timeout */
+#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
+#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
+#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */
+#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */
+#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */
+#define LSI_VALUE ((uint32_t)40000) /* 40kHz */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Register_Offset Register offsets
+ * @{
+ */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+#define RCC_CR_OFFSET 0x00
+#define RCC_CFGR_OFFSET 0x04
+#define RCC_CIR_OFFSET 0x08
+#define RCC_BDCR_OFFSET 0x20
+#define RCC_CSR_OFFSET 0x24
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
+ * @brief RCC registers bit address in the alias region
+ * @{
+ */
+#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
+#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
+#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
+#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
+#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
+
+/* --- CR Register ---*/
+/* Alias word address of HSION bit */
+#define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION)
+#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSION_BIT_NUMBER * 4)))
+/* Alias word address of HSEON bit */
+#define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON)
+#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSEON_BIT_NUMBER * 4)))
+/* Alias word address of CSSON bit */
+#define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON)
+#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_CSSON_BIT_NUMBER * 4)))
+/* Alias word address of PLLON bit */
+#define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON)
+#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_PLLON_BIT_NUMBER * 4)))
+
+/* --- CSR Register ---*/
+/* Alias word address of LSION bit */
+#define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION)
+#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSION_BIT_NUMBER * 4)))
+
+/* Alias word address of RMVF bit */
+#define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF)
+#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RMVF_BIT_NUMBER * 4)))
+
+/* --- BDCR Registers ---*/
+/* Alias word address of LSEON bit */
+#define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEON)
+#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEON_BIT_NUMBER * 4)))
+
+/* Alias word address of LSEON bit */
+#define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEBYP)
+#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEBYP_BIT_NUMBER * 4)))
+
+/* Alias word address of RTCEN bit */
+#define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_BDCR_RTCEN)
+#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_RTCEN_BIT_NUMBER * 4)))
+
+/* Alias word address of BDRST bit */
+#define RCC_BDRST_BIT_NUMBER POSITION_VAL(RCC_BDCR_BDRST)
+#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_BDRST_BIT_NUMBER * 4)))
+
+/**
+ * @}
+ */
+
+/* CR register byte 2 (Bits[23:16]) base address */
+#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
+
+/* CIR register byte 1 (Bits[15:8]) base address */
+#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
+
+/* CIR register byte 2 (Bits[23:16]) base address */
+#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
+
+/* Defines used for Flags */
+#define CR_REG_INDEX ((uint8_t)1)
+#define BDCR_REG_INDEX ((uint8_t)2)
+#define CSR_REG_INDEX ((uint8_t)3)
+
+#define RCC_FLAG_MASK ((uint8_t)0x1F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Macros
+ * @{
+ */
+/** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy
+ * @{
+ */
+#define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+/**
+ * @}
+ */
+
+#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \
+ ((__SOURCE__) == RCC_PLLSOURCE_HSE))
+#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
+#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
+ ((__HSE__) == RCC_HSE_BYPASS))
+#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
+ ((__LSE__) == RCC_LSE_BYPASS))
+#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
+#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
+#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
+#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
+ ((__PLL__) == RCC_PLL_ON))
+
+#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
+ (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
+ (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \
+ (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
+#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
+#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
+#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV512))
+#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
+ ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
+ ((__PCLK__) == RCC_HCLK_DIV16))
+#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
+#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
+#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Types RCC Exported Types
+ * @{
+ */
+
+/**
+ * @brief RCC PLL configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PLLState; /*!< PLLState: The new state of the PLL.
+ This parameter can be a value of @ref RCC_PLL_Config */
+
+ uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
+ This parameter must be a value of @ref RCC_PLL_Clock_Source */
+
+ uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
+ This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */
+} RCC_PLLInitTypeDef;
+
+/**
+ * @brief RCC System, AHB and APB busses clock configuration structure definition
+ */
+typedef struct
+{
+ uint32_t ClockType; /*!< The clock to be configured.
+ This parameter can be a value of @ref RCC_System_Clock_Type */
+
+ uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
+ This parameter can be a value of @ref RCC_System_Clock_Source */
+
+ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+ This parameter can be a value of @ref RCC_AHB_Clock_Source */
+
+ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+
+ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+} RCC_ClkInitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_Exported_Constants RCC Exported Constants
+ * @{
+ */
+
+/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
+ * @{
+ */
+
+#define RCC_PLLSOURCE_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Oscillator_Type Oscillator Type
+ * @{
+ */
+#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
+#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
+#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
+#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
+#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSE_Config HSE Config
+ * @{
+ */
+#define RCC_HSE_OFF ((uint32_t)0x00000000) /*!< HSE clock deactivation */
+#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
+#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSE_Config LSE Config
+ * @{
+ */
+#define RCC_LSE_OFF ((uint32_t)0x00000000) /*!< LSE clock deactivation */
+#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
+#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSI_Config HSI Config
+ * @{
+ */
+#define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */
+#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
+
+#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSI_Config LSI Config
+ * @{
+ */
+#define RCC_LSI_OFF ((uint32_t)0x00000000) /*!< LSI clock deactivation */
+#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Config PLL Config
+ * @{
+ */
+#define RCC_PLL_NONE ((uint32_t)0x00000000) /*!< PLL is not configured */
+#define RCC_PLL_OFF ((uint32_t)0x00000001) /*!< PLL deactivation */
+#define RCC_PLL_ON ((uint32_t)0x00000002) /*!< PLL activation */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Type System Clock Type
+ * @{
+ */
+#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /*!< SYSCLK to configure */
+#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /*!< HCLK to configure */
+#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /*!< PCLK1 to configure */
+#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /*!< PCLK2 to configure */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Source System Clock Source
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
+#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
+#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
+ * @{
+ */
+#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
+#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
+#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
+#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
+#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
+#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
+#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
+#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
+#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
+ * @{
+ */
+#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
+#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
+#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
+#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
+#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
+ * @{
+ */
+#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 128 used as RTC clock */
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_MCO_Index MCO Index
+ * @{
+ */
+#define RCC_MCO1 ((uint32_t)0x00000000)
+#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
+ * @{
+ */
+#define RCC_MCODIV_1 ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Interrupt Interrupts
+ * @{
+ */
+#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
+#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
+#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
+#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
+#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
+#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flag Flags
+ * Elements values convention: XXXYYYYYb
+ * - YYYYY : Flag position in the register
+ * - XXX : Register index
+ * - 001: CR register
+ * - 010: BDCR register
+ * - 011: CSR register
+ * @{
+ */
+/* Flags in the CR register */
+#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */
+#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */
+#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */
+
+/* Flags in the CSR register */
+#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */
+#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */
+#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */
+#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */
+#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
+#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
+#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
+
+/* Flags in the BDCR register */
+#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< External Low Speed oscillator Ready */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Macros RCC Exported Macros
+ * @{
+ */
+
+/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
+ /* Delay after an RCC peripheral clock enabling */\
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
+ /* Delay after an RCC peripheral clock enabling */\
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
+ /* Delay after an RCC peripheral clock enabling */\
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
+ /* Delay after an RCC peripheral clock enabling */\
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
+#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
+#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
+#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
+#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
+#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
+#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
+#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
+#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
+#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ /* Delay after an RCC peripheral clock enabling */\
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ /* Delay after an RCC peripheral clock enabling */\
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+ /* Delay after an RCC peripheral clock enabling */\
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_USART2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+ /* Delay after an RCC peripheral clock enabling */\
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+ /* Delay after an RCC peripheral clock enabling */\
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_BKP_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
+ /* Delay after an RCC peripheral clock enabling */\
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_PWR_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+ /* Delay after an RCC peripheral clock enabling */\
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
+#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
+
+#define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
+#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
+#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
+#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
+#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
+#define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
+#define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
+#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
+#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_AFIO_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
+ /* Delay after an RCC peripheral clock enabling */\
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
+ /* Delay after an RCC peripheral clock enabling */\
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
+ /* Delay after an RCC peripheral clock enabling */\
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
+ /* Delay after an RCC peripheral clock enabling */\
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
+ /* Delay after an RCC peripheral clock enabling */\
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+ /* Delay after an RCC peripheral clock enabling */\
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+ /* Delay after an RCC peripheral clock enabling */\
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ /* Delay after an RCC peripheral clock enabling */\
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_USART1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+ /* Delay after an RCC peripheral clock enabling */\
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
+#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
+#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))
+#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))
+#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
+
+#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
+#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
+#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+
+#define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)
+#define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
+#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
+#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
+#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
+#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
+
+#define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST))
+#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
+
+#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
+
+#define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))
+#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST))
+#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST))
+#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST))
+#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST))
+#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST))
+#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
+
+#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
+#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
+
+#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
+#define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))
+#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))
+#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))
+#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))
+#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
+
+#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
+#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSI_Configuration HSI Configuration
+ * @{
+ */
+
+/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
+ * @note HSI can not be stopped if it is used as system clock source. In this case,
+ * you have to select another source of the system clock then stop the HSI.
+ * @note After enabling the HSI, the application software should wait on HSIRDY
+ * flag to be set indicating that HSI clock is stable and can be used as
+ * system clock source.
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+ * clock cycles.
+ */
+#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
+#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
+
+/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
+ * @note The calibration is used to compensate for the variations in voltage
+ * and temperature that influence the frequency of the internal HSI RC.
+ * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
+ * (default is RCC_HSICALIBRATION_DEFAULT).
+ * This parameter must be a number between 0 and 0x1F.
+ */
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
+ (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSI_Configuration LSI Configuration
+ * @{
+ */
+
+/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
+ * @note After enabling the LSI, the application software should wait on
+ * LSIRDY flag to be set indicating that LSI clock is stable and can
+ * be used to clock the IWDG and/or the RTC.
+ */
+#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
+
+/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
+ * @note LSI can not be disabled if the IWDG is running.
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+ * clock cycles.
+ */
+#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSE_Configuration HSE Configuration
+ * @{
+ */
+
+/**
+ * @brief Macro to configure the External High Speed oscillator (HSE).
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+ * supported by this macro. User should request a transition to HSE Off
+ * first and then HSE On or HSE Bypass.
+ * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+ * software should wait on HSERDY flag to be set indicating that HSE clock
+ * is stable and can be used to clock the PLL and/or system clock.
+ * @note HSE state can not be changed if it is used directly or through the
+ * PLL as system clock. In this case, you have to select another source
+ * of the system clock then change the HSE state (ex. disable it).
+ * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
+ * @note This function reset the CSSON bit, so if the clock security system(CSS)
+ * was previously enabled you have to enable it again after calling this
+ * function.
+ * @param __STATE__ specifies the new state of the HSE.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
+ * 6 HSE oscillator clock cycles.
+ * @arg @ref RCC_HSE_ON turn ON the HSE oscillator
+ * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
+ */
+#define __HAL_RCC_HSE_CONFIG(__STATE__) \
+ do{ \
+ if ((__STATE__) == RCC_HSE_ON) \
+ { \
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \
+ } \
+ else if ((__STATE__) == RCC_HSE_OFF) \
+ { \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ } \
+ else if ((__STATE__) == RCC_HSE_BYPASS) \
+ { \
+ SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \
+ } \
+ else \
+ { \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ } \
+ }while(0)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSE_Configuration LSE Configuration
+ * @{
+ */
+
+/**
+ * @brief Macro to configure the External Low Speed oscillator (LSE).
+ * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
+ * @note As the LSE is in the Backup domain and write access is denied to
+ * this domain after reset, you have to enable write access using
+ * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+ * (to be done once after reset).
+ * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
+ * software should wait on LSERDY flag to be set indicating that LSE clock
+ * is stable and can be used to clock the RTC.
+ * @param __STATE__ specifies the new state of the LSE.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
+ * 6 LSE oscillator clock cycles.
+ * @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
+ * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
+ */
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \
+ do{ \
+ if ((__STATE__) == RCC_LSE_ON) \
+ { \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ } \
+ else if ((__STATE__) == RCC_LSE_OFF) \
+ { \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ } \
+ else if ((__STATE__) == RCC_LSE_BYPASS) \
+ { \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ } \
+ else \
+ { \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ } \
+ }while(0)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Configuration PLL Configuration
+ * @{
+ */
+
+/** @brief Macro to enable the main PLL.
+ * @note After enabling the main PLL, the application software should wait on
+ * PLLRDY flag to be set indicating that PLL clock is stable and can
+ * be used as system clock source.
+ * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
+
+/** @brief Macro to disable the main PLL.
+ * @note The main PLL can not be disabled if it is used as system clock source
+ */
+#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
+
+/** @brief Macro to configure the main PLL clock source and multiplication factors.
+ * @note This function must be used only when the main PLL is disabled.
+ *
+ * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry
+ * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
+ * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4
+ * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6
+ @if STM32F105xC
+ * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
+ @elseif STM32F107xC
+ * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
+ @else
+ * @arg @ref RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2
+ * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3
+ * @arg @ref RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10
+ * @arg @ref RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11
+ * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12
+ * @arg @ref RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13
+ * @arg @ref RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14
+ * @arg @ref RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15
+ * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16
+ @endif
+ * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8
+ * @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9
+ *
+ */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))
+
+/** @brief Get oscillator clock selected as PLL input clock
+ * @retval The clock source used for PLL entry. The returned value can be one
+ * of the following:
+ * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock
+ * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
+ */
+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Get_Clock_source Get Clock source
+ * @{
+ */
+
+/**
+ * @brief Macro to configure the system clock source.
+ * @param __SYSCLKSOURCE__ specifies the system clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
+ * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
+ * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
+ */
+#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
+
+/** @brief Macro to get the clock source used as system clock.
+ * @retval The clock source used as system clock. The returned value can be one
+ * of the following:
+ * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
+ * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
+ * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
+ */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
+ * @{
+ */
+
+#if defined(RCC_CFGR_MCO_3)
+/** @brief Macro to configure the MCO clock.
+ * @param __MCOCLKSOURCE__ specifies the MCO clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected by 2 selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected (for Ethernet) as MCO clock
+ * @param __MCODIV__ specifies the MCO clock prescaler.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
+ */
+#else
+/** @brief Macro to configure the MCO clock.
+ * @param __MCOCLKSOURCE__ specifies the MCO clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock
+ * @param __MCODIV__ specifies the MCO clock prescaler.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
+ */
+#endif
+
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
+
+
+/**
+ * @}
+ */
+
+ /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
+ * @{
+ */
+
+/** @brief Macro to configure the RTC clock (RTCCLK).
+ * @note As the RTC clock configuration bits are in the Backup domain and write
+ * access is denied to this domain after reset, you have to enable write
+ * access using the Power Backup Access macro before to configure
+ * the RTC clock source (to be done once after reset).
+ * @note Once the RTC clock is configured it can't be changed unless the
+ * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
+ * a Power On Reset (POR).
+ *
+ * @param __RTC_CLKSOURCE__ specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
+ * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
+ * work in STOP and STANDBY modes, and can be used as wakeup source.
+ * However, when the HSE clock is used as RTC clock source, the RTC
+ * cannot be used in STOP and STANDBY modes.
+ * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
+ * RTC clock source).
+ */
+#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
+
+/** @brief Macro to get the RTC clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
+ */
+#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
+
+/** @brief Macro to enable the the RTC clock.
+ * @note These macros must be used only after the RTC clock source was selected.
+ */
+#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
+
+/** @brief Macro to disable the the RTC clock.
+ * @note These macros must be used only after the RTC clock source was selected.
+ */
+#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
+
+/** @brief Macro to force the Backup domain reset.
+ * @note This function resets the RTC peripheral (including the backup registers)
+ * and the RTC clock source selection in RCC_BDCR register.
+ */
+#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
+
+/** @brief Macros to release the Backup domain reset.
+ */
+#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
+ * @brief macros to manage the specified RCC Flags and interrupts.
+ * @{
+ */
+
+/** @brief Enable RCC interrupt.
+ * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
+ * @arg @ref RCC_IT_LSERDY LSE ready interrupt
+ * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
+ * @arg @ref RCC_IT_HSERDY HSE ready interrupt
+ * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
+ @if STM32F105xx
+ * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
+ * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
+ @elsif STM32F107xx
+ * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
+ * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
+ @endif
+ */
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
+
+/** @brief Disable RCC interrupt.
+ * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
+ * @arg @ref RCC_IT_LSERDY LSE ready interrupt
+ * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
+ * @arg @ref RCC_IT_HSERDY HSE ready interrupt
+ * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
+ @if STM32F105xx
+ * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
+ * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
+ @elsif STM32F107xx
+ * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
+ * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
+ @endif
+ */
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
+
+/** @brief Clear the RCC's interrupt pending bits.
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
+ * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
+ * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
+ * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
+ * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
+ @if STM32F105xx
+ * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
+ * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
+ @elsif STM32F107xx
+ * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
+ * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
+ @endif
+ * @arg @ref RCC_IT_CSS Clock Security System interrupt
+ */
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
+
+/** @brief Check the RCC's interrupt has occurred or not.
+ * @param __INTERRUPT__ specifies the RCC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
+ * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
+ * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
+ * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
+ * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
+ @if STM32F105xx
+ * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
+ * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
+ @elsif STM32F107xx
+ * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
+ * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
+ @endif
+ * @arg @ref RCC_IT_CSS Clock Security System interrupt
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Set RMVF bit to clear the reset flags.
+ * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
+ * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
+ */
+#define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)
+
+/** @brief Check RCC flag is set or not.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
+ * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
+ * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
+ @if STM32F105xx
+ * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
+ * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
+ @elsif STM32F107xx
+ * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
+ * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
+ @endif
+ * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
+ * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
+ * @arg @ref RCC_FLAG_PINRST Pin reset.
+ * @arg @ref RCC_FLAG_PORRST POR/PDR reset.
+ * @arg @ref RCC_FLAG_SFTRST Software reset.
+ * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
+ * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
+ * @arg @ref RCC_FLAG_LPWRRST Low Power reset.
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : \
+ ((((__FLAG__) >> 5) == BDCR_REG_INDEX)? RCC->BDCR : \
+ RCC->CSR)) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Include RCC HAL Extension module */
+#include "stm32f1xx_hal_rcc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCC_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization and de-initialization functions ******************************/
+void HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Functions_Group2
+ * @{
+ */
+
+/* Peripheral Control functions ************************************************/
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
+void HAL_RCC_EnableCSS(void);
+void HAL_RCC_DisableCSS(void);
+uint32_t HAL_RCC_GetSysClockFreq(void);
+uint32_t HAL_RCC_GetHCLKFreq(void);
+uint32_t HAL_RCC_GetPCLK1Freq(void);
+uint32_t HAL_RCC_GetPCLK2Freq(void);
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
+
+/* CSS NMI IRQ handler */
+void HAL_RCC_NMI_IRQHandler(void);
+
+/* User Callbacks in non blocking mode (IT mode) */
+void HAL_RCC_CSSCallback(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_RCC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1926 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_rcc_ex.h
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief Header file of RCC HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_RCC_EX_H
+#define __STM32F1xx_HAL_RCC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RCCEx
+ * @{
+ */
+
+/** @addtogroup RCCEx_Private_Constants
+ * @{
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+
+/* Alias word address of PLLI2SON bit */
+#define PLLI2SON_BITNUMBER POSITION_VAL(RCC_CR_PLL3ON)
+#define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLI2SON_BITNUMBER * 4)))
+/* Alias word address of PLL2ON bit */
+#define PLL2ON_BITNUMBER POSITION_VAL(RCC_CR_PLL2ON)
+#define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLL2ON_BITNUMBER * 4)))
+
+#define PLLI2S_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+#define PLL2_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+
+#endif /* STM32F105xC || STM32F107xC */
+
+
+#define CR_REG_INDEX ((uint8_t)1)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCCEx_Private_Macros
+ * @{
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || \
+ ((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2))
+#endif /* STM32F105xC || STM32F107xC */
+
+#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
+ || defined(STM32F100xE)
+#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2) || \
+ ((__DIV__) == RCC_HSE_PREDIV_DIV3) || ((__DIV__) == RCC_HSE_PREDIV_DIV4) || \
+ ((__DIV__) == RCC_HSE_PREDIV_DIV5) || ((__DIV__) == RCC_HSE_PREDIV_DIV6) || \
+ ((__DIV__) == RCC_HSE_PREDIV_DIV7) || ((__DIV__) == RCC_HSE_PREDIV_DIV8) || \
+ ((__DIV__) == RCC_HSE_PREDIV_DIV9) || ((__DIV__) == RCC_HSE_PREDIV_DIV10) || \
+ ((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || \
+ ((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || \
+ ((__DIV__) == RCC_HSE_PREDIV_DIV15) || ((__DIV__) == RCC_HSE_PREDIV_DIV16))
+
+#else
+#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2))
+#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
+ ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
+ ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
+ ((__MUL__) == RCC_PLL_MUL6_5))
+
+#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
+ || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
+ || ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \
+ || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \
+ || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
+
+#else
+#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \
+ ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
+ ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
+ ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
+ ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \
+ ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \
+ ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \
+ ((__MUL__) == RCC_PLL_MUL16))
+
+#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
+ || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
+ || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
+
+#endif /* STM32F105xC || STM32F107xC*/
+
+#define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) || \
+ ((__ADCCLK__) == RCC_ADCPCLK2_DIV6) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8))
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO))
+
+#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO))
+
+#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV2) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV3))
+
+#define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8) || ((__MUL__) == RCC_PLLI2S_MUL9) || \
+ ((__MUL__) == RCC_PLLI2S_MUL10) || ((__MUL__) == RCC_PLLI2S_MUL11) || \
+ ((__MUL__) == RCC_PLLI2S_MUL12) || ((__MUL__) == RCC_PLLI2S_MUL13) || \
+ ((__MUL__) == RCC_PLLI2S_MUL14) || ((__MUL__) == RCC_PLLI2S_MUL16) || \
+ ((__MUL__) == RCC_PLLI2S_MUL20))
+
+#define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1) || ((__DIV__) == RCC_HSE_PREDIV2_DIV2) || \
+ ((__DIV__) == RCC_HSE_PREDIV2_DIV3) || ((__DIV__) == RCC_HSE_PREDIV2_DIV4) || \
+ ((__DIV__) == RCC_HSE_PREDIV2_DIV5) || ((__DIV__) == RCC_HSE_PREDIV2_DIV6) || \
+ ((__DIV__) == RCC_HSE_PREDIV2_DIV7) || ((__DIV__) == RCC_HSE_PREDIV2_DIV8) || \
+ ((__DIV__) == RCC_HSE_PREDIV2_DIV9) || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) || \
+ ((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || \
+ ((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14) || \
+ ((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16))
+
+#define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || \
+ ((__PLL__) == RCC_PLL2_ON))
+
+#define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8) || ((__MUL__) == RCC_PLL2_MUL9) || \
+ ((__MUL__) == RCC_PLL2_MUL10) || ((__MUL__) == RCC_PLL2_MUL11) || \
+ ((__MUL__) == RCC_PLL2_MUL12) || ((__MUL__) == RCC_PLL2_MUL13) || \
+ ((__MUL__) == RCC_PLL2_MUL14) || ((__MUL__) == RCC_PLL2_MUL16) || \
+ ((__MUL__) == RCC_PLL2_MUL20))
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
+ ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
+
+#elif defined(STM32F103xE) || defined(STM32F103xG)
+
+#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)
+
+#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK)
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
+ ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
+
+
+#elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
+ || defined(STM32F103xB)
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
+ ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
+
+#else
+
+#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
+ ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC))
+
+#endif /* STM32F105xC || STM32F107xC */
+
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
+ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
+
+#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5))
+
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+ * @{
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+/**
+ * @brief RCC PLL2 configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PLL2State; /*!< The new state of the PLL2.
+ This parameter can be a value of @ref RCCEx_PLL2_Config */
+
+ uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock
+ This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.
+ This parameter can be a value of @ref RCCEx_Prediv2_Factor */
+
+#endif /* STM32F105xC || STM32F107xC */
+} RCC_PLL2InitTypeDef;
+
+#endif /* STM32F105xC || STM32F107xC */
+
+/**
+ * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
+ */
+typedef struct
+{
+ uint32_t OscillatorType; /*!< The oscillators to be configured.
+ This parameter can be a value of @ref RCC_Oscillator_Type */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ uint32_t Prediv1Source; /*!< The Prediv1 source value.
+ This parameter can be a value of @ref RCCEx_Prediv1_Source */
+#endif /* STM32F105xC || STM32F107xC */
+
+ uint32_t HSEState; /*!< The new state of the HSE.
+ This parameter can be a value of @ref RCC_HSE_Config */
+
+ uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM)
+ This parameter can be a value of @ref RCCEx_Prediv1_Factor */
+
+ uint32_t LSEState; /*!< The new state of the LSE.
+ This parameter can be a value of @ref RCC_LSE_Config */
+
+ uint32_t HSIState; /*!< The new state of the HSI.
+ This parameter can be a value of @ref RCC_HSI_Config */
+
+ uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+
+ uint32_t LSIState; /*!< The new state of the LSI.
+ This parameter can be a value of @ref RCC_LSI_Config */
+
+ RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */
+#endif /* STM32F105xC || STM32F107xC */
+} RCC_OscInitTypeDef;
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+/**
+ * @brief RCC PLLI2S configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock
+ This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.
+ This parameter can be a value of @ref RCCEx_Prediv2_Factor */
+
+#endif /* STM32F105xC || STM32F107xC */
+} RCC_PLLI2SInitTypeDef;
+#endif /* STM32F105xC || STM32F107xC */
+
+/**
+ * @brief RCC extended clocks structure definition
+ */
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< specifies the RTC clock source.
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t AdcClockSelection; /*!< ADC clock source
+ This parameter can be a value of @ref RCCEx_ADC_Prescaler */
+
+#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
+ || defined(STM32F107xC)
+ uint32_t I2s2ClockSelection; /*!< I2S2 clock source
+ This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */
+
+ uint32_t I2s3ClockSelection; /*!< I2S3 clock source
+ This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */
+
+#endif /* STM32F105xC || STM32F107xC */
+#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
+ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
+ || defined(STM32F105xC) || defined(STM32F107xC)
+ uint32_t UsbClockSelection; /*!< USB clock source
+ This parameter can be a value of @ref RCCEx_USB_Prescaler */
+
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+} RCC_PeriphCLKInitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
+ * @{
+ */
+
+/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
+ * @{
+ */
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_ADC ((uint32_t)0x00000002)
+#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
+ || defined(STM32F107xC)
+#define RCC_PERIPHCLK_I2S2 ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_I2S3 ((uint32_t)0x00000008)
+#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
+ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
+ || defined(STM32F105xC) || defined(STM32F107xC)
+#define RCC_PERIPHCLK_USB ((uint32_t)0x00000010)
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_ADC_Prescaler ADC Prescaler
+ * @{
+ */
+#define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
+#define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
+#define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
+#define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
+
+/**
+ * @}
+ */
+
+#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
+ || defined(STM32F107xC)
+/** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source
+ * @{
+ */
+#define RCC_I2S2CLKSOURCE_SYSCLK ((uint32_t)0x00000000)
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC
+#endif /* STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source
+ * @{
+ */
+#define RCC_I2S3CLKSOURCE_SYSCLK ((uint32_t)0x00000000)
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC
+#endif /* STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
+ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
+
+/** @defgroup RCCEx_USB_Prescaler USB Prescaler
+ * @{
+ */
+#define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE
+#define RCC_USBCLKSOURCE_PLL_DIV1_5 ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
+
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+/** @defgroup RCCEx_USB_Prescaler USB Prescaler
+ * @{
+ */
+#define RCC_USBCLKSOURCE_PLL_DIV2 RCC_CFGR_OTGFSPRE
+#define RCC_USBCLKSOURCE_PLL_DIV3 ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor
+ * @{
+ */
+
+#define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */
+#define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */
+#define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */
+#define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */
+#define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */
+#define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */
+#define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */
+#define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */
+#define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */
+
+/**
+ * @}
+ */
+#endif /* STM32F105xC || STM32F107xC */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+/** @defgroup RCCEx_Prediv1_Source Prediv1 Source
+ * @{
+ */
+
+#define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE
+#define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2
+
+/**
+ * @}
+ */
+#endif /* STM32F105xC || STM32F107xC */
+
+/** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor
+ * @{
+ */
+
+#define RCC_HSE_PREDIV_DIV1 ((uint32_t)0x00000000)
+
+#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
+ || defined(STM32F100xE)
+#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2
+#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3
+#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4
+#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5
+#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6
+#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7
+#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8
+#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9
+#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10
+#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11
+#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12
+#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13
+#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14
+#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15
+#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16
+#else
+#define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE
+#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
+
+/**
+ * @}
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+/** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor
+ * @{
+ */
+
+#define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */
+#define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */
+#define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */
+#define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */
+#define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */
+#define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */
+#define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */
+#define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */
+#define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */
+#define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */
+#define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */
+#define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */
+#define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */
+#define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */
+#define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */
+#define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_PLL2_Config PLL Config
+ * @{
+ */
+#define RCC_PLL2_NONE ((uint32_t)0x00000000)
+#define RCC_PLL2_OFF ((uint32_t)0x00000001)
+#define RCC_PLL2_ON ((uint32_t)0x00000002)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor
+ * @{
+ */
+
+#define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */
+#define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */
+#define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */
+#define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */
+#define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */
+#define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */
+#define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */
+#define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */
+#define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F105xC || STM32F107xC */
+
+/** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor
+ * @{
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#else
+#define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2
+#define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3
+#endif /* STM32F105xC || STM32F107xC */
+#define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4
+#define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5
+#define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6
+#define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7
+#define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8
+#define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5
+#else
+#define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10
+#define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11
+#define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12
+#define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13
+#define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14
+#define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15
+#define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16
+#endif /* STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source
+ * @{
+ */
+#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK)
+#define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK)
+#define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI)
+#define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE)
+#define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2)
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK)
+#define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2)
+#define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE)
+#define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK)
+#endif /* STM32F105xC || STM32F107xC*/
+/**
+ * @}
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+/** @defgroup RCCEx_Interrupt RCCEx Interrupt
+ * @{
+ */
+#define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF)
+#define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_Flag RCCEx Flag
+ * Elements values convention: 0XXYYYYYb
+ * - YYYYY : Flag position in the register
+ * - XX : Register index
+ * - 01: CR register
+ * @{
+ */
+/* Flags in the CR register */
+#define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLL2RDY)))
+#define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLL3RDY)))
+/**
+ * @}
+ */
+#endif /* STM32F105xC || STM32F107xC*/
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
+ * @{
+ */
+
+/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+
+#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
+ || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\
+ || defined (STM32F100xE)
+#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
+
+#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
+ || defined(STM32F103xG) || defined (STM32F100xE)
+#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
+
+#if defined(STM32F103xE) || defined(STM32F103xG)
+#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+
+#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN))
+#endif /* STM32F103xE || STM32F103xG */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN))
+#endif /* STM32F105xC || STM32F107xC*/
+
+#if defined(STM32F107xC)
+#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN))
+#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN))
+#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN))
+
+/**
+ * @brief Enable ETHERNET clock.
+ */
+#define __HAL_RCC_ETH_CLK_ENABLE() do { \
+ __HAL_RCC_ETHMAC_CLK_ENABLE(); \
+ __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
+ __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
+ } while(0)
+/**
+ * @brief Disable ETHERNET clock.
+ */
+#define __HAL_RCC_ETH_CLK_DISABLE() do { \
+ __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
+ __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
+ __HAL_RCC_ETHMAC_CLK_DISABLE(); \
+ } while(0)
+
+#endif /* STM32F107xC*/
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+
+#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
+ || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\
+ || defined (STM32F100xE)
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
+#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
+ || defined(STM32F103xG) || defined (STM32F100xE)
+#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET)
+#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET)
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
+#if defined(STM32F103xE) || defined(STM32F103xG)
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET)
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET)
+#endif /* STM32F103xE || STM32F103xG */
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET)
+#endif /* STM32F105xC || STM32F107xC*/
+#if defined(STM32F107xC)
+#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET)
+#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET)
+#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET)
+#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET)
+#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET)
+#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET)
+#endif /* STM32F107xC*/
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
+ || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
+#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
+#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+
+#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
+ || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
+ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
+ || defined(STM32F105xC) || defined(STM32F107xC)
+#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
+#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
+
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
+ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
+#define __HAL_RCC_USB_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
+
+#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
+ || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_UART4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_UART5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_DAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
+
+#if defined(STM32F100xB) || defined (STM32F100xE)
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_DAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_CEC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
+#endif /* STM32F100xB || STM32F100xE */
+
+#ifdef STM32F100xE
+#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_UART4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_UART5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
+#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#endif /* STM32F100xE */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
+#endif /* STM32F105xC || STM32F107xC */
+
+#if defined(STM32F101xG) || defined(STM32F103xG)
+#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#endif /* STM32F101xG || STM32F103xG*/
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
+ || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
+#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
+ || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
+ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
+ || defined(STM32F105xC) || defined(STM32F107xC)
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
+#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
+#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
+#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
+ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
+#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
+#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
+#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
+ || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
+#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
+#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
+#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
+#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
+#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
+#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
+#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
+#if defined(STM32F100xB) || defined (STM32F100xE)
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
+#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
+#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
+#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
+#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
+#endif /* STM32F100xB || STM32F100xE */
+#ifdef STM32F100xE
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
+#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
+#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
+#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
+#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
+#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
+#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
+#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
+#endif /* STM32F100xE */
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
+#endif /* STM32F105xC || STM32F107xC */
+#if defined(STM32F101xG) || defined(STM32F103xG)
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
+#endif /* STM32F101xG || STM32F103xG*/
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+
+#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
+ || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
+ || defined(STM32F103xG)
+#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
+#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
+
+#if defined(STM32F100xB) || defined(STM32F100xE)
+#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
+#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
+#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
+#endif /* STM32F100xB || STM32F100xE */
+
+#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
+ || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
+ || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
+ || defined(STM32F107xC)
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN))
+#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
+
+#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
+ || defined(STM32F103xG)
+#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
+#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
+
+#if defined(STM32F103xE) || defined(STM32F103xG)
+#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
+#endif /* STM32F103xE || STM32F103xG */
+
+#if defined(STM32F100xE)
+#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
+#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
+#endif /* STM32F100xE */
+
+#if defined(STM32F101xG) || defined(STM32F103xG)
+#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
+#endif /* STM32F101xG || STM32F103xG */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+
+#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
+ || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
+ || defined(STM32F103xG)
+#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
+#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
+#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
+#if defined(STM32F100xB) || defined(STM32F100xE)
+#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
+#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
+#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
+#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
+#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
+#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
+#endif /* STM32F100xB || STM32F100xE */
+#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
+ || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
+ || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
+ || defined(STM32F107xC)
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)
+#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
+#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
+ || defined(STM32F103xG)
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
+#if defined(STM32F103xE) || defined(STM32F103xG)
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
+#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
+#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
+#endif /* STM32F103xE || STM32F103xG */
+#if defined(STM32F100xE)
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
+#endif /* STM32F100xE */
+#if defined(STM32F101xG) || defined(STM32F103xG)
+#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
+#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
+#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
+#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
+#endif /* STM32F101xG || STM32F103xG */
+
+/**
+ * @}
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+/** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release
+ * @brief Force or release AHB peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST))
+#if defined(STM32F107xC)
+#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST))
+#endif /* STM32F107xC */
+
+#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST))
+#if defined(STM32F107xC)
+#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST))
+#endif /* STM32F107xC */
+
+/**
+ * @}
+ */
+#endif /* STM32F105xC || STM32F107xC */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ * @{
+ */
+
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
+ || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
+#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
+
+#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
+#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+
+#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
+ || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
+ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
+ || defined(STM32F105xC) || defined(STM32F107xC)
+#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
+
+#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
+#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
+
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
+ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
+#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
+#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
+
+#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
+ || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+
+#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
+
+#if defined(STM32F100xB) || defined (STM32F100xE)
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
+
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
+#endif /* STM32F100xB || STM32F100xE */
+
+#if defined (STM32F100xE)
+#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
+#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
+
+#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
+#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#endif /* STM32F100xE */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
+
+#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
+#endif /* STM32F105xC || STM32F107xC */
+
+#if defined(STM32F101xG) || defined(STM32F103xG)
+#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+
+#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#endif /* STM32F101xG || STM32F103xG */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ * @{
+ */
+
+#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
+ || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
+ || defined(STM32F103xG)
+#define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST))
+
+#define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))
+#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
+
+#if defined(STM32F100xB) || defined(STM32F100xE)
+#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
+#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
+#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
+
+#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
+#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
+#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
+#endif /* STM32F100xB || STM32F100xE */
+
+#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
+ || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
+ || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
+ || defined(STM32F107xC)
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST))
+
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))
+#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
+
+#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
+ || defined(STM32F103xG)
+#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
+#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
+
+#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
+
+#if defined(STM32F103xE) || defined(STM32F103xG)
+#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST))
+
+#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST))
+#endif /* STM32F103xE || STM32F103xG */
+
+#if defined(STM32F100xE)
+#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
+#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
+
+#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
+#endif /* STM32F100xE */
+
+#if defined(STM32F101xG) || defined(STM32F103xG)
+#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
+#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
+
+#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
+#endif /* STM32F101xG || STM32F103xG*/
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_HSE_Configuration HSE Configuration
+ * @{
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
+ || defined(STM32F100xE)
+/**
+ * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
+ * @note Predivision factor can not be changed if PLL is used as system clock
+ * In this case, you have to select another source of the system clock, disable the PLL and
+ * then change the HSE predivision factor.
+ * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
+ * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
+ */
+#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__))
+#else
+/**
+ * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
+ * @note Predivision factor can not be changed if PLL is used as system clock
+ * In this case, you have to select another source of the system clock, disable the PLL and
+ * then change the HSE predivision factor.
+ * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
+ * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2.
+ */
+#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
+ MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))
+
+#endif /* STM32F105xC || STM32F107xC */
+
+#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
+ || defined(STM32F100xE)
+/**
+ * @brief Macro to get prediv1 factor for PLL.
+ */
+#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)
+
+#else
+/**
+ * @brief Macro to get prediv1 factor for PLL.
+ */
+#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)
+
+#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
+
+/**
+ * @}
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+/** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration
+ * @{
+ */
+
+/** @brief Macros to enable the main PLLI2S.
+ * @note After enabling the main PLLI2S, the application software should wait on
+ * PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can
+ * be used as system clock source.
+ * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
+
+/** @brief Macros to disable the main PLLI2S.
+ * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
+
+/** @brief macros to configure the main PLLI2S multiplication factor.
+ * @note This function must be used only when the main PLLI2S is disabled.
+ *
+ * @param __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8
+ * @arg @ref RCC_PLLI2S_MUL9 PLLI2SVCO = PLLI2S clock entry x 9
+ * @arg @ref RCC_PLLI2S_MUL10 PLLI2SVCO = PLLI2S clock entry x 10
+ * @arg @ref RCC_PLLI2S_MUL11 PLLI2SVCO = PLLI2S clock entry x 11
+ * @arg @ref RCC_PLLI2S_MUL12 PLLI2SVCO = PLLI2S clock entry x 12
+ * @arg @ref RCC_PLLI2S_MUL13 PLLI2SVCO = PLLI2S clock entry x 13
+ * @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14
+ * @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16
+ * @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20
+ *
+ */
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__))
+
+/**
+ * @}
+ */
+
+#endif /* STM32F105xC || STM32F107xC */
+
+/** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration
+ * @brief Macros to configure clock source of different peripherals.
+ * @{
+ */
+
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
+ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
+/** @brief Macro to configure the USB clock.
+ * @param __USBCLKSOURCE__ specifies the USB clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock
+ * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock
+ */
+#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))
+
+/** @brief Macro to get the USB clock (USBCLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock
+ * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock
+ */
+#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
+
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+
+/** @brief Macro to configure the USB OTSclock.
+ * @param __USBCLKSOURCE__ specifies the USB clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock
+ * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock
+ */
+#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__))
+
+/** @brief Macro to get the USB clock (USBCLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock
+ * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock
+ */
+#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE)))
+
+#endif /* STM32F105xC || STM32F107xC */
+
+/** @brief Macro to configure the ADCx clock (x=1 to 3 depending on devices).
+ * @param __ADCCLKSOURCE__ specifies the ADC clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock
+ * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock
+ * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock
+ * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock
+ */
+#define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))
+
+/** @brief Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock
+ * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock
+ * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock
+ * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock
+ */
+#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
+
+/**
+ * @}
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+
+/** @addtogroup RCCEx_HSE_Configuration
+ * @{
+ */
+
+/**
+ * @brief Macro to configure the PLL2 & PLLI2S Predivision factor.
+ * @note Predivision factor can not be changed if PLL2 is used indirectly as system clock
+ * In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and
+ * then change the PREDIV2 factor.
+ * @param __HSE_PREDIV2_VALUE__ specifies the PREDIV2 value applied to PLL2 & PLLI2S.
+ * This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16.
+ */
+#define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__))
+
+/**
+ * @brief Macro to get prediv2 factor for PLL2 & PLL3.
+ */
+#define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCCEx_PLLI2S_Configuration
+ * @{
+ */
+
+/** @brief Macros to enable the main PLL2.
+ * @note After enabling the main PLL2, the application software should wait on
+ * PLL2RDY flag to be set indicating that PLL2 clock is stable and can
+ * be used as system clock source.
+ * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLL2_ENABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = ENABLE)
+
+/** @brief Macros to disable the main PLL2.
+ * @note The main PLL2 can not be disabled if it is used indirectly as system clock source
+ * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLL2_DISABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = DISABLE)
+
+/** @brief macros to configure the main PLL2 multiplication factor.
+ * @note This function must be used only when the main PLL2 is disabled.
+ *
+ * @param __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8
+ * @arg @ref RCC_PLL2_MUL9 PLL2VCO = PLL2 clock entry x 9
+ * @arg @ref RCC_PLL2_MUL10 PLL2VCO = PLL2 clock entry x 10
+ * @arg @ref RCC_PLL2_MUL11 PLL2VCO = PLL2 clock entry x 11
+ * @arg @ref RCC_PLL2_MUL12 PLL2VCO = PLL2 clock entry x 12
+ * @arg @ref RCC_PLL2_MUL13 PLL2VCO = PLL2 clock entry x 13
+ * @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14
+ * @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16
+ * @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20
+ *
+ */
+#define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2S_Configuration I2S Configuration
+ * @brief Macros to configure clock source of I2S peripherals.
+ * @{
+ */
+
+/** @brief Macro to configure the I2S2 clock.
+ * @param __I2S2CLKSOURCE__ specifies the I2S2 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
+ * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
+ */
+#define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__))
+
+/** @brief Macro to get the I2S2 clock (I2S2CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
+ * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
+ */
+#define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC)))
+
+/** @brief Macro to configure the I2S3 clock.
+ * @param __I2S2CLKSOURCE__ specifies the I2S3 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
+ * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
+ */
+#define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__))
+
+/** @brief Macro to get the I2S3 clock (I2S3CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
+ * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
+ */
+#define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC)))
+
+/**
+ * @}
+ */
+
+#endif /* STM32F105xC || STM32F107xC */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCCEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCCEx_Exported_Functions_Group1
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
+
+/**
+ * @}
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+/** @addtogroup RCCEx_Exported_Functions_Group2
+ * @{
+ */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCCEx_Exported_Functions_Group3
+ * @{
+ */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init);
+HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void);
+
+/**
+ * @}
+ */
+#endif /* STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_RCC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1767 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_tim.h
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief Header file of TIM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_TIM_H
+#define __STM32F1xx_HAL_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIM_Exported_Types TIM Exported Types
+ * @{
+ */
+/**
+ * @brief TIM Time base Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t CounterMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_Counter_Mode */
+
+ uint32_t Period; /*!< Specifies the period value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t ClockDivision; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_ClockDivision */
+
+ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the RCR value (N).
+ This means in PWM mode that (N+1) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+ @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_Base_InitTypeDef;
+
+/**
+ * @brief TIM Output Compare Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCFastMode; /*!< Specifies the Fast mode state.
+ This parameter can be a value of @ref TIM_Output_Fast_State
+ @note This parameter is valid only in PWM1 and PWM2 mode. */
+
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_OC_InitTypeDef;
+
+/**
+ * @brief TIM One Pulse Mode Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_OnePulse_InitTypeDef;
+
+
+/**
+ * @brief TIM Input Capture Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_IC_InitTypeDef;
+
+/**
+ * @brief TIM Encoder Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Encoder_Mode */
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t IC1Selection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+ uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t IC2Selection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC2Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_Encoder_InitTypeDef;
+
+
+/**
+ * @brief TIM Clock Configuration Handle Structure definition
+ */
+typedef struct
+{
+ uint32_t ClockSource; /*!< TIM clock sources
+ This parameter can be a value of @ref TIM_Clock_Source */
+ uint32_t ClockPolarity; /*!< TIM clock polarity
+ This parameter can be a value of @ref TIM_Clock_Polarity */
+ uint32_t ClockPrescaler; /*!< TIM clock prescaler
+ This parameter can be a value of @ref TIM_Clock_Prescaler */
+ uint32_t ClockFilter; /*!< TIM clock filter
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+}TIM_ClockConfigTypeDef;
+
+/**
+ * @brief TIM Clear Input Configuration Handle Structure definition
+ */
+typedef struct
+{
+ uint32_t ClearInputState; /*!< TIM clear Input state
+ This parameter can be ENABLE or DISABLE */
+ uint32_t ClearInputSource; /*!< TIM clear Input sources
+ This parameter can be a value of @ref TIM_ClearInput_Source */
+ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
+ This parameter can be a value of @ref TIM_ClearInput_Polarity */
+ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
+ This parameter can be a value of @ref TIM_ClearInput_Prescaler */
+ uint32_t ClearInputFilter; /*!< TIM Clear Input filter
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+}TIM_ClearInputConfigTypeDef;
+
+/**
+ * @brief TIM Slave configuration Structure definition
+ */
+typedef struct {
+ uint32_t SlaveMode; /*!< Slave mode selection
+ This parameter can be a value of @ref TIM_Slave_Mode */
+ uint32_t InputTrigger; /*!< Input Trigger source
+ This parameter can be a value of @ref TIM_Trigger_Selection */
+ uint32_t TriggerPolarity; /*!< Input Trigger polarity
+ This parameter can be a value of @ref TIM_Trigger_Polarity */
+ uint32_t TriggerPrescaler; /*!< Input trigger prescaler
+ This parameter can be a value of @ref TIM_Trigger_Prescaler */
+ uint32_t TriggerFilter; /*!< Input trigger filter
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+}TIM_SlaveConfigTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
+ HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
+ HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
+}HAL_TIM_StateTypeDef;
+
+/**
+ * @brief HAL Active channel structures definition
+ */
+typedef enum
+{
+ HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
+ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
+ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
+ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
+ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
+}HAL_TIM_ActiveChannel;
+
+/**
+ * @brief TIM Time Base Handle Structure definition
+ */
+typedef struct
+{
+ TIM_TypeDef *Instance; /*!< Register base address */
+ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
+ HAL_TIM_ActiveChannel Channel; /*!< Active channel */
+ DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
+ This array is accessed by a @ref TIM_DMA_Handle_index */
+ HAL_LockTypeDef Lock; /*!< Locking object */
+ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
+}TIM_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_Exported_Constants TIM Exported Constants
+ * @{
+ */
+
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
+ * @{
+ */
+#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
+ * @{
+ */
+#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
+ * @{
+ */
+#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
+#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
+#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Counter_Mode TIM Counter Mode
+ * @{
+ */
+#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
+#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
+#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
+#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
+#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClockDivision TIM ClockDivision
+ * @{
+ */
+#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
+#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
+#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
+ * @{
+ */
+#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
+#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
+#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
+#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
+#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
+#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
+#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
+#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_State TIM Output Compare State
+ * @{
+ */
+#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
+#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State
+ * @{
+ */
+#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
+#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
+ * @{
+ */
+#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
+#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
+ * @{
+ */
+#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
+#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
+ * @{
+ */
+#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
+#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
+ * @{
+ */
+#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
+#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
+ * @{
+ */
+#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
+#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Channel TIM Channel
+ * @{
+ */
+#define TIM_CHANNEL_1 ((uint32_t)0x0000)
+#define TIM_CHANNEL_2 ((uint32_t)0x0004)
+#define TIM_CHANNEL_3 ((uint32_t)0x0008)
+#define TIM_CHANNEL_4 ((uint32_t)0x000C)
+#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
+ * @{
+ */
+#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
+#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
+#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
+ * @{
+ */
+#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
+ * @{
+ */
+#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
+#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
+#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
+ * @{
+ */
+#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
+#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
+ * @{
+ */
+#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
+#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
+#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
+ * @{
+ */
+#define TIM_IT_UPDATE (TIM_DIER_UIE)
+#define TIM_IT_CC1 (TIM_DIER_CC1IE)
+#define TIM_IT_CC2 (TIM_DIER_CC2IE)
+#define TIM_IT_CC3 (TIM_DIER_CC3IE)
+#define TIM_IT_CC4 (TIM_DIER_CC4IE)
+#define TIM_IT_COM (TIM_DIER_COMIE)
+#define TIM_IT_TRIGGER (TIM_DIER_TIE)
+#define TIM_IT_BREAK (TIM_DIER_BIE)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Commutation_Source TIM Commutation Source
+ * @{
+ */
+#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
+#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_sources TIM DMA Sources
+ * @{
+ */
+#define TIM_DMA_UPDATE (TIM_DIER_UDE)
+#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
+#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
+#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
+#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
+#define TIM_DMA_COM (TIM_DIER_COMDE)
+#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Event_Source TIM Event Source
+ * @{
+ */
+#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
+#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
+#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
+#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
+#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
+#define TIM_EVENTSOURCE_COM TIM_EGR_COMG
+#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
+#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Flag_definition TIM Flag Definition
+ * @{
+ */
+#define TIM_FLAG_UPDATE (TIM_SR_UIF)
+#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
+#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
+#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
+#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
+#define TIM_FLAG_COM (TIM_SR_COMIF)
+#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
+#define TIM_FLAG_BREAK (TIM_SR_BIF)
+#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
+#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
+#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
+#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Source TIM Clock Source
+ * @{
+ */
+#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
+#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
+#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
+#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
+#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
+#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
+#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
+#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
+#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
+#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
+ * @{
+ */
+#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
+ * @{
+ */
+#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Source TIM ClearInput Source
+ * @{
+ */
+#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
+#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)
+#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
+ * @{
+ */
+#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
+ * @{
+ */
+#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
+ * @{
+ */
+#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
+#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
+ * @{
+ */
+#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
+#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Lock_level TIM Lock level
+ * @{
+ */
+#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
+#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
+#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
+#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable
+ * @{
+ */
+#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
+#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
+ * @{
+ */
+#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
+#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
+/**
+ * @}
+ */
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
+ * @{
+ */
+#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
+#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
+ * @{
+ */
+#define TIM_TRGO_RESET ((uint32_t)0x0000)
+#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
+#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
+#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
+#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
+#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
+#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
+#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Slave_Mode TIM Slave Mode
+ * @{
+ */
+#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
+#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
+#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
+#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
+#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
+ * @{
+ */
+#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
+#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
+ * @{
+ */
+#define TIM_TS_ITR0 ((uint32_t)0x0000)
+#define TIM_TS_ITR1 ((uint32_t)0x0010)
+#define TIM_TS_ITR2 ((uint32_t)0x0020)
+#define TIM_TS_ITR3 ((uint32_t)0x0030)
+#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
+#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
+#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
+#define TIM_TS_ETRF ((uint32_t)0x0070)
+#define TIM_TS_NONE ((uint32_t)0xFFFF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
+ * @{
+ */
+#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
+ * @{
+ */
+#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
+ * @{
+ */
+#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
+#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
+ * @{
+ */
+#define TIM_DMABASE_CR1 (0x00000000)
+#define TIM_DMABASE_CR2 (0x00000001)
+#define TIM_DMABASE_SMCR (0x00000002)
+#define TIM_DMABASE_DIER (0x00000003)
+#define TIM_DMABASE_SR (0x00000004)
+#define TIM_DMABASE_EGR (0x00000005)
+#define TIM_DMABASE_CCMR1 (0x00000006)
+#define TIM_DMABASE_CCMR2 (0x00000007)
+#define TIM_DMABASE_CCER (0x00000008)
+#define TIM_DMABASE_CNT (0x00000009)
+#define TIM_DMABASE_PSC (0x0000000A)
+#define TIM_DMABASE_ARR (0x0000000B)
+#define TIM_DMABASE_RCR (0x0000000C)
+#define TIM_DMABASE_CCR1 (0x0000000D)
+#define TIM_DMABASE_CCR2 (0x0000000E)
+#define TIM_DMABASE_CCR3 (0x0000000F)
+#define TIM_DMABASE_CCR4 (0x00000010)
+#define TIM_DMABASE_BDTR (0x00000011)
+#define TIM_DMABASE_DCR (0x00000012)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
+ * @{
+ */
+#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
+#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
+#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
+#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
+#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
+#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
+#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
+#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
+#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
+#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
+#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
+#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
+#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
+#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
+#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
+#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
+#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
+#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
+ * @{
+ */
+#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
+ * @{
+ */
+#define TIM_CCx_ENABLE ((uint32_t)0x0001)
+#define TIM_CCx_DISABLE ((uint32_t)0x0000)
+#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
+#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private Constants -----------------------------------------------------------*/
+/** @defgroup TIM_Private_Constants TIM Private Constants
+ * @{
+ */
+
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
+#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
+
+/**
+ * @}
+ */
+
+/* Private Macros -----------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+ * @{
+ */
+
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
+ ((MODE) == TIM_COUNTERMODE_DOWN) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
+
+#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
+ ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
+ ((DIV) == TIM_CLOCKDIVISION_DIV4))
+
+#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
+ ((MODE) == TIM_OCMODE_PWM2))
+
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
+ ((MODE) == TIM_OCMODE_ACTIVE) || \
+ ((MODE) == TIM_OCMODE_INACTIVE) || \
+ ((MODE) == TIM_OCMODE_TOGGLE) || \
+ ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
+ ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
+
+#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
+ ((STATE) == TIM_OCFAST_ENABLE))
+
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
+ ((POLARITY) == TIM_OCPOLARITY_LOW))
+
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
+ ((POLARITY) == TIM_OCNPOLARITY_LOW))
+
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
+ ((STATE) == TIM_OCIDLESTATE_RESET))
+
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
+ ((STATE) == TIM_OCNIDLESTATE_RESET))
+
+#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))
+
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
+ ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
+ ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
+
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
+ ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
+ ((SELECTION) == TIM_ICSELECTION_TRC))
+
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \
+ ((PRESCALER) == TIM_ICPSC_DIV8))
+
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
+ ((MODE) == TIM_OPMODE_REPETITIVE))
+
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
+ ((MODE) == TIM_ENCODERMODE_TI2) || \
+ ((MODE) == TIM_ENCODERMODE_TI12))
+
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
+
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
+
+#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
+
+#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
+
+#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
+
+#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
+
+#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \
+ ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
+ ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))
+
+#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+ ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+
+#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
+
+#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
+ ((STATE) == TIM_OSSR_DISABLE))
+
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
+ ((STATE) == TIM_OSSI_DISABLE))
+
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
+ ((LEVEL) == TIM_LOCKLEVEL_1) || \
+ ((LEVEL) == TIM_LOCKLEVEL_2) || \
+ ((LEVEL) == TIM_LOCKLEVEL_3))
+
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
+ ((STATE) == TIM_BREAK_DISABLE))
+
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
+ ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+ ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
+
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
+ ((SOURCE) == TIM_TRGO_ENABLE) || \
+ ((SOURCE) == TIM_TRGO_UPDATE) || \
+ ((SOURCE) == TIM_TRGO_OC1) || \
+ ((SOURCE) == TIM_TRGO_OC1REF) || \
+ ((SOURCE) == TIM_TRGO_OC2REF) || \
+ ((SOURCE) == TIM_TRGO_OC3REF) || \
+ ((SOURCE) == TIM_TRGO_OC4REF))
+
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
+ ((MODE) == TIM_SLAVEMODE_GATED) || \
+ ((MODE) == TIM_SLAVEMODE_RESET) || \
+ ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
+ ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
+
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
+ ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
+
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_TI1F_ED) || \
+ ((SELECTION) == TIM_TS_TI1FP1) || \
+ ((SELECTION) == TIM_TS_TI2FP2) || \
+ ((SELECTION) == TIM_TS_ETRF))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_NONE))
+
+#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
+
+#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
+
+#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
+
+#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
+ ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
+
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
+ ((BASE) == TIM_DMABASE_CR2) || \
+ ((BASE) == TIM_DMABASE_SMCR) || \
+ ((BASE) == TIM_DMABASE_DIER) || \
+ ((BASE) == TIM_DMABASE_SR) || \
+ ((BASE) == TIM_DMABASE_EGR) || \
+ ((BASE) == TIM_DMABASE_CCMR1) || \
+ ((BASE) == TIM_DMABASE_CCMR2) || \
+ ((BASE) == TIM_DMABASE_CCER) || \
+ ((BASE) == TIM_DMABASE_CNT) || \
+ ((BASE) == TIM_DMABASE_PSC) || \
+ ((BASE) == TIM_DMABASE_ARR) || \
+ ((BASE) == TIM_DMABASE_RCR) || \
+ ((BASE) == TIM_DMABASE_CCR1) || \
+ ((BASE) == TIM_DMABASE_CCR2) || \
+ ((BASE) == TIM_DMABASE_CCR3) || \
+ ((BASE) == TIM_DMABASE_CCR4) || \
+ ((BASE) == TIM_DMABASE_BDTR) || \
+ ((BASE) == TIM_DMABASE_DCR))
+
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
+
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+
+/** @brief Set TIM IC prescaler
+ * @param __HANDLE__: TIM handle
+ * @param __CHANNEL__: specifies TIM Channel
+ * @param __ICPSC__: specifies the prescaler value.
+ * @retval None
+ */
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
+
+/** @brief Reset TIM IC prescaler
+ * @param __HANDLE__: TIM handle
+ * @param __CHANNEL__: specifies TIM Channel
+ * @retval None
+ */
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
+ ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
+
+
+/** @brief Set TIM IC polarity
+ * @param __HANDLE__: TIM handle
+ * @param __CHANNEL__: specifies TIM Channel
+ * @param __POLARITY__: specifies TIM Channel Polarity
+ * @retval None
+ */
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
+ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
+
+/** @brief Reset TIM IC polarity
+ * @param __HANDLE__: TIM handle
+ * @param __CHANNEL__: specifies TIM Channel
+ * @retval None
+ */
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+ ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
+
+/**
+ * @}
+ */
+
+/* Private Functions --------------------------------------------------------*/
+/** @addtogroup TIM_Private_Functions
+ * @{
+ */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMAError(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup TIM_Exported_Macros TIM Exported Macros
+ * @{
+ */
+
+/** @brief Reset TIM handle state
+ * @param __HANDLE__: TIM handle.
+ * @retval None
+ */
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
+
+/**
+ * @brief Enable the TIM peripheral.
+ * @param __HANDLE__: TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
+
+/**
+ * @brief Enable the TIM main Output.
+ * @param __HANDLE__: TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
+
+/**
+ * @brief Disable the TIM peripheral.
+ * @param __HANDLE__: TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE(__HANDLE__) \
+ do { \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
+ { \
+ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+ } \
+ } \
+ } while(0)
+/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
+/**
+ * @brief Disable the TIM main Output.
+ * @param __HANDLE__: TIM handle
+ * @retval None
+ * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
+ */
+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
+ do { \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
+ { \
+ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+ } \
+ } \
+ } while(0)
+
+/**
+ * @brief Enables the specified TIM interrupt.
+ * @param __HANDLE__: specifies the TIM Handle.
+ * @param __INTERRUPT__: specifies the TIM interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified TIM interrupt.
+ * @param __HANDLE__: specifies the TIM Handle.
+ * @param __INTERRUPT__: specifies the TIM interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
+
+/**
+ * @brief Enables the specified DMA request.
+ * @param __HANDLE__: specifies the TIM Handle.
+ * @param __DMA__: specifies the TIM DMA request to enable.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: Update DMA request
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
+ * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
+ * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
+ * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
+ * @arg TIM_DMA_COM: Commutation DMA request
+ * @arg TIM_DMA_TRIGGER: Trigger DMA request
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
+
+/**
+ * @brief Disables the specified DMA request.
+ * @param __HANDLE__: specifies the TIM Handle.
+ * @param __DMA__: specifies the TIM DMA request to disable.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: Update DMA request
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
+ * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
+ * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
+ * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
+ * @arg TIM_DMA_COM: Commutation DMA request
+ * @arg TIM_DMA_TRIGGER: Trigger DMA request
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+
+/**
+ * @brief Checks whether the specified TIM interrupt flag is set or not.
+ * @param __HANDLE__: specifies the TIM Handle.
+ * @param __FLAG__: specifies the TIM interrupt flag to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_UPDATE: Update interrupt flag
+ * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+ * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+ * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+ * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+ * @arg TIM_FLAG_COM: Commutation interrupt flag
+ * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+ * @arg TIM_FLAG_BREAK: Break interrupt flag
+ * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+ * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+ * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+ * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clears the specified TIM interrupt flag.
+ * @param __HANDLE__: specifies the TIM Handle.
+ * @param __FLAG__: specifies the TIM interrupt flag to clear.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_UPDATE: Update interrupt flag
+ * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+ * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+ * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+ * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+ * @arg TIM_FLAG_COM: Commutation interrupt flag
+ * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+ * @arg TIM_FLAG_BREAK: Break interrupt flag
+ * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+ * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+ * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+ * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/**
+ * @brief Checks whether the specified TIM interrupt has occurred or not.
+ * @param __HANDLE__: TIM handle
+ * @param __INTERRUPT__: specifies the TIM interrupt source to check.
+ * @retval The state of TIM_IT (SET or RESET).
+ */
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief Clear the TIM interrupt pending bits
+ * @param __HANDLE__: TIM handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * @retval None
+ */
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
+
+/**
+ * @brief Indicates whether or not the TIM Counter is used as downcounter
+ * @param __HANDLE__: TIM handle.
+ * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
+ * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder
+mode.
+ */
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
+
+/**
+ * @brief Sets the TIM active prescaler register value on update event.
+ * @param __HANDLE__: TIM handle.
+ * @param __PRESC__: specifies the active prescaler register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
+
+/**
+ * @brief Sets the TIM Capture Compare Register value on runtime without
+ * calling another time ConfigChannel function.
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__ : TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __COMPARE__: specifies the Capture Compare register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
+(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
+
+/**
+ * @brief Gets the TIM Capture Compare Register value on runtime
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__ : TIM Channel associated with the capture compare register
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get capture/compare 1 register value
+ * @arg TIM_CHANNEL_2: get capture/compare 2 register value
+ * @arg TIM_CHANNEL_3: get capture/compare 3 register value
+ * @arg TIM_CHANNEL_4: get capture/compare 4 register value
+ * @retval None
+ */
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+ (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
+
+/**
+ * @brief Sets the TIM Counter Register value on runtime.
+ * @param __HANDLE__: TIM handle.
+ * @param __COUNTER__: specifies the Counter register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+
+/**
+ * @brief Gets the TIM Counter Register value on runtime.
+ * @param __HANDLE__: TIM handle.
+ * @retval None
+ */
+#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
+ ((__HANDLE__)->Instance->CNT)
+
+/**
+ * @brief Sets the TIM Autoreload Register value on runtime without calling
+ * another time any Init function.
+ * @param __HANDLE__: TIM handle.
+ * @param __AUTORELOAD__: specifies the Counter register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
+ do{ \
+ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
+ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
+ } while(0)
+
+/**
+ * @brief Gets the TIM Autoreload Register value on runtime
+ * @param __HANDLE__: TIM handle.
+ * @retval None
+ */
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
+ ((__HANDLE__)->Instance->ARR)
+
+/**
+ * @brief Sets the TIM Clock Division value on runtime without calling
+ * another time any Init function.
+ * @param __HANDLE__: TIM handle.
+ * @param __CKD__: specifies the clock division value.
+ * This parameter can be one of the following value:
+ * @arg TIM_CLOCKDIVISION_DIV1
+ * @arg TIM_CLOCKDIVISION_DIV2
+ * @arg TIM_CLOCKDIVISION_DIV4
+ * @retval None
+ */
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
+ do{ \
+ (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
+ (__HANDLE__)->Instance->CR1 |= (__CKD__); \
+ (__HANDLE__)->Init.ClockDivision = (__CKD__); \
+ } while(0)
+
+/**
+ * @brief Gets the TIM Clock Division value on runtime
+ * @param __HANDLE__: TIM handle.
+ * @retval None
+ */
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+
+/**
+ * @brief Sets the TIM Input Capture prescaler on runtime without calling
+ * another time HAL_TIM_IC_ConfigChannel() function.
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__ : TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
+ do{ \
+ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+ } while(0)
+
+/**
+ * @brief Gets the TIM Input Capture prescaler on runtime
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__: TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
+ * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
+ * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
+ * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
+ * @retval None
+ */
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
+ (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
+
+/**
+ * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
+ * @param __HANDLE__: TIM handle.
+ * @note When the USR bit of the TIMx_CR1 register is set, only counter
+ * overflow/underflow generates an update interrupt or DMA request (if
+ * enabled)
+ * @retval None
+ */
+#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
+
+/**
+ * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
+ * @param __HANDLE__: TIM handle.
+ * @note When the USR bit of the TIMx_CR1 register is reset, any of the
+ * following events generate an update interrupt or DMA request (if
+ * enabled):
+ * (+) Counter overflow/underflow
+ * (+) Setting the UG bit
+ * (+) Update generation through the slave mode controller
+ * @retval None
+ */
+#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
+
+/**
+ * @brief Sets the TIM Capture x input polarity on runtime.
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__: TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __POLARITY__: Polarity for TIx source
+ * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
+ * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
+ * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
+ * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
+ * @retval None
+ */
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+ do{ \
+ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+ }while(0)
+
+/**
+ * @}
+ */
+
+/* Include TIM HAL Extension module */
+#include "stm32f1xx_hal_tim_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group1
+ * @{
+ */
+/* Time Base functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group2
+ * @{
+ */
+/* Timer Output Compare functions **********************************************/
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group3
+ * @{
+ */
+/* Timer PWM functions *********************************************************/
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group4
+ * @{
+ */
+/* Timer Input Capture functions ***********************************************/
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group5
+ * @{
+ */
+/* Timer One Pulse functions ***************************************************/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group6
+ * @{
+ */
+/* Timer Encoder functions *****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group7
+ * @{
+ */
+/* Interrupt Handler functions **********************************************/
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group8
+ * @{
+ */
+/* Control functions *********************************************************/
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
+ uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
+ uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group9
+ * @{
+ */
+/* Callback in non blocking modes (Interrupt and DMA) *************************/
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group10
+ * @{
+ */
+/* Peripheral State functions **************************************************/
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_TIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,312 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_tim_ex.h
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief Header file of TIM HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_TIM_EX_H
+#define __STM32F1xx_HAL_TIM_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup TIMEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Types TIMEx Exported Types
+ * @{
+ */
+
+
+/**
+ * @brief TIM Hall sensor Configuration Structure definition
+ */
+
+typedef struct
+{
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+} TIM_HallSensor_InitTypeDef;
+
+
+#if defined (STM32F100xB) || defined (STM32F100xE) || \
+ defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
+ defined (STM32F105xC) || defined (STM32F107xC)
+
+/**
+ * @brief TIM Break and Dead time configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t OffStateRunMode; /*!< TIM off state in run mode
+ This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
+ This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+ uint32_t LockLevel; /*!< TIM Lock level
+ This parameter can be a value of @ref TIM_Lock_level */
+ uint32_t DeadTime; /*!< TIM dead Time
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+ uint32_t BreakState; /*!< TIM Break State
+ This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+ uint32_t BreakPolarity; /*!< TIM Break input polarity
+ This parameter can be a value of @ref TIM_Break_Polarity */
+ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BreakDeadTimeConfigTypeDef;
+
+#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
+ /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
+ /* defined(STM32F105xC) || defined(STM32F107xC) */
+
+/**
+ * @brief TIM Master configuration Structure definition
+ */
+typedef struct {
+ uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
+ This parameter can be a value of @ref TIM_Master_Mode_Selection */
+ uint32_t MasterSlaveMode; /*!< Master/slave mode selection
+ This parameter can be a value of @ref TIM_Master_Slave_Mode */
+}TIM_MasterConfigTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+#if defined (STM32F100xB) || defined (STM32F100xE) || \
+ defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
+ defined (STM32F105xC) || defined (STM32F107xC)
+/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
+ * @{
+ */
+
+/** @defgroup TIMEx_Clock_Filter TIMEx Clock Filter
+ * @{
+ */
+#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFF) /*!< BreakDead Time */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
+ /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
+ /* defined(STM32F105xC) || defined(STM32F107xC) */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIMEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group1
+ * @{
+ */
+/* Timer Hall Sensor functions **********************************************/
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
+
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
+
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+#if defined (STM32F100xB) || defined (STM32F100xE) || \
+ defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
+ defined (STM32F105xC) || defined (STM32F107xC)
+
+/** @addtogroup TIMEx_Exported_Functions_Group2
+ * @{
+ */
+/* Timer Complementary Output Compare functions *****************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group3
+ * @{
+ */
+/* Timer Complementary PWM functions ****************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group4
+ * @{
+ */
+/* Timer Complementary One Pulse functions **********************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+ * @}
+ */
+#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
+ /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
+ /* defined(STM32F105xC) || defined(STM32F107xC) */
+
+/** @addtogroup TIMEx_Exported_Functions_Group5
+ * @{
+ */
+/* Extended Control functions ************************************************/
+#if defined (STM32F100xB) || defined (STM32F100xE) || \
+ defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
+ defined (STM32F105xC) || defined (STM32F107xC)
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
+ /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
+ /* defined(STM32F105xC) || defined(STM32F107xC) */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group6
+ * @{
+ */
+/* Extension Callback *********************************************************/
+void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+#if defined (STM32F100xB) || defined (STM32F100xE) || \
+ defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
+ defined (STM32F105xC) || defined (STM32F107xC)
+/** @addtogroup TIMEx_Exported_Functions_Group7
+ * @{
+ */
+/* Extension Peripheral State functions **************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
+ /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
+ /* defined(STM32F105xC) || defined(STM32F107xC) */
+
+/**
+ * @}
+ */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
+* @{
+*/
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+/**
+* @}
+*/
+/* End of private functions --------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F1xx_HAL_TIM_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,751 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_uart.h
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief Header file of UART HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_UART_H
+#define __STM32F1xx_HAL_UART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup UART
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UART_Exported_Types UART Exported Types
+ * @{
+ */
+
+
+/**
+ * @brief UART Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((PCLKx) / (16 * (huart->Init.BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref UART_Word_Length */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref UART_Stop_Bits */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref UART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref UART_Mode */
+
+ uint32_t HwFlowCtl; /*!< Specifies wether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref UART_Hardware_Flow_Control */
+
+ uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
+ This parameter can be a value of @ref UART_Over_Sampling. This feature is not available
+ on STM32F1xx family, so OverSampling parameter should always be set to 16. */
+}UART_InitTypeDef;
+
+/**
+ * @brief HAL UART State structures definition
+ */
+typedef enum
+{
+ HAL_UART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
+ HAL_UART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_UART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_UART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_UART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_UART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
+ HAL_UART_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_UART_STATE_ERROR = 0x04 /*!< Error */
+}HAL_UART_StateTypeDef;
+
+
+/**
+ * @brief UART handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /*!< UART registers base address */
+
+ UART_InitTypeDef Init; /*!< UART communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< UART Tx Transfer size */
+
+ uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< UART Rx Transfer size */
+
+ uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
+
+ DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_UART_StateTypeDef State; /*!< UART communication state */
+
+ __IO uint32_t ErrorCode; /*!< UART Error code */
+
+}UART_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UART_Exported_Constants UART Exported constants
+ * @{
+ */
+
+/** @defgroup UART_Error_Codes UART Error Codes
+ * @{
+ */
+
+#define HAL_UART_ERROR_NONE ((uint32_t)0x00) /*!< No error */
+#define HAL_UART_ERROR_PE ((uint32_t)0x01) /*!< Parity error */
+#define HAL_UART_ERROR_NE ((uint32_t)0x02) /*!< Noise error */
+#define HAL_UART_ERROR_FE ((uint32_t)0x04) /*!< frame error */
+#define HAL_UART_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */
+#define HAL_UART_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */
+
+/**
+ * @}
+ */
+
+
+
+
+/** @defgroup UART_Word_Length UART Word Length
+ * @{
+ */
+#define UART_WORDLENGTH_8B ((uint32_t)0x00000000)
+#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
+/**
+ * @}
+ */
+
+/** @defgroup UART_Stop_Bits UART Number of Stop Bits
+ * @{
+ */
+#define UART_STOPBITS_1 ((uint32_t)0x00000000)
+#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
+/**
+ * @}
+ */
+
+/** @defgroup UART_Parity UART Parity
+ * @{
+ */
+#define HAL_UART_PARITY_NONE ((uint32_t)0x00000000)
+#define HAL_UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
+#define HAL_UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
+ * @{
+ */
+#define UART_HWCONTROL_NONE ((uint32_t)0x00000000)
+#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
+#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
+#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Mode UART Transfer Mode
+ * @{
+ */
+#define UART_MODE_RX ((uint32_t)USART_CR1_RE)
+#define UART_MODE_TX ((uint32_t)USART_CR1_TE)
+#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+
+/**
+ * @}
+ */
+
+ /** @defgroup UART_State UART State
+ * @{
+ */
+#define UART_STATE_DISABLE ((uint32_t)0x00000000)
+#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
+/**
+ * @}
+ */
+
+/** @defgroup UART_Over_Sampling UART Over Sampling
+ * @{
+ */
+#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length
+ * @{
+ */
+#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000)
+#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)
+/**
+ * @}
+ */
+
+/** @defgroup UART_WakeUp_functions UART Wakeup Functions
+ * @{
+ */
+#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000)
+#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)
+/**
+ * @}
+ */
+
+/** @defgroup UART_Flags UART FLags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the SR register
+ * @{
+ */
+#define UART_FLAG_CTS ((uint32_t)USART_SR_CTS)
+#define UART_FLAG_LBD ((uint32_t)USART_SR_LBD)
+#define UART_FLAG_TXE ((uint32_t)USART_SR_TXE)
+#define UART_FLAG_TC ((uint32_t)USART_SR_TC)
+#define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
+#define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
+#define UART_FLAG_ORE ((uint32_t)USART_SR_ORE)
+#define UART_FLAG_NE ((uint32_t)USART_SR_NE)
+#define UART_FLAG_FE ((uint32_t)USART_SR_FE)
+#define UART_FLAG_PE ((uint32_t)USART_SR_PE)
+/**
+ * @}
+ */
+
+/** @defgroup UART_Interrupt_definition UART Interrupt Definitions
+ * Elements values convention: 0xY000XXXX
+ * - XXXX : Interrupt mask (16 bits) in the Y register
+ * - Y : Interrupt source register (2bits)
+ * - 0001: CR1 register
+ * - 0010: CR2 register
+ * - 0011: CR3 register
+ *
+ * @{
+ */
+
+#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
+#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
+#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
+#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
+#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
+
+#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
+
+#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
+#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28 | USART_CR3_EIE))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup UART_Exported_Macros UART Exported Macros
+ * @{
+ */
+
+
+/** @brief Reset UART handle state
+ * @param __HANDLE__: specifies the UART Handle.
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @retval None
+ */
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET)
+
+/** @brief Flush the UART DR register
+ * @param __HANDLE__: specifies the UART Handle.
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ */
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
+
+/** @brief Check whether the specified UART flag is set or not.
+ * @param __HANDLE__: specifies the UART Handle.
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
+ * @arg UART_FLAG_LBD: LIN Break detection flag
+ * @arg UART_FLAG_TXE: Transmit data register empty flag
+ * @arg UART_FLAG_TC: Transmission Complete flag
+ * @arg UART_FLAG_RXNE: Receive data register not empty flag
+ * @arg UART_FLAG_IDLE: Idle Line detection flag
+ * @arg UART_FLAG_ORE: OverRun Error flag
+ * @arg UART_FLAG_NE: Noise Error flag
+ * @arg UART_FLAG_FE: Framing Error flag
+ * @arg UART_FLAG_PE: Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the specified UART pending flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
+ * @arg UART_FLAG_LBD: LIN Break detection flag.
+ * @arg UART_FLAG_TC: Transmission Complete flag.
+ * @arg UART_FLAG_RXNE: Receive data register not empty flag.
+ *
+ * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) flags are cleared by software
+ * sequence: a read operation to USART_SR register followed by a read
+ * operation to USART_DR register.
+ * @note RXNE flag can be also cleared by a read to the USART_DR register.
+ * @note TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register followed by a write operation to USART_DR register.
+ * @note TXE flag is cleared only by a write to the USART_DR register.
+ *
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/** @brief Clear the UART PE pending flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \
+do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ UNUSED(tmpreg); \
+}while(0)
+
+
+
+/** @brief Clear the UART FE pending flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the UART NE pending flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the UART ORE pending flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the UART IDLE pending flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Enable the specified UART interrupt.
+ * @param __HANDLE__: specifies the UART Handle.
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @param __INTERRUPT__: specifies the UART interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg UART_IT_CTS: CTS change interrupt
+ * @arg UART_IT_LBD: LIN Break detection interrupt
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg UART_IT_TC: Transmission complete interrupt
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg UART_IT_IDLE: Idle line detection interrupt
+ * @arg UART_IT_PE: Parity Error interrupt
+ * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
+
+
+/** @brief Disable the specified UART interrupt.
+ * @param __HANDLE__: specifies the UART Handle.
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @param __INTERRUPT__: specifies the UART interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg UART_IT_CTS: CTS change interrupt
+ * @arg UART_IT_LBD: LIN Break detection interrupt
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg UART_IT_TC: Transmission complete interrupt
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg UART_IT_IDLE: Idle line detection interrupt
+ * @arg UART_IT_PE: Parity Error interrupt
+ * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
+
+/** @brief Check whether the specified UART interrupt has occurred or not.
+ * @param __HANDLE__: specifies the UART Handle.
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @param __IT__: specifies the UART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
+ * @arg UART_IT_LBD: LIN Break detection interrupt
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg UART_IT_TC: Transmission complete interrupt
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg UART_IT_IDLE: Idle line detection interrupt
+ * @arg UART_IT_ERR: Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == UART_CR2_REG_INDEX)? \
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
+
+/** @brief Enable CTS flow control
+ * This macro allows to enable CTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be any USARTx (supporting the HW Flow control feature).
+ * It is used to select the USART peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
+ } while(0)
+
+/** @brief Disable CTS flow control
+ * This macro allows to disable CTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be any USARTx (supporting the HW Flow control feature).
+ * It is used to select the USART peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
+ do{ \
+ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
+ } while(0)
+
+/** @brief Enable RTS flow control
+ * This macro allows to enable RTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be any USARTx (supporting the HW Flow control feature).
+ * It is used to select the USART peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
+ } while(0)
+
+/** @brief Disable RTS flow control
+ * This macro allows to disable RTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be any USARTx (supporting the HW Flow control feature).
+ * It is used to select the USART peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
+ do{ \
+ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
+ } while(0)
+
+
+/** @brief Enable UART
+ * @param __HANDLE__: specifies the UART Handle.
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @retval None
+ */
+#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable UART
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @retval None
+ */
+#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/**
+ * @}
+ */
+
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup UART_Private_Macros UART Private Macros
+ * @{
+ */
+
+#define UART_CR1_REG_INDEX 1
+#define UART_CR2_REG_INDEX 2
+#define UART_CR3_REG_INDEX 3
+
+#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
+#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100)
+#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+/* UART BRR = mantissa + overflow + fraction
+ = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0F) */
+#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4) + \
+ (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0)) + \
+ (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0F))
+#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
+ ((LENGTH) == UART_WORDLENGTH_9B))
+#define IS_UART_LIN_WORD_LENGTH(LENGTH) ((LENGTH) == UART_WORDLENGTH_8B)
+
+#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
+ ((STOPBITS) == UART_STOPBITS_2))
+
+#define IS_UART_PARITY(PARITY) (((PARITY) == HAL_UART_PARITY_NONE) || \
+ ((PARITY) == HAL_UART_PARITY_EVEN) || \
+ ((PARITY) == HAL_UART_PARITY_ODD))
+
+#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
+ (((CONTROL) == UART_HWCONTROL_NONE) || \
+ ((CONTROL) == UART_HWCONTROL_RTS) || \
+ ((CONTROL) == UART_HWCONTROL_CTS) || \
+ ((CONTROL) == UART_HWCONTROL_RTS_CTS))
+
+#define IS_UART_MODE(MODE) ((((MODE) & (~((uint32_t)UART_MODE_TX_RX))) == 0x00) && \
+ ((MODE) != (uint32_t)0x00000000))
+
+#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
+ ((STATE) == UART_STATE_ENABLE))
+
+#define IS_UART_OVERSAMPLING(SAMPLING) ((SAMPLING) == UART_OVERSAMPLING_16)
+#define IS_UART_LIN_OVERSAMPLING(SAMPLING) ((SAMPLING) == UART_OVERSAMPLING_16)
+
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
+ ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
+
+#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
+ ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
+
+
+/** Check UART Baud rate
+ * __BAUDRATE__: Baudrate specified by the user
+ * The maximum Baud Rate is derived from the maximum clock on APB (i.e. 72 MHz)
+ * divided by the smallest oversampling used on the USART (i.e. 16)
+ * Retrun : TRUE or FALSE
+ */
+#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001)
+
+/** Check UART Node Address
+ * __ADDRESS__: UART Node address specified by the user
+ * UART Node address is used in Multi processor communication for wakeup
+ * with address mark detection.
+ * This parameter must be a number between Min_Data = 0 and Max_Data = 15
+ * Return : TRUE or FALSE
+ */
+#define IS_UART_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
+
+/** UART interruptions flag mask
+ */
+#define UART_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
+ USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup UART_Exported_Functions UART Exported Functions
+ * @{
+ */
+
+/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
+HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
+void HAL_UART_MspInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Errors functions
+ * @{
+ */
+
+/* Peripheral State and Errors functions **************************************************/
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_UART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_usart.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_usart.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,617 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_usart.h
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief Header file of USART HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_USART_H
+#define __STM32F1xx_HAL_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup USART
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup USART_Exported_Types USART Exported Types
+ * @{
+ */
+
+
+/**
+ * @brief USART Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((PCLKx) / (16 * (husart->Init.BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref USART_Word_Length */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_Stop_Bits */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref USART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref USART_Mode */
+
+ uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref USART_Clock_Polarity */
+
+ uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref USART_Clock_Phase */
+
+ uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref USART_Last_Bit */
+}USART_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_USART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
+ HAL_USART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_USART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_USART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_USART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_USART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission Reception process is ongoing */
+ HAL_USART_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_USART_STATE_ERROR = 0x04 /*!< Error */
+}HAL_USART_StateTypeDef;
+
+
+/**
+ * @brief USART handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /*!< USART registers base address */
+
+ USART_InitTypeDef Init; /*!< Usart communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to Usart Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< Usart Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /*!< Usart Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to Usart Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< Usart Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /*!< Usart Rx Transfer Counter */
+
+ DMA_HandleTypeDef *hdmatx; /*!< Usart Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< Usart Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_USART_StateTypeDef State; /*!< Usart communication state */
+
+ __IO uint32_t ErrorCode; /*!< USART Error code */
+
+}USART_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_Exported_Constants USART Exported constants
+ * @{
+ */
+
+/** @defgroup USART_Error_Codes USART Error Codes
+ * @{
+ */
+#define HAL_USART_ERROR_NONE ((uint32_t)0x00) /*!< No error */
+#define HAL_USART_ERROR_PE ((uint32_t)0x01) /*!< Parity error */
+#define HAL_USART_ERROR_NE ((uint32_t)0x02) /*!< Noise error */
+#define HAL_USART_ERROR_FE ((uint32_t)0x04) /*!< frame error */
+#define HAL_USART_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */
+#define HAL_USART_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Word_Length USART Word Length
+ * @{
+ */
+#define USART_WORDLENGTH_8B ((uint32_t)0x00000000)
+#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
+/**
+ * @}
+ */
+
+/** @defgroup USART_Stop_Bits USART Number of Stop Bits
+ * @{
+ */
+#define USART_STOPBITS_1 ((uint32_t)0x00000000)
+#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
+#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
+#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Parity USART Parity
+ * @{
+ */
+#define USART_PARITY_NONE ((uint32_t)0x00000000)
+#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
+#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Mode USART Mode
+ * @{
+ */
+#define USART_MODE_RX ((uint32_t)USART_CR1_RE)
+#define USART_MODE_TX ((uint32_t)USART_CR1_TE)
+#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock USART Clock
+ * @{
+ */
+#define USART_CLOCK_DISABLE ((uint32_t)0x00000000)
+#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Polarity USART Clock Polarity
+ * @{
+ */
+#define USART_POLARITY_LOW ((uint32_t)0x00000000)
+#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Phase USART Clock Phase
+ * @{
+ */
+#define USART_PHASE_1EDGE ((uint32_t)0x00000000)
+#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
+/**
+ * @}
+ */
+
+/** @defgroup USART_Last_Bit USART Last Bit
+ * @{
+ */
+#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000)
+#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
+/**
+ * @}
+ */
+
+/** @defgroup USART_NACK_State USART NACK State
+ * @{
+ */
+#define USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
+#define USART_NACK_DISABLE ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup USART_Flags USART Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the SR register
+ * @{
+ */
+
+#define USART_FLAG_CTS ((uint32_t)USART_SR_CTS)
+#define USART_FLAG_LBD ((uint32_t)USART_SR_LBD)
+#define USART_FLAG_TXE ((uint32_t)USART_SR_TXE)
+#define USART_FLAG_TC ((uint32_t)USART_SR_TC)
+#define USART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
+#define USART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
+#define USART_FLAG_ORE ((uint32_t)USART_SR_ORE)
+#define USART_FLAG_NE ((uint32_t)USART_SR_NE)
+#define USART_FLAG_FE ((uint32_t)USART_SR_FE)
+#define USART_FLAG_PE ((uint32_t)USART_SR_PE)
+/**
+ * @}
+ */
+
+/** @defgroup USART_Interrupt_definition USART Interrupts Definition
+ * Elements values convention: 0xY000XXXX
+ * - XXXX : Interrupt mask (16 bits) in the Y register
+ * - Y : Interrupt source register (4bits)
+ * - 0001: CR1 register
+ * - 0010: CR2 register
+ * - 0011: CR3 register
+ *
+ * @{
+ */
+
+#define USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
+#define USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
+#define USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
+#define USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
+#define USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
+
+#define USART_IT_LBD ((uint32_t)(USART_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
+
+#define USART_IT_CTS ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
+#define USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_EIE))
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USART_Exported_Macros USART Exported Macros
+ * @{
+ */
+
+
+/** @brief Reset USART handle state
+ * @param __HANDLE__: specifies the USART Handle.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
+
+/** @brief Check whether the specified USART flag is set or not.
+ * @param __HANDLE__: specifies the USART Handle.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg USART_FLAG_TXE: Transmit data register empty flag
+ * @arg USART_FLAG_TC: Transmission Complete flag
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag
+ * @arg USART_FLAG_IDLE: Idle Line detection flag
+ * @arg USART_FLAG_ORE: OverRun Error flag
+ * @arg USART_FLAG_NE: Noise Error flag
+ * @arg USART_FLAG_FE: Framing Error flag
+ * @arg USART_FLAG_PE: Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+
+#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the specified USART pending flags.
+ * @param __HANDLE__: specifies the USART Handle.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg USART_FLAG_TC: Transmission Complete flag.
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag.
+ *
+ * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) flags are cleared by software
+ * sequence: a read operation to USART_SR register followed by a read
+ * operation to USART_DR register.
+ * @note RXNE flag can be also cleared by a read to the USART_DR register.
+ * @note TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register followed by a write operation to USART_DR register.
+ * @note TXE flag is cleared only by a write to the USART_DR register.
+ *
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/** @brief Clear the USART PE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) \
+do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ UNUSED(tmpreg); \
+}while(0)
+
+
+/** @brief Clear the USART FE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the USART NE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the USART ORE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Clear the USART IDLE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief Enable the specified Usart interrupts.
+ * @param __HANDLE__: specifies the USART Handle.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @param __INTERRUPT__: specifies the USART interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg USART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_PE: Parity Error interrupt
+ * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
+
+
+/** @brief Disable the specified Usart interrupts.
+ * @param __HANDLE__: specifies the USART Handle.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @param __INTERRUPT__: specifies the USART interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg USART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_PE: Parity Error interrupt
+ * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
+
+
+
+/** @brief Check whether the specified Usart interrupt has occurred or not.
+ * @param __HANDLE__: specifies the USART Handle.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @param __IT__: specifies the USART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg USART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_ERR: Error interrupt
+ * @arg USART_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == USART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == USART_CR2_REG_INDEX)? \
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
+
+/** @brief Enable USART
+ * @param __HANDLE__: specifies the USART Handle.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_USART_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE))
+
+/** @brief Disable USART
+ * @param __HANDLE__: specifies the USART Handle.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
+ */
+#define __HAL_USART_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE))
+
+
+/**
+ * @}
+ */
+
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup USART_Private_Macros USART Private Macros
+ * @{
+ */
+
+#define USART_CR1_REG_INDEX 1
+#define USART_CR2_REG_INDEX 2
+#define USART_CR3_REG_INDEX 3
+
+#define USART_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25)/(4*(__BAUD__)))
+#define USART_DIVMANT(__PCLK__, __BAUD__) (USART_DIV((__PCLK__), (__BAUD__))/100)
+#define USART_DIVFRAQ(__PCLK__, __BAUD__) (((USART_DIV((__PCLK__), (__BAUD__)) - (USART_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100)
+#define USART_BRR(__PCLK__, __BAUD__) ((USART_DIVMANT((__PCLK__), (__BAUD__)) << 4)|(USART_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0F))
+
+/** Check USART Baud rate
+ * __BAUDRATE__: Baudrate specified by the user
+ * The maximum Baud Rate is derived from the maximum clock on APB (i.e. 72 MHz)
+ * divided by the smallest oversampling used on the USART (i.e. 16)
+ * return : TRUE or FALSE
+ */
+#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001)
+
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
+ ((LENGTH) == USART_WORDLENGTH_9B))
+
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
+ ((STOPBITS) == USART_STOPBITS_0_5) || \
+ ((STOPBITS) == USART_STOPBITS_1_5) || \
+ ((STOPBITS) == USART_STOPBITS_2))
+
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
+ ((PARITY) == USART_PARITY_EVEN) || \
+ ((PARITY) == USART_PARITY_ODD))
+
+#define IS_USART_MODE(MODE) ((((MODE) & (~((uint32_t)USART_MODE_TX_RX))) == 0x00) && ((MODE) != (uint32_t)0x00000000))
+
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \
+ ((CLOCK) == USART_CLOCK_ENABLE))
+
+#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
+
+#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
+
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
+ ((LASTBIT) == USART_LASTBIT_ENABLE))
+
+#define IS_USART_NACK_STATE(NACK) (((NACK) == USART_NACK_ENABLE) || \
+ ((NACK) == USART_NACK_DISABLE))
+
+/** USART interruptions flag mask
+ *
+ */
+#define USART_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
+ USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup USART_Exported_Functions USART Exported Functions
+ * @{
+ */
+
+/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ******************************/
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
+void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
+
+/**
+ * @}
+ */
+
+/* Peripheral Control functions ***********************************************/
+
+/** @addtogroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @{
+ */
+
+/* Peripheral State and Error functions ***************************************/
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
+uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_USART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,526 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal.c
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief HAL module driver.
+ * This is the common part of the HAL initialization
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The common HAL driver contains a set of generic and common APIs that can be
+ used by the PPP peripheral drivers and the user to start using the HAL.
+ [..]
+ The HAL contains two APIs' categories:
+ (+) Common HAL APIs
+ (+) Services HAL APIs
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HAL HAL
+ * @brief HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup HAL_Private_Constants HAL Private Constants
+ * @{
+ */
+
+/**
+ * @brief STM32F1xx HAL Driver version number
+ */
+#define __STM32F1xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
+#define __STM32F1xx_HAL_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
+#define __STM32F1xx_HAL_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */
+#define __STM32F1xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24)\
+ |(__STM32F1xx_HAL_VERSION_SUB1 << 16)\
+ |(__STM32F1xx_HAL_VERSION_SUB2 << 8 )\
+ |(__STM32F1xx_HAL_VERSION_RC))
+
+#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/** @defgroup HAL_Private_Variables HAL Private Variables
+ * @{
+ */
+
+static __IO uint32_t uwTick;
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Functions HAL Exported Functions
+ * @{
+ */
+
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initializes the Flash interface, the NVIC allocation and initial clock
+ configuration. It initializes the source of time base also when timeout
+ is needed and the backup domain when enabled.
+ (+) de-Initializes common part of the HAL.
+ (+) Configure The time base source to have 1ms time base with a dedicated
+ Tick interrupt priority.
+ (++) Systick timer is used by default as source of time base, but user
+ can eventually implement his proper time base source (a general purpose
+ timer for example or other time source), keeping in mind that Time base
+ duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
+ handled in milliseconds basis.
+ (++) Time base configuration function (HAL_InitTick ()) is called automatically
+ at the beginning of the program after reset by HAL_Init() or at any time
+ when clock is configured, by HAL_RCC_ClockConfig().
+ (++) Source of time base is configured to generate interrupts at regular
+ time intervals. Care must be taken if HAL_Delay() is called from a
+ peripheral ISR process, the Tick interrupt line must have higher priority
+ (numerically lower) than the peripheral interrupt. Otherwise the caller
+ ISR process will be blocked.
+ (++) functions affecting time base configurations are declared as __Weak
+ to make override possible in case of other implementations in user file.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function configures the Flash prefetch,
+ * Configures time base source, NVIC and Low level hardware
+ * @note This function is called at the beginning of program after reset and before
+ * the clock configuration
+ * @note The time base configuration is based on MSI clock when exiting from Reset.
+ * Once done, time base tick start incrementing.
+ * In the default implementation,Systick is used as source of time base.
+ * The tick variable is incremented each 1ms in its ISR.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_Init(void)
+{
+ /* Configure Flash prefetch */
+#if (PREFETCH_ENABLE != 0)
+#if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \
+ defined(STM32F102x6) || defined(STM32F102xB) || \
+ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
+ defined(STM32F105xC) || defined(STM32F107xC)
+
+ /* Prefetch buffer is not available on value line devices */
+ __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif
+#endif /* PREFETCH_ENABLE */
+
+ /* Set Interrupt Group Priority */
+ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+ /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */
+ HAL_InitTick(TICK_INT_PRIORITY);
+
+ /* Init the low level hardware */
+ HAL_MspInit();
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief This function de-Initializes common part of the HAL and stops the source
+ * of time base.
+ * @note This function is optional.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DeInit(void)
+{
+ /* Reset of all peripherals */
+ __HAL_RCC_APB1_FORCE_RESET();
+ __HAL_RCC_APB1_RELEASE_RESET();
+
+ __HAL_RCC_APB2_FORCE_RESET();
+ __HAL_RCC_APB2_RELEASE_RESET();
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ __HAL_RCC_AHB_FORCE_RESET();
+ __HAL_RCC_AHB_RELEASE_RESET();
+#endif
+
+ /* De-Init the low level hardware */
+ HAL_MspDeInit();
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the MSP.
+ * @retval None
+ */
+__weak void HAL_MspInit(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the MSP.
+ * @retval None
+ */
+__weak void HAL_MspDeInit(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief This function configures the source of the time base.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * @note This function is called automatically at the beginning of program after
+ * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
+ * @note In the default implementation, SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals.
+ * Care must be taken if HAL_Delay() is called from a peripheral ISR process,
+ * The the SysTick interrupt must have higher priority (numerically lower)
+ * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+ * The function is declared as __Weak to be overwritten in case of other
+ * implementation in user file.
+ * @param TickPriority: Tick interrupt priority.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ /*Configure the SysTick to have interrupt in 1ms time basis*/
+ HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
+
+ /*Configure the SysTick IRQ priority */
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
+ * @brief HAL Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### HAL Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Provide a tick value in millisecond
+ (+) Provide a blocking delay in millisecond
+ (+) Suspend the time base source interrupt
+ (+) Resume the time base source interrupt
+ (+) Get the HAL API driver version
+ (+) Get the device identifier
+ (+) Get the device revision identifier
+ (+) Enable/Disable Debug module during Sleep mode
+ (+) Enable/Disable Debug module during STOP mode
+ (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function is called to increment a global variable "uwTick"
+ * used as application time base.
+ * @note In the default implementation, this variable is incremented each 1ms
+ * in Systick ISR.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_IncTick(void)
+{
+ uwTick++;
+}
+
+/**
+ * @brief Provides a tick value in millisecond.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval tick value
+ */
+__weak uint32_t HAL_GetTick(void)
+{
+ return uwTick;
+}
+
+/**
+ * @brief This function provides accurate delay (in milliseconds) based
+ * on variable incremented.
+ * @note In the default implementation , SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals where uwTick
+ * is incremented.
+ * @note ThiS function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @param Delay: specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+__weak void HAL_Delay(__IO uint32_t Delay)
+{
+ uint32_t tickstart = 0;
+ tickstart = HAL_GetTick();
+ while((HAL_GetTick() - tickstart) < Delay)
+ {
+ }
+}
+
+/**
+ * @brief Suspend Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+ * is called, the the SysTick interrupt will be disabled and so Tick increment
+ * is suspended.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_SuspendTick(void)
+{
+ /* Disable SysTick Interrupt */
+ CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+ * is called, the the SysTick interrupt will be enabled and so Tick increment
+ * is resumed.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_ResumeTick(void)
+{
+ /* Enable SysTick Interrupt */
+ SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief This method returns the HAL revision
+ * @retval version: 0xXYZR (8bits for each decimal, R for RC)
+ */
+uint32_t HAL_GetHalVersion(void)
+{
+ return __STM32F1xx_HAL_VERSION;
+}
+
+/**
+ * @brief Returns the device revision identifier.
+ * Note: On devices STM32F10xx8 and STM32F10xxB,
+ * STM32F101xC/D/E and STM32F103xC/D/E,
+ * STM32F101xF/G and STM32F103xF/G
+ * STM32F10xx4 and STM32F10xx6
+ * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+ * debug mode (not accessible by the user software in normal mode).
+ * Refer to errata sheet of these devices for more details.
+ * @retval Device revision identifier
+ */
+uint32_t HAL_GetREVID(void)
+{
+ return((DBGMCU->IDCODE) >> POSITION_VAL(DBGMCU_IDCODE_REV_ID));
+}
+
+/**
+ * @brief Returns the device identifier.
+ * Note: On devices STM32F10xx8 and STM32F10xxB,
+ * STM32F101xC/D/E and STM32F103xC/D/E,
+ * STM32F101xF/G and STM32F103xF/G
+ * STM32F10xx4 and STM32F10xx6
+ * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+ * debug mode (not accessible by the user software in normal mode).
+ * Refer to errata sheet of these devices for more details.
+ * @retval Device identifier
+ */
+uint32_t HAL_GetDEVID(void)
+{
+ return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
+}
+
+/**
+ * @brief Enable the Debug Module during SLEEP mode
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGSleepMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Disable the Debug Module during SLEEP mode
+ * Note: On devices STM32F10xx8 and STM32F10xxB,
+ * STM32F101xC/D/E and STM32F103xC/D/E,
+ * STM32F101xF/G and STM32F103xF/G
+ * STM32F10xx4 and STM32F10xx6
+ * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+ * debug mode (not accessible by the user software in normal mode).
+ * Refer to errata sheet of these devices for more details.
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGSleepMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Enable the Debug Module during STOP mode
+ * Note: On devices STM32F10xx8 and STM32F10xxB,
+ * STM32F101xC/D/E and STM32F103xC/D/E,
+ * STM32F101xF/G and STM32F103xF/G
+ * STM32F10xx4 and STM32F10xx6
+ * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+ * debug mode (not accessible by the user software in normal mode).
+ * Refer to errata sheet of these devices for more details.
+ * Note: On all STM32F1 devices:
+ * If the system tick timer interrupt is enabled during the Stop mode
+ * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup
+ * the system from Stop mode.
+ * Workaround: To debug the Stop mode, disable the system tick timer
+ * interrupt.
+ * Refer to errata sheet of these devices for more details.
+ * Note: On all STM32F1 devices:
+ * If the system tick timer interrupt is enabled during the Stop mode
+ * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup
+ * the system from Stop mode.
+ * Workaround: To debug the Stop mode, disable the system tick timer
+ * interrupt.
+ * Refer to errata sheet of these devices for more details.
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGStopMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Disable the Debug Module during STOP mode
+ * Note: On devices STM32F10xx8 and STM32F10xxB,
+ * STM32F101xC/D/E and STM32F103xC/D/E,
+ * STM32F101xF/G and STM32F103xF/G
+ * STM32F10xx4 and STM32F10xx6
+ * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+ * debug mode (not accessible by the user software in normal mode).
+ * Refer to errata sheet of these devices for more details.
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGStopMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Enable the Debug Module during STANDBY mode
+ * Note: On devices STM32F10xx8 and STM32F10xxB,
+ * STM32F101xC/D/E and STM32F103xC/D/E,
+ * STM32F101xF/G and STM32F103xF/G
+ * STM32F10xx4 and STM32F10xx6
+ * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+ * debug mode (not accessible by the user software in normal mode).
+ * Refer to errata sheet of these devices for more details.
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGStandbyMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Disable the Debug Module during STANDBY mode
+ * Note: On devices STM32F10xx8 and STM32F10xxB,
+ * STM32F101xC/D/E and STM32F103xC/D/E,
+ * STM32F101xF/G and STM32F103xF/G
+ * STM32F10xx4 and STM32F10xx6
+ * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+ * debug mode (not accessible by the user software in normal mode).
+ * Refer to errata sheet of these devices for more details.
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGStandbyMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,494 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_cortex.c
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief CORTEX HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the CORTEX:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ * @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+
+ [..]
+ *** How to configure Interrupts using Cortex HAL driver ***
+ ===========================================================
+ [..]
+ This section provide functions allowing to configure the NVIC interrupts (IRQ).
+ The Cortex-M3 exceptions are managed by CMSIS functions.
+
+ (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
+ function according to the following table.
+
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
+ ==========================================================================================================================
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
+ ==========================================================================================================================
+ NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority
+ | | | 4 bits for subpriority
+ --------------------------------------------------------------------------------------------------------------------------
+ NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
+ | | | 3 bits for subpriority
+ --------------------------------------------------------------------------------------------------------------------------
+ NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
+ | | | 2 bits for subpriority
+ --------------------------------------------------------------------------------------------------------------------------
+ NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
+ | | | 1 bits for subpriority
+ --------------------------------------------------------------------------------------------------------------------------
+ NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
+ | | | 0 bits for subpriority
+ ==========================================================================================================================
+ (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
+
+ (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
+
+
+ -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
+ The pending IRQ priority will be managed only by the sub priority.
+
+ -@- IRQ priority order (sorted by highest to lowest priority):
+ (+@) Lowest pre-emption priority
+ (+@) Lowest sub priority
+ (+@) Lowest hardware priority (IRQ number)
+
+ [..]
+ *** How to configure Systick using Cortex HAL driver ***
+ ========================================================
+ [..]
+ Setup SysTick Timer for 1 msec interrupts.
+
+ (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
+ is a CMSIS function that:
+ (++) Configures the SysTick Reload register with value passed as function parameter.
+ (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
+ (++) Resets the SysTick Counter register.
+ (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+ (++) Enables the SysTick Interrupt.
+ (++) Starts the SysTick Counter.
+
+ (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the function
+ HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+ HAL_SYSTICK_Config() function call.
+
+ (+) You can change the SysTick IRQ priority by calling the
+ HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
+ call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
+
+ (+) To adjust the SysTick time base, use the following formula:
+
+ Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
+ (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+ (++) Reload Value should not exceed 0xFFFFFF
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CORTEX CORTEX
+ * @brief CORTEX HAL module driver
+ * @{
+ */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+ * @{
+ */
+
+
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..]
+ This section provide the Cortex HAL driver functions allowing to configure Interrupts
+ Systick functionalities
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Sets the priority grouping field (pre-emption priority and subpriority)
+ * using the required unlock sequence.
+ * @param PriorityGroup: The priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
+ * 4 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
+ * 3 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
+ * 2 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
+ * 1 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
+ * 0 bits for subpriority
+ * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
+ * The pending IRQ priority will be managed only by the subpriority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+ NVIC_SetPriorityGrouping(PriorityGroup);
+}
+
+/**
+ * @brief Sets the priority of an interrupt.
+ * @param IRQn: External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
+ * @param PreemptPriority: The pre-emption priority for the IRQn channel.
+ * This parameter can be a value between 0 and 15
+ * A lower priority value indicates a higher priority
+ * @param SubPriority: the subpriority level for the IRQ channel.
+ * This parameter can be a value between 0 and 15
+ * A lower priority value indicates a higher priority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t prioritygroup = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+
+ prioritygroup = NVIC_GetPriorityGrouping();
+
+ NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+}
+
+/**
+ * @brief Enables a device specific interrupt in the NVIC interrupt controller.
+ * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+ * function should be called before.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
+ * @retval None
+ */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Enable interrupt */
+ NVIC_EnableIRQ(IRQn);
+}
+
+/**
+ * @brief Disables a device specific interrupt in the NVIC interrupt controller.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
+ * @retval None
+ */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+
+ /* Disable interrupt */
+ NVIC_DisableIRQ(IRQn);
+}
+
+/**
+ * @brief Initiates a system reset request to reset the MCU.
+ * @retval None
+ */
+void HAL_NVIC_SystemReset(void)
+{
+ /* System Reset */
+ NVIC_SystemReset();
+}
+
+/**
+ * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ * Counter is in free running mode to generate periodic interrupts.
+ * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
+ * @retval status: - 0 Function succeeded.
+ * - 1 Function failed.
+ */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+ return SysTick_Config(TicksNumb);
+}
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Cortex control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the CORTEX
+ (NVIC, SYSTICK, MPU) functionalities.
+
+
+@endverbatim
+ * @{
+ */
+
+#if (__MPU_PRESENT == 1)
+/**
+ * @brief Initializes and configures the Region and the memory to be protected.
+ * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
+ * the initialization and configuration information.
+ * @retval None
+ */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+ assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+
+ /* Set the Region number */
+ MPU->RNR = MPU_Init->Number;
+
+ if ((MPU_Init->Enable) != RESET)
+ {
+ /* Check the parameters */
+ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+ assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+ assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+ assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+ assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+ assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+ assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+ assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+
+ MPU->RBAR = MPU_Init->BaseAddress;
+ MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
+ ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
+ ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
+ ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
+ ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
+ ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
+ ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
+ ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
+ ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
+ }
+ else
+ {
+ MPU->RBAR = 0x00;
+ MPU->RASR = 0x00;
+ }
+}
+#endif /* __MPU_PRESENT */
+
+/**
+ * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
+ * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
+ */
+uint32_t HAL_NVIC_GetPriorityGrouping(void)
+{
+ /* Get the PRIGROUP[10:8] field value */
+ return NVIC_GetPriorityGrouping();
+}
+
+/**
+ * @brief Gets the priority of an interrupt.
+ * @param IRQn: External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
+ * @param PriorityGroup: the priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
+ * 4 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
+ * 3 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
+ * 2 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
+ * 1 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
+ * 0 bits for subpriority
+ * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
+ * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
+ * @retval None
+ */
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+ /* Get priority for Cortex-M system or device specific interrupts */
+ NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
+}
+
+/**
+ * @brief Sets Pending bit of an external interrupt.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
+ * @retval None
+ */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ /* Set interrupt pending */
+ NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Gets Pending Interrupt (reads the pending register in the NVIC
+ * and returns the pending bit for the specified interrupt).
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
+ * @retval status: - 0 Interrupt status is not pending.
+ * - 1 Interrupt status is pending.
+ */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ /* Return 1 if pending else 0 */
+ return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Clears the pending bit of an external interrupt.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
+ * @retval None
+ */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ /* Clear pending interrupt */
+ NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
+ * @retval status: - 0 Interrupt status is not pending.
+ * - 1 Interrupt status is pending.
+ */
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
+{
+ /* Return 1 if active else 0 */
+ return NVIC_GetActive(IRQn);
+}
+
+/**
+ * @brief Configures the SysTick clock source.
+ * @param CLKSource: specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+ * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+ * @retval None
+ */
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+ if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
+ {
+ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+ }
+ else
+ {
+ SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+ }
+}
+
+/**
+ * @brief This function handles SYSTICK interrupt request.
+ * @retval None
+ */
+void HAL_SYSTICK_IRQHandler(void)
+{
+ HAL_SYSTICK_Callback();
+}
+
+/**
+ * @brief SYSTICK callback.
+ * @retval None
+ */
+__weak void HAL_SYSTICK_Callback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SYSTICK_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,709 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_dma.c
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief DMA HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the Direct Memory Access (DMA) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and errors functions
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable and configure the peripheral to be connected to the DMA Channel
+ (except for internal SRAM / FLASH memories: no initialization is
+ necessary) please refer to Reference manual for connection between peripherals
+ and DMA requests.
+
+ (#) For a given Channel, program the required configuration through the following parameters:
+ Transfer Direction, Source and Destination data formats,
+ Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
+ using HAL_DMA_Init() function.
+
+ (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
+ detection.
+
+ (#) Use HAL_DMA_Abort() function to abort the current transfer
+
+ -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
+ address and destination address and the Length of data to be transferred
+ (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
+ case a fixed Timeout can be configured by User depending from his application.
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+ (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+ (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
+ Source address and destination address and the Length of data to be transferred.
+ In this case the DMA interrupt is configured
+ (+) Use HAL_DMAy_Channelx_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+ (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
+ add his own function by customization of function pointer XferCpltCallback and
+ XferErrorCallback (i.e a member of DMA handle structure).
+
+ *** DMA HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in DMA HAL driver.
+
+ (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
+ (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
+ (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
+ (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
+ (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
+ (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
+ (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
+
+ [..]
+ (@) You can refer to the DMA HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DMA DMA
+ * @brief DMA HAL module driver
+ * @{
+ */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Constants DMA Private Constants
+ * @{
+ */
+#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+ * @{
+ */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Functions DMA Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to initialize the DMA Channel source
+ and destination addresses, incrementation and data sizes, transfer direction,
+ circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
+ [..]
+ The HAL_DMA_Init() function follows the DMA configuration procedures as described in
+ reference manual.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the DMA according to the specified
+ * parameters in the DMA_InitTypeDef and create the associated handle.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+{
+ uint32_t tmp = 0;
+
+ /* Check the DMA handle allocation */
+ if(hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+ assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+ assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+ assert_param(IS_DMA_MODE(hdma->Init.Mode));
+ assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+
+ if(hdma->State == HAL_DMA_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hdma->Lock = HAL_UNLOCKED;
+ }
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Get the CR register value */
+ tmp = hdma->Instance->CCR;
+
+ /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
+ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
+ DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
+ DMA_CCR_DIR));
+
+ /* Prepare the DMA Channel configuration */
+ tmp |= hdma->Init.Direction |
+ hdma->Init.PeriphInc | hdma->Init.MemInc |
+ hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ hdma->Init.Mode | hdma->Init.Priority;
+
+ /* Write to DMA Channel CR register */
+ hdma->Instance->CCR = tmp;
+
+ /* Initialise the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Initialize the DMA state*/
+ hdma->State = HAL_DMA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the DMA peripheral
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
+{
+ /* Check the DMA handle allocation */
+ if(hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+ /* Check the DMA peripheral state */
+ if(hdma->State == HAL_DMA_STATE_BUSY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable the selected DMA Channelx */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Reset DMA Channel control register */
+ hdma->Instance->CCR = 0;
+
+ /* Reset DMA Channel Number of Data to Transfer register */
+ hdma->Instance->CNDTR = 0;
+
+ /* Reset DMA Channel peripheral address register */
+ hdma->Instance->CPAR = 0;
+
+ /* Reset DMA Channel memory address register */
+ hdma->Instance->CMAR = 0;
+
+ /* Clear all flags */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+ /* Initialize the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Initialize the DMA state */
+ hdma->State = HAL_DMA_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
+ * @brief I/O operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the source, destination address and data length and Start DMA transfer
+ (+) Configure the source, destination address and data length and
+ Start DMA transfer with interrupt
+ (+) Abort DMA transfer
+ (+) Poll for transfer complete
+ (+) Handle DMA interrupt request
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the DMA Transfer.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param SrcAddress: The source memory Buffer address
+ * @param DstAddress: The destination memory Buffer address
+ * @param DataLength: The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+ /* Disable the peripheral */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Configure the source, destination address and the data length */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the Peripheral */
+ __HAL_DMA_ENABLE(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the DMA Transfer with interrupt enabled.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param SrcAddress: The source memory Buffer address
+ * @param DstAddress: The destination memory Buffer address
+ * @param DataLength: The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+ /* Disable the peripheral */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Configure the source, destination address and the data length */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the transfer complete interrupt */
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
+
+ /* Enable the Half transfer complete interrupt */
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
+
+ /* Enable the transfer Error interrupt */
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
+
+ /* Enable the Peripheral */
+ __HAL_DMA_ENABLE(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Aborts the DMA Transfer.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ *
+ * @note After disabling a DMA Channel, a check for wait until the DMA Channel is
+ * effectively disabled is added. If a Channel is disabled
+ * while a data transfer is ongoing, the current data will be transferred
+ * and the Channel will be effectively disabled only after the transfer of
+ * this single data is finished.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+{
+ uint32_t tickstart = 0x00;
+
+ /* Disable the channel */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check if the DMA Channel is effectively disabled */
+ while((hdma->Instance->CCR & DMA_CCR_EN) != 0)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
+ {
+ /* Update error code */
+ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Polling for transfer complete.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param CompleteLevel: Specifies the DMA level complete.
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
+{
+ uint32_t temp;
+ uint32_t tickstart = 0x00;
+
+ /* Get the level transfer complete flag */
+ if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+ {
+ /* Transfer Complete flag */
+ temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
+ }
+ else
+ {
+ /* Half Transfer Complete flag */
+ temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
+ {
+ if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
+ {
+ /* Clear the transfer error flags */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+
+ /* Update error code */
+ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
+
+ /* Change the DMA state */
+ hdma->State= HAL_DMA_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Update error code */
+ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+ {
+ /* Clear the transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+
+ /* The selected Channelx EN bit is cleared (DMA is disabled and
+ all transfers are complete) */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ }
+ else
+ {
+ /* Clear the half transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+ /* The selected Channelx EN bit is cleared (DMA is disabled and
+ all transfers of half buffer are complete) */
+ hdma->State = HAL_DMA_STATE_READY_HALF;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles DMA interrupt request.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval None
+ */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+ /* Transfer Error Interrupt management ***************************************/
+ if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
+ {
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
+ {
+ /* Disable the transfer error interrupt */
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
+
+ /* Clear the transfer error flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+
+ /* Update error code */
+ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ if (hdma->XferErrorCallback != NULL)
+ {
+ /* Transfer error callback */
+ hdma->XferErrorCallback(hdma);
+ }
+ }
+ }
+
+ /* Half Transfer Complete Interrupt management ******************************/
+ if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
+ {
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
+ {
+ /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
+ {
+ /* Disable the half transfer interrupt */
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+ }
+ /* Clear the half transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_READY_HALF;
+
+ if(hdma->XferHalfCpltCallback != NULL)
+ {
+ /* Half transfer callback */
+ hdma->XferHalfCpltCallback(hdma);
+ }
+ }
+ }
+
+ /* Transfer Complete Interrupt management ***********************************/
+ if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
+ {
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
+ {
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
+ {
+ /* Disable the transfer complete interrupt */
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
+ }
+ /* Clear the transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+
+ /* Update error code */
+ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_NONE);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ if(hdma->XferCpltCallback != NULL)
+ {
+ /* Transfer complete callback */
+ hdma->XferCpltCallback(hdma);
+ }
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Check the DMA state
+ (+) Get error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the DMA state.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL state
+ */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
+{
+ return hdma->State;
+}
+
+/**
+ * @brief Return the DMA error code
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval DMA Error Code
+ */
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
+{
+ return hdma->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Functions DMA Private Functions
+ * @{
+ */
+
+/**
+ * @brief Sets the DMA Transfer parameter.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param SrcAddress: The source memory Buffer address
+ * @param DstAddress: The destination memory Buffer address
+ * @param DataLength: The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ /* Configure DMA Channel data length */
+ hdma->Instance->CNDTR = DataLength;
+
+ /* Peripheral to Memory */
+ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+ {
+ /* Configure DMA Channel destination address */
+ hdma->Instance->CPAR = DstAddress;
+
+ /* Configure DMA Channel source address */
+ hdma->Instance->CMAR = SrcAddress;
+ }
+ /* Memory to Peripheral */
+ else
+ {
+ /* Configure DMA Channel source address */
+ hdma->Instance->CPAR = SrcAddress;
+
+ /* Configure DMA Channel destination address */
+ hdma->Instance->CMAR = DstAddress;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,974 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_flash.c
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief FLASH HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the internal FLASH memory:
+ * + Program operations functions
+ * + Memory Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### FLASH peripheral features #####
+ ==============================================================================
+ [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
+ to the Flash memory. It implements the erase and program Flash memory operations
+ and the read and write protection mechanisms.
+
+ [..] The Flash memory interface accelerates code execution with a system of instruction
+ prefetch.
+
+ [..] The FLASH main features are:
+ (+) Flash memory read operations
+ (+) Flash memory program/erase operations
+ (+) Read / write protections
+ (+) Prefetch on I-Code
+ (+) Option Bytes programming
+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver provides functions and macros to configure and program the FLASH
+ memory of all STM32F1xx devices.
+
+ (#) FLASH Memory I/O Programming functions: this group includes all needed
+ functions to erase and program the main memory:
+ (++) Lock and Unlock the FLASH interface
+ (++) Erase function: Erase page, erase all pages
+ (++) Program functions: half word, word and doubleword
+
+ (#) FLASH Option Bytes Programming functions: this group includes all needed
+ functions to manage the Option Bytes:
+ (++) Lock and Unlock the Option Bytes
+ (++) Set/Reset the write protection
+ (++) Set the Read protection Level
+ (++) Program the user Option Bytes
+ (++) Launch the Option Bytes loader
+ (++) Erase Option Bytes
+ (++) Program the data Option Bytes
+ (++) Get the Write protection.
+ (++) Get the user option bytes.
+
+ (#) Interrupts and flags management functions : this group
+ includes all needed functions to:
+ (++) Handle FLASH interrupts
+ (++) Wait for last FLASH operation according to its status
+ (++) Get error flag status
+
+ [..] In addition to these function, this driver includes a set of macros allowing
+ to handle the following operations:
+
+ (+) Set/Get the latency
+ (+) Enable/Disable the prefetch buffer
+ (+) Enable/Disable the half cycle access
+ (+) Enable/Disable the FLASH interrupts
+ (+) Monitor the FLASH flags status
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/** @defgroup FLASH FLASH
+ * @brief FLASH HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup FLASH_Private_Constants FLASH Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macro ---------------------------- ---------------------------------*/
+/** @defgroup FLASH_Private_Macros FLASH Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Variables FLASH Private Variables
+ * @{
+ */
+/* Variables used for Erase pages under interruption*/
+FLASH_ProcessTypeDef pFlash;
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASH_Private_Functions FLASH Private Functions
+ * @{
+ */
+static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
+static void FLASH_SetErrorCode(void);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
+ * @{
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
+ * @brief Programming operation functions
+ *
+@verbatim
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Program halfword, word or double word at a specified address
+ * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
+ *
+ * @note If an erase and a program operations are requested simultaneously,
+ * the erase operation is performed before the program one.
+ *
+ * @note FLASH should be previously erased before new programmation (only exception to this
+ * is when 0x0000 is programmed)
+ *
+ * @param TypeProgram: Indicate the way to program at a specified address.
+ * This parameter can be a value of @ref FLASH_Type_Program
+ * @param Address: Specifies the address to be programmed.
+ * @param Data: Specifies the data to be programmed
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+ uint8_t index = 0;
+ uint8_t nbiterations = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+#if defined(FLASH_BANK2_END)
+ if(Address <= FLASH_BANK1_END)
+ {
+#endif /* FLASH_BANK2_END */
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+#if defined(FLASH_BANK2_END)
+ }
+ else
+ {
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* FLASH_BANK2_END */
+
+ if(status == HAL_OK)
+ {
+ if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
+ {
+ /* Program halfword (16-bit) at a specified address. */
+ nbiterations = 1;
+ }
+ else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
+ {
+ /* Program word (32-bit = 2*16-bit) at a specified address. */
+ nbiterations = 2;
+ }
+ else
+ {
+ /* Program double word (64-bit = 4*16-bit) at a specified address. */
+ nbiterations = 4;
+ }
+
+ for (index = 0; index < nbiterations; index++)
+ {
+ FLASH_Program_HalfWord((Address + (2*index)), (uint16_t)(Data >> (16*index)));
+
+#if defined(FLASH_BANK2_END)
+ if(Address <= FLASH_BANK1_END)
+ {
+#endif /* FLASH_BANK2_END */
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the program operation is completed, disable the PG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
+#if defined(FLASH_BANK2_END)
+ }
+ else
+ {
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the program operation is completed, disable the PG Bit */
+ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG);
+ }
+#endif /* FLASH_BANK2_END */
+ /* In case of error, stop programation procedure */
+ if (status != HAL_OK)
+ {
+ break;
+ }
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Program halfword, word or double word at a specified address with interrupt enabled.
+ * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
+ *
+ * @note If an erase and a program operations are requested simultaneously,
+ * the erase operation is performed before the program one.
+ *
+ * @param TypeProgram: Indicate the way to program at a specified address.
+ * This parameter can be a value of @ref FLASH_Type_Program
+ * @param Address: Specifies the address to be programmed.
+ * @param Data: Specifies the data to be programmed
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+#if defined(FLASH_BANK2_END)
+ /* If procedure already ongoing, reject the next one */
+ if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
+ {
+ return HAL_ERROR;
+ }
+
+ if(Address <= FLASH_BANK1_END)
+ {
+ /* Enable End of FLASH Operation and Error source interrupts */
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1);
+
+ }else
+ {
+ /* Enable End of FLASH Operation and Error source interrupts */
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);
+ }
+#else
+ /* Enable End of FLASH Operation and Error source interrupts */
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
+#endif /* FLASH_BANK2_END */
+
+ pFlash.Address = Address;
+ pFlash.Data = Data;
+
+ if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
+ {
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;
+ /*Program halfword (16-bit) at a specified address.*/
+ pFlash.DataRemaining = 1;
+ }
+ else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
+ {
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD;
+ /*Program word (32-bit : 2*16-bit) at a specified address.*/
+ pFlash.DataRemaining = 2;
+ }
+ else
+ {
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD;
+ /*Program double word (64-bit : 4*16-bit) at a specified address.*/
+ pFlash.DataRemaining = 4;
+ }
+
+ /*Program halfword (16-bit) at a specified address.*/
+ FLASH_Program_HalfWord(Address, (uint16_t)Data);
+
+ return status;
+}
+
+/**
+ * @brief This function handles FLASH interrupt request.
+ * @retval None
+ */
+void HAL_FLASH_IRQHandler(void)
+{
+ uint32_t addresstmp = 0;
+
+ /* Check FLASH operation error flags */
+#if defined(FLASH_BANK2_END)
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK1) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK1) || \
+ (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)))
+#else
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
+#endif /* FLASH_BANK2_END */
+ {
+ /*return the faulty address*/
+ addresstmp = pFlash.Address;
+ /* Reset address */
+ pFlash.Address = 0xFFFFFFFF;
+
+ /*Save the Error code*/
+ FLASH_SetErrorCode();
+
+ /* FLASH error interrupt user callback */
+ HAL_FLASH_OperationErrorCallback(addresstmp);
+
+ /* Stop the procedure ongoing*/
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+
+ /* Check FLASH End of Operation flag */
+#if defined(FLASH_BANK2_END)
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK1))
+ {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK1);
+#else
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+ {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+#endif /* FLASH_BANK2_END */
+
+ /* Process can continue only if no error detected */
+ if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
+ {
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
+ {
+ /* Nb of pages to erased can be decreased */
+ pFlash.DataRemaining--;
+
+ /* Check if there are still pages to erase*/
+ if(pFlash.DataRemaining != 0)
+ {
+ addresstmp = pFlash.Address;
+ /*Indicate user which sector has been erased*/
+ HAL_FLASH_EndOfOperationCallback(addresstmp);
+
+ /*Increment sector number*/
+ addresstmp = pFlash.Address + FLASH_PAGE_SIZE;
+ pFlash.Address = addresstmp;
+
+ /* If the erase operation is completed, disable the PER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
+
+ FLASH_PageErase(addresstmp);
+ }
+ else
+ {
+ /*No more pages to Erase, user callback can be called.*/
+ /*Reset Sector and stop Erase pages procedure*/
+ pFlash.Address = addresstmp = 0xFFFFFFFF;
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ /* FLASH EOP interrupt user callback */
+ HAL_FLASH_EndOfOperationCallback(addresstmp);
+ }
+ }
+ else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
+ {
+ /* Operation is completed, disable the MER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
+
+#if defined(FLASH_BANK2_END)
+ /* Stop Mass Erase procedure if no pending mass erase on other bank */
+ if (HAL_IS_BIT_CLR(FLASH->CR2, FLASH_CR2_MER))
+ {
+#endif /* FLASH_BANK2_END */
+ /* MassErase ended. Return the selected bank*/
+ /* FLASH EOP interrupt user callback */
+ HAL_FLASH_EndOfOperationCallback(0);
+
+ /* Stop Mass Erase procedure*/
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+#if defined(FLASH_BANK2_END)
+ }
+#endif /* FLASH_BANK2_END */
+ else
+ {
+ /* Nb of 16-bit data to program can be decreased */
+ pFlash.DataRemaining--;
+
+ /* Check if there are still 16-bit data to program */
+ if(pFlash.DataRemaining != 0)
+ {
+ /* Increment address to 16-bit */
+ pFlash.Address += 2;
+ addresstmp = pFlash.Address;
+
+ /* Shift to have next 16-bit data */
+ pFlash.Data = (pFlash.Data >> 16);
+
+ /* Operation is completed, disable the PG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
+
+ /*Program halfword (16-bit) at a specified address.*/
+ FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
+ }
+ else
+ {
+ /*Program ended. Return the selected address*/
+ /* FLASH EOP interrupt user callback */
+ if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+ }
+ else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2);
+ }
+ else
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6);
+ }
+
+ /* Reset Address and stop Program procedure*/
+ pFlash.Address = 0xFFFFFFFF;
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+ }
+ }
+ }
+
+#if defined(FLASH_BANK2_END)
+ /* Check FLASH End of Operation flag */
+ if(__HAL_FLASH_GET_FLAG( FLASH_FLAG_EOP_BANK2))
+ {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2);
+
+ /* Process can continue only if no error detected */
+ if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
+ {
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
+ {
+ /* Nb of pages to erased can be decreased */
+ pFlash.DataRemaining--;
+
+ /* Check if there are still pages to erase*/
+ if(pFlash.DataRemaining != 0)
+ {
+ /* Indicate user which page address has been erased*/
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+
+ /* Increment page address to next page */
+ pFlash.Address += FLASH_PAGE_SIZE;
+ addresstmp = pFlash.Address;
+
+ /* Operation is completed, disable the PER Bit */
+ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER);
+
+ FLASH_PageErase(addresstmp);
+ }
+ else
+ {
+ /*No more pages to Erase*/
+
+ /*Reset Address and stop Erase pages procedure*/
+ pFlash.Address = 0xFFFFFFFF;
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+
+ /* FLASH EOP interrupt user callback */
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+ }
+ }
+ else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
+ {
+ /* Operation is completed, disable the MER Bit */
+ CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER);
+
+ if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_MER))
+ {
+ /* MassErase ended. Return the selected bank*/
+ /* FLASH EOP interrupt user callback */
+ HAL_FLASH_EndOfOperationCallback(0);
+
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+ }
+ else
+ {
+ /* Nb of 16-bit data to program can be decreased */
+ pFlash.DataRemaining--;
+
+ /* Check if there are still 16-bit data to program */
+ if(pFlash.DataRemaining != 0)
+ {
+ /* Increment address to 16-bit */
+ pFlash.Address += 2;
+ addresstmp = pFlash.Address;
+
+ /* Shift to have next 16-bit data */
+ pFlash.Data = (pFlash.Data >> 16);
+
+ /* Operation is completed, disable the PG Bit */
+ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG);
+
+ /*Program halfword (16-bit) at a specified address.*/
+ FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
+ }
+ else
+ {
+ /*Program ended. Return the selected address*/
+ /* FLASH EOP interrupt user callback */
+ if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+ }
+ else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address-2);
+ }
+ else
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address-6);
+ }
+
+ /* Reset Address and stop Program procedure*/
+ pFlash.Address = 0xFFFFFFFF;
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+ }
+ }
+ }
+#endif
+
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
+ {
+#if defined(FLASH_BANK2_END)
+ /* Operation is completed, disable the PG, PER and MER Bits for both bank */
+ CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
+ CLEAR_BIT(FLASH->CR2, (FLASH_CR2_PG | FLASH_CR2_PER | FLASH_CR2_MER));
+
+ /* Disable End of FLASH Operation and Error source interrupts for both banks */
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1 | FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);
+#else
+ /* Operation is completed, disable the PG, PER and MER Bits */
+ CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
+
+ /* Disable End of FLASH Operation and Error source interrupts */
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
+#endif /* FLASH_BANK2_END */
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ }
+}
+
+
+/**
+ * @brief FLASH end of operation interrupt callback
+ * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
+ * - Mass Erase: No return value expected
+ * - Pages Erase: Address of the page which has been erased
+ * (if 0xFFFFFFFF, it means that all the selected pages have been erased)
+ * - Program: Address which was selected for data program
+ * @retval none
+ */
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(ReturnValue);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief FLASH operation error interrupt callback
+ * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
+ * - Mass Erase: No return value expected
+ * - Pages Erase: Address of the page which returned an error
+ * - Program: Address which was selected for data program
+ * @retval none
+ */
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(ReturnValue);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the FLASH
+ memory operations.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Unlock the FLASH control register access
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+{
+ if (HAL_IS_BIT_SET(FLASH->CR, FLASH_CR_LOCK))
+ {
+ /* Authorize the FLASH Registers access */
+ WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+ WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+#if defined(FLASH_BANK2_END)
+ if (HAL_IS_BIT_SET(FLASH->CR2, FLASH_CR2_LOCK))
+ {
+ /* Authorize the FLASH BANK2 Registers access */
+ WRITE_REG(FLASH->KEYR2, FLASH_KEY1);
+ WRITE_REG(FLASH->KEYR2, FLASH_KEY2);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+#endif /* FLASH_BANK2_END */
+ return HAL_OK;
+}
+
+/**
+ * @brief Locks the FLASH control register access
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Lock(void)
+{
+ /* Set the LOCK Bit to lock the FLASH Registers access */
+ SET_BIT(FLASH->CR, FLASH_CR_LOCK);
+
+#if defined(FLASH_BANK2_END)
+ /* Set the LOCK Bit to lock the FLASH BANK2 Registers access */
+ SET_BIT(FLASH->CR2, FLASH_CR2_LOCK);
+#endif /* FLASH_BANK2_END */
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Unlock the FLASH Option Control Registers access.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
+{
+ if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE))
+ {
+ /* Authorizes the Option Byte register programming */
+ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
+ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Lock the FLASH Option Control Registers access.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
+{
+ /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Launch the option byte loading.
+ * @note This function will reset automatically the MCU.
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
+{
+ /* Initiates a system reset request to launch the option byte loading */
+ HAL_NVIC_SystemReset();
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the FLASH peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Get the specific FLASH error flag.
+ * @retval FLASH_ErrorCode: The returned value can be:
+ * @ref FLASH_Error_Codes
+ */
+uint32_t HAL_FLASH_GetError(void)
+{
+ return pFlash.ErrorCode;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Program a half-word (16-bit) at a specified address.
+ * @param Address: specifies the address to be programmed.
+ * @param Data: specifies the data to be programmed.
+ * @retval None
+ */
+static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
+{
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+#if defined(FLASH_BANK2_END)
+ if(Address <= FLASH_BANK1_END)
+ {
+#endif /* FLASH_BANK2_END */
+ /* Proceed to program the new data */
+ SET_BIT(FLASH->CR, FLASH_CR_PG);
+#if defined(FLASH_BANK2_END)
+ }
+ else
+ {
+ /* Proceed to program the new data */
+ SET_BIT(FLASH->CR2, FLASH_CR2_PG);
+ }
+#endif /* FLASH_BANK2_END */
+
+ /* Write data in the address */
+ *(__IO uint16_t*)Address = Data;
+}
+
+/**
+ * @brief Wait for a FLASH operation to complete.
+ * @param Timeout: maximum flash operation timeout
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+ /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
+ Even if the FLASH operation fails, the BUSY flag will be reset and an error
+ flag will be set */
+
+ uint32_t tickstart = HAL_GetTick();
+
+ while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Check FLASH End of Operation flag */
+ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+ {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+ }
+
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
+ __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
+ __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
+ {
+ /*Save the error code*/
+ FLASH_SetErrorCode();
+ return HAL_ERROR;
+ }
+
+ /* If there is no error flag set */
+ return HAL_OK;
+}
+
+#if defined(FLASH_BANK2_END)
+/**
+ * @brief Wait for a FLASH BANK2 operation to complete.
+ * @param Timeout: maximum flash operation timeout
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout)
+{
+ /* Wait for the FLASH BANK2 operation to complete by polling on BUSY flag to be reset.
+ Even if the FLASH BANK2 operation fails, the BUSY flag will be reset and an error
+ flag will be set */
+
+ uint32_t tickstart = HAL_GetTick();
+
+ while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY_BANK2))
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Check FLASH End of Operation flag */
+ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2))
+ {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2);
+ }
+
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))
+ {
+ /*Save the error code*/
+ FLASH_SetErrorCode();
+ return HAL_ERROR;
+ }
+
+ /* If there is an error flag set */
+ return HAL_OK;
+
+}
+#endif /* FLASH_BANK2_END */
+
+/**
+ * @brief Set the specific FLASH error flag.
+ * @retval None
+ */
+static void FLASH_SetErrorCode(void)
+{
+#if defined(FLASH_BANK2_END)
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2))
+#else
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
+#endif /* FLASH_BANK2_END */
+ {
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
+ }
+#if defined(FLASH_BANK2_END)
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))
+#else
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
+#endif /* FLASH_BANK2_END */
+ {
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
+ }
+
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
+ {
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
+ }
+
+ /* Clear FLASH error pending bits */
+#if defined(FLASH_BANK2_END)
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2);
+#else
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
+#endif /* FLASH_BANK2_END */
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1140 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_flash_ex.c
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief Extended FLASH HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the FLASH peripheral:
+ * + Extended Initialization/de-initialization functions
+ * + Extended I/O operation functions
+ * + Extended Peripheral Control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### Flash peripheral extended features #####
+ ==============================================================================
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to configure and program the FLASH memory
+ of all STM32F1xxx devices. It includes
+
+ (++) Set/Reset the write protection
+ (++) Program the user Option Bytes
+ (++) Get the Read protection Level
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/** @addtogroup FLASH
+ * @{
+ */
+/** @addtogroup FLASH_Private_Variables
+ * @{
+ */
+/* Variables used for Erase pages under interruption*/
+extern FLASH_ProcessTypeDef pFlash;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx FLASHEx
+ * @brief FLASH HAL Extension module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants
+ * @{
+ */
+#define FLASH_POSITION_IWDGSW_BIT (uint32_t)POSITION_VAL(FLASH_OBR_IWDG_SW)
+#define FLASH_POSITION_OB_USERDATA0_BIT (uint32_t)POSITION_VAL(FLASH_OBR_DATA0)
+#define FLASH_POSITION_OB_USERDATA1_BIT (uint32_t)POSITION_VAL(FLASH_OBR_DATA1)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
+ * @{
+ */
+/* Erase operations */
+static void FLASH_MassErase(uint32_t Banks);
+
+/* Option bytes control */
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage);
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage);
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel);
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig);
+static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
+static uint32_t FLASH_OB_GetWRP(void);
+static uint32_t FLASH_OB_GetRDP(void);
+static uint8_t FLASH_OB_GetUser(void);
+
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
+ * @{
+ */
+
+/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions
+ * @brief FLASH Memory Erasing functions
+ *
+@verbatim
+ ==============================================================================
+ ##### FLASH Erasing Programming functions #####
+ ==============================================================================
+
+ [..] The FLASH Memory Erasing functions, includes the following functions:
+ (+) @ref HAL_FLASHEx_Erase: return only when erase has been done
+ (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback
+ is called with parameter 0xFFFFFFFF
+
+ [..] Any operation of erase should follow these steps:
+ (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and
+ program memory access.
+ (#) Call the desired function to erase page.
+ (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access
+ (recommended to protect the FLASH memory against possible unwanted operation).
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Perform a mass erase or erase the specified FLASH memory pages
+ * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
+ * must be called before.
+ * Call the @ref HAL_FLASH_Lock() to disable the flash memory access
+ * (recommended to protect the FLASH memory against possible unwanted operation)
+ * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+ * contains the configuration information for the erasing.
+ *
+ * @param[out] PageError pointer to variable that
+ * contains the configuration information on faulty page in case of error
+ * (0xFFFFFFFF means that all the pages have been correctly erased)
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+ uint32_t address = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+ if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+ {
+#if defined(FLASH_BANK2_END)
+ if (pEraseInit->Banks == FLASH_BANK_BOTH)
+ {
+ /* Mass Erase requested for Bank1 and Bank2 */
+ /* Wait for last operation to be completed */
+ if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && \
+ (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK))
+ {
+ /*Mass erase to be done*/
+ FLASH_MassErase(FLASH_BANK_BOTH);
+
+ /* Wait for last operation to be completed */
+ if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && \
+ (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK))
+ {
+ status = HAL_OK;
+ }
+
+ /* If the erase operation is completed, disable the MER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
+ CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER);
+ }
+ }
+ else if (pEraseInit->Banks == FLASH_BANK_2)
+ {
+ /* Mass Erase requested for Bank2 */
+ /* Wait for last operation to be completed */
+ if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
+ {
+ /*Mass erase to be done*/
+ FLASH_MassErase(FLASH_BANK_2);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the MER Bit */
+ CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER);
+ }
+ }
+ else
+#endif /* FLASH_BANK2_END */
+ {
+ /* Mass Erase requested for Bank1 */
+ /* Wait for last operation to be completed */
+ if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
+ {
+ /*Mass erase to be done*/
+ FLASH_MassErase(FLASH_BANK_1);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the MER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
+ }
+ }
+ }
+ else
+ {
+ /* Page Erase is requested */
+ /* Check the parameters */
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
+ assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
+
+#if defined(FLASH_BANK2_END)
+ /* Page Erase requested on address located on bank2 */
+ if(pEraseInit->PageAddress > FLASH_BANK1_END)
+ {
+ /* Wait for last operation to be completed */
+ if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
+ {
+ /*Initialization of PageError variable*/
+ *PageError = 0xFFFFFFFF;
+
+ /* Erase by page by page to be done*/
+ for(address = pEraseInit->PageAddress;
+ address < (pEraseInit->PageAddress + (pEraseInit->NbPages)*FLASH_PAGE_SIZE);
+ address += FLASH_PAGE_SIZE)
+ {
+ FLASH_PageErase(address);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the PER Bit */
+ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER);
+
+ if (status != HAL_OK)
+ {
+ /* In case of error, stop erase procedure and return the faulty address */
+ *PageError = address;
+ break;
+ }
+ }
+ }
+ }
+ else
+#endif /* FLASH_BANK2_END */
+ {
+ /* Page Erase requested on address located on bank1 */
+ /* Wait for last operation to be completed */
+ if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
+ {
+ /*Initialization of PageError variable*/
+ *PageError = 0xFFFFFFFF;
+
+ /* Erase page by page to be done*/
+ for(address = pEraseInit->PageAddress;
+ address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
+ address += FLASH_PAGE_SIZE)
+ {
+ FLASH_PageErase(address);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the PER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
+
+ if (status != HAL_OK)
+ {
+ /* In case of error, stop erase procedure and return the faulty address */
+ *PageError = address;
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled
+ * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
+ * must be called before.
+ * Call the @ref HAL_FLASH_Lock() to disable the flash memory access
+ * (recommended to protect the FLASH memory against possible unwanted operation)
+ * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+ * contains the configuration information for the erasing.
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* If procedure already ongoing, reject the next one */
+ if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+ /* Enable End of FLASH Operation and Error source interrupts */
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
+
+#if defined(FLASH_BANK2_END)
+ /* Enable End of FLASH Operation and Error source interrupts */
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);
+
+#endif
+ if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+ {
+ /*Mass erase to be done*/
+ pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
+ FLASH_MassErase(pEraseInit->Banks);
+ }
+ else
+ {
+ /* Erase by page to be done*/
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
+ assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
+
+ pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
+ pFlash.DataRemaining = pEraseInit->NbPages;
+ pFlash.Address = pEraseInit->PageAddress;
+
+ /*Erase 1st page and wait for IT*/
+ FLASH_PageErase(pEraseInit->PageAddress);
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions
+ * @brief Option Bytes Programming functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Option Bytes Programming functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the FLASH
+ option bytes operations.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Erases the FLASH option bytes.
+ * @note This functions erases all option bytes except the Read protection (RDP).
+ * The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
+ * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
+ * (system reset will occur)
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_FLASHEx_OBErase(void)
+{
+ uint8_t rdptmp = OB_RDP_LEVEL_0;
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Get the actual read protection Option Byte value */
+ rdptmp = FLASH_OB_GetRDP();
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* If the previous operation is completed, proceed to erase the option bytes */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTER);
+ SET_BIT(FLASH->CR, FLASH_CR_STRT);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the OPTER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
+
+ if(status == HAL_OK)
+ {
+ /* Restore the last read protection Option Byte value */
+ status = FLASH_OB_RDP_LevelConfig(rdptmp);
+ }
+ }
+
+ /* Return the erase status */
+ return status;
+}
+
+/**
+ * @brief Program option bytes
+ * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
+ * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
+ * (system reset will occur)
+ *
+ * @param pOBInit pointer to an FLASH_OBInitStruct structure that
+ * contains the configuration information for the programming.
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
+
+ /* Write protection configuration */
+ if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
+ {
+ assert_param(IS_WRPSTATE(pOBInit->WRPState));
+ if (pOBInit->WRPState == OB_WRPSTATE_ENABLE)
+ {
+ /* Enable of Write protection on the selected page */
+ status = FLASH_OB_EnableWRP(pOBInit->WRPPage);
+ }
+ else
+ {
+ /* Disable of Write protection on the selected page */
+ status = FLASH_OB_DisableWRP(pOBInit->WRPPage);
+ }
+ if (status != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ return status;
+ }
+ }
+
+ /* Read protection configuration */
+ if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
+ {
+ status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
+ if (status != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ return status;
+ }
+ }
+
+ /* USER configuration */
+ if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
+ {
+ status = FLASH_OB_UserConfig(pOBInit->USERConfig);
+ if (status != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ return status;
+ }
+ }
+
+ /* DATA configuration*/
+ if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA)
+ {
+ status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData);
+ if (status != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ return status;
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Get the Option byte configuration
+ * @param pOBInit pointer to an FLASH_OBInitStruct structure that
+ * contains the configuration information for the programming.
+ *
+ * @retval None
+ */
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+ pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER;
+
+ /*Get WRP*/
+ pOBInit->WRPPage = FLASH_OB_GetWRP();
+
+ /*Get RDP Level*/
+ pOBInit->RDPLevel = FLASH_OB_GetRDP();
+
+ /*Get USER*/
+ pOBInit->USERConfig = FLASH_OB_GetUser();
+}
+
+/**
+ * @brief Get the Option byte user data
+ * @param DATAAdress Address of the option byte DATA
+ * This parameter can be one of the following values:
+ * @arg @ref OB_DATA_ADDRESS_DATA0
+ * @arg @ref OB_DATA_ADDRESS_DATA1
+ * @retval Value programmed in USER data
+ */
+uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress)
+{
+ uint32_t value = 0;
+
+ if (DATAAdress == OB_DATA_ADDRESS_DATA0)
+ {
+ /* Get value programmed in OB USER Data0 */
+ value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT;
+ }
+ else
+ {
+ /* Get value programmed in OB USER Data1 */
+ value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT;
+ }
+
+ return value;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASHEx_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Full erase of FLASH memory Bank
+ * @param Banks Banks to be erased
+ * This parameter can be one of the following values:
+ * @arg @ref FLASH_BANK_1 Bank1 to be erased
+ @if STM32F101xG
+ * @arg @ref FLASH_BANK_2 Bank2 to be erased
+ * @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased
+ @endif
+ @if STM32F103xG
+ * @arg @ref FLASH_BANK_2 Bank2 to be erased
+ * @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased
+ @endif
+ *
+ * @retval None
+ */
+static void FLASH_MassErase(uint32_t Banks)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_BANK(Banks));
+
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+#if defined(FLASH_BANK2_END)
+ if(Banks == FLASH_BANK_BOTH)
+ {
+ /* bank1 & bank2 will be erased*/
+ SET_BIT(FLASH->CR, FLASH_CR_MER);
+ SET_BIT(FLASH->CR2, FLASH_CR2_MER);
+ SET_BIT(FLASH->CR, FLASH_CR_STRT);
+ SET_BIT(FLASH->CR2, FLASH_CR2_STRT);
+ }
+ else if(Banks == FLASH_BANK_2)
+ {
+ /*Only bank2 will be erased*/
+ SET_BIT(FLASH->CR2, FLASH_CR2_MER);
+ SET_BIT(FLASH->CR2, FLASH_CR2_STRT);
+ }
+ else
+ {
+#endif /* FLASH_BANK2_END */
+ /* Only bank1 will be erased*/
+ SET_BIT(FLASH->CR, FLASH_CR_MER);
+ SET_BIT(FLASH->CR, FLASH_CR_STRT);
+#if defined(FLASH_BANK2_END)
+ }
+#endif /* FLASH_BANK2_END */
+}
+
+/**
+ * @brief Enable the write protection of the desired pages
+ * @note An option byte erase is done automatically in this function.
+ * @note When the memory read protection level is selected (RDP level = 1),
+ * it is not possible to program or erase the flash page i if
+ * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+ *
+ * @param WriteProtectPage specifies the page(s) to be write protected.
+ * The value of this parameter depend on device used within the same series
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint16_t WRP0_Data = 0xFFFF;
+#if defined(FLASH_WRP1_WRP1)
+ uint16_t WRP1_Data = 0xFFFF;
+#endif /* FLASH_WRP1_WRP1 */
+#if defined(FLASH_WRP2_WRP2)
+ uint16_t WRP2_Data = 0xFFFF;
+#endif /* FLASH_WRP2_WRP2 */
+#if defined(FLASH_WRP3_WRP3)
+ uint16_t WRP3_Data = 0xFFFF;
+#endif /* FLASH_WRP3_WRP3 */
+
+ /* Check the parameters */
+ assert_param(IS_OB_WRP(WriteProtectPage));
+
+ /* Get current write protected pages and the new pages to be protected ******/
+ WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage));
+
+#if defined(OB_WRP_PAGES0TO15MASK)
+ WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
+#elif defined(OB_WRP_PAGES0TO31MASK)
+ WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
+#endif /* OB_WRP_PAGES0TO31MASK */
+
+#if defined(OB_WRP_PAGES16TO31MASK)
+ WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8);
+#elif defined(OB_WRP_PAGES32TO63MASK)
+ WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8);
+#endif /* OB_WRP_PAGES32TO63MASK */
+
+#if defined(OB_WRP_PAGES64TO95MASK)
+ WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16);
+#endif /* OB_WRP_PAGES64TO95MASK */
+#if defined(OB_WRP_PAGES32TO47MASK)
+ WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16);
+#endif /* OB_WRP_PAGES32TO47MASK */
+
+#if defined(OB_WRP_PAGES96TO127MASK)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24);
+#elif defined(OB_WRP_PAGES48TO255MASK)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24);
+#elif defined(OB_WRP_PAGES48TO511MASK)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24);
+#elif defined(OB_WRP_PAGES48TO127MASK)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24);
+#endif /* OB_WRP_PAGES96TO127MASK */
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* To be able to write again option byte, need to perform a option byte erase */
+ status = HAL_FLASHEx_OBErase();
+ if (status == HAL_OK)
+ {
+ /* Enable write protection */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+
+#if defined(FLASH_WRP0_WRP0)
+ if(WRP0_Data != 0xFF)
+ {
+ OB->WRP0 &= WRP0_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* FLASH_WRP0_WRP0 */
+
+#if defined(FLASH_WRP1_WRP1)
+ if((status == HAL_OK) && (WRP1_Data != 0xFF))
+ {
+ OB->WRP1 &= WRP1_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* FLASH_WRP1_WRP1 */
+
+#if defined(FLASH_WRP2_WRP2)
+ if((status == HAL_OK) && (WRP2_Data != 0xFF))
+ {
+ OB->WRP2 &= WRP2_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* FLASH_WRP2_WRP2 */
+
+#if defined(FLASH_WRP3_WRP3)
+ if((status == HAL_OK) && (WRP3_Data != 0xFF))
+ {
+ OB->WRP3 &= WRP3_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* FLASH_WRP3_WRP3 */
+
+ /* if the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Disable the write protection of the desired pages
+ * @note An option byte erase is done automatically in this function.
+ * @note When the memory read protection level is selected (RDP level = 1),
+ * it is not possible to program or erase the flash page i if
+ * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+ *
+ * @param WriteProtectPage specifies the page(s) to be write unprotected.
+ * The value of this parameter depend on device used within the same series
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint16_t WRP0_Data = 0xFFFF;
+#if defined(FLASH_WRP1_WRP1)
+ uint16_t WRP1_Data = 0xFFFF;
+#endif /* FLASH_WRP1_WRP1 */
+#if defined(FLASH_WRP2_WRP2)
+ uint16_t WRP2_Data = 0xFFFF;
+#endif /* FLASH_WRP2_WRP2 */
+#if defined(FLASH_WRP3_WRP3)
+ uint16_t WRP3_Data = 0xFFFF;
+#endif /* FLASH_WRP3_WRP3 */
+
+ /* Check the parameters */
+ assert_param(IS_OB_WRP(WriteProtectPage));
+
+ /* Get current write protected pages and the new pages to be unprotected ******/
+ WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage);
+
+#if defined(OB_WRP_PAGES0TO15MASK)
+ WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
+#elif defined(OB_WRP_PAGES0TO31MASK)
+ WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
+#endif /* OB_WRP_PAGES0TO31MASK */
+
+#if defined(OB_WRP_PAGES16TO31MASK)
+ WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8);
+#elif defined(OB_WRP_PAGES32TO63MASK)
+ WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8);
+#endif /* OB_WRP_PAGES32TO63MASK */
+
+#if defined(OB_WRP_PAGES64TO95MASK)
+ WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16);
+#endif /* OB_WRP_PAGES64TO95MASK */
+#if defined(OB_WRP_PAGES32TO47MASK)
+ WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16);
+#endif /* OB_WRP_PAGES32TO47MASK */
+
+#if defined(OB_WRP_PAGES96TO127MASK)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24);
+#elif defined(OB_WRP_PAGES48TO255MASK)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24);
+#elif defined(OB_WRP_PAGES48TO511MASK)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24);
+#elif defined(OB_WRP_PAGES48TO127MASK)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24);
+#endif /* OB_WRP_PAGES96TO127MASK */
+
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* To be able to write again option byte, need to perform a option byte erase */
+ status = HAL_FLASHEx_OBErase();
+ if (status == HAL_OK)
+ {
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+
+#if defined(FLASH_WRP0_WRP0)
+ if(WRP0_Data != 0xFF)
+ {
+ OB->WRP0 |= WRP0_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* FLASH_WRP0_WRP0 */
+
+#if defined(FLASH_WRP1_WRP1)
+ if((status == HAL_OK) && (WRP1_Data != 0xFF))
+ {
+ OB->WRP1 |= WRP1_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* FLASH_WRP1_WRP1 */
+
+#if defined(FLASH_WRP2_WRP2)
+ if((status == HAL_OK) && (WRP2_Data != 0xFF))
+ {
+ OB->WRP2 |= WRP2_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* FLASH_WRP2_WRP2 */
+
+#if defined(FLASH_WRP3_WRP3)
+ if((status == HAL_OK) && (WRP3_Data != 0xFF))
+ {
+ OB->WRP3 |= WRP3_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* FLASH_WRP3_WRP3 */
+
+ /* if the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Set the read protection level.
+ * @param ReadProtectLevel specifies the read protection level.
+ * This parameter can be one of the following values:
+ * @arg @ref OB_RDP_LEVEL_0 No protection
+ * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* If the previous operation is completed, proceed to erase the option bytes */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTER);
+ SET_BIT(FLASH->CR, FLASH_CR_STRT);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the OPTER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
+
+ if(status == HAL_OK)
+ {
+ /* Enable the Option Bytes Programming operation */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+
+ WRITE_REG(OB->RDP, ReadProtectLevel);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* if the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Program the FLASH User Option Byte.
+ * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
+ * @param UserConfig The FLASH User Option Bytes values FLASH_OBR_IWDG_SW(Bit2),
+ * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4).
+ * And BFBF2(Bit5) for STM32F101xG and STM32F103xG .
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW)));
+ assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST)));
+ assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST)));
+#if defined(FLASH_BANK2_END)
+ assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET)));
+#endif /* FLASH_BANK2_END */
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Enable the Option Bytes Programming operation */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+
+#if defined(FLASH_BANK2_END)
+ OB->USER = (UserConfig | 0xF0);
+#else
+ OB->USER = (UserConfig | 0x88);
+#endif /* FLASH_BANK2_END */
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* if the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Programs a half word at a specified Option Byte Data address.
+ * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
+ * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
+ * (system reset will occur)
+ * Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
+ * @param Address specifies the address to be programmed.
+ * This parameter can be 0x1FFFF804 or 0x1FFFF806.
+ * @param Data specifies the data to be programmed.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_OB_DATA_ADDRESS(Address));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Enables the Option Bytes Programming operation */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ *(__IO uint16_t*)Address = Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
+ /* Return the Option Byte Data Program Status */
+ return status;
+}
+
+/**
+ * @brief Return the FLASH Write Protection Option Bytes value.
+ * @retval The FLASH Write Protection Option Bytes value
+ */
+static uint32_t FLASH_OB_GetWRP(void)
+{
+ /* Return the FLASH write protection Register value */
+ return (uint32_t)(READ_REG(FLASH->WRPR));
+}
+
+/**
+ * @brief Returns the FLASH Read Protection level.
+ * @retval FLASH ReadOut Protection Status:
+ * This parameter can be one of the following values:
+ * @arg @ref OB_RDP_LEVEL_0 No protection
+ * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
+ */
+static uint32_t FLASH_OB_GetRDP(void)
+{
+ uint32_t readstatus = OB_RDP_LEVEL_0;
+ uint32_t tmp_reg = 0;
+
+ /* Read RDP level bits */
+ tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT);
+
+ if (tmp_reg == FLASH_OBR_RDPRT)
+ {
+ readstatus = OB_RDP_LEVEL_1;
+ }
+ else
+ {
+ readstatus = OB_RDP_LEVEL_0;
+ }
+
+ return readstatus;
+}
+
+/**
+ * @brief Return the FLASH User Option Byte value.
+ * @retval The FLASH User Option Bytes values: FLASH_OBR_IWDG_SW(Bit2),
+ * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4).
+ * And FLASH_OBR_BFB2(Bit5) for STM32F101xG and STM32F103xG .
+ */
+static uint8_t FLASH_OB_GetUser(void)
+{
+ /* Return the User Option Byte */
+ return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Erase the specified FLASH memory page
+ * @param PageAddress FLASH page to erase
+ * The value of this parameter depend on device used within the same series
+ *
+ * @retval None
+ */
+void FLASH_PageErase(uint32_t PageAddress)
+{
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+#if defined(FLASH_BANK2_END)
+ if(PageAddress > FLASH_BANK1_END)
+ {
+ /* Proceed to erase the page */
+ SET_BIT(FLASH->CR2, FLASH_CR2_PER);
+ WRITE_REG(FLASH->AR2, PageAddress);
+ SET_BIT(FLASH->CR2, FLASH_CR2_STRT);
+ }
+ else
+ {
+#endif /* FLASH_BANK2_END */
+ /* Proceed to erase the page */
+ SET_BIT(FLASH->CR, FLASH_CR_PER);
+ WRITE_REG(FLASH->AR, PageAddress);
+ SET_BIT(FLASH->CR, FLASH_CR_STRT);
+#if defined(FLASH_BANK2_END)
+ }
+#endif /* FLASH_BANK2_END */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,597 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_gpio.c
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief GPIO HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the General Purpose Input/Output (GPIO) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### GPIO Peripheral features #####
+ ==============================================================================
+ [..]
+ Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
+ port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
+ in several modes:
+ (+) Input mode
+ (+) Analog mode
+ (+) Output mode
+ (+) Alternate function mode
+ (+) External interrupt/event lines
+
+ [..]
+ During and just after reset, the alternate functions and external interrupt
+ lines are not active and the I/O ports are configured in input floating mode.
+
+ [..]
+ All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+ activated or not.
+
+ [..]
+ In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+ type and the IO speed can be selected depending on the VDD value.
+
+ [..]
+ All ports have external interrupt/event capability. To use external interrupt
+ lines, the port must be configured in input mode. All available GPIO pins are
+ connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+
+ [..]
+ The external interrupt/event controller consists of up to 20 edge detectors in connectivity
+ line devices, or 19 edge detectors in other devices for generating event/interrupt requests.
+ Each input line can be independently configured to select the type (event or interrupt) and
+ the corresponding trigger event (rising or falling or both). Each line can also masked
+ independently. A pending register maintains the status line of the interrupt requests
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable the GPIO APB2 clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE().
+
+ (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+ (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
+ (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
+ structure.
+ (++) In case of Output or alternate function mode selection: the speed is
+ configured through "Speed" member from GPIO_InitTypeDef structure
+ (++) Analog mode is required when a pin is to be used as ADC channel
+ or DAC output.
+ (++) In case of external interrupt/event selection the "Mode" member from
+ GPIO_InitTypeDef structure select the type (interrupt or event) and
+ the corresponding trigger event (rising or falling or both).
+
+ (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
+ mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
+ HAL_NVIC_EnableIRQ().
+
+ (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
+
+ (#) To set/reset the level of a pin configured in output mode use
+ HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+
+ (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+
+ (#) During and just after reset, the alternate functions are not
+ active and the GPIO pins are configured in input floating mode (except JTAG
+ pins).
+
+ (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
+ (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
+ priority over the GPIO function.
+
+ (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
+ general purpose PD0 and PD1, respectively, when the HSE oscillator is off.
+ The HSE has priority over the GPIO function.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup GPIO GPIO
+ * @brief GPIO HAL module driver
+ * @{
+ */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Constants GPIO Private Constants
+ * @{
+ */
+
+#define GPIO_MODE ((uint32_t)0x00000003)
+#define EXTI_MODE ((uint32_t)0x10000000)
+#define GPIO_MODE_IT ((uint32_t)0x00010000)
+#define GPIO_MODE_EVT ((uint32_t)0x00020000)
+#define RISING_EDGE ((uint32_t)0x00100000)
+#define FALLING_EDGE ((uint32_t)0x00200000)
+#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
+#define GPIO_NUMBER ((uint32_t)16)
+
+/* Definitions for bit manipulation of CRL and CRH register */
+#define GPIO_CR_MODE_INPUT ((uint32_t)0x00000000) /*!< 00: Input mode (reset state) */
+#define GPIO_CR_CNF_ANALOG ((uint32_t)0x00000000) /*!< 00: Analog mode */
+#define GPIO_CR_CNF_INPUT_FLOATING ((uint32_t)0x00000004) /*!< 01: Floating input (reset state) */
+#define GPIO_CR_CNF_INPUT_PU_PD ((uint32_t)0x00000008) /*!< 10: Input with pull-up / pull-down */
+#define GPIO_CR_CNF_GP_OUTPUT_PP ((uint32_t)0x00000000) /*!< 00: General purpose output push-pull */
+#define GPIO_CR_CNF_GP_OUTPUT_OD ((uint32_t)0x00000004) /*!< 01: General purpose output Open-drain */
+#define GPIO_CR_CNF_AF_OUTPUT_PP ((uint32_t)0x00000008) /*!< 10: Alternate function output Push-pull */
+#define GPIO_CR_CNF_AF_OUTPUT_OD ((uint32_t)0x0000000C) /*!< 11: Alternate function output Open-drain */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
+ * @{
+ */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization and deinitialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and deinitialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to initialize and de-initialize the GPIOs
+ to be ready for use.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+ * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
+ * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
+ * the configuration information for the specified GPIO peripheral.
+ * @retval None
+ */
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+ uint32_t position;
+ uint32_t ioposition = 0x00;
+ uint32_t iocurrent = 0x00;
+ uint32_t temp = 0x00;
+ uint32_t config = 0x00;
+ __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
+ uint32_t registeroffset = 0; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+ assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+
+ /* Configure the port pins */
+ for (position = 0; position < GPIO_NUMBER; position++)
+ {
+ /* Get the IO position */
+ ioposition = ((uint32_t)0x01) << position;
+
+ /* Get the current IO position */
+ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
+
+ if (iocurrent == ioposition)
+ {
+ /* Check the Alternate function parameters */
+ assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+
+ /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
+ switch (GPIO_Init->Mode)
+ {
+ /* If we are configuring the pin in OUTPUT push-pull mode */
+ case GPIO_MODE_OUTPUT_PP:
+ /* Check the GPIO speed parameter */
+ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+ config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
+ break;
+
+ /* If we are configuring the pin in OUTPUT open-drain mode */
+ case GPIO_MODE_OUTPUT_OD:
+ /* Check the GPIO speed parameter */
+ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+ config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
+ break;
+
+ /* If we are configuring the pin in ALTERNATE FUNCTION push-pull mode */
+ case GPIO_MODE_AF_PP:
+ /* Check the GPIO speed parameter */
+ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+ config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
+ break;
+
+ /* If we are configuring the pin in ALTERNATE FUNCTION open-drain mode */
+ case GPIO_MODE_AF_OD:
+ /* Check the GPIO speed parameter */
+ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+ config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
+ break;
+
+ /* If we are configuring the pin in INPUT (also applicable to EVENT and IT mode) */
+ case GPIO_MODE_INPUT:
+ case GPIO_MODE_IT_RISING:
+ case GPIO_MODE_IT_FALLING:
+ case GPIO_MODE_IT_RISING_FALLING:
+ case GPIO_MODE_EVT_RISING:
+ case GPIO_MODE_EVT_FALLING:
+ case GPIO_MODE_EVT_RISING_FALLING:
+ /* Check the GPIO pull parameter */
+ assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+ if(GPIO_Init->Pull == GPIO_NOPULL)
+ {
+ config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
+ }
+ else if(GPIO_Init->Pull == GPIO_PULLUP)
+ {
+ config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
+
+ /* Set the corresponding ODR bit */
+ GPIOx->BSRR = ioposition;
+ }
+ else /* GPIO_PULLDOWN */
+ {
+ config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
+
+ /* Reset the corresponding ODR bit */
+ GPIOx->BRR = ioposition;
+ }
+ break;
+
+ /* If we are configuring the pin in INPUT analog mode */
+ case GPIO_MODE_ANALOG:
+ config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
+ break;
+
+ /* Parameters are checked with assert_param */
+ default:
+ break;
+ }
+
+ /* Check if the current bit belongs to first half or last half of the pin count number
+ in order to address CRH or CRL register*/
+ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
+ registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2) : ((position - 8) << 2);
+
+ /* Apply the new configuration of the pin to the register */
+ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), (config << registeroffset));
+
+ /*--------------------- EXTI Mode Configuration ------------------------*/
+ /* Configure the External Interrupt or event for the current IO */
+ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+ {
+ /* Enable AFIO Clock */
+ __HAL_RCC_AFIO_CLK_ENABLE();
+ temp = AFIO->EXTICR[position >> 2];
+ CLEAR_BIT(temp, ((uint32_t)0x0F) << (4 * (position & 0x03)));
+ SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
+ AFIO->EXTICR[position >> 2] = temp;
+
+
+ /* Configure the interrupt mask */
+ if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+ {
+ SET_BIT(EXTI->IMR, iocurrent);
+ }
+ else
+ {
+ CLEAR_BIT(EXTI->IMR, iocurrent);
+ }
+
+ /* Configure the event mask */
+ if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+ {
+ SET_BIT(EXTI->EMR, iocurrent);
+ }
+ else
+ {
+ CLEAR_BIT(EXTI->EMR, iocurrent);
+ }
+
+ /* Enable or disable the rising trigger */
+ if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+ {
+ SET_BIT(EXTI->RTSR, iocurrent);
+ }
+ else
+ {
+ CLEAR_BIT(EXTI->RTSR, iocurrent);
+ }
+
+ /* Enable or disable the falling trigger */
+ if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+ {
+ SET_BIT(EXTI->FTSR, iocurrent);
+ }
+ else
+ {
+ CLEAR_BIT(EXTI->FTSR, iocurrent);
+ }
+ }
+ }
+ }
+}
+
+/**
+ * @brief De-initializes the GPIOx peripheral registers to their default reset values.
+ * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be one of GPIO_PIN_x where x can be (0..15).
+ * @retval None
+ */
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+ uint32_t position = 0x00;
+ uint32_t iocurrent = 0x00;
+ uint32_t tmp = 0x00;
+ __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
+ uint32_t registeroffset = 0;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* Configure the port pins */
+ while ((GPIO_Pin >> position) != 0)
+ {
+ /* Get current io position */
+ iocurrent = (GPIO_Pin) & ((uint32_t)1 << position);
+
+ if (iocurrent)
+ {
+ /*------------------------- GPIO Mode Configuration --------------------*/
+ /* Check if the current bit belongs to first half or last half of the pin count number
+ in order to address CRH or CRL register */
+ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
+ registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2) : ((position - 8) << 2);
+
+ /* CRL/CRH default value is floating input(0x04) shifted to correct position */
+ MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), GPIO_CRL_CNF0_0 << registeroffset);
+
+ /* ODR default value is 0 */
+ CLEAR_BIT(GPIOx->ODR, iocurrent);
+
+ /*------------------------- EXTI Mode Configuration --------------------*/
+ /* Clear the External Interrupt or Event for the current IO */
+
+ tmp = AFIO->EXTICR[position >> 2];
+ tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
+ if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))
+ {
+ tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
+ CLEAR_BIT(AFIO->EXTICR[position >> 2], tmp);
+
+ /* Clear EXTI line configuration */
+ CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent);
+ CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent);
+
+ /* Clear Rising Falling edge configuration */
+ CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent);
+ CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent);
+ }
+ }
+
+ position++;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
+ * @brief GPIO Read and Write
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the GPIOs.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Reads the specified input port pin.
+ * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
+ * @param GPIO_Pin: specifies the port bit to read.
+ * This parameter can be GPIO_PIN_x where x can be (0..15).
+ * @retval The input port pin value.
+ */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ GPIO_PinState bitstatus;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
+ {
+ bitstatus = GPIO_PIN_SET;
+ }
+ else
+ {
+ bitstatus = GPIO_PIN_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Sets or clears the selected data port bit.
+ *
+ * @note This function uses GPIOx_BSRR register to allow atomic read/modify
+ * accesses. In this way, there is no risk of an IRQ occurring between
+ * the read and the modify access.
+ *
+ * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be one of GPIO_PIN_x where x can be (0..15).
+ * @param PinState: specifies the value to be written to the selected bit.
+ * This parameter can be one of the GPIO_PinState enum values:
+ * @arg GPIO_BIT_RESET: to clear the port pin
+ * @arg GPIO_BIT_SET: to set the port pin
+ * @retval None
+ */
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+ assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+ if(PinState != GPIO_PIN_RESET)
+ {
+ GPIOx->BSRR = GPIO_Pin;
+ }
+ else
+ {
+ GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
+ }
+}
+
+/**
+ * @brief Toggles the specified GPIO pin
+ * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
+ * @param GPIO_Pin: Specifies the pins to be toggled.
+ * @retval None
+ */
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ GPIOx->ODR ^= GPIO_Pin;
+}
+
+/**
+* @brief Locks GPIO Pins configuration registers.
+* @note The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence
+* has been applied on a port bit, it is no longer possible to modify the value of the port bit until
+* the next reset.
+* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
+* @param GPIO_Pin: specifies the port bit to be locked.
+* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+* @retval None
+*/
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* Apply lock key write sequence */
+ SET_BIT(tmp, GPIO_Pin);
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ GPIOx->LCKR = tmp;
+ /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+ GPIOx->LCKR = GPIO_Pin;
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ GPIOx->LCKR = tmp;
+ /* Read LCKK bit*/
+ tmp = GPIOx->LCKR;
+
+ if((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK))
+ {
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief This function handles EXTI interrupt request.
+ * @param GPIO_Pin: Specifies the pins connected EXTI line
+ * @retval None
+ */
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+{
+ /* EXTI line interrupt detected */
+ if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
+ {
+ __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
+ HAL_GPIO_EXTI_Callback(GPIO_Pin);
+ }
+}
+
+/**
+ * @brief EXTI line detection callback
+ * @param GPIO_Pin: Specifies the pins connected EXTI line
+ * @retval None
+ */
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(GPIO_Pin);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_GPIO_EXTI_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,145 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_gpio_ex.c
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief GPIO Extension HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the General Purpose Input/Output (GPIO) extension peripheral.
+ * + Extended features functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### GPIO Peripheral extension features #####
+ ==============================================================================
+ [..] GPIO module on STM32F1 family, manage also the AFIO register:
+ (+) Possibility to use the EVENTOUT Cortex feature
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to use EVENTOUT Cortex feature
+ (#) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()
+ (#) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()
+ (#) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup GPIOEx GPIOEx
+ * @brief GPIO HAL module driver
+ * @{
+ */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/** @defgroup GPIOEx_Exported_Functions GPIOEx Exported Functions
+ * @{
+ */
+
+/** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions
+ * @brief Extended features functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Extended features functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()
+ (+) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()
+ (+) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
+ * @param GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal.
+ * This parameter can be a value of @ref GPIOEx_EVENTOUT_PORT.
+ * @param GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal.
+ * This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN.
+ * @retval None
+ */
+void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource)
+{
+ /* Verify the parameters */
+ assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource));
+ assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource));
+
+ /* Apply the new configuration */
+ MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT)|(AFIO_EVCR_PIN), (GPIO_PortSource)|(GPIO_PinSource));
+}
+
+/**
+ * @brief Enables the Event Output.
+ * @retval None
+ */
+void HAL_GPIOEx_EnableEventout(void)
+{
+ SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
+}
+
+/**
+ * @brief Disables the Event Output.
+ * @retval None
+ */
+void HAL_GPIOEx_DisableEventout(void)
+{
+ CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1270 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_rcc.c
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief RCC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Reset and Clock Control (RCC) peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### RCC specific features #####
+ ==============================================================================
+ [..]
+ After reset the device is running from Internal High Speed oscillator
+ (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
+ and all peripherals are off except internal SRAM, Flash and JTAG.
+ (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
+ all peripherals mapped on these buses are running at HSI speed.
+ (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
+ (+) All GPIOs are in input floating state, except the JTAG pins which
+ are assigned to be used for debug purpose.
+ [..] Once the device started from reset, the user application has to:
+ (+) Configure the clock source to be used to drive the System clock
+ (if the application needs higher frequency/performance)
+ (+) Configure the System clock frequency and Flash settings
+ (+) Configure the AHB and APB buses prescalers
+ (+) Enable the clock for the peripheral(s) to be used
+ (+) Configure the clock source(s) for peripherals whose clocks are not
+ derived from the System clock (I2S, RTC, ADC, USB OTG FS)
+
+ ##### RCC Limitations #####
+ ==============================================================================
+ [..]
+ A delay between an RCC peripheral clock enable and the effective peripheral
+ enabling should be taken into account in order to manage the peripheral read/write
+ from/to registers.
+ (+) This delay depends on the peripheral mapping.
+ (++) AHB & APB peripherals, 1 dummy read is necessary
+
+ [..]
+ Workarounds:
+ (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+ inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RCC RCC
+* @brief RCC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+ * @{
+ */
+/* Bits position in in the CFGR register */
+#define RCC_CFGR_HPRE_BITNUMBER POSITION_VAL(RCC_CFGR_HPRE)
+#define RCC_CFGR_PPRE1_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE1)
+#define RCC_CFGR_PPRE2_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE2)
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup RCC_Private_Macros RCC Private Macros
+ * @{
+ */
+
+#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
+#define MCO1_GPIO_PORT GPIOA
+#define MCO1_PIN GPIO_PIN_8
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Variables RCC Private Variables
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Functions RCC Exported Functions
+ * @{
+ */
+
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to configure the internal/external oscillators
+ (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
+ and APB2).
+
+ [..] Internal/external clock and PLL configuration
+ (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
+ the PLL as System clock source.
+ (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
+ clock source.
+
+ (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x) crystal oscillator used directly or
+ through the PLL as System clock source. Can be used also as RTC clock source.
+
+ (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
+
+ (#) PLL (clocked by HSI or HSE), featuring different output clocks:
+ (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx)
+ (++) The second output is used to generate the clock for the USB OTG FS (48 MHz)
+
+ (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
+ and if a HSE clock failure occurs(HSE used directly or through PLL as System
+ clock source), the System clocks automatically switched to HSI and an interrupt
+ is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
+ (Non-Maskable Interrupt) exception vector.
+
+ (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,
+ HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x
+
+ [..] System, AHB and APB buses clocks configuration
+ (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
+ HSE and PLL.
+ The AHB clock (HCLK) is derived from System clock through configurable
+ prescaler and used to clock the CPU, memory and peripherals mapped
+ on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
+ from AHB clock through configurable prescalers and used to clock
+ the peripherals mapped on these buses. You can use
+ "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
+
+ -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
+ (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
+ divided by 128.
+ (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz
+ to work correctly. This clock is derived of the main PLL through PLL Multiplier.
+ (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK
+ (+@) IWDG clock which is always the LSI clock.
+
+ (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz.
+ For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz.
+ Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.
+ @endverbatim
+ * @{
+ */
+
+/*
+ Additional consideration on the SYSCLK based on Latency settings:
+ +-----------------------------------------------+
+ | Latency | SYSCLK clock frequency (MHz) |
+ |---------------|-------------------------------|
+ |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
+ |---------------|-------------------------------|
+ |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
+ |---------------|-------------------------------|
+ |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
+ +-----------------------------------------------+
+ */
+
+/**
+ * @brief Resets the RCC clock configuration to the default reset state.
+ * @note The default reset state of the clock configuration is given below:
+ * - HSI ON and used as system clock source
+ * - HSE and PLL OFF
+ * - AHB, APB1 and APB2 prescaler set to 1.
+ * - CSS and MCO1 OFF
+ * - All interrupts disabled
+ * @note This function does not modify the configuration of the
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
+ * @retval None
+ */
+void HAL_RCC_DeInit(void)
+{
+ /* Switch SYSCLK to HSI */
+ CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
+
+ /* Reset HSEON, CSSON, & PLLON bits */
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
+
+ /* Reset HSEBYP bit */
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+
+ /* Reset CFGR register */
+ CLEAR_REG(RCC->CFGR);
+
+ /* Set HSITRIM bits to the reset value */
+ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_CR_HSITRIM)));
+
+#if (defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE))
+ /* Reset CFGR2 register */
+ CLEAR_REG(RCC->CFGR2);
+
+#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
+ /* Disable all interrupts */
+ CLEAR_REG(RCC->CIR);
+
+ /* Update the SystemCoreClock global variable */
+ SystemCoreClock = HSI_VALUE;
+}
+
+/**
+ * @brief Initializes the RCC Oscillators according to the specified parameters in the
+ * RCC_OscInitTypeDef.
+ * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC Oscillators.
+ * @note The PLL is not disabled when used as system clock.
+ * @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)
+ * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+ * supported by this macro. User should request a transition to LSE Off
+ * first and then LSE On or LSE Bypass.
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+ * supported by this macro. User should request a transition to HSE Off
+ * first and then HSE On or HSE Bypass.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(RCC_OscInitStruct != NULL);
+ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+
+ /*------------------------------- HSE Configuration ------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+
+ /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
+ {
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Set the new HSE configuration ---------------------------------------*/
+ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+
+
+ /* Check the HSE State */
+ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+ {
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*----------------------------- HSI Configuration --------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+ assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+ /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
+ {
+ /* When HSI is used as system clock it will not disabled */
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+ {
+ return HAL_ERROR;
+ }
+ /* Otherwise, just the calibration is allowed */
+ else
+ {
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ }
+ }
+ else
+ {
+ /* Check the HSI State */
+ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
+ {
+ /* Enable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_ENABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ }
+ else
+ {
+ /* Disable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_DISABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*------------------------------ LSI Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+ /* Check the LSI State */
+ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
+ {
+ /* Enable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_ENABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* To have a fully stabilized clock in the specified range, a software delay of 1ms
+ should be added.*/
+ HAL_Delay(1);
+ }
+ else
+ {
+ /* Disable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_DISABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /*------------------------------ LSE Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set the new LSE configuration -----------------------------------------*/
+ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+ /* Check the LSE State */
+ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
+ {
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+#if defined(RCC_CR_PLL2ON)
+ /*-------------------------------- PLL2 Configuration -----------------------*/
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State));
+ if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE)
+ {
+ /* This bit can not be cleared if the PLL2 clock is used indirectly as system
+ clock (i.e. it is used as PLL clock entry that is used as system clock). */
+ if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
+ (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
+ ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ if((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL));
+ assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value));
+
+ /* Prediv2 can be written only when the PLLI2S is disabled. */
+ /* Return an error only if new value is different from the programmed value */
+ if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
+ (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable the main PLL2. */
+ __HAL_RCC_PLL2_DISABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL2 is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the HSE prediv2 factor --------------------------------*/
+ __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value);
+
+ /* Configure the main PLL2 multiplication factors. */
+ __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL);
+
+ /* Enable the main PLL2. */
+ __HAL_RCC_PLL2_ENABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL2 is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Set PREDIV1 source to HSE */
+ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
+
+ /* Disable the main PLL2. */
+ __HAL_RCC_PLL2_DISABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL2 is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+
+#endif /* RCC_CR_PLL2ON */
+ /*-------------------------------- PLL Configuration -----------------------*/
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+ if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+ {
+ /* Check if the PLL is used as system clock or not */
+ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ {
+ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+ assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
+
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the HSE prediv factor --------------------------------*/
+ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
+ if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
+ {
+ /* Check the parameter */
+ assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
+#if defined(RCC_CFGR2_PREDIV1SRC)
+ assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source));
+
+ /* Set PREDIV1 source */
+ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
+#endif /* RCC_CFGR2_PREDIV1SRC */
+
+ /* Set PREDIV1 Value */
+ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
+ }
+
+ /* Configure the main PLL clock source and multiplication factors. */
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ RCC_OscInitStruct->PLL.PLLMUL);
+ /* Enable the main PLL. */
+ __HAL_RCC_PLL_ENABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CPU, AHB and APB buses clocks according to the specified
+ * parameters in the RCC_ClkInitStruct.
+ * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC peripheral.
+ * @param FLatency FLASH Latency
+ * The value of this parameter depend on device used within the same series
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
+ *
+ * @note The HSI is used (enabled by hardware) as system clock source after
+ * start-up from Reset, wake-up from STOP and STANDBY mode, or in case
+ * of failure of the HSE used directly or indirectly as system clock
+ * (if the Clock Security System CSS is enabled).
+ *
+ * @note A switch from one clock source to another occurs only if the target
+ * clock source is ready (clock stable after start-up delay or PLL locked).
+ * If a clock source which is not yet ready is selected, the switch will
+ * occur when the clock source will be ready.
+ * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
+ * currently used as system clock source.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(RCC_ClkInitStruct != NULL);
+ assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
+ assert_param(IS_FLASH_LATENCY(FLatency));
+
+ /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+ must be correctly programmed according to the frequency of the CPU clock
+ (HCLK) of the device. */
+
+#if defined(FLASH_ACR_LATENCY)
+ /* Increasing the number of wait states because of higher CPU frequency */
+ if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+#endif /* FLASH_ACR_LATENCY */
+ /*-------------------------- HCLK Configuration --------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ {
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ }
+
+ /*------------------------- SYSCLK Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ {
+ assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+
+ /* HSE is selected as System Clock Source */
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ /* Check the HSE ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* PLL is selected as System Clock Source */
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ /* Check the PLL ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* HSI is selected as System Clock Source */
+ else
+ {
+ /* Check the HSI ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+#if defined(FLASH_ACR_LATENCY)
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ {
+ return HAL_ERROR;
+ }
+ }
+#endif /* FLASH_ACR_LATENCY */
+
+ /*-------------------------- PCLK1 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ {
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
+ }
+
+ /*-------------------------- PCLK2 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ {
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
+ }
+
+ /* Update the SystemCoreClock global variable */
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
+
+ /* Configure the source of time base considering new system clocks settings*/
+ HAL_InitTick (TICK_INT_PRIORITY);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief RCC clocks control functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the RCC Clocks
+ frequencies.
+
+ @endverbatim
+ * @{
+ */
+
+/**
+ * @brief Selects the clock source to output on MCO pin.
+ * @note MCO pin should be configured in alternate function mode.
+ * @param RCC_MCOx specifies the output direction for the clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
+ * @param RCC_MCOSource specifies the clock source to output.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
+ @if STM32F105xC
+ * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source
+ @endif
+ @if STM32F107xC
+ * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source
+ @endif
+ * @param RCC_MCODiv specifies the MCO DIV.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCODIV_1 no division applied to MCO clock
+ * @retval None
+ */
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
+{
+ GPIO_InitTypeDef gpio = {0};
+
+ /* Check the parameters */
+ assert_param(IS_RCC_MCO(RCC_MCOx));
+ assert_param(IS_RCC_MCODIV(RCC_MCODiv));
+ assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
+
+ /* Configure the MCO1 pin in alternate function mode */
+ gpio.Mode = GPIO_MODE_AF_PP;
+ gpio.Speed = GPIO_SPEED_FREQ_HIGH;
+ gpio.Pull = GPIO_NOPULL;
+ gpio.Pin = MCO1_PIN;
+
+ /* MCO1 Clock Enable */
+ MCO1_CLK_ENABLE();
+
+ HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
+
+ /* Configure the MCO clock source */
+ __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
+}
+
+/**
+ * @brief Enables the Clock Security System.
+ * @note If a failure is detected on the HSE oscillator clock, this oscillator
+ * is automatically disabled and an interrupt is generated to inform the
+ * software about the failure (Clock Security System Interrupt, CSSI),
+ * allowing the MCU to perform rescue operations. The CSSI is linked to
+ * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
+ * @retval None
+ */
+void HAL_RCC_EnableCSS(void)
+{
+ *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief Disables the Clock Security System.
+ * @retval None
+ */
+void HAL_RCC_DisableCSS(void)
+{
+ *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
+}
+
+/**
+ * @brief Returns the SYSCLK frequency
+ * @note The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+ * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE
+ * divided by PREDIV factor(**)
+ * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE
+ * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
+ * @note (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ * @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * @note The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @note This function can be used by the user application to compute the
+ * baud-rate for the communication peripherals or configure other parameters.
+ *
+ * @note Each time SYSCLK changes, this function must be called to update the
+ * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+ *
+ * @retval SYSCLK frequency
+ */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+#if defined(RCC_CFGR2_PREDIV1SRC)
+ const uint8_t aPLLMULFactorTable[12] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 13};
+ const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
+#else
+ const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
+#if defined(RCC_CFGR2_PREDIV1)
+ const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
+#else
+ const uint8_t aPredivFactorTable[2] = { 1, 2};
+#endif /*RCC_CFGR2_PREDIV1*/
+
+#endif
+ uint32_t tmpreg = 0, prediv = 0, pllclk = 0, pllmul = 0;
+ uint32_t sysclockfreq = 0;
+#if defined(RCC_CFGR2_PREDIV1SRC)
+ uint32_t prediv2 = 0, pll2mul = 0;
+#endif /*RCC_CFGR2_PREDIV1SRC*/
+
+ tmpreg = RCC->CFGR;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (tmpreg & RCC_CFGR_SWS)
+ {
+ case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
+ {
+ sysclockfreq = HSE_VALUE;
+ break;
+ }
+ case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
+ {
+ pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)];
+ if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
+ {
+#if defined(RCC_CFGR2_PREDIV1)
+ prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> POSITION_VAL(RCC_CFGR2_PREDIV1)];
+#else
+ prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> POSITION_VAL(RCC_CFGR_PLLXTPRE)];
+#endif /*RCC_CFGR2_PREDIV1*/
+#if defined(RCC_CFGR2_PREDIV1SRC)
+
+ if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
+ {
+ /* PLL2 selected as Prediv1 source */
+ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
+ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
+ pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> POSITION_VAL(RCC_CFGR2_PLL2MUL)) + 2;
+ pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv) * pllmul);
+ }
+ else
+ {
+ /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
+ pllclk = (uint32_t)((HSE_VALUE / prediv) * pllmul);
+ }
+
+ /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
+ /* In this case need to divide pllclk by 2 */
+ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)])
+ {
+ pllclk = pllclk / 2;
+ }
+#else
+ /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
+ pllclk = (uint32_t)((HSE_VALUE / prediv) * pllmul);
+#endif /*RCC_CFGR2_PREDIV1SRC*/
+ }
+ else
+ {
+ /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
+ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
+ }
+ sysclockfreq = pllclk;
+ break;
+ }
+ case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
+ default: /* HSI used as system clock */
+ {
+ sysclockfreq = HSI_VALUE;
+ break;
+ }
+ }
+ return sysclockfreq;
+}
+
+/**
+ * @brief Returns the HCLK frequency
+ * @note Each time HCLK changes, this function must be called to update the
+ * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
+ *
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ * and updated within this function
+ * @retval HCLK frequency
+ */
+uint32_t HAL_RCC_GetHCLKFreq(void)
+{
+ return SystemCoreClock;
+}
+
+/**
+ * @brief Returns the PCLK1 frequency
+ * @note Each time PCLK1 changes, this function must be called to update the
+ * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval PCLK1 frequency
+ */
+uint32_t HAL_RCC_GetPCLK1Freq(void)
+{
+ /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]);
+}
+
+/**
+ * @brief Returns the PCLK2 frequency
+ * @note Each time PCLK2 changes, this function must be called to update the
+ * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval PCLK2 frequency
+ */
+uint32_t HAL_RCC_GetPCLK2Freq(void)
+{
+ /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
+ return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]);
+}
+
+/**
+ * @brief Configures the RCC_OscInitStruct according to the internal
+ * RCC configuration registers.
+ * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+ * will be configured.
+ * @retval None
+ */
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ /* Check the parameters */
+ assert_param(RCC_OscInitStruct != NULL);
+
+ /* Set all possible values for the Oscillator type parameter ---------------*/
+ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \
+ | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
+
+#if defined(RCC_CFGR2_PREDIV1SRC)
+ /* Get the Prediv1 source --------------------------------------------------*/
+ RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC);
+#endif /* RCC_CFGR2_PREDIV1SRC */
+
+ /* Get the HSE configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+ }
+ else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+ }
+ RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
+
+ /* Get the HSI configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
+ {
+ RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+ }
+
+ RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
+
+ /* Get the LSE configuration -----------------------------------------------*/
+ if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+ }
+ else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+ }
+
+ /* Get the LSI configuration -----------------------------------------------*/
+ if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
+ {
+ RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+ }
+
+
+ /* Get the PLL configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
+ {
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+ }
+ RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
+ RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);
+#if defined(RCC_CR_PLL2ON)
+ /* Get the PLL2 configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_PLL2ON) == RCC_CR_PLL2ON)
+ {
+ RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF;
+ }
+ RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2();
+ RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL);
+#endif /* RCC_CR_PLL2ON */
+}
+
+/**
+ * @brief Get the RCC_ClkInitStruct according to the internal
+ * RCC configuration registers.
+ * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
+ * contains the current clock configuration.
+ * @param pFLatency Pointer on the Flash Latency.
+ * @retval None
+ */
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
+{
+ /* Check the parameters */
+ assert_param(RCC_ClkInitStruct != NULL);
+ assert_param(pFLatency != NULL);
+
+ /* Set all possible values for the Clock type parameter --------------------*/
+ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+
+ /* Get the SYSCLK configuration --------------------------------------------*/
+ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
+
+ /* Get the HCLK configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
+
+ /* Get the APB1 configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
+
+ /* Get the APB2 configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
+
+#if defined(FLASH_ACR_LATENCY)
+ /* Get the Flash Wait State (Latency) configuration ------------------------*/
+ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
+#else
+ /* For VALUE lines devices, only LATENCY_0 can be set*/
+ *pFLatency = (uint32_t)FLASH_LATENCY_0;
+#endif
+}
+
+/**
+ * @brief This function handles the RCC CSS interrupt request.
+ * @note This API should be called under the NMI_Handler().
+ * @retval None
+ */
+void HAL_RCC_NMI_IRQHandler(void)
+{
+ /* Check RCC CSSF flag */
+ if(__HAL_RCC_GET_IT(RCC_IT_CSS))
+ {
+ /* RCC Clock Security System interrupt user callback */
+ HAL_RCC_CSSCallback();
+
+ /* Clear RCC CSS pending bit */
+ __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
+ }
+}
+
+/**
+ * @brief RCC Clock Security System interrupt callback
+ * @retval none
+ */
+__weak void HAL_RCC_CSSCallback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RCC_CSSCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,870 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_rcc_ex.c
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief Extended RCC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities RCC extension peripheral:
+ * + Extended Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/** @defgroup RCCEx RCCEx
+ * @brief RCC Extension HAL module driver.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
+ * @{
+ */
+
+/** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the RCC Clocks
+ frequencies.
+ [..]
+ (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
+ select the RTC clock source; in this case the Backup domain will be reset in
+ order to modify the RTC Clock source, as consequence RTC registers (including
+ the backup registers) are set to their reset values.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
+ * RCC_PeriphCLKInitTypeDef.
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * contains the configuration information for the Extended Peripherals clocks(RTC clock).
+ *
+ * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+ * the RTC clock source; in this case the Backup domain will be reset in
+ * order to modify the RTC Clock source, as consequence RTC registers (including
+ * the backup registers) are set to their reset values.
+ *
+ * @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on
+ * one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to
+ * manually disable it.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tickstart = 0, temp_reg = 0;
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ uint32_t pllactive = 0;
+#endif /* STM32F105xC || STM32F107xC */
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+ /*------------------------------- RTC/LCD Configuration ------------------------*/
+ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
+ {
+ /* check for RTC Parameters used to output RTCCLK */
+ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
+ if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+ {
+ /* Store the content of BDCR register before the reset of Backup Domain */
+ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+ /* Restore the Content of BDCR register */
+ RCC->BDCR = temp_reg;
+
+ /* Wait for LSERDY if LSE was enabled */
+ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
+ {
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+ }
+
+ /*------------------------------ ADC clock Configuration ------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
+
+ /* Configure the ADC clock source */
+ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
+ }
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ /*------------------------------ I2S2 Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection));
+
+ /* Configure the I2S2 clock source */
+ __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection);
+ }
+
+ /*------------------------------ I2S3 Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection));
+
+ /* Configure the I2S3 clock source */
+ __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection);
+ }
+
+ /*------------------------------ PLL I2S Configuration ----------------------*/
+ /* Check that PLLI2S need to be enabled */
+ if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
+ {
+ /* Update flag to indicate that PLL I2S should be active */
+ pllactive = 1;
+ }
+
+ /* Check if PLL I2S need to be enabled */
+ if (pllactive == 1)
+ {
+ /* Enable PLL I2S only if not active */
+ if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON))
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL));
+ assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value));
+
+ /* Prediv2 can be written only when the PLL2 is disabled. */
+ /* Return an error only if new value is different from the programmed value */
+ if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \
+ (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Configure the HSE prediv2 factor --------------------------------*/
+ __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value);
+
+ /* Configure the main PLLI2S multiplication factors. */
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL);
+
+ /* Enable the main PLLI2S. */
+ __HAL_RCC_PLLI2S_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLLI2S is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */
+ if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL)
+ {
+ return HAL_ERROR;
+ }
+ }
+ }
+#endif /* STM32F105xC || STM32F107xC */
+
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
+ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
+ || defined(STM32F105xC) || defined(STM32F107xC)
+ /*------------------------------ USB clock Configuration ------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
+
+ /* Configure the USB clock source */
+ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
+ }
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the PeriphClkInit according to the internal
+ * RCC configuration registers.
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks).
+ * @retval None
+ */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t srcclk = 0;
+
+ /* Set all possible values for the extended clock type parameter------------*/
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
+
+ /* Get the RTC configuration -----------------------------------------------*/
+ srcclk = __HAL_RCC_GET_RTC_SOURCE();
+ /* Source clock is LSE or LSI*/
+ PeriphClkInit->RTCClockSelection = srcclk;
+
+ /* Get the ADC clock configuration -----------------------------------------*/
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC;
+ PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ /* Get the I2S2 clock configuration -----------------------------------------*/
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
+ PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE();
+
+ /* Get the I2S3 clock configuration -----------------------------------------*/
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
+ PeriphClkInit->I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE();
+
+#endif /* STM32F105xC || STM32F107xC */
+
+#if defined(STM32F103xE) || defined(STM32F103xG)
+ /* Get the I2S2 clock configuration -----------------------------------------*/
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
+ PeriphClkInit->I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK;
+
+ /* Get the I2S3 clock configuration -----------------------------------------*/
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
+ PeriphClkInit->I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK;
+
+#endif /* STM32F103xE || STM32F103xG */
+
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
+ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
+ || defined(STM32F105xC) || defined(STM32F107xC)
+ /* Get the USB clock configuration -----------------------------------------*/
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
+ PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+}
+
+/**
+ * @brief Returns the peripheral clock frequency
+ * @note Returns 0 if peripheral clock is unknown
+ * @param PeriphClk Peripheral clock identifier
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock
+ @if STM32F103xE
+ * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
+ @endif
+ @if STM32F103xG
+ * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
+ @endif
+ @if STM32F105xC
+ * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
+ @endif
+ @if STM32F107xC
+ * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
+ @endif
+ @if STM32F102xx
+ * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
+ @endif
+ @if STM32F103xx
+ * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
+ @endif
+ * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
+ */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
+ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
+ || defined(STM32F105xC) || defined(STM32F107xC)
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ const uint8_t aPLLMULFactorTable[12] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 13};
+ const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
+#else
+ const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
+ const uint8_t aPredivFactorTable[2] = { 1, 2};
+#endif
+#endif
+ uint32_t temp_reg = 0, frequency = 0;
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
+ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
+ || defined(STM32F105xC) || defined(STM32F107xC)
+ uint32_t prediv1 = 0, pllclk = 0, pllmul = 0;
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ uint32_t pll2mul = 0, pll3mul = 0, prediv2 = 0;
+#endif /* STM32F105xC || STM32F107xC */
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
+
+ switch (PeriphClk)
+ {
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
+ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
+ || defined(STM32F105xC) || defined(STM32F107xC)
+ case RCC_PERIPHCLK_USB:
+ {
+ /* Get RCC configuration ------------------------------------------------------*/
+ temp_reg = RCC->CFGR;
+
+ /* Check if PLL is enabled */
+ if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLLON))
+ {
+ pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)];
+ if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
+ {
+#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
+ || defined(STM32F100xE)
+ prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> POSITION_VAL(RCC_CFGR2_PREDIV1)];
+#else
+ prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> POSITION_VAL(RCC_CFGR_PLLXTPRE)];
+#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
+ {
+ /* PLL2 selected as Prediv1 source */
+ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
+ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
+ pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> POSITION_VAL(RCC_CFGR2_PLL2MUL)) + 2;
+ pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul);
+ }
+ else
+ {
+ /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
+ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
+ }
+
+ /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
+ /* In this case need to divide pllclk by 2 */
+ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)])
+ {
+ pllclk = pllclk / 2;
+ }
+#else
+ if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
+ {
+ /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
+ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
+ }
+#endif /* STM32F105xC || STM32F107xC */
+ }
+ else
+ {
+ /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
+ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
+ }
+
+ /* Calcul of the USB frequency*/
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */
+ if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2)
+ {
+ /* Prescaler of 2 selected for USB */
+ frequency = pllclk;
+ }
+ else
+ {
+ /* Prescaler of 3 selected for USB */
+ frequency = (2 * pllclk) / 3;
+ }
+#else
+ /* USBCLK = PLLCLK / USB prescaler */
+ if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL)
+ {
+ /* No prescaler selected for USB */
+ frequency = pllclk;
+ }
+ else
+ {
+ /* Prescaler of 1.5 selected for USB */
+ frequency = (pllclk * 2) / 3;
+ }
+#endif
+ }
+ break;
+ }
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
+ || defined(STM32F107xC)
+ case RCC_PERIPHCLK_I2S2:
+ {
+#if defined(STM32F103xE) || defined(STM32F103xG)
+ /* SYSCLK used as source clock for I2S2 */
+ frequency = HAL_RCC_GetSysClockFreq();
+#else
+ if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK)
+ {
+ /* SYSCLK used as source clock for I2S2 */
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else
+ {
+ /* Check if PLLI2S is enabled */
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
+ {
+ /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
+ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
+ pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> POSITION_VAL(RCC_CFGR2_PLL3MUL)) + 2;
+ frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
+ }
+ }
+#endif /* STM32F103xE || STM32F103xG */
+ break;
+ }
+ case RCC_PERIPHCLK_I2S3:
+ {
+#if defined(STM32F103xE) || defined(STM32F103xG)
+ /* SYSCLK used as source clock for I2S3 */
+ frequency = HAL_RCC_GetSysClockFreq();
+#else
+ if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK)
+ {
+ /* SYSCLK used as source clock for I2S3 */
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ else
+ {
+ /* Check if PLLI2S is enabled */
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
+ {
+ /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
+ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
+ pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> POSITION_VAL(RCC_CFGR2_PLL3MUL)) + 2;
+ frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
+ }
+ }
+#endif /* STM32F103xE || STM32F103xG */
+ break;
+ }
+#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+ case RCC_PERIPHCLK_RTC:
+ {
+ /* Get RCC BDCR configuration ------------------------------------------------------*/
+ temp_reg = RCC->BDCR;
+
+ /* Check if LSE is ready if RTC clock selection is LSE */
+ if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Check if LSI is ready if RTC clock selection is LSI */
+ else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
+ {
+ frequency = LSI_VALUE;
+ }
+ else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
+ {
+ frequency = HSE_VALUE / 128;
+ }
+ /* Clock not enabled for RTC*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+ case RCC_PERIPHCLK_ADC:
+ {
+ frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> POSITION_VAL(RCC_CFGR_ADCPRE_DIV4)) + 1) * 2);
+ break;
+ }
+ default:
+ {
+ break;
+ }
+ }
+ return(frequency);
+}
+
+/**
+ * @}
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+/** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function
+ * @brief PLLI2S Management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended PLLI2S Management functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the PLLI2S
+ activation or deactivation
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable PLLI2S
+ * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that
+ * contains the configuration information for the PLLI2S
+ * @note The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)
+{
+ uint32_t tickstart = 0;
+
+ /* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/
+ if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL));
+ assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value));
+
+ /* Prediv2 can be written only when the PLL2 is disabled. */
+ /* Return an error only if new value is different from the programmed value */
+ if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \
+ (__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable the main PLLI2S. */
+ __HAL_RCC_PLLI2S_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLLI2S is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the HSE prediv2 factor --------------------------------*/
+ __HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value);
+
+
+ /* Configure the main PLLI2S multiplication factors. */
+ __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL);
+
+ /* Enable the main PLLI2S. */
+ __HAL_RCC_PLLI2S_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLLI2S is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* PLLI2S cannot be modified as already used by I2S2 or I2S3 */
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable PLLI2S
+ * @note PLLI2S is not disabled if used by I2S2 or I2S3 Interface.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
+{
+ uint32_t tickstart = 0;
+
+ /* Disable PLL I2S as not requested by I2S2 or I2S3*/
+ if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
+ {
+ /* Disable the main PLLI2S. */
+ __HAL_RCC_PLLI2S_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLLI2S is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function
+ * @brief PLL2 Management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended PLL2 Management functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the PLL2
+ activation or deactivation
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable PLL2
+ * @param PLL2Init pointer to an RCC_PLL2InitTypeDef structure that
+ * contains the configuration information for the PLL2
+ * @note The PLL2 configuration not modified if used indirectly as system clock.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init)
+{
+ uint32_t tickstart = 0;
+
+ /* This bit can not be cleared if the PLL2 clock is used indirectly as system
+ clock (i.e. it is used as PLL clock entry that is used as system clock). */
+ if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
+ (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
+ ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL));
+ assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value));
+
+ /* Prediv2 can be written only when the PLLI2S is disabled. */
+ /* Return an error only if new value is different from the programmed value */
+ if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
+ (__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable the main PLL2. */
+ __HAL_RCC_PLL2_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL2 is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the HSE prediv2 factor --------------------------------*/
+ __HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value);
+
+ /* Configure the main PLL2 multiplication factors. */
+ __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL);
+
+ /* Enable the main PLL2. */
+ __HAL_RCC_PLL2_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL2 is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable PLL2
+ * @note PLL2 is not disabled if used indirectly as system clock.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
+{
+ uint32_t tickstart = 0;
+
+ /* This bit can not be cleared if the PLL2 clock is used indirectly as system
+ clock (i.e. it is used as PLL clock entry that is used as system clock). */
+ if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
+ (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
+ ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Disable the main PLL2. */
+ __HAL_RCC_PLL2_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL2 is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+#endif /* STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,5379 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_tim.c
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief TIM HAL module driver
+ * This file provides firmware functions to manage the following
+ * functionalities of the Timer (TIM) peripheral:
+ * + Time Base Initialization
+ * + Time Base Start
+ * + Time Base Start Interruption
+ * + Time Base Start DMA
+ * + Time Output Compare/PWM Initialization
+ * + Time Output Compare/PWM Channel Configuration
+ * + Time Output Compare/PWM Start
+ * + Time Output Compare/PWM Start Interruption
+ * + Time Output Compare/PWM Start DMA
+ * + Time Input Capture Initialization
+ * + Time Input Capture Channel Configuration
+ * + Time Input Capture Start
+ * + Time Input Capture Start Interruption
+ * + Time Input Capture Start DMA
+ * + Time One Pulse Initialization
+ * + Time One Pulse Channel Configuration
+ * + Time One Pulse Start
+ * + Time Encoder Interface Initialization
+ * + Time Encoder Interface Start
+ * + Time Encoder Interface Start Interruption
+ * + Time Encoder Interface Start DMA
+ * + Commutation Event configuration with Interruption and DMA
+ * + Time OCRef clear configuration
+ * + Time External Clock configuration
+ @verbatim
+ ==============================================================================
+ ##### TIMER Generic features #####
+ ==============================================================================
+ [..] The Timer features include:
+ (#) 16-bit up, down, up/down auto-reload counter.
+ (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
+ counter clock frequency either by any factor between 1 and 65536.
+ (#) Up to 4 independent channels for:
+ (++) Input Capture
+ (++) Output Compare
+ (++) PWM generation (Edge and Center-aligned Mode)
+ (++) One-pulse mode output
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Initialize the TIM low level resources by implementing the following functions
+ depending from feature used :
+ (++) Time Base : HAL_TIM_Base_MspInit()
+ (++) Input Capture : HAL_TIM_IC_MspInit()
+ (++) Output Compare : HAL_TIM_OC_MspInit()
+ (++) PWM generation : HAL_TIM_PWM_MspInit()
+ (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+ (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
+
+ (#) Initialize the TIM low level resources :
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+ (##) TIM pins configuration
+ (+++) Enable the clock for the TIM GPIOs using the following function:
+ __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+ (#) The external Clock can be configured, if needed (the default clock is the
+ internal clock from the APBx), using the following function:
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before
+ any start function.
+
+ (#) Configure the TIM in the desired functioning mode using one of the
+ Initialization function of this driver:
+ (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+ (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
+ Output Compare signal.
+ (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+ PWM signal.
+ (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+ external signal.
+ (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+ in One Pulse Mode.
+ (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+
+ (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
+ (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
+ (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
+ (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
+ (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
+ (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
+ (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
+
+ (#) The DMA Burst is managed with the two following functions:
+ HAL_TIM_DMABurst_WriteStart()
+ HAL_TIM_DMABurst_ReadStart()
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup TIM TIM
+ * @brief TIM HAL module driver
+ * @{
+ */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup TIM_Private_Functions TIM Private Functions
+ * @{
+ */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
+static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef * sSlaveConfig);
+
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup TIM_Exported_Functions TIM Exported Functions
+ * @{
+ */
+
+/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
+ * @brief Time Base functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Base functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM base.
+ (+) De-initialize the TIM base.
+ (+) Start the Time Base.
+ (+) Stop the Time Base.
+ (+) Start the Time Base and enable interrupt.
+ (+) Stop the Time Base and disable interrupt.
+ (+) Start the Time Base and enable DMA transfer.
+ (+) Stop the Time Base and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Time base Unit according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @param htim : TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ HAL_TIM_Base_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Set the Time Base configuration */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM Base peripheral
+ * @param htim : TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_Base_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Base MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_Base_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Base MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_Base_MspDeInit could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief Starts the TIM Base generation.
+ * @param htim : TIM handle
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Change the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation.
+ * @param htim : TIM handle
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Base generation in interrupt mode.
+ * @param htim : TIM handle
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Enable the TIM Update interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation in interrupt mode.
+ * @param htim : TIM handle
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ /* Disable the TIM Update interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Base generation in DMA mode.
+ * @param htim : TIM handle
+ * @param pData : The source Buffer address.
+ * @param Length : The length of data to be transferred from memory to peripheral.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((pData == 0 ) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
+
+ /* Enable the TIM Update DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation in DMA mode.
+ * @param htim : TIM handle
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
+ * @brief Time Output Compare functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Output Compare functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Output Compare.
+ (+) De-initialize the TIM Output Compare.
+ (+) Start the Time Output Compare.
+ (+) Stop the Time Output Compare.
+ (+) Start the Time Output Compare and enable interrupt.
+ (+) Stop the Time Output Compare and disable interrupt.
+ (+) Start the Time Output Compare and enable DMA transfer.
+ (+) Stop the Time Output Compare and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Output Compare according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @param htim : TIM Output Compare handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OC_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the Output Compare */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim : TIM Output Compare handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OC_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Output Compare MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_OC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Output Compare MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_OC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation.
+ * @param htim : TIM Output Compare handle
+ * @param Channel : TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode.
+ * @param htim : TIM OC handle
+ * @param Channel : TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode.
+ * @param htim : TIM Output Compare handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in DMA mode.
+ * @param htim : TIM Output Compare handle
+ * @param Channel : TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData : The source Buffer address.
+ * @param Length : The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0 ) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in DMA mode.
+ * @param htim : TIM Output Compare handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
+ * @brief Time PWM functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time PWM functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM PWM.
+ (+) De-initialize the TIM PWM.
+ (+) Start the Time PWM.
+ (+) Stop the Time PWM.
+ (+) Start the Time PWM and enable interrupt.
+ (+) Stop the Time PWM and disable interrupt.
+ (+) Start the Time PWM and enable DMA transfer.
+ (+) Stop the Time PWM and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM PWM Time Base according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @param htim : TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_PWM_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the PWM */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim : TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_PWM_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM PWM MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM PWM MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the PWM signal generation.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the PWM signal generation in interrupt mode.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation in interrupt mode.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM PWM signal generation in DMA mode.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData : The source Buffer address.
+ * @param Length : The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0 ) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+ /* Enable the TIM Output Capture/Compare 3 request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM PWM signal generation in DMA mode.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
+ * @brief Time Input Capture functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Input Capture functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Input Capture.
+ (+) De-initialize the TIM Input Capture.
+ (+) Start the Time Input Capture.
+ (+) Stop the Time Input Capture.
+ (+) Start the Time Input Capture and enable interrupt.
+ (+) Stop the Time Input Capture and disable interrupt.
+ (+) Start the Time Input Capture and enable DMA transfer.
+ (+) Stop the Time Input Capture and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Input Capture Time base according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @param htim : TIM Input Capture handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_IC_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the input capture */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim : TIM Input Capture handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_IC_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Input Capture MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_IC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Input Capture MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_IC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement.
+ * @param htim : TIM Input Capture handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement in interrupt mode.
+ * @param htim : TIM Input Capture handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement in interrupt mode.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement in DMA mode.
+ * @param htim : TIM Input Capture handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData : The destination Buffer address.
+ * @param Length : The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((pData == 0 ) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement in DMA mode.
+ * @param htim : TIM Input Capture handle
+ * @param Channel : TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
+ * @brief Time One Pulse functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time One Pulse functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM One Pulse.
+ (+) De-initialize the TIM One Pulse.
+ (+) Start the Time One Pulse.
+ (+) Stop the Time One Pulse.
+ (+) Start the Time One Pulse and enable interrupt.
+ (+) Stop the Time One Pulse and disable interrupt.
+ (+) Start the Time One Pulse and enable DMA transfer.
+ (+) Stop the Time One Pulse and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM One Pulse Time Base according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @param htim : TIM OnePulse handle
+ * @param OnePulseMode : Select the One pulse mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
+ * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OnePulse_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Configure the Time base in the One Pulse Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Reset the OPM Bit */
+ htim->Instance->CR1 &= ~TIM_CR1_OPM;
+
+ /* Configure the OPM Mode */
+ htim->Instance->CR1 |= OnePulseMode;
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM One Pulse
+ * @param htim : TIM One Pulse handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_OnePulse_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM One Pulse MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_OnePulse_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM One Pulse MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation.
+ * @param htim : TIM One Pulse handle
+ * @param OutputChannel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Enable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+ No need to enable the counter, it's enabled automatically by hardware
+ (the counter starts in response to a stimulus and generate a pulse */
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation.
+ * @param htim : TIM One Pulse handle
+ * @param OutputChannel : TIM Channels to be disable
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Disable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode.
+ * @param htim : TIM One Pulse handle
+ * @param OutputChannel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Enable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+ No need to enable the counter, it's enabled automatically by hardware
+ (the counter starts in response to a stimulus and generate a pulse */
+
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode.
+ * @param htim : TIM One Pulse handle
+ * @param OutputChannel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+ /* Disable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
+ * @brief Time Encoder functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Encoder functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Encoder.
+ (+) De-initialize the TIM Encoder.
+ (+) Start the Time Encoder.
+ (+) Stop the Time Encoder.
+ (+) Start the Time Encoder and enable interrupt.
+ (+) Stop the Time Encoder and disable interrupt.
+ (+) Start the Time Encoder and enable DMA transfer.
+ (+) Stop the Time Encoder and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Encoder Interface and create the associated handle.
+ * @param htim : TIM Encoder Interface handle
+ * @param sConfig : TIM Encoder Interface configuration structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
+{
+ uint32_t tmpsmcr = 0;
+ uint32_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_Encoder_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Reset the SMS bits */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+
+ /* Configure the Time base in the Encoder Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = htim->Instance->CCMR1;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = htim->Instance->CCER;
+
+ /* Set the encoder Mode */
+ tmpsmcr |= sConfig->EncoderMode;
+
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+ tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
+
+ /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+ tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+ tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
+ tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
+
+ /* Set the TI1 and the TI2 Polarities */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+ tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+ tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
+
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+
+ /* Write to TIMx CCMR1 */
+ htim->Instance->CCMR1 = tmpccmr1;
+
+ /* Write to TIMx CCER */
+ htim->Instance->CCER = tmpccer;
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief DeInitializes the TIM Encoder interface
+ * @param htim : TIM Encoder handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_Encoder_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Encoder Interface MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_Encoder_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Encoder Interface MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface.
+ * @param htim : TIM Encoder Interface handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Enable the encoder interface channels */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
+ }
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
+ }
+ }
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface.
+ * @param htim : TIM Encoder Interface handle
+ * @param Channel : TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ break;
+ }
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ break;
+ }
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface in interrupt mode.
+ * @param htim : TIM Encoder Interface handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Enable the encoder interface channels */
+ /* Enable the capture compare Interrupts 1 and/or 2 */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface in interrupt mode.
+ * @param htim : TIM Encoder Interface handle
+ * @param Channel : TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ if(Channel == TIM_CHANNEL_1)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 1 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ else if(Channel == TIM_CHANNEL_2)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 2 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ else
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 1 and 2 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface in DMA mode.
+ * @param htim : TIM Encoder Interface handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @param pData1 : The destination Buffer address for IC1.
+ * @param pData2 : The destination Buffer address for IC2.
+ * @param Length : The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
+
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
+
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ }
+ break;
+
+ case TIM_CHANNEL_ALL:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
+
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ default:
+ break;
+ }
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface in DMA mode.
+ * @param htim : TIM Encoder Interface handle
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ if(Channel == TIM_CHANNEL_1)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 1 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ else if(Channel == TIM_CHANNEL_2)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 2 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ else
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 1 and 2 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+ * @brief IRQ handler management
+ *
+@verbatim
+ ==============================================================================
+ ##### IRQ handler management #####
+ ==============================================================================
+ [..]
+ This section provides Timer IRQ handler function.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief This function handles TIM interrupts requests.
+ * @param htim : TIM handle
+ * @retval None
+ */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+{
+ /* Capture compare 1 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
+ {
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+ /* Input capture event */
+ if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ }
+ /* Capture compare 2 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ /* Input capture event */
+ if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* Capture compare 3 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ /* Input capture event */
+ if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* Capture compare 4 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ /* Input capture event */
+ if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* TIM Update event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+ HAL_TIM_PeriodElapsedCallback(htim);
+ }
+ }
+ /* TIM Break input event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+ HAL_TIMEx_BreakCallback(htim);
+ }
+ }
+ /* TIM Trigger detection event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+ HAL_TIM_TriggerCallback(htim);
+ }
+ }
+ /* TIM commutation event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+ HAL_TIMEx_CommutationCallback(htim);
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+ (+) Configure External Clock source.
+ (+) Configure Complementary channels, break features and dead time.
+ (+) Configure Master and the Slave synchronization.
+ (+) Configure the DMA Burst Mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the TIM Output Compare Channels according to the specified
+ * parameters in the TIM_OC_InitTypeDef.
+ * @param htim : TIM Output Compare handle
+ * @param sConfig : TIM Output Compare configuration structure
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ /* Configure the TIM Channel 1 in Output Compare */
+ TIM_OC1_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ /* Configure the TIM Channel 2 in Output Compare */
+ TIM_OC2_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+ /* Configure the TIM Channel 3 in Output Compare */
+ TIM_OC3_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+ /* Configure the TIM Channel 4 in Output Compare */
+ TIM_OC4_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ default:
+ break;
+ }
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Input Capture Channels according to the specified
+ * parameters in the TIM_IC_InitTypeDef.
+ * @param htim : TIM IC handle
+ * @param sConfig : TIM Input Capture configuration structure
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ if (Channel == TIM_CHANNEL_1)
+ {
+ /* TI1 Configuration */
+ TIM_TI1_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+ /* Set the IC1PSC value */
+ htim->Instance->CCMR1 |= sConfig->ICPrescaler;
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ /* TI2 Configuration */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_TI2_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC2PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+ /* Set the IC2PSC value */
+ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
+ }
+ else if (Channel == TIM_CHANNEL_3)
+ {
+ /* TI3 Configuration */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ TIM_TI3_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC3PSC Bits */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
+
+ /* Set the IC3PSC value */
+ htim->Instance->CCMR2 |= sConfig->ICPrescaler;
+ }
+ else
+ {
+ /* TI4 Configuration */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ TIM_TI4_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC4PSC Bits */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
+
+ /* Set the IC4PSC value */
+ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM PWM channels according to the specified
+ * parameters in the TIM_OC_InitTypeDef.
+ * @param htim : TIM handle
+ * @param sConfig : TIM PWM configuration structure
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
+{
+ __HAL_LOCK(htim);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+ assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ /* Configure the Channel 1 in PWM mode */
+ TIM_OC1_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel1 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ /* Configure the Channel 2 in PWM mode */
+ TIM_OC2_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel2 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+ /* Configure the Channel 3 in PWM mode */
+ TIM_OC3_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel3 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+ /* Configure the Channel 4 in PWM mode */
+ TIM_OC4_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel4 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM One Pulse Channels according to the specified
+ * parameters in the TIM_OnePulse_InitTypeDef.
+ * @param htim : TIM One Pulse handle
+ * @param sConfig : TIM One Pulse configuration structure
+ * @param OutputChannel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param InputChannel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
+{
+ TIM_OC_InitTypeDef temp1;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
+ assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
+
+ if(OutputChannel != InputChannel)
+ {
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Extract the Ouput compare configuration from sConfig structure */
+ temp1.OCMode = sConfig->OCMode;
+ temp1.Pulse = sConfig->Pulse;
+ temp1.OCPolarity = sConfig->OCPolarity;
+ temp1.OCNPolarity = sConfig->OCNPolarity;
+ temp1.OCIdleState = sConfig->OCIdleState;
+ temp1.OCNIdleState = sConfig->OCNIdleState;
+
+ switch (OutputChannel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ TIM_OC1_SetConfig(htim->Instance, &temp1);
+ }
+ break;
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_OC2_SetConfig(htim->Instance, &temp1);
+ }
+ break;
+ default:
+ break;
+ }
+ switch (InputChannel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+ sConfig->ICSelection, sConfig->ICFilter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+ /* Select the Trigger source */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI1FP1;
+
+ /* Select the Slave Mode */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ }
+ break;
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+ sConfig->ICSelection, sConfig->ICFilter);
+
+ /* Reset the IC2PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+ /* Select the Trigger source */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI2FP2;
+
+ /* Select the Slave Mode */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
+ * @param htim : TIM handle
+ * @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_DCR
+ * @param BurstRequestSrc : TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer : The Buffer address.
+ * @param BurstLength : DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
+ uint32_t* BurstBuffer, uint32_t BurstLength)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((BurstBuffer == 0 ) && (BurstLength > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch(BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_CC1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_CC2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_CC3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_CC4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_COM:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_TRIGGER:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ default:
+ break;
+ }
+ /* configure the DMA Burst Mode */
+ htim->Instance->DCR = BurstBaseAddress | BurstLength;
+
+ /* Enable the TIM DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM DMA Burst mode
+ * @param htim : TIM handle
+ * @param BurstRequestSrc : TIM DMA Request sources to disable
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+ /* Abort the DMA transfer (at least disable the DMA channel) */
+ switch(BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+ }
+ break;
+ case TIM_DMA_CC1:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+ }
+ break;
+ case TIM_DMA_CC2:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+ }
+ break;
+ case TIM_DMA_CC3:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+ }
+ break;
+ case TIM_DMA_CC4:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+ }
+ break;
+ case TIM_DMA_COM:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ }
+ break;
+ case TIM_DMA_TRIGGER:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+ * @param htim : TIM handle
+ * @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_DCR
+ * @param BurstRequestSrc : TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer : The Buffer address.
+ * @param BurstLength : DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
+ uint32_t *BurstBuffer, uint32_t BurstLength)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((BurstBuffer == 0 ) && (BurstLength > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch(BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_CC1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_CC2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_CC3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_CC4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_COM:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_TRIGGER:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* configure the DMA Burst Mode */
+ htim->Instance->DCR = BurstBaseAddress | BurstLength;
+
+ /* Enable the TIM DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA burst reading
+ * @param htim : TIM handle
+ * @param BurstRequestSrc : TIM DMA Request sources to disable.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+ /* Abort the DMA transfer (at least disable the DMA channel) */
+ switch(BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+ }
+ break;
+ case TIM_DMA_CC1:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+ }
+ break;
+ case TIM_DMA_CC2:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+ }
+ break;
+ case TIM_DMA_CC3:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+ }
+ break;
+ case TIM_DMA_CC4:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+ }
+ break;
+ case TIM_DMA_COM:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ }
+ break;
+ case TIM_DMA_TRIGGER:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Generate a software event
+ * @param htim : TIM handle
+ * @param EventSource : specifies the event source.
+ * This parameter can be one of the following values:
+ * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
+ * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
+ * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
+ * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
+ * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
+ * @arg TIM_EVENTSOURCE_COM: Timer COM event source
+ * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
+ * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
+ * @note TIM6 and TIM7 can only generate an update event.
+ * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17.
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_EVENT_SOURCE(EventSource));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ /* Change the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Set the event sources */
+ htim->Instance->EGR = EventSource;
+
+ /* Change the TIM state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the OCRef clear feature
+ * @param htim : TIM handle
+ * @param sClearInputConfig : pointer to a TIM_ClearInputConfigTypeDef structure that
+ * contains the OCREF clear feature and parameters for the TIM peripheral.
+ * @param Channel : specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
+{
+ uint32_t tmpsmcr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+ assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+ assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+ assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ switch (sClearInputConfig->ClearInputSource)
+ {
+ case TIM_CLEARINPUTSOURCE_NONE:
+ {
+ /* Clear the OCREF clear selection bit */
+ tmpsmcr &= ~TIM_SMCR_OCCS;
+
+ /* Clear the ETR Bits */
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+ /* Set TIMx_SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ }
+ break;
+
+ case TIM_CLEARINPUTSOURCE_ETR:
+ {
+ TIM_ETR_SetConfig(htim->Instance,
+ sClearInputConfig->ClearInputPrescaler,
+ sClearInputConfig->ClearInputPolarity,
+ sClearInputConfig->ClearInputFilter);
+
+ /* Set the OCREF clear selection bit */
+ htim->Instance->SMCR |= TIM_SMCR_OCCS;
+ }
+ break;
+ default:
+ break;
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 1 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 1 */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
+ }
+ }
+ break;
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 2 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 2 */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
+ }
+ }
+ break;
+ case TIM_CHANNEL_3:
+ {
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 3 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 3 */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
+ }
+ }
+ break;
+ case TIM_CHANNEL_4:
+ {
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 4 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 4 */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the clock source to be used
+ * @param htim : TIM handle
+ * @param sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that
+ * contains the clock source information for the TIM peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
+{
+ uint32_t tmpsmcr = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+
+ /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+ tmpsmcr = htim->Instance->SMCR;
+ tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ htim->Instance->SMCR = tmpsmcr;
+
+ switch (sClockSourceConfig->ClockSource)
+ {
+ case TIM_CLOCKSOURCE_INTERNAL:
+ {
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ /* Disable slave mode to clock the prescaler directly with the internal clock */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ }
+ break;
+
+ case TIM_CLOCKSOURCE_ETRMODE1:
+ {
+ /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+
+ /* Check ETR input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ /* Configure the ETR Clock source */
+ TIM_ETR_SetConfig(htim->Instance,
+ sClockSourceConfig->ClockPrescaler,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+ /* Reset the SMS and TS Bits */
+ tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ /* Select the External clock mode1 and the ETRF trigger */
+ tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ }
+ break;
+
+ case TIM_CLOCKSOURCE_ETRMODE2:
+ {
+ /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
+
+ /* Check ETR input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ /* Configure the ETR Clock source */
+ TIM_ETR_SetConfig(htim->Instance,
+ sClockSourceConfig->ClockPrescaler,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ /* Enable the External clock mode2 */
+ htim->Instance->SMCR |= TIM_SMCR_ECE;
+ }
+ break;
+
+ case TIM_CLOCKSOURCE_TI1:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ /* Check TI1 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+ }
+ break;
+ case TIM_CLOCKSOURCE_TI2:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ /* Check TI2 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ TIM_TI2_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+ }
+ break;
+ case TIM_CLOCKSOURCE_TI1ED:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ /* Check TI1 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+ }
+ break;
+ case TIM_CLOCKSOURCE_ITR0:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
+ }
+ break;
+ case TIM_CLOCKSOURCE_ITR1:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
+ }
+ break;
+ case TIM_CLOCKSOURCE_ITR2:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
+ }
+ break;
+ case TIM_CLOCKSOURCE_ITR3:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
+ }
+ break;
+
+ default:
+ break;
+ }
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Selects the signal connected to the TI1 input: direct from CH1_input
+ * or a XOR combination between CH1_input, CH2_input & CH3_input
+ * @param htim : TIM handle.
+ * @param TI1_Selection : Indicate whether or not channel 1 is connected to the
+ * output of a XOR gate.
+ * This parameter can be one of the following values:
+ * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
+ * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
+ * pins are connected to the TI1 input (XOR combination)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
+{
+ uint32_t tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = htim->Instance->CR2;
+
+ /* Reset the TI1 selection */
+ tmpcr2 &= ~TIM_CR2_TI1S;
+
+ /* Set the the TI1 selection */
+ tmpcr2 |= TI1_Selection;
+
+ /* Write to TIMxCR2 */
+ htim->Instance->CR2 = tmpcr2;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIM in Slave mode
+ * @param htim : TIM handle.
+ * @param sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that
+ * contains the selected trigger (internal trigger input, filtered
+ * timer input or external trigger input) and the ) and the Slave
+ * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
+
+ /* Disable Trigger Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
+
+ /* Disable Trigger DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+ }
+
+/**
+ * @brief Configures the TIM in Slave mode in interrupt mode
+ * @param htim: TIM handle.
+ * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
+ * contains the selected trigger (internal trigger input, filtered
+ * timer input or external trigger input) and the ) and the Slave
+ * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef * sSlaveConfig)
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
+
+ /* Enable Trigger Interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
+
+ /* Disable Trigger DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read the captured value from Capture Compare unit
+ * @param htim : TIM handle.
+ * @param Channel : TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1 : TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2 : TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3 : TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4 : TIM Channel 4 selected
+ * @retval Captured value
+ */
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpreg = 0;
+
+ __HAL_LOCK(htim);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ /* Return the capture 1 value */
+ tmpreg = htim->Instance->CCR1;
+
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Return the capture 2 value */
+ tmpreg = htim->Instance->CCR2;
+
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ /* Return the capture 3 value */
+ tmpreg = htim->Instance->CCR3;
+
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ /* Return the capture 4 value */
+ tmpreg = htim->Instance->CCR4;
+
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ __HAL_UNLOCK(htim);
+ return tmpreg;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+ * @brief TIM Callbacks functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM Callbacks functions #####
+ ==============================================================================
+ [..]
+ This section provides TIM callback functions:
+ (+) Timer Period elapsed callback
+ (+) Timer Output Compare callback
+ (+) Timer Input capture callback
+ (+) Timer Trigger callback
+ (+) Timer Error callback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Period elapsed callback in non blocking mode
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+ */
+
+}
+/**
+ * @brief Output Compare callback in non blocking mode
+ * @param htim : TIM OC handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+ */
+}
+/**
+ * @brief Input Capture callback in non blocking mode
+ * @param htim : TIM IC handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief PWM Pulse finished callback in non blocking mode
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Trigger detection callback in non blocking mode
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_TriggerCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Timer error callback in non blocking mode
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the TIM Base state
+ * @param htim : TIM Base handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM OC state
+ * @param htim : TIM Ouput Compare handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM PWM state
+ * @param htim : TIM handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM Input Capture state
+ * @param htim : TIM IC handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM One Pulse Mode state
+ * @param htim : TIM OPM handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM Encoder Mode state
+ * @param htim : TIM Encoder handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief TIM DMA error callback
+ * @param hdma : pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ HAL_TIM_ErrorCallback(htim);
+}
+
+/**
+ * @brief TIM DMA Delay Pulse complete callback.
+ * @param hdma : pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+/**
+ * @brief TIM DMA Capture complete callback.
+ * @param hdma : pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+
+ HAL_TIM_IC_CaptureCallback(htim);
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Period Elapse complete callback.
+ * @param hdma : pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ HAL_TIM_PeriodElapsedCallback(htim);
+}
+
+/**
+ * @brief TIM DMA Trigger callback.
+ * @param hdma : pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ HAL_TIM_TriggerCallback(htim);
+}
+
+/**
+ * @brief Time Base configuration
+ * @param TIMx : TIM periheral
+ * @param Structure : TIM Base configuration structure
+ * @retval None
+ */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+{
+ uint32_t tmpcr1 = 0;
+ tmpcr1 = TIMx->CR1;
+
+ /* Set TIM Time Base Unit parameters ---------------------------------------*/
+ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+ {
+ /* Select the Counter Mode */
+ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+ tmpcr1 |= Structure->CounterMode;
+ }
+
+ if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+ {
+ /* Set the clock division */
+ tmpcr1 &= ~TIM_CR1_CKD;
+ tmpcr1 |= (uint32_t)Structure->ClockDivision;
+ }
+
+ TIMx->CR1 = tmpcr1;
+
+ /* Set the Autoreload value */
+ TIMx->ARR = (uint32_t)Structure->Period ;
+
+ /* Set the Prescaler value */
+ TIMx->PSC = (uint32_t)Structure->Prescaler;
+
+ if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+ {
+ /* Set the Repetition Counter value */
+ TIMx->RCR = Structure->RepetitionCounter;
+ }
+
+ /* Generate an update event to reload the Prescaler
+ and the repetition counter(only for TIM1 and TIM8) value immediatly */
+ TIMx->EGR = TIM_EGR_UG;
+}
+
+/**
+ * @brief Time Ouput Compare 1 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config : The ouput configuration structure
+ * @retval None
+ */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0;
+ uint32_t tmpccer = 0;
+ uint32_t tmpcr2 = 0;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= ~TIM_CCMR1_OC1M;
+ tmpccmrx &= ~TIM_CCMR1_CC1S;
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC1P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= OC_Config->OCPolarity;
+
+ if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC1NP;
+ /* Set the Output N Polarity */
+ tmpccer |= OC_Config->OCNPolarity;
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC1NE;
+ }
+
+ if(IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS1;
+ tmpcr2 &= ~TIM_CR2_OIS1N;
+ /* Set the Output Idle state */
+ tmpcr2 |= OC_Config->OCIdleState;
+ /* Set the Output N Idle state */
+ tmpcr2 |= OC_Config->OCNIdleState;
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR1 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Time Ouput Compare 2 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config : The ouput configuration structure
+ * @retval None
+ */
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0;
+ uint32_t tmpccer = 0;
+ uint32_t tmpcr2 = 0;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR1_OC2M;
+ tmpccmrx &= ~TIM_CCMR1_CC2S;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC2P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 4);
+
+ if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
+ {
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC2NP;
+ /* Set the Output N Polarity */
+ tmpccer |= (OC_Config->OCNPolarity << 4);
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC2NE;
+
+ }
+
+ if(IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS2;
+ tmpcr2 &= ~TIM_CR2_OIS2N;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 2);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (OC_Config->OCNIdleState << 2);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR2 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Time Ouput Compare 3 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config : The ouput configuration structure
+ * @retval None
+ */
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0;
+ uint32_t tmpccer = 0;
+ uint32_t tmpcr2 = 0;
+
+ /* Disable the Channel 3: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC3E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR2_OC3M;
+ tmpccmrx &= ~TIM_CCMR2_CC3S;
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC3P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 8);
+
+ if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
+ {
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC3NP;
+ /* Set the Output N Polarity */
+ tmpccer |= (OC_Config->OCNPolarity << 8);
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC3NE;
+ }
+
+ if(IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS3;
+ tmpcr2 &= ~TIM_CR2_OIS3N;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 4);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (OC_Config->OCNIdleState << 4);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR3 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Time Ouput Compare 4 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config : The ouput configuration structure
+ * @retval None
+ */
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0;
+ uint32_t tmpccer = 0;
+ uint32_t tmpcr2 = 0;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC4E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR2_OC4M;
+ tmpccmrx &= ~TIM_CCMR2_CC4S;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC4P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 12);
+
+ if(IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS4;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 6);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR4 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+
+/**
+ * @brief Time Slave configuration
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param sSlaveConfig: The slave configuration structure
+ * @retval None
+ */
+static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef * sSlaveConfig)
+{
+ uint32_t tmpsmcr = 0;
+ uint32_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* Reset the Trigger Selection Bits */
+ tmpsmcr &= ~TIM_SMCR_TS;
+ /* Set the Input Trigger source */
+ tmpsmcr |= sSlaveConfig->InputTrigger;
+
+ /* Reset the slave mode Bits */
+ tmpsmcr &= ~TIM_SMCR_SMS;
+ /* Set the slave mode */
+ tmpsmcr |= sSlaveConfig->SlaveMode;
+
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+
+ /* Configure the trigger prescaler, filter, and polarity */
+ switch (sSlaveConfig->InputTrigger)
+ {
+ case TIM_TS_ETRF:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+ /* Configure the ETR Trigger source */
+ TIM_ETR_SetConfig(htim->Instance,
+ sSlaveConfig->TriggerPrescaler,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ }
+ break;
+
+ case TIM_TS_TI1F_ED:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ tmpccer = htim->Instance->CCER;
+ htim->Instance->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = htim->Instance->CCMR1;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ htim->Instance->CCMR1 = tmpccmr1;
+ htim->Instance->CCER = tmpccer;
+
+ }
+ break;
+
+ case TIM_TS_TI1FP1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Configure TI1 Filter and Polarity */
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ }
+ break;
+
+ case TIM_TS_TI2FP2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Configure TI2 Filter and Polarity */
+ TIM_TI2_ConfigInputStage(htim->Instance,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ }
+ break;
+
+ case TIM_TS_ITR0:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ }
+ break;
+
+ case TIM_TS_ITR1:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ }
+ break;
+
+ case TIM_TS_ITR2:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ }
+ break;
+
+ case TIM_TS_ITR3:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ }
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Configure the TI1 as Input.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection : specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
+ * @param TIM_ICFilter : Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+ * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+ * protected against un-initialized filter and polarity values.
+ */
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+ {
+ tmpccmr1 &= ~TIM_CCMR1_CC1S;
+ tmpccmr1 |= TIM_ICSelection;
+ }
+ else
+ {
+ tmpccmr1 |= TIM_CCMR1_CC1S_0;
+ }
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
+
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the Polarity and Filter for TI1.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICFilter : Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ tmpccer = TIMx->CCER;
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= (TIM_ICFilter << 4);
+
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ tmpccer |= TIM_ICPolarity;
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI2 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection : specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
+ * @param TIM_ICFilter : Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
+ * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
+ * protected against un-initialized filter and polarity values.
+ */
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ tmpccmr1 &= ~TIM_CCMR1_CC2S;
+ tmpccmr1 |= (TIM_ICSelection << 8);
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
+
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1 ;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the Polarity and Filter for TI2.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICFilter : Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ tmpccmr1 |= (TIM_ICFilter << 12);
+
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= (TIM_ICPolarity << 4);
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1 ;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI3 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection : specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
+ * @param TIM_ICFilter : Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+ * protected against un-initialized filter and polarity values.
+ */
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr2 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC3E;
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ tmpccmr2 &= ~TIM_CCMR2_CC3S;
+ tmpccmr2 |= TIM_ICSelection;
+
+ /* Set the filter */
+ tmpccmr2 &= ~TIM_CCMR2_IC3F;
+ tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
+
+ /* Select the Polarity and set the CC3E Bit */
+ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
+ tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI4 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection : specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
+ * @param TIM_ICFilter : Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+ * protected against un-initialized filter and polarity values.
+ * @retval None
+ */
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr2 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC4E;
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ tmpccmr2 &= ~TIM_CCMR2_CC4S;
+ tmpccmr2 |= (TIM_ICSelection << 8);
+
+ /* Set the filter */
+ tmpccmr2 &= ~TIM_CCMR2_IC4F;
+ tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
+
+ /* Select the Polarity and set the CC4E Bit */
+ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
+ tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
+
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer ;
+}
+
+/**
+ * @brief Selects the Input Trigger source
+ * @param TIMx to select the TIM peripheral
+ * @param InputTriggerSource : The Input Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0 : Internal Trigger 0
+ * @arg TIM_TS_ITR1 : Internal Trigger 1
+ * @arg TIM_TS_ITR2 : Internal Trigger 2
+ * @arg TIM_TS_ITR3 : Internal Trigger 3
+ * @arg TIM_TS_TI1F_ED : TI1 Edge Detector
+ * @arg TIM_TS_TI1FP1 : Filtered Timer Input 1
+ * @arg TIM_TS_TI2FP2 : Filtered Timer Input 2
+ * @arg TIM_TS_ETRF : External Trigger input
+ * @retval None
+ */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
+{
+ uint32_t tmpsmcr = 0;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+ /* Reset the TS Bits */
+ tmpsmcr &= ~TIM_SMCR_TS;
+ /* Set the Input Trigger source and the slave mode*/
+ tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+/**
+ * @brief Configures the TIMx External Trigger (ETR).
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ExtTRGPrescaler : The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
+ * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
+ * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
+ * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity : The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
+ * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
+ * @param ExtTRGFilter : External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+ uint32_t tmpsmcr = 0;
+
+ tmpsmcr = TIMx->SMCR;
+
+ /* Reset the ETR Bits */
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+ /* Set the Prescaler, the Filter value and the Polarity */
+ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
+
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel x.
+ * @param TIMx to select the TIM peripheral
+ * @param Channel : specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @param ChannelState : specifies the TIM Channel CCxE bit new state.
+ * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
+ * @retval None
+ */
+void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_TIM_CHANNELS(Channel));
+
+ tmp = TIM_CCER_CC1E << Channel;
+
+ /* Reset the CCxE Bit */
+ TIMx->CCER &= ~tmp;
+
+ /* Set or reset the CCxE Bit */
+ TIMx->CCER |= (uint32_t)(ChannelState << Channel);
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1857 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_tim_ex.c
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief TIM HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Timer Extended peripheral:
+ * + Time Hall Sensor Interface Initialization
+ * + Time Hall Sensor Interface Start
+ * + Time Complementary signal bread and dead time configuration
+ * + Time Master and Slave synchronization configuration
+ * + Timer remapping capabilities configuration
+ @verbatim
+ ==============================================================================
+ ##### TIMER Extended features #####
+ ==============================================================================
+ [..]
+ The Timer Extended features include:
+ (#) Complementary outputs with programmable dead-time for :
+ (++) Output Compare
+ (++) PWM generation (Edge and Center-aligned Mode)
+ (++) One-pulse mode output
+ (#) Synchronization circuit to control the timer with external signals and to
+ interconnect several timers together.
+ (#) Break input to put the timer output signals in reset state or in a known state.
+ (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
+ positioning purposes
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Initialize the TIM low level resources by implementing the following functions
+ depending from feature used :
+ (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
+ (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
+ (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
+
+ (#) Initialize the TIM low level resources :
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+ (##) TIM pins configuration
+ (+++) Enable the clock for the TIM GPIOs using the following function:
+ __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+ (#) The external Clock can be configured, if needed (the default clock is the
+ internal clock from the APBx), using the following function:
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before
+ any start function.
+
+ (#) Configure the TIM in the desired functioning mode using one of the
+ initialization function of this driver:
+ (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
+ Timer Hall Sensor Interface and the commutation event with the corresponding
+ Interrupt and DMA request if needed (Note that One Timer is used to interface
+ with the Hall sensor Interface and another Timer should be used to use
+ the commutation event).
+
+ (#) Activate the TIM peripheral using one of the start functions:
+ (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
+ (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
+ (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
+
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup TIMEx TIMEx
+ * @brief TIM Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+#if defined (STM32F100xB) || defined (STM32F100xE) || \
+ defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
+ defined (STM32F105xC) || defined (STM32F107xC)
+/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
+ * @{
+ */
+static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
+/**
+ * @}
+ */
+#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
+ /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
+ /* defined(STM32F105xC) || defined(STM32F107xC) */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
+ * @{
+ */
+
+
+/** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
+ * @brief Timer Hall Sensor functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Hall Sensor functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure TIM HAL Sensor.
+ (+) De-initialize TIM HAL Sensor.
+ (+) Start the Hall Sensor Interface.
+ (+) Stop the Hall Sensor Interface.
+ (+) Start the Hall Sensor Interface and enable interrupts.
+ (+) Stop the Hall Sensor Interface and disable interrupts.
+ (+) Start the Hall Sensor Interface and enable DMA transfers.
+ (+) Stop the Hall Sensor Interface and disable DMA transfers.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
+ * @param htim : TIM Encoder Interface handle
+ * @param sConfig : TIM Hall Sensor configuration structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
+{
+ TIM_OC_InitTypeDef OC_Config;
+
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIMEx_HallSensor_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Configure the Time base in the Encoder Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
+ TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+ /* Set the IC1PSC value */
+ htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
+
+ /* Enable the Hall sensor interface (XOR function of the three inputs) */
+ htim->Instance->CR2 |= TIM_CR2_TI1S;
+
+ /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+
+ /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+
+ /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
+ OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
+ OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+ OC_Config.OCMode = TIM_OCMODE_PWM2;
+ OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+ OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+ OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+ OC_Config.Pulse = sConfig->Commutation_Delay;
+
+ TIM_OC2_SetConfig(htim->Instance, &OC_Config);
+
+ /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
+ register to 101 */
+ htim->Instance->CR2 &= ~TIM_CR2_MMS;
+ htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM Hall Sensor interface
+ * @param htim : TIM Hall Sensor handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIMEx_HallSensor_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Hall Sensor MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Hall Sensor MSP.
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface.
+ * @param htim : TIM Hall Sensor handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall sensor Interface.
+ * @param htim : TIM Hall Sensor handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channel 1
+ (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
+ * @param htim : TIM Hall Sensor handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+ /* Enable the capture compare Interrupts 1 event */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
+ * @param htim : TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channel 1
+ (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts event */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface in DMA mode.
+ * @param htim : TIM Hall Sensor handle
+ * @param pData : The destination Buffer address.
+ * @param Length : The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0 ) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Set the DMA Input Capture 1 Callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel for Capture 1*/
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
+
+ /* Enable the capture compare 1 Interrupt */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall Sensor Interface in DMA mode.
+ * @param htim : TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channel 1
+ (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+
+ /* Disable the capture compare Interrupts 1 event */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+#if defined (STM32F100xB) || defined (STM32F100xE) || \
+ defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
+ defined (STM32F105xC) || defined (STM32F107xC)
+
+/** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
+ * @brief Timer Complementary Output Compare functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary Output Compare functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary Output Compare/PWM.
+ (+) Stop the Complementary Output Compare/PWM.
+ (+) Start the Complementary Output Compare/PWM and enable interrupts.
+ (+) Stop the Complementary Output Compare/PWM and disable interrupts.
+ (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
+ (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the TIM Output Compare signal generation on the complementary
+ * output.
+ * @param htim : TIM Output Compare handle
+ * @param Channel : TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation on the complementary
+ * output.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode
+ * on the complementary output.
+ * @param htim : TIM OC handle
+ * @param Channel : TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the TIM Break interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode
+ * on the complementary output.
+ * @param htim : TIM Output Compare handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ tmpccer = htim->Instance->CCER;
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+ {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in DMA mode
+ * on the complementary output.
+ * @param htim : TIM Output Compare handle
+ * @param Channel : TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData : The source Buffer address.
+ * @param Length : The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0 ) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+{
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in DMA mode
+ * on the complementary output.
+ * @param htim : TIM Output Compare handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
+ * @brief Timer Complementary PWM functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary PWM functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary PWM.
+ (+) Stop the Complementary PWM.
+ (+) Start the Complementary PWM and enable interrupts.
+ (+) Stop the Complementary PWM and disable interrupts.
+ (+) Start the Complementary PWM and enable DMA transfers.
+ (+) Stop the Complementary PWM and disable DMA transfers.
+ (+) Start the Complementary Input Capture measurement.
+ (+) Stop the Complementary Input Capture.
+ (+) Start the Complementary Input Capture and enable interrupts.
+ (+) Stop the Complementary Input Capture and disable interrupts.
+ (+) Start the Complementary Input Capture and enable DMA transfers.
+ (+) Stop the Complementary Input Capture and disable DMA transfers.
+ (+) Start the Complementary One Pulse generation.
+ (+) Stop the Complementary One Pulse.
+ (+) Start the Complementary One Pulse and enable interrupts.
+ (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the PWM signal generation on the complementary output.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation on the complementary output.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the PWM signal generation in interrupt mode on the
+ * complementary output.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the TIM Break interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation in interrupt mode on the
+ * complementary output.
+ * @param htim : TIM handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ tmpccer = htim->Instance->CCER;
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+ {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM PWM signal generation in DMA mode on the
+ * complementary output
+ * @param htim : TIM handle
+ * @param Channel : TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData : The source Buffer address.
+ * @param Length : The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0 ) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
+ * output
+ * @param htim : TIM handle
+ * @param Channel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
+ * @brief Timer Complementary One Pulse functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary One Pulse functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary One Pulse generation.
+ (+) Stop the Complementary One Pulse.
+ (+) Start the Complementary One Pulse and enable interrupts.
+ (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the TIM One Pulse signal generation on the complemetary
+ * output.
+ * @param htim : TIM One Pulse handle
+ * @param OutputChannel : TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Enable the complementary One Pulse output */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation on the complementary
+ * output.
+ * @param htim : TIM One Pulse handle
+ * @param OutputChannel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Disable the complementary One Pulse output */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
+ * complementary channel.
+ * @param htim : TIM One Pulse handle
+ * @param OutputChannel : TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+ /* Enable the complementary One Pulse output */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+
+/**
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
+ * complementary channel.
+ * @param htim : TIM One Pulse handle
+ * @param OutputChannel : TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+ /* Disable the complementary One Pulse output */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
+ /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
+ /* defined(STM32F105xC) || defined(STM32F107xC) */
+
+/** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Configure the commutation event in case of use of the Hall sensor interface.
+ (+) Configure Complementary channels, break features and dead time.
+ (+) Configure Master synchronization.
+
+@endverbatim
+ * @{
+ */
+
+#if defined (STM32F100xB) || defined (STM32F100xE) || \
+ defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
+ defined (STM32F105xC) || defined (STM32F107xC)
+
+/**
+ * @brief Configure the TIM commutation event sequence.
+ * @note: this function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI input of the Timer,
+ * the typical use of this feature is with the use of another Timer(interface Timer)
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.
+ * @param htim : TIM handle
+ * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource : the Commutation Event source
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the TIM commutation event sequence with interrupt.
+ * @note: this function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI input of the Timer,
+ * the typical use of this feature is with the use of another Timer(interface Timer)
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.
+ * @param htim : TIM handle
+ * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource : the Commutation Event source
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ /* Enable the Commutation Interrupt Request */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the TIM commutation event sequence with DMA.
+ * @note: this function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI input of the Timer,
+ * the typical use of this feature is with the use of another Timer(interface Timer)
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.
+ * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
+ * @param htim : TIM handle
+ * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource : the Commutation Event source
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ /* Enable the Commutation DMA Request */
+ /* Set the DMA Commutation Callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the Commutation DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+ * and the AOE(automatic output enable).
+ * @param htim : TIM handle
+ * @param sBreakDeadTimeConfig : pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
+ * contains the BDTR Register configuration information for the TIM peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+ TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+ assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+ assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+ assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
+ assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+ assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+ assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+ htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode |
+ sBreakDeadTimeConfig->OffStateIDLEMode |
+ sBreakDeadTimeConfig->LockLevel |
+ sBreakDeadTimeConfig->DeadTime |
+ sBreakDeadTimeConfig->BreakState |
+ sBreakDeadTimeConfig->BreakPolarity |
+ sBreakDeadTimeConfig->AutomaticOutput;
+
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
+ /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
+ /* defined(STM32F105xC) || defined(STM32F107xC) */
+
+/**
+ * @brief Configures the TIM in master mode.
+ * @param htim : TIM handle.
+ * @param sMasterConfig : pointer to a TIM_MasterConfigTypeDef structure that
+ * contains the selected trigger output (TRGO) and the Master/Slave
+ * mode.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+ assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Reset the MMS Bits */
+ htim->Instance->CR2 &= ~TIM_CR2_MMS;
+ /* Select the TRGO source */
+ htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
+
+ /* Reset the MSM Bit */
+ htim->Instance->SMCR &= ~TIM_SMCR_MSM;
+ /* Set or Reset the MSM Bit */
+ htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
+ * @brief Extension Callbacks functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Extension Callbacks functions #####
+ ==============================================================================
+ [..]
+ This section provides Extension TIM callback functions:
+ (+) Timer Commutation callback
+ (+) Timer Break callback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Hall commutation changed callback in non blocking mode
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_CommutationCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Break detection callback in non blocking mode
+ * @param htim : TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_BreakCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief TIM DMA Commutation callback.
+ * @param hdma : pointer to DMA handle.
+ * @retval None
+ */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ HAL_TIMEx_CommutationCallback(htim);
+}
+
+/**
+ * @}
+ */
+
+#if defined (STM32F100xB) || defined (STM32F100xE) || \
+ defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
+ defined (STM32F105xC) || defined (STM32F107xC)
+
+/** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions
+ * @brief Extension Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Extension Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the TIM Hall Sensor interface state
+ * @param htim : TIM Hall Sensor handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @}
+ */
+#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
+ /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
+ /* defined(STM32F105xC) || defined(STM32F107xC) */
+
+/**
+ * @}
+ */
+
+#if defined (STM32F100xB) || defined (STM32F100xE) || \
+ defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
+ defined (STM32F105xC) || defined (STM32F107xC)
+
+/** @addtogroup TIMEx_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel xN.
+ * @param TIMx to select the TIM peripheral
+ * @param Channel : specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_Channel_1: TIM Channel 1
+ * @arg TIM_Channel_2: TIM Channel 2
+ * @arg TIM_Channel_3: TIM Channel 3
+ * @param ChannelNState : specifies the TIM Channel CCxNE bit new state.
+ * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
+ * @retval None
+ */
+static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
+{
+ uint32_t tmp = 0;
+
+ tmp = TIM_CCER_CC1NE << Channel;
+
+ /* Reset the CCxNE Bit */
+ TIMx->CCER &= ~tmp;
+
+ /* Set or reset the CCxNE Bit */
+ TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
+}
+
+/**
+ * @}
+ */
+
+#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
+ /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
+ /* defined(STM32F105xC) || defined(STM32F107xC) */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1921 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_uart.c
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief UART HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Errors functions
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The UART HAL driver can be used as follows:
+
+ (#) Declare a UART_HandleTypeDef handle structure.
+
+ (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
+ (##) Enable the USARTx interface clock.
+ (##) UART pins configuration:
+ (+++) Enable the clock for the UART GPIOs.
+ (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
+ (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
+ and HAL_UART_Receive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
+ and HAL_UART_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required
+ Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the DMA Tx/Rx channel.
+ (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
+ (used for last byte sending completion detection in DMA non circular mode)
+
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
+ flow control and Mode(Receiver/Transmitter) in the huart Init structure.
+
+ (#) For the UART asynchronous mode, initialize the UART registers by calling
+ the HAL_UART_Init() API.
+
+ (#) For the UART Half duplex mode, initialize the UART registers by calling
+ the HAL_HalfDuplex_Init() API.
+
+ (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.
+
+ (#) For the Multi-Processor mode, initialize the UART registers by calling
+ the HAL_MultiProcessor_Init() API.
+
+ [..]
+ (@) The specific UART interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit
+ and receive process.
+
+ [..]
+ (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the
+ low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customed
+ HAL_UART_MspInit() API.
+
+ [..]
+ Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_UART_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
+ (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
+ (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_RxCpltCallback
+ (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_UART_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
+ (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
+ (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_RxCpltCallback
+ (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_UART_ErrorCallback
+ (+) Pause the DMA Transfer using HAL_UART_DMAPause()
+ (+) Resume the DMA Transfer using HAL_UART_DMAResume()
+ (+) Stop the DMA Transfer using HAL_UART_DMAStop()
+
+ *** UART HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in UART HAL driver.
+
+ (+) __HAL_UART_ENABLE: Enable the UART peripheral
+ (+) __HAL_UART_DISABLE: Disable the UART peripheral
+ (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
+ (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
+ (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
+ (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
+ (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not
+
+ [..]
+ (@) You can refer to the UART HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup UART UART
+ * @brief HAL UART module driver
+ * @{
+ */
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup UART_Private_Functions UART Private Functions
+ * @{
+ */
+static void UART_SetConfig (UART_HandleTypeDef *huart);
+static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
+static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
+static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAError(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup UART_Exported_Functions UART Exported Functions
+ * @{
+ */
+
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+ in asynchronous mode.
+ (+) For the asynchronous mode only these parameters can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Stop Bit
+ (++) Parity
+ (++) Hardware flow control
+ (++) Receiver/transmitter modes
+ [..]
+ The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs
+ follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor
+ configuration procedures (details for the procedures are available in reference manuals
+ (RM0008 for STM32F10Xxx MCUs and RM0041 for STM32F100xx MCUs)).
+
+
+@endverbatim
+ * @{
+ */
+
+/*
+ Additionnal remark: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),
+ the possible UART frame formats are as listed in the following table:
+ +-------------------------------------------------------------+
+ | M bit | PCE bit | UART frame |
+ |---------------------|---------------------------------------|
+ | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|-----------|---------------------------------------|
+ | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|-----------|---------------------------------------|
+ | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|-----------|---------------------------------------|
+ | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ +-------------------------------------------------------------+
+*/
+
+/**
+ * @brief Initializes the UART mode according to the specified parameters in
+ * the UART_InitTypeDef and create the associated handle.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+ {
+ /* The hardware flow control is available only for USART1, USART2, USART3 */
+ assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
+ assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
+ }
+ else
+ {
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+ }
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+ assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+
+ if(huart->State == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_UART_MspInit(huart);
+ }
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Disable the peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ UART_SetConfig(huart);
+
+ /* In asynchronous mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+ /* Enable the peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* Initialize the UART state */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->State= HAL_UART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the half-duplex mode according to the specified
+ * parameters in the UART_InitTypeDef and create the associated handle.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check UART instance */
+ assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+ assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+
+ if(huart->State == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_UART_MspInit(huart);
+ }
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Disable the peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ UART_SetConfig(huart);
+
+ /* In half-duplex mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
+
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
+
+ /* Enable the peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* Initialize the UART state*/
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->State= HAL_UART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the LIN mode according to the specified
+ * parameters in the UART_InitTypeDef and create the associated handle.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param BreakDetectLength: Specifies the LIN break detection length.
+ * This parameter can be one of the following values:
+ * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
+ * @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the LIN UART instance */
+ assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+ /* Check the Break detection length parameter */
+ assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
+ assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength));
+ assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling));
+
+ if(huart->State == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_UART_MspInit(huart);
+ }
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Disable the peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ UART_SetConfig(huart);
+
+ /* In LIN mode, the following bits must be kept cleared:
+ - CLKEN bits in the USART_CR2 register,
+ - SCEN and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
+
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+ SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
+
+ /* Set the USART LIN Break detection length. */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
+
+ /* Enable the peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* Initialize the UART state*/
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->State= HAL_UART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the Multi-Processor mode according to the specified
+ * parameters in the UART_InitTypeDef and create the associated handle.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param Address: UART node address
+ * @param WakeUpMethod: specifies the UART wakeup method.
+ * This parameter can be one of the following values:
+ * @arg UART_WAKEUPMETHOD_IDLELINE: Wakeup by an idle line detection
+ * @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wakeup by an address mark
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check UART instance capabilities */
+ assert_param(IS_UART_MULTIPROCESSOR_INSTANCE(huart->Instance));
+
+ /* Check the Address & wake up method parameters */
+ assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
+ assert_param(IS_UART_ADDRESS(Address));
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+ assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+
+ if(huart->State == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_UART_MspInit(huart);
+ }
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Disable the peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ UART_SetConfig(huart);
+
+ /* In Multi-Processor mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register */
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+ /* Set the USART address node */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, Address);
+
+ /* Set the wake up method by setting the WAKE bit in the CR1 register */
+ MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
+
+ /* Enable the peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* Initialize the UART state */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->State= HAL_UART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the UART peripheral.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ huart->Instance->CR1 = 0x0;
+ huart->Instance->CR2 = 0x0;
+ huart->Instance->CR3 = 0x0;
+
+ /* DeInit the low level hardware */
+ HAL_UART_MspDeInit(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->State = HAL_UART_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief UART MSP Init.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval None
+ */
+ __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_UART_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief UART MSP DeInit.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval None
+ */
+ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_UART_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions
+ * @brief UART Transmit and Receive functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the UART asynchronous
+ and Half duplex data transfers.
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) Non blocking mode: The communication is performed using Interrupts
+ or DMA, these APIs return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or receive process.
+ The HAL_UART_ErrorCallback() user callback will be executed when
+ a communication error is detected.
+
+ (#) Blocking mode APIs are:
+ (++) HAL_UART_Transmit()
+ (++) HAL_UART_Receive()
+
+ (#) Non Blocking mode APIs with Interrupt are:
+ (++) HAL_UART_Transmit_IT()
+ (++) HAL_UART_Receive_IT()
+ (++) HAL_UART_IRQHandler()
+
+ (#) Non Blocking mode functions with DMA are:
+ (++) HAL_UART_Transmit_DMA()
+ (++) HAL_UART_Receive_DMA()
+ (++) HAL_UART_DMAPause()
+ (++) HAL_UART_DMAResume()
+ (++) HAL_UART_DMAStop()
+
+ (#) A set of Transfer Complete Callbacks are provided in non blocking mode:
+ (++) HAL_UART_TxHalfCpltCallback()
+ (++) HAL_UART_TxCpltCallback()
+ (++) HAL_UART_RxHalfCpltCallback()
+ (++) HAL_UART_RxCpltCallback()
+ (++) HAL_UART_ErrorCallback()
+
+ [..]
+ (@) In the Half duplex communication, it is forbidden to run the transmit
+ and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX
+ can't be useful.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sends an amount of data in blocking mode.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp;
+ uint32_t tmp_state = 0;
+
+ tmp_state = huart->State;
+ if((tmp_state == HAL_UART_STATE_READY) || (tmp_state == HAL_UART_STATE_BUSY_RX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ /* Check if a non-blocking receive process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX;
+ }
+
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+ while(huart->TxXferCount > 0)
+ {
+ huart->TxXferCount--;
+ if(huart->Init.WordLength == UART_WORDLENGTH_9B)
+ {
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ tmp = (uint16_t*) pData;
+ huart->Instance->DR = (*tmp & (uint16_t)0x01FF);
+ if(huart->Init.Parity == HAL_UART_PARITY_NONE)
+ {
+ pData +=2;
+ }
+ else
+ {
+ pData +=1;
+ }
+ }
+ else
+ {
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ huart->Instance->DR = (*pData++ & (uint8_t)0xFF);
+ }
+ }
+
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Check if a non-blocking receive process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_RX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receives an amount of data in blocking mode.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be received
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp;
+ uint32_t tmp_state = 0;
+
+ tmp_state = huart->State;
+ if((tmp_state == HAL_UART_STATE_READY) || (tmp_state == HAL_UART_STATE_BUSY_TX))
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ /* Check if a non-blocking transmit process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_BUSY_RX;
+ }
+
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+
+ /* Check the remain data to be received */
+ while(huart->RxXferCount > 0)
+ {
+ huart->RxXferCount--;
+ if(huart->Init.WordLength == UART_WORDLENGTH_9B)
+ {
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ tmp = (uint16_t*) pData ;
+ if(huart->Init.Parity == HAL_UART_PARITY_NONE)
+ {
+ *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
+ pData +=2;
+ }
+ else
+ {
+ *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
+ pData +=1;
+ }
+
+ }
+ else
+ {
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if(huart->Init.Parity == HAL_UART_PARITY_NONE)
+ {
+ *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
+ }
+ else
+ {
+ *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
+ }
+
+ }
+ }
+
+ /* Check if a non-blocking transmit process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_READY;
+ }
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sends an amount of data in non blocking mode.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ uint32_t tmp_state = 0;
+
+ tmp_state = huart->State;
+ if((tmp_state == HAL_UART_STATE_READY) || (tmp_state == HAL_UART_STATE_BUSY_RX))
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->pTxBuffPtr = pData;
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ /* Check if a receive process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Transmit data register empty Interrupt */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receives an amount of data in non blocking mode
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ uint32_t tmp_state = 0;
+
+ tmp_state = huart->State;
+ if((tmp_state == HAL_UART_STATE_READY) || (tmp_state == HAL_UART_STATE_BUSY_TX))
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ /* Check if a transmit process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_BUSY_RX;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Parity Error Interrupt */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_PE);
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
+
+ /* Enable the UART Data Register not empty Interrupt */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sends an amount of data in non blocking mode.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+ uint32_t tmp_state = 0;
+
+ tmp_state = huart->State;
+ if((tmp_state == HAL_UART_STATE_READY) || (tmp_state == HAL_UART_STATE_BUSY_RX))
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->pTxBuffPtr = pData;
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ /* Check if a receive process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX;
+ }
+
+ /* Set the UART DMA transfer complete callback */
+ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
+
+ /* Set the UART DMA Half transfer complete callback */
+ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
+
+ /* Set the DMA error callback */
+ huart->hdmatx->XferErrorCallback = UART_DMAError;
+
+ /* Enable the UART transmit DMA channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->DR, Size);
+
+ /* Clear the TC flag in the SR register by writing 0 to it */
+ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the UART CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receives an amount of data in non blocking mode.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be received
+ * @note When the UART parity is enabled (PCE = 1), the received data contain
+ * the parity bit (MSB position)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+ uint32_t tmp_state = 0;
+
+ tmp_state = huart->State;
+ if((tmp_state == HAL_UART_STATE_READY) || (tmp_state == HAL_UART_STATE_BUSY_TX))
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ /* Check if a transmit process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_BUSY_RX;
+ }
+
+ /* Set the UART DMA transfer complete callback */
+ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+
+ /* Set the UART DMA Half transfer complete callback */
+ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+
+ /* Set the DMA error callback */
+ huart->hdmarx->XferErrorCallback = UART_DMAError;
+
+ /* Enable the DMA channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the UART CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Pauses the DMA Transfer.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ if(huart->State == HAL_UART_STATE_BUSY_TX)
+ {
+ /* Disable the UART DMA Tx request */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ }
+ else if(huart->State == HAL_UART_STATE_BUSY_RX)
+ {
+ /* Disable the UART DMA Rx request */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ }
+ else if (huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ /* Disable the UART DMA Tx & Rx requests */
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR));
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_ERROR;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the DMA Transfer.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ if(huart->State == HAL_UART_STATE_BUSY_TX)
+ {
+ /* Enable the UART DMA Tx request */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ }
+ else if(huart->State == HAL_UART_STATE_BUSY_RX)
+ {
+ /* Clear the Overrun flag before resumming the Rx transfer*/
+ __HAL_UART_CLEAR_OREFLAG(huart);
+ /* Enable the UART DMA Rx request */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ }
+ else if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ /* Clear the Overrun flag before resumming the Rx transfer*/
+ __HAL_UART_CLEAR_OREFLAG(huart);
+ /* Enable the UART DMA Tx & Rx request */
+ SET_BIT(huart->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR));
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_ERROR;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the DMA Transfer.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
+{
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():
+ when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
+ */
+
+ /* Disable the UART Tx/Rx DMA requests */
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR));
+
+ /* Abort the UART DMA tx channel */
+ if(huart->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(huart->hdmatx);
+ }
+ /* Abort the UART DMA rx channel */
+ if(huart->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(huart->hdmarx);
+ }
+
+ huart->State = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles UART interrupt request.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval None
+ */
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
+{
+ uint32_t tmp_flag = 0, tmp_it_source = 0;
+
+ tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_PE);
+ tmp_it_source = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE);
+ /* UART parity error interrupt occurred ------------------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ }
+
+ tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_FE);
+ tmp_it_source = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR);
+ /* UART frame error interrupt occurred -------------------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ }
+
+ tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_NE);
+ /* UART noise error interrupt occurred -------------------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ }
+
+ tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_ORE);
+ /* UART Over-Run interrupt occurred ----------------------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_ORE;
+ }
+
+ tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE);
+ tmp_it_source = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE);
+ /* UART in mode Receiver ---------------------------------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ UART_Receive_IT(huart);
+ }
+
+ tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_TXE);
+ tmp_it_source = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE);
+ /* UART in mode Transmitter ------------------------------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ UART_Transmit_IT(huart);
+ }
+
+ tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_TC);
+ tmp_it_source = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC);
+ /* UART in mode Transmitter end --------------------------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ UART_EndTransmit_IT(huart);
+ }
+
+ if(huart->ErrorCode != HAL_UART_ERROR_NONE)
+ {
+ /* Clear all the error flag at once */
+ __HAL_UART_CLEAR_PEFLAG(huart);
+
+ /* Set the UART state ready to be able to start again the process */
+ huart->State = HAL_UART_STATE_READY;
+
+ HAL_UART_ErrorCallback(huart);
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callbacks.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval None
+ */
+ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_UART_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callbacks.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval None
+ */
+ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_UART_TxHalfCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval None
+ */
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_UART_RxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callbacks.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval None
+ */
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_UART_RxHalfCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief UART error callbacks.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval None
+ */
+ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_UART_ErrorCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
+ * @brief UART control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the UART:
+ (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character.
+ (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode.
+ (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software.
+ (+) HAL_HalfDuplex_EnableTransmitter() API to enable the UART transmitter and disables the UART receiver in Half Duplex mode
+ (+) HAL_HalfDuplex_EnableReceiver() API to enable the UART receiver and disables the UART transmitter in Half Duplex mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmits break characters.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
+{
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Send break characters */
+ SET_BIT(huart->Instance->CR1, USART_CR1_SBK);
+
+ huart->State = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enters the UART in mute mode.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
+{
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Enable the USART mute mode by setting the RWU bit in the CR1 register */
+ SET_BIT(huart->Instance->CR1, USART_CR1_RWU);
+
+ huart->State = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Exits the UART mute mode: wake up software.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart)
+{
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU);
+
+ huart->State = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables the UART transmitter and disables the UART receiver.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Clear TE and RE bits */
+ /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
+ MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_TE | USART_CR1_RE), USART_CR1_TE);
+
+ huart->State = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables the UART receiver and disables the UART transmitter.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Clear TE and RE bits */
+ /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
+ MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_TE | USART_CR1_RE), USART_CR1_RE);
+
+ huart->State = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions
+ * @brief UART State and Errors functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Errors functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to return the State of
+ UART communication process, return Peripheral Errors occurred during communication
+ process
+ (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral.
+ (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the UART state.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL state
+ */
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
+{
+ return huart->State;
+}
+
+/**
+* @brief Return the UART error code
+* @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART.
+* @retval UART Error Code
+*/
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
+{
+ return huart->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Private_Functions UART Private Functions
+ * @brief UART Private functions
+ * @{
+ */
+/**
+ * @brief DMA UART transmit process complete callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* DMA Normal mode*/
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ huart->TxXferCount = 0;
+
+ /* Disable the DMA transfer for transmit request by setting the DMAT bit
+ in the UART CR3 register */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+ }
+ /* DMA Circular mode */
+ else
+ {
+ HAL_UART_TxCpltCallback(huart);
+ }
+}
+
+/**
+ * @brief DMA UART transmit process half complete callback
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_UART_TxHalfCpltCallback(huart);
+}
+
+/**
+ * @brief DMA UART receive process complete callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* DMA Normal mode*/
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ huart->RxXferCount = 0;
+
+ /* Disable the DMA transfer for the receiver request by setting the DMAR bit
+ in the UART CR3 register */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Check if a transmit process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_READY;
+ }
+ }
+ HAL_UART_RxCpltCallback(huart);
+}
+
+/**
+ * @brief DMA UART receive process half complete callback
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_UART_RxHalfCpltCallback(huart);
+}
+
+/**
+ * @brief DMA UART communication error callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void UART_DMAError(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ huart->RxXferCount = 0;
+ huart->TxXferCount = 0;
+ huart->State= HAL_UART_STATE_READY;
+ huart->ErrorCode |= HAL_UART_ERROR_DMA;
+ HAL_UART_ErrorCallback(huart);
+}
+
+/**
+ * @brief This function handles UART Communication Timeout.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param Flag: specifies the UART flag to check.
+ * @param Status: The new Flag status (SET or RESET).
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_UART_GET_FLAG(huart, Flag) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
+ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
+ __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
+ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+
+ huart->State= HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_UART_GET_FLAG(huart, Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
+ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
+ __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
+ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+
+ huart->State= HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Sends an amount of data in non blocking mode.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
+{
+ uint16_t* tmp;
+ uint32_t tmp_state = 0;
+
+ tmp_state = huart->State;
+ if((tmp_state == HAL_UART_STATE_BUSY_TX) || (tmp_state == HAL_UART_STATE_BUSY_TX_RX))
+ {
+ if(huart->Init.WordLength == UART_WORDLENGTH_9B)
+ {
+ tmp = (uint16_t*) huart->pTxBuffPtr;
+ huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
+ if(huart->Init.Parity == HAL_UART_PARITY_NONE)
+ {
+ huart->pTxBuffPtr += 2;
+ }
+ else
+ {
+ huart->pTxBuffPtr += 1;
+ }
+ }
+ else
+ {
+ huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
+ }
+
+ if(--huart->TxXferCount == 0)
+ {
+ /* Disable the UART Transmit Complete Interrupt */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+ }
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Wraps up transmission in non blocking mode.
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable the UART Transmit Complete Interrupt */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
+
+ /* Check if a receive process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_RX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_READY;
+ }
+
+ HAL_UART_TxCpltCallback(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives an amount of data in non blocking mode
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
+{
+ uint16_t* tmp;
+ uint32_t tmp_state = 0;
+
+ tmp_state = huart->State;
+ if((tmp_state == HAL_UART_STATE_BUSY_RX) || (tmp_state == HAL_UART_STATE_BUSY_TX_RX))
+ {
+ if(huart->Init.WordLength == UART_WORDLENGTH_9B)
+ {
+ tmp = (uint16_t*) huart->pRxBuffPtr;
+ if(huart->Init.Parity == HAL_UART_PARITY_NONE)
+ {
+ *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
+ huart->pRxBuffPtr += 2;
+ }
+ else
+ {
+ *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
+ huart->pRxBuffPtr += 1;
+ }
+ }
+ else
+ {
+ if(huart->Init.Parity == HAL_UART_PARITY_NONE)
+ {
+ *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
+ }
+ else
+ {
+ *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
+ }
+ }
+
+ if(--huart->RxXferCount == 0)
+ {
+ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
+
+ /* Check if a transmit process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX;
+ }
+ else
+ {
+ /* Disable the UART Parity Error Interrupt */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+
+ huart->State = HAL_UART_STATE_READY;
+ }
+ HAL_UART_RxCpltCallback(huart);
+
+ return HAL_OK;
+ }
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Configures the UART peripheral.
+ * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval None
+ */
+static void UART_SetConfig(UART_HandleTypeDef *huart)
+{
+ uint32_t tmpreg = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
+ assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+ assert_param(IS_UART_PARITY(huart->Init.Parity));
+ assert_param(IS_UART_MODE(huart->Init.Mode));
+
+ /*------- UART-associated USART registers setting : CR2 Configuration ------*/
+ /* Configure the UART Stop Bits: Set STOP[13:12] bits according
+ * to huart->Init.StopBits value */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+
+ /*------- UART-associated USART registers setting : CR1 Configuration ------*/
+ /* Configure the UART Word Length, Parity and mode:
+ Set the M bits according to huart->Init.WordLength value
+ Set PCE and PS bits according to huart->Init.Parity value
+ Set TE and RE bits according to huart->Init.Mode value */
+ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode ;
+ MODIFY_REG(huart->Instance->CR1,
+ (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE),
+ tmpreg);
+
+ /*------- UART-associated USART registers setting : CR3 Configuration ------*/
+ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
+ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
+
+ /*------- UART-associated USART registers setting : BRR Configuration ------*/
+ if((huart->Instance == USART1))
+ {
+ huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
+ }
+ else
+ {
+ huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
+ }
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_usart.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_usart.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1893 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_usart.c
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief USART HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Errors functions
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The USART HAL driver can be used as follows:
+
+ (#) Declare a USART_HandleTypeDef handle structure.
+ (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
+ (##) Enable the USARTx interface clock.
+ (##) USART pins configuration:
+ (+++) Enable the clock for the USART GPIOs.
+ (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
+ (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
+ HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
+ HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initilalized DMA handle to the USART DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+ (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
+ (used for last byte sending completion detection in DMA non circular mode)
+
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
+ flow control and Mode(Receiver/Transmitter) in the husart Init structure.
+
+ (#) Initialize the USART registers by calling the HAL_USART_Init() API:
+ (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customed HAL_USART_MspInit(&husart) API.
+
+ -@@- The specific USART interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
+
+ (#) Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_USART_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_USART_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
+ (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
+ (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_RxCpltCallback
+ (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_USART_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA()
+ (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA()
+ (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_RxCpltCallback
+ (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_USART_ErrorCallback
+ (+) Pause the DMA Transfer using HAL_USART_DMAPause()
+ (+) Resume the DMA Transfer using HAL_USART_DMAResume()
+ (+) Stop the DMA Transfer using HAL_USART_DMAStop()
+
+ *** USART HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in USART HAL driver.
+
+ (+) __HAL_USART_ENABLE: Enable the USART peripheral
+ (+) __HAL_USART_DISABLE: Disable the USART peripheral
+ (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
+ (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
+ (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
+ (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt
+ (+) __HAL_USART_GET_IT_SOURCE: Check whether the specified USART interrupt has occurred or not
+
+ [..]
+ (@) You can refer to the USART HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup USART USART
+ * @brief HAL USART Synchronous module driver
+ * @{
+ */
+#ifdef HAL_USART_MODULE_ENABLED
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup USART_Private_Constants USART Private Constants
+ * @{
+ */
+#define DUMMY_DATA 0xFFFF
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup USART_Private_Functions USART Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
+static void USART_SetConfig (USART_HandleTypeDef *husart);
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMAError(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+
+/** @defgroup USART_Exported_Functions USART Exported Functions
+ * @{
+ */
+
+/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USART
+ in asynchronous and in synchronous modes.
+ (+) For the asynchronous mode only these parameters can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Stop Bit
+ (++) Parity
+ (++) USART polarity
+ (++) USART phase
+ (++) USART LastBit
+ (++) Receiver/transmitter modes
+
+ [..]
+ The HAL_USART_Init() function follows the USART synchronous configuration
+ procedure (details for the procedure are available in reference manuals
+ (RM0008 for STM32F10Xxx MCUs and RM0041 for STM32F100xx MCUs)).
+
+@endverbatim
+ * @{
+ */
+
+/*
+ Additionnal remark: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),
+ the possible USART frame formats are as listed in the following table:
+ +-------------------------------------------------------------+
+ | M bit | PCE bit | USART frame |
+ |---------------------|---------------------------------------|
+ | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|-----------|---------------------------------------|
+ | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|-----------|---------------------------------------|
+ | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|-----------|---------------------------------------|
+ | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ +-------------------------------------------------------------+
+*/
+
+/**
+ * @brief Initializes the USART mode according to the specified
+ * parameters in the USART_InitTypeDef and create the associated handle.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
+{
+ /* Check the USART handle allocation */
+ if(husart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_USART_INSTANCE(husart->Instance));
+
+ if(husart->State == HAL_USART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ husart->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_USART_MspInit(husart);
+ }
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ /* Set the USART Communication parameters */
+ USART_SetConfig(husart);
+
+ /* In USART mode, the following bits must be kept cleared:
+ - LINEN bit in the USART_CR2 register
+ - HDSEL, SCEN and IREN bits in the USART_CR3 register */
+ CLEAR_BIT(husart->Instance->CR2, USART_CR2_LINEN);
+ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
+
+ /* Enable the Peripheral */
+ __HAL_USART_ENABLE(husart);
+
+ /* Initialize the USART state */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State= HAL_USART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the USART peripheral.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
+{
+ /* Check the USART handle allocation */
+ if(husart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_USART_INSTANCE(husart->Instance));
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_USART_DISABLE(husart);
+
+ /* DeInit the low level hardware */
+ HAL_USART_MspDeInit(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USART MSP Init.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+ __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_USART_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief USART MSP DeInit.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_USART_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Functions_Group2 IO operation functions
+ * @brief USART Transmit and Receive functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the USART synchronous
+ data transfers.
+
+ [..]
+ The USART supports master mode only: it cannot receive or send data related to an input
+ clock (SCLK is always an output).
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback()
+ user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_USART_ErrorCallback() user callback will be executed when a communication
+ error is detected
+
+ (#) Blocking mode APIs are :
+ (++) HAL_USART_Transmit() in simplex mode
+ (++) HAL_USART_Receive() in full duplex receive only
+ (++) HAL_USART_TransmitReceive() in full duplex mode
+
+ (#) Non Blocking mode APIs with Interrupt are :
+ (++) HAL_USART_Transmit_IT()in simplex mode
+ (++) HAL_USART_Receive_IT() in full duplex receive only
+ (++) HAL_USART_TransmitReceive_IT() in full duplex mode
+ (++) HAL_USART_IRQHandler()
+
+ (#) Non Blocking mode functions with DMA are :
+ (++) HAL_USART_Transmit_DMA()in simplex mode
+ (++) HAL_USART_Receive_DMA() in full duplex receive only
+ (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
+ (++) HAL_USART_DMAPause()
+ (++) HAL_USART_DMAResume()
+ (++) HAL_USART_DMAStop()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_USART_TxHalfCpltCallback()
+ (++) HAL_USART_TxCpltCallback()
+ (++) HAL_USART_RxHalfCpltCallback()
+ (++) HAL_USART_RxCpltCallback()
+ (++) HAL_USART_ErrorCallback()
+ (++) HAL_USART_TxRxCpltCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Simplex Send an amount of data in blocking mode.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp=0;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX;
+
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+ while(husart->TxXferCount > 0)
+ {
+ husart->TxXferCount--;
+ if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+ {
+ /* Wait for TC flag in order to write data in DR */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ tmp = (uint16_t*) pTxData;
+ WRITE_REG(husart->Instance->DR, (*tmp & (uint16_t)0x01FF));
+ if(husart->Init.Parity == USART_PARITY_NONE)
+ {
+ pTxData += 2;
+ }
+ else
+ {
+ pTxData += 1;
+ }
+ }
+ else
+ {
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ WRITE_REG(husart->Instance->DR, (*pTxData++ & (uint8_t)0xFF));
+ }
+ }
+
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Receive an amount of data in blocking mode.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pRxData: Pointer to data buffer
+ * @param Size: Amount of data to be received
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp=0;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pRxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ husart->RxXferSize = Size;
+ husart->RxXferCount = Size;
+ /* Check the remain data to be received */
+ while(husart->RxXferCount > 0)
+ {
+ husart->RxXferCount--;
+ if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+ {
+ /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ /* Send dummy byte in order to generate clock */
+ WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x01FF));
+
+ /* Wait for RXNE Flag */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ tmp = (uint16_t*) pRxData ;
+ if(husart->Init.Parity == USART_PARITY_NONE)
+ {
+ *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
+ pRxData +=2;
+ }
+ else
+ {
+ *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
+ pRxData +=1;
+ }
+ }
+ else
+ {
+ /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Send Dummy Byte in order to generate clock */
+ WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x00FF));
+
+ /* Wait until RXNE flag is set to receive the byte */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if(husart->Init.Parity == USART_PARITY_NONE)
+ {
+ /* Receive data */
+ *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
+ }
+ else
+ {
+ /* Receive data */
+ *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
+ }
+
+ }
+ }
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData: Pointer to data transmitted buffer
+ * @param pRxData: Pointer to data received buffer
+ * @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp=0;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ husart->RxXferSize = Size;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+ husart->RxXferCount = Size;
+
+ /* Check the remain data to be received */
+ while(husart->TxXferCount > 0)
+ {
+ husart->TxXferCount--;
+ husart->RxXferCount--;
+ if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+ {
+ /* Wait for TC flag in order to write data in DR */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ tmp = (uint16_t*) pTxData;
+ WRITE_REG(husart->Instance->DR, (*tmp & (uint16_t)0x01FF));
+ if(husart->Init.Parity == USART_PARITY_NONE)
+ {
+ pTxData += 2;
+ }
+ else
+ {
+ pTxData += 1;
+ }
+
+ /* Wait for RXNE Flag */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ tmp = (uint16_t*) pRxData ;
+ if(husart->Init.Parity == USART_PARITY_NONE)
+ {
+ *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
+ pRxData += 2;
+ }
+ else
+ {
+ *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
+ pRxData += 1;
+ }
+ }
+ else
+ {
+ /* Wait for TC flag in order to write data in DR */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ WRITE_REG(husart->Instance->DR, (*pTxData++ & (uint8_t)0x00FF));
+
+ /* Wait for RXNE Flag */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if(husart->Init.Parity == USART_PARITY_NONE)
+ {
+ /* Receive data */
+ *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
+ }
+ else
+ {
+ /* Receive data */
+ *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
+ }
+ }
+ }
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Simplex Send an amount of data in non-blocking mode.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ * @note The USART errors are not managed to avoid the overrun error.
+ */
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
+{
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX;
+
+ /* The USART Error Interrupts: (Frame error, Noise error, Overrun error)
+ are not managed by the USART transmit process to avoid the overrun interrupt
+ when the USART mode is configured for transmit and receive "USART_MODE_TX_RX"
+ to benefit for the frame error and noise interrupts the USART mode should be
+ configured only for transmit "USART_MODE_TX"
+ The __HAL_USART_ENABLE_IT(husart, USART_IT_ERR) can be used to enable the Frame error,
+ Noise error interrupt */
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Transmit Data Register Empty Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Simplex Receive an amount of data in non-blocking mode.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pRxData: Pointer to data buffer
+ * @param Size: Amount of data to be received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
+{
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pRxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->RxXferCount = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Data Register not empty Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);
+
+ /* Enable the USART Parity Error Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
+
+ /* Send dummy byte in order to generate the clock for the slave to send data */
+ WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x01FF));
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData: Pointer to data transmitted buffer
+ * @param pRxData: Pointer to data received buffer
+ * @param Size: Amount of data to be received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->RxXferCount = Size;
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX_RX;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Data Register not empty Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);
+
+ /* Enable the USART Parity Error Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
+
+ /* Enable the USART Transmit Data Register Empty Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Simplex Send an amount of data in non-blocking mode.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
+{
+ uint32_t *tmp=0;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX;
+
+ /* Set the USART DMA transfer complete callback */
+ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+
+ /* Set the DMA error callback */
+ husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+ /* Enable the USART transmit DMA channel */
+ tmp = (uint32_t*)&pTxData;
+ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
+
+ /* Clear the TC flag in the SR register by writing 0 to it */
+ __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Receive an amount of data in non-blocking mode.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pRxData: Pointer to data buffer
+ * @param Size: Amount of data to be received
+ * @retval HAL status
+ * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
+ * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
+ */
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
+{
+ uint32_t *tmp=0;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pRxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->pTxBuffPtr = pRxData;
+ husart->TxXferSize = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ /* Set the USART DMA Rx transfer complete callback */
+ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+
+ /* Set the USART DMA Rx transfer error callback */
+ husart->hdmarx->XferErrorCallback = USART_DMAError;
+
+ /* Enable the USART receive DMA channel */
+ tmp = (uint32_t*)&pRxData;
+ HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size);
+
+ /* Enable the USART transmit DMA channel: the transmit channel is used in order
+ to generate in the non-blocking mode the clock to the slave device,
+ this mode isn't a simplex receive mode but a full-duplex receive one */
+ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
+
+ /* Clear the Overrun flag just before enabling the DMA Rx request: mandatory for the second transfer
+ when using the USART in circular mode */
+ __HAL_USART_CLEAR_OREFLAG(husart);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData: Pointer to data transmitted buffer
+ * @param pRxData: Pointer to data received buffer
+ * @param Size: Amount of data to be received
+ * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+ uint32_t *tmp=0;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX_RX;
+
+ /* Set the USART DMA Rx transfer complete callback */
+ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+
+ /* Set the USART DMA Tx transfer complete callback */
+ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+
+ /* Set the USART DMA Tx transfer error callback */
+ husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+ /* Set the USART DMA Rx transfer error callback */
+ husart->hdmarx->XferErrorCallback = USART_DMAError;
+
+ /* Enable the USART receive DMA channel */
+ tmp = (uint32_t*)&pRxData;
+ HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size);
+
+ /* Enable the USART transmit DMA channel */
+ tmp = (uint32_t*)&pTxData;
+ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
+
+ /* Clear the TC flag in the SR register by writing 0 to it */
+ __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
+
+ /* Clear the Overrun flag: mandatory for the second transfer in circular mode */
+ __HAL_USART_CLEAR_OREFLAG(husart);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Pauses the DMA Transfer.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
+{
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ /* Disable the USART DMA Tx request */
+ CLEAR_BIT(husart->Instance->CR3, (uint32_t)(USART_CR3_DMAT));
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the DMA Transfer.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
+{
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ /* Enable the USART DMA Tx request */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the DMA Transfer.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
+{
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback():
+ when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback()
+ */
+
+ /* Abort the USART DMA Tx channel */
+ if(husart->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(husart->hdmatx);
+ }
+ /* Abort the USART DMA Rx channel */
+ if(husart->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(husart->hdmarx);
+ }
+
+ /* Disable the USART Tx/Rx DMA requests */
+ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR));
+
+ husart->State = HAL_USART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles USART interrupt request.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
+{
+ uint32_t tmp_flag = 0, tmp_it_source = 0;
+
+ tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_PE);
+ tmp_it_source = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_PE);
+ /* USART parity error interrupt occurred -----------------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ husart->ErrorCode |= HAL_USART_ERROR_PE;
+ }
+
+ tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_FE);
+ tmp_it_source = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR);
+ /* USART frame error interrupt occurred ------------------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ husart->ErrorCode |= HAL_USART_ERROR_FE;
+ }
+
+ tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_NE);
+ /* USART noise error interrupt occurred ------------------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ husart->ErrorCode |= HAL_USART_ERROR_NE;
+ }
+
+ tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_ORE);
+ /* USART Over-Run interrupt occurred ---------------------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ husart->ErrorCode |= HAL_USART_ERROR_ORE;
+ }
+
+ if(husart->ErrorCode != HAL_USART_ERROR_NONE)
+ {
+ /* Clear all the error flag at once */
+ __HAL_USART_CLEAR_PEFLAG(husart);
+
+ /* Set the USART state ready to be able to start again the process */
+ husart->State = HAL_USART_STATE_READY;
+
+ HAL_USART_ErrorCallback(husart);
+ }
+
+ tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE);
+ tmp_it_source = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_RXNE);
+ /* USART in mode Receiver --------------------------------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ USART_Receive_IT(husart);
+ }
+ else
+ {
+ USART_TransmitReceive_IT(husart);
+ }
+ }
+
+ tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_TXE);
+ tmp_it_source = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TXE);
+ /* USART in mode Transmitter -----------------------------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ USART_Transmit_IT(husart);
+ }
+ else
+ {
+ USART_TransmitReceive_IT(husart);
+ }
+ }
+
+ tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_TC);
+ tmp_it_source = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC);
+ /* USART in mode Transmitter (transmission end) -----------------------------*/
+ if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ {
+ USART_EndTransmit_IT(husart);
+ }
+
+}
+
+
+/**
+ * @brief Tx Transfer completed callbacks.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_USART_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callbacks.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+ __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_USART_TxHalfCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_USART_RxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callbacks.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_USART_RxHalfCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx/Rx Transfers completed callback for the non-blocking process.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_USART_TxRxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief USART error callbacks.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+ __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_USART_ErrorCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief USART State and Errors functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Errors functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to return the State of
+ USART communication
+ process, return Peripheral Errors occurred during communication process
+ (+) HAL_USART_GetState() API can be helpful to check in run-time the state
+ of the USART peripheral.
+ (+) HAL_USART_GetError() check in run-time errors that could be occurred during
+ communication.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the USART state.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL state
+ */
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
+{
+ return husart->State;
+}
+
+/**
+ * @brief Return the USART error code
+ * @param husart : pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART.
+ * @retval USART Error Code
+ */
+uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
+{
+ return husart->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_Functions USART Private Functions
+ * @brief USART Private functions
+ * @{
+ */
+/**
+ * @brief DMA USART transmit process complete callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ husart->TxXferCount = 0;
+
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the USART CR3 register */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+ }
+ }
+ /* DMA Circular mode */
+ else
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ HAL_USART_TxCpltCallback(husart);
+ }
+ }
+}
+
+/**
+ * @brief DMA USART transmit process half complete callback
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_USART_TxHalfCpltCallback(husart);
+}
+
+/**
+ * @brief DMA USART receive process complete callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ husart->RxXferCount = 0;
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ /* Disable the DMA transfer for the receiver requests by setting the DMAR bit
+ in the USART CR3 register */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ husart->State= HAL_USART_STATE_READY;
+ HAL_USART_RxCpltCallback(husart);
+ }
+ /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/
+ else
+ {
+ /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit
+ in the USART CR3 register */
+ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR));
+
+ husart->State= HAL_USART_STATE_READY;
+ HAL_USART_TxRxCpltCallback(husart);
+ }
+ }
+ /* DMA circular mode */
+ else
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ HAL_USART_RxCpltCallback(husart);
+ }
+ /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/
+ else
+ {
+ HAL_USART_TxRxCpltCallback(husart);
+ }
+ }
+}
+
+/**
+ * @brief DMA USART receive process half complete callback
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_USART_RxHalfCpltCallback(husart);
+}
+
+/**
+ * @brief DMA USART communication error callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void USART_DMAError(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ husart->RxXferCount = 0;
+ husart->TxXferCount = 0;
+ husart->ErrorCode |= HAL_USART_ERROR_DMA;
+ husart->State= HAL_USART_STATE_READY;
+
+ HAL_USART_ErrorCallback(husart);
+}
+
+/**
+ * @brief This function handles USART Communication Timeout.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param Flag: specifies the USART flag to check.
+ * @param Status: The new Flag status (SET or RESET).
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_USART_GET_FLAG(husart, Flag) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+
+ husart->State= HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_USART_GET_FLAG(husart, Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+
+ husart->State= HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Simplex Send an amount of data in non-blocking mode.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
+ * @note The USART errors are not managed to avoid the overrun error.
+ */
+static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
+{
+ uint16_t* tmp=0;
+
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+ {
+ tmp = (uint16_t*) husart->pTxBuffPtr;
+ WRITE_REG(husart->Instance->DR, (uint16_t)(*tmp & (uint16_t)0x01FF));
+ if(husart->Init.Parity == USART_PARITY_NONE)
+ {
+ husart->pTxBuffPtr += 2;
+ }
+ else
+ {
+ husart->pTxBuffPtr += 1;
+ }
+ }
+ else
+ {
+ WRITE_REG(husart->Instance->DR, (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF));
+ }
+
+ if(--husart->TxXferCount == 0)
+ {
+ /* Disable the USART Transmit data register empty Interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+ }
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Wraps up transmission in non blocking mode.
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
+{
+ /* Disable the USART Transmit Complete Interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+
+ husart->State = HAL_USART_STATE_READY;
+
+ HAL_USART_TxCpltCallback(husart);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Simplex Receive an amount of data in non-blocking mode.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
+{
+ uint16_t* tmp=0;
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+ {
+ tmp = (uint16_t*) husart->pRxBuffPtr;
+ if(husart->Init.Parity == USART_PARITY_NONE)
+ {
+ *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
+ husart->pRxBuffPtr += 2;
+ }
+ else
+ {
+ *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
+ husart->pRxBuffPtr += 1;
+ }
+ if(--husart->RxXferCount != 0x00)
+ {
+ /* Send dummy byte in order to generate the clock for the slave to send the next data */
+ WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x01FF));
+ }
+ }
+ else
+ {
+ if(husart->Init.Parity == USART_PARITY_NONE)
+ {
+ *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
+ }
+ else
+ {
+ *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
+ }
+
+ if(--husart->RxXferCount != 0x00)
+ {
+ /* Send dummy byte in order to generate the clock for the slave to send the next data */
+ WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x00FF));
+ }
+ }
+
+ if(husart->RxXferCount == 0)
+ {
+ /* Disable the USART RXNE Interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
+
+ /* Disable the USART Parity Error Interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+
+ husart->State = HAL_USART_STATE_READY;
+ HAL_USART_RxCpltCallback(husart);
+
+ return HAL_OK;
+ }
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
+{
+ uint16_t* tmp=0;
+
+ if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
+ {
+ if(husart->TxXferCount != 0x00)
+ {
+ if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
+ {
+ if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+ {
+ tmp = (uint16_t*) husart->pTxBuffPtr;
+ WRITE_REG(husart->Instance->DR, (uint16_t)(*tmp & (uint16_t)0x01FF));
+ if(husart->Init.Parity == USART_PARITY_NONE)
+ {
+ husart->pTxBuffPtr += 2;
+ }
+ else
+ {
+ husart->pTxBuffPtr += 1;
+ }
+ }
+ else
+ {
+ WRITE_REG(husart->Instance->DR, (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF));
+ }
+ husart->TxXferCount--;
+
+ /* Check the latest data transmitted */
+ if(husart->TxXferCount == 0)
+ {
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+ }
+ }
+ }
+
+ if(husart->RxXferCount != 0x00)
+ {
+ if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
+ {
+ if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+ {
+ tmp = (uint16_t*) husart->pRxBuffPtr;
+ if(husart->Init.Parity == USART_PARITY_NONE)
+ {
+ *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
+ husart->pRxBuffPtr += 2;
+ }
+ else
+ {
+ *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
+ husart->pRxBuffPtr += 1;
+ }
+ }
+ else
+ {
+ if(husart->Init.Parity == USART_PARITY_NONE)
+ {
+ *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
+ }
+ else
+ {
+ *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
+ }
+ }
+ husart->RxXferCount--;
+ }
+ }
+
+ /* Check the latest data received */
+ if(husart->RxXferCount == 0)
+ {
+ __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
+
+ /* Disable the USART Parity Error Interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+
+ husart->State = HAL_USART_STATE_READY;
+
+ HAL_USART_TxRxCpltCallback(husart);
+
+ return HAL_OK;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Configures the USART peripheral.
+ * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+static void USART_SetConfig(USART_HandleTypeDef *husart)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
+ assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
+ assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
+ assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
+ assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
+ assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
+ assert_param(IS_USART_PARITY(husart->Init.Parity));
+ assert_param(IS_USART_MODE(husart->Init.Mode));
+
+ /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
+ receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */
+ CLEAR_BIT(husart->Instance->CR1, ((uint32_t)(USART_CR1_TE | USART_CR1_RE)));
+
+ /*---------------------------- USART CR2 Configuration ---------------------*/
+ /* Configure the USART Clock, CPOL, CPHA and LastBit -----------------------*/
+ /* Set CPOL bit according to husart->Init.CLKPolarity value */
+ /* Set CPHA bit according to husart->Init.CLKPhase value */
+ /* Set LBCL bit according to husart->Init.CLKLastBit value */
+ /* Set Stop Bits: Set STOP[13:12] bits according to husart->Init.StopBits value */
+ /* Write to USART CR2 */
+ MODIFY_REG(husart->Instance->CR2,
+ (uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP),
+ ((uint32_t)(USART_CLOCK_ENABLE| husart->Init.CLKPolarity | husart->Init.CLKPhase| husart->Init.CLKLastBit | husart->Init.StopBits)));
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Configure the USART Word Length, Parity and mode:
+ Set the M bits according to husart->Init.WordLength value
+ Set PCE and PS bits according to husart->Init.Parity value
+ Set TE and RE bits according to husart->Init.Mode value */
+ MODIFY_REG(husart->Instance->CR1,
+ (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE),
+ (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ /* Clear CTSE and RTSE bits */
+ CLEAR_BIT(husart->Instance->CR3, (uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE));
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ if((husart->Instance == USART1))
+ {
+ husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate);
+ }
+ else
+ {
+ husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_USART_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/stm32f1xx_hal_conf.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/stm32f1xx_hal_conf.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,367 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_conf.h
+ * @author MCD Application Team
+ * @version V1.0.4
+ * @date 29-April-2016
+ * @brief HAL configuration template file.
+ * This file should be copied to the application folder and renamed
+ * to stm32f1xx_hal_conf.h.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_CONF_H
+#define __STM32F1xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+//#define HAL_ADC_MODULE_ENABLED
+//#define HAL_CAN_MODULE_ENABLED
+//#define HAL_CEC_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+//#define HAL_CRC_MODULE_ENABLED
+//#define HAL_DAC_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+//#define HAL_ETH_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+//#define HAL_HCD_MODULE_ENABLED
+//#define HAL_I2C_MODULE_ENABLED
+//#define HAL_I2S_MODULE_ENABLED
+//#define HAL_IRDA_MODULE_ENABLED
+//#define HAL_IWDG_MODULE_ENABLED
+//#define HAL_NAND_MODULE_ENABLED
+//#define HAL_NOR_MODULE_ENABLED
+//#define HAL_PCCARD_MODULE_ENABLED
+//#define HAL_PCD_MODULE_ENABLED
+//#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+//#define HAL_RTC_MODULE_ENABLED
+//#define HAL_SD_MODULE_ENABLED
+//#define HAL_SMARTCARD_MODULE_ENABLED
+//#define HAL_SPI_MODULE_ENABLED
+//#define HAL_SRAM_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+//#define HAL_WWDG_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+#if defined(USE_STM3210C_EVAL)
+ #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#else
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ * This value is used by the UART, RTC HAL module to compute the system frequency
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+ #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((uint32_t)0x000F) /*!< tick interrupt priority */
+#define USE_RTOS 0
+#define PREFETCH_ENABLE 1
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/*#define USE_FULL_ASSERT 1*/
+
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0 2
+#define MAC_ADDR1 0
+#define MAC_ADDR2 0
+#define MAC_ADDR3 0
+#define MAC_ADDR4 0
+#define MAC_ADDR5 0
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
+#define ETH_RXBUFNB ((uint32_t)8) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS 0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
+#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
+
+#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
+#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
+#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
+#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
+#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
+
+#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
+#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
+#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
+
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
+#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
+#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
+#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
+#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
+
+#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
+#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
+
+#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
+#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
+
+
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f1xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f1xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32f1xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+ #include "stm32f1xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f1xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32f1xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f1xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f1xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f1xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f1xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f1xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32f1xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32f1xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f1xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f1xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f1xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f1xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f1xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+ #include "stm32f1xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f1xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32f1xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f1xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f1xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f1xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f1xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f1xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f1xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f1xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f1xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f1xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/armcc/startup_stm32f103xb.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/stm32/stm32f103xb/armcc/startup_stm32f103xb.S Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,324 @@ +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32f103xb.s +;* Author : MCD Application Team +;* Version : V4.1.0 +;* Date : 29-April-2016 +;* Description : STM32F103xB Devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* COPYRIGHT(c) 2016 STMicroelectronics +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT g_board_info +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD DAPLINK_BUILD_KEY ; Build type - BL/IF + DCD DAPLINK_HIC_ID ; Compatibility + DCD DAPLINK_VERSION ; Version + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD g_board_info ; Ptr to Board info, family info other target details + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/cmsis/stm32f103xb.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/cmsis/stm32f103xb.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,10639 @@
+/**
+ ******************************************************************************
+ * @file stm32f103xb.h
+ * @author MCD Application Team
+ * @version V4.1.0
+ * @date 29-April-2016
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32F1xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral.s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f103xb
+ * @{
+ */
+
+#ifndef __STM32F103xB_H
+#define __STM32F103xB_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+ #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
+#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+ /*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** STM32 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< Tamper Interrupt */
+ RTC_IRQn = 3, /*!< RTC global Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+} IRQn_Type;
+
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"
+#include "system_stm32f1xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR;
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SMPR1;
+ __IO uint32_t SMPR2;
+ __IO uint32_t JOFR1;
+ __IO uint32_t JOFR2;
+ __IO uint32_t JOFR3;
+ __IO uint32_t JOFR4;
+ __IO uint32_t HTR;
+ __IO uint32_t LTR;
+ __IO uint32_t SQR1;
+ __IO uint32_t SQR2;
+ __IO uint32_t SQR3;
+ __IO uint32_t JSQR;
+ __IO uint32_t JDR1;
+ __IO uint32_t JDR2;
+ __IO uint32_t JDR3;
+ __IO uint32_t JDR4;
+ __IO uint32_t DR;
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
+ __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
+ uint32_t RESERVED[16];
+ __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Backup Registers
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0;
+ __IO uint32_t DR1;
+ __IO uint32_t DR2;
+ __IO uint32_t DR3;
+ __IO uint32_t DR4;
+ __IO uint32_t DR5;
+ __IO uint32_t DR6;
+ __IO uint32_t DR7;
+ __IO uint32_t DR8;
+ __IO uint32_t DR9;
+ __IO uint32_t DR10;
+ __IO uint32_t RTCCR;
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} BKP_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR;
+ __IO uint32_t TDTR;
+ __IO uint32_t TDLR;
+ __IO uint32_t TDHR;
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR;
+ __IO uint32_t RDTR;
+ __IO uint32_t RDLR;
+ __IO uint32_t RDHR;
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1;
+ __IO uint32_t FR2;
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR;
+ __IO uint32_t MSR;
+ __IO uint32_t TSR;
+ __IO uint32_t RF0R;
+ __IO uint32_t RF1R;
+ __IO uint32_t IER;
+ __IO uint32_t ESR;
+ __IO uint32_t BTR;
+ uint32_t RESERVED0[88];
+ CAN_TxMailBox_TypeDef sTxMailBox[3];
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
+ uint32_t RESERVED1[12];
+ __IO uint32_t FMR;
+ __IO uint32_t FM1R;
+ uint32_t RESERVED2;
+ __IO uint32_t FS1R;
+ uint32_t RESERVED3;
+ __IO uint32_t FFA1R;
+ uint32_t RESERVED4;
+ __IO uint32_t FA1R;
+ uint32_t RESERVED5[8];
+ CAN_FilterRegister_TypeDef sFilterRegister[14];
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE;
+ __IO uint32_t CR;
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR;
+ __IO uint32_t CNDTR;
+ __IO uint32_t CPAR;
+ __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR;
+ __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR;
+ __IO uint32_t EMR;
+ __IO uint32_t RTSR;
+ __IO uint32_t FTSR;
+ __IO uint32_t SWIER;
+ __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR;
+ __IO uint32_t KEYR;
+ __IO uint32_t OPTKEYR;
+ __IO uint32_t SR;
+ __IO uint32_t CR;
+ __IO uint32_t AR;
+ __IO uint32_t RESERVED;
+ __IO uint32_t OBR;
+ __IO uint32_t WRPR;
+} FLASH_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint16_t RDP;
+ __IO uint16_t USER;
+ __IO uint16_t Data0;
+ __IO uint16_t Data1;
+ __IO uint16_t WRP0;
+ __IO uint16_t WRP1;
+ __IO uint16_t WRP2;
+ __IO uint16_t WRP3;
+} OB_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t CRL;
+ __IO uint32_t CRH;
+ __IO uint32_t IDR;
+ __IO uint32_t ODR;
+ __IO uint32_t BSRR;
+ __IO uint32_t BRR;
+ __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t EVCR;
+ __IO uint32_t MAPR;
+ __IO uint32_t EXTICR[4];
+ uint32_t RESERVED0;
+ __IO uint32_t MAPR2;
+} AFIO_TypeDef;
+/**
+ * @brief Inter Integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t OAR1;
+ __IO uint32_t OAR2;
+ __IO uint32_t DR;
+ __IO uint32_t SR1;
+ __IO uint32_t SR2;
+ __IO uint32_t CCR;
+ __IO uint32_t TRISE;
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFGR;
+ __IO uint32_t CIR;
+ __IO uint32_t APB2RSTR;
+ __IO uint32_t APB1RSTR;
+ __IO uint32_t AHBENR;
+ __IO uint32_t APB2ENR;
+ __IO uint32_t APB1ENR;
+ __IO uint32_t BDCR;
+ __IO uint32_t CSR;
+
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t CRH;
+ __IO uint32_t CRL;
+ __IO uint32_t PRLH;
+ __IO uint32_t PRLL;
+ __IO uint32_t DIVH;
+ __IO uint32_t DIVL;
+ __IO uint32_t CNTH;
+ __IO uint32_t CNTL;
+ __IO uint32_t ALRH;
+ __IO uint32_t ALRL;
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER;
+ __IO uint32_t CLKCR;
+ __IO uint32_t ARG;
+ __IO uint32_t CMD;
+ __I uint32_t RESPCMD;
+ __I uint32_t RESP1;
+ __I uint32_t RESP2;
+ __I uint32_t RESP3;
+ __I uint32_t RESP4;
+ __IO uint32_t DTIMER;
+ __IO uint32_t DLEN;
+ __IO uint32_t DCTRL;
+ __I uint32_t DCOUNT;
+ __I uint32_t STA;
+ __IO uint32_t ICR;
+ __IO uint32_t MASK;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SR;
+ __IO uint32_t DR;
+ __IO uint32_t CRCPR;
+ __IO uint32_t RXCRCR;
+ __IO uint32_t TXCRCR;
+ __IO uint32_t I2SCFGR;
+} SPI_TypeDef;
+
+/**
+ * @brief TIM Timers
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+}TIM_TypeDef;
+
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Universal Serial Bus Full Speed Device
+ */
+
+typedef struct
+{
+ __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
+ __IO uint16_t RESERVED0; /*!< Reserved */
+ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
+ __IO uint16_t RESERVED1; /*!< Reserved */
+ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
+ __IO uint16_t RESERVED2; /*!< Reserved */
+ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
+ __IO uint16_t RESERVED3; /*!< Reserved */
+ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
+ __IO uint16_t RESERVED4; /*!< Reserved */
+ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
+ __IO uint16_t RESERVED5; /*!< Reserved */
+ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
+ __IO uint16_t RESERVED6; /*!< Reserved */
+ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
+ __IO uint16_t RESERVED7[17]; /*!< Reserved */
+ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
+ __IO uint16_t RESERVED8; /*!< Reserved */
+ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
+ __IO uint16_t RESERVED9; /*!< Reserved */
+ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
+ __IO uint16_t RESERVEDA; /*!< Reserved */
+ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
+ __IO uint16_t RESERVEDB; /*!< Reserved */
+ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
+ __IO uint16_t RESERVEDC; /*!< Reserved */
+} USB_TypeDef;
+
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+
+#define SDIO_BASE (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
+#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+
+
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+/* USB device FS */
+#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define USB ((USB_TypeDef *) USB_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define BKP ((BKP_TypeDef *) BKP_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
+#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
+#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
+#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
+#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
+#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
+#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
+#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/* */
+/* Backup registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for BKP_DR1 register ********************/
+#define BKP_DR1_D_Pos (0U)
+#define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR2 register ********************/
+#define BKP_DR2_D_Pos (0U)
+#define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR3 register ********************/
+#define BKP_DR3_D_Pos (0U)
+#define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR4 register ********************/
+#define BKP_DR4_D_Pos (0U)
+#define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR5 register ********************/
+#define BKP_DR5_D_Pos (0U)
+#define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR6 register ********************/
+#define BKP_DR6_D_Pos (0U)
+#define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR7 register ********************/
+#define BKP_DR7_D_Pos (0U)
+#define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR8 register ********************/
+#define BKP_DR8_D_Pos (0U)
+#define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR9 register ********************/
+#define BKP_DR9_D_Pos (0U)
+#define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR10 register *******************/
+#define BKP_DR10_D_Pos (0U)
+#define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */
+
+#define RTC_BKP_NUMBER 10
+
+/****************** Bit definition for BKP_RTCCR register *******************/
+#define BKP_RTCCR_CAL_Pos (0U)
+#define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */
+#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */
+#define BKP_RTCCR_CCO_Pos (7U)
+#define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */
+#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */
+#define BKP_RTCCR_ASOE_Pos (8U)
+#define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */
+#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */
+#define BKP_RTCCR_ASOS_Pos (9U)
+#define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */
+#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */
+
+/******************** Bit definition for BKP_CR register ********************/
+#define BKP_CR_TPE_Pos (0U)
+#define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */
+#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */
+#define BKP_CR_TPAL_Pos (1U)
+#define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */
+#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */
+
+/******************* Bit definition for BKP_CSR register ********************/
+#define BKP_CSR_CTE_Pos (0U)
+#define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */
+#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */
+#define BKP_CSR_CTI_Pos (1U)
+#define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */
+#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */
+#define BKP_CSR_TPIE_Pos (2U)
+#define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */
+#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */
+#define BKP_CSR_TEF_Pos (8U)
+#define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */
+#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */
+#define BKP_CSR_TIF_Pos (9U)
+#define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */
+#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE_Pos (14U)
+#define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */
+#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */
+#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE_Pos (17U)
+#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMULL_Pos (18U)
+#define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+
+#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL3_Pos (18U)
+#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMULL4_Pos (19U)
+#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMULL5_Pos (18U)
+#define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */
+#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMULL6_Pos (20U)
+#define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMULL7_Pos (18U)
+#define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */
+#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMULL8_Pos (19U)
+#define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */
+#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMULL9_Pos (18U)
+#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
+#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMULL10_Pos (21U)
+#define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMULL11_Pos (18U)
+#define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */
+#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMULL12_Pos (19U)
+#define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */
+#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMULL13_Pos (18U)
+#define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */
+#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMULL14_Pos (20U)
+#define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */
+#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMULL15_Pos (18U)
+#define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */
+#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMULL16_Pos (19U)
+#define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */
+#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */
+#define RCC_CFGR_USBPRE_Pos (22U)
+#define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO_Pos (24U)
+#define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+ /* Reference defines */
+ #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
+ #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
+ #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
+ #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
+ #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
+ #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
+ #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
+ #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
+ #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
+
+/*!<****************** Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
+
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_AFIORST_Pos (0U)
+#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */
+#define RCC_APB2RSTR_IOPARST_Pos (2U)
+#define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */
+#define RCC_APB2RSTR_IOPBRST_Pos (3U)
+#define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
+#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */
+#define RCC_APB2RSTR_IOPCRST_Pos (4U)
+#define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */
+#define RCC_APB2RSTR_IOPDRST_Pos (5U)
+#define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */
+#define RCC_APB2RSTR_ADC1RST_Pos (9U)
+#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */
+
+#define RCC_APB2RSTR_ADC2RST_Pos (10U)
+#define RCC_APB2RSTR_ADC2RST_Msk (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */
+#define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */
+
+#define RCC_APB2RSTR_TIM1RST_Pos (11U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
+
+
+#define RCC_APB2RSTR_IOPERST_Pos (6U)
+#define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
+#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */
+
+
+
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+
+#define RCC_APB1RSTR_CAN1RST_Pos (25U)
+#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */
+
+#define RCC_APB1RSTR_BKPRST_Pos (27U)
+#define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
+
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */
+#define RCC_APB1RSTR_USART3RST_Pos (18U)
+#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
+
+#define RCC_APB1RSTR_USBRST_Pos (23U)
+#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */
+
+
+
+
+
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN_Pos (0U)
+#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN_Pos (2U)
+#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN_Pos (4U)
+#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
+#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN_Pos (6U)
+#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+
+
+
+
+/****************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_AFIOEN_Pos (0U)
+#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */
+#define RCC_APB2ENR_IOPAEN_Pos (2U)
+#define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */
+#define RCC_APB2ENR_IOPBEN_Pos (3U)
+#define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */
+#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */
+#define RCC_APB2ENR_IOPCEN_Pos (4U)
+#define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */
+#define RCC_APB2ENR_IOPDEN_Pos (5U)
+#define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */
+#define RCC_APB2ENR_ADC1EN_Pos (9U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */
+
+#define RCC_APB2ENR_ADC2EN_Pos (10U)
+#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */
+#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */
+
+#define RCC_APB2ENR_TIM1EN_Pos (11U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
+
+
+#define RCC_APB2ENR_IOPEEN_Pos (6U)
+#define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
+#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */
+
+
+
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
+
+#define RCC_APB1ENR_CAN1EN_Pos (25U)
+#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
+#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */
+
+#define RCC_APB1ENR_BKPEN_Pos (27U)
+#define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
+
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */
+#define RCC_APB1ENR_USART3EN_Pos (18U)
+#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
+
+#define RCC_APB1ENR_USBEN_Pos (23U)
+#define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */
+
+
+
+
+
+
+/******************* Bit definition for RCC_BDCR register *******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+/*!< RTC congiguration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register ********************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_CRL register *******************/
+#define GPIO_CRL_MODE_Pos (0U)
+#define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRL_MODE0_Pos (0U)
+#define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRL_MODE1_Pos (4U)
+#define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */
+#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */
+#define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRL_MODE2_Pos (8U)
+#define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */
+#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */
+#define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRL_MODE3_Pos (12U)
+#define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */
+#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */
+#define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRL_MODE4_Pos (16U)
+#define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */
+#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */
+#define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRL_MODE5_Pos (20U)
+#define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */
+#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */
+#define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRL_MODE6_Pos (24U)
+#define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */
+#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */
+#define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRL_MODE7_Pos (28U)
+#define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */
+#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */
+#define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRL_CNF_Pos (2U)
+#define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRL_CNF0_Pos (2U)
+#define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */
+#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */
+#define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRL_CNF1_Pos (6U)
+#define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */
+#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */
+#define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRL_CNF2_Pos (10U)
+#define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */
+#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */
+#define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRL_CNF3_Pos (14U)
+#define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */
+#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */
+#define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRL_CNF4_Pos (18U)
+#define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */
+#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */
+#define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRL_CNF5_Pos (22U)
+#define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */
+#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */
+#define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRL_CNF6_Pos (26U)
+#define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */
+#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */
+#define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRL_CNF7_Pos (30U)
+#define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */
+#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */
+#define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_CRH register *******************/
+#define GPIO_CRH_MODE_Pos (0U)
+#define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRH_MODE8_Pos (0U)
+#define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */
+#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */
+#define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRH_MODE9_Pos (4U)
+#define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */
+#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */
+#define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRH_MODE10_Pos (8U)
+#define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */
+#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */
+#define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRH_MODE11_Pos (12U)
+#define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */
+#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */
+#define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRH_MODE12_Pos (16U)
+#define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */
+#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */
+#define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRH_MODE13_Pos (20U)
+#define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */
+#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */
+#define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRH_MODE14_Pos (24U)
+#define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */
+#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */
+#define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRH_MODE15_Pos (28U)
+#define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */
+#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */
+#define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRH_CNF_Pos (2U)
+#define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRH_CNF8_Pos (2U)
+#define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */
+#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */
+#define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRH_CNF9_Pos (6U)
+#define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */
+#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */
+#define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRH_CNF10_Pos (10U)
+#define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */
+#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */
+#define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRH_CNF11_Pos (14U)
+#define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */
+#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */
+#define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRH_CNF12_Pos (18U)
+#define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */
+#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */
+#define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRH_CNF13_Pos (22U)
+#define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */
+#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */
+#define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRH_CNF14_Pos (26U)
+#define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */
+#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */
+#define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRH_CNF15_Pos (30U)
+#define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */
+#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */
+#define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */
+
+/*!<****************** Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR0_Pos (0U)
+#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1_Pos (1U)
+#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2_Pos (2U)
+#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3_Pos (3U)
+#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4_Pos (4U)
+#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5_Pos (5U)
+#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6_Pos (6U)
+#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7_Pos (7U)
+#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8_Pos (8U)
+#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9_Pos (9U)
+#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10_Pos (10U)
+#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11_Pos (11U)
+#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12_Pos (12U)
+#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13_Pos (13U)
+#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14_Pos (14U)
+#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15_Pos (15U)
+#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR0_Pos (0U)
+#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1_Pos (1U)
+#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2_Pos (2U)
+#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3_Pos (3U)
+#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4_Pos (4U)
+#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5_Pos (5U)
+#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6_Pos (6U)
+#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7_Pos (7U)
+#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8_Pos (8U)
+#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9_Pos (9U)
+#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10_Pos (10U)
+#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11_Pos (11U)
+#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12_Pos (12U)
+#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13_Pos (13U)
+#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14_Pos (14U)
+#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15_Pos (15U)
+#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_BSRR register *******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_BRR register *******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_LCKR register *******************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for AFIO_EVCR register *******************/
+#define AFIO_EVCR_PIN_Pos (0U)
+#define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
+
+/*!< PIN configuration */
+#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX1_Pos (0U)
+#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
+#define AFIO_EVCR_PIN_PX2_Pos (1U)
+#define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */
+#define AFIO_EVCR_PIN_PX3_Pos (0U)
+#define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */
+#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */
+#define AFIO_EVCR_PIN_PX4_Pos (2U)
+#define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */
+#define AFIO_EVCR_PIN_PX5_Pos (0U)
+#define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */
+#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */
+#define AFIO_EVCR_PIN_PX6_Pos (1U)
+#define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */
+#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */
+#define AFIO_EVCR_PIN_PX7_Pos (0U)
+#define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */
+#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */
+#define AFIO_EVCR_PIN_PX8_Pos (3U)
+#define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */
+#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */
+#define AFIO_EVCR_PIN_PX9_Pos (0U)
+#define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */
+#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */
+#define AFIO_EVCR_PIN_PX10_Pos (1U)
+#define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */
+#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */
+#define AFIO_EVCR_PIN_PX11_Pos (0U)
+#define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */
+#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */
+#define AFIO_EVCR_PIN_PX12_Pos (2U)
+#define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */
+#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */
+#define AFIO_EVCR_PIN_PX13_Pos (0U)
+#define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */
+#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */
+#define AFIO_EVCR_PIN_PX14_Pos (1U)
+#define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */
+#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */
+#define AFIO_EVCR_PIN_PX15_Pos (0U)
+#define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */
+
+#define AFIO_EVCR_PORT_Pos (4U)
+#define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */
+#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
+
+/*!< PORT configuration */
+#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PB_Pos (4U)
+#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
+#define AFIO_EVCR_PORT_PC_Pos (5U)
+#define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */
+#define AFIO_EVCR_PORT_PD_Pos (4U)
+#define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */
+#define AFIO_EVCR_PORT_PE_Pos (6U)
+#define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */
+
+#define AFIO_EVCR_EVOE_Pos (7U)
+#define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */
+#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */
+
+/****************** Bit definition for AFIO_MAPR register *******************/
+#define AFIO_MAPR_SPI1_REMAP_Pos (0U)
+#define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
+#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP_Pos (1U)
+#define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
+#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */
+#define AFIO_MAPR_USART1_REMAP_Pos (2U)
+#define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
+#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */
+#define AFIO_MAPR_USART2_REMAP_Pos (3U)
+#define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
+#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */
+
+#define AFIO_MAPR_USART3_REMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */
+#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
+
+/* USART3_REMAP configuration */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_MAPR_TIM1_REMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAPR_TIM2_REMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAPR_TIM3_REMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
+#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_MAPR_TIM4_REMAP_Pos (12U)
+#define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */
+#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */
+
+#define AFIO_MAPR_CAN_REMAP_Pos (13U)
+#define AFIO_MAPR_CAN_REMAP_Msk (0x3U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */
+#define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
+#define AFIO_MAPR_CAN_REMAP_0 (0x1U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */
+#define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */
+
+/*!< CAN_REMAP configuration */
+#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U)
+#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */
+#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
+#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U)
+#define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3U << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */
+#define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
+
+#define AFIO_MAPR_PD01_REMAP_Pos (15U)
+#define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
+#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */
+#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
+
+#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
+#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+
+/***************** Bit definition for AFIO_EXTICR1 register *****************/
+#define AFIO_EXTICR1_EXTI0_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
+#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
+#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
+#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
+#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */
+
+/***************** Bit definition for AFIO_EXTICR2 register *****************/
+#define AFIO_EXTICR2_EXTI4_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
+#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
+#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
+#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
+#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */
+
+/***************** Bit definition for AFIO_EXTICR3 register *****************/
+#define AFIO_EXTICR3_EXTI8_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
+#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
+#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
+#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
+#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */
+
+/***************** Bit definition for AFIO_EXTICR4 register *****************/
+#define AFIO_EXTICR4_EXTI12_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
+#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
+#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
+#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
+#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */
+
+/****************** Bit definition for AFIO_MAPR2 register ******************/
+
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+
+/* References Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+
+/* References Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
+#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
+#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
+#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
+#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
+#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
+#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
+#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
+#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
+#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
+#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
+#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
+#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
+#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
+#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
+#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
+#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
+#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
+#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
+#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
+#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
+#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
+#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
+#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
+#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
+#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
+#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
+#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
+#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
+#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
+#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
+#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
+#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
+#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
+#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
+#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
+#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
+#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
+#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+
+/* References Defines */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
+#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+
+/* References Defines */
+#define EXTI_PR_PIF0 EXTI_PR_PR0
+#define EXTI_PR_PIF1 EXTI_PR_PR1
+#define EXTI_PR_PIF2 EXTI_PR_PR2
+#define EXTI_PR_PIF3 EXTI_PR_PR3
+#define EXTI_PR_PIF4 EXTI_PR_PR4
+#define EXTI_PR_PIF5 EXTI_PR_PR5
+#define EXTI_PR_PIF6 EXTI_PR_PR6
+#define EXTI_PR_PIF7 EXTI_PR_PR7
+#define EXTI_PR_PIF8 EXTI_PR_PR8
+#define EXTI_PR_PIF9 EXTI_PR_PR9
+#define EXTI_PR_PIF10 EXTI_PR_PR10
+#define EXTI_PR_PIF11 EXTI_PR_PR11
+#define EXTI_PR_PIF12 EXTI_PR_PR12
+#define EXTI_PR_PIF13 EXTI_PR_PR13
+#define EXTI_PR_PIF14 EXTI_PR_PR14
+#define EXTI_PR_PIF15 EXTI_PR_PR15
+#define EXTI_PR_PIF16 EXTI_PR_PR16
+#define EXTI_PR_PIF17 EXTI_PR_PR17
+#define EXTI_PR_PIF18 EXTI_PR_PR18
+#define EXTI_PR_PIF19 EXTI_PR_PR19
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register *******************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register ******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register *******************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register *******************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
+ */
+#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
+#define ADC_SR_EOS_Pos (1U)
+#define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
+#define ADC_SR_JEOS_Pos (2U)
+#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
+
+/* Legacy defines */
+#define ADC_SR_EOC (ADC_SR_EOS)
+#define ADC_SR_JEOC (ADC_SR_JEOS)
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+
+#define ADC_CR1_EOSIE_Pos (5U)
+#define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
+#define ADC_CR1_JEOSIE_Pos (7U)
+#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
+
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+
+#define ADC_CR1_DUALMOD_Pos (16U)
+#define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */
+#define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */
+#define ADC_CR1_DUALMOD_0 (0x1U << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */
+#define ADC_CR1_DUALMOD_1 (0x2U << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */
+#define ADC_CR1_DUALMOD_2 (0x4U << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */
+#define ADC_CR1_DUALMOD_3 (0x8U << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */
+
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+
+/* Legacy defines */
+#define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
+#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
+#define ADC_CR2_CAL_Pos (2U)
+#define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */
+#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */
+#define ADC_CR2_RSTCAL_Pos (3U)
+#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */
+#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+
+#define ADC_CR2_JEXTSEL_Pos (12U)
+#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */
+
+#define ADC_CR2_JEXTTRIG_Pos (15U)
+#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */
+#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */
+
+#define ADC_CR2_EXTSEL_Pos (17U)
+#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */
+
+#define ADC_CR2_EXTTRIG_Pos (20U)
+#define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */
+#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */
+#define ADC_CR2_JSWSTART_Pos (21U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
+#define ADC_CR2_SWSTART_Pos (22U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
+#define ADC_CR2_TSVREFE_Pos (23U)
+#define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
+#define ADC_DR_ADC2DATA_Pos (16U)
+#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */
+
+
+/*****************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for TIM_CR1 register *******************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register *******************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register ******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_OCCS_Pos (3U)
+#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
+#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register ******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register *******************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register *******************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register ******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register ******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register ******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register *******************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register *******************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register *******************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register *******************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register ******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register ******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register ******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register ******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register ******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register *******************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register ******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register ********************/
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for RTC_CRH register ********************/
+#define RTC_CRH_SECIE_Pos (0U)
+#define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */
+#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */
+#define RTC_CRH_ALRIE_Pos (1U)
+#define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */
+#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */
+#define RTC_CRH_OWIE_Pos (2U)
+#define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */
+#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */
+
+/******************* Bit definition for RTC_CRL register ********************/
+#define RTC_CRL_SECF_Pos (0U)
+#define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */
+#define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */
+#define RTC_CRL_ALRF_Pos (1U)
+#define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */
+#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */
+#define RTC_CRL_OWF_Pos (2U)
+#define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */
+#define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */
+#define RTC_CRL_RSF_Pos (3U)
+#define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */
+#define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */
+#define RTC_CRL_CNF_Pos (4U)
+#define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */
+#define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */
+#define RTC_CRL_RTOFF_Pos (5U)
+#define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */
+#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */
+
+/******************* Bit definition for RTC_PRLH register *******************/
+#define RTC_PRLH_PRL_Pos (0U)
+#define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */
+#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */
+
+/******************* Bit definition for RTC_PRLL register *******************/
+#define RTC_PRLL_PRL_Pos (0U)
+#define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */
+#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */
+
+/******************* Bit definition for RTC_DIVH register *******************/
+#define RTC_DIVH_RTC_DIV_Pos (0U)
+#define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */
+#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */
+
+/******************* Bit definition for RTC_DIVL register *******************/
+#define RTC_DIVL_RTC_DIV_Pos (0U)
+#define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */
+#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */
+
+/******************* Bit definition for RTC_CNTH register *******************/
+#define RTC_CNTH_RTC_CNT_Pos (0U)
+#define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */
+
+/******************* Bit definition for RTC_CNTL register *******************/
+#define RTC_CNTL_RTC_CNT_Pos (0U)
+#define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */
+
+/******************* Bit definition for RTC_ALRH register *******************/
+#define RTC_ALRH_RTC_ALR_Pos (0U)
+#define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */
+
+/******************* Bit definition for RTC_ALRL register *******************/
+#define RTC_ALRL_RTC_ALR_Pos (0U)
+#define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* USB Device FS */
+/* */
+/******************************************************************************/
+
+/*!< Endpoint-specific registers */
+#define USB_EP0R USB_BASE /*!< Endpoint 0 register address */
+#define USB_EP1R (USB_BASE + 0x00000004) /*!< Endpoint 1 register address */
+#define USB_EP2R (USB_BASE + 0x00000008) /*!< Endpoint 2 register address */
+#define USB_EP3R (USB_BASE + 0x0000000C) /*!< Endpoint 3 register address */
+#define USB_EP4R (USB_BASE + 0x00000010) /*!< Endpoint 4 register address */
+#define USB_EP5R (USB_BASE + 0x00000014) /*!< Endpoint 5 register address */
+#define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */
+#define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */
+
+/* bit positions */
+#define USB_EP_CTR_RX_Pos (15U)
+#define USB_EP_CTR_RX_Msk (0x1U << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX_Pos (14U)
+#define USB_EP_DTOG_RX_Msk (0x1U << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT_Pos (12U)
+#define USB_EPRX_STAT_Msk (0x3U << USB_EPRX_STAT_Pos) /*!< 0x00003000 */
+#define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */
+#define USB_EP_SETUP_Pos (11U)
+#define USB_EP_SETUP_Msk (0x1U << USB_EP_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */
+#define USB_EP_T_FIELD_Pos (9U)
+#define USB_EP_T_FIELD_Msk (0x3U << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */
+#define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */
+#define USB_EP_KIND_Pos (8U)
+#define USB_EP_KIND_Msk (0x1U << USB_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */
+#define USB_EP_CTR_TX_Pos (7U)
+#define USB_EP_CTR_TX_Msk (0x1U << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX_Pos (6U)
+#define USB_EP_DTOG_TX_Msk (0x1U << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT_Pos (4U)
+#define USB_EPTX_STAT_Msk (0x3U << USB_EPTX_STAT_Pos) /*!< 0x00000030 */
+#define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD_Pos (0U)
+#define USB_EPADDR_FIELD_Msk (0xFU << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */
+#define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+ /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK_Pos (9U)
+#define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
+#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK ((uint32_t)0x00000000) /*!< EndPoint BULK */
+#define USB_EP_CONTROL ((uint32_t)0x00000200) /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT ((uint32_t)0x00000600) /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS ((uint32_t)0x00000000) /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL ((uint32_t)0x00000010) /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK ((uint32_t)0x00000020) /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID ((uint32_t)0x00000030) /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS ((uint32_t)0x00000000) /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL ((uint32_t)0x00001000) /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK ((uint32_t)0x00002000) /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID ((uint32_t)0x00003000) /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
+
+/******************* Bit definition for USB_EP0R register *******************/
+#define USB_EP0R_EA_Pos (0U)
+#define USB_EP0R_EA_Msk (0xFU << USB_EP0R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP0R_EA USB_EP0R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP0R_STAT_TX_Pos (4U)
+#define USB_EP0R_STAT_TX_Msk (0x3U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP0R_STAT_TX_0 (0x1U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP0R_STAT_TX_1 (0x2U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP0R_DTOG_TX_Pos (6U)
+#define USB_EP0R_DTOG_TX_Msk (0x1U << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP0R_CTR_TX_Pos (7U)
+#define USB_EP0R_CTR_TX_Msk (0x1U << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP0R_EP_KIND_Pos (8U)
+#define USB_EP0R_EP_KIND_Msk (0x1U << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP0R_EP_TYPE_Pos (9U)
+#define USB_EP0R_EP_TYPE_Msk (0x3U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP0R_EP_TYPE_0 (0x1U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP0R_EP_TYPE_1 (0x2U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP0R_SETUP_Pos (11U)
+#define USB_EP0R_SETUP_Msk (0x1U << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP0R_STAT_RX_Pos (12U)
+#define USB_EP0R_STAT_RX_Msk (0x3U << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP0R_STAT_RX_0 (0x1U << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP0R_STAT_RX_1 (0x2U << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP0R_DTOG_RX_Pos (14U)
+#define USB_EP0R_DTOG_RX_Msk (0x1U << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP0R_CTR_RX_Pos (15U)
+#define USB_EP0R_CTR_RX_Msk (0x1U << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP1R register *******************/
+#define USB_EP1R_EA_Pos (0U)
+#define USB_EP1R_EA_Msk (0xFU << USB_EP1R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP1R_EA USB_EP1R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP1R_STAT_TX_Pos (4U)
+#define USB_EP1R_STAT_TX_Msk (0x3U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP1R_STAT_TX_0 (0x1U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP1R_STAT_TX_1 (0x2U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP1R_DTOG_TX_Pos (6U)
+#define USB_EP1R_DTOG_TX_Msk (0x1U << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP1R_CTR_TX_Pos (7U)
+#define USB_EP1R_CTR_TX_Msk (0x1U << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP1R_EP_KIND_Pos (8U)
+#define USB_EP1R_EP_KIND_Msk (0x1U << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP1R_EP_TYPE_Pos (9U)
+#define USB_EP1R_EP_TYPE_Msk (0x3U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP1R_EP_TYPE_0 (0x1U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP1R_EP_TYPE_1 (0x2U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP1R_SETUP_Pos (11U)
+#define USB_EP1R_SETUP_Msk (0x1U << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP1R_STAT_RX_Pos (12U)
+#define USB_EP1R_STAT_RX_Msk (0x3U << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP1R_STAT_RX_0 (0x1U << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP1R_STAT_RX_1 (0x2U << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP1R_DTOG_RX_Pos (14U)
+#define USB_EP1R_DTOG_RX_Msk (0x1U << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP1R_CTR_RX_Pos (15U)
+#define USB_EP1R_CTR_RX_Msk (0x1U << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP2R register *******************/
+#define USB_EP2R_EA_Pos (0U)
+#define USB_EP2R_EA_Msk (0xFU << USB_EP2R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP2R_EA USB_EP2R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP2R_STAT_TX_Pos (4U)
+#define USB_EP2R_STAT_TX_Msk (0x3U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP2R_STAT_TX_0 (0x1U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP2R_STAT_TX_1 (0x2U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP2R_DTOG_TX_Pos (6U)
+#define USB_EP2R_DTOG_TX_Msk (0x1U << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP2R_CTR_TX_Pos (7U)
+#define USB_EP2R_CTR_TX_Msk (0x1U << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP2R_EP_KIND_Pos (8U)
+#define USB_EP2R_EP_KIND_Msk (0x1U << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP2R_EP_TYPE_Pos (9U)
+#define USB_EP2R_EP_TYPE_Msk (0x3U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP2R_EP_TYPE_0 (0x1U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP2R_EP_TYPE_1 (0x2U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP2R_SETUP_Pos (11U)
+#define USB_EP2R_SETUP_Msk (0x1U << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP2R_STAT_RX_Pos (12U)
+#define USB_EP2R_STAT_RX_Msk (0x3U << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP2R_STAT_RX_0 (0x1U << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP2R_STAT_RX_1 (0x2U << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP2R_DTOG_RX_Pos (14U)
+#define USB_EP2R_DTOG_RX_Msk (0x1U << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP2R_CTR_RX_Pos (15U)
+#define USB_EP2R_CTR_RX_Msk (0x1U << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP3R register *******************/
+#define USB_EP3R_EA_Pos (0U)
+#define USB_EP3R_EA_Msk (0xFU << USB_EP3R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP3R_EA USB_EP3R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP3R_STAT_TX_Pos (4U)
+#define USB_EP3R_STAT_TX_Msk (0x3U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP3R_STAT_TX_0 (0x1U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP3R_STAT_TX_1 (0x2U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP3R_DTOG_TX_Pos (6U)
+#define USB_EP3R_DTOG_TX_Msk (0x1U << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP3R_CTR_TX_Pos (7U)
+#define USB_EP3R_CTR_TX_Msk (0x1U << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP3R_EP_KIND_Pos (8U)
+#define USB_EP3R_EP_KIND_Msk (0x1U << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP3R_EP_TYPE_Pos (9U)
+#define USB_EP3R_EP_TYPE_Msk (0x3U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP3R_EP_TYPE_0 (0x1U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP3R_EP_TYPE_1 (0x2U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP3R_SETUP_Pos (11U)
+#define USB_EP3R_SETUP_Msk (0x1U << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP3R_STAT_RX_Pos (12U)
+#define USB_EP3R_STAT_RX_Msk (0x3U << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP3R_STAT_RX_0 (0x1U << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP3R_STAT_RX_1 (0x2U << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP3R_DTOG_RX_Pos (14U)
+#define USB_EP3R_DTOG_RX_Msk (0x1U << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP3R_CTR_RX_Pos (15U)
+#define USB_EP3R_CTR_RX_Msk (0x1U << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP4R register *******************/
+#define USB_EP4R_EA_Pos (0U)
+#define USB_EP4R_EA_Msk (0xFU << USB_EP4R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP4R_EA USB_EP4R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP4R_STAT_TX_Pos (4U)
+#define USB_EP4R_STAT_TX_Msk (0x3U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP4R_STAT_TX_0 (0x1U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP4R_STAT_TX_1 (0x2U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP4R_DTOG_TX_Pos (6U)
+#define USB_EP4R_DTOG_TX_Msk (0x1U << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP4R_CTR_TX_Pos (7U)
+#define USB_EP4R_CTR_TX_Msk (0x1U << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP4R_EP_KIND_Pos (8U)
+#define USB_EP4R_EP_KIND_Msk (0x1U << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP4R_EP_TYPE_Pos (9U)
+#define USB_EP4R_EP_TYPE_Msk (0x3U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP4R_EP_TYPE_0 (0x1U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP4R_EP_TYPE_1 (0x2U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP4R_SETUP_Pos (11U)
+#define USB_EP4R_SETUP_Msk (0x1U << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP4R_STAT_RX_Pos (12U)
+#define USB_EP4R_STAT_RX_Msk (0x3U << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP4R_STAT_RX_0 (0x1U << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP4R_STAT_RX_1 (0x2U << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP4R_DTOG_RX_Pos (14U)
+#define USB_EP4R_DTOG_RX_Msk (0x1U << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP4R_CTR_RX_Pos (15U)
+#define USB_EP4R_CTR_RX_Msk (0x1U << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP5R register *******************/
+#define USB_EP5R_EA_Pos (0U)
+#define USB_EP5R_EA_Msk (0xFU << USB_EP5R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP5R_EA USB_EP5R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP5R_STAT_TX_Pos (4U)
+#define USB_EP5R_STAT_TX_Msk (0x3U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP5R_STAT_TX_0 (0x1U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP5R_STAT_TX_1 (0x2U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP5R_DTOG_TX_Pos (6U)
+#define USB_EP5R_DTOG_TX_Msk (0x1U << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP5R_CTR_TX_Pos (7U)
+#define USB_EP5R_CTR_TX_Msk (0x1U << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP5R_EP_KIND_Pos (8U)
+#define USB_EP5R_EP_KIND_Msk (0x1U << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP5R_EP_TYPE_Pos (9U)
+#define USB_EP5R_EP_TYPE_Msk (0x3U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP5R_EP_TYPE_0 (0x1U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP5R_EP_TYPE_1 (0x2U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP5R_SETUP_Pos (11U)
+#define USB_EP5R_SETUP_Msk (0x1U << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP5R_STAT_RX_Pos (12U)
+#define USB_EP5R_STAT_RX_Msk (0x3U << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP5R_STAT_RX_0 (0x1U << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP5R_STAT_RX_1 (0x2U << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP5R_DTOG_RX_Pos (14U)
+#define USB_EP5R_DTOG_RX_Msk (0x1U << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP5R_CTR_RX_Pos (15U)
+#define USB_EP5R_CTR_RX_Msk (0x1U << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP6R register *******************/
+#define USB_EP6R_EA_Pos (0U)
+#define USB_EP6R_EA_Msk (0xFU << USB_EP6R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP6R_EA USB_EP6R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP6R_STAT_TX_Pos (4U)
+#define USB_EP6R_STAT_TX_Msk (0x3U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP6R_STAT_TX_0 (0x1U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP6R_STAT_TX_1 (0x2U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP6R_DTOG_TX_Pos (6U)
+#define USB_EP6R_DTOG_TX_Msk (0x1U << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP6R_CTR_TX_Pos (7U)
+#define USB_EP6R_CTR_TX_Msk (0x1U << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP6R_EP_KIND_Pos (8U)
+#define USB_EP6R_EP_KIND_Msk (0x1U << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP6R_EP_TYPE_Pos (9U)
+#define USB_EP6R_EP_TYPE_Msk (0x3U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP6R_EP_TYPE_0 (0x1U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP6R_EP_TYPE_1 (0x2U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP6R_SETUP_Pos (11U)
+#define USB_EP6R_SETUP_Msk (0x1U << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP6R_STAT_RX_Pos (12U)
+#define USB_EP6R_STAT_RX_Msk (0x3U << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP6R_STAT_RX_0 (0x1U << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP6R_STAT_RX_1 (0x2U << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP6R_DTOG_RX_Pos (14U)
+#define USB_EP6R_DTOG_RX_Msk (0x1U << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP6R_CTR_RX_Pos (15U)
+#define USB_EP6R_CTR_RX_Msk (0x1U << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP7R register *******************/
+#define USB_EP7R_EA_Pos (0U)
+#define USB_EP7R_EA_Msk (0xFU << USB_EP7R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP7R_EA USB_EP7R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP7R_STAT_TX_Pos (4U)
+#define USB_EP7R_STAT_TX_Msk (0x3U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP7R_STAT_TX_0 (0x1U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP7R_STAT_TX_1 (0x2U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP7R_DTOG_TX_Pos (6U)
+#define USB_EP7R_DTOG_TX_Msk (0x1U << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP7R_CTR_TX_Pos (7U)
+#define USB_EP7R_CTR_TX_Msk (0x1U << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP7R_EP_KIND_Pos (8U)
+#define USB_EP7R_EP_KIND_Msk (0x1U << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP7R_EP_TYPE_Pos (9U)
+#define USB_EP7R_EP_TYPE_Msk (0x3U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP7R_EP_TYPE_0 (0x1U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP7R_EP_TYPE_1 (0x2U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP7R_SETUP_Pos (11U)
+#define USB_EP7R_SETUP_Msk (0x1U << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP7R_STAT_RX_Pos (12U)
+#define USB_EP7R_STAT_RX_Msk (0x3U << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP7R_STAT_RX_0 (0x1U << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP7R_STAT_RX_1 (0x2U << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP7R_DTOG_RX_Pos (14U)
+#define USB_EP7R_DTOG_RX_Msk (0x1U << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP7R_CTR_RX_Pos (15U)
+#define USB_EP7R_CTR_RX_Msk (0x1U << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/*!< Common registers */
+/******************* Bit definition for USB_CNTR register *******************/
+#define USB_CNTR_FRES_Pos (0U)
+#define USB_CNTR_FRES_Msk (0x1U << USB_CNTR_FRES_Pos) /*!< 0x00000001 */
+#define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!< Force USB Reset */
+#define USB_CNTR_PDWN_Pos (1U)
+#define USB_CNTR_PDWN_Msk (0x1U << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */
+#define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!< Power down */
+#define USB_CNTR_LP_MODE_Pos (2U)
+#define USB_CNTR_LP_MODE_Msk (0x1U << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */
+#define USB_CNTR_LP_MODE USB_CNTR_LP_MODE_Msk /*!< Low-power mode */
+#define USB_CNTR_FSUSP_Pos (3U)
+#define USB_CNTR_FSUSP_Msk (0x1U << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */
+#define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!< Force suspend */
+#define USB_CNTR_RESUME_Pos (4U)
+#define USB_CNTR_RESUME_Msk (0x1U << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */
+#define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!< Resume request */
+#define USB_CNTR_ESOFM_Pos (8U)
+#define USB_CNTR_ESOFM_Msk (0x1U << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */
+#define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!< Expected Start Of Frame Interrupt Mask */
+#define USB_CNTR_SOFM_Pos (9U)
+#define USB_CNTR_SOFM_Msk (0x1U << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */
+#define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!< Start Of Frame Interrupt Mask */
+#define USB_CNTR_RESETM_Pos (10U)
+#define USB_CNTR_RESETM_Msk (0x1U << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */
+#define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!< RESET Interrupt Mask */
+#define USB_CNTR_SUSPM_Pos (11U)
+#define USB_CNTR_SUSPM_Msk (0x1U << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */
+#define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!< Suspend mode Interrupt Mask */
+#define USB_CNTR_WKUPM_Pos (12U)
+#define USB_CNTR_WKUPM_Msk (0x1U << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */
+#define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!< Wakeup Interrupt Mask */
+#define USB_CNTR_ERRM_Pos (13U)
+#define USB_CNTR_ERRM_Msk (0x1U << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */
+#define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!< Error Interrupt Mask */
+#define USB_CNTR_PMAOVRM_Pos (14U)
+#define USB_CNTR_PMAOVRM_Msk (0x1U << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
+#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!< Packet Memory Area Over / Underrun Interrupt Mask */
+#define USB_CNTR_CTRM_Pos (15U)
+#define USB_CNTR_CTRM_Msk (0x1U << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */
+#define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!< Correct Transfer Interrupt Mask */
+
+/******************* Bit definition for USB_ISTR register *******************/
+#define USB_ISTR_EP_ID_Pos (0U)
+#define USB_ISTR_EP_ID_Msk (0xFU << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */
+#define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!< Endpoint Identifier */
+#define USB_ISTR_DIR_Pos (4U)
+#define USB_ISTR_DIR_Msk (0x1U << USB_ISTR_DIR_Pos) /*!< 0x00000010 */
+#define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!< Direction of transaction */
+#define USB_ISTR_ESOF_Pos (8U)
+#define USB_ISTR_ESOF_Msk (0x1U << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */
+#define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame */
+#define USB_ISTR_SOF_Pos (9U)
+#define USB_ISTR_SOF_Msk (0x1U << USB_ISTR_SOF_Pos) /*!< 0x00000200 */
+#define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame */
+#define USB_ISTR_RESET_Pos (10U)
+#define USB_ISTR_RESET_Msk (0x1U << USB_ISTR_RESET_Pos) /*!< 0x00000400 */
+#define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!< USB RESET request */
+#define USB_ISTR_SUSP_Pos (11U)
+#define USB_ISTR_SUSP_Msk (0x1U << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */
+#define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< Suspend mode request */
+#define USB_ISTR_WKUP_Pos (12U)
+#define USB_ISTR_WKUP_Msk (0x1U << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */
+#define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< Wake up */
+#define USB_ISTR_ERR_Pos (13U)
+#define USB_ISTR_ERR_Msk (0x1U << USB_ISTR_ERR_Pos) /*!< 0x00002000 */
+#define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< Error */
+#define USB_ISTR_PMAOVR_Pos (14U)
+#define USB_ISTR_PMAOVR_Msk (0x1U << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */
+#define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!< Packet Memory Area Over / Underrun */
+#define USB_ISTR_CTR_Pos (15U)
+#define USB_ISTR_CTR_Msk (0x1U << USB_ISTR_CTR_Pos) /*!< 0x00008000 */
+#define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!< Correct Transfer */
+
+/******************* Bit definition for USB_FNR register ********************/
+#define USB_FNR_FN_Pos (0U)
+#define USB_FNR_FN_Msk (0x7FFU << USB_FNR_FN_Pos) /*!< 0x000007FF */
+#define USB_FNR_FN USB_FNR_FN_Msk /*!< Frame Number */
+#define USB_FNR_LSOF_Pos (11U)
+#define USB_FNR_LSOF_Msk (0x3U << USB_FNR_LSOF_Pos) /*!< 0x00001800 */
+#define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!< Lost SOF */
+#define USB_FNR_LCK_Pos (13U)
+#define USB_FNR_LCK_Msk (0x1U << USB_FNR_LCK_Pos) /*!< 0x00002000 */
+#define USB_FNR_LCK USB_FNR_LCK_Msk /*!< Locked */
+#define USB_FNR_RXDM_Pos (14U)
+#define USB_FNR_RXDM_Msk (0x1U << USB_FNR_RXDM_Pos) /*!< 0x00004000 */
+#define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< Receive Data - Line Status */
+#define USB_FNR_RXDP_Pos (15U)
+#define USB_FNR_RXDP_Msk (0x1U << USB_FNR_RXDP_Pos) /*!< 0x00008000 */
+#define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!< Receive Data + Line Status */
+
+/****************** Bit definition for USB_DADDR register *******************/
+#define USB_DADDR_ADD_Pos (0U)
+#define USB_DADDR_ADD_Msk (0x7FU << USB_DADDR_ADD_Pos) /*!< 0x0000007F */
+#define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!< ADD[6:0] bits (Device Address) */
+#define USB_DADDR_ADD0_Pos (0U)
+#define USB_DADDR_ADD0_Msk (0x1U << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */
+#define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!< Bit 0 */
+#define USB_DADDR_ADD1_Pos (1U)
+#define USB_DADDR_ADD1_Msk (0x1U << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */
+#define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!< Bit 1 */
+#define USB_DADDR_ADD2_Pos (2U)
+#define USB_DADDR_ADD2_Msk (0x1U << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */
+#define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!< Bit 2 */
+#define USB_DADDR_ADD3_Pos (3U)
+#define USB_DADDR_ADD3_Msk (0x1U << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */
+#define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!< Bit 3 */
+#define USB_DADDR_ADD4_Pos (4U)
+#define USB_DADDR_ADD4_Msk (0x1U << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */
+#define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!< Bit 4 */
+#define USB_DADDR_ADD5_Pos (5U)
+#define USB_DADDR_ADD5_Msk (0x1U << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */
+#define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!< Bit 5 */
+#define USB_DADDR_ADD6_Pos (6U)
+#define USB_DADDR_ADD6_Msk (0x1U << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */
+#define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!< Bit 6 */
+
+#define USB_DADDR_EF_Pos (7U)
+#define USB_DADDR_EF_Msk (0x1U << USB_DADDR_EF_Pos) /*!< 0x00000080 */
+#define USB_DADDR_EF USB_DADDR_EF_Msk /*!< Enable Function */
+
+/****************** Bit definition for USB_BTABLE register ******************/
+#define USB_BTABLE_BTABLE_Pos (3U)
+#define USB_BTABLE_BTABLE_Msk (0x1FFFU << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
+#define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!< Buffer Table */
+
+/*!< Buffer descriptor table */
+/***************** Bit definition for USB_ADDR0_TX register *****************/
+#define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
+#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_TX register *****************/
+#define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
+#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_TX register *****************/
+#define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
+#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_TX register *****************/
+#define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
+#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_TX register *****************/
+#define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
+#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_TX register *****************/
+#define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
+#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_TX register *****************/
+#define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
+#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_TX register *****************/
+#define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
+#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_TX register ****************/
+#define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
+#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
+
+/***************** Bit definition for USB_COUNT1_TX register ****************/
+#define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
+#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
+
+/***************** Bit definition for USB_COUNT2_TX register ****************/
+#define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
+#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
+
+/***************** Bit definition for USB_COUNT3_TX register ****************/
+#define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
+#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
+
+/***************** Bit definition for USB_COUNT4_TX register ****************/
+#define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
+#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
+
+/***************** Bit definition for USB_COUNT5_TX register ****************/
+#define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
+#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
+
+/***************** Bit definition for USB_COUNT6_TX register ****************/
+#define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
+#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
+
+/***************** Bit definition for USB_COUNT7_TX register ****************/
+#define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
+#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
+#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
+
+/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
+#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
+
+/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
+#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
+
+/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
+#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
+
+/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
+#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
+
+/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
+#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
+
+/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
+#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
+
+/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
+#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
+
+/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
+#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
+
+/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
+#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
+
+/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
+#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
+
+/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
+#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
+
+/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
+#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
+
+/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
+#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
+
+/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
+#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
+
+/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
+#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_ADDR0_RX register *****************/
+#define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
+#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_RX register *****************/
+#define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
+#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_RX register *****************/
+#define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
+#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_RX register *****************/
+#define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
+#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_RX register *****************/
+#define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
+#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_RX register *****************/
+#define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
+#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_RX register *****************/
+#define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
+#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_RX register *****************/
+#define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
+#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_RX register ****************/
+#define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
+#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT0_RX_BLSIZE_Pos (15U)
+#define USB_COUNT0_RX_BLSIZE_Msk (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT1_RX register ****************/
+#define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
+#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT1_RX_BLSIZE_Pos (15U)
+#define USB_COUNT1_RX_BLSIZE_Msk (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT2_RX register ****************/
+#define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
+#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT2_RX_BLSIZE_Pos (15U)
+#define USB_COUNT2_RX_BLSIZE_Msk (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT3_RX register ****************/
+#define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
+#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT3_RX_BLSIZE_Pos (15U)
+#define USB_COUNT3_RX_BLSIZE_Msk (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT4_RX register ****************/
+#define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
+#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT4_RX_BLSIZE_Pos (15U)
+#define USB_COUNT4_RX_BLSIZE_Msk (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT5_RX register ****************/
+#define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
+#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT5_RX_BLSIZE_Pos (15U)
+#define USB_COUNT5_RX_BLSIZE_Msk (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT6_RX register ****************/
+#define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
+#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT6_RX_BLSIZE_Pos (15U)
+#define USB_COUNT6_RX_BLSIZE_Msk (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT7_RX register ****************/
+#define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
+#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT7_RX_BLSIZE_Pos (15U)
+#define USB_COUNT7_RX_BLSIZE_Msk (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
+#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
+#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
+#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
+#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
+#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
+#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
+#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
+#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
+#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
+#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
+#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
+#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
+#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
+#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
+#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
+#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+
+/*!< CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ_Pos (0U)
+#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
+#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!< Initialization Request */
+#define CAN_MCR_SLEEP_Pos (1U)
+#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
+#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!< Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos (2U)
+#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
+#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!< Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos (3U)
+#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
+#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!< Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos (4U)
+#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
+#define CAN_MCR_NART CAN_MCR_NART_Msk /*!< No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos (5U)
+#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
+#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!< Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos (6U)
+#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
+#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!< Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos (7U)
+#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
+#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!< Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos (15U)
+#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
+#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!< CAN software master reset */
+#define CAN_MCR_DBF_Pos (16U)
+#define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
+#define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!< CAN Debug freeze */
+
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK_Pos (0U)
+#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
+#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!< Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos (1U)
+#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
+#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!< Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos (2U)
+#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
+#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!< Error Interrupt */
+#define CAN_MSR_WKUI_Pos (3U)
+#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
+#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!< Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos (4U)
+#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
+#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!< Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos (8U)
+#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
+#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!< Transmit Mode */
+#define CAN_MSR_RXM_Pos (9U)
+#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
+#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!< Receive Mode */
+#define CAN_MSR_SAMP_Pos (10U)
+#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
+#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!< Last Sample Point */
+#define CAN_MSR_RX_Pos (11U)
+#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
+#define CAN_MSR_RX CAN_MSR_RX_Msk /*!< CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0_Pos (0U)
+#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
+#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!< Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos (1U)
+#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
+#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!< Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos (2U)
+#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
+#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!< Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos (3U)
+#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
+#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!< Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos (7U)
+#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!< Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos (8U)
+#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
+#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!< Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos (9U)
+#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
+#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!< Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos (10U)
+#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
+#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!< Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos (11U)
+#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
+#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!< Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos (15U)
+#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!< Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos (16U)
+#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
+#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!< Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos (17U)
+#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
+#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!< Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos (18U)
+#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
+#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!< Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos (19U)
+#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
+#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!< Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos (23U)
+#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!< Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos (24U)
+#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
+#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!< Mailbox Code */
+
+#define CAN_TSR_TME_Pos (26U)
+#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
+#define CAN_TSR_TME CAN_TSR_TME_Msk /*!< TME[2:0] bits */
+#define CAN_TSR_TME0_Pos (26U)
+#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
+#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!< Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos (27U)
+#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
+#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!< Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos (28U)
+#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
+#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!< Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos (29U)
+#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
+#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!< LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos (29U)
+#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
+#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!< Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos (30U)
+#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
+#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!< Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos (31U)
+#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
+#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!< Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0_Pos (0U)
+#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
+#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!< FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos (3U)
+#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
+#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!< FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos (4U)
+#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!< FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos (5U)
+#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!< Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1_Pos (0U)
+#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
+#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!< FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos (3U)
+#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
+#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!< FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos (4U)
+#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!< FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos (5U)
+#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!< Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE_Pos (0U)
+#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
+#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!< Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos (1U)
+#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
+#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!< FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos (2U)
+#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
+#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!< FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos (3U)
+#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
+#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!< FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos (4U)
+#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
+#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!< FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos (5U)
+#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
+#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!< FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos (6U)
+#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
+#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!< FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
+#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!< Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos (9U)
+#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
+#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!< Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos (10U)
+#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
+#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!< Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos (11U)
+#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
+#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!< Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos (15U)
+#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
+#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!< Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos (16U)
+#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
+#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!< Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos (17U)
+#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
+#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!< Sleep Interrupt Enable */
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF_Pos (0U)
+#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
+#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!< Error Warning Flag */
+#define CAN_ESR_EPVF_Pos (1U)
+#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
+#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!< Error Passive Flag */
+#define CAN_ESR_BOFF_Pos (2U)
+#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
+#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!< Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos (4U)
+#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
+#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!< LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
+#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
+#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos (16U)
+#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
+#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!< Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos (24U)
+#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
+#define CAN_ESR_REC CAN_ESR_REC_Msk /*!< Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP_Pos (0U)
+#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
+#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos (16U)
+#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
+#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
+#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
+#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
+#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos (20U)
+#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
+#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
+#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
+#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos (24U)
+#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
+#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
+#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos (30U)
+#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
+#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos (31U)
+#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
+#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
+
+/*!< Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ_Pos (0U)
+#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!< Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos (1U)
+#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos (2U)
+#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!< Identifier Extension */
+#define CAN_TI0R_EXID_Pos (3U)
+#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!< Extended Identifier */
+#define CAN_TI0R_STID_Pos (21U)
+#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC_Pos (0U)
+#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!< Data Length Code */
+#define CAN_TDT0R_TGT_Pos (8U)
+#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!< Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos (16U)
+#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!< Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0_Pos (0U)
+#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos (8U)
+#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos (16U)
+#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos (24U)
+#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!< Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4_Pos (0U)
+#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos (8U)
+#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos (16U)
+#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos (24U)
+#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ_Pos (0U)
+#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!< Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos (1U)
+#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos (2U)
+#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!< Identifier Extension */
+#define CAN_TI1R_EXID_Pos (3U)
+#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!< Extended Identifier */
+#define CAN_TI1R_STID_Pos (21U)
+#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC_Pos (0U)
+#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!< Data Length Code */
+#define CAN_TDT1R_TGT_Pos (8U)
+#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!< Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos (16U)
+#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0_Pos (0U)
+#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos (8U)
+#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos (16U)
+#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos (24U)
+#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4_Pos (0U)
+#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos (8U)
+#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos (16U)
+#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos (24U)
+#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ_Pos (0U)
+#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!< Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos (1U)
+#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos (2U)
+#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!< Identifier Extension */
+#define CAN_TI2R_EXID_Pos (3U)
+#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!< Extended identifier */
+#define CAN_TI2R_STID_Pos (21U)
+#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC_Pos (0U)
+#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!< Data Length Code */
+#define CAN_TDT2R_TGT_Pos (8U)
+#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!< Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos (16U)
+#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0_Pos (0U)
+#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos (8U)
+#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos (16U)
+#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos (24U)
+#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4_Pos (0U)
+#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos (8U)
+#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos (16U)
+#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos (24U)
+#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR_Pos (1U)
+#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos (2U)
+#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!< Identifier Extension */
+#define CAN_RI0R_EXID_Pos (3U)
+#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!< Extended Identifier */
+#define CAN_RI0R_STID_Pos (21U)
+#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC_Pos (0U)
+#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!< Data Length Code */
+#define CAN_RDT0R_FMI_Pos (8U)
+#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!< Filter Match Index */
+#define CAN_RDT0R_TIME_Pos (16U)
+#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0_Pos (0U)
+#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos (8U)
+#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos (16U)
+#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos (24U)
+#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4_Pos (0U)
+#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos (8U)
+#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos (16U)
+#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos (24U)
+#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR_Pos (1U)
+#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos (2U)
+#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!< Identifier Extension */
+#define CAN_RI1R_EXID_Pos (3U)
+#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!< Extended identifier */
+#define CAN_RI1R_STID_Pos (21U)
+#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC_Pos (0U)
+#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!< Data Length Code */
+#define CAN_RDT1R_FMI_Pos (8U)
+#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!< Filter Match Index */
+#define CAN_RDT1R_TIME_Pos (16U)
+#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0_Pos (0U)
+#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos (8U)
+#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos (16U)
+#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos (24U)
+#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4_Pos (0U)
+#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos (8U)
+#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos (16U)
+#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos (24U)
+#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!< Data byte 7 */
+
+/*!< CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT_Pos (0U)
+#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
+#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!< Filter Init Mode */
+#define CAN_FMR_CAN2SB_Pos (8U)
+#define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
+#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!< CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM_Pos (0U)
+#define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
+#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!< Filter Mode */
+#define CAN_FM1R_FBM0_Pos (0U)
+#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
+#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!< Filter Init Mode for filter 0 */
+#define CAN_FM1R_FBM1_Pos (1U)
+#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
+#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!< Filter Init Mode for filter 1 */
+#define CAN_FM1R_FBM2_Pos (2U)
+#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
+#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!< Filter Init Mode for filter 2 */
+#define CAN_FM1R_FBM3_Pos (3U)
+#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
+#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!< Filter Init Mode for filter 3 */
+#define CAN_FM1R_FBM4_Pos (4U)
+#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
+#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!< Filter Init Mode for filter 4 */
+#define CAN_FM1R_FBM5_Pos (5U)
+#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
+#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!< Filter Init Mode for filter 5 */
+#define CAN_FM1R_FBM6_Pos (6U)
+#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
+#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!< Filter Init Mode for filter 6 */
+#define CAN_FM1R_FBM7_Pos (7U)
+#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
+#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!< Filter Init Mode for filter 7 */
+#define CAN_FM1R_FBM8_Pos (8U)
+#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
+#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!< Filter Init Mode for filter 8 */
+#define CAN_FM1R_FBM9_Pos (9U)
+#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
+#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!< Filter Init Mode for filter 9 */
+#define CAN_FM1R_FBM10_Pos (10U)
+#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
+#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!< Filter Init Mode for filter 10 */
+#define CAN_FM1R_FBM11_Pos (11U)
+#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
+#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!< Filter Init Mode for filter 11 */
+#define CAN_FM1R_FBM12_Pos (12U)
+#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
+#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!< Filter Init Mode for filter 12 */
+#define CAN_FM1R_FBM13_Pos (13U)
+#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
+#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!< Filter Init Mode for filter 13 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC_Pos (0U)
+#define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
+#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!< Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos (0U)
+#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
+#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!< Filter Scale Configuration for filter 0 */
+#define CAN_FS1R_FSC1_Pos (1U)
+#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
+#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!< Filter Scale Configuration for filter 1 */
+#define CAN_FS1R_FSC2_Pos (2U)
+#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
+#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!< Filter Scale Configuration for filter 2 */
+#define CAN_FS1R_FSC3_Pos (3U)
+#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
+#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!< Filter Scale Configuration for filter 3 */
+#define CAN_FS1R_FSC4_Pos (4U)
+#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
+#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!< Filter Scale Configuration for filter 4 */
+#define CAN_FS1R_FSC5_Pos (5U)
+#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
+#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!< Filter Scale Configuration for filter 5 */
+#define CAN_FS1R_FSC6_Pos (6U)
+#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
+#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!< Filter Scale Configuration for filter 6 */
+#define CAN_FS1R_FSC7_Pos (7U)
+#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
+#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!< Filter Scale Configuration for filter 7 */
+#define CAN_FS1R_FSC8_Pos (8U)
+#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
+#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!< Filter Scale Configuration for filter 8 */
+#define CAN_FS1R_FSC9_Pos (9U)
+#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
+#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!< Filter Scale Configuration for filter 9 */
+#define CAN_FS1R_FSC10_Pos (10U)
+#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
+#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!< Filter Scale Configuration for filter 10 */
+#define CAN_FS1R_FSC11_Pos (11U)
+#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
+#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!< Filter Scale Configuration for filter 11 */
+#define CAN_FS1R_FSC12_Pos (12U)
+#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
+#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!< Filter Scale Configuration for filter 12 */
+#define CAN_FS1R_FSC13_Pos (13U)
+#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
+#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!< Filter Scale Configuration for filter 13 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA_Pos (0U)
+#define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
+#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!< Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos (0U)
+#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!< Filter FIFO Assignment for filter 0 */
+#define CAN_FFA1R_FFA1_Pos (1U)
+#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!< Filter FIFO Assignment for filter 1 */
+#define CAN_FFA1R_FFA2_Pos (2U)
+#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!< Filter FIFO Assignment for filter 2 */
+#define CAN_FFA1R_FFA3_Pos (3U)
+#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!< Filter FIFO Assignment for filter 3 */
+#define CAN_FFA1R_FFA4_Pos (4U)
+#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!< Filter FIFO Assignment for filter 4 */
+#define CAN_FFA1R_FFA5_Pos (5U)
+#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!< Filter FIFO Assignment for filter 5 */
+#define CAN_FFA1R_FFA6_Pos (6U)
+#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!< Filter FIFO Assignment for filter 6 */
+#define CAN_FFA1R_FFA7_Pos (7U)
+#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!< Filter FIFO Assignment for filter 7 */
+#define CAN_FFA1R_FFA8_Pos (8U)
+#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!< Filter FIFO Assignment for filter 8 */
+#define CAN_FFA1R_FFA9_Pos (9U)
+#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!< Filter FIFO Assignment for filter 9 */
+#define CAN_FFA1R_FFA10_Pos (10U)
+#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!< Filter FIFO Assignment for filter 10 */
+#define CAN_FFA1R_FFA11_Pos (11U)
+#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!< Filter FIFO Assignment for filter 11 */
+#define CAN_FFA1R_FFA12_Pos (12U)
+#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!< Filter FIFO Assignment for filter 12 */
+#define CAN_FFA1R_FFA13_Pos (13U)
+#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!< Filter FIFO Assignment for filter 13 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT_Pos (0U)
+#define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
+#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!< Filter Active */
+#define CAN_FA1R_FACT0_Pos (0U)
+#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
+#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!< Filter 0 Active */
+#define CAN_FA1R_FACT1_Pos (1U)
+#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
+#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!< Filter 1 Active */
+#define CAN_FA1R_FACT2_Pos (2U)
+#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
+#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!< Filter 2 Active */
+#define CAN_FA1R_FACT3_Pos (3U)
+#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
+#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!< Filter 3 Active */
+#define CAN_FA1R_FACT4_Pos (4U)
+#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
+#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!< Filter 4 Active */
+#define CAN_FA1R_FACT5_Pos (5U)
+#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
+#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!< Filter 5 Active */
+#define CAN_FA1R_FACT6_Pos (6U)
+#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
+#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!< Filter 6 Active */
+#define CAN_FA1R_FACT7_Pos (7U)
+#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
+#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!< Filter 7 Active */
+#define CAN_FA1R_FACT8_Pos (8U)
+#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
+#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!< Filter 8 Active */
+#define CAN_FA1R_FACT9_Pos (9U)
+#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
+#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!< Filter 9 Active */
+#define CAN_FA1R_FACT10_Pos (10U)
+#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
+#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!< Filter 10 Active */
+#define CAN_FA1R_FACT11_Pos (11U)
+#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
+#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!< Filter 11 Active */
+#define CAN_FA1R_FACT12_Pos (12U)
+#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
+#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!< Filter 12 Active */
+#define CAN_FA1R_FACT13_Pos (13U)
+#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
+#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!< Filter 13 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0_Pos (0U)
+#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F0R1_FB1_Pos (1U)
+#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F0R1_FB2_Pos (2U)
+#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F0R1_FB3_Pos (3U)
+#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F0R1_FB4_Pos (4U)
+#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F0R1_FB5_Pos (5U)
+#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F0R1_FB6_Pos (6U)
+#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F0R1_FB7_Pos (7U)
+#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F0R1_FB8_Pos (8U)
+#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F0R1_FB9_Pos (9U)
+#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F0R1_FB10_Pos (10U)
+#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F0R1_FB11_Pos (11U)
+#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F0R1_FB12_Pos (12U)
+#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F0R1_FB13_Pos (13U)
+#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F0R1_FB14_Pos (14U)
+#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F0R1_FB15_Pos (15U)
+#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F0R1_FB16_Pos (16U)
+#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F0R1_FB17_Pos (17U)
+#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F0R1_FB18_Pos (18U)
+#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F0R1_FB19_Pos (19U)
+#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F0R1_FB20_Pos (20U)
+#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F0R1_FB21_Pos (21U)
+#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F0R1_FB22_Pos (22U)
+#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F0R1_FB23_Pos (23U)
+#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F0R1_FB24_Pos (24U)
+#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F0R1_FB25_Pos (25U)
+#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F0R1_FB26_Pos (26U)
+#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F0R1_FB27_Pos (27U)
+#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F0R1_FB28_Pos (28U)
+#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F0R1_FB29_Pos (29U)
+#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F0R1_FB30_Pos (30U)
+#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F0R1_FB31_Pos (31U)
+#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0_Pos (0U)
+#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F1R1_FB1_Pos (1U)
+#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F1R1_FB2_Pos (2U)
+#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F1R1_FB3_Pos (3U)
+#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F1R1_FB4_Pos (4U)
+#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F1R1_FB5_Pos (5U)
+#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F1R1_FB6_Pos (6U)
+#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F1R1_FB7_Pos (7U)
+#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F1R1_FB8_Pos (8U)
+#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F1R1_FB9_Pos (9U)
+#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F1R1_FB10_Pos (10U)
+#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F1R1_FB11_Pos (11U)
+#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F1R1_FB12_Pos (12U)
+#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F1R1_FB13_Pos (13U)
+#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F1R1_FB14_Pos (14U)
+#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F1R1_FB15_Pos (15U)
+#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F1R1_FB16_Pos (16U)
+#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F1R1_FB17_Pos (17U)
+#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F1R1_FB18_Pos (18U)
+#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F1R1_FB19_Pos (19U)
+#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F1R1_FB20_Pos (20U)
+#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F1R1_FB21_Pos (21U)
+#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F1R1_FB22_Pos (22U)
+#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F1R1_FB23_Pos (23U)
+#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F1R1_FB24_Pos (24U)
+#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F1R1_FB25_Pos (25U)
+#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F1R1_FB26_Pos (26U)
+#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F1R1_FB27_Pos (27U)
+#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F1R1_FB28_Pos (28U)
+#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F1R1_FB29_Pos (29U)
+#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F1R1_FB30_Pos (30U)
+#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F1R1_FB31_Pos (31U)
+#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0_Pos (0U)
+#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F2R1_FB1_Pos (1U)
+#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F2R1_FB2_Pos (2U)
+#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F2R1_FB3_Pos (3U)
+#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F2R1_FB4_Pos (4U)
+#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F2R1_FB5_Pos (5U)
+#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F2R1_FB6_Pos (6U)
+#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F2R1_FB7_Pos (7U)
+#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F2R1_FB8_Pos (8U)
+#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F2R1_FB9_Pos (9U)
+#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F2R1_FB10_Pos (10U)
+#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F2R1_FB11_Pos (11U)
+#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F2R1_FB12_Pos (12U)
+#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F2R1_FB13_Pos (13U)
+#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F2R1_FB14_Pos (14U)
+#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F2R1_FB15_Pos (15U)
+#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F2R1_FB16_Pos (16U)
+#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F2R1_FB17_Pos (17U)
+#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F2R1_FB18_Pos (18U)
+#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F2R1_FB19_Pos (19U)
+#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F2R1_FB20_Pos (20U)
+#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F2R1_FB21_Pos (21U)
+#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F2R1_FB22_Pos (22U)
+#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F2R1_FB23_Pos (23U)
+#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F2R1_FB24_Pos (24U)
+#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F2R1_FB25_Pos (25U)
+#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F2R1_FB26_Pos (26U)
+#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F2R1_FB27_Pos (27U)
+#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F2R1_FB28_Pos (28U)
+#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F2R1_FB29_Pos (29U)
+#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F2R1_FB30_Pos (30U)
+#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F2R1_FB31_Pos (31U)
+#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0_Pos (0U)
+#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F3R1_FB1_Pos (1U)
+#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F3R1_FB2_Pos (2U)
+#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F3R1_FB3_Pos (3U)
+#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F3R1_FB4_Pos (4U)
+#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F3R1_FB5_Pos (5U)
+#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F3R1_FB6_Pos (6U)
+#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F3R1_FB7_Pos (7U)
+#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F3R1_FB8_Pos (8U)
+#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F3R1_FB9_Pos (9U)
+#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F3R1_FB10_Pos (10U)
+#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F3R1_FB11_Pos (11U)
+#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F3R1_FB12_Pos (12U)
+#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F3R1_FB13_Pos (13U)
+#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F3R1_FB14_Pos (14U)
+#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F3R1_FB15_Pos (15U)
+#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F3R1_FB16_Pos (16U)
+#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F3R1_FB17_Pos (17U)
+#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F3R1_FB18_Pos (18U)
+#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F3R1_FB19_Pos (19U)
+#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F3R1_FB20_Pos (20U)
+#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F3R1_FB21_Pos (21U)
+#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F3R1_FB22_Pos (22U)
+#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F3R1_FB23_Pos (23U)
+#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F3R1_FB24_Pos (24U)
+#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F3R1_FB25_Pos (25U)
+#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F3R1_FB26_Pos (26U)
+#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F3R1_FB27_Pos (27U)
+#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F3R1_FB28_Pos (28U)
+#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F3R1_FB29_Pos (29U)
+#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F3R1_FB30_Pos (30U)
+#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F3R1_FB31_Pos (31U)
+#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0_Pos (0U)
+#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F4R1_FB1_Pos (1U)
+#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F4R1_FB2_Pos (2U)
+#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F4R1_FB3_Pos (3U)
+#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F4R1_FB4_Pos (4U)
+#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F4R1_FB5_Pos (5U)
+#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F4R1_FB6_Pos (6U)
+#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F4R1_FB7_Pos (7U)
+#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F4R1_FB8_Pos (8U)
+#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F4R1_FB9_Pos (9U)
+#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F4R1_FB10_Pos (10U)
+#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F4R1_FB11_Pos (11U)
+#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F4R1_FB12_Pos (12U)
+#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F4R1_FB13_Pos (13U)
+#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F4R1_FB14_Pos (14U)
+#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F4R1_FB15_Pos (15U)
+#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F4R1_FB16_Pos (16U)
+#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F4R1_FB17_Pos (17U)
+#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F4R1_FB18_Pos (18U)
+#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F4R1_FB19_Pos (19U)
+#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F4R1_FB20_Pos (20U)
+#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F4R1_FB21_Pos (21U)
+#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F4R1_FB22_Pos (22U)
+#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F4R1_FB23_Pos (23U)
+#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F4R1_FB24_Pos (24U)
+#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F4R1_FB25_Pos (25U)
+#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F4R1_FB26_Pos (26U)
+#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F4R1_FB27_Pos (27U)
+#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F4R1_FB28_Pos (28U)
+#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F4R1_FB29_Pos (29U)
+#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F4R1_FB30_Pos (30U)
+#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F4R1_FB31_Pos (31U)
+#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0_Pos (0U)
+#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F5R1_FB1_Pos (1U)
+#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F5R1_FB2_Pos (2U)
+#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F5R1_FB3_Pos (3U)
+#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F5R1_FB4_Pos (4U)
+#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F5R1_FB5_Pos (5U)
+#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F5R1_FB6_Pos (6U)
+#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F5R1_FB7_Pos (7U)
+#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F5R1_FB8_Pos (8U)
+#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F5R1_FB9_Pos (9U)
+#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F5R1_FB10_Pos (10U)
+#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F5R1_FB11_Pos (11U)
+#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F5R1_FB12_Pos (12U)
+#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F5R1_FB13_Pos (13U)
+#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F5R1_FB14_Pos (14U)
+#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F5R1_FB15_Pos (15U)
+#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F5R1_FB16_Pos (16U)
+#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F5R1_FB17_Pos (17U)
+#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F5R1_FB18_Pos (18U)
+#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F5R1_FB19_Pos (19U)
+#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F5R1_FB20_Pos (20U)
+#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F5R1_FB21_Pos (21U)
+#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F5R1_FB22_Pos (22U)
+#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F5R1_FB23_Pos (23U)
+#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F5R1_FB24_Pos (24U)
+#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F5R1_FB25_Pos (25U)
+#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F5R1_FB26_Pos (26U)
+#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F5R1_FB27_Pos (27U)
+#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F5R1_FB28_Pos (28U)
+#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F5R1_FB29_Pos (29U)
+#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F5R1_FB30_Pos (30U)
+#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F5R1_FB31_Pos (31U)
+#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0_Pos (0U)
+#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F6R1_FB1_Pos (1U)
+#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F6R1_FB2_Pos (2U)
+#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F6R1_FB3_Pos (3U)
+#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F6R1_FB4_Pos (4U)
+#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F6R1_FB5_Pos (5U)
+#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F6R1_FB6_Pos (6U)
+#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F6R1_FB7_Pos (7U)
+#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F6R1_FB8_Pos (8U)
+#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F6R1_FB9_Pos (9U)
+#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F6R1_FB10_Pos (10U)
+#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F6R1_FB11_Pos (11U)
+#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F6R1_FB12_Pos (12U)
+#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F6R1_FB13_Pos (13U)
+#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F6R1_FB14_Pos (14U)
+#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F6R1_FB15_Pos (15U)
+#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F6R1_FB16_Pos (16U)
+#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F6R1_FB17_Pos (17U)
+#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F6R1_FB18_Pos (18U)
+#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F6R1_FB19_Pos (19U)
+#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F6R1_FB20_Pos (20U)
+#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F6R1_FB21_Pos (21U)
+#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F6R1_FB22_Pos (22U)
+#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F6R1_FB23_Pos (23U)
+#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F6R1_FB24_Pos (24U)
+#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F6R1_FB25_Pos (25U)
+#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F6R1_FB26_Pos (26U)
+#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F6R1_FB27_Pos (27U)
+#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F6R1_FB28_Pos (28U)
+#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F6R1_FB29_Pos (29U)
+#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F6R1_FB30_Pos (30U)
+#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F6R1_FB31_Pos (31U)
+#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0_Pos (0U)
+#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F7R1_FB1_Pos (1U)
+#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F7R1_FB2_Pos (2U)
+#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F7R1_FB3_Pos (3U)
+#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F7R1_FB4_Pos (4U)
+#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F7R1_FB5_Pos (5U)
+#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F7R1_FB6_Pos (6U)
+#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F7R1_FB7_Pos (7U)
+#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F7R1_FB8_Pos (8U)
+#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F7R1_FB9_Pos (9U)
+#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F7R1_FB10_Pos (10U)
+#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F7R1_FB11_Pos (11U)
+#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F7R1_FB12_Pos (12U)
+#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F7R1_FB13_Pos (13U)
+#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F7R1_FB14_Pos (14U)
+#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F7R1_FB15_Pos (15U)
+#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F7R1_FB16_Pos (16U)
+#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F7R1_FB17_Pos (17U)
+#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F7R1_FB18_Pos (18U)
+#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F7R1_FB19_Pos (19U)
+#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F7R1_FB20_Pos (20U)
+#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F7R1_FB21_Pos (21U)
+#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F7R1_FB22_Pos (22U)
+#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F7R1_FB23_Pos (23U)
+#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F7R1_FB24_Pos (24U)
+#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F7R1_FB25_Pos (25U)
+#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F7R1_FB26_Pos (26U)
+#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F7R1_FB27_Pos (27U)
+#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F7R1_FB28_Pos (28U)
+#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F7R1_FB29_Pos (29U)
+#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F7R1_FB30_Pos (30U)
+#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F7R1_FB31_Pos (31U)
+#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0_Pos (0U)
+#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F8R1_FB1_Pos (1U)
+#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F8R1_FB2_Pos (2U)
+#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F8R1_FB3_Pos (3U)
+#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F8R1_FB4_Pos (4U)
+#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F8R1_FB5_Pos (5U)
+#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F8R1_FB6_Pos (6U)
+#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F8R1_FB7_Pos (7U)
+#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F8R1_FB8_Pos (8U)
+#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F8R1_FB9_Pos (9U)
+#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F8R1_FB10_Pos (10U)
+#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F8R1_FB11_Pos (11U)
+#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F8R1_FB12_Pos (12U)
+#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F8R1_FB13_Pos (13U)
+#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F8R1_FB14_Pos (14U)
+#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F8R1_FB15_Pos (15U)
+#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F8R1_FB16_Pos (16U)
+#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F8R1_FB17_Pos (17U)
+#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F8R1_FB18_Pos (18U)
+#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F8R1_FB19_Pos (19U)
+#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F8R1_FB20_Pos (20U)
+#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F8R1_FB21_Pos (21U)
+#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F8R1_FB22_Pos (22U)
+#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F8R1_FB23_Pos (23U)
+#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F8R1_FB24_Pos (24U)
+#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F8R1_FB25_Pos (25U)
+#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F8R1_FB26_Pos (26U)
+#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F8R1_FB27_Pos (27U)
+#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F8R1_FB28_Pos (28U)
+#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F8R1_FB29_Pos (29U)
+#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F8R1_FB30_Pos (30U)
+#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F8R1_FB31_Pos (31U)
+#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0_Pos (0U)
+#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F9R1_FB1_Pos (1U)
+#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F9R1_FB2_Pos (2U)
+#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F9R1_FB3_Pos (3U)
+#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F9R1_FB4_Pos (4U)
+#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F9R1_FB5_Pos (5U)
+#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F9R1_FB6_Pos (6U)
+#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F9R1_FB7_Pos (7U)
+#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F9R1_FB8_Pos (8U)
+#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F9R1_FB9_Pos (9U)
+#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F9R1_FB10_Pos (10U)
+#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F9R1_FB11_Pos (11U)
+#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F9R1_FB12_Pos (12U)
+#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F9R1_FB13_Pos (13U)
+#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F9R1_FB14_Pos (14U)
+#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F9R1_FB15_Pos (15U)
+#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F9R1_FB16_Pos (16U)
+#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F9R1_FB17_Pos (17U)
+#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F9R1_FB18_Pos (18U)
+#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F9R1_FB19_Pos (19U)
+#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F9R1_FB20_Pos (20U)
+#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F9R1_FB21_Pos (21U)
+#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F9R1_FB22_Pos (22U)
+#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F9R1_FB23_Pos (23U)
+#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F9R1_FB24_Pos (24U)
+#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F9R1_FB25_Pos (25U)
+#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F9R1_FB26_Pos (26U)
+#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F9R1_FB27_Pos (27U)
+#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F9R1_FB28_Pos (28U)
+#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F9R1_FB29_Pos (29U)
+#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F9R1_FB30_Pos (30U)
+#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F9R1_FB31_Pos (31U)
+#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0_Pos (0U)
+#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F10R1_FB1_Pos (1U)
+#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F10R1_FB2_Pos (2U)
+#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F10R1_FB3_Pos (3U)
+#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F10R1_FB4_Pos (4U)
+#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F10R1_FB5_Pos (5U)
+#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F10R1_FB6_Pos (6U)
+#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F10R1_FB7_Pos (7U)
+#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F10R1_FB8_Pos (8U)
+#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F10R1_FB9_Pos (9U)
+#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F10R1_FB10_Pos (10U)
+#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F10R1_FB11_Pos (11U)
+#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F10R1_FB12_Pos (12U)
+#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F10R1_FB13_Pos (13U)
+#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F10R1_FB14_Pos (14U)
+#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F10R1_FB15_Pos (15U)
+#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F10R1_FB16_Pos (16U)
+#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F10R1_FB17_Pos (17U)
+#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F10R1_FB18_Pos (18U)
+#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F10R1_FB19_Pos (19U)
+#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F10R1_FB20_Pos (20U)
+#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F10R1_FB21_Pos (21U)
+#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F10R1_FB22_Pos (22U)
+#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F10R1_FB23_Pos (23U)
+#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F10R1_FB24_Pos (24U)
+#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F10R1_FB25_Pos (25U)
+#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F10R1_FB26_Pos (26U)
+#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F10R1_FB27_Pos (27U)
+#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F10R1_FB28_Pos (28U)
+#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F10R1_FB29_Pos (29U)
+#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F10R1_FB30_Pos (30U)
+#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F10R1_FB31_Pos (31U)
+#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0_Pos (0U)
+#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F11R1_FB1_Pos (1U)
+#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F11R1_FB2_Pos (2U)
+#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F11R1_FB3_Pos (3U)
+#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F11R1_FB4_Pos (4U)
+#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F11R1_FB5_Pos (5U)
+#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F11R1_FB6_Pos (6U)
+#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F11R1_FB7_Pos (7U)
+#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F11R1_FB8_Pos (8U)
+#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F11R1_FB9_Pos (9U)
+#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F11R1_FB10_Pos (10U)
+#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F11R1_FB11_Pos (11U)
+#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F11R1_FB12_Pos (12U)
+#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F11R1_FB13_Pos (13U)
+#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F11R1_FB14_Pos (14U)
+#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F11R1_FB15_Pos (15U)
+#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F11R1_FB16_Pos (16U)
+#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F11R1_FB17_Pos (17U)
+#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F11R1_FB18_Pos (18U)
+#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F11R1_FB19_Pos (19U)
+#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F11R1_FB20_Pos (20U)
+#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F11R1_FB21_Pos (21U)
+#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F11R1_FB22_Pos (22U)
+#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F11R1_FB23_Pos (23U)
+#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F11R1_FB24_Pos (24U)
+#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F11R1_FB25_Pos (25U)
+#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F11R1_FB26_Pos (26U)
+#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F11R1_FB27_Pos (27U)
+#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F11R1_FB28_Pos (28U)
+#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F11R1_FB29_Pos (29U)
+#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F11R1_FB30_Pos (30U)
+#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F11R1_FB31_Pos (31U)
+#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0_Pos (0U)
+#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F12R1_FB1_Pos (1U)
+#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F12R1_FB2_Pos (2U)
+#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F12R1_FB3_Pos (3U)
+#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F12R1_FB4_Pos (4U)
+#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F12R1_FB5_Pos (5U)
+#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F12R1_FB6_Pos (6U)
+#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F12R1_FB7_Pos (7U)
+#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F12R1_FB8_Pos (8U)
+#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F12R1_FB9_Pos (9U)
+#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F12R1_FB10_Pos (10U)
+#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F12R1_FB11_Pos (11U)
+#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F12R1_FB12_Pos (12U)
+#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F12R1_FB13_Pos (13U)
+#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F12R1_FB14_Pos (14U)
+#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F12R1_FB15_Pos (15U)
+#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F12R1_FB16_Pos (16U)
+#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F12R1_FB17_Pos (17U)
+#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F12R1_FB18_Pos (18U)
+#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F12R1_FB19_Pos (19U)
+#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F12R1_FB20_Pos (20U)
+#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F12R1_FB21_Pos (21U)
+#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F12R1_FB22_Pos (22U)
+#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F12R1_FB23_Pos (23U)
+#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F12R1_FB24_Pos (24U)
+#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F12R1_FB25_Pos (25U)
+#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F12R1_FB26_Pos (26U)
+#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F12R1_FB27_Pos (27U)
+#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F12R1_FB28_Pos (28U)
+#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F12R1_FB29_Pos (29U)
+#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F12R1_FB30_Pos (30U)
+#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F12R1_FB31_Pos (31U)
+#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0_Pos (0U)
+#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F13R1_FB1_Pos (1U)
+#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F13R1_FB2_Pos (2U)
+#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F13R1_FB3_Pos (3U)
+#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F13R1_FB4_Pos (4U)
+#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F13R1_FB5_Pos (5U)
+#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F13R1_FB6_Pos (6U)
+#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F13R1_FB7_Pos (7U)
+#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F13R1_FB8_Pos (8U)
+#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F13R1_FB9_Pos (9U)
+#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F13R1_FB10_Pos (10U)
+#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F13R1_FB11_Pos (11U)
+#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F13R1_FB12_Pos (12U)
+#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F13R1_FB13_Pos (13U)
+#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F13R1_FB14_Pos (14U)
+#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F13R1_FB15_Pos (15U)
+#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F13R1_FB16_Pos (16U)
+#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F13R1_FB17_Pos (17U)
+#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F13R1_FB18_Pos (18U)
+#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F13R1_FB19_Pos (19U)
+#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F13R1_FB20_Pos (20U)
+#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F13R1_FB21_Pos (21U)
+#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F13R1_FB22_Pos (22U)
+#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F13R1_FB23_Pos (23U)
+#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F13R1_FB24_Pos (24U)
+#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F13R1_FB25_Pos (25U)
+#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F13R1_FB26_Pos (26U)
+#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F13R1_FB27_Pos (27U)
+#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F13R1_FB28_Pos (28U)
+#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F13R1_FB29_Pos (29U)
+#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F13R1_FB30_Pos (30U)
+#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F13R1_FB31_Pos (31U)
+#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0_Pos (0U)
+#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F0R2_FB1_Pos (1U)
+#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F0R2_FB2_Pos (2U)
+#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F0R2_FB3_Pos (3U)
+#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F0R2_FB4_Pos (4U)
+#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F0R2_FB5_Pos (5U)
+#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F0R2_FB6_Pos (6U)
+#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F0R2_FB7_Pos (7U)
+#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F0R2_FB8_Pos (8U)
+#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F0R2_FB9_Pos (9U)
+#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F0R2_FB10_Pos (10U)
+#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F0R2_FB11_Pos (11U)
+#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F0R2_FB12_Pos (12U)
+#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F0R2_FB13_Pos (13U)
+#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F0R2_FB14_Pos (14U)
+#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F0R2_FB15_Pos (15U)
+#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F0R2_FB16_Pos (16U)
+#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F0R2_FB17_Pos (17U)
+#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F0R2_FB18_Pos (18U)
+#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F0R2_FB19_Pos (19U)
+#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F0R2_FB20_Pos (20U)
+#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F0R2_FB21_Pos (21U)
+#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F0R2_FB22_Pos (22U)
+#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F0R2_FB23_Pos (23U)
+#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F0R2_FB24_Pos (24U)
+#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F0R2_FB25_Pos (25U)
+#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F0R2_FB26_Pos (26U)
+#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F0R2_FB27_Pos (27U)
+#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F0R2_FB28_Pos (28U)
+#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F0R2_FB29_Pos (29U)
+#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F0R2_FB30_Pos (30U)
+#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F0R2_FB31_Pos (31U)
+#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0_Pos (0U)
+#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F1R2_FB1_Pos (1U)
+#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F1R2_FB2_Pos (2U)
+#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F1R2_FB3_Pos (3U)
+#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F1R2_FB4_Pos (4U)
+#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F1R2_FB5_Pos (5U)
+#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F1R2_FB6_Pos (6U)
+#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F1R2_FB7_Pos (7U)
+#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F1R2_FB8_Pos (8U)
+#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F1R2_FB9_Pos (9U)
+#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F1R2_FB10_Pos (10U)
+#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F1R2_FB11_Pos (11U)
+#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F1R2_FB12_Pos (12U)
+#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F1R2_FB13_Pos (13U)
+#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F1R2_FB14_Pos (14U)
+#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F1R2_FB15_Pos (15U)
+#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F1R2_FB16_Pos (16U)
+#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F1R2_FB17_Pos (17U)
+#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F1R2_FB18_Pos (18U)
+#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F1R2_FB19_Pos (19U)
+#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F1R2_FB20_Pos (20U)
+#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F1R2_FB21_Pos (21U)
+#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F1R2_FB22_Pos (22U)
+#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F1R2_FB23_Pos (23U)
+#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F1R2_FB24_Pos (24U)
+#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F1R2_FB25_Pos (25U)
+#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F1R2_FB26_Pos (26U)
+#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F1R2_FB27_Pos (27U)
+#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F1R2_FB28_Pos (28U)
+#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F1R2_FB29_Pos (29U)
+#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F1R2_FB30_Pos (30U)
+#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F1R2_FB31_Pos (31U)
+#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0_Pos (0U)
+#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F2R2_FB1_Pos (1U)
+#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F2R2_FB2_Pos (2U)
+#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F2R2_FB3_Pos (3U)
+#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F2R2_FB4_Pos (4U)
+#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F2R2_FB5_Pos (5U)
+#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F2R2_FB6_Pos (6U)
+#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F2R2_FB7_Pos (7U)
+#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F2R2_FB8_Pos (8U)
+#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F2R2_FB9_Pos (9U)
+#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F2R2_FB10_Pos (10U)
+#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F2R2_FB11_Pos (11U)
+#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F2R2_FB12_Pos (12U)
+#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F2R2_FB13_Pos (13U)
+#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F2R2_FB14_Pos (14U)
+#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F2R2_FB15_Pos (15U)
+#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F2R2_FB16_Pos (16U)
+#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F2R2_FB17_Pos (17U)
+#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F2R2_FB18_Pos (18U)
+#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F2R2_FB19_Pos (19U)
+#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F2R2_FB20_Pos (20U)
+#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F2R2_FB21_Pos (21U)
+#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F2R2_FB22_Pos (22U)
+#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F2R2_FB23_Pos (23U)
+#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F2R2_FB24_Pos (24U)
+#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F2R2_FB25_Pos (25U)
+#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F2R2_FB26_Pos (26U)
+#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F2R2_FB27_Pos (27U)
+#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F2R2_FB28_Pos (28U)
+#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F2R2_FB29_Pos (29U)
+#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F2R2_FB30_Pos (30U)
+#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F2R2_FB31_Pos (31U)
+#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0_Pos (0U)
+#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F3R2_FB1_Pos (1U)
+#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F3R2_FB2_Pos (2U)
+#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F3R2_FB3_Pos (3U)
+#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F3R2_FB4_Pos (4U)
+#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F3R2_FB5_Pos (5U)
+#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F3R2_FB6_Pos (6U)
+#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F3R2_FB7_Pos (7U)
+#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F3R2_FB8_Pos (8U)
+#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F3R2_FB9_Pos (9U)
+#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F3R2_FB10_Pos (10U)
+#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F3R2_FB11_Pos (11U)
+#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F3R2_FB12_Pos (12U)
+#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F3R2_FB13_Pos (13U)
+#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F3R2_FB14_Pos (14U)
+#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F3R2_FB15_Pos (15U)
+#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F3R2_FB16_Pos (16U)
+#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F3R2_FB17_Pos (17U)
+#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F3R2_FB18_Pos (18U)
+#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F3R2_FB19_Pos (19U)
+#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F3R2_FB20_Pos (20U)
+#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F3R2_FB21_Pos (21U)
+#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F3R2_FB22_Pos (22U)
+#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F3R2_FB23_Pos (23U)
+#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F3R2_FB24_Pos (24U)
+#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F3R2_FB25_Pos (25U)
+#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F3R2_FB26_Pos (26U)
+#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F3R2_FB27_Pos (27U)
+#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F3R2_FB28_Pos (28U)
+#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F3R2_FB29_Pos (29U)
+#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F3R2_FB30_Pos (30U)
+#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F3R2_FB31_Pos (31U)
+#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0_Pos (0U)
+#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F4R2_FB1_Pos (1U)
+#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F4R2_FB2_Pos (2U)
+#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F4R2_FB3_Pos (3U)
+#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F4R2_FB4_Pos (4U)
+#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F4R2_FB5_Pos (5U)
+#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F4R2_FB6_Pos (6U)
+#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F4R2_FB7_Pos (7U)
+#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F4R2_FB8_Pos (8U)
+#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F4R2_FB9_Pos (9U)
+#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F4R2_FB10_Pos (10U)
+#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F4R2_FB11_Pos (11U)
+#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F4R2_FB12_Pos (12U)
+#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F4R2_FB13_Pos (13U)
+#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F4R2_FB14_Pos (14U)
+#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F4R2_FB15_Pos (15U)
+#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F4R2_FB16_Pos (16U)
+#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F4R2_FB17_Pos (17U)
+#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F4R2_FB18_Pos (18U)
+#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F4R2_FB19_Pos (19U)
+#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F4R2_FB20_Pos (20U)
+#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F4R2_FB21_Pos (21U)
+#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F4R2_FB22_Pos (22U)
+#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F4R2_FB23_Pos (23U)
+#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F4R2_FB24_Pos (24U)
+#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F4R2_FB25_Pos (25U)
+#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F4R2_FB26_Pos (26U)
+#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F4R2_FB27_Pos (27U)
+#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F4R2_FB28_Pos (28U)
+#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F4R2_FB29_Pos (29U)
+#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F4R2_FB30_Pos (30U)
+#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F4R2_FB31_Pos (31U)
+#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0_Pos (0U)
+#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F5R2_FB1_Pos (1U)
+#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F5R2_FB2_Pos (2U)
+#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F5R2_FB3_Pos (3U)
+#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F5R2_FB4_Pos (4U)
+#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F5R2_FB5_Pos (5U)
+#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F5R2_FB6_Pos (6U)
+#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F5R2_FB7_Pos (7U)
+#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F5R2_FB8_Pos (8U)
+#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F5R2_FB9_Pos (9U)
+#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F5R2_FB10_Pos (10U)
+#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F5R2_FB11_Pos (11U)
+#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F5R2_FB12_Pos (12U)
+#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F5R2_FB13_Pos (13U)
+#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F5R2_FB14_Pos (14U)
+#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F5R2_FB15_Pos (15U)
+#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F5R2_FB16_Pos (16U)
+#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F5R2_FB17_Pos (17U)
+#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F5R2_FB18_Pos (18U)
+#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F5R2_FB19_Pos (19U)
+#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F5R2_FB20_Pos (20U)
+#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F5R2_FB21_Pos (21U)
+#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F5R2_FB22_Pos (22U)
+#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F5R2_FB23_Pos (23U)
+#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F5R2_FB24_Pos (24U)
+#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F5R2_FB25_Pos (25U)
+#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F5R2_FB26_Pos (26U)
+#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F5R2_FB27_Pos (27U)
+#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F5R2_FB28_Pos (28U)
+#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F5R2_FB29_Pos (29U)
+#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F5R2_FB30_Pos (30U)
+#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F5R2_FB31_Pos (31U)
+#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0_Pos (0U)
+#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F6R2_FB1_Pos (1U)
+#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F6R2_FB2_Pos (2U)
+#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F6R2_FB3_Pos (3U)
+#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F6R2_FB4_Pos (4U)
+#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F6R2_FB5_Pos (5U)
+#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F6R2_FB6_Pos (6U)
+#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F6R2_FB7_Pos (7U)
+#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F6R2_FB8_Pos (8U)
+#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F6R2_FB9_Pos (9U)
+#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F6R2_FB10_Pos (10U)
+#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F6R2_FB11_Pos (11U)
+#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F6R2_FB12_Pos (12U)
+#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F6R2_FB13_Pos (13U)
+#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F6R2_FB14_Pos (14U)
+#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F6R2_FB15_Pos (15U)
+#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F6R2_FB16_Pos (16U)
+#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F6R2_FB17_Pos (17U)
+#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F6R2_FB18_Pos (18U)
+#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F6R2_FB19_Pos (19U)
+#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F6R2_FB20_Pos (20U)
+#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F6R2_FB21_Pos (21U)
+#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F6R2_FB22_Pos (22U)
+#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F6R2_FB23_Pos (23U)
+#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F6R2_FB24_Pos (24U)
+#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F6R2_FB25_Pos (25U)
+#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F6R2_FB26_Pos (26U)
+#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F6R2_FB27_Pos (27U)
+#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F6R2_FB28_Pos (28U)
+#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F6R2_FB29_Pos (29U)
+#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F6R2_FB30_Pos (30U)
+#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F6R2_FB31_Pos (31U)
+#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0_Pos (0U)
+#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F7R2_FB1_Pos (1U)
+#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F7R2_FB2_Pos (2U)
+#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F7R2_FB3_Pos (3U)
+#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F7R2_FB4_Pos (4U)
+#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F7R2_FB5_Pos (5U)
+#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F7R2_FB6_Pos (6U)
+#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F7R2_FB7_Pos (7U)
+#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F7R2_FB8_Pos (8U)
+#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F7R2_FB9_Pos (9U)
+#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F7R2_FB10_Pos (10U)
+#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F7R2_FB11_Pos (11U)
+#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F7R2_FB12_Pos (12U)
+#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F7R2_FB13_Pos (13U)
+#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F7R2_FB14_Pos (14U)
+#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F7R2_FB15_Pos (15U)
+#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F7R2_FB16_Pos (16U)
+#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F7R2_FB17_Pos (17U)
+#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F7R2_FB18_Pos (18U)
+#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F7R2_FB19_Pos (19U)
+#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F7R2_FB20_Pos (20U)
+#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F7R2_FB21_Pos (21U)
+#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F7R2_FB22_Pos (22U)
+#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F7R2_FB23_Pos (23U)
+#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F7R2_FB24_Pos (24U)
+#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F7R2_FB25_Pos (25U)
+#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F7R2_FB26_Pos (26U)
+#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F7R2_FB27_Pos (27U)
+#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F7R2_FB28_Pos (28U)
+#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F7R2_FB29_Pos (29U)
+#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F7R2_FB30_Pos (30U)
+#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F7R2_FB31_Pos (31U)
+#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0_Pos (0U)
+#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F8R2_FB1_Pos (1U)
+#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F8R2_FB2_Pos (2U)
+#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F8R2_FB3_Pos (3U)
+#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F8R2_FB4_Pos (4U)
+#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F8R2_FB5_Pos (5U)
+#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F8R2_FB6_Pos (6U)
+#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F8R2_FB7_Pos (7U)
+#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F8R2_FB8_Pos (8U)
+#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F8R2_FB9_Pos (9U)
+#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F8R2_FB10_Pos (10U)
+#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F8R2_FB11_Pos (11U)
+#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F8R2_FB12_Pos (12U)
+#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F8R2_FB13_Pos (13U)
+#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F8R2_FB14_Pos (14U)
+#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F8R2_FB15_Pos (15U)
+#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F8R2_FB16_Pos (16U)
+#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F8R2_FB17_Pos (17U)
+#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F8R2_FB18_Pos (18U)
+#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F8R2_FB19_Pos (19U)
+#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F8R2_FB20_Pos (20U)
+#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F8R2_FB21_Pos (21U)
+#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F8R2_FB22_Pos (22U)
+#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F8R2_FB23_Pos (23U)
+#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F8R2_FB24_Pos (24U)
+#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F8R2_FB25_Pos (25U)
+#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F8R2_FB26_Pos (26U)
+#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F8R2_FB27_Pos (27U)
+#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F8R2_FB28_Pos (28U)
+#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F8R2_FB29_Pos (29U)
+#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F8R2_FB30_Pos (30U)
+#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F8R2_FB31_Pos (31U)
+#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0_Pos (0U)
+#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F9R2_FB1_Pos (1U)
+#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F9R2_FB2_Pos (2U)
+#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F9R2_FB3_Pos (3U)
+#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F9R2_FB4_Pos (4U)
+#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F9R2_FB5_Pos (5U)
+#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F9R2_FB6_Pos (6U)
+#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F9R2_FB7_Pos (7U)
+#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F9R2_FB8_Pos (8U)
+#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F9R2_FB9_Pos (9U)
+#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F9R2_FB10_Pos (10U)
+#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F9R2_FB11_Pos (11U)
+#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F9R2_FB12_Pos (12U)
+#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F9R2_FB13_Pos (13U)
+#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F9R2_FB14_Pos (14U)
+#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F9R2_FB15_Pos (15U)
+#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F9R2_FB16_Pos (16U)
+#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F9R2_FB17_Pos (17U)
+#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F9R2_FB18_Pos (18U)
+#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F9R2_FB19_Pos (19U)
+#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F9R2_FB20_Pos (20U)
+#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F9R2_FB21_Pos (21U)
+#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F9R2_FB22_Pos (22U)
+#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F9R2_FB23_Pos (23U)
+#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F9R2_FB24_Pos (24U)
+#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F9R2_FB25_Pos (25U)
+#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F9R2_FB26_Pos (26U)
+#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F9R2_FB27_Pos (27U)
+#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F9R2_FB28_Pos (28U)
+#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F9R2_FB29_Pos (29U)
+#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F9R2_FB30_Pos (30U)
+#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F9R2_FB31_Pos (31U)
+#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0_Pos (0U)
+#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F10R2_FB1_Pos (1U)
+#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F10R2_FB2_Pos (2U)
+#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F10R2_FB3_Pos (3U)
+#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F10R2_FB4_Pos (4U)
+#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F10R2_FB5_Pos (5U)
+#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F10R2_FB6_Pos (6U)
+#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F10R2_FB7_Pos (7U)
+#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F10R2_FB8_Pos (8U)
+#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F10R2_FB9_Pos (9U)
+#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F10R2_FB10_Pos (10U)
+#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F10R2_FB11_Pos (11U)
+#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F10R2_FB12_Pos (12U)
+#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F10R2_FB13_Pos (13U)
+#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F10R2_FB14_Pos (14U)
+#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F10R2_FB15_Pos (15U)
+#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F10R2_FB16_Pos (16U)
+#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F10R2_FB17_Pos (17U)
+#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F10R2_FB18_Pos (18U)
+#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F10R2_FB19_Pos (19U)
+#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F10R2_FB20_Pos (20U)
+#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F10R2_FB21_Pos (21U)
+#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F10R2_FB22_Pos (22U)
+#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F10R2_FB23_Pos (23U)
+#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F10R2_FB24_Pos (24U)
+#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F10R2_FB25_Pos (25U)
+#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F10R2_FB26_Pos (26U)
+#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F10R2_FB27_Pos (27U)
+#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F10R2_FB28_Pos (28U)
+#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F10R2_FB29_Pos (29U)
+#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F10R2_FB30_Pos (30U)
+#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F10R2_FB31_Pos (31U)
+#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0_Pos (0U)
+#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F11R2_FB1_Pos (1U)
+#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F11R2_FB2_Pos (2U)
+#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F11R2_FB3_Pos (3U)
+#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F11R2_FB4_Pos (4U)
+#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F11R2_FB5_Pos (5U)
+#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F11R2_FB6_Pos (6U)
+#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F11R2_FB7_Pos (7U)
+#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F11R2_FB8_Pos (8U)
+#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F11R2_FB9_Pos (9U)
+#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F11R2_FB10_Pos (10U)
+#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F11R2_FB11_Pos (11U)
+#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F11R2_FB12_Pos (12U)
+#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F11R2_FB13_Pos (13U)
+#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F11R2_FB14_Pos (14U)
+#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F11R2_FB15_Pos (15U)
+#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F11R2_FB16_Pos (16U)
+#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F11R2_FB17_Pos (17U)
+#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F11R2_FB18_Pos (18U)
+#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F11R2_FB19_Pos (19U)
+#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F11R2_FB20_Pos (20U)
+#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F11R2_FB21_Pos (21U)
+#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F11R2_FB22_Pos (22U)
+#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F11R2_FB23_Pos (23U)
+#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F11R2_FB24_Pos (24U)
+#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F11R2_FB25_Pos (25U)
+#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F11R2_FB26_Pos (26U)
+#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F11R2_FB27_Pos (27U)
+#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F11R2_FB28_Pos (28U)
+#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F11R2_FB29_Pos (29U)
+#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F11R2_FB30_Pos (30U)
+#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F11R2_FB31_Pos (31U)
+#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0_Pos (0U)
+#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F12R2_FB1_Pos (1U)
+#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F12R2_FB2_Pos (2U)
+#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F12R2_FB3_Pos (3U)
+#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F12R2_FB4_Pos (4U)
+#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F12R2_FB5_Pos (5U)
+#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F12R2_FB6_Pos (6U)
+#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F12R2_FB7_Pos (7U)
+#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F12R2_FB8_Pos (8U)
+#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F12R2_FB9_Pos (9U)
+#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F12R2_FB10_Pos (10U)
+#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F12R2_FB11_Pos (11U)
+#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F12R2_FB12_Pos (12U)
+#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F12R2_FB13_Pos (13U)
+#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F12R2_FB14_Pos (14U)
+#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F12R2_FB15_Pos (15U)
+#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F12R2_FB16_Pos (16U)
+#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F12R2_FB17_Pos (17U)
+#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F12R2_FB18_Pos (18U)
+#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F12R2_FB19_Pos (19U)
+#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F12R2_FB20_Pos (20U)
+#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F12R2_FB21_Pos (21U)
+#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F12R2_FB22_Pos (22U)
+#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F12R2_FB23_Pos (23U)
+#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F12R2_FB24_Pos (24U)
+#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F12R2_FB25_Pos (25U)
+#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F12R2_FB26_Pos (26U)
+#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F12R2_FB27_Pos (27U)
+#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F12R2_FB28_Pos (28U)
+#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F12R2_FB29_Pos (29U)
+#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F12R2_FB30_Pos (30U)
+#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F12R2_FB31_Pos (31U)
+#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0_Pos (0U)
+#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F13R2_FB1_Pos (1U)
+#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F13R2_FB2_Pos (2U)
+#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F13R2_FB3_Pos (3U)
+#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F13R2_FB4_Pos (4U)
+#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F13R2_FB5_Pos (5U)
+#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F13R2_FB6_Pos (6U)
+#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F13R2_FB7_Pos (7U)
+#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F13R2_FB8_Pos (8U)
+#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F13R2_FB9_Pos (9U)
+#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F13R2_FB10_Pos (10U)
+#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F13R2_FB11_Pos (11U)
+#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F13R2_FB12_Pos (12U)
+#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F13R2_FB13_Pos (13U)
+#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F13R2_FB14_Pos (14U)
+#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F13R2_FB15_Pos (15U)
+#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F13R2_FB16_Pos (16U)
+#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F13R2_FB17_Pos (17U)
+#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F13R2_FB18_Pos (18U)
+#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F13R2_FB19_Pos (19U)
+#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F13R2_FB20_Pos (20U)
+#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F13R2_FB21_Pos (21U)
+#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F13R2_FB22_Pos (22U)
+#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F13R2_FB23_Pos (23U)
+#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F13R2_FB24_Pos (24U)
+#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F13R2_FB25_Pos (25U)
+#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F13R2_FB26_Pos (26U)
+#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F13R2_FB27_Pos (27U)
+#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F13R2_FB28_Pos (28U)
+#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F13R2_FB29_Pos (29U)
+#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F13R2_FB30_Pos (30U)
+#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F13R2_FB31_Pos (31U)
+#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
+#define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
+#define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
+#define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)
+#define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
+#define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
+#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
+#define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */
+#define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U)
+#define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */
+#define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk /*!< Debug CAN1 stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
+
+#define FLASH_ACR_HLFCYA_Pos (3U)
+#define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
+#define FLASH_ACR_PRFTBE_Pos (4U)
+#define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS_Pos (5U)
+#define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR_Pos (0U)
+#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
+
+#define RDP_KEY_Pos (0U)
+#define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */
+#define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
+#define FLASH_KEY1_Pos (0U)
+#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
+#define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
+#define FLASH_KEY2_Pos (0U)
+#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
+#define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
+
+#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
+#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
+
+/****************** Bit definition for FLASH_SR register ********************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_PGERR_Pos (2U)
+#define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
+#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
+#define FLASH_SR_WRPRTERR_Pos (4U)
+#define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
+#define FLASH_SR_EOP_Pos (5U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
+#define FLASH_CR_PER_Pos (1U)
+#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
+#define FLASH_CR_OPTPG_Pos (4U)
+#define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
+#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
+#define FLASH_CR_OPTER_Pos (5U)
+#define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
+#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
+#define FLASH_CR_STRT_Pos (6U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
+#define FLASH_CR_LOCK_Pos (7U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
+#define FLASH_CR_OPTWRE_Pos (9U)
+#define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE_Pos (10U)
+#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
+#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE_Pos (12U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR_Pos (0U)
+#define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR_Pos (0U)
+#define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
+#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT_Pos (1U)
+#define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
+#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
+
+#define FLASH_OBR_IWDG_SW_Pos (2U)
+#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */
+#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP_Pos (3U)
+#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */
+#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY_Pos (4U)
+#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
+#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OBR_USER_Pos (2U)
+#define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x0000001C */
+#define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OBR_DATA0_Pos (10U)
+#define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */
+#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
+#define FLASH_OBR_DATA1_Pos (18U)
+#define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */
+#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for FLASH_RDP register *******************/
+#define FLASH_RDP_RDP_Pos (0U)
+#define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */
+#define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */
+#define FLASH_RDP_nRDP_Pos (8U)
+#define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */
+
+/****************** Bit definition for FLASH_USER register ******************/
+#define FLASH_USER_USER_Pos (16U)
+#define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */
+#define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */
+#define FLASH_USER_nUSER_Pos (24U)
+#define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */
+#define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */
+
+/****************** Bit definition for FLASH_Data0 register *****************/
+#define FLASH_DATA0_DATA0_Pos (0U)
+#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */
+#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */
+#define FLASH_DATA0_nDATA0_Pos (8U)
+#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */
+#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_Data1 register *****************/
+#define FLASH_DATA1_DATA1_Pos (16U)
+#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */
+#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */
+#define FLASH_DATA1_nDATA1_Pos (24U)
+#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */
+#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define FLASH_WRP0_WRP0_Pos (0U)
+#define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */
+#define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP0_nWRP0_Pos (8U)
+#define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP1 register ******************/
+#define FLASH_WRP1_WRP1_Pos (16U)
+#define FLASH_WRP1_WRP1_Msk (0xFFU << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP1_nWRP1_Pos (24U)
+#define FLASH_WRP1_nWRP1_Msk (0xFFU << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
+#define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP2 register ******************/
+#define FLASH_WRP2_WRP2_Pos (0U)
+#define FLASH_WRP2_WRP2_Msk (0xFFU << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP2_nWRP2_Pos (8U)
+#define FLASH_WRP2_nWRP2_Msk (0xFFU << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP3 register ******************/
+#define FLASH_WRP3_WRP3_Pos (16U)
+#define FLASH_WRP3_WRP3_Msk (0xFFU << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP3_nWRP3_Pos (24U)
+#define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
+#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
+
+
+
+/**
+ * @}
+*/
+
+/**
+ * @}
+*/
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2))
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/****************************** CAN Instances *********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/****************************** DAC Instances *********************************/
+
+/****************************** DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE))
+
+/**************************** GPIO Alternate Function Instances ***************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************************** START TIM Instances ***************************/
+/****************************** TIM Instances *********************************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))))
+
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ (((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3)))
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
+/****************************** END TIM Instances *****************************/
+
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/***************** UART Instances : Multi-Processor mode **********************/
+#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/***************** UART Instances : DMA mode available **********************/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/**************************** WWDG Instances *****************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+
+
+
+/**
+ * @}
+*/
+/******************************************************************************/
+/* For a painless codes migration between the STM32F1xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F1 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_IRQn ADC1_2_IRQn
+#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
+#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
+#define TIM9_IRQn TIM1_BRK_IRQn
+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
+#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
+#define TIM11_IRQn TIM1_TRG_COM_IRQn
+#define TIM10_IRQn TIM1_UP_IRQn
+#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
+#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
+#define CEC_IRQn USBWakeUp_IRQn
+#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
+#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
+#define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
+#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
+#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
+
+
+/* Aliases for __IRQHandler */
+#define ADC1_IRQHandler ADC1_2_IRQHandler
+#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
+#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
+#define TIM9_IRQHandler TIM1_BRK_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM10_IRQHandler TIM1_UP_IRQHandler
+#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
+#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
+#define CEC_IRQHandler USBWakeUp_IRQHandler
+#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
+#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
+#define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
+#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
+#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+ }
+#endif /* __cplusplus */
+
+#endif /* __STM32F103xB_H */
+
+
+
+ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/cmsis/stm32f1xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/cmsis/stm32f1xx.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,238 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx.h
+ * @author MCD Application Team
+ * @version V4.1.0
+ * @date 29-April-2016
+ * @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F1xx device used in the target application
+ * - To use or not the peripherals drivers in application code(i.e.
+ * code will be based on direct access to peripherals registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f1xx
+ * @{
+ */
+
+#ifndef __STM32F1XX_H
+#define __STM32F1XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F1)
+#define STM32F1
+#endif /* STM32F1 */
+
+/* Uncomment the line below according to the target STM32L device used in your
+ application
+ */
+
+#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \
+ !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \
+ !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)
+ /* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
+ /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
+ /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
+ /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
+ /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */
+ /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
+ /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
+ /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
+ /* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
+ /* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
+ /* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
+ /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
+ /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
+ /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number
+ */
+#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
+#define __STM32F1_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
+#define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
+ |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
+ |(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
+ |(__STM32F1_CMSIS_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F100xB)
+ #include "stm32f100xb.h"
+#elif defined(STM32F100xE)
+ #include "stm32f100xe.h"
+#elif defined(STM32F101x6)
+ #include "stm32f101x6.h"
+#elif defined(STM32F101xB)
+ #include "stm32f101xb.h"
+#elif defined(STM32F101xE)
+ #include "stm32f101xe.h"
+#elif defined(STM32F101xG)
+ #include "stm32f101xg.h"
+#elif defined(STM32F102x6)
+ #include "stm32f102x6.h"
+#elif defined(STM32F102xB)
+ #include "stm32f102xb.h"
+#elif defined(STM32F103x6)
+ #include "stm32f103x6.h"
+#elif defined(STM32F103xB)
+ #include "stm32f103xb.h"
+#elif defined(STM32F103xE)
+ #include "stm32f103xe.h"
+#elif defined(STM32F103xG)
+ #include "stm32f103xg.h"
+#elif defined(STM32F105xC)
+ #include "stm32f105xc.h"
+#elif defined(STM32F107xC)
+ #include "stm32f107xc.h"
+#else
+ #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f1xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F1xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/cmsis/system_stm32f1xx.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/cmsis/system_stm32f1xx.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,448 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f1xx.c
+ * @author MCD Application Team
+ * @version V4.1.0
+ * @date 29-April-2016
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+ * factors, AHB/APBx prescalers and Flash settings).
+ * This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f1xx_xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
+ * the product used), refer to "HSE_VALUE".
+ * When HSE is used as system clock source, directly or through PLL, and you
+ * are using different crystal you have to adapt the HSE value to your own
+ * configuration.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f1xx_system
+ * @{
+ */
+
+/** @addtogroup STM32F1xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f1xx.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F1xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F1xx_System_Private_Defines
+ * @{
+ */
+
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSI_VALUE */
+
+/*!< Uncomment the following line if you need to use external SRAM */
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+/* #define DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F1xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F1xx_System_Private_Variables
+ * @{
+ */
+
+/*******************************************************************************
+* Clock Definitions
+*******************************************************************************/
+#if defined(STM32F100xB) ||defined(STM32F100xE)
+ uint32_t SystemCoreClock = 24000000; /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+ uint32_t SystemCoreClock = 72000000; /*!< System Clock Frequency (Core Clock) */
+#endif
+
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+#ifdef DATA_IN_ExtSRAM
+ static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F1xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the Embedded Flash Interface, the PLL and update the
+ * SystemCoreClock variable.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+ /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#if !defined(STM32F105xC) && !defined(STM32F107xC)
+ RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+ RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F105xC */
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ /* Reset PLL2ON and PLL3ON bits */
+ RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x00FF0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#elif defined(STM32F100xB) || defined(STM32F100xE)
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#else
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+#endif /* STM32F105xC */
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+ #ifdef DATA_IN_ExtSRAM
+ SystemInit_ExtMemCtl();
+ #endif /* DATA_IN_ExtSRAM */
+#endif
+
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+ * 8 MHz or 25 MHz, depending on the product used), user has to ensure
+ * that HSE_VALUE is same as the real frequency of the crystal used.
+ * Otherwise, this function may have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+ uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F105xC */
+
+#if defined(STM32F100xB) || defined(STM32F100xE)
+ uint32_t prediv1factor = 0;
+#endif /* STM32F100xB or STM32F100xE */
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock */
+
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+#if !defined(STM32F105xC) && !defined(STM32F107xC)
+ pllmull = ( pllmull >> 18) + 2;
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ #if defined(STM32F100xB) || defined(STM32F100xE)
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+ #else
+ /* HSE selected as PLL clock entry */
+ if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+ {/* HSE oscillator clock divided by 2 */
+ SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ SystemCoreClock = HSE_VALUE * pllmull;
+ }
+ #endif
+ }
+#else
+ pllmull = pllmull >> 18;
+
+ if (pllmull != 0x0D)
+ {
+ pllmull += 2;
+ }
+ else
+ { /* PLL multiplication factor = PLL input clock * 6.5 */
+ pllmull = 13 / 2;
+ }
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {/* PREDIV1 selected as PLL clock entry */
+
+ /* Get PREDIV1 clock source and division factor */
+ prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+
+ if (prediv1source == 0)
+ {
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+ }
+ else
+ {/* PLL2 clock selected as PREDIV1 clock entry */
+
+ /* Get PREDIV2 division factor and PLL2 multiplication factor */
+ prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+ pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
+ SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
+ }
+ }
+#endif /* STM32F105xC */
+ break;
+
+ default:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+/**
+ * @brief Setup the external memory controller. Called in startup_stm32f1xx.s
+ * before jump to __main
+ * @param None
+ * @retval None
+ */
+#ifdef DATA_IN_ExtSRAM
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32f1xx_xx.s/.c before jump to main.
+ * This function configures the external SRAM mounted on STM3210E-EVAL
+ * board (STM32 High density devices). This SRAM will be used as program
+ * data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+ __IO uint32_t tmpreg;
+ /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
+ required, then adjust the Register Addresses */
+
+ /* Enable FSMC clock */
+ RCC->AHBENR = 0x00000114;
+
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
+
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
+ RCC->APB2ENR = 0x000001E0;
+
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
+
+ (void)(tmpreg);
+
+/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
+/*---------------- SRAM Address lines configuration -------------------------*/
+/*---------------- NOE and NWE configuration --------------------------------*/
+/*---------------- NE3 configuration ----------------------------------------*/
+/*---------------- NBL0, NBL1 configuration ---------------------------------*/
+
+ GPIOD->CRL = 0x44BB44BB;
+ GPIOD->CRH = 0xBBBBBBBB;
+
+ GPIOE->CRL = 0xB44444BB;
+ GPIOE->CRH = 0xBBBBBBBB;
+
+ GPIOF->CRL = 0x44BBBBBB;
+ GPIOF->CRH = 0xBBBB4444;
+
+ GPIOG->CRL = 0x44BBBBBB;
+ GPIOG->CRH = 0x444B4B44;
+
+/*---------------- FSMC Configuration ---------------------------------------*/
+/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
+
+ FSMC_Bank1->BTCR[4] = 0x00001091;
+ FSMC_Bank1->BTCR[5] = 0x00110212;
+}
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/cmsis/system_stm32f1xx.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/cmsis/system_stm32f1xx.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,116 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f10x.h
+ * @author MCD Application Team
+ * @version V4.1.0
+ * @date 29-April-2016
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f10x_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F10X_H
+#define __SYSTEM_STM32F10X_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F10x_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F10x_System_Exported_types
+ * @{
+ */
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F10X_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/daplink_addr.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/stm32/stm32f103xb/daplink_addr.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,82 @@ +/** + * @file daplink_addr.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef DAPLINK_ADDR_H +#define DAPLINK_ADDR_H + +/* Device sizes */ + +#define DAPLINK_ROM_START 0x08000000 +#define DAPLINK_ROM_SIZE 0x00020000 + +#define DAPLINK_RAM_START 0x20000000 +#define DAPLINK_RAM_SIZE 0x00005000 + +/* ROM sizes */ + +#define DAPLINK_ROM_BL_START 0x08000000 +#define DAPLINK_ROM_BL_SIZE 0x0000BC00 + +#define DAPLINK_ROM_CONFIG_ADMIN_START 0x0800BC00 +#define DAPLINK_ROM_CONFIG_ADMIN_SIZE 0x00000400 + +#define DAPLINK_ROM_IF_START 0x0800C000 +#define DAPLINK_ROM_IF_SIZE 0x00013C00 + +#define DAPLINK_ROM_CONFIG_USER_START 0x0801FC00 +#define DAPLINK_ROM_CONFIG_USER_SIZE 0x00000400 + +/* RAM sizes */ + +#define DAPLINK_RAM_APP_START 0x20000000 +#define DAPLINK_RAM_APP_SIZE 0x00004F00 + +#define DAPLINK_RAM_SHARED_START 0x20004F00 +#define DAPLINK_RAM_SHARED_SIZE 0x00000100 + +/* Flash Programming Info */ + +#define DAPLINK_SECTOR_SIZE 0x00000400 +#define DAPLINK_MIN_WRITE_SIZE 0x00000400 + +/* Current build */ + +#if defined(DAPLINK_BL) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_BL_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_IF_SIZE + +#elif defined(DAPLINK_IF) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_IF_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_BL_SIZE + +#else + +#error "Build must be either bootloader or interface" + +#endif + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/flash.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/flash.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,120 @@
+/**
+ * @file flash_hal_stm32f103xb.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_hal.h" // FlashOS Structures
+#include "target_config.h" // target_device
+#include "stm32f1xx.h"
+#include "util.h"
+#include "string.h"
+#include "target_board.h"
+
+/*********************************************************************
+*
+* Static code
+*
+**********************************************************************
+*/
+
+/*********************************************************************
+*
+* Public code
+*
+**********************************************************************
+*/
+uint32_t Init(uint32_t adr, uint32_t clk, uint32_t fnc)
+{
+ //
+ // No special init required
+ //
+ return (0);
+}
+
+uint32_t UnInit(uint32_t fnc)
+{
+ //
+ // No special uninit required
+ //
+ return (0);
+}
+
+uint32_t EraseChip(void)
+{
+ FLASH_EraseInitTypeDef erase_init;
+ uint32_t error;
+ uint32_t ret = 0; // O.K.
+ if (g_board_info.target_cfg) {
+ HAL_FLASH_Unlock();
+ //bootloader, interface flashing only concerns 1 flash region
+ util_assert((g_board_info.target_cfg->flash_regions[0].end - g_board_info.target_cfg->flash_regions[0].start) %
+ FLASH_PAGE_SIZE == 0);
+ memset(&erase_init, 0, sizeof(erase_init));
+ erase_init.TypeErase = FLASH_TYPEERASE_PAGES;
+ erase_init.PageAddress = g_board_info.target_cfg->flash_regions[0].start;
+ erase_init.NbPages = (g_board_info.target_cfg->flash_regions[0].end - g_board_info.target_cfg->flash_regions[0].start) % FLASH_PAGE_SIZE;
+ if (HAL_FLASHEx_Erase(&erase_init, &error) != HAL_OK) {
+ ret = 1;
+ }
+
+ HAL_FLASH_Lock();
+ }else{
+ ret = 1;
+ }
+ return ret;
+}
+
+uint32_t EraseSector(uint32_t adr)
+{
+ FLASH_EraseInitTypeDef erase_init;
+ uint32_t error;
+ uint32_t ret = 0; // O.K.
+
+ HAL_FLASH_Unlock();
+
+ memset(&erase_init, 0, sizeof(erase_init));
+ erase_init.TypeErase = FLASH_TYPEERASE_PAGES;
+ erase_init.PageAddress = adr;
+ erase_init.NbPages = 1;
+ if (HAL_FLASHEx_Erase(&erase_init, &error) != HAL_OK) {
+ ret = 1;
+ }
+
+ HAL_FLASH_Lock();
+ return ret;
+}
+
+uint32_t ProgramPage(uint32_t adr, uint32_t sz, uint32_t *buf)
+{
+ uint32_t i;
+ uint32_t ret = 0; // O.K.
+
+ HAL_FLASH_Unlock();
+
+ util_assert(sz % 4 == 0);
+ for (i = 0; i < sz / 4; i++) {
+ if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, adr + i * 4, buf[i]) != HAL_OK) {
+ ret = 1;
+ break;
+ }
+ }
+
+ HAL_FLASH_Lock();
+ return ret;
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/gpio.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/gpio.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,232 @@
+/**
+ * @file gpio.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "stm32f1xx.h"
+#include "DAP_config.h"
+#include "gpio.h"
+#include "daplink.h"
+#include "util.h"
+
+static TIM_HandleTypeDef timer;
+
+static void busy_wait(uint32_t cycles)
+{
+ volatile uint32_t i;
+ i = cycles;
+
+ while (i > 0) {
+ i--;
+ }
+}
+
+static uint32_t tim1_clk_div(uint32_t apb2clkdiv)
+{
+ switch (apb2clkdiv) {
+ case RCC_CFGR_PPRE2_DIV2:
+ return 1;
+ case RCC_CFGR_PPRE2_DIV4:
+ return 2;
+ case RCC_CFGR_PPRE2_DIV8:
+ return 4;
+ default: // RCC_CFGR_PPRE2_DIV1
+ return 1;
+ }
+}
+
+static void output_clock_enable(void)
+{
+ HAL_StatusTypeDef ret;
+ RCC_ClkInitTypeDef clk_init;
+ TIM_OC_InitTypeDef pwm_config;
+ uint32_t unused;
+ uint32_t period;
+ uint32_t source_clock;
+
+ HAL_RCC_GetClockConfig(&clk_init, &unused);
+
+ /* Compute the period value to have TIMx counter clock equal to 8000000 Hz */
+ source_clock = SystemCoreClock / tim1_clk_div(clk_init.APB2CLKDivider);
+ period = (uint32_t)(source_clock / 8000000) - 1;
+
+ /* Set TIMx instance */
+ timer.Instance = TIM1;
+
+ timer.Init.Period = period;
+ timer.Init.Prescaler = 0;
+ timer.Init.ClockDivision = 0;
+ timer.Init.CounterMode = TIM_COUNTERMODE_UP;
+ timer.Init.RepetitionCounter = 0;//period / 2;
+
+ __HAL_RCC_TIM1_CLK_ENABLE();
+
+ ret = HAL_TIM_PWM_DeInit(&timer);
+ if (ret != HAL_OK) {
+ util_assert(0);
+ return;
+ }
+
+ ret = HAL_TIM_PWM_Init(&timer);
+ if (ret != HAL_OK) {
+ util_assert(0);
+ return;
+ }
+
+ pwm_config.OCMode = TIM_OCMODE_PWM2;
+ pwm_config.Pulse = 0; // TODO - make sure this isn't used
+ pwm_config.OCPolarity = TIM_OCPOLARITY_HIGH;
+ pwm_config.OCNPolarity = TIM_OCPOLARITY_HIGH;
+ pwm_config.OCFastMode = TIM_OCFAST_DISABLE;
+ pwm_config.OCIdleState = TIM_OCIDLESTATE_RESET;
+ pwm_config.OCNIdleState = TIM_OCIDLESTATE_RESET;
+ ret = HAL_TIM_PWM_ConfigChannel(&timer, &pwm_config, TIM_CHANNEL_1);
+ if (ret != HAL_OK) {
+ util_assert(0);
+ return;
+ }
+
+ __HAL_TIM_SET_COMPARE(&timer, TIM_CHANNEL_1, period / 2);
+ ret = HAL_TIM_PWM_Start(&timer, TIM_CHANNEL_1);
+ if (ret != HAL_OK) {
+ util_assert(0);
+ return;
+ }
+
+ return;
+}
+
+void gpio_init(void)
+{
+ GPIO_InitTypeDef GPIO_InitStructure;
+ // enable clock to ports
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+ // Enable USB connect pin
+ __HAL_RCC_AFIO_CLK_ENABLE();
+ // Disable JTAG to free pins for other uses
+ // Note - SWD is still enabled
+ __HAL_AFIO_REMAP_SWJ_NOJTAG();
+
+ USB_CONNECT_PORT_ENABLE();
+ USB_CONNECT_OFF();
+ GPIO_InitStructure.Pin = USB_CONNECT_PIN;
+ GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_HIGH;
+ GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP;
+ HAL_GPIO_Init(USB_CONNECT_PORT, &GPIO_InitStructure);
+ // configure LEDs
+ HAL_GPIO_WritePin(RUNNING_LED_PORT, RUNNING_LED_PIN, GPIO_PIN_SET);
+ GPIO_InitStructure.Pin = RUNNING_LED_PIN;
+ GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_HIGH;
+ GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP;
+ HAL_GPIO_Init(RUNNING_LED_PORT, &GPIO_InitStructure);
+
+ HAL_GPIO_WritePin(CONNECTED_LED_PORT, CONNECTED_LED_PIN, GPIO_PIN_SET);
+ GPIO_InitStructure.Pin = CONNECTED_LED_PIN;
+ GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_HIGH;
+ GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP;
+ HAL_GPIO_Init(CONNECTED_LED_PORT, &GPIO_InitStructure);
+
+ HAL_GPIO_WritePin(PIN_CDC_LED_PORT, PIN_CDC_LED, GPIO_PIN_SET);
+ GPIO_InitStructure.Pin = PIN_CDC_LED;
+ GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_HIGH;
+ GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP;
+ HAL_GPIO_Init(PIN_CDC_LED_PORT, &GPIO_InitStructure);
+
+ HAL_GPIO_WritePin(PIN_MSC_LED_PORT, PIN_MSC_LED, GPIO_PIN_SET);
+ GPIO_InitStructure.Pin = PIN_MSC_LED;
+ GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_HIGH;
+ GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP;
+ HAL_GPIO_Init(PIN_MSC_LED_PORT, &GPIO_InitStructure);
+
+ // reset button configured as gpio open drain output with a pullup
+ HAL_GPIO_WritePin(nRESET_PIN_PORT, nRESET_PIN, GPIO_PIN_SET);
+ GPIO_InitStructure.Pin = nRESET_PIN;
+ GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_OD;
+ GPIO_InitStructure.Pull = GPIO_PULLUP;
+ HAL_GPIO_Init(nRESET_PIN_PORT, &GPIO_InitStructure);
+
+ // Turn on power to the board. When the target is unpowered
+ // it holds the reset line low.
+ HAL_GPIO_WritePin(POWER_EN_PIN_PORT, POWER_EN_PIN, GPIO_PIN_RESET);
+ GPIO_InitStructure.Pin = POWER_EN_PIN;
+ GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_HIGH;
+ GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP;
+ HAL_GPIO_Init(POWER_EN_PIN_PORT, &GPIO_InitStructure);
+
+ // Setup the 8MHz MCO
+ GPIO_InitStructure.Pin = GPIO_PIN_8;
+ GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_HIGH;
+ GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
+ output_clock_enable();
+
+ // Let the voltage rails stabilize. This is especailly important
+ // during software resets, since the target's 3.3v rail can take
+ // 20-50ms to drain. During this time the target could be driving
+ // the reset pin low, causing the bootloader to think the reset
+ // button is pressed.
+ // Note: With optimization set to -O2 the value 1000000 delays for ~85ms
+ busy_wait(1000000);
+}
+
+void gpio_set_hid_led(gpio_led_state_t state)
+{
+ // LED is active low
+ HAL_GPIO_WritePin(PIN_HID_LED_PORT, PIN_HID_LED, state ? GPIO_PIN_RESET : GPIO_PIN_SET);
+}
+
+void gpio_set_cdc_led(gpio_led_state_t state)
+{
+ // LED is active low
+ HAL_GPIO_WritePin(PIN_CDC_LED_PORT, PIN_CDC_LED, state ? GPIO_PIN_RESET : GPIO_PIN_SET);
+}
+
+void gpio_set_msc_led(gpio_led_state_t state)
+{
+ // LED is active low
+ HAL_GPIO_WritePin(PIN_MSC_LED_PORT, PIN_MSC_LED, state ? GPIO_PIN_RESET : GPIO_PIN_SET);
+}
+
+uint8_t gpio_get_reset_btn_no_fwrd(void)
+{
+ return (nRESET_PIN_PORT->IDR & nRESET_PIN) ? 0 : 1;
+}
+
+uint8_t gpio_get_reset_btn_fwrd(void)
+{
+ return 0;
+}
+
+
+uint8_t GPIOGetButtonState(void)
+{
+ return 0;
+}
+
+void target_forward_reset(bool assert_reset)
+{
+ // Do nothing - reset is forwarded in gpio_get_sw_reset
+}
+
+void gpio_set_board_power(bool powerEnabled)
+{
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/read_uid.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/read_uid.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,37 @@
+/**
+ * @file read_uid.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "stm32f1xx.h"
+#include "read_uid.h"
+
+void read_unique_id(uint32_t *id)
+{
+ uint32_t Device_Serial0, Device_Serial1, Device_Serial2;
+
+ Device_Serial0 = *(uint32_t*)(0x1FFFF7E8);
+ Device_Serial1 = *(uint32_t*)(0x1FFFF7EC);
+ Device_Serial2 = *(uint32_t*)(0x1FFFF7F0);
+
+ id[0] = Device_Serial0;
+ id[1] = Device_Serial1;
+ id[2] = Device_Serial2;
+ id[3] = 0xA5A5A5A5;
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/sdk.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/sdk.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,175 @@
+/**
+ * @file sdk.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "stm32f1xx.h"
+#include "DAP_config.h"
+#include "gpio.h"
+#include "daplink.h"
+#include "util.h"
+#include "cortex_m.h"
+
+TIM_HandleTypeDef timer;
+uint32_t time_count;
+
+static uint32_t tim2_clk_div(uint32_t apb1clkdiv);
+
+/**
+ * @brief Switch the PLL source from HSI to HSE bypass, and select the PLL as SYSCLK
+ * source.
+ * The system Clock is configured as follow :
+ * System Clock source = PLL (HSE bypass)
+ * SYSCLK(Hz) = 72000000
+ * HCLK(Hz) = 72000000
+ * AHB Prescaler = 1
+ * APB1 Prescaler = 2
+ * APB2 Prescaler = 1
+ * HSE Frequency(Hz) = 8000000
+ * HSE PREDIV1 = 1
+ * PLLMUL = 9
+ * Flash Latency(WS) = 2
+ * @param None
+ * @retval None
+ */
+void sdk_init()
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+
+ SystemCoreClockUpdate();
+ HAL_Init();
+
+ /* Select HSI as system clock source to allow modification of the PLL configuration */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ /* Initialization Error */
+ util_assert(0);
+ }
+
+ /* Enable HSE bypass Oscillator, select it as PLL source and finally activate the PLL */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSEState = RCC_CR_HSEON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ /* Initialization Error */
+ util_assert(0);
+ }
+
+ /* Select the PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+ /* Initialization Error */
+ util_assert(0);
+ }
+}
+
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ HAL_StatusTypeDef ret;
+ RCC_ClkInitTypeDef clk_init;
+ uint32_t unused;
+ uint32_t prescaler;
+ uint32_t source_clock;
+
+ HAL_RCC_GetClockConfig(&clk_init, &unused);
+
+ /* Compute the prescaler value to have TIMx counter clock equal to 4000 Hz */
+ source_clock = SystemCoreClock / tim2_clk_div(clk_init.APB1CLKDivider);
+ prescaler = (uint32_t)(source_clock / 4000) - 1;
+
+ /* Set TIMx instance */
+ timer.Instance = TIM2;
+
+ timer.Init.Period = 0xFFFF;
+ timer.Init.Prescaler = prescaler;
+ timer.Init.ClockDivision = 0;
+ timer.Init.CounterMode = TIM_COUNTERMODE_UP;
+ timer.Init.RepetitionCounter = 0;
+
+ __HAL_RCC_TIM2_CLK_ENABLE();
+
+ ret = HAL_TIM_Base_DeInit(&timer);
+ if (ret != HAL_OK) {
+ return ret;
+ }
+
+ time_count = 0;
+ ret = HAL_TIM_Base_Init(&timer);
+ if (ret != HAL_OK) {
+ return ret;
+ }
+
+ ret = HAL_TIM_Base_Start(&timer);
+ if (ret != HAL_OK) {
+ return ret;
+ }
+
+ return HAL_OK;
+}
+
+
+void HAL_IncTick(void)
+{
+ // Do nothing
+}
+
+uint32_t HAL_GetTick(void)
+{
+ cortex_int_state_t state;
+ state = cortex_int_get_and_disable();
+ const uint32_t ticks = __HAL_TIM_GET_COUNTER(&timer) / 4;
+ time_count += (ticks - time_count) & 0x3FFF;
+ cortex_int_restore(state);
+ return time_count;
+}
+
+void HAL_SuspendTick(void)
+{
+ HAL_TIM_Base_Start(&timer);
+}
+
+void HAL_ResumeTick(void)
+{
+ HAL_TIM_Base_Stop(&timer);
+}
+
+static uint32_t tim2_clk_div(uint32_t apb1clkdiv)
+{
+ switch (apb1clkdiv) {
+ case RCC_CFGR_PPRE1_DIV2:
+ return 1;
+ case RCC_CFGR_PPRE1_DIV4:
+ return 2;
+ case RCC_CFGR_PPRE1_DIV8:
+ return 4;
+ case RCC_CFGR_PPRE1_DIV16:
+ return 8;
+ default:
+ return 1;
+ }
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/uart.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/uart.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,254 @@
+/**
+ * @file uart.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "string.h"
+
+#include "stm32f1xx.h"
+#include "uart.h"
+#include "gpio.h"
+#include "util.h"
+#include "circ_buf.h"
+#include "IO_Config.h"
+
+// For usart
+#define CDC_UART USART2
+#define CDC_UART_ENABLE() __HAL_RCC_USART2_CLK_ENABLE()
+#define CDC_UART_DISABLE() __HAL_RCC_USART2_CLK_DISABLE()
+#define CDC_UART_IRQn USART2_IRQn
+#define CDC_UART_IRQn_Handler USART2_IRQHandler
+
+#define UART_PINS_PORT_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
+#define UART_PINS_PORT_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE()
+
+#define UART_TX_PORT GPIOA
+#define UART_TX_PIN GPIO_PIN_2
+
+#define UART_RX_PORT GPIOA
+#define UART_RX_PIN GPIO_PIN_3
+
+#define UART_CTS_PORT GPIOA
+#define UART_CTS_PIN GPIO_PIN_0
+
+#define UART_RTS_PORT GPIOA
+#define UART_RTS_PIN GPIO_PIN_1
+
+
+#define RX_OVRF_MSG "<DAPLink:Overflow>\n"
+#define RX_OVRF_MSG_SIZE (sizeof(RX_OVRF_MSG) - 1)
+#define BUFFER_SIZE (512)
+
+circ_buf_t write_buffer;
+uint8_t write_buffer_data[BUFFER_SIZE];
+circ_buf_t read_buffer;
+uint8_t read_buffer_data[BUFFER_SIZE];
+
+static UART_Configuration configuration = {
+ .Baudrate = 9600,
+ .DataBits = UART_DATA_BITS_8,
+ .Parity = UART_PARITY_NONE,
+ .StopBits = UART_STOP_BITS_1,
+ .FlowControl = UART_FLOW_CONTROL_NONE,
+};
+
+extern uint32_t SystemCoreClock;
+
+
+
+static void clear_buffers(void)
+{
+ circ_buf_init(&write_buffer, write_buffer_data, sizeof(write_buffer_data));
+ circ_buf_init(&read_buffer, read_buffer_data, sizeof(read_buffer_data));
+}
+
+int32_t uart_initialize(void)
+{
+ GPIO_InitTypeDef GPIO_InitStructure;
+
+ CDC_UART->CR1 &= ~(USART_IT_TXE | USART_IT_RXNE);
+ clear_buffers();
+
+ CDC_UART_ENABLE();
+ UART_PINS_PORT_ENABLE();
+
+ //TX pin
+ GPIO_InitStructure.Pin = UART_TX_PIN;
+ GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_HIGH;
+ GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
+ HAL_GPIO_Init(UART_TX_PORT, &GPIO_InitStructure);
+ //RX pin
+ GPIO_InitStructure.Pin = UART_RX_PIN;
+ GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_HIGH;
+ GPIO_InitStructure.Mode = GPIO_MODE_INPUT;
+ GPIO_InitStructure.Pull = GPIO_PULLUP;
+ HAL_GPIO_Init(UART_RX_PORT, &GPIO_InitStructure);
+ //CTS pin, input
+ GPIO_InitStructure.Pin = UART_CTS_PIN;
+ GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_HIGH;
+ GPIO_InitStructure.Mode = GPIO_MODE_INPUT;
+ GPIO_InitStructure.Pull = GPIO_PULLUP;
+ HAL_GPIO_Init(UART_CTS_PORT, &GPIO_InitStructure);
+ //RTS pin, output low
+ HAL_GPIO_WritePin(UART_RTS_PORT, UART_RTS_PIN, GPIO_PIN_RESET);
+ GPIO_InitStructure.Pin = UART_RTS_PIN;
+ GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_HIGH;
+ GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP;
+ HAL_GPIO_Init(UART_RTS_PORT, &GPIO_InitStructure);
+
+ NVIC_EnableIRQ(CDC_UART_IRQn);
+
+ return 1;
+}
+
+int32_t uart_uninitialize(void)
+{
+ CDC_UART->CR1 &= ~(USART_IT_TXE | USART_IT_RXNE);
+ clear_buffers();
+ return 1;
+}
+
+int32_t uart_reset(void)
+{
+ const uint32_t cr1 = CDC_UART->CR1;
+ CDC_UART->CR1 = cr1 & ~(USART_IT_TXE | USART_IT_RXNE);
+ clear_buffers();
+ CDC_UART->CR1 = cr1 & ~USART_IT_TXE;
+ return 1;
+}
+
+int32_t uart_set_configuration(UART_Configuration *config)
+{
+ UART_HandleTypeDef uart_handle;
+ HAL_StatusTypeDef status;
+
+ memset(&uart_handle, 0, sizeof(uart_handle));
+ uart_handle.Instance = CDC_UART;
+
+ // parity
+ configuration.Parity = config->Parity;
+ if(config->Parity == UART_PARITY_ODD) {
+ uart_handle.Init.Parity = HAL_UART_PARITY_ODD;
+ } else if(config->Parity == UART_PARITY_EVEN) {
+ uart_handle.Init.Parity = HAL_UART_PARITY_EVEN;
+ } else if(config->Parity == UART_PARITY_NONE) {
+ uart_handle.Init.Parity = HAL_UART_PARITY_NONE;
+ } else { //Other not support
+ uart_handle.Init.Parity = HAL_UART_PARITY_NONE;
+ configuration.Parity = UART_PARITY_NONE;
+ }
+
+ // stop bits
+ configuration.StopBits = config->StopBits;
+ if(config->StopBits == UART_STOP_BITS_2) {
+ uart_handle.Init.StopBits = UART_STOPBITS_2;
+ } else if(config->StopBits == UART_STOP_BITS_1_5) {
+ uart_handle.Init.StopBits = UART_STOPBITS_2;
+ configuration.StopBits = UART_STOP_BITS_2;
+ } else if(config->StopBits == UART_STOP_BITS_1) {
+ uart_handle.Init.StopBits = UART_STOPBITS_1;
+ } else {
+ uart_handle.Init.StopBits = UART_STOPBITS_1;
+ configuration.StopBits = UART_STOP_BITS_1;
+ }
+
+ //Only 8 bit support
+ configuration.DataBits = UART_DATA_BITS_8;
+ uart_handle.Init.WordLength = UART_WORDLENGTH_8B;
+
+ // No flow control
+ configuration.FlowControl = UART_FLOW_CONTROL_NONE;
+ uart_handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+
+ // Specified baudrate
+ configuration.Baudrate = config->Baudrate;
+ uart_handle.Init.BaudRate = config->Baudrate;
+
+ // TX and RX
+ uart_handle.Init.Mode = UART_MODE_TX_RX;
+
+ // Disable uart and tx/rx interrupt
+ CDC_UART->CR1 &= ~(USART_IT_TXE | USART_IT_RXNE);
+
+ clear_buffers();
+
+ status = HAL_UART_DeInit(&uart_handle);
+ util_assert(HAL_OK == status);
+ status = HAL_UART_Init(&uart_handle);
+ util_assert(HAL_OK == status);
+ (void)status;
+
+ CDC_UART->CR1 |= USART_IT_RXNE;
+
+ return 1;
+}
+
+int32_t uart_get_configuration(UART_Configuration *config)
+{
+ config->Baudrate = configuration.Baudrate;
+ config->DataBits = configuration.DataBits;
+ config->Parity = configuration.Parity;
+ config->StopBits = configuration.StopBits;
+ config->FlowControl = UART_FLOW_CONTROL_NONE;
+
+ return 1;
+}
+
+int32_t uart_write_free(void)
+{
+ return circ_buf_count_free(&write_buffer);
+}
+
+int32_t uart_write_data(uint8_t *data, uint16_t size)
+{
+ uint32_t cnt = circ_buf_write(&write_buffer, data, size);
+ CDC_UART->CR1 |= USART_IT_TXE;
+
+ return cnt;
+}
+
+int32_t uart_read_data(uint8_t *data, uint16_t size)
+{
+ return circ_buf_read(&read_buffer, data, size);
+}
+
+void CDC_UART_IRQn_Handler(void)
+{
+ const uint32_t sr = CDC_UART->SR;
+
+ if (sr & USART_SR_RXNE) {
+ uint8_t dat = CDC_UART->DR;
+ uint32_t free = circ_buf_count_free(&read_buffer);
+ if (free > RX_OVRF_MSG_SIZE) {
+ circ_buf_push(&read_buffer, dat);
+ } else if (RX_OVRF_MSG_SIZE == free) {
+ circ_buf_write(&read_buffer, (uint8_t*)RX_OVRF_MSG, RX_OVRF_MSG_SIZE);
+ } else {
+ // Drop character
+ }
+ }
+
+ if (sr & USART_SR_TXE) {
+ if (circ_buf_count_used(&write_buffer) > 0) {
+ CDC_UART->DR = circ_buf_pop(&write_buffer);
+ } else {
+ CDC_UART->CR1 &= ~USART_IT_TXE;
+ }
+ }
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/usb_buf.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/stm32/stm32f103xb/usb_buf.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,31 @@ +/** + * @file usb_buf.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef USB_BUF_H +#define USB_BUF_H + + +#include "stdint.h" + +#define USB_MSC_BUF_SIZE (512) +uint32_t usb_buffer[USB_MSC_BUF_SIZE / sizeof(uint32_t)]; + +#endif
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/usb_config.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/hic_hal/stm32/stm32f103xb/usb_config.c Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,554 @@ +/** + * @file usb_config.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "util.h" + +// <e> USB Device +// <i> Enable the USB Device functionality +#define USBD_ENABLE 1 +#define USBD_RTX_CORE_STACK 0 +#define USBD_RTX_DEVICE_STACK 0 +#define USBD_RTX_ENDPOINT0_STACK 0 + +// <o0.0> High-speed +// <i> Enable high-speed functionality (if device supports it) +#define USBD_HS_ENABLE 0 +#if (defined(WEBUSB_INTERFACE) || defined(WINUSB_INTERFACE) || defined(BULK_ENDPOINT)) +#define USBD_BOS_ENABLE 1 +#else +#define USBD_BOS_ENABLE 0 +#endif +// <h> Device Settings +// <i> These settings affect Device Descriptor +// <o0> Power +// <i> Default Power Setting +// <0=> Bus-powered +// <1=> Self-powered +// <o1> Max Endpoint 0 Packet Size +// <i> Maximum packet size for endpoint zero (bMaxPacketSize0) +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes +// <o2.0..15> Vendor ID <0x0000-0xFFFF> +// <i> Vendor ID assigned by the USB-IF (idVendor) +// <o3.0..15> Product ID <0x0000-0xFFFF> +// <i> Product ID assigned by the manufacturer (idProduct) +// <o4.0..15> Device Release Number <0x0000-0xFFFF> +// <i> Device release number in binary-coded decimal (bcdDevice) +// </h> +#define USBD_POWER 0 +#define USBD_MAX_PACKET0 64 +#define USBD_DEVDESC_IDVENDOR 0x0D28 +#define USBD_DEVDESC_IDPRODUCT 0x0204 +#define USBD_DEVDESC_BCDDEVICE 0x0100 //was 0x0100 + +// <h> Configuration Settings +// <i> These settings affect Configuration Descriptor +// <o0.5> Remote Wakeup +// <i> Configuration support for remote wakeup (D5: of bmAttributes) +// <o1.0..7> Maximum Power Consumption (in mA) <0-510><#/2> +// <i> Maximum power consumption of the USB device +// <i> from the bus in this specific configuration +// <i> when the device is fully operational (bMaxPower) +// </h> +#define USBD_CFGDESC_BMATTRIBUTES 0x80 +#define USBD_CFGDESC_BMAXPOWER 0xFA + +// <h> String Settings +// <i> These settings affect String Descriptor +// <o0.0..15> Language ID <0x0000-0xFCFF> +// <i> English (United States) = 0x0409 +// <s0.126> Manufacturer String +// <i> String descriptor describing manufacturer +// <s1.126> Product String +// <i> String descriptor describing product +// <e1.0> Serial Number +// <i> Enable serial number string +// <i> If disabled serial number string will not be assigned to the USB Device +// <s2.126> Serial Number String +// <i> String descriptor describing device's serial number +// </e> +// </h> +#define USBD_STRDESC_LANGID 0x0409 +#define USBD_STRDESC_MAN L"ARM" +#define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" +#define USBD_STRDESC_SER_ENABLE 1 +#define USBD_STRDESC_SER L"0001A0000000" + +// <e0> Class Support +// <i> Enables USB Device Class specific Requests +#define USBD_CLASS_ENABLE 1 + +// <e0.0> Human Interface Device (HID) +// <i> Enable class support for Human Interface Device (HID) +// <h> Interrupt Endpoint Settings +// <o1.0..4> Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o2.0..4> Interrupt Out Endpoint Number <0=> Not used <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <i> If interrupt out endpoint is not used select "Not used" +// <h> Endpoint Settings +// <o3.0..7> Maximum Endpoint Packet Size (in bytes) <0-64> +// <o4.0..7> Endpoint polling Interval (in ms) <1-255> +// <e5> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o6.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o6.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// <o7.0..7> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// </e> +// </h> +// </h> +// <h> Human Interface Device Settings +// <i> Device specific settings +// <s0.126> HID Interface String +// <o8.0..4> Number of Input Reports <1-32> +// <o9.0..4> Number of Output Reports <1-32> +// <o10.0..15> Maximum Input Report Size (in bytes) <1-65535> +// <o11.0..15> Maximum Output Report Size (in bytes) <1-65535> +// <o12.0..15> Maximum Feature Report Size (in bytes) <1-65535> +// </h> +// </e> +#ifndef HID_ENDPOINT +#define HID_ENDPOINT 0 +#else +#define HID_ENDPOINT 1 +#endif + +#ifndef WEBUSB_INTERFACE +#define WEBUSB_INTERFACE 0 +#else +#define WEBUSB_INTERFACE 1 +#endif + +#define USBD_HID_ENABLE HID_ENDPOINT +#ifndef BULK_ENDPOINT //check if bulk endpoint is not enabled +#define USBD_HID_EP_INTIN 1 +#define USBD_HID_EP_INTOUT 1 +#else //if bulk endpoint is enabled remove interrupt endpoints from the hid +#define USBD_HID_EP_INTIN 0 +#define USBD_HID_EP_INTOUT 0 +#endif +#define USBD_HID_EP_INTIN_STACK 0 +#define USBD_HID_WMAXPACKETSIZE 64 +#define USBD_HID_BINTERVAL 1 +#define USBD_HID_HS_ENABLE 0 +#define USBD_HID_HS_WMAXPACKETSIZE 64 +#define USBD_HID_HS_BINTERVAL 6 +#define USBD_HID_STRDESC L"CMSIS-DAP v1" +#define USBD_WEBUSB_STRDESC L"WebUSB: CMSIS-DAP" +#define USBD_HID_INREPORT_NUM 1 +#define USBD_HID_OUTREPORT_NUM 1 +#define USBD_HID_INREPORT_MAX_SZ 64 +#define USBD_HID_OUTREPORT_MAX_SZ 64 +#define USBD_HID_FEATREPORT_MAX_SZ 1 + +// <e0.0> Mass Storage Device (MSC) +// <i> Enable class support for Mass Storage Device (MSC) +// <h> Bulk Endpoint Settings +// <o1.0..4> Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o2.0..4> Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o3> Maximum Packet Size <1-1024> +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5> Maximum Packet Size <1-1024> +// <o6> Maximum NAK Rate <0-255> +// </e> +// </h> +// </h> +// <h> Mass Storage Device Settings +// <i> Device specific settings +// <s0.126> MSC Interface String +// <h> Inquiry Data +// <s1.8> Vendor Identification +// <s2.16> Product Identification +// <s3.4> Product Revision Level +// </h> +// </h> +// </e> +#ifndef MSC_ENDPOINT +#define MSC_ENDPOINT 0 +#else +#define MSC_ENDPOINT 1 +#endif +#define USBD_MSC_ENABLE MSC_ENDPOINT +#define USBD_MSC_EP_BULKIN 2 +#define USBD_MSC_EP_BULKOUT 2 +#define USBD_MSC_EP_BULKIN_STACK 0 +#define USBD_MSC_WMAXPACKETSIZE 64 +#define USBD_MSC_HS_ENABLE 0 +#define USBD_MSC_HS_WMAXPACKETSIZE 512 +#define USBD_MSC_HS_BINTERVAL 0 +#define USBD_MSC_STRDESC L"USB_MSC" +// Make sure changes to USBD_MSC_INQUIRY_DATA are coordinated with mbed-ls +// since this is used to detect DAPLink drives +#define USBD_MSC_INQUIRY_DATA "MBED " \ + "VFS " \ + "0.1" + +// <e0.0> Audio Device (ADC) +// <i> Enable class support for Audio Device (ADC) +// <h> Isochronous Endpoint Settings +// <o1.0..4> Isochronous Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o2.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o3.0..10> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o5.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// </e> +// </h> +// </h> +// <h> Audio Device Settings +// <i> Device specific settings +// <s0.126> Audio Control Interface String +// <s1.126> Audio Streaming (Zero Bandwidth) Interface String +// <s2.126> Audio Streaming (Operational) Interface String +// <o6.0..7> Audio Subframe Size (in bytes) <0-255> +// <o7.0..7> Sample Resolution (in bits) <0-255> +// <o8.0..23> Sample Frequency (in Hz) <0-16777215> +// <o9> Packet Size (in bytes) <1-256> +// <o10> Packet Count <1-16> +// </h> +// </e> +#define USBD_ADC_ENABLE 0 +#define USBD_ADC_EP_ISOOUT 3 +#define USBD_ADC_WMAXPACKETSIZE 64 +#define USBD_ADC_BINTERVAL 1 +#define USBD_ADC_HS_ENABLE 0 +#define USBD_ADC_HS_WMAXPACKETSIZE 64 +#define USBD_ADC_CIF_STRDESC L"USB_ADC" +#define USBD_ADC_SIF1_STRDESC L"USB_ADC1" +#define USBD_ADC_SIF2_STRDESC L"USB_ADC2" +#define USBD_ADC_BSUBFRAMESIZE 2 +#define USBD_ADC_BBITRESOLUTION 16 +#define USBD_ADC_TSAMFREQ 32000 +#define USBD_ADC_CFG_P_S 32 +#define USBD_ADC_CFG_P_C 1 + +// <e0> Communication Device (CDC) - Abstract Control Model (ACM) +// <i> Enable class support for Communication Device (CDC) - Abstract Control Model (ACM) +// <h> Interrupt Endpoint Settings +// <o1.0..4> Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o2.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o3.0..10> Endpoint polling Interval (in ms) <0-255> +// <e4> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o5.0..10> Maximum Endpoint Packet Size (in bytes) <0-1024> +// <o5.11..12> Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// <o6.0..10> Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// </e4> +// </h> +// </h> +// <h> Bulk Endpoint Settings +// <o7.0..4> Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <o8.0..4> Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// <h> Endpoint Settings +// <o9> Maximum Packet Size <1-1024> +// <e10> High-speed +// <i> If high-speed is enabled set endpoint settings for it +// <o11> Maximum Packet Size <1-1024> +// <o12> Maximum NAK Rate <0-255> +// </e10> +// </h> +// </h> +// <h> Communication Device Settings +// <i> Device specific settings +// <s0.126> Communication Class Interface String +// <s1.126> Data Class Interface String +// <o13> Maximum Communication Device Send Buffer Size +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// <o14> Maximum Communication Device Receive Buffer Size +// <i> Minimum size must be as big as maximum packet size for Bulk Out Endpoint +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// </h> +// </e> + +#ifndef CDC_ENDPOINT +#define CDC_ENDPOINT 0 +#else +#define CDC_ENDPOINT 1 +#endif +#define USBD_CDC_ACM_ENABLE CDC_ENDPOINT +#define USBD_CDC_ACM_EP_INTIN 3 +#define USBD_CDC_ACM_EP_INTIN_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE 16 +#define USBD_CDC_ACM_BINTERVAL 32 +#define USBD_CDC_ACM_HS_ENABLE 0 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE 16 +#define USBD_CDC_ACM_HS_BINTERVAL 2 +#define USBD_CDC_ACM_EP_BULKIN 4 +#define USBD_CDC_ACM_EP_BULKOUT 4 +#define USBD_CDC_ACM_EP_BULKIN_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE1 16 +#define USBD_CDC_ACM_HS_ENABLE1 0 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE1 16 +#define USBD_CDC_ACM_HS_BINTERVAL1 0 +#define USBD_CDC_ACM_CIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_DIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_SENDBUF_SIZE 64 +#define USBD_CDC_ACM_RECEIVEBUF_SIZE 64 +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Send Buffer size must be larger or equal to Bulk In maximum packet size!" +#endif +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Receive Buffer size must be larger or equal to Bulk Out maximum packet size!" +#endif + +// <e0> Custom Class Device +// <i> Enables USB Custom Class Requests +// <i> Class IDs: +// <i> 0x00 - Class Reserved ID +// <i> 0x01 - Class Audio ID +// <i> 0x02 - Class Communications ID +// <i> 0x03 - Class Human Interface ID +// <i> 0x04 - Class Monitor ID +// <i> 0x05 - Class Physical Interface ID +// <i> 0x06 - Class Power ID +// <i> 0x07 - Class Printer ID +// <i> 0x08 - Class Storage ID +// <i> 0x09 - Class HUB ID +// <i> 0xEF - Class Miscellaneous ID +// <i> 0xFF - Class Vendor Specific ID +// </e> +#define USBD_CLS_ENABLE 0 + +// WebUSB support +#define USBD_WEBUSB_ENABLE WEBUSB_INTERFACE +#define USBD_WEBUSB_VENDOR_CODE 0x21 +#define USBD_WEBUSB_LANDING_URL "os.mbed.com/webusb/landing-page/?bid=" +#define USBD_WEBUSB_ORIGIN_URL "os.mbed.com/" + +// Microsoft OS Descriptors 2.0 (WinUSB) support +#define USBD_WINUSB_ENABLE WINUSB_INTERFACE +#define USBD_WINUSB_VENDOR_CODE 0x20 +// </e> +// </e> + +#ifndef BULK_ENDPOINT +#define BULK_ENDPOINT 0 +#else +#define BULK_ENDPOINT 1 +#endif +#define USBD_BULK_ENABLE BULK_ENDPOINT +#define USBD_BULK_EP_BULKIN 1 // fixme: both bulk and hid ep cannot be both enabled in a single build +#define USBD_BULK_EP_BULKOUT 1 +#define USBD_BULK_EP_BULKIN_SWO 6 +#define USBD_BULK_WMAXPACKETSIZE 64 +#define USBD_BULK_HS_ENABLE 0 +#define USBD_BULK_HS_WMAXPACKETSIZE 512 +#define USBD_BULK_STRDESC L"CMSIS-DAP v2" + +/* USB Device Calculations ---------------------------------------------------*/ + +#define USBD_IF_NUM_MAX (USBD_BULK_ENABLE+USBD_WEBUSB_ENABLE+USBD_HID_ENABLE+USBD_MSC_ENABLE+(USBD_ADC_ENABLE*2)+(USBD_CDC_ACM_ENABLE*2)+USBD_CLS_ENABLE) +#define USBD_MULTI_IF (USBD_CDC_ACM_ENABLE*(USBD_HID_ENABLE|USBD_MSC_ENABLE|USBD_ADC_ENABLE|USBD_CLS_ENABLE|USBD_WEBUSB_ENABLE|USBD_BULK_ENABLE)) +// #define MAX(x, y) (((x) < (y)) ? (y) : (x)) +#define USBD_EP_NUM_CALC0 MAX((USBD_HID_ENABLE *(USBD_HID_EP_INTIN )), (USBD_HID_ENABLE *(USBD_HID_EP_INTOUT))) +#define USBD_EP_NUM_CALC1 MAX((USBD_MSC_ENABLE *(USBD_MSC_EP_BULKIN )), (USBD_MSC_ENABLE *(USBD_MSC_EP_BULKOUT))) +#define USBD_EP_NUM_CALC2 MAX((USBD_ADC_ENABLE *(USBD_ADC_EP_ISOOUT )), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_INTIN))) +#define USBD_EP_NUM_CALC3 MAX((USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKIN)), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKOUT))) +#define USBD_EP_NUM_CALC4 MAX(USBD_EP_NUM_CALC0, USBD_EP_NUM_CALC1) +#define USBD_EP_NUM_CALC5 MAX(USBD_EP_NUM_CALC2, USBD_EP_NUM_CALC3) +#define USBD_EP_NUM_CALC6 MAX(USBD_EP_NUM_CALC4, USBD_EP_NUM_CALC5) +#define USBD_EP_NUM_CALC7 MAX((USBD_BULK_ENABLE*(USBD_BULK_EP_BULKIN)), (USBD_BULK_ENABLE*(USBD_BULK_EP_BULKOUT))) +#define USBD_EP_NUM MAX(USBD_EP_NUM_CALC6, USBD_EP_NUM_CALC7) + + +#if (USBD_HID_ENABLE) +#if (USBD_MSC_ENABLE) +#if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN)))|| \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKOUT))) +#error "HID and Mass Storage Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_ADC_ENABLE) +#if ((USBD_HID_EP_INTIN == USBD_ADC_EP_ISOOUT) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_ADC_EP_ISOOUT))) +#error "HID and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (((USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKOUT))|| \ + ((USBD_HID_EP_INTOUT != 0) && \ + ((USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKOUT)))) +#error "HID and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_MSC_ENABLE) +#if (USBD_ADC_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_ADC_EP_ISOOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_ADC_EP_ISOOUT)) +#error "Mass Storage Device and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Mass Storage Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_ADC_ENABLE) +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Audio Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#define USBD_ADC_CIF_NUM (0) +#define USBD_ADC_SIF1_NUM (1) +#define USBD_ADC_SIF2_NUM (2) + + +#define USBD_ADC_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+0) +#define USBD_ADC_SIF1_STR_NUM (3+USBD_STRDESC_SER_ENABLE+1) +#define USBD_ADC_SIF2_STR_NUM (3+USBD_STRDESC_SER_ENABLE+2) +#define USBD_CDC_ACM_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+0) +#define USBD_CDC_ACM_DIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+1) +#define USBD_HID_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2) +#define USBD_WEBUSB_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) +#define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) +#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) + + +#if (USBD_HID_ENABLE) +#if (USBD_HID_HS_ENABLE) +#define USBD_HID_MAX_PACKET ((USBD_HID_HS_WMAXPACKETSIZE > USBD_HID_WMAXPACKETSIZE) ? USBD_HID_HS_WMAXPACKETSIZE : USBD_HID_WMAXPACKETSIZE) +#else +#define USBD_HID_MAX_PACKET (USBD_HID_WMAXPACKETSIZE) +#endif +#else +#define USBD_HID_MAX_PACKET (0) +#endif +#if (USBD_MSC_ENABLE) +#if (USBD_MSC_HS_ENABLE) +#define USBD_MSC_MAX_PACKET ((USBD_MSC_HS_WMAXPACKETSIZE > USBD_MSC_WMAXPACKETSIZE) ? USBD_MSC_HS_WMAXPACKETSIZE : USBD_MSC_WMAXPACKETSIZE) +#else +#define USBD_MSC_MAX_PACKET (USBD_MSC_WMAXPACKETSIZE) +#endif +#else +#define USBD_MSC_MAX_PACKET (0) +#endif +#if (USBD_ADC_ENABLE) +#if (USBD_ADC_HS_ENABLE) +#define USBD_ADC_MAX_PACKET ((USBD_ADC_HS_WMAXPACKETSIZE > USBD_ADC_WMAXPACKETSIZE) ? USBD_ADC_HS_WMAXPACKETSIZE : USBD_ADC_WMAXPACKETSIZE) +#else +#define USBD_ADC_MAX_PACKET (USBD_ADC_WMAXPACKETSIZE) +#endif +#else +#define USBD_ADC_MAX_PACKET (0) +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (USBD_CDC_ACM_HS_ENABLE) +#define USBD_CDC_ACM_MAX_PACKET ((USBD_CDC_ACM_HS_WMAXPACKETSIZE > USBD_CDC_ACM_WMAXPACKETSIZE) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE : USBD_CDC_ACM_WMAXPACKETSIZE) +#else +#define USBD_CDC_ACM_MAX_PACKET (USBD_CDC_ACM_WMAXPACKETSIZE) +#endif +#if (USBD_CDC_ACM_HS_ENABLE1) +#define USBD_CDC_ACM_MAX_PACKET1 ((USBD_CDC_ACM_HS_WMAXPACKETSIZE1 > USBD_CDC_ACM_WMAXPACKETSIZE1) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE1 : USBD_CDC_ACM_WMAXPACKETSIZE1) +#else +#define USBD_CDC_ACM_MAX_PACKET1 (USBD_CDC_ACM_WMAXPACKETSIZE1) +#endif +#else +#define USBD_CDC_ACM_MAX_PACKET (0) +#define USBD_CDC_ACM_MAX_PACKET1 (0) +#endif +#if (USBD_BULK_ENABLE) +#if (USBD_BULK_HS_ENABLE) +#define USBD_BULK_MAX_PACKET ((USBD_BULK_HS_WMAXPACKETSIZE > USBD_BULK_WMAXPACKETSIZE) ? USBD_BULK_HS_WMAXPACKETSIZE : USBD_BULK_WMAXPACKETSIZE) +#else +#define USBD_BULK_MAX_PACKET (USBD_BULK_WMAXPACKETSIZE) +#endif +#else +#define USBD_BULK_MAX_PACKET (0) +#endif + +#define USBD_MAX_PACKET_CALC0 ((USBD_HID_MAX_PACKET > USBD_HID_MAX_PACKET ) ? (USBD_HID_MAX_PACKET ) : (USBD_HID_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC1 ((USBD_ADC_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET ) ? (USBD_ADC_MAX_PACKET ) : (USBD_CDC_ACM_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC2 ((USBD_MAX_PACKET_CALC0 > USBD_MAX_PACKET_CALC1 ) ? (USBD_MAX_PACKET_CALC0) : (USBD_MAX_PACKET_CALC1 )) +#define USBD_MAX_PACKET_CALC3 ((USBD_BULK_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET1 ) ? (USBD_BULK_MAX_PACKET) : (USBD_CDC_ACM_MAX_PACKET1 )) +#define USBD_MAX_PACKET ((USBD_MAX_PACKET_CALC3 > USBD_MAX_PACKET_CALC2 ) ? (USBD_MAX_PACKET_CALC3) : (USBD_MAX_PACKET_CALC2 )) + + +/*------------------------------------------------------------------------------ + * USB Config Functions + *----------------------------------------------------------------------------*/ + +#ifndef __USB_CONFIG___ +#define __USB_CONFIG__ + +#ifndef __NO_USB_LIB_C +#include "usb_lib.c" +#endif + +#endif /* __USB_CONFIG__ */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/usbd_STM32F103.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/usbd_STM32F103.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,770 @@
+/*
+ * Copyright (c) 2004-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*----------------------------------------------------------------------------
+* RL-ARM - USB
+*----------------------------------------------------------------------------
+* Name: usbd_STM32F103.c
+* Purpose: Hardware Layer module for ST STM32F103
+* Rev.: V4.70
+*---------------------------------------------------------------------------*/
+
+/* Double Buffering is not supported */
+
+#include <rl_usb.h>
+#include "stm32f1xx.h"
+#include "usbreg.h"
+#include "IO_Config.h"
+#include "cortex_m.h"
+#include "string.h"
+
+#define __NO_USB_LIB_C
+#include "usb_config.c"
+
+#define USB_ISTR_W0C_MASK (ISTR_PMAOVR | ISTR_ERR | ISTR_WKUP | ISTR_SUSP | ISTR_RESET | ISTR_SOF | ISTR_ESOF)
+#define VAL_MASK 0xFFFF
+#define VAL_SHIFT 16
+#define EP_NUM_MASK 0xFFFF
+#define EP_NUM_SHIFT 0
+
+#define USB_DBL_BUF_EP 0x0000
+
+#define EP_BUF_ADDR (sizeof(EP_BUF_DSCR)*(USBD_EP_NUM+1)) /* Endpoint Buf Adr */
+
+EP_BUF_DSCR *pBUF_DSCR = (EP_BUF_DSCR *)USB_PMA_ADDR; /* Ptr to EP Buf Desc */
+
+U16 FreeBufAddr; /* Endpoint Free Buffer Address */
+
+uint32_t StatQueue[(USBD_EP_NUM + 1) * 2 + 1];
+uint32_t StatQueueHead = 0;
+uint32_t StatQueueTail = 0;
+uint32_t LastIstr = 0;
+
+
+inline static void stat_enque(uint32_t stat)
+{
+ cortex_int_state_t state;
+ state = cortex_int_get_and_disable();
+ StatQueue[StatQueueTail] = stat;
+ StatQueueTail = (StatQueueTail + 1) % (sizeof(StatQueue) / sizeof(StatQueue[0]));
+ cortex_int_restore(state);
+}
+
+inline static uint32_t stat_deque()
+{
+ cortex_int_state_t state;
+ uint32_t stat;
+ state = cortex_int_get_and_disable();
+ stat = StatQueue[StatQueueHead];
+ StatQueueHead = (StatQueueHead + 1) % (sizeof(StatQueue) / sizeof(StatQueue[0]));
+ cortex_int_restore(state);
+
+ return stat;
+}
+
+inline static uint32_t stat_is_empty()
+{
+ cortex_int_state_t state;
+ uint32_t empty;
+ state = cortex_int_get_and_disable();
+ empty = StatQueueHead == StatQueueTail;
+ cortex_int_restore(state);
+ return empty;
+}
+
+
+/*
+ * Reset Endpoint
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void EP_Reset(U32 EPNum)
+{
+ U32 num, val;
+ num = EPNum & 0x0F;
+ val = EPxREG(num);
+
+ if (EPNum & 0x80) { /* IN Endpoint */
+ EPxREG(num) = val & (EP_MASK | EP_DTOG_TX);
+ } else { /* OUT Endpoint */
+ EPxREG(num) = val & (EP_MASK | EP_DTOG_RX);
+ }
+}
+
+
+/*
+ * Set Endpoint Status
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * stat: New Status
+ * Return Value: None
+ */
+
+void EP_Status(U32 EPNum, U32 stat)
+{
+ U32 num, val;
+ num = EPNum & 0x0F;
+ val = EPxREG(num);
+
+ if (EPNum & 0x80) { /* IN Endpoint */
+ EPxREG(num) = EP_VAL_UNCHANGED(val) | ((val ^ stat) & EP_STAT_TX);
+ } else { /* OUT Endpoint */
+ EPxREG(num) = EP_VAL_UNCHANGED(val) | ((val ^ stat) & EP_STAT_RX);
+ }
+}
+
+
+/*
+ * USB Device Interrupt enable
+ * Called by USBD_Init to enable the USB Interrupt
+ * Return Value: None
+ */
+
+#ifdef __RTX
+void __svc(1) USBD_IntrEna(void);
+void __SVC_1(void)
+{
+#else
+void USBD_IntrEna(void)
+{
+#endif
+ NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);
+}
+
+
+/*
+ * USB Device Initialize Function
+ * Called by the User to initialize USB
+ * Return Value: None
+ */
+
+void USBD_Init(void)
+{
+ RCC->APB1ENR |= (1 << 23); /* enable clock for USB */
+ USBD_IntrEna(); /* Enable USB Interrupts */
+ /* Control USB connecting via SW */
+ USB_CONNECT_OFF();
+}
+
+
+/*
+ * USB Device Connect Function
+ * Called by the User to Connect/Disconnect USB Device
+ * Parameters: con: Connect/Disconnect
+ * Return Value: None
+ */
+
+void USBD_Connect(BOOL con)
+{
+ if (con) {
+ CNTR = CNTR_FRES; /* Force USB Reset */
+ CNTR = 0;
+ ISTR = 0; /* Clear Interrupt Status */
+ CNTR = CNTR_RESETM | CNTR_SUSPM | CNTR_WKUPM; /* USB Interrupt Mask */
+ USB_CONNECT_ON();
+ } else {
+ CNTR = CNTR_FRES | CNTR_PDWN; /* Switch Off USB Device */
+ USB_CONNECT_OFF();
+ }
+}
+
+
+/*
+ * USB Device Reset Function
+ * Called automatically on USB Device Reset
+ * Return Value: None
+ */
+
+void USBD_Reset(void)
+{
+ NVIC_DisableIRQ(USB_LP_CAN1_RX0_IRQn);
+
+ /* Double Buffering is not yet supported */
+ ISTR = 0; /* Clear Interrupt Status */
+ CNTR = CNTR_CTRM | CNTR_RESETM | CNTR_SUSPM | CNTR_WKUPM |
+#ifdef __RTX
+ ((USBD_RTX_DevTask != 0) ? CNTR_ERRM : 0) |
+ ((USBD_RTX_DevTask != 0) ? CNTR_PMAOVRM : 0) |
+ ((USBD_RTX_DevTask != 0) ? CNTR_SOFM : 0) |
+ ((USBD_RTX_DevTask != 0) ? CNTR_ESOFM : 0);
+#else
+ ((USBD_P_Error_Event != 0) ? CNTR_ERRM : 0) |
+ ((USBD_P_Error_Event != 0) ? CNTR_PMAOVRM : 0) |
+ ((USBD_P_SOF_Event != 0) ? CNTR_SOFM : 0) |
+ ((USBD_P_SOF_Event != 0) ? CNTR_ESOFM : 0);
+#endif
+ FreeBufAddr = EP_BUF_ADDR;
+ BTABLE = 0x00; /* set BTABLE Address */
+ /* Setup Control Endpoint 0 */
+ pBUF_DSCR->ADDR_TX = FreeBufAddr;
+ FreeBufAddr += USBD_MAX_PACKET0;
+ pBUF_DSCR->ADDR_RX = FreeBufAddr;
+ FreeBufAddr += USBD_MAX_PACKET0;
+
+ if (USBD_MAX_PACKET0 > 62) {
+ pBUF_DSCR->COUNT_RX = ((USBD_MAX_PACKET0 << 5) - 1) | 0x8000;
+ } else {
+ pBUF_DSCR->COUNT_RX = USBD_MAX_PACKET0 << 9;
+ }
+
+ EPxREG(0) = EP_CONTROL | EP_RX_VALID;
+ DADDR = DADDR_EF | 0; /* Enable USB Default Address */
+
+ NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);
+}
+
+
+/*
+ * USB Device Suspend Function
+ * Called automatically on USB Device Suspend
+ * Return Value: None
+ */
+
+void USBD_Suspend(void)
+{
+ CNTR |= CNTR_FSUSP; /* Force Suspend */
+ CNTR |= CNTR_LPMODE; /* Low Power Mode */
+}
+
+
+/*
+ * USB Device Resume Function
+ * Called automatically on USB Device Resume
+ * Return Value: None
+ */
+
+void USBD_Resume(void)
+{
+ /* Performed by Hardware */
+}
+
+
+/*
+ * USB Device Remote Wakeup Function
+ * Called automatically on USB Device Remote Wakeup
+ * Return Value: None
+ */
+
+void USBD_WakeUp(void)
+{
+ CNTR &= ~CNTR_FSUSP; /* Clear Suspend */
+}
+
+
+/*
+ * USB Device Remote Wakeup Configuration Function
+ * Parameters: cfg: Device Enable/Disable
+ * Return Value: None
+ */
+
+void USBD_WakeUpCfg(BOOL cfg)
+{
+ /* Not needed */
+}
+
+
+/*
+ * USB Device Set Address Function
+ * Parameters: adr: USB Device Address
+ * setup: Called in setup stage (!=0), else after status stage
+ * Return Value: None
+ */
+
+void USBD_SetAddress(U32 adr, U32 setup)
+{
+ if (setup) {
+ return;
+ }
+
+ DADDR = DADDR_EF | adr;
+}
+
+
+/*
+ * USB Device Configure Function
+ * Parameters: cfg: Device Configure/Deconfigure
+ * Return Value: None
+ */
+
+void USBD_Configure(BOOL cfg)
+{
+ if (cfg == __FALSE) {
+ FreeBufAddr = EP_BUF_ADDR;
+ FreeBufAddr += 2 * USBD_MAX_PACKET0; /* reset Buffer address */
+ }
+}
+
+
+/*
+ * Configure USB Device Endpoint according to Descriptor
+ * Parameters: pEPD: Pointer to Device Endpoint Descriptor
+ * Return Value: None
+ */
+
+void USBD_ConfigEP(USB_ENDPOINT_DESCRIPTOR *pEPD)
+{
+ /* Double Buffering is not yet supported */
+ U32 num, val;
+ num = pEPD->bEndpointAddress & 0x0F;
+ val = pEPD->wMaxPacketSize;
+
+ if (pEPD->bEndpointAddress & USB_ENDPOINT_DIRECTION_MASK) {
+ (pBUF_DSCR + num)->ADDR_TX = FreeBufAddr;
+ val = (val + 1) & ~1;
+ } else {
+ (pBUF_DSCR + num)->ADDR_RX = FreeBufAddr;
+
+ if (val > 62) {
+ val = (val + 31) & ~31;
+ (pBUF_DSCR + num)->COUNT_RX = ((val << 5) - 1) | 0x8000;
+ } else {
+ val = (val + 1) & ~1;
+ (pBUF_DSCR + num)->COUNT_RX = val << 9;
+ }
+ }
+
+ FreeBufAddr += val;
+
+ switch (pEPD->bmAttributes & USB_ENDPOINT_TYPE_MASK) {
+ case USB_ENDPOINT_TYPE_CONTROL:
+ val = EP_CONTROL;
+ break;
+
+ case USB_ENDPOINT_TYPE_ISOCHRONOUS:
+ val = EP_ISOCHRONOUS;
+ break;
+
+ case USB_ENDPOINT_TYPE_BULK:
+ val = EP_BULK;
+
+ if (USB_DBL_BUF_EP & (1 << num)) {
+ val |= EP_KIND;
+ }
+
+ break;
+
+ case USB_ENDPOINT_TYPE_INTERRUPT:
+ val = EP_INTERRUPT;
+ break;
+ }
+
+ val |= num;
+ EPxREG(num) = val;
+}
+
+
+/*
+ * Set Direction for USB Device Control Endpoint
+ * Parameters: dir: Out (dir == 0), In (dir <> 0)
+ * Return Value: None
+ */
+
+void USBD_DirCtrlEP(U32 dir)
+{
+ /* Not needed */
+}
+
+
+/*
+ * Enable USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_EnableEP(U32 EPNum)
+{
+ EP_Status(EPNum, EP_TX_NAK | EP_RX_VALID); /* EP is able to receive */
+}
+
+
+/*
+ * Disable USB Endpoint
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_DisableEP(U32 EPNum)
+{
+ EP_Status(EPNum, EP_TX_DIS | EP_RX_DIS);
+}
+
+
+/*
+ * Reset USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_ResetEP(U32 EPNum)
+{
+ EP_Reset(EPNum);
+}
+
+
+/*
+ * Set Stall for USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_SetStallEP(U32 EPNum)
+{
+ EP_Status(EPNum, EP_TX_STALL | EP_RX_STALL);
+}
+
+
+/*
+ * Clear Stall for USB Device Endpoint
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_ClrStallEP(U32 EPNum)
+{
+ EP_Reset(EPNum); /* reset DTog Bits */
+ EP_Status(EPNum, EP_TX_VALID | EP_RX_VALID);
+}
+
+
+/*
+ * Clear USB Device Endpoint Buffer
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_ClearEPBuf(U32 EPNum)
+{
+ ;
+}
+
+
+/*
+ * Read USB Device Endpoint Data
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * pData: Pointer to Data Buffer
+ * Return Value: Number of bytes read
+ */
+
+U32 USBD_ReadEP(U32 EPNum, U8 *pData, U32 bufsz)
+{
+ /* Double Buffering is not yet supported */
+ U32 num, cnt, *pv, n;
+ num = EPNum & 0x0F;
+ pv = (U32 *)(USB_PMA_ADDR + 2 * ((pBUF_DSCR + num)->ADDR_RX));
+ cnt = (pBUF_DSCR + num)->COUNT_RX & EP_COUNT_MASK;
+ if (cnt > bufsz) {
+ cnt = bufsz;
+ }
+
+ for (n = 0; n < (cnt + 1) / 2; n++) {
+ *((__packed U16 *)pData) = *pv++;
+ pData += 2;
+ }
+
+ EP_Status(EPNum, EP_RX_VALID);
+ return (cnt);
+}
+
+
+/*
+ * Write USB Device Endpoint Data
+ * Parameters: EPNum: Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * pData: Pointer to Data Buffer
+ * cnt: Number of bytes to write
+ * Return Value: Number of bytes written
+ */
+
+U32 USBD_WriteEP(U32 EPNum, U8 *pData, U32 cnt)
+{
+ /* Double Buffering is not yet supported */
+ U32 num, *pv, n;
+ U16 statusEP;
+ num = EPNum & 0x0F;
+ pv = (U32 *)(USB_PMA_ADDR + 2 * ((pBUF_DSCR + num)->ADDR_TX));
+
+ for (n = 0; n < (cnt + 1) / 2; n++) {
+ *pv++ = *((__packed U16 *)pData);
+ pData += 2;
+ }
+
+ (pBUF_DSCR + num)->COUNT_TX = cnt;
+ statusEP = EPxREG(num);
+
+ if ((statusEP & EP_STAT_TX) != EP_TX_STALL) {
+ EP_Status(EPNum, EP_TX_VALID); /* do not make EP valid if stalled */
+ }
+
+ return (cnt);
+}
+
+
+/*
+ * Get USB Device Last Frame Number
+ * Parameters: None
+ * Return Value: Frame Number
+ */
+
+U32 USBD_GetFrame(void)
+{
+ return (FNR & FNR_FN);
+}
+
+
+#ifdef __RTX
+U32 LastError; /* Last Error */
+
+/*
+ * Get USB Last Error Code
+ * Parameters: None
+ * Return Value: Error Code
+ */
+
+U32 USBD_GetError(void)
+{
+ return (LastError);
+}
+#endif
+
+
+/*
+ * USB Device Interrupt Service Routine
+ */
+
+void USB_LP_CAN1_RX0_IRQHandler(void)
+{
+ uint32_t istr;
+ uint32_t num;
+ uint32_t val;
+
+ istr = ISTR;
+ // Zero out endpoint ID since this is read from the queue
+ LastIstr |= istr & ~(ISTR_DIR | ISTR_EP_ID);
+ // Clear interrupts that are pending
+ ISTR = ~(istr & USB_ISTR_W0C_MASK);
+ if (istr & ISTR_CTR) {
+ while ((istr = ISTR) & ISTR_CTR) {
+ num = istr & ISTR_EP_ID;
+ val = EPxREG(num);
+
+ // Process and filter out the zero length status out endpoint to prevent
+ // the next SETUP packet from being dropped.
+ if ((0 == num) && (val & EP_CTR_RX) && !(val & EP_SETUP)
+ && (0 == ((pBUF_DSCR + num)->COUNT_RX & EP_COUNT_MASK))) {
+ if (val & EP_CTR_TX) {
+ // Drop the RX event but not TX
+ stat_enque((((val & VAL_MASK) & ~EP_CTR_RX) << VAL_SHIFT) |
+ ((num & EP_NUM_MASK) << EP_NUM_SHIFT));
+ } else {
+ // Drop the event
+ }
+ } else {
+ stat_enque(((val & VAL_MASK) << VAL_SHIFT) |
+ ((num & EP_NUM_MASK) << EP_NUM_SHIFT));
+ }
+
+
+ if (val & EP_CTR_RX) {
+ EPxREG(num) = EP_VAL_UNCHANGED(val) & ~EP_CTR_RX;
+ }
+
+ if (val & EP_CTR_TX) {
+ EPxREG(num) = EP_VAL_UNCHANGED(val) & ~EP_CTR_TX;
+ }
+ }
+ }
+
+ USBD_SignalHandler();
+}
+
+void USBD_Handler(void)
+{
+ U32 istr, num, val, num_val;
+ cortex_int_state_t state;
+
+ // Get ISTR
+ state = cortex_int_get_and_disable();
+ istr = LastIstr;
+ LastIstr = 0;
+ cortex_int_restore(state);
+
+ /* USB Reset Request */
+ if (istr & ISTR_RESET) {
+ USBD_Reset();
+ usbd_reset_core();
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_RESET, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Reset_Event) {
+ USBD_P_Reset_Event();
+ }
+
+#endif
+ }
+
+ /* USB Suspend Request */
+ if (istr & ISTR_SUSP) {
+ USBD_Suspend();
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_SUSPEND, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Suspend_Event) {
+ USBD_P_Suspend_Event();
+ }
+
+#endif
+ }
+
+ /* USB Wakeup */
+ if (istr & ISTR_WKUP) {
+ USBD_WakeUp();
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_RESUME, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Resume_Event) {
+ USBD_P_Resume_Event();
+ }
+
+#endif
+ }
+
+ /* Start of Frame */
+ if (istr & ISTR_SOF) {
+#ifdef __RTX
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_SOF, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_SOF_Event) {
+ USBD_P_SOF_Event();
+ }
+
+#endif
+ }
+
+ /* PMA Over/underrun */
+ if (istr & ISTR_PMAOVR) {
+#ifdef __RTX
+ LastError = 2;
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_ERROR, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Error_Event) {
+ USBD_P_Error_Event(2);
+ }
+
+#endif
+ }
+
+ /* Error: No Answer, CRC Error, Bit Stuff Error, Frame Format Error */
+ if (istr & ISTR_ERR) {
+#ifdef __RTX
+ LastError = 1;
+
+ if (USBD_RTX_DevTask) {
+ isr_evt_set(USBD_EVT_ERROR, USBD_RTX_DevTask);
+ }
+
+#else
+
+ if (USBD_P_Error_Event) {
+ USBD_P_Error_Event(1);
+ }
+
+#endif
+ }
+
+ /* Endpoint Interrupts */
+ while ((istr & ISTR_CTR) && !stat_is_empty()) {
+ num_val = stat_deque();
+ num = (num_val >> EP_NUM_SHIFT) & EP_NUM_MASK;
+ val = (num_val >> VAL_SHIFT) & VAL_MASK;
+ if (val & EP_CTR_TX) {
+#ifdef __RTX
+
+ if (USBD_RTX_EPTask[num]) {
+ isr_evt_set(USBD_EVT_IN, USBD_RTX_EPTask[num]);
+ }
+
+#else
+
+ if (USBD_P_EP[num]) {
+ USBD_P_EP[num](USBD_EVT_IN);
+ }
+
+#endif
+ }
+
+ if (val & EP_CTR_RX) {
+#ifdef __RTX
+
+ if (USBD_RTX_EPTask[num]) {
+ isr_evt_set((val & EP_SETUP) ? USBD_EVT_SETUP : USBD_EVT_OUT, USBD_RTX_EPTask[num]);
+ }
+
+#else
+
+ if (USBD_P_EP[num]) {
+ USBD_P_EP[num]((val & EP_SETUP) ? USBD_EVT_SETUP : USBD_EVT_OUT);
+ }
+
+#endif
+ }
+ }
+}
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/stm32/stm32f103xb/usbreg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/stm32/stm32f103xb/usbreg.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2004-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*----------------------------------------------------------------------------
+ * RL-ARM - USB
+ *----------------------------------------------------------------------------
+ * Name: usbreg.h
+ * Purpose: Hardware Layer Definitions for ST STM32F10x
+ *---------------------------------------------------------------------------*/
+
+#ifndef __USBREG_H
+#define __USBREG_H
+
+
+#define REG(x) (*((volatile unsigned int *)(x)))
+
+#define USB_BASE_ADDR 0x40005C00 /* USB Registers Base Address */
+#define USB_PMA_ADDR 0x40006000 /* USB Packet Memory Area Address */
+
+
+/* Common Registers */
+#define CNTR REG(USB_BASE_ADDR + 0x40) /* Control Register */
+#define ISTR REG(USB_BASE_ADDR + 0x44) /* Interrupt Status Register */
+#define FNR REG(USB_BASE_ADDR + 0x48) /* Frame Number Register */
+#define DADDR REG(USB_BASE_ADDR + 0x4C) /* Device Address Register */
+#define BTABLE REG(USB_BASE_ADDR + 0x50) /* Buffer Table Address Register */
+
+/* CNTR: Control Register Bit Definitions */
+#define CNTR_CTRM 0x8000 /* Correct Transfer Interrupt Mask */
+#define CNTR_PMAOVRM 0x4000 /* Packet Memory Aerea Over/underrun Interrupt Mask */
+#define CNTR_ERRM 0x2000 /* Error Interrupt Mask */
+#define CNTR_WKUPM 0x1000 /* Wake-up Interrupt Mask */
+#define CNTR_SUSPM 0x0800 /* Suspend Mode Interrupt Mask */
+#define CNTR_RESETM 0x0400 /* USB Reset Interrupt Mask */
+#define CNTR_SOFM 0x0200 /* Start of Frame Interrupt Mask */
+#define CNTR_ESOFM 0x0100 /* Expected Start of Frame Interrupt Mask */
+#define CNTR_RESUME 0x0010 /* Resume Request */
+#define CNTR_FSUSP 0x0008 /* Force Suspend */
+#define CNTR_LPMODE 0x0004 /* Low-power Mode */
+#define CNTR_PDWN 0x0002 /* Power Down */
+#define CNTR_FRES 0x0001 /* Force USB Reset */
+
+/* ISTR: Interrupt Status Register Bit Definitions */
+#define ISTR_CTR 0x8000 /* Correct Transfer */
+#define ISTR_PMAOVR 0x4000 /* Packet Memory Aerea Over/underrun */
+#define ISTR_ERR 0x2000 /* Error */
+#define ISTR_WKUP 0x1000 /* Wake-up */
+#define ISTR_SUSP 0x0800 /* Suspend Mode */
+#define ISTR_RESET 0x0400 /* USB Reset */
+#define ISTR_SOF 0x0200 /* Start of Frame */
+#define ISTR_ESOF 0x0100 /* Expected Start of Frame */
+#define ISTR_DIR 0x0010 /* Direction of Transaction */
+#define ISTR_EP_ID 0x000F /* EndPoint Identifier */
+
+/* FNR: Frame Number Register Bit Definitions */
+#define FNR_RXDP 0x8000 /* D+ Data Line Status */
+#define FNR_RXDM 0x4000 /* D- Data Line Status */
+#define FNR_LCK 0x2000 /* Locked */
+#define FNR_LSOF 0x1800 /* Lost SOF */
+#define FNR_FN 0x07FF /* Frame Number */
+
+/* DADDR: Device Address Register Bit Definitions */
+#define DADDR_EF 0x0080 /* Enable Function */
+#define DADDR_ADD 0x007F /* Device Address */
+
+
+/* EndPoint Registers */
+#define EPxREG(x) REG(USB_BASE_ADDR + 4*(x))
+
+/* EPxREG: EndPoint Registers Bit Definitions */
+#define EP_CTR_RX 0x8000 /* Correct RX Transfer */
+#define EP_DTOG_RX 0x4000 /* RX Data Toggle */
+#define EP_STAT_RX 0x3000 /* RX Status */
+#define EP_SETUP 0x0800 /* EndPoint Setup */
+#define EP_TYPE 0x0600 /* EndPoint Type */
+#define EP_KIND 0x0100 /* EndPoint Kind */
+#define EP_CTR_TX 0x0080 /* Correct TX Transfer */
+#define EP_DTOG_TX 0x0040 /* TX Data Toggle */
+#define EP_STAT_TX 0x0030 /* TX Status */
+#define EP_EA 0x000F /* EndPoint Address */
+
+/* EndPoint Register Mask (No Toggle Fields) */
+#define EP_MASK (EP_CTR_RX|EP_SETUP|EP_TYPE|EP_KIND|EP_CTR_TX|EP_EA)
+/* EndPoint Register Mask (Write zero to clear) */
+#define EP_MASK_RC_W0 (EP_CTR_RX|EP_CTR_TX)
+/* Mask off all toggle bits and set write zero to clear bits to 1. */
+/* This creates a value that can be written back to the EndPoint register */
+/* which does not change any status bits. */
+#define EP_VAL_UNCHANGED(val) (((val) & EP_MASK) | EP_MASK_RC_W0)
+
+/* EP_TYPE: EndPoint Types */
+#define EP_BULK 0x0000 /* BULK EndPoint */
+#define EP_CONTROL 0x0200 /* CONTROL EndPoint */
+#define EP_ISOCHRONOUS 0x0400 /* ISOCHRONOUS EndPoint */
+#define EP_INTERRUPT 0x0600 /* INTERRUPT EndPoint */
+
+/* EP_KIND: EndPoint Kind */
+#define EP_DBL_BUF EP_KIND /* Double Buffer for Bulk Endpoint */
+#define EP_STATUS_OUT EP_KIND /* Status Out for Control Endpoint */
+
+/* EP_STAT_TX: TX Status */
+#define EP_TX_DIS 0x0000 /* Disabled */
+#define EP_TX_STALL 0x0010 /* Stalled */
+#define EP_TX_NAK 0x0020 /* NAKed */
+#define EP_TX_VALID 0x0030 /* Valid */
+
+/* EP_STAT_RX: RX Status */
+#define EP_RX_DIS 0x0000 /* Disabled */
+#define EP_RX_STALL 0x1000 /* Stalled */
+#define EP_RX_NAK 0x2000 /* NAKed */
+#define EP_RX_VALID 0x3000 /* Valid */
+
+
+/* Endpoint Buffer Descriptor */
+typedef struct _EP_BUF_DSCR {
+ U32 ADDR_TX;
+ U32 COUNT_TX;
+ U32 ADDR_RX;
+ U32 COUNT_RX;
+} EP_BUF_DSCR;
+
+#define EP_ADDR_MASK 0xFFFE /* Address Mask */
+#define EP_COUNT_MASK 0x03FF /* Count Mask */
+
+
+#endif /* __USBREG_H */
diff -r 000000000000 -r 01f31e923fe2 source/hic_hal/uart.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/uart.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,94 @@
+/**
+ * @file uart.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef UART_H
+#define UART_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Parity enumerator */
+typedef enum {
+ UART_PARITY_NONE = 0,
+ UART_PARITY_ODD = 1,
+ UART_PARITY_EVEN = 2,
+ UART_PARITY_MARK = 3,
+ UART_PARITY_SPACE = 4
+} UART_Parity;
+
+/* Stop Bits enumerator */
+typedef enum {
+ UART_STOP_BITS_1 = 0,
+ UART_STOP_BITS_1_5 = 1,
+ UART_STOP_BITS_2 = 2
+} UART_StopBits;
+
+/* Data Bits enumerator */
+typedef enum {
+ UART_DATA_BITS_5 = 5,
+ UART_DATA_BITS_6 = 6,
+ UART_DATA_BITS_7 = 7,
+ UART_DATA_BITS_8 = 8,
+ UART_DATA_BITS_16 = 16
+} UART_DataBits;
+
+/* Flow control enumerator */
+typedef enum {
+ UART_FLOW_CONTROL_NONE = 0,
+ UART_FLOW_CONTROL_RTS_CTS = 1,
+ UART_FLOW_CONTROL_XON_XOFF = 2
+} UART_FlowControl;
+
+/* UART Port Properties structure */
+typedef struct {
+ uint32_t Baudrate;
+ UART_DataBits DataBits;
+ UART_Parity Parity;
+ UART_StopBits StopBits;
+ UART_FlowControl FlowControl;
+} UART_Configuration;
+
+/*-----------------------------------------------------------------------------
+ * FUNCTION PROTOTYPES
+ *----------------------------------------------------------------------------*/
+
+/* UART driver function prototypes */
+extern int32_t uart_initialize(void);
+extern int32_t uart_uninitialize(void);
+extern int32_t uart_reset(void);
+extern int32_t uart_set_configuration(UART_Configuration *config);
+extern int32_t uart_get_configuration(UART_Configuration *config);
+extern int32_t uart_write_free(void);
+extern int32_t uart_write_data(uint8_t *data, uint16_t size);
+extern int32_t uart_read_data(uint8_t *data, uint16_t size);
+extern void uart_set_control_line_state(uint16_t ctrl_bmp);
+extern void uart_software_flow_control(void);
+extern void uart_enable_flow_control(bool enabled);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/rtos/RTL.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/rtos/RTL.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,671 @@
+/**
+ * @file RTL.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __RTL_H__
+#define __RTL_H__
+
+/* RL-ARM version number. */
+#define __RL_ARM_VER 471
+
+#define __task __declspec(noreturn)
+#define __used __attribute__((used))
+
+#ifndef NULL
+ #ifdef __cplusplus
+ #define NULL 0
+ #else
+ #define NULL ((void *) 0)
+ #endif
+#endif
+
+#ifndef EOF
+ #define EOF (-1)
+#endif
+
+#ifndef __size_t
+ #define __size_t 1
+ typedef unsigned int size_t;
+#endif
+
+typedef signed char S8;
+typedef unsigned char U8;
+typedef short S16;
+typedef unsigned short U16;
+typedef int S32;
+typedef unsigned int U32;
+typedef long long S64;
+typedef unsigned long long U64;
+typedef unsigned char BIT;
+typedef unsigned int BOOL;
+
+#ifndef __TRUE
+ #define __TRUE 1
+#endif
+#ifndef __FALSE
+ #define __FALSE 0
+#endif
+
+#ifdef __BIG_ENDIAN
+ #define U32_LE(v) (U32)(__rev(v))
+ #define U16_LE(v) (U16)(__rev(v) >> 16)
+ #define U32_BE(v) (U32)(v)
+ #define U16_BE(v) (U16)(v)
+#else
+ #define U32_BE(v) (U32)(__rev(v))
+ #define U16_BE(v) (U16)(__rev(v) >> 16)
+ #define U32_LE(v) (U32)(v)
+ #define U16_LE(v) (U16)(v)
+#endif
+#define ntohs(v) U16_BE(v)
+#define ntohl(v) U32_BE(v)
+#define htons(v) ntohs(v)
+#define htonl(v) ntohl(v)
+
+/*----------------------------------------------------------------------------
+ * RTX Kernel API
+ *---------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Definition of Semaphore type */
+typedef U32 OS_SEM[2];
+
+/* Definition of Mailbox type */
+#define os_mbx_declare(name,cnt) U32 name [4 + cnt]
+typedef U32 OS_MBX[];
+
+/* Definition of Mutex type */
+typedef U32 OS_MUT[3];
+
+/* Task Identification number. */
+typedef U32 OS_TID;
+
+/* Function return of system calls returning an object identification */
+typedef void *OS_ID;
+
+/* Function return of system calls indicating an event or completion state */
+typedef U32 OS_RESULT;
+
+/* Return codes */
+#define OS_R_TMO 0x01
+#define OS_R_EVT 0x02
+#define OS_R_SEM 0x03
+#define OS_R_MBX 0x04
+#define OS_R_MUT 0x05
+
+#define OS_R_OK 0x00
+#define OS_R_NOK 0xff
+
+#define OS_TCB_SIZE 48
+#define OS_TMR_SIZE 8
+
+/* Error Codes */
+#define OS_ERR_STK_OVF 1
+#define OS_ERR_FIFO_OVF 2
+#define OS_ERR_MBX_OVF 3
+
+#if !(__TARGET_ARCH_6S_M || __TARGET_ARCH_7_M || __TARGET_ARCH_7E_M)
+
+/*----------------------------------------------------------------------------
+ * Functions ARM
+ *---------------------------------------------------------------------------*/
+
+/* Task Management */
+#define os_sys_init(tsk) os_sys_init0(tsk,0,NULL)
+#define os_sys_init_prio(tsk,prio) os_sys_init0(tsk,prio,NULL)
+#define os_sys_init_user(tsk,prio,stk,size) \
+ os_sys_init0(tsk,prio|(size<<8),stk)
+#define os_tsk_create(tsk,prio) os_tsk_create0(tsk,prio,NULL,NULL)
+#define os_tsk_create_user(tsk,prio,stk,size) \
+ os_tsk_create0(tsk,prio|(size<<8),stk,NULL)
+#define os_tsk_create_ex(tsk,prio,argv) os_tsk_create_ex0(tsk,prio,NULL,argv)
+#define os_tsk_create_user_ex(tsk,prio,stk,size,argv) \
+ os_tsk_create_ex0(tsk,prio|(size<<8),stk,argv)
+#define os_tsk_delete_self() os_tsk_delete(0)
+#define os_tsk_prio_self(prio) os_tsk_prio(0,prio)
+#define isr_tsk_get() os_tsk_self()
+
+extern void os_sys_init0 (void (*task)(void), U32 prio_stksz, void *stk);
+extern OS_TID os_tsk_create0 (void (*task)(void), U32 prio_stksz,
+ void *stk, void *argv);
+extern OS_TID os_tsk_create_ex0 (void (*task)(void *), U32 prio_stksz,
+ void *stk, void *argv);
+extern OS_TID os_tsk_self (void);
+extern void os_tsk_pass (void);
+extern OS_RESULT os_tsk_prio (OS_TID task_id, U8 new_prio);
+extern OS_RESULT os_tsk_delete (OS_TID task_id);
+
+/* Event flag Management */
+#define os_evt_wait_or(wflags,tmo) os_evt_wait(wflags,tmo,__FALSE)
+#define os_evt_wait_and(wflags,tmo) os_evt_wait(wflags,tmo,__TRUE)
+
+extern OS_RESULT os_evt_wait (U16 wait_flags, U16 timeout, BOOL and_wait);
+extern void os_evt_set (U16 event_flags, OS_TID task_id);
+extern void os_evt_clr (U16 clear_flags, OS_TID task_id);
+extern void isr_evt_set (U16 event_flags, OS_TID task_id);
+extern U16 os_evt_get (void);
+
+/* Semaphore Management */
+extern void os_sem_init (OS_ID semaphore, U16 token_count);
+extern OS_RESULT os_sem_send (OS_ID semaphore);
+extern OS_RESULT os_sem_wait (OS_ID semaphore, U16 timeout);
+extern void isr_sem_send (OS_ID semaphore);
+
+/* Mailbox Management */
+#define isr_mbx_check(mbx) os_mbx_check(mbx)
+
+extern void os_mbx_init (OS_ID mailbox, U16 mbx_size);
+extern OS_RESULT os_mbx_send (OS_ID mailbox, void *message_ptr, U16 timeout);
+extern OS_RESULT os_mbx_wait (OS_ID mailbox, void **message, U16 timeout);
+extern OS_RESULT os_mbx_check (OS_ID mailbox);
+extern void isr_mbx_send (OS_ID mailbox, void *message_ptr);
+extern OS_RESULT isr_mbx_receive (OS_ID mailbox, void **message);
+
+/* Mutex Management */
+extern void os_mut_init (OS_ID mutex);
+extern OS_RESULT os_mut_release (OS_ID mutex);
+extern OS_RESULT os_mut_wait (OS_ID mutex, U16 timeout);
+
+/* Time Management */
+extern U32 os_time_get (void);
+extern void os_dly_wait (U16 delay_time);
+extern void os_itv_set (U16 interval_time);
+extern void os_itv_wait (void);
+
+/* User Timer Management */
+extern OS_ID os_tmr_create (U16 tcnt, U16 info);
+extern OS_ID os_tmr_kill (OS_ID timer);
+
+/* System Functions */
+extern U32 os_suspend (void);
+extern void os_resume (U32 sleep_time);
+extern void tsk_lock (void) __swi (5);
+extern void tsk_unlock (void);
+
+/* Fixed Memory Block Management Functions */
+extern int _init_box (void *box_mem, U32 box_size, U32 blk_size);
+extern void *_alloc_box (void *box_mem) __swi (1);
+extern void *_calloc_box (void *box_mem);
+extern int _free_box (void *box_mem, void *box) __swi (2);
+
+#else
+
+/*----------------------------------------------------------------------------
+ * Functions Cortex-M
+ *---------------------------------------------------------------------------*/
+
+#define __SVC_0 __svc_indirect(0)
+
+/* Task Management */
+extern void os_set_env (void);
+extern void rt_sys_init (void (*task)(void), U8 priority, void *stk);
+extern void rt_tsk_pass (void);
+extern OS_TID rt_tsk_self (void);
+extern OS_RESULT rt_tsk_prio (OS_TID task_id, U8 new_prio);
+extern OS_TID rt_tsk_create (void (*task)(void), U8 priority, void *stk, void *argv);
+extern OS_RESULT rt_tsk_delete (OS_TID task_id);
+
+#define os_sys_init(tsk) os_set_env(); \
+ _os_sys_init((U32)rt_sys_init,tsk,0,NULL)
+#define os_sys_init_user(tsk,prio,stk,size) \
+ os_set_env(); \
+ _os_sys_init((U32)rt_sys_init,tsk,prio|(size<<8),stk)
+#define os_sys_init_prio(tsk,prio) os_set_env(); \
+ _os_sys_init((U32)rt_sys_init,tsk,prio,NULL)
+#define os_tsk_create(tsk,prio) _os_tsk_create((U32)rt_tsk_create,tsk,prio,NULL,NULL)
+#define os_tsk_create_user(tsk,prio,stk,size) \
+ _os_tsk_create((U32)rt_tsk_create,tsk,prio|(size<<8),stk,NULL)
+#define os_tsk_create_ex(tsk,prio,argv) _os_tsk_create_ex((U32)rt_tsk_create,tsk,prio,NULL,argv)
+#define os_tsk_create_user_ex(tsk,prio,stk,size,argv) \
+ _os_tsk_create_ex((U32)rt_tsk_create,tsk,prio|(size<<8),stk,argv)
+#define os_tsk_self() _os_tsk_self((U32)rt_tsk_self)
+#define os_tsk_pass() _os_tsk_pass((U32)rt_tsk_pass)
+#define os_tsk_prio(task_id,new_prio) _os_tsk_prio((U32)rt_tsk_prio,task_id,new_prio)
+#define os_tsk_prio_self(prio) _os_tsk_prio((U32)rt_tsk_prio,0,prio)
+#define os_tsk_delete(task_id) _os_tsk_delete((U32)rt_tsk_delete,task_id)
+#define os_tsk_delete_self() _os_tsk_delete((U32)rt_tsk_delete, 0)
+#define isr_tsk_get() rt_tsk_self()
+
+extern void _os_sys_init(U32 p, void (*task)(void), U32 prio_stksz,
+ void *stk) __SVC_0;
+extern OS_TID _os_tsk_create (U32 p, void (*task)(void), U32 prio_stksz,
+ void *stk, void *argv) __SVC_0;
+extern OS_TID _os_tsk_create_ex (U32 p, void (*task)(void *), U32 prio_stksz,
+ void *stk, void *argv) __SVC_0;
+extern OS_TID _os_tsk_self (U32 p) __SVC_0;
+extern void _os_tsk_pass (U32 p) __SVC_0;
+extern OS_RESULT _os_tsk_prio (U32 p, OS_TID task_id, U8 new_prio) __SVC_0;
+extern OS_RESULT _os_tsk_delete (U32 p, OS_TID task_id) __SVC_0;
+
+/* Event flag Management */
+extern OS_RESULT rt_evt_wait (U16 wait_flags, U16 timeout, BOOL and_wait);
+extern void rt_evt_set (U16 event_flags, OS_TID task_id);
+extern void rt_evt_clr (U16 clear_flags, OS_TID task_id);
+extern U16 rt_evt_get (void);
+
+#define os_evt_wait_or(wflags,tmo) _os_evt_wait((U32)rt_evt_wait,wflags,tmo,__FALSE)
+#define os_evt_wait_and(wflags,tmo) _os_evt_wait((U32)rt_evt_wait,wflags,tmo,__TRUE)
+#define os_evt_set(evt_flags,task_id) _os_evt_set((U32)rt_evt_set,evt_flags,task_id)
+#define os_evt_clr(clr_flags,task_id) _os_evt_clr((U32)rt_evt_clr,clr_flags,task_id)
+#define os_evt_get() _os_evt_get((U32)rt_evt_get)
+
+extern OS_RESULT _os_evt_wait(U32 p, U16 wait_flags, U16 timeout,
+ BOOL and_wait) __SVC_0;
+extern void _os_evt_set (U32 p, U16 event_flags, OS_TID task_id) __SVC_0;
+extern void _os_evt_clr (U32 p, U16 clear_flags, OS_TID task_id) __SVC_0;
+extern U16 _os_evt_get (U32 p) __SVC_0;
+extern void isr_evt_set (U16 event_flags, OS_TID task_id);
+
+/* Semaphore Management */
+extern void rt_sem_init (OS_ID semaphore, U16 token_count);
+extern OS_RESULT rt_sem_send (OS_ID semaphore);
+extern OS_RESULT rt_sem_wait (OS_ID semaphore, U16 timeout);
+
+#define os_sem_init(sem,t_count) _os_sem_init((U32)rt_sem_init,sem,t_count)
+#define os_sem_send(sem) _os_sem_send((U32)rt_sem_send,sem)
+#define os_sem_wait(sem,tmo) _os_sem_wait((U32)rt_sem_wait,sem,tmo)
+
+extern void _os_sem_init (U32 p, OS_ID semaphore,
+ U16 token_count) __SVC_0;
+extern OS_RESULT _os_sem_send (U32 p, OS_ID semaphore) __SVC_0;
+extern OS_RESULT _os_sem_wait (U32 p, OS_ID semaphore, U16 timeout) __SVC_0;
+extern void isr_sem_send (OS_ID semaphore);
+
+/* Mailbox Management */
+extern void rt_mbx_init (OS_ID mailbox, U16 mbx_size);
+extern OS_RESULT rt_mbx_send (OS_ID mailbox, void *p_msg, U16 timeout);
+extern OS_RESULT rt_mbx_wait (OS_ID mailbox, void **message, U16 timeout);
+extern OS_RESULT rt_mbx_check (OS_ID mailbox);
+
+#define os_mbx_init(mbx,mbx_size) _os_mbx_init((U32)rt_mbx_init,mbx,mbx_size)
+#define os_mbx_send(mbx,p_msg,tmo) _os_mbx_send((U32)rt_mbx_send,mbx,p_msg,tmo)
+#define os_mbx_wait(mbx,message,tmo) _os_mbx_wait((U32)rt_mbx_wait,mbx,message,tmo)
+#define os_mbx_check(mbx) _os_mbx_check((U32)rt_mbx_check,mbx)
+#define isr_mbx_check(mbx) rt_mbx_check(mbx)
+
+extern void _os_mbx_init (U32 p, OS_ID mailbox, U16 mbx_size) __SVC_0;
+extern OS_RESULT _os_mbx_send (U32 p, OS_ID mailbox, void *message_ptr,
+ U16 timeout) __SVC_0;
+extern OS_RESULT _os_mbx_wait (U32 p, OS_ID mailbox, void **message,
+ U16 timeout) __SVC_0;
+extern OS_RESULT _os_mbx_check (U32 p, OS_ID mailbox) __SVC_0;
+extern void isr_mbx_send (OS_ID mailbox, void *message_ptr);
+extern OS_RESULT isr_mbx_receive (OS_ID mailbox, void **message);
+
+/* Mutex Management */
+extern void rt_mut_init (OS_ID mutex);
+extern OS_RESULT rt_mut_release (OS_ID mutex);
+extern OS_RESULT rt_mut_wait (OS_ID mutex, U16 timeout);
+
+#define os_mut_init(mutex) _os_mut_init((U32)rt_mut_init,mutex)
+#define os_mut_release(mutex) _os_mut_release((U32)rt_mut_release,mutex)
+#define os_mut_wait(mutex,timeout) _os_mut_wait((U32)rt_mut_wait,mutex,timeout)
+
+extern void _os_mut_init (U32 p, OS_ID mutex) __SVC_0;
+extern OS_RESULT _os_mut_release (U32 p, OS_ID mutex) __SVC_0;
+extern OS_RESULT _os_mut_wait (U32 p, OS_ID mutex, U16 timeout) __SVC_0;
+
+/* Time Management */
+extern U32 rt_time_get (void);
+extern void rt_dly_wait (U16 delay_time);
+extern void rt_itv_set (U16 interval_time);
+extern void rt_itv_wait (void);
+
+#define os_time_get() _os_time_get((U32)rt_time_get)
+#define os_dly_wait(delay_time) _os_dly_wait((U32)rt_dly_wait,delay_time)
+#define os_itv_set(interval_time) _os_itv_set((U32)rt_itv_set,interval_time)
+#define os_itv_wait() _os_itv_wait((U32)rt_itv_wait)
+
+extern U32 _os_time_get (U32 p) __SVC_0;
+extern void _os_dly_wait (U32 p, U16 delay_time) __SVC_0;
+extern void _os_itv_set (U32 p, U16 interval_time) __SVC_0;
+extern void _os_itv_wait (U32 p) __SVC_0;
+
+/* User Timer Management */
+extern OS_ID rt_tmr_create (U16 tcnt, U16 info);
+extern OS_ID rt_tmr_kill (OS_ID timer);
+
+#define os_tmr_create(tcnt,info) _os_tmr_create((U32)rt_tmr_create,tcnt,info)
+#define os_tmr_kill(timer) _os_tmr_kill((U32)rt_tmr_kill,timer)
+
+extern OS_ID _os_tmr_create (U32 p, U16 tcnt, U16 info) __SVC_0;
+extern OS_ID _os_tmr_kill (U32 p, OS_ID timer) __SVC_0;
+
+/* System Functions */
+extern U32 rt_suspend (void);
+extern void rt_resume (U32 sleep_time);
+extern void rt_tsk_lock (void);
+extern void rt_tsk_unlock (void);
+
+#define os_suspend() _os_suspend((U32)rt_suspend)
+#define os_resume(sleep_time) _os_resume((U32)rt_resume,sleep_time)
+#define tsk_lock() _os_tsk_lock((U32)rt_tsk_lock)
+#define tsk_unlock() _os_tsk_unlock((U32)rt_tsk_unlock)
+
+extern U32 _os_suspend (U32 p) __SVC_0;
+extern void _os_resume (U32 p, U32 sleep_time) __SVC_0;
+extern void _os_tsk_lock (U32 p) __SVC_0;
+extern void _os_tsk_unlock (U32 p) __SVC_0;
+
+/* Fixed Memory Block Management Functions */
+extern int _init_box (void *box_mem, U32 box_size, U32 blk_size);
+extern void *_alloc_box (void *box_mem);
+extern void *_calloc_box (void *box_mem);
+extern int _free_box (void *box_mem, void *box);
+
+#endif
+
+#define BOX_ALIGN_8 0x80000000
+#define _declare_box(pool,size,cnt) U32 pool[(((size)+3)/4)*(cnt) + 3]
+#define _declare_box8(pool,size,cnt) U64 pool[(((size)+7)/8)*(cnt) + 2]
+#define _init_box8(pool,size,bsize) _init_box (pool,size,bsize | BOX_ALIGN_8)
+
+/* For compatibility with older configurations.*/
+#define os_stk_overflow os_error
+
+/*----------------------------------------------------------------------------
+ * Flash File System API
+ *---------------------------------------------------------------------------*/
+
+typedef struct { /* RL Time format (FFS, TCPnet) */
+ U8 hr; /* Hours [0..23] */
+ U8 min; /* Minutes [0..59] */
+ U8 sec; /* Seconds [0..59] */
+ U8 day; /* Day [1..31] */
+ U8 mon; /* Month [1..12] */
+ U16 year; /* Year [1980..2107] */
+} RL_TIME;
+
+typedef struct { /* Search info record */
+ S8 name[256]; /* Name */
+ U32 size; /* File size in bytes */
+ U16 fileID; /* System Identification */
+ U8 attrib; /* Attributes */
+ RL_TIME time; /* Create/Modify Time */
+} FINFO;
+
+extern int finit (const char *drive);
+extern int funinit (const char *drive);
+extern int fdelete (const char *filename);
+extern int frename (const char *oldname, const char *newname);
+extern int ffind (const char *pattern, FINFO *info);
+extern U64 ffree (const char *drive);
+extern int fformat (const char *drive);
+extern int fanalyse (const char *drive);
+extern int fcheck (const char *drive);
+extern int fdefrag (const char *drive);
+extern int fattrib (const char *par, const char *path);
+extern int fvol (const char *drive, char *buf);
+
+/* The following macros provide for common functions */
+#define unlink(fn) fdelete(fn);
+
+/*----------------------------------------------------------------------------
+ * TCPnet API
+ *---------------------------------------------------------------------------*/
+
+/* UDP Options */
+#define UDP_OPT_SEND_CS 0x01 /* Calculate Checksum for UDP send frames */
+#define UDP_OPT_CHK_CS 0x02 /* Verify Checksum for received UDP frames */
+
+/* TCP Socket Types */
+#define TCP_TYPE_SERVER 0x01 /* Socket Type Server (open for listening) */
+#define TCP_TYPE_CLIENT 0x02 /* Socket Type Client (initiate connect) */
+#define TCP_TYPE_DELAY_ACK 0x04 /* Socket Type Delayed Acknowledge */
+#define TCP_TYPE_FLOW_CTRL 0x08 /* Socket Type Flow Control */
+#define TCP_TYPE_KEEP_ALIVE 0x10 /* Socket Type Keep Alive */
+#define TCP_TYPE_CLIENT_SERVER (TCP_TYPE_SERVER | TCP_TYPE_CLIENT)
+
+/* TCP Callback Events */
+#define TCP_EVT_CONREQ 0 /* Connect request received event */
+#define TCP_EVT_CONNECT 1 /* Connection established event */
+#define TCP_EVT_CLOSE 2 /* Connection was properly closed */
+#define TCP_EVT_ABORT 3 /* Connection is for some reason aborted */
+#define TCP_EVT_ACK 4 /* Previously send data acknowledged */
+#define TCP_EVT_DATA 5 /* Data received event */
+
+/* TCP States */
+#define TCP_STATE_FREE 0 /* Entry is free and unused */
+#define TCP_STATE_CLOSED 1 /* Entry allocated, socket still closed */
+#define TCP_STATE_LISTEN 2 /* Socket waiting for incoming connection */
+#define TCP_STATE_SYN_REC 3 /* SYN frame received */
+#define TCP_STATE_SYN_SENT 4 /* SYN packet sent to establish a connect. */
+#define TCP_STATE_FINW1 5 /* Tcp_close started FIN packet was sent */
+#define TCP_STATE_FINW2 6 /* Our FIN ack-ed, waiting for remote FIN */
+#define TCP_STATE_CLOSING 7 /* Received FIN independently of our FIN */
+#define TCP_STATE_LAST_ACK 8 /* Waiting for last ACK for our FIN */
+#define TCP_STATE_TWAIT 9 /* Timed waiting for 2MSL */
+#define TCP_STATE_CONNECT 10 /* TCP Connection established */
+
+/* BSD Socket Address Family */
+#define AF_UNSPEC 0 /* Unspecified */
+#define AF_INET 1 /* Internet Address Family (UDP, TCP) */
+#define AF_NETBIOS 2 /* NetBios-style addresses */
+
+/* BSD Protocol families, same as address families */
+#define PF_UNSPEC AF_UNSPEC
+#define PF_INET AF_INET
+#define PF_NETBIOS AF_NETBIOS
+
+/* BSD Socket Type */
+#define SOCK_STREAM 1 /* Stream Socket (Connection oriented) */
+#define SOCK_DGRAM 2 /* Datagram Socket (Connectionless) */
+
+/* BSD Socket Protocol */
+#define IPPROTO_TCP 1 /* TCP Protocol */
+#define IPPROTO_UDP 2 /* UDP Protocol */
+
+/* BSD Internet Addresses */
+#define INADDR_ANY 0x00000000 /* All IP addresses accepted */
+#define INADDR_NONE 0xffffffff /* No IP address accepted */
+
+/* BSD Socket Return values */
+#define SCK_SUCCESS 0 /* Success */
+#define SCK_ERROR (-1) /* General Error */
+#define SCK_EINVALID (-2) /* Invalid socket descriptor */
+#define SCK_EINVALIDPARA (-3) /* Invalid parameter */
+#define SCK_EWOULDBLOCK (-4) /* It would have blocked. */
+#define SCK_EMEMNOTAVAIL (-5) /* Not enough memory in memory pool */
+#define SCK_ECLOSED (-6) /* Connection is closed or aborted */
+#define SCK_ELOCKED (-7) /* Socket is locked in RTX environment */
+#define SCK_ETIMEOUT (-8) /* Socket, Host Resolver timeout */
+#define SCK_EINPROGRESS (-9) /* Host Name resolving in progress */
+#define SCK_ENONAME (-10) /* Host Name not existing */
+
+/* BSD Socket flags parameter */
+#define MSG_DONTWAIT 0x01 /* Enables non-blocking operation */
+#define MSG_PEEK 0x02 /* Peeks at the incoming data */
+
+/* BSD Socket ioctl commands */
+#define FIONBIO 1 /* Set mode (blocking/non-blocking) */
+#define FIO_DELAY_ACK 2 /* Set DELAY_ACK mode for stream socket */
+#define FIO_KEEP_ALIVE 3 /* Set KEEP_ALIVE mode for stream socket */
+#define FIO_FLOW_CTRL 4 /* Set FLOW_CTRL mode for stream socket */
+
+/* ICMP (ping) Callback Events */
+#define ICMP_EVT_SUCCESS 0 /* Pinged Host responded */
+#define ICMP_EVT_TIMEOUT 1 /* Timeout, no ping response received */
+
+/* DNS Client Callback Events */
+#define DNS_EVT_SUCCESS 0 /* Host name successfully resolved */
+#define DNS_EVT_NONAME 1 /* DNS Error, no such name */
+#define DNS_EVT_TIMEOUT 2 /* Timeout resolving host */
+#define DNS_EVT_ERROR 3 /* Erroneous response packet */
+
+/* DNS 'get_host_by_name()' result codes */
+#define DNS_RES_OK 0 /* Resolver successfully started */
+#define DNS_ERROR_BUSY 1 /* Resolver busy, can't process request */
+#define DNS_ERROR_LABEL 2 /* Label in Hostname not valid */
+#define DNS_ERROR_NAME 3 /* Entire Hostname not valid */
+#define DNS_ERROR_NOSRV 4 /* Prim. DNS server not specified (0.0.0.0)*/
+#define DNS_ERROR_PARAM 5 /* Invalid parameter */
+
+/* SMTP Client Callback Events */
+#define SMTP_EVT_SUCCESS 0 /* Email successfully sent */
+#define SMTP_EVT_TIMEOUT 1 /* Timeout sending email */
+#define SMTP_EVT_ERROR 2 /* Error when sending email */
+
+/* FTP Client Commands */
+#define FTPC_CMD_PUT 0 /* Puts a file on FTP server */
+#define FTPC_CMD_GET 1 /* Retrieves a file from FTP server */
+#define FTPC_CMD_APPEND 2 /* Append file on FTP server (with create) */
+#define FTPC_CMD_DELETE 3 /* Deletes a file on FTP server */
+#define FTPC_CMD_LIST 4 /* Lists files stored on FTP server */
+#define FTPC_CMD_RENAME 5 /* Renames a file on FTP server */
+#define FTPC_CMD_MKDIR 6 /* Makes a directory on FTP server */
+#define FTPC_CMD_RMDIR 7 /* Removes an empty directory on FTP server*/
+
+/* FTP Client Callback Events */
+#define FTPC_EVT_SUCCESS 0 /* File operation successful */
+#define FTPC_EVT_TIMEOUT 1 /* Timeout on file operation */
+#define FTPC_EVT_LOGINFAIL 2 /* Login error, username/passw invalid */
+#define FTPC_EVT_NOACCESS 3 /* File access not allowed */
+#define FTPC_EVT_NOTFOUND 4 /* File not found */
+#define FTPC_EVT_NOPATH 5 /* Working directory path not found */
+#define FTPC_EVT_ERRLOCAL 6 /* Local file open error */
+#define FTPC_EVT_ERROR 7 /* Generic FTP client error */
+
+/* TFTP Client Callback Events */
+#define TFTPC_EVT_SUCCESS 0 /* File operation successful */
+#define TFTPC_EVT_TIMEOUT 1 /* Timeout on file operation */
+#define TFTPC_EVT_NOACCESS 2 /* File access not allowed */
+#define TFTPC_EVT_NOTFOUND 3 /* File not found */
+#define TFTPC_EVT_DISKFULL 4 /* Disk full (local or remote) */
+#define TFTPC_EVT_ERROR 5 /* Generic TFTP client error */
+
+/* ARP Cache Entry types */
+#define ARP_FIXED_IP 0 /* Fixed IP adrs is refreshed after tout */
+#define ARP_TEMP_IP 1 /* Temp adrs is removed after timeout */
+
+/* BSD Socket typedef's */
+typedef struct sockaddr { /* << Generic Socket Address structure >> */
+ U16 sa_family; /* Address family */
+ char sa_data[14]; /* Direct address (up to 14 bytes) */
+} SOCKADDR;
+
+#pragma push
+#pragma anon_unions
+
+typedef struct in_addr { /* << Generic IPv4 Address structure >> */
+ union {
+ struct {
+ U8 s_b1,s_b2,s_b3,s_b4; /* IP address, byte access */
+ };
+ struct {
+ U16 s_w1,s_w2; /* IP address, short int access */
+ };
+ U32 s_addr; /* IP address in network byte order */
+ };
+} IN_ADDR;
+#pragma pop
+
+typedef struct sockaddr_in { /* << IPv4 Socket Address structure >> */
+ S16 sin_family; /* Socket domain */
+ U16 sin_port; /* Port */
+ IN_ADDR sin_addr; /* IP address */
+ S8 sin_zero[8]; /* reserved */
+} SOCKADDR_IN;
+
+typedef struct hostent { /* << BSD Host Entry structure >> */
+ char *h_name; /* Official name of host */
+ char **h_aliases; /* Pointer to an array of alias names */
+ S16 h_addrtype; /* Address Type: AF_INET, AF_NETBIOS */
+ S16 h_length; /* Length of address in bytes */
+ char **h_addr_list; /* Pointer to an array of IPv4 addresses */
+} HOSTENT;
+
+extern void init_TcpNet (void);
+extern BOOL main_TcpNet (void);
+extern void timer_tick (void);
+extern U8 udp_get_socket (U8 tos, U8 opt,
+ U16 (*listener)(U8 socket, U8 *remip, U16 port, U8 *buf, U16 len));
+extern BOOL udp_release_socket (U8 socket);
+extern BOOL udp_open (U8 socket, U16 locport);
+extern BOOL udp_close (U8 socket);
+extern BOOL udp_mcast_ttl (U8 socket, U8 ttl);
+extern U8 *udp_get_buf (U16 size);
+extern BOOL udp_send (U8 socket, U8 *remip, U16 remport, U8 *buf, U16 dlen);
+extern U8 tcp_get_socket (U8 type, U8 tos, U16 tout,
+ U16 (*listener)(U8 socket, U8 event, U8 *buf, U16 len));
+extern BOOL tcp_release_socket (U8 socket);
+extern BOOL tcp_listen (U8 socket, U16 locport);
+extern BOOL tcp_connect (U8 socket, U8 *remip, U16 remport, U16 locport);
+extern U8 *tcp_get_buf (U16 size);
+extern U16 tcp_max_dsize (U8 socket);
+extern BOOL tcp_check_send (U8 socket);
+extern U8 tcp_get_state (U8 socket);
+extern BOOL tcp_send (U8 socket, U8 *buf, U16 dlen);
+extern BOOL tcp_close (U8 socket);
+extern BOOL tcp_abort (U8 socket);
+extern void tcp_reset_window (U8 socket);
+extern BOOL arp_cache_ip (U8 *ipadr, U8 type);
+extern BOOL arp_cache_mac (U8 *hwadr);
+extern void ppp_listen (const char *user, const char *passw);
+extern void ppp_connect (const char *dialnum, const char *user, const char *passw);
+extern void ppp_close (void);
+extern BOOL ppp_is_up (void);
+extern void slip_listen (void);
+extern void slip_connect (const char *dialnum);
+extern void slip_close (void);
+extern BOOL slip_is_up (void);
+extern U8 get_host_by_name (U8 *hostn, void (*cbfunc)(U8 event, U8 *host_ip));
+extern BOOL smtp_connect (U8 *ipadr, U16 port, void (*cbfunc)(U8 event));
+extern void dhcp_disable (void);
+extern BOOL igmp_join (U8 *group_ip);
+extern BOOL igmp_leave (U8 *group_ip);
+extern BOOL snmp_trap (U8 *manager_ip, U8 gen_trap, U8 spec_trap, U16 *obj_list);
+extern BOOL snmp_set_community (const char *community);
+extern BOOL icmp_ping (U8 *remip, void (*cbfunc)(U8 event));
+extern BOOL ftpc_connect (U8 *ipadr, U16 port, U8 command, void (*cbfunc)(U8 event));
+extern BOOL tftpc_put (U8 *ipadr, U16 port,
+ const char *src, const char *dst, void (*cbfunc)(U8 event));
+extern BOOL tftpc_get (U8 *ipadr, U16 port,
+ const char *src, const char *dst, void (*cbfunc)(U8 event));
+extern BOOL sntp_get_time (U8 *ipadr, void (*cbfunc)(U32 utc_time));
+
+/* BSD Socket API */
+extern int socket (int family, int type, int protocol);
+extern int bind (int sock, const SOCKADDR *addr, int addrlen);
+extern int listen (int sock, int backlog);
+extern int accept (int sock, SOCKADDR *addr, int *addrlen);
+extern int connect (int sock, SOCKADDR *addr, int addrlen);
+extern int send (int sock, const char *buf, int len, int flags);
+extern int sendto (int sock, const char *buf, int len, int flags, SOCKADDR *to, int tolen);
+extern int recv (int sock, char *buf, int len, int flags);
+extern int recvfrom (int sock, char *buf, int len, int flags, SOCKADDR *from, int *fromlen);
+extern int closesocket (int sock);
+extern int getpeername (int sock, SOCKADDR *name, int *namelen);
+extern int getsockname (int sock, SOCKADDR *name, int *namelen);
+extern int ioctlsocket (int sock, long cmd, unsigned long *argp);
+extern HOSTENT *gethostbyname (const char *name, int *err);
+
+#ifdef __cplusplus
+}
+#endif
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+#endif
+
diff -r 000000000000 -r 01f31e923fe2 source/rtos/RTX_Config.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/rtos/RTX_Config.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,217 @@
+/**
+ * @file RTX_Config.c
+ * @brief Project settings for the RTX kernel
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTL.h"
+#include "util.h"
+#include "cortex_m.h"
+
+/*----------------------------------------------------------------------------
+ * RTX User configuration part BEGIN
+ *---------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+//
+// <h>Task Configuration
+// =====================
+//
+// <o>Number of concurrent running tasks <0-250>
+// <i> Define max. number of tasks that will run at the same time.
+// <i> Default: 6
+#ifndef OS_TASKCNT
+#define OS_TASKCNT 4
+// Threads with user provided stacks:
+// -serial_process
+// -hid_process
+// -timer_task_30mS
+// -main_task
+#endif
+
+// <o>Number of tasks with user-provided stack <0-250>
+// <i> Define the number of tasks that will use a bigger stack.
+// <i> The memory space for the stack is provided by the user.
+// <i> Default: 0
+#ifndef OS_PRIVCNT
+#define OS_PRIVCNT OS_TASKCNT
+// All tasks use private stacks (aside from background thread)
+#endif
+
+// <o>Task stack size [bytes] <20-4096:8><#/4>
+// <i> Set the stack size for tasks which is assigned by the system.
+// <i> Default: 200
+#ifndef OS_STKSIZE
+#define OS_STKSIZE 34
+// Used by:
+// -os_idle_demon
+#endif
+
+// <q>Check for the stack overflow
+// ===============================
+// <i> Include the stack checking code for a stack overflow.
+// <i> Note that additional code reduces the Kernel performance.
+#ifndef OS_STKCHECK
+#define OS_STKCHECK 1
+#endif
+
+// <q>Run in privileged mode
+// =========================
+// <i> Run all Tasks in privileged mode.
+// <i> Default: Unprivileged
+#ifndef OS_RUNPRIV
+#define OS_RUNPRIV 1
+#endif
+
+// </h>
+// <h>SysTick Timer Configuration
+// =============================
+// <o>Timer clock value [Hz] <1-1000000000>
+// <i> Set the timer clock value for selected timer.
+#ifndef OS_CLOCK
+#error "OS_CLOCK should be defined by HIC configuration"
+#endif
+
+// <o>Timer tick value [us] <1-1000000>
+// <i> Set the timer tick value for selected timer.
+#ifndef OS_TICK
+#error "OS_TICK should be defined by RTOS configuration"
+#endif
+
+// </h>
+
+// <h>System Configuration
+// =======================
+// <e>Round-Robin Task switching
+// =============================
+// <i> Enable Round-Robin Task switching.
+#ifndef OS_ROBIN
+#define OS_ROBIN 0
+#endif
+
+// <o>Round-Robin Timeout [ticks] <1-1000>
+// <i> Define how long a task will execute before a task switch.
+// <i> Default: 5
+#ifndef OS_ROBINTOUT
+#define OS_ROBINTOUT 10
+#endif
+
+// </e>
+
+// <o>Number of user timers <0-250>
+// <i> Define max. number of user timers that will run at the same time.
+// <i> Default: 0 (User timers disabled)
+#ifndef OS_TIMERCNT
+#define OS_TIMERCNT 0
+#endif
+
+// <o>ISR FIFO Queue size<4=> 4 entries <8=> 8 entries
+// <12=> 12 entries <16=> 16 entries
+// <24=> 24 entries <32=> 32 entries
+// <48=> 48 entries <64=> 64 entries
+// <96=> 96 entries
+// <i> ISR functions store requests to this buffer,
+// <i> when they are called from the iterrupt handler.
+// <i> Default: 16 entries
+#ifndef OS_FIFOSZ
+#define OS_FIFOSZ 4
+#endif
+
+// </h>
+
+//------------- <<< end of configuration section >>> -----------------------
+
+// Standard library system mutexes
+// ===============================
+// Define max. number system mutexes that are used to protect
+// the arm standard runtime library. For microlib they are not used.
+#ifndef OS_MUTEXCNT
+#define OS_MUTEXCNT 1
+#endif
+
+/*----------------------------------------------------------------------------
+ * RTX User configuration part END
+ *---------------------------------------------------------------------------*/
+
+#define OS_TRV ((U32)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
+
+/*----------------------------------------------------------------------------
+ * Global Functions
+ *---------------------------------------------------------------------------*/
+
+/*--------------------------- os_idle_demon ---------------------------------*/
+
+__task void os_idle_demon(void)
+{
+ /* The idle demon is a system task, running when no other task is ready */
+ /* to run. The 'os_xxx' function calls are not allowed from this task. */
+ for (;;) {
+ /* HERE: include optional user code to be executed when no task runs.*/
+ }
+}
+
+
+/*--------------------------- os_tmr_call -----------------------------------*/
+
+void os_tmr_call(U16 info)
+{
+ /* This function is called when the user timer has expired. Parameter */
+ /* 'info' holds the value, defined when the timer was created. */
+ /* HERE: include optional user code to be executed on timeout. */
+}
+
+
+/*--------------------------- os_error --------------------------------------*/
+
+void os_error(U32 err_code)
+{
+ /* This function is called when a runtime error is detected. Parameter */
+ /* 'err_code' holds the runtime error code (defined in RTL.H). */
+ switch (err_code) {
+ case OS_ERR_STK_OVF:
+ util_assert(0);
+ break;
+
+ case OS_ERR_FIFO_OVF:
+ util_assert(0);
+ break;
+
+ case OS_ERR_MBX_OVF:
+ util_assert(0);
+ break;
+
+ default:
+ util_assert(0);
+ break;
+ }
+
+ SystemReset();
+
+ for (;;); // Wait for reset
+}
+
+
+/*----------------------------------------------------------------------------
+ * RTX Configuration Functions
+ *---------------------------------------------------------------------------*/
+
+#include "RTX_lib.c"
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff -r 000000000000 -r 01f31e923fe2 source/rtos/RTX_Config.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/rtos/RTX_Config.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,62 @@ +/** + * @file RTX_Config.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Error Codes */ +#define OS_ERR_STK_OVF 1 +#define OS_ERR_FIFO_OVF 2 +#define OS_ERR_MBX_OVF 3 + +/* Definitions */ +#define BOX_ALIGN_8 0x80000000 +#define _declare_box(pool,size,cnt) U32 pool[(((size)+3)/4)*(cnt) + 3] +#define _declare_box8(pool,size,cnt) U64 pool[(((size)+7)/8)*(cnt) + 2] +#define _init_box8(pool,size,bsize) _init_box (pool,size,(bsize) | BOX_ALIGN_8) + +/* Variables */ +extern U32 mp_tcb[]; +extern U64 mp_stk[]; +extern U32 os_fifo[]; +extern void *os_active_TCB[]; + +/* Constants */ +extern U16 const os_maxtaskrun; +extern U32 const os_trv; +extern U8 const os_flags; +extern U32 const os_stackinfo; +extern U32 const os_rrobin; +extern U32 const os_clockrate; +extern U32 const os_timernum; +extern U16 const mp_tcb_size; +extern U32 const mp_stk_size; +extern U32 const *m_tmr; +extern U16 const mp_tmr_size; +extern U8 const os_fifo_size; + +/* Functions */ +extern void os_idle_demon (void); +extern int os_tick_init (void); +extern void os_tick_irqack (void); +extern void os_tmr_call (U16 info); +extern void os_error (U32 err_code); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/
diff -r 000000000000 -r 01f31e923fe2 source/rtos/RTX_lib.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/rtos/RTX_lib.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,440 @@
+/**
+ * @file RTX_lib.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#pragma thumb
+#pragma O3
+
+/*----------------------------------------------------------------------------
+ * Definitions
+ *---------------------------------------------------------------------------*/
+#if (__TARGET_ARCH_6S_M || __TARGET_ARCH_7_M || __TARGET_ARCH_7E_M)
+ #define __CM__ 1
+#elif (__TARGET_ARCH_7_R)
+ #define __CR__ 1
+#else
+ #define __ARM__ 1
+#endif
+
+#if (__ARM__ || __CR__)
+ #define runtask_id() os_tsk_self()
+ #define mutex_init(m) os_mut_init(m)
+#endif
+#if (__CM__)
+ #ifndef OS_TIMER
+ #define OS_TIMER 0
+ #endif
+ #define runtask_id() rt_tsk_self()
+ #define mutex_init(m) rt_mut_init(m)
+#endif
+
+#define mutex_wait(m) os_mut_wait(m,0xFFFF)
+#define mutex_rel(m) os_mut_release(m)
+
+
+/*----------------------------------------------------------------------------
+ * Global Variables
+ *---------------------------------------------------------------------------*/
+U16 const os_maxtaskrun = OS_TASKCNT;
+U32 const os_stackinfo = (OS_STKCHECK<<24)| (OS_PRIVCNT<<16) | (OS_STKSIZE*4);
+U32 const os_rrobin = (OS_ROBIN << 16) | OS_ROBINTOUT;
+#if (__CM__)
+ U32 const os_trv = OS_TRV;
+#endif
+#if (__CM__ || __CR__)
+ U8 const os_flags = OS_RUNPRIV;
+#endif
+
+/* Export following defines to uVision debugger. */
+U32 const os_clockrate __attribute__((used)) = OS_TICK;
+U32 const os_timernum __attribute__((used)) = (OS_TIMER << 16) | OS_TIMERCNT;
+
+/* Memory pool for TCB allocation */
+_declare_box (mp_tcb, OS_TCB_SIZE, OS_TASKCNT);
+U16 const mp_tcb_size = sizeof(mp_tcb);
+
+/* Memory pool for System stack allocation (+ os_idle_demon). */
+_declare_box8 (mp_stk, OS_STKSIZE*4, OS_TASKCNT-OS_PRIVCNT+1);
+U32 const mp_stk_size = sizeof(mp_stk);
+
+#ifndef OS_FIFOSZ
+ #define OS_FIFOSZ 16
+#endif
+
+/* Fifo Queue buffer for ISR requests.*/
+U32 os_fifo[OS_FIFOSZ*2+1];
+U8 const os_fifo_size = OS_FIFOSZ;
+
+/* An array of Active task pointers. */
+void *os_active_TCB[OS_TASKCNT];
+
+#if (OS_TIMERCNT != 0)
+ /* Memory pool for User Timer allocation */
+ _declare_box (mp_tmr, OS_TMR_SIZE, OS_TIMERCNT);
+ U16 const mp_tmr_size = sizeof(mp_tmr);
+ U32 const *m_tmr = &mp_tmr[0];
+#else
+ U32 const *m_tmr = NULL;
+ U16 const mp_tmr_size = 0;
+#endif
+
+#ifndef __MICROLIB
+ /* A memory space for arm standard library. */
+ static U32 std_libspace[OS_TASKCNT][96/4];
+ static OS_MUT std_libmutex[OS_MUTEXCNT];
+ static U32 nr_mutex;
+ extern void *__libspace_start;
+#endif
+
+/*----------------------------------------------------------------------------
+ * Tick Timer configuration for ARM7/9, Cortex-R4
+ *---------------------------------------------------------------------------*/
+
+#if (__ARM__ || __CR__)
+
+extern void os_clock_interrupt (void);
+
+/*--------------------------- os_tmr_init -----------------------------------*/
+
+#ifndef __OS_TMR_INIT
+void os_tmr_init (void) {
+ /* Initialize hardware timer as system tick timer. */
+ OS_TINIT();
+}
+#endif
+
+/*--------------------------- os_tmr_reload ---------------------------------*/
+
+#if (!defined(__OS_TMR_RELOAD) && defined(OS_TREL))
+void os_tmr_reload (void) {
+ /* Reload system timer for next period. */
+ OS_TREL();
+}
+#endif
+
+/*--------------------------- os_tmr_force_irq ------------------------------*/
+
+#ifndef __OS_TMR_FORCE_IRQ
+void os_tmr_force_irq (void) {
+ /* Force a timer interrupt. */
+ OS_TFIRQ();
+}
+#endif
+
+/*--------------------------- os_tmr_inspect_cnt ----------------------------*/
+
+#ifndef __OS_TMR_INSPECT_CNT
+U32 os_tmr_inspect_cnt (void) {
+ /* Inspect current value of rtx timer. */
+ return (OS_TVAL);
+}
+#endif
+
+/*--------------------------- os_tmr_inspect_ovf ----------------------------*/
+
+#ifndef __OS_TMR_INSPECT_OVF
+BOOL os_tmr_inspect_ovf (void) {
+ /* Inspect current state of timer overflow flag. */
+ return (OS_TOVF);
+}
+#endif
+
+/*--------------------------- os_irq_ack_lock -------------------------------*/
+
+#ifndef __OS_IRQ_ACK_LOCK
+void os_irq_ack_lock (void) {
+ /* Acknowledge and disable a timer interrupt. */
+ OS_TIACK();
+ OS_LOCK();
+}
+#endif
+
+/*--------------------------- tsk_lock --------------------------------------*/
+
+#ifndef __TSK_LOCK
+void __swi(5) tsk_lock (void);
+void __SWI_5 (void) {
+ /* Disable RTX System Tick Timer interrupts. */
+ OS_LOCK();
+}
+#endif
+
+/*--------------------------- tsk_unlock ------------------------------------*/
+
+#ifndef __TSK_UNLOCK
+void tsk_unlock (void) {
+ /* Enable RTX System Tick Timer Interrupts. */
+ OS_UNLOCK();
+}
+#endif
+
+#endif /* #if (__ARM__ || __CR__) */
+
+
+/*----------------------------------------------------------------------------
+ * RT Agent interface for ARM7/9
+ *---------------------------------------------------------------------------*/
+
+#if (__ARM__ && __RTA_RTX_CONFIG)
+
+#include "RT_Agent.h"
+
+#if (__RTA_ENABLED && __RTA_RTX_TASK_SWITCHING)
+/*
+ * RT Agent - Event Viewer Packing
+ *
+ * |---+---------+---------+------|
+ * | 0 | os_time | hw_tick | t_id |
+ * |---+---------+---------+------|
+ * bit 31 ^ 7 0
+ * +-- OS_TIME_SL
+ *
+ * value hw_tick is truncated by number of bits specified by OS_TVAL_SR
+ * value os_time is shifted left by number of bits specified by OS_TIME_SL
+ */
+
+/* Define pack shift values depending on the tick time value OS_TICK. */
+/* Packing results in a time of ~1 second being represented, and an */
+/* accuracy of ~0.15us. (based on the hw tick timer accuracy. */
+
+#if ((OS_TICK) < 0x80) // OS_TICK < 128us ==> tick 14 bits, timer 9
+ #define OS_TIME_SL 17
+#elif ((OS_TICK) < 0x100) // OS_TICK < 256us ==> tick 13 bits, timer 10
+ #define OS_TIME_SL 18
+#elif ((OS_TICK) < 0x200) // OS_TICK < 512us ==> tick 12 bits, timer 11
+ #define OS_TIME_SL 19
+#elif ((OS_TICK) < 0x400) // OS_TICK < 1.024ms ==> tick 11 bits, timer 12
+ #define OS_TIME_SL 20
+#elif ((OS_TICK) < 0x800) // OS_TICK < 2.048ms ==> tick 10 bits, timer 13
+ #define OS_TIME_SL 21
+#elif ((OS_TICK) < 0x1000) // OS_TICK < 4.096ms ==> tick 9 bits, timer 14
+ #define OS_TIME_SL 22
+#elif ((OS_TICK) < 0x2000) // OS_TICK < 8.192ms ==> tick 8 bits, timer 15
+ #define OS_TIME_SL 23
+#elif ((OS_TICK) < 0x4000) // OS_TICK < 16.384ms ==> tick 7 bits, timer 16
+ #define OS_TIME_SL 24
+#elif ((OS_TICK) < 0x8000) // OS_TICK < 32.768ms ==> tick 6 bits, timer 17
+ #define OS_TIME_SL 25
+#elif ((OS_TICK) < 0x10000) // OS_TICK < 65.536ms ==> tick 5 bits, timer 18
+ #define OS_TIME_SL 26
+#elif ((OS_TICK) < 0x20000) // OS_TICK < 131.070ms ==> tick 4 bits, timer 19
+ #define OS_TIME_SL 27
+#elif ((OS_TICK) < 0x40000) // OS_TICK < 262.140ms ==> tick 3 bits, timer 20
+ #define OS_TIME_SL 28
+#elif ((OS_TICK) < 0x80000) // OS_TICK < 524.280ms ==> tick 2 bits, timer 21
+ #define OS_TIME_SL 29
+#else // OS_TICK >= 524.280ms ==> tick 1 bit, timer 22
+ #define OS_TIME_SL 30
+#endif
+
+/* Define hw_tick truncation depending on the timer reload value OS_TRV */
+#if ((OS_TRV) < 0x10)
+ #define OS_TVAL_SR (12 - OS_TIME_SL)
+#elif ((OS_TRV) < 0x20)
+ #define OS_TVAL_SR (13 - OS_TIME_SL)
+#elif ((OS_TRV) < 0x40)
+ #define OS_TVAL_SR (14 - OS_TIME_SL)
+#elif ((OS_TRV) < 0x80)
+ #define OS_TVAL_SR (15 - OS_TIME_SL)
+#elif ((OS_TRV) < 0x100)
+ #define OS_TVAL_SR (16 - OS_TIME_SL)
+#elif ((OS_TRV) < 0x200)
+ #define OS_TVAL_SR (17 - OS_TIME_SL)
+#elif ((OS_TRV) < 0x400)
+ #define OS_TVAL_SR (18 - OS_TIME_SL)
+#elif ((OS_TRV) < 0x800)
+ #define OS_TVAL_SR (19 - OS_TIME_SL)
+#elif ((OS_TRV) < 0x1000)
+ #define OS_TVAL_SR (20 - OS_TIME_SL)
+#elif ((OS_TRV) < 0x2000)
+ #define OS_TVAL_SR (21 - OS_TIME_SL)
+#elif ((OS_TRV) < 0x4000)
+ #define OS_TVAL_SR (22 - OS_TIME_SL)
+#elif ((OS_TRV) < 0x8000)
+ #define OS_TVAL_SR (23 - OS_TIME_SL)
+#elif ((OS_TRV) < 0x10000)
+ #define OS_TVAL_SR (24 - OS_TIME_SL)
+#elif ((OS_TRV) < 0x20000)
+ #define OS_TVAL_SR (25 - OS_TIME_SL)
+#elif ((OS_TRV) < 0x40000)
+ #define OS_TVAL_SR (26 - OS_TIME_SL)
+#elif ((OS_TRV) < 0x80000)
+ #define OS_TVAL_SR (27 - OS_TIME_SL)
+#elif ((OS_TRV) < 0x100000)
+ #define OS_TVAL_SR (28 - OS_TIME_SL)
+#elif ((OS_TRV) < 0x200000)
+ #define OS_TVAL_SR (29 - OS_TIME_SL)
+#elif ((OS_TRV) < 0x400000)
+ #define OS_TVAL_SR (30 - OS_TIME_SL)
+#elif ((OS_TRV) < 0x800000)
+ #define OS_TVAL_SR (31 - OS_TIME_SL)
+#elif ((OS_TRV) < 0x1000000)
+ #define OS_TVAL_SR (32 - OS_TIME_SL)
+#elif ((OS_TRV) < 0x2000000)
+ #define OS_TVAL_SR (33 - OS_TIME_SL)
+#elif ((OS_TRV) < 0x4000000)
+ #define OS_TVAL_SR (34 - OS_TIME_SL)
+#elif ((OS_TRV) < 0x8000000)
+ #define OS_TVAL_SR (35 - OS_TIME_SL)
+#else
+ #define OS_TVAL_SR (36 - OS_TIME_SL)
+#endif
+
+#if (OS_TVAL_SR < 0)
+ #undef OS_TVAL_SR
+ #define OS_TVAL_SR 0
+#endif
+
+extern U32 os_time;
+
+/* Export following defines to uVision debugger. */
+U8 const os_time_sl __attribute__((used)) = OS_TIME_SL;
+U32 const os_treload __attribute__((used)) = OS_TRV;
+
+__weak extern void RTA_Task_Mon (unsigned int tsk);
+
+#define RTA_CMD_RTX_TASK_INFO 0x0A
+
+void rt_notify (U32 ptask, U32 create_tid) {
+ /* Notify RTA user of a task creation/deletion. */
+ U32 msg[2];
+
+ /* (BOOL)create << 8 | task_id - parameter packed in RTX library */
+ msg[0] = create_tid;
+ msg[1] = (U32)ptask;
+ RTA_Msg (RTA_CMD_RTX_TASK_INFO, (U32 *)&msg, 2);
+}
+
+/*--------------------------- rt_post_taskswitch ----------------------------*/
+
+void rt_post_taskswitch (U32 task_id) {
+ U32 tsk_event;
+
+ /* Add the current timer value (with bottom bits removed) */
+ tsk_event = OS_TVAL >> OS_TVAL_SR;
+ /* Shif timer value into place, add the task ID. */
+ tsk_event = (tsk_event << 8) | task_id;
+ /* Add the OS tick time. */
+ tsk_event = tsk_event | (os_time << OS_TIME_SL);
+ /* Mask off the top bit to indicate a task switch message. */
+ tsk_event &= 0x7FFFFFFFU;
+
+ RTA_Task_Mon (tsk_event);
+}
+
+#endif /* #if (__RTA_ENABLED && __RTA_RTX_TASK_SWITCHING) */
+
+/*--------------------------- rt_init ---------------------------------------*/
+
+void rt_init (void) {
+ RTA_Init ();
+}
+
+
+#include "RT_Agent.c"
+
+#endif /* #if (__ARM__ && __RTA_RTX_CONFIG) */
+
+
+/*----------------------------------------------------------------------------
+ * RTX Optimizations (empty functions)
+ *---------------------------------------------------------------------------*/
+
+#if (__ARM__ || __CR__) && OS_ROBIN == 0
+ void os_init_robin (void) {;}
+ void os_chk_robin (void) {;}
+#endif
+
+#if (__ARM__ || __CR__) && OS_STKCHECK == 0
+ void os_stk_check (U32 stk) {;}
+#endif
+
+#if (__CM__) && OS_ROBIN == 0
+ void rt_init_robin (void) {;}
+ void rt_chk_robin (void) {;}
+#endif
+
+#if (__CM__) && OS_STKCHECK == 0
+ void rt_stk_check (void) {;}
+#endif
+
+
+/*----------------------------------------------------------------------------
+ * Standard Library multithreading interface
+ *---------------------------------------------------------------------------*/
+
+#ifndef __MICROLIB
+
+/*--------------------------- __user_perthread_libspace ---------------------*/
+
+void *__user_perthread_libspace (void) {
+ /* Provide a separate libspace for each task. */
+ U32 idx;
+
+ idx = runtask_id ();
+ if (idx == 0) {
+ /* RTX not running yet. */
+ return (&__libspace_start);
+ }
+ return ((void *)&std_libspace[idx-1]);
+}
+
+/*--------------------------- _mutex_initialize -----------------------------*/
+
+int _mutex_initialize (OS_ID *mutex) {
+ /* Allocate and initialize a system mutex. */
+
+ if (nr_mutex >= OS_MUTEXCNT) {
+ /* If you are here, you need to increase the number OS_MUTEXCNT. */
+ for (;;);
+ }
+ *mutex = &std_libmutex[nr_mutex++];
+ mutex_init (*mutex);
+ return (1);
+}
+
+
+/*--------------------------- _mutex_acquire --------------------------------*/
+
+__used void _mutex_acquire (OS_ID *mutex) {
+ /* Acquire a system mutex, lock stdlib resources. */
+ if (runtask_id ()) {
+ /* RTX running, acquire a mutex. */
+ mutex_wait (*mutex);
+ }
+}
+
+
+/*--------------------------- _mutex_release --------------------------------*/
+
+__used void _mutex_release (OS_ID *mutex) {
+ /* Release a system mutex, unlock stdlib resources. */
+ if (runtask_id ()) {
+ /* RTX runnning, release a mutex. */
+ mutex_rel (*mutex);
+ }
+}
+
+#endif
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
diff -r 000000000000 -r 01f31e923fe2 source/rtos/cm0/HAL_CM1.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/rtos/cm0/HAL_CM1.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,352 @@
+/**
+ * @file HAL_CM1.c
+ * @brief HAL for Cortex-M0(p)
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_HAL_CM.h"
+#include "rt_Task.h"
+#include "rt_List.h"
+#include "rt_MemBox.h"
+
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_set_PSP ------------------------------------*/
+
+__asm void rt_set_PSP (U32 stack) {
+ MSR PSP,R0
+ BX LR
+}
+
+
+/*--------------------------- rt_get_PSP ------------------------------------*/
+
+__asm U32 rt_get_PSP (void) {
+ MRS R0,PSP
+ BX LR
+}
+
+
+/*--------------------------- os_set_env ------------------------------------*/
+
+__asm void os_set_env (void) {
+ /* Switch to Unprivileged/Privileged Thread mode, use PSP. */
+ MOV R0,SP ; PSP = MSP
+ MSR PSP,R0
+ LDR R0,=__cpp(&os_flags)
+ LDRB R0,[R0]
+ LSLS R0,#31
+ BNE PrivilegedE
+ MOVS R0,#0x03 ; Unprivileged Thread mode, use PSP
+ MSR CONTROL,R0
+ BX LR
+PrivilegedE
+ MOVS R0,#0x02 ; Privileged Thread mode, use PSP
+ MSR CONTROL,R0
+ BX LR
+
+ ALIGN
+}
+
+
+/*--------------------------- _alloc_box ------------------------------------*/
+
+__asm void *_alloc_box (void *box_mem) {
+ /* Function wrapper for Unprivileged/Privileged mode. */
+ LDR R3,=__cpp(rt_alloc_box)
+ MOV R12,R3
+ MRS R3,IPSR
+ LSLS R3,#24
+ BNE PrivilegedA
+ MRS R3,CONTROL
+ LSLS R3,#31
+ BEQ PrivilegedA
+ SVC 0
+ BX LR
+PrivilegedA
+ BX R12
+
+ ALIGN
+}
+
+
+/*--------------------------- _free_box -------------------------------------*/
+
+__asm int _free_box (void *box_mem, void *box) {
+ /* Function wrapper for Unprivileged/Privileged mode. */
+ LDR R3,=__cpp(rt_free_box)
+ MOV R12,R3
+ MRS R3,IPSR
+ LSLS R3,#24
+ BNE PrivilegedF
+ MRS R3,CONTROL
+ LSLS R3,#31
+ BEQ PrivilegedF
+ SVC 0
+ BX LR
+PrivilegedF
+ BX R12
+
+ ALIGN
+}
+
+
+/*-------------------------- SVC_Handler ------------------------------------*/
+
+__asm void SVC_Handler (void) {
+ PRESERVE8
+
+ IMPORT SVC_Count
+ IMPORT SVC_Table
+ IMPORT rt_stk_check
+
+ MRS R0,PSP ; Read PSP
+ LDR R1,[R0,#24] ; Read Saved PC from Stack
+ SUBS R1,R1,#2 ; Point to SVC Instruction
+ LDRB R1,[R1] ; Load SVC Number
+ CMP R1,#0
+ BNE SVC_User ; User SVC Number > 0
+
+ MOV LR,R4
+ LDMIA R0,{R0-R3,R4} ; Read R0-R3,R12 from stack
+ MOV R12,R4
+ MOV R4,LR
+ BLX R12 ; Call SVC Function
+
+ LDR R3,=__cpp(&os_tsk)
+ LDMIA R3!,{R1,R2} ; os_tsk.run, os_tsk.new
+ CMP R1,R2
+ BEQ SVC_Exit ; no task switch
+
+ SUBS R3,#8
+ CMP R1,#0 ; Runtask deleted?
+ BEQ SVC_Restore
+
+ PUSH {R2,R3}
+ ADDS R1,#32 ; for STRB offset < 32
+ MOVS R3,#1
+ STRB R3,[R1,#TCB_RETUPD-32] ; os_tsk.run->ret_upd = 1
+
+ MRS R3,PSP ; Read PSP
+ SUBS R3,R3,#32 ; Adjust Start Address
+ STR R3,[R1,#TCB_TSTACK-32] ; Update os_tsk.run->tsk_stack
+ STMIA R3!,{R4-R7} ; Save old context (R4-R7)
+ MOV R4,R8
+ MOV R5,R9
+ MOV R6,R10
+ MOV R7,R11
+ STMIA R3!,{R4-R7} ; Save old context (R8-R11)
+ BL rt_stk_check ; Check for Stack overflow
+ POP {R2,R3}
+
+SVC_Restore
+ STR R2,[R3] ; os_tsk.run = os_tsk.new
+
+ ADDS R2,#32 ; for STRB offset < 32
+ LDR R3,[R2,#TCB_TSTACK-32] ; os_tsk.new->tsk_stack
+ ADDS R3,R3,#16 ; Adjust Start Address
+ LDMIA R3!,{R4-R7} ; Restore new Context (R8-R11)
+ MOV R8,R4
+ MOV R9,R5
+ MOV R10,R6
+ MOV R11,R7
+ MSR PSP,R3 ; Write PSP
+ SUBS R3,R3,#32 ; Adjust Start Address
+ LDMIA R3!,{R4-R7} ; Restore new Context (R4-R7)
+
+ LDRB R0,[R2,#TCB_RETUPD-32] ; Update ret_val ?
+ CMP R0,#0
+ BEQ SVC_Return
+ LDRB R0,[R2,#TCB_RETVAL-32] ; Write os_tsk.new->ret_val
+
+SVC_Exit
+ MRS R3,PSP ; Read PSP
+ STR R0,[R3] ; Function return value
+
+SVC_Return
+ MOVS R3,#:NOT:0xFFFFFFFD ; Set EXC_RETURN value
+ MVNS R3,R3
+ BX R3 ; RETI to Thread Mode, use PSP
+
+ /*------------------- User SVC ------------------------------*/
+
+SVC_User
+ PUSH {R4,LR} ; Save Registers
+ LDR R2,=SVC_Count
+ LDR R2,[R2]
+ CMP R1,R2
+ BHI SVC_Done ; Overflow
+
+ LDR R4,=SVC_Table-4
+ LSLS R1,R1,#2
+ LDR R4,[R4,R1] ; Load SVC Function Address
+ MOV LR,R4
+
+ LDMIA R0,{R0-R3,R4} ; Read R0-R3,R12 from stack
+ MOV R12,R4
+ BLX LR ; Call SVC Function
+
+ MRS R4,PSP ; Read PSP
+ STMIA R4!,{R0-R3} ; Function return values
+SVC_Done
+ POP {R4,PC} ; RETI
+
+ ALIGN
+}
+
+
+/*-------------------------- PendSV_Handler ---------------------------------*/
+
+__asm void PendSV_Handler (void) {
+ PRESERVE8
+
+ BL __cpp(rt_pop_req)
+
+Sys_Switch
+ LDR R3,=__cpp(&os_tsk)
+ LDMIA R3!,{R1,R2} ; os_tsk.run, os_tsk.new
+ CMP R1,R2
+ BEQ Sys_Exit ; no task switch
+
+ SUBS R3,#8
+ PUSH {R2,R3}
+ ADDS R1,#32 ; for STRB offset < 32
+
+ MOVS R3,#0
+ STRB R3,[R1,#TCB_RETUPD-32] ; os_tsk.run->ret_upd = 0
+ MRS R3,PSP ; Read PSP
+ SUBS R3,R3,#32 ; Adjust Start Address
+ STR R3,[R1,#TCB_TSTACK-32] ; Update os_tsk.run->tsk_stack
+ STMIA R3!,{R4-R7} ; Save old context (R4-R7)
+ MOV R4,R8
+ MOV R5,R9
+ MOV R6,R10
+ MOV R7,R11
+ STMIA R3!,{R4-R7} ; Save old context (R8-R11)
+ BL rt_stk_check ; Check for Stack overflow
+
+ POP {R2,R3}
+ STR R2,[R3] ; os_tsk.run = os_tsk.new
+ ADDS R2,#32 ; for STRB offset < 32
+
+ LDR R3,[R2,#TCB_TSTACK-32] ; os_tsk.new->tsk_stack
+ ADDS R3,R3,#16 ; Adjust Start Address
+ LDMIA R3!,{R4-R7} ; Restore new Context (R8-R11)
+ MOV R8,R4
+ MOV R9,R5
+ MOV R10,R6
+ MOV R11,R7
+ MSR PSP,R3 ; Write PSP
+ SUBS R3,R3,#32 ; Adjust Start Address
+ LDMIA R3!,{R4-R7} ; Restore new Context (R4-R7)
+
+ LDRB R0,[R2,#TCB_RETUPD-32] ; Update ret_val ?
+ CMP R0,#0
+ BEQ Sys_Exit
+ LDRB R0,[R2,#TCB_RETVAL-32] ; Write os_tsk.new->ret_val
+ STR R0,[R3,#16]
+Sys_Exit
+ MOVS R3,#:NOT:0xFFFFFFFD ; Set EXC_RETURN value
+ MVNS R3,R3
+ BX R3 ; RETI to Thread Mode, use PSP
+
+ ALIGN
+}
+
+
+/*-------------------------- SysTick_Handler --------------------------------*/
+
+__asm void SysTick_Handler (void) {
+ PRESERVE8
+
+ BL __cpp(rt_systick)
+ B Sys_Switch
+
+ ALIGN
+}
+
+
+/*-------------------------- OS_Tick_Handler --------------------------------*/
+
+__asm void OS_Tick_Handler (void) {
+ PRESERVE8
+
+ BL __cpp(os_tick_irqack)
+ BL __cpp(rt_systick)
+ B Sys_Switch
+
+ ALIGN
+}
+
+
+/*--------------------------- rt_init_stack ---------------------------------*/
+
+void rt_init_stack (P_TCB p_TCB, FUNCP task_body) {
+ /* Prepare TCB and saved context for a first time start of a task. */
+ U32 *stk,i,size;
+
+ /* Prepare a complete interrupt frame for first task start */
+ size = p_TCB->priv_stack >> 2;
+ if (size == 0) {
+ size = (U16)os_stackinfo >> 2;
+ }
+
+ /* Write to the top of stack. */
+ stk = &p_TCB->stack[size];
+
+ /* Auto correct to 8-byte ARM stack alignment. */
+ if ((U32)stk & 0x04) {
+ stk--;
+ }
+
+ stk -= 16;
+
+ /* Default xPSR and initial PC */
+ stk[15] = INITIAL_xPSR;
+ stk[14] = (U32)task_body;
+
+ /* Clear R1-R12,LR registers. */
+ for (i = 0; i < 14; i++) {
+ stk[i] = 0;
+ }
+
+ /* Assign a void pointer to R0. */
+ stk[8] = (U32)p_TCB->msg;
+
+ /* Initial Task stack pointer. */
+ p_TCB->tsk_stack = (U32)stk;
+
+ /* Task entry point. */
+ p_TCB->ptask = task_body;
+
+ /* Set a magic word for checking of stack overflow. */
+ p_TCB->stack[0] = MAGIC_WORD;
+}
+
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
diff -r 000000000000 -r 01f31e923fe2 source/rtos/cm3/HAL_CM3.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/rtos/cm3/HAL_CM3.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,354 @@
+/**
+ * @file HAL_CM3.c
+ * @brief HAL for Cortex-M3
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_HAL_CM.h"
+#include "rt_Task.h"
+#include "rt_List.h"
+#include "rt_MemBox.h"
+
+
+/*----------------------------------------------------------------------------
+ * Global Variables
+ *---------------------------------------------------------------------------*/
+
+BIT dbg_msg;
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_set_PSP ------------------------------------*/
+
+__asm void rt_set_PSP (U32 stack) {
+ MSR PSP,R0
+ BX LR
+}
+
+
+/*--------------------------- rt_get_PSP ------------------------------------*/
+
+__asm U32 rt_get_PSP (void) {
+ MRS R0,PSP
+ BX LR
+}
+
+
+/*--------------------------- os_set_env ------------------------------------*/
+
+__asm void os_set_env (void) {
+ /* Switch to Unprivileged/Privileged Thread mode, use PSP. */
+ MOV R0,SP ; PSP = MSP
+ MSR PSP,R0
+ LDR R0,=__cpp(&os_flags)
+ LDRB R0,[R0]
+ LSLS R0,#31
+ MOVNE R0,#0x02 ; Privileged Thread mode, use PSP
+ MOVEQ R0,#0x03 ; Unprivileged Thread mode, use PSP
+ MSR CONTROL,R0
+ BX LR
+
+ ALIGN
+}
+
+
+/*--------------------------- _alloc_box ------------------------------------*/
+
+__asm void *_alloc_box (void *box_mem) {
+ /* Function wrapper for Unprivileged/Privileged mode. */
+ LDR R12,=__cpp(rt_alloc_box)
+ MRS R3,IPSR
+ LSLS R3,#24
+ BXNE R12
+ MRS R3,CONTROL
+ LSLS R3,#31
+ BXEQ R12
+ SVC 0
+ BX LR
+
+ ALIGN
+}
+
+
+/*--------------------------- _free_box -------------------------------------*/
+
+__asm int _free_box (void *box_mem, void *box) {
+ /* Function wrapper for Unprivileged/Privileged mode. */
+ LDR R12,=__cpp(rt_free_box)
+ MRS R3,IPSR
+ LSLS R3,#24
+ BXNE R12
+ MRS R3,CONTROL
+ LSLS R3,#31
+ BXEQ R12
+ SVC 0
+ BX LR
+
+ ALIGN
+}
+
+
+/*-------------------------- SVC_Handler ------------------------------------*/
+
+__asm void SVC_Handler (void) {
+ PRESERVE8
+
+#ifdef IFX_XMC4XXX
+ EXPORT SVC_Handler_Veneer
+SVC_Handler_Veneer
+#endif
+
+ IMPORT SVC_Count
+ IMPORT SVC_Table
+ IMPORT rt_stk_check
+
+ MRS R0,PSP ; Read PSP
+ LDR R1,[R0,#24] ; Read Saved PC from Stack
+ LDRB R1,[R1,#-2] ; Load SVC Number
+ CBNZ R1,SVC_User
+
+ LDM R0,{R0-R3,R12} ; Read R0-R3,R12 from stack
+ BLX R12 ; Call SVC Function
+
+ MRS R12,PSP ; Read PSP
+ LDR R3,=__cpp(&os_tsk)
+ LDM R3,{R1,R2} ; os_tsk.run, os_tsk.new
+ CMP R1,R2
+ BEQ SVC_Exit ; no task switch
+
+ CBZ R1,SVC_Restore ; Runtask deleted?
+
+ PUSH {R2,R3}
+ MOV R3,#1
+ STRB R3,[R1,#TCB_RETUPD] ; os_tsk.run->ret_upd = 1
+ STMDB R12!,{R4-R11} ; Save Old context
+ STR R12,[R1,#TCB_TSTACK] ; Update os_tsk.run->tsk_stack
+ BL rt_stk_check ; Check for Stack overflow
+ POP {R2,R3}
+
+SVC_Restore
+ STR R2,[R3] ; os_tsk.run = os_tsk.new
+
+ LDR R12,[R2,#TCB_TSTACK] ; os_tsk.new->tsk_stack
+ LDMIA R12!,{R4-R11} ; Restore New Context
+ LDRB R3,[R2,#TCB_RETUPD] ; Update ret_val?
+ MSR PSP,R12 ; Write PSP
+
+ CBZ R3,SVC_Return
+ LDRB R0,[R2,#TCB_RETVAL] ; Write os_tsk.new->ret_val
+
+SVC_Exit
+ STR R0,[R12] ; Function return value
+
+SVC_Return
+ MVN LR,#:NOT:0xFFFFFFFD ; set EXC_RETURN value
+#ifdef IFX_XMC4XXX
+ PUSH {LR}
+ POP {PC}
+#else
+ BX LR
+#endif
+
+ /*------------------- User SVC ------------------------------*/
+
+SVC_User
+ PUSH {R4,LR} ; Save Registers
+ LDR R2,=SVC_Count
+ LDR R2,[R2]
+ CMP R1,R2
+ BHI SVC_Done ; Overflow
+
+ LDR R4,=SVC_Table-4
+ LDR R4,[R4,R1,LSL #2] ; Load SVC Function Address
+
+ LDM R0,{R0-R3,R12} ; Read R0-R3,R12 from stack
+ BLX R4 ; Call SVC Function
+
+ MRS R12,PSP
+ STM R12,{R0-R3} ; Function return values
+SVC_Done
+ POP {R4,PC} ; RETI
+
+ ALIGN
+}
+
+
+/*-------------------------- PendSV_Handler ---------------------------------*/
+
+__asm void PendSV_Handler (void) {
+ PRESERVE8
+
+#ifdef IFX_XMC4XXX
+ EXPORT PendSV_Handler_Veneer
+PendSV_Handler_Veneer
+#endif
+
+ BL __cpp(rt_pop_req)
+
+Sys_Switch
+ LDR R3,=__cpp(&os_tsk)
+ LDM R3,{R1,R2} ; os_tsk.run, os_tsk.new
+ CMP R1,R2
+ BEQ Sys_Exit
+
+ PUSH {R2,R3}
+ MOV R3,#0
+ STRB R3,[R1,#TCB_RETUPD] ; os_tsk.run->ret_upd = 0
+ MRS R12,PSP ; Read PSP
+ STMDB R12!,{R4-R11} ; Save Old context
+ STR R12,[R1,#TCB_TSTACK] ; Update os_tsk.run->tsk_stack
+ BL rt_stk_check ; Check for Stack overflow
+
+ POP {R2,R3}
+ STR R2,[R3] ; os_tsk.run = os_tsk.new
+
+ LDR R12,[R2,#TCB_TSTACK] ; os_tsk.new->tsk_stack
+ LDMIA R12!,{R4-R11} ; Restore New Context
+ MSR PSP,R12 ; Write PSP
+
+ LDRB R3,[R2,#TCB_RETUPD] ; Update ret_val?
+ CBZ R3,Sys_Exit
+ LDRB R3,[R2,#TCB_RETVAL] ; Write os_tsk.new->ret_val
+ STR R3,[R12]
+Sys_Exit
+ MVN LR,#:NOT:0xFFFFFFFD ; set EXC_RETURN value
+#ifdef IFX_XMC4XXX
+ PUSH {LR}
+ POP {PC}
+#else
+ BX LR ; Return to Thread Mode
+#endif
+
+ ALIGN
+}
+
+
+/*-------------------------- SysTick_Handler --------------------------------*/
+
+__asm void SysTick_Handler (void) {
+ PRESERVE8
+
+#ifdef IFX_XMC4XXX
+ EXPORT SysTick_Handler_Veneer
+SysTick_Handler_Veneer
+#endif
+
+ BL __cpp(rt_systick)
+ B Sys_Switch
+
+ ALIGN
+}
+
+
+/*-------------------------- OS_Tick_Handler --------------------------------*/
+
+__asm void OS_Tick_Handler (void) {
+ PRESERVE8
+
+ BL __cpp(os_tick_irqack)
+ BL __cpp(rt_systick)
+ B Sys_Switch
+
+ ALIGN
+}
+
+
+/*--------------------------- rt_init_stack ---------------------------------*/
+
+void rt_init_stack (P_TCB p_TCB, FUNCP task_body) {
+ /* Prepare TCB and saved context for a first time start of a task. */
+ U32 *stk,i,size;
+
+ /* Prepare a complete interrupt frame for first task start */
+ size = p_TCB->priv_stack >> 2;
+ if (size == 0) {
+ size = (U16)os_stackinfo >> 2;
+ }
+
+ /* Write to the top of stack. */
+ stk = &p_TCB->stack[size];
+
+ /* Auto correct to 8-byte ARM stack alignment. */
+ if ((U32)stk & 0x04) {
+ stk--;
+ }
+
+ stk -= 16;
+
+ /* Default xPSR and initial PC */
+ stk[15] = INITIAL_xPSR;
+ stk[14] = (U32)task_body;
+
+ /* Clear R1-R12,LR registers. */
+ for (i = 0; i < 14; i++) {
+ stk[i] = 0;
+ }
+
+ /* Assign a void pointer to R0. */
+ stk[8] = (U32)p_TCB->msg;
+
+ /* Initial Task stack pointer. */
+ p_TCB->tsk_stack = (U32)stk;
+
+ /* Task entry point. */
+ p_TCB->ptask = task_body;
+
+ /* Set a magic word for checking of stack overflow. */
+ p_TCB->stack[0] = MAGIC_WORD;
+}
+
+
+/*--------------------------- dbg_init --------------------------------------*/
+
+void dbg_init (void) {
+ if ((DEMCR & DEMCR_TRCENA) &&
+ (ITM_CONTROL & ITM_ITMENA) &&
+ (ITM_ENABLE & (1UL << 31))) {
+ dbg_msg = __TRUE;
+ }
+}
+
+
+/*--------------------------- dbg_task_notify -------------------------------*/
+
+void dbg_task_notify (P_TCB p_tcb, BOOL create) {
+ while (ITM_PORT31_U32 == 0);
+ ITM_PORT31_U32 = (U32)p_tcb->ptask;
+ while (ITM_PORT31_U32 == 0);
+ ITM_PORT31_U16 = (create << 8) | p_tcb->task_id;
+}
+
+
+/*--------------------------- dbg_task_switch -------------------------------*/
+
+void dbg_task_switch (U32 task_id) {
+ while (ITM_PORT31_U32 == 0);
+ ITM_PORT31_U8 = task_id;
+}
+
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
diff -r 000000000000 -r 01f31e923fe2 source/rtos/cm4/HAL_CM4.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/rtos/cm4/HAL_CM4.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,385 @@
+/**
+ * @file HAL_CM3.c
+ * @brief HAL for Cortex-M4
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_HAL_CM.h"
+#include "rt_Task.h"
+#include "rt_List.h"
+#include "rt_MemBox.h"
+
+
+/*----------------------------------------------------------------------------
+ * Global Variables
+ *---------------------------------------------------------------------------*/
+
+BIT dbg_msg;
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_set_PSP ------------------------------------*/
+
+__asm void rt_set_PSP (U32 stack) {
+ MSR PSP,R0
+ BX LR
+}
+
+
+/*--------------------------- rt_get_PSP ------------------------------------*/
+
+__asm U32 rt_get_PSP (void) {
+ MRS R0,PSP
+ BX LR
+}
+
+
+/*--------------------------- os_set_env ------------------------------------*/
+
+__asm void os_set_env (void) {
+ /* Switch to Unprivileged/Privileged Thread mode, use PSP. */
+ MOV R0,SP ; PSP = MSP
+ MSR PSP,R0
+ LDR R0,=__cpp(&os_flags)
+ LDRB R0,[R0]
+ LSLS R0,#31
+ MOVNE R0,#0x02 ; Privileged Thread mode, use PSP
+ MOVEQ R0,#0x03 ; Unprivileged Thread mode, use PSP
+ MSR CONTROL,R0
+ BX LR
+
+ ALIGN
+}
+
+
+/*--------------------------- _alloc_box ------------------------------------*/
+
+__asm void *_alloc_box (void *box_mem) {
+ /* Function wrapper for Unprivileged/Privileged mode. */
+ LDR R12,=__cpp(rt_alloc_box)
+ MRS R3,IPSR
+ LSLS R3,#24
+ BXNE R12
+ MRS R3,CONTROL
+ LSLS R3,#31
+ BXEQ R12
+ SVC 0
+ BX LR
+
+ ALIGN
+}
+
+
+/*--------------------------- _free_box -------------------------------------*/
+
+__asm int _free_box (void *box_mem, void *box) {
+ /* Function wrapper for Unprivileged/Privileged mode. */
+ LDR R12,=__cpp(rt_free_box)
+ MRS R3,IPSR
+ LSLS R3,#24
+ BXNE R12
+ MRS R3,CONTROL
+ LSLS R3,#31
+ BXEQ R12
+ SVC 0
+ BX LR
+
+ ALIGN
+}
+
+
+/*-------------------------- SVC_Handler ------------------------------------*/
+
+__asm void SVC_Handler (void) {
+ PRESERVE8
+
+#ifdef IFX_XMC4XXX
+ EXPORT SVC_Handler_Veneer
+SVC_Handler_Veneer
+#endif
+
+ IMPORT SVC_Count
+ IMPORT SVC_Table
+ IMPORT rt_stk_check
+
+ MRS R0,PSP ; Read PSP
+ LDR R1,[R0,#24] ; Read Saved PC from Stack
+ LDRB R1,[R1,#-2] ; Load SVC Number
+ CBNZ R1,SVC_User
+
+ PUSH {R4,LR} ; Save EXC_RETURN
+ LDM R0,{R0-R3,R12} ; Read R0-R3,R12 from stack
+ BLX R12 ; Call SVC Function
+ POP {R4,LR} ; Restore EXC_RETURN
+
+ MRS R12,PSP ; Read PSP
+ LDR R3,=__cpp(&os_tsk)
+ LDM R3,{R1,R2} ; os_tsk.run, os_tsk.new
+ CMP R1,R2
+ BEQ SVC_Exit ; no task switch
+
+ CBZ R1,SVC_Restore ; Runtask deleted?
+
+ PUSH {R2,R3}
+ TST LR,#0x10 ; is it extended frame?
+ VSTMDBEQ R12!,{S16-S31} ; yes, stack also VFP hi-regs
+ MOVEQ R3,#0x03 ; os_tsk->ret_upd val
+ MOVNE R3,#0x01
+
+ STRB R3,[R1,#TCB_RETUPD] ; os_tsk.run->ret_upd = val
+ STMDB R12!,{R4-R11} ; Save Old context
+ STR R12,[R1,#TCB_TSTACK] ; Update os_tsk.run->tsk_stack
+ BL rt_stk_check ; Check for Stack overflow
+ POP {R2,R3}
+
+SVC_Restore
+ STR R2,[R3] ; os_tsk.run = os_tsk.new
+
+ LDR R12,[R2,#TCB_TSTACK] ; os_tsk.new->tsk_stack
+ LDMIA R12!,{R4-R11} ; Restore New Context
+ LDRB R3,[R2,#TCB_RETUPD] ; Update ret_val?
+
+ TST R3,#0x02 ; VFP Active?
+ VLDMIANE R12!,{S16-S31} ; restore VFP hi-registers
+ MVNNE LR,#:NOT:0xFFFFFFED ; set EXC_RETURN value
+ MVNEQ LR,#:NOT:0xFFFFFFFD
+ MSR PSP,R12 ; Write PSP
+
+ TST R3,#0x01
+#ifdef IFX_XMC4XXX
+ PUSHEQ {LR}
+ POPEQ {PC}
+#else
+ BXEQ LR ; RETI
+#endif
+
+ LDRB R0,[R2,#TCB_RETVAL] ; Write os_tsk.new->ret_val
+SVC_Exit
+ STR R0,[R12] ; Function return value
+#ifdef IFX_XMC4XXX
+ PUSH {LR}
+ POP {PC}
+#else
+ BX LR
+#endif
+
+ /*------------------- User SVC ------------------------------*/
+
+SVC_User
+ PUSH {R4,LR} ; Save Registers
+ LDR R2,=SVC_Count
+ LDR R2,[R2]
+ CMP R1,R2
+ BHI SVC_Done ; Overflow
+
+ LDR R4,=SVC_Table-4
+ LDR R4,[R4,R1,LSL #2] ; Load SVC Function Address
+
+ LDM R0,{R0-R3,R12} ; Read R0-R3,R12 from stack
+ BLX R4 ; Call SVC Function
+
+ MRS R12,PSP
+ STM R12,{R0-R3} ; Function return values
+SVC_Done
+ POP {R4,PC} ; RETI
+
+ ALIGN
+}
+
+
+/*-------------------------- PendSV_Handler ---------------------------------*/
+
+__asm void PendSV_Handler (void) {
+ PRESERVE8
+
+#ifdef IFX_XMC4XXX
+ EXPORT PendSV_Handler_Veneer
+PendSV_Handler_Veneer
+#endif
+
+ PUSH {R4,LR} ; Save EXC_RETURN
+ BL __cpp(rt_pop_req)
+
+Sys_Switch
+ POP {R4,LR} ; Restore EXC_RETURN
+
+ LDR R3,=__cpp(&os_tsk)
+ LDM R3,{R1,R2} ; os_tsk.run, os_tsk.new
+ CMP R1,R2
+#ifdef IFX_XMC4XXX
+ PUSHEQ {LR}
+ POPEQ {PC}
+#else
+ BXEQ LR ; RETI, no task switch
+#endif
+
+ PUSH {R2,R3}
+ MRS R12,PSP ; Read PSP
+ TST LR,#0x10 ; is it extended frame?
+ VSTMDBEQ R12!,{S16-S31} ; yes, stack also VFP hi-regs
+ MOVEQ R3,#0x02 ; os_tsk->ret_upd val
+ MOVNE R3,#0x00
+
+ STRB R3,[R1,#TCB_RETUPD] ; os_tsk.run->ret_upd = 0
+ STMDB R12!,{R4-R11} ; Save Old context
+ STR R12,[R1,#TCB_TSTACK] ; Update os_tsk.run->tsk_stack
+ BL rt_stk_check ; Check for Stack overflow
+
+ POP {R2,R3}
+ STR R2,[R3] ; os_tsk.run = os_tsk.new
+
+ LDR R12,[R2,#TCB_TSTACK] ; os_tsk.new->tsk_stack
+ LDMIA R12!,{R4-R11} ; Restore New Context
+ LDRB R3,[R2,#TCB_RETUPD] ; Update ret_val?
+
+ TST R3,#0x02 ; VFP Active?
+ VLDMIANE R12!,{S16-S31} ; restore VFP hi-regs
+ MVNNE LR,#:NOT:0xFFFFFFED ; set EXC_RETURN value
+ MVNEQ LR,#:NOT:0xFFFFFFFD
+ MSR PSP,R12 ; Write PSP
+
+ TST R3,#0x01
+ LDRBNE R3,[R2,#TCB_RETVAL] ; Write os_tsk.new->ret_val
+ STRNE R3,[R12]
+#ifdef IFX_XMC4XXX
+ PUSH {LR}
+ POP {PC}
+#else
+ BX LR ; Return to Thread Mode
+#endif
+
+ ALIGN
+}
+
+
+/*-------------------------- SysTick_Handler --------------------------------*/
+
+__asm void SysTick_Handler (void) {
+ PRESERVE8
+
+#ifdef IFX_XMC4XXX
+ EXPORT SysTick_Handler_Veneer
+SysTick_Handler_Veneer
+#endif
+
+ PUSH {R4,LR} ; Save EXC_RETURN
+ BL __cpp(rt_systick)
+ B Sys_Switch
+
+ ALIGN
+}
+
+
+/*-------------------------- OS_Tick_Handler --------------------------------*/
+
+__asm void OS_Tick_Handler (void) {
+ PRESERVE8
+
+ PUSH {R4,LR} ; Save EXC_RETURN
+ BL __cpp(os_tick_irqack)
+ BL __cpp(rt_systick)
+ B Sys_Switch
+
+ ALIGN
+}
+
+
+/*--------------------------- rt_init_stack ---------------------------------*/
+
+void rt_init_stack (P_TCB p_TCB, FUNCP task_body) {
+ /* Prepare TCB and saved context for a first time start of a task. */
+ U32 *stk,i,size;
+
+ /* Prepare a complete interrupt frame for first task start */
+ size = p_TCB->priv_stack >> 2;
+ if (size == 0) {
+ size = (U16)os_stackinfo >> 2;
+ }
+
+ /* Write to the top of stack. */
+ stk = &p_TCB->stack[size];
+
+ /* Auto correct to 8-byte stack alignment. */
+ if ((U32)stk & 0x04) {
+ stk--;
+ }
+
+ stk -= 16;
+
+ /* Default xPSR and initial PC */
+ stk[15] = INITIAL_xPSR;
+ stk[14] = (U32)task_body;
+
+ /* Clear R1-R12,LR registers. */
+ for (i = 0; i < 14; i++) {
+ stk[i] = 0;
+ }
+
+ /* Assign a void pointer to R0. */
+ stk[8] = (U32)p_TCB->msg;
+
+ /* Initial Task stack pointer. */
+ p_TCB->tsk_stack = (U32)stk;
+
+ /* Task entry point. */
+ p_TCB->ptask = task_body;
+
+ /* Set a magic word for checking of stack overflow. */
+ p_TCB->stack[0] = MAGIC_WORD;
+}
+
+
+/*--------------------------- dbg_init --------------------------------------*/
+
+void dbg_init (void) {
+ if ((DEMCR & DEMCR_TRCENA) &&
+ (ITM_CONTROL & ITM_ITMENA) &&
+ (ITM_ENABLE & (1UL << 31))) {
+ dbg_msg = __TRUE;
+ }
+}
+
+
+/*--------------------------- dbg_task_notify -------------------------------*/
+
+void dbg_task_notify (P_TCB p_tcb, BOOL create) {
+ while (ITM_PORT31_U32 == 0);
+ ITM_PORT31_U32 = (U32)p_tcb->ptask;
+ while (ITM_PORT31_U32 == 0);
+ ITM_PORT31_U16 = (create << 8) | p_tcb->task_id;
+}
+
+
+/*--------------------------- dbg_task_switch -------------------------------*/
+
+void dbg_task_switch (U32 task_id) {
+ while (ITM_PORT31_U32 == 0);
+ ITM_PORT31_U8 = task_id;
+}
+
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
diff -r 000000000000 -r 01f31e923fe2 source/rtos/cmsis_os2.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/rtos/cmsis_os2.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,756 @@
+/*
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date: 18. June 2018
+ * $Revision: V2.1.3
+ *
+ * Project: CMSIS-RTOS2 API
+ * Title: cmsis_os2.h header file
+ *
+ * Version 2.1.3
+ * Additional functions allowed to be called from Interrupt Service Routines:
+ * - osThreadGetId
+ * Version 2.1.2
+ * Additional functions allowed to be called from Interrupt Service Routines:
+ * - osKernelGetInfo, osKernelGetState
+ * Version 2.1.1
+ * Additional functions allowed to be called from Interrupt Service Routines:
+ * - osKernelGetTickCount, osKernelGetTickFreq
+ * Changed Kernel Tick type to uint32_t:
+ * - updated: osKernelGetTickCount, osDelayUntil
+ * Version 2.1.0
+ * Support for critical and uncritical sections (nesting safe):
+ * - updated: osKernelLock, osKernelUnlock
+ * - added: osKernelRestoreLock
+ * Updated Thread and Event Flags:
+ * - changed flags parameter and return type from int32_t to uint32_t
+ * Version 2.0.0
+ * Initial Release
+ *---------------------------------------------------------------------------*/
+
+#ifndef CMSIS_OS2_H_
+#define CMSIS_OS2_H_
+
+#ifndef __NO_RETURN
+#if defined(__CC_ARM)
+#define __NO_RETURN __declspec(noreturn)
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#define __NO_RETURN __attribute__((__noreturn__))
+#elif defined(__GNUC__)
+#define __NO_RETURN __attribute__((__noreturn__))
+#elif defined(__ICCARM__)
+#define __NO_RETURN __noreturn
+#else
+#define __NO_RETURN
+#endif
+#endif
+
+#include <stdint.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+// ==== Enumerations, structures, defines ====
+
+/// Version information.
+typedef struct {
+ uint32_t api; ///< API version (major.minor.rev: mmnnnrrrr dec).
+ uint32_t kernel; ///< Kernel version (major.minor.rev: mmnnnrrrr dec).
+} osVersion_t;
+
+/// Kernel state.
+typedef enum {
+ osKernelInactive = 0, ///< Inactive.
+ osKernelReady = 1, ///< Ready.
+ osKernelRunning = 2, ///< Running.
+ osKernelLocked = 3, ///< Locked.
+ osKernelSuspended = 4, ///< Suspended.
+ osKernelError = -1, ///< Error.
+ osKernelReserved = 0x7FFFFFFFU ///< Prevents enum down-size compiler optimization.
+} osKernelState_t;
+
+/// Thread state.
+typedef enum {
+ osThreadInactive = 0, ///< Inactive.
+ osThreadReady = 1, ///< Ready.
+ osThreadRunning = 2, ///< Running.
+ osThreadBlocked = 3, ///< Blocked.
+ osThreadTerminated = 4, ///< Terminated.
+ osThreadError = -1, ///< Error.
+ osThreadReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
+} osThreadState_t;
+
+/// Priority values.
+typedef enum {
+ osPriorityNone = 0, ///< No priority (not initialized).
+ osPriorityIdle = 1, ///< Reserved for Idle thread.
+ osPriorityLow = 8, ///< Priority: low
+ osPriorityLow1 = 8+1, ///< Priority: low + 1
+ osPriorityLow2 = 8+2, ///< Priority: low + 2
+ osPriorityLow3 = 8+3, ///< Priority: low + 3
+ osPriorityLow4 = 8+4, ///< Priority: low + 4
+ osPriorityLow5 = 8+5, ///< Priority: low + 5
+ osPriorityLow6 = 8+6, ///< Priority: low + 6
+ osPriorityLow7 = 8+7, ///< Priority: low + 7
+ osPriorityBelowNormal = 16, ///< Priority: below normal
+ osPriorityBelowNormal1 = 16+1, ///< Priority: below normal + 1
+ osPriorityBelowNormal2 = 16+2, ///< Priority: below normal + 2
+ osPriorityBelowNormal3 = 16+3, ///< Priority: below normal + 3
+ osPriorityBelowNormal4 = 16+4, ///< Priority: below normal + 4
+ osPriorityBelowNormal5 = 16+5, ///< Priority: below normal + 5
+ osPriorityBelowNormal6 = 16+6, ///< Priority: below normal + 6
+ osPriorityBelowNormal7 = 16+7, ///< Priority: below normal + 7
+ osPriorityNormal = 24, ///< Priority: normal
+ osPriorityNormal1 = 24+1, ///< Priority: normal + 1
+ osPriorityNormal2 = 24+2, ///< Priority: normal + 2
+ osPriorityNormal3 = 24+3, ///< Priority: normal + 3
+ osPriorityNormal4 = 24+4, ///< Priority: normal + 4
+ osPriorityNormal5 = 24+5, ///< Priority: normal + 5
+ osPriorityNormal6 = 24+6, ///< Priority: normal + 6
+ osPriorityNormal7 = 24+7, ///< Priority: normal + 7
+ osPriorityAboveNormal = 32, ///< Priority: above normal
+ osPriorityAboveNormal1 = 32+1, ///< Priority: above normal + 1
+ osPriorityAboveNormal2 = 32+2, ///< Priority: above normal + 2
+ osPriorityAboveNormal3 = 32+3, ///< Priority: above normal + 3
+ osPriorityAboveNormal4 = 32+4, ///< Priority: above normal + 4
+ osPriorityAboveNormal5 = 32+5, ///< Priority: above normal + 5
+ osPriorityAboveNormal6 = 32+6, ///< Priority: above normal + 6
+ osPriorityAboveNormal7 = 32+7, ///< Priority: above normal + 7
+ osPriorityHigh = 40, ///< Priority: high
+ osPriorityHigh1 = 40+1, ///< Priority: high + 1
+ osPriorityHigh2 = 40+2, ///< Priority: high + 2
+ osPriorityHigh3 = 40+3, ///< Priority: high + 3
+ osPriorityHigh4 = 40+4, ///< Priority: high + 4
+ osPriorityHigh5 = 40+5, ///< Priority: high + 5
+ osPriorityHigh6 = 40+6, ///< Priority: high + 6
+ osPriorityHigh7 = 40+7, ///< Priority: high + 7
+ osPriorityRealtime = 48, ///< Priority: realtime
+ osPriorityRealtime1 = 48+1, ///< Priority: realtime + 1
+ osPriorityRealtime2 = 48+2, ///< Priority: realtime + 2
+ osPriorityRealtime3 = 48+3, ///< Priority: realtime + 3
+ osPriorityRealtime4 = 48+4, ///< Priority: realtime + 4
+ osPriorityRealtime5 = 48+5, ///< Priority: realtime + 5
+ osPriorityRealtime6 = 48+6, ///< Priority: realtime + 6
+ osPriorityRealtime7 = 48+7, ///< Priority: realtime + 7
+ osPriorityISR = 56, ///< Reserved for ISR deferred thread.
+ osPriorityError = -1, ///< System cannot determine priority or illegal priority.
+ osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
+} osPriority_t;
+
+/// Entry point of a thread.
+typedef void (*osThreadFunc_t) (void *argument);
+
+/// Timer callback function.
+typedef void (*osTimerFunc_t) (void *argument);
+
+/// Timer type.
+typedef enum {
+ osTimerOnce = 0, ///< One-shot timer.
+ osTimerPeriodic = 1 ///< Repeating timer.
+} osTimerType_t;
+
+// Timeout value.
+#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value.
+
+// Flags options (\ref osThreadFlagsWait and \ref osEventFlagsWait).
+#define osFlagsWaitAny 0x00000000U ///< Wait for any flag (default).
+#define osFlagsWaitAll 0x00000001U ///< Wait for all flags.
+#define osFlagsNoClear 0x00000002U ///< Do not clear flags which have been specified to wait for.
+
+// Flags errors (returned by osThreadFlagsXxxx and osEventFlagsXxxx).
+#define osFlagsError 0x80000000U ///< Error indicator.
+#define osFlagsErrorUnknown 0xFFFFFFFFU ///< osError (-1).
+#define osFlagsErrorTimeout 0xFFFFFFFEU ///< osErrorTimeout (-2).
+#define osFlagsErrorResource 0xFFFFFFFDU ///< osErrorResource (-3).
+#define osFlagsErrorParameter 0xFFFFFFFCU ///< osErrorParameter (-4).
+#define osFlagsErrorISR 0xFFFFFFFAU ///< osErrorISR (-6).
+
+// Thread attributes (attr_bits in \ref osThreadAttr_t).
+#define osThreadDetached 0x00000000U ///< Thread created in detached mode (default)
+#define osThreadJoinable 0x00000001U ///< Thread created in joinable mode
+
+// Mutex attributes (attr_bits in \ref osMutexAttr_t).
+#define osMutexRecursive 0x00000001U ///< Recursive mutex.
+#define osMutexPrioInherit 0x00000002U ///< Priority inherit protocol.
+#define osMutexRobust 0x00000008U ///< Robust mutex.
+
+/// Status code values returned by CMSIS-RTOS functions.
+typedef enum {
+ osOK = 0, ///< Operation completed successfully.
+ osError = -1, ///< Unspecified RTOS error: run-time error but no other error message fits.
+ osErrorTimeout = -2, ///< Operation not completed within the timeout period.
+ osErrorResource = -3, ///< Resource not available.
+ osErrorParameter = -4, ///< Parameter error.
+ osErrorNoMemory = -5, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation.
+ osErrorISR = -6, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines.
+ osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
+} osStatus_t;
+
+
+/// \details Thread ID identifies the thread.
+typedef void *osThreadId_t;
+
+/// \details Timer ID identifies the timer.
+typedef void *osTimerId_t;
+
+/// \details Event Flags ID identifies the event flags.
+typedef void *osEventFlagsId_t;
+
+/// \details Mutex ID identifies the mutex.
+typedef void *osMutexId_t;
+
+/// \details Semaphore ID identifies the semaphore.
+typedef void *osSemaphoreId_t;
+
+/// \details Memory Pool ID identifies the memory pool.
+typedef void *osMemoryPoolId_t;
+
+/// \details Message Queue ID identifies the message queue.
+typedef void *osMessageQueueId_t;
+
+
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+
+
+/// Attributes structure for thread.
+typedef struct {
+ const char *name; ///< name of the thread
+ uint32_t attr_bits; ///< attribute bits
+ void *cb_mem; ///< memory for control block
+ uint32_t cb_size; ///< size of provided memory for control block
+ void *stack_mem; ///< memory for stack
+ uint32_t stack_size; ///< size of stack
+ osPriority_t priority; ///< initial thread priority (default: osPriorityNormal)
+ TZ_ModuleId_t tz_module; ///< TrustZone module identifier
+ uint32_t reserved; ///< reserved (must be 0)
+} osThreadAttr_t;
+
+/// Attributes structure for timer.
+typedef struct {
+ const char *name; ///< name of the timer
+ uint32_t attr_bits; ///< attribute bits
+ void *cb_mem; ///< memory for control block
+ uint32_t cb_size; ///< size of provided memory for control block
+} osTimerAttr_t;
+
+/// Attributes structure for event flags.
+typedef struct {
+ const char *name; ///< name of the event flags
+ uint32_t attr_bits; ///< attribute bits
+ void *cb_mem; ///< memory for control block
+ uint32_t cb_size; ///< size of provided memory for control block
+} osEventFlagsAttr_t;
+
+/// Attributes structure for mutex.
+typedef struct {
+ const char *name; ///< name of the mutex
+ uint32_t attr_bits; ///< attribute bits
+ void *cb_mem; ///< memory for control block
+ uint32_t cb_size; ///< size of provided memory for control block
+} osMutexAttr_t;
+
+/// Attributes structure for semaphore.
+typedef struct {
+ const char *name; ///< name of the semaphore
+ uint32_t attr_bits; ///< attribute bits
+ void *cb_mem; ///< memory for control block
+ uint32_t cb_size; ///< size of provided memory for control block
+} osSemaphoreAttr_t;
+
+/// Attributes structure for memory pool.
+typedef struct {
+ const char *name; ///< name of the memory pool
+ uint32_t attr_bits; ///< attribute bits
+ void *cb_mem; ///< memory for control block
+ uint32_t cb_size; ///< size of provided memory for control block
+ void *mp_mem; ///< memory for data storage
+ uint32_t mp_size; ///< size of provided memory for data storage
+} osMemoryPoolAttr_t;
+
+/// Attributes structure for message queue.
+typedef struct {
+ const char *name; ///< name of the message queue
+ uint32_t attr_bits; ///< attribute bits
+ void *cb_mem; ///< memory for control block
+ uint32_t cb_size; ///< size of provided memory for control block
+ void *mq_mem; ///< memory for data storage
+ uint32_t mq_size; ///< size of provided memory for data storage
+} osMessageQueueAttr_t;
+
+
+// ==== Kernel Management Functions ====
+
+/// Initialize the RTOS Kernel.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osKernelInitialize (void);
+
+/// Get RTOS Kernel Information.
+/// \param[out] version pointer to buffer for retrieving version information.
+/// \param[out] id_buf pointer to buffer for retrieving kernel identification string.
+/// \param[in] id_size size of buffer for kernel identification string.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size);
+
+/// Get the current RTOS Kernel state.
+/// \return current RTOS Kernel state.
+osKernelState_t osKernelGetState (void);
+
+/// Start the RTOS Kernel scheduler.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osKernelStart (void);
+
+/// Lock the RTOS Kernel scheduler.
+/// \return previous lock state (1 - locked, 0 - not locked, error code if negative).
+int32_t osKernelLock (void);
+
+/// Unlock the RTOS Kernel scheduler.
+/// \return previous lock state (1 - locked, 0 - not locked, error code if negative).
+int32_t osKernelUnlock (void);
+
+/// Restore the RTOS Kernel scheduler lock state.
+/// \param[in] lock lock state obtained by \ref osKernelLock or \ref osKernelUnlock.
+/// \return new lock state (1 - locked, 0 - not locked, error code if negative).
+int32_t osKernelRestoreLock (int32_t lock);
+
+/// Suspend the RTOS Kernel scheduler.
+/// \return time in ticks, for how long the system can sleep or power-down.
+uint32_t osKernelSuspend (void);
+
+/// Resume the RTOS Kernel scheduler.
+/// \param[in] sleep_ticks time in ticks for how long the system was in sleep or power-down mode.
+void osKernelResume (uint32_t sleep_ticks);
+
+/// Get the RTOS kernel tick count.
+/// \return RTOS kernel current tick count.
+uint32_t osKernelGetTickCount (void);
+
+/// Get the RTOS kernel tick frequency.
+/// \return frequency of the kernel tick in hertz, i.e. kernel ticks per second.
+uint32_t osKernelGetTickFreq (void);
+
+/// Get the RTOS kernel system timer count.
+/// \return RTOS kernel current system timer count as 32-bit value.
+uint32_t osKernelGetSysTimerCount (void);
+
+/// Get the RTOS kernel system timer frequency.
+/// \return frequency of the system timer in hertz, i.e. timer ticks per second.
+uint32_t osKernelGetSysTimerFreq (void);
+
+
+// ==== Thread Management Functions ====
+
+/// Create a thread and add it to Active Threads.
+/// \param[in] func thread function.
+/// \param[in] argument pointer that is passed to the thread function as start argument.
+/// \param[in] attr thread attributes; NULL: default values.
+/// \return thread ID for reference by other functions or NULL in case of error.
+osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr);
+
+/// Get name of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return name as null-terminated string.
+const char *osThreadGetName (osThreadId_t thread_id);
+
+/// Return the thread ID of the current running thread.
+/// \return thread ID for reference by other functions or NULL in case of error.
+osThreadId_t osThreadGetId (void);
+
+/// Get current thread state of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return current thread state of the specified thread.
+osThreadState_t osThreadGetState (osThreadId_t thread_id);
+
+/// Get stack size of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return stack size in bytes.
+uint32_t osThreadGetStackSize (osThreadId_t thread_id);
+
+/// Get available stack space of a thread based on stack watermark recording during execution.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return remaining stack space in bytes.
+uint32_t osThreadGetStackSpace (osThreadId_t thread_id);
+
+/// Change priority of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \param[in] priority new priority value for the thread function.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority);
+
+/// Get current priority of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return current priority value of the specified thread.
+osPriority_t osThreadGetPriority (osThreadId_t thread_id);
+
+/// Pass control to next thread that is in state \b READY.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadYield (void);
+
+/// Suspend execution of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadSuspend (osThreadId_t thread_id);
+
+/// Resume execution of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadResume (osThreadId_t thread_id);
+
+/// Detach a thread (thread storage can be reclaimed when thread terminates).
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadDetach (osThreadId_t thread_id);
+
+/// Wait for specified thread to terminate.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadJoin (osThreadId_t thread_id);
+
+/// Terminate execution of current running thread.
+__NO_RETURN void osThreadExit (void);
+
+/// Terminate execution of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadTerminate (osThreadId_t thread_id);
+
+/// Get number of active threads.
+/// \return number of active threads.
+uint32_t osThreadGetCount (void);
+
+/// Enumerate active threads.
+/// \param[out] thread_array pointer to array for retrieving thread IDs.
+/// \param[in] array_items maximum number of items in array for retrieving thread IDs.
+/// \return number of enumerated threads.
+uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items);
+
+
+// ==== Thread Flags Functions ====
+
+/// Set the specified Thread Flags of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \param[in] flags specifies the flags of the thread that shall be set.
+/// \return thread flags after setting or error code if highest bit set.
+uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags);
+
+/// Clear the specified Thread Flags of current running thread.
+/// \param[in] flags specifies the flags of the thread that shall be cleared.
+/// \return thread flags before clearing or error code if highest bit set.
+uint32_t osThreadFlagsClear (uint32_t flags);
+
+/// Get the current Thread Flags of current running thread.
+/// \return current thread flags.
+uint32_t osThreadFlagsGet (void);
+
+/// Wait for one or more Thread Flags of the current running thread to become signaled.
+/// \param[in] flags specifies the flags to wait for.
+/// \param[in] options specifies flags options (osFlagsXxxx).
+/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return thread flags before clearing or error code if highest bit set.
+uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout);
+
+
+// ==== Generic Wait Functions ====
+
+/// Wait for Timeout (Time Delay).
+/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value
+/// \return status code that indicates the execution status of the function.
+osStatus_t osDelay (uint32_t ticks);
+
+/// Wait until specified time.
+/// \param[in] ticks absolute time in ticks
+/// \return status code that indicates the execution status of the function.
+osStatus_t osDelayUntil (uint32_t ticks);
+
+
+// ==== Timer Management Functions ====
+
+/// Create and Initialize a timer.
+/// \param[in] func function pointer to callback function.
+/// \param[in] type \ref osTimerOnce for one-shot or \ref osTimerPeriodic for periodic behavior.
+/// \param[in] argument argument to the timer callback function.
+/// \param[in] attr timer attributes; NULL: default values.
+/// \return timer ID for reference by other functions or NULL in case of error.
+osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr);
+
+/// Get name of a timer.
+/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
+/// \return name as null-terminated string.
+const char *osTimerGetName (osTimerId_t timer_id);
+
+/// Start or restart a timer.
+/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
+/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value of the timer.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks);
+
+/// Stop a timer.
+/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osTimerStop (osTimerId_t timer_id);
+
+/// Check if a timer is running.
+/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
+/// \return 0 not running, 1 running.
+uint32_t osTimerIsRunning (osTimerId_t timer_id);
+
+/// Delete a timer.
+/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osTimerDelete (osTimerId_t timer_id);
+
+
+// ==== Event Flags Management Functions ====
+
+/// Create and Initialize an Event Flags object.
+/// \param[in] attr event flags attributes; NULL: default values.
+/// \return event flags ID for reference by other functions or NULL in case of error.
+osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr);
+
+/// Get name of an Event Flags object.
+/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
+/// \return name as null-terminated string.
+const char *osEventFlagsGetName (osEventFlagsId_t ef_id);
+
+/// Set the specified Event Flags.
+/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
+/// \param[in] flags specifies the flags that shall be set.
+/// \return event flags after setting or error code if highest bit set.
+uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags);
+
+/// Clear the specified Event Flags.
+/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
+/// \param[in] flags specifies the flags that shall be cleared.
+/// \return event flags before clearing or error code if highest bit set.
+uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags);
+
+/// Get the current Event Flags.
+/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
+/// \return current event flags.
+uint32_t osEventFlagsGet (osEventFlagsId_t ef_id);
+
+/// Wait for one or more Event Flags to become signaled.
+/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
+/// \param[in] flags specifies the flags to wait for.
+/// \param[in] options specifies flags options (osFlagsXxxx).
+/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return event flags before clearing or error code if highest bit set.
+uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout);
+
+/// Delete an Event Flags object.
+/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id);
+
+
+// ==== Mutex Management Functions ====
+
+/// Create and Initialize a Mutex object.
+/// \param[in] attr mutex attributes; NULL: default values.
+/// \return mutex ID for reference by other functions or NULL in case of error.
+osMutexId_t osMutexNew (const osMutexAttr_t *attr);
+
+/// Get name of a Mutex object.
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
+/// \return name as null-terminated string.
+const char *osMutexGetName (osMutexId_t mutex_id);
+
+/// Acquire a Mutex or timeout if it is locked.
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
+/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout);
+
+/// Release a Mutex that was acquired by \ref osMutexAcquire.
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMutexRelease (osMutexId_t mutex_id);
+
+/// Get Thread which owns a Mutex object.
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
+/// \return thread ID of owner thread or NULL when mutex was not acquired.
+osThreadId_t osMutexGetOwner (osMutexId_t mutex_id);
+
+/// Delete a Mutex object.
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMutexDelete (osMutexId_t mutex_id);
+
+
+// ==== Semaphore Management Functions ====
+
+/// Create and Initialize a Semaphore object.
+/// \param[in] max_count maximum number of available tokens.
+/// \param[in] initial_count initial number of available tokens.
+/// \param[in] attr semaphore attributes; NULL: default values.
+/// \return semaphore ID for reference by other functions or NULL in case of error.
+osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr);
+
+/// Get name of a Semaphore object.
+/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
+/// \return name as null-terminated string.
+const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id);
+
+/// Acquire a Semaphore token or timeout if no tokens are available.
+/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
+/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout);
+
+/// Release a Semaphore token up to the initial maximum count.
+/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id);
+
+/// Get current Semaphore token count.
+/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
+/// \return number of tokens available.
+uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id);
+
+/// Delete a Semaphore object.
+/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id);
+
+
+// ==== Memory Pool Management Functions ====
+
+/// Create and Initialize a Memory Pool object.
+/// \param[in] block_count maximum number of memory blocks in memory pool.
+/// \param[in] block_size memory block size in bytes.
+/// \param[in] attr memory pool attributes; NULL: default values.
+/// \return memory pool ID for reference by other functions or NULL in case of error.
+osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr);
+
+/// Get name of a Memory Pool object.
+/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return name as null-terminated string.
+const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id);
+
+/// Allocate a memory block from a Memory Pool.
+/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
+/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return address of the allocated memory block or NULL in case of no memory is available.
+void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout);
+
+/// Return an allocated memory block back to a Memory Pool.
+/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
+/// \param[in] block address of the allocated memory block to be returned to the memory pool.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block);
+
+/// Get maximum number of memory blocks in a Memory Pool.
+/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return maximum number of memory blocks.
+uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id);
+
+/// Get memory block size in a Memory Pool.
+/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return memory block size in bytes.
+uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id);
+
+/// Get number of memory blocks used in a Memory Pool.
+/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return number of memory blocks used.
+uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id);
+
+/// Get number of memory blocks available in a Memory Pool.
+/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return number of memory blocks available.
+uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id);
+
+/// Delete a Memory Pool object.
+/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id);
+
+
+// ==== Message Queue Management Functions ====
+
+/// Create and Initialize a Message Queue object.
+/// \param[in] msg_count maximum number of messages in queue.
+/// \param[in] msg_size maximum message size in bytes.
+/// \param[in] attr message queue attributes; NULL: default values.
+/// \return message queue ID for reference by other functions or NULL in case of error.
+osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr);
+
+/// Get name of a Message Queue object.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \return name as null-terminated string.
+const char *osMessageQueueGetName (osMessageQueueId_t mq_id);
+
+/// Put a Message into a Queue or timeout if Queue is full.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \param[in] msg_ptr pointer to buffer with message to put into a queue.
+/// \param[in] msg_prio message priority.
+/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout);
+
+/// Get a Message from a Queue or timeout if Queue is empty.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \param[out] msg_ptr pointer to buffer for message to get from a queue.
+/// \param[out] msg_prio pointer to buffer for message priority or NULL.
+/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout);
+
+/// Get maximum number of messages in a Message Queue.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \return maximum number of messages.
+uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id);
+
+/// Get maximum message size in a Memory Pool.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \return maximum message size in bytes.
+uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id);
+
+/// Get number of queued messages in a Message Queue.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \return number of queued messages.
+uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id);
+
+/// Get number of available slots for messages in a Message Queue.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \return number of available slots for messages.
+uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id);
+
+/// Reset a Message Queue to initial empty state.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id);
+
+/// Delete a Message Queue object.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // CMSIS_OS2_H_
diff -r 000000000000 -r 01f31e923fe2 source/rtos/cmsis_os2_port.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/rtos/cmsis_os2_port.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,141 @@
+/**
+ * @file cmsis_os2_port.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "cmsis_os2.h"
+#include "RTL.h"
+#include "cortex_m.h"
+
+#define MAIN_TASK_PRIORITY (10)
+#define MAIN_TASK_STACK (800)
+static uint64_t stk_main_task [MAIN_TASK_STACK / sizeof(uint64_t)];
+
+#define TIMER_TASK_30_PRIORITY (11)
+#define TIMER_TASK_STACK (136)
+static uint64_t stk_timer_task[TIMER_TASK_STACK / sizeof(uint64_t)];
+
+static uint32_t taskCount = 0;
+static osTimerFunc_t onlyTimerFunction = NULL;
+static uint32_t timerTick = 0;
+
+static OS_MUT onlyMutex;
+
+osStatus_t osKernelInitialize(void)
+{
+ taskCount = 0;
+ return osOK;
+}
+
+osThreadId_t osThreadNew(osThreadFunc_t func, void *argument, const osThreadAttr_t *attr)
+{
+ OS_TID tid = 0;
+ //first task will init the rtx
+ if (taskCount == 0) {
+ os_sys_init_user((void (*)(void))func, MAIN_TASK_PRIORITY, stk_main_task, MAIN_TASK_STACK);
+ }
+ else {
+ tid = os_tsk_create((void (*)(void))func, MAIN_TASK_PRIORITY+1);
+ }
+ taskCount++;
+ return (osThreadId_t) tid;
+}
+
+uint32_t osThreadFlagsSet(osThreadId_t thread_id, uint32_t flags)
+{
+ if (cortex_in_isr()){
+ isr_evt_set(flags, (OS_TID)thread_id);
+ }else {
+ os_evt_set(flags, (OS_TID)thread_id);
+ }
+ return flags;
+}
+
+osStatus_t osKernelStart(void)
+{
+ //first thread already started the kernel
+ return osOK;
+}
+
+// Timer task
+static void rt_timer_task(void)
+{
+ os_itv_set(timerTick);
+ while (1) {
+ os_itv_wait();
+ if (onlyTimerFunction) {
+ onlyTimerFunction(NULL);
+ }
+ }
+}
+
+osTimerId_t osTimerNew(osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr)
+{
+ OS_TID tid = 0;
+ onlyTimerFunction = func;
+ return (osTimerId_t)tid;
+}
+
+osStatus_t osTimerStart(osTimerId_t timer_id, uint32_t ticks)
+{
+ timerTick = ticks;
+ OS_TID tid = os_tsk_create_user(rt_timer_task, TIMER_TASK_30_PRIORITY, (void *)stk_timer_task, TIMER_TASK_STACK);
+ return osOK;
+}
+
+uint32_t osThreadFlagsWait(uint32_t flags, uint32_t options, uint32_t timeout)
+{
+ os_evt_wait_or(flags, timeout);
+ return os_evt_get();
+}
+
+osMutexId_t osMutexNew(const osMutexAttr_t *attr)
+{
+ os_mut_init(onlyMutex);
+ return (osMutexId_t)onlyMutex;
+}
+
+osStatus_t osMutexAcquire(osMutexId_t mutex_id, uint32_t timeout)
+{
+ os_mut_wait((OS_ID)mutex_id, timeout);
+ return osOK;
+}
+
+osStatus_t osMutexRelease(osMutexId_t mutex_id)
+{
+ os_mut_release((OS_ID)mutex_id);
+ return osOK;
+}
+
+osThreadId_t osThreadGetId(void)
+{
+ return (osThreadId_t)os_tsk_self();
+}
+
+osStatus_t osDelay(uint32_t ticks)
+{
+ os_dly_wait(ticks);
+ return osOK;
+}
+
+uint32_t osKernelGetSysTimerCount(void)
+{
+ return os_time_get();
+}
+
diff -r 000000000000 -r 01f31e923fe2 source/rtos/rt_Event.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/rtos/rt_Event.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,169 @@
+/**
+ * @file rt_Event.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_Event.h"
+#include "rt_List.h"
+#include "rt_Task.h"
+
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_evt_wait -----------------------------------*/
+
+OS_RESULT rt_evt_wait (U16 wait_flags, U16 timeout, BOOL and_wait) {
+ /* Wait for one or more event flags with optional time-out. */
+ /* "wait_flags" identifies the flags to wait for. */
+ /* "timeout" is the time-out limit in system ticks (0xffff if no time-out) */
+ /* "and_wait" specifies the AND-ing of "wait_flags" as condition to be met */
+ /* to complete the wait. (OR-ing if set to 0). */
+ U32 block_state;
+
+ if (and_wait) {
+ /* Check for AND-connected events */
+ if ((os_tsk.run->events & wait_flags) == wait_flags) {
+ os_tsk.run->events &= ~wait_flags;
+ return (OS_R_EVT);
+ }
+ block_state = WAIT_AND;
+ }
+ else {
+ /* Check for OR-connected events */
+ if (os_tsk.run->events & wait_flags) {
+ os_tsk.run->waits = os_tsk.run->events & wait_flags;
+ os_tsk.run->events &= ~wait_flags;
+ return (OS_R_EVT);
+ }
+ block_state = WAIT_OR;
+ }
+ /* Task has to wait */
+ os_tsk.run->waits = wait_flags;
+ rt_block (timeout, (U8)block_state);
+ return (OS_R_TMO);
+}
+
+
+/*--------------------------- rt_evt_set ------------------------------------*/
+
+void rt_evt_set (U16 event_flags, OS_TID task_id) {
+ /* Set one or more event flags of a selectable task. */
+ P_TCB p_tcb;
+
+ p_tcb = os_active_TCB[task_id-1];
+ if (p_tcb == NULL) {
+ return;
+ }
+ p_tcb->events |= event_flags;
+ event_flags = p_tcb->waits;
+ /* If the task is not waiting for an event, it should not be put */
+ /* to ready state. */
+ if (p_tcb->state == WAIT_AND) {
+ /* Check for AND-connected events */
+ if ((p_tcb->events & event_flags) == event_flags) {
+ goto wkup;
+ }
+ }
+ if (p_tcb->state == WAIT_OR) {
+ /* Check for OR-connected events */
+ if (p_tcb->events & event_flags) {
+ p_tcb->waits &= p_tcb->events;
+wkup: p_tcb->events &= ~event_flags;
+ rt_rmv_dly (p_tcb);
+ p_tcb->events &= ~event_flags;
+ p_tcb->state = READY;
+ p_tcb->ret_val = OS_R_EVT;
+ rt_dispatch (p_tcb);
+ }
+ }
+}
+
+
+/*--------------------------- rt_evt_clr ------------------------------------*/
+
+void rt_evt_clr (U16 clear_flags, OS_TID task_id) {
+ /* Clear one or more event flags (identified by "clear_flags") of a */
+ /* selectable task (identified by "task"). */
+ P_TCB task = os_active_TCB[task_id-1];
+
+ if (task == NULL) {
+ return;
+ }
+ task->events &= ~clear_flags;
+}
+
+
+/*--------------------------- isr_evt_set -----------------------------------*/
+
+void isr_evt_set (U16 event_flags, OS_TID task_id) {
+ /* Same function as "os_evt_set", but to be called by ISRs. */
+ P_TCB p_tcb = os_active_TCB[task_id-1];
+
+ if (p_tcb == NULL) {
+ return;
+ }
+ rt_psq_enq (p_tcb, event_flags);
+ rt_psh_req ();
+}
+
+
+/*--------------------------- rt_evt_get ------------------------------------*/
+
+U16 rt_evt_get (void) {
+ /* Get events of a running task after waiting for OR connected events. */
+ return (os_tsk.run->waits);
+}
+
+
+/*--------------------------- rt_evt_psh ------------------------------------*/
+
+void rt_evt_psh (P_TCB p_CB, U16 set_flags) {
+ /* Check if task has to be waken up */
+ U16 event_flags;
+
+ p_CB->events |= set_flags;
+ event_flags = p_CB->waits;
+ if (p_CB->state == WAIT_AND) {
+ /* Check for AND-connected events */
+ if ((p_CB->events & event_flags) == event_flags) {
+ goto rdy;
+ }
+ }
+ if (p_CB->state == WAIT_OR) {
+ /* Check for OR-connected events */
+ if (p_CB->events & event_flags) {
+ p_CB->waits &= p_CB->events;
+rdy: p_CB->events &= ~event_flags;
+ rt_rmv_dly (p_CB);
+ p_CB->state = READY;
+ p_CB->ret_val = OS_R_EVT;
+ rt_put_prio (&os_rdy, p_CB);
+ }
+ }
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff -r 000000000000 -r 01f31e923fe2 source/rtos/rt_Event.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/rtos/rt_Event.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,33 @@ +/** + * @file rt_Event.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Functions */ +extern OS_RESULT rt_evt_wait (U16 wait_flags, U16 timeout, BOOL and_wait); +extern void rt_evt_set (U16 event_flags, OS_TID task_id); +extern void rt_evt_clr (U16 clear_flags, OS_TID task_id); +extern void isr_evt_set (U16 event_flags, OS_TID task_id); +extern U16 rt_evt_get (void); +extern void rt_evt_psh (P_TCB p_CB, U16 set_flags); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ +
diff -r 000000000000 -r 01f31e923fe2 source/rtos/rt_HAL_CM.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/rtos/rt_HAL_CM.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,169 @@
+/**
+ * @file rt_HAL_CM.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Definitions */
+#define INITIAL_xPSR 0x01000000
+#define DEMCR_TRCENA 0x01000000
+#define ITM_ITMENA 0x00000001
+#define MAGIC_WORD 0xE25A2EA5
+
+// ARMCC has deprecated use for ldrex and strex functions
+// from C so do not used them on any devices.
+#if (0)
+ #define __USE_EXCLUSIVE_ACCESS
+#else
+ #undef __USE_EXCLUSIVE_ACCESS
+#endif
+
+/* NVIC registers */
+#define NVIC_ST_CTRL (*((volatile U32 *)0xE000E010))
+#define NVIC_ST_RELOAD (*((volatile U32 *)0xE000E014))
+#define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018))
+#define NVIC_ISER ((volatile U32 *)0xE000E100)
+#define NVIC_ICER ((volatile U32 *)0xE000E180)
+#if (__TARGET_ARCH_6S_M)
+#define NVIC_IP ((volatile U32 *)0xE000E400)
+#else
+#define NVIC_IP ((volatile U8 *)0xE000E400)
+#endif
+#define NVIC_INT_CTRL (*((volatile U32 *)0xE000ED04))
+#define NVIC_AIR_CTRL (*((volatile U32 *)0xE000ED0C))
+#define NVIC_SYS_PRI2 (*((volatile U32 *)0xE000ED1C))
+#define NVIC_SYS_PRI3 (*((volatile U32 *)0xE000ED20))
+
+#define OS_PEND_IRQ() NVIC_INT_CTRL = (1<<28)
+#define OS_PENDING ((NVIC_INT_CTRL >> 26) & (1<<2 | 1))
+#define OS_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_PENDING) << 25
+#define OS_PEND(fl,p) NVIC_INT_CTRL = (fl | p<<2) << 26
+#define OS_LOCK() NVIC_ST_CTRL = 0x0005
+#define OS_UNLOCK() NVIC_ST_CTRL = 0x0007
+
+#define OS_X_PENDING ((NVIC_INT_CTRL >> 28) & 1)
+#define OS_X_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_X_PENDING) << 27
+#define OS_X_PEND(fl,p) NVIC_INT_CTRL = (fl | p) << 28
+#if (__TARGET_ARCH_6S_M)
+#define OS_X_INIT(n) NVIC_IP[n>>2] |= 0xFF << (8*(n & 0x03)); \
+ NVIC_ISER[n>>5] = 1 << (n & 0x1F)
+#else
+#define OS_X_INIT(n) NVIC_IP[n] = 0xFF; \
+ NVIC_ISER[n>>5] = 1 << (n & 0x1F)
+#endif
+#define OS_X_LOCK(n) NVIC_ICER[n>>5] = 1 << (n & 0x1F)
+#define OS_X_UNLOCK(n) NVIC_ISER[n>>5] = 1 << (n & 0x1F)
+
+/* Core Debug registers */
+#define DEMCR (*((volatile U32 *)0xE000EDFC))
+
+/* ITM registers */
+#define ITM_CONTROL (*((volatile U32 *)0xE0000E80))
+#define ITM_ENABLE (*((volatile U32 *)0xE0000E00))
+#define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078))
+#define ITM_PORT31_U32 (*((volatile U32 *)0xE000007C))
+#define ITM_PORT31_U16 (*((volatile U16 *)0xE000007C))
+#define ITM_PORT31_U8 (*((volatile U8 *)0xE000007C))
+
+/* Variables */
+extern BIT dbg_msg;
+
+/* Functions */
+#ifdef __USE_EXCLUSIVE_ACCESS
+ #define rt_inc(p) while(__strex((__ldrex(p)+1),p))
+ #define rt_dec(p) while(__strex((__ldrex(p)-1),p))
+#else
+ #define rt_inc(p) __disable_irq();(*p)++;__enable_irq();
+ #define rt_dec(p) __disable_irq();(*p)--;__enable_irq();
+#endif
+
+static inline U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
+ U32 cnt,c2;
+#ifdef __USE_EXCLUSIVE_ACCESS
+ do {
+ if ((cnt = __ldrex(count)) == size) {
+ __clrex();
+ return (cnt); }
+ } while (__strex(cnt+1, count));
+ do {
+ c2 = (cnt = __ldrex(first)) + 1;
+ if (c2 == size) c2 = 0;
+ } while (__strex(c2, first));
+#else
+ __disable_irq();
+ if ((cnt = *count) < size) {
+ *count = cnt+1;
+ c2 = (cnt = *first) + 1;
+ if (c2 == size) c2 = 0;
+ *first = c2;
+ }
+ __enable_irq ();
+#endif
+ return (cnt);
+}
+
+static inline void rt_systick_init (void) {
+ NVIC_ST_RELOAD = os_trv;
+ NVIC_ST_CURRENT = 0;
+ NVIC_ST_CTRL = 0x0007;
+ NVIC_SYS_PRI3 |= 0xFF000000;
+}
+
+static inline void rt_svc_init (void) {
+#if !(__TARGET_ARCH_6S_M)
+ int sh,prigroup;
+#endif
+ NVIC_SYS_PRI3 |= 0x00FF0000;
+#if (__TARGET_ARCH_6S_M)
+ NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000;
+#else
+ sh = 8 - __clz (~((NVIC_SYS_PRI3 << 8) & 0xFF000000));
+ prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07);
+ if (prigroup >= sh) {
+ sh = prigroup + 1;
+ }
+ NVIC_SYS_PRI2 = ((0xFEFFFFFF << sh) & 0xFF000000) | (NVIC_SYS_PRI2 & 0x00FFFFFF);
+#endif
+}
+
+extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
+extern void rt_set_PSP (U32 stack);
+extern U32 rt_get_PSP (void);
+extern void os_set_env (void);
+extern void *_alloc_box (void *box_mem);
+extern int _free_box (void *box_mem, void *box);
+
+extern void dbg_init (void);
+extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
+extern void dbg_task_switch (U32 task_id);
+
+#ifdef DBG_MSG
+#define DBG_INIT() dbg_init()
+#define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
+#define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new!=os_tsk.run)) \
+ dbg_task_switch(task_id)
+#else
+#define DBG_INIT()
+#define DBG_TASK_NOTIFY(p_tcb,create)
+#define DBG_TASK_SWITCH(task_id)
+#endif
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
diff -r 000000000000 -r 01f31e923fe2 source/rtos/rt_List.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/rtos/rt_List.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,308 @@
+/**
+ * @file rt_List.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_List.h"
+#include "rt_Task.h"
+#include "rt_Time.h"
+#include "rt_HAL_CM.h"
+
+/*----------------------------------------------------------------------------
+ * Global Variables
+ *---------------------------------------------------------------------------*/
+
+/* List head of chained ready tasks */
+struct OS_XCB os_rdy;
+/* List head of chained delay tasks */
+struct OS_XCB os_dly;
+
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_put_prio -----------------------------------*/
+
+void rt_put_prio (P_XCB p_CB, P_TCB p_task) {
+ /* Put task identified with "p_task" into list ordered by priority. */
+ /* "p_CB" points to head of list; list has always an element at end with */
+ /* a priority less than "p_task->prio". */
+ P_TCB p_CB2;
+ U32 prio;
+ BOOL sem_mbx = __FALSE;
+
+ if (p_CB->cb_type == SCB || p_CB->cb_type == MCB || p_CB->cb_type == MUCB) {
+ sem_mbx = __TRUE;
+ }
+ prio = p_task->prio;
+ p_CB2 = p_CB->p_lnk;
+ /* Search for an entry in the list */
+ while (p_CB2 != NULL && prio <= p_CB2->prio) {
+ p_CB = (P_XCB)p_CB2;
+ p_CB2 = p_CB2->p_lnk;
+ }
+ /* Entry found, insert the task into the list */
+ p_task->p_lnk = p_CB2;
+ p_CB->p_lnk = p_task;
+ if (sem_mbx) {
+ if (p_CB2 != NULL) {
+ p_CB2->p_rlnk = p_task;
+ }
+ p_task->p_rlnk = (P_TCB)p_CB;
+ }
+ else {
+ p_task->p_rlnk = NULL;
+ }
+}
+
+
+/*--------------------------- rt_get_first ----------------------------------*/
+
+P_TCB rt_get_first (P_XCB p_CB) {
+ /* Get task at head of list: it is the task with highest priority. */
+ /* "p_CB" points to head of list. */
+ P_TCB p_first;
+
+ p_first = p_CB->p_lnk;
+ p_CB->p_lnk = p_first->p_lnk;
+ if (p_CB->cb_type == SCB || p_CB->cb_type == MCB || p_CB->cb_type == MUCB) {
+ if (p_first->p_lnk != NULL) {
+ p_first->p_lnk->p_rlnk = (P_TCB)p_CB;
+ p_first->p_lnk = NULL;
+ }
+ p_first->p_rlnk = NULL;
+ }
+ else {
+ p_first->p_lnk = NULL;
+ }
+ return (p_first);
+}
+
+
+/*--------------------------- rt_put_rdy_first ------------------------------*/
+
+void rt_put_rdy_first (P_TCB p_task) {
+ /* Put task identified with "p_task" at the head of the ready list. The */
+ /* task must have at least a priority equal to highest priority in list. */
+ p_task->p_lnk = os_rdy.p_lnk;
+ p_task->p_rlnk = NULL;
+ os_rdy.p_lnk = p_task;
+}
+
+
+/*--------------------------- rt_get_same_rdy_prio --------------------------*/
+
+P_TCB rt_get_same_rdy_prio (void) {
+ /* Remove a task of same priority from ready list if any exists. Other- */
+ /* wise return NULL. */
+ P_TCB p_first;
+
+ p_first = os_rdy.p_lnk;
+ if (p_first->prio == os_tsk.run->prio) {
+ os_rdy.p_lnk = os_rdy.p_lnk->p_lnk;
+ return (p_first);
+ }
+ return (NULL);
+}
+
+
+/*--------------------------- rt_resort_prio --------------------------------*/
+
+void rt_resort_prio (P_TCB p_task) {
+ /* Re-sort ordered lists after the priority of 'p_task' has changed. */
+ P_TCB p_CB;
+
+ if (p_task->p_rlnk == NULL) {
+ if (p_task->state == READY) {
+ /* Task is chained into READY list. */
+ p_CB = (P_TCB)&os_rdy;
+ goto res;
+ }
+ }
+ else {
+ p_CB = p_task->p_rlnk;
+ while (p_CB->cb_type == TCB) {
+ /* Find a header of this task chain list. */
+ p_CB = p_CB->p_rlnk;
+ }
+res:rt_rmv_list (p_task);
+ rt_put_prio ((P_XCB)p_CB, p_task);
+ }
+}
+
+
+/*--------------------------- rt_put_dly ------------------------------------*/
+
+void rt_put_dly (P_TCB p_task, U16 delay) {
+ /* Put a task identified with "p_task" into chained delay wait list using */
+ /* a delay value of "delay". */
+ P_TCB p;
+ U32 delta,idelay = delay;
+
+ p = (P_TCB)&os_dly;
+ if (p->p_dlnk == NULL) {
+ /* Delay list empty */
+ delta = 0;
+ goto last;
+ }
+ delta = os_dly.delta_time;
+ while (delta < idelay) {
+ if (p->p_dlnk == NULL) {
+ /* End of list found */
+last: p_task->p_dlnk = NULL;
+ p->p_dlnk = p_task;
+ p_task->p_blnk = p;
+ p->delta_time = (U16)(idelay - delta);
+ p_task->delta_time = 0;
+ return;
+ }
+ p = p->p_dlnk;
+ delta += p->delta_time;
+ }
+ /* Right place found */
+ p_task->p_dlnk = p->p_dlnk;
+ p->p_dlnk = p_task;
+ p_task->p_blnk = p;
+ if (p_task->p_dlnk != NULL) {
+ p_task->p_dlnk->p_blnk = p_task;
+ }
+ p_task->delta_time = (U16)(delta - idelay);
+ p->delta_time -= p_task->delta_time;
+}
+
+
+/*--------------------------- rt_dec_dly ------------------------------------*/
+
+void rt_dec_dly (void) {
+ /* Decrement delta time of list head: remove tasks having a value of zero.*/
+ P_TCB p_rdy;
+
+ if (os_dly.p_dlnk == NULL) {
+ return;
+ }
+ os_dly.delta_time--;
+ while ((os_dly.delta_time == 0) && (os_dly.p_dlnk != NULL)) {
+ p_rdy = os_dly.p_dlnk;
+ if (p_rdy->p_rlnk != NULL) {
+ /* Task is really enqueued, remove task from semaphore/mailbox */
+ /* timeout waiting list. */
+ p_rdy->p_rlnk->p_lnk = p_rdy->p_lnk;
+ if (p_rdy->p_lnk != NULL) {
+ p_rdy->p_lnk->p_rlnk = p_rdy->p_rlnk;
+ p_rdy->p_lnk = NULL;
+ }
+ p_rdy->p_rlnk = NULL;
+ }
+ rt_put_prio (&os_rdy, p_rdy);
+ os_dly.delta_time = p_rdy->delta_time;
+ if (p_rdy->state == WAIT_ITV) {
+ /* Calculate the next time for interval wait. */
+ p_rdy->delta_time = p_rdy->interval_time + (U16)os_time;
+ }
+ p_rdy->state = READY;
+ p_rdy->ret_val = OS_R_TMO;
+ os_dly.p_dlnk = p_rdy->p_dlnk;
+ if (p_rdy->p_dlnk != NULL) {
+ p_rdy->p_dlnk->p_blnk = (P_TCB)&os_dly;
+ p_rdy->p_dlnk = NULL;
+ }
+ p_rdy->p_blnk = NULL;
+ }
+}
+
+
+/*--------------------------- rt_rmv_list -----------------------------------*/
+
+void rt_rmv_list (P_TCB p_task) {
+ /* Remove task identified with "p_task" from ready, semaphore or mailbox */
+ /* waiting list if enqueued. */
+ P_TCB p_b;
+
+ if (p_task->p_rlnk != NULL) {
+ /* A task is enqueued in semaphore / mailbox waiting list. */
+ p_task->p_rlnk->p_lnk = p_task->p_lnk;
+ if (p_task->p_lnk != NULL) {
+ p_task->p_lnk->p_rlnk = p_task->p_rlnk;
+ }
+ return;
+ }
+
+ p_b = (P_TCB)&os_rdy;
+ while (p_b != NULL) {
+ /* Search the ready list for task "p_task" */
+ if (p_b->p_lnk == p_task) {
+ p_b->p_lnk = p_task->p_lnk;
+ return;
+ }
+ p_b = p_b->p_lnk;
+ }
+}
+
+
+/*--------------------------- rt_rmv_dly ------------------------------------*/
+
+void rt_rmv_dly (P_TCB p_task) {
+ /* Remove task identified with "p_task" from delay list if enqueued. */
+ P_TCB p_b;
+
+ p_b = p_task->p_blnk;
+ if (p_b != NULL) {
+ /* Task is really enqueued */
+ p_b->p_dlnk = p_task->p_dlnk;
+ if (p_task->p_dlnk != NULL) {
+ /* 'p_task' is in the middle of list */
+ p_b->delta_time += p_task->delta_time;
+ p_task->p_dlnk->p_blnk = p_b;
+ p_task->p_dlnk = NULL;
+ }
+ else {
+ /* 'p_task' is at the end of list */
+ p_b->delta_time = 0;
+ }
+ p_task->p_blnk = NULL;
+ }
+}
+
+
+/*--------------------------- rt_psq_enq ------------------------------------*/
+
+void rt_psq_enq (OS_ID entry, U32 arg) {
+ /* Insert post service request "entry" into ps-queue. */
+ U32 idx;
+
+ idx = rt_inc_qi (os_psq->size, &os_psq->count, &os_psq->first);
+ if (idx < os_psq->size) {
+ os_psq->q[idx].id = entry;
+ os_psq->q[idx].arg = arg;
+ }
+ else {
+ os_error (OS_ERR_FIFO_OVF);
+ }
+}
+
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
diff -r 000000000000 -r 01f31e923fe2 source/rtos/rt_List.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/rtos/rt_List.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,54 @@ +/** + * @file rt_List.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Definitions */ + +/* Values for 'cb_type' */ +#define TCB 0 +#define MCB 1 +#define SCB 2 +#define MUCB 3 +#define HCB 4 + +/* Variables */ +extern struct OS_XCB os_rdy; +extern struct OS_XCB os_dly; + +/* Functions */ +extern void rt_put_prio (P_XCB p_CB, P_TCB p_task); +extern P_TCB rt_get_first (P_XCB p_CB); +extern void rt_put_rdy_first (P_TCB p_task); +extern P_TCB rt_get_same_rdy_prio (void); +extern void rt_resort_prio (P_TCB p_task); +extern void rt_put_dly (P_TCB p_task, U16 delay); +extern void rt_dec_dly (void); +extern void rt_rmv_list (P_TCB p_task); +extern void rt_rmv_dly (P_TCB p_task); +extern void rt_psq_enq (OS_ID entry, U32 arg); + +/* This is a fast macro generating in-line code */ +#define rt_rdy_prio(void) (os_rdy.p_lnk->prio) + + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ +
diff -r 000000000000 -r 01f31e923fe2 source/rtos/rt_Mailbox.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/rtos/rt_Mailbox.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,248 @@
+/**
+ * @file rt_Mailbox.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_List.h"
+#include "rt_Mailbox.h"
+#include "rt_Task.h"
+#include "rt_HAL_CM.h"
+
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_mbx_init -----------------------------------*/
+
+void rt_mbx_init (OS_ID mailbox, U16 mbx_size) {
+ /* Initialize a mailbox */
+ P_MCB p_MCB = mailbox;
+
+ p_MCB->cb_type = MCB;
+ p_MCB->isr_st = 0;
+ p_MCB->p_lnk = NULL;
+ p_MCB->first = 0;
+ p_MCB->last = 0;
+ p_MCB->count = 0;
+ p_MCB->size = (mbx_size + sizeof(void *) - sizeof(struct OS_MCB)) /
+ (U32)sizeof (void *);
+}
+
+
+/*--------------------------- rt_mbx_send -----------------------------------*/
+
+OS_RESULT rt_mbx_send (OS_ID mailbox, void *p_msg, U16 timeout) {
+ /* Send message to a mailbox */
+ P_MCB p_MCB = mailbox;
+ P_TCB p_TCB;
+
+ if (p_MCB->p_lnk != NULL && p_MCB->count == 0) {
+ /* A task is waiting for message */
+ p_TCB = rt_get_first ((P_XCB)p_MCB);
+ *p_TCB->msg = p_msg;
+ p_TCB->ret_val = OS_R_MBX;
+ rt_rmv_dly (p_TCB);
+ rt_dispatch (p_TCB);
+ os_tsk.run->ret_val = OS_R_OK;
+ }
+ else {
+ /* Store message in mailbox queue */
+ if (p_MCB->count == p_MCB->size) {
+ /* No free message entry, wait for one. If message queue is full, */
+ /* then no task is waiting for message. The 'p_MCB->p_lnk' list */
+ /* pointer can now be reused for send message waits task list. */
+ if (timeout == 0) {
+ return (OS_R_TMO);
+ }
+ if (p_MCB->p_lnk != NULL) {
+ rt_put_prio ((P_XCB)p_MCB, os_tsk.run);
+ }
+ else {
+ p_MCB->p_lnk = os_tsk.run;
+ os_tsk.run->p_lnk = NULL;
+ os_tsk.run->p_rlnk = (P_TCB)p_MCB;
+ /* Signal the 'isr_mbx_receive ()' that the task is waiting */
+ /* to send a message */
+ p_MCB->isr_st = 1;
+ }
+ os_tsk.run->msg = p_msg;
+ rt_block (timeout, WAIT_MBX);
+ return (OS_R_TMO);
+ }
+ /* Yes, there is a free entry in a mailbox. */
+ p_MCB->msg[p_MCB->first] = p_msg;
+ rt_inc (&p_MCB->count);
+ if (++p_MCB->first == p_MCB->size) {
+ p_MCB->first = 0;
+ }
+ }
+ return (OS_R_OK);
+}
+
+
+/*--------------------------- rt_mbx_wait -----------------------------------*/
+
+OS_RESULT rt_mbx_wait (OS_ID mailbox, void **message, U16 timeout) {
+ /* Receive a message; possibly wait for it */
+ P_MCB p_MCB = mailbox;
+ P_TCB p_TCB;
+
+ /* If a message is available in the fifo buffer */
+ /* remove it from the fifo buffer and return. */
+ if (p_MCB->count) {
+ *message = p_MCB->msg[p_MCB->last];
+ if (++p_MCB->last == p_MCB->size) {
+ p_MCB->last = 0;
+ }
+ if (p_MCB->p_lnk != NULL) {
+ /* A task is waiting to send message */
+ p_TCB = rt_get_first ((P_XCB)p_MCB);
+ p_TCB->ret_val = OS_R_OK;
+ p_MCB->msg[p_MCB->first] = p_TCB->msg;
+ if (++p_MCB->first == p_MCB->size) {
+ p_MCB->first = 0;
+ }
+ rt_rmv_dly (p_TCB);
+ rt_dispatch (p_TCB);
+ os_tsk.run->ret_val = OS_R_OK;
+ }
+ else {
+ rt_dec (&p_MCB->count);
+ }
+ return (OS_R_OK);
+ }
+ /* No message available: wait for one */
+ if (timeout == 0) {
+ return (OS_R_TMO);
+ }
+ if (p_MCB->p_lnk != NULL) {
+ rt_put_prio ((P_XCB)p_MCB, os_tsk.run);
+ }
+ else {
+ p_MCB->p_lnk = os_tsk.run;
+ os_tsk.run->p_lnk = NULL;
+ os_tsk.run->p_rlnk = (P_TCB)p_MCB;
+ }
+ rt_block(timeout, WAIT_MBX);
+ os_tsk.run->msg = message;
+ return (OS_R_TMO);
+}
+
+
+/*--------------------------- rt_mbx_check ----------------------------------*/
+
+OS_RESULT rt_mbx_check (OS_ID mailbox) {
+ /* Check for free space in a mailbox. Returns the number of messages */
+ /* that can be stored to a mailbox. It returns 0 when mailbox is full. */
+ P_MCB p_MCB = mailbox;
+
+ return (p_MCB->size - p_MCB->count);
+}
+
+
+/*--------------------------- isr_mbx_send ----------------------------------*/
+
+void isr_mbx_send (OS_ID mailbox, void *p_msg) {
+ /* Same function as "os_mbx_send", but to be called by ISRs. */
+ P_MCB p_MCB = mailbox;
+
+ rt_psq_enq (p_MCB, (U32)p_msg);
+ rt_psh_req ();
+}
+
+
+/*--------------------------- isr_mbx_receive -------------------------------*/
+
+OS_RESULT isr_mbx_receive (OS_ID mailbox, void **message) {
+ /* Receive a message in the interrupt function. The interrupt function */
+ /* should not wait for a message since this would block the rtx os. */
+ P_MCB p_MCB = mailbox;
+
+ if (p_MCB->count) {
+ /* A message is available in the fifo buffer. */
+ *message = p_MCB->msg[p_MCB->last];
+ if (p_MCB->isr_st == 1) {
+ /* A task is locked waiting to send message */
+ p_MCB->isr_st = 2;
+ rt_psq_enq (p_MCB, 0);
+ rt_psh_req ();
+ }
+ rt_dec (&p_MCB->count);
+ if (++p_MCB->last == p_MCB->size) {
+ p_MCB->last = 0;
+ }
+ return (OS_R_MBX);
+ }
+ return (OS_R_OK);
+}
+
+
+/*--------------------------- rt_mbx_psh ------------------------------------*/
+
+void rt_mbx_psh (P_MCB p_CB, void *p_msg) {
+ /* Store the message to the mailbox queue or pass it to task directly. */
+ P_TCB p_TCB;
+
+ /* Check if this was an 'isr_mbx_receive ()' post service request. */
+ if (p_CB->p_lnk != NULL && p_CB->isr_st == 2) {
+ /* A task is waiting to send message, remove it from the waiting list. */
+ p_CB->isr_st = 0;
+ p_TCB = rt_get_first ((P_XCB)p_CB);
+ p_TCB->ret_val = OS_R_OK;
+ /* Store the message to the mailbox queue. */
+ p_CB->msg[p_CB->first] = p_TCB->msg;
+ rt_inc (&p_CB->count);
+ if (++p_CB->first == p_CB->size) {
+ p_CB->first = 0;
+ }
+ goto rdy;
+ }
+ /* A task is waiting for message, pass the message to task directly. */
+ if (p_CB->p_lnk != NULL && p_CB->count == 0) {
+ p_TCB = rt_get_first ((P_XCB)p_CB);
+ *p_TCB->msg = p_msg;
+ p_TCB->ret_val = OS_R_MBX;
+rdy:p_TCB->state = READY;
+ rt_rmv_dly (p_TCB);
+ rt_put_prio (&os_rdy, p_TCB);
+ }
+ else {
+ /* No task is waiting for message, store the message to the mailbox queue.*/
+ if (p_CB->count < p_CB->size) {
+ p_CB->msg[p_CB->first] = p_msg;
+ rt_inc (&p_CB->count);
+ if (++p_CB->first == p_CB->size) {
+ p_CB->first = 0;
+ }
+ }
+ else {
+ os_error (OS_ERR_MBX_OVF);
+ }
+ }
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
diff -r 000000000000 -r 01f31e923fe2 source/rtos/rt_Mailbox.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/rtos/rt_Mailbox.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,35 @@ +/** + * @file rt_Mailbox.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Functions */ +extern void rt_mbx_init (OS_ID mailbox, U16 mbx_size); +extern OS_RESULT rt_mbx_send (OS_ID mailbox, void *p_msg, U16 timeout); +extern OS_RESULT rt_mbx_wait (OS_ID mailbox, void **message, U16 timeout); +extern OS_RESULT rt_mbx_check (OS_ID mailbox); +extern void isr_mbx_send (OS_ID mailbox, void *p_msg); +extern OS_RESULT isr_mbx_receive (OS_ID mailbox, void **message); +extern void rt_mbx_psh (P_MCB p_CB, void *p_msg); + + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ +
diff -r 000000000000 -r 01f31e923fe2 source/rtos/rt_MemBox.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/rtos/rt_MemBox.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,153 @@
+/**
+ * @file rt_MemBox.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_MemBox.h"
+#include "rt_HAL_CM.h"
+
+/*----------------------------------------------------------------------------
+ * Global Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- _init_box -------------------------------------*/
+
+int _init_box (void *box_mem, U32 box_size, U32 blk_size) {
+ /* Initialize memory block system, returns 0 if OK, 1 if fails. */
+ void *end;
+ void *blk;
+ void *next;
+ U32 sizeof_bm;
+
+ /* Create memory structure. */
+ if (blk_size & BOX_ALIGN_8) {
+ /* Memory blocks 8-byte aligned. */
+ blk_size = ((blk_size & ~BOX_ALIGN_8) + 7) & ~7;
+ sizeof_bm = (sizeof (struct OS_BM) + 7) & ~7;
+ }
+ else {
+ /* Memory blocks 4-byte aligned. */
+ blk_size = (blk_size + 3) & ~3;
+ sizeof_bm = sizeof (struct OS_BM);
+ }
+ if (blk_size == 0) {
+ return (1);
+ }
+ if ((blk_size + sizeof_bm) > box_size) {
+ return (1);
+ }
+ /* Create a Memory structure. */
+ blk = ((U8 *) box_mem) + sizeof_bm;
+ ((P_BM) box_mem)->free = blk;
+ end = ((U8 *) box_mem) + box_size;
+ ((P_BM) box_mem)->end = end;
+ ((P_BM) box_mem)->blk_size = blk_size;
+
+ /* Link all free blocks using offsets. */
+ end = ((U8 *) end) - blk_size;
+ while (1) {
+ next = ((U8 *) blk) + blk_size;
+ if (next > end) break;
+ *((void **)blk) = next;
+ blk = next;
+ }
+ /* end marker */
+ *((void **)blk) = 0;
+ return (0);
+}
+
+/*--------------------------- rt_alloc_box ----------------------------------*/
+
+void *rt_alloc_box (void *box_mem) {
+ /* Allocate a memory block and return start address. */
+ void **free;
+#ifndef __USE_EXCLUSIVE_ACCESS
+ int irq_dis;
+
+ irq_dis = __disable_irq ();
+ free = ((P_BM) box_mem)->free;
+ if (free) {
+ ((P_BM) box_mem)->free = *free;
+ }
+ if (!irq_dis) __enable_irq ();
+#else
+ do {
+ if ((free = (void **)__ldrex(&((P_BM) box_mem)->free)) == 0) {
+ __clrex();
+ break;
+ }
+ } while (__strex((U32)*free, &((P_BM) box_mem)->free));
+#endif
+ return (free);
+}
+
+
+/*--------------------------- _calloc_box -----------------------------------*/
+
+void *_calloc_box (void *box_mem) {
+ /* Allocate a 0-initialized memory block and return start address. */
+ void *free;
+ U32 *p;
+ U32 i;
+
+ free = _alloc_box (box_mem);
+ if (free) {
+ p = free;
+ for (i = ((P_BM) box_mem)->blk_size; i; i -= 4) {
+ *p = 0;
+ p++;
+ }
+ }
+ return (free);
+}
+
+
+/*--------------------------- rt_free_box -----------------------------------*/
+
+int rt_free_box (void *box_mem, void *box) {
+ /* Free a memory block, returns 0 if OK, 1 if box does not belong to box_mem */
+#ifndef __USE_EXCLUSIVE_ACCESS
+ int irq_dis;
+#endif
+
+ if (box < box_mem || box >= ((P_BM) box_mem)->end) {
+ return (1);
+ }
+
+#ifndef __USE_EXCLUSIVE_ACCESS
+ irq_dis = __disable_irq ();
+ *((void **)box) = ((P_BM) box_mem)->free;
+ ((P_BM) box_mem)->free = box;
+ if (!irq_dis) __enable_irq ();
+#else
+ do {
+ *((void **)box) = (void *)__ldrex(&((P_BM) box_mem)->free);
+ } while (__strex ((U32)box, &((P_BM) box_mem)->free));
+#endif
+ return (0);
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
diff -r 000000000000 -r 01f31e923fe2 source/rtos/rt_MemBox.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/rtos/rt_MemBox.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,33 @@ +/** + * @file rt_MemBox.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Functions */ +#define rt_init_box _init_box +#define rt_calloc_box _calloc_box +extern int _init_box (void *box_mem, U32 box_size, U32 blk_size); +extern void *rt_alloc_box (void *box_mem); +extern void * _calloc_box (void *box_mem); +extern int rt_free_box (void *box_mem, void *box); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ +
diff -r 000000000000 -r 01f31e923fe2 source/rtos/rt_Mutex.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/rtos/rt_Mutex.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,142 @@
+/**
+ * @file rt_Mutex.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_List.h"
+#include "rt_Task.h"
+#include "rt_Mutex.h"
+
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_mut_init -----------------------------------*/
+
+void rt_mut_init (OS_ID mutex) {
+ /* Initialize a mutex object */
+ P_MUCB p_MCB = mutex;
+
+ p_MCB->cb_type = MUCB;
+ p_MCB->prio = 0;
+ p_MCB->level = 0;
+ p_MCB->p_lnk = NULL;
+ p_MCB->owner = NULL;
+}
+
+
+/*--------------------------- rt_mut_release --------------------------------*/
+
+OS_RESULT rt_mut_release (OS_ID mutex) {
+ /* Release a mutex object */
+ P_MUCB p_MCB = mutex;
+ P_TCB p_TCB;
+
+ if (p_MCB->level == 0 || p_MCB->owner != os_tsk.run) {
+ /* Unbalanced mutex release or task is not the owner */
+ return (OS_R_NOK);
+ }
+ if (--p_MCB->level != 0) {
+ return (OS_R_OK);
+ }
+ /* Restore owner task's priority. */
+ os_tsk.run->prio = p_MCB->prio;
+ if (p_MCB->p_lnk != NULL) {
+ /* A task is waiting for mutex. */
+ p_TCB = rt_get_first ((P_XCB)p_MCB);
+ p_TCB->ret_val = OS_R_MUT;
+ rt_rmv_dly (p_TCB);
+ /* A waiting task becomes the owner of this mutex. */
+ p_MCB->level = 1;
+ p_MCB->owner = p_TCB;
+ p_MCB->prio = p_TCB->prio;
+ /* Priority inversion, check which task continues. */
+ if (os_tsk.run->prio >= rt_rdy_prio()) {
+ rt_dispatch (p_TCB);
+ }
+ else {
+ /* Ready task has higher priority than running task. */
+ rt_put_prio (&os_rdy, os_tsk.run);
+ rt_put_prio (&os_rdy, p_TCB);
+ os_tsk.run->state = READY;
+ p_TCB->state = READY;
+ rt_dispatch (NULL);
+ }
+ os_tsk.run->ret_val = OS_R_OK;
+ }
+ else {
+ /* Check if own priority raised by priority inversion. */
+ if (rt_rdy_prio() > os_tsk.run->prio) {
+ rt_put_prio (&os_rdy, os_tsk.run);
+ os_tsk.run->state = READY;
+ rt_dispatch (NULL);
+ os_tsk.run->ret_val = OS_R_OK;
+ }
+ }
+ return (OS_R_OK);
+}
+
+
+/*--------------------------- rt_mut_wait -----------------------------------*/
+
+OS_RESULT rt_mut_wait (OS_ID mutex, U16 timeout) {
+ /* Wait for a mutex, continue when mutex is free. */
+ P_MUCB p_MCB = mutex;
+
+ if (p_MCB->level == 0) {
+ p_MCB->owner = os_tsk.run;
+ p_MCB->prio = os_tsk.run->prio;
+ goto inc;
+ }
+ if (p_MCB->owner == os_tsk.run) {
+ /* OK, running task is the owner of this mutex. */
+inc:p_MCB->level++;
+ return (OS_R_OK);
+ }
+ /* Mutex owned by another task, wait until released. */
+ if (timeout == 0) {
+ return (OS_R_TMO);
+ }
+ /* Raise the owner task priority if lower than current priority. */
+ /* This priority inversion is called priority inheritance. */
+ if (p_MCB->prio < os_tsk.run->prio) {
+ p_MCB->owner->prio = os_tsk.run->prio;
+ rt_resort_prio (p_MCB->owner);
+ }
+ if (p_MCB->p_lnk != NULL) {
+ rt_put_prio ((P_XCB)p_MCB, os_tsk.run);
+ }
+ else {
+ p_MCB->p_lnk = os_tsk.run;
+ os_tsk.run->p_lnk = NULL;
+ os_tsk.run->p_rlnk = (P_TCB)p_MCB;
+ }
+ rt_block(timeout, WAIT_MUT);
+ return (OS_R_TMO);
+}
+
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
diff -r 000000000000 -r 01f31e923fe2 source/rtos/rt_Mutex.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/rtos/rt_Mutex.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,30 @@ +/** + * @file rt_Mutex.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Functions */ +extern void rt_mut_init (OS_ID mutex); +extern OS_RESULT rt_mut_release (OS_ID mutex); +extern OS_RESULT rt_mut_wait (OS_ID mutex, U16 timeout); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ +
diff -r 000000000000 -r 01f31e923fe2 source/rtos/rt_Robin.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/rtos/rt_Robin.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,70 @@
+/**
+ * @file rt_Robin.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_List.h"
+#include "rt_Task.h"
+#include "rt_Time.h"
+#include "rt_Robin.h"
+
+/*----------------------------------------------------------------------------
+ * Global Variables
+ *---------------------------------------------------------------------------*/
+
+struct OS_ROBIN os_robin;
+
+
+/*----------------------------------------------------------------------------
+ * Global Functions
+ *---------------------------------------------------------------------------*/
+
+/*--------------------------- rt_init_robin ---------------------------------*/
+
+__weak void rt_init_robin (void) {
+ /* Initialize Round Robin variables. */
+ os_robin.task = NULL;
+ os_robin.tout = (U16)os_rrobin;
+}
+
+/*--------------------------- rt_chk_robin ----------------------------------*/
+
+__weak void rt_chk_robin (void) {
+ /* Check if Round Robin timeout expired and switch to the next ready task.*/
+ P_TCB p_new;
+
+ if (os_robin.task != os_rdy.p_lnk) {
+ /* New task was suspended, reset Round Robin timeout. */
+ os_robin.task = os_rdy.p_lnk;
+ os_robin.time = (U16)os_time + os_robin.tout - 1;
+ }
+ if (os_robin.time == (U16)os_time) {
+ /* Round Robin timeout has expired, swap Robin tasks. */
+ os_robin.task = NULL;
+ p_new = rt_get_first (&os_rdy);
+ rt_put_prio ((P_XCB)&os_rdy, p_new);
+ }
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
diff -r 000000000000 -r 01f31e923fe2 source/rtos/rt_Robin.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/rtos/rt_Robin.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,32 @@ +/** + * @file rt_Robin.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Variables */ +extern struct OS_ROBIN os_robin; + +/* Functions */ +extern void rt_init_robin (void); +extern void rt_chk_robin (void); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ +
diff -r 000000000000 -r 01f31e923fe2 source/rtos/rt_Semaphore.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/rtos/rt_Semaphore.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,131 @@
+/**
+ * @file rt_Semaphore.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_List.h"
+#include "rt_Task.h"
+#include "rt_Semaphore.h"
+
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_sem_init -----------------------------------*/
+
+void rt_sem_init (OS_ID semaphore, U16 token_count) {
+ /* Initialize a semaphore */
+ P_SCB p_SCB = semaphore;
+
+ p_SCB->cb_type = SCB;
+ p_SCB->p_lnk = NULL;
+ p_SCB->tokens = token_count;
+}
+
+
+/*--------------------------- rt_sem_send -----------------------------------*/
+
+OS_RESULT rt_sem_send (OS_ID semaphore) {
+ /* Return a token to semaphore */
+ P_SCB p_SCB = semaphore;
+ P_TCB p_TCB;
+
+ if (p_SCB->p_lnk != NULL) {
+ /* A task is waiting for token */
+ p_TCB = rt_get_first ((P_XCB)p_SCB);
+ p_TCB->ret_val = OS_R_SEM;
+ rt_rmv_dly (p_TCB);
+ rt_dispatch (p_TCB);
+ os_tsk.run->ret_val = OS_R_OK;
+ }
+ else {
+ /* Store token. */
+ p_SCB->tokens++;
+ }
+ return (OS_R_OK);
+}
+
+
+/*--------------------------- rt_sem_wait -----------------------------------*/
+
+OS_RESULT rt_sem_wait (OS_ID semaphore, U16 timeout) {
+ /* Obtain a token; possibly wait for it */
+ P_SCB p_SCB = semaphore;
+
+ if (p_SCB->tokens) {
+ p_SCB->tokens--;
+ return (OS_R_OK);
+ }
+ /* No token available: wait for one */
+ if (timeout == 0) {
+ return (OS_R_TMO);
+ }
+ if (p_SCB->p_lnk != NULL) {
+ rt_put_prio ((P_XCB)p_SCB, os_tsk.run);
+ }
+ else {
+ p_SCB->p_lnk = os_tsk.run;
+ os_tsk.run->p_lnk = NULL;
+ os_tsk.run->p_rlnk = (P_TCB)p_SCB;
+ }
+ rt_block(timeout, WAIT_SEM);
+ return (OS_R_TMO);
+}
+
+
+/*--------------------------- isr_sem_send ----------------------------------*/
+
+void isr_sem_send (OS_ID semaphore) {
+ /* Same function as "os_sem"send", but to be called by ISRs */
+ P_SCB p_SCB = semaphore;
+
+ rt_psq_enq (p_SCB, 0);
+ rt_psh_req ();
+}
+
+
+/*--------------------------- rt_sem_psh ------------------------------------*/
+
+void rt_sem_psh (P_SCB p_CB) {
+ /* Check if task has to be waken up */
+ P_TCB p_TCB;
+
+ if (p_CB->p_lnk != NULL) {
+ /* A task is waiting for token */
+ p_TCB = rt_get_first ((P_XCB)p_CB);
+ rt_rmv_dly (p_TCB);
+ p_TCB->state = READY;
+ p_TCB->ret_val = OS_R_SEM;
+ rt_put_prio (&os_rdy, p_TCB);
+ }
+ else {
+ /* Store token */
+ p_CB->tokens++;
+ }
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
diff -r 000000000000 -r 01f31e923fe2 source/rtos/rt_Semaphore.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/rtos/rt_Semaphore.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,32 @@ +/** + * @file rt_Semaphore.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Functions */ +extern void rt_sem_init (OS_ID semaphore, U16 token_count); +extern OS_RESULT rt_sem_send (OS_ID semaphore); +extern OS_RESULT rt_sem_wait (OS_ID semaphore, U16 timeout); +extern void isr_sem_send (OS_ID semaphore); +extern void rt_sem_psh (P_SCB p_CB); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ +
diff -r 000000000000 -r 01f31e923fe2 source/rtos/rt_System.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/rtos/rt_System.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,274 @@
+/**
+ * @file rt_System.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_Task.h"
+#include "rt_System.h"
+#include "rt_Event.h"
+#include "rt_List.h"
+#include "rt_Mailbox.h"
+#include "rt_Semaphore.h"
+#include "rt_Time.h"
+#include "rt_Timer.h"
+#include "rt_Robin.h"
+#include "rt_HAL_CM.h"
+
+/*----------------------------------------------------------------------------
+ * Global Variables
+ *---------------------------------------------------------------------------*/
+
+int os_tick_irqn;
+
+/*----------------------------------------------------------------------------
+ * Local Variables
+ *---------------------------------------------------------------------------*/
+
+static volatile BIT os_lock;
+static volatile BIT os_psh_flag;
+static U8 pend_flags;
+
+/*----------------------------------------------------------------------------
+ * Global Functions
+ *---------------------------------------------------------------------------*/
+
+__asm void $$RTX$$version (void) {
+ /* Export a version number symbol for a version control. */
+
+ EXPORT __RL_RTX_VER
+
+__RL_RTX_VER EQU 0x470
+}
+
+
+/*--------------------------- rt_suspend ------------------------------------*/
+
+U32 rt_suspend (void) {
+ /* Suspend OS scheduler */
+ U32 delta = 0xFFFF;
+
+ rt_tsk_lock();
+
+ if (os_dly.p_dlnk) {
+ delta = os_dly.delta_time;
+ }
+ if (os_tmr.next) {
+ if (os_tmr.tcnt < delta) delta = os_tmr.tcnt;
+ }
+
+ return (delta);
+}
+
+
+/*--------------------------- rt_resume -------------------------------------*/
+
+void rt_resume (U32 sleep_time) {
+ /* Resume OS scheduler after suspend */
+ P_TCB next;
+ U32 delta;
+
+ os_tsk.run->state = READY;
+ rt_put_rdy_first (os_tsk.run);
+
+ os_robin.task = NULL;
+
+ /* Update delays. */
+ if (os_dly.p_dlnk) {
+ delta = sleep_time;
+ if (delta >= os_dly.delta_time) {
+ delta -= os_dly.delta_time;
+ os_time += os_dly.delta_time;
+ os_dly.delta_time = 1;
+ while (os_dly.p_dlnk) {
+ rt_dec_dly();
+ if (delta == 0) break;
+ delta--;
+ os_time++;
+ }
+ } else {
+ os_time += delta;
+ os_dly.delta_time -= delta;
+ }
+ } else {
+ os_time += sleep_time;
+ }
+
+ /* Check the user timers. */
+ if (os_tmr.next) {
+ delta = sleep_time;
+ if (delta >= os_tmr.tcnt) {
+ delta -= os_tmr.tcnt;
+ os_tmr.tcnt = 1;
+ while (os_tmr.next) {
+ rt_tmr_tick();
+ if (delta == 0) break;
+ delta--;
+ }
+ } else {
+ os_tmr.tcnt -= delta;
+ }
+ }
+
+ /* Switch back to highest ready task */
+ next = rt_get_first (&os_rdy);
+ rt_switch_req (next);
+
+ rt_tsk_unlock();
+}
+
+
+/*--------------------------- rt_tsk_lock -----------------------------------*/
+
+void rt_tsk_lock (void) {
+ /* Prevent task switching by locking out scheduler */
+ if (os_tick_irqn < 0) {
+ OS_LOCK();
+ os_lock = __TRUE;
+ OS_UNPEND (&pend_flags);
+ } else {
+ OS_X_LOCK(os_tick_irqn);
+ os_lock = __TRUE;
+ OS_X_UNPEND (&pend_flags);
+ }
+}
+
+
+/*--------------------------- rt_tsk_unlock ---------------------------------*/
+
+void rt_tsk_unlock (void) {
+ /* Unlock scheduler and re-enable task switching */
+ if (os_tick_irqn < 0) {
+ OS_UNLOCK();
+ os_lock = __FALSE;
+ OS_PEND (pend_flags, os_psh_flag);
+ os_psh_flag = __FALSE;
+ } else {
+ OS_X_UNLOCK(os_tick_irqn);
+ os_lock = __FALSE;
+ OS_X_PEND (pend_flags, os_psh_flag);
+ os_psh_flag = __FALSE;
+ }
+}
+
+
+/*--------------------------- rt_psh_req ------------------------------------*/
+
+void rt_psh_req (void) {
+ /* Initiate a post service handling request if required. */
+ if (os_lock == __FALSE) {
+ OS_PEND_IRQ ();
+ }
+ else {
+ os_psh_flag = __TRUE;
+ }
+}
+
+
+/*--------------------------- rt_pop_req ------------------------------------*/
+
+void rt_pop_req (void) {
+ /* Process an ISR post service requests. */
+ struct OS_XCB *p_CB;
+ P_TCB next;
+ U32 idx;
+
+ os_tsk.run->state = READY;
+ rt_put_rdy_first (os_tsk.run);
+
+ idx = os_psq->last;
+ while (os_psq->count) {
+ p_CB = os_psq->q[idx].id;
+ if (p_CB->cb_type == TCB) {
+ /* Is of TCB type */
+ rt_evt_psh ((P_TCB)p_CB, (U16)os_psq->q[idx].arg);
+ }
+ else if (p_CB->cb_type == MCB) {
+ /* Is of MCB type */
+ rt_mbx_psh ((P_MCB)p_CB, (void *)os_psq->q[idx].arg);
+ }
+ else {
+ /* Must be of SCB type */
+ rt_sem_psh ((P_SCB)p_CB);
+ }
+ if (++idx == os_psq->size) idx = 0;
+ rt_dec (&os_psq->count);
+ }
+ os_psq->last = idx;
+
+ next = rt_get_first (&os_rdy);
+ rt_switch_req (next);
+}
+
+
+/*--------------------------- os_tick_init ----------------------------------*/
+
+__weak int os_tick_init (void) {
+ /* Initialize SysTick timer as system tick timer. */
+ rt_systick_init ();
+ return (-1); /* Return IRQ number of SysTick timer */
+}
+
+
+/*--------------------------- os_tick_irqack --------------------------------*/
+
+__weak void os_tick_irqack (void) {
+ /* Acknowledge timer interrupt. */
+}
+
+
+/*--------------------------- rt_systick ------------------------------------*/
+
+void rt_systick (void) {
+ /* Check for system clock update, suspend running task. */
+ P_TCB next;
+
+ os_tsk.run->state = READY;
+ rt_put_rdy_first (os_tsk.run);
+
+ /* Check Round Robin timeout. */
+ rt_chk_robin ();
+
+ /* Update delays. */
+ os_time++;
+ rt_dec_dly ();
+
+ /* Check the user timers. */
+ rt_tmr_tick ();
+
+ /* Switch back to highest ready task */
+ next = rt_get_first (&os_rdy);
+ rt_switch_req (next);
+}
+
+/*--------------------------- rt_stk_check ----------------------------------*/
+
+__weak void rt_stk_check (void) {
+ /* Check for stack overflow. */
+ if ((os_tsk.run->tsk_stack < (U32)os_tsk.run->stack) ||
+ (os_tsk.run->stack[0] != MAGIC_WORD)) {
+ os_error (OS_ERR_STK_OVF);
+ }
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
diff -r 000000000000 -r 01f31e923fe2 source/rtos/rt_System.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/rtos/rt_System.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,39 @@ +/** + * @file rt_System.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Variables */ +#define os_psq ((P_PSQ)&os_fifo) +extern int os_tick_irqn; + +/* Functions */ +extern U32 rt_suspend (void); +extern void rt_resume (U32 sleep_time); +extern void rt_tsk_lock (void); +extern void rt_tsk_unlock (void); +extern void rt_psh_req (void); +extern void rt_pop_req (void); +extern void rt_systick (void); +extern void rt_stk_check (void); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ +
diff -r 000000000000 -r 01f31e923fe2 source/rtos/rt_Task.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/rtos/rt_Task.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,336 @@
+/**
+ * @file rt_Task.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_Task.h"
+#include "rt_List.h"
+#include "rt_MemBox.h"
+#include "rt_Robin.h"
+#include "rt_HAL_CM.h"
+
+/*----------------------------------------------------------------------------
+ * Global Variables
+ *---------------------------------------------------------------------------*/
+
+/* Running and next task info. */
+struct OS_TSK os_tsk;
+
+/* Task Control Blocks of idle demon */
+struct OS_TCB os_idle_TCB;
+
+
+/*----------------------------------------------------------------------------
+ * Local Functions
+ *---------------------------------------------------------------------------*/
+
+static OS_TID rt_get_TID (void) {
+ U32 tid;
+
+ for (tid = 1; tid <= os_maxtaskrun; tid++) {
+ if (os_active_TCB[tid-1] == NULL) {
+ return ((OS_TID)tid);
+ }
+ }
+ return (0);
+}
+
+
+/*--------------------------- rt_init_context -------------------------------*/
+
+static void rt_init_context (P_TCB p_TCB, U8 priority, FUNCP task_body) {
+ /* Initialize general part of the Task Control Block. */
+ p_TCB->cb_type = TCB;
+ p_TCB->state = READY;
+ p_TCB->prio = priority;
+ p_TCB->p_lnk = NULL;
+ p_TCB->p_rlnk = NULL;
+ p_TCB->p_dlnk = NULL;
+ p_TCB->p_blnk = NULL;
+ p_TCB->delta_time = 0;
+ p_TCB->interval_time = 0;
+ p_TCB->events = 0;
+ p_TCB->waits = 0;
+ p_TCB->ret_val = OS_R_OK;
+ p_TCB->ret_upd = 0;
+
+ if (p_TCB->priv_stack == 0) {
+ /* Allocate the memory space for the stack. */
+ p_TCB->stack = rt_alloc_box (mp_stk);
+ }
+ rt_init_stack (p_TCB, task_body);
+}
+
+
+/*--------------------------- rt_switch_req ---------------------------------*/
+
+void rt_switch_req (P_TCB p_new) {
+ /* Switch to next task (identified by "p_new"). */
+ os_tsk.new = p_new;
+ p_new->state = RUNNING;
+ DBG_TASK_SWITCH(p_new->task_id);
+}
+
+
+/*--------------------------- rt_dispatch -----------------------------------*/
+
+void rt_dispatch (P_TCB next_TCB) {
+ /* Dispatch next task if any identified or dispatch highest ready task */
+ /* "next_TCB" identifies a task to run or has value NULL (=no next task) */
+ if (next_TCB == NULL) {
+ /* Running task was blocked: continue with highest ready task */
+ next_TCB = rt_get_first (&os_rdy);
+ rt_switch_req (next_TCB);
+ }
+ else {
+ /* Check which task continues */
+ if (next_TCB->prio > os_tsk.run->prio) {
+ /* preempt running task */
+ rt_put_rdy_first (os_tsk.run);
+ os_tsk.run->state = READY;
+ rt_switch_req (next_TCB);
+ }
+ else {
+ /* put next task into ready list, no task switch takes place */
+ next_TCB->state = READY;
+ rt_put_prio (&os_rdy, next_TCB);
+ }
+ }
+}
+
+
+/*--------------------------- rt_block --------------------------------------*/
+
+void rt_block (U16 timeout, U8 block_state) {
+ /* Block running task and choose next ready task. */
+ /* "timeout" sets a time-out value or is 0xffff (=no time-out). */
+ /* "block_state" defines the appropriate task state */
+ P_TCB next_TCB;
+
+ if (timeout) {
+ if (timeout < 0xffff) {
+ rt_put_dly (os_tsk.run, timeout);
+ }
+ os_tsk.run->state = block_state;
+ next_TCB = rt_get_first (&os_rdy);
+ rt_switch_req (next_TCB);
+ }
+}
+
+
+/*--------------------------- rt_tsk_pass -----------------------------------*/
+
+void rt_tsk_pass (void) {
+ /* Allow tasks of same priority level to run cooperatively.*/
+ P_TCB p_new;
+
+ p_new = rt_get_same_rdy_prio();
+ if (p_new != NULL) {
+ rt_put_prio ((P_XCB)&os_rdy, os_tsk.run);
+ os_tsk.run->state = READY;
+ rt_switch_req (p_new);
+ }
+}
+
+
+/*--------------------------- rt_tsk_self -----------------------------------*/
+
+OS_TID rt_tsk_self (void) {
+ /* Return own task identifier value. */
+ if (os_tsk.run == NULL) {
+ return (0);
+ }
+ return (os_tsk.run->task_id);
+}
+
+
+/*--------------------------- rt_tsk_prio -----------------------------------*/
+
+OS_RESULT rt_tsk_prio (OS_TID task_id, U8 new_prio) {
+ /* Change execution priority of a task to "new_prio". */
+ P_TCB p_task;
+
+ if (task_id == 0) {
+ /* Change execution priority of calling task. */
+ os_tsk.run->prio = new_prio;
+run:if (rt_rdy_prio() > new_prio) {
+ rt_put_prio (&os_rdy, os_tsk.run);
+ os_tsk.run->state = READY;
+ os_tsk.run->ret_val = OS_R_OK;
+ rt_dispatch (NULL);
+ }
+ return (OS_R_OK);
+ }
+
+ /* Find the task in the "os_active_TCB" array. */
+ if (task_id > os_maxtaskrun || os_active_TCB[task_id-1] == NULL) {
+ /* Task with "task_id" not found or not started. */
+ return (OS_R_NOK);
+ }
+ p_task = os_active_TCB[task_id-1];
+ p_task->prio = new_prio;
+ if (p_task == os_tsk.run) {
+ goto run;
+ }
+ rt_resort_prio (p_task);
+ if (p_task->state == READY) {
+ /* Task enqueued in a ready list. */
+ p_task = rt_get_first (&os_rdy);
+ os_tsk.run->ret_val = OS_R_OK;
+ rt_dispatch (p_task);
+ }
+ return (OS_R_OK);
+}
+
+
+/*--------------------------- rt_tsk_create ---------------------------------*/
+
+OS_TID rt_tsk_create (FUNCP task, U32 prio_stksz, void *stk, void *argv) {
+ /* Start a new task declared with "task". */
+ P_TCB task_context;
+ U32 i;
+
+ /* Priority 0 is reserved for idle task! */
+ if ((prio_stksz & 0xFF) == 0) {
+ prio_stksz += 1;
+ }
+ task_context = rt_alloc_box (mp_tcb);
+ if (task_context == NULL) {
+ return (0);
+ }
+ /* If "size != 0" use a private user provided stack. */
+ task_context->stack = stk;
+ task_context->priv_stack = prio_stksz >> 8;
+ /* Pass parameter 'argv' to 'rt_init_context' */
+ task_context->msg = argv;
+ /* For 'size == 0' system allocates the user stack from the memory pool. */
+ rt_init_context (task_context, prio_stksz & 0xFF, task);
+
+ /* Find a free entry in 'os_active_TCB' table. */
+ i = rt_get_TID ();
+ os_active_TCB[i-1] = task_context;
+ task_context->task_id = i;
+ DBG_TASK_NOTIFY(task_context, __TRUE);
+ rt_dispatch (task_context);
+ os_tsk.run->ret_val = i;
+ return ((OS_TID)i);
+}
+
+
+/*--------------------------- rt_tsk_delete ---------------------------------*/
+
+OS_RESULT rt_tsk_delete (OS_TID task_id) {
+ /* Terminate the task identified with "task_id". */
+ P_TCB task_context;
+
+ if (task_id == 0 || task_id == os_tsk.run->task_id) {
+ /* Terminate itself. */
+ os_tsk.run->state = INACTIVE;
+ os_tsk.run->tsk_stack = rt_get_PSP ();
+ rt_stk_check ();
+ os_active_TCB[os_tsk.run->task_id-1] = NULL;
+ rt_free_box (mp_stk, os_tsk.run->stack);
+ os_tsk.run->stack = NULL;
+ DBG_TASK_NOTIFY(os_tsk.run, __FALSE);
+ rt_free_box (mp_tcb, os_tsk.run);
+ os_tsk.run = NULL;
+ rt_dispatch (NULL);
+ /* The program should never come to this point. */
+ }
+ else {
+ /* Find the task in the "os_active_TCB" array. */
+ if (task_id > os_maxtaskrun || os_active_TCB[task_id-1] == NULL) {
+ /* Task with "task_id" not found or not started. */
+ return (OS_R_NOK);
+ }
+ task_context = os_active_TCB[task_id-1];
+ rt_rmv_list (task_context);
+ rt_rmv_dly (task_context);
+ os_active_TCB[task_id-1] = NULL;
+ rt_free_box (mp_stk, task_context->stack);
+ task_context->stack = NULL;
+ DBG_TASK_NOTIFY(task_context, __FALSE);
+ rt_free_box (mp_tcb, task_context);
+ }
+ return (OS_R_OK);
+}
+
+
+/*--------------------------- rt_sys_init -----------------------------------*/
+
+void rt_sys_init (FUNCP first_task, U32 prio_stksz, void *stk) {
+ /* Initialize system and start up task declared with "first_task". */
+ U32 i;
+
+ DBG_INIT();
+
+ /* Initialize dynamic memory and task TCB pointers to NULL. */
+ for (i = 0; i < os_maxtaskrun; i++) {
+ os_active_TCB[i] = NULL;
+ }
+ rt_init_box (&mp_tcb, mp_tcb_size, sizeof(struct OS_TCB));
+ rt_init_box (&mp_stk, mp_stk_size, BOX_ALIGN_8 | (U16)(os_stackinfo));
+ rt_init_box ((U32 *)m_tmr, mp_tmr_size, sizeof(struct OS_TMR));
+
+ /* Set up TCB of idle demon */
+ os_idle_TCB.task_id = 255;
+ os_idle_TCB.priv_stack = 0;
+ rt_init_context (&os_idle_TCB, 0, os_idle_demon);
+
+ /* Set up ready list: initially empty */
+ os_rdy.cb_type = HCB;
+ os_rdy.p_lnk = NULL;
+ /* Set up delay list: initially empty */
+ os_dly.cb_type = HCB;
+ os_dly.p_dlnk = NULL;
+ os_dly.p_blnk = NULL;
+ os_dly.delta_time = 0;
+
+ /* Fix SP and systemvariables to assume idle task is running */
+ /* Transform main program into idle task by assuming idle TCB */
+ rt_set_PSP (os_idle_TCB.tsk_stack+32);
+ os_tsk.run = &os_idle_TCB;
+ os_tsk.run->state = RUNNING;
+
+ /* Initialize ps queue */
+ os_psq->first = 0;
+ os_psq->last = 0;
+ os_psq->size = os_fifo_size;
+
+ rt_init_robin ();
+
+ /* Intitialize SVC and PendSV */
+ rt_svc_init ();
+
+ /* Intitialize system clock timer */
+ os_tick_irqn = os_tick_init ();
+ if (os_tick_irqn >= 0) {
+ OS_X_INIT(os_tick_irqn);
+ }
+
+ /* Start up first user task before entering the endless loop */
+ rt_tsk_create (first_task, prio_stksz, stk, NULL);
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff -r 000000000000 -r 01f31e923fe2 source/rtos/rt_Task.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/rtos/rt_Task.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,69 @@ +/** + * @file rt_Task.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Definitions */ + +/* Values for 'state' */ +#define INACTIVE 0 +#define READY 1 +#define RUNNING 2 +#define WAIT_DLY 3 +#define WAIT_ITV 4 +#define WAIT_OR 5 +#define WAIT_AND 6 +#define WAIT_SEM 7 +#define WAIT_MBX 8 +#define WAIT_MUT 9 + +/* Return codes */ +#define OS_R_TMO 0x01 +#define OS_R_EVT 0x02 +#define OS_R_SEM 0x03 +#define OS_R_MBX 0x04 +#define OS_R_MUT 0x05 + +#define OS_R_OK 0x00 +#define OS_R_NOK 0xff + +/* Variables */ +extern struct OS_TSK os_tsk; +extern struct OS_TCB os_idle_TCB; + +/* Functions */ +extern void rt_switch_req (P_TCB p_new); +extern void rt_dispatch (P_TCB next_TCB); +extern void rt_block (U16 timeout, U8 block_state); +extern void rt_tsk_pass (void); +extern OS_TID rt_tsk_self (void); +extern OS_RESULT rt_tsk_prio (OS_TID task_id, U8 new_prio); +extern OS_TID rt_tsk_create (FUNCP task, U32 prio_stksz, void *stk, void *argv); +extern OS_RESULT rt_tsk_delete (OS_TID task_id); +extern void rt_sys_init (FUNCP first_task, U32 prio_stksz, void *stk); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + + + + + +
diff -r 000000000000 -r 01f31e923fe2 source/rtos/rt_Time.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/rtos/rt_Time.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,81 @@
+/**
+ * @file rt_Time.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_Task.h"
+#include "rt_Time.h"
+
+/*----------------------------------------------------------------------------
+ * Global Variables
+ *---------------------------------------------------------------------------*/
+
+/* Free running system tick counter */
+U32 os_time;
+
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_time_get -----------------------------------*/
+
+U32 rt_time_get (void) {
+ /* Get system time tick */
+ return (os_time);
+}
+
+
+/*--------------------------- rt_dly_wait -----------------------------------*/
+
+void rt_dly_wait (U16 delay_time) {
+ /* Delay task by "delay_time" */
+ rt_block (delay_time, WAIT_DLY);
+}
+
+
+/*--------------------------- rt_itv_set ------------------------------------*/
+
+void rt_itv_set (U16 interval_time) {
+ /* Set interval length and define start of first interval */
+ os_tsk.run->interval_time = interval_time;
+ os_tsk.run->delta_time = interval_time + (U16)os_time;
+}
+
+
+/*--------------------------- rt_itv_wait -----------------------------------*/
+
+void rt_itv_wait (void) {
+ /* Wait for interval end and define start of next one */
+ U16 delta;
+
+ delta = os_tsk.run->delta_time - (U16)os_time;
+ os_tsk.run->delta_time += os_tsk.run->interval_time;
+ if ((delta & 0x8000) == 0) {
+ rt_block (delta, WAIT_ITV);
+ }
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
diff -r 000000000000 -r 01f31e923fe2 source/rtos/rt_Time.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/rtos/rt_Time.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,34 @@ +/** + * @file rt_Time.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Variables */ +extern U32 os_time; + +/* Functions */ +extern U32 rt_time_get (void); +extern void rt_dly_wait (U16 delay_time); +extern void rt_itv_set (U16 interval_time); +extern void rt_itv_wait (void); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ +
diff -r 000000000000 -r 01f31e923fe2 source/rtos/rt_Timer.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/rtos/rt_Timer.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,116 @@
+/**
+ * @file rt_Timer.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_Timer.h"
+#include "rt_MemBox.h"
+
+
+/*----------------------------------------------------------------------------
+ * Global Variables
+ *---------------------------------------------------------------------------*/
+
+/* User Timer list pointer */
+struct OS_XTMR os_tmr;
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+/*--------------------------- rt_tmr_tick -----------------------------------*/
+
+void rt_tmr_tick (void) {
+ /* Decrement delta count of timer list head. Timers having the value of */
+ /* zero are removed from the list and the callback function is called. */
+ P_TMR p;
+
+ if (os_tmr.next == NULL) {
+ return;
+ }
+ os_tmr.tcnt--;
+ while (os_tmr.tcnt == 0 && (p = os_tmr.next) != NULL) {
+ /* Call a user provided function to handle an elapsed timer */
+ os_tmr_call (p->info);
+ os_tmr.tcnt = p->tcnt;
+ os_tmr.next = p->next;
+ rt_free_box ((U32 *)m_tmr, p);
+ }
+}
+
+/*--------------------------- rt_tmr_create ---------------------------------*/
+
+OS_ID rt_tmr_create (U16 tcnt, U16 info) {
+ /* Create an user timer and put it into the chained timer list using */
+ /* a timeout count value of "tcnt". User parameter "info" is used as a */
+ /* parameter for the user provided callback function "os_tmr_call ()". */
+ P_TMR p_tmr, p;
+ U32 delta,itcnt = tcnt;
+
+ if (tcnt == 0 || m_tmr == NULL) {
+ return (NULL);
+ }
+ p_tmr = rt_alloc_box ((U32 *)m_tmr);
+ if (!p_tmr) {
+ return (NULL);
+ }
+ p_tmr->info = info;
+ p = (P_TMR)&os_tmr;
+ delta = p->tcnt;
+ while (delta < itcnt && p->next != NULL) {
+ p = p->next;
+ delta += p->tcnt;
+ }
+ /* Right place found, insert timer into the list */
+ p_tmr->next = p->next;
+ p_tmr->tcnt = (U16)(delta - itcnt);
+ p->next = p_tmr;
+ p->tcnt -= p_tmr->tcnt;
+ return (p_tmr);
+}
+
+/*--------------------------- rt_tmr_kill -----------------------------------*/
+
+OS_ID rt_tmr_kill (OS_ID timer) {
+ /* Remove user timer from the chained timer list. */
+ P_TMR p, p_tmr;
+
+ p_tmr = (P_TMR)timer;
+ p = (P_TMR)&os_tmr;
+ /* Search timer list for requested timer */
+ while (p->next != p_tmr) {
+ if (p->next == NULL) {
+ /* Failed, "timer" is not in the timer list */
+ return (p_tmr);
+ }
+ p = p->next;
+ }
+ /* Timer was found, remove it from the list */
+ p->next = p_tmr->next;
+ p->tcnt += p_tmr->tcnt;
+ rt_free_box ((U32 *)m_tmr, p_tmr);
+ /* Timer killed */
+ return (NULL);
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff -r 000000000000 -r 01f31e923fe2 source/rtos/rt_Timer.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/rtos/rt_Timer.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,33 @@ +/** + * @file rt_Timer.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Variables */ +extern struct OS_XTMR os_tmr; + +/* Functions */ +extern void rt_tmr_tick (void); +extern OS_ID rt_tmr_create (U16 tcnt, U16 info); +extern OS_ID rt_tmr_kill (OS_ID timer); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ +
diff -r 000000000000 -r 01f31e923fe2 source/rtos/rt_TypeDef.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/rtos/rt_TypeDef.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,152 @@
+/**
+ * @file rt_TypeDef.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Types */
+typedef char S8;
+typedef unsigned char U8;
+typedef short S16;
+typedef unsigned short U16;
+typedef int S32;
+typedef unsigned int U32;
+typedef long long S64;
+typedef unsigned long long U64;
+typedef unsigned char BIT;
+typedef unsigned int BOOL;
+typedef void (*FUNCP)(void);
+
+typedef U32 OS_TID;
+typedef void *OS_ID;
+typedef U32 OS_RESULT;
+
+typedef struct OS_TCB {
+ /* General part: identical for all implementations. */
+ U8 cb_type; /* Control Block Type */
+ U8 state; /* Task state */
+ U8 prio; /* Execution priority */
+ U8 task_id; /* Task ID value for optimized TCB access */
+ struct OS_TCB *p_lnk; /* Link pointer for ready/sem. wait list */
+ struct OS_TCB *p_rlnk; /* Link pointer for sem./mbx lst backwards */
+ struct OS_TCB *p_dlnk; /* Link pointer for delay list */
+ struct OS_TCB *p_blnk; /* Link pointer for delay list backwards */
+ U16 delta_time; /* Time until time out */
+ U16 interval_time; /* Time interval for periodic waits */
+ U16 events; /* Event flags */
+ U16 waits; /* Wait flags */
+ void **msg; /* Direct message passing when task waits */
+ U8 ret_val; /* Return value upon completion of a wait */
+
+ /* Hardware dependant part: specific for CM processor */
+ U8 ret_upd; /* Updated return value */
+ U16 priv_stack; /* Private stack size, 0= system assigned */
+ U32 tsk_stack; /* Current task Stack pointer (R13) */
+ U32 *stack; /* Pointer to Task Stack memory block */
+
+ /* Task entry point used for uVision debugger */
+ FUNCP ptask; /* Task entry address */
+} *P_TCB;
+#define TCB_RETVAL 32 /* 'ret_val' offset */
+#define TCB_RETUPD 33 /* 'ret_upd' offset */
+#define TCB_TSTACK 36 /* 'tsk_stack' offset */
+
+typedef struct OS_PSFE { /* Post Service Fifo Entry */
+ void *id; /* Object Identification */
+ U32 arg; /* Object Argument */
+} *P_PSFE;
+
+typedef struct OS_PSQ { /* Post Service Queue */
+ U8 first; /* FIFO Head Index */
+ U8 last; /* FIFO Tail Index */
+ U8 count; /* Number of stored items in FIFO */
+ U8 size; /* FIFO Size */
+ struct OS_PSFE q[1]; /* FIFO Content */
+} *P_PSQ;
+
+typedef struct OS_TSK {
+ P_TCB run; /* Current running task */
+ P_TCB new; /* Scheduled task to run */
+} *P_TSK;
+
+typedef struct OS_ROBIN { /* Round Robin Control */
+ P_TCB task; /* Round Robin task */
+ U16 time; /* Round Robin switch time */
+ U16 tout; /* Round Robin timeout */
+} *P_ROBIN;
+
+typedef struct OS_XCB {
+ U8 cb_type; /* Control Block Type */
+ struct OS_TCB *p_lnk; /* Link pointer for ready/sem. wait list */
+ struct OS_TCB *p_rlnk; /* Link pointer for sem./mbx lst backwards */
+ struct OS_TCB *p_dlnk; /* Link pointer for delay list */
+ struct OS_TCB *p_blnk; /* Link pointer for delay list backwards */
+ U16 delta_time; /* Time until time out */
+} *P_XCB;
+
+typedef struct OS_MCB {
+ U8 cb_type; /* Control Block Type */
+ U8 isr_st; /* State flag variable for isr functions */
+ struct OS_TCB *p_lnk; /* Chain of tasks waiting for message */
+ U16 first; /* Index of the message list begin */
+ U16 last; /* Index of the message list end */
+ U16 count; /* Actual number of stored messages */
+ U16 size; /* Maximum number of stored messages */
+ void *msg[1]; /* FIFO for Message pointers 1st element */
+} *P_MCB;
+
+typedef struct OS_SCB {
+ U8 cb_type; /* Control Block Type */
+ U16 tokens; /* Semaphore tokens */
+ struct OS_TCB *p_lnk; /* Chain of tasks waiting for tokens */
+} *P_SCB;
+
+typedef struct OS_MUCB {
+ U8 cb_type; /* Control Block Type */
+ U8 prio; /* Owner task default priority */
+ U16 level; /* Call nesting level */
+ struct OS_TCB *p_lnk; /* Chain of tasks waiting for mutex */
+ struct OS_TCB *owner; /* Mutex owner task */
+} *P_MUCB;
+
+typedef struct OS_XTMR {
+ struct OS_TMR *next;
+ U16 tcnt;
+} *P_XTMR;
+
+typedef struct OS_TMR {
+ struct OS_TMR *next; /* Link pointer to Next timer */
+ U16 tcnt; /* Timer delay count */
+ U16 info; /* User defined call info */
+} *P_TMR;
+
+typedef struct OS_BM {
+ void *free; /* Pointer to first free memory block */
+ void *end; /* Pointer to memory block end */
+ U32 blk_size; /* Memory block size */
+} *P_BM;
+
+/* Definitions */
+#define __TRUE 1
+#define __FALSE 0
+#define NULL ((void *) 0)
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
diff -r 000000000000 -r 01f31e923fe2 source/rtos_none/SysTick_Handler.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/rtos_none/SysTick_Handler.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,119 @@
+/**
+ * @file SysTick_Handler.c
+ * @brief No RTOS port only needs a systick handler
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "SysTick_Handler.h"
+#include "device.h"
+
+//SysTick Timer Configuration
+#ifndef OS_CLOCK
+#error "OS_CLOCK should be defined by HIC configuration"
+#endif
+
+//Set the timer tick value for selected timer.
+#ifndef OS_TICK
+#error "OS_TICK should be defined by RTOS configuration"
+#endif
+
+#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
+
+
+static volatile uint32_t tick_counter = 0;
+static volatile uint32_t event_flags =0;
+static volatile uint32_t wait_counter = 0;
+
+static osTimerFunc_t sysTickCb = NULL;
+static uint32_t tickFreq = 0;
+static osThreadFunc_t mainFuncCb = NULL;
+
+void sysTickInit(void)
+{
+ tick_counter = 0;
+ event_flags=0;
+ wait_counter = 0;
+ sysTickCb = NULL;
+ tickFreq = 0;
+ mainFuncCb = NULL;
+ SysTick_Config(OS_TRV);
+}
+
+
+void SysTick_Handler(void)
+{
+ if (sysTickCb && tickFreq && (tick_counter % tickFreq)==0) {
+ sysTickCb(NULL);
+ }
+ tick_counter++;
+ if(wait_counter){
+ --wait_counter;
+ }
+}
+
+void sysTickRegCallback(osTimerFunc_t callback)
+{
+ sysTickCb = callback;
+}
+
+void sysTickFreqSet(uint32_t ticks)
+{
+ tickFreq = ticks;
+}
+
+void sysTickWait(uint32_t wait)
+{
+ wait_counter = wait;
+ while(wait_counter);
+}
+
+void sysTickEvtSet(uint32_t flag)
+{
+ __disable_irq();
+ event_flags |= flag;
+ __enable_irq();
+}
+
+uint32_t sysTickEvtWaitOr(uint32_t flag)
+{
+ uint32_t return_flags=0;
+ while ((flag&event_flags)==0);
+ return_flags = event_flags;
+ __disable_irq();
+ event_flags &= ~return_flags;
+ __enable_irq();
+ return return_flags;
+}
+
+uint32_t sysTickTime(void)
+{
+ return tick_counter;
+}
+
+void sysTickRegMainFunc(osThreadFunc_t func)
+{
+ mainFuncCb = func;
+}
+
+void sysTickStartMain(void)
+{
+ if(mainFuncCb){
+ mainFuncCb(NULL);
+ }
+}
+
diff -r 000000000000 -r 01f31e923fe2 source/rtos_none/SysTick_Handler.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/rtos_none/SysTick_Handler.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,48 @@
+/**
+ * @file Systick_Handler.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef SYSTICK_HANDLER_H_
+#define SYSTICK_HANDLER_H_
+
+#include "cmsis_os2.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//functions based on system tick
+void sysTickInit(void);
+void sysTickRegCallback(osTimerFunc_t callback);
+void sysTickFreqSet(uint32_t ticks);
+void sysTickWait(uint32_t wait);
+void sysTickEvtSet(uint32_t flag);
+uint32_t sysTickEvtWaitOr(uint32_t flag);
+uint32_t sysTickTime(void);
+void sysTickRegMainFunc(osThreadFunc_t func);
+void sysTickStartMain(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/rtos_none/cmsis_os2.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/rtos_none/cmsis_os2.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,756 @@
+/*
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date: 18. June 2018
+ * $Revision: V2.1.3
+ *
+ * Project: CMSIS-RTOS2 API
+ * Title: cmsis_os2.h header file
+ *
+ * Version 2.1.3
+ * Additional functions allowed to be called from Interrupt Service Routines:
+ * - osThreadGetId
+ * Version 2.1.2
+ * Additional functions allowed to be called from Interrupt Service Routines:
+ * - osKernelGetInfo, osKernelGetState
+ * Version 2.1.1
+ * Additional functions allowed to be called from Interrupt Service Routines:
+ * - osKernelGetTickCount, osKernelGetTickFreq
+ * Changed Kernel Tick type to uint32_t:
+ * - updated: osKernelGetTickCount, osDelayUntil
+ * Version 2.1.0
+ * Support for critical and uncritical sections (nesting safe):
+ * - updated: osKernelLock, osKernelUnlock
+ * - added: osKernelRestoreLock
+ * Updated Thread and Event Flags:
+ * - changed flags parameter and return type from int32_t to uint32_t
+ * Version 2.0.0
+ * Initial Release
+ *---------------------------------------------------------------------------*/
+
+#ifndef CMSIS_OS2_H_
+#define CMSIS_OS2_H_
+
+#ifndef __NO_RETURN
+#if defined(__CC_ARM)
+#define __NO_RETURN __declspec(noreturn)
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#define __NO_RETURN __attribute__((__noreturn__))
+#elif defined(__GNUC__)
+#define __NO_RETURN __attribute__((__noreturn__))
+#elif defined(__ICCARM__)
+#define __NO_RETURN __noreturn
+#else
+#define __NO_RETURN
+#endif
+#endif
+
+#include <stdint.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+// ==== Enumerations, structures, defines ====
+
+/// Version information.
+typedef struct {
+ uint32_t api; ///< API version (major.minor.rev: mmnnnrrrr dec).
+ uint32_t kernel; ///< Kernel version (major.minor.rev: mmnnnrrrr dec).
+} osVersion_t;
+
+/// Kernel state.
+typedef enum {
+ osKernelInactive = 0, ///< Inactive.
+ osKernelReady = 1, ///< Ready.
+ osKernelRunning = 2, ///< Running.
+ osKernelLocked = 3, ///< Locked.
+ osKernelSuspended = 4, ///< Suspended.
+ osKernelError = -1, ///< Error.
+ osKernelReserved = 0x7FFFFFFFU ///< Prevents enum down-size compiler optimization.
+} osKernelState_t;
+
+/// Thread state.
+typedef enum {
+ osThreadInactive = 0, ///< Inactive.
+ osThreadReady = 1, ///< Ready.
+ osThreadRunning = 2, ///< Running.
+ osThreadBlocked = 3, ///< Blocked.
+ osThreadTerminated = 4, ///< Terminated.
+ osThreadError = -1, ///< Error.
+ osThreadReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
+} osThreadState_t;
+
+/// Priority values.
+typedef enum {
+ osPriorityNone = 0, ///< No priority (not initialized).
+ osPriorityIdle = 1, ///< Reserved for Idle thread.
+ osPriorityLow = 8, ///< Priority: low
+ osPriorityLow1 = 8+1, ///< Priority: low + 1
+ osPriorityLow2 = 8+2, ///< Priority: low + 2
+ osPriorityLow3 = 8+3, ///< Priority: low + 3
+ osPriorityLow4 = 8+4, ///< Priority: low + 4
+ osPriorityLow5 = 8+5, ///< Priority: low + 5
+ osPriorityLow6 = 8+6, ///< Priority: low + 6
+ osPriorityLow7 = 8+7, ///< Priority: low + 7
+ osPriorityBelowNormal = 16, ///< Priority: below normal
+ osPriorityBelowNormal1 = 16+1, ///< Priority: below normal + 1
+ osPriorityBelowNormal2 = 16+2, ///< Priority: below normal + 2
+ osPriorityBelowNormal3 = 16+3, ///< Priority: below normal + 3
+ osPriorityBelowNormal4 = 16+4, ///< Priority: below normal + 4
+ osPriorityBelowNormal5 = 16+5, ///< Priority: below normal + 5
+ osPriorityBelowNormal6 = 16+6, ///< Priority: below normal + 6
+ osPriorityBelowNormal7 = 16+7, ///< Priority: below normal + 7
+ osPriorityNormal = 24, ///< Priority: normal
+ osPriorityNormal1 = 24+1, ///< Priority: normal + 1
+ osPriorityNormal2 = 24+2, ///< Priority: normal + 2
+ osPriorityNormal3 = 24+3, ///< Priority: normal + 3
+ osPriorityNormal4 = 24+4, ///< Priority: normal + 4
+ osPriorityNormal5 = 24+5, ///< Priority: normal + 5
+ osPriorityNormal6 = 24+6, ///< Priority: normal + 6
+ osPriorityNormal7 = 24+7, ///< Priority: normal + 7
+ osPriorityAboveNormal = 32, ///< Priority: above normal
+ osPriorityAboveNormal1 = 32+1, ///< Priority: above normal + 1
+ osPriorityAboveNormal2 = 32+2, ///< Priority: above normal + 2
+ osPriorityAboveNormal3 = 32+3, ///< Priority: above normal + 3
+ osPriorityAboveNormal4 = 32+4, ///< Priority: above normal + 4
+ osPriorityAboveNormal5 = 32+5, ///< Priority: above normal + 5
+ osPriorityAboveNormal6 = 32+6, ///< Priority: above normal + 6
+ osPriorityAboveNormal7 = 32+7, ///< Priority: above normal + 7
+ osPriorityHigh = 40, ///< Priority: high
+ osPriorityHigh1 = 40+1, ///< Priority: high + 1
+ osPriorityHigh2 = 40+2, ///< Priority: high + 2
+ osPriorityHigh3 = 40+3, ///< Priority: high + 3
+ osPriorityHigh4 = 40+4, ///< Priority: high + 4
+ osPriorityHigh5 = 40+5, ///< Priority: high + 5
+ osPriorityHigh6 = 40+6, ///< Priority: high + 6
+ osPriorityHigh7 = 40+7, ///< Priority: high + 7
+ osPriorityRealtime = 48, ///< Priority: realtime
+ osPriorityRealtime1 = 48+1, ///< Priority: realtime + 1
+ osPriorityRealtime2 = 48+2, ///< Priority: realtime + 2
+ osPriorityRealtime3 = 48+3, ///< Priority: realtime + 3
+ osPriorityRealtime4 = 48+4, ///< Priority: realtime + 4
+ osPriorityRealtime5 = 48+5, ///< Priority: realtime + 5
+ osPriorityRealtime6 = 48+6, ///< Priority: realtime + 6
+ osPriorityRealtime7 = 48+7, ///< Priority: realtime + 7
+ osPriorityISR = 56, ///< Reserved for ISR deferred thread.
+ osPriorityError = -1, ///< System cannot determine priority or illegal priority.
+ osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
+} osPriority_t;
+
+/// Entry point of a thread.
+typedef void (*osThreadFunc_t) (void *argument);
+
+/// Timer callback function.
+typedef void (*osTimerFunc_t) (void *argument);
+
+/// Timer type.
+typedef enum {
+ osTimerOnce = 0, ///< One-shot timer.
+ osTimerPeriodic = 1 ///< Repeating timer.
+} osTimerType_t;
+
+// Timeout value.
+#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value.
+
+// Flags options (\ref osThreadFlagsWait and \ref osEventFlagsWait).
+#define osFlagsWaitAny 0x00000000U ///< Wait for any flag (default).
+#define osFlagsWaitAll 0x00000001U ///< Wait for all flags.
+#define osFlagsNoClear 0x00000002U ///< Do not clear flags which have been specified to wait for.
+
+// Flags errors (returned by osThreadFlagsXxxx and osEventFlagsXxxx).
+#define osFlagsError 0x80000000U ///< Error indicator.
+#define osFlagsErrorUnknown 0xFFFFFFFFU ///< osError (-1).
+#define osFlagsErrorTimeout 0xFFFFFFFEU ///< osErrorTimeout (-2).
+#define osFlagsErrorResource 0xFFFFFFFDU ///< osErrorResource (-3).
+#define osFlagsErrorParameter 0xFFFFFFFCU ///< osErrorParameter (-4).
+#define osFlagsErrorISR 0xFFFFFFFAU ///< osErrorISR (-6).
+
+// Thread attributes (attr_bits in \ref osThreadAttr_t).
+#define osThreadDetached 0x00000000U ///< Thread created in detached mode (default)
+#define osThreadJoinable 0x00000001U ///< Thread created in joinable mode
+
+// Mutex attributes (attr_bits in \ref osMutexAttr_t).
+#define osMutexRecursive 0x00000001U ///< Recursive mutex.
+#define osMutexPrioInherit 0x00000002U ///< Priority inherit protocol.
+#define osMutexRobust 0x00000008U ///< Robust mutex.
+
+/// Status code values returned by CMSIS-RTOS functions.
+typedef enum {
+ osOK = 0, ///< Operation completed successfully.
+ osError = -1, ///< Unspecified RTOS error: run-time error but no other error message fits.
+ osErrorTimeout = -2, ///< Operation not completed within the timeout period.
+ osErrorResource = -3, ///< Resource not available.
+ osErrorParameter = -4, ///< Parameter error.
+ osErrorNoMemory = -5, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation.
+ osErrorISR = -6, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines.
+ osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
+} osStatus_t;
+
+
+/// \details Thread ID identifies the thread.
+typedef void *osThreadId_t;
+
+/// \details Timer ID identifies the timer.
+typedef void *osTimerId_t;
+
+/// \details Event Flags ID identifies the event flags.
+typedef void *osEventFlagsId_t;
+
+/// \details Mutex ID identifies the mutex.
+typedef void *osMutexId_t;
+
+/// \details Semaphore ID identifies the semaphore.
+typedef void *osSemaphoreId_t;
+
+/// \details Memory Pool ID identifies the memory pool.
+typedef void *osMemoryPoolId_t;
+
+/// \details Message Queue ID identifies the message queue.
+typedef void *osMessageQueueId_t;
+
+
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+
+
+/// Attributes structure for thread.
+typedef struct {
+ const char *name; ///< name of the thread
+ uint32_t attr_bits; ///< attribute bits
+ void *cb_mem; ///< memory for control block
+ uint32_t cb_size; ///< size of provided memory for control block
+ void *stack_mem; ///< memory for stack
+ uint32_t stack_size; ///< size of stack
+ osPriority_t priority; ///< initial thread priority (default: osPriorityNormal)
+ TZ_ModuleId_t tz_module; ///< TrustZone module identifier
+ uint32_t reserved; ///< reserved (must be 0)
+} osThreadAttr_t;
+
+/// Attributes structure for timer.
+typedef struct {
+ const char *name; ///< name of the timer
+ uint32_t attr_bits; ///< attribute bits
+ void *cb_mem; ///< memory for control block
+ uint32_t cb_size; ///< size of provided memory for control block
+} osTimerAttr_t;
+
+/// Attributes structure for event flags.
+typedef struct {
+ const char *name; ///< name of the event flags
+ uint32_t attr_bits; ///< attribute bits
+ void *cb_mem; ///< memory for control block
+ uint32_t cb_size; ///< size of provided memory for control block
+} osEventFlagsAttr_t;
+
+/// Attributes structure for mutex.
+typedef struct {
+ const char *name; ///< name of the mutex
+ uint32_t attr_bits; ///< attribute bits
+ void *cb_mem; ///< memory for control block
+ uint32_t cb_size; ///< size of provided memory for control block
+} osMutexAttr_t;
+
+/// Attributes structure for semaphore.
+typedef struct {
+ const char *name; ///< name of the semaphore
+ uint32_t attr_bits; ///< attribute bits
+ void *cb_mem; ///< memory for control block
+ uint32_t cb_size; ///< size of provided memory for control block
+} osSemaphoreAttr_t;
+
+/// Attributes structure for memory pool.
+typedef struct {
+ const char *name; ///< name of the memory pool
+ uint32_t attr_bits; ///< attribute bits
+ void *cb_mem; ///< memory for control block
+ uint32_t cb_size; ///< size of provided memory for control block
+ void *mp_mem; ///< memory for data storage
+ uint32_t mp_size; ///< size of provided memory for data storage
+} osMemoryPoolAttr_t;
+
+/// Attributes structure for message queue.
+typedef struct {
+ const char *name; ///< name of the message queue
+ uint32_t attr_bits; ///< attribute bits
+ void *cb_mem; ///< memory for control block
+ uint32_t cb_size; ///< size of provided memory for control block
+ void *mq_mem; ///< memory for data storage
+ uint32_t mq_size; ///< size of provided memory for data storage
+} osMessageQueueAttr_t;
+
+
+// ==== Kernel Management Functions ====
+
+/// Initialize the RTOS Kernel.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osKernelInitialize (void);
+
+/// Get RTOS Kernel Information.
+/// \param[out] version pointer to buffer for retrieving version information.
+/// \param[out] id_buf pointer to buffer for retrieving kernel identification string.
+/// \param[in] id_size size of buffer for kernel identification string.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size);
+
+/// Get the current RTOS Kernel state.
+/// \return current RTOS Kernel state.
+osKernelState_t osKernelGetState (void);
+
+/// Start the RTOS Kernel scheduler.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osKernelStart (void);
+
+/// Lock the RTOS Kernel scheduler.
+/// \return previous lock state (1 - locked, 0 - not locked, error code if negative).
+int32_t osKernelLock (void);
+
+/// Unlock the RTOS Kernel scheduler.
+/// \return previous lock state (1 - locked, 0 - not locked, error code if negative).
+int32_t osKernelUnlock (void);
+
+/// Restore the RTOS Kernel scheduler lock state.
+/// \param[in] lock lock state obtained by \ref osKernelLock or \ref osKernelUnlock.
+/// \return new lock state (1 - locked, 0 - not locked, error code if negative).
+int32_t osKernelRestoreLock (int32_t lock);
+
+/// Suspend the RTOS Kernel scheduler.
+/// \return time in ticks, for how long the system can sleep or power-down.
+uint32_t osKernelSuspend (void);
+
+/// Resume the RTOS Kernel scheduler.
+/// \param[in] sleep_ticks time in ticks for how long the system was in sleep or power-down mode.
+void osKernelResume (uint32_t sleep_ticks);
+
+/// Get the RTOS kernel tick count.
+/// \return RTOS kernel current tick count.
+uint32_t osKernelGetTickCount (void);
+
+/// Get the RTOS kernel tick frequency.
+/// \return frequency of the kernel tick in hertz, i.e. kernel ticks per second.
+uint32_t osKernelGetTickFreq (void);
+
+/// Get the RTOS kernel system timer count.
+/// \return RTOS kernel current system timer count as 32-bit value.
+uint32_t osKernelGetSysTimerCount (void);
+
+/// Get the RTOS kernel system timer frequency.
+/// \return frequency of the system timer in hertz, i.e. timer ticks per second.
+uint32_t osKernelGetSysTimerFreq (void);
+
+
+// ==== Thread Management Functions ====
+
+/// Create a thread and add it to Active Threads.
+/// \param[in] func thread function.
+/// \param[in] argument pointer that is passed to the thread function as start argument.
+/// \param[in] attr thread attributes; NULL: default values.
+/// \return thread ID for reference by other functions or NULL in case of error.
+osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr);
+
+/// Get name of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return name as null-terminated string.
+const char *osThreadGetName (osThreadId_t thread_id);
+
+/// Return the thread ID of the current running thread.
+/// \return thread ID for reference by other functions or NULL in case of error.
+osThreadId_t osThreadGetId (void);
+
+/// Get current thread state of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return current thread state of the specified thread.
+osThreadState_t osThreadGetState (osThreadId_t thread_id);
+
+/// Get stack size of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return stack size in bytes.
+uint32_t osThreadGetStackSize (osThreadId_t thread_id);
+
+/// Get available stack space of a thread based on stack watermark recording during execution.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return remaining stack space in bytes.
+uint32_t osThreadGetStackSpace (osThreadId_t thread_id);
+
+/// Change priority of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \param[in] priority new priority value for the thread function.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority);
+
+/// Get current priority of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return current priority value of the specified thread.
+osPriority_t osThreadGetPriority (osThreadId_t thread_id);
+
+/// Pass control to next thread that is in state \b READY.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadYield (void);
+
+/// Suspend execution of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadSuspend (osThreadId_t thread_id);
+
+/// Resume execution of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadResume (osThreadId_t thread_id);
+
+/// Detach a thread (thread storage can be reclaimed when thread terminates).
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadDetach (osThreadId_t thread_id);
+
+/// Wait for specified thread to terminate.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadJoin (osThreadId_t thread_id);
+
+/// Terminate execution of current running thread.
+__NO_RETURN void osThreadExit (void);
+
+/// Terminate execution of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadTerminate (osThreadId_t thread_id);
+
+/// Get number of active threads.
+/// \return number of active threads.
+uint32_t osThreadGetCount (void);
+
+/// Enumerate active threads.
+/// \param[out] thread_array pointer to array for retrieving thread IDs.
+/// \param[in] array_items maximum number of items in array for retrieving thread IDs.
+/// \return number of enumerated threads.
+uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items);
+
+
+// ==== Thread Flags Functions ====
+
+/// Set the specified Thread Flags of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \param[in] flags specifies the flags of the thread that shall be set.
+/// \return thread flags after setting or error code if highest bit set.
+uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags);
+
+/// Clear the specified Thread Flags of current running thread.
+/// \param[in] flags specifies the flags of the thread that shall be cleared.
+/// \return thread flags before clearing or error code if highest bit set.
+uint32_t osThreadFlagsClear (uint32_t flags);
+
+/// Get the current Thread Flags of current running thread.
+/// \return current thread flags.
+uint32_t osThreadFlagsGet (void);
+
+/// Wait for one or more Thread Flags of the current running thread to become signaled.
+/// \param[in] flags specifies the flags to wait for.
+/// \param[in] options specifies flags options (osFlagsXxxx).
+/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return thread flags before clearing or error code if highest bit set.
+uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout);
+
+
+// ==== Generic Wait Functions ====
+
+/// Wait for Timeout (Time Delay).
+/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value
+/// \return status code that indicates the execution status of the function.
+osStatus_t osDelay (uint32_t ticks);
+
+/// Wait until specified time.
+/// \param[in] ticks absolute time in ticks
+/// \return status code that indicates the execution status of the function.
+osStatus_t osDelayUntil (uint32_t ticks);
+
+
+// ==== Timer Management Functions ====
+
+/// Create and Initialize a timer.
+/// \param[in] func function pointer to callback function.
+/// \param[in] type \ref osTimerOnce for one-shot or \ref osTimerPeriodic for periodic behavior.
+/// \param[in] argument argument to the timer callback function.
+/// \param[in] attr timer attributes; NULL: default values.
+/// \return timer ID for reference by other functions or NULL in case of error.
+osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr);
+
+/// Get name of a timer.
+/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
+/// \return name as null-terminated string.
+const char *osTimerGetName (osTimerId_t timer_id);
+
+/// Start or restart a timer.
+/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
+/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value of the timer.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks);
+
+/// Stop a timer.
+/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osTimerStop (osTimerId_t timer_id);
+
+/// Check if a timer is running.
+/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
+/// \return 0 not running, 1 running.
+uint32_t osTimerIsRunning (osTimerId_t timer_id);
+
+/// Delete a timer.
+/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osTimerDelete (osTimerId_t timer_id);
+
+
+// ==== Event Flags Management Functions ====
+
+/// Create and Initialize an Event Flags object.
+/// \param[in] attr event flags attributes; NULL: default values.
+/// \return event flags ID for reference by other functions or NULL in case of error.
+osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr);
+
+/// Get name of an Event Flags object.
+/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
+/// \return name as null-terminated string.
+const char *osEventFlagsGetName (osEventFlagsId_t ef_id);
+
+/// Set the specified Event Flags.
+/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
+/// \param[in] flags specifies the flags that shall be set.
+/// \return event flags after setting or error code if highest bit set.
+uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags);
+
+/// Clear the specified Event Flags.
+/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
+/// \param[in] flags specifies the flags that shall be cleared.
+/// \return event flags before clearing or error code if highest bit set.
+uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags);
+
+/// Get the current Event Flags.
+/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
+/// \return current event flags.
+uint32_t osEventFlagsGet (osEventFlagsId_t ef_id);
+
+/// Wait for one or more Event Flags to become signaled.
+/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
+/// \param[in] flags specifies the flags to wait for.
+/// \param[in] options specifies flags options (osFlagsXxxx).
+/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return event flags before clearing or error code if highest bit set.
+uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout);
+
+/// Delete an Event Flags object.
+/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id);
+
+
+// ==== Mutex Management Functions ====
+
+/// Create and Initialize a Mutex object.
+/// \param[in] attr mutex attributes; NULL: default values.
+/// \return mutex ID for reference by other functions or NULL in case of error.
+osMutexId_t osMutexNew (const osMutexAttr_t *attr);
+
+/// Get name of a Mutex object.
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
+/// \return name as null-terminated string.
+const char *osMutexGetName (osMutexId_t mutex_id);
+
+/// Acquire a Mutex or timeout if it is locked.
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
+/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout);
+
+/// Release a Mutex that was acquired by \ref osMutexAcquire.
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMutexRelease (osMutexId_t mutex_id);
+
+/// Get Thread which owns a Mutex object.
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
+/// \return thread ID of owner thread or NULL when mutex was not acquired.
+osThreadId_t osMutexGetOwner (osMutexId_t mutex_id);
+
+/// Delete a Mutex object.
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMutexDelete (osMutexId_t mutex_id);
+
+
+// ==== Semaphore Management Functions ====
+
+/// Create and Initialize a Semaphore object.
+/// \param[in] max_count maximum number of available tokens.
+/// \param[in] initial_count initial number of available tokens.
+/// \param[in] attr semaphore attributes; NULL: default values.
+/// \return semaphore ID for reference by other functions or NULL in case of error.
+osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr);
+
+/// Get name of a Semaphore object.
+/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
+/// \return name as null-terminated string.
+const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id);
+
+/// Acquire a Semaphore token or timeout if no tokens are available.
+/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
+/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout);
+
+/// Release a Semaphore token up to the initial maximum count.
+/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id);
+
+/// Get current Semaphore token count.
+/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
+/// \return number of tokens available.
+uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id);
+
+/// Delete a Semaphore object.
+/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id);
+
+
+// ==== Memory Pool Management Functions ====
+
+/// Create and Initialize a Memory Pool object.
+/// \param[in] block_count maximum number of memory blocks in memory pool.
+/// \param[in] block_size memory block size in bytes.
+/// \param[in] attr memory pool attributes; NULL: default values.
+/// \return memory pool ID for reference by other functions or NULL in case of error.
+osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr);
+
+/// Get name of a Memory Pool object.
+/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return name as null-terminated string.
+const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id);
+
+/// Allocate a memory block from a Memory Pool.
+/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
+/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return address of the allocated memory block or NULL in case of no memory is available.
+void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout);
+
+/// Return an allocated memory block back to a Memory Pool.
+/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
+/// \param[in] block address of the allocated memory block to be returned to the memory pool.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block);
+
+/// Get maximum number of memory blocks in a Memory Pool.
+/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return maximum number of memory blocks.
+uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id);
+
+/// Get memory block size in a Memory Pool.
+/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return memory block size in bytes.
+uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id);
+
+/// Get number of memory blocks used in a Memory Pool.
+/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return number of memory blocks used.
+uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id);
+
+/// Get number of memory blocks available in a Memory Pool.
+/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return number of memory blocks available.
+uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id);
+
+/// Delete a Memory Pool object.
+/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id);
+
+
+// ==== Message Queue Management Functions ====
+
+/// Create and Initialize a Message Queue object.
+/// \param[in] msg_count maximum number of messages in queue.
+/// \param[in] msg_size maximum message size in bytes.
+/// \param[in] attr message queue attributes; NULL: default values.
+/// \return message queue ID for reference by other functions or NULL in case of error.
+osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr);
+
+/// Get name of a Message Queue object.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \return name as null-terminated string.
+const char *osMessageQueueGetName (osMessageQueueId_t mq_id);
+
+/// Put a Message into a Queue or timeout if Queue is full.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \param[in] msg_ptr pointer to buffer with message to put into a queue.
+/// \param[in] msg_prio message priority.
+/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout);
+
+/// Get a Message from a Queue or timeout if Queue is empty.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \param[out] msg_ptr pointer to buffer for message to get from a queue.
+/// \param[out] msg_prio pointer to buffer for message priority or NULL.
+/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout);
+
+/// Get maximum number of messages in a Message Queue.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \return maximum number of messages.
+uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id);
+
+/// Get maximum message size in a Memory Pool.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \return maximum message size in bytes.
+uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id);
+
+/// Get number of queued messages in a Message Queue.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \return number of queued messages.
+uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id);
+
+/// Get number of available slots for messages in a Message Queue.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \return number of available slots for messages.
+uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id);
+
+/// Reset a Message Queue to initial empty state.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id);
+
+/// Delete a Message Queue object.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // CMSIS_OS2_H_
diff -r 000000000000 -r 01f31e923fe2 source/rtos_none/cmsis_os2_port.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/rtos_none/cmsis_os2_port.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,89 @@
+/**
+ * @file cmsis_os2_port.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "cmsis_os2.h"
+#include "SysTick_Handler.h"
+
+osStatus_t osKernelInitialize(void)
+{
+ sysTickInit();
+ return osOK;
+}
+
+osThreadId_t osThreadNew(osThreadFunc_t func, void *argument, const osThreadAttr_t *attr)
+{
+ sysTickRegMainFunc(func);
+ return (osThreadId_t)1;
+}
+
+osStatus_t osKernelStart(void)
+{
+ sysTickStartMain();
+ return osOK;
+}
+
+uint32_t osThreadFlagsSet(osThreadId_t thread_id, uint32_t flags)
+{
+ sysTickEvtSet(flags);
+ return flags;
+}
+
+osStatus_t osDelay(uint32_t ticks)
+{
+ sysTickWait(ticks);
+ return osOK;
+}
+
+osTimerId_t osTimerNew(osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr)
+{
+ sysTickRegCallback(func);
+ return (osTimerId_t)1;
+}
+
+osStatus_t osTimerStart(osTimerId_t timer_id, uint32_t ticks)
+{
+ sysTickFreqSet(ticks);
+ return osOK;
+}
+
+uint32_t osThreadFlagsWait(uint32_t flags, uint32_t options, uint32_t timeout)
+{
+ return sysTickEvtWaitOr(flags);
+}
+
+osMutexId_t osMutexNew(const osMutexAttr_t *attr)
+{
+ return NULL;
+}
+
+osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout)
+{
+ return osOK;
+}
+
+osStatus_t osMutexRelease (osMutexId_t mutex_id)
+{
+ return osOK;
+}
+
+osThreadId_t osThreadGetId (void)
+{
+ return (osThreadId_t)1;
+}
diff -r 000000000000 -r 01f31e923fe2 source/target/target_board.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/target/target_board.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,77 @@
+/**
+ * @file target_board.c
+ * @brief Implementation of target_family.h
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+#include "target_board.h"
+
+// Default empty board info.
+__attribute__((weak))
+const board_info_t g_board_info = {
+ .info_version = kBoardInfoVersion,
+ .board_id = "0000",
+ .daplink_url_name = "MBED HTM",
+ .daplink_drive_name = "DAPLINK ",
+ .daplink_target_url = "https://mbed.org/device/?code=@U?version=@V?target_id=@T",
+};
+
+
+const char * get_board_id(void)
+{
+ if (g_board_info.target_cfg && g_board_info.target_cfg->rt_board_id) {
+ return g_board_info.target_cfg->rt_board_id; //flexible board id
+ }else{
+ return g_board_info.board_id;
+ }
+}
+
+uint16_t get_family_id(void)
+{
+ if (g_board_info.target_cfg && g_board_info.target_cfg->rt_family_id) {
+ return g_board_info.target_cfg->rt_family_id; //flexible family id
+ }else{
+ return g_board_info.family_id;
+ }
+}
+
+#if (defined(__ICCARM__))
+#pragma optimize = none
+uint8_t flash_algo_valid(void)
+#elif (defined(__CC_ARM))
+#pragma push
+#pragma O0
+uint8_t flash_algo_valid(void)
+#elif (!defined(__GNUC__))
+/* #pragma GCC push_options */
+/* #pragma GCC optimize("O0") */
+uint8_t __attribute__((optimize("O0"))) flash_algo_valid(void)
+#else
+#error "Unknown compiler"
+#endif
+{
+ return (g_board_info.target_cfg != 0);
+}
+
+#if (defined(__CC_ARM))
+#pragma pop
+#endif
+#if (defined(__GNUC__))
+/* #pragma GCC pop_options */
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/target/target_board.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/target/target_board.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,114 @@
+/**
+ * @file target_board.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2018-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef TARGET_BOARD_H
+#define TARGET_BOARD_H
+
+#include <stdint.h>
+#include "target_config.h"
+#include "target_family.h"
+#include "virtual_fs.h"
+
+//! @brief Current board info version.
+//!
+//! - Version 1: Initial version.
+enum _board_info_version {
+ kBoardInfoVersion = 1, //!< The current board info version.
+};
+
+//! @brief Flags for board_info
+enum _board_info_flags {
+ kEnablePageErase = (1 << 0), /*!< Enable page programming and sector erase for drag and drop */
+ kEnableUnderResetConnect = (1 << 1), /*!< Enable under reset connection when enabling debug mode */
+};
+
+/*!
+ * @brief Board customization info.
+ *
+ * Each board must have a unique 4-character Board ID. For Mbed OS targets, the Board ID is the same
+ * as the Mbed Platform ID. These IDs are nominally allocated by Arm in order to guarantee there are
+ * no conflicts between boards. Please see the DAPLink documentation for more.
+ *
+ * The family_id member tells DAPLink which device family the on-board target belongs to. This then
+ * determines certain behaviours, such as how to reset the target. Family IDs are defined in the
+ * #family_id_t enumeration.
+ *
+ * The board initialization function pointers allow the board to override the routines defined
+ * by the device family.
+ */
+typedef struct __attribute__((__packed__)) board_info {
+ uint16_t info_version; /*!< Version number of the board info */
+ uint16_t family_id; /*!< Use to select or identify target family from defined target family or custom ones */
+ char board_id[5]; /*!< 4-char board ID plus null terminator */
+ uint8_t _padding[3];
+ uint32_t flags; /*!< Flags from #_board_info_flags */
+ target_cfg_t *target_cfg; /*!< Specific chip configuration for the target and enables MSD when non-NULL */
+
+ //! @name MSD customization
+ //@{
+ vfs_filename_t daplink_url_name; /*!< Customize the URL file name */
+ vfs_filename_t daplink_drive_name; /*!< Customize the MSD DAPLink drive name */
+ char daplink_target_url[64]; /*!< Customize the target url in DETAILS.TXT */
+ //@}
+
+ //! @name Board initialization customization
+ //@{
+ void (*prerun_board_config)(void); /*!< Specific board debug/ID related initialization */
+ void (*swd_set_target_reset)(uint8_t asserted); /*!< Boards can customize how to send reset to the target with precedence over target family */
+ uint8_t (*target_set_state)(target_state_t state); /*!< Boards can customize target debug states with precedence over target family */
+ uint32_t soft_reset_type; /*!< Boards can override software reset type to VECTRESET or SYSRESETREQ */
+ //@}
+} board_info_t;
+
+//! @brief Information describing the board on which DAPLink is running.
+extern const board_info_t g_board_info;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//! @brief Returns the 4-char ID of the board used by the running firmware.
+//!
+//! For firmware with no board, the board ID is "0000".
+const char * get_board_id(void);
+
+//! @brief Returns the family ID for the target associated with the board.
+//!
+//! The family ID will be 0 if there is no board.
+uint16_t get_family_id(void);
+
+//! @brief Whether the board has a valid flash algo.
+uint8_t flash_algo_valid(void);
+
+//! @brief Returns the MSD HTML help filename or a default.
+static inline const char * get_daplink_url_name ( void ) { return ((g_board_info.daplink_url_name[0] != 0) ? g_board_info.daplink_url_name : "MBED HTM"); }
+
+//! @brief Returns the MSD volume name or a default.
+static inline const char * get_daplink_drive_name ( void ) { return ((g_board_info.daplink_drive_name[0] != 0) ? g_board_info.daplink_drive_name : "DAPLINK "); }
+
+//! @brief Returns the target information URL or a default.
+static inline const char * get_daplink_target_url ( void ) { return ((g_board_info.daplink_target_url[0] != 0) ? g_board_info.daplink_target_url : "https://mbed.org/device/?code=@U?version=@V?target_id=@T"); }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/target/target_config.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/target/target_config.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,72 @@
+/**
+ * @file target_config.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef TARGET_CONFIG_H
+#define TARGET_CONFIG_H
+
+#include <stddef.h>
+#include <stdint.h>
+
+#include "flash_blob.h"
+#include "util.h"
+
+//! This can vary from target to target and should be in the structure or flash blob
+#define TARGET_AUTO_INCREMENT_PAGE_SIZE (1024)
+
+//! Additional flash and ram regions
+#define MAX_REGIONS (10)
+
+//! @brief Option flags for memory regions.
+enum _region_flags {
+ kRegionIsDefault = (1 << 0), /*!< Out of bounds regions will use the same flash algo if this is set */
+ kRegionIsSecure = (1 << 1), /*!< The region can only be accessed from the secure world. Only applies for TrustZone-enabled targets. */
+};
+
+/*!
+ * @brief Details of a target flash or RAM memory region.
+ */
+typedef struct __attribute__((__packed__)) region_info {
+ uint32_t start; /*!< Region start address. */
+ uint32_t end; /*!< Region end address. */
+ uint32_t flags; /*!< Flags for this region from the #_region_flags enumeration. */
+ uint32_t alias_index; /*!< Use with flags; will point to a different index if there is an alias region */
+ program_target_t *flash_algo; /*!< A pointer to the flash algorithm structure */
+} region_info_t;
+
+/*!
+ * @brief Information required to program target flash.
+ */
+typedef struct __attribute__((__packed__)) target_cfg {
+ uint32_t version; /*!< Target configuration version */
+ const sector_info_t* sectors_info; /*!< Sector start and length list */
+ uint32_t sector_info_length; /*!< Number of entries in the sectors_info array */
+ region_info_t flash_regions[MAX_REGIONS]; /*!< Flash regions */
+ region_info_t ram_regions[MAX_REGIONS]; /*!< RAM regions */
+ const char *rt_board_id; /*!< If assigned, this is a flexible board ID */
+ uint16_t rt_family_id; /*!< If assigned, this is a flexible family ID */
+ uint8_t erase_reset; /*!< Reset after performing an erase */
+ uint8_t pad;
+} target_cfg_t;
+
+extern target_cfg_t target_device;
+
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/target/target_family.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/target/target_family.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,161 @@
+/**
+ * @file target_family.c
+ * @brief Implementation of target_family.h
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "daplink.h"
+#include "DAP_config.h"
+#include "swd_host.h"
+#include "target_family.h"
+#include "target_board.h"
+
+// Stub families
+const target_family_descriptor_t g_hw_reset_family = {
+ .family_id = kStub_HWReset_FamilyID,
+ .default_reset_type = kHardwareReset,
+};
+
+const target_family_descriptor_t g_sw_vectreset_family = {
+ .family_id = kStub_SWVectReset_FamilyID,
+ .default_reset_type = kSoftwareReset,
+ .soft_reset_type = VECTRESET,
+};
+
+const target_family_descriptor_t g_sw_sysresetreq_family = {
+ .family_id = kStub_SWSysReset_FamilyID,
+ .default_reset_type = kSoftwareReset,
+ .soft_reset_type = SYSRESETREQ,
+};
+
+//Weakly define family
+__attribute__((weak))
+const target_family_descriptor_t g_nxp_kinetis_kseries = {0};
+__attribute__((weak))
+const target_family_descriptor_t g_nxp_kinetis_lseries = {0};
+__attribute__((weak))
+const target_family_descriptor_t g_nxp_kinetis_k32w_series = {0};
+__attribute__((weak))
+const target_family_descriptor_t g_nxp_mimxrt = {0};
+__attribute__((weak))
+const target_family_descriptor_t g_nxp_rapid_iot = {0};
+__attribute__((weak))
+const target_family_descriptor_t g_nordic_nrf51 = {0};
+__attribute__((weak))
+const target_family_descriptor_t g_nordic_nrf52 = {0};
+__attribute__((weak))
+const target_family_descriptor_t g_realtek_rtl8195am = {0};
+__attribute__((weak))
+const target_family_descriptor_t g_ti_family = {0};
+__attribute__((weak))
+const target_family_descriptor_t g_wiznet_family = {0};
+__attribute__((weak))
+const target_family_descriptor_t g_renesas_family = {0};
+__attribute__((weak))
+const target_family_descriptor_t g_toshiba_tz_family = {0};
+
+__attribute__((weak))
+const target_family_descriptor_t *g_families[] = {
+ &g_hw_reset_family,
+ &g_sw_vectreset_family,
+ &g_sw_sysresetreq_family,
+ &g_nxp_kinetis_kseries,
+ &g_nxp_kinetis_lseries,
+ &g_nxp_kinetis_k32w_series,
+ &g_nxp_mimxrt,
+ &g_nxp_rapid_iot,
+ &g_nordic_nrf51,
+ &g_nordic_nrf52,
+ &g_realtek_rtl8195am,
+ &g_ti_family,
+ &g_wiznet_family,
+ &g_renesas_family,
+ &g_toshiba_tz_family,
+ 0 // list terminator
+};
+
+__attribute__((weak))
+const target_family_descriptor_t *g_target_family = NULL;
+
+
+void init_family(void)
+{
+ uint8_t index = 0;
+ uint16_t family_id = get_family_id();
+ if (g_target_family != NULL){ //already set
+ return;
+ }
+
+ while (g_families[index]!=0) {
+ if (g_families[index]->family_id && (g_families[index]->family_id == family_id)) {
+ g_target_family = g_families[index];
+ break;
+ }
+ index++;
+ }
+
+ if(g_target_family == NULL){ //default family
+ g_target_family = &g_hw_reset_family;
+ }
+}
+
+uint8_t target_set_state(target_state_t state)
+{
+ if (g_board_info.target_set_state) { //target specific
+ g_board_info.target_set_state(state);
+ }
+ if (g_target_family) {
+ if (g_target_family->target_set_state) {
+ //customize target state
+ return g_target_family->target_set_state(state);
+ } else {
+ if (g_target_family->default_reset_type == kHardwareReset) {
+ return swd_set_target_state_hw(state);
+ } else if (g_target_family->default_reset_type == kSoftwareReset) {
+ if (g_board_info.soft_reset_type) { //board has precedence
+ swd_set_soft_reset(g_board_info.soft_reset_type);
+ } else if (g_target_family->soft_reset_type) {
+ swd_set_soft_reset(g_target_family->soft_reset_type);
+ }
+ return swd_set_target_state_sw(state);
+ }else {
+ return 1;
+ }
+ }
+ }else{
+ return 0;
+ }
+}
+
+void swd_set_target_reset(uint8_t asserted)
+{
+ if (g_target_family && g_target_family->swd_set_target_reset) {
+ g_target_family->swd_set_target_reset(asserted);
+ }else {
+ (asserted) ? PIN_nRESET_OUT(0) : PIN_nRESET_OUT(1);
+ }
+}
+
+uint32_t target_get_apsel()
+{
+ if (g_target_family && g_target_family->apsel) {
+ return g_target_family->apsel;
+ } else {
+ return 0;
+ }
+}
diff -r 000000000000 -r 01f31e923fe2 source/target/target_family.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/target/target_family.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,151 @@
+/**
+ * @file target_family.h
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2018-2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef TARGET_FAMILY_H
+#define TARGET_FAMILY_H
+
+#include <stdint.h>
+#include <string.h>
+
+//! @brief Creates a family ID from a vendor ID and family index within that vendor.
+#define VENDOR_TO_FAMILY(vendor, family) ((vendor) << 8 | (family))
+
+//! @brief States into which the target can be placed.
+//!
+//! These enums are passed to target_set_state() and indicate the desired state into which
+//! the target should be reset.
+typedef enum _target_state {
+ RESET_HOLD, //!< Hold target in reset
+ RESET_PROGRAM, //!< Reset target and setup for flash programming
+ RESET_RUN, //!< Reset target and run normally
+ NO_DEBUG, //!< Disable debug on running target
+ DEBUG, //!< Enable debug on running target
+ HALT, //!< Halt the target without resetting it
+ RUN, //!< Resume the target without resetting it
+ POST_FLASH_RESET, //!< Reset target after flash programming
+ POWER_ON, //!< Poweron the target
+ SHUTDOWN, //!< Poweroff the target
+} target_state_t;
+
+//! @brief Options for reset.
+typedef enum _reset_type {
+ kHardwareReset = 1,
+ kSoftwareReset,
+} reset_type_t;
+
+//! @brief Unique IDs for vendors.
+//!
+//! The vendor IDs are the same as those used for the _DeviceVendorEnum_ defined for the PDSC file
+//! format from CMSIS-Packs. See the [DeviceVendorEnum
+//! documentation](https://arm-software.github.io/CMSIS_5/Pack/html/pdsc_family_pg.html#DeviceVendorEnum)
+//! for the list of ID values.
+enum _vendor_ids {
+ kStub_VendorID = 0,
+ kNXP_VendorID = 11,
+ kTI_VendorID = 16,
+ kNordic_VendorID = 54,
+ kToshiba_VendorID = 92,
+ kRenesas_VendorID = 117,
+ kWiznet_VendorID = 122,
+ kRealtek_VendorID = 124,
+};
+
+//! @brief Unique IDs for device families supported by DAPLink.
+//!
+//! The values of these enums are created with the VENDOR_TO_FAMILY() macro. Vendor IDs come from
+//! the #_vendor_ids enumeration. The family index for each ID is simply an integer that is unique
+//! within the family.
+//!
+//! There are several "stub" families defined with a stub vendor. These families are meant to be
+//! used for devices that do not require any customized behaviour in order to be successfully
+//! controlled by DAPLink. The individual stub families provide some options for what reset type
+//! should be used, either hardware or software.
+//!
+//! To add a new family, first determine if you can simply use one of the stub families. For many
+//! devices, the stub families are sufficient and using them reduces complexity.
+//!
+//! If you do need a new family ID, first check if the vendor is present in #_vendor_ids. If not,
+//! add the vendor ID to that enum (see its documentation for the source of vendor ID values).
+//! Then pick a unique family index by adding 1 to the highest existing family index within that
+//! vendor. For a family with a new vendor, the family index should be 1.
+typedef enum _family_id {
+ kStub_HWReset_FamilyID = VENDOR_TO_FAMILY(kStub_VendorID, 1),
+ kStub_SWVectReset_FamilyID = VENDOR_TO_FAMILY(kStub_VendorID, 2),
+ kStub_SWSysReset_FamilyID = VENDOR_TO_FAMILY(kStub_VendorID, 3),
+ kNXP_KinetisK_FamilyID = VENDOR_TO_FAMILY(kNXP_VendorID, 1),
+ kNXP_KinetisL_FamilyID = VENDOR_TO_FAMILY(kNXP_VendorID, 2),
+ kNXP_Mimxrt_FamilyID = VENDOR_TO_FAMILY(kNXP_VendorID, 3),
+ kNXP_RapidIot_FamilyID = VENDOR_TO_FAMILY(kNXP_VendorID, 4),
+ kNXP_KinetisK32W_FamilyID = VENDOR_TO_FAMILY(kNXP_VendorID, 5),
+ kNordic_Nrf51_FamilyID = VENDOR_TO_FAMILY(kNordic_VendorID, 1),
+ kNordic_Nrf52_FamilyID = VENDOR_TO_FAMILY(kNordic_VendorID, 2),
+ kRealtek_Rtl8195am_FamilyID = VENDOR_TO_FAMILY(kRealtek_VendorID, 1),
+ kTI_Cc3220sf_FamilyID = VENDOR_TO_FAMILY(kTI_VendorID, 1),
+ kToshiba_Tz_FamilyID = VENDOR_TO_FAMILY(kToshiba_VendorID, 1),
+ kWiznet_W7500_FamilyID = VENDOR_TO_FAMILY(kWiznet_VendorID, 1),
+ kRenesas_FamilyID = VENDOR_TO_FAMILY(kRenesas_VendorID, 1),
+} family_id_t;
+
+//! @brief Defines all characteristics of a device family.
+typedef struct target_family_descriptor {
+ uint16_t family_id; /*!< Use to select or identify target family from defined target family or custom ones */
+ reset_type_t default_reset_type; /*!< Target family can select predefined reset from kHardwareReset and kSoftwareReset */
+ uint32_t soft_reset_type; /*!< Families can override software reset type to VECTRESET or SYSRESETREQ */
+ void (*target_before_init_debug)(void); /*!< Target dependant function before debug initialization */
+ void (*prerun_target_config)(void); /*!< Target specific initialization */
+ uint8_t (*target_unlock_sequence)(void); /*!< Unlock targets that can enter lock state */
+ uint8_t (*security_bits_set)(uint32_t addr, uint8_t *data, uint32_t size); /*!< Check security bits in the programmable flash region */
+ uint8_t (*target_set_state)(target_state_t state); /*!< Families can customize target debug states */
+ void (*swd_set_target_reset)(uint8_t asserted); /*!< Families can customize how to send reset to the target */
+ uint8_t (*validate_bin_nvic)(const uint8_t *buf); /*!< Validate a bin file to be flash by drag and drop */
+ uint8_t (*validate_hexfile)(const uint8_t *buf); /*!< Validate a hex file to be flash by drag and drop */
+ uint32_t apsel; /*!< APSEL for the family */
+} target_family_descriptor_t;
+
+//! @brief The active family used by the board.
+//!
+//! This global is initialized by init_family() just after DAPLink boots. Normally it matches
+//! the family specified by the #board_info_t::family_id field of #g_board_info.
+extern const target_family_descriptor_t *g_target_family;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//! @brief Initialize g_target_family.
+void init_family(void);
+
+//! @brief Reset the target into a new state.
+//!
+//! Used to prepare the target for some operation, or release it for user control.
+uint8_t target_set_state(target_state_t state);
+
+//! @brief Controls reset of the target.
+void swd_set_target_reset(uint8_t asserted);
+
+//! @brief Get the APSEL for the AHB-AP to use for controlling the target.
+uint32_t target_get_apsel(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/usb/bulk/usbd_bulk.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/usb/bulk/usbd_bulk.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,109 @@
+/**
+ * @file usbd_bulk.c
+ * @brief DAPv2 BULK driver
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2019, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+
+#include "rl_usb.h"
+#include "usb_for_lib.h"
+#include "util.h"
+#include "DAP_queue.h"
+
+static U8 *ptrDataIn;
+static U16 DataInReceLen;
+static DAP_queue DAP_Cmd_queue;
+
+static volatile uint8_t USB_ResponseIdle;
+
+void usbd_bulk_init(void)
+{
+ ptrDataIn = USBD_Bulk_BulkOutBuf;
+ DataInReceLen = 0;
+ DAP_queue_init(&DAP_Cmd_queue);
+ USB_ResponseIdle = 1;
+}
+
+/*
+ * USB Device Bulk In Endpoint Event Callback
+ * Parameters: event: not used (just for compatibility)
+ * Return Value: None
+ */
+
+void USBD_BULK_EP_BULKIN_Event(U32 event)
+{
+ uint8_t * sbuf = 0;
+ int slen;
+ if(DAP_queue_get_send_buf(&DAP_Cmd_queue, &sbuf, &slen)){
+ USBD_WriteEP(usbd_bulk_ep_bulkin | 0x80, sbuf, slen);
+ } else {
+ USB_ResponseIdle = 1;
+ }
+}
+
+
+/*
+ * USB Device Bulk Out Endpoint Event Callback
+ * Parameters: event: not used (just for compatibility)
+ * Return Value: None
+ */
+
+void USBD_BULK_EP_BULKOUT_Event(U32 event)
+{
+ U16 bytes_rece;
+ uint8_t * rbuf;
+
+ bytes_rece = USBD_ReadEP(usbd_bulk_ep_bulkout, ptrDataIn, USBD_Bulk_BulkBufSize - DataInReceLen);
+ ptrDataIn += bytes_rece;
+ DataInReceLen += bytes_rece;
+
+ if ((DataInReceLen >= USBD_Bulk_BulkBufSize) ||
+ (bytes_rece < usbd_bulk_maxpacketsize[USBD_HighSpeed])) {
+ if (DAP_queue_execute_buf(&DAP_Cmd_queue, USBD_Bulk_BulkOutBuf, DataInReceLen, &rbuf)) {
+ //Trigger the BULKIn for the reply
+ if (USB_ResponseIdle) {
+ USBD_BULK_EP_BULKIN_Event(0);
+ USB_ResponseIdle = 0;
+ }
+ }
+ //revert the input pointers
+ DataInReceLen = 0;
+ ptrDataIn = USBD_Bulk_BulkOutBuf;
+ }
+}
+
+
+/*
+ * USB Device Bulk In/Out Endpoint Event Callback
+ * Parameters: event: USB Device Event
+ * USBD_EVT_OUT: Output Event
+ * USBD_EVT_IN: Input Event
+ * Return Value: None
+ */
+
+void USBD_BULK_EP_BULK_Event(U32 event)
+{
+ if (event & USBD_EVT_OUT) {
+ USBD_BULK_EP_BULKOUT_Event(0);
+ }
+
+ if (event & USBD_EVT_IN) {
+ USBD_BULK_EP_BULKIN_Event(0);
+ }
+}
diff -r 000000000000 -r 01f31e923fe2 source/usb/cdc/usbd_cdc_acm.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/usb/cdc/usbd_cdc_acm.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,823 @@
+/**
+ * @file usbd_cdc_acm.c
+ * @brief Communication Device Class driver
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+
+#include "rl_usb.h"
+#include "usb_for_lib.h"
+
+
+/* Module global variables */
+
+/** \ingroup USBD_CDC_ACM_global_variables
+ \defgroup USBD_CDC_ACM_GLOBAL_VAR Global Variables (GLOBAL_VAR)
+ \brief Global variables used in USBD CDC ACM module
+ */
+int32_t data_send_access; /*!< Flag active while send data (in the send intermediate buffer) is being accessed */
+int32_t data_send_active; /*!< Flag active while data is being sent */
+int32_t data_send_zlp; /*!< Flag active when ZLP needs to be sent */
+int32_t data_to_send_wr; /*!< Number of bytes written to the send intermediate buffer */
+int32_t data_to_send_rd; /*!< Number of bytes read from the send intermediate buffer */
+uint8_t *ptr_data_to_send; /*!< Pointer to the send intermediate buffer to the data to be sent */
+uint8_t *ptr_data_sent; /*!< Pointer to the send intermediate buffer to the data already sent */
+
+int32_t data_read_access; /*!< Flag active while read data (in the receive intermediate buffer) is being accessed */
+int32_t data_receive_int_access; /*!< Flag active while read data (in the receive intermediate buffer) is being accessed from the IRQ function*/
+int32_t data_received_pending_pckts; /*!< Number of packets received but not handled (pending) */
+int32_t data_no_space_for_receive; /*!< Flag active while there is no more space for reception */
+uint8_t *ptr_data_received; /*!< Pointer to the receive intermediate buffer to the received unread data */
+uint8_t *ptr_data_read; /*!< Pointer to the receive intermediate buffer to the received read data */
+
+uint16_t control_line_state; /*!< Control line state settings bitmap (0. bit - DTR state, 1. bit - RTS state) */
+
+CDC_LINE_CODING line_coding; /*!< Communication settings */
+
+/* end of group USBD_CDC_ACM_GLOBAL_VAR */
+
+
+/* Functions that should be provided by user to use standard Virtual COM port
+ functionality */
+__weak int32_t USBD_CDC_ACM_PortInitialize(void)
+{
+ return (0);
+}
+__weak int32_t USBD_CDC_ACM_PortUninitialize(void)
+{
+ return (0);
+}
+__weak int32_t USBD_CDC_ACM_PortReset(void)
+{
+ return (0);
+}
+__weak int32_t USBD_CDC_ACM_PortSetLineCoding(CDC_LINE_CODING *line_coding)
+{
+ return (0);
+}
+__weak int32_t USBD_CDC_ACM_PortGetLineCoding(CDC_LINE_CODING *line_coding)
+{
+ return (0);
+}
+__weak int32_t USBD_CDC_ACM_PortSetControlLineState(uint16_t ctrl_bmp)
+{
+ return (0);
+}
+
+/* Functions that can be used by user to use standard Virtual COM port
+ functionality */
+int32_t USBD_CDC_ACM_DataSend(const uint8_t *buf, int32_t len);
+int32_t USBD_CDC_ACM_PutChar(const uint8_t ch);
+int32_t USBD_CDC_ACM_DataRead(uint8_t *buf, int32_t len);
+int32_t USBD_CDC_ACM_GetChar(void);
+__weak int32_t USBD_CDC_ACM_DataReceived(int32_t len)
+{
+ return (0);
+}
+int32_t USBD_CDC_ACM_DataAvailable(void);
+int32_t USBD_CDC_ACM_Notify(uint16_t stat);
+
+/* Functions handling CDC ACM requests (can be overridden to provide custom
+ handling of CDC ACM requests) */
+__weak int32_t USBD_CDC_ACM_SendEncapsulatedCommand(void)
+{
+ return (0);
+}
+__weak int32_t USBD_CDC_ACM_GetEncapsulatedResponse(void)
+{
+ return (0);
+}
+__weak int32_t USBD_CDC_ACM_SetCommFeature(uint16_t feat)
+{
+ return (0);
+}
+__weak int32_t USBD_CDC_ACM_GetCommFeature(uint16_t feat)
+{
+ return (0);
+}
+__weak int32_t USBD_CDC_ACM_ClearCommFeature(uint16_t feat)
+{
+ return (0);
+}
+__weak int32_t USBD_CDC_ACM_SendBreak(uint16_t dur)
+{
+ return (0);
+}
+
+
+/* Local function prototypes */
+static void USBD_CDC_ACM_EP_BULKOUT_HandleData(void);
+static void USBD_CDC_ACM_EP_BULKIN_HandleData(void);
+
+
+/*----------------- USB CDC ACM class handling functions ---------------------*/
+
+/** \brief Initialization of the USB CDC class (ACM)
+
+ The function calls USBD_CDC_ACM_PortInitialize function which
+ initializes Virtual COM Port.
+
+ \return 0 Function failed.
+ \return 1 Function succeeded.
+ */
+
+__weak int32_t USBD_CDC_ACM_Initialize(void)
+{
+ data_send_access = 0;
+ data_send_active = 0;
+ data_send_zlp = 0;
+ data_to_send_wr = 0;
+ data_to_send_rd = 0;
+ ptr_data_to_send = USBD_CDC_ACM_SendBuf;
+ ptr_data_sent = USBD_CDC_ACM_SendBuf;
+ data_read_access = 0;
+ data_receive_int_access = 0;
+ data_received_pending_pckts = 0;
+ data_no_space_for_receive = 0;
+ ptr_data_received = USBD_CDC_ACM_ReceiveBuf;
+ ptr_data_read = USBD_CDC_ACM_ReceiveBuf;
+ control_line_state = 0;
+ line_coding.dwDTERate = 9600;
+ line_coding.bCharFormat = 0;
+ line_coding.bParityType = 0;
+ line_coding.bDataBits = 8;
+ return (USBD_CDC_ACM_PortInitialize());
+}
+
+
+/** \brief Uninitialization of the USB CDC class (ACM)
+
+ The function calls USBD_CDC_ACM_PortUninitialize function which
+ uninitializes Virtual COM Port.
+
+ \return 0 Function failed.
+ \return 1 Function succeeded.
+ */
+
+__weak int32_t USBD_CDC_ACM_Uninitialization(void)
+{
+ return (USBD_CDC_ACM_PortUninitialize());
+}
+
+
+/** \brief Reset of the USB CDC class (ACM) variables and states
+
+ The function resets class variables and states, it calls
+ USBD_CDC_ACM_PortReset function which resets Virtual COM Port variables
+ and states and calls USBD_CDC_ACM_PortSetLineCoding function with
+ default parameters to set default communication settings for the
+ Virtual COM Port.
+
+ \return 0 Function failed.
+ \return 1 Function succeeded.
+ */
+
+__weak int32_t USBD_CDC_ACM_Reset(void)
+{
+ data_send_access = 0;
+ data_send_active = 0;
+ data_send_zlp = 0;
+ data_to_send_wr = 0;
+ data_to_send_rd = 0;
+ ptr_data_to_send = USBD_CDC_ACM_SendBuf;
+ ptr_data_sent = USBD_CDC_ACM_SendBuf;
+ data_read_access = 0;
+ data_receive_int_access = 0;
+ data_received_pending_pckts = 0;
+ data_no_space_for_receive = 0;
+ ptr_data_received = USBD_CDC_ACM_ReceiveBuf;
+ ptr_data_read = USBD_CDC_ACM_ReceiveBuf;
+ control_line_state = 0;
+ USBD_CDC_ACM_PortReset();
+ line_coding.dwDTERate = 9600;
+ line_coding.bCharFormat = 0;
+ line_coding.bParityType = 0;
+ line_coding.bDataBits = 8;
+ return (USBD_CDC_ACM_PortSetLineCoding(&line_coding));
+}
+
+
+/** \brief Sets Line Coding for the USB CDC ACM Virtual COM Port
+
+ The function is a callback function that forwards USB CDC ACM request
+ to set communication settings to the Virtual COM Port.
+
+ \return 0 Function failed.
+ \return 1 Function succeeded.
+ */
+
+__weak int32_t USBD_CDC_ACM_SetLineCoding(void)
+{
+ line_coding.dwDTERate = (USBD_EP0Buf[0] << 0) |
+ (USBD_EP0Buf[1] << 8) |
+ (USBD_EP0Buf[2] << 16) |
+ (USBD_EP0Buf[3] << 24) ;
+ line_coding.bCharFormat = USBD_EP0Buf[4];
+ line_coding.bParityType = USBD_EP0Buf[5];
+ line_coding.bDataBits = USBD_EP0Buf[6];
+ return (USBD_CDC_ACM_PortSetLineCoding(&line_coding));
+}
+
+
+/** \brief Gets Line Coding from the USB CDC ACM Virtual COM Port
+
+ The function is a callback function that forwards USB CDC ACM request
+ to get communication settings from the Virtual COM Port.
+
+ \return 0 Function failed.
+ \return 1 Function succeeded.
+ */
+
+__weak int32_t USBD_CDC_ACM_GetLineCoding(void)
+{
+ if (USBD_CDC_ACM_PortGetLineCoding(&line_coding)) {
+ USBD_EP0Buf[0] = (line_coding.dwDTERate >> 0) & 0xFF;
+ USBD_EP0Buf[1] = (line_coding.dwDTERate >> 8) & 0xFF;
+ USBD_EP0Buf[2] = (line_coding.dwDTERate >> 16) & 0xFF;
+ USBD_EP0Buf[3] = (line_coding.dwDTERate >> 24) & 0xFF;
+ USBD_EP0Buf[4] = line_coding.bCharFormat;
+ USBD_EP0Buf[5] = line_coding.bParityType;
+ USBD_EP0Buf[6] = line_coding.bDataBits;
+ return (1);
+ }
+
+ return (0);
+}
+
+
+/** \brief Sets Control Line State for the USB CDC ACM Virtual COM Port
+
+ The function is a callback function that forwards USB CDC ACM request
+ to set desired control line state to the Virtual COM Port.
+
+ \param [in] ctrl_bmp Control line settings bitmap (
+ 0. bit - DTR state,
+ 1. bit - RTS state).
+ \return 0 Function failed.
+ \return 1 Function succeeded.
+ */
+
+__weak int32_t USBD_CDC_ACM_SetControlLineState(uint16_t ctrl_bmp)
+{
+ control_line_state = ctrl_bmp;
+ return (USBD_CDC_ACM_PortSetControlLineState(ctrl_bmp));
+}
+
+
+/*----------------- USB CDC ACM user API functions ---------------------------*/
+
+/** \brief Number of free bytes in the Send buffer
+*/
+int32_t USBD_CDC_ACM_DataFree(void)
+{
+ return ((int32_t)usbd_cdc_acm_sendbuf_sz) - (data_to_send_wr - data_to_send_rd);
+}
+
+/** \brief Sends data over the USB CDC ACM Virtual COM Port
+
+ The function puts requested data to the send intermediate buffer and
+ prepares it for sending over the Virtual COM Port.
+
+ \param [in] buf Buffer containing data to be sent.
+ \param [in] len Maximum number of bytes to be sent.
+ \return Number of bytes accepted to be sent.
+ */
+
+int32_t USBD_CDC_ACM_DataSend(const uint8_t *buf, int32_t len)
+{
+ int32_t len_data, len_available, len_before_wrap;
+ uint8_t *buf_loc;
+ buf_loc = (uint8_t *)buf; /* Pointer to buf */
+ len_data = data_to_send_wr - data_to_send_rd; /* Num of data in buffer*/
+ len_available = ((int32_t)usbd_cdc_acm_sendbuf_sz) - len_data; /* Num of
+ bytes of space available */
+
+ if (len_available <= 0) { /* If no space for data to send */
+ return (0);
+ }
+
+ if (len > len_available) /* If more data requested for sending
+ then available space */
+ {
+ len = len_available; /* Correct to maximum available */
+ }
+
+ len_before_wrap = 0; /* Circular buffer size before wrap */
+
+ if ((ptr_data_to_send >= ptr_data_sent) && /* If wrap is possible to happen */
+ ((ptr_data_to_send + len) >= (USBD_CDC_ACM_SendBuf + usbd_cdc_acm_sendbuf_sz))) {
+ /* If data wraps around end of buffer */
+ len_before_wrap = USBD_CDC_ACM_SendBuf + usbd_cdc_acm_sendbuf_sz - ptr_data_to_send;
+ memcpy(ptr_data_to_send, buf_loc, len_before_wrap); /* Copy data till end */
+ buf_loc += len_before_wrap; /* Increment buf pointer */
+ len -= len_before_wrap; /* Decrement bytes to send*/
+ ptr_data_to_send = USBD_CDC_ACM_SendBuf; /* Wrap send buffer
+ pointer to beginning of
+ the send buffer */
+ }
+
+ if (len) { /* If there are bytes to send */
+ memcpy(ptr_data_to_send, buf_loc, len); /* Copy data to send buffer */
+ ptr_data_to_send += len; /* Correct position of write pointer */
+ }
+
+ len += len_before_wrap; /* Total number of bytes prepared for
+ send */
+ data_to_send_wr += len; /* Bytes prepared to send counter */
+ return (len); /* Number of bytes accepted for send */
+}
+
+
+/** \brief Sends a single character over the USB CDC ACM Virtual COM Port
+
+ The function puts requested data character to the send intermediate buffer
+ and prepares it for sending over the Virtual COM Port.
+
+ \param [in] ch Character to be sent.
+ \return -1 Function failed.
+ \return Character accepted to be sent.
+ */
+
+int32_t USBD_CDC_ACM_PutChar(const uint8_t ch)
+{
+ if ((USBD_CDC_ACM_DataSend(&ch, 1)) == 1) {
+ return ((uint32_t) ch);
+ }
+
+ return (-1);
+}
+
+
+/** \brief Reads data received over the USB CDC ACM Virtual COM Port
+
+ The function reads data from the receive intermediate buffer that was
+ received over the Virtual COM Port.
+
+ \param [in] buf Buffer to where data will be read.
+ \param [in] len Maximum number of bytes to be read.
+ \return Number of bytes actually read.
+ */
+
+int32_t USBD_CDC_ACM_DataRead(uint8_t *buf, int32_t len)
+{
+ int32_t len_data;
+
+ if (ptr_data_received > ptr_data_read) { /*If there is already received data */
+ len_data = ptr_data_received - ptr_data_read; /* Available bytes of data */
+
+ if (len > len_data) { /* If more requested then available */
+ len = len_data; /* correct to return maximum available*/
+ }
+
+ memcpy(buf, ptr_data_read, len); /* Copy received data to provided buf */
+ ptr_data_read += len; /* Correct position of read pointer */
+ } else {
+ len = 0; /* No data received */
+ }
+
+ return (len); /* Number of bytes actually read */
+}
+
+
+/** \brief Reads one character of data received over the USB CDC ACM Virtual COM Port
+
+ The function reads data character from the receive intermediate buffer that
+ was received over the Virtual COM Port.
+
+ \return -1 No character available.
+ \return Received character.
+ */
+
+int32_t USBD_CDC_ACM_GetChar(void)
+{
+ uint8_t ch;
+
+ if ((USBD_CDC_ACM_DataRead(&ch, 1)) == 1) {
+ return ((int32_t) ch);
+ }
+
+ return (-1);
+}
+
+
+/** \brief Retrieves number of bytes received over the USB CDC ACM Virtual COM Port
+
+ The function retrieves number of bytes available in the intermediate buffer
+ that were received over the Virtual COM Port.
+
+ \return Number of bytes available for read.
+ */
+
+int32_t USBD_CDC_ACM_DataAvailable(void)
+{
+ return (ptr_data_received - ptr_data_read);
+}
+
+
+/** \brief Sends a notification of Virtual COM Port statuses and line states
+
+ The function sends error and line status of the Virtual COM Port over the
+ Interrupt endpoint. (SerialState notification is defined in usbcdc11.pdf, 6.3.5.)
+
+ \param [in] stat Error and line statuses (
+ 6. bit - bOverRun,
+ 5. bit - bParity,
+ 4. bit - bFraming,
+ 3. bit - bRingSignal,
+ 2. bit - bBreak,
+ 1. bit - bTxCarrier (DSR line state),
+ 0. bit - bRxCarrier (DCD line status)).
+ \return 0 Function failed.
+ \return 1 Function succeeded.
+ */
+
+int32_t USBD_CDC_ACM_Notify(uint16_t stat)
+{
+ if (USBD_Configuration) {
+ USBD_CDC_ACM_NotifyBuf[0] = 0xA1; /* bmRequestType */
+ USBD_CDC_ACM_NotifyBuf[1] = CDC_NOTIFICATION_SERIAL_STATE;/* bNotification
+ (SERIAL_STATE) */
+ USBD_CDC_ACM_NotifyBuf[2] = 0x00; /* wValue */
+ USBD_CDC_ACM_NotifyBuf[3] = 0x00;
+ USBD_CDC_ACM_NotifyBuf[4] = 0x00; /* wIndex (Interface 0) */
+ USBD_CDC_ACM_NotifyBuf[5] = 0x00;
+ USBD_CDC_ACM_NotifyBuf[6] = 0x02; /* wLength */
+ USBD_CDC_ACM_NotifyBuf[7] = 0x00;
+ USBD_CDC_ACM_NotifyBuf[8] = stat >> 0; /* UART State Bitmap */
+ USBD_CDC_ACM_NotifyBuf[9] = stat >> 8;
+ /* Write notification to be sent */
+ USBD_WriteEP(usbd_cdc_acm_ep_intin | 0x80, USBD_CDC_ACM_NotifyBuf, 10);
+ return (1);
+ }
+
+ return (0);
+}
+
+
+/*----------------- USB CDC ACM communication event handlers -----------------*/
+
+/** \brief Handle Reset Events
+
+ The function handles Reset events.
+ */
+
+void USBD_CDC_ACM_Reset_Event(void)
+{
+ USBD_CDC_ACM_Reset();
+}
+
+
+/** \brief Handle SOF Events
+
+ The function handles Start Of Frame events. It checks if there is pending
+ data on the Bulk Out endpoint and handles it
+ (USBD_CDC_ACM_EP_BULKOUT_HandleData) if there is enough space in the
+ intermediate receive buffer and it calls received function callback
+ (USBD_CDC_ACM_DataReceived) it also activates data send over the Bulk In
+ endpoint if there is data to be sent (USBD_CDC_ACM_EP_BULKIN_HandleData).
+ */
+
+void USBD_CDC_ACM_SOF_Event(void)
+{
+ if (!USBD_Configuration) {
+ // Don't process events until CDC is
+ // configured and the endpoints enabled
+ return;
+ }
+ if ((!data_read_access) && /* If not read active */
+ (ptr_data_received == ptr_data_read) && /* If received and read
+ pointers point to same
+ the location */
+ (ptr_data_received != USBD_CDC_ACM_ReceiveBuf)) {
+ /* and if receive
+ pointer does not already
+ point to the start of
+ the receive buffer */
+ data_read_access = 1; /* Block access to read data */
+ ptr_data_received = USBD_CDC_ACM_ReceiveBuf; /* Correct received pointer
+ to point to the start of
+ the receive buffer */
+ ptr_data_read = USBD_CDC_ACM_ReceiveBuf; /* Correct read pointer to
+ point to the start of the
+ receive buffer */
+ data_no_space_for_receive = 0; /* There is space for
+ reception available */
+ data_read_access = 0; /* Allow access to read data */
+ }
+
+ if (data_received_pending_pckts && /* If packets are pending */
+ (!data_read_access) && /* and if not read active */
+ (!data_no_space_for_receive)) { /* and if there is space to receive */
+ data_read_access = 1; /* Disable access to read data */
+ USBD_CDC_ACM_EP_BULKOUT_HandleData(); /* Handle received data */
+ data_read_access = 0; /* Enable access to read data */
+
+ if (ptr_data_received != ptr_data_read) {
+ USBD_CDC_ACM_DataReceived(ptr_data_received - ptr_data_read);
+ } /* Call
+
+ received callback */
+ }
+
+ if ((!data_send_access) && /* If send data is not being accessed */
+ (!data_send_active) && /* and send is not active */
+ (data_to_send_wr - data_to_send_rd) /* and if there is data to be sent */
+//&& ((control_line_state & 3) == 3) /* and if DTR and RTS is 1 */
+ ) {
+ data_send_access = 1; /* Block access to send data */
+ data_send_active = 1; /* Start data sending */
+ USBD_CDC_ACM_EP_BULKIN_HandleData();/* Handle data to send */
+ data_send_access = 0; /* Allow access to send data */
+ }
+}
+
+
+/** \brief Handle Interrupt In Endpoint Events
+
+ The function handles Interrupt In endpoint events.
+
+ \param [in] event Type of event (USBD_EVT_IN - input event).
+ */
+
+void USBD_CDC_ACM_EP_INTIN_Event(uint32_t event)
+{
+ /* Notification will be loadad aynchronously and sent automatically upon
+ Interrupt IN token reception */
+}
+
+
+/** \brief Handle Bulk Out Endpoint Received Data
+
+ The function handles data received on the Bulk Out endpoint. It reads the
+ received data to the receive intermediate buffer if there is enough space
+ available.
+ */
+
+static void USBD_CDC_ACM_EP_BULKOUT_HandleData()
+{
+ uint32_t len_free_to_recv;
+ int32_t len_received;
+
+ if ((usbd_cdc_acm_receivebuf_sz - (ptr_data_received - USBD_CDC_ACM_ReceiveBuf)) >= usbd_cdc_acm_maxpacketsize1[USBD_HighSpeed]) {
+ /* If there is space for 1 max packet */
+ /* Read received packet to receive buf*/
+ len_free_to_recv = usbd_cdc_acm_receivebuf_sz - (ptr_data_received - USBD_CDC_ACM_ReceiveBuf);
+ len_received = USBD_ReadEP(usbd_cdc_acm_ep_bulkout, ptr_data_received, len_free_to_recv);
+ ptr_data_received += len_received; /* Correct pointer to received data */
+
+ if (data_received_pending_pckts && /* If packet was pending */
+ !data_receive_int_access) { /* and not interrupt access */
+ data_received_pending_pckts--; /* Decrement pending packets number */
+ }
+ } else {
+ data_no_space_for_receive = 1; /* There is no space in receive buffer
+ for the newly received data */
+
+ if (data_receive_int_access) {
+ /* If this access is from interrupt
+ function */
+ data_received_pending_pckts++; /* then this is new unhandled packet */
+ }
+ }
+}
+
+
+/** \brief Handle Bulk In Endpoint Data to Send
+
+ The function handles data to be sent on the Bulk In endpoint. It transmits
+ pending data to be sent that is already in the send intermediate buffer,
+ and it also sends Zero Length Packet if last packet sent was not a short
+ packet.
+ */
+
+static void USBD_CDC_ACM_EP_BULKIN_HandleData(void)
+{
+ int32_t len_to_send, len_sent;
+
+ if (!data_send_active) { /* If sending is not active */
+ return;
+ }
+
+ len_to_send = data_to_send_wr - data_to_send_rd; /* Num of data to send */
+
+ /* Check if sending is finished */
+ if (!len_to_send && /* If all data was sent */
+ !data_send_zlp) { /* and ZLP was sent if necessary also */
+ data_send_active = 0; /* Sending not active any more */
+ return;
+ }
+
+ /* Check if data needs to be sent */
+ if (len_to_send) {
+ /* If there is data available do be
+ sent */
+ if ((ptr_data_sent >= ptr_data_to_send) && /* If data before end of buf avail*/
+ ((ptr_data_sent + len_to_send) >= (USBD_CDC_ACM_SendBuf + usbd_cdc_acm_sendbuf_sz))) {
+ /* and if available data wraps around
+ the end of the send buffer */
+ /* Correct bytes to send to data
+ available untill end of send buf */
+ len_to_send = USBD_CDC_ACM_SendBuf + usbd_cdc_acm_sendbuf_sz - ptr_data_sent;
+ }
+
+ if (len_to_send > usbd_cdc_acm_maxpacketsize1[USBD_HighSpeed]) {
+ /* If
+ there is more data to be sent then
+ can be sent in a single packet */
+ /* Correct to send maximum pckt size */
+ len_to_send = usbd_cdc_acm_maxpacketsize1[USBD_HighSpeed];
+ }
+ } else if (data_send_zlp) { /* or if ZLP should be sent */
+ len_to_send = 0;
+ }
+
+ data_send_zlp = 0;
+ /* Send data */
+ len_sent = USBD_WriteEP(usbd_cdc_acm_ep_bulkin | 0x80, ptr_data_sent, len_to_send);
+ ptr_data_sent += len_sent; /* Correct position of sent pointer */
+ data_to_send_rd += len_sent; /* Correct num of bytes left to send */
+
+ if (ptr_data_sent == USBD_CDC_ACM_SendBuf + usbd_cdc_acm_sendbuf_sz)
+ /* If pointer to sent data wraps */
+ {
+ ptr_data_sent = USBD_CDC_ACM_SendBuf;
+ } /* Correct it to beginning of send
+
+ buffer */
+
+ if ((data_to_send_wr == data_to_send_rd) && /* If there are no more
+ bytes available to be sent */
+ (len_sent == usbd_cdc_acm_maxpacketsize1[USBD_HighSpeed])) {
+ /* If last packet size was same as
+ maximum packet size */
+ data_send_zlp = 1; /* ZLP packet should be sent */
+ } else {
+ data_send_zlp = 0; /* No ZLP packet should be sent */
+ }
+}
+
+
+/** \brief Handle Bulk Out Endpoint Events
+
+ The function handles Bulk Out endpoint events. It calls
+ USBD_CDC_ACM_EP_BULKOUT_HandleData function to handle received data
+ unless data was being accessed in which case function just acknowledges
+ that there is data to be handled later.
+
+ \param [in] event Type of event (USBD_EVT_OUT - output event).
+ */
+
+void USBD_CDC_ACM_EP_BULKOUT_Event(uint32_t event)
+{
+ if (data_read_access) {
+ /* If data is being accessed from
+ read function */
+ data_received_pending_pckts++; /* 1 more packet received and not
+ handled */
+ return;
+ }
+
+ data_read_access = 1; /* Block access to read data */
+ data_receive_int_access = 1; /* Read access from interrupt function*/
+ USBD_CDC_ACM_EP_BULKOUT_HandleData(); /* Handle received data */
+ data_receive_int_access = 0; /* Read access from interrupt func end*/
+ data_read_access = 0; /* Allow access to read data */
+
+ if (ptr_data_received != ptr_data_read) {
+ USBD_CDC_ACM_DataReceived(ptr_data_received - ptr_data_read);
+ } /* Call
+
+ received callback */
+}
+
+
+/** \brief Handle Bulk In Endpoint Events
+
+ The function handles Bulk In endpoint events. It calls
+ USBD_CDC_ACM_EP_BULKIN_HandleData function to handle send data
+ unless data was being accessed in which case function just returns.
+
+ \param [in] event Type of event (USBD_EVT_IN - input event).
+ */
+
+void USBD_CDC_ACM_EP_BULKIN_Event(uint32_t event)
+{
+ if (data_send_access /* If send data is being accessed */
+// ||((control_line_state & 3) != 3) /* or if DTR or RTS is 0 */
+ ) {
+ return;
+ }
+
+ data_send_access = 1; /* Block access to send data */
+ USBD_CDC_ACM_EP_BULKIN_HandleData(); /* Handle data to send */
+ data_send_access = 0; /* Allow access to send data */
+}
+
+
+/** \brief Handle Bulk In/Out Endpoint Events
+
+ The function handles Bulk In/Out endpoint events. It is used for endpoints
+ that do In and Out functionality on the same endpoint number. It dispatches
+ events to appropriate In or Out event handlers.
+
+ \param [in] event Type of event (
+ USBD_EVT_IN - input event,
+ USBD_EVT_OUT - output event).
+ */
+
+void USBD_CDC_ACM_EP_BULK_Event(uint32_t event)
+{
+ if (event & USBD_EVT_OUT) {
+ USBD_CDC_ACM_EP_BULKOUT_Event(event);
+ }
+
+ if (event & USBD_EVT_IN) {
+ USBD_CDC_ACM_EP_BULKIN_Event(event);
+ }
+}
+
+
+#ifdef __RTX /* RTX tasks for handling events */
+
+/** \brief Task Handling Interrupt In Endpoint Events
+
+ The task dispatches Interrupt In events to the Interrupt In handling
+ function (USBD_CDC_ACM_EP_INTIN_Event).
+ */
+
+void USBD_RTX_CDC_ACM_EP_INTIN_Event(void)
+{
+ for (;;) {
+ usbd_os_evt_wait_or(0xFFFF, 0xFFFF);
+ USBD_CDC_ACM_EP_INTIN_Event(usbd_os_evt_get());
+ }
+}
+
+
+/** \brief Task Handling Bulk In Endpoint Events
+
+ The task dispatches Bulk In events to the Bulk In handling
+ function (USBD_CDC_ACM_EP_BULKIN_Event).
+ */
+
+void USBD_RTX_CDC_ACM_EP_BULKIN_Event(void)
+{
+ for (;;) {
+ usbd_os_evt_wait_or(0xFFFF, 0xFFFF);
+
+ if (usbd_os_evt_get() & USBD_EVT_IN) {
+ USBD_CDC_ACM_EP_BULKIN_Event(0);
+ }
+ }
+}
+
+
+/** \brief Task Handling Bulk Out Endpoint Events
+
+ The task dispatches Bulk Out events to the Bulk Out handling
+ function (USBD_CDC_ACM_EP_BULKOUT_Event).
+ */
+
+void USBD_RTX_CDC_ACM_EP_BULKOUT_Event(void)
+{
+ for (;;) {
+ usbd_os_evt_wait_or(0xFFFF, 0xFFFF);
+
+ if (usbd_os_evt_get() & USBD_EVT_OUT) {
+ USBD_CDC_ACM_EP_BULKOUT_Event(0);
+ }
+ }
+}
+
+
+/** \brief Task Handling Bulk In/Out Endpoint Events
+
+ The task dispatches Bulk In/Out events to the Bulk In/Out handling
+ function (USBD_CDC_ACM_EP_BULK_Event).
+ */
+
+void USBD_RTX_CDC_ACM_EP_BULK_Event(void)
+{
+ for (;;) {
+ usbd_os_evt_wait_or(0xFFFF, 0xFFFF);
+ USBD_CDC_ACM_EP_BULK_Event(usbd_os_evt_get());
+ }
+}
+#endif
+
diff -r 000000000000 -r 01f31e923fe2 source/usb/cdc/usbd_core_cdc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/usb/cdc/usbd_core_cdc.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,146 @@
+/**
+ * @file usbd_core_cdc.c
+ * @brief Communication Device Class driver
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+
+#include "rl_usb.h"
+#include "usb_for_lib.h"
+
+
+/*
+ * USB Device Endpoint 0 Event Callback - CDC specific handling (Setup Request To Interface)
+ * Parameters: none
+ * Return Value: TRUE - Setup class request ok, FALSE - Setup class request not supported
+ */
+
+__weak BOOL USBD_EndPoint0_Setup_CDC_ReqToIF(void)
+{
+ if ((USBD_SetupPacket.wIndexL == usbd_cdc_acm_cif_num) || /* IF number correct? */
+ (USBD_SetupPacket.wIndexL == usbd_cdc_acm_dif_num)) {
+ switch (USBD_SetupPacket.bRequest) {
+ case CDC_SEND_ENCAPSULATED_COMMAND:
+ USBD_EP0Data.pData = USBD_EP0Buf; /* data to be received, see USBD_EVT_OUT */
+ return (__TRUE);
+
+ case CDC_GET_ENCAPSULATED_RESPONSE:
+ if (USBD_CDC_ACM_GetEncapsulatedResponse()) {
+ USBD_EP0Data.pData = USBD_EP0Buf; /* point to data to be sent */
+ USBD_DataInStage(); /* send requested data */
+ return (__TRUE);
+ }
+
+ break;
+
+ case CDC_SET_COMM_FEATURE:
+ USBD_EP0Data.pData = USBD_EP0Buf; /* data to be received, see USBD_EVT_OUT */
+ return (__TRUE);
+
+ case CDC_GET_COMM_FEATURE:
+ if (USBD_CDC_ACM_GetCommFeature(USBD_SetupPacket.wValue)) {
+ USBD_EP0Data.pData = USBD_EP0Buf; /* point to data to be sent */
+ USBD_DataInStage(); /* send requested data */
+ return (__TRUE);
+ }
+
+ break;
+
+ case CDC_CLEAR_COMM_FEATURE:
+ if (USBD_CDC_ACM_ClearCommFeature(USBD_SetupPacket.wValue)) {
+ USBD_StatusInStage(); /* send Acknowledge */
+ return (__TRUE);
+ }
+
+ break;
+
+ case CDC_SET_LINE_CODING:
+ USBD_EP0Data.pData = USBD_EP0Buf; /* data to be received, see USBD_EVT_OUT */
+ return (__TRUE);
+
+ case CDC_GET_LINE_CODING:
+ if (USBD_CDC_ACM_GetLineCoding()) {
+ USBD_EP0Data.pData = USBD_EP0Buf; /* point to data to be sent */
+ USBD_DataInStage(); /* send requested data */
+ return (__TRUE);
+ }
+
+ break;
+
+ case CDC_SET_CONTROL_LINE_STATE:
+ if (USBD_CDC_ACM_SetControlLineState(USBD_SetupPacket.wValue)) {
+ USBD_StatusInStage(); /* send Acknowledge */
+ return (__TRUE);
+ }
+
+ break;
+
+ case CDC_SEND_BREAK:
+ if (USBD_CDC_ACM_SendBreak(USBD_SetupPacket.wValue)) {
+ USBD_StatusInStage(); /* send Acknowledge */
+ return (__TRUE);
+ }
+
+ break;
+ }
+ }
+
+ return (__FALSE);
+}
+
+
+/*
+ * USB Device Endpoint 0 Event Callback - CDC specific handling (Out Request To Interface)
+ * Parameters: none
+ * Return Value: TRUE - Out class request ok, FALSE - Out class request not supported
+ */
+
+__weak BOOL USBD_EndPoint0_Out_CDC_ReqToIF(void)
+{
+ if ((USBD_SetupPacket.wIndexL == usbd_cdc_acm_cif_num) || /* IF number correct? */
+ (USBD_SetupPacket.wIndexL == usbd_cdc_acm_dif_num)) {
+ switch (USBD_SetupPacket.bRequest) {
+ case CDC_SEND_ENCAPSULATED_COMMAND:
+ if (USBD_CDC_ACM_SendEncapsulatedCommand()) {
+ USBD_StatusInStage(); /* send Acknowledge */
+ return (__TRUE);
+ }
+
+ break;
+
+ case CDC_SET_COMM_FEATURE:
+ if (USBD_CDC_ACM_SetCommFeature(USBD_SetupPacket.wValue)) {
+ USBD_StatusInStage(); /* send Acknowledge */
+ return (__TRUE);
+ }
+
+ break;
+
+ case CDC_SET_LINE_CODING:
+ if (USBD_CDC_ACM_SetLineCoding()) {
+ USBD_StatusInStage(); /* send Acknowledge */
+ return (__TRUE);
+ }
+
+ break;
+ }
+ }
+
+ return (__FALSE);
+}
diff -r 000000000000 -r 01f31e923fe2 source/usb/hid/usbd_core_hid.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/usb/hid/usbd_core_hid.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,174 @@
+/**
+ * @file usbd_core_hid.c
+ * @brief Human Interface Device driver
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+
+#include "rl_usb.h"
+#include "usb_for_lib.h"
+
+
+/*
+ * Get Descriptor USB Device Request - HID specific handling
+ * Parameters: None
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+__weak BOOL USBD_ReqGetDescriptor_HID(U8 **pD, U32 *len)
+{
+ switch (USBD_SetupPacket.wValueH) {
+ case HID_HID_DESCRIPTOR_TYPE:
+ if (USBD_SetupPacket.wIndexL != usbd_hid_if_num &&
+ USBD_SetupPacket.wIndexL != usbd_webusb_if_num) {
+ return (__FALSE);
+ }
+
+ if ((!usbd_hs_enable) && (USBD_HighSpeed == __TRUE)) {
+ return (__FALSE); /* High speed request but high-speed not enabled */
+ }
+
+ if (USBD_HighSpeed == __FALSE) {
+ *pD = (U8 *)USBD_ConfigDescriptor;
+ } else {
+ *pD = (U8 *)USBD_ConfigDescriptor_HS;
+ }
+
+ USBD_EP0Data.pData = *pD + USBD_HID_DescriptorOffset;
+ *len = USB_HID_DESC_SIZE;
+ break;
+
+ case HID_REPORT_DESCRIPTOR_TYPE:
+ if (USBD_SetupPacket.wIndexL != usbd_hid_if_num &&
+ USBD_SetupPacket.wIndexL != usbd_webusb_if_num) {
+ return (__FALSE);
+ }
+
+ USBD_EP0Data.pData = (U8 *)USBD_HID_ReportDescriptor;
+ *len = USBD_HID_ReportDescriptorSize;
+ break;
+
+ case HID_PHYSICAL_DESCRIPTOR_TYPE:
+ return (__FALSE); /* HID Physical Descriptor is not supported */
+
+ default:
+ return (__FALSE);
+ }
+
+ return (__TRUE);
+}
+
+
+/*
+ * USB Device Endpoint 0 Event Callback - HID specific handling (Setup Request To Interface)
+ * Parameters: none
+ * Return Value: TRUE - Setup class request ok, FALSE - Setup class request not supported
+ */
+
+__weak BOOL USBD_EndPoint0_Setup_HID_ReqToIF(void)
+{
+ if (USBD_SetupPacket.wIndexL == usbd_hid_if_num ||
+ USBD_SetupPacket.wIndexL == usbd_webusb_if_num) {
+ switch (USBD_SetupPacket.bRequest) {
+ case HID_REQUEST_GET_REPORT:
+ if (USBD_HID_GetReport()) {
+ if (USBD_SetupPacket.wValueH == HID_REPORT_INPUT) {
+ USBD_EP0Data.pData = &USBD_HID_InReport[1]; /* point to data to be sent (skip ReportID) */
+ } else if (USBD_SetupPacket.wValueH == HID_REPORT_FEATURE) {
+ USBD_EP0Data.pData = &USBD_HID_FeatReport[1]; /* point to data to be sent (skip ReportID) */
+ }
+
+ USBD_DataInStage(); /* send requested data */
+ return (__TRUE);
+ }
+
+ break;
+
+ case HID_REQUEST_SET_REPORT:
+ if (USBD_SetupPacket.wValueH == HID_REPORT_OUTPUT) {
+ USBD_EP0Data.pData = &USBD_HID_OutReport[1]; /* out data to be received (skip ReportID) */
+ } else if (USBD_SetupPacket.wValueH == HID_REPORT_FEATURE) {
+ USBD_EP0Data.pData = &USBD_HID_FeatReport[1]; /* out data to be received (skip ReportID) */
+ }
+
+ return (__TRUE);
+
+ case HID_REQUEST_GET_IDLE:
+ if (USBD_HID_GetIdle()) {
+ USBD_EP0Data.pData = USBD_EP0Buf; /* point to data to be sent */
+ USBD_DataInStage(); /* send requested data */
+ return (__TRUE);
+ }
+
+ break;
+
+ case HID_REQUEST_SET_IDLE:
+ if (USBD_HID_SetIdle()) {
+ USBD_StatusInStage(); /* send Acknowledge */
+ return (__TRUE);
+ }
+
+ break;
+
+ case HID_REQUEST_GET_PROTOCOL:
+ if (USBD_HID_GetProtocol()) {
+ USBD_EP0Data.pData = USBD_EP0Buf; /* point to data to be sent */
+ USBD_DataInStage(); /* send requested data */
+ return (__TRUE);
+ }
+
+ break;
+
+ case HID_REQUEST_SET_PROTOCOL:
+ if (USBD_HID_SetProtocol()) {
+ USBD_StatusInStage(); /* send Acknowledge */
+ return (__TRUE);
+ }
+
+ break;
+ }
+ }
+
+ return (__FALSE);
+}
+
+
+/*
+ * USB Device Endpoint 0 Event Callback - HID specific handling (Out Request To Interface)
+ * Parameters: none
+ * Return Value: TRUE - Out class request ok, FALSE - Out class request not supported
+ */
+
+__weak BOOL USBD_EndPoint0_Out_HID_ReqToIF(void)
+{
+ if (USBD_SetupPacket.wIndexL == usbd_hid_if_num ||
+ USBD_SetupPacket.wIndexL == usbd_webusb_if_num) {
+ switch (USBD_SetupPacket.bRequest) {
+ case HID_REQUEST_SET_REPORT:
+ if (USBD_HID_SetReport()) {
+ USBD_StatusInStage(); /* send Acknowledge */
+ return (__TRUE);
+ }
+
+ break;
+ }
+ }
+
+ return (__FALSE);
+}
diff -r 000000000000 -r 01f31e923fe2 source/usb/hid/usbd_hid.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/usb/hid/usbd_hid.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,557 @@
+/**
+ * @file usbd_hid.c
+ * @brief Human Interface Device driver
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+
+#include "rl_usb.h"
+#include "usb_for_lib.h"
+
+
+U8 USBD_HID_Protocol;
+
+BOOL DataOutAsyncReq;
+U32 DataOutUpdateReqMask;
+U8 *ptrDataOut;
+volatile U16 DataOutToSendLen;
+U16 DataOutSentLen;
+BOOL DataOutEndWithShortPacket;
+
+U8 *ptrDataIn;
+U16 DataInReceMax;
+U16 DataInReceLen;
+
+U8 *ptrDataFeat;
+U16 DataFeatReceLen;
+
+
+/* Dummy Weak Functions that need to be provided by user */
+__weak void usbd_hid_init(void)
+{
+
+}
+__weak int usbd_hid_get_report(U8 rtype, U8 rid, U8 *buf, U8 req)
+{
+ return (0);
+};
+__weak void usbd_hid_set_report(U8 rtype, U8 rid, U8 *buf, int len, U8 req)
+{
+
+}
+__weak U8 usbd_hid_get_protocol(void)
+{
+ return (0);
+};
+__weak void usbd_hid_set_protocol(U8 protocol)
+{
+
+};
+
+
+/*
+ * USB Device HID Get Report Request Callback
+ * Called automatically on USB Device HID Get Report Request
+ * Parameters: None
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+BOOL USBD_HID_GetReport(void)
+{
+ U8 *ptr_buf = 0;
+
+ /* Report Type = USBD_SetupPacket.wValueH */
+ /* Report ID = USBD_SetupPacket.wValueL */
+ /* Report Length = USBD_SetupPacket.wLength */
+ switch (USBD_SetupPacket.wValueH) {
+ case HID_REPORT_INPUT:
+ ptr_buf = &USBD_HID_InReport[1];
+ break;
+
+ case HID_REPORT_OUTPUT:
+ return (__FALSE); /* Not Supported */
+
+ case HID_REPORT_FEATURE:
+ ptr_buf = &USBD_HID_FeatReport[1];
+ break;
+ }
+
+ usbd_hid_get_report(USBD_SetupPacket.wValueH, USBD_SetupPacket.wValueL, ptr_buf, USBD_HID_REQ_EP_CTRL);
+ return (__TRUE);
+}
+
+
+/*
+ * USB Device HID Set Report Request Callback
+ * Called automatically on USB Device HID Set Report Request
+ * Parameters: None
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+BOOL USBD_HID_SetReport(void)
+{
+ U8 *ptr_buf = 0;
+
+ /* Report Type = USBD_SetupPacket.wValueH */
+ /* Report ID = USBD_SetupPacket.wValueL */
+ /* Report Length = USBD_SetupPacket.wLength */
+ switch (USBD_SetupPacket.wValueH) {
+ case HID_REPORT_INPUT:
+ return (__FALSE); /* Not Supported */
+
+ case HID_REPORT_OUTPUT:
+ ptr_buf = &USBD_HID_OutReport[1];
+ break;
+
+ case HID_REPORT_FEATURE:
+ ptr_buf = &USBD_HID_FeatReport[1];
+ break;
+ }
+
+ usbd_hid_set_report(USBD_SetupPacket.wValueH, USBD_SetupPacket.wValueL, ptr_buf, USBD_SetupPacket.wLength, USBD_HID_REQ_EP_CTRL);
+ return (__TRUE);
+}
+
+
+/*
+ * USB Device HID Get Idle Request Callback
+ * Called automatically on USB Device HID Get Idle Request
+ * Parameters: None
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+BOOL USBD_HID_GetIdle(void)
+{
+ USBD_EP0Buf[0] = USBD_HID_IdleSet[USBD_SetupPacket.wValueL];
+ return (__TRUE);
+}
+
+
+/*
+ * USB Device HID Set Idle Request Callback
+ * Called automatically on USB Device HID Set Idle Request
+ * Parameters: None
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+BOOL USBD_HID_SetIdle(void)
+{
+ U8 i;
+
+ if (USBD_SetupPacket.wValueL) { /* If > 0 Report ID specified */
+ USBD_HID_IdleSet[USBD_SetupPacket.wValueL - 1] = USBD_SetupPacket.wValueH;
+ } else { /* If == 0 all reports */
+ for (i = 0; i < usbd_hid_inreport_num; i++) {
+ USBD_HID_IdleSet[i] = USBD_SetupPacket.wValueH;
+ }
+ }
+
+ return (__TRUE);
+}
+
+
+/*
+ * USB Device HID Get Protocol Request Callback
+ * Called automatically on USB Device HID Get Protocol Request
+ * Parameters: None
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+BOOL USBD_HID_GetProtocol(void)
+{
+ USBD_EP0Buf[0] = usbd_hid_get_protocol();
+ return (__TRUE);
+}
+
+
+/*
+ * USB Device HID Set Protocol Request Callback
+ * Called automatically on USB Device HID Set Protocol Request
+ * Parameters: None
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+BOOL USBD_HID_SetProtocol(void)
+{
+ usbd_hid_set_protocol(USBD_SetupPacket.wValueL);
+ return (__TRUE);
+}
+
+
+/*
+ * USB Device HID Interrupt In Endpoint Event Callback
+ * Parameters: event: not used (just for compatibility)
+ * Return Value: None
+ */
+
+void USBD_HID_EP_INTIN_Event(U32 event)
+{
+ U8 i;
+ U16 bytes_to_send;
+
+ /* Check if sending is finished */
+ if ((DataOutSentLen >= DataOutToSendLen) &&
+ !DataOutEndWithShortPacket) { /* If all sent and short packet also */
+ ptrDataOut = NULL;
+ DataOutSentLen = 0;
+ DataOutToSendLen = usbd_hid_get_report(HID_REPORT_INPUT, USBD_HID_InReport[0], &USBD_HID_InReport[1], USBD_HID_REQ_EP_INT);
+
+ if (DataOutToSendLen) { /* If new send should be started */
+ ptrDataOut = USBD_HID_InReport;
+
+ if (usbd_hid_inreport_num <= 1) { /* If only in 1 report skip ReportID */
+ ptrDataOut++;
+ } else { /* If more in reports, send ReportID */
+ DataOutToSendLen++;
+ }
+ }
+ }
+
+ /* Check if new data out sending should be started */
+ if (!DataOutToSendLen) { /* If send not in progress */
+ if (DataOutAsyncReq) { /* If asynchronous send requested */
+ DataOutAsyncReq = __FALSE;
+ } else if (DataOutUpdateReqMask) { /* If update requested */
+ if (usbd_hid_inreport_num <= 1) { /* If only one in report in system */
+ if (DataOutUpdateReqMask) {
+ USBD_HID_InReport[0] = 0; /* ReportID = 0 */
+ DataOutSentLen = 0;
+ DataOutToSendLen = usbd_hid_get_report(HID_REPORT_INPUT, 0, &USBD_HID_InReport[1], USBD_HID_REQ_PERIOD_UPDATE);
+
+ if (DataOutToSendLen) {
+ ptrDataOut = &USBD_HID_InReport[1];
+ }
+
+ DataOutUpdateReqMask = 0;
+ }
+ } else { /* If multiple reports in system */
+ for (i = USBD_HID_InReport[0]; ; i++) {
+ if (i >= 32) {
+ i = 0;
+ }
+
+ if (DataOutUpdateReqMask & (1 << i)) {
+ USBD_HID_InReport[0] = i + 1; /* ReportID */
+ DataOutSentLen = 0;
+ DataOutToSendLen = usbd_hid_get_report(HID_REPORT_INPUT, i + 1, &USBD_HID_InReport[1], USBD_HID_REQ_PERIOD_UPDATE);
+
+ if (DataOutToSendLen) {
+ ptrDataOut = USBD_HID_InReport;
+ DataOutToSendLen++;
+ }
+
+ DataOutUpdateReqMask &= ~(1 << i);
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ /* Check if data needs to be sent */
+ if (DataOutToSendLen ||
+ DataOutEndWithShortPacket) { /* If sending is in progress */
+ bytes_to_send = DataOutToSendLen - DataOutSentLen;
+
+ if (bytes_to_send > usbd_hid_maxpacketsize[USBD_HighSpeed]) {
+ bytes_to_send = usbd_hid_maxpacketsize[USBD_HighSpeed];
+ }
+
+ if (usbd_hid_ep_intin != 0) { //control ep does the sending to host
+ USBD_WriteEP(usbd_hid_ep_intin | 0x80, ptrDataOut, bytes_to_send);
+ }
+
+ ptrDataOut += bytes_to_send;
+ DataOutSentLen += bytes_to_send;
+
+ if ((DataOutSentLen < usbd_hid_inreport_max_sz) &&
+ (bytes_to_send == usbd_hid_maxpacketsize[USBD_HighSpeed])) {
+ /* If short packet should be sent also*/
+ DataOutEndWithShortPacket = __TRUE;
+ } else {
+ DataOutEndWithShortPacket = __FALSE;
+ }
+ }
+}
+
+
+/*
+ * USB Device HID Interrupt Out Endpoint Event Callback
+ * Parameters: event: not used (just for compatibility)
+ * Return Value: None
+ */
+
+void USBD_HID_EP_INTOUT_Event(U32 event)
+{
+ U16 bytes_rece;
+
+ if (!DataInReceLen) { /* Check if new reception */
+ ptrDataIn = USBD_HID_OutReport;
+ DataInReceMax = usbd_hid_outreport_max_sz;
+ DataInReceLen = 0;
+ }
+
+ bytes_rece = USBD_ReadEP(usbd_hid_ep_intout, ptrDataIn, DataInReceMax - DataInReceLen);
+ ptrDataIn += bytes_rece;
+ DataInReceLen += bytes_rece;
+
+ if (!bytes_rece ||
+ (DataInReceLen >= usbd_hid_outreport_max_sz) ||
+ (bytes_rece < usbd_hid_maxpacketsize[USBD_HighSpeed])) {
+ if (usbd_hid_outreport_num <= 1) { /* If only one out report in system */
+ usbd_hid_set_report(HID_REPORT_OUTPUT, 0 , USBD_HID_OutReport , DataInReceLen, USBD_HID_REQ_EP_INT);
+ } else {
+ usbd_hid_set_report(HID_REPORT_OUTPUT, USBD_HID_OutReport[0], &USBD_HID_OutReport[1], DataInReceLen - 1, USBD_HID_REQ_EP_INT);
+ }
+
+ DataInReceLen = 0;
+ }
+}
+
+
+/*
+ * USB Device HID Configure Callback
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_HID_Configure_Event(void)
+{
+ /* Reset all variables after connect event */
+ USBD_HID_Protocol = 0;
+ DataOutAsyncReq = __FALSE;
+ DataOutUpdateReqMask = __FALSE;
+ ptrDataOut = NULL;
+ DataOutToSendLen = 0;
+ DataOutSentLen = 0;
+ DataOutEndWithShortPacket = __FALSE;
+ ptrDataIn = NULL;
+ DataInReceMax = 0;
+ DataInReceLen = 0;
+ ptrDataFeat = NULL;
+ DataFeatReceLen = 0;
+}
+
+
+/*
+ * USB Device HID Interrupt In/Out Endpoint Event Callback
+ * Parameters: event: USB Device Event
+ * USBD_EVT_IN: Input Event
+ * USBD_EVT_OUT: Output Event
+ * Return Value: None
+ */
+
+void USBD_HID_EP_INT_Event(U32 event)
+{
+ if (event & USBD_EVT_IN) {
+ USBD_HID_EP_INTIN_Event(event);
+ }
+
+ if (event & USBD_EVT_OUT) {
+ USBD_HID_EP_INTOUT_Event(event);
+ }
+}
+
+
+/*
+ * USB Device HID SOF Handler (handles report timings: polling and idle times)
+ * Called automatically on USB Device Start of Frame
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_HID_SOF_Event(void)
+{
+ static U8 cnt_for_4ms = 0;
+ U8 i;
+ BOOL tick_4ms, do_polling, polling_reload, idle_reload;
+
+ if (USBD_Configuration) {
+ tick_4ms = __FALSE;
+
+ if (cnt_for_4ms++ >= ((4 << (3 * USBD_HighSpeed))) - 1) {
+ cnt_for_4ms = 0;
+ tick_4ms = __TRUE;
+ }
+
+ polling_reload = __FALSE;
+
+ if (USBD_HID_PollingCnt < 255) {
+ USBD_HID_PollingCnt++;
+ }
+
+ if (USBD_HID_PollingCnt == usbd_hid_interval[USBD_HighSpeed]) {
+ polling_reload = __TRUE; /* If polling interval expired */
+ }
+
+ for (i = 0; i < usbd_hid_inreport_num; i++) {
+ idle_reload = __FALSE;
+
+ if (tick_4ms) {
+ if (USBD_HID_IdleCnt[i] < 255) {
+ USBD_HID_IdleCnt[i]++;
+ }
+
+ if (USBD_HID_IdleReload[i]) {
+ if (USBD_HID_IdleCnt[i] >= USBD_HID_IdleReload[i]) {
+ idle_reload = __TRUE; /* If idle period expired */
+ }
+ }
+ }
+
+ do_polling = (usbd_hid_interval[USBD_HighSpeed] > ((U16)(USBD_HID_IdleReload[i]) << (2 << (3 * USBD_HighSpeed)))) && (USBD_HID_IdleReload[i] != 0);
+
+ if (polling_reload) {
+ if (do_polling) {
+ /* If polling is longer than idle */
+ DataOutUpdateReqMask |= (1 << i);
+ }
+ }
+
+ if (USBD_HID_IdleReload[i] != USBD_HID_IdleSet[i]) {
+ if (USBD_HID_IdleCnt[i] >= USBD_HID_IdleSet[i]) {
+ DataOutUpdateReqMask |= (1 << i);
+ cnt_for_4ms = 0;
+ }
+
+ USBD_HID_IdleReload[i] = USBD_HID_IdleSet[i];
+ }
+
+ if (idle_reload) {
+ if (!do_polling) {
+ DataOutUpdateReqMask |= (1 << i);
+ }
+
+ USBD_HID_IdleCnt[i] = 0;
+ }
+ }
+
+ if (polling_reload) {
+ USBD_HID_PollingCnt = 0;
+ }
+
+ if (DataOutUpdateReqMask && !DataOutToSendLen) { /* If pending */
+ /* refresh request and no active data */
+ /* out then start data out */
+ USBD_HID_EP_INTIN_Event(0);
+ }
+ }
+}
+
+
+#ifdef __RTX /* RTX task for handling events */
+
+/*
+ * USB Device HID Interrupt In Endpoint Event Handler Task
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_RTX_HID_EP_INTIN_Event(void)
+{
+ for (;;) {
+ usbd_os_evt_wait_or(0xFFFF, 0xFFFF);
+
+ if (usbd_os_evt_get() & USBD_EVT_IN) {
+ USBD_HID_EP_INTIN_Event(0);
+ }
+ }
+}
+
+
+/*
+ * USB Device HID Interrupt Out Endpoint Event Handler Task
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_RTX_HID_EP_INTOUT_Event(void)
+{
+ for (;;) {
+ usbd_os_evt_wait_or(0xFFFF, 0xFFFF);
+
+ if (usbd_os_evt_get() & USBD_EVT_OUT) {
+ USBD_HID_EP_INTOUT_Event(0);
+ }
+ }
+}
+
+
+/*
+ * USB Device HID Interrupt In/Out Endpoint Event Handler Task
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_RTX_HID_EP_INT_Event(void)
+{
+ for (;;) {
+ usbd_os_evt_wait_or(0xFFFF, 0xFFFF);
+ USBD_HID_EP_INT_Event(usbd_os_evt_get());
+ }
+}
+#endif
+
+
+/*
+ * USB Device HID Get Report Trigger (asynchronous Get_Report request)
+ * Parameters: rid: Report ID
+ * buf: Pointer to data buffer
+ * len: Number of bytes to be sent
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+BOOL usbd_hid_get_report_trigger(U8 rid, U8 *buf, int len)
+{
+ if (len > usbd_hid_inreport_max_sz) {
+ return (__FALSE);
+ }
+
+ if (USBD_Configuration) {
+ DataOutAsyncReq = __TRUE; /* Asynchronous data out request */
+
+ while (DataOutToSendLen) {
+ if (!USBD_Configuration) { /* If device not configured reject rq */
+ DataOutAsyncReq = __FALSE; /* Asynchronous data out request */
+ ptrDataOut = NULL;
+ DataOutSentLen = 0;
+ DataOutToSendLen = 0;
+ return (__FALSE);
+ }
+ }
+
+ USBD_HID_InReport[0] = rid;
+ memcpy(&USBD_HID_InReport[1], buf, len);
+ ptrDataOut = USBD_HID_InReport;
+ DataOutSentLen = 0;
+ DataOutToSendLen = len;
+
+ if (usbd_hid_inreport_num <= 1) { /* If only 1 in report skip ReportID */
+ ptrDataOut ++;
+ } else { /* If more in reports, send ReportID */
+ DataOutToSendLen ++;
+ }
+
+ USBD_HID_EP_INTIN_Event(0);
+ USBD_HID_IdleCnt[rid] = 0;
+ return (__TRUE);
+ }
+
+ return (__FALSE);
+}
diff -r 000000000000 -r 01f31e923fe2 source/usb/hid/usbd_user_hid.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/usb/hid/usbd_user_hid.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,145 @@
+/**
+ * @file usbd_user_hid.c
+ * @brief HID driver for CMSIS-DAP packet processing
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+#include "rl_usb.h"
+#include "usb.h"
+#define __NO_USB_LIB_C
+#include "usb_config.c"
+#include "DAP_config.h"
+#include "DAP.h"
+#include "util.h"
+#include "DAP_queue.h"
+#include "main.h"
+
+
+#if (USBD_HID_OUTREPORT_MAX_SZ > DAP_PACKET_SIZE)
+#error "USB HID Output Report Size must be less than DAP Packet Size"
+#endif
+#if (USBD_HID_INREPORT_MAX_SZ > DAP_PACKET_SIZE)
+#error "USB HID Input Report Size must be less than DAP Packet Size"
+#endif
+
+static volatile uint8_t USB_ResponseIdle;
+static DAP_queue DAP_Cmd_queue;
+
+void hid_send_packet()
+{
+ uint8_t * sbuf;
+ int slen;
+ if (DAP_queue_get_send_buf(&DAP_Cmd_queue, &sbuf, &slen)) {
+ if (slen > USBD_HID_OUTREPORT_MAX_SZ){
+ util_assert(0);
+ }else {
+ usbd_hid_get_report_trigger(0, sbuf, USBD_HID_OUTREPORT_MAX_SZ);
+ }
+ }
+}
+
+// USB HID Callback: when system initializes
+void usbd_hid_init(void)
+{
+ USB_ResponseIdle = 1;
+ DAP_queue_init(&DAP_Cmd_queue);
+}
+
+// USB HID Callback: when data needs to be prepared for the host
+int usbd_hid_get_report(U8 rtype, U8 rid, U8 *buf, U8 req)
+{
+ uint8_t * sbuf;
+ int slen;
+ switch (rtype) {
+ case HID_REPORT_INPUT:
+ switch (req) {
+ case USBD_HID_REQ_PERIOD_UPDATE:
+ break;
+
+ case USBD_HID_REQ_EP_CTRL:
+ case USBD_HID_REQ_EP_INT:
+ if (DAP_queue_get_send_buf(&DAP_Cmd_queue, &sbuf, &slen)) {
+ if (slen > USBD_HID_OUTREPORT_MAX_SZ){
+ util_assert(0);
+ }else {
+ memcpy(buf, sbuf, slen);
+ return (USBD_HID_OUTREPORT_MAX_SZ);
+ }
+ } else if (req == USBD_HID_REQ_EP_INT) {
+ USB_ResponseIdle = 1;
+ }
+ break;
+ }
+
+ break;
+
+ case HID_REPORT_FEATURE:
+ break;
+ }
+
+ return (0);
+}
+
+// USB HID override function return 1 if the activity is trivial or response is null
+__attribute__((weak))
+uint8_t usbd_hid_no_activity(U8 *buf)
+{
+ return 0;
+}
+
+// USB HID Callback: when data is received from the host
+void usbd_hid_set_report(U8 rtype, U8 rid, U8 *buf, int len, U8 req)
+{
+ uint8_t * rbuf;
+ main_led_state_t led_next_state = MAIN_LED_FLASH;
+ switch (rtype) {
+ case HID_REPORT_OUTPUT:
+ if (len == 0) {
+ break;
+ }
+
+ if (buf[0] == ID_DAP_TransferAbort) {
+ DAP_TransferAbort = 1;
+ break;
+ }
+
+ // execute and store to DAP_queue
+ if (DAP_queue_execute_buf(&DAP_Cmd_queue, buf, len, &rbuf)) {
+ if(usbd_hid_no_activity(rbuf) == 1){
+ //revert HID LED to default if the response is null
+ led_next_state = MAIN_LED_DEF;
+ }
+ if (USB_ResponseIdle) {
+ hid_send_packet();
+ USB_ResponseIdle = 0;
+ }
+ } else {
+ util_assert(0);
+ }
+
+ main_blink_hid_led(led_next_state);
+
+ break;
+
+ case HID_REPORT_FEATURE:
+ break;
+ }
+}
+
+
diff -r 000000000000 -r 01f31e923fe2 source/usb/msc/usbd_core_msc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/usb/msc/usbd_core_msc.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,76 @@
+/**
+ * @file usbd_core_msc.c
+ * @brief Mass Storage Class driver
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+
+#include "rl_usb.h"
+#include "usb_for_lib.h"
+
+
+/*
+ * Clear Feature USB Device Request - MSC specific handling
+ * Parameters: EPNum: Endpoint number
+ * Return Value: None
+ */
+
+__weak void USBD_ReqClrFeature_MSC(U32 EPNum)
+{
+ USBD_MSC_ClrStallEP(EPNum);
+}
+
+
+/*
+ * USB Device Endpoint 0 Event Callback - MSC specific handling (Setup Request To Interface)
+ * Parameters: none
+ * Return Value: TRUE - Setup class request ok, FALSE - Setup class request not supported
+ */
+
+__weak BOOL USBD_EndPoint0_Setup_MSC_ReqToIF(void)
+{
+ if (USBD_SetupPacket.wIndexL == usbd_msc_if_num) { /* IF number correct? */
+ switch (USBD_SetupPacket.bRequest) {
+ case MSC_REQUEST_RESET:
+ if ((USBD_SetupPacket.wValue == 0) && /* RESET with invalid parameters -> STALL */
+ (USBD_SetupPacket.wLength == 0)) {
+ if (USBD_MSC_Reset()) {
+ USBD_StatusInStage();
+ return (__TRUE);
+ }
+ }
+
+ break;
+
+ case MSC_REQUEST_GET_MAX_LUN:
+ if ((USBD_SetupPacket.wValue == 0) && /* GET_MAX_LUN with invalid parameters -> STALL */
+ (USBD_SetupPacket.wLength == 1)) {
+ if (USBD_MSC_GetMaxLUN()) {
+ USBD_EP0Data.pData = USBD_EP0Buf;
+ USBD_DataInStage();
+ return (__TRUE);
+ }
+ }
+
+ break;
+ }
+ }
+
+ return (__FALSE);
+}
diff -r 000000000000 -r 01f31e923fe2 source/usb/msc/usbd_msc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/usb/msc/usbd_msc.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1216 @@
+/**
+ * @file usbd_msc.c
+ * @brief Mass Storage Class driver
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+
+#include "rl_usb.h"
+#include "usb_for_lib.h"
+#include "util.h"
+
+BOOL USBD_MSC_MediaReady = __FALSE;
+BOOL USBD_MSC_ReadOnly = __FALSE;
+U32 USBD_MSC_MemorySize;
+U32 USBD_MSC_BlockSize;
+U32 USBD_MSC_BlockGroup;
+U32 USBD_MSC_BlockCount;
+U8 *USBD_MSC_BlockBuf;
+
+MSC_CBW USBD_MSC_CBW; /* Command Block Wrapper */
+MSC_CSW USBD_MSC_CSW; /* Command Status Wrapper */
+
+BOOL USBD_MSC_MediaReadyEx = __FALSE; /* Previous state of Media ready */
+BOOL MemOK; /* Memory OK */
+
+U32 Block; /* R/W Block */
+U32 Offset; /* R/W Offset */
+U32 Length; /* R/W Length */
+
+U8 BulkStage; /* Bulk Stage */
+U32 BulkLen; /* Bulk In/Out Length */
+
+
+/* Dummy Weak Functions that need to be provided by user */
+__weak void usbd_msc_init()
+{
+
+}
+__weak void usbd_msc_read_sect(U32 block, U8 *buf, U32 num_of_blocks)
+{
+
+}
+__weak void usbd_msc_write_sect(U32 block, U8 *buf, U32 num_of_blocks)
+{
+
+}
+__weak void usbd_msc_start_stop(BOOL start)
+{
+
+}
+
+
+/*
+ * Set Stall for USB Device MSC Endpoint
+ * Parameters: EPNum: USB Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_MSC_SetStallEP(U32 EPNum) /* set EP halt status according stall status */
+{
+ USBD_SetStallEP(EPNum);
+ USBD_EndPointHalt |= (EPNum & 0x80) ? ((1 << 16) << (EPNum & 0x0F)) : (1 << EPNum);
+}
+
+
+/*
+ * Clear Stall for USB Device MSC Endpoint
+ * Parameters: EPNum: USB Device Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USBD_MSC_ClrStallEP(U32 EPNum) /* clear EP halt status according stall status */
+{
+ U32 n, m;
+ n = USBD_SetupPacket.wIndexL & 0x8F;
+ m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n);
+
+ if ((n == (usbd_msc_ep_bulkin | 0x80)) && ((USBD_EndPointHalt & m) != 0)) {
+ /* Compliance Test: rewrite CSW after unstall */
+ if (USBD_MSC_CSW.dSignature == MSC_CSW_Signature) {
+ USBD_WriteEP((usbd_msc_ep_bulkin | 0x80), (U8 *)&USBD_MSC_CSW, sizeof(USBD_MSC_CSW));
+ }
+ }
+}
+
+
+/*
+ * USB Device MSC Mass Storage Reset Request Callback
+ * Called automatically on USB Device Mass Storage Reset Request
+ * Parameters: None
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+BOOL USBD_MSC_Reset(void)
+{
+ USBD_EndPointStall = 0x00000000; /* EP must stay stalled */
+ USBD_MSC_CSW.dSignature = 0; /* invalid signature */
+ BulkStage = MSC_BS_RESET;
+ return (__TRUE);
+}
+
+
+/*
+ * USB Device MSC Get Max LUN Request Callback
+ * Called automatically on USB Device Get Max LUN Request
+ * Parameters: None
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+BOOL USBD_MSC_GetMaxLUN(void)
+{
+ USBD_EP0Buf[0] = 0; /* one LUN associated with this device */
+ return (__TRUE);
+}
+
+
+/*
+ * USB Device Check Media Ready
+ * Parameters: None
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+BOOL USBD_MSC_CheckMedia(void)
+{
+ USBD_MSC_MediaReadyEx = USBD_MSC_MediaReady;
+
+ if (!USBD_MSC_MediaReady) {
+ if (USBD_MSC_CBW.dDataLength) {
+ if ((USBD_MSC_CBW.bmFlags & 0x80) != 0) {
+ USBD_MSC_SetStallEP(usbd_msc_ep_bulkin | 0x80);
+ } else {
+ if (USBD_MSC_CSW.dDataResidue != BulkLen) {
+ // Only stall if this isn't the last transfer
+ USBD_MSC_SetStallEP(usbd_msc_ep_bulkout);
+ }
+ }
+ }
+
+ USBD_MSC_CSW.bStatus = CSW_CMD_FAILED;
+ USBD_MSC_SetCSW();
+ return (__FALSE);
+ }
+
+ return (__TRUE);
+}
+
+
+/*
+ * USB Device MSC Memory Read Callback
+ * Called automatically on USB Device Memory Read Event
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_MSC_MemoryRead(void)
+{
+ U32 n, m;
+
+ if (Block >= USBD_MSC_BlockCount) {
+ n = 0;
+ USBD_MSC_SetStallEP(usbd_msc_ep_bulkin | 0x80);
+ USBD_MSC_CSW.bStatus = CSW_CMD_PASSED;
+ USBD_MSC_SetCSW();
+ } else {
+ if (Length > usbd_msc_maxpacketsize[USBD_HighSpeed]) {
+ n = usbd_msc_maxpacketsize[USBD_HighSpeed];
+ } else {
+ n = Length;
+ }
+ }
+
+ if (!USBD_MSC_CheckMedia()) {
+ n = 0;
+ }
+
+ if ((Offset == 0) && (n != 0)) {
+ m = (Length + (USBD_MSC_BlockSize - 1)) / USBD_MSC_BlockSize;
+
+ if (m > USBD_MSC_BlockGroup) {
+ m = USBD_MSC_BlockGroup;
+ }
+
+ usbd_msc_read_sect(Block, USBD_MSC_BlockBuf, m);
+ }
+
+ if (n) {
+ USBD_WriteEP(usbd_msc_ep_bulkin | 0x80, &USBD_MSC_BlockBuf[Offset], n);
+ Offset += n;
+ Length -= n;
+ }
+
+ if (Offset == USBD_MSC_BlockGroup * USBD_MSC_BlockSize) {
+ Offset = 0;
+ Block += USBD_MSC_BlockGroup;
+ }
+
+ USBD_MSC_CSW.dDataResidue -= n;
+
+ if (!n) {
+ return;
+ }
+
+ if (Length == 0) {
+ BulkStage = MSC_BS_DATA_IN_LAST;
+ USBD_MSC_CSW.bStatus = CSW_CMD_PASSED;
+ }
+}
+
+
+/*
+ * USB Device MSC Memory Write Callback
+ * Called automatically on USB Device Memory Write Event
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_MSC_MemoryWrite(void)
+{
+ U32 n;
+
+ if (Block >= USBD_MSC_BlockCount) {
+ BulkLen = 0;
+ USBD_MSC_SetStallEP(usbd_msc_ep_bulkout);
+ USBD_MSC_CSW.bStatus = CSW_CMD_PASSED;
+ USBD_MSC_SetCSW();
+ }
+
+ if (!USBD_MSC_CheckMedia()) {
+ BulkLen = 0;
+ }
+
+ if (Offset + BulkLen > USBD_MSC_BlockSize) {
+ // This write would have overflowed USBD_MSC_BlockBuf
+ util_assert(0);
+ return;
+ }
+
+ for (n = 0; n < BulkLen; n++) {
+ USBD_MSC_BlockBuf[Offset + n] = USBD_MSC_BulkBuf[n];
+ }
+
+ Offset += BulkLen;
+ Length -= BulkLen;
+
+ if (BulkLen) {
+ if ((Length == 0) && (Offset != 0)) {
+ n = (Offset + (USBD_MSC_BlockSize - 1)) / USBD_MSC_BlockSize;
+
+ if (n > USBD_MSC_BlockGroup) {
+ n = USBD_MSC_BlockGroup;
+ }
+
+ usbd_msc_write_sect(Block, USBD_MSC_BlockBuf, n);
+ Offset = 0;
+ Block += n;
+ } else if (Offset == USBD_MSC_BlockGroup * USBD_MSC_BlockSize) {
+ usbd_msc_write_sect(Block, USBD_MSC_BlockBuf, USBD_MSC_BlockGroup);
+ Offset = 0;
+ Block += USBD_MSC_BlockGroup;
+ }
+ }
+
+ USBD_MSC_CSW.dDataResidue -= BulkLen;
+
+ if (!BulkLen) {
+ return;
+ }
+
+ if ((Length == 0) || (BulkStage == MSC_BS_CSW)) {
+ USBD_MSC_CSW.bStatus = CSW_CMD_PASSED;
+ USBD_MSC_SetCSW();
+ }
+}
+
+
+/*
+ * USB Device MSC Memory Verify Callback
+ * Called automatically on USB Device Memory Verify Event
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_MSC_MemoryVerify(void)
+{
+ U32 n;
+
+ if (Block >= USBD_MSC_BlockCount) {
+ BulkLen = 0;
+ USBD_MSC_SetStallEP(usbd_msc_ep_bulkout);
+ USBD_MSC_CSW.bStatus = CSW_CMD_PASSED;
+ USBD_MSC_SetCSW();
+ }
+
+ if (!USBD_MSC_CheckMedia()) {
+ BulkLen = 0;
+ }
+
+ if (BulkLen) {
+ if ((Offset == 0) && (BulkLen != 0)) {
+ n = (Length + (USBD_MSC_BlockSize - 1)) / USBD_MSC_BlockSize;
+
+ if (n > USBD_MSC_BlockGroup) {
+ n = USBD_MSC_BlockGroup;
+ }
+
+ usbd_msc_read_sect(Block, USBD_MSC_BlockBuf, n);
+ }
+
+ for (n = 0; n < BulkLen; n++) {
+ if (USBD_MSC_BlockBuf[Offset + n] != USBD_MSC_BulkBuf[n]) {
+ MemOK = __FALSE;
+ break;
+ }
+ }
+ }
+
+ Offset += BulkLen;
+ Length -= BulkLen;
+
+ if (Offset == USBD_MSC_BlockGroup * USBD_MSC_BlockSize) {
+ Offset = 0;
+ Block += USBD_MSC_BlockGroup;
+ }
+
+ USBD_MSC_CSW.dDataResidue -= BulkLen;
+
+ if (!BulkLen) {
+ return;
+ }
+
+ if ((Length == 0) || (BulkStage == MSC_BS_CSW)) {
+ USBD_MSC_CSW.bStatus = (MemOK) ? CSW_CMD_PASSED : CSW_CMD_FAILED;
+ USBD_MSC_SetCSW();
+ }
+}
+
+
+/*
+ * USB Device MSC SCSI Read/Write Setup Callback
+ * Parameters: None
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+BOOL USBD_MSC_RWSetup(void)
+{
+ U32 n;
+ /* Logical Block Address of First Block */
+ n = (USBD_MSC_CBW.CB[2] << 24) |
+ (USBD_MSC_CBW.CB[3] << 16) |
+ (USBD_MSC_CBW.CB[4] << 8) |
+ (USBD_MSC_CBW.CB[5] << 0);
+ Block = n;
+ Offset = 0;
+
+ /* Number of Blocks to transfer */
+ switch (USBD_MSC_CBW.CB[0]) {
+ case SCSI_WRITE10:
+ case SCSI_VERIFY10:
+ if (!USBD_MSC_CheckMedia()) {
+ return (__FALSE);
+ }
+
+ case SCSI_READ10:
+ n = (USBD_MSC_CBW.CB[7] << 8) |
+ (USBD_MSC_CBW.CB[8] << 0);
+ break;
+
+ case SCSI_WRITE12:
+ if (!USBD_MSC_CheckMedia()) {
+ return (__FALSE);
+ }
+
+ case SCSI_READ12:
+ n = (USBD_MSC_CBW.CB[6] << 24) |
+ (USBD_MSC_CBW.CB[7] << 16) |
+ (USBD_MSC_CBW.CB[8] << 8) |
+ (USBD_MSC_CBW.CB[9] << 0);
+ break;
+ }
+
+ Length = n * USBD_MSC_BlockSize;
+
+ if (USBD_MSC_CBW.dDataLength == 0) { /* host requests no data */
+ USBD_MSC_CSW.bStatus = CSW_CMD_FAILED;
+ USBD_MSC_SetCSW();
+ return (__FALSE);
+ }
+
+ if (USBD_MSC_CBW.dDataLength != Length) {
+ if ((USBD_MSC_CBW.bmFlags & 0x80) != 0) { /* stall appropriate EP */
+ USBD_MSC_SetStallEP(usbd_msc_ep_bulkin | 0x80);
+ } else {
+ USBD_MSC_SetStallEP(usbd_msc_ep_bulkout);
+ }
+
+ USBD_MSC_CSW.bStatus = CSW_CMD_FAILED;
+ USBD_MSC_SetCSW();
+ return (__FALSE);
+ }
+
+ return (__TRUE);
+}
+
+
+/*
+ * USB Device Check Data IN Format
+ * Parameters: None
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+BOOL USBD_MSC_DataInFormat(void)
+{
+ if (USBD_MSC_CBW.dDataLength == 0) {
+ USBD_MSC_CSW.bStatus = CSW_PHASE_ERROR;
+ USBD_MSC_SetCSW();
+ return (__FALSE);
+ }
+
+ if ((USBD_MSC_CBW.bmFlags & 0x80) == 0) {
+ USBD_MSC_SetStallEP(usbd_msc_ep_bulkout);
+ USBD_MSC_CSW.bStatus = CSW_PHASE_ERROR;
+ USBD_MSC_SetCSW();
+ return (__FALSE);
+ }
+
+ return (__TRUE);
+}
+
+
+/*
+ * USB Device Perform Data IN Transfer
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_MSC_DataInTransfer(void)
+{
+ if (BulkLen >= USBD_MSC_CBW.dDataLength) {
+ BulkLen = USBD_MSC_CBW.dDataLength;
+ BulkStage = MSC_BS_DATA_IN_LAST;
+ } else {
+ BulkStage = MSC_BS_DATA_IN_LAST_STALL; /* short or zero packet */
+ }
+
+ USBD_WriteEP(usbd_msc_ep_bulkin | 0x80, USBD_MSC_BulkBuf, BulkLen);
+ USBD_MSC_CSW.dDataResidue -= BulkLen;
+ USBD_MSC_CSW.bStatus = CSW_CMD_PASSED;
+}
+
+
+/*
+ * USB Device MSC SCSI Test Unit Ready Callback
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_MSC_TestUnitReady(void)
+{
+ if (USBD_MSC_CBW.dDataLength != 0) {
+ if ((USBD_MSC_CBW.bmFlags & 0x80) != 0) {
+ USBD_MSC_SetStallEP(usbd_msc_ep_bulkin | 0x80);
+ } else {
+ USBD_MSC_SetStallEP(usbd_msc_ep_bulkout);
+ }
+
+ USBD_MSC_CSW.bStatus = CSW_CMD_FAILED;
+ USBD_MSC_SetCSW();
+ return;
+ }
+
+ if (!USBD_MSC_CheckMedia()) {
+ return;
+ }
+
+ USBD_MSC_CSW.bStatus = CSW_CMD_PASSED;
+ USBD_MSC_SetCSW();
+}
+
+
+/*
+ * USB Device MSC SCSI Request Sense Callback
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_MSC_RequestSense(void)
+{
+ if (!USBD_MSC_DataInFormat()) {
+ return;
+ }
+
+ USBD_MSC_BulkBuf[ 0] = 0x70; /* Response Code */
+ USBD_MSC_BulkBuf[ 1] = 0x00;
+
+ if ((USBD_MSC_MediaReadyEx ^ USBD_MSC_MediaReady) & USBD_MSC_MediaReady) { /* If media state changed to ready */
+ USBD_MSC_BulkBuf[ 2] = 0x06; /* UNIT ATTENTION */
+ USBD_MSC_BulkBuf[12] = 0x28; /* Additional Sense Code: Not ready to ready transition */
+ USBD_MSC_BulkBuf[13] = 0x00; /* Additional Sense Code Qualifier */
+ USBD_MSC_MediaReadyEx = USBD_MSC_MediaReady;
+ } else if (!USBD_MSC_MediaReady) {
+ USBD_MSC_BulkBuf[ 2] = 0x02; /* NOT READY */
+ USBD_MSC_BulkBuf[12] = 0x3A; /* Additional Sense Code: Medium not present */
+ USBD_MSC_BulkBuf[13] = 0x00; /* Additional Sense Code Qualifier */
+ } else {
+ if (USBD_MSC_CSW.bStatus == CSW_CMD_PASSED) {
+ USBD_MSC_BulkBuf[ 2] = 0x00; /* NO SENSE */
+ USBD_MSC_BulkBuf[12] = 0x00; /* Additional Sense Code: No additional code */
+ USBD_MSC_BulkBuf[13] = 0x00; /* Additional Sense Code Qualifier */
+ } else {
+ USBD_MSC_BulkBuf[ 2] = 0x05; /* ILLEGAL REQUEST */
+ USBD_MSC_BulkBuf[12] = 0x20; /* Additional Sense Code: Invalid command */
+ USBD_MSC_BulkBuf[13] = 0x00; /* Additional Sense Code Qualifier */
+ }
+ }
+
+ USBD_MSC_BulkBuf[ 3] = 0x00;
+ USBD_MSC_BulkBuf[ 4] = 0x00;
+ USBD_MSC_BulkBuf[ 5] = 0x00;
+ USBD_MSC_BulkBuf[ 6] = 0x00;
+ USBD_MSC_BulkBuf[ 7] = 0x0A; /* Additional Length */
+ USBD_MSC_BulkBuf[ 8] = 0x00;
+ USBD_MSC_BulkBuf[ 9] = 0x00;
+ USBD_MSC_BulkBuf[10] = 0x00;
+ USBD_MSC_BulkBuf[11] = 0x00;
+ USBD_MSC_BulkBuf[14] = 0x00;
+ USBD_MSC_BulkBuf[15] = 0x00;
+ USBD_MSC_BulkBuf[16] = 0x00;
+ USBD_MSC_BulkBuf[17] = 0x00;
+ BulkLen = 18;
+ USBD_MSC_DataInTransfer();
+}
+
+
+/*
+ * USB Device MSC SCSI Inquiry Callback
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_MSC_Inquiry(void)
+{
+ U8 i;
+ U8 *ptr_str;
+
+ if (!USBD_MSC_DataInFormat()) {
+ return;
+ }
+
+ USBD_MSC_BulkBuf[ 0] = 0x00; /* Direct Access Device */
+ USBD_MSC_BulkBuf[ 1] = 0x80; /* RMB = 1: Removable Medium */
+ USBD_MSC_BulkBuf[ 2] = 0x02; /* Version: ANSI X3.131: 1994 */
+ USBD_MSC_BulkBuf[ 3] = 0x02;
+ USBD_MSC_BulkBuf[ 4] = 36 - 4; /* Additional Length */
+ USBD_MSC_BulkBuf[ 5] = 0x00; /* SCCS = 0: No Storage Controller Component */
+ USBD_MSC_BulkBuf[ 6] = 0x00;
+ USBD_MSC_BulkBuf[ 7] = 0x00;
+ ptr_str = (U8 *)usbd_msc_inquiry_data;
+
+ for (i = 8; i < 36; i++) { /* Product Information + */
+ if (*ptr_str) { /* Product Revision Level */
+ USBD_MSC_BulkBuf[i] = *ptr_str++;
+ } else {
+ USBD_MSC_BulkBuf[i] = ' ';
+ }
+ }
+
+ BulkLen = 36;
+ USBD_MSC_DataInTransfer();
+}
+
+
+/*
+ * USB Device MSC SCSI Start Stop Unit Callback
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_MSC_StartStopUnit(void)
+{
+ if (!USBD_MSC_CBW.CB[3]) { /* If power condition modifier is 0 */
+ USBD_MSC_MediaReady = USBD_MSC_CBW.CB[4] & 0x01; /* Media ready = START bit value */
+ usbd_msc_start_stop(USBD_MSC_MediaReady);
+ USBD_MSC_CSW.bStatus = CSW_CMD_PASSED; /* Start Stop Unit -> pass */
+ USBD_MSC_SetCSW();
+ return;
+ }
+
+ USBD_MSC_CSW.bStatus = CSW_CMD_FAILED; /* Start Stop Unit -> fail */
+ USBD_MSC_SetCSW();
+}
+
+
+/*
+ * USB Device MSC SCSI Media Removal Callback
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_MSC_MediaRemoval(void)
+{
+ if (USBD_MSC_CBW.CB[4] & 1) { /* If prevent */
+ USBD_MSC_CSW.bStatus = CSW_CMD_FAILED; /* Prevent media removal -> fail */
+ } else { /* If allow */
+ USBD_MSC_CSW.bStatus = CSW_CMD_PASSED; /* Allow media removal -> pass */
+ }
+
+ USBD_MSC_SetCSW();
+}
+
+
+/*
+ * USB Device MSC SCSI Mode Sense (6-Byte) Callback
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_MSC_ModeSense6(void)
+{
+ if (!USBD_MSC_DataInFormat()) {
+ return;
+ }
+
+ if (!USBD_MSC_CheckMedia()) {
+ return;
+ }
+
+ USBD_MSC_BulkBuf[ 0] = 0x03;
+ USBD_MSC_BulkBuf[ 1] = 0x00;
+ USBD_MSC_BulkBuf[ 2] = (USBD_MSC_ReadOnly << 7);
+ USBD_MSC_BulkBuf[ 3] = 0x00;
+ BulkLen = 4;
+
+ /* Win host requests maximum number of bytes but as all we have is 4 bytes we have
+ to tell host back that it is all we have, that's why we correct residue */
+ if (USBD_MSC_CSW.dDataResidue > BulkLen) {
+ USBD_MSC_CBW.dDataLength = BulkLen;
+ USBD_MSC_CSW.dDataResidue = BulkLen;
+ }
+
+ USBD_MSC_DataInTransfer();
+}
+
+
+/*
+ * USB Device MSC SCSI Mode Sense (10-Byte) Callback
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_MSC_ModeSense10(void)
+{
+ if (!USBD_MSC_DataInFormat()) {
+ return;
+ }
+
+ if (!USBD_MSC_CheckMedia()) {
+ return;
+ }
+
+ USBD_MSC_BulkBuf[ 0] = 0x00;
+ USBD_MSC_BulkBuf[ 1] = 0x06;
+ USBD_MSC_BulkBuf[ 2] = 0x00;
+ USBD_MSC_BulkBuf[ 3] = (USBD_MSC_ReadOnly << 7);
+ USBD_MSC_BulkBuf[ 4] = 0x00;
+ USBD_MSC_BulkBuf[ 5] = 0x00;
+ USBD_MSC_BulkBuf[ 6] = 0x00;
+ USBD_MSC_BulkBuf[ 7] = 0x00;
+ BulkLen = 8;
+
+ /* Win host requests maximum number of bytes but as all we have is 8 bytes we have
+ to tell host back that it is all we have, that's why we correct residue */
+ if (USBD_MSC_CSW.dDataResidue > BulkLen) {
+ USBD_MSC_CBW.dDataLength = BulkLen;
+ USBD_MSC_CSW.dDataResidue = BulkLen;
+ }
+
+ USBD_MSC_DataInTransfer();
+}
+
+
+/*
+ * USB Device MSC SCSI Read Capacity Callback
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_MSC_ReadCapacity(void)
+{
+ if (!USBD_MSC_DataInFormat()) {
+ return;
+ }
+
+ if (!USBD_MSC_CheckMedia()) {
+ return;
+ }
+
+ /* Last Logical Block */
+ USBD_MSC_BulkBuf[ 0] = ((USBD_MSC_BlockCount - 1) >> 24) & 0xFF;
+ USBD_MSC_BulkBuf[ 1] = ((USBD_MSC_BlockCount - 1) >> 16) & 0xFF;
+ USBD_MSC_BulkBuf[ 2] = ((USBD_MSC_BlockCount - 1) >> 8) & 0xFF;
+ USBD_MSC_BulkBuf[ 3] = ((USBD_MSC_BlockCount - 1) >> 0) & 0xFF;
+ /* Block Length */
+ USBD_MSC_BulkBuf[ 4] = (USBD_MSC_BlockSize >> 24) & 0xFF;
+ USBD_MSC_BulkBuf[ 5] = (USBD_MSC_BlockSize >> 16) & 0xFF;
+ USBD_MSC_BulkBuf[ 6] = (USBD_MSC_BlockSize >> 8) & 0xFF;
+ USBD_MSC_BulkBuf[ 7] = (USBD_MSC_BlockSize >> 0) & 0xFF;
+ BulkLen = 8;
+ USBD_MSC_DataInTransfer();
+}
+
+
+/*
+ * USB Device MSC SCSI Read Format Capacity Callback
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_MSC_ReadFormatCapacity(void)
+{
+ if (!USBD_MSC_DataInFormat()) {
+ return;
+ }
+
+ if (!USBD_MSC_CheckMedia()) {
+ return;
+ }
+
+ USBD_MSC_BulkBuf[ 0] = 0x00;
+ USBD_MSC_BulkBuf[ 1] = 0x00;
+ USBD_MSC_BulkBuf[ 2] = 0x00;
+ USBD_MSC_BulkBuf[ 3] = 0x08; /* Capacity List Length */
+ /* Block Count */
+ USBD_MSC_BulkBuf[ 4] = (USBD_MSC_BlockCount >> 24) & 0xFF;
+ USBD_MSC_BulkBuf[ 5] = (USBD_MSC_BlockCount >> 16) & 0xFF;
+ USBD_MSC_BulkBuf[ 6] = (USBD_MSC_BlockCount >> 8) & 0xFF;
+ USBD_MSC_BulkBuf[ 7] = (USBD_MSC_BlockCount >> 0) & 0xFF;
+ /* Block Length */
+ USBD_MSC_BulkBuf[ 8] = 0x02; /* Descriptor Code: Formatted Media */
+ USBD_MSC_BulkBuf[ 9] = (USBD_MSC_BlockSize >> 16) & 0xFF;
+ USBD_MSC_BulkBuf[10] = (USBD_MSC_BlockSize >> 8) & 0xFF;
+ USBD_MSC_BulkBuf[11] = (USBD_MSC_BlockSize >> 0) & 0xFF;
+ BulkLen = 12;
+
+ /* Win host requests maximum number of bytes but as all we have is 12 bytes we have
+ to tell host back that it is all we have, that's why we correct residue */
+ if (USBD_MSC_CSW.dDataResidue > BulkLen) {
+ USBD_MSC_CBW.dDataLength = BulkLen;
+ USBD_MSC_CSW.dDataResidue = BulkLen;
+ }
+
+ USBD_MSC_DataInTransfer();
+}
+
+
+/*
+ * USB Device MSC SCSI Synchronize Cache (10/16-Byte) Callback
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_MSC_SynchronizeCache(void)
+{
+ /* Synchronize check always passes as we always write data dirrectly
+ so cache is always synchronized */
+ USBD_MSC_CSW.bStatus = CSW_CMD_PASSED;
+ USBD_MSC_SetCSW();
+}
+
+
+/*
+ * USB Device MSC ATA Pass-Through Callback
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_MSC_ATAPassThrough(void)
+{
+ if (!USBD_MSC_DataInFormat()) {
+ return;
+ }
+
+ USBD_MSC_BulkBuf[ 0] = 0x02;
+ USBD_MSC_BulkBuf[ 1] = 0x02;
+ BulkLen = 2;
+ BulkStage = MSC_BS_DATA_IN_LAST;
+
+ /* Win host requests maximum number of bytes but as all we have is 2 bytes we have
+ to tell host back that it is all we have, that's why we correct residue */
+ if (USBD_MSC_CSW.dDataResidue > BulkLen) {
+ USBD_MSC_CBW.dDataLength = BulkLen;
+ USBD_MSC_CSW.dDataResidue = BulkLen;
+ }
+
+ USBD_WriteEP(usbd_msc_ep_bulkin | 0x80, USBD_MSC_BulkBuf, BulkLen);
+ USBD_MSC_CSW.dDataResidue -= BulkLen;
+ USBD_MSC_CSW.bStatus = CSW_CMD_FAILED;
+}
+
+/*
+ * USB Device MSC Service Action (16-Byte) Callback
+ * Parameters: None
+ * Return Value: None
+ */
+
+
+void USBD_MSC_ServiceActionIn16(void)
+{
+ if (!USBD_MSC_DataInFormat()) {
+ return;
+ }
+
+ USBD_MSC_BulkBuf[ 0] = 0x20;
+ USBD_MSC_BulkBuf[ 1] = 0x00;
+ USBD_MSC_BulkBuf[31] = 0x00;
+ BulkLen = 32;
+ BulkStage = MSC_BS_DATA_IN_LAST;
+ USBD_WriteEP(usbd_msc_ep_bulkin | 0x80, USBD_MSC_BulkBuf, BulkLen);
+ USBD_MSC_CSW.dDataResidue -= BulkLen;
+ USBD_MSC_CSW.bStatus = CSW_CMD_FAILED;
+}
+
+
+/*
+ * USB Device MSC Get Command Block Wrapper Callback
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_MSC_GetCBW(void)
+{
+ U32 n;
+ U32 copy_size;
+ copy_size = MIN(BulkLen, sizeof(USBD_MSC_CBW));
+
+ for (n = 0; n < copy_size; n++) {
+ *((U8 *)&USBD_MSC_CBW + n) = USBD_MSC_BulkBuf[n];
+ }
+
+ if ((BulkLen == sizeof(USBD_MSC_CBW)) && (USBD_MSC_CBW.dSignature == MSC_CBW_Signature)) {
+ /* Valid USBD_MSC_CBW */
+ USBD_MSC_CSW.dTag = USBD_MSC_CBW.dTag;
+ USBD_MSC_CSW.dDataResidue = USBD_MSC_CBW.dDataLength;
+
+ if ((USBD_MSC_CBW.bLUN > 0) ||
+ (USBD_MSC_CBW.bCBLength < 1) ||
+ (USBD_MSC_CBW.bCBLength > 16)) {
+fail:
+ USBD_MSC_CSW.bStatus = CSW_CMD_FAILED;
+ USBD_MSC_SetCSW();
+ } else {
+ switch (USBD_MSC_CBW.CB[0]) {
+ case SCSI_TEST_UNIT_READY:
+ USBD_MSC_TestUnitReady();
+ break;
+
+ case SCSI_REQUEST_SENSE:
+ USBD_MSC_RequestSense();
+ break;
+
+ case SCSI_FORMAT_UNIT:
+ goto fail;
+
+ case SCSI_INQUIRY:
+ USBD_MSC_Inquiry();
+ break;
+
+ case SCSI_START_STOP_UNIT:
+ USBD_MSC_StartStopUnit();
+ break;
+
+ case SCSI_MEDIA_REMOVAL:
+ USBD_MSC_MediaRemoval();
+ break;
+
+ case SCSI_MODE_SELECT6:
+ goto fail;
+
+ case SCSI_MODE_SENSE6:
+ USBD_MSC_ModeSense6();
+ break;
+
+ case SCSI_MODE_SELECT10:
+ goto fail;
+
+ case SCSI_MODE_SENSE10:
+ USBD_MSC_ModeSense10();
+ break;
+
+ case SCSI_READ_FORMAT_CAPACITIES:
+ USBD_MSC_ReadFormatCapacity();
+ break;
+
+ case SCSI_READ_CAPACITY:
+ USBD_MSC_ReadCapacity();
+ break;
+
+ case SCSI_ATA_COMMAND_PASS_THROUGH12:
+ USBD_MSC_ATAPassThrough();
+ break;
+
+ case SCSI_SERVICE_ACTION_IN16:
+ USBD_MSC_ServiceActionIn16();
+ break;
+
+ case SCSI_READ10:
+ case SCSI_READ12:
+ if (USBD_MSC_RWSetup()) {
+ if ((USBD_MSC_CBW.bmFlags & 0x80) != 0) {
+ BulkStage = MSC_BS_DATA_IN;
+ USBD_MSC_MemoryRead();
+ } else { /* direction mismatch */
+ USBD_MSC_SetStallEP(usbd_msc_ep_bulkout);
+ USBD_MSC_CSW.bStatus = CSW_PHASE_ERROR;
+ USBD_MSC_SetCSW();
+ }
+ }
+
+ break;
+
+ case SCSI_WRITE10:
+ case SCSI_WRITE12:
+ if (USBD_MSC_RWSetup()) {
+ if ((USBD_MSC_CBW.bmFlags & 0x80) == 0) {
+ BulkStage = MSC_BS_DATA_OUT;
+ } else { /* direction mismatch */
+ USBD_MSC_SetStallEP(usbd_msc_ep_bulkin | 0x80);
+ USBD_MSC_CSW.bStatus = CSW_PHASE_ERROR;
+ USBD_MSC_SetCSW();
+ }
+ }
+
+ break;
+
+ case SCSI_VERIFY10:
+ if ((USBD_MSC_CBW.CB[1] & 0x02) == 0) {
+ // BYTCHK = 0 -> CRC Check (not implemented)
+ USBD_MSC_CSW.bStatus = CSW_CMD_PASSED;
+ USBD_MSC_SetCSW();
+ break;
+ }
+
+ if (USBD_MSC_RWSetup()) {
+ if ((USBD_MSC_CBW.bmFlags & 0x80) == 0) {
+ BulkStage = MSC_BS_DATA_OUT;
+ MemOK = __TRUE;
+ } else {
+ USBD_MSC_SetStallEP(usbd_msc_ep_bulkin | 0x80);
+ USBD_MSC_CSW.bStatus = CSW_PHASE_ERROR;
+ USBD_MSC_SetCSW();
+ }
+ }
+
+ break;
+
+ case SCSI_SYNC_CACHE10:
+ case SCSI_SYNC_CACHE16:
+ USBD_MSC_SynchronizeCache();
+ break;
+
+ case SCSI_REPORT_ID_INFO:
+ USBD_MSC_SetStallEP(usbd_msc_ep_bulkin | 0x80);
+ goto fail;
+
+ default:
+ goto fail;
+ }
+ }
+ } else {
+ /* Invalid USBD_MSC_CBW */
+ USBD_MSC_SetStallEP(usbd_msc_ep_bulkin | 0x80);
+ /* set EP to stay stalled */
+ USBD_EndPointStall |= ((1 << 16) << (usbd_msc_ep_bulkin & 0x0F));
+ USBD_MSC_SetStallEP(usbd_msc_ep_bulkout);
+ /* set EP to stay stalled */
+ USBD_EndPointStall |= 1 << usbd_msc_ep_bulkout;
+ BulkStage = MSC_BS_ERROR;
+ }
+}
+
+
+/*
+ * USB Device MSC Set Command Status Wrapper Callback
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_MSC_SetCSW(void)
+{
+ USBD_MSC_CSW.dSignature = MSC_CSW_Signature;
+ USBD_WriteEP(usbd_msc_ep_bulkin | 0x80, (U8 *)&USBD_MSC_CSW, sizeof(USBD_MSC_CSW));
+ BulkStage = MSC_BS_CSW;
+}
+
+
+/*
+ * USB Device MSC Bulk In Callback
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_MSC_BulkIn(void)
+{
+ switch (BulkStage) {
+ case MSC_BS_DATA_IN:
+ switch (USBD_MSC_CBW.CB[0]) {
+ case SCSI_READ10:
+ case SCSI_READ12:
+ USBD_MSC_MemoryRead();
+ break;
+ }
+
+ break;
+
+ case MSC_BS_DATA_IN_LAST:
+ USBD_MSC_SetCSW();
+ break;
+
+ case MSC_BS_DATA_IN_LAST_STALL:
+ USBD_MSC_SetStallEP(usbd_msc_ep_bulkin | 0x80);
+ USBD_MSC_SetCSW();
+ break;
+
+ case MSC_BS_CSW:
+ BulkStage = MSC_BS_CBW;
+ break;
+
+ default:
+ break;
+ }
+}
+
+
+/*
+ * USB Device MSC Bulk Out Callback
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_MSC_BulkOut(void)
+{
+ switch (BulkStage) {
+ case MSC_BS_CBW:
+ USBD_MSC_GetCBW();
+ break;
+
+ case MSC_BS_DATA_OUT:
+ switch (USBD_MSC_CBW.CB[0]) {
+ case SCSI_WRITE10:
+ case SCSI_WRITE12:
+ USBD_MSC_MemoryWrite();
+ break;
+
+ case SCSI_VERIFY10:
+ USBD_MSC_MemoryVerify();
+ break;
+ }
+ break;
+
+ case MSC_BS_CSW:
+ // Previous transfer must be complete
+ // before the next transfer begins.
+ //
+ // If bulk out is stalled then just
+ // drop this packet and don't assert.
+ // This packet was left over from before
+ // the transfer aborted with a stall.
+ util_assert(USBD_EndPointHalt & (1 << usbd_msc_ep_bulkout));
+ break;
+
+ case MSC_BS_RESET:
+ // If Bulk-Only Mass Storage Reset command was received on
+ // Control Endpoint ignore next Bulk OUT transfer if it was not
+ // a CBW (as it means it was a unprocessed leftover from
+ // transfer before reset happened)
+ BulkStage = MSC_BS_CBW;
+ if (BulkLen == sizeof(USBD_MSC_CBW)) {
+ // If it is a CBW size packet go process it as CBW
+ USBD_MSC_GetCBW();
+ }
+ break;
+
+ default:
+ USBD_MSC_SetStallEP(usbd_msc_ep_bulkout);
+ USBD_MSC_CSW.bStatus = CSW_PHASE_ERROR;
+ USBD_MSC_SetCSW();
+ break;
+ }
+}
+
+/** \brief Handle Reset Events
+
+ The function handles Reset events.
+ */
+
+void USBD_MSC_Reset_Event(void)
+{
+ USBD_MSC_Reset();
+}
+
+/*
+ * USB Device MSC Bulk In Endpoint Event Callback
+ * Parameters: event: not used (just for compatibility)
+ * Return Value: None
+ */
+
+void USBD_MSC_EP_BULKIN_Event(U32 event)
+{
+ USBD_MSC_BulkIn();
+}
+
+
+/*
+ * USB Device MSC Bulk Out Endpoint Event Callback
+ * Parameters: event: not used (just for compatibility)
+ * Return Value: None
+ */
+
+void USBD_MSC_EP_BULKOUT_Event(U32 event)
+{
+ BulkLen = USBD_ReadEP(usbd_msc_ep_bulkout, USBD_MSC_BulkBuf, USBD_MSC_BulkBufSize);
+ USBD_MSC_BulkOut();
+}
+
+
+/*
+ * USB Device MSC Bulk In/Out Endpoint Event Callback
+ * Parameters: event: USB Device Event
+ * USBD_EVT_OUT: Output Event
+ * USBD_EVT_IN: Input Event
+ * Return Value: None
+ */
+
+void USBD_MSC_EP_BULK_Event(U32 event)
+{
+ if (event & USBD_EVT_OUT) {
+ USBD_MSC_EP_BULKOUT_Event(0);
+ }
+
+ if (event & USBD_EVT_IN) {
+ USBD_MSC_EP_BULKIN_Event(0);
+ }
+}
+
+
+#ifdef __RTX /* RTX tasks for handling events */
+
+/*
+ * USB Device MSC Bulk In Endpoint Event Handler Task
+ * Parameters: None
+ * Return Value: None
+ */
+
+__task void USBD_RTX_MSC_EP_BULKIN_Event(void)
+{
+ for (;;) {
+ usbd_os_evt_wait_or(0xFFFF, 0xFFFF);
+
+ if (usbd_os_evt_get() & USBD_EVT_IN) {
+ USBD_MSC_EP_BULKIN_Event(0);
+ }
+ }
+}
+
+
+/*
+ * USB Device MSC Bulk Out Endpoint Event Handler Task
+ * Parameters: None
+ * Return Value: None
+ */
+
+__task void USBD_RTX_MSC_EP_BULKOUT_Event(void)
+{
+ for (;;) {
+ usbd_os_evt_wait_or(0xFFFF, 0xFFFF);
+
+ if (usbd_os_evt_get() & USBD_EVT_OUT) {
+ USBD_MSC_EP_BULKOUT_Event(0);
+ }
+ }
+}
+
+
+/*
+ * USB Device MSC Bulk In/Out Endpoint Event Handler Task
+ * Parameters: None
+ * Return Value: None
+ */
+
+__task void USBD_RTX_MSC_EP_BULK_Event(void)
+{
+ for (;;) {
+ usbd_os_evt_wait_or(0xFFFF, 0xFFFF);
+ USBD_MSC_EP_BULK_Event(usbd_os_evt_get());
+ }
+}
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/usb/rl_usb.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/usb/rl_usb.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,99 @@
+/**
+ * @file rl_usb.h
+ * @brief USB Device Library header
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __RL_USB_H__
+#define __RL_USB_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include "usb.h"
+
+/***************** Functions *************************************************/
+
+/* USB Device functions exported from USB Device Core module */
+extern void usbd_init(void);
+extern void usbd_connect(BOOL con);
+extern void usbd_reset_core(void);
+extern BOOL usbd_configured(void);
+
+/* USB Device user functions imported to USB HID Class module */
+extern void usbd_hid_init(void);
+extern BOOL usbd_hid_get_report_trigger(U8 rid, U8 *buf, int len);
+extern int usbd_hid_get_report(U8 rtype, U8 rid, U8 *buf, U8 req);
+extern void usbd_hid_set_report(U8 rtype, U8 rid, U8 *buf, int len, U8 req);
+extern U8 usbd_hid_get_protocol(void);
+extern void usbd_hid_set_protocol(U8 protocol);
+
+/* USB Device user functions imported to USB Mass Storage Class module */
+extern void usbd_msc_init(void);
+extern void usbd_msc_read_sect(U32 block, U8 *buf, U32 num_of_blocks);
+extern void usbd_msc_write_sect(U32 block, U8 *buf, U32 num_of_blocks);
+extern void usbd_msc_start_stop(BOOL start);
+
+/* USB Device user functions imported to USB Audio Class module */
+extern void usbd_adc_init(void);
+
+/* USB Device CDC ACM class functions called automatically by USBD Core module*/
+extern int32_t USBD_CDC_ACM_Initialize(void);
+extern int32_t USBD_CDC_ACM_Uninitialize(void);
+extern int32_t USBD_CDC_ACM_Reset(void);
+/* USB Device CDC ACM class user functions */
+extern int32_t USBD_CDC_ACM_PortInitialize(void);
+extern int32_t USBD_CDC_ACM_PortUninitialize(void);
+extern int32_t USBD_CDC_ACM_PortReset(void);
+extern int32_t USBD_CDC_ACM_PortSetLineCoding(CDC_LINE_CODING *line_coding);
+extern int32_t USBD_CDC_ACM_PortGetLineCoding(CDC_LINE_CODING *line_coding);
+extern int32_t USBD_CDC_ACM_PortSetControlLineState(uint16_t ctrl_bmp);
+extern int32_t USBD_CDC_ACM_DataSend(const uint8_t *buf, int32_t len);
+extern int32_t USBD_CDC_ACM_DataFree(void);
+extern int32_t USBD_CDC_ACM_PutChar(const uint8_t ch);
+extern int32_t USBD_CDC_ACM_DataRead(uint8_t *buf, int32_t len);
+extern int32_t USBD_CDC_ACM_GetChar(void);
+extern int32_t USBD_CDC_ACM_DataAvailable(void);
+extern int32_t USBD_CDC_ACM_Notify(uint16_t stat);
+/* USB Device CDC ACM class overridable functions */
+extern int32_t USBD_CDC_ACM_SendEncapsulatedCommand(void);
+extern int32_t USBD_CDC_ACM_GetEncapsulatedResponse(void);
+extern int32_t USBD_CDC_ACM_SetCommFeature(uint16_t feat);
+extern int32_t USBD_CDC_ACM_GetCommFeature(uint16_t feat);
+extern int32_t USBD_CDC_ACM_ClearCommFeature(uint16_t feat);
+extern int32_t USBD_CDC_ACM_SetLineCoding(void);
+extern int32_t USBD_CDC_ACM_GetLineCoding(void);
+extern int32_t USBD_CDC_ACM_SetControlLineState(uint16_t ctrl_bmp);
+extern int32_t USBD_CDC_ACM_SendBreak(uint16_t dur);
+
+/* USB Device user functions imported to USB Custom Class module */
+extern void usbd_cls_init(void);
+extern void usbd_cls_sof(void);
+extern BOOL usbd_cls_dev_req(BOOL setup);
+extern BOOL usbd_cls_if_req(BOOL setup);
+extern BOOL usbd_cls_ep_req(BOOL setup);
+
+extern void usbd_bulk_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __RL_USB_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/usb.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/usb/usb.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,50 @@ +/** + * @file usb.h + * @brief USB Header + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __USB_H__ +#define __USB_H__ + +/* General USB header files */ +#include "usb_def.h" +#include "usb_cdc.h" +#include "usb_hid.h" +#include "usb_msc.h" +#include "usb_bulk.h" +#include "usb_webusb.h" +#include "usb_winusb.h" + + +/* USB Device header files */ +#include "usbd_core.h" +#include "usbd_core_cdc.h" +#include "usbd_core_hid.h" +#include "usbd_core_msc.h" +#include "usbd_core_webusb.h" +#include "usbd_core_winusb.h" + +#include "usbd_desc.h" +#include "usbd_event.h" +#include "usbd_cdc_acm.h" +#include "usbd_hid.h" +#include "usbd_msc.h" +#include "usbd_hw.h" + +#endif /* __USB_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/usb_bulk.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/usb/usb_bulk.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,32 @@ +/** + * @file usbd_bulk.h + * @brief USB Device Bulk header + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __USBD_BULK_H__ +#define __USBD_BULK_H__ + +/*--------------------------- Event handling routines ------------------------*/ + +extern void USBD_BULK_EP_BULKIN_Event(U32 event); +extern void USBD_BULK_EP_BULKOUT_Event(U32 event); +extern void USBD_BULK_EP_BULK_Event(U32 event); + + +#endif /* __USBD_BULK_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/usb_cdc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/usb/usb_cdc.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,253 @@
+/**
+ * @file usb_cdc.h
+ * @brief USB CDC driver header
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __USB_CDC_H
+#define __USB_CDC_H
+
+/*------------------------------------------------------------------------------
+ * Definitions based on usbcdc11.pdf (www.usb.org)
+ *----------------------------------------------------------------------------*/
+/* Communication device class specification version 1.10 */
+#define CDC_V1_10 0x0110
+
+/* Communication interface class code */
+/* (usbcdc11.pdf, 4.2, Table 15) */
+#define CDC_COMMUNICATION_INTERFACE_CLASS 0x02
+
+/* Communication interface class subclass codes */
+/* (usbcdc11.pdf, 4.3, Table 16) */
+#define CDC_DIRECT_LINE_CONTROL_MODEL 0x01
+#define CDC_ABSTRACT_CONTROL_MODEL 0x02
+#define CDC_TELEPHONE_CONTROL_MODEL 0x03
+#define CDC_MULTI_CHANNEL_CONTROL_MODEL 0x04
+#define CDC_CAPI_CONTROL_MODEL 0x05
+#define CDC_ETHERNET_NETWORKING_CONTROL_MODEL 0x06
+#define CDC_ATM_NETWORKING_CONTROL_MODEL 0x07
+
+/* Communication interface class control protocol codes */
+/* (usbcdc11.pdf, 4.4, Table 17) */
+#define CDC_PROTOCOL_COMMON_AT_COMMANDS 0x01
+
+/* Data interface class code */
+/* (usbcdc11.pdf, 4.5, Table 18) */
+#define CDC_DATA_INTERFACE_CLASS 0x0A
+
+/* Data interface class protocol codes */
+/* (usbcdc11.pdf, 4.7, Table 19) */
+#define CDC_PROTOCOL_ISDN_BRI 0x30
+#define CDC_PROTOCOL_HDLC 0x31
+#define CDC_PROTOCOL_TRANSPARENT 0x32
+#define CDC_PROTOCOL_Q921_MANAGEMENT 0x50
+#define CDC_PROTOCOL_Q921_DATA_LINK 0x51
+#define CDC_PROTOCOL_Q921_MULTIPLEXOR 0x52
+#define CDC_PROTOCOL_V42 0x90
+#define CDC_PROTOCOL_EURO_ISDN 0x91
+#define CDC_PROTOCOL_V24_RATE_ADAPTATION 0x92
+#define CDC_PROTOCOL_CAPI 0x93
+#define CDC_PROTOCOL_HOST_BASED_DRIVER 0xFD
+#define CDC_PROTOCOL_DESCRIBED_IN_PUFD 0xFE
+
+/* Type values for bDescriptorType field of functional descriptors */
+/* (usbcdc11.pdf, 5.2.3, Table 24) */
+#define CDC_CS_INTERFACE 0x24
+#define CDC_CS_ENDPOINT 0x25
+
+/* Type values for bDescriptorSubtype field of functional descriptors */
+/* (usbcdc11.pdf, 5.2.3, Table 25) */
+#define CDC_HEADER 0x00
+#define CDC_CALL_MANAGEMENT 0x01
+#define CDC_ABSTRACT_CONTROL_MANAGEMENT 0x02
+#define CDC_DIRECT_LINE_MANAGEMENT 0x03
+#define CDC_TELEPHONE_RINGER 0x04
+#define CDC_REPORTING_CAPABILITIES 0x05
+#define CDC_UNION 0x06
+#define CDC_COUNTRY_SELECTION 0x07
+#define CDC_TELEPHONE_OPERATIONAL_MODES 0x08
+#define CDC_USB_TERMINAL 0x09
+#define CDC_NETWORK_CHANNEL 0x0A
+#define CDC_PROTOCOL_UNIT 0x0B
+#define CDC_EXTENSION_UNIT 0x0C
+#define CDC_MULTI_CHANNEL_MANAGEMENT 0x0D
+#define CDC_CAPI_CONTROL_MANAGEMENT 0x0E
+#define CDC_ETHERNET_NETWORKING 0x0F
+#define CDC_ATM_NETWORKING 0x10
+
+/* CDC class-specific request codes */
+/* (usbcdc11.pdf, 6.2, Table 46) */
+/* see Table 45 for info about the specific requests. */
+#define CDC_SEND_ENCAPSULATED_COMMAND 0x00
+#define CDC_GET_ENCAPSULATED_RESPONSE 0x01
+#define CDC_SET_COMM_FEATURE 0x02
+#define CDC_GET_COMM_FEATURE 0x03
+#define CDC_CLEAR_COMM_FEATURE 0x04
+#define CDC_SET_AUX_LINE_STATE 0x10
+#define CDC_SET_HOOK_STATE 0x11
+#define CDC_PULSE_SETUP 0x12
+#define CDC_SEND_PULSE 0x13
+#define CDC_SET_PULSE_TIME 0x14
+#define CDC_RING_AUX_JACK 0x15
+#define CDC_SET_LINE_CODING 0x20
+#define CDC_GET_LINE_CODING 0x21
+#define CDC_SET_CONTROL_LINE_STATE 0x22
+#define CDC_SEND_BREAK 0x23
+#define CDC_SET_RINGER_PARMS 0x30
+#define CDC_GET_RINGER_PARMS 0x31
+#define CDC_SET_OPERATION_PARMS 0x32
+#define CDC_GET_OPERATION_PARMS 0x33
+#define CDC_SET_LINE_PARMS 0x34
+#define CDC_GET_LINE_PARMS 0x35
+#define CDC_DIAL_DIGITS 0x36
+#define CDC_SET_UNIT_PARAMETER 0x37
+#define CDC_GET_UNIT_PARAMETER 0x38
+#define CDC_CLEAR_UNIT_PARAMETER 0x39
+#define CDC_GET_PROFILE 0x3A
+#define CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40
+#define CDC_SET_ETHERNET_PMP_FILTER 0x41
+#define CDC_GET_ETHERNET_PMP_FILTER 0x42
+#define CDC_SET_ETHERNET_PACKET_FILTER 0x43
+#define CDC_GET_ETHERNET_STATISTIC 0x44
+#define CDC_SET_ATM_DATA_FORMAT 0x50
+#define CDC_GET_ATM_DEVICE_STATISTICS 0x51
+#define CDC_SET_ATM_DEFAULT_VC 0x52
+#define CDC_GET_ATM_VC_STATISTICS 0x53
+
+/* Communication feature selector codes */
+/* (usbcdc11.pdf, 6.2.2..6.2.4, Table 47) */
+#define CDC_ABSTRACT_STATE 0x01
+#define CDC_COUNTRY_SETTING 0x02
+
+/* Feature Status returned for ABSTRACT_STATE Selector */
+/* (usbcdc11.pdf, 6.2.3, Table 48) */
+#define CDC_IDLE_SETTING (1 << 0)
+#define CDC_DATA_MULTPLEXED_STATE (1 << 1)
+
+
+/* Control signal bitmap values for the SetControlLineState request */
+/* (usbcdc11.pdf, 6.2.14, Table 51) */
+#define CDC_DTE_PRESENT (1 << 0)
+#define CDC_ACTIVATE_CARRIER (1 << 1)
+
+/* CDC class-specific notification codes */
+/* (usbcdc11.pdf, 6.3, Table 68) */
+/* see Table 67 for Info about class-specific notifications */
+#define CDC_NOTIFICATION_NETWORK_CONNECTION 0x00
+#define CDC_RESPONSE_AVAILABLE 0x01
+#define CDC_AUX_JACK_HOOK_STATE 0x08
+#define CDC_RING_DETECT 0x09
+#define CDC_NOTIFICATION_SERIAL_STATE 0x20
+#define CDC_CALL_STATE_CHANGE 0x28
+#define CDC_LINE_STATE_CHANGE 0x29
+#define CDC_CONNECTION_SPEED_CHANGE 0x2A
+
+/* UART state bitmap values (Serial state notification). */
+/* (usbcdc11.pdf, 6.3.5, Table 69) */
+#define CDC_SERIAL_STATE_OVERRUN (1 << 6) /* receive data overrun error has occurred */
+#define CDC_SERIAL_STATE_OVERRUN_Pos ( 6)
+#define CDC_SERIAL_STATE_OVERRUN_Msk (1 << CDC_SERIAL_STATE_OVERRUN_Pos)
+#define CDC_SERIAL_STATE_PARITY (1 << 5) /* parity error has occurred */
+#define CDC_SERIAL_STATE_PARITY_Pos ( 5)
+#define CDC_SERIAL_STATE_PARITY_Msk (1 << CDC_SERIAL_STATE_PARITY_Pos)
+#define CDC_SERIAL_STATE_FRAMING (1 << 4) /* framing error has occurred */
+#define CDC_SERIAL_STATE_FRAMING_Pos ( 4)
+#define CDC_SERIAL_STATE_FRAMING_Msk (1 << CDC_SERIAL_STATE_FRAMING_Pos)
+#define CDC_SERIAL_STATE_RING (1 << 3) /* state of ring signal detection */
+#define CDC_SERIAL_STATE_RING_Pos ( 3)
+#define CDC_SERIAL_STATE_RING_Msk (1 << CDC_SERIAL_STATE_RING_Pos)
+#define CDC_SERIAL_STATE_BREAK (1 << 2) /* state of break detection */
+#define CDC_SERIAL_STATE_BREAK_Pos ( 2)
+#define CDC_SERIAL_STATE_BREAK_Msk (1 << CDC_SERIAL_STATE_BREAK_Pos)
+#define CDC_SERIAL_STATE_TX_CARRIER (1 << 1) /* state of transmission carrier */
+#define CDC_SERIAL_STATE_TX_CARRIER_Pos ( 1)
+#define CDC_SERIAL_STATE_TX_CARRIER_Msk (1 << CDC_SERIAL_STATE_TX_CARRIER_Pos)
+#define CDC_SERIAL_STATE_RX_CARRIER (1 << 0) /* state of receiver carrier */
+#define CDC_SERIAL_STATE_RX_CARRIER_Pos ( 0)
+#define CDC_SERIAL_STATE_RX_CARRIER_Msk (1 << CDC_SERIAL_STATE_RX_CARRIER_Pos)
+
+
+/*------------------------------------------------------------------------------
+ * Structures based on usbcdc11.pdf (www.usb.org)
+ *----------------------------------------------------------------------------*/
+
+/* Header functional descriptor */
+/* (usbcdc11.pdf, 5.2.3.1) */
+/* This header must precede any list of class-specific descriptors. */
+typedef __packed struct _CDC_HEADER_DESCRIPTOR {
+ U8 bFunctionLength; /* size of this descriptor in bytes */
+ U8 bDescriptorType; /* CS_INTERFACE descriptor type */
+ U8 bDescriptorSubtype; /* Header functional descriptor subtype */
+ U16 bcdCDC; /* USB CDC specification release version */
+} CDC_HEADER_DESCRIPTOR;
+
+/* Call management functional descriptor */
+/* (usbcdc11.pdf, 5.2.3.2) */
+/* Describes the processing of calls for the communication class interface. */
+typedef __packed struct _CDC_CALL_MANAGEMENT_DESCRIPTOR {
+ U8 bFunctionLength; /* size of this descriptor in bytes */
+ U8 bDescriptorType; /* CS_INTERFACE descriptor type */
+ U8 bDescriptorSubtype; /* call management functional descriptor subtype */
+ U8 bmCapabilities; /* capabilities that this configuration supports */
+ U8 bDataInterface; /* interface number of the data class interface used for call management (optional) */
+} CDC_CALL_MANAGEMENT_DESCRIPTOR;
+
+/* Abstract control management functional descriptor */
+/* (usbcdc11.pdf, 5.2.3.3) */
+/* Describes the command supported by the communication interface class with the Abstract Control Model subclass code. */
+typedef __packed struct _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR {
+ U8 bFunctionLength; /* size of this descriptor in bytes */
+ U8 bDescriptorType; /* CS_INTERFACE descriptor type */
+ U8 bDescriptorSubtype; /* abstract control management functional descriptor subtype */
+ U8 bmCapabilities; /* capabilities supported by this configuration */
+} CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR;
+
+/* Union functional descriptors */
+/* (usbcdc11.pdf, 5.2.3.8) */
+/* Describes the relationship between a group of interfaces that can be considered to form a functional unit. */
+typedef __packed struct _CDC_UNION_DESCRIPTOR {
+ U8 bFunctionLength; /* size of this descriptor in bytes */
+ U8 bDescriptorType; /* CS_INTERFACE descriptor type */
+ U8 bDescriptorSubtype; /* union functional descriptor subtype */
+ U8 bMasterInterface; /* interface number designated as master */
+} CDC_UNION_DESCRIPTOR;
+
+/* Union functional descriptors with one slave interface */
+/* (usbcdc11.pdf, 5.2.3.8) */
+typedef __packed struct _CDC_UNION_1SLAVE_DESCRIPTOR {
+ CDC_UNION_DESCRIPTOR sUnion; /* Union functional descriptor */
+ U8 bSlaveInterfaces[1]; /* Slave interface 0 */
+} CDC_UNION_1SLAVE_DESCRIPTOR;
+
+/* Line coding structure */
+/* Format of the data returned when a GetLineCoding request is received */
+/* (usbcdc11.pdf, 6.2.13) */
+typedef __packed struct _CDC_LINE_CODING {
+ U32 dwDTERate; /* Data terminal rate in bits per second */
+ U8 bCharFormat; /* Number of stop bits */
+ U8 bParityType; /* Parity bit type */
+ U8 bDataBits; /* Number of data bits */
+} CDC_LINE_CODING;
+
+/* Notification header */
+/* Data sent on the notification endpoint must follow this header. */
+/* see USB_SETUP_PACKET in file usb.h */
+typedef USB_SETUP_PACKET CDC_NOTIFICATION_HEADER;
+
+#endif /* __USB_CDC_H */
+
diff -r 000000000000 -r 01f31e923fe2 source/usb/usb_def.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/usb/usb_def.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,330 @@
+/**
+ * @file usb_def.h
+ * @brief USB defines
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __USB_DEF_H__
+#define __USB_DEF_H__
+
+#pragma anon_unions
+
+#include <stdint.h>
+#include <stddef.h>
+
+#ifndef NULL
+ #ifdef __cplusplus
+ #define NULL 0
+ #else
+ #define NULL ((void *) 0)
+ #endif
+#endif
+
+#ifndef EOF
+ #define EOF (-1)
+#endif
+
+#ifndef __size_t
+ #define __size_t 1
+ typedef unsigned int size_t;
+#endif
+
+typedef signed char S8;
+typedef unsigned char U8;
+typedef short S16;
+typedef unsigned short U16;
+typedef int S32;
+typedef unsigned int U32;
+typedef long long S64;
+typedef unsigned long long U64;
+typedef unsigned char BIT;
+typedef unsigned int BOOL;
+
+#ifndef __TRUE
+ #define __TRUE 1
+#endif
+#ifndef __FALSE
+ #define __FALSE 0
+#endif
+
+
+/* bmRequestType.Dir */
+#define REQUEST_HOST_TO_DEVICE 0
+#define REQUEST_DEVICE_TO_HOST 1
+
+/* bmRequestType.Type */
+#define REQUEST_STANDARD 0
+#define REQUEST_CLASS 1
+#define REQUEST_VENDOR 2
+#define REQUEST_RESERVED 3
+
+/* bmRequestType.Recipient */
+#define REQUEST_TO_DEVICE 0
+#define REQUEST_TO_INTERFACE 1
+#define REQUEST_TO_ENDPOINT 2
+#define REQUEST_TO_OTHER 3
+
+/* bmRequestType Definition */
+typedef __packed struct _REQUEST_TYPE {
+ U8 Recipient : 5; /* D4..0: Recipient */
+ U8 Type : 2; /* D6..5: Type */
+ U8 Dir : 1; /* D7: Data Phase Txsfer Direction */
+} REQUEST_TYPE;
+
+/* USB Standard Request Codes */
+#define USB_REQUEST_GET_STATUS 0
+#define USB_REQUEST_CLEAR_FEATURE 1
+#define USB_REQUEST_SET_FEATURE 3
+#define USB_REQUEST_SET_ADDRESS 5
+#define USB_REQUEST_GET_DESCRIPTOR 6
+#define USB_REQUEST_SET_DESCRIPTOR 7
+#define USB_REQUEST_GET_CONFIGURATION 8
+#define USB_REQUEST_SET_CONFIGURATION 9
+#define USB_REQUEST_GET_INTERFACE 10
+#define USB_REQUEST_SET_INTERFACE 11
+#define USB_REQUEST_SYNC_FRAME 12
+
+/* USB GET_STATUS Bit Values */
+#define USB_GETSTATUS_SELF_POWERED 0x01
+#define USB_GETSTATUS_REMOTE_WAKEUP 0x02
+#define USB_GETSTATUS_ENDPOINT_STALL 0x01
+
+/* USB Standard Feature selectors */
+#define USB_FEATURE_ENDPOINT_STALL 0
+#define USB_FEATURE_REMOTE_WAKEUP 1
+
+/* USB Default Control Pipe Setup Packet */
+typedef __packed struct _USB_SETUP_PACKET {
+ REQUEST_TYPE bmRequestType; /* bmRequestType */
+ U8 bRequest; /* bRequest */
+ __packed union {
+ U16 wValue; /* wValue */
+ __packed struct {
+ U8 wValueL;
+ U8 wValueH;
+ };
+ };
+ __packed union {
+ U16 wIndex; /* wIndex */
+ __packed struct {
+ U8 wIndexL;
+ U8 wIndexH;
+ };
+ };
+ U16 wLength; /* wLength */
+} USB_SETUP_PACKET;
+
+
+/* USB Descriptor Types */
+#define USB_DEVICE_DESCRIPTOR_TYPE 1
+#define USB_CONFIGURATION_DESCRIPTOR_TYPE 2
+#define USB_STRING_DESCRIPTOR_TYPE 3
+#define USB_INTERFACE_DESCRIPTOR_TYPE 4
+#define USB_ENDPOINT_DESCRIPTOR_TYPE 5
+#define USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE 6
+#define USB_OTHER_SPEED_CONFIG_DESCRIPTOR_TYPE 7
+#define USB_INTERFACE_POWER_DESCRIPTOR_TYPE 8
+#define USB_OTG_DESCRIPTOR_TYPE 9
+#define USB_DEBUG_DESCRIPTOR_TYPE 10
+#define USB_INTERFACE_ASSOCIATION_DESCRIPTOR_TYPE 11
+#define USB_BINARY_OBJECT_STORE_DESCRIPTOR_TYPE 15
+#define USB_DEVICE_CAPABILITY_DESCRIPTOR_TYPE 16
+
+/* USB Device Classes */
+#define USB_DEVICE_CLASS_RESERVED 0x00
+#define USB_DEVICE_CLASS_AUDIO 0x01
+#define USB_DEVICE_CLASS_COMMUNICATIONS 0x02
+#define USB_DEVICE_CLASS_HUMAN_INTERFACE 0x03
+#define USB_DEVICE_CLASS_MONITOR 0x04
+#define USB_DEVICE_CLASS_PHYSICAL_INTERFACE 0x05
+#define USB_DEVICE_CLASS_POWER 0x06
+#define USB_DEVICE_CLASS_PRINTER 0x07
+#define USB_DEVICE_CLASS_STORAGE 0x08
+#define USB_DEVICE_CLASS_HUB 0x09
+#define USB_DEVICE_CLASS_MISCELLANEOUS 0xEF
+#define USB_DEVICE_CLASS_APPLICATION_SPECIFIC 0xFE
+#define USB_DEVICE_CLASS_VENDOR_SPECIFIC 0xFF
+
+/* bmAttributes in Configuration Descriptor */
+#define USB_CONFIG_POWERED_MASK 0x40
+#define USB_CONFIG_BUS_POWERED 0x80
+#define USB_CONFIG_SELF_POWERED 0xC0
+#define USB_CONFIG_REMOTE_WAKEUP 0x20
+
+/* bMaxPower in Configuration Descriptor */
+#define USB_CONFIG_POWER_MA(mA) ((mA)/2)
+
+/* bEndpointAddress in Endpoint Descriptor */
+#define USB_ENDPOINT_DIRECTION_MASK 0x80
+#define USB_ENDPOINT_OUT(addr) ((addr) | 0x00)
+#define USB_ENDPOINT_IN(addr) ((addr) | 0x80)
+
+/* bmAttributes in Endpoint Descriptor */
+#define USB_ENDPOINT_TYPE_MASK 0x03
+#define USB_ENDPOINT_TYPE_CONTROL 0x00
+#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01
+#define USB_ENDPOINT_TYPE_BULK 0x02
+#define USB_ENDPOINT_TYPE_INTERRUPT 0x03
+#define USB_ENDPOINT_SYNC_MASK 0x0C
+#define USB_ENDPOINT_SYNC_NO_SYNCHRONIZATION 0x00
+#define USB_ENDPOINT_SYNC_ASYNCHRONOUS 0x04
+#define USB_ENDPOINT_SYNC_ADAPTIVE 0x08
+#define USB_ENDPOINT_SYNC_SYNCHRONOUS 0x0C
+#define USB_ENDPOINT_USAGE_MASK 0x30
+#define USB_ENDPOINT_USAGE_DATA 0x00
+#define USB_ENDPOINT_USAGE_FEEDBACK 0x10
+#define USB_ENDPOINT_USAGE_IMPLICIT_FEEDBACK 0x20
+#define USB_ENDPOINT_USAGE_RESERVED 0x30
+
+/* bDevCapabilityType in Device Capability Descriptor */
+#define USB_DEVICE_CAPABILITY_WIRELESS_USB 1
+#define USB_DEVICE_CAPABILITY_USB_2_0_EXTENSION 2
+#define USB_DEVICE_CAPABILITY_SUPERSPEED_USB 3
+#define USB_DEVICE_CAPABILITY_CONTAINER_ID 4
+#define USB_DEVICE_CAPABILITY_PLATFORM 5
+#define USB_DEVICE_CAPABILITY_POWER_DELIVERY_CAPABILITY 6
+#define USB_DEVICE_CAPABILITY_BATTERY_INFO_CAPABILITY 7
+#define USB_DEVICE_CAPABILITY_PD_CONSUMER_PORT_CAPABILITY 8
+#define USB_DEVICE_CAPABILITY_PD_PROVIDER_PORT_CAPABILITY 9
+#define USB_DEVICE_CAPABILITY_SUPERSPEED_PLUS 10
+#define USB_DEVICE_CAPABILITY_PRECISION_TIME_MEASUREMENT 11
+#define USB_DEVICE_CAPABILITY_WIRELESS_USB_EXT 12
+
+/* USB Standard Device Descriptor */
+typedef __packed struct _USB_DEVICE_DESCRIPTOR {
+ U8 bLength;
+ U8 bDescriptorType;
+ U16 bcdUSB;
+ U8 bDeviceClass;
+ U8 bDeviceSubClass;
+ U8 bDeviceProtocol;
+ U8 bMaxPacketSize0;
+ U16 idVendor;
+ U16 idProduct;
+ U16 bcdDevice;
+ U8 iManufacturer;
+ U8 iProduct;
+ U8 iSerialNumber;
+ U8 bNumConfigurations;
+} USB_DEVICE_DESCRIPTOR;
+
+/* USB 2.0 Device Qualifier Descriptor */
+typedef __packed struct _USB_DEVICE_QUALIFIER_DESCRIPTOR {
+ U8 bLength;
+ U8 bDescriptorType;
+ U16 bcdUSB;
+ U8 bDeviceClass;
+ U8 bDeviceSubClass;
+ U8 bDeviceProtocol;
+ U8 bMaxPacketSize0;
+ U8 bNumConfigurations;
+ U8 bReserved;
+} USB_DEVICE_QUALIFIER_DESCRIPTOR;
+
+/* USB Standard Configuration Descriptor */
+typedef __packed struct _USB_CONFIGURATION_DESCRIPTOR {
+ U8 bLength;
+ U8 bDescriptorType;
+ U16 wTotalLength;
+ U8 bNumInterfaces;
+ U8 bConfigurationValue;
+ U8 iConfiguration;
+ U8 bmAttributes;
+ U8 bMaxPower;
+} USB_CONFIGURATION_DESCRIPTOR;
+
+/* USB Standard Interface Descriptor */
+typedef __packed struct _USB_INTERFACE_DESCRIPTOR {
+ U8 bLength;
+ U8 bDescriptorType;
+ U8 bInterfaceNumber;
+ U8 bAlternateSetting;
+ U8 bNumEndpoints;
+ U8 bInterfaceClass;
+ U8 bInterfaceSubClass;
+ U8 bInterfaceProtocol;
+ U8 iInterface;
+} USB_INTERFACE_DESCRIPTOR;
+
+/* USB Standard Endpoint Descriptor */
+typedef __packed struct _USB_ENDPOINT_DESCRIPTOR {
+ U8 bLength;
+ U8 bDescriptorType;
+ U8 bEndpointAddress;
+ U8 bmAttributes;
+ U16 wMaxPacketSize;
+ U8 bInterval;
+} USB_ENDPOINT_DESCRIPTOR;
+
+/* USB String Descriptor */
+typedef __packed struct _USB_STRING_DESCRIPTOR {
+ U8 bLength;
+ U8 bDescriptorType;
+ U16 bString/*[]*/;
+} USB_STRING_DESCRIPTOR;
+
+/* USB Common Descriptor */
+typedef __packed struct _USB_COMMON_DESCRIPTOR {
+ U8 bLength;
+ U8 bDescriptorType;
+} USB_COMMON_DESCRIPTOR;
+
+/* USB Interface Association Descriptor */
+typedef __packed struct _USB_INTERFACE_ASSOCIATION_DESCRIPTOR {
+ U8 bLength;
+ U8 bDescriptorType;
+ U8 bFirstInterface;
+ U8 bInterfaceCount;
+ U8 bFunctionClass;
+ U8 bFunctionSubclass;
+ U8 bFunctionProtocol;
+ U8 iFunction;
+} USB_INTERFACE_ASSOCIATION_DESCRIPTOR;
+
+/* USB Binary Object Store Descriptor */
+typedef __packed struct _USB_BINARY_OBJECT_STORE_DESCRIPTOR {
+ U8 bLength;
+ U8 bDescriptorType;
+ U16 wTotalLength;
+ U8 bNumDeviceCaps;
+} USB_BINARY_OBJECT_STORE_DESCRIPTOR;
+
+/* Union Functional Descriptor */
+typedef __packed struct _UNION_FUNCTIONAL_DESCRIPTOR {
+ U8 bLength;
+ U8 bDescriptorType;
+ U8 bDescriptorSubtype;
+ U8 bMasterInterface;
+ U8 bSlaveInterface0;
+} UNION_FUNCTIONAL_DESCRIPTOR;
+
+typedef __packed struct _WINUSB_FUNCTION_SUBSET_HEADER {
+ U16 wLength;
+ U16 wDescriptorType;
+ U8 bFirstInterface;
+ U8 bReserved;
+} WINUSB_FUNCTION_SUBSET_HEADER;
+
+/* USB Device Capability Descriptor */
+typedef __packed struct _USB_DEVICE_CAPABILITY_DESCRIPTOR {
+ U8 bLength;
+ U8 bDescriptorType;
+ U8 bDevCapabilityType;
+} USB_DEVICE_CAPABILITY_DESCRIPTOR;
+
+#endif /* __USB_DEF_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/usb_for_lib.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/usb/usb_for_lib.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,33 @@ +/** + * @file usb_for_lib.h + * @brief USB driver header + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __USB_FOR_LIB_H__ +#define __USB_FOR_LIB_H__ + +/* USB Device header files */ +#include "usbd_lib_cdc.h" +#include "usbd_lib_hid.h" +#include "usbd_lib_msc.h" + +/* USB System Configuration header file */ +#include "usb_lib.h" + +#endif /* __USB_FOR_LIB_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/usb_hid.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/usb/usb_hid.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,380 @@
+/**
+ * @file usb_hid.h
+ * @brief USB hid driver header
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __USB_HID_H__
+#define __USB_HID_H__
+
+
+/* HID Subclass Codes */
+#define HID_SUBCLASS_NONE 0x00
+#define HID_SUBCLASS_BOOT 0x01
+
+/* HID Protocol Codes */
+#define HID_PROTOCOL_NONE 0x00
+#define HID_PROTOCOL_BOOT 0x00
+#define HID_PROTOCOL_KEYBOARD 0x01
+#define HID_PROTOCOL_REPORT 0x01
+#define HID_PROTOCOL_MOUSE 0x02
+
+
+/* HID Descriptor Types */
+#define HID_HID_DESCRIPTOR_TYPE 0x21
+#define HID_REPORT_DESCRIPTOR_TYPE 0x22
+#define HID_PHYSICAL_DESCRIPTOR_TYPE 0x23
+
+
+/* HID Descriptor */
+typedef __packed struct _HID_DESCRIPTOR {
+ U8 bLength;
+ U8 bDescriptorType;
+ U16 bcdHID;
+ U8 bCountryCode;
+ U8 bNumDescriptors;
+ /* Array of one or more descriptors */
+ __packed struct _HID_DESCRIPTOR_LIST {
+ U8 bDescriptorType;
+ U16 wDescriptorLength;
+ } DescriptorList[1];
+} HID_DESCRIPTOR;
+
+
+/* HID Request Codes */
+#define HID_REQUEST_GET_REPORT 0x01
+#define HID_REQUEST_GET_IDLE 0x02
+#define HID_REQUEST_GET_PROTOCOL 0x03
+#define HID_REQUEST_SET_REPORT 0x09
+#define HID_REQUEST_SET_IDLE 0x0A
+#define HID_REQUEST_SET_PROTOCOL 0x0B
+
+/* HID Report Types */
+#define HID_REPORT_INPUT 0x01
+#define HID_REPORT_OUTPUT 0x02
+#define HID_REPORT_FEATURE 0x03
+
+
+/* Usage Pages */
+#define HID_USAGE_PAGE_UNDEFINED 0x00
+#define HID_USAGE_PAGE_GENERIC 0x01
+#define HID_USAGE_PAGE_SIMULATION 0x02
+#define HID_USAGE_PAGE_VR 0x03
+#define HID_USAGE_PAGE_SPORT 0x04
+#define HID_USAGE_PAGE_GAME 0x05
+#define HID_USAGE_PAGE_DEV_CONTROLS 0x06
+#define HID_USAGE_PAGE_KEYBOARD 0x07
+#define HID_USAGE_PAGE_LED 0x08
+#define HID_USAGE_PAGE_BUTTON 0x09
+#define HID_USAGE_PAGE_ORDINAL 0x0A
+#define HID_USAGE_PAGE_TELEPHONY 0x0B
+#define HID_USAGE_PAGE_CONSUMER 0x0C
+#define HID_USAGE_PAGE_DIGITIZER 0x0D
+#define HID_USAGE_PAGE_UNICODE 0x10
+#define HID_USAGE_PAGE_ALPHANUMERIC 0x14
+/* ... */
+
+
+/* Generic Desktop Page (0x01) */
+#define HID_USAGE_GENERIC_POINTER 0x01
+#define HID_USAGE_GENERIC_MOUSE 0x02
+#define HID_USAGE_GENERIC_JOYSTICK 0x04
+#define HID_USAGE_GENERIC_GAMEPAD 0x05
+#define HID_USAGE_GENERIC_KEYBOARD 0x06
+#define HID_USAGE_GENERIC_KEYPAD 0x07
+#define HID_USAGE_GENERIC_X 0x30
+#define HID_USAGE_GENERIC_Y 0x31
+#define HID_USAGE_GENERIC_Z 0x32
+#define HID_USAGE_GENERIC_RX 0x33
+#define HID_USAGE_GENERIC_RY 0x34
+#define HID_USAGE_GENERIC_RZ 0x35
+#define HID_USAGE_GENERIC_SLIDER 0x36
+#define HID_USAGE_GENERIC_DIAL 0x37
+#define HID_USAGE_GENERIC_WHEEL 0x38
+#define HID_USAGE_GENERIC_HATSWITCH 0x39
+#define HID_USAGE_GENERIC_COUNTED_BUFFER 0x3A
+#define HID_USAGE_GENERIC_BYTE_COUNT 0x3B
+#define HID_USAGE_GENERIC_MOTION_WAKEUP 0x3C
+#define HID_USAGE_GENERIC_VX 0x40
+#define HID_USAGE_GENERIC_VY 0x41
+#define HID_USAGE_GENERIC_VZ 0x42
+#define HID_USAGE_GENERIC_VBRX 0x43
+#define HID_USAGE_GENERIC_VBRY 0x44
+#define HID_USAGE_GENERIC_VBRZ 0x45
+#define HID_USAGE_GENERIC_VNO 0x46
+#define HID_USAGE_GENERIC_SYSTEM_CTL 0x80
+#define HID_USAGE_GENERIC_SYSCTL_POWER 0x81
+#define HID_USAGE_GENERIC_SYSCTL_SLEEP 0x82
+#define HID_USAGE_GENERIC_SYSCTL_WAKE 0x83
+#define HID_USAGE_GENERIC_SYSCTL_CONTEXT_MENU 0x84
+#define HID_USAGE_GENERIC_SYSCTL_MAIN_MENU 0x85
+#define HID_USAGE_GENERIC_SYSCTL_APP_MENU 0x86
+#define HID_USAGE_GENERIC_SYSCTL_HELP_MENU 0x87
+#define HID_USAGE_GENERIC_SYSCTL_MENU_EXIT 0x88
+#define HID_USAGE_GENERIC_SYSCTL_MENU_SELECT 0x89
+#define HID_USAGE_GENERIC_SYSCTL_MENU_RIGHT 0x8A
+#define HID_USAGE_GENERIC_SYSCTL_MENU_LEFT 0x8B
+#define HID_USAGE_GENERIC_SYSCTL_MENU_UP 0x8C
+#define HID_USAGE_GENERIC_SYSCTL_MENU_DOWN 0x8D
+/* ... */
+
+/* Simulation Controls Page (0x02) */
+/* ... */
+#define HID_USAGE_SIMULATION_RUDDER 0xBA
+#define HID_USAGE_SIMULATION_THROTTLE 0xBB
+/* ... */
+
+/* Virtual Reality Controls Page (0x03) */
+/* ... */
+
+/* Sport Controls Page (0x04) */
+/* ... */
+
+/* Game Controls Page (0x05) */
+/* ... */
+
+/* Generic Device Controls Page (0x06) */
+/* ... */
+
+/* Keyboard/Keypad Page (0x07) */
+
+/* Keyboard Usage Keys */
+extern const unsigned char HID_KEYBOARD_ID_TO_ASCII[256];
+extern const unsigned char HID_KEYBOARD_ALT_ID_TO_ASCII[57];
+
+/* Error "Keys" */
+#define HID_USAGE_KEYBOARD_NOEVENT 0x00
+#define HID_USAGE_KEYBOARD_ROLLOVER 0x01
+#define HID_USAGE_KEYBOARD_POSTFAIL 0x02
+#define HID_USAGE_KEYBOARD_UNDEFINED 0x03
+
+/* Letters */
+#define HID_USAGE_KEYBOARD_aA 0x04
+#define HID_USAGE_KEYBOARD_zZ 0x1D
+
+/* Numbers */
+#define HID_USAGE_KEYBOARD_ONE 0x1E
+#define HID_USAGE_KEYBOARD_ZERO 0x27
+
+#define HID_USAGE_KEYBOARD_RETURN 0x28
+#define HID_USAGE_KEYBOARD_ESCAPE 0x29
+#define HID_USAGE_KEYBOARD_DELETE 0x2A
+
+/* Funtion Keys */
+#define HID_USAGE_KEYBOARD_F1 0x3A
+#define HID_USAGE_KEYBOARD_F12 0x45
+
+#define HID_USAGE_KEYBOARD_PRINT_SCREEN 0x46
+
+/* Modifier Keys */
+#define HID_USAGE_KEYBOARD_LCTRL 0xE0
+#define HID_USAGE_KEYBOARD_LSHFT 0xE1
+#define HID_USAGE_KEYBOARD_LALT 0xE2
+#define HID_USAGE_KEYBOARD_LGUI 0xE3
+#define HID_USAGE_KEYBOARD_RCTRL 0xE4
+#define HID_USAGE_KEYBOARD_RSHFT 0xE5
+#define HID_USAGE_KEYBOARD_RALT 0xE6
+#define HID_USAGE_KEYBOARD_RGUI 0xE7
+#define HID_USAGE_KEYBOARD_SCROLL_LOCK 0x47
+#define HID_USAGE_KEYBOARD_NUM_LOCK 0x53
+#define HID_USAGE_KEYBOARD_CAPS_LOCK 0x39
+
+/* Modifier Keys (values) */
+#define HID_USAGE_KEYBOARD_MOD_LCTRL 0x01
+#define HID_USAGE_KEYBOARD_MOD_LSHIFT 0x02
+#define HID_USAGE_KEYBOARD_MOD_LALTL 0x04
+#define HID_USAGE_KEYBOARD_MOD_LGUI 0x08
+#define HID_USAGE_KEYBOARD_MOD_RCTRL 0x10
+#define HID_USAGE_KEYBOARD_MOD_RSHIFT 0x20
+#define HID_USAGE_KEYBOARD_MOD_RALTL 0x40
+#define HID_USAGE_KEYBOARD_MOD_RGUI 0x80
+
+/* ... */
+
+/* LED Page (0x08) */
+#define HID_USAGE_LED_NUM_LOCK 0x01
+#define HID_USAGE_LED_CAPS_LOCK 0x02
+#define HID_USAGE_LED_SCROLL_LOCK 0x03
+#define HID_USAGE_LED_COMPOSE 0x04
+#define HID_USAGE_LED_KANA 0x05
+#define HID_USAGE_LED_POWER 0x06
+#define HID_USAGE_LED_SHIFT 0x07
+#define HID_USAGE_LED_DO_NOT_DISTURB 0x08
+#define HID_USAGE_LED_MUTE 0x09
+#define HID_USAGE_LED_TONE_ENABLE 0x0A
+#define HID_USAGE_LED_HIGH_CUT_FILTER 0x0B
+#define HID_USAGE_LED_LOW_CUT_FILTER 0x0C
+#define HID_USAGE_LED_EQUALIZER_ENABLE 0x0D
+#define HID_USAGE_LED_SOUND_FIELD_ON 0x0E
+#define HID_USAGE_LED_SURROUND_FIELD_ON 0x0F
+#define HID_USAGE_LED_REPEAT 0x10
+#define HID_USAGE_LED_STEREO 0x11
+#define HID_USAGE_LED_SAMPLING_RATE_DETECT 0x12
+#define HID_USAGE_LED_SPINNING 0x13
+#define HID_USAGE_LED_CAV 0x14
+#define HID_USAGE_LED_CLV 0x15
+#define HID_USAGE_LED_RECORDING_FORMAT_DET 0x16
+#define HID_USAGE_LED_OFF_HOOK 0x17
+#define HID_USAGE_LED_RING 0x18
+#define HID_USAGE_LED_MESSAGE_WAITING 0x19
+#define HID_USAGE_LED_DATA_MODE 0x1A
+#define HID_USAGE_LED_BATTERY_OPERATION 0x1B
+#define HID_USAGE_LED_BATTERY_OK 0x1C
+#define HID_USAGE_LED_BATTERY_LOW 0x1D
+#define HID_USAGE_LED_SPEAKER 0x1E
+#define HID_USAGE_LED_HEAD_SET 0x1F
+#define HID_USAGE_LED_HOLD 0x20
+#define HID_USAGE_LED_MICROPHONE 0x21
+#define HID_USAGE_LED_COVERAGE 0x22
+#define HID_USAGE_LED_NIGHT_MODE 0x23
+#define HID_USAGE_LED_SEND_CALLS 0x24
+#define HID_USAGE_LED_CALL_PICKUP 0x25
+#define HID_USAGE_LED_CONFERENCE 0x26
+#define HID_USAGE_LED_STAND_BY 0x27
+#define HID_USAGE_LED_CAMERA_ON 0x28
+#define HID_USAGE_LED_CAMERA_OFF 0x29
+#define HID_USAGE_LED_ON_LINE 0x2A
+#define HID_USAGE_LED_OFF_LINE 0x2B
+#define HID_USAGE_LED_BUSY 0x2C
+#define HID_USAGE_LED_READY 0x2D
+#define HID_USAGE_LED_PAPER_OUT 0x2E
+#define HID_USAGE_LED_PAPER_JAM 0x2F
+#define HID_USAGE_LED_REMOTE 0x30
+#define HID_USAGE_LED_FORWARD 0x31
+#define HID_USAGE_LED_REVERSE 0x32
+#define HID_USAGE_LED_STOP 0x33
+#define HID_USAGE_LED_REWIND 0x34
+#define HID_USAGE_LED_FAST_FORWARD 0x35
+#define HID_USAGE_LED_PLAY 0x36
+#define HID_USAGE_LED_PAUSE 0x37
+#define HID_USAGE_LED_RECORD 0x38
+#define HID_USAGE_LED_ERROR 0x39
+#define HID_USAGE_LED_SELECTED_INDICATOR 0x3A
+#define HID_USAGE_LED_IN_USE_INDICATOR 0x3B
+#define HID_USAGE_LED_MULTI_MODE_INDICATOR 0x3C
+#define HID_USAGE_LED_INDICATOR_ON 0x3D
+#define HID_USAGE_LED_INDICATOR_FLASH 0x3E
+#define HID_USAGE_LED_INDICATOR_SLOW_BLINK 0x3F
+#define HID_USAGE_LED_INDICATOR_FAST_BLINK 0x40
+#define HID_USAGE_LED_INDICATOR_OFF 0x41
+#define HID_USAGE_LED_FLASH_ON_TIME 0x42
+#define HID_USAGE_LED_SLOW_BLINK_ON_TIME 0x43
+#define HID_USAGE_LED_SLOW_BLINK_OFF_TIME 0x44
+#define HID_USAGE_LED_FAST_BLINK_ON_TIME 0x45
+#define HID_USAGE_LED_FAST_BLINK_OFF_TIME 0x46
+#define HID_USAGE_LED_INDICATOR_COLOR 0x47
+#define HID_USAGE_LED_RED 0x48
+#define HID_USAGE_LED_GREEN 0x49
+#define HID_USAGE_LED_AMBER 0x4A
+#define HID_USAGE_LED_GENERIC_INDICATOR 0x4B
+
+/* Button Page (0x09) */
+/* There is no need to label these usages. */
+
+/* Ordinal Page (0x0A) */
+/* There is no need to label these usages. */
+
+/* Telephony Device Page (0x0B) */
+#define HID_USAGE_TELEPHONY_PHONE 0x01
+#define HID_USAGE_TELEPHONY_ANSWERING_MACHINE 0x02
+#define HID_USAGE_TELEPHONY_MESSAGE_CONTROLS 0x03
+#define HID_USAGE_TELEPHONY_HANDSET 0x04
+#define HID_USAGE_TELEPHONY_HEADSET 0x05
+#define HID_USAGE_TELEPHONY_KEYPAD 0x06
+#define HID_USAGE_TELEPHONY_PROGRAMMABLE_BUTTON 0x07
+/* ... */
+
+/* Consumer Page (0x0C) */
+#define HID_USAGE_CONSUMER_CONTROL 0x01
+/* ... */
+
+/* and others ... */
+
+
+/* HID Report Item Macros */
+
+/* Main Items */
+#define HID_Input(x) 0x81,x
+#define HID_Output(x) 0x91,x
+#define HID_Feature(x) 0xB1,x
+#define HID_Collection(x) 0xA1,x
+#define HID_EndCollection 0xC0
+
+/* Data (Input, Output, Feature) */
+#define HID_Data 0<<0
+#define HID_Constant 1<<0
+#define HID_Array 0<<1
+#define HID_Variable 1<<1
+#define HID_Absolute 0<<2
+#define HID_Relative 1<<2
+#define HID_NoWrap 0<<3
+#define HID_Wrap 1<<3
+#define HID_Linear 0<<4
+#define HID_NonLinear 1<<4
+#define HID_PreferredState 0<<5
+#define HID_NoPreferred 1<<5
+#define HID_NoNullPosition 0<<6
+#define HID_NullState 1<<6
+#define HID_NonVolatile 0<<7
+#define HID_Volatile 1<<7
+
+/* Collection Data */
+#define HID_Physical 0x00
+#define HID_Application 0x01
+#define HID_Logical 0x02
+#define HID_Report 0x03
+#define HID_NamedArray 0x04
+#define HID_UsageSwitch 0x05
+#define HID_UsageModifier 0x06
+
+/* Global Items */
+#define HID_UsagePage(x) 0x05,x
+#define HID_UsagePageVendor(x) 0x06,x,0xFF
+#define HID_LogicalMin(x) 0x15,x
+#define HID_LogicalMinS(x) 0x16,(x&0xFF),((x>>8)&0xFF)
+#define HID_LogicalMinL(x) 0x17,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF)
+#define HID_LogicalMax(x) 0x25,x
+#define HID_LogicalMaxS(x) 0x26,(x&0xFF),((x>>8)&0xFF)
+#define HID_LogicalMaxL(x) 0x27,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF)
+#define HID_PhysicalMin(x) 0x35,x
+#define HID_PhysicalMinS(x) 0x36,(x&0xFF),((x>>8)&0xFF)
+#define HID_PhysicalMinL(x) 0x37,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF)
+#define HID_PhysicalMax(x) 0x45,x
+#define HID_PhysicalMaxS(x) 0x46,(x&0xFF),((x>>8)&0xFF)
+#define HID_PhysicalMaxL(x) 0x47,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF)
+#define HID_UnitExponent(x) 0x55,x
+#define HID_Unit(x) 0x65,x
+#define HID_UnitS(x) 0x66,(x&0xFF),((x>>8)&0xFF)
+#define HID_UnitL(x) 0x67,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF)
+#define HID_ReportSize(x) 0x75,x
+#define HID_ReportSizeS(x) 0x76,(x&0xFF),((x>>8)&0xFF)
+#define HID_ReportSizeL(x) 0x77,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF)
+#define HID_ReportID(x) 0x85,x
+#define HID_ReportCount(x) 0x95,x
+#define HID_ReportCountS(x) 0x96,(x&0xFF),((x>>8)&0xFF)
+#define HID_ReportCountL(x) 0x97,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF)
+#define HID_Push 0xA4
+#define HID_Pop 0xB4
+
+/* Local Items */
+#define HID_Usage(x) 0x09,x
+#define HID_UsageMin(x) 0x19,x
+#define HID_UsageMax(x) 0x29,x
+
+
+#endif /* __USB_HID_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/usb_lib.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/usb/usb_lib.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,2741 @@
+/**
+ * @file usb_lib.c
+ * @brief USB library
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+#include "rl_usb.h"
+#include "usb.h"
+#include "settings.h"
+
+#pragma thumb
+#pragma O3
+
+
+/*------------------------------------------------------------------------------
+ * Library for usb_config.c
+ *----------------------------------------------------------------------------*/
+
+#ifdef __USB_CONFIG__
+
+/*------------------------------------------------------------------------------
+ * USB Device Configuration
+ *----------------------------------------------------------------------------*/
+
+#if (USBD_ENABLE)
+
+U8 USBD_AltSetting[USBD_IF_NUM_MAX];
+U8 USBD_EP0Buf[USBD_MAX_PACKET0];
+const U8 usbd_power = USBD_POWER;
+const U8 usbd_hs_enable = USBD_HS_ENABLE;
+const U8 usbd_bos_enable = USBD_BOS_ENABLE;
+U16 usbd_if_num = USBD_IF_NUM_MAX;
+const U8 usbd_ep_num = USBD_EP_NUM;
+const U8 usbd_max_packet0 = USBD_MAX_PACKET0;
+
+
+/*------------------------------------------------------------------------------
+ * USB Device Class Configuration
+ *----------------------------------------------------------------------------*/
+
+#if (!USBD_HID_BINTERVAL)
+#define USBD_HID_INTERVAL 1
+#else
+#define USBD_HID_INTERVAL USBD_HID_BINTERVAL
+#endif
+#if (!USBD_HID_HS_BINTERVAL)
+#define USBD_HID_HS_INTERVAL 1
+#else
+#define USBD_HID_HS_INTERVAL (2 << ((USBD_HID_HS_BINTERVAL & 0x0F)-1))
+#endif
+
+#if (USBD_HID_ENABLE)
+U8 usbd_hid_if_num; //assigned during runtime init
+const U8 usbd_hid_ep_intin = USBD_HID_EP_INTIN;
+const U8 usbd_hid_ep_intout = USBD_HID_EP_INTOUT;
+const U16 usbd_hid_interval[2] = {USBD_HID_INTERVAL, USBD_HID_HS_INTERVAL};
+const U16 usbd_hid_maxpacketsize[2] = {USBD_HID_WMAXPACKETSIZE, USBD_HID_HS_WMAXPACKETSIZE};
+const U8 usbd_hid_inreport_num = USBD_HID_INREPORT_NUM;
+const U8 usbd_hid_outreport_num = USBD_HID_OUTREPORT_NUM;
+const U16 usbd_hid_inreport_max_sz = USBD_HID_INREPORT_MAX_SZ;
+const U16 usbd_hid_outreport_max_sz = USBD_HID_OUTREPORT_MAX_SZ;
+const U16 usbd_hid_featreport_max_sz = USBD_HID_FEATREPORT_MAX_SZ;
+U16 USBD_HID_PollingCnt;
+U8 USBD_HID_IdleCnt[USBD_HID_INREPORT_NUM];
+U8 USBD_HID_IdleReload[USBD_HID_INREPORT_NUM];
+U8 USBD_HID_IdleSet[USBD_HID_INREPORT_NUM];
+U8 USBD_HID_InReport[USBD_HID_INREPORT_MAX_SZ + 1];
+U8 USBD_HID_OutReport[USBD_HID_OUTREPORT_MAX_SZ + 1];
+U8 USBD_HID_FeatReport[USBD_HID_FEATREPORT_MAX_SZ + 1];
+#endif
+
+#if (USBD_MSC_ENABLE)
+U8 usbd_msc_if_num; //assigned during runtime init
+const U8 usbd_msc_ep_bulkin = USBD_MSC_EP_BULKIN;
+const U8 usbd_msc_ep_bulkout = USBD_MSC_EP_BULKOUT;
+const U16 usbd_msc_maxpacketsize[2] = {USBD_MSC_WMAXPACKETSIZE, USBD_MSC_HS_WMAXPACKETSIZE};
+const U8 *usbd_msc_inquiry_data = USBD_MSC_INQUIRY_DATA;
+const U16 USBD_MSC_BulkBufSize = USBD_MSC_MAX_PACKET;
+U8 USBD_MSC_BulkBuf[USBD_MSC_MAX_PACKET];
+#endif
+
+#if (USBD_ADC_ENABLE)
+const U8 usbd_adc_cif_num = USBD_ADC_CIF_NUM;
+const U8 usbd_adc_sif1_num = USBD_ADC_SIF1_NUM;
+const U8 usbd_adc_sif2_num = USBD_ADC_SIF2_NUM;
+const U8 usbd_adc_ep_isoout = USBD_ADC_EP_ISOOUT;
+const U32 usbd_adc_cfg_datafreq = USBD_ADC_TSAMFREQ;
+const U32 usbd_adc_cfg_p_s = USBD_ADC_CFG_P_S;
+const U32 usbd_adc_cfg_p_c = USBD_ADC_CFG_P_C;
+const U32 usbd_adc_cfg_b_s = (8 * USBD_ADC_CFG_P_C *USBD_ADC_CFG_P_S);
+S16 USBD_ADC_DataBuf[8 * USBD_ADC_CFG_P_C * USBD_ADC_CFG_P_S];
+#endif
+
+#ifndef USBD_CDC_ACM_ENABLE
+#if (USBD_CDC_ENABLE == 1)
+#error "Please update usb_config.c file with new definitions for CDC, as new CDC is incompatible with the old one!"
+#else
+#define USBD_CDC_ACM_ENABLE 0
+#endif
+#endif
+
+#if (USBD_CDC_ACM_ENABLE)
+U8 usbd_cdc_acm_cif_num = 0; //assigned during runtime init
+U8 usbd_cdc_acm_dif_num = 0; //assigned during runtime init
+const U8 usbd_cdc_acm_ep_intin = USBD_CDC_ACM_EP_INTIN;
+const U8 usbd_cdc_acm_ep_bulkin = USBD_CDC_ACM_EP_BULKIN;
+const U8 usbd_cdc_acm_ep_bulkout = USBD_CDC_ACM_EP_BULKOUT;
+const U16 usbd_cdc_acm_sendbuf_sz = USBD_CDC_ACM_SENDBUF_SIZE;
+const U16 usbd_cdc_acm_receivebuf_sz = USBD_CDC_ACM_RECEIVEBUF_SIZE;
+const U16 usbd_cdc_acm_maxpacketsize[2] = {USBD_CDC_ACM_WMAXPACKETSIZE, USBD_CDC_ACM_HS_WMAXPACKETSIZE};
+const U16 usbd_cdc_acm_maxpacketsize1[2] = {USBD_CDC_ACM_WMAXPACKETSIZE1, USBD_CDC_ACM_HS_WMAXPACKETSIZE1};
+U8 USBD_CDC_ACM_SendBuf[USBD_CDC_ACM_SENDBUF_SIZE];
+U8 USBD_CDC_ACM_ReceiveBuf[USBD_CDC_ACM_RECEIVEBUF_SIZE];
+U8 USBD_CDC_ACM_NotifyBuf[10];
+#endif
+
+#if (USBD_WEBUSB_ENABLE)
+U8 usbd_webusb_if_num; //assigned during runtime init
+const U8 usbd_webusb_vendor_code = USBD_WEBUSB_VENDOR_CODE;
+#else
+const U8 usbd_webusb_vendor_code;
+#endif
+
+#if (USBD_WINUSB_ENABLE)
+const U8 usbd_winusb_vendor_code = USBD_WINUSB_VENDOR_CODE;
+#else
+const U8 usbd_winusb_vendor_code;
+#endif
+
+#if (USBD_BULK_ENABLE)
+U8 usbd_bulk_if_num = 0; //assigned during runtime init
+const U8 usbd_bulk_ep_bulkin = USBD_BULK_EP_BULKIN;
+const U8 usbd_bulk_ep_bulkout = USBD_BULK_EP_BULKOUT;
+const U16 usbd_bulk_maxpacketsize[2] = {USBD_BULK_WMAXPACKETSIZE, USBD_BULK_HS_WMAXPACKETSIZE};
+const U16 USBD_Bulk_BulkBufSize = USBD_BULK_MAX_PACKET;
+U8 USBD_Bulk_BulkInBuf[USBD_BULK_MAX_PACKET];
+U8 USBD_Bulk_BulkOutBuf[USBD_BULK_MAX_PACKET];
+#endif
+
+/*------------------------------------------------------------------------------
+ * USB Device Override Event Handler Fuctions
+ *----------------------------------------------------------------------------*/
+
+#if (USBD_HID_ENABLE)
+#ifndef __RTX
+void USBD_Configure_Event(void)
+{
+ USBD_HID_Configure_Event();
+}
+#endif
+#ifdef __RTX
+#if ((USBD_HID_EP_INTOUT != 0) && (USBD_HID_EP_INTIN != USBD_HID_EP_INTOUT))
+#if (USBD_HID_EP_INTIN == 1)
+#define USBD_RTX_EndPoint1 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 2)
+#define USBD_RTX_EndPoint2 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 3)
+#define USBD_RTX_EndPoint3 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 4)
+#define USBD_RTX_EndPoint4 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 5)
+#define USBD_RTX_EndPoint5 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 6)
+#define USBD_RTX_EndPoint6 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 7)
+#define USBD_RTX_EndPoint7 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 8)
+#define USBD_RTX_EndPoint8 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 9)
+#define USBD_RTX_EndPoint9 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 10)
+#define USBD_RTX_EndPoint10 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 11)
+#define USBD_RTX_EndPoint11 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 12)
+#define USBD_RTX_EndPoint12 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 13)
+#define USBD_RTX_EndPoint13 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 14)
+#define USBD_RTX_EndPoint14 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 15)
+#define USBD_RTX_EndPoint15 USBD_RTX_HID_EP_INTIN_Event
+#endif
+
+#if (USBD_HID_EP_INTOUT == 1)
+#define USBD_RTX_EndPoint1 USBD_RTX_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 2)
+#define USBD_RTX_EndPoint2 USBD_RTX_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 3)
+#define USBD_RTX_EndPoint3 USBD_RTX_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 4)
+#define USBD_RTX_EndPoint4 USBD_RTX_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 5)
+#define USBD_RTX_EndPoint5 USBD_RTX_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 6)
+#define USBD_RTX_EndPoint6 USBD_RTX_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 7)
+#define USBD_RTX_EndPoint7 USBD_RTX_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 8)
+#define USBD_RTX_EndPoint8 USBD_RTX_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 9)
+#define USBD_RTX_EndPoint9 USBD_RTX_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 10)
+#define USBD_RTX_EndPoint10 USBD_RTX_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 11)
+#define USBD_RTX_EndPoint11 USBD_RTX_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 12)
+#define USBD_RTX_EndPoint12 USBD_RTX_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 13)
+#define USBD_RTX_EndPoint13 USBD_RTX_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 14)
+#define USBD_RTX_EndPoint14 USBD_RTX_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 15)
+#define USBD_RTX_EndPoint15 USBD_RTX_HID_EP_INTOUT_Event
+#endif
+#elif (USBD_HID_EP_INTOUT != 0)
+#if (USBD_HID_EP_INTIN == 1)
+#define USBD_RTX_EndPoint1 USBD_RTX_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 2)
+#define USBD_RTX_EndPoint2 USBD_RTX_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 3)
+#define USBD_RTX_EndPoint3 USBD_RTX_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 4)
+#define USBD_RTX_EndPoint4 USBD_RTX_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 5)
+#define USBD_RTX_EndPoint5 USBD_RTX_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 6)
+#define USBD_RTX_EndPoint6 USBD_RTX_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 7)
+#define USBD_RTX_EndPoint7 USBD_RTX_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 8)
+#define USBD_RTX_EndPoint8 USBD_RTX_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 9)
+#define USBD_RTX_EndPoint9 USBD_RTX_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 10)
+#define USBD_RTX_EndPoint10 USBD_RTX_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 11)
+#define USBD_RTX_EndPoint11 USBD_RTX_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 12)
+#define USBD_RTX_EndPoint12 USBD_RTX_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 13)
+#define USBD_RTX_EndPoint13 USBD_RTX_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 14)
+#define USBD_RTX_EndPoint14 USBD_RTX_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 15)
+#define USBD_RTX_EndPoint15 USBD_RTX_HID_EP_INT_Event
+#endif
+#else
+#if (USBD_HID_EP_INTIN == 1)
+#define USBD_RTX_EndPoint1 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 2)
+#define USBD_RTX_EndPoint2 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 3)
+#define USBD_RTX_EndPoint3 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 4)
+#define USBD_RTX_EndPoint4 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 5)
+#define USBD_RTX_EndPoint5 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 6)
+#define USBD_RTX_EndPoint6 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 7)
+#define USBD_RTX_EndPoint7 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 8)
+#define USBD_RTX_EndPoint8 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 9)
+#define USBD_RTX_EndPoint9 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 10)
+#define USBD_RTX_EndPoint10 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 11)
+#define USBD_RTX_EndPoint11 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 12)
+#define USBD_RTX_EndPoint12 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 13)
+#define USBD_RTX_EndPoint13 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 14)
+#define USBD_RTX_EndPoint14 USBD_RTX_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 15)
+#define USBD_RTX_EndPoint15 USBD_RTX_HID_EP_INTIN_Event
+#endif
+#endif
+#else
+#if (USBD_HID_EP_INTIN != USBD_HID_EP_INTOUT)
+#if (USBD_HID_EP_INTIN == 1)
+#define USBD_EndPoint1 USBD_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 2)
+#define USBD_EndPoint2 USBD_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 3)
+#define USBD_EndPoint3 USBD_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 4)
+#define USBD_EndPoint4 USBD_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 5)
+#define USBD_EndPoint5 USBD_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 6)
+#define USBD_EndPoint6 USBD_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 7)
+#define USBD_EndPoint7 USBD_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 8)
+#define USBD_EndPoint8 USBD_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 9)
+#define USBD_EndPoint9 USBD_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 10)
+#define USBD_EndPoint10 USBD_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 11)
+#define USBD_EndPoint11 USBD_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 12)
+#define USBD_EndPoint12 USBD_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 13)
+#define USBD_EndPoint13 USBD_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 14)
+#define USBD_EndPoint14 USBD_HID_EP_INTIN_Event
+#elif (USBD_HID_EP_INTIN == 15)
+#define USBD_EndPoint15 USBD_HID_EP_INTIN_Event
+#endif
+
+#if (USBD_HID_EP_INTOUT == 1)
+#define USBD_EndPoint1 USBD_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 2)
+#define USBD_EndPoint2 USBD_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 3)
+#define USBD_EndPoint3 USBD_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 4)
+#define USBD_EndPoint4 USBD_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 5)
+#define USBD_EndPoint5 USBD_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 6)
+#define USBD_EndPoint6 USBD_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 7)
+#define USBD_EndPoint7 USBD_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 8)
+#define USBD_EndPoint8 USBD_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 9)
+#define USBD_EndPoint9 USBD_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 10)
+#define USBD_EndPoint10 USBD_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 11)
+#define USBD_EndPoint11 USBD_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 12)
+#define USBD_EndPoint12 USBD_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 13)
+#define USBD_EndPoint13 USBD_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 14)
+#define USBD_EndPoint14 USBD_HID_EP_INTOUT_Event
+#elif (USBD_HID_EP_INTOUT == 15)
+#define USBD_EndPoint15 USBD_HID_EP_INTOUT_Event
+#endif
+
+#else
+
+#if (USBD_HID_EP_INTIN == 1)
+#define USBD_EndPoint1 USBD_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 2)
+#define USBD_EndPoint2 USBD_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 3)
+#define USBD_EndPoint3 USBD_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 4)
+#define USBD_EndPoint4 USBD_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 5)
+#define USBD_EndPoint5 USBD_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 6)
+#define USBD_EndPoint6 USBD_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 7)
+#define USBD_EndPoint7 USBD_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 8)
+#define USBD_EndPoint8 USBD_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 9)
+#define USBD_EndPoint9 USBD_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 10)
+#define USBD_EndPoint10 USBD_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 11)
+#define USBD_EndPoint11 USBD_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 12)
+#define USBD_EndPoint12 USBD_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 13)
+#define USBD_EndPoint13 USBD_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 14)
+#define USBD_EndPoint14 USBD_HID_EP_INT_Event
+#elif (USBD_HID_EP_INTIN == 15)
+#define USBD_EndPoint15 USBD_HID_EP_INT_Event
+#endif
+
+#endif /* (USBD_HID_EP_INTIN != USBD_HID_EP_INTOUT) */
+
+#endif /*#ifdef __RTX*/
+#else
+BOOL USBD_ReqGetDescriptor_HID(U8 **pD, U32 *len)
+{
+ return (__FALSE);
+}
+BOOL USBD_EndPoint0_Setup_HID_ReqToIF(void)
+{
+ return (__FALSE);
+}
+BOOL USBD_EndPoint0_Out_HID_ReqToIF(void)
+{
+ return (__FALSE);
+}
+#endif /* (USBD_HID_ENABLE) */
+
+#if (USBD_MSC_ENABLE)
+#ifdef __RTX
+#if (USBD_MSC_EP_BULKIN != USBD_MSC_EP_BULKOUT)
+#if (USBD_MSC_EP_BULKIN == 1)
+#define USBD_RTX_EndPoint1 USBD_RTX_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 2)
+#define USBD_RTX_EndPoint2 USBD_RTX_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 3)
+#define USBD_RTX_EndPoint3 USBD_RTX_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 4)
+#define USBD_RTX_EndPoint4 USBD_RTX_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 5)
+#define USBD_RTX_EndPoint5 USBD_RTX_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 6)
+#define USBD_RTX_EndPoint6 USBD_RTX_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 7)
+#define USBD_RTX_EndPoint7 USBD_RTX_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 8)
+#define USBD_RTX_EndPoint8 USBD_RTX_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 9)
+#define USBD_RTX_EndPoint9 USBD_RTX_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 10)
+#define USBD_RTX_EndPoint10 USBD_RTX_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 11)
+#define USBD_RTX_EndPoint11 USBD_RTX_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 12)
+#define USBD_RTX_EndPoint12 USBD_RTX_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 13)
+#define USBD_RTX_EndPoint13 USBD_RTX_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 14)
+#define USBD_RTX_EndPoint14 USBD_RTX_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 15)
+#define USBD_RTX_EndPoint15 USBD_RTX_MSC_EP_BULKIN_Event
+#endif
+
+#if (USBD_MSC_EP_BULKOUT == 1)
+#define USBD_RTX_EndPoint1 USBD_RTX_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 2)
+#define USBD_RTX_EndPoint2 USBD_RTX_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 3)
+#define USBD_RTX_EndPoint3 USBD_RTX_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 4)
+#define USBD_RTX_EndPoint4 USBD_RTX_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 5)
+#define USBD_RTX_EndPoint5 USBD_RTX_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 6)
+#define USBD_RTX_EndPoint6 USBD_RTX_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 7)
+#define USBD_RTX_EndPoint7 USBD_RTX_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 8)
+#define USBD_RTX_EndPoint8 USBD_RTX_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 9)
+#define USBD_RTX_EndPoint9 USBD_RTX_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 10)
+#define USBD_RTX_EndPoint10 USBD_RTX_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 11)
+#define USBD_RTX_EndPoint11 USBD_RTX_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 12)
+#define USBD_RTX_EndPoint12 USBD_RTX_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 13)
+#define USBD_RTX_EndPoint13 USBD_RTX_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 14)
+#define USBD_RTX_EndPoint14 USBD_RTX_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 15)
+#define USBD_RTX_EndPoint15 USBD_RTX_MSC_EP_BULKOUT_Event
+#endif
+#else
+#if (USBD_MSC_EP_BULKIN == 1)
+#define USBD_RTX_EndPoint1 USBD_RTX_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 2)
+#define USBD_RTX_EndPoint2 USBD_RTX_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 3)
+#define USBD_RTX_EndPoint3 USBD_RTX_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 4)
+#define USBD_RTX_EndPoint4 USBD_RTX_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 5)
+#define USBD_RTX_EndPoint5 USBD_RTX_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 6)
+#define USBD_RTX_EndPoint6 USBD_RTX_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 7)
+#define USBD_RTX_EndPoint7 USBD_RTX_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 8)
+#define USBD_RTX_EndPoint8 USBD_RTX_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 9)
+#define USBD_RTX_EndPoint9 USBD_RTX_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 10)
+#define USBD_RTX_EndPoint10 USBD_RTX_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 11)
+#define USBD_RTX_EndPoint11 USBD_RTX_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 12)
+#define USBD_RTX_EndPoint12 USBD_RTX_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 13)
+#define USBD_RTX_EndPoint13 USBD_RTX_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 14)
+#define USBD_RTX_EndPoint14 USBD_RTX_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 15)
+#define USBD_RTX_EndPoint15 USBD_RTX_MSC_EP_BULK_Event
+#endif
+#endif
+#else
+#if (USBD_MSC_EP_BULKIN != USBD_MSC_EP_BULKOUT)
+#if (USBD_MSC_EP_BULKIN == 1)
+#define USBD_EndPoint1 USBD_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 2)
+#define USBD_EndPoint2 USBD_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 3)
+#define USBD_EndPoint3 USBD_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 4)
+#define USBD_EndPoint4 USBD_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 5)
+#define USBD_EndPoint5 USBD_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 6)
+#define USBD_EndPoint6 USBD_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 7)
+#define USBD_EndPoint7 USBD_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 8)
+#define USBD_EndPoint8 USBD_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 9)
+#define USBD_EndPoint9 USBD_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 10)
+#define USBD_EndPoint10 USBD_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 11)
+#define USBD_EndPoint11 USBD_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 12)
+#define USBD_EndPoint12 USBD_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 13)
+#define USBD_EndPoint13 USBD_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 14)
+#define USBD_EndPoint14 USBD_MSC_EP_BULKIN_Event
+#elif (USBD_MSC_EP_BULKIN == 15)
+#define USBD_EndPoint15 USBD_MSC_EP_BULKIN_Event
+#endif
+
+#if (USBD_MSC_EP_BULKOUT == 1)
+#define USBD_EndPoint1 USBD_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 2)
+#define USBD_EndPoint2 USBD_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 3)
+#define USBD_EndPoint3 USBD_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 4)
+#define USBD_EndPoint4 USBD_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 5)
+#define USBD_EndPoint5 USBD_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 6)
+#define USBD_EndPoint6 USBD_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 7)
+#define USBD_EndPoint7 USBD_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 8)
+#define USBD_EndPoint8 USBD_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 9)
+#define USBD_EndPoint9 USBD_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 10)
+#define USBD_EndPoint10 USBD_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 11)
+#define USBD_EndPoint11 USBD_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 12)
+#define USBD_EndPoint12 USBD_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 13)
+#define USBD_EndPoint13 USBD_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 14)
+#define USBD_EndPoint14 USBD_MSC_EP_BULKOUT_Event
+#elif (USBD_MSC_EP_BULKOUT == 15)
+#define USBD_EndPoint15 USBD_MSC_EP_BULKOUT_Event
+#endif
+#else
+#if (USBD_MSC_EP_BULKIN == 1)
+#define USBD_EndPoint1 USBD_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 2)
+#define USBD_EndPoint2 USBD_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 3)
+#define USBD_EndPoint3 USBD_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 4)
+#define USBD_EndPoint4 USBD_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 5)
+#define USBD_EndPoint5 USBD_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 6)
+#define USBD_EndPoint6 USBD_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 7)
+#define USBD_EndPoint7 USBD_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 8)
+#define USBD_EndPoint8 USBD_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 9)
+#define USBD_EndPoint9 USBD_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 10)
+#define USBD_EndPoint10 USBD_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 11)
+#define USBD_EndPoint11 USBD_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 12)
+#define USBD_EndPoint12 USBD_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 13)
+#define USBD_EndPoint13 USBD_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 14)
+#define USBD_EndPoint14 USBD_MSC_EP_BULK_Event
+#elif (USBD_MSC_EP_BULKIN == 15)
+#define USBD_EndPoint15 USBD_MSC_EP_BULK_Event
+#endif
+#endif
+#endif
+#else
+void USBD_ReqClrFeature_MSC(U32 EPNum)
+{
+
+}
+BOOL USBD_EndPoint0_Setup_MSC_ReqToIF(void)
+{
+ return (__FALSE);
+}
+BOOL USBD_EndPoint0_Out_MSC_ReqToIF(void)
+{
+ return (__FALSE);
+}
+#endif /* (USBD_MSC_ENABLE) */
+
+#if (USBD_ADC_ENABLE == 0)
+BOOL USBD_EndPoint0_Setup_ADC_ReqToIF(void)
+{
+ return (__FALSE);
+}
+BOOL USBD_EndPoint0_Setup_ADC_ReqToEP(void)
+{
+ return (__FALSE);
+}
+BOOL USBD_EndPoint0_Out_ADC_ReqToIF(void)
+{
+ return (__FALSE);
+}
+BOOL USBD_EndPoint0_Out_ADC_ReqToEP(void)
+{
+ return (__FALSE);
+}
+#endif /* (USBD_ADC_ENABLE) */
+
+#if (USBD_CDC_ACM_ENABLE)
+#ifdef __RTX
+#if (USBD_CDC_ACM_EP_INTIN == 1)
+#define USBD_RTX_EndPoint1 USBD_RTX_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 2)
+#define USBD_RTX_EndPoint2 USBD_RTX_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 3)
+#define USBD_RTX_EndPoint3 USBD_RTX_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 4)
+#define USBD_RTX_EndPoint4 USBD_RTX_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 5)
+#define USBD_RTX_EndPoint5 USBD_RTX_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 6)
+#define USBD_RTX_EndPoint6 USBD_RTX_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 7)
+#define USBD_RTX_EndPoint7 USBD_RTX_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 8)
+#define USBD_RTX_EndPoint8 USBD_RTX_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 9)
+#define USBD_RTX_EndPoint9 USBD_RTX_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 10)
+#define USBD_RTX_EndPoint10 USBD_RTX_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 11)
+#define USBD_RTX_EndPoint11 USBD_RTX_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 12)
+#define USBD_RTX_EndPoint12 USBD_RTX_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 13)
+#define USBD_RTX_EndPoint13 USBD_RTX_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 14)
+#define USBD_RTX_EndPoint14 USBD_RTX_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 15)
+#define USBD_RTX_EndPoint15 USBD_RTX_CDC_ACM_EP_INTIN_Event
+#endif
+#else
+#if (USBD_CDC_ACM_EP_INTIN == 1)
+#define USBD_EndPoint1 USBD_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 2)
+#define USBD_EndPoint2 USBD_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 3)
+#define USBD_EndPoint3 USBD_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 4)
+#define USBD_EndPoint4 USBD_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 5)
+#define USBD_EndPoint5 USBD_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 6)
+#define USBD_EndPoint6 USBD_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 7)
+#define USBD_EndPoint7 USBD_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 8)
+#define USBD_EndPoint8 USBD_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 9)
+#define USBD_EndPoint9 USBD_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 10)
+#define USBD_EndPoint10 USBD_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 11)
+#define USBD_EndPoint11 USBD_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 12)
+#define USBD_EndPoint12 USBD_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 13)
+#define USBD_EndPoint13 USBD_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 14)
+#define USBD_EndPoint14 USBD_CDC_ACM_EP_INTIN_Event
+#elif (USBD_CDC_ACM_EP_INTIN == 15)
+#define USBD_EndPoint15 USBD_CDC_ACM_EP_INTIN_Event
+#endif
+#endif
+
+#ifdef __RTX
+#if (USBD_CDC_ACM_EP_BULKIN != USBD_CDC_ACM_EP_BULKOUT)
+#if (USBD_CDC_ACM_EP_BULKIN == 1)
+#define USBD_RTX_EndPoint1 USBD_RTX_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 2)
+#define USBD_RTX_EndPoint2 USBD_RTX_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 3)
+#define USBD_RTX_EndPoint3 USBD_RTX_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 4)
+#define USBD_RTX_EndPoint4 USBD_RTX_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 5)
+#define USBD_RTX_EndPoint5 USBD_RTX_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 6)
+#define USBD_RTX_EndPoint6 USBD_RTX_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 7)
+#define USBD_RTX_EndPoint7 USBD_RTX_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 8)
+#define USBD_RTX_EndPoint8 USBD_RTX_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 9)
+#define USBD_RTX_EndPoint9 USBD_RTX_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 10)
+#define USBD_RTX_EndPoint10 USBD_RTX_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 11)
+#define USBD_RTX_EndPoint11 USBD_RTX_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 12)
+#define USBD_RTX_EndPoint12 USBD_RTX_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 13)
+#define USBD_RTX_EndPoint13 USBD_RTX_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 14)
+#define USBD_RTX_EndPoint14 USBD_RTX_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 15)
+#define USBD_RTX_EndPoint15 USBD_RTX_CDC_ACM_EP_BULKIN_Event
+#endif
+
+#if (USBD_CDC_ACM_EP_BULKOUT == 1)
+#define USBD_RTX_EndPoint1 USBD_RTX_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 2)
+#define USBD_RTX_EndPoint2 USBD_RTX_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 3)
+#define USBD_RTX_EndPoint3 USBD_RTX_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 4)
+#define USBD_RTX_EndPoint4 USBD_RTX_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 5)
+#define USBD_RTX_EndPoint5 USBD_RTX_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 6)
+#define USBD_RTX_EndPoint6 USBD_RTX_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 7)
+#define USBD_RTX_EndPoint7 USBD_RTX_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 8)
+#define USBD_RTX_EndPoint8 USBD_RTX_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 9)
+#define USBD_RTX_EndPoint9 USBD_RTX_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 10)
+#define USBD_RTX_EndPoint10 USBD_RTX_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 11)
+#define USBD_RTX_EndPoint11 USBD_RTX_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 12)
+#define USBD_RTX_EndPoint12 USBD_RTX_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 13)
+#define USBD_RTX_EndPoint13 USBD_RTX_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 14)
+#define USBD_RTX_EndPoint14 USBD_RTX_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 15)
+#define USBD_RTX_EndPoint15 USBD_RTX_CDC_ACM_EP_BULKOUT_Event
+#endif
+#else
+#if (USBD_CDC_ACM_EP_BULKIN == 1)
+#define USBD_RTX_EndPoint1 USBD_RTX_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 2)
+#define USBD_RTX_EndPoint2 USBD_RTX_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 3)
+#define USBD_RTX_EndPoint3 USBD_RTX_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 4)
+#define USBD_RTX_EndPoint4 USBD_RTX_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 5)
+#define USBD_RTX_EndPoint5 USBD_RTX_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 6)
+#define USBD_RTX_EndPoint6 USBD_RTX_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 7)
+#define USBD_RTX_EndPoint7 USBD_RTX_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 8)
+#define USBD_RTX_EndPoint8 USBD_RTX_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 9)
+#define USBD_RTX_EndPoint9 USBD_RTX_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 10)
+#define USBD_RTX_EndPoint10 USBD_RTX_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 11)
+#define USBD_RTX_EndPoint11 USBD_RTX_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 12)
+#define USBD_RTX_EndPoint12 USBD_RTX_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 13)
+#define USBD_RTX_EndPoint13 USBD_RTX_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 14)
+#define USBD_RTX_EndPoint14 USBD_RTX_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 15)
+#define USBD_RTX_EndPoint15 USBD_RTX_CDC_ACM_EP_BULK_Event
+#endif
+#endif
+#else
+#if (USBD_CDC_ACM_EP_BULKIN != USBD_CDC_ACM_EP_BULKOUT)
+#if (USBD_CDC_ACM_EP_BULKIN == 1)
+#define USBD_EndPoint1 USBD_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 2)
+#define USBD_EndPoint2 USBD_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 3)
+#define USBD_EndPoint3 USBD_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 4)
+#define USBD_EndPoint4 USBD_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 5)
+#define USBD_EndPoint5 USBD_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 6)
+#define USBD_EndPoint6 USBD_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 7)
+#define USBD_EndPoint7 USBD_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 8)
+#define USBD_EndPoint8 USBD_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 9)
+#define USBD_EndPoint9 USBD_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 10)
+#define USBD_EndPoint10 USBD_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 11)
+#define USBD_EndPoint11 USBD_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 12)
+#define USBD_EndPoint12 USBD_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 13)
+#define USBD_EndPoint13 USBD_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 14)
+#define USBD_EndPoint14 USBD_CDC_ACM_EP_BULKIN_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 15)
+#define USBD_EndPoint15 USBD_CDC_ACM_EP_BULKIN_Event
+#endif
+
+#if (USBD_CDC_ACM_EP_BULKOUT == 1)
+#define USBD_EndPoint1 USBD_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 2)
+#define USBD_EndPoint2 USBD_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 3)
+#define USBD_EndPoint3 USBD_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 4)
+#define USBD_EndPoint4 USBD_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 5)
+#define USBD_EndPoint5 USBD_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 6)
+#define USBD_EndPoint6 USBD_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 7)
+#define USBD_EndPoint7 USBD_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 8)
+#define USBD_EndPoint8 USBD_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 9)
+#define USBD_EndPoint9 USBD_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 10)
+#define USBD_EndPoint10 USBD_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 11)
+#define USBD_EndPoint11 USBD_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 12)
+#define USBD_EndPoint12 USBD_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 13)
+#define USBD_EndPoint13 USBD_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 14)
+#define USBD_EndPoint14 USBD_CDC_ACM_EP_BULKOUT_Event
+#elif (USBD_CDC_ACM_EP_BULKOUT == 15)
+#define USBD_EndPoint15 USBD_CDC_ACM_EP_BULKOUT_Event
+#endif
+#else
+#if (USBD_CDC_ACM_EP_BULKIN == 1)
+#define USBD_EndPoint1 USBD_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 2)
+#define USBD_EndPoint2 USBD_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 3)
+#define USBD_EndPoint3 USBD_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 4)
+#define USBD_EndPoint4 USBD_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 5)
+#define USBD_EndPoint5 USBD_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 6)
+#define USBD_EndPoint6 USBD_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 7)
+#define USBD_EndPoint7 USBD_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 8)
+#define USBD_EndPoint8 USBD_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 9)
+#define USBD_EndPoint9 USBD_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 10)
+#define USBD_EndPoint10 USBD_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 11)
+#define USBD_EndPoint11 USBD_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 12)
+#define USBD_EndPoint12 USBD_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 13)
+#define USBD_EndPoint13 USBD_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 14)
+#define USBD_EndPoint14 USBD_CDC_ACM_EP_BULK_Event
+#elif (USBD_CDC_ACM_EP_BULKIN == 15)
+#define USBD_EndPoint15 USBD_CDC_ACM_EP_BULK_Event
+#endif
+#endif
+#endif
+#else
+BOOL USBD_EndPoint0_Setup_CDC_ReqToIF(void)
+{
+ return (__FALSE);
+}
+BOOL USBD_EndPoint0_Out_CDC_ReqToIF(void)
+{
+ return (__FALSE);
+}
+#endif /* (USBD_CDC_ACM_ENABLE) */
+
+#if (USBD_BULK_ENABLE)
+
+#if (USBD_BULK_EP_BULKIN != USBD_BULK_EP_BULKOUT)
+
+#if (USBD_BULK_EP_BULKIN == 1)
+#define USBD_EndPoint1 USBD_BULK_EP_BULKIN_Event
+#elif (USBD_BULK_EP_BULKIN == 2)
+#define USBD_EndPoint2 USBD_BULK_EP_BULKIN_Event
+#elif (USBD_BULK_EP_BULKIN == 3)
+#define USBD_EndPoint3 USBD_BULK_EP_BULKIN_Event
+#elif (USBD_BULK_EP_BULKIN == 4)
+#define USBD_EndPoint4 USBD_BULK_EP_BULKIN_Event
+#elif (USBD_BULK_EP_BULKIN == 5)
+#define USBD_EndPoint5 USBD_BULK_EP_BULKIN_Event
+#elif (USBD_BULK_EP_BULKIN == 6)
+#define USBD_EndPoint6 USBD_BULK_EP_BULKIN_Event
+#elif (USBD_BULK_EP_BULKIN == 7)
+#define USBD_EndPoint7 USBD_BULK_EP_BULKIN_Event
+#elif (USBD_BULK_EP_BULKIN == 8)
+#define USBD_EndPoint8 USBD_BULK_EP_BULKIN_Event
+#elif (USBD_BULK_EP_BULKIN == 9)
+#define USBD_EndPoint9 USBD_BULK_EP_BULKIN_Event
+#elif (USBD_BULK_EP_BULKIN == 10)
+#define USBD_EndPoint10 USBD_BULK_EP_BULKIN_Event
+#elif (USBD_BULK_EP_BULKIN == 11)
+#define USBD_EndPoint11 USBD_BULK_EP_BULKIN_Event
+#elif (USBD_BULK_EP_BULKIN == 12)
+#define USBD_EndPoint12 USBD_BULK_EP_BULKIN_Event
+#elif (USBD_BULK_EP_BULKIN == 13)
+#define USBD_EndPoint13 USBD_BULK_EP_BULKIN_Event
+#elif (USBD_BULK_EP_BULKIN == 14)
+#define USBD_EndPoint14 USBD_BULK_EP_BULKIN_Event
+#elif (USBD_BULK_EP_BULKIN == 15)
+#define USBD_EndPoint15 USBD_BULK_EP_BULKIN_Event
+#endif
+
+#if (USBD_BULK_EP_BULKOUT == 1)
+#define USBD_EndPoint1 USBD_BULK_EP_BULKOUT_Event
+#elif (USBD_BULK_EP_BULKOUT == 2)
+#define USBD_EndPoint2 USBD_BULK_EP_BULKOUT_Event
+#elif (USBD_BULK_EP_BULKOUT == 3)
+#define USBD_EndPoint3 USBD_BULK_EP_BULKOUT_Event
+#elif (USBD_BULK_EP_BULKOUT == 4)
+#define USBD_EndPoint4 USBD_BULK_EP_BULKOUT_Event
+#elif (USBD_BULK_EP_BULKOUT == 5)
+#define USBD_EndPoint5 USBD_BULK_EP_BULKOUT_Event
+#elif (USBD_BULK_EP_BULKOUT == 6)
+#define USBD_EndPoint6 USBD_BULK_EP_BULKOUT_Event
+#elif (USBD_BULK_EP_BULKOUT == 7)
+#define USBD_EndPoint7 USBD_BULK_EP_BULKOUT_Event
+#elif (USBD_BULK_EP_BULKOUT == 8)
+#define USBD_EndPoint8 USBD_BULK_EP_BULKOUT_Event
+#elif (USBD_BULK_EP_BULKOUT == 9)
+#define USBD_EndPoint9 USBD_BULK_EP_BULKOUT_Event
+#elif (USBD_BULK_EP_BULKOUT == 10)
+#define USBD_EndPoint10 USBD_BULK_EP_BULKOUT_Event
+#elif (USBD_BULK_EP_BULKOUT == 11)
+#define USBD_EndPoint11 USBD_BULK_EP_BULKOUT_Event
+#elif (USBD_BULK_EP_BULKOUT == 12)
+#define USBD_EndPoint12 USBD_BULK_EP_BULKOUT_Event
+#elif (USBD_BULK_EP_BULKOUT == 13)
+#define USBD_EndPoint13 USBD_BULK_EP_BULKOUT_Event
+#elif (USBD_BULK_EP_BULKOUT == 14)
+#define USBD_EndPoint14 USBD_BULK_EP_BULKOUT_Event
+#elif (USBD_BULK_EP_BULKOUT == 15)
+#define USBD_EndPoint15 USBD_BULK_EP_BULKOUT_Event
+#endif
+
+#else
+#if (USBD_BULK_EP_BULKIN == 1)
+#define USBD_EndPoint1 USBD_BULK_EP_BULK_Event
+#elif (USBD_BULK_EP_BULKIN == 2)
+#define USBD_EndPoint2 USBD_BULK_EP_BULK_Event
+#elif (USBD_BULK_EP_BULKIN == 3)
+#define USBD_EndPoint3 USBD_BULK_EP_BULK_Event
+#elif (USBD_BULK_EP_BULKIN == 4)
+#define USBD_EndPoint4 USBD_BULK_EP_BULK_Event
+#elif (USBD_BULK_EP_BULKIN == 5)
+#define USBD_EndPoint5 USBD_BULK_EP_BULK_Event
+#elif (USBD_BULK_EP_BULKIN == 6)
+#define USBD_EndPoint6 USBD_BULK_EP_BULK_Event
+#elif (USBD_BULK_EP_BULKIN == 7)
+#define USBD_EndPoint7 USBD_BULK_EP_BULK_Event
+#elif (USBD_BULK_EP_BULKIN == 8)
+#define USBD_EndPoint8 USBD_BULK_EP_BULK_Event
+#elif (USBD_BULK_EP_BULKIN == 9)
+#define USBD_EndPoint9 USBD_BULK_EP_BULK_Event
+#elif (USBD_BULK_EP_BULKIN == 10)
+#define USBD_EndPoint10 USBD_BULK_EP_BULK_Event
+#elif (USBD_BULK_EP_BULKIN == 11)
+#define USBD_EndPoint11 USBD_BULK_EP_BULK_Event
+#elif (USBD_BULK_EP_BULKIN == 12)
+#define USBD_EndPoint12 USBD_BULK_EP_BULK_Event
+#elif (USBD_BULK_EP_BULKIN == 13)
+#define USBD_EndPoint13 USBD_BULK_EP_BULK_Event
+#elif (USBD_BULK_EP_BULKIN == 14)
+#define USBD_EndPoint14 USBD_BULK_EP_BULK_Event
+#elif (USBD_BULK_EP_BULKIN == 15)
+#define USBD_EndPoint15 USBD_BULK_EP_BULK_Event
+#endif
+#endif
+
+#endif /* (USBD_BULK_ENABLE) */
+
+#if (USBD_CLS_ENABLE)
+#else
+BOOL USBD_EndPoint0_Setup_CLS_ReqToDEV(void)
+{
+ return (__FALSE);
+}
+BOOL USBD_EndPoint0_Setup_CLS_ReqToIF(void)
+{
+ return (__FALSE);
+}
+BOOL USBD_EndPoint0_Setup_CLS_ReqToEP(void)
+{
+ return (__FALSE);
+}
+BOOL USBD_EndPoint0_Out_CLS_ReqToDEV(void)
+{
+ return (__FALSE);
+}
+BOOL USBD_EndPoint0_Out_CLS_ReqToIF(void)
+{
+ return (__FALSE);
+}
+BOOL USBD_EndPoint0_Out_CLS_ReqToEP(void)
+{
+ return (__FALSE);
+}
+#endif /* (USBD_CLS_ENABLE) */
+
+#if ((USBD_CDC_ACM_ENABLE))
+#ifndef __RTX
+void USBD_Reset_Event(void)
+{
+#if (USBD_CDC_ACM_ENABLE)
+ USBD_CDC_ACM_Reset_Event();
+#endif
+#if (USBD_MSC_ENABLE)
+ USBD_MSC_Reset_Event();
+#endif
+}
+#endif
+#endif /* ((USBD_CDC_ACM_ENABLE)) */
+
+#if ((USBD_HID_ENABLE) || (USBD_ADC_ENABLE) || (USBD_CDC_ACM_ENABLE) || (USBD_CLS_ENABLE))
+#ifndef __RTX
+void USBD_SOF_Event(void)
+{
+#if (USBD_HID_ENABLE)
+ USBD_HID_SOF_Event();
+#endif
+#if (USBD_ADC_ENABLE)
+ USBD_ADC_SOF_Event();
+#endif
+#if (USBD_CDC_ACM_ENABLE)
+ USBD_CDC_ACM_SOF_Event();
+#endif
+#if (USBD_CLS_ENABLE)
+ USBD_CLS_SOF_Event();
+#endif
+}
+#endif
+#endif /* ((USBD_HID_ENABLE) || (USBD_ADC_ENABLE) || (USBD_CDC_ACM_ENABLE) || (USBD_CLS_ENABLE)) */
+
+/* USB Device - Device Events Callback Functions */
+__weak void USBD_Power_Event(BOOL power);
+__weak void USBD_Reset_Event(void);
+__weak void USBD_Suspend_Event(void);
+__weak void USBD_Resume_Event(void);
+__weak void USBD_WakeUp_Event(void);
+__weak void USBD_SOF_Event(void);
+__weak void USBD_Error_Event(U32 error);
+
+/* USB Device - Device Events Callback Pointers */
+void (* const USBD_P_Power_Event)(BOOL power) = USBD_Power_Event;
+void (* const USBD_P_Reset_Event)(void) = USBD_Reset_Event;
+void (* const USBD_P_Suspend_Event)(void) = USBD_Suspend_Event;
+void (* const USBD_P_Resume_Event)(void) = USBD_Resume_Event;
+void (* const USBD_P_WakeUp_Event)(void) = USBD_WakeUp_Event;
+void (* const USBD_P_SOF_Event)(void) = USBD_SOF_Event;
+void (* const USBD_P_Error_Event)(U32 error) = USBD_Error_Event;
+
+/* USB Device - Endpoint Events Callback Functions */
+extern void USBD_EndPoint0(U32 event);
+#ifndef USBD_EndPoint1
+__weak void USBD_EndPoint1(U32 event);
+#endif
+#ifndef USBD_EndPoint2
+__weak void USBD_EndPoint2(U32 event);
+#endif
+#ifndef USBD_EndPoint3
+__weak void USBD_EndPoint3(U32 event);
+#endif
+#ifndef USBD_EndPoint4
+__weak void USBD_EndPoint4(U32 event);
+#endif
+#ifndef USBD_EndPoint5
+__weak void USBD_EndPoint5(U32 event);
+#endif
+#ifndef USBD_EndPoint6
+__weak void USBD_EndPoint6(U32 event);
+#endif
+#ifndef USBD_EndPoint7
+__weak void USBD_EndPoint7(U32 event);
+#endif
+#ifndef USBD_EndPoint8
+__weak void USBD_EndPoint8(U32 event);
+#endif
+#ifndef USBD_EndPoint9
+__weak void USBD_EndPoint9(U32 event);
+#endif
+#ifndef USBD_EndPoint10
+__weak void USBD_EndPoint10(U32 event);
+#endif
+#ifndef USBD_EndPoint11
+__weak void USBD_EndPoint11(U32 event);
+#endif
+#ifndef USBD_EndPoint12
+__weak void USBD_EndPoint12(U32 event);
+#endif
+#ifndef USBD_EndPoint13
+__weak void USBD_EndPoint13(U32 event);
+#endif
+#ifndef USBD_EndPoint14
+__weak void USBD_EndPoint14(U32 event);
+#endif
+#ifndef USBD_EndPoint15
+__weak void USBD_EndPoint15(U32 event);
+#endif
+
+/* USB Device - Endpoint Events Callback Pointers */
+void (* const USBD_P_EP[16])(U32 event) = {
+ USBD_EndPoint0,
+ USBD_EndPoint1,
+ USBD_EndPoint2,
+ USBD_EndPoint3,
+ USBD_EndPoint4,
+ USBD_EndPoint5,
+ USBD_EndPoint6,
+ USBD_EndPoint7,
+ USBD_EndPoint8,
+ USBD_EndPoint9,
+ USBD_EndPoint10,
+ USBD_EndPoint11,
+ USBD_EndPoint12,
+ USBD_EndPoint13,
+ USBD_EndPoint14,
+ USBD_EndPoint15
+};
+
+/* USB Device - Core Events Callback Functions */
+__weak void USBD_Configure_Event(void);
+__weak void USBD_Interface_Event(void);
+__weak void USBD_Feature_Event(void);
+
+/* USB Device - Core Events Callback Pointers */
+void (* const USBD_P_Configure_Event)(void) = USBD_Configure_Event;
+void (* const USBD_P_Interface_Event)(void) = USBD_Interface_Event;
+void (* const USBD_P_Feature_Event)(void) = USBD_Feature_Event;
+
+#ifdef __RTX
+const BOOL __rtx = __TRUE;
+
+#if ((USBD_HID_ENABLE) || (USBD_ADC_ENABLE) || (USBD_CDC_ACM_ENABLE) || (USBD_CLS_ENABLE))
+__weak void USBD_RTX_Device(void)
+{
+ U16 evt;
+
+ for (;;) {
+ os_evt_wait_or(0xFFFF, 0xFFFF); /* Wait for an Event */
+ evt = os_evt_get(); /* Get Event Flags */
+
+ if (evt & USBD_EVT_RESET) {
+#if (USBD_CDC_ACM_ENABLE)
+ USBD_CDC_ACM_Reset_Event();
+#endif
+#if (USBD_MSC_ENABLE)
+ USBD_MSC_Reset_Event();
+#endif
+ }
+
+ if (evt & USBD_EVT_SOF) {
+#if (USBD_HID_ENABLE)
+ USBD_HID_SOF_Event();
+#endif
+#if (USBD_ADC_ENABLE)
+ USBD_ADC_SOF_Event();
+#endif
+#if (USBD_CDC_ACM_ENABLE)
+ USBD_CDC_ACM_SOF_Event();
+#endif
+#if (USBD_CLS_ENABLE)
+ USBD_CLS_SOF_Event();
+#endif
+ }
+ }
+}
+#else
+__weak void USBD_RTX_Device(void);
+#endif
+
+/* USB Device - Device Events Callback Pointer */
+void (* const USBD_RTX_P_Device)(void) = USBD_RTX_Device;
+
+/* USB Device Endpoint Events Callback Functions */
+extern void USBD_RTX_EndPoint0(void);
+#ifndef USBD_RTX_EndPoint1
+__weak void USBD_RTX_EndPoint1(void);
+#endif
+#ifndef USBD_RTX_EndPoint2
+__weak void USBD_RTX_EndPoint2(void);
+#endif
+#ifndef USBD_RTX_EndPoint3
+__weak void USBD_RTX_EndPoint3(void);
+#endif
+#ifndef USBD_RTX_EndPoint4
+__weak void USBD_RTX_EndPoint4(void);
+#endif
+#ifndef USBD_RTX_EndPoint5
+__weak void USBD_RTX_EndPoint5(void);
+#endif
+#ifndef USBD_RTX_EndPoint6
+__weak void USBD_RTX_EndPoint6(void);
+#endif
+#ifndef USBD_RTX_EndPoint7
+__weak void USBD_RTX_EndPoint7(void);
+#endif
+#ifndef USBD_RTX_EndPoint8
+__weak void USBD_RTX_EndPoint8(void);
+#endif
+#ifndef USBD_RTX_EndPoint9
+__weak void USBD_RTX_EndPoint9(void);
+#endif
+#ifndef USBD_RTX_EndPoint10
+__weak void USBD_RTX_EndPoint10(void);
+#endif
+#ifndef USBD_RTX_EndPoint11
+__weak void USBD_RTX_EndPoint11(void);
+#endif
+#ifndef USBD_RTX_EndPoint12
+__weak void USBD_RTX_EndPoint12(void);
+#endif
+#ifndef USBD_RTX_EndPoint13
+__weak void USBD_RTX_EndPoint13(void);
+#endif
+#ifndef USBD_RTX_EndPoint14
+__weak void USBD_RTX_EndPoint14(void);
+#endif
+#ifndef USBD_RTX_EndPoint15
+__weak void USBD_RTX_EndPoint15(void);
+#endif
+
+#if (USBD_HID_ENABLE)
+__weak void USBD_RTX_Core(void)
+{
+ U16 evt;
+
+ for (;;) {
+ os_evt_wait_or(0xFFFF, 0xFFFF); /* Wait for an Event */
+ evt = os_evt_get(); /* Get Event Flags */
+
+ if (evt & USBD_EVT_SET_CFG) {
+ USBD_HID_Configure_Event();
+ }
+ }
+}
+#else
+__weak void USBD_RTX_Core(void);
+#endif
+
+/* USB Device - Core Events Callback Pointer */
+void (* const USBD_RTX_P_Core)(void) = USBD_RTX_Core;
+
+/* USB Device Endpoint Events Callback Pointers */
+void (* const USBD_RTX_P_EP[16])(void) = {
+ USBD_RTX_EndPoint0,
+ USBD_RTX_EndPoint1,
+ USBD_RTX_EndPoint2,
+ USBD_RTX_EndPoint3,
+ USBD_RTX_EndPoint4,
+ USBD_RTX_EndPoint5,
+ USBD_RTX_EndPoint6,
+ USBD_RTX_EndPoint7,
+ USBD_RTX_EndPoint8,
+ USBD_RTX_EndPoint9,
+ USBD_RTX_EndPoint10,
+ USBD_RTX_EndPoint11,
+ USBD_RTX_EndPoint12,
+ USBD_RTX_EndPoint13,
+ USBD_RTX_EndPoint14,
+ USBD_RTX_EndPoint15,
+};
+
+void usbd_os_evt_set(U16 event_flags, U32 task)
+{
+ if (task) {
+ os_evt_set(event_flags, task);
+ }
+}
+U16 usbd_os_evt_get(void)
+{
+ return (os_evt_get());
+}
+U32 usbd_os_evt_wait_or(U16 wait_flags, U16 timeout)
+{
+ return (os_evt_wait_or(wait_flags, timeout));
+}
+
+#else
+const BOOL __rtx = __FALSE;
+
+void usbd_os_evt_set(U16 event_flags, U32 task)
+{
+
+}
+U16 usbd_os_evt_get(void)
+{
+ return (0);
+}
+U32 usbd_os_evt_wait_or(U16 wait_flags, U16 timeout)
+{
+ return (0);
+}
+#endif
+
+#ifdef __RTX
+
+typedef struct {
+ void *stack;
+ U16 size;
+} user_stack_t;
+
+#if USBD_ENABLE && !defined(USBD_RTX_CORE_STACK)
+#error "USB core stack must be defined"
+#endif
+#if USBD_ENABLE && !defined(USBD_RTX_DEVICE_STACK)
+#error "USB device stack must be defined"
+#endif
+#if USBD_ENABLE && !defined(USBD_RTX_ENDPOINT0_STACK)
+#error "USB endpoint 0 must be defined"
+#endif
+
+#if !defined(USBD_HID_EP_INTIN_STACK)
+#define USBD_HID_EP_INTIN_STACK 0
+#endif
+#if !defined(USBD_HID_EP_INTOUT_STACK)
+#define USBD_HID_EP_INTOUT_STACK 0
+#endif
+#if !defined(USBD_MSC_EP_BULKIN_STACK)
+#define USBD_MSC_EP_BULKIN_STACK 0
+#endif
+#if !defined(USBD_MSC_EP_BULKOUT_STACK)
+#define USBD_MSC_EP_BULKOUT_STACK 0
+#endif
+#if !defined(USBD_ADC_EP_ISOOUT_STACK)
+#define USBD_ADC_EP_ISOOUT_STACK 0
+#endif
+#if !defined(USBD_CDC_ACM_EP_INTIN_STACK)
+#define USBD_CDC_ACM_EP_INTIN_STACK 0
+#endif
+#if !defined(USBD_CDC_ACM_EP_BULKIN_STACK)
+#define USBD_CDC_ACM_EP_BULKIN_STACK 0
+#endif
+#if !defined(USBD_CDC_ACM_EP_BULKOUT_STACK)
+#define USBD_CDC_ACM_EP_BULKOUT_STACK 0
+#endif
+
+#if USBD_HID_EP_INTIN == 0 && USBD_HID_EP_INTIN_STACK > 0
+#error "USBD_HID_EP_INTIN stack unused - must be 0"
+#endif
+#if USBD_HID_EP_INTOUT == 0 && USBD_HID_EP_INTOUT_STACK > 0
+#error "USBD_HID_EP_INTOUT stack unused - must be 0"
+#endif
+#if USBD_MSC_EP_BULKIN == 0 && USBD_MSC_EP_BULKIN_STACK > 0
+#error "USBD_MSC_EP_BULKIN stack unused - must be 0"
+#endif
+#if USBD_MSC_EP_BULKOUT == 0 && USBD_MSC_EP_BULKOUT_STACK > 0
+#error "USBD_MSC_EP_BULKOUT stack unused - must be 0"
+#endif
+#if USBD_ADC_EP_ISOOUT == 0 && USBD_ADC_EP_ISOOUT_STACK > 0
+#error "USBD_ADC_EP_ISOOUT stack unused - must be 0"
+#endif
+#if USBD_CDC_ACM_EP_INTIN == 0 && USBD_CDC_ACM_EP_INTIN_STACK > 0
+#error "USBD_CDC_ACM_EP_INTIN stack unused - must be 0"
+#endif
+#if USBD_CDC_ACM_EP_BULKIN == 0 && USBD_CDC_ACM_EP_BULKIN_STACK > 0
+#error "USBD_CDC_ACM_EP_BULKIN stack unused - must be 0"
+#endif
+#if USBD_CDC_ACM_EP_BULKOUT == 0 && USBD_CDC_ACM_EP_BULKOUT_STACK > 0
+#error "USBD_CDC_ACM_EP_BULKOUT stack unused - must be 0"
+#endif
+
+#if USBD_ENABLE
+static U64 usbd_core_stack[USBD_RTX_CORE_STACK / 8];
+static U64 usbd_device_stack[USBD_RTX_DEVICE_STACK / 8];
+static U64 usbd_endpoint0_stack[USBD_RTX_ENDPOINT0_STACK / 8];
+#endif
+
+#if (USBD_HID_EP_INTIN_STACK > 0)
+static U64 usbd_hid_ep_intin_stack[USBD_HID_EP_INTIN_STACK / 8];
+#endif
+#if (USBD_HID_EP_INTOUT_STACK > 0)
+static U64 usbd_hid_ep_intout_stack[USBD_HID_EP_INTOUT_STACK / 8];
+#endif
+#if (USBD_MSC_EP_BULKIN_STACK > 0)
+static U64 usbd_msc_ep_bulkin_stack[USBD_MSC_EP_BULKIN_STACK / 8];
+#endif
+#if (USBD_MSC_EP_BULKOUT_STACK > 0)
+static U64 usbd_msc_ep_bulkout_stack[USBD_MSC_EP_BULKOUT_STACK / 8];
+#endif
+#if (USBD_ADC_EP_ISOOUT_STACK > 0)
+static U64 usbd_adc_ep_isoout_stack[USBD_ADC_EP_ISOOUT_STACK / 8];
+#endif
+#if (USBD_CDC_ACM_EP_INTIN_STACK > 0)
+static U64 usbd_cdc_acm_ep_intin_stack[USBD_CDC_ACM_EP_INTIN_STACK / 8];
+#endif
+#if (USBD_CDC_ACM_EP_BULKIN_STACK > 0)
+static U64 usbd_cdc_acm_ep_bulkin_stack[USBD_CDC_ACM_EP_BULKIN_STACK / 8];
+#endif
+#if (USBD_CDC_ACM_EP_BULKOUT_STACK > 0)
+static U64 usbd_cdc_acm_ep_bulkout_stack[USBD_CDC_ACM_EP_BULKOUT_STACK / 8];
+#endif
+
+// Check HID
+#if (USBD_HID_ENABLE && !USBD_HID_EP_INTIN_STACK && USBD_HID_EP_INTIN != USBD_HID_EP_INTOUT)
+#error "USBD_HID_EP_INTIN_STACK must be defined"
+#endif
+#if (USBD_HID_ENABLE && !USBD_HID_EP_INTOUT_STACK && USBD_HID_EP_INTIN != USBD_HID_EP_INTOUT && USBD_HID_EP_INTOUT != 0)
+#error "USBD_HID_EP_INTOUT_STACK must be defined"
+#endif
+#if (USBD_HID_ENABLE && USBD_HID_EP_INTIN_STACK == 0 && USBD_HID_EP_INTOUT_STACK == 0)
+#error "HID stack must be defined"
+#endif
+#if (USBD_HID_EP_INTIN_STACK > 0 && USBD_HID_EP_INTOUT_STACK > 0 && USBD_HID_EP_INTIN == USBD_HID_EP_INTOUT)
+#error "Multiple HID stacks defined for same EP"
+#endif
+
+// Check MSC
+#if (USBD_MSC_ENABLE && !USBD_MSC_EP_BULKIN_STACK && USBD_MSC_EP_BULKIN != USBD_MSC_EP_BULKOUT)
+#error "USBD_MSC_EP_BULKIN_STACK must be defined"
+#endif
+#if (USBD_MSC_ENABLE && !USBD_MSC_EP_BULKOUT_STACK && USBD_MSC_EP_BULKIN != USBD_MSC_EP_BULKOUT)
+#error "USBD_MSC_EP_BULKIN_STACK must be defined"
+#endif
+#if (USBD_MSC_ENABLE && USBD_MSC_EP_BULKIN_STACK == 0 && USBD_MSC_EP_BULKOUT_STACK == 0)
+#error "MSC stack must be defined"
+#endif
+#if (USBD_MSC_EP_BULKIN_STACK > 0 && USBD_MSC_EP_BULKOUT_STACK > 0 && USBD_MSC_EP_BULKIN == USBD_MSC_EP_BULKOUT)
+#error "Multiple MSC stacks defined for same EP"
+#endif
+
+// Check ADC
+#if (USBD_ADC_ENABLE && !USBD_ADC_EP_ISOOUT_STACK)
+#error "ADC stack must be defined"
+#endif
+
+// Check CDC
+#if (USBD_CDC_ACM_ENABLE && !USBD_CDC_ACM_EP_INTIN_STACK)
+#error "CDC ACM INTIN stack must be defined"
+#endif
+#if (USBD_CDC_ACM_ENABLE && !USBD_CDC_ACM_EP_BULKIN_STACK && USBD_CDC_ACM_EP_BULKIN != USBD_CDC_ACM_EP_BULKOUT)
+#error "USBD_CDC_ACM_EP_BULKIN must be defined"
+#endif
+#if (USBD_CDC_ACM_ENABLE && !USBD_CDC_ACM_EP_BULKOUT_STACK && USBD_CDC_ACM_EP_BULKIN != USBD_CDC_ACM_EP_BULKOUT)
+#error "USBD_CDC_ACM_EP_BULKOUT must be defined"
+#endif
+#if (USBD_CDC_ACM_ENABLE && USBD_CDC_ACM_EP_BULKIN_STACK == 0 && USBD_CDC_ACM_EP_BULKOUT_STACK == 0)
+#error "CDC BULK stack must be defined"
+#endif
+#if (USBD_CDC_ACM_EP_BULKIN_STACK > 0 && USBD_CDC_ACM_EP_BULKOUT_STACK > 0 && USBD_CDC_ACM_EP_BULKIN == USBD_CDC_ACM_EP_BULKOUT)
+#error "Multiple CDC stacks defined for same EP"
+#endif
+
+static const user_stack_t user_stack_list[16] = {
+#if USBD_ENABLE
+ [0] = {usbd_endpoint0_stack, sizeof(usbd_endpoint0_stack)},
+#endif
+#if (USBD_HID_EP_INTIN_STACK > 0)
+ [USBD_HID_EP_INTIN] = {usbd_hid_ep_intin_stack, sizeof(usbd_hid_ep_intin_stack)},
+#endif
+#if (USBD_HID_EP_INTOUT_STACK > 0)
+ [USBD_HID_EP_INTOUT] = {usbd_hid_ep_intout_stack, sizeof(usbd_hid_ep_intout_stack)},
+#endif
+#if (USBD_MSC_EP_BULKIN_STACK > 0)
+ [USBD_MSC_EP_BULKIN] = {usbd_msc_ep_bulkin_stack, sizeof(usbd_msc_ep_bulkin_stack)},
+#endif
+#if (USBD_MSC_EP_BULKOUT_STACK > 0)
+ [USBD_MSC_EP_BULKOUT] = {usbd_msc_ep_bulkout_stack, sizeof(usbd_msc_ep_bulkout_stack)},
+#endif
+#if (USBD_ADC_EP_ISOOUT_STACK > 0)
+ [USBD_ADC_EP_ISOOUT] = {usbd_adc_ep_isoout_stack, sizeof(usbd_adc_ep_isoout_stack)},
+#endif
+#if (USBD_CDC_ACM_EP_INTIN_STACK > 0)
+ [USBD_CDC_ACM_EP_INTIN] = {usbd_cdc_acm_ep_intin_stack, sizeof(usbd_cdc_acm_ep_intin_stack)},
+#endif
+#if (USBD_CDC_ACM_EP_BULKIN_STACK > 0)
+ [USBD_CDC_ACM_EP_BULKIN] = {usbd_cdc_acm_ep_bulkin_stack, sizeof(usbd_cdc_acm_ep_bulkin_stack)},
+#endif
+#if (USBD_CDC_ACM_EP_BULKOUT_STACK > 0)
+ [USBD_CDC_ACM_EP_BULKOUT] = {usbd_cdc_acm_ep_bulkout_stack, sizeof(usbd_cdc_acm_ep_bulkout_stack)},
+#endif
+};
+
+#endif /* __RTX */
+
+void USBD_RTX_TaskInit(void)
+{
+#ifdef __RTX
+ /* Initialize memory pools for endpoints */
+ U32 i;
+ USBD_RTX_DevTask = 0;
+
+ if (USBD_RTX_P_Device) {
+ USBD_RTX_DevTask = os_tsk_create_user(USBD_RTX_Device, 3, usbd_device_stack,
+ sizeof(usbd_device_stack));
+ }
+
+ for (i = 0; i <= 15; i++) {
+ USBD_RTX_EPTask[i] = 0;
+
+ if (USBD_RTX_P_EP[i]) {
+ // Set the control endpoint (endpoint 0) thread to a high priority.
+ // According to the USB 2.0 specification, the time to complete standard
+ // request with no data must be under 50ms. If a long caluclation
+ // such as a CRC is running on a higher priority thread, USB enumeration
+ // can fail because of this timeout.
+ uint8_t priority = 0 == i ? 200 : 20;
+ USBD_RTX_EPTask[i] = os_tsk_create_user(USBD_RTX_P_EP[i], priority, user_stack_list[i].stack,
+ user_stack_list[i].size);
+ }
+ }
+
+ USBD_RTX_CoreTask = 0;
+
+ if (USBD_RTX_P_Core) {
+ USBD_RTX_CoreTask = os_tsk_create_user(USBD_RTX_Core, 2, usbd_core_stack,
+ sizeof(usbd_core_stack));
+ }
+
+#endif
+}
+
+/*------------------------------------------------------------------------------
+ * CDC Sizes
+ *----------------------------------------------------------------------------*/
+#define CDC_HEADER_SIZE 5
+#define CDC_CALL_MANAGEMENT_SIZE 5
+#define CDC_ABSTRACT_CONTROL_MANAGEMENT_SIZE 4
+#define CDC_UNION_SIZE 5
+
+/*------------------------------------------------------------------------------
+ * USB Device Descriptors
+ *----------------------------------------------------------------------------*/
+#define USBD_MSC_DESC_LEN (USB_INTERFACE_DESC_SIZE + 2*USB_ENDPOINT_DESC_SIZE)
+#define USBD_CDC_ACM_DESC_LEN (USBD_MULTI_IF * USB_INTERFACE_ASSOC_DESC_SIZE + \
+ /* CDC Interface 1 */ \
+ USB_INTERFACE_DESC_SIZE + CDC_HEADER_SIZE + CDC_CALL_MANAGEMENT_SIZE + \
+ CDC_ABSTRACT_CONTROL_MANAGEMENT_SIZE + CDC_UNION_SIZE + USB_ENDPOINT_DESC_SIZE + \
+ /* CDC Interface 2 */ \
+ USB_INTERFACE_DESC_SIZE + USB_ENDPOINT_DESC_SIZE + USB_ENDPOINT_DESC_SIZE)
+#define USBD_HID_DESC_LEN (USB_INTERFACE_DESC_SIZE + USB_HID_DESC_SIZE + \
+ (USB_ENDPOINT_DESC_SIZE*((USBD_HID_EP_INTIN != 0)+(USBD_HID_EP_INTOUT != 0))))
+#define USBD_BULK_DESC_LEN (USB_INTERFACE_DESC_SIZE + 2*USB_ENDPOINT_DESC_SIZE)
+
+#define USBD_HID_DESC_OFS (USB_CONFIGUARTION_DESC_SIZE + USB_INTERFACE_DESC_SIZE + \
+ USBD_MSC_ENABLE * USBD_MSC_DESC_LEN + USBD_CDC_ACM_ENABLE * USBD_CDC_ACM_DESC_LEN)
+
+#define USBD_WTOTALLENGTH_MAX (USB_CONFIGUARTION_DESC_SIZE + \
+ USBD_CDC_ACM_DESC_LEN * USBD_CDC_ACM_ENABLE + \
+ USBD_HID_DESC_LEN * USBD_HID_ENABLE + \
+ (USB_INTERFACE_DESC_SIZE) * USBD_WEBUSB_ENABLE + \
+ USBD_BULK_DESC_LEN * USBD_BULK_ENABLE + \
+ USBD_MSC_DESC_LEN * USBD_MSC_ENABLE)
+
+/*------------------------------------------------------------------------------
+ Default HID Report Descriptor
+ *----------------------------------------------------------------------------*/
+
+/* Bit Input Output
+ 0 IN0 OUT0
+ 1 IN1 OUT1
+ 2 IN2 OUT2
+ 3 IN3 OUT3
+ 4 IN4 OUT4
+ 5 IN5 OUT5
+ 6 IN6 OUT6
+ 7 IN7 OUT7
+*/
+
+__weak \
+const U8 USBD_HID_ReportDescriptor[] = {
+ HID_UsagePageVendor(0x00),
+ HID_Usage(0x01),
+ HID_Collection(HID_Application),
+ HID_LogicalMin(0), /* value range: 0 - 0xFF */
+ HID_LogicalMaxS(0xFF),
+ HID_ReportSize(8), /* 8 bits */
+#if (USBD_HID_INREPORT_MAX_SZ > 255)
+ HID_ReportCountS(USBD_HID_INREPORT_MAX_SZ),
+#else
+ HID_ReportCount(USBD_HID_INREPORT_MAX_SZ),
+#endif
+ HID_Usage(0x01),
+ HID_Input(HID_Data | HID_Variable | HID_Absolute),
+#if (USBD_HID_OUTREPORT_MAX_SZ > 255)
+ HID_ReportCountS(USBD_HID_OUTREPORT_MAX_SZ),
+#else
+ HID_ReportCount(USBD_HID_OUTREPORT_MAX_SZ),
+#endif
+ HID_Usage(0x01),
+ HID_Output(HID_Data | HID_Variable | HID_Absolute),
+#if (USBD_HID_FEATREPORT_MAX_SZ > 255)
+ HID_ReportCountS(USBD_HID_FEATREPORT_MAX_SZ),
+#else
+ HID_ReportCount(USBD_HID_FEATREPORT_MAX_SZ),
+#endif
+ HID_Usage(0x01),
+ HID_Feature(HID_Data | HID_Variable | HID_Absolute),
+ HID_EndCollection,
+};
+
+__weak \
+const U16 USBD_HID_ReportDescriptorSize = sizeof(USBD_HID_ReportDescriptor);
+
+__weak \
+U16 USBD_HID_DescriptorOffset = USBD_HID_DESC_OFS;
+
+/* USB Device Standard Descriptor */
+__weak \
+const U8 USBD_DeviceDescriptor[] = {
+ USB_DEVICE_DESC_SIZE, /* bLength */
+ USB_DEVICE_DESCRIPTOR_TYPE, /* bDescriptorType */
+#if (USBD_BOS_ENABLE)
+ WBVAL(0x0210), /* 2.10 */ /* bcdUSB */
+#elif ((USBD_HS_ENABLE) || (USBD_MULTI_IF))
+ WBVAL(0x0200), /* 2.00 */ /* bcdUSB */
+#else
+ WBVAL(0x0110), /* 1.10 */ /* bcdUSB */
+#endif
+#if (USBD_MULTI_IF)
+ USB_DEVICE_CLASS_MISCELLANEOUS, /* bDeviceClass */
+ 0x02, /* bDeviceSubClass */
+ 0x01, /* bDeviceProtocol */
+#elif (USBD_CDC_ACM_ENABLE)
+ USB_DEVICE_CLASS_COMMUNICATIONS, /* bDeviceClass CDC*/
+ 0x00, /* bDeviceSubClass */
+ 0x00, /* bDeviceProtocol */
+#else
+ 0x00, /* bDeviceClass */
+ 0x00, /* bDeviceSubClass */
+ 0x00, /* bDeviceProtocol */
+#endif
+ USBD_MAX_PACKET0, /* bMaxPacketSize0 */
+ WBVAL(USBD_DEVDESC_IDVENDOR), /* idVendor */
+ WBVAL(USBD_DEVDESC_IDPRODUCT), /* idProduct */
+ WBVAL(USBD_DEVDESC_BCDDEVICE), /* bcdDevice */
+ 0x01, /* iManufacturer */
+ 0x02, /* iProduct */
+ 0x03 * USBD_STRDESC_SER_ENABLE, /* iSerialNumber */
+ 0x01 /* bNumConfigurations: one possible configuration*/
+};
+
+#if (USBD_HS_ENABLE)
+/* USB Device Qualifier Descriptor (for Full Speed) */
+__weak \
+const U8 USBD_DeviceQualifier[] = {
+ USB_DEVICE_QUALI_SIZE, /* bLength */
+ USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE, /* bDescriptorType */
+#if (USBD_BOS_ENABLE)
+ WBVAL(0x0210), /* 2.10 */ /* bcdUSB */
+#else
+ WBVAL(0x0200), /* 2.00 */ /* bcdUSB */
+#endif
+ 0x00, /* bDeviceClass */
+ 0x00, /* bDeviceSubClass */
+ 0x00, /* bDeviceProtocol */
+ USBD_MAX_PACKET0, /* bMaxPacketSize0 */
+ 0x01, /* bNumConfigurations */
+ 0x00 /* bReserved */
+};
+
+/* USB Device Qualifier Descriptor for High Speed */
+__weak \
+const U8 USBD_DeviceQualifier_HS[] = {
+ USB_DEVICE_QUALI_SIZE, /* bLength */
+ USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE, /* bDescriptorType */
+#if (USBD_BOS_ENABLE)
+ WBVAL(0x0210), /* 2.10 */ /* bcdUSB */
+#else
+ WBVAL(0x0200), /* 2.00 */ /* bcdUSB */
+#endif
+ 0x00, /* bDeviceClass */
+ 0x00, /* bDeviceSubClass */
+ 0x00, /* bDeviceProtocol */
+ USBD_MAX_PACKET0, /* bMaxPacketSize0 */
+ 0x01, /* bNumConfigurations */
+ 0x00 /* bReserved */
+};
+#else
+/* USB Device Qualifier Descriptor (for Full Speed) */
+__weak \
+const U8 USBD_DeviceQualifier[] = { 0 };
+
+/* USB Device Qualifier Descriptor for High Speed */
+__weak \
+const U8 USBD_DeviceQualifier_HS[] = { 0 };
+#endif
+
+#if (USBD_WINUSB_ENABLE)
+
+#define FUNCTION_SUBSET_LEN 160
+#define DEVICE_INTERFACE_GUIDS_FEATURE_LEN 132
+
+#define USBD_WINUSB_DESC_SET_LEN (WINUSB_DESCRIPTOR_SET_HEADER_SIZE + USBD_WEBUSB_ENABLE * FUNCTION_SUBSET_LEN + USBD_BULK_ENABLE * FUNCTION_SUBSET_LEN)
+
+U8 USBD_WinUSBDescriptorSetDescriptor[] = {
+ WBVAL(WINUSB_DESCRIPTOR_SET_HEADER_SIZE), /* wLength */
+ WBVAL(WINUSB_SET_HEADER_DESCRIPTOR_TYPE), /* wDescriptorType */
+ 0x00, 0x00, 0x03, 0x06, /* >= Win 8.1 */ /* dwWindowsVersion*/
+ WBVAL(USBD_WINUSB_DESC_SET_LEN), /* wDescriptorSetTotalLength */
+#if (USBD_WEBUSB_ENABLE)
+ WBVAL(WINUSB_FUNCTION_SUBSET_HEADER_SIZE),// wLength
+ WBVAL(WINUSB_SUBSET_HEADER_FUNCTION_TYPE),// wDescriptorType
+ 0, // bFirstInterface USBD_WINUSB_IF_NUM
+ 0, // bReserved
+ WBVAL(FUNCTION_SUBSET_LEN), // wSubsetLength
+ WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_SIZE), // wLength
+ WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_TYPE), // wDescriptorType
+ 'W', 'I', 'N', 'U', 'S', 'B', 0, 0, // CompatibleId
+ 0, 0, 0, 0, 0, 0, 0, 0, // SubCompatibleId
+ WBVAL(DEVICE_INTERFACE_GUIDS_FEATURE_LEN),// wLength
+ WBVAL(WINUSB_FEATURE_REG_PROPERTY_TYPE), // wDescriptorType
+ WBVAL(WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ), // wPropertyDataType
+ WBVAL(42), // wPropertyNameLength
+ 'D',0,'e',0,'v',0,'i',0,'c',0,'e',0,
+ 'I',0,'n',0,'t',0,'e',0,'r',0,'f',0,'a',0,'c',0,'e',0,
+ 'G',0,'U',0,'I',0,'D',0,'s',0,0,0,
+ WBVAL(80), // wPropertyDataLength
+ '{',0,
+ '9',0,'2',0,'C',0,'E',0,'6',0,'4',0,'6',0,'2',0,'-',0,
+ '9',0,'C',0,'7',0,'7',0,'-',0,
+ '4',0,'6',0,'F',0,'E',0,'-',0,
+ '9',0,'3',0,'3',0,'B',0,'-',
+ 0,'3',0,'1',0,'C',0,'B',0,'9',0,'C',0,'5',0,'A',0,'A',0,'3',0,'B',0,'9',0,
+ '}',0,0,0,0,0,
+#endif
+#if (USBD_BULK_ENABLE)
+ WBVAL(WINUSB_FUNCTION_SUBSET_HEADER_SIZE),/* wLength */
+ WBVAL(WINUSB_SUBSET_HEADER_FUNCTION_TYPE),/* wDescriptorType */
+ 0, /* bFirstInterface USBD_BULK_IF_NUM*/
+ 0, /* bReserved */
+ WBVAL(FUNCTION_SUBSET_LEN), /* wSubsetLength */
+ WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_SIZE), /* wLength */
+ WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_TYPE), /* wDescriptorType */
+ 'W', 'I', 'N', 'U', 'S', 'B', 0, 0, /* CompatibleId*/
+ 0, 0, 0, 0, 0, 0, 0, 0, /* SubCompatibleId*/
+ WBVAL(DEVICE_INTERFACE_GUIDS_FEATURE_LEN),/* wLength */
+ WBVAL(WINUSB_FEATURE_REG_PROPERTY_TYPE), /* wDescriptorType */
+ WBVAL(WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ), /* wPropertyDataType */
+ WBVAL(42), /* wPropertyNameLength */
+ 'D',0,'e',0,'v',0,'i',0,'c',0,'e',0,
+ 'I',0,'n',0,'t',0,'e',0,'r',0,'f',0,'a',0,'c',0,'e',0,
+ 'G',0,'U',0,'I',0,'D',0,'s',0,0,0,
+ WBVAL(80), /* wPropertyDataLength */
+ '{',0,
+ 'C',0,'D',0,'B',0,'3',0,'B',0,'5',0,'A',0,'D',0,'-',0,
+ '2',0,'9',0,'3',0,'B',0,'-',0,
+ '4',0,'6',0,'6',0,'3',0,'-',0,
+ 'A',0,'A',0,'3',0,'6',0,'-',
+ 0,'1',0,'A',0,'A',0,'E',0,'4',0,'6',0,'4',0,'6',0,'3',0,'7',0,'7',0,'6',0,
+ '}',0,0,0,0,0,
+#endif
+};
+
+#else
+
+const U8 USBD_WinUSBDescriptorSetDescriptor[] = { 0 };
+
+BOOL USBD_EndPoint0_Setup_WinUSB_ReqToDevice(void)
+{
+ return (__FALSE);
+}
+
+#endif
+
+#if (USBD_BOS_ENABLE)
+
+#define USBD_NUM_DEV_CAPABILITIES (USBD_WEBUSB_ENABLE + USBD_WINUSB_ENABLE)
+
+#define USBD_WEBUSB_DESC_LEN (sizeof(WEBUSB_PLATFORM_CAPABILITY_DESCRIPTOR))
+
+#define USBD_WINUSB_DESC_LEN (sizeof(WINUSB_PLATFORM_CAPABILITY_DESCRIPTOR))
+
+#define USBD_BOS_WTOTALLENGTH (USB_BOS_DESC_SIZE + \
+ USBD_WEBUSB_DESC_LEN * USBD_WEBUSB_ENABLE + \
+ USBD_WINUSB_DESC_LEN * USBD_WINUSB_ENABLE)
+
+__weak \
+const U8 USBD_BinaryObjectStoreDescriptor[] = {
+ USB_BOS_DESC_SIZE, /* bLength */
+ USB_BINARY_OBJECT_STORE_DESCRIPTOR_TYPE,/* bDescriptorType */
+ WBVAL(USBD_BOS_WTOTALLENGTH), /* wTotalLength */
+ USBD_NUM_DEV_CAPABILITIES, /* bNumDeviceCaps */
+#if (USBD_WEBUSB_ENABLE)
+ USBD_WEBUSB_DESC_LEN, /* bLength */
+ USB_DEVICE_CAPABILITY_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_DEVICE_CAPABILITY_PLATFORM, /* bDevCapabilityType */
+ 0x00, /* bReserved */
+ 0x38, 0xB6, 0x08, 0x34, /* PlatformCapabilityUUID */
+ 0xA9, 0x09, 0xA0, 0x47,
+ 0x8B, 0xFD, 0xA0, 0x76,
+ 0x88, 0x15, 0xB6, 0x65,
+ WBVAL(0x0100), /* 1.00 */ /* bcdVersion */
+ USBD_WEBUSB_VENDOR_CODE, /* bVendorCode */
+ 0, /* iLandingPage */
+#endif
+#if (USBD_WINUSB_ENABLE)
+ USBD_WINUSB_DESC_LEN, /* bLength */
+ USB_DEVICE_CAPABILITY_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_DEVICE_CAPABILITY_PLATFORM, /* bDevCapabilityType */
+ 0x00, /* bReserved */
+ 0xDF, 0x60, 0xDD, 0xD8, /* PlatformCapabilityUUID */
+ 0x89, 0x45, 0xC7, 0x4C,
+ 0x9C, 0xD2, 0x65, 0x9D,
+ 0x9E, 0x64, 0x8A, 0x9F,
+ 0x00, 0x00, 0x03, 0x06, /* >= Win 8.1 *//* dwWindowsVersion*/
+ WBVAL(USBD_WINUSB_DESC_SET_LEN), /* wDescriptorSetTotalLength */
+ USBD_WINUSB_VENDOR_CODE, /* bVendorCode */
+ 0, /* bAltEnumCode */
+#endif
+};
+
+#else
+__weak \
+const U8 USBD_BinaryObjectStoreDescriptor[] = { 0 };
+
+#endif
+
+#define HID_DESC \
+ /* Interface, Alternate Setting 0, HID Class */ \
+ USB_INTERFACE_DESC_SIZE, /* bLength */ \
+ USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ 0x00, /* bInterfaceNumber USBD_HID_IF_NUM*/ \
+ 0x00, /* bAlternateSetting */ \
+ 0x00+(USBD_HID_EP_INTIN != 0)+(USBD_HID_EP_INTOUT != 0), /*0x01+(USBD_HID_EP_INTOUT != 0),*/ /* bNumEndpoints */ \
+ USB_DEVICE_CLASS_HUMAN_INTERFACE, /* bInterfaceClass */ \
+ HID_SUBCLASS_NONE, /* bInterfaceSubClass */ \
+ HID_PROTOCOL_NONE, /* bInterfaceProtocol */ \
+ USBD_HID_IF_STR_NUM, /* iInterface */ \
+ \
+/* HID Class Descriptor */ \
+ USB_HID_DESC_SIZE, /* bLength */ \
+ HID_HID_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ WBVAL(0x0100), /* 1.00 */ /* bcdHID */ \
+ 0x00, /* bCountryCode */ \
+ 0x01, /* bNumDescriptors */ \
+ HID_REPORT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ WBVAL(USB_HID_REPORT_DESC_SIZE), /* wDescriptorLength */
+
+#define VENDOR_DESC_IAD(first,num_of_ifs) /* Vendor: Interface Association Descriptor */ \
+ USB_INTERFACE_ASSOC_DESC_SIZE, /* bLength */ \
+ USB_INTERFACE_ASSOCIATION_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ (first), /* bFirstInterface */ \
+ (num_of_ifs), /* bInterfaceCount */ \
+ USB_DEVICE_CLASS_VENDOR_SPECIFIC, /* bFunctionClass */ \
+ 0x00, /* bFunctionSubclass */ \
+ 0x00, /* bFunctionProtocol */ \
+ 0x00, /* iFunction */
+
+#define WEBUSB_DESC \
+/* Interface, Alternate Setting 0, VENDOR_SPECIFIC Class */ \
+ USB_INTERFACE_DESC_SIZE, /* bLength */ \
+ USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ 0x00, /* bInterfaceNumber USBD_WEBUSB_IF_NUM */ \
+ 0x00, /* bAlternateSetting */ \
+ 0x00, /* bNumEndpoints */ \
+ USB_DEVICE_CLASS_VENDOR_SPECIFIC, /* bInterfaceClass */ \
+ USB_DEVICE_CLASS_HUMAN_INTERFACE, /* bInterfaceSubClass */ \
+ HID_PROTOCOL_NONE, /* bInterfaceProtocol */ \
+ USBD_WEBUSB_IF_STR_NUM, /* iInterface */ \
+
+#define HID_EP_IN /* HID Endpoint for Low-speed/Full-speed */ \
+/* Endpoint, HID Interrupt In */ \
+ USB_ENDPOINT_DESC_SIZE, /* bLength */ \
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USB_ENDPOINT_IN(USBD_HID_EP_INTIN), /* bEndpointAddress */ \
+ USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */ \
+ WBVAL(USBD_HID_WMAXPACKETSIZE), /* wMaxPacketSize */ \
+ USBD_HID_BINTERVAL, /* bInterval */
+
+#define HID_EP_OUT /* HID Endpoint for Low-speed/Full-speed */ \
+/* Endpoint, HID Interrupt Out */ \
+ USB_ENDPOINT_DESC_SIZE, /* bLength */ \
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USB_ENDPOINT_OUT(USBD_HID_EP_INTOUT), /* bEndpointAddress */ \
+ USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */ \
+ WBVAL(USBD_HID_WMAXPACKETSIZE), /* wMaxPacketSize */ \
+ USBD_HID_BINTERVAL, /* bInterval */
+
+#define HID_EP_INOUT /* HID Endpoint for Low-speed/Full-speed */ \
+/* Endpoint, HID Interrupt In */ \
+ USB_ENDPOINT_DESC_SIZE, /* bLength */ \
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USB_ENDPOINT_IN(USBD_HID_EP_INTIN), /* bEndpointAddress */ \
+ USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */ \
+ WBVAL(USBD_HID_WMAXPACKETSIZE), /* wMaxPacketSize */ \
+ USBD_HID_BINTERVAL, /* bInterval */ \
+ \
+/* Endpoint, HID Interrupt Out */ \
+ USB_ENDPOINT_DESC_SIZE, /* bLength */ \
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USB_ENDPOINT_OUT(USBD_HID_EP_INTOUT), /* bEndpointAddress */ \
+ USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */ \
+ WBVAL(USBD_HID_WMAXPACKETSIZE), /* wMaxPacketSize */ \
+ USBD_HID_BINTERVAL, /* bInterval */
+
+#define HID_EP_IN_HS /* HID Endpoint for High-speed */ \
+/* Endpoint, HID Interrupt In */ \
+ USB_ENDPOINT_DESC_SIZE, /* bLength */ \
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USB_ENDPOINT_IN(USBD_HID_EP_INTIN), /* bEndpointAddress */ \
+ USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */ \
+ WBVAL(USBD_HID_HS_WMAXPACKETSIZE), /* wMaxPacketSize */ \
+ USBD_HID_HS_BINTERVAL, /* bInterval */
+
+#define HID_EP_OUT_HS /* HID Endpoint for High-speed */ \
+/* Endpoint, HID Interrupt Out */ \
+ USB_ENDPOINT_DESC_SIZE, /* bLength */ \
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USB_ENDPOINT_OUT(USBD_HID_EP_INTOUT), /* bEndpointAddress */ \
+ USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */ \
+ WBVAL(USBD_HID_HS_WMAXPACKETSIZE), /* wMaxPacketSize */ \
+ USBD_HID_HS_BINTERVAL, /* bInterval */
+
+#define HID_EP_INOUT_HS /* HID Endpoint for High-speed */ \
+/* Endpoint, HID Interrupt In */ \
+ USB_ENDPOINT_DESC_SIZE, /* bLength */ \
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USB_ENDPOINT_IN(USBD_HID_EP_INTIN), /* bEndpointAddress */ \
+ USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */ \
+ WBVAL(USBD_HID_HS_WMAXPACKETSIZE), /* wMaxPacketSize */ \
+ USBD_HID_HS_BINTERVAL, /* bInterval */ \
+ \
+/* Endpoint, HID Interrupt Out */ \
+ USB_ENDPOINT_DESC_SIZE, /* bLength */ \
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USB_ENDPOINT_OUT(USBD_HID_EP_INTOUT), /* bEndpointAddress */ \
+ USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */ \
+ WBVAL(USBD_HID_HS_WMAXPACKETSIZE), /* wMaxPacketSize */ \
+ USBD_HID_HS_BINTERVAL, /* bInterval */
+
+#define MSC_DESC \
+/* Interface, Alternate Setting 0, MSC Class */ \
+ USB_INTERFACE_DESC_SIZE, /* bLength */ \
+ USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ 0x00, /* bInterfaceNumber USBD_MSC_IF_NUM*/ \
+ 0x00, /* bAlternateSetting */ \
+ 0x02, /* bNumEndpoints */ \
+ USB_DEVICE_CLASS_STORAGE, /* bInterfaceClass */ \
+ MSC_SUBCLASS_SCSI, /* bInterfaceSubClass */ \
+ MSC_PROTOCOL_BULK_ONLY, /* bInterfaceProtocol */ \
+ USBD_MSC_IF_STR_NUM, /* iInterface */
+
+#define MSC_EP /* MSC Endpoints for Low-speed/Full-speed */ \
+/* Endpoint, EP Bulk IN */ \
+ USB_ENDPOINT_DESC_SIZE, /* bLength */ \
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USB_ENDPOINT_IN(USBD_MSC_EP_BULKIN), /* bEndpointAddress */ \
+ USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ \
+ WBVAL(USBD_MSC_WMAXPACKETSIZE), /* wMaxPacketSize */ \
+ 0x00, /* bInterval: ignore for Bulk transfer */ \
+ \
+/* Endpoint, EP Bulk OUT */ \
+ USB_ENDPOINT_DESC_SIZE, /* bLength */ \
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USB_ENDPOINT_OUT(USBD_MSC_EP_BULKOUT),/* bEndpointAddress */ \
+ USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ \
+ WBVAL(USBD_MSC_WMAXPACKETSIZE), /* wMaxPacketSize */ \
+ 0x00, /* bInterval: ignore for Bulk transfer */
+
+#define MSC_EP_HS /* MSC Endpoints for High-speed */ \
+/* Endpoint, EP Bulk IN */ \
+ USB_ENDPOINT_DESC_SIZE, /* bLength */ \
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USB_ENDPOINT_IN(USBD_MSC_EP_BULKIN), /* bEndpointAddress */ \
+ USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ \
+ WBVAL(USBD_MSC_HS_WMAXPACKETSIZE), /* wMaxPacketSize */ \
+ USBD_MSC_HS_BINTERVAL, /* bInterval */ \
+ \
+/* Endpoint, EP Bulk OUT */ \
+ USB_ENDPOINT_DESC_SIZE, /* bLength */ \
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USB_ENDPOINT_OUT(USBD_MSC_EP_BULKOUT),/* bEndpointAddress */ \
+ USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ \
+ WBVAL(USBD_MSC_HS_WMAXPACKETSIZE), /* wMaxPacketSize */ \
+ USBD_MSC_HS_BINTERVAL, /* bInterval */
+
+#define BULK_DESC \
+/* Interface, Alternate Setting 0, MSC Class */ \
+ USB_INTERFACE_DESC_SIZE, /* bLength */ \
+ USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ 0x00, /* bInterfaceNumber USBD_BULK_IF_NUM*/ \
+ 0x00, /* bAlternateSetting */ \
+ 0x02, /* bNumEndpoints */ \
+ USB_DEVICE_CLASS_VENDOR_SPECIFIC, /* bInterfaceClass */ \
+ 0x00, /* bInterfaceSubClass */ \
+ 0x00, /* bInterfaceProtocol */ \
+ USBD_BULK_IF_STR_NUM, /* iInterface */
+
+#define BULK_EP /* MSC Endpoints for Low-speed/Full-speed */ \
+/* Endpoint, EP Bulk OUT */ \
+ USB_ENDPOINT_DESC_SIZE, /* bLength */ \
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USB_ENDPOINT_OUT(USBD_BULK_EP_BULKOUT),/* bEndpointAddress */ \
+ USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ \
+ WBVAL(USBD_BULK_WMAXPACKETSIZE), /* wMaxPacketSize */ \
+ 0x00, /* bInterval: ignore for Bulk transfer */ \
+ \
+/* Endpoint, EP Bulk IN */ \
+ USB_ENDPOINT_DESC_SIZE, /* bLength */ \
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USB_ENDPOINT_IN(USBD_BULK_EP_BULKIN), /* bEndpointAddress */ \
+ USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ \
+ WBVAL(USBD_BULK_WMAXPACKETSIZE), /* wMaxPacketSize */ \
+ 0x00, /* bInterval: ignore for Bulk transfer */
+
+#define BULK_EP_HS /* MSC Endpoints for Low-speed/Full-speed */ \
+/* Endpoint, EP Bulk OUT */ \
+ USB_ENDPOINT_DESC_SIZE, /* bLength */ \
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USB_ENDPOINT_OUT(USBD_BULK_EP_BULKOUT), /* bEndpointAddress */ \
+ USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ \
+ WBVAL(USBD_BULK_HS_WMAXPACKETSIZE), /* wMaxPacketSize */ \
+ 0x00, /* bInterval: ignore for Bulk transfer */ \
+ \
+/* Endpoint, EP Bulk IN */ \
+ USB_ENDPOINT_DESC_SIZE, /* bLength */ \
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USB_ENDPOINT_IN(USBD_BULK_EP_BULKIN),/* bEndpointAddress */ \
+ USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ \
+ WBVAL(USBD_BULK_HS_WMAXPACKETSIZE), /* wMaxPacketSize */ \
+ 0x00, /* bInterval: ignore for Bulk transfer */
+
+#define ADC_DESC_IAD(first,num_of_ifs) /* ADC: Interface Association Descriptor */ \
+ USB_INTERFACE_ASSOC_DESC_SIZE, /* bLength */ \
+ USB_INTERFACE_ASSOCIATION_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ (first), /* bFirstInterface */ \
+ (num_of_ifs), /* bInterfaceCount */ \
+ USB_DEVICE_CLASS_AUDIO, /* bFunctionClass */ \
+ AUDIO_SUBCLASS_AUDIOCONTROL, /* bFunctionSubclass */ \
+ AUDIO_PROTOCOL_UNDEFINED, /* bFunctionProtocol */ \
+ USBD_ADC_CIF_STR_NUM, /* iFunction */ \
+
+#define ADC_DESC \
+/* Interface, Alternate Setting 0, Audio Control */ \
+ USB_INTERFACE_DESC_SIZE, /* bLength */ \
+ USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USBD_ADC_CIF_NUM, /* bInterfaceNumber */ \
+ 0x00, /* bAlternateSetting */ \
+ 0x00, /* bNumEndpoints */ \
+ USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \
+ AUDIO_SUBCLASS_AUDIOCONTROL, /* bInterfaceSubClass */ \
+ AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ \
+ USBD_ADC_CIF_STR_NUM, /* iInterface */ \
+/* Audio Control Interface */ \
+ AUDIO_CONTROL_INTERFACE_DESC_SZ(1), /* bLength */ \
+ AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ AUDIO_CONTROL_HEADER, /* bDescriptorSubtype */ \
+ WBVAL(0x0100), /* 1.00 */ /* bcdADC */ \
+ WBVAL( /* wTotalLength */ \
+ AUDIO_CONTROL_INTERFACE_DESC_SZ(1) + \
+ AUDIO_INPUT_TERMINAL_DESC_SIZE + \
+ AUDIO_FEATURE_UNIT_DESC_SZ(1,1) + \
+ AUDIO_OUTPUT_TERMINAL_DESC_SIZE \
+ ), \
+ 0x01, /* bInCollection */ \
+ 0x01, /* baInterfaceNr */ \
+ \
+/* Audio Input Terminal */ \
+ AUDIO_INPUT_TERMINAL_DESC_SIZE, /* bLength */ \
+ AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ AUDIO_CONTROL_INPUT_TERMINAL, /* bDescriptorSubtype */ \
+ 0x01, /* bTerminalID */ \
+ WBVAL(AUDIO_TERMINAL_USB_STREAMING), /* wTerminalType */ \
+ 0x00, /* bAssocTerminal */ \
+ 0x01, /* bNrChannels */ \
+ WBVAL(AUDIO_CHANNEL_M), /* wChannelConfig */ \
+ 0x00, /* iChannelNames */ \
+ 0x00, /* iTerminal */ \
+ \
+/* Audio Feature Unit */ \
+ AUDIO_FEATURE_UNIT_DESC_SZ(1,1), /* bLength */ \
+ AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ AUDIO_CONTROL_FEATURE_UNIT, /* bDescriptorSubtype */ \
+ 0x02, /* bUnitID */ \
+ 0x01, /* bSourceID */ \
+ 0x01, /* bControlSize */ \
+ AUDIO_CONTROL_MUTE | \
+ AUDIO_CONTROL_VOLUME, /* bmaControls(0) */ \
+ 0x00, /* bmaControls(1) */ \
+ 0x00, /* iTerminal */ \
+ \
+/* Audio Output Terminal */ \
+ AUDIO_OUTPUT_TERMINAL_DESC_SIZE, /* bLength */ \
+ AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ AUDIO_CONTROL_OUTPUT_TERMINAL, /* bDescriptorSubtype */ \
+ 0x03, /* bTerminalID */ \
+ WBVAL(AUDIO_TERMINAL_SPEAKER), /* wTerminalType */ \
+ 0x00, /* bAssocTerminal */ \
+ 0x02, /* bSourceID */ \
+ 0x00, /* iTerminal */ \
+ \
+/* Interface, Alternate Setting 0, Audio Streaming - Zero Bandwith */ \
+ USB_INTERFACE_DESC_SIZE, /* bLength */ \
+ USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USBD_ADC_SIF1_NUM, /* bInterfaceNumber */ \
+ 0x00, /* bAlternateSetting */ \
+ 0x00, /* bNumEndpoints */ \
+ USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \
+ AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ \
+ AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ \
+ USBD_ADC_SIF1_STR_NUM, /* iInterface */ \
+ \
+/* Interface, Alternate Setting 1, Audio Streaming - Operational */ \
+ USB_INTERFACE_DESC_SIZE, /* bLength */ \
+ USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USBD_ADC_SIF1_NUM, /* bInterfaceNumber */ \
+ 0x01, /* bAlternateSetting */ \
+ 0x01, /* bNumEndpoints */ \
+ USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \
+ AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ \
+ AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ \
+ USBD_ADC_SIF2_STR_NUM, /* iInterface */ \
+ \
+/* Audio Streaming Interface */ \
+ AUDIO_STREAMING_INTERFACE_DESC_SIZE, /* bLength */ \
+ AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ AUDIO_STREAMING_GENERAL, /* bDescriptorSubtype */ \
+ 0x01, /* bTerminalLink */ \
+ 0x01, /* bDelay */ \
+ WBVAL(AUDIO_FORMAT_PCM), /* wFormatTag */ \
+ \
+/* Audio Type I Format */ \
+ AUDIO_FORMAT_TYPE_I_DESC_SZ(1), /* bLength */ \
+ AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ AUDIO_STREAMING_FORMAT_TYPE, /* bDescriptorSubtype */ \
+ AUDIO_FORMAT_TYPE_I, /* bFormatType */ \
+ 0x01, /* bNrChannels */ \
+ USBD_ADC_BSUBFRAMESIZE, /* bSubFrameSize */ \
+ USBD_ADC_BBITRESOLUTION, /* bBitResolution */ \
+ 0x01, /* bSamFreqType */ \
+ B3VAL(USBD_ADC_TSAMFREQ), /* tSamFreq */
+
+#define ADC_EP /* ADC Endpoints for Low-speed/Full-speed */ \
+/* Endpoint, EP ISO OUT - Standard Descriptor */ \
+ AUDIO_STANDARD_ENDPOINT_DESC_SIZE, /* bLength */ \
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USB_ENDPOINT_OUT(USBD_ADC_EP_ISOOUT), /* bEndpointAddress */ \
+ USB_ENDPOINT_TYPE_ISOCHRONOUS, /* bmAttributes */ \
+ WBVAL(USBD_ADC_WMAXPACKETSIZE), /* wMaxPacketSize */ \
+ USBD_ADC_BINTERVAL, /* bInterval */ \
+ 0x00, /* bRefresh */ \
+ 0x00, /* bSynchAddress */ \
+ \
+/* Endpoint - Audio Streaming */ \
+ AUDIO_STREAMING_ENDPOINT_DESC_SIZE, /* bLength */ \
+ AUDIO_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ AUDIO_ENDPOINT_GENERAL, /* bDescriptor */ \
+ 0x00, /* bmAttributes */ \
+ 0x00, /* bLockDelayUnits */ \
+ WBVAL(0x0000), /* wLockDelay */
+
+#define ADC_EP_HS /* ADC Endpoints for High-speed */ \
+/* Endpoint, EP ISO OUT - Standard Descriptor */ \
+ AUDIO_STANDARD_ENDPOINT_DESC_SIZE, /* bLength */ \
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USB_ENDPOINT_OUT(USBD_ADC_EP_ISOOUT), /* bEndpointAddress */ \
+ USB_ENDPOINT_TYPE_ISOCHRONOUS, /* bmAttributes */ \
+ WBVAL(USBD_ADC_HS_WMAXPACKETSIZE), /* wMaxPacketSize */ \
+ USBD_ADC_BINTERVAL, /* bInterval */ \
+ 0x00, /* bRefresh */ \
+ 0x00, /* bSynchAddress */ \
+ \
+/* Endpoint - Audio Streaming */ \
+ AUDIO_STREAMING_ENDPOINT_DESC_SIZE, /* bLength */ \
+ AUDIO_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ AUDIO_ENDPOINT_GENERAL, /* bDescriptor */ \
+ 0x00, /* bmAttributes */ \
+ 0x00, /* bLockDelayUnits */ \
+ WBVAL(0x0000), /* wLockDelay */
+
+#define CDC_ACM_DESC_IAD(first,num_of_ifs) /* CDC: Interface Association Descriptor */ \
+ USB_INTERFACE_ASSOC_DESC_SIZE, /* bLength */ \
+ USB_INTERFACE_ASSOCIATION_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ (first), /* bFirstInterface */ \
+ (num_of_ifs), /* bInterfaceCount */ \
+ CDC_COMMUNICATION_INTERFACE_CLASS, /* bFunctionClass (Communication Class) */ \
+ CDC_ABSTRACT_CONTROL_MODEL, /* bFunctionSubclass (Abstract Control Model) */ \
+ 0x01, /* bFunctionProtocol (V.25ter, Common AT commands) */ \
+ USBD_CDC_ACM_CIF_STR_NUM, /* iFunction */ \
+
+#define CDC_ACM_DESC_IF0 \
+/* Interface, Alternate Setting 0, CDC Class */ \
+ USB_INTERFACE_DESC_SIZE, /* bLength */ \
+ USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ 0x00, /* bInterfaceNumber: Number of Interface USBD_CDC_ACM_CIF_NUM*/ \
+ 0x00, /* bAlternateSetting: Alternate setting */ \
+ 0x01, /* bNumEndpoints: One endpoint used */ \
+ CDC_COMMUNICATION_INTERFACE_CLASS, /* bInterfaceClass: Communication Interface Class */ \
+ CDC_ABSTRACT_CONTROL_MODEL, /* bInterfaceSubClass: Abstract Control Model */ \
+ 0x01, /* bInterfaceProtocol: no protocol used */ \
+ USBD_CDC_ACM_CIF_STR_NUM, /* iInterface: */ \
+ \
+/* Header Functional Descriptor */ \
+ CDC_HEADER_SIZE, /* bLength: Endpoint Descriptor size */ \
+ CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ \
+ CDC_HEADER, /* bDescriptorSubtype: Header Func Desc */ \
+ WBVAL(CDC_V1_10), /* 1.10 */ /* bcdCDC */ \
+/* Call Management Functional Descriptor */ \
+ CDC_CALL_MANAGEMENT_SIZE, /* bFunctionLength */ \
+ CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ \
+ CDC_CALL_MANAGEMENT, /* bDescriptorSubtype: Call Management Func Desc */ \
+ 0x03, /* bmCapabilities: device handles call management */ \
+ 0x02, /* bDataInterface: CDC data IF ID */ \
+/* Abstract Control Management Functional Descriptor */ \
+ CDC_ABSTRACT_CONTROL_MANAGEMENT_SIZE, /* bFunctionLength */ \
+ CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ \
+ CDC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype: Abstract Control Management desc */ \
+ 0x06, /* bmCapabilities: SET_LINE_CODING, GET_LINE_CODING, SET_CONTROL_LINE_STATE supported */ \
+/* Union Functional Descriptor */ \
+ CDC_UNION_SIZE, /* bFunctionLength */ \
+ CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */ \
+ CDC_UNION, /* bDescriptorSubtype: Union func desc */ \
+ 0x00, /* bMasterInterface: Communication class interface is master USBD_CDC_ACM_CIF_NUM*/ \
+ 0x00, /* bSlaveInterface0: Data class interface is slave 0 USBD_CDC_ACM_DIF_NUM*/
+
+#define CDC_ACM_EP_IF0 /* CDC Endpoints for Interface 0 for Low-speed/Full-speed */ \
+/* Endpoint, EP Interrupt IN */ /* event notification (optional) */ \
+ USB_ENDPOINT_DESC_SIZE, /* bLength */ \
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USB_ENDPOINT_IN(USBD_CDC_ACM_EP_INTIN),/* bEndpointAddress */ \
+ USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */ \
+ WBVAL(USBD_CDC_ACM_WMAXPACKETSIZE), /* wMaxPacketSize */ \
+ USBD_CDC_ACM_BINTERVAL, /* bInterval */
+
+#define CDC_ACM_EP_IF0_HS /* CDC Endpoints for Interface 0 for High-speed */ \
+/* Endpoint, EP Interrupt IN */ /* event notification (optional) */ \
+ USB_ENDPOINT_DESC_SIZE, /* bLength */ \
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USB_ENDPOINT_IN(USBD_CDC_ACM_EP_INTIN),/* bEndpointAddress */ \
+ USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */ \
+ WBVAL(USBD_CDC_ACM_HS_WMAXPACKETSIZE),/* wMaxPacketSize */ \
+ USBD_CDC_ACM_HS_BINTERVAL, /* bInterval */
+
+#define CDC_ACM_DESC_IF1 \
+/* Interface, Alternate Setting 0, Data class interface descriptor*/ \
+ USB_INTERFACE_DESC_SIZE, /* bLength */ \
+ USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ 0x00, /* bInterfaceNumber: Number of Interface USBD_CDC_ACM_DIF_NUM*/ \
+ 0x00, /* bAlternateSetting: no alternate setting */ \
+ 0x02, /* bNumEndpoints: two endpoints used */ \
+ CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass: Data Interface Class */ \
+ 0x00, /* bInterfaceSubClass: no subclass available */ \
+ 0x00, /* bInterfaceProtocol: no protocol used */ \
+ USBD_CDC_ACM_DIF_STR_NUM, /* iInterface */
+
+#define CDC_ACM_EP_IF1 /* CDC Endpoints for Interface 1 for Low-speed/Full-speed */ \
+/* Endpoint, EP Bulk OUT */ \
+ USB_ENDPOINT_DESC_SIZE, /* bLength */ \
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USB_ENDPOINT_OUT(USBD_CDC_ACM_EP_BULKOUT),/* bEndpointAddress */ \
+ USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ \
+ WBVAL(USBD_CDC_ACM_WMAXPACKETSIZE1), /* wMaxPacketSize */ \
+ 0x00, /* bInterval: ignore for Bulk transfer */ \
+ \
+/* Endpoint, EP Bulk IN */ \
+ USB_ENDPOINT_DESC_SIZE, /* bLength */ \
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USB_ENDPOINT_IN(USBD_CDC_ACM_EP_BULKIN),/* bEndpointAddress */ \
+ USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ \
+ WBVAL(USBD_CDC_ACM_WMAXPACKETSIZE1), /* wMaxPacketSize */ \
+ 0x00, /* bInterval: ignore for Bulk transfer */
+
+#define CDC_ACM_EP_IF1_HS /* CDC Endpoints for Interface 1 for High-speed */ \
+/* Endpoint, EP Bulk OUT */ \
+ USB_ENDPOINT_DESC_SIZE, /* bLength */ \
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USB_ENDPOINT_OUT(USBD_CDC_ACM_EP_BULKOUT),/* bEndpointAddress */ \
+ USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ \
+ WBVAL(USBD_CDC_ACM_HS_WMAXPACKETSIZE1),/* wMaxPacketSize */ \
+ USBD_CDC_ACM_HS_BINTERVAL1, /* bInterval */ \
+ \
+/* Endpoint, EP Bulk IN */ \
+ USB_ENDPOINT_DESC_SIZE, /* bLength */ \
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \
+ USB_ENDPOINT_IN(USBD_CDC_ACM_EP_BULKIN),/* bEndpointAddress */ \
+ USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ \
+ WBVAL(USBD_CDC_ACM_HS_WMAXPACKETSIZE1),/* wMaxPacketSize */ \
+ USBD_CDC_ACM_HS_BINTERVAL1, /* bInterval */
+
+/* USB Device Configuration Descriptor (for Full Speed) */
+/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor) */
+__weak \
+U8 USBD_ConfigDescriptor[200] = { 0 };
+
+#if (USBD_HS_ENABLE == 0) /* If High-speed not enabled, declare dummy descriptors for High-speed */
+__weak \
+U8 USBD_ConfigDescriptor_HS[] = { 0 };
+#else
+/* USB Device Configuration Descriptor (for High Speed) */
+/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor) */
+__weak \
+U8 USBD_ConfigDescriptor_HS[200] = { 0 };
+
+#endif
+
+/* USB Device Create String Descriptor */
+#define USBD_STR_DEF(n) \
+ struct { \
+ U8 len; \
+ U8 type; \
+ U16 str[sizeof(USBD_##n)/2-1]; \
+ } desc##n
+
+#define USBD_STR_VAL(n) \
+ { sizeof(USBD_##n), USB_STRING_DESCRIPTOR_TYPE, USBD_##n }
+
+__weak \
+const struct {
+ struct {
+ U8 len;
+ U8 type;
+ U16 langid;
+ } desc_langid;
+ USBD_STR_DEF(STRDESC_MAN);
+ USBD_STR_DEF(STRDESC_PROD);
+#if (USBD_STRDESC_SER_ENABLE)
+ USBD_STR_DEF(STRDESC_SER);
+#endif
+#if (USBD_ADC_ENABLE)
+ USBD_STR_DEF(ADC_CIF_STRDESC);
+ USBD_STR_DEF(ADC_SIF1_STRDESC);
+ USBD_STR_DEF(ADC_SIF2_STRDESC);
+#endif
+#if (USBD_CDC_ACM_ENABLE)
+ USBD_STR_DEF(CDC_ACM_CIF_STRDESC);
+ USBD_STR_DEF(CDC_ACM_DIF_STRDESC);
+#endif
+#if (USBD_HID_ENABLE)
+ USBD_STR_DEF(HID_STRDESC);
+#endif
+#if (USBD_WEBUSB_ENABLE)
+ USBD_STR_DEF(WEBUSB_STRDESC);
+#endif
+#if (USBD_MSC_ENABLE)
+ USBD_STR_DEF(MSC_STRDESC);
+#endif
+#if (USBD_BULK_ENABLE)
+ USBD_STR_DEF(BULK_STRDESC);
+#endif
+} USBD_StringDescriptor
+= {
+ { 4, USB_STRING_DESCRIPTOR_TYPE, USBD_STRDESC_LANGID },
+ USBD_STR_VAL(STRDESC_MAN),
+ USBD_STR_VAL(STRDESC_PROD),
+#if (USBD_STRDESC_SER_ENABLE)
+ USBD_STR_VAL(STRDESC_SER),
+#endif
+#if (USBD_ADC_ENABLE)
+ USBD_STR_VAL(ADC_CIF_STRDESC),
+ USBD_STR_VAL(ADC_SIF1_STRDESC),
+ USBD_STR_VAL(ADC_SIF2_STRDESC),
+#endif
+#if (USBD_CDC_ACM_ENABLE)
+ USBD_STR_VAL(CDC_ACM_CIF_STRDESC),
+ USBD_STR_VAL(CDC_ACM_DIF_STRDESC),
+#endif
+#if (USBD_HID_ENABLE)
+ USBD_STR_VAL(HID_STRDESC),
+#endif
+#if (USBD_WEBUSB_ENABLE)
+ USBD_STR_VAL(WEBUSB_STRDESC),
+#endif
+#if (USBD_MSC_ENABLE)
+ USBD_STR_VAL(MSC_STRDESC),
+#endif
+#if (USBD_BULK_ENABLE)
+ USBD_STR_VAL(BULK_STRDESC),
+#endif
+};
+
+#if (USBD_WEBUSB_ENABLE)
+
+#define WEBUSB_NUM_FUNCTIONS (1)
+
+#define WEBUSB_WTOTALLENGTH (WEBUSB_DESCRIPTOR_SET_HEADER_SIZE + \
+ WEBUSB_CONFIGURATION_SUBSET_HEADER_SIZE +\
+ (WEBUSB_NUM_FUNCTIONS * (WEBUSB_FUNCTION_SUBSET_HEADER_SIZE + 1)))
+
+/* WebUSB Create URL Descriptor */
+#define WEBUSB_URL_DEF(n) \
+ struct { \
+ U8 bLength; \
+ U8 bDescriptorType; \
+ U8 bScheme; \
+ U8 URL[sizeof(USBD_##n)+3];\
+ } url##n
+
+#define WEBUSB_HTTP_URL_VAL(n) \
+{ \
+ (sizeof(USBD_##n) + 3) + 3, \
+ WEBUSB_URL_TYPE, \
+ WEBUSB_URL_SCHEME_HTTP, \
+ USBD_##n \
+}
+
+#define WEBUSB_HTTPS_URL_VAL(n) \
+{ \
+ (sizeof(USBD_##n) + 3) + 3, \
+ WEBUSB_URL_TYPE, \
+ WEBUSB_URL_SCHEME_HTTPS, \
+ USBD_##n \
+}
+
+__weak \
+struct {
+ WEBUSB_URL_DEF(WEBUSB_LANDING_URL);
+ WEBUSB_URL_DEF(WEBUSB_ORIGIN_URL);
+} USBD_WebUSBURLDescriptor
+= {
+ WEBUSB_HTTPS_URL_VAL(WEBUSB_LANDING_URL),
+ WEBUSB_HTTPS_URL_VAL(WEBUSB_ORIGIN_URL),
+};
+
+#else
+
+U8 USBD_WebUSBURLDescriptor[] = { 0 };
+
+BOOL USBD_EndPoint0_Setup_WebUSB_ReqToDevice(void)
+{
+ return (__FALSE);
+}
+
+#endif //USBD_WEBUSB_ENABLE
+
+
+extern uint8_t flash_algo_valid(void);
+
+static U16 start_desc_fill(U8 * config_desc, U8 * config_desc_hs, U8 if_num) {
+ U8 * pD = 0;
+ const U8 start_desc[] = {
+ /* Configuration 1 */
+ USB_CONFIGUARTION_DESC_SIZE, // bLength
+ USB_CONFIGURATION_DESCRIPTOR_TYPE, // bDescriptorType
+ WBVAL(USBD_WTOTALLENGTH_MAX), // wTotalLength
+ USBD_IF_NUM_MAX, // bNumInterfaces
+ 0x01, // bConfigurationValue: 0x01 is used to select this configuration
+ 0x00, // iConfiguration: no string to describe this configuration
+ USBD_CFGDESC_BMATTRIBUTES | // bmAttributes
+ (USBD_POWER << 6),
+ USBD_CFGDESC_BMAXPOWER // bMaxPower, device power consumption
+ };
+ pD = config_desc;
+ memcpy(pD, start_desc, sizeof(start_desc));
+
+#if (USBD_HS_ENABLE == 1)
+ pD = config_desc_hs;
+ memcpy(pD, start_desc, sizeof(start_desc));
+#endif
+
+ return sizeof(start_desc);
+}
+
+static U16 hid_desc_fill(U8 * config_desc, U8 * config_desc_hs, U8 if_num) {
+ U8 * pD = 0;
+ const U8 hid_desc[] = {
+ HID_DESC
+ #if ((USBD_HID_EP_INTOUT != 0) && (USBD_HID_EP_INTIN != 0))
+ HID_EP_INOUT
+ #elif (USBD_HID_EP_INTIN != 0)
+ HID_EP_IN
+ #elif (USBD_HID_EP_INTOUT != 0)
+ HID_EP_OUT
+ #endif
+ };
+ pD = config_desc;
+ memcpy(pD, hid_desc, sizeof(hid_desc));
+ ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber = if_num;
+#if (USBD_HS_ENABLE == 1)
+ const U8 hid_desc_hs[] = {
+ HID_DESC
+ #if ((USBD_HID_EP_INTOUT != 0) && (USBD_HID_EP_INTIN != 0))
+ HID_EP_INOUT_HS
+ #elif (USBD_HID_EP_INTIN != 0) //#else
+ HID_EP_IN_HS
+ #elif (USBD_HID_EP_INTOUT != 0)
+ HID_EP_OUT_HS
+ #endif
+ };
+ pD = config_desc_hs;
+ memcpy(pD, hid_desc_hs, sizeof(hid_desc_hs));
+ ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber = if_num;
+#endif
+ return sizeof(hid_desc);
+}
+
+static U16 acm_cdc_desc_fill(U8 * config_desc, U8 * config_desc_hs, U8 if_num) {
+ U8 * pD = 0;
+ const U8 cdc_desc[] = {
+ #if (USBD_MULTI_IF)
+ CDC_ACM_DESC_IAD(0, 2)
+ #endif
+ CDC_ACM_DESC_IF0
+ CDC_ACM_EP_IF0
+ CDC_ACM_DESC_IF1
+ CDC_ACM_EP_IF1
+ };
+ pD = config_desc;
+ memcpy(pD, cdc_desc, sizeof(cdc_desc));
+
+#if (USBD_MULTI_IF)
+ ((USB_INTERFACE_ASSOCIATION_DESCRIPTOR *)pD)->bFirstInterface = if_num;
+ pD += USB_INTERFACE_ASSOC_DESC_SIZE;
+#endif
+
+ ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber = if_num;
+ pD += USB_INTERFACE_DESC_SIZE + CDC_HEADER_SIZE + CDC_CALL_MANAGEMENT_SIZE + CDC_ABSTRACT_CONTROL_MANAGEMENT_SIZE;
+ ((UNION_FUNCTIONAL_DESCRIPTOR*)pD)->bMasterInterface = if_num;
+ ((UNION_FUNCTIONAL_DESCRIPTOR*)pD)->bSlaveInterface0 = if_num + 1;
+ pD += CDC_UNION_SIZE + USB_ENDPOINT_DESC_SIZE;
+ ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber = if_num + 1;
+
+#if (USBD_HS_ENABLE == 1)
+ const U8 cdc_desc_hs[] = {
+ #if (USBD_MULTI_IF)
+ CDC_ACM_DESC_IAD(0, 2)
+ #endif
+ CDC_ACM_DESC_IF0
+ CDC_ACM_EP_IF0_HS
+ CDC_ACM_DESC_IF1
+ CDC_ACM_EP_IF1_HS
+ };
+ pD = config_desc_hs;
+ memcpy(pD, cdc_desc_hs, sizeof(cdc_desc_hs));
+
+#if (USBD_MULTI_IF)
+ ((USB_INTERFACE_ASSOCIATION_DESCRIPTOR *)pD)->bFirstInterface = if_num;
+ pD += USB_INTERFACE_ASSOC_DESC_SIZE;
+#endif
+
+ ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber = if_num;
+ pD += USB_INTERFACE_DESC_SIZE + CDC_HEADER_SIZE + CDC_CALL_MANAGEMENT_SIZE + CDC_ABSTRACT_CONTROL_MANAGEMENT_SIZE;
+ ((UNION_FUNCTIONAL_DESCRIPTOR*)pD)->bMasterInterface = if_num;
+ ((UNION_FUNCTIONAL_DESCRIPTOR*)pD)->bSlaveInterface0 = if_num + 1;
+ pD += CDC_UNION_SIZE + USB_ENDPOINT_DESC_SIZE;
+ ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber = if_num +1 ;
+#endif //(USBD_HS_ENABLE == 1)
+ return sizeof(cdc_desc);
+}
+
+static U16 msc_desc_fill(U8 * config_desc, U8 * config_desc_hs, U8 if_num) {
+ U8 * pD = 0;
+ const U8 msc_desc[] = {
+ MSC_DESC
+ MSC_EP
+ };
+ pD = config_desc;
+ memcpy(pD, msc_desc, sizeof(msc_desc));
+
+ ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber = if_num;
+
+#if (USBD_HS_ENABLE == 1)
+ const U8 msc_desc_hs[] = {
+ MSC_DESC
+ MSC_EP_HS
+ };
+ pD = config_desc_hs;
+ memcpy(pD, msc_desc_hs, sizeof(msc_desc_hs));
+ ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber = if_num;
+#endif
+
+ return sizeof(msc_desc);
+}
+
+#if (USBD_WEBUSB_ENABLE)
+static U16 webusb_desc_fill(U8 * config_desc, U8 * config_desc_hs, U8 if_num) {
+ U8 * pD = 0;
+ const U8 webusb_desc[] = {
+ WEBUSB_DESC
+ };
+ pD = config_desc;
+ memcpy(pD, webusb_desc, sizeof(webusb_desc));
+ ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber = if_num;
+
+#if (USBD_HS_ENABLE == 1)
+ pD = config_desc_hs;
+ memcpy(pD, webusb_desc, sizeof(webusb_desc));
+ ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber = if_num;
+#endif
+
+#if (USBD_WINUSB_ENABLE)
+ pD = USBD_WinUSBDescriptorSetDescriptor + WINUSB_DESCRIPTOR_SET_HEADER_SIZE;
+ ((WINUSB_FUNCTION_SUBSET_HEADER*)pD)->bFirstInterface = if_num;
+#else
+#error "WEBUSB requires WINUSB!"
+#endif
+
+ return sizeof(webusb_desc);
+}
+#endif
+
+#if (USBD_BULK_ENABLE)
+static U16 bulk_desc_fill(U8 * config_desc, U8 * config_desc_hs, U8 if_num) {
+ U8 * pD = 0;
+ const U8 bulk_desc[] = {
+ BULK_DESC
+ BULK_EP
+ };
+ pD = config_desc;
+ memcpy(pD, bulk_desc, sizeof(bulk_desc));
+ ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber = if_num;
+#if (USBD_HS_ENABLE == 1)
+ const U8 bulk_desc_hs[] = {
+ BULK_DESC
+ BULK_EP_HS
+ };
+ pD = config_desc_hs;
+ memcpy(pD, bulk_desc_hs, sizeof(bulk_desc_hs));
+ ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber = if_num;
+#endif
+
+#if (USBD_WINUSB_ENABLE)
+ pD = USBD_WinUSBDescriptorSetDescriptor + WINUSB_DESCRIPTOR_SET_HEADER_SIZE;
+#if (USBD_WEBUSB_ENABLE)
+ pD += WINUSB_FUNCTION_SUBSET_HEADER_SIZE + WINUSB_FEATURE_COMPATIBLE_ID_SIZE + DEVICE_INTERFACE_GUIDS_FEATURE_LEN;
+#endif
+ ((WINUSB_FUNCTION_SUBSET_HEADER*)pD)->bFirstInterface = if_num;
+#else
+#error "BULK interfaces requires WINUSB!"
+#endif
+
+ return sizeof(bulk_desc);
+}
+#endif
+
+void usbd_class_init(void)
+{
+ U8 if_num = 0;
+ U16 desc_ptr = 0;
+
+ desc_ptr += start_desc_fill(&USBD_ConfigDescriptor[desc_ptr], &USBD_ConfigDescriptor_HS[desc_ptr], if_num);
+
+#if (USBD_ADC_ENABLE)
+ usbd_adc_init();
+#endif
+
+
+#if (USBD_MSC_ENABLE)
+
+#if !(defined(DAPLINK_BL)) && defined(DRAG_N_DROP_SUPPORT)
+ //change descriptors here
+ if (config_ram_get_disable_msd() == 1 || flash_algo_valid()==0 ){
+ usbd_if_num -= USBD_MSC_ENABLE;
+ USB_CONFIGURATION_DESCRIPTOR * usb_conf_desc = (USB_CONFIGURATION_DESCRIPTOR *)USBD_ConfigDescriptor;
+ usb_conf_desc->bNumInterfaces = usbd_if_num;
+ U16 usb_wtotal_len = USBD_WTOTALLENGTH_MAX - (USBD_MSC_DESC_LEN * USBD_MSC_ENABLE);
+ usb_conf_desc->wTotalLength = usb_wtotal_len;
+ USBD_ConfigDescriptor[usb_wtotal_len] = 0;
+ USBD_HID_DescriptorOffset -= USBD_MSC_ENABLE * USBD_MSC_DESC_LEN;
+#if (USBD_HS_ENABLE == 1)
+ usb_conf_desc = (USB_CONFIGURATION_DESCRIPTOR *)USBD_ConfigDescriptor_HS;
+ usb_conf_desc->bNumInterfaces = usbd_if_num;
+ usb_conf_desc->wTotalLength = usb_wtotal_len;
+ USBD_ConfigDescriptor_HS[usb_wtotal_len] = 0;
+#endif
+ } else
+#endif
+ {
+ usbd_msc_if_num = if_num++;
+ desc_ptr += msc_desc_fill(&USBD_ConfigDescriptor[desc_ptr], &USBD_ConfigDescriptor_HS[desc_ptr], usbd_msc_if_num);
+ usbd_msc_init();
+
+ }
+#endif //#if (USBD_MSC_ENABLE)
+
+#if (USBD_CDC_ACM_ENABLE)
+ usbd_cdc_acm_cif_num = if_num++;
+ usbd_cdc_acm_dif_num = if_num++;
+ desc_ptr += acm_cdc_desc_fill(&USBD_ConfigDescriptor[desc_ptr], &USBD_ConfigDescriptor_HS[desc_ptr], usbd_cdc_acm_cif_num);
+ USBD_CDC_ACM_Initialize();
+#endif
+
+#if (USBD_HID_ENABLE)
+ usbd_hid_if_num = if_num++;
+ desc_ptr += hid_desc_fill(&USBD_ConfigDescriptor[desc_ptr], &USBD_ConfigDescriptor_HS[desc_ptr], usbd_hid_if_num);
+ usbd_hid_init();
+#endif
+
+#if (USBD_WEBUSB_ENABLE)
+ usbd_webusb_if_num = if_num++;
+ desc_ptr += webusb_desc_fill(&USBD_ConfigDescriptor[desc_ptr], &USBD_ConfigDescriptor_HS[desc_ptr], usbd_webusb_if_num);
+#endif
+
+#if (USBD_BULK_ENABLE)
+ usbd_bulk_if_num = if_num++;
+ desc_ptr += bulk_desc_fill(&USBD_ConfigDescriptor[desc_ptr], &USBD_ConfigDescriptor_HS[desc_ptr], usbd_bulk_if_num);
+ usbd_bulk_init();
+#endif
+
+#if (USBD_CLS_ENABLE)
+ usbd_cls_init();
+#endif
+
+}
+
+#endif //USBD_ENABLE
+
+#endif /* __USB_CONFIG__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/usb_lib.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/usb/usb_lib.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,132 @@ +/** + * @file usb_lib.h + * @brief USB library header + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __USB_LIB_H__ +#define __USB_LIB_H__ + +/*------------------------------------------------------------------------------ + * USB Device Configuration + *----------------------------------------------------------------------------*/ +extern U8 USBD_AltSetting[]; +extern U8 USBD_EP0Buf[]; +extern const U8 usbd_power; +extern const U8 usbd_hs_enable; +extern const U8 usbd_bos_enable; +extern const U16 usbd_if_num; +extern const U8 usbd_ep_num; +extern const U8 usbd_max_packet0; + + +/*------------------------------------------------------------------------------ + * USB Device Class Configuration + *----------------------------------------------------------------------------*/ +extern const U8 usbd_hid_enable; +extern U8 usbd_hid_if_num; +extern U8 usbd_webusb_if_num; +extern const U8 usbd_hid_ep_intin; +extern const U8 usbd_hid_ep_intout; +extern const U16 usbd_hid_interval [2]; +extern const U16 usbd_hid_maxpacketsize[2]; +extern const U8 usbd_hid_inreport_num; +extern const U8 usbd_hid_outreport_num; +extern const U16 usbd_hid_inreport_max_sz; +extern const U16 usbd_hid_outreport_max_sz; +extern const U16 usbd_hid_featreport_max_sz; +extern U16 USBD_HID_PollingCnt; +extern U16 USBD_HID_PollingReload[]; +extern U8 USBD_HID_IdleCnt[]; +extern U8 USBD_HID_IdleReload[]; +extern U8 USBD_HID_IdleSet[]; +extern U8 USBD_HID_InReport[]; +extern U8 USBD_HID_OutReport[]; +extern U8 USBD_HID_FeatReport[]; + +extern const U8 usbd_msc_enable; +extern U8 usbd_msc_if_num; +extern const U8 usbd_msc_ep_bulkin; +extern const U8 usbd_msc_ep_bulkout; +extern const U16 usbd_msc_maxpacketsize[2]; +extern const U8 *usbd_msc_inquiry_data; +extern const U16 USBD_MSC_BulkBufSize; +extern U8 USBD_MSC_BulkBuf[]; + +extern const U8 usbd_adc_enable; +extern const U8 usbd_adc_cif_num; +extern const U8 usbd_adc_sif1_num; +extern const U8 usbd_adc_sif2_num; +extern const U8 usbd_adc_ep_isoout; +extern const U32 usbd_adc_cfg_datafreq; +extern const U32 usbd_adc_cfg_p_s; +extern const U32 usbd_adc_cfg_p_c; +extern const U32 usbd_adc_cfg_b_s; +extern S16 USBD_ADC_DataBuf[]; + +extern const U8 usbd_cdc_acm_enable; +extern U8 usbd_cdc_acm_cif_num; +extern U8 usbd_cdc_acm_dif_num; +extern const U8 usbd_cdc_acm_bufsize; +extern const U8 usbd_cdc_acm_ep_intin; +extern const U8 usbd_cdc_acm_ep_bulkin; +extern const U8 usbd_cdc_acm_ep_bulkout; +extern const U16 usbd_cdc_acm_sendbuf_sz; +extern const U16 usbd_cdc_acm_receivebuf_sz; +extern const U16 usbd_cdc_acm_maxpacketsize[2]; +extern const U16 usbd_cdc_acm_maxpacketsize1[2]; +extern U8 USBD_CDC_ACM_SendBuf[]; +extern U8 USBD_CDC_ACM_ReceiveBuf[]; +extern U8 USBD_CDC_ACM_NotifyBuf[10]; + +extern const U8 usbd_webusb_vendor_code; +extern const U8 usbd_winusb_vendor_code; + +extern const U8 usbd_bulk_enable; +extern U8 usbd_bulk_if_num; +extern const U8 usbd_bulk_ep_bulkin; +extern const U8 usbd_bulk_ep_bulkout; +extern const U16 usbd_bulk_maxpacketsize[2]; +extern const U16 USBD_Bulk_BulkBufSize; +extern U8 USBD_Bulk_BulkInBuf[]; +extern U8 USBD_Bulk_BulkOutBuf[]; + +extern void usbd_os_evt_set(U16 event_flags, U32 task); +extern U16 usbd_os_evt_get(void); +extern U32 usbd_os_evt_wait_or(U16 wait_flags, U16 timeout); + +extern const BOOL __rtx; + + +/*------------------------------------------------------------------------------ + * USB Device Descriptors + *----------------------------------------------------------------------------*/ +extern const U8 USBD_HID_ReportDescriptor[]; +extern const U16 USBD_HID_ReportDescriptorSize; +extern const U16 USBD_HID_DescriptorOffset; +extern const U8 USBD_DeviceDescriptor[]; +extern const U8 USBD_DeviceQualifier[]; +extern const U8 USBD_DeviceQualifier_HS[]; +extern U8 USBD_ConfigDescriptor[]; +extern U8 USBD_ConfigDescriptor_HS[]; +extern const U8 USBD_BinaryObjectStoreDescriptor[]; +extern const U8 USBD_StringDescriptor[]; +extern const U8 USBD_WebUSBURLDescriptor[]; +extern const U8 USBD_WinUSBDescriptorSetDescriptor[]; + +#endif /* __USB_LIB_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/usb_msc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/usb/usb_msc.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,113 @@
+/**
+ * @file usb_msc.h
+ * @brief USB mass storage header
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __USB_MSC_H__
+#define __USB_MSC_H__
+
+
+/* MSC Subclass Codes */
+#define MSC_SUBCLASS_RBC 0x01
+#define MSC_SUBCLASS_SFF8020I_MMC2 0x02
+#define MSC_SUBCLASS_QIC157 0x03
+#define MSC_SUBCLASS_UFI 0x04
+#define MSC_SUBCLASS_SFF8070I 0x05
+#define MSC_SUBCLASS_SCSI 0x06
+
+/* MSC Protocol Codes */
+#define MSC_PROTOCOL_CBI_INT 0x00
+#define MSC_PROTOCOL_CBI_NOINT 0x01
+#define MSC_PROTOCOL_BULK_ONLY 0x50
+
+
+/* MSC Request Codes */
+#define MSC_REQUEST_RESET 0xFF
+#define MSC_REQUEST_GET_MAX_LUN 0xFE
+
+
+/* MSC Bulk-only Stage */
+#define MSC_BS_CBW 0 /* Command Block Wrapper */
+#define MSC_BS_DATA_OUT 1 /* Data Out Phase */
+#define MSC_BS_DATA_IN 2 /* Data In Phase */
+#define MSC_BS_DATA_IN_LAST 3 /* Data In Last Phase */
+#define MSC_BS_DATA_IN_LAST_STALL 4 /* Data In Last Phase with Stall */
+#define MSC_BS_CSW 5 /* Command Status Wrapper */
+#define MSC_BS_ERROR 6 /* Error */
+#define MSC_BS_RESET 7 /* Bulk-Only Mass Storage Reset */
+
+
+/* Bulk-only Command Block Wrapper */
+typedef __packed struct _MSC_CBW {
+ U32 dSignature;
+ U32 dTag;
+ U32 dDataLength;
+ U8 bmFlags;
+ U8 bLUN;
+ U8 bCBLength;
+ U8 CB[16];
+} MSC_CBW;
+
+/* Bulk-only Command Status Wrapper */
+typedef __packed struct _MSC_CSW {
+ U32 dSignature;
+ U32 dTag;
+ U32 dDataResidue;
+ U8 bStatus;
+} MSC_CSW;
+
+#define MSC_CBW_Signature 0x43425355
+#define MSC_CSW_Signature 0x53425355
+
+
+/* CSW Status Definitions */
+#define CSW_CMD_PASSED 0x00
+#define CSW_CMD_FAILED 0x01
+#define CSW_PHASE_ERROR 0x02
+
+
+/* SCSI Commands */
+#define SCSI_TEST_UNIT_READY 0x00
+#define SCSI_REQUEST_SENSE 0x03
+#define SCSI_FORMAT_UNIT 0x04
+#define SCSI_INQUIRY 0x12
+#define SCSI_MODE_SELECT6 0x15
+#define SCSI_MODE_SENSE6 0x1A
+#define SCSI_START_STOP_UNIT 0x1B
+#define SCSI_MEDIA_REMOVAL 0x1E
+#define SCSI_READ_FORMAT_CAPACITIES 0x23
+#define SCSI_READ_CAPACITY 0x25
+#define SCSI_READ10 0x28
+#define SCSI_WRITE10 0x2A
+#define SCSI_VERIFY10 0x2F
+#define SCSI_SYNC_CACHE10 0x35
+#define SCSI_READ12 0xA8
+#define SCSI_WRITE12 0xAA
+#define SCSI_MODE_SELECT10 0x55
+#define SCSI_MODE_SENSE10 0x5A
+#define SCSI_SYNC_CACHE16 0x91
+#define SCSI_ATA_COMMAND_PASS_THROUGH12 0xA1
+#define SCSI_ATA_COMMAND_PASS_THROUGH16 0x85
+#define SCSI_SERVICE_ACTION_IN12 0xAB
+#define SCSI_SERVICE_ACTION_IN16 0x9E
+#define SCSI_SERVICE_ACTION_OUT12 0xA9
+#define SCSI_SERVICE_ACTION_OUT16 0x9F
+#define SCSI_REPORT_ID_INFO 0xA3
+
+#endif /* __USB_MSC_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/usb_webusb.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/usb/usb_webusb.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,62 @@
+/**
+ * @file usb_webusb.h
+ * @brief WebUSB driver header
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __USB_WEBUSB_H__
+#define __USB_WEBUSB_H__
+
+/* WebUSB Descriptor Types */
+#define WEBUSB_DESCRIPTOR_SET_HEADER_TYPE 0x00
+#define WEBUSB_CONFIGURATION_SUBSET_HEADER_TYPE 0x01
+#define WEBUSB_FUNCTION_SUBSET_HEADER_TYPE 0x02
+#define WEBUSB_URL_TYPE 0x03
+
+/* WebUSB Platform Capability Descriptor */
+typedef __packed struct _WEBUSB_PLATFORM_CAPABILITY_DESCRIPTOR {
+ U8 bLength;
+ U8 bDescriptorType;
+ U8 bDevCapabilityType;
+ U8 bReserved;
+ U8 platformCapabilityUUID[16];
+ U16 bcdVersion;
+ U8 bVendorCode;
+ U8 iLandingPage;
+} WEBUSB_PLATFORM_CAPABILITY_DESCRIPTOR;
+
+typedef __packed struct _WEBUSB_URL_DESCRIPTOR {
+ U8 bLength;
+ U8 bDescriptorType;
+ U8 bScheme;
+ char URL[];
+} WEBUSB_URL_DESCRIPTOR;
+
+/* WebUSB Request Codes */
+#define WEBUSB_REQUEST_GET_URL 0x02
+
+/* bScheme in URL descriptor */
+#define WEBUSB_URL_SCHEME_HTTP 0x00
+#define WEBUSB_URL_SCHEME_HTTPS 0x01
+
+/* WebUSB Descriptor sizes */
+#define WEBUSB_DESCRIPTOR_SET_HEADER_SIZE 5
+#define WEBUSB_CONFIGURATION_SUBSET_HEADER_SIZE 4
+#define WEBUSB_FUNCTION_SUBSET_HEADER_SIZE 3
+
+#endif /* __USB_WEBUSB_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/usb_winusb.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/usb/usb_winusb.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,68 @@
+/**
+ * @file usb_winusb.h
+ * @brief WinUSB driver header
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __USB_WINUSB_H__
+#define __USB_WINUSB_H__
+
+/* WinUSB Microsoft OS 2.0 Descriptor Types */
+#define WINUSB_SET_HEADER_DESCRIPTOR_TYPE 0x00
+#define WINUSB_SUBSET_HEADER_CONFIGURATION_TYPE 0x01
+#define WINUSB_SUBSET_HEADER_FUNCTION_TYPE 0x02
+#define WINUSB_FEATURE_COMPATIBLE_ID_TYPE 0x03
+#define WINUSB_FEATURE_REG_PROPERTY_TYPE 0x04
+#define WINUSB_FEATURE_MIN_RESUME_TIME_TYPE 0x05
+#define WINUSB_FEATURE_MODEL_ID_TYPE 0x06
+#define WINUSB_FEATURE_CCGP_DEVICE_TYPE 0x07
+
+
+#define WINUSB_PROP_DATA_TYPE_REG_SZ 0x01
+#define WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ 0x07
+
+/* WinUSB Microsoft OS 2.0 descriptor Platform Capability Descriptor */
+typedef __packed struct _WINUSB_PLATFORM_CAPABILITY_DESCRIPTOR {
+ U8 bLength;
+ U8 bDescriptorType;
+ U8 bDevCapabilityType;
+ U8 bReserved;
+ U8 platformCapabilityUUID[16];
+ U32 dwWindowsVersion;
+ U16 wDescriptorSetTotalLength;
+ U8 bVendorCode;
+ U8 bAltEnumCode;
+} WINUSB_PLATFORM_CAPABILITY_DESCRIPTOR;
+
+/* WinUSB Microsoft OS 2.0 descriptor set header */
+typedef __packed struct _WINUSB_DESCRIPTOR_SET_HEADER {
+ U16 wLength;
+ U16 wDescriptorType;
+ U32 dwWindowsVersion;
+ U16 wTotalLength;
+} WINUSB_DESCRIPTOR_SET_HEADER;
+
+/* WinUSB Microsoft OS 2.0 descriptor request codes */
+#define WINUSB_REQUEST_GET_DESCRIPTOR_SET 0x07
+#define WINUSB_REQUEST_SET_ALT_ENUM 0x08
+
+/* WinUSB Microsoft OS 2.0 descriptor sizes */
+#define WINUSB_DESCRIPTOR_SET_HEADER_SIZE 10
+#define WINUSB_FUNCTION_SUBSET_HEADER_SIZE 8
+#define WINUSB_FEATURE_COMPATIBLE_ID_SIZE 20
+#endif // __USB_WINUSB_H__
diff -r 000000000000 -r 01f31e923fe2 source/usb/usbd_cdc.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/usb/usbd_cdc.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,46 @@ +/** + * @file usbd_cdc.h + * @brief USB device CDC header + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __USBD_CDC_H__ +#define __USBD_CDC_H__ + + +/*--------------------------- Event handling routines ------------------------*/ + +extern void usbd_vcom_serial2usb(void); +extern void usbd_vcom_chkserstate(void); +extern void usbd_vcom_usb2serial(void); +extern void usbd_cdc_ser_flush(void); + +extern void USBD_CDC_SOF_Event(void); + +extern void USBD_CDC_EP_INTIN_Event(U32 event); +extern void USBD_CDC_EP_BULKIN_Event(U32 event); +extern void USBD_CDC_EP_BULKOUT_Event(U32 event); +extern void USBD_CDC_EP_BULK_Event(U32 event); + +extern void USBD_RTX_CDC_EP_INTIN_Event(void); +extern void USBD_RTX_CDC_EP_BULKIN_Event(void); +extern void USBD_RTX_CDC_EP_BULKOUT_Event(void); +extern void USBD_RTX_CDC_EP_BULK_Event(void); + + +#endif /* __USBD_CDC_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/usbd_cdc_acm.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/usb/usbd_cdc_acm.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,44 @@ +/** + * @file usbd_cdc_acm.h + * @brief USB CDC ACM header + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __USBD_CDC_ACM_H__ +#define __USBD_CDC_ACM_H__ + + +/*--------------------------- Event handling routines ------------------------*/ + +extern void USBD_CDC_ACM_Reset_Event(void); + +extern void USBD_CDC_ACM_SOF_Event(void); + +extern void USBD_CDC_ACM_EP_INTIN_Event(U32 event); +extern void USBD_CDC_ACM_EP_BULKIN_Event(U32 event); +extern void USBD_CDC_ACM_EP_BULKOUT_Event(U32 event); +extern void USBD_CDC_ACM_EP_BULK_Event(U32 event); + +#ifdef __RTX +extern void USBD_RTX_CDC_ACM_EP_INTIN_Event(void); +extern void USBD_RTX_CDC_ACM_EP_BULKIN_Event(void); +extern void USBD_RTX_CDC_ACM_EP_BULKOUT_Event(void); +extern void USBD_RTX_CDC_ACM_EP_BULK_Event(void); +#endif + +#endif /* __USBD_CDC_ACM_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/usbd_core.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/usb/usbd_core.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,1056 @@
+/**
+ * @file usbd_core.c
+ * @brief USB Device core
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+#include "rl_usb.h"
+#include "usb_for_lib.h"
+#include "info.h"
+
+U16 USBD_DeviceStatus;
+U8 USBD_DeviceAddress;
+U8 USBD_Configuration;
+U32 USBD_EndPointMask;
+U32 USBD_EndPointHalt;
+U32 USBD_EndPointStall; /* EP must stay stalled */
+U8 USBD_NumInterfaces;
+U8 USBD_HighSpeed;
+U8 USBD_ZLP;
+
+USBD_EP_DATA USBD_EP0Data;
+USB_SETUP_PACKET USBD_SetupPacket;
+
+#ifdef __RTX
+OS_TID USBD_RTX_DevTask; /* USB Device Task ID */
+OS_TID USBD_RTX_EPTask[16]; /* USB Endpoint Task ID's */
+OS_TID USBD_RTX_CoreTask; /* USB Core Task ID */
+#endif
+
+
+__asm void $$USBD$$version(void)
+{
+ /* Export a version number symbol for a version control. */
+ EXPORT __RL_USBD_VER
+__RL_USBD_VER EQU 0x470
+}
+
+
+/*
+ * Init USB Device Core and Hardware
+ * Parameters: None
+ * Return Value: None
+ */
+
+void usbd_init(void)
+{
+ USBD_HighSpeed = __FALSE;
+ usbd_class_init();
+ USBD_RTX_TaskInit();
+ USBD_Init();
+}
+
+
+/*
+ * USB Device Connect/Disconnect Function
+ * Called by the User to Connect/Disconnect USB Device
+ * Parameters: con: Connect/Disconnect
+ * Return Value: None
+ */
+
+void usbd_connect(BOOL con)
+{
+ USBD_Connect(con);
+}
+
+
+/*
+ * Reset USB Device Core
+ * Parameters: None
+ * Return Value: None
+ */
+
+void usbd_reset_core(void)
+{
+ USBD_DeviceStatus = usbd_power;
+ USBD_DeviceAddress = 0;
+ USBD_Configuration = 0;
+ USBD_EndPointMask = 0x00010001;
+ USBD_EndPointHalt = 0x00000000;
+ USBD_EndPointStall = 0x00000000;
+}
+
+
+/*
+ * USB Device Configured Function
+ * Called by the User to check id USB Device is configured
+ * Parameters:
+ * Return Value: Configurated state (FALSE = unconfigured, TRUE = configured)
+ */
+
+BOOL usbd_configured(void)
+{
+ if (USBD_Configuration) {
+ return (__TRUE);
+ }
+
+ return (__FALSE);
+}
+
+
+/*
+ * USB Device Request - Setup Stage
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_SetupStage(void)
+{
+ USBD_ReadEP(0x00, (U8 *)&USBD_SetupPacket, sizeof(USBD_SetupPacket));
+}
+
+
+/*
+ * USB Device Request - Data In Stage
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_DataInStage(void)
+{
+ U32 cnt;
+
+ if (USBD_EP0Data.Count > usbd_max_packet0) {
+ cnt = usbd_max_packet0;
+ } else {
+ cnt = USBD_EP0Data.Count;
+ }
+
+ if (!cnt) {
+ USBD_ZLP = 0;
+ }
+
+ cnt = USBD_WriteEP(0x80, USBD_EP0Data.pData, cnt);
+ USBD_EP0Data.pData += cnt;
+ USBD_EP0Data.Count -= cnt;
+}
+
+
+/*
+ * USB Device Request - Data Out Stage
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_DataOutStage(void)
+{
+ U32 cnt;
+ cnt = USBD_ReadEP(0x00, USBD_EP0Data.pData, USBD_EP0Data.Count);
+ USBD_EP0Data.pData += cnt;
+ USBD_EP0Data.Count -= cnt;
+}
+
+
+/*
+ * USB Device Request - Status In Stage
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_StatusInStage(void)
+{
+ USBD_WriteEP(0x80, NULL, 0);
+}
+
+
+/*
+ * USB Device Request - Status Out Stage
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USBD_StatusOutStage(void)
+{
+ USBD_ReadEP(0x00, USBD_EP0Buf, usbd_max_packet0);
+}
+
+
+/*
+ * Get Status USB Device Request
+ * Parameters: None
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+static inline BOOL USBD_ReqGetStatus(void)
+{
+ U32 n, m;
+
+ switch (USBD_SetupPacket.bmRequestType.Recipient) {
+ case REQUEST_TO_DEVICE:
+ USBD_EP0Data.pData = (U8 *)&USBD_DeviceStatus;
+ break;
+
+ case REQUEST_TO_INTERFACE:
+ if ((USBD_Configuration != 0) && (USBD_SetupPacket.wIndexL < USBD_NumInterfaces)) {
+ *((__packed U16 *)USBD_EP0Buf) = 0;
+ USBD_EP0Data.pData = USBD_EP0Buf;
+ } else {
+ return (__FALSE);
+ }
+
+ break;
+
+ case REQUEST_TO_ENDPOINT:
+ n = USBD_SetupPacket.wIndexL & 0x8F;
+ m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n);
+
+ if (((USBD_Configuration != 0) || ((n & 0x0F) == 0)) && (USBD_EndPointMask & m)) {
+ *((__packed U16 *)USBD_EP0Buf) = (USBD_EndPointHalt & m) ? 1 : 0;
+ USBD_EP0Data.pData = USBD_EP0Buf;
+ } else {
+ return (__FALSE);
+ }
+
+ break;
+
+ default:
+ return (__FALSE);
+ }
+
+ return (__TRUE);
+}
+
+
+/*
+ * Set/Clear Feature USB Device Request
+ * Parameters: sc: 0 - Clear, 1 - Set
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+static inline BOOL USBD_ReqSetClrFeature(U32 sc)
+{
+ U32 n, m;
+
+ switch (USBD_SetupPacket.bmRequestType.Recipient) {
+ case REQUEST_TO_DEVICE:
+ if (USBD_SetupPacket.wValue == USB_FEATURE_REMOTE_WAKEUP) {
+ if (sc) {
+ USBD_WakeUpCfg(__TRUE);
+ USBD_DeviceStatus |= USB_GETSTATUS_REMOTE_WAKEUP;
+ } else {
+ USBD_WakeUpCfg(__FALSE);
+ USBD_DeviceStatus &= ~USB_GETSTATUS_REMOTE_WAKEUP;
+ }
+ } else {
+ return (__FALSE);
+ }
+
+ break;
+
+ case REQUEST_TO_INTERFACE:
+ return (__FALSE);
+
+ case REQUEST_TO_ENDPOINT:
+ n = USBD_SetupPacket.wIndexL & 0x8F;
+ m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n);
+
+ if ((USBD_Configuration != 0) && ((n & 0x0F) != 0) && (USBD_EndPointMask & m)) {
+ if (USBD_SetupPacket.wValue == USB_FEATURE_ENDPOINT_STALL) {
+ if (sc) {
+ USBD_SetStallEP(n);
+ USBD_EndPointHalt |= m;
+ } else {
+ if ((USBD_EndPointStall & m) != 0) {
+ return (__TRUE);
+ }
+
+ USBD_ClrStallEP(n);
+ USBD_ReqClrFeature_MSC(n);
+ USBD_EndPointHalt &= ~m;
+ }
+ } else {
+ return (__FALSE);
+ }
+ } else {
+ return (__FALSE);
+ }
+
+ break;
+
+ default:
+ return (__FALSE);
+ }
+
+ return (__TRUE);
+}
+
+
+/*
+ * Set Address USB Device Request
+ * Parameters: None
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+static inline BOOL USBD_ReqSetAddress(void)
+{
+ switch (USBD_SetupPacket.bmRequestType.Recipient) {
+ case REQUEST_TO_DEVICE:
+ USBD_DeviceAddress = 0x80 | USBD_SetupPacket.wValueL;
+ break;
+
+ default:
+ return (__FALSE);
+ }
+
+ return (__TRUE);
+}
+
+
+/*
+ * Get Descriptor USB Device Request
+ * Parameters: None
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+static inline BOOL USBD_ReqGetDescriptor(void)
+{
+ U8 *pD;
+ U32 len, n;
+
+ switch (USBD_SetupPacket.bmRequestType.Recipient) {
+ case REQUEST_TO_DEVICE:
+ switch (USBD_SetupPacket.wValueH) {
+ case USB_DEVICE_DESCRIPTOR_TYPE:
+ USBD_EP0Data.pData = (U8 *)USBD_DeviceDescriptor;
+ len = USB_DEVICE_DESC_SIZE;
+ break;
+
+ case USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE:
+ if (!usbd_hs_enable) {
+ return (__FALSE); /* High speed not enabled */
+ }
+
+ if (USBD_HighSpeed == __FALSE) {
+ USBD_EP0Data.pData = (U8 *)USBD_DeviceQualifier;
+ } else {
+ USBD_EP0Data.pData = (U8 *)USBD_DeviceQualifier_HS;
+ }
+
+ len = USB_DEVICE_QUALI_SIZE;
+ break;
+
+ case USB_CONFIGURATION_DESCRIPTOR_TYPE:
+ if ((!usbd_hs_enable) && (USBD_HighSpeed == __TRUE)) {
+ return (__FALSE); /* High speed request but high-speed not enabled */
+ }
+
+ if (USBD_HighSpeed == __FALSE) {
+ pD = (U8 *)USBD_ConfigDescriptor;
+ ((USB_CONFIGURATION_DESCRIPTOR *)pD)->bDescriptorType = USB_CONFIGURATION_DESCRIPTOR_TYPE; //same descriptor is used in other configuration
+ } else {
+ pD = (U8 *)USBD_ConfigDescriptor_HS;
+ ((USB_CONFIGURATION_DESCRIPTOR *)pD)->bDescriptorType = USB_CONFIGURATION_DESCRIPTOR_TYPE; //same descriptor is used in other configuration
+ }
+
+ for (n = 0; n != USBD_SetupPacket.wValueL; n++) {
+ if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bLength != 0) {
+ pD += ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength;
+ }
+ }
+
+ if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bLength == 0) {
+ return (__FALSE);
+ }
+
+ USBD_EP0Data.pData = pD;
+ len = ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength;
+ break;
+
+ case USB_OTHER_SPEED_CONFIG_DESCRIPTOR_TYPE:
+ if (!usbd_hs_enable) {
+ return (__FALSE); /* High speed not enabled */
+ }
+
+ if (USBD_HighSpeed == __FALSE) {
+ pD = (U8 *)USBD_ConfigDescriptor_HS;
+ ((USB_CONFIGURATION_DESCRIPTOR *)pD)->bDescriptorType = USB_OTHER_SPEED_CONFIG_DESCRIPTOR_TYPE; //same descriptor is used in main configuration
+ } else {
+ pD = (U8 *)USBD_ConfigDescriptor;
+ ((USB_CONFIGURATION_DESCRIPTOR *)pD)->bDescriptorType = USB_OTHER_SPEED_CONFIG_DESCRIPTOR_TYPE; //same descriptor is used in main configuration
+ }
+
+ for (n = 0; n != USBD_SetupPacket.wValueL; n++) {
+ if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bLength != 0) {
+ pD += ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength;
+ }
+ }
+
+ if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bLength == 0) {
+ return (__FALSE);
+ }
+
+ USBD_EP0Data.pData = pD;
+ len = ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength;
+ break;
+
+ case USB_STRING_DESCRIPTOR_TYPE:
+ pD = (U8 *)USBD_StringDescriptor;
+
+ // added by sam to send unique id string descriptor
+ if (USBD_SetupPacket.wValueL == 3) {
+ USBD_EP0Data.pData = (uint8_t *)info_get_unique_id_string_descriptor();
+ len = ((USB_STRING_DESCRIPTOR *)USBD_EP0Data.pData)->bLength;
+ break;
+ }
+
+ for (n = 0; n != USBD_SetupPacket.wValueL; n++) {
+ if (((USB_STRING_DESCRIPTOR *)pD)->bLength != 0) {
+ pD += ((USB_STRING_DESCRIPTOR *)pD)->bLength;
+ }
+ }
+
+ if (((USB_STRING_DESCRIPTOR *)pD)->bLength == 0) {
+ return (__FALSE);
+ }
+
+ USBD_EP0Data.pData = pD;
+ len = ((USB_STRING_DESCRIPTOR *)pD)->bLength;
+ break;
+
+ case USB_BINARY_OBJECT_STORE_DESCRIPTOR_TYPE:
+ if (!usbd_bos_enable) {
+ return (__FALSE); /* High speed not enabled */
+ }
+
+ pD = (U8 *)USBD_BinaryObjectStoreDescriptor;
+ USBD_EP0Data.pData = pD;
+
+ if (((USB_BINARY_OBJECT_STORE_DESCRIPTOR *)pD)->bLength == 0) {
+ return (__FALSE);
+ }
+
+ len = ((USB_BINARY_OBJECT_STORE_DESCRIPTOR *)pD)->wTotalLength;
+ break;
+
+ default:
+ return (__FALSE);
+ }
+
+ break;
+
+ case REQUEST_TO_INTERFACE:
+ if (!USBD_ReqGetDescriptor_HID(&pD, &len)) {
+ return (__FALSE);
+ }
+
+ break;
+
+ default:
+ return (__FALSE);
+ }
+
+ if (USBD_EP0Data.Count > len) {
+ USBD_EP0Data.Count = len;
+
+ if (!(USBD_EP0Data.Count & (usbd_max_packet0 - 1))) {
+ USBD_ZLP = 1;
+ }
+ }
+
+ return (__TRUE);
+}
+
+
+/*
+ * Get Configuration USB Device Request
+ * Parameters: None
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+static inline BOOL USBD_ReqGetConfiguration(void)
+{
+ switch (USBD_SetupPacket.bmRequestType.Recipient) {
+ case REQUEST_TO_DEVICE:
+ USBD_EP0Data.pData = &USBD_Configuration;
+ break;
+
+ default:
+ return (__FALSE);
+ }
+
+ return (__TRUE);
+}
+
+
+/*
+ * Set Configuration USB Device Request
+ * Parameters: None
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+static inline BOOL USBD_ReqSetConfiguration(void)
+{
+ USB_CONFIGURATION_DESCRIPTOR *pD;
+ U32 alt = 0;
+ U32 n, m;
+
+ switch (USBD_SetupPacket.bmRequestType.Recipient) {
+ case REQUEST_TO_DEVICE:
+ if (USBD_SetupPacket.wValueL) {
+ if ((!usbd_hs_enable) && (USBD_HighSpeed == __TRUE)) {
+ return (__FALSE); /* High speed request but high-speed not enabled */
+ }
+
+ if (USBD_HighSpeed == __FALSE) {
+ pD = (USB_CONFIGURATION_DESCRIPTOR *)USBD_ConfigDescriptor;
+ } else {
+ pD = (USB_CONFIGURATION_DESCRIPTOR *)USBD_ConfigDescriptor_HS;
+ }
+
+ while (pD->bLength) {
+ switch (pD->bDescriptorType) {
+ case USB_CONFIGURATION_DESCRIPTOR_TYPE:
+ case USB_OTHER_SPEED_CONFIG_DESCRIPTOR_TYPE:
+ if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bConfigurationValue == USBD_SetupPacket.wValueL) {
+ USBD_Configuration = USBD_SetupPacket.wValueL;
+ USBD_NumInterfaces = ((USB_CONFIGURATION_DESCRIPTOR *)pD)->bNumInterfaces;
+
+ for (n = 0; n < usbd_if_num; n++) {
+ USBD_AltSetting[n] = 0;
+ }
+
+ for (n = 1; n < 16; n++) {
+ if (USBD_EndPointMask & (1 << n)) {
+ USBD_DisableEP(n);
+ }
+
+ if (USBD_EndPointMask & ((1 << 16) << n)) {
+ USBD_DisableEP(n | 0x80);
+ }
+ }
+
+ USBD_EndPointMask = 0x00010001;
+ USBD_EndPointHalt = 0x00000000;
+ USBD_EndPointStall = 0x00000000;
+ USBD_Configure(__TRUE);
+
+ if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bmAttributes & USB_CONFIG_POWERED_MASK) {
+ USBD_DeviceStatus |= USB_GETSTATUS_SELF_POWERED;
+ } else {
+ USBD_DeviceStatus &= ~USB_GETSTATUS_SELF_POWERED;
+ }
+ } else {
+ pD = (USB_CONFIGURATION_DESCRIPTOR *)((U8 *)pD + ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength);
+ continue;
+ }
+
+ break;
+
+ case USB_INTERFACE_DESCRIPTOR_TYPE:
+ alt = ((USB_INTERFACE_DESCRIPTOR *)pD)->bAlternateSetting;
+ break;
+
+ case USB_ENDPOINT_DESCRIPTOR_TYPE:
+ if (alt == 0) {
+ n = ((USB_ENDPOINT_DESCRIPTOR *)pD)->bEndpointAddress & 0x8F;
+ m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n);
+ USBD_EndPointMask |= m;
+ USBD_ConfigEP((void *)pD);
+ USBD_EnableEP(n);
+ USBD_ResetEP(n);
+ }
+
+ break;
+ }
+
+ pD = (USB_CONFIGURATION_DESCRIPTOR *)((U8 *)pD + pD->bLength);
+ }
+ } else {
+ USBD_Configuration = 0;
+
+ for (n = 1; n < 16; n++) {
+ if (USBD_EndPointMask & (1 << n)) {
+ USBD_DisableEP(n);
+ }
+
+ if (USBD_EndPointMask & ((1 << 16) << n)) {
+ USBD_DisableEP(n | 0x80);
+ }
+ }
+
+ USBD_EndPointMask = 0x00010001;
+ USBD_EndPointHalt = 0x00000000;
+ USBD_EndPointStall = 0x00000000;
+ USBD_Configure(__FALSE);
+ }
+
+ if (USBD_Configuration != USBD_SetupPacket.wValueL) {
+ return (__FALSE);
+ }
+
+ break;
+
+ default:
+ return (__FALSE);
+ }
+
+ return (__TRUE);
+}
+
+
+/*
+ * Get Interface USB Device Request
+ * Parameters: None
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+static inline BOOL USBD_ReqGetInterface(void)
+{
+ switch (USBD_SetupPacket.bmRequestType.Recipient) {
+ case REQUEST_TO_INTERFACE:
+ if ((USBD_Configuration != 0) && (USBD_SetupPacket.wIndexL < USBD_NumInterfaces)) {
+ USBD_EP0Data.pData = USBD_AltSetting + USBD_SetupPacket.wIndexL;
+ } else {
+ return (__FALSE);
+ }
+
+ break;
+
+ default:
+ return (__FALSE);
+ }
+
+ return (__TRUE);
+}
+
+
+/*
+ * Set Interface USB Device Request
+ * Parameters: None
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+static inline BOOL USBD_ReqSetInterface(void)
+{
+ USB_COMMON_DESCRIPTOR *pD;
+ U32 ifn = 0, alt = 0, old = 0, msk = 0;
+ U32 n, m;
+ BOOL set;
+
+ switch (USBD_SetupPacket.bmRequestType.Recipient) {
+ case REQUEST_TO_INTERFACE:
+ if (USBD_Configuration == 0) {
+ return (__FALSE);
+ }
+
+ set = __FALSE;
+
+ if ((!usbd_hs_enable) && (USBD_HighSpeed == __TRUE)) {
+ return (__FALSE); /* High speed request but high-speed not enabled */
+ }
+
+ if (USBD_HighSpeed == __FALSE) {
+ pD = (USB_COMMON_DESCRIPTOR *)USBD_ConfigDescriptor;
+ } else {
+ pD = (USB_COMMON_DESCRIPTOR *)USBD_ConfigDescriptor_HS;
+ }
+
+ while (pD->bLength) {
+ switch (pD->bDescriptorType) {
+ case USB_CONFIGURATION_DESCRIPTOR_TYPE:
+ case USB_OTHER_SPEED_CONFIG_DESCRIPTOR_TYPE:
+ if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bConfigurationValue != USBD_Configuration) {
+ pD = (USB_COMMON_DESCRIPTOR *)((U8 *)pD + ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength);
+ continue;
+ }
+
+ break;
+
+ case USB_INTERFACE_DESCRIPTOR_TYPE:
+ ifn = ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber;
+ alt = ((USB_INTERFACE_DESCRIPTOR *)pD)->bAlternateSetting;
+ msk = 0;
+
+ if ((ifn == USBD_SetupPacket.wIndexL) && (alt == USBD_SetupPacket.wValueL)) {
+ set = __TRUE;
+ old = USBD_AltSetting[ifn];
+ USBD_AltSetting[ifn] = (U8)alt;
+ }
+
+ break;
+
+ case USB_ENDPOINT_DESCRIPTOR_TYPE:
+ if (ifn == USBD_SetupPacket.wIndexL) {
+ n = ((USB_ENDPOINT_DESCRIPTOR *)pD)->bEndpointAddress & 0x8F;
+ m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n);
+
+ if (alt == USBD_SetupPacket.wValueL) {
+ USBD_EndPointMask |= m;
+ USBD_EndPointHalt &= ~m;
+ USBD_ConfigEP((USB_ENDPOINT_DESCRIPTOR *)pD);
+ USBD_EnableEP(n);
+ USBD_ResetEP(n);
+ msk |= m;
+ } else if ((alt == old) && ((msk & m) == 0)) {
+ USBD_EndPointMask &= ~m;
+ USBD_EndPointHalt &= ~m;
+ USBD_DisableEP(n);
+ }
+ }
+
+ break;
+ }
+
+ pD = (USB_COMMON_DESCRIPTOR *)((U8 *)pD + pD->bLength);
+ }
+
+ break;
+
+ default:
+ return (__FALSE);
+ }
+
+ return (set);
+}
+
+
+/*
+ * USB Device Endpoint 0 Event Callback
+ * Parameters: event
+ * Return Value: none
+ */
+
+void USBD_EndPoint0(U32 event)
+{
+ if (event & USBD_EVT_SETUP) {
+ USBD_SetupStage();
+ USBD_DirCtrlEP(USBD_SetupPacket.bmRequestType.Dir);
+ USBD_EP0Data.Count = USBD_SetupPacket.wLength; /* Number of bytes to transfer */
+
+ switch (USBD_SetupPacket.bmRequestType.Type) {
+ case REQUEST_STANDARD:
+ switch (USBD_SetupPacket.bRequest) {
+ case USB_REQUEST_GET_STATUS:
+ if (!USBD_ReqGetStatus()) {
+ goto stall;
+ }
+
+ USBD_DataInStage();
+ break;
+
+ case USB_REQUEST_CLEAR_FEATURE:
+ if (!USBD_ReqSetClrFeature(0)) {
+ goto stall;
+ }
+
+ USBD_StatusInStage();
+#ifdef __RTX
+
+ if (__rtx) {
+ if (USBD_RTX_CoreTask) {
+ usbd_os_evt_set(USBD_EVT_CLR_FEATURE, USBD_RTX_CoreTask);
+ }
+ } else {
+#endif
+
+ if (USBD_P_Feature_Event) {
+ USBD_P_Feature_Event();
+ }
+
+#ifdef __RTX
+ }
+
+#endif
+ break;
+
+ case USB_REQUEST_SET_FEATURE:
+ if (!USBD_ReqSetClrFeature(1)) {
+ goto stall;
+ }
+
+ USBD_StatusInStage();
+#ifdef __RTX
+
+ if (__rtx) {
+ if (USBD_RTX_CoreTask) {
+ usbd_os_evt_set(USBD_EVT_SET_FEATURE, USBD_RTX_CoreTask);
+ }
+ } else {
+#endif
+
+ if (USBD_P_Feature_Event) {
+ USBD_P_Feature_Event();
+ }
+
+#ifdef __RTX
+ }
+
+#endif
+ break;
+
+ case USB_REQUEST_SET_ADDRESS:
+ if (!USBD_ReqSetAddress()) {
+ goto stall;
+ }
+
+ USBD_SetAddress(USBD_DeviceAddress & 0x7F, 1);
+ USBD_StatusInStage();
+ break;
+
+ case USB_REQUEST_GET_DESCRIPTOR:
+ if (!USBD_ReqGetDescriptor()) {
+ goto stall;
+ }
+
+ USBD_DataInStage();
+ break;
+
+ case USB_REQUEST_SET_DESCRIPTOR:
+ goto stall;
+
+ case USB_REQUEST_GET_CONFIGURATION:
+ if (!USBD_ReqGetConfiguration()) {
+ goto stall;
+ }
+
+ USBD_DataInStage();
+ break;
+
+ case USB_REQUEST_SET_CONFIGURATION:
+ if (!USBD_ReqSetConfiguration()) {
+ goto stall;
+ }
+
+ USBD_StatusInStage();
+#ifdef __RTX
+
+ if (__rtx) {
+ if (USBD_RTX_CoreTask) {
+ usbd_os_evt_set(USBD_EVT_SET_CFG, USBD_RTX_CoreTask);
+ }
+ } else {
+#endif
+
+ if (USBD_P_Configure_Event) {
+ USBD_P_Configure_Event();
+ }
+
+#ifdef __RTX
+ }
+
+#endif
+ break;
+
+ case USB_REQUEST_GET_INTERFACE:
+ if (!USBD_ReqGetInterface()) {
+ goto stall;
+ }
+
+ USBD_DataInStage();
+ break;
+
+ case USB_REQUEST_SET_INTERFACE:
+ if (!USBD_ReqSetInterface()) {
+ goto stall;
+ }
+
+ USBD_StatusInStage();
+#ifdef __RTX
+
+ if (__rtx) {
+ if (USBD_RTX_CoreTask) {
+ usbd_os_evt_set(USBD_EVT_SET_IF, USBD_RTX_CoreTask);
+ }
+ } else {
+#endif
+
+ if (USBD_P_Interface_Event) {
+ USBD_P_Interface_Event();
+ }
+
+#ifdef __RTX
+ }
+
+#endif
+ break;
+
+ default:
+ goto stall;
+ }
+
+ break; /* end case REQUEST_STANDARD */
+
+ case REQUEST_CLASS:
+ switch (USBD_SetupPacket.bmRequestType.Recipient) {
+ case REQUEST_TO_DEVICE:
+ goto stall; /* not supported */
+
+ case REQUEST_TO_INTERFACE:
+ if (USBD_EndPoint0_Setup_HID_ReqToIF()) {
+ goto setup_class_ok;
+ }
+
+ if (USBD_EndPoint0_Setup_MSC_ReqToIF()) {
+ goto setup_class_ok;
+ }
+
+ if (USBD_EndPoint0_Setup_CDC_ReqToIF()) {
+ goto setup_class_ok;
+ }
+
+ goto stall; /* not supported */
+
+ /* end case REQUEST_TO_INTERFACE */
+
+ case REQUEST_TO_ENDPOINT:
+ goto stall;
+
+ /* end case REQUEST_TO_ENDPOINT */
+
+ default:
+ goto stall;
+ }
+
+setup_class_ok: /* request finished successfully */
+ break; /* end case REQUEST_CLASS */
+
+ case REQUEST_VENDOR:
+ switch (USBD_SetupPacket.bmRequestType.Recipient) {
+ case REQUEST_TO_DEVICE:
+ if (USBD_EndPoint0_Setup_WebUSB_ReqToDevice()) {
+ goto setup_vendor_ok;
+ }
+
+ if (USBD_EndPoint0_Setup_WinUSB_ReqToDevice()) {
+ goto setup_vendor_ok;
+ }
+
+ goto stall;
+
+ default:
+ goto stall;
+ }
+setup_vendor_ok:
+ break; /* end case REQUEST_VENDOR */
+
+ default:
+stall:
+ if ((USBD_SetupPacket.bmRequestType.Dir == REQUEST_HOST_TO_DEVICE) &&
+ (USBD_SetupPacket.wLength != 0)) {
+ USBD_SetStallEP(0x00);
+ } else {
+ USBD_SetStallEP(0x80);
+ }
+
+ USBD_EP0Data.Count = 0;
+ break;
+ }
+ }
+
+ if (event & USBD_EVT_OUT) {
+ if (USBD_SetupPacket.bmRequestType.Dir == REQUEST_HOST_TO_DEVICE) {
+ if (USBD_EP0Data.Count) { /* still data to receive ? */
+ USBD_DataOutStage(); /* receive data */
+
+ if (USBD_EP0Data.Count == 0) { /* data complete ? */
+ switch (USBD_SetupPacket.bmRequestType.Type) {
+ case REQUEST_STANDARD:
+ goto stall_i; /* not supported */
+
+ case REQUEST_CLASS:
+ switch (USBD_SetupPacket.bmRequestType.Recipient) {
+ case REQUEST_TO_DEVICE:
+ goto stall_i; /* not supported */
+
+ case REQUEST_TO_INTERFACE:
+ if (USBD_EndPoint0_Out_HID_ReqToIF()) {
+ goto out_class_ok;
+ }
+
+ if (USBD_EndPoint0_Out_CDC_ReqToIF()) {
+ goto out_class_ok;
+ }
+
+ goto stall_i;
+
+ /* end case REQUEST_TO_INTERFACE */
+
+ case REQUEST_TO_ENDPOINT:
+ goto stall_i;
+
+ /* end case REQUEST_TO_ENDPOINT */
+
+ default:
+ goto stall_i;
+ }
+
+out_class_ok: /* request finished successfully */
+ break; /* end case REQUEST_CLASS */
+
+ default:
+stall_i:
+ USBD_SetStallEP(0x80);
+ USBD_EP0Data.Count = 0;
+ break;
+ }
+ }
+ }
+ } else {
+ USBD_StatusOutStage(); /* receive Acknowledge */
+ }
+ } /* end USBD_EVT_OUT */
+
+ if (event & USBD_EVT_IN) {
+ if (USBD_SetupPacket.bmRequestType.Dir == REQUEST_DEVICE_TO_HOST) {
+ if (USBD_EP0Data.Count || USBD_ZLP) {
+ USBD_DataInStage(); /* send data */
+ }
+ } else {
+ if (USBD_DeviceAddress & 0x80) {
+ USBD_DeviceAddress &= 0x7F;
+ USBD_SetAddress(USBD_DeviceAddress, 0);
+ }
+ }
+ } /* end USBD_EVT_IN */
+
+ if (event & USBD_EVT_OUT_STALL) {
+ USBD_ClrStallEP(0x00);
+ }
+
+ if (event & USBD_EVT_IN_STALL) {
+ USBD_ClrStallEP(0x80);
+ }
+}
+
+
+/*
+ * USB Device Endpoint 0 RTX Task
+ * Parameters: none
+ * Return Value: none
+ */
+
+#ifdef __RTX
+void USBD_RTX_EndPoint0(void)
+{
+ for (;;) {
+ usbd_os_evt_wait_or(0xFFFF, 0xFFFF);
+ USBD_EndPoint0(usbd_os_evt_get());
+ }
+}
+#endif
diff -r 000000000000 -r 01f31e923fe2 source/usb/usbd_core.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/usb/usbd_core.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,75 @@
+/**
+ * @file usbd_core.h
+ * @brief USB Device Core header
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __USBD_CORE_H__
+#define __USBD_CORE_H__
+
+
+/*--------------------------- Data structures --------------------------------*/
+
+/* USB Device Core Endpoint Data Structure */
+typedef struct _USBD_EP_DATA {
+ U8 *pData;
+ U16 Count;
+} USBD_EP_DATA;
+
+
+/*--------------------------- Global variables -------------------------------*/
+
+/* USB Device Core Global Variables */
+extern U16 USBD_DeviceStatus;
+extern U8 USBD_DeviceAddress;
+extern U8 USBD_Configuration;
+extern U32 USBD_EndPointMask;
+extern U32 USBD_EndPointHalt;
+extern U32 USBD_EndPointStall;
+extern U8 USBD_NumInterfaces;
+extern U8 USBD_HighSpeed;
+extern U8 USBD_ZLP;
+
+extern USBD_EP_DATA USBD_EP0Data;
+extern USB_SETUP_PACKET USBD_SetupPacket;
+
+#ifdef __RTX
+extern OS_TID USBD_RTX_DevTask;
+extern OS_TID USBD_RTX_EPTask[];
+extern OS_TID USBD_RTX_CoreTask;
+#endif
+
+/*--------------------------- Functions exported to class specific files -----*/
+
+extern void USBD_SetupStage(void);
+extern void USBD_DataInStage(void);
+extern void USBD_DataOutStage(void);
+extern void USBD_StatusInStage(void);
+extern void USBD_StatusOutStage(void);
+
+
+/*--------------------------- Event handling routines ------------------------*/
+
+extern void usbd_class_init(void);
+extern void USBD_EndPoint0(U32 event);
+
+#ifdef __RTX
+extern void USBD_RTX_EndPoint0(void);
+#endif
+
+#endif /* __USBD_CORE_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/usbd_core_cdc.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/usb/usbd_core_cdc.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,32 @@ +/** + * @file usbd_core_cdc.h + * @brief USB Device Core CDC header + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __USBD_CORE_CDC_H__ +#define __USBD_CORE_CDC_H__ + + +/*--------------------------- Core overridable class specific functions ------*/ + +extern BOOL USBD_EndPoint0_Setup_CDC_ReqToIF(void); +extern BOOL USBD_EndPoint0_Out_CDC_ReqToIF(void); + + +#endif /* __USBD_CORE_CDC_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/usbd_core_hid.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/usb/usbd_core_hid.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,33 @@ +/** + * @file usbd_core_hid.h + * @brief USB Device Core HID header + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __USBD_CORE_HID_H__ +#define __USBD_CORE_HID_H__ + + +/*--------------------------- Core overridable class specific functions ------*/ + +extern BOOL USBD_ReqGetDescriptor_HID(U8 **pD, U32 *len); +extern BOOL USBD_EndPoint0_Setup_HID_ReqToIF(void); +extern BOOL USBD_EndPoint0_Out_HID_ReqToIF(void); + + +#endif /* __USBD_CORE_HID_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/usbd_core_msc.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/usb/usbd_core_msc.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,33 @@ +/** + * @file usbd_core_msc.h + * @brief USB Device Core CDC header + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __USBD_CORE_MSC_H__ +#define __USBD_CORE_MSC_H__ + + +/*--------------------------- Core overridable class specific functions ------*/ + +extern void USBD_ReqClrFeature_MSC(U32 EPNum); +extern BOOL USBD_EndPoint0_Setup_MSC_ReqToIF(void); +extern BOOL USBD_EndPoint0_Out_MSC_ReqToIF(void); + + +#endif /* __USBD_CORE_MSC_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/usbd_core_webusb.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/usb/usbd_core_webusb.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,30 @@ +/** + * @file usbd_core_webusb.h + * @brief USB Device Core WebUSB header + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __USBD_CORE_WEBUSB_H__ +#define __USBD_CORE_WEBUSB_H__ + + +/*--------------------------- Core overridable vendor specific functions ------*/ + +extern BOOL USBD_EndPoint0_Setup_WebUSB_ReqToDevice(void); + +#endif /* __USBD_CORE_WEBUSB_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/usbd_core_winusb.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/usb/usbd_core_winusb.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,30 @@ +/** + * @file usbd_core_winusb.h + * @brief USB Device Core WinUSB header + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __USBD_CORE_WINUSB_H__ +#define __USBD_CORE_WINUSB_H__ + + +/*--------------------------- Core overridable vendor specific functions ------*/ + +extern BOOL USBD_EndPoint0_Setup_WinUSB_ReqToDevice(void); + +#endif /* __USBD_CORE_WINUSB_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/usbd_desc.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/usb/usbd_desc.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,37 @@ +/** + * @file usbd_desc.h + * @brief USB Device Descriptor header + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __USBD_DESC_H__ +#define __USBD_DESC_H__ + +#define WBVAL(x) (x & 0xFF),((x >> 8) & 0xFF) +#define B3VAL(x) (x & 0xFF),((x >> 8) & 0xFF),((x >> 16) & 0xFF) +#define USB_DEVICE_DESC_SIZE (sizeof(USB_DEVICE_DESCRIPTOR)) +#define USB_DEVICE_QUALI_SIZE (sizeof(USB_DEVICE_QUALIFIER_DESCRIPTOR)) +#define USB_CONFIGUARTION_DESC_SIZE (sizeof(USB_CONFIGURATION_DESCRIPTOR)) +#define USB_INTERFACE_ASSOC_DESC_SIZE (sizeof(USB_INTERFACE_ASSOCIATION_DESCRIPTOR)) +#define USB_INTERFACE_DESC_SIZE (sizeof(USB_INTERFACE_DESCRIPTOR)) +#define USB_ENDPOINT_DESC_SIZE (sizeof(USB_ENDPOINT_DESCRIPTOR)) +#define USB_BOS_DESC_SIZE (sizeof(USB_BINARY_OBJECT_STORE_DESCRIPTOR)) +#define USB_HID_DESC_SIZE (sizeof(HID_DESCRIPTOR)) +#define USB_HID_REPORT_DESC_SIZE (sizeof(USBD_HID_ReportDescriptor)) + +#endif /* __USBD_DESC_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/usbd_event.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/usb/usbd_event.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,77 @@ +/** + * @file usbd_event.h + * @brief USB Device Event header + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __USBD_EVENT_H__ +#define __USBD_EVENT_H__ + + +/* USB Device - Device Events */ +#define USBD_EVT_POWER_ON (1 << 0) /* USB Power On */ +#define USBD_EVT_POWER_OFF (1 << 1) /* USB Power Off */ +#define USBD_EVT_RESET (1 << 2) /* USB Bus Reset */ +#define USBD_EVT_WAKEUP (1 << 3) /* USB Remote Wakeup */ +#define USBD_EVT_SUSPEND (1 << 4) /* USB Suspend */ +#define USBD_EVT_RESUME (1 << 5) /* USB Resume */ +#define USBD_EVT_SOF (1 << 6) /* USB Start of Frame */ +#define USBD_EVT_ERROR (1 << 7) /* USB Error */ + +/* USB Device - Endpoint Events */ +#define USBD_EVT_SETUP (1 << 1) /* Setup Packet */ +#define USBD_EVT_OUT (1 << 2) /* OUT Packet */ +#define USBD_EVT_IN (1 << 3) /* IN Packet */ +#define USBD_EVT_OUT_NAK (1 << 4) /* OUT Packet - Not Acknowledged */ +#define USBD_EVT_IN_NAK (1 << 5) /* IN Packet - Not Acknowledged */ +#define USBD_EVT_OUT_STALL (1 << 6) /* OUT Packet - Stalled */ +#define USBD_EVT_IN_STALL (1 << 7) /* IN Packet - Stalled */ +#define USBD_EVT_OUT_DMA_EOT (1 << 8) /* DMA OUT EP - End of Transfer */ +#define USBD_EVT_IN_DMA_EOT (1 << 9) /* DMA IN EP - End of Transfer */ +#define USBD_EVT_OUT_DMA_NDR (1 << 10) /* DMA OUT EP - New Descriptor Request*/ +#define USBD_EVT_IN_DMA_NDR (1 << 11) /* DMA IN EP - New Descriptor Request*/ +#define USBD_EVT_OUT_DMA_ERR (1 << 12) /* DMA OUT EP - Error */ +#define USBD_EVT_IN_DMA_ERR (1 << 13) /* DMA IN EP - Error */ + +/* USB Device - Core Events */ +#define USBD_EVT_SET_CFG (1 << 0) /* Set Configuration */ +#define USBD_EVT_SET_IF (1 << 1) /* Set Interface */ +#define USBD_EVT_SET_FEATURE (1 << 2) /* Set Feature */ +#define USBD_EVT_CLR_FEATURE (1 << 3) /* Clear Feature */ + +/* USB Device - Device Events Callback Pointers */ +extern void (* const USBD_P_Power_Event)(BOOL power); +extern void (* const USBD_P_Reset_Event)(void); +extern void (* const USBD_P_Suspend_Event)(void); +extern void (* const USBD_P_Resume_Event)(void); +extern void (* const USBD_P_WakeUp_Event)(void); +extern void (* const USBD_P_SOF_Event)(void); +extern void (* const USBD_P_Error_Event)(U32 error); + +/* USB Device - Endpoint Events Callback Pointers */ +extern void (* const USBD_P_EP[16])(U32 event); + +/* USB Device - Core Events Callback Pointers */ +extern void (* const USBD_P_Configure_Event)(void); +extern void (* const USBD_P_Interface_Event)(void); +extern void (* const USBD_P_Feature_Event)(void); + +/* USB Device - RTX version RTX tasks initialization */ +extern void USBD_RTX_TaskInit(void); + +#endif /* __USBD_EVENT_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/usbd_hid.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/usb/usbd_hid.h Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,50 @@
+/**
+ * @file usbd_hid.h
+ * @brief USB Device HID header
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __USBD_HID_H__
+#define __USBD_HID_H__
+
+
+/*--------------------------- Global constants -------------------------------*/
+
+/* USB HID Class API enumerated constants */
+enum {
+ USBD_HID_REQ_EP_CTRL = 0, /* Request from control endpoint */
+ USBD_HID_REQ_EP_INT, /* Request from interrupt endpoint */
+ USBD_HID_REQ_PERIOD_UPDATE /* Request from periodic update */
+};
+
+
+/*--------------------------- Event handling routines ------------------------*/
+
+extern void USBD_HID_Configure_Event(void);
+extern void USBD_HID_SOF_Event(void);
+
+extern void USBD_HID_EP_INTIN_Event(U32 event);
+extern void USBD_HID_EP_INTOUT_Event(U32 event);
+extern void USBD_HID_EP_INT_Event(U32 event);
+#ifdef __RTX
+extern void USBD_RTX_HID_EP_INTIN_Event(void);
+extern void USBD_RTX_HID_EP_INTOUT_Event(void);
+extern void USBD_RTX_HID_EP_INT_Event(void);
+#endif
+
+#endif /* __USBD_HID_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/usbd_hw.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/usb/usbd_hw.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,51 @@ +/** + * @file usbd_hw.h + * @brief USB Device Hardware header + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __USBD_HW_H__ +#define __USBD_HW_H__ + + +/* USB Hardware Functions */ +extern void USBD_Init(void); +extern void USBD_Connect(BOOL con); +extern void USBD_Reset(void); +extern void USBD_Suspend(void); +extern void USBD_Resume(void); +extern void USBD_WakeUp(void); +extern void USBD_WakeUpCfg(BOOL cfg); +extern void USBD_SetAddress(U32 adr, U32 setup); +extern void USBD_Configure(BOOL cfg); +extern void USBD_ConfigEP(USB_ENDPOINT_DESCRIPTOR *pEPD); +extern void USBD_DirCtrlEP(U32 dir); +extern void USBD_EnableEP(U32 EPNum); +extern void USBD_DisableEP(U32 EPNum); +extern void USBD_ResetEP(U32 EPNum); +extern void USBD_SetStallEP(U32 EPNum); +extern void USBD_ClrStallEP(U32 EPNum); +extern void USBD_ClearEPBuf(U32 EPNum); +extern U32 USBD_ReadEP(U32 EPNum, U8 *pData, U32 cnt); +extern U32 USBD_WriteEP(U32 EPNum, U8 *pData, U32 cnt); +extern U32 USBD_GetFrame(void); +extern U32 USBD_GetError(void); +extern void USBD_SignalHandler(void); +extern void USBD_Handler(void); + +#endif /* __USBD_HW_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/usbd_lib_cdc.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/usb/usbd_lib_cdc.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,39 @@ +/** + * @file usbd_lib_cdc.h + * @brief USB Device CDC Library header + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __USBD_LIB_CDC_H__ +#define __USBD_LIB_CDC_H__ + + +/*--------------------------- USB Requests -----------------------------------*/ + +extern int32_t USBD_CDC_ACM_SendEncapsulatedCommand(void); +extern int32_t USBD_CDC_ACM_GetEncapsulatedResponse(void); +extern int32_t USBD_CDC_ACM_SetCommFeature(uint16_t feat); +extern int32_t USBD_CDC_ACM_GetCommFeature(uint16_t feat); +extern int32_t USBD_CDC_ACM_ClearCommFeature(uint16_t feat); +extern int32_t USBD_CDC_ACM_SetLineCoding(void); +extern int32_t USBD_CDC_ACM_GetLineCoding(void); +extern int32_t USBD_CDC_ACM_SetControlLineState(uint16_t ctrl_bmp); +extern int32_t USBD_CDC_ACM_SendBreak(uint16_t dur); + + +#endif /* __USBD_LIB_CDC_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/usbd_lib_hid.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/usb/usbd_lib_hid.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,36 @@ +/** + * @file usbd_lib_hid.h + * @brief USB Device HID Library header + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __USBD_LIB_HID_H__ +#define __USBD_LIB_HID_H__ + + +/*--------------------------- USB Requests -----------------------------------*/ + +extern BOOL USBD_HID_GetReport(void); +extern BOOL USBD_HID_SetReport(void); +extern BOOL USBD_HID_GetIdle(void); +extern BOOL USBD_HID_SetIdle(void); +extern BOOL USBD_HID_GetProtocol(void); +extern BOOL USBD_HID_SetProtocol(void); + + +#endif /* __USBD_LIB_HID_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/usbd_lib_msc.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/usb/usbd_lib_msc.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,35 @@ +/** + * @file usbd_lib_msc.h + * @brief USB Device MSC Library header + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __USBD_LIB_MSC_H__ +#define __USBD_LIB_MSC_H__ + + +/*--------------------------- USB Requests -----------------------------------*/ + +extern void USBD_MSC_ClrStallEP(U32 EPNum); +extern BOOL USBD_MSC_Reset(void); +extern BOOL USBD_MSC_GetMaxLUN(void); +extern void USBD_MSC_GetCBW(void); +extern void USBD_MSC_SetCSW(void); + + +#endif /* __USBD_LIB_MSC_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/usbd_msc.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/source/usb/usbd_msc.h Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,52 @@ +/** + * @file usbd_msc.h + * @brief USB Device MSC header + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __USBD_MSC_H__ +#define __USBD_MSC_H__ + + +/*--------------------------- Global variables -------------------------------*/ + +/* USB Device Mass Storage Device Class Global Variables */ +extern BOOL USBD_MSC_MediaReady; +extern BOOL USBD_MSC_ReadOnly; +extern U32 USBD_MSC_MemorySize; +extern U32 USBD_MSC_BlockSize; +extern U32 USBD_MSC_BlockGroup; +extern U32 USBD_MSC_BlockCount; +extern U8 *USBD_MSC_BlockBuf; + + +/*--------------------------- Event handling routines ------------------------*/ + +extern void USBD_MSC_Reset_Event(void); + +extern void USBD_MSC_EP_BULKIN_Event(U32 event); +extern void USBD_MSC_EP_BULKOUT_Event(U32 event); +extern void USBD_MSC_EP_BULK_Event(U32 event); + +#ifdef __RTX +extern void USBD_RTX_MSC_EP_BULKIN_Event(void); +extern void USBD_RTX_MSC_EP_BULKOUT_Event(void); +extern void USBD_RTX_MSC_EP_BULK_Event(void); +#endif + +#endif /* __USBD_MSC_H__ */
diff -r 000000000000 -r 01f31e923fe2 source/usb/webusb/usbd_core_webusb.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/usb/webusb/usbd_core_webusb.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,85 @@
+/**
+ * @file usbd_core_webusb.c
+ * @brief WebUSB Device driver
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+
+#include "rl_usb.h"
+#include "usb_for_lib.h"
+#include "info.h"
+
+/*
+ * USB Device Endpoint 0 Event Callback - WebUSB specific handling (Setup Request To Device)
+ * Parameters: none
+ * Return Value: TRUE - Setup vendor request ok, FALSE - Setup vendor request not supported
+ */
+
+__weak BOOL USBD_EndPoint0_Setup_WebUSB_ReqToDevice(void)
+{
+ U8 *pD;
+ U32 len, n;
+
+ BOOL success = (__FALSE);
+ if (USBD_SetupPacket.bRequest == usbd_webusb_vendor_code) { /* vendor code correct? */
+ switch (USBD_SetupPacket.wIndex) {
+ case WEBUSB_REQUEST_GET_URL:
+ pD = (U8 *)USBD_WebUSBURLDescriptor;
+ if (USBD_SetupPacket.wValueL == 0) {
+ success = (__FALSE);
+ break;
+ }
+
+ for (n = 0; n + 1 < USBD_SetupPacket.wValueL; n++) {
+ if (((WEBUSB_URL_DESCRIPTOR *)pD)->bLength != 0) {
+ pD += ((WEBUSB_URL_DESCRIPTOR *)pD)->bLength;
+ }
+ }
+
+ if (((WEBUSB_URL_DESCRIPTOR *)pD)->bLength == 0) {
+ success = (__FALSE);
+ break;
+ }
+ strcat(((WEBUSB_URL_DESCRIPTOR *)pD)->URL, info_get_board_id());
+ USBD_EP0Data.pData = pD;
+ len = ((WEBUSB_URL_DESCRIPTOR *)pD)->bLength;
+
+ success = (__TRUE);
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ if (success) {
+ if (len < USBD_SetupPacket.wLength) {
+ USBD_EP0Data.Count = len;
+ if (!(len & (usbd_max_packet0 - 1))) {
+ USBD_ZLP = 1;
+ }
+ } else {
+ USBD_EP0Data.Count = USBD_SetupPacket.wLength;
+ }
+
+ USBD_DataInStage();
+ }
+
+ return success;
+}
diff -r 000000000000 -r 01f31e923fe2 source/usb/winusb/usbd_core_winusb.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/source/usb/winusb/usbd_core_winusb.c Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,67 @@
+/**
+ * @file usbd_core_winusb.c
+ * @brief WinUSB Device driver
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <string.h>
+
+#include "rl_usb.h"
+#include "usb_for_lib.h"
+
+/*
+ * USB Device Endpoint 0 Event Callback - WinUSB specific handling (Setup Request To Device)
+ * Parameters: none
+ * Return Value: TRUE - Setup vendor request ok, FALSE - Setup vendor request not supported
+ */
+
+__weak BOOL USBD_EndPoint0_Setup_WinUSB_ReqToDevice(void)
+{
+ U8 *pD;
+ U32 len;
+
+ BOOL success = (__FALSE);
+ if (USBD_SetupPacket.bRequest == usbd_winusb_vendor_code) { /* vendor code correct? */
+ switch (USBD_SetupPacket.wIndex) {
+ case WINUSB_REQUEST_GET_DESCRIPTOR_SET:
+ pD = (U8 *)USBD_WinUSBDescriptorSetDescriptor;
+ USBD_EP0Data.pData = pD;
+ len = ((WINUSB_DESCRIPTOR_SET_HEADER *)pD)->wTotalLength;
+ success = (__TRUE);
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ if (success) {
+ if (len < USBD_SetupPacket.wLength) {
+ USBD_EP0Data.Count = len;
+ if (!(len & (usbd_max_packet0 - 1))) {
+ USBD_ZLP = 1;
+ }
+ } else {
+ USBD_EP0Data.Count = USBD_SetupPacket.wLength;
+ }
+
+ USBD_DataInStage();
+ }
+
+ return success;
+}
diff -r 000000000000 -r 01f31e923fe2 test/Acceptance Criteria.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/test/Acceptance Criteria.txt Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,27 @@ +Minimum Acceptance Criteria for a release of DAPLink interface firmware. + * All tests are pass/fail + +HIC Acceptance Test for DAPLink Firmware +The test suite should be ran on each of the following operating systems + * Operating Systems: + * Windows 7, 8.x, 10 + * Ubuntu Linux > 12.04 + * Mac OSX > 10.9 + +The test(s) validates the following functionallities: + * USB HID: CMSIS-DAP Debugging + * Keil validation (windows only) + * pyOCD basic_test.py + + * USB CDC: Terminal Echo and Break + * echo 1024 bytes + * break command for reset + + * USB MSD: drag-n-drop programming + * Chrome - latest + * Internet Explorer - latest + * Firefox - latest + * Safari - latest (Mac only) + * cp, copy, xcopy, mv commands (based on OS compatibility) + +
diff -r 000000000000 -r 01f31e923fe2 test/board.py --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/test/board.py Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,66 @@ +# +# DAPLink Interface Firmware +# Copyright (c) 2009-2016, ARM Limited, All Rights Reserved +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +from __future__ import absolute_import + + +class Board(object): + + def update_interface(self): + raise NotImplementedError() + + def update_bootloader(self): + raise NotImplementedError() + + def prepare_for_testing(self): + raise NotImplementedError() + + @property + def hw_msd_support(self): + """Set to True if the hardware supports mass storage""" + raise NotImplementedError() + + @property + def hw_cdc_support(self): + """Set to True if the hardware supports a serial port""" + raise NotImplementedError() + + @property + def hw_hid_support(self): + """Set to True if the hardware supports HID""" + raise NotImplementedError() + + @property + def mount_point(self): + """Mount point of the drive or None if no SW support""" + raise NotImplementedError() + + @property + def serial_port(self): + """Serial port string usable with pySerial or None if no SW support""" + raise NotImplementedError() + + @property + def board_id(self): + """The ID of this board type""" + raise NotImplementedError() + + @property + def unique_id(self): + """ID which uniquely identifies this board""" + raise NotImplementedError()
diff -r 000000000000 -r 01f31e923fe2 test/daplink_board.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/test/daplink_board.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,727 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+from __future__ import absolute_import
+
+import os
+import re
+import time
+import subprocess
+import sys
+import binascii
+import itertools
+import mbed_lstools
+import info
+import test_daplink
+from test_info import TestInfoStub, TestInfo
+from intelhex import IntelHex
+from pyocd.core.helpers import ConnectHelper
+
+FILE_IGNORE_PATTERN_LIST = [
+ re.compile("\\._\\.Trashes")
+]
+
+
+# This prevents the following error message from getting
+# displayed on windows if the mbed dismounts unexpectedly
+# during a transfer:
+# There is no disk in the drive. Please insert a disk into
+# drive \Device\<Harddiskx>\<rdrive>
+def disable_popup():
+ if sys.platform.startswith("win"):
+ # pylint: disable=invalid-name
+ import ctypes
+ SEM_FAILCRITICALERRORS = 1
+ GetErrorMode = \
+ ctypes.windll.kernel32.GetErrorMode # @UndefinedVariable
+ GetErrorMode.restype = ctypes.c_uint
+ GetErrorMode.argtypes = []
+ SetErrorMode = \
+ ctypes.windll.kernel32.SetErrorMode # @UndefinedVariable
+ SetErrorMode.restype = ctypes.c_uint
+ SetErrorMode.argtypes = [ctypes.c_uint]
+
+ err_mode = GetErrorMode()
+ err_mode |= SEM_FAILCRITICALERRORS
+ SetErrorMode(err_mode)
+
+disable_popup()
+
+
+def get_all_attached_daplink_boards():
+ all_boards = []
+ lstools = mbed_lstools.create()
+ mbed_list = lstools.list_mbeds()
+ for mbed in mbed_list:
+ unique_id = mbed['target_id']
+ board = DaplinkBoard(unique_id)
+ if board._mode is not None: #Valid daplink should have set this mode
+ all_boards.append(board)
+ else:
+ print("Warning: DAPLink tests cannot be done on board %s" % board.unique_id)
+ return all_boards
+
+
+def _unique_id_to_host_id(unique_id):
+ """Return the chip id unique to the daplink host procesor
+
+ Unique ID has the following fomat
+ Board ID - 4 bytes
+ Version - 4 bytes
+ Host ID - Everything else
+ """
+ return unique_id[8:8 + 32]
+
+
+def _get_board_endpoints(unique_id):
+ """Return a tuple of unique_id, serial_port, mount_point"""
+ lstools = mbed_lstools.create()
+ mbed_list = lstools.list_mbeds()
+
+ host_id = _unique_id_to_host_id(unique_id)
+ for mbed in mbed_list:
+ mbed_unique_id = mbed['target_id']
+ mbed_serial_port = mbed['serial_port']
+ mbed_mount_point = mbed['mount_point']
+ mbed_host_id = _unique_id_to_host_id(mbed_unique_id)
+ if mbed_host_id == host_id:
+ return mbed_unique_id, mbed_serial_port, mbed_mount_point
+ return None
+
+
+def _ranges(i):
+ for _, b in itertools.groupby(enumerate(i), lambda x_y: x_y[1] - x_y[0]):
+ b = list(b)
+ yield b[0][1], b[-1][1]
+
+
+def _parse_kvp_file(file_path, parent_test=None):
+ """Parse details.txt and return True if successful"""
+ test_info = None
+ kvp = {}
+ if parent_test is not None:
+ test_info = parent_test.create_subtest('parse_kvp_file')
+ line_format = re.compile("^([a-zA-Z0-9 ]+): +(.+)$")
+ if not os.path.isfile(file_path):
+ return kvp
+
+ with open(file_path, "r") as file_handle:
+ for line in file_handle:
+ if len(line) <= 0:
+ if test_info is not None:
+ test_info.failure("Empty line in %s" % file_path)
+ continue
+
+ if line[0] == '#':
+ # The line is a comment
+ continue
+
+ match = line_format.match(line)
+ if match is None:
+ if test_info is not None:
+ test_info.failure("Invalid line: %s" % line)
+ continue
+
+ key = match.group(1)
+ key = key.lower().replace(" ", "_")
+ value = match.group(2)
+ value = value.lower()
+ value = value.strip()
+ if key in kvp:
+ if test_info is not None:
+ test_info.failure("Duplicate key %s" % key)
+ continue
+ kvp[key] = value
+ return kvp
+
+
+def _compute_crc(hex_file_path):
+ # Read in hex file
+ new_hex_file = IntelHex()
+ new_hex_file.padding = 0xFF
+ new_hex_file.fromfile(hex_file_path, format='hex')
+
+ # Get the starting and ending address
+ addresses = new_hex_file.addresses()
+ addresses.sort()
+ start_end_pairs = list(_ranges(addresses))
+ regions = len(start_end_pairs)
+ assert regions == 1, ("Error - only 1 region allowed in "
+ "hex file %i found." % regions)
+ start, end = start_end_pairs[0]
+
+ # Compute checksum over the range (don't include data at location of crc)
+ size = end - start + 1
+ crc_size = size - 4
+ data = new_hex_file.tobinarray(start=start, size=crc_size)
+ data_crc32 = binascii.crc32(data) & 0xFFFFFFFF
+
+ # Grab the crc from the image
+ embedded_crc32 = (((new_hex_file[end - 3] & 0xFF) << 0) |
+ ((new_hex_file[end - 2] & 0xFF) << 8) |
+ ((new_hex_file[end - 1] & 0xFF) << 16) |
+ ((new_hex_file[end - 0] & 0xFF) << 24))
+ return data_crc32, embedded_crc32
+
+
+def _run_chkdsk(drive):
+ args = ["chkdsk", drive]
+ process = subprocess.Popen(args, stdin=subprocess.PIPE,
+ stdout=subprocess.PIPE,
+ stderr=subprocess.PIPE)
+ process.communicate(input=bytearray('n\r\n',encoding='ascii')) # Answer no if prompted
+ process.wait()
+ return process.returncode
+
+
+class AssertInfo(object):
+
+ def __init__(self, file_name, line_number):
+ self._file = file_name
+ self._line = line_number
+
+ @property
+ def file(self):
+ return self._file
+
+ @property
+ def line(self):
+ return self._line
+
+
+class DaplinkBoard(object):
+
+ MODE_IF = "interface"
+ MODE_BL = "bootloader"
+
+ # Keys for details.txt
+ KEY_UNIQUE_ID = "unique_id"
+ KEY_HIC_ID = "hic_id"
+ KEY_MODE = "daplink_mode"
+ KEY_BL_VERSION = "bootloader_version"
+ KEY_IF_VERSION = "interface_version"
+ KEY_GIT_SHA = "git_sha"
+ KEY_LOCAL_MODS = "local_mods"
+ KEY_USB_INTERFACES = "usb_interfaces"
+ KEY_BL_CRC = "bootloader_crc"
+ KEY_IF_CRC = "interface_crc"
+ KEY_REMOUNT_COUNT = "remount_count"
+
+ def __init__(self, unique_id):
+
+ self.unique_id = unique_id
+ self.details_txt = None
+ self._mode = None
+ self._remount_count = None
+ self._assert = None
+ self._check_fs_on_remount = False
+ self._manage_assert = False
+ self.update_board_info()
+
+ def __str__(self):
+ return "Name=%s Unique ID=%s" % (self.name, self.get_unique_id())
+
+ def get_unique_id(self):
+ return self.unique_id
+
+ def get_board_id(self):
+ return self.board_id
+
+ @property
+ def hic_id(self):
+ return self._hic_id
+
+ @property
+ def name(self):
+ if self.board_id in info.BOARD_ID_TO_BUILD_TARGET:
+ board_target = info.BOARD_ID_TO_BUILD_TARGET[self.board_id]
+ else:
+ board_target = "Unknown"
+ return board_target
+
+ def get_serial_port(self):
+ return self.serial_port
+
+ def get_mount_point(self):
+ return self.mount_point
+
+ def get_connected(self):
+ """Check if the board is connected"""
+ return os.path.isdir(self.mount_point)
+
+ def get_failure_message_and_type(self):
+ """Get the failure message and types from fail.txt
+
+ return None if there there is no failure
+ """
+ error = None
+ error_type = None
+ fail_file = self.get_file_path('FAIL.TXT')
+ if not self.get_connected():
+ raise Exception('Board not connected')
+ if os.path.isfile(fail_file):
+ with open(fail_file, 'r') as fail_file_handle:
+ msg = fail_file_handle.read()
+ lines = msg.splitlines()
+ if len(lines) == 2:
+ if lines[0].startswith('error: '):
+ error = lines[0][7:]
+ else:
+ raise Exception('Can not parse error line in FAIL.TXT')
+ if lines[1].startswith('type: '):
+ error_type = lines[1][6:]
+ else:
+ raise Exception('Can not parse type line in FAIL.TXT')
+ else:
+ raise Exception('Wrong number of lines in FAIL.TXT, expected: 2')
+ return error, error_type
+
+ def get_assert_info(self):
+ """Return an AssertInfo if an assert occurred, else None"""
+ return self._assert
+
+ def get_mode(self):
+ """Return either MODE_IF or MODE_BL"""
+ assert ((self._mode is DaplinkBoard.MODE_BL) or
+ (self._mode is DaplinkBoard.MODE_IF))
+ return self._mode
+
+ def get_file_path(self, file_name):
+ """Convenience function to the path to a file on the drive"""
+ return os.path.normpath(self.mount_point + os.sep + file_name)
+
+ def refresh(self, parent_test):
+ """Remount driver to get updated contents"""
+ refresh_filename = self.get_file_path('REFRESH.ACT')
+ with open(refresh_filename, 'wb') as _:
+ pass
+ self.wait_for_remount(parent_test)
+
+ def set_mode(self, mode, parent_test=None):
+ """Set the mode to either MODE_IF or MODE_BL"""
+ assert ((mode is DaplinkBoard.MODE_BL) or
+ (mode is DaplinkBoard.MODE_IF))
+ if parent_test is None:
+ parent_test = TestInfoStub()
+ test_info = parent_test.create_subtest('set_mode')
+ current_mode = self.get_mode()
+ if current_mode is mode:
+ # No mode change needed
+ return
+
+ if mode is self.MODE_BL:
+ test_info.info("changing mode IF -> BL")
+ # Create file to enter BL mode
+ start_bl_path = self.get_file_path('START_BL.ACT')
+ with open(start_bl_path, 'wb') as _: pass
+ elif mode is self.MODE_IF:
+ test_info.info("changing mode BL -> IF")
+ # Create file to enter IF mode
+ start_if_path = self.get_file_path('START_IF.ACT')
+ with open(start_if_path, 'wb') as _: pass
+ else:
+ test_info.warning("Board is in unknown mode")
+ self.wait_for_remount(test_info)
+
+ new_mode = self.get_mode()
+ if new_mode != mode:
+ test_info.failure("Board in wrong mode: %s" % new_mode)
+ raise Exception("Could not change board mode")
+
+ def set_check_fs_on_remount(self, enabled):
+ assert isinstance(enabled, bool)
+ self._check_fs_on_remount = enabled
+ self.set_assert_auto_manage(enabled)
+
+ def set_assert_auto_manage(self, enabled):
+ assert isinstance(enabled, bool)
+ self.clear_assert()
+ self._manage_assert = enabled
+
+ def clear_assert(self):
+ assert_path = self.get_file_path("ASSERT.TXT")
+ if os.path.isfile(assert_path):
+ os.remove(assert_path)
+ self.wait_for_remount(TestInfoStub())
+
+ def run_board_test(self, parent_test):
+ test_daplink.daplink_test(self, parent_test)
+
+ def read_target_memory(self, addr, size, resume=True):
+ assert self.get_mode() == self.MODE_IF
+ with ConnectHelper.session_with_chosen_probe(unique_id=self.get_unique_id(),
+ resume_on_disconnect=resume) as session:
+ data = session.target.read_memory_block8(addr, size)
+ return bytearray(data)
+
+ def test_fs(self, parent_test):
+ """Check if the raw filesystem is valid"""
+ if sys.platform.startswith("win"):
+ test_info = parent_test.create_subtest('test_fs')
+ returncode = _run_chkdsk(self.mount_point)
+ test_info.info('chkdsk returned %s' % returncode)
+ if returncode != 0:
+ test_info.failure('Disk corrupt')
+
+ # Windows 8/10 workaround - rerun chkdsk until disk caching is on
+ # Notes about this problem:
+ # - This is less likely to occur when the "storage" service is
+ # turned off and/or you are running as administrator
+ # - When creating a directory with os.mkdir the
+ # following error occurs: "WindowsError: [Error 1392] The
+ # file or directory is corrupted and unreadable: '<directory>'"
+ # - When creating a file with open(<filename>, "wb") the
+ # following error occurs: "OError: [Errno 22] invalid
+ # mode ('wb') or filename: '<filename>'"
+ # - When a file or directory is created on the drive in explorer
+ # and you preform a refresh, the newly created file or
+ # directory disappears
+ persist_test_dir = self.get_file_path("persist_test_dir")
+ for _ in range(10):
+ try:
+ os.mkdir(persist_test_dir)
+ except EnvironmentError as exception:
+ test_info.info("cache check exception %s" % exception)
+ if os.path.exists(persist_test_dir):
+ os.rmdir(persist_test_dir)
+ break
+ test_info.info("running checkdisk to re-enable caching")
+ _run_chkdsk(self.mount_point)
+ else:
+ raise Exception("Unable to re-enable caching")
+
+ # TODO - as a future improvement add linux and mac support
+
+ # Tests for the following:
+ # 1. Correct files present -TODO
+ # 2. Contents of file are valid ascii
+ # 3. Each line ends with \r\n
+ # 4. There is no whitespace at the end of the line
+ # 5. Each file ends with \r\n
+ def test_fs_contents(self, parent_test):
+ """Check if the file contents are valid"""
+ test_info = parent_test.create_subtest('test_fs_contents')
+ non_ascii = b'[^\x20-\x7F\r\n]'
+ non_cr_lf = b'\r[^\n]|[^\r]\n'
+ trail_white = b'(?:\ \r|\ \n)'
+ end_of_file = b'\r\n$'
+ files = os.listdir(self.mount_point)
+ non_ascii_re = re.compile(non_ascii)
+ non_cr_lf_re = re.compile(non_cr_lf)
+ trail_white_re = re.compile(trail_white)
+ end_of_file_re = re.compile(end_of_file)
+ for filename in files:
+ filepath = self.get_file_path(filename)
+ if not os.path.isfile(filepath):
+ test_info.info("Skipping non file item %s" % filepath)
+ continue
+ skip = False
+ for pattern in FILE_IGNORE_PATTERN_LIST:
+ if pattern.match(filename):
+ skip = True
+ break
+ if skip:
+ continue
+
+ with open(filepath, 'rb') as file_handle:
+ file_contents = file_handle.read()
+ if non_ascii_re.search(file_contents):
+ test_info.failure("Non ascii characters in %s" % filepath)
+ elif non_cr_lf_re.search(file_contents):
+ test_info.failure("File has non-standard line endings %s" %
+ filepath)
+ elif trail_white_re.search(file_contents):
+ test_info.warning("File trailing whitespace %s" %
+ filepath)
+ elif end_of_file_re.search(file_contents) is None:
+ test_info.warning("No newline at end of file %s" %
+ filepath)
+ else:
+ test_info.info("File %s valid" % filepath)
+
+ self.test_details_txt(test_info)
+
+ def load_interface(self, filepath, parent_test):
+ """Load an interface binary or hex"""
+ assert isinstance(filepath, str), "Invalid bootloader image!"
+ assert isinstance(parent_test, TestInfo), "Invalid parent test object!"
+
+ test_info = parent_test.create_subtest('load_interface')
+ self.set_mode(self.MODE_BL, test_info)
+
+ data_crc, crc_in_image = _compute_crc(filepath)
+ assert data_crc == crc_in_image, ("CRC in interface is wrong "
+ "expected 0x%x, found 0x%x" %
+ (data_crc, crc_in_image))
+
+ filename = os.path.basename(filepath)
+ with open(filepath, 'rb') as firmware_file:
+ data = firmware_file.read()
+ out_file = self.get_file_path(filename)
+ start = time.time()
+ with open(out_file, 'wb') as firmware_file:
+ firmware_file.write(data)
+ stop = time.time()
+ test_info.info("programming took %s s" % (stop - start))
+ self.wait_for_remount(test_info)
+
+ # Check the CRC
+ self.set_mode(self.MODE_IF, test_info)
+ if DaplinkBoard.KEY_IF_CRC not in self.details_txt:
+ test_info.failure("No interface CRC in details.txt")
+ return
+ details_crc = int(self.details_txt[DaplinkBoard.KEY_IF_CRC], 0)
+ test_info.info("Interface crc: 0x%x" % details_crc)
+ if data_crc != details_crc:
+ test_info.failure("Interface CRC is wrong")
+
+ def load_bootloader(self, filepath, parent_test):
+ """Load a bootloader binary or hex"""
+ assert isinstance(filepath, str), "Invalid bootloader image!"
+ assert isinstance(parent_test, TestInfo), "Invalid parent test object!"
+
+ test_info = parent_test.create_subtest('load_bootloader')
+ self.set_mode(self.MODE_IF, test_info)
+
+ # Check image CRC
+ data_crc, crc_in_image = _compute_crc(filepath)
+ assert data_crc == crc_in_image, ("CRC in bootloader is wrong "
+ "expected 0x%x, found 0x%x" %
+ (data_crc, crc_in_image))
+
+ filename = os.path.basename(filepath)
+ with open(filepath, 'rb') as firmware_file:
+ data = firmware_file.read()
+ out_file = self.get_file_path(filename)
+ start = time.time()
+ with open(out_file, 'wb') as firmware_file:
+ firmware_file.write(data)
+ stop = time.time()
+ test_info.info("programming took %s s" % (stop - start))
+ self.wait_for_remount(test_info)
+
+ # Check the CRC
+ self.set_mode(self.MODE_IF, test_info)
+ if DaplinkBoard.KEY_BL_CRC not in self.details_txt:
+ test_info.failure("No bootloader CRC in details.txt")
+ return
+ details_crc = int(self.details_txt[DaplinkBoard.KEY_BL_CRC], 0)
+ test_info.info("Bootloader crc: 0x%x" % details_crc)
+ if data_crc != details_crc:
+ test_info.failure("Bootloader CRC is wrong")
+
+ def wait_for_remount(self, parent_test, wait_time=600):
+ mode = self._mode
+ count = self._remount_count
+ test_info = parent_test.create_subtest('wait_for_remount')
+
+ elapsed = 0
+ start = time.time()
+ remounted = False
+ while os.path.isdir(self.mount_point):
+ if self.update_board_info(False): #check info if it is already mounted
+ if mode is not None and self._mode is not None and mode is not self._mode:
+ remounted = True
+ test_info.info("already remounted with change mode")
+ break
+ elif count is not None and self._remount_count is not None and count != self._remount_count:
+ remounted = True
+ test_info.info("already remounted with change mount count")
+ break
+ if elapsed > wait_time:
+ raise Exception("Dismount timed out")
+ time.sleep(0.1)
+ elapsed += 0.2
+ else:
+ stop = time.time()
+ test_info.info("unmount took %s s" % (stop - start))
+ elapsed = 0
+ start = time.time()
+
+ while not remounted:
+ if self.update_board_info(False):
+ if os.path.isdir(self.mount_point):
+ # Information returned by mbed-ls could be old.
+ # Only break from the loop if the second call to
+ # mbed-ls returns the same mount point.
+ tmp_mount = self.mount_point
+ if self.update_board_info(False):
+ if tmp_mount == self.mount_point:
+ break
+ if elapsed > wait_time:
+ raise Exception("Mount timed out")
+ time.sleep(0.1)
+ elapsed += 0.1
+ stop = time.time()
+ test_info.info("mount took %s s" % (stop - start))
+
+ if count is not None and self._remount_count is not None:
+ expected_count = (0 if mode is not self._mode
+ else (count + 1) & 0xFFFFFFFF)
+ if expected_count != self._remount_count:
+ test_info.failure('Expected remount count of %s got %s' %
+ (expected_count, self._remount_count))
+
+ # If enabled check the filesystem
+ if self._check_fs_on_remount:
+ self.test_fs(parent_test)
+ self.test_fs_contents(parent_test)
+ self.test_details_txt(parent_test)
+ if self._manage_assert:
+ if self._assert is not None:
+ test_info.failure('Assert on line %s in file %s' %
+ (self._assert.line, self._assert.file))
+ self.clear_assert()
+
+ def update_board_info(self, exptn_on_fail=True):
+ """Update board info
+
+ Update all board information variables that could
+ change when remounting or changing modes.
+ Note - before this function is set self.unique_id
+ must be set.
+ """
+
+ try:
+ endpoints = _get_board_endpoints(self.unique_id)
+ if endpoints is None:
+ if exptn_on_fail:
+ raise Exception("Could not update board info: %s" %
+ self.unique_id)
+ return False
+ self.unique_id, self.serial_port, self.mount_point = endpoints
+ # Serial port can be missing
+ if self.unique_id is None:
+ if exptn_on_fail:
+ raise Exception("Mount point is null")
+ return False
+ if self.mount_point is None:
+ if exptn_on_fail:
+ raise Exception("Mount point is null")
+ return False
+ self.board_id = int(self.unique_id[0:4], 16)
+ self._hic_id = int(self.unique_id[-8:], 16)
+
+ # Note - Some legacy boards might not have details.txt
+ details_txt_path = self.get_file_path("details.txt")
+ self.details_txt = _parse_kvp_file(details_txt_path)
+ self._parse_assert_txt()
+
+ self._remount_count = None
+ if DaplinkBoard.KEY_REMOUNT_COUNT in self.details_txt:
+ self._remount_count = int(self.details_txt[DaplinkBoard.KEY_REMOUNT_COUNT])
+ self._mode = None
+ if DaplinkBoard.KEY_MODE in self.details_txt:
+ DETAILS_TO_MODE = {
+ "interface": DaplinkBoard.MODE_IF,
+ "bootloader": DaplinkBoard.MODE_BL,
+ }
+ mode_str = self.details_txt[DaplinkBoard.KEY_MODE]
+ self._mode = DETAILS_TO_MODE[mode_str]
+ else:
+ #check for race condition here
+ return False
+ return True
+ except Exception as e:
+ if exptn_on_fail:
+ raise e
+ else:
+ return False
+
+ def test_details_txt(self, parent_test):
+ """Check that details.txt has all requied fields"""
+ test_info = parent_test.create_subtest('test_details_txt')
+ required_key_and_format = {
+ DaplinkBoard.KEY_UNIQUE_ID: re.compile("^[a-f0-9]{48}$"),
+ DaplinkBoard.KEY_HIC_ID: re.compile("^[a-f0-9]{8}$"),
+ DaplinkBoard.KEY_GIT_SHA: re.compile("^[a-f0-9]{40}$"),
+ DaplinkBoard.KEY_LOCAL_MODS: re.compile("^[01]{1}$"),
+ DaplinkBoard.KEY_USB_INTERFACES: re.compile("^.+$"),
+ DaplinkBoard.KEY_MODE: re.compile("(interface|bootloader)"),
+ }
+ optional_key_and_format = {
+ DaplinkBoard.KEY_BL_VERSION: re.compile("^[0-9]{4}$"),
+ DaplinkBoard.KEY_IF_VERSION: re.compile("^[0-9]{4}$"),
+ DaplinkBoard.KEY_BL_CRC: re.compile("^0x[a-f0-9]{8}$"),
+ DaplinkBoard.KEY_IF_CRC: re.compile("^0x[a-f0-9]{8}$"),
+ }
+ # 1. keys and values are alphanumeric
+ # 2. no duplicate keys
+ # 3. format is key : value
+ # 4. required keys are present
+ # 5. optional keys have the expected format
+ details_txt_path = self.get_file_path("details.txt")
+ details_txt = _parse_kvp_file(details_txt_path, test_info)
+ if not details_txt:
+ test_info.failure("Could not parse details.txt")
+ return
+
+ # Check for required keys
+ for key in required_key_and_format:
+ if key not in details_txt:
+ test_info.failure("Missing detail.txt entry: %s" % key)
+ continue
+
+ value = details_txt[key]
+ pattern = required_key_and_format[key]
+ if pattern.match(value) is None:
+ test_info.failure("Bad format detail.txt %s: %s" %
+ (key, value))
+
+ # Check format of optional values
+ for key in optional_key_and_format:
+ if key not in details_txt:
+ continue
+
+ value = details_txt[key]
+ pattern = optional_key_and_format[key]
+ if pattern.match(value) is None:
+ test_info.failure("Bad format detail.txt %s: %s" %
+ (key, value))
+
+ # Check details.txt contents
+ details_unique_id = None
+ details_hic_id = None
+ if DaplinkBoard.KEY_UNIQUE_ID in details_txt:
+ details_unique_id = details_txt[DaplinkBoard.KEY_UNIQUE_ID]
+ if DaplinkBoard.KEY_HIC_ID in details_txt:
+ details_hic_id = details_txt[DaplinkBoard.KEY_HIC_ID]
+ if details_unique_id is not None:
+ if details_unique_id != self.unique_id:
+ test_info.failure("Unique ID mismatch in details.txt "
+ "details.txt=%s, usb=%s" %
+ (details_unique_id, self.unique_id))
+ if details_hic_id is not None:
+ usb_hic = details_unique_id[-8:]
+ if details_hic_id != usb_hic:
+ test_info.failure("HIC ID is not the last 8 "
+ "digits of unique ID "
+ "details.txt=%s, usb=%s" %
+ (details_hic_id, usb_hic))
+
+ def _parse_assert_txt(self):
+ file_path = self.get_file_path("ASSERT.TXT")
+ if not os.path.isfile(file_path):
+ self._assert = None
+ return
+
+ assert_table = _parse_kvp_file(file_path)
+ assert "file" in assert_table
+ assert "line" in assert_table
+
+ self._assert = AssertInfo(assert_table["file"], assert_table['line'])
diff -r 000000000000 -r 01f31e923fe2 test/daplink_firmware.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/test/daplink_firmware.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,201 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+from __future__ import absolute_import
+import os
+import info
+import re
+import firmware
+
+
+def load_bundle_from_release(directory):
+ """ Return a bundle representing the given build"""
+ return ReleaseFirmwareBundle(directory)
+
+
+def load_bundle_from_project(tool='uvision'):
+ """
+ Return a bundle for the given tool
+
+ Note - This does not build the project. It only returns the
+ firmware that has already been built.
+ """
+ assert (tool == 'uvision' or tool == 'mbedcli'), 'Input tool %s is not supported' % (tool)
+
+ self_path = os.path.abspath(__file__)
+ test_dir = os.path.dirname(self_path)
+ daplink_dir = os.path.dirname(test_dir)
+ assert os.path.basename(test_dir) == 'test', 'The script "%s" must be ' \
+ 'located in the "test" directory of daplink to work correctly.'
+
+ if tool == 'uvision':
+ project_dir = os.path.join(daplink_dir, 'projectfiles', tool)
+ build_folder = 'build'
+ elif tool == 'mbedcli':
+ project_dir = os.path.join(daplink_dir, 'BUILD')
+ build_folder = 'ARM-CUSTOM_PROFILE'
+
+ return ProjectFirmwareBundle(project_dir, build_folder)
+
+
+class ReleaseFirmwareBundle(firmware.FirmwareBundle):
+ """Class to abstract access a formal build as a bundle"""
+
+ def __init__(self, directory):
+ bundle_contents = os.listdir(directory)
+ firmware_list = []
+ for name in bundle_contents:
+ path = directory + os.sep + name
+ if os.path.isdir(path):
+ daplink_firmware = DAPLinkFirmware(name, self, path)
+ if daplink_firmware.valid:
+ firmware_list.append(daplink_firmware)
+ elif os.path.isfile(path):
+ # Parse relevent info
+ pass
+ else:
+ assert False
+ self._firmware_list = firmware_list
+
+ def get_firmware_list(self):
+ return self._firmware_list
+
+ @property
+ def build_sha(self):
+ raise NotImplementedError()
+
+ @property
+ def build_local_mods(self):
+ raise NotImplementedError()
+
+
+class ProjectFirmwareBundle(firmware.FirmwareBundle):
+ """Class to abstract access to daplink's build directory as a bundle"""
+
+ def __init__(self, project_dir, build_folder):
+
+ if not os.path.exists(project_dir):
+ print ("Error: DAPLink project folder %s missing" % project_dir)
+ exit(-1)
+
+ project_dir_list = os.listdir(project_dir)
+ if not project_dir_list:
+ print ("Error: DAPLink projects not build yet at %s" % project_dir)
+ exit(-1)
+
+ firmware_list = []
+ for name in project_dir_list:
+ build_dir = os.path.join(project_dir, name, build_folder)
+ if os.path.isdir(build_dir):
+ daplink_firmware = DAPLinkFirmware(name.lower(), self, build_dir)
+ if daplink_firmware.valid:
+ firmware_list.append(daplink_firmware)
+ self._firmware_list = firmware_list
+
+ def get_firmware_list(self):
+ return self._firmware_list
+
+ @property
+ def build_sha(self):
+ raise NotImplementedError()
+
+ @property
+ def build_local_mods(self):
+ raise NotImplementedError()
+
+
+class DAPLinkFirmware(firmware.Firmware):
+ """Class to abstract access to a daplink firmware image"""
+
+ _IF_RE = re.compile("^([a-z0-9]+)([_a-z0-9]*)_if$")
+ _BL_RE = re.compile("^([a-z0-9]+)_bl$")
+
+ def __init__(self, name, bundle, directory):
+ self._name = name
+ self._bundle = bundle
+ self._directory = directory
+ self._valid = False
+
+ # Set type
+ self._type = None
+ string_hic = None
+ match = self._IF_RE.match(name)
+ if match:
+ string_hic = match.group(1)
+ self._type = self.TYPE.INTERFACE
+ match = self._BL_RE.match(name)
+ if match:
+ string_hic = match.group(1)
+ self._type = self.TYPE.BOOTLOADER
+ if self._type is None:
+ assert False, 'Bad project name "%s"' % name
+
+ # Set HIC
+ assert string_hic in info.HIC_STRING_TO_ID, 'Unknown HIC "%s" must ' \
+ 'be added to HIC_STRING_TO_ID in info.py' % string_hic
+ self._hic_id = info.HIC_STRING_TO_ID[string_hic]
+
+ # Check firmware name and type
+ assert self._type in self.TYPE, "Invalid type %s" % self._type
+ if self._type is self.TYPE.INTERFACE:
+ if name not in info.FIRMWARE_SET:
+ print('Warning: board "%s" no entry in SUPPORTED_CONFIGURATIONS in info.py' % name)
+
+ # Set file paths
+ self._bin_path = self._directory + os.sep + '%s_crc.bin' % name
+ self._hex_path = self._directory + os.sep + '%s_crc.hex' % name
+ self._bin_path = os.path.abspath(self._bin_path)
+ self._hex_path = os.path.abspath(self._hex_path)
+ if not os.path.isfile(self._bin_path):
+ return # Failure
+ if not os.path.isfile(self._hex_path):
+ return # Failure
+
+ self._valid = True
+
+ def __str__(self):
+ return "Name=%s" % (self.name)
+
+ @property
+ def valid(self):
+ """Set to True if the firmware is valid"""
+ return self._valid
+
+ @property
+ def name(self):
+ return self._name
+
+ @property
+ def hic_id(self):
+ return self._hic_id
+
+ @property
+ def type(self):
+ return self._type
+
+ @property
+ def bin_path(self):
+ return self._bin_path
+
+ @property
+ def hex_path(self):
+ return self._hex_path
+
+ @property
+ def elf_path(self):
+ return self._elf_path
diff -r 000000000000 -r 01f31e923fe2 test/firmware.py --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/test/firmware.py Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,79 @@ +# +# DAPLink Interface Firmware +# Copyright (c) 2009-2016, ARM Limited, All Rights Reserved +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +from __future__ import absolute_import +from enum import Enum + + +class FirmwareBundle(object): + + def get_firmware_list(self): + """Return the firmware objects associated with this bundle""" + raise NotImplementedError() + + @property + def build_sha(self): + """The GIT SHA this build was created at as a string or None""" + raise NotImplementedError() + + @property + def build_local_mods(self): + """True if this was a clean build, False otherwise""" + raise NotImplementedError() + + +class Firmware(object): + """Class wrapping a firmware build""" + + class TYPE(Enum): + BOOTLOADER = 1 + INTERFACE = 2 + + def __str__(self): + """A string that describes this firmware""" + raise NotImplementedError() + + @property + def name(self): + """Name of this project""" + raise NotImplementedError() + + @property + def hic_id(self): + """HIC ID for the type of board this firmware can run on""" + raise NotImplementedError() + + @property + def type(self): + """Build type - either interface or bootloader""" + raise NotImplementedError() + + @property + def bin_path(self): + """Path to the binary vesion of this firmware or None""" + raise NotImplementedError() + + @property + def hex_path(self): + """Path to the hex vesion of this firmware or None""" + raise NotImplementedError() + + @property + def elf_path(self): + """Path to the hex vesion of this firmware or None""" + raise NotImplementedError()
diff -r 000000000000 -r 01f31e923fe2 test/hid_test.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/test/hid_test.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,217 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+from __future__ import absolute_import
+
+from time import sleep
+from random import randrange
+import math
+
+from pyocd.core.helpers import ConnectHelper
+from pyocd.core.memory_map import MemoryType
+from pyocd.flash.loader import FileProgrammer
+from pyocd.utility.conversion import float32_to_u32
+
+# TODO - make a dedicated test
+# TODO - test all DapLink commands
+# TODO - test various clock speeds
+# TODO - test turnaround settings
+# TODO - test HID speed
+# TODO - test ram/rom transfer speeds
+
+
+def test_hid(workspace, parent_test):
+ test_info = parent_test.create_subtest("HID test")
+ board = workspace.board
+ with ConnectHelper.session_with_chosen_probe(unique_id=board.get_unique_id()) as session:
+ mbed_board = session.board
+ target = mbed_board.target
+ binary_file = workspace.target.bin_path
+
+ ram_region = target.memory_map.get_first_region_of_type(MemoryType.RAM)
+ rom_region = target.memory_map.get_boot_memory()
+
+ addr = ram_region.start + 4
+ size = 0x502
+ addr_bin = rom_region.start
+ addr_flash = rom_region.start + rom_region.length // 2
+
+ flash = rom_region.flash
+
+ test_info.info("\r\n\r\n----- FLASH NEW BINARY -----")
+ FileProgrammer(session).program(binary_file, base_address=addr_bin)
+
+ test_info.info("\r\n\r\n------ GET Unique ID ------")
+ test_info.info("Unique ID: %s" % mbed_board.unique_id)
+
+ test_info.info("\r\n\r\n------ TEST READ / WRITE CORE REGISTER ------")
+ pc = target.read_core_register('pc')
+ test_info.info("initial pc: 0x%X" % target.read_core_register('pc'))
+ # write in pc dummy value
+ target.write_core_register('pc', 0x3D82)
+ test_info.info("now pc: 0x%X" % target.read_core_register('pc'))
+ # write initial pc value
+ target.write_core_register('pc', pc)
+ test_info.info("initial pc value rewritten: 0x%X" %
+ target.read_core_register('pc'))
+
+ msp = target.read_core_register('msp')
+ psp = target.read_core_register('psp')
+ test_info.info("MSP = 0x%08x; PSP = 0x%08x" % (msp, psp))
+
+ control = target.read_core_register('control')
+ faultmask = target.read_core_register('faultmask')
+ basepri = target.read_core_register('basepri')
+ primask = target.read_core_register('primask')
+ test_info.info("CONTROL = 0x%02x; FAULTMASK = 0x%02x; BASEPRI = 0x%02x; PRIMASK = 0x%02x" % (control, faultmask, basepri, primask))
+
+ target.write_core_register('primask', 1)
+ newPrimask = target.read_core_register('primask')
+ test_info.info("New PRIMASK = 0x%02x" % newPrimask)
+ target.write_core_register('primask', primask)
+ newPrimask = target.read_core_register('primask')
+ test_info.info("Restored PRIMASK = 0x%02x" % newPrimask)
+
+ if target.has_fpu:
+ s0 = target.read_core_register('s0')
+ test_info.info("S0 = %g (0x%08x)" % (s0, float32_to_u32(s0)))
+ target.write_core_register('s0', math.pi)
+ newS0 = target.read_core_register('s0')
+ test_info.info("New S0 = %g (0x%08x)" %
+ (newS0, float32_to_u32(newS0)))
+ target.write_core_register('s0', s0)
+ newS0 = target.read_core_register('s0')
+ test_info.info("Restored S0 = %g (0x%08x)" %
+ (newS0, float32_to_u32(newS0)))
+
+ test_info.info("\r\n\r\n------ TEST HALT / RESUME ------")
+
+ test_info.info("resume")
+ target.resume()
+ sleep(0.2)
+
+ test_info.info("halt")
+ target.halt()
+ test_info.info("HALT: pc: 0x%X" % target.read_core_register('pc'))
+ sleep(0.2)
+
+ test_info.info("\r\n\r\n------ TEST STEP ------")
+
+ test_info.info("reset and halt")
+ target.reset_and_halt()
+ currentPC = target.read_core_register('pc')
+ test_info.info("HALT: pc: 0x%X" % currentPC)
+ sleep(0.2)
+
+ for i in range(4):
+ test_info.info("step")
+ target.step()
+ newPC = target.read_core_register('pc')
+ test_info.info("STEP: pc: 0x%X" % newPC)
+ currentPC = newPC
+ sleep(0.2)
+
+ test_info.info("\r\n\r\n------ TEST READ / WRITE MEMORY ------")
+ target.halt()
+ test_info.info("READ32/WRITE32")
+ val = randrange(0, 0xffffffff)
+ test_info.info("write32 0x%X at 0x%X" % (val, addr))
+ target.write32(addr, val)
+ res = target.read32(addr)
+ test_info.info("read32 at 0x%X: 0x%X" % (addr, res))
+ if res != val:
+ test_info.failure("ERROR in READ/WRITE 32")
+
+ test_info.info("\r\nREAD16/WRITE16")
+ val = randrange(0, 0xffff)
+ test_info.info("write16 0x%X at 0x%X" % (val, addr + 2))
+ target.write16(addr + 2, val)
+ res = target.read16(addr + 2)
+ test_info.info("read16 at 0x%X: 0x%X" % (addr + 2, res))
+ if res != val:
+ test_info.failure("ERROR in READ/WRITE 16")
+
+ test_info.info("\r\nREAD8/WRITE8")
+ val = randrange(0, 0xff)
+ test_info.info("write8 0x%X at 0x%X" % (val, addr + 1))
+ target.write8(addr + 1, val)
+ res = target.read8(addr + 1)
+ test_info.info("read8 at 0x%X: 0x%X" % (addr + 1, res))
+ if res != val:
+ test_info.failure("ERROR in READ/WRITE 8")
+
+ test_info.info("\r\n\r\n------ TEST READ / WRITE MEMORY BLOCK ------")
+ data = [randrange(1, 50) for _ in range(size)]
+ target.write_memory_block8(addr, data)
+ block = target.read_memory_block8(addr, size)
+ error = False
+ for i in range(len(block)):
+ if (block[i] != data[i]):
+ error = True
+ test_info.info("ERROR: 0x%X, 0x%X, 0x%X!!!" %
+ ((addr + i), block[i], data[i]))
+ if error:
+ test_info.failure("TEST FAILED")
+ else:
+ test_info.info("TEST PASSED")
+
+ test_info.info("\r\n\r\n------ TEST RESET ------")
+ target.reset()
+ sleep(0.1)
+ target.halt()
+
+ for i in range(5):
+ target.step()
+ test_info.info("pc: 0x%X" % target.read_core_register('pc'))
+
+ test_info.info("\r\n\r\n------ TEST PROGRAM/ERASE PAGE ------")
+ # Fill 3 pages with 0x55
+ page_size = flash.get_page_info(addr_flash).size
+ fill = [0x55] * page_size
+ for i in range(0, 3):
+ address = addr_flash + page_size * i
+ # Test only supports a location with 3 aligned
+ # pages of the same size
+ current_page_size = flash.get_page_info(addr_flash).size
+ assert page_size == current_page_size
+ assert address % current_page_size == 0
+
+ flash.init(flash.Operation.ERASE)
+ flash.erase_page(address)
+ flash.uninit()
+
+ flash.init(flash.Operation.PROGRAM)
+ flash.program_page(address, fill)
+ flash.uninit()
+ # Erase the middle page
+ flash.init(flash.Operation.ERASE)
+ flash.erase_page(addr_flash + page_size)
+ flash.cleanup()
+ # Verify the 1st and 3rd page were not erased, and that the 2nd page is fully erased
+ data = target.read_memory_block8(addr_flash, page_size * 3)
+ expected = fill + [0xFF] * page_size + fill
+ if data == expected:
+ test_info.info("TEST PASSED")
+ else:
+ test_info.failure("TEST FAILED")
+
+ test_info.info("\r\n\r\n----- Restoring image -----")
+ FileProgrammer(session).program(binary_file, base_address=addr_bin)
+
+ target.reset()
+ test_info.info("HID test complete")
diff -r 000000000000 -r 01f31e923fe2 test/info.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/test/info.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,399 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+from __future__ import absolute_import
+
+# Name of all projects ready for public release
+# and info on the file to be distributed
+PROJECT_RELEASE_INFO = {
+ # Project Name Legacy Offset Extension
+ ("k20dx_frdmk22f_if", True, 0x8000, "bin" ),
+ ("k20dx_frdmk64f_if", True, 0x5000, "bin" ),
+ ("k20dx_hexiwear_if", True, 0x8000, "bin" ),
+ ("k20dx_rapid_iot_if", True, 0x8000, "bin" ),
+ ("k20dx_frdmk66f_if", True, 0x8000, "bin" ),
+ ("k20dx_frdmk28f_if", True, 0x8000, "bin" ),
+ ("k20dx_frdmk82f_if", True, 0x8000, "bin" ),
+ ("kl26z_microbit_if", False, 0x8000, "hex" ),
+ ("lpc11u35_lpc812xpresso_if", False, 0x0000, "bin" ),
+ ("lpc11u35_lpc824xpresso_if", False, 0x0000, "bin" ),
+ ("lpc4322_lpc54114xpresso_if", False, 0x10000, "bin" ),
+ ("lpc4322_lpc54608xpresso_if", False, 0x10000, "bin" ),
+ ("lpc4322_lpc55s69xpresso_if", False, 0x10000, "bin" ),
+ ("lpc11u35_ssci1114_if", False, 0x0000, "bin" ),
+ ("sam3u2c_mkit_dk_dongle_nrf5x_if", True, 0x5000, "bin" ),
+ ("k20dx_frdmk20dx_if", True, 0x8000, "bin" ),
+ ("k20dx_frdmkw24d_if", True, 0x8000, "bin" ),
+ ("k20dx_frdmkw41z_if", True, 0x8000, "bin" ),
+ ("k20dx_frdmkl02z_if", True, 0x8000, "bin" ),
+ ("k20dx_frdmkl05z_if", True, 0x8000, "bin" ),
+ ("k20dx_frdmkl25z_if", True, 0x8000, "bin" ),
+ ("k20dx_frdmkl26z_if", True, 0x8000, "bin" ),
+ ("k20dx_frdmkl27z_if", True, 0x8000, "bin" ),
+ ("k20dx_frdmkl28z_if", True, 0x8000, "bin" ),
+ ("k20dx_twrkl28z72m_if", True, 0x8000, "bin" ),
+ ("k20dx_frdmkl43z_if", True, 0x8000, "bin" ),
+ ("k20dx_frdmkl46z_if", True, 0x8000, "bin" ),
+ ("k20dx_frdmkl82z_if", True, 0x5000, "bin" ),
+ ("k20dx_frdmke15z_if", True, 0x8000, "bin" ),
+ ("k20dx_twrke18f_if", True, 0x8000, "bin" ),
+ ("k20dx_hvpke18f_if", True, 0x8000, "bin" ),
+ ("k20dx_mimxrt1020_evk_qspi_if", True, 0x8000, "bin" ),
+ ("k20dx_mimxrt1050_evk_hyper_if", True, 0x8000, "bin" ),
+ ("k20dx_mimxrt1050_evk_qspi_if", True, 0x8000, "bin" ),
+ ('k20dx_ep_agora_if', True, 0x0000, "bin" ),
+ ("k26f_frdmk32w042_if", False, 0x8000, "bin" ),
+ ("lpc11u35_archble_if", False, 0x0000, "bin" ),
+ ("lpc11u35_archpro_if", False, 0x0000, "bin" ),
+ ("lpc11u35_archmax_if", False, 0x0000, "bin" ),
+ ("lpc11u35_wio3g_if", False, 0x0000, "bin" ),
+ ("lpc11u35_wiobg96_if", False, 0x0000, "bin" ),
+ ("lpc11u35_wio_emw3166_if", False, 0x0000, "bin" ),
+ ("lpc11u35_hrm1017_if", False, 0x0000, "bin" ),
+ ("lpc11u35_sscity_if", False, 0x0000, "bin" ),
+ ("lpc11u35_ssci824_if", False, 0x0000, "bin" ),
+ ("lpc11u35_ro359b_if", False, 0x0000, "bin" ),
+ ("k20dx_rbl_if", True, 0x5000, "bin" ),
+ ("k20dx_rblnano_if", True, 0x5000, "bin" ),
+ ("lpc11u35_archlink_if", False, 0x0000, "bin" ),
+ ("lpc11u35_tiny_if", False, 0x0000, "bin" ),
+ ("lpc11u35_c027_if", False, 0x0000, "bin" ),
+ ("sam3u2c_ncs36510rf_if", False, 0x8000, "bin" ),
+ ("kl26z_nina_b1_if", False, 0x8000, "bin" ),
+ ("lpc11u35_lpc4088dm_if", False, 0x0000, "bin" ),
+ ("lpc11u35_lpc4088qsb_if", False, 0x0000, "bin" ),
+ ('lpc11u35_ssci_chibi_if', False, 0x0000, "bin" ),
+ ('lpc11u35_ff1705_l151_if', False, 0x0000, "bin" ),
+ ('lpc11u35_ff_lpc546xx_if', False, 0x0000, "bin" ),
+ ('lpc11u35_mini_iot_lpc54018_if', False, 0x0000, "bin" ),
+ ("k20dx_xdot_l151_if", False, 0x8000, "bin" ),
+ ('lpc11u35_6lowpan_borderrouterhat_if', None, 0x0000, "bin" ),
+ ('lpc11u35_6lowpan_borderrouterusb_if', None, 0x0000, "bin" ),
+ ('lpc11u35_6lowpan_borderrouterethernet_if', None, 0x0000, "bin" ),
+ ('lpc11u35_gr_peach_if', None, 0x0000, "bin" ),
+ ('lpc11u35_gr_lychee_if', None, 0x0000, "bin" ),
+ ('lpc11u35_nz32_sc151_if', False, 0x0000, "bin" ),
+ ('lpc11u35_wizwiki_w7500_if', False, 0x0000, "bin" ),
+ ('lpc11u35_wizwiki_w7500_eco_if', False, 0x0000, "bin" ),
+ ('lpc11u35_wizwiki_w7500p_if', False, 0x0000, "bin" ),
+ ("sam3u2c_ublox_evk_nina_b1_if", True, 0x5000, "bin" ),
+ ("lpc11u35_vbluno51_if", False, 0x0000, "bin" ),
+ ('lpc11u35_mtconnect04s_if', False, 0x0000, "bin" ),
+ ('lpc11u35_mbed_cloud_connect_if', False, 0x0000, "bin" ),
+ ("lpc11u35_rtl8195am_if", False, 0x0000, "bin" ),
+ ("lpc11u35_96b_nitrogen_if", False, 0x0000, "bin" ),
+ ('lpc11u35_mtb_mxchip_emw3166_if', False, 0x0000, "bin" ),
+ ('lpc11u35_mtb_nina_b112_if', False, 0x0000, "bin" ),
+ ('lpc11u35_mtb_murata_abz_078_if', False, 0x0000, "bin" ),
+ ('lpc11u35_mtb_rak811_if', False, 0x0000, "bin" ),
+ ('lpc11u35_mtb_wise1510_if', False, 0x0000, "bin" ),
+ ('lpc11u35_mtb_wise1530_if', False, 0x0000, "bin" ),
+ ('lpc11u35_mtb_wise1570_if', False, 0x0000, "bin" ),
+ ('lpc11u35_mtb_laird_bl652_if', False, 0x0000, "bin" ),
+ ('lpc11u35_mtb_usi_wm_bn_bm_22_if', False, 0x0000, "bin" ),
+ ('lpc11u35_dipdap_sdt52832b_if', False, 0x0000, "bin" ),
+ ('lpc11u35_dipdap_sdt32429b_if', False, 0x0000, "bin" ),
+ ('lpc11u35_dipdap_sdt32439b_if', False, 0x0000, "bin" ),
+ ('lpc11u35_dipdap_sdt64b_if', False, 0x0000, "bin" ),
+ ('lpc11u35_dipdap_sdt51822b_if', False, 0x0000, "bin" ),
+ ('lpc11u35_mtb_ublox_odin_w2_if', False, 0x0000, "bin" ),
+ ('lpc11u35_mtb_mts_dragonfly_if', False, 0x0000, "bin" ),
+ ('lpc11u35_mtb_mts_xdot_if', False, 0x0000, "bin" ),
+ ('lpc11u35_dipdap_cc3220sf_if', False, 0x0000, "bin" ),
+ ('lpc11u35_mtb_laird_bl654_if', False, 0x0000, "bin" ),
+ ('lpc11u35_mtb_murata_bl241_if', False, 0x0000, "bin" ),
+ ('lpc11u35_mtb_stm_s2lp_if', False, 0x0000, "bin" ),
+ ('lpc11u35_mtb_stm32l475_if', False, 0x0000, "bin" ),
+ ('lpc11u35_mtb_aconno_acn52832_if', False, 0x0000, "bin" ),
+ ('lpc11u35_mtb_stm32f439_if', False, 0x0000, "bin" ),
+ ('lpc11u35_musca_a_if', False, 0x0000, "bin" ),
+ ('lpc11u35_musca_b_if', False, 0x0000, "bin" ),
+ ('lpc11u35_musca_b_eflash_if', False, 0x0000, "bin" ),
+ ('max32620_max32625mbed_if', False, 0x0000, "bin" ),
+ ('max32625_max32620fthr_if', False, 0x0000, "bin" ),
+ ('max32625_max32630fthr_if', False, 0x0000, "bin" ),
+ ('kl26z_if', False, 0x0000, "bin" ),
+ ('k20dx_if', False, 0x0000, "bin" ),
+ ('k26f_if', False, 0x0000, "bin" ),
+ ('lpc11u35_if', False, 0x0000, "bin" ),
+ ('lpc4322_if', False, 0x0000, "bin" ),
+ ('max32620_if', False, 0x0000, "bin" ),
+ ('max32625_if', False, 0x0000, "bin" ),
+ ('sam3u2c_if', False, 0x0000, "bin" ),
+ ('stm32f103xb_if', False, 0x0000, "bin" ),
+}
+
+# Add new HICs here
+VENDOR_ID = {
+ 'Stub': 0,
+ 'NXP': 11,
+ 'TI': 16,
+ 'Nordic': 54,
+ 'Toshiba': 92,
+ 'Renesas' : 117,
+ 'Wiznet': 122,
+ 'Realtek': 124,
+}
+
+def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y
+
+# All supported configurations
+SUPPORTED_CONFIGURATIONS = [
+ # Board ID Family ID Firmware Bootloader Target
+ ( 0x0200, VENDOR_TO_FAMILY('NXP', 2), 'k20dx_frdmkl25z_if', 'k20dx_bl', 'KL25Z' ),
+ ( 0x0201, VENDOR_TO_FAMILY('NXP', 2), 'k20dx_frdmkw41z_if', 'k20dx_bl', 'FRDM-KW41Z' ),
+ ( 0x0203, VENDOR_TO_FAMILY('NXP', 2), 'k20dx_twrkl28z72m_if', 'k20dx_bl', None ),
+ ( 0x0204, VENDOR_TO_FAMILY('NXP', 2), 'k20dx_frdmkl02z_if', 'k20dx_bl', None ),
+ ( 0x0205, VENDOR_TO_FAMILY('NXP', 2), 'k20dx_frdmkl28z_if', 'k20dx_bl', None ),
+ ( 0x0206, VENDOR_TO_FAMILY('NXP', 1), 'k20dx_twrke18f_if', 'k20dx_bl', None ),
+ ( 0x0210, VENDOR_TO_FAMILY('NXP', 2), 'k20dx_frdmkl05z_if', 'k20dx_bl', 'FRDM-KL05Z' ),
+ ( 0x0213, VENDOR_TO_FAMILY('NXP', 2), 'k20dx_frdmke15z_if', 'k20dx_bl', None ),
+ ( 0x0214, VENDOR_TO_FAMILY('NXP', 4), 'k20dx_hexiwear_if', 'k20dx_bl', 'HEXIWEAR' ),
+ ( 0x0216, VENDOR_TO_FAMILY('NXP', 1), 'k20dx_hvpke18f_if', 'k20dx_bl', None ),
+ ( 0x0217, VENDOR_TO_FAMILY('NXP', 1), 'k20dx_frdmk82f_if', 'k20dx_bl', 'FRDM-K82F' ),
+ ( 0x0218, VENDOR_TO_FAMILY('NXP', 2), 'k20dx_frdmkl82z_if', 'k20dx_bl', 'FRDM-KL82Z' ),
+ ( 0x0220, VENDOR_TO_FAMILY('NXP', 2), 'k20dx_frdmkl46z_if', 'k20dx_bl', 'FRDM-KL46Z' ),
+ ( 0x0224, VENDOR_TO_FAMILY('NXP', 1), 'k20dx_frdmk28f_if', 'k20dx_bl', None ), # TODO - set target to 'FRDM-K28F' when mbed-os supports this
+ ( 0x0225, VENDOR_TO_FAMILY('NXP', 1), 'k26f_frdmk32w042_if', 'k26f_bl', None ), # TODO - set target to 'FRDM-K32W042' when mbed-os supports this
+ ( 0x0226, VENDOR_TO_FAMILY('NXP', 3), 'k20dx_mimxrt1020_evk_qspi_if', 'k20dx_bl', None ), # TODO - set target to 'MIMX6RT1050' when mbed-os supports this
+ ( 0x0227, VENDOR_TO_FAMILY('NXP', 3), 'k20dx_mimxrt1050_evk_hyper_if', 'k20dx_bl', None ), # TODO - set target to 'MIMX6RT1050' when mbed-os supports this
+ ( 0x0227, VENDOR_TO_FAMILY('NXP', 3), 'k20dx_mimxrt1050_evk_qspi_if', 'k20dx_bl', None ), # TODO - set target to 'MIMX6RT1050' when mbed-os supports this
+ ( 0x0228, VENDOR_TO_FAMILY('NXP', 4), 'k20dx_rapid_iot_if', 'k20dx_bl', None ), # TODO - set target to 'Rapid-IoT' when mbed-os supports this
+ ( 0x0230, VENDOR_TO_FAMILY('NXP', 1), 'k20dx_frdmk20dx_if', 'k20dx_bl', 'FRDM-K20D50M' ),
+ ( 0x0231, VENDOR_TO_FAMILY('NXP', 1), 'k20dx_frdmk22f_if', 'k20dx_bl', 'FRDM-K22F' ),
+ ( 0x0236, VENDOR_TO_FAMILY('NXP', 0), 'lpc4322_lpc55s69xpresso_if', 'lpc4322_bl', 'LPCXpresso55S69' ),
+ ( 0x0240, VENDOR_TO_FAMILY('NXP', 1), 'k20dx_frdmk64f_if', 'k20dx_bl', 'FRDM-K64F' ),
+ ( 0x0250, VENDOR_TO_FAMILY('NXP', 1), 'k20dx_frdmkw24d_if', 'k20dx_bl', 'FRDM-KW24D512' ),
+ ( 0x0260, VENDOR_TO_FAMILY('NXP', 2), 'k20dx_frdmkl26z_if', 'k20dx_bl', None ),
+ ( 0x0261, VENDOR_TO_FAMILY('NXP', 2), 'k20dx_frdmkl27z_if', 'k20dx_bl', 'FRDM-KL27Z' ),
+ ( 0x0262, VENDOR_TO_FAMILY('NXP', 2), 'k20dx_frdmkl43z_if', 'k20dx_bl', 'FRDM-KL43Z' ),
+ ( 0x0311, VENDOR_TO_FAMILY('NXP', 1), 'k20dx_frdmk66f_if', 'k20dx_bl', 'FRDM-K66F' ),
+ ( 0x0350, VENDOR_TO_FAMILY('Stub', 1), 'k20dx_xdot_l151_if', 'k20dx_bl', None ), # TODO - set target to 'MTS-xDot-L151CC' when mbed-os supports this
+ ( 0x0360, VENDOR_TO_FAMILY('NXP', 1), 'lpc4322_hani_iot_if', 'lpc4322_bl', 'HANI-IOT' ),
+ ( 0x0409, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32630fthr_if', 'max32625_bl', 'MAX32630' ),
+ ( 0x0415, VENDOR_TO_FAMILY('Stub', 1), 'max32620_max32625mbed_if', 'max32620_bl', 'MAX32625' ),
+ ( 0x0418, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32620fthr_if', 'max32625_bl', 'MAX32620' ),
+ ( 0x0450, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_ublox_odin_w2_if', None, None ),
+ ( 0x0451, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_mxchip_emw3166_if', None, None ), # TODO - set target when mbed-os supports this
+ ( 0x0453, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_mts_xdot_if', None, None ),
+ ( 0x0454, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_mts_dragonfly_if', None, None ),
+ ( 0x0455, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_mtb_nina_b112_if', None, None ), # TODO - set target when mbed-os supports this
+ ( 0x0456, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_murata_abz_078_if', None, None ), # TODO - set target when mbed-os supports this
+ ( 0x0457, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_rak811_if', None, None ), # TODO - set target when mbed-os supports this
+ ( 0x0458, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1510_if', None, None ), # TODO - set target when mbed-os supports this
+ ( 0x0459, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1530_if', None, None ), # TODO - set target when mbed-os supports this
+ ( 0x0460, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1570_if', None, None ), # TODO - set target when mbed-os supports this
+ ( 0x0461, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_mtb_laird_bl652_if', None, None ), # TODO - set target when mbed-os supports this
+ ( 0x0462, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_usi_wm_bn_bm_22_if', None, None ), # TODO - set target when mbed-os supports this
+ ( 0x0465, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_mtb_laird_bl654_if', None, None ), # TODO - set target when mbed-os supports this
+ ( 0x0466, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_mtb_murata_bl241_if', None, None ), # TODO - set target when mbed-os supports this
+ ( 0x0467, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_stm_s2lp_if', None, None ), # TODO - set target when mbed-os supports this
+ ( 0x0468, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_stm32l475_if', None, None ), # TODO - set target when mbed-os supports this
+ ( 0x0469, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_stm32f439_if', None, None ), # TODO - set target when mbed-os supports this
+ ( 0x0472, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_mtb_aconno_acn52832_if', None, None ), # TODO - set target when mbed-os supports this
+ ( 0x0700, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f103rb_if', 'stm32f103xb_bl', 'ST-Nucleo-F103RB' ),
+ ( 0x0720, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f401re_if', 'stm32f103xb_bl', 'ST-Nucleo-F401RE' ),
+ ( 0x0720, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f072rb_if', 'stm32f103xb_bl', 'ST-Nucleo-F072RB' ),
+ ( 0x0735, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f334r8_if', 'stm32f103xb_bl', 'ST-Nucleo-F334R8' ),
+ ( 0x0740, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f411re_if', 'stm32f103xb_bl', 'ST-Nucleo-F411RE' ),
+ ( 0x0765, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32l476rg_if', 'stm32f103xb_bl', 'ST-Nucleo-L476RG' ),
+ ( 0x0796, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f429zi_if', 'stm32f103xb_bl', 'ST-Nucleo-F429ZI' ),
+ ( 0x0816, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f746zg_if', 'stm32f103xb_bl', 'ST-Nucleo-F746ZG' ),
+ ( 0x0824, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_lpc824xpresso_if', None, 'LPCXpresso824-MAX' ),
+ ( 0x0835, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f207zg_if', 'stm32f103xb_bl', 'ST-Nucleo-F207ZG' ),
+ ( 0x1017, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_hrm1017_if', None, 'mbed-HRM1017' ),
+ ( 0x1018, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_ssci824_if', None, 'Switch-Science-mbed-LPC824' ),
+ ( 0x1019, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_sscity_if', None, 'Switch-Science-mbed-TY51822r3' ),
+ ( 0x1021, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_ssci_chibi_if', None, None ), # TODO - set target to 'SSCI-MBIT' when mbed-os supports this
+ ( 0x1022, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_ro359b_if', None, None ),
+ ( 0x1050, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_lpc812xpresso_if', None, 'NXP-LPC800-MAX' ),
+ ( 0x1054, VENDOR_TO_FAMILY('Stub', 1), 'lpc4322_lpc54114xpresso_if', 'lpc4322_bl', 'LPCXpresso54114' ),
+ ( 0x1056, VENDOR_TO_FAMILY('Stub', 1), 'lpc4322_lpc54608xpresso_if', 'lpc4322_bl', 'LPCXpresso54608' ),
+ ( 0x1060, VENDOR_TO_FAMILY('NXP', 0), 'lpc11u35_lpc4088qsb_if', None, 'EA-LPC4088' ),
+ ( 0x1062, VENDOR_TO_FAMILY('NXP', 0), 'lpc11u35_lpc4088dm_if', None, 'EA-LPC4088-Display-Module' ),
+ ( 0x1070, VENDOR_TO_FAMILY('Nordic', 1), 'sam3u2c_mkit_dk_dongle_nrf5x_if', 'sam3u2c_bl', 'Nordic-nRF51822' ),
+ ( 0x1090, VENDOR_TO_FAMILY('Nordic', 1), 'k20dx_rbl_if', 'k20dx_bl', 'RedBearLab-nRF51822' ),
+ ( 0x1095, VENDOR_TO_FAMILY('Nordic', 1), 'k20dx_rblnano_if', 'k20dx_bl', 'RedBearLab-BLE-Nano' ),
+ ( 0x1100, VENDOR_TO_FAMILY('Nordic', 1), 'sam3u2c_mkit_dk_dongle_nrf5x_if', 'sam3u2c_bl', 'Nordic-nRF51-DK' ),
+ ( 0x1101, VENDOR_TO_FAMILY('Nordic', 2), 'sam3u2c_mkit_dk_dongle_nrf5x_if', 'sam3u2c_bl', 'Nordic-nRF52-DK' ),
+ ( 0x1102, VENDOR_TO_FAMILY('Nordic', 2), 'sam3u2c_mkit_dk_dongle_nrf5x_if', 'sam3u2c_bl', 'Nordic-nRF52840-DK' ),
+ ( 0x1114, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_ssci1114_if', None, 'LPC1114FN28' ),
+ ( 0x1120, VENDOR_TO_FAMILY('Nordic', 1), 'sam3u2c_mkit_dk_dongle_nrf5x_if', 'sam3u2c_bl', 'Nordic-nRF51-Dongle' ),
+ ( 0x1200, VENDOR_TO_FAMILY('Stub', 3), 'sam3u2c_ncs36510rf_if', 'sam3u2c_bl', None ),# TODO - Set to 'ncs36510' when non-zero flash addresses are supported
+ ( 0x1234, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_c027_if', None, 'u-blox-C027' ),
+ ( 0x1236, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_ublox_evk_odin_w2_if', 'stm32f103xb_bl', 'ublox-EVK-ODIN-W2' ),
+ ( 0x1237, VENDOR_TO_FAMILY('Nordic', 2), 'sam3u2c_ublox_evk_nina_b1_if', 'sam3u2c_bl', 'U-BLOX-EVK-NINA-B1' ),
+ ( 0x1238, VENDOR_TO_FAMILY('Nordic', 1), 'kl26z_nina_b1_if', 'kl26z_bl', 'u-blox-NINA-B1' ),
+ ( 0x1309, VENDOR_TO_FAMILY('Stub', 3), 'm48ssidae_numaker_m252kg_if', 'm48ssidae_bl', None ),
+ ( 0x1310, VENDOR_TO_FAMILY('Stub', 3), 'm48ssidae_numaker_iot_m263a_if', 'm48ssidae_bl', None ),
+ ( 0x2201, VENDOR_TO_FAMILY('Wiznet', 1), 'lpc11u35_wizwiki_w7500_if', None, 'WIZwiki-W7500' ),
+ ( 0x2202, VENDOR_TO_FAMILY('Wiznet', 1), 'lpc11u35_wizwiki_w7500_eco_if', None, 'WIZwiki-W7500ECO' ),
+ ( 0x2203, VENDOR_TO_FAMILY('Wiznet', 1), 'lpc11u35_wizwiki_w7500p_if', None, 'WIZwiki-W7500P' ),
+ ( 0x2410, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mbed_cloud_connect_if', None, None ),
+ ( 0x2600, VENDOR_TO_FAMILY('Nordic', 2), 'k20dx_ep_agora_if', None, None ),
+ ( 0x3104, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_dipdap_sdt52832b_if', None, None ),
+ ( 0x3108, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_dipdap_sdt32429b_if', None, None ),
+ ( 0x3105, VENDOR_TO_FAMILY('NXP', 1), 'lpc11u35_dipdap_sdt64b_if', None, None ),
+ ( 0x3103, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_dipdap_sdt51822b_if', None, None ),
+ ( 0x3110, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_dipdap_sdt32439b_if', None, None ),
+ ( 0x3300, VENDOR_TO_FAMILY('TI', 1), 'lpc11u35_dipdap_cc3220sf_if', None, 'CC3220SF' ),
+ ( 0x4600, VENDOR_TO_FAMILY('Realtek', 1), 'lpc11u35_rtl8195am_if', None, 'REALTEK-RTL8195AM' ),
+ ( 0x5006, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_musca_a_if', None, 'ARM_MUSCA_A1' ),
+ ( 0x5007, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_musca_b_if', None, 'ARM_MUSCA_B1' ),
+ ( 0x5007, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_musca_b_eflash_if', None, 'ARM_MUSCA_B1' ),
+ ( 0x5050, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_arm_watch_stm32f411_if', None, None ),
+ ( 0x5051, VENDOR_TO_FAMILY('Stub', 3), 'lpc11u35_arm_watch_efm32_if', None, None ),
+ ( 0x5052, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_arm_watch_nrf51_if', None, None ),
+ ( 0x5500, VENDOR_TO_FAMILY('Renesas', 1), 'lpc11u35_gr_peach_if', None, None ), # TODO - Set to 'Renesas-GR-PEACH' once this target builds
+ ( 0x5501, VENDOR_TO_FAMILY('Renesas', 1), 'lpc11u35_gr_lychee_if', None, None ), # TODO - Set to 'Renesas-GR-LYCHEE' once this target builds
+ ( 0x6660, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_nz32_sc151_if', None, None ), # TODO - set target to 'NZ32-SC151' when mbed-os supports this
+ ( 0x7010, VENDOR_TO_FAMILY('Toshiba', 1), 'lpc11u35_blueninja_if', None, None ), # TODO - set target to 'BlueNinja-CDP-TZ01B' when mbed-os supports this
+ ( 0x7402, VENDOR_TO_FAMILY('NXP', 1), 'lpc11u35_6lowpan_borderrouterhat_if', None, 'mbed-6LoWPAN-Border-Router-HAT' ),
+ ( 0x7403, VENDOR_TO_FAMILY('NXP', 1), 'lpc11u35_6lowpan_borderrouterusb_if', None, 'mbed-6LoWPAN-Border-Router-USB' ),
+ ( 0x7404, VENDOR_TO_FAMILY('NXP', 1), 'lpc11u35_6lowpan_borderrouterethernet_if', None, 'mbed-6LoWPAN-Border-Router-ETHERNET' ),
+ ( 0x8080, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_ff1705_l151_if', None, None ), # TODO - set target to 'L-TEK-FF1705' when mbed-os supports this
+ ( 0x8081, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_ff_lpc546xx_if', None, None ), # TODO - set target to 'L-TEK-FF-LPC546XX' when mbed-os supports this
+ ( 0x9004, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_archpro_if', None, 'Seeeduino-Arch-Pro' ),
+ ( 0x9009, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_archble_if', None, 'Seeed-Arch-BLE' ),
+ ( 0x9011, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_archmax_if', None, 'Seeed-Arch-Max' ),
+ ( 0x9012, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_tiny_if', None, 'Seeed-Tiny-BLE' ),
+ ( 0x9013, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_archlink_if', None, 'Seeed-Arch-Link' ),
+ ( 0x9014, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_wio3g_if', None, None ),
+ ( 0x9015, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_wiobg96_if', None, None ),
+ ( 0x9016, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_96b_nitrogen_if', None, None ), # TODO - set target to 'Seeed-96Boards-Nitrogen' when mbed-os supports this
+ ( 0x9017, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_wio_emw3166_if', None, 'WIO_EMW3166' ), # TODO - set target to 'Seeed-96Boards-Nitrogen' when mbed-os supports this
+ ( 0x9900, VENDOR_TO_FAMILY('Nordic', 1), 'kl26z_microbit_if', 'kl26z_bl', 'Microbit' ),
+ ( 0x9901, VENDOR_TO_FAMILY('Nordic', 1), 'kl26z_microbit_if', 'kl26z_bl', 'Microbit' ),
+ ( 0xC000, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_cocorico_if', None, 'CoCo-ri-Co' ),
+ ( 0xC006, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_vbluno51_if', None, 'VBLUNO51' ),
+ ( 0xC005, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_mtconnect04s_if', None, 'MtConnect04S' ),
+ ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'kl26z_if', None, None ),
+ ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'k20dx_if', None, None ),
+ ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'k26f_if', None, None ),
+ ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_if', None, None ),
+ ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'lpc4322_if', None, None ),
+ ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'max32620_if', None, None ),
+ ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'max32625_if', None, None ),
+ ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'sam3u2c_if', None, None ),
+ ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_if', None, None ),
+]
+
+# Add new HICs here
+HIC_STRING_TO_ID = {
+ 'k20dx': 0x97969900,
+ 'kl26z': 0x97969901,
+ 'lpc11u35': 0x97969902,
+ 'sam3u2c': 0x97969903,
+ 'max32620': 0x97969904,
+ 'lpc4322': 0x97969905,
+ 'max32625': 0x97969906,
+ 'stm32f103xb': 0x97969908,
+ 'k26f': 0x97969909,
+ 'm48ssidae': 0x97969921,
+}
+
+BOARD_ID_LOCKED_WHEN_ERASED = set([
+ 0x0231, # K22F
+ 0x0224, # K28F
+ 0x0240, # K64F
+ 0x0214, # HEXIWEAR
+ 0x0228, # RAPID-IOT
+ 0x0311, # K66F
+ 0x0230, # K20DX
+ 0x0200, # KL25Z
+ 0x0205, # FRDM-KL28Z
+ 0x0203, # TWR-KL28Z72M
+ 0x0206, # TWR-KE18F
+ 0x0220, # KL46Z
+ 0x0210, # KL05Z
+ 0x0213, # FRDM-KE15Z
+ 0x0216, # HVP-KE18F
+ 0x0217, # FRDM-K82F
+ 0x0225, # FRDM-K32W042
+ 0x0261, # FRDM-KL27Z
+ 0x0262, # FRDM-KL43Z
+ 0x0218, # FRDM-KL82Z
+ 0x1022, # RO359B (K24F)
+ 0x0201, # KW41Z
+])
+
+BOARD_ID_SUPPORTING_PAGE_ERASE = set([
+ 0x0214, # HEXIWEAR
+ 0x0225, # FRDM-K32W042
+ 0x0226, # MIMXRT1020 EVK
+ 0x0227, # MIMXRT1050 EVK
+ 0x0228, # k20dx_rapid_iot_if
+ 0x0235, # lpc11u35_mini_iot_lpc54018_if
+ 0x0236, # LPCXpresso55S69
+ 0x0240, # K64F
+ 0x0311, # K66F
+ 0x0409, # MAX32630FTHR
+ 0x0415, # MAX32625MBED
+ 0x0418, # MAX32620FTHR
+ 0x0450, # mtb_ublox_odin_w2
+ 0x0456, # lpc11u35_mtb_murata_abz_078_if
+ 0x0457, # lpc11u35_mtb_rak811_if
+ 0x0460, # WISE-1570
+ 0x0468, # lpc11u35_mtb_stm32l475_if
+ 0x0469, # lpc11u35_mtb_stm32f439_if
+ 0x1101, # Nordic-nRF52-DK
+ 0x1102, # Nordic-nRF52840-DK
+ 0x1309, # NuMaker-M252KG
+ 0x1310, # NuMaker-IoT-M263A
+ 0x2410, # lpc11u35_mbed_cloud_connect_if
+ 0x3103, # dipdap_sdt51822b
+ 0x3104, # dipdap_sdt52832b
+ 0x3105, # dipdap_sdt64b
+ 0x3108, # dipdap_sdt32429b
+ 0x3110, # dipdap_sdt32439b
+ 0x3300, # dipdap_cc3220sf
+ 0x4600, # REALTEK-RTL8195AM
+ 0x5500, # GR-PEACH
+ 0x5501, # GR-LYCHEE
+])
+
+#Hack until these targets have an image with a valid vector table
+TARGET_WITH_BAD_VECTOR_TABLE_LIST = [
+ 'Microbit',
+ 'Nordic-nRF51-DK',
+ 'Nordic-nRF52-DK',
+ 'Nordic-nRF52840-DK',
+ 'Nordic-nRF51822',
+ 'Nordic-nRF51-Dongle',
+ 'Seeed-Arch-BLE',
+ 'mbed-HRM1017',
+ 'Switch-Science-mbed-TY51822r3',
+ 'RedBearLab-nRF51822',
+ 'RedBearLab-BLE-Nano',
+ 'Seeed-Tiny-BLE',
+ 'Seeed-Arch-Link',
+ 'SSCI-MBIT',
+ 'BlueNinja',
+ 'U-BLOX-EVK-NINA-B1',
+ 'VNG-VBLUno51',
+ 'REALTEK-RTL8195AM']
+
+BOARD_ID_TO_BUILD_TARGET = {config[0]: config[4] for config in
+ SUPPORTED_CONFIGURATIONS}
+FIRMWARE_SET = set((config[2] for config in SUPPORTED_CONFIGURATIONS))
+TARGET_SET = set((target[4] for target in SUPPORTED_CONFIGURATIONS if
+ target[4] is not None))
+
+TARGET_WITH_COMPILE_API_LIST = [config[4] for config in
+ SUPPORTED_CONFIGURATIONS if
+ config[4] is not None]
diff -r 000000000000 -r 01f31e923fe2 test/mbedapi.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/test/mbedapi.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,160 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+"""
+
+Usage example:
+
+python mbedapi.py --repo http://developer.mbed.org/users/dan/code/pubtest/
+--user dan --api http://developer.mbed.org --platform mbed-LPC1768
+--destdir /tmp/ --debug 2
+
+This will compile http://developer.mbed.org/users/dan/code/pubtest/
+for the 1768 and download the result.
+
+Examples of options:
+--extra_symbols "foo=bar,x=y"
+
+--replace_file "main.cpp:/tmp/replace_main.cpp"
+(can be repeated)
+
+"""
+import os
+import getpass
+import json
+import time
+import requests
+import logging
+
+MBED_API_SERVER = 'https://os.mbed.com/'
+
+
+def build_repo(user, password, repo, platform, destdir,
+ replace='', symbols='', clean=False, api=MBED_API_SERVER):
+
+ payload = {
+ 'clean': clean,
+ 'platform': platform,
+ 'repo': repo,
+ 'extra_symbols': symbols
+ }
+
+ if replace:
+ replace = []
+ for pair in replace:
+ dest = pair.split(':')[0]
+ src = pair.split(':')[1]
+ print(dest)
+ cwd = os.getcwd()
+ srcfile = open(os.path.join(cwd, src), 'r')
+ replace.append({dest: srcfile.read()})
+
+ payload['replace'] = json.dumps(replace)
+ logging.debug("Payload is: %s" % payload)
+
+ auth = (user, password,)
+
+ # send task to api
+ logging.debug(api + "/api/v2/tasks/compiler/start/" + "| data: " +
+ str(payload))
+ r = requests.post(api + "/api/v2/tasks/compiler/start/",
+ data=payload, auth=auth)
+
+ logging.debug(r.content)
+
+ if r.status_code != 200:
+ raise Exception("Error while talking to the mbed API")
+
+ uuid = json.loads(r.content)['result']['data']['task_id']
+ logging.debug("Task accepted and given ID: %s" % uuid)
+ success = False
+
+ # poll for output
+ for check in range(0, 40):
+ logging.debug("Checking for output: cycle %s of %s" % (check, 10))
+ time.sleep(2)
+ r = requests.get(api + "/api/v2/tasks/compiler/output/%s" %
+ uuid, auth=auth)
+ logging.debug(r.content)
+ response = json.loads(r.content)
+ messages = response['result']['data']['new_messages']
+ percent = 0
+ for message in messages:
+ if message.get('message'):
+ if message.get('type') != 'debug':
+ logging.info("[%s] %s" % (message['type'],
+ message['message']))
+ if message.get('action'):
+ if message.get('percent'):
+ percent = message['percent']
+ logging.info("[%s%% - %s] %s " % (percent, message['action'],
+ message.get('file', '')))
+
+ if response['result']['data']['task_complete']:
+ logging.info("Task completed.")
+ success = response['result']['data']['compilation_success']
+ logging.info("Compile success: %s" % (success))
+ break
+
+ # now download
+ if success:
+ logging.info("Downloading your binary")
+ params = {
+ 'repomode': True,
+ 'program': response['result']['data']['program'],
+ 'binary': response['result']['data']['binary'],
+ 'task_id': uuid
+ }
+ r = requests.get(api + "/api/v2/tasks/compiler/bin/",
+ params=params, auth=auth)
+ destination = os.path.join(destdir,
+ response['result']['data']['binary'])
+
+ with open(destination, 'wb') as fd:
+ for chunk in r.iter_content(1024):
+ fd.write(chunk)
+
+ logging.info("Finished!")
+ else:
+ raise Exception("Failed to build platform %s" % platform)
+ return destination
+
+if __name__ == "__main__":
+ import argparse
+ parser = argparse.ArgumentParser(description='Build an mbed repository.')
+ parser.add_argument('--user', type=str, help='Your username on mbed.', required=True)
+ parser.add_argument('--password', type=str, help='Your password on mbed.', default=None, required=False)
+ parser.add_argument('--api', type=str, help='URL to API server', required=False, default=MBED_API_SERVER)
+ parser.add_argument('--repo', type=str, help='URL of repository to build.', required=True)
+ parser.add_argument('--platform', type=str, help='Platform name', required=True)
+ parser.add_argument('--destdir', type=str, help='Binary destination directory', required=True)
+ parser.add_argument('--replace_file', type=str, help='Replace file and build. Can be repeated. Syntax: remotepath:localpath', required=False, action='append')
+ parser.add_argument('--extra_symbols', type=str, help='Provide extra symbols to build system', required=False, action='append')
+ parser.add_argument('--clean', action='store_true', help='Force clean build')
+ parser.add_argument('--debug', help='Show debugging info', required=False)
+
+ args = parser.parse_args()
+ if args.debug:
+ logging.basicConfig(level=logging.DEBUG)
+ else:
+ logging.basicConfig(level=logging.INFO)
+ if args.password is None:
+ args.password = getpass.getpass('mbed password: ')
+ build_repo(args.user, args.password, args.repo, args.platform,
+ args.destdir, args.replace_file, args.extra_symbols,
+ args.clean, args.api)
diff -r 000000000000 -r 01f31e923fe2 test/msd_test.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/test/msd_test.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,483 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+from __future__ import absolute_import
+from __future__ import division
+import os
+import time
+import shutil
+import six
+import info
+import intelhex
+from test_info import TestInfo
+
+from pyocd.core.helpers import ConnectHelper
+from pyocd.core.memory_map import MemoryType
+
+def _same(d1, d2):
+ assert type(d1) is bytearray
+ assert type(d2) is bytearray
+ for i in range(min(len(d1), len(d2))):
+ if d1[i] != d2[i]:
+ return False
+ if len(d1) != len(d2):
+ return False
+ return True
+
+MOCK_DIR_LIST = [
+ "test",
+ "blarg",
+ "very_long_directory_name",
+ "very_long_directory_name/and_subdirectory_name"
+]
+
+MOCK_FILE_LIST = [
+ (".test", "blarg"),
+ ("test/file1", "asdofahweaw"),
+ ("file.jpg", "file contents here")
+]
+
+MOCK_DIR_LIST_AFTER = [
+ "test2",
+ "blarg2",
+ "very_long_directory_name2",
+ "very_long_directory_name2/and_subdirectory_name"
+]
+
+MOCK_FILE_LIST_AFTER = [
+ (".test2", "blarg"),
+ ("test2/file12", "asdofahweaw"),
+ ("file2.jpg", "file contents here")
+]
+
+class MassStorageTester(object):
+
+ RETRY_COUNT = 5
+ DELAY_BEFORE_RETRY_S = 30
+
+ def __init__(self, board, parent_test, test_name):
+ self.board = board
+ self.parent_test = parent_test
+ self.test_name = test_name
+ self._expected_failure_msg = None
+ self._flush_time = 0.1
+ self._load_with_shutils = None
+ self._flush_size = None
+ self._programming_data = None
+ self._mock_file_list = []
+ self._mock_dir_list = []
+ self._mock_file_list_after = []
+ self._mock_dir_list_after = []
+ self._programming_file_name = None
+ self._start = 0
+
+ def set_shutils_copy(self, source_file_name):
+ """
+ Change mode to shutil file copy
+
+ This option cannot be used with set_programming_data.
+ """
+ assert type(source_file_name) is str
+ assert self._load_with_shutils is None
+ self._source_file_name = source_file_name
+ self._load_with_shutils = True
+
+ def set_programming_data(self, data, file_name):
+ """
+ Set data to program over mass storage
+
+ Data should be the conetents of the hex or binary file
+ being loaded. This option cannot be used with set_shutils_copy.
+ """
+ assert type(data) is bytearray
+ assert type(file_name) is str
+ assert(self._load_with_shutils is False or
+ self._load_with_shutils is None)
+ self._load_with_shutils = False
+ self._programming_data = data
+ self._programming_file_name = file_name
+
+ def set_flush_size(self, size):
+ """Set the block size to simulate a flush of"""
+ assert isinstance(size, six.integer_types)
+ self._flush_size = size
+
+ def set_expected_data(self, data, start=0):
+ """Data that should have been written to the device"""
+ assert data is None or type(data) is bytearray
+ self._expected_data = data
+ self._start = start
+
+ def set_expected_failure_msg(self, msg, error_type):
+ """Set the expected failure message as a string"""
+ assert msg is None or type(msg) is str
+ self._expected_failure_msg = msg
+ self._expected_failure_type = error_type
+
+ def add_mock_files(self, file_list):
+ """Add a list of tuples containing a file and contents"""
+ self._mock_file_list.extend(file_list)
+
+ def add_mock_dirs(self, dir_list):
+ """Add a list of directoies"""
+ self._mock_dir_list.extend(dir_list)
+
+ def add_mock_files_after_load(self, file_list):
+ """Add a list of tuples containing a file and contents"""
+ self._mock_file_list_after.extend(file_list)
+
+ def add_mock_dirs_after_load(self, dir_list):
+ """Add a list of directoies"""
+ self._mock_dir_list_after.extend(dir_list)
+
+ def _check_data_correct(self, expected_data, _):
+ """Return True if the actual data written matches the expected"""
+ data_len = len(expected_data)
+ data_loaded = self.board.read_target_memory(self._start, data_len)
+ return _same(expected_data, data_loaded)
+
+ def run(self):
+ for retry_count in range(self.RETRY_COUNT):
+ test_info = TestInfo(self.test_name)
+ if retry_count > 0:
+ test_info.info('Previous attempts %s' % retry_count)
+ try:
+ self._run(test_info)
+ except IOError:
+ time.sleep(self.DELAY_BEFORE_RETRY_S)
+ # Update board info since a remount could have occurred
+ self.board.update_board_info()
+ continue
+ self.parent_test.attach_subtest(test_info)
+ break
+ else:
+ raise Exception("Flashing failed after %i retries" %
+ self.RETRY_COUNT)
+
+ def _run(self, test_info):
+ # Expected data must be set, even if to None
+ assert hasattr(self, '_expected_data')
+
+ # Windows 8/10 workaround
+ # ----
+ # By default Windows 8 and 10 access and write to removable drives
+ # shortly after they are connected. If this occurs at the same time
+ # as a file copy the file could be sent out of order causing DAPLink
+ # programming to terminate early and report an error.
+ #
+ # This causes testing to intermittently fail with errors such as:
+ # - "The transfer timed out."
+ # - "File sent out of order by PC. Target might
+ # not be programmed correctly."
+ #
+ # To prevent Windows from writing to removable drives on connect
+ # drive indexing can be turned off with the following procedure:
+ # - Start the program "gpedit.msc"
+ # - Navigate to "Computer Configuration \ Administrative Templates
+ # \ Windows Components \ Search"
+ # - Enable the policy "Do not allow locations on removable drives
+ # to be added to libraries."
+ #
+ # Rather than requiring all testers of DAPLink make this setting
+ # change the below sleep has been added. This added delay allows
+ # windows to complete the writes it performs shortly after connect.
+ # This allows testing to be performed without interruption.
+ #
+ # Note - if drive indexing is turned off as mentioned above then
+ # this sleep is not needed.
+ time.sleep(2)
+
+ # Copy mock files before test
+ self._mock_file_list = []
+ for dir_name in self._mock_dir_list:
+ dir_path = self.board.get_file_path(dir_name)
+ os.mkdir(dir_path)
+ for file_name, file_contents in self._mock_file_list:
+ file_path = self.board.get_file_path(file_name)
+ with open(file_path, 'wb') as file_handle:
+ file_handle.write(file_contents)
+
+ programming_file_name = None
+ if self._programming_file_name is not None:
+ programming_file_name = \
+ self.board.get_file_path(self._programming_file_name)
+
+ # Write data to the file
+ start = time.time()
+ if self._load_with_shutils:
+ # Copy with shutils
+ shutil.copy(self._source_file_name, self.board.get_mount_point())
+ elif self._flush_size is not None:
+ # Simulate flushes during the file transfer
+ # Note - The file is explicitly opened and closed to more
+ # consistently simulate the undesirable behavior flush can
+ # cause. On Windows flushing a file causes the data to be
+ # written out immediately, but only sometimes causes the
+ # filesize to get updated.
+ size = len(self._programming_data)
+ for addr in range(0, size, self._flush_size):
+ data = self._programming_data[addr:addr + self._flush_size]
+ with open(programming_file_name, 'ab') as file_handle:
+ file_handle.write(data)
+ time.sleep(self._flush_time)
+ else:
+ # Perform a normal copy
+ with open(programming_file_name, 'wb') as load_file:
+ load_file.write(self._programming_data)
+ stop = time.time()
+ diff = stop - start
+ test_info.info('Loading took %ss' % diff)
+ if self._expected_data is not None:
+ test_info.info('Programming rate %sB/s' %
+ (len(self._expected_data) / diff))
+ if self._programming_data is not None:
+ test_info.info('MSD transfer rate %sB/s' %
+ (len(self._programming_data) / diff))
+
+ # Copy mock files after loading
+ self._mock_file_list = []
+ for dir_name in self._mock_dir_list_after:
+ dir_path = self.board.get_file_path(dir_name)
+ os.mkdir(dir_path)
+ for file_name, file_contents in self._mock_file_list_after:
+ file_path = self.board.get_file_path(file_name)
+ with open(file_path, 'w') as file_handle:
+ file_handle.write(file_contents)
+
+ self.board.wait_for_remount(test_info)
+
+ # Verify the disk is still valid
+ self.board.test_fs(test_info)
+
+ # Check various failure cases
+ msg, error_type = self.board.get_failure_message_and_type()
+ failure_expected = self._expected_failure_msg is not None
+ failure_occured = msg is not None
+ if failure_occured and not failure_expected:
+ test_info.failure('Device reported failure: "%s"' % msg.strip())
+ return
+ if failure_expected and not failure_occured:
+ test_info.failure('Failure expected but did not occur')
+ return
+ if failure_expected and failure_occured:
+ if msg == self._expected_failure_msg and error_type == self._expected_failure_type:
+ test_info.info(
+ 'Failure as expected: "%s, %s"' %
+ (msg.strip(), error_type.strip()))
+ elif msg != self._expected_failure_msg:
+ test_info.failure('Failure but wrong string: "%s" vs "%s"' %
+ (msg.strip(),
+ self._expected_failure_msg.strip()))
+ else:
+ test_info.failure(
+ 'Failure but wrong type: "%s" vs "%s"' %
+ (error_type.strip(), self._expected_failure_type.strip()))
+ return
+
+ # These cases should have been handled above
+ assert not failure_expected
+ assert not failure_occured
+
+ # If there is expected data then compare
+ if self._expected_data:
+ if self._check_data_correct(self._expected_data, test_info):
+ test_info.info("Data matches")
+ else:
+ test_info.failure('Data does not match')
+
+
+def test_mass_storage(workspace, parent_test):
+ """Test the mass storage endpoint
+
+ Requirements:
+ None
+
+ Positional arguments:
+ filename - A string containing the name of the file to load
+
+ Return:
+ True if the test passed, False otherwise
+ """
+ test_info = parent_test.create_subtest('test_mass_storage')
+
+ # Setup test
+ board = workspace.board
+ target = workspace.target
+ bin_file = target.bin_path
+ hex_file = target.hex_path
+ with open(bin_file, 'rb') as test_file:
+ bin_file_contents = bytearray(test_file.read())
+ with open(hex_file, 'rb') as test_file:
+ hex_file_contents = bytearray(test_file.read())
+ blank_bin_contents = bytearray([0xff]) * 0x2000
+ vectors_and_pad = bin_file_contents[0:32] + blank_bin_contents
+ locked_when_erased = board.get_board_id() in info.BOARD_ID_LOCKED_WHEN_ERASED
+ page_erase_supported = board.get_board_id() in info.BOARD_ID_SUPPORTING_PAGE_ERASE
+ bad_vector_table = target.name in info.TARGET_WITH_BAD_VECTOR_TABLE_LIST
+
+ intel_hex = intelhex.IntelHex(hex_file)
+ addresses = intel_hex.addresses()
+ addresses.sort()
+ start = addresses[0]
+
+ # Test loading a binary file with shutils
+ if not bad_vector_table:
+ test = MassStorageTester(board, test_info, "Shutil binary file load")
+ test.set_shutils_copy(bin_file)
+ test.set_expected_data(bin_file_contents, start)
+ test.run()
+
+ # Test loading a binary file with flushes
+ if not bad_vector_table:
+ test = MassStorageTester(board, test_info, "Load binary with flushes")
+ test.set_programming_data(bin_file_contents, 'image.bin')
+ test.set_expected_data(bin_file_contents, start)
+ test.set_flush_size(0x1000)
+ test.run()
+
+ # Test loading a hex file with shutils
+ test = MassStorageTester(board, test_info, "Shutil hex file load")
+ test.set_shutils_copy(hex_file)
+ test.set_expected_data(bin_file_contents, start)
+ test.run()
+
+ # Test loading a hex file with flushes
+ test = MassStorageTester(board, test_info, "Load hex with flushes")
+ test.set_programming_data(hex_file_contents, 'image.hex')
+ test.set_expected_data(bin_file_contents, start)
+ test.set_flush_size(0x1000)
+ test.run()
+
+ # Test loading a binary smaller than a sector
+ if not bad_vector_table:
+ test = MassStorageTester(board, test_info, "Load .bin smaller than sector")
+ test_data_size = 0x789
+ test_data = bin_file_contents[0:0 + test_data_size]
+ test.set_programming_data(test_data, 'image.bin')
+ test.set_expected_data(test_data, start)
+ test.run()
+
+ # Test loading a blank binary - this image should cause a timeout
+ # since it doesn't have a valid vector table
+ test = MassStorageTester(board, test_info, "Load blank binary")
+ test.set_programming_data(blank_bin_contents, 'image.bin')
+ test.set_expected_failure_msg("The transfer timed out.", "transient, user")
+ test.set_expected_data(None, start)
+ test.run()
+
+ # Test loading a blank binary with a vector table but padded with 0xFF.
+ # A blank image can lock some devices.
+ if not bad_vector_table:
+ test = MassStorageTester(board, test_info, "Load blank binary + vector table")
+ test.set_programming_data(vectors_and_pad, 'image.bin')
+ if locked_when_erased:
+ test.set_expected_failure_msg("The interface firmware ABORTED programming. Image is trying to set security bits", "user")
+ test.set_expected_data(None, start)
+ else:
+ test.set_expected_data(vectors_and_pad, start)
+ test.run()
+
+ # Test a normal load with dummy files created beforehand
+ test = MassStorageTester(board, test_info, "Extra Files")
+ test.set_programming_data(hex_file_contents, 'image.hex')
+ test.add_mock_dirs(MOCK_DIR_LIST)
+ test.add_mock_files(MOCK_FILE_LIST)
+ test.add_mock_dirs_after_load(MOCK_DIR_LIST_AFTER)
+ test.add_mock_files_after_load(MOCK_FILE_LIST_AFTER)
+ test.set_expected_data(bin_file_contents, start)
+ test.run()
+ # Note - it is not unexpected for an "Extra Files" test to fail
+ # when a binary file is loaded, since there is no way to
+ # tell where the end of the file is.
+
+ if page_erase_supported:
+ # Test page erase, a.k.a. sector erase by generating iHex with discrete addresses,
+ # programing the device then comparing device memory against expected content.
+ test = MassStorageTester(board, test_info, "Sector Erase")
+ with ConnectHelper.session_with_chosen_probe(unique_id=board.get_unique_id(), open_session=False) as session:
+ memory_map = session.target.memory_map
+ flash_regions = memory_map.get_regions_of_type(MemoryType.FLASH)
+
+ max_address = intel_hex.maxaddr()
+ # Create an object. We'll add the addresses of unused even blocks to it first, then unused odd blocks for each region
+ ih = intelhex.IntelHex()
+ # Add the content from test bin first
+ expected_bin_contents = bin_file_contents
+ for region_index, the_region in enumerate(flash_regions):
+ if the_region.is_boot_memory is False:
+ continue
+ flash_start = the_region.start
+ flash_length = the_region.length
+ block_size = the_region.blocksize
+
+ number_of_blocks = flash_length // block_size
+
+ # Sanity check the regions are contiguous
+ if region_index:
+ assert flash_start == (flash_regions[region_index - 1].start + flash_regions[region_index - 1].length)
+
+ if max_address >= (flash_start + flash_length):
+ # This bin image crosses this region, don't modify the content, go to the next region
+ continue
+ elif max_address >= flash_start:
+ # This bin image occupies partial region. Skip the used portion to avoid touching any security bits and pad the rest
+ expected_bin_contents += bytearray([0xff]) * (flash_start + flash_length - max_address - 1)
+ # Calculate the starting block after the image to avoid stumbling upon security bits
+ block_start = (max_address - flash_start) // block_size + 1
+ else:
+ # This bin image doesn't reach this region
+ expected_bin_contents += bytearray([0xff]) * flash_length
+ block_start = 0
+ # For all even blocks, overwrite all addresses with 0x55; for all odd blocks, overwrite all addresses with 0xAA
+ for pass_number in range (2):
+ if pass_number == 0:
+ modifier = 0x55
+ else:
+ modifier = 0xAA
+ block_start += 1
+ for block_idx in range(block_start, number_of_blocks, 2):
+ for address_to_modify in range (flash_start + block_idx * block_size, flash_start + (block_idx + 1) * block_size):
+ expected_bin_contents[address_to_modify] = modifier
+ ih[address_to_modify] = modifier
+ if not os.path.exists("tmp"):
+ os.makedirs("tmp")
+ # Write out the modified iHex to file
+ ih.tofile("tmp/interleave.hex", format='hex')
+ # Load this hex file with shutils
+ test.set_shutils_copy("tmp/interleave.hex")
+ test.set_expected_data(expected_bin_contents, start)
+ test.run()
+
+ # Finally, load a good binary
+ test = MassStorageTester(board, test_info, "Load good file to restore state")
+ test.set_programming_data(hex_file_contents, 'image.hex')
+ test.set_expected_data(bin_file_contents, start)
+ test.run()
+
+ # Ideas for future tests - contributions welcome
+ # -Zero length file
+ # -Corrupt hex file
+ # -Dummy files loaded before test
+ # -Very large file
+ # -Any MSD regressions
+ # -Security bits in hex files
+ # -Hex file with data at the end **
+ # -Hidden files
+ # -change file extension
+ # -Change size (make smaller)
+ # -change starting address
diff -r 000000000000 -r 01f31e923fe2 test/run_test.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/test/run_test.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,707 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+"""
+DAPLink validation and testing tool
+
+optional arguments:
+ -h, --help show this help message and exit
+ --targetdir TARGETDIR
+ Directory with pre-built target test images.
+ --user USER MBED username (required for compile-api)
+ --password PASSWORD MBED password (required for compile-api)
+ --firmwaredir FIRMWAREDIR
+ Directory with firmware images to test
+ --firmware {k20dx_k64f_if,lpc11u35_sscity_if,...} (run script with --help to see full list)
+ Firmware to test
+ --project-tool TOOL choices=['uvision', 'mbedcli'],'Tool used to compile the project',
+ default='uvision'
+ --logdir LOGDIR Directory to log test results to
+ --noloadif Skip load step for interface.
+ --notestendpt Dont test the interface USB endpoints.
+ --loadbl Load bootloader before test.
+ --testdl Run DAPLink specific tests. The DAPLink test tests
+ bootloader updates so use with caution
+ --testfirst If multiple boards of the same type are found only
+ test the first one.
+ --verbose {Minimal,Normal,Verbose,All}
+ Verbose output
+ --dryrun Print info on configurations but dont actually run
+ tests.
+ --force Try to run tests even if there are problems. Delete logs from previous run.
+Example usages
+------------------------
+
+Test all built projects in the repository:
+test_all.py --user <username> --password <password>
+
+Test everything on a single project in the repository:
+test_all.py --project <project> --testfirst --user <username>
+ --password <password>
+
+Verify that the USB endpoints are working correctly on
+an existing board with firmware already loaded:
+test_all.py --noloadif --user <username> --password <password>
+"""
+from __future__ import absolute_import
+from __future__ import print_function
+
+import os
+import shutil
+import argparse
+import subprocess
+from enum import Enum
+from hid_test import test_hid
+from serial_test import test_serial
+from msd_test import test_mass_storage
+from usb_test import test_usb
+from daplink_board import get_all_attached_daplink_boards
+from project_generator.generate import Generator
+from test_info import TestInfo
+from daplink_firmware import load_bundle_from_project, load_bundle_from_release
+from firmware import Firmware
+from target import load_target_bundle, build_target_bundle
+from test_daplink import daplink_test
+import info
+
+DEFAULT_TEST_DIR = './test_results'
+
+VERB_MINIMAL = 'Minimal' # Just top level errors
+VERB_NORMAL = 'Normal' # Top level errors and warnings
+VERB_VERBOSE = 'Verbose' # All errors and warnings
+VERB_ALL = 'All' # All errors
+VERB_LEVELS = [VERB_MINIMAL, VERB_NORMAL, VERB_VERBOSE, VERB_ALL]
+
+
+def test_endpoints(workspace, parent_test):
+ """Run tests to validate DAPLINK fimrware"""
+ test_info = parent_test.create_subtest('test_endpoints')
+ test_hid(workspace, test_info)
+ test_serial(workspace, test_info)
+ test_mass_storage(workspace, test_info)
+ test_usb(workspace, test_info)
+
+
+class TestConfiguration(object):
+ """Wrap all the resources needed to run a test"""
+ def __init__(self, name):
+ self.name = name
+ self.board = None
+ self.target = None
+ self.if_firmware = None
+ self.bl_firmware = None
+
+ def __str__(self):
+ name_board = '<None>'
+ name_target = '<None>'
+ name_if_firmware = '<None>'
+ name_bl_firmware = '<None>'
+ if self.board is not None:
+ name_board = self.board.name
+ if self.target is not None:
+ name_target = self.target.name
+ if self.if_firmware is not None:
+ name_if_firmware = self.if_firmware.name
+ if self.bl_firmware is not None:
+ name_bl_firmware = self.bl_firmware.name
+ return "APP=%s BL=%s Board=%s Target=%s" % (name_if_firmware,
+ name_bl_firmware,
+ name_board, name_target)
+
+
+class TestManager(object):
+ """Handle tests configuration running and results"""
+
+ class _STATE(Enum):
+ INIT = 0
+ CONFIGURED = 1
+ COMPLETE = 2
+
+ def __init__(self):
+ # By default test all configurations and boards
+ self._target_list = []
+ self._board_list = []
+ self._firmware_list = []
+ self._only_test_first = False
+ self._load_if = True
+ self._load_bl = True
+ self._test_daplink = True
+ self._test_ep = True
+
+ # Internal state
+ self._state = self._STATE.INIT
+ self._test_configuration_list = None
+ self._all_tests_pass = None
+ self._firmware_filter = None
+ self._untested_firmware = None
+
+ @property
+ def all_tests_pass(self):
+ assert self._all_tests_pass is not None, 'Must call run_tests first'
+ return self._all_tests_pass
+
+ def set_test_first_board_only(self, first):
+ """Only test one board of each type"""
+ assert isinstance(first, bool)
+ assert self._state is self._STATE.INIT
+ self._only_test_first = first
+
+ def set_load_if(self, load):
+ """Load new interface firmware before testing"""
+ assert isinstance(load, bool)
+ assert self._state is self._STATE.INIT
+ self._load_if = load
+
+ def set_load_bl(self, load):
+ """Load new bootloader firmware before testing"""
+ assert isinstance(load, bool)
+ assert self._state is self._STATE.INIT
+ self._load_bl = load
+
+ def set_test_daplink(self, run_test):
+ """Run DAPLink specific tests"""
+ assert isinstance(run_test, bool)
+ assert self._state is self._STATE.INIT
+ self._test_daplink = run_test
+
+ def set_test_ep(self, run_test):
+ """Test each endpoint - MSD, CDC, HID"""
+ assert isinstance(run_test, bool)
+ assert self._state is self._STATE.INIT
+ self._test_ep = run_test
+
+ def add_firmware(self, firmware_list):
+ """Add firmware to be tested"""
+ assert self._state is self._STATE.INIT
+ self._firmware_list.extend(firmware_list)
+
+ def add_boards(self, board_list):
+ """Add boards to be used for testing"""
+ assert self._state is self._STATE.INIT
+ self._board_list.extend(board_list)
+
+ def add_targets(self, target_list):
+ """Add targets to be used for testing"""
+ assert self._state is self._STATE.INIT
+ self._target_list.extend(target_list)
+
+ def set_firmware_filter(self, name_list):
+ """Test only the project names passed given"""
+ assert self._state is self._STATE.INIT
+ assert self._firmware_filter is None
+ self._firmware_filter = set(name_list)
+
+ def run_tests(self):
+ """Run all configurations"""
+ # Tests can only be run once per TestManager instance
+ assert self._state is self._STATE.CONFIGURED
+ self._state = self._STATE.COMPLETE
+
+ all_tests_pass = True
+ for test_configuration in self._test_configuration_list:
+ board = test_configuration.board
+ test_info = TestInfo(test_configuration.name)
+ test_configuration.test_info = test_info
+
+ test_info.info("Board: %s" % test_configuration.board)
+ test_info.info("Application: %s" %
+ test_configuration.if_firmware)
+ test_info.info("Bootloader: %s" %
+ test_configuration.bl_firmware)
+ test_info.info("Target: %s" % test_configuration.target)
+
+
+ if self._load_if:
+ if_path = test_configuration.if_firmware.hex_path
+ board.load_interface(if_path, test_info)
+
+ valid_bl = test_configuration.bl_firmware is not None
+ if self._load_bl and valid_bl:
+ bl_path = test_configuration.bl_firmware.hex_path
+ board.load_bootloader(bl_path, test_info)
+
+ board.set_check_fs_on_remount(True)
+
+ if self._test_daplink:
+ daplink_test(test_configuration, test_info)
+
+ if self._test_ep:
+ test_endpoints(test_configuration, test_info)
+
+ if test_info.get_failed():
+ all_tests_pass = False
+
+ self._all_tests_pass = all_tests_pass
+
+ def print_results(self, info_level):
+ assert self._state is self._STATE.COMPLETE
+ # Print info for boards tested
+ for test_configuration in self._test_configuration_list:
+ print('')
+ test_info = test_configuration.test_info
+ if info_level == VERB_MINIMAL:
+ test_info.print_msg(TestInfo.FAILURE, 0)
+ elif info_level == VERB_NORMAL:
+ test_info.print_msg(TestInfo.WARNING, None)
+ elif info_level == VERB_VERBOSE:
+ test_info.print_msg(TestInfo.WARNING, None)
+ elif info_level == VERB_ALL:
+ test_info.print_msg(TestInfo.INFO, None)
+ else:
+ # This should never happen
+ assert False
+
+ def write_test_results(self, directory, git_sha=None, local_changes=None,
+ info_level=TestInfo.INFO):
+ assert self._state is self._STATE.COMPLETE
+
+ assert not os.path.exists(directory)
+ os.mkdir(directory)
+
+ # Write out version of tools used for test
+ tools_file = directory + os.sep + 'requirements.txt'
+ with open(tools_file, "w") as file_handle:
+ command = ['pip', 'freeze']
+ subprocess.check_call(command, stdin=subprocess.PIPE,
+ stdout=file_handle,
+ stderr=subprocess.STDOUT)
+
+ # Write out each test result
+ for test_configuration in self._test_configuration_list:
+ test_info = test_configuration.test_info
+ file_path = directory + os.sep + test_info.name + '.txt'
+ with open(file_path, 'w') as file_handle:
+ file_handle.write("Test configuration: %s\n" %
+ test_configuration)
+ file_handle.write("Board: %s\n" % test_configuration.board)
+ file_handle.write("Application: %s\n" %
+ test_configuration.if_firmware)
+ file_handle.write("Bootloader: %s\n" %
+ test_configuration.bl_firmware)
+ file_handle.write("Target: %s\n" % test_configuration.target)
+ file_handle.write("\n")
+ test_info.print_msg(info_level, None, log_file=file_handle)
+
+ # Write out summary
+ summary_file = directory + os.sep + 'summary.txt'
+ with open(summary_file, "w") as file_handle:
+ # Overall result
+ if self.all_tests_pass:
+ file_handle.write("All tests pass\n\n")
+ else:
+ file_handle.write("One or more tests have failed\n\n")
+
+ if git_sha is not None and local_changes is not None:
+ file_handle.write("Git info for test:\n")
+ file_handle.write(" Git SHA: %s\n" % git_sha)
+ file_handle.write(" Local changes: %s\n" % local_changes)
+ file_handle.write("\n")
+
+ # Results for each test
+ file_handle.write("Test settings:\n")
+ file_handle.write(" Load application before test: %s\n" %
+ self._load_if)
+ file_handle.write(" Load bootloader before test: %s\n" %
+ self._load_bl)
+ file_handle.write(" Run DAPLink specific tests: %s\n" %
+ self._test_daplink)
+ file_handle.write(" Run endpoint tests: %s\n" %
+ self._test_ep)
+ file_handle.write("\n")
+
+ # Results for each test
+ file_handle.write("Tested configurations:\n")
+ for test_configuration in self._test_configuration_list:
+ test_info = test_configuration.test_info
+ test_passed = test_info.get_failed() == 0
+ result_str = 'Pass' if test_passed else 'Fail'
+ file_handle.write(" %s: %s\n" %
+ (test_configuration, result_str))
+ file_handle.write("\n")
+
+ # Untested firmware
+ untested_list = self.get_untested_firmware()
+ if len(untested_list) == 0:
+ file_handle.write("All firmware in package tested\n")
+ else:
+ file_handle.write("Untested firmware:\n")
+ for untested_fw in self.get_untested_firmware():
+ file_handle.write(" %s\n" % untested_fw.name)
+ file_handle.write("\n")
+
+ # Target test images
+ target_dir = directory + os.sep + 'target'
+ os.mkdir(target_dir)
+ for target in self._target_list:
+ new_hex = target_dir + os.sep + os.path.basename(target.hex_path)
+ shutil.copy(target.hex_path, new_hex)
+ new_bin = target_dir + os.sep + os.path.basename(target.bin_path)
+ shutil.copy(target.bin_path, new_bin)
+
+ def get_test_configurations(self):
+ assert self._state in (self._STATE.CONFIGURED,
+ self._STATE.COMPLETE)
+ return self._test_configuration_list
+
+ def get_untested_firmware(self):
+ assert self._state in (self._STATE.CONFIGURED,
+ self._STATE.COMPLETE)
+ return self._untested_firmware
+
+ def build_test_configurations(self, parent_test):
+ assert self._state is self._STATE.INIT
+ self._state = self._STATE.CONFIGURED
+ test_info = parent_test.create_subtest('Build test configuration')
+
+ # Create table mapping each board id to a list of boards with that ID
+ board_id_to_board_list = {}
+ for board in self._board_list:
+ board_id = board.get_board_id()
+ if board_id not in board_id_to_board_list:
+ board_id_to_board_list[board_id] = []
+ board_list = board_id_to_board_list[board_id]
+ if self._only_test_first and len(board_list) > 1:
+ # Ignore this board since we already have one
+ test_info.info('Ignoring extra boards of type 0x%x' %
+ board_id)
+ continue
+ board_list.append(board)
+
+ # Create a list for bootloader firmware and interface firmware
+ bootloader_firmware_list = []
+ filtered_interface_firmware_list = []
+ for firmware in self._firmware_list:
+ if firmware.type == Firmware.TYPE.BOOTLOADER:
+ bootloader_firmware_list.append(firmware)
+ elif firmware.type == Firmware.TYPE.INTERFACE:
+ name = firmware.name
+ if ((self._firmware_filter is None) or
+ (name in self._firmware_filter)):
+ filtered_interface_firmware_list.append(firmware)
+ else:
+ assert False, 'Unsupported firmware type "%s"' % firmware.type
+
+ # Create a table mapping name to object with that name
+ TARGET_NAME_TO_TARGET = {target.name: target for target in
+ self._target_list}
+ FIRMWARE_NAME_TO_FIRMWARE = {firmware.name: firmware for firmware in
+ filtered_interface_firmware_list}
+ BL_NAME_TO_BL = {firmware.name: firmware for firmware in
+ bootloader_firmware_list}
+
+ # Explicitly specified boards must be present
+ fw_name_set = set(fw.name for fw in filtered_interface_firmware_list)
+ if self._firmware_filter is not None:
+ assert self._firmware_filter == fw_name_set
+
+ # Create test configurations for each supported configuration
+ test_conf_list = []
+ untested_firmware = set(filtered_interface_firmware_list)
+ for board_id, family_id, fw_name, bl_fw_name, target_name in info.SUPPORTED_CONFIGURATIONS:
+ target = None
+ if_firmware = None
+ bl_firmware = None
+ if target_name in TARGET_NAME_TO_TARGET:
+ target = TARGET_NAME_TO_TARGET[target_name]
+ if fw_name in FIRMWARE_NAME_TO_FIRMWARE:
+ if_firmware = FIRMWARE_NAME_TO_FIRMWARE[fw_name]
+ if bl_fw_name in BL_NAME_TO_BL:
+ bl_firmware = BL_NAME_TO_BL[bl_fw_name]
+
+ target_required = self._test_ep
+ bl_required = self._load_bl or self._test_daplink
+ if if_firmware is None:
+ # Skip configuration
+ continue
+ if target_required and target is None:
+ # Skip configuration
+ test_info.info('No target to test firmware %s' % fw_name)
+ continue
+ if bl_required and bl_firmware is None:
+ # Skip configuration
+ test_info.info('No bootloader to test firmware %s' % fw_name)
+ continue
+ # Check if there is a board to test this firmware
+ # and if not skip it
+ if board_id not in board_id_to_board_list:
+ test_info.info('No board to test firmware %s' % fw_name)
+ continue
+
+ # Create a test configuration for each board
+ board_list = board_id_to_board_list[board_id]
+ for board in board_list:
+ test_conf = TestConfiguration(if_firmware.name + ' ' +
+ board.name)
+ test_conf.if_firmware = if_firmware
+ test_conf.bl_firmware = bl_firmware
+ test_conf.board = board
+ test_conf.target = target
+ test_conf_list.append(test_conf)
+ # remove this from the untested list
+ if if_firmware in untested_firmware:
+ untested_firmware.remove(if_firmware)
+ assert bl_firmware not in untested_firmware
+
+ self._untested_firmware = list(untested_firmware)
+ self._test_configuration_list = test_conf_list
+
+
+def get_firmware_names(project_dir):
+
+ # Save current directory
+ cur_dir = os.getcwd()
+ os.chdir(project_dir)
+ try:
+ all_names = set()
+ projects = list(Generator('projects.yaml').generate())
+ for project in projects:
+ assert project.name not in all_names
+ all_names.add(project.name)
+ finally:
+ # Restore the current directory
+ os.chdir(cur_dir)
+ return list(all_names)
+
+
+def get_git_info(project_dir):
+ cur_dir = os.getcwd()
+ os.chdir(project_dir)
+
+ # Get the git SHA.
+ try:
+ git_sha = subprocess.check_output(["git", "rev-parse",
+ "--verify", "HEAD"])
+ git_sha = git_sha.strip()
+ except (subprocess.CalledProcessError, WindowsError):
+ print("#> ERROR: Failed to get git SHA, do you "
+ "have git in your PATH environment variable?")
+ exit(-1)
+
+ # Check are there any local, uncommitted modifications.
+ try:
+ subprocess.check_output(["git", "diff", "--no-ext-diff",
+ "--quiet", "--exit-code"])
+ except subprocess.CalledProcessError:
+ git_has_changes = True
+ else:
+ git_has_changes = False
+
+ os.chdir(cur_dir)
+
+ return git_sha, git_has_changes
+
+
+def main():
+ self_path = os.path.abspath(__file__)
+ test_dir = os.path.dirname(self_path)
+ daplink_dir = os.path.dirname(test_dir)
+
+ # We make assumptions that break if user copies script file outside the test dir
+ if os.path.basename(test_dir) != "test":
+ print("Error - this script must reside in the test directory")
+ exit(-1)
+
+ git_sha, local_changes = get_git_info(daplink_dir)
+ firmware_list = get_firmware_names(daplink_dir)
+ firmware_choices = [firmware for firmware in firmware_list if
+ firmware.endswith('_if')]
+
+ description = 'DAPLink validation and testing tool'
+ parser = argparse.ArgumentParser(description=description)
+ parser.add_argument('--targetdir',
+ help='Directory with pre-built target test images.',
+ default=None)
+ parser.add_argument('--user', type=str, default=None,
+ help='MBED username (required for compile-api)')
+ parser.add_argument('--password', type=str, default=None,
+ help='MBED password (required for compile-api)')
+ parser.add_argument('--firmwaredir',
+ help='Directory with firmware images to test',
+ default=None)
+ parser.add_argument('--project-tool', choices=['uvision', 'mbedcli'],
+ help='Tool used to compile the project',
+ default='uvision')
+ parser.add_argument('--firmware', help='Firmware to test', action='append',
+ choices=firmware_choices, default=[], required=False)
+ parser.add_argument('--logdir', help='Directory to log test results to',
+ default=DEFAULT_TEST_DIR)
+ parser.add_argument('--noloadif', help='Skip load step for interface.',
+ default=False, action='store_true')
+ parser.add_argument('--notestendpt', help='Dont test the interface '
+ 'USB endpoints.', default=False, action='store_true')
+ parser.add_argument('--loadbl', help='Load bootloader before test.',
+ default=False, action='store_true')
+ parser.add_argument('--testdl', help='Run DAPLink specific tests. '
+ 'The DAPLink test tests bootloader updates so use'
+ 'with caution',
+ default=False, action='store_true')
+ parser.add_argument('--testfirst', help='If multiple boards of the same '
+ 'type are found only test the first one.',
+ default=False, action='store_true')
+ parser.add_argument('--verbose', help='Verbose output',
+ choices=VERB_LEVELS, default=VERB_NORMAL)
+ parser.add_argument('--dryrun', default=False, action='store_true',
+ help='Print info on configurations but dont '
+ 'actually run tests.')
+ parser.add_argument('--force', action='store_true', default=False,
+ help='Try to run tests even if there are problems. Delete logs from previous run.')
+ args = parser.parse_args()
+
+ use_prebuilt = args.targetdir is not None
+ use_compile_api = args.user is not None and args.password is not None
+
+ test_info = TestInfo('DAPLink')
+
+ # Validate args
+
+ # See if user wants to test endpoints. If yes and he didn't provide
+ # target test binaries, use the Compile API to build them
+ all_targets = None
+ if not args.notestendpt:
+ if not use_prebuilt and not use_compile_api:
+ print("Endpoint test requires target test images.")
+ print(" Directory with pre-built target test images")
+ print(" must be specified with '--targetdir'")
+ print("OR")
+ print(" developer.mbed.org login credentials must be ")
+ print(" specified with '--user' and '--password' so test ")
+ print(" images can be built with the RESTful Compile API.")
+ print("NOTE: you can skip the endpoint tests altogether ")
+ print("with --notestendpt")
+
+ exit(-1)
+
+ if args.targetdir is not None:
+ target_dir = args.targetdir
+ else:
+ target_dir = daplink_dir + os.sep + 'tmp'
+ build_target_bundle(target_dir, args.user, args.password, test_info)
+
+ target_bundle = load_target_bundle(target_dir)
+ all_targets = target_bundle.get_target_list()
+
+ if os.path.exists(args.logdir):
+ if args.force:
+ shutil.rmtree(args.logdir)
+ else:
+ print('Error - test results directory "%s" already exists' %
+ args.logdir)
+ exit(-1)
+
+ # Get all relevant info
+ if args.firmwaredir is None:
+ firmware_bundle = load_bundle_from_project(args.project_tool)
+ else:
+ firmware_bundle = load_bundle_from_release(args.firmwaredir)
+
+ all_firmware = firmware_bundle.get_firmware_list()
+ all_boards = get_all_attached_daplink_boards()
+
+ for board in all_boards:
+ if board.get_mode() == board.MODE_BL:
+ print('Switching to APP mode on board: %s' % board.unique_id)
+ try:
+ board.set_mode(board.MODE_IF)
+ except Exception:
+ print('Unable to switch mode on board: %s' % board.unique_id)
+
+ # Make sure firmware is present
+ firmware_explicitly_specified = len(args.firmware) != 0
+ if firmware_explicitly_specified:
+ all_firmware_names = set(fw.name for fw in all_firmware)
+ firmware_missing = False
+ for firmware_name in args.firmware:
+ if firmware_name not in all_firmware_names:
+ firmware_missing = True
+ test_info.failure('Cannot find firmware %s' % firmware_name)
+ if firmware_missing:
+ test_info.failure('Firmware missing - aborting test')
+ exit(-1)
+
+ # Create manager and add resources
+ tester = TestManager()
+ tester.add_firmware(all_firmware)
+ tester.add_boards(all_boards)
+ if all_targets is not None:
+ tester.add_targets(all_targets)
+ if firmware_explicitly_specified:
+ tester.set_firmware_filter(args.firmware)
+
+ # Configure test manager
+ tester.set_test_first_board_only(args.testfirst)
+ tester.set_load_if(not args.noloadif)
+ tester.set_test_ep(not args.notestendpt)
+ tester.set_load_bl(args.loadbl)
+ tester.set_test_daplink(args.testdl)
+
+ # Build test configurations
+ tester.build_test_configurations(test_info)
+
+ test_config_list = tester.get_test_configurations()
+ if len(test_config_list) == 0:
+ test_info.failure("Nothing that can be tested")
+ exit(-1)
+ else:
+ test_info.info('Test configurations to be run:')
+ index = 0
+ for test_config in test_config_list:
+ test_info.info(' %i: %s' % (index, test_config))
+ index += 1
+ test_info.info('')
+
+ untested_list = tester.get_untested_firmware()
+ if len(untested_list) == 0:
+ test_info.info("All firmware can be tested")
+ else:
+ test_info.info('Fimrware that will not be tested:')
+ for untested_firmware in untested_list:
+ test_info.info(' %s' % untested_firmware.name)
+ test_info.info('')
+
+ if firmware_explicitly_specified and len(untested_list) != 0:
+ test_info.failure("Exiting because not all firmware could be tested")
+ exit(-1)
+
+ # If this is a dryrun don't run tests, just print info
+ if args.dryrun:
+ exit(0)
+
+ # Run tests
+ tester.run_tests()
+
+ # Print test results
+ tester.print_results(args.verbose)
+ tester.write_test_results(args.logdir,
+ git_sha=git_sha,
+ local_changes=local_changes)
+
+ # Warn about untested boards
+ print('')
+ for firmware in tester.get_untested_firmware():
+ print('Warning - configuration %s is untested' % firmware.name)
+
+ if tester.all_tests_pass:
+ print("All boards passed")
+ exit(0)
+ else:
+ print("Test Failed")
+ exit(-1)
+
+
+if __name__ == "__main__":
+ main()
diff -r 000000000000 -r 01f31e923fe2 test/serial_test.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/test/serial_test.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,281 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+from __future__ import absolute_import
+from __future__ import division
+import queue
+import functools
+import serial
+import threading
+import time
+
+ERROR_TIMEOUT_SECONDS = 10.0
+
+
+def _same(d1, d2):
+ #Do a string or bytearray compare
+ if d1 != d2:
+ return False
+ return True
+
+# http://digital.ni.com/public.nsf/allkb/D37754FFA24F7C3F86256706005B9BE7
+standard_baud = [
+ 9600,
+ 14400,
+ 19200,
+ 28800,
+ 38400,
+ #56000, #TODO - uncomment once daplink-validation supports 56000 on nrf5x
+ 57600,
+ 115200,
+ ]
+timing_test_baud = standard_baud[3:]
+
+
+def calc_timeout(length, baud):
+ """Calculate a timeout given the data and baudrate
+
+ Positional arguments:
+ length - size of data to be sent
+ baud - baud rate to send data
+
+ Calculate a reasonable timeout given the supplied parameters.
+ This function adds slightly more time then is needed, to accont
+ for latency and various configurations.
+ """
+ return 12 * float(length) / float(baud) + 0.2
+
+
+class SerialTester(object):
+ """Helper object to buffer serial and setup baud"""
+
+ def __init__(self, port):
+ self.raw_serial = serial.Serial(port=port,bytesize=serial.EIGHTBITS, parity=serial.PARITY_NONE, stopbits=serial.STOPBITS_ONE, timeout=None, xonxoff=False, rtscts=False, write_timeout=None, dsrdtr=False, inter_byte_timeout=None, exclusive=None)
+ self.raw_serial.write_timeout = ERROR_TIMEOUT_SECONDS
+ self._queue = queue.Queue()
+ self._write_thread = threading.Thread(target=self._serial_main)
+ self._write_thread.start()
+
+ def __enter__(self):
+ return self
+
+ def __exit__(self, exception_type, value, traceback):
+ self._queue.put(None)
+ self._write_thread.join(ERROR_TIMEOUT_SECONDS)
+ assert not self._write_thread.isAlive(), "Thread join failed"
+ self.raw_serial.close()
+ self.raw_serial = None
+ return False
+
+ def new_session_with_baud(self, baud, parent_test):
+ """Start a new session by restarting target and setting baud"""
+ test_info = parent_test.create_subtest("Set Baud")
+
+ # Set baud to 115200
+ self.raw_serial.baudrate = 115200
+ self.raw_serial.timeout = 1.0
+
+ # Reset the target
+ self.raw_serial.reset_output_buffer()
+ self.raw_serial.reset_input_buffer()
+ self.raw_serial.sendBreak()
+
+ # Wait until the target is initialized
+ expected_resp = "{init}"
+ resp = self.read(len(expected_resp))
+ if not _same(resp.decode(), expected_resp):
+ test_info.failure("Fail on init: %s" % resp)
+ return False
+
+ # Change baudrate to that of the first test
+ command = "{baud:%i}" % baud
+ self.write(command.encode())
+ resp = self.read(len(command))
+ if not _same(resp.decode(), command):
+ test_info.failure("Fail on baud command: %s" % resp)
+ return False
+
+ # Update baud of local serial port
+ self.raw_serial.baudrate = baud
+
+ # Read the response indicating that the baudrate
+ # on the target has changed
+ expected_resp = "{change}"
+ resp = self.read(len(expected_resp))
+ if not _same(resp.decode(), expected_resp):
+ test_info.failure("Fail on baud change %s" % resp)
+ return False
+
+ # Set default timeout
+ self.raw_serial.timeout = ERROR_TIMEOUT_SECONDS
+
+ # Success
+ return True
+
+ def read(self, length):
+ """Read serial data"""
+ return self.raw_serial.read(length)
+
+ def write(self, data):
+ """Write serial port data in the background"""
+ func = functools.partial(self.raw_serial.write, data)
+ self._queue.put(func)
+
+ def set_read_timeout(self, timeout):
+ """Set timeout for read operations"""
+ assert self._queue.empty(), "Queue must be empty to change timeout"
+ self.raw_serial.timeout = timeout
+
+ def flush(self):
+ """Wait for all writes to complete"""
+ self._queue.join()
+ assert self._queue.empty()
+
+ def _serial_main(self):
+ """Write helper thread"""
+ while True:
+ task = self._queue.get(True)
+ if task is None:
+ self._queue.task_done()
+ # End of processing is an empty task
+ break
+ try:
+ task()
+ except serial.SerialTimeoutException:
+ pass
+ self._queue.task_done()
+
+
+def test_serial(workspace, parent_test):
+ """Test the serial port endpoint
+
+ Requirements:
+ -daplink-validation must be loaded for the target.
+
+ Positional arguments:
+ port - the serial port to open as a string
+
+ Return:
+ True if the test passed, False otherwise
+ """
+ test_info = parent_test.create_subtest("Serial test")
+ board = workspace.board
+ port = board.get_serial_port()
+ test_info.info("Testing serial port %s" % port)
+
+ # Note: OSX sends a break command when a serial port is closed.
+ # To avoid problems while testing keep the serial port open the
+ # whole time. Use the property 'baudrate' to change the baud
+ # instead of opening a new instance.
+
+ with SerialTester(port) as sp:
+
+ # Generate a 4KB block of dummy data
+ # and test supported baud rates
+ test_data = [i for i in range(0, 256)] * 4 * 4
+ test_data = bytearray(test_data)
+ for baud in standard_baud:
+
+ test_info.info("Testing baud %i" % baud)
+ success = sp.new_session_with_baud(baud, test_info)
+ if not success:
+ test_info.failure("Unable to setup session")
+ continue
+
+ # Perform test
+ sp.write(test_data)
+ resp = sp.read(len(test_data))
+ if _same(test_data, resp):
+ test_info.info("Pass")
+ else:
+ test_info.failure("Fail on baud %s" % baud)
+
+ # Timing stress test - send data at critical points
+ # in time like right as the transmitter is turned off
+ # ------------------
+ # Test sequence
+ # 1. Send a block of data (vary size for the test)
+ # 2. Wait until 1 byte is read back
+ # 3. Write 1 byte
+ # 4. Read back all data
+ test_data = [i for i in range(0, 256)] * 4 * 4
+ test_data = bytearray(test_data)
+ for baud in timing_test_baud:
+
+ test_info.info("Timing test baud %i" % baud)
+ success = sp.new_session_with_baud(baud, test_info)
+ if not success:
+ test_info.failure("Unable to setup session")
+ continue
+
+ test_pass = True
+ for data_size in range(1, 10):
+ data = test_data[0:data_size + 1]
+ for _ in range(0, 1000):
+ resp = bytearray()
+
+ sp.write(data[0:data_size])
+ resp += sp.read(1)
+ sp.write(data[-1:])
+ resp += sp.read(data_size)
+ sp.flush()
+ if not _same(data, resp):
+ test_pass = False
+ test_info.info("fail size - %s" % data_size)
+ break
+
+ if test_pass:
+ test_info.info("Pass")
+ else:
+ test_info.failure("Fail on timing test with baud %s"
+ % baud)
+
+ # Setting change smoke test - reconfigure settings while
+ # in the middle of a transfer and verify nothing bad
+ test_data = [i for i in range(0, 128)]
+ test_data = bytearray(test_data)
+ sp.new_session_with_baud(115200, test_info)
+ sp.set_read_timeout(0)
+ for baud in standard_baud:
+ sp.raw_serial.baudrate = baud
+ sp.write(test_data)
+ xfer_time = float(len(test_data) * 10) / float(baud)
+ time.sleep(xfer_time / 2)
+ # Discard data
+ sp.read(1024)
+ # Read any leftover data
+ sp.flush()
+ sp.raw_serial.baudrate = 115200
+ sp.set_read_timeout(1.0)
+ sp.read(128 * len(standard_baud))
+
+ # Generate a 8 KB block of dummy data
+ # and test a large block transfer
+ test_data = [i for i in range(0, 256)] * 4 * 8
+ test_data = bytearray(test_data)
+ sp.new_session_with_baud(115200, test_info)
+
+ sp.write(test_data)
+ resp = sp.read(len(test_data))
+ if _same(resp, test_data):
+ test_info.info("Block test passed")
+ else:
+ test_info.failure("Block test failed")
+
+ # Refresh to check for asserts
+ board.refresh(test_info)
diff -r 000000000000 -r 01f31e923fe2 test/stress_tests/cdc_stress_test.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/test/stress_tests/cdc_stress_test.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,90 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2016-2017, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+import mbed_lstools
+import threading
+import time
+import serial
+
+should_exit = False
+exit_cond = threading.Condition()
+print_mut = threading.RLock()
+global_start_time = time.time()
+
+
+def _get_time():
+ return time.time() - global_start_time
+
+
+def sync_print(msg):
+ with print_mut:
+ print(msg)
+
+
+def cdc_throughput_main(thread_index, serial_port):
+ global should_exit
+ ser = None
+ try:
+ count = 0
+ while not should_exit:
+ ser = serial.Serial(serial_port) # open serial port
+ ser.baudrate = 115200
+ ser.write("this is test data")
+ ser.baudrate = 9600
+ ser.write("more test data")
+ ser.close()
+
+ if count % 10 == 0:
+ sync_print("Thread %i on loop %10i at %.6f - %s - port %s" %
+ (thread_index, count, _get_time(),
+ time.strftime("%H:%M:%S"), serial_port))
+ count += 1
+
+ except:
+ sync_print("Error on thread %i serial port %s" %
+ (thread_index, serial_port))
+ if ser is not None:
+ ser.close()
+ with exit_cond:
+ should_exit = 1
+ exit_cond.notify_all()
+ raise
+
+
+def main():
+ global should_exit
+ lstools = mbed_lstools.create()
+ mbed_list = lstools.list_mbeds()
+ for thread_index, mbed in enumerate(mbed_list):
+ cdc_thread = threading.Thread(target=cdc_throughput_main,
+ args=(thread_index, mbed['serial_port']))
+ cdc_thread.start()
+
+ try:
+ with exit_cond:
+ while not should_exit:
+ exit_cond.wait(1)
+ except KeyboardInterrupt:
+ pass
+ should_exit = True
+
+ sync_print("Exiting")
+
+
+if __name__ == "__main__":
+ main()
diff -r 000000000000 -r 01f31e923fe2 test/stress_tests/hid_usb_test.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/test/stress_tests/hid_usb_test.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,85 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2016-2017, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+import mbed_lstools
+import threading
+import time
+import pyocd
+
+should_exit = False
+exit_cond = threading.Condition()
+print_mut = threading.RLock()
+global_start_time = time.time()
+
+
+def _get_time():
+ return time.time() - global_start_time
+
+
+def sync_print(msg):
+ with print_mut:
+ print(msg)
+
+
+def hid_main(thread_index, board_id):
+ global should_exit
+ count = 0
+ try:
+ device = pyocd.probe.pydapaccess.DAPAccess.get_device(board_id)
+ while not should_exit:
+ device.open()
+ info = device.vendor(0)
+ info = str(bytearray(info[1:1 + info[0]]))
+ assert info == board_id
+ device.close()
+ if count % 100 == 0:
+ sync_print("Thread %i on loop %10i at %.6f - %s - board %s" %
+ (thread_index, count, _get_time(),
+ time.strftime("%H:%M:%S"), board_id))
+ count += 1
+
+ except:
+ sync_print("Thread %i exception board %s" % (thread_index, board_id))
+ with exit_cond:
+ should_exit = 1
+ exit_cond.notify_all()
+ raise
+
+
+def main():
+ global should_exit
+ lstools = mbed_lstools.create()
+ mbed_list = lstools.list_mbeds()
+ for thread_index, mbed in enumerate(mbed_list):
+ msd_thread = threading.Thread(target=hid_main,
+ args=(thread_index, mbed['target_id']))
+ msd_thread.start()
+
+ try:
+ with exit_cond:
+ while not should_exit:
+ exit_cond.wait(1)
+ except KeyboardInterrupt:
+ pass
+ should_exit = True
+
+ sync_print("Exiting")
+
+
+if __name__ == "__main__":
+ main()
diff -r 000000000000 -r 01f31e923fe2 test/stress_tests/msd_remount_test.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/test/stress_tests/msd_remount_test.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,149 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2016-2017, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+import mbed_lstools
+import threading
+import time
+import os
+import sys
+
+
+# This prevents the following error message from getting
+# displayed on windows if the mbed dismounts unexpectedly
+# during a transfer:
+# There is no disk in the drive. Please insert a disk into
+# drive \Device\<Harddiskx>\<rdrive>
+def disable_popup():
+ if sys.platform.startswith("win"):
+ # pylint: disable=invalid-name
+ import ctypes
+ SEM_FAILCRITICALERRORS = 1
+ GetErrorMode = \
+ ctypes.windll.kernel32.GetErrorMode # @UndefinedVariable
+ GetErrorMode.restype = ctypes.c_uint
+ GetErrorMode.argtypes = []
+ SetErrorMode = \
+ ctypes.windll.kernel32.SetErrorMode # @UndefinedVariable
+ SetErrorMode.restype = ctypes.c_uint
+ SetErrorMode.argtypes = [ctypes.c_uint]
+
+ err_mode = GetErrorMode()
+ err_mode |= SEM_FAILCRITICALERRORS
+ SetErrorMode(err_mode)
+
+MAX_REMOUNT_TIME = 5 * 60
+should_exit = False
+exit_cond = threading.Condition()
+print_mut = threading.RLock()
+global_start_time = time.time()
+
+
+class ExitException(Exception):
+ pass
+
+
+def _get_time():
+ return time.time() - global_start_time
+
+
+def sync_print(msg):
+ with print_mut:
+ print(msg)
+
+
+def get_mount_point(board_id):
+ lstools = mbed_lstools.create()
+ mbed_list = lstools.list_mbeds()
+ for mbed in mbed_list:
+ if mbed['target_id'] == board_id:
+ return mbed['mount_point']
+ else:
+ Exception("Board %s not found" % board_id)
+
+
+def msd_remount_main(thread_index, board_id):
+ global should_exit
+ try:
+ mount_point = get_mount_point(board_id)
+ while True:
+ if should_exit:
+ raise ExitException()
+
+ # Trigger a remount
+ sync_print("Triggering remount for %i %s - %s at %.6f - %s" %
+ (thread_index, mount_point, board_id, _get_time(),
+ time.strftime("%H:%M:%S")))
+ file_path = mount_point + "/" + "refresh.act"
+ with open(file_path, "wb") as _:
+ pass
+
+ # Wait for board to dismount
+ start_time = time.time()
+ while os.path.exists(mount_point):
+ if should_exit:
+ raise ExitException()
+ if time.time() - start_time > MAX_REMOUNT_TIME:
+ raise Exception("Board remount timed out")
+ time.sleep(0.1)
+ sync_print("Drive %s dismount" % mount_point)
+
+ # Wait for drive to come back
+ mount_point = None
+ start_time = time.time()
+ while mount_point is None:
+ if should_exit:
+ raise ExitException()
+ mount_point = get_mount_point(board_id)
+ if time.time() - start_time > MAX_REMOUNT_TIME:
+ raise Exception("Board remount timed out")
+ time.sleep(0.1)
+ assert os.path.exists(mount_point)
+
+ sync_print("Remount complete as %s" % mount_point)
+ except ExitException:
+ pass
+ except:
+ sync_print("Thread %i exception board %s" % (thread_index, board_id))
+ with exit_cond:
+ should_exit = 1
+ exit_cond.notify_all()
+ raise
+
+
+def main():
+ global should_exit
+ disable_popup()
+ lstools = mbed_lstools.create()
+ mbed_list = lstools.list_mbeds()
+ for thread_index, mbed in enumerate(mbed_list):
+ msd_thread = threading.Thread(target=msd_remount_main,
+ args=(thread_index, mbed['target_id']))
+ msd_thread.start()
+
+ try:
+ with exit_cond:
+ while not should_exit:
+ exit_cond.wait(1)
+ except KeyboardInterrupt:
+ pass
+ should_exit = True
+
+ sync_print("Exiting")
+
+if __name__ == "__main__":
+ main()
diff -r 000000000000 -r 01f31e923fe2 test/target.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/test/target.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,162 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+from __future__ import absolute_import
+import os
+import time
+import info
+import mbedapi
+from test_info import TestInfoStub
+from intelhex import IntelHex
+
+TEST_REPO = 'https://developer.mbed.org/users/c1728p9/code/daplink-validation/'
+
+
+def load_target_bundle(directory):
+ return TargetBundle(directory)
+
+
+class TargetBundle(object):
+
+ def __init__(self, directory):
+ dir_contents = os.listdir(directory)
+ name_to_target = {}
+ for name in dir_contents:
+ base_name, extension = os.path.splitext(name)
+ path = directory + os.sep + name
+ if os.path.isdir(path):
+ # Directories are unused
+ pass
+ elif os.path.isfile(path):
+ if extension not in ('.bin', '.hex'):
+ continue
+ if base_name not in name_to_target:
+ name_to_target[base_name] = Target(base_name)
+ if extension == '.bin':
+ name_to_target[base_name].set_bin_path(path)
+ elif extension == '.hex':
+ name_to_target[base_name].set_hex_path(path)
+ else:
+ # Unsupported file type
+ pass
+ else:
+ assert False
+ all_targets = list(name_to_target.values())
+ self._target_list = [target for target in all_targets if target.valid]
+
+ def get_target_list(self):
+ """Return the target objects associated with this bundle"""
+ return self._target_list
+
+
+def build_target_bundle(directory, username, password, parent_test=None):
+ """Build target firmware package"""
+ if parent_test is None:
+ parent_test = TestInfoStub()
+ target_names = info.TARGET_WITH_COMPILE_API_LIST
+ for build_name in target_names:
+ name_base = os.path.normpath(directory + os.sep + build_name)
+ target_hex_path = name_base + '.hex'
+ target_bin_path = name_base + '.bin'
+
+ # Build target test image
+ test_info = parent_test.create_subtest('Building target %s' %
+ build_name)
+ if not os.path.isdir(directory):
+ os.mkdir(directory)
+ # Remove previous build files
+ if os.path.isfile(target_hex_path):
+ os.remove(target_hex_path)
+ if os.path.isfile(target_bin_path):
+ os.remove(target_bin_path)
+ test_info.info('Starting remote build')
+ start = time.time()
+ built_file = mbedapi.build_repo(username, password,
+ TEST_REPO, build_name,
+ directory)
+ stop = time.time()
+ test_info.info("Build took %s seconds" % (stop - start))
+ extension = os.path.splitext(built_file)[1].lower()
+ assert extension == '.hex' or extension == '.bin'
+ if extension == '.hex':
+ intel_hex = IntelHex(built_file)
+ # Only supporting devices with the starting
+ # address at 0 currently
+ assert intel_hex.minaddr() == 0
+ intel_hex.tobinfile(target_bin_path)
+ os.rename(built_file, target_hex_path)
+ if extension == '.bin':
+ intel_hex = IntelHex()
+ intel_hex.loadbin(built_file, offset=0)
+ intel_hex.tofile(target_hex_path, 'hex')
+ os.rename(built_file, target_bin_path)
+
+ # Assert that required files are present
+ assert os.path.isfile(target_hex_path)
+ assert os.path.isfile(target_bin_path)
+
+
+class Target(object):
+
+ def __init__(self, name, hex_path=None, bin_path=None):
+ self._name = name
+ self._valid = False
+ self._hex_path = None
+ self._bin_path = None
+ if hex_path is not None:
+ self.set_hex_path(hex_path)
+ if bin_path is not None:
+ self.set_bin_path(bin_path)
+ self._valid = True
+
+ def __str__(self):
+ return "Name=%s" % self.name
+
+ def set_hex_path(self, path):
+ base_name = os.path.basename(path)
+ assert self._hex_path is None
+ assert base_name == self._name + '.hex'
+ path = os.path.abspath(path)
+ assert os.path.isfile(path)
+ self._hex_path = path
+
+ def set_bin_path(self, path):
+ base_name = os.path.basename(path)
+ assert self._bin_path is None
+ assert base_name == self._name + '.bin'
+ path = os.path.abspath(path)
+ assert os.path.isfile(path)
+ self._bin_path = path
+
+ @property
+ def valid(self):
+ hex_valid = self._hex_path is not None
+ bin_valid = self._bin_path is not None
+ return hex_valid and bin_valid and self._valid
+
+ @property
+ def name(self):
+ return self._name
+
+ @property
+ def hex_path(self):
+ return self._hex_path
+
+ @property
+ def bin_path(self):
+ return self._bin_path
diff -r 000000000000 -r 01f31e923fe2 test/test_daplink.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/test/test_daplink.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,449 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+from __future__ import absolute_import
+import future
+import os
+import binascii
+import intelhex
+import sys
+
+try:
+ from cStringIO import StringIO
+except ImportError:
+ from io import StringIO
+
+from msd_test import (MassStorageTester, MOCK_DIR_LIST, MOCK_FILE_LIST,
+ MOCK_DIR_LIST_AFTER, MOCK_FILE_LIST_AFTER)
+
+TRIGGER_ASSERT_FILE_NAME = "ASSERT.ACT"
+ASSERT_FILE_NAME = "ASSERT.TXT"
+NEED_BL_FILE_NAME = "NEED_BL.TXT"
+DAPLINK_VECTOR_TABLE_OFFSET = 0x00
+DAPLINK_BUILD_KEY_OFFSET = 0x20
+DAPLINK_HIC_ID_OFFSET = 0x24
+
+
+def intel_hex_get_sections(intel_hex):
+ """Return list of address, size tuples"""
+ addresses = intel_hex.addresses()
+ addresses.sort()
+ section_list = []
+ section_start = None
+ last_addr = None
+ for addr in addresses:
+ if section_start is None:
+ section_start = addr
+ last_addr = addr
+ if addr == last_addr or addr == last_addr + 1:
+ last_addr = addr
+ else:
+ section_size = last_addr - section_start + 1
+ section_list.append((section_start, section_size))
+ section_start = addr
+ last_addr = addr
+ if section_start is not None:
+ section_size = last_addr - section_start + 1
+ section_list.append((section_start, section_size))
+ return section_list
+
+
+def bin_data_to_hex_data(addr, data):
+ """Covert binary data to a string in intel hex format"""
+ intel_hex = intelhex.IntelHex()
+ if sys.version_info >= (3,0):
+ data = data.decode('latin1')
+ intel_hex.puts(addr, data)
+ sio = StringIO()
+ intel_hex.tofile(sio, format='hex')
+ hex_data = sio.getvalue()
+ return bytearray(hex_data.encode('latin1'))
+
+
+class DLMassStorageTester(MassStorageTester):
+ """DAPLink mass storage tester"""
+
+ def __init__(self, board, parent_test, test_name, test_mode):
+ super(DLMassStorageTester, self).__init__(board, parent_test,
+ test_name)
+ self._expected_mode = None
+ self._actual_mode = None
+ self._test_mode = test_mode
+ if self._test_mode == board.MODE_IF:
+ self._crc_tag = board.KEY_BL_CRC
+ elif self._test_mode == board.MODE_BL:
+ self._crc_tag = board.KEY_IF_CRC
+ else:
+ assert False
+
+ def _run(self, test_info):
+ assert self._expected_mode is not None
+ # Set board to the correct mode before running test
+ self.board.set_mode(self._test_mode)
+ self._actual_mode = None
+
+ super(DLMassStorageTester, self)._run(test_info)
+
+ if self._actual_mode is None:
+ # Set expected mode if it hasn't been set in _check_data_correct
+ self._actual_mode = self.board.get_mode()
+ if self._expected_mode is not self._actual_mode:
+ test_info.failure("Wrong mode after test - Expected "
+ " %s got %s" % (self._expected_mode,
+ self._actual_mode))
+
+ def set_expected_mode(self, mode):
+ self._expected_mode = mode
+
+ def _check_data_correct(self, expected_data, test_info):
+ board = self.board
+ self._actual_mode = self.board.get_mode()
+ board.set_mode(self._test_mode)
+ if self._crc_tag not in board.details_txt:
+ test_info.info("CRC not in details.txt")
+ return False
+ actual_crc32 = int(self.board.details_txt[self._crc_tag], 16)
+ expected_crc32 = binascii.crc32(expected_data[0:-4]) & 0xFFFFFFFF
+ test_info.info("Expected CRC: 0x%08x, actual crc: 0x%08x" %
+ (expected_crc32, actual_crc32))
+ return actual_crc32 == expected_crc32
+
+
+def daplink_test(workspace, parent_test):
+ board = workspace.board
+ interface = workspace.if_firmware
+ test_info = parent_test.create_subtest('daplink_test')
+
+ intel_hex = intelhex.IntelHex(interface.hex_path)
+ section_list = intel_hex_get_sections(intel_hex)
+ assert len(section_list) == 1, ("Only 1 section supported, found %s" %
+ len(section_list))
+ start, length = section_list[0]
+
+ bin_data = bytearray(intel_hex.tobinarray(start=start, size=length))
+ sio = StringIO()
+ intel_hex.tofile(sio, format='hex')
+ hex_data = sio.getvalue()
+ hex_data = bytearray(hex_data.encode('latin1'))
+
+ # Make sure asserts work as expected
+ test_assert(workspace, test_info)
+
+ # Test loading a binary file with shutils
+ test = DLMassStorageTester(board, test_info, "Shutil binary file load "
+ "interface", board.MODE_BL)
+ test.set_shutils_copy(interface.bin_path)
+ test.set_expected_data(bin_data, start)
+ test.set_expected_mode(board.MODE_IF)
+ test.run()
+
+ # Test loading a hex file with shutils
+ test = DLMassStorageTester(board, test_info, "Shutil hex file load "
+ "interface", board.MODE_BL)
+ test.set_shutils_copy(interface.hex_path)
+ test.set_expected_data(bin_data, start)
+ test.set_expected_mode(board.MODE_IF)
+ test.run()
+
+ test_file_type('bin', board.MODE_BL, board, test_info, start, bin_data)
+ test_file_type('hex', board.MODE_BL, board, test_info, start, bin_data)
+
+ # Test bootloader updates
+ firmware = workspace.bl_firmware
+ intel_hex = intelhex.IntelHex(firmware.hex_path)
+ section_list = intel_hex_get_sections(intel_hex)
+ assert len(section_list) == 1, ("Only 1 section supported, found %s" %
+ len(section_list))
+ start, length = section_list[0]
+
+ bin_data = bytearray(intel_hex.tobinarray(start=start, size=length))
+ sio = StringIO()
+ intel_hex.tofile(sio, format='hex')
+ hex_data = sio.getvalue()
+ hex_data = bytearray(hex_data.encode('latin1'))
+
+ # Test loading a binary file with shutils
+ test = DLMassStorageTester(board, test_info, "Shutil binary file load "
+ "bootloader", board.MODE_IF)
+ test.set_shutils_copy(firmware.bin_path)
+ test.set_expected_data(bin_data, start)
+ test.set_expected_mode(board.MODE_IF)
+ test.run()
+
+ # Test loading a hex file with shutils
+ test = DLMassStorageTester(board, test_info, "Shutil hex file load "
+ "bootloader", board.MODE_IF)
+ test.set_shutils_copy(firmware.hex_path)
+ test.set_expected_data(bin_data, start)
+ test.set_expected_mode(board.MODE_IF)
+ test.run()
+
+ test_file_type('bin', board.MODE_IF, board, test_info, start, bin_data)
+ test_file_type('hex', board.MODE_IF, board, test_info, start, bin_data)
+
+
+def test_assert(workspace, parent_test):
+ """Test that asserts work and persist across modes"""
+ board = workspace.board
+ test_info = parent_test.create_subtest('Assert Test')
+
+ board.set_assert_auto_manage(False)
+
+ board.set_mode(board.MODE_IF)
+
+ # Create a test assert file
+ test_info.info('Triggering assert by creating %s' %
+ TRIGGER_ASSERT_FILE_NAME)
+ trigger_assert_path = board.get_file_path(TRIGGER_ASSERT_FILE_NAME)
+ with open(trigger_assert_path, 'wb') as _:
+ pass
+ board.wait_for_remount(test_info)
+
+ test_info.info('Checking that assert file was created')
+ board.set_mode(board.MODE_IF)
+ assert_path = board.get_file_path(ASSERT_FILE_NAME)
+ if not os.path.exists(assert_path):
+ test_info.failure('Assert file not created')
+
+ test_info.info('Checking that assert file persists if->bl')
+ board.set_mode(board.MODE_BL)
+ assert_path = board.get_file_path(ASSERT_FILE_NAME)
+ if not os.path.exists(assert_path):
+ test_info.failure('Assert file not created')
+
+ test_info.info('Checking that assert file persists bl->if')
+ board.set_mode(board.MODE_IF)
+ assert_path = board.get_file_path(ASSERT_FILE_NAME)
+ if not os.path.exists(assert_path):
+ test_info.failure('Assert file not created')
+
+ board.clear_assert()
+
+ board.set_mode(board.MODE_IF)
+ assert_path = board.get_file_path(ASSERT_FILE_NAME)
+ if os.path.exists(assert_path):
+ test_info.failure('Assert file not cleared correctly')
+
+ board.set_mode(board.MODE_BL)
+ assert_path = board.get_file_path(ASSERT_FILE_NAME)
+ if os.path.exists(assert_path):
+ test_info.failure('Assert file not cleared correctly')
+
+ board.set_mode(board.MODE_IF)
+ assert_path = board.get_file_path(ASSERT_FILE_NAME)
+ if os.path.exists(assert_path):
+ test_info.failure('Assert file not cleared correctly')
+
+ board.set_assert_auto_manage(True)
+
+
+def test_file_type(file_type, board_mode, board, parent_test,
+ data_start, raw_data):
+ """Test updates of a given file type using the given mode"""
+ assert file_type in ('hex', 'bin'), 'Unsupported file type %s' % file_type
+
+ if board_mode == board.MODE_IF:
+ data_type = board.MODE_BL
+ elif board_mode == board.MODE_BL:
+ data_type = board.MODE_IF
+ else:
+ assert False
+
+ test_info = parent_test.create_subtest('%s %s filetype test' %
+ (file_type, data_type))
+
+ def get_file_name(base='image'):
+ """Get the file name to be used for loading"""
+ return base + '.' + file_type
+
+ def get_file_content(addr, bin_data):
+ """Get the file contents to be used for loading"""
+ if file_type == 'bin':
+ return bytearray(bin_data) # Make a copy
+ elif file_type == 'hex':
+ return bin_data_to_hex_data(addr, bin_data)
+
+ # Test partial update
+ file_name = get_file_name()
+ local_data = get_file_content(data_start, raw_data[0:len(raw_data) // 2])
+ test = DLMassStorageTester(board, test_info, "Load partial",
+ board_mode)
+ test.set_programming_data(local_data, file_name)
+ test.set_expected_data(None)
+ test.set_expected_failure_msg("In application programming failed because "
+ "the update sent was incomplete.", "interface")
+ test.set_expected_mode(board_mode)
+ test.run()
+ # If bootloader is missing then this should be indicated by a file
+ if board_mode == board.MODE_IF:
+ if not os.path.isfile(board.get_file_path(NEED_BL_FILE_NAME)):
+ test_info.failure("Bootloader missing but file %s not present" %
+ NEED_BL_FILE_NAME)
+ test_info.info("Testing switch to bootloader")
+ try:
+ board.set_mode(board.MODE_BL)
+ test_info.failure("Board switched to bootloader mode")
+ except Exception:
+ pass
+ finally:
+ if board.get_mode() == board.MODE_IF:
+ test_info.info("Device able to recover from bad BL")
+ else:
+ test_info.failure("Device in wrong mode")
+
+ # Test loading a normal image
+ file_name = get_file_name()
+ local_data = get_file_content(data_start, raw_data)
+ test = DLMassStorageTester(board, test_info, "Normal Load",
+ board_mode)
+ test.set_programming_data(local_data, file_name)
+ test.set_expected_data(raw_data)
+ test.set_expected_mode(board.MODE_IF)
+ test.run()
+
+ # Wrong starting address
+ if file_type != 'bin':
+ mode_to_error = {
+ board.MODE_IF: ('The starting address for the bootloader '
+ 'update is wrong.'),
+ board.MODE_BL: ('The starting address for the interface '
+ 'update is wrong.')
+ }
+ file_name = get_file_name()
+ local_data = get_file_content(data_start + 0x400, raw_data)
+ test = DLMassStorageTester(board, test_info, "Wrong Address",
+ board_mode)
+ test.set_expected_failure_msg(mode_to_error[board_mode], 'user')
+ test.set_programming_data(local_data, file_name)
+ test.set_expected_data(raw_data)
+ test.set_expected_mode(board_mode)
+ test.run()
+
+ # Test flushes during update
+ file_name = get_file_name()
+ local_data = get_file_content(data_start, raw_data)
+ test = DLMassStorageTester(board, test_info, "Load with flushes",
+ board_mode)
+ test.set_programming_data(local_data, file_name)
+ test.set_expected_data(raw_data)
+ test.set_flush_size(0x1000)
+ test.set_expected_mode(board.MODE_IF)
+ test.run()
+
+ # Test bad crc
+ file_name = get_file_name()
+ local_raw_data = bytearray(raw_data)
+ local_raw_data[-1] = (local_raw_data[-1] + 1) % 0x100 # Corrupt CRC
+ local_data = get_file_content(data_start, local_raw_data)
+ test = DLMassStorageTester(board, test_info, 'Wrong CRC',
+ board_mode)
+ test.set_programming_data(local_data, file_name)
+ if board_mode == board.MODE_IF:
+ test.set_expected_failure_msg('The bootloader CRC did not pass.', 'interface')
+ test.set_expected_data(None)
+ elif board_mode == board.MODE_BL:
+ # Interface images can be from other vendors and be missing
+ # the crc, so don't treat this as an error
+ test.set_expected_data(local_raw_data)
+ test.set_expected_mode(board.MODE_IF)
+ test.run()
+ # If bootloader is missing then this should be indicated by a file
+ if (board_mode == board.MODE_IF and
+ not os.path.isfile(board.get_file_path(NEED_BL_FILE_NAME))):
+ test_info.failure("Bootloader missing but file %s not present" %
+ NEED_BL_FILE_NAME)
+
+ # Test load with extra padding
+ file_name = get_file_name()
+ local_data = get_file_content(data_start, raw_data)
+ local_data.extend(b'\xFF' * 0x1000)
+ test = DLMassStorageTester(board, test_info, "Padded load", board_mode)
+ test.set_programming_data(local_data, file_name)
+ test.set_expected_data(raw_data)
+ test.set_expected_mode(board.MODE_IF)
+ test.run()
+
+ # Test bad crc in file data
+ # Note - crc is only a requirment for loading bootloades
+ if board_mode == board.MODE_IF:
+ file_name = get_file_name()
+ local_raw_data = bytearray(raw_data)
+ local_raw_data[0x100] = (local_raw_data[0x100] + 1) % 0x100 # Corrupt CRC
+ local_data = get_file_content(data_start, local_raw_data)
+ test = DLMassStorageTester(board, test_info, 'Wrong data CRC',
+ board_mode)
+ test.set_programming_data(local_data, file_name)
+ test.set_expected_failure_msg('The bootloader CRC did not pass.', 'interface')
+ test.set_expected_data(None)
+ test.set_expected_mode(board.MODE_IF)
+ test.run()
+ # If bootloader is missing then this should be indicated by a file
+ if not os.path.isfile(board.get_file_path(NEED_BL_FILE_NAME)):
+ test_info.failure("Bootloader missing but file %s not present" %
+ NEED_BL_FILE_NAME)
+
+ # Restore a good image
+ file_name = get_file_name()
+ local_data = get_file_content(data_start, raw_data)
+ test = DLMassStorageTester(board, test_info, "Normal Load",
+ board_mode)
+ test.set_programming_data(local_data, file_name)
+ test.set_expected_data(raw_data)
+ test.set_expected_mode(board.MODE_IF)
+ test.run()
+
+ # Test wrong HIC ID
+ # Bootloader should perform interface update regardless of key
+ if data_type == board.MODE_IF:
+ local_raw_data = bytearray(raw_data)
+ local_raw_data[DAPLINK_HIC_ID_OFFSET] = \
+ (local_raw_data[DAPLINK_HIC_ID_OFFSET] + 1) % 0x100
+ file_name = get_file_name()
+ local_data = get_file_content(data_start, local_raw_data)
+ test = DLMassStorageTester(board, test_info, "Wrong HIC ID",
+ board_mode)
+ test.set_programming_data(local_data, file_name)
+ test.set_expected_data(local_raw_data)
+ test.set_expected_mode(board.MODE_IF)
+ test.run()
+
+ # TODO future - Wrong type
+
+ # Test a normal load with dummy files created beforehand
+ file_name = get_file_name()
+ local_data = get_file_content(data_start, raw_data)
+ test = DLMassStorageTester(board, test_info, "Extra Files", board_mode)
+ test.set_programming_data(local_data, file_name)
+ test.add_mock_dirs(MOCK_DIR_LIST)
+ test.add_mock_files(MOCK_FILE_LIST)
+ test.add_mock_dirs_after_load(MOCK_DIR_LIST_AFTER)
+ test.add_mock_files_after_load(MOCK_FILE_LIST_AFTER)
+ test.set_expected_data(raw_data)
+ test.set_expected_mode(board.MODE_IF)
+ test.run()
+
+ # Restore good image
+ file_name = get_file_name()
+ local_data = get_file_content(data_start, raw_data)
+ test = DLMassStorageTester(board, test_info, "Restore image",
+ board_mode)
+ test.set_programming_data(local_data, file_name)
+ test.set_expected_data(raw_data)
+ test.set_expected_mode(board.MODE_IF)
+ test.run()
+
diff -r 000000000000 -r 01f31e923fe2 test/test_info.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/test/test_info.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,189 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+from __future__ import absolute_import
+from __future__ import print_function
+import six
+import sys
+import time
+
+
+class TestInfo(object):
+ # Higher number = more severe
+ SUBTEST = 0
+ INFO = 1
+ WARNING = 2
+ FAILURE = 3
+
+ _MSG_TYPES = set((INFO, WARNING, FAILURE))
+ _MSG_LEVEL_TO_FMT_STR = {
+ INFO: "Info: %s",
+ WARNING: "Warning: %s",
+ FAILURE: "Failure: %s",
+ }
+
+ def __init__(self, name, init_print=True):
+ self._all = []
+ self.failures = 0
+ self.warnings = 0
+ self.infos = 0
+ self.name = name
+ if init_print:
+ self._print_msg("SubTest: " + name)
+
+ def failure(self, msg):
+ assert isinstance(msg, six.string_types)
+ self._add_entry(self.FAILURE, msg)
+
+ def warning(self, msg):
+ assert isinstance(msg, six.string_types)
+ self._add_entry(self.WARNING, msg)
+
+ def info(self, msg):
+ assert isinstance(msg, six.string_types)
+ self._add_entry(self.INFO, msg)
+
+ def print_msg(self, warning_level, max_recursion=0, spacing=2,
+ log_file=sys.stdout, _recursion_level=0):
+ """
+ Print problems at the given level
+
+ By default only the top level passes and fails are printed.
+ Set max_recursion to the number of subtests to be printed, or
+ to None if all levels should be printed.
+ """
+ assert warning_level in self._MSG_TYPES
+ assert max_recursion is None or max_recursion >= 0
+
+ if self.get_failed():
+ result_str = 'Failure'
+ test_level = self.FAILURE
+ elif self.get_warning():
+ result_str = 'Warning'
+ test_level = self.WARNING
+ else:
+ result_str = 'Pass'
+ test_level = self.INFO
+ prefix = ' ' * (_recursion_level * spacing)
+
+ # Check if test should be printed - the waning level
+ # is enabled, or this is the top level test
+ if test_level < warning_level and _recursion_level != 0:
+ return
+
+ # Print test header
+ print(prefix + "Test: %s: %s" % (self.name, result_str),
+ file=log_file)
+
+ # Check for recursion termination
+ if max_recursion is not None and _recursion_level > max_recursion:
+ return
+ _recursion_level += 1
+
+ # Print messages
+ prefix = ' ' * (_recursion_level * spacing)
+ for msg_level, msg in self._all:
+ if msg_level == self.SUBTEST:
+ test_info = msg
+ test_info.print_msg(warning_level, max_recursion,
+ spacing, log_file, _recursion_level)
+ else:
+ fmt = prefix + self._MSG_LEVEL_TO_FMT_STR[msg_level]
+ if msg_level >= warning_level:
+ print(fmt % msg, file=log_file)
+
+ def get_failed(self):
+ self._update_counts()
+ return self.failures != 0
+
+ def get_warning(self):
+ self._update_counts()
+ return self.warnings != 0
+
+ def get_name(self):
+ return self.name
+
+ def create_subtest(self, name):
+ assert isinstance(name, six.string_types)
+ test_info = TestInfo(name)
+ self._add_entry(self.SUBTEST, test_info)
+ return test_info
+
+ def attach_subtest(self, subtest):
+ assert isinstance(subtest, TestInfo)
+ self._add_entry(self.SUBTEST, subtest)
+
+ def get_counts(self):
+ """
+ Return the number of events that occured
+
+ Return the number of even messages as a
+ tuple containing (failure_count, warning_count, info_count).
+ """
+ self._update_counts()
+ return self.failures, self.warnings, self.infos
+
+ def _update_counts(self):
+ self.failures, self.warnings, self.infos = 0, 0, 0
+ for msg_level, msg in self._all:
+ if msg_level == self.SUBTEST:
+ test_info = msg
+ failures, warnings, infos = test_info.get_counts()
+ self.failures += failures
+ self.warnings += warnings
+ self.infos += infos
+ else:
+ if msg_level == self.FAILURE:
+ self.failures += 1
+ elif msg_level == self.WARNING:
+ self.warnings += 1
+ elif msg_level == self.INFO:
+ self.infos += 1
+ else:
+ # Should never get here
+ assert False
+
+ def _add_entry(self, entry_type, msg):
+ if entry_type is self.SUBTEST:
+ assert isinstance(msg, TestInfo)
+ # Test name printed in constructor
+ else:
+ assert isinstance(msg, six.string_types)
+ self._print_msg(msg)
+ self._all.append((entry_type, msg))
+
+ @staticmethod
+ def _print_msg(msg):
+ print(get_timestamp_tag() + msg)
+
+
+class TestInfoStub(TestInfo):
+
+ def __init__(self):
+ super(TestInfoStub, self).__init__('stub test', False)
+
+ def create_subtest(self, name):
+ assert isinstance(name, six.string_types)
+ return TestInfoStub()
+
+ @staticmethod
+ def _print_msg(msg):
+ print(get_timestamp_tag() + "%s"%(msg,))
+
+def get_timestamp_tag():
+ return "[{:0<17f}] ".format(time.time())
diff -r 000000000000 -r 01f31e923fe2 test/usb_cdc.py --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/test/usb_cdc.py Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,182 @@ +# +# DAPLink Interface Firmware +# Copyright (c) 2016-2016, ARM Limited, All Rights Reserved +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +import usb.util + + +class USBCdc(object): + """Wrapper class for a CDC usb device""" + + # Communication commands documented in + # PSTN120 inside CDC1.2_WMC1.1_012011 + + CLASS_CDC_DATA = 0xa + CLASS_CDC_COMM = 0x2 + + FORMAT_STOP_BITS_1_0 = 0 + FORMAT_STOP_BITS_1_5 = 1 + FORMAT_STOP_BITS_2_0 = 2 + + PARITY_NONE = 0 + PARITY_ODD = 1 + PARITY_EVEN = 2 + PARITY_MARK = 3 + PARITY_SPACE = 4 + + DATA_BITS_5 = 5 + DATA_BITS_6 = 6 + DATA_BITS_7 = 7 + DATA_BITS_8 = 8 + DATA_BITS_16 = 16 + + SEND_BREAK_ON = 0xFFFF + SEND_BREAK_OFF = 0x0000 + + def __init__(self, device): + self._dev = device + self._if_data = None + self._if_comm = None + self.ep_data_out = None + self.ep_data_in = None + self._locked = False + self.timeout = 10000 + + # Find interfaces + for interface in device.get_active_configuration(): + if interface.bInterfaceClass == USBCdc.CLASS_CDC_DATA: + assert self._if_data is None + self._if_data = interface + if interface.bInterfaceClass == USBCdc.CLASS_CDC_COMM: + assert self._if_comm is None + self._if_comm = interface + assert self._if_data is not None + assert self._if_comm is not None + + # Find endpoints + for endpoint in self._if_data: + if endpoint.bEndpointAddress & 0x80: + assert self.ep_data_in is None + self.ep_data_in = endpoint + else: + assert self.ep_data_out is None + self.ep_data_out = endpoint + assert self.ep_data_in is not None + assert self.ep_data_out is not None + + def lock(self): + """Acquire exclisive access to CDC""" + assert not self._locked + + for interface in (self._if_data, self._if_comm): + num = interface.bInterfaceNumber + try: + if self._dev.is_kernel_driver_active(num): + self._dev.detach_kernel_driver(num) + except NotImplementedError: + pass + except usb.core.USBError: + pass + usb.util.claim_interface(self._dev, num) + self._locked = True + + def unlock(self): + """Release exclusive access to CDC""" + assert self._locked + + for interface in (self._if_data, self._if_comm): + num = interface.bInterfaceNumber + usb.util.release_interface(self._dev, num) + try: + self._dev.attach_kernel_driver(num) + except NotImplementedError: + pass + except usb.core.USBError: + pass + self._locked = False + + def set_line_coding(self, baud, fmt=FORMAT_STOP_BITS_1_0, + parity=PARITY_NONE, databits=DATA_BITS_8): + """Send the SetLineCoding CDC command""" + assert self._locked + + data = bytearray(7) + data[0] = (baud >> (8 * 0)) & 0xFF + data[1] = (baud >> (8 * 1)) & 0xFF + data[2] = (baud >> (8 * 2)) & 0xFF + data[3] = (baud >> (8 * 3)) & 0xFF + data[4] = fmt + data[5] = parity + data[6] = databits + + request_type = 0x21 + request = 0x20 # SET_LINE_CODING + value = 0 # Always 0 for this request + index = self._if_comm.bInterfaceNumber # Communication interface + self._dev.ctrl_transfer(request_type, request, value, index, data, + self.timeout) + + def get_line_coding(self): + """Send the GetLineCoding CDC command + + Returns a tuple containing + baud, fmt, parity, databits + """ + assert self._locked + + request_type = 0xA1 + request = 0x21 # GET_LINE_CODING + value = 0 # Always 0 for this request + index = self._if_comm.bInterfaceNumber # Communication interface + resp = self._dev.ctrl_transfer(request_type, request, value, index, 7, + self.timeout) + baud = (((resp[0] & 0xFF) << (8 * 0)) | + ((resp[1] & 0xFF) << (8 * 1)) | + ((resp[2] & 0xFF) << (8 * 2)) | + ((resp[3] & 0xFF) << (8 * 3))) + fmt = resp[4] + parity = resp[5] + databits = resp[6] + return (baud, fmt, parity, databits) + + def send_break(self, break_time): + """Send the SendBreak CDC command""" + assert self._locked + assert break_time & ~0xFFFF == 0, "Value outside of supported range" + + request_type = 0x21 + request = 0x23 # SEND_BREAK + value = break_time # Duration of break in ms + index = self._if_comm.bInterfaceNumber # Communication interface + self._dev.ctrl_transfer(request_type, request, value, index, None, + self.timeout) + + def read(self, size, timeout=None): + """Read from the CDC data endpoint""" + assert self._locked + + if timeout is None: + timeout = self.timeout + return self.ep_data_in.read(size, timeout) + + def write(self, data, timeout=None): + """Write to the CDC data endpoint""" + assert self._locked + + if timeout is None: + timeout = self.timeout + self.ep_data_out.write(data, self.timeout)
diff -r 000000000000 -r 01f31e923fe2 test/usb_hid.py --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/test/usb_hid.py Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,162 @@ +# +# DAPLink Interface Firmware +# Copyright (c) 2016-2016, ARM Limited, All Rights Reserved +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +import usb.util + + +class USBHid(object): + """Wrapper class for a HID usb device""" + + # HID commands documented in + # Device Class Definition for Human Interface Devices (HID) + + CLASS_HID = 0x3 + + DESC_TYPE_HID = 0x21 + DESC_TYPE_REPORT = 0x22 + DESC_TYPE_PHYSICAL = 0x23 + + REPORT_TYPE_INPUT = 1 + REPORT_TYPE_OUTPUT = 2 + REPORT_TYPE_FEATURE = 3 + + def __init__(self, device): + self._dev = device + self._if = None + self.ep_in = None + self.ep_out = None + self._locked = False + self.timeout = 10 * 1000 + + # Find interface + for interface in device.get_active_configuration(): + if interface.bInterfaceClass == USBHid.CLASS_HID: + assert self._if is None + self._if = interface + assert self._if is not None + + # Find endpoints + for endpoint in self._if: + if endpoint.bEndpointAddress & 0x80: + assert self.ep_in is None + self.ep_in = endpoint + else: + assert self.ep_out is None + self.ep_out = endpoint + assert self.ep_in is not None + # Endpoint out can be None + + def lock(self): + """Acquire exclisive access to HID""" + assert not self._locked + + num = self._if.bInterfaceNumber + try: + if self._dev.is_kernel_driver_active(num): + self._dev.detach_kernel_driver(num) + except NotImplementedError: + pass + except usb.core.USBError: + pass + usb.util.claim_interface(self._dev, num) + self._locked = True + + def unlock(self): + """Release exclusive access to HID""" + assert self._locked + + num = self._if.bInterfaceNumber + usb.util.release_interface(self._dev, num) + try: + self._dev.attach_kernel_driver(num) + except NotImplementedError: + pass + except usb.core.USBError: + pass + self._locked = False + + def set_idle(self, report_id=0, duration=0): + """Send a HID Set_Idle request""" + assert self._locked + assert report_id & ~0xFF == 0 + assert duration & ~0xFF == 0 + + request_type = 0x21 + request = 0x0A # SET_IDLE + value = ((duration << 8) | (report_id << 0)) # Report and duration + index = self._if.bInterfaceNumber # HID interface + self._dev.ctrl_transfer(request_type, request, value, index, None) + + def get_descriptor(self, desc_type, index): + """Get the given descriptor""" + assert self._locked + assert desc_type & ~0xFF == 0 + assert index & ~0xFF == 0 + + request_type = 0x81 + request = 0x6 # GET_DESCRIPTOR + value = (((index & 0xFF) << (0 * 8)) | + ((desc_type & 0xFF) << (1 * 8))) # Descriptor type and index + index = self._if.bInterfaceNumber # HID interface + return self._dev.ctrl_transfer(request_type, request, + value, index, 256) + + def set_report_req(self, data, report_type=REPORT_TYPE_OUTPUT, + report_id=0): + """Set a report of the given type""" + assert self._locked + assert report_type & ~0xFF == 0 + assert report_id & ~0xFF == 0 + + request_type = 0x21 + request = 0x09 # SET_REPORT + value = ((report_type << 8) | + (report_id << 0)) # Report and duration + index = self._if.bInterfaceNumber # HID interface + self._dev.ctrl_transfer(request_type, request, value, index, data, + self.timeout) + + def get_report_req(self, data_size, report_type=REPORT_TYPE_INPUT, + report_id=0): + """Set a report of the given type""" + assert self._locked + assert report_type & ~0xFF == 0 + assert report_id & ~0xFF == 0 + + request_type = 0xA1 + request = 0x01 # SET_REPORT + value = ((report_type << 8) | + (report_id << 0)) # Report and duration + index = self._if.bInterfaceNumber # HID interface + return self._dev.ctrl_transfer(request_type, request, value, index, + data_size, self.timeout) + + def set_report(self, data): + """Send report to the device""" + assert self._locked + + if self.ep_out is None: + self.set_report_req(data) + else: + self.ep_out.write(data, 10 * 1000) + + def get_report(self, size): + """Read report from the device""" + assert self._locked + + return self.ep_in.read(size, 10 * 1000)
diff -r 000000000000 -r 01f31e923fe2 test/usb_msd.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/test/usb_msd.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,387 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2016-2016, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+import os
+import struct
+import numbers
+import time
+import usb.util
+
+
+class USBMsd(object):
+ """Wrapper class for a MSD usb device"""
+
+ # Bulk only transport documented in
+ # "Universal Serial Bus Mass Storage Class"
+ # SCSI commands documented in "SCSI Commands Reference Manual" by Seagate
+
+ CLASS_MSD = 0x8
+ # Write 10
+ # Read 10
+ # Test unit ready
+ # Request Sense
+
+ # dCBWSignature
+ # dCBWTag
+ # dCBWDataTransferLength
+ # bmCBWFlags
+ # bCBWLUN
+ # bCBWCBLength
+ FMT_CBW = "<IIIBBB"
+
+ # dCSWSignature
+ # dCSWTag
+ # dCSWDataResidue
+ # bCSWStatus
+ FMT_CSW = "<IIIB"
+
+ CSW_STATUS_PASSED = 0
+ CSW_STATUS_FAILED = 1
+ CSW_STATUS_PHASE_ERROR = 2
+
+ class SCSIError(Exception):
+
+ def __init__(self, error):
+ Exception.__init__(self)
+ self.value = error
+
+ # Some SCSI commands
+ # Value Keil middleware define Seagate name
+ # 0x12 SCSI_INQUIRY INQUIRY
+ # 0x23 SCSI_READ_FORMAT_CAPACITIES Missing
+ # 0x25 SCSI_READ_CAPACITY READ CAPACITY (10)
+ # 0x28 SCSI_READ10 READ (10)
+ # 0x1A SCSI_MODE_SENSE6 MODE SENSE (6)
+ # 0x00 SCSI_TEST_UNIT_READY TEST UNIT READY
+ # 0x2A SCSI_WRITE10 WRITE (10)
+ # 0x03 SCSI_REQUEST_SENSE REQUEST SENSE
+ # 0x1E SCSI_MEDIA_REMOVAL Missing
+
+ def __init__(self, device):
+ self._dev = device
+ self._if = None
+ self.ep_in = None
+ self.ep_out = None
+ self._locked = False
+ self._cbw_tag = 0
+ self.timeout = 60 * 1000
+ # delays are for testing only
+ self.delay_cbw_to_data = 0
+ self.delay_data_to_csw = 0
+
+ # Find interface
+ for interface in device.get_active_configuration():
+ if interface.bInterfaceClass == USBMsd.CLASS_MSD:
+ assert self._if is None
+ self._if = interface
+ assert self._if is not None
+
+ # Find endpoints
+ for endpoint in self._if:
+ if endpoint.bEndpointAddress & 0x80:
+ assert self.ep_in is None
+ self.ep_in = endpoint
+ else:
+ assert self.ep_out is None
+ self.ep_out = endpoint
+ assert self.ep_in is not None
+ assert self.ep_out is not None
+
+ def lock(self):
+ """Acquire exclisive access to MSD"""
+ assert not self._locked
+
+ num = self._if.bInterfaceNumber
+ try:
+ if self._dev.is_kernel_driver_active(num):
+ self._dev.detach_kernel_driver(num)
+ except NotImplementedError:
+ pass
+ except usb.core.USBError:
+ pass
+ usb.util.claim_interface(self._dev, num)
+ self._locked = True
+
+ def unlock(self):
+ """Release exclusive access to MSD"""
+ assert self._locked
+
+ num = self._if.bInterfaceNumber
+ usb.util.release_interface(self._dev, num)
+ try:
+ self._dev.attach_kernel_driver(num)
+ except NotImplementedError:
+ pass
+ except usb.core.USBError:
+ pass
+ self._locked = False
+
+ def scsi_read10(self, lba, block_count):
+ """Send the SCSI read 10 command and return the data read"""
+ block_size = 512
+
+ cbwcb = bytearray(10)
+ cbwcb[0] = 0x28
+ cbwcb[2] = (lba >> (8 * 3)) & 0xFF
+ cbwcb[3] = (lba >> (8 * 2)) & 0xFF
+ cbwcb[4] = (lba >> (8 * 1)) & 0xFF
+ cbwcb[5] = (lba >> (8 * 0)) & 0xFF
+ cbwcb[7] = (block_count >> (8 * 1)) & 0xFF
+ cbwcb[8] = (block_count >> (8 * 0)) & 0xFF
+ ret, data = self._msd_transfer(cbwcb, 0, block_count * block_size)
+ if ret != self.CSW_STATUS_PASSED:
+ raise self.SCSIError(ret)
+ return data
+
+ def scsi_write10(self, lba, data):
+ """Send the SCSI write 10 command"""
+ block_size = 512
+
+ assert len(data) % block_size == 0
+ block_count = (len(data) + (block_size - 1)) // block_size
+
+ cbwcb = bytearray(10)
+ cbwcb[0] = 0x2A
+ cbwcb[2] = (lba >> (8 * 3)) & 0xFF
+ cbwcb[3] = (lba >> (8 * 2)) & 0xFF
+ cbwcb[4] = (lba >> (8 * 1)) & 0xFF
+ cbwcb[5] = (lba >> (8 * 0)) & 0xFF
+ cbwcb[7] = (block_count >> (8 * 1)) & 0xFF
+ cbwcb[8] = (block_count >> (8 * 0)) & 0xFF
+ ret, _ = self._msd_transfer(cbwcb, 0, data)
+ if ret != self.CSW_STATUS_PASSED:
+ raise self.SCSIError(ret)
+
+ def scsi_test_unit_ready(self):
+ """Send the SCSI test unit ready command and return status"""
+ cbwcb = bytearray(10)
+ cbwcb[0] = 0
+ ret, _ = self._msd_transfer(cbwcb, 0)
+ return ret
+
+ def _msd_transfer(self, cbwcb, lun, size_or_data=None):
+ """Perform a bulk only transfer"""
+ assert self._locked
+ assert 1 <= len(cbwcb) <= 16
+
+ # Increment packet tag
+ transfer_tag = self._cbw_tag
+ self._cbw_tag = (self._cbw_tag + 1) & 0xFFFFFFFF
+
+ # None means data size of zero
+ if size_or_data is None:
+ size_or_data = 0
+
+ in_transfer = isinstance(size_or_data, numbers.Number)
+ transfer_size = (size_or_data if in_transfer else len(size_or_data))
+ assert in_transfer or len(size_or_data) > 0
+
+ # Phase - Command transport
+ cbw_signature = 0x43425355
+ cbw_tag = transfer_tag
+ cbw_data_transfer_length = transfer_size
+ cbw_flags = (1 << 7) if in_transfer else 0
+ cbw_lun = lun
+ cbw_length = len(cbwcb)
+ params = [cbw_signature, cbw_tag, cbw_data_transfer_length,
+ cbw_flags, cbw_lun, cbw_length]
+ cbw = struct.pack(self.FMT_CBW, *params)
+ pad_size = 16 - len(cbwcb)
+ payload = cbw + cbwcb + bytearray(pad_size)
+ self.ep_out.write(payload)
+
+ if self.delay_cbw_to_data != 0:
+ time.sleep(self.delay_cbw_to_data)
+
+ # Phase - Data Out or Data In (Optional)
+ data = None
+ if transfer_size > 0:
+ endpoint = self.ep_in if in_transfer else self.ep_out
+ try:
+ if in_transfer:
+ data = self.ep_in.read(transfer_size, self.timeout)
+ else:
+ self.ep_out.write(size_or_data, self.timeout)
+ except usb.core.USBError:
+ endpoint.clear_halt()
+
+ if self.delay_data_to_csw != 0:
+ time.sleep(self.delay_data_to_csw)
+
+ # Phase - Status Transport
+ csw = self.ep_in.read(13, self.timeout)
+ csw_signature, csw_tag, csw_data_residue, csw_status = \
+ struct.unpack(self.FMT_CSW, csw)
+ assert csw_signature == 0x53425355
+ assert csw_tag == transfer_tag
+ #TODO - check residue
+ return (csw_status, data)
+
+
+class Struct(object):
+ """Base class for a C structure"""
+
+ def __init__(self, name, structure, data):
+ field_list = [field[0] for field in structure]
+ fmt_list = [field[1] for field in structure]
+ format_str = "<" + "".join(fmt_list)
+ struct_size = struct.calcsize(format_str)
+ value_list = struct.unpack(format_str, data[:struct_size])
+ value_dict = {}
+ for name, value in zip(field_list, value_list):
+ value_dict[name] = value
+ self.name = name
+ self.format_str = format_str
+ self.field_list = field_list
+ self.value_dict = value_dict
+ self.size = struct_size
+
+ def __getitem__(self, key):
+ return self.value_dict[key]
+
+ def __setitem__(self, key, value):
+ self.value_dict[key] = value
+
+ def __str__(self):
+ desc = ""
+ desc += self.name + ":" + os.linesep
+ for field in self.field_list:
+ value = self.value_dict[field]
+ if isinstance(value, bytes):
+ value = list(bytearray(value))
+ desc += (" %s=%s" + os.linesep) % (field, value)
+ return desc
+
+ def pack(self):
+ """Return a byte representation of this structure"""
+ value_list = []
+ for field in self.field_list:
+ value_list.append(self.value_dict[field])
+ return struct.pack(self.format_str, *value_list)
+
+
+class MBR(Struct):
+ """Wrapper class for a FAT MBR"""
+
+ STRUCTURE = (
+ ("BS_jmpBoot", "3s"),
+ ("BS_OEMName", "8s"),
+ ("BPB_BytsPerSec", "H"),
+ ("BPB_SecPerClus", "B"),
+ ("BPB_RsvdSecCnt", "H"),
+ ("BPB_NumFATs", "B"),
+ ("BPB_RootEntCnt", "H"),
+ ("BPB_TotSec16", "H"),
+ ("BPB_Media", "B"),
+ ("BPB_FATSz16", "H"),
+ ("BPB_SecPerTrk", "H"),
+ ("BPB_NumHeads", "H"),
+ ("BPB_HiddSec", "L"),
+ ("BPB_TotSec32", "L"),
+ )
+
+ def __init__(self, data, sector=None):
+ Struct.__init__(self, "MBR", self.STRUCTURE, data)
+ self.sector = sector
+
+
+class DirectoryEntry(Struct):
+ """Wrapper class for a FAT DirectoryEntry"""
+
+ STRUCTURE = (
+ ("DIR_Name", "11s"),
+ ("DIR_Attr", "B"),
+ ("DIR_NTRes", "B"),
+ ("DIR_CrtTimeTenth", "B"),
+ ("DIR_CrtTime", "H"),
+ ("DIR_CrtDate", "H"),
+ ("DIR_LstAccDate", "H"),
+ ("DIR_FstClusHI", "H"),
+ ("DIR_WrtTime", "H"),
+ ("DIR_WrtDate", "H"),
+ ("DIR_FstClusLO", "H"),
+ ("DIR_FileSize", "L"),
+ )
+
+ def __init__(self, data):
+ Struct.__init__(self, "DirectoryEntry", self.STRUCTURE, data)
+
+
+class Directory(object):
+ """Wrapper class for a FAT Directory"""
+
+ ENTRY_SIZE = 32
+
+ def __init__(self, entry_count, data, sector=None):
+ directory_list = []
+ for i in range(entry_count):
+ start = i * self.ENTRY_SIZE
+ dir_data = data[start:start + self.ENTRY_SIZE]
+ entry = DirectoryEntry(dir_data)
+ directory_list.append(entry)
+ self.directory_list = directory_list
+ self.sector = sector
+
+ def __iter__(self):
+ return iter(self.directory_list)
+
+ def __getitem__(self, key):
+ return self.directory_list[key]
+
+ def find_free_entry_index(self):
+ """Find a free index in this Directory or return None"""
+ for idx, directory in enumerate(self.directory_list):
+ name_data = bytearray(directory["DIR_Name"])
+ if name_data[0] in (0x00, 0xE5):
+ return idx
+ return None
+
+ def pack(self):
+ """Return a byte a Directory"""
+ data = bytearray()
+ for directory in self.directory_list:
+ data.extend(directory.pack())
+ return data
+
+
+class Fat(object):
+ """Wrapper class for a FAT filesystem on a SCSI device"""
+
+ SECTOR_SIZE = 512
+ CLUSTER_SIZE = 4 * 1024
+
+ def __init__(self, msd):
+ self.msd = msd
+ self.reload()
+
+ def reload(self):
+ """Reload all internal data of this Fat filesystem"""
+
+ # Read MBR
+ mbr_data = self.msd.scsi_read10(0, 1)
+ mbr = MBR(mbr_data, 0)
+
+ # Read in the root directory
+ root_dir_sec = (mbr["BPB_RsvdSecCnt"] +
+ (mbr["BPB_NumFATs"] * mbr["BPB_FATSz16"]))
+ sec_count = (mbr["BPB_RootEntCnt"] * 32 + 512 - 1) // 512
+ root_dir_data = self.msd.scsi_read10(root_dir_sec, sec_count)
+ root_dir = Directory(mbr["BPB_RootEntCnt"], root_dir_data,
+ root_dir_sec)
+ self.mbr = mbr
+ self.root_dir = root_dir
diff -r 000000000000 -r 01f31e923fe2 test/usb_test.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/test/usb_test.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,440 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2016-2016, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+""" Module for low level and targeted USB tests"""
+
+from __future__ import print_function
+
+import os
+import usb.core
+import functools
+import threading
+import time
+from usb_cdc import USBCdc
+from usb_hid import USBHid
+from usb_msd import USBMsd, Fat
+
+DISMOUNT_TIME_S = 10.00
+
+
+def test_usb(workspace, parent_test, force=False):
+ """Run raw USB tests
+
+ Requirements:
+ -daplink-validation must be loaded for the target.
+ """
+
+ # Only test on supported platforms
+ if not _platform_supports_usb_test() and not force:
+ parent_test.info("Skipping USB test on this platform")
+ return
+ test_info = parent_test.create_subtest("USB test")
+
+ # Find the device under test
+ serial_number = workspace.board.get_unique_id()
+ dev = _daplink_from_serial_number(serial_number)
+ if dev is None:
+ test_info.failure("Could not find board with serial number %s" %
+ serial_number)
+ return
+
+ # Create wrappers for and acquire exclusive access to interfaces
+ cdc = USBCdc(dev)
+ hid = USBHid(dev)
+ msd = USBMsd(dev)
+ cdc.lock()
+ hid.lock()
+ msd.lock()
+
+ try:
+
+ for usb_test_on in (False, True):
+
+ _set_usb_test_mode(hid, usb_test_on)
+
+ test_cdc(test_info, cdc)
+
+ test_hid(test_info, hid)
+
+ test_msd(test_info, msd)
+
+ test_msd_stall(test_info, msd)
+
+ test_control(test_info, dev, cdc, hid, msd)
+
+ test_all(test_info, cdc, hid, msd)
+
+ # TODO - future enhancements
+ # MSD remount + hid
+ # STALL IN and STALL OUT
+
+ finally:
+ try:
+ _set_usb_test_mode(hid, False)
+ except usb.core.USBError:
+ pass
+ cdc.unlock()
+ hid.unlock()
+ msd.unlock()
+
+
+def main():
+ """Run the usb test as a stand alone program"""
+
+ import test_info
+ import mock
+
+ def get_unique_id(unique_id):
+ """Mock function to return a unique id"""
+ return unique_id
+
+ dev_list = usb.core.find(find_all=True, custom_match=_daplink_match)
+ for dev in dev_list:
+ board_id = dev.serial_number
+ print("Testing board %s" % board_id)
+ print("----------------")
+ mock_ws = mock.Mock()
+ mock_ws.board = mock.Mock()
+ mock_ws.board.unique_id = dev.serial_number
+ mock_ws.board.get_unique_id = functools.partial(get_unique_id,
+ board_id)
+ test_usb(mock_ws, test_info.TestInfoStub(), True)
+
+
+def test_cdc(test_info, cdc):
+ """Smoke test of the CDC endpoint"""
+ cdc.set_line_coding(115200)
+ baud, fmt, parity, databits = cdc.get_line_coding()
+ test_info.info("Baud %i, fmt %i, parity %i, databits %i" %
+ (baud, fmt, parity, databits))
+ cdc.send_break(cdc.SEND_BREAK_ON)
+ cdc.send_break(cdc.SEND_BREAK_OFF)
+ data = cdc.read(1024)
+ test_info.info("Serial port data: %s" % bytearray(data))
+ cdc.write("Hello world")
+ data = cdc.read(1024)
+ test_info.info("Serial port data2: %s" % bytearray(data))
+
+
+def test_hid(test_info, hid):
+ """Smoke test of the HID endpoint"""
+ hid.set_idle()
+ report = hid.get_descriptor(hid.DESC_TYPE_REPORT, 0)
+ test_info.info("Report descriptor: %s" % report)
+ # Send CMSIS-DAP vendor command to get the serial number
+ data = bytearray(64)
+ data[0] = 0x80
+ hid.set_report(data)
+ resp = hid.get_report(64)
+ length = resp[1]
+ test_info.info("CMSIS-DAP response: %s" %
+ bytearray(resp[1:1 + length]).decode("utf-8"))
+
+
+def test_msd(test_info, msd):
+ """MSD endpoint tests"""
+
+ # Simple read
+ mbr = msd.scsi_read10(0, 1)
+ test_info.info("MBR[0:16]: %s" % mbr[0:16])
+
+ # Test FAT filesystem
+ fat = Fat(msd)
+ print(fat.mbr)
+
+ # Grab entries in the root directory
+ root_dir = fat.root_dir
+ for entry in root_dir:
+ if entry["DIR_Name"][0] != "\0":
+ print(entry)
+
+ # Trigger a remount
+ dir_idx = root_dir.find_free_entry_index()
+ root_dir[dir_idx]["DIR_Name"] = "REFRESH ACT"
+ root_dir_data = root_dir.pack()
+ msd.scsi_write10(root_dir.sector, root_dir_data)
+
+ test_info.info("Added file to root directory")
+ start = time.time()
+ while time.time() - start < DISMOUNT_TIME_S:
+ try:
+ msd.scsi_read10(0, 1)
+ except msd.SCSIError:
+ test_info.info("Dismount detected")
+ break
+ else:
+ test_info.failure("Device failed to dismount")
+
+ start = time.time()
+ while time.time() - start < DISMOUNT_TIME_S:
+ try:
+ msd.scsi_read10(0, 1)
+ test_info.info("Mount detected")
+ break
+ except msd.SCSIError:
+ pass
+ else:
+ test_info.failure("Device failed to mount")
+
+
+def test_msd_stall(test_info, msd):
+ """Test stalls coming at various times in the middle of MSD xfers"""
+ fat = Fat(msd)
+ root_dir = fat.root_dir
+ dir_idx = root_dir.find_free_entry_index()
+ root_dir[dir_idx]["DIR_Name"] = "REFRESH ACT"
+ root_dir_data = root_dir.pack()
+
+ # Test that a write fails if media is removed after the CBW
+ # stage but before the CSW stage
+ msd.scsi_write10(root_dir.sector, root_dir_data)
+ msd.delay_cbw_to_data = 1.0
+ retval = msd.CSW_STATUS_PASSED
+ try:
+ msd.scsi_write10(0, bytearray(512))
+ test_info.failure("Device failed to stall data stage")
+ except msd.SCSIError as error:
+ retval = error.value
+ msd.delay_cbw_to_data = 0
+ # Make sure device still works as expected
+ time.sleep(3)
+ msd.scsi_read10(0, 1)
+ msd.scsi_write10(0, bytearray(512))
+ if retval == msd.CSW_STATUS_FAILED:
+ test_info.info("Test CBW,Stall,Data OUT - Pass")
+ else:
+ test_info.failure("Device returned wrong status")
+
+ # Test that a write succeeds even if media is removed
+ # after the OUT stage but before the CSW stage
+ msd.scsi_write10(root_dir.sector, root_dir_data)
+ msd.delay_data_to_csw = 1.0
+ msd.scsi_write10(0, bytearray(512))
+ msd.delay_data_to_csw = 0
+ # Make sure device still works as expected
+ time.sleep(3)
+ msd.scsi_read10(0, 1)
+ msd.scsi_write10(0, bytearray(512))
+ test_info.info("Test DATA OUT,Stall,CSW - Pass")
+
+ # Test that a read succeeds even if media is removed
+ # after the IN stage but before the CSW stage
+ msd.scsi_write10(root_dir.sector, root_dir_data)
+ msd.delay_data_to_csw = 1.0
+ resp = msd.scsi_read10(0, 1)
+ assert len(resp) == 512
+ msd.delay_data_to_csw = 0
+ # Make sure device still works as expected
+ time.sleep(3)
+ msd.scsi_read10(0, 1)
+ msd.scsi_write10(0, bytearray(512))
+ test_info.info("Test DATA IN,Stall,CSW - Pass")
+
+ # Test that a test unit ready succeeds even if media is removed
+ # after the CBW stage but before the CSW stage
+ msd.scsi_write10(root_dir.sector, root_dir_data)
+ msd.delay_data_to_csw = 1.0
+ resp = msd.scsi_test_unit_ready()
+ msd.delay_data_to_csw = 0
+ # Make sure device still works as expected
+ time.sleep(3)
+ msd.scsi_read10(0, 1)
+ msd.scsi_write10(0, bytearray(512))
+ if resp == msd.CSW_STATUS_PASSED:
+ test_info.info("Test CBW,Stall,CSW - Pass")
+ else:
+ test_info.failure("Test CBW,Stall,CSW - Failed")
+
+ # Test that a test unit ready succeeds even if media is removed
+ # after the CBW stage but before the CSW stage
+ msd.scsi_write10(root_dir.sector, root_dir_data)
+ time.sleep(1.0)
+ resp = msd.scsi_test_unit_ready()
+ # Make sure device still works as expected
+ time.sleep(3)
+ msd.scsi_read10(0, 1)
+ msd.scsi_write10(0, bytearray(512))
+ if resp == msd.CSW_STATUS_FAILED:
+ test_info.info("Test CBW,Stall,CSW - Pass")
+ else:
+ test_info.failure("Test CBW,Stall,CSW - Failed")
+
+
+def test_control(test_info, dev, cdc, hid, msd):
+ """Test for the control endpoint"""
+
+ test_info.info("testing control transfer with size a multiple of 256")
+ request_type = 0x80
+ request = 0x06 # Get descriptor
+ value = 0x200 # Configuration descriptor
+ index = 0 # Always 0 for this request
+ resp = dev.ctrl_transfer(request_type, request, value, index, 256)
+ assert len(resp) > 0
+
+ test_info.info("testing control commands")
+ # Test various patterns of control transfers
+ #
+ # Some devices have had problems with back-to-back
+ # control transfers. Intentionally send these sequences
+ # to make sure they are properly handled.
+ for _ in range(100):
+ # Control transfer with a data in stage
+ cdc.get_line_coding()
+ for _ in range(100):
+ # Control transfer with a data out stage followed
+ # by a control transfer with a data in stage
+ cdc.set_line_coding(115200)
+ cdc.get_line_coding()
+ for _ in range(100):
+ # Control transfer with a data out stage
+ cdc.set_line_coding(115200)
+
+ test_info.info("testing endpoint clearing")
+
+ cdc.ep_data_out.clear_halt()
+ cdc.ep_data_out.write('') # DATA0
+ cdc.ep_data_out.clear_halt()
+ cdc.ep_data_out.write('') # DATA0
+
+ cdc.ep_data_out.clear_halt()
+ cdc.ep_data_out.write('') # DATA 0
+ cdc.ep_data_out.write('') # DATA 1
+ cdc.ep_data_out.clear_halt()
+ cdc.ep_data_out.write('') # DATA 0
+
+
+def test_all(test_info, cdc, hid, msd):
+ """Test all endpoints in parallel"""
+ mutex = threading.RLock()
+ terminate = False
+ error_msg_list = []
+
+ def _safe_print(message):
+ """Thread safe wrapper to print messages"""
+ with mutex:
+ print(message)
+
+ def _test_msd():
+ """MSD thread entry point for parallel testing"""
+ try:
+ _safe_print("msd started")
+ msd_data = msd.scsi_read10(100, 1)
+ while not terminate:
+ #msd_data = 'x' * 1024 * 16 # 16KB
+ msd.scsi_write10(100, msd_data)
+ _safe_print("msd end")
+ except:
+ error_msg_list.append("MSD test failed")
+ raise
+
+ def _test_cdc():
+ """CDC thread entry point for parallel testing"""
+ try:
+ _safe_print("cdc started")
+ while not terminate:
+ cdc.set_line_coding(115200)
+ cdc.get_line_coding()
+ cdc.send_break(cdc.SEND_BREAK_ON)
+ cdc.send_break(cdc.SEND_BREAK_OFF)
+ cdc.read(1024)
+ cdc.write("Hello world")
+ cdc.read(1024)
+ _safe_print("cdc end")
+ except:
+ error_msg_list.append("CDC test failed")
+ raise
+
+ def _test_hid():
+ """HID thread entry point for parallel testing"""
+ try:
+ _safe_print("hid started")
+ data = bytearray(64)
+ data[0] = 0x80
+ while not terminate:
+ hid.set_report(data)
+ resp = hid.get_report(64)
+ assert resp[0] == 0x80
+ _safe_print("hid end")
+ except:
+ error_msg_list.append("HID test failed")
+ raise
+
+ thread_list = []
+ for function in (_test_msd, _test_cdc, _test_hid):
+ thread = threading.Thread(target=function)
+ thread.start()
+ thread_list.append(thread)
+
+ time.sleep(10)
+
+ terminate = True
+ for thread in thread_list:
+ thread.join()
+
+ for error in error_msg_list:
+ test_info.failure(error)
+
+
+def _daplink_match(dev):
+ """DAPLink match function to be used with usb.core.find"""
+ try:
+ device_string = dev.product
+ except ValueError:
+ return False
+ if device_string is None:
+ return False
+ if device_string.find("CMSIS-DAP") < 0:
+ return False
+ return True
+
+
+def _daplink_from_serial_number(serial_number):
+ """Return a usb handle to the DAPLink device with the serial number"""
+ dev_list = usb.core.find(find_all=True, custom_match=_daplink_match)
+ for dev in dev_list:
+ if dev.serial_number == serial_number:
+ return dev
+ return None
+
+
+def _platform_supports_usb_test():
+ """Return True if this platform supports USB testing, False otherwise"""
+ if os.name != "posix":
+ return False
+ if not hasattr(os, 'uname'):
+ if False:
+ # Hack to supress warnings for uname not existing
+ os.uname = lambda: [None]
+ return False
+ if os.uname()[0] == "Darwin":
+ return False
+ return True
+
+
+def _set_usb_test_mode(hid, enabled):
+ """Set to True to enable USB testing mode"""
+ data = bytearray(64)
+ data[0] = 0x88
+ data[1] = 1 if enabled else 0
+ hid.set_report(data)
+ resp = hid.get_report(64)
+ if (resp[0] != 0x88) or (resp[1] != 1):
+ raise Exception("Error configuring USB test mode")
+
+
+if __name__ == "__main__":
+ main()
diff -r 000000000000 -r 01f31e923fe2 tools/build_release.bat --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/build_release.bat Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,103 @@ +:: +:: DAPLink Interface Firmware +:: Copyright (c) 2009-2016, ARM Limited, All Rights Reserved +:: SPDX-License-Identifier: Apache-2.0 +:: +:: Licensed under the Apache License, Version 2.0 (the "License"); you may +:: not use this file except in compliance with the License. +:: You may obtain a copy of the License at +:: +:: http://www.apache.org/licenses/LICENSE-2.0 +:: +:: Unless required by applicable law or agreed to in writing, software +:: distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +:: WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +:: See the License for the specific language governing permissions and +:: limitations under the License. +:: +setlocal enabledelayedexpansion +@rem Script assumes working directory is workspace root. Force it. +cd %~dp0..\ + +@rem See if we can find uVision. This logic is consistent with progen +@if [%UV4%]==[] ( + @echo UV4 variable is not set, trying to autodetect.. + if EXIST c:\keil\uv4\uv4.exe ( + set UV4=c:\keil\uv4\uv4.exe + ) else if EXIST c:\keil_v5\uv4\uv4.exe ( + set UV4=c:\keil_v5\uv4\uv4.exe + ) else goto error_nomdk +) +@echo USING UV4=%UV4% + +@set project_tool=%1 +@set env_folder=%2 +@set requirements_file=%3 + + +@rem Select an existing virtualenv as first parameter +@if not [%env_folder%]==[] ( + echo Using virtualenv %env_folder% + @if exist %env_folder% call %env_folder%\Scripts\activate && goto :env_folder_ok +) else ( + echo Checking env folder + @if exist env goto :env_ok +) + + +echo Creating python virtual environment && virtualenv env +:env_ok +call env\Scripts\activate +:env_folder_ok + +@echo Doing pip install +@REM use project requirements if not specified +if [%requirements_file%]==[] pip install -r requirements.txt +@REM use custom requirements if specified +if not [%requirements_file%]==[] pip install -r %requirements_file% + +@if [%project_tool%]==[mbedcli] ( + @REM setup mbed dependencies + echo Building for mbed cli + + @if [%ARM_PATH%]==[] ( + @echo ARM_PATH variable is not set, trying to autodetect.. + if EXIST C:\KEIL_V4\ARM\ARMCC\ ( + set ARM_PATH=C:\KEIL_V4\ARM\ARMCC + ) else if EXIST C:\KEIL_V5\ARM\ARMCC\ ( + set ARM_PATH=C:\KEIL_V5\ARM\ARMCC + ) else goto error_armpath + ) + @echo USING ARM_PATH=!ARM_PATH! + + mbed deploy + mbed config root . + mbed config ARM_PATH !ARM_PATH! + python tools/mbedcli_compile.py --clean --release + @if !errorlevel! neq 0 exit /B !errorlevel! + python tools/copy_release_files.py --project-tool mbedcli + exit /B !errorlevel! +) else ( + + @REM build bootloader images first (In the future this should be done with a pattern like *_bl) + echo Building for uvision release + progen generate -t uvision -b -p kl26z_bl + progen generate -t uvision -b -p k20dx_bl + progen generate -t uvision -b -p sam3u2c_bl + @REM build but continue if there are errors + progen generate -t uvision -b + @if !errorlevel! neq 0 exit /B !errorlevel! + python tools/copy_release_files.py --project-tool uvision + exit /B !errorlevel! +) + +:error_nomdk +@echo Error: Keil MDK not installed or not found. If you installed it to a +@echo non-default location, you need to set environment variable UV4 to +@echo the path of the executable +@exit /B 1 + +:error_armpath +@echo Error: Need to set environment variable ARM_PATH to +@echo the path of ARM compiler +@exit /B 1
diff -r 000000000000 -r 01f31e923fe2 tools/build_release.sh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/build_release.sh Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,57 @@
+#!/bin/bash -e
+##
+## DAPLink Interface Firmware
+## Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+## SPDX-License-Identifier: Apache-2.0
+##
+## Licensed under the Apache License, Version 2.0 (the "License"); you may
+## not use this file except in compliance with the License.
+## You may obtain a copy of the License at
+##
+## http://www.apache.org/licenses/LICENSE-2.0
+##
+## Unless required by applicable law or agreed to in writing, software
+## distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+## WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+## See the License for the specific language governing permissions and
+## limitations under the License.
+##
+
+project_tool=$1
+env_folder=${2-env}
+requirements_file=${3-requirements.txt}
+
+if [[ "$project_tool" != "mbedcli" && "$project_tool" != "" ]]; then
+ echo "Only mbedcli is supported in Linux build"
+ exit 1
+else
+ echo "Compiling in Linux using mbedcli"
+fi
+
+if [[ "$ARM_PATH" == "" ]]; then
+ echo "Need variable ARM_PATH to point to ARMCC directory"
+ exit 1
+else
+ echo "Using ARMCC in $ARM_PATH"
+fi
+
+echo $env_folder
+echo $requirements_file
+
+if [ ! -d $env_folder ];then
+ echo "Generating virtualenv folder $env_folder"
+ virtualenv $env_folder
+else
+ echo "Using $env_folder"
+fi
+
+source $env_folder/bin/activate
+pip install -r $requirements_file
+mbed deploy
+
+python tools/mbedcli_compile.py --clean --release
+if [ $? -ne 0 ]; then
+ exit $?
+fi
+python tools/copy_release_files.py --project-tool mbedcli
+exit $?
diff -r 000000000000 -r 01f31e923fe2 tools/coding_style/astyle.bat --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/coding_style/astyle.bat Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,51 @@ +:: +:: DAPLink Interface Firmware +:: Copyright (c) 2009-2016, ARM Limited, All Rights Reserved +:: SPDX-License-Identifier: Apache-2.0 +:: +:: Licensed under the Apache License, Version 2.0 (the "License"); you may +:: not use this file except in compliance with the License. +:: You may obtain a copy of the License at +:: +:: http://www.apache.org/licenses/LICENSE-2.0 +:: +:: Unless required by applicable law or agreed to in writing, software +:: distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +:: WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +:: See the License for the specific language governing permissions and +:: limitations under the License. +:: + +@echo off + +:: Get the source path +set /p path_to_source=Enter the source path: +:: a method for removing the surrounding quotes when spaces are used +:: in the path of a passed directory +set path_to_source=%path_to_source:"=% +:: and the types of files to format +set cpp=*.cpp +set cc=*.cc +set c=*.c +set h=*.h +set hh=*.hh +set hh=*.hpp + +echo. +echo formating files of type: +echo %path_to_source%\%cpp% +echo %path_to_source%\%cc% +echo %path_to_source%\%c% +echo %path_to_source%\%h% +echo %path_to_source%\%hh% +echo. + +astyle --options=style.txt "%path_to_source%\%cpp%" +astyle --options=style.txt "%path_to_source%\%cc%" +astyle --options=style.txt "%path_to_source%\%c%" +astyle --options=style.txt "%path_to_source%\%hh%" +astyle --options=style.txt "%path_to_source%\%h%" +astyle --options=style.txt "%path_to_source%\%hpp%" + + +pause \ No newline at end of file
diff -r 000000000000 -r 01f31e923fe2 tools/coding_style/style.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/coding_style/style.txt Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,52 @@ +# +# DAPLink Interface Firmware +# Copyright (c) 2009-2016, ARM Limited, All Rights Reserved +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +# coding style +--style=k&r + +# spaces in place of tabs +-s4 + +#indent switch statements +-S + +#pad statement blocks +-f + +#pad operators in statements and paren in +-p +-U +-H + +#add brackets to single line logic +-j + +#pointers on the name +-k3 +-W3 + +#search folders recursivly for source +-r + +#preserve original files date and time +-Z + +#misc +--delete-empty-lines +--close-templates +--lineend=linux
diff -r 000000000000 -r 01f31e923fe2 tools/combine_images.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/combine_images.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,102 @@
+#!/usr/bin/env python
+
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+import argparse
+import itertools
+import os.path
+from intelhex import IntelHex
+
+
+def ranges(i):
+ for _, b in itertools.groupby(enumerate(i), lambda (x, y): y - x):
+ b = list(b)
+ yield b[0][1], b[-1][1]
+
+
+def print_hex_info(filename, intel_hex):
+ print "File: %s" % filename
+ addresses = intel_hex.addresses()
+ addresses.sort()
+ data_list = list(ranges(addresses))
+ for start, end in data_list:
+ print " 0x%x, 0x%x" % (start, end)
+
+
+def merge_hex(hex1, hex2):
+ hex1_dict = hex1.todict()
+ hex2_dict = hex2.todict()
+
+ # The key "start_addr" shows up the hex
+ # dictionary so remove it
+ if "start_addr" in hex1_dict:
+ del hex1_dict["start_addr"]
+ if "start_addr" in hex2_dict:
+ del hex2_dict["start_addr"]
+
+ keys = hex2_dict.keys()
+ keys.sort()
+
+ # Verify nothing unexpected is in the dict
+ for key in keys:
+ if not type(key) in (int, long):
+ print 'Unknown key "%s" of type %s' % (key, type(key))
+
+ for key in keys:
+ if key in hex1_dict:
+ raise Exception("Overlapping data at 0x%x" % key)
+ hex1_dict[key] = hex2_dict[key]
+ return IntelHex(hex1_dict)
+
+parser = argparse.ArgumentParser(description='Hex file merger')
+parser.add_argument("--hex", type=str, default=[], action='append', help="Hex file to add to list of files to merge. This can be specified multiple times.")
+parser.add_argument("--bin", nargs=2, type=str, default=[], metavar=('FILE', 'ADDR'), action='append', help="Binary file to add to list of files to merge. This can be specified multiple times.")
+parser.add_argument("--output_file", type=str, default='image.hex', help="Name of output hex file.")
+parser.add_argument("--output_bin_file", type=str, help="Name of output binary file. May be specified in addition to --output_file.")
+
+
+def main():
+ args = parser.parse_args()
+ base_hex = IntelHex()
+ # Merge in hex files
+ for file_name in args.hex:
+ file_name = os.path.expanduser(file_name)
+ new_hex_data = IntelHex()
+ print "opening file %s" % file_name
+ new_hex_data.fromfile(file_name, format='hex')
+ print_hex_info(file_name, new_hex_data)
+ base_hex = merge_hex(base_hex, new_hex_data)
+ # Merge in binary files
+ for file_name, addr_str in args.bin:
+ file_name = os.path.expanduser(file_name)
+ offset = int(addr_str, 0)
+ new_hex_data = IntelHex()
+ new_hex_data.loadbin(file_name, offset=offset)
+ print_hex_info(file_name, new_hex_data)
+ base_hex = merge_hex(base_hex, new_hex_data)
+ # Write out data
+ print_hex_info(os.path.expanduser(args.output_file), base_hex)
+ with open(os.path.expanduser(args.output_file), 'wb') as output_file:
+ base_hex.tofile(output_file, 'hex')
+ if args.output_bin_file is not None:
+ with open(os.path.expanduser(args.output_bin_file), 'wb') as output_file:
+ base_hex.tofile(output_file, 'bin')
+
+if __name__ == '__main__':
+ main()
diff -r 000000000000 -r 01f31e923fe2 tools/copy_release_files.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/copy_release_files.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,151 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+"""
+Copy release files from the uvision build directories into a release package
+
+This script is intended to be called the script creating a daplink build.
+"""
+from __future__ import absolute_import
+from __future__ import print_function
+
+import os
+import shutil
+import glob
+import argparse
+
+from subprocess import check_output, CalledProcessError
+
+COPY_PATTERN_LIST = [
+ "%s_crc*.bin",
+ "%s_crc*.hex",
+ "%s_crc*.txt",
+ ]
+OPTIONAL_COPY_PATTERN_LIST = [
+ "%s.axf",
+ "%s.elf",
+ "%s_crc*.c",
+ "%s.build_log.htm",
+ "%s.map",
+ "%s.htm",
+ "%s_map.html",
+]
+
+TOOL_DIR = {
+ 'uvision' : { 'proj_dir': os.path.join('projectfiles', 'uvision') , 'rel_dir' : 'uvision_release', 'build_dir' : 'build' },
+ 'mbedcli' : { 'proj_dir': 'BUILD' , 'rel_dir' : 'mbedcli_release', 'build_dir' : 'ARM-CUSTOM_PROFILE' }
+}
+
+def generate_info_files(dir):
+
+ output_info_file = os.path.join(os.path.normpath(dir),'git_info.txt')
+ output_requirements_file = os.path.join(os.path.normpath(dir),'build_requirements.txt')
+
+ # Get the git SHA.
+ try:
+ git_sha = check_output("git rev-parse --verify HEAD", shell=True)
+ git_sha = git_sha.decode().strip()
+ except:
+ print("ERROR - failed to get git SHA, do you have git.exe in your PATH environment variable?")
+ return 1
+
+ # Check are there any local, uncommitted modifications.
+ try:
+ check_output("git diff --no-ext-diff --quiet --exit-code", shell=True)
+ except (CalledProcessError, OSError):
+ git_has_changes = '1'
+ else:
+ git_has_changes = '0'
+
+ # Get the requirements version.
+ try:
+ pip_freeze = check_output("pip list", shell=True).decode().strip()
+ except:
+ print("ERROR - failed requirements, pip not installed?")
+ return 1
+
+
+ # Create the version files
+ try:
+ with open(output_info_file, 'w+') as file:
+ file.write(git_sha + '\n' + 'Uncommitted Changes:' + git_has_changes + '\n' )
+ with open(output_requirements_file, 'w+') as file:
+ file.write(pip_freeze)
+ except IOError:
+ print("Error - failed to write information and version files")
+ return 1;
+ return 0
+
+
+def main():
+ """Copy imporant files for the current release"""
+ parser = argparse.ArgumentParser(description='Copy imporant files for the current release')
+ parser.add_argument('--project-tool', type=str, default='uvision', choices=['uvision', 'mbedcli'], help='Choose from uvision and mbedcli')
+ args = parser.parse_args()
+
+ self_path = os.path.abspath(__file__)
+ tools_dir = os.path.dirname(self_path)
+ daplink_dir = os.path.dirname(tools_dir)
+
+ if os.path.basename(tools_dir) != "tools":
+ print("Error - this script must be run from the tools directory")
+ exit(-1)
+
+ proj_dir = os.path.join(daplink_dir, TOOL_DIR[args.project_tool]['proj_dir'])
+ rel_dir = os.path.join(daplink_dir, TOOL_DIR[args.project_tool]['rel_dir'])
+ build_dir = TOOL_DIR[args.project_tool]['build_dir']
+ # Make sure uvision dir is present
+ if not os.path.isdir(proj_dir):
+ print("Error - uvision directory '%s' missing" % proj_dir)
+ exit(-1)
+
+ # Clean release dir is present
+ if os.path.isdir(rel_dir):
+ shutil.rmtree(rel_dir)
+
+ os.mkdir(rel_dir)
+
+ generate_info_files(rel_dir)
+
+ project_list = os.listdir(proj_dir)
+ for project in project_list:
+ src_dir = os.path.join(proj_dir, project, build_dir)
+ dest_dir = os.path.join(rel_dir, project.lower())
+
+ #only copy a built project
+ if not os.path.exists(src_dir):
+ continue
+
+ # File must not have been copied already
+ if os.path.exists(dest_dir):
+ print("Error - package dir '%s' alread exists" % dest_dir)
+ exit(-1)
+ os.mkdir(dest_dir)
+
+ for file_pattern in COPY_PATTERN_LIST:
+ file_name = file_pattern % project.lower()
+ file_source = os.path.join(src_dir, file_name)
+ for file_wild in glob.glob(file_source):
+ shutil.copy(file_wild, dest_dir)
+ for file_pattern in OPTIONAL_COPY_PATTERN_LIST:
+ file_name = file_pattern % project.lower()
+ file_source = os.path.join(src_dir, file_name)
+ for file_wild in glob.glob(file_source):
+ shutil.copy(file_wild, dest_dir)
+
+main()
diff -r 000000000000 -r 01f31e923fe2 tools/flash_algo.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/flash_algo.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,359 @@
+#!/usr/bin/env python
+"""
+ mbed
+ Copyright (c) 2017-2019 ARM Limited
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+"""
+
+from __future__ import print_function
+import os
+import struct
+import binascii
+import argparse
+import logging
+from six.moves import StringIO
+import jinja2
+from collections import namedtuple
+from itertools import count
+
+from elftools.common.py3compat import bytes2str
+from elftools.elf.elffile import ELFFile
+from elftools.elf.sections import SymbolTableSection
+
+logger = logging.getLogger(__name__)
+logger.addHandler(logging.NullHandler())
+
+
+def main():
+ parser = argparse.ArgumentParser(description="Algo Extracter")
+ parser.add_argument("input", help="File to extract flash algo from")
+ parser.add_argument("template", default="py_blob.tmpl",
+ help="Template to use")
+ parser.add_argument("output", help="Output file")
+ args = parser.parse_args()
+
+ with open(args.input, "rb") as file_handle:
+ data = file_handle.read()
+ algo = PackFlashAlgo(data)
+ algo.process_template(args.template, args.output)
+
+
+class PackFlashAlgo(object):
+ """
+ Class to wrap a flash algo
+
+ This class is intended to provide easy access to the information
+ provided by a flash algorithm, such as symbols and the flash
+ algorithm itself.
+ """
+
+ REQUIRED_SYMBOLS = set([
+ "Init",
+ "UnInit",
+ "EraseSector",
+ "ProgramPage",
+ ])
+
+ EXTRA_SYMBOLS = set([
+ "BlankCheck",
+ "EraseChip",
+ "Verify",
+ ])
+
+ def __init__(self, data):
+ """Construct a PackFlashAlgorithm from an ElfFileSimple"""
+ self.elf = ElfFileSimple(data)
+ self.flash_info = PackFlashInfo(self.elf)
+
+ self.flash_start = self.flash_info.start
+ self.flash_size = self.flash_info.size
+ self.page_size = self.flash_info.page_size
+ self.sector_sizes = self.flash_info.sector_info_list
+
+ symbols = {}
+ symbols.update(_extract_symbols(self.elf, self.REQUIRED_SYMBOLS))
+ symbols.update(_extract_symbols(self.elf, self.EXTRA_SYMBOLS,
+ default=0xFFFFFFFF))
+ self.symbols = symbols
+
+ sections_to_find = (
+ ("PrgCode", "SHT_PROGBITS"),
+ ("PrgData", "SHT_PROGBITS"),
+ ("PrgData", "SHT_NOBITS"),
+ )
+
+ ro_rw_zi = _find_sections(self.elf, sections_to_find)
+ ro_rw_zi = _algo_fill_zi_if_missing(ro_rw_zi)
+ error_msg = _algo_check_for_section_problems(ro_rw_zi)
+ if error_msg is not None:
+ raise Exception(error_msg)
+
+ sect_ro, sect_rw, sect_zi = ro_rw_zi
+ self.ro_start = sect_ro["sh_addr"]
+ self.ro_size = sect_ro["sh_size"]
+ self.rw_start = sect_rw["sh_addr"]
+ self.rw_size = sect_rw["sh_size"]
+ self.zi_start = sect_zi["sh_addr"]
+ self.zi_size = sect_zi["sh_size"]
+
+ self.algo_data = _create_algo_bin(ro_rw_zi)
+
+ def format_algo_data(self, spaces, group_size, fmt):
+ """"
+ Return a string representing algo_data suitable for use in a template
+
+ The string is intended for use in a template.
+
+ :param spaces: The number of leading spaces for each line
+ :param group_size: number of elements per line (element type
+ depends of format)
+ :param fmt: - format to create - can be either "hex" or "c"
+ """
+ padding = " " * spaces
+ if fmt == "hex":
+ blob = binascii.b2a_hex(self.algo_data)
+ line_list = []
+ for i in xrange(0, len(blob), group_size):
+ line_list.append('"' + blob[i:i + group_size] + '"')
+ return ("\n" + padding).join(line_list)
+ elif fmt == "c":
+ blob = self.algo_data[:]
+ pad_size = 0 if len(blob) % 4 == 0 else 4 - len(blob) % 4
+ blob = blob + "\x00" * pad_size
+ integer_list = struct.unpack("<" + "L" * (len(blob) / 4), blob)
+ line_list = []
+ for pos in range(0, len(integer_list), group_size):
+ group = ["0x%08x" % value for value in
+ integer_list[pos:pos + group_size]]
+ line_list.append(", ".join(group))
+ return (",\n" + padding).join(line_list)
+ else:
+ raise Exception("Unsupported format %s" % fmt)
+
+ def process_template(self, template_path, output_path, data_dict=None):
+ """
+ Generate output from the supplied template
+
+ All the public methods and fields of this class can be accessed from
+ the template via "algo".
+
+ :param template_path: Relative or absolute file path to the template
+ :param output_path: Relative or absolute file path to create
+ :param data_dict: Additional data to use when generating
+ """
+ if data_dict is None:
+ data_dict = {}
+ else:
+ assert isinstance(data_dict, dict)
+ data_dict = dict(data_dict)
+ assert "algo" not in data_dict, "algo already set by user data"
+ data_dict["algo"] = self
+
+ with open(template_path) as file_handle:
+ template_text = file_handle.read()
+
+ template = jinja2.Template(template_text)
+ target_text = template.render(data_dict)
+
+ with open(output_path, "wb") as file_handle:
+ file_handle.write(target_text)
+
+
+def _extract_symbols(simple_elf, symbols, default=None):
+ """Fill 'symbols' field with required flash algo symbols"""
+ to_ret = {}
+ for symbol in symbols:
+ if symbol not in simple_elf.symbols:
+ if default is not None:
+ to_ret[symbol] = default
+ continue
+ raise Exception("Missing symbol %s" % symbol)
+ to_ret[symbol] = simple_elf.symbols[symbol].value
+ return to_ret
+
+
+def _find_sections(elf, name_type_pairs):
+ """Return a list of sections the same length and order of the input list"""
+ sections = [None] * len(name_type_pairs)
+ for section in elf.iter_sections():
+ section_name = bytes2str(section.name)
+ section_type = section["sh_type"]
+ for i, name_and_type in enumerate(name_type_pairs):
+ if name_and_type != (section_name, section_type):
+ continue
+ if sections[i] is not None:
+ raise Exception("Elf contains duplicate section %s attr %s" %
+ (section_name, section_type))
+ sections[i] = section
+ return sections
+
+
+def _algo_fill_zi_if_missing(ro_rw_zi):
+ """Create an empty zi section if it is missing"""
+ s_ro, s_rw, s_zi = ro_rw_zi
+ if s_rw is None:
+ return ro_rw_zi
+ if s_zi is not None:
+ return ro_rw_zi
+ s_zi = {
+ "sh_addr": s_rw["sh_addr"] + s_rw["sh_size"],
+ "sh_size": 0
+ }
+ return s_ro, s_rw, s_zi
+
+
+def _algo_check_for_section_problems(ro_rw_zi):
+ """Return a string describing any errors with the layout or None if good"""
+ s_ro, s_rw, s_zi = ro_rw_zi
+ if s_ro is None:
+ return "RO section is missing"
+ if s_rw is None:
+ return "RW section is missing"
+ if s_zi is None:
+ return "ZI section is missing"
+ if s_ro["sh_addr"] != 0:
+ return "RO section does not start at address 0"
+ if s_ro["sh_addr"] + s_ro["sh_size"] != s_rw["sh_addr"]:
+ return "RW section does not follow RO section"
+ if s_rw["sh_addr"] + s_rw["sh_size"] != s_zi["sh_addr"]:
+ return "ZI section does not follow RW section"
+ return None
+
+
+def _create_algo_bin(ro_rw_zi):
+ """Create a binary blob of the flash algo which can execute from ram"""
+ sect_ro, sect_rw, sect_zi = ro_rw_zi
+ algo_size = sect_ro["sh_size"] + sect_rw["sh_size"] + sect_zi["sh_size"]
+ algo_data = bytearray(algo_size)
+ for section in (sect_ro, sect_rw):
+ start = section["sh_addr"]
+ size = section["sh_size"]
+ data = section.data()
+ assert len(data) == size
+ algo_data[start:start + size] = data
+ return algo_data
+
+
+class PackFlashInfo(object):
+ """Wrapper class for the non-executable information in an FLM file"""
+
+ FLASH_DEVICE_STRUCT = "<H128sHLLLLBxxxLL"
+ FLASH_SECTORS_STRUCT = "<LL"
+ FLASH_SECTORS_STRUCT_SIZE = struct.calcsize(FLASH_SECTORS_STRUCT)
+ SECTOR_END = 0xFFFFFFFF
+
+ def __init__(self, elf_simple):
+ dev_info = elf_simple.symbols["FlashDevice"]
+ info_start = dev_info.value
+ info_size = struct.calcsize(self.FLASH_DEVICE_STRUCT)
+ data = elf_simple.read(info_start, info_size)
+ values = struct.unpack(self.FLASH_DEVICE_STRUCT, data)
+
+ self.version = values[0]
+ self.name = values[1].strip("\x00")
+ self.type = values[2]
+ self.start = values[3]
+ self.size = values[4]
+ self.page_size = values[5]
+ self.value_empty = values[7]
+ self.prog_timeout_ms = values[8]
+ self.erase_timeout_ms = values[9]
+
+ sector_gen = self._sector_and_sz_itr(elf_simple,
+ info_start + info_size)
+ self.sector_info_list = list(sector_gen)
+
+ def __str__(self):
+ desc = ""
+ desc += "Flash Device:" + os.linesep
+ desc += " name=%s" % self.name + os.linesep
+ desc += " version=0x%x" % self.version + os.linesep
+ desc += " type=%i" % self.type + os.linesep
+ desc += " start=0x%x" % self.start + os.linesep
+ desc += " size=0x%x" % self.size + os.linesep
+ desc += " page_size=0x%x" % self.page_size + os.linesep
+ desc += " value_empty=0x%x" % self.value_empty + os.linesep
+ desc += " prog_timeout_ms=%i" % self.prog_timeout_ms + os.linesep
+ desc += " erase_timeout_ms=%i" % self.erase_timeout_ms + os.linesep
+ desc += " sectors:" + os.linesep
+ for sector_start, sector_size in self.sector_info_list:
+ desc += (" start=0x%x, size=0x%x" %
+ (sector_start, sector_size) + os.linesep)
+ return desc
+
+ def _sector_and_sz_itr(self, elf_simple, data_start):
+ """Iterator which returns starting address and sector size"""
+ for entry_start in count(data_start, self.FLASH_SECTORS_STRUCT_SIZE):
+ data = elf_simple.read(entry_start, self.FLASH_SECTORS_STRUCT_SIZE)
+ size, start = struct.unpack(self.FLASH_SECTORS_STRUCT, data)
+ start_and_size = start, size
+ if start_and_size == (self.SECTOR_END, self.SECTOR_END):
+ return
+ yield start_and_size
+
+
+SymbolSimple = namedtuple("SymbolSimple", "name, value, size")
+
+
+class ElfFileSimple(ELFFile):
+ """Wrapper for elf object which allows easy access to symbols and rom"""
+
+ def __init__(self, data):
+ """Construct a ElfFileSimple from bytes or a bytearray"""
+ super(ElfFileSimple, self).__init__(StringIO.StringIO(data))
+ self.symbols = self._read_symbol_table()
+
+ def _read_symbol_table(self):
+ """Read the symbol table into the field "symbols" for easy use"""
+ section = self.get_section_by_name(b".symtab")
+ if not section:
+ raise Exception("Missing symbol table")
+
+ if not isinstance(section, SymbolTableSection):
+ raise Exception("Invalid symbol table section")
+
+ symbols = {}
+ for symbol in section.iter_symbols():
+ name_str = bytes2str(symbol.name)
+ if name_str in symbols:
+ logging.debug("Duplicate symbol %s", name_str)
+ symbols[name_str] = SymbolSimple(name_str, symbol["st_value"],
+ symbol["st_size"])
+ return symbols
+
+ def read(self, addr, size):
+ """Read program data from the elf file
+
+ :param addr: physical address (load address) to read from
+ :param size: number of bytes to read
+ :return: Requested data or None if address is unmapped
+ """
+ for segment in self.iter_segments():
+ seg_addr = segment["p_paddr"]
+ seg_size = min(segment["p_memsz"], segment["p_filesz"])
+ if addr >= seg_addr + seg_size:
+ continue
+ if addr + size <= seg_addr:
+ continue
+ # There is at least some overlap
+
+ if addr >= seg_addr and addr + size <= seg_addr + seg_size:
+ # Region is fully contained
+ data = segment.data()
+ start = addr - seg_addr
+ return data[start:start + size]
+
+
+if __name__ == '__main__':
+ main()
diff -r 000000000000 -r 01f31e923fe2 tools/generate_config.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/generate_config.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,82 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+import struct
+import argparse
+from intelhex import IntelHex
+
+CFG_KEY = 0x6b766c64
+# Must stay in sync with the structure cfg_setting
+# in the header file config_settings.h:
+# 32 - key
+# 16 - offset_of_end
+# 8 - auto_rst
+# 8 - automation_allowed
+# 8 - overflow_detect
+# 0 - 'end' member omitted
+FORMAT = '<LHBBB'
+FORMAT_LENGTH = struct.calcsize(FORMAT)
+MINIMUM_ALIGN = 1 << 10 # 1k aligned
+
+
+def create_hex(filename, addr, auto_rst, automation_allowed,
+ overflow_detect, pad_size):
+ file_format = 'hex'
+ intel_hex = IntelHex()
+ intel_hex.puts(addr, struct.pack(FORMAT, CFG_KEY, FORMAT_LENGTH, auto_rst,
+ automation_allowed, overflow_detect))
+ pad_addr = addr + FORMAT_LENGTH
+ pad_byte_count = pad_size - (FORMAT_LENGTH % pad_size)
+ pad_data = '\xFF' * pad_byte_count
+ intel_hex.puts(pad_addr, pad_data)
+ with open(filename, 'wb') as f:
+ intel_hex.tofile(f, file_format)
+
+
+def str_to_int(val):
+ return int(val, 0)
+
+
+POWERS_OF_TWO = [2**num for num in range(0, 32)]
+parser = argparse.ArgumentParser(description='Configuration Creator')
+parser.add_argument("--addr", type=str_to_int, required=True, help="Address of configuration data")
+parser.add_argument("--auto_rst", type=int, required=True, choices=[0, 1], help="Auto reset configuration value")
+parser.add_argument("--automation_allowed", type=int, required=True, choices=[0,1], help="Allow automation from filesystem interaction")
+parser.add_argument("--overflow_detect", type=int, required=True, choices=[0,1], help="Enable detection of UART overflow")
+parser.add_argument("--pad", type=int, default=16, choices=POWERS_OF_TWO, metavar="{1, 2, 4,...}", help="Byte aligned boundary to pad region to")
+parser.add_argument("--output_file", type=str, default='settings.hex', help="Name of output file")
+
+
+def main():
+ args = parser.parse_args()
+ print "Output file %s" % args.output_file
+ print "Config Offset 0x%x" % args.addr
+ if args.addr % MINIMUM_ALIGN != 0:
+ print "WARNING! Configuration is not on a 1K boundary"
+ if args.addr % args.pad != 0:
+ print "WARNING! Configuration is not aligned to pad size"
+ print "Settings:"
+ print " auto_rst: %i" % args.auto_rst
+ print " automation_allowed: %i" % args.automation_allowed
+ print " overflow_detect: %i" % args.overflow_detect
+ print ""
+ create_hex(args.output_file, args.addr, args.auto_rst,
+ args.automation_allowed, args.overflow_detect, args.pad)
+
+if __name__ == '__main__':
+ main()
diff -r 000000000000 -r 01f31e923fe2 tools/launch_uvision.bat --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/launch_uvision.bat Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,68 @@ +:: +:: DAPLink Interface Firmware +:: Copyright (c) 2009-2016, ARM Limited, All Rights Reserved +:: SPDX-License-Identifier: Apache-2.0 +:: +:: Licensed under the Apache License, Version 2.0 (the "License"); you may +:: not use this file except in compliance with the License. +:: You may obtain a copy of the License at +:: +:: http://www.apache.org/licenses/LICENSE-2.0 +:: +:: Unless required by applicable law or agreed to in writing, software +:: distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +:: WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +:: See the License for the specific language governing permissions and +:: limitations under the License. +:: +:: Launches uVision with the python environment needed to build DAPLink +:: +:: git and python are expected to be in PATH. Project will fail to build otherwise +:: + +setlocal + +@rem Script assumes working directory is workspace root. Force it. +cd %~dp0..\ + +@rem See if we can find uVision. This logic is consistent with progen +@if [%UV4%]==[] ( + @echo UV4 variable is not set, trying to autodetect.. + if EXIST c:\keil\uv4\uv4.exe ( + set UV4=c:\keil\uv4\uv4.exe + ) else if EXIST c:\keil_v5\uv4\uv4.exe ( + set UV4=c:\keil_v5\uv4\uv4.exe + ) else goto error_nomdk +) +@echo USING UV4=%UV4% +set uv4exe=%UV4% + +@rem Select an existing virtualenv as first parameter +@if not [%1]==[] ( + echo Using virtualenv %1 + @if exist %1 call %1\Scripts\activate && goto :env_folder_ok +) else ( + @if exist env goto :env_ok +) + + +echo Creating python virtual environment && virtualenv env +:env_ok +call env\Scripts\activate +:env_folder_ok + +@echo Doing pip install +@REM use project requirements if not specified +if [%2]==[] pip install -r requirements.txt +@REM use custom requirements if specified +if not [%2]==[] pip install -r %2 + +start %uv4exe% +exit /B 0 + +:error_nomdk +@echo Error: Keil MDK not installed or not found. If you installed it to a +@echo non-default location, you need to set environment variable UV4 to +@echo the path of the executable +@exit /B 1 +
diff -r 000000000000 -r 01f31e923fe2 tools/make_update_yml.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/make_update_yml.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,176 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2018, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+import logging
+
+logging.basicConfig(format='Line: %(lineno)d %(message)s')
+logger = logging.getLogger('yaml gen')
+logger.setLevel(logging.DEBUG)
+
+
+class DefaultList(list):
+ def sort(self, *args, **kwargs):
+ pass
+
+class TargetList(list):
+ def sort(self, *args, **kwargs):
+ pass
+
+class InstructionList(list):
+ def sort(self, *args, **kwargs):
+ pass
+
+
+#instruction steps for firmware
+InstructionsText = {
+ 'default':InstructionList([
+ ('windows', [
+ '1. Download the firmware file.',
+ '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate and mount as `BOOTLOADER` or `MAINTENANCE`. For boards that enumerate as `BOOTLOADER` [see our blog to determine if an update for the DAPLink bootloader is available.](https://os.mbed.com/blog/entry/DAPLink-bootloader-update/)',
+ '3. Drag-and-drop the firmware file onto the mounted drive.',
+ '4. Wait for the file copy operation to complete.',
+ '5. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.'
+ ]),
+ ('osx', [
+ '1. Download the firmware file.',
+ '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate as `BOOTLOADER` or `MAINTENANCE`. For boards that enumerate as `BOOTLOADER` [see our blog to determine if an update for the DAPLink bootloader is available.](https://os.mbed.com/blog/entry/DAPLink-bootloader-update/)',
+ '3. In a terminal execute',
+ ' - `sudo mount -u -w -o sync /Volumes/MAINTENANCE ; cp -X <path to firmware file> /Volumes/MAINTENANCE/`',
+ ' - Note: If your drive does not mount as `MAINTENANCE` make sure to change this to match the name of the mounted disk attached to your system.',
+ '4. Wait for the file copy operation to complete.',
+ '5. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.'
+ ]),
+ ('linux', [
+ '1. Download the firmware file.',
+ '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate as `BOOTLOADER` or `MAINTENANCE`. For boards that enumerate as `BOOTLOADER` [see our blog to determine if an update for the DAPLink bootloader is available.](https://os.mbed.com/blog/entry/DAPLink-bootloader-update/)',
+ '3. In a terminal execute',
+ ' - `cp <path to firmware file> <MAINTENANCE> && sync`',
+ ' - Note: make sure to change `MAINTENANCE` to the name of the mount point of the drive on your system.',
+ '4. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.'
+ ])
+ ]),
+ 'lpc11u35':InstructionList([
+ ('windows', [
+ '1. Download the firmware file.',
+ '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate and mount as `CRP DISABLD`',
+ '3. Delete the file named `firmware.bin`, then drag and drop or copy the new bin file',
+ '4. Wait for the file copy operation to complete.',
+ '5. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.'
+ ]),
+ ('osx', [
+ '1. Download the firmware file.',
+ '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate and mount as `CRP DISABLD`',
+ '3. Delete the file named `firmware.bin`',
+ '4. In a terminal execute',
+ ' - `sudo mount -u -w -o sync /Volumes/CRP\ DISABLD ; rm /Volumes/CRP\ DISABLD/firmware.bin && cp -X <path to firmware file> /Volumes/CRP\ DISABLD/`',
+ '5. Wait for the file copy operation to complete.',
+ '6. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.'
+ ]),
+ ('linux', [
+ '1. Download the firmware file.',
+ '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate and mount as `CRP DISABLD`',
+ '3. Delete the file named `firmware.bin`',
+ '4. In a terminal execute',
+ ' - `cp <path to firmware file> <CRP DISABLD> && sync`',
+ ' - Note: make sure to change `CRP DISABLD` to the name of the mount point on your system.',
+ '5. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.'
+ ])
+ ])
+
+}
+
+
+def string_writer(element):
+ if type(element) is str:
+ return element
+ elif type(element) is int:
+ return "_0x%04i" % element
+ else:
+ return None
+
+
+def yml_object_parser(f, entry, level, tabs):
+ header = " " * level * tabs
+ if type(entry) is list:
+ for element in entry:
+ yml_object_parser(f, element, level, tabs);
+
+ elif type(entry) is dict:
+ for key in entry:
+ f.write('-' + ' ' * (level * tabs -1) + string_writer(key) + ": ");
+ value = string_writer(entry[key])
+ if value is not None:
+ f.write(value)
+ f.write('\n')
+ else:
+ f.write('\n')
+ yml_object_parser(f, entry[key], level + 1, tabs);
+
+
+ elif type(entry) is DefaultList:
+ for target in entry:
+ if type(target) is tuple:
+ #print target
+ f.write(" " * level * tabs + string_writer(target[0]) + ": ");
+ value = string_writer(target[1])
+ if value is not None:
+ f.write(value)
+ f.write('\n')
+ else:
+ f.write('\n')
+ yml_object_parser(f, target[1], level + 1, tabs);
+ else:
+ logger.error("Not expecting input type %s %s " % (type(target), str(target)))
+
+ elif type(entry) is TargetList:
+ #print "found TargetList"
+ for target in entry:
+ if type(target) is tuple:
+ #print target
+ f.write(" " * (level-1) * tabs + string_writer(target[0]) + ": ");
+ value = string_writer(target[1])
+ if value is not None:
+ f.write(value)
+ f.write('\n')
+ else:
+ f.write('\n')
+ yml_object_parser(f, target[1], level, tabs);
+ else:
+ logger.error("Not expecting input type %s %s " % (type(target), str(target)))
+
+ elif type(entry) is InstructionList:
+ #print "found InstructionList"
+ for target in entry:
+ if type(target) is tuple:
+ f.write(" " * level * tabs + string_writer(target[0]) + ": |\n")
+ if type(target[1]) is list:
+ for texts in target[1]:
+ f.write(" " * (level + 1) * tabs + string_writer(texts) + "\n")
+ else:
+ logger.error("Not expecting input type %s %s " % (type(target[1]), str(target[1])))
+ else:
+ logger.error("Not expecting input type %s %s " % (type(target), str(target)))
+ else:
+ logger.error("Not expecting input type %s %s " % (type(entry), str(entry)))
+
+
+def make_update_yml_file(file_loc, entries, explicit_start=False, tab=2):
+ with open(file_loc, "w") as yml_file:
+ if explicit_start is True:
+ yml_file.write("---\n")
+ yml_object_parser(yml_file, entries, 1, tab);
diff -r 000000000000 -r 01f31e923fe2 tools/mbedcli_compile.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/mbedcli_compile.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,122 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2018, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+import argparse
+import os
+import sys
+import shutil
+import yaml
+import mbedcli_tools
+from pre_build_script import generate_version_file
+from package_release_files import package_release_files
+from post_build_script import post_build_script
+
+self_path = os.path.abspath(__file__)
+tools_dir = os.path.dirname(self_path)
+daplink_dir = os.path.dirname(tools_dir)
+test_dir = os.path.join(daplink_dir, "test")
+sys.path.append(test_dir)
+
+import info
+
+PROJECTS_YAML = "projects.yaml"
+VERSION_YAML = "version.yaml"
+
+def main():
+ """python -u tools/mbedcli_compile.py kl26z_microbit_if kl26z_bl --clean"""
+ #parse project yaml file for project list
+ project_list = []
+ with open(PROJECTS_YAML, 'r') as top_yaml:
+ try:
+ topdict = yaml.load(top_yaml)
+ for dict_key in topdict:
+ if dict_key == 'projects':
+ for project in topdict[dict_key]:
+ project_list.append(project)
+ break
+ except yaml.YAMLError as ex:
+ print("Found yaml parse error", ex)
+ #parse the arguments
+ projects = "List of supported projects\n\n" + ", ".join(project_list) #
+ parser = argparse.ArgumentParser(description='mbedcli compile support for DAPLink', epilog=projects, formatter_class=argparse.RawDescriptionHelpFormatter)
+ parser.add_argument('projects', help='Selectively compile only the firmware specified otherwise all projects',
+ nargs='*', type=str, default=[])
+ parser.add_argument("--board-id", type=str, help="board id to for the target in hex")
+ parser.add_argument("--family-id", type=str, help="family id to for the target in hex")
+ parser.add_argument("--bin-offset", type=str, help="binary offset in hex")
+ parser.add_argument('--release', dest='release', action='store_true', help='Create a release with the yaml version file')
+ parser.add_argument('--build-folder', type=str, default='BUILD', help='Release directory to grab files from')
+ parser.add_argument('--release-folder', type=str, default='firmware', help='Directory to create and place files in')
+ parser.add_argument('--toolchain', type=str, default='ARM', help='Toolchain directory if present')
+ parser.add_argument('--clean', dest='clean', action='store_true', help='Rebuild or delete build folder before compile')
+ parser.add_argument('-v', dest='verbosity', action='count', help='Pass verbosity level to mbed compile -vv for more')
+ parser.set_defaults(clean=False)
+ parser.set_defaults(release=False)
+ args = parser.parse_args()
+ self_path = os.path.abspath(__file__)
+ tools_dir = os.path.dirname(self_path)
+ daplink_dir = os.path.dirname(tools_dir)
+ if os.path.basename(tools_dir) != "tools":
+ print("Error - this script must be run from the tools directory")
+ exit(-1)
+ version_git_dir = os.path.join(daplink_dir, "source", "daplink")
+ generate_version_file(version_git_dir)
+ if not args.projects == []:
+ for project in args.projects:
+ print("Compiling %s" % project)
+ (cli_hex_output,crc_file_output) = mbedcli_tools.mbedcli_run(daplink_dir, args.build_folder, project, args.toolchain, args.clean, args.verbosity)
+ print("Creating crc padded binaries %s" % os.path.basename(cli_hex_output))
+ post_build_script(cli_hex_output, crc_file_output, args.board_id, args.family_id, args.bin_offset)
+ else:
+ print("compiling all firmware")
+ #generate a dictionary of board ID, and family ID
+ id_map = {}
+ for board_id, family_id, firmware, bootloader, target in info.SUPPORTED_CONFIGURATIONS:
+ if firmware in id_map:
+ id_map[firmware].append((hex(board_id), hex(family_id)))
+ else:
+ id_map[firmware] = [(hex(board_id), hex(family_id))]
+ for project in project_list:
+ print("Compiling %s" % project)
+ (cli_hex_output,crc_file_output) = mbedcli_tools.mbedcli_run(daplink_dir, args.build_folder, project, args.toolchain, args.clean, args.verbosity)
+ print("Creating crc padded binaries %s" % os.path.basename(cli_hex_output))
+ #can be a legacy build or 0 board_id and family_id
+ post_build_script(cli_hex_output, crc_file_output)
+ #do a build with board_id and family_id
+ if project in id_map:
+ for (boardid, familyid) in id_map[project]:
+ print(project, boardid, familyid)
+ post_build_script(cli_hex_output, crc_file_output, boardid, familyid)
+ if args.release is True:
+ release_version = 0
+ with open(os.path.join("records","tools", VERSION_YAML), 'r') as ver_yaml:
+ try:
+ verdict = yaml.load(ver_yaml)
+ release_version = int(verdict['common']['macros'][0].split('=')[1])
+ except yaml.YAMLError as ex:
+ print("Found yaml parse error", ex)
+
+ release_dir = args.release_folder + "_%04i" % release_version
+ if os.path.exists(release_dir):
+ print("Deleting %s" % release_dir)
+ shutil.rmtree(release_dir, ignore_errors=True)
+ print("Releasing directory: " + release_dir)
+ toolchain_dir = args.toolchain+"-CUSTOM_PROFILE"
+ package_release_files(args.build_folder, release_dir, release_version, toolchain_dir)
+
+main()
diff -r 000000000000 -r 01f31e923fe2 tools/mbedcli_tools/__init__.py --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/mbedcli_tools/__init__.py Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,19 @@ +# +# DAPLink Interface Firmware +# Copyright (c) 2009-2018, ARM Limited, All Rights Reserved +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +from mbedcli_run import mbedcli_run
diff -r 000000000000 -r 01f31e923fe2 tools/mbedcli_tools/generate_custom_cli_files.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/mbedcli_tools/generate_custom_cli_files.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,65 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2018, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+import json
+
+def generate_custom_profile(build_dicts, compiler='ARM', tool_search='make_armcc', filename = 'custom_profile.json'):
+ profile_dict = {
+ compiler: {
+ "common": [],
+ "asm": [],
+ "c": [],
+ "cxx": [],
+ "ld": []
+ }
+ }
+ if 'tool_specific' in build_dicts:
+ for entry in build_dicts['tool_specific']:
+ if entry == tool_search:
+ if 'misc' in build_dicts['tool_specific'][entry]:
+ for flags in build_dicts['tool_specific'][entry]['misc']:
+ if flags.endswith('_flags'):
+ cli_entry = flags[:-len('_flags')]
+ if cli_entry in profile_dict[compiler]:
+ profile_dict[compiler][cli_entry].extend(build_dicts['tool_specific'][entry]['misc'][flags])
+ else:
+ profile_dict[compiler][cli_entry] = build_dicts['tool_specific'][entry]['misc'][flags]
+
+ with open(filename, 'w') as custom_profile:
+ json.dump(profile_dict, custom_profile, indent=4, separators=(',', ': '))
+
+def generate_custom_targets(target_name, build_dicts, out_ext='hex', filename = 'custom_targets.json'):
+ target_dict = {
+ target_name : {
+ "core": build_dicts['common']['core'][0],
+ "supported_toolchains": ["ARM"],
+ "inherits": ["Target"],
+ "OUTPUT_EXT": out_ext,
+ "macros" : []
+ }
+ }
+ if 'common' in build_dicts:
+ for entry in build_dicts['common']:
+ if entry == 'macros':
+ if entry in target_dict[target_name]:
+ target_dict[target_name][entry].extend(build_dicts['common'][entry])
+ else:
+ target_dict[target_name][entry] = build_dicts['common'][entry]
+
+ with open(filename, 'w') as custom_targets:
+ json.dump(target_dict,custom_targets, indent=4, separators=(',', ': '))
diff -r 000000000000 -r 01f31e923fe2 tools/mbedcli_tools/generate_mbedcli_files.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/mbedcli_tools/generate_mbedcli_files.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,88 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2018, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+import argparse
+import yaml
+import sys
+import logging
+from generate_custom_cli_files import generate_custom_targets
+from generate_custom_cli_files import generate_custom_profile
+from generate_mbedignore import generate_mbedignore
+
+logging.basicConfig(format='Line: %(lineno)d %(message)s')
+logger = logging.getLogger('yaml gen')
+logger.setLevel(logging.DEBUG)
+
+def parse_yaml_dicts(input_dicts, output_dicts):
+ for key in input_dicts:
+ if key in output_dicts: #merge
+ if type(output_dicts[key]) is dict:
+ parse_yaml_dicts(input_dicts[key], output_dicts[key])
+ elif type(output_dicts[key]) is list:
+ output_dicts[key].extend(input_dicts[key])
+ else:
+ logger.error('Wrong type', typeof(output_dicts[key]))
+ else:
+ output_dicts[key] = input_dicts[key]
+
+def parse_yaml_files(list_of_list, data_dict):
+ if type(list_of_list) is list:
+ for entry in list_of_list:
+ if type(entry) is list:
+ parse_yaml_files(entry, data_dict)
+ elif type(entry) is str and entry.endswith('.yaml'):
+ try:
+ with open(entry, 'r') as yaml_file:
+ yaml_entries = yaml.load(yaml_file)
+ parse_yaml_dicts(yaml_entries, data_dict)
+
+ except yaml.YAMLError as ex:
+ logger.error("Found yaml parse error", ex)
+ else:
+ logger.error('Wrong type', typeof(entry))
+ else:
+ logger.error('Wrong type', typeof(list_of_list))
+
+def generate_mbedcli_files(projects_yaml, target_project):
+ with open(projects_yaml, 'r') as top_yaml:
+ try:
+ build_data = {}
+ topdict = yaml.load(top_yaml)
+ for dict_key in topdict:
+ if dict_key == 'projects':
+ for project in topdict[dict_key]:
+ if project == target_project:
+ parse_yaml_files(topdict[dict_key][project], build_data)
+ generate_custom_targets(project, build_data)
+ generate_custom_profile(build_data)
+ generate_mbedignore(build_data)
+ break
+ break
+ except yaml.YAMLError as ex:
+ logger.error("Found yaml parse error", ex)
+
+if __name__ == "__main__":
+ parser = argparse.ArgumentParser(description='projects.yaml file parser')
+ parser.add_argument("--projects_yaml", type=str, default='projects.yaml', help="top projects.yaml file")
+ parser.add_argument("--target_project", type=str, help="target project to be compiled")
+ args = parser.parse_args()
+
+ if not args.target_project or args.target_project is '':
+ sys.exit('Need a target project to compile DAPLink!')
+
+ generate_mbedcli_files(args.projects_yaml, args.target_project)
diff -r 000000000000 -r 01f31e923fe2 tools/mbedcli_tools/generate_mbedignore.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/mbedcli_tools/generate_mbedignore.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,70 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2018, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+import os
+
+def add_list_path(input_path_list, ouput_path_dict):
+ for path_list in input_path_list:
+ repath = os.path.normpath(path_list)
+ if os.path.isfile(repath):
+ dir_path = os.path.dirname(repath)
+ if dir_path in ouput_path_dict:
+ ouput_path_dict[dir_path].append(os.path.basename(repath))
+ else:
+ ouput_path_dict[dir_path]= [os.path.basename(repath)]
+ elif repath not in ouput_path_dict: #check if it's already in the folder filter list
+ ouput_path_dict[repath]=[]
+
+def generate_mbedignore(build_dicts, topsource = 'source', filename = '.mbedignore'):
+ sources_tag = ['sources', 'includes']
+ sources_list = []
+ src_folder_file_dict = {}
+ if 'common' in build_dicts:
+ #do sources first
+ for tag in sources_tag:
+ if tag in build_dicts['common']:
+ if type(build_dicts['common'][tag]) is dict:
+ for srd_dir in build_dicts['common'][tag]:
+ if type(build_dicts['common'][tag][srd_dir]) is list:
+ add_list_path(build_dicts['common'][tag][srd_dir], src_folder_file_dict)
+ elif type(build_dicts['common'][tag]) is list:
+ add_list_path(build_dicts['common'][tag], src_folder_file_dict)
+ ignore_list = []
+ for file in os.listdir("./"):
+ if file != topsource:
+ ignore_list.append(file)
+ for root, dirs, files in os.walk(topsource):
+ if root in src_folder_file_dict:
+ if src_folder_file_dict[root] != []:
+ for filter_file in files:
+ if filter_file not in src_folder_file_dict[root] and not filter_file.endswith('.h'):
+ ignore_list.append(os.path.join(root, filter_file))
+ continue
+ else:
+ for src_folder in src_folder_file_dict:
+ if root in src_folder:
+ for filter_file in files:
+ ignore_list.append(os.path.join(root, filter_file))
+ break
+ else:
+ ignore_list.append(root)
+ with open(filename, 'w') as ignore_file:
+ for ignore_path in ignore_list:
+ if os.path.isdir(ignore_path):
+ ignore_path = os.path.join(ignore_path, '*')
+ ignore_file.write(ignore_path+'\n')
diff -r 000000000000 -r 01f31e923fe2 tools/mbedcli_tools/mbedcli_run.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/mbedcli_tools/mbedcli_run.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,56 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2018, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+import os
+import shutil
+import subprocess
+from generate_mbedcli_files import generate_mbedcli_files
+
+def call_and_copy_output(args):
+ try:
+ process = subprocess.Popen(args, stdout=None, stderr=subprocess.STDOUT)
+ process.wait()
+ if process.returncode != 0:
+ print("Error - mbed compile!")
+ exit(process.returncode)
+ except (OSError, ValueError) as e:
+ print("Error - Cannot do mbed compile")
+ print(e.output)
+ exit(1)
+
+def mbedcli_run(daplink_dir, build_folder, project, toolchain, clean, verbosity):
+ generate_mbedcli_files(os.path.join(daplink_dir, "projects.yaml"), project)
+ project_dir=os.path.join(daplink_dir, build_folder, project.upper())
+ if clean is True and os.path.exists(project_dir):
+ print("Deleting %s" % project_dir)
+ shutil.rmtree(project_dir, ignore_errors=True)
+ args = ["mbed", "compile", "-m", project, "-t", toolchain, "--profile", "custom_profile.json"]
+ if verbosity is not None:
+ args.append("-" + "v" * verbosity)
+ call_and_copy_output(args)
+ cli_name_out = os.path.basename(daplink_dir)
+ build_dir = os.path.join(project_dir, toolchain+"-CUSTOM_PROFILE")
+ for file in os.listdir(build_dir):
+ if file.startswith(cli_name_out):
+ rename_file = os.path.join(build_dir, file.replace(cli_name_out, project, 1))
+ if os.path.exists(rename_file):
+ os.remove(rename_file)
+ os.rename(os.path.join(build_dir, file), rename_file)
+ cli_hex_output = os.path.join(build_dir, project + ".hex")
+ crc_file_output = os.path.join(build_dir, project + "_crc")
+ return (cli_hex_output,crc_file_output)
diff -r 000000000000 -r 01f31e923fe2 tools/offset_update.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/offset_update.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,61 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+from __future__ import absolute_import
+
+from builtins import bytes
+
+import argparse
+
+
+def dec_or_hex(val):
+ return int(val, 0)
+
+
+def create_padded_image(input_file, output_file, start,
+ pad_start, copy_size):
+ pad_size = start - pad_start
+ with open(input_file, 'rb') as file_handle:
+ data = file_handle.read()
+ output_data = data[0:copy_size] + bytes([0xff] * (pad_size - copy_size)) + data
+ with open(output_file, 'wb') as file_handle:
+ data = file_handle.write(output_data)
+
+
+def main():
+ parser = argparse.ArgumentParser(description='File Padder')
+ parser.add_argument("bin", type=str, default=None,
+ help="Input binary file")
+ parser.add_argument("--start", type=dec_or_hex, default=0x8000,
+ help="Starting address of input binary file")
+ parser.add_argument("--padded_start", type=dec_or_hex, default=0x5000,
+ help="Starting address after padding.")
+ parser.add_argument("--output", type=str, required=True,
+ help="Output file")
+ parser.add_argument("--copysize", type=str, default=0x40,
+ help="Size of original binary to copy")
+ args = parser.parse_args()
+
+ # Data is appened to front so padded start must be less than start
+ assert args.start > args.padded_start
+ create_padded_image(args.bin, args.output, args.start,
+ args.padded_start, args.copysize)
+
+
+if __name__ == "__main__":
+ main()
diff -r 000000000000 -r 01f31e923fe2 tools/package_release_files.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/package_release_files.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,125 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+import os
+import sys
+import shutil
+import argparse
+import yaml
+import subprocess
+
+self_path = os.path.abspath(__file__)
+tools_dir = os.path.dirname(self_path)
+daplink_dir = os.path.dirname(tools_dir)
+test_dir = os.path.join(daplink_dir, "test")
+sys.path.append(test_dir)
+
+import info
+
+from make_update_yml import DefaultList
+from make_update_yml import TargetList
+from make_update_yml import InstructionsText
+from make_update_yml import make_update_yml_file
+
+import zipfile
+
+def make_bin_zip(dir, name):
+ working_dir = os.getcwd()
+ os.chdir(dir)
+ with zipfile.ZipFile(name, mode='w') as zipf:
+ for file in os.listdir("./"):
+ if file.endswith(".bin") or file.endswith(".hex"):
+ zipf.write(os.path.join("./", file))
+ #go back
+ os.chdir(working_dir)
+
+def package_release_files(source, dest, version, toolchain):
+
+ proj_dir = source
+ output_dir = dest
+ build_number = "%04i" % version
+
+ update_yml_entries = [{'default':DefaultList([
+ ('website', 'http://os.mbed.com/platforms'),
+ ('fw_version', "'" + build_number + "'"),
+ ('image_format', '.bin'),
+ ('instructions', InstructionsText['default'])
+ ]) }]
+
+ if os.path.exists(output_dir):
+ shutil.rmtree(output_dir)
+ print (output_dir + ' existed and deleted!!')
+
+ os.mkdir(output_dir)
+
+ for prj_name, legacy, offset, extension in info.PROJECT_RELEASE_INFO:
+ legacy_str = "_legacy" if legacy else ""
+ source_offset_str = "_0x%04x" % offset if legacy else ""
+ source_name = prj_name + "_crc" + legacy_str + source_offset_str + "." + extension
+ source_dir_part = os.path.join(proj_dir, prj_name, toolchain).upper()
+ source_path = os.path.join(source_dir_part, source_name)
+ if not os.path.isfile(source_path):
+ print("Warning %s not added to release" % prj_name)
+ continue
+ items = prj_name.split('_') # "k20dx_frdmk22f_if" -> ("k20dx", "frdmk22f", "if")
+ assert items[-1] == "if", "Unexpected string: %s" % items[2]
+ host_mcu = items[0]
+ base_name = '_'.join(items[1:-1])
+ dest_offset_str = "_0x%04x" % offset
+ dest_name = build_number + "_" + host_mcu + "_" + base_name + dest_offset_str + "." + extension
+ dest_path = os.path.join(output_dir, dest_name)
+ shutil.copyfile(source_path, dest_path)
+
+ product_code = 'NOT SUPPORTED'
+ for board_id, family_id, fimware, bootloader, target in info.SUPPORTED_CONFIGURATIONS:
+ if fimware == prj_name:
+ product_code = board_id
+ if target is not None:
+ target_name = target
+ else:
+ target_name = base_name.upper()
+
+ fw_instuction = InstructionsText['default']
+ for fw_name_key in InstructionsText:
+ if fw_name_key in dest_name.lower():
+ fw_instuction = InstructionsText[fw_name_key]
+ break;
+
+ if extension == 'bin':
+ update_yml_entries.append({target_name:TargetList([
+ ('name', target_name),
+ ('product_code', "'" + format(product_code, '04x') + "'"),
+ ('fw_name', host_mcu + "_" + base_name + dest_offset_str),
+ ('instructions', fw_instuction)
+ ])});
+
+ make_bin_zip(output_dir, build_number + '_release_package_' + subprocess.check_output(['git', 'rev-parse', '--short', 'HEAD']).decode().strip() + '.zip')
+
+ make_update_yml_file(os.path.join(output_dir, 'update.yml'), update_yml_entries, explicit_start=True)
+
+if __name__ == "__main__":
+ parser = argparse.ArgumentParser(description='Package a release for distribution')
+ parser.add_argument('source', help='Release directory to grab files from')
+ parser.add_argument('dest', help='Directory to create and place files in')
+ parser.add_argument('version', type=int, help='Version number of this release')
+ parser.add_argument('--toolchain', type=str, default='', help='Toolchain directory if present')
+ args = parser.parse_args()
+
+ print("args",args.source,args.dest,args.version,args.toolchain)
+
+ package_release_files(args.source,args.dest,args.version,args.toolchain)
diff -r 000000000000 -r 01f31e923fe2 tools/post_build_script.bat --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/post_build_script.bat Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,38 @@ +:: +:: DAPLink Interface Firmware +:: Copyright (c) 2009-2016, ARM Limited, All Rights Reserved +:: SPDX-License-Identifier: Apache-2.0 +:: +:: Licensed under the Apache License, Version 2.0 (the "License"); you may +:: not use this file except in compliance with the License. +:: You may obtain a copy of the License at +:: +:: http://www.apache.org/licenses/LICENSE-2.0 +:: +:: Unless required by applicable law or agreed to in writing, software +:: distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +:: WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +:: See the License for the specific language governing permissions and +:: limitations under the License. +:: + +@set PROJECT_DIR=%1 +@set KEIL_ARM=%2 +@set TOOLS=..\..\..\tools + +@REM add fromelf to PATH +@set PATH=%KEIL_ARM%\ARMCC\bin;%path% + +@python --version 2> nul +@if %errorlevel% neq 0 echo Error: python not in PATH. If you are manually building the project, make sure to launch uVision from the python venv && exit /B %errorlevel% + +fromelf --bin %PROJECT_DIR%.axf -o %PROJECT_DIR%.bin +@if %errorlevel% neq 0 exit /b %errorlevel% + +fromelf --i32 %PROJECT_DIR%.axf -o %PROJECT_DIR%.hex +@if %errorlevel% neq 0 exit /b %errorlevel% + +python %TOOLS%\post_build_script.py %PROJECT_DIR%.hex %PROJECT_DIR%_crc +@if %errorlevel% neq 0 exit /b %errorlevel% + +@exit 0
diff -r 000000000000 -r 01f31e923fe2 tools/post_build_script.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/post_build_script.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,264 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+from __future__ import absolute_import
+from __future__ import print_function
+
+import argparse
+import itertools
+import binascii
+import struct
+import intelhex
+import offset_update
+from os.path import dirname, join
+from flash_algo import PackFlashAlgo
+
+VECTOR_FMT = "<7I"
+CHECKSUM_FMT = "<1I"
+CHECKSUM_OFFSET = 0x1C
+TARGET_INFO_OFFSET = 13*4
+ALIGN_PADS = 4
+
+def ranges(i):
+ for _, b in itertools.groupby(enumerate(i), lambda x_y: x_y[1] - x_y[0]):
+ b = list(b)
+ yield b[0][1], b[-1][1]
+
+def post_build_script(input_file, output_file, board_id=None, family_id=None, bin_offset=None, flash_algo_file=None, target_ram_start=None, target_ram_end=None, flash_blob_entry="0x20000000"):
+ output_format_file = '-'.join(filter(None, (output_file, board_id, family_id, bin_offset)))
+ print(output_format_file)
+ output_file_hex = output_format_file + ".hex"
+ output_file_binary = output_format_file + ".bin"
+ output_file_txt = output_format_file + ".txt"
+ output_file_c = output_format_file + ".c"
+ output_file_c_generic = join(dirname(output_file), "bootloader_image.c")
+ output_file_legacy = output_format_file + "_legacy_0x8000.bin"
+ output_file_legacy_5000 = output_format_file + "_legacy_0x5000.bin"
+ output_file_legacy_txt = output_format_file + "_legacy.txt"
+
+ # Read in hex file
+ new_hex_file = intelhex.IntelHex()
+ new_hex_file.padding = 0xFF
+
+ if input_file.lower().endswith('.bin'):
+ if bin_offset is not None:
+ new_hex_file.loadbin(input_file, offset=int(bin_offset, 16))
+ else:
+ new_hex_file.loadbin(input_file)
+ else: #always assume hex format
+ new_hex_file.fromfile(input_file, format='hex')
+
+
+ # Get the starting and ending address
+ addresses = new_hex_file.addresses()
+ addresses.sort()
+ start_end_pairs = list(ranges(addresses))
+ regions = len(start_end_pairs)
+ assert regions == 1, ("Error - only 1 region allowed in "
+ "hex file %i found." % regions)
+ start, end = start_end_pairs[0]
+
+ pack_flash_algo = None
+ if flash_algo_file is not None:
+ with open(flash_algo_file, "rb") as file_handle:
+ pack_flash_algo = PackFlashAlgo(file_handle.read())
+
+ # Checksum the vector table
+ #
+ # Note this is only required for NXP devices but
+ # it doesn't hurt to checksum all builds
+
+ # Compute a checksum on the first 7 vector nvic vectors
+ vector_size = struct.calcsize(VECTOR_FMT)
+ vector_data = new_hex_file.tobinarray(start=start, size=vector_size)
+ vectors = struct.unpack(VECTOR_FMT, vector_data)
+ assert len(vectors) == 7, "Incorrect size of %i" % len(vectors)
+ checksum = 0
+ for vector in vectors:
+ checksum += vector
+ checksum = (~checksum + 1) & 0xFFFFFFFF # Two's compliment
+ # Write checksum back to hex
+ csum_start = CHECKSUM_OFFSET + start
+ csum_data = struct.pack(CHECKSUM_FMT, checksum)
+ assert len(csum_data) == 4
+ new_hex_file.puts(csum_start, csum_data)
+
+ print("board_id", board_id)
+ print("family_id", family_id)
+ print("bin_offset", bin_offset)
+ if board_id is not None or family_id is not None:
+ target_info_addr = new_hex_file.gets(start + TARGET_INFO_OFFSET, 4)
+ target_addr_unpack = struct.unpack("<1I",target_info_addr)[0]
+ print("board_info offset: ",hex(target_addr_unpack - start))
+ #family_id is in integer hex
+ if family_id is not None:
+ new_hex_file.puts(target_addr_unpack + 2,struct.pack('<1H',int(family_id, 16)))
+ #board_id is in string hex
+ if board_id is not None:
+ new_hex_file.puts(target_addr_unpack + 4,struct.pack('4s',"%.04X" % int(board_id, 16)))
+ if pack_flash_algo is not None:
+ blob_header = (0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2)
+ stack_size = 0x200
+ region_info_fmt = '5I'
+ region_info_total = 10
+ target_cfg_fmt = '3I'+ region_info_fmt*region_info_total*2 + 'IHBB'
+ sector_info_fmt = '2I'
+ sector_info_len = len(pack_flash_algo.sector_sizes)
+ program_target_fmt = '14I'
+ flash_blob_entry = int(flash_blob_entry, 16)
+ blob_pad_size = ((len(pack_flash_algo.algo_data) + ALIGN_PADS -1) // ALIGN_PADS * ALIGN_PADS) - len(pack_flash_algo.algo_data)
+ blob_header_size = len(blob_header) * 4
+ total_struct_size = blob_header_size + len(pack_flash_algo.algo_data) + blob_pad_size + sector_info_len*struct.calcsize(sector_info_fmt) + struct.calcsize(program_target_fmt) + struct.calcsize(target_cfg_fmt)
+ flash_blob_addr = end + 1 - 4 - total_struct_size #make room for crc
+ print("flash_blob offset:", hex(flash_blob_addr - start))
+ new_hex_file.puts(flash_blob_addr, struct.pack('<'+'I'*len(blob_header), *blob_header))
+ new_hex_file.puts(flash_blob_addr + blob_header_size, pack_flash_algo.algo_data + "\x00" * blob_pad_size)
+ sector_info_addr = flash_blob_addr+blob_header_size + len(pack_flash_algo.algo_data) + blob_pad_size
+ sector_info_arr = []
+ for flash_start, flash_size in pack_flash_algo.sector_sizes:
+ sector_info_arr.append(flash_start + pack_flash_algo.flash_start)
+ sector_info_arr.append(flash_size)
+ print("sector_info offset:", hex(sector_info_addr - start))
+ new_hex_file.puts(sector_info_addr,struct.pack('<' + 'I'*len(sector_info_arr), *sector_info_arr))
+ program_target_addr = sector_info_addr + len(sector_info_arr)*4
+ stack_pointer = (flash_blob_entry + blob_header_size + pack_flash_algo.rw_start + pack_flash_algo.rw_size + stack_size + 0x100 - 1) // 0x100 * 0x100
+ print("program_target offset:", hex(program_target_addr - start))
+ new_hex_file.puts(program_target_addr,struct.pack('<' + program_target_fmt,
+ pack_flash_algo.symbols['Init'] + blob_header_size + flash_blob_entry,
+ pack_flash_algo.symbols['UnInit'] + blob_header_size + flash_blob_entry,
+ pack_flash_algo.symbols['EraseChip'] + blob_header_size + flash_blob_entry if pack_flash_algo.symbols['EraseChip'] != 0xffffffff else 0,
+ pack_flash_algo.symbols['EraseSector'] + blob_header_size + flash_blob_entry,
+ pack_flash_algo.symbols['ProgramPage'] + blob_header_size + flash_blob_entry,
+ pack_flash_algo.symbols['Verify'] + blob_header_size + flash_blob_entry if pack_flash_algo.symbols['Verify'] != 0xffffffff else 0,
+ flash_blob_entry + 1, #BKPT : start of blob + 1
+ flash_blob_entry + blob_header_size + pack_flash_algo.rw_start, #RSB : blob start + header + rw data offset
+ stack_pointer, #RSP : stack pointer
+ flash_blob_entry + 0x00000A00, #mem buffer location
+ flash_blob_entry, #location to write prog_blob in target RAM
+ blob_header_size + len(pack_flash_algo.algo_data) + blob_pad_size, #prog_blob size
+ flash_blob_addr, #address of prog_blob
+ pack_flash_algo.page_size #ram_to_flash_bytes_to_be_written
+ ))
+ target_cfg_addr = program_target_addr + struct.calcsize(program_target_fmt)
+ print("target_cfg offset:", hex(target_cfg_addr - start))
+ if target_ram_start is None or target_ram_end is None:
+ raise Exception("target_ram_start and target_ram_end should be defined!")
+ first_flash_region = (pack_flash_algo.flash_start, pack_flash_algo.flash_start + pack_flash_algo.flash_size, 1, 0, program_target_addr)
+ first_ram_region = (int(target_ram_start, 16), int(target_ram_end, 16), 0, 0, 0)
+ emypty_region = (0, 0, 0, 0, 0) * (region_info_total -1)
+ all_regions = first_flash_region + emypty_region + first_ram_region + emypty_region
+ target_flags = ( 0, 0, 0, 0) #realtime board ID, family ID and erase reset flag
+ regions_flags = all_regions + target_flags
+ new_hex_file.puts(target_cfg_addr, struct.pack('<' + target_cfg_fmt,
+ 0x1, #script generated
+ sector_info_addr, # Sector start and length list
+ sector_info_len, #Sector start and length list total
+ *regions_flags
+ ))
+ board_info_flag = 1 if pack_flash_algo.symbols['EraseSector'] != 0xffffffff else 0 #kEnablePageErase
+ new_hex_file.puts(target_addr_unpack + 12,struct.pack('<1I', board_info_flag)) #always enable page erase EraseSector is a required symbol in flash algo
+ new_hex_file.puts(target_addr_unpack + 16,struct.pack('<1I', target_cfg_addr))
+
+ # CRC the entire image
+ #
+ # This is required for all builds
+
+ # Compute checksum over the range (don't include data at location of crc)
+ size = end - start + 1
+ crc_size = size - 4
+ data = new_hex_file.tobinarray(start=start, size=crc_size)
+ crc32 = binascii.crc32(data) & 0xFFFFFFFF
+
+ # Write CRC to the file in little endian
+ new_hex_file[end - 3] = (crc32 >> 0) & 0xFF
+ new_hex_file[end - 2] = (crc32 >> 8) & 0xFF
+ new_hex_file[end - 1] = (crc32 >> 16) & 0xFF
+ new_hex_file[end - 0] = (crc32 >> 24) & 0xFF
+
+ # Write out file(s)
+ new_hex_file.tofile(output_file_hex, 'hex')
+ new_hex_file.tofile(output_file_binary, 'bin')
+ with open(output_file_txt, 'w') as file_handle:
+ file_handle.write("0x%08x\r\n" % crc32)
+
+ # Write out data as a C array
+ data = new_hex_file.tobinarray(start=start, size=size)
+ data = list(bytearray(data))
+ output_data = ('static const unsigned int image_start = 0x%08x;\n'
+ 'static const unsigned int image_size = 0x%08x;\n'
+ 'static const char image_data[0x%08x] = {\n ' %
+ (start, size, size))
+ for i, byte_val in enumerate(data):
+ output_data += '0x%02x' % byte_val + ', '
+ if ((i + 1) % 0x20) == 0:
+ output_data += '\n '
+ output_data += '};\n'
+ with open(output_file_c, 'w') as file_handle:
+ file_handle.write(output_data)
+ with open(output_file_c_generic, 'w') as file_handle:
+ file_handle.write(output_data)
+
+ # Print info on operation
+ print("Start 0x%x, Length 0x%x, CRC32 0x%08x" % (start, size, crc32))
+
+ if start == 0x8000 or start == 0x10000 or start == 0x88000 or start == 0x0800C000:
+ if start == 0x0800C000:
+ # Adjust for ST-Link
+ pad_addr = start - 0x8000
+ else:
+ pad_addr = start - 0x3000
+ legacy_zero = start + 7 * 4
+ legacy_size = 4 * 4
+ legacy_hex_file = intelhex.IntelHex(new_hex_file)
+ for addr in range(legacy_zero, legacy_zero + legacy_size):
+ legacy_hex_file[addr] = 0
+ data = legacy_hex_file.tobinarray(start=start, size=crc_size)
+ crc32 = binascii.crc32(data) & 0xFFFFFFFF
+ # Write CRC to the file in little endian
+ legacy_hex_file[end - 3] = (crc32 >> 0) & 0xFF
+ legacy_hex_file[end - 2] = (crc32 >> 8) & 0xFF
+ legacy_hex_file[end - 1] = (crc32 >> 16) & 0xFF
+ legacy_hex_file[end - 0] = (crc32 >> 24) & 0xFF
+ legacy_hex_file.tofile(output_file_legacy, 'bin')
+ with open(output_file_legacy_txt, 'w') as file_handle:
+ file_handle.write("0x%08x\r\n" % crc32)
+ offset_update.create_padded_image(output_file_legacy,
+ output_file_legacy_5000,
+ start, pad_addr, 0x40)
+
+if __name__ == '__main__':
+ parser = argparse.ArgumentParser(description='Post build tool for Board ID, Family ID, Target flash algo and CRC generation')
+ parser.add_argument("input", type=str, help="Hex or bin file to read from.")
+ parser.add_argument("output", type=str,
+ help="Output base file name to write crc, board_id and family_id.")
+ parser.add_argument("--board-id", type=str,
+ help="board id to for the target in hex")
+ parser.add_argument("--family-id", type=str,
+ help="family id to for the target in hex")
+ parser.add_argument("--bin-offset", type=str,
+ help="binary offset in hex can be supplied if input is bin")
+ parser.add_argument("--flash-algo-file", type=str,
+ help="Elf, axf, or flm to extract flash algo from")
+ parser.add_argument("--target-ram-start", type=str,
+ help="Lowest address of target RAM for flash algo in hex")
+ parser.add_argument("--target-ram-end", type=str,
+ help="Highest address of target RAM for flash algo in hex")
+ parser.add_argument("--flash-blob-entry", type=str, default="0x20000000",
+ help="Entry point of flash algo in the target")
+ args = parser.parse_args()
+ post_build_script(args.input, args.output, args.board_id, args.family_id, args.bin_offset, args.flash_algo_file, args.target_ram_start, args.target_ram_end, args.flash_blob_entry)
diff -r 000000000000 -r 01f31e923fe2 tools/post_build_script.sh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/post_build_script.sh Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,29 @@
+#!/bin/bash -e
+##
+## DAPLink Interface Firmware
+## Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+## SPDX-License-Identifier: Apache-2.0
+##
+## Licensed under the Apache License, Version 2.0 (the "License"); you may
+## not use this file except in compliance with the License.
+## You may obtain a copy of the License at
+##
+## http://www.apache.org/licenses/LICENSE-2.0
+##
+## Unless required by applicable law or agreed to in writing, software
+## distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+## WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+## See the License for the specific language governing permissions and
+## limitations under the License.
+##
+
+export PROJECT_DIR=build
+export TOOLS=../../../tools
+
+python --version 2> /dev/null
+
+fromelf --bin $PROJECT_DIR/*.axf -o $PROJECT_DIR/firmware.bin
+
+fromelf --i32 $PROJECT_DIR/*.axf -o $PROJECT_DIR/firmware.hex
+
+python ${TOOLS}/post_compute_crc.py ${PROJECT_DIR}/firmware.hex ${PROJECT_DIR}/firmware_crc
diff -r 000000000000 -r 01f31e923fe2 tools/pre_build_script.bat --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/pre_build_script.bat Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,37 @@ +:: +:: DAPLink Interface Firmware +:: Copyright (c) 2009-2016, ARM Limited, All Rights Reserved +:: SPDX-License-Identifier: Apache-2.0 +:: +:: Licensed under the Apache License, Version 2.0 (the "License"); you may +:: not use this file except in compliance with the License. +:: You may obtain a copy of the License at +:: +:: http://www.apache.org/licenses/LICENSE-2.0 +:: +:: Unless required by applicable law or agreed to in writing, software +:: distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +:: WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +:: See the License for the specific language governing permissions and +:: limitations under the License. +:: + +@set TOOLS=..\..\..\tools +@set DIR=..\..\..\source\daplink + +@python --version 2> nul +@if %errorlevel% neq 0 goto nopython + +@REM Run python script to create or update version_git.h +python %TOOLS%\pre_build_script.py +@if %errorlevel% neq 0 exit /B %errorlevel% + +@exit /B 0 + +:nopython +echo Error: python not in PATH. If you are manually building the project, make sure to launch uVision from the python venv +@REM Create default version_git.h. This is so the project +@REM builds if python is not installed +copy %DIR%\version_git_tmpl.txt %DIR%\version_git.h +exit /B %errorlevel% +
diff -r 000000000000 -r 01f31e923fe2 tools/pre_build_script.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/pre_build_script.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,106 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+from __future__ import absolute_import
+from __future__ import print_function
+
+import sys
+import os
+import argparse
+from subprocess import check_output, CalledProcessError
+
+VERSION_GIT_FILE_TEMPLATE = """
+/**
+ * @file version_git.h
+ * @brief GIT version info
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef VERSION_GIT_H
+#define VERSION_GIT_H
+
+#define GIT_COMMIT_SHA \"%s\"
+#define GIT_LOCAL_MODS %d
+
+#endif
+
+"""
+
+
+
+def generate_version_file(version_git_dir):
+
+ output_file = os.path.join(os.path.normpath(version_git_dir),'version_git.h')
+ print("#> Pre-build script start")
+
+ # Get the git SHA.
+ print("#> Getting git SHA")
+ try:
+ git_sha = check_output("git rev-parse --verify HEAD", shell=True)
+ git_sha = git_sha.decode().strip()
+ except:
+ print("#> ERROR: Failed to get git SHA, do you have git.exe in your PATH environment variable?")
+ return 1
+
+ # Check are there any local, uncommitted modifications.
+ print("#> Checking for local changes")
+ try:
+ check_output("git diff --no-ext-diff --quiet --exit-code", shell=True)
+ except (CalledProcessError, OSError):
+ git_has_changes = 1
+ else:
+ git_has_changes = 0
+
+
+ # Create the version file. Only overwrite an existing file if it changes.
+ version_text = VERSION_GIT_FILE_TEMPLATE % (git_sha, git_has_changes)
+ try:
+ with open(output_file, 'r') as version_file:
+ current_version_text = version_file.read()
+ except IOError:
+ current_version_text = ''
+ if version_text != current_version_text:
+ print("#> Writing git version file")
+ with open(output_file, 'w+') as version_file:
+ version_file.write(version_text)
+ else:
+ print("#> Keeping git version file since it didn't need to change")
+
+ print("#> Pre-build script completed written %s" % output_file )
+
+ return 0
+
+if __name__ == "__main__":
+ parser = argparse.ArgumentParser(description='git version generator')
+ parser.add_argument("--version_git_dir", type=str, default='../../../source/daplink/', help="directory to output version_git.h file")
+ args = parser.parse_args()
+ exit(generate_version_file(args.version_git_dir))
diff -r 000000000000 -r 01f31e923fe2 tools/pre_build_script.sh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/pre_build_script.sh Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,27 @@
+#!/bin/bash -e
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+export TOOLS=../../../tools
+export DIR=../../../source/daplink
+# Create dsion_git_tmpl.txt ${DIR}\version_git.h
+
+python --version 2> nul
+
+# Run python script to delete default version_git.h and create the real one
+python ${TOOLS}/pre_build_script.py
diff -r 000000000000 -r 01f31e923fe2 tools/test_loop.sh --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/test_loop.sh Tue Apr 07 12:55:42 2020 +0200 @@ -0,0 +1,27 @@ +#!/bin/sh +# Local tests looper until fail. CeDeROM 20170815 +# Runs all tests on all supported Boards/Targets on provided environment. +LOGDIR=../test/out/ +TGTDIR=../bin/target + +echo "ARE WE INSIDE VALID VIRTUALENV READY FOR TESTING?" +echo "LOGDIR: $LOGDIR" +echo "TGTDIR: $TGTDIR" +echo "Press Ctrl+C to Abort, Return to Start.." +read + +while [ 1 ]; do + TIME=`date +%s` + SAY_ITERATION="STARTING DAPLINK TEST ITERATION $TIME" + echo $SAY_ITERATION + if say "" ; then say "$SAY_ITERATION" ; fi + python ../test/run_test.py --targetdir $TGTDIR --testdl --loadbl --verbose All --logdir "$LOGDIR"/$TIME + RES=$? + if [ $RES -ne 0 ]; then + SAY_ERROR="DAPLINK TESTING ERROR, TEST $TIME FAILED MISERABLY WITH STATUS $RES, EJECTING!" + echo "$SAY_ERROR" + if say "" ; then say -v "bad news" "$SAY_ERROR" ; fi + if [ -f "$LOGDIR"/summary.txt ]; then cat "$LOGDIR"/summary.txt; fi + break + fi +done
diff -r 000000000000 -r 01f31e923fe2 tools/update_yml.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tools/update_yml.py Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,92 @@
+#
+# DAPLink Interface Firmware
+# Copyright (c) 2009-2018, ARM Limited, All Rights Reserved
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+import yaml
+
+#classes needed to generate update.yml files
+class TargetList(list):
+ def sort(self, *args, **kwargs):
+ pass
+
+class InstructionList(unicode):
+ def sort(self, *args, **kwargs):
+ pass
+
+#Remove the sorting by default
+yaml.add_representer(TargetList, yaml.representer.SafeRepresenter.represent_dict)
+#needed block style for the instruction steps
+yaml.add_representer(InstructionList, lambda dumper, data: dumper.represent_scalar(u'tag:yaml.org,2002:str', data, style='|') )
+
+
+#instruction steps for firmware
+InstructionsText = {
+ 'default':TargetList([
+ ('windows', InstructionList(
+ '1. Download the firmware file.\n'
+ '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate and mount as `BOOTLOADER` or `MAINTENANCE`. For boards that enumerate as `BOOTLOADER` [see our blog to determine if an update for the DAPLink bootloader is available.](https://os.mbed.com/blog/entry/DAPLink-bootloader-update/)\n'
+ '3. Drag-and-drop the firmware file onto the mounted drive.\n'
+ '4. Wait for the file copy operation to complete.\n'
+ '5. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.\n'
+ )),
+ ('osx', InstructionList(
+ '1. Download the firmware file.\n'
+ '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate as `BOOTLOADER` or `MAINTENANCE`. For boards that enumerate as `BOOTLOADER` [see our blog to determine if an update for the DAPLink bootloader is available.](https://os.mbed.com/blog/entry/DAPLink-bootloader-update/)\n'
+ '3. In a terminal execute\n'
+ ' - `sudo mount -u -w -o sync /Volumes/MAINTENANCE ; cp -X <path to firmware file> /Volumes/MAINTENANCE/`\n'
+ ' - Note: If your drive does not mount as `MAINTENANCE` make sure to change this to match the name of the mounted disk attached to your system.\n'
+ '4. Wait for the file copy operation to complete.\n'
+ '5. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.\n'
+ )),
+ ('linux', InstructionList(
+ '1. Download the firmware file.\n'
+ '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate as `BOOTLOADER` or `MAINTENANCE`. For boards that enumerate as `BOOTLOADER` [see our blog to determine if an update for the DAPLink bootloader is available.](https://os.mbed.com/blog/entry/DAPLink-bootloader-update/)\n'
+ '3. In a terminal execute\n'
+ ' - `cp <path to firmware file> <MAINTENANCE> && sync`\n'
+ ' - Note: make sure to change `MAINTENANCE` to the name of the mount point of the drive on your system.\n'
+ '4. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.\n'
+ ))
+ ]),
+ 'lpc11u35':TargetList([
+ ('windows', InstructionList(
+ '1. Download the firmware file.\n'
+ '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate and mount as `CRP DISABLD`\n'
+ '3. Delete the file named `firmware.bin`\n'
+ '4. Wait for the file copy operation to complete.\n'
+ '5. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.\n'
+ )),
+ ('osx', InstructionList(
+ '1. Download the firmware file.\n'
+ '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate and mount as `CRP DISABLD`\n'
+ '3. Delete the file named `firmware.bin`'
+ '4. In a terminal execute\n'
+ ' - `sudo mount -u -w -o sync /Volumes/CRP\ DISABLD ; rm /Volumes/CRP\ DISABLD/firmware.bin && cp -X <path to firmware file> /Volumes/CRP\ DISABLD/`\n'
+ '5. Wait for the file copy operation to complete.\n'
+ '6. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.\n'
+ )),
+ ('linux', InstructionList(
+ '1. Download the firmware file.\n'
+ '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate and mount as `CRP DISABLD`\n'
+ '3. Delete the file named `firmware.bin`\n'
+ '4. In a terminal execute\n'
+ ' - `cp <path to firmware file> <CRP DISABLD> && sync`\n'
+ ' - Note: make sure to change `CRP DISABLD` to the name of the mount point on your system.\n'
+ '5. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.\n'
+ ))
+ ])
+
+}